APB1 bus speed wrong when set to 72Mhz SYSCLK

[etrombly]

The documentation says the low speed bus, APB1 should not go above 36Mhz. So when selecting 72Mhz SYSCLK the ppre1 register is set to 0x4 (divide HCLK by 2). When using 36Mhz to calculate the timer delay for 1 second the led blinks at half second intervals.

[etrombly]

From page 93 of the RM0008 manual:

The timer clock frequencies are automatically fixed by hardware. There are two cases:

1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected.
2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected.