VHDL backend support for arbitrary function orders in where clauses

[HWoidt]

Issue by HWoidt
Saturday Jul 11, 2015 at 13:07 GMT
Originally opened as https://gits-15.sys.kth.se/ingo/forsyde-deep/issues/20

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Reported by shani...@gmail.com, Jan 19, 2010

To reproduce the problem:

1. Define a process function which has included functions inside a where
   clause.
2. Generate the VHDL code and try to simulate/synthesize the output.

The VHDL backend generates the output sub-functions in the VHDL code in the
same order as were defined in the design. This may result to using a
function in the VHDL code before defining it.
As a workaround, the designer could define the functions in the
define-then-use order which is not a common practice in functional programming.