multidimentional fixed size vector error in modelsim simulation on generated vhdl code

[fuzhouxiang]

Hi. I find there is also something wrong with multi-dimensional fixed size vector. The simulation in forsyde deep is fine, but the generated VHDL code cannot be simulated.

My code is:

{-# LANGUAGE TemplateHaskell #-}
module Take where
import ForSyDe.Deep 
import Data.Int
import Data.TypeLevel
import Data.Param.FSVec

takeProcFun :: ProcFun(FSVec D2 (FSVec D2 Int32) -> FSVec D2 (FSVec D2 Int32))
takeProcFun = $(newProcFun
    [d| takeProcFun :: FSVec D2 (FSVec D2 Int32) -> FSVec D2 (FSVec D2 Int32) 
        takeProcFun x = x
    |])

takeProc :: Signal (FSVec D2 (FSVec D2 Int32)) -> Signal (FSVec D2 (FSVec D2 Int32)) 
takeProc = mapSY "proc1" takeProcFun

takeSysDef :: SysDef(Signal (FSVec D2 (FSVec D2 Int32)) -> Signal (FSVec D2 (FSVec D2 Int32)))
takeSysDef = newSysDef takeProc "mingzi" ["in"] ["out"]

x1 = (1 :: Int32) +> (2 :: Int32) +> empty
x2 = (4 :: Int32) +> (5 :: Int32) +> empty

y1 = x1 +> x2 +> empty

The simulation result in forsyde deep is:

simulate takeSysDef [y1]
[<<1,2>,<4,5>>]

But error happens in modelsim simulation:

writeAndModelsimVHDL Nothing takeSysDef [y1]
Running: vmap forsyde /home/embedded/Downloads/deep/.stack-work/install/x86_64-linux-tinfo6/41f3446f00eaf30900387f62586718ab816bbd89d646a1e0d09fd9d4762383ee/8.0.2/share/x86_64-linux-ghc-8.0.2/forsyde-deep-0.2.0/lib/modelsim
Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
vmap forsyde /home/embedded/Downloads/deep/.stack-work/install/x86_64-linux-tinfo6/41f3446f00eaf30900387f62586718ab816bbd89d646a1e0d09fd9d4762383ee/8.0.2/share/x86_64-linux-ghc-8.0.2/forsyde-deep-0.2.0/lib/modelsim 
Modifying modelsim.ini
Running: vlib mingzi_lib/modelsim
** Warning: (vlib-34) Library already exists at "mingzi_lib/modelsim".
Running: vcom -93 -quiet -nologo -work mingzi_lib/modelsim mingzi_lib/mingzi_lib.vhd
** Error: mingzi_lib/mingzi_lib.vhd(13): (vcom-1136) Unknown identifier "fsvec_2_int32".
** Note: mingzi_lib/mingzi_lib.vhd(187): VHDL Compiler exiting
*** Exception: VHDL Compilation Error: Modelsim failed
in system definition `mingzi' (created in <unkown>)
CallStack (from HasCallStack):
  error, called at src/ForSyDe/Deep/ForSyDeErr.hs:461:18 in forsyde-deep-0.2.0-7deUbX6BizeCKOZ9sbSqT7:ForSyDe.Deep.ForSyDeErr
*Take> writeVHDL takeSysDef
*Take> writeAndModelsimVHDL Nothing takeSysDef [y1]
Running: vmap forsyde /home/embedded/Downloads/deep/.stack-work/install/x86_64-linux-tinfo6/41f3446f00eaf30900387f62586718ab816bbd89d646a1e0d09fd9d4762383ee/8.0.2/share/x86_64-linux-ghc-8.0.2/forsyde-deep-0.2.0/lib/modelsim
Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020
vmap forsyde /home/embedded/Downloads/deep/.stack-work/install/x86_64-linux-tinfo6/41f3446f00eaf30900387f62586718ab816bbd89d646a1e0d09fd9d4762383ee/8.0.2/share/x86_64-linux-ghc-8.0.2/forsyde-deep-0.2.0/lib/modelsim 
Copying /home/embedded/intelFPGA/20.1/modelsim_ase/linuxaloem/../modelsim.ini to modelsim.ini
Modifying modelsim.ini
Running: vlib mingzi_lib/modelsim
Running: vcom -93 -quiet -nologo -work mingzi_lib/modelsim mingzi_lib/mingzi_lib.vhd
** Error: mingzi_lib/mingzi_lib.vhd(13): (vcom-1136) Unknown identifier "fsvec_2_int32".
** Note: mingzi_lib/mingzi_lib.vhd(187): VHDL Compiler exiting
*** Exception: VHDL Compilation Error: Modelsim failed
in system definition `mingzi' (created in <unkown>)
CallStack (from HasCallStack):
  error, called at src/ForSyDe/Deep/ForSyDeErr.hs:461:18 in forsyde-deep-0.2.0-7deUbX6BizeCKOZ9sbSqT7:ForSyDe.Deep.ForSyDeErr

[fuzhouxiang]

This can be solved by changing the order of type and subtype in generated library.
The original generated package looks like this:

 type fsvec_int32 is array (fsvec_index range <>) of int32;
 
 type fsvec_fsvec_2_int32 is array (fsvec_index range <>) of fsvec_2_int32;
 
 subtype fsvec_2_int32 is fsvec_int32 (0 to 1);
 
 subtype fsvec_2_fsvec_2_int32 is fsvec_fsvec_2_int32 (0 to 1);

To make it able to compile, we should reorder it to:

 type fsvec_int32 is array (fsvec_index range <>) of int32;
 
 subtype fsvec_2_int32 is fsvec_int32 (0 to 1);
 
 type fsvec_fsvec_2_int32 is array (fsvec_index range <>) of fsvec_2_int32;
      
 subtype fsvec_2_fsvec_2_int32 is fsvec_fsvec_2_int32 (0 to 1);