I am looking to setup the RISCV vector processor with multiple memory banks, like the TCDM, and with multiple data-consumer ports, the default 4 VLSU's already defined in the Spatz-core. However I ran into the following:
|
int err = this->io_itf[0].req(req); |
Why is only 1 out of 4 VLSU ports used?
Kind regards,
Geerten
I am looking to setup the RISCV vector processor with multiple memory banks, like the TCDM, and with multiple data-consumer ports, the default 4 VLSU's already defined in the Spatz-core. However I ran into the following:
gvsoc-core/models/cpu/iss/include/isa_lib/vint.h
Line 5603 in 0b182b3
Why is only 1 out of 4 VLSU ports used?
Kind regards,
Geerten