AES-128 Verilog Implementation

A complete Verilog implementation of AES-128 encryption, designed for FPGA deployment with UART interface support. This project provides both core AES encryption modules and board-specific implementations.

Authors: Charles Brammell and Joshua Chen

Quick Start

For AES Encryption

AES128_Encryptor aes_inst (
    .clk(clk),
    .rst(rst),
    .start(start),
    .plaintext(plaintext),    // 128-bit input
    .key_in(key),             // 128-bit key
    .ciphertext(ciphertext),  // 128-bit output
    .done(done)               // encryption complete
);

Project Structure

• RTL.md - Detailed module reference and architecture
• VERIFICATION.md - Testing and verification guide
• IMPLEMENTATION.md - Nexys A7 board setup and UART communication

rtl/
├── core/          # AES building blocks
├── uart/          # UART communication
└── top/           # User interfaces

verification/     # Python test scripts
testbench/        # Verilog testbenches
constraints/      # FPGA pin constraints
AES_Project_Final/ # Vivado project (do not modify)