agp.h

/*
 * AGPGART module version 2.0
 * Copyright (C) 2003 Tungsten Graphics
 * Copyright (C) 2003 Jeff Hartmann
 * Copyright (C) 1999 Precision Insight, Inc.
 * Copyright (C) 1999 Xi Graphics, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, 
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE 
 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _AGP_BACKEND_PRIV_H
#define _AGP_BACKEND_PRIV_H 1

extern struct list_head agp_info_list;
extern struct agp_bridge_data **agp_contexts;
extern struct agp_bridge_data *agp_bridge;
extern int agp_num_contexts;
extern int agp_memory_reserved;
extern __u32 *agp_gatt_table;
extern int agp_try_unsupported __initdata;

#define AGP_GET_CONTEXT_CHECK(x)	(agp_get_context_check(x))
#define AGP_GET_CONTEXT(x)		(agp_contexts[x])

void global_cache_flush(void);
void global_tlb_flush(void);

/* Device probing routines */
int __init agp_find_supported_device(void);
void agp_store_driver_name(const char *vendor, const char *chipset);


enum aper_size_type {
	U8_APER_SIZE,
	U16_APER_SIZE,
	U32_APER_SIZE,
	LVL2_APER_SIZE,
	FIXED_APER_SIZE
};

typedef struct _aper_size_info_8 {
	int size;
	int num_entries;
	int page_order;
	u8 size_value;
} aper_size_info_8;

typedef struct _aper_size_info_16 {
	int size;
	int num_entries;
	int page_order;
	u16 size_value;
} aper_size_info_16;

typedef struct _aper_size_info_32 {
	int size;
	int num_entries;
	int page_order;
	u32 size_value;
} aper_size_info_32;

typedef struct _aper_size_info_lvl2 {
	int size;
	int num_entries;
	u32 size_value;
} aper_size_info_lvl2;

typedef struct _aper_size_info_fixed {
	int size;
	int num_entries;
	int page_order;
} aper_size_info_fixed;

typedef struct agp_bridge_data {
	/* The pci device for the first agp host bridge. */
	struct pci_dev *dev;

	/* Agp information about this bridge and its masters */
	agp_extended_info *info;
	int ctx_idx;
	char *driver_name;

	/* Spinlock for list access. */
	spinlock_t list_lock;
	/* All agp_memory currently in the system */
	struct list_head memory_list;
	/* All agp_memory currently bound into the aperture */
	struct list_head bound_list;

	/* pointer to any device specific data which drivers might need. */
	void *dev_private_data;

	/* Some general agpgart module stuff.  Note that the version here
	 * must stay constant for now because of a mistake in the agpgart
	 * support code in the Xserver.  Thats okay though since we
	 * added another query mechanism when agp 3.0 support was added.
	 * consider changing this version only if you break compatibility.
	 */
	agp_version *version;
	int max_memory_agp;			/* in number of pages */
	atomic_t current_memory_agp;
	atomic_t agp_in_use;

	/* Some agp registers on the first host bridge we abuse. */
	u32 mode;
	int capndx;

	/* Chipset information */
	enum chipset_type type;
	enum aper_size_type size_type;
	void *aperture_sizes;
	void *previous_size;
	void *current_size;
	int aperture_size_idx;
	int num_aperture_sizes;

	/* Some information about the gatt table bits we add to each
	 * type of agp memory.
	 */
	u8 gatt_mask;
	int gatt_mask_shift;

	/* Information related to the actual gatt table */
	struct page *gatt;
	struct page *scratch_page;
	/* Will probably be removed before I ship.  Legacy driver support
	 * atm.
	 */
	unsigned long scratch_page_addr;
	unsigned long scratch_page_entry;

	u32 *gatt_table;
	unsigned long gart_bus_addr;
	unsigned long gatt_bus_addr;

	/* a pointer to the key list bit vector */
	unsigned long *key_list;

	/* Flags: could be combined into a bit field
	 * leave that for another day.
	 */
	int needs_scratch_page;
	int cant_use_aperture;
	int fast_unbound_access;
	int has_cache_coherent;
	int using_64b_gatt;
	int keep_pages;

	/* agp and system page information */
	unsigned long alloc_page_mask;
	unsigned long agp_page_mask;
	int alloc_page_shift;
	int agp_page_shift;

	/* Protection bits for vma's */
	pgprot_t default_prot;
	pgprot_t cached_prot;

	pgprot_t user_mask;
	pgprot_t default_bits;
	pgprot_t cached_bits;
   
	/* Links to driver specific functions */

	int (*fetch_size)(void);
	int (*configure)(void);
	void (*agp_enable)(u32);
	void (*cleanup)(void);
	void (*tlb_flush)(agp_memory *);
	void (*tlb_enable)(void);
	void (*tlb_disable)(void);
	unsigned long (*mask_memory)(unsigned long, int);
	void (*cache_flush)(void);
	int (*create_gatt_table)(void);
	int (*free_gatt_table)(void);
	int (*insert_memory)(agp_memory *, off_t, int);
	int (*remove_memory)(agp_memory *, off_t, int);
	agp_memory *(*alloc_by_type)(size_t, int);
	void (*free_by_type)(agp_memory *);
	int (*get_reserved_map)(agp_memory *);

	int (*suspend)(void);
	void (*resume)(void);

	struct page *(*agp_alloc_page)(pgprot_t);
	void (*agp_free_page)(struct page *);

	struct page *(*mem_ofs_to_page)(agp_memory *, unsigned long);
	int (*mem_insert_pages)(agp_memory *, int);
	void (*mem_remove_pages)(agp_memory *);
	void (*fill_range_with_page)(int, int, struct page *);

	int (*get_vm_config)(struct pci_dev *);
} agp_context;

#define OUTREG64(mmap, addr, val)   __raw_writeq((val), (mmap)+(addr))
#define OUTREG32(mmap, addr, val)   __raw_writel((val), (mmap)+(addr))
#define OUTREG16(mmap, addr, val)   __raw_writew((val), (mmap)+(addr))
#define OUTREG8(mmap, addr, val)   __raw_writeb((val), (mmap)+(addr))

#define INREG64(mmap, addr)         __raw_readq((mmap)+(addr))
#define INREG32(mmap, addr)         __raw_readl((mmap)+(addr))
#define INREG16(mmap, addr)         __raw_readw((mmap)+(addr))
#define INREG8(mmap, addr)         __raw_readb((mmap)+(addr))

#define KB(x) ((x) * 1024)
#define MB(x) (KB (KB (x)))
#define GB(x) (MB (KB (x)))

#define CACHE_FLUSH	agp_bridge->cache_flush
#define A_SIZE_8(x)	((aper_size_info_8 *) x)
#define A_SIZE_16(x)	((aper_size_info_16 *) x)
#define A_SIZE_32(x)	((aper_size_info_32 *) x)
#define A_SIZE_LVL2(x)  ((aper_size_info_lvl2 *) x)
#define A_SIZE_FIX(x)	((aper_size_info_fixed *) x)
#define A_IDX8(i)	(A_SIZE_8(agp_bridge->aperture_sizes) + i)
#define A_IDX16(i)	(A_SIZE_16(agp_bridge->aperture_sizes) + i)
#define A_IDX32(i)	(A_SIZE_32(agp_bridge->aperture_sizes) + i)
#define A_IDXLVL2(i)	(A_SIZE_LVL2(agp_bridge->aperture_sizes) + i)
#define A_IDXFIX(i)	(A_SIZE_FIX(agp_bridge->aperture_sizes) + i)
#define MAXKEY		(4096 * 32)

#define AGPGART_MODULE_NAME	"agpgart"
#define PFX			AGPGART_MODULE_NAME ": "

#ifndef PCI_DEVICE_ID_VIA_82C691_0
#define PCI_DEVICE_ID_VIA_82C691_0      0x0691
#endif
#ifndef PCI_DEVICE_ID_VIA_8371_0
#define PCI_DEVICE_ID_VIA_8371_0      0x0391
#endif
#ifndef PCI_DEVICE_ID_VIA_8363_0
#define PCI_DEVICE_ID_VIA_8363_0      0x0305
#endif
#ifndef PCI_DEVICE_ID_VIA_82C694X_0
#define PCI_DEVICE_ID_VIA_82C694X_0      0x0605
#endif
#ifndef PCI_DEVICE_ID_INTEL_810_0
#define PCI_DEVICE_ID_INTEL_810_0       0x7120
#endif
#ifndef PCI_DEVICE_ID_INTEL_845_G_0
#define PCI_DEVICE_ID_INTEL_845_G_0	0x2560
#endif
#ifndef PCI_DEVICE_ID_INTEL_845_G_1
#define PCI_DEVICE_ID_INTEL_845_G_1     0x2562
#endif
#ifndef PCI_DEVICE_ID_INTEL_830_M_0
#define PCI_DEVICE_ID_INTEL_830_M_0	0x3575
#endif
#ifndef PCI_DEVICE_ID_INTEL_830_M_1
#define PCI_DEVICE_ID_INTEL_830_M_1     0x3577
#endif
#ifndef PCI_DEVICE_ID_INTEL_820_0
#define PCI_DEVICE_ID_INTEL_820_0       0x2500
#endif
#ifndef PCI_DEVICE_ID_INTEL_820_UP_0
#define PCI_DEVICE_ID_INTEL_820_UP_0    0x2501
#endif
#ifndef PCI_DEVICE_ID_INTEL_840_0
#define PCI_DEVICE_ID_INTEL_840_0		0x1a21
#endif
#ifndef PCI_DEVICE_ID_INTEL_845_0
#define PCI_DEVICE_ID_INTEL_845_0     0x1a30
#endif
#ifndef PCI_DEVICE_ID_INTEL_850_0
#define PCI_DEVICE_ID_INTEL_850_0     0x2530
#endif
#ifndef PCI_DEVICE_ID_INTEL_860_0
#define PCI_DEVICE_ID_INTEL_860_0     0x2531
#endif
#ifndef PCI_DEVICE_ID_INTEL_810_DC100_0
#define PCI_DEVICE_ID_INTEL_810_DC100_0 0x7122
#endif
#ifndef PCI_DEVICE_ID_INTEL_810_E_0
#define PCI_DEVICE_ID_INTEL_810_E_0     0x7124
#endif
#ifndef PCI_DEVICE_ID_INTEL_82443GX_0
#define PCI_DEVICE_ID_INTEL_82443GX_0   0x71a0
#endif
#ifndef PCI_DEVICE_ID_INTEL_810_1
#define PCI_DEVICE_ID_INTEL_810_1       0x7121
#endif
#ifndef PCI_DEVICE_ID_INTEL_810_DC100_1
#define PCI_DEVICE_ID_INTEL_810_DC100_1 0x7123
#endif
#ifndef PCI_DEVICE_ID_INTEL_810_E_1
#define PCI_DEVICE_ID_INTEL_810_E_1     0x7125
#endif
#ifndef PCI_DEVICE_ID_INTEL_815_0
#define PCI_DEVICE_ID_INTEL_815_0       0x1130
#endif
#ifndef PCI_DEVICE_ID_INTEL_815_1
#define PCI_DEVICE_ID_INTEL_815_1       0x1132
#endif
#ifndef PCI_DEVICE_ID_INTEL_82443GX_1
#define PCI_DEVICE_ID_INTEL_82443GX_1   0x71a1
#endif
#ifndef PCI_DEVICE_ID_AMD_IRONGATE_0
#define PCI_DEVICE_ID_AMD_IRONGATE_0    0x7006
#endif
#ifndef PCI_DEVICE_ID_AMD_761_0
#define PCI_DEVICE_ID_AMD_761_0         0x700e
#endif
#ifndef PCI_DEVICE_ID_AMD_762_0
#define PCI_DEVICE_ID_AMD_762_0		0x700C
#endif
#ifndef PCI_DEVICE_ID_AMD_8151_0
#define PCI_DEVICE_ID_AMD_8151_0	0x7454
#endif
#ifndef PCI_VENDOR_ID_AL
#define PCI_VENDOR_ID_AL		0x10b9
#endif
#ifndef PCI_DEVICE_ID_AL_M1541_0
#define PCI_DEVICE_ID_AL_M1541_0	0x1541
#endif
#ifndef PCI_DEVICE_ID_AL_M1621_0
#define PCI_DEVICE_ID_AL_M1621_0	0x1621
#endif
#ifndef PCI_DEVICE_ID_AL_M1631_0
#define PCI_DEVICE_ID_AL_M1631_0	0x1631
#endif
#ifndef PCI_DEVICE_ID_AL_M1632_0
#define PCI_DEVICE_ID_AL_M1632_0	0x1632
#endif
#ifndef PCI_DEVICE_ID_AL_M1641_0
#define PCI_DEVICE_ID_AL_M1641_0	0x1641
#endif
#ifndef PCI_DEVICE_ID_AL_M1644_0
#define PCI_DEVICE_ID_AL_M1644_0	0x1644
#endif
#ifndef PCI_DEVICE_ID_AL_M1647_0
#define PCI_DEVICE_ID_AL_M1647_0	0x1647
#endif
#ifndef PCI_DEVICE_ID_AL_M1651_0
#define PCI_DEVICE_ID_AL_M1651_0	0x1651
#endif
#ifndef PCI_DEVICE_ID_AL_M1671_0
#define PCI_DEVICE_ID_AL_M1671_0	0x1671
#endif

/* Standard agp registers */
#define AGPSTAT 			0x4
#define AGPCMD				0x8
#define AGPNEPG 			0x16

#define AGP_MAJOR_VERSION_MASK		((1<<20)|(1<<21)|(1<<22)|(1<<23))
#define AGP_MAJOR_VERSION_SHIFT 	(20)
#define AGP_MINOR_VERSION_MASK		((1<<19)|(1<<18)|(1<<17)|(1<<16))
#define AGP_MINOR_VERSION_SHIFT 	(16)
#define AGPSTAT_CAL_4_MS		(0)
#define AGPSTAT_CAL_16_MS		(1<<10)
#define AGPSTAT_CAL_64_MS		(1<<11)
#define AGPSTAT_CAL_256_MS		((1<<11)|(1<<10))
#define AGPSTAT_CAL_MASK       		((1<<12)|(1<<11)|(1<<10))
#define AGPSTAT_ARQSZ			((1<<15)|(1<<14)|(1<<13))
#define AGPSTAT_ARQSZ_SHIFT		13
#define AGPSTAT_RQ_DEPTH		(0xff000000)
#define AGPSTAT_RQD_SHIFT		24
#define AGPSTAT_SBA			(1<<9)
#define AGPSTAT_AGP_ENABLE		(1<<8)
#define AGPSTAT_FW			(1<<4)
#define AGPSTAT_MODE_3_0		(1<<3)
#define AGPSTAT3_RSVD			(1<<2)
#define AGPSTAT3_8X			(1<<1)
#define AGPSTAT3_4X			(1)
#define AGPSTAT2_4X			(1<<2)
#define AGPSTAT2_2X			(1<<1)
#define AGPSTAT2_1X			(1)
#define AGPSTAT_HOST_TRANS		(1<<6)
#define AGPSTAT_OVER4G			(1<<5)
#define AGPSTAT_SUPPORT_GART64B 	(1<<7)
#define AGPSTAT_SUPPORT_COHERENT	(1<<8)
#define AGPSTAT_SUPPORT_ISOCHRONOUS	(1<<17)

#define AGPNEPG_SELECT_ORDER(x) 	((x - 12) << 12)
#define AGPNEPG_SUPPORT_ORDER(x)	(1 << (x - 12))
#define AGPNEPG_ORDER_MASK		((1<<15)|(1<<14)|(1<<13)|(1<<12))
#define AGP_U32_ADDRESS_BITS		28

/* gatt bits from the AGP 3.0 specification (generally work on all devices) */
#define AGP_GATT_VALID_PAGE		0x1
#define AGP_GATT_CACHED_PAGE		(1<<1)

/* default gatt mask and gatt shift values */
#define AGP_DEFAULT_GATT_MASK		((1<<3)|(1<<2)|(1<<1)|1)
#define AGP_DEFAULT_GATT_SHIFT		0

/* intel register */
#define INTEL_APBASE    0x10
#define INTEL_APSIZE    0xb4
#define INTEL_ATTBASE   0xb8
#define INTEL_AGPCTRL   0xb0
#define INTEL_NBXCFG    0x50
#define INTEL_ERRSTS    0x91

/* intel i830 registers */
#define I830_GMCH_CTRL             0x52
#define I830_GMCH_ENABLED          0x4
#define I830_GMCH_MEM_MASK         0x1
#define I830_GMCH_MEM_64M          0x1
#define I830_GMCH_MEM_128M         0
#define I830_GMCH_GMS_MASK         0x70
#define I830_GMCH_GMS_DISABLED     0x00
#define I830_GMCH_GMS_LOCAL        0x10
#define I830_GMCH_GMS_STOLEN_512   0x20
#define I830_GMCH_GMS_STOLEN_1024  0x30
#define I830_GMCH_GMS_STOLEN_8192  0x40
#define I830_RDRAM_CHANNEL_TYPE    0x03010
#define I830_RDRAM_ND(x)           (((x) & 0x20) >> 5)
#define I830_RDRAM_DDT(x)          (((x) & 0x18) >> 3)

/* This one is for I830MP w. an external graphic card */
#define INTEL_I830_ERRSTS          0x92

/* intel 815 register */
#define INTEL_815_APCONT        0x51
#define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF

/* intel i820 registers */
#define INTEL_I820_RDCR     0x51
#define INTEL_I820_ERRSTS   0xc8

/* intel i840 registers */
#define INTEL_I840_MCHCFG   0x50
#define INTEL_I840_ERRSTS   0xc8
 
/* intel i845 registers */
#define INTEL_I845_AGPM     0x51
#define INTEL_I845_ERRSTS   0xc8

/* intel i850 registers */
#define INTEL_I850_MCHCFG   0x50
#define INTEL_I850_ERRSTS   0xc8

/* intel i860 registers */
#define INTEL_I860_MCHCFG	0x50
#define INTEL_I860_ERRSTS	0xc8

/* intel i810 registers */
#define I810_GMADDR 0x10
#define I810_MMADDR 0x14
#define I810_PTE_BASE          0x10000
#define I810_PTE_MAIN_UNCACHED 0x00000000
#define I810_PTE_LOCAL         0x00000002
#define I810_PTE_VALID         0x00000001
#define I810_SMRAM_MISCC       0x70
#define I810_GFX_MEM_WIN_SIZE  0x00010000
#define I810_GFX_MEM_WIN_32M   0x00010000
#define I810_GMS               0x000000c0
#define I810_GMS_DISABLE       0x00000000
#define I810_PGETBL_CTL        0x2020
#define I810_PGETBL_ENABLED    0x00000001
#define I810_DRAM_CTL          0x3000
#define I810_DRAM_ROW_0        0x00000001
#define I810_DRAM_ROW_0_SDRAM  0x00000001

/* VIA register */
#define VIA_APBASE      0x10
#define VIA_GARTCTRL    0x80
#define VIA_APSIZE      0x84
#define VIA_ATTBASE     0x88

/* SiS registers */
#define SIS_APBASE      0x10
#define SIS_ATTBASE     0x90
#define SIS_APSIZE      0x94
#define SIS_TLBCNTRL    0x97
#define SIS_TLBFLUSH    0x98

/* AMD registers */
#define AMD_APBASE      0x10
#define AMD_MMBASE      0x14
#define AMD_APSIZE      0xac
#define AMD_MODECNTL    0xb0
#define AMD_MODECNTL2   0xb2
#define AMD_GARTENABLE  0x02	/* In mmio region (16-bit register) */
#define AMD_ATTBASE     0x04	/* In mmio region (32-bit register) */
#define AMD_TLBFLUSH    0x0c	/* In mmio region (32-bit register) */
#define AMD_CACHEENTRY  0x10	/* In mmio region (32-bit register) */

#define AMD_8151_APSIZE	0xb4
#define AMD_8151_GARTBLOCK	0xb8

#define AMD_X86_64_GARTAPERTURECTL	0x90
#define AMD_X86_64_GARTAPERTUREBASE	0x94
#define AMD_X86_64_GARTTABLEBASE	0x98
#define AMD_X86_64_GARTCACHECTL		0x9c
#define AMD_X86_64_GARTEN	1<<0

#define AMD_8151_VMAPERTURE		0x10
#define AMD_8151_AGP_CTL		0xb0
#define AMD_8151_APERTURESIZE	0xb4
#define AMD_8151_GARTPTR		0xb8
#define AMD_8151_GTLBEN	1<<7
#define AMD_8151_APEREN	1<<8

/* ALi registers */
#define ALI_APBASE	0x10
#define ALI_AGPCTRL	0xb8
#define ALI_ATTBASE	0xbc
#define ALI_TLBCTRL	0xc0
#define ALI_TAGCTRL	0xc4
#define ALI_CACHE_FLUSH_CTRL	0xD0
#define ALI_CACHE_FLUSH_ADDR_MASK	0xFFFFF000
#define ALI_CACHE_FLUSH_EN	0x100

/* Serverworks Registers */
#define SVWRKS_APSIZE 0x10
#define SVWRKS_SIZE_MASK 0xfe000000

#define SVWRKS_MMBASE 0x14
#define SVWRKS_CACHING 0x4b
#define SVWRKS_FEATURE 0x68

/* func 1 registers */
#define SVWRKS_AGP_ENABLE 0x60
#define SVWRKS_COMMAND 0x04

/* Memory mapped registers */
#define SVWRKS_GART_CACHE 0x02
#define SVWRKS_GATTBASE   0x04
#define SVWRKS_TLBFLUSH   0x10
#define SVWRKS_POSTFLUSH  0x14
#define SVWRKS_DIRFLUSH   0x0c

/* HP ZX1 SBA registers */
#define HP_ZX1_CTRL		0x200
#define HP_ZX1_IBASE		0x300
#define HP_ZX1_IMASK		0x308
#define HP_ZX1_PCOM		0x310
#define HP_ZX1_TCNFG		0x318
#define HP_ZX1_PDIR_BASE	0x320
#define HP_ZX1_CACHE_FLUSH	0x428

#include "agp_query.h"
#include "agp_vm.h"
#include "agp_lists.h"
#include "agp_generic.h"
#include "agp_context.h"

#endif				/* _AGP_BACKEND_PRIV_H */