FSP-M MRC Training Issues

[TuguiAndreiDG]

Hello,

We are developing an Intel N100 (Alder Lake N) SoM, and we are using the following LPDDR5x RAM chips: MT62F1G32D2DS-023 WT:B.
We have configured the right SPD table, as suggested by Intel and mapped the correct DQ/DQS values, UserBD and CCC Config for the RAM.
We are currently using the v6304 version of the FSP and we have an issue during MRC Training, where it stops at 'Read Leveling Training' and does not continue forward. This issue happens when all 4 channels of the memory controller are being used. Attached, you will find the logs related to this issue:

mrc-training-4-channels-enabled.txt

If we leave just one channel enabled, we pass the 'Read Leveling Training' and the rest of the enabled training algorithms, but at the end we get an error at the following 'Install EFI Memory' log. We have attached the logs for this behaviour as well:

mrc-training-1-channel-enabled.txt

We also attached the the SPD table and the DQ/DQS values we used:

SPD&DQ_DQS.txt

Could you help us solving this issue?
We thank you in advance.

@LowLJ1999

[MihaiGruieti1]

I would like to add that the issue happens on validated hardware, that we know for sure that it has 100% working LPDDR5 interface.