From 3d845238deb3ea2c61964f2c9b009d72529525b1 Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Wed, 11 Feb 2026 15:53:19 -0800 Subject: [PATCH 01/13] feature: dmr reporting and configuration Signed-off-by: Harper, Jason M --- cmd/config/config_tables.go | 6 +++--- cmd/config/set.go | 4 ++-- cmd/report/report_tables.go | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/cmd/config/config_tables.go b/cmd/config/config_tables.go index 0b56b9ba..bc9a3633 100644 --- a/cmd/config/config_tables.go +++ b/cmd/config/config_tables.go @@ -71,7 +71,7 @@ func configurationTableValues(outputs map[string]script.ScriptOutput) []table.Fi {Name: "Package Power / TDP", Description: "--tdp ", Values: []string{extract.TDPFromOutput(outputs)}}, {Name: "Core SSE Frequency", Description: "--core-max ", Values: []string{sseFrequenciesFromOutput(outputs)}}, } - if strings.Contains(uarch, cpus.UarchSRF) || strings.Contains(uarch, cpus.UarchGNR) || strings.Contains(uarch, cpus.UarchCWF) { + if strings.Contains(uarch, cpus.UarchSRF) || strings.Contains(uarch, cpus.UarchGNR) || strings.Contains(uarch, cpus.UarchCWF) || strings.Contains(uarch, cpus.UarchDMR) { fields = append(fields, []table.Field{ {Name: "Uncore Max Frequency (Compute)", Description: "--uncore-max-compute ", Values: []string{extract.UncoreMinMaxDieFrequencyFromOutput(true, true, outputs)}}, {Name: "Uncore Min Frequency (Compute)", Description: "--uncore-min-compute ", Values: []string{extract.UncoreMinMaxDieFrequencyFromOutput(false, true, outputs)}}, @@ -89,8 +89,8 @@ func configurationTableValues(outputs map[string]script.ScriptOutput) []table.Fi {Name: "Energy Performance Preference", Description: "--epp <0-255>", Values: []string{extract.EPPFromOutput(outputs)}}, {Name: "Scaling Governor", Description: "--gov <" + strings.Join(governorOptions, "|") + ">", Values: []string{strings.TrimSpace(outputs[script.ScalingGovernorScriptName].Stdout)}}, }...) - // add ELC (for SRF, CWF and GNR only) - if strings.Contains(uarch, cpus.UarchSRF) || strings.Contains(uarch, cpus.UarchGNR) || strings.Contains(uarch, cpus.UarchCWF) { + // add ELC (for SRF, CWF, GNR, and DMR only) + if strings.Contains(uarch, cpus.UarchSRF) || strings.Contains(uarch, cpus.UarchGNR) || strings.Contains(uarch, cpus.UarchCWF) || strings.Contains(uarch, cpus.UarchDMR) { fields = append(fields, table.Field{Name: "Efficiency Latency Control", Description: "--elc <" + strings.Join(elcOptions, "|") + ">", Values: []string{extract.ELCSummaryFromOutput(outputs)}}) } // add prefetchers diff --git a/cmd/config/set.go b/cmd/config/set.go index 1983be49..aff6fdd5 100644 --- a/cmd/config/set.go +++ b/cmd/config/set.go @@ -819,7 +819,7 @@ done `, Superuser: true, Vendors: []string{cpus.IntelVendor}, - MicroArchitectures: []string{cpus.UarchGNR, cpus.UarchGNR_D, cpus.UarchSRF, cpus.UarchCWF}, + MicroArchitectures: []string{cpus.UarchGNR, cpus.UarchGNR_D, cpus.UarchSRF, cpus.UarchCWF, cpus.UarchDMR}, Depends: []string{"pcm-tpmi"}, } _, err := runScript(myTarget, setScript, localTempDir) @@ -842,7 +842,7 @@ pcm-tpmi 2 0x18 -d -b 38:32 -w 0 # EFFICIENCY_LATENCY_CTRL_LOW_THRESHOLD `, Superuser: true, Vendors: []string{cpus.IntelVendor}, - MicroArchitectures: []string{cpus.UarchGNR, cpus.UarchGNR_D, cpus.UarchSRF, cpus.UarchCWF}, + MicroArchitectures: []string{cpus.UarchGNR, cpus.UarchGNR_D, cpus.UarchSRF, cpus.UarchCWF, cpus.UarchDMR}, Depends: []string{"pcm-tpmi"}, } _, err := runScript(myTarget, setScript, localTempDir) diff --git a/cmd/report/report_tables.go b/cmd/report/report_tables.go index 527a3a68..f3c157c5 100644 --- a/cmd/report/report_tables.go +++ b/cmd/report/report_tables.go @@ -815,7 +815,7 @@ func uncoreTableValues(outputs map[string]script.ScriptOutput) []table.Field { slog.Error("failed to get uarch from script outputs") return []table.Field{} } - if strings.Contains(uarch, cpus.UarchSRF) || strings.Contains(uarch, cpus.UarchGNR) || strings.Contains(uarch, cpus.UarchCWF) { + if strings.Contains(uarch, cpus.UarchSRF) || strings.Contains(uarch, cpus.UarchGNR) || strings.Contains(uarch, cpus.UarchCWF) || strings.Contains(uarch, cpus.UarchDMR) { return []table.Field{ {Name: "Min Frequency (Compute)", Values: []string{extract.UncoreMinMaxDieFrequencyFromOutput(false, true, outputs)}}, {Name: "Min Frequency (I/O)", Values: []string{extract.UncoreMinMaxDieFrequencyFromOutput(false, false, outputs)}}, From e25630d9688293a2caa63fc992002895e027cf9a Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Thu, 12 Feb 2026 06:46:21 -0800 Subject: [PATCH 02/13] add DMR L2P prefetcher Signed-off-by: Harper, Jason M --- internal/extract/prefetcher.go | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/internal/extract/prefetcher.go b/internal/extract/prefetcher.go index ef9f5076..648d2eaa 100644 --- a/internal/extract/prefetcher.go +++ b/internal/extract/prefetcher.go @@ -34,6 +34,7 @@ const ( PrefetcherHomelessName = "Homeless" PrefetcherLLCName = "LLC" PrefetcherLLCStreamName = "LLC Stream" + PrefetcherL2PName = "L2P" ) // PrefetcherDefinition represents a prefetcher configuration. @@ -103,6 +104,13 @@ var PrefetcherDefinitions = []PrefetcherDefinition{ Bit: 7, Uarchs: []string{cpus.UarchGNR}, }, + { + ShortName: PrefetcherL2PName, + Description: "L2P", + Msr: MsrPrefetchControl, + Bit: 12, + Uarchs: []string{cpus.UarchDMR}, + }, { ShortName: PrefetcherHomelessName, Description: "Homeless prefetch allows early fetch of the demand miss into the MLC when we don't have enough resources to track this demand in the L1 cache.", From 87189a3fdbb14e158e6614faed1ffc8d165eedd2 Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Thu, 12 Feb 2026 11:31:06 -0800 Subject: [PATCH 03/13] feature: enhance L2P prefetcher management and definitions Signed-off-by: Harper, Jason M --- internal/extract/prefetcher.go | 103 +++++++++++++++++++++++---------- 1 file changed, 71 insertions(+), 32 deletions(-) diff --git a/internal/extract/prefetcher.go b/internal/extract/prefetcher.go index 648d2eaa..09616b8d 100644 --- a/internal/extract/prefetcher.go +++ b/internal/extract/prefetcher.go @@ -39,28 +39,31 @@ const ( // PrefetcherDefinition represents a prefetcher configuration. type PrefetcherDefinition struct { - ShortName string - Description string - Msr int - Bit int - Uarchs []string + ShortName string + Description string + Msr int + Bit int + Uarchs []string + ManagedByL2P bool // indicates if the prefetcher is dynamically managed by the L2P algorithm } // PrefetcherDefinitions contains all known prefetcher definitions. var PrefetcherDefinitions = []PrefetcherDefinition{ { - ShortName: PrefetcherL2HWName, - Description: "L2 Hardware (MLC Streamer) fetches additional lines of code or data into the L2 cache.", - Msr: MsrPrefetchControl, - Bit: 0, - Uarchs: []string{"all"}, + ShortName: PrefetcherL2HWName, + Description: "L2 Hardware (MLC Streamer) fetches additional lines of code or data into the L2 cache.", + Msr: MsrPrefetchControl, + Bit: 0, + Uarchs: []string{"all"}, + ManagedByL2P: true, }, { - ShortName: PrefetcherL2AdjName, - Description: "L2 Adjacent Cache Line (MLC Spatial) fetches the cache line that comprises a cache line pair.", - Msr: MsrPrefetchControl, - Bit: 1, - Uarchs: []string{"all"}, + ShortName: PrefetcherL2AdjName, + Description: "L2 Adjacent Cache Line (MLC Spatial) fetches the cache line that comprises a cache line pair.", + Msr: MsrPrefetchControl, + Bit: 1, + Uarchs: []string{"all"}, + ManagedByL2P: true, }, { ShortName: PrefetcherDCUHWName, @@ -84,18 +87,20 @@ var PrefetcherDefinitions = []PrefetcherDefinition{ Uarchs: []string{"all"}, }, { - ShortName: PrefetcherAMPName, - Description: "Adaptive Multipath Probability (MLC AMP) predicts access patterns based on previous patterns and fetches the corresponding cache lines into the L2 cache.", - Msr: MsrPrefetchControl, - Bit: 5, - Uarchs: []string{cpus.UarchSPR, cpus.UarchEMR, cpus.UarchGNR}, + ShortName: PrefetcherAMPName, + Description: "Adaptive Multipath Probability (MLC AMP) predicts access patterns based on previous patterns and fetches the corresponding cache lines into the L2 cache.", + Msr: MsrPrefetchControl, + Bit: 5, + Uarchs: []string{cpus.UarchSPR, cpus.UarchEMR, cpus.UarchGNR, cpus.UarchDMR}, + ManagedByL2P: true, }, { - ShortName: PrefetcherLLCPPName, - Description: "Last Level Cache Page (MLC LLC Page) Prefetcher", - Msr: MsrPrefetchControl, - Bit: 6, - Uarchs: []string{cpus.UarchGNR}, + ShortName: PrefetcherLLCPPName, + Description: "Last Level Cache Page (MLC LLC Page) Prefetcher", + Msr: MsrPrefetchControl, + Bit: 6, + Uarchs: []string{cpus.UarchGNR, cpus.UarchDMR}, + ManagedByL2P: true, }, { ShortName: PrefetcherAOPName, @@ -105,8 +110,10 @@ var PrefetcherDefinitions = []PrefetcherDefinition{ Uarchs: []string{cpus.UarchGNR}, }, { + // ON DMR, when enabled, prefetchers at bit 0, 1, 5, and 6 are dynamically controlled by the L2P algorithm + // ON SPR/EMR/GNR, if prefetchers at bit 0, 1, 5, and 6 are enabled, they are dynamically controlled by the L2P algorithm ShortName: PrefetcherL2PName, - Description: "L2P", + Description: "L2P is an algorithm that dynamically enables or disables prefetchers based on real-time telemetry.", Msr: MsrPrefetchControl, Bit: 12, Uarchs: []string{cpus.UarchDMR}, @@ -170,6 +177,18 @@ func PrefetchersFromOutput(outputs map[string]script.ScriptOutput) [][]string { if uarch == "" { return [][]string{} } + // if on DMR, we need to check if L2P is enabled first, as it dynamically manages the prefetchers at bit 0, 1, 5, and 6 + l2pEnabled := false + if slices.Contains([]string{cpus.UarchDMR}, uarch[:3]) { + l2pVal := ValFromRegexSubmatch(outputs[script.PrefetchControlName].Stdout, `^([0-9a-fA-F]+)`) + if l2pVal != "" { + var err error + l2pEnabled, err = IsPrefetcherEnabled(l2pVal, 12) + if err != nil { + slog.Warn("error checking L2P enabled status", slog.String("error", err.Error())) + } + } + } for _, pf := range PrefetcherDefinitions { if slices.Contains(pf.Uarchs, "all") || slices.Contains(pf.Uarchs, uarch[:3]) { var scriptName string @@ -194,10 +213,14 @@ func PrefetchersFromOutput(outputs map[string]script.ScriptOutput) [][]string { slog.Warn("error checking prefetcher enabled status", slog.String("error", err.Error())) continue } - if enabled { - enabledDisabled = "Enabled" + if l2pEnabled && pf.ManagedByL2P { + enabledDisabled = "Managed by L2P" } else { - enabledDisabled = "Disabled" + if enabled { + enabledDisabled = "Enabled" + } else { + enabledDisabled = "Disabled" + } } out = append(out, []string{pf.ShortName, pf.Description, fmt.Sprintf("0x%04X", pf.Msr), strconv.Itoa(pf.Bit), enabledDisabled}) } @@ -211,6 +234,18 @@ func PrefetchersSummaryFromOutput(outputs map[string]script.ScriptOutput) string if uarch == "" { return "" } + // if on DMR, we need to check if L2P is enabled first, as it dynamically manages the prefetchers at bit 0, 1, 5, and 6 + l2pEnabled := false + if slices.Contains([]string{cpus.UarchDMR}, uarch[:3]) { + l2pVal := ValFromRegexSubmatch(outputs[script.PrefetchControlName].Stdout, `^([0-9a-fA-F]+)`) + if l2pVal != "" { + var err error + l2pEnabled, err = IsPrefetcherEnabled(l2pVal, 12) + if err != nil { + slog.Warn("error checking L2P enabled status", slog.String("error", err.Error())) + } + } + } var prefList []string for _, pf := range PrefetcherDefinitions { if slices.Contains(pf.Uarchs, "all") || slices.Contains(pf.Uarchs, uarch[:3]) { @@ -236,10 +271,14 @@ func PrefetchersSummaryFromOutput(outputs map[string]script.ScriptOutput) string slog.Warn("error checking prefetcher enabled status", slog.String("error", err.Error())) continue } - if enabled { - enabledDisabled = "Enabled" + if l2pEnabled && pf.ManagedByL2P { + enabledDisabled = "Managed by L2P" } else { - enabledDisabled = "Disabled" + if enabled { + enabledDisabled = "Enabled" + } else { + enabledDisabled = "Disabled" + } } prefList = append(prefList, fmt.Sprintf("%s: %s", pf.ShortName, enabledDisabled)) } From 0ba1c21ea2ebab430e70d1cbf8f205b951efc44e Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Thu, 12 Feb 2026 12:45:37 -0800 Subject: [PATCH 04/13] refactor prefetcher funcs to eliminate duplication Signed-off-by: Harper, Jason M --- internal/extract/prefetcher.go | 160 ++++++++++++++------------------- 1 file changed, 68 insertions(+), 92 deletions(-) diff --git a/internal/extract/prefetcher.go b/internal/extract/prefetcher.go index 09616b8d..9696c9b8 100644 --- a/internal/extract/prefetcher.go +++ b/internal/extract/prefetcher.go @@ -170,12 +170,17 @@ func IsPrefetcherEnabled(msrValue string, bit int) (bool, error) { return bitMask&msrInt == 0, nil } -// PrefetchersFromOutput extracts prefetcher status from script outputs. -func PrefetchersFromOutput(outputs map[string]script.ScriptOutput) [][]string { - out := make([][]string, 0) +// resolvedPrefetcher holds the resolved status of a single prefetcher. +type resolvedPrefetcher struct { + Definition PrefetcherDefinition + Status string // "Enabled", "Disabled", or "Managed by L2P" +} + +// resolvePrefetchers determines the status of each applicable prefetcher from script outputs. +func resolvePrefetchers(outputs map[string]script.ScriptOutput) []resolvedPrefetcher { uarch := UarchFromOutput(outputs) if uarch == "" { - return [][]string{} + return nil } // if on DMR, we need to check if L2P is enabled first, as it dynamically manages the prefetchers at bit 0, 1, 5, and 6 l2pEnabled := false @@ -189,102 +194,73 @@ func PrefetchersFromOutput(outputs map[string]script.ScriptOutput) [][]string { } } } + var results []resolvedPrefetcher for _, pf := range PrefetcherDefinitions { - if slices.Contains(pf.Uarchs, "all") || slices.Contains(pf.Uarchs, uarch[:3]) { - var scriptName string - switch pf.Msr { - case MsrPrefetchControl: - scriptName = script.PrefetchControlName - case MsrPrefetchers: - scriptName = script.PrefetchersName - case MsrAtomPrefTuning1: - scriptName = script.PrefetchersAtomName - default: - slog.Error("unknown msr for prefetcher", slog.String("msr", fmt.Sprintf("0x%x", pf.Msr))) - continue - } - msrVal := ValFromRegexSubmatch(outputs[scriptName].Stdout, `^([0-9a-fA-F]+)`) - if msrVal == "" { - continue - } - var enabledDisabled string - enabled, err := IsPrefetcherEnabled(msrVal, pf.Bit) - if err != nil { - slog.Warn("error checking prefetcher enabled status", slog.String("error", err.Error())) - continue - } - if l2pEnabled && pf.ManagedByL2P { - enabledDisabled = "Managed by L2P" - } else { - if enabled { - enabledDisabled = "Enabled" - } else { - enabledDisabled = "Disabled" - } - } - out = append(out, []string{pf.ShortName, pf.Description, fmt.Sprintf("0x%04X", pf.Msr), strconv.Itoa(pf.Bit), enabledDisabled}) + if !slices.Contains(pf.Uarchs, "all") && !slices.Contains(pf.Uarchs, uarch[:3]) { + continue + } + var scriptName string + switch pf.Msr { + case MsrPrefetchControl: + scriptName = script.PrefetchControlName + case MsrPrefetchers: + scriptName = script.PrefetchersName + case MsrAtomPrefTuning1: + scriptName = script.PrefetchersAtomName + default: + slog.Error("unknown msr for prefetcher", slog.String("msr", fmt.Sprintf("0x%x", pf.Msr))) + continue } + msrVal := ValFromRegexSubmatch(outputs[scriptName].Stdout, `^([0-9a-fA-F]+)`) + if msrVal == "" { + continue + } + enabled, err := IsPrefetcherEnabled(msrVal, pf.Bit) + if err != nil { + slog.Warn("error checking prefetcher enabled status", slog.String("error", err.Error())) + continue + } + var status string + if l2pEnabled && pf.ManagedByL2P { + status = "Managed by L2P" + } else if enabled { + status = "Enabled" + } else { + status = "Disabled" + } + results = append(results, resolvedPrefetcher{Definition: pf, Status: status}) + } + return results +} + +// PrefetchersFromOutput extracts prefetcher status from script outputs. +func PrefetchersFromOutput(outputs map[string]script.ScriptOutput) [][]string { + resolved := resolvePrefetchers(outputs) + if resolved == nil { + return [][]string{} + } + out := make([][]string, 0, len(resolved)) + for _, r := range resolved { + out = append(out, []string{ + r.Definition.ShortName, + r.Definition.Description, + fmt.Sprintf("0x%04X", r.Definition.Msr), + strconv.Itoa(r.Definition.Bit), + r.Status, + }) } return out } // PrefetchersSummaryFromOutput returns a summary of all prefetcher statuses. func PrefetchersSummaryFromOutput(outputs map[string]script.ScriptOutput) string { - uarch := UarchFromOutput(outputs) - if uarch == "" { - return "" - } - // if on DMR, we need to check if L2P is enabled first, as it dynamically manages the prefetchers at bit 0, 1, 5, and 6 - l2pEnabled := false - if slices.Contains([]string{cpus.UarchDMR}, uarch[:3]) { - l2pVal := ValFromRegexSubmatch(outputs[script.PrefetchControlName].Stdout, `^([0-9a-fA-F]+)`) - if l2pVal != "" { - var err error - l2pEnabled, err = IsPrefetcherEnabled(l2pVal, 12) - if err != nil { - slog.Warn("error checking L2P enabled status", slog.String("error", err.Error())) - } - } - } - var prefList []string - for _, pf := range PrefetcherDefinitions { - if slices.Contains(pf.Uarchs, "all") || slices.Contains(pf.Uarchs, uarch[:3]) { - var scriptName string - switch pf.Msr { - case MsrPrefetchControl: - scriptName = script.PrefetchControlName - case MsrPrefetchers: - scriptName = script.PrefetchersName - case MsrAtomPrefTuning1: - scriptName = script.PrefetchersAtomName - default: - slog.Error("unknown msr for prefetcher", slog.String("msr", fmt.Sprintf("0x%x", pf.Msr))) - continue - } - msrVal := ValFromRegexSubmatch(outputs[scriptName].Stdout, `^([0-9a-fA-F]+)`) - if msrVal == "" { - continue - } - var enabledDisabled string - enabled, err := IsPrefetcherEnabled(msrVal, pf.Bit) - if err != nil { - slog.Warn("error checking prefetcher enabled status", slog.String("error", err.Error())) - continue - } - if l2pEnabled && pf.ManagedByL2P { - enabledDisabled = "Managed by L2P" - } else { - if enabled { - enabledDisabled = "Enabled" - } else { - enabledDisabled = "Disabled" - } - } - prefList = append(prefList, fmt.Sprintf("%s: %s", pf.ShortName, enabledDisabled)) - } + resolved := resolvePrefetchers(outputs) + if len(resolved) == 0 { + return "None" } - if len(prefList) > 0 { - return strings.Join(prefList, ", ") + prefList := make([]string, 0, len(resolved)) + for _, r := range resolved { + prefList = append(prefList, fmt.Sprintf("%s: %s", r.Definition.ShortName, r.Status)) } - return "None" + return strings.Join(prefList, ", ") } From 6db7f48ce0e8a579534eaa218e30943b6ae25817 Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Fri, 13 Feb 2026 08:05:17 -0800 Subject: [PATCH 05/13] 16 cache ways Signed-off-by: Harper, Jason M --- internal/cpus/cpus.go | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/internal/cpus/cpus.go b/internal/cpus/cpus.go index 0f1171a5..58e0d9de 100644 --- a/internal/cpus/cpus.go +++ b/internal/cpus/cpus.go @@ -141,7 +141,7 @@ var cpuCharacteristicsMap = map[string]CPUCharacteristics{ UarchGNR_X3: {MicroArchitecture: UarchGNR_X3, MemoryChannelCount: 12, LogicalThreadCount: 2, CacheWayCount: 16}, // Granite Rapids - AP (UCC) UarchGNR_D: {MicroArchitecture: UarchGNR_D, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 16}, // Granite Rapids - D UarchCWF: {MicroArchitecture: UarchCWF, MemoryChannelCount: 12, LogicalThreadCount: 1, CacheWayCount: 0}, // Clearwater Forest - generic - UarchDMR: {MicroArchitecture: UarchDMR, MemoryChannelCount: 16, LogicalThreadCount: 1, CacheWayCount: 0}, // Diamond Rapids + UarchDMR: {MicroArchitecture: UarchDMR, MemoryChannelCount: 16, LogicalThreadCount: 1, CacheWayCount: 16}, // Diamond Rapids // AMD CPUs UarchNaples: {MicroArchitecture: UarchNaples, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 0}, // Naples UarchRome: {MicroArchitecture: UarchRome, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 0}, // Rome From f8506ed20f19ca8475ae006a6119dadca041e08c Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Wed, 11 Feb 2026 15:53:19 -0800 Subject: [PATCH 06/13] feature: dmr reporting and configuration Signed-off-by: Harper, Jason M --- cmd/config/config_tables.go | 6 +++--- cmd/config/set.go | 4 ++-- cmd/report/report_tables.go | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/cmd/config/config_tables.go b/cmd/config/config_tables.go index 0b56b9ba..bc9a3633 100644 --- a/cmd/config/config_tables.go +++ b/cmd/config/config_tables.go @@ -71,7 +71,7 @@ func configurationTableValues(outputs map[string]script.ScriptOutput) []table.Fi {Name: "Package Power / TDP", Description: "--tdp ", Values: []string{extract.TDPFromOutput(outputs)}}, {Name: "Core SSE Frequency", Description: "--core-max ", Values: []string{sseFrequenciesFromOutput(outputs)}}, } - if strings.Contains(uarch, cpus.UarchSRF) || strings.Contains(uarch, cpus.UarchGNR) || strings.Contains(uarch, cpus.UarchCWF) { + if strings.Contains(uarch, cpus.UarchSRF) || strings.Contains(uarch, cpus.UarchGNR) || strings.Contains(uarch, cpus.UarchCWF) || strings.Contains(uarch, cpus.UarchDMR) { fields = append(fields, []table.Field{ {Name: "Uncore Max Frequency (Compute)", Description: "--uncore-max-compute ", Values: []string{extract.UncoreMinMaxDieFrequencyFromOutput(true, true, outputs)}}, {Name: "Uncore Min Frequency (Compute)", Description: "--uncore-min-compute ", Values: []string{extract.UncoreMinMaxDieFrequencyFromOutput(false, true, outputs)}}, @@ -89,8 +89,8 @@ func configurationTableValues(outputs map[string]script.ScriptOutput) []table.Fi {Name: "Energy Performance Preference", Description: "--epp <0-255>", Values: []string{extract.EPPFromOutput(outputs)}}, {Name: "Scaling Governor", Description: "--gov <" + strings.Join(governorOptions, "|") + ">", Values: []string{strings.TrimSpace(outputs[script.ScalingGovernorScriptName].Stdout)}}, }...) - // add ELC (for SRF, CWF and GNR only) - if strings.Contains(uarch, cpus.UarchSRF) || strings.Contains(uarch, cpus.UarchGNR) || strings.Contains(uarch, cpus.UarchCWF) { + // add ELC (for SRF, CWF, GNR, and DMR only) + if strings.Contains(uarch, cpus.UarchSRF) || strings.Contains(uarch, cpus.UarchGNR) || strings.Contains(uarch, cpus.UarchCWF) || strings.Contains(uarch, cpus.UarchDMR) { fields = append(fields, table.Field{Name: "Efficiency Latency Control", Description: "--elc <" + strings.Join(elcOptions, "|") + ">", Values: []string{extract.ELCSummaryFromOutput(outputs)}}) } // add prefetchers diff --git a/cmd/config/set.go b/cmd/config/set.go index 1983be49..aff6fdd5 100644 --- a/cmd/config/set.go +++ b/cmd/config/set.go @@ -819,7 +819,7 @@ done `, Superuser: true, Vendors: []string{cpus.IntelVendor}, - MicroArchitectures: []string{cpus.UarchGNR, cpus.UarchGNR_D, cpus.UarchSRF, cpus.UarchCWF}, + MicroArchitectures: []string{cpus.UarchGNR, cpus.UarchGNR_D, cpus.UarchSRF, cpus.UarchCWF, cpus.UarchDMR}, Depends: []string{"pcm-tpmi"}, } _, err := runScript(myTarget, setScript, localTempDir) @@ -842,7 +842,7 @@ pcm-tpmi 2 0x18 -d -b 38:32 -w 0 # EFFICIENCY_LATENCY_CTRL_LOW_THRESHOLD `, Superuser: true, Vendors: []string{cpus.IntelVendor}, - MicroArchitectures: []string{cpus.UarchGNR, cpus.UarchGNR_D, cpus.UarchSRF, cpus.UarchCWF}, + MicroArchitectures: []string{cpus.UarchGNR, cpus.UarchGNR_D, cpus.UarchSRF, cpus.UarchCWF, cpus.UarchDMR}, Depends: []string{"pcm-tpmi"}, } _, err := runScript(myTarget, setScript, localTempDir) diff --git a/cmd/report/report_tables.go b/cmd/report/report_tables.go index 527a3a68..f3c157c5 100644 --- a/cmd/report/report_tables.go +++ b/cmd/report/report_tables.go @@ -815,7 +815,7 @@ func uncoreTableValues(outputs map[string]script.ScriptOutput) []table.Field { slog.Error("failed to get uarch from script outputs") return []table.Field{} } - if strings.Contains(uarch, cpus.UarchSRF) || strings.Contains(uarch, cpus.UarchGNR) || strings.Contains(uarch, cpus.UarchCWF) { + if strings.Contains(uarch, cpus.UarchSRF) || strings.Contains(uarch, cpus.UarchGNR) || strings.Contains(uarch, cpus.UarchCWF) || strings.Contains(uarch, cpus.UarchDMR) { return []table.Field{ {Name: "Min Frequency (Compute)", Values: []string{extract.UncoreMinMaxDieFrequencyFromOutput(false, true, outputs)}}, {Name: "Min Frequency (I/O)", Values: []string{extract.UncoreMinMaxDieFrequencyFromOutput(false, false, outputs)}}, From 49901112eedf07ae531870887a10871edbeae216 Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Thu, 12 Feb 2026 06:46:21 -0800 Subject: [PATCH 07/13] add DMR L2P prefetcher Signed-off-by: Harper, Jason M --- internal/extract/prefetcher.go | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/internal/extract/prefetcher.go b/internal/extract/prefetcher.go index ef9f5076..648d2eaa 100644 --- a/internal/extract/prefetcher.go +++ b/internal/extract/prefetcher.go @@ -34,6 +34,7 @@ const ( PrefetcherHomelessName = "Homeless" PrefetcherLLCName = "LLC" PrefetcherLLCStreamName = "LLC Stream" + PrefetcherL2PName = "L2P" ) // PrefetcherDefinition represents a prefetcher configuration. @@ -103,6 +104,13 @@ var PrefetcherDefinitions = []PrefetcherDefinition{ Bit: 7, Uarchs: []string{cpus.UarchGNR}, }, + { + ShortName: PrefetcherL2PName, + Description: "L2P", + Msr: MsrPrefetchControl, + Bit: 12, + Uarchs: []string{cpus.UarchDMR}, + }, { ShortName: PrefetcherHomelessName, Description: "Homeless prefetch allows early fetch of the demand miss into the MLC when we don't have enough resources to track this demand in the L1 cache.", From ce6c4d074eaf442f857ac47a950941fea18cca82 Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Thu, 12 Feb 2026 11:31:06 -0800 Subject: [PATCH 08/13] feature: enhance L2P prefetcher management and definitions Signed-off-by: Harper, Jason M --- internal/extract/prefetcher.go | 103 +++++++++++++++++++++++---------- 1 file changed, 71 insertions(+), 32 deletions(-) diff --git a/internal/extract/prefetcher.go b/internal/extract/prefetcher.go index 648d2eaa..09616b8d 100644 --- a/internal/extract/prefetcher.go +++ b/internal/extract/prefetcher.go @@ -39,28 +39,31 @@ const ( // PrefetcherDefinition represents a prefetcher configuration. type PrefetcherDefinition struct { - ShortName string - Description string - Msr int - Bit int - Uarchs []string + ShortName string + Description string + Msr int + Bit int + Uarchs []string + ManagedByL2P bool // indicates if the prefetcher is dynamically managed by the L2P algorithm } // PrefetcherDefinitions contains all known prefetcher definitions. var PrefetcherDefinitions = []PrefetcherDefinition{ { - ShortName: PrefetcherL2HWName, - Description: "L2 Hardware (MLC Streamer) fetches additional lines of code or data into the L2 cache.", - Msr: MsrPrefetchControl, - Bit: 0, - Uarchs: []string{"all"}, + ShortName: PrefetcherL2HWName, + Description: "L2 Hardware (MLC Streamer) fetches additional lines of code or data into the L2 cache.", + Msr: MsrPrefetchControl, + Bit: 0, + Uarchs: []string{"all"}, + ManagedByL2P: true, }, { - ShortName: PrefetcherL2AdjName, - Description: "L2 Adjacent Cache Line (MLC Spatial) fetches the cache line that comprises a cache line pair.", - Msr: MsrPrefetchControl, - Bit: 1, - Uarchs: []string{"all"}, + ShortName: PrefetcherL2AdjName, + Description: "L2 Adjacent Cache Line (MLC Spatial) fetches the cache line that comprises a cache line pair.", + Msr: MsrPrefetchControl, + Bit: 1, + Uarchs: []string{"all"}, + ManagedByL2P: true, }, { ShortName: PrefetcherDCUHWName, @@ -84,18 +87,20 @@ var PrefetcherDefinitions = []PrefetcherDefinition{ Uarchs: []string{"all"}, }, { - ShortName: PrefetcherAMPName, - Description: "Adaptive Multipath Probability (MLC AMP) predicts access patterns based on previous patterns and fetches the corresponding cache lines into the L2 cache.", - Msr: MsrPrefetchControl, - Bit: 5, - Uarchs: []string{cpus.UarchSPR, cpus.UarchEMR, cpus.UarchGNR}, + ShortName: PrefetcherAMPName, + Description: "Adaptive Multipath Probability (MLC AMP) predicts access patterns based on previous patterns and fetches the corresponding cache lines into the L2 cache.", + Msr: MsrPrefetchControl, + Bit: 5, + Uarchs: []string{cpus.UarchSPR, cpus.UarchEMR, cpus.UarchGNR, cpus.UarchDMR}, + ManagedByL2P: true, }, { - ShortName: PrefetcherLLCPPName, - Description: "Last Level Cache Page (MLC LLC Page) Prefetcher", - Msr: MsrPrefetchControl, - Bit: 6, - Uarchs: []string{cpus.UarchGNR}, + ShortName: PrefetcherLLCPPName, + Description: "Last Level Cache Page (MLC LLC Page) Prefetcher", + Msr: MsrPrefetchControl, + Bit: 6, + Uarchs: []string{cpus.UarchGNR, cpus.UarchDMR}, + ManagedByL2P: true, }, { ShortName: PrefetcherAOPName, @@ -105,8 +110,10 @@ var PrefetcherDefinitions = []PrefetcherDefinition{ Uarchs: []string{cpus.UarchGNR}, }, { + // ON DMR, when enabled, prefetchers at bit 0, 1, 5, and 6 are dynamically controlled by the L2P algorithm + // ON SPR/EMR/GNR, if prefetchers at bit 0, 1, 5, and 6 are enabled, they are dynamically controlled by the L2P algorithm ShortName: PrefetcherL2PName, - Description: "L2P", + Description: "L2P is an algorithm that dynamically enables or disables prefetchers based on real-time telemetry.", Msr: MsrPrefetchControl, Bit: 12, Uarchs: []string{cpus.UarchDMR}, @@ -170,6 +177,18 @@ func PrefetchersFromOutput(outputs map[string]script.ScriptOutput) [][]string { if uarch == "" { return [][]string{} } + // if on DMR, we need to check if L2P is enabled first, as it dynamically manages the prefetchers at bit 0, 1, 5, and 6 + l2pEnabled := false + if slices.Contains([]string{cpus.UarchDMR}, uarch[:3]) { + l2pVal := ValFromRegexSubmatch(outputs[script.PrefetchControlName].Stdout, `^([0-9a-fA-F]+)`) + if l2pVal != "" { + var err error + l2pEnabled, err = IsPrefetcherEnabled(l2pVal, 12) + if err != nil { + slog.Warn("error checking L2P enabled status", slog.String("error", err.Error())) + } + } + } for _, pf := range PrefetcherDefinitions { if slices.Contains(pf.Uarchs, "all") || slices.Contains(pf.Uarchs, uarch[:3]) { var scriptName string @@ -194,10 +213,14 @@ func PrefetchersFromOutput(outputs map[string]script.ScriptOutput) [][]string { slog.Warn("error checking prefetcher enabled status", slog.String("error", err.Error())) continue } - if enabled { - enabledDisabled = "Enabled" + if l2pEnabled && pf.ManagedByL2P { + enabledDisabled = "Managed by L2P" } else { - enabledDisabled = "Disabled" + if enabled { + enabledDisabled = "Enabled" + } else { + enabledDisabled = "Disabled" + } } out = append(out, []string{pf.ShortName, pf.Description, fmt.Sprintf("0x%04X", pf.Msr), strconv.Itoa(pf.Bit), enabledDisabled}) } @@ -211,6 +234,18 @@ func PrefetchersSummaryFromOutput(outputs map[string]script.ScriptOutput) string if uarch == "" { return "" } + // if on DMR, we need to check if L2P is enabled first, as it dynamically manages the prefetchers at bit 0, 1, 5, and 6 + l2pEnabled := false + if slices.Contains([]string{cpus.UarchDMR}, uarch[:3]) { + l2pVal := ValFromRegexSubmatch(outputs[script.PrefetchControlName].Stdout, `^([0-9a-fA-F]+)`) + if l2pVal != "" { + var err error + l2pEnabled, err = IsPrefetcherEnabled(l2pVal, 12) + if err != nil { + slog.Warn("error checking L2P enabled status", slog.String("error", err.Error())) + } + } + } var prefList []string for _, pf := range PrefetcherDefinitions { if slices.Contains(pf.Uarchs, "all") || slices.Contains(pf.Uarchs, uarch[:3]) { @@ -236,10 +271,14 @@ func PrefetchersSummaryFromOutput(outputs map[string]script.ScriptOutput) string slog.Warn("error checking prefetcher enabled status", slog.String("error", err.Error())) continue } - if enabled { - enabledDisabled = "Enabled" + if l2pEnabled && pf.ManagedByL2P { + enabledDisabled = "Managed by L2P" } else { - enabledDisabled = "Disabled" + if enabled { + enabledDisabled = "Enabled" + } else { + enabledDisabled = "Disabled" + } } prefList = append(prefList, fmt.Sprintf("%s: %s", pf.ShortName, enabledDisabled)) } From 0d1ffffe9e5e67bf1f0e18a9140404e00ef3b7d8 Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Thu, 12 Feb 2026 12:45:37 -0800 Subject: [PATCH 09/13] refactor prefetcher funcs to eliminate duplication Signed-off-by: Harper, Jason M --- internal/extract/prefetcher.go | 160 ++++++++++++++------------------- 1 file changed, 68 insertions(+), 92 deletions(-) diff --git a/internal/extract/prefetcher.go b/internal/extract/prefetcher.go index 09616b8d..9696c9b8 100644 --- a/internal/extract/prefetcher.go +++ b/internal/extract/prefetcher.go @@ -170,12 +170,17 @@ func IsPrefetcherEnabled(msrValue string, bit int) (bool, error) { return bitMask&msrInt == 0, nil } -// PrefetchersFromOutput extracts prefetcher status from script outputs. -func PrefetchersFromOutput(outputs map[string]script.ScriptOutput) [][]string { - out := make([][]string, 0) +// resolvedPrefetcher holds the resolved status of a single prefetcher. +type resolvedPrefetcher struct { + Definition PrefetcherDefinition + Status string // "Enabled", "Disabled", or "Managed by L2P" +} + +// resolvePrefetchers determines the status of each applicable prefetcher from script outputs. +func resolvePrefetchers(outputs map[string]script.ScriptOutput) []resolvedPrefetcher { uarch := UarchFromOutput(outputs) if uarch == "" { - return [][]string{} + return nil } // if on DMR, we need to check if L2P is enabled first, as it dynamically manages the prefetchers at bit 0, 1, 5, and 6 l2pEnabled := false @@ -189,102 +194,73 @@ func PrefetchersFromOutput(outputs map[string]script.ScriptOutput) [][]string { } } } + var results []resolvedPrefetcher for _, pf := range PrefetcherDefinitions { - if slices.Contains(pf.Uarchs, "all") || slices.Contains(pf.Uarchs, uarch[:3]) { - var scriptName string - switch pf.Msr { - case MsrPrefetchControl: - scriptName = script.PrefetchControlName - case MsrPrefetchers: - scriptName = script.PrefetchersName - case MsrAtomPrefTuning1: - scriptName = script.PrefetchersAtomName - default: - slog.Error("unknown msr for prefetcher", slog.String("msr", fmt.Sprintf("0x%x", pf.Msr))) - continue - } - msrVal := ValFromRegexSubmatch(outputs[scriptName].Stdout, `^([0-9a-fA-F]+)`) - if msrVal == "" { - continue - } - var enabledDisabled string - enabled, err := IsPrefetcherEnabled(msrVal, pf.Bit) - if err != nil { - slog.Warn("error checking prefetcher enabled status", slog.String("error", err.Error())) - continue - } - if l2pEnabled && pf.ManagedByL2P { - enabledDisabled = "Managed by L2P" - } else { - if enabled { - enabledDisabled = "Enabled" - } else { - enabledDisabled = "Disabled" - } - } - out = append(out, []string{pf.ShortName, pf.Description, fmt.Sprintf("0x%04X", pf.Msr), strconv.Itoa(pf.Bit), enabledDisabled}) + if !slices.Contains(pf.Uarchs, "all") && !slices.Contains(pf.Uarchs, uarch[:3]) { + continue + } + var scriptName string + switch pf.Msr { + case MsrPrefetchControl: + scriptName = script.PrefetchControlName + case MsrPrefetchers: + scriptName = script.PrefetchersName + case MsrAtomPrefTuning1: + scriptName = script.PrefetchersAtomName + default: + slog.Error("unknown msr for prefetcher", slog.String("msr", fmt.Sprintf("0x%x", pf.Msr))) + continue } + msrVal := ValFromRegexSubmatch(outputs[scriptName].Stdout, `^([0-9a-fA-F]+)`) + if msrVal == "" { + continue + } + enabled, err := IsPrefetcherEnabled(msrVal, pf.Bit) + if err != nil { + slog.Warn("error checking prefetcher enabled status", slog.String("error", err.Error())) + continue + } + var status string + if l2pEnabled && pf.ManagedByL2P { + status = "Managed by L2P" + } else if enabled { + status = "Enabled" + } else { + status = "Disabled" + } + results = append(results, resolvedPrefetcher{Definition: pf, Status: status}) + } + return results +} + +// PrefetchersFromOutput extracts prefetcher status from script outputs. +func PrefetchersFromOutput(outputs map[string]script.ScriptOutput) [][]string { + resolved := resolvePrefetchers(outputs) + if resolved == nil { + return [][]string{} + } + out := make([][]string, 0, len(resolved)) + for _, r := range resolved { + out = append(out, []string{ + r.Definition.ShortName, + r.Definition.Description, + fmt.Sprintf("0x%04X", r.Definition.Msr), + strconv.Itoa(r.Definition.Bit), + r.Status, + }) } return out } // PrefetchersSummaryFromOutput returns a summary of all prefetcher statuses. func PrefetchersSummaryFromOutput(outputs map[string]script.ScriptOutput) string { - uarch := UarchFromOutput(outputs) - if uarch == "" { - return "" - } - // if on DMR, we need to check if L2P is enabled first, as it dynamically manages the prefetchers at bit 0, 1, 5, and 6 - l2pEnabled := false - if slices.Contains([]string{cpus.UarchDMR}, uarch[:3]) { - l2pVal := ValFromRegexSubmatch(outputs[script.PrefetchControlName].Stdout, `^([0-9a-fA-F]+)`) - if l2pVal != "" { - var err error - l2pEnabled, err = IsPrefetcherEnabled(l2pVal, 12) - if err != nil { - slog.Warn("error checking L2P enabled status", slog.String("error", err.Error())) - } - } - } - var prefList []string - for _, pf := range PrefetcherDefinitions { - if slices.Contains(pf.Uarchs, "all") || slices.Contains(pf.Uarchs, uarch[:3]) { - var scriptName string - switch pf.Msr { - case MsrPrefetchControl: - scriptName = script.PrefetchControlName - case MsrPrefetchers: - scriptName = script.PrefetchersName - case MsrAtomPrefTuning1: - scriptName = script.PrefetchersAtomName - default: - slog.Error("unknown msr for prefetcher", slog.String("msr", fmt.Sprintf("0x%x", pf.Msr))) - continue - } - msrVal := ValFromRegexSubmatch(outputs[scriptName].Stdout, `^([0-9a-fA-F]+)`) - if msrVal == "" { - continue - } - var enabledDisabled string - enabled, err := IsPrefetcherEnabled(msrVal, pf.Bit) - if err != nil { - slog.Warn("error checking prefetcher enabled status", slog.String("error", err.Error())) - continue - } - if l2pEnabled && pf.ManagedByL2P { - enabledDisabled = "Managed by L2P" - } else { - if enabled { - enabledDisabled = "Enabled" - } else { - enabledDisabled = "Disabled" - } - } - prefList = append(prefList, fmt.Sprintf("%s: %s", pf.ShortName, enabledDisabled)) - } + resolved := resolvePrefetchers(outputs) + if len(resolved) == 0 { + return "None" } - if len(prefList) > 0 { - return strings.Join(prefList, ", ") + prefList := make([]string, 0, len(resolved)) + for _, r := range resolved { + prefList = append(prefList, fmt.Sprintf("%s: %s", r.Definition.ShortName, r.Status)) } - return "None" + return strings.Join(prefList, ", ") } From 302b00bbe17cf522d8e13288e5aaf27b184e2191 Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Fri, 13 Feb 2026 08:05:17 -0800 Subject: [PATCH 10/13] 16 cache ways Signed-off-by: Harper, Jason M --- internal/cpus/cpus.go | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/internal/cpus/cpus.go b/internal/cpus/cpus.go index dd70f50f..718fb56b 100644 --- a/internal/cpus/cpus.go +++ b/internal/cpus/cpus.go @@ -141,7 +141,7 @@ var cpuCharacteristicsMap = map[string]CPUCharacteristics{ UarchGNR_X3: {MicroArchitecture: UarchGNR_X3, MemoryChannelCount: 12, LogicalThreadCount: 2, CacheWayCount: 16}, // Granite Rapids - AP (UCC) UarchGNR_D: {MicroArchitecture: UarchGNR_D, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 16}, // Granite Rapids - D UarchCWF: {MicroArchitecture: UarchCWF, MemoryChannelCount: 12, LogicalThreadCount: 1, CacheWayCount: 16}, // Clearwater Forest - generic - UarchDMR: {MicroArchitecture: UarchDMR, MemoryChannelCount: 16, LogicalThreadCount: 1, CacheWayCount: 0}, // Diamond Rapids + UarchDMR: {MicroArchitecture: UarchDMR, MemoryChannelCount: 16, LogicalThreadCount: 1, CacheWayCount: 16}, // Diamond Rapids - generic // AMD CPUs UarchNaples: {MicroArchitecture: UarchNaples, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 0}, // Naples UarchRome: {MicroArchitecture: UarchRome, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 0}, // Rome From 899ae82fd5965f832d7dd3519424c3b4a7e3248d Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Fri, 13 Feb 2026 08:13:36 -0800 Subject: [PATCH 11/13] fix merge Signed-off-by: Harper, Jason M --- internal/cpus/cpus.go | 5 ----- 1 file changed, 5 deletions(-) diff --git a/internal/cpus/cpus.go b/internal/cpus/cpus.go index b7f8118e..718fb56b 100644 --- a/internal/cpus/cpus.go +++ b/internal/cpus/cpus.go @@ -140,13 +140,8 @@ var cpuCharacteristicsMap = map[string]CPUCharacteristics{ UarchGNR_X2: {MicroArchitecture: UarchGNR_X2, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 16}, // Granite Rapids - SP (XCC) UarchGNR_X3: {MicroArchitecture: UarchGNR_X3, MemoryChannelCount: 12, LogicalThreadCount: 2, CacheWayCount: 16}, // Granite Rapids - AP (UCC) UarchGNR_D: {MicroArchitecture: UarchGNR_D, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 16}, // Granite Rapids - D -<<<<<<< HEAD UarchCWF: {MicroArchitecture: UarchCWF, MemoryChannelCount: 12, LogicalThreadCount: 1, CacheWayCount: 16}, // Clearwater Forest - generic UarchDMR: {MicroArchitecture: UarchDMR, MemoryChannelCount: 16, LogicalThreadCount: 1, CacheWayCount: 16}, // Diamond Rapids - generic -======= - UarchCWF: {MicroArchitecture: UarchCWF, MemoryChannelCount: 12, LogicalThreadCount: 1, CacheWayCount: 0}, // Clearwater Forest - generic - UarchDMR: {MicroArchitecture: UarchDMR, MemoryChannelCount: 16, LogicalThreadCount: 1, CacheWayCount: 16}, // Diamond Rapids ->>>>>>> 6db7f48ce0e8a579534eaa218e30943b6ae25817 // AMD CPUs UarchNaples: {MicroArchitecture: UarchNaples, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 0}, // Naples UarchRome: {MicroArchitecture: UarchRome, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 0}, // Rome From 8795246b8b561df3baf5123d3370f9850211262d Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Sat, 14 Feb 2026 17:01:33 -0800 Subject: [PATCH 12/13] fix: enhance error handling in TDPFromOutput function Signed-off-by: Harper, Jason M --- internal/extract/power.go | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/internal/extract/power.go b/internal/extract/power.go index 396a41d1..d62d303d 100644 --- a/internal/extract/power.go +++ b/internal/extract/power.go @@ -247,9 +247,13 @@ func ELCFieldValuesFromOutput(outputs map[string]script.ScriptOutput) (fieldValu func TDPFromOutput(outputs map[string]script.ScriptOutput) string { msrHex := strings.TrimSpace(outputs[script.PackagePowerLimitName].Stdout) msr, err := strconv.ParseInt(msrHex, 16, 0) - if err != nil || msr == 0 { + if err != nil { + slog.Error("failed to parse TDP value", slog.String("error", err.Error()), slog.String("msrHex", msrHex)) return "" } + if msr == 0 { + return "Unknown" + } return fmt.Sprint(msr/8) + "W" } From 7f6d14275c09cc88d47160f7b8af168110823e3c Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Sat, 14 Feb 2026 17:01:54 -0800 Subject: [PATCH 13/13] fix: update CacheWayCount for Diamond Rapids CPU characteristics Signed-off-by: Harper, Jason M --- internal/cpus/cpus.go | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/internal/cpus/cpus.go b/internal/cpus/cpus.go index 718fb56b..b548a257 100644 --- a/internal/cpus/cpus.go +++ b/internal/cpus/cpus.go @@ -141,7 +141,7 @@ var cpuCharacteristicsMap = map[string]CPUCharacteristics{ UarchGNR_X3: {MicroArchitecture: UarchGNR_X3, MemoryChannelCount: 12, LogicalThreadCount: 2, CacheWayCount: 16}, // Granite Rapids - AP (UCC) UarchGNR_D: {MicroArchitecture: UarchGNR_D, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 16}, // Granite Rapids - D UarchCWF: {MicroArchitecture: UarchCWF, MemoryChannelCount: 12, LogicalThreadCount: 1, CacheWayCount: 16}, // Clearwater Forest - generic - UarchDMR: {MicroArchitecture: UarchDMR, MemoryChannelCount: 16, LogicalThreadCount: 1, CacheWayCount: 16}, // Diamond Rapids - generic + UarchDMR: {MicroArchitecture: UarchDMR, MemoryChannelCount: 16, LogicalThreadCount: 1, CacheWayCount: 10}, // Diamond Rapids - generic // AMD CPUs UarchNaples: {MicroArchitecture: UarchNaples, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 0}, // Naples UarchRome: {MicroArchitecture: UarchRome, MemoryChannelCount: 8, LogicalThreadCount: 2, CacheWayCount: 0}, // Rome