diff --git a/.gitmodules b/.gitmodules index 2d5a760762..bd195d3e07 100644 --- a/.gitmodules +++ b/.gitmodules @@ -90,3 +90,7 @@ path = addins/pulp/tech_cells url = https://github.com/pulp-platform/tech_cells_generic.git branch = master +[submodule "idma"] + path = addins/pulp/idma + url = https://github.com/juanschroeder/iDMA + branch = cvwsoc diff --git a/addins/cvwsoc/litedram/genesys2soc/include/generated/csr.h b/addins/cvwsoc/litedram/genesys2soc/include/generated/csr.h index 6fbda1e69d..56afaccfe4 100644 --- a/addins/cvwsoc/litedram/genesys2soc/include/generated/csr.h +++ b/addins/cvwsoc/litedram/genesys2soc/include/generated/csr.h @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by LiteX (b3d0f0260) on 2026-03-21 22:19:06 +// Auto-generated by LiteX (777d97377) on 2026-06-22 19:46:31 //-------------------------------------------------------------------------------- //-------------------------------------------------------------------------------- diff --git a/addins/cvwsoc/litedram/genesys2soc/include/generated/git.h b/addins/cvwsoc/litedram/genesys2soc/include/generated/git.h index 1a874ef8b7..5171849d9c 100644 --- a/addins/cvwsoc/litedram/genesys2soc/include/generated/git.h +++ b/addins/cvwsoc/litedram/genesys2soc/include/generated/git.h @@ -1,8 +1,8 @@ //-------------------------------------------------------------------------------- -// Auto-generated by LiteX (b3d0f0260) on 2026-03-21 22:19:06 +// Auto-generated by LiteX (777d97377) on 2026-06-22 19:46:31 //-------------------------------------------------------------------------------- #ifndef __GENERATED_GIT_H #define __GENERATED_GIT_H -#define LITEX_GIT_SHA1 "b3d0f0260" +#define LITEX_GIT_SHA1 "777d97377" #endif diff --git a/addins/cvwsoc/litedram/genesys2soc/include/generated/mem.h b/addins/cvwsoc/litedram/genesys2soc/include/generated/mem.h index 2f13338392..afa7b199ec 100644 --- a/addins/cvwsoc/litedram/genesys2soc/include/generated/mem.h +++ b/addins/cvwsoc/litedram/genesys2soc/include/generated/mem.h @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by LiteX (b3d0f0260) on 2026-03-21 22:19:06 +// Auto-generated by LiteX (777d97377) on 2026-06-22 19:46:31 //-------------------------------------------------------------------------------- #ifndef __GENERATED_MEM_H #define __GENERATED_MEM_H diff --git a/addins/cvwsoc/litedram/genesys2soc/include/generated/soc.h b/addins/cvwsoc/litedram/genesys2soc/include/generated/soc.h index 41fee2704e..9bb5654bed 100644 --- a/addins/cvwsoc/litedram/genesys2soc/include/generated/soc.h +++ b/addins/cvwsoc/litedram/genesys2soc/include/generated/soc.h @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by LiteX (b3d0f0260) on 2026-03-21 22:19:06 +// Auto-generated by LiteX (777d97377) on 2026-06-22 19:46:31 //-------------------------------------------------------------------------------- #ifndef __GENERATED_SOC_H #define __GENERATED_SOC_H diff --git a/addins/cvwsoc/litedram/genesys2w32soc/include/generated/csr.h b/addins/cvwsoc/litedram/genesys2w32soc/include/generated/csr.h index 03adde8619..382374ad5e 100644 --- a/addins/cvwsoc/litedram/genesys2w32soc/include/generated/csr.h +++ b/addins/cvwsoc/litedram/genesys2w32soc/include/generated/csr.h @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by LiteX (777d97377) on 2026-06-09 14:12:28 +// Auto-generated by LiteX (777d97377) on 2026-06-22 19:53:44 //-------------------------------------------------------------------------------- //-------------------------------------------------------------------------------- diff --git a/addins/cvwsoc/litedram/genesys2w32soc/include/generated/git.h b/addins/cvwsoc/litedram/genesys2w32soc/include/generated/git.h index 7fd9c2e1f8..7264b59dbb 100644 --- a/addins/cvwsoc/litedram/genesys2w32soc/include/generated/git.h +++ b/addins/cvwsoc/litedram/genesys2w32soc/include/generated/git.h @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by LiteX (777d97377) on 2026-06-09 14:12:28 +// Auto-generated by LiteX (777d97377) on 2026-06-22 19:53:44 //-------------------------------------------------------------------------------- #ifndef __GENERATED_GIT_H #define __GENERATED_GIT_H diff --git a/addins/cvwsoc/litedram/genesys2w32soc/include/generated/mem.h b/addins/cvwsoc/litedram/genesys2w32soc/include/generated/mem.h index 02d3960636..38f628be6a 100644 --- a/addins/cvwsoc/litedram/genesys2w32soc/include/generated/mem.h +++ b/addins/cvwsoc/litedram/genesys2w32soc/include/generated/mem.h @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by LiteX (777d97377) on 2026-06-09 14:12:28 +// Auto-generated by LiteX (777d97377) on 2026-06-22 19:53:44 //-------------------------------------------------------------------------------- #ifndef __GENERATED_MEM_H #define __GENERATED_MEM_H diff --git a/addins/cvwsoc/litedram/genesys2w32soc/include/generated/soc.h b/addins/cvwsoc/litedram/genesys2w32soc/include/generated/soc.h index 24cd903c3e..7d972d1714 100644 --- a/addins/cvwsoc/litedram/genesys2w32soc/include/generated/soc.h +++ b/addins/cvwsoc/litedram/genesys2w32soc/include/generated/soc.h @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by LiteX (777d97377) on 2026-06-09 14:12:28 +// Auto-generated by LiteX (777d97377) on 2026-06-22 19:53:44 //-------------------------------------------------------------------------------- #ifndef __GENERATED_SOC_H #define __GENERATED_SOC_H diff --git a/addins/cvwsoc/litedram/litedram_genesys2_fixed.v b/addins/cvwsoc/litedram/litedram_genesys2.v similarity index 99% rename from addins/cvwsoc/litedram/litedram_genesys2_fixed.v rename to addins/cvwsoc/litedram/litedram_genesys2.v index 3f11d70df6..3ae487275c 100644 --- a/addins/cvwsoc/litedram/litedram_genesys2_fixed.v +++ b/addins/cvwsoc/litedram/litedram_genesys2.v @@ -6,15 +6,13 @@ // Build your hardware, easily! // https://github.com/enjoy-digital/litex // -// Filename : litedram_genesys2_v6.v +// Filename : litedram_genesys2.v // Top : LiteDRAMCore // Device : // Hierarchy : disabled // LiteX sha1 : 777d97377 -// Date : 2026-03-30 17:34:48 +// Date : 2026-06-22 19:46:31 //------------------------------------------------------------------------------ -// Generated from https://github.com/juanschroeder/litedram.git, branch 'wbuf_fix' -// Config vs default Genesys 2: AXI interface instead of Wishbone/Native. `timescale 1ns / 1ps @@ -22,7 +20,7 @@ // Module //------------------------------------------------------------------------------ -module litedram_genesys2_fixed ( +module litedram_genesys2 ( input wire clk, output wire [14:0] ddram_a, output wire [2:0] ddram_ba, @@ -46,24 +44,24 @@ module litedram_genesys2_fixed ( output wire user_clk, input wire [29:0] user_port_axi_0_araddr, input wire [1:0] user_port_axi_0_arburst, - input wire [3:0] user_port_axi_0_arid, + input wire [4:0] user_port_axi_0_arid, input wire [7:0] user_port_axi_0_arlen, output wire user_port_axi_0_arready, input wire [2:0] user_port_axi_0_arsize, input wire user_port_axi_0_arvalid, input wire [29:0] user_port_axi_0_awaddr, input wire [1:0] user_port_axi_0_awburst, - input wire [3:0] user_port_axi_0_awid, + input wire [4:0] user_port_axi_0_awid, input wire [7:0] user_port_axi_0_awlen, output wire user_port_axi_0_awready, input wire [2:0] user_port_axi_0_awsize, input wire user_port_axi_0_awvalid, - output wire [3:0] user_port_axi_0_bid, + output wire [4:0] user_port_axi_0_bid, input wire user_port_axi_0_bready, output wire [1:0] user_port_axi_0_bresp, output wire user_port_axi_0_bvalid, output wire [63:0] user_port_axi_0_rdata, - output wire [3:0] user_port_axi_0_rid, + output wire [4:0] user_port_axi_0_rid, output wire user_port_axi_0_rlast, input wire user_port_axi_0_rready, output wire [1:0] user_port_axi_0_rresp, @@ -194,7 +192,6 @@ LiteDRAMCore │ ├── bitslip_71 (BitSlip) [Gen] │ ├── tappeddelayline_2 (TappedDelayLine) [Gen] │ ├── tappeddelayline_3 (TappedDelayLine) [Gen] -│ ├── [BB:ISERDESE2] │ ├── [BB:ODELAYE2] │ ├── [BB:IDELAYE2] │ ├── [BB:IOBUF] @@ -265,11 +262,6 @@ LiteDRAMCore │ ├── [BB:IOBUF] │ ├── [BB:OSERDESE2] │ ├── [BB:ISERDESE2] -│ ├── [BB:ODELAYE2] -│ ├── [BB:IDELAYE2] -│ ├── [BB:IOBUF] -│ ├── [BB:OSERDESE2] -│ ├── [BB:OSERDESE2] │ ├── [BB:ISERDESE2] │ ├── [BB:ODELAYE2] │ ├── [BB:IDELAYE2] @@ -336,17 +328,6 @@ LiteDRAMCore │ ├── [BB:IOBUF] │ ├── [BB:OSERDESE2] │ ├── [BB:ODELAYE2] -│ ├── [BB:OBUFDS] -│ ├── [BB:OSERDESE2] -│ ├── [BB:ODELAYE2] -│ ├── [BB:OSERDESE2] -│ ├── [BB:ODELAYE2] -│ ├── [BB:OSERDESE2] -│ ├── [BB:ODELAYE2] -│ ├── [BB:OSERDESE2] -│ ├── [BB:ODELAYE2] -│ ├── [BB:OSERDESE2] -│ ├── [BB:ODELAYE2] │ ├── [BB:OSERDESE2] │ ├── [BB:ODELAYE2] │ ├── [BB:OSERDESE2] @@ -387,6 +368,7 @@ LiteDRAMCore │ ├── [BB:ODELAYE2] │ ├── [BB:OSERDESE2] │ ├── [BB:ODELAYE2] +│ ├── [BB:IOBUFDS] │ ├── [BB:OSERDESE2] │ ├── [BB:ODELAYE2] │ ├── [BB:IOBUFDS] @@ -398,7 +380,6 @@ LiteDRAMCore │ ├── [BB:IOBUFDS] │ ├── [BB:OSERDESE2] │ ├── [BB:ODELAYE2] -│ ├── [BB:IOBUFDS] │ ├── [BB:OSERDESE2] │ ├── [BB:ODELAYE2] │ ├── [BB:OSERDESE2] @@ -406,7 +387,10 @@ LiteDRAMCore │ ├── [BB:OSERDESE2] │ ├── [BB:ODELAYE2] │ ├── [BB:OSERDESE2] +│ ├── [BB:ISERDESE2] │ ├── [BB:ODELAYE2] +│ ├── [BB:IDELAYE2] +│ ├── [BB:IOBUF] │ ├── [BB:OSERDESE2] │ ├── [BB:ISERDESE2] │ ├── [BB:ODELAYE2] @@ -426,7 +410,21 @@ LiteDRAMCore │ ├── [BB:ISERDESE2] │ ├── [BB:ODELAYE2] │ ├── [BB:IDELAYE2] -│ └── [BB:IOBUF] +│ ├── [BB:IOBUF] +│ ├── [BB:OSERDESE2] +│ ├── [BB:OSERDESE2] +│ ├── [BB:ODELAYE2] +│ ├── [BB:OBUFDS] +│ ├── [BB:OSERDESE2] +│ ├── [BB:ODELAYE2] +│ ├── [BB:OSERDESE2] +│ ├── [BB:ODELAYE2] +│ ├── [BB:OSERDESE2] +│ ├── [BB:ODELAYE2] +│ ├── [BB:OSERDESE2] +│ ├── [BB:ODELAYE2] +│ ├── [BB:OSERDESE2] +│ └── [BB:ODELAYE2] ├── sdram (LiteDRAMCore) │ ├── dfii (DFIInjector) │ │ ├── pi0 (PhaseInjector) @@ -995,7 +993,7 @@ wire iodelay_rst; reg main_ar_first = 1'd0; reg main_ar_last = 1'd0; reg main_ar_param_dest = 1'd0; -wire [3:0] main_ar_param_id; +wire [4:0] main_ar_param_id; reg main_ar_param_user = 1'd0; wire [29:0] main_ar_payload_addr; wire [1:0] main_ar_payload_burst; @@ -1011,7 +1009,7 @@ wire main_ar_valid; reg main_aw_first = 1'd0; reg main_aw_last = 1'd0; reg main_aw_param_dest = 1'd0; -wire [3:0] main_aw_param_id; +wire [4:0] main_aw_param_id; reg main_aw_param_user = 1'd0; wire [29:0] main_aw_payload_addr; wire [1:0] main_aw_payload_burst; @@ -1026,10 +1024,10 @@ wire main_aw_ready; wire main_aw_valid; wire main_b_first; wire main_b_last; -(* mark_debug = "true" *) wire [3:0] main_b_param_id; -(* mark_debug = "true" *) wire [1:0] main_b_payload_resp; -(* mark_debug = "true" *) wire main_b_ready; -(* mark_debug = "true" *) wire main_b_valid; +wire [4:0] main_b_param_id; +wire [1:0] main_b_payload_resp; +wire main_b_ready; +wire main_b_valid; reg main_bankmachine0_auto_precharge = 1'd0; reg [14:0] main_bankmachine0_cmd_payload_a = 15'd0; wire [2:0] main_bankmachine0_cmd_payload_ba; @@ -2746,13 +2744,13 @@ wire main_litedramnativeportconverter_addr_changed; reg [26:0] main_litedramnativeportconverter_cmd_addr = 27'd0; reg [26:0] main_litedramnativeportconverter_cmd_addr_litedramcore_next_value0 = 27'd0; reg main_litedramnativeportconverter_cmd_addr_litedramcore_next_value_ce0 = 1'd0; -(* mark_debug = "true" *) reg main_litedramnativeportconverter_cmd_last = 1'd0; +reg main_litedramnativeportconverter_cmd_last = 1'd0; reg main_litedramnativeportconverter_cmd_last_litedramcore_next_value2 = 1'd0; reg main_litedramnativeportconverter_cmd_last_litedramcore_next_value_ce2 = 1'd0; -(* mark_debug = "true" *) reg main_litedramnativeportconverter_cmd_we = 1'd0; +reg main_litedramnativeportconverter_cmd_we = 1'd0; reg main_litedramnativeportconverter_cmd_we_litedramcore_next_value1 = 1'd0; reg main_litedramnativeportconverter_cmd_we_litedramcore_next_value_ce1 = 1'd0; -(* mark_debug = "true" *) wire main_litedramnativeportconverter_next_cmd; +wire main_litedramnativeportconverter_next_cmd; reg [3:0] main_litedramnativeportconverter_port_to = 4'd0; reg [3:0] main_litedramnativeportconverter_port_to_litedramcore_next_value3 = 4'd0; reg main_litedramnativeportconverter_port_to_litedramcore_next_value_ce3 = 1'd0; @@ -2848,7 +2846,7 @@ reg main_litedramnativeportconverter_wdata_buffer_pipe_valid_source_la reg [255:0] main_litedramnativeportconverter_wdata_buffer_pipe_valid_source_payload_data = 256'd0; reg [31:0] main_litedramnativeportconverter_wdata_buffer_pipe_valid_source_payload_we = 32'd0; wire main_litedramnativeportconverter_wdata_buffer_pipe_valid_source_ready; -(* mark_debug = "true" *) reg main_litedramnativeportconverter_wdata_buffer_pipe_valid_source_valid = 1'd0; +reg main_litedramnativeportconverter_wdata_buffer_pipe_valid_source_valid = 1'd0; reg main_litedramnativeportconverter_wdata_buffer_sink_sink_first = 1'd0; reg main_litedramnativeportconverter_wdata_buffer_sink_sink_last = 1'd0; wire [255:0] main_litedramnativeportconverter_wdata_buffer_sink_sink_payload_data; @@ -2861,8 +2859,8 @@ wire [255:0] main_litedramnativeportconverter_wdata_buffer_source_source_payloa wire [31:0] main_litedramnativeportconverter_wdata_buffer_source_source_payload_we; wire main_litedramnativeportconverter_wdata_buffer_source_source_ready; wire main_litedramnativeportconverter_wdata_buffer_source_source_valid; -(* mark_debug = "true" *) reg [3:0] main_litedramnativeportconverter_wdata_chunk = 4'd1; -(* mark_debug = "true" *) wire main_litedramnativeportconverter_wdata_chunk_valid; +reg [3:0] main_litedramnativeportconverter_wdata_chunk = 4'd1; +wire main_litedramnativeportconverter_wdata_chunk_valid; reg [1:0] main_litedramnativeportconverter_wdata_converter_converter_demux = 2'd0; wire main_litedramnativeportconverter_wdata_converter_converter_load_part; wire main_litedramnativeportconverter_wdata_converter_converter_sink_first; @@ -2882,7 +2880,7 @@ reg main_litedramnativeportconverter_wdata_converter_sink_last = 1'd0; reg [63:0] main_litedramnativeportconverter_wdata_converter_sink_payload_data = 64'd0; reg [7:0] main_litedramnativeportconverter_wdata_converter_sink_payload_we = 8'd0; wire main_litedramnativeportconverter_wdata_converter_sink_ready; -(* mark_debug = "true" *) reg main_litedramnativeportconverter_wdata_converter_sink_valid = 1'd0; +reg main_litedramnativeportconverter_wdata_converter_sink_valid = 1'd0; wire main_litedramnativeportconverter_wdata_converter_source_first; wire main_litedramnativeportconverter_wdata_converter_source_last; reg [255:0] main_litedramnativeportconverter_wdata_converter_source_payload_data = 256'd0; @@ -2904,7 +2902,7 @@ wire main_litedramnativeportconverter_wdata_fifo_fifo_out_first; wire main_litedramnativeportconverter_wdata_fifo_fifo_out_last; wire [63:0] main_litedramnativeportconverter_wdata_fifo_fifo_out_payload_data; wire [7:0] main_litedramnativeportconverter_wdata_fifo_fifo_out_payload_we; -(* mark_debug = "true" *) reg [1:0] main_litedramnativeportconverter_wdata_fifo_level = 2'd0; +reg [1:0] main_litedramnativeportconverter_wdata_fifo_level = 2'd0; reg [1:0] main_litedramnativeportconverter_wdata_fifo_produce = 2'd0; wire [1:0] main_litedramnativeportconverter_wdata_fifo_rdport_adr; wire [73:0] main_litedramnativeportconverter_wdata_fifo_rdport_dat_r; @@ -2924,13 +2922,13 @@ wire main_litedramnativeportconverter_wdata_fifo_source_valid; wire [73:0] main_litedramnativeportconverter_wdata_fifo_syncfifo_din; wire [73:0] main_litedramnativeportconverter_wdata_fifo_syncfifo_dout; wire main_litedramnativeportconverter_wdata_fifo_syncfifo_re; -(* mark_debug = "true" *) wire main_litedramnativeportconverter_wdata_fifo_syncfifo_readable; +wire main_litedramnativeportconverter_wdata_fifo_syncfifo_readable; wire main_litedramnativeportconverter_wdata_fifo_syncfifo_we; -(* mark_debug = "true" *) wire main_litedramnativeportconverter_wdata_fifo_syncfifo_writable; +wire main_litedramnativeportconverter_wdata_fifo_syncfifo_writable; reg [1:0] main_litedramnativeportconverter_wdata_fifo_wrport_adr = 2'd0; wire [73:0] main_litedramnativeportconverter_wdata_fifo_wrport_dat_w; wire main_litedramnativeportconverter_wdata_fifo_wrport_we; -(* mark_debug = "true" *) wire main_litedramnativeportconverter_wdata_finished; +wire main_litedramnativeportconverter_wdata_finished; reg [31:0] main_litedramnativeportconverter_wdata_sel = 32'd0; wire main_locked; reg main_master_p0_act_n = 1'd1; @@ -2999,11 +2997,11 @@ reg main_master_p3_wrdata_en = 1'd0; reg [7:0] main_master_p3_wrdata_mask = 8'd0; wire main_max_time0; wire main_max_time1; -(* mark_debug = "true" *) reg main_new_port_cmd_last = 1'd0; -(* mark_debug = "true" *) reg [26:0] main_new_port_cmd_payload_addr = 27'd0; -(* mark_debug = "true" *) reg main_new_port_cmd_payload_we = 1'd0; -(* mark_debug = "true" *) reg main_new_port_cmd_ready = 1'd0; -(* mark_debug = "true" *) reg main_new_port_cmd_valid = 1'd0; +reg main_new_port_cmd_last = 1'd0; +reg [26:0] main_new_port_cmd_payload_addr = 27'd0; +reg main_new_port_cmd_payload_we = 1'd0; +reg main_new_port_cmd_ready = 1'd0; +reg main_new_port_cmd_valid = 1'd0; reg main_new_port_flush = 1'd0; reg main_new_port_rdata_first = 1'd0; reg main_new_port_rdata_last = 1'd0; @@ -3011,11 +3009,11 @@ reg [63:0] main_new_port_rdata_payload_data = 64'd0; wire main_new_port_rdata_ready; reg main_new_port_rdata_valid = 1'd0; reg main_new_port_wdata_first = 1'd0; -(* mark_debug = "true" *) (* keep = "true" *) reg main_new_port_wdata_last = 1'd0; +reg main_new_port_wdata_last = 1'd0; wire [63:0] main_new_port_wdata_payload_data; wire [7:0] main_new_port_wdata_payload_we; -(* mark_debug = "true" *) wire main_new_port_wdata_ready; -(* mark_debug = "true" *) wire main_new_port_wdata_valid; +wire main_new_port_wdata_ready; +wire main_new_port_wdata_valid; reg [14:0] main_nop_a = 15'd0; reg [2:0] main_nop_ba = 3'd0; wire main_odt; @@ -3111,21 +3109,21 @@ reg [63:0] main_phaseinjector3_rddata_status = 64'd0; wire main_phaseinjector3_rddata_we; reg main_phaseinjector3_wrdata_re = 1'd0; reg [63:0] main_phaseinjector3_wrdata_storage = 64'd0; -(* mark_debug = "true" *) reg [24:0] main_port_cmd_payload_addr = 25'd0; -(* mark_debug = "true" *) reg main_port_cmd_payload_we = 1'd0; -(* mark_debug = "true" *) wire main_port_cmd_ready; -(* mark_debug = "true" *) reg main_port_cmd_valid = 1'd0; +reg [24:0] main_port_cmd_payload_addr = 25'd0; +reg main_port_cmd_payload_we = 1'd0; +wire main_port_cmd_ready; +reg main_port_cmd_valid = 1'd0; reg main_port_rdata_first = 1'd0; reg main_port_rdata_last = 1'd0; wire [255:0] main_port_rdata_payload_data; wire main_port_rdata_ready; wire main_port_rdata_valid; wire main_port_wdata_first; -(* mark_debug = "true" *) wire main_port_wdata_last; +wire main_port_wdata_last; wire [255:0] main_port_wdata_payload_data; wire [31:0] main_port_wdata_payload_we; -(* mark_debug = "true" *) wire main_port_wdata_ready; -(* mark_debug = "true" *) wire main_port_wdata_valid; +wire main_port_wdata_ready; +wire main_port_wdata_valid; reg main_postponer_count = 1'd0; wire main_postponer_req_i; reg main_postponer_req_o = 1'd0; @@ -3133,7 +3131,7 @@ reg main_power_down = 1'd0; wire main_r_first; wire main_r_last; wire main_r_param_dest; -wire [3:0] main_r_param_id; +wire [4:0] main_r_param_id; wire main_r_param_user; wire [63:0] main_r_payload_data; reg [1:0] main_r_payload_resp = 2'd0; @@ -3143,7 +3141,7 @@ wire main_ras_allowed; reg main_re = 1'd0; wire main_read_ar_first; wire main_read_ar_last; -wire [3:0] main_read_ar_param_id; +wire [4:0] main_read_ar_param_id; wire [29:0] main_read_ar_payload_addr; reg main_read_ar_ready = 1'd0; wire main_read_ar_valid; @@ -3159,38 +3157,38 @@ reg [3:0] main_read_id_buffer_consume = 4'd0; wire main_read_id_buffer_do_read; wire main_read_id_buffer_fifo_in_first; wire main_read_id_buffer_fifo_in_last; -wire [3:0] main_read_id_buffer_fifo_in_payload_id; +wire [4:0] main_read_id_buffer_fifo_in_payload_id; wire main_read_id_buffer_fifo_out_first; wire main_read_id_buffer_fifo_out_last; -wire [3:0] main_read_id_buffer_fifo_out_payload_id; +wire [4:0] main_read_id_buffer_fifo_out_payload_id; reg [4:0] main_read_id_buffer_level = 5'd0; reg [3:0] main_read_id_buffer_produce = 4'd0; wire [3:0] main_read_id_buffer_rdport_adr; -wire [5:0] main_read_id_buffer_rdport_dat_r; +wire [6:0] main_read_id_buffer_rdport_dat_r; reg main_read_id_buffer_replace = 1'd0; reg main_read_id_buffer_sink_first = 1'd0; wire main_read_id_buffer_sink_last; -wire [3:0] main_read_id_buffer_sink_payload_id; +wire [4:0] main_read_id_buffer_sink_payload_id; wire main_read_id_buffer_sink_ready; wire main_read_id_buffer_sink_valid; wire main_read_id_buffer_source_first; wire main_read_id_buffer_source_last; -wire [3:0] main_read_id_buffer_source_payload_id; +wire [4:0] main_read_id_buffer_source_payload_id; wire main_read_id_buffer_source_ready; wire main_read_id_buffer_source_valid; -wire [5:0] main_read_id_buffer_syncfifo_din; -wire [5:0] main_read_id_buffer_syncfifo_dout; +wire [6:0] main_read_id_buffer_syncfifo_din; +wire [6:0] main_read_id_buffer_syncfifo_dout; wire main_read_id_buffer_syncfifo_re; wire main_read_id_buffer_syncfifo_readable; wire main_read_id_buffer_syncfifo_we; wire main_read_id_buffer_syncfifo_writable; reg [3:0] main_read_id_buffer_wrport_adr = 4'd0; -wire [5:0] main_read_id_buffer_wrport_dat_w; +wire [6:0] main_read_id_buffer_wrport_dat_w; wire main_read_id_buffer_wrport_we; wire main_read_pipe_valid_sink_first; wire main_read_pipe_valid_sink_last; wire main_read_pipe_valid_sink_param_dest; -wire [3:0] main_read_pipe_valid_sink_param_id; +wire [4:0] main_read_pipe_valid_sink_param_id; wire main_read_pipe_valid_sink_param_user; wire [29:0] main_read_pipe_valid_sink_payload_addr; wire [1:0] main_read_pipe_valid_sink_payload_burst; @@ -3206,7 +3204,7 @@ wire main_read_pipe_valid_sink_valid; reg main_read_pipe_valid_source_first = 1'd0; reg main_read_pipe_valid_source_last = 1'd0; reg main_read_pipe_valid_source_param_dest = 1'd0; -reg [3:0] main_read_pipe_valid_source_param_id = 4'd0; +reg [4:0] main_read_pipe_valid_source_param_id = 5'd0; reg main_read_pipe_valid_source_param_user = 1'd0; reg [29:0] main_read_pipe_valid_source_payload_addr = 30'd0; reg [1:0] main_read_pipe_valid_source_payload_burst = 2'd0; @@ -3225,14 +3223,14 @@ wire main_read_r_buffer_do_read; wire main_read_r_buffer_fifo_in_first; wire main_read_r_buffer_fifo_in_last; wire main_read_r_buffer_fifo_in_param_dest; -wire [3:0] main_read_r_buffer_fifo_in_param_id; +wire [4:0] main_read_r_buffer_fifo_in_param_id; wire main_read_r_buffer_fifo_in_param_user; wire [63:0] main_read_r_buffer_fifo_in_payload_data; wire [1:0] main_read_r_buffer_fifo_in_payload_resp; wire main_read_r_buffer_fifo_out_first; wire main_read_r_buffer_fifo_out_last; wire main_read_r_buffer_fifo_out_param_dest; -wire [3:0] main_read_r_buffer_fifo_out_param_id; +wire [4:0] main_read_r_buffer_fifo_out_param_id; wire main_read_r_buffer_fifo_out_param_user; wire [63:0] main_read_r_buffer_fifo_out_payload_data; wire [1:0] main_read_r_buffer_fifo_out_payload_resp; @@ -3242,7 +3240,7 @@ reg [4:0] main_read_r_buffer_level2 = 5'd0; reg [3:0] main_read_r_buffer_produce = 4'd0; wire main_read_r_buffer_queue; wire [3:0] main_read_r_buffer_rdport_adr; -wire [73:0] main_read_r_buffer_rdport_dat_r; +wire [74:0] main_read_r_buffer_rdport_dat_r; wire main_read_r_buffer_rdport_re; wire main_read_r_buffer_re; reg main_read_r_buffer_readable = 1'd0; @@ -3250,7 +3248,7 @@ reg main_read_r_buffer_replace = 1'd0; wire main_read_r_buffer_sink_first; wire main_read_r_buffer_sink_last; reg main_read_r_buffer_sink_param_dest = 1'd0; -reg [3:0] main_read_r_buffer_sink_param_id = 4'd0; +reg [4:0] main_read_r_buffer_sink_param_id = 5'd0; reg main_read_r_buffer_sink_param_user = 1'd0; wire [63:0] main_read_r_buffer_sink_payload_data; reg [1:0] main_read_r_buffer_sink_payload_resp = 2'd0; @@ -3259,25 +3257,25 @@ wire main_read_r_buffer_sink_valid; wire main_read_r_buffer_source_first; wire main_read_r_buffer_source_last; wire main_read_r_buffer_source_param_dest; -wire [3:0] main_read_r_buffer_source_param_id; +wire [4:0] main_read_r_buffer_source_param_id; wire main_read_r_buffer_source_param_user; wire [63:0] main_read_r_buffer_source_payload_data; wire [1:0] main_read_r_buffer_source_payload_resp; wire main_read_r_buffer_source_ready; wire main_read_r_buffer_source_valid; -wire [73:0] main_read_r_buffer_syncfifo_din; -wire [73:0] main_read_r_buffer_syncfifo_dout; +wire [74:0] main_read_r_buffer_syncfifo_din; +wire [74:0] main_read_r_buffer_syncfifo_dout; wire main_read_r_buffer_syncfifo_re; wire main_read_r_buffer_syncfifo_readable; wire main_read_r_buffer_syncfifo_we; wire main_read_r_buffer_syncfifo_writable; reg [3:0] main_read_r_buffer_wrport_adr = 4'd0; -wire [73:0] main_read_r_buffer_wrport_dat_w; +wire [74:0] main_read_r_buffer_wrport_dat_w; wire main_read_r_buffer_wrport_we; wire main_read_sink_sink_first; wire main_read_sink_sink_last; wire main_read_sink_sink_param_dest; -wire [3:0] main_read_sink_sink_param_id; +wire [4:0] main_read_sink_sink_param_id; wire main_read_sink_sink_param_user; wire [29:0] main_read_sink_sink_payload_addr; wire [1:0] main_read_sink_sink_payload_burst; @@ -3293,7 +3291,7 @@ wire main_read_sink_sink_valid; wire main_read_source_source_first; wire main_read_source_source_last; wire main_read_source_source_param_dest; -wire [3:0] main_read_source_source_param_id; +wire [4:0] main_read_source_source_param_id; wire main_read_source_source_param_user; wire [29:0] main_read_source_source_payload_addr; wire [1:0] main_read_source_source_payload_burst; @@ -3420,16 +3418,16 @@ reg [2:0] main_twtrcon_count = 3'd0; (* dont_touch = "true" *) reg main_twtrcon_ready = 1'd0; wire main_twtrcon_valid; -(* mark_debug = "true" *) reg main_user_enable = 1'd0; +reg main_user_enable = 1'd0; reg main_w_first = 1'd0; -(* mark_debug = "true" *) wire main_w_last; +wire main_w_last; reg main_w_param_dest = 1'd0; reg main_w_param_id = 1'd0; reg main_w_param_user = 1'd0; wire [63:0] main_w_payload_data; wire [7:0] main_w_payload_strb; -(* mark_debug = "true" *) reg main_w_ready = 1'd0; -(* mark_debug = "true" *) wire main_w_valid; +reg main_w_ready = 1'd0; +wire main_w_valid; wire main_wants_refresh; wire main_wants_zqcs; wire main_wb_bus_ack; @@ -3444,56 +3442,56 @@ wire [3:0] main_wb_bus_sel; wire main_wb_bus_stb; wire main_wb_bus_we; wire main_write_available; -(* mark_debug = "true" *) wire main_write_aw_first; -(* mark_debug = "true" *) wire main_write_aw_last; -wire [3:0] main_write_aw_param_id; +wire main_write_aw_first; +wire main_write_aw_last; +wire [4:0] main_write_aw_param_id; wire [29:0] main_write_aw_payload_addr; reg main_write_aw_ready = 1'd0; -(* mark_debug = "true" *) wire main_write_aw_valid; +wire main_write_aw_valid; reg main_write_axi_w_connect = 1'd1; -(* mark_debug = "true" *) reg [7:0] main_write_beat_count = 8'd0; +reg [7:0] main_write_beat_count = 8'd0; reg signed [12:0] main_write_beat_offset = 13'd0; wire [11:0] main_write_beat_size; wire [11:0] main_write_beat_wrap; -(* mark_debug = "true" *) wire main_write_can_write; +wire main_write_can_write; wire main_write_cmd_grant; wire main_write_cmd_request; reg [3:0] main_write_id_buffer_consume = 4'd0; wire main_write_id_buffer_do_read; wire main_write_id_buffer_fifo_in_first; wire main_write_id_buffer_fifo_in_last; -wire [3:0] main_write_id_buffer_fifo_in_payload_id; +wire [4:0] main_write_id_buffer_fifo_in_payload_id; wire main_write_id_buffer_fifo_out_first; wire main_write_id_buffer_fifo_out_last; -wire [3:0] main_write_id_buffer_fifo_out_payload_id; +wire [4:0] main_write_id_buffer_fifo_out_payload_id; reg [4:0] main_write_id_buffer_level = 5'd0; reg [3:0] main_write_id_buffer_produce = 4'd0; wire [3:0] main_write_id_buffer_rdport_adr; -wire [5:0] main_write_id_buffer_rdport_dat_r; +wire [6:0] main_write_id_buffer_rdport_dat_r; reg main_write_id_buffer_replace = 1'd0; reg main_write_id_buffer_sink_first = 1'd0; reg main_write_id_buffer_sink_last = 1'd0; -wire [3:0] main_write_id_buffer_sink_payload_id; +wire [4:0] main_write_id_buffer_sink_payload_id; wire main_write_id_buffer_sink_ready; wire main_write_id_buffer_sink_valid; wire main_write_id_buffer_source_first; wire main_write_id_buffer_source_last; -(* mark_debug = "true" *) wire [3:0] main_write_id_buffer_source_payload_id; -(* mark_debug = "true" *) reg main_write_id_buffer_source_ready = 1'd0; -(* mark_debug = "true" *) wire main_write_id_buffer_source_valid; -wire [5:0] main_write_id_buffer_syncfifo_din; -wire [5:0] main_write_id_buffer_syncfifo_dout; +wire [4:0] main_write_id_buffer_source_payload_id; +reg main_write_id_buffer_source_ready = 1'd0; +wire main_write_id_buffer_source_valid; +wire [6:0] main_write_id_buffer_syncfifo_din; +wire [6:0] main_write_id_buffer_syncfifo_dout; wire main_write_id_buffer_syncfifo_re; wire main_write_id_buffer_syncfifo_readable; wire main_write_id_buffer_syncfifo_we; wire main_write_id_buffer_syncfifo_writable; reg [3:0] main_write_id_buffer_wrport_adr = 4'd0; -wire [5:0] main_write_id_buffer_wrport_dat_w; +wire [6:0] main_write_id_buffer_wrport_dat_w; wire main_write_id_buffer_wrport_we; wire main_write_pipe_valid_sink_first; wire main_write_pipe_valid_sink_last; wire main_write_pipe_valid_sink_param_dest; -wire [3:0] main_write_pipe_valid_sink_param_id; +wire [4:0] main_write_pipe_valid_sink_param_id; wire main_write_pipe_valid_sink_param_user; wire [29:0] main_write_pipe_valid_sink_payload_addr; wire [1:0] main_write_pipe_valid_sink_payload_burst; @@ -3509,7 +3507,7 @@ wire main_write_pipe_valid_sink_valid; reg main_write_pipe_valid_source_first = 1'd0; reg main_write_pipe_valid_source_last = 1'd0; reg main_write_pipe_valid_source_param_dest = 1'd0; -reg [3:0] main_write_pipe_valid_source_param_id = 4'd0; +reg [4:0] main_write_pipe_valid_source_param_id = 5'd0; reg main_write_pipe_valid_source_param_user = 1'd0; reg [29:0] main_write_pipe_valid_source_payload_addr = 30'd0; reg [1:0] main_write_pipe_valid_source_payload_burst = 2'd0; @@ -3526,42 +3524,42 @@ reg [3:0] main_write_resp_buffer_consume = 4'd0; wire main_write_resp_buffer_do_read; wire main_write_resp_buffer_fifo_in_first; wire main_write_resp_buffer_fifo_in_last; -wire [3:0] main_write_resp_buffer_fifo_in_payload_id; +wire [4:0] main_write_resp_buffer_fifo_in_payload_id; wire [1:0] main_write_resp_buffer_fifo_in_payload_resp; wire main_write_resp_buffer_fifo_out_first; wire main_write_resp_buffer_fifo_out_last; -wire [3:0] main_write_resp_buffer_fifo_out_payload_id; +wire [4:0] main_write_resp_buffer_fifo_out_payload_id; wire [1:0] main_write_resp_buffer_fifo_out_payload_resp; reg [4:0] main_write_resp_buffer_level = 5'd0; reg [3:0] main_write_resp_buffer_produce = 4'd0; wire [3:0] main_write_resp_buffer_rdport_adr; -wire [7:0] main_write_resp_buffer_rdport_dat_r; +wire [8:0] main_write_resp_buffer_rdport_dat_r; reg main_write_resp_buffer_replace = 1'd0; reg main_write_resp_buffer_sink_first = 1'd0; reg main_write_resp_buffer_sink_last = 1'd0; -(* mark_debug = "true" *) reg [3:0] main_write_resp_buffer_sink_payload_id = 4'd0; -(* mark_debug = "true" *) reg [1:0] main_write_resp_buffer_sink_payload_resp = 2'd0; +reg [4:0] main_write_resp_buffer_sink_payload_id = 5'd0; +reg [1:0] main_write_resp_buffer_sink_payload_resp = 2'd0; wire main_write_resp_buffer_sink_ready; -(* mark_debug = "true" *) reg main_write_resp_buffer_sink_valid = 1'd0; +reg main_write_resp_buffer_sink_valid = 1'd0; wire main_write_resp_buffer_source_first; wire main_write_resp_buffer_source_last; -(* mark_debug = "true" *) wire [3:0] main_write_resp_buffer_source_payload_id; -(* mark_debug = "true" *) wire [1:0] main_write_resp_buffer_source_payload_resp; -(* mark_debug = "true" *) wire main_write_resp_buffer_source_ready; -(* mark_debug = "true" *) wire main_write_resp_buffer_source_valid; -wire [7:0] main_write_resp_buffer_syncfifo_din; -wire [7:0] main_write_resp_buffer_syncfifo_dout; +wire [4:0] main_write_resp_buffer_source_payload_id; +wire [1:0] main_write_resp_buffer_source_payload_resp; +wire main_write_resp_buffer_source_ready; +wire main_write_resp_buffer_source_valid; +wire [8:0] main_write_resp_buffer_syncfifo_din; +wire [8:0] main_write_resp_buffer_syncfifo_dout; wire main_write_resp_buffer_syncfifo_re; wire main_write_resp_buffer_syncfifo_readable; wire main_write_resp_buffer_syncfifo_we; wire main_write_resp_buffer_syncfifo_writable; reg [3:0] main_write_resp_buffer_wrport_adr = 4'd0; -wire [7:0] main_write_resp_buffer_wrport_dat_w; +wire [8:0] main_write_resp_buffer_wrport_dat_w; wire main_write_resp_buffer_wrport_we; wire main_write_sink_sink_first; wire main_write_sink_sink_last; wire main_write_sink_sink_param_dest; -wire [3:0] main_write_sink_sink_param_id; +wire [4:0] main_write_sink_sink_param_id; wire main_write_sink_sink_param_user; wire [29:0] main_write_sink_sink_payload_addr; wire [1:0] main_write_sink_sink_payload_burst; @@ -3577,7 +3575,7 @@ wire main_write_sink_sink_valid; wire main_write_source_source_first; wire main_write_source_source_last; wire main_write_source_source_param_dest; -wire [3:0] main_write_source_source_param_id; +wire [4:0] main_write_source_source_param_id; wire main_write_source_source_param_user; wire [29:0] main_write_source_source_payload_addr; wire [1:0] main_write_source_source_payload_burst; @@ -3594,57 +3592,57 @@ reg [3:0] main_write_w_buffer_consume = 4'd0; wire main_write_w_buffer_dequeue; wire main_write_w_buffer_do_read; wire main_write_w_buffer_fifo_in_first; -(* mark_debug = "true" *) wire main_write_w_buffer_fifo_in_last; +wire main_write_w_buffer_fifo_in_last; wire main_write_w_buffer_fifo_in_param_dest; -wire [3:0] main_write_w_buffer_fifo_in_param_id; +wire [4:0] main_write_w_buffer_fifo_in_param_id; wire main_write_w_buffer_fifo_in_param_user; wire [63:0] main_write_w_buffer_fifo_in_payload_data; wire [7:0] main_write_w_buffer_fifo_in_payload_strb; wire main_write_w_buffer_fifo_out_first; wire main_write_w_buffer_fifo_out_last; wire main_write_w_buffer_fifo_out_param_dest; -wire [3:0] main_write_w_buffer_fifo_out_param_id; +wire [4:0] main_write_w_buffer_fifo_out_param_id; wire main_write_w_buffer_fifo_out_param_user; wire [63:0] main_write_w_buffer_fifo_out_payload_data; wire [7:0] main_write_w_buffer_fifo_out_payload_strb; -(* mark_debug = "true" *) reg [4:0] main_write_w_buffer_level0 = 5'd0; +reg [4:0] main_write_w_buffer_level0 = 5'd0; wire [4:0] main_write_w_buffer_level1; -(* mark_debug = "true" *) reg [4:0] main_write_w_buffer_level2 = 5'd0; +reg [4:0] main_write_w_buffer_level2 = 5'd0; reg [3:0] main_write_w_buffer_produce = 4'd0; wire main_write_w_buffer_queue; wire [3:0] main_write_w_buffer_rdport_adr; -wire [79:0] main_write_w_buffer_rdport_dat_r; +wire [80:0] main_write_w_buffer_rdport_dat_r; wire main_write_w_buffer_rdport_re; wire main_write_w_buffer_re; reg main_write_w_buffer_readable = 1'd0; reg main_write_w_buffer_replace = 1'd0; reg main_write_w_buffer_sink_first = 1'd0; -(* mark_debug = "true" *) reg main_write_w_buffer_sink_last = 1'd0; +reg main_write_w_buffer_sink_last = 1'd0; reg main_write_w_buffer_sink_param_dest = 1'd0; -reg [3:0] main_write_w_buffer_sink_param_id = 4'd0; +reg [4:0] main_write_w_buffer_sink_param_id = 5'd0; reg main_write_w_buffer_sink_param_user = 1'd0; reg [63:0] main_write_w_buffer_sink_payload_data = 64'd0; reg [7:0] main_write_w_buffer_sink_payload_strb = 8'd0; -(* mark_debug = "true" *) wire main_write_w_buffer_sink_ready; -(* mark_debug = "true" *) reg main_write_w_buffer_sink_valid = 1'd0; +wire main_write_w_buffer_sink_ready; +reg main_write_w_buffer_sink_valid = 1'd0; wire main_write_w_buffer_source_first; -(* mark_debug = "true" *) wire main_write_w_buffer_source_last; +wire main_write_w_buffer_source_last; wire main_write_w_buffer_source_param_dest; -wire [3:0] main_write_w_buffer_source_param_id; +wire [4:0] main_write_w_buffer_source_param_id; wire main_write_w_buffer_source_param_user; -(* mark_debug = "true" *) wire [63:0] main_write_w_buffer_source_payload_data; -(* mark_debug = "true" *) wire [7:0] main_write_w_buffer_source_payload_strb; -(* mark_debug = "true" *) wire main_write_w_buffer_source_ready; -(* mark_debug = "true" *) wire main_write_w_buffer_source_valid; -wire [79:0] main_write_w_buffer_syncfifo_din; -wire [79:0] main_write_w_buffer_syncfifo_dout; +wire [63:0] main_write_w_buffer_source_payload_data; +wire [7:0] main_write_w_buffer_source_payload_strb; +wire main_write_w_buffer_source_ready; +wire main_write_w_buffer_source_valid; +wire [80:0] main_write_w_buffer_syncfifo_din; +wire [80:0] main_write_w_buffer_syncfifo_dout; wire main_write_w_buffer_syncfifo_re; wire main_write_w_buffer_syncfifo_readable; wire main_write_w_buffer_syncfifo_we; wire main_write_w_buffer_syncfifo_writable; reg [3:0] main_write_w_buffer_wrport_adr = 4'd0; -wire [79:0] main_write_w_buffer_wrport_dat_w; -(* mark_debug = "true" *) wire main_write_w_buffer_wrport_we; +wire [80:0] main_write_w_buffer_wrport_dat_w; +wire main_write_w_buffer_wrport_we; reg main_zqcs_executer_done = 1'd0; reg main_zqcs_executer_start = 1'd0; reg [4:0] main_zqcs_executer_trigger = 5'd0; @@ -13405,7 +13403,7 @@ always @(*) begin end end always @(*) begin - main_write_resp_buffer_sink_payload_id <= 4'd0; + main_write_resp_buffer_sink_payload_id <= 5'd0; if (((main_write_w_buffer_source_valid & main_write_w_buffer_source_last) & main_write_w_buffer_source_ready)) begin main_write_resp_buffer_sink_payload_id <= main_write_id_buffer_source_payload_id; end @@ -13507,7 +13505,7 @@ always @(*) begin end end always @(*) begin - main_write_w_buffer_sink_param_id <= 4'd0; + main_write_w_buffer_sink_param_id <= 5'd0; if (main_write_axi_w_connect) begin main_write_w_buffer_sink_param_id <= main_w_param_id; end @@ -25233,12 +25231,12 @@ assign main_litedramnativeportconverter_wdata_fifo_rdport_dat_r = storage_9[main //------------------------------------------------------------------------------ -// Memory storage_10: 16-words x 80-bit +// Memory storage_10: 16-words x 81-bit //------------------------------------------------------------------------------ // Port 0 | Read: ---- | Write: Sync | Mode: Read-First // Port 1 | Read: Sync | Write: ---- | -reg [79:0] storage_10[0:15]; -reg [79:0] storage_10_dat1; +reg [80:0] storage_10[0:15]; +reg [80:0] storage_10_dat1; always @(posedge sys_clk) begin if (main_write_w_buffer_wrport_we) storage_10[main_write_w_buffer_wrport_adr] <= main_write_w_buffer_wrport_dat_w; @@ -25251,11 +25249,11 @@ assign main_write_w_buffer_rdport_dat_r = storage_10_dat1; //------------------------------------------------------------------------------ -// Memory storage_11: 16-words x 6-bit +// Memory storage_11: 16-words x 7-bit //------------------------------------------------------------------------------ // Port 0 | Read: ---- | Write: Sync | Mode: Read-First // Port 1 | Read: Async | Write: ---- | -reg [5:0] storage_11[0:15]; +reg [6:0] storage_11[0:15]; always @(posedge sys_clk) begin if (main_write_id_buffer_wrport_we) storage_11[main_write_id_buffer_wrport_adr] <= main_write_id_buffer_wrport_dat_w; @@ -25266,11 +25264,11 @@ assign main_write_id_buffer_rdport_dat_r = storage_11[main_write_id_buffer_rdpor //------------------------------------------------------------------------------ -// Memory storage_12: 16-words x 8-bit +// Memory storage_12: 16-words x 9-bit //------------------------------------------------------------------------------ // Port 0 | Read: ---- | Write: Sync | Mode: Read-First // Port 1 | Read: Async | Write: ---- | -reg [7:0] storage_12[0:15]; +reg [8:0] storage_12[0:15]; always @(posedge sys_clk) begin if (main_write_resp_buffer_wrport_we) storage_12[main_write_resp_buffer_wrport_adr] <= main_write_resp_buffer_wrport_dat_w; @@ -25281,12 +25279,12 @@ assign main_write_resp_buffer_rdport_dat_r = storage_12[main_write_resp_buffer_r //------------------------------------------------------------------------------ -// Memory storage_13: 16-words x 74-bit +// Memory storage_13: 16-words x 75-bit //------------------------------------------------------------------------------ // Port 0 | Read: ---- | Write: Sync | Mode: Read-First // Port 1 | Read: Sync | Write: ---- | -reg [73:0] storage_13[0:15]; -reg [73:0] storage_13_dat1; +reg [74:0] storage_13[0:15]; +reg [74:0] storage_13_dat1; always @(posedge sys_clk) begin if (main_read_r_buffer_wrport_we) storage_13[main_read_r_buffer_wrport_adr] <= main_read_r_buffer_wrport_dat_w; @@ -25299,11 +25297,11 @@ assign main_read_r_buffer_rdport_dat_r = storage_13_dat1; //------------------------------------------------------------------------------ -// Memory storage_14: 16-words x 6-bit +// Memory storage_14: 16-words x 7-bit //------------------------------------------------------------------------------ // Port 0 | Read: ---- | Write: Sync | Mode: Read-First // Port 1 | Read: Async | Write: ---- | -reg [5:0] storage_14[0:15]; +reg [6:0] storage_14[0:15]; always @(posedge sys_clk) begin if (main_read_id_buffer_wrport_we) storage_14[main_read_id_buffer_wrport_adr] <= main_read_id_buffer_wrport_dat_w; @@ -25606,5 +25604,5 @@ FDPE #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2026-03-30 17:34:48. +// Auto-Generated by LiteX on 2026-06-22 19:46:31. //------------------------------------------------------------------------------ diff --git a/addins/cvwsoc/litedram/litedram_genesys2w32.v b/addins/cvwsoc/litedram/litedram_genesys2w32.v index f962c95c69..4d18be28dc 100644 --- a/addins/cvwsoc/litedram/litedram_genesys2w32.v +++ b/addins/cvwsoc/litedram/litedram_genesys2w32.v @@ -11,7 +11,7 @@ // Device : // Hierarchy : disabled // LiteX sha1 : 777d97377 -// Date : 2026-06-09 14:12:29 +// Date : 2026-06-22 19:53:44 //------------------------------------------------------------------------------ `timescale 1ns / 1ps @@ -44,24 +44,24 @@ module litedram_genesys2w32 ( output wire user_clk, input wire [29:0] user_port_axi_0_araddr, input wire [1:0] user_port_axi_0_arburst, - input wire [3:0] user_port_axi_0_arid, + input wire [4:0] user_port_axi_0_arid, input wire [7:0] user_port_axi_0_arlen, output wire user_port_axi_0_arready, input wire [2:0] user_port_axi_0_arsize, input wire user_port_axi_0_arvalid, input wire [29:0] user_port_axi_0_awaddr, input wire [1:0] user_port_axi_0_awburst, - input wire [3:0] user_port_axi_0_awid, + input wire [4:0] user_port_axi_0_awid, input wire [7:0] user_port_axi_0_awlen, output wire user_port_axi_0_awready, input wire [2:0] user_port_axi_0_awsize, input wire user_port_axi_0_awvalid, - output wire [3:0] user_port_axi_0_bid, + output wire [4:0] user_port_axi_0_bid, input wire user_port_axi_0_bready, output wire [1:0] user_port_axi_0_bresp, output wire user_port_axi_0_bvalid, output wire [31:0] user_port_axi_0_rdata, - output wire [3:0] user_port_axi_0_rid, + output wire [4:0] user_port_axi_0_rid, output wire user_port_axi_0_rlast, input wire user_port_axi_0_rready, output wire [1:0] user_port_axi_0_rresp, @@ -192,6 +192,7 @@ LiteDRAMCore │ ├── bitslip_71 (BitSlip) [Gen] │ ├── tappeddelayline_2 (TappedDelayLine) [Gen] │ ├── tappeddelayline_3 (TappedDelayLine) [Gen] +│ ├── [BB:OSERDESE2] │ ├── [BB:ISERDESE2] │ ├── [BB:ODELAYE2] │ ├── [BB:IDELAYE2] @@ -201,8 +202,6 @@ LiteDRAMCore │ ├── [BB:ODELAYE2] │ ├── [BB:IDELAYE2] │ ├── [BB:IOBUF] -│ ├── [BB:IDELAYE2] -│ ├── [BB:IOBUF] │ ├── [BB:OSERDESE2] │ ├── [BB:ISERDESE2] │ ├── [BB:ODELAYE2] @@ -263,13 +262,15 @@ LiteDRAMCore │ ├── [BB:ODELAYE2] │ ├── [BB:IDELAYE2] │ ├── [BB:IOBUF] +│ ├── [BB:ODELAYE2] +│ ├── [BB:IDELAYE2] +│ ├── [BB:IOBUF] │ ├── [BB:OSERDESE2] │ ├── [BB:ISERDESE2] │ ├── [BB:ODELAYE2] │ ├── [BB:IDELAYE2] │ ├── [BB:IOBUF] │ ├── [BB:OSERDESE2] -│ ├── [BB:OSERDESE2] │ ├── [BB:ISERDESE2] │ ├── [BB:ODELAYE2] │ ├── [BB:IDELAYE2] @@ -330,7 +331,10 @@ LiteDRAMCore │ ├── [BB:IDELAYE2] │ ├── [BB:IOBUF] │ ├── [BB:OSERDESE2] -│ ├── [BB:ISERDESE2] +│ ├── [BB:ODELAYE2] +│ ├── [BB:OSERDESE2] +│ ├── [BB:ODELAYE2] +│ ├── [BB:OSERDESE2] │ ├── [BB:ODELAYE2] │ ├── [BB:OSERDESE2] │ ├── [BB:ODELAYE2] @@ -413,17 +417,13 @@ LiteDRAMCore │ ├── [BB:IDELAYE2] │ ├── [BB:IOBUF] │ ├── [BB:OSERDESE2] -│ ├── [BB:ODELAYE2] +│ ├── [BB:ISERDESE2] │ ├── [BB:OSERDESE2] │ ├── [BB:ODELAYE2] -│ ├── [BB:ODELAYE2] │ ├── [BB:OBUFDS] │ ├── [BB:OSERDESE2] │ ├── [BB:ODELAYE2] │ ├── [BB:OSERDESE2] -│ ├── [BB:ODELAYE2] -│ ├── [BB:OSERDESE2] -│ ├── [BB:OSERDESE2] │ └── [BB:ODELAYE2] ├── sdram (LiteDRAMCore) │ ├── dfii (DFIInjector) @@ -993,7 +993,7 @@ wire iodelay_rst; reg main_ar_first = 1'd0; reg main_ar_last = 1'd0; reg main_ar_param_dest = 1'd0; -wire [3:0] main_ar_param_id; +wire [4:0] main_ar_param_id; reg main_ar_param_user = 1'd0; wire [29:0] main_ar_payload_addr; wire [1:0] main_ar_payload_burst; @@ -1009,7 +1009,7 @@ wire main_ar_valid; reg main_aw_first = 1'd0; reg main_aw_last = 1'd0; reg main_aw_param_dest = 1'd0; -wire [3:0] main_aw_param_id; +wire [4:0] main_aw_param_id; reg main_aw_param_user = 1'd0; wire [29:0] main_aw_payload_addr; wire [1:0] main_aw_payload_burst; @@ -1024,7 +1024,7 @@ wire main_aw_ready; wire main_aw_valid; wire main_b_first; wire main_b_last; -wire [3:0] main_b_param_id; +wire [4:0] main_b_param_id; wire [1:0] main_b_payload_resp; wire main_b_ready; wire main_b_valid; @@ -3131,7 +3131,7 @@ reg main_power_down = 1'd0; wire main_r_first; wire main_r_last; wire main_r_param_dest; -wire [3:0] main_r_param_id; +wire [4:0] main_r_param_id; wire main_r_param_user; wire [31:0] main_r_payload_data; reg [1:0] main_r_payload_resp = 2'd0; @@ -3141,7 +3141,7 @@ wire main_ras_allowed; reg main_re = 1'd0; wire main_read_ar_first; wire main_read_ar_last; -wire [3:0] main_read_ar_param_id; +wire [4:0] main_read_ar_param_id; wire [29:0] main_read_ar_payload_addr; reg main_read_ar_ready = 1'd0; wire main_read_ar_valid; @@ -3157,38 +3157,38 @@ reg [3:0] main_read_id_buffer_consume = 4'd0; wire main_read_id_buffer_do_read; wire main_read_id_buffer_fifo_in_first; wire main_read_id_buffer_fifo_in_last; -wire [3:0] main_read_id_buffer_fifo_in_payload_id; +wire [4:0] main_read_id_buffer_fifo_in_payload_id; wire main_read_id_buffer_fifo_out_first; wire main_read_id_buffer_fifo_out_last; -wire [3:0] main_read_id_buffer_fifo_out_payload_id; +wire [4:0] main_read_id_buffer_fifo_out_payload_id; reg [4:0] main_read_id_buffer_level = 5'd0; reg [3:0] main_read_id_buffer_produce = 4'd0; wire [3:0] main_read_id_buffer_rdport_adr; -wire [5:0] main_read_id_buffer_rdport_dat_r; +wire [6:0] main_read_id_buffer_rdport_dat_r; reg main_read_id_buffer_replace = 1'd0; reg main_read_id_buffer_sink_first = 1'd0; wire main_read_id_buffer_sink_last; -wire [3:0] main_read_id_buffer_sink_payload_id; +wire [4:0] main_read_id_buffer_sink_payload_id; wire main_read_id_buffer_sink_ready; wire main_read_id_buffer_sink_valid; wire main_read_id_buffer_source_first; wire main_read_id_buffer_source_last; -wire [3:0] main_read_id_buffer_source_payload_id; +wire [4:0] main_read_id_buffer_source_payload_id; wire main_read_id_buffer_source_ready; wire main_read_id_buffer_source_valid; -wire [5:0] main_read_id_buffer_syncfifo_din; -wire [5:0] main_read_id_buffer_syncfifo_dout; +wire [6:0] main_read_id_buffer_syncfifo_din; +wire [6:0] main_read_id_buffer_syncfifo_dout; wire main_read_id_buffer_syncfifo_re; wire main_read_id_buffer_syncfifo_readable; wire main_read_id_buffer_syncfifo_we; wire main_read_id_buffer_syncfifo_writable; reg [3:0] main_read_id_buffer_wrport_adr = 4'd0; -wire [5:0] main_read_id_buffer_wrport_dat_w; +wire [6:0] main_read_id_buffer_wrport_dat_w; wire main_read_id_buffer_wrport_we; wire main_read_pipe_valid_sink_first; wire main_read_pipe_valid_sink_last; wire main_read_pipe_valid_sink_param_dest; -wire [3:0] main_read_pipe_valid_sink_param_id; +wire [4:0] main_read_pipe_valid_sink_param_id; wire main_read_pipe_valid_sink_param_user; wire [29:0] main_read_pipe_valid_sink_payload_addr; wire [1:0] main_read_pipe_valid_sink_payload_burst; @@ -3204,7 +3204,7 @@ wire main_read_pipe_valid_sink_valid; reg main_read_pipe_valid_source_first = 1'd0; reg main_read_pipe_valid_source_last = 1'd0; reg main_read_pipe_valid_source_param_dest = 1'd0; -reg [3:0] main_read_pipe_valid_source_param_id = 4'd0; +reg [4:0] main_read_pipe_valid_source_param_id = 5'd0; reg main_read_pipe_valid_source_param_user = 1'd0; reg [29:0] main_read_pipe_valid_source_payload_addr = 30'd0; reg [1:0] main_read_pipe_valid_source_payload_burst = 2'd0; @@ -3223,14 +3223,14 @@ wire main_read_r_buffer_do_read; wire main_read_r_buffer_fifo_in_first; wire main_read_r_buffer_fifo_in_last; wire main_read_r_buffer_fifo_in_param_dest; -wire [3:0] main_read_r_buffer_fifo_in_param_id; +wire [4:0] main_read_r_buffer_fifo_in_param_id; wire main_read_r_buffer_fifo_in_param_user; wire [31:0] main_read_r_buffer_fifo_in_payload_data; wire [1:0] main_read_r_buffer_fifo_in_payload_resp; wire main_read_r_buffer_fifo_out_first; wire main_read_r_buffer_fifo_out_last; wire main_read_r_buffer_fifo_out_param_dest; -wire [3:0] main_read_r_buffer_fifo_out_param_id; +wire [4:0] main_read_r_buffer_fifo_out_param_id; wire main_read_r_buffer_fifo_out_param_user; wire [31:0] main_read_r_buffer_fifo_out_payload_data; wire [1:0] main_read_r_buffer_fifo_out_payload_resp; @@ -3240,7 +3240,7 @@ reg [4:0] main_read_r_buffer_level2 = 5'd0; reg [3:0] main_read_r_buffer_produce = 4'd0; wire main_read_r_buffer_queue; wire [3:0] main_read_r_buffer_rdport_adr; -wire [41:0] main_read_r_buffer_rdport_dat_r; +wire [42:0] main_read_r_buffer_rdport_dat_r; wire main_read_r_buffer_rdport_re; wire main_read_r_buffer_re; reg main_read_r_buffer_readable = 1'd0; @@ -3248,7 +3248,7 @@ reg main_read_r_buffer_replace = 1'd0; wire main_read_r_buffer_sink_first; wire main_read_r_buffer_sink_last; reg main_read_r_buffer_sink_param_dest = 1'd0; -reg [3:0] main_read_r_buffer_sink_param_id = 4'd0; +reg [4:0] main_read_r_buffer_sink_param_id = 5'd0; reg main_read_r_buffer_sink_param_user = 1'd0; wire [31:0] main_read_r_buffer_sink_payload_data; reg [1:0] main_read_r_buffer_sink_payload_resp = 2'd0; @@ -3257,25 +3257,25 @@ wire main_read_r_buffer_sink_valid; wire main_read_r_buffer_source_first; wire main_read_r_buffer_source_last; wire main_read_r_buffer_source_param_dest; -wire [3:0] main_read_r_buffer_source_param_id; +wire [4:0] main_read_r_buffer_source_param_id; wire main_read_r_buffer_source_param_user; wire [31:0] main_read_r_buffer_source_payload_data; wire [1:0] main_read_r_buffer_source_payload_resp; wire main_read_r_buffer_source_ready; wire main_read_r_buffer_source_valid; -wire [41:0] main_read_r_buffer_syncfifo_din; -wire [41:0] main_read_r_buffer_syncfifo_dout; +wire [42:0] main_read_r_buffer_syncfifo_din; +wire [42:0] main_read_r_buffer_syncfifo_dout; wire main_read_r_buffer_syncfifo_re; wire main_read_r_buffer_syncfifo_readable; wire main_read_r_buffer_syncfifo_we; wire main_read_r_buffer_syncfifo_writable; reg [3:0] main_read_r_buffer_wrport_adr = 4'd0; -wire [41:0] main_read_r_buffer_wrport_dat_w; +wire [42:0] main_read_r_buffer_wrport_dat_w; wire main_read_r_buffer_wrport_we; wire main_read_sink_sink_first; wire main_read_sink_sink_last; wire main_read_sink_sink_param_dest; -wire [3:0] main_read_sink_sink_param_id; +wire [4:0] main_read_sink_sink_param_id; wire main_read_sink_sink_param_user; wire [29:0] main_read_sink_sink_payload_addr; wire [1:0] main_read_sink_sink_payload_burst; @@ -3291,7 +3291,7 @@ wire main_read_sink_sink_valid; wire main_read_source_source_first; wire main_read_source_source_last; wire main_read_source_source_param_dest; -wire [3:0] main_read_source_source_param_id; +wire [4:0] main_read_source_source_param_id; wire main_read_source_source_param_user; wire [29:0] main_read_source_source_payload_addr; wire [1:0] main_read_source_source_payload_burst; @@ -3444,7 +3444,7 @@ wire main_wb_bus_we; wire main_write_available; wire main_write_aw_first; wire main_write_aw_last; -wire [3:0] main_write_aw_param_id; +wire [4:0] main_write_aw_param_id; wire [29:0] main_write_aw_payload_addr; reg main_write_aw_ready = 1'd0; wire main_write_aw_valid; @@ -3460,38 +3460,38 @@ reg [3:0] main_write_id_buffer_consume = 4'd0; wire main_write_id_buffer_do_read; wire main_write_id_buffer_fifo_in_first; wire main_write_id_buffer_fifo_in_last; -wire [3:0] main_write_id_buffer_fifo_in_payload_id; +wire [4:0] main_write_id_buffer_fifo_in_payload_id; wire main_write_id_buffer_fifo_out_first; wire main_write_id_buffer_fifo_out_last; -wire [3:0] main_write_id_buffer_fifo_out_payload_id; +wire [4:0] main_write_id_buffer_fifo_out_payload_id; reg [4:0] main_write_id_buffer_level = 5'd0; reg [3:0] main_write_id_buffer_produce = 4'd0; wire [3:0] main_write_id_buffer_rdport_adr; -wire [5:0] main_write_id_buffer_rdport_dat_r; +wire [6:0] main_write_id_buffer_rdport_dat_r; reg main_write_id_buffer_replace = 1'd0; reg main_write_id_buffer_sink_first = 1'd0; reg main_write_id_buffer_sink_last = 1'd0; -wire [3:0] main_write_id_buffer_sink_payload_id; +wire [4:0] main_write_id_buffer_sink_payload_id; wire main_write_id_buffer_sink_ready; wire main_write_id_buffer_sink_valid; wire main_write_id_buffer_source_first; wire main_write_id_buffer_source_last; -wire [3:0] main_write_id_buffer_source_payload_id; +wire [4:0] main_write_id_buffer_source_payload_id; reg main_write_id_buffer_source_ready = 1'd0; wire main_write_id_buffer_source_valid; -wire [5:0] main_write_id_buffer_syncfifo_din; -wire [5:0] main_write_id_buffer_syncfifo_dout; +wire [6:0] main_write_id_buffer_syncfifo_din; +wire [6:0] main_write_id_buffer_syncfifo_dout; wire main_write_id_buffer_syncfifo_re; wire main_write_id_buffer_syncfifo_readable; wire main_write_id_buffer_syncfifo_we; wire main_write_id_buffer_syncfifo_writable; reg [3:0] main_write_id_buffer_wrport_adr = 4'd0; -wire [5:0] main_write_id_buffer_wrport_dat_w; +wire [6:0] main_write_id_buffer_wrport_dat_w; wire main_write_id_buffer_wrport_we; wire main_write_pipe_valid_sink_first; wire main_write_pipe_valid_sink_last; wire main_write_pipe_valid_sink_param_dest; -wire [3:0] main_write_pipe_valid_sink_param_id; +wire [4:0] main_write_pipe_valid_sink_param_id; wire main_write_pipe_valid_sink_param_user; wire [29:0] main_write_pipe_valid_sink_payload_addr; wire [1:0] main_write_pipe_valid_sink_payload_burst; @@ -3507,7 +3507,7 @@ wire main_write_pipe_valid_sink_valid; reg main_write_pipe_valid_source_first = 1'd0; reg main_write_pipe_valid_source_last = 1'd0; reg main_write_pipe_valid_source_param_dest = 1'd0; -reg [3:0] main_write_pipe_valid_source_param_id = 4'd0; +reg [4:0] main_write_pipe_valid_source_param_id = 5'd0; reg main_write_pipe_valid_source_param_user = 1'd0; reg [29:0] main_write_pipe_valid_source_payload_addr = 30'd0; reg [1:0] main_write_pipe_valid_source_payload_burst = 2'd0; @@ -3524,42 +3524,42 @@ reg [3:0] main_write_resp_buffer_consume = 4'd0; wire main_write_resp_buffer_do_read; wire main_write_resp_buffer_fifo_in_first; wire main_write_resp_buffer_fifo_in_last; -wire [3:0] main_write_resp_buffer_fifo_in_payload_id; +wire [4:0] main_write_resp_buffer_fifo_in_payload_id; wire [1:0] main_write_resp_buffer_fifo_in_payload_resp; wire main_write_resp_buffer_fifo_out_first; wire main_write_resp_buffer_fifo_out_last; -wire [3:0] main_write_resp_buffer_fifo_out_payload_id; +wire [4:0] main_write_resp_buffer_fifo_out_payload_id; wire [1:0] main_write_resp_buffer_fifo_out_payload_resp; reg [4:0] main_write_resp_buffer_level = 5'd0; reg [3:0] main_write_resp_buffer_produce = 4'd0; wire [3:0] main_write_resp_buffer_rdport_adr; -wire [7:0] main_write_resp_buffer_rdport_dat_r; +wire [8:0] main_write_resp_buffer_rdport_dat_r; reg main_write_resp_buffer_replace = 1'd0; reg main_write_resp_buffer_sink_first = 1'd0; reg main_write_resp_buffer_sink_last = 1'd0; -reg [3:0] main_write_resp_buffer_sink_payload_id = 4'd0; +reg [4:0] main_write_resp_buffer_sink_payload_id = 5'd0; reg [1:0] main_write_resp_buffer_sink_payload_resp = 2'd0; wire main_write_resp_buffer_sink_ready; reg main_write_resp_buffer_sink_valid = 1'd0; wire main_write_resp_buffer_source_first; wire main_write_resp_buffer_source_last; -wire [3:0] main_write_resp_buffer_source_payload_id; +wire [4:0] main_write_resp_buffer_source_payload_id; wire [1:0] main_write_resp_buffer_source_payload_resp; wire main_write_resp_buffer_source_ready; wire main_write_resp_buffer_source_valid; -wire [7:0] main_write_resp_buffer_syncfifo_din; -wire [7:0] main_write_resp_buffer_syncfifo_dout; +wire [8:0] main_write_resp_buffer_syncfifo_din; +wire [8:0] main_write_resp_buffer_syncfifo_dout; wire main_write_resp_buffer_syncfifo_re; wire main_write_resp_buffer_syncfifo_readable; wire main_write_resp_buffer_syncfifo_we; wire main_write_resp_buffer_syncfifo_writable; reg [3:0] main_write_resp_buffer_wrport_adr = 4'd0; -wire [7:0] main_write_resp_buffer_wrport_dat_w; +wire [8:0] main_write_resp_buffer_wrport_dat_w; wire main_write_resp_buffer_wrport_we; wire main_write_sink_sink_first; wire main_write_sink_sink_last; wire main_write_sink_sink_param_dest; -wire [3:0] main_write_sink_sink_param_id; +wire [4:0] main_write_sink_sink_param_id; wire main_write_sink_sink_param_user; wire [29:0] main_write_sink_sink_payload_addr; wire [1:0] main_write_sink_sink_payload_burst; @@ -3575,7 +3575,7 @@ wire main_write_sink_sink_valid; wire main_write_source_source_first; wire main_write_source_source_last; wire main_write_source_source_param_dest; -wire [3:0] main_write_source_source_param_id; +wire [4:0] main_write_source_source_param_id; wire main_write_source_source_param_user; wire [29:0] main_write_source_source_payload_addr; wire [1:0] main_write_source_source_payload_burst; @@ -3594,14 +3594,14 @@ wire main_write_w_buffer_do_read; wire main_write_w_buffer_fifo_in_first; wire main_write_w_buffer_fifo_in_last; wire main_write_w_buffer_fifo_in_param_dest; -wire [3:0] main_write_w_buffer_fifo_in_param_id; +wire [4:0] main_write_w_buffer_fifo_in_param_id; wire main_write_w_buffer_fifo_in_param_user; wire [31:0] main_write_w_buffer_fifo_in_payload_data; wire [3:0] main_write_w_buffer_fifo_in_payload_strb; wire main_write_w_buffer_fifo_out_first; wire main_write_w_buffer_fifo_out_last; wire main_write_w_buffer_fifo_out_param_dest; -wire [3:0] main_write_w_buffer_fifo_out_param_id; +wire [4:0] main_write_w_buffer_fifo_out_param_id; wire main_write_w_buffer_fifo_out_param_user; wire [31:0] main_write_w_buffer_fifo_out_payload_data; wire [3:0] main_write_w_buffer_fifo_out_payload_strb; @@ -3611,7 +3611,7 @@ reg [4:0] main_write_w_buffer_level2 = 5'd0; reg [3:0] main_write_w_buffer_produce = 4'd0; wire main_write_w_buffer_queue; wire [3:0] main_write_w_buffer_rdport_adr; -wire [43:0] main_write_w_buffer_rdport_dat_r; +wire [44:0] main_write_w_buffer_rdport_dat_r; wire main_write_w_buffer_rdport_re; wire main_write_w_buffer_re; reg main_write_w_buffer_readable = 1'd0; @@ -3619,7 +3619,7 @@ reg main_write_w_buffer_replace = 1'd0; reg main_write_w_buffer_sink_first = 1'd0; reg main_write_w_buffer_sink_last = 1'd0; reg main_write_w_buffer_sink_param_dest = 1'd0; -reg [3:0] main_write_w_buffer_sink_param_id = 4'd0; +reg [4:0] main_write_w_buffer_sink_param_id = 5'd0; reg main_write_w_buffer_sink_param_user = 1'd0; reg [31:0] main_write_w_buffer_sink_payload_data = 32'd0; reg [3:0] main_write_w_buffer_sink_payload_strb = 4'd0; @@ -3628,20 +3628,20 @@ reg main_write_w_buffer_sink_valid = 1'd0; wire main_write_w_buffer_source_first; wire main_write_w_buffer_source_last; wire main_write_w_buffer_source_param_dest; -wire [3:0] main_write_w_buffer_source_param_id; +wire [4:0] main_write_w_buffer_source_param_id; wire main_write_w_buffer_source_param_user; wire [31:0] main_write_w_buffer_source_payload_data; wire [3:0] main_write_w_buffer_source_payload_strb; wire main_write_w_buffer_source_ready; wire main_write_w_buffer_source_valid; -wire [43:0] main_write_w_buffer_syncfifo_din; -wire [43:0] main_write_w_buffer_syncfifo_dout; +wire [44:0] main_write_w_buffer_syncfifo_din; +wire [44:0] main_write_w_buffer_syncfifo_dout; wire main_write_w_buffer_syncfifo_re; wire main_write_w_buffer_syncfifo_readable; wire main_write_w_buffer_syncfifo_we; wire main_write_w_buffer_syncfifo_writable; reg [3:0] main_write_w_buffer_wrport_adr = 4'd0; -wire [43:0] main_write_w_buffer_wrport_dat_w; +wire [44:0] main_write_w_buffer_wrport_dat_w; wire main_write_w_buffer_wrport_we; reg main_zqcs_executer_done = 1'd0; reg main_zqcs_executer_start = 1'd0; @@ -13433,7 +13433,7 @@ always @(*) begin end end always @(*) begin - main_write_resp_buffer_sink_payload_id <= 4'd0; + main_write_resp_buffer_sink_payload_id <= 5'd0; if (((main_write_w_buffer_source_valid & main_write_w_buffer_source_last) & main_write_w_buffer_source_ready)) begin main_write_resp_buffer_sink_payload_id <= main_write_id_buffer_source_payload_id; end @@ -13535,7 +13535,7 @@ always @(*) begin end end always @(*) begin - main_write_w_buffer_sink_param_id <= 4'd0; + main_write_w_buffer_sink_param_id <= 5'd0; if (main_write_axi_w_connect) begin main_write_w_buffer_sink_param_id <= main_w_param_id; end @@ -25267,12 +25267,12 @@ assign main_litedramnativeportconverter_wdata_fifo_rdport_dat_r = storage_9[main //------------------------------------------------------------------------------ -// Memory storage_10: 16-words x 44-bit +// Memory storage_10: 16-words x 45-bit //------------------------------------------------------------------------------ // Port 0 | Read: ---- | Write: Sync | Mode: Read-First // Port 1 | Read: Sync | Write: ---- | -reg [43:0] storage_10[0:15]; -reg [43:0] storage_10_dat1; +reg [44:0] storage_10[0:15]; +reg [44:0] storage_10_dat1; always @(posedge sys_clk) begin if (main_write_w_buffer_wrport_we) storage_10[main_write_w_buffer_wrport_adr] <= main_write_w_buffer_wrport_dat_w; @@ -25285,11 +25285,11 @@ assign main_write_w_buffer_rdport_dat_r = storage_10_dat1; //------------------------------------------------------------------------------ -// Memory storage_11: 16-words x 6-bit +// Memory storage_11: 16-words x 7-bit //------------------------------------------------------------------------------ // Port 0 | Read: ---- | Write: Sync | Mode: Read-First // Port 1 | Read: Async | Write: ---- | -reg [5:0] storage_11[0:15]; +reg [6:0] storage_11[0:15]; always @(posedge sys_clk) begin if (main_write_id_buffer_wrport_we) storage_11[main_write_id_buffer_wrport_adr] <= main_write_id_buffer_wrport_dat_w; @@ -25300,11 +25300,11 @@ assign main_write_id_buffer_rdport_dat_r = storage_11[main_write_id_buffer_rdpor //------------------------------------------------------------------------------ -// Memory storage_12: 16-words x 8-bit +// Memory storage_12: 16-words x 9-bit //------------------------------------------------------------------------------ // Port 0 | Read: ---- | Write: Sync | Mode: Read-First // Port 1 | Read: Async | Write: ---- | -reg [7:0] storage_12[0:15]; +reg [8:0] storage_12[0:15]; always @(posedge sys_clk) begin if (main_write_resp_buffer_wrport_we) storage_12[main_write_resp_buffer_wrport_adr] <= main_write_resp_buffer_wrport_dat_w; @@ -25315,12 +25315,12 @@ assign main_write_resp_buffer_rdport_dat_r = storage_12[main_write_resp_buffer_r //------------------------------------------------------------------------------ -// Memory storage_13: 16-words x 42-bit +// Memory storage_13: 16-words x 43-bit //------------------------------------------------------------------------------ // Port 0 | Read: ---- | Write: Sync | Mode: Read-First // Port 1 | Read: Sync | Write: ---- | -reg [41:0] storage_13[0:15]; -reg [41:0] storage_13_dat1; +reg [42:0] storage_13[0:15]; +reg [42:0] storage_13_dat1; always @(posedge sys_clk) begin if (main_read_r_buffer_wrport_we) storage_13[main_read_r_buffer_wrport_adr] <= main_read_r_buffer_wrport_dat_w; @@ -25333,11 +25333,11 @@ assign main_read_r_buffer_rdport_dat_r = storage_13_dat1; //------------------------------------------------------------------------------ -// Memory storage_14: 16-words x 6-bit +// Memory storage_14: 16-words x 7-bit //------------------------------------------------------------------------------ // Port 0 | Read: ---- | Write: Sync | Mode: Read-First // Port 1 | Read: Async | Write: ---- | -reg [5:0] storage_14[0:15]; +reg [6:0] storage_14[0:15]; always @(posedge sys_clk) begin if (main_read_id_buffer_wrport_we) storage_14[main_read_id_buffer_wrport_adr] <= main_read_id_buffer_wrport_dat_w; @@ -25640,5 +25640,5 @@ FDPE #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2026-06-09 14:12:29. +// Auto-Generated by LiteX on 2026-06-22 19:53:45. //------------------------------------------------------------------------------ diff --git a/addins/cvwsoc/uberddr3/uberddr3_wrapper.sv b/addins/cvwsoc/uberddr3/uberddr3_wrapper.sv index 10f963f5cc..c34b3765aa 100644 --- a/addins/cvwsoc/uberddr3/uberddr3_wrapper.sv +++ b/addins/cvwsoc/uberddr3/uberddr3_wrapper.sv @@ -204,49 +204,49 @@ module uberddr3_wrapper #( // ------------------------------------------------------------------------ // Internal AXI wiring: external SoC-facing AXI -> axi_adapter -> internal 256-bit AXI // ------------------------------------------------------------------------ - wire [AXI_ID_WIDTH-1:0] axi256_awid; - wire [AXI_ADDR_WIDTH-1:0] axi256_awaddr_full; - wire [7:0] axi256_awlen; - wire [2:0] axi256_awsize; - wire [1:0] axi256_awburst; + (* mark_debug = "true" *) wire [AXI_ID_WIDTH-1:0] axi256_awid; + (* mark_debug = "true" *) wire [AXI_ADDR_WIDTH-1:0] axi256_awaddr_full; + (* mark_debug = "true" *) wire [7:0] axi256_awlen; + (* mark_debug = "true" *) wire [2:0] axi256_awsize; + (* mark_debug = "true" *) wire [1:0] axi256_awburst; wire axi256_awlock; wire [3:0] axi256_awcache; wire [2:0] axi256_awprot; wire [3:0] axi256_awqos; wire [3:0] axi256_awregion; - wire axi256_awvalid; - wire axi256_awready; + (* mark_debug = "true" *) wire axi256_awvalid; + (* mark_debug = "true" *) wire axi256_awready; wire [UBER_AXI_DATA_WIDTH-1:0] axi256_wdata; - wire [UBER_AXI_DATA_WIDTH/8-1:0] axi256_wstrb; - wire axi256_wlast; - wire axi256_wvalid; - wire axi256_wready; - - wire [AXI_ID_WIDTH-1:0] axi256_bid; - wire [1:0] axi256_bresp; - wire axi256_bvalid; - wire axi256_bready; - - wire [AXI_ID_WIDTH-1:0] axi256_arid; - wire [AXI_ADDR_WIDTH-1:0] axi256_araddr_full; - wire [7:0] axi256_arlen; - wire [2:0] axi256_arsize; - wire [1:0] axi256_arburst; + (* mark_debug = "true" *) wire [UBER_AXI_DATA_WIDTH/8-1:0] axi256_wstrb; + (* mark_debug = "true" *) wire axi256_wlast; + (* mark_debug = "true" *) wire axi256_wvalid; + (* mark_debug = "true" *) wire axi256_wready; + + (* mark_debug = "true" *) wire [AXI_ID_WIDTH-1:0] axi256_bid; + (* mark_debug = "true" *) wire [1:0] axi256_bresp; + (* mark_debug = "true" *) wire axi256_bvalid; + (* mark_debug = "true" *) wire axi256_bready; + + (* mark_debug = "true" *) wire [AXI_ID_WIDTH-1:0] axi256_arid; + (* mark_debug = "true" *) wire [AXI_ADDR_WIDTH-1:0] axi256_araddr_full; + (* mark_debug = "true" *) wire [7:0] axi256_arlen; + (* mark_debug = "true" *) wire [2:0] axi256_arsize; + (* mark_debug = "true" *) wire [1:0] axi256_arburst; wire axi256_arlock; wire [3:0] axi256_arcache; wire [2:0] axi256_arprot; wire [3:0] axi256_arqos; wire [3:0] axi256_arregion; - wire axi256_arvalid; - wire axi256_arready; + (* mark_debug = "true" *) wire axi256_arvalid; + (* mark_debug = "true" *) wire axi256_arready; - wire [AXI_ID_WIDTH-1:0] axi256_rid; + (* mark_debug = "true" *) wire [AXI_ID_WIDTH-1:0] axi256_rid; wire [UBER_AXI_DATA_WIDTH-1:0] axi256_rdata; - wire [1:0] axi256_rresp; - wire axi256_rlast; - wire axi256_rvalid; - wire axi256_rready; + (* mark_debug = "true" *) wire [1:0] axi256_rresp; + (* mark_debug = "true" *) wire axi256_rlast; + (* mark_debug = "true" *) wire axi256_rvalid; + (* mark_debug = "true" *) wire axi256_rready; axi_adapter #( .ADDR_WIDTH (AXI_ADDR_WIDTH), diff --git a/addins/cvwsoc/vga/axi_vga_wrap.sv b/addins/cvwsoc/vga/axi_vga_wrap.sv index 9eab452941..e13999cf05 100644 --- a/addins/cvwsoc/vga/axi_vga_wrap.sv +++ b/addins/cvwsoc/vga/axi_vga_wrap.sv @@ -16,6 +16,7 @@ module axi_vga_wrap #( parameter int unsigned AXI_ADDR_W = 32, parameter int unsigned AXI_DATA_W = 64, parameter int unsigned AXI_ID_W = 4, + parameter int unsigned AXI_M_ID_W = AXI_ID_W, parameter int unsigned AXI_USER_W = 1 ) ( input logic aclk, @@ -69,7 +70,7 @@ module axi_vga_wrap #( // ---------------------------- // AXI MASTER (scanout) to xbar S02 // ---------------------------- - output logic [AXI_ID_W-1:0] m_axi_awid, + output logic [AXI_M_ID_W-1:0] m_axi_awid, output logic [AXI_ADDR_W-1:0] m_axi_awaddr, output logic [7:0] m_axi_awlen, output logic [2:0] m_axi_awsize, @@ -86,12 +87,12 @@ module axi_vga_wrap #( output logic m_axi_wvalid, input logic m_axi_wready, - input logic [AXI_ID_W-1:0] m_axi_bid, + input logic [AXI_M_ID_W-1:0] m_axi_bid, input logic [1:0] m_axi_bresp, input logic m_axi_bvalid, output logic m_axi_bready, - output logic [AXI_ID_W-1:0] m_axi_arid, + output logic [AXI_M_ID_W-1:0] m_axi_arid, output logic [AXI_ADDR_W-1:0] m_axi_araddr, output logic [7:0] m_axi_arlen, output logic [2:0] m_axi_arsize, @@ -102,7 +103,7 @@ module axi_vga_wrap #( output logic m_axi_arvalid, input logic m_axi_arready, - input logic [AXI_ID_W-1:0] m_axi_rid, + input logic [AXI_M_ID_W-1:0] m_axi_rid, input logic [AXI_DATA_W-1:0] m_axi_rdata, input logic [1:0] m_axi_rresp, input logic m_axi_rlast, @@ -127,9 +128,19 @@ module axi_vga_wrap #( typedef logic [AXI_ADDR_W-1:0] axi_addr_t; typedef logic [AXI_DATA_W-1:0] axi_data_t; typedef logic [AXI_DATA_W/8-1:0] axi_strb_t; - typedef logic [AXI_ID_W-1:0] axi_id_t; + typedef logic [AXI_ID_W-1:0] cfg_axi_id_t; + typedef logic [AXI_M_ID_W-1:0] axi_id_t; typedef logic [AXI_USER_W-1:0] axi_user_t; + `AXI_TYPEDEF_AW_CHAN_T(cfg_aw_chan_t, axi_addr_t, cfg_axi_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T (cfg_w_chan_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T (cfg_b_chan_t, cfg_axi_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(cfg_ar_chan_t, axi_addr_t, cfg_axi_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T (cfg_r_chan_t, axi_data_t, cfg_axi_id_t, axi_user_t) + + `AXI_TYPEDEF_REQ_T (cfg_axi_req_t, cfg_aw_chan_t, cfg_w_chan_t, cfg_ar_chan_t) + `AXI_TYPEDEF_RESP_T(cfg_axi_resp_t, cfg_b_chan_t, cfg_r_chan_t) + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, axi_addr_t, axi_id_t, axi_user_t) `AXI_TYPEDEF_W_CHAN_T (w_chan_t, axi_data_t, axi_strb_t, axi_user_t) `AXI_TYPEDEF_B_CHAN_T (b_chan_t, axi_id_t, axi_user_t) @@ -158,8 +169,8 @@ module axi_vga_wrap #( // ---------------------------- // Discrete <-> struct signals // ---------------------------- - axi_req_t cfg_axi_req; - axi_resp_t cfg_axi_resp; + cfg_axi_req_t cfg_axi_req; + cfg_axi_resp_t cfg_axi_resp; axi_req_t vga_axi_req; axi_resp_t vga_axi_resp; @@ -285,8 +296,8 @@ module axi_vga_wrap #( .CutMemReqs (1'b1), //As in Cheshire project //.CutMemRsps (1'b0), .CutMemRsps (1'b1), //Not set like this in Cheshire project - .axi_req_t (axi_req_t), - .axi_rsp_t (axi_resp_t), + .axi_req_t (cfg_axi_req_t), + .axi_rsp_t (cfg_axi_resp_t), .reg_req_t (reg_req_t), .reg_rsp_t (reg_resp_t) ) i_axi_to_reg ( @@ -308,7 +319,7 @@ module axi_vga_wrap #( //.BlueWidth(4), .AXIAddrWidth ( AXI_ADDR_W ), .AXIDataWidth ( AXI_DATA_W ), - .AXIIdWidth ( AXI_ID_W ), + .AXIIdWidth ( AXI_M_ID_W ), .AXIUserWidth ( AXI_USER_W ), .AXIStrbWidth ( AXI_DATA_W/8 ), .axi_req_t ( axi_req_t ), diff --git a/addins/pulp/idma b/addins/pulp/idma new file mode 160000 index 0000000000..785cbd1741 --- /dev/null +++ b/addins/pulp/idma @@ -0,0 +1 @@ +Subproject commit 785cbd17415c5cba16ee73e0682de1498ac14113 diff --git a/config/derivlist.txt b/config/derivlist.txt index b07ff4eef5..5ea1759973 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -91,9 +91,9 @@ WISHBONE_ETH_RANGE 64'h00003FFF WISHBONE_STUB_SUPPORTED 1 WISHBONE_STUB_BASE 64'h11005000 WISHBONE_STUB_RANGE 64'h00000FFF -AXI_DMA_SUPPORTED 1 -AXI_DMA_BASE 64'h100A0000 -AXI_DMA_RANGE 64'h0000FFFF +XILINX_AXI_DMA_SUPPORTED 0 +XILINX_AXI_DMA_BASE 64'h100A0000 +XILINX_AXI_DMA_RANGE 64'h0000FFFF AXI_VGA_SUPPORTED 1 AXI_VGA_BASE 64'h100B0000 AXI_VGA_RANGE 64'h00000FFF @@ -122,12 +122,18 @@ WISHBONE_ETH_RANGE 64'h00003FFF WISHBONE_STUB_SUPPORTED 1 WISHBONE_STUB_BASE 64'h11005000 WISHBONE_STUB_RANGE 64'h00000FFF +AXI_IDMA_SUPPORTED 0 +AXI_IDMA_BASE 64'h10080000 +AXI_IDMA_RANGE 64'h00000FFF +AXI_IDMA_REG64_SUPPORTED 0 +AXI_IDMA_REG64_BASE 64'h10081000 +AXI_IDMA_REG64_RANGE 64'h00000FFF AXI_SDHCI_SUPPORTED 1 AXI_SDHCI_BASE 64'h10090000 AXI_SDHCI_RANGE 64'h00001FFF -AXI_DMA_SUPPORTED 1 -AXI_DMA_BASE 64'h100A0000 -AXI_DMA_RANGE 64'h0000FFFF +XILINX_AXI_DMA_SUPPORTED 0 +XILINX_AXI_DMA_BASE 64'h100A0000 +XILINX_AXI_DMA_RANGE 64'h0000FFFF AXI_VGA_SUPPORTED 1 AXI_VGA_BASE 64'h100B0000 AXI_VGA_RANGE 64'h00000FFF @@ -153,8 +159,10 @@ deriv fpgagenesys2socxlnx fpgagenesys2soc XILINX_AXI_BR_SUPPORTED 1 XILINX_CDC_SUPPORTED 1 XILINX_XBAR_SUPPORTED 1 +XILINX_AXI_DMA_SUPPORTED 1 UBERDDR3_SUPPORTED 0 LITEDRAM_SUPPORTED 0 +AXI_IDMA_SUPPORTED 0 # RV32 builds deriv buildrootrv32 rv32gc @@ -208,12 +216,18 @@ WISHBONE_ETH_RANGE 64'h00003FFF WISHBONE_STUB_SUPPORTED 1 WISHBONE_STUB_BASE 64'h11005000 WISHBONE_STUB_RANGE 64'h00000FFF +AXI_IDMA_SUPPORTED 0 +AXI_IDMA_BASE 64'h10080000 +AXI_IDMA_RANGE 64'h00000FFF +AXI_IDMA_REG64_SUPPORTED 0 +AXI_IDMA_REG64_BASE 64'h10081000 +AXI_IDMA_REG64_RANGE 64'h00000FFF AXI_SDHCI_SUPPORTED 1 AXI_SDHCI_BASE 64'h10090000 AXI_SDHCI_RANGE 64'h00001FFF -AXI_DMA_SUPPORTED 1 -AXI_DMA_BASE 64'h100A0000 -AXI_DMA_RANGE 64'h0000FFFF +XILINX_AXI_DMA_SUPPORTED 0 +XILINX_AXI_DMA_BASE 64'h100A0000 +XILINX_AXI_DMA_RANGE 64'h0000FFFF AXI_VGA_SUPPORTED 1 AXI_VGA_BASE 64'h100B0000 AXI_VGA_RANGE 64'h00000FFF @@ -249,6 +263,10 @@ LITEDRAM_SUPPORTED 1 # RV32 (XLEN=32) with AHBW=64 deriv fpgagenesys2rv32w64soc fpgagenesys2rv32soc AHBW 64 +UBERDDR3_SUPPORTED 0 +LITEDRAM_SUPPORTED 1 +AXI_IDMA_SUPPORTED 1 +AXI_IDMA_REG64_SUPPORTED 1 # temporary spitest configuration diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index f11ab65ef3..a9c2c1c9ff 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -207,12 +207,18 @@ localparam logic [63:0] WISHBONE_ETH_RANGE = 64'h00003FFF; localparam logic WISHBONE_STUB_SUPPORTED = 0; localparam logic [63:0] WISHBONE_STUB_BASE = 64'h11005000; localparam logic [63:0] WISHBONE_STUB_RANGE = 64'h00000FFF; +localparam logic AXI_IDMA_SUPPORTED = 0; +localparam logic [63:0] AXI_IDMA_BASE = 64'h10080000; +localparam logic [63:0] AXI_IDMA_RANGE = 64'h00000FFF; +localparam logic AXI_IDMA_REG64_SUPPORTED = 0; +localparam logic [63:0] AXI_IDMA_REG64_BASE = 64'h10081000; +localparam logic [63:0] AXI_IDMA_REG64_RANGE = 64'h00000FFF; localparam logic AXI_SDHCI_SUPPORTED = 0; localparam logic [63:0] AXI_SDHCI_BASE = 64'h10090000; localparam logic [63:0] AXI_SDHCI_RANGE = 64'h00000FFF; -localparam logic AXI_DMA_SUPPORTED = 0; -localparam logic [63:0] AXI_DMA_BASE = 64'h100A0000; -localparam logic [63:0] AXI_DMA_RANGE = 64'h0000FFFF; +localparam logic XILINX_AXI_DMA_SUPPORTED = 0; +localparam logic [63:0] XILINX_AXI_DMA_BASE = 64'h100A0000; +localparam logic [63:0] XILINX_AXI_DMA_RANGE = 64'h0000FFFF; localparam logic AXI_VGA_SUPPORTED = 0; localparam logic [63:0] AXI_VGA_BASE = 64'h100B0000; localparam logic [63:0] AXI_VGA_RANGE = 64'h00000FFF; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 186304edf5..bfbaa87b75 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -208,12 +208,18 @@ localparam logic [63:0] WISHBONE_ETH_RANGE = 64'h00003FFF; localparam logic WISHBONE_STUB_SUPPORTED = 0; localparam logic [63:0] WISHBONE_STUB_BASE = 64'h11005000; localparam logic [63:0] WISHBONE_STUB_RANGE = 64'h00000FFF; +localparam logic AXI_IDMA_SUPPORTED = 0; +localparam logic [63:0] AXI_IDMA_BASE = 64'h10080000; +localparam logic [63:0] AXI_IDMA_RANGE = 64'h00000FFF; +localparam logic AXI_IDMA_REG64_SUPPORTED = 0; +localparam logic [63:0] AXI_IDMA_REG64_BASE = 64'h10081000; +localparam logic [63:0] AXI_IDMA_REG64_RANGE = 64'h00000FFF; localparam logic AXI_SDHCI_SUPPORTED = 0; localparam logic [63:0] AXI_SDHCI_BASE = 64'h10090000; localparam logic [63:0] AXI_SDHCI_RANGE = 64'h00000FFF; -localparam logic AXI_DMA_SUPPORTED = 0; -localparam logic [63:0] AXI_DMA_BASE = 64'h100A0000; -localparam logic [63:0] AXI_DMA_RANGE = 64'h0000FFFF; +localparam logic XILINX_AXI_DMA_SUPPORTED = 0; +localparam logic [63:0] XILINX_AXI_DMA_BASE = 64'h100A0000; +localparam logic [63:0] XILINX_AXI_DMA_RANGE = 64'h0000FFFF; localparam logic AXI_VGA_SUPPORTED = 0; localparam logic [63:0] AXI_VGA_BASE = 64'h100B0000; localparam logic [63:0] AXI_VGA_RANGE = 64'h00000FFF; diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index ef0080836d..9912ad7bc4 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -109,12 +109,18 @@ localparam cvw_t P = '{ WISHBONE_STUB_SUPPORTED : WISHBONE_STUB_SUPPORTED, WISHBONE_STUB_BASE : WISHBONE_STUB_BASE, WISHBONE_STUB_RANGE : WISHBONE_STUB_RANGE, + AXI_IDMA_SUPPORTED : AXI_IDMA_SUPPORTED, + AXI_IDMA_BASE : AXI_IDMA_BASE, + AXI_IDMA_RANGE : AXI_IDMA_RANGE, + AXI_IDMA_REG64_SUPPORTED : AXI_IDMA_REG64_SUPPORTED, + AXI_IDMA_REG64_BASE : AXI_IDMA_REG64_BASE, + AXI_IDMA_REG64_RANGE : AXI_IDMA_REG64_RANGE, AXI_SDHCI_SUPPORTED : AXI_SDHCI_SUPPORTED, AXI_SDHCI_BASE : AXI_SDHCI_BASE, AXI_SDHCI_RANGE : AXI_SDHCI_RANGE, - AXI_DMA_SUPPORTED : AXI_DMA_SUPPORTED, - AXI_DMA_BASE : AXI_DMA_BASE, - AXI_DMA_RANGE : AXI_DMA_RANGE, + XILINX_AXI_DMA_SUPPORTED : XILINX_AXI_DMA_SUPPORTED, + XILINX_AXI_DMA_BASE : XILINX_AXI_DMA_BASE, + XILINX_AXI_DMA_RANGE : XILINX_AXI_DMA_RANGE, AXI_VGA_SUPPORTED : AXI_VGA_SUPPORTED, AXI_VGA_BASE : AXI_VGA_BASE, AXI_VGA_RANGE : AXI_VGA_RANGE, diff --git a/fpga/constraints/debug-boot-uberddr3.xdc b/fpga/constraints/debug-boot-uberddr3.xdc index f964b12a0f..03d383aeba 100644 --- a/fpga/constraints/debug-boot-uberddr3.xdc +++ b/fpga/constraints/debug-boot-uberddr3.xdc @@ -40,3 +40,36 @@ ila_add_probe u_ila_axi -net ddr3/o_s_axi_arready # ila_add_probe u_ila_axi -net ddr3/i_s_axi_bready #ila_add_probe u_ila_axi -bus ddr3/main_b_param_id -msb 3 -lsb 0 -order lsb2msb #ila_add_probe u_ila_axi -bus ddr3/main_b_payload_resp -msb 1 -lsb 0 -order lsb2msb + +# UberDDR3 wrapper internal 256-bit AXI adapter output. +ila_add_probe u_ila_axi -net ddr3/axi256_awvalid +ila_add_probe u_ila_axi -net ddr3/axi256_awready +ila_add_probe u_ila_axi -bus ddr3/axi256_awid -msb 4 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus ddr3/axi256_awaddr_full -msb 31 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus ddr3/axi256_awlen -msb 7 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus ddr3/axi256_awsize -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus ddr3/axi256_awburst -msb 1 -lsb 0 -order lsb2msb + +ila_add_probe u_ila_axi -net ddr3/axi256_wvalid +ila_add_probe u_ila_axi -net ddr3/axi256_wready +ila_add_probe u_ila_axi -bus ddr3/axi256_wstrb -msb 31 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net ddr3/axi256_wlast + +ila_add_probe u_ila_axi -net ddr3/axi256_bvalid +ila_add_probe u_ila_axi -net ddr3/axi256_bready +ila_add_probe u_ila_axi -bus ddr3/axi256_bid -msb 4 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus ddr3/axi256_bresp -msb 1 -lsb 0 -order lsb2msb + +ila_add_probe u_ila_axi -net ddr3/axi256_arvalid +ila_add_probe u_ila_axi -net ddr3/axi256_arready +ila_add_probe u_ila_axi -bus ddr3/axi256_arid -msb 4 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus ddr3/axi256_araddr_full -msb 31 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus ddr3/axi256_arlen -msb 7 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus ddr3/axi256_arsize -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus ddr3/axi256_arburst -msb 1 -lsb 0 -order lsb2msb + +ila_add_probe u_ila_axi -net ddr3/axi256_rvalid +ila_add_probe u_ila_axi -net ddr3/axi256_rready +ila_add_probe u_ila_axi -bus ddr3/axi256_rid -msb 4 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net ddr3/axi256_rlast +ila_add_probe u_ila_axi -bus ddr3/axi256_rresp -msb 1 -lsb 0 -order lsb2msb diff --git a/fpga/constraints/debug-boot.xdc b/fpga/constraints/debug-boot.xdc index 78353edf57..cb2829e440 100644 --- a/fpga/constraints/debug-boot.xdc +++ b/fpga/constraints/debug-boot.xdc @@ -80,6 +80,50 @@ ila_add_probe u_ila_spi -net HRESPEXT ila_add_probe u_ila_spi -net HMASTLOCK #ila_add_probe u_ila_spi -bus HWSTRB -msb 7 -lsb 0 -order lsb2msb +# AHB-AXI bridge minimal signals +# AXI bridge output signals required by bridge_trace_analyzer +ila_add_probe u_ila_spi -bus m_axi_awid -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_awaddr -msb 31 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_awlen -msb 7 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_awsize -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_awburst -msb 1 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -net m_axi_awlock +ila_add_probe u_ila_spi -bus m_axi_awcache -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_awprot -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -net m_axi_awvalid +ila_add_probe u_ila_spi -net m_axi_awready + +ila_add_probe u_ila_spi -bus m_axi_wdata -msb auto -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_wstrb -msb 7 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -net m_axi_wlast +ila_add_probe u_ila_spi -net m_axi_wvalid +ila_add_probe u_ila_spi -net m_axi_wready + +ila_add_probe u_ila_spi -bus m_axi_bid -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -net m_axi_bvalid +ila_add_probe u_ila_spi -net m_axi_bready + +ila_add_probe u_ila_spi -bus m_axi_arid -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_araddr -msb 31 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_arlen -msb 7 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_arsize -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_arburst -msb 1 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -net m_axi_arlock +ila_add_probe u_ila_spi -bus m_axi_arcache -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_arprot -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -net m_axi_arvalid +ila_add_probe u_ila_spi -net m_axi_arready + +ila_add_probe u_ila_spi -bus m_axi_rid -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_rdata -msb auto -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -net m_axi_rlast +ila_add_probe u_ila_spi -net m_axi_rvalid +ila_add_probe u_ila_spi -net m_axi_rready + +ila_add_probe u_ila_spi -bus m_axi_bresp -msb 1 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -bus m_axi_rresp -msb 1 -lsb 0 -order lsb2msb +ila_add_probe u_ila_spi -net peripheral_aresetn +#ila_add_probe u_ila_spi -net BUSCORERSTn ####################################################### # AXI side ILA @@ -351,6 +395,241 @@ ila_add_probe u_ila_axi -bus BUS_axi_araddr -msb 31 -lsb 0 -order lsb2msb # ila_add_probe u_ila_axi -bus BUS_cb_axi_bresp -msb 1 -lsb 0 -order lsb2msb # ila_add_probe u_ila_axi -bus ddr3/user_port_axi_0_bid -msb 3 -lsb 0 -order lsb2msb +# CPU CDC output -> XBAR CPU-master input: cpu_cdc_to_xbar_axi_* +ila_add_probe u_ila_axi -bus BUS_axi_awid -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_awaddr -msb 31 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_awlen -msb 7 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_awsize -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_awburst -msb 1 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_axi_awlock +ila_add_probe u_ila_axi -bus BUS_axi_awcache -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_awprot -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_awqos -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_awregion -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_axi_awvalid +ila_add_probe u_ila_axi -net BUS_axi_awready +ila_add_probe u_ila_axi -bus BUS_axi_wdata -msb 63 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_wstrb -msb 7 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_axi_wlast +ila_add_probe u_ila_axi -net BUS_axi_wvalid +ila_add_probe u_ila_axi -net BUS_axi_wready +ila_add_probe u_ila_axi -bus BUS_axi_bid -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_bresp -msb 1 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_axi_bvalid +ila_add_probe u_ila_axi -net BUS_axi_bready +ila_add_probe u_ila_axi -bus BUS_axi_arid -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_araddr -msb 31 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_arlen -msb 7 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_arsize -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_arburst -msb 1 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_axi_arlock +ila_add_probe u_ila_axi -bus BUS_axi_arcache -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_arprot -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_arqos -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_arregion -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_axi_arvalid +ila_add_probe u_ila_axi -net BUS_axi_arready +ila_add_probe u_ila_axi -bus BUS_axi_rid -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_rdata -msb 63 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_axi_rresp -msb 1 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_axi_rlast +ila_add_probe u_ila_axi -net BUS_axi_rvalid +ila_add_probe u_ila_axi -net BUS_axi_rready +#ila_add_probe u_ila_axi -net BUSCORERSTn + +# XBAR -> iDMA register-slave port at 0x10080000: xbar_to_idma_cfg_axi_* +# Packed crossbar M07 == CB_M_IDMA_DESC. +ila_add_probe u_ila_axi -bus cb_m_axi_awid -msb 39 -lsb 35 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_awaddr -msb 255 -lsb 224 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_awlen -msb 63 -lsb 56 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_awsize -msb 23 -lsb 21 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_awburst -msb 15 -lsb 14 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_awlock -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_awcache -msb 31 -lsb 28 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_awprot -msb 23 -lsb 21 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_awqos -msb 31 -lsb 28 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_awregion -msb 31 -lsb 28 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_awvalid -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_awready -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_wdata -msb 511 -lsb 448 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_wstrb -msb 63 -lsb 56 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_wlast -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_wvalid -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_wready -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_bid -msb 39 -lsb 35 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_bresp -msb 15 -lsb 14 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_bvalid -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_bready -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_arid -msb 39 -lsb 35 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_araddr -msb 255 -lsb 224 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_arlen -msb 63 -lsb 56 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_arsize -msb 23 -lsb 21 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_arburst -msb 15 -lsb 14 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_arlock -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_arcache -msb 31 -lsb 28 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_arprot -msb 23 -lsb 21 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_arqos -msb 31 -lsb 28 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_arregion -msb 31 -lsb 28 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_arvalid -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_arready -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_rid -msb 39 -lsb 35 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_rdata -msb 511 -lsb 448 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_rresp -msb 15 -lsb 14 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_rlast -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_rvalid -msb 7 -lsb 7 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_m_axi_rready -msb 7 -lsb 7 -order lsb2msb + +# iDMA master -> XBAR master-input port: idma_m_axi_* descriptor fetch. +# Packed crossbar S04 == CB_S_IDMA_FE, iDMA descriptor frontend AXI master. +ila_add_probe u_ila_axi -bus cb_s_axi_awid -msb 24 -lsb 20 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awaddr -msb 159 -lsb 128 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awlen -msb 39 -lsb 32 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awsize -msb 14 -lsb 12 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awburst -msb 9 -lsb 8 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awlock -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awcache -msb 19 -lsb 16 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awprot -msb 14 -lsb 12 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awqos -msb 19 -lsb 16 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awvalid -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awready -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_wdata -msb 319 -lsb 256 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_wstrb -msb 39 -lsb 32 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_wlast -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_wvalid -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_wready -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_bid -msb 24 -lsb 20 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_bresp -msb 9 -lsb 8 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_bvalid -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_bready -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arid -msb 24 -lsb 20 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_araddr -msb 159 -lsb 128 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arlen -msb 39 -lsb 32 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arsize -msb 14 -lsb 12 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arburst -msb 9 -lsb 8 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arlock -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arcache -msb 19 -lsb 16 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arprot -msb 14 -lsb 12 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arqos -msb 19 -lsb 16 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arvalid -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arready -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_rid -msb 24 -lsb 20 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_rdata -msb 319 -lsb 256 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_rresp -msb 9 -lsb 8 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_rlast -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_rvalid -msb 4 -lsb 4 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_rready -msb 4 -lsb 4 -order lsb2msb + +# iDMA master -> XBAR master-input port: idma_m_axi_* backend data traffic. +# Packed crossbar S05 == CB_S_IDMA_BE, iDMA backend AXI master. +ila_add_probe u_ila_axi -bus cb_s_axi_awid -msb 29 -lsb 25 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awaddr -msb 191 -lsb 160 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awlen -msb 47 -lsb 40 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awsize -msb 17 -lsb 15 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awburst -msb 11 -lsb 10 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awlock -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awcache -msb 23 -lsb 20 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awprot -msb 17 -lsb 15 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awqos -msb 23 -lsb 20 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awvalid -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_awready -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_wdata -msb 383 -lsb 320 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_wstrb -msb 47 -lsb 40 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_wlast -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_wvalid -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_wready -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_bid -msb 29 -lsb 25 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_bresp -msb 11 -lsb 10 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_bvalid -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_bready -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arid -msb 29 -lsb 25 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_araddr -msb 191 -lsb 160 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arlen -msb 47 -lsb 40 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arsize -msb 17 -lsb 15 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arburst -msb 11 -lsb 10 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arlock -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arcache -msb 23 -lsb 20 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arprot -msb 17 -lsb 15 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arqos -msb 23 -lsb 20 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arvalid -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_arready -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_rid -msb 29 -lsb 25 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_rdata -msb 383 -lsb 320 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_rresp -msb 11 -lsb 10 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_rlast -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_rvalid -msb 5 -lsb 5 -order lsb2msb +ila_add_probe u_ila_axi -bus cb_s_axi_rready -msb 5 -lsb 5 -order lsb2msb + +# XBAR -> DDR slave port: xbar_to_ddr_axi_* +# Use the named DDR/MIG-facing slice of packed crossbar M00. +ila_add_probe u_ila_axi -bus BUS_cb_axi_awid -msb 4 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_awaddr -msb 29 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_awlen -msb 7 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_awsize -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_awburst -msb 1 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_cb_axi_awlock +ila_add_probe u_ila_axi -bus BUS_cb_axi_awcache -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_awprot -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_awqos -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_awregion -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_cb_axi_awvalid +ila_add_probe u_ila_axi -net BUS_cb_axi_awready +ila_add_probe u_ila_axi -bus BUS_cb_axi_wdata -msb 63 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_wstrb -msb 7 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_cb_axi_wlast +ila_add_probe u_ila_axi -net BUS_cb_axi_wvalid +ila_add_probe u_ila_axi -net BUS_cb_axi_wready +ila_add_probe u_ila_axi -bus BUS_cb_axi_bid -msb 4 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_bresp -msb 1 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_cb_axi_bvalid +ila_add_probe u_ila_axi -net BUS_cb_axi_bready +ila_add_probe u_ila_axi -bus BUS_cb_axi_arid -msb 4 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_araddr -msb 29 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_arlen -msb 7 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_arsize -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_arburst -msb 1 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_cb_axi_arlock +ila_add_probe u_ila_axi -bus BUS_cb_axi_arcache -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_arprot -msb 2 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_arqos -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_arregion -msb 3 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_cb_axi_arvalid +ila_add_probe u_ila_axi -net BUS_cb_axi_arready +ila_add_probe u_ila_axi -bus BUS_cb_axi_rid -msb 4 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_rdata -msb 63 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -bus BUS_cb_axi_rresp -msb 1 -lsb 0 -order lsb2msb +ila_add_probe u_ila_axi -net BUS_cb_axi_rlast +ila_add_probe u_ila_axi -net BUS_cb_axi_rvalid +ila_add_probe u_ila_axi -net BUS_cb_axi_rready + + +# iDMA internal signals. +ila_add_probe u_ila_axi -net dma_irq_raw +#ila_add_probe u_ila_axi -net gen_idma.idma_i/rst_ni +#ila_add_probe u_ila_axi -bus gen_idma.idma_i/busy -msb 7 -lsb 0 -order lsb2msb +#ila_add_probe u_ila_axi -net gen_idma.idma_i/idma_req_valid +#ila_add_probe u_ila_axi -net gen_idma.idma_i/idma_req_ready +# ila_add_probe u_ila_axi -bus gen_idma.idma_i/dbg_idma_req_src_addr -msb 31 -lsb 0 -order lsb2msb +# ila_add_probe u_ila_axi -bus gen_idma.idma_i/dbg_idma_req_dst_addr -msb 31 -lsb 0 -order lsb2msb +# ila_add_probe u_ila_axi -bus gen_idma.idma_i/dbg_idma_req_length -msb 31 -lsb 0 -order lsb2msb +# ila_add_probe u_ila_axi -net gen_idma.idma_i/idma_rsp_valid +# ila_add_probe u_ila_axi -net gen_idma.idma_i/idma_rsp_ready +# ila_add_probe u_ila_axi -net gen_idma.idma_i/gen_desc64.desc64_irq_pulse +# ila_add_probe u_ila_axi -net gen_idma.idma_i/gen_desc64.desc64_irq_pending +# ila_add_probe u_ila_axi -bus gen_idma.idma_i/gen_desc64.desc64_i/input_addr -msb 63 -lsb 0 -order lsb2msb +# ila_add_probe u_ila_axi -net gen_idma.idma_i/gen_desc64.desc64_i/input_addr_valid +# ila_add_probe u_ila_axi -net gen_idma.idma_i/gen_desc64.desc64_i/input_addr_ready +# ila_add_probe u_ila_axi -net gen_idma.idma_i/gen_desc64.desc64_i/dbg_desc_arvalid +# ila_add_probe u_ila_axi -bus gen_idma.idma_i/gen_desc64.desc64_i/dbg_desc_araddr -msb 31 -lsb 0 -order lsb2msb +# ila_add_probe u_ila_axi -bus gen_idma.idma_i/gen_desc64.desc64_i/dbg_desc_arlen -msb 7 -lsb 0 -order lsb2msb +# ila_add_probe u_ila_axi -net gen_idma.idma_i/gen_desc64.desc_req_valid +# ila_add_probe u_ila_axi -net gen_idma.idma_i/gen_desc64.desc_req_ready +# ila_add_probe u_ila_axi -bus gen_idma.idma_i/gen_desc64.dbg_desc_req_src_addr -msb 31 -lsb 0 -order lsb2msb +# ila_add_probe u_ila_axi -bus gen_idma.idma_i/gen_desc64.dbg_desc_req_dst_addr -msb 31 -lsb 0 -order lsb2msb +# ila_add_probe u_ila_axi -bus gen_idma.idma_i/gen_desc64.dbg_desc_req_length -msb 31 -lsb 0 -order lsb2msb +# ila_add_probe u_ila_axi -net gen_idma.idma_i/fe_arb_i/is_new_idma_req +# ila_add_probe u_ila_axi -net gen_idma.idma_i/fe_arb_i/is_new_idma_rsp +# ila_add_probe u_ila_axi -bus gen_idma.idma_i/fe_arb_i/ongoing_req_cnt_q -msb 5 -lsb 0 -order lsb2msb + # DDR calibration ila_add_probe u_ila_axi -net mmcm_locked ila_add_probe u_ila_axi -net c0_init_calib_complete diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index a2389e862f..8d172457cb 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -195,8 +195,7 @@ IP_NEXYSA7SOC: $(dst)/sysrst.log \ IP_GENESYS2SOC: $(dst)/sysrst.log \ MEM_GENESYS2 \ - $(dst)/mmcm-genesys2soc.log \ - $(dst)/axicdma.log + $(dst)/mmcm-genesys2soc.log IP_GENESYS2SOCXLNX: $(dst)/sysrst.log \ MEM_GENESYS2SOCXLNX \ @@ -207,8 +206,7 @@ IP_GENESYS2SOCXLNX: $(dst)/sysrst.log \ $(dst)/clkconverter.log IP_GENESYS2RV32SOC: $(dst)/sysrst.log \ - $(dst)/mmcm-genesys2soc.log \ - $(dst)/axicdma.log + $(dst)/mmcm-genesys2soc.log # Generate Memory IP Blocks .PHONY: MEM_VCU MEM_Arty diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 1ea864eb56..c8f19d5ec0 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -65,7 +65,7 @@ if {$board=="ArtyA7" || $board=="genesys2"} { import_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci # FIXME: remove later # import_ip IP/ahbaxibridge.srcs/sources_1/ip/ahbaxibridge/ahbaxibridge.xci - import_ip IP/axicdma.srcs/sources_1/ip/axicdma/axicdma.xci + # import_ip IP/axicdma.srcs/sources_1/ip/axicdma/axicdma.xci } elseif {$board=="genesys2socxlnx" } { import_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci import_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci @@ -155,8 +155,10 @@ if {$board=="nexysa7soc" || $board=="genesys2soc" || $board=="genesys2rv32soc" ../src/CopiedFiles_do_not_add_to_repo/sdhci/hw/include \ ../src/CopiedFiles_do_not_add_to_repo/pulp/register_interface/include \ ../src/CopiedFiles_do_not_add_to_repo/pulp/axi/include \ + ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/src/include \ ../src/CopiedFiles_do_not_add_to_repo/pulp/common_cells/include} [current_fileset] + # cvwsoc stuff add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/cvwsoc/*/*.v ../src/CopiedFiles_do_not_add_to_repo/cvwsoc/*/*.sv] # Pulp files add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/*/src/*.sv] @@ -185,6 +187,27 @@ if {$board=="nexysa7soc" || $board=="genesys2soc" || $board=="genesys2rv32soc" ../src/CopiedFiles_do_not_add_to_repo/sdhci/hw/*/*.sv \ ] + # iDMA stuff + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/src/idma_pkg.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/src/backend/*.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/src/frontend/idma_transfer_id_gen.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/src/frontend/desc64/idma_desc64_ar_gen.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/src/frontend/desc64/idma_desc64_ar_gen_prefetch.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/src/frontend/desc64/idma_desc64_reader.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/src/frontend/desc64/idma_desc64_reader_gater.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/src/frontend/desc64/idma_desc64_reshaper.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/src/frontend/desc64/idma_desc64_reg_wrapper.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/src/frontend/desc64/idma_desc64_top.sv] + # iDMA: generated RTL + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/target/rtl/idma_transport_layer_rw_axi.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/target/rtl/idma_legalizer_rw_axi.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/target/rtl/idma_backend_rw_axi.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/target/rtl/idma_desc64_reg_pkg.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/target/rtl/idma_desc64_reg_top.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/target/rtl/idma_reg64_1d_reg_pkg.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/target/rtl/idma_reg64_1d_reg_top.sv] + add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/pulp/idma/target/rtl/idma_reg64_1d_top.sv] + report_compile_order -constraints > reports/compile_order.rpt } diff --git a/fpga/generatorxc7/Makefile b/fpga/generatorxc7/Makefile index 163701c596..fbcb69c862 100644 --- a/fpga/generatorxc7/Makefile +++ b/fpga/generatorxc7/Makefile @@ -230,7 +230,7 @@ $(PREPROCESS_STAMP): $(CONFIG_VH) $(RTL_INPUTS) $(PULP_AXI_CDC_SRCS) $(TOP_SV) $ sed -i -E 's/(localparam logic WISHBONE_STUB_SUPPORTED[[:space:]]*=[[:space:]]*)1;/\10;/' $(SRC_COPY)/config/config.vh # Disable optional AXI peripherals that are not routed in this OpenXC7 bitstream. sed -i -E 's/(localparam logic AXI_SDHCI_SUPPORTED[[:space:]]*=[[:space:]]*)1;/\10;/' $(SRC_COPY)/config/config.vh - sed -i -E 's/(localparam logic AXI_DMA_SUPPORTED[[:space:]]*=[[:space:]]*)1;/\10;/' $(SRC_COPY)/config/config.vh + sed -i -E 's/(localparam logic XILINX_AXI_DMA_SUPPORTED[[:space:]]*=[[:space:]]*)1;/\10;/' $(SRC_COPY)/config/config.vh sed -i -E 's/(localparam logic AXI_VGA_SUPPORTED[[:space:]]*=[[:space:]]*)1;/\10;/' $(SRC_COPY)/config/config.vh sed -i -E 's/(localparam logic AXI_USB_SUPPORTED[[:space:]]*=[[:space:]]*)1;/\10;/' $(SRC_COPY)/config/config.vh sed -i -E 's/(localparam logic AXI_ETH_SUPPORTED[[:space:]]*=[[:space:]]*)1;/\10;/' $(SRC_COPY)/config/config.vh diff --git a/fpga/src/fpgaTopGenesys2SoC.sv b/fpga/src/fpgaTopGenesys2SoC.sv index 75afddc5b6..5f4fc2766f 100644 --- a/fpga/src/fpgaTopGenesys2SoC.sv +++ b/fpga/src/fpgaTopGenesys2SoC.sv @@ -136,18 +136,21 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) localparam int unsigned AXI_QOS_W = 4; localparam int unsigned AXI_RESP_W = 2; - // XBAR is slave for: CPU, CDMA, VGA, USB - localparam int unsigned N_SLV = 4; - // XBAR is master for: DDR3, CDMA, VGA, USB, LITEETH, LiteDRAM CSR, SDHCI - localparam int unsigned N_MST = 7; + // XBAR is slave for: CPU, CDMA, VGA, USB, iDMA descriptor fetch, iDMA backend + localparam int unsigned N_SLV = 6; + // XBAR is master for: DDR3, CDMA, VGA, USB, LITEETH, LiteDRAM CSR, SDHCI, iDMA desc64, iDMA reg64 + localparam int unsigned N_MST = 9; localparam int unsigned SLV_ID_W = 2; - localparam int unsigned MST_ID_W = SLV_ID_W + $clog2(N_SLV); // 2+2=4 (goes to MIG) - localparam int unsigned N_RULES = 7; + localparam int unsigned MST_ID_W = SLV_ID_W + $clog2(N_SLV); + localparam int unsigned DDR_ID_W = MST_ID_W; + localparam int unsigned N_RULES = 9; localparam int unsigned CB_S_CPU = 0; localparam int unsigned CB_S_CDMA = 1; localparam int unsigned CB_S_VGA = 2; localparam int unsigned CB_S_USB = 3; + localparam int unsigned CB_S_IDMA_FE = 4; + localparam int unsigned CB_S_IDMA_BE = 5; localparam int unsigned CB_M_DDR = 0; localparam int unsigned CB_M_CDMA_REG = 1; @@ -156,6 +159,8 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) localparam int unsigned CB_M_ETH_REG = 4; localparam int unsigned CB_M_DRAM_CSR = 5; localparam int unsigned CB_M_SDHCI = 6; + localparam int unsigned CB_M_IDMA_DESC = 7; + localparam int unsigned CB_M_IDMA_REG64 = 8; localparam int unsigned MIG_ADDR_WIDTH = 30; localparam int unsigned DDR_ADDR_BITS = MIG_ADDR_WIDTH; @@ -186,18 +191,18 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // AHB Signals from Wally logic HCLKOpen; logic HRESETnOpen; - logic [P.AHBW-1:0] HRDATAEXT; - logic HREADYEXT; + (* mark_debug = "true" *) logic [P.AHBW-1:0] HRDATAEXT; + (* mark_debug = "true" *) logic HREADYEXT; (* mark_debug = "true" *) logic HRESPEXT; logic HSELEXT; - logic [55:0] HADDR; - logic [P.AHBW-1:0] HWDATA; - logic [STRB_W-1:0] HWSTRB; - logic HWRITE; - logic [2:0] HSIZE; + (* mark_debug = "true" *) logic [55:0] HADDR; + (* mark_debug = "true" *) logic [P.AHBW-1:0] HWDATA; + (* mark_debug = "true" *) logic [STRB_W-1:0] HWSTRB; + (* mark_debug = "true" *) logic HWRITE; + (* mark_debug = "true" *) logic [2:0] HSIZE; (* mark_debug = "true" *) logic [2:0] HBURST; - logic [1:0] HTRANS; - logic HREADY; + (* mark_debug = "true" *) logic [1:0] HTRANS; + (* mark_debug = "true" *) logic HREADY; (* mark_debug = "true" *) logic [3:0] HPROT; (* mark_debug = "true" *) logic HMASTLOCK; @@ -205,48 +210,48 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) logic [31:0] GPIOIN, GPIOOUT, GPIOEN; // AHB to AXI Bridge Signals - logic [3:0] m_axi_awid; + (* mark_debug = "true" *) logic [3:0] m_axi_awid; (* mark_debug = "true" *) logic [7:0] m_axi_awlen; (* mark_debug = "true" *) logic [2:0] m_axi_awsize; (* mark_debug = "true" *) logic [1:0] m_axi_awburst; - logic [3:0] m_axi_awcache; + (* mark_debug = "true" *) logic [3:0] m_axi_awcache; (* mark_debug = "true" *) logic [31:0] m_axi_awaddr; - logic [2:0] m_axi_awprot; + (* mark_debug = "true" *) logic [2:0] m_axi_awprot; (* mark_debug = "true" *) logic m_axi_awvalid; (* mark_debug = "true" *) logic m_axi_awready; - logic m_axi_awlock; + (* mark_debug = "true" *) logic m_axi_awlock; (* mark_debug = "true" *) logic [P.AHBW-1:0] m_axi_wdata; (* mark_debug = "true" *) logic [STRB_W-1:0] m_axi_wstrb; (* mark_debug = "true" *) logic m_axi_wlast; (* mark_debug = "true" *) logic m_axi_wvalid; (* mark_debug = "true" *) logic m_axi_wready; - logic [3:0] m_axi_bid; - logic [1:0] m_axi_bresp; + (* mark_debug = "true" *) logic [3:0] m_axi_bid; + (* mark_debug = "true" *) logic [1:0] m_axi_bresp; (* mark_debug = "true" *) logic m_axi_bvalid; (* mark_debug = "true" *) logic m_axi_bready; - logic [3:0] m_axi_arid; + (* mark_debug = "true" *) logic [3:0] m_axi_arid; (* mark_debug = "true" *) logic [7:0] m_axi_arlen; - logic [2:0] m_axi_arsize; - logic [1:0] m_axi_arburst; - logic [2:0] m_axi_arprot; - logic [3:0] m_axi_arcache; - logic m_axi_arvalid; - logic [31:0] m_axi_araddr; - logic m_axi_arlock; - logic m_axi_arready; - logic [3:0] m_axi_rid; - logic [P.AHBW-1:0] m_axi_rdata; - logic [1:0] m_axi_rresp; - logic m_axi_rvalid; - logic m_axi_rlast; - logic m_axi_rready; + (* mark_debug = "true" *) logic [2:0] m_axi_arsize; + (* mark_debug = "true" *) logic [1:0] m_axi_arburst; + (* mark_debug = "true" *) logic [2:0] m_axi_arprot; + (* mark_debug = "true" *) logic [3:0] m_axi_arcache; + (* mark_debug = "true" *) logic m_axi_arvalid; + (* mark_debug = "true" *) logic [31:0] m_axi_araddr; + (* mark_debug = "true" *) logic m_axi_arlock; + (* mark_debug = "true" *) logic m_axi_arready; + (* mark_debug = "true" *) logic [3:0] m_axi_rid; + (* mark_debug = "true" *) logic [P.AHBW-1:0] m_axi_rdata; + (* mark_debug = "true" *) logic [1:0] m_axi_rresp; + (* mark_debug = "true" *) logic m_axi_rvalid; + (* mark_debug = "true" *) logic m_axi_rlast; + (* mark_debug = "true" *) logic m_axi_rready; // AXI Signals going out of Clock Converter - logic [3:0] BUS_axi_arregion; - logic [3:0] BUS_axi_arqos; - logic [3:0] BUS_axi_awregion; - logic [3:0] BUS_axi_awqos; - logic [3:0] BUS_axi_awid; + (* mark_debug = "true" *) logic [3:0] BUS_axi_arregion; + (* mark_debug = "true" *) logic [3:0] BUS_axi_arqos; + (* mark_debug = "true" *) logic [3:0] BUS_axi_awregion; + (* mark_debug = "true" *) logic [3:0] BUS_axi_awqos; + (* mark_debug = "true" *) logic [3:0] BUS_axi_awid; (* mark_debug = "true" *) logic [7:0] BUS_axi_awlen; (* mark_debug = "true" *) logic [2:0] BUS_axi_awsize; (* mark_debug = "true" *) logic [1:0] BUS_axi_awburst; @@ -283,30 +288,30 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) (* mark_debug = "true" *) logic BUS_axi_rready; // AXI master Signals going out of Clock Converter (MIG-facing, M00 slice) - logic [3:0] BUS_cb_axi_arregion; - logic [3:0] BUS_cb_axi_arqos; - logic [3:0] BUS_cb_axi_awregion; - logic [3:0] BUS_cb_axi_awqos; - logic [3:0] BUS_cb_axi_awid; + (* mark_debug = "true" *) logic [3:0] BUS_cb_axi_arregion; + (* mark_debug = "true" *) logic [3:0] BUS_cb_axi_arqos; + (* mark_debug = "true" *) logic [3:0] BUS_cb_axi_awregion; + (* mark_debug = "true" *) logic [3:0] BUS_cb_axi_awqos; + (* mark_debug = "true" *) logic [DDR_ID_W-1:0] BUS_cb_axi_awid; (* mark_debug = "true" *) logic [7:0] BUS_cb_axi_awlen; (* mark_debug = "true" *) logic [2:0] BUS_cb_axi_awsize; - logic [1:0] BUS_cb_axi_awburst; + (* mark_debug = "true" *) logic [1:0] BUS_cb_axi_awburst; (* mark_debug = "true" *) logic [3:0] BUS_cb_axi_awcache; (* mark_debug = "true" *) logic [31:0] BUS_cb_axi_awaddr; (* mark_debug = "true" *) logic [2:0] BUS_cb_axi_awprot; (* mark_debug = "true" *) logic BUS_cb_axi_awvalid; (* mark_debug = "true" *) logic BUS_cb_axi_awready; - logic BUS_cb_axi_awlock; + (* mark_debug = "true" *) logic BUS_cb_axi_awlock; (* mark_debug = "true" *) logic [P.AHBW-1:0] BUS_cb_axi_wdata; - logic [STRB_W-1:0] BUS_cb_axi_wstrb; + (* mark_debug = "true" *) logic [STRB_W-1:0] BUS_cb_axi_wstrb; (* mark_debug = "true" *) logic BUS_cb_axi_wlast; (* mark_debug = "true" *) logic BUS_cb_axi_wvalid; (* mark_debug = "true" *) logic BUS_cb_axi_wready; - logic [3:0] BUS_cb_axi_bid; + (* mark_debug = "true" *) logic [DDR_ID_W-1:0] BUS_cb_axi_bid; (* mark_debug = "true" *) logic [1:0] BUS_cb_axi_bresp; (* mark_debug = "true" *) logic BUS_cb_axi_bvalid; (* mark_debug = "true" *) logic BUS_cb_axi_bready; - (* mark_debug = "true" *) logic [3:0] BUS_cb_axi_arid; + (* mark_debug = "true" *) logic [DDR_ID_W-1:0] BUS_cb_axi_arid; (* mark_debug = "true" *) logic [7:0] BUS_cb_axi_arlen; (* mark_debug = "true" *) logic [2:0] BUS_cb_axi_arsize; (* mark_debug = "true" *) logic [1:0] BUS_cb_axi_arburst; @@ -314,9 +319,9 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) (* mark_debug = "true" *) logic [3:0] BUS_cb_axi_arcache; (* mark_debug = "true" *) logic BUS_cb_axi_arvalid; (* mark_debug = "true" *) logic [31:0] BUS_cb_axi_araddr; - logic BUS_cb_axi_arlock; + (* mark_debug = "true" *) logic BUS_cb_axi_arlock; (* mark_debug = "true" *) logic BUS_cb_axi_arready; - (* mark_debug = "true" *) logic [3:0] BUS_cb_axi_rid; + (* mark_debug = "true" *) logic [DDR_ID_W-1:0] BUS_cb_axi_rid; (* mark_debug = "true" *) logic [P.AHBW-1:0] BUS_cb_axi_rdata; (* mark_debug = "true" *) logic [1:0] BUS_cb_axi_rresp; (* mark_debug = "true" *) logic BUS_cb_axi_rvalid; @@ -326,96 +331,96 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // Crossbar packed M_AXI ports // Crossbar uses ADDR_WIDTH=32, DATA_WIDTH=DATA_W, ID_WIDTH=4 // NUM_MI=7 => M00=DDR, M01=CDMA, M02=VGA, M03=USB, M04=LiteEth, M05=LiteDRAM CSR, M06=SDHCI. - wire [N_MST*MST_ID_W-1:0] cb_m_axi_awid; - wire [N_MST*ADDR_W-1:0] cb_m_axi_awaddr; - wire [N_MST*AXI_LEN_W-1:0] cb_m_axi_awlen; - wire [N_MST*AXI_SIZE_W-1:0] cb_m_axi_awsize; - wire [N_MST*AXI_BURST_W-1:0] cb_m_axi_awburst; - wire [N_MST-1:0] cb_m_axi_awlock; - wire [N_MST*AXI_CACHE_W-1:0] cb_m_axi_awcache; - wire [N_MST*AXI_PROT_W-1:0] cb_m_axi_awprot; - wire [N_MST*AXI_QOS_W-1:0] cb_m_axi_awregion; - wire [N_MST*AXI_QOS_W-1:0] cb_m_axi_awqos; - wire [N_MST-1:0] cb_m_axi_awvalid; - wire [N_MST-1:0] cb_m_axi_awready; - - wire [N_MST*DATA_W-1:0] cb_m_axi_wdata; - wire [N_MST*STRB_W-1:0] cb_m_axi_wstrb; - wire [N_MST-1:0] cb_m_axi_wlast; - wire [N_MST-1:0] cb_m_axi_wvalid; - wire [N_MST-1:0] cb_m_axi_wready; - - wire [N_MST*MST_ID_W-1:0] cb_m_axi_bid; - wire [N_MST*AXI_RESP_W-1:0] cb_m_axi_bresp; - wire [N_MST-1:0] cb_m_axi_bvalid; - wire [N_MST-1:0] cb_m_axi_bready; - - wire [N_MST*MST_ID_W-1:0] cb_m_axi_arid; - wire [N_MST*ADDR_W-1:0] cb_m_axi_araddr; - wire [N_MST*AXI_LEN_W-1:0] cb_m_axi_arlen; - wire [N_MST*AXI_SIZE_W-1:0] cb_m_axi_arsize; - wire [N_MST*AXI_BURST_W-1:0] cb_m_axi_arburst; - wire [N_MST-1:0] cb_m_axi_arlock; - wire [N_MST*AXI_CACHE_W-1:0] cb_m_axi_arcache; - wire [N_MST*AXI_PROT_W-1:0] cb_m_axi_arprot; - wire [N_MST*AXI_QOS_W-1:0] cb_m_axi_arregion; - wire [N_MST*AXI_QOS_W-1:0] cb_m_axi_arqos; - wire [N_MST-1:0] cb_m_axi_arvalid; - wire [N_MST-1:0] cb_m_axi_arready; - - wire [N_MST*MST_ID_W-1:0] cb_m_axi_rid; - wire [N_MST*DATA_W-1:0] cb_m_axi_rdata; - wire [N_MST*AXI_RESP_W-1:0] cb_m_axi_rresp; - wire [N_MST-1:0] cb_m_axi_rlast; - wire [N_MST-1:0] cb_m_axi_rvalid; - wire [N_MST-1:0] cb_m_axi_rready; + (* mark_debug = "true" *) wire [N_MST*MST_ID_W-1:0] cb_m_axi_awid; + (* mark_debug = "true" *) wire [N_MST*ADDR_W-1:0] cb_m_axi_awaddr; + (* mark_debug = "true" *) wire [N_MST*AXI_LEN_W-1:0] cb_m_axi_awlen; + (* mark_debug = "true" *) wire [N_MST*AXI_SIZE_W-1:0] cb_m_axi_awsize; + (* mark_debug = "true" *) wire [N_MST*AXI_BURST_W-1:0] cb_m_axi_awburst; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_awlock; + (* mark_debug = "true" *) wire [N_MST*AXI_CACHE_W-1:0] cb_m_axi_awcache; + (* mark_debug = "true" *) wire [N_MST*AXI_PROT_W-1:0] cb_m_axi_awprot; + (* mark_debug = "true" *) wire [N_MST*AXI_QOS_W-1:0] cb_m_axi_awregion; + (* mark_debug = "true" *) wire [N_MST*AXI_QOS_W-1:0] cb_m_axi_awqos; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_awvalid; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_awready; + + (* mark_debug = "true" *) wire [N_MST*DATA_W-1:0] cb_m_axi_wdata; + (* mark_debug = "true" *) wire [N_MST*STRB_W-1:0] cb_m_axi_wstrb; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_wlast; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_wvalid; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_wready; + + (* mark_debug = "true" *) wire [N_MST*MST_ID_W-1:0] cb_m_axi_bid; + (* mark_debug = "true" *) wire [N_MST*AXI_RESP_W-1:0] cb_m_axi_bresp; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_bvalid; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_bready; + + (* mark_debug = "true" *) wire [N_MST*MST_ID_W-1:0] cb_m_axi_arid; + (* mark_debug = "true" *) wire [N_MST*ADDR_W-1:0] cb_m_axi_araddr; + (* mark_debug = "true" *) wire [N_MST*AXI_LEN_W-1:0] cb_m_axi_arlen; + (* mark_debug = "true" *) wire [N_MST*AXI_SIZE_W-1:0] cb_m_axi_arsize; + (* mark_debug = "true" *) wire [N_MST*AXI_BURST_W-1:0] cb_m_axi_arburst; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_arlock; + (* mark_debug = "true" *) wire [N_MST*AXI_CACHE_W-1:0] cb_m_axi_arcache; + (* mark_debug = "true" *) wire [N_MST*AXI_PROT_W-1:0] cb_m_axi_arprot; + (* mark_debug = "true" *) wire [N_MST*AXI_QOS_W-1:0] cb_m_axi_arregion; + (* mark_debug = "true" *) wire [N_MST*AXI_QOS_W-1:0] cb_m_axi_arqos; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_arvalid; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_arready; + + (* mark_debug = "true" *) wire [N_MST*MST_ID_W-1:0] cb_m_axi_rid; + (* mark_debug = "true" *) wire [N_MST*DATA_W-1:0] cb_m_axi_rdata; + (* mark_debug = "true" *) wire [N_MST*AXI_RESP_W-1:0] cb_m_axi_rresp; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_rlast; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_rvalid; + (* mark_debug = "true" *) wire [N_MST-1:0] cb_m_axi_rready; // Crossbar packed S_AXI ports // NUM_SI=4 (S00=CPU, S01=CDMA, S02=VGA, S03=USB OHCI DMA) - wire [N_SLV*MST_ID_W-1:0] cb_s_axi_awid; - wire [N_SLV*ADDR_W-1:0] cb_s_axi_awaddr; - wire [N_SLV*AXI_LEN_W-1:0] cb_s_axi_awlen; - wire [N_SLV*AXI_SIZE_W-1:0] cb_s_axi_awsize; - wire [N_SLV*AXI_BURST_W-1:0] cb_s_axi_awburst; - wire [N_SLV-1:0] cb_s_axi_awlock; - wire [N_SLV*AXI_CACHE_W-1:0] cb_s_axi_awcache; - wire [N_SLV*AXI_PROT_W-1:0] cb_s_axi_awprot; - wire [N_SLV*AXI_QOS_W-1:0] cb_s_axi_awqos; - wire [N_SLV-1:0] cb_s_axi_awvalid; - wire [N_SLV-1:0] cb_s_axi_awready; - - wire [N_SLV*DATA_W-1:0] cb_s_axi_wdata; - wire [N_SLV*STRB_W-1:0] cb_s_axi_wstrb; - wire [N_SLV-1:0] cb_s_axi_wlast; - wire [N_SLV-1:0] cb_s_axi_wvalid; - wire [N_SLV-1:0] cb_s_axi_wready; - - wire [N_SLV*MST_ID_W-1:0] cb_s_axi_bid; - wire [N_SLV*AXI_RESP_W-1:0] cb_s_axi_bresp; - wire [N_SLV-1:0] cb_s_axi_bvalid; - wire [N_SLV-1:0] cb_s_axi_bready; - - wire [N_SLV*MST_ID_W-1:0] cb_s_axi_arid; - wire [N_SLV*ADDR_W-1:0] cb_s_axi_araddr; - wire [N_SLV*AXI_LEN_W-1:0] cb_s_axi_arlen; - wire [N_SLV*AXI_SIZE_W-1:0] cb_s_axi_arsize; - wire [N_SLV*AXI_BURST_W-1:0] cb_s_axi_arburst; - wire [N_SLV-1:0] cb_s_axi_arlock; - wire [N_SLV*AXI_CACHE_W-1:0] cb_s_axi_arcache; - wire [N_SLV*AXI_PROT_W-1:0] cb_s_axi_arprot; - wire [N_SLV*AXI_QOS_W-1:0] cb_s_axi_arqos; - wire [N_SLV-1:0] cb_s_axi_arvalid; - wire [N_SLV-1:0] cb_s_axi_arready; - - wire [N_SLV*MST_ID_W-1:0] cb_s_axi_rid; - wire [N_SLV*DATA_W-1:0] cb_s_axi_rdata; - wire [N_SLV*AXI_RESP_W-1:0] cb_s_axi_rresp; - wire [N_SLV-1:0] cb_s_axi_rlast; - wire [N_SLV-1:0] cb_s_axi_rvalid; - wire [N_SLV-1:0] cb_s_axi_rready; + (* mark_debug = "true" *) wire [N_SLV*MST_ID_W-1:0] cb_s_axi_awid; + (* mark_debug = "true" *) wire [N_SLV*ADDR_W-1:0] cb_s_axi_awaddr; + (* mark_debug = "true" *) wire [N_SLV*AXI_LEN_W-1:0] cb_s_axi_awlen; + (* mark_debug = "true" *) wire [N_SLV*AXI_SIZE_W-1:0] cb_s_axi_awsize; + (* mark_debug = "true" *) wire [N_SLV*AXI_BURST_W-1:0] cb_s_axi_awburst; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_awlock; + (* mark_debug = "true" *) wire [N_SLV*AXI_CACHE_W-1:0] cb_s_axi_awcache; + (* mark_debug = "true" *) wire [N_SLV*AXI_PROT_W-1:0] cb_s_axi_awprot; + (* mark_debug = "true" *) wire [N_SLV*AXI_QOS_W-1:0] cb_s_axi_awqos; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_awvalid; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_awready; + + (* mark_debug = "true" *) wire [N_SLV*DATA_W-1:0] cb_s_axi_wdata; + (* mark_debug = "true" *) wire [N_SLV*STRB_W-1:0] cb_s_axi_wstrb; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_wlast; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_wvalid; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_wready; + + (* mark_debug = "true" *) wire [N_SLV*MST_ID_W-1:0] cb_s_axi_bid; + (* mark_debug = "true" *) wire [N_SLV*AXI_RESP_W-1:0] cb_s_axi_bresp; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_bvalid; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_bready; + + (* mark_debug = "true" *) wire [N_SLV*MST_ID_W-1:0] cb_s_axi_arid; + (* mark_debug = "true" *) wire [N_SLV*ADDR_W-1:0] cb_s_axi_araddr; + (* mark_debug = "true" *) wire [N_SLV*AXI_LEN_W-1:0] cb_s_axi_arlen; + (* mark_debug = "true" *) wire [N_SLV*AXI_SIZE_W-1:0] cb_s_axi_arsize; + (* mark_debug = "true" *) wire [N_SLV*AXI_BURST_W-1:0] cb_s_axi_arburst; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_arlock; + (* mark_debug = "true" *) wire [N_SLV*AXI_CACHE_W-1:0] cb_s_axi_arcache; + (* mark_debug = "true" *) wire [N_SLV*AXI_PROT_W-1:0] cb_s_axi_arprot; + (* mark_debug = "true" *) wire [N_SLV*AXI_QOS_W-1:0] cb_s_axi_arqos; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_arvalid; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_arready; + + (* mark_debug = "true" *) wire [N_SLV*MST_ID_W-1:0] cb_s_axi_rid; + (* mark_debug = "true" *) wire [N_SLV*DATA_W-1:0] cb_s_axi_rdata; + (* mark_debug = "true" *) wire [N_SLV*AXI_RESP_W-1:0] cb_s_axi_rresp; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_rlast; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_rvalid; + (* mark_debug = "true" *) wire [N_SLV-1:0] cb_s_axi_rready; // AXI CDMA M_AXI (master into crossbar S01) - logic [3:0] cdma_m_axi_awid; + logic [SLV_ID_W-1:0] cdma_m_axi_awid; logic [31:0] cdma_m_axi_awaddr; logic [7:0] cdma_m_axi_awlen; logic [2:0] cdma_m_axi_awsize; @@ -430,11 +435,11 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) logic cdma_m_axi_wlast; logic cdma_m_axi_wvalid; logic cdma_m_axi_wready; - logic [3:0] cdma_m_axi_bid; + logic [MST_ID_W-1:0] cdma_m_axi_bid; logic [1:0] cdma_m_axi_bresp; logic cdma_m_axi_bvalid; logic cdma_m_axi_bready; - logic [3:0] cdma_m_axi_arid; + logic [SLV_ID_W-1:0] cdma_m_axi_arid; logic [31:0] cdma_m_axi_araddr; logic [7:0] cdma_m_axi_arlen; logic [2:0] cdma_m_axi_arsize; @@ -444,7 +449,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) logic [2:0] cdma_m_axi_arprot; logic cdma_m_axi_arvalid; logic cdma_m_axi_arready; - logic [3:0] cdma_m_axi_rid; + logic [MST_ID_W-1:0] cdma_m_axi_rid; logic [P.AHBW-1:0] cdma_m_axi_rdata; logic [1:0] cdma_m_axi_rresp; logic cdma_m_axi_rlast; @@ -453,7 +458,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // AXI VGA scanout M_AXI (master into crossbar S02) - logic [3:0] vga_m_axi_awid; + logic [SLV_ID_W-1:0] vga_m_axi_awid; logic [31:0] vga_m_axi_awaddr; logic [7:0] vga_m_axi_awlen; logic [2:0] vga_m_axi_awsize; @@ -470,12 +475,12 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) logic vga_m_axi_wvalid; logic vga_m_axi_wready; - logic [3:0] vga_m_axi_bid; + logic [SLV_ID_W-1:0] vga_m_axi_bid; logic [1:0] vga_m_axi_bresp; logic vga_m_axi_bvalid; logic vga_m_axi_bready; - logic [3:0] vga_m_axi_arid; + logic [SLV_ID_W-1:0] vga_m_axi_arid; logic [31:0] vga_m_axi_araddr; logic [7:0] vga_m_axi_arlen; logic [2:0] vga_m_axi_arsize; @@ -486,7 +491,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) logic vga_m_axi_arvalid; logic vga_m_axi_arready; - logic [3:0] vga_m_axi_rid; + logic [SLV_ID_W-1:0] vga_m_axi_rid; logic [P.AHBW-1:0] vga_m_axi_rdata; logic [1:0] vga_m_axi_rresp; logic vga_m_axi_rlast; @@ -494,7 +499,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) logic vga_m_axi_rready; // USB OHCI DMA M_AXI (master into crossbar S03) - (* mark_debug = "true" *) logic [3:0] usb_m_axi_awid; + (* mark_debug = "true" *) logic [SLV_ID_W-1:0] usb_m_axi_awid; (* mark_debug = "true" *) logic [31:0] usb_m_axi_awaddr; (* mark_debug = "true" *) logic [7:0] usb_m_axi_awlen; (* mark_debug = "true" *) logic [2:0] usb_m_axi_awsize; @@ -511,12 +516,12 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) (* mark_debug = "true" *) logic usb_m_axi_wvalid; (* mark_debug = "true" *) logic usb_m_axi_wready; - (* mark_debug = "true" *) logic [3:0] usb_m_axi_bid; + (* mark_debug = "true" *) logic [SLV_ID_W-1:0] usb_m_axi_bid; (* mark_debug = "true" *) logic [1:0] usb_m_axi_bresp; (* mark_debug = "true" *) logic usb_m_axi_bvalid; (* mark_debug = "true" *) logic usb_m_axi_bready; - (* mark_debug = "true" *) logic [3:0] usb_m_axi_arid; + (* mark_debug = "true" *) logic [SLV_ID_W-1:0] usb_m_axi_arid; (* mark_debug = "true" *) logic [31:0] usb_m_axi_araddr; (* mark_debug = "true" *) logic [7:0] usb_m_axi_arlen; (* mark_debug = "true" *) logic [2:0] usb_m_axi_arsize; @@ -527,7 +532,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) (* mark_debug = "true" *) logic usb_m_axi_arvalid; (* mark_debug = "true" *) logic usb_m_axi_arready; - (* mark_debug = "true" *) logic [3:0] usb_m_axi_rid; + (* mark_debug = "true" *) logic [SLV_ID_W-1:0] usb_m_axi_rid; (* mark_debug = "true" *) logic [P.AHBW-1:0] usb_m_axi_rdata; (* mark_debug = "true" *) logic [1:0] usb_m_axi_rresp; (* mark_debug = "true" *) logic usb_m_axi_rlast; @@ -545,11 +550,11 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) wire reg_arready; wire reg_bvalid; wire [1:0] reg_bresp; - wire [3:0] reg_bid; + wire [MST_ID_W-1:0] reg_bid; wire reg_rvalid; wire reg_rlast; wire [1:0] reg_rresp; - wire [3:0] reg_rid; + wire [MST_ID_W-1:0] reg_rid; wire [P.AHBW-1:0] reg_rdata; // VGA regs window path (M02) signals back to crossbar @@ -558,11 +563,11 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) wire vga_reg_arready; wire vga_reg_bvalid; wire [1:0] vga_reg_bresp; - wire [3:0] vga_reg_bid; + wire [MST_ID_W-1:0] vga_reg_bid; wire vga_reg_rvalid; wire vga_reg_rlast; wire [1:0] vga_reg_rresp; - wire [3:0] vga_reg_rid; + wire [MST_ID_W-1:0] vga_reg_rid; wire [P.AHBW-1:0] vga_reg_rdata; // USB regs window path (M03) signals back to crossbar @@ -571,11 +576,11 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) wire usb_reg_arready; wire usb_reg_bvalid; wire [1:0] usb_reg_bresp; - wire [3:0] usb_reg_bid; + wire [MST_ID_W-1:0] usb_reg_bid; wire usb_reg_rvalid; wire usb_reg_rlast; wire [1:0] usb_reg_rresp; - wire [3:0] usb_reg_rid; + wire [MST_ID_W-1:0] usb_reg_rid; wire [P.AHBW-1:0] usb_reg_rdata; // USB regs window path (M03) signals back to crossbar @@ -584,11 +589,11 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) wire liteeth_reg_arready; wire liteeth_reg_bvalid; wire [1:0] liteeth_reg_bresp; - wire [3:0] liteeth_reg_bid; + wire [MST_ID_W-1:0] liteeth_reg_bid; wire liteeth_reg_rvalid; wire liteeth_reg_rlast; wire [1:0] liteeth_reg_rresp; - wire [3:0] liteeth_reg_rid; + wire [MST_ID_W-1:0] liteeth_reg_rid; wire [P.AHBW-1:0] liteeth_reg_rdata; // LiteDRAM CSR path (M05) signals back to crossbar — declared at module level @@ -599,11 +604,11 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) logic litedram_axi_arready; logic litedram_axi_bvalid; logic [1:0] litedram_axi_bresp; - logic [3:0] litedram_axi_bid; + logic [MST_ID_W-1:0] litedram_axi_bid; logic litedram_axi_rvalid; logic litedram_axi_rlast; logic [1:0] litedram_axi_rresp; - logic [3:0] litedram_axi_rid; + logic [MST_ID_W-1:0] litedram_axi_rid; logic [P.AHBW-1:0] litedram_axi_rdata; // SDHCI regs window path (M06) signals back to crossbar. @@ -612,11 +617,11 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) logic sdhci_reg_arready; logic sdhci_reg_bvalid; logic [1:0] sdhci_reg_bresp; - logic [3:0] sdhci_reg_bid; + logic [MST_ID_W-1:0] sdhci_reg_bid; logic sdhci_reg_rvalid; logic sdhci_reg_rlast; logic [1:0] sdhci_reg_rresp; - logic [3:0] sdhci_reg_rid; + logic [MST_ID_W-1:0] sdhci_reg_rid; logic [P.AHBW-1:0] sdhci_reg_rdata; (* mark_debug = "true" *) logic sd_clk_o; @@ -723,16 +728,18 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) wire pc_lite_rvalid; wire pc_lite_rready; - wire dma_introut; + (* mark_debug = "true" *) logic dma_irq_raw; logic dma_introut_sync; + logic axi_dma_intr_sync; + (* ASYNC_REG="TRUE" *) logic [1:0] dma_irq_sync; logic usb_phy_resetn_sync; // IMPORTANT: the generated AXI CDMA instance in this project is an ID-less / lock-less AXI master. // It does not expose m_axi_awid/arid/bid/rid nor m_axi_awlock/arlock ports. - // To satisfy the crossbar (ID_WIDTH=4, THREAD_ID_WIDTH=3) we drive those missing sidebands to 0. - assign cdma_m_axi_awid = 4'b0000; - assign cdma_m_axi_arid = 4'b0000; + // To satisfy the crossbar source-port ID sideband, drive those missing IDs to 0. + assign cdma_m_axi_awid = '0; + assign cdma_m_axi_arid = '0; assign cdma_m_axi_awlock = 1'b0; assign cdma_m_axi_arlock = 1'b0; @@ -809,7 +816,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) assign BUS_cb_axi_rready = cb_m_axi_rready[CB_M_DDR]; // Pack crossbar S_AXI (S00=CPU/BUS, S01=CDMA, S02=VGA, S03=USB OHCI DMA). - // Crossbar SI thread IDs are 2 bits, so keep only the low 2 bits in each 4-bit packed ID slot. + // Crossbar source-port thread IDs are SLV_ID_W bits; the xbar adds the port tag internally. assign cb_s_axi_awid[CB_S_CPU*MST_ID_W +: MST_ID_W] = {{(MST_ID_W-SLV_ID_W){1'b0}}, BUS_axi_awid[SLV_ID_W-1:0]}; assign cb_s_axi_awid[CB_S_CDMA*MST_ID_W +: MST_ID_W] = {{(MST_ID_W-SLV_ID_W){1'b0}}, cdma_m_axi_awid[SLV_ID_W-1:0]}; assign cb_s_axi_awid[CB_S_VGA*MST_ID_W +: MST_ID_W] = {{(MST_ID_W-SLV_ID_W){1'b0}}, vga_m_axi_awid[SLV_ID_W-1:0]}; @@ -971,12 +978,12 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) assign vga_m_axi_wready = cb_s_axi_wready[CB_S_VGA]; assign vga_m_axi_bvalid = cb_s_axi_bvalid[CB_S_VGA]; assign vga_m_axi_bresp = cb_s_axi_bresp[CB_S_VGA*AXI_RESP_W +: AXI_RESP_W]; - assign vga_m_axi_bid = cb_s_axi_bid[CB_S_VGA*MST_ID_W +: MST_ID_W]; + assign vga_m_axi_bid = cb_s_axi_bid[CB_S_VGA*MST_ID_W +: SLV_ID_W]; assign vga_m_axi_arready = cb_s_axi_arready[CB_S_VGA]; assign vga_m_axi_rvalid = cb_s_axi_rvalid[CB_S_VGA]; assign vga_m_axi_rlast = cb_s_axi_rlast[CB_S_VGA]; assign vga_m_axi_rresp = cb_s_axi_rresp[CB_S_VGA*AXI_RESP_W +: AXI_RESP_W]; - assign vga_m_axi_rid = cb_s_axi_rid[CB_S_VGA*MST_ID_W +: MST_ID_W]; + assign vga_m_axi_rid = cb_s_axi_rid[CB_S_VGA*MST_ID_W +: SLV_ID_W]; assign vga_m_axi_rdata = cb_s_axi_rdata[CB_S_VGA*DATA_W +: DATA_W]; // Split back to USB OHCI DMA master (S03) @@ -984,12 +991,12 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) assign usb_m_axi_wready = cb_s_axi_wready[CB_S_USB]; assign usb_m_axi_bvalid = cb_s_axi_bvalid[CB_S_USB]; assign usb_m_axi_bresp = cb_s_axi_bresp[CB_S_USB*AXI_RESP_W +: AXI_RESP_W]; - assign usb_m_axi_bid = cb_s_axi_bid[CB_S_USB*MST_ID_W +: MST_ID_W]; + assign usb_m_axi_bid = cb_s_axi_bid[CB_S_USB*MST_ID_W +: SLV_ID_W]; assign usb_m_axi_arready = cb_s_axi_arready[CB_S_USB]; assign usb_m_axi_rvalid = cb_s_axi_rvalid[CB_S_USB]; assign usb_m_axi_rlast = cb_s_axi_rlast[CB_S_USB]; assign usb_m_axi_rresp = cb_s_axi_rresp[CB_S_USB*AXI_RESP_W +: AXI_RESP_W]; - assign usb_m_axi_rid = cb_s_axi_rid[CB_S_USB*MST_ID_W +: MST_ID_W]; + assign usb_m_axi_rid = cb_s_axi_rid[CB_S_USB*MST_ID_W +: SLV_ID_W]; assign usb_m_axi_rdata = cb_s_axi_rdata[CB_S_USB*DATA_W +: DATA_W]; @@ -1220,8 +1227,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) .WB_RMII_MDIO, .WB_RMII_RST_N, .WB_RMII_PHY_IRQ - //, .AXI_DMAIntr(dma_introut) - , .AXI_DMAIntr(dma_introut_sync) + , .AXI_DMAIntr(axi_dma_intr_sync) //, .AXI_USBIntr(usb_irq) , .AXI_USBIntr(usb_irq_ff2) , .AXI_EthIntr(liteeth_irq_ff2) @@ -1387,6 +1393,114 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) `AXI_TYPEDEF_REQ_T (mst_req_t, mst_aw_t, axi_w_t, mst_ar_t) `AXI_TYPEDEF_RESP_T (mst_resp_t, mst_b_t, mst_r_t) + (* mark_debug = "true" *) slv_req_t [1:0] idma_xbar_mst_req; + (* mark_debug = "true" *) slv_resp_t [1:0] idma_xbar_mst_rsp; + (* mark_debug = "true" *) mst_req_t [1:0] idma_xbar_slv_req; + (* mark_debug = "true" *) mst_resp_t [1:0] idma_xbar_slv_rsp; + + localparam int unsigned IDMA_XBAR_S_PORTS [2] = '{CB_S_IDMA_FE, CB_S_IDMA_BE}; + localparam int unsigned IDMA_XBAR_M_PORTS [2] = '{CB_M_IDMA_DESC, CB_M_IDMA_REG64}; + + for (genvar i = 0; i < 2; i++) begin : gen_idma_xbar_s_pack + localparam int unsigned S = IDMA_XBAR_S_PORTS[i]; + + assign cb_s_axi_awid[S*MST_ID_W +: MST_ID_W] = {{(MST_ID_W-SLV_ID_W){1'b0}}, idma_xbar_mst_req[i].aw.id}; + assign cb_s_axi_awaddr[S*ADDR_W +: ADDR_W] = idma_xbar_mst_req[i].aw.addr; + assign cb_s_axi_awlen[S*AXI_LEN_W +: AXI_LEN_W] = idma_xbar_mst_req[i].aw.len; + assign cb_s_axi_awsize[S*AXI_SIZE_W +: AXI_SIZE_W] = idma_xbar_mst_req[i].aw.size; + assign cb_s_axi_awburst[S*AXI_BURST_W +: AXI_BURST_W] = idma_xbar_mst_req[i].aw.burst; + assign cb_s_axi_awlock[S] = idma_xbar_mst_req[i].aw.lock; + assign cb_s_axi_awcache[S*AXI_CACHE_W +: AXI_CACHE_W] = idma_xbar_mst_req[i].aw.cache; + assign cb_s_axi_awprot[S*AXI_PROT_W +: AXI_PROT_W] = idma_xbar_mst_req[i].aw.prot; + assign cb_s_axi_awqos[S*AXI_QOS_W +: AXI_QOS_W] = idma_xbar_mst_req[i].aw.qos; + assign cb_s_axi_awvalid[S] = idma_xbar_mst_req[i].aw_valid; + assign idma_xbar_mst_rsp[i].aw_ready = cb_s_axi_awready[S]; + + assign cb_s_axi_wdata[S*DATA_W +: DATA_W] = idma_xbar_mst_req[i].w.data; + assign cb_s_axi_wstrb[S*STRB_W +: STRB_W] = idma_xbar_mst_req[i].w.strb; + assign cb_s_axi_wlast[S] = idma_xbar_mst_req[i].w.last; + assign cb_s_axi_wvalid[S] = idma_xbar_mst_req[i].w_valid; + assign idma_xbar_mst_rsp[i].w_ready = cb_s_axi_wready[S]; + + assign cb_s_axi_bready[S] = idma_xbar_mst_req[i].b_ready; + assign idma_xbar_mst_rsp[i].b_valid = cb_s_axi_bvalid[S]; + assign idma_xbar_mst_rsp[i].b.id = cb_s_axi_bid[S*MST_ID_W +: SLV_ID_W]; + assign idma_xbar_mst_rsp[i].b.resp = cb_s_axi_bresp[S*AXI_RESP_W +: AXI_RESP_W]; + assign idma_xbar_mst_rsp[i].b.user = '0; + + assign cb_s_axi_arid[S*MST_ID_W +: MST_ID_W] = {{(MST_ID_W-SLV_ID_W){1'b0}}, idma_xbar_mst_req[i].ar.id}; + assign cb_s_axi_araddr[S*ADDR_W +: ADDR_W] = idma_xbar_mst_req[i].ar.addr; + assign cb_s_axi_arlen[S*AXI_LEN_W +: AXI_LEN_W] = idma_xbar_mst_req[i].ar.len; + assign cb_s_axi_arsize[S*AXI_SIZE_W +: AXI_SIZE_W] = idma_xbar_mst_req[i].ar.size; + assign cb_s_axi_arburst[S*AXI_BURST_W +: AXI_BURST_W] = idma_xbar_mst_req[i].ar.burst; + assign cb_s_axi_arlock[S] = idma_xbar_mst_req[i].ar.lock; + assign cb_s_axi_arcache[S*AXI_CACHE_W +: AXI_CACHE_W] = idma_xbar_mst_req[i].ar.cache; + assign cb_s_axi_arprot[S*AXI_PROT_W +: AXI_PROT_W] = idma_xbar_mst_req[i].ar.prot; + assign cb_s_axi_arqos[S*AXI_QOS_W +: AXI_QOS_W] = idma_xbar_mst_req[i].ar.qos; + assign cb_s_axi_arvalid[S] = idma_xbar_mst_req[i].ar_valid; + assign idma_xbar_mst_rsp[i].ar_ready = cb_s_axi_arready[S]; + + assign cb_s_axi_rready[S] = idma_xbar_mst_req[i].r_ready; + assign idma_xbar_mst_rsp[i].r_valid = cb_s_axi_rvalid[S]; + assign idma_xbar_mst_rsp[i].r.id = cb_s_axi_rid[S*MST_ID_W +: SLV_ID_W]; + assign idma_xbar_mst_rsp[i].r.data = cb_s_axi_rdata[S*DATA_W +: DATA_W]; + assign idma_xbar_mst_rsp[i].r.resp = cb_s_axi_rresp[S*AXI_RESP_W +: AXI_RESP_W]; + assign idma_xbar_mst_rsp[i].r.last = cb_s_axi_rlast[S]; + assign idma_xbar_mst_rsp[i].r.user = '0; + end + + for (genvar i = 0; i < 2; i++) begin : gen_idma_xbar_m_unpack + localparam int unsigned M = IDMA_XBAR_M_PORTS[i]; + + assign idma_xbar_slv_req[i].aw.id = cb_m_axi_awid[M*MST_ID_W +: MST_ID_W]; + assign idma_xbar_slv_req[i].aw.addr = cb_m_axi_awaddr[M*ADDR_W +: ADDR_W]; + assign idma_xbar_slv_req[i].aw.len = cb_m_axi_awlen[M*AXI_LEN_W +: AXI_LEN_W]; + assign idma_xbar_slv_req[i].aw.size = cb_m_axi_awsize[M*AXI_SIZE_W +: AXI_SIZE_W]; + assign idma_xbar_slv_req[i].aw.burst = cb_m_axi_awburst[M*AXI_BURST_W +: AXI_BURST_W]; + assign idma_xbar_slv_req[i].aw.lock = cb_m_axi_awlock[M]; + assign idma_xbar_slv_req[i].aw.cache = cb_m_axi_awcache[M*AXI_CACHE_W +: AXI_CACHE_W]; + assign idma_xbar_slv_req[i].aw.prot = cb_m_axi_awprot[M*AXI_PROT_W +: AXI_PROT_W]; + assign idma_xbar_slv_req[i].aw.qos = cb_m_axi_awqos[M*AXI_QOS_W +: AXI_QOS_W]; + assign idma_xbar_slv_req[i].aw.region = cb_m_axi_awregion[M*AXI_QOS_W +: AXI_QOS_W]; + assign idma_xbar_slv_req[i].aw.atop = '0; + assign idma_xbar_slv_req[i].aw.user = '0; + assign idma_xbar_slv_req[i].aw_valid = cb_m_axi_awvalid[M]; + assign cb_m_axi_awready[M] = idma_xbar_slv_rsp[i].aw_ready; + + assign idma_xbar_slv_req[i].w.data = cb_m_axi_wdata[M*DATA_W +: DATA_W]; + assign idma_xbar_slv_req[i].w.strb = cb_m_axi_wstrb[M*STRB_W +: STRB_W]; + assign idma_xbar_slv_req[i].w.last = cb_m_axi_wlast[M]; + assign idma_xbar_slv_req[i].w.user = '0; + assign idma_xbar_slv_req[i].w_valid = cb_m_axi_wvalid[M]; + assign cb_m_axi_wready[M] = idma_xbar_slv_rsp[i].w_ready; + + assign idma_xbar_slv_req[i].b_ready = cb_m_axi_bready[M]; + assign cb_m_axi_bvalid[M] = idma_xbar_slv_rsp[i].b_valid; + assign cb_m_axi_bresp[M*AXI_RESP_W +: AXI_RESP_W] = idma_xbar_slv_rsp[i].b.resp; + assign cb_m_axi_bid[M*MST_ID_W +: MST_ID_W] = idma_xbar_slv_rsp[i].b.id; + + assign idma_xbar_slv_req[i].ar.id = cb_m_axi_arid[M*MST_ID_W +: MST_ID_W]; + assign idma_xbar_slv_req[i].ar.addr = cb_m_axi_araddr[M*ADDR_W +: ADDR_W]; + assign idma_xbar_slv_req[i].ar.len = cb_m_axi_arlen[M*AXI_LEN_W +: AXI_LEN_W]; + assign idma_xbar_slv_req[i].ar.size = cb_m_axi_arsize[M*AXI_SIZE_W +: AXI_SIZE_W]; + assign idma_xbar_slv_req[i].ar.burst = cb_m_axi_arburst[M*AXI_BURST_W +: AXI_BURST_W]; + assign idma_xbar_slv_req[i].ar.lock = cb_m_axi_arlock[M]; + assign idma_xbar_slv_req[i].ar.cache = cb_m_axi_arcache[M*AXI_CACHE_W +: AXI_CACHE_W]; + assign idma_xbar_slv_req[i].ar.prot = cb_m_axi_arprot[M*AXI_PROT_W +: AXI_PROT_W]; + assign idma_xbar_slv_req[i].ar.qos = cb_m_axi_arqos[M*AXI_QOS_W +: AXI_QOS_W]; + assign idma_xbar_slv_req[i].ar.region = cb_m_axi_arregion[M*AXI_QOS_W +: AXI_QOS_W]; + assign idma_xbar_slv_req[i].ar.user = '0; + assign idma_xbar_slv_req[i].ar_valid = cb_m_axi_arvalid[M]; + assign cb_m_axi_arready[M] = idma_xbar_slv_rsp[i].ar_ready; + + assign idma_xbar_slv_req[i].r_ready = cb_m_axi_rready[M]; + assign cb_m_axi_rvalid[M] = idma_xbar_slv_rsp[i].r_valid; + assign cb_m_axi_rdata[M*DATA_W +: DATA_W] = idma_xbar_slv_rsp[i].r.data; + assign cb_m_axi_rresp[M*AXI_RESP_W +: AXI_RESP_W] = idma_xbar_slv_rsp[i].r.resp; + assign cb_m_axi_rlast[M] = idma_xbar_slv_rsp[i].r.last; + assign cb_m_axi_rid[M*MST_ID_W +: MST_ID_W] = idma_xbar_slv_rsp[i].r.id; + end + localparam int unsigned AXI_USER_W = 1; typedef logic [AXI_USER_W-1:0] axi_user_t; //what is this for? @@ -1771,14 +1885,6 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // 4'b0001, // S02 // 4'b0001 // S03 // }; - // Still doesn't work - //localparam bit [N_MST-1:0][N_SLV-1:0] CONN = '{ - // 4'b1111, // M00 (DDR) <- allow all S ports - // 4'b0001, // M01 (CDMA regs) <- allow only S00 (CPU) - // 4'b0001, // M02 (VGA regs) <- allow only S00 - // 4'b0001 // M03 (USB regs) <- allow only S00 - //}; - // Address map rules (end_addr is exclusive) //localparam axi_pkg::xbar_rule_32_t ADDR_MAP [N_RULES-1:0] = '{ localparam axi_pkg::xbar_rule_32_t [N_RULES-1:0] ADDR_MAP = '{ @@ -1788,14 +1894,22 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) end_addr: axi_addr_t'(64'h8000_0000 + (64'(1) << DDR_ADDR_BITS)) }, // register windows - '{ idx: 1, start_addr: 32'h100A_0000, end_addr: 32'h100A_1000 }, // CDMA regs + '{ idx: CB_M_CDMA_REG, + start_addr: axi_addr_t'(P.XILINX_AXI_DMA_BASE[31:0]), + end_addr: axi_addr_t'(P.XILINX_AXI_DMA_BASE[31:0] + P.XILINX_AXI_DMA_RANGE[31:0] + 32'd1) }, // CDMA regs '{ idx: 2, start_addr: 32'h100B_0000, end_addr: 32'h100B_1000 }, // VGA regs '{ idx: 3, start_addr: 32'h100C_0000, end_addr: 32'h100C_1000 }, // USB regs '{ idx: 4, start_addr: 32'h100D_0000, end_addr: 32'h100F_0000 }, // AXI ETH regs '{ idx: 5, start_addr: 32'h100F_0000, end_addr: 32'h100F_2000 }, // LiteDRAM CSR interface '{ idx: 6, start_addr: axi_addr_t'(P.AXI_SDHCI_BASE[31:0]), - end_addr: axi_addr_t'(P.AXI_SDHCI_BASE[31:0] + P.AXI_SDHCI_RANGE[31:0] + 32'd1) } // SDHCI regs + end_addr: axi_addr_t'(P.AXI_SDHCI_BASE[31:0] + P.AXI_SDHCI_RANGE[31:0] + 32'd1) }, // SDHCI regs + '{ idx: CB_M_IDMA_DESC, + start_addr: axi_addr_t'(P.AXI_IDMA_BASE[31:0]), + end_addr: axi_addr_t'(P.AXI_IDMA_BASE[31:0] + P.AXI_IDMA_RANGE[31:0] + 32'd1) }, // iDMA desc64 regs + '{ idx: CB_M_IDMA_REG64, + start_addr: axi_addr_t'(P.AXI_IDMA_REG64_BASE[31:0]), + end_addr: axi_addr_t'(P.AXI_IDMA_REG64_BASE[31:0] + P.AXI_IDMA_REG64_RANGE[31:0] + 32'd1) } // iDMA reg64 regs }; // ------------------------------ @@ -1954,6 +2068,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) .AXI_ADDR_W ( ADDR_W ), .AXI_DATA_W ( DATA_W ), .AXI_ID_W ( MST_ID_W ), + .AXI_M_ID_W ( SLV_ID_W ), .AXI_USER_W ( 1 ) ) axi_vga_wrap_i ( .aclk (BUSCLK), @@ -2258,7 +2373,13 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) .m_axil_rready ( usb_lite_rready ) ); end else begin : gen_usb_axi64_to_axilite32 - axi64_mmio_to_axilite32_v2 mmio_usbregs ( + // Switched from axi64_mmio_to_axilite32_v2 to parameterized v3 for MST_ID_W IDs. + // This USB register path must be re-tested. + axi_mmio_to_axilite32_v3 #( + .AXI_ADDR_WIDTH ( ADDR_W ), + .AXI_DATA_WIDTH ( DATA_W ), + .AXI_ID_WIDTH ( MST_ID_W ) + ) mmio_usbregs ( .aclk(BUSCLK), .aresetn(BUSRSTn), @@ -2342,7 +2463,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // NOTE: phy_clk should be 48 MHz (or another integer multiple of 12 MHz). rmii_clk50 is only a placeholder. usb_ohci_wrap #( .DMA_AXI_DATA_WIDTH ( DATA_W ), - .DMA_AXI_ID_WIDTH ( MST_ID_W ) + .DMA_AXI_ID_WIDTH ( SLV_ID_W ) ) usb_ohci_i ( // Clocks / resets .ctrl_clk (BUSCLK), @@ -2846,11 +2967,11 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) assign sdhci_reg_arready = 1'b0; assign sdhci_reg_bvalid = 1'b0; assign sdhci_reg_bresp = 2'b00; - assign sdhci_reg_bid = 4'b0000; + assign sdhci_reg_bid = '0; assign sdhci_reg_rvalid = 1'b0; assign sdhci_reg_rlast = 1'b0; assign sdhci_reg_rresp = 2'b00; - assign sdhci_reg_rid = 4'b0000; + assign sdhci_reg_rid = '0; assign sdhci_reg_rdata = '0; end @@ -2865,152 +2986,302 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) end - // M01 -> MMIO bridge -> AXI4-Lite/32 -> CDMA regs - axi64_mmio_to_axilite32_v2 mmio_cdmaregs ( - .aclk(BUSCLK), - .aresetn(BUSRSTn), - - // AXI4 slave side from crossbar M01 - .s_axi_awid (cb_m_axi_awid[CB_M_CDMA_REG*MST_ID_W +: MST_ID_W]), - .s_axi_awaddr (cb_m_axi_awaddr[CB_M_CDMA_REG*ADDR_W +: ADDR_W]), - .s_axi_awlen (cb_m_axi_awlen[CB_M_CDMA_REG*AXI_LEN_W +: AXI_LEN_W]), - .s_axi_awsize (cb_m_axi_awsize[CB_M_CDMA_REG*AXI_SIZE_W +: AXI_SIZE_W]), - .s_axi_awburst (cb_m_axi_awburst[CB_M_CDMA_REG*AXI_BURST_W +: AXI_BURST_W]), - .s_axi_awvalid (cb_m_axi_awvalid[CB_M_CDMA_REG]), - .s_axi_awready (reg_awready), - - .s_axi_wdata (cb_m_axi_wdata[CB_M_CDMA_REG*DATA_W +: DATA_W]), - .s_axi_wstrb (cb_m_axi_wstrb[CB_M_CDMA_REG*STRB_W +: STRB_W]), - .s_axi_wlast (cb_m_axi_wlast[CB_M_CDMA_REG]), - .s_axi_wvalid (cb_m_axi_wvalid[CB_M_CDMA_REG]), - .s_axi_wready (reg_wready), - - .s_axi_bresp (reg_bresp), - .s_axi_bvalid (reg_bvalid), - .s_axi_bid (reg_bid), - .s_axi_bready (cb_m_axi_bready[CB_M_CDMA_REG]), - - .s_axi_arid (cb_m_axi_arid[CB_M_CDMA_REG*MST_ID_W +: MST_ID_W]), - .s_axi_araddr (cb_m_axi_araddr[CB_M_CDMA_REG*ADDR_W +: ADDR_W]), - .s_axi_arlen (cb_m_axi_arlen[CB_M_CDMA_REG*AXI_LEN_W +: AXI_LEN_W]), - .s_axi_arsize (cb_m_axi_arsize[CB_M_CDMA_REG*AXI_SIZE_W +: AXI_SIZE_W]), - .s_axi_arburst (cb_m_axi_arburst[CB_M_CDMA_REG*AXI_BURST_W +: AXI_BURST_W]), - .s_axi_arvalid (cb_m_axi_arvalid[CB_M_CDMA_REG]), - .s_axi_arready (reg_arready), - - .s_axi_rdata (reg_rdata), - .s_axi_rresp (reg_rresp), - .s_axi_rlast (reg_rlast), - .s_axi_rvalid (reg_rvalid), - .s_axi_rid (reg_rid), - .s_axi_rready (cb_m_axi_rready[CB_M_CDMA_REG]), - - // AXI4-Lite master side to CDMA - .m_axil_awaddr (pc_lite_awaddr), - .m_axil_awprot (pc_lite_awprot), - .m_axil_awvalid(pc_lite_awvalid), - .m_axil_awready(pc_lite_awready), - - .m_axil_wdata (pc_lite_wdata), - .m_axil_wstrb (pc_lite_wstrb), - .m_axil_wvalid (pc_lite_wvalid), - .m_axil_wready (pc_lite_wready), - - .m_axil_bresp (pc_lite_bresp), - .m_axil_bvalid (pc_lite_bvalid), - .m_axil_bready (pc_lite_bready), - - .m_axil_araddr (pc_lite_araddr), - .m_axil_arprot (pc_lite_arprot), - .m_axil_arvalid(pc_lite_arvalid), - .m_axil_arready(pc_lite_arready), - - .m_axil_rdata (pc_lite_rdata), - .m_axil_rresp (pc_lite_rresp), - .m_axil_rvalid (pc_lite_rvalid), - .m_axil_rready (pc_lite_rready) - ); + if (P.XILINX_AXI_DMA_SUPPORTED) begin : gen_axicdma + assign idma_xbar_mst_req = '0; + assign idma_xbar_slv_rsp = '0; - // SYNC CDMA INT signal in different clock domain - // latch/synchronize CDMA interrupt request coming from a different clock domain after two flip-flops - (* ASYNC_REG="TRUE" *) logic [1:0] dma_irq_sync; + // M01 -> MMIO bridge -> AXI4-Lite/32 -> CDMA regs + // Switched from axi64_mmio_to_axilite32_v2 to parameterized v3 for MST_ID_W IDs. + // This CDMA register path has not been re-tested after the adapter change. + axi_mmio_to_axilite32_v3 #( + .AXI_ADDR_WIDTH ( ADDR_W ), + .AXI_DATA_WIDTH ( DATA_W ), + .AXI_ID_WIDTH ( MST_ID_W ) + ) mmio_cdmaregs ( + .aclk(BUSCLK), + .aresetn(BUSRSTn), + + // AXI4 slave side from crossbar M01 + .s_axi_awid (cb_m_axi_awid[CB_M_CDMA_REG*MST_ID_W +: MST_ID_W]), + .s_axi_awaddr (cb_m_axi_awaddr[CB_M_CDMA_REG*ADDR_W +: ADDR_W]), + .s_axi_awlen (cb_m_axi_awlen[CB_M_CDMA_REG*AXI_LEN_W +: AXI_LEN_W]), + .s_axi_awsize (cb_m_axi_awsize[CB_M_CDMA_REG*AXI_SIZE_W +: AXI_SIZE_W]), + .s_axi_awburst (cb_m_axi_awburst[CB_M_CDMA_REG*AXI_BURST_W +: AXI_BURST_W]), + .s_axi_awvalid (cb_m_axi_awvalid[CB_M_CDMA_REG]), + .s_axi_awready (reg_awready), + + .s_axi_wdata (cb_m_axi_wdata[CB_M_CDMA_REG*DATA_W +: DATA_W]), + .s_axi_wstrb (cb_m_axi_wstrb[CB_M_CDMA_REG*STRB_W +: STRB_W]), + .s_axi_wlast (cb_m_axi_wlast[CB_M_CDMA_REG]), + .s_axi_wvalid (cb_m_axi_wvalid[CB_M_CDMA_REG]), + .s_axi_wready (reg_wready), + + .s_axi_bresp (reg_bresp), + .s_axi_bvalid (reg_bvalid), + .s_axi_bid (reg_bid), + .s_axi_bready (cb_m_axi_bready[CB_M_CDMA_REG]), + + .s_axi_arid (cb_m_axi_arid[CB_M_CDMA_REG*MST_ID_W +: MST_ID_W]), + .s_axi_araddr (cb_m_axi_araddr[CB_M_CDMA_REG*ADDR_W +: ADDR_W]), + .s_axi_arlen (cb_m_axi_arlen[CB_M_CDMA_REG*AXI_LEN_W +: AXI_LEN_W]), + .s_axi_arsize (cb_m_axi_arsize[CB_M_CDMA_REG*AXI_SIZE_W +: AXI_SIZE_W]), + .s_axi_arburst (cb_m_axi_arburst[CB_M_CDMA_REG*AXI_BURST_W +: AXI_BURST_W]), + .s_axi_arvalid (cb_m_axi_arvalid[CB_M_CDMA_REG]), + .s_axi_arready (reg_arready), + + .s_axi_rdata (reg_rdata), + .s_axi_rresp (reg_rresp), + .s_axi_rlast (reg_rlast), + .s_axi_rvalid (reg_rvalid), + .s_axi_rid (reg_rid), + .s_axi_rready (cb_m_axi_rready[CB_M_CDMA_REG]), + + // AXI4-Lite master side to CDMA + .m_axil_awaddr (pc_lite_awaddr), + .m_axil_awprot (pc_lite_awprot), + .m_axil_awvalid(pc_lite_awvalid), + .m_axil_awready(pc_lite_awready), + + .m_axil_wdata (pc_lite_wdata), + .m_axil_wstrb (pc_lite_wstrb), + .m_axil_wvalid (pc_lite_wvalid), + .m_axil_wready (pc_lite_wready), + + .m_axil_bresp (pc_lite_bresp), + .m_axil_bvalid (pc_lite_bvalid), + .m_axil_bready (pc_lite_bready), + + .m_axil_araddr (pc_lite_araddr), + .m_axil_arprot (pc_lite_arprot), + .m_axil_arvalid(pc_lite_arvalid), + .m_axil_arready(pc_lite_arready), + + .m_axil_rdata (pc_lite_rdata), + .m_axil_rresp (pc_lite_rresp), + .m_axil_rvalid (pc_lite_rvalid), + .m_axil_rready (pc_lite_rready) + ); + + axicdma axicdma ( + .m_axi_aclk (BUSCLK), + .s_axi_lite_aclk (BUSCLK), + .s_axi_lite_aresetn(BUSRSTn), + + // AXI4-Lite control + // This project generates CDMA with a small AXI4-Lite address port (6 bits). + // Base address decode is done in the crossbar; CDMA only needs low bits for register offsets. + .s_axi_lite_awaddr (pc_lite_awaddr[5:0]), + .s_axi_lite_awvalid(pc_lite_awvalid), + .s_axi_lite_awready(pc_lite_awready), + + .s_axi_lite_wdata (pc_lite_wdata), + .s_axi_lite_wvalid (pc_lite_wvalid), + .s_axi_lite_wready (pc_lite_wready), + + .s_axi_lite_bresp (pc_lite_bresp), + .s_axi_lite_bvalid (pc_lite_bvalid), + .s_axi_lite_bready (pc_lite_bready), + + .s_axi_lite_araddr (pc_lite_araddr[5:0]), + .s_axi_lite_arvalid(pc_lite_arvalid), + .s_axi_lite_arready(pc_lite_arready), + + .s_axi_lite_rdata (pc_lite_rdata), + .s_axi_lite_rresp (pc_lite_rresp), + .s_axi_lite_rvalid (pc_lite_rvalid), + .s_axi_lite_rready (pc_lite_rready), + + // AXI4 MM2MM master into crossbar S01 + .m_axi_awaddr (cdma_m_axi_awaddr), + .m_axi_awlen (cdma_m_axi_awlen), + .m_axi_awsize (cdma_m_axi_awsize), + .m_axi_awburst (cdma_m_axi_awburst), + .m_axi_awcache (cdma_m_axi_awcache), + .m_axi_awprot (cdma_m_axi_awprot), + .m_axi_awvalid (cdma_m_axi_awvalid), + .m_axi_awready (cdma_m_axi_awready), + + .m_axi_wdata (cdma_m_axi_wdata), + .m_axi_wstrb (cdma_m_axi_wstrb), + .m_axi_wlast (cdma_m_axi_wlast), + .m_axi_wvalid (cdma_m_axi_wvalid), + .m_axi_wready (cdma_m_axi_wready), + + .m_axi_bresp (cdma_m_axi_bresp), + .m_axi_bvalid (cdma_m_axi_bvalid), + .m_axi_bready (cdma_m_axi_bready), + + .m_axi_araddr (cdma_m_axi_araddr), + .m_axi_arlen (cdma_m_axi_arlen), + .m_axi_arsize (cdma_m_axi_arsize), + .m_axi_arburst (cdma_m_axi_arburst), + .m_axi_arcache (cdma_m_axi_arcache), + .m_axi_arprot (cdma_m_axi_arprot), + .m_axi_arvalid (cdma_m_axi_arvalid), + .m_axi_arready (cdma_m_axi_arready), + + .m_axi_rdata (cdma_m_axi_rdata), + .m_axi_rresp (cdma_m_axi_rresp), + .m_axi_rlast (cdma_m_axi_rlast), + .m_axi_rvalid (cdma_m_axi_rvalid), + .m_axi_rready (cdma_m_axi_rready), + + .cdma_introut (dma_irq_raw) + ); + end else if (P.AXI_IDMA_SUPPORTED || P.AXI_IDMA_REG64_SUPPORTED) begin : gen_idma + assign reg_awready = 1'b0; + assign reg_wready = 1'b0; + assign reg_arready = 1'b0; + assign reg_bvalid = 1'b0; + assign reg_bresp = 2'b00; + assign reg_bid = '0; + assign reg_rvalid = 1'b0; + assign reg_rlast = 1'b0; + assign reg_rresp = 2'b00; + assign reg_rid = '0; + assign reg_rdata = '0; + + assign pc_lite_awaddr = '0; + assign pc_lite_awprot = '0; + assign pc_lite_awvalid = 1'b0; + assign pc_lite_awready = 1'b0; + assign pc_lite_wdata = '0; + assign pc_lite_wstrb = '0; + assign pc_lite_wvalid = 1'b0; + assign pc_lite_wready = 1'b0; + assign pc_lite_bresp = 2'b00; + assign pc_lite_bvalid = 1'b0; + assign pc_lite_bready = 1'b0; + assign pc_lite_araddr = '0; + assign pc_lite_arprot = '0; + assign pc_lite_arvalid = 1'b0; + assign pc_lite_arready = 1'b0; + assign pc_lite_rdata = '0; + assign pc_lite_rresp = 2'b00; + assign pc_lite_rvalid = 1'b0; + assign pc_lite_rready = 1'b0; + + assign cdma_m_axi_awaddr = '0; + assign cdma_m_axi_awlen = '0; + assign cdma_m_axi_awsize = '0; + assign cdma_m_axi_awburst = '0; + assign cdma_m_axi_awcache = '0; + assign cdma_m_axi_awprot = '0; + assign cdma_m_axi_awvalid = 1'b0; + assign cdma_m_axi_wdata = '0; + assign cdma_m_axi_wstrb = '0; + assign cdma_m_axi_wlast = 1'b0; + assign cdma_m_axi_wvalid = 1'b0; + assign cdma_m_axi_bready = 1'b0; + assign cdma_m_axi_araddr = '0; + assign cdma_m_axi_arlen = '0; + assign cdma_m_axi_arsize = '0; + assign cdma_m_axi_arburst = '0; + assign cdma_m_axi_arcache = '0; + assign cdma_m_axi_arprot = '0; + assign cdma_m_axi_arvalid = 1'b0; + assign cdma_m_axi_rready = 1'b0; + + idma_wrap #( + .AxiAddrWidth ( ADDR_W ), + .AxiDataWidth ( DATA_W ), + .AxiIdWidth ( SLV_ID_W ), + .AxiUserWidth ( 1 ), + .AxiSlvIdWidth ( MST_ID_W ), + .AxiMaxReadTxns ( 4 ), + .AxiMaxWriteTxns ( 4 ), + .NumAxInFlight ( 4 ), + .MemSysDepth ( 0 ), + .JobFifoDepth ( 2 ), + .RAWCouplingAvail ( 1'b0 ), + .EnableDesc64 ( P.AXI_IDMA_SUPPORTED ), + .EnableReg64 ( P.AXI_IDMA_REG64_SUPPORTED ), + .EnableReg64TwoD ( 1'b0 ), + .axi_mst_req_t ( slv_req_t ), + .axi_mst_rsp_t ( slv_resp_t ), + .axi_slv_req_t ( mst_req_t ), + .axi_slv_rsp_t ( mst_resp_t ) + ) idma_i ( + .clk_i ( BUSCLK ), + .rst_ni ( BUSCORERSTn ), + .testmode_i ( 1'b0 ), + .axi_mst_fe_req_o ( idma_xbar_mst_req[0] ), + .axi_mst_fe_rsp_i ( idma_xbar_mst_rsp[0] ), + .axi_mst_be_req_o ( idma_xbar_mst_req[1] ), + .axi_mst_be_rsp_i ( idma_xbar_mst_rsp[1] ), + .axi_slv_req_i ( idma_xbar_slv_req ), + .axi_slv_rsp_o ( idma_xbar_slv_rsp ), + .irq_o ( dma_irq_raw ) + ); + end else begin : gen_no_dma + assign reg_awready = 1'b0; + assign reg_wready = 1'b0; + assign reg_arready = 1'b0; + assign reg_bvalid = 1'b0; + assign reg_bresp = 2'b00; + assign reg_bid = '0; + assign reg_rvalid = 1'b0; + assign reg_rlast = 1'b0; + assign reg_rresp = 2'b00; + assign reg_rid = '0; + assign reg_rdata = '0; + + assign pc_lite_awaddr = '0; + assign pc_lite_awprot = '0; + assign pc_lite_awvalid = 1'b0; + assign pc_lite_awready = 1'b0; + assign pc_lite_wdata = '0; + assign pc_lite_wstrb = '0; + assign pc_lite_wvalid = 1'b0; + assign pc_lite_wready = 1'b0; + assign pc_lite_bresp = 2'b00; + assign pc_lite_bvalid = 1'b0; + assign pc_lite_bready = 1'b0; + assign pc_lite_araddr = '0; + assign pc_lite_arprot = '0; + assign pc_lite_arvalid = 1'b0; + assign pc_lite_arready = 1'b0; + assign pc_lite_rdata = '0; + assign pc_lite_rresp = 2'b00; + assign pc_lite_rvalid = 1'b0; + assign pc_lite_rready = 1'b0; + + assign cdma_m_axi_awaddr = '0; + assign cdma_m_axi_awlen = '0; + assign cdma_m_axi_awsize = '0; + assign cdma_m_axi_awburst = '0; + assign cdma_m_axi_awcache = '0; + assign cdma_m_axi_awprot = '0; + assign cdma_m_axi_awvalid = 1'b0; + assign cdma_m_axi_wdata = '0; + assign cdma_m_axi_wstrb = '0; + assign cdma_m_axi_wlast = 1'b0; + assign cdma_m_axi_wvalid = 1'b0; + assign cdma_m_axi_bready = 1'b0; + assign cdma_m_axi_araddr = '0; + assign cdma_m_axi_arlen = '0; + assign cdma_m_axi_arsize = '0; + assign cdma_m_axi_arburst = '0; + assign cdma_m_axi_arcache = '0; + assign cdma_m_axi_arprot = '0; + assign cdma_m_axi_arvalid = 1'b0; + assign cdma_m_axi_rready = 1'b0; + + assign idma_xbar_mst_req = '0; + assign idma_xbar_slv_rsp = '0; + assign dma_irq_raw = 1'b0; + end - //always_ff @(posedge clk_out3_mmcm or posedge reset) begin always_ff @(posedge CPUCLK or posedge peripheral_reset) begin - if (peripheral_reset) - dma_irq_sync <= 2'b00; - else - dma_irq_sync <= {dma_irq_sync[0], dma_introut}; // dma_introut = introut signal + if (peripheral_reset) begin + dma_irq_sync <= 2'b00; + end else begin + dma_irq_sync <= {dma_irq_sync[0], dma_irq_raw}; + end end assign dma_introut_sync = dma_irq_sync[1]; - - axicdma axicdma ( - .m_axi_aclk (BUSCLK), - .s_axi_lite_aclk (BUSCLK), - .s_axi_lite_aresetn(BUSRSTn), - - // AXI4-Lite control - // This project generates CDMA with a small AXI4-Lite address port (6 bits). - // Base address decode is done in the crossbar; CDMA only needs low bits for register offsets. - .s_axi_lite_awaddr (pc_lite_awaddr[5:0]), - .s_axi_lite_awvalid(pc_lite_awvalid), - .s_axi_lite_awready(pc_lite_awready), - - .s_axi_lite_wdata (pc_lite_wdata), - .s_axi_lite_wvalid (pc_lite_wvalid), - .s_axi_lite_wready (pc_lite_wready), - - .s_axi_lite_bresp (pc_lite_bresp), - .s_axi_lite_bvalid (pc_lite_bvalid), - .s_axi_lite_bready (pc_lite_bready), - - .s_axi_lite_araddr (pc_lite_araddr[5:0]), - .s_axi_lite_arvalid(pc_lite_arvalid), - .s_axi_lite_arready(pc_lite_arready), - - .s_axi_lite_rdata (pc_lite_rdata), - .s_axi_lite_rresp (pc_lite_rresp), - .s_axi_lite_rvalid (pc_lite_rvalid), - .s_axi_lite_rready (pc_lite_rready), - - // AXI4 MM2MM master into crossbar S01 - .m_axi_awaddr (cdma_m_axi_awaddr), - .m_axi_awlen (cdma_m_axi_awlen), - .m_axi_awsize (cdma_m_axi_awsize), - .m_axi_awburst (cdma_m_axi_awburst), - .m_axi_awcache (cdma_m_axi_awcache), - .m_axi_awprot (cdma_m_axi_awprot), - .m_axi_awvalid (cdma_m_axi_awvalid), - .m_axi_awready (cdma_m_axi_awready), - - .m_axi_wdata (cdma_m_axi_wdata), - .m_axi_wstrb (cdma_m_axi_wstrb), - .m_axi_wlast (cdma_m_axi_wlast), - .m_axi_wvalid (cdma_m_axi_wvalid), - .m_axi_wready (cdma_m_axi_wready), - - .m_axi_bresp (cdma_m_axi_bresp), - .m_axi_bvalid (cdma_m_axi_bvalid), - .m_axi_bready (cdma_m_axi_bready), - - .m_axi_araddr (cdma_m_axi_araddr), - .m_axi_arlen (cdma_m_axi_arlen), - .m_axi_arsize (cdma_m_axi_arsize), - .m_axi_arburst (cdma_m_axi_arburst), - .m_axi_arcache (cdma_m_axi_arcache), - .m_axi_arprot (cdma_m_axi_arprot), - .m_axi_arvalid (cdma_m_axi_arvalid), - .m_axi_arready (cdma_m_axi_arready), - - .m_axi_rdata (cdma_m_axi_rdata), - .m_axi_rresp (cdma_m_axi_rresp), - .m_axi_rlast (cdma_m_axi_rlast), - .m_axi_rvalid (cdma_m_axi_rvalid), - .m_axi_rready (cdma_m_axi_rready), - - .cdma_introut (dma_introut) - ); + assign axi_dma_intr_sync = dma_introut_sync; // CDC: synchronizer for calib_complete signal logic ddr_ready_raw; @@ -3046,11 +3317,11 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) assign litedram_axi_arready = 1'b0; assign litedram_axi_bvalid = 1'b0; assign litedram_axi_bresp = 2'b0; - assign litedram_axi_bid = 4'b0; + assign litedram_axi_bid = '0; assign litedram_axi_rvalid = 1'b0; assign litedram_axi_rlast = 1'b0; assign litedram_axi_rresp = 2'b0; - assign litedram_axi_rid = 4'b0; + assign litedram_axi_rid = '0; assign litedram_axi_rdata = '0; // DDR3 Controller @@ -3291,7 +3562,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) ); if (DATA_W == 64) begin - litedram_genesys2_fixed ddr3( + litedram_genesys2 ddr3( .clk (clk200), // external 200 MHz board clock .rst(rst_req), @@ -3442,15 +3713,17 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) assign litedram_axi_arready = 1'b0; assign litedram_axi_bvalid = 1'b0; assign litedram_axi_bresp = 2'b0; - assign litedram_axi_bid = 4'b0; + assign litedram_axi_bid = '0; assign litedram_axi_rvalid = 1'b0; assign litedram_axi_rlast = 1'b0; assign litedram_axi_rresp = 2'b0; - assign litedram_axi_rid = 4'b0; + assign litedram_axi_rid = '0; assign litedram_axi_rdata = '0; uberddr3_wrapper #( - .AXI_DATA_WIDTH(DATA_W) + .AXI_ID_WIDTH(DDR_ID_W), + .AXI_DATA_WIDTH(DATA_W), + .UBER_AXI_ID_WIDTH(DDR_ID_W) ) ddr3 ( .i_clk_200(clk200), diff --git a/linux/devicetree/wally-genesys2rv32soc.dts b/linux/devicetree/wally-genesys2rv32soc.dts index 40495a2eac..ecc061a642 100644 --- a/linux/devicetree/wally-genesys2rv32soc.dts +++ b/linux/devicetree/wally-genesys2rv32soc.dts @@ -7,7 +7,7 @@ model = "wally-virt,qemu"; chosen { - bootargs = "root=/dev/mmcblk1p5 rw console=ttyS0,115200 loglevel=7 init=/sbin/init rootwait "; + bootargs = "root=/dev/mmcblk1p5 rw earlycon=uart8250,mmio,0x10000000 console=ttyS0,115200 loglevel=7 init=/sbin/init rootwait "; stdout-path = "/soc/uart@10000000"; // needed for the FB @@ -17,10 +17,8 @@ //320 x 240 framebuffer0: framebuffer@85040000 { - // framebuffer0: framebuffer@84040000 { // uncached framebuffer (disabled) compatible = "simple-framebuffer"; reg = <0x0 0x85040000 0x0 0x00025800>; - // reg = <0x0 0x84040000 0x0 0x00025800>; width = <320>; height = <240>; stride = <640>; // 320 * 2 @@ -183,13 +181,14 @@ clock-output-names = "busclk"; }; - cdma0: dma@100A0000 { + /* + cdma0: dma@100A0000 { compatible = "xlnx,axi-cdma-1.00.a"; reg = <0x0 0x100A0000 0x0 0x1000>; #dma-cells = <1>; xlnx,addrwidth = <0x20>; // 32-bit addresses - status = "okay"; + status = "disabled"; // DMA visible memory window. @@ -214,6 +213,23 @@ xlnx,max-burst-len = <0x10>; }; }; + */ + + idma: dma-controller@10080000 { + model = "eth,idma-engine"; + compatible = "eth,idma-engine"; + reg = <0x0 0x10080000 0x0 0x1000>; + interrupt-parent = <&plic>; + //interrupts = <20>; + interrupts = <13>; + eth,input-slots = <1>; + eth,pending-slots = <1>; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <127>; + dma-noncoherent; // non-default + memory-region = <&uncached_memory_idma>; + }; usb@100C0000 { compatible = "generic-ohci"; @@ -251,19 +267,25 @@ }; + // Remark: u-boot might dynamically add its reserved regions, so they should match reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; + // 1 MB uncached region: 0x84000000-- 0x840FFFFF uncached_memory_usb: uncached-memory@84000000 { reg = <0x0 0x84000000 0x0 0x0040000>; // 256 KiB uncached DDR no-map; }; - // uncached: 0x25800 is needed for 320x240 but we assign the rest of uncached region - framebuffer@84040000 { - reg = <0x0 0x84040000 0x0 0x000C0000>; + uncached_memory_idma: idma-desc@84040000 { + reg = <0x0 0x84040000 0x0 0x00004000>; //16 KB + no-map; + }; + + uncached_rest@84044000 { + reg = <0x0 0x84044000 0x0 0x000BC000>; // rest of uncached RAM no-map; }; @@ -273,12 +295,6 @@ no-map; }; - dmabuffer@BFE00000 { - compatible = "shared-dma-pool"; - reg = <0x0 0xBFE00000 0x0 0x00100000>; // 1 MiB reserved - no-map; - }; - // Prevent Linux from using this region opensbi@80000000 { reg = <0x0 0x80000000 0x0 0x0080000>; // 512 Kib diff --git a/linux/devicetree/wally-genesys2soc.dts b/linux/devicetree/wally-genesys2soc.dts index a99660b1a0..d93cdca0e8 100644 --- a/linux/devicetree/wally-genesys2soc.dts +++ b/linux/devicetree/wally-genesys2soc.dts @@ -7,7 +7,7 @@ model = "wally-virt,qemu"; chosen { - bootargs = "root=/dev/mmcblk1p5 rw console=ttyS0,115200 loglevel=7 init=/sbin/init rootwait "; + bootargs = "root=/dev/mmcblk1p5 rw earlycon=uart8250,mmio,0x10000000 console=ttyS0,115200 loglevel=7 init=/sbin/init rootwait "; stdout-path = "/soc/uart@10000000"; // needed for the FB @@ -188,8 +188,7 @@ #dma-cells = <1>; xlnx,addrwidth = <0x20>; // 32-bit addresses - status = "okay"; - + status = "disabled"; // DMA visible memory window. // For your 128MB DDR at 0x8000_0000..0x87FF_FFFF: diff --git a/linux/genCvwsocPreload.sh b/linux/genCvwsocPreload.sh index e0a7446a37..496da7acc0 100755 --- a/linux/genCvwsocPreload.sh +++ b/linux/genCvwsocPreload.sh @@ -235,6 +235,13 @@ if rootfs_mode == "jffs2": bank-width = <{rootfs_bank_width}>; erase-size = <{rootfs_erase_size}>; }}; +''' + rootfs_reserved_node = f''' + + romfs_reserved: rootfs@{rootfs_addr:x} {{ + reg = <0x{rootfs_addr >> 32:x} 0x{rootfs_addr & 0xffffffff:08x} 0x0 0x{rootfs_size:x}>; + no-map; + }}; ''' reserved_node = f''' @@ -253,8 +260,9 @@ if rootfs_mode == "jffs2": src = re.sub(r'\n\s*(?:romfs|rootfs)@[0-9a-fA-F]+\s*\{.*?\n\s*\};', rootfs_node.rstrip(), src, flags=re.S) else: src = re.sub(r'\n\s*soc\s*\{', rootfs_node + '\n soc {', src, count=1) - if re.search(r'\n\s*reserved-memory\s*\{.*?\n\s*\};', src, flags=re.S): - src = re.sub(r'\n\s*reserved-memory\s*\{.*?\n\s*\};', reserved_node.rstrip(), src, flags=re.S) + reserved_close_re = r'\n\s*\};(?=\n\s*cpus\s*\{)' + if re.search(r'\n\s*reserved-memory\s*\{', src) and re.search(reserved_close_re, src): + src = re.sub(reserved_close_re, rootfs_reserved_node.rstrip() + '\n };', src, count=1) else: src = re.sub(r'\n\s*soc\s*\{', reserved_node + '\n soc {', src, count=1) else: diff --git a/sim/verilator/Makefile.cvwsoc b/sim/verilator/Makefile.cvwsoc index af3af01628..4c5daa6b37 100644 --- a/sim/verilator/Makefile.cvwsoc +++ b/sim/verilator/Makefile.cvwsoc @@ -3,15 +3,35 @@ SHELL := /bin/bash .PHONY: \ all linux uboot run-cvwsoc qemu qemu-preload runcmd-cvwsoc clean \ + cleantb \ gen-cvwsoc-linux-preload gen-cvwsoc-uboot-preload gen-cvwsoc-sd-image \ gen-cvwsoc-linux-fast-preload \ qemu-linux-preload qemu-uboot-preload qemu-linux qemu-uboot \ qemu-linux-fast qemu-linux-fast-preload qemu-preload-linux-fast \ run-cvwsoc-linux run-cvwsoc-uboot runcmd-cvwsoc-linux runcmd-cvwsoc-uboot \ - run-cvwsoc-linux-fast run-cvwsoc-linxu-fast \ + run-cvwsoc-linux-fast sim-fast sim-fast-uboot \ FORCE .DELETE_ON_ERROR: +# If cleanup is mixed with a build/run goal, keep this top-level make serial. +# The recursive Verilator C++ build still receives the jobserver from -j. +ifneq ($(filter clean cleantb,$(MAKECMDGOALS)),) +ifneq ($(filter-out clean cleantb,$(MAKECMDGOALS)),) +.NOTPARALLEL: +endif +endif + +CPUSETTINGS ?= + +ifneq ($(filter sim-fast sim-fast-uboot,$(MAKECMDGOALS)),) +PERF_CPU ?= 6 +RV32 ?= 1 +CONFIG ?= fpgagenesys2rv32w64soc +CPUSETTINGS ?= taskset -c $(PERF_CPU) +endif + +# prefix for Verilator. E.g. 'taskset -c 2' + WALLY ?= $(abspath $(dir $(lastword $(MAKEFILE_LIST)))/../..) export WALLY BOOL_TRUE := 1 yes YES true TRUE @@ -37,6 +57,7 @@ PULP_AXI_ROOT := $(PULP_ROOT)/axi PULP_COMMON_CELLS_ROOT := $(PULP_ROOT)/common_cells PULP_REGISTER_INTERFACE_ROOT := $(PULP_ROOT)/register_interface SDHCI_ROOT := $(COPIED_ROOT)/sdhci/hw +IDMA_ROOT := $(PULP_ROOT)/idma CVWSOC_DEPLOY_ROOT ?= /yocto/fpga/kas-cvwsoc/build/tmp/deploy/images CVWSOC_MACHINE ?= $(if $(CVWSOC_RV32),cvwsoc-virt32,cvwsoc-virt) @@ -189,6 +210,7 @@ TRACE_DEPTH ?= 1 PARAMS ?= --trace-depth $(TRACE_DEPTH) --threads $(THREADS) EXTRA_PARAMS ?= NONPROF ?= --stats +#WARN_ARGS ?= -Wno-fatal -Werror-UNOPTFLAT WARN_ARGS ?= -Wno-fatal PLUS_ARGS ?= EXTRA_PLUS_ARGS ?= @@ -201,11 +223,11 @@ CVWSOC_DATA_MEMH ?= $(WALLY)/fpga/src/data.mem CVWSOC_BOOTROM_MEMH_DEPS := $(if $(CVWSOC_BOOTROM),$(CVWSOC_BOOTROM_MEMH) $(CVWSOC_DATA_MEMH)) CVWSOC_BOOTROM_PLUS_ARGS := $(if $(CVWSOC_BOOTROM),+BOOTROM_MEMH=$(CVWSOC_BOOTROM_MEMH) +UNCORE_RAM_MEMH=$(CVWSOC_DATA_MEMH)) UART_LOG ?= +# TRACE selects tracing mode: 0 disables, runtime/1 enables C++ SIGUSR1 FST, sv enables SV $dumpvars FST. TRACE ?= 0 -TRACE_MODE ?= runtime -TRACE_ENABLED := $(filter $(BOOL_TRUE),$(TRACE)) +TRACE_ENABLED := $(filter-out 0 no NO false FALSE,$(TRACE)) TRACE_BUILD_ARGS := $(if $(TRACE_ENABLED),--trace-fst,) -TRACE_PARAM_ARG := $(if $(TRACE_ENABLED),$(if $(filter sv,$(TRACE_MODE)),MAKE_VCD=1,MAKE_VCD=0),MAKE_VCD=0) +TRACE_PARAM_ARG := $(if $(filter sv,$(TRACE)),MAKE_VCD=1,MAKE_VCD=0) ALL_PARAM_ARGS := $(strip $(PARAM_ARGS) $(TRACE_PARAM_ARG)) EXPANDED_PARAM_ARGS := $(patsubst %,-G%,$(ALL_PARAM_ARGS)) UART_STDOUT ?= 0 @@ -240,9 +262,11 @@ COMMON_CELLS_SOURCES := \ $(PULP_COMMON_CELLS_ROOT)/src/id_queue.sv \ $(PULP_COMMON_CELLS_ROOT)/src/onehot_to_bin.sv \ $(PULP_COMMON_CELLS_ROOT)/src/fifo_v3.sv \ + $(PULP_COMMON_CELLS_ROOT)/src/passthrough_stream_fifo.sv \ $(PULP_COMMON_CELLS_ROOT)/src/spill_register_flushable.sv \ $(PULP_COMMON_CELLS_ROOT)/src/spill_register.sv \ $(PULP_COMMON_CELLS_ROOT)/src/stream_register.sv \ + $(PULP_COMMON_CELLS_ROOT)/src/fall_through_register.sv \ $(PULP_COMMON_CELLS_ROOT)/src/addr_decode_dync.sv \ $(PULP_COMMON_CELLS_ROOT)/src/addr_decode.sv \ $(PULP_COMMON_CELLS_ROOT)/src/cdc_fifo_gray.sv \ @@ -250,6 +274,7 @@ COMMON_CELLS_SOURCES := \ $(PULP_COMMON_CELLS_ROOT)/src/stream_arbiter.sv \ $(PULP_COMMON_CELLS_ROOT)/src/stream_arbiter_flushable.sv \ $(PULP_COMMON_CELLS_ROOT)/src/stream_fifo.sv \ + $(PULP_COMMON_CELLS_ROOT)/src/stream_fifo_optimal_wrap.sv \ $(PULP_COMMON_CELLS_ROOT)/src/stream_fork.sv \ $(PULP_COMMON_CELLS_ROOT)/src/stream_fork_dynamic.sv \ $(PULP_COMMON_CELLS_ROOT)/src/stream_join.sv \ @@ -273,6 +298,7 @@ AXI_SOURCES := \ $(PULP_AXI_ROOT)/src/axi_id_prepend.sv \ $(PULP_AXI_ROOT)/src/axi_multicut.sv \ $(PULP_AXI_ROOT)/src/axi_mux.sv \ + $(PULP_AXI_ROOT)/src/axi_rw_join.sv \ $(PULP_AXI_ROOT)/src/axi_err_slv.sv \ $(PULP_AXI_ROOT)/src/axi_cdc.sv \ $(PULP_AXI_ROOT)/src/axi_demux.sv \ @@ -286,6 +312,30 @@ PULP_REGISTER_INTERFACE_SOURCES := \ $(filter-out $(PULP_ROOT)/register_interface/src/reg_test.sv, \ $(wildcard $(PULP_ROOT)/register_interface/src/*.sv)) +IDMA_GENERATED_SOURCES := \ + $(IDMA_ROOT)/target/rtl/idma_transport_layer_rw_axi.sv \ + $(IDMA_ROOT)/target/rtl/idma_legalizer_rw_axi.sv \ + $(IDMA_ROOT)/target/rtl/idma_backend_rw_axi.sv \ + $(IDMA_ROOT)/target/rtl/idma_desc64_reg_pkg.sv \ + $(IDMA_ROOT)/target/rtl/idma_desc64_reg_top.sv \ + $(IDMA_ROOT)/target/rtl/idma_reg64_1d_reg_pkg.sv \ + $(IDMA_ROOT)/target/rtl/idma_reg64_1d_reg_top.sv \ + $(IDMA_ROOT)/target/rtl/idma_reg64_1d_top.sv + +IDMA_SOURCES := \ + $(IDMA_ROOT)/src/idma_pkg.sv \ + $(wildcard $(IDMA_ROOT)/src/backend/*.sv) \ + $(IDMA_GENERATED_SOURCES) \ + $(IDMA_ROOT)/src/frontend/desc64/idma_desc64_ar_gen.sv \ + $(IDMA_ROOT)/src/frontend/desc64/idma_desc64_ar_gen_prefetch.sv \ + $(IDMA_ROOT)/src/frontend/desc64/idma_desc64_reader.sv \ + $(IDMA_ROOT)/src/frontend/desc64/idma_desc64_reader_gater.sv \ + $(IDMA_ROOT)/src/frontend/desc64/idma_desc64_reshaper.sv \ + $(IDMA_ROOT)/src/frontend/desc64/idma_desc64_reg_wrapper.sv \ + $(IDMA_ROOT)/src/frontend/desc64/idma_desc64_top.sv \ + $(IDMA_ROOT)/src/frontend/idma_transfer_id_gen.sv \ + $(WALLY)/addins/cvwsoc/dma/idma_wrap.sv + CORE_SOURCES := $(filter-out \ $(wildcard $(COPIED_ROOT)/testbench/sdc/*.sv) \ @@ -339,6 +389,7 @@ INCLUDE_PATH := \ -I$(PULP_AXI_ROOT)/include \ -I$(PULP_COMMON_CELLS_ROOT)/include \ -I$(PULP_REGISTER_INTERFACE_ROOT)/include \ + -I$(IDMA_ROOT)/src/include \ -I$(SDHCI_ROOT)/include VERILOG_AXI_SOURCES := \ @@ -353,6 +404,7 @@ SOURCES := \ $(BRIDGE_RTL) \ $(VERILOG_AXI_SOURCES) \ $(PULP_REGISTER_INTERFACE_SOURCES) \ + $(IDMA_SOURCES) \ $(PERIPH_SOURCES) DEPENDENCIES := \ @@ -365,8 +417,14 @@ $(COPIED_ROOT)/config/config.vh: $(CONFIG_VH) FORCE mkdir -p $(dir $@) @if ! cmp -s "$<" "$@"; then cp "$<" "$@"; fi +$(IDMA_GENERATED_SOURCES): + $(MAKE) -C $(IDMA_ROOT) \ + IDMA_REG_DIR=$(PULP_REGISTER_INTERFACE_ROOT) \ + IDMA_CC_DIR=$(PULP_COMMON_CELLS_ROOT) \ + $(patsubst $(IDMA_ROOT)/%,%,$@) + # this is for GCC -OPT_GEN ?= VM_PARALLEL_BUILDS=1 OPT_FAST="-O4 -march=native" OPT_GLOBAL="-O3 -march=native" OPT_SLOW="-O0" +OPT_GEN ?= VM_PARALLEL_BUILDS=1 OPT_FAST="-O3 -march=native" OPT_GLOBAL="-O3 -march=native" OPT_SLOW="-O1" OPT_COMP ?= -O3 VERILATOR_USER_CPPFLAGS ?= -DsetBit=set @@ -377,7 +435,7 @@ define RUN_VERILATOR if [[ -n "$(EXT_RAM_BIN)" ]]; then args="$$args +EXT_RAM_BIN=$(EXT_RAM_BIN)"; fi; \ if [[ -n "$(CVWSOC_SD_IMAGE_DEPS)" ]]; then args="$$args +SD_IMAGE=$(CVWSOC_SD_IMAGE)"; fi; \ if [[ -n "$(UART_LOG)" ]]; then args="$$args +UART_LOG=$(UART_LOG)"; fi; \ - $(WORKDIR)/V$(TESTBENCH) $$args + $(CPUSETTINGS) $(WORKDIR)/V$(TESTBENCH) $$args endef define CVWSOC_PRELOAD_COMMON_ENV @@ -479,221 +537,159 @@ $(CVWSOC_PRELOAD_DIR)/ram-cvwsoc-uboot-run.bin: $(CVWSOC_UBOOT_EXT_RAM_BIN) $(CV FORCE: -$(CVWSOC_LINUX_QEMU_CFG): FORCE | $(CVWSOC_PRELOAD_DIR) +CVWSOC_CFG_QEMU_KEYS := \ + MODE IMAGE_KIND INITRD_EXT2 FW_JUMP_BIN KERNEL_SRC INITRD_SRC DTS_SRC BOOTARGS \ + QEMU_RAM_MB CPU_ARGS CVWSOC_XLEN CVWSOC_BUS_WIDTH PRELOAD_WORD_BYTES \ + DTC_BIN UNLZ4_BIN KERNEL_ADDR UBOOT_ADDR UBOOT_STUB_BIN KERNEL_DTB_ADDR INITRD_ADDR \ + QEMU_KERNEL QEMU_INITRD GENERATED_DTS GENERATED_DTB EXTERNAL_DTB + +CVWSOC_CFG_FAST_KEYS := \ + MODE ROOTFS_MODE IMAGE_KIND FW_JUMP_BIN KERNEL_SRC INITRD_SRC DTS_SRC BOOTARGS \ + QEMU_RAM_MB CPU_ARGS CVWSOC_XLEN CVWSOC_BUS_WIDTH PRELOAD_WORD_BYTES \ + DTC_BIN UNLZ4_BIN KERNEL_ADDR UBOOT_ADDR UBOOT_STUB_BIN KERNEL_DTB_ADDR INITRD_ADDR \ + ROOTFS_ADDR ROOTFS_COMPATIBLE ROOTFS_DTS_SIZE ROOTFS_BANK_WIDTH ROOTFS_ERASE_SIZE \ + QEMU_KERNEL QEMU_INITRD GENERATED_DTS GENERATED_DTB EXTERNAL_DTB + +CVWSOC_CFG_UBOOT_QEMU_KEYS := \ + MODE IMAGE_KIND INITRD_EXT2 FW_JUMP_BIN UBOOT_BIN UBOOT_DTB KERNEL_SRC INITRD_SRC DTS_SRC BOOTARGS \ + QEMU_RAM_MB CPU_ARGS CVWSOC_XLEN CVWSOC_BUS_WIDTH PRELOAD_WORD_BYTES \ + DTC_BIN UNLZ4_BIN KERNEL_ADDR UBOOT_DTB_ADDR KERNEL_DTB_ADDR INITRD_ADDR \ + QEMU_KERNEL QEMU_INITRD GENERATED_DTS GENERATED_DTB + +CVWSOC_CFG_PRELOAD_KEYS := \ + MODE IMAGE_KIND INITRD_EXT2 FW_JUMP_BIN KERNEL_SRC INITRD_SRC DTS_SRC BOOTARGS \ + QEMU_BIN QEMU_RAM_MB CPU_ARGS GDB_BIN OBJCOPY_BIN CVWSOC_XLEN CVWSOC_BUS_WIDTH PRELOAD_WORD_BYTES \ + DTC_BIN UNLZ4_BIN KERNEL_ADDR UBOOT_ADDR UBOOT_STUB_BIN KERNEL_DTB_ADDR INITRD_ADDR \ + RAW_BOOTMEM_FILE BOOTMEM_FILE RAW_RAM_FILE RAM_FILE QEMU_KERNEL QEMU_INITRD GENERATED_DTS GENERATED_DTB + +CVWSOC_CFG_FAST_PRELOAD_KEYS := \ + MODE ROOTFS_MODE IMAGE_KIND FW_JUMP_BIN KERNEL_SRC INITRD_SRC DTS_SRC BOOTARGS \ + QEMU_BIN QEMU_RAM_MB CPU_ARGS GDB_BIN OBJCOPY_BIN CVWSOC_XLEN CVWSOC_BUS_WIDTH PRELOAD_WORD_BYTES \ + DTC_BIN UNLZ4_BIN KERNEL_ADDR UBOOT_ADDR UBOOT_STUB_BIN KERNEL_DTB_ADDR INITRD_ADDR \ + ROOTFS_ADDR ROOTFS_COMPATIBLE ROOTFS_DTS_SIZE ROOTFS_BANK_WIDTH ROOTFS_ERASE_SIZE \ + RAW_BOOTMEM_FILE BOOTMEM_FILE RAW_RAM_FILE RAM_FILE QEMU_KERNEL QEMU_INITRD GENERATED_DTS GENERATED_DTB + +CVWSOC_CFG_UBOOT_PRELOAD_KEYS := \ + MODE IMAGE_KIND INITRD_EXT2 FW_JUMP_BIN UBOOT_BIN UBOOT_DTB KERNEL_SRC INITRD_SRC DTS_SRC BOOTARGS \ + QEMU_BIN QEMU_RAM_MB CPU_ARGS GDB_BIN OBJCOPY_BIN CVWSOC_XLEN CVWSOC_BUS_WIDTH PRELOAD_WORD_BYTES \ + DTC_BIN UNLZ4_BIN KERNEL_ADDR UBOOT_DTB_ADDR KERNEL_DTB_ADDR INITRD_ADDR \ + RAW_BOOTMEM_FILE BOOTMEM_FILE RAW_RAM_FILE RAM_FILE QEMU_KERNEL QEMU_INITRD GENERATED_DTS GENERATED_DTB EXTERNAL_DTB + +CVWSOC_CFG_IMAGE_KIND = $(CVWSOC_IMAGE_NAME) +CVWSOC_CFG_INITRD_EXT2 = $(if $(CVWSOC_USE_EXT2),1,0) +CVWSOC_CFG_FW_JUMP_BIN = $(CVWSOC_FW_JUMP_BIN) +CVWSOC_CFG_KERNEL_SRC = $(CVWSOC_LINUX_KERNEL_SRC) +CVWSOC_CFG_INITRD_SRC = $(CVWSOC_LINUX_INITRD_SRC) +CVWSOC_CFG_DTS_SRC = $(CVWSOC_DTS_SRC) +CVWSOC_CFG_BOOTARGS = $(CVWSOC_LINUX_BOOTARGS) +CVWSOC_CFG_QEMU_BIN = $(QEMU_BIN) +CVWSOC_CFG_QEMU_RAM_MB = $(QEMU_RAM_MB) +CVWSOC_CFG_CPU_ARGS = $(CPU_ARGS) +CVWSOC_CFG_GDB_BIN = $(GDB_BIN) +CVWSOC_CFG_OBJCOPY_BIN = $(OBJCOPY_BIN) +CVWSOC_CFG_CVWSOC_XLEN = $(CVWSOC_XLEN) +CVWSOC_CFG_CVWSOC_BUS_WIDTH = $(CVWSOC_BUS_WIDTH) +CVWSOC_CFG_PRELOAD_WORD_BYTES = $(CVWSOC_WORD_BYTES) +CVWSOC_CFG_DTC_BIN = $(DTC_BIN) +CVWSOC_CFG_UNLZ4_BIN = $(UNLZ4_BIN) +CVWSOC_CFG_KERNEL_ADDR = $(CVWSOC_KERNEL_ADDR) +CVWSOC_CFG_UBOOT_ADDR = $(UBOOT_ADDR) +CVWSOC_CFG_UBOOT_STUB_BIN = $(CVWSOC_UBOOT_STUB_BIN) +CVWSOC_CFG_UBOOT_BIN = $(CVWSOC_UBOOT_BIN) +CVWSOC_CFG_UBOOT_DTB = $(CVWSOC_UBOOT_DTB) +CVWSOC_CFG_UBOOT_DTB_ADDR = $(UBOOT_DTB_ADDR) +CVWSOC_CFG_KERNEL_DTB_ADDR = $(KERNEL_DTB_ADDR) +CVWSOC_CFG_INITRD_ADDR = $(INITRD_ADDR) +CVWSOC_CFG_ROOTFS_DTS_SIZE = $(ROOTFS_DTS_SIZE) +CVWSOC_CFG_EXTERNAL_DTB = $(CVWSOC_VERILATOR_DTB) + +define WRITE_CVWSOC_CFG @tmp="$@.tmp"; \ { \ - printf 'MODE=linux\n'; \ - printf 'IMAGE_KIND=%s\n' '$(CVWSOC_IMAGE_NAME)'; \ - printf 'INITRD_EXT2=%s\n' '$(if $(CVWSOC_USE_EXT2),1,0)'; \ - printf 'FW_JUMP_BIN=%s\n' '$(CVWSOC_FW_JUMP_BIN)'; \ - printf 'KERNEL_SRC=%s\n' '$(CVWSOC_LINUX_KERNEL_SRC)'; \ - printf 'INITRD_SRC=%s\n' '$(CVWSOC_LINUX_INITRD_SRC)'; \ - printf 'DTS_SRC=%s\n' '$(CVWSOC_DTS_SRC)'; \ - printf 'BOOTARGS=%s\n' '$(CVWSOC_LINUX_BOOTARGS)'; \ - printf 'QEMU_RAM_MB=%s\n' '$(QEMU_RAM_MB)'; \ - printf 'CPU_ARGS=%s\n' '$(CPU_ARGS)'; \ - printf 'CVWSOC_XLEN=%s\n' '$(CVWSOC_XLEN)'; \ - printf 'CVWSOC_BUS_WIDTH=%s\n' '$(CVWSOC_BUS_WIDTH)'; \ - printf 'PRELOAD_WORD_BYTES=%s\n' '$(CVWSOC_WORD_BYTES)'; \ - printf 'DTC_BIN=%s\n' '$(DTC_BIN)'; \ - printf 'UNLZ4_BIN=%s\n' '$(UNLZ4_BIN)'; \ - printf 'KERNEL_ADDR=%s\n' '$(CVWSOC_KERNEL_ADDR)'; \ - printf 'UBOOT_ADDR=%s\n' '$(UBOOT_ADDR)'; \ - printf 'UBOOT_STUB_BIN=%s\n' '$(CVWSOC_UBOOT_STUB_BIN)'; \ - printf 'KERNEL_DTB_ADDR=%s\n' '$(KERNEL_DTB_ADDR)'; \ - printf 'INITRD_ADDR=%s\n' '$(INITRD_ADDR)'; \ - printf 'QEMU_KERNEL=%s\n' '$(CVWSOC_LINUX_QEMU_KERNEL)'; \ - printf 'QEMU_INITRD=%s\n' '$(CVWSOC_LINUX_QEMU_INITRD)'; \ - printf 'GENERATED_DTS=%s\n' '$(CVWSOC_LINUX_QEMU_DTS)'; \ - printf 'GENERATED_DTB=%s\n' '$(CVWSOC_LINUX_QEMU_DTB)'; \ - printf 'EXTERNAL_DTB=%s\n' '$(CVWSOC_VERILATOR_DTB)'; \ + $(foreach key,$(CVWSOC_CFG_KEYS),printf '%s=%s\n' '$(key)' '$(CVWSOC_CFG_$(key))';) \ } > "$$tmp"; \ if ! cmp -s "$$tmp" "$@"; then mv "$$tmp" "$@"; else rm -f "$$tmp"; fi +endef +$(CVWSOC_LINUX_QEMU_CFG): CVWSOC_CFG_KEYS := $(CVWSOC_CFG_QEMU_KEYS) +$(CVWSOC_LINUX_QEMU_CFG): CVWSOC_CFG_MODE := linux +$(CVWSOC_LINUX_QEMU_CFG): CVWSOC_CFG_QEMU_KERNEL := $(CVWSOC_LINUX_QEMU_KERNEL) +$(CVWSOC_LINUX_QEMU_CFG): CVWSOC_CFG_QEMU_INITRD := $(CVWSOC_LINUX_QEMU_INITRD) +$(CVWSOC_LINUX_QEMU_CFG): CVWSOC_CFG_GENERATED_DTS := $(CVWSOC_LINUX_QEMU_DTS) +$(CVWSOC_LINUX_QEMU_CFG): CVWSOC_CFG_GENERATED_DTB := $(CVWSOC_LINUX_QEMU_DTB) +$(CVWSOC_LINUX_QEMU_CFG): FORCE | $(CVWSOC_PRELOAD_DIR) + $(WRITE_CVWSOC_CFG) + +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_KEYS := $(CVWSOC_CFG_FAST_KEYS) +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_MODE := linux-fast +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_ROOTFS_MODE := $(CVWSOC_QEMU_FAST_ROOTFS_MODE) +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_INITRD_SRC := $(CVWSOC_LINUX_FAST_ROOTFS_SRC) +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_BOOTARGS := $(CVWSOC_QEMU_FAST_BOOTARGS) +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_ROOTFS_ADDR := $(CVWSOC_QEMU_FAST_ROOTFS_ADDR) +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_ROOTFS_COMPATIBLE := $(CVWSOC_QEMU_FAST_ROOTFS_COMPATIBLE) +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_ROOTFS_BANK_WIDTH := $(CVWSOC_QEMU_FAST_ROOTFS_BANK_WIDTH) +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_ROOTFS_ERASE_SIZE := $(CVWSOC_QEMU_FAST_ROOTFS_ERASE_SIZE) +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_QEMU_KERNEL := $(CVWSOC_LINUX_FAST_QEMU_KERNEL) +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_QEMU_INITRD := $(CVWSOC_LINUX_FAST_QEMU_ROOTFS) +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_GENERATED_DTS := $(CVWSOC_LINUX_FAST_QEMU_DTS) +$(CVWSOC_LINUX_FAST_QEMU_CFG): CVWSOC_CFG_GENERATED_DTB := $(CVWSOC_LINUX_FAST_QEMU_DTB) $(CVWSOC_LINUX_FAST_QEMU_CFG): FORCE | $(CVWSOC_PRELOAD_DIR) - @tmp="$@.tmp"; \ - { \ - printf 'MODE=linux-fast\n'; \ - printf 'ROOTFS_MODE=%s\n' '$(CVWSOC_QEMU_FAST_ROOTFS_MODE)'; \ - printf 'IMAGE_KIND=%s\n' '$(CVWSOC_IMAGE_NAME)'; \ - printf 'FW_JUMP_BIN=%s\n' '$(CVWSOC_FW_JUMP_BIN)'; \ - printf 'KERNEL_SRC=%s\n' '$(CVWSOC_LINUX_KERNEL_SRC)'; \ - printf 'INITRD_SRC=%s\n' '$(CVWSOC_LINUX_FAST_ROOTFS_SRC)'; \ - printf 'DTS_SRC=%s\n' '$(CVWSOC_DTS_SRC)'; \ - printf 'BOOTARGS=%s\n' '$(CVWSOC_QEMU_FAST_BOOTARGS)'; \ - printf 'QEMU_RAM_MB=%s\n' '$(QEMU_RAM_MB)'; \ - printf 'CPU_ARGS=%s\n' '$(CPU_ARGS)'; \ - printf 'CVWSOC_XLEN=%s\n' '$(CVWSOC_XLEN)'; \ - printf 'CVWSOC_BUS_WIDTH=%s\n' '$(CVWSOC_BUS_WIDTH)'; \ - printf 'PRELOAD_WORD_BYTES=%s\n' '$(CVWSOC_WORD_BYTES)'; \ - printf 'DTC_BIN=%s\n' '$(DTC_BIN)'; \ - printf 'UNLZ4_BIN=%s\n' '$(UNLZ4_BIN)'; \ - printf 'KERNEL_ADDR=%s\n' '$(CVWSOC_KERNEL_ADDR)'; \ - printf 'UBOOT_ADDR=%s\n' '$(UBOOT_ADDR)'; \ - printf 'UBOOT_STUB_BIN=%s\n' '$(CVWSOC_UBOOT_STUB_BIN)'; \ - printf 'KERNEL_DTB_ADDR=%s\n' '$(KERNEL_DTB_ADDR)'; \ - printf 'INITRD_ADDR=%s\n' '$(INITRD_ADDR)'; \ - printf 'ROOTFS_ADDR=%s\n' '$(CVWSOC_QEMU_FAST_ROOTFS_ADDR)'; \ - printf 'ROOTFS_COMPATIBLE=%s\n' '$(CVWSOC_QEMU_FAST_ROOTFS_COMPATIBLE)'; \ - printf 'ROOTFS_DTS_SIZE=%s\n' '$(ROOTFS_DTS_SIZE)'; \ - printf 'ROOTFS_BANK_WIDTH=%s\n' '$(CVWSOC_QEMU_FAST_ROOTFS_BANK_WIDTH)'; \ - printf 'ROOTFS_ERASE_SIZE=%s\n' '$(CVWSOC_QEMU_FAST_ROOTFS_ERASE_SIZE)'; \ - printf 'QEMU_KERNEL=%s\n' '$(CVWSOC_LINUX_FAST_QEMU_KERNEL)'; \ - printf 'QEMU_INITRD=%s\n' '$(CVWSOC_LINUX_FAST_QEMU_ROOTFS)'; \ - printf 'GENERATED_DTS=%s\n' '$(CVWSOC_LINUX_FAST_QEMU_DTS)'; \ - printf 'GENERATED_DTB=%s\n' '$(CVWSOC_LINUX_FAST_QEMU_DTB)'; \ - printf 'EXTERNAL_DTB=%s\n' '$(CVWSOC_VERILATOR_DTB)'; \ - } > "$$tmp"; \ - if ! cmp -s "$$tmp" "$@"; then mv "$$tmp" "$@"; else rm -f "$$tmp"; fi - + $(WRITE_CVWSOC_CFG) + +$(CVWSOC_UBOOT_QEMU_CFG): CVWSOC_CFG_KEYS := $(CVWSOC_CFG_UBOOT_QEMU_KEYS) +$(CVWSOC_UBOOT_QEMU_CFG): CVWSOC_CFG_MODE := uboot +$(CVWSOC_UBOOT_QEMU_CFG): CVWSOC_CFG_QEMU_KERNEL := $(CVWSOC_UBOOT_QEMU_KERNEL) +$(CVWSOC_UBOOT_QEMU_CFG): CVWSOC_CFG_QEMU_INITRD := $(CVWSOC_UBOOT_QEMU_INITRD) +$(CVWSOC_UBOOT_QEMU_CFG): CVWSOC_CFG_GENERATED_DTS := $(CVWSOC_UBOOT_QEMU_DTS) +$(CVWSOC_UBOOT_QEMU_CFG): CVWSOC_CFG_GENERATED_DTB := $(CVWSOC_UBOOT_QEMU_DTB) $(CVWSOC_UBOOT_QEMU_CFG): FORCE | $(CVWSOC_PRELOAD_DIR) - @tmp="$@.tmp"; \ - { \ - printf 'MODE=uboot\n'; \ - printf 'IMAGE_KIND=%s\n' '$(CVWSOC_IMAGE_NAME)'; \ - printf 'INITRD_EXT2=%s\n' '$(if $(CVWSOC_USE_EXT2),1,0)'; \ - printf 'FW_JUMP_BIN=%s\n' '$(CVWSOC_FW_JUMP_BIN)'; \ - printf 'UBOOT_BIN=%s\n' '$(CVWSOC_UBOOT_BIN)'; \ - printf 'UBOOT_DTB=%s\n' '$(CVWSOC_UBOOT_DTB)'; \ - printf 'KERNEL_SRC=%s\n' '$(CVWSOC_LINUX_KERNEL_SRC)'; \ - printf 'INITRD_SRC=%s\n' '$(CVWSOC_LINUX_INITRD_SRC)'; \ - printf 'DTS_SRC=%s\n' '$(CVWSOC_DTS_SRC)'; \ - printf 'BOOTARGS=%s\n' '$(CVWSOC_LINUX_BOOTARGS)'; \ - printf 'QEMU_RAM_MB=%s\n' '$(QEMU_RAM_MB)'; \ - printf 'CPU_ARGS=%s\n' '$(CPU_ARGS)'; \ - printf 'CVWSOC_XLEN=%s\n' '$(CVWSOC_XLEN)'; \ - printf 'CVWSOC_BUS_WIDTH=%s\n' '$(CVWSOC_BUS_WIDTH)'; \ - printf 'PRELOAD_WORD_BYTES=%s\n' '$(CVWSOC_WORD_BYTES)'; \ - printf 'DTC_BIN=%s\n' '$(DTC_BIN)'; \ - printf 'UNLZ4_BIN=%s\n' '$(UNLZ4_BIN)'; \ - printf 'KERNEL_ADDR=%s\n' '$(CVWSOC_KERNEL_ADDR)'; \ - printf 'UBOOT_DTB_ADDR=%s\n' '$(UBOOT_DTB_ADDR)'; \ - printf 'KERNEL_DTB_ADDR=%s\n' '$(KERNEL_DTB_ADDR)'; \ - printf 'INITRD_ADDR=%s\n' '$(INITRD_ADDR)'; \ - printf 'QEMU_KERNEL=%s\n' '$(CVWSOC_UBOOT_QEMU_KERNEL)'; \ - printf 'QEMU_INITRD=%s\n' '$(CVWSOC_UBOOT_QEMU_INITRD)'; \ - printf 'GENERATED_DTS=%s\n' '$(CVWSOC_UBOOT_QEMU_DTS)'; \ - printf 'GENERATED_DTB=%s\n' '$(CVWSOC_UBOOT_QEMU_DTB)'; \ - } > "$$tmp"; \ - if ! cmp -s "$$tmp" "$@"; then mv "$$tmp" "$@"; else rm -f "$$tmp"; fi - + $(WRITE_CVWSOC_CFG) + +$(CVWSOC_LINUX_PRELOAD_CFG): CVWSOC_CFG_KEYS := $(CVWSOC_CFG_PRELOAD_KEYS) +$(CVWSOC_LINUX_PRELOAD_CFG): CVWSOC_CFG_MODE := linux +$(CVWSOC_LINUX_PRELOAD_CFG): CVWSOC_CFG_RAW_BOOTMEM_FILE := $(CVWSOC_LINUX_RAW_BOOTROM_BIN) +$(CVWSOC_LINUX_PRELOAD_CFG): CVWSOC_CFG_BOOTMEM_FILE := $(CVWSOC_LINUX_BOOTROM_BIN) +$(CVWSOC_LINUX_PRELOAD_CFG): CVWSOC_CFG_RAW_RAM_FILE := $(CVWSOC_LINUX_RAW_EXT_RAM_BIN) +$(CVWSOC_LINUX_PRELOAD_CFG): CVWSOC_CFG_RAM_FILE := $(CVWSOC_LINUX_EXT_RAM_BIN) +$(CVWSOC_LINUX_PRELOAD_CFG): CVWSOC_CFG_QEMU_KERNEL := $(CVWSOC_LINUX_QEMU_KERNEL) +$(CVWSOC_LINUX_PRELOAD_CFG): CVWSOC_CFG_QEMU_INITRD := $(CVWSOC_LINUX_QEMU_INITRD) +$(CVWSOC_LINUX_PRELOAD_CFG): CVWSOC_CFG_GENERATED_DTS := $(CVWSOC_LINUX_QEMU_DTS) +$(CVWSOC_LINUX_PRELOAD_CFG): CVWSOC_CFG_GENERATED_DTB := $(CVWSOC_LINUX_QEMU_DTB) $(CVWSOC_LINUX_PRELOAD_CFG): FORCE | $(CVWSOC_PRELOAD_DIR) - @tmp="$@.tmp"; \ - { \ - printf 'MODE=linux\n'; \ - printf 'IMAGE_KIND=%s\n' '$(CVWSOC_IMAGE_NAME)'; \ - printf 'INITRD_EXT2=%s\n' '$(if $(CVWSOC_USE_EXT2),1,0)'; \ - printf 'FW_JUMP_BIN=%s\n' '$(CVWSOC_FW_JUMP_BIN)'; \ - printf 'KERNEL_SRC=%s\n' '$(CVWSOC_LINUX_KERNEL_SRC)'; \ - printf 'INITRD_SRC=%s\n' '$(CVWSOC_LINUX_INITRD_SRC)'; \ - printf 'DTS_SRC=%s\n' '$(CVWSOC_DTS_SRC)'; \ - printf 'BOOTARGS=%s\n' '$(CVWSOC_LINUX_BOOTARGS)'; \ - printf 'QEMU_BIN=%s\n' '$(QEMU_BIN)'; \ - printf 'QEMU_RAM_MB=%s\n' '$(QEMU_RAM_MB)'; \ - printf 'CPU_ARGS=%s\n' '$(CPU_ARGS)'; \ - printf 'GDB_BIN=%s\n' '$(GDB_BIN)'; \ - printf 'OBJCOPY_BIN=%s\n' '$(OBJCOPY_BIN)'; \ - printf 'CVWSOC_XLEN=%s\n' '$(CVWSOC_XLEN)'; \ - printf 'CVWSOC_BUS_WIDTH=%s\n' '$(CVWSOC_BUS_WIDTH)'; \ - printf 'PRELOAD_WORD_BYTES=%s\n' '$(CVWSOC_WORD_BYTES)'; \ - printf 'DTC_BIN=%s\n' '$(DTC_BIN)'; \ - printf 'UNLZ4_BIN=%s\n' '$(UNLZ4_BIN)'; \ - printf 'KERNEL_ADDR=%s\n' '$(CVWSOC_KERNEL_ADDR)'; \ - printf 'UBOOT_ADDR=%s\n' '$(UBOOT_ADDR)'; \ - printf 'UBOOT_STUB_BIN=%s\n' '$(CVWSOC_UBOOT_STUB_BIN)'; \ - printf 'KERNEL_DTB_ADDR=%s\n' '$(KERNEL_DTB_ADDR)'; \ - printf 'INITRD_ADDR=%s\n' '$(INITRD_ADDR)'; \ - printf 'RAW_BOOTMEM_FILE=%s\n' '$(CVWSOC_LINUX_RAW_BOOTROM_BIN)'; \ - printf 'BOOTMEM_FILE=%s\n' '$(CVWSOC_LINUX_BOOTROM_BIN)'; \ - printf 'RAW_RAM_FILE=%s\n' '$(CVWSOC_LINUX_RAW_EXT_RAM_BIN)'; \ - printf 'RAM_FILE=%s\n' '$(CVWSOC_LINUX_EXT_RAM_BIN)'; \ - printf 'QEMU_KERNEL=%s\n' '$(CVWSOC_LINUX_QEMU_KERNEL)'; \ - printf 'QEMU_INITRD=%s\n' '$(CVWSOC_LINUX_QEMU_INITRD)'; \ - printf 'GENERATED_DTS=%s\n' '$(CVWSOC_LINUX_QEMU_DTS)'; \ - printf 'GENERATED_DTB=%s\n' '$(CVWSOC_LINUX_QEMU_DTB)'; \ - } > "$$tmp"; \ - if ! cmp -s "$$tmp" "$@"; then mv "$$tmp" "$@"; else rm -f "$$tmp"; fi - + $(WRITE_CVWSOC_CFG) + +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_KEYS := $(CVWSOC_CFG_FAST_PRELOAD_KEYS) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_MODE := linux-fast +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_ROOTFS_MODE := jffs2 +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_INITRD_SRC := $(CVWSOC_LINUX_FAST_ROOTFS_SRC) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_BOOTARGS := $(CVWSOC_LINUX_FAST_BOOTARGS) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_ROOTFS_ADDR := $(ROOTFS_ADDR) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_ROOTFS_COMPATIBLE := $(ROOTFS_COMPATIBLE) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_ROOTFS_BANK_WIDTH := $(ROOTFS_BANK_WIDTH) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_ROOTFS_ERASE_SIZE := $(ROOTFS_ERASE_SIZE) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_RAW_BOOTMEM_FILE := $(CVWSOC_LINUX_FAST_RAW_BOOTROM_BIN) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_BOOTMEM_FILE := $(CVWSOC_LINUX_FAST_BOOTROM_BIN) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_RAW_RAM_FILE := $(CVWSOC_LINUX_FAST_RAW_EXT_RAM_BIN) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_RAM_FILE := $(CVWSOC_LINUX_FAST_EXT_RAM_BIN) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_QEMU_KERNEL := $(CVWSOC_LINUX_FAST_QEMU_KERNEL) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_QEMU_INITRD := $(CVWSOC_LINUX_FAST_QEMU_ROOTFS) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_GENERATED_DTS := $(CVWSOC_LINUX_FAST_QEMU_DTS) +$(CVWSOC_LINUX_FAST_PRELOAD_CFG): CVWSOC_CFG_GENERATED_DTB := $(CVWSOC_LINUX_FAST_QEMU_DTB) $(CVWSOC_LINUX_FAST_PRELOAD_CFG): FORCE | $(CVWSOC_PRELOAD_DIR) - @tmp="$@.tmp"; \ - { \ - printf 'MODE=linux-fast\n'; \ - printf 'ROOTFS_MODE=jffs2\n'; \ - printf 'IMAGE_KIND=%s\n' '$(CVWSOC_IMAGE_NAME)'; \ - printf 'FW_JUMP_BIN=%s\n' '$(CVWSOC_FW_JUMP_BIN)'; \ - printf 'KERNEL_SRC=%s\n' '$(CVWSOC_LINUX_KERNEL_SRC)'; \ - printf 'INITRD_SRC=%s\n' '$(CVWSOC_LINUX_FAST_ROOTFS_SRC)'; \ - printf 'DTS_SRC=%s\n' '$(CVWSOC_DTS_SRC)'; \ - printf 'BOOTARGS=%s\n' '$(CVWSOC_LINUX_FAST_BOOTARGS)'; \ - printf 'QEMU_BIN=%s\n' '$(QEMU_BIN)'; \ - printf 'QEMU_RAM_MB=%s\n' '$(QEMU_RAM_MB)'; \ - printf 'CPU_ARGS=%s\n' '$(CPU_ARGS)'; \ - printf 'GDB_BIN=%s\n' '$(GDB_BIN)'; \ - printf 'OBJCOPY_BIN=%s\n' '$(OBJCOPY_BIN)'; \ - printf 'CVWSOC_XLEN=%s\n' '$(CVWSOC_XLEN)'; \ - printf 'CVWSOC_BUS_WIDTH=%s\n' '$(CVWSOC_BUS_WIDTH)'; \ - printf 'PRELOAD_WORD_BYTES=%s\n' '$(CVWSOC_WORD_BYTES)'; \ - printf 'DTC_BIN=%s\n' '$(DTC_BIN)'; \ - printf 'UNLZ4_BIN=%s\n' '$(UNLZ4_BIN)'; \ - printf 'KERNEL_ADDR=%s\n' '$(CVWSOC_KERNEL_ADDR)'; \ - printf 'UBOOT_ADDR=%s\n' '$(UBOOT_ADDR)'; \ - printf 'UBOOT_STUB_BIN=%s\n' '$(CVWSOC_UBOOT_STUB_BIN)'; \ - printf 'KERNEL_DTB_ADDR=%s\n' '$(KERNEL_DTB_ADDR)'; \ - printf 'INITRD_ADDR=%s\n' '$(INITRD_ADDR)'; \ - printf 'ROOTFS_ADDR=%s\n' '$(ROOTFS_ADDR)'; \ - printf 'ROOTFS_COMPATIBLE=%s\n' '$(ROOTFS_COMPATIBLE)'; \ - printf 'ROOTFS_DTS_SIZE=%s\n' '$(ROOTFS_DTS_SIZE)'; \ - printf 'ROOTFS_BANK_WIDTH=%s\n' '$(ROOTFS_BANK_WIDTH)'; \ - printf 'ROOTFS_ERASE_SIZE=%s\n' '$(ROOTFS_ERASE_SIZE)'; \ - printf 'RAW_BOOTMEM_FILE=%s\n' '$(CVWSOC_LINUX_FAST_RAW_BOOTROM_BIN)'; \ - printf 'BOOTMEM_FILE=%s\n' '$(CVWSOC_LINUX_FAST_BOOTROM_BIN)'; \ - printf 'RAW_RAM_FILE=%s\n' '$(CVWSOC_LINUX_FAST_RAW_EXT_RAM_BIN)'; \ - printf 'RAM_FILE=%s\n' '$(CVWSOC_LINUX_FAST_EXT_RAM_BIN)'; \ - printf 'QEMU_KERNEL=%s\n' '$(CVWSOC_LINUX_FAST_QEMU_KERNEL)'; \ - printf 'QEMU_INITRD=%s\n' '$(CVWSOC_LINUX_FAST_QEMU_ROOTFS)'; \ - printf 'GENERATED_DTS=%s\n' '$(CVWSOC_LINUX_FAST_QEMU_DTS)'; \ - printf 'GENERATED_DTB=%s\n' '$(CVWSOC_LINUX_FAST_QEMU_DTB)'; \ - } > "$$tmp"; \ - if ! cmp -s "$$tmp" "$@"; then mv "$$tmp" "$@"; else rm -f "$$tmp"; fi - + $(WRITE_CVWSOC_CFG) + +$(CVWSOC_UBOOT_PRELOAD_CFG): CVWSOC_CFG_KEYS := $(CVWSOC_CFG_UBOOT_PRELOAD_KEYS) +$(CVWSOC_UBOOT_PRELOAD_CFG): CVWSOC_CFG_MODE := uboot +$(CVWSOC_UBOOT_PRELOAD_CFG): CVWSOC_CFG_RAW_BOOTMEM_FILE := $(CVWSOC_UBOOT_RAW_BOOTROM_BIN) +$(CVWSOC_UBOOT_PRELOAD_CFG): CVWSOC_CFG_BOOTMEM_FILE := $(CVWSOC_UBOOT_BOOTROM_BIN) +$(CVWSOC_UBOOT_PRELOAD_CFG): CVWSOC_CFG_RAW_RAM_FILE := $(CVWSOC_UBOOT_RAW_EXT_RAM_BIN) +$(CVWSOC_UBOOT_PRELOAD_CFG): CVWSOC_CFG_RAM_FILE := $(CVWSOC_UBOOT_EXT_RAM_BIN) +$(CVWSOC_UBOOT_PRELOAD_CFG): CVWSOC_CFG_QEMU_KERNEL := $(CVWSOC_UBOOT_QEMU_KERNEL) +$(CVWSOC_UBOOT_PRELOAD_CFG): CVWSOC_CFG_QEMU_INITRD := $(CVWSOC_UBOOT_QEMU_INITRD) +$(CVWSOC_UBOOT_PRELOAD_CFG): CVWSOC_CFG_GENERATED_DTS := $(CVWSOC_UBOOT_QEMU_DTS) +$(CVWSOC_UBOOT_PRELOAD_CFG): CVWSOC_CFG_GENERATED_DTB := $(CVWSOC_UBOOT_QEMU_DTB) $(CVWSOC_UBOOT_PRELOAD_CFG): FORCE | $(CVWSOC_PRELOAD_DIR) - @tmp="$@.tmp"; \ - { \ - printf 'MODE=uboot\n'; \ - printf 'IMAGE_KIND=%s\n' '$(CVWSOC_IMAGE_NAME)'; \ - printf 'INITRD_EXT2=%s\n' '$(if $(CVWSOC_USE_EXT2),1,0)'; \ - printf 'FW_JUMP_BIN=%s\n' '$(CVWSOC_FW_JUMP_BIN)'; \ - printf 'UBOOT_BIN=%s\n' '$(CVWSOC_UBOOT_BIN)'; \ - printf 'UBOOT_DTB=%s\n' '$(CVWSOC_UBOOT_DTB)'; \ - printf 'KERNEL_SRC=%s\n' '$(CVWSOC_LINUX_KERNEL_SRC)'; \ - printf 'INITRD_SRC=%s\n' '$(CVWSOC_LINUX_INITRD_SRC)'; \ - printf 'DTS_SRC=%s\n' '$(CVWSOC_DTS_SRC)'; \ - printf 'BOOTARGS=%s\n' '$(CVWSOC_LINUX_BOOTARGS)'; \ - printf 'QEMU_BIN=%s\n' '$(QEMU_BIN)'; \ - printf 'QEMU_RAM_MB=%s\n' '$(QEMU_RAM_MB)'; \ - printf 'CPU_ARGS=%s\n' '$(CPU_ARGS)'; \ - printf 'GDB_BIN=%s\n' '$(GDB_BIN)'; \ - printf 'OBJCOPY_BIN=%s\n' '$(OBJCOPY_BIN)'; \ - printf 'CVWSOC_XLEN=%s\n' '$(CVWSOC_XLEN)'; \ - printf 'CVWSOC_BUS_WIDTH=%s\n' '$(CVWSOC_BUS_WIDTH)'; \ - printf 'PRELOAD_WORD_BYTES=%s\n' '$(CVWSOC_WORD_BYTES)'; \ - printf 'DTC_BIN=%s\n' '$(DTC_BIN)'; \ - printf 'UNLZ4_BIN=%s\n' '$(UNLZ4_BIN)'; \ - printf 'KERNEL_ADDR=%s\n' '$(CVWSOC_KERNEL_ADDR)'; \ - printf 'UBOOT_DTB_ADDR=%s\n' '$(UBOOT_DTB_ADDR)'; \ - printf 'KERNEL_DTB_ADDR=%s\n' '$(KERNEL_DTB_ADDR)'; \ - printf 'INITRD_ADDR=%s\n' '$(INITRD_ADDR)'; \ - printf 'RAW_BOOTMEM_FILE=%s\n' '$(CVWSOC_UBOOT_RAW_BOOTROM_BIN)'; \ - printf 'BOOTMEM_FILE=%s\n' '$(CVWSOC_UBOOT_BOOTROM_BIN)'; \ - printf 'RAW_RAM_FILE=%s\n' '$(CVWSOC_UBOOT_RAW_EXT_RAM_BIN)'; \ - printf 'RAM_FILE=%s\n' '$(CVWSOC_UBOOT_EXT_RAM_BIN)'; \ - printf 'QEMU_KERNEL=%s\n' '$(CVWSOC_UBOOT_QEMU_KERNEL)'; \ - printf 'QEMU_INITRD=%s\n' '$(CVWSOC_UBOOT_QEMU_INITRD)'; \ - printf 'GENERATED_DTS=%s\n' '$(CVWSOC_UBOOT_QEMU_DTS)'; \ - printf 'GENERATED_DTB=%s\n' '$(CVWSOC_UBOOT_QEMU_DTB)'; \ - printf 'EXTERNAL_DTB=%s\n' '$(CVWSOC_VERILATOR_DTB)'; \ - } > "$$tmp"; \ - if ! cmp -s "$$tmp" "$@"; then mv "$$tmp" "$@"; else rm -f "$$tmp"; fi + $(WRITE_CVWSOC_CFG) $(CVWSOC_LINUX_QEMU_ASSETS) &: $(CVWSOC_LINUX_QEMU_CFG) $(WALLY)/linux/genCvwsocPreload.sh $(CVWSOC_DTS_SRC) $(CVWSOC_VERILATOR_DTB) $(CVWSOC_FW_JUMP_BIN) $(CVWSOC_LINUX_KERNEL_SRC) $(CVWSOC_LINUX_INITRD_SRC) $(CVWSOC_UBOOT_STUB_BIN) | $(CVWSOC_PRELOAD_DIR) SNAPSHOT_AT_HANDOFF=0 \ @@ -928,7 +924,13 @@ run-cvwsoc-linux-fast: UART_LOG := $(VERILATOR_DIR)/logs/testbench_cvwsoc_linux_ run-cvwsoc-linux-fast: $(CVWSOC_LINUX_FAST_RUN_DEPS) $(WORKDIR)/V$(TESTBENCH) $(CVWSOC_SD_IMAGE_DEPS) $(RUN_VERILATOR) -run-cvwsoc-linxu-fast: run-cvwsoc-linux-fast +# Fastest road to Linux shell prompt +sim-fast: + $(MAKE) -f $(lastword $(MAKEFILE_LIST)) RV32=$(RV32) CONFIG=$(CONFIG) CPUSETTINGS="$(CPUSETTINGS)" run-cvwsoc-linux-fast -j$$(nproc) + +# Fastest road to U-Boot prompt +sim-fast-uboot: + $(MAKE) -f $(lastword $(MAKEFILE_LIST)) RV32=$(RV32) CONFIG=$(CONFIG) CPUSETTINGS="$(CPUSETTINGS)" run-cvwsoc-uboot -j$$(nproc) run-cvwsoc-uboot: BOOTROM_BIN := $(if $(CVWSOC_BOOTROM),,$(CVWSOC_UBOOT_BOOTROM_BIN)) run-cvwsoc-uboot: EXT_RAM_BIN := $(if $(CVWSOC_BOOTROM),,$(CVWSOC_UBOOT_RUN_EXT_RAM_BIN)) @@ -958,7 +960,7 @@ runcmd-cvwsoc-uboot: $(CVWSOC_UBOOT_RUNCMD_DEPS) $(WORKDIR)/V$(TESTBENCH) $(CVWS printf '%s\r' "$(RUNCMD)" > $(RUNCMD_FILE) $(RUN_VERILATOR) -$(WORKDIR)/V$(TESTBENCH): $(WORKDIR)/V$(TESTBENCH).mk +$(WORKDIR)/V$(TESTBENCH): $(WORKDIR)/V$(TESTBENCH).mk $(WRAPPER) $(MAKE) -C $(WORKDIR) -f V$(TESTBENCH).mk \ OBJCACHE=ccache $(OPT_GEN) USER_CPPFLAGS="$(USER_CPPFLAGS) $(VERILATOR_USER_CPPFLAGS)" CXX=/usr/bin/g++ LINK=/usr/bin/g++ V$(TESTBENCH) @@ -979,13 +981,17 @@ $(WORKDIR)/V$(TESTBENCH).mk: $(DEPENDENCIES) $(EXPANDED_PARAM_ARGS) \ $(SOURCES) -clean: +cleantb: rm -rf \ $(VERILATOR_DIR)/wkdir/$(CONFIG)_cvwsoc \ $(VERILATOR_DIR)/wkdir/$(CONFIG)_cvwsoc_trace \ $(VERILATOR_DIR)/logs/testbench_cvwsoc*.out \ $(VERILATOR_DIR)/logs/testbench_cvwsoc*.pid \ $(RUNCMD_FILE) \ + dump.fst + +clean: cleantb + rm -rf \ $(CVWSOC_LINUX_QEMU_CFG) \ $(CVWSOC_UBOOT_QEMU_CFG) \ $(CVWSOC_LINUX_FAST_QEMU_CFG) \ @@ -1007,5 +1013,4 @@ clean: $(CVWSOC_LINUX_FAST_RAW_BOOTROM_BIN) \ $(CVWSOC_LINUX_FAST_RAW_EXT_RAM_BIN) \ $(CVWSOC_SD_IMAGE) \ - $(CVWSOC_SD_IMAGE).tmp \ - dump.fst + $(CVWSOC_SD_IMAGE).tmp diff --git a/sim/verilator/wrapper_cvwsoc.cpp b/sim/verilator/wrapper_cvwsoc.cpp index eb9ef06418..f40755b0b5 100644 --- a/sim/verilator/wrapper_cvwsoc.cpp +++ b/sim/verilator/wrapper_cvwsoc.cpp @@ -166,6 +166,12 @@ extern "C" void on_sigusr2(int) { g_trace_status_req.store(true, std::memory_order_relaxed); } +std::atomic g_stop_req{false}; + +extern "C" void on_stop(int) { + g_stop_req.store(true, std::memory_order_relaxed); +} + class UartPtyBridge { public: static constexpr std::uint64_t kNoTime = std::numeric_limits::max(); @@ -357,7 +363,7 @@ int main(int argc, char** argv, char**) { contextp->threads(sim_threads); contextp->commandArgs(argc, argv); #if VM_TRACE - Verilated::traceEverOn(true); + contextp->traceEverOn(true); #endif const std::unique_ptr topp{new Vtestbench_cvwsoc{contextp.get(), ""}}; @@ -390,6 +396,9 @@ int main(int argc, char** argv, char**) { topp->rootp->DUT_UART_RX = 1; + std::signal(SIGINT, on_stop); + std::signal(SIGTERM, on_stop); + #if VM_TRACE const std::string trace_prefix = get_plusarg_value(argc, argv, "+TRACE_FILE_PREFIX=", "dump"); @@ -414,7 +423,8 @@ int main(int argc, char** argv, char**) { } #endif - while (VL_LIKELY(!contextp->gotFinish())) { + while (VL_LIKELY(!contextp->gotFinish() + && !g_stop_req.load(std::memory_order_relaxed))) { #if VM_TRACE if (runtime_trace_control && g_trace_toggle_req.exchange(false, std::memory_order_relaxed)) { @@ -484,6 +494,16 @@ int main(int argc, char** argv, char**) { contextp->time(next_time); } + const bool interrupted = g_stop_req.load(std::memory_order_relaxed); + + if (interrupted) { + std::printf("[sim] caught SIGINT/SIGTERM, closing simulation cleanly at time=%llu\n", + static_cast(contextp->time())); + std::fflush(stdout); + } + + topp->final(); + #if VM_TRACE if (trace_enabled && tfp) { tfp->flush(); @@ -496,7 +516,6 @@ int main(int argc, char** argv, char**) { } #endif - topp->final(); contextp->statsPrintSummary(); - return 0; + return interrupted ? 130 : 0; } diff --git a/src/cvw.sv b/src/cvw.sv index 111f5c349a..55b5778d60 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -164,12 +164,18 @@ typedef struct packed { logic WISHBONE_STUB_SUPPORTED; logic [63:0] WISHBONE_STUB_BASE; logic [63:0] WISHBONE_STUB_RANGE; + logic AXI_IDMA_SUPPORTED; + logic [63:0] AXI_IDMA_BASE; + logic [63:0] AXI_IDMA_RANGE; + logic AXI_IDMA_REG64_SUPPORTED; + logic [63:0] AXI_IDMA_REG64_BASE; + logic [63:0] AXI_IDMA_REG64_RANGE; logic AXI_SDHCI_SUPPORTED; logic [63:0] AXI_SDHCI_BASE; logic [63:0] AXI_SDHCI_RANGE; - logic AXI_DMA_SUPPORTED; - logic [63:0] AXI_DMA_BASE; - logic [63:0] AXI_DMA_RANGE; + logic XILINX_AXI_DMA_SUPPORTED; + logic [63:0] XILINX_AXI_DMA_BASE; + logic [63:0] XILINX_AXI_DMA_RANGE; logic AXI_VGA_SUPPORTED; logic [63:0] AXI_VGA_BASE; logic [63:0] AXI_VGA_RANGE; diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv index e07f366109..481343119b 100644 --- a/src/mmu/adrdecs.sv +++ b/src/mmu/adrdecs.sv @@ -33,7 +33,7 @@ module adrdecs import cvw::*; #(parameter cvw_t P) ( input logic [P.PA_BITS-1:0] PhysicalAddress, input logic AccessRW, AccessRX, AccessRWXC, input logic [1:0] Size, - output logic [19:0] SelRegions + output logic [21:0] SelRegions ); localparam logic [3:0] SUPPORTED_SIZE = (P.LLEN == 32 ? 4'b0111 : 4'b1111); @@ -50,15 +50,17 @@ module adrdecs import cvw::*; #(parameter cvw_t P) ( adrdec #(P.PA_BITS) sdcdec(PhysicalAddress, P.SDC_BASE[P.PA_BITS-1:0], P.SDC_RANGE[P.PA_BITS-1:0], P.SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[10]); adrdec #(P.PA_BITS) spidec(PhysicalAddress, P.SPI_BASE[P.PA_BITS-1:0], P.SPI_RANGE[P.PA_BITS-1:0], P.SPI_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[11]); adrdec #(P.PA_BITS) wbdec(PhysicalAddress, P.WISHBONE_BASE[P.PA_BITS-1:0], P.WISHBONE_RANGE[P.PA_BITS-1:0], P.WISHBONE_SUPPORTED, AccessRW, Size, 4'b0111, SelRegions[12]); - adrdec #(P.PA_BITS) axidmadec(PhysicalAddress, P.AXI_DMA_BASE[P.PA_BITS-1:0], P.AXI_DMA_RANGE[P.PA_BITS-1:0], P.AXI_DMA_SUPPORTED, AccessRW, Size, 4'b0111, SelRegions[13]); + adrdec #(P.PA_BITS) axicdmadec(PhysicalAddress, P.XILINX_AXI_DMA_BASE[P.PA_BITS-1:0], P.XILINX_AXI_DMA_RANGE[P.PA_BITS-1:0], P.XILINX_AXI_DMA_SUPPORTED, AccessRW, Size, 4'b0111, SelRegions[13]); adrdec #(P.PA_BITS) axivgadec(PhysicalAddress, P.AXI_VGA_BASE[P.PA_BITS-1:0], P.AXI_VGA_RANGE[P.PA_BITS-1:0], P.AXI_VGA_SUPPORTED, AccessRW, Size, 4'b0111, SelRegions[14]); adrdec #(P.PA_BITS) axiusbdec(PhysicalAddress, P.AXI_USB_BASE[P.PA_BITS-1:0], P.AXI_USB_RANGE[P.PA_BITS-1:0], P.AXI_USB_SUPPORTED, AccessRW, Size, 4'b0111, SelRegions[15]); adrdec #(P.PA_BITS) axiethdec(PhysicalAddress, P.AXI_ETH_BASE[P.PA_BITS-1:0], P.AXI_ETH_RANGE[P.PA_BITS-1:0], P.AXI_ETH_SUPPORTED, AccessRW, Size, 4'b0111, SelRegions[16]); adrdec #(P.PA_BITS) axilddec(PhysicalAddress, P.LITEDRAM_BASE[P.PA_BITS-1:0], P.LITEDRAM_RANGE[P.PA_BITS-1:0], P.LITEDRAM_SUPPORTED, AccessRW, Size, 4'b0111, SelRegions[17]); adrdec #(P.PA_BITS) axidummydec(PhysicalAddress, P.AXI_DUMMY_BASE[P.PA_BITS-1:0], P.AXI_DUMMY_RANGE[P.PA_BITS-1:0], P.AXI_DUMMY_SUPPORTED, AccessRW, Size, 4'b0111, SelRegions[18]); adrdec #(P.PA_BITS) axisdhcidec(PhysicalAddress, P.AXI_SDHCI_BASE[P.PA_BITS-1:0], P.AXI_SDHCI_RANGE[P.PA_BITS-1:0], P.AXI_SDHCI_SUPPORTED, AccessRW, Size, 4'b0111, SelRegions[19]); + adrdec #(P.PA_BITS) axiidmadec(PhysicalAddress, P.AXI_IDMA_BASE[P.PA_BITS-1:0], P.AXI_IDMA_RANGE[P.PA_BITS-1:0], P.AXI_IDMA_SUPPORTED, AccessRW, Size, 4'b0111, SelRegions[20]); + adrdec #(P.PA_BITS) axiidmareg64dec(PhysicalAddress, P.AXI_IDMA_REG64_BASE[P.PA_BITS-1:0], P.AXI_IDMA_REG64_RANGE[P.PA_BITS-1:0], P.AXI_IDMA_REG64_SUPPORTED, AccessRW, Size, 4'b0111, SelRegions[21]); - assign SelRegions[0] = ~|(SelRegions[19:1]); // none of the regions are selected + assign SelRegions[0] = ~|(SelRegions[21:1]); // none of the regions are selected endmodule // verilator lint_on UNOPTFLAT diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index 8fd5f0bf88..ec9e9eb42e 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -46,7 +46,7 @@ module pmachecker import cvw::*; #(parameter cvw_t P) ( logic PMAAccessFault; logic AccessRW, AccessRWXC, AccessRX; - logic [19:0] SelRegions; + logic [21:0] SelRegions; logic AtomicAllowed; logic CacheableRegion, IdempotentRegion; logic UncachedMemRegion; diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index d1b1bc9d4d..64aab43f45 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -92,7 +92,7 @@ module uncore import cvw::*; #(parameter cvw_t P)( logic [3:0] wb_sel; logic wb_we, wb_cyc, wb_stb, wb_ack, wb_err; - logic [19:0] HSELRegions; + logic [21:0] HSELRegions; logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART,HSELSDC, HSELSPI; logic HSELDTIMD, HSELIROMD, HSELEXTD_DDR, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD, HSELSPID; // Wishbone extension @@ -129,6 +129,12 @@ module uncore import cvw::*; #(parameter cvw_t P)( // SDHCI AXI peripheral logic HSELAXISDHCI; logic HSELAXISDHCID; + // iDMA desc64 AXI peripheral + logic HSELAXIIDMA; + logic HSELAXIIDMAD; + // iDMA reg64 AXI peripheral + logic HSELAXIIDMAREG64; + logic HSELAXIIDMAREG64D; logic PCLK, PRESETn, PWRITE, PENABLE; @@ -164,7 +170,7 @@ module uncore import cvw::*; #(parameter cvw_t P)( adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions); // unswizzle HSEL signals - assign {HSELAXISDHCI, HSELAXIDUMMY, HSELAXILITEDRAM, HSELAXIETH, HSELAXIUSB, HSELAXIVGA, HSELAXIDMA, HSELWbIsland, HSELSPI, HSELSDC, HSELPLIC, HSELUART, HSELGPIO, HSELCLINT, HSELRam, HSELBootRom, HSELEXT_DDR, HSELIROM, HSELDTIM} = HSELRegions[19:1]; + assign {HSELAXIIDMAREG64, HSELAXIIDMA, HSELAXISDHCI, HSELAXIDUMMY, HSELAXILITEDRAM, HSELAXIETH, HSELAXIUSB, HSELAXIVGA, HSELAXIDMA, HSELWbIsland, HSELSPI, HSELSDC, HSELPLIC, HSELUART, HSELGPIO, HSELCLINT, HSELRam, HSELBootRom, HSELEXT_DDR, HSELIROM, HSELDTIM} = HSELRegions[21:1]; // AHB -> APB bridge ahbapbbridge #(P, 6) ahbapbbridge ( @@ -278,8 +284,8 @@ module uncore import cvw::*; #(parameter cvw_t P)( end // AXI Select signals - assign HSELEXTD_ALL = HSELEXTD_DDR | HSELAXIDMAD | HSELAXIVGAD | HSELAXIUSBD | HSELAXIETHD | HSELAXILITEDRAMD | HSELAXIDUMMYD | HSELAXISDHCID; - assign HSELEXT = HSELEXT_DDR | HSELAXIDMA | HSELAXIVGA | HSELAXIUSB | HSELAXIETH | HSELAXILITEDRAM | HSELAXIDUMMY | HSELAXISDHCI; // OUTPUT + assign HSELEXTD_ALL = HSELEXTD_DDR | HSELAXIDMAD | HSELAXIVGAD | HSELAXIUSBD | HSELAXIETHD | HSELAXILITEDRAMD | HSELAXIDUMMYD | HSELAXISDHCID | HSELAXIIDMAD | HSELAXIIDMAREG64D; + assign HSELEXT = HSELEXT_DDR | HSELAXIDMA | HSELAXIVGA | HSELAXIUSB | HSELAXIETH | HSELAXILITEDRAM | HSELAXIDUMMY | HSELAXISDHCI | HSELAXIIDMA | HSELAXIIDMAREG64; // OUTPUT // AHB Read Multiplexer assign HRDATA = ({P.AHBW{HSELRamD}} & HREADRam) | @@ -306,8 +312,8 @@ module uncore import cvw::*; #(parameter cvw_t P)( // takes more than 1 cycle to respond it needs to hold on to the old select until the // device is ready. Hence this register must be selectively enabled by HREADY. // However on reset None must be selected. - flopenl #(20) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 20'b1, - {HSELAXISDHCID, HSELAXIDUMMYD, HSELAXILITEDRAMD, HSELAXIETHD, HSELAXIUSBD, HSELAXIVGAD, HSELAXIDMAD, HSELWbIslandD, HSELSPID, HSELSDCD, HSELPLICD, HSELUARTD, HSELGPIOD, HSELCLINTD, + flopenl #(22) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 22'b1, + {HSELAXIIDMAREG64D, HSELAXIIDMAD, HSELAXISDHCID, HSELAXIDUMMYD, HSELAXILITEDRAMD, HSELAXIETHD, HSELAXIUSBD, HSELAXIVGAD, HSELAXIDMAD, HSELWbIslandD, HSELSPID, HSELSDCD, HSELPLICD, HSELUARTD, HSELGPIOD, HSELCLINTD, HSELRamD, HSELBootRomD, HSELEXTD_DDR, HSELIROMD, HSELDTIMD, HSELNoneD}); flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED); endmodule diff --git a/testbench/testbench_cvwsoc.sv b/testbench/testbench_cvwsoc.sv index 5c53048e39..05ea5ce704 100644 --- a/testbench/testbench_cvwsoc.sv +++ b/testbench/testbench_cvwsoc.sv @@ -5,8 +5,6 @@ // Wally SoC -> external AHB -> AHB/AXI bridge -> AXI CDC -> AXI xbar // -> functional AXI RAM + small AXI peripheral RAM // -// This keeps the bridge-focused setup intact while adding the missing base -// bus components used by the cvwsoc virtual platform. /////////////////////////////////////////// `timescale 1ns / 1ps @@ -26,7 +24,8 @@ import cvw::*; module testbench_cvwsoc #( parameter int unsigned CLK_PERIOD_NS = 10, //parameter int unsigned BUS_CLK_PERIOD_NS = 7, - parameter int unsigned BUS_CLK_PERIOD_NS = 5, //a bit faster simulation? + // busclk value affects simulation speed + parameter int unsigned BUS_CLK_PERIOD_NS = 10, parameter int unsigned RESET_CYCLES = 32, parameter int unsigned BUS_RESET_CYCLES = 64, parameter int unsigned EXT_MEM_ADDR_WIDTH = 30, @@ -64,7 +63,7 @@ module testbench_cvwsoc #( `else tmp.AXI_SDHCI_SUPPORTED = 1'b0; `endif - tmp.AXI_DMA_SUPPORTED = 1'b0; + tmp.XILINX_AXI_DMA_SUPPORTED = 1'b0; tmp.AXI_VGA_SUPPORTED = 1'b0; tmp.AXI_USB_SUPPORTED = 1'b0; tmp.AXI_ETH_SUPPORTED = 1'b0; @@ -73,6 +72,8 @@ module testbench_cvwsoc #( // Veri-lator $readmemh complains when boot.mem is bigger than size tmp.BOOTROM_RANGE = 64'h1FFFF; tmp.AXI_DUMMY_SUPPORTED = 1'b1; + tmp.AXI_IDMA_SUPPORTED = 1'b0; // enable to have iDMA + tmp.AXI_IDMA_REG64_SUPPORTED = 1'b1; cvwsoc_sim_cfg = tmp; end endfunction @@ -80,14 +81,18 @@ module testbench_cvwsoc #( localparam BUSW = P.AHBW; // AXI width = AHB width localparam cvw_t SOC_P = cvwsoc_sim_cfg(P); localparam int unsigned AXI_ID_WIDTH = 4; - localparam int unsigned XBAR_NUM_SLV_PORTS = 2; - localparam int unsigned XBAR_NUM_MST_PORTS = 3; - localparam int unsigned XBAR_NUM_ADDR_RULES = 3; + localparam int unsigned XBAR_NUM_SLV_PORTS = 3; + localparam int unsigned XBAR_NUM_MST_PORTS = 5; + localparam int unsigned XBAR_NUM_ADDR_RULES = 5; localparam int unsigned AXI_MST_ID_WIDTH = AXI_ID_WIDTH + $clog2(XBAR_NUM_SLV_PORTS); localparam logic [31:0] EXT_RAM_BASE_ADDR = 32'h8000_0000; localparam logic [31:0] EXT_RAM_END_ADDR = EXT_RAM_BASE_ADDR + (32'd1 << EXT_MEM_ADDR_WIDTH); localparam logic [31:0] SDHCI_BASE_ADDR = SOC_P.AXI_SDHCI_BASE[31:0]; localparam logic [31:0] SDHCI_END_ADDR = SDHCI_BASE_ADDR + SOC_P.AXI_SDHCI_RANGE[31:0] + 32'd1; + localparam logic [31:0] AXI_IDMA_BASE_ADDR = SOC_P.AXI_IDMA_BASE[31:0]; + localparam logic [31:0] AXI_IDMA_END_ADDR = AXI_IDMA_BASE_ADDR + SOC_P.AXI_IDMA_RANGE[31:0] + 32'd1; + localparam logic [31:0] AXI_IDMA_REG64_BASE_ADDR = SOC_P.AXI_IDMA_REG64_BASE[31:0]; + localparam logic [31:0] AXI_IDMA_REG64_END_ADDR = AXI_IDMA_REG64_BASE_ADDR + SOC_P.AXI_IDMA_REG64_RANGE[31:0] + 32'd1; localparam logic [31:0] AXI_DUMMY_BASE_ADDR = SOC_P.AXI_DUMMY_BASE[31:0]; localparam logic [31:0] AXI_DUMMY_END_ADDR = AXI_DUMMY_BASE_ADDR + SOC_P.AXI_DUMMY_RANGE[31:0] + 32'd1; localparam longint unsigned HEARTBEAT_CYCLES = 10_000_000; @@ -143,7 +148,9 @@ module testbench_cvwsoc #( localparam axi_pkg::xbar_rule_32_t [XBAR_NUM_ADDR_RULES-1:0] XBAR_ADDR_MAP = '{ '{ idx: 0, start_addr: EXT_RAM_BASE_ADDR, end_addr: EXT_RAM_END_ADDR }, '{ idx: 1, start_addr: SDHCI_BASE_ADDR, end_addr: SDHCI_END_ADDR }, - '{ idx: 2, start_addr: AXI_DUMMY_BASE_ADDR, end_addr: AXI_DUMMY_END_ADDR } + '{ idx: 2, start_addr: AXI_DUMMY_BASE_ADDR, end_addr: AXI_DUMMY_END_ADDR }, + '{ idx: 3, start_addr: AXI_IDMA_BASE_ADDR, end_addr: AXI_IDMA_END_ADDR }, + '{ idx: 4, start_addr: AXI_IDMA_REG64_BASE_ADDR, end_addr: AXI_IDMA_REG64_END_ADDR } }; // --------------------------------------------------------------------------- @@ -196,11 +203,13 @@ module testbench_cvwsoc #( // Top-level debug aliases. The focused FST dump only keeps signals that are // reachable from this testbench scope, so keep the fault/debug path here. - logic [19:0] dbg_uncore_hselregions; + logic [21:0] dbg_uncore_hselregions; logic dbg_uncore_hsel_ram; logic dbg_uncore_hsel_ram_d; logic dbg_uncore_hsel_axisdhci; logic dbg_uncore_hsel_axisdhci_d; + logic dbg_uncore_hsel_axidma; + logic dbg_uncore_hsel_axidma_d; logic [P.PA_BITS-1:0] dbg_uncore_haddr; logic [P.AHBW-1:0] dbg_uncore_hwdata; logic [P.AHBW/8-1:0] dbg_uncore_hwstrb; @@ -285,15 +294,18 @@ module testbench_cvwsoc #( logic WB_RMII_RST_N; logic WB_RMII_PHY_IRQ = 1'b0; - logic AXI_DMAIntr = 1'b0; + //logic AXI_DMAIntr; + logic AXI_IDMAIntr; logic AXI_USBIntr = 1'b0; logic AXI_EthIntr = 1'b0; logic AXI_SDHCIIntr; logic AXI_SDHCIIntr_orig; - logic AXI_DummyIntr = 1'b0; + logic AXI_DummyIntr; logic AXI_DummyIntr_orig; logic ExternalStall = 1'b0; + //assign AXI_DMAIntr = AXI_IDMAIntr; + // --------------------------------------------------------------------------- // Bridge AXI master signals // --------------------------------------------------------------------------- @@ -361,6 +373,8 @@ module testbench_cvwsoc #( assign dbg_uncore_hselregions = soc.uncoregen.uncore.HSELRegions; assign dbg_uncore_hsel_axisdhci = soc.uncoregen.uncore.HSELAXISDHCI; assign dbg_uncore_hsel_axisdhci_d = soc.uncoregen.uncore.HSELAXISDHCID; + assign dbg_uncore_hsel_axidma = soc.uncoregen.uncore.HSELAXIDMA; + assign dbg_uncore_hsel_axidma_d = soc.uncoregen.uncore.HSELAXIDMAD; assign dbg_load_misaligned_fault_m = soc.core.LoadMisalignedFaultM; assign dbg_load_access_fault_m = soc.core.LoadAccessFaultM; assign dbg_load_page_fault_m = soc.core.LoadPageFaultM; @@ -480,7 +494,7 @@ module testbench_cvwsoc #( .WB_RMII_MDIO(WB_RMII_MDIO), .WB_RMII_RST_N(WB_RMII_RST_N), .WB_RMII_PHY_IRQ(WB_RMII_PHY_IRQ), - .AXI_DMAIntr(AXI_DMAIntr), + .AXI_DMAIntr(AXI_IDMAIntr), .AXI_USBIntr(AXI_USBIntr), .AXI_EthIntr(AXI_EthIntr), .AXI_SDHCIIntr(AXI_SDHCIIntr), @@ -618,12 +632,405 @@ module testbench_cvwsoc #( .dst_resp_i (cdc_axi_resp) ); - // Slave port 0 is the real SoC traffic coming through the CDC. Slave port 1 - // is an always-idle dummy master so the xbar is instantiated with more than - // one requester. + // Slave port 0 is CPU traffic through the CDC. Slave port 1 is desc64 + // descriptor-fetch traffic. Slave port 2 is the shared iDMA backend master. assign slv_req[0] = cdc_axi_req; assign cdc_axi_resp = slv_resp[0]; - assign slv_req[1] = '0; + + logic dbg_idmar64_irq_pending; + logic dbg_idmar64_irq_enable; + logic dbg_idmar64_irq_clear_wr; + logic dbg_idmar64_irq_enable_wr; + logic dbg_idmar64_sel_irq_status; + logic dbg_idmar64_sel_irq_enable; + logic dbg_idmar64_sel_irq; + logic dbg_idmar64_axi_aw_valid; + logic dbg_idmar64_axi_aw_ready; + logic [31:0] dbg_idmar64_axi_aw_addr; + logic dbg_idmar64_axi_w_valid; + logic dbg_idmar64_axi_w_ready; + logic [BUSW-1:0] dbg_idmar64_axi_w_data; + logic [BUSW/8-1:0] dbg_idmar64_axi_w_strb; + logic dbg_idmar64_axi_b_valid; + logic dbg_idmar64_axi_b_ready; + logic [1:0] dbg_idmar64_axi_b_resp; + logic dbg_idmar64_reg_req_valid; + logic dbg_idmar64_reg_req_write; + logic [31:0] dbg_idmar64_reg_req_addr; + logic [31:0] dbg_idmar64_reg_req_wdata; + logic [3:0] dbg_idmar64_reg_req_wstrb; + logic dbg_idmar64_reg_rsp_ready; + logic dbg_idmar64_reg_rsp_error; + logic [31:0] dbg_idmar64_reg_rsp_rdata; + logic dbg_idmar64_idma_reg_req_valid; + logic dbg_idmar64_idma_reg_req_write; + logic [31:0] dbg_idmar64_idma_reg_req_addr; + logic [31:0] dbg_idmar64_idma_reg_req_wdata; + logic [3:0] dbg_idmar64_idma_reg_req_wstrb; + logic dbg_idmar64_idma_reg_rsp_ready; + logic dbg_idmar64_idma_reg_rsp_error; + logic [31:0] dbg_idmar64_idma_reg_rsp_rdata; + logic dbg_idmad64_irq; + logic dbg_idmad64_irq_pending; + logic dbg_idmad64_irq_enable; + logic dbg_idmad64_irq_clear_wr; + logic dbg_idmad64_irq_enable_wr; + logic dbg_idmad64_mmio_aw_valid; + logic dbg_idmad64_mmio_aw_ready; + logic [31:0] dbg_idmad64_mmio_aw_addr; + logic dbg_idmad64_mmio_w_valid; + logic dbg_idmad64_mmio_w_ready; + logic [BUSW-1:0] dbg_idmad64_mmio_w_data; + logic [BUSW/8-1:0] dbg_idmad64_mmio_w_strb; + logic dbg_idmad64_mmio_b_valid; + logic dbg_idmad64_mmio_b_ready; + logic [1:0] dbg_idmad64_mmio_b_resp; + logic dbg_idmad64_mmio_ar_valid; + logic dbg_idmad64_mmio_ar_ready; + logic [31:0] dbg_idmad64_mmio_ar_addr; + logic dbg_idmad64_mmio_r_valid; + logic dbg_idmad64_mmio_r_ready; + logic [BUSW-1:0] dbg_idmad64_mmio_r_data; + logic [1:0] dbg_idmad64_mmio_r_resp; + logic dbg_idmad64_desc_ar_valid; + logic dbg_idmad64_desc_ar_ready; + logic [31:0] dbg_idmad64_desc_ar_addr; + logic [7:0] dbg_idmad64_desc_ar_len; + logic dbg_idmad64_desc_r_valid; + logic dbg_idmad64_desc_r_ready; + logic [BUSW-1:0] dbg_idmad64_desc_r_data; + logic dbg_idmad64_desc_r_last; + logic dbg_idmad64_desc_aw_valid; + logic dbg_idmad64_desc_aw_ready; + logic [31:0] dbg_idmad64_desc_aw_addr; + logic dbg_idmad64_desc_w_valid; + logic dbg_idmad64_desc_w_ready; + logic [BUSW-1:0] dbg_idmad64_desc_w_data; + logic [BUSW/8-1:0] dbg_idmad64_desc_w_strb; + logic dbg_idmad64_desc_b_valid; + logic dbg_idmad64_desc_b_ready; + logic dbg_idmad64_be_ar_valid; + logic dbg_idmad64_be_ar_ready; + logic [31:0] dbg_idmad64_be_ar_addr; + logic [7:0] dbg_idmad64_be_ar_len; + logic dbg_idmad64_be_r_valid; + logic dbg_idmad64_be_r_ready; + logic [BUSW-1:0] dbg_idmad64_be_r_data; + logic dbg_idmad64_be_r_last; + logic dbg_idmad64_be_aw_valid; + logic dbg_idmad64_be_aw_ready; + logic [31:0] dbg_idmad64_be_aw_addr; + logic [7:0] dbg_idmad64_be_aw_len; + logic dbg_idmad64_be_w_valid; + logic dbg_idmad64_be_w_ready; + logic [BUSW-1:0] dbg_idmad64_be_w_data; + logic [BUSW/8-1:0] dbg_idmad64_be_w_strb; + logic dbg_idmad64_be_b_valid; + logic dbg_idmad64_be_b_ready; + logic dbg_idmad64_input_addr_valid; + logic dbg_idmad64_input_addr_ready; + logic [63:0] dbg_idmad64_input_addr; + logic dbg_idmad64_queued_addr_valid; + logic dbg_idmad64_queued_addr_ready; + logic [63:0] dbg_idmad64_queued_addr; + logic dbg_idmad64_idma_req_valid; + logic dbg_idmad64_idma_req_ready; + logic dbg_idmad64_idma_rsp_valid; + logic dbg_idmad64_idma_rsp_ready; + logic dbg_idmad64_do_irq; + logic dbg_idmad64_do_irq_valid; + logic dbg_idmad64_do_irq_ready; + logic dbg_idmad64_do_irq_out; + + mst_req_t [1:0] idma_slv_req; + mst_resp_t [1:0] idma_slv_resp; + + assign idma_slv_req[0] = mst_req[3]; + assign idma_slv_req[1] = mst_req[4]; + assign mst_resp[3] = idma_slv_resp[0]; + assign mst_resp[4] = idma_slv_resp[1]; + + if (SOC_P.AXI_IDMA_SUPPORTED || SOC_P.AXI_IDMA_REG64_SUPPORTED) begin : gen_idma + idma_wrap #( + .AxiAddrWidth ( 32 ), + .AxiDataWidth ( BUSW ), + .AxiIdWidth ( AXI_ID_WIDTH ), + .AxiUserWidth ( 1 ), + .AxiSlvIdWidth ( AXI_MST_ID_WIDTH ), + .AxiMaxReadTxns ( 4 ), + .AxiMaxWriteTxns ( 4 ), + .NumAxInFlight ( 4 ), + .MemSysDepth ( 0 ), + .JobFifoDepth ( 2 ), + .RAWCouplingAvail ( 1'b0 ), + .EnableDesc64 ( SOC_P.AXI_IDMA_SUPPORTED ), + .EnableReg64 ( SOC_P.AXI_IDMA_REG64_SUPPORTED ), + .EnableReg64TwoD ( 1'b0 ), + .axi_mst_req_t ( slv_req_t ), + .axi_mst_rsp_t ( slv_resp_t ), + .axi_slv_req_t ( mst_req_t ), + .axi_slv_rsp_t ( mst_resp_t ) + ) idma_i ( + .clk_i ( bus_clk ), + .rst_ni ( ~bus_reset ), + .testmode_i ( 1'b0 ), + .axi_mst_fe_req_o ( slv_req[1] ), + .axi_mst_fe_rsp_i ( slv_resp[1] ), + .axi_mst_be_req_o ( slv_req[2] ), + .axi_mst_be_rsp_i ( slv_resp[2] ), + .axi_slv_req_i ( idma_slv_req ), + .axi_slv_rsp_o ( idma_slv_resp ), + .irq_o ( AXI_IDMAIntr ) + ); + + assign dbg_idmar64_irq_pending = idma_i.irq_pending; + assign dbg_idmar64_irq_enable = idma_i.irq_enable; + assign dbg_idmar64_irq_clear_wr = idma_i.irq_clear_wr; + assign dbg_idmar64_irq_enable_wr = idma_i.irq_enable_wr; + assign dbg_idmar64_sel_irq_status = idma_i.sel_irq_status; + assign dbg_idmar64_sel_irq_enable = idma_i.sel_irq_enable; + assign dbg_idmar64_sel_irq = idma_i.sel_irq; + assign dbg_idmar64_axi_aw_valid = mst_req[4].aw_valid; + assign dbg_idmar64_axi_aw_ready = mst_resp[4].aw_ready; + assign dbg_idmar64_axi_aw_addr = mst_req[4].aw.addr; + assign dbg_idmar64_axi_w_valid = mst_req[4].w_valid; + assign dbg_idmar64_axi_w_ready = mst_resp[4].w_ready; + assign dbg_idmar64_axi_w_data = mst_req[4].w.data; + assign dbg_idmar64_axi_w_strb = mst_req[4].w.strb; + assign dbg_idmar64_axi_b_valid = mst_resp[4].b_valid; + assign dbg_idmar64_axi_b_ready = mst_req[4].b_ready; + assign dbg_idmar64_axi_b_resp = mst_resp[4].b.resp; + assign dbg_idmar64_reg_req_valid = idma_i.dma_reg_req.valid; + assign dbg_idmar64_reg_req_write = idma_i.dma_reg_req.write; + assign dbg_idmar64_reg_req_addr = idma_i.dma_reg_req.addr[31:0]; + assign dbg_idmar64_reg_req_wdata = idma_i.dma_reg_req.wdata; + assign dbg_idmar64_reg_req_wstrb = idma_i.dma_reg_req.wstrb; + assign dbg_idmar64_reg_rsp_ready = idma_i.dma_reg_rsp.ready; + assign dbg_idmar64_reg_rsp_error = idma_i.dma_reg_rsp.error; + assign dbg_idmar64_reg_rsp_rdata = idma_i.dma_reg_rsp.rdata; + assign dbg_idmar64_idma_reg_req_valid = idma_i.idma_reg_req.valid; + assign dbg_idmar64_idma_reg_req_write = idma_i.idma_reg_req.write; + assign dbg_idmar64_idma_reg_req_addr = idma_i.idma_reg_req.addr[31:0]; + assign dbg_idmar64_idma_reg_req_wdata = idma_i.idma_reg_req.wdata; + assign dbg_idmar64_idma_reg_req_wstrb = idma_i.idma_reg_req.wstrb; + assign dbg_idmar64_idma_reg_rsp_ready = idma_i.idma_reg_rsp.ready; + assign dbg_idmar64_idma_reg_rsp_error = idma_i.idma_reg_rsp.error; + assign dbg_idmar64_idma_reg_rsp_rdata = idma_i.idma_reg_rsp.rdata; + + assign dbg_idmad64_irq = AXI_IDMAIntr; + assign dbg_idmad64_irq_pending = idma_i.desc64_irq_pending; + assign dbg_idmad64_irq_enable = idma_i.desc64_irq_enable; + assign dbg_idmad64_irq_clear_wr = idma_i.desc64_irq_clear_wr; + assign dbg_idmad64_irq_enable_wr = idma_i.desc64_irq_enable_wr; + assign dbg_idmad64_mmio_aw_valid = mst_req[3].aw_valid; + assign dbg_idmad64_mmio_aw_ready = mst_resp[3].aw_ready; + assign dbg_idmad64_mmio_aw_addr = mst_req[3].aw.addr; + assign dbg_idmad64_mmio_w_valid = mst_req[3].w_valid; + assign dbg_idmad64_mmio_w_ready = mst_resp[3].w_ready; + assign dbg_idmad64_mmio_w_data = mst_req[3].w.data; + assign dbg_idmad64_mmio_w_strb = mst_req[3].w.strb; + assign dbg_idmad64_mmio_b_valid = mst_resp[3].b_valid; + assign dbg_idmad64_mmio_b_ready = mst_req[3].b_ready; + assign dbg_idmad64_mmio_b_resp = mst_resp[3].b.resp; + assign dbg_idmad64_mmio_ar_valid = mst_req[3].ar_valid; + assign dbg_idmad64_mmio_ar_ready = mst_resp[3].ar_ready; + assign dbg_idmad64_mmio_ar_addr = mst_req[3].ar.addr; + assign dbg_idmad64_mmio_r_valid = mst_resp[3].r_valid; + assign dbg_idmad64_mmio_r_ready = mst_req[3].r_ready; + assign dbg_idmad64_mmio_r_data = mst_resp[3].r.data; + assign dbg_idmad64_mmio_r_resp = mst_resp[3].r.resp; + assign dbg_idmad64_desc_ar_valid = slv_req[1].ar_valid; + assign dbg_idmad64_desc_ar_ready = slv_resp[1].ar_ready; + assign dbg_idmad64_desc_ar_addr = slv_req[1].ar.addr; + assign dbg_idmad64_desc_ar_len = slv_req[1].ar.len; + assign dbg_idmad64_desc_r_valid = slv_resp[1].r_valid; + assign dbg_idmad64_desc_r_ready = slv_req[1].r_ready; + assign dbg_idmad64_desc_r_data = slv_resp[1].r.data; + assign dbg_idmad64_desc_r_last = slv_resp[1].r.last; + assign dbg_idmad64_desc_aw_valid = slv_req[1].aw_valid; + assign dbg_idmad64_desc_aw_ready = slv_resp[1].aw_ready; + assign dbg_idmad64_desc_aw_addr = slv_req[1].aw.addr; + assign dbg_idmad64_desc_w_valid = slv_req[1].w_valid; + assign dbg_idmad64_desc_w_ready = slv_resp[1].w_ready; + assign dbg_idmad64_desc_w_data = slv_req[1].w.data; + assign dbg_idmad64_desc_w_strb = slv_req[1].w.strb; + assign dbg_idmad64_desc_b_valid = slv_resp[1].b_valid; + assign dbg_idmad64_desc_b_ready = slv_req[1].b_ready; + assign dbg_idmad64_be_ar_valid = slv_req[2].ar_valid; + assign dbg_idmad64_be_ar_ready = slv_resp[2].ar_ready; + assign dbg_idmad64_be_ar_addr = slv_req[2].ar.addr; + assign dbg_idmad64_be_ar_len = slv_req[2].ar.len; + assign dbg_idmad64_be_r_valid = slv_resp[2].r_valid; + assign dbg_idmad64_be_r_ready = slv_req[2].r_ready; + assign dbg_idmad64_be_r_data = slv_resp[2].r.data; + assign dbg_idmad64_be_r_last = slv_resp[2].r.last; + assign dbg_idmad64_be_aw_valid = slv_req[2].aw_valid; + assign dbg_idmad64_be_aw_ready = slv_resp[2].aw_ready; + assign dbg_idmad64_be_aw_addr = slv_req[2].aw.addr; + assign dbg_idmad64_be_aw_len = slv_req[2].aw.len; + assign dbg_idmad64_be_w_valid = slv_req[2].w_valid; + assign dbg_idmad64_be_w_ready = slv_resp[2].w_ready; + assign dbg_idmad64_be_w_data = slv_req[2].w.data; + assign dbg_idmad64_be_w_strb = slv_req[2].w.strb; + assign dbg_idmad64_be_b_valid = slv_resp[2].b_valid; + assign dbg_idmad64_be_b_ready = slv_req[2].b_ready; + + if (SOC_P.AXI_IDMA_SUPPORTED) begin : gen_desc64_dbg + assign dbg_idmad64_input_addr_valid = + idma_i.gen_desc64.desc64_i.input_addr_valid; + assign dbg_idmad64_input_addr_ready = + idma_i.gen_desc64.desc64_i.input_addr_ready; + assign dbg_idmad64_input_addr = + idma_i.gen_desc64.desc64_i.input_addr; + assign dbg_idmad64_queued_addr_valid = + idma_i.gen_desc64.desc64_i.queued_addr_valid; + assign dbg_idmad64_queued_addr_ready = + idma_i.gen_desc64.desc64_i.queued_addr_ready; + assign dbg_idmad64_queued_addr = + idma_i.gen_desc64.desc64_i.queued_addr; + assign dbg_idmad64_idma_req_valid = + idma_i.gen_desc64.desc64_i.idma_req_valid_o; + assign dbg_idmad64_idma_req_ready = + idma_i.gen_desc64.desc64_i.idma_req_ready_i; + assign dbg_idmad64_idma_rsp_valid = + idma_i.gen_desc64.desc64_i.idma_rsp_valid_i; + assign dbg_idmad64_idma_rsp_ready = + idma_i.gen_desc64.desc64_i.idma_rsp_ready_o; + assign dbg_idmad64_do_irq = + idma_i.gen_desc64.desc64_i.do_irq; + assign dbg_idmad64_do_irq_valid = + idma_i.gen_desc64.desc64_i.do_irq_valid; + assign dbg_idmad64_do_irq_ready = + idma_i.gen_desc64.desc64_i.do_irq_ready; + assign dbg_idmad64_do_irq_out = + idma_i.gen_desc64.desc64_i.do_irq_out; + end else begin : gen_no_desc64_dbg + assign dbg_idmad64_input_addr_valid = 1'b0; + assign dbg_idmad64_input_addr_ready = 1'b0; + assign dbg_idmad64_input_addr = '0; + assign dbg_idmad64_queued_addr_valid = 1'b0; + assign dbg_idmad64_queued_addr_ready = 1'b0; + assign dbg_idmad64_queued_addr = '0; + assign dbg_idmad64_idma_req_valid = 1'b0; + assign dbg_idmad64_idma_req_ready = 1'b0; + assign dbg_idmad64_idma_rsp_valid = 1'b0; + assign dbg_idmad64_idma_rsp_ready = 1'b0; + assign dbg_idmad64_do_irq = 1'b0; + assign dbg_idmad64_do_irq_valid = 1'b0; + assign dbg_idmad64_do_irq_ready = 1'b0; + assign dbg_idmad64_do_irq_out = 1'b0; + end + + end else begin : gen_no_idma + assign slv_req[1] = '0; + assign slv_req[2] = '0; + assign idma_slv_resp = '0; + assign AXI_IDMAIntr = 1'b0; + assign dbg_idmar64_irq_pending = 1'b0; + assign dbg_idmar64_irq_enable = 1'b0; + assign dbg_idmar64_irq_clear_wr = 1'b0; + assign dbg_idmar64_irq_enable_wr = 1'b0; + assign dbg_idmar64_sel_irq_status = 1'b0; + assign dbg_idmar64_sel_irq_enable = 1'b0; + assign dbg_idmar64_sel_irq = 1'b0; + assign dbg_idmar64_axi_aw_valid = 1'b0; + assign dbg_idmar64_axi_aw_ready = 1'b0; + assign dbg_idmar64_axi_aw_addr = '0; + assign dbg_idmar64_axi_w_valid = 1'b0; + assign dbg_idmar64_axi_w_ready = 1'b0; + assign dbg_idmar64_axi_w_data = '0; + assign dbg_idmar64_axi_w_strb = '0; + assign dbg_idmar64_axi_b_valid = 1'b0; + assign dbg_idmar64_axi_b_ready = 1'b0; + assign dbg_idmar64_axi_b_resp = '0; + assign dbg_idmar64_reg_req_valid = 1'b0; + assign dbg_idmar64_reg_req_write = 1'b0; + assign dbg_idmar64_reg_req_addr = '0; + assign dbg_idmar64_reg_req_wdata = '0; + assign dbg_idmar64_reg_req_wstrb = '0; + assign dbg_idmar64_reg_rsp_ready = 1'b0; + assign dbg_idmar64_reg_rsp_error = 1'b0; + assign dbg_idmar64_reg_rsp_rdata = '0; + assign dbg_idmar64_idma_reg_req_valid = 1'b0; + assign dbg_idmar64_idma_reg_req_write = 1'b0; + assign dbg_idmar64_idma_reg_req_addr = '0; + assign dbg_idmar64_idma_reg_req_wdata = '0; + assign dbg_idmar64_idma_reg_req_wstrb = '0; + assign dbg_idmar64_idma_reg_rsp_ready = 1'b0; + assign dbg_idmar64_idma_reg_rsp_error = 1'b0; + assign dbg_idmar64_idma_reg_rsp_rdata = '0; + assign dbg_idmad64_irq = 1'b0; + assign dbg_idmad64_irq_pending = 1'b0; + assign dbg_idmad64_irq_enable = 1'b0; + assign dbg_idmad64_irq_clear_wr = 1'b0; + assign dbg_idmad64_irq_enable_wr = 1'b0; + assign dbg_idmad64_mmio_aw_valid = 1'b0; + assign dbg_idmad64_mmio_aw_ready = 1'b0; + assign dbg_idmad64_mmio_aw_addr = '0; + assign dbg_idmad64_mmio_w_valid = 1'b0; + assign dbg_idmad64_mmio_w_ready = 1'b0; + assign dbg_idmad64_mmio_w_data = '0; + assign dbg_idmad64_mmio_w_strb = '0; + assign dbg_idmad64_mmio_b_valid = 1'b0; + assign dbg_idmad64_mmio_b_ready = 1'b0; + assign dbg_idmad64_mmio_b_resp = '0; + assign dbg_idmad64_mmio_ar_valid = 1'b0; + assign dbg_idmad64_mmio_ar_ready = 1'b0; + assign dbg_idmad64_mmio_ar_addr = '0; + assign dbg_idmad64_mmio_r_valid = 1'b0; + assign dbg_idmad64_mmio_r_ready = 1'b0; + assign dbg_idmad64_mmio_r_data = '0; + assign dbg_idmad64_mmio_r_resp = '0; + assign dbg_idmad64_desc_ar_valid = 1'b0; + assign dbg_idmad64_desc_ar_ready = 1'b0; + assign dbg_idmad64_desc_ar_addr = '0; + assign dbg_idmad64_desc_ar_len = '0; + assign dbg_idmad64_desc_r_valid = 1'b0; + assign dbg_idmad64_desc_r_ready = 1'b0; + assign dbg_idmad64_desc_r_data = '0; + assign dbg_idmad64_desc_r_last = 1'b0; + assign dbg_idmad64_desc_aw_valid = 1'b0; + assign dbg_idmad64_desc_aw_ready = 1'b0; + assign dbg_idmad64_desc_aw_addr = '0; + assign dbg_idmad64_desc_w_valid = 1'b0; + assign dbg_idmad64_desc_w_ready = 1'b0; + assign dbg_idmad64_desc_w_data = '0; + assign dbg_idmad64_desc_w_strb = '0; + assign dbg_idmad64_desc_b_valid = 1'b0; + assign dbg_idmad64_desc_b_ready = 1'b0; + assign dbg_idmad64_be_ar_valid = 1'b0; + assign dbg_idmad64_be_ar_ready = 1'b0; + assign dbg_idmad64_be_ar_addr = '0; + assign dbg_idmad64_be_ar_len = '0; + assign dbg_idmad64_be_r_valid = 1'b0; + assign dbg_idmad64_be_r_ready = 1'b0; + assign dbg_idmad64_be_r_data = '0; + assign dbg_idmad64_be_r_last = 1'b0; + assign dbg_idmad64_be_aw_valid = 1'b0; + assign dbg_idmad64_be_aw_ready = 1'b0; + assign dbg_idmad64_be_aw_addr = '0; + assign dbg_idmad64_be_aw_len = '0; + assign dbg_idmad64_be_w_valid = 1'b0; + assign dbg_idmad64_be_w_ready = 1'b0; + assign dbg_idmad64_be_w_data = '0; + assign dbg_idmad64_be_w_strb = '0; + assign dbg_idmad64_be_b_valid = 1'b0; + assign dbg_idmad64_be_b_ready = 1'b0; + assign dbg_idmad64_input_addr_valid = 1'b0; + assign dbg_idmad64_input_addr_ready = 1'b0; + assign dbg_idmad64_input_addr = '0; + assign dbg_idmad64_queued_addr_valid = 1'b0; + assign dbg_idmad64_queued_addr_ready = 1'b0; + assign dbg_idmad64_queued_addr = '0; + assign dbg_idmad64_idma_req_valid = 1'b0; + assign dbg_idmad64_idma_req_ready = 1'b0; + assign dbg_idmad64_idma_rsp_valid = 1'b0; + assign dbg_idmad64_idma_rsp_ready = 1'b0; + assign dbg_idmad64_do_irq = 1'b0; + assign dbg_idmad64_do_irq_valid = 1'b0; + assign dbg_idmad64_do_irq_ready = 1'b0; + assign dbg_idmad64_do_irq_out = 1'b0; + end axi_xbar #( .Cfg (XBAR_CFG), @@ -1448,7 +1855,7 @@ module testbench_cvwsoc #( $display("Loaded boot ROM hex from %s", bootrom_memh); end - if (P.UNCORE_RAM_SUPPORTED) begin + if (SOC_P.UNCORE_RAM_SUPPORTED) begin if (uncore_ram_memh.len() != 0) begin $readmemh(uncore_ram_memh, soc.uncoregen.uncore.ram.ram.memory.ram.RAM, @@ -1601,7 +2008,7 @@ module testbench_cvwsoc #( // Mirror the internal UART character stream into a log file. This keeps the // bridge-era debug flow intact while allowing lightweight scripted input. - if (P.UART_SUPPORTED) begin : uart_logger + if (SOC_P.UART_SUPPORTED) begin : uart_logger string uart_char_str; string uart_prefix_str; string uart_wallclock_str;