RISC-V compilation target: Tenstorrent hardware acceleration for FHE

[Pattermesh]

Proposal

Investigate Tenstorrent's open-source RISC-V + AI accelerator ecosystem as a hardware acceleration backend for FHE operations.

Why

• Tenstorrent Blackhole: 120 Tensix cores, 664 TFLOPS matrix compute, 180MB SRAM
• FHE bootstrapping bottleneck = polynomial multiplication = structured matrix ops = what Tensix does
• RISC-V scalar crypto extensions (Zkn/Zks) provide hardware AES, SHA-2/3
• This repo already has Rust bindings started (bindings/rust/build.rs)
• No one has built FHE acceleration on Tenstorrent — first mover opportunity

Roadmap

1. Map TFHE/BGV/BFV operations to Tensix matrix engine capabilities
2. Write TT-Metalium kernels for NTT/iNTT
3. Extend Rust bindings with optional --features tenstorrent backend
4. Benchmark against GPU FHE implementations

References

• tenstorrent/tt-metal — low-level kernel programming
• tenstorrent/riscv-ocelot — open RV64GC core
• tenstorrent/whisper — RISC-V ISS with crypto extensions