perf(cpu/matmul): Q8_0 outer-product GEMM via AVX2 VNNI (VPDPBUSD-256) — unblock #61 register pressure

[jamesburton]

Summary

Implement the Q8_0 outer-product GEMM kernel using AVX2 VNNI (AvxVnni.MultiplyWideningAndAdd → VPDPBUSD-256), completing the Q8_0 half of ROADMAP Phase 3 Step 26 (the F32 half is #312 / PR #315).

Background

PR #61 landed the Q8_0 outer-product family but left it register-pressure-bound: the AVX2 microkernel holds only 3 live accumulators (one weight row at a time) to stay under the 16-YMM ceiling, because the s8×s8 reduction needs a maddubs + madd(ones) pair plus a ones mask and a prod temporary.

AVX2 VNNI (AvxVnni, shipped since .NET 5) fuses multiply + widen + accumulate into a single VPDPBUSD, eliminating the ones register and the prod temporary. That lifts safe accumulator residency from 3 → 6 rows and clears the ~23-YMM problem that blocked #61's dispatch.

Scope

• OuterProductQ8_0Vnni_4x3 in src/DotLLM.Cpu/Kernels/MatMul.cs: acc = AvxVnni.MultiplyWideningAndAdd(Vector256<int>.Zero, absX.AsByte(), adjW), replacing the AVX2 integer-reduction pair. Same 4-row × 3-token output tile, abs/sign idiom and per-block dw·dx float fold preserved → bit-identical per cell to the AVX2 path (same FMA order).
• Dispatch: VNNI branch ahead of AVX2 in OuterProductGemmQ8_0 (single-threaded) + OuterProductGemmQ8_0Worker (parallel); not taken on AVX512BW CPUs (they keep the 4×6 AVX512 path) — targets AVX2+VNNI-without-AVX512.
• Register budget: 4-row R4 group processed as two 2-row sub-passes → 6 float acc + 3 token vectors + ~4-5 transients ≈ 13-14 YMM ≤ 16.

Acceptance criteria

• VNNI microkernel parity vs scalar reference (bit-exact) and vs AVX2, over multi-block K.
• GEMM-dispatch parity over discriminating shapes (full tile, multi-block K, row+token tails, large 128×32) — not degenerate shapes (per the cross-backend testing rule).
• Self-checking discrimination test (deliberate cell perturbation rejected). Verified: a tile bug fails 22/22; clean = 75/75 pass.
• Dispatch into public GemmQ8_0 — deferred. The Q8_0 outer-product family requires R4-repacked weights and currently has no production callers; the public GemmQ8_0 (n>1) path routes row-major weights through ComputeGemmTiled. Wiring needs a per-call full-matrix R4 repack (architecturally significant) — tracked separately, mirrors the deferred F32 caller-wiring in kernels(cpu)(matmul): F32 outer-product tiled GEMM kernel for prefill (ROADMAP Phase 3 Step 26) #312/kernels(cpu)(matmul): F32 outer-product tiled GEMM kernel for prefill #315.
• Benchmark (V256-VNNI vs AVX2 vs Step 26: Outer-product tiled matmul — kernels + investigation (blocked on AVX2) #61 baseline) on a VNNI-capable CPU — pending a long-running session.

References

• kernels(cpu)(matmul): F32 outer-product tiled GEMM kernel for prefill (ROADMAP Phase 3 Step 26) #312 / PR kernels(cpu)(matmul): F32 outer-product tiled GEMM kernel for prefill #315 — F32 outer-product kernel (this stacks on it)
• PR Step 26: Outer-product tiled matmul — kernels + investigation (blocked on AVX2) #61 — original Q8_0 outer-product family (register-pressure-bound)
• ROADMAP Phase 3 Step 26
• llama.cpp ggml-cpu VNNI int8 path (mul_sum_i8_pairs) — authoritative semantics