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**PTP Lab Clock Simulator and Process Bus Timing Monitor for IEC 61850 lab work.**
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**Process Bus Timing Lab: a Windows PTP lab simulator and timing-health monitor for IEC 61850 FAT, SAT, analyzer validation, and Process Bus troubleshooting.**
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Process Bus Timing Lab is a Windows-friendly **PTPv2 Layer-2 lab simulator**, **IEC 61850 Process Bus timing visibility tool**, and **passive PTP health monitor**for FAT, SAT, commissioning preparation, analyzer validation, VLAN/QinQ verification, and controlled timing-fault scenarios.
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Process Bus Timing Lab helps substation automation engineers see whether PTPv2 Layer-2 timing traffic is visible, decodable, VLAN/QinQ-aware, and healthy enough for lab discussion before SV and GOOSE testing becomes guesswork.
> **Safety boundary:** this project is a lab simulator and diagnostic companion. It is **not** a certified PTP grandmaster, GPS clock, hardware-timestamped timing source, relay-acceptance reference, or replacement for IEC/IEEE 61850-9-3 compliant timing equipment.
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Substation automation engineers often need to know whether the test network actually carries usable PTP traffic before troubleshooting Sampled Values, GOOSE, or protection relay behavior. This project helps answer practical questions quickly:
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## Product screenshot
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- “Can Wireshark or my analyzer see PTP on this NIC?”
- “Is this process-bus VLAN carrying visible PTP traffic?”
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- “Can I reproduce GM-lost, missing-Follow_Up, sequence-jump, or degraded-clock symptoms?”
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- “Can I export a short PDF/ZIP evidence package for engineering discussion?”
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> Add the supplied dashboard screenshot as `docs/assets/ptp-lab-dashboard.png` to show the real WPF workspace on GitHub and GitHub Pages.
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> **Safety boundary:** this project is a lab simulator and diagnostic companion. It is **not** a certified timing source, GPS grandmaster, hardware-timestamped clock, or relay-acceptance timing reference.
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## Best-fit use cases
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*The dashboard combines Clock Profile setup, Live Timing Flow counters, Scenario Player actions, VLAN settings, RAW self-test, and Timing Health diagnostics in one compact engineering workspace.*
- Npcap / SharpPcap RAW NIC smoke testing on Windows.
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- FAT/SAT preparation and issue evidence export.
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## Why this tool exists
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## Highlights
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In real Process Bus work, a relay, analyzer, or SV injector problem is often diagnosed too late because the timing layer is treated as invisible background infrastructure. Process Bus Timing Lab gives engineers a practical timing workspace for early-stage lab validation:
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- WPF dashboard with Demo Mode fallback.
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- Console tool for adapter listing, protocol validation, RAW self-test, passive monitor, health monitor, and evidence export.
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- PTPv2 Layer-2 serializer for Announce, Sync, Follow_Up, Pdelay_Req, Pdelay_Resp, and Pdelay_Resp_Follow_Up.
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- Untagged, VLAN, and QinQ Ethernet frame builders.
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- SharpPcap/Npcap RAW transport isolated behind a dedicated project.
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- VLAN-aware capture filter for untagged, VLAN, and QinQ PTP.
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- Passive monitor grouped by domain and source clock identity.
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- Timing-health validator with explainable PASS/WARN/FAIL checks.
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- PDF report and ZIP session evidence export.
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- xUnit protocol regression tests and GitHub Actions CI.
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- Apache-2.0 license.
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- Confirm whether PTP traffic is visible on the selected NIC.
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- Validate analyzer decoding for Announce, Sync, Follow_Up, and Pdelay messages.
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- Exercise untagged, VLAN-tagged, and QinQ PTP frame paths.
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- Trigger controlled timing symptoms such as GM lost, missing Follow_Up, sequence jump, degraded clock, and stopped Pdelay.
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- Export evidence packages for FAT/SAT notes, analyzer validation, and engineering discussion.
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## Portable release packages
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## Core capabilities
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Release automation produces direct self-contained Windows single-file EXE artifacts:
This project does not provide hardware timestamping, clock servo discipline, BMCA-complete grandmaster behavior, conformance certification, or relay-acceptance timing guarantees. Use certified PTP grandmaster equipment for protection, metering, and final commissioning workflows.
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