A simple 32-bit 5-stage RISC-V processor in SystemVerilog based on the book Computer Organization and Design by Patterson & Hennesy. Inspired by https://github.com/masoud-ata/PH-RISC-V
The list of commands that are (to be) implemented:
A simple 32-bit 5-stage RISC-V processor in SystemVerilog based on the book Computer Organization and Design by Patterson & Hennesy. Inspired by https://github.com/masoud-ata/PH-RISC-V
The list of commands that are (to be) implemented: