Q: Verilog Spec "not" Gate Type

[MarceloDanigno]

(This might be more related to naja-verilog than naja/najaeda itself.)

Hi Christophe! 👋

Me and some colleagues are using najaeda for some experiments, in which we extract features from instances in a design. Our input benchmarks are unmapped structural verilog (so with and, nand, not, buf, xor, xnor master cells).

One thing we do is a breath-first search of the whole netlist, starting from input ports. Things run perfectly until we reach inverters (not) or buffers (buf). The direction data seems to not be set (or not match), thus ending our search prematurely. I did look briefly into the spec and it seems that not and buf are multi-output, single-input master cells. From digging into the repo a bit, it seems that naja already supports this (on nl/NLDB0?).

What would be the correct way to travel through the netlist based on pin direction? Or could it be another issue at hand? Below is a google colab notebook with a testcase:

https://colab.research.google.com/drive/1uKJQlq8Cnzyhq5EEX5oYP-7Yb4QP40BJ?usp=sharing

Thanks for the help! Marcelo.

[xtofalex]

Hi @MarceloDanigno , thanks a lot for reporting this. This is clearly a bug.
Thanks for reporting the bug with codecollab !
I've opened #265 to follow up on this.
Hopefully should be quickly fixed.

[MarceloDanigno]

Got it. Thanks for the support!