From fd78db51ea85443a9daaf1b7693226423c976cc0 Mon Sep 17 00:00:00 2001
From: robert-binarylabs <114159685+robert-binarylabs@users.noreply.github.com>
Date: Tue, 22 Aug 2023 14:25:41 +0200
Subject: [PATCH] only start when ready

---
 Verilog/source/SPI_Master.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Verilog/source/SPI_Master.v b/Verilog/source/SPI_Master.v
index d03e7d1..d957497 100644
--- a/Verilog/source/SPI_Master.v
+++ b/Verilog/source/SPI_Master.v
@@ -101,7 +101,7 @@ module SPI_Master
       r_Leading_Edge  <= 1'b0;
       r_Trailing_Edge <= 1'b0;
       
-      if (i_TX_DV)
+      if (i_TX_DV && o_TX_Ready)
       begin
         o_TX_Ready      <= 1'b0;
         r_SPI_Clk_Edges <= 16;  // Total # edges in one byte ALWAYS 16