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defines.v
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// Copyright 2015 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the “License”); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// ============================================================================= //
// Company: Multitherman Laboratory @ DEIS - University of Bologna //
// Viale Risorgimento 2 40136 //
// Bologna - fax 0512093785 - //
// //
// Engineer: Igor Loi - igor.loi@unibo.it //
// //
// //
// Additional contributions by: //
// //
// //
// //
// Create Date: 18/11/2014 //
// Design Name: AXI 4 INTERCONNECT //
// Module Name: none //
// Project Name: PULP //
// Language: SystemVerilog //
// //
// Description: axi_node defines and macros //
// //
// //
// Revision: //
// Revision v0.1 - 18/11/2014 : File Created //
// //
// //
// //
// //
// //
// //
// ============================================================================= //
`define OKAY 2'b00
`define EXOKAY 2'b01
`define SLVERR 2'b10
`define DECERR 2'b11
//`define USE_CFG_BLOCK
//`define USE_APB