diff --git a/SPECS/linux-lts-kmhv2/0001-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch b/SPECS/linux-lts-kmhv2/0001-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch deleted file mode 100644 index 5a3619f868..0000000000 --- a/SPECS/linux-lts-kmhv2/0001-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch +++ /dev/null @@ -1,65 +0,0 @@ -From fc295beff7031f45a9ab9984a426817f27ed21fe Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 28 May 2026 14:18:23 +0800 -Subject: [PATCH] RUYI: mmc: sdhci-of-dwcmshc: Add support for SG2042 FPGA - variant - -Add support for a testing variant of the SG2042 SDHCI controller without -PHY reset and without the "timer" clock. - -[ Vivian: Adjust context for 6.18 ] -Signed-off-by: Vivian Wang ---- - drivers/mmc/host/sdhci-of-dwcmshc.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c -index 5b7ffc359414..9f3482b2a311 100644 ---- a/drivers/mmc/host/sdhci-of-dwcmshc.c -+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c -@@ -1194,6 +1194,16 @@ static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { - .platform_execute_tuning = th1520_execute_tuning, - }; - -+static const struct sdhci_ops sdhci_dwcmshc_sg2042_fpga_ops = { -+ .set_clock = sdhci_set_clock, -+ .set_bus_width = sdhci_set_bus_width, -+ .set_uhs_signaling = dwcmshc_set_uhs_signaling, -+ .get_max_clock = dwcmshc_get_max_clock, -+ .reset = sdhci_reset, -+ .adma_write_desc = dwcmshc_adma_write_desc, -+ .platform_execute_tuning = th1520_execute_tuning, -+}; -+ - static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = { - .pdata = { - .ops = &sdhci_dwcmshc_ops, -@@ -1263,6 +1273,14 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { - .init = sg2042_init, - }; - -+static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_fpga_pdata = { -+ .pdata = { -+ .ops = &sdhci_dwcmshc_sg2042_fpga_ops, -+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, -+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, -+ }, -+}; -+ - static const struct cqhci_host_ops dwcmshc_cqhci_ops = { - .enable = dwcmshc_sdhci_cqe_enable, - .disable = sdhci_cqe_disable, -@@ -1363,6 +1381,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { - .compatible = "sophgo,sg2042-dwcmshc", - .data = &sdhci_dwcmshc_sg2042_pdata, - }, -+ { -+ .compatible = "sophgo,sg2042-fpga-dwcmshc", -+ .data = &sdhci_dwcmshc_sg2042_fpga_pdata, -+ }, - {}, - }; - MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); --- -2.54.0 - diff --git a/SPECS/linux-lts-kmhv2/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch b/SPECS/linux-lts-kmhv2/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch index 5a44481abf..dd82e46153 100644 --- a/SPECS/linux-lts-kmhv2/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch +++ b/SPECS/linux-lts-kmhv2/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch @@ -1,7 +1,7 @@ -From 68f4d24c96b911ab659b964add869d541d519b43 Mon Sep 17 00:00:00 2001 +From e8197b44ac58d76565180793e59b2ff39d0ff8a1 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 5 Dec 2025 10:42:07 +0800 -Subject: [PATCH 001/467] UPSTREAM: drm/ttm: add pgprot handling for RISC-V +Subject: [RUYI PATCH] UPSTREAM: drm/ttm: add pgprot handling for RISC-V MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0001-XIANGSHAN-Flush-all-tlb-in-set_pte.patch b/SPECS/linux-lts-kmhv2/0001-XIANGSHAN-Flush-all-tlb-in-set_pte.patch index 99340fe4e2..a8bd9c03dd 100644 --- a/SPECS/linux-lts-kmhv2/0001-XIANGSHAN-Flush-all-tlb-in-set_pte.patch +++ b/SPECS/linux-lts-kmhv2/0001-XIANGSHAN-Flush-all-tlb-in-set_pte.patch @@ -1,7 +1,7 @@ -From 7c072bb9e9f01429f8040ac7fc65086c052beb89 Mon Sep 17 00:00:00 2001 +From 8c1d176b72034e3df9780310de7c4ea43d72c9ed Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Fri, 20 Mar 2026 15:31:20 +0800 -Subject: [PATCH 1/3] XIANGSHAN: Flush all tlb in set_pte() +Subject: [RUYI PATCH] XIANGSHAN: Flush all tlb in set_pte() Signed-off-by: Ran Wang Signed-off-by: Han Gao diff --git a/SPECS/linux-lts-kmhv2/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch b/SPECS/linux-lts-kmhv2/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch index c7224a0b81..b8cb7f6ff0 100644 --- a/SPECS/linux-lts-kmhv2/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch +++ b/SPECS/linux-lts-kmhv2/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch @@ -1,8 +1,8 @@ -From a6570cc0fbc912cd59b63b6cc0e3dfb0e74e8d08 Mon Sep 17 00:00:00 2001 +From 172fa2e5a76c1351ea1bb6903e1d03944ce8a778 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:33:43 +0800 -Subject: [PATCH 002/467] UPSTREAM: riscv: sophgo: dts: add PCIe controllers - for SG2042 +Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: add PCIe controllers for + SG2042 Add PCIe controller nodes in DTS for Sophgo SG2042. Default they are disabled. diff --git a/SPECS/linux-lts-kmhv2/0002-XIANGSHAN-Add-two-sbi-calls.patch b/SPECS/linux-lts-kmhv2/0002-XIANGSHAN-Add-two-sbi-calls.patch index ea4bd70ae2..eb448a6a4e 100644 --- a/SPECS/linux-lts-kmhv2/0002-XIANGSHAN-Add-two-sbi-calls.patch +++ b/SPECS/linux-lts-kmhv2/0002-XIANGSHAN-Add-two-sbi-calls.patch @@ -1,7 +1,7 @@ -From eb55ca6799bbf38ce108fc237284f10f279a1da7 Mon Sep 17 00:00:00 2001 +From 72813582d41500d578c0d5b500c4224f33824e91 Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Fri, 20 Mar 2026 15:36:58 +0800 -Subject: [PATCH 2/3] XIANGSHAN: Add two sbi calls +Subject: [RUYI PATCH] XIANGSHAN: Add two sbi calls Signed-off-by: Ran Wang Signed-off-by: Han Gao diff --git a/SPECS/linux-lts-kmhv2/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch b/SPECS/linux-lts-kmhv2/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch index 7528086c94..43e4f49e7c 100644 --- a/SPECS/linux-lts-kmhv2/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch +++ b/SPECS/linux-lts-kmhv2/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch @@ -1,8 +1,7 @@ -From a2b3dccf02d815c4cbbaa8ea797f337204196c30 Mon Sep 17 00:00:00 2001 +From eb8e783adc4036ef80be48cfc8469b4be20fb577 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:34:05 +0800 -Subject: [PATCH 003/467] UPSTREAM: riscv: sophgo: dts: enable PCIe for - PioneerBox +Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: enable PCIe for PioneerBox Enable PCIe controllers for PioneerBox, which uses SG2042 SoC. diff --git a/SPECS/linux-lts-kmhv2/0003-XIANGSHAN-Add-workaround-to-retry-when-access-fault.patch b/SPECS/linux-lts-kmhv2/0003-XIANGSHAN-Add-workaround-to-retry-when-access-fault.patch index 9043b9f47c..1aee7a490c 100644 --- a/SPECS/linux-lts-kmhv2/0003-XIANGSHAN-Add-workaround-to-retry-when-access-fault.patch +++ b/SPECS/linux-lts-kmhv2/0003-XIANGSHAN-Add-workaround-to-retry-when-access-fault.patch @@ -1,7 +1,7 @@ -From 7601c632bcc8afe89b7f067eb31bec6b9ca6b2ca Mon Sep 17 00:00:00 2001 +From 221755ad22855e46ff06ad063bde801c81b4bb75 Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Fri, 20 Mar 2026 15:50:27 +0800 -Subject: [PATCH 3/3] XIANGSHAN: Add workaround to retry when access fault +Subject: [RUYI PATCH] XIANGSHAN: Add workaround to retry when access fault Signed-off-by: Ran Wang Signed-off-by: Han Gao diff --git a/SPECS/linux-lts-kmhv2/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch b/SPECS/linux-lts-kmhv2/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch index 4191eceda0..46b8b479dc 100644 --- a/SPECS/linux-lts-kmhv2/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch +++ b/SPECS/linux-lts-kmhv2/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch @@ -1,7 +1,7 @@ -From ea11e07b03ac17c6cc757dd58c1097140d35647f Mon Sep 17 00:00:00 2001 +From 97f3ca4bfb8cf08fc5f01da48adbd2e295d9bf62 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:39:22 +0800 -Subject: [PATCH 004/467] UPSTREAM: riscv: sophgo: dts: enable PCIe for +Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X Enable PCIe controllers for Sophgo SG2042_EVB_V1.X board, diff --git a/SPECS/linux-lts-kmhv2/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch b/SPECS/linux-lts-kmhv2/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch index fa69fdde31..118243db74 100644 --- a/SPECS/linux-lts-kmhv2/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch +++ b/SPECS/linux-lts-kmhv2/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch @@ -1,7 +1,7 @@ -From 85ca5757d41f28ceee07c296a8562fc8ee987444 Mon Sep 17 00:00:00 2001 +From adfc1b75ef3710cc675487e2d856fe811e92c9cf Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:40:09 +0800 -Subject: [PATCH 005/467] UPSTREAM: riscv: sophgo: dts: enable PCIe for +Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0 Enable PCIe controllers for Sophgo SG2042_EVB_V2.0 board, diff --git a/SPECS/linux-lts-kmhv2/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch b/SPECS/linux-lts-kmhv2/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch index 434e018363..0105843995 100644 --- a/SPECS/linux-lts-kmhv2/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch +++ b/SPECS/linux-lts-kmhv2/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch @@ -1,7 +1,7 @@ -From 6655e6812bc952f6ca617368b081df8ab2f94dc0 Mon Sep 17 00:00:00 2001 +From 0fe3f721fe45c7b4cfd9c65eaea2e94c7d05d05a Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:50 +0800 -Subject: [PATCH 006/467] UPSTREAM: riscv: dts: sophgo: Add SPI NOR node for +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Add SPI NOR node for SG2042 Add SPI NOR controller node for SG2042 diff --git a/SPECS/linux-lts-kmhv2/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch b/SPECS/linux-lts-kmhv2/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch index a2068d8a3f..e7d51ad4e9 100644 --- a/SPECS/linux-lts-kmhv2/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch +++ b/SPECS/linux-lts-kmhv2/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch @@ -1,7 +1,7 @@ -From 15e5a76787a30da2ef62756cfd195210851cf09f Mon Sep 17 00:00:00 2001 +From 9e5ebf3bb03d5951a1ac6273a557a7d3b42aaf5d Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:51 +0800 -Subject: [PATCH 007/467] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for PioneerBox Enable SPI NOR node for PioneerBox device tree diff --git a/SPECS/linux-lts-kmhv2/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch b/SPECS/linux-lts-kmhv2/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch index dea06361cb..0353c0d45c 100644 --- a/SPECS/linux-lts-kmhv2/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch +++ b/SPECS/linux-lts-kmhv2/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch @@ -1,7 +1,7 @@ -From d1a07634e134fcadea2caad89fcdcf622e23a136 Mon Sep 17 00:00:00 2001 +From ca6b4bc1ae282908399370569de96b507b11a199 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:52 +0800 -Subject: [PATCH 008/467] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1 Enable SPI NOR node for SG2042_EVB_V1 device tree diff --git a/SPECS/linux-lts-kmhv2/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch b/SPECS/linux-lts-kmhv2/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch index 9584149d3e..849dbb07fb 100644 --- a/SPECS/linux-lts-kmhv2/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch +++ b/SPECS/linux-lts-kmhv2/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch @@ -1,7 +1,7 @@ -From 53f32e5b4fe4b9f2bd8fecbf74e973f6b8c32c42 Mon Sep 17 00:00:00 2001 +From ef69ecb5f71cc9ec10bbe973e96dec13a22d83c5 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:53 +0800 -Subject: [PATCH 009/467] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2 Enable SPI NOR node for SG2042_EVB_V2 device tree diff --git a/SPECS/linux-lts-kmhv2/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch b/SPECS/linux-lts-kmhv2/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch index 176f1f72fa..f9aa138c7a 100644 --- a/SPECS/linux-lts-kmhv2/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch +++ b/SPECS/linux-lts-kmhv2/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch @@ -1,8 +1,8 @@ -From fa290cfeb4782f7d5f70c9bfc7c9a45a8d783bba Mon Sep 17 00:00:00 2001 +From 4cec01963100499caa46c4c97acb3d80549132f6 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Fri, 14 Nov 2025 08:38:03 +0800 -Subject: [PATCH 010/467] UPSTREAM: dt-bindings: net: sophgo,sg2044-dwmac: add - phy mode restriction +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: net: sophgo,sg2044-dwmac: add phy + mode restriction As the ethernet controller of SG2044 and SG2042 only supports RGMII phy. Add phy-mode property to restrict the value. diff --git a/SPECS/linux-lts-kmhv2/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch b/SPECS/linux-lts-kmhv2/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch index eab71a2128..d0b72dcb45 100644 --- a/SPECS/linux-lts-kmhv2/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch +++ b/SPECS/linux-lts-kmhv2/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch @@ -1,7 +1,7 @@ -From 5d275d4fdc0ad5140b356cbcb753365217315b31 Mon Sep 17 00:00:00 2001 +From 97f62d7522d266af5df939fe3f50a0e365d78d37 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 14 Oct 2025 09:48:29 +0800 -Subject: [PATCH 011/467] UPSTREAM: perf vendor events riscv: add T-HEAD C920V2 +Subject: [RUYI PATCH] UPSTREAM: perf vendor events riscv: add T-HEAD C920V2 JSON support T-HEAD C920 has a V2 iteration, which supports Sscompmf. The V2 diff --git a/SPECS/linux-lts-kmhv2/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch b/SPECS/linux-lts-kmhv2/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch index a79f509cec..de2b418bcf 100644 --- a/SPECS/linux-lts-kmhv2/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch +++ b/SPECS/linux-lts-kmhv2/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch @@ -1,8 +1,8 @@ -From 367f56da193fa8ee4a1896f1086d913d2ce34435 Mon Sep 17 00:00:00 2001 +From e140a5124e38afd1d68eb3c9da0a96a9bc0c1fd8 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:32 +0100 -Subject: [PATCH 012/467] UPSTREAM: rust: macros: Add support for 'imports_ns' - to module! +Subject: [RUYI PATCH] UPSTREAM: rust: macros: Add support for 'imports_ns' to + module! MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch b/SPECS/linux-lts-kmhv2/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch index 03d9743457..a4878efc8e 100644 --- a/SPECS/linux-lts-kmhv2/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch +++ b/SPECS/linux-lts-kmhv2/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch @@ -1,8 +1,7 @@ -From 21c80df86a56778bb86caf30236f44822c7c78ab Mon Sep 17 00:00:00 2001 +From 6eec5416f899b995199e6a78acdba366552fe74b Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:01 +0200 -Subject: [PATCH 013/467] UPSTREAM: pwm: Export `pwmchip_release` for external - use +Subject: [RUYI PATCH] UPSTREAM: pwm: Export `pwmchip_release` for external use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch b/SPECS/linux-lts-kmhv2/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch index 1bc49e3700..3a11557826 100644 --- a/SPECS/linux-lts-kmhv2/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch +++ b/SPECS/linux-lts-kmhv2/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch @@ -1,7 +1,7 @@ -From 7012d45ae8771935292a62a8dcaa765c6adb7f56 Mon Sep 17 00:00:00 2001 +From dc77d3e5fd4e58d58519c452e5ab3a3dc0d30352 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:02 +0200 -Subject: [PATCH 014/467] UPSTREAM: rust: pwm: Add Kconfig and basic data +Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Add Kconfig and basic data structures MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 diff --git a/SPECS/linux-lts-kmhv2/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch b/SPECS/linux-lts-kmhv2/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch index b977783a21..ae5c79af9d 100644 --- a/SPECS/linux-lts-kmhv2/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch +++ b/SPECS/linux-lts-kmhv2/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch @@ -1,7 +1,7 @@ -From df53f3655e6b9bf34d2b0af69746d7e7efcf5c82 Mon Sep 17 00:00:00 2001 +From fad4bc85d938d1fa411bfc7c09b2c327dc21cad2 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:03 +0200 -Subject: [PATCH 015/467] UPSTREAM: rust: pwm: Add complete abstraction layer +Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Add complete abstraction layer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch b/SPECS/linux-lts-kmhv2/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch index 40837d9bee..abdc4b8594 100644 --- a/SPECS/linux-lts-kmhv2/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch +++ b/SPECS/linux-lts-kmhv2/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch @@ -1,7 +1,7 @@ -From 5ad798527f4b4099b19ab390304846d618b490fb Mon Sep 17 00:00:00 2001 +From a8369a239ce03856b5d63e39d5c92586c0641c18 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:33 +0100 -Subject: [PATCH 016/467] UPSTREAM: rust: pwm: Add module_pwm_platform_driver! +Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Add module_pwm_platform_driver! macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 diff --git a/SPECS/linux-lts-kmhv2/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch b/SPECS/linux-lts-kmhv2/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch index 8a537db5b7..a2e4a4474c 100644 --- a/SPECS/linux-lts-kmhv2/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch +++ b/SPECS/linux-lts-kmhv2/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch @@ -1,8 +1,8 @@ -From 07a4233a04f77fea6255070d799f8158192c7896 Mon Sep 17 00:00:00 2001 +From 0bed1f7ddadef9191b85230b6f078bf48a1ddfc1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 25 Oct 2025 14:23:56 +0200 -Subject: [PATCH 017/467] UPSTREAM: rust: pwm: Drop wrapping of PWM polarity - and state +Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Drop wrapping of PWM polarity and + state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch b/SPECS/linux-lts-kmhv2/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch index 1bf1f84011..aaf7682aaf 100644 --- a/SPECS/linux-lts-kmhv2/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch +++ b/SPECS/linux-lts-kmhv2/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch @@ -1,7 +1,7 @@ -From 124a1875f86fff16688c63594e8e073464b6f4dd Mon Sep 17 00:00:00 2001 +From ce0cfe6521836f8d1bff1dbb1dd784f8dbe2f0f1 Mon Sep 17 00:00:00 2001 From: Miguel Ojeda Date: Wed, 29 Oct 2025 19:19:40 +0100 -Subject: [PATCH 018/467] UPSTREAM: rust: pwm: Fix broken intra-doc link +Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Fix broken intra-doc link MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch b/SPECS/linux-lts-kmhv2/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch index 6d68bf4ad8..4a1351eb60 100644 --- a/SPECS/linux-lts-kmhv2/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch +++ b/SPECS/linux-lts-kmhv2/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch @@ -1,7 +1,7 @@ -From 5c016dc78cc84fad38fbee81b56b42b02313be87 Mon Sep 17 00:00:00 2001 +From 323a18dcdb57c3c4a56d687fff097af3249b0fe3 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:04 +0200 -Subject: [PATCH 019/467] UPSTREAM: pwm: Add Rust driver for T-HEAD TH1520 SoC +Subject: [RUYI PATCH] UPSTREAM: pwm: Add Rust driver for T-HEAD TH1520 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch b/SPECS/linux-lts-kmhv2/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch index 7e8f6f69f9..72b7b6e552 100644 --- a/SPECS/linux-lts-kmhv2/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch +++ b/SPECS/linux-lts-kmhv2/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch @@ -1,8 +1,8 @@ -From 75682c170513cae6790cdc8c45c039ae28ac86a8 Mon Sep 17 00:00:00 2001 +From 1ff5f22be0212ca408aa7b7fb452742a1c0e44d8 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:05 +0200 -Subject: [PATCH 020/467] UPSTREAM: dt-bindings: pwm: thead: Add T-HEAD TH1520 - PWM controller +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pwm: thead: Add T-HEAD TH1520 PWM + controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch b/SPECS/linux-lts-kmhv2/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch index 2822d39394..b045d4a3cf 100644 --- a/SPECS/linux-lts-kmhv2/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch +++ b/SPECS/linux-lts-kmhv2/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch @@ -1,7 +1,7 @@ -From 16e23a75ada51fa0c1e922c0c532193c2465a324 Mon Sep 17 00:00:00 2001 +From d512570ff756b751d74f27121ccd6784be182855 Mon Sep 17 00:00:00 2001 From: Miguel Ojeda Date: Wed, 29 Oct 2025 19:25:02 +0100 -Subject: [PATCH 021/467] UPSTREAM: pwm: Fix Rust formatting +Subject: [RUYI PATCH] UPSTREAM: pwm: Fix Rust formatting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch b/SPECS/linux-lts-kmhv2/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch index e395108a1d..06d4f3cc31 100644 --- a/SPECS/linux-lts-kmhv2/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch +++ b/SPECS/linux-lts-kmhv2/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch @@ -1,8 +1,8 @@ -From 24db3f421ffa17c4b9c6a3a054c6cb6d164a3645 Mon Sep 17 00:00:00 2001 +From b8e48fd0e9516c83f6a6193730b5d042ed5263bd Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:35 +0100 -Subject: [PATCH 022/467] UPSTREAM: pwm: th1520: Fix clippy warning for - redundant struct field init +Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: Fix clippy warning for redundant + struct field init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch b/SPECS/linux-lts-kmhv2/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch index b5b15a3878..b4384ef364 100644 --- a/SPECS/linux-lts-kmhv2/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch +++ b/SPECS/linux-lts-kmhv2/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch @@ -1,8 +1,8 @@ -From 0e92472e39f3b94fbd120e69f625a2b4d5ade50d Mon Sep 17 00:00:00 2001 +From e4ad935868f5592d06155265261be5934f1821ec Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:34 +0100 -Subject: [PATCH 023/467] UPSTREAM: pwm: th1520: Use - module_pwm_platform_driver! macro +Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: Use module_pwm_platform_driver! + macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch b/SPECS/linux-lts-kmhv2/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch index 5f7489ce32..f01d4fe843 100644 --- a/SPECS/linux-lts-kmhv2/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch +++ b/SPECS/linux-lts-kmhv2/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch @@ -1,8 +1,7 @@ -From 0580c630050cf90e3e014a44e421a8876ab2c452 Mon Sep 17 00:00:00 2001 +From 04ac502626ab9c23c88cb52a8447f2a6d6871231 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 9 Dec 2025 21:06:03 +0100 -Subject: [PATCH 024/467] UPSTREAM: pwm: th1520: Fix missing Kconfig - dependencies +Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: Fix missing Kconfig dependencies MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch b/SPECS/linux-lts-kmhv2/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch index 7f73a0b809..4f6592382a 100644 --- a/SPECS/linux-lts-kmhv2/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch +++ b/SPECS/linux-lts-kmhv2/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch @@ -1,7 +1,7 @@ -From 95091d9394da630c87c6cfa3824b397f4eee2f73 Mon Sep 17 00:00:00 2001 +From c413ed4426b184f8cb2304ff2897825e2a215871 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 19 Sep 2025 04:44:47 +0800 -Subject: [PATCH 025/467] UPSTREAM: riscv: dts: thead: add xtheadvector to the +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add xtheadvector to the th1520 devicetree The th1520 support xtheadvector [1] so it can be included in the diff --git a/SPECS/linux-lts-kmhv2/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch b/SPECS/linux-lts-kmhv2/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch index c199f87111..645a855fa1 100644 --- a/SPECS/linux-lts-kmhv2/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch +++ b/SPECS/linux-lts-kmhv2/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch @@ -1,7 +1,7 @@ -From ce397038e6fdb45ea0afe6fc74d6710bb294ef61 Mon Sep 17 00:00:00 2001 +From d86f79c2f13ca9a4c232cce2f5dd5020f18a9656 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 19 Sep 2025 04:44:48 +0800 -Subject: [PATCH 026/467] UPSTREAM: riscv: dts: thead: add ziccrse for th1520 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add ziccrse for th1520 Existing rv64 hardware conforms to the rva20 profile. diff --git a/SPECS/linux-lts-kmhv2/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch b/SPECS/linux-lts-kmhv2/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch index 756d021b59..02c41e4add 100644 --- a/SPECS/linux-lts-kmhv2/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch +++ b/SPECS/linux-lts-kmhv2/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch @@ -1,7 +1,7 @@ -From bc00f9a0bbb6c14f199943da7ff9f30859dee923 Mon Sep 17 00:00:00 2001 +From 6c54c277dfd8b9c53a91aac3aa08d80a40eef35d Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 19 Sep 2025 04:44:49 +0800 -Subject: [PATCH 027/467] UPSTREAM: riscv: dts: thead: add zfh for th1520 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add zfh for th1520 th1520 support Zfh ISA extension. It supports the same RISC-V extensions as SG2042. diff --git a/SPECS/linux-lts-kmhv2/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch b/SPECS/linux-lts-kmhv2/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch index 6dc799bdb4..1da5ef41e5 100644 --- a/SPECS/linux-lts-kmhv2/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch +++ b/SPECS/linux-lts-kmhv2/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch @@ -1,7 +1,7 @@ -From ccee5be0d66e8a00cbb23864ba081c741a37e009 Mon Sep 17 00:00:00 2001 +From 3ca9f9c1f974516ed56055f86fe810e70234d2e0 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:06 +0200 -Subject: [PATCH 028/467] UPSTREAM: riscv: dts: thead: Add PWM controller node +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add PWM controller node Add the Device Tree node for the T-HEAD TH1520 SoC's PWM controller. diff --git a/SPECS/linux-lts-kmhv2/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch b/SPECS/linux-lts-kmhv2/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch index 4d0f44e4d2..16a6ff7a16 100644 --- a/SPECS/linux-lts-kmhv2/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch +++ b/SPECS/linux-lts-kmhv2/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch @@ -1,7 +1,7 @@ -From 6e4ddc5ab60b81304d73eac230c5c2d9b641f114 Mon Sep 17 00:00:00 2001 +From 34e6c9de17b9ff861746760bfc9334e3fc3060cb Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:07 +0200 -Subject: [PATCH 029/467] UPSTREAM: riscv: dts: thead: Add PWM fan and thermal +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add PWM fan and thermal control Add Device Tree nodes to enable a PWM controlled fan and it's associated diff --git a/SPECS/linux-lts-kmhv2/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch b/SPECS/linux-lts-kmhv2/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch index b61a71c164..073023bb11 100644 --- a/SPECS/linux-lts-kmhv2/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch +++ b/SPECS/linux-lts-kmhv2/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch @@ -1,7 +1,7 @@ -From 177d1708f10af38636c322a58f9e71637e3553b3 Mon Sep 17 00:00:00 2001 +From 185f8436e47e0844df0a0d25fbb995a69a565fd1 Mon Sep 17 00:00:00 2001 From: Lucas Zampieri Date: Fri, 24 Oct 2025 09:36:40 +0100 -Subject: [PATCH 030/467] UPSTREAM: dt-bindings: vendor-prefixes: Add UltraRISC +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: vendor-prefixes: Add UltraRISC Add vendor prefix for UltraRISC Technology Co., Ltd. diff --git a/SPECS/linux-lts-kmhv2/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch b/SPECS/linux-lts-kmhv2/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch index 6ba2aa9b16..a9e42fff55 100644 --- a/SPECS/linux-lts-kmhv2/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch +++ b/SPECS/linux-lts-kmhv2/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch @@ -1,7 +1,7 @@ -From 1cb2556af5d85298241d0bccaeab5658801c313a Mon Sep 17 00:00:00 2001 +From 38033dfbe309976053db7684228a93e90a76f54f Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Fri, 24 Oct 2025 09:36:41 +0100 -Subject: [PATCH 031/467] UPSTREAM: dt-bindings: interrupt-controller: Add +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: Add UltraRISC DP1000 PLIC Add compatible strings for the PLIC found in UltraRISC DP1000 SoC. diff --git a/SPECS/linux-lts-kmhv2/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch b/SPECS/linux-lts-kmhv2/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch index cd328f7134..c47e05232b 100644 --- a/SPECS/linux-lts-kmhv2/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch +++ b/SPECS/linux-lts-kmhv2/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch @@ -1,7 +1,7 @@ -From 58300649d94886f078c9ae5211d5e73fdb5d86dd Mon Sep 17 00:00:00 2001 +From 3f8b27c28b0516d4675130d799e52fe0e47cc190 Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Fri, 24 Oct 2025 09:36:42 +0100 -Subject: [PATCH 032/467] UPSTREAM: irqchip/sifive-plic: Cache the interrupt +Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Cache the interrupt enable state Optimize the PLIC driver by maintaining the interrupt enable state in the diff --git a/SPECS/linux-lts-kmhv2/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch b/SPECS/linux-lts-kmhv2/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch index 849bb391aa..35bf32dde3 100644 --- a/SPECS/linux-lts-kmhv2/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch +++ b/SPECS/linux-lts-kmhv2/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch @@ -1,8 +1,8 @@ -From 47ff9167559df87c4792972c083b403e13935fed Mon Sep 17 00:00:00 2001 +From 4ef8a6c6a0ad3046bd79c8e7ba68b55f65faba37 Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Fri, 24 Oct 2025 09:36:43 +0100 -Subject: [PATCH 033/467] UPSTREAM: irqchip/sifive-plic: Add support for - UltraRISC DP1000 PLIC +Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Add support for UltraRISC + DP1000 PLIC Add a new compatible for the plic found in UltraRISC DP1000 with a quirk to work around a known hardware bug with IRQ claiming in the UR-CP100 cores. diff --git a/SPECS/linux-lts-kmhv2/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch b/SPECS/linux-lts-kmhv2/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch index d396f1c218..d80cdc947a 100644 --- a/SPECS/linux-lts-kmhv2/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch +++ b/SPECS/linux-lts-kmhv2/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch @@ -1,8 +1,8 @@ -From 44af92527d4da6d483b4439b15fafb8133938613 Mon Sep 17 00:00:00 2001 +From 88d1fb14b13933d5016b00a18582e2c2dec28c29 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 2 Jan 2026 14:58:39 +0000 -Subject: [PATCH 034/467] UPSTREAM: riscv: cpu_ops_sbi: smp_processor_id() - returns int, not unsigned int +Subject: [RUYI PATCH] UPSTREAM: riscv: cpu_ops_sbi: smp_processor_id() returns + int, not unsigned int The print in sbi_cpu_stop() assumes smp_processor_id() returns an unsigned int, when it is actually an int. Fix the format string to diff --git a/SPECS/linux-lts-kmhv2/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch b/SPECS/linux-lts-kmhv2/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch index 5bf082acbe..8df22862a6 100644 --- a/SPECS/linux-lts-kmhv2/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch +++ b/SPECS/linux-lts-kmhv2/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch @@ -1,8 +1,8 @@ -From 5b142274eb87250e655c690bfa35b94fa0c7e37d Mon Sep 17 00:00:00 2001 +From b73688a2f1f8a16a7bb9609da304ebfd1dd7f968 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:29:59 -0500 -Subject: [PATCH 035/467] UPSTREAM: spi: dt-bindings: fsl-qspi: support - SpacemiT K1 +Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: support SpacemiT + K1 Add the SpacemiT K1 SoC QSPI IP to the list of supported hardware. This is the first non-Freescale device represented here. It has a nearly diff --git a/SPECS/linux-lts-kmhv2/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch b/SPECS/linux-lts-kmhv2/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch index df87b1b4de..398331aef3 100644 --- a/SPECS/linux-lts-kmhv2/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch +++ b/SPECS/linux-lts-kmhv2/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch @@ -1,7 +1,7 @@ -From 3ac3b07de446afd26f22edb65a08e995d1e10394 Mon Sep 17 00:00:00 2001 +From 10c6bee274527e1fa5cf933eade792a8269bfa6e Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:00 -0500 -Subject: [PATCH 036/467] UPSTREAM: spi: dt-bindings: fsl-qspi: add optional +Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: add optional resets Allow two resets to be defined to support the SpacemiT K1 SoC QSPI IP. diff --git a/SPECS/linux-lts-kmhv2/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch b/SPECS/linux-lts-kmhv2/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch index 8cf653eea4..cb7815d689 100644 --- a/SPECS/linux-lts-kmhv2/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch +++ b/SPECS/linux-lts-kmhv2/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch @@ -1,7 +1,7 @@ -From 2383a4b7bd0919af694b0148ac45bfa98b5c3e5e Mon Sep 17 00:00:00 2001 +From eef2e7554dce124c0d27d06663f545ebf8b06b4f Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:01 -0500 -Subject: [PATCH 037/467] UPSTREAM: spi: fsl-qspi: add optional reset support +Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: add optional reset support Add support for one or more optional exclusive resets. These simply need to be deasserted at probe time, and can remain that way for the life of the diff --git a/SPECS/linux-lts-kmhv2/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch b/SPECS/linux-lts-kmhv2/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch index 5790e35633..78d52fb913 100644 --- a/SPECS/linux-lts-kmhv2/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch +++ b/SPECS/linux-lts-kmhv2/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch @@ -1,7 +1,7 @@ -From 6c4d84191d4a646424af4fd8f0bfa0cb6a8b88a5 Mon Sep 17 00:00:00 2001 +From 01d5441431b796aa0c7bef71294e87584b3a7ac2 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:02 -0500 -Subject: [PATCH 038/467] UPSTREAM: spi: fsl-qspi: switch predicates to bool +Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: switch predicates to bool Change all the needs_*() functions so they are no longer inline, and return bool rather than int. diff --git a/SPECS/linux-lts-kmhv2/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch b/SPECS/linux-lts-kmhv2/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch index 2a0208b72d..2a381e6fb3 100644 --- a/SPECS/linux-lts-kmhv2/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch +++ b/SPECS/linux-lts-kmhv2/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch @@ -1,7 +1,7 @@ -From df1020f14b967f34e7183e2820998cf3ae06f448 Mon Sep 17 00:00:00 2001 +From 513e5c7ca8e7b4847c1a9fa9328ecc1da6e03ca4 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:03 -0500 -Subject: [PATCH 039/467] UPSTREAM: spi: fsl-qspi: add a clock disable quirk +Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: add a clock disable quirk The SpacemiT K1 SoC QSPI implementation needs to avoid shutting off the clock when changing its rate. Add a new quirk to indicate that disabling diff --git a/SPECS/linux-lts-kmhv2/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch b/SPECS/linux-lts-kmhv2/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch index 25af899158..c71778c496 100644 --- a/SPECS/linux-lts-kmhv2/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch +++ b/SPECS/linux-lts-kmhv2/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch @@ -1,8 +1,7 @@ -From 5ee33dac7a10929555229bc766263ba35d9f130b Mon Sep 17 00:00:00 2001 +From a5d94c358a562e2cf863fff92b78f0ee109abf10 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:04 -0500 -Subject: [PATCH 040/467] UPSTREAM: spi: fsl-qspi: introduce sfa_size devtype - data +Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: introduce sfa_size devtype data In fsl_qspi_default_setup(), four registers define the size of blocks of data to written to each of four chips that comprise SPI NOR flash storage. diff --git a/SPECS/linux-lts-kmhv2/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch b/SPECS/linux-lts-kmhv2/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch index 2b3039720f..f9a55c89ea 100644 --- a/SPECS/linux-lts-kmhv2/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch +++ b/SPECS/linux-lts-kmhv2/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch @@ -1,7 +1,7 @@ -From a8bec413546fceae68a0a397e5a6838e88544773 Mon Sep 17 00:00:00 2001 +From 014a6255ae46191c6eae14aa9de40535b4226ff0 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:05 -0500 -Subject: [PATCH 041/467] UPSTREAM: spi: fsl-qspi: support the SpacemiT K1 SoC +Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: support the SpacemiT K1 SoC Allow the SPI_FSL_QUADSPI Kconfig option to be selected if ARCH_SPACEMIT enabled. diff --git a/SPECS/linux-lts-kmhv2/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch b/SPECS/linux-lts-kmhv2/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch index 6059a178c4..8ad45c9e57 100644 --- a/SPECS/linux-lts-kmhv2/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch +++ b/SPECS/linux-lts-kmhv2/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch @@ -1,7 +1,7 @@ -From da811b95eb6cac6d2befd327921dfa943928d913 Mon Sep 17 00:00:00 2001 +From 0d6c9d0a071fcea507cb2b62195d329fbfd4e3fa Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 13 Nov 2025 15:45:35 -0600 -Subject: [PATCH 042/467] UPSTREAM: dt-bindings: pci: spacemit: Introduce PCIe +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pci: spacemit: Introduce PCIe host controller Add the Devicetree binding for the PCIe Root Complex found on the SpacemiT diff --git a/SPECS/linux-lts-kmhv2/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch b/SPECS/linux-lts-kmhv2/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch index c6df251f89..15f880c23c 100644 --- a/SPECS/linux-lts-kmhv2/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch +++ b/SPECS/linux-lts-kmhv2/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch @@ -1,8 +1,7 @@ -From 2cd4c603d19ce303b9a474892adb6f0982e1a630 Mon Sep 17 00:00:00 2001 +From e886894eecb01fde7c6d687a520c00f8f8c6577b Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 13 Nov 2025 15:45:37 -0600 -Subject: [PATCH 043/467] UPSTREAM: PCI: spacemit: Add SpacemiT PCIe host - driver +Subject: [RUYI PATCH] UPSTREAM: PCI: spacemit: Add SpacemiT PCIe host driver Introduce a driver for the PCIe host controller found in the SpacemiT K1 SoC. The hardware is derived from the Synopsys DesignWare PCIe IP. The diff --git a/SPECS/linux-lts-kmhv2/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch b/SPECS/linux-lts-kmhv2/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch index 1485b4db34..9f87089128 100644 --- a/SPECS/linux-lts-kmhv2/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch +++ b/SPECS/linux-lts-kmhv2/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch @@ -1,8 +1,8 @@ -From 13a1831ca9975f970aa93217ef8f0d78be839558 Mon Sep 17 00:00:00 2001 +From dd167e5e356efc521fea95cca3dab9214d112f2f Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 17 Oct 2025 11:16:17 +0800 -Subject: [PATCH 044/467] UPSTREAM: ASoC: dt-bindings: Add bindings for - SpacemiT K1 +Subject: [RUYI PATCH] UPSTREAM: ASoC: dt-bindings: Add bindings for SpacemiT + K1 Add dt-binding for the i2s driver of SpacemiT's K1 SoC. diff --git a/SPECS/linux-lts-kmhv2/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch b/SPECS/linux-lts-kmhv2/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch index 7ac964a344..79edb29c56 100644 --- a/SPECS/linux-lts-kmhv2/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch +++ b/SPECS/linux-lts-kmhv2/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch @@ -1,7 +1,7 @@ -From 80ddb8319d498df366ee69857ac128f3a759fa09 Mon Sep 17 00:00:00 2001 +From f80e4dd0f340bda7a0c1d1cbcb59d4a346aa00dd Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 17 Oct 2025 11:16:18 +0800 -Subject: [PATCH 045/467] UPSTREAM: ASoC: spacemit: add i2s support for K1 SoC +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: add i2s support for K1 SoC Add ASoC platform driver for the SpacemiT K1 SoC full-duplex I2S controller. diff --git a/SPECS/linux-lts-kmhv2/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch b/SPECS/linux-lts-kmhv2/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch index 9821983f58..0efa4da8f2 100644 --- a/SPECS/linux-lts-kmhv2/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch +++ b/SPECS/linux-lts-kmhv2/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch @@ -1,7 +1,7 @@ -From f28219b541a910d335af7fc7097a19a6e07b8712 Mon Sep 17 00:00:00 2001 +From affb820dfce75897605fbf89105fc1537a97d75b Mon Sep 17 00:00:00 2001 From: Hendrik Hamerlinck Date: Wed, 17 Sep 2025 08:59:07 +0200 -Subject: [PATCH 046/467] UPSTREAM: riscv: dts: spacemit: add UART pinctrl +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add UART pinctrl combinations Add UART pinctrl configurations based on the SoC datasheet and the diff --git a/SPECS/linux-lts-kmhv2/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch b/SPECS/linux-lts-kmhv2/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch index 548745b649..0351d09704 100644 --- a/SPECS/linux-lts-kmhv2/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch +++ b/SPECS/linux-lts-kmhv2/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch @@ -1,8 +1,7 @@ -From 3f8785742d64517f721a7a1a9e35822265ad85a4 Mon Sep 17 00:00:00 2001 +From 1df92e173f9dd68d0498d92fb07c15a5b2ddf8eb Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:54 -0500 -Subject: [PATCH 047/467] UPSTREAM: riscv: dts: spacemit: enable the i2c8 - adapter +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable the i2c8 adapter Define properties for the I2C adapter that provides access to the SpacemiT P1 PMIC. Enable this adapter on the Banana Pi BPI-F3. diff --git a/SPECS/linux-lts-kmhv2/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch b/SPECS/linux-lts-kmhv2/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch index f309738c32..3b5e57ed41 100644 --- a/SPECS/linux-lts-kmhv2/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch +++ b/SPECS/linux-lts-kmhv2/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch @@ -1,8 +1,7 @@ -From 60174cdbef524e4485dec91e48413d76da328022 Mon Sep 17 00:00:00 2001 +From b0c37d9383e9fff2cfae5d13e29a5b2fd134e33b Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:55 -0500 -Subject: [PATCH 048/467] UPSTREAM: riscv: dts: spacemit: define fixed - regulators +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define fixed regulators Define the DC power input and the 4v power as fixed supplies in the Banana Pi BPI-F3. diff --git a/SPECS/linux-lts-kmhv2/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch b/SPECS/linux-lts-kmhv2/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch index 0d1ed9ad79..4b13e15e20 100644 --- a/SPECS/linux-lts-kmhv2/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch +++ b/SPECS/linux-lts-kmhv2/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch @@ -1,7 +1,7 @@ -From 43691716fd0d18bd887592bb3f1a7dc63e9b49be Mon Sep 17 00:00:00 2001 +From 7fc9ff12b887fdc874ebb28f553e807648b6a4d4 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:56 -0500 -Subject: [PATCH 049/467] UPSTREAM: riscv: dts: spacemit: define regulator +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define regulator constraints Define basic constraints for the regulators in the SpacemiT P1 PMIC, diff --git a/SPECS/linux-lts-kmhv2/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch b/SPECS/linux-lts-kmhv2/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch index 4266d9d06e..c64be604a7 100644 --- a/SPECS/linux-lts-kmhv2/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch +++ b/SPECS/linux-lts-kmhv2/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch @@ -1,8 +1,8 @@ -From 3d02f5d734bb489dc5c101affd5ad99687ffaffd Mon Sep 17 00:00:00 2001 +From a276be6d58f16c9c62bd6c0f76f6b2133fcfff5b Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 26 Sep 2025 19:54:37 +0200 -Subject: [PATCH 050/467] UPSTREAM: riscv: dts: spacemit: enable the i2c2 - adapter on BPI-F3 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable the i2c2 adapter + on BPI-F3 Define properties for the I2C adapter, and enable it on the BPI-F3. It will be used by the 24c02 eeprom. diff --git a/SPECS/linux-lts-kmhv2/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch b/SPECS/linux-lts-kmhv2/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch index feedcc216d..5c72618d50 100644 --- a/SPECS/linux-lts-kmhv2/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch +++ b/SPECS/linux-lts-kmhv2/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch @@ -1,7 +1,7 @@ -From dc2d05a9865f35af5203640dc5f517c300667ae2 Mon Sep 17 00:00:00 2001 +From c34d30a8bde9d30953c0d83f0fa993d925f5e038 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 26 Sep 2025 19:54:38 +0200 -Subject: [PATCH 051/467] UPSTREAM: riscv: dts: spacemit: add 24c02 eeprom on +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add 24c02 eeprom on BPI-F3 The BPI-F3 board includes a 24c02 eeprom, that stores the MAC addresses diff --git a/SPECS/linux-lts-kmhv2/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch b/SPECS/linux-lts-kmhv2/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch index 3c9f8346f3..3e089bc47b 100644 --- a/SPECS/linux-lts-kmhv2/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch +++ b/SPECS/linux-lts-kmhv2/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch @@ -1,7 +1,7 @@ -From 583c054150ac0bc72eb5f38eba8088468c3e93b5 Mon Sep 17 00:00:00 2001 +From d0ff2694bd729289ac0e0a95bd0ad9c82b10cbe1 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 26 Sep 2025 19:54:39 +0200 -Subject: [PATCH 052/467] UPSTREAM: riscv: dts: spacemit: add i2c aliases on +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add i2c aliases on BPI-F3 Add i2c aliases for i2c2 and i2c8 on BPI-F3. This is useful to keep a diff --git a/SPECS/linux-lts-kmhv2/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch b/SPECS/linux-lts-kmhv2/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch index 6ed1f8203d..2f6950c455 100644 --- a/SPECS/linux-lts-kmhv2/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch +++ b/SPECS/linux-lts-kmhv2/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch @@ -1,8 +1,8 @@ -From 84af2f4907b4dfc470ac41d11760d57cd7907927 Mon Sep 17 00:00:00 2001 +From 13fa4b662d56827d91fb4cbc78cbaf44253e90c9 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Wed, 22 Oct 2025 20:18:38 +0000 -Subject: [PATCH 053/467] UPSTREAM: riscv: dts: spacemit: add Ethernet and PDMA - to OrangePi RV2 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add Ethernet and PDMA to + OrangePi RV2 The OrangePi RV2 board ships two RGMII ethernet ports. Each has an external Motorcomm YT8531C PHY attached, the PHY uses GPIO diff --git a/SPECS/linux-lts-kmhv2/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch b/SPECS/linux-lts-kmhv2/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch index 2b5114e787..e1ebb490cb 100644 --- a/SPECS/linux-lts-kmhv2/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch +++ b/SPECS/linux-lts-kmhv2/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch @@ -1,7 +1,7 @@ -From 0c5f1b6c12c4797ce96d82ce0bc35941b7d11848 Mon Sep 17 00:00:00 2001 +From 3dafd093bd3316afd9db38030ed61ebb2382f469 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 23 Oct 2025 15:28:30 +0800 -Subject: [PATCH 054/467] UPSTREAM: riscv: dts: spacemit: add MusePi Pro board +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add MusePi Pro board device tree Add initial device tree support for the MusePi Pro board [1]. diff --git a/SPECS/linux-lts-kmhv2/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch b/SPECS/linux-lts-kmhv2/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch index b802662e55..1d90bd8999 100644 --- a/SPECS/linux-lts-kmhv2/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch +++ b/SPECS/linux-lts-kmhv2/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch @@ -1,7 +1,7 @@ -From 31318a05caadf4e7a9d89bf5c11a7e4bb248e835 Mon Sep 17 00:00:00 2001 +From ba2b866292f1f2f274ff75a54e87fe7bc5dad3e2 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:06 -0500 -Subject: [PATCH 055/467] UPSTREAM: riscv: dts: spacemit: enable K1 SoC QSPI on +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable K1 SoC QSPI on BPI-F3 Define DTS nodes to enable support for QSPI on the K1 SoC, including the diff --git a/SPECS/linux-lts-kmhv2/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch b/SPECS/linux-lts-kmhv2/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch index fdb81df0ad..6288d13917 100644 --- a/SPECS/linux-lts-kmhv2/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch +++ b/SPECS/linux-lts-kmhv2/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch @@ -1,8 +1,8 @@ -From bb2450948146eabe3ab427e20f97b58aca4b1d6c Mon Sep 17 00:00:00 2001 +From 24c1c297e0c77c81c2e3a9ed9690f3e133986a22 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Wed, 12 Nov 2025 04:44:42 +0000 -Subject: [PATCH 056/467] UPSTREAM: riscv: dts: spacemit: Add OrangePi R2S - board device tree +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add OrangePi R2S board + device tree Add initial device tree support for the OrangePi RV2 board [1], which is marketed as using the Ky X1 SoC but is identical in die and package diff --git a/SPECS/linux-lts-kmhv2/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch b/SPECS/linux-lts-kmhv2/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch index 8604ed55e1..d6b11da6e5 100644 --- a/SPECS/linux-lts-kmhv2/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch +++ b/SPECS/linux-lts-kmhv2/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch @@ -1,7 +1,7 @@ -From baea402c4353408511c0a1dd49a95a3a6cefa14c Mon Sep 17 00:00:00 2001 +From 1831ac73812e9bb0337b60cf0cbe5e61baaf4769 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 5 Nov 2025 11:37:43 +0800 -Subject: [PATCH 057/467] UPSTREAM: riscv: dts: spacemit: reorder i2c2 node +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: reorder i2c2 node Reorder the i2c2 node to its correct position according to its register address.This improves the readability and maintainability diff --git a/SPECS/linux-lts-kmhv2/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch b/SPECS/linux-lts-kmhv2/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch index ae0c476561..128376f03e 100644 --- a/SPECS/linux-lts-kmhv2/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch +++ b/SPECS/linux-lts-kmhv2/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch @@ -1,8 +1,8 @@ -From c45c776b556de646db335514a310bf0caf45e297 Mon Sep 17 00:00:00 2001 +From 30931c3912167e96f982909390b4cb13d61548d5 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 5 Nov 2025 11:37:44 +0800 -Subject: [PATCH 058/467] UPSTREAM: riscv: dts: spacemit: define all missing - I2C controller nodes +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define all missing I2C + controller nodes SpacemiT K1 SoC is equipped with a total of nine I2C controllers, ranging from I2C0 to I2C8. diff --git a/SPECS/linux-lts-kmhv2/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch b/SPECS/linux-lts-kmhv2/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch index 9df139c76a..637f8129fd 100644 --- a/SPECS/linux-lts-kmhv2/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch +++ b/SPECS/linux-lts-kmhv2/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch @@ -1,8 +1,7 @@ -From 70f112bf88bec82aeedec4c778bcd4f3232a0765 Mon Sep 17 00:00:00 2001 +From 915b04c620188a1aac7cc9e8481bd1dc3069817d Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Tue, 18 Nov 2025 14:08:06 +0800 -Subject: [PATCH 059/467] UPSTREAM: rtc: spacemit: MFD_SPACEMIT_P1 as - dependencies +Subject: [RUYI PATCH] UPSTREAM: rtc: spacemit: MFD_SPACEMIT_P1 as dependencies RTC_DRV_SPACEMIT_P1 is a subdevice of P1 and should depend on MFD_SPACEMIT_P1 rather than selecting it directly. Using 'select' diff --git a/SPECS/linux-lts-kmhv2/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch b/SPECS/linux-lts-kmhv2/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch index 8c75b3d1d7..8765e4955a 100644 --- a/SPECS/linux-lts-kmhv2/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch +++ b/SPECS/linux-lts-kmhv2/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch @@ -1,8 +1,8 @@ -From 5428e4b1551b578c73d4dbb8ca29e15132ed6cc3 Mon Sep 17 00:00:00 2001 +From 6069d468c347c12814556df14bbe53dade5799be Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Mon, 27 Oct 2025 13:48:05 +0800 -Subject: [PATCH 060/467] UPSTREAM: mfd: simple-mfd-i2c: Remove select I2C_K1 - from MFD_SPACEMIT_P1 +Subject: [RUYI PATCH] UPSTREAM: mfd: simple-mfd-i2c: Remove select I2C_K1 from + MFD_SPACEMIT_P1 select will force a symbol to a specific value without considering its dependencies. As a result, the i2c-k1 driver will fail to build diff --git a/SPECS/linux-lts-kmhv2/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch b/SPECS/linux-lts-kmhv2/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch index e03efac6a9..29f66cd23f 100644 --- a/SPECS/linux-lts-kmhv2/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch +++ b/SPECS/linux-lts-kmhv2/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch @@ -1,7 +1,7 @@ -From d7b622bee8767fa7990914aca5f7df68b486ec3a Mon Sep 17 00:00:00 2001 +From eef8f9cc817fec7a4c2229a9b9ee475a0efcf53b Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 3 Nov 2025 00:01:59 +0100 -Subject: [PATCH 061/467] UPSTREAM: driver: reset: spacemit-p1: add driver for +Subject: [RUYI PATCH] UPSTREAM: driver: reset: spacemit-p1: add driver for poweroff/reboot This driver implements poweroff/reboot support for the SpacemiT P1 PMIC diff --git a/SPECS/linux-lts-kmhv2/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch b/SPECS/linux-lts-kmhv2/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch index e1ec6c0a80..9e03454da1 100644 --- a/SPECS/linux-lts-kmhv2/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch +++ b/SPECS/linux-lts-kmhv2/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch @@ -1,7 +1,7 @@ -From 689210eca440a1f4fbcfb711fec8d91331cea13e Mon Sep 17 00:00:00 2001 +From a33608232c9c99d13d018635c30ee0ff1983de7e Mon Sep 17 00:00:00 2001 From: Yunhui Cui Date: Tue, 16 Dec 2025 09:47:19 +0800 -Subject: [PATCH 062/467] UPSTREAM: riscv: remove irqflags.h inclusion in +Subject: [RUYI PATCH] UPSTREAM: riscv: remove irqflags.h inclusion in asm/bitops.h The arch/riscv/include/asm/bitops.h does not functionally require diff --git a/SPECS/linux-lts-kmhv2/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch b/SPECS/linux-lts-kmhv2/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch index 4191f8109c..0fb3f34661 100644 --- a/SPECS/linux-lts-kmhv2/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch +++ b/SPECS/linux-lts-kmhv2/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch @@ -1,7 +1,7 @@ -From c7f82d8c41148f7827e892b69de32cfc5f5b6ac8 Mon Sep 17 00:00:00 2001 +From 34f41ea98d21a5605f1d5973259656f6e6557de0 Mon Sep 17 00:00:00 2001 From: Zongmin Zhou Date: Thu, 20 Nov 2025 17:58:31 +0800 -Subject: [PATCH 063/467] UPSTREAM: riscv/atomic.h: use RISCV_FULL_BARRIER in +Subject: [RUYI PATCH] UPSTREAM: riscv/atomic.h: use RISCV_FULL_BARRIER in _arch_atomic* function. Replace the same code with the pre-defined macro diff --git a/SPECS/linux-lts-kmhv2/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch b/SPECS/linux-lts-kmhv2/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch index 81b4d9efe4..0604111102 100644 --- a/SPECS/linux-lts-kmhv2/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch +++ b/SPECS/linux-lts-kmhv2/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch @@ -1,7 +1,7 @@ -From 11ee08759592cbf595fbbc34aab1f2e631fcaaf1 Mon Sep 17 00:00:00 2001 +From 8030689f50a72fc225dd6c31ad77d6b868549463 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 21 Aug 2025 10:17:08 +0200 -Subject: [PATCH 064/467] UPSTREAM: drm/dumb-buffers: Sanitize output on errors +Subject: [RUYI PATCH] UPSTREAM: drm/dumb-buffers: Sanitize output on errors The ioctls MODE_CREATE_DUMB and MODE_MAP_DUMB return results into a memory buffer supplied by user space. On errors, it is possible that diff --git a/SPECS/linux-lts-kmhv2/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch b/SPECS/linux-lts-kmhv2/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch index a51677cd2c..c249232713 100644 --- a/SPECS/linux-lts-kmhv2/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch +++ b/SPECS/linux-lts-kmhv2/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch @@ -1,8 +1,8 @@ -From ffc2daa0d4924fb2007651922cc6c14f597aff80 Mon Sep 17 00:00:00 2001 +From cf1dda8a91f6866dead5cfac3205be1ea706a065 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 21 Aug 2025 10:17:09 +0200 -Subject: [PATCH 065/467] UPSTREAM: drm/dumb-buffers: Provide helper to set - pitch and size +Subject: [RUYI PATCH] UPSTREAM: drm/dumb-buffers: Provide helper to set pitch + and size Add drm_modes_size_dumb(), a helper to calculate the dumb-buffer scanline pitch and allocation size. Implementations of struct diff --git a/SPECS/linux-lts-kmhv2/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch b/SPECS/linux-lts-kmhv2/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch new file mode 100644 index 0000000000..d3d98f5867 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch @@ -0,0 +1,72 @@ +From 5a54ac19c87347a2165595055cab86383cefac4f Mon Sep 17 00:00:00 2001 +From: Thomas Zimmermann +Date: Tue, 16 Sep 2025 10:36:22 +0200 +Subject: [RUYI PATCH] UPSTREAM: drm/hypervdrm: Use vblank timer + +HyperV's virtual hardware does not provide vblank interrupts. Use a +vblank timer to simulate the interrupt. Rate-limits the display's +update frequency to the display-mode settings. Avoids excessive CPU +overhead with compositors that do not rate-limit their output. + +Signed-off-by: Thomas Zimmermann +Reviewed-by: Javier Martinez Canillas +Tested-by: Michael Kelley +Tested-by: Prasanna Kumar T S M +Link: https://lore.kernel.org/r/20250916083816.30275-5-tzimmermann@suse.de +(cherry picked from commit 52e6b198833411564e0b9ce6e96bbd3d72f961e7) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/hyperv/hyperv_drm_modeset.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c +index 945b9482bcb3..6e6eb1c12a68 100644 +--- a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c ++++ b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c +@@ -19,6 +19,8 @@ + #include + #include + #include ++#include ++#include + + #include "hyperv_drm.h" + +@@ -111,11 +113,15 @@ static void hyperv_crtc_helper_atomic_enable(struct drm_crtc *crtc, + crtc_state->mode.hdisplay, + crtc_state->mode.vdisplay, + plane_state->fb->pitches[0]); ++ ++ drm_crtc_vblank_on(crtc); + } + + static const struct drm_crtc_helper_funcs hyperv_crtc_helper_funcs = { + .atomic_check = drm_crtc_helper_atomic_check, ++ .atomic_flush = drm_crtc_vblank_atomic_flush, + .atomic_enable = hyperv_crtc_helper_atomic_enable, ++ .atomic_disable = drm_crtc_vblank_atomic_disable, + }; + + static const struct drm_crtc_funcs hyperv_crtc_funcs = { +@@ -125,6 +131,7 @@ static const struct drm_crtc_funcs hyperv_crtc_funcs = { + .page_flip = drm_atomic_helper_page_flip, + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, ++ DRM_CRTC_VBLANK_TIMER_FUNCS, + }; + + static int hyperv_plane_atomic_check(struct drm_plane *plane, +@@ -321,6 +328,10 @@ int hyperv_mode_config_init(struct hyperv_drm_device *hv) + return ret; + } + ++ ret = drm_vblank_init(dev, 1); ++ if (ret) ++ return ret; ++ + drm_mode_config_reset(dev); + + return 0; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0066-UPSTREAM-drm-vblank-Add-vblank-timer.patch b/SPECS/linux-lts-kmhv2/0066-UPSTREAM-drm-vblank-Add-vblank-timer.patch deleted file mode 100644 index 9ae7a30e23..0000000000 --- a/SPECS/linux-lts-kmhv2/0066-UPSTREAM-drm-vblank-Add-vblank-timer.patch +++ /dev/null @@ -1,533 +0,0 @@ -From e7f0684e97837281f337a4249384ae7efd8c3fc0 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Tue, 16 Sep 2025 10:36:19 +0200 -Subject: [PATCH 066/467] UPSTREAM: drm/vblank: Add vblank timer - -The vblank timer simulates a vblank interrupt for hardware without -support. Rate-limits the display update frequency. - -DRM drivers for hardware without vblank support apply display updates -ASAP. A vblank event informs DRM clients of the completed update. -Userspace compositors immediately schedule the next update, which -creates significant load on virtualization outputs. Display updates -are usually fast on virtualization outputs, as their framebuffers are -in regular system memory and there's no hardware vblank interrupt to -throttle the update rate. - -The vblank timer is a HR timer that signals the vblank in software. -It limits the update frequency of a DRM driver similar to a hardware -vblank interrupt. The timer is not synchronized to the actual vblank -interval of the display. - -The code has been adopted from vkms, which added the funtionality -in commit 3a0709928b17 ("drm/vkms: Add vblank events simulated by -hrtimers"). - -The new implementation is part of the existing vblank support, -which sets up the timer automatically. Drivers only have to start -and cancel the vblank timer as part of enabling and disabling the -CRTC. The new vblank helper library provides callbacks for struct -drm_crtc_funcs. - -The standard way for handling vblank is to call drm_crtc_handle_vblank(). -Drivers that require additional processing, such as vkms, can init -handle_vblank_timeout in struct drm_crtc_helper_funcs to refer to -their timeout handler. - -There's a possible deadlock between drm_crtc_handle_vblank() and -hrtimer_cancel(). [1] The implementation avoids to call hrtimer_cancel() -directly and instead signals to the timer function to not restart -itself. - -v4: -- fix possible race condition between timeout and atomic commit (Michael) -v3: -- avoid deadlock when cancelling timer (Ville, Lyude) -v2: -- implement vblank timer entirely in vblank helpers -- downgrade overrun warning to debug -- fix docs - -Signed-off-by: Thomas Zimmermann -Tested-by: Louis Chauvet -Reviewed-by: Louis Chauvet -Reviewed-by: Javier Martinez Canillas -Tested-by: Michael Kelley -Link: https://lore.kernel.org/all/20250510094757.4174662-1-zengheng4@huawei.com/ # [1] -Link: https://lore.kernel.org/r/20250916083816.30275-2-tzimmermann@suse.de -(cherry picked from commit 74afeb8128502a529041a2566febd26053a7be11) -Signed-off-by: Han Gao ---- - Documentation/gpu/drm-kms-helpers.rst | 12 ++ - drivers/gpu/drm/Makefile | 3 +- - drivers/gpu/drm/drm_vblank.c | 172 ++++++++++++++++++++++- - drivers/gpu/drm/drm_vblank_helper.c | 96 +++++++++++++ - include/drm/drm_modeset_helper_vtables.h | 12 ++ - include/drm/drm_vblank.h | 32 +++++ - include/drm/drm_vblank_helper.h | 33 +++++ - 7 files changed, 357 insertions(+), 3 deletions(-) - create mode 100644 drivers/gpu/drm/drm_vblank_helper.c - create mode 100644 include/drm/drm_vblank_helper.h - -diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst -index 5139705089f2..781129f78b06 100644 ---- a/Documentation/gpu/drm-kms-helpers.rst -+++ b/Documentation/gpu/drm-kms-helpers.rst -@@ -92,6 +92,18 @@ GEM Atomic Helper Reference - .. kernel-doc:: drivers/gpu/drm/drm_gem_atomic_helper.c - :export: - -+VBLANK Helper Reference -+----------------------- -+ -+.. kernel-doc:: drivers/gpu/drm/drm_vblank_helper.c -+ :doc: overview -+ -+.. kernel-doc:: include/drm/drm_vblank_helper.h -+ :internal: -+ -+.. kernel-doc:: drivers/gpu/drm/drm_vblank_helper.c -+ :export: -+ - Simple KMS Helper Reference - =========================== - -diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile -index 742f0d590c5a..b248e64587ed 100644 ---- a/drivers/gpu/drm/Makefile -+++ b/drivers/gpu/drm/Makefile -@@ -152,7 +152,8 @@ drm_kms_helper-y := \ - drm_plane_helper.o \ - drm_probe_helper.o \ - drm_self_refresh_helper.o \ -- drm_simple_kms_helper.o -+ drm_simple_kms_helper.o \ -+ drm_vblank_helper.o - drm_kms_helper-$(CONFIG_DRM_PANEL_BRIDGE) += bridge/panel.o - drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fb_helper.o - obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o -diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c -index 46f59883183d..61e211fd3c9c 100644 ---- a/drivers/gpu/drm/drm_vblank.c -+++ b/drivers/gpu/drm/drm_vblank.c -@@ -136,8 +136,17 @@ - * vblanks after a timer has expired, which can be configured through the - * ``vblankoffdelay`` module parameter. - * -- * Drivers for hardware without support for vertical-blanking interrupts -- * must not call drm_vblank_init(). For such drivers, atomic helpers will -+ * Drivers for hardware without support for vertical-blanking interrupts can -+ * use DRM vblank timers to send vblank events at the rate of the current -+ * display mode's refresh. While not synchronized to the hardware's -+ * vertical-blanking regions, the timer helps DRM clients and compositors to -+ * adapt their update cycle to the display output. Drivers should set up -+ * vblanking as usual, but call drm_crtc_vblank_start_timer() and -+ * drm_crtc_vblank_cancel_timer() as part of their atomic mode setting. -+ * See also DRM vblank helpers for more information. -+ * -+ * Drivers without support for vertical-blanking interrupts nor timers must -+ * not call drm_vblank_init(). For these drivers, atomic helpers will - * automatically generate fake vblank events as part of the display update. - * This functionality also can be controlled by the driver by enabling and - * disabling struct drm_crtc_state.no_vblank. -@@ -508,6 +517,9 @@ static void drm_vblank_init_release(struct drm_device *dev, void *ptr) - drm_WARN_ON(dev, READ_ONCE(vblank->enabled) && - drm_core_check_feature(dev, DRIVER_MODESET)); - -+ if (vblank->vblank_timer.crtc) -+ hrtimer_cancel(&vblank->vblank_timer.timer); -+ - drm_vblank_destroy_worker(vblank); - timer_delete_sync(&vblank->disable_timer); - } -@@ -2162,3 +2174,159 @@ int drm_crtc_queue_sequence_ioctl(struct drm_device *dev, void *data, - return ret; - } - -+/* -+ * VBLANK timer -+ */ -+ -+static enum hrtimer_restart drm_vblank_timer_function(struct hrtimer *timer) -+{ -+ struct drm_vblank_crtc_timer *vtimer = -+ container_of(timer, struct drm_vblank_crtc_timer, timer); -+ struct drm_crtc *crtc = vtimer->crtc; -+ const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; -+ struct drm_device *dev = crtc->dev; -+ unsigned long flags; -+ ktime_t interval; -+ u64 ret_overrun; -+ bool succ; -+ -+ spin_lock_irqsave(&vtimer->interval_lock, flags); -+ interval = vtimer->interval; -+ spin_unlock_irqrestore(&vtimer->interval_lock, flags); -+ -+ if (!interval) -+ return HRTIMER_NORESTART; -+ -+ ret_overrun = hrtimer_forward_now(&vtimer->timer, interval); -+ if (ret_overrun != 1) -+ drm_dbg_vbl(dev, "vblank timer overrun\n"); -+ -+ if (crtc_funcs->handle_vblank_timeout) -+ succ = crtc_funcs->handle_vblank_timeout(crtc); -+ else -+ succ = drm_crtc_handle_vblank(crtc); -+ if (!succ) -+ return HRTIMER_NORESTART; -+ -+ return HRTIMER_RESTART; -+} -+ -+/** -+ * drm_crtc_vblank_start_timer - Starts the vblank timer on the given CRTC -+ * @crtc: the CRTC -+ * -+ * Drivers should call this function from their CRTC's enable_vblank -+ * function to start a vblank timer. The timer will fire after the duration -+ * of a full frame. drm_crtc_vblank_cancel_timer() disables a running timer. -+ * -+ * Returns: -+ * 0 on success, or a negative errno code otherwise. -+ */ -+int drm_crtc_vblank_start_timer(struct drm_crtc *crtc) -+{ -+ struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); -+ struct drm_vblank_crtc_timer *vtimer = &vblank->vblank_timer; -+ unsigned long flags; -+ -+ if (!vtimer->crtc) { -+ /* -+ * Set up the data structures on the first invocation. -+ */ -+ vtimer->crtc = crtc; -+ spin_lock_init(&vtimer->interval_lock); -+ hrtimer_setup(&vtimer->timer, drm_vblank_timer_function, -+ CLOCK_MONOTONIC, HRTIMER_MODE_REL); -+ } else { -+ /* -+ * Timer should not be active. If it is, wait for the -+ * previous cancel operations to finish. -+ */ -+ while (hrtimer_active(&vtimer->timer)) -+ hrtimer_try_to_cancel(&vtimer->timer); -+ } -+ -+ drm_calc_timestamping_constants(crtc, &crtc->mode); -+ -+ spin_lock_irqsave(&vtimer->interval_lock, flags); -+ vtimer->interval = ns_to_ktime(vblank->framedur_ns); -+ spin_unlock_irqrestore(&vtimer->interval_lock, flags); -+ -+ hrtimer_start(&vtimer->timer, vtimer->interval, HRTIMER_MODE_REL); -+ -+ return 0; -+} -+EXPORT_SYMBOL(drm_crtc_vblank_start_timer); -+ -+/** -+ * drm_crtc_vblank_start_timer - Cancels the given CRTC's vblank timer -+ * @crtc: the CRTC -+ * -+ * Drivers should call this function from their CRTC's disable_vblank -+ * function to stop a vblank timer. -+ */ -+void drm_crtc_vblank_cancel_timer(struct drm_crtc *crtc) -+{ -+ struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); -+ struct drm_vblank_crtc_timer *vtimer = &vblank->vblank_timer; -+ unsigned long flags; -+ -+ /* -+ * Calling hrtimer_cancel() can result in a deadlock with DRM's -+ * vblank_time_lime_lock and hrtimers' softirq_expiry_lock. So -+ * clear interval and indicate cancellation. The timer function -+ * will cancel itself on the next invocation. -+ */ -+ -+ spin_lock_irqsave(&vtimer->interval_lock, flags); -+ vtimer->interval = 0; -+ spin_unlock_irqrestore(&vtimer->interval_lock, flags); -+ -+ hrtimer_try_to_cancel(&vtimer->timer); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_cancel_timer); -+ -+/** -+ * drm_crtc_vblank_get_vblank_timeout - Returns the vblank timeout -+ * @crtc: The CRTC -+ * @vblank_time: Returns the next vblank timestamp -+ * -+ * The helper drm_crtc_vblank_get_vblank_timeout() returns the next vblank -+ * timestamp of the CRTC's vblank timer according to the timer's expiry -+ * time. -+ */ -+void drm_crtc_vblank_get_vblank_timeout(struct drm_crtc *crtc, ktime_t *vblank_time) -+{ -+ struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); -+ struct drm_vblank_crtc_timer *vtimer = &vblank->vblank_timer; -+ u64 cur_count; -+ ktime_t cur_time; -+ -+ if (!READ_ONCE(vblank->enabled)) { -+ *vblank_time = ktime_get(); -+ return; -+ } -+ -+ /* -+ * A concurrent vblank timeout could update the expires field before -+ * we compare it with the vblank time. Hence we'd compare the old -+ * expiry time to the new vblank time; deducing the timer had already -+ * expired. Reread until we get consistent values from both fields. -+ */ -+ do { -+ cur_count = drm_crtc_vblank_count_and_time(crtc, &cur_time); -+ *vblank_time = READ_ONCE(vtimer->timer.node.expires); -+ } while (cur_count != drm_crtc_vblank_count_and_time(crtc, &cur_time)); -+ -+ if (drm_WARN_ON(crtc->dev, !ktime_compare(*vblank_time, cur_time))) -+ return; /* Already expired */ -+ -+ /* -+ * To prevent races we roll the hrtimer forward before we do any -+ * interrupt processing - this is how real hw works (the interrupt -+ * is only generated after all the vblank registers are updated) -+ * and what the vblank core expects. Therefore we need to always -+ * correct the timestamp by one frame. -+ */ -+ *vblank_time = ktime_sub(*vblank_time, vtimer->interval); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_get_vblank_timeout); -diff --git a/drivers/gpu/drm/drm_vblank_helper.c b/drivers/gpu/drm/drm_vblank_helper.c -new file mode 100644 -index 000000000000..f94d1e706191 ---- /dev/null -+++ b/drivers/gpu/drm/drm_vblank_helper.c -@@ -0,0 +1,96 @@ -+// SPDX-License-Identifier: MIT -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/** -+ * DOC: overview -+ * -+ * The vblank helper library provides functions for supporting vertical -+ * blanking in DRM drivers. -+ * -+ * For vblank timers, several callback implementations are available. -+ * Drivers enable support for vblank timers by setting the vblank callbacks -+ * in struct &drm_crtc_funcs to the helpers provided by this library. The -+ * initializer macro DRM_CRTC_VBLANK_TIMER_FUNCS does this conveniently. -+ * -+ * Once the driver enables vblank support with drm_vblank_init(), each -+ * CRTC's vblank timer fires according to the programmed display mode. By -+ * default, the vblank timer invokes drm_crtc_handle_vblank(). Drivers with -+ * more specific requirements can set their own handler function in -+ * struct &drm_crtc_helper_funcs.handle_vblank_timeout. -+ */ -+ -+/* -+ * VBLANK timer -+ */ -+ -+/** -+ * drm_crtc_vblank_helper_enable_vblank_timer - Implements struct &drm_crtc_funcs.enable_vblank -+ * @crtc: The CRTC -+ * -+ * The helper drm_crtc_vblank_helper_enable_vblank_timer() implements -+ * enable_vblank of struct drm_crtc_helper_funcs for CRTCs that require -+ * a VBLANK timer. It sets up the timer on the first invocation. The -+ * started timer expires after the current frame duration. See struct -+ * &drm_vblank_crtc.framedur_ns. -+ * -+ * See also struct &drm_crtc_helper_funcs.enable_vblank. -+ * -+ * Returns: -+ * 0 on success, or a negative errno code otherwise. -+ */ -+int drm_crtc_vblank_helper_enable_vblank_timer(struct drm_crtc *crtc) -+{ -+ return drm_crtc_vblank_start_timer(crtc); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_helper_enable_vblank_timer); -+ -+/** -+ * drm_crtc_vblank_helper_disable_vblank_timer - Implements struct &drm_crtc_funcs.disable_vblank -+ * @crtc: The CRTC -+ * -+ * The helper drm_crtc_vblank_helper_disable_vblank_timer() implements -+ * disable_vblank of struct drm_crtc_funcs for CRTCs that require a -+ * VBLANK timer. -+ * -+ * See also struct &drm_crtc_helper_funcs.disable_vblank. -+ */ -+void drm_crtc_vblank_helper_disable_vblank_timer(struct drm_crtc *crtc) -+{ -+ drm_crtc_vblank_cancel_timer(crtc); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_helper_disable_vblank_timer); -+ -+/** -+ * drm_crtc_vblank_helper_get_vblank_timestamp_from_timer - -+ * Implements struct &drm_crtc_funcs.get_vblank_timestamp -+ * @crtc: The CRTC -+ * @max_error: Maximum acceptable error -+ * @vblank_time: Returns the next vblank timestamp -+ * @in_vblank_irq: True is called from drm_crtc_handle_vblank() -+ * -+ * The helper drm_crtc_helper_get_vblank_timestamp_from_timer() implements -+ * get_vblank_timestamp of struct drm_crtc_funcs for CRTCs that require a -+ * VBLANK timer. It returns the timestamp according to the timer's expiry -+ * time. -+ * -+ * See also struct &drm_crtc_funcs.get_vblank_timestamp. -+ * -+ * Returns: -+ * True on success, or false otherwise. -+ */ -+bool drm_crtc_vblank_helper_get_vblank_timestamp_from_timer(struct drm_crtc *crtc, -+ int *max_error, -+ ktime_t *vblank_time, -+ bool in_vblank_irq) -+{ -+ drm_crtc_vblank_get_vblank_timeout(crtc, vblank_time); -+ -+ return true; -+} -+EXPORT_SYMBOL(drm_crtc_vblank_helper_get_vblank_timestamp_from_timer); -diff --git a/include/drm/drm_modeset_helper_vtables.h b/include/drm/drm_modeset_helper_vtables.h -index ce7c7aeac887..fe32854b7ffe 100644 ---- a/include/drm/drm_modeset_helper_vtables.h -+++ b/include/drm/drm_modeset_helper_vtables.h -@@ -490,6 +490,18 @@ struct drm_crtc_helper_funcs { - bool in_vblank_irq, int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode); -+ -+ /** -+ * @handle_vblank_timeout: Handles timeouts of the vblank timer. -+ * -+ * Called by CRTC's the vblank timer on each timeout. Semantics is -+ * equivalient to drm_crtc_handle_vblank(). Implementations should -+ * invoke drm_crtc_handle_vblank() as part of processing the timeout. -+ * -+ * This callback is optional. If unset, the vblank timer invokes -+ * drm_crtc_handle_vblank() directly. -+ */ -+ bool (*handle_vblank_timeout)(struct drm_crtc *crtc); - }; - - /** -diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h -index 151ab1e85b1b..ffa564d79638 100644 ---- a/include/drm/drm_vblank.h -+++ b/include/drm/drm_vblank.h -@@ -25,6 +25,7 @@ - #define _DRM_VBLANK_H_ - - #include -+#include - #include - #include - #include -@@ -103,6 +104,28 @@ struct drm_vblank_crtc_config { - bool disable_immediate; - }; - -+/** -+ * struct drm_vblank_crtc_timer - vblank timer for a CRTC -+ */ -+struct drm_vblank_crtc_timer { -+ /** -+ * @timer: The vblank's high-resolution timer -+ */ -+ struct hrtimer timer; -+ /** -+ * @interval_lock: Protects @interval -+ */ -+ spinlock_t interval_lock; -+ /** -+ * @interval: Duration between two vblanks -+ */ -+ ktime_t interval; -+ /** -+ * @crtc: The timer's CRTC -+ */ -+ struct drm_crtc *crtc; -+}; -+ - /** - * struct drm_vblank_crtc - vblank tracking for a CRTC - * -@@ -254,6 +277,11 @@ struct drm_vblank_crtc { - * cancelled. - */ - wait_queue_head_t work_wait_queue; -+ -+ /** -+ * @vblank_timer: Holds the state of the vblank timer -+ */ -+ struct drm_vblank_crtc_timer vblank_timer; - }; - - struct drm_vblank_crtc *drm_crtc_vblank_crtc(struct drm_crtc *crtc); -@@ -290,6 +318,10 @@ wait_queue_head_t *drm_crtc_vblank_waitqueue(struct drm_crtc *crtc); - void drm_crtc_set_max_vblank_count(struct drm_crtc *crtc, - u32 max_vblank_count); - -+int drm_crtc_vblank_start_timer(struct drm_crtc *crtc); -+void drm_crtc_vblank_cancel_timer(struct drm_crtc *crtc); -+void drm_crtc_vblank_get_vblank_timeout(struct drm_crtc *crtc, ktime_t *vblank_time); -+ - /* - * Helpers for struct drm_crtc_funcs - */ -diff --git a/include/drm/drm_vblank_helper.h b/include/drm/drm_vblank_helper.h -new file mode 100644 -index 000000000000..74a971d0cfba ---- /dev/null -+++ b/include/drm/drm_vblank_helper.h -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef _DRM_VBLANK_HELPER_H_ -+#define _DRM_VBLANK_HELPER_H_ -+ -+#include -+#include -+ -+struct drm_crtc; -+ -+/* -+ * VBLANK timer -+ */ -+ -+int drm_crtc_vblank_helper_enable_vblank_timer(struct drm_crtc *crtc); -+void drm_crtc_vblank_helper_disable_vblank_timer(struct drm_crtc *crtc); -+bool drm_crtc_vblank_helper_get_vblank_timestamp_from_timer(struct drm_crtc *crtc, -+ int *max_error, -+ ktime_t *vblank_time, -+ bool in_vblank_irq); -+ -+/** -+ * DRM_CRTC_VBLANK_TIMER_FUNCS - Default implementation for VBLANK timers -+ * -+ * This macro initializes struct &drm_crtc_funcs to default helpers for -+ * VBLANK timers. -+ */ -+#define DRM_CRTC_VBLANK_TIMER_FUNCS \ -+ .enable_vblank = drm_crtc_vblank_helper_enable_vblank_timer, \ -+ .disable_vblank = drm_crtc_vblank_helper_disable_vblank_timer, \ -+ .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp_from_timer -+ -+#endif --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch b/SPECS/linux-lts-kmhv2/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch new file mode 100644 index 0000000000..d6a9555b97 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch @@ -0,0 +1,200 @@ +From 82e88d4cfa7af6b1ae6ffc952a7d1903d2c8e3ea Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 29 Jan 2026 09:56:06 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI/MSI: Convert the boolean no_64bit_msi flag + to a DMA address mask + +Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but +implement less than 64 address bits. This breaks on platforms where such +a device is assigned an MSI address higher than what's supported. + +Currently, no_64bit_msi bit is set for these devices, meaning that only +32-bit MSI addresses are allowed for them. However, on some platforms the +MSI doorbell address is above the 32-bit limit but within the addressable +range of the device. + +As a first step to enable MSI on those combinations of devices and +platforms, convert the boolean no_64bit_msi flag to a DMA mask and fixup +the affected usage sites: + + - no_64bit_msi = 1 -> msi_addr_mask = DMA_BIT_MASK(32) + - no_64bit_msi = 0 -> msi_addr_mask = DMA_BIT_MASK(64) + - if (no_64bit_msi) -> if (msi_addr_mask < DMA_BIT_MASK(64)) + +Since no values other than DMA_BIT_MASK(32) and DMA_BIT_MASK(64) are used, +this is functionally equivalent. + +This prepares for changing the binary decision between 32 and 64 bit to a +DMA mask based decision which allows to support systems which have a DMA +address space less than 64bit but a MSI doorbell address above the 32-bit +limit. + +[ tglx: Massaged changelog ] + +Signed-off-by: Vivian Wang +Signed-off-by: Thomas Gleixner +Reviewed-by: Brett Creeley # ionic +Reviewed-by: Thomas Gleixner +Acked-by: Takashi Iwai # sound +Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-1-70da998f2750@iscas.ac.cn +(cherry picked from commit 386ced19e9a348e8131d20f009e692fa8fcc4568) +Signed-off-by: Han Gao +--- + arch/powerpc/platforms/powernv/pci-ioda.c | 2 +- + arch/powerpc/platforms/pseries/msi.c | 4 ++-- + drivers/gpu/drm/radeon/radeon_irq_kms.c | 2 +- + drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 2 +- + drivers/pci/msi/msi.c | 2 +- + drivers/pci/msi/pcidev_msi.c | 2 +- + drivers/pci/probe.c | 7 +++++++ + include/linux/pci.h | 8 +++++++- + sound/hda/controllers/intel.c | 2 +- + 9 files changed, 22 insertions(+), 9 deletions(-) + +diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c +index b0c1d9d16fb5..1c78fdfb7b03 100644 +--- a/arch/powerpc/platforms/powernv/pci-ioda.c ++++ b/arch/powerpc/platforms/powernv/pci-ioda.c +@@ -1666,7 +1666,7 @@ static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, + return -ENXIO; + + /* Force 32-bit MSI on some broken devices */ +- if (dev->no_64bit_msi) ++ if (dev->msi_addr_mask < DMA_BIT_MASK(64)) + is_64 = 0; + + /* Assign XIVE to PE */ +diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c +index 56f17296545a..67bc001688c6 100644 +--- a/arch/powerpc/platforms/pseries/msi.c ++++ b/arch/powerpc/platforms/pseries/msi.c +@@ -388,7 +388,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type, + */ + again: + if (type == PCI_CAP_ID_MSI) { +- if (pdev->no_64bit_msi) { ++ if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) { + rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec); + if (rc < 0) { + /* +@@ -414,7 +414,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type, + if (use_32bit_msi_hack && rc > 0) + rtas_hack_32bit_msi_gen2(pdev); + } else { +- if (pdev->no_64bit_msi) ++ if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) + rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSIX_FN, nvec); + else + rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec); +diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c +index 9961251b44ba..d550554a6f3f 100644 +--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c ++++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c +@@ -252,7 +252,7 @@ static bool radeon_msi_ok(struct radeon_device *rdev) + */ + if (rdev->family < CHIP_BONAIRE) { + dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n"); +- rdev->pdev->no_64bit_msi = 1; ++ rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32); + } + + /* force MSI on */ +diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c +index 70d86c5f52fb..0671deae9a28 100644 +--- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c ++++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c +@@ -331,7 +331,7 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + + #ifdef CONFIG_PPC64 + /* Ensure MSI/MSI-X interrupts lie within addressable physical memory */ +- pdev->no_64bit_msi = 1; ++ pdev->msi_addr_mask = DMA_BIT_MASK(32); + #endif + + err = ionic_setup_one(ionic); +diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c +index e010ecd9f90d..fb9a42bec62e 100644 +--- a/drivers/pci/msi/msi.c ++++ b/drivers/pci/msi/msi.c +@@ -322,7 +322,7 @@ static int msi_verify_entries(struct pci_dev *dev) + { + struct msi_desc *entry; + +- if (!dev->no_64bit_msi) ++ if (dev->msi_addr_mask == DMA_BIT_MASK(64)) + return 0; + + msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) { +diff --git a/drivers/pci/msi/pcidev_msi.c b/drivers/pci/msi/pcidev_msi.c +index 5520aff53b56..0b0346813092 100644 +--- a/drivers/pci/msi/pcidev_msi.c ++++ b/drivers/pci/msi/pcidev_msi.c +@@ -24,7 +24,7 @@ void pci_msi_init(struct pci_dev *dev) + } + + if (!(ctrl & PCI_MSI_FLAGS_64BIT)) +- dev->no_64bit_msi = 1; ++ dev->msi_addr_mask = DMA_BIT_MASK(32); + } + + void pci_msix_init(struct pci_dev *dev) +diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c +index 4e4e38e62691..0a3b0df92fc2 100644 +--- a/drivers/pci/probe.c ++++ b/drivers/pci/probe.c +@@ -2026,6 +2026,13 @@ int pci_setup_device(struct pci_dev *dev) + */ + dev->dma_mask = 0xffffffff; + ++ /* ++ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit ++ * if MSI (rather than MSI-X) capability does not have ++ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. ++ */ ++ dev->msi_addr_mask = DMA_BIT_MASK(64); ++ + dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), + dev->bus->number, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn)); +diff --git a/include/linux/pci.h b/include/linux/pci.h +index 89f5a4290b6e..3ea77b9c5901 100644 +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -377,6 +377,13 @@ struct pci_dev { + 0xffffffff. You only need to change + this if your device has broken DMA + or supports 64-bit transfers. */ ++ u64 msi_addr_mask; /* Mask of the bits of bus address for ++ MSI that this device implements. ++ Normally set based on device ++ capabilities. You only need to ++ change this if your device claims ++ to support 64-bit MSI but implements ++ fewer than 64 address bits. */ + + struct device_dma_parameters dma_parms; + +@@ -442,7 +449,6 @@ struct pci_dev { + + unsigned int is_busmaster:1; /* Is busmaster */ + unsigned int no_msi:1; /* May not use MSI */ +- unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ + unsigned int block_cfg_access:1; /* Config space access blocked */ + unsigned int broken_parity_status:1; /* Generates false positive parity */ + unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ +diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c +index 98367b87d801..44781b87d58e 100644 +--- a/sound/hda/controllers/intel.c ++++ b/sound/hda/controllers/intel.c +@@ -1907,7 +1907,7 @@ static int azx_first_init(struct azx *chip) + + if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { + dev_dbg(card->dev, "Disabling 64bit MSI\n"); +- pci->no_64bit_msi = true; ++ pci->msi_addr_mask = DMA_BIT_MASK(32); + } + + pci_set_master(pci); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0067-UPSTREAM-drm-vblank-Add-CRTC-helpers-for-simple-use-.patch b/SPECS/linux-lts-kmhv2/0067-UPSTREAM-drm-vblank-Add-CRTC-helpers-for-simple-use-.patch deleted file mode 100644 index 7253e51186..0000000000 --- a/SPECS/linux-lts-kmhv2/0067-UPSTREAM-drm-vblank-Add-CRTC-helpers-for-simple-use-.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 583cfbbf548a142881ed47ae9a5e1ab10a4ddbb6 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Tue, 16 Sep 2025 10:36:20 +0200 -Subject: [PATCH 067/467] UPSTREAM: drm/vblank: Add CRTC helpers for simple use - cases - -Implement atomic_flush, atomic_enable and atomic_disable of struct -drm_crtc_helper_funcs for vblank handling. Driver with no further -requirements can use these functions instead of adding their own. -Also simplifies the use of vblank timers. - -The code has been adopted from vkms, which added the funtionality -in commit 3a0709928b17 ("drm/vkms: Add vblank events simulated by -hrtimers"). - -v3: -- mention vkms (Javier) -v2: -- fix docs - -Signed-off-by: Thomas Zimmermann -Reviewed-by: Javier Martinez Canillas -Tested-by: Michael Kelley -Link: https://lore.kernel.org/r/20250916083816.30275-3-tzimmermann@suse.de -(cherry picked from commit d54dbb5963bdbdf8559903fe2b2343e871adcb30) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/drm_vblank_helper.c | 80 +++++++++++++++++++++++++++++ - include/drm/drm_vblank_helper.h | 23 +++++++++ - 2 files changed, 103 insertions(+) - -diff --git a/drivers/gpu/drm/drm_vblank_helper.c b/drivers/gpu/drm/drm_vblank_helper.c -index f94d1e706191..a04a6ba1b0ca 100644 ---- a/drivers/gpu/drm/drm_vblank_helper.c -+++ b/drivers/gpu/drm/drm_vblank_helper.c -@@ -1,5 +1,6 @@ - // SPDX-License-Identifier: MIT - -+#include - #include - #include - #include -@@ -17,6 +18,12 @@ - * Drivers enable support for vblank timers by setting the vblank callbacks - * in struct &drm_crtc_funcs to the helpers provided by this library. The - * initializer macro DRM_CRTC_VBLANK_TIMER_FUNCS does this conveniently. -+ * The driver further has to send the VBLANK event from its atomic_flush -+ * callback and control vblank from the CRTC's atomic_enable and atomic_disable -+ * callbacks. The callbacks are located in struct &drm_crtc_helper_funcs. -+ * The vblank helper library provides implementations of these callbacks -+ * for drivers without further requirements. The initializer macro -+ * DRM_CRTC_HELPER_VBLANK_FUNCS sets them coveniently. - * - * Once the driver enables vblank support with drm_vblank_init(), each - * CRTC's vblank timer fires according to the programmed display mode. By -@@ -25,6 +32,79 @@ - * struct &drm_crtc_helper_funcs.handle_vblank_timeout. - */ - -+/* -+ * VBLANK helpers -+ */ -+ -+/** -+ * drm_crtc_vblank_atomic_flush - -+ * Implements struct &drm_crtc_helper_funcs.atomic_flush -+ * @crtc: The CRTC -+ * @state: The atomic state to apply -+ * -+ * The helper drm_crtc_vblank_atomic_flush() implements atomic_flush of -+ * struct drm_crtc_helper_funcs for CRTCs that only need to send out a -+ * VBLANK event. -+ * -+ * See also struct &drm_crtc_helper_funcs.atomic_flush. -+ */ -+void drm_crtc_vblank_atomic_flush(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct drm_device *dev = crtc->dev; -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); -+ struct drm_pending_vblank_event *event; -+ -+ spin_lock_irq(&dev->event_lock); -+ -+ event = crtc_state->event; -+ crtc_state->event = NULL; -+ -+ if (event) { -+ if (drm_crtc_vblank_get(crtc) == 0) -+ drm_crtc_arm_vblank_event(crtc, event); -+ else -+ drm_crtc_send_vblank_event(crtc, event); -+ } -+ -+ spin_unlock_irq(&dev->event_lock); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_atomic_flush); -+ -+/** -+ * drm_crtc_vblank_atomic_enable - Implements struct &drm_crtc_helper_funcs.atomic_enable -+ * @crtc: The CRTC -+ * @state: The atomic state -+ * -+ * The helper drm_crtc_vblank_atomic_enable() implements atomic_enable -+ * of struct drm_crtc_helper_funcs for CRTCs the only need to enable VBLANKs. -+ * -+ * See also struct &drm_crtc_helper_funcs.atomic_enable. -+ */ -+void drm_crtc_vblank_atomic_enable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ drm_crtc_vblank_on(crtc); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_atomic_enable); -+ -+/** -+ * drm_crtc_vblank_atomic_disable - Implements struct &drm_crtc_helper_funcs.atomic_disable -+ * @crtc: The CRTC -+ * @state: The atomic state -+ * -+ * The helper drm_crtc_vblank_atomic_disable() implements atomic_disable -+ * of struct drm_crtc_helper_funcs for CRTCs the only need to disable VBLANKs. -+ * -+ * See also struct &drm_crtc_funcs.atomic_disable. -+ */ -+void drm_crtc_vblank_atomic_disable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ drm_crtc_vblank_off(crtc); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_atomic_disable); -+ - /* - * VBLANK timer - */ -diff --git a/include/drm/drm_vblank_helper.h b/include/drm/drm_vblank_helper.h -index 74a971d0cfba..fcd8a9b35846 100644 ---- a/include/drm/drm_vblank_helper.h -+++ b/include/drm/drm_vblank_helper.h -@@ -6,8 +6,31 @@ - #include - #include - -+struct drm_atomic_state; - struct drm_crtc; - -+/* -+ * VBLANK helpers -+ */ -+ -+void drm_crtc_vblank_atomic_flush(struct drm_crtc *crtc, -+ struct drm_atomic_state *state); -+void drm_crtc_vblank_atomic_enable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state); -+void drm_crtc_vblank_atomic_disable(struct drm_crtc *crtc, -+ struct drm_atomic_state *crtc_state); -+ -+/** -+ * DRM_CRTC_HELPER_VBLANK_FUNCS - Default implementation for VBLANK helpers -+ * -+ * This macro initializes struct &drm_crtc_helper_funcs to default helpers -+ * for VBLANK handling. -+ */ -+#define DRM_CRTC_HELPER_VBLANK_FUNCS \ -+ .atomic_flush = drm_crtc_vblank_atomic_flush, \ -+ .atomic_enable = drm_crtc_vblank_atomic_enable, \ -+ .atomic_disable = drm_crtc_vblank_atomic_disable -+ - /* - * VBLANK timer - */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch b/SPECS/linux-lts-kmhv2/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch new file mode 100644 index 0000000000..46bc6278e3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch @@ -0,0 +1,52 @@ +From 4f4b809bc01cd7d00cf117b7e99a2a2b18a9d9f9 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 29 Jan 2026 09:56:07 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI/MSI: Check the device specific address + mask in msi_verify_entries() + +Instead of a 32-bit/64-bit dichotomy, check the MSI address against +the device specific address mask. + +This allows platforms with an MSI doorbell address above the 32-bit limit +to work with devices without full 64-bit MSI address support, as long as +the doorbell is within the addressable range of the device. + +[ tglx: Massaged changelog ] + +Signed-off-by: Vivian Wang +Signed-off-by: Thomas Gleixner +Reviewed-by: Thomas Gleixner +Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-2-70da998f2750@iscas.ac.cn +(cherry picked from commit 52f0d862f595a2fa18ef44532619a080c24fe4cb) +Signed-off-by: Han Gao +--- + drivers/pci/msi/msi.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c +index fb9a42bec62e..e2412175d7af 100644 +--- a/drivers/pci/msi/msi.c ++++ b/drivers/pci/msi/msi.c +@@ -321,14 +321,16 @@ static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, + static int msi_verify_entries(struct pci_dev *dev) + { + struct msi_desc *entry; ++ u64 address; + + if (dev->msi_addr_mask == DMA_BIT_MASK(64)) + return 0; + + msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) { +- if (entry->msg.address_hi) { +- pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n", +- entry->msg.address_hi, entry->msg.address_lo); ++ address = (u64)entry->msg.address_hi << 32 | entry->msg.address_lo; ++ if (address & ~dev->msi_addr_mask) { ++ pci_err(dev, "arch assigned 64-bit MSI address %#llx above device MSI address mask %#llx\n", ++ address, dev->msi_addr_mask); + break; + } + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0068-UPSTREAM-drm-vkms-Convert-to-DRM-s-vblank-timer.patch b/SPECS/linux-lts-kmhv2/0068-UPSTREAM-drm-vkms-Convert-to-DRM-s-vblank-timer.patch deleted file mode 100644 index 6dbce8b177..0000000000 --- a/SPECS/linux-lts-kmhv2/0068-UPSTREAM-drm-vkms-Convert-to-DRM-s-vblank-timer.patch +++ /dev/null @@ -1,172 +0,0 @@ -From 5c2dba8da42db8a451df4751fdd00dea997959e4 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Tue, 16 Sep 2025 10:36:21 +0200 -Subject: [PATCH 068/467] UPSTREAM: drm/vkms: Convert to DRM's vblank timer - -Replace vkms' vblank timer with the DRM implementation. The DRM -code is identical in concept, but differs in implementation. - -Vblank timers are covered in vblank helpers and initializer macros, -so remove the corresponding hrtimer in struct vkms_output. The -vblank timer calls vkms' custom timeout code via handle_vblank_timeout -in struct drm_crtc_helper_funcs. - -Signed-off-by: Thomas Zimmermann -Tested-by: Louis Chauvet -Reviewed-by: Louis Chauvet -Reviewed-by: Javier Martinez Canillas -Link: https://lore.kernel.org/r/20250916083816.30275-4-tzimmermann@suse.de -(cherry picked from commit 02e2681ffe1addde1fc8c35d05657b16bfa79613) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/vkms/vkms_crtc.c | 83 +++----------------------------- - drivers/gpu/drm/vkms/vkms_drv.h | 2 - - 2 files changed, 7 insertions(+), 78 deletions(-) - -diff --git a/drivers/gpu/drm/vkms/vkms_crtc.c b/drivers/gpu/drm/vkms/vkms_crtc.c -index e60573e0f3e9..bd79f24686dc 100644 ---- a/drivers/gpu/drm/vkms/vkms_crtc.c -+++ b/drivers/gpu/drm/vkms/vkms_crtc.c -@@ -7,25 +7,18 @@ - #include - #include - #include -+#include - - #include "vkms_drv.h" - --static enum hrtimer_restart vkms_vblank_simulate(struct hrtimer *timer) -+static bool vkms_crtc_handle_vblank_timeout(struct drm_crtc *crtc) - { -- struct vkms_output *output = container_of(timer, struct vkms_output, -- vblank_hrtimer); -- struct drm_crtc *crtc = &output->crtc; -+ struct vkms_output *output = drm_crtc_to_vkms_output(crtc); - struct vkms_crtc_state *state; -- u64 ret_overrun; - bool ret, fence_cookie; - - fence_cookie = dma_fence_begin_signalling(); - -- ret_overrun = hrtimer_forward_now(&output->vblank_hrtimer, -- output->period_ns); -- if (ret_overrun != 1) -- pr_warn("%s: vblank timer overrun\n", __func__); -- - spin_lock(&output->lock); - ret = drm_crtc_handle_vblank(crtc); - if (!ret) -@@ -57,55 +50,6 @@ static enum hrtimer_restart vkms_vblank_simulate(struct hrtimer *timer) - - dma_fence_end_signalling(fence_cookie); - -- return HRTIMER_RESTART; --} -- --static int vkms_enable_vblank(struct drm_crtc *crtc) --{ -- struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); -- struct vkms_output *out = drm_crtc_to_vkms_output(crtc); -- -- hrtimer_setup(&out->vblank_hrtimer, &vkms_vblank_simulate, CLOCK_MONOTONIC, -- HRTIMER_MODE_REL); -- out->period_ns = ktime_set(0, vblank->framedur_ns); -- hrtimer_start(&out->vblank_hrtimer, out->period_ns, HRTIMER_MODE_REL); -- -- return 0; --} -- --static void vkms_disable_vblank(struct drm_crtc *crtc) --{ -- struct vkms_output *out = drm_crtc_to_vkms_output(crtc); -- -- hrtimer_cancel(&out->vblank_hrtimer); --} -- --static bool vkms_get_vblank_timestamp(struct drm_crtc *crtc, -- int *max_error, ktime_t *vblank_time, -- bool in_vblank_irq) --{ -- struct vkms_output *output = drm_crtc_to_vkms_output(crtc); -- struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); -- -- if (!READ_ONCE(vblank->enabled)) { -- *vblank_time = ktime_get(); -- return true; -- } -- -- *vblank_time = READ_ONCE(output->vblank_hrtimer.node.expires); -- -- if (WARN_ON(*vblank_time == vblank->time)) -- return true; -- -- /* -- * To prevent races we roll the hrtimer forward before we do any -- * interrupt processing - this is how real hw works (the interrupt is -- * only generated after all the vblank registers are updated) and what -- * the vblank core expects. Therefore we need to always correct the -- * timestampe by one frame. -- */ -- *vblank_time -= output->period_ns; -- - return true; - } - -@@ -159,9 +103,7 @@ static const struct drm_crtc_funcs vkms_crtc_funcs = { - .reset = vkms_atomic_crtc_reset, - .atomic_duplicate_state = vkms_atomic_crtc_duplicate_state, - .atomic_destroy_state = vkms_atomic_crtc_destroy_state, -- .enable_vblank = vkms_enable_vblank, -- .disable_vblank = vkms_disable_vblank, -- .get_vblank_timestamp = vkms_get_vblank_timestamp, -+ DRM_CRTC_VBLANK_TIMER_FUNCS, - .get_crc_sources = vkms_get_crc_sources, - .set_crc_source = vkms_set_crc_source, - .verify_crc_source = vkms_verify_crc_source, -@@ -213,18 +155,6 @@ static int vkms_crtc_atomic_check(struct drm_crtc *crtc, - return 0; - } - --static void vkms_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_atomic_state *state) --{ -- drm_crtc_vblank_on(crtc); --} -- --static void vkms_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_atomic_state *state) --{ -- drm_crtc_vblank_off(crtc); --} -- - static void vkms_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) - __acquires(&vkms_output->lock) -@@ -265,8 +195,9 @@ static const struct drm_crtc_helper_funcs vkms_crtc_helper_funcs = { - .atomic_check = vkms_crtc_atomic_check, - .atomic_begin = vkms_crtc_atomic_begin, - .atomic_flush = vkms_crtc_atomic_flush, -- .atomic_enable = vkms_crtc_atomic_enable, -- .atomic_disable = vkms_crtc_atomic_disable, -+ .atomic_enable = drm_crtc_vblank_atomic_enable, -+ .atomic_disable = drm_crtc_vblank_atomic_disable, -+ .handle_vblank_timeout = vkms_crtc_handle_vblank_timeout, - }; - - struct vkms_output *vkms_crtc_init(struct drm_device *dev, struct drm_plane *primary, -diff --git a/drivers/gpu/drm/vkms/vkms_drv.h b/drivers/gpu/drm/vkms/vkms_drv.h -index 8013c31efe3b..fb9711e1c6fb 100644 ---- a/drivers/gpu/drm/vkms/vkms_drv.h -+++ b/drivers/gpu/drm/vkms/vkms_drv.h -@@ -215,8 +215,6 @@ struct vkms_output { - struct drm_crtc crtc; - struct drm_writeback_connector wb_connector; - struct drm_encoder wb_encoder; -- struct hrtimer vblank_hrtimer; -- ktime_t period_ns; - struct workqueue_struct *composer_workq; - spinlock_t lock; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0069-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch b/SPECS/linux-lts-kmhv2/0069-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch deleted file mode 100644 index 0ad15ed0ef..0000000000 --- a/SPECS/linux-lts-kmhv2/0069-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch +++ /dev/null @@ -1,72 +0,0 @@ -From e0e2839348f82a4bba9e9a4c7f122ed62ae7b0e1 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Tue, 16 Sep 2025 10:36:22 +0200 -Subject: [PATCH 069/467] UPSTREAM: drm/hypervdrm: Use vblank timer - -HyperV's virtual hardware does not provide vblank interrupts. Use a -vblank timer to simulate the interrupt. Rate-limits the display's -update frequency to the display-mode settings. Avoids excessive CPU -overhead with compositors that do not rate-limit their output. - -Signed-off-by: Thomas Zimmermann -Reviewed-by: Javier Martinez Canillas -Tested-by: Michael Kelley -Tested-by: Prasanna Kumar T S M -Link: https://lore.kernel.org/r/20250916083816.30275-5-tzimmermann@suse.de -(cherry picked from commit 52e6b198833411564e0b9ce6e96bbd3d72f961e7) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/hyperv/hyperv_drm_modeset.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c -index 945b9482bcb3..6e6eb1c12a68 100644 ---- a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c -+++ b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c -@@ -19,6 +19,8 @@ - #include - #include - #include -+#include -+#include - - #include "hyperv_drm.h" - -@@ -111,11 +113,15 @@ static void hyperv_crtc_helper_atomic_enable(struct drm_crtc *crtc, - crtc_state->mode.hdisplay, - crtc_state->mode.vdisplay, - plane_state->fb->pitches[0]); -+ -+ drm_crtc_vblank_on(crtc); - } - - static const struct drm_crtc_helper_funcs hyperv_crtc_helper_funcs = { - .atomic_check = drm_crtc_helper_atomic_check, -+ .atomic_flush = drm_crtc_vblank_atomic_flush, - .atomic_enable = hyperv_crtc_helper_atomic_enable, -+ .atomic_disable = drm_crtc_vblank_atomic_disable, - }; - - static const struct drm_crtc_funcs hyperv_crtc_funcs = { -@@ -125,6 +131,7 @@ static const struct drm_crtc_funcs hyperv_crtc_funcs = { - .page_flip = drm_atomic_helper_page_flip, - .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, -+ DRM_CRTC_VBLANK_TIMER_FUNCS, - }; - - static int hyperv_plane_atomic_check(struct drm_plane *plane, -@@ -321,6 +328,10 @@ int hyperv_mode_config_init(struct hyperv_drm_device *hv) - return ret; - } - -+ ret = drm_vblank_init(dev, 1); -+ if (ret) -+ return ret; -+ - drm_mode_config_reset(dev); - - return 0; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch b/SPECS/linux-lts-kmhv2/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch new file mode 100644 index 0000000000..02e46aef2a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch @@ -0,0 +1,74 @@ +From 9dcbec59b17ddb9befc7e35efebe9f69ebeb2745 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 29 Jan 2026 09:56:08 +0800 +Subject: [RUYI PATCH] UPSTREAM: drm/radeon: Make MSI address limit based on + the device DMA limit +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The radeon driver restricts the MSI message address for devices older than +the BONAIR generation to 32-bit MSI addresses due to the former +restrictions of the PCI/MSI code which only allowed either 32-bit or full +64-bit address range. + +This does not work on platforms which have a MSI doorbell address above the +32-bit boundary but do not support the full 64 bit address range. + +The PCI/MSI core converted this binary decision to a DMA_BIT_MASK() based +decision, which allows to describe the device limitations precisely. + +Convert the driver to provide the exact DMA address limitations to the +PCI/MSI core. That allows devices which do not support the full 64-bit +address space to work on platforms which have a MSI doorbell address above +the 32-bit limit as long as it is within the hardware's addressable range. + +[ tglx: Massage changelog ] + +Signed-off-by: Vivian Wang +Signed-off-by: Thomas Gleixner +Reviewed-by: Christian König +Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-3-70da998f2750@iscas.ac.cn +(cherry picked from commit 617562bbe12df796fc21df5fbf262eadf083a90f) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/radeon/radeon_device.c | 1 + + drivers/gpu/drm/radeon/radeon_irq_kms.c | 10 ---------- + 2 files changed, 1 insertion(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c +index 9e35b14e2bf0..92a3e3ee673c 100644 +--- a/drivers/gpu/drm/radeon/radeon_device.c ++++ b/drivers/gpu/drm/radeon/radeon_device.c +@@ -1374,6 +1374,7 @@ int radeon_device_init(struct radeon_device *rdev, + pr_warn("radeon: No suitable DMA available\n"); + return r; + } ++ rdev->pdev->msi_addr_mask = DMA_BIT_MASK(dma_bits); + rdev->need_swiotlb = drm_need_swiotlb(dma_bits); + + /* Registers mapping */ +diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c +index d550554a6f3f..839d619e5602 100644 +--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c ++++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c +@@ -245,16 +245,6 @@ static bool radeon_msi_ok(struct radeon_device *rdev) + if (rdev->flags & RADEON_IS_AGP) + return false; + +- /* +- * Older chips have a HW limitation, they can only generate 40 bits +- * of address for "64-bit" MSIs which breaks on some platforms, notably +- * IBM POWER servers, so we limit them +- */ +- if (rdev->family < CHIP_BONAIRE) { +- dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n"); +- rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32); +- } +- + /* force MSI on */ + if (radeon_msi == 1) + return true; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch b/SPECS/linux-lts-kmhv2/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch new file mode 100644 index 0000000000..5f8bf385cf --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch @@ -0,0 +1,65 @@ +From ed396d380559185d5e0dfad4f40fc5cd8c0382d1 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 29 Jan 2026 09:56:09 +0800 +Subject: [RUYI PATCH] UPSTREAM: ALSA: hda/intel: Make MSI address limit based + on the device DMA limit + +The hda/intel driver restricts the MSI message address for devices which do +not advertise full 64-bit DMA address space support to 32-bit due to the +former restrictions of the PCI/MSI code which only allowed either 32-bit or +a full 64-bit address range. + +This does not work on platforms which have a MSI doorbell address above the +32-bit boundary but do not support the full 64 bit address range. + +The PCI/MSI core converted this binary decision to a DMA_BIT_MASK() based +decision, which allows to describe the device limitations precisely. + +Convert the driver to provide the exact DMA address limitations to the +PCI/MSI core. That allows devices which do not support the full 64-bit +address space to work on platforms which have a MSI doorbell address above +the 32-bit limit as long as it is within the hardware's addressable range. + +[ tglx: Massage changelog ] + +Signed-off-by: Vivian Wang +Signed-off-by: Thomas Gleixner +Acked-by: Takashi Iwai +Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-4-70da998f2750@iscas.ac.cn +(cherry picked from commit cb9b6f9d2be6bda1b0117b147df40f982ce06888) +Signed-off-by: Han Gao +--- + sound/hda/controllers/intel.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c +index 44781b87d58e..6f89875e7c3c 100644 +--- a/sound/hda/controllers/intel.c ++++ b/sound/hda/controllers/intel.c +@@ -1905,11 +1905,6 @@ static int azx_first_init(struct azx *chip) + chip->gts_present = true; + #endif + +- if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { +- dev_dbg(card->dev, "Disabling 64bit MSI\n"); +- pci->msi_addr_mask = DMA_BIT_MASK(32); +- } +- + pci_set_master(pci); + + gcap = azx_readw(chip, GCAP); +@@ -1960,6 +1955,11 @@ static int azx_first_init(struct azx *chip) + dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); + dma_set_max_seg_size(&pci->dev, UINT_MAX); + ++ if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { ++ dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits); ++ pci->msi_addr_mask = DMA_BIT_MASK(dma_bits); ++ } ++ + /* read number of streams from GCAP register instead of using + * hardcoded value + */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0070-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch b/SPECS/linux-lts-kmhv2/0070-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch deleted file mode 100644 index 443c2abc64..0000000000 --- a/SPECS/linux-lts-kmhv2/0070-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch +++ /dev/null @@ -1,200 +0,0 @@ -From be105cf6e6a53eea68ee3af9b6c42db92be45a34 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 29 Jan 2026 09:56:06 +0800 -Subject: [PATCH 070/467] UPSTREAM: PCI/MSI: Convert the boolean no_64bit_msi - flag to a DMA address mask - -Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but -implement less than 64 address bits. This breaks on platforms where such -a device is assigned an MSI address higher than what's supported. - -Currently, no_64bit_msi bit is set for these devices, meaning that only -32-bit MSI addresses are allowed for them. However, on some platforms the -MSI doorbell address is above the 32-bit limit but within the addressable -range of the device. - -As a first step to enable MSI on those combinations of devices and -platforms, convert the boolean no_64bit_msi flag to a DMA mask and fixup -the affected usage sites: - - - no_64bit_msi = 1 -> msi_addr_mask = DMA_BIT_MASK(32) - - no_64bit_msi = 0 -> msi_addr_mask = DMA_BIT_MASK(64) - - if (no_64bit_msi) -> if (msi_addr_mask < DMA_BIT_MASK(64)) - -Since no values other than DMA_BIT_MASK(32) and DMA_BIT_MASK(64) are used, -this is functionally equivalent. - -This prepares for changing the binary decision between 32 and 64 bit to a -DMA mask based decision which allows to support systems which have a DMA -address space less than 64bit but a MSI doorbell address above the 32-bit -limit. - -[ tglx: Massaged changelog ] - -Signed-off-by: Vivian Wang -Signed-off-by: Thomas Gleixner -Reviewed-by: Brett Creeley # ionic -Reviewed-by: Thomas Gleixner -Acked-by: Takashi Iwai # sound -Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-1-70da998f2750@iscas.ac.cn -(cherry picked from commit 386ced19e9a348e8131d20f009e692fa8fcc4568) -Signed-off-by: Han Gao ---- - arch/powerpc/platforms/powernv/pci-ioda.c | 2 +- - arch/powerpc/platforms/pseries/msi.c | 4 ++-- - drivers/gpu/drm/radeon/radeon_irq_kms.c | 2 +- - drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 2 +- - drivers/pci/msi/msi.c | 2 +- - drivers/pci/msi/pcidev_msi.c | 2 +- - drivers/pci/probe.c | 7 +++++++ - include/linux/pci.h | 8 +++++++- - sound/hda/controllers/intel.c | 2 +- - 9 files changed, 22 insertions(+), 9 deletions(-) - -diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c -index b0c1d9d16fb5..1c78fdfb7b03 100644 ---- a/arch/powerpc/platforms/powernv/pci-ioda.c -+++ b/arch/powerpc/platforms/powernv/pci-ioda.c -@@ -1666,7 +1666,7 @@ static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, - return -ENXIO; - - /* Force 32-bit MSI on some broken devices */ -- if (dev->no_64bit_msi) -+ if (dev->msi_addr_mask < DMA_BIT_MASK(64)) - is_64 = 0; - - /* Assign XIVE to PE */ -diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c -index 56f17296545a..67bc001688c6 100644 ---- a/arch/powerpc/platforms/pseries/msi.c -+++ b/arch/powerpc/platforms/pseries/msi.c -@@ -388,7 +388,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type, - */ - again: - if (type == PCI_CAP_ID_MSI) { -- if (pdev->no_64bit_msi) { -+ if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) { - rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec); - if (rc < 0) { - /* -@@ -414,7 +414,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type, - if (use_32bit_msi_hack && rc > 0) - rtas_hack_32bit_msi_gen2(pdev); - } else { -- if (pdev->no_64bit_msi) -+ if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) - rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSIX_FN, nvec); - else - rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec); -diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c -index 9961251b44ba..d550554a6f3f 100644 ---- a/drivers/gpu/drm/radeon/radeon_irq_kms.c -+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c -@@ -252,7 +252,7 @@ static bool radeon_msi_ok(struct radeon_device *rdev) - */ - if (rdev->family < CHIP_BONAIRE) { - dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n"); -- rdev->pdev->no_64bit_msi = 1; -+ rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32); - } - - /* force MSI on */ -diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c -index 70d86c5f52fb..0671deae9a28 100644 ---- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c -+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c -@@ -331,7 +331,7 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) - - #ifdef CONFIG_PPC64 - /* Ensure MSI/MSI-X interrupts lie within addressable physical memory */ -- pdev->no_64bit_msi = 1; -+ pdev->msi_addr_mask = DMA_BIT_MASK(32); - #endif - - err = ionic_setup_one(ionic); -diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c -index e010ecd9f90d..fb9a42bec62e 100644 ---- a/drivers/pci/msi/msi.c -+++ b/drivers/pci/msi/msi.c -@@ -322,7 +322,7 @@ static int msi_verify_entries(struct pci_dev *dev) - { - struct msi_desc *entry; - -- if (!dev->no_64bit_msi) -+ if (dev->msi_addr_mask == DMA_BIT_MASK(64)) - return 0; - - msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) { -diff --git a/drivers/pci/msi/pcidev_msi.c b/drivers/pci/msi/pcidev_msi.c -index 5520aff53b56..0b0346813092 100644 ---- a/drivers/pci/msi/pcidev_msi.c -+++ b/drivers/pci/msi/pcidev_msi.c -@@ -24,7 +24,7 @@ void pci_msi_init(struct pci_dev *dev) - } - - if (!(ctrl & PCI_MSI_FLAGS_64BIT)) -- dev->no_64bit_msi = 1; -+ dev->msi_addr_mask = DMA_BIT_MASK(32); - } - - void pci_msix_init(struct pci_dev *dev) -diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c -index 4e4e38e62691..0a3b0df92fc2 100644 ---- a/drivers/pci/probe.c -+++ b/drivers/pci/probe.c -@@ -2026,6 +2026,13 @@ int pci_setup_device(struct pci_dev *dev) - */ - dev->dma_mask = 0xffffffff; - -+ /* -+ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit -+ * if MSI (rather than MSI-X) capability does not have -+ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. -+ */ -+ dev->msi_addr_mask = DMA_BIT_MASK(64); -+ - dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), - dev->bus->number, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn)); -diff --git a/include/linux/pci.h b/include/linux/pci.h -index 89f5a4290b6e..3ea77b9c5901 100644 ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -377,6 +377,13 @@ struct pci_dev { - 0xffffffff. You only need to change - this if your device has broken DMA - or supports 64-bit transfers. */ -+ u64 msi_addr_mask; /* Mask of the bits of bus address for -+ MSI that this device implements. -+ Normally set based on device -+ capabilities. You only need to -+ change this if your device claims -+ to support 64-bit MSI but implements -+ fewer than 64 address bits. */ - - struct device_dma_parameters dma_parms; - -@@ -442,7 +449,6 @@ struct pci_dev { - - unsigned int is_busmaster:1; /* Is busmaster */ - unsigned int no_msi:1; /* May not use MSI */ -- unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ - unsigned int block_cfg_access:1; /* Config space access blocked */ - unsigned int broken_parity_status:1; /* Generates false positive parity */ - unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ -diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c -index 98367b87d801..44781b87d58e 100644 ---- a/sound/hda/controllers/intel.c -+++ b/sound/hda/controllers/intel.c -@@ -1907,7 +1907,7 @@ static int azx_first_init(struct azx *chip) - - if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { - dev_dbg(card->dev, "Disabling 64bit MSI\n"); -- pci->no_64bit_msi = true; -+ pci->msi_addr_mask = DMA_BIT_MASK(32); - } - - pci_set_master(pci); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0071-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch b/SPECS/linux-lts-kmhv2/0071-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch deleted file mode 100644 index c99a180597..0000000000 --- a/SPECS/linux-lts-kmhv2/0071-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 76e89b16cb73690ff25af12682731fc117be5c3e Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 29 Jan 2026 09:56:07 +0800 -Subject: [PATCH 071/467] UPSTREAM: PCI/MSI: Check the device specific address - mask in msi_verify_entries() - -Instead of a 32-bit/64-bit dichotomy, check the MSI address against -the device specific address mask. - -This allows platforms with an MSI doorbell address above the 32-bit limit -to work with devices without full 64-bit MSI address support, as long as -the doorbell is within the addressable range of the device. - -[ tglx: Massaged changelog ] - -Signed-off-by: Vivian Wang -Signed-off-by: Thomas Gleixner -Reviewed-by: Thomas Gleixner -Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-2-70da998f2750@iscas.ac.cn -(cherry picked from commit 52f0d862f595a2fa18ef44532619a080c24fe4cb) -Signed-off-by: Han Gao ---- - drivers/pci/msi/msi.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - -diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c -index fb9a42bec62e..e2412175d7af 100644 ---- a/drivers/pci/msi/msi.c -+++ b/drivers/pci/msi/msi.c -@@ -321,14 +321,16 @@ static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, - static int msi_verify_entries(struct pci_dev *dev) - { - struct msi_desc *entry; -+ u64 address; - - if (dev->msi_addr_mask == DMA_BIT_MASK(64)) - return 0; - - msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) { -- if (entry->msg.address_hi) { -- pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n", -- entry->msg.address_hi, entry->msg.address_lo); -+ address = (u64)entry->msg.address_hi << 32 | entry->msg.address_lo; -+ if (address & ~dev->msi_addr_mask) { -+ pci_err(dev, "arch assigned 64-bit MSI address %#llx above device MSI address mask %#llx\n", -+ address, dev->msi_addr_mask); - break; - } - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch b/SPECS/linux-lts-kmhv2/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch new file mode 100644 index 0000000000..9eb8c66514 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch @@ -0,0 +1,64 @@ +From f4bd9635e84e4d37d8e56a08bbd43581faeddc96 Mon Sep 17 00:00:00 2001 +From: Michael Orlitzky +Date: Wed, 7 Jan 2026 06:29:22 -0500 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: enable hardware clock + (RTC) on the Milk-V Pioneer + +These boards have a working hardware clock if you put a CR-1220 +battery in them. We enable it using information from a 6.1.x vendor +kernel. + +Reviewed-by: Chen Wang +Signed-off-by: Michael Orlitzky +Link: https://lore.kernel.org/r/20260107112922.20013-2-michael@orlitzky.com +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +Signed-off-by: Chen Wang +(cherry picked from commit 9e81c522680db5998c872fb91ff7877cf3d8ff42) +Signed-off-by: Han Gao +--- + .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 21 +++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +index 54d8386bf9c0..ecf8c1e29079 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts ++++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +@@ -52,6 +52,17 @@ &emmc { + status = "okay"; + }; + ++&i2c0 { ++ pinctrl-0 = <&i2c0_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ rtc: rtc@68 { ++ compatible = "dallas,ds1307"; ++ reg = <0x68>; ++ }; ++}; ++ + &i2c1 { + pinctrl-0 = <&i2c1_cfg>; + pinctrl-names = "default"; +@@ -89,6 +100,16 @@ sdhci-emmc-rst-pwr-pins { + }; + }; + ++ i2c0_cfg: i2c0-cfg { ++ i2c0-pins { ++ pinmux = , ++ ; ++ bias-pull-up; ++ drive-strength-microamp = <26800>; ++ input-schmitt-enable; ++ }; ++ }; ++ + i2c1_cfg: i2c1-cfg { + i2c1-pins { + pinmux = , +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0072-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch b/SPECS/linux-lts-kmhv2/0072-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch deleted file mode 100644 index 3eaeffad7c..0000000000 --- a/SPECS/linux-lts-kmhv2/0072-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch +++ /dev/null @@ -1,74 +0,0 @@ -From ad4fb64413f53de6281889e26345c8138c8057f0 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 29 Jan 2026 09:56:08 +0800 -Subject: [PATCH 072/467] UPSTREAM: drm/radeon: Make MSI address limit based on - the device DMA limit -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The radeon driver restricts the MSI message address for devices older than -the BONAIR generation to 32-bit MSI addresses due to the former -restrictions of the PCI/MSI code which only allowed either 32-bit or full -64-bit address range. - -This does not work on platforms which have a MSI doorbell address above the -32-bit boundary but do not support the full 64 bit address range. - -The PCI/MSI core converted this binary decision to a DMA_BIT_MASK() based -decision, which allows to describe the device limitations precisely. - -Convert the driver to provide the exact DMA address limitations to the -PCI/MSI core. That allows devices which do not support the full 64-bit -address space to work on platforms which have a MSI doorbell address above -the 32-bit limit as long as it is within the hardware's addressable range. - -[ tglx: Massage changelog ] - -Signed-off-by: Vivian Wang -Signed-off-by: Thomas Gleixner -Reviewed-by: Christian König -Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-3-70da998f2750@iscas.ac.cn -(cherry picked from commit 617562bbe12df796fc21df5fbf262eadf083a90f) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/radeon/radeon_device.c | 1 + - drivers/gpu/drm/radeon/radeon_irq_kms.c | 10 ---------- - 2 files changed, 1 insertion(+), 10 deletions(-) - -diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c -index 9e35b14e2bf0..92a3e3ee673c 100644 ---- a/drivers/gpu/drm/radeon/radeon_device.c -+++ b/drivers/gpu/drm/radeon/radeon_device.c -@@ -1374,6 +1374,7 @@ int radeon_device_init(struct radeon_device *rdev, - pr_warn("radeon: No suitable DMA available\n"); - return r; - } -+ rdev->pdev->msi_addr_mask = DMA_BIT_MASK(dma_bits); - rdev->need_swiotlb = drm_need_swiotlb(dma_bits); - - /* Registers mapping */ -diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c -index d550554a6f3f..839d619e5602 100644 ---- a/drivers/gpu/drm/radeon/radeon_irq_kms.c -+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c -@@ -245,16 +245,6 @@ static bool radeon_msi_ok(struct radeon_device *rdev) - if (rdev->flags & RADEON_IS_AGP) - return false; - -- /* -- * Older chips have a HW limitation, they can only generate 40 bits -- * of address for "64-bit" MSIs which breaks on some platforms, notably -- * IBM POWER servers, so we limit them -- */ -- if (rdev->family < CHIP_BONAIRE) { -- dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n"); -- rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32); -- } -- - /* force MSI on */ - if (radeon_msi == 1) - return true; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch b/SPECS/linux-lts-kmhv2/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch new file mode 100644 index 0000000000..0d1f78cb37 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch @@ -0,0 +1,654 @@ +From 4a0cc33492f3fc8e642380ddcf6f355a4ec6cfc1 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Tue, 13 Jan 2026 10:38:26 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Move PLIC and CLINT node + into CPU dtsi + +As we have a separate CPU dtsi file, move the PLIC and CLINT +node to the CPU dtsi file. This will make the sg2042.dtsi focus +on peripheral devices, and make the CPU dtsi force CPU related +devices. + +Reviewed-by: Chen Wang +Link: https://lore.kernel.org/r/20260113023828.790136-1-inochiama@gmail.com +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +Signed-off-by: Chen Wang +(cherry picked from commit 5e6836e735f9c9c5e8e1d1dce02dfed5fe566e8f) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 305 ++++++++++++++++++++ + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 303 ------------------- + 2 files changed, 305 insertions(+), 303 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +index 94a4b71acad3..509488eee432 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +@@ -2189,4 +2189,309 @@ l2_cache15: cache-controller-15 { + cache-unified; + }; + }; ++ ++ soc { ++ intc: interrupt-controller@7090000000 { ++ compatible = "sophgo,sg2042-plic", "thead,c900-plic"; ++ #address-cells = <0>; ++ #interrupt-cells = <2>; ++ reg = <0x00000070 0x90000000 0x00000000 0x04000000>; ++ interrupt-controller; ++ interrupts-extended = ++ <&cpu0_intc 11>, <&cpu0_intc 9>, ++ <&cpu1_intc 11>, <&cpu1_intc 9>, ++ <&cpu2_intc 11>, <&cpu2_intc 9>, ++ <&cpu3_intc 11>, <&cpu3_intc 9>, ++ <&cpu4_intc 11>, <&cpu4_intc 9>, ++ <&cpu5_intc 11>, <&cpu5_intc 9>, ++ <&cpu6_intc 11>, <&cpu6_intc 9>, ++ <&cpu7_intc 11>, <&cpu7_intc 9>, ++ <&cpu8_intc 11>, <&cpu8_intc 9>, ++ <&cpu9_intc 11>, <&cpu9_intc 9>, ++ <&cpu10_intc 11>, <&cpu10_intc 9>, ++ <&cpu11_intc 11>, <&cpu11_intc 9>, ++ <&cpu12_intc 11>, <&cpu12_intc 9>, ++ <&cpu13_intc 11>, <&cpu13_intc 9>, ++ <&cpu14_intc 11>, <&cpu14_intc 9>, ++ <&cpu15_intc 11>, <&cpu15_intc 9>, ++ <&cpu16_intc 11>, <&cpu16_intc 9>, ++ <&cpu17_intc 11>, <&cpu17_intc 9>, ++ <&cpu18_intc 11>, <&cpu18_intc 9>, ++ <&cpu19_intc 11>, <&cpu19_intc 9>, ++ <&cpu20_intc 11>, <&cpu20_intc 9>, ++ <&cpu21_intc 11>, <&cpu21_intc 9>, ++ <&cpu22_intc 11>, <&cpu22_intc 9>, ++ <&cpu23_intc 11>, <&cpu23_intc 9>, ++ <&cpu24_intc 11>, <&cpu24_intc 9>, ++ <&cpu25_intc 11>, <&cpu25_intc 9>, ++ <&cpu26_intc 11>, <&cpu26_intc 9>, ++ <&cpu27_intc 11>, <&cpu27_intc 9>, ++ <&cpu28_intc 11>, <&cpu28_intc 9>, ++ <&cpu29_intc 11>, <&cpu29_intc 9>, ++ <&cpu30_intc 11>, <&cpu30_intc 9>, ++ <&cpu31_intc 11>, <&cpu31_intc 9>, ++ <&cpu32_intc 11>, <&cpu32_intc 9>, ++ <&cpu33_intc 11>, <&cpu33_intc 9>, ++ <&cpu34_intc 11>, <&cpu34_intc 9>, ++ <&cpu35_intc 11>, <&cpu35_intc 9>, ++ <&cpu36_intc 11>, <&cpu36_intc 9>, ++ <&cpu37_intc 11>, <&cpu37_intc 9>, ++ <&cpu38_intc 11>, <&cpu38_intc 9>, ++ <&cpu39_intc 11>, <&cpu39_intc 9>, ++ <&cpu40_intc 11>, <&cpu40_intc 9>, ++ <&cpu41_intc 11>, <&cpu41_intc 9>, ++ <&cpu42_intc 11>, <&cpu42_intc 9>, ++ <&cpu43_intc 11>, <&cpu43_intc 9>, ++ <&cpu44_intc 11>, <&cpu44_intc 9>, ++ <&cpu45_intc 11>, <&cpu45_intc 9>, ++ <&cpu46_intc 11>, <&cpu46_intc 9>, ++ <&cpu47_intc 11>, <&cpu47_intc 9>, ++ <&cpu48_intc 11>, <&cpu48_intc 9>, ++ <&cpu49_intc 11>, <&cpu49_intc 9>, ++ <&cpu50_intc 11>, <&cpu50_intc 9>, ++ <&cpu51_intc 11>, <&cpu51_intc 9>, ++ <&cpu52_intc 11>, <&cpu52_intc 9>, ++ <&cpu53_intc 11>, <&cpu53_intc 9>, ++ <&cpu54_intc 11>, <&cpu54_intc 9>, ++ <&cpu55_intc 11>, <&cpu55_intc 9>, ++ <&cpu56_intc 11>, <&cpu56_intc 9>, ++ <&cpu57_intc 11>, <&cpu57_intc 9>, ++ <&cpu58_intc 11>, <&cpu58_intc 9>, ++ <&cpu59_intc 11>, <&cpu59_intc 9>, ++ <&cpu60_intc 11>, <&cpu60_intc 9>, ++ <&cpu61_intc 11>, <&cpu61_intc 9>, ++ <&cpu62_intc 11>, <&cpu62_intc 9>, ++ <&cpu63_intc 11>, <&cpu63_intc 9>; ++ riscv,ndev = <224>; ++ }; ++ ++ clint_mswi: interrupt-controller@7094000000 { ++ compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; ++ reg = <0x00000070 0x94000000 0x00000000 0x00004000>; ++ interrupts-extended = <&cpu0_intc 3>, ++ <&cpu1_intc 3>, ++ <&cpu2_intc 3>, ++ <&cpu3_intc 3>, ++ <&cpu4_intc 3>, ++ <&cpu5_intc 3>, ++ <&cpu6_intc 3>, ++ <&cpu7_intc 3>, ++ <&cpu8_intc 3>, ++ <&cpu9_intc 3>, ++ <&cpu10_intc 3>, ++ <&cpu11_intc 3>, ++ <&cpu12_intc 3>, ++ <&cpu13_intc 3>, ++ <&cpu14_intc 3>, ++ <&cpu15_intc 3>, ++ <&cpu16_intc 3>, ++ <&cpu17_intc 3>, ++ <&cpu18_intc 3>, ++ <&cpu19_intc 3>, ++ <&cpu20_intc 3>, ++ <&cpu21_intc 3>, ++ <&cpu22_intc 3>, ++ <&cpu23_intc 3>, ++ <&cpu24_intc 3>, ++ <&cpu25_intc 3>, ++ <&cpu26_intc 3>, ++ <&cpu27_intc 3>, ++ <&cpu28_intc 3>, ++ <&cpu29_intc 3>, ++ <&cpu30_intc 3>, ++ <&cpu31_intc 3>, ++ <&cpu32_intc 3>, ++ <&cpu33_intc 3>, ++ <&cpu34_intc 3>, ++ <&cpu35_intc 3>, ++ <&cpu36_intc 3>, ++ <&cpu37_intc 3>, ++ <&cpu38_intc 3>, ++ <&cpu39_intc 3>, ++ <&cpu40_intc 3>, ++ <&cpu41_intc 3>, ++ <&cpu42_intc 3>, ++ <&cpu43_intc 3>, ++ <&cpu44_intc 3>, ++ <&cpu45_intc 3>, ++ <&cpu46_intc 3>, ++ <&cpu47_intc 3>, ++ <&cpu48_intc 3>, ++ <&cpu49_intc 3>, ++ <&cpu50_intc 3>, ++ <&cpu51_intc 3>, ++ <&cpu52_intc 3>, ++ <&cpu53_intc 3>, ++ <&cpu54_intc 3>, ++ <&cpu55_intc 3>, ++ <&cpu56_intc 3>, ++ <&cpu57_intc 3>, ++ <&cpu58_intc 3>, ++ <&cpu59_intc 3>, ++ <&cpu60_intc 3>, ++ <&cpu61_intc 3>, ++ <&cpu62_intc 3>, ++ <&cpu63_intc 3>; ++ }; ++ ++ clint_mtimer0: timer@70ac004000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu0_intc 7>, ++ <&cpu1_intc 7>, ++ <&cpu2_intc 7>, ++ <&cpu3_intc 7>; ++ }; ++ ++ clint_mtimer1: timer@70ac014000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu4_intc 7>, ++ <&cpu5_intc 7>, ++ <&cpu6_intc 7>, ++ <&cpu7_intc 7>; ++ }; ++ ++ clint_mtimer2: timer@70ac024000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu8_intc 7>, ++ <&cpu9_intc 7>, ++ <&cpu10_intc 7>, ++ <&cpu11_intc 7>; ++ }; ++ ++ clint_mtimer3: timer@70ac034000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu12_intc 7>, ++ <&cpu13_intc 7>, ++ <&cpu14_intc 7>, ++ <&cpu15_intc 7>; ++ }; ++ ++ clint_mtimer4: timer@70ac044000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu16_intc 7>, ++ <&cpu17_intc 7>, ++ <&cpu18_intc 7>, ++ <&cpu19_intc 7>; ++ }; ++ ++ clint_mtimer5: timer@70ac054000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu20_intc 7>, ++ <&cpu21_intc 7>, ++ <&cpu22_intc 7>, ++ <&cpu23_intc 7>; ++ }; ++ ++ clint_mtimer6: timer@70ac064000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu24_intc 7>, ++ <&cpu25_intc 7>, ++ <&cpu26_intc 7>, ++ <&cpu27_intc 7>; ++ }; ++ ++ clint_mtimer7: timer@70ac074000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu28_intc 7>, ++ <&cpu29_intc 7>, ++ <&cpu30_intc 7>, ++ <&cpu31_intc 7>; ++ }; ++ ++ clint_mtimer8: timer@70ac084000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu32_intc 7>, ++ <&cpu33_intc 7>, ++ <&cpu34_intc 7>, ++ <&cpu35_intc 7>; ++ }; ++ ++ clint_mtimer9: timer@70ac094000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu36_intc 7>, ++ <&cpu37_intc 7>, ++ <&cpu38_intc 7>, ++ <&cpu39_intc 7>; ++ }; ++ ++ clint_mtimer10: timer@70ac0a4000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu40_intc 7>, ++ <&cpu41_intc 7>, ++ <&cpu42_intc 7>, ++ <&cpu43_intc 7>; ++ }; ++ ++ clint_mtimer11: timer@70ac0b4000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu44_intc 7>, ++ <&cpu45_intc 7>, ++ <&cpu46_intc 7>, ++ <&cpu47_intc 7>; ++ }; ++ ++ clint_mtimer12: timer@70ac0c4000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu48_intc 7>, ++ <&cpu49_intc 7>, ++ <&cpu50_intc 7>, ++ <&cpu51_intc 7>; ++ }; ++ ++ clint_mtimer13: timer@70ac0d4000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu52_intc 7>, ++ <&cpu53_intc 7>, ++ <&cpu54_intc 7>, ++ <&cpu55_intc 7>; ++ }; ++ ++ clint_mtimer14: timer@70ac0e4000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu56_intc 7>, ++ <&cpu57_intc 7>, ++ <&cpu58_intc 7>, ++ <&cpu59_intc 7>; ++ }; ++ ++ clint_mtimer15: timer@70ac0f4000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu60_intc 7>, ++ <&cpu61_intc 7>, ++ <&cpu62_intc 7>, ++ <&cpu63_intc 7>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +index ec99da39150f..e6891f95d479 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +@@ -352,309 +352,6 @@ pcie_rc3: pcie@7062800000 { + status = "disabled"; + }; + +- clint_mswi: interrupt-controller@7094000000 { +- compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; +- reg = <0x00000070 0x94000000 0x00000000 0x00004000>; +- interrupts-extended = <&cpu0_intc 3>, +- <&cpu1_intc 3>, +- <&cpu2_intc 3>, +- <&cpu3_intc 3>, +- <&cpu4_intc 3>, +- <&cpu5_intc 3>, +- <&cpu6_intc 3>, +- <&cpu7_intc 3>, +- <&cpu8_intc 3>, +- <&cpu9_intc 3>, +- <&cpu10_intc 3>, +- <&cpu11_intc 3>, +- <&cpu12_intc 3>, +- <&cpu13_intc 3>, +- <&cpu14_intc 3>, +- <&cpu15_intc 3>, +- <&cpu16_intc 3>, +- <&cpu17_intc 3>, +- <&cpu18_intc 3>, +- <&cpu19_intc 3>, +- <&cpu20_intc 3>, +- <&cpu21_intc 3>, +- <&cpu22_intc 3>, +- <&cpu23_intc 3>, +- <&cpu24_intc 3>, +- <&cpu25_intc 3>, +- <&cpu26_intc 3>, +- <&cpu27_intc 3>, +- <&cpu28_intc 3>, +- <&cpu29_intc 3>, +- <&cpu30_intc 3>, +- <&cpu31_intc 3>, +- <&cpu32_intc 3>, +- <&cpu33_intc 3>, +- <&cpu34_intc 3>, +- <&cpu35_intc 3>, +- <&cpu36_intc 3>, +- <&cpu37_intc 3>, +- <&cpu38_intc 3>, +- <&cpu39_intc 3>, +- <&cpu40_intc 3>, +- <&cpu41_intc 3>, +- <&cpu42_intc 3>, +- <&cpu43_intc 3>, +- <&cpu44_intc 3>, +- <&cpu45_intc 3>, +- <&cpu46_intc 3>, +- <&cpu47_intc 3>, +- <&cpu48_intc 3>, +- <&cpu49_intc 3>, +- <&cpu50_intc 3>, +- <&cpu51_intc 3>, +- <&cpu52_intc 3>, +- <&cpu53_intc 3>, +- <&cpu54_intc 3>, +- <&cpu55_intc 3>, +- <&cpu56_intc 3>, +- <&cpu57_intc 3>, +- <&cpu58_intc 3>, +- <&cpu59_intc 3>, +- <&cpu60_intc 3>, +- <&cpu61_intc 3>, +- <&cpu62_intc 3>, +- <&cpu63_intc 3>; +- }; +- +- clint_mtimer0: timer@70ac004000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu0_intc 7>, +- <&cpu1_intc 7>, +- <&cpu2_intc 7>, +- <&cpu3_intc 7>; +- }; +- +- clint_mtimer1: timer@70ac014000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu4_intc 7>, +- <&cpu5_intc 7>, +- <&cpu6_intc 7>, +- <&cpu7_intc 7>; +- }; +- +- clint_mtimer2: timer@70ac024000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu8_intc 7>, +- <&cpu9_intc 7>, +- <&cpu10_intc 7>, +- <&cpu11_intc 7>; +- }; +- +- clint_mtimer3: timer@70ac034000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu12_intc 7>, +- <&cpu13_intc 7>, +- <&cpu14_intc 7>, +- <&cpu15_intc 7>; +- }; +- +- clint_mtimer4: timer@70ac044000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu16_intc 7>, +- <&cpu17_intc 7>, +- <&cpu18_intc 7>, +- <&cpu19_intc 7>; +- }; +- +- clint_mtimer5: timer@70ac054000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu20_intc 7>, +- <&cpu21_intc 7>, +- <&cpu22_intc 7>, +- <&cpu23_intc 7>; +- }; +- +- clint_mtimer6: timer@70ac064000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu24_intc 7>, +- <&cpu25_intc 7>, +- <&cpu26_intc 7>, +- <&cpu27_intc 7>; +- }; +- +- clint_mtimer7: timer@70ac074000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu28_intc 7>, +- <&cpu29_intc 7>, +- <&cpu30_intc 7>, +- <&cpu31_intc 7>; +- }; +- +- clint_mtimer8: timer@70ac084000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu32_intc 7>, +- <&cpu33_intc 7>, +- <&cpu34_intc 7>, +- <&cpu35_intc 7>; +- }; +- +- clint_mtimer9: timer@70ac094000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu36_intc 7>, +- <&cpu37_intc 7>, +- <&cpu38_intc 7>, +- <&cpu39_intc 7>; +- }; +- +- clint_mtimer10: timer@70ac0a4000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu40_intc 7>, +- <&cpu41_intc 7>, +- <&cpu42_intc 7>, +- <&cpu43_intc 7>; +- }; +- +- clint_mtimer11: timer@70ac0b4000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu44_intc 7>, +- <&cpu45_intc 7>, +- <&cpu46_intc 7>, +- <&cpu47_intc 7>; +- }; +- +- clint_mtimer12: timer@70ac0c4000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu48_intc 7>, +- <&cpu49_intc 7>, +- <&cpu50_intc 7>, +- <&cpu51_intc 7>; +- }; +- +- clint_mtimer13: timer@70ac0d4000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu52_intc 7>, +- <&cpu53_intc 7>, +- <&cpu54_intc 7>, +- <&cpu55_intc 7>; +- }; +- +- clint_mtimer14: timer@70ac0e4000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu56_intc 7>, +- <&cpu57_intc 7>, +- <&cpu58_intc 7>, +- <&cpu59_intc 7>; +- }; +- +- clint_mtimer15: timer@70ac0f4000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu60_intc 7>, +- <&cpu61_intc 7>, +- <&cpu62_intc 7>, +- <&cpu63_intc 7>; +- }; +- +- intc: interrupt-controller@7090000000 { +- compatible = "sophgo,sg2042-plic", "thead,c900-plic"; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x00000070 0x90000000 0x00000000 0x04000000>; +- interrupt-controller; +- interrupts-extended = +- <&cpu0_intc 11>, <&cpu0_intc 9>, +- <&cpu1_intc 11>, <&cpu1_intc 9>, +- <&cpu2_intc 11>, <&cpu2_intc 9>, +- <&cpu3_intc 11>, <&cpu3_intc 9>, +- <&cpu4_intc 11>, <&cpu4_intc 9>, +- <&cpu5_intc 11>, <&cpu5_intc 9>, +- <&cpu6_intc 11>, <&cpu6_intc 9>, +- <&cpu7_intc 11>, <&cpu7_intc 9>, +- <&cpu8_intc 11>, <&cpu8_intc 9>, +- <&cpu9_intc 11>, <&cpu9_intc 9>, +- <&cpu10_intc 11>, <&cpu10_intc 9>, +- <&cpu11_intc 11>, <&cpu11_intc 9>, +- <&cpu12_intc 11>, <&cpu12_intc 9>, +- <&cpu13_intc 11>, <&cpu13_intc 9>, +- <&cpu14_intc 11>, <&cpu14_intc 9>, +- <&cpu15_intc 11>, <&cpu15_intc 9>, +- <&cpu16_intc 11>, <&cpu16_intc 9>, +- <&cpu17_intc 11>, <&cpu17_intc 9>, +- <&cpu18_intc 11>, <&cpu18_intc 9>, +- <&cpu19_intc 11>, <&cpu19_intc 9>, +- <&cpu20_intc 11>, <&cpu20_intc 9>, +- <&cpu21_intc 11>, <&cpu21_intc 9>, +- <&cpu22_intc 11>, <&cpu22_intc 9>, +- <&cpu23_intc 11>, <&cpu23_intc 9>, +- <&cpu24_intc 11>, <&cpu24_intc 9>, +- <&cpu25_intc 11>, <&cpu25_intc 9>, +- <&cpu26_intc 11>, <&cpu26_intc 9>, +- <&cpu27_intc 11>, <&cpu27_intc 9>, +- <&cpu28_intc 11>, <&cpu28_intc 9>, +- <&cpu29_intc 11>, <&cpu29_intc 9>, +- <&cpu30_intc 11>, <&cpu30_intc 9>, +- <&cpu31_intc 11>, <&cpu31_intc 9>, +- <&cpu32_intc 11>, <&cpu32_intc 9>, +- <&cpu33_intc 11>, <&cpu33_intc 9>, +- <&cpu34_intc 11>, <&cpu34_intc 9>, +- <&cpu35_intc 11>, <&cpu35_intc 9>, +- <&cpu36_intc 11>, <&cpu36_intc 9>, +- <&cpu37_intc 11>, <&cpu37_intc 9>, +- <&cpu38_intc 11>, <&cpu38_intc 9>, +- <&cpu39_intc 11>, <&cpu39_intc 9>, +- <&cpu40_intc 11>, <&cpu40_intc 9>, +- <&cpu41_intc 11>, <&cpu41_intc 9>, +- <&cpu42_intc 11>, <&cpu42_intc 9>, +- <&cpu43_intc 11>, <&cpu43_intc 9>, +- <&cpu44_intc 11>, <&cpu44_intc 9>, +- <&cpu45_intc 11>, <&cpu45_intc 9>, +- <&cpu46_intc 11>, <&cpu46_intc 9>, +- <&cpu47_intc 11>, <&cpu47_intc 9>, +- <&cpu48_intc 11>, <&cpu48_intc 9>, +- <&cpu49_intc 11>, <&cpu49_intc 9>, +- <&cpu50_intc 11>, <&cpu50_intc 9>, +- <&cpu51_intc 11>, <&cpu51_intc 9>, +- <&cpu52_intc 11>, <&cpu52_intc 9>, +- <&cpu53_intc 11>, <&cpu53_intc 9>, +- <&cpu54_intc 11>, <&cpu54_intc 9>, +- <&cpu55_intc 11>, <&cpu55_intc 9>, +- <&cpu56_intc 11>, <&cpu56_intc 9>, +- <&cpu57_intc 11>, <&cpu57_intc 9>, +- <&cpu58_intc 11>, <&cpu58_intc 9>, +- <&cpu59_intc 11>, <&cpu59_intc 9>, +- <&cpu60_intc 11>, <&cpu60_intc 9>, +- <&cpu61_intc 11>, <&cpu61_intc 9>, +- <&cpu62_intc 11>, <&cpu62_intc 9>, +- <&cpu63_intc 11>, <&cpu63_intc 9>; +- riscv,ndev = <224>; +- }; +- + rstgen: reset-controller@7030013000 { + compatible = "sophgo,sg2042-reset"; + reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0073-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch b/SPECS/linux-lts-kmhv2/0073-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch deleted file mode 100644 index ff05d9aa86..0000000000 --- a/SPECS/linux-lts-kmhv2/0073-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 749d96eafd7fb34b9586ad8b894f76b4c121a47a Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 29 Jan 2026 09:56:09 +0800 -Subject: [PATCH 073/467] UPSTREAM: ALSA: hda/intel: Make MSI address limit - based on the device DMA limit - -The hda/intel driver restricts the MSI message address for devices which do -not advertise full 64-bit DMA address space support to 32-bit due to the -former restrictions of the PCI/MSI code which only allowed either 32-bit or -a full 64-bit address range. - -This does not work on platforms which have a MSI doorbell address above the -32-bit boundary but do not support the full 64 bit address range. - -The PCI/MSI core converted this binary decision to a DMA_BIT_MASK() based -decision, which allows to describe the device limitations precisely. - -Convert the driver to provide the exact DMA address limitations to the -PCI/MSI core. That allows devices which do not support the full 64-bit -address space to work on platforms which have a MSI doorbell address above -the 32-bit limit as long as it is within the hardware's addressable range. - -[ tglx: Massage changelog ] - -Signed-off-by: Vivian Wang -Signed-off-by: Thomas Gleixner -Acked-by: Takashi Iwai -Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-4-70da998f2750@iscas.ac.cn -(cherry picked from commit cb9b6f9d2be6bda1b0117b147df40f982ce06888) -Signed-off-by: Han Gao ---- - sound/hda/controllers/intel.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c -index 44781b87d58e..6f89875e7c3c 100644 ---- a/sound/hda/controllers/intel.c -+++ b/sound/hda/controllers/intel.c -@@ -1905,11 +1905,6 @@ static int azx_first_init(struct azx *chip) - chip->gts_present = true; - #endif - -- if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { -- dev_dbg(card->dev, "Disabling 64bit MSI\n"); -- pci->msi_addr_mask = DMA_BIT_MASK(32); -- } -- - pci_set_master(pci); - - gcap = azx_readw(chip, GCAP); -@@ -1960,6 +1955,11 @@ static int azx_first_init(struct azx *chip) - dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); - dma_set_max_seg_size(&pci->dev, UINT_MAX); - -+ if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { -+ dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits); -+ pci->msi_addr_mask = DMA_BIT_MASK(dma_bits); -+ } -+ - /* read number of streams from GCAP register instead of using - * hardcoded value - */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch b/SPECS/linux-lts-kmhv2/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch new file mode 100644 index 0000000000..0d20c75013 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch @@ -0,0 +1,216 @@ +From 05c376f7568773671fcd81b7cc92e365126410d0 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Tue, 13 Jan 2026 10:38:27 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: fix the node order of + SG2042 peripheral + +In sg2042.dtsi, some peripheral device node does not follow the +address order. Reorder them in ascending order by address. + +Reviewed-by: Chen Wang +Link: https://lore.kernel.org/r/20260113023828.790136-2-inochiama@gmail.com +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +Signed-off-by: Chen Wang +(cherry picked from commit ebb87dd74c34a76e1e93041e9329cf9269be35ed) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 176 ++++++++++++------------- + 1 file changed, 88 insertions(+), 88 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +index e6891f95d479..9fddf3f0b3b9 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +@@ -264,94 +264,6 @@ clkgen: clock-controller@7030012000 { + #clock-cells = <1>; + }; + +- pcie_rc0: pcie@7060000000 { +- compatible = "sophgo,sg2042-pcie-host"; +- device_type = "pci"; +- reg = <0x70 0x60000000 0x0 0x00800000>, +- <0x40 0x00000000 0x0 0x00001000>; +- reg-names = "reg", "cfg"; +- linux,pci-domain = <0>; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, +- <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, +- <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, +- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, +- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; +- bus-range = <0x0 0xff>; +- vendor-id = <0x1f1c>; +- device-id = <0x2042>; +- cdns,no-bar-match-nbits = <48>; +- msi-parent = <&msi>; +- status = "disabled"; +- }; +- +- pcie_rc1: pcie@7060800000 { +- compatible = "sophgo,sg2042-pcie-host"; +- device_type = "pci"; +- reg = <0x70 0x60800000 0x0 0x00800000>, +- <0x44 0x00000000 0x0 0x00001000>; +- reg-names = "reg", "cfg"; +- linux,pci-domain = <1>; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, +- <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, +- <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, +- <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, +- <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; +- bus-range = <0x0 0xff>; +- vendor-id = <0x1f1c>; +- device-id = <0x2042>; +- cdns,no-bar-match-nbits = <48>; +- msi-parent = <&msi>; +- status = "disabled"; +- }; +- +- pcie_rc2: pcie@7062000000 { +- compatible = "sophgo,sg2042-pcie-host"; +- device_type = "pci"; +- reg = <0x70 0x62000000 0x0 0x00800000>, +- <0x48 0x00000000 0x0 0x00001000>; +- reg-names = "reg", "cfg"; +- linux,pci-domain = <2>; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, +- <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, +- <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, +- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, +- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; +- bus-range = <0x0 0xff>; +- vendor-id = <0x1f1c>; +- device-id = <0x2042>; +- cdns,no-bar-match-nbits = <48>; +- msi-parent = <&msi>; +- status = "disabled"; +- }; +- +- pcie_rc3: pcie@7062800000 { +- compatible = "sophgo,sg2042-pcie-host"; +- device_type = "pci"; +- reg = <0x70 0x62800000 0x0 0x00800000>, +- <0x4c 0x00000000 0x0 0x00001000>; +- reg-names = "reg", "cfg"; +- linux,pci-domain = <3>; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, +- <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, +- <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, +- <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, +- <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; +- bus-range = <0x0 0xff>; +- vendor-id = <0x1f1c>; +- device-id = <0x2042>; +- cdns,no-bar-match-nbits = <48>; +- msi-parent = <&msi>; +- status = "disabled"; +- }; +- + rstgen: reset-controller@7030013000 { + compatible = "sophgo,sg2042-reset"; + reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; +@@ -486,5 +398,93 @@ sd: mmc@704002b000 { + "timer"; + status = "disabled"; + }; ++ ++ pcie_rc0: pcie@7060000000 { ++ compatible = "sophgo,sg2042-pcie-host"; ++ device_type = "pci"; ++ reg = <0x70 0x60000000 0x0 0x00800000>, ++ <0x40 0x00000000 0x0 0x00001000>; ++ reg-names = "reg", "cfg"; ++ linux,pci-domain = <0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, ++ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; ++ bus-range = <0x0 0xff>; ++ vendor-id = <0x1f1c>; ++ device-id = <0x2042>; ++ cdns,no-bar-match-nbits = <48>; ++ msi-parent = <&msi>; ++ status = "disabled"; ++ }; ++ ++ pcie_rc1: pcie@7060800000 { ++ compatible = "sophgo,sg2042-pcie-host"; ++ device_type = "pci"; ++ reg = <0x70 0x60800000 0x0 0x00800000>, ++ <0x44 0x00000000 0x0 0x00001000>; ++ reg-names = "reg", "cfg"; ++ linux,pci-domain = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, ++ <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; ++ bus-range = <0x0 0xff>; ++ vendor-id = <0x1f1c>; ++ device-id = <0x2042>; ++ cdns,no-bar-match-nbits = <48>; ++ msi-parent = <&msi>; ++ status = "disabled"; ++ }; ++ ++ pcie_rc2: pcie@7062000000 { ++ compatible = "sophgo,sg2042-pcie-host"; ++ device_type = "pci"; ++ reg = <0x70 0x62000000 0x0 0x00800000>, ++ <0x48 0x00000000 0x0 0x00001000>; ++ reg-names = "reg", "cfg"; ++ linux,pci-domain = <2>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, ++ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, ++ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; ++ bus-range = <0x0 0xff>; ++ vendor-id = <0x1f1c>; ++ device-id = <0x2042>; ++ cdns,no-bar-match-nbits = <48>; ++ msi-parent = <&msi>; ++ status = "disabled"; ++ }; ++ ++ pcie_rc3: pcie@7062800000 { ++ compatible = "sophgo,sg2042-pcie-host"; ++ device_type = "pci"; ++ reg = <0x70 0x62800000 0x0 0x00800000>, ++ <0x4c 0x00000000 0x0 0x00001000>; ++ reg-names = "reg", "cfg"; ++ linux,pci-domain = <3>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, ++ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, ++ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, ++ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; ++ bus-range = <0x0 0xff>; ++ vendor-id = <0x1f1c>; ++ device-id = <0x2042>; ++ cdns,no-bar-match-nbits = <48>; ++ msi-parent = <&msi>; ++ status = "disabled"; ++ }; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0074-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch b/SPECS/linux-lts-kmhv2/0074-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch deleted file mode 100644 index 37197af0cf..0000000000 --- a/SPECS/linux-lts-kmhv2/0074-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 30a1d9c76630cd4198787ef0603dd4921f1559cf Mon Sep 17 00:00:00 2001 -From: Michael Orlitzky -Date: Wed, 7 Jan 2026 06:29:22 -0500 -Subject: [PATCH 074/467] UPSTREAM: riscv: dts: sophgo: enable hardware clock - (RTC) on the Milk-V Pioneer - -These boards have a working hardware clock if you put a CR-1220 -battery in them. We enable it using information from a 6.1.x vendor -kernel. - -Reviewed-by: Chen Wang -Signed-off-by: Michael Orlitzky -Link: https://lore.kernel.org/r/20260107112922.20013-2-michael@orlitzky.com -Signed-off-by: Inochi Amaoto -Signed-off-by: Chen Wang -Signed-off-by: Chen Wang -(cherry picked from commit 9e81c522680db5998c872fb91ff7877cf3d8ff42) -Signed-off-by: Han Gao ---- - .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 21 +++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts -index 54d8386bf9c0..ecf8c1e29079 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts -+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts -@@ -52,6 +52,17 @@ &emmc { - status = "okay"; - }; - -+&i2c0 { -+ pinctrl-0 = <&i2c0_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ rtc: rtc@68 { -+ compatible = "dallas,ds1307"; -+ reg = <0x68>; -+ }; -+}; -+ - &i2c1 { - pinctrl-0 = <&i2c1_cfg>; - pinctrl-names = "default"; -@@ -89,6 +100,16 @@ sdhci-emmc-rst-pwr-pins { - }; - }; - -+ i2c0_cfg: i2c0-cfg { -+ i2c0-pins { -+ pinmux = , -+ ; -+ bias-pull-up; -+ drive-strength-microamp = <26800>; -+ input-schmitt-enable; -+ }; -+ }; -+ - i2c1_cfg: i2c1-cfg { - i2c1-pins { - pinmux = , --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux-lts-kmhv2/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch new file mode 100644 index 0000000000..5f97d6ec8f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch @@ -0,0 +1,38 @@ +From 7b375e6d39b2d52853eaff4e1f70555adadc5253 Mon Sep 17 00:00:00 2001 +From: Javier Martinez Canillas +Date: Sat, 6 Dec 2025 14:44:53 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Enable i2c8 adapter for + Milk-V Jupiter + +The adapter is used to access the SpacemiT P1 PMIC present in this board. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20251206134532.1741648-2-javierm@redhat.com +Signed-off-by: Yixun Lan +(cherry picked from commit f33ccc2316304f3a71e40e53f1568e75042b0a4b) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 28afd39b28da..aa425f02c1f4 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -72,6 +72,12 @@ &pdma { + status = "okay"; + }; + ++&i2c8 { ++ pinctrl-0 = <&i2c8_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0075-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch b/SPECS/linux-lts-kmhv2/0075-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch deleted file mode 100644 index bf6b8b20f9..0000000000 --- a/SPECS/linux-lts-kmhv2/0075-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch +++ /dev/null @@ -1,654 +0,0 @@ -From e07dd958a1dd608e75f5d83068968406cf2c73a1 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Tue, 13 Jan 2026 10:38:26 +0800 -Subject: [PATCH 075/467] UPSTREAM: riscv: dts: sophgo: Move PLIC and CLINT - node into CPU dtsi - -As we have a separate CPU dtsi file, move the PLIC and CLINT -node to the CPU dtsi file. This will make the sg2042.dtsi focus -on peripheral devices, and make the CPU dtsi force CPU related -devices. - -Reviewed-by: Chen Wang -Link: https://lore.kernel.org/r/20260113023828.790136-1-inochiama@gmail.com -Signed-off-by: Inochi Amaoto -Signed-off-by: Chen Wang -Signed-off-by: Chen Wang -(cherry picked from commit 5e6836e735f9c9c5e8e1d1dce02dfed5fe566e8f) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 305 ++++++++++++++++++++ - arch/riscv/boot/dts/sophgo/sg2042.dtsi | 303 ------------------- - 2 files changed, 305 insertions(+), 303 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -index 94a4b71acad3..509488eee432 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -@@ -2189,4 +2189,309 @@ l2_cache15: cache-controller-15 { - cache-unified; - }; - }; -+ -+ soc { -+ intc: interrupt-controller@7090000000 { -+ compatible = "sophgo,sg2042-plic", "thead,c900-plic"; -+ #address-cells = <0>; -+ #interrupt-cells = <2>; -+ reg = <0x00000070 0x90000000 0x00000000 0x04000000>; -+ interrupt-controller; -+ interrupts-extended = -+ <&cpu0_intc 11>, <&cpu0_intc 9>, -+ <&cpu1_intc 11>, <&cpu1_intc 9>, -+ <&cpu2_intc 11>, <&cpu2_intc 9>, -+ <&cpu3_intc 11>, <&cpu3_intc 9>, -+ <&cpu4_intc 11>, <&cpu4_intc 9>, -+ <&cpu5_intc 11>, <&cpu5_intc 9>, -+ <&cpu6_intc 11>, <&cpu6_intc 9>, -+ <&cpu7_intc 11>, <&cpu7_intc 9>, -+ <&cpu8_intc 11>, <&cpu8_intc 9>, -+ <&cpu9_intc 11>, <&cpu9_intc 9>, -+ <&cpu10_intc 11>, <&cpu10_intc 9>, -+ <&cpu11_intc 11>, <&cpu11_intc 9>, -+ <&cpu12_intc 11>, <&cpu12_intc 9>, -+ <&cpu13_intc 11>, <&cpu13_intc 9>, -+ <&cpu14_intc 11>, <&cpu14_intc 9>, -+ <&cpu15_intc 11>, <&cpu15_intc 9>, -+ <&cpu16_intc 11>, <&cpu16_intc 9>, -+ <&cpu17_intc 11>, <&cpu17_intc 9>, -+ <&cpu18_intc 11>, <&cpu18_intc 9>, -+ <&cpu19_intc 11>, <&cpu19_intc 9>, -+ <&cpu20_intc 11>, <&cpu20_intc 9>, -+ <&cpu21_intc 11>, <&cpu21_intc 9>, -+ <&cpu22_intc 11>, <&cpu22_intc 9>, -+ <&cpu23_intc 11>, <&cpu23_intc 9>, -+ <&cpu24_intc 11>, <&cpu24_intc 9>, -+ <&cpu25_intc 11>, <&cpu25_intc 9>, -+ <&cpu26_intc 11>, <&cpu26_intc 9>, -+ <&cpu27_intc 11>, <&cpu27_intc 9>, -+ <&cpu28_intc 11>, <&cpu28_intc 9>, -+ <&cpu29_intc 11>, <&cpu29_intc 9>, -+ <&cpu30_intc 11>, <&cpu30_intc 9>, -+ <&cpu31_intc 11>, <&cpu31_intc 9>, -+ <&cpu32_intc 11>, <&cpu32_intc 9>, -+ <&cpu33_intc 11>, <&cpu33_intc 9>, -+ <&cpu34_intc 11>, <&cpu34_intc 9>, -+ <&cpu35_intc 11>, <&cpu35_intc 9>, -+ <&cpu36_intc 11>, <&cpu36_intc 9>, -+ <&cpu37_intc 11>, <&cpu37_intc 9>, -+ <&cpu38_intc 11>, <&cpu38_intc 9>, -+ <&cpu39_intc 11>, <&cpu39_intc 9>, -+ <&cpu40_intc 11>, <&cpu40_intc 9>, -+ <&cpu41_intc 11>, <&cpu41_intc 9>, -+ <&cpu42_intc 11>, <&cpu42_intc 9>, -+ <&cpu43_intc 11>, <&cpu43_intc 9>, -+ <&cpu44_intc 11>, <&cpu44_intc 9>, -+ <&cpu45_intc 11>, <&cpu45_intc 9>, -+ <&cpu46_intc 11>, <&cpu46_intc 9>, -+ <&cpu47_intc 11>, <&cpu47_intc 9>, -+ <&cpu48_intc 11>, <&cpu48_intc 9>, -+ <&cpu49_intc 11>, <&cpu49_intc 9>, -+ <&cpu50_intc 11>, <&cpu50_intc 9>, -+ <&cpu51_intc 11>, <&cpu51_intc 9>, -+ <&cpu52_intc 11>, <&cpu52_intc 9>, -+ <&cpu53_intc 11>, <&cpu53_intc 9>, -+ <&cpu54_intc 11>, <&cpu54_intc 9>, -+ <&cpu55_intc 11>, <&cpu55_intc 9>, -+ <&cpu56_intc 11>, <&cpu56_intc 9>, -+ <&cpu57_intc 11>, <&cpu57_intc 9>, -+ <&cpu58_intc 11>, <&cpu58_intc 9>, -+ <&cpu59_intc 11>, <&cpu59_intc 9>, -+ <&cpu60_intc 11>, <&cpu60_intc 9>, -+ <&cpu61_intc 11>, <&cpu61_intc 9>, -+ <&cpu62_intc 11>, <&cpu62_intc 9>, -+ <&cpu63_intc 11>, <&cpu63_intc 9>; -+ riscv,ndev = <224>; -+ }; -+ -+ clint_mswi: interrupt-controller@7094000000 { -+ compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; -+ reg = <0x00000070 0x94000000 0x00000000 0x00004000>; -+ interrupts-extended = <&cpu0_intc 3>, -+ <&cpu1_intc 3>, -+ <&cpu2_intc 3>, -+ <&cpu3_intc 3>, -+ <&cpu4_intc 3>, -+ <&cpu5_intc 3>, -+ <&cpu6_intc 3>, -+ <&cpu7_intc 3>, -+ <&cpu8_intc 3>, -+ <&cpu9_intc 3>, -+ <&cpu10_intc 3>, -+ <&cpu11_intc 3>, -+ <&cpu12_intc 3>, -+ <&cpu13_intc 3>, -+ <&cpu14_intc 3>, -+ <&cpu15_intc 3>, -+ <&cpu16_intc 3>, -+ <&cpu17_intc 3>, -+ <&cpu18_intc 3>, -+ <&cpu19_intc 3>, -+ <&cpu20_intc 3>, -+ <&cpu21_intc 3>, -+ <&cpu22_intc 3>, -+ <&cpu23_intc 3>, -+ <&cpu24_intc 3>, -+ <&cpu25_intc 3>, -+ <&cpu26_intc 3>, -+ <&cpu27_intc 3>, -+ <&cpu28_intc 3>, -+ <&cpu29_intc 3>, -+ <&cpu30_intc 3>, -+ <&cpu31_intc 3>, -+ <&cpu32_intc 3>, -+ <&cpu33_intc 3>, -+ <&cpu34_intc 3>, -+ <&cpu35_intc 3>, -+ <&cpu36_intc 3>, -+ <&cpu37_intc 3>, -+ <&cpu38_intc 3>, -+ <&cpu39_intc 3>, -+ <&cpu40_intc 3>, -+ <&cpu41_intc 3>, -+ <&cpu42_intc 3>, -+ <&cpu43_intc 3>, -+ <&cpu44_intc 3>, -+ <&cpu45_intc 3>, -+ <&cpu46_intc 3>, -+ <&cpu47_intc 3>, -+ <&cpu48_intc 3>, -+ <&cpu49_intc 3>, -+ <&cpu50_intc 3>, -+ <&cpu51_intc 3>, -+ <&cpu52_intc 3>, -+ <&cpu53_intc 3>, -+ <&cpu54_intc 3>, -+ <&cpu55_intc 3>, -+ <&cpu56_intc 3>, -+ <&cpu57_intc 3>, -+ <&cpu58_intc 3>, -+ <&cpu59_intc 3>, -+ <&cpu60_intc 3>, -+ <&cpu61_intc 3>, -+ <&cpu62_intc 3>, -+ <&cpu63_intc 3>; -+ }; -+ -+ clint_mtimer0: timer@70ac004000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu0_intc 7>, -+ <&cpu1_intc 7>, -+ <&cpu2_intc 7>, -+ <&cpu3_intc 7>; -+ }; -+ -+ clint_mtimer1: timer@70ac014000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu4_intc 7>, -+ <&cpu5_intc 7>, -+ <&cpu6_intc 7>, -+ <&cpu7_intc 7>; -+ }; -+ -+ clint_mtimer2: timer@70ac024000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu8_intc 7>, -+ <&cpu9_intc 7>, -+ <&cpu10_intc 7>, -+ <&cpu11_intc 7>; -+ }; -+ -+ clint_mtimer3: timer@70ac034000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu12_intc 7>, -+ <&cpu13_intc 7>, -+ <&cpu14_intc 7>, -+ <&cpu15_intc 7>; -+ }; -+ -+ clint_mtimer4: timer@70ac044000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu16_intc 7>, -+ <&cpu17_intc 7>, -+ <&cpu18_intc 7>, -+ <&cpu19_intc 7>; -+ }; -+ -+ clint_mtimer5: timer@70ac054000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu20_intc 7>, -+ <&cpu21_intc 7>, -+ <&cpu22_intc 7>, -+ <&cpu23_intc 7>; -+ }; -+ -+ clint_mtimer6: timer@70ac064000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu24_intc 7>, -+ <&cpu25_intc 7>, -+ <&cpu26_intc 7>, -+ <&cpu27_intc 7>; -+ }; -+ -+ clint_mtimer7: timer@70ac074000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu28_intc 7>, -+ <&cpu29_intc 7>, -+ <&cpu30_intc 7>, -+ <&cpu31_intc 7>; -+ }; -+ -+ clint_mtimer8: timer@70ac084000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu32_intc 7>, -+ <&cpu33_intc 7>, -+ <&cpu34_intc 7>, -+ <&cpu35_intc 7>; -+ }; -+ -+ clint_mtimer9: timer@70ac094000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu36_intc 7>, -+ <&cpu37_intc 7>, -+ <&cpu38_intc 7>, -+ <&cpu39_intc 7>; -+ }; -+ -+ clint_mtimer10: timer@70ac0a4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu40_intc 7>, -+ <&cpu41_intc 7>, -+ <&cpu42_intc 7>, -+ <&cpu43_intc 7>; -+ }; -+ -+ clint_mtimer11: timer@70ac0b4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu44_intc 7>, -+ <&cpu45_intc 7>, -+ <&cpu46_intc 7>, -+ <&cpu47_intc 7>; -+ }; -+ -+ clint_mtimer12: timer@70ac0c4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu48_intc 7>, -+ <&cpu49_intc 7>, -+ <&cpu50_intc 7>, -+ <&cpu51_intc 7>; -+ }; -+ -+ clint_mtimer13: timer@70ac0d4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu52_intc 7>, -+ <&cpu53_intc 7>, -+ <&cpu54_intc 7>, -+ <&cpu55_intc 7>; -+ }; -+ -+ clint_mtimer14: timer@70ac0e4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu56_intc 7>, -+ <&cpu57_intc 7>, -+ <&cpu58_intc 7>, -+ <&cpu59_intc 7>; -+ }; -+ -+ clint_mtimer15: timer@70ac0f4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu60_intc 7>, -+ <&cpu61_intc 7>, -+ <&cpu62_intc 7>, -+ <&cpu63_intc 7>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -index ec99da39150f..e6891f95d479 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -@@ -352,309 +352,6 @@ pcie_rc3: pcie@7062800000 { - status = "disabled"; - }; - -- clint_mswi: interrupt-controller@7094000000 { -- compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; -- reg = <0x00000070 0x94000000 0x00000000 0x00004000>; -- interrupts-extended = <&cpu0_intc 3>, -- <&cpu1_intc 3>, -- <&cpu2_intc 3>, -- <&cpu3_intc 3>, -- <&cpu4_intc 3>, -- <&cpu5_intc 3>, -- <&cpu6_intc 3>, -- <&cpu7_intc 3>, -- <&cpu8_intc 3>, -- <&cpu9_intc 3>, -- <&cpu10_intc 3>, -- <&cpu11_intc 3>, -- <&cpu12_intc 3>, -- <&cpu13_intc 3>, -- <&cpu14_intc 3>, -- <&cpu15_intc 3>, -- <&cpu16_intc 3>, -- <&cpu17_intc 3>, -- <&cpu18_intc 3>, -- <&cpu19_intc 3>, -- <&cpu20_intc 3>, -- <&cpu21_intc 3>, -- <&cpu22_intc 3>, -- <&cpu23_intc 3>, -- <&cpu24_intc 3>, -- <&cpu25_intc 3>, -- <&cpu26_intc 3>, -- <&cpu27_intc 3>, -- <&cpu28_intc 3>, -- <&cpu29_intc 3>, -- <&cpu30_intc 3>, -- <&cpu31_intc 3>, -- <&cpu32_intc 3>, -- <&cpu33_intc 3>, -- <&cpu34_intc 3>, -- <&cpu35_intc 3>, -- <&cpu36_intc 3>, -- <&cpu37_intc 3>, -- <&cpu38_intc 3>, -- <&cpu39_intc 3>, -- <&cpu40_intc 3>, -- <&cpu41_intc 3>, -- <&cpu42_intc 3>, -- <&cpu43_intc 3>, -- <&cpu44_intc 3>, -- <&cpu45_intc 3>, -- <&cpu46_intc 3>, -- <&cpu47_intc 3>, -- <&cpu48_intc 3>, -- <&cpu49_intc 3>, -- <&cpu50_intc 3>, -- <&cpu51_intc 3>, -- <&cpu52_intc 3>, -- <&cpu53_intc 3>, -- <&cpu54_intc 3>, -- <&cpu55_intc 3>, -- <&cpu56_intc 3>, -- <&cpu57_intc 3>, -- <&cpu58_intc 3>, -- <&cpu59_intc 3>, -- <&cpu60_intc 3>, -- <&cpu61_intc 3>, -- <&cpu62_intc 3>, -- <&cpu63_intc 3>; -- }; -- -- clint_mtimer0: timer@70ac004000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu0_intc 7>, -- <&cpu1_intc 7>, -- <&cpu2_intc 7>, -- <&cpu3_intc 7>; -- }; -- -- clint_mtimer1: timer@70ac014000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu4_intc 7>, -- <&cpu5_intc 7>, -- <&cpu6_intc 7>, -- <&cpu7_intc 7>; -- }; -- -- clint_mtimer2: timer@70ac024000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu8_intc 7>, -- <&cpu9_intc 7>, -- <&cpu10_intc 7>, -- <&cpu11_intc 7>; -- }; -- -- clint_mtimer3: timer@70ac034000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu12_intc 7>, -- <&cpu13_intc 7>, -- <&cpu14_intc 7>, -- <&cpu15_intc 7>; -- }; -- -- clint_mtimer4: timer@70ac044000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu16_intc 7>, -- <&cpu17_intc 7>, -- <&cpu18_intc 7>, -- <&cpu19_intc 7>; -- }; -- -- clint_mtimer5: timer@70ac054000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu20_intc 7>, -- <&cpu21_intc 7>, -- <&cpu22_intc 7>, -- <&cpu23_intc 7>; -- }; -- -- clint_mtimer6: timer@70ac064000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu24_intc 7>, -- <&cpu25_intc 7>, -- <&cpu26_intc 7>, -- <&cpu27_intc 7>; -- }; -- -- clint_mtimer7: timer@70ac074000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu28_intc 7>, -- <&cpu29_intc 7>, -- <&cpu30_intc 7>, -- <&cpu31_intc 7>; -- }; -- -- clint_mtimer8: timer@70ac084000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu32_intc 7>, -- <&cpu33_intc 7>, -- <&cpu34_intc 7>, -- <&cpu35_intc 7>; -- }; -- -- clint_mtimer9: timer@70ac094000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu36_intc 7>, -- <&cpu37_intc 7>, -- <&cpu38_intc 7>, -- <&cpu39_intc 7>; -- }; -- -- clint_mtimer10: timer@70ac0a4000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu40_intc 7>, -- <&cpu41_intc 7>, -- <&cpu42_intc 7>, -- <&cpu43_intc 7>; -- }; -- -- clint_mtimer11: timer@70ac0b4000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu44_intc 7>, -- <&cpu45_intc 7>, -- <&cpu46_intc 7>, -- <&cpu47_intc 7>; -- }; -- -- clint_mtimer12: timer@70ac0c4000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu48_intc 7>, -- <&cpu49_intc 7>, -- <&cpu50_intc 7>, -- <&cpu51_intc 7>; -- }; -- -- clint_mtimer13: timer@70ac0d4000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu52_intc 7>, -- <&cpu53_intc 7>, -- <&cpu54_intc 7>, -- <&cpu55_intc 7>; -- }; -- -- clint_mtimer14: timer@70ac0e4000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu56_intc 7>, -- <&cpu57_intc 7>, -- <&cpu58_intc 7>, -- <&cpu59_intc 7>; -- }; -- -- clint_mtimer15: timer@70ac0f4000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu60_intc 7>, -- <&cpu61_intc 7>, -- <&cpu62_intc 7>, -- <&cpu63_intc 7>; -- }; -- -- intc: interrupt-controller@7090000000 { -- compatible = "sophgo,sg2042-plic", "thead,c900-plic"; -- #address-cells = <0>; -- #interrupt-cells = <2>; -- reg = <0x00000070 0x90000000 0x00000000 0x04000000>; -- interrupt-controller; -- interrupts-extended = -- <&cpu0_intc 11>, <&cpu0_intc 9>, -- <&cpu1_intc 11>, <&cpu1_intc 9>, -- <&cpu2_intc 11>, <&cpu2_intc 9>, -- <&cpu3_intc 11>, <&cpu3_intc 9>, -- <&cpu4_intc 11>, <&cpu4_intc 9>, -- <&cpu5_intc 11>, <&cpu5_intc 9>, -- <&cpu6_intc 11>, <&cpu6_intc 9>, -- <&cpu7_intc 11>, <&cpu7_intc 9>, -- <&cpu8_intc 11>, <&cpu8_intc 9>, -- <&cpu9_intc 11>, <&cpu9_intc 9>, -- <&cpu10_intc 11>, <&cpu10_intc 9>, -- <&cpu11_intc 11>, <&cpu11_intc 9>, -- <&cpu12_intc 11>, <&cpu12_intc 9>, -- <&cpu13_intc 11>, <&cpu13_intc 9>, -- <&cpu14_intc 11>, <&cpu14_intc 9>, -- <&cpu15_intc 11>, <&cpu15_intc 9>, -- <&cpu16_intc 11>, <&cpu16_intc 9>, -- <&cpu17_intc 11>, <&cpu17_intc 9>, -- <&cpu18_intc 11>, <&cpu18_intc 9>, -- <&cpu19_intc 11>, <&cpu19_intc 9>, -- <&cpu20_intc 11>, <&cpu20_intc 9>, -- <&cpu21_intc 11>, <&cpu21_intc 9>, -- <&cpu22_intc 11>, <&cpu22_intc 9>, -- <&cpu23_intc 11>, <&cpu23_intc 9>, -- <&cpu24_intc 11>, <&cpu24_intc 9>, -- <&cpu25_intc 11>, <&cpu25_intc 9>, -- <&cpu26_intc 11>, <&cpu26_intc 9>, -- <&cpu27_intc 11>, <&cpu27_intc 9>, -- <&cpu28_intc 11>, <&cpu28_intc 9>, -- <&cpu29_intc 11>, <&cpu29_intc 9>, -- <&cpu30_intc 11>, <&cpu30_intc 9>, -- <&cpu31_intc 11>, <&cpu31_intc 9>, -- <&cpu32_intc 11>, <&cpu32_intc 9>, -- <&cpu33_intc 11>, <&cpu33_intc 9>, -- <&cpu34_intc 11>, <&cpu34_intc 9>, -- <&cpu35_intc 11>, <&cpu35_intc 9>, -- <&cpu36_intc 11>, <&cpu36_intc 9>, -- <&cpu37_intc 11>, <&cpu37_intc 9>, -- <&cpu38_intc 11>, <&cpu38_intc 9>, -- <&cpu39_intc 11>, <&cpu39_intc 9>, -- <&cpu40_intc 11>, <&cpu40_intc 9>, -- <&cpu41_intc 11>, <&cpu41_intc 9>, -- <&cpu42_intc 11>, <&cpu42_intc 9>, -- <&cpu43_intc 11>, <&cpu43_intc 9>, -- <&cpu44_intc 11>, <&cpu44_intc 9>, -- <&cpu45_intc 11>, <&cpu45_intc 9>, -- <&cpu46_intc 11>, <&cpu46_intc 9>, -- <&cpu47_intc 11>, <&cpu47_intc 9>, -- <&cpu48_intc 11>, <&cpu48_intc 9>, -- <&cpu49_intc 11>, <&cpu49_intc 9>, -- <&cpu50_intc 11>, <&cpu50_intc 9>, -- <&cpu51_intc 11>, <&cpu51_intc 9>, -- <&cpu52_intc 11>, <&cpu52_intc 9>, -- <&cpu53_intc 11>, <&cpu53_intc 9>, -- <&cpu54_intc 11>, <&cpu54_intc 9>, -- <&cpu55_intc 11>, <&cpu55_intc 9>, -- <&cpu56_intc 11>, <&cpu56_intc 9>, -- <&cpu57_intc 11>, <&cpu57_intc 9>, -- <&cpu58_intc 11>, <&cpu58_intc 9>, -- <&cpu59_intc 11>, <&cpu59_intc 9>, -- <&cpu60_intc 11>, <&cpu60_intc 9>, -- <&cpu61_intc 11>, <&cpu61_intc 9>, -- <&cpu62_intc 11>, <&cpu62_intc 9>, -- <&cpu63_intc 11>, <&cpu63_intc 9>; -- riscv,ndev = <224>; -- }; -- - rstgen: reset-controller@7030013000 { - compatible = "sophgo,sg2042-reset"; - reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch b/SPECS/linux-lts-kmhv2/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch new file mode 100644 index 0000000000..1a8e836f5a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch @@ -0,0 +1,51 @@ +From 4274a55a8dac98543297e2416ea7c7f40c4f641a Mon Sep 17 00:00:00 2001 +From: Javier Martinez Canillas +Date: Sat, 6 Dec 2025 14:44:54 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Define fixed regulators + for Milk-V Jupiter + +Define the DC power input and the 4v power as fixed regulator supplies. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20251206134532.1741648-3-javierm@redhat.com +Signed-off-by: Yixun Lan +(cherry picked from commit ae9d03f8aec76c1bff21083b67c211238d7c57b1) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index aa425f02c1f4..5babed4d7094 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -20,6 +20,25 @@ aliases { + chosen { + stdout-path = "serial0"; + }; ++ ++ reg_dc_in: dc-in-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_in_12v"; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_vcc_4v: vcc-4v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_4v"; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <®_dc_in>; ++ }; + }; + + ð0 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0076-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch b/SPECS/linux-lts-kmhv2/0076-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch deleted file mode 100644 index 568815bda9..0000000000 --- a/SPECS/linux-lts-kmhv2/0076-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch +++ /dev/null @@ -1,216 +0,0 @@ -From bc212a22b04c56496e4f069f7f3fca8cffd37025 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Tue, 13 Jan 2026 10:38:27 +0800 -Subject: [PATCH 076/467] UPSTREAM: riscv: dts: sophgo: fix the node order of - SG2042 peripheral - -In sg2042.dtsi, some peripheral device node does not follow the -address order. Reorder them in ascending order by address. - -Reviewed-by: Chen Wang -Link: https://lore.kernel.org/r/20260113023828.790136-2-inochiama@gmail.com -Signed-off-by: Inochi Amaoto -Signed-off-by: Chen Wang -Signed-off-by: Chen Wang -(cherry picked from commit ebb87dd74c34a76e1e93041e9329cf9269be35ed) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042.dtsi | 176 ++++++++++++------------- - 1 file changed, 88 insertions(+), 88 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -index e6891f95d479..9fddf3f0b3b9 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -@@ -264,94 +264,6 @@ clkgen: clock-controller@7030012000 { - #clock-cells = <1>; - }; - -- pcie_rc0: pcie@7060000000 { -- compatible = "sophgo,sg2042-pcie-host"; -- device_type = "pci"; -- reg = <0x70 0x60000000 0x0 0x00800000>, -- <0x40 0x00000000 0x0 0x00001000>; -- reg-names = "reg", "cfg"; -- linux,pci-domain = <0>; -- #address-cells = <3>; -- #size-cells = <2>; -- ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, -- <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, -- <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, -- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, -- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; -- bus-range = <0x0 0xff>; -- vendor-id = <0x1f1c>; -- device-id = <0x2042>; -- cdns,no-bar-match-nbits = <48>; -- msi-parent = <&msi>; -- status = "disabled"; -- }; -- -- pcie_rc1: pcie@7060800000 { -- compatible = "sophgo,sg2042-pcie-host"; -- device_type = "pci"; -- reg = <0x70 0x60800000 0x0 0x00800000>, -- <0x44 0x00000000 0x0 0x00001000>; -- reg-names = "reg", "cfg"; -- linux,pci-domain = <1>; -- #address-cells = <3>; -- #size-cells = <2>; -- ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, -- <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, -- <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, -- <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, -- <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; -- bus-range = <0x0 0xff>; -- vendor-id = <0x1f1c>; -- device-id = <0x2042>; -- cdns,no-bar-match-nbits = <48>; -- msi-parent = <&msi>; -- status = "disabled"; -- }; -- -- pcie_rc2: pcie@7062000000 { -- compatible = "sophgo,sg2042-pcie-host"; -- device_type = "pci"; -- reg = <0x70 0x62000000 0x0 0x00800000>, -- <0x48 0x00000000 0x0 0x00001000>; -- reg-names = "reg", "cfg"; -- linux,pci-domain = <2>; -- #address-cells = <3>; -- #size-cells = <2>; -- ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, -- <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, -- <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, -- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, -- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; -- bus-range = <0x0 0xff>; -- vendor-id = <0x1f1c>; -- device-id = <0x2042>; -- cdns,no-bar-match-nbits = <48>; -- msi-parent = <&msi>; -- status = "disabled"; -- }; -- -- pcie_rc3: pcie@7062800000 { -- compatible = "sophgo,sg2042-pcie-host"; -- device_type = "pci"; -- reg = <0x70 0x62800000 0x0 0x00800000>, -- <0x4c 0x00000000 0x0 0x00001000>; -- reg-names = "reg", "cfg"; -- linux,pci-domain = <3>; -- #address-cells = <3>; -- #size-cells = <2>; -- ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, -- <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, -- <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, -- <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, -- <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; -- bus-range = <0x0 0xff>; -- vendor-id = <0x1f1c>; -- device-id = <0x2042>; -- cdns,no-bar-match-nbits = <48>; -- msi-parent = <&msi>; -- status = "disabled"; -- }; -- - rstgen: reset-controller@7030013000 { - compatible = "sophgo,sg2042-reset"; - reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; -@@ -486,5 +398,93 @@ sd: mmc@704002b000 { - "timer"; - status = "disabled"; - }; -+ -+ pcie_rc0: pcie@7060000000 { -+ compatible = "sophgo,sg2042-pcie-host"; -+ device_type = "pci"; -+ reg = <0x70 0x60000000 0x0 0x00800000>, -+ <0x40 0x00000000 0x0 0x00001000>; -+ reg-names = "reg", "cfg"; -+ linux,pci-domain = <0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, -+ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, -+ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, -+ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, -+ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; -+ bus-range = <0x0 0xff>; -+ vendor-id = <0x1f1c>; -+ device-id = <0x2042>; -+ cdns,no-bar-match-nbits = <48>; -+ msi-parent = <&msi>; -+ status = "disabled"; -+ }; -+ -+ pcie_rc1: pcie@7060800000 { -+ compatible = "sophgo,sg2042-pcie-host"; -+ device_type = "pci"; -+ reg = <0x70 0x60800000 0x0 0x00800000>, -+ <0x44 0x00000000 0x0 0x00001000>; -+ reg-names = "reg", "cfg"; -+ linux,pci-domain = <1>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, -+ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, -+ <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, -+ <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, -+ <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; -+ bus-range = <0x0 0xff>; -+ vendor-id = <0x1f1c>; -+ device-id = <0x2042>; -+ cdns,no-bar-match-nbits = <48>; -+ msi-parent = <&msi>; -+ status = "disabled"; -+ }; -+ -+ pcie_rc2: pcie@7062000000 { -+ compatible = "sophgo,sg2042-pcie-host"; -+ device_type = "pci"; -+ reg = <0x70 0x62000000 0x0 0x00800000>, -+ <0x48 0x00000000 0x0 0x00001000>; -+ reg-names = "reg", "cfg"; -+ linux,pci-domain = <2>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, -+ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, -+ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, -+ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, -+ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; -+ bus-range = <0x0 0xff>; -+ vendor-id = <0x1f1c>; -+ device-id = <0x2042>; -+ cdns,no-bar-match-nbits = <48>; -+ msi-parent = <&msi>; -+ status = "disabled"; -+ }; -+ -+ pcie_rc3: pcie@7062800000 { -+ compatible = "sophgo,sg2042-pcie-host"; -+ device_type = "pci"; -+ reg = <0x70 0x62800000 0x0 0x00800000>, -+ <0x4c 0x00000000 0x0 0x00001000>; -+ reg-names = "reg", "cfg"; -+ linux,pci-domain = <3>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, -+ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, -+ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, -+ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, -+ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; -+ bus-range = <0x0 0xff>; -+ vendor-id = <0x1f1c>; -+ device-id = <0x2042>; -+ cdns,no-bar-match-nbits = <48>; -+ msi-parent = <&msi>; -+ status = "disabled"; -+ }; - }; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux-lts-kmhv2/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch new file mode 100644 index 0000000000..1be8407564 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch @@ -0,0 +1,145 @@ +From 0af31fdff636f13c96b48c14fe2dce73dbf55dfd Mon Sep 17 00:00:00 2001 +From: Javier Martinez Canillas +Date: Sat, 6 Dec 2025 14:44:55 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Define the P1 PMIC + regulators for Milk-V Jupiter + +Define the SpacemiT P1 PMIC voltage regulators and their constraints. + +The power management hardware design on the Milk-V Jupiter is identical to +the Banana Pi BPI-F3, so the DT Nodes were taken from k1-bananapi-f3.dts. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20251206134532.1741648-4-javierm@redhat.com +Signed-off-by: Yixun Lan +(cherry picked from commit 7d307daa12b15a97269f577d5dcf50518758b568) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 110 ++++++++++++++++++ + 1 file changed, 110 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 5babed4d7094..800a112d5d70 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -95,6 +95,116 @@ &i2c8 { + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; + status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ vin-supply = <®_vcc_4v>; ++ ++ regulators { ++ buck1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3_1v8: buck3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ aldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ dldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo7 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ }; ++ }; + }; + + &uart0 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch b/SPECS/linux-lts-kmhv2/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch new file mode 100644 index 0000000000..51bfee722a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch @@ -0,0 +1,152 @@ +From 0cb6f99b1dee1c78c2cb66de8612480e505be4b7 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Thu, 18 Dec 2025 09:12:27 -0600 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: Add SpacemiT + PCIe/combo PHY + +Add the Device Tree binding for the PCIe/USB 3.0 combo PHY found in +the SpacemiT K1 SoC. This is one of three PCIe PHYs, and is unusual +in that only the combo PHY can perform a calibration step needed to +determine settings used by the other two PCIe PHYs. + +Calibration must be done with the combo PHY in PCIe mode, and to allow +this to occur independent of the eventual use for the PHY (PCIe or USB) +some PCIe-related properties must be supplied: clocks; resets; and a +syscon phandle. + +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Alex Elder +Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1] +Tested-by: Yixun Lan +Link: https://patch.msgid.link/20251218151235.454997-2-elder@riscstar.com +Signed-off-by: Vinod Koul +(cherry picked from commit f6194de7df023ecfd5156caf8e2762487be07ef7) +Signed-off-by: Han Gao +--- + .../bindings/phy/spacemit,k1-combo-phy.yaml | 114 ++++++++++++++++++ + 1 file changed, 114 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml +new file mode 100644 +index 000000000000..b59476cd78b5 +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml +@@ -0,0 +1,114 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 PCIe/USB3 Combo PHY ++ ++maintainers: ++ - Alex Elder ++ ++description: > ++ Of the three PHYs on the SpacemiT K1 SoC capable of being used for ++ PCIe, one is a combo PHY that can also be configured for use by a ++ USB 3 controller. Using PCIe or USB 3 is a board design decision. ++ ++ The combo PHY is also the only PCIe PHY that is able to determine ++ PCIe calibration values to use, and this must be determined before ++ the other two PCIe PHYs can be used. This calibration must be ++ performed with the combo PHY in PCIe mode, and is this is done ++ when the combo PHY is probed. ++ ++ The combo PHY uses an external oscillator as a reference clock. ++ During normal operation, the PCIe or USB port driver is responsible ++ for ensuring all other clocks needed by a PHY are enabled, and all ++ resets affecting the PHY are deasserted. However, for the combo ++ PHY to perform calibration independent of whether it's later used ++ for PCIe or USB, all PCIe mode clocks and resets must be defined. ++ ++properties: ++ compatible: ++ const: spacemit,k1-combo-phy ++ ++ reg: ++ items: ++ - description: PHY control registers ++ ++ clocks: ++ items: ++ - description: External oscillator used by the PHY PLL ++ - description: DWC PCIe Data Bus Interface (DBI) clock ++ - description: DWC PCIe application AXI-bus Master interface clock ++ - description: DWC PCIe application AXI-bus slave interface clock ++ ++ clock-names: ++ items: ++ - const: refclk ++ - const: dbi ++ - const: mstr ++ - const: slv ++ ++ resets: ++ items: ++ - description: PHY reset; remains deasserted after initialization ++ - description: DWC PCIe Data Bus Interface (DBI) reset ++ - description: DWC PCIe application AXI-bus Master interface reset ++ - description: DWC PCIe application AXI-bus slave interface reset ++ ++ reset-names: ++ items: ++ - const: phy ++ - const: dbi ++ - const: mstr ++ - const: slv ++ ++ spacemit,apmu: ++ description: ++ A phandle that refers to the APMU system controller, whose ++ regmap is used in setting the mode ++ $ref: /schemas/types.yaml#/definitions/phandle ++ ++ "#phy-cells": ++ const: 1 ++ description: ++ The argument value (PHY_TYPE_PCIE or PHY_TYPE_USB3) determines ++ whether the PHY operates in PCIe or USB3 mode. ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - spacemit,apmu ++ - "#phy-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ phy@c0b10000 { ++ compatible = "spacemit,k1-combo-phy"; ++ reg = <0xc0b10000 0x1000>; ++ clocks = <&vctcxo_24m>, ++ <&syscon_apmu CLK_PCIE0_DBI>, ++ <&syscon_apmu CLK_PCIE0_MASTER>, ++ <&syscon_apmu CLK_PCIE0_SLAVE>; ++ clock-names = "refclk", ++ "dbi", ++ "mstr", ++ "slv"; ++ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, ++ <&syscon_apmu RESET_PCIE0_DBI>, ++ <&syscon_apmu RESET_PCIE0_MASTER>, ++ <&syscon_apmu RESET_PCIE0_SLAVE>; ++ reset-names = "phy", ++ "dbi", ++ "mstr", ++ "slv"; ++ spacemit,apmu = <&syscon_apmu>; ++ #phy-cells = <1>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0077-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux-lts-kmhv2/0077-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch deleted file mode 100644 index 7f626bb434..0000000000 --- a/SPECS/linux-lts-kmhv2/0077-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 424c28f6634db764db1cd2faa2f13e276f698b61 Mon Sep 17 00:00:00 2001 -From: Javier Martinez Canillas -Date: Sat, 6 Dec 2025 14:44:53 +0100 -Subject: [PATCH 077/467] UPSTREAM: riscv: dts: spacemit: Enable i2c8 adapter - for Milk-V Jupiter - -The adapter is used to access the SpacemiT P1 PMIC present in this board. - -Signed-off-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20251206134532.1741648-2-javierm@redhat.com -Signed-off-by: Yixun Lan -(cherry picked from commit f33ccc2316304f3a71e40e53f1568e75042b0a4b) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 28afd39b28da..aa425f02c1f4 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -72,6 +72,12 @@ &pdma { - status = "okay"; - }; - -+&i2c8 { -+ pinctrl-0 = <&i2c8_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch b/SPECS/linux-lts-kmhv2/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch new file mode 100644 index 0000000000..9b069cb469 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch @@ -0,0 +1,103 @@ +From 69d5a6d06db546fbe5f911a20eff130b7eb44927 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Thu, 18 Dec 2025 09:12:28 -0600 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: Introduce PCIe PHY + +Add the Device Tree binding for two PCIe PHYs present on the SpacemiT +K1 SoC. These PHYs are dependent on a separate combo PHY, which +determines at probe time the calibration values used by the PCIe-only +PHYs. + +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Alex Elder +Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1] +Tested-by: Yixun Lan +Link: https://patch.msgid.link/20251218151235.454997-3-elder@riscstar.com +Signed-off-by: Vinod Koul +(cherry picked from commit 326a278a3682d390269699f68e597b5ef5a57d26) +Signed-off-by: Han Gao +--- + .../bindings/phy/spacemit,k1-pcie-phy.yaml | 71 +++++++++++++++++++ + 1 file changed, 71 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml +new file mode 100644 +index 000000000000..019b28349be7 +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml +@@ -0,0 +1,71 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 PCIe PHY ++ ++maintainers: ++ - Alex Elder ++ ++description: > ++ Two PHYs on the SpacemiT K1 SoC used for only for PCIe. These ++ PHYs must be configured using calibration values that are ++ determined by a third "combo PHY". The combo PHY determines ++ these calibration values during probe so they can be used for ++ the two PCIe-only PHYs. ++ ++ The PHY uses an external oscillator as a reference clock. During ++ normal operation, the PCIe host driver is responsible for ensuring ++ all other clocks needed by a PHY are enabled, and all resets ++ affecting the PHY are deasserted. ++ ++properties: ++ compatible: ++ const: spacemit,k1-pcie-phy ++ ++ reg: ++ items: ++ - description: PHY control registers ++ ++ clocks: ++ items: ++ - description: External oscillator used by the PHY PLL ++ ++ clock-names: ++ const: refclk ++ ++ resets: ++ items: ++ - description: PHY reset; remains deasserted after initialization ++ ++ reset-names: ++ const: phy ++ ++ "#phy-cells": ++ const: 0 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - "#phy-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ phy@c0c10000 { ++ compatible = "spacemit,k1-pcie-phy"; ++ reg = <0xc0c10000 0x1000>; ++ clocks = <&vctcxo_24m>; ++ clock-names = "refclk"; ++ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; ++ reset-names = "phy"; ++ #phy-cells = <0>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0078-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch b/SPECS/linux-lts-kmhv2/0078-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch deleted file mode 100644 index 707ca5b47b..0000000000 --- a/SPECS/linux-lts-kmhv2/0078-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 02cddb709249c02e0e30f24ad102a5b7190d26c2 Mon Sep 17 00:00:00 2001 -From: Javier Martinez Canillas -Date: Sat, 6 Dec 2025 14:44:54 +0100 -Subject: [PATCH 078/467] UPSTREAM: riscv: dts: spacemit: Define fixed - regulators for Milk-V Jupiter - -Define the DC power input and the 4v power as fixed regulator supplies. - -Signed-off-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20251206134532.1741648-3-javierm@redhat.com -Signed-off-by: Yixun Lan -(cherry picked from commit ae9d03f8aec76c1bff21083b67c211238d7c57b1) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index aa425f02c1f4..5babed4d7094 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -20,6 +20,25 @@ aliases { - chosen { - stdout-path = "serial0"; - }; -+ -+ reg_dc_in: dc-in-12v { -+ compatible = "regulator-fixed"; -+ regulator-name = "dc_in_12v"; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_vcc_4v: vcc-4v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_4v"; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <®_dc_in>; -+ }; - }; - - ð0 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch b/SPECS/linux-lts-kmhv2/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch new file mode 100644 index 0000000000..78fc295801 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch @@ -0,0 +1,758 @@ +From ec3144e3a9c21e5c60712fe8b72eb68e9f8c120f Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Thu, 18 Dec 2025 09:12:29 -0600 +Subject: [RUYI PATCH] UPSTREAM: phy: spacemit: Introduce PCIe/combo PHY + +Introduce a driver that supports three PHYs found on the SpacemiT +K1 SoC. The first PHY is a combo PHY that can be configured for +use for either USB 3 or PCIe. The other two PHYs support PCIe +only. + +All three PHYs must be programmed with an 8 bit receiver termination +value, which must be determined dynamically. Only the combo PHY is +able to determine this value. The combo PHY performs a special +calibration step at probe time to discover this, and that value is +used to program each PHY that operates in PCIe mode. The combo +PHY must therefore be probed before either of the PCIe-only PHYs +will be used. + +Each PHY has an internal PLL driven from an external oscillator. +This PLL started when the PHY is first initialized, and stays +on thereafter. + +During normal operation, the USB or PCIe driver using the PHY must +ensure (other) clocks and resets are set up properly. + +However PCIe mode clocks are enabled and resets are de-asserted +temporarily by this driver to perform the calibration step on the +combo PHY. + +Tested-by: Junzhong Pan +Signed-off-by: Alex Elder +Reviewed-by: Neil Armstrong +Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1] +Tested-by: Yixun Lan +Link: https://patch.msgid.link/20251218151235.454997-4-elder@riscstar.com +Signed-off-by: Vinod Koul +(cherry picked from commit 57e920b92724dd568526990c04e79ed54241c5fc) +Signed-off-by: Han Gao +--- + drivers/phy/Kconfig | 11 + + drivers/phy/Makefile | 1 + + drivers/phy/phy-spacemit-k1-pcie.c | 670 +++++++++++++++++++++++++++++ + 3 files changed, 682 insertions(+) + create mode 100644 drivers/phy/phy-spacemit-k1-pcie.c + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index 678dd0452f0a..1984c2e56122 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -101,6 +101,17 @@ config PHY_NXP_PTN3222 + schemes. It supports all three USB 2.0 data rates: Low Speed, Full + Speed and High Speed. + ++config PHY_SPACEMIT_K1_PCIE ++ tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC" ++ depends on ARCH_SPACEMIT || COMPILE_TEST ++ depends on HAS_IOMEM ++ depends on OF ++ select GENERIC_PHY ++ default ARCH_SPACEMIT ++ help ++ Enable support for the PCIe and USB 3 combo PHY and two ++ PCIe-only PHYs used in the SpacemiT K1 SoC. ++ + source "drivers/phy/allwinner/Kconfig" + source "drivers/phy/amlogic/Kconfig" + source "drivers/phy/broadcom/Kconfig" +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index bfb27fb5a494..a206133a3515 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o + obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o + obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o + obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o ++obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-spacemit-k1-pcie.o + obj-y += allwinner/ \ + amlogic/ \ + broadcom/ \ +diff --git a/drivers/phy/phy-spacemit-k1-pcie.c b/drivers/phy/phy-spacemit-k1-pcie.c +new file mode 100644 +index 000000000000..75477bea7f70 +--- /dev/null ++++ b/drivers/phy/phy-spacemit-k1-pcie.c +@@ -0,0 +1,670 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * SpacemiT K1 PCIe and PCIe/USB 3 combo PHY driver ++ * ++ * Copyright (C) 2025 by RISCstar Solutions Corporation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* ++ * Three PCIe ports are supported in the SpacemiT K1 SoC, and this driver ++ * supports their PHYs. ++ * ++ * The PHY for PCIe port A is different from the PHYs for ports B and C: ++ * - It has one lane, while ports B and C have two ++ * - It is a combo PHY can be used for PCIe or USB 3 ++ * - It can automatically calibrate PCIe TX and RX termination settings ++ * ++ * The PHY functionality for PCIe ports B and C is identical: ++ * - They have two PCIe lanes (but can be restricted to 1 via device tree) ++ * - They are used for PCIe only ++ * - They are configured using TX and RX values computed for port A ++ * ++ * A given board is designed to use the combo PHY for either PCIe or USB 3. ++ * Whether the combo PHY is configured for PCIe or USB 3 is specified in ++ * device tree using a phandle plus an argument. The argument indicates ++ * the type (either PHY_TYPE_PCIE or PHY_TYPE_USB3). ++ * ++ * Each PHY has a reset that it gets and deasserts during initialization. ++ * Each depends also on other clocks and resets provided by the controller ++ * hardware (PCIe or USB) it is associated with. The controller drivers ++ * are required to enable any clocks and de-assert any resets that affect ++ * PHY operation. In addition each PHY implements an internal PLL, driven ++ * by an external (24 MHz) oscillator. ++ * ++ * PCIe PHYs must be programmed with RX and TX calibration values. The ++ * combo PHY is the only one that can determine these values. They are ++ * determined by temporarily enabling the combo PHY in PCIe mode at probe ++ * time (if necessary). This calibration only needs to be done once, and ++ * when it has completed the TX and RX values are saved. ++ * ++ * To allow the combo PHY to be enabled for calibration, the resets and ++ * clocks it uses in PCIe mode must be supplied. ++ */ ++ ++struct k1_pcie_phy { ++ struct device *dev; /* PHY provider device */ ++ struct phy *phy; ++ void __iomem *regs; ++ u32 pcie_lanes; /* Max (1 or 2) unless limited by DT */ ++ struct clk *pll; ++ struct clk_hw pll_hw; /* Private PLL clock */ ++ ++ /* The remaining fields are only used for the combo PHY */ ++ u32 type; /* PHY_TYPE_PCIE or PHY_TYPE_USB3 */ ++ struct regmap *pmu; /* MMIO regmap (no errors) */ ++}; ++ ++#define CALIBRATION_TIMEOUT 500000 /* For combo PHY (usec) */ ++#define PLL_TIMEOUT 500000 /* For PHY PLL lock (usec) */ ++#define POLL_DELAY 500 /* Time between polls (usec) */ ++ ++/* Selecting the combo PHY operating mode requires APMU regmap access */ ++#define SYSCON_APMU "spacemit,apmu" ++ ++/* PMU space, for selecting between PCIe and USB 3 mode (combo PHY only) */ ++ ++#define PMUA_USB_PHY_CTRL0 0x0110 ++#define COMBO_PHY_SEL BIT(3) /* 0: PCIe; 1: USB 3 */ ++ ++#define PCIE_CLK_RES_CTRL 0x03cc ++#define PCIE_APP_HOLD_PHY_RST BIT(30) ++ ++/* PHY register space */ ++ ++/* Offset between lane 0 and lane 1 registers when there are two */ ++#define PHY_LANE_OFFSET 0x0400 ++ ++/* PHY PLL configuration */ ++#define PCIE_PU_ADDR_CLK_CFG 0x0008 ++#define PLL_READY BIT(0) /* read-only */ ++#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) ++#define TIMER_ADJ_USB 0x2 ++#define TIMER_ADJ_PCIE 0x6 ++#define CFG_SW_PHY_INIT_DONE BIT(11) /* We set after PLL config */ ++ ++#define PCIE_RC_DONE_STATUS 0x0018 ++#define CFG_FORCE_RCV_RETRY BIT(10) /* Used for PCIe */ ++ ++/* PCIe PHY lane calibration; assumes 24MHz input clock */ ++#define PCIE_RC_CAL_REG2 0x0020 ++#define RC_CAL_TOGGLE BIT(22) ++#define CLKSEL GENMASK(31, 29) ++#define CLKSEL_24M 0x3 ++ ++/* Additional PHY PLL configuration (USB 3 and PCIe) */ ++#define PCIE_PU_PLL_1 0x0048 ++#define REF_100_WSSC BIT(12) /* 1: input is 100MHz, SSC */ ++#define FREF_SEL GENMASK(15, 13) ++#define FREF_24M 0x1 ++#define SSC_DEP_SEL GENMASK(19, 16) ++#define SSC_DEP_NONE 0x0 ++#define SSC_DEP_5000PPM 0xa ++ ++/* PCIe PHY configuration */ ++#define PCIE_PU_PLL_2 0x004c ++#define GEN_REF100 BIT(4) /* 1: generate 100MHz clk */ ++ ++#define PCIE_RX_REG1 0x0050 ++#define EN_RTERM BIT(3) ++#define AFE_RTERM_REG GENMASK(11, 8) ++ ++#define PCIE_RX_REG2 0x0054 ++#define RX_RTERM_SEL BIT(5) /* 0: use AFE_RTERM_REG value */ ++ ++#define PCIE_LTSSM_DIS_ENTRY 0x005c ++#define CFG_REFCLK_MODE GENMASK(9, 8) ++#define RFCLK_MODE_DRIVER 0x1 ++#define OVRD_REFCLK_MODE BIT(10) /* 1: use CFG_RFCLK_MODE */ ++ ++#define PCIE_TX_REG1 0x0064 ++#define TX_RTERM_REG GENMASK(15, 12) ++#define TX_RTERM_SEL BIT(25) /* 1: use TX_RTERM_REG */ ++ ++/* Zeroed for the combo PHY operating in USB mode */ ++#define USB3_TEST_CTRL 0x0068 ++ ++/* PHY calibration values, determined by the combo PHY at probe time */ ++#define PCIE_RCAL_RESULT 0x0084 /* Port A PHY only */ ++#define RTERM_VALUE_RX GENMASK(3, 0) ++#define RTERM_VALUE_TX GENMASK(7, 4) ++#define R_TUNE_DONE BIT(10) ++ ++static u32 k1_phy_rterm = ~0; /* Invalid initial value */ ++ ++/* Save the RX and TX receiver termination values */ ++static void k1_phy_rterm_set(u32 val) ++{ ++ k1_phy_rterm = val & (RTERM_VALUE_RX | RTERM_VALUE_TX); ++} ++ ++static bool k1_phy_rterm_valid(void) ++{ ++ /* Valid if no bits outside those we care about are set */ ++ return !(k1_phy_rterm & ~(RTERM_VALUE_RX | RTERM_VALUE_TX)); ++} ++ ++static u32 k1_phy_rterm_rx(void) ++{ ++ return FIELD_GET(RTERM_VALUE_RX, k1_phy_rterm); ++} ++ ++static u32 k1_phy_rterm_tx(void) ++{ ++ return FIELD_GET(RTERM_VALUE_TX, k1_phy_rterm); ++} ++ ++/* Only the combo PHY has a PMU pointer defined */ ++static bool k1_phy_port_a(struct k1_pcie_phy *k1_phy) ++{ ++ return !!k1_phy->pmu; ++} ++ ++/* The PLL clocks are driven by the external oscillator */ ++static const struct clk_parent_data k1_pcie_phy_data[] = { ++ { .fw_name = "refclk", }, ++}; ++ ++static struct k1_pcie_phy *clk_hw_to_k1_phy(struct clk_hw *clk_hw) ++{ ++ return container_of(clk_hw, struct k1_pcie_phy, pll_hw); ++} ++ ++/* USB mode only works on the combo PHY, which has only one lane */ ++static void k1_pcie_phy_pll_prepare_usb(struct k1_pcie_phy *k1_phy) ++{ ++ void __iomem *regs = k1_phy->regs; ++ u32 val; ++ ++ val = readl(regs + PCIE_PU_ADDR_CLK_CFG); ++ val &= ~CFG_INTERNAL_TIMER_ADJ; ++ val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_USB); ++ writel(val, regs + PCIE_PU_ADDR_CLK_CFG); ++ ++ val = readl(regs + PCIE_PU_PLL_1); ++ val &= ~SSC_DEP_SEL; ++ val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_5000PPM); ++ writel(val, regs + PCIE_PU_PLL_1); ++} ++ ++/* Perform PCIe-specific register updates before starting the PLL clock */ ++static void k1_pcie_phy_pll_prepare_pcie(struct k1_pcie_phy *k1_phy) ++{ ++ void __iomem *regs = k1_phy->regs; ++ u32 val; ++ u32 i; ++ ++ for (i = 0; i < k1_phy->pcie_lanes; i++) { ++ val = readl(regs + PCIE_PU_ADDR_CLK_CFG); ++ val &= ~CFG_INTERNAL_TIMER_ADJ; ++ val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_PCIE); ++ writel(val, regs + PCIE_PU_ADDR_CLK_CFG); ++ ++ regs += PHY_LANE_OFFSET; /* Next lane */ ++ } ++ ++ regs = k1_phy->regs; ++ val = readl(regs + PCIE_RC_DONE_STATUS); ++ val |= CFG_FORCE_RCV_RETRY; ++ writel(val, regs + PCIE_RC_DONE_STATUS); ++ ++ val = readl(regs + PCIE_PU_PLL_1); ++ val &= ~SSC_DEP_SEL; ++ val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_NONE); ++ writel(val, regs + PCIE_PU_PLL_1); ++ ++ val = readl(regs + PCIE_PU_PLL_2); ++ val |= GEN_REF100; /* Enable 100 MHz PLL output clock */ ++ writel(val, regs + PCIE_PU_PLL_2); ++} ++ ++static int k1_pcie_phy_pll_prepare(struct clk_hw *clk_hw) ++{ ++ struct k1_pcie_phy *k1_phy = clk_hw_to_k1_phy(clk_hw); ++ void __iomem *regs = k1_phy->regs; ++ u32 val; ++ u32 i; ++ ++ if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3) ++ k1_pcie_phy_pll_prepare_usb(k1_phy); ++ else ++ k1_pcie_phy_pll_prepare_pcie(k1_phy); ++ ++ /* ++ * Disable 100 MHz input reference with spread-spectrum ++ * clocking and select the 24 MHz clock input frequency ++ */ ++ val = readl(regs + PCIE_PU_PLL_1); ++ val &= ~REF_100_WSSC; ++ val &= ~FREF_SEL; ++ val |= FIELD_PREP(FREF_SEL, FREF_24M); ++ writel(val, regs + PCIE_PU_PLL_1); ++ ++ /* Mark PLL configuration done on all lanes */ ++ for (i = 0; i < k1_phy->pcie_lanes; i++) { ++ val = readl(regs + PCIE_PU_ADDR_CLK_CFG); ++ val |= CFG_SW_PHY_INIT_DONE; ++ writel(val, regs + PCIE_PU_ADDR_CLK_CFG); ++ ++ regs += PHY_LANE_OFFSET; /* Next lane */ ++ } ++ ++ /* ++ * Wait for indication the PHY PLL is locked. Lanes for ports ++ * B and C share a PLL, so it's enough to sample just lane 0. ++ */ ++ return readl_poll_timeout(k1_phy->regs + PCIE_PU_ADDR_CLK_CFG, ++ val, val & PLL_READY, ++ POLL_DELAY, PLL_TIMEOUT); ++} ++ ++/* Prepare implies enable, and once enabled, it's always on */ ++static const struct clk_ops k1_pcie_phy_pll_ops = { ++ .prepare = k1_pcie_phy_pll_prepare, ++}; ++ ++/* We represent the PHY PLL as a private clock */ ++static int k1_pcie_phy_pll_setup(struct k1_pcie_phy *k1_phy) ++{ ++ struct clk_hw *hw = &k1_phy->pll_hw; ++ struct device *dev = k1_phy->dev; ++ struct clk_init_data init = { }; ++ char *name; ++ int ret; ++ ++ name = kasprintf(GFP_KERNEL, "pcie%u_phy_pll", k1_phy->phy->id); ++ if (!name) ++ return -ENOMEM; ++ ++ init.name = name; ++ init.ops = &k1_pcie_phy_pll_ops; ++ init.parent_data = k1_pcie_phy_data; ++ init.num_parents = ARRAY_SIZE(k1_pcie_phy_data); ++ ++ hw->init = &init; ++ ++ ret = devm_clk_hw_register(dev, hw); ++ ++ kfree(name); /* __clk_register() duplicates the name we provide */ ++ ++ if (ret) ++ return ret; ++ ++ k1_phy->pll = devm_clk_hw_get_clk(dev, hw, "pll"); ++ if (IS_ERR(k1_phy->pll)) ++ return PTR_ERR(k1_phy->pll); ++ ++ return 0; ++} ++ ++/* Select PCIe or USB 3 mode for the combo PHY. */ ++static void k1_combo_phy_sel(struct k1_pcie_phy *k1_phy, bool usb) ++{ ++ struct regmap *pmu = k1_phy->pmu; ++ ++ /* Only change it if it's not already in the desired state */ ++ if (!regmap_test_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL) == usb) ++ regmap_assign_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL, usb); ++} ++ ++static void k1_pcie_phy_init_pcie(struct k1_pcie_phy *k1_phy) ++{ ++ u32 rx_rterm = k1_phy_rterm_rx(); ++ u32 tx_rterm = k1_phy_rterm_tx(); ++ void __iomem *regs; ++ u32 val; ++ int i; ++ ++ /* For the combo PHY, set PHY to PCIe mode */ ++ if (k1_phy_port_a(k1_phy)) ++ k1_combo_phy_sel(k1_phy, false); ++ ++ regs = k1_phy->regs; ++ for (i = 0; i < k1_phy->pcie_lanes; i++) { ++ val = readl(regs + PCIE_RX_REG1); ++ ++ /* Set RX analog front-end receiver termination value */ ++ val &= ~AFE_RTERM_REG; ++ val |= FIELD_PREP(AFE_RTERM_REG, rx_rterm); ++ ++ /* And enable refclock receiver termination */ ++ val |= EN_RTERM; ++ writel(val, regs + PCIE_RX_REG1); ++ ++ val = readl(regs + PCIE_RX_REG2); ++ /* Use PCIE_RX_REG1 AFE_RTERM_REG value */ ++ val &= ~RX_RTERM_SEL; ++ writel(val, regs + PCIE_RX_REG2); ++ ++ val = readl(regs + PCIE_TX_REG1); ++ ++ /* Set TX driver termination value */ ++ val &= ~TX_RTERM_REG; ++ val |= FIELD_PREP(TX_RTERM_REG, tx_rterm); ++ ++ /* Use PCIE_TX_REG1 TX_RTERM_REG value */ ++ val |= TX_RTERM_SEL; ++ writel(val, regs + PCIE_TX_REG1); ++ ++ /* Set the input clock to 24 MHz, and clear RC_CAL_TOGGLE */ ++ val = readl(regs + PCIE_RC_CAL_REG2); ++ val &= CLKSEL; ++ val |= FIELD_PREP(CLKSEL, CLKSEL_24M); ++ val &= ~RC_CAL_TOGGLE; ++ writel(val, regs + PCIE_RC_CAL_REG2); ++ ++ /* Now trigger recalibration by setting RC_CAL_TOGGLE again */ ++ val |= RC_CAL_TOGGLE; ++ writel(val, regs + PCIE_RC_CAL_REG2); ++ ++ val = readl(regs + PCIE_LTSSM_DIS_ENTRY); ++ /* Override the reference clock; set to refclk driver mode */ ++ val |= OVRD_REFCLK_MODE; ++ val &= ~CFG_REFCLK_MODE; ++ val |= FIELD_PREP(CFG_REFCLK_MODE, RFCLK_MODE_DRIVER); ++ writel(val, regs + PCIE_LTSSM_DIS_ENTRY); ++ ++ regs += PHY_LANE_OFFSET; /* Next lane */ ++ } ++} ++ ++/* Only called for combo PHY */ ++static void k1_pcie_phy_init_usb(struct k1_pcie_phy *k1_phy) ++{ ++ k1_combo_phy_sel(k1_phy, true); ++ ++ /* We're not doing any testing */ ++ writel(0, k1_phy->regs + USB3_TEST_CTRL); ++} ++ ++static int k1_pcie_phy_init(struct phy *phy) ++{ ++ struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy); ++ ++ /* Note: port type is only valid for port A (both checks needed) */ ++ if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3) ++ k1_pcie_phy_init_usb(k1_phy); ++ else ++ k1_pcie_phy_init_pcie(k1_phy); ++ ++ ++ return clk_prepare_enable(k1_phy->pll); ++} ++ ++static int k1_pcie_phy_exit(struct phy *phy) ++{ ++ struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy); ++ ++ clk_disable_unprepare(k1_phy->pll); ++ ++ return 0; ++} ++ ++static const struct phy_ops k1_pcie_phy_ops = { ++ .init = k1_pcie_phy_init, ++ .exit = k1_pcie_phy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++/* ++ * Get values needed for calibrating PHYs operating in PCIe mode. Only ++ * the combo PHY is able to do this, and its calibration values are used ++ * for configuring all PCIe PHYs. ++ * ++ * We always need to de-assert the "global" reset on the combo PHY, ++ * because the USB driver depends on it. If used for PCIe, that driver ++ * will (also) de-assert this, but by leaving it de-asserted for the ++ * combo PHY, the USB driver doesn't have to do this. Note: although ++ * SpacemiT refers to this as the global reset, we name the "phy" reset. ++ * ++ * In addition, we guarantee the APP_HOLD_PHY_RESET bit is clear for the ++ * combo PHY, so the USB driver doesn't have to manage that either. The ++ * PCIe driver is free to change this bit for normal operation. ++ * ++ * Calibration only needs to be done once. It's possible calibration has ++ * already completed (e.g., it might have happened in the boot loader, or ++ * -EPROBE_DEFER might result in this function being called again). So we ++ * check that early too, to avoid doing it more than once. ++ * ++ * Otherwise we temporarily power up the PHY using the PCIe app clocks ++ * and resets, wait for the hardware to indicate calibration is done, ++ * grab the value, then shut the PHY down again. ++ */ ++static int k1_pcie_combo_phy_calibrate(struct k1_pcie_phy *k1_phy) ++{ ++ struct reset_control_bulk_data resets[] = { ++ { .id = "dbi", }, ++ { .id = "mstr", }, ++ { .id = "slv", }, ++ }; ++ struct clk_bulk_data clocks[] = { ++ { .id = "dbi", }, ++ { .id = "mstr", }, ++ { .id = "slv", }, ++ }; ++ struct device *dev = k1_phy->dev; ++ int ret = 0; ++ int val; ++ ++ /* Nothing to do if we already set the receiver termination value */ ++ if (k1_phy_rterm_valid()) ++ return 0; ++ ++ /* ++ * We also guarantee the APP_HOLD_PHY_RESET bit is clear. We can ++ * leave this bit clear even if an error happens below. ++ */ ++ regmap_assign_bits(k1_phy->pmu, PCIE_CLK_RES_CTRL, ++ PCIE_APP_HOLD_PHY_RST, false); ++ ++ /* If the calibration already completed (e.g. by U-Boot), we're done */ ++ val = readl(k1_phy->regs + PCIE_RCAL_RESULT); ++ if (val & R_TUNE_DONE) ++ goto out_tune_done; ++ ++ /* Put the PHY into PCIe mode */ ++ k1_combo_phy_sel(k1_phy, false); ++ ++ /* Get and enable the PCIe app clocks */ ++ ret = clk_bulk_get(dev, ARRAY_SIZE(clocks), clocks); ++ if (ret < 0) ++ goto out_tune_done; ++ ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); ++ if (ret) ++ goto out_put_clocks; ++ ++ /* Get the PCIe application resets (not the PHY reset) */ ++ ret = reset_control_bulk_get_shared(dev, ARRAY_SIZE(resets), resets); ++ if (ret) ++ goto out_disable_clocks; ++ ++ /* De-assert the PCIe application resets */ ++ ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets); ++ if (ret) ++ goto out_put_resets; ++ ++ /* ++ * This is the core activity here. Wait for the hardware to ++ * signal that it has completed calibration/tuning. Once it ++ * has, the register value will contain the values we'll ++ * use to configure PCIe PHYs. ++ */ ++ ret = readl_poll_timeout(k1_phy->regs + PCIE_RCAL_RESULT, ++ val, val & R_TUNE_DONE, ++ POLL_DELAY, CALIBRATION_TIMEOUT); ++ ++ /* Clean up. We're done with the resets and clocks */ ++ reset_control_bulk_assert(ARRAY_SIZE(resets), resets); ++out_put_resets: ++ reset_control_bulk_put(ARRAY_SIZE(resets), resets); ++out_disable_clocks: ++ clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); ++out_put_clocks: ++ clk_bulk_put(ARRAY_SIZE(clocks), clocks); ++out_tune_done: ++ /* If we got the value without timing out, set k1_phy_rterm */ ++ if (!ret) ++ k1_phy_rterm_set(val); ++ ++ return ret; ++} ++ ++static struct phy * ++k1_pcie_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) ++{ ++ struct k1_pcie_phy *k1_phy = dev_get_drvdata(dev); ++ u32 type; ++ ++ /* The argument specifying the PHY mode is required */ ++ if (args->args_count != 1) ++ return ERR_PTR(-EINVAL); ++ ++ /* We only support PCIe and USB 3 mode */ ++ type = args->args[0]; ++ if (type != PHY_TYPE_PCIE && type != PHY_TYPE_USB3) ++ return ERR_PTR(-EINVAL); ++ ++ /* This PHY can only be used once */ ++ if (k1_phy->type != PHY_NONE) ++ return ERR_PTR(-EBUSY); ++ ++ k1_phy->type = type; ++ ++ return k1_phy->phy; ++} ++ ++/* Use the maximum number of PCIe lanes unless limited by device tree */ ++static u32 k1_pcie_num_lanes(struct k1_pcie_phy *k1_phy, bool port_a) ++{ ++ struct device *dev = k1_phy->dev; ++ u32 count = 0; ++ u32 max; ++ int ret; ++ ++ ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &count); ++ if (count == 1) ++ return 1; ++ ++ if (count == 2 && !port_a) ++ return 2; ++ ++ max = port_a ? 1 : 2; ++ if (ret != -EINVAL) ++ dev_warn(dev, "bad lane count %u for port; using %u\n", ++ count, max); ++ ++ return max; ++} ++ ++static int k1_pcie_combo_phy_probe(struct k1_pcie_phy *k1_phy) ++{ ++ struct device *dev = k1_phy->dev; ++ struct regmap *regmap; ++ int ret; ++ ++ /* Setting the PHY mode requires access to the PMU regmap */ ++ regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), SYSCON_APMU); ++ if (IS_ERR(regmap)) ++ return dev_err_probe(dev, PTR_ERR(regmap), "failed to get PMU\n"); ++ k1_phy->pmu = regmap; ++ ++ ret = k1_pcie_combo_phy_calibrate(k1_phy); ++ if (ret) ++ return dev_err_probe(dev, ret, "calibration failed\n"); ++ ++ /* Needed by k1_pcie_combo_phy_xlate(), which also sets k1_phy->type */ ++ dev_set_drvdata(dev, k1_phy); ++ ++ return 0; ++} ++ ++static int k1_pcie_phy_probe(struct platform_device *pdev) ++{ ++ struct phy *(*xlate)(struct device *dev, ++ const struct of_phandle_args *args); ++ struct device *dev = &pdev->dev; ++ struct reset_control *phy_reset; ++ struct phy_provider *provider; ++ struct k1_pcie_phy *k1_phy; ++ bool probing_port_a; ++ int ret; ++ ++ xlate = of_device_get_match_data(dev); ++ probing_port_a = xlate == k1_pcie_combo_phy_xlate; ++ ++ /* Only the combo PHY can calibrate, so it must probe first */ ++ if (!k1_phy_rterm_valid() && !probing_port_a) ++ return -EPROBE_DEFER; ++ ++ k1_phy = devm_kzalloc(dev, sizeof(*k1_phy), GFP_KERNEL); ++ if (!k1_phy) ++ return -ENOMEM; ++ k1_phy->dev = dev; ++ ++ k1_phy->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(k1_phy->regs)) ++ return dev_err_probe(dev, PTR_ERR(k1_phy->regs), ++ "error mapping registers\n"); ++ ++ /* De-assert the PHY (global) reset and leave it that way */ ++ phy_reset = devm_reset_control_get_exclusive_deasserted(dev, "phy"); ++ if (IS_ERR(phy_reset)) ++ return PTR_ERR(phy_reset); ++ ++ if (probing_port_a) { ++ ret = k1_pcie_combo_phy_probe(k1_phy); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "error probing combo phy\n"); ++ } ++ ++ k1_phy->pcie_lanes = k1_pcie_num_lanes(k1_phy, probing_port_a); ++ ++ k1_phy->phy = devm_phy_create(dev, NULL, &k1_pcie_phy_ops); ++ if (IS_ERR(k1_phy->phy)) ++ return dev_err_probe(dev, PTR_ERR(k1_phy->phy), ++ "error creating phy\n"); ++ phy_set_drvdata(k1_phy->phy, k1_phy); ++ ++ ret = k1_pcie_phy_pll_setup(k1_phy); ++ if (ret) ++ return dev_err_probe(dev, ret, "error initializing clock\n"); ++ ++ provider = devm_of_phy_provider_register(dev, xlate); ++ if (IS_ERR(provider)) ++ return dev_err_probe(dev, PTR_ERR(provider), ++ "error registering provider\n"); ++ return 0; ++} ++ ++static const struct of_device_id k1_pcie_phy_of_match[] = { ++ { .compatible = "spacemit,k1-combo-phy", k1_pcie_combo_phy_xlate, }, ++ { .compatible = "spacemit,k1-pcie-phy", of_phy_simple_xlate, }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, k1_pcie_phy_of_match); ++ ++static struct platform_driver k1_pcie_phy_driver = { ++ .probe = k1_pcie_phy_probe, ++ .driver = { ++ .of_match_table = k1_pcie_phy_of_match, ++ .name = "spacemit-k1-pcie-phy", ++ } ++}; ++module_platform_driver(k1_pcie_phy_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K1 PCIe and USB 3 PHY driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0079-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux-lts-kmhv2/0079-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch deleted file mode 100644 index 2215cfd65e..0000000000 --- a/SPECS/linux-lts-kmhv2/0079-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch +++ /dev/null @@ -1,145 +0,0 @@ -From 160cf483f6a088e178a125f0e3a1e3013726ce5c Mon Sep 17 00:00:00 2001 -From: Javier Martinez Canillas -Date: Sat, 6 Dec 2025 14:44:55 +0100 -Subject: [PATCH 079/467] UPSTREAM: riscv: dts: spacemit: Define the P1 PMIC - regulators for Milk-V Jupiter - -Define the SpacemiT P1 PMIC voltage regulators and their constraints. - -The power management hardware design on the Milk-V Jupiter is identical to -the Banana Pi BPI-F3, so the DT Nodes were taken from k1-bananapi-f3.dts. - -Signed-off-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20251206134532.1741648-4-javierm@redhat.com -Signed-off-by: Yixun Lan -(cherry picked from commit 7d307daa12b15a97269f577d5dcf50518758b568) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 110 ++++++++++++++++++ - 1 file changed, 110 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 5babed4d7094..800a112d5d70 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -95,6 +95,116 @@ &i2c8 { - pinctrl-0 = <&i2c8_cfg>; - pinctrl-names = "default"; - status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin-supply = <®_vcc_4v>; -+ -+ regulators { -+ buck1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3_1v8: buck3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ aldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ dldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo7 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ }; -+ }; - }; - - &uart0 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0080-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch b/SPECS/linux-lts-kmhv2/0080-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch deleted file mode 100644 index 4511c729d0..0000000000 --- a/SPECS/linux-lts-kmhv2/0080-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch +++ /dev/null @@ -1,152 +0,0 @@ -From 506b6beaa759b6c9a08da251acd900242abbc6db Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Thu, 18 Dec 2025 09:12:27 -0600 -Subject: [PATCH 080/467] UPSTREAM: dt-bindings: phy: spacemit: Add SpacemiT - PCIe/combo PHY - -Add the Device Tree binding for the PCIe/USB 3.0 combo PHY found in -the SpacemiT K1 SoC. This is one of three PCIe PHYs, and is unusual -in that only the combo PHY can perform a calibration step needed to -determine settings used by the other two PCIe PHYs. - -Calibration must be done with the combo PHY in PCIe mode, and to allow -this to occur independent of the eventual use for the PHY (PCIe or USB) -some PCIe-related properties must be supplied: clocks; resets; and a -syscon phandle. - -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Alex Elder -Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1] -Tested-by: Yixun Lan -Link: https://patch.msgid.link/20251218151235.454997-2-elder@riscstar.com -Signed-off-by: Vinod Koul -(cherry picked from commit f6194de7df023ecfd5156caf8e2762487be07ef7) -Signed-off-by: Han Gao ---- - .../bindings/phy/spacemit,k1-combo-phy.yaml | 114 ++++++++++++++++++ - 1 file changed, 114 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml -new file mode 100644 -index 000000000000..b59476cd78b5 ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml -@@ -0,0 +1,114 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K1 PCIe/USB3 Combo PHY -+ -+maintainers: -+ - Alex Elder -+ -+description: > -+ Of the three PHYs on the SpacemiT K1 SoC capable of being used for -+ PCIe, one is a combo PHY that can also be configured for use by a -+ USB 3 controller. Using PCIe or USB 3 is a board design decision. -+ -+ The combo PHY is also the only PCIe PHY that is able to determine -+ PCIe calibration values to use, and this must be determined before -+ the other two PCIe PHYs can be used. This calibration must be -+ performed with the combo PHY in PCIe mode, and is this is done -+ when the combo PHY is probed. -+ -+ The combo PHY uses an external oscillator as a reference clock. -+ During normal operation, the PCIe or USB port driver is responsible -+ for ensuring all other clocks needed by a PHY are enabled, and all -+ resets affecting the PHY are deasserted. However, for the combo -+ PHY to perform calibration independent of whether it's later used -+ for PCIe or USB, all PCIe mode clocks and resets must be defined. -+ -+properties: -+ compatible: -+ const: spacemit,k1-combo-phy -+ -+ reg: -+ items: -+ - description: PHY control registers -+ -+ clocks: -+ items: -+ - description: External oscillator used by the PHY PLL -+ - description: DWC PCIe Data Bus Interface (DBI) clock -+ - description: DWC PCIe application AXI-bus Master interface clock -+ - description: DWC PCIe application AXI-bus slave interface clock -+ -+ clock-names: -+ items: -+ - const: refclk -+ - const: dbi -+ - const: mstr -+ - const: slv -+ -+ resets: -+ items: -+ - description: PHY reset; remains deasserted after initialization -+ - description: DWC PCIe Data Bus Interface (DBI) reset -+ - description: DWC PCIe application AXI-bus Master interface reset -+ - description: DWC PCIe application AXI-bus slave interface reset -+ -+ reset-names: -+ items: -+ - const: phy -+ - const: dbi -+ - const: mstr -+ - const: slv -+ -+ spacemit,apmu: -+ description: -+ A phandle that refers to the APMU system controller, whose -+ regmap is used in setting the mode -+ $ref: /schemas/types.yaml#/definitions/phandle -+ -+ "#phy-cells": -+ const: 1 -+ description: -+ The argument value (PHY_TYPE_PCIE or PHY_TYPE_USB3) determines -+ whether the PHY operates in PCIe or USB3 mode. -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ - spacemit,apmu -+ - "#phy-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ phy@c0b10000 { -+ compatible = "spacemit,k1-combo-phy"; -+ reg = <0xc0b10000 0x1000>; -+ clocks = <&vctcxo_24m>, -+ <&syscon_apmu CLK_PCIE0_DBI>, -+ <&syscon_apmu CLK_PCIE0_MASTER>, -+ <&syscon_apmu CLK_PCIE0_SLAVE>; -+ clock-names = "refclk", -+ "dbi", -+ "mstr", -+ "slv"; -+ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, -+ <&syscon_apmu RESET_PCIE0_DBI>, -+ <&syscon_apmu RESET_PCIE0_MASTER>, -+ <&syscon_apmu RESET_PCIE0_SLAVE>; -+ reset-names = "phy", -+ "dbi", -+ "mstr", -+ "slv"; -+ spacemit,apmu = <&syscon_apmu>; -+ #phy-cells = <1>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch b/SPECS/linux-lts-kmhv2/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch new file mode 100644 index 0000000000..4a013ca623 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch @@ -0,0 +1,41 @@ +From 1fce0749e1bf54d192dde74d2c105f51a35ab4d4 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Thu, 18 Dec 2025 09:12:30 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add a PCIe regulator + +Define a 3.3v fixed voltage regulator to be used by PCIe on the +Banana Pi BPI-F3. On this platform, this regulator is always on. + +Signed-off-by: Alex Elder +Reviewed-by: Yixun Lan +Tested-by: Yixun Lan +Link: https://lore.kernel.org/r/20251218151235.454997-5-elder@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 73a6c811fa0d07078c9e1eaecea76ce26fb5f10e) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 02f218a16318..71f48454ba47 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -33,6 +33,14 @@ led1 { + }; + }; + ++ pcie_vcc_3v3: pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PCIE_VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + reg_dc_in: dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0081-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch b/SPECS/linux-lts-kmhv2/0081-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch deleted file mode 100644 index db99c863ec..0000000000 --- a/SPECS/linux-lts-kmhv2/0081-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 3cd6a40bb10240022a2201bf5616dd9ed857f053 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Thu, 18 Dec 2025 09:12:28 -0600 -Subject: [PATCH 081/467] UPSTREAM: dt-bindings: phy: spacemit: Introduce PCIe - PHY - -Add the Device Tree binding for two PCIe PHYs present on the SpacemiT -K1 SoC. These PHYs are dependent on a separate combo PHY, which -determines at probe time the calibration values used by the PCIe-only -PHYs. - -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Alex Elder -Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1] -Tested-by: Yixun Lan -Link: https://patch.msgid.link/20251218151235.454997-3-elder@riscstar.com -Signed-off-by: Vinod Koul -(cherry picked from commit 326a278a3682d390269699f68e597b5ef5a57d26) -Signed-off-by: Han Gao ---- - .../bindings/phy/spacemit,k1-pcie-phy.yaml | 71 +++++++++++++++++++ - 1 file changed, 71 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml -new file mode 100644 -index 000000000000..019b28349be7 ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml -@@ -0,0 +1,71 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K1 PCIe PHY -+ -+maintainers: -+ - Alex Elder -+ -+description: > -+ Two PHYs on the SpacemiT K1 SoC used for only for PCIe. These -+ PHYs must be configured using calibration values that are -+ determined by a third "combo PHY". The combo PHY determines -+ these calibration values during probe so they can be used for -+ the two PCIe-only PHYs. -+ -+ The PHY uses an external oscillator as a reference clock. During -+ normal operation, the PCIe host driver is responsible for ensuring -+ all other clocks needed by a PHY are enabled, and all resets -+ affecting the PHY are deasserted. -+ -+properties: -+ compatible: -+ const: spacemit,k1-pcie-phy -+ -+ reg: -+ items: -+ - description: PHY control registers -+ -+ clocks: -+ items: -+ - description: External oscillator used by the PHY PLL -+ -+ clock-names: -+ const: refclk -+ -+ resets: -+ items: -+ - description: PHY reset; remains deasserted after initialization -+ -+ reset-names: -+ const: phy -+ -+ "#phy-cells": -+ const: 0 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ - "#phy-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ phy@c0c10000 { -+ compatible = "spacemit,k1-pcie-phy"; -+ reg = <0xc0c10000 0x1000>; -+ clocks = <&vctcxo_24m>; -+ clock-names = "refclk"; -+ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; -+ reset-names = "phy"; -+ #phy-cells = <0>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch b/SPECS/linux-lts-kmhv2/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch new file mode 100644 index 0000000000..ba9f3b4975 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch @@ -0,0 +1,331 @@ +From cca8801247fe6e5967002d5519f537917e6a9bf5 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Thu, 18 Dec 2025 09:12:31 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: PCIe and PHY-related + updates + +Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC. + +Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3 +board. The combo PHY is used for USB on this board, and that will be +enabled when USB 3 support is accepted. + +The combo PHY must perform a calibration step to determine configuration +values used by the PCIe-only PHYs. As a result, it must be enabled if +either of the other two PHYs is enabled. + +Signed-off-by: Alex Elder +Reviewed-by: Yixun Lan +Tested-by: Yixun Lan +Link: https://lore.kernel.org/r/20251218151235.454997-6-elder@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 0be016a4b5d1b927de04e2e7a0a2bce51aacbfff) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 36 ++++ + arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 33 ++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 176 ++++++++++++++++++ + 3 files changed, 245 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 71f48454ba47..3f10efd925dc 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -61,6 +61,12 @@ reg_vcc_4v: vcc-4v { + }; + }; + ++&combo_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_3_cfg>; ++ status = "okay"; ++}; ++ + &emmc { + bus-width = <8>; + mmc-hs400-1_8v; +@@ -272,6 +278,36 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++}; ++ ++&pcie1 { ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++}; ++ ++&pcie2 { ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +index e922e05ff856..b13dcb10f4d6 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +@@ -530,6 +530,39 @@ uart9-2-pins { + }; + }; + ++ pcie0_3_cfg: pcie0-3-cfg { ++ pcie0-3-pins { ++ pinmux = , /* PERST# */ ++ , /* WAKE# */ ++ ; /* CLKREQ# */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <21>; ++ }; ++ }; ++ ++ pcie1_3_cfg: pcie1-3-cfg { ++ pcie1-3-pins { ++ pinmux = , /* PERST# */ ++ , /* WAKE# */ ++ ; /* CLKREQ# */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <21>; ++ }; ++ }; ++ ++ pcie2_4_cfg: pcie2-4-cfg { ++ pcie2-4-pins { ++ pinmux = , /* PERST# */ ++ , /* WAKE# */ ++ ; /* CLKREQ# */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <21>; ++ }; ++ }; ++ + pwm14_1_cfg: pwm14-1-cfg { + pwm14-1-pins { + pinmux = ; +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 7818ca4979b6..86d1db14e2ee 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -4,6 +4,7 @@ + */ + + #include ++#include + + /dts-v1/; + / { +@@ -423,6 +424,52 @@ i2c5: i2c@d4013800 { + status = "disabled"; + }; + ++ combo_phy: phy@c0b10000 { ++ compatible = "spacemit,k1-combo-phy"; ++ reg = <0x0 0xc0b10000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>, ++ <&syscon_apmu CLK_PCIE0_DBI>, ++ <&syscon_apmu CLK_PCIE0_MASTER>, ++ <&syscon_apmu CLK_PCIE0_SLAVE>; ++ clock-names = "refclk", ++ "dbi", ++ "mstr", ++ "slv"; ++ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, ++ <&syscon_apmu RESET_PCIE0_DBI>, ++ <&syscon_apmu RESET_PCIE0_MASTER>, ++ <&syscon_apmu RESET_PCIE0_SLAVE>; ++ reset-names = "phy", ++ "dbi", ++ "mstr", ++ "slv"; ++ #phy-cells = <1>; ++ spacemit,apmu = <&syscon_apmu>; ++ status = "disabled"; ++ }; ++ ++ pcie1_phy: phy@c0c10000 { ++ compatible = "spacemit,k1-pcie-phy"; ++ reg = <0x0 0xc0c10000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>; ++ clock-names = "refclk"; ++ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; ++ reset-names = "phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie2_phy: phy@c0d10000 { ++ compatible = "spacemit,k1-pcie-phy"; ++ reg = <0x0 0xc0d10000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>; ++ clock-names = "refclk"; ++ resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; ++ reset-names = "phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k1-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; +@@ -969,6 +1016,135 @@ pcie-bus { + #size-cells = <2>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, + <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; ++ pcie0: pcie@ca000000 { ++ device_type = "pci"; ++ compatible = "spacemit,k1-pcie"; ++ reg = <0x0 0xca000000 0x0 0x00001000>, ++ <0x0 0xca300000 0x0 0x0001ff24>, ++ <0x0 0x8f000000 0x0 0x00002000>, ++ <0x0 0xc0b20000 0x0 0x00001000>; ++ reg-names = "dbi", ++ "atu", ++ "config", ++ "link"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, ++ <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>; ++ interrupts = <141>; ++ interrupt-names = "msi"; ++ clocks = <&syscon_apmu CLK_PCIE0_DBI>, ++ <&syscon_apmu CLK_PCIE0_MASTER>, ++ <&syscon_apmu CLK_PCIE0_SLAVE>; ++ clock-names = "dbi", ++ "mstr", ++ "slv"; ++ resets = <&syscon_apmu RESET_PCIE0_DBI>, ++ <&syscon_apmu RESET_PCIE0_MASTER>, ++ <&syscon_apmu RESET_PCIE0_SLAVE>; ++ reset-names = "dbi", ++ "mstr", ++ "slv"; ++ spacemit,apmu = <&syscon_apmu 0x03cc>; ++ status = "disabled"; ++ ++ pcie0_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ ++ pcie1: pcie@ca400000 { ++ device_type = "pci"; ++ compatible = "spacemit,k1-pcie"; ++ reg = <0x0 0xca400000 0x0 0x00001000>, ++ <0x0 0xca700000 0x0 0x0001ff24>, ++ <0x0 0x9f000000 0x0 0x00002000>, ++ <0x0 0xc0c20000 0x0 0x00001000>; ++ reg-names = "dbi", ++ "atu", ++ "config", ++ "link"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, ++ <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>; ++ interrupts = <142>; ++ interrupt-names = "msi"; ++ clocks = <&syscon_apmu CLK_PCIE1_DBI>, ++ <&syscon_apmu CLK_PCIE1_MASTER>, ++ <&syscon_apmu CLK_PCIE1_SLAVE>; ++ clock-names = "dbi", ++ "mstr", ++ "slv"; ++ resets = <&syscon_apmu RESET_PCIE1_DBI>, ++ <&syscon_apmu RESET_PCIE1_MASTER>, ++ <&syscon_apmu RESET_PCIE1_SLAVE>; ++ reset-names = "dbi", ++ "mstr", ++ "slv"; ++ spacemit,apmu = <&syscon_apmu 0x3d4>; ++ status = "disabled"; ++ ++ pcie1_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ ++ pcie2: pcie@ca800000 { ++ device_type = "pci"; ++ compatible = "spacemit,k1-pcie"; ++ reg = <0x0 0xca800000 0x0 0x00001000>, ++ <0x0 0xcab00000 0x0 0x0001ff24>, ++ <0x0 0xb7000000 0x0 0x00002000>, ++ <0x0 0xc0d20000 0x0 0x00001000>; ++ reg-names = "dbi", ++ "atu", ++ "config", ++ "link"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, ++ <0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>; ++ interrupts = <143>; ++ interrupt-names = "msi"; ++ clocks = <&syscon_apmu CLK_PCIE2_DBI>, ++ <&syscon_apmu CLK_PCIE2_MASTER>, ++ <&syscon_apmu CLK_PCIE2_SLAVE>; ++ clock-names = "dbi", ++ "mstr", ++ "slv"; ++ resets = <&syscon_apmu RESET_PCIE2_DBI>, ++ <&syscon_apmu RESET_PCIE2_MASTER>, ++ <&syscon_apmu RESET_PCIE2_SLAVE>; ++ reset-names = "dbi", ++ "mstr", ++ "slv"; ++ spacemit,apmu = <&syscon_apmu 0x3dc>; ++ status = "disabled"; ++ ++ pcie2_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; + }; + + storage-bus { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch b/SPECS/linux-lts-kmhv2/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch new file mode 100644 index 0000000000..c158eae42a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch @@ -0,0 +1,38 @@ +From f388858d4abee4592cdb3e48a66ed3c681b5801f Mon Sep 17 00:00:00 2001 +From: Encrow Thorne +Date: Tue, 30 Dec 2025 23:06:51 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: i2c: spacemit: add optional + resets + +The I2C controller requires a reset to ensure it starts from a clean state. + +Add the 'resets' property to support this hardware requirement. + +Signed-off-by: Encrow Thorne +Reviewed-by: Troy Mitchell +Acked-by: Rob Herring (Arm) +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20251230150653.42097-1-jyc0019@gmail.com +(cherry picked from commit ad0876a84631fee7b0ad4cd8118b9696aa566671) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml +index b7220fff2235..5896fb120501 100644 +--- a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml ++++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml +@@ -41,6 +41,9 @@ properties: + default: 400000 + maximum: 3300000 + ++ resets: ++ maxItems: 1 ++ + required: + - compatible + - reg +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0082-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch b/SPECS/linux-lts-kmhv2/0082-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch deleted file mode 100644 index 10a079192b..0000000000 --- a/SPECS/linux-lts-kmhv2/0082-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch +++ /dev/null @@ -1,758 +0,0 @@ -From 096da94e3a5fd9f1512f24b16feafb77786b5dfc Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Thu, 18 Dec 2025 09:12:29 -0600 -Subject: [PATCH 082/467] UPSTREAM: phy: spacemit: Introduce PCIe/combo PHY - -Introduce a driver that supports three PHYs found on the SpacemiT -K1 SoC. The first PHY is a combo PHY that can be configured for -use for either USB 3 or PCIe. The other two PHYs support PCIe -only. - -All three PHYs must be programmed with an 8 bit receiver termination -value, which must be determined dynamically. Only the combo PHY is -able to determine this value. The combo PHY performs a special -calibration step at probe time to discover this, and that value is -used to program each PHY that operates in PCIe mode. The combo -PHY must therefore be probed before either of the PCIe-only PHYs -will be used. - -Each PHY has an internal PLL driven from an external oscillator. -This PLL started when the PHY is first initialized, and stays -on thereafter. - -During normal operation, the USB or PCIe driver using the PHY must -ensure (other) clocks and resets are set up properly. - -However PCIe mode clocks are enabled and resets are de-asserted -temporarily by this driver to perform the calibration step on the -combo PHY. - -Tested-by: Junzhong Pan -Signed-off-by: Alex Elder -Reviewed-by: Neil Armstrong -Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1] -Tested-by: Yixun Lan -Link: https://patch.msgid.link/20251218151235.454997-4-elder@riscstar.com -Signed-off-by: Vinod Koul -(cherry picked from commit 57e920b92724dd568526990c04e79ed54241c5fc) -Signed-off-by: Han Gao ---- - drivers/phy/Kconfig | 11 + - drivers/phy/Makefile | 1 + - drivers/phy/phy-spacemit-k1-pcie.c | 670 +++++++++++++++++++++++++++++ - 3 files changed, 682 insertions(+) - create mode 100644 drivers/phy/phy-spacemit-k1-pcie.c - -diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig -index 678dd0452f0a..1984c2e56122 100644 ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -101,6 +101,17 @@ config PHY_NXP_PTN3222 - schemes. It supports all three USB 2.0 data rates: Low Speed, Full - Speed and High Speed. - -+config PHY_SPACEMIT_K1_PCIE -+ tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC" -+ depends on ARCH_SPACEMIT || COMPILE_TEST -+ depends on HAS_IOMEM -+ depends on OF -+ select GENERIC_PHY -+ default ARCH_SPACEMIT -+ help -+ Enable support for the PCIe and USB 3 combo PHY and two -+ PCIe-only PHYs used in the SpacemiT K1 SoC. -+ - source "drivers/phy/allwinner/Kconfig" - source "drivers/phy/amlogic/Kconfig" - source "drivers/phy/broadcom/Kconfig" -diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile -index bfb27fb5a494..a206133a3515 100644 ---- a/drivers/phy/Makefile -+++ b/drivers/phy/Makefile -@@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o - obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o - obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o - obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o -+obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-spacemit-k1-pcie.o - obj-y += allwinner/ \ - amlogic/ \ - broadcom/ \ -diff --git a/drivers/phy/phy-spacemit-k1-pcie.c b/drivers/phy/phy-spacemit-k1-pcie.c -new file mode 100644 -index 000000000000..75477bea7f70 ---- /dev/null -+++ b/drivers/phy/phy-spacemit-k1-pcie.c -@@ -0,0 +1,670 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * SpacemiT K1 PCIe and PCIe/USB 3 combo PHY driver -+ * -+ * Copyright (C) 2025 by RISCstar Solutions Corporation. All rights reserved. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* -+ * Three PCIe ports are supported in the SpacemiT K1 SoC, and this driver -+ * supports their PHYs. -+ * -+ * The PHY for PCIe port A is different from the PHYs for ports B and C: -+ * - It has one lane, while ports B and C have two -+ * - It is a combo PHY can be used for PCIe or USB 3 -+ * - It can automatically calibrate PCIe TX and RX termination settings -+ * -+ * The PHY functionality for PCIe ports B and C is identical: -+ * - They have two PCIe lanes (but can be restricted to 1 via device tree) -+ * - They are used for PCIe only -+ * - They are configured using TX and RX values computed for port A -+ * -+ * A given board is designed to use the combo PHY for either PCIe or USB 3. -+ * Whether the combo PHY is configured for PCIe or USB 3 is specified in -+ * device tree using a phandle plus an argument. The argument indicates -+ * the type (either PHY_TYPE_PCIE or PHY_TYPE_USB3). -+ * -+ * Each PHY has a reset that it gets and deasserts during initialization. -+ * Each depends also on other clocks and resets provided by the controller -+ * hardware (PCIe or USB) it is associated with. The controller drivers -+ * are required to enable any clocks and de-assert any resets that affect -+ * PHY operation. In addition each PHY implements an internal PLL, driven -+ * by an external (24 MHz) oscillator. -+ * -+ * PCIe PHYs must be programmed with RX and TX calibration values. The -+ * combo PHY is the only one that can determine these values. They are -+ * determined by temporarily enabling the combo PHY in PCIe mode at probe -+ * time (if necessary). This calibration only needs to be done once, and -+ * when it has completed the TX and RX values are saved. -+ * -+ * To allow the combo PHY to be enabled for calibration, the resets and -+ * clocks it uses in PCIe mode must be supplied. -+ */ -+ -+struct k1_pcie_phy { -+ struct device *dev; /* PHY provider device */ -+ struct phy *phy; -+ void __iomem *regs; -+ u32 pcie_lanes; /* Max (1 or 2) unless limited by DT */ -+ struct clk *pll; -+ struct clk_hw pll_hw; /* Private PLL clock */ -+ -+ /* The remaining fields are only used for the combo PHY */ -+ u32 type; /* PHY_TYPE_PCIE or PHY_TYPE_USB3 */ -+ struct regmap *pmu; /* MMIO regmap (no errors) */ -+}; -+ -+#define CALIBRATION_TIMEOUT 500000 /* For combo PHY (usec) */ -+#define PLL_TIMEOUT 500000 /* For PHY PLL lock (usec) */ -+#define POLL_DELAY 500 /* Time between polls (usec) */ -+ -+/* Selecting the combo PHY operating mode requires APMU regmap access */ -+#define SYSCON_APMU "spacemit,apmu" -+ -+/* PMU space, for selecting between PCIe and USB 3 mode (combo PHY only) */ -+ -+#define PMUA_USB_PHY_CTRL0 0x0110 -+#define COMBO_PHY_SEL BIT(3) /* 0: PCIe; 1: USB 3 */ -+ -+#define PCIE_CLK_RES_CTRL 0x03cc -+#define PCIE_APP_HOLD_PHY_RST BIT(30) -+ -+/* PHY register space */ -+ -+/* Offset between lane 0 and lane 1 registers when there are two */ -+#define PHY_LANE_OFFSET 0x0400 -+ -+/* PHY PLL configuration */ -+#define PCIE_PU_ADDR_CLK_CFG 0x0008 -+#define PLL_READY BIT(0) /* read-only */ -+#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) -+#define TIMER_ADJ_USB 0x2 -+#define TIMER_ADJ_PCIE 0x6 -+#define CFG_SW_PHY_INIT_DONE BIT(11) /* We set after PLL config */ -+ -+#define PCIE_RC_DONE_STATUS 0x0018 -+#define CFG_FORCE_RCV_RETRY BIT(10) /* Used for PCIe */ -+ -+/* PCIe PHY lane calibration; assumes 24MHz input clock */ -+#define PCIE_RC_CAL_REG2 0x0020 -+#define RC_CAL_TOGGLE BIT(22) -+#define CLKSEL GENMASK(31, 29) -+#define CLKSEL_24M 0x3 -+ -+/* Additional PHY PLL configuration (USB 3 and PCIe) */ -+#define PCIE_PU_PLL_1 0x0048 -+#define REF_100_WSSC BIT(12) /* 1: input is 100MHz, SSC */ -+#define FREF_SEL GENMASK(15, 13) -+#define FREF_24M 0x1 -+#define SSC_DEP_SEL GENMASK(19, 16) -+#define SSC_DEP_NONE 0x0 -+#define SSC_DEP_5000PPM 0xa -+ -+/* PCIe PHY configuration */ -+#define PCIE_PU_PLL_2 0x004c -+#define GEN_REF100 BIT(4) /* 1: generate 100MHz clk */ -+ -+#define PCIE_RX_REG1 0x0050 -+#define EN_RTERM BIT(3) -+#define AFE_RTERM_REG GENMASK(11, 8) -+ -+#define PCIE_RX_REG2 0x0054 -+#define RX_RTERM_SEL BIT(5) /* 0: use AFE_RTERM_REG value */ -+ -+#define PCIE_LTSSM_DIS_ENTRY 0x005c -+#define CFG_REFCLK_MODE GENMASK(9, 8) -+#define RFCLK_MODE_DRIVER 0x1 -+#define OVRD_REFCLK_MODE BIT(10) /* 1: use CFG_RFCLK_MODE */ -+ -+#define PCIE_TX_REG1 0x0064 -+#define TX_RTERM_REG GENMASK(15, 12) -+#define TX_RTERM_SEL BIT(25) /* 1: use TX_RTERM_REG */ -+ -+/* Zeroed for the combo PHY operating in USB mode */ -+#define USB3_TEST_CTRL 0x0068 -+ -+/* PHY calibration values, determined by the combo PHY at probe time */ -+#define PCIE_RCAL_RESULT 0x0084 /* Port A PHY only */ -+#define RTERM_VALUE_RX GENMASK(3, 0) -+#define RTERM_VALUE_TX GENMASK(7, 4) -+#define R_TUNE_DONE BIT(10) -+ -+static u32 k1_phy_rterm = ~0; /* Invalid initial value */ -+ -+/* Save the RX and TX receiver termination values */ -+static void k1_phy_rterm_set(u32 val) -+{ -+ k1_phy_rterm = val & (RTERM_VALUE_RX | RTERM_VALUE_TX); -+} -+ -+static bool k1_phy_rterm_valid(void) -+{ -+ /* Valid if no bits outside those we care about are set */ -+ return !(k1_phy_rterm & ~(RTERM_VALUE_RX | RTERM_VALUE_TX)); -+} -+ -+static u32 k1_phy_rterm_rx(void) -+{ -+ return FIELD_GET(RTERM_VALUE_RX, k1_phy_rterm); -+} -+ -+static u32 k1_phy_rterm_tx(void) -+{ -+ return FIELD_GET(RTERM_VALUE_TX, k1_phy_rterm); -+} -+ -+/* Only the combo PHY has a PMU pointer defined */ -+static bool k1_phy_port_a(struct k1_pcie_phy *k1_phy) -+{ -+ return !!k1_phy->pmu; -+} -+ -+/* The PLL clocks are driven by the external oscillator */ -+static const struct clk_parent_data k1_pcie_phy_data[] = { -+ { .fw_name = "refclk", }, -+}; -+ -+static struct k1_pcie_phy *clk_hw_to_k1_phy(struct clk_hw *clk_hw) -+{ -+ return container_of(clk_hw, struct k1_pcie_phy, pll_hw); -+} -+ -+/* USB mode only works on the combo PHY, which has only one lane */ -+static void k1_pcie_phy_pll_prepare_usb(struct k1_pcie_phy *k1_phy) -+{ -+ void __iomem *regs = k1_phy->regs; -+ u32 val; -+ -+ val = readl(regs + PCIE_PU_ADDR_CLK_CFG); -+ val &= ~CFG_INTERNAL_TIMER_ADJ; -+ val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_USB); -+ writel(val, regs + PCIE_PU_ADDR_CLK_CFG); -+ -+ val = readl(regs + PCIE_PU_PLL_1); -+ val &= ~SSC_DEP_SEL; -+ val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_5000PPM); -+ writel(val, regs + PCIE_PU_PLL_1); -+} -+ -+/* Perform PCIe-specific register updates before starting the PLL clock */ -+static void k1_pcie_phy_pll_prepare_pcie(struct k1_pcie_phy *k1_phy) -+{ -+ void __iomem *regs = k1_phy->regs; -+ u32 val; -+ u32 i; -+ -+ for (i = 0; i < k1_phy->pcie_lanes; i++) { -+ val = readl(regs + PCIE_PU_ADDR_CLK_CFG); -+ val &= ~CFG_INTERNAL_TIMER_ADJ; -+ val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_PCIE); -+ writel(val, regs + PCIE_PU_ADDR_CLK_CFG); -+ -+ regs += PHY_LANE_OFFSET; /* Next lane */ -+ } -+ -+ regs = k1_phy->regs; -+ val = readl(regs + PCIE_RC_DONE_STATUS); -+ val |= CFG_FORCE_RCV_RETRY; -+ writel(val, regs + PCIE_RC_DONE_STATUS); -+ -+ val = readl(regs + PCIE_PU_PLL_1); -+ val &= ~SSC_DEP_SEL; -+ val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_NONE); -+ writel(val, regs + PCIE_PU_PLL_1); -+ -+ val = readl(regs + PCIE_PU_PLL_2); -+ val |= GEN_REF100; /* Enable 100 MHz PLL output clock */ -+ writel(val, regs + PCIE_PU_PLL_2); -+} -+ -+static int k1_pcie_phy_pll_prepare(struct clk_hw *clk_hw) -+{ -+ struct k1_pcie_phy *k1_phy = clk_hw_to_k1_phy(clk_hw); -+ void __iomem *regs = k1_phy->regs; -+ u32 val; -+ u32 i; -+ -+ if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3) -+ k1_pcie_phy_pll_prepare_usb(k1_phy); -+ else -+ k1_pcie_phy_pll_prepare_pcie(k1_phy); -+ -+ /* -+ * Disable 100 MHz input reference with spread-spectrum -+ * clocking and select the 24 MHz clock input frequency -+ */ -+ val = readl(regs + PCIE_PU_PLL_1); -+ val &= ~REF_100_WSSC; -+ val &= ~FREF_SEL; -+ val |= FIELD_PREP(FREF_SEL, FREF_24M); -+ writel(val, regs + PCIE_PU_PLL_1); -+ -+ /* Mark PLL configuration done on all lanes */ -+ for (i = 0; i < k1_phy->pcie_lanes; i++) { -+ val = readl(regs + PCIE_PU_ADDR_CLK_CFG); -+ val |= CFG_SW_PHY_INIT_DONE; -+ writel(val, regs + PCIE_PU_ADDR_CLK_CFG); -+ -+ regs += PHY_LANE_OFFSET; /* Next lane */ -+ } -+ -+ /* -+ * Wait for indication the PHY PLL is locked. Lanes for ports -+ * B and C share a PLL, so it's enough to sample just lane 0. -+ */ -+ return readl_poll_timeout(k1_phy->regs + PCIE_PU_ADDR_CLK_CFG, -+ val, val & PLL_READY, -+ POLL_DELAY, PLL_TIMEOUT); -+} -+ -+/* Prepare implies enable, and once enabled, it's always on */ -+static const struct clk_ops k1_pcie_phy_pll_ops = { -+ .prepare = k1_pcie_phy_pll_prepare, -+}; -+ -+/* We represent the PHY PLL as a private clock */ -+static int k1_pcie_phy_pll_setup(struct k1_pcie_phy *k1_phy) -+{ -+ struct clk_hw *hw = &k1_phy->pll_hw; -+ struct device *dev = k1_phy->dev; -+ struct clk_init_data init = { }; -+ char *name; -+ int ret; -+ -+ name = kasprintf(GFP_KERNEL, "pcie%u_phy_pll", k1_phy->phy->id); -+ if (!name) -+ return -ENOMEM; -+ -+ init.name = name; -+ init.ops = &k1_pcie_phy_pll_ops; -+ init.parent_data = k1_pcie_phy_data; -+ init.num_parents = ARRAY_SIZE(k1_pcie_phy_data); -+ -+ hw->init = &init; -+ -+ ret = devm_clk_hw_register(dev, hw); -+ -+ kfree(name); /* __clk_register() duplicates the name we provide */ -+ -+ if (ret) -+ return ret; -+ -+ k1_phy->pll = devm_clk_hw_get_clk(dev, hw, "pll"); -+ if (IS_ERR(k1_phy->pll)) -+ return PTR_ERR(k1_phy->pll); -+ -+ return 0; -+} -+ -+/* Select PCIe or USB 3 mode for the combo PHY. */ -+static void k1_combo_phy_sel(struct k1_pcie_phy *k1_phy, bool usb) -+{ -+ struct regmap *pmu = k1_phy->pmu; -+ -+ /* Only change it if it's not already in the desired state */ -+ if (!regmap_test_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL) == usb) -+ regmap_assign_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL, usb); -+} -+ -+static void k1_pcie_phy_init_pcie(struct k1_pcie_phy *k1_phy) -+{ -+ u32 rx_rterm = k1_phy_rterm_rx(); -+ u32 tx_rterm = k1_phy_rterm_tx(); -+ void __iomem *regs; -+ u32 val; -+ int i; -+ -+ /* For the combo PHY, set PHY to PCIe mode */ -+ if (k1_phy_port_a(k1_phy)) -+ k1_combo_phy_sel(k1_phy, false); -+ -+ regs = k1_phy->regs; -+ for (i = 0; i < k1_phy->pcie_lanes; i++) { -+ val = readl(regs + PCIE_RX_REG1); -+ -+ /* Set RX analog front-end receiver termination value */ -+ val &= ~AFE_RTERM_REG; -+ val |= FIELD_PREP(AFE_RTERM_REG, rx_rterm); -+ -+ /* And enable refclock receiver termination */ -+ val |= EN_RTERM; -+ writel(val, regs + PCIE_RX_REG1); -+ -+ val = readl(regs + PCIE_RX_REG2); -+ /* Use PCIE_RX_REG1 AFE_RTERM_REG value */ -+ val &= ~RX_RTERM_SEL; -+ writel(val, regs + PCIE_RX_REG2); -+ -+ val = readl(regs + PCIE_TX_REG1); -+ -+ /* Set TX driver termination value */ -+ val &= ~TX_RTERM_REG; -+ val |= FIELD_PREP(TX_RTERM_REG, tx_rterm); -+ -+ /* Use PCIE_TX_REG1 TX_RTERM_REG value */ -+ val |= TX_RTERM_SEL; -+ writel(val, regs + PCIE_TX_REG1); -+ -+ /* Set the input clock to 24 MHz, and clear RC_CAL_TOGGLE */ -+ val = readl(regs + PCIE_RC_CAL_REG2); -+ val &= CLKSEL; -+ val |= FIELD_PREP(CLKSEL, CLKSEL_24M); -+ val &= ~RC_CAL_TOGGLE; -+ writel(val, regs + PCIE_RC_CAL_REG2); -+ -+ /* Now trigger recalibration by setting RC_CAL_TOGGLE again */ -+ val |= RC_CAL_TOGGLE; -+ writel(val, regs + PCIE_RC_CAL_REG2); -+ -+ val = readl(regs + PCIE_LTSSM_DIS_ENTRY); -+ /* Override the reference clock; set to refclk driver mode */ -+ val |= OVRD_REFCLK_MODE; -+ val &= ~CFG_REFCLK_MODE; -+ val |= FIELD_PREP(CFG_REFCLK_MODE, RFCLK_MODE_DRIVER); -+ writel(val, regs + PCIE_LTSSM_DIS_ENTRY); -+ -+ regs += PHY_LANE_OFFSET; /* Next lane */ -+ } -+} -+ -+/* Only called for combo PHY */ -+static void k1_pcie_phy_init_usb(struct k1_pcie_phy *k1_phy) -+{ -+ k1_combo_phy_sel(k1_phy, true); -+ -+ /* We're not doing any testing */ -+ writel(0, k1_phy->regs + USB3_TEST_CTRL); -+} -+ -+static int k1_pcie_phy_init(struct phy *phy) -+{ -+ struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy); -+ -+ /* Note: port type is only valid for port A (both checks needed) */ -+ if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3) -+ k1_pcie_phy_init_usb(k1_phy); -+ else -+ k1_pcie_phy_init_pcie(k1_phy); -+ -+ -+ return clk_prepare_enable(k1_phy->pll); -+} -+ -+static int k1_pcie_phy_exit(struct phy *phy) -+{ -+ struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy); -+ -+ clk_disable_unprepare(k1_phy->pll); -+ -+ return 0; -+} -+ -+static const struct phy_ops k1_pcie_phy_ops = { -+ .init = k1_pcie_phy_init, -+ .exit = k1_pcie_phy_exit, -+ .owner = THIS_MODULE, -+}; -+ -+/* -+ * Get values needed for calibrating PHYs operating in PCIe mode. Only -+ * the combo PHY is able to do this, and its calibration values are used -+ * for configuring all PCIe PHYs. -+ * -+ * We always need to de-assert the "global" reset on the combo PHY, -+ * because the USB driver depends on it. If used for PCIe, that driver -+ * will (also) de-assert this, but by leaving it de-asserted for the -+ * combo PHY, the USB driver doesn't have to do this. Note: although -+ * SpacemiT refers to this as the global reset, we name the "phy" reset. -+ * -+ * In addition, we guarantee the APP_HOLD_PHY_RESET bit is clear for the -+ * combo PHY, so the USB driver doesn't have to manage that either. The -+ * PCIe driver is free to change this bit for normal operation. -+ * -+ * Calibration only needs to be done once. It's possible calibration has -+ * already completed (e.g., it might have happened in the boot loader, or -+ * -EPROBE_DEFER might result in this function being called again). So we -+ * check that early too, to avoid doing it more than once. -+ * -+ * Otherwise we temporarily power up the PHY using the PCIe app clocks -+ * and resets, wait for the hardware to indicate calibration is done, -+ * grab the value, then shut the PHY down again. -+ */ -+static int k1_pcie_combo_phy_calibrate(struct k1_pcie_phy *k1_phy) -+{ -+ struct reset_control_bulk_data resets[] = { -+ { .id = "dbi", }, -+ { .id = "mstr", }, -+ { .id = "slv", }, -+ }; -+ struct clk_bulk_data clocks[] = { -+ { .id = "dbi", }, -+ { .id = "mstr", }, -+ { .id = "slv", }, -+ }; -+ struct device *dev = k1_phy->dev; -+ int ret = 0; -+ int val; -+ -+ /* Nothing to do if we already set the receiver termination value */ -+ if (k1_phy_rterm_valid()) -+ return 0; -+ -+ /* -+ * We also guarantee the APP_HOLD_PHY_RESET bit is clear. We can -+ * leave this bit clear even if an error happens below. -+ */ -+ regmap_assign_bits(k1_phy->pmu, PCIE_CLK_RES_CTRL, -+ PCIE_APP_HOLD_PHY_RST, false); -+ -+ /* If the calibration already completed (e.g. by U-Boot), we're done */ -+ val = readl(k1_phy->regs + PCIE_RCAL_RESULT); -+ if (val & R_TUNE_DONE) -+ goto out_tune_done; -+ -+ /* Put the PHY into PCIe mode */ -+ k1_combo_phy_sel(k1_phy, false); -+ -+ /* Get and enable the PCIe app clocks */ -+ ret = clk_bulk_get(dev, ARRAY_SIZE(clocks), clocks); -+ if (ret < 0) -+ goto out_tune_done; -+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); -+ if (ret) -+ goto out_put_clocks; -+ -+ /* Get the PCIe application resets (not the PHY reset) */ -+ ret = reset_control_bulk_get_shared(dev, ARRAY_SIZE(resets), resets); -+ if (ret) -+ goto out_disable_clocks; -+ -+ /* De-assert the PCIe application resets */ -+ ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets); -+ if (ret) -+ goto out_put_resets; -+ -+ /* -+ * This is the core activity here. Wait for the hardware to -+ * signal that it has completed calibration/tuning. Once it -+ * has, the register value will contain the values we'll -+ * use to configure PCIe PHYs. -+ */ -+ ret = readl_poll_timeout(k1_phy->regs + PCIE_RCAL_RESULT, -+ val, val & R_TUNE_DONE, -+ POLL_DELAY, CALIBRATION_TIMEOUT); -+ -+ /* Clean up. We're done with the resets and clocks */ -+ reset_control_bulk_assert(ARRAY_SIZE(resets), resets); -+out_put_resets: -+ reset_control_bulk_put(ARRAY_SIZE(resets), resets); -+out_disable_clocks: -+ clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); -+out_put_clocks: -+ clk_bulk_put(ARRAY_SIZE(clocks), clocks); -+out_tune_done: -+ /* If we got the value without timing out, set k1_phy_rterm */ -+ if (!ret) -+ k1_phy_rterm_set(val); -+ -+ return ret; -+} -+ -+static struct phy * -+k1_pcie_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) -+{ -+ struct k1_pcie_phy *k1_phy = dev_get_drvdata(dev); -+ u32 type; -+ -+ /* The argument specifying the PHY mode is required */ -+ if (args->args_count != 1) -+ return ERR_PTR(-EINVAL); -+ -+ /* We only support PCIe and USB 3 mode */ -+ type = args->args[0]; -+ if (type != PHY_TYPE_PCIE && type != PHY_TYPE_USB3) -+ return ERR_PTR(-EINVAL); -+ -+ /* This PHY can only be used once */ -+ if (k1_phy->type != PHY_NONE) -+ return ERR_PTR(-EBUSY); -+ -+ k1_phy->type = type; -+ -+ return k1_phy->phy; -+} -+ -+/* Use the maximum number of PCIe lanes unless limited by device tree */ -+static u32 k1_pcie_num_lanes(struct k1_pcie_phy *k1_phy, bool port_a) -+{ -+ struct device *dev = k1_phy->dev; -+ u32 count = 0; -+ u32 max; -+ int ret; -+ -+ ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &count); -+ if (count == 1) -+ return 1; -+ -+ if (count == 2 && !port_a) -+ return 2; -+ -+ max = port_a ? 1 : 2; -+ if (ret != -EINVAL) -+ dev_warn(dev, "bad lane count %u for port; using %u\n", -+ count, max); -+ -+ return max; -+} -+ -+static int k1_pcie_combo_phy_probe(struct k1_pcie_phy *k1_phy) -+{ -+ struct device *dev = k1_phy->dev; -+ struct regmap *regmap; -+ int ret; -+ -+ /* Setting the PHY mode requires access to the PMU regmap */ -+ regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), SYSCON_APMU); -+ if (IS_ERR(regmap)) -+ return dev_err_probe(dev, PTR_ERR(regmap), "failed to get PMU\n"); -+ k1_phy->pmu = regmap; -+ -+ ret = k1_pcie_combo_phy_calibrate(k1_phy); -+ if (ret) -+ return dev_err_probe(dev, ret, "calibration failed\n"); -+ -+ /* Needed by k1_pcie_combo_phy_xlate(), which also sets k1_phy->type */ -+ dev_set_drvdata(dev, k1_phy); -+ -+ return 0; -+} -+ -+static int k1_pcie_phy_probe(struct platform_device *pdev) -+{ -+ struct phy *(*xlate)(struct device *dev, -+ const struct of_phandle_args *args); -+ struct device *dev = &pdev->dev; -+ struct reset_control *phy_reset; -+ struct phy_provider *provider; -+ struct k1_pcie_phy *k1_phy; -+ bool probing_port_a; -+ int ret; -+ -+ xlate = of_device_get_match_data(dev); -+ probing_port_a = xlate == k1_pcie_combo_phy_xlate; -+ -+ /* Only the combo PHY can calibrate, so it must probe first */ -+ if (!k1_phy_rterm_valid() && !probing_port_a) -+ return -EPROBE_DEFER; -+ -+ k1_phy = devm_kzalloc(dev, sizeof(*k1_phy), GFP_KERNEL); -+ if (!k1_phy) -+ return -ENOMEM; -+ k1_phy->dev = dev; -+ -+ k1_phy->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(k1_phy->regs)) -+ return dev_err_probe(dev, PTR_ERR(k1_phy->regs), -+ "error mapping registers\n"); -+ -+ /* De-assert the PHY (global) reset and leave it that way */ -+ phy_reset = devm_reset_control_get_exclusive_deasserted(dev, "phy"); -+ if (IS_ERR(phy_reset)) -+ return PTR_ERR(phy_reset); -+ -+ if (probing_port_a) { -+ ret = k1_pcie_combo_phy_probe(k1_phy); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "error probing combo phy\n"); -+ } -+ -+ k1_phy->pcie_lanes = k1_pcie_num_lanes(k1_phy, probing_port_a); -+ -+ k1_phy->phy = devm_phy_create(dev, NULL, &k1_pcie_phy_ops); -+ if (IS_ERR(k1_phy->phy)) -+ return dev_err_probe(dev, PTR_ERR(k1_phy->phy), -+ "error creating phy\n"); -+ phy_set_drvdata(k1_phy->phy, k1_phy); -+ -+ ret = k1_pcie_phy_pll_setup(k1_phy); -+ if (ret) -+ return dev_err_probe(dev, ret, "error initializing clock\n"); -+ -+ provider = devm_of_phy_provider_register(dev, xlate); -+ if (IS_ERR(provider)) -+ return dev_err_probe(dev, PTR_ERR(provider), -+ "error registering provider\n"); -+ return 0; -+} -+ -+static const struct of_device_id k1_pcie_phy_of_match[] = { -+ { .compatible = "spacemit,k1-combo-phy", k1_pcie_combo_phy_xlate, }, -+ { .compatible = "spacemit,k1-pcie-phy", of_phy_simple_xlate, }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, k1_pcie_phy_of_match); -+ -+static struct platform_driver k1_pcie_phy_driver = { -+ .probe = k1_pcie_phy_probe, -+ .driver = { -+ .of_match_table = k1_pcie_phy_of_match, -+ .name = "spacemit-k1-pcie-phy", -+ } -+}; -+module_platform_driver(k1_pcie_phy_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K1 PCIe and USB 3 PHY driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0083-UPSTREAM-i2c-k1-add-reset-support.patch b/SPECS/linux-lts-kmhv2/0083-UPSTREAM-i2c-k1-add-reset-support.patch new file mode 100644 index 0000000000..8df67ed42a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0083-UPSTREAM-i2c-k1-add-reset-support.patch @@ -0,0 +1,56 @@ +From ed3b67eff1ecc6048f6b6a76bff5a97ff2abb964 Mon Sep 17 00:00:00 2001 +From: Encrow Thorne +Date: Tue, 30 Dec 2025 23:06:52 +0800 +Subject: [RUYI PATCH] UPSTREAM: i2c: k1: add reset support + +The K1 I2C controller provides a reset line that needs to be deasserted +before the controller can be accessed. + +Add reset support to the driver to ensure the controller starts in the +required state. + +Signed-off-by: Encrow Thorne +Reviewed-by: Troy Mitchell +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20251230150653.42097-2-jyc0019@gmail.com +(cherry picked from commit b96259551b337225bb0e7afb3452b98435dd8b81) +Signed-off-by: Han Gao +--- + drivers/i2c/busses/i2c-k1.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index 8ef6d5d1927b..d0948a16de3e 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++ #include + + /* spacemit i2c registers */ + #define SPACEMIT_ICR 0x0 /* Control register */ +@@ -534,6 +535,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + struct device *dev = &pdev->dev; + struct device_node *of_node = pdev->dev.of_node; + struct spacemit_i2c_dev *i2c; ++ struct reset_control *rst; + int ret; + + i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); +@@ -578,6 +580,11 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); + ++ rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); ++ if (IS_ERR(rst)) ++ return dev_err_probe(dev, PTR_ERR(rst), ++ "failed to acquire deasserted reset\n"); ++ + spacemit_i2c_reset(i2c); + + i2c_set_adapdata(&i2c->adapt, i2c); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0083-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch b/SPECS/linux-lts-kmhv2/0083-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch deleted file mode 100644 index f3892b1a9e..0000000000 --- a/SPECS/linux-lts-kmhv2/0083-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch +++ /dev/null @@ -1,41 +0,0 @@ -From d4491d4d3cdceae1b08777accb31e16fced2cedf Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Thu, 18 Dec 2025 09:12:30 -0600 -Subject: [PATCH 083/467] UPSTREAM: riscv: dts: spacemit: Add a PCIe regulator - -Define a 3.3v fixed voltage regulator to be used by PCIe on the -Banana Pi BPI-F3. On this platform, this regulator is always on. - -Signed-off-by: Alex Elder -Reviewed-by: Yixun Lan -Tested-by: Yixun Lan -Link: https://lore.kernel.org/r/20251218151235.454997-5-elder@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 73a6c811fa0d07078c9e1eaecea76ce26fb5f10e) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 02f218a16318..71f48454ba47 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -33,6 +33,14 @@ led1 { - }; - }; - -+ pcie_vcc_3v3: pcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "PCIE_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ - reg_dc_in: dc-in-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_in_12v"; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0084-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch b/SPECS/linux-lts-kmhv2/0084-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch deleted file mode 100644 index 0ce1356ac4..0000000000 --- a/SPECS/linux-lts-kmhv2/0084-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch +++ /dev/null @@ -1,331 +0,0 @@ -From 18a1bfdbf520d71a0a3013e286a6cb9152dca8b4 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Thu, 18 Dec 2025 09:12:31 -0600 -Subject: [PATCH 084/467] UPSTREAM: riscv: dts: spacemit: PCIe and PHY-related - updates - -Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC. - -Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3 -board. The combo PHY is used for USB on this board, and that will be -enabled when USB 3 support is accepted. - -The combo PHY must perform a calibration step to determine configuration -values used by the PCIe-only PHYs. As a result, it must be enabled if -either of the other two PHYs is enabled. - -Signed-off-by: Alex Elder -Reviewed-by: Yixun Lan -Tested-by: Yixun Lan -Link: https://lore.kernel.org/r/20251218151235.454997-6-elder@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 0be016a4b5d1b927de04e2e7a0a2bce51aacbfff) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 36 ++++ - arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 33 ++++ - arch/riscv/boot/dts/spacemit/k1.dtsi | 176 ++++++++++++++++++ - 3 files changed, 245 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 71f48454ba47..3f10efd925dc 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -61,6 +61,12 @@ reg_vcc_4v: vcc-4v { - }; - }; - -+&combo_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie0_3_cfg>; -+ status = "okay"; -+}; -+ - &emmc { - bus-width = <8>; - mmc-hs400-1_8v; -@@ -272,6 +278,36 @@ dldo7 { - }; - }; - -+&pcie1_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_3_cfg>; -+ status = "okay"; -+}; -+ -+&pcie1_port { -+ phys = <&pcie1_phy>; -+}; -+ -+&pcie1 { -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+ status = "okay"; -+}; -+ -+&pcie2_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_4_cfg>; -+ status = "okay"; -+}; -+ -+&pcie2_port { -+ phys = <&pcie2_phy>; -+}; -+ -+&pcie2 { -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -index e922e05ff856..b13dcb10f4d6 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -@@ -530,6 +530,39 @@ uart9-2-pins { - }; - }; - -+ pcie0_3_cfg: pcie0-3-cfg { -+ pcie0-3-pins { -+ pinmux = , /* PERST# */ -+ , /* WAKE# */ -+ ; /* CLKREQ# */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <21>; -+ }; -+ }; -+ -+ pcie1_3_cfg: pcie1-3-cfg { -+ pcie1-3-pins { -+ pinmux = , /* PERST# */ -+ , /* WAKE# */ -+ ; /* CLKREQ# */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <21>; -+ }; -+ }; -+ -+ pcie2_4_cfg: pcie2-4-cfg { -+ pcie2-4-pins { -+ pinmux = , /* PERST# */ -+ , /* WAKE# */ -+ ; /* CLKREQ# */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <21>; -+ }; -+ }; -+ - pwm14_1_cfg: pwm14-1-cfg { - pwm14-1-pins { - pinmux = ; -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 7818ca4979b6..86d1db14e2ee 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -4,6 +4,7 @@ - */ - - #include -+#include - - /dts-v1/; - / { -@@ -423,6 +424,52 @@ i2c5: i2c@d4013800 { - status = "disabled"; - }; - -+ combo_phy: phy@c0b10000 { -+ compatible = "spacemit,k1-combo-phy"; -+ reg = <0x0 0xc0b10000 0x0 0x1000>; -+ clocks = <&vctcxo_24m>, -+ <&syscon_apmu CLK_PCIE0_DBI>, -+ <&syscon_apmu CLK_PCIE0_MASTER>, -+ <&syscon_apmu CLK_PCIE0_SLAVE>; -+ clock-names = "refclk", -+ "dbi", -+ "mstr", -+ "slv"; -+ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, -+ <&syscon_apmu RESET_PCIE0_DBI>, -+ <&syscon_apmu RESET_PCIE0_MASTER>, -+ <&syscon_apmu RESET_PCIE0_SLAVE>; -+ reset-names = "phy", -+ "dbi", -+ "mstr", -+ "slv"; -+ #phy-cells = <1>; -+ spacemit,apmu = <&syscon_apmu>; -+ status = "disabled"; -+ }; -+ -+ pcie1_phy: phy@c0c10000 { -+ compatible = "spacemit,k1-pcie-phy"; -+ reg = <0x0 0xc0c10000 0x0 0x1000>; -+ clocks = <&vctcxo_24m>; -+ clock-names = "refclk"; -+ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; -+ reset-names = "phy"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ pcie2_phy: phy@c0d10000 { -+ compatible = "spacemit,k1-pcie-phy"; -+ reg = <0x0 0xc0d10000 0x0 0x1000>; -+ clocks = <&vctcxo_24m>; -+ clock-names = "refclk"; -+ resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; -+ reset-names = "phy"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k1-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; -@@ -969,6 +1016,135 @@ pcie-bus { - #size-cells = <2>; - dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, - <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; -+ pcie0: pcie@ca000000 { -+ device_type = "pci"; -+ compatible = "spacemit,k1-pcie"; -+ reg = <0x0 0xca000000 0x0 0x00001000>, -+ <0x0 0xca300000 0x0 0x0001ff24>, -+ <0x0 0x8f000000 0x0 0x00002000>, -+ <0x0 0xc0b20000 0x0 0x00001000>; -+ reg-names = "dbi", -+ "atu", -+ "config", -+ "link"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, -+ <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>; -+ interrupts = <141>; -+ interrupt-names = "msi"; -+ clocks = <&syscon_apmu CLK_PCIE0_DBI>, -+ <&syscon_apmu CLK_PCIE0_MASTER>, -+ <&syscon_apmu CLK_PCIE0_SLAVE>; -+ clock-names = "dbi", -+ "mstr", -+ "slv"; -+ resets = <&syscon_apmu RESET_PCIE0_DBI>, -+ <&syscon_apmu RESET_PCIE0_MASTER>, -+ <&syscon_apmu RESET_PCIE0_SLAVE>; -+ reset-names = "dbi", -+ "mstr", -+ "slv"; -+ spacemit,apmu = <&syscon_apmu 0x03cc>; -+ status = "disabled"; -+ -+ pcie0_port: pcie@0 { -+ device_type = "pci"; -+ compatible = "pciclass,0604"; -+ reg = <0x0 0x0 0x0 0x0 0x0>; -+ bus-range = <0x01 0xff>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ }; -+ }; -+ -+ pcie1: pcie@ca400000 { -+ device_type = "pci"; -+ compatible = "spacemit,k1-pcie"; -+ reg = <0x0 0xca400000 0x0 0x00001000>, -+ <0x0 0xca700000 0x0 0x0001ff24>, -+ <0x0 0x9f000000 0x0 0x00002000>, -+ <0x0 0xc0c20000 0x0 0x00001000>; -+ reg-names = "dbi", -+ "atu", -+ "config", -+ "link"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, -+ <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>; -+ interrupts = <142>; -+ interrupt-names = "msi"; -+ clocks = <&syscon_apmu CLK_PCIE1_DBI>, -+ <&syscon_apmu CLK_PCIE1_MASTER>, -+ <&syscon_apmu CLK_PCIE1_SLAVE>; -+ clock-names = "dbi", -+ "mstr", -+ "slv"; -+ resets = <&syscon_apmu RESET_PCIE1_DBI>, -+ <&syscon_apmu RESET_PCIE1_MASTER>, -+ <&syscon_apmu RESET_PCIE1_SLAVE>; -+ reset-names = "dbi", -+ "mstr", -+ "slv"; -+ spacemit,apmu = <&syscon_apmu 0x3d4>; -+ status = "disabled"; -+ -+ pcie1_port: pcie@0 { -+ device_type = "pci"; -+ compatible = "pciclass,0604"; -+ reg = <0x0 0x0 0x0 0x0 0x0>; -+ bus-range = <0x01 0xff>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ }; -+ }; -+ -+ pcie2: pcie@ca800000 { -+ device_type = "pci"; -+ compatible = "spacemit,k1-pcie"; -+ reg = <0x0 0xca800000 0x0 0x00001000>, -+ <0x0 0xcab00000 0x0 0x0001ff24>, -+ <0x0 0xb7000000 0x0 0x00002000>, -+ <0x0 0xc0d20000 0x0 0x00001000>; -+ reg-names = "dbi", -+ "atu", -+ "config", -+ "link"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, -+ <0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>, -+ <0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>; -+ interrupts = <143>; -+ interrupt-names = "msi"; -+ clocks = <&syscon_apmu CLK_PCIE2_DBI>, -+ <&syscon_apmu CLK_PCIE2_MASTER>, -+ <&syscon_apmu CLK_PCIE2_SLAVE>; -+ clock-names = "dbi", -+ "mstr", -+ "slv"; -+ resets = <&syscon_apmu RESET_PCIE2_DBI>, -+ <&syscon_apmu RESET_PCIE2_MASTER>, -+ <&syscon_apmu RESET_PCIE2_SLAVE>; -+ reset-names = "dbi", -+ "mstr", -+ "slv"; -+ spacemit,apmu = <&syscon_apmu 0x3dc>; -+ status = "disabled"; -+ -+ pcie2_port: pcie@0 { -+ device_type = "pci"; -+ compatible = "pciclass,0604"; -+ reg = <0x0 0x0 0x0 0x0 0x0>; -+ bus-range = <0x01 0xff>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ }; -+ }; - }; - - storage-bus { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch b/SPECS/linux-lts-kmhv2/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch new file mode 100644 index 0000000000..19f85450fa --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch @@ -0,0 +1,87 @@ +From 3aa8e6c84101edb3c499478758e4a82cc230af36 Mon Sep 17 00:00:00 2001 +From: Encrow Thorne +Date: Tue, 30 Dec 2025 23:06:53 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add reset property + +Add resets property to K1 I2C node. + +Signed-off-by: Encrow Thorne +Link: https://lore.kernel.org/r/20251230150653.42097-3-jyc0019@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 7d6fe7e381d2912300df06e1a7e7a6f6a9269af0) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 86d1db14e2ee..4c045da95d72 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -368,6 +368,7 @@ i2c0: i2c@d4010800 { + <&syscon_apbc CLK_TWSI0_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI0>; + interrupts = <36>; + status = "disabled"; + }; +@@ -381,6 +382,7 @@ i2c1: i2c@d4011000 { + <&syscon_apbc CLK_TWSI1_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI1>; + interrupts = <37>; + status = "disabled"; + }; +@@ -394,6 +396,7 @@ i2c2: i2c@d4012000 { + <&syscon_apbc CLK_TWSI2_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI2>; + interrupts = <38>; + status = "disabled"; + }; +@@ -407,6 +410,7 @@ i2c4: i2c@d4012800 { + <&syscon_apbc CLK_TWSI4_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI4>; + interrupts = <40>; + status = "disabled"; + }; +@@ -420,6 +424,7 @@ i2c5: i2c@d4013800 { + <&syscon_apbc CLK_TWSI5_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI5>; + interrupts = <41>; + status = "disabled"; + }; +@@ -490,6 +495,7 @@ i2c6: i2c@d4018800 { + <&syscon_apbc CLK_TWSI6_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI6>; + interrupts = <70>; + status = "disabled"; + }; +@@ -593,6 +599,7 @@ i2c7: i2c@d401d000 { + <&syscon_apbc CLK_TWSI7_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI7>; + interrupts = <18>; + status = "disabled"; + }; +@@ -606,6 +613,7 @@ i2c8: i2c@d401d800 { + <&syscon_apbc CLK_TWSI8_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI8>; + interrupts = <19>; + status = "disabled"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0085-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch b/SPECS/linux-lts-kmhv2/0085-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch deleted file mode 100644 index 55238bb179..0000000000 --- a/SPECS/linux-lts-kmhv2/0085-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 76c5487f89e7e980c33e0ff5153a4b508e920406 Mon Sep 17 00:00:00 2001 -From: Encrow Thorne -Date: Tue, 30 Dec 2025 23:06:51 +0800 -Subject: [PATCH 085/467] UPSTREAM: dt-bindings: i2c: spacemit: add optional - resets - -The I2C controller requires a reset to ensure it starts from a clean state. - -Add the 'resets' property to support this hardware requirement. - -Signed-off-by: Encrow Thorne -Reviewed-by: Troy Mitchell -Acked-by: Rob Herring (Arm) -Signed-off-by: Andi Shyti -Link: https://lore.kernel.org/r/20251230150653.42097-1-jyc0019@gmail.com -(cherry picked from commit ad0876a84631fee7b0ad4cd8118b9696aa566671) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml -index b7220fff2235..5896fb120501 100644 ---- a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml -+++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml -@@ -41,6 +41,9 @@ properties: - default: 400000 - maximum: 3300000 - -+ resets: -+ maxItems: 1 -+ - required: - - compatible - - reg --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch b/SPECS/linux-lts-kmhv2/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch new file mode 100644 index 0000000000..eae9b4c51d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch @@ -0,0 +1,69 @@ +From 9d8fbb22b0d4fc7ec75661abcee3d71ca556f67a Mon Sep 17 00:00:00 2001 +From: Ze Huang +Date: Fri, 17 Oct 2025 22:49:52 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: add K1 USB2 PHY + +Add support for USB2 PHY found on SpacemiT K1 SoC. + +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Ze Huang +Tested-by: Aurelien Jarno +Tested-by: Junzhong Pan +Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-1-7cf9ea2477a1@linux.dev +Signed-off-by: Vinod Koul +(cherry picked from commit 61b84d5b20af2a4c9944972202c1386026598928) +Signed-off-by: Han Gao +--- + .../bindings/phy/spacemit,usb2-phy.yaml | 40 +++++++++++++++++++ + 1 file changed, 40 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml +new file mode 100644 +index 000000000000..43eaca90d88c +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml +@@ -0,0 +1,40 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 SoC USB 2.0 PHY ++ ++maintainers: ++ - Ze Huang ++ ++properties: ++ compatible: ++ const: spacemit,k1-usb2-phy ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 0 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - "#phy-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ usb-phy@c09c0000 { ++ compatible = "spacemit,k1-usb2-phy"; ++ reg = <0xc09c0000 0x200>; ++ clocks = <&syscon_apmu 15>; ++ #phy-cells = <0>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0086-UPSTREAM-i2c-k1-add-reset-support.patch b/SPECS/linux-lts-kmhv2/0086-UPSTREAM-i2c-k1-add-reset-support.patch deleted file mode 100644 index a444fe362e..0000000000 --- a/SPECS/linux-lts-kmhv2/0086-UPSTREAM-i2c-k1-add-reset-support.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 22ab3f10aeaedca84e6ca2414362223f5873ce76 Mon Sep 17 00:00:00 2001 -From: Encrow Thorne -Date: Tue, 30 Dec 2025 23:06:52 +0800 -Subject: [PATCH 086/467] UPSTREAM: i2c: k1: add reset support - -The K1 I2C controller provides a reset line that needs to be deasserted -before the controller can be accessed. - -Add reset support to the driver to ensure the controller starts in the -required state. - -Signed-off-by: Encrow Thorne -Reviewed-by: Troy Mitchell -Signed-off-by: Andi Shyti -Link: https://lore.kernel.org/r/20251230150653.42097-2-jyc0019@gmail.com -(cherry picked from commit b96259551b337225bb0e7afb3452b98435dd8b81) -Signed-off-by: Han Gao ---- - drivers/i2c/busses/i2c-k1.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index 8ef6d5d1927b..d0948a16de3e 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+ #include - - /* spacemit i2c registers */ - #define SPACEMIT_ICR 0x0 /* Control register */ -@@ -534,6 +535,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - struct device *dev = &pdev->dev; - struct device_node *of_node = pdev->dev.of_node; - struct spacemit_i2c_dev *i2c; -+ struct reset_control *rst; - int ret; - - i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); -@@ -578,6 +580,11 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); - -+ rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); -+ if (IS_ERR(rst)) -+ return dev_err_probe(dev, PTR_ERR(rst), -+ "failed to acquire deasserted reset\n"); -+ - spacemit_i2c_reset(i2c); - - i2c_set_adapdata(&i2c->adapt, i2c); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch b/SPECS/linux-lts-kmhv2/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch new file mode 100644 index 0000000000..dd0a27e19d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch @@ -0,0 +1,297 @@ +From 6fe75e59d1834ffff41681bcd52b6a1a83446f3e Mon Sep 17 00:00:00 2001 +From: Ze Huang +Date: Fri, 17 Oct 2025 22:49:53 +0800 +Subject: [RUYI PATCH] UPSTREAM: phy: spacemit: support K1 USB2.0 PHY + controller + +The SpacemiT K1 SoC includes three USB ports: + +- One USB2.0 OTG port +- One USB2.0 host-only port +- One USB3.0 port with an integrated USB2.0 DRD interface + +Each of these ports is connected to a USB2.0 PHY responsible for USB2 +transmission. + +This commit adds support for the SpacemiT K1 USB2.0 PHY, which is +compliant with the USB 2.0 specification and supports both 8-bit 60MHz +and 16-bit 30MHz parallel interfaces. + +Signed-off-by: Ze Huang +Tested-by: Aurelien Jarno +Tested-by: Junzhong Pan +Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-2-7cf9ea2477a1@linux.dev +Signed-off-by: Vinod Koul +(cherry picked from commit fe4bc1a08638309b6be1af37210930b856908eb7) +Signed-off-by: Han Gao +--- + drivers/phy/Kconfig | 1 + + drivers/phy/Makefile | 1 + + drivers/phy/spacemit/Kconfig | 13 ++ + drivers/phy/spacemit/Makefile | 2 + + drivers/phy/spacemit/phy-k1-usb2.c | 200 +++++++++++++++++++++++++++++ + 5 files changed, 217 insertions(+) + create mode 100644 drivers/phy/spacemit/Kconfig + create mode 100644 drivers/phy/spacemit/Makefile + create mode 100644 drivers/phy/spacemit/phy-k1-usb2.c + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index 1984c2e56122..95ee47f0fbc7 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -134,6 +134,7 @@ source "drivers/phy/rockchip/Kconfig" + source "drivers/phy/samsung/Kconfig" + source "drivers/phy/socionext/Kconfig" + source "drivers/phy/sophgo/Kconfig" ++source "drivers/phy/spacemit/Kconfig" + source "drivers/phy/st/Kconfig" + source "drivers/phy/starfive/Kconfig" + source "drivers/phy/sunplus/Kconfig" +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index a206133a3515..950dd4f14372 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -37,6 +37,7 @@ obj-y += allwinner/ \ + samsung/ \ + socionext/ \ + sophgo/ \ ++ spacemit/ \ + st/ \ + starfive/ \ + sunplus/ \ +diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig +new file mode 100644 +index 000000000000..0136aee2e8a2 +--- /dev/null ++++ b/drivers/phy/spacemit/Kconfig +@@ -0,0 +1,13 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++# ++# Phy drivers for SpacemiT platforms ++# ++config PHY_SPACEMIT_K1_USB2 ++ tristate "SpacemiT K1 USB 2.0 PHY support" ++ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF ++ depends on COMMON_CLK ++ depends on USB_COMMON ++ select GENERIC_PHY ++ help ++ Enable this to support K1 USB 2.0 PHY driver. This driver takes care of ++ enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. +diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile +new file mode 100644 +index 000000000000..fec0b425a948 +--- /dev/null ++++ b/drivers/phy/spacemit/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o +diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c +new file mode 100644 +index 000000000000..342061380012 +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k1-usb2.c +@@ -0,0 +1,200 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * SpacemiT K1 USB 2.0 PHY driver ++ * ++ * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd ++ * Copyright (C) 2025 Ze Huang ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PHY_RST_MODE_CTRL 0x04 ++#define PHY_PLL_RDY BIT(0) ++#define PHY_CLK_CDR_EN BIT(1) ++#define PHY_CLK_PLL_EN BIT(2) ++#define PHY_CLK_MAC_EN BIT(3) ++#define PHY_MAC_RSTN BIT(5) ++#define PHY_CDR_RSTN BIT(6) ++#define PHY_PLL_RSTN BIT(7) ++/* ++ * hs line state sel (Bit 13): ++ * - 1 (Default): Internal HS line state is set to 01 when usb_hs_tx_en is valid. ++ * - 0: Internal HS line state is always driven by usb_hs_lstate. ++ * ++ * fs line state sel (Bit 14): ++ * - 1 (Default): FS line state is determined by the output data ++ * (usb_fs_datain/b). ++ * - 0: FS line state is always determined by the input data (dmo/dpo). ++ */ ++#define PHY_HS_LINE_TX_MODE BIT(13) ++#define PHY_FS_LINE_TX_MODE BIT(14) ++ ++#define PHY_INIT_MODE_BITS (PHY_FS_LINE_TX_MODE | PHY_HS_LINE_TX_MODE) ++#define PHY_CLK_ENABLE_BITS (PHY_CLK_PLL_EN | PHY_CLK_CDR_EN | \ ++ PHY_CLK_MAC_EN) ++#define PHY_DEASSERT_RST_BITS (PHY_PLL_RSTN | PHY_CDR_RSTN | \ ++ PHY_MAC_RSTN) ++ ++#define PHY_TX_HOST_CTRL 0x10 ++#define PHY_HST_DISC_AUTO_CLR BIT(2) /* autoclear hs host disc when re-connect */ ++ ++#define PHY_HSTXP_HW_CTRL 0x34 ++#define PHY_HSTXP_RSTN BIT(2) /* generate reset for clock hstxp */ ++#define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */ ++#define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */ ++ ++#define PHY_PLL_DIV_CFG 0x98 ++#define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) ++#define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) ++#define PHY_FDIV_FRACT_20_21 BIT(12) /* fdiv_reg<21>, <20>, bit21 == bit20 */ ++/* ++ * freq_sel<1:0> ++ * if ref clk freq=24.0MHz-->freq_sel<2:0> == 3b'001, then internal divider value == 80 ++ */ ++#define PHY_FDIV_FRACT_0_1 GENMASK(14, 13) ++/* ++ * pll divider value selection ++ * 1: divider value will choose internal default value ,dependent on freq_sel<1:0> ++ * 0: divider value will be over ride by fdiv_reg<21:0> ++ */ ++#define PHY_DIV_LOCAL_EN BIT(15) ++ ++#define PHY_SEL_FREQ_24MHZ 0x01 ++#define FDIV_REG_MASK (PHY_FDIV_FRACT_20_21 | PHY_FDIV_FRACT_16_19 | \ ++ PHY_FDIV_FRACT_8_15) ++#define FDIV_REG_VAL 0x1ec4 /* 0x100 selects 24MHz, rest are default */ ++ ++#define K1_USB2PHY_RESET_TIME_MS 50 ++ ++struct spacemit_usb2phy { ++ struct phy *phy; ++ struct clk *clk; ++ struct regmap *regmap_base; ++}; ++ ++static const struct regmap_config phy_regmap_config = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ .max_register = 0x200, ++}; ++ ++static int spacemit_usb2phy_init(struct phy *phy) ++{ ++ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); ++ struct regmap *map = sphy->regmap_base; ++ u32 val; ++ int ret; ++ ++ ret = clk_enable(sphy->clk); ++ if (ret) { ++ dev_err(&phy->dev, "failed to enable clock\n"); ++ clk_disable(sphy->clk); ++ return ret; ++ } ++ ++ /* ++ * make sure the usb controller is not under reset process before ++ * any configuration ++ */ ++ usleep_range(150, 200); ++ ++ /* 24M ref clk */ ++ val = FIELD_PREP(FDIV_REG_MASK, FDIV_REG_VAL) | ++ FIELD_PREP(PHY_FDIV_FRACT_0_1, PHY_SEL_FREQ_24MHZ) | ++ PHY_DIV_LOCAL_EN; ++ regmap_write(map, PHY_PLL_DIV_CFG, val); ++ ++ ret = regmap_read_poll_timeout(map, PHY_RST_MODE_CTRL, val, ++ (val & PHY_PLL_RDY), ++ 500, K1_USB2PHY_RESET_TIME_MS * 1000); ++ if (ret) { ++ dev_err(&phy->dev, "wait PLLREADY timeout\n"); ++ clk_disable(sphy->clk); ++ return ret; ++ } ++ ++ /* release usb2 phy internal reset and enable clock gating */ ++ val = (PHY_INIT_MODE_BITS | PHY_CLK_ENABLE_BITS | PHY_DEASSERT_RST_BITS); ++ regmap_write(map, PHY_RST_MODE_CTRL, val); ++ ++ val = (PHY_HSTXP_RSTN | PHY_CLK_HSTXP_EN | PHY_HSTXP_MODE); ++ regmap_write(map, PHY_HSTXP_HW_CTRL, val); ++ ++ /* auto clear host disc */ ++ regmap_update_bits(map, PHY_TX_HOST_CTRL, PHY_HST_DISC_AUTO_CLR, ++ PHY_HST_DISC_AUTO_CLR); ++ ++ return 0; ++} ++ ++static int spacemit_usb2phy_exit(struct phy *phy) ++{ ++ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); ++ ++ clk_disable(sphy->clk); ++ ++ return 0; ++} ++ ++static const struct phy_ops spacemit_usb2phy_ops = { ++ .init = spacemit_usb2phy_init, ++ .exit = spacemit_usb2phy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++static int spacemit_usb2phy_probe(struct platform_device *pdev) ++{ ++ struct phy_provider *phy_provider; ++ struct device *dev = &pdev->dev; ++ struct spacemit_usb2phy *sphy; ++ void __iomem *base; ++ ++ sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); ++ if (!sphy) ++ return -ENOMEM; ++ ++ sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL); ++ if (IS_ERR(sphy->clk)) ++ return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ sphy->regmap_base = devm_regmap_init_mmio(dev, base, &phy_regmap_config); ++ if (IS_ERR(sphy->regmap_base)) ++ return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n"); ++ ++ sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops); ++ if (IS_ERR(sphy->phy)) ++ return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); ++ ++ phy_set_drvdata(sphy->phy, sphy); ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static const struct of_device_id spacemit_usb2phy_dt_match[] = { ++ { .compatible = "spacemit,k1-usb2-phy", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); ++ ++static struct platform_driver spacemit_usb2_phy_driver = { ++ .probe = spacemit_usb2phy_probe, ++ .driver = { ++ .name = "spacemit-usb2-phy", ++ .of_match_table = spacemit_usb2phy_dt_match, ++ }, ++}; ++module_platform_driver(spacemit_usb2_phy_driver); ++ ++MODULE_DESCRIPTION("Spacemit USB 2.0 PHY driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch b/SPECS/linux-lts-kmhv2/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch new file mode 100644 index 0000000000..dc4568a151 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch @@ -0,0 +1,44 @@ +From 11169d35e4ee7faf38d3e24da227dd6ca781964d Mon Sep 17 00:00:00 2001 +From: Ze Huang +Date: Sun, 11 Jan 2026 14:41:02 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add USB2 PHY node for K1 + +K1's DWC3 USB 3.0 controller requires two separate PHYs to function: +the USB 3.0 combophy (for SuperSpeed) and a USB 2.0 PHY (for High-Speed, +Full-Speed, etc.). + +Add node for this second USB 2.0 PHY (usbphy2). + +Tested-by: Aurelien Jarno +Signed-off-by: Ze Huang +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-1-f5ebd546e904@linux.dev +Signed-off-by: Yixun Lan +(cherry picked from commit 9d591fef025d5008f23ab339a10006b151150578) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 4c045da95d72..dfabda5ed4fa 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -429,6 +429,14 @@ i2c5: i2c@d4013800 { + status = "disabled"; + }; + ++ usbphy2: phy@c0a30000 { ++ compatible = "spacemit,k1-usb2-phy"; ++ reg = <0x0 0xc0a30000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_USB30>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + combo_phy: phy@c0b10000 { + compatible = "spacemit,k1-combo-phy"; + reg = <0x0 0xc0b10000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0087-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch b/SPECS/linux-lts-kmhv2/0087-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch deleted file mode 100644 index 3792ddbbb7..0000000000 --- a/SPECS/linux-lts-kmhv2/0087-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 44a7ef4342a13da4cdca6f3bde4e71312846a07f Mon Sep 17 00:00:00 2001 -From: Encrow Thorne -Date: Tue, 30 Dec 2025 23:06:53 +0800 -Subject: [PATCH 087/467] UPSTREAM: riscv: dts: spacemit: add reset property - -Add resets property to K1 I2C node. - -Signed-off-by: Encrow Thorne -Link: https://lore.kernel.org/r/20251230150653.42097-3-jyc0019@gmail.com -Signed-off-by: Yixun Lan -(cherry picked from commit 7d6fe7e381d2912300df06e1a7e7a6f6a9269af0) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 86d1db14e2ee..4c045da95d72 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -368,6 +368,7 @@ i2c0: i2c@d4010800 { - <&syscon_apbc CLK_TWSI0_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI0>; - interrupts = <36>; - status = "disabled"; - }; -@@ -381,6 +382,7 @@ i2c1: i2c@d4011000 { - <&syscon_apbc CLK_TWSI1_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI1>; - interrupts = <37>; - status = "disabled"; - }; -@@ -394,6 +396,7 @@ i2c2: i2c@d4012000 { - <&syscon_apbc CLK_TWSI2_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI2>; - interrupts = <38>; - status = "disabled"; - }; -@@ -407,6 +410,7 @@ i2c4: i2c@d4012800 { - <&syscon_apbc CLK_TWSI4_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI4>; - interrupts = <40>; - status = "disabled"; - }; -@@ -420,6 +424,7 @@ i2c5: i2c@d4013800 { - <&syscon_apbc CLK_TWSI5_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI5>; - interrupts = <41>; - status = "disabled"; - }; -@@ -490,6 +495,7 @@ i2c6: i2c@d4018800 { - <&syscon_apbc CLK_TWSI6_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI6>; - interrupts = <70>; - status = "disabled"; - }; -@@ -593,6 +599,7 @@ i2c7: i2c@d401d000 { - <&syscon_apbc CLK_TWSI7_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI7>; - interrupts = <18>; - status = "disabled"; - }; -@@ -606,6 +613,7 @@ i2c8: i2c@d401d800 { - <&syscon_apbc CLK_TWSI8_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI8>; - interrupts = <19>; - status = "disabled"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0088-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch b/SPECS/linux-lts-kmhv2/0088-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch deleted file mode 100644 index 77424cfb1a..0000000000 --- a/SPECS/linux-lts-kmhv2/0088-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch +++ /dev/null @@ -1,69 +0,0 @@ -From e521f4b92c204c0a9d6242ff41c3c872440dbab8 Mon Sep 17 00:00:00 2001 -From: Ze Huang -Date: Fri, 17 Oct 2025 22:49:52 +0800 -Subject: [PATCH 088/467] UPSTREAM: dt-bindings: phy: spacemit: add K1 USB2 PHY - -Add support for USB2 PHY found on SpacemiT K1 SoC. - -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Ze Huang -Tested-by: Aurelien Jarno -Tested-by: Junzhong Pan -Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-1-7cf9ea2477a1@linux.dev -Signed-off-by: Vinod Koul -(cherry picked from commit 61b84d5b20af2a4c9944972202c1386026598928) -Signed-off-by: Han Gao ---- - .../bindings/phy/spacemit,usb2-phy.yaml | 40 +++++++++++++++++++ - 1 file changed, 40 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -new file mode 100644 -index 000000000000..43eaca90d88c ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -@@ -0,0 +1,40 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K1 SoC USB 2.0 PHY -+ -+maintainers: -+ - Ze Huang -+ -+properties: -+ compatible: -+ const: spacemit,k1-usb2-phy -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ maxItems: 1 -+ -+ "#phy-cells": -+ const: 0 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - "#phy-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ usb-phy@c09c0000 { -+ compatible = "spacemit,k1-usb2-phy"; -+ reg = <0xc09c0000 0x200>; -+ clocks = <&syscon_apmu 15>; -+ #phy-cells = <0>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch b/SPECS/linux-lts-kmhv2/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch new file mode 100644 index 0000000000..f327e7bfc3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch @@ -0,0 +1,59 @@ +From f38cd0cdcf8e8fecf3db47eb57caf5849e92aa36 Mon Sep 17 00:00:00 2001 +From: Ze Huang +Date: Sun, 11 Jan 2026 14:41:03 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add DWC3 USB 3.0 + controller node for K1 + +Add node for the Synopsys DWC3 USB 3.0 host controller on the K1 SoC. +The controller resides on the 'storage-bus' and uses its DMA +translations. + +Tested-by: Aurelien Jarno +Signed-off-by: Ze Huang +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-2-f5ebd546e904@linux.dev +Signed-off-by: Yixun Lan +(cherry picked from commit 6e8dcd141833a23d7117fe16896f6d5dfdb2e112) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index dfabda5ed4fa..137fc26ddc29 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -1170,6 +1170,30 @@ storage-bus { + #size-cells = <2>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; + ++ usb_dwc3: usb@c0a00000 { ++ compatible = "spacemit,k1-dwc3"; ++ reg = <0x0 0xc0a00000 0x0 0x10000>; ++ clocks = <&syscon_apmu CLK_USB30>; ++ clock-names = "usbdrd30"; ++ interrupts = <125>; ++ phys = <&usbphy2>, <&combo_phy PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi"; ++ resets = <&syscon_apmu RESET_USB30_AHB>, ++ <&syscon_apmu RESET_USB30_VCC>, ++ <&syscon_apmu RESET_USB30_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ reset-delay = <2>; ++ snps,hsphy_interface = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,dis_rxdet_inp3_quirk; ++ status = "disabled"; ++ }; ++ + emmc: mmc@d4281000 { + compatible = "spacemit,k1-sdhci"; + reg = <0x0 0xd4281000 0x0 0x200>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0089-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch b/SPECS/linux-lts-kmhv2/0089-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch deleted file mode 100644 index 5dc7268528..0000000000 --- a/SPECS/linux-lts-kmhv2/0089-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch +++ /dev/null @@ -1,297 +0,0 @@ -From fcc3def145a5601559279ba46a849f87baebfb1e Mon Sep 17 00:00:00 2001 -From: Ze Huang -Date: Fri, 17 Oct 2025 22:49:53 +0800 -Subject: [PATCH 089/467] UPSTREAM: phy: spacemit: support K1 USB2.0 PHY - controller - -The SpacemiT K1 SoC includes three USB ports: - -- One USB2.0 OTG port -- One USB2.0 host-only port -- One USB3.0 port with an integrated USB2.0 DRD interface - -Each of these ports is connected to a USB2.0 PHY responsible for USB2 -transmission. - -This commit adds support for the SpacemiT K1 USB2.0 PHY, which is -compliant with the USB 2.0 specification and supports both 8-bit 60MHz -and 16-bit 30MHz parallel interfaces. - -Signed-off-by: Ze Huang -Tested-by: Aurelien Jarno -Tested-by: Junzhong Pan -Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-2-7cf9ea2477a1@linux.dev -Signed-off-by: Vinod Koul -(cherry picked from commit fe4bc1a08638309b6be1af37210930b856908eb7) -Signed-off-by: Han Gao ---- - drivers/phy/Kconfig | 1 + - drivers/phy/Makefile | 1 + - drivers/phy/spacemit/Kconfig | 13 ++ - drivers/phy/spacemit/Makefile | 2 + - drivers/phy/spacemit/phy-k1-usb2.c | 200 +++++++++++++++++++++++++++++ - 5 files changed, 217 insertions(+) - create mode 100644 drivers/phy/spacemit/Kconfig - create mode 100644 drivers/phy/spacemit/Makefile - create mode 100644 drivers/phy/spacemit/phy-k1-usb2.c - -diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig -index 1984c2e56122..95ee47f0fbc7 100644 ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -134,6 +134,7 @@ source "drivers/phy/rockchip/Kconfig" - source "drivers/phy/samsung/Kconfig" - source "drivers/phy/socionext/Kconfig" - source "drivers/phy/sophgo/Kconfig" -+source "drivers/phy/spacemit/Kconfig" - source "drivers/phy/st/Kconfig" - source "drivers/phy/starfive/Kconfig" - source "drivers/phy/sunplus/Kconfig" -diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile -index a206133a3515..950dd4f14372 100644 ---- a/drivers/phy/Makefile -+++ b/drivers/phy/Makefile -@@ -37,6 +37,7 @@ obj-y += allwinner/ \ - samsung/ \ - socionext/ \ - sophgo/ \ -+ spacemit/ \ - st/ \ - starfive/ \ - sunplus/ \ -diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig -new file mode 100644 -index 000000000000..0136aee2e8a2 ---- /dev/null -+++ b/drivers/phy/spacemit/Kconfig -@@ -0,0 +1,13 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+# -+# Phy drivers for SpacemiT platforms -+# -+config PHY_SPACEMIT_K1_USB2 -+ tristate "SpacemiT K1 USB 2.0 PHY support" -+ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF -+ depends on COMMON_CLK -+ depends on USB_COMMON -+ select GENERIC_PHY -+ help -+ Enable this to support K1 USB 2.0 PHY driver. This driver takes care of -+ enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. -diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile -new file mode 100644 -index 000000000000..fec0b425a948 ---- /dev/null -+++ b/drivers/phy/spacemit/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o -diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c -new file mode 100644 -index 000000000000..342061380012 ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k1-usb2.c -@@ -0,0 +1,200 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * SpacemiT K1 USB 2.0 PHY driver -+ * -+ * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd -+ * Copyright (C) 2025 Ze Huang -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define PHY_RST_MODE_CTRL 0x04 -+#define PHY_PLL_RDY BIT(0) -+#define PHY_CLK_CDR_EN BIT(1) -+#define PHY_CLK_PLL_EN BIT(2) -+#define PHY_CLK_MAC_EN BIT(3) -+#define PHY_MAC_RSTN BIT(5) -+#define PHY_CDR_RSTN BIT(6) -+#define PHY_PLL_RSTN BIT(7) -+/* -+ * hs line state sel (Bit 13): -+ * - 1 (Default): Internal HS line state is set to 01 when usb_hs_tx_en is valid. -+ * - 0: Internal HS line state is always driven by usb_hs_lstate. -+ * -+ * fs line state sel (Bit 14): -+ * - 1 (Default): FS line state is determined by the output data -+ * (usb_fs_datain/b). -+ * - 0: FS line state is always determined by the input data (dmo/dpo). -+ */ -+#define PHY_HS_LINE_TX_MODE BIT(13) -+#define PHY_FS_LINE_TX_MODE BIT(14) -+ -+#define PHY_INIT_MODE_BITS (PHY_FS_LINE_TX_MODE | PHY_HS_LINE_TX_MODE) -+#define PHY_CLK_ENABLE_BITS (PHY_CLK_PLL_EN | PHY_CLK_CDR_EN | \ -+ PHY_CLK_MAC_EN) -+#define PHY_DEASSERT_RST_BITS (PHY_PLL_RSTN | PHY_CDR_RSTN | \ -+ PHY_MAC_RSTN) -+ -+#define PHY_TX_HOST_CTRL 0x10 -+#define PHY_HST_DISC_AUTO_CLR BIT(2) /* autoclear hs host disc when re-connect */ -+ -+#define PHY_HSTXP_HW_CTRL 0x34 -+#define PHY_HSTXP_RSTN BIT(2) /* generate reset for clock hstxp */ -+#define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */ -+#define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */ -+ -+#define PHY_PLL_DIV_CFG 0x98 -+#define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) -+#define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) -+#define PHY_FDIV_FRACT_20_21 BIT(12) /* fdiv_reg<21>, <20>, bit21 == bit20 */ -+/* -+ * freq_sel<1:0> -+ * if ref clk freq=24.0MHz-->freq_sel<2:0> == 3b'001, then internal divider value == 80 -+ */ -+#define PHY_FDIV_FRACT_0_1 GENMASK(14, 13) -+/* -+ * pll divider value selection -+ * 1: divider value will choose internal default value ,dependent on freq_sel<1:0> -+ * 0: divider value will be over ride by fdiv_reg<21:0> -+ */ -+#define PHY_DIV_LOCAL_EN BIT(15) -+ -+#define PHY_SEL_FREQ_24MHZ 0x01 -+#define FDIV_REG_MASK (PHY_FDIV_FRACT_20_21 | PHY_FDIV_FRACT_16_19 | \ -+ PHY_FDIV_FRACT_8_15) -+#define FDIV_REG_VAL 0x1ec4 /* 0x100 selects 24MHz, rest are default */ -+ -+#define K1_USB2PHY_RESET_TIME_MS 50 -+ -+struct spacemit_usb2phy { -+ struct phy *phy; -+ struct clk *clk; -+ struct regmap *regmap_base; -+}; -+ -+static const struct regmap_config phy_regmap_config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .max_register = 0x200, -+}; -+ -+static int spacemit_usb2phy_init(struct phy *phy) -+{ -+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); -+ struct regmap *map = sphy->regmap_base; -+ u32 val; -+ int ret; -+ -+ ret = clk_enable(sphy->clk); -+ if (ret) { -+ dev_err(&phy->dev, "failed to enable clock\n"); -+ clk_disable(sphy->clk); -+ return ret; -+ } -+ -+ /* -+ * make sure the usb controller is not under reset process before -+ * any configuration -+ */ -+ usleep_range(150, 200); -+ -+ /* 24M ref clk */ -+ val = FIELD_PREP(FDIV_REG_MASK, FDIV_REG_VAL) | -+ FIELD_PREP(PHY_FDIV_FRACT_0_1, PHY_SEL_FREQ_24MHZ) | -+ PHY_DIV_LOCAL_EN; -+ regmap_write(map, PHY_PLL_DIV_CFG, val); -+ -+ ret = regmap_read_poll_timeout(map, PHY_RST_MODE_CTRL, val, -+ (val & PHY_PLL_RDY), -+ 500, K1_USB2PHY_RESET_TIME_MS * 1000); -+ if (ret) { -+ dev_err(&phy->dev, "wait PLLREADY timeout\n"); -+ clk_disable(sphy->clk); -+ return ret; -+ } -+ -+ /* release usb2 phy internal reset and enable clock gating */ -+ val = (PHY_INIT_MODE_BITS | PHY_CLK_ENABLE_BITS | PHY_DEASSERT_RST_BITS); -+ regmap_write(map, PHY_RST_MODE_CTRL, val); -+ -+ val = (PHY_HSTXP_RSTN | PHY_CLK_HSTXP_EN | PHY_HSTXP_MODE); -+ regmap_write(map, PHY_HSTXP_HW_CTRL, val); -+ -+ /* auto clear host disc */ -+ regmap_update_bits(map, PHY_TX_HOST_CTRL, PHY_HST_DISC_AUTO_CLR, -+ PHY_HST_DISC_AUTO_CLR); -+ -+ return 0; -+} -+ -+static int spacemit_usb2phy_exit(struct phy *phy) -+{ -+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); -+ -+ clk_disable(sphy->clk); -+ -+ return 0; -+} -+ -+static const struct phy_ops spacemit_usb2phy_ops = { -+ .init = spacemit_usb2phy_init, -+ .exit = spacemit_usb2phy_exit, -+ .owner = THIS_MODULE, -+}; -+ -+static int spacemit_usb2phy_probe(struct platform_device *pdev) -+{ -+ struct phy_provider *phy_provider; -+ struct device *dev = &pdev->dev; -+ struct spacemit_usb2phy *sphy; -+ void __iomem *base; -+ -+ sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); -+ if (!sphy) -+ return -ENOMEM; -+ -+ sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL); -+ if (IS_ERR(sphy->clk)) -+ return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); -+ -+ base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ sphy->regmap_base = devm_regmap_init_mmio(dev, base, &phy_regmap_config); -+ if (IS_ERR(sphy->regmap_base)) -+ return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n"); -+ -+ sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops); -+ if (IS_ERR(sphy->phy)) -+ return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); -+ -+ phy_set_drvdata(sphy->phy, sphy); -+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id spacemit_usb2phy_dt_match[] = { -+ { .compatible = "spacemit,k1-usb2-phy", }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); -+ -+static struct platform_driver spacemit_usb2_phy_driver = { -+ .probe = spacemit_usb2phy_probe, -+ .driver = { -+ .name = "spacemit-usb2-phy", -+ .of_match_table = spacemit_usb2phy_dt_match, -+ }, -+}; -+module_platform_driver(spacemit_usb2_phy_driver); -+ -+MODULE_DESCRIPTION("Spacemit USB 2.0 PHY driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch b/SPECS/linux-lts-kmhv2/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch new file mode 100644 index 0000000000..ada9b260b3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch @@ -0,0 +1,88 @@ +From 35bdc15291717adfaa52c4c9d060b5da8fac5ddf Mon Sep 17 00:00:00 2001 +From: Ze Huang +Date: Sun, 11 Jan 2026 14:41:04 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Enable USB3.0 on + BananaPi-F3 + +Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the +Banana Pi F3 board. + +The board utilizes a VLI VL817 hub, which requires two separate power +supplies: one VBUS and one for hub itself. Add two GPIO-controlled +fixed-regulators to manage this. + +Tested-by: Aurelien Jarno +Signed-off-by: Ze Huang +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-3-f5ebd546e904@linux.dev +Signed-off-by: Yixun Lan +(cherry picked from commit c7e62c4eea026d42d192a0b86ce7313086ef2093) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 46 +++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 3f10efd925dc..5971605754b3 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -59,6 +59,25 @@ reg_vcc_4v: vcc-4v { + regulator-always-on; + vin-supply = <®_dc_in>; + }; ++ ++ usb3-vbus-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB30_VBUS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ usb3_hub_5v: usb3-hub-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB30_HUB"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; + }; + + &combo_phy { +@@ -313,3 +332,30 @@ &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub_2_0: hub@1 { ++ compatible = "usb2109,2817"; ++ reg = <0x1>; ++ vdd-supply = <&usb3_hub_5v>; ++ peer-hub = <&hub_3_0>; ++ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; ++ }; ++ ++ hub_3_0: hub@2 { ++ compatible = "usb2109,817"; ++ reg = <0x2>; ++ vdd-supply = <&usb3_hub_5v>; ++ peer-hub = <&hub_2_0>; ++ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch b/SPECS/linux-lts-kmhv2/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch new file mode 100644 index 0000000000..3e646a9468 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch @@ -0,0 +1,44 @@ +From 58100bb2e0beb94bf6f7d14ee1fbc0ba755686ab Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 2 Jan 2026 15:00:22 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pinctrl: spacemit: convert drive + strength to schema format + +In order to better extend the pinctrl support for future new SoC, convert +drive strength setting from free form text to more standard schema format. + +Signed-off-by: Yixun Lan +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Linus Walleij +(cherry picked from commit c3efac0592f88ab48c8eef028268e6514908be51) +Signed-off-by: Han Gao +--- + .../bindings/pinctrl/spacemit,k1-pinctrl.yaml | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +index d80e88aa07b4..609d7db97822 100644 +--- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml ++++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +@@ -72,10 +72,14 @@ patternProperties: + enum: [ 0, 1 ] + + drive-strength: +- description: | +- typical current when output high level. +- 1.8V output: 11, 21, 32, 42 (mA) +- 3.3V output: 7, 10, 13, 16, 19, 23, 26, 29 (mA) ++ description: ++ typical current (in mA) when the output at high level. ++ oneOf: ++ - enum: [ 11, 21, 32, 42 ] ++ description: For K1 SoC, 1.8V voltage output ++ ++ - enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ] ++ description: For K1 SoC, 3.3V voltage output + + input-schmitt: + description: | +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0090-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch b/SPECS/linux-lts-kmhv2/0090-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch deleted file mode 100644 index 091c89cba7..0000000000 --- a/SPECS/linux-lts-kmhv2/0090-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 70d873fa83fb580cdd0722e586b71f7d82918b64 Mon Sep 17 00:00:00 2001 -From: Ze Huang -Date: Sun, 11 Jan 2026 14:41:02 +0800 -Subject: [PATCH 090/467] UPSTREAM: riscv: dts: spacemit: Add USB2 PHY node for - K1 - -K1's DWC3 USB 3.0 controller requires two separate PHYs to function: -the USB 3.0 combophy (for SuperSpeed) and a USB 2.0 PHY (for High-Speed, -Full-Speed, etc.). - -Add node for this second USB 2.0 PHY (usbphy2). - -Tested-by: Aurelien Jarno -Signed-off-by: Ze Huang -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-1-f5ebd546e904@linux.dev -Signed-off-by: Yixun Lan -(cherry picked from commit 9d591fef025d5008f23ab339a10006b151150578) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 4c045da95d72..dfabda5ed4fa 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -429,6 +429,14 @@ i2c5: i2c@d4013800 { - status = "disabled"; - }; - -+ usbphy2: phy@c0a30000 { -+ compatible = "spacemit,k1-usb2-phy"; -+ reg = <0x0 0xc0a30000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_USB30>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - combo_phy: phy@c0b10000 { - compatible = "spacemit,k1-combo-phy"; - reg = <0x0 0xc0b10000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch b/SPECS/linux-lts-kmhv2/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch new file mode 100644 index 0000000000..39afc5d902 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch @@ -0,0 +1,51 @@ +From 2038df152864bcab073a9afa519466c854b79d21 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 2 Jan 2026 15:00:23 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pinctrl: spacemit: add K3 SoC + support + +Add new compatible string for SpacemiT K3 SoC, the pinctrl IP shares +almost same logic with previous K1 generation, but has different register +offset and pin configuration, for example the drive strength and +schmitter trigger settings has been changed. + +Signed-off-by: Yixun Lan +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Linus Walleij +(cherry picked from commit 5adaa1a8c08839617e5a6385fe05a8baa63e355f) +Signed-off-by: Han Gao +--- + .../bindings/pinctrl/spacemit,k1-pinctrl.yaml | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +index 609d7db97822..9a76cffcbaee 100644 +--- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml ++++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +@@ -11,7 +11,9 @@ maintainers: + + properties: + compatible: +- const: spacemit,k1-pinctrl ++ enum: ++ - spacemit,k1-pinctrl ++ - spacemit,k3-pinctrl + + reg: + items: +@@ -81,6 +83,12 @@ patternProperties: + - enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ] + description: For K1 SoC, 3.3V voltage output + ++ - enum: [ 2, 4, 6, 7, 9, 11, 13, 14, 21, 23, 25, 26, 28, 30, 31, 33 ] ++ description: For K3 SoC, 1.8V voltage output ++ ++ - enum: [ 3, 5, 7, 9, 11, 13, 15, 17, 25, 27, 29, 31, 33, 35, 37, 38 ] ++ description: For K3 SoC, 1.8V voltage output ++ + input-schmitt: + description: | + typical threshold for schmitt trigger. +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0091-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch b/SPECS/linux-lts-kmhv2/0091-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch deleted file mode 100644 index f42a890268..0000000000 --- a/SPECS/linux-lts-kmhv2/0091-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch +++ /dev/null @@ -1,59 +0,0 @@ -From b30b757a7e4570e7923bf3fcebcf0ff34a42b70c Mon Sep 17 00:00:00 2001 -From: Ze Huang -Date: Sun, 11 Jan 2026 14:41:03 +0800 -Subject: [PATCH 091/467] UPSTREAM: riscv: dts: spacemit: Add DWC3 USB 3.0 - controller node for K1 - -Add node for the Synopsys DWC3 USB 3.0 host controller on the K1 SoC. -The controller resides on the 'storage-bus' and uses its DMA -translations. - -Tested-by: Aurelien Jarno -Signed-off-by: Ze Huang -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-2-f5ebd546e904@linux.dev -Signed-off-by: Yixun Lan -(cherry picked from commit 6e8dcd141833a23d7117fe16896f6d5dfdb2e112) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 24 ++++++++++++++++++++++++ - 1 file changed, 24 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index dfabda5ed4fa..137fc26ddc29 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -1170,6 +1170,30 @@ storage-bus { - #size-cells = <2>; - dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; - -+ usb_dwc3: usb@c0a00000 { -+ compatible = "spacemit,k1-dwc3"; -+ reg = <0x0 0xc0a00000 0x0 0x10000>; -+ clocks = <&syscon_apmu CLK_USB30>; -+ clock-names = "usbdrd30"; -+ interrupts = <125>; -+ phys = <&usbphy2>, <&combo_phy PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi"; -+ resets = <&syscon_apmu RESET_USB30_AHB>, -+ <&syscon_apmu RESET_USB30_VCC>, -+ <&syscon_apmu RESET_USB30_PHY>; -+ reset-names = "ahb", "vcc", "phy"; -+ reset-delay = <2>; -+ snps,hsphy_interface = "utmi"; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ snps,dis_rxdet_inp3_quirk; -+ status = "disabled"; -+ }; -+ - emmc: mmc@d4281000 { - compatible = "spacemit,k1-sdhci"; - reg = <0x0 0xd4281000 0x0 0x200>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch b/SPECS/linux-lts-kmhv2/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch new file mode 100644 index 0000000000..36707ca688 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch @@ -0,0 +1,448 @@ +From fa64b4a9c989f85c6522c5cb06ef127c6dab3d27 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 2 Jan 2026 15:00:24 +0800 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: k3: add initial pin support + +For the pinctrl IP of SpacemiT's K3 SoC, it has different register offset +comparing with previous SoC generation, so introduce a function to do the +pin to offset mapping. Also add all the pinctrl data. + +Signed-off-by: Yixun Lan +Signed-off-by: Linus Walleij +(cherry picked from commit 7412311c4655497b6ab6dd7b802f9390f0f57dc7) +Signed-off-by: Han Gao +--- + drivers/pinctrl/spacemit/Kconfig | 4 +- + drivers/pinctrl/spacemit/pinctrl-k1.c | 354 +++++++++++++++++++++++++- + 2 files changed, 352 insertions(+), 6 deletions(-) + +diff --git a/drivers/pinctrl/spacemit/Kconfig b/drivers/pinctrl/spacemit/Kconfig +index d6f6017fd097..c021d51033d1 100644 +--- a/drivers/pinctrl/spacemit/Kconfig ++++ b/drivers/pinctrl/spacemit/Kconfig +@@ -4,7 +4,7 @@ + # + + config PINCTRL_SPACEMIT_K1 +- bool "SpacemiT K1 SoC Pinctrl driver" ++ bool "SpacemiT K1/K3 SoC Pinctrl driver" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on OF + default ARCH_SPACEMIT +@@ -12,7 +12,7 @@ config PINCTRL_SPACEMIT_K1 + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help +- Say Y to select the pinctrl driver for K1 SoC. ++ Say Y to select the pinctrl driver for K1/K3 SoC. + This pin controller allows selecting the mux function for + each pin. This driver can also be built as a module called + pinctrl-k1. +diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c +index 33af9b5791c1..441817f539e3 100644 +--- a/drivers/pinctrl/spacemit/pinctrl-k1.c ++++ b/drivers/pinctrl/spacemit/pinctrl-k1.c +@@ -66,6 +66,7 @@ struct spacemit_pinctrl_data { + const struct pinctrl_pin_desc *pins; + const struct spacemit_pin *data; + u16 npins; ++ unsigned int (*pin_to_offset)(unsigned int pin); + }; + + struct spacemit_pin_mux_config { +@@ -79,7 +80,7 @@ struct spacemit_pin_drv_strength { + }; + + /* map pin id to pinctrl register offset, refer MFPR definition */ +-static unsigned int spacemit_pin_to_offset(unsigned int pin) ++static unsigned int spacemit_k1_pin_to_offset(unsigned int pin) + { + unsigned int offset = 0; + +@@ -124,10 +125,17 @@ static unsigned int spacemit_pin_to_offset(unsigned int pin) + return offset << 2; + } + ++static unsigned int spacemit_k3_pin_to_offset(unsigned int pin) ++{ ++ unsigned int offset = pin > 130 ? (pin + 2) : pin; ++ ++ return offset << 2; ++} ++ + static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, + unsigned int pin) + { +- return pctrl->regs + spacemit_pin_to_offset(pin); ++ return pctrl->regs + pctrl->data->pin_to_offset(pin); + } + + static u16 spacemit_dt_get_pin(u32 value) +@@ -177,7 +185,7 @@ static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev, + void __iomem *reg; + u32 value; + +- seq_printf(seq, "offset: 0x%04x ", spacemit_pin_to_offset(pin)); ++ seq_printf(seq, "offset: 0x%04x ", pctrl->data->pin_to_offset(pin)); + seq_printf(seq, "type: %s ", io_type_desc[type]); + + reg = spacemit_pin_to_reg(pctrl, pin); +@@ -1042,10 +1050,348 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { + .pins = k1_pin_desc, + .data = k1_pin_data, + .npins = ARRAY_SIZE(k1_pin_desc), ++ .pin_to_offset = spacemit_k1_pin_to_offset, ++}; ++ ++static const struct pinctrl_pin_desc k3_pin_desc[] = { ++ PINCTRL_PIN(0, "GPIO_00"), ++ PINCTRL_PIN(1, "GPIO_01"), ++ PINCTRL_PIN(2, "GPIO_02"), ++ PINCTRL_PIN(3, "GPIO_03"), ++ PINCTRL_PIN(4, "GPIO_04"), ++ PINCTRL_PIN(5, "GPIO_05"), ++ PINCTRL_PIN(6, "GPIO_06"), ++ PINCTRL_PIN(7, "GPIO_07"), ++ PINCTRL_PIN(8, "GPIO_08"), ++ PINCTRL_PIN(9, "GPIO_09"), ++ PINCTRL_PIN(10, "GPIO_10"), ++ PINCTRL_PIN(11, "GPIO_11"), ++ PINCTRL_PIN(12, "GPIO_12"), ++ PINCTRL_PIN(13, "GPIO_13"), ++ PINCTRL_PIN(14, "GPIO_14"), ++ PINCTRL_PIN(15, "GPIO_15"), ++ PINCTRL_PIN(16, "GPIO_16"), ++ PINCTRL_PIN(17, "GPIO_17"), ++ PINCTRL_PIN(18, "GPIO_18"), ++ PINCTRL_PIN(19, "GPIO_19"), ++ PINCTRL_PIN(20, "GPIO_20"), ++ PINCTRL_PIN(21, "GPIO_21"), ++ PINCTRL_PIN(22, "GPIO_22"), ++ PINCTRL_PIN(23, "GPIO_23"), ++ PINCTRL_PIN(24, "GPIO_24"), ++ PINCTRL_PIN(25, "GPIO_25"), ++ PINCTRL_PIN(26, "GPIO_26"), ++ PINCTRL_PIN(27, "GPIO_27"), ++ PINCTRL_PIN(28, "GPIO_28"), ++ PINCTRL_PIN(29, "GPIO_29"), ++ PINCTRL_PIN(30, "GPIO_30"), ++ PINCTRL_PIN(31, "GPIO_31"), ++ PINCTRL_PIN(32, "GPIO_32"), ++ PINCTRL_PIN(33, "GPIO_33"), ++ PINCTRL_PIN(34, "GPIO_34"), ++ PINCTRL_PIN(35, "GPIO_35"), ++ PINCTRL_PIN(36, "GPIO_36"), ++ PINCTRL_PIN(37, "GPIO_37"), ++ PINCTRL_PIN(38, "GPIO_38"), ++ PINCTRL_PIN(39, "GPIO_39"), ++ PINCTRL_PIN(40, "GPIO_40"), ++ PINCTRL_PIN(41, "GPIO_41"), ++ PINCTRL_PIN(42, "GPIO_42"), ++ PINCTRL_PIN(43, "GPIO_43"), ++ PINCTRL_PIN(44, "GPIO_44"), ++ PINCTRL_PIN(45, "GPIO_45"), ++ PINCTRL_PIN(46, "GPIO_46"), ++ PINCTRL_PIN(47, "GPIO_47"), ++ PINCTRL_PIN(48, "GPIO_48"), ++ PINCTRL_PIN(49, "GPIO_49"), ++ PINCTRL_PIN(50, "GPIO_50"), ++ PINCTRL_PIN(51, "GPIO_51"), ++ PINCTRL_PIN(52, "GPIO_52"), ++ PINCTRL_PIN(53, "GPIO_53"), ++ PINCTRL_PIN(54, "GPIO_54"), ++ PINCTRL_PIN(55, "GPIO_55"), ++ PINCTRL_PIN(56, "GPIO_56"), ++ PINCTRL_PIN(57, "GPIO_57"), ++ PINCTRL_PIN(58, "GPIO_58"), ++ PINCTRL_PIN(59, "GPIO_59"), ++ PINCTRL_PIN(60, "GPIO_60"), ++ PINCTRL_PIN(61, "GPIO_61"), ++ PINCTRL_PIN(62, "GPIO_62"), ++ PINCTRL_PIN(63, "GPIO_63"), ++ PINCTRL_PIN(64, "GPIO_64"), ++ PINCTRL_PIN(65, "GPIO_65"), ++ PINCTRL_PIN(66, "GPIO_66"), ++ PINCTRL_PIN(67, "GPIO_67"), ++ PINCTRL_PIN(68, "GPIO_68"), ++ PINCTRL_PIN(69, "GPIO_69"), ++ PINCTRL_PIN(70, "GPIO_70"), ++ PINCTRL_PIN(71, "GPIO_71"), ++ PINCTRL_PIN(72, "GPIO_72"), ++ PINCTRL_PIN(73, "GPIO_73"), ++ PINCTRL_PIN(74, "GPIO_74"), ++ PINCTRL_PIN(75, "GPIO_75"), ++ PINCTRL_PIN(76, "GPIO_76"), ++ PINCTRL_PIN(77, "GPIO_77"), ++ PINCTRL_PIN(78, "GPIO_78"), ++ PINCTRL_PIN(79, "GPIO_79"), ++ PINCTRL_PIN(80, "GPIO_80"), ++ PINCTRL_PIN(81, "GPIO_81"), ++ PINCTRL_PIN(82, "GPIO_82"), ++ PINCTRL_PIN(83, "GPIO_83"), ++ PINCTRL_PIN(84, "GPIO_84"), ++ PINCTRL_PIN(85, "GPIO_85"), ++ PINCTRL_PIN(86, "GPIO_86"), ++ PINCTRL_PIN(87, "GPIO_87"), ++ PINCTRL_PIN(88, "GPIO_88"), ++ PINCTRL_PIN(89, "GPIO_89"), ++ PINCTRL_PIN(90, "GPIO_90"), ++ PINCTRL_PIN(91, "GPIO_91"), ++ PINCTRL_PIN(92, "GPIO_92"), ++ PINCTRL_PIN(93, "GPIO_93"), ++ PINCTRL_PIN(94, "GPIO_94"), ++ PINCTRL_PIN(95, "GPIO_95"), ++ PINCTRL_PIN(96, "GPIO_96"), ++ PINCTRL_PIN(97, "GPIO_97"), ++ PINCTRL_PIN(98, "GPIO_98"), ++ PINCTRL_PIN(99, "GPIO_99"), ++ PINCTRL_PIN(100, "GPIO_100"), ++ PINCTRL_PIN(101, "GPIO_101"), ++ PINCTRL_PIN(102, "GPIO_102"), ++ PINCTRL_PIN(103, "GPIO_103"), ++ PINCTRL_PIN(104, "GPIO_104"), ++ PINCTRL_PIN(105, "GPIO_105"), ++ PINCTRL_PIN(106, "GPIO_106"), ++ PINCTRL_PIN(107, "GPIO_107"), ++ PINCTRL_PIN(108, "GPIO_108"), ++ PINCTRL_PIN(109, "GPIO_109"), ++ PINCTRL_PIN(110, "GPIO_110"), ++ PINCTRL_PIN(111, "GPIO_111"), ++ PINCTRL_PIN(112, "GPIO_112"), ++ PINCTRL_PIN(113, "GPIO_113"), ++ PINCTRL_PIN(114, "GPIO_114"), ++ PINCTRL_PIN(115, "GPIO_115"), ++ PINCTRL_PIN(116, "GPIO_116"), ++ PINCTRL_PIN(117, "GPIO_117"), ++ PINCTRL_PIN(118, "GPIO_118"), ++ PINCTRL_PIN(119, "GPIO_119"), ++ PINCTRL_PIN(120, "GPIO_120"), ++ PINCTRL_PIN(121, "GPIO_121"), ++ PINCTRL_PIN(122, "GPIO_122"), ++ PINCTRL_PIN(123, "GPIO_123"), ++ PINCTRL_PIN(124, "GPIO_124"), ++ PINCTRL_PIN(125, "GPIO_125"), ++ PINCTRL_PIN(126, "GPIO_126"), ++ PINCTRL_PIN(127, "GPIO_127"), ++ PINCTRL_PIN(128, "PWR_SCL"), ++ PINCTRL_PIN(129, "PWR_SDA"), ++ PINCTRL_PIN(130, "VCXO_EN"), ++ PINCTRL_PIN(131, "PMIC_INT_N"), ++ PINCTRL_PIN(132, "MMC1_DAT3"), ++ PINCTRL_PIN(133, "MMC1_DAT2"), ++ PINCTRL_PIN(134, "MMC1_DAT1"), ++ PINCTRL_PIN(135, "MMC1_DAT0"), ++ PINCTRL_PIN(136, "MMC1_CMD"), ++ PINCTRL_PIN(137, "MMC1_CLK"), ++ PINCTRL_PIN(138, "QSPI_DAT0"), ++ PINCTRL_PIN(139, "QSPI_DAT1"), ++ PINCTRL_PIN(140, "QSPI_DAT2"), ++ PINCTRL_PIN(141, "QSPI_DAT3"), ++ PINCTRL_PIN(142, "QSPI_CS0"), ++ PINCTRL_PIN(143, "QSPI_CS1"), ++ PINCTRL_PIN(144, "QSPI_CLK"), ++ PINCTRL_PIN(145, "PRI_TDI"), ++ PINCTRL_PIN(146, "PRI_TMS"), ++ PINCTRL_PIN(147, "PRI_TCK"), ++ PINCTRL_PIN(148, "PRI_TDO"), ++ PINCTRL_PIN(149, "PWR_SSP_SCLK"), ++ PINCTRL_PIN(150, "PWR_SSP_FRM"), ++ PINCTRL_PIN(151, "PWR_SSP_TXD"), ++ PINCTRL_PIN(152, "PWR_SSP_RXD"), ++}; ++ ++static const struct spacemit_pin k3_pin_data[ARRAY_SIZE(k3_pin_desc)] = { ++ /* GPIO1 bank */ ++ K1_FUNC_PIN(0, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(1, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(2, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(3, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(4, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(5, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(6, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(7, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(8, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(9, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(10, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(11, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(12, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(13, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(14, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(15, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(16, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(17, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(18, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(19, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(20, 0, IO_TYPE_EXTERNAL), ++ ++ /* GPIO2 bank */ ++ K1_FUNC_PIN(21, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(22, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(23, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(24, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(25, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(26, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(27, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(28, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(29, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(30, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(31, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(32, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(33, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(34, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(35, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(36, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(37, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(38, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(39, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(40, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(41, 0, IO_TYPE_EXTERNAL), ++ ++ /* GPIO3 bank */ ++ K1_FUNC_PIN(42, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(43, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(44, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(45, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(46, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(47, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(48, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(49, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(50, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(51, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(52, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(53, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(54, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(55, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(56, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(57, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(58, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(59, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(60, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(61, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(62, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(63, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(64, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(65, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(66, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(67, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(68, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(69, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(70, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(71, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(72, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(73, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(74, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(75, 0, IO_TYPE_1V8), ++ ++ /* GPIO4 bank */ ++ K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(81, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(82, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(83, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(84, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(85, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(86, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(87, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(88, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(89, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(90, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(91, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(92, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(93, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(94, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(95, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(96, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(97, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(98, 0, IO_TYPE_EXTERNAL), ++ ++ /* GPIO5 bank */ ++ K1_FUNC_PIN(99, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(100, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(101, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(102, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(103, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(104, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(105, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(106, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(107, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(108, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(109, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(110, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(111, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(112, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(113, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(114, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(115, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(116, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(117, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(118, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(119, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(120, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(121, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(122, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(123, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(124, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(125, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(126, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(127, 0, IO_TYPE_EXTERNAL), ++ ++ /* PMIC */ ++ K1_FUNC_PIN(128, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(129, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(130, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(131, 0, IO_TYPE_1V8), ++ ++ /* SD/MMC1 */ ++ K1_FUNC_PIN(132, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(133, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(134, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(135, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(136, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(137, 1, IO_TYPE_EXTERNAL), ++ ++ /* QSPI */ ++ K1_FUNC_PIN(138, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(139, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(140, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(141, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(142, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(143, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(144, 1, IO_TYPE_EXTERNAL), ++ ++ /* PMIC */ ++ K1_FUNC_PIN(145, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(146, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(147, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(148, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(149, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(150, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(151, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(152, 1, IO_TYPE_1V8), ++}; ++ ++static const struct spacemit_pinctrl_data k3_pinctrl_data = { ++ .pins = k3_pin_desc, ++ .data = k3_pin_data, ++ .npins = ARRAY_SIZE(k3_pin_desc), ++ .pin_to_offset = spacemit_k3_pin_to_offset, + }; + + static const struct of_device_id k1_pinctrl_ids[] = { + { .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data }, ++ { .compatible = "spacemit,k3-pinctrl", .data = &k3_pinctrl_data }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, k1_pinctrl_ids); +@@ -1061,5 +1407,5 @@ static struct platform_driver k1_pinctrl_driver = { + builtin_platform_driver(k1_pinctrl_driver); + + MODULE_AUTHOR("Yixun Lan "); +-MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1 SoC"); ++MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1/K3 SoC"); + MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0092-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch b/SPECS/linux-lts-kmhv2/0092-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch deleted file mode 100644 index 072d73ce93..0000000000 --- a/SPECS/linux-lts-kmhv2/0092-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 3f32c9b526efb54621fa05106172ff0a751d71c5 Mon Sep 17 00:00:00 2001 -From: Ze Huang -Date: Sun, 11 Jan 2026 14:41:04 +0800 -Subject: [PATCH 092/467] UPSTREAM: riscv: dts: spacemit: Enable USB3.0 on - BananaPi-F3 - -Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the -Banana Pi F3 board. - -The board utilizes a VLI VL817 hub, which requires two separate power -supplies: one VBUS and one for hub itself. Add two GPIO-controlled -fixed-regulators to manage this. - -Tested-by: Aurelien Jarno -Signed-off-by: Ze Huang -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-3-f5ebd546e904@linux.dev -Signed-off-by: Yixun Lan -(cherry picked from commit c7e62c4eea026d42d192a0b86ce7313086ef2093) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 46 +++++++++++++++++++ - 1 file changed, 46 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 3f10efd925dc..5971605754b3 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -59,6 +59,25 @@ reg_vcc_4v: vcc-4v { - regulator-always-on; - vin-supply = <®_dc_in>; - }; -+ -+ usb3-vbus-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "USB30_VBUS"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ usb3_hub_5v: usb3-hub-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "USB30_HUB"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; - }; - - &combo_phy { -@@ -313,3 +332,30 @@ &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ hub_2_0: hub@1 { -+ compatible = "usb2109,2817"; -+ reg = <0x1>; -+ vdd-supply = <&usb3_hub_5v>; -+ peer-hub = <&hub_3_0>; -+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; -+ }; -+ -+ hub_3_0: hub@2 { -+ compatible = "usb2109,817"; -+ reg = <0x2>; -+ vdd-supply = <&usb3_hub_5v>; -+ peer-hub = <&hub_2_0>; -+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0093-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch b/SPECS/linux-lts-kmhv2/0093-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch deleted file mode 100644 index 90c3f81528..0000000000 --- a/SPECS/linux-lts-kmhv2/0093-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch +++ /dev/null @@ -1,44 +0,0 @@ -From a74398cd1206eaac108f02079a5c123a819062fc Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 2 Jan 2026 15:00:22 +0800 -Subject: [PATCH 093/467] UPSTREAM: dt-bindings: pinctrl: spacemit: convert - drive strength to schema format - -In order to better extend the pinctrl support for future new SoC, convert -drive strength setting from free form text to more standard schema format. - -Signed-off-by: Yixun Lan -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Linus Walleij -(cherry picked from commit c3efac0592f88ab48c8eef028268e6514908be51) -Signed-off-by: Han Gao ---- - .../bindings/pinctrl/spacemit,k1-pinctrl.yaml | 12 ++++++++---- - 1 file changed, 8 insertions(+), 4 deletions(-) - -diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -index d80e88aa07b4..609d7db97822 100644 ---- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -+++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -@@ -72,10 +72,14 @@ patternProperties: - enum: [ 0, 1 ] - - drive-strength: -- description: | -- typical current when output high level. -- 1.8V output: 11, 21, 32, 42 (mA) -- 3.3V output: 7, 10, 13, 16, 19, 23, 26, 29 (mA) -+ description: -+ typical current (in mA) when the output at high level. -+ oneOf: -+ - enum: [ 11, 21, 32, 42 ] -+ description: For K1 SoC, 1.8V voltage output -+ -+ - enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ] -+ description: For K1 SoC, 3.3V voltage output - - input-schmitt: - description: | --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch b/SPECS/linux-lts-kmhv2/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch new file mode 100644 index 0000000000..1885c27345 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch @@ -0,0 +1,325 @@ +From 57250a2d8e90085ff17ab7670d16519f41b64f28 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 2 Jan 2026 15:00:25 +0800 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: k3: adjust drive strength + and schmitter trigger + +K3 SoC expand drive strength to 4 bits which support even larger +settings table comparing to old SoC generation. Also schmitter trigger +setting is changed to 1 bit. + +Signed-off-by: Yixun Lan +Signed-off-by: Linus Walleij +(cherry picked from commit 3f20bdf7151834547a85231c28538f49601481ee) +Signed-off-by: Han Gao +--- + drivers/pinctrl/spacemit/pinctrl-k1.c | 163 ++++++++++++++++++-------- + 1 file changed, 116 insertions(+), 47 deletions(-) + +diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c +index 441817f539e3..07267c5f0f44 100644 +--- a/drivers/pinctrl/spacemit/pinctrl-k1.c ++++ b/drivers/pinctrl/spacemit/pinctrl-k1.c +@@ -24,11 +24,12 @@ + #include "pinctrl-k1.h" + + /* +- * +---------+----------+-----------+--------+--------+----------+--------+ +- * | pull | drive | schmitter | slew | edge | strong | mux | +- * | up/down | strength | trigger | rate | detect | pull | mode | +- * +---------+----------+-----------+--------+--------+----------+--------+ +- * 3 bits 3 bits 2 bits 1 bit 3 bits 1 bit 3 bits ++ * | pull | drive | schmitter | slew | edge | strong | mux | ++ * SoC | up/down | strength | trigger | rate | detect | pull | mode | ++ *-----+---------+----------+-----------+-------+--------+--------+--------+ ++ * K1 | 3 bits | 3 bits | 2 bits | 1 bit | 3 bits | 1 bit | 3 bits | ++ *-----+---------+----------+-----------+-------+--------+--------+--------+ ++ * K3 | 3 bits | 4 bits | 1 bits | 1 bit | 3 bits | 1 bit | 3 bits | + */ + + #define PAD_MUX GENMASK(2, 0) +@@ -38,12 +39,29 @@ + #define PAD_EDGE_CLEAR BIT(6) + #define PAD_SLEW_RATE GENMASK(12, 11) + #define PAD_SLEW_RATE_EN BIT(7) +-#define PAD_SCHMITT GENMASK(9, 8) +-#define PAD_DRIVE GENMASK(12, 10) ++#define PAD_SCHMITT_K1 GENMASK(9, 8) ++#define PAD_DRIVE_K1 GENMASK(12, 10) ++#define PAD_SCHMITT_K3 BIT(8) ++#define PAD_DRIVE_K3 GENMASK(12, 9) + #define PAD_PULLDOWN BIT(13) + #define PAD_PULLUP BIT(14) + #define PAD_PULL_EN BIT(15) + ++struct spacemit_pin_drv_strength { ++ u8 val; ++ u32 mA; ++}; ++ ++struct spacemit_pinctrl_dconf { ++ u64 schmitt_mask; ++ u64 drive_mask; ++ ++ struct spacemit_pin_drv_strength *ds_1v8_tbl; ++ size_t ds_1v8_tbl_num; ++ struct spacemit_pin_drv_strength *ds_3v3_tbl; ++ size_t ds_3v3_tbl_num; ++}; ++ + struct spacemit_pin { + u16 pin; + u16 flags; +@@ -67,6 +85,7 @@ struct spacemit_pinctrl_data { + const struct spacemit_pin *data; + u16 npins; + unsigned int (*pin_to_offset)(unsigned int pin); ++ const struct spacemit_pinctrl_dconf *dconf; + }; + + struct spacemit_pin_mux_config { +@@ -74,11 +93,6 @@ struct spacemit_pin_mux_config { + u32 config; + }; + +-struct spacemit_pin_drv_strength { +- u8 val; +- u32 mA; +-}; +- + /* map pin id to pinctrl register offset, refer MFPR definition */ + static unsigned int spacemit_k1_pin_to_offset(unsigned int pin) + { +@@ -193,23 +207,70 @@ static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev, + seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value); + } + +-/* use IO high level output current as the table */ +-static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = { +- { 0, 11 }, +- { 2, 21 }, +- { 4, 32 }, +- { 6, 42 }, ++static const struct spacemit_pinctrl_dconf k1_drive_conf = { ++ .drive_mask = PAD_DRIVE_K1, ++ .schmitt_mask = PAD_SCHMITT_K1, ++ .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) { ++ { 0, 11 }, ++ { 2, 21 }, ++ { 4, 32 }, ++ { 6, 42 }, ++ }, ++ .ds_1v8_tbl_num = 4, ++ .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) { ++ { 0, 7 }, ++ { 2, 10 }, ++ { 4, 13 }, ++ { 6, 16 }, ++ { 1, 19 }, ++ { 3, 23 }, ++ { 5, 26 }, ++ { 7, 29 }, ++ }, ++ .ds_3v3_tbl_num = 8, + }; + +-static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = { +- { 0, 7 }, +- { 2, 10 }, +- { 4, 13 }, +- { 6, 16 }, +- { 1, 19 }, +- { 3, 23 }, +- { 5, 26 }, +- { 7, 29 }, ++static const struct spacemit_pinctrl_dconf k3_drive_conf = { ++ .drive_mask = PAD_DRIVE_K3, ++ .schmitt_mask = PAD_SCHMITT_K3, ++ .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) { ++ { 0, 2 }, ++ { 1, 4 }, ++ { 2, 6 }, ++ { 3, 7 }, ++ { 4, 9 }, ++ { 5, 11 }, ++ { 6, 13 }, ++ { 7, 14 }, ++ { 8, 21 }, ++ { 9, 23 }, ++ { 10, 25 }, ++ { 11, 26 }, ++ { 12, 28 }, ++ { 13, 30 }, ++ { 14, 31 }, ++ { 15, 33 }, ++ }, ++ .ds_1v8_tbl_num = 16, ++ .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) { ++ { 0, 3 }, ++ { 1, 5 }, ++ { 2, 7 }, ++ { 3, 9 }, ++ { 4, 11 }, ++ { 5, 13 }, ++ { 6, 15 }, ++ { 7, 17 }, ++ { 8, 25 }, ++ { 9, 27 }, ++ { 10, 29 }, ++ { 11, 31 }, ++ { 12, 33 }, ++ { 13, 35 }, ++ { 14, 37 }, ++ { 15, 38 }, ++ }, ++ .ds_3v3_tbl_num = 16, + }; + + static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl, +@@ -237,16 +298,17 @@ static inline u32 spacemit_get_ds_mA(struct spacemit_pin_drv_strength *tbl, + } + + static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type, ++ const struct spacemit_pinctrl_dconf *dconf, + u32 mA) + { + switch (type) { + case IO_TYPE_1V8: +- return spacemit_get_ds_value(spacemit_ds_1v8_tbl, +- ARRAY_SIZE(spacemit_ds_1v8_tbl), ++ return spacemit_get_ds_value(dconf->ds_1v8_tbl, ++ dconf->ds_1v8_tbl_num, + mA); + case IO_TYPE_3V3: +- return spacemit_get_ds_value(spacemit_ds_3v3_tbl, +- ARRAY_SIZE(spacemit_ds_3v3_tbl), ++ return spacemit_get_ds_value(dconf->ds_3v3_tbl, ++ dconf->ds_3v3_tbl_num, + mA); + default: + return 0; +@@ -254,16 +316,17 @@ static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type, + } + + static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type, ++ const struct spacemit_pinctrl_dconf *dconf, + u32 value) + { + switch (type) { + case IO_TYPE_1V8: +- return spacemit_get_ds_mA(spacemit_ds_1v8_tbl, +- ARRAY_SIZE(spacemit_ds_1v8_tbl), +- value & 0x6); ++ return spacemit_get_ds_mA(dconf->ds_1v8_tbl, ++ dconf->ds_1v8_tbl_num, ++ value); + case IO_TYPE_3V3: +- return spacemit_get_ds_mA(spacemit_ds_3v3_tbl, +- ARRAY_SIZE(spacemit_ds_3v3_tbl), ++ return spacemit_get_ds_mA(dconf->ds_3v3_tbl, ++ dconf->ds_3v3_tbl_num, + value); + default: + return 0; +@@ -510,6 +573,7 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, + #define ENABLE_DRV_STRENGTH BIT(1) + #define ENABLE_SLEW_RATE BIT(2) + static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, ++ const struct spacemit_pinctrl_dconf *dconf, + unsigned long *configs, + unsigned int num_configs, + u32 *value) +@@ -547,8 +611,8 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, + drv_strength = arg; + break; + case PIN_CONFIG_INPUT_SCHMITT: +- v &= ~PAD_SCHMITT; +- v |= FIELD_PREP(PAD_SCHMITT, arg); ++ v &= ~dconf->schmitt_mask; ++ v |= (arg << __ffs(dconf->schmitt_mask)) & dconf->schmitt_mask; + break; + case PIN_CONFIG_POWER_SOURCE: + voltage = arg; +@@ -584,10 +648,10 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, + } + } + +- val = spacemit_get_driver_strength(type, drv_strength); ++ val = spacemit_get_driver_strength(type, dconf, drv_strength); + +- v &= ~PAD_DRIVE; +- v |= FIELD_PREP(PAD_DRIVE, val); ++ v &= ~dconf->drive_mask; ++ v |= (val << __ffs(dconf->drive_mask)) & dconf->drive_mask; + } + + if (flag & ENABLE_SLEW_RATE) { +@@ -637,7 +701,8 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + u32 value; + +- if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) ++ if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, ++ configs, num_configs, &value)) + return -EINVAL; + + return spacemit_pin_set_config(pctrl, pin, value); +@@ -659,7 +724,8 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, + return -EINVAL; + + spin = spacemit_get_pin(pctrl, group->grp.pins[0]); +- if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) ++ if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, ++ configs, num_configs, &value)) + return -EINVAL; + + for (i = 0; i < group->grp.npins; i++) +@@ -693,6 +759,7 @@ static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *seq, unsigned int pin) + { + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); ++ const struct spacemit_pinctrl_dconf *dconf = pctrl->data->dconf; + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin); + void __iomem *reg = spacemit_pin_to_reg(pctrl, pin); +@@ -703,17 +770,17 @@ static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev, + + seq_printf(seq, ", io type (%s)", io_type_desc[type]); + +- tmp = FIELD_GET(PAD_DRIVE, value); ++ tmp = (value & dconf->drive_mask) >> __ffs(dconf->drive_mask); + if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) { +- mA = spacemit_get_drive_strength_mA(type, tmp); ++ mA = spacemit_get_drive_strength_mA(type, dconf, tmp); + seq_printf(seq, ", drive strength (%d mA)", mA); + } + + /* drive strength depend on power source, so show all values */ + if (type == IO_TYPE_EXTERNAL) + seq_printf(seq, ", drive strength (%d or %d mA)", +- spacemit_get_drive_strength_mA(IO_TYPE_1V8, tmp), +- spacemit_get_drive_strength_mA(IO_TYPE_3V3, tmp)); ++ spacemit_get_drive_strength_mA(IO_TYPE_1V8, dconf, tmp), ++ spacemit_get_drive_strength_mA(IO_TYPE_3V3, dconf, tmp)); + + seq_printf(seq, ", register (0x%04x)", value); + } +@@ -1051,6 +1118,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { + .data = k1_pin_data, + .npins = ARRAY_SIZE(k1_pin_desc), + .pin_to_offset = spacemit_k1_pin_to_offset, ++ .dconf = &k1_drive_conf, + }; + + static const struct pinctrl_pin_desc k3_pin_desc[] = { +@@ -1387,6 +1455,7 @@ static const struct spacemit_pinctrl_data k3_pinctrl_data = { + .data = k3_pin_data, + .npins = ARRAY_SIZE(k3_pin_desc), + .pin_to_offset = spacemit_k3_pin_to_offset, ++ .dconf = &k3_drive_conf, + }; + + static const struct of_device_id k1_pinctrl_ids[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch b/SPECS/linux-lts-kmhv2/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch deleted file mode 100644 index 7ec035b202..0000000000 --- a/SPECS/linux-lts-kmhv2/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 37ffcc8cf5dbf1d1553b54b67b39e8f7728b2714 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 2 Jan 2026 15:00:23 +0800 -Subject: [PATCH 094/467] UPSTREAM: dt-bindings: pinctrl: spacemit: add K3 SoC - support - -Add new compatible string for SpacemiT K3 SoC, the pinctrl IP shares -almost same logic with previous K1 generation, but has different register -offset and pin configuration, for example the drive strength and -schmitter trigger settings has been changed. - -Signed-off-by: Yixun Lan -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Linus Walleij -(cherry picked from commit 5adaa1a8c08839617e5a6385fe05a8baa63e355f) -Signed-off-by: Han Gao ---- - .../bindings/pinctrl/spacemit,k1-pinctrl.yaml | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -index 609d7db97822..9a76cffcbaee 100644 ---- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -+++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -@@ -11,7 +11,9 @@ maintainers: - - properties: - compatible: -- const: spacemit,k1-pinctrl -+ enum: -+ - spacemit,k1-pinctrl -+ - spacemit,k3-pinctrl - - reg: - items: -@@ -81,6 +83,12 @@ patternProperties: - - enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ] - description: For K1 SoC, 3.3V voltage output - -+ - enum: [ 2, 4, 6, 7, 9, 11, 13, 14, 21, 23, 25, 26, 28, 30, 31, 33 ] -+ description: For K3 SoC, 1.8V voltage output -+ -+ - enum: [ 3, 5, 7, 9, 11, 13, 15, 17, 25, 27, 29, 31, 33, 35, 37, 38 ] -+ description: For K3 SoC, 1.8V voltage output -+ - input-schmitt: - description: | - typical threshold for schmitt trigger. --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch b/SPECS/linux-lts-kmhv2/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch new file mode 100644 index 0000000000..b203991c2d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch @@ -0,0 +1,49 @@ +From f3a4b85d5279965fc53d7163a005b2e64ff1327a Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 14:42:38 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pinctrl: spacemit: add syscon + property + +In order to access the protected IO power domain registers, a valid +unlock sequence must be performed by writing the required keys to the +AIB Secure Access Register (ASAR). + +The ASAR register resides within the APBC register address space. +A corresponding syscon property is added to allow the pinctrl driver +to access this register. + +Signed-off-by: Troy Mitchell +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Linus Walleij +(cherry picked from commit e817f0223d78818cd6c0e3480355c9a9cfbc0096) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +index 9a76cffcbaee..141dcedb81fb 100644 +--- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml ++++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +@@ -32,6 +32,10 @@ properties: + resets: + maxItems: 1 + ++ spacemit,apbc: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: Phandle to syscon that access the protected register ++ + patternProperties: + '-cfg$': + type: object +@@ -138,6 +142,7 @@ examples: + clocks = <&syscon_apbc 42>, + <&syscon_apbc 94>; + clock-names = "func", "bus"; ++ spacemit,apbc = <&syscon_apbc>; + + uart0_2_cfg: uart0-2-cfg { + uart0-2-pins { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0095-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch b/SPECS/linux-lts-kmhv2/0095-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch deleted file mode 100644 index a3919c7994..0000000000 --- a/SPECS/linux-lts-kmhv2/0095-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch +++ /dev/null @@ -1,449 +0,0 @@ -From 33f3e51747fc087ba55c240d5d94baeb18d26db3 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 2 Jan 2026 15:00:24 +0800 -Subject: [PATCH 095/467] UPSTREAM: pinctrl: spacemit: k3: add initial pin - support - -For the pinctrl IP of SpacemiT's K3 SoC, it has different register offset -comparing with previous SoC generation, so introduce a function to do the -pin to offset mapping. Also add all the pinctrl data. - -Signed-off-by: Yixun Lan -Signed-off-by: Linus Walleij -(cherry picked from commit 7412311c4655497b6ab6dd7b802f9390f0f57dc7) -Signed-off-by: Han Gao ---- - drivers/pinctrl/spacemit/Kconfig | 4 +- - drivers/pinctrl/spacemit/pinctrl-k1.c | 354 +++++++++++++++++++++++++- - 2 files changed, 352 insertions(+), 6 deletions(-) - -diff --git a/drivers/pinctrl/spacemit/Kconfig b/drivers/pinctrl/spacemit/Kconfig -index d6f6017fd097..c021d51033d1 100644 ---- a/drivers/pinctrl/spacemit/Kconfig -+++ b/drivers/pinctrl/spacemit/Kconfig -@@ -4,7 +4,7 @@ - # - - config PINCTRL_SPACEMIT_K1 -- bool "SpacemiT K1 SoC Pinctrl driver" -+ bool "SpacemiT K1/K3 SoC Pinctrl driver" - depends on ARCH_SPACEMIT || COMPILE_TEST - depends on OF - default ARCH_SPACEMIT -@@ -12,7 +12,7 @@ config PINCTRL_SPACEMIT_K1 - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF - help -- Say Y to select the pinctrl driver for K1 SoC. -+ Say Y to select the pinctrl driver for K1/K3 SoC. - This pin controller allows selecting the mux function for - each pin. This driver can also be built as a module called - pinctrl-k1. -diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c -index 33af9b5791c1..441817f539e3 100644 ---- a/drivers/pinctrl/spacemit/pinctrl-k1.c -+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c -@@ -66,6 +66,7 @@ struct spacemit_pinctrl_data { - const struct pinctrl_pin_desc *pins; - const struct spacemit_pin *data; - u16 npins; -+ unsigned int (*pin_to_offset)(unsigned int pin); - }; - - struct spacemit_pin_mux_config { -@@ -79,7 +80,7 @@ struct spacemit_pin_drv_strength { - }; - - /* map pin id to pinctrl register offset, refer MFPR definition */ --static unsigned int spacemit_pin_to_offset(unsigned int pin) -+static unsigned int spacemit_k1_pin_to_offset(unsigned int pin) - { - unsigned int offset = 0; - -@@ -124,10 +125,17 @@ static unsigned int spacemit_pin_to_offset(unsigned int pin) - return offset << 2; - } - -+static unsigned int spacemit_k3_pin_to_offset(unsigned int pin) -+{ -+ unsigned int offset = pin > 130 ? (pin + 2) : pin; -+ -+ return offset << 2; -+} -+ - static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, - unsigned int pin) - { -- return pctrl->regs + spacemit_pin_to_offset(pin); -+ return pctrl->regs + pctrl->data->pin_to_offset(pin); - } - - static u16 spacemit_dt_get_pin(u32 value) -@@ -177,7 +185,7 @@ static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev, - void __iomem *reg; - u32 value; - -- seq_printf(seq, "offset: 0x%04x ", spacemit_pin_to_offset(pin)); -+ seq_printf(seq, "offset: 0x%04x ", pctrl->data->pin_to_offset(pin)); - seq_printf(seq, "type: %s ", io_type_desc[type]); - - reg = spacemit_pin_to_reg(pctrl, pin); -@@ -1042,10 +1050,348 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { - .pins = k1_pin_desc, - .data = k1_pin_data, - .npins = ARRAY_SIZE(k1_pin_desc), -+ .pin_to_offset = spacemit_k1_pin_to_offset, -+}; -+ -+static const struct pinctrl_pin_desc k3_pin_desc[] = { -+ PINCTRL_PIN(0, "GPIO_00"), -+ PINCTRL_PIN(1, "GPIO_01"), -+ PINCTRL_PIN(2, "GPIO_02"), -+ PINCTRL_PIN(3, "GPIO_03"), -+ PINCTRL_PIN(4, "GPIO_04"), -+ PINCTRL_PIN(5, "GPIO_05"), -+ PINCTRL_PIN(6, "GPIO_06"), -+ PINCTRL_PIN(7, "GPIO_07"), -+ PINCTRL_PIN(8, "GPIO_08"), -+ PINCTRL_PIN(9, "GPIO_09"), -+ PINCTRL_PIN(10, "GPIO_10"), -+ PINCTRL_PIN(11, "GPIO_11"), -+ PINCTRL_PIN(12, "GPIO_12"), -+ PINCTRL_PIN(13, "GPIO_13"), -+ PINCTRL_PIN(14, "GPIO_14"), -+ PINCTRL_PIN(15, "GPIO_15"), -+ PINCTRL_PIN(16, "GPIO_16"), -+ PINCTRL_PIN(17, "GPIO_17"), -+ PINCTRL_PIN(18, "GPIO_18"), -+ PINCTRL_PIN(19, "GPIO_19"), -+ PINCTRL_PIN(20, "GPIO_20"), -+ PINCTRL_PIN(21, "GPIO_21"), -+ PINCTRL_PIN(22, "GPIO_22"), -+ PINCTRL_PIN(23, "GPIO_23"), -+ PINCTRL_PIN(24, "GPIO_24"), -+ PINCTRL_PIN(25, "GPIO_25"), -+ PINCTRL_PIN(26, "GPIO_26"), -+ PINCTRL_PIN(27, "GPIO_27"), -+ PINCTRL_PIN(28, "GPIO_28"), -+ PINCTRL_PIN(29, "GPIO_29"), -+ PINCTRL_PIN(30, "GPIO_30"), -+ PINCTRL_PIN(31, "GPIO_31"), -+ PINCTRL_PIN(32, "GPIO_32"), -+ PINCTRL_PIN(33, "GPIO_33"), -+ PINCTRL_PIN(34, "GPIO_34"), -+ PINCTRL_PIN(35, "GPIO_35"), -+ PINCTRL_PIN(36, "GPIO_36"), -+ PINCTRL_PIN(37, "GPIO_37"), -+ PINCTRL_PIN(38, "GPIO_38"), -+ PINCTRL_PIN(39, "GPIO_39"), -+ PINCTRL_PIN(40, "GPIO_40"), -+ PINCTRL_PIN(41, "GPIO_41"), -+ PINCTRL_PIN(42, "GPIO_42"), -+ PINCTRL_PIN(43, "GPIO_43"), -+ PINCTRL_PIN(44, "GPIO_44"), -+ PINCTRL_PIN(45, "GPIO_45"), -+ PINCTRL_PIN(46, "GPIO_46"), -+ PINCTRL_PIN(47, "GPIO_47"), -+ PINCTRL_PIN(48, "GPIO_48"), -+ PINCTRL_PIN(49, "GPIO_49"), -+ PINCTRL_PIN(50, "GPIO_50"), -+ PINCTRL_PIN(51, "GPIO_51"), -+ PINCTRL_PIN(52, "GPIO_52"), -+ PINCTRL_PIN(53, "GPIO_53"), -+ PINCTRL_PIN(54, "GPIO_54"), -+ PINCTRL_PIN(55, "GPIO_55"), -+ PINCTRL_PIN(56, "GPIO_56"), -+ PINCTRL_PIN(57, "GPIO_57"), -+ PINCTRL_PIN(58, "GPIO_58"), -+ PINCTRL_PIN(59, "GPIO_59"), -+ PINCTRL_PIN(60, "GPIO_60"), -+ PINCTRL_PIN(61, "GPIO_61"), -+ PINCTRL_PIN(62, "GPIO_62"), -+ PINCTRL_PIN(63, "GPIO_63"), -+ PINCTRL_PIN(64, "GPIO_64"), -+ PINCTRL_PIN(65, "GPIO_65"), -+ PINCTRL_PIN(66, "GPIO_66"), -+ PINCTRL_PIN(67, "GPIO_67"), -+ PINCTRL_PIN(68, "GPIO_68"), -+ PINCTRL_PIN(69, "GPIO_69"), -+ PINCTRL_PIN(70, "GPIO_70"), -+ PINCTRL_PIN(71, "GPIO_71"), -+ PINCTRL_PIN(72, "GPIO_72"), -+ PINCTRL_PIN(73, "GPIO_73"), -+ PINCTRL_PIN(74, "GPIO_74"), -+ PINCTRL_PIN(75, "GPIO_75"), -+ PINCTRL_PIN(76, "GPIO_76"), -+ PINCTRL_PIN(77, "GPIO_77"), -+ PINCTRL_PIN(78, "GPIO_78"), -+ PINCTRL_PIN(79, "GPIO_79"), -+ PINCTRL_PIN(80, "GPIO_80"), -+ PINCTRL_PIN(81, "GPIO_81"), -+ PINCTRL_PIN(82, "GPIO_82"), -+ PINCTRL_PIN(83, "GPIO_83"), -+ PINCTRL_PIN(84, "GPIO_84"), -+ PINCTRL_PIN(85, "GPIO_85"), -+ PINCTRL_PIN(86, "GPIO_86"), -+ PINCTRL_PIN(87, "GPIO_87"), -+ PINCTRL_PIN(88, "GPIO_88"), -+ PINCTRL_PIN(89, "GPIO_89"), -+ PINCTRL_PIN(90, "GPIO_90"), -+ PINCTRL_PIN(91, "GPIO_91"), -+ PINCTRL_PIN(92, "GPIO_92"), -+ PINCTRL_PIN(93, "GPIO_93"), -+ PINCTRL_PIN(94, "GPIO_94"), -+ PINCTRL_PIN(95, "GPIO_95"), -+ PINCTRL_PIN(96, "GPIO_96"), -+ PINCTRL_PIN(97, "GPIO_97"), -+ PINCTRL_PIN(98, "GPIO_98"), -+ PINCTRL_PIN(99, "GPIO_99"), -+ PINCTRL_PIN(100, "GPIO_100"), -+ PINCTRL_PIN(101, "GPIO_101"), -+ PINCTRL_PIN(102, "GPIO_102"), -+ PINCTRL_PIN(103, "GPIO_103"), -+ PINCTRL_PIN(104, "GPIO_104"), -+ PINCTRL_PIN(105, "GPIO_105"), -+ PINCTRL_PIN(106, "GPIO_106"), -+ PINCTRL_PIN(107, "GPIO_107"), -+ PINCTRL_PIN(108, "GPIO_108"), -+ PINCTRL_PIN(109, "GPIO_109"), -+ PINCTRL_PIN(110, "GPIO_110"), -+ PINCTRL_PIN(111, "GPIO_111"), -+ PINCTRL_PIN(112, "GPIO_112"), -+ PINCTRL_PIN(113, "GPIO_113"), -+ PINCTRL_PIN(114, "GPIO_114"), -+ PINCTRL_PIN(115, "GPIO_115"), -+ PINCTRL_PIN(116, "GPIO_116"), -+ PINCTRL_PIN(117, "GPIO_117"), -+ PINCTRL_PIN(118, "GPIO_118"), -+ PINCTRL_PIN(119, "GPIO_119"), -+ PINCTRL_PIN(120, "GPIO_120"), -+ PINCTRL_PIN(121, "GPIO_121"), -+ PINCTRL_PIN(122, "GPIO_122"), -+ PINCTRL_PIN(123, "GPIO_123"), -+ PINCTRL_PIN(124, "GPIO_124"), -+ PINCTRL_PIN(125, "GPIO_125"), -+ PINCTRL_PIN(126, "GPIO_126"), -+ PINCTRL_PIN(127, "GPIO_127"), -+ PINCTRL_PIN(128, "PWR_SCL"), -+ PINCTRL_PIN(129, "PWR_SDA"), -+ PINCTRL_PIN(130, "VCXO_EN"), -+ PINCTRL_PIN(131, "PMIC_INT_N"), -+ PINCTRL_PIN(132, "MMC1_DAT3"), -+ PINCTRL_PIN(133, "MMC1_DAT2"), -+ PINCTRL_PIN(134, "MMC1_DAT1"), -+ PINCTRL_PIN(135, "MMC1_DAT0"), -+ PINCTRL_PIN(136, "MMC1_CMD"), -+ PINCTRL_PIN(137, "MMC1_CLK"), -+ PINCTRL_PIN(138, "QSPI_DAT0"), -+ PINCTRL_PIN(139, "QSPI_DAT1"), -+ PINCTRL_PIN(140, "QSPI_DAT2"), -+ PINCTRL_PIN(141, "QSPI_DAT3"), -+ PINCTRL_PIN(142, "QSPI_CS0"), -+ PINCTRL_PIN(143, "QSPI_CS1"), -+ PINCTRL_PIN(144, "QSPI_CLK"), -+ PINCTRL_PIN(145, "PRI_TDI"), -+ PINCTRL_PIN(146, "PRI_TMS"), -+ PINCTRL_PIN(147, "PRI_TCK"), -+ PINCTRL_PIN(148, "PRI_TDO"), -+ PINCTRL_PIN(149, "PWR_SSP_SCLK"), -+ PINCTRL_PIN(150, "PWR_SSP_FRM"), -+ PINCTRL_PIN(151, "PWR_SSP_TXD"), -+ PINCTRL_PIN(152, "PWR_SSP_RXD"), -+}; -+ -+static const struct spacemit_pin k3_pin_data[ARRAY_SIZE(k3_pin_desc)] = { -+ /* GPIO1 bank */ -+ K1_FUNC_PIN(0, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(1, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(2, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(3, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(4, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(5, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(6, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(7, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(8, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(9, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(10, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(11, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(12, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(13, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(14, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(15, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(16, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(17, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(18, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(19, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(20, 0, IO_TYPE_EXTERNAL), -+ -+ /* GPIO2 bank */ -+ K1_FUNC_PIN(21, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(22, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(23, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(24, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(25, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(26, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(27, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(28, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(29, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(30, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(31, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(32, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(33, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(34, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(35, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(36, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(37, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(38, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(39, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(40, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(41, 0, IO_TYPE_EXTERNAL), -+ -+ /* GPIO3 bank */ -+ K1_FUNC_PIN(42, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(43, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(44, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(45, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(46, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(47, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(48, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(49, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(50, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(51, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(52, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(53, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(54, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(55, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(56, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(57, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(58, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(59, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(60, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(61, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(62, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(63, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(64, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(65, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(66, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(67, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(68, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(69, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(70, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(71, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(72, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(73, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(74, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(75, 0, IO_TYPE_1V8), -+ -+ /* GPIO4 bank */ -+ K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(81, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(82, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(83, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(84, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(85, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(86, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(87, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(88, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(89, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(90, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(91, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(92, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(93, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(94, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(95, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(96, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(97, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(98, 0, IO_TYPE_EXTERNAL), -+ -+ /* GPIO5 bank */ -+ K1_FUNC_PIN(99, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(100, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(101, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(102, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(103, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(104, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(105, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(106, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(107, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(108, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(109, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(110, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(111, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(112, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(113, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(114, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(115, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(116, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(117, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(118, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(119, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(120, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(121, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(122, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(123, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(124, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(125, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(126, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(127, 0, IO_TYPE_EXTERNAL), -+ -+ /* PMIC */ -+ K1_FUNC_PIN(128, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(129, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(130, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(131, 0, IO_TYPE_1V8), -+ -+ /* SD/MMC1 */ -+ K1_FUNC_PIN(132, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(133, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(134, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(135, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(136, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(137, 1, IO_TYPE_EXTERNAL), -+ -+ /* QSPI */ -+ K1_FUNC_PIN(138, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(139, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(140, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(141, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(142, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(143, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(144, 1, IO_TYPE_EXTERNAL), -+ -+ /* PMIC */ -+ K1_FUNC_PIN(145, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(146, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(147, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(148, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(149, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(150, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(151, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(152, 1, IO_TYPE_1V8), -+}; -+ -+static const struct spacemit_pinctrl_data k3_pinctrl_data = { -+ .pins = k3_pin_desc, -+ .data = k3_pin_data, -+ .npins = ARRAY_SIZE(k3_pin_desc), -+ .pin_to_offset = spacemit_k3_pin_to_offset, - }; - - static const struct of_device_id k1_pinctrl_ids[] = { - { .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data }, -+ { .compatible = "spacemit,k3-pinctrl", .data = &k3_pinctrl_data }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, k1_pinctrl_ids); -@@ -1061,5 +1407,5 @@ static struct platform_driver k1_pinctrl_driver = { - builtin_platform_driver(k1_pinctrl_driver); - - MODULE_AUTHOR("Yixun Lan "); --MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1 SoC"); -+MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1/K3 SoC"); - MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch b/SPECS/linux-lts-kmhv2/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch new file mode 100644 index 0000000000..377503eb76 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch @@ -0,0 +1,263 @@ +From 0a07233b0f550ed136cd45130d55ac5e079fc795 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 14:42:39 +0800 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: support I/O power domain + configuration + +Dual-voltage GPIO banks default to 3.3V operation. Even when a bank is +externally supplied with 1.8V, the internal logic remains in the 3.3V +domain, leading to functional failures. + +Add support for programming the IO domain power control registers to +allow explicit configuration for 1.8V operation. + +These registers are secure due to hardware safety constraints. +Specifically, configuring the domain for 1.8V while externally supplying +3.3V causes back-powering and potential pin damage. Consequently, access +requires unlocking the AIB Secure Access Register (ASAR) in the APBC +block before any read or write operation. + +Signed-off-by: Troy Mitchell +Signed-off-by: Linus Walleij +(cherry picked from commit 450e2487d5a28260f70ad7fbf3060e7f8304203d) +Signed-off-by: Han Gao +--- + drivers/pinctrl/spacemit/pinctrl-k1.c | 129 +++++++++++++++++++++++++- + 1 file changed, 126 insertions(+), 3 deletions(-) + +diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c +index 07267c5f0f44..71390402aaa6 100644 +--- a/drivers/pinctrl/spacemit/pinctrl-k1.c ++++ b/drivers/pinctrl/spacemit/pinctrl-k1.c +@@ -7,8 +7,10 @@ + #include + #include + #include ++#include + #include + #include ++#include + #include + #include + +@@ -47,6 +49,27 @@ + #define PAD_PULLUP BIT(14) + #define PAD_PULL_EN BIT(15) + ++#define IO_PWR_DOMAIN_OFFSET 0x800 ++ ++#define IO_PWR_DOMAIN_GPIO2_Kx 0x0c ++#define IO_PWR_DOMAIN_MMC_Kx 0x1c ++ ++#define IO_PWR_DOMAIN_GPIO3_K1 0x10 ++#define IO_PWR_DOMAIN_QSPI_K1 0x20 ++ ++#define IO_PWR_DOMAIN_GPIO1_K3 0x04 ++#define IO_PWR_DOMAIN_GPIO5_K3 0x10 ++#define IO_PWR_DOMAIN_GPIO4_K3 0x20 ++#define IO_PWR_DOMAIN_QSPI_K3 0x2c ++ ++#define IO_PWR_DOMAIN_V18EN BIT(2) ++ ++#define APBC_ASFAR 0x50 ++#define APBC_ASSAR 0x54 ++ ++#define APBC_ASFAR_AKEY 0xbaba ++#define APBC_ASSAR_AKEY 0xeb10 ++ + struct spacemit_pin_drv_strength { + u8 val; + u32 mA; +@@ -78,6 +101,8 @@ struct spacemit_pinctrl { + raw_spinlock_t lock; + + void __iomem *regs; ++ ++ struct regmap *regmap_apbc; + }; + + struct spacemit_pinctrl_data { +@@ -85,6 +110,7 @@ struct spacemit_pinctrl_data { + const struct spacemit_pin *data; + u16 npins; + unsigned int (*pin_to_offset)(unsigned int pin); ++ unsigned int (*pin_to_io_pd_offset)(unsigned int pin); + const struct spacemit_pinctrl_dconf *dconf; + }; + +@@ -146,6 +172,56 @@ static unsigned int spacemit_k3_pin_to_offset(unsigned int pin) + return offset << 2; + } + ++static unsigned int spacemit_k1_pin_to_io_pd_offset(unsigned int pin) ++{ ++ unsigned int offset = 0; ++ ++ switch (pin) { ++ case 47 ... 52: ++ offset = IO_PWR_DOMAIN_GPIO3_K1; ++ break; ++ case 75 ... 80: ++ offset = IO_PWR_DOMAIN_GPIO2_Kx; ++ break; ++ case 98 ... 103: ++ offset = IO_PWR_DOMAIN_QSPI_K1; ++ break; ++ case 104 ... 109: ++ offset = IO_PWR_DOMAIN_MMC_Kx; ++ break; ++ } ++ ++ return offset; ++} ++ ++static unsigned int spacemit_k3_pin_to_io_pd_offset(unsigned int pin) ++{ ++ unsigned int offset = 0; ++ ++ switch (pin) { ++ case 0 ... 20: ++ offset = IO_PWR_DOMAIN_GPIO1_K3; ++ break; ++ case 21 ... 41: ++ offset = IO_PWR_DOMAIN_GPIO2_Kx; ++ break; ++ case 76 ... 98: ++ offset = IO_PWR_DOMAIN_GPIO4_K3; ++ break; ++ case 99 ... 127: ++ offset = IO_PWR_DOMAIN_GPIO5_K3; ++ break; ++ case 132 ... 137: ++ offset = IO_PWR_DOMAIN_MMC_Kx; ++ break; ++ case 138 ... 144: ++ offset = IO_PWR_DOMAIN_QSPI_K3; ++ break; ++ } ++ ++ return offset; ++} ++ + static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, + unsigned int pin) + { +@@ -365,6 +441,42 @@ static int spacemit_pctrl_check_power(struct pinctrl_dev *pctldev, + return 0; + } + ++static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl, ++ const struct spacemit_pin *spin, ++ const enum spacemit_pin_io_type type) ++{ ++ u32 offset, val = 0; ++ ++ if (!pctrl->regmap_apbc) ++ return; ++ ++ offset = pctrl->data->pin_to_io_pd_offset(spin->pin); ++ ++ /* Other bits are reserved so don't need to save them */ ++ if (type == IO_TYPE_1V8) ++ val = IO_PWR_DOMAIN_V18EN; ++ ++ /* ++ * IO power domain registers are protected and cannot be accessed ++ * directly. Before performing any read or write to the IO power ++ * domain registers, an explicit unlock sequence must be issued ++ * via the AIB Secure Access Register (ASAR). ++ * ++ * The unlock sequence allows exactly one subsequent access to the ++ * IO power domain registers. After that access completes, the ASAR ++ * keys are automatically cleared, and the registers become locked ++ * again. ++ * ++ * This mechanism ensures that IO power domain configuration is ++ * performed intentionally, as incorrect voltage settings may ++ * result in functional failures or hardware damage. ++ */ ++ regmap_write(pctrl->regmap_apbc, APBC_ASFAR, APBC_ASFAR_AKEY); ++ regmap_write(pctrl->regmap_apbc, APBC_ASSAR, APBC_ASSAR_AKEY); ++ ++ writel_relaxed(val, pctrl->regs + IO_PWR_DOMAIN_OFFSET + offset); ++} ++ + static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, +@@ -572,7 +684,8 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, + + #define ENABLE_DRV_STRENGTH BIT(1) + #define ENABLE_SLEW_RATE BIT(2) +-static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, ++static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, ++ const struct spacemit_pin *spin, + const struct spacemit_pinctrl_dconf *dconf, + unsigned long *configs, + unsigned int num_configs, +@@ -646,6 +759,7 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, + default: + return -EINVAL; + } ++ spacemit_set_io_pwr_domain(pctrl, spin, type); + } + + val = spacemit_get_driver_strength(type, dconf, drv_strength); +@@ -701,7 +815,7 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + u32 value; + +- if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, ++ if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, + configs, num_configs, &value)) + return -EINVAL; + +@@ -724,7 +838,7 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, + return -EINVAL; + + spin = spacemit_get_pin(pctrl, group->grp.pins[0]); +- if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, ++ if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, + configs, num_configs, &value)) + return -EINVAL; + +@@ -795,6 +909,7 @@ static const struct pinconf_ops spacemit_pinconf_ops = { + + static int spacemit_pinctrl_probe(struct platform_device *pdev) + { ++ struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct spacemit_pinctrl *pctrl; + struct clk *func_clk, *bus_clk; +@@ -816,6 +931,12 @@ static int spacemit_pinctrl_probe(struct platform_device *pdev) + if (IS_ERR(pctrl->regs)) + return PTR_ERR(pctrl->regs); + ++ pctrl->regmap_apbc = syscon_regmap_lookup_by_phandle(np, "spacemit,apbc"); ++ if (IS_ERR(pctrl->regmap_apbc)) { ++ dev_warn(dev, "no syscon found, disable power voltage switch functionality\n"); ++ pctrl->regmap_apbc = NULL; ++ } ++ + func_clk = devm_clk_get_enabled(dev, "func"); + if (IS_ERR(func_clk)) + return dev_err_probe(dev, PTR_ERR(func_clk), "failed to get func clock\n"); +@@ -1118,6 +1239,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { + .data = k1_pin_data, + .npins = ARRAY_SIZE(k1_pin_desc), + .pin_to_offset = spacemit_k1_pin_to_offset, ++ .pin_to_io_pd_offset = spacemit_k1_pin_to_io_pd_offset, + .dconf = &k1_drive_conf, + }; + +@@ -1455,6 +1577,7 @@ static const struct spacemit_pinctrl_data k3_pinctrl_data = { + .data = k3_pin_data, + .npins = ARRAY_SIZE(k3_pin_desc), + .pin_to_offset = spacemit_k3_pin_to_offset, ++ .pin_to_io_pd_offset = spacemit_k3_pin_to_io_pd_offset, + .dconf = &k3_drive_conf, + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0096-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch b/SPECS/linux-lts-kmhv2/0096-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch deleted file mode 100644 index 02226d7349..0000000000 --- a/SPECS/linux-lts-kmhv2/0096-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch +++ /dev/null @@ -1,325 +0,0 @@ -From 407a2b9253b9c3e753302f3a24021c64b468be47 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 2 Jan 2026 15:00:25 +0800 -Subject: [PATCH 096/467] UPSTREAM: pinctrl: spacemit: k3: adjust drive - strength and schmitter trigger - -K3 SoC expand drive strength to 4 bits which support even larger -settings table comparing to old SoC generation. Also schmitter trigger -setting is changed to 1 bit. - -Signed-off-by: Yixun Lan -Signed-off-by: Linus Walleij -(cherry picked from commit 3f20bdf7151834547a85231c28538f49601481ee) -Signed-off-by: Han Gao ---- - drivers/pinctrl/spacemit/pinctrl-k1.c | 163 ++++++++++++++++++-------- - 1 file changed, 116 insertions(+), 47 deletions(-) - -diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c -index 441817f539e3..07267c5f0f44 100644 ---- a/drivers/pinctrl/spacemit/pinctrl-k1.c -+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c -@@ -24,11 +24,12 @@ - #include "pinctrl-k1.h" - - /* -- * +---------+----------+-----------+--------+--------+----------+--------+ -- * | pull | drive | schmitter | slew | edge | strong | mux | -- * | up/down | strength | trigger | rate | detect | pull | mode | -- * +---------+----------+-----------+--------+--------+----------+--------+ -- * 3 bits 3 bits 2 bits 1 bit 3 bits 1 bit 3 bits -+ * | pull | drive | schmitter | slew | edge | strong | mux | -+ * SoC | up/down | strength | trigger | rate | detect | pull | mode | -+ *-----+---------+----------+-----------+-------+--------+--------+--------+ -+ * K1 | 3 bits | 3 bits | 2 bits | 1 bit | 3 bits | 1 bit | 3 bits | -+ *-----+---------+----------+-----------+-------+--------+--------+--------+ -+ * K3 | 3 bits | 4 bits | 1 bits | 1 bit | 3 bits | 1 bit | 3 bits | - */ - - #define PAD_MUX GENMASK(2, 0) -@@ -38,12 +39,29 @@ - #define PAD_EDGE_CLEAR BIT(6) - #define PAD_SLEW_RATE GENMASK(12, 11) - #define PAD_SLEW_RATE_EN BIT(7) --#define PAD_SCHMITT GENMASK(9, 8) --#define PAD_DRIVE GENMASK(12, 10) -+#define PAD_SCHMITT_K1 GENMASK(9, 8) -+#define PAD_DRIVE_K1 GENMASK(12, 10) -+#define PAD_SCHMITT_K3 BIT(8) -+#define PAD_DRIVE_K3 GENMASK(12, 9) - #define PAD_PULLDOWN BIT(13) - #define PAD_PULLUP BIT(14) - #define PAD_PULL_EN BIT(15) - -+struct spacemit_pin_drv_strength { -+ u8 val; -+ u32 mA; -+}; -+ -+struct spacemit_pinctrl_dconf { -+ u64 schmitt_mask; -+ u64 drive_mask; -+ -+ struct spacemit_pin_drv_strength *ds_1v8_tbl; -+ size_t ds_1v8_tbl_num; -+ struct spacemit_pin_drv_strength *ds_3v3_tbl; -+ size_t ds_3v3_tbl_num; -+}; -+ - struct spacemit_pin { - u16 pin; - u16 flags; -@@ -67,6 +85,7 @@ struct spacemit_pinctrl_data { - const struct spacemit_pin *data; - u16 npins; - unsigned int (*pin_to_offset)(unsigned int pin); -+ const struct spacemit_pinctrl_dconf *dconf; - }; - - struct spacemit_pin_mux_config { -@@ -74,11 +93,6 @@ struct spacemit_pin_mux_config { - u32 config; - }; - --struct spacemit_pin_drv_strength { -- u8 val; -- u32 mA; --}; -- - /* map pin id to pinctrl register offset, refer MFPR definition */ - static unsigned int spacemit_k1_pin_to_offset(unsigned int pin) - { -@@ -193,23 +207,70 @@ static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev, - seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value); - } - --/* use IO high level output current as the table */ --static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = { -- { 0, 11 }, -- { 2, 21 }, -- { 4, 32 }, -- { 6, 42 }, -+static const struct spacemit_pinctrl_dconf k1_drive_conf = { -+ .drive_mask = PAD_DRIVE_K1, -+ .schmitt_mask = PAD_SCHMITT_K1, -+ .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) { -+ { 0, 11 }, -+ { 2, 21 }, -+ { 4, 32 }, -+ { 6, 42 }, -+ }, -+ .ds_1v8_tbl_num = 4, -+ .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) { -+ { 0, 7 }, -+ { 2, 10 }, -+ { 4, 13 }, -+ { 6, 16 }, -+ { 1, 19 }, -+ { 3, 23 }, -+ { 5, 26 }, -+ { 7, 29 }, -+ }, -+ .ds_3v3_tbl_num = 8, - }; - --static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = { -- { 0, 7 }, -- { 2, 10 }, -- { 4, 13 }, -- { 6, 16 }, -- { 1, 19 }, -- { 3, 23 }, -- { 5, 26 }, -- { 7, 29 }, -+static const struct spacemit_pinctrl_dconf k3_drive_conf = { -+ .drive_mask = PAD_DRIVE_K3, -+ .schmitt_mask = PAD_SCHMITT_K3, -+ .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) { -+ { 0, 2 }, -+ { 1, 4 }, -+ { 2, 6 }, -+ { 3, 7 }, -+ { 4, 9 }, -+ { 5, 11 }, -+ { 6, 13 }, -+ { 7, 14 }, -+ { 8, 21 }, -+ { 9, 23 }, -+ { 10, 25 }, -+ { 11, 26 }, -+ { 12, 28 }, -+ { 13, 30 }, -+ { 14, 31 }, -+ { 15, 33 }, -+ }, -+ .ds_1v8_tbl_num = 16, -+ .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) { -+ { 0, 3 }, -+ { 1, 5 }, -+ { 2, 7 }, -+ { 3, 9 }, -+ { 4, 11 }, -+ { 5, 13 }, -+ { 6, 15 }, -+ { 7, 17 }, -+ { 8, 25 }, -+ { 9, 27 }, -+ { 10, 29 }, -+ { 11, 31 }, -+ { 12, 33 }, -+ { 13, 35 }, -+ { 14, 37 }, -+ { 15, 38 }, -+ }, -+ .ds_3v3_tbl_num = 16, - }; - - static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl, -@@ -237,16 +298,17 @@ static inline u32 spacemit_get_ds_mA(struct spacemit_pin_drv_strength *tbl, - } - - static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type, -+ const struct spacemit_pinctrl_dconf *dconf, - u32 mA) - { - switch (type) { - case IO_TYPE_1V8: -- return spacemit_get_ds_value(spacemit_ds_1v8_tbl, -- ARRAY_SIZE(spacemit_ds_1v8_tbl), -+ return spacemit_get_ds_value(dconf->ds_1v8_tbl, -+ dconf->ds_1v8_tbl_num, - mA); - case IO_TYPE_3V3: -- return spacemit_get_ds_value(spacemit_ds_3v3_tbl, -- ARRAY_SIZE(spacemit_ds_3v3_tbl), -+ return spacemit_get_ds_value(dconf->ds_3v3_tbl, -+ dconf->ds_3v3_tbl_num, - mA); - default: - return 0; -@@ -254,16 +316,17 @@ static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type, - } - - static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type, -+ const struct spacemit_pinctrl_dconf *dconf, - u32 value) - { - switch (type) { - case IO_TYPE_1V8: -- return spacemit_get_ds_mA(spacemit_ds_1v8_tbl, -- ARRAY_SIZE(spacemit_ds_1v8_tbl), -- value & 0x6); -+ return spacemit_get_ds_mA(dconf->ds_1v8_tbl, -+ dconf->ds_1v8_tbl_num, -+ value); - case IO_TYPE_3V3: -- return spacemit_get_ds_mA(spacemit_ds_3v3_tbl, -- ARRAY_SIZE(spacemit_ds_3v3_tbl), -+ return spacemit_get_ds_mA(dconf->ds_3v3_tbl, -+ dconf->ds_3v3_tbl_num, - value); - default: - return 0; -@@ -510,6 +573,7 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, - #define ENABLE_DRV_STRENGTH BIT(1) - #define ENABLE_SLEW_RATE BIT(2) - static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, -+ const struct spacemit_pinctrl_dconf *dconf, - unsigned long *configs, - unsigned int num_configs, - u32 *value) -@@ -547,8 +611,8 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, - drv_strength = arg; - break; - case PIN_CONFIG_INPUT_SCHMITT: -- v &= ~PAD_SCHMITT; -- v |= FIELD_PREP(PAD_SCHMITT, arg); -+ v &= ~dconf->schmitt_mask; -+ v |= (arg << __ffs(dconf->schmitt_mask)) & dconf->schmitt_mask; - break; - case PIN_CONFIG_POWER_SOURCE: - voltage = arg; -@@ -584,10 +648,10 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, - } - } - -- val = spacemit_get_driver_strength(type, drv_strength); -+ val = spacemit_get_driver_strength(type, dconf, drv_strength); - -- v &= ~PAD_DRIVE; -- v |= FIELD_PREP(PAD_DRIVE, val); -+ v &= ~dconf->drive_mask; -+ v |= (val << __ffs(dconf->drive_mask)) & dconf->drive_mask; - } - - if (flag & ENABLE_SLEW_RATE) { -@@ -637,7 +701,8 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, - const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); - u32 value; - -- if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) -+ if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, -+ configs, num_configs, &value)) - return -EINVAL; - - return spacemit_pin_set_config(pctrl, pin, value); -@@ -659,7 +724,8 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, - return -EINVAL; - - spin = spacemit_get_pin(pctrl, group->grp.pins[0]); -- if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) -+ if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, -+ configs, num_configs, &value)) - return -EINVAL; - - for (i = 0; i < group->grp.npins; i++) -@@ -693,6 +759,7 @@ static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *seq, unsigned int pin) - { - struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); -+ const struct spacemit_pinctrl_dconf *dconf = pctrl->data->dconf; - const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); - enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin); - void __iomem *reg = spacemit_pin_to_reg(pctrl, pin); -@@ -703,17 +770,17 @@ static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev, - - seq_printf(seq, ", io type (%s)", io_type_desc[type]); - -- tmp = FIELD_GET(PAD_DRIVE, value); -+ tmp = (value & dconf->drive_mask) >> __ffs(dconf->drive_mask); - if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) { -- mA = spacemit_get_drive_strength_mA(type, tmp); -+ mA = spacemit_get_drive_strength_mA(type, dconf, tmp); - seq_printf(seq, ", drive strength (%d mA)", mA); - } - - /* drive strength depend on power source, so show all values */ - if (type == IO_TYPE_EXTERNAL) - seq_printf(seq, ", drive strength (%d or %d mA)", -- spacemit_get_drive_strength_mA(IO_TYPE_1V8, tmp), -- spacemit_get_drive_strength_mA(IO_TYPE_3V3, tmp)); -+ spacemit_get_drive_strength_mA(IO_TYPE_1V8, dconf, tmp), -+ spacemit_get_drive_strength_mA(IO_TYPE_3V3, dconf, tmp)); - - seq_printf(seq, ", register (0x%04x)", value); - } -@@ -1051,6 +1118,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { - .data = k1_pin_data, - .npins = ARRAY_SIZE(k1_pin_desc), - .pin_to_offset = spacemit_k1_pin_to_offset, -+ .dconf = &k1_drive_conf, - }; - - static const struct pinctrl_pin_desc k3_pin_desc[] = { -@@ -1387,6 +1455,7 @@ static const struct spacemit_pinctrl_data k3_pinctrl_data = { - .data = k3_pin_data, - .npins = ARRAY_SIZE(k3_pin_desc), - .pin_to_offset = spacemit_k3_pin_to_offset, -+ .dconf = &k3_drive_conf, - }; - - static const struct of_device_id k1_pinctrl_ids[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch b/SPECS/linux-lts-kmhv2/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch new file mode 100644 index 0000000000..8f6837bba8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch @@ -0,0 +1,48 @@ +From 404911e71521a30847ea8198f0e48c7d6c92dac5 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 14:42:40 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: pinctrl: update register + and IO power + +Change the size of the reg register to 0x1000 to match the hardware. +This register range covers the IO power domain's register addresses. + +The IO power domain registers are protected. In order to access the +protected IO power domain registers, a valid unlock sequence must be +performed by writing the required keys to the AIB Secure Access Register +(ASAR). + +The ASAR register resides within the APBC register address space. +A corresponding syscon property `spacemit,apbc` is added to allow +the pinctrl driver to access this register. + +Signed-off-by: Troy Mitchell +Acked-by: Linus Walleij +Link: https://lore.kernel.org/r/20260108-kx-pinctrl-aib-io-pwr-domain-v2-3-6bcb46146e53@linux.spacemit.com +Signed-off-by: Yixun Lan +(cherry picked from commit 4083d8d6c0aa445fc440d70a5258351c47547ee2) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 137fc26ddc29..e22a5f030fa2 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -628,10 +628,11 @@ i2c8: i2c@d401d800 { + + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k1-pinctrl"; +- reg = <0x0 0xd401e000 0x0 0x400>; ++ reg = <0x0 0xd401e000 0x0 0x1000>; + clocks = <&syscon_apbc CLK_AIB>, + <&syscon_apbc CLK_AIB_BUS>; + clock-names = "func", "bus"; ++ spacemit,apbc = <&syscon_apbc>; + }; + + pwm8: pwm@d4020000 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0097-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch b/SPECS/linux-lts-kmhv2/0097-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch deleted file mode 100644 index 6328b7b073..0000000000 --- a/SPECS/linux-lts-kmhv2/0097-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 9c53bc78545cc3c695e01922464a71c887179572 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 8 Jan 2026 14:42:38 +0800 -Subject: [PATCH 097/467] UPSTREAM: dt-bindings: pinctrl: spacemit: add syscon - property - -In order to access the protected IO power domain registers, a valid -unlock sequence must be performed by writing the required keys to the -AIB Secure Access Register (ASAR). - -The ASAR register resides within the APBC register address space. -A corresponding syscon property is added to allow the pinctrl driver -to access this register. - -Signed-off-by: Troy Mitchell -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Linus Walleij -(cherry picked from commit e817f0223d78818cd6c0e3480355c9a9cfbc0096) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -index 9a76cffcbaee..141dcedb81fb 100644 ---- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -+++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -@@ -32,6 +32,10 @@ properties: - resets: - maxItems: 1 - -+ spacemit,apbc: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: Phandle to syscon that access the protected register -+ - patternProperties: - '-cfg$': - type: object -@@ -138,6 +142,7 @@ examples: - clocks = <&syscon_apbc 42>, - <&syscon_apbc 94>; - clock-names = "func", "bus"; -+ spacemit,apbc = <&syscon_apbc>; - - uart0_2_cfg: uart0-2-cfg { - uart0-2-pins { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch b/SPECS/linux-lts-kmhv2/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch new file mode 100644 index 0000000000..9c1db3eb89 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch @@ -0,0 +1,78 @@ +From 33a192939d2dd110bc17a0f1c65a5c654c617d16 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 25 Dec 2025 14:24:20 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: update ratified version of + h, svinval, svnapot, svpbmt + +The descriptions for h, svinval, svnapot, and svpbmt extensions currently +reference the "20191213 version of the privileged ISA specification". +While an Unprivileged ISA document exists with that date, there is no +corresponding ratified Privileged ISA specification. + +These extensions were ratified in the RISC-V Instruction Set Manual, +Volume II: Privileged Architecture, Version 20211203. Update the +descriptions to reference the correct specification version. + +RISC-V International hosts a website [1] for ratified specifications. +Following the "Ratified ISA Specifications", historical versions of +Volume II Privileged ISA can be found. + +Link: https://riscv.org/specifications/ratified/ [1] +Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") +Acked-by: Conor Dooley +Signed-off-by: Guodong Xu +Signed-off-by: Conor Dooley +(cherry picked from commit fff010c776f715904ba0823bb347eac00dccffa2) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/extensions.yaml | 19 +++++++++++-------- + 1 file changed, 11 insertions(+), 8 deletions(-) + +diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml +index 543ac94718e8..aa38809ecf06 100644 +--- a/Documentation/devicetree/bindings/riscv/extensions.yaml ++++ b/Documentation/devicetree/bindings/riscv/extensions.yaml +@@ -117,8 +117,9 @@ properties: + + - const: h + description: +- The standard H extension for hypervisors as ratified in the 20191213 +- version of the privileged ISA specification. ++ The standard H extension for hypervisors as ratified in the RISC-V ++ Instruction Set Manual, Volume II Privileged Architecture, ++ Document Version 20211203. + + # multi-letter extensions, sorted alphanumerically + - const: smaia +@@ -202,20 +203,22 @@ properties: + - const: svinval + description: + The standard Svinval supervisor-level extension for fine-grained +- address-translation cache invalidation as ratified in the 20191213 +- version of the privileged ISA specification. ++ address-translation cache invalidation as ratified in the RISC-V ++ Instruction Set Manual, Volume II Privileged Architecture, ++ Document Version 20211203. + + - const: svnapot + description: + The standard Svnapot supervisor-level extensions for napot +- translation contiguity as ratified in the 20191213 version of the +- privileged ISA specification. ++ translation contiguity as ratified in the RISC-V Instruction Set ++ Manual, Volume II Privileged Architecture, Document Version ++ 20211203. + + - const: svpbmt + description: + The standard Svpbmt supervisor-level extensions for page-based +- memory types as ratified in the 20191213 version of the privileged +- ISA specification. ++ memory types as ratified in the RISC-V Instruction Set Manual, ++ Volume II Privileged Architecture, Document Version 20211203. + + - const: svvptc + description: +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch b/SPECS/linux-lts-kmhv2/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch new file mode 100644 index 0000000000..03b356c1c3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch @@ -0,0 +1,91 @@ +From 8b082ec91bd4cfaf11f3a1b69d1b66ea599ba3f1 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Sat, 10 Jan 2026 13:18:18 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add B ISA extension + description + +Add description of the single-letter B extension for Bit Manipulation. +B is mandatory for RVA23U64. + +The B extension is ratified in the 20240411 version of the unprivileged +ISA specification. According to the ratified spec, the B standard +extension comprises instructions provided by the Zba, Zbb, and Zbs +extensions. + +Add two-way dependency check to enforce that B implies Zba/Zbb/Zbs; and +when Zba/Zbb/Zbs (all of them) are specified, then B must be added too. + +The reason why B/Zba/Zbb/Zbs must coexist at the same time is that +unlike other single-letter extensions, B was ratified (Apr/2024) much +later than its component extensions Zba/Zbb/Zbs (Jun/2021). + +When "b" is specified, zba/zbb/zbs must be present to ensure +backward compatibility with existing software and kernels that only +look for the explicit component strings. + +When all three components zba/zbb/zbs are specified, "b" should also be +present. Making "b" mandatory when all three components are present. + +Existing devicetrees with zba/zbb/zbs but without "b" will generate +warnings that can be fixed in follow-up patches. + +Signed-off-by: Guodong Xu +Signed-off-by: Conor Dooley +(cherry picked from commit 0cdb7fc1879b1b858463125630f4dd5af6b111ad) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/extensions.yaml | 31 +++++++++++++++++++ + 1 file changed, 31 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml +index aa38809ecf06..36afd1cc42cf 100644 +--- a/Documentation/devicetree/bindings/riscv/extensions.yaml ++++ b/Documentation/devicetree/bindings/riscv/extensions.yaml +@@ -109,6 +109,13 @@ properties: + The standard C extension for compressed instructions, as ratified in + the 20191213 version of the unprivileged ISA specification. + ++ - const: b ++ description: ++ The standard B extension for bit manipulation instructions, as ++ ratified in the 20240411 version of the unprivileged ISA ++ specification. The B standard extension comprises instructions ++ provided by the Zba, Zbb, and Zbs extensions. ++ + - const: v + description: + The standard V extension for vector operations, as ratified +@@ -727,6 +734,30 @@ properties: + then: + contains: + const: f ++ # B comprises Zba, Zbb, and Zbs ++ - if: ++ contains: ++ const: b ++ then: ++ allOf: ++ - contains: ++ const: zba ++ - contains: ++ const: zbb ++ - contains: ++ const: zbs ++ # Zba, Zbb, Zbs together require B ++ - if: ++ allOf: ++ - contains: ++ const: zba ++ - contains: ++ const: zbb ++ - contains: ++ const: zbs ++ then: ++ contains: ++ const: b + # Zcb depends on Zca + - if: + contains: +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0098-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch b/SPECS/linux-lts-kmhv2/0098-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch deleted file mode 100644 index 220390317f..0000000000 --- a/SPECS/linux-lts-kmhv2/0098-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch +++ /dev/null @@ -1,263 +0,0 @@ -From 4d7b192ae28c8fd62c4887c36d1d2daf3d5537ab Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 8 Jan 2026 14:42:39 +0800 -Subject: [PATCH 098/467] UPSTREAM: pinctrl: spacemit: support I/O power domain - configuration - -Dual-voltage GPIO banks default to 3.3V operation. Even when a bank is -externally supplied with 1.8V, the internal logic remains in the 3.3V -domain, leading to functional failures. - -Add support for programming the IO domain power control registers to -allow explicit configuration for 1.8V operation. - -These registers are secure due to hardware safety constraints. -Specifically, configuring the domain for 1.8V while externally supplying -3.3V causes back-powering and potential pin damage. Consequently, access -requires unlocking the AIB Secure Access Register (ASAR) in the APBC -block before any read or write operation. - -Signed-off-by: Troy Mitchell -Signed-off-by: Linus Walleij -(cherry picked from commit 450e2487d5a28260f70ad7fbf3060e7f8304203d) -Signed-off-by: Han Gao ---- - drivers/pinctrl/spacemit/pinctrl-k1.c | 129 +++++++++++++++++++++++++- - 1 file changed, 126 insertions(+), 3 deletions(-) - -diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c -index 07267c5f0f44..71390402aaa6 100644 ---- a/drivers/pinctrl/spacemit/pinctrl-k1.c -+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c -@@ -7,8 +7,10 @@ - #include - #include - #include -+#include - #include - #include -+#include - #include - #include - -@@ -47,6 +49,27 @@ - #define PAD_PULLUP BIT(14) - #define PAD_PULL_EN BIT(15) - -+#define IO_PWR_DOMAIN_OFFSET 0x800 -+ -+#define IO_PWR_DOMAIN_GPIO2_Kx 0x0c -+#define IO_PWR_DOMAIN_MMC_Kx 0x1c -+ -+#define IO_PWR_DOMAIN_GPIO3_K1 0x10 -+#define IO_PWR_DOMAIN_QSPI_K1 0x20 -+ -+#define IO_PWR_DOMAIN_GPIO1_K3 0x04 -+#define IO_PWR_DOMAIN_GPIO5_K3 0x10 -+#define IO_PWR_DOMAIN_GPIO4_K3 0x20 -+#define IO_PWR_DOMAIN_QSPI_K3 0x2c -+ -+#define IO_PWR_DOMAIN_V18EN BIT(2) -+ -+#define APBC_ASFAR 0x50 -+#define APBC_ASSAR 0x54 -+ -+#define APBC_ASFAR_AKEY 0xbaba -+#define APBC_ASSAR_AKEY 0xeb10 -+ - struct spacemit_pin_drv_strength { - u8 val; - u32 mA; -@@ -78,6 +101,8 @@ struct spacemit_pinctrl { - raw_spinlock_t lock; - - void __iomem *regs; -+ -+ struct regmap *regmap_apbc; - }; - - struct spacemit_pinctrl_data { -@@ -85,6 +110,7 @@ struct spacemit_pinctrl_data { - const struct spacemit_pin *data; - u16 npins; - unsigned int (*pin_to_offset)(unsigned int pin); -+ unsigned int (*pin_to_io_pd_offset)(unsigned int pin); - const struct spacemit_pinctrl_dconf *dconf; - }; - -@@ -146,6 +172,56 @@ static unsigned int spacemit_k3_pin_to_offset(unsigned int pin) - return offset << 2; - } - -+static unsigned int spacemit_k1_pin_to_io_pd_offset(unsigned int pin) -+{ -+ unsigned int offset = 0; -+ -+ switch (pin) { -+ case 47 ... 52: -+ offset = IO_PWR_DOMAIN_GPIO3_K1; -+ break; -+ case 75 ... 80: -+ offset = IO_PWR_DOMAIN_GPIO2_Kx; -+ break; -+ case 98 ... 103: -+ offset = IO_PWR_DOMAIN_QSPI_K1; -+ break; -+ case 104 ... 109: -+ offset = IO_PWR_DOMAIN_MMC_Kx; -+ break; -+ } -+ -+ return offset; -+} -+ -+static unsigned int spacemit_k3_pin_to_io_pd_offset(unsigned int pin) -+{ -+ unsigned int offset = 0; -+ -+ switch (pin) { -+ case 0 ... 20: -+ offset = IO_PWR_DOMAIN_GPIO1_K3; -+ break; -+ case 21 ... 41: -+ offset = IO_PWR_DOMAIN_GPIO2_Kx; -+ break; -+ case 76 ... 98: -+ offset = IO_PWR_DOMAIN_GPIO4_K3; -+ break; -+ case 99 ... 127: -+ offset = IO_PWR_DOMAIN_GPIO5_K3; -+ break; -+ case 132 ... 137: -+ offset = IO_PWR_DOMAIN_MMC_Kx; -+ break; -+ case 138 ... 144: -+ offset = IO_PWR_DOMAIN_QSPI_K3; -+ break; -+ } -+ -+ return offset; -+} -+ - static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, - unsigned int pin) - { -@@ -365,6 +441,42 @@ static int spacemit_pctrl_check_power(struct pinctrl_dev *pctldev, - return 0; - } - -+static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl, -+ const struct spacemit_pin *spin, -+ const enum spacemit_pin_io_type type) -+{ -+ u32 offset, val = 0; -+ -+ if (!pctrl->regmap_apbc) -+ return; -+ -+ offset = pctrl->data->pin_to_io_pd_offset(spin->pin); -+ -+ /* Other bits are reserved so don't need to save them */ -+ if (type == IO_TYPE_1V8) -+ val = IO_PWR_DOMAIN_V18EN; -+ -+ /* -+ * IO power domain registers are protected and cannot be accessed -+ * directly. Before performing any read or write to the IO power -+ * domain registers, an explicit unlock sequence must be issued -+ * via the AIB Secure Access Register (ASAR). -+ * -+ * The unlock sequence allows exactly one subsequent access to the -+ * IO power domain registers. After that access completes, the ASAR -+ * keys are automatically cleared, and the registers become locked -+ * again. -+ * -+ * This mechanism ensures that IO power domain configuration is -+ * performed intentionally, as incorrect voltage settings may -+ * result in functional failures or hardware damage. -+ */ -+ regmap_write(pctrl->regmap_apbc, APBC_ASFAR, APBC_ASFAR_AKEY); -+ regmap_write(pctrl->regmap_apbc, APBC_ASSAR, APBC_ASSAR_AKEY); -+ -+ writel_relaxed(val, pctrl->regs + IO_PWR_DOMAIN_OFFSET + offset); -+} -+ - static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **maps, -@@ -572,7 +684,8 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, - - #define ENABLE_DRV_STRENGTH BIT(1) - #define ENABLE_SLEW_RATE BIT(2) --static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, -+static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, -+ const struct spacemit_pin *spin, - const struct spacemit_pinctrl_dconf *dconf, - unsigned long *configs, - unsigned int num_configs, -@@ -646,6 +759,7 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, - default: - return -EINVAL; - } -+ spacemit_set_io_pwr_domain(pctrl, spin, type); - } - - val = spacemit_get_driver_strength(type, dconf, drv_strength); -@@ -701,7 +815,7 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, - const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); - u32 value; - -- if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, -+ if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, - configs, num_configs, &value)) - return -EINVAL; - -@@ -724,7 +838,7 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, - return -EINVAL; - - spin = spacemit_get_pin(pctrl, group->grp.pins[0]); -- if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, -+ if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, - configs, num_configs, &value)) - return -EINVAL; - -@@ -795,6 +909,7 @@ static const struct pinconf_ops spacemit_pinconf_ops = { - - static int spacemit_pinctrl_probe(struct platform_device *pdev) - { -+ struct device_node *np = pdev->dev.of_node; - struct device *dev = &pdev->dev; - struct spacemit_pinctrl *pctrl; - struct clk *func_clk, *bus_clk; -@@ -816,6 +931,12 @@ static int spacemit_pinctrl_probe(struct platform_device *pdev) - if (IS_ERR(pctrl->regs)) - return PTR_ERR(pctrl->regs); - -+ pctrl->regmap_apbc = syscon_regmap_lookup_by_phandle(np, "spacemit,apbc"); -+ if (IS_ERR(pctrl->regmap_apbc)) { -+ dev_warn(dev, "no syscon found, disable power voltage switch functionality\n"); -+ pctrl->regmap_apbc = NULL; -+ } -+ - func_clk = devm_clk_get_enabled(dev, "func"); - if (IS_ERR(func_clk)) - return dev_err_probe(dev, PTR_ERR(func_clk), "failed to get func clock\n"); -@@ -1118,6 +1239,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { - .data = k1_pin_data, - .npins = ARRAY_SIZE(k1_pin_desc), - .pin_to_offset = spacemit_k1_pin_to_offset, -+ .pin_to_io_pd_offset = spacemit_k1_pin_to_io_pd_offset, - .dconf = &k1_drive_conf, - }; - -@@ -1455,6 +1577,7 @@ static const struct spacemit_pinctrl_data k3_pinctrl_data = { - .data = k3_pin_data, - .npins = ARRAY_SIZE(k3_pin_desc), - .pin_to_offset = spacemit_k3_pin_to_offset, -+ .pin_to_io_pd_offset = spacemit_k3_pin_to_io_pd_offset, - .dconf = &k3_drive_conf, - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch b/SPECS/linux-lts-kmhv2/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch new file mode 100644 index 0000000000..f6b09dc50b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch @@ -0,0 +1,131 @@ +From 293192824603c354264f56113a64fc91d889d750 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Sat, 10 Jan 2026 13:18:19 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add descriptions for + Za64rs, Ziccamoa, Ziccif, and Zicclsm + +Add descriptions for four extensions: Za64rs, Ziccamoa, Ziccif, and +Zicclsm. These extensions are ratified in RISC-V Profiles Version 1.0 +(commit b1d806605f87 "Updated to ratified state."). + +They are introduced as new extension names for existing features and +regulate implementation details for RISC-V Profile compliance. According +to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, they are +mandatory for the following profiles: + + - za64rs: Mandatory in RVA22U64, RVA23U64 + - ziccamoa: Mandatory in RVA20U64, RVA22U64, RVA23U64 + - ziccif: Mandatory in RVA20U64, RVA22U64, RVA23U64 + - zicclsm: Mandatory in RVA20U64, RVA22U64, RVA23U64 + +Ziccrse specifies the main memory must support "RsrvEventual", which is +one (totally there are four) of the support level for Load-Reserved/ +Store-Conditional (LR/SC) atomic instructions. Thus it depends on Zalrsc. + +Ziccamoa specifies the main memory must support AMOArithmetic, among the +four levels of PMA support defined for AMOs in the A extension. Thus it +depends on Zaamo. + +Za64rs defines reservation sets are contiguous, naturally aligned, and a +maximum of 64 bytes. Za64rs is consumed by two extensions: Zalrsc and +Zawrs. Zawrs itself depends on Zalrsc too. + +Based on the relationship that "A" = Zaamo + Zalrsc, add the following +dependencies checks: + Za64rs -> Zalrsc or A + Ziccrse -> Zalrsc or A + Ziccamoa -> Zaamo or A + +Signed-off-by: Guodong Xu +Acked-by: Conor Dooley +Signed-off-by: Conor Dooley +(cherry picked from commit b321256a4f36227e0c1ae54e8c6c48524dcba83d) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/extensions.yaml | 49 +++++++++++++++++++ + 1 file changed, 49 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml +index 36afd1cc42cf..bebbd7797d49 100644 +--- a/Documentation/devicetree/bindings/riscv/extensions.yaml ++++ b/Documentation/devicetree/bindings/riscv/extensions.yaml +@@ -234,6 +234,12 @@ properties: + as ratified at commit 4a69197e5617 ("Update to ratified state") of + riscv-svvptc. + ++ - const: za64rs ++ description: ++ The standard Za64rs extension for reservation set size of at most ++ 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit ++ b1d806605f87 ("Updated to ratified state.") ++ + - const: zaamo + description: | + The standard Zaamo extension for atomic memory operations as +@@ -370,6 +376,27 @@ properties: + in commit 64074bc ("Update version numbers for Zfh/Zfinx") of + riscv-isa-manual. + ++ - const: ziccamoa ++ description: ++ The standard Ziccamoa extension for main memory (cacheability and ++ coherence) must support all atomics in A, as ratified in RISC-V ++ Profiles Version 1.0, with commit b1d806605f87 ("Updated to ++ ratified state.") ++ ++ - const: ziccif ++ description: ++ The standard Ziccif extension for main memory (cacheability and ++ coherence) instruction fetch atomicity, as ratified in RISC-V ++ Profiles Version 1.0, with commit b1d806605f87 ("Updated to ++ ratified state.") ++ ++ - const: zicclsm ++ description: ++ The standard Zicclsm extension for main memory (cacheability and ++ coherence) must support misaligned loads and stores, as ratified ++ in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated ++ to ratified state.") ++ + - const: ziccrse + description: + The standard Ziccrse extension which provides forward progress +@@ -758,6 +785,18 @@ properties: + then: + contains: + const: b ++ # Za64rs and Ziccrse depend on Zalrsc or A ++ - if: ++ contains: ++ anyOf: ++ - const: za64rs ++ - const: ziccrse ++ then: ++ oneOf: ++ - contains: ++ const: zalrsc ++ - contains: ++ const: a + # Zcb depends on Zca + - if: + contains: +@@ -799,6 +838,16 @@ properties: + then: + contains: + const: f ++ # Ziccamoa depends on Zaamo or A ++ - if: ++ contains: ++ const: ziccamoa ++ then: ++ oneOf: ++ - contains: ++ const: zaamo ++ - contains: ++ const: a + # Zvfbfmin depends on V or Zve32f + - if: + contains: +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0099-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch b/SPECS/linux-lts-kmhv2/0099-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch deleted file mode 100644 index 678fbcc0c7..0000000000 --- a/SPECS/linux-lts-kmhv2/0099-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 5379340efd812454feda9bf0ebc36dad03992fda Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 8 Jan 2026 14:42:40 +0800 -Subject: [PATCH 099/467] UPSTREAM: riscv: dts: spacemit: pinctrl: update - register and IO power - -Change the size of the reg register to 0x1000 to match the hardware. -This register range covers the IO power domain's register addresses. - -The IO power domain registers are protected. In order to access the -protected IO power domain registers, a valid unlock sequence must be -performed by writing the required keys to the AIB Secure Access Register -(ASAR). - -The ASAR register resides within the APBC register address space. -A corresponding syscon property `spacemit,apbc` is added to allow -the pinctrl driver to access this register. - -Signed-off-by: Troy Mitchell -Acked-by: Linus Walleij -Link: https://lore.kernel.org/r/20260108-kx-pinctrl-aib-io-pwr-domain-v2-3-6bcb46146e53@linux.spacemit.com -Signed-off-by: Yixun Lan -(cherry picked from commit 4083d8d6c0aa445fc440d70a5258351c47547ee2) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 137fc26ddc29..e22a5f030fa2 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -628,10 +628,11 @@ i2c8: i2c@d401d800 { - - pinctrl: pinctrl@d401e000 { - compatible = "spacemit,k1-pinctrl"; -- reg = <0x0 0xd401e000 0x0 0x400>; -+ reg = <0x0 0xd401e000 0x0 0x1000>; - clocks = <&syscon_apbc CLK_AIB>, - <&syscon_apbc CLK_AIB_BUS>; - clock-names = "func", "bus"; -+ spacemit,apbc = <&syscon_apbc>; - }; - - pwm8: pwm@d4020000 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch b/SPECS/linux-lts-kmhv2/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch new file mode 100644 index 0000000000..347e39618f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch @@ -0,0 +1,89 @@ +From 9f1f119c5d51420861951a5660e8714b87fcf2ce Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Sat, 10 Jan 2026 13:18:20 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add Ssccptr, Sscounterenw, + Sstvala, Sstvecd, Ssu64xl + +Add descriptions for five new extensions: Ssccptr, Sscounterenw, Sstvala, +Sstvecd, and Ssu64xl. These extensions are ratified in RISC-V Profiles +Version 1.0 (commit b1d806605f87 "Updated to ratified state."). + +They are introduced as new extension names for existing features and +regulate implementation details for RISC-V Profile compliance. According +to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, their +requirement status are: + + - Ssccptr: Mandatory in RVA20S64, RVA22S64, RVA23S64 + - Sscounterenw: Mandatory in RVA22S64, RVA23S64 + - Sstvala: Mandatory in RVA20S64, RVA22S64, RVA23S64 + - Sstvecd: Mandatory in RVA20S64, RVA22S64, RVA23S64 + - Ssu64xl: Optional in RVA20S64, RVA22S64; Mandatory in RVA23S64 + +Signed-off-by: Guodong Xu +Acked-by: Conor Dooley +Signed-off-by: Conor Dooley +(cherry picked from commit c712413333f8e19cc3de4e9cd1a3ed8a53169cc9) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/extensions.yaml | 32 +++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml +index bebbd7797d49..81cff2e5b06f 100644 +--- a/Documentation/devicetree/bindings/riscv/extensions.yaml ++++ b/Documentation/devicetree/bindings/riscv/extensions.yaml +@@ -161,12 +161,26 @@ properties: + behavioural changes to interrupts as frozen at commit ccbddab + ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + ++ - const: ssccptr ++ description: | ++ The standard Ssccptr extension for main memory (cacheability and ++ coherence) hardware page-table reads, as ratified in RISC-V ++ Profiles Version 1.0, with commit b1d806605f87 ("Updated to ++ ratified state.") ++ + - const: sscofpmf + description: | + The standard Sscofpmf supervisor-level extension for count overflow + and mode-based filtering as ratified at commit 01d1df0 ("Add ability + to manually trigger workflow. (#2)") of riscv-count-overflow. + ++ - const: sscounterenw ++ description: | ++ The standard Sscounterenw extension for support writable enables ++ in scounteren for any supported counter, as ratified in RISC-V ++ Profiles Version 1.0, with commit b1d806605f87 ("Updated to ++ ratified state.") ++ + - const: ssnpm + description: | + The standard Ssnpm extension for next-mode pointer masking as +@@ -179,6 +193,24 @@ properties: + ratified at commit 3f9ed34 ("Add ability to manually trigger + workflow. (#2)") of riscv-time-compare. + ++ - const: sstvala ++ description: | ++ The standard Sstvala extension for stval provides all needed values ++ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 ++ ("Updated to ratified state.") ++ ++ - const: sstvecd ++ description: | ++ The standard Sstvecd extension for stvec supports Direct mode as ++ ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 ++ ("Updated to ratified state.") ++ ++ - const: ssu64xl ++ description: | ++ The standard Ssu64xl extension for UXLEN=64 must be supported, as ++ ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 ++ ("Updated to ratified state.") ++ + - const: svade + description: | + The standard Svade supervisor-level extension for SW-managed PTE A/D +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0100-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch b/SPECS/linux-lts-kmhv2/0100-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch deleted file mode 100644 index 3f371e8651..0000000000 --- a/SPECS/linux-lts-kmhv2/0100-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch +++ /dev/null @@ -1,78 +0,0 @@ -From bd353c8584ce96ff556b222bfcbd29bbce5d0a16 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 25 Dec 2025 14:24:20 +0800 -Subject: [PATCH 100/467] UPSTREAM: dt-bindings: riscv: update ratified version - of h, svinval, svnapot, svpbmt - -The descriptions for h, svinval, svnapot, and svpbmt extensions currently -reference the "20191213 version of the privileged ISA specification". -While an Unprivileged ISA document exists with that date, there is no -corresponding ratified Privileged ISA specification. - -These extensions were ratified in the RISC-V Instruction Set Manual, -Volume II: Privileged Architecture, Version 20211203. Update the -descriptions to reference the correct specification version. - -RISC-V International hosts a website [1] for ratified specifications. -Following the "Ratified ISA Specifications", historical versions of -Volume II Privileged ISA can be found. - -Link: https://riscv.org/specifications/ratified/ [1] -Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") -Acked-by: Conor Dooley -Signed-off-by: Guodong Xu -Signed-off-by: Conor Dooley -(cherry picked from commit fff010c776f715904ba0823bb347eac00dccffa2) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/riscv/extensions.yaml | 19 +++++++++++-------- - 1 file changed, 11 insertions(+), 8 deletions(-) - -diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml -index 543ac94718e8..aa38809ecf06 100644 ---- a/Documentation/devicetree/bindings/riscv/extensions.yaml -+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml -@@ -117,8 +117,9 @@ properties: - - - const: h - description: -- The standard H extension for hypervisors as ratified in the 20191213 -- version of the privileged ISA specification. -+ The standard H extension for hypervisors as ratified in the RISC-V -+ Instruction Set Manual, Volume II Privileged Architecture, -+ Document Version 20211203. - - # multi-letter extensions, sorted alphanumerically - - const: smaia -@@ -202,20 +203,22 @@ properties: - - const: svinval - description: - The standard Svinval supervisor-level extension for fine-grained -- address-translation cache invalidation as ratified in the 20191213 -- version of the privileged ISA specification. -+ address-translation cache invalidation as ratified in the RISC-V -+ Instruction Set Manual, Volume II Privileged Architecture, -+ Document Version 20211203. - - - const: svnapot - description: - The standard Svnapot supervisor-level extensions for napot -- translation contiguity as ratified in the 20191213 version of the -- privileged ISA specification. -+ translation contiguity as ratified in the RISC-V Instruction Set -+ Manual, Volume II Privileged Architecture, Document Version -+ 20211203. - - - const: svpbmt - description: - The standard Svpbmt supervisor-level extensions for page-based -- memory types as ratified in the 20191213 version of the privileged -- ISA specification. -+ memory types as ratified in the RISC-V Instruction Set Manual, -+ Volume II Privileged Architecture, Document Version 20211203. - - - const: svvptc - description: --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0101-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch b/SPECS/linux-lts-kmhv2/0101-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch deleted file mode 100644 index 3298ffafa4..0000000000 --- a/SPECS/linux-lts-kmhv2/0101-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch +++ /dev/null @@ -1,91 +0,0 @@ -From b7ad5620e1cca351de602305d9722ab055f70643 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Sat, 10 Jan 2026 13:18:18 +0800 -Subject: [PATCH 101/467] UPSTREAM: dt-bindings: riscv: Add B ISA extension - description - -Add description of the single-letter B extension for Bit Manipulation. -B is mandatory for RVA23U64. - -The B extension is ratified in the 20240411 version of the unprivileged -ISA specification. According to the ratified spec, the B standard -extension comprises instructions provided by the Zba, Zbb, and Zbs -extensions. - -Add two-way dependency check to enforce that B implies Zba/Zbb/Zbs; and -when Zba/Zbb/Zbs (all of them) are specified, then B must be added too. - -The reason why B/Zba/Zbb/Zbs must coexist at the same time is that -unlike other single-letter extensions, B was ratified (Apr/2024) much -later than its component extensions Zba/Zbb/Zbs (Jun/2021). - -When "b" is specified, zba/zbb/zbs must be present to ensure -backward compatibility with existing software and kernels that only -look for the explicit component strings. - -When all three components zba/zbb/zbs are specified, "b" should also be -present. Making "b" mandatory when all three components are present. - -Existing devicetrees with zba/zbb/zbs but without "b" will generate -warnings that can be fixed in follow-up patches. - -Signed-off-by: Guodong Xu -Signed-off-by: Conor Dooley -(cherry picked from commit 0cdb7fc1879b1b858463125630f4dd5af6b111ad) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/riscv/extensions.yaml | 31 +++++++++++++++++++ - 1 file changed, 31 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml -index aa38809ecf06..36afd1cc42cf 100644 ---- a/Documentation/devicetree/bindings/riscv/extensions.yaml -+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml -@@ -109,6 +109,13 @@ properties: - The standard C extension for compressed instructions, as ratified in - the 20191213 version of the unprivileged ISA specification. - -+ - const: b -+ description: -+ The standard B extension for bit manipulation instructions, as -+ ratified in the 20240411 version of the unprivileged ISA -+ specification. The B standard extension comprises instructions -+ provided by the Zba, Zbb, and Zbs extensions. -+ - - const: v - description: - The standard V extension for vector operations, as ratified -@@ -727,6 +734,30 @@ properties: - then: - contains: - const: f -+ # B comprises Zba, Zbb, and Zbs -+ - if: -+ contains: -+ const: b -+ then: -+ allOf: -+ - contains: -+ const: zba -+ - contains: -+ const: zbb -+ - contains: -+ const: zbs -+ # Zba, Zbb, Zbs together require B -+ - if: -+ allOf: -+ - contains: -+ const: zba -+ - contains: -+ const: zbb -+ - contains: -+ const: zbs -+ then: -+ contains: -+ const: b - # Zcb depends on Zca - - if: - contains: --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch b/SPECS/linux-lts-kmhv2/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch new file mode 100644 index 0000000000..f4ee934072 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch @@ -0,0 +1,118 @@ +From 1642e810c6656b4e941561a7bb884e733c44a2f6 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Sat, 10 Jan 2026 13:18:21 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add Sha and its comprised + extensions + +Add descriptions for the Sha extension and the seven extensions it +comprises: Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, +and Ssstateen. + +Sha is ratified in the RVA23 Profiles Version 1.0 (commit 0273f3c921b6 +"rva23/rvb23 ratified") as a new profile-defined extension that captures +the full set of features that are mandated to be supported along with +the H extension. + +Extensions Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, +and Ssstateen are ratified in the RISC-V Profiles Version 1.0 (commit +b1d806605f87 "Updated to ratified state"). + +The requirement status for Sha and its comprised extension in RISC-V +Profiles are: + - Sha: Mandatory in RVA23S64 + - H: Optional in RVA22S64; Mandatory in RVA23S64 + - Shcounterenw: Optional in RVA22S64; Mandatory in RVA23S64 + - Shgatpa: Optional in RVA22S64; Mandatory in RVA23S64 + - Shtvala: Optional in RVA22S64; Mandatory in RVA23S64 + - Shvsatpa: Optional in RVA22S64; Mandatory in RVA23S64 + - Shvstvala: Optional in RVA22S64; Mandatory in RVA23S64 + - Shvstvecd: Optional in RVA22S64; Mandatory in RVA23S64 + - Ssstateen: Optional in RVA22S64; Mandatory in RVA23S64 + +Signed-off-by: Guodong Xu +Acked-by: Conor Dooley +Signed-off-by: Conor Dooley +(cherry picked from commit 89febd6a02768200fcfc86ee57f1ece632805bff) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/extensions.yaml | 57 +++++++++++++++++++ + 1 file changed, 57 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml +index 81cff2e5b06f..abe72eaa6c59 100644 +--- a/Documentation/devicetree/bindings/riscv/extensions.yaml ++++ b/Documentation/devicetree/bindings/riscv/extensions.yaml +@@ -129,6 +129,57 @@ properties: + Document Version 20211203. + + # multi-letter extensions, sorted alphanumerically ++ - const: sha ++ description: | ++ The standard Sha extension for augmented hypervisor extension as ++ ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6 ++ ("rva23/rvb23 ratified"). ++ ++ Sha captures the full set of features that are mandated to be ++ supported along with the H extension. Sha comprises the following ++ extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, ++ Shvstvecd, and Ssstateen. ++ ++ - const: shcounterenw ++ description: | ++ The standard Shcounterenw extension for support writable enables ++ in hcounteren for any supported counter, as ratified in RISC-V ++ Profiles Version 1.0, with commit b1d806605f87 ("Updated to ++ ratified state.") ++ ++ - const: shgatpa ++ description: | ++ The standard Shgatpa extension indicates that for each supported ++ virtual memory scheme SvNN supported in satp, the corresponding ++ hgatp SvNNx4 mode must be supported. The hgatp mode Bare must ++ also be supported. It is ratified in RISC-V Profiles Version 1.0, ++ with commit b1d806605f87 ("Updated to ratified state.") ++ ++ - const: shtvala ++ description: | ++ The standard Shtvala extension for htval be written with the ++ faulting guest physical address in all circumstances permitted by ++ the ISA. It is ratified in RISC-V Profiles Version 1.0, with ++ commit b1d806605f87 ("Updated to ratified state.") ++ ++ - const: shvsatpa ++ description: | ++ The standard Shvsatpa extension for vsatp supporting all translation ++ modes supported in satp, as ratified in RISC-V Profiles Version 1.0, ++ with commit b1d806605f87 ("Updated to ratified state.") ++ ++ - const: shvstvala ++ description: | ++ The standard Shvstvala extension for vstval provides all needed ++ values as ratified in RISC-V Profiles Version 1.0, with commit ++ b1d806605f87 ("Updated to ratified state.") ++ ++ - const: shvstvecd ++ description: | ++ The standard Shvstvecd extension for vstvec supporting Direct mode, ++ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 ++ ("Updated to ratified state.") ++ + - const: smaia + description: | + The standard Smaia supervisor-level extension for the advanced +@@ -187,6 +238,12 @@ properties: + ratified at commit d70011dde6c2 ("Update to ratified state") + of riscv-j-extension. + ++ - const: ssstateen ++ description: | ++ The standard Ssstateen extension for supervisor-mode view of the ++ state-enable extension, as ratified in RISC-V Profiles Version 1.0, ++ with commit b1d806605f87 ("Updated to ratified state.") ++ + - const: sstc + description: | + The standard Sstc supervisor-level extension for time compare as +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0102-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch b/SPECS/linux-lts-kmhv2/0102-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch deleted file mode 100644 index 10b2fa9c6e..0000000000 --- a/SPECS/linux-lts-kmhv2/0102-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 40de97191a9ea8701aed74a3c0772761a8046235 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Sat, 10 Jan 2026 13:18:19 +0800 -Subject: [PATCH 102/467] UPSTREAM: dt-bindings: riscv: Add descriptions for - Za64rs, Ziccamoa, Ziccif, and Zicclsm - -Add descriptions for four extensions: Za64rs, Ziccamoa, Ziccif, and -Zicclsm. These extensions are ratified in RISC-V Profiles Version 1.0 -(commit b1d806605f87 "Updated to ratified state."). - -They are introduced as new extension names for existing features and -regulate implementation details for RISC-V Profile compliance. According -to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, they are -mandatory for the following profiles: - - - za64rs: Mandatory in RVA22U64, RVA23U64 - - ziccamoa: Mandatory in RVA20U64, RVA22U64, RVA23U64 - - ziccif: Mandatory in RVA20U64, RVA22U64, RVA23U64 - - zicclsm: Mandatory in RVA20U64, RVA22U64, RVA23U64 - -Ziccrse specifies the main memory must support "RsrvEventual", which is -one (totally there are four) of the support level for Load-Reserved/ -Store-Conditional (LR/SC) atomic instructions. Thus it depends on Zalrsc. - -Ziccamoa specifies the main memory must support AMOArithmetic, among the -four levels of PMA support defined for AMOs in the A extension. Thus it -depends on Zaamo. - -Za64rs defines reservation sets are contiguous, naturally aligned, and a -maximum of 64 bytes. Za64rs is consumed by two extensions: Zalrsc and -Zawrs. Zawrs itself depends on Zalrsc too. - -Based on the relationship that "A" = Zaamo + Zalrsc, add the following -dependencies checks: - Za64rs -> Zalrsc or A - Ziccrse -> Zalrsc or A - Ziccamoa -> Zaamo or A - -Signed-off-by: Guodong Xu -Acked-by: Conor Dooley -Signed-off-by: Conor Dooley -(cherry picked from commit b321256a4f36227e0c1ae54e8c6c48524dcba83d) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/riscv/extensions.yaml | 49 +++++++++++++++++++ - 1 file changed, 49 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml -index 36afd1cc42cf..bebbd7797d49 100644 ---- a/Documentation/devicetree/bindings/riscv/extensions.yaml -+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml -@@ -234,6 +234,12 @@ properties: - as ratified at commit 4a69197e5617 ("Update to ratified state") of - riscv-svvptc. - -+ - const: za64rs -+ description: -+ The standard Za64rs extension for reservation set size of at most -+ 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit -+ b1d806605f87 ("Updated to ratified state.") -+ - - const: zaamo - description: | - The standard Zaamo extension for atomic memory operations as -@@ -370,6 +376,27 @@ properties: - in commit 64074bc ("Update version numbers for Zfh/Zfinx") of - riscv-isa-manual. - -+ - const: ziccamoa -+ description: -+ The standard Ziccamoa extension for main memory (cacheability and -+ coherence) must support all atomics in A, as ratified in RISC-V -+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to -+ ratified state.") -+ -+ - const: ziccif -+ description: -+ The standard Ziccif extension for main memory (cacheability and -+ coherence) instruction fetch atomicity, as ratified in RISC-V -+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to -+ ratified state.") -+ -+ - const: zicclsm -+ description: -+ The standard Zicclsm extension for main memory (cacheability and -+ coherence) must support misaligned loads and stores, as ratified -+ in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated -+ to ratified state.") -+ - - const: ziccrse - description: - The standard Ziccrse extension which provides forward progress -@@ -758,6 +785,18 @@ properties: - then: - contains: - const: b -+ # Za64rs and Ziccrse depend on Zalrsc or A -+ - if: -+ contains: -+ anyOf: -+ - const: za64rs -+ - const: ziccrse -+ then: -+ oneOf: -+ - contains: -+ const: zalrsc -+ - contains: -+ const: a - # Zcb depends on Zca - - if: - contains: -@@ -799,6 +838,16 @@ properties: - then: - contains: - const: f -+ # Ziccamoa depends on Zaamo or A -+ - if: -+ contains: -+ const: ziccamoa -+ then: -+ oneOf: -+ - contains: -+ const: zaamo -+ - contains: -+ const: a - # Zvfbfmin depends on V or Zve32f - - if: - contains: --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch b/SPECS/linux-lts-kmhv2/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch new file mode 100644 index 0000000000..7eef93f3d7 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch @@ -0,0 +1,868 @@ +From 815614b3265facda28aaa4572e120d8f049a9c79 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 07:18:59 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: sg2044: Add "b" ISA + extension + +"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs +(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency +checking rule is now enforced, which requires that when zba, zbb, and zbs +are all specified, "b" must be added as well. Failing to do this will +cause dtbs_check schema check warnings. + +According to uabi.rst, as a single-letter extension, "b" should be added +after "c" in canonical order. + +Update sg2044-cpus.dtsi to conform to this rule. + +Signed-off-by: Guodong Xu +Reviewed-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-3-254dd61cf947@riscstar.com +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +Signed-off-by: Chen Wang +(cherry picked from commit f16ae81b80ca4e721f4c4ed1f28390115f7721eb) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 256 ++++++++++---------- + 1 file changed, 128 insertions(+), 128 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +index 523799a1a8b8..3135409c2149 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +@@ -24,10 +24,10 @@ cpu0: cpu@0 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache0>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -60,10 +60,10 @@ cpu1: cpu@1 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache0>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -96,10 +96,10 @@ cpu2: cpu@2 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache0>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -132,10 +132,10 @@ cpu3: cpu@3 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache0>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -168,10 +168,10 @@ cpu4: cpu@4 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache1>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -204,10 +204,10 @@ cpu5: cpu@5 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache1>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -240,10 +240,10 @@ cpu6: cpu@6 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache1>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -276,10 +276,10 @@ cpu7: cpu@7 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache1>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -312,10 +312,10 @@ cpu8: cpu@8 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache2>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -348,10 +348,10 @@ cpu9: cpu@9 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache2>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -384,10 +384,10 @@ cpu10: cpu@10 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache2>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -420,10 +420,10 @@ cpu11: cpu@11 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache2>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -456,10 +456,10 @@ cpu12: cpu@12 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache3>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -492,10 +492,10 @@ cpu13: cpu@13 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache3>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -528,10 +528,10 @@ cpu14: cpu@14 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache3>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -564,10 +564,10 @@ cpu15: cpu@15 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache3>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -600,10 +600,10 @@ cpu16: cpu@16 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache4>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -636,10 +636,10 @@ cpu17: cpu@17 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache4>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -672,10 +672,10 @@ cpu18: cpu@18 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache4>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -708,10 +708,10 @@ cpu19: cpu@19 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache4>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -744,10 +744,10 @@ cpu20: cpu@20 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache5>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -780,10 +780,10 @@ cpu21: cpu@21 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache5>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -816,10 +816,10 @@ cpu22: cpu@22 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache5>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -852,10 +852,10 @@ cpu23: cpu@23 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache5>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -888,10 +888,10 @@ cpu24: cpu@24 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache6>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -924,10 +924,10 @@ cpu25: cpu@25 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache6>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -960,10 +960,10 @@ cpu26: cpu@26 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache6>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -996,10 +996,10 @@ cpu27: cpu@27 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache6>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1032,10 +1032,10 @@ cpu28: cpu@28 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache7>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1068,10 +1068,10 @@ cpu29: cpu@29 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache7>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1104,10 +1104,10 @@ cpu30: cpu@30 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache7>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1140,10 +1140,10 @@ cpu31: cpu@31 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache7>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1176,10 +1176,10 @@ cpu32: cpu@32 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache8>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1212,10 +1212,10 @@ cpu33: cpu@33 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache8>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1248,10 +1248,10 @@ cpu34: cpu@34 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache8>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1284,10 +1284,10 @@ cpu35: cpu@35 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache8>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1320,10 +1320,10 @@ cpu36: cpu@36 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache9>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1356,10 +1356,10 @@ cpu37: cpu@37 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache9>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1392,10 +1392,10 @@ cpu38: cpu@38 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache9>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1428,10 +1428,10 @@ cpu39: cpu@39 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache9>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1464,10 +1464,10 @@ cpu40: cpu@40 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache10>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1500,10 +1500,10 @@ cpu41: cpu@41 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache10>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1536,10 +1536,10 @@ cpu42: cpu@42 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache10>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1572,10 +1572,10 @@ cpu43: cpu@43 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache10>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1608,10 +1608,10 @@ cpu44: cpu@44 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache11>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1644,10 +1644,10 @@ cpu45: cpu@45 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache11>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1680,10 +1680,10 @@ cpu46: cpu@46 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache11>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1716,10 +1716,10 @@ cpu47: cpu@47 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache11>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1752,10 +1752,10 @@ cpu48: cpu@48 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache12>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1788,10 +1788,10 @@ cpu49: cpu@49 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache12>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1824,10 +1824,10 @@ cpu50: cpu@50 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache12>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1860,10 +1860,10 @@ cpu51: cpu@51 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache12>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1896,10 +1896,10 @@ cpu52: cpu@52 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache13>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1932,10 +1932,10 @@ cpu53: cpu@53 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache13>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1968,10 +1968,10 @@ cpu54: cpu@54 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache13>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2004,10 +2004,10 @@ cpu55: cpu@55 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache13>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2040,10 +2040,10 @@ cpu56: cpu@56 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache14>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2076,10 +2076,10 @@ cpu57: cpu@57 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache14>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2112,10 +2112,10 @@ cpu58: cpu@58 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache14>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2148,10 +2148,10 @@ cpu59: cpu@59 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache14>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2184,10 +2184,10 @@ cpu60: cpu@60 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache15>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2220,10 +2220,10 @@ cpu61: cpu@61 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache15>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2256,10 +2256,10 @@ cpu62: cpu@62 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache15>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2292,10 +2292,10 @@ cpu63: cpu@63 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache15>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0103-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch b/SPECS/linux-lts-kmhv2/0103-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch deleted file mode 100644 index 8f9f20a577..0000000000 --- a/SPECS/linux-lts-kmhv2/0103-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch +++ /dev/null @@ -1,89 +0,0 @@ -From cb41ade08efabd7980780c3df13115056b7d5bbe Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Sat, 10 Jan 2026 13:18:20 +0800 -Subject: [PATCH 103/467] UPSTREAM: dt-bindings: riscv: Add Ssccptr, - Sscounterenw, Sstvala, Sstvecd, Ssu64xl - -Add descriptions for five new extensions: Ssccptr, Sscounterenw, Sstvala, -Sstvecd, and Ssu64xl. These extensions are ratified in RISC-V Profiles -Version 1.0 (commit b1d806605f87 "Updated to ratified state."). - -They are introduced as new extension names for existing features and -regulate implementation details for RISC-V Profile compliance. According -to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, their -requirement status are: - - - Ssccptr: Mandatory in RVA20S64, RVA22S64, RVA23S64 - - Sscounterenw: Mandatory in RVA22S64, RVA23S64 - - Sstvala: Mandatory in RVA20S64, RVA22S64, RVA23S64 - - Sstvecd: Mandatory in RVA20S64, RVA22S64, RVA23S64 - - Ssu64xl: Optional in RVA20S64, RVA22S64; Mandatory in RVA23S64 - -Signed-off-by: Guodong Xu -Acked-by: Conor Dooley -Signed-off-by: Conor Dooley -(cherry picked from commit c712413333f8e19cc3de4e9cd1a3ed8a53169cc9) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/riscv/extensions.yaml | 32 +++++++++++++++++++ - 1 file changed, 32 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml -index bebbd7797d49..81cff2e5b06f 100644 ---- a/Documentation/devicetree/bindings/riscv/extensions.yaml -+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml -@@ -161,12 +161,26 @@ properties: - behavioural changes to interrupts as frozen at commit ccbddab - ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. - -+ - const: ssccptr -+ description: | -+ The standard Ssccptr extension for main memory (cacheability and -+ coherence) hardware page-table reads, as ratified in RISC-V -+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to -+ ratified state.") -+ - - const: sscofpmf - description: | - The standard Sscofpmf supervisor-level extension for count overflow - and mode-based filtering as ratified at commit 01d1df0 ("Add ability - to manually trigger workflow. (#2)") of riscv-count-overflow. - -+ - const: sscounterenw -+ description: | -+ The standard Sscounterenw extension for support writable enables -+ in scounteren for any supported counter, as ratified in RISC-V -+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to -+ ratified state.") -+ - - const: ssnpm - description: | - The standard Ssnpm extension for next-mode pointer masking as -@@ -179,6 +193,24 @@ properties: - ratified at commit 3f9ed34 ("Add ability to manually trigger - workflow. (#2)") of riscv-time-compare. - -+ - const: sstvala -+ description: | -+ The standard Sstvala extension for stval provides all needed values -+ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 -+ ("Updated to ratified state.") -+ -+ - const: sstvecd -+ description: | -+ The standard Sstvecd extension for stvec supports Direct mode as -+ ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 -+ ("Updated to ratified state.") -+ -+ - const: ssu64xl -+ description: | -+ The standard Ssu64xl extension for UXLEN=64 must be supported, as -+ ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 -+ ("Updated to ratified state.") -+ - - const: svade - description: | - The standard Svade supervisor-level extension for SW-managed PTE A/D --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch b/SPECS/linux-lts-kmhv2/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch new file mode 100644 index 0000000000..1f0aba5728 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch @@ -0,0 +1,130 @@ +From 039b44e9b855295ac8945486ffea47d65240d000 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 07:19:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1: Add "b" ISA + extension + +"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs +(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency +checking rule is now enforced, which requires that when zba, zbb, and zbs +are all specified, "b" must be added as well. Failing to do this will +cause dtbs_check schema check warnings. + +According to uabi.rst, as a single-letter extension, "b" should be added +after "c" in canonical order. + +Update k1.dtsi to conform to this rule. + +Signed-off-by: Guodong Xu +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-4-254dd61cf947@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 4168630825f95bf57729dad46d2a097096e73e4d) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 32 ++++++++++++++-------------- + 1 file changed, 16 insertions(+), 16 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index e22a5f030fa2..0a884947fda4 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -54,9 +54,9 @@ cpu_0: cpu@0 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <0>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -84,9 +84,9 @@ cpu_1: cpu@1 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <1>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -114,9 +114,9 @@ cpu_2: cpu@2 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <2>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -144,9 +144,9 @@ cpu_3: cpu@3 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <3>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -174,9 +174,9 @@ cpu_4: cpu@4 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <4>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -204,9 +204,9 @@ cpu_5: cpu@5 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <5>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -234,9 +234,9 @@ cpu_6: cpu@6 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <6>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -264,9 +264,9 @@ cpu_7: cpu@7 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <7>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0104-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch b/SPECS/linux-lts-kmhv2/0104-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch deleted file mode 100644 index 6613221727..0000000000 --- a/SPECS/linux-lts-kmhv2/0104-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 76d1441d889e836547a5be7be06231426dd50fc7 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Sat, 10 Jan 2026 13:18:21 +0800 -Subject: [PATCH 104/467] UPSTREAM: dt-bindings: riscv: Add Sha and its - comprised extensions - -Add descriptions for the Sha extension and the seven extensions it -comprises: Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, -and Ssstateen. - -Sha is ratified in the RVA23 Profiles Version 1.0 (commit 0273f3c921b6 -"rva23/rvb23 ratified") as a new profile-defined extension that captures -the full set of features that are mandated to be supported along with -the H extension. - -Extensions Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, -and Ssstateen are ratified in the RISC-V Profiles Version 1.0 (commit -b1d806605f87 "Updated to ratified state"). - -The requirement status for Sha and its comprised extension in RISC-V -Profiles are: - - Sha: Mandatory in RVA23S64 - - H: Optional in RVA22S64; Mandatory in RVA23S64 - - Shcounterenw: Optional in RVA22S64; Mandatory in RVA23S64 - - Shgatpa: Optional in RVA22S64; Mandatory in RVA23S64 - - Shtvala: Optional in RVA22S64; Mandatory in RVA23S64 - - Shvsatpa: Optional in RVA22S64; Mandatory in RVA23S64 - - Shvstvala: Optional in RVA22S64; Mandatory in RVA23S64 - - Shvstvecd: Optional in RVA22S64; Mandatory in RVA23S64 - - Ssstateen: Optional in RVA22S64; Mandatory in RVA23S64 - -Signed-off-by: Guodong Xu -Acked-by: Conor Dooley -Signed-off-by: Conor Dooley -(cherry picked from commit 89febd6a02768200fcfc86ee57f1ece632805bff) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/riscv/extensions.yaml | 57 +++++++++++++++++++ - 1 file changed, 57 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml -index 81cff2e5b06f..abe72eaa6c59 100644 ---- a/Documentation/devicetree/bindings/riscv/extensions.yaml -+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml -@@ -129,6 +129,57 @@ properties: - Document Version 20211203. - - # multi-letter extensions, sorted alphanumerically -+ - const: sha -+ description: | -+ The standard Sha extension for augmented hypervisor extension as -+ ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6 -+ ("rva23/rvb23 ratified"). -+ -+ Sha captures the full set of features that are mandated to be -+ supported along with the H extension. Sha comprises the following -+ extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, -+ Shvstvecd, and Ssstateen. -+ -+ - const: shcounterenw -+ description: | -+ The standard Shcounterenw extension for support writable enables -+ in hcounteren for any supported counter, as ratified in RISC-V -+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to -+ ratified state.") -+ -+ - const: shgatpa -+ description: | -+ The standard Shgatpa extension indicates that for each supported -+ virtual memory scheme SvNN supported in satp, the corresponding -+ hgatp SvNNx4 mode must be supported. The hgatp mode Bare must -+ also be supported. It is ratified in RISC-V Profiles Version 1.0, -+ with commit b1d806605f87 ("Updated to ratified state.") -+ -+ - const: shtvala -+ description: | -+ The standard Shtvala extension for htval be written with the -+ faulting guest physical address in all circumstances permitted by -+ the ISA. It is ratified in RISC-V Profiles Version 1.0, with -+ commit b1d806605f87 ("Updated to ratified state.") -+ -+ - const: shvsatpa -+ description: | -+ The standard Shvsatpa extension for vsatp supporting all translation -+ modes supported in satp, as ratified in RISC-V Profiles Version 1.0, -+ with commit b1d806605f87 ("Updated to ratified state.") -+ -+ - const: shvstvala -+ description: | -+ The standard Shvstvala extension for vstval provides all needed -+ values as ratified in RISC-V Profiles Version 1.0, with commit -+ b1d806605f87 ("Updated to ratified state.") -+ -+ - const: shvstvecd -+ description: | -+ The standard Shvstvecd extension for vstvec supporting Direct mode, -+ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 -+ ("Updated to ratified state.") -+ - - const: smaia - description: | - The standard Smaia supervisor-level extension for the advanced -@@ -187,6 +238,12 @@ properties: - ratified at commit d70011dde6c2 ("Update to ratified state") - of riscv-j-extension. - -+ - const: ssstateen -+ description: | -+ The standard Ssstateen extension for supervisor-mode view of the -+ state-enable extension, as ratified in RISC-V Profiles Version 1.0, -+ with commit b1d806605f87 ("Updated to ratified state.") -+ - - const: sstc - description: | - The standard Sstc supervisor-level extension for time compare as --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch b/SPECS/linux-lts-kmhv2/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch new file mode 100644 index 0000000000..8f2845d570 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch @@ -0,0 +1,48 @@ +From 3a49674fb8ec24236b9a789e322ccc05b66c4d65 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:40 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: add SpacemiT X100 CPU + compatible + +Add compatible string for the SpacemiT X100 core. [1] + +The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100 +supports the RISC-V vector and hypervisor extensions and all mandatory +extersions as required by the RVA23U64 and RVA23S64 profiles, per the +definition in 'RVA23 Profile, Version 1.0'. [2] + +From a microarchieture viewpoint, the X100 features a 4-issue +out-of-order pipeline. + +X100 is used in SpacemiT K3 SoC. + +Acked-by: Paul Walmsley +Acked-by: Krzysztof Kozlowski +Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] +Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2] +Reviewed-by: Yixun Lan +Reviewed-by: Heinrich Schuchardt +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-1-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 81a52103b90f5cddc41c34f633c014a956236abc) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml +index 153d0dac57fb..a86819565394 100644 +--- a/Documentation/devicetree/bindings/riscv/cpus.yaml ++++ b/Documentation/devicetree/bindings/riscv/cpus.yaml +@@ -60,6 +60,7 @@ properties: + - sifive,u7 + - sifive,u74 + - sifive,u74-mc ++ - spacemit,x100 + - spacemit,x60 + - thead,c906 + - thead,c908 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch b/SPECS/linux-lts-kmhv2/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch new file mode 100644 index 0000000000..10acec0266 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch @@ -0,0 +1,32 @@ +From 9e4be2e7c734325e83668eba93f9e2dbc1220efa Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:41 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: timer: add SpacemiT K3 CLINT + +Add compatible string for SpacemiT K3 CLINT. + +Acked-by: Conor Dooley +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-2-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 6cdeb30db4d8faf9f1fa7ab863d91d36a584716d) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml +index d85a1a088b35..63165939465a 100644 +--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml ++++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml +@@ -33,6 +33,7 @@ properties: + - eswin,eic7700-clint # ESWIN EIC7700 + - sifive,fu540-c000-clint # SiFive FU540 + - spacemit,k1-clint # SpacemiT K1 ++ - spacemit,k3-clint # SpacemiT K3 + - starfive,jh7100-clint # StarFive JH7100 + - starfive,jh7110-clint # StarFive JH7110 + - starfive,jh8100-clint # StarFive JH8100 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0105-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch b/SPECS/linux-lts-kmhv2/0105-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch deleted file mode 100644 index fb246009b4..0000000000 --- a/SPECS/linux-lts-kmhv2/0105-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch +++ /dev/null @@ -1,868 +0,0 @@ -From 0fd7679a286d8f4656076076047b3c5627b87815 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 07:18:59 +0800 -Subject: [PATCH 105/467] UPSTREAM: riscv: dts: sophgo: sg2044: Add "b" ISA - extension - -"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs -(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency -checking rule is now enforced, which requires that when zba, zbb, and zbs -are all specified, "b" must be added as well. Failing to do this will -cause dtbs_check schema check warnings. - -According to uabi.rst, as a single-letter extension, "b" should be added -after "c" in canonical order. - -Update sg2044-cpus.dtsi to conform to this rule. - -Signed-off-by: Guodong Xu -Reviewed-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-3-254dd61cf947@riscstar.com -Signed-off-by: Inochi Amaoto -Signed-off-by: Chen Wang -Signed-off-by: Chen Wang -(cherry picked from commit f16ae81b80ca4e721f4c4ed1f28390115f7721eb) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 256 ++++++++++---------- - 1 file changed, 128 insertions(+), 128 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -index 523799a1a8b8..3135409c2149 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -@@ -24,10 +24,10 @@ cpu0: cpu@0 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache0>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -60,10 +60,10 @@ cpu1: cpu@1 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache0>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -96,10 +96,10 @@ cpu2: cpu@2 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache0>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -132,10 +132,10 @@ cpu3: cpu@3 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache0>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -168,10 +168,10 @@ cpu4: cpu@4 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache1>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -204,10 +204,10 @@ cpu5: cpu@5 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache1>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -240,10 +240,10 @@ cpu6: cpu@6 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache1>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -276,10 +276,10 @@ cpu7: cpu@7 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache1>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -312,10 +312,10 @@ cpu8: cpu@8 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache2>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -348,10 +348,10 @@ cpu9: cpu@9 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache2>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -384,10 +384,10 @@ cpu10: cpu@10 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache2>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -420,10 +420,10 @@ cpu11: cpu@11 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache2>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -456,10 +456,10 @@ cpu12: cpu@12 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache3>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -492,10 +492,10 @@ cpu13: cpu@13 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache3>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -528,10 +528,10 @@ cpu14: cpu@14 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache3>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -564,10 +564,10 @@ cpu15: cpu@15 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache3>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -600,10 +600,10 @@ cpu16: cpu@16 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache4>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -636,10 +636,10 @@ cpu17: cpu@17 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache4>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -672,10 +672,10 @@ cpu18: cpu@18 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache4>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -708,10 +708,10 @@ cpu19: cpu@19 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache4>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -744,10 +744,10 @@ cpu20: cpu@20 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache5>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -780,10 +780,10 @@ cpu21: cpu@21 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache5>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -816,10 +816,10 @@ cpu22: cpu@22 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache5>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -852,10 +852,10 @@ cpu23: cpu@23 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache5>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -888,10 +888,10 @@ cpu24: cpu@24 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache6>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -924,10 +924,10 @@ cpu25: cpu@25 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache6>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -960,10 +960,10 @@ cpu26: cpu@26 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache6>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -996,10 +996,10 @@ cpu27: cpu@27 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache6>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1032,10 +1032,10 @@ cpu28: cpu@28 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache7>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1068,10 +1068,10 @@ cpu29: cpu@29 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache7>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1104,10 +1104,10 @@ cpu30: cpu@30 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache7>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1140,10 +1140,10 @@ cpu31: cpu@31 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache7>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1176,10 +1176,10 @@ cpu32: cpu@32 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache8>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1212,10 +1212,10 @@ cpu33: cpu@33 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache8>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1248,10 +1248,10 @@ cpu34: cpu@34 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache8>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1284,10 +1284,10 @@ cpu35: cpu@35 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache8>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1320,10 +1320,10 @@ cpu36: cpu@36 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache9>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1356,10 +1356,10 @@ cpu37: cpu@37 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache9>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1392,10 +1392,10 @@ cpu38: cpu@38 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache9>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1428,10 +1428,10 @@ cpu39: cpu@39 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache9>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1464,10 +1464,10 @@ cpu40: cpu@40 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache10>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1500,10 +1500,10 @@ cpu41: cpu@41 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache10>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1536,10 +1536,10 @@ cpu42: cpu@42 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache10>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1572,10 +1572,10 @@ cpu43: cpu@43 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache10>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1608,10 +1608,10 @@ cpu44: cpu@44 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache11>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1644,10 +1644,10 @@ cpu45: cpu@45 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache11>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1680,10 +1680,10 @@ cpu46: cpu@46 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache11>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1716,10 +1716,10 @@ cpu47: cpu@47 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache11>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1752,10 +1752,10 @@ cpu48: cpu@48 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache12>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1788,10 +1788,10 @@ cpu49: cpu@49 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache12>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1824,10 +1824,10 @@ cpu50: cpu@50 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache12>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1860,10 +1860,10 @@ cpu51: cpu@51 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache12>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1896,10 +1896,10 @@ cpu52: cpu@52 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache13>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1932,10 +1932,10 @@ cpu53: cpu@53 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache13>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1968,10 +1968,10 @@ cpu54: cpu@54 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache13>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2004,10 +2004,10 @@ cpu55: cpu@55 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache13>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2040,10 +2040,10 @@ cpu56: cpu@56 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache14>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2076,10 +2076,10 @@ cpu57: cpu@57 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache14>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2112,10 +2112,10 @@ cpu58: cpu@58 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache14>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2148,10 +2148,10 @@ cpu59: cpu@59 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache14>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2184,10 +2184,10 @@ cpu60: cpu@60 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache15>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2220,10 +2220,10 @@ cpu61: cpu@61 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache15>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2256,10 +2256,10 @@ cpu62: cpu@62 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache15>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2292,10 +2292,10 @@ cpu63: cpu@63 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache15>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch b/SPECS/linux-lts-kmhv2/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch new file mode 100644 index 0000000000..f8b908b4e1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch @@ -0,0 +1,33 @@ +From 57ea95edd2da52d808cbd5a6d874d1cb368dea05 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:42 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: add + SpacemiT K3 APLIC + +Add compatible string for SpacemiT K3 APLIC. + +Acked-by: Conor Dooley +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-3-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 60490ca6d54b6f0a00223a4fe59bb180bb1538bf) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +index bef00521d5da..0718071444d2 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml ++++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +@@ -28,6 +28,7 @@ properties: + items: + - enum: + - qemu,aplic ++ - spacemit,k3-aplic + - const: riscv,aplic + + reg: +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0106-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch b/SPECS/linux-lts-kmhv2/0106-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch deleted file mode 100644 index 8190f7f0ca..0000000000 --- a/SPECS/linux-lts-kmhv2/0106-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch +++ /dev/null @@ -1,130 +0,0 @@ -From adaead5f6b5ea0e1fd34595fb5fe60ad48dd0471 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 07:19:00 +0800 -Subject: [PATCH 106/467] UPSTREAM: riscv: dts: spacemit: k1: Add "b" ISA - extension - -"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs -(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency -checking rule is now enforced, which requires that when zba, zbb, and zbs -are all specified, "b" must be added as well. Failing to do this will -cause dtbs_check schema check warnings. - -According to uabi.rst, as a single-letter extension, "b" should be added -after "c" in canonical order. - -Update k1.dtsi to conform to this rule. - -Signed-off-by: Guodong Xu -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-4-254dd61cf947@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 4168630825f95bf57729dad46d2a097096e73e4d) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 32 ++++++++++++++-------------- - 1 file changed, 16 insertions(+), 16 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index e22a5f030fa2..0a884947fda4 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -54,9 +54,9 @@ cpu_0: cpu@0 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <0>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -84,9 +84,9 @@ cpu_1: cpu@1 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <1>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -114,9 +114,9 @@ cpu_2: cpu@2 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <2>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -144,9 +144,9 @@ cpu_3: cpu@3 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <3>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -174,9 +174,9 @@ cpu_4: cpu@4 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <4>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -204,9 +204,9 @@ cpu_5: cpu@5 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <5>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -234,9 +234,9 @@ cpu_6: cpu@6 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <6>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -264,9 +264,9 @@ cpu_7: cpu@7 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <7>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch b/SPECS/linux-lts-kmhv2/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch new file mode 100644 index 0000000000..9699a897cf --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch @@ -0,0 +1,33 @@ +From 7d7a00a794501c279b94f46e44c33a60cc0ecf71 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:43 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: add + SpacemiT K3 IMSIC + +Add compatible string for SpacemiT K3 IMSIC. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-4-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit a716729a3ce1055efab477030235777d2be0852b) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/interrupt-controller/riscv,imsics.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml +index c23b5c09fdb9..feec122bddde 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml ++++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml +@@ -48,6 +48,7 @@ properties: + items: + - enum: + - qemu,imsics ++ - spacemit,k3-imsics + - const: riscv,imsics + + reg: +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0107-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch b/SPECS/linux-lts-kmhv2/0107-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch deleted file mode 100644 index 809cf69223..0000000000 --- a/SPECS/linux-lts-kmhv2/0107-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 8e1a61160ad52213d592d47106334dc60232a82b Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:40 +0800 -Subject: [PATCH 107/467] UPSTREAM: dt-bindings: riscv: add SpacemiT X100 CPU - compatible - -Add compatible string for the SpacemiT X100 core. [1] - -The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100 -supports the RISC-V vector and hypervisor extensions and all mandatory -extersions as required by the RVA23U64 and RVA23S64 profiles, per the -definition in 'RVA23 Profile, Version 1.0'. [2] - -From a microarchieture viewpoint, the X100 features a 4-issue -out-of-order pipeline. - -X100 is used in SpacemiT K3 SoC. - -Acked-by: Paul Walmsley -Acked-by: Krzysztof Kozlowski -Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] -Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2] -Reviewed-by: Yixun Lan -Reviewed-by: Heinrich Schuchardt -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-1-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 81a52103b90f5cddc41c34f633c014a956236abc) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml -index 153d0dac57fb..a86819565394 100644 ---- a/Documentation/devicetree/bindings/riscv/cpus.yaml -+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml -@@ -60,6 +60,7 @@ properties: - - sifive,u7 - - sifive,u74 - - sifive,u74-mc -+ - spacemit,x100 - - spacemit,x60 - - thead,c906 - - thead,c908 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch b/SPECS/linux-lts-kmhv2/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch new file mode 100644 index 0000000000..0f66a78fa3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch @@ -0,0 +1,46 @@ +From 90385ee4dee92d3b318cb4a03b5de245c87b06f2 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:44 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: spacemit: add K3 and + Pico-ITX board bindings + +Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX +which is a 2.5-inch single-board computer. + +Acked-by: Conor Dooley +Reviewed-by: Yixun Lan +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-5-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 7cb5fafc180f6e188af7943d6b162051f22490fc) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml +index c56b62a6299a..eca403a8e49e 100644 +--- a/Documentation/devicetree/bindings/riscv/spacemit.yaml ++++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml +@@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# + title: SpacemiT SoC-based boards + + maintainers: ++ - Guodong Xu + - Yangyu Chen + - Yixun Lan + +@@ -24,6 +25,10 @@ properties: + - milkv,jupiter + - xunlong,orangepi-rv2 + - const: spacemit,k1 ++ - items: ++ - enum: ++ - spacemit,k3-pico-itx ++ - const: spacemit,k3 + + additionalProperties: true + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0108-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch b/SPECS/linux-lts-kmhv2/0108-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch deleted file mode 100644 index 8b1c7bc20d..0000000000 --- a/SPECS/linux-lts-kmhv2/0108-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 7095ed807e459baec17231d727e1e5399c4753c7 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:41 +0800 -Subject: [PATCH 108/467] UPSTREAM: dt-bindings: timer: add SpacemiT K3 CLINT - -Add compatible string for SpacemiT K3 CLINT. - -Acked-by: Conor Dooley -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-2-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 6cdeb30db4d8faf9f1fa7ab863d91d36a584716d) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml -index d85a1a088b35..63165939465a 100644 ---- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml -+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml -@@ -33,6 +33,7 @@ properties: - - eswin,eic7700-clint # ESWIN EIC7700 - - sifive,fu540-c000-clint # SiFive FU540 - - spacemit,k1-clint # SpacemiT K1 -+ - spacemit,k3-clint # SpacemiT K3 - - starfive,jh7100-clint # StarFive JH7100 - - starfive,jh7110-clint # StarFive JH7110 - - starfive,jh8100-clint # StarFive JH8100 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0109-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch b/SPECS/linux-lts-kmhv2/0109-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch deleted file mode 100644 index 3257d1e8d2..0000000000 --- a/SPECS/linux-lts-kmhv2/0109-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch +++ /dev/null @@ -1,33 +0,0 @@ -From a5bf205e23df3a195f132f1b23867635454771e9 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:42 +0800 -Subject: [PATCH 109/467] UPSTREAM: dt-bindings: interrupt-controller: add - SpacemiT K3 APLIC - -Add compatible string for SpacemiT K3 APLIC. - -Acked-by: Conor Dooley -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-3-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 60490ca6d54b6f0a00223a4fe59bb180bb1538bf) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml -index bef00521d5da..0718071444d2 100644 ---- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml -+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml -@@ -28,6 +28,7 @@ properties: - items: - - enum: - - qemu,aplic -+ - spacemit,k3-aplic - - const: riscv,aplic - - reg: --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch b/SPECS/linux-lts-kmhv2/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch new file mode 100644 index 0000000000..f038974db6 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch @@ -0,0 +1,608 @@ +From b4a0b52d7cdbe329b44301f63847faf1c8631060 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:45 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add initial support for + K3 SoC + +SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant. +Add nodes of uarts, timer and interrupt-controllers. Also add M-mode +APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware +topology and ready for potential firmware usage. + +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-6-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 56f37e391a626f964615ee5939710eff212b621f) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 578 +++++++++++++++++++++++++++ + 1 file changed, 578 insertions(+) + create mode 100644 arch/riscv/boot/dts/spacemit/k3.dtsi + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +new file mode 100644 +index 000000000000..b69cf81b5d55 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -0,0 +1,578 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ * Copyright (c) 2026 Guodong Xu ++ */ ++ ++#include ++ ++/dts-v1/; ++ ++/ { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ model = "SpacemiT K3"; ++ compatible = "spacemit,k3"; ++ ++ cpus: cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ timebase-frequency = <24000000>; ++ ++ cpu_0: cpu@0 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <0>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache0>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu0_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_1: cpu@1 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <1>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache0>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu1_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_2: cpu@2 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <2>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache0>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu2_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_3: cpu@3 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <3>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache0>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu3_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_4: cpu@4 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <4>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache1>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu4_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_5: cpu@5 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <5>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache1>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu5_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_6: cpu@6 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <6>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache1>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu6_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_7: cpu@7 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <7>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache1>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu7_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ l2_cache0: cache-controller-0 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <4194304>; ++ cache-sets = <4096>; ++ cache-unified; ++ }; ++ ++ l2_cache1: cache-controller-1 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <4194304>; ++ cache-sets = <4096>; ++ cache-unified; ++ }; ++ ++ cpu-map { ++ cluster0 { ++ core0 { ++ cpu = <&cpu_0>; ++ }; ++ core1 { ++ cpu = <&cpu_1>; ++ }; ++ core2 { ++ cpu = <&cpu_2>; ++ }; ++ core3 { ++ cpu = <&cpu_3>; ++ }; ++ }; ++ ++ cluster1 { ++ core0 { ++ cpu = <&cpu_4>; ++ }; ++ core1 { ++ cpu = <&cpu_5>; ++ }; ++ core2 { ++ cpu = <&cpu_6>; ++ }; ++ core3 { ++ cpu = <&cpu_7>; ++ }; ++ }; ++ }; ++ }; ++ ++ soc: soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&saplic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ dma-noncoherent; ++ ranges; ++ ++ uart0: serial@d4017000 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@d4017100 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017100 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@d4017200 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017200 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@d4017300 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017300 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart5: serial@d4017400 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017400 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart6: serial@d4017500 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017500 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart7: serial@d4017600 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017600 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart8: serial@d4017700 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017700 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart9: serial@d4017800 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017800 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart10: serial@d401f000 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd401f000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ simsic: interrupt-controller@e0400000 { ++ compatible = "spacemit,k3-imsics", "riscv,imsics"; ++ reg = <0x0 0xe0400000 0x0 0x200000>; ++ #interrupt-cells = <0>; ++ #msi-cells = <0>; ++ interrupt-controller; ++ interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, ++ <&cpu2_intc 9>, <&cpu3_intc 9>, ++ <&cpu4_intc 9>, <&cpu5_intc 9>, ++ <&cpu6_intc 9>, <&cpu7_intc 9>; ++ msi-controller; ++ riscv,guest-index-bits = <6>; ++ riscv,hart-index-bits = <4>; ++ riscv,num-guest-ids = <511>; ++ riscv,num-ids = <511>; ++ }; ++ ++ saplic: interrupt-controller@e0804000 { ++ compatible = "spacemit,k3-aplic", "riscv,aplic"; ++ reg = <0x0 0xe0804000 0x0 0x4000>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ msi-parent = <&simsic>; ++ riscv,num-sources = <512>; ++ }; ++ ++ clint: timer@e081c000 { ++ compatible = "spacemit,k3-clint", "sifive,clint0"; ++ reg = <0x0 0xe081c000 0x0 0x4000>; ++ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, ++ <&cpu1_intc 3>, <&cpu1_intc 7>, ++ <&cpu2_intc 3>, <&cpu2_intc 7>, ++ <&cpu3_intc 3>, <&cpu3_intc 7>, ++ <&cpu4_intc 3>, <&cpu4_intc 7>, ++ <&cpu5_intc 3>, <&cpu5_intc 7>, ++ <&cpu6_intc 3>, <&cpu6_intc 7>, ++ <&cpu7_intc 3>, <&cpu7_intc 7>; ++ }; ++ ++ mimsic: interrupt-controller@f1000000 { ++ compatible = "spacemit,k3-imsics", "riscv,imsics"; ++ reg = <0x0 0xf1000000 0x0 0x10000>; ++ #interrupt-cells = <0>; ++ #msi-cells = <0>; ++ interrupt-controller; ++ interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, ++ <&cpu2_intc 11>, <&cpu3_intc 11>, ++ <&cpu4_intc 11>, <&cpu5_intc 11>, ++ <&cpu6_intc 11>, <&cpu7_intc 11>; ++ msi-controller; ++ riscv,guest-index-bits = <6>; ++ riscv,hart-index-bits = <4>; ++ riscv,num-guest-ids = <511>; ++ riscv,num-ids = <511>; ++ status = "reserved"; ++ }; ++ ++ maplic: interrupt-controller@f1800000 { ++ compatible = "spacemit,k3-aplic", "riscv,aplic"; ++ reg = <0x0 0xf1800000 0x0 0x4000>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ msi-parent = <&mimsic>; ++ riscv,children = <&saplic>; ++ riscv,delegation = <&saplic 1 512>; ++ riscv,num-sources = <512>; ++ status = "reserved"; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0110-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch b/SPECS/linux-lts-kmhv2/0110-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch deleted file mode 100644 index 1568e712e5..0000000000 --- a/SPECS/linux-lts-kmhv2/0110-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch +++ /dev/null @@ -1,33 +0,0 @@ -From d63371e2a5c8738aa915c7d56267e1a929c22dba Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:43 +0800 -Subject: [PATCH 110/467] UPSTREAM: dt-bindings: interrupt-controller: add - SpacemiT K3 IMSIC - -Add compatible string for SpacemiT K3 IMSIC. - -Acked-by: Krzysztof Kozlowski -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-4-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit a716729a3ce1055efab477030235777d2be0852b) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/interrupt-controller/riscv,imsics.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml -index c23b5c09fdb9..feec122bddde 100644 ---- a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml -+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml -@@ -48,6 +48,7 @@ properties: - items: - - enum: - - qemu,imsics -+ - spacemit,k3-imsics - - const: riscv,imsics - - reg: --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch b/SPECS/linux-lts-kmhv2/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch new file mode 100644 index 0000000000..f252517e9d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch @@ -0,0 +1,70 @@ +From 377151dae3f25558fd27556e52c4f0854c988c8b Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:46 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add K3 Pico-ITX board + support + +K3 Pico-ITX is a 2.5-inch single-board computer equipted with a SpacemiT +K3 SoC. + +This minimal device tree enables booting into a serial console with UART +output. + +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-7-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 7a61318049861b777f098d7148d892d7dc79b010) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/Makefile | 1 + + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++++++++++++++++++ + 2 files changed, 30 insertions(+) + create mode 100644 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts + +diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile +index 95889e7269d1..7e2b87702571 100644 +--- a/arch/riscv/boot/dts/spacemit/Makefile ++++ b/arch/riscv/boot/dts/spacemit/Makefile +@@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb ++dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +new file mode 100644 +index 000000000000..b691304d4b74 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ * Copyright (c) 2026 Guodong Xu ++ */ ++ ++#include "k3.dtsi" ++ ++/ { ++ model = "SpacemiT K3 Pico-ITX"; ++ compatible = "spacemit,k3-pico-itx", "spacemit,k3"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0"; ++ }; ++ ++ memory@100000000 { ++ device_type = "memory"; ++ reg = <0x1 0x00000000 0x4 0x00000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch b/SPECS/linux-lts-kmhv2/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch new file mode 100644 index 0000000000..ec9ea29ffd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch @@ -0,0 +1,53 @@ +From 2503ec0c2acbeba44796cf9a39cd65176b1b41b8 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 19 Dec 2025 09:28:18 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: Hide common clock driver from + user controller + +Since the common clock driver is only a dependency for other spacemit +clock driver, it should not be enabled individually, so hide this in +the Kconfig UI and let other spacemit clock driver select it. + +Signed-off-by: Inochi Amaoto +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20251219012819.440972-3-inochiama@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 99735a742f7e9a3e7f4cb6c58edf1b38101e7657) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/Kconfig | 14 ++++++-------- + 1 file changed, 6 insertions(+), 8 deletions(-) + +diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig +index 3854f6ae6d0e..3351e8bc801d 100644 +--- a/drivers/clk/spacemit/Kconfig ++++ b/drivers/clk/spacemit/Kconfig +@@ -1,19 +1,17 @@ + # SPDX-License-Identifier: GPL-2.0-only + +-config SPACEMIT_CCU +- tristate "Clock support for SpacemiT SoCs" ++menu "Clock support for SpacemiT platforms" + depends on ARCH_SPACEMIT || COMPILE_TEST ++ ++config SPACEMIT_CCU ++ tristate + select AUXILIARY_BUS + select MFD_SYSCON +- help +- Say Y to enable clock controller unit support for SpacemiT SoCs. +- +-if SPACEMIT_CCU + + config SPACEMIT_K1_CCU + tristate "Support for SpacemiT K1 SoC" +- depends on ARCH_SPACEMIT || COMPILE_TEST ++ select SPACEMIT_CCU + help + Support for clock controller unit in SpacemiT K1 SoC. + +-endif ++endmenu +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0111-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch b/SPECS/linux-lts-kmhv2/0111-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch deleted file mode 100644 index 38620c5098..0000000000 --- a/SPECS/linux-lts-kmhv2/0111-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch +++ /dev/null @@ -1,46 +0,0 @@ -From f7c8a235eb0f117b1a38380fced43d1f12ce6a90 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:44 +0800 -Subject: [PATCH 111/467] UPSTREAM: dt-bindings: riscv: spacemit: add K3 and - Pico-ITX board bindings - -Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX -which is a 2.5-inch single-board computer. - -Acked-by: Conor Dooley -Reviewed-by: Yixun Lan -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-5-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 7cb5fafc180f6e188af7943d6b162051f22490fc) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml -index c56b62a6299a..eca403a8e49e 100644 ---- a/Documentation/devicetree/bindings/riscv/spacemit.yaml -+++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml -@@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# - title: SpacemiT SoC-based boards - - maintainers: -+ - Guodong Xu - - Yangyu Chen - - Yixun Lan - -@@ -24,6 +25,10 @@ properties: - - milkv,jupiter - - xunlong,orangepi-rv2 - - const: spacemit,k1 -+ - items: -+ - enum: -+ - spacemit,k3-pico-itx -+ - const: spacemit,k3 - - additionalProperties: true - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch b/SPECS/linux-lts-kmhv2/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch new file mode 100644 index 0000000000..02f0837e38 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch @@ -0,0 +1,73 @@ +From 5fd55e32b05d7b1c89471933925ea500ab96dc8f Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 19 Dec 2025 21:52:08 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: prepare common ccu header + +In order to prepare adding clock driver for new K3 SoC, extract generic +code to a separate common ccu header file, so they are not defined +in K1 SoC-specific file, and then can be shared by all clock drivers. + +Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-1-badf635993d3@gentoo.org +Reviewed-by: Alex Elder +Signed-off-by: Yixun Lan +(cherry picked from commit 2b7a02c322922a37cc5fc15d055b794cc2193062) +Signed-off-by: Han Gao +--- + include/soc/spacemit/ccu.h | 21 +++++++++++++++++++++ + include/soc/spacemit/k1-syscon.h | 12 +----------- + 2 files changed, 22 insertions(+), 11 deletions(-) + create mode 100644 include/soc/spacemit/ccu.h + +diff --git a/include/soc/spacemit/ccu.h b/include/soc/spacemit/ccu.h +new file mode 100644 +index 000000000000..84dcdecccc05 +--- /dev/null ++++ b/include/soc/spacemit/ccu.h +@@ -0,0 +1,21 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __SOC_SPACEMIT_CCU_H__ ++#define __SOC_SPACEMIT_CCU_H__ ++ ++#include ++#include ++ ++/* Auxiliary device used to represent a CCU reset controller */ ++struct spacemit_ccu_adev { ++ struct auxiliary_device adev; ++ struct regmap *regmap; ++}; ++ ++static inline struct spacemit_ccu_adev * ++to_spacemit_ccu_adev(struct auxiliary_device *adev) ++{ ++ return container_of(adev, struct spacemit_ccu_adev, adev); ++} ++ ++#endif /* __SOC_SPACEMIT_CCU_H__ */ +diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-syscon.h +index 354751562c55..0be7a2e8d445 100644 +--- a/include/soc/spacemit/k1-syscon.h ++++ b/include/soc/spacemit/k1-syscon.h +@@ -5,17 +5,7 @@ + #ifndef __SOC_K1_SYSCON_H__ + #define __SOC_K1_SYSCON_H__ + +-/* Auxiliary device used to represent a CCU reset controller */ +-struct spacemit_ccu_adev { +- struct auxiliary_device adev; +- struct regmap *regmap; +-}; +- +-static inline struct spacemit_ccu_adev * +-to_spacemit_ccu_adev(struct auxiliary_device *adev) +-{ +- return container_of(adev, struct spacemit_ccu_adev, adev); +-} ++#include "ccu.h" + + /* APBS register offset */ + #define APBS_PLL1_SWCR1 0x100 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0112-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch b/SPECS/linux-lts-kmhv2/0112-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch deleted file mode 100644 index 238312a7d2..0000000000 --- a/SPECS/linux-lts-kmhv2/0112-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch +++ /dev/null @@ -1,608 +0,0 @@ -From fe51e7041e2aff1c2d9c8aa9847ccab8ca54a056 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:45 +0800 -Subject: [PATCH 112/467] UPSTREAM: riscv: dts: spacemit: add initial support - for K3 SoC - -SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant. -Add nodes of uarts, timer and interrupt-controllers. Also add M-mode -APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware -topology and ready for potential firmware usage. - -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-6-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 56f37e391a626f964615ee5939710eff212b621f) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 578 +++++++++++++++++++++++++++ - 1 file changed, 578 insertions(+) - create mode 100644 arch/riscv/boot/dts/spacemit/k3.dtsi - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -new file mode 100644 -index 000000000000..b69cf81b5d55 ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -0,0 +1,578 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd -+ * Copyright (c) 2026 Guodong Xu -+ */ -+ -+#include -+ -+/dts-v1/; -+ -+/ { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ model = "SpacemiT K3"; -+ compatible = "spacemit,k3"; -+ -+ cpus: cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ timebase-frequency = <24000000>; -+ -+ cpu_0: cpu@0 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <0>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache0>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu0_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_1: cpu@1 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <1>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache0>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu1_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_2: cpu@2 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <2>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache0>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu2_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_3: cpu@3 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <3>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache0>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu3_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_4: cpu@4 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <4>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache1>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu4_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_5: cpu@5 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <5>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache1>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu5_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_6: cpu@6 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <6>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache1>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu6_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_7: cpu@7 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <7>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache1>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu7_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ l2_cache0: cache-controller-0 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <4194304>; -+ cache-sets = <4096>; -+ cache-unified; -+ }; -+ -+ l2_cache1: cache-controller-1 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <4194304>; -+ cache-sets = <4096>; -+ cache-unified; -+ }; -+ -+ cpu-map { -+ cluster0 { -+ core0 { -+ cpu = <&cpu_0>; -+ }; -+ core1 { -+ cpu = <&cpu_1>; -+ }; -+ core2 { -+ cpu = <&cpu_2>; -+ }; -+ core3 { -+ cpu = <&cpu_3>; -+ }; -+ }; -+ -+ cluster1 { -+ core0 { -+ cpu = <&cpu_4>; -+ }; -+ core1 { -+ cpu = <&cpu_5>; -+ }; -+ core2 { -+ cpu = <&cpu_6>; -+ }; -+ core3 { -+ cpu = <&cpu_7>; -+ }; -+ }; -+ }; -+ }; -+ -+ soc: soc { -+ compatible = "simple-bus"; -+ interrupt-parent = <&saplic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ dma-noncoherent; -+ ranges; -+ -+ uart0: serial@d4017000 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017000 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@d4017100 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017100 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart3: serial@d4017200 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017200 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart4: serial@d4017300 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017300 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart5: serial@d4017400 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017400 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart6: serial@d4017500 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017500 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart7: serial@d4017600 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017600 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart8: serial@d4017700 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017700 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart9: serial@d4017800 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017800 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart10: serial@d401f000 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd401f000 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ simsic: interrupt-controller@e0400000 { -+ compatible = "spacemit,k3-imsics", "riscv,imsics"; -+ reg = <0x0 0xe0400000 0x0 0x200000>; -+ #interrupt-cells = <0>; -+ #msi-cells = <0>; -+ interrupt-controller; -+ interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, -+ <&cpu2_intc 9>, <&cpu3_intc 9>, -+ <&cpu4_intc 9>, <&cpu5_intc 9>, -+ <&cpu6_intc 9>, <&cpu7_intc 9>; -+ msi-controller; -+ riscv,guest-index-bits = <6>; -+ riscv,hart-index-bits = <4>; -+ riscv,num-guest-ids = <511>; -+ riscv,num-ids = <511>; -+ }; -+ -+ saplic: interrupt-controller@e0804000 { -+ compatible = "spacemit,k3-aplic", "riscv,aplic"; -+ reg = <0x0 0xe0804000 0x0 0x4000>; -+ #interrupt-cells = <2>; -+ interrupt-controller; -+ msi-parent = <&simsic>; -+ riscv,num-sources = <512>; -+ }; -+ -+ clint: timer@e081c000 { -+ compatible = "spacemit,k3-clint", "sifive,clint0"; -+ reg = <0x0 0xe081c000 0x0 0x4000>; -+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, -+ <&cpu1_intc 3>, <&cpu1_intc 7>, -+ <&cpu2_intc 3>, <&cpu2_intc 7>, -+ <&cpu3_intc 3>, <&cpu3_intc 7>, -+ <&cpu4_intc 3>, <&cpu4_intc 7>, -+ <&cpu5_intc 3>, <&cpu5_intc 7>, -+ <&cpu6_intc 3>, <&cpu6_intc 7>, -+ <&cpu7_intc 3>, <&cpu7_intc 7>; -+ }; -+ -+ mimsic: interrupt-controller@f1000000 { -+ compatible = "spacemit,k3-imsics", "riscv,imsics"; -+ reg = <0x0 0xf1000000 0x0 0x10000>; -+ #interrupt-cells = <0>; -+ #msi-cells = <0>; -+ interrupt-controller; -+ interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, -+ <&cpu2_intc 11>, <&cpu3_intc 11>, -+ <&cpu4_intc 11>, <&cpu5_intc 11>, -+ <&cpu6_intc 11>, <&cpu7_intc 11>; -+ msi-controller; -+ riscv,guest-index-bits = <6>; -+ riscv,hart-index-bits = <4>; -+ riscv,num-guest-ids = <511>; -+ riscv,num-ids = <511>; -+ status = "reserved"; -+ }; -+ -+ maplic: interrupt-controller@f1800000 { -+ compatible = "spacemit,k3-aplic", "riscv,aplic"; -+ reg = <0x0 0xf1800000 0x0 0x4000>; -+ #interrupt-cells = <2>; -+ interrupt-controller; -+ msi-parent = <&mimsic>; -+ riscv,children = <&saplic>; -+ riscv,delegation = <&saplic 1 512>; -+ riscv,num-sources = <512>; -+ status = "reserved"; -+ }; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch b/SPECS/linux-lts-kmhv2/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch new file mode 100644 index 0000000000..07bf26b3d3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch @@ -0,0 +1,463 @@ +From 882ae01390f0d71acbaa666ad62660f1690558cb Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 19 Dec 2025 08:07:23 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: extract common ccu functions + +Refactor the probe function of SpacemiT's clock, and extract a common ccu +file, so new clock driver added in the future can share the same code, +which would lower the burden of maintenance. Since this commit changes the +module name from spacemit_ccu_k1 to spacemit_ccu where the auxiliary device +registered, the auxiliary device id need to be adjusted. Idea of the patch +comes from the review of K3 clock driver, please refer to this disucssion[1] +for more detail. + +This change will introduce a runtime break to reset driver, and will be +fixed in follow-up commit: +ecff77f7c041 ("reset: spacemit: fix auxiliary device id") + +Link: https://lore.kernel.org/all/aTo8sCPpVM1o9PKX@pie/ [1] +Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-2-badf635993d3@gentoo.org +Suggested-by: Yao Zi +Reviewed-by: Alex Elder +Signed-off-by: Yixun Lan +(cherry picked from commit 99669468d24ce21be12f3751e7381c47ab2c9ecd) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k1.c | 179 +----------------------------- + drivers/clk/spacemit/ccu_common.c | 171 ++++++++++++++++++++++++++++ + drivers/clk/spacemit/ccu_common.h | 10 ++ + 3 files changed, 186 insertions(+), 174 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c +index 01d9485b615d..02c792a73759 100644 +--- a/drivers/clk/spacemit/ccu-k1.c ++++ b/drivers/clk/spacemit/ccu-k1.c +@@ -5,15 +5,10 @@ + */ + + #include +-#include + #include +-#include +-#include +-#include + #include + #include + #include +-#include + #include + + #include "ccu_common.h" +@@ -23,14 +18,6 @@ + + #include + +-struct spacemit_ccu_data { +- const char *reset_name; +- struct clk_hw **hws; +- size_t num; +-}; +- +-static DEFINE_IDA(auxiliary_ids); +- + /* APBS clocks start, APBS region contains and only contains all PLL clocks */ + + /* +@@ -1001,167 +988,6 @@ static const struct spacemit_ccu_data k1_ccu_apbc2_data = { + .reset_name = "apbc2-reset", + }; + +-static int spacemit_ccu_register(struct device *dev, +- struct regmap *regmap, +- struct regmap *lock_regmap, +- const struct spacemit_ccu_data *data) +-{ +- struct clk_hw_onecell_data *clk_data; +- int i, ret; +- +- /* Nothing to do if the CCU does not implement any clocks */ +- if (!data->hws) +- return 0; +- +- clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), +- GFP_KERNEL); +- if (!clk_data) +- return -ENOMEM; +- +- clk_data->num = data->num; +- +- for (i = 0; i < data->num; i++) { +- struct clk_hw *hw = data->hws[i]; +- struct ccu_common *common; +- const char *name; +- +- if (!hw) { +- clk_data->hws[i] = ERR_PTR(-ENOENT); +- continue; +- } +- +- name = hw->init->name; +- +- common = hw_to_ccu_common(hw); +- common->regmap = regmap; +- common->lock_regmap = lock_regmap; +- +- ret = devm_clk_hw_register(dev, hw); +- if (ret) { +- dev_err(dev, "Cannot register clock %d - %s\n", +- i, name); +- return ret; +- } +- +- clk_data->hws[i] = hw; +- } +- +- ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); +- if (ret) +- dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); +- +- return ret; +-} +- +-static void spacemit_cadev_release(struct device *dev) +-{ +- struct auxiliary_device *adev = to_auxiliary_dev(dev); +- +- ida_free(&auxiliary_ids, adev->id); +- kfree(to_spacemit_ccu_adev(adev)); +-} +- +-static void spacemit_adev_unregister(void *data) +-{ +- struct auxiliary_device *adev = data; +- +- auxiliary_device_delete(adev); +- auxiliary_device_uninit(adev); +-} +- +-static int spacemit_ccu_reset_register(struct device *dev, +- struct regmap *regmap, +- const char *reset_name) +-{ +- struct spacemit_ccu_adev *cadev; +- struct auxiliary_device *adev; +- int ret; +- +- /* Nothing to do if the CCU does not implement a reset controller */ +- if (!reset_name) +- return 0; +- +- cadev = kzalloc(sizeof(*cadev), GFP_KERNEL); +- if (!cadev) +- return -ENOMEM; +- +- cadev->regmap = regmap; +- +- adev = &cadev->adev; +- adev->name = reset_name; +- adev->dev.parent = dev; +- adev->dev.release = spacemit_cadev_release; +- adev->dev.of_node = dev->of_node; +- ret = ida_alloc(&auxiliary_ids, GFP_KERNEL); +- if (ret < 0) +- goto err_free_cadev; +- adev->id = ret; +- +- ret = auxiliary_device_init(adev); +- if (ret) +- goto err_free_aux_id; +- +- ret = auxiliary_device_add(adev); +- if (ret) { +- auxiliary_device_uninit(adev); +- return ret; +- } +- +- return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); +- +-err_free_aux_id: +- ida_free(&auxiliary_ids, adev->id); +-err_free_cadev: +- kfree(cadev); +- +- return ret; +-} +- +-static int k1_ccu_probe(struct platform_device *pdev) +-{ +- struct regmap *base_regmap, *lock_regmap = NULL; +- const struct spacemit_ccu_data *data; +- struct device *dev = &pdev->dev; +- int ret; +- +- base_regmap = device_node_to_regmap(dev->of_node); +- if (IS_ERR(base_regmap)) +- return dev_err_probe(dev, PTR_ERR(base_regmap), +- "failed to get regmap\n"); +- +- /* +- * The lock status of PLLs locate in MPMU region, while PLLs themselves +- * are in APBS region. Reference to MPMU syscon is required to check PLL +- * status. +- */ +- if (of_device_is_compatible(dev->of_node, "spacemit,k1-pll")) { +- struct device_node *mpmu = of_parse_phandle(dev->of_node, +- "spacemit,mpmu", 0); +- if (!mpmu) +- return dev_err_probe(dev, -ENODEV, +- "Cannot parse MPMU region\n"); +- +- lock_regmap = device_node_to_regmap(mpmu); +- of_node_put(mpmu); +- +- if (IS_ERR(lock_regmap)) +- return dev_err_probe(dev, PTR_ERR(lock_regmap), +- "failed to get lock regmap\n"); +- } +- +- data = of_device_get_match_data(dev); +- +- ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); +- if (ret) +- return dev_err_probe(dev, ret, "failed to register clocks\n"); +- +- ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); +- if (ret) +- return dev_err_probe(dev, ret, "failed to register resets\n"); +- +- return 0; +-} +- + static const struct of_device_id of_k1_ccu_match[] = { + { + .compatible = "spacemit,k1-pll", +@@ -1195,6 +1021,11 @@ static const struct of_device_id of_k1_ccu_match[] = { + }; + MODULE_DEVICE_TABLE(of, of_k1_ccu_match); + ++static int k1_ccu_probe(struct platform_device *pdev) ++{ ++ return spacemit_ccu_probe(pdev, "spacemit,k1-pll"); ++} ++ + static struct platform_driver k1_ccu_driver = { + .driver = { + .name = "spacemit,k1-ccu", +diff --git a/drivers/clk/spacemit/ccu_common.c b/drivers/clk/spacemit/ccu_common.c +index 4412c4104dab..5f05b17f8452 100644 +--- a/drivers/clk/spacemit/ccu_common.c ++++ b/drivers/clk/spacemit/ccu_common.c +@@ -1,6 +1,177 @@ + // SPDX-License-Identifier: GPL-2.0-only + ++#include ++#include ++#include + #include ++#include ++#include ++#include ++ ++#include "ccu_common.h" ++ ++static DEFINE_IDA(auxiliary_ids); ++static int spacemit_ccu_register(struct device *dev, ++ struct regmap *regmap, ++ struct regmap *lock_regmap, ++ const struct spacemit_ccu_data *data) ++{ ++ struct clk_hw_onecell_data *clk_data; ++ int i, ret; ++ ++ /* Nothing to do if the CCU does not implement any clocks */ ++ if (!data->hws) ++ return 0; ++ ++ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), ++ GFP_KERNEL); ++ if (!clk_data) ++ return -ENOMEM; ++ ++ clk_data->num = data->num; ++ ++ for (i = 0; i < data->num; i++) { ++ struct clk_hw *hw = data->hws[i]; ++ struct ccu_common *common; ++ const char *name; ++ ++ if (!hw) { ++ clk_data->hws[i] = ERR_PTR(-ENOENT); ++ continue; ++ } ++ ++ name = hw->init->name; ++ ++ common = hw_to_ccu_common(hw); ++ common->regmap = regmap; ++ common->lock_regmap = lock_regmap; ++ ++ ret = devm_clk_hw_register(dev, hw); ++ if (ret) { ++ dev_err(dev, "Cannot register clock %d - %s\n", ++ i, name); ++ return ret; ++ } ++ ++ clk_data->hws[i] = hw; ++ } ++ ++ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); ++ if (ret) ++ dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); ++ ++ return ret; ++} ++ ++static void spacemit_cadev_release(struct device *dev) ++{ ++ struct auxiliary_device *adev = to_auxiliary_dev(dev); ++ ++ ida_free(&auxiliary_ids, adev->id); ++ kfree(to_spacemit_ccu_adev(adev)); ++} ++ ++static void spacemit_adev_unregister(void *data) ++{ ++ struct auxiliary_device *adev = data; ++ ++ auxiliary_device_delete(adev); ++ auxiliary_device_uninit(adev); ++} ++ ++static int spacemit_ccu_reset_register(struct device *dev, ++ struct regmap *regmap, ++ const char *reset_name) ++{ ++ struct spacemit_ccu_adev *cadev; ++ struct auxiliary_device *adev; ++ int ret; ++ ++ /* Nothing to do if the CCU does not implement a reset controller */ ++ if (!reset_name) ++ return 0; ++ ++ cadev = kzalloc(sizeof(*cadev), GFP_KERNEL); ++ if (!cadev) ++ return -ENOMEM; ++ ++ cadev->regmap = regmap; ++ ++ adev = &cadev->adev; ++ adev->name = reset_name; ++ adev->dev.parent = dev; ++ adev->dev.release = spacemit_cadev_release; ++ adev->dev.of_node = dev->of_node; ++ ret = ida_alloc(&auxiliary_ids, GFP_KERNEL); ++ if (ret < 0) ++ goto err_free_cadev; ++ adev->id = ret; ++ ++ ret = auxiliary_device_init(adev); ++ if (ret) ++ goto err_free_aux_id; ++ ++ ret = auxiliary_device_add(adev); ++ if (ret) { ++ auxiliary_device_uninit(adev); ++ return ret; ++ } ++ ++ return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); ++ ++err_free_aux_id: ++ ida_free(&auxiliary_ids, adev->id); ++err_free_cadev: ++ kfree(cadev); ++ ++ return ret; ++} ++ ++int spacemit_ccu_probe(struct platform_device *pdev, const char *compat) ++{ ++ struct regmap *base_regmap, *lock_regmap = NULL; ++ const struct spacemit_ccu_data *data; ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ base_regmap = device_node_to_regmap(dev->of_node); ++ if (IS_ERR(base_regmap)) ++ return dev_err_probe(dev, PTR_ERR(base_regmap), ++ "failed to get regmap\n"); ++ ++ /* ++ * The lock status of PLLs locate in MPMU region, while PLLs themselves ++ * are in APBS region. Reference to MPMU syscon is required to check PLL ++ * status. ++ */ ++ if (compat && of_device_is_compatible(dev->of_node, compat)) { ++ struct device_node *mpmu = of_parse_phandle(dev->of_node, ++ "spacemit,mpmu", 0); ++ if (!mpmu) ++ return dev_err_probe(dev, -ENODEV, ++ "Cannot parse MPMU region\n"); ++ ++ lock_regmap = device_node_to_regmap(mpmu); ++ of_node_put(mpmu); ++ ++ if (IS_ERR(lock_regmap)) ++ return dev_err_probe(dev, PTR_ERR(lock_regmap), ++ "failed to get lock regmap\n"); ++ } ++ ++ data = of_device_get_match_data(dev); ++ ++ ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to register clocks\n"); ++ ++ ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to register resets\n"); ++ ++ return 0; ++} ++EXPORT_SYMBOL_NS_GPL(spacemit_ccu_probe, "CLK_SPACEMIT"); + + MODULE_DESCRIPTION("SpacemiT CCU common clock driver"); + MODULE_LICENSE("GPL"); +diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h +index da72f3836e0b..7ae244b5eace 100644 +--- a/drivers/clk/spacemit/ccu_common.h ++++ b/drivers/clk/spacemit/ccu_common.h +@@ -7,6 +7,8 @@ + #ifndef _CCU_COMMON_H_ + #define _CCU_COMMON_H_ + ++#include ++#include + #include + + struct ccu_common { +@@ -36,6 +38,12 @@ static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) + return container_of(hw, struct ccu_common, hw); + } + ++struct spacemit_ccu_data { ++ const char *reset_name; ++ struct clk_hw **hws; ++ size_t num; ++}; ++ + #define ccu_read(c, reg) \ + ({ \ + u32 tmp; \ +@@ -45,4 +53,6 @@ static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) + #define ccu_update(c, reg, mask, val) \ + regmap_update_bits((c)->regmap, (c)->reg_##reg, mask, val) + ++int spacemit_ccu_probe(struct platform_device *pdev, const char *compat); ++ + #endif /* _CCU_COMMON_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0113-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch b/SPECS/linux-lts-kmhv2/0113-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch deleted file mode 100644 index b8abaeb4f2..0000000000 --- a/SPECS/linux-lts-kmhv2/0113-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch +++ /dev/null @@ -1,70 +0,0 @@ -From fcd998b46e6d0b3681c7f4192cb27b126e034191 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:46 +0800 -Subject: [PATCH 113/467] UPSTREAM: riscv: dts: spacemit: add K3 Pico-ITX board - support - -K3 Pico-ITX is a 2.5-inch single-board computer equipted with a SpacemiT -K3 SoC. - -This minimal device tree enables booting into a serial console with UART -output. - -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-7-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 7a61318049861b777f098d7148d892d7dc79b010) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/Makefile | 1 + - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++++++++++++++++++ - 2 files changed, 30 insertions(+) - create mode 100644 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts - -diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile -index 95889e7269d1..7e2b87702571 100644 ---- a/arch/riscv/boot/dts/spacemit/Makefile -+++ b/arch/riscv/boot/dts/spacemit/Makefile -@@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb -+dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -new file mode 100644 -index 000000000000..b691304d4b74 ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd -+ * Copyright (c) 2026 Guodong Xu -+ */ -+ -+#include "k3.dtsi" -+ -+/ { -+ model = "SpacemiT K3 Pico-ITX"; -+ compatible = "spacemit,k3-pico-itx", "spacemit,k3"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0"; -+ }; -+ -+ memory@100000000 { -+ device_type = "memory"; -+ reg = <0x1 0x00000000 0x4 0x00000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0114-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch b/SPECS/linux-lts-kmhv2/0114-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch deleted file mode 100644 index ec4fc1255f..0000000000 --- a/SPECS/linux-lts-kmhv2/0114-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 0e02ccc906b37757be6723a81e0e8d49131246c6 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 19 Dec 2025 09:28:18 +0800 -Subject: [PATCH 114/467] UPSTREAM: clk: spacemit: Hide common clock driver - from user controller - -Since the common clock driver is only a dependency for other spacemit -clock driver, it should not be enabled individually, so hide this in -the Kconfig UI and let other spacemit clock driver select it. - -Signed-off-by: Inochi Amaoto -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20251219012819.440972-3-inochiama@gmail.com -Signed-off-by: Yixun Lan -(cherry picked from commit 99735a742f7e9a3e7f4cb6c58edf1b38101e7657) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/Kconfig | 14 ++++++-------- - 1 file changed, 6 insertions(+), 8 deletions(-) - -diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig -index 3854f6ae6d0e..3351e8bc801d 100644 ---- a/drivers/clk/spacemit/Kconfig -+++ b/drivers/clk/spacemit/Kconfig -@@ -1,19 +1,17 @@ - # SPDX-License-Identifier: GPL-2.0-only - --config SPACEMIT_CCU -- tristate "Clock support for SpacemiT SoCs" -+menu "Clock support for SpacemiT platforms" - depends on ARCH_SPACEMIT || COMPILE_TEST -+ -+config SPACEMIT_CCU -+ tristate - select AUXILIARY_BUS - select MFD_SYSCON -- help -- Say Y to enable clock controller unit support for SpacemiT SoCs. -- --if SPACEMIT_CCU - - config SPACEMIT_K1_CCU - tristate "Support for SpacemiT K1 SoC" -- depends on ARCH_SPACEMIT || COMPILE_TEST -+ select SPACEMIT_CCU - help - Support for clock controller unit in SpacemiT K1 SoC. - --endif -+endmenu --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch b/SPECS/linux-lts-kmhv2/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch new file mode 100644 index 0000000000..195fb33162 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch @@ -0,0 +1,79 @@ +From 597e2f7d18294ec1b59dc52d5be6ac61f4ef6075 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Sat, 3 Jan 2026 14:14:36 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: add platform SoC prefix to + reset name + +This change is needed for adding future new SpacemiT K3 reset driver. + +Since both K1 and K3 reset code register via the same module which its +name changed to spacemit_ccu, it's necessary to encode the platform/SoC +in the reset auxiliary device name to distinguish them, otherwise two +reset drivers will claim to support same "compatible" auxiliary device +even in the case of only one CCU clock driver got registered, which in +the end lead to a broken reset driver. + +This change will introduce a runtime break to reset driver, and will be +fixed in follow-up commit: +ecff77f7c041 ("reset: spacemit: fix auxiliary device id") + +Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-3-badf635993d3@gentoo.org +Reviewed-by: Alex Elder +Signed-off-by: Yixun Lan +(cherry picked from commit 0664a46f93e2fb2f75fa05b5f08949600cce88f9) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k1.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c +index 02c792a73759..dee14d25f75d 100644 +--- a/drivers/clk/spacemit/ccu-k1.c ++++ b/drivers/clk/spacemit/ccu-k1.c +@@ -789,7 +789,7 @@ static struct clk_hw *k1_ccu_mpmu_hws[] = { + }; + + static const struct spacemit_ccu_data k1_ccu_mpmu_data = { +- .reset_name = "mpmu-reset", ++ .reset_name = "k1-mpmu-reset", + .hws = k1_ccu_mpmu_hws, + .num = ARRAY_SIZE(k1_ccu_mpmu_hws), + }; +@@ -900,7 +900,7 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { + }; + + static const struct spacemit_ccu_data k1_ccu_apbc_data = { +- .reset_name = "apbc-reset", ++ .reset_name = "k1-apbc-reset", + .hws = k1_ccu_apbc_hws, + .num = ARRAY_SIZE(k1_ccu_apbc_hws), + }; +@@ -971,21 +971,21 @@ static struct clk_hw *k1_ccu_apmu_hws[] = { + }; + + static const struct spacemit_ccu_data k1_ccu_apmu_data = { +- .reset_name = "apmu-reset", ++ .reset_name = "k1-apmu-reset", + .hws = k1_ccu_apmu_hws, + .num = ARRAY_SIZE(k1_ccu_apmu_hws), + }; + + static const struct spacemit_ccu_data k1_ccu_rcpu_data = { +- .reset_name = "rcpu-reset", ++ .reset_name = "k1-rcpu-reset", + }; + + static const struct spacemit_ccu_data k1_ccu_rcpu2_data = { +- .reset_name = "rcpu2-reset", ++ .reset_name = "k1-rcpu2-reset", + }; + + static const struct spacemit_ccu_data k1_ccu_apbc2_data = { +- .reset_name = "apbc2-reset", ++ .reset_name = "k1-apbc2-reset", + }; + + static const struct of_device_id of_k1_ccu_match[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0115-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch b/SPECS/linux-lts-kmhv2/0115-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch deleted file mode 100644 index 8a5722dcf6..0000000000 --- a/SPECS/linux-lts-kmhv2/0115-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 771281a6b5e7596444e45eefb3739c0fdc34a300 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 19 Dec 2025 21:52:08 +0800 -Subject: [PATCH 115/467] UPSTREAM: clk: spacemit: prepare common ccu header - -In order to prepare adding clock driver for new K3 SoC, extract generic -code to a separate common ccu header file, so they are not defined -in K1 SoC-specific file, and then can be shared by all clock drivers. - -Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-1-badf635993d3@gentoo.org -Reviewed-by: Alex Elder -Signed-off-by: Yixun Lan -(cherry picked from commit 2b7a02c322922a37cc5fc15d055b794cc2193062) -Signed-off-by: Han Gao ---- - include/soc/spacemit/ccu.h | 21 +++++++++++++++++++++ - include/soc/spacemit/k1-syscon.h | 12 +----------- - 2 files changed, 22 insertions(+), 11 deletions(-) - create mode 100644 include/soc/spacemit/ccu.h - -diff --git a/include/soc/spacemit/ccu.h b/include/soc/spacemit/ccu.h -new file mode 100644 -index 000000000000..84dcdecccc05 ---- /dev/null -+++ b/include/soc/spacemit/ccu.h -@@ -0,0 +1,21 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __SOC_SPACEMIT_CCU_H__ -+#define __SOC_SPACEMIT_CCU_H__ -+ -+#include -+#include -+ -+/* Auxiliary device used to represent a CCU reset controller */ -+struct spacemit_ccu_adev { -+ struct auxiliary_device adev; -+ struct regmap *regmap; -+}; -+ -+static inline struct spacemit_ccu_adev * -+to_spacemit_ccu_adev(struct auxiliary_device *adev) -+{ -+ return container_of(adev, struct spacemit_ccu_adev, adev); -+} -+ -+#endif /* __SOC_SPACEMIT_CCU_H__ */ -diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-syscon.h -index 354751562c55..0be7a2e8d445 100644 ---- a/include/soc/spacemit/k1-syscon.h -+++ b/include/soc/spacemit/k1-syscon.h -@@ -5,17 +5,7 @@ - #ifndef __SOC_K1_SYSCON_H__ - #define __SOC_K1_SYSCON_H__ - --/* Auxiliary device used to represent a CCU reset controller */ --struct spacemit_ccu_adev { -- struct auxiliary_device adev; -- struct regmap *regmap; --}; -- --static inline struct spacemit_ccu_adev * --to_spacemit_ccu_adev(struct auxiliary_device *adev) --{ -- return container_of(adev, struct spacemit_ccu_adev, adev); --} -+#include "ccu.h" - - /* APBS register offset */ - #define APBS_PLL1_SWCR1 0x100 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch b/SPECS/linux-lts-kmhv2/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch new file mode 100644 index 0000000000..1bbdfdf4b9 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch @@ -0,0 +1,43 @@ +From 195ce637ead66f8aff72ecf491637b937ab32985 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 19 Dec 2025 05:34:39 +0800 +Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: fix auxiliary device id + +Due to the auxiliary register procedure moved to ccu common module where +the module name changed to spacemit_ccu, then the reset auxiliary device +register id also need to be adjusted in order to prepare for adding new +K3 reset driver, otherwise two reset drivers will claim to support same +"compatible" auxiliary device. + +In order to prevent the reset driver breakage, this commit is necessary +as a post-fix for changes introduced by two patches below, and should be +merged with them to make the patch series runtime bisectable. +("clk: spacemit: add platform SoC prefix to reset name") +("clk: spacemit: extract common ccu functions") + +Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-4-badf635993d3@gentoo.org +Acked-by: Philipp Zabel +Reviewed-by: Alex Elder +Signed-off-by: Yixun Lan +(cherry picked from commit ecff77f7c04141cc18ee2482936c96117060c0f2) +Signed-off-by: Han Gao +--- + drivers/reset/reset-spacemit.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/reset-spacemit.c +index e1272aff28f7..cc7fd1f8750d 100644 +--- a/drivers/reset/reset-spacemit.c ++++ b/drivers/reset/reset-spacemit.c +@@ -278,7 +278,7 @@ static int spacemit_reset_probe(struct auxiliary_device *adev, + + #define K1_AUX_DEV_ID(_unit) \ + { \ +- .name = "spacemit_ccu_k1." #_unit "-reset", \ ++ .name = "spacemit_ccu.k1-" #_unit "-reset", \ + .driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0116-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch b/SPECS/linux-lts-kmhv2/0116-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch deleted file mode 100644 index 1d0ba908ed..0000000000 --- a/SPECS/linux-lts-kmhv2/0116-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch +++ /dev/null @@ -1,463 +0,0 @@ -From 4884ecab8b7bfb72589924db174968f01edb5910 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 19 Dec 2025 08:07:23 +0800 -Subject: [PATCH 116/467] UPSTREAM: clk: spacemit: extract common ccu functions - -Refactor the probe function of SpacemiT's clock, and extract a common ccu -file, so new clock driver added in the future can share the same code, -which would lower the burden of maintenance. Since this commit changes the -module name from spacemit_ccu_k1 to spacemit_ccu where the auxiliary device -registered, the auxiliary device id need to be adjusted. Idea of the patch -comes from the review of K3 clock driver, please refer to this disucssion[1] -for more detail. - -This change will introduce a runtime break to reset driver, and will be -fixed in follow-up commit: -ecff77f7c041 ("reset: spacemit: fix auxiliary device id") - -Link: https://lore.kernel.org/all/aTo8sCPpVM1o9PKX@pie/ [1] -Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-2-badf635993d3@gentoo.org -Suggested-by: Yao Zi -Reviewed-by: Alex Elder -Signed-off-by: Yixun Lan -(cherry picked from commit 99669468d24ce21be12f3751e7381c47ab2c9ecd) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k1.c | 179 +----------------------------- - drivers/clk/spacemit/ccu_common.c | 171 ++++++++++++++++++++++++++++ - drivers/clk/spacemit/ccu_common.h | 10 ++ - 3 files changed, 186 insertions(+), 174 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c -index 01d9485b615d..02c792a73759 100644 ---- a/drivers/clk/spacemit/ccu-k1.c -+++ b/drivers/clk/spacemit/ccu-k1.c -@@ -5,15 +5,10 @@ - */ - - #include --#include - #include --#include --#include --#include - #include - #include - #include --#include - #include - - #include "ccu_common.h" -@@ -23,14 +18,6 @@ - - #include - --struct spacemit_ccu_data { -- const char *reset_name; -- struct clk_hw **hws; -- size_t num; --}; -- --static DEFINE_IDA(auxiliary_ids); -- - /* APBS clocks start, APBS region contains and only contains all PLL clocks */ - - /* -@@ -1001,167 +988,6 @@ static const struct spacemit_ccu_data k1_ccu_apbc2_data = { - .reset_name = "apbc2-reset", - }; - --static int spacemit_ccu_register(struct device *dev, -- struct regmap *regmap, -- struct regmap *lock_regmap, -- const struct spacemit_ccu_data *data) --{ -- struct clk_hw_onecell_data *clk_data; -- int i, ret; -- -- /* Nothing to do if the CCU does not implement any clocks */ -- if (!data->hws) -- return 0; -- -- clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), -- GFP_KERNEL); -- if (!clk_data) -- return -ENOMEM; -- -- clk_data->num = data->num; -- -- for (i = 0; i < data->num; i++) { -- struct clk_hw *hw = data->hws[i]; -- struct ccu_common *common; -- const char *name; -- -- if (!hw) { -- clk_data->hws[i] = ERR_PTR(-ENOENT); -- continue; -- } -- -- name = hw->init->name; -- -- common = hw_to_ccu_common(hw); -- common->regmap = regmap; -- common->lock_regmap = lock_regmap; -- -- ret = devm_clk_hw_register(dev, hw); -- if (ret) { -- dev_err(dev, "Cannot register clock %d - %s\n", -- i, name); -- return ret; -- } -- -- clk_data->hws[i] = hw; -- } -- -- ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); -- if (ret) -- dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); -- -- return ret; --} -- --static void spacemit_cadev_release(struct device *dev) --{ -- struct auxiliary_device *adev = to_auxiliary_dev(dev); -- -- ida_free(&auxiliary_ids, adev->id); -- kfree(to_spacemit_ccu_adev(adev)); --} -- --static void spacemit_adev_unregister(void *data) --{ -- struct auxiliary_device *adev = data; -- -- auxiliary_device_delete(adev); -- auxiliary_device_uninit(adev); --} -- --static int spacemit_ccu_reset_register(struct device *dev, -- struct regmap *regmap, -- const char *reset_name) --{ -- struct spacemit_ccu_adev *cadev; -- struct auxiliary_device *adev; -- int ret; -- -- /* Nothing to do if the CCU does not implement a reset controller */ -- if (!reset_name) -- return 0; -- -- cadev = kzalloc(sizeof(*cadev), GFP_KERNEL); -- if (!cadev) -- return -ENOMEM; -- -- cadev->regmap = regmap; -- -- adev = &cadev->adev; -- adev->name = reset_name; -- adev->dev.parent = dev; -- adev->dev.release = spacemit_cadev_release; -- adev->dev.of_node = dev->of_node; -- ret = ida_alloc(&auxiliary_ids, GFP_KERNEL); -- if (ret < 0) -- goto err_free_cadev; -- adev->id = ret; -- -- ret = auxiliary_device_init(adev); -- if (ret) -- goto err_free_aux_id; -- -- ret = auxiliary_device_add(adev); -- if (ret) { -- auxiliary_device_uninit(adev); -- return ret; -- } -- -- return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); -- --err_free_aux_id: -- ida_free(&auxiliary_ids, adev->id); --err_free_cadev: -- kfree(cadev); -- -- return ret; --} -- --static int k1_ccu_probe(struct platform_device *pdev) --{ -- struct regmap *base_regmap, *lock_regmap = NULL; -- const struct spacemit_ccu_data *data; -- struct device *dev = &pdev->dev; -- int ret; -- -- base_regmap = device_node_to_regmap(dev->of_node); -- if (IS_ERR(base_regmap)) -- return dev_err_probe(dev, PTR_ERR(base_regmap), -- "failed to get regmap\n"); -- -- /* -- * The lock status of PLLs locate in MPMU region, while PLLs themselves -- * are in APBS region. Reference to MPMU syscon is required to check PLL -- * status. -- */ -- if (of_device_is_compatible(dev->of_node, "spacemit,k1-pll")) { -- struct device_node *mpmu = of_parse_phandle(dev->of_node, -- "spacemit,mpmu", 0); -- if (!mpmu) -- return dev_err_probe(dev, -ENODEV, -- "Cannot parse MPMU region\n"); -- -- lock_regmap = device_node_to_regmap(mpmu); -- of_node_put(mpmu); -- -- if (IS_ERR(lock_regmap)) -- return dev_err_probe(dev, PTR_ERR(lock_regmap), -- "failed to get lock regmap\n"); -- } -- -- data = of_device_get_match_data(dev); -- -- ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); -- if (ret) -- return dev_err_probe(dev, ret, "failed to register clocks\n"); -- -- ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); -- if (ret) -- return dev_err_probe(dev, ret, "failed to register resets\n"); -- -- return 0; --} -- - static const struct of_device_id of_k1_ccu_match[] = { - { - .compatible = "spacemit,k1-pll", -@@ -1195,6 +1021,11 @@ static const struct of_device_id of_k1_ccu_match[] = { - }; - MODULE_DEVICE_TABLE(of, of_k1_ccu_match); - -+static int k1_ccu_probe(struct platform_device *pdev) -+{ -+ return spacemit_ccu_probe(pdev, "spacemit,k1-pll"); -+} -+ - static struct platform_driver k1_ccu_driver = { - .driver = { - .name = "spacemit,k1-ccu", -diff --git a/drivers/clk/spacemit/ccu_common.c b/drivers/clk/spacemit/ccu_common.c -index 4412c4104dab..5f05b17f8452 100644 ---- a/drivers/clk/spacemit/ccu_common.c -+++ b/drivers/clk/spacemit/ccu_common.c -@@ -1,6 +1,177 @@ - // SPDX-License-Identifier: GPL-2.0-only - -+#include -+#include -+#include - #include -+#include -+#include -+#include -+ -+#include "ccu_common.h" -+ -+static DEFINE_IDA(auxiliary_ids); -+static int spacemit_ccu_register(struct device *dev, -+ struct regmap *regmap, -+ struct regmap *lock_regmap, -+ const struct spacemit_ccu_data *data) -+{ -+ struct clk_hw_onecell_data *clk_data; -+ int i, ret; -+ -+ /* Nothing to do if the CCU does not implement any clocks */ -+ if (!data->hws) -+ return 0; -+ -+ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), -+ GFP_KERNEL); -+ if (!clk_data) -+ return -ENOMEM; -+ -+ clk_data->num = data->num; -+ -+ for (i = 0; i < data->num; i++) { -+ struct clk_hw *hw = data->hws[i]; -+ struct ccu_common *common; -+ const char *name; -+ -+ if (!hw) { -+ clk_data->hws[i] = ERR_PTR(-ENOENT); -+ continue; -+ } -+ -+ name = hw->init->name; -+ -+ common = hw_to_ccu_common(hw); -+ common->regmap = regmap; -+ common->lock_regmap = lock_regmap; -+ -+ ret = devm_clk_hw_register(dev, hw); -+ if (ret) { -+ dev_err(dev, "Cannot register clock %d - %s\n", -+ i, name); -+ return ret; -+ } -+ -+ clk_data->hws[i] = hw; -+ } -+ -+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); -+ if (ret) -+ dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); -+ -+ return ret; -+} -+ -+static void spacemit_cadev_release(struct device *dev) -+{ -+ struct auxiliary_device *adev = to_auxiliary_dev(dev); -+ -+ ida_free(&auxiliary_ids, adev->id); -+ kfree(to_spacemit_ccu_adev(adev)); -+} -+ -+static void spacemit_adev_unregister(void *data) -+{ -+ struct auxiliary_device *adev = data; -+ -+ auxiliary_device_delete(adev); -+ auxiliary_device_uninit(adev); -+} -+ -+static int spacemit_ccu_reset_register(struct device *dev, -+ struct regmap *regmap, -+ const char *reset_name) -+{ -+ struct spacemit_ccu_adev *cadev; -+ struct auxiliary_device *adev; -+ int ret; -+ -+ /* Nothing to do if the CCU does not implement a reset controller */ -+ if (!reset_name) -+ return 0; -+ -+ cadev = kzalloc(sizeof(*cadev), GFP_KERNEL); -+ if (!cadev) -+ return -ENOMEM; -+ -+ cadev->regmap = regmap; -+ -+ adev = &cadev->adev; -+ adev->name = reset_name; -+ adev->dev.parent = dev; -+ adev->dev.release = spacemit_cadev_release; -+ adev->dev.of_node = dev->of_node; -+ ret = ida_alloc(&auxiliary_ids, GFP_KERNEL); -+ if (ret < 0) -+ goto err_free_cadev; -+ adev->id = ret; -+ -+ ret = auxiliary_device_init(adev); -+ if (ret) -+ goto err_free_aux_id; -+ -+ ret = auxiliary_device_add(adev); -+ if (ret) { -+ auxiliary_device_uninit(adev); -+ return ret; -+ } -+ -+ return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); -+ -+err_free_aux_id: -+ ida_free(&auxiliary_ids, adev->id); -+err_free_cadev: -+ kfree(cadev); -+ -+ return ret; -+} -+ -+int spacemit_ccu_probe(struct platform_device *pdev, const char *compat) -+{ -+ struct regmap *base_regmap, *lock_regmap = NULL; -+ const struct spacemit_ccu_data *data; -+ struct device *dev = &pdev->dev; -+ int ret; -+ -+ base_regmap = device_node_to_regmap(dev->of_node); -+ if (IS_ERR(base_regmap)) -+ return dev_err_probe(dev, PTR_ERR(base_regmap), -+ "failed to get regmap\n"); -+ -+ /* -+ * The lock status of PLLs locate in MPMU region, while PLLs themselves -+ * are in APBS region. Reference to MPMU syscon is required to check PLL -+ * status. -+ */ -+ if (compat && of_device_is_compatible(dev->of_node, compat)) { -+ struct device_node *mpmu = of_parse_phandle(dev->of_node, -+ "spacemit,mpmu", 0); -+ if (!mpmu) -+ return dev_err_probe(dev, -ENODEV, -+ "Cannot parse MPMU region\n"); -+ -+ lock_regmap = device_node_to_regmap(mpmu); -+ of_node_put(mpmu); -+ -+ if (IS_ERR(lock_regmap)) -+ return dev_err_probe(dev, PTR_ERR(lock_regmap), -+ "failed to get lock regmap\n"); -+ } -+ -+ data = of_device_get_match_data(dev); -+ -+ ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to register clocks\n"); -+ -+ ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to register resets\n"); -+ -+ return 0; -+} -+EXPORT_SYMBOL_NS_GPL(spacemit_ccu_probe, "CLK_SPACEMIT"); - - MODULE_DESCRIPTION("SpacemiT CCU common clock driver"); - MODULE_LICENSE("GPL"); -diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h -index da72f3836e0b..7ae244b5eace 100644 ---- a/drivers/clk/spacemit/ccu_common.h -+++ b/drivers/clk/spacemit/ccu_common.h -@@ -7,6 +7,8 @@ - #ifndef _CCU_COMMON_H_ - #define _CCU_COMMON_H_ - -+#include -+#include - #include - - struct ccu_common { -@@ -36,6 +38,12 @@ static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) - return container_of(hw, struct ccu_common, hw); - } - -+struct spacemit_ccu_data { -+ const char *reset_name; -+ struct clk_hw **hws; -+ size_t num; -+}; -+ - #define ccu_read(c, reg) \ - ({ \ - u32 tmp; \ -@@ -45,4 +53,6 @@ static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) - #define ccu_update(c, reg, mask, val) \ - regmap_update_bits((c)->regmap, (c)->reg_##reg, mask, val) - -+int spacemit_ccu_probe(struct platform_device *pdev, const char *compat); -+ - #endif /* _CCU_COMMON_H_ */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch b/SPECS/linux-lts-kmhv2/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch new file mode 100644 index 0000000000..eb8a0da4ac --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch @@ -0,0 +1,519 @@ +From 4887997f9fc66c19a62763d21f3beb9036a5470b Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Sat, 1 Nov 2025 20:56:42 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: soc: spacemit: k3: add clock + support + +Add compatible strings for clock drivers to support Spacemit K3 SoC, +also includes all the defined clock IDs. + +The SpacemiT K3 SoC clock IP is scattered over several different blocks, +which are APBC, APBS, APMU, DCIU, MPMU, all of them are capable of +generating clock and reset signals. APMU and MPMU have additional Power +Domain management functionality. + +Following is a brief list that shows devices managed in each block: + +APBC: UART, GPIO, PWM, SPI, TIMER, I2S, IR, DR, TSEN, IPC, CAN +APBS: various PPL clocks control +APMU: CCI, CPU, CSI, ISP, LCD, USB, QSPI, DMA, VPU, GPU, DSI, PCIe, EMAC.. +DCID: SRAM, DMA, TCM +MPMU: various PLL1 derived clocks, UART, WATCHDOG, I2S + +Link: https://lore.kernel.org/r/20260108-k3-clk-v5-1-42a11b74ad58@gentoo.org +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Yixun Lan +(cherry picked from commit efe897b557e211a09f51d749eae5eca933e8bf56) +Signed-off-by: Han Gao +--- + .../bindings/clock/spacemit,k1-pll.yaml | 9 +- + .../soc/spacemit/spacemit,k1-syscon.yaml | 14 +- + .../dt-bindings/clock/spacemit,k3-clocks.h | 390 ++++++++++++++++++ + 3 files changed, 408 insertions(+), 5 deletions(-) + create mode 100644 include/dt-bindings/clock/spacemit,k3-clocks.h + +diff --git a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml +index 06bafd68c00a..cddf6a56dac0 100644 +--- a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml ++++ b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml +@@ -4,14 +4,16 @@ + $id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# + +-title: SpacemiT K1 PLL ++title: SpacemiT K1/K3 PLL + + maintainers: + - Haylen Chu + + properties: + compatible: +- const: spacemit,k1-pll ++ enum: ++ - spacemit,k1-pll ++ - spacemit,k3-pll + + reg: + maxItems: 1 +@@ -28,7 +30,8 @@ properties: + "#clock-cells": + const: 1 + description: +- See for valid indices. ++ For K1 SoC, check for valid indices. ++ For K3 SoC, check for valid indices. + + required: + - compatible +diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +index 133a391ee68c..d87131da30bc 100644 +--- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml ++++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +@@ -4,7 +4,7 @@ + $id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# + +-title: SpacemiT K1 SoC System Controller ++title: SpacemiT K1/K3 SoC System Controller + + maintainers: + - Haylen Chu +@@ -22,6 +22,10 @@ properties: + - spacemit,k1-syscon-rcpu + - spacemit,k1-syscon-rcpu2 + - spacemit,k1-syscon-apbc2 ++ - spacemit,k3-syscon-apbc ++ - spacemit,k3-syscon-apmu ++ - spacemit,k3-syscon-dciu ++ - spacemit,k3-syscon-mpmu + + reg: + maxItems: 1 +@@ -39,7 +43,8 @@ properties: + "#clock-cells": + const: 1 + description: +- See for valid indices. ++ For K1 SoC, check for valid indices. ++ For K3 SoC, check for valid indices. + + "#power-domain-cells": + const: 1 +@@ -60,6 +65,8 @@ allOf: + enum: + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu ++ - spacemit,k3-syscon-apmu ++ - spacemit,k3-syscon-mpmu + then: + required: + - "#power-domain-cells" +@@ -74,6 +81,9 @@ allOf: + - spacemit,k1-syscon-apbc + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu ++ - spacemit,k3-syscon-apbc ++ - spacemit,k3-syscon-apmu ++ - spacemit,k3-syscon-mpmu + then: + required: + - clocks +diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h +new file mode 100644 +index 000000000000..b22336f3ae40 +--- /dev/null ++++ b/include/dt-bindings/clock/spacemit,k3-clocks.h +@@ -0,0 +1,390 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ ++ ++#ifndef _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ ++#define _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ ++ ++/* APBS (PLL) clocks */ ++#define CLK_PLL1 0 ++#define CLK_PLL2 1 ++#define CLK_PLL3 2 ++#define CLK_PLL4 3 ++#define CLK_PLL5 4 ++#define CLK_PLL6 5 ++#define CLK_PLL7 6 ++#define CLK_PLL8 7 ++#define CLK_PLL1_D2 8 ++#define CLK_PLL1_D3 9 ++#define CLK_PLL1_D4 10 ++#define CLK_PLL1_D5 11 ++#define CLK_PLL1_D6 12 ++#define CLK_PLL1_D7 13 ++#define CLK_PLL1_D8 14 ++#define CLK_PLL1_DX 15 ++#define CLK_PLL1_D64 16 ++#define CLK_PLL1_D10_AUD 17 ++#define CLK_PLL1_D100_AUD 18 ++#define CLK_PLL2_D1 19 ++#define CLK_PLL2_D2 20 ++#define CLK_PLL2_D3 21 ++#define CLK_PLL2_D4 22 ++#define CLK_PLL2_D5 23 ++#define CLK_PLL2_D6 24 ++#define CLK_PLL2_D7 25 ++#define CLK_PLL2_D8 26 ++#define CLK_PLL2_66 27 ++#define CLK_PLL2_33 28 ++#define CLK_PLL2_50 29 ++#define CLK_PLL2_25 30 ++#define CLK_PLL2_20 31 ++#define CLK_PLL2_D24_125 32 ++#define CLK_PLL2_D120_25 33 ++#define CLK_PLL3_D1 34 ++#define CLK_PLL3_D2 35 ++#define CLK_PLL3_D3 36 ++#define CLK_PLL3_D4 37 ++#define CLK_PLL3_D5 38 ++#define CLK_PLL3_D6 39 ++#define CLK_PLL3_D7 40 ++#define CLK_PLL3_D8 41 ++#define CLK_PLL4_D1 42 ++#define CLK_PLL4_D2 43 ++#define CLK_PLL4_D3 44 ++#define CLK_PLL4_D4 45 ++#define CLK_PLL4_D5 46 ++#define CLK_PLL4_D6 47 ++#define CLK_PLL4_D7 48 ++#define CLK_PLL4_D8 49 ++#define CLK_PLL5_D1 50 ++#define CLK_PLL5_D2 51 ++#define CLK_PLL5_D3 52 ++#define CLK_PLL5_D4 53 ++#define CLK_PLL5_D5 54 ++#define CLK_PLL5_D6 55 ++#define CLK_PLL5_D7 56 ++#define CLK_PLL5_D8 57 ++#define CLK_PLL6_D1 58 ++#define CLK_PLL6_D2 59 ++#define CLK_PLL6_D3 60 ++#define CLK_PLL6_D4 61 ++#define CLK_PLL6_D5 62 ++#define CLK_PLL6_D6 63 ++#define CLK_PLL6_D7 64 ++#define CLK_PLL6_D8 65 ++#define CLK_PLL6_80 66 ++#define CLK_PLL6_40 67 ++#define CLK_PLL6_20 68 ++#define CLK_PLL7_D1 69 ++#define CLK_PLL7_D2 70 ++#define CLK_PLL7_D3 71 ++#define CLK_PLL7_D4 72 ++#define CLK_PLL7_D5 73 ++#define CLK_PLL7_D6 74 ++#define CLK_PLL7_D7 75 ++#define CLK_PLL7_D8 76 ++#define CLK_PLL8_D1 77 ++#define CLK_PLL8_D2 78 ++#define CLK_PLL8_D3 79 ++#define CLK_PLL8_D4 80 ++#define CLK_PLL8_D5 81 ++#define CLK_PLL8_D6 82 ++#define CLK_PLL8_D7 83 ++#define CLK_PLL8_D8 84 ++ ++/* MPMU clocks */ ++#define CLK_MPMU_PLL1_307P2 0 ++#define CLK_MPMU_PLL1_76P8 1 ++#define CLK_MPMU_PLL1_61P44 2 ++#define CLK_MPMU_PLL1_153P6 3 ++#define CLK_MPMU_PLL1_102P4 4 ++#define CLK_MPMU_PLL1_51P2 5 ++#define CLK_MPMU_PLL1_51P2_AP 6 ++#define CLK_MPMU_PLL1_57P6 7 ++#define CLK_MPMU_PLL1_25P6 8 ++#define CLK_MPMU_PLL1_12P8 9 ++#define CLK_MPMU_PLL1_12P8_WDT 10 ++#define CLK_MPMU_PLL1_6P4 11 ++#define CLK_MPMU_PLL1_3P2 12 ++#define CLK_MPMU_PLL1_1P6 13 ++#define CLK_MPMU_PLL1_0P8 14 ++#define CLK_MPMU_PLL1_409P6 15 ++#define CLK_MPMU_PLL1_204P8 16 ++#define CLK_MPMU_PLL1_491 17 ++#define CLK_MPMU_PLL1_245P76 18 ++#define CLK_MPMU_PLL1_614 19 ++#define CLK_MPMU_PLL1_47P26 20 ++#define CLK_MPMU_PLL1_31P5 21 ++#define CLK_MPMU_PLL1_819 22 ++#define CLK_MPMU_PLL1_1228 23 ++#define CLK_MPMU_APB 24 ++#define CLK_MPMU_SLOW_UART 25 ++#define CLK_MPMU_SLOW_UART1 26 ++#define CLK_MPMU_SLOW_UART2 27 ++#define CLK_MPMU_WDT 28 ++#define CLK_MPMU_WDT_BUS 29 ++#define CLK_MPMU_RIPC 30 ++#define CLK_MPMU_I2S_153P6 31 ++#define CLK_MPMU_I2S_153P6_BASE 32 ++#define CLK_MPMU_I2S_SYSCLK_SRC 33 ++#define CLK_MPMU_I2S1_SYSCLK 34 ++#define CLK_MPMU_I2S_BCLK 35 ++#define CLK_MPMU_I2S0_SYSCLK_SEL 36 ++#define CLK_MPMU_I2S2_SYSCLK_SEL 37 ++#define CLK_MPMU_I2S3_SYSCLK_SEL 38 ++#define CLK_MPMU_I2S4_SYSCLK_SEL 39 ++#define CLK_MPMU_I2S5_SYSCLK_SEL 40 ++#define CLK_MPMU_I2S0_SYSCLK_DIV 41 ++#define CLK_MPMU_I2S2_SYSCLK_DIV 42 ++#define CLK_MPMU_I2S3_SYSCLK_DIV 43 ++#define CLK_MPMU_I2S4_SYSCLK_DIV 44 ++#define CLK_MPMU_I2S5_SYSCLK_DIV 45 ++#define CLK_MPMU_I2S0_SYSCLK 46 ++#define CLK_MPMU_I2S2_SYSCLK 47 ++#define CLK_MPMU_I2S3_SYSCLK 48 ++#define CLK_MPMU_I2S4_SYSCLK 49 ++#define CLK_MPMU_I2S5_SYSCLK 50 ++ ++/* APBC clocks */ ++#define CLK_APBC_UART0 0 ++#define CLK_APBC_UART2 1 ++#define CLK_APBC_UART3 2 ++#define CLK_APBC_UART4 3 ++#define CLK_APBC_UART5 4 ++#define CLK_APBC_UART6 5 ++#define CLK_APBC_UART7 6 ++#define CLK_APBC_UART8 7 ++#define CLK_APBC_UART9 8 ++#define CLK_APBC_UART10 9 ++#define CLK_APBC_UART0_BUS 10 ++#define CLK_APBC_UART2_BUS 11 ++#define CLK_APBC_UART3_BUS 12 ++#define CLK_APBC_UART4_BUS 13 ++#define CLK_APBC_UART5_BUS 14 ++#define CLK_APBC_UART6_BUS 15 ++#define CLK_APBC_UART7_BUS 16 ++#define CLK_APBC_UART8_BUS 17 ++#define CLK_APBC_UART9_BUS 18 ++#define CLK_APBC_UART10_BUS 19 ++#define CLK_APBC_GPIO 20 ++#define CLK_APBC_GPIO_BUS 21 ++#define CLK_APBC_PWM0 22 ++#define CLK_APBC_PWM1 23 ++#define CLK_APBC_PWM2 24 ++#define CLK_APBC_PWM3 25 ++#define CLK_APBC_PWM4 26 ++#define CLK_APBC_PWM5 27 ++#define CLK_APBC_PWM6 28 ++#define CLK_APBC_PWM7 29 ++#define CLK_APBC_PWM8 30 ++#define CLK_APBC_PWM9 31 ++#define CLK_APBC_PWM10 32 ++#define CLK_APBC_PWM11 33 ++#define CLK_APBC_PWM12 34 ++#define CLK_APBC_PWM13 35 ++#define CLK_APBC_PWM14 36 ++#define CLK_APBC_PWM15 37 ++#define CLK_APBC_PWM16 38 ++#define CLK_APBC_PWM17 39 ++#define CLK_APBC_PWM18 40 ++#define CLK_APBC_PWM19 41 ++#define CLK_APBC_PWM0_BUS 42 ++#define CLK_APBC_PWM1_BUS 43 ++#define CLK_APBC_PWM2_BUS 44 ++#define CLK_APBC_PWM3_BUS 45 ++#define CLK_APBC_PWM4_BUS 46 ++#define CLK_APBC_PWM5_BUS 47 ++#define CLK_APBC_PWM6_BUS 48 ++#define CLK_APBC_PWM7_BUS 49 ++#define CLK_APBC_PWM8_BUS 50 ++#define CLK_APBC_PWM9_BUS 51 ++#define CLK_APBC_PWM10_BUS 52 ++#define CLK_APBC_PWM11_BUS 53 ++#define CLK_APBC_PWM12_BUS 54 ++#define CLK_APBC_PWM13_BUS 55 ++#define CLK_APBC_PWM14_BUS 56 ++#define CLK_APBC_PWM15_BUS 57 ++#define CLK_APBC_PWM16_BUS 58 ++#define CLK_APBC_PWM17_BUS 59 ++#define CLK_APBC_PWM18_BUS 60 ++#define CLK_APBC_PWM19_BUS 61 ++#define CLK_APBC_SPI0_I2S_BCLK 62 ++#define CLK_APBC_SPI1_I2S_BCLK 63 ++#define CLK_APBC_SPI3_I2S_BCLK 64 ++#define CLK_APBC_SPI0 65 ++#define CLK_APBC_SPI1 66 ++#define CLK_APBC_SPI3 67 ++#define CLK_APBC_SPI0_BUS 68 ++#define CLK_APBC_SPI1_BUS 69 ++#define CLK_APBC_SPI3_BUS 70 ++#define CLK_APBC_RTC 71 ++#define CLK_APBC_RTC_BUS 72 ++#define CLK_APBC_TWSI0 73 ++#define CLK_APBC_TWSI1 74 ++#define CLK_APBC_TWSI2 75 ++#define CLK_APBC_TWSI4 76 ++#define CLK_APBC_TWSI5 77 ++#define CLK_APBC_TWSI6 78 ++#define CLK_APBC_TWSI8 79 ++#define CLK_APBC_TWSI0_BUS 80 ++#define CLK_APBC_TWSI1_BUS 81 ++#define CLK_APBC_TWSI2_BUS 82 ++#define CLK_APBC_TWSI4_BUS 83 ++#define CLK_APBC_TWSI5_BUS 84 ++#define CLK_APBC_TWSI6_BUS 85 ++#define CLK_APBC_TWSI8_BUS 86 ++#define CLK_APBC_TIMERS0 87 ++#define CLK_APBC_TIMERS1 88 ++#define CLK_APBC_TIMERS2 89 ++#define CLK_APBC_TIMERS3 90 ++#define CLK_APBC_TIMERS4 91 ++#define CLK_APBC_TIMERS5 92 ++#define CLK_APBC_TIMERS6 93 ++#define CLK_APBC_TIMERS7 94 ++#define CLK_APBC_TIMERS0_BUS 95 ++#define CLK_APBC_TIMERS1_BUS 96 ++#define CLK_APBC_TIMERS2_BUS 97 ++#define CLK_APBC_TIMERS3_BUS 98 ++#define CLK_APBC_TIMERS4_BUS 99 ++#define CLK_APBC_TIMERS5_BUS 100 ++#define CLK_APBC_TIMERS6_BUS 101 ++#define CLK_APBC_TIMERS7_BUS 102 ++#define CLK_APBC_AIB 103 ++#define CLK_APBC_AIB_BUS 104 ++#define CLK_APBC_ONEWIRE 105 ++#define CLK_APBC_ONEWIRE_BUS 106 ++#define CLK_APBC_I2S0_BCLK 107 ++#define CLK_APBC_I2S1_BCLK 108 ++#define CLK_APBC_I2S2_BCLK 109 ++#define CLK_APBC_I2S3_BCLK 110 ++#define CLK_APBC_I2S4_BCLK 111 ++#define CLK_APBC_I2S5_BCLK 112 ++#define CLK_APBC_I2S0 113 ++#define CLK_APBC_I2S1 114 ++#define CLK_APBC_I2S2 115 ++#define CLK_APBC_I2S3 116 ++#define CLK_APBC_I2S4 117 ++#define CLK_APBC_I2S5 118 ++#define CLK_APBC_I2S0_BUS 119 ++#define CLK_APBC_I2S1_BUS 120 ++#define CLK_APBC_I2S2_BUS 121 ++#define CLK_APBC_I2S3_BUS 122 ++#define CLK_APBC_I2S4_BUS 123 ++#define CLK_APBC_I2S5_BUS 124 ++#define CLK_APBC_DRO 125 ++#define CLK_APBC_IR0 126 ++#define CLK_APBC_IR1 127 ++#define CLK_APBC_TSEN 128 ++#define CLK_APBC_TSEN_BUS 129 ++#define CLK_APBC_IPC_AP2RCPU 130 ++#define CLK_APBC_IPC_AP2RCPU_BUS 131 ++#define CLK_APBC_CAN0 132 ++#define CLK_APBC_CAN1 133 ++#define CLK_APBC_CAN2 134 ++#define CLK_APBC_CAN3 135 ++#define CLK_APBC_CAN4 136 ++#define CLK_APBC_CAN0_BUS 137 ++#define CLK_APBC_CAN1_BUS 138 ++#define CLK_APBC_CAN2_BUS 139 ++#define CLK_APBC_CAN3_BUS 140 ++#define CLK_APBC_CAN4_BUS 141 ++ ++/* APMU clocks */ ++#define CLK_APMU_AXICLK 0 ++#define CLK_APMU_CCI550 1 ++#define CLK_APMU_CPU_C0_CORE 2 ++#define CLK_APMU_CPU_C1_CORE 3 ++#define CLK_APMU_CPU_C2_CORE 4 ++#define CLK_APMU_CPU_C3_CORE 5 ++#define CLK_APMU_CCIC2PHY 6 ++#define CLK_APMU_CCIC3PHY 7 ++#define CLK_APMU_CSI 8 ++#define CLK_APMU_ISP_BUS 9 ++#define CLK_APMU_D1P_1228P8 10 ++#define CLK_APMU_D1P_819P2 11 ++#define CLK_APMU_D1P_614P4 12 ++#define CLK_APMU_D1P_491P52 13 ++#define CLK_APMU_D1P_409P6 14 ++#define CLK_APMU_D1P_307P2 15 ++#define CLK_APMU_D1P_245P76 16 ++#define CLK_APMU_V2D 17 ++#define CLK_APMU_DSI_ESC 18 ++#define CLK_APMU_LCD_HCLK 19 ++#define CLK_APMU_LCD_DSC 20 ++#define CLK_APMU_LCD_PXCLK 21 ++#define CLK_APMU_LCD_MCLK 22 ++#define CLK_APMU_CCIC_4X 23 ++#define CLK_APMU_CCIC1PHY 24 ++#define CLK_APMU_SC2_HCLK 25 ++#define CLK_APMU_SDH_AXI 26 ++#define CLK_APMU_SDH0 27 ++#define CLK_APMU_SDH1 28 ++#define CLK_APMU_SDH2 29 ++#define CLK_APMU_USB2_BUS 30 ++#define CLK_APMU_USB3_PORTA_BUS 31 ++#define CLK_APMU_USB3_PORTB_BUS 32 ++#define CLK_APMU_USB3_PORTC_BUS 33 ++#define CLK_APMU_USB3_PORTD_BUS 34 ++#define CLK_APMU_QSPI 35 ++#define CLK_APMU_QSPI_BUS 36 ++#define CLK_APMU_DMA 37 ++#define CLK_APMU_AES_WTM 38 ++#define CLK_APMU_VPU 39 ++#define CLK_APMU_DTC 40 ++#define CLK_APMU_GPU 41 ++#define CLK_APMU_MC_AHB 42 ++#define CLK_APMU_TOP_DCLK 43 ++#define CLK_APMU_UCIE 44 ++#define CLK_APMU_UCIE_SBCLK 45 ++#define CLK_APMU_RCPU 46 ++#define CLK_APMU_DSI4LN2_DSI_ESC 47 ++#define CLK_APMU_DSI4LN2_LCD_DSC 48 ++#define CLK_APMU_DSI4LN2_LCD_PXCLK 49 ++#define CLK_APMU_DSI4LN2_LCD_MCLK 50 ++#define CLK_APMU_DSI4LN2_DPU_ACLK 51 ++#define CLK_APMU_DPU_ACLK 52 ++#define CLK_APMU_UFS_ACLK 53 ++#define CLK_APMU_EDP0_PXCLK 54 ++#define CLK_APMU_EDP1_PXCLK 55 ++#define CLK_APMU_PCIE_PORTA_MSTE 56 ++#define CLK_APMU_PCIE_PORTA_SLV 57 ++#define CLK_APMU_PCIE_PORTB_MSTE 58 ++#define CLK_APMU_PCIE_PORTB_SLV 59 ++#define CLK_APMU_PCIE_PORTC_MSTE 60 ++#define CLK_APMU_PCIE_PORTC_SLV 61 ++#define CLK_APMU_PCIE_PORTD_MSTE 62 ++#define CLK_APMU_PCIE_PORTD_SLV 63 ++#define CLK_APMU_PCIE_PORTE_MSTE 64 ++#define CLK_APMU_PCIE_PORTE_SLV 65 ++#define CLK_APMU_EMAC0_BUS 66 ++#define CLK_APMU_EMAC0_REF 67 ++#define CLK_APMU_EMAC0_1588 68 ++#define CLK_APMU_EMAC0_RGMII_TX 69 ++#define CLK_APMU_EMAC1_BUS 70 ++#define CLK_APMU_EMAC1_REF 71 ++#define CLK_APMU_EMAC1_1588 72 ++#define CLK_APMU_EMAC1_RGMII_TX 73 ++#define CLK_APMU_EMAC2_BUS 74 ++#define CLK_APMU_EMAC2_REF 75 ++#define CLK_APMU_EMAC2_1588 76 ++#define CLK_APMU_EMAC2_RGMII_TX 77 ++#define CLK_APMU_ESPI_SCLK_SRC 78 ++#define CLK_APMU_ESPI_SCLK 79 ++#define CLK_APMU_ESPI_MCLK 80 ++#define CLK_APMU_CAM_SRC1 81 ++#define CLK_APMU_CAM_SRC2 82 ++#define CLK_APMU_CAM_SRC3 83 ++#define CLK_APMU_CAM_SRC4 84 ++#define CLK_APMU_ISIM_VCLK0 85 ++#define CLK_APMU_ISIM_VCLK1 86 ++#define CLK_APMU_ISIM_VCLK2 87 ++#define CLK_APMU_ISIM_VCLK3 88 ++ ++/* DCIU clocks */ ++#define CLK_DCIU_HDMA 0 ++#define CLK_DCIU_DMA350 1 ++#define CLK_DCIU_C2_TCM_PIPE 2 ++#define CLK_DCIU_C3_TCM_PIPE 3 ++ ++#endif /* _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0117-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch b/SPECS/linux-lts-kmhv2/0117-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch deleted file mode 100644 index 72381976e0..0000000000 --- a/SPECS/linux-lts-kmhv2/0117-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 7c0b4de9221472ba52db151507973c2e67c7f5c2 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sat, 3 Jan 2026 14:14:36 +0800 -Subject: [PATCH 117/467] UPSTREAM: clk: spacemit: add platform SoC prefix to - reset name - -This change is needed for adding future new SpacemiT K3 reset driver. - -Since both K1 and K3 reset code register via the same module which its -name changed to spacemit_ccu, it's necessary to encode the platform/SoC -in the reset auxiliary device name to distinguish them, otherwise two -reset drivers will claim to support same "compatible" auxiliary device -even in the case of only one CCU clock driver got registered, which in -the end lead to a broken reset driver. - -This change will introduce a runtime break to reset driver, and will be -fixed in follow-up commit: -ecff77f7c041 ("reset: spacemit: fix auxiliary device id") - -Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-3-badf635993d3@gentoo.org -Reviewed-by: Alex Elder -Signed-off-by: Yixun Lan -(cherry picked from commit 0664a46f93e2fb2f75fa05b5f08949600cce88f9) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k1.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c -index 02c792a73759..dee14d25f75d 100644 ---- a/drivers/clk/spacemit/ccu-k1.c -+++ b/drivers/clk/spacemit/ccu-k1.c -@@ -789,7 +789,7 @@ static struct clk_hw *k1_ccu_mpmu_hws[] = { - }; - - static const struct spacemit_ccu_data k1_ccu_mpmu_data = { -- .reset_name = "mpmu-reset", -+ .reset_name = "k1-mpmu-reset", - .hws = k1_ccu_mpmu_hws, - .num = ARRAY_SIZE(k1_ccu_mpmu_hws), - }; -@@ -900,7 +900,7 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { - }; - - static const struct spacemit_ccu_data k1_ccu_apbc_data = { -- .reset_name = "apbc-reset", -+ .reset_name = "k1-apbc-reset", - .hws = k1_ccu_apbc_hws, - .num = ARRAY_SIZE(k1_ccu_apbc_hws), - }; -@@ -971,21 +971,21 @@ static struct clk_hw *k1_ccu_apmu_hws[] = { - }; - - static const struct spacemit_ccu_data k1_ccu_apmu_data = { -- .reset_name = "apmu-reset", -+ .reset_name = "k1-apmu-reset", - .hws = k1_ccu_apmu_hws, - .num = ARRAY_SIZE(k1_ccu_apmu_hws), - }; - - static const struct spacemit_ccu_data k1_ccu_rcpu_data = { -- .reset_name = "rcpu-reset", -+ .reset_name = "k1-rcpu-reset", - }; - - static const struct spacemit_ccu_data k1_ccu_rcpu2_data = { -- .reset_name = "rcpu2-reset", -+ .reset_name = "k1-rcpu2-reset", - }; - - static const struct spacemit_ccu_data k1_ccu_apbc2_data = { -- .reset_name = "apbc2-reset", -+ .reset_name = "k1-apbc2-reset", - }; - - static const struct of_device_id of_k1_ccu_match[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch b/SPECS/linux-lts-kmhv2/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch new file mode 100644 index 0000000000..3bd158963f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch @@ -0,0 +1,101 @@ +From f461f20d8d5d33bdf1d9fa07acf5a6337f03e57c Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 31 Oct 2025 20:40:46 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: ccu_mix: add inverted enable + gate clock + +K3 SoC has the clock IP which support to write value 0 for enabling the +clock, while write 1 for disabling it, thus the enable BIT is inverted. +So, introduce a flag to support the inverted gate clock. + +Link: https://lore.kernel.org/r/20260108-k3-clk-v5-2-42a11b74ad58@gentoo.org +Signed-off-by: Yixun Lan +(cherry picked from commit ace73b7e27633ec770cfb24cd4ff42c24815a9aa) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu_mix.c | 12 ++++++++---- + drivers/clk/spacemit/ccu_mix.h | 12 ++++++++++++ + 2 files changed, 20 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu_mix.c b/drivers/clk/spacemit/ccu_mix.c +index 9a3fc9ea1ce5..a8b407049bf4 100644 +--- a/drivers/clk/spacemit/ccu_mix.c ++++ b/drivers/clk/spacemit/ccu_mix.c +@@ -16,17 +16,19 @@ + static void ccu_gate_disable(struct clk_hw *hw) + { + struct ccu_mix *mix = hw_to_ccu_mix(hw); ++ struct ccu_gate_config *gate = &mix->gate; ++ u32 val = gate->inverted ? gate->mask : 0; + +- ccu_update(&mix->common, ctrl, mix->gate.mask, 0); ++ ccu_update(&mix->common, ctrl, gate->mask, val); + } + + static int ccu_gate_enable(struct clk_hw *hw) + { + struct ccu_mix *mix = hw_to_ccu_mix(hw); + struct ccu_gate_config *gate = &mix->gate; ++ u32 val = gate->inverted ? 0 : gate->mask; + +- ccu_update(&mix->common, ctrl, gate->mask, gate->mask); +- ++ ccu_update(&mix->common, ctrl, gate->mask, val); + return 0; + } + +@@ -34,8 +36,10 @@ static int ccu_gate_is_enabled(struct clk_hw *hw) + { + struct ccu_mix *mix = hw_to_ccu_mix(hw); + struct ccu_gate_config *gate = &mix->gate; ++ u32 tmp = ccu_read(&mix->common, ctrl) & gate->mask; ++ u32 val = gate->inverted ? 0 : gate->mask; + +- return (ccu_read(&mix->common, ctrl) & gate->mask) == gate->mask; ++ return !!(tmp == val); + } + + static unsigned long ccu_factor_recalc_rate(struct clk_hw *hw, +diff --git a/drivers/clk/spacemit/ccu_mix.h b/drivers/clk/spacemit/ccu_mix.h +index 54d40cd39b27..8a70cf151461 100644 +--- a/drivers/clk/spacemit/ccu_mix.h ++++ b/drivers/clk/spacemit/ccu_mix.h +@@ -16,9 +16,11 @@ + * + * @mask: Mask to enable the gate. Some clocks may have more than one bit + * set in this field. ++ * @inverted: Enable bit is inverted, 1 - disable clock, 0 - enable clock + */ + struct ccu_gate_config { + u32 mask; ++ bool inverted; + }; + + struct ccu_factor_config { +@@ -48,6 +50,7 @@ struct ccu_mix { + #define CCU_FACTOR_INIT(_div, _mul) { .div = _div, .mul = _mul } + #define CCU_MUX_INIT(_shift, _width) { .shift = _shift, .width = _width } + #define CCU_DIV_INIT(_shift, _width) { .shift = _shift, .width = _width } ++#define CCU_GATE_FLAGS_INIT(_mask, _inverted) { .mask = _mask, .inverted = _inverted } + + #define CCU_PARENT_HW(_parent) { .hw = &_parent.common.hw } + #define CCU_PARENT_NAME(_name) { .fw_name = #_name } +@@ -101,6 +104,15 @@ static struct ccu_mix _name = { \ + } \ + } + ++#define CCU_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _inverted, _flags) \ ++static struct ccu_mix _name = { \ ++ .gate = CCU_GATE_FLAGS_INIT(_mask_gate, _inverted), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ CCU_MIX_INITHW(_name, _parent, spacemit_ccu_gate_ops, _flags), \ ++ } \ ++} ++ + #define CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \ + _mul, _flags) \ + static struct ccu_mix _name = { \ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch b/SPECS/linux-lts-kmhv2/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch new file mode 100644 index 0000000000..6dfcedf96e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch @@ -0,0 +1,285 @@ +From a7ce4c7a2f5e9b248b21befc2f291b0d3ae3b195 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 27 Oct 2025 21:41:24 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: ccu_pll: add plla type clock + +Introduce a new clock PLLA for SpacemiT's K3 SoC which has a different +register layout comparing to previous PPL type. And, It is configured +by swcr1, swcr3 and swcr2 BIT[15:8]. + +Link: https://lore.kernel.org/r/20260108-k3-clk-v5-3-42a11b74ad58@gentoo.org +Signed-off-by: Yixun Lan +(cherry picked from commit 3a086236c600739d6653c0405d86aff7d6f03c06) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu_common.h | 1 + + drivers/clk/spacemit/ccu_pll.c | 118 ++++++++++++++++++++++++++++++ + drivers/clk/spacemit/ccu_pll.h | 57 ++++++++++++--- + 3 files changed, 166 insertions(+), 10 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h +index 7ae244b5eace..8691698e007d 100644 +--- a/drivers/clk/spacemit/ccu_common.h ++++ b/drivers/clk/spacemit/ccu_common.h +@@ -26,6 +26,7 @@ struct ccu_common { + /* For PLL */ + struct { + u32 reg_swcr1; ++ u32 reg_swcr2; + u32 reg_swcr3; + }; + }; +diff --git a/drivers/clk/spacemit/ccu_pll.c b/drivers/clk/spacemit/ccu_pll.c +index 76d0244873d8..d4066a0ed452 100644 +--- a/drivers/clk/spacemit/ccu_pll.c ++++ b/drivers/clk/spacemit/ccu_pll.c +@@ -17,6 +17,9 @@ + #define PLL_SWCR3_EN ((u32)BIT(31)) + #define PLL_SWCR3_MASK GENMASK(30, 0) + ++#define PLLA_SWCR2_EN ((u32)BIT(16)) ++#define PLLA_SWCR2_MASK GENMASK(15, 8) ++ + static const struct ccu_pll_rate_tbl *ccu_pll_lookup_best_rate(struct ccu_pll *pll, + unsigned long rate) + { +@@ -148,6 +151,110 @@ static int ccu_pll_init(struct clk_hw *hw) + return 0; + } + ++static const struct ccu_pll_rate_tbl *ccu_plla_lookup_matched_entry(struct ccu_pll *pll) ++{ ++ struct ccu_pll_config *config = &pll->config; ++ const struct ccu_pll_rate_tbl *entry; ++ u32 i, swcr1, swcr2, swcr3; ++ ++ swcr1 = ccu_read(&pll->common, swcr1); ++ swcr2 = ccu_read(&pll->common, swcr2); ++ swcr2 &= PLLA_SWCR2_MASK; ++ swcr3 = ccu_read(&pll->common, swcr3); ++ ++ for (i = 0; i < config->tbl_num; i++) { ++ entry = &config->rate_tbl[i]; ++ ++ if (swcr1 == entry->swcr1 && ++ swcr2 == entry->swcr2 && ++ swcr3 == entry->swcr3) ++ return entry; ++ } ++ ++ return NULL; ++} ++ ++static void ccu_plla_update_param(struct ccu_pll *pll, const struct ccu_pll_rate_tbl *entry) ++{ ++ struct ccu_common *common = &pll->common; ++ ++ regmap_write(common->regmap, common->reg_swcr1, entry->swcr1); ++ regmap_write(common->regmap, common->reg_swcr3, entry->swcr3); ++ ccu_update(common, swcr2, PLLA_SWCR2_MASK, entry->swcr2); ++} ++ ++static int ccu_plla_is_enabled(struct clk_hw *hw) ++{ ++ struct ccu_common *common = hw_to_ccu_common(hw); ++ ++ return ccu_read(common, swcr2) & PLLA_SWCR2_EN; ++} ++ ++static int ccu_plla_enable(struct clk_hw *hw) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ struct ccu_common *common = &pll->common; ++ unsigned int tmp; ++ ++ ccu_update(common, swcr2, PLLA_SWCR2_EN, PLLA_SWCR2_EN); ++ ++ /* check lock status */ ++ return regmap_read_poll_timeout_atomic(common->lock_regmap, ++ pll->config.reg_lock, ++ tmp, ++ tmp & pll->config.mask_lock, ++ PLL_DELAY_US, PLL_TIMEOUT_US); ++} ++ ++static void ccu_plla_disable(struct clk_hw *hw) ++{ ++ struct ccu_common *common = hw_to_ccu_common(hw); ++ ++ ccu_update(common, swcr2, PLLA_SWCR2_EN, 0); ++} ++ ++/* ++ * PLLAs must be gated before changing rate, which is ensured by ++ * flag CLK_SET_RATE_GATE. ++ */ ++static int ccu_plla_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ const struct ccu_pll_rate_tbl *entry; ++ ++ entry = ccu_pll_lookup_best_rate(pll, rate); ++ ccu_plla_update_param(pll, entry); ++ ++ return 0; ++} ++ ++static unsigned long ccu_plla_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ const struct ccu_pll_rate_tbl *entry; ++ ++ entry = ccu_plla_lookup_matched_entry(pll); ++ ++ WARN_ON_ONCE(!entry); ++ ++ return entry ? entry->rate : 0; ++} ++ ++static int ccu_plla_init(struct clk_hw *hw) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ ++ if (ccu_plla_lookup_matched_entry(pll)) ++ return 0; ++ ++ ccu_plla_disable(hw); ++ ccu_plla_update_param(pll, &pll->config.rate_tbl[0]); ++ ++ return 0; ++} ++ + const struct clk_ops spacemit_ccu_pll_ops = { + .init = ccu_pll_init, + .enable = ccu_pll_enable, +@@ -158,3 +265,14 @@ const struct clk_ops spacemit_ccu_pll_ops = { + .is_enabled = ccu_pll_is_enabled, + }; + EXPORT_SYMBOL_NS_GPL(spacemit_ccu_pll_ops, "CLK_SPACEMIT"); ++ ++const struct clk_ops spacemit_ccu_plla_ops = { ++ .init = ccu_plla_init, ++ .enable = ccu_plla_enable, ++ .disable = ccu_plla_disable, ++ .set_rate = ccu_plla_set_rate, ++ .recalc_rate = ccu_plla_recalc_rate, ++ .determine_rate = ccu_pll_determine_rate, ++ .is_enabled = ccu_plla_is_enabled, ++}; ++EXPORT_SYMBOL_NS_GPL(spacemit_ccu_plla_ops, "CLK_SPACEMIT"); +diff --git a/drivers/clk/spacemit/ccu_pll.h b/drivers/clk/spacemit/ccu_pll.h +index 0592f4c3068c..e41db5c97c1a 100644 +--- a/drivers/clk/spacemit/ccu_pll.h ++++ b/drivers/clk/spacemit/ccu_pll.h +@@ -16,14 +16,31 @@ + * configuration. + * + * @rate: PLL rate +- * @swcr1: Register value of PLLX_SW1_CTRL (PLLx_SWCR1). +- * @swcr3: Register value of the PLLx_SW3_CTRL's lowest 31 bits of +- * PLLx_SW3_CTRL (PLLx_SWCR3). This highest bit is for enabling +- * the PLL and not contained in this field. ++ * @swcr1: Value of register PLLx_SW1_CTRL. ++ * @swcr2: Value of register PLLAx_SW2_CTRL. ++ * @swcr3: value of register PLLx_SW3_CTRL. ++ * ++ * See below tables for the register used in PPL/PPLA clocks ++ * ++ * Regular PLL type ++ * | Enable | swcr3 | PLLx_SW3_CTRL - BIT[31] | ++ * ----------------------------------------------- ++ * | Config | swcr1 | PLLx_SW1_CTRL - BIT[31:0] | ++ * | | swcr2 | Not used | ++ * | | swcr3 | PLLx_SW3_CTRL - BIT[30:0] | ++ * ++ * Special PLL type A ++ * | Enable | swcr2 | PLLAx_SW2_CTRL - BIT[16] | ++ * ----------------------------------------------- ++ * | Config | swcr1 | PLLAx_SW1_CTRL - BIT[31:0] | ++ * | | swcr2 | PLLAx_SW2_CTRL - BIT[15:8] | ++ * | | swcr3 | PLLAx_SW3_CTRL - BIT[31:0] | ++ * + */ + struct ccu_pll_rate_tbl { + unsigned long rate; + u32 swcr1; ++ u32 swcr2; + u32 swcr3; + }; + +@@ -36,11 +53,19 @@ struct ccu_pll_config { + + #define CCU_PLL_RATE(_rate, _swcr1, _swcr3) \ + { \ +- .rate = _rate, \ ++ .rate = _rate, \ + .swcr1 = _swcr1, \ + .swcr3 = _swcr3, \ + } + ++#define CCU_PLLA_RATE(_rate, _swcr1, _swcr2, _swcr3) \ ++ { \ ++ .rate = _rate, \ ++ .swcr1 = _swcr1, \ ++ .swcr2 = _swcr2, \ ++ .swcr3 = _swcr3, \ ++ } ++ + struct ccu_pll { + struct ccu_common common; + struct ccu_pll_config config; +@@ -54,26 +79,37 @@ struct ccu_pll { + .mask_lock = (_mask_lock), \ + } + +-#define CCU_PLL_HWINIT(_name, _flags) \ ++#define CCU_PLL_COMMON_HWINIT(_name, _ops, _flags) \ + (&(struct clk_init_data) { \ + .name = #_name, \ +- .ops = &spacemit_ccu_pll_ops, \ ++ .ops = _ops, \ + .parent_data = &(struct clk_parent_data) { .index = 0 }, \ + .num_parents = 1, \ + .flags = _flags, \ + }) + +-#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \ +- _mask_lock, _flags) \ ++#define CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ ++ _reg_lock, _mask_lock, _ops, _flags) \ + static struct ccu_pll _name = { \ + .config = CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock), \ + .common = { \ + .reg_swcr1 = _reg_swcr1, \ ++ .reg_swcr2 = _reg_swcr2, \ + .reg_swcr3 = _reg_swcr3, \ +- .hw.init = CCU_PLL_HWINIT(_name, _flags) \ ++ .hw.init = CCU_PLL_COMMON_HWINIT(_name, _ops, _flags) \ + } \ + } + ++#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \ ++ _mask_lock, _flags) \ ++ CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, 0, _reg_swcr3, \ ++ _reg_lock, _mask_lock, &spacemit_ccu_pll_ops, _flags) ++ ++#define CCU_PLLA_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ ++ _reg_lock, _mask_lock, _flags) \ ++ CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ ++ _reg_lock, _mask_lock, &spacemit_ccu_plla_ops, _flags) ++ + static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw) + { + struct ccu_common *common = hw_to_ccu_common(hw); +@@ -82,5 +118,6 @@ static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw) + } + + extern const struct clk_ops spacemit_ccu_pll_ops; ++extern const struct clk_ops spacemit_ccu_plla_ops; + + #endif +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0118-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch b/SPECS/linux-lts-kmhv2/0118-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch deleted file mode 100644 index 42dc66ad65..0000000000 --- a/SPECS/linux-lts-kmhv2/0118-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 316e5feca8326de2fcdcb6a5ad36fbdbf7b12758 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 19 Dec 2025 05:34:39 +0800 -Subject: [PATCH 118/467] UPSTREAM: reset: spacemit: fix auxiliary device id - -Due to the auxiliary register procedure moved to ccu common module where -the module name changed to spacemit_ccu, then the reset auxiliary device -register id also need to be adjusted in order to prepare for adding new -K3 reset driver, otherwise two reset drivers will claim to support same -"compatible" auxiliary device. - -In order to prevent the reset driver breakage, this commit is necessary -as a post-fix for changes introduced by two patches below, and should be -merged with them to make the patch series runtime bisectable. -("clk: spacemit: add platform SoC prefix to reset name") -("clk: spacemit: extract common ccu functions") - -Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-4-badf635993d3@gentoo.org -Acked-by: Philipp Zabel -Reviewed-by: Alex Elder -Signed-off-by: Yixun Lan -(cherry picked from commit ecff77f7c04141cc18ee2482936c96117060c0f2) -Signed-off-by: Han Gao ---- - drivers/reset/reset-spacemit.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/reset-spacemit.c -index e1272aff28f7..cc7fd1f8750d 100644 ---- a/drivers/reset/reset-spacemit.c -+++ b/drivers/reset/reset-spacemit.c -@@ -278,7 +278,7 @@ static int spacemit_reset_probe(struct auxiliary_device *adev, - - #define K1_AUX_DEV_ID(_unit) \ - { \ -- .name = "spacemit_ccu_k1." #_unit "-reset", \ -+ .name = "spacemit_ccu.k1-" #_unit "-reset", \ - .driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ - } - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch b/SPECS/linux-lts-kmhv2/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch new file mode 100644 index 0000000000..8ce677d1e4 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch @@ -0,0 +1,299 @@ +From 22c56093a5cbcc8d011f81d4523ee8160d5caa5f Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Sat, 20 Dec 2025 21:28:15 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: extract common header + +Extracting common header file, which will be shared by clock and reset +drivers. So will make it easy to add reset driver for K3 SoC later. + +Link: https://lore.kernel.org/r/20260108-k3-clk-v5-4-42a11b74ad58@gentoo.org +Signed-off-by: Yixun Lan +(cherry picked from commit 091d19cc24018f2bd783e932fb2403cb7a2bdb3c) +Signed-off-by: Han Gao +--- + include/soc/spacemit/k3-syscon.h | 273 +++++++++++++++++++++++++++++++ + 1 file changed, 273 insertions(+) + create mode 100644 include/soc/spacemit/k3-syscon.h + +diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h +new file mode 100644 +index 000000000000..0299bea065a0 +--- /dev/null ++++ b/include/soc/spacemit/k3-syscon.h +@@ -0,0 +1,273 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* SpacemiT clock and reset driver definitions for the K3 SoC */ ++ ++#ifndef __SOC_K3_SYSCON_H__ ++#define __SOC_K3_SYSCON_H__ ++ ++#include "ccu.h" ++ ++/* APBS register offset */ ++#define APBS_PLL1_SWCR1 0x100 ++#define APBS_PLL1_SWCR2 0x104 ++#define APBS_PLL1_SWCR3 0x108 ++#define APBS_PLL2_SWCR1 0x118 ++#define APBS_PLL2_SWCR2 0x11c ++#define APBS_PLL2_SWCR3 0x120 ++#define APBS_PLL3_SWCR1 0x124 ++#define APBS_PLL3_SWCR2 0x128 ++#define APBS_PLL3_SWCR3 0x12c ++#define APBS_PLL4_SWCR1 0x130 ++#define APBS_PLL4_SWCR2 0x134 ++#define APBS_PLL4_SWCR3 0x138 ++#define APBS_PLL5_SWCR1 0x13c ++#define APBS_PLL5_SWCR2 0x140 ++#define APBS_PLL5_SWCR3 0x144 ++#define APBS_PLL6_SWCR1 0x148 ++#define APBS_PLL6_SWCR2 0x14c ++#define APBS_PLL6_SWCR3 0x150 ++#define APBS_PLL7_SWCR1 0x158 ++#define APBS_PLL7_SWCR2 0x15c ++#define APBS_PLL7_SWCR3 0x160 ++#define APBS_PLL8_SWCR1 0x180 ++#define APBS_PLL8_SWCR2 0x184 ++#define APBS_PLL8_SWCR3 0x188 ++ ++/* MPMU register offset */ ++#define MPMU_FCCR 0x0008 ++#define MPMU_POSR 0x0010 ++#define POSR_PLL1_LOCK BIT(24) ++#define POSR_PLL2_LOCK BIT(25) ++#define POSR_PLL3_LOCK BIT(26) ++#define POSR_PLL4_LOCK BIT(27) ++#define POSR_PLL5_LOCK BIT(28) ++#define POSR_PLL6_LOCK BIT(29) ++#define POSR_PLL7_LOCK BIT(30) ++#define POSR_PLL8_LOCK BIT(31) ++#define MPMU_SUCCR 0x0014 ++#define MPMU_ISCCR 0x0044 ++#define MPMU_WDTPCR 0x0200 ++#define MPMU_RIPCCR 0x0210 ++#define MPMU_ACGR 0x1024 ++#define MPMU_APBCSCR 0x1050 ++#define MPMU_SUCCR_1 0x10b0 ++ ++#define MPMU_I2S0_SYSCLK 0x1100 ++#define MPMU_I2S2_SYSCLK 0x1104 ++#define MPMU_I2S3_SYSCLK 0x1108 ++#define MPMU_I2S4_SYSCLK 0x110c ++#define MPMU_I2S5_SYSCLK 0x1110 ++#define MPMU_I2S_SYSCLK_CTRL 0x1114 ++ ++/* APBC register offset */ ++#define APBC_UART0_CLK_RST 0x00 ++#define APBC_UART2_CLK_RST 0x04 ++#define APBC_GPIO_CLK_RST 0x08 ++#define APBC_PWM0_CLK_RST 0x0c ++#define APBC_PWM1_CLK_RST 0x10 ++#define APBC_PWM2_CLK_RST 0x14 ++#define APBC_PWM3_CLK_RST 0x18 ++#define APBC_TWSI8_CLK_RST 0x20 ++#define APBC_UART3_CLK_RST 0x24 ++#define APBC_RTC_CLK_RST 0x28 ++#define APBC_TWSI0_CLK_RST 0x2c ++#define APBC_TWSI1_CLK_RST 0x30 ++#define APBC_TIMERS0_CLK_RST 0x34 ++#define APBC_TWSI2_CLK_RST 0x38 ++#define APBC_AIB_CLK_RST 0x3c ++#define APBC_TWSI4_CLK_RST 0x40 ++#define APBC_TIMERS1_CLK_RST 0x44 ++#define APBC_ONEWIRE_CLK_RST 0x48 ++#define APBC_TWSI5_CLK_RST 0x4c ++#define APBC_DRO_CLK_RST 0x58 ++#define APBC_IR0_CLK_RST 0x5c ++#define APBC_IR1_CLK_RST 0x1c ++#define APBC_TWSI6_CLK_RST 0x60 ++#define APBC_COUNTER_CLK_SEL 0x64 ++#define APBC_TSEN_CLK_RST 0x6c ++#define APBC_UART4_CLK_RST 0x70 ++#define APBC_UART5_CLK_RST 0x74 ++#define APBC_UART6_CLK_RST 0x78 ++#define APBC_SSP3_CLK_RST 0x7c ++#define APBC_SSPA0_CLK_RST 0x80 ++#define APBC_SSPA1_CLK_RST 0x84 ++#define APBC_SSPA2_CLK_RST 0x88 ++#define APBC_SSPA3_CLK_RST 0x8c ++#define APBC_IPC_AP2AUD_CLK_RST 0x90 ++#define APBC_UART7_CLK_RST 0x94 ++#define APBC_UART8_CLK_RST 0x98 ++#define APBC_UART9_CLK_RST 0x9c ++#define APBC_CAN0_CLK_RST 0xa0 ++#define APBC_CAN1_CLK_RST 0xa4 ++#define APBC_PWM4_CLK_RST 0xa8 ++#define APBC_PWM5_CLK_RST 0xac ++#define APBC_PWM6_CLK_RST 0xb0 ++#define APBC_PWM7_CLK_RST 0xb4 ++#define APBC_PWM8_CLK_RST 0xb8 ++#define APBC_PWM9_CLK_RST 0xbc ++#define APBC_PWM10_CLK_RST 0xc0 ++#define APBC_PWM11_CLK_RST 0xc4 ++#define APBC_PWM12_CLK_RST 0xc8 ++#define APBC_PWM13_CLK_RST 0xcc ++#define APBC_PWM14_CLK_RST 0xd0 ++#define APBC_PWM15_CLK_RST 0xd4 ++#define APBC_PWM16_CLK_RST 0xd8 ++#define APBC_PWM17_CLK_RST 0xdc ++#define APBC_PWM18_CLK_RST 0xe0 ++#define APBC_PWM19_CLK_RST 0xe4 ++#define APBC_TIMERS2_CLK_RST 0x11c ++#define APBC_TIMERS3_CLK_RST 0x120 ++#define APBC_TIMERS4_CLK_RST 0x124 ++#define APBC_TIMERS5_CLK_RST 0x128 ++#define APBC_TIMERS6_CLK_RST 0x12c ++#define APBC_TIMERS7_CLK_RST 0x130 ++ ++#define APBC_CAN2_CLK_RST 0x148 ++#define APBC_CAN3_CLK_RST 0x14c ++#define APBC_CAN4_CLK_RST 0x150 ++#define APBC_UART10_CLK_RST 0x154 ++#define APBC_SSP0_CLK_RST 0x158 ++#define APBC_SSP1_CLK_RST 0x15c ++#define APBC_SSPA4_CLK_RST 0x160 ++#define APBC_SSPA5_CLK_RST 0x164 ++ ++/* APMU register offset */ ++#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 ++#define APMU_ISP_CLK_RES_CTRL 0x038 ++#define APMU_PMU_CLK_GATE_CTRL 0x040 ++#define APMU_LCD_CLK_RES_CTRL1 0x044 ++#define APMU_LCD_SPI_CLK_RES_CTRL 0x048 ++#define APMU_LCD_CLK_RES_CTRL2 0x04c ++#define APMU_CCIC_CLK_RES_CTRL 0x050 ++#define APMU_SDH0_CLK_RES_CTRL 0x054 ++#define APMU_SDH1_CLK_RES_CTRL 0x058 ++#define APMU_USB_CLK_RES_CTRL 0x05c ++#define APMU_QSPI_CLK_RES_CTRL 0x060 ++#define APMU_DMA_CLK_RES_CTRL 0x064 ++#define APMU_AES_CLK_RES_CTRL 0x068 ++#define APMU_MCB_CLK_RES_CTRL 0x06c ++#define APMU_VPU_CLK_RES_CTRL 0x0a4 ++#define APMU_DTC_CLK_RES_CTRL 0x0ac ++#define APMU_GPU_CLK_RES_CTRL 0x0cc ++#define APMU_SDH2_CLK_RES_CTRL 0x0e0 ++#define APMU_PMUA_MC_CTRL 0x0e8 ++#define APMU_PMU_CC2_AP 0x100 ++#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 ++#define APMU_UCIE_CTRL 0x11c ++#define APMU_RCPU_CLK_RES_CTRL 0x14c ++#define APMU_TOP_DCLK_CTRL 0x158 ++#define APMU_LCD_EDP_CTRL 0x23c ++#define APMU_UFS_CLK_RES_CTRL 0x268 ++#define APMU_LCD_CLK_RES_CTRL3 0x26c ++#define APMU_LCD_CLK_RES_CTRL4 0x270 ++#define APMU_LCD_CLK_RES_CTRL5 0x274 ++#define APMU_CCI550_CLK_CTRL 0x300 ++#define APMU_ACLK_CLK_CTRL 0x388 ++#define APMU_CPU_C0_CLK_CTRL 0x38C ++#define APMU_CPU_C1_CLK_CTRL 0x390 ++#define APMU_CPU_C2_CLK_CTRL 0x394 ++#define APMU_CPU_C3_CLK_CTRL 0x208 ++#define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 ++#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 ++#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 ++#define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 ++#define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 ++#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 ++#define APMU_EMAC1_CLK_RES_CTRL 0x3ec ++#define APMU_EMAC2_CLK_RES_CTRL 0x248 ++#define APMU_ESPI_CLK_RES_CTRL 0x240 ++#define APMU_SNR_ISIM_VCLK_CTRL 0x3f8 ++ ++/* DCIU register offsets */ ++#define DCIU_DMASYS_CLK_EN 0x234 ++#define DCIU_DMASYS_SDMA_CLK_EN 0x238 ++#define DCIU_C2_TCM_PIPE_CLK 0x244 ++#define DCIU_C3_TCM_PIPE_CLK 0x248 ++ ++#define DCIU_DMASYS_S0_RSTN 0x204 ++#define DCIU_DMASYS_S1_RSTN 0x208 ++#define DCIU_DMASYS_A0_RSTN 0x20C ++#define DCIU_DMASYS_A1_RSTN 0x210 ++#define DCIU_DMASYS_A2_RSTN 0x214 ++#define DCIU_DMASYS_A3_RSTN 0x218 ++#define DCIU_DMASYS_A4_RSTN 0x21C ++#define DCIU_DMASYS_A5_RSTN 0x220 ++#define DCIU_DMASYS_A6_RSTN 0x224 ++#define DCIU_DMASYS_A7_RSTN 0x228 ++#define DCIU_DMASYS_RSTN 0x22C ++#define DCIU_DMASYS_SDMA_RSTN 0x230 ++ ++/* RCPU SYSCTRL register offsets */ ++#define RCPU_CAN_CLK_RST 0x4c ++#define RCPU_CAN1_CLK_RST 0xF0 ++#define RCPU_CAN2_CLK_RST 0xF4 ++#define RCPU_CAN3_CLK_RST 0xF8 ++#define RCPU_CAN4_CLK_RST 0xFC ++#define RCPU_IRC_CLK_RST 0x48 ++#define RCPU_IRC1_CLK_RST 0xEC ++#define RCPU_GMAC_CLK_RST 0xE4 ++#define RCPU_ESPI_CLK_RST 0xDC ++#define RCPU_AUDIO_I2S0_SYS_CLK_CTRL 0x70 ++#define RCPU_AUDIO_I2S1_SYS_CLK_CTRL 0x44 ++ ++/* RCPU UARTCTRL register offsets */ ++#define RCPU1_UART0_CLK_RST 0x00 ++#define RCPU1_UART1_CLK_RST 0x04 ++#define RCPU1_UART2_CLK_RST 0x08 ++#define RCPU1_UART3_CLK_RST 0x0c ++#define RCPU1_UART4_CLK_RST 0x10 ++#define RCPU1_UART5_CLK_RST 0x14 ++ ++/* RCPU I2SCTRL register offsets */ ++#define RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL 0x60 ++#define RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL 0x64 ++#define RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL 0x68 ++#define RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL 0x6C ++ ++#define RCPU2_AUDIO_I2S2_SYS_CLK_CTRL 0x44 ++#define RCPU2_AUDIO_I2S3_SYS_CLK_CTRL 0x54 ++ ++/* RCPU SPICTRL register offsets */ ++#define RCPU3_SSP0_CLK_RST 0x00 ++#define RCPU3_SSP1_CLK_RST 0x04 ++#define RCPU3_PWR_SSP_CLK_RST 0x08 ++ ++/* RCPU I2CCTRL register offsets */ ++#define RCPU4_I2C0_CLK_RST 0x00 ++#define RCPU4_I2C1_CLK_RST 0x04 ++#define RCPU4_PWR_I2C_CLK_RST 0x08 ++ ++/* RPMU register offsets */ ++#define RCPU5_AON_PER_CLK_RST_CTRL 0x2C ++#define RCPU5_TIMER1_CLK_RST 0x4C ++#define RCPU5_TIMER2_CLK_RST 0x70 ++#define RCPU5_TIMER3_CLK_RST 0x78 ++#define RCPU5_TIMER4_CLK_RST 0x7C ++#define RCPU5_GPIO_AND_EDGE_CLK_RST 0x74 ++#define RCPU5_RCPU_BUS_CLK_CTRL 0xC0 ++#define RCPU5_RT24_CORE0_CLK_CTRL 0xC4 ++#define RCPU5_RT24_CORE1_CLK_CTRL 0xC8 ++#define RCPU5_RT24_CORE0_SW_RESET 0xCC ++#define RCPU5_RT24_CORE1_SW_RESET 0xD0 ++ ++/* RCPU PWMCTRL register offsets */ ++#define RCPU6_PWM0_CLK_RST 0x00 ++#define RCPU6_PWM1_CLK_RST 0x04 ++#define RCPU6_PWM2_CLK_RST 0x08 ++#define RCPU6_PWM3_CLK_RST 0x0c ++#define RCPU6_PWM4_CLK_RST 0x10 ++#define RCPU6_PWM5_CLK_RST 0x14 ++#define RCPU6_PWM6_CLK_RST 0x18 ++#define RCPU6_PWM7_CLK_RST 0x1c ++#define RCPU6_PWM8_CLK_RST 0x20 ++#define RCPU6_PWM9_CLK_RST 0x24 ++ ++/* APBC2 SEC register offsets */ ++#define APBC2_UART1_CLK_RST 0x00 ++#define APBC2_SSP2_CLK_RST 0x04 ++#define APBC2_TWSI3_CLK_RST 0x08 ++#define APBC2_RTC_CLK_RST 0x0c ++#define APBC2_TIMERS_CLK_RST 0x10 ++#define APBC2_GPIO_CLK_RST 0x1c ++ ++#endif /* __SOC_K3_SYSCON_H__ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0119-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch b/SPECS/linux-lts-kmhv2/0119-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch deleted file mode 100644 index 5b56ed2c06..0000000000 --- a/SPECS/linux-lts-kmhv2/0119-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch +++ /dev/null @@ -1,519 +0,0 @@ -From 57bc7378dba997a6f4714c6180bf65bbaf53dccb Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sat, 1 Nov 2025 20:56:42 +0800 -Subject: [PATCH 119/467] UPSTREAM: dt-bindings: soc: spacemit: k3: add clock - support - -Add compatible strings for clock drivers to support Spacemit K3 SoC, -also includes all the defined clock IDs. - -The SpacemiT K3 SoC clock IP is scattered over several different blocks, -which are APBC, APBS, APMU, DCIU, MPMU, all of them are capable of -generating clock and reset signals. APMU and MPMU have additional Power -Domain management functionality. - -Following is a brief list that shows devices managed in each block: - -APBC: UART, GPIO, PWM, SPI, TIMER, I2S, IR, DR, TSEN, IPC, CAN -APBS: various PPL clocks control -APMU: CCI, CPU, CSI, ISP, LCD, USB, QSPI, DMA, VPU, GPU, DSI, PCIe, EMAC.. -DCID: SRAM, DMA, TCM -MPMU: various PLL1 derived clocks, UART, WATCHDOG, I2S - -Link: https://lore.kernel.org/r/20260108-k3-clk-v5-1-42a11b74ad58@gentoo.org -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Yixun Lan -(cherry picked from commit efe897b557e211a09f51d749eae5eca933e8bf56) -Signed-off-by: Han Gao ---- - .../bindings/clock/spacemit,k1-pll.yaml | 9 +- - .../soc/spacemit/spacemit,k1-syscon.yaml | 14 +- - .../dt-bindings/clock/spacemit,k3-clocks.h | 390 ++++++++++++++++++ - 3 files changed, 408 insertions(+), 5 deletions(-) - create mode 100644 include/dt-bindings/clock/spacemit,k3-clocks.h - -diff --git a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml -index 06bafd68c00a..cddf6a56dac0 100644 ---- a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml -+++ b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml -@@ -4,14 +4,16 @@ - $id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml# - $schema: http://devicetree.org/meta-schemas/core.yaml# - --title: SpacemiT K1 PLL -+title: SpacemiT K1/K3 PLL - - maintainers: - - Haylen Chu - - properties: - compatible: -- const: spacemit,k1-pll -+ enum: -+ - spacemit,k1-pll -+ - spacemit,k3-pll - - reg: - maxItems: 1 -@@ -28,7 +30,8 @@ properties: - "#clock-cells": - const: 1 - description: -- See for valid indices. -+ For K1 SoC, check for valid indices. -+ For K3 SoC, check for valid indices. - - required: - - compatible -diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml -index 133a391ee68c..d87131da30bc 100644 ---- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml -+++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml -@@ -4,7 +4,7 @@ - $id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml# - $schema: http://devicetree.org/meta-schemas/core.yaml# - --title: SpacemiT K1 SoC System Controller -+title: SpacemiT K1/K3 SoC System Controller - - maintainers: - - Haylen Chu -@@ -22,6 +22,10 @@ properties: - - spacemit,k1-syscon-rcpu - - spacemit,k1-syscon-rcpu2 - - spacemit,k1-syscon-apbc2 -+ - spacemit,k3-syscon-apbc -+ - spacemit,k3-syscon-apmu -+ - spacemit,k3-syscon-dciu -+ - spacemit,k3-syscon-mpmu - - reg: - maxItems: 1 -@@ -39,7 +43,8 @@ properties: - "#clock-cells": - const: 1 - description: -- See for valid indices. -+ For K1 SoC, check for valid indices. -+ For K3 SoC, check for valid indices. - - "#power-domain-cells": - const: 1 -@@ -60,6 +65,8 @@ allOf: - enum: - - spacemit,k1-syscon-apmu - - spacemit,k1-syscon-mpmu -+ - spacemit,k3-syscon-apmu -+ - spacemit,k3-syscon-mpmu - then: - required: - - "#power-domain-cells" -@@ -74,6 +81,9 @@ allOf: - - spacemit,k1-syscon-apbc - - spacemit,k1-syscon-apmu - - spacemit,k1-syscon-mpmu -+ - spacemit,k3-syscon-apbc -+ - spacemit,k3-syscon-apmu -+ - spacemit,k3-syscon-mpmu - then: - required: - - clocks -diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h -new file mode 100644 -index 000000000000..b22336f3ae40 ---- /dev/null -+++ b/include/dt-bindings/clock/spacemit,k3-clocks.h -@@ -0,0 +1,390 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd -+ */ -+ -+#ifndef _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ -+#define _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ -+ -+/* APBS (PLL) clocks */ -+#define CLK_PLL1 0 -+#define CLK_PLL2 1 -+#define CLK_PLL3 2 -+#define CLK_PLL4 3 -+#define CLK_PLL5 4 -+#define CLK_PLL6 5 -+#define CLK_PLL7 6 -+#define CLK_PLL8 7 -+#define CLK_PLL1_D2 8 -+#define CLK_PLL1_D3 9 -+#define CLK_PLL1_D4 10 -+#define CLK_PLL1_D5 11 -+#define CLK_PLL1_D6 12 -+#define CLK_PLL1_D7 13 -+#define CLK_PLL1_D8 14 -+#define CLK_PLL1_DX 15 -+#define CLK_PLL1_D64 16 -+#define CLK_PLL1_D10_AUD 17 -+#define CLK_PLL1_D100_AUD 18 -+#define CLK_PLL2_D1 19 -+#define CLK_PLL2_D2 20 -+#define CLK_PLL2_D3 21 -+#define CLK_PLL2_D4 22 -+#define CLK_PLL2_D5 23 -+#define CLK_PLL2_D6 24 -+#define CLK_PLL2_D7 25 -+#define CLK_PLL2_D8 26 -+#define CLK_PLL2_66 27 -+#define CLK_PLL2_33 28 -+#define CLK_PLL2_50 29 -+#define CLK_PLL2_25 30 -+#define CLK_PLL2_20 31 -+#define CLK_PLL2_D24_125 32 -+#define CLK_PLL2_D120_25 33 -+#define CLK_PLL3_D1 34 -+#define CLK_PLL3_D2 35 -+#define CLK_PLL3_D3 36 -+#define CLK_PLL3_D4 37 -+#define CLK_PLL3_D5 38 -+#define CLK_PLL3_D6 39 -+#define CLK_PLL3_D7 40 -+#define CLK_PLL3_D8 41 -+#define CLK_PLL4_D1 42 -+#define CLK_PLL4_D2 43 -+#define CLK_PLL4_D3 44 -+#define CLK_PLL4_D4 45 -+#define CLK_PLL4_D5 46 -+#define CLK_PLL4_D6 47 -+#define CLK_PLL4_D7 48 -+#define CLK_PLL4_D8 49 -+#define CLK_PLL5_D1 50 -+#define CLK_PLL5_D2 51 -+#define CLK_PLL5_D3 52 -+#define CLK_PLL5_D4 53 -+#define CLK_PLL5_D5 54 -+#define CLK_PLL5_D6 55 -+#define CLK_PLL5_D7 56 -+#define CLK_PLL5_D8 57 -+#define CLK_PLL6_D1 58 -+#define CLK_PLL6_D2 59 -+#define CLK_PLL6_D3 60 -+#define CLK_PLL6_D4 61 -+#define CLK_PLL6_D5 62 -+#define CLK_PLL6_D6 63 -+#define CLK_PLL6_D7 64 -+#define CLK_PLL6_D8 65 -+#define CLK_PLL6_80 66 -+#define CLK_PLL6_40 67 -+#define CLK_PLL6_20 68 -+#define CLK_PLL7_D1 69 -+#define CLK_PLL7_D2 70 -+#define CLK_PLL7_D3 71 -+#define CLK_PLL7_D4 72 -+#define CLK_PLL7_D5 73 -+#define CLK_PLL7_D6 74 -+#define CLK_PLL7_D7 75 -+#define CLK_PLL7_D8 76 -+#define CLK_PLL8_D1 77 -+#define CLK_PLL8_D2 78 -+#define CLK_PLL8_D3 79 -+#define CLK_PLL8_D4 80 -+#define CLK_PLL8_D5 81 -+#define CLK_PLL8_D6 82 -+#define CLK_PLL8_D7 83 -+#define CLK_PLL8_D8 84 -+ -+/* MPMU clocks */ -+#define CLK_MPMU_PLL1_307P2 0 -+#define CLK_MPMU_PLL1_76P8 1 -+#define CLK_MPMU_PLL1_61P44 2 -+#define CLK_MPMU_PLL1_153P6 3 -+#define CLK_MPMU_PLL1_102P4 4 -+#define CLK_MPMU_PLL1_51P2 5 -+#define CLK_MPMU_PLL1_51P2_AP 6 -+#define CLK_MPMU_PLL1_57P6 7 -+#define CLK_MPMU_PLL1_25P6 8 -+#define CLK_MPMU_PLL1_12P8 9 -+#define CLK_MPMU_PLL1_12P8_WDT 10 -+#define CLK_MPMU_PLL1_6P4 11 -+#define CLK_MPMU_PLL1_3P2 12 -+#define CLK_MPMU_PLL1_1P6 13 -+#define CLK_MPMU_PLL1_0P8 14 -+#define CLK_MPMU_PLL1_409P6 15 -+#define CLK_MPMU_PLL1_204P8 16 -+#define CLK_MPMU_PLL1_491 17 -+#define CLK_MPMU_PLL1_245P76 18 -+#define CLK_MPMU_PLL1_614 19 -+#define CLK_MPMU_PLL1_47P26 20 -+#define CLK_MPMU_PLL1_31P5 21 -+#define CLK_MPMU_PLL1_819 22 -+#define CLK_MPMU_PLL1_1228 23 -+#define CLK_MPMU_APB 24 -+#define CLK_MPMU_SLOW_UART 25 -+#define CLK_MPMU_SLOW_UART1 26 -+#define CLK_MPMU_SLOW_UART2 27 -+#define CLK_MPMU_WDT 28 -+#define CLK_MPMU_WDT_BUS 29 -+#define CLK_MPMU_RIPC 30 -+#define CLK_MPMU_I2S_153P6 31 -+#define CLK_MPMU_I2S_153P6_BASE 32 -+#define CLK_MPMU_I2S_SYSCLK_SRC 33 -+#define CLK_MPMU_I2S1_SYSCLK 34 -+#define CLK_MPMU_I2S_BCLK 35 -+#define CLK_MPMU_I2S0_SYSCLK_SEL 36 -+#define CLK_MPMU_I2S2_SYSCLK_SEL 37 -+#define CLK_MPMU_I2S3_SYSCLK_SEL 38 -+#define CLK_MPMU_I2S4_SYSCLK_SEL 39 -+#define CLK_MPMU_I2S5_SYSCLK_SEL 40 -+#define CLK_MPMU_I2S0_SYSCLK_DIV 41 -+#define CLK_MPMU_I2S2_SYSCLK_DIV 42 -+#define CLK_MPMU_I2S3_SYSCLK_DIV 43 -+#define CLK_MPMU_I2S4_SYSCLK_DIV 44 -+#define CLK_MPMU_I2S5_SYSCLK_DIV 45 -+#define CLK_MPMU_I2S0_SYSCLK 46 -+#define CLK_MPMU_I2S2_SYSCLK 47 -+#define CLK_MPMU_I2S3_SYSCLK 48 -+#define CLK_MPMU_I2S4_SYSCLK 49 -+#define CLK_MPMU_I2S5_SYSCLK 50 -+ -+/* APBC clocks */ -+#define CLK_APBC_UART0 0 -+#define CLK_APBC_UART2 1 -+#define CLK_APBC_UART3 2 -+#define CLK_APBC_UART4 3 -+#define CLK_APBC_UART5 4 -+#define CLK_APBC_UART6 5 -+#define CLK_APBC_UART7 6 -+#define CLK_APBC_UART8 7 -+#define CLK_APBC_UART9 8 -+#define CLK_APBC_UART10 9 -+#define CLK_APBC_UART0_BUS 10 -+#define CLK_APBC_UART2_BUS 11 -+#define CLK_APBC_UART3_BUS 12 -+#define CLK_APBC_UART4_BUS 13 -+#define CLK_APBC_UART5_BUS 14 -+#define CLK_APBC_UART6_BUS 15 -+#define CLK_APBC_UART7_BUS 16 -+#define CLK_APBC_UART8_BUS 17 -+#define CLK_APBC_UART9_BUS 18 -+#define CLK_APBC_UART10_BUS 19 -+#define CLK_APBC_GPIO 20 -+#define CLK_APBC_GPIO_BUS 21 -+#define CLK_APBC_PWM0 22 -+#define CLK_APBC_PWM1 23 -+#define CLK_APBC_PWM2 24 -+#define CLK_APBC_PWM3 25 -+#define CLK_APBC_PWM4 26 -+#define CLK_APBC_PWM5 27 -+#define CLK_APBC_PWM6 28 -+#define CLK_APBC_PWM7 29 -+#define CLK_APBC_PWM8 30 -+#define CLK_APBC_PWM9 31 -+#define CLK_APBC_PWM10 32 -+#define CLK_APBC_PWM11 33 -+#define CLK_APBC_PWM12 34 -+#define CLK_APBC_PWM13 35 -+#define CLK_APBC_PWM14 36 -+#define CLK_APBC_PWM15 37 -+#define CLK_APBC_PWM16 38 -+#define CLK_APBC_PWM17 39 -+#define CLK_APBC_PWM18 40 -+#define CLK_APBC_PWM19 41 -+#define CLK_APBC_PWM0_BUS 42 -+#define CLK_APBC_PWM1_BUS 43 -+#define CLK_APBC_PWM2_BUS 44 -+#define CLK_APBC_PWM3_BUS 45 -+#define CLK_APBC_PWM4_BUS 46 -+#define CLK_APBC_PWM5_BUS 47 -+#define CLK_APBC_PWM6_BUS 48 -+#define CLK_APBC_PWM7_BUS 49 -+#define CLK_APBC_PWM8_BUS 50 -+#define CLK_APBC_PWM9_BUS 51 -+#define CLK_APBC_PWM10_BUS 52 -+#define CLK_APBC_PWM11_BUS 53 -+#define CLK_APBC_PWM12_BUS 54 -+#define CLK_APBC_PWM13_BUS 55 -+#define CLK_APBC_PWM14_BUS 56 -+#define CLK_APBC_PWM15_BUS 57 -+#define CLK_APBC_PWM16_BUS 58 -+#define CLK_APBC_PWM17_BUS 59 -+#define CLK_APBC_PWM18_BUS 60 -+#define CLK_APBC_PWM19_BUS 61 -+#define CLK_APBC_SPI0_I2S_BCLK 62 -+#define CLK_APBC_SPI1_I2S_BCLK 63 -+#define CLK_APBC_SPI3_I2S_BCLK 64 -+#define CLK_APBC_SPI0 65 -+#define CLK_APBC_SPI1 66 -+#define CLK_APBC_SPI3 67 -+#define CLK_APBC_SPI0_BUS 68 -+#define CLK_APBC_SPI1_BUS 69 -+#define CLK_APBC_SPI3_BUS 70 -+#define CLK_APBC_RTC 71 -+#define CLK_APBC_RTC_BUS 72 -+#define CLK_APBC_TWSI0 73 -+#define CLK_APBC_TWSI1 74 -+#define CLK_APBC_TWSI2 75 -+#define CLK_APBC_TWSI4 76 -+#define CLK_APBC_TWSI5 77 -+#define CLK_APBC_TWSI6 78 -+#define CLK_APBC_TWSI8 79 -+#define CLK_APBC_TWSI0_BUS 80 -+#define CLK_APBC_TWSI1_BUS 81 -+#define CLK_APBC_TWSI2_BUS 82 -+#define CLK_APBC_TWSI4_BUS 83 -+#define CLK_APBC_TWSI5_BUS 84 -+#define CLK_APBC_TWSI6_BUS 85 -+#define CLK_APBC_TWSI8_BUS 86 -+#define CLK_APBC_TIMERS0 87 -+#define CLK_APBC_TIMERS1 88 -+#define CLK_APBC_TIMERS2 89 -+#define CLK_APBC_TIMERS3 90 -+#define CLK_APBC_TIMERS4 91 -+#define CLK_APBC_TIMERS5 92 -+#define CLK_APBC_TIMERS6 93 -+#define CLK_APBC_TIMERS7 94 -+#define CLK_APBC_TIMERS0_BUS 95 -+#define CLK_APBC_TIMERS1_BUS 96 -+#define CLK_APBC_TIMERS2_BUS 97 -+#define CLK_APBC_TIMERS3_BUS 98 -+#define CLK_APBC_TIMERS4_BUS 99 -+#define CLK_APBC_TIMERS5_BUS 100 -+#define CLK_APBC_TIMERS6_BUS 101 -+#define CLK_APBC_TIMERS7_BUS 102 -+#define CLK_APBC_AIB 103 -+#define CLK_APBC_AIB_BUS 104 -+#define CLK_APBC_ONEWIRE 105 -+#define CLK_APBC_ONEWIRE_BUS 106 -+#define CLK_APBC_I2S0_BCLK 107 -+#define CLK_APBC_I2S1_BCLK 108 -+#define CLK_APBC_I2S2_BCLK 109 -+#define CLK_APBC_I2S3_BCLK 110 -+#define CLK_APBC_I2S4_BCLK 111 -+#define CLK_APBC_I2S5_BCLK 112 -+#define CLK_APBC_I2S0 113 -+#define CLK_APBC_I2S1 114 -+#define CLK_APBC_I2S2 115 -+#define CLK_APBC_I2S3 116 -+#define CLK_APBC_I2S4 117 -+#define CLK_APBC_I2S5 118 -+#define CLK_APBC_I2S0_BUS 119 -+#define CLK_APBC_I2S1_BUS 120 -+#define CLK_APBC_I2S2_BUS 121 -+#define CLK_APBC_I2S3_BUS 122 -+#define CLK_APBC_I2S4_BUS 123 -+#define CLK_APBC_I2S5_BUS 124 -+#define CLK_APBC_DRO 125 -+#define CLK_APBC_IR0 126 -+#define CLK_APBC_IR1 127 -+#define CLK_APBC_TSEN 128 -+#define CLK_APBC_TSEN_BUS 129 -+#define CLK_APBC_IPC_AP2RCPU 130 -+#define CLK_APBC_IPC_AP2RCPU_BUS 131 -+#define CLK_APBC_CAN0 132 -+#define CLK_APBC_CAN1 133 -+#define CLK_APBC_CAN2 134 -+#define CLK_APBC_CAN3 135 -+#define CLK_APBC_CAN4 136 -+#define CLK_APBC_CAN0_BUS 137 -+#define CLK_APBC_CAN1_BUS 138 -+#define CLK_APBC_CAN2_BUS 139 -+#define CLK_APBC_CAN3_BUS 140 -+#define CLK_APBC_CAN4_BUS 141 -+ -+/* APMU clocks */ -+#define CLK_APMU_AXICLK 0 -+#define CLK_APMU_CCI550 1 -+#define CLK_APMU_CPU_C0_CORE 2 -+#define CLK_APMU_CPU_C1_CORE 3 -+#define CLK_APMU_CPU_C2_CORE 4 -+#define CLK_APMU_CPU_C3_CORE 5 -+#define CLK_APMU_CCIC2PHY 6 -+#define CLK_APMU_CCIC3PHY 7 -+#define CLK_APMU_CSI 8 -+#define CLK_APMU_ISP_BUS 9 -+#define CLK_APMU_D1P_1228P8 10 -+#define CLK_APMU_D1P_819P2 11 -+#define CLK_APMU_D1P_614P4 12 -+#define CLK_APMU_D1P_491P52 13 -+#define CLK_APMU_D1P_409P6 14 -+#define CLK_APMU_D1P_307P2 15 -+#define CLK_APMU_D1P_245P76 16 -+#define CLK_APMU_V2D 17 -+#define CLK_APMU_DSI_ESC 18 -+#define CLK_APMU_LCD_HCLK 19 -+#define CLK_APMU_LCD_DSC 20 -+#define CLK_APMU_LCD_PXCLK 21 -+#define CLK_APMU_LCD_MCLK 22 -+#define CLK_APMU_CCIC_4X 23 -+#define CLK_APMU_CCIC1PHY 24 -+#define CLK_APMU_SC2_HCLK 25 -+#define CLK_APMU_SDH_AXI 26 -+#define CLK_APMU_SDH0 27 -+#define CLK_APMU_SDH1 28 -+#define CLK_APMU_SDH2 29 -+#define CLK_APMU_USB2_BUS 30 -+#define CLK_APMU_USB3_PORTA_BUS 31 -+#define CLK_APMU_USB3_PORTB_BUS 32 -+#define CLK_APMU_USB3_PORTC_BUS 33 -+#define CLK_APMU_USB3_PORTD_BUS 34 -+#define CLK_APMU_QSPI 35 -+#define CLK_APMU_QSPI_BUS 36 -+#define CLK_APMU_DMA 37 -+#define CLK_APMU_AES_WTM 38 -+#define CLK_APMU_VPU 39 -+#define CLK_APMU_DTC 40 -+#define CLK_APMU_GPU 41 -+#define CLK_APMU_MC_AHB 42 -+#define CLK_APMU_TOP_DCLK 43 -+#define CLK_APMU_UCIE 44 -+#define CLK_APMU_UCIE_SBCLK 45 -+#define CLK_APMU_RCPU 46 -+#define CLK_APMU_DSI4LN2_DSI_ESC 47 -+#define CLK_APMU_DSI4LN2_LCD_DSC 48 -+#define CLK_APMU_DSI4LN2_LCD_PXCLK 49 -+#define CLK_APMU_DSI4LN2_LCD_MCLK 50 -+#define CLK_APMU_DSI4LN2_DPU_ACLK 51 -+#define CLK_APMU_DPU_ACLK 52 -+#define CLK_APMU_UFS_ACLK 53 -+#define CLK_APMU_EDP0_PXCLK 54 -+#define CLK_APMU_EDP1_PXCLK 55 -+#define CLK_APMU_PCIE_PORTA_MSTE 56 -+#define CLK_APMU_PCIE_PORTA_SLV 57 -+#define CLK_APMU_PCIE_PORTB_MSTE 58 -+#define CLK_APMU_PCIE_PORTB_SLV 59 -+#define CLK_APMU_PCIE_PORTC_MSTE 60 -+#define CLK_APMU_PCIE_PORTC_SLV 61 -+#define CLK_APMU_PCIE_PORTD_MSTE 62 -+#define CLK_APMU_PCIE_PORTD_SLV 63 -+#define CLK_APMU_PCIE_PORTE_MSTE 64 -+#define CLK_APMU_PCIE_PORTE_SLV 65 -+#define CLK_APMU_EMAC0_BUS 66 -+#define CLK_APMU_EMAC0_REF 67 -+#define CLK_APMU_EMAC0_1588 68 -+#define CLK_APMU_EMAC0_RGMII_TX 69 -+#define CLK_APMU_EMAC1_BUS 70 -+#define CLK_APMU_EMAC1_REF 71 -+#define CLK_APMU_EMAC1_1588 72 -+#define CLK_APMU_EMAC1_RGMII_TX 73 -+#define CLK_APMU_EMAC2_BUS 74 -+#define CLK_APMU_EMAC2_REF 75 -+#define CLK_APMU_EMAC2_1588 76 -+#define CLK_APMU_EMAC2_RGMII_TX 77 -+#define CLK_APMU_ESPI_SCLK_SRC 78 -+#define CLK_APMU_ESPI_SCLK 79 -+#define CLK_APMU_ESPI_MCLK 80 -+#define CLK_APMU_CAM_SRC1 81 -+#define CLK_APMU_CAM_SRC2 82 -+#define CLK_APMU_CAM_SRC3 83 -+#define CLK_APMU_CAM_SRC4 84 -+#define CLK_APMU_ISIM_VCLK0 85 -+#define CLK_APMU_ISIM_VCLK1 86 -+#define CLK_APMU_ISIM_VCLK2 87 -+#define CLK_APMU_ISIM_VCLK3 88 -+ -+/* DCIU clocks */ -+#define CLK_DCIU_HDMA 0 -+#define CLK_DCIU_DMA350 1 -+#define CLK_DCIU_C2_TCM_PIPE 2 -+#define CLK_DCIU_C3_TCM_PIPE 3 -+ -+#endif /* _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0120-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch b/SPECS/linux-lts-kmhv2/0120-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch deleted file mode 100644 index 5c1f5ce5c7..0000000000 --- a/SPECS/linux-lts-kmhv2/0120-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 963fb293372d266d46bee16fa3f3b74d277c8831 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 31 Oct 2025 20:40:46 +0800 -Subject: [PATCH 120/467] UPSTREAM: clk: spacemit: ccu_mix: add inverted enable - gate clock - -K3 SoC has the clock IP which support to write value 0 for enabling the -clock, while write 1 for disabling it, thus the enable BIT is inverted. -So, introduce a flag to support the inverted gate clock. - -Link: https://lore.kernel.org/r/20260108-k3-clk-v5-2-42a11b74ad58@gentoo.org -Signed-off-by: Yixun Lan -(cherry picked from commit ace73b7e27633ec770cfb24cd4ff42c24815a9aa) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu_mix.c | 12 ++++++++---- - drivers/clk/spacemit/ccu_mix.h | 12 ++++++++++++ - 2 files changed, 20 insertions(+), 4 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu_mix.c b/drivers/clk/spacemit/ccu_mix.c -index 9a3fc9ea1ce5..a8b407049bf4 100644 ---- a/drivers/clk/spacemit/ccu_mix.c -+++ b/drivers/clk/spacemit/ccu_mix.c -@@ -16,17 +16,19 @@ - static void ccu_gate_disable(struct clk_hw *hw) - { - struct ccu_mix *mix = hw_to_ccu_mix(hw); -+ struct ccu_gate_config *gate = &mix->gate; -+ u32 val = gate->inverted ? gate->mask : 0; - -- ccu_update(&mix->common, ctrl, mix->gate.mask, 0); -+ ccu_update(&mix->common, ctrl, gate->mask, val); - } - - static int ccu_gate_enable(struct clk_hw *hw) - { - struct ccu_mix *mix = hw_to_ccu_mix(hw); - struct ccu_gate_config *gate = &mix->gate; -+ u32 val = gate->inverted ? 0 : gate->mask; - -- ccu_update(&mix->common, ctrl, gate->mask, gate->mask); -- -+ ccu_update(&mix->common, ctrl, gate->mask, val); - return 0; - } - -@@ -34,8 +36,10 @@ static int ccu_gate_is_enabled(struct clk_hw *hw) - { - struct ccu_mix *mix = hw_to_ccu_mix(hw); - struct ccu_gate_config *gate = &mix->gate; -+ u32 tmp = ccu_read(&mix->common, ctrl) & gate->mask; -+ u32 val = gate->inverted ? 0 : gate->mask; - -- return (ccu_read(&mix->common, ctrl) & gate->mask) == gate->mask; -+ return !!(tmp == val); - } - - static unsigned long ccu_factor_recalc_rate(struct clk_hw *hw, -diff --git a/drivers/clk/spacemit/ccu_mix.h b/drivers/clk/spacemit/ccu_mix.h -index 54d40cd39b27..8a70cf151461 100644 ---- a/drivers/clk/spacemit/ccu_mix.h -+++ b/drivers/clk/spacemit/ccu_mix.h -@@ -16,9 +16,11 @@ - * - * @mask: Mask to enable the gate. Some clocks may have more than one bit - * set in this field. -+ * @inverted: Enable bit is inverted, 1 - disable clock, 0 - enable clock - */ - struct ccu_gate_config { - u32 mask; -+ bool inverted; - }; - - struct ccu_factor_config { -@@ -48,6 +50,7 @@ struct ccu_mix { - #define CCU_FACTOR_INIT(_div, _mul) { .div = _div, .mul = _mul } - #define CCU_MUX_INIT(_shift, _width) { .shift = _shift, .width = _width } - #define CCU_DIV_INIT(_shift, _width) { .shift = _shift, .width = _width } -+#define CCU_GATE_FLAGS_INIT(_mask, _inverted) { .mask = _mask, .inverted = _inverted } - - #define CCU_PARENT_HW(_parent) { .hw = &_parent.common.hw } - #define CCU_PARENT_NAME(_name) { .fw_name = #_name } -@@ -101,6 +104,15 @@ static struct ccu_mix _name = { \ - } \ - } - -+#define CCU_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _inverted, _flags) \ -+static struct ccu_mix _name = { \ -+ .gate = CCU_GATE_FLAGS_INIT(_mask_gate, _inverted), \ -+ .common = { \ -+ .reg_ctrl = _reg_ctrl, \ -+ CCU_MIX_INITHW(_name, _parent, spacemit_ccu_gate_ops, _flags), \ -+ } \ -+} -+ - #define CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \ - _mul, _flags) \ - static struct ccu_mix _name = { \ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch b/SPECS/linux-lts-kmhv2/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch new file mode 100644 index 0000000000..ca7b6c2396 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch @@ -0,0 +1,1541 @@ +From 878e4e3217cc3b8b51d6d5480b8c6c8120d47144 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Sun, 2 Nov 2025 21:17:17 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: add the clock tree + +Add clock support to SpacemiT K3 SoC, the clock tree consist of several +blocks which are APBC, APBS, APMU, DCIU, MPUM. + +Link: https://lore.kernel.org/r/20260108-k3-clk-v5-5-42a11b74ad58@gentoo.org +Signed-off-by: Yixun Lan +(cherry picked from commit e371a77255b837f5d64c9d2520f87e41ea5350b9) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/Kconfig | 6 + + drivers/clk/spacemit/Makefile | 3 + + drivers/clk/spacemit/ccu-k3.c | 1487 +++++++++++++++++++++++++++++++++ + 3 files changed, 1496 insertions(+) + create mode 100644 drivers/clk/spacemit/ccu-k3.c + +diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig +index 3351e8bc801d..4ebe6aaa1980 100644 +--- a/drivers/clk/spacemit/Kconfig ++++ b/drivers/clk/spacemit/Kconfig +@@ -14,4 +14,10 @@ config SPACEMIT_K1_CCU + help + Support for clock controller unit in SpacemiT K1 SoC. + ++config SPACEMIT_K3_CCU ++ tristate "Support for SpacemiT K3 SoC" ++ select SPACEMIT_CCU ++ help ++ Support for clock controller unit in SpacemiT K3 SoC. ++ + endmenu +diff --git a/drivers/clk/spacemit/Makefile b/drivers/clk/spacemit/Makefile +index ad2bf315109b..0925eda384b4 100644 +--- a/drivers/clk/spacemit/Makefile ++++ b/drivers/clk/spacemit/Makefile +@@ -8,3 +8,6 @@ spacemit-ccu-y += ccu_ddn.o + + obj-$(CONFIG_SPACEMIT_K1_CCU) += spacemit-ccu-k1.o + spacemit-ccu-k1-y += ccu-k1.o ++ ++obj-$(CONFIG_SPACEMIT_K3_CCU) += spacemit-ccu-k3.o ++spacemit-ccu-k3-y += ccu-k3.o +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +new file mode 100644 +index 000000000000..e98afd59f05c +--- /dev/null ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -0,0 +1,1487 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "ccu_common.h" ++#include "ccu_pll.h" ++#include "ccu_mix.h" ++#include "ccu_ddn.h" ++ ++#include ++ ++/* APBS clocks start, APBS region contains and only contains all PLL clocks */ ++ ++/* ++ * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for ++ * peripherals. ++ */ ++static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = { ++ CCU_PLLA_RATE(2457600000UL, 0x0b330ccc, 0x0000cd00, 0xa0558989), ++}; ++ ++static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { ++ CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c), ++}; ++ ++static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = { ++ CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), ++}; ++ ++static const struct ccu_pll_rate_tbl pll4_rate_tbl[] = { ++ CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), ++}; ++ ++static const struct ccu_pll_rate_tbl pll5_rate_tbl[] = { ++ CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), ++}; ++ ++static const struct ccu_pll_rate_tbl pll6_rate_tbl[] = { ++ CCU_PLLA_RATE(3200000000UL, 0x0b422aaa, 0x0000ab00, 0xa0558e8e), ++}; ++ ++static const struct ccu_pll_rate_tbl pll7_rate_tbl[] = { ++ CCU_PLLA_RATE(2800000000UL, 0x0b3a1555, 0x00005500, 0xa0558b8b), ++}; ++ ++static const struct ccu_pll_rate_tbl pll8_rate_tbl[] = { ++ CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), ++}; ++ ++CCU_PLLA_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR2, APBS_PLL1_SWCR3, ++ MPMU_POSR, POSR_PLL1_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2, APBS_PLL2_SWCR3, ++ MPMU_POSR, POSR_PLL2_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR2, APBS_PLL3_SWCR3, ++ MPMU_POSR, POSR_PLL3_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll4, pll4_rate_tbl, APBS_PLL4_SWCR1, APBS_PLL4_SWCR2, APBS_PLL4_SWCR3, ++ MPMU_POSR, POSR_PLL4_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll5, pll5_rate_tbl, APBS_PLL5_SWCR1, APBS_PLL5_SWCR2, APBS_PLL5_SWCR3, ++ MPMU_POSR, POSR_PLL5_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll6, pll6_rate_tbl, APBS_PLL6_SWCR1, APBS_PLL6_SWCR2, APBS_PLL6_SWCR3, ++ MPMU_POSR, POSR_PLL6_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll7, pll7_rate_tbl, APBS_PLL7_SWCR1, APBS_PLL7_SWCR2, APBS_PLL7_SWCR3, ++ MPMU_POSR, POSR_PLL7_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll8, pll8_rate_tbl, APBS_PLL8_SWCR1, APBS_PLL8_SWCR2, APBS_PLL8_SWCR3, ++ MPMU_POSR, POSR_PLL8_LOCK, CLK_SET_RATE_GATE); ++ ++CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1, ++ CLK_IS_CRITICAL); ++CCU_DIV_GATE_DEFINE(pll1_dx, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, 23, 5, BIT(22), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(31), 64, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(21), 10, 1); ++CCU_FACTOR_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1_aud_245p7), 10, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1); ++CCU_FACTOR_DEFINE(pll2_66, CCU_PARENT_HW(pll2_d5), 9, 1); ++CCU_FACTOR_DEFINE(pll2_33, CCU_PARENT_HW(pll2_66), 2, 1); ++CCU_FACTOR_DEFINE(pll2_50, CCU_PARENT_HW(pll2_d5), 12, 1); ++CCU_FACTOR_DEFINE(pll2_25, CCU_PARENT_HW(pll2_50), 2, 1); ++CCU_FACTOR_DEFINE(pll2_20, CCU_PARENT_HW(pll2_d5), 30, 1); ++CCU_FACTOR_DEFINE(pll2_d24_125, CCU_PARENT_HW(pll2_d3), 8, 1); ++CCU_FACTOR_DEFINE(pll2_d120_25, CCU_PARENT_HW(pll2_d3), 40, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll4_d1, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d2, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d3, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d4, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d5, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d6, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d7, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d8, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll5_d1, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d2, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d3, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d4, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d5, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d6, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d7, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d8, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll6_d1, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d2, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d3, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d4, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d5, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d6, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d7, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d8, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(7), 8, 1); ++CCU_FACTOR_DEFINE(pll6_80, CCU_PARENT_HW(pll6_d5), 8, 1); ++CCU_FACTOR_DEFINE(pll6_40, CCU_PARENT_HW(pll6_d5), 16, 1); ++CCU_FACTOR_DEFINE(pll6_20, CCU_PARENT_HW(pll6_d5), 32, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll7_d1, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d2, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d3, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d4, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d5, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d6, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d7, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d8, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll8_d1, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d2, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d3, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d4, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d5, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d6, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d7, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d8, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(7), 8, 1); ++/* APBS clocks end */ ++ ++/* MPMU clocks start */ ++CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13), 0); ++CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1); ++CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1); ++CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(12), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(7), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(11), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(8), 16, 3); ++CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(4), 12, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(3), 24, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(19), 24, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(2), 48, 1); ++ ++CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1); ++CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1); ++CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1); ++ ++CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1); ++ ++CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1); ++ ++CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(10), 13, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6), 39, 2); ++ ++CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0); ++ ++CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0); ++ ++static const struct clk_parent_data apb_parents[] = { ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d24_102p4), ++}; ++CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0); ++ ++CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc_32k), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED); ++CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 2, 0); ++CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 2, 0); ++ ++CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0); ++CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), 0); ++ ++CCU_GATE_DEFINE(r_ipc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, BIT(0), 0); ++ ++CCU_FACTOR_DEFINE(i2s_153p6, CCU_PARENT_HW(pll1_d8_307p2), 2, 1); ++ ++static const struct clk_parent_data i2s_153p6_base_parents[] = { ++ CCU_PARENT_HW(i2s_153p6), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DEFINE(i2s_153p6_base, i2s_153p6_base_parents, MPMU_FCCR, 29, 1, 0); ++ ++static const struct clk_parent_data i2s_sysclk_src_parents[] = { ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(i2s_153p6_base), ++}; ++CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0); ++ ++CCU_DDN_DEFINE(i2s1_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0); ++ ++CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s1_sysclk), MPMU_ISCCR, 27, 2, BIT(29), 0); ++ ++static const struct clk_parent_data i2s_sysclk_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_NAME(vctcxo_24m), ++ CCU_PARENT_HW(pll2_d5), ++ CCU_PARENT_NAME(vctcxo_24m), ++}; ++CCU_MUX_DEFINE(i2s0_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 0, 2, 0); ++CCU_MUX_DEFINE(i2s2_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 4, 2, 0); ++CCU_MUX_DEFINE(i2s3_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 12, 2, 0); ++CCU_MUX_DEFINE(i2s4_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 16, 2, 0); ++CCU_MUX_DEFINE(i2s5_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 20, 2, 0); ++ ++CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 1, 0); ++ ++static const struct clk_parent_data i2s2_sysclk_parents[] = { ++ CCU_PARENT_HW(i2s1_sysclk), ++ CCU_PARENT_HW(i2s2_sysclk_div), ++}; ++CCU_GATE_DEFINE(i2s0_sysclk, CCU_PARENT_HW(i2s0_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(2), 0); ++CCU_MUX_GATE_DEFINE(i2s2_sysclk, i2s2_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 8, 1, BIT(6), 0); ++CCU_GATE_DEFINE(i2s3_sysclk, CCU_PARENT_HW(i2s3_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(14), 0); ++CCU_GATE_DEFINE(i2s4_sysclk, CCU_PARENT_HW(i2s4_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(18), 0); ++CCU_GATE_DEFINE(i2s5_sysclk, CCU_PARENT_HW(i2s5_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(22), 0); ++/* MPMU clocks end */ ++ ++/* APBC clocks start */ ++static const struct clk_parent_data uart_clk_parents[] = { ++ CCU_PARENT_HW(pll1_m3d128_57p6), ++ CCU_PARENT_HW(slow_uart1_14p74), ++ CCU_PARENT_HW(slow_uart2_48), ++}; ++CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart10_clk, uart_clk_parents, APBC_UART10_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART10_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data pwm_parents[] = { ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_NAME(osc_32k), ++}; ++CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data i2s_bclk_parents[] = { ++ CCU_PARENT_NAME(vctcxo_1m), ++ CCU_PARENT_HW(i2s_bclk), ++}; ++CCU_MUX_DEFINE(spi0_i2s_bclk, i2s_bclk_parents, APBC_SSP0_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(spi1_i2s_bclk, i2s_bclk_parents, APBC_SSP1_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(spi3_i2s_bclk, i2s_bclk_parents, APBC_SSP3_CLK_RST, 3, 1, 0); ++ ++static const struct clk_parent_data spi0_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(spi0_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(spi0_clk, spi0_parents, APBC_SSP0_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data spi1_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(spi1_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(spi1_clk, spi1_parents, APBC_SSP1_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data spi3_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(spi3_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(spi3_clk, spi3_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(spi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(spi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(spi3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, BIT(0), 0); ++ ++ ++CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc_32k), APBC_RTC_CLK_RST, ++ BIT(7) | BIT(1), 0); ++CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data twsi_parents[] = { ++ CCU_PARENT_HW(pll1_d78_31p5), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d40_61p44), ++}; ++CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi8_clk, twsi_parents, APBC_TWSI8_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI8_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data timer_parents[] = { ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_NAME(osc_32k), ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_NAME(vctcxo_3m), ++ CCU_PARENT_NAME(vctcxo_1m), ++}; ++CCU_MUX_GATE_DEFINE(timers0_clk, timer_parents, APBC_TIMERS0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers3_clk, timer_parents, APBC_TIMERS3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers4_clk, timer_parents, APBC_TIMERS4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers5_clk, timer_parents, APBC_TIMERS5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers6_clk, timer_parents, APBC_TIMERS6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers7_clk, timer_parents, APBC_TIMERS7_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(timers0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS7_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_RST, BIT(0), 0); ++ ++/* ++ * When i2s_bclk is selected as the parent clock of sspa, ++ * the hardware requires bit3 to be set ++ */ ++ ++CCU_MUX_DEFINE(i2s0_i2s_bclk, i2s_bclk_parents, APBC_SSPA0_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s1_i2s_bclk, i2s_bclk_parents, APBC_SSPA1_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s2_i2s_bclk, i2s_bclk_parents, APBC_SSPA2_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s3_i2s_bclk, i2s_bclk_parents, APBC_SSPA3_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s4_i2s_bclk, i2s_bclk_parents, APBC_SSPA4_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s5_i2s_bclk, i2s_bclk_parents, APBC_SSPA5_CLK_RST, 3, 1, 0); ++ ++static const struct clk_parent_data i2s0_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s0_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s0_clk, i2s0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s1_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s1_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s1_clk, i2s1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s2_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s2_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s2_clk, i2s2_parents, APBC_SSPA2_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s3_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s3_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s3_clk, i2s3_parents, APBC_SSPA3_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s4_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s4_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s4_clk, i2s4_parents, APBC_SSPA4_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s5_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s5_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s5_clk, i2s5_parents, APBC_SSPA5_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(i2s0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA5_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(ir0_clk, CCU_PARENT_HW(apb_clk), APBC_IR0_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(ir1_clk, CCU_PARENT_HW(apb_clk), APBC_IR1_CLK_RST, BIT(1), 0); ++ ++CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(ipc_ap2rcpu_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(ipc_ap2rcpu_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data can_parents[] = { ++ CCU_PARENT_HW(pll6_20), ++ CCU_PARENT_HW(pll6_40), ++ CCU_PARENT_HW(pll6_80), ++}; ++CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(can1_clk, can_parents, APBC_CAN1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(can2_clk, can_parents, APBC_CAN2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(can3_clk, can_parents, APBC_CAN3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(can4_clk, can_parents, APBC_CAN4_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(can1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(can2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(can3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(can4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN4_CLK_RST, BIT(0), 0); ++/* APBC clocks end */ ++ ++/* APMU clocks start */ ++static const struct clk_parent_data axi_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++}; ++CCU_MUX_DIV_FC_DEFINE(axi_clk, axi_clk_parents, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), 0, 1, 0); ++ ++static const struct clk_parent_data cci550_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll7_d3), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll7_d2), ++}; ++CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL, 8, 2, BIT(12), 0, 3, ++ CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c0_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll3_d2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll3_d1), ++}; ++CCU_MUX_DIV_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL, ++ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c1_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll4_d2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll4_d1), ++}; ++CCU_MUX_DIV_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL, ++ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c2_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll5_d2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll5_d1), ++}; ++CCU_MUX_DIV_FC_DEFINE(cpu_c2_core_clk, cpu_c2_clk_parents, APMU_CPU_C2_CLK_CTRL, ++ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c3_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll8_d2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll8_d1), ++}; ++CCU_MUX_DIV_FC_DEFINE(cpu_c3_core_clk, cpu_c3_clk_parents, APMU_CPU_C3_CLK_CTRL, ++ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data ccic2phy_parents[] = { ++ CCU_PARENT_HW(pll1_d24_102p4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0); ++ ++static const struct clk_parent_data ccic3phy_parents[] = { ++ CCU_PARENT_HW(pll1_d24_102p4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0); ++ ++static const struct clk_parent_data csi_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15), ++ 16, 3, BIT(4), 0); ++ ++static const struct clk_parent_data isp_bus_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d10_245p76), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23), ++ 21, 2, BIT(17), 0); ++ ++CCU_GATE_DEFINE(d1p_1228p8, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMU_CLK_GATE_CTRL, BIT(31), 0); ++CCU_GATE_DEFINE(d1p_819p2, CCU_PARENT_HW(pll1_d3_819p2), APMU_PMU_CLK_GATE_CTRL, BIT(30), 0); ++CCU_GATE_DEFINE(d1p_614p4, CCU_PARENT_HW(pll1_d4_614p4), APMU_PMU_CLK_GATE_CTRL, BIT(29), 0); ++CCU_GATE_DEFINE(d1p_491p52, CCU_PARENT_HW(pll1_d5_491p52), APMU_PMU_CLK_GATE_CTRL, BIT(28), 0); ++CCU_GATE_DEFINE(d1p_409p6, CCU_PARENT_HW(pll1_d6_409p6), APMU_PMU_CLK_GATE_CTRL, BIT(27), 0); ++CCU_GATE_DEFINE(d1p_307p2, CCU_PARENT_HW(pll1_d8_307p2), APMU_PMU_CLK_GATE_CTRL, BIT(26), 0); ++CCU_GATE_DEFINE(d1p_245p76, CCU_PARENT_HW(pll1_d10_245p76), APMU_PMU_CLK_GATE_CTRL, BIT(22), 0); ++ ++static const struct clk_parent_data v2d_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d4_614p4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28), 12, 2, ++ BIT(8), 0); ++ ++static const struct clk_parent_data dsiesc_parents[] = { ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll1_d52_47p26), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d32_76p8), ++}; ++CCU_MUX_GATE_DEFINE(dsi_esc_clk, dsiesc_parents, APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0); ++ ++CCU_GATE_DEFINE(lcd_hclk, CCU_PARENT_HW(axi_clk), APMU_LCD_CLK_RES_CTRL1, BIT(5), 0); ++ ++static const struct clk_parent_data lcd_dsc_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_HW(pll7_d5), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll2_d8), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_dsc_clk, lcd_dsc_parents, APMU_LCD_CLK_RES_CTRL2, ++ APMU_LCD_CLK_RES_CTRL1, 25, 3, BIT(26), 29, 3, BIT(14), 0); ++ ++static const struct clk_parent_data lcdpx_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_HW(pll7_d5), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll2_d8), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_pxclk, lcdpx_parents, APMU_LCD_CLK_RES_CTRL2, ++ APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(30), 21, 3, BIT(16), 0); ++ ++static const struct clk_parent_data lcdmclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_mclk, lcdmclk_parents, APMU_LCD_CLK_RES_CTRL2, ++ APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0); ++ ++static const struct clk_parent_data ccic_4x_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES_CTRL, 18, 3, ++ BIT(15), 23, 2, BIT(4), 0); ++ ++static const struct clk_parent_data ccic1phy_parents[] = { ++ CCU_PARENT_HW(pll1_d24_102p4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0); ++ ++ ++static const struct clk_parent_data sc2hclk_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll2_d4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(sc2_hclk, sc2hclk_parents, APMU_CCIC_CLK_RES_CTRL, 10, 3, ++ BIT(16), 8, 2, BIT(3), 0); ++ ++CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(axi_clk), APMU_SDH0_CLK_RES_CTRL, BIT(3), 0); ++static const struct clk_parent_data sdh01_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d8), ++ CCU_PARENT_HW(pll2_d5), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_HW(pll1_dx), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL, 8, 3, ++ BIT(11), 5, 3, BIT(4), 0); ++CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL, 8, 3, ++ BIT(11), 5, 3, BIT(4), 0); ++static const struct clk_parent_data sdh2_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d8), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_HW(pll1_dx), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, ++ BIT(11), 5, 3, BIT(4), 0); ++ ++CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(4), 0); ++CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); ++CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(12), 0); ++CCU_GATE_DEFINE(usb3_portd_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(16), 0); ++ ++static const struct clk_parent_data qspi_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll2_d8), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_HW(pll1_dx), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_NAME(reserved_clk), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL, 9, 3, ++ BIT(12), 6, 3, BIT(4), 0); ++CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(axi_clk), APMU_QSPI_CLK_RES_CTRL, BIT(3), 0); ++ ++CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(axi_clk), APMU_DMA_CLK_RES_CTRL, BIT(3), 0); ++ ++static const struct clk_parent_data aes_wtm_parents[] = { ++ CCU_PARENT_HW(pll1_d12_204p8), ++ CCU_PARENT_HW(pll1_d24_102p4), ++}; ++CCU_MUX_GATE_DEFINE(aes_wtm_clk, aes_wtm_parents, APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0); ++ ++static const struct clk_parent_data vpu_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll2_d5), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13, 3, ++ BIT(21), 10, 3, BIT(3), 0); ++ ++CCU_GATE_DEFINE(dtc_clk, CCU_PARENT_HW(axi_clk), APMU_DTC_CLK_RES_CTRL, BIT(3), 0); ++ ++static const struct clk_parent_data gpu_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll2_d5), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12, 3, ++ BIT(15), 18, 3, BIT(4), 0); ++ ++CCU_GATE_DEFINE(mc_ahb_clk, CCU_PARENT_HW(axi_clk), APMU_PMUA_MC_CTRL, BIT(1), 0); ++ ++static const struct clk_parent_data top_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll3_d4), ++ CCU_PARENT_HW(pll6_d5), ++ CCU_PARENT_HW(pll7_d4), ++ CCU_PARENT_HW(pll6_d4), ++ CCU_PARENT_HW(pll7_d3), ++ CCU_PARENT_HW(pll6_d3), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(top_dclk, top_parents, APMU_TOP_DCLK_CTRL, 5, 3, ++ BIT(8), 2, 3, BIT(1), 0); ++ ++static const struct clk_parent_data ucie_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll3_d4), ++ CCU_PARENT_HW(pll6_d5), ++ CCU_PARENT_HW(pll7_d4), ++ CCU_PARENT_HW(pll6_d4), ++}; ++CCU_MUX_GATE_DEFINE(ucie_clk, ucie_parents, APMU_UCIE_CTRL, 4, 3, BIT(0), 0); ++CCU_GATE_DEFINE(ucie_sbclk, CCU_PARENT_HW(axi_clk), APMU_UCIE_CTRL, BIT(8), 0); ++ ++static const struct clk_parent_data rcpu_clk_parents[] = { ++ CCU_PARENT_HW(pll1_aud_245p7), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d6_409p6), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, ++ 4, 3, BIT(15), 7, 3, BIT(12), 0); ++ ++static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll1_d52_47p26), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d32_76p8), ++}; ++CCU_MUX_GATE_DEFINE(dsi4ln2_dsi_esc_clk, dsi4ln2_dsi_esc_parents, APMU_LCD_CLK_RES_CTRL3, ++ 0, 1, BIT(2), 0); ++ ++static const struct clk_parent_data dsi4ln2_lcd_dsc_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll7_d5), ++ CCU_PARENT_HW(pll6_d6), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_dsc_clk, dsi4ln2_lcd_dsc_parents, ++ APMU_LCD_CLK_RES_CTRL4, APMU_LCD_CLK_RES_CTRL3, ++ 25, 3, BIT(26), 29, 3, BIT(14), 0); ++ ++static const struct clk_parent_data dsi4ln2_lcdpx_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll7_d5), ++ CCU_PARENT_HW(pll6_d6), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll2_d8), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_pxclk, dsi4ln2_lcdpx_parents, APMU_LCD_CLK_RES_CTRL4, ++ APMU_LCD_CLK_RES_CTRL3, 17, 3, BIT(30), 21, 3, BIT(16), 0); ++ ++static const struct clk_parent_data dsi4ln2_lcd_mclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_mclk, dsi4ln2_lcd_mclk_parents, APMU_LCD_CLK_RES_CTRL4, ++ APMU_LCD_CLK_RES_CTRL3, 1, 4, BIT(29), 5, 3, BIT(0), 0); ++ ++static const struct clk_parent_data dpu_aclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll2_d4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(dsi4ln2_dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, ++ 2, 3, BIT(30), 5, 3, BIT(1), 0); ++ ++CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, 17, 3, BIT(31), ++ 20, 3, BIT(16), 0); ++ ++static const struct clk_parent_data ufs_aclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll2_d4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8), ++ 2, 3, BIT(1), 0); ++ ++static const struct clk_parent_data edp0_pclk_parents[] = { ++ CCU_PARENT_HW(lcd_pxclk), ++ CCU_PARENT_NAME(external_clk), ++}; ++CCU_MUX_GATE_DEFINE(edp0_pxclk, edp0_pclk_parents, APMU_LCD_EDP_CTRL, 2, 1, BIT(1), 0); ++ ++static const struct clk_parent_data edp1_pclk_parents[] = { ++ CCU_PARENT_HW(dsi4ln2_lcd_pxclk), ++ CCU_PARENT_NAME(external_clk), ++}; ++CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); ++ ++CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); ++CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); ++CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); ++CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); ++CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); ++CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); ++CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); ++CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); ++CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); ++CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); ++ ++static const struct clk_parent_data emac_1588_parents[] = { ++ CCU_PARENT_NAME(vctcxo_24m), ++ CCU_PARENT_HW(pll2_d24_125), ++}; ++ ++CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_FLAGS_DEFINE(emac0_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC0_CLK_RES_CTRL, ++ BIT(14), true, 0); ++CCU_MUX_DEFINE(emac0_1588_clk, emac_1588_parents, APMU_EMAC0_CLK_RES_CTRL, 15, 1, 0); ++CCU_GATE_DEFINE(emac0_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC0_CLK_RES_CTRL, ++ BIT(8), 0); ++CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_FLAGS_DEFINE(emac1_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC1_CLK_RES_CTRL, ++ BIT(14), true, 0); ++CCU_MUX_DEFINE(emac1_1588_clk, emac_1588_parents, APMU_EMAC1_CLK_RES_CTRL, 15, 1, 0); ++CCU_GATE_DEFINE(emac1_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC1_CLK_RES_CTRL, ++ BIT(8), 0); ++CCU_GATE_DEFINE(emac2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC2_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_FLAGS_DEFINE(emac2_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC2_CLK_RES_CTRL, ++ BIT(14), true, 0); ++CCU_MUX_DEFINE(emac2_1588_clk, emac_1588_parents, APMU_EMAC2_CLK_RES_CTRL, 15, 1, 0); ++CCU_GATE_DEFINE(emac2_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC2_CLK_RES_CTRL, ++ BIT(8), 0); ++ ++static const struct clk_parent_data espi_sclk_src_parents[] = { ++ CCU_PARENT_HW(pll2_20), ++ CCU_PARENT_HW(pll2_25), ++ CCU_PARENT_HW(pll2_33), ++ CCU_PARENT_HW(pll2_50), ++ CCU_PARENT_HW(pll2_66), ++}; ++CCU_MUX_DEFINE(espi_sclk_src, espi_sclk_src_parents, APMU_ESPI_CLK_RES_CTRL, 4, 3, 0); ++ ++static const struct clk_parent_data espi_sclk_parents[] = { ++ CCU_PARENT_NAME(external_clk), ++ CCU_PARENT_HW(espi_sclk_src), ++}; ++CCU_MUX_GATE_DEFINE(espi_sclk, espi_sclk_parents, APMU_ESPI_CLK_RES_CTRL, 7, 1, BIT(3), 0); ++ ++CCU_GATE_DEFINE(espi_mclk, CCU_PARENT_HW(axi_clk), APMU_ESPI_CLK_RES_CTRL, BIT(1), 0); ++ ++CCU_FACTOR_DEFINE(cam_src1_clk, CCU_PARENT_HW(pll1_d6_409p6), 15, 1); ++CCU_FACTOR_DEFINE(cam_src2_clk, CCU_PARENT_HW(pll2_d5), 25, 1); ++CCU_FACTOR_DEFINE(cam_src3_clk, CCU_PARENT_HW(pll2_d6), 20, 1); ++CCU_FACTOR_DEFINE(cam_src4_clk, CCU_PARENT_HW(pll1_d6_409p6), 16, 1); ++ ++static const struct clk_parent_data isim_vclk_parents[] = { ++ CCU_PARENT_HW(cam_src1_clk), ++ CCU_PARENT_HW(cam_src2_clk), ++ CCU_PARENT_HW(cam_src3_clk), ++ CCU_PARENT_HW(cam_src4_clk), ++}; ++CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out0, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 3, 4, ++ 1, 2, BIT(0), 0); ++CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out1, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 11, 4, ++ 9, 2, BIT(8), 0); ++CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out2, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 19, 4, ++ 17, 2, BIT(16), 0); ++CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 27, 4, ++ 25, 2, BIT(24), 0); ++/* APMU clocks end */ ++ ++/* DCIU clocks start */ ++CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); ++CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); ++CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); ++CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); ++/* DCIU clocks end */ ++ ++static struct clk_hw *k3_ccu_pll_hws[] = { ++ [CLK_PLL1] = &pll1.common.hw, ++ [CLK_PLL2] = &pll2.common.hw, ++ [CLK_PLL3] = &pll3.common.hw, ++ [CLK_PLL4] = &pll4.common.hw, ++ [CLK_PLL5] = &pll5.common.hw, ++ [CLK_PLL6] = &pll6.common.hw, ++ [CLK_PLL7] = &pll7.common.hw, ++ [CLK_PLL8] = &pll8.common.hw, ++ [CLK_PLL1_D2] = &pll1_d2.common.hw, ++ [CLK_PLL1_D3] = &pll1_d3.common.hw, ++ [CLK_PLL1_D4] = &pll1_d4.common.hw, ++ [CLK_PLL1_D5] = &pll1_d5.common.hw, ++ [CLK_PLL1_D6] = &pll1_d6.common.hw, ++ [CLK_PLL1_D7] = &pll1_d7.common.hw, ++ [CLK_PLL1_D8] = &pll1_d8.common.hw, ++ [CLK_PLL1_DX] = &pll1_dx.common.hw, ++ [CLK_PLL1_D64] = &pll1_d64_38p4.common.hw, ++ [CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw, ++ [CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw, ++ [CLK_PLL2_D1] = &pll2_d1.common.hw, ++ [CLK_PLL2_D2] = &pll2_d2.common.hw, ++ [CLK_PLL2_D3] = &pll2_d3.common.hw, ++ [CLK_PLL2_D4] = &pll2_d4.common.hw, ++ [CLK_PLL2_D5] = &pll2_d5.common.hw, ++ [CLK_PLL2_D6] = &pll2_d6.common.hw, ++ [CLK_PLL2_D7] = &pll2_d7.common.hw, ++ [CLK_PLL2_D8] = &pll2_d8.common.hw, ++ [CLK_PLL2_66] = &pll2_66.common.hw, ++ [CLK_PLL2_33] = &pll2_33.common.hw, ++ [CLK_PLL2_50] = &pll2_50.common.hw, ++ [CLK_PLL2_25] = &pll2_25.common.hw, ++ [CLK_PLL2_20] = &pll2_20.common.hw, ++ [CLK_PLL2_D24_125] = &pll2_d24_125.common.hw, ++ [CLK_PLL2_D120_25] = &pll2_d120_25.common.hw, ++ [CLK_PLL3_D1] = &pll3_d1.common.hw, ++ [CLK_PLL3_D2] = &pll3_d2.common.hw, ++ [CLK_PLL3_D3] = &pll3_d3.common.hw, ++ [CLK_PLL3_D4] = &pll3_d4.common.hw, ++ [CLK_PLL3_D5] = &pll3_d5.common.hw, ++ [CLK_PLL3_D6] = &pll3_d6.common.hw, ++ [CLK_PLL3_D7] = &pll3_d7.common.hw, ++ [CLK_PLL3_D8] = &pll3_d8.common.hw, ++ [CLK_PLL4_D1] = &pll4_d1.common.hw, ++ [CLK_PLL4_D2] = &pll4_d2.common.hw, ++ [CLK_PLL4_D3] = &pll4_d3.common.hw, ++ [CLK_PLL4_D4] = &pll4_d4.common.hw, ++ [CLK_PLL4_D5] = &pll4_d5.common.hw, ++ [CLK_PLL4_D6] = &pll4_d6.common.hw, ++ [CLK_PLL4_D7] = &pll4_d7.common.hw, ++ [CLK_PLL4_D8] = &pll4_d8.common.hw, ++ [CLK_PLL5_D1] = &pll5_d1.common.hw, ++ [CLK_PLL5_D2] = &pll5_d2.common.hw, ++ [CLK_PLL5_D3] = &pll5_d3.common.hw, ++ [CLK_PLL5_D4] = &pll5_d4.common.hw, ++ [CLK_PLL5_D5] = &pll5_d5.common.hw, ++ [CLK_PLL5_D6] = &pll5_d6.common.hw, ++ [CLK_PLL5_D7] = &pll5_d7.common.hw, ++ [CLK_PLL5_D8] = &pll5_d8.common.hw, ++ [CLK_PLL6_D1] = &pll6_d1.common.hw, ++ [CLK_PLL6_D2] = &pll6_d2.common.hw, ++ [CLK_PLL6_D3] = &pll6_d3.common.hw, ++ [CLK_PLL6_D4] = &pll6_d4.common.hw, ++ [CLK_PLL6_D5] = &pll6_d5.common.hw, ++ [CLK_PLL6_D6] = &pll6_d6.common.hw, ++ [CLK_PLL6_D7] = &pll6_d7.common.hw, ++ [CLK_PLL6_D8] = &pll6_d8.common.hw, ++ [CLK_PLL6_80] = &pll6_80.common.hw, ++ [CLK_PLL6_40] = &pll6_40.common.hw, ++ [CLK_PLL6_20] = &pll6_20.common.hw, ++ [CLK_PLL7_D1] = &pll7_d1.common.hw, ++ [CLK_PLL7_D2] = &pll7_d2.common.hw, ++ [CLK_PLL7_D3] = &pll7_d3.common.hw, ++ [CLK_PLL7_D4] = &pll7_d4.common.hw, ++ [CLK_PLL7_D5] = &pll7_d5.common.hw, ++ [CLK_PLL7_D6] = &pll7_d6.common.hw, ++ [CLK_PLL7_D7] = &pll7_d7.common.hw, ++ [CLK_PLL7_D8] = &pll7_d8.common.hw, ++ [CLK_PLL8_D1] = &pll8_d1.common.hw, ++ [CLK_PLL8_D2] = &pll8_d2.common.hw, ++ [CLK_PLL8_D3] = &pll8_d3.common.hw, ++ [CLK_PLL8_D4] = &pll8_d4.common.hw, ++ [CLK_PLL8_D5] = &pll8_d5.common.hw, ++ [CLK_PLL8_D6] = &pll8_d6.common.hw, ++ [CLK_PLL8_D7] = &pll8_d7.common.hw, ++ [CLK_PLL8_D8] = &pll8_d8.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_pll_data = { ++ /* The APBS CCU implements PLLs, but no resets */ ++ .hws = k3_ccu_pll_hws, ++ .num = ARRAY_SIZE(k3_ccu_pll_hws), ++}; ++ ++static struct clk_hw *k3_ccu_mpmu_hws[] = { ++ [CLK_MPMU_PLL1_307P2] = &pll1_d8_307p2.common.hw, ++ [CLK_MPMU_PLL1_76P8] = &pll1_d32_76p8.common.hw, ++ [CLK_MPMU_PLL1_61P44] = &pll1_d40_61p44.common.hw, ++ [CLK_MPMU_PLL1_153P6] = &pll1_d16_153p6.common.hw, ++ [CLK_MPMU_PLL1_102P4] = &pll1_d24_102p4.common.hw, ++ [CLK_MPMU_PLL1_51P2] = &pll1_d48_51p2.common.hw, ++ [CLK_MPMU_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw, ++ [CLK_MPMU_PLL1_57P6] = &pll1_m3d128_57p6.common.hw, ++ [CLK_MPMU_PLL1_25P6] = &pll1_d96_25p6.common.hw, ++ [CLK_MPMU_PLL1_12P8] = &pll1_d192_12p8.common.hw, ++ [CLK_MPMU_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw, ++ [CLK_MPMU_PLL1_6P4] = &pll1_d384_6p4.common.hw, ++ [CLK_MPMU_PLL1_3P2] = &pll1_d768_3p2.common.hw, ++ [CLK_MPMU_PLL1_1P6] = &pll1_d1536_1p6.common.hw, ++ [CLK_MPMU_PLL1_0P8] = &pll1_d3072_0p8.common.hw, ++ [CLK_MPMU_PLL1_409P6] = &pll1_d6_409p6.common.hw, ++ [CLK_MPMU_PLL1_204P8] = &pll1_d12_204p8.common.hw, ++ [CLK_MPMU_PLL1_491] = &pll1_d5_491p52.common.hw, ++ [CLK_MPMU_PLL1_245P76] = &pll1_d10_245p76.common.hw, ++ [CLK_MPMU_PLL1_614] = &pll1_d4_614p4.common.hw, ++ [CLK_MPMU_PLL1_47P26] = &pll1_d52_47p26.common.hw, ++ [CLK_MPMU_PLL1_31P5] = &pll1_d78_31p5.common.hw, ++ [CLK_MPMU_PLL1_819] = &pll1_d3_819p2.common.hw, ++ [CLK_MPMU_PLL1_1228] = &pll1_d2_1228p8.common.hw, ++ [CLK_MPMU_APB] = &apb_clk.common.hw, ++ [CLK_MPMU_SLOW_UART] = &slow_uart.common.hw, ++ [CLK_MPMU_SLOW_UART1] = &slow_uart1_14p74.common.hw, ++ [CLK_MPMU_SLOW_UART2] = &slow_uart2_48.common.hw, ++ [CLK_MPMU_WDT] = &wdt_clk.common.hw, ++ [CLK_MPMU_WDT_BUS] = &wdt_bus_clk.common.hw, ++ [CLK_MPMU_RIPC] = &r_ipc_clk.common.hw, ++ [CLK_MPMU_I2S_153P6] = &i2s_153p6.common.hw, ++ [CLK_MPMU_I2S_153P6_BASE] = &i2s_153p6_base.common.hw, ++ [CLK_MPMU_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw, ++ [CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw, ++ [CLK_MPMU_I2S_BCLK] = &i2s_bclk.common.hw, ++ [CLK_MPMU_I2S0_SYSCLK_SEL] = &i2s0_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S2_SYSCLK_SEL] = &i2s2_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S3_SYSCLK_SEL] = &i2s3_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S4_SYSCLK_SEL] = &i2s4_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S5_SYSCLK_SEL] = &i2s5_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S0_SYSCLK_DIV] = &i2s0_sysclk_div.common.hw, ++ [CLK_MPMU_I2S2_SYSCLK_DIV] = &i2s2_sysclk_div.common.hw, ++ [CLK_MPMU_I2S3_SYSCLK_DIV] = &i2s3_sysclk_div.common.hw, ++ [CLK_MPMU_I2S4_SYSCLK_DIV] = &i2s4_sysclk_div.common.hw, ++ [CLK_MPMU_I2S5_SYSCLK_DIV] = &i2s5_sysclk_div.common.hw, ++ [CLK_MPMU_I2S0_SYSCLK] = &i2s0_sysclk.common.hw, ++ [CLK_MPMU_I2S2_SYSCLK] = &i2s2_sysclk.common.hw, ++ [CLK_MPMU_I2S3_SYSCLK] = &i2s3_sysclk.common.hw, ++ [CLK_MPMU_I2S4_SYSCLK] = &i2s4_sysclk.common.hw, ++ [CLK_MPMU_I2S5_SYSCLK] = &i2s5_sysclk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_mpmu_data = { ++ .reset_name = "k3-mpmu-reset", ++ .hws = k3_ccu_mpmu_hws, ++ .num = ARRAY_SIZE(k3_ccu_mpmu_hws), ++}; ++ ++static struct clk_hw *k3_ccu_apbc_hws[] = { ++ [CLK_APBC_UART0] = &uart0_clk.common.hw, ++ [CLK_APBC_UART2] = &uart2_clk.common.hw, ++ [CLK_APBC_UART3] = &uart3_clk.common.hw, ++ [CLK_APBC_UART4] = &uart4_clk.common.hw, ++ [CLK_APBC_UART5] = &uart5_clk.common.hw, ++ [CLK_APBC_UART6] = &uart6_clk.common.hw, ++ [CLK_APBC_UART7] = &uart7_clk.common.hw, ++ [CLK_APBC_UART8] = &uart8_clk.common.hw, ++ [CLK_APBC_UART9] = &uart9_clk.common.hw, ++ [CLK_APBC_UART10] = &uart10_clk.common.hw, ++ [CLK_APBC_UART0_BUS] = &uart0_bus_clk.common.hw, ++ [CLK_APBC_UART2_BUS] = &uart2_bus_clk.common.hw, ++ [CLK_APBC_UART3_BUS] = &uart3_bus_clk.common.hw, ++ [CLK_APBC_UART4_BUS] = &uart4_bus_clk.common.hw, ++ [CLK_APBC_UART5_BUS] = &uart5_bus_clk.common.hw, ++ [CLK_APBC_UART6_BUS] = &uart6_bus_clk.common.hw, ++ [CLK_APBC_UART7_BUS] = &uart7_bus_clk.common.hw, ++ [CLK_APBC_UART8_BUS] = &uart8_bus_clk.common.hw, ++ [CLK_APBC_UART9_BUS] = &uart9_bus_clk.common.hw, ++ [CLK_APBC_UART10_BUS] = &uart10_bus_clk.common.hw, ++ [CLK_APBC_GPIO] = &gpio_clk.common.hw, ++ [CLK_APBC_GPIO_BUS] = &gpio_bus_clk.common.hw, ++ [CLK_APBC_PWM0] = &pwm0_clk.common.hw, ++ [CLK_APBC_PWM1] = &pwm1_clk.common.hw, ++ [CLK_APBC_PWM2] = &pwm2_clk.common.hw, ++ [CLK_APBC_PWM3] = &pwm3_clk.common.hw, ++ [CLK_APBC_PWM4] = &pwm4_clk.common.hw, ++ [CLK_APBC_PWM5] = &pwm5_clk.common.hw, ++ [CLK_APBC_PWM6] = &pwm6_clk.common.hw, ++ [CLK_APBC_PWM7] = &pwm7_clk.common.hw, ++ [CLK_APBC_PWM8] = &pwm8_clk.common.hw, ++ [CLK_APBC_PWM9] = &pwm9_clk.common.hw, ++ [CLK_APBC_PWM10] = &pwm10_clk.common.hw, ++ [CLK_APBC_PWM11] = &pwm11_clk.common.hw, ++ [CLK_APBC_PWM12] = &pwm12_clk.common.hw, ++ [CLK_APBC_PWM13] = &pwm13_clk.common.hw, ++ [CLK_APBC_PWM14] = &pwm14_clk.common.hw, ++ [CLK_APBC_PWM15] = &pwm15_clk.common.hw, ++ [CLK_APBC_PWM16] = &pwm16_clk.common.hw, ++ [CLK_APBC_PWM17] = &pwm17_clk.common.hw, ++ [CLK_APBC_PWM18] = &pwm18_clk.common.hw, ++ [CLK_APBC_PWM19] = &pwm19_clk.common.hw, ++ [CLK_APBC_PWM0_BUS] = &pwm0_bus_clk.common.hw, ++ [CLK_APBC_PWM1_BUS] = &pwm1_bus_clk.common.hw, ++ [CLK_APBC_PWM2_BUS] = &pwm2_bus_clk.common.hw, ++ [CLK_APBC_PWM3_BUS] = &pwm3_bus_clk.common.hw, ++ [CLK_APBC_PWM4_BUS] = &pwm4_bus_clk.common.hw, ++ [CLK_APBC_PWM5_BUS] = &pwm5_bus_clk.common.hw, ++ [CLK_APBC_PWM6_BUS] = &pwm6_bus_clk.common.hw, ++ [CLK_APBC_PWM7_BUS] = &pwm7_bus_clk.common.hw, ++ [CLK_APBC_PWM8_BUS] = &pwm8_bus_clk.common.hw, ++ [CLK_APBC_PWM9_BUS] = &pwm9_bus_clk.common.hw, ++ [CLK_APBC_PWM10_BUS] = &pwm10_bus_clk.common.hw, ++ [CLK_APBC_PWM11_BUS] = &pwm11_bus_clk.common.hw, ++ [CLK_APBC_PWM12_BUS] = &pwm12_bus_clk.common.hw, ++ [CLK_APBC_PWM13_BUS] = &pwm13_bus_clk.common.hw, ++ [CLK_APBC_PWM14_BUS] = &pwm14_bus_clk.common.hw, ++ [CLK_APBC_PWM15_BUS] = &pwm15_bus_clk.common.hw, ++ [CLK_APBC_PWM16_BUS] = &pwm16_bus_clk.common.hw, ++ [CLK_APBC_PWM17_BUS] = &pwm17_bus_clk.common.hw, ++ [CLK_APBC_PWM18_BUS] = &pwm18_bus_clk.common.hw, ++ [CLK_APBC_PWM19_BUS] = &pwm19_bus_clk.common.hw, ++ [CLK_APBC_SPI0_I2S_BCLK] = &spi0_i2s_bclk.common.hw, ++ [CLK_APBC_SPI1_I2S_BCLK] = &spi1_i2s_bclk.common.hw, ++ [CLK_APBC_SPI3_I2S_BCLK] = &spi3_i2s_bclk.common.hw, ++ [CLK_APBC_SPI0] = &spi0_clk.common.hw, ++ [CLK_APBC_SPI1] = &spi1_clk.common.hw, ++ [CLK_APBC_SPI3] = &spi3_clk.common.hw, ++ [CLK_APBC_SPI0_BUS] = &spi0_bus_clk.common.hw, ++ [CLK_APBC_SPI1_BUS] = &spi1_bus_clk.common.hw, ++ [CLK_APBC_SPI3_BUS] = &spi3_bus_clk.common.hw, ++ [CLK_APBC_RTC] = &rtc_clk.common.hw, ++ [CLK_APBC_RTC_BUS] = &rtc_bus_clk.common.hw, ++ [CLK_APBC_TWSI0] = &twsi0_clk.common.hw, ++ [CLK_APBC_TWSI1] = &twsi1_clk.common.hw, ++ [CLK_APBC_TWSI2] = &twsi2_clk.common.hw, ++ [CLK_APBC_TWSI4] = &twsi4_clk.common.hw, ++ [CLK_APBC_TWSI5] = &twsi5_clk.common.hw, ++ [CLK_APBC_TWSI6] = &twsi6_clk.common.hw, ++ [CLK_APBC_TWSI8] = &twsi8_clk.common.hw, ++ [CLK_APBC_TWSI0_BUS] = &twsi0_bus_clk.common.hw, ++ [CLK_APBC_TWSI1_BUS] = &twsi1_bus_clk.common.hw, ++ [CLK_APBC_TWSI2_BUS] = &twsi2_bus_clk.common.hw, ++ [CLK_APBC_TWSI4_BUS] = &twsi4_bus_clk.common.hw, ++ [CLK_APBC_TWSI5_BUS] = &twsi5_bus_clk.common.hw, ++ [CLK_APBC_TWSI6_BUS] = &twsi6_bus_clk.common.hw, ++ [CLK_APBC_TWSI8_BUS] = &twsi8_bus_clk.common.hw, ++ [CLK_APBC_TIMERS0] = &timers0_clk.common.hw, ++ [CLK_APBC_TIMERS1] = &timers1_clk.common.hw, ++ [CLK_APBC_TIMERS2] = &timers2_clk.common.hw, ++ [CLK_APBC_TIMERS3] = &timers3_clk.common.hw, ++ [CLK_APBC_TIMERS4] = &timers4_clk.common.hw, ++ [CLK_APBC_TIMERS5] = &timers5_clk.common.hw, ++ [CLK_APBC_TIMERS6] = &timers6_clk.common.hw, ++ [CLK_APBC_TIMERS7] = &timers7_clk.common.hw, ++ [CLK_APBC_TIMERS0_BUS] = &timers0_bus_clk.common.hw, ++ [CLK_APBC_TIMERS1_BUS] = &timers1_bus_clk.common.hw, ++ [CLK_APBC_TIMERS2_BUS] = &timers2_bus_clk.common.hw, ++ [CLK_APBC_TIMERS3_BUS] = &timers3_bus_clk.common.hw, ++ [CLK_APBC_TIMERS4_BUS] = &timers4_bus_clk.common.hw, ++ [CLK_APBC_TIMERS5_BUS] = &timers5_bus_clk.common.hw, ++ [CLK_APBC_TIMERS6_BUS] = &timers6_bus_clk.common.hw, ++ [CLK_APBC_TIMERS7_BUS] = &timers7_bus_clk.common.hw, ++ [CLK_APBC_AIB] = &aib_clk.common.hw, ++ [CLK_APBC_AIB_BUS] = &aib_bus_clk.common.hw, ++ [CLK_APBC_ONEWIRE] = &onewire_clk.common.hw, ++ [CLK_APBC_ONEWIRE_BUS] = &onewire_bus_clk.common.hw, ++ [CLK_APBC_I2S0_BCLK] = &i2s0_i2s_bclk.common.hw, ++ [CLK_APBC_I2S1_BCLK] = &i2s1_i2s_bclk.common.hw, ++ [CLK_APBC_I2S2_BCLK] = &i2s2_i2s_bclk.common.hw, ++ [CLK_APBC_I2S3_BCLK] = &i2s3_i2s_bclk.common.hw, ++ [CLK_APBC_I2S4_BCLK] = &i2s4_i2s_bclk.common.hw, ++ [CLK_APBC_I2S5_BCLK] = &i2s5_i2s_bclk.common.hw, ++ [CLK_APBC_I2S0] = &i2s0_clk.common.hw, ++ [CLK_APBC_I2S1] = &i2s1_clk.common.hw, ++ [CLK_APBC_I2S2] = &i2s2_clk.common.hw, ++ [CLK_APBC_I2S3] = &i2s3_clk.common.hw, ++ [CLK_APBC_I2S4] = &i2s4_clk.common.hw, ++ [CLK_APBC_I2S5] = &i2s5_clk.common.hw, ++ [CLK_APBC_I2S0_BUS] = &i2s0_bus_clk.common.hw, ++ [CLK_APBC_I2S1_BUS] = &i2s1_bus_clk.common.hw, ++ [CLK_APBC_I2S2_BUS] = &i2s2_bus_clk.common.hw, ++ [CLK_APBC_I2S3_BUS] = &i2s3_bus_clk.common.hw, ++ [CLK_APBC_I2S4_BUS] = &i2s4_bus_clk.common.hw, ++ [CLK_APBC_I2S5_BUS] = &i2s5_bus_clk.common.hw, ++ [CLK_APBC_DRO] = &dro_clk.common.hw, ++ [CLK_APBC_IR0] = &ir0_clk.common.hw, ++ [CLK_APBC_IR1] = &ir1_clk.common.hw, ++ [CLK_APBC_TSEN] = &tsen_clk.common.hw, ++ [CLK_APBC_TSEN_BUS] = &tsen_bus_clk.common.hw, ++ [CLK_APBC_IPC_AP2RCPU] = &ipc_ap2rcpu_clk.common.hw, ++ [CLK_APBC_IPC_AP2RCPU_BUS] = &ipc_ap2rcpu_bus_clk.common.hw, ++ [CLK_APBC_CAN0] = &can0_clk.common.hw, ++ [CLK_APBC_CAN1] = &can1_clk.common.hw, ++ [CLK_APBC_CAN2] = &can2_clk.common.hw, ++ [CLK_APBC_CAN3] = &can3_clk.common.hw, ++ [CLK_APBC_CAN4] = &can4_clk.common.hw, ++ [CLK_APBC_CAN0_BUS] = &can0_bus_clk.common.hw, ++ [CLK_APBC_CAN1_BUS] = &can1_bus_clk.common.hw, ++ [CLK_APBC_CAN2_BUS] = &can2_bus_clk.common.hw, ++ [CLK_APBC_CAN3_BUS] = &can3_bus_clk.common.hw, ++ [CLK_APBC_CAN4_BUS] = &can4_bus_clk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_apbc_data = { ++ .reset_name = "k3-apbc-reset", ++ .hws = k3_ccu_apbc_hws, ++ .num = ARRAY_SIZE(k3_ccu_apbc_hws), ++}; ++ ++static struct clk_hw *k3_ccu_apmu_hws[] = { ++ [CLK_APMU_AXICLK] = &axi_clk.common.hw, ++ [CLK_APMU_CCI550] = &cci550_clk.common.hw, ++ [CLK_APMU_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw, ++ [CLK_APMU_CPU_C1_CORE] = &cpu_c1_core_clk.common.hw, ++ [CLK_APMU_CPU_C2_CORE] = &cpu_c2_core_clk.common.hw, ++ [CLK_APMU_CPU_C3_CORE] = &cpu_c3_core_clk.common.hw, ++ [CLK_APMU_CCIC2PHY] = &ccic2phy_clk.common.hw, ++ [CLK_APMU_CCIC3PHY] = &ccic3phy_clk.common.hw, ++ [CLK_APMU_CSI] = &csi_clk.common.hw, ++ [CLK_APMU_ISP_BUS] = &isp_bus_clk.common.hw, ++ [CLK_APMU_D1P_1228P8] = &d1p_1228p8.common.hw, ++ [CLK_APMU_D1P_819P2] = &d1p_819p2.common.hw, ++ [CLK_APMU_D1P_614P4] = &d1p_614p4.common.hw, ++ [CLK_APMU_D1P_491P52] = &d1p_491p52.common.hw, ++ [CLK_APMU_D1P_409P6] = &d1p_409p6.common.hw, ++ [CLK_APMU_D1P_307P2] = &d1p_307p2.common.hw, ++ [CLK_APMU_D1P_245P76] = &d1p_245p76.common.hw, ++ [CLK_APMU_V2D] = &v2d_clk.common.hw, ++ [CLK_APMU_DSI_ESC] = &dsi_esc_clk.common.hw, ++ [CLK_APMU_LCD_HCLK] = &lcd_hclk.common.hw, ++ [CLK_APMU_LCD_DSC] = &lcd_dsc_clk.common.hw, ++ [CLK_APMU_LCD_PXCLK] = &lcd_pxclk.common.hw, ++ [CLK_APMU_LCD_MCLK] = &lcd_mclk.common.hw, ++ [CLK_APMU_CCIC_4X] = &ccic_4x_clk.common.hw, ++ [CLK_APMU_CCIC1PHY] = &ccic1phy_clk.common.hw, ++ [CLK_APMU_SC2_HCLK] = &sc2_hclk.common.hw, ++ [CLK_APMU_SDH_AXI] = &sdh_axi_aclk.common.hw, ++ [CLK_APMU_SDH0] = &sdh0_clk.common.hw, ++ [CLK_APMU_SDH1] = &sdh1_clk.common.hw, ++ [CLK_APMU_SDH2] = &sdh2_clk.common.hw, ++ [CLK_APMU_USB2_BUS] = &usb2_bus_clk.common.hw, ++ [CLK_APMU_USB3_PORTA_BUS] = &usb3_porta_bus_clk.common.hw, ++ [CLK_APMU_USB3_PORTB_BUS] = &usb3_portb_bus_clk.common.hw, ++ [CLK_APMU_USB3_PORTC_BUS] = &usb3_portc_bus_clk.common.hw, ++ [CLK_APMU_USB3_PORTD_BUS] = &usb3_portd_bus_clk.common.hw, ++ [CLK_APMU_QSPI] = &qspi_clk.common.hw, ++ [CLK_APMU_QSPI_BUS] = &qspi_bus_clk.common.hw, ++ [CLK_APMU_DMA] = &dma_clk.common.hw, ++ [CLK_APMU_AES_WTM] = &aes_wtm_clk.common.hw, ++ [CLK_APMU_VPU] = &vpu_clk.common.hw, ++ [CLK_APMU_DTC] = &dtc_clk.common.hw, ++ [CLK_APMU_GPU] = &gpu_clk.common.hw, ++ [CLK_APMU_MC_AHB] = &mc_ahb_clk.common.hw, ++ [CLK_APMU_TOP_DCLK] = &top_dclk.common.hw, ++ [CLK_APMU_UCIE] = &ucie_clk.common.hw, ++ [CLK_APMU_UCIE_SBCLK] = &ucie_sbclk.common.hw, ++ [CLK_APMU_RCPU] = &rcpu_clk.common.hw, ++ [CLK_APMU_DSI4LN2_DSI_ESC] = &dsi4ln2_dsi_esc_clk.common.hw, ++ [CLK_APMU_DSI4LN2_LCD_DSC] = &dsi4ln2_lcd_dsc_clk.common.hw, ++ [CLK_APMU_DSI4LN2_LCD_PXCLK] = &dsi4ln2_lcd_pxclk.common.hw, ++ [CLK_APMU_DSI4LN2_LCD_MCLK] = &dsi4ln2_lcd_mclk.common.hw, ++ [CLK_APMU_DSI4LN2_DPU_ACLK] = &dsi4ln2_dpu_aclk.common.hw, ++ [CLK_APMU_DPU_ACLK] = &dpu_aclk.common.hw, ++ [CLK_APMU_UFS_ACLK] = &ufs_aclk.common.hw, ++ [CLK_APMU_EDP0_PXCLK] = &edp0_pxclk.common.hw, ++ [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, ++ [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw, ++ [CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw, ++ [CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw, ++ [CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw, ++ [CLK_APMU_EMAC0_RGMII_TX] = &emac0_rgmii_tx_clk.common.hw, ++ [CLK_APMU_EMAC1_BUS] = &emac1_bus_clk.common.hw, ++ [CLK_APMU_EMAC1_REF] = &emac1_ref_clk.common.hw, ++ [CLK_APMU_EMAC1_1588] = &emac1_1588_clk.common.hw, ++ [CLK_APMU_EMAC1_RGMII_TX] = &emac1_rgmii_tx_clk.common.hw, ++ [CLK_APMU_EMAC2_BUS] = &emac2_bus_clk.common.hw, ++ [CLK_APMU_EMAC2_REF] = &emac2_ref_clk.common.hw, ++ [CLK_APMU_EMAC2_1588] = &emac2_1588_clk.common.hw, ++ [CLK_APMU_EMAC2_RGMII_TX] = &emac2_rgmii_tx_clk.common.hw, ++ [CLK_APMU_ESPI_SCLK_SRC] = &espi_sclk_src.common.hw, ++ [CLK_APMU_ESPI_SCLK] = &espi_sclk.common.hw, ++ [CLK_APMU_ESPI_MCLK] = &espi_mclk.common.hw, ++ [CLK_APMU_CAM_SRC1] = &cam_src1_clk.common.hw, ++ [CLK_APMU_CAM_SRC2] = &cam_src2_clk.common.hw, ++ [CLK_APMU_CAM_SRC3] = &cam_src3_clk.common.hw, ++ [CLK_APMU_CAM_SRC4] = &cam_src4_clk.common.hw, ++ [CLK_APMU_ISIM_VCLK0] = &isim_vclk_out0.common.hw, ++ [CLK_APMU_ISIM_VCLK1] = &isim_vclk_out1.common.hw, ++ [CLK_APMU_ISIM_VCLK2] = &isim_vclk_out2.common.hw, ++ [CLK_APMU_ISIM_VCLK3] = &isim_vclk_out3.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_apmu_data = { ++ .reset_name = "k3-apmu-reset", ++ .hws = k3_ccu_apmu_hws, ++ .num = ARRAY_SIZE(k3_ccu_apmu_hws), ++}; ++ ++static struct clk_hw *k3_ccu_dciu_hws[] = { ++ [CLK_DCIU_HDMA] = &hdma_clk.common.hw, ++ [CLK_DCIU_DMA350] = &dma350_clk.common.hw, ++ [CLK_DCIU_C2_TCM_PIPE] = &c2_tcm_pipe_clk.common.hw, ++ [CLK_DCIU_C3_TCM_PIPE] = &c3_tcm_pipe_clk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_dciu_data = { ++ .reset_name = "k3-dciu-reset", ++ .hws = k3_ccu_dciu_hws, ++ .num = ARRAY_SIZE(k3_ccu_dciu_hws), ++}; ++ ++static const struct of_device_id of_k3_ccu_match[] = { ++ { ++ .compatible = "spacemit,k3-pll", ++ .data = &k3_ccu_pll_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-mpmu", ++ .data = &k3_ccu_mpmu_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-apbc", ++ .data = &k3_ccu_apbc_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-apmu", ++ .data = &k3_ccu_apmu_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-dciu", ++ .data = &k3_ccu_dciu_data, ++ }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, of_k3_ccu_match); ++ ++static int k3_ccu_probe(struct platform_device *pdev) ++{ ++ return spacemit_ccu_probe(pdev, "spacemit,k3-pll"); ++} ++ ++static struct platform_driver k3_ccu_driver = { ++ .driver = { ++ .name = "spacemit,k3-ccu", ++ .of_match_table = of_k3_ccu_match, ++ }, ++ .probe = k3_ccu_probe, ++}; ++module_platform_driver(k3_ccu_driver); ++ ++MODULE_IMPORT_NS("CLK_SPACEMIT"); ++MODULE_DESCRIPTION("SpacemiT K3 CCU driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0121-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch b/SPECS/linux-lts-kmhv2/0121-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch deleted file mode 100644 index 31fdf94a99..0000000000 --- a/SPECS/linux-lts-kmhv2/0121-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch +++ /dev/null @@ -1,285 +0,0 @@ -From 8a1339992d26116b2566f2ad5313da25901e4b2a Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 27 Oct 2025 21:41:24 +0800 -Subject: [PATCH 121/467] UPSTREAM: clk: spacemit: ccu_pll: add plla type clock - -Introduce a new clock PLLA for SpacemiT's K3 SoC which has a different -register layout comparing to previous PPL type. And, It is configured -by swcr1, swcr3 and swcr2 BIT[15:8]. - -Link: https://lore.kernel.org/r/20260108-k3-clk-v5-3-42a11b74ad58@gentoo.org -Signed-off-by: Yixun Lan -(cherry picked from commit 3a086236c600739d6653c0405d86aff7d6f03c06) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu_common.h | 1 + - drivers/clk/spacemit/ccu_pll.c | 118 ++++++++++++++++++++++++++++++ - drivers/clk/spacemit/ccu_pll.h | 57 ++++++++++++--- - 3 files changed, 166 insertions(+), 10 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h -index 7ae244b5eace..8691698e007d 100644 ---- a/drivers/clk/spacemit/ccu_common.h -+++ b/drivers/clk/spacemit/ccu_common.h -@@ -26,6 +26,7 @@ struct ccu_common { - /* For PLL */ - struct { - u32 reg_swcr1; -+ u32 reg_swcr2; - u32 reg_swcr3; - }; - }; -diff --git a/drivers/clk/spacemit/ccu_pll.c b/drivers/clk/spacemit/ccu_pll.c -index 76d0244873d8..d4066a0ed452 100644 ---- a/drivers/clk/spacemit/ccu_pll.c -+++ b/drivers/clk/spacemit/ccu_pll.c -@@ -17,6 +17,9 @@ - #define PLL_SWCR3_EN ((u32)BIT(31)) - #define PLL_SWCR3_MASK GENMASK(30, 0) - -+#define PLLA_SWCR2_EN ((u32)BIT(16)) -+#define PLLA_SWCR2_MASK GENMASK(15, 8) -+ - static const struct ccu_pll_rate_tbl *ccu_pll_lookup_best_rate(struct ccu_pll *pll, - unsigned long rate) - { -@@ -148,6 +151,110 @@ static int ccu_pll_init(struct clk_hw *hw) - return 0; - } - -+static const struct ccu_pll_rate_tbl *ccu_plla_lookup_matched_entry(struct ccu_pll *pll) -+{ -+ struct ccu_pll_config *config = &pll->config; -+ const struct ccu_pll_rate_tbl *entry; -+ u32 i, swcr1, swcr2, swcr3; -+ -+ swcr1 = ccu_read(&pll->common, swcr1); -+ swcr2 = ccu_read(&pll->common, swcr2); -+ swcr2 &= PLLA_SWCR2_MASK; -+ swcr3 = ccu_read(&pll->common, swcr3); -+ -+ for (i = 0; i < config->tbl_num; i++) { -+ entry = &config->rate_tbl[i]; -+ -+ if (swcr1 == entry->swcr1 && -+ swcr2 == entry->swcr2 && -+ swcr3 == entry->swcr3) -+ return entry; -+ } -+ -+ return NULL; -+} -+ -+static void ccu_plla_update_param(struct ccu_pll *pll, const struct ccu_pll_rate_tbl *entry) -+{ -+ struct ccu_common *common = &pll->common; -+ -+ regmap_write(common->regmap, common->reg_swcr1, entry->swcr1); -+ regmap_write(common->regmap, common->reg_swcr3, entry->swcr3); -+ ccu_update(common, swcr2, PLLA_SWCR2_MASK, entry->swcr2); -+} -+ -+static int ccu_plla_is_enabled(struct clk_hw *hw) -+{ -+ struct ccu_common *common = hw_to_ccu_common(hw); -+ -+ return ccu_read(common, swcr2) & PLLA_SWCR2_EN; -+} -+ -+static int ccu_plla_enable(struct clk_hw *hw) -+{ -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ struct ccu_common *common = &pll->common; -+ unsigned int tmp; -+ -+ ccu_update(common, swcr2, PLLA_SWCR2_EN, PLLA_SWCR2_EN); -+ -+ /* check lock status */ -+ return regmap_read_poll_timeout_atomic(common->lock_regmap, -+ pll->config.reg_lock, -+ tmp, -+ tmp & pll->config.mask_lock, -+ PLL_DELAY_US, PLL_TIMEOUT_US); -+} -+ -+static void ccu_plla_disable(struct clk_hw *hw) -+{ -+ struct ccu_common *common = hw_to_ccu_common(hw); -+ -+ ccu_update(common, swcr2, PLLA_SWCR2_EN, 0); -+} -+ -+/* -+ * PLLAs must be gated before changing rate, which is ensured by -+ * flag CLK_SET_RATE_GATE. -+ */ -+static int ccu_plla_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ const struct ccu_pll_rate_tbl *entry; -+ -+ entry = ccu_pll_lookup_best_rate(pll, rate); -+ ccu_plla_update_param(pll, entry); -+ -+ return 0; -+} -+ -+static unsigned long ccu_plla_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ const struct ccu_pll_rate_tbl *entry; -+ -+ entry = ccu_plla_lookup_matched_entry(pll); -+ -+ WARN_ON_ONCE(!entry); -+ -+ return entry ? entry->rate : 0; -+} -+ -+static int ccu_plla_init(struct clk_hw *hw) -+{ -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ -+ if (ccu_plla_lookup_matched_entry(pll)) -+ return 0; -+ -+ ccu_plla_disable(hw); -+ ccu_plla_update_param(pll, &pll->config.rate_tbl[0]); -+ -+ return 0; -+} -+ - const struct clk_ops spacemit_ccu_pll_ops = { - .init = ccu_pll_init, - .enable = ccu_pll_enable, -@@ -158,3 +265,14 @@ const struct clk_ops spacemit_ccu_pll_ops = { - .is_enabled = ccu_pll_is_enabled, - }; - EXPORT_SYMBOL_NS_GPL(spacemit_ccu_pll_ops, "CLK_SPACEMIT"); -+ -+const struct clk_ops spacemit_ccu_plla_ops = { -+ .init = ccu_plla_init, -+ .enable = ccu_plla_enable, -+ .disable = ccu_plla_disable, -+ .set_rate = ccu_plla_set_rate, -+ .recalc_rate = ccu_plla_recalc_rate, -+ .determine_rate = ccu_pll_determine_rate, -+ .is_enabled = ccu_plla_is_enabled, -+}; -+EXPORT_SYMBOL_NS_GPL(spacemit_ccu_plla_ops, "CLK_SPACEMIT"); -diff --git a/drivers/clk/spacemit/ccu_pll.h b/drivers/clk/spacemit/ccu_pll.h -index 0592f4c3068c..e41db5c97c1a 100644 ---- a/drivers/clk/spacemit/ccu_pll.h -+++ b/drivers/clk/spacemit/ccu_pll.h -@@ -16,14 +16,31 @@ - * configuration. - * - * @rate: PLL rate -- * @swcr1: Register value of PLLX_SW1_CTRL (PLLx_SWCR1). -- * @swcr3: Register value of the PLLx_SW3_CTRL's lowest 31 bits of -- * PLLx_SW3_CTRL (PLLx_SWCR3). This highest bit is for enabling -- * the PLL and not contained in this field. -+ * @swcr1: Value of register PLLx_SW1_CTRL. -+ * @swcr2: Value of register PLLAx_SW2_CTRL. -+ * @swcr3: value of register PLLx_SW3_CTRL. -+ * -+ * See below tables for the register used in PPL/PPLA clocks -+ * -+ * Regular PLL type -+ * | Enable | swcr3 | PLLx_SW3_CTRL - BIT[31] | -+ * ----------------------------------------------- -+ * | Config | swcr1 | PLLx_SW1_CTRL - BIT[31:0] | -+ * | | swcr2 | Not used | -+ * | | swcr3 | PLLx_SW3_CTRL - BIT[30:0] | -+ * -+ * Special PLL type A -+ * | Enable | swcr2 | PLLAx_SW2_CTRL - BIT[16] | -+ * ----------------------------------------------- -+ * | Config | swcr1 | PLLAx_SW1_CTRL - BIT[31:0] | -+ * | | swcr2 | PLLAx_SW2_CTRL - BIT[15:8] | -+ * | | swcr3 | PLLAx_SW3_CTRL - BIT[31:0] | -+ * - */ - struct ccu_pll_rate_tbl { - unsigned long rate; - u32 swcr1; -+ u32 swcr2; - u32 swcr3; - }; - -@@ -36,11 +53,19 @@ struct ccu_pll_config { - - #define CCU_PLL_RATE(_rate, _swcr1, _swcr3) \ - { \ -- .rate = _rate, \ -+ .rate = _rate, \ - .swcr1 = _swcr1, \ - .swcr3 = _swcr3, \ - } - -+#define CCU_PLLA_RATE(_rate, _swcr1, _swcr2, _swcr3) \ -+ { \ -+ .rate = _rate, \ -+ .swcr1 = _swcr1, \ -+ .swcr2 = _swcr2, \ -+ .swcr3 = _swcr3, \ -+ } -+ - struct ccu_pll { - struct ccu_common common; - struct ccu_pll_config config; -@@ -54,26 +79,37 @@ struct ccu_pll { - .mask_lock = (_mask_lock), \ - } - --#define CCU_PLL_HWINIT(_name, _flags) \ -+#define CCU_PLL_COMMON_HWINIT(_name, _ops, _flags) \ - (&(struct clk_init_data) { \ - .name = #_name, \ -- .ops = &spacemit_ccu_pll_ops, \ -+ .ops = _ops, \ - .parent_data = &(struct clk_parent_data) { .index = 0 }, \ - .num_parents = 1, \ - .flags = _flags, \ - }) - --#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \ -- _mask_lock, _flags) \ -+#define CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ -+ _reg_lock, _mask_lock, _ops, _flags) \ - static struct ccu_pll _name = { \ - .config = CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock), \ - .common = { \ - .reg_swcr1 = _reg_swcr1, \ -+ .reg_swcr2 = _reg_swcr2, \ - .reg_swcr3 = _reg_swcr3, \ -- .hw.init = CCU_PLL_HWINIT(_name, _flags) \ -+ .hw.init = CCU_PLL_COMMON_HWINIT(_name, _ops, _flags) \ - } \ - } - -+#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \ -+ _mask_lock, _flags) \ -+ CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, 0, _reg_swcr3, \ -+ _reg_lock, _mask_lock, &spacemit_ccu_pll_ops, _flags) -+ -+#define CCU_PLLA_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ -+ _reg_lock, _mask_lock, _flags) \ -+ CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ -+ _reg_lock, _mask_lock, &spacemit_ccu_plla_ops, _flags) -+ - static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw) - { - struct ccu_common *common = hw_to_ccu_common(hw); -@@ -82,5 +118,6 @@ static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw) - } - - extern const struct clk_ops spacemit_ccu_pll_ops; -+extern const struct clk_ops spacemit_ccu_plla_ops; - - #endif --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch b/SPECS/linux-lts-kmhv2/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch new file mode 100644 index 0000000000..c049403590 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch @@ -0,0 +1,235 @@ +From c8b8aab18243d5ad3ee4a6b980f1448aee344adb Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 20 Jan 2026 19:10:49 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: soc: spacemit: Add K3 reset + support and IDs + +Update the spacemit,k1-syscon.yaml binding to document K3 SoC reset +support. + +K3 reset devices are registered at runtime as auxiliary devices by the +K3 CCU driver. Since K3 reuses the K1 syscon binding, there is no separate +YAML binding file for K3 resets. + +Update #reset-cells description to document where reset IDs are defined. + +Acked-by: Alex Elder +Acked-by: Krzysztof Kozlowski +Signed-off-by: Guodong Xu +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] +Signed-off-by: Philipp Zabel +(cherry picked from commit 216e0a5e98e5f0f02a818884e8acf340892cecae) +Signed-off-by: Han Gao +--- + .../soc/spacemit/spacemit,k1-syscon.yaml | 8 +- + .../dt-bindings/reset/spacemit,k3-resets.h | 171 ++++++++++++++++++ + 2 files changed, 178 insertions(+), 1 deletion(-) + create mode 100644 include/dt-bindings/reset/spacemit,k3-resets.h + +diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +index d87131da30bc..d3a7c93c3c54 100644 +--- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml ++++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +@@ -10,7 +10,7 @@ maintainers: + - Haylen Chu + + description: +- System controllers found on SpacemiT K1 SoC, which are capable of ++ System controllers found on SpacemiT K1/K3 SoC, which are capable of + clock, reset and power-management functions. + + properties: +@@ -51,6 +51,12 @@ properties: + + "#reset-cells": + const: 1 ++ description: | ++ ID of the reset controller line. Valid IDs are defined in corresponding ++ files: ++ ++ For SpacemiT K1, see include/dt-bindings/clock/spacemit,k1-syscon.h ++ For SpacemiT K3, see include/dt-bindings/reset/spacemit,k3-resets.h + + required: + - compatible +diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h +new file mode 100644 +index 000000000000..79ac1c22b7b5 +--- /dev/null ++++ b/include/dt-bindings/reset/spacemit,k3-resets.h +@@ -0,0 +1,171 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ ++ ++#ifndef _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ ++#define _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ ++ ++/* MPMU resets */ ++#define RESET_MPMU_WDT 0 ++#define RESET_MPMU_RIPC 1 ++ ++/* APBC resets */ ++#define RESET_APBC_UART0 0 ++#define RESET_APBC_UART2 1 ++#define RESET_APBC_UART3 2 ++#define RESET_APBC_UART4 3 ++#define RESET_APBC_UART5 4 ++#define RESET_APBC_UART6 5 ++#define RESET_APBC_UART7 6 ++#define RESET_APBC_UART8 7 ++#define RESET_APBC_UART9 8 ++#define RESET_APBC_UART10 9 ++#define RESET_APBC_GPIO 10 ++#define RESET_APBC_PWM0 11 ++#define RESET_APBC_PWM1 12 ++#define RESET_APBC_PWM2 13 ++#define RESET_APBC_PWM3 14 ++#define RESET_APBC_PWM4 15 ++#define RESET_APBC_PWM5 16 ++#define RESET_APBC_PWM6 17 ++#define RESET_APBC_PWM7 18 ++#define RESET_APBC_PWM8 19 ++#define RESET_APBC_PWM9 20 ++#define RESET_APBC_PWM10 21 ++#define RESET_APBC_PWM11 22 ++#define RESET_APBC_PWM12 23 ++#define RESET_APBC_PWM13 24 ++#define RESET_APBC_PWM14 25 ++#define RESET_APBC_PWM15 26 ++#define RESET_APBC_PWM16 27 ++#define RESET_APBC_PWM17 28 ++#define RESET_APBC_PWM18 29 ++#define RESET_APBC_PWM19 30 ++#define RESET_APBC_SPI0 31 ++#define RESET_APBC_SPI1 32 ++#define RESET_APBC_SPI3 33 ++#define RESET_APBC_RTC 34 ++#define RESET_APBC_TWSI0 35 ++#define RESET_APBC_TWSI1 36 ++#define RESET_APBC_TWSI2 37 ++#define RESET_APBC_TWSI4 38 ++#define RESET_APBC_TWSI5 39 ++#define RESET_APBC_TWSI6 40 ++#define RESET_APBC_TWSI8 41 ++#define RESET_APBC_TIMERS0 42 ++#define RESET_APBC_TIMERS1 43 ++#define RESET_APBC_TIMERS2 44 ++#define RESET_APBC_TIMERS3 45 ++#define RESET_APBC_TIMERS4 46 ++#define RESET_APBC_TIMERS5 47 ++#define RESET_APBC_TIMERS6 48 ++#define RESET_APBC_TIMERS7 49 ++#define RESET_APBC_AIB 50 ++#define RESET_APBC_ONEWIRE 51 ++#define RESET_APBC_I2S0 52 ++#define RESET_APBC_I2S1 53 ++#define RESET_APBC_I2S2 54 ++#define RESET_APBC_I2S3 55 ++#define RESET_APBC_I2S4 56 ++#define RESET_APBC_I2S5 57 ++#define RESET_APBC_DRO 58 ++#define RESET_APBC_IR0 59 ++#define RESET_APBC_IR1 60 ++#define RESET_APBC_TSEN 61 ++#define RESET_IPC_AP2AUD 62 ++#define RESET_APBC_CAN0 63 ++#define RESET_APBC_CAN1 64 ++#define RESET_APBC_CAN2 65 ++#define RESET_APBC_CAN3 66 ++#define RESET_APBC_CAN4 67 ++ ++/* APMU resets */ ++#define RESET_APMU_CSI 0 ++#define RESET_APMU_CCIC2PHY 1 ++#define RESET_APMU_CCIC3PHY 2 ++#define RESET_APMU_ISP_CIBUS 3 ++#define RESET_APMU_DSI_ESC 4 ++#define RESET_APMU_LCD 5 ++#define RESET_APMU_V2D 6 ++#define RESET_APMU_LCD_MCLK 7 ++#define RESET_APMU_LCD_DSCCLK 8 ++#define RESET_APMU_SC2_HCLK 9 ++#define RESET_APMU_CCIC_4X 10 ++#define RESET_APMU_CCIC1_PHY 11 ++#define RESET_APMU_SDH_AXI 12 ++#define RESET_APMU_SDH0 13 ++#define RESET_APMU_SDH1 14 ++#define RESET_APMU_SDH2 15 ++#define RESET_APMU_USB2 16 ++#define RESET_APMU_USB3_PORTA 17 ++#define RESET_APMU_USB3_PORTB 18 ++#define RESET_APMU_USB3_PORTC 19 ++#define RESET_APMU_USB3_PORTD 20 ++#define RESET_APMU_QSPI 21 ++#define RESET_APMU_QSPI_BUS 22 ++#define RESET_APMU_DMA 23 ++#define RESET_APMU_AES_WTM 24 ++#define RESET_APMU_MCB_DCLK 25 ++#define RESET_APMU_MCB_ACLK 26 ++#define RESET_APMU_VPU 27 ++#define RESET_APMU_DTC 28 ++#define RESET_APMU_GPU 29 ++#define RESET_APMU_ALZO 30 ++#define RESET_APMU_MC 31 ++#define RESET_APMU_CPU0_POP 32 ++#define RESET_APMU_CPU0_SW 33 ++#define RESET_APMU_CPU1_POP 34 ++#define RESET_APMU_CPU1_SW 35 ++#define RESET_APMU_CPU2_POP 36 ++#define RESET_APMU_CPU2_SW 37 ++#define RESET_APMU_CPU3_POP 38 ++#define RESET_APMU_CPU3_SW 39 ++#define RESET_APMU_C0_MPSUB_SW 40 ++#define RESET_APMU_CPU4_POP 41 ++#define RESET_APMU_CPU4_SW 42 ++#define RESET_APMU_CPU5_POP 43 ++#define RESET_APMU_CPU5_SW 44 ++#define RESET_APMU_CPU6_POP 45 ++#define RESET_APMU_CPU6_SW 46 ++#define RESET_APMU_CPU7_POP 47 ++#define RESET_APMU_CPU7_SW 48 ++#define RESET_APMU_C1_MPSUB_SW 49 ++#define RESET_APMU_MPSUB_DBG 50 ++#define RESET_APMU_UCIE 51 ++#define RESET_APMU_RCPU 52 ++#define RESET_APMU_DSI4LN2_ESCCLK 53 ++#define RESET_APMU_DSI4LN2_LCD_SW 54 ++#define RESET_APMU_DSI4LN2_LCD_MCLK 55 ++#define RESET_APMU_DSI4LN2_LCD_DSCCLK 56 ++#define RESET_APMU_DSI4LN2_DPU_ACLK 57 ++#define RESET_APMU_DPU_ACLK 58 ++#define RESET_APMU_UFS_ACLK 59 ++#define RESET_APMU_EDP0 60 ++#define RESET_APMU_EDP1 61 ++#define RESET_APMU_PCIE_PORTA 62 ++#define RESET_APMU_PCIE_PORTB 63 ++#define RESET_APMU_PCIE_PORTC 64 ++#define RESET_APMU_PCIE_PORTD 65 ++#define RESET_APMU_PCIE_PORTE 66 ++#define RESET_APMU_EMAC0 67 ++#define RESET_APMU_EMAC1 68 ++#define RESET_APMU_EMAC2 69 ++#define RESET_APMU_ESPI_MCLK 70 ++#define RESET_APMU_ESPI_SCLK 71 ++ ++/* DCIU resets*/ ++#define RESET_DCIU_HDMA 0 ++#define RESET_DCIU_DMA350 1 ++#define RESET_DCIU_DMA350_0 2 ++#define RESET_DCIU_DMA350_1 3 ++#define RESET_DCIU_AXIDMA0 4 ++#define RESET_DCIU_AXIDMA1 5 ++#define RESET_DCIU_AXIDMA2 6 ++#define RESET_DCIU_AXIDMA3 7 ++#define RESET_DCIU_AXIDMA4 8 ++#define RESET_DCIU_AXIDMA5 9 ++#define RESET_DCIU_AXIDMA6 10 ++#define RESET_DCIU_AXIDMA7 11 ++ ++#endif /* _DT_BINDINGS_RESET_SPACEMIT_K3_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0122-UPSTREAM-clk-spacemit-k3-extract-common-header.patch b/SPECS/linux-lts-kmhv2/0122-UPSTREAM-clk-spacemit-k3-extract-common-header.patch deleted file mode 100644 index deefe5b921..0000000000 --- a/SPECS/linux-lts-kmhv2/0122-UPSTREAM-clk-spacemit-k3-extract-common-header.patch +++ /dev/null @@ -1,299 +0,0 @@ -From 3b39ff3c0baef35c207ed2fe3f34137a9a874573 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sat, 20 Dec 2025 21:28:15 +0800 -Subject: [PATCH 122/467] UPSTREAM: clk: spacemit: k3: extract common header - -Extracting common header file, which will be shared by clock and reset -drivers. So will make it easy to add reset driver for K3 SoC later. - -Link: https://lore.kernel.org/r/20260108-k3-clk-v5-4-42a11b74ad58@gentoo.org -Signed-off-by: Yixun Lan -(cherry picked from commit 091d19cc24018f2bd783e932fb2403cb7a2bdb3c) -Signed-off-by: Han Gao ---- - include/soc/spacemit/k3-syscon.h | 273 +++++++++++++++++++++++++++++++ - 1 file changed, 273 insertions(+) - create mode 100644 include/soc/spacemit/k3-syscon.h - -diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h -new file mode 100644 -index 000000000000..0299bea065a0 ---- /dev/null -+++ b/include/soc/spacemit/k3-syscon.h -@@ -0,0 +1,273 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* SpacemiT clock and reset driver definitions for the K3 SoC */ -+ -+#ifndef __SOC_K3_SYSCON_H__ -+#define __SOC_K3_SYSCON_H__ -+ -+#include "ccu.h" -+ -+/* APBS register offset */ -+#define APBS_PLL1_SWCR1 0x100 -+#define APBS_PLL1_SWCR2 0x104 -+#define APBS_PLL1_SWCR3 0x108 -+#define APBS_PLL2_SWCR1 0x118 -+#define APBS_PLL2_SWCR2 0x11c -+#define APBS_PLL2_SWCR3 0x120 -+#define APBS_PLL3_SWCR1 0x124 -+#define APBS_PLL3_SWCR2 0x128 -+#define APBS_PLL3_SWCR3 0x12c -+#define APBS_PLL4_SWCR1 0x130 -+#define APBS_PLL4_SWCR2 0x134 -+#define APBS_PLL4_SWCR3 0x138 -+#define APBS_PLL5_SWCR1 0x13c -+#define APBS_PLL5_SWCR2 0x140 -+#define APBS_PLL5_SWCR3 0x144 -+#define APBS_PLL6_SWCR1 0x148 -+#define APBS_PLL6_SWCR2 0x14c -+#define APBS_PLL6_SWCR3 0x150 -+#define APBS_PLL7_SWCR1 0x158 -+#define APBS_PLL7_SWCR2 0x15c -+#define APBS_PLL7_SWCR3 0x160 -+#define APBS_PLL8_SWCR1 0x180 -+#define APBS_PLL8_SWCR2 0x184 -+#define APBS_PLL8_SWCR3 0x188 -+ -+/* MPMU register offset */ -+#define MPMU_FCCR 0x0008 -+#define MPMU_POSR 0x0010 -+#define POSR_PLL1_LOCK BIT(24) -+#define POSR_PLL2_LOCK BIT(25) -+#define POSR_PLL3_LOCK BIT(26) -+#define POSR_PLL4_LOCK BIT(27) -+#define POSR_PLL5_LOCK BIT(28) -+#define POSR_PLL6_LOCK BIT(29) -+#define POSR_PLL7_LOCK BIT(30) -+#define POSR_PLL8_LOCK BIT(31) -+#define MPMU_SUCCR 0x0014 -+#define MPMU_ISCCR 0x0044 -+#define MPMU_WDTPCR 0x0200 -+#define MPMU_RIPCCR 0x0210 -+#define MPMU_ACGR 0x1024 -+#define MPMU_APBCSCR 0x1050 -+#define MPMU_SUCCR_1 0x10b0 -+ -+#define MPMU_I2S0_SYSCLK 0x1100 -+#define MPMU_I2S2_SYSCLK 0x1104 -+#define MPMU_I2S3_SYSCLK 0x1108 -+#define MPMU_I2S4_SYSCLK 0x110c -+#define MPMU_I2S5_SYSCLK 0x1110 -+#define MPMU_I2S_SYSCLK_CTRL 0x1114 -+ -+/* APBC register offset */ -+#define APBC_UART0_CLK_RST 0x00 -+#define APBC_UART2_CLK_RST 0x04 -+#define APBC_GPIO_CLK_RST 0x08 -+#define APBC_PWM0_CLK_RST 0x0c -+#define APBC_PWM1_CLK_RST 0x10 -+#define APBC_PWM2_CLK_RST 0x14 -+#define APBC_PWM3_CLK_RST 0x18 -+#define APBC_TWSI8_CLK_RST 0x20 -+#define APBC_UART3_CLK_RST 0x24 -+#define APBC_RTC_CLK_RST 0x28 -+#define APBC_TWSI0_CLK_RST 0x2c -+#define APBC_TWSI1_CLK_RST 0x30 -+#define APBC_TIMERS0_CLK_RST 0x34 -+#define APBC_TWSI2_CLK_RST 0x38 -+#define APBC_AIB_CLK_RST 0x3c -+#define APBC_TWSI4_CLK_RST 0x40 -+#define APBC_TIMERS1_CLK_RST 0x44 -+#define APBC_ONEWIRE_CLK_RST 0x48 -+#define APBC_TWSI5_CLK_RST 0x4c -+#define APBC_DRO_CLK_RST 0x58 -+#define APBC_IR0_CLK_RST 0x5c -+#define APBC_IR1_CLK_RST 0x1c -+#define APBC_TWSI6_CLK_RST 0x60 -+#define APBC_COUNTER_CLK_SEL 0x64 -+#define APBC_TSEN_CLK_RST 0x6c -+#define APBC_UART4_CLK_RST 0x70 -+#define APBC_UART5_CLK_RST 0x74 -+#define APBC_UART6_CLK_RST 0x78 -+#define APBC_SSP3_CLK_RST 0x7c -+#define APBC_SSPA0_CLK_RST 0x80 -+#define APBC_SSPA1_CLK_RST 0x84 -+#define APBC_SSPA2_CLK_RST 0x88 -+#define APBC_SSPA3_CLK_RST 0x8c -+#define APBC_IPC_AP2AUD_CLK_RST 0x90 -+#define APBC_UART7_CLK_RST 0x94 -+#define APBC_UART8_CLK_RST 0x98 -+#define APBC_UART9_CLK_RST 0x9c -+#define APBC_CAN0_CLK_RST 0xa0 -+#define APBC_CAN1_CLK_RST 0xa4 -+#define APBC_PWM4_CLK_RST 0xa8 -+#define APBC_PWM5_CLK_RST 0xac -+#define APBC_PWM6_CLK_RST 0xb0 -+#define APBC_PWM7_CLK_RST 0xb4 -+#define APBC_PWM8_CLK_RST 0xb8 -+#define APBC_PWM9_CLK_RST 0xbc -+#define APBC_PWM10_CLK_RST 0xc0 -+#define APBC_PWM11_CLK_RST 0xc4 -+#define APBC_PWM12_CLK_RST 0xc8 -+#define APBC_PWM13_CLK_RST 0xcc -+#define APBC_PWM14_CLK_RST 0xd0 -+#define APBC_PWM15_CLK_RST 0xd4 -+#define APBC_PWM16_CLK_RST 0xd8 -+#define APBC_PWM17_CLK_RST 0xdc -+#define APBC_PWM18_CLK_RST 0xe0 -+#define APBC_PWM19_CLK_RST 0xe4 -+#define APBC_TIMERS2_CLK_RST 0x11c -+#define APBC_TIMERS3_CLK_RST 0x120 -+#define APBC_TIMERS4_CLK_RST 0x124 -+#define APBC_TIMERS5_CLK_RST 0x128 -+#define APBC_TIMERS6_CLK_RST 0x12c -+#define APBC_TIMERS7_CLK_RST 0x130 -+ -+#define APBC_CAN2_CLK_RST 0x148 -+#define APBC_CAN3_CLK_RST 0x14c -+#define APBC_CAN4_CLK_RST 0x150 -+#define APBC_UART10_CLK_RST 0x154 -+#define APBC_SSP0_CLK_RST 0x158 -+#define APBC_SSP1_CLK_RST 0x15c -+#define APBC_SSPA4_CLK_RST 0x160 -+#define APBC_SSPA5_CLK_RST 0x164 -+ -+/* APMU register offset */ -+#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 -+#define APMU_ISP_CLK_RES_CTRL 0x038 -+#define APMU_PMU_CLK_GATE_CTRL 0x040 -+#define APMU_LCD_CLK_RES_CTRL1 0x044 -+#define APMU_LCD_SPI_CLK_RES_CTRL 0x048 -+#define APMU_LCD_CLK_RES_CTRL2 0x04c -+#define APMU_CCIC_CLK_RES_CTRL 0x050 -+#define APMU_SDH0_CLK_RES_CTRL 0x054 -+#define APMU_SDH1_CLK_RES_CTRL 0x058 -+#define APMU_USB_CLK_RES_CTRL 0x05c -+#define APMU_QSPI_CLK_RES_CTRL 0x060 -+#define APMU_DMA_CLK_RES_CTRL 0x064 -+#define APMU_AES_CLK_RES_CTRL 0x068 -+#define APMU_MCB_CLK_RES_CTRL 0x06c -+#define APMU_VPU_CLK_RES_CTRL 0x0a4 -+#define APMU_DTC_CLK_RES_CTRL 0x0ac -+#define APMU_GPU_CLK_RES_CTRL 0x0cc -+#define APMU_SDH2_CLK_RES_CTRL 0x0e0 -+#define APMU_PMUA_MC_CTRL 0x0e8 -+#define APMU_PMU_CC2_AP 0x100 -+#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 -+#define APMU_UCIE_CTRL 0x11c -+#define APMU_RCPU_CLK_RES_CTRL 0x14c -+#define APMU_TOP_DCLK_CTRL 0x158 -+#define APMU_LCD_EDP_CTRL 0x23c -+#define APMU_UFS_CLK_RES_CTRL 0x268 -+#define APMU_LCD_CLK_RES_CTRL3 0x26c -+#define APMU_LCD_CLK_RES_CTRL4 0x270 -+#define APMU_LCD_CLK_RES_CTRL5 0x274 -+#define APMU_CCI550_CLK_CTRL 0x300 -+#define APMU_ACLK_CLK_CTRL 0x388 -+#define APMU_CPU_C0_CLK_CTRL 0x38C -+#define APMU_CPU_C1_CLK_CTRL 0x390 -+#define APMU_CPU_C2_CLK_CTRL 0x394 -+#define APMU_CPU_C3_CLK_CTRL 0x208 -+#define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 -+#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 -+#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 -+#define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 -+#define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 -+#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 -+#define APMU_EMAC1_CLK_RES_CTRL 0x3ec -+#define APMU_EMAC2_CLK_RES_CTRL 0x248 -+#define APMU_ESPI_CLK_RES_CTRL 0x240 -+#define APMU_SNR_ISIM_VCLK_CTRL 0x3f8 -+ -+/* DCIU register offsets */ -+#define DCIU_DMASYS_CLK_EN 0x234 -+#define DCIU_DMASYS_SDMA_CLK_EN 0x238 -+#define DCIU_C2_TCM_PIPE_CLK 0x244 -+#define DCIU_C3_TCM_PIPE_CLK 0x248 -+ -+#define DCIU_DMASYS_S0_RSTN 0x204 -+#define DCIU_DMASYS_S1_RSTN 0x208 -+#define DCIU_DMASYS_A0_RSTN 0x20C -+#define DCIU_DMASYS_A1_RSTN 0x210 -+#define DCIU_DMASYS_A2_RSTN 0x214 -+#define DCIU_DMASYS_A3_RSTN 0x218 -+#define DCIU_DMASYS_A4_RSTN 0x21C -+#define DCIU_DMASYS_A5_RSTN 0x220 -+#define DCIU_DMASYS_A6_RSTN 0x224 -+#define DCIU_DMASYS_A7_RSTN 0x228 -+#define DCIU_DMASYS_RSTN 0x22C -+#define DCIU_DMASYS_SDMA_RSTN 0x230 -+ -+/* RCPU SYSCTRL register offsets */ -+#define RCPU_CAN_CLK_RST 0x4c -+#define RCPU_CAN1_CLK_RST 0xF0 -+#define RCPU_CAN2_CLK_RST 0xF4 -+#define RCPU_CAN3_CLK_RST 0xF8 -+#define RCPU_CAN4_CLK_RST 0xFC -+#define RCPU_IRC_CLK_RST 0x48 -+#define RCPU_IRC1_CLK_RST 0xEC -+#define RCPU_GMAC_CLK_RST 0xE4 -+#define RCPU_ESPI_CLK_RST 0xDC -+#define RCPU_AUDIO_I2S0_SYS_CLK_CTRL 0x70 -+#define RCPU_AUDIO_I2S1_SYS_CLK_CTRL 0x44 -+ -+/* RCPU UARTCTRL register offsets */ -+#define RCPU1_UART0_CLK_RST 0x00 -+#define RCPU1_UART1_CLK_RST 0x04 -+#define RCPU1_UART2_CLK_RST 0x08 -+#define RCPU1_UART3_CLK_RST 0x0c -+#define RCPU1_UART4_CLK_RST 0x10 -+#define RCPU1_UART5_CLK_RST 0x14 -+ -+/* RCPU I2SCTRL register offsets */ -+#define RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL 0x60 -+#define RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL 0x64 -+#define RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL 0x68 -+#define RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL 0x6C -+ -+#define RCPU2_AUDIO_I2S2_SYS_CLK_CTRL 0x44 -+#define RCPU2_AUDIO_I2S3_SYS_CLK_CTRL 0x54 -+ -+/* RCPU SPICTRL register offsets */ -+#define RCPU3_SSP0_CLK_RST 0x00 -+#define RCPU3_SSP1_CLK_RST 0x04 -+#define RCPU3_PWR_SSP_CLK_RST 0x08 -+ -+/* RCPU I2CCTRL register offsets */ -+#define RCPU4_I2C0_CLK_RST 0x00 -+#define RCPU4_I2C1_CLK_RST 0x04 -+#define RCPU4_PWR_I2C_CLK_RST 0x08 -+ -+/* RPMU register offsets */ -+#define RCPU5_AON_PER_CLK_RST_CTRL 0x2C -+#define RCPU5_TIMER1_CLK_RST 0x4C -+#define RCPU5_TIMER2_CLK_RST 0x70 -+#define RCPU5_TIMER3_CLK_RST 0x78 -+#define RCPU5_TIMER4_CLK_RST 0x7C -+#define RCPU5_GPIO_AND_EDGE_CLK_RST 0x74 -+#define RCPU5_RCPU_BUS_CLK_CTRL 0xC0 -+#define RCPU5_RT24_CORE0_CLK_CTRL 0xC4 -+#define RCPU5_RT24_CORE1_CLK_CTRL 0xC8 -+#define RCPU5_RT24_CORE0_SW_RESET 0xCC -+#define RCPU5_RT24_CORE1_SW_RESET 0xD0 -+ -+/* RCPU PWMCTRL register offsets */ -+#define RCPU6_PWM0_CLK_RST 0x00 -+#define RCPU6_PWM1_CLK_RST 0x04 -+#define RCPU6_PWM2_CLK_RST 0x08 -+#define RCPU6_PWM3_CLK_RST 0x0c -+#define RCPU6_PWM4_CLK_RST 0x10 -+#define RCPU6_PWM5_CLK_RST 0x14 -+#define RCPU6_PWM6_CLK_RST 0x18 -+#define RCPU6_PWM7_CLK_RST 0x1c -+#define RCPU6_PWM8_CLK_RST 0x20 -+#define RCPU6_PWM9_CLK_RST 0x24 -+ -+/* APBC2 SEC register offsets */ -+#define APBC2_UART1_CLK_RST 0x00 -+#define APBC2_SSP2_CLK_RST 0x04 -+#define APBC2_TWSI3_CLK_RST 0x08 -+#define APBC2_RTC_CLK_RST 0x0c -+#define APBC2_TIMERS_CLK_RST 0x10 -+#define APBC2_GPIO_CLK_RST 0x1c -+ -+#endif /* __SOC_K3_SYSCON_H__ */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch b/SPECS/linux-lts-kmhv2/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch new file mode 100644 index 0000000000..6775e0de91 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch @@ -0,0 +1,124 @@ +From f58dcbda59da2a11300427e92f4c1abb7c6898f7 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 20 Jan 2026 19:10:50 +0800 +Subject: [RUYI PATCH] UPSTREAM: reset: Create subdirectory for SpacemiT + drivers + +Create a dedicated subdirectory for SpacemiT reset drivers to allow +for better organization as support for more SoCs is added. + +Move the existing K1 reset driver into this new directory and rename +it to reset-spacemit-k1.c. + +Rename the Kconfig symbol to RESET_SPACEMIT_K1 and update its default +from ARCH_SPACEMIT to SPACEMIT_K1_CCU. The reset driver depends on the +clock driver to register reset devices as an auxiliary device, so the +default should reflect this dependency. + +Also sort the drivers/reset/Kconfig entries alphabetically. + +Reviewed-by: Alex Elder +Signed-off-by: Guodong Xu +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] +Signed-off-by: Philipp Zabel +(cherry picked from commit 2875b4b5d2657ff2fd979103d88e9afcae51481c) +Signed-off-by: Han Gao +--- + drivers/reset/Kconfig | 12 ++---------- + drivers/reset/Makefile | 2 +- + drivers/reset/spacemit/Kconfig | 14 ++++++++++++++ + drivers/reset/spacemit/Makefile | 2 ++ + .../reset-spacemit-k1.c} | 0 + 5 files changed, 19 insertions(+), 11 deletions(-) + create mode 100644 drivers/reset/spacemit/Kconfig + create mode 100644 drivers/reset/spacemit/Makefile + rename drivers/reset/{reset-spacemit.c => spacemit/reset-spacemit-k1.c} (100%) + +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index b3b9e0f9d8c4..096f57fb7ccf 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -286,15 +286,6 @@ config RESET_SOCFPGA + This enables the reset driver for the SoCFPGA ARMv7 platforms. This + driver gets initialized early during platform init calls. + +-config RESET_SPACEMIT +- tristate "SpacemiT reset driver" +- depends on ARCH_SPACEMIT || COMPILE_TEST +- select AUXILIARY_BUS +- default ARCH_SPACEMIT +- help +- This enables the reset controller driver for SpacemiT SoCs, +- including the K1. +- + config RESET_SUNPLUS + bool "Sunplus SoCs Reset Driver" if COMPILE_TEST + default ARCH_SUNPLUS +@@ -393,9 +384,10 @@ config RESET_ZYNQMP + This enables the reset controller driver for Xilinx ZynqMP SoCs. + + source "drivers/reset/amlogic/Kconfig" ++source "drivers/reset/hisilicon/Kconfig" ++source "drivers/reset/spacemit/Kconfig" + source "drivers/reset/starfive/Kconfig" + source "drivers/reset/sti/Kconfig" +-source "drivers/reset/hisilicon/Kconfig" + source "drivers/reset/tegra/Kconfig" + + endif +diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile +index f7934f9fb90b..e0934ab7153c 100644 +--- a/drivers/reset/Makefile ++++ b/drivers/reset/Makefile +@@ -2,6 +2,7 @@ + obj-y += core.o + obj-y += amlogic/ + obj-y += hisilicon/ ++obj-y += spacemit/ + obj-y += starfive/ + obj-y += sti/ + obj-y += tegra/ +@@ -37,7 +38,6 @@ obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o + obj-$(CONFIG_RESET_SCMI) += reset-scmi.o + obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o + obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o +-obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o + obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o + obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o + obj-$(CONFIG_RESET_TH1520) += reset-th1520.o +diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig +new file mode 100644 +index 000000000000..552884e8b72a +--- /dev/null ++++ b/drivers/reset/spacemit/Kconfig +@@ -0,0 +1,14 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config RESET_SPACEMIT_K1 ++ tristate "SpacemiT K1 reset driver" ++ depends on ARCH_SPACEMIT || COMPILE_TEST ++ depends on SPACEMIT_K1_CCU ++ select AUXILIARY_BUS ++ default SPACEMIT_K1_CCU ++ help ++ Support for reset controller in SpacemiT K1 SoC. ++ This driver works with the SpacemiT K1 clock controller ++ unit (CCU) driver to provide reset control functionality ++ for various peripherals and subsystems in the SoC. ++ +diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile +new file mode 100644 +index 000000000000..34e3350136bb +--- /dev/null ++++ b/drivers/reset/spacemit/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o +diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/spacemit/reset-spacemit-k1.c +similarity index 100% +rename from drivers/reset/reset-spacemit.c +rename to drivers/reset/spacemit/reset-spacemit-k1.c +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0123-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch b/SPECS/linux-lts-kmhv2/0123-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch deleted file mode 100644 index 606059384f..0000000000 --- a/SPECS/linux-lts-kmhv2/0123-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch +++ /dev/null @@ -1,1541 +0,0 @@ -From 762b40db00f83f963c11e08eb0a8b6a4ed8d3e58 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sun, 2 Nov 2025 21:17:17 +0800 -Subject: [PATCH 123/467] UPSTREAM: clk: spacemit: k3: add the clock tree - -Add clock support to SpacemiT K3 SoC, the clock tree consist of several -blocks which are APBC, APBS, APMU, DCIU, MPUM. - -Link: https://lore.kernel.org/r/20260108-k3-clk-v5-5-42a11b74ad58@gentoo.org -Signed-off-by: Yixun Lan -(cherry picked from commit e371a77255b837f5d64c9d2520f87e41ea5350b9) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/Kconfig | 6 + - drivers/clk/spacemit/Makefile | 3 + - drivers/clk/spacemit/ccu-k3.c | 1487 +++++++++++++++++++++++++++++++++ - 3 files changed, 1496 insertions(+) - create mode 100644 drivers/clk/spacemit/ccu-k3.c - -diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig -index 3351e8bc801d..4ebe6aaa1980 100644 ---- a/drivers/clk/spacemit/Kconfig -+++ b/drivers/clk/spacemit/Kconfig -@@ -14,4 +14,10 @@ config SPACEMIT_K1_CCU - help - Support for clock controller unit in SpacemiT K1 SoC. - -+config SPACEMIT_K3_CCU -+ tristate "Support for SpacemiT K3 SoC" -+ select SPACEMIT_CCU -+ help -+ Support for clock controller unit in SpacemiT K3 SoC. -+ - endmenu -diff --git a/drivers/clk/spacemit/Makefile b/drivers/clk/spacemit/Makefile -index ad2bf315109b..0925eda384b4 100644 ---- a/drivers/clk/spacemit/Makefile -+++ b/drivers/clk/spacemit/Makefile -@@ -8,3 +8,6 @@ spacemit-ccu-y += ccu_ddn.o - - obj-$(CONFIG_SPACEMIT_K1_CCU) += spacemit-ccu-k1.o - spacemit-ccu-k1-y += ccu-k1.o -+ -+obj-$(CONFIG_SPACEMIT_K3_CCU) += spacemit-ccu-k3.o -+spacemit-ccu-k3-y += ccu-k3.o -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -new file mode 100644 -index 000000000000..e98afd59f05c ---- /dev/null -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -0,0 +1,1487 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "ccu_common.h" -+#include "ccu_pll.h" -+#include "ccu_mix.h" -+#include "ccu_ddn.h" -+ -+#include -+ -+/* APBS clocks start, APBS region contains and only contains all PLL clocks */ -+ -+/* -+ * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for -+ * peripherals. -+ */ -+static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = { -+ CCU_PLLA_RATE(2457600000UL, 0x0b330ccc, 0x0000cd00, 0xa0558989), -+}; -+ -+static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { -+ CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c), -+}; -+ -+static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = { -+ CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), -+}; -+ -+static const struct ccu_pll_rate_tbl pll4_rate_tbl[] = { -+ CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), -+}; -+ -+static const struct ccu_pll_rate_tbl pll5_rate_tbl[] = { -+ CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), -+}; -+ -+static const struct ccu_pll_rate_tbl pll6_rate_tbl[] = { -+ CCU_PLLA_RATE(3200000000UL, 0x0b422aaa, 0x0000ab00, 0xa0558e8e), -+}; -+ -+static const struct ccu_pll_rate_tbl pll7_rate_tbl[] = { -+ CCU_PLLA_RATE(2800000000UL, 0x0b3a1555, 0x00005500, 0xa0558b8b), -+}; -+ -+static const struct ccu_pll_rate_tbl pll8_rate_tbl[] = { -+ CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), -+}; -+ -+CCU_PLLA_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR2, APBS_PLL1_SWCR3, -+ MPMU_POSR, POSR_PLL1_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2, APBS_PLL2_SWCR3, -+ MPMU_POSR, POSR_PLL2_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR2, APBS_PLL3_SWCR3, -+ MPMU_POSR, POSR_PLL3_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll4, pll4_rate_tbl, APBS_PLL4_SWCR1, APBS_PLL4_SWCR2, APBS_PLL4_SWCR3, -+ MPMU_POSR, POSR_PLL4_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll5, pll5_rate_tbl, APBS_PLL5_SWCR1, APBS_PLL5_SWCR2, APBS_PLL5_SWCR3, -+ MPMU_POSR, POSR_PLL5_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll6, pll6_rate_tbl, APBS_PLL6_SWCR1, APBS_PLL6_SWCR2, APBS_PLL6_SWCR3, -+ MPMU_POSR, POSR_PLL6_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll7, pll7_rate_tbl, APBS_PLL7_SWCR1, APBS_PLL7_SWCR2, APBS_PLL7_SWCR3, -+ MPMU_POSR, POSR_PLL7_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll8, pll8_rate_tbl, APBS_PLL8_SWCR1, APBS_PLL8_SWCR2, APBS_PLL8_SWCR3, -+ MPMU_POSR, POSR_PLL8_LOCK, CLK_SET_RATE_GATE); -+ -+CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1, -+ CLK_IS_CRITICAL); -+CCU_DIV_GATE_DEFINE(pll1_dx, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, 23, 5, BIT(22), 0); -+CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(31), 64, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(21), 10, 1); -+CCU_FACTOR_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1_aud_245p7), 10, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1); -+CCU_FACTOR_DEFINE(pll2_66, CCU_PARENT_HW(pll2_d5), 9, 1); -+CCU_FACTOR_DEFINE(pll2_33, CCU_PARENT_HW(pll2_66), 2, 1); -+CCU_FACTOR_DEFINE(pll2_50, CCU_PARENT_HW(pll2_d5), 12, 1); -+CCU_FACTOR_DEFINE(pll2_25, CCU_PARENT_HW(pll2_50), 2, 1); -+CCU_FACTOR_DEFINE(pll2_20, CCU_PARENT_HW(pll2_d5), 30, 1); -+CCU_FACTOR_DEFINE(pll2_d24_125, CCU_PARENT_HW(pll2_d3), 8, 1); -+CCU_FACTOR_DEFINE(pll2_d120_25, CCU_PARENT_HW(pll2_d3), 40, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(7), 8, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll4_d1, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d2, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d3, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d4, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d5, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d6, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d7, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d8, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(7), 8, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll5_d1, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d2, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d3, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d4, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d5, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d6, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d7, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d8, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(7), 8, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll6_d1, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d2, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d3, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d4, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d5, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d6, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d7, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d8, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(7), 8, 1); -+CCU_FACTOR_DEFINE(pll6_80, CCU_PARENT_HW(pll6_d5), 8, 1); -+CCU_FACTOR_DEFINE(pll6_40, CCU_PARENT_HW(pll6_d5), 16, 1); -+CCU_FACTOR_DEFINE(pll6_20, CCU_PARENT_HW(pll6_d5), 32, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll7_d1, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d2, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d3, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d4, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d5, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d6, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d7, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d8, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(7), 8, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll8_d1, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d2, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d3, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d4, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d5, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d6, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d7, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d8, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(7), 8, 1); -+/* APBS clocks end */ -+ -+/* MPMU clocks start */ -+CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13), 0); -+CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1); -+CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1); -+CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(12), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(7), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(11), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(8), 16, 3); -+CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(4), 12, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(3), 24, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(19), 24, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(2), 48, 1); -+ -+CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1); -+CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1); -+CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1); -+ -+CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0); -+CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1); -+ -+CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0); -+CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1); -+ -+CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0); -+CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(10), 13, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6), 39, 2); -+ -+CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0); -+ -+CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0); -+ -+static const struct clk_parent_data apb_parents[] = { -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d24_102p4), -+}; -+CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0); -+ -+CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc_32k), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED); -+CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 2, 0); -+CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 2, 0); -+ -+CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0); -+CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), 0); -+ -+CCU_GATE_DEFINE(r_ipc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, BIT(0), 0); -+ -+CCU_FACTOR_DEFINE(i2s_153p6, CCU_PARENT_HW(pll1_d8_307p2), 2, 1); -+ -+static const struct clk_parent_data i2s_153p6_base_parents[] = { -+ CCU_PARENT_HW(i2s_153p6), -+ CCU_PARENT_HW(pll1_d8_307p2), -+}; -+CCU_MUX_DEFINE(i2s_153p6_base, i2s_153p6_base_parents, MPMU_FCCR, 29, 1, 0); -+ -+static const struct clk_parent_data i2s_sysclk_src_parents[] = { -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(i2s_153p6_base), -+}; -+CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0); -+ -+CCU_DDN_DEFINE(i2s1_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0); -+ -+CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s1_sysclk), MPMU_ISCCR, 27, 2, BIT(29), 0); -+ -+static const struct clk_parent_data i2s_sysclk_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_NAME(vctcxo_24m), -+ CCU_PARENT_HW(pll2_d5), -+ CCU_PARENT_NAME(vctcxo_24m), -+}; -+CCU_MUX_DEFINE(i2s0_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 0, 2, 0); -+CCU_MUX_DEFINE(i2s2_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 4, 2, 0); -+CCU_MUX_DEFINE(i2s3_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 12, 2, 0); -+CCU_MUX_DEFINE(i2s4_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 16, 2, 0); -+CCU_MUX_DEFINE(i2s5_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 20, 2, 0); -+ -+CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 1, 0); -+CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 1, 0); -+CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 1, 0); -+CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 1, 0); -+CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 1, 0); -+ -+static const struct clk_parent_data i2s2_sysclk_parents[] = { -+ CCU_PARENT_HW(i2s1_sysclk), -+ CCU_PARENT_HW(i2s2_sysclk_div), -+}; -+CCU_GATE_DEFINE(i2s0_sysclk, CCU_PARENT_HW(i2s0_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(2), 0); -+CCU_MUX_GATE_DEFINE(i2s2_sysclk, i2s2_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 8, 1, BIT(6), 0); -+CCU_GATE_DEFINE(i2s3_sysclk, CCU_PARENT_HW(i2s3_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(14), 0); -+CCU_GATE_DEFINE(i2s4_sysclk, CCU_PARENT_HW(i2s4_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(18), 0); -+CCU_GATE_DEFINE(i2s5_sysclk, CCU_PARENT_HW(i2s5_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(22), 0); -+/* MPMU clocks end */ -+ -+/* APBC clocks start */ -+static const struct clk_parent_data uart_clk_parents[] = { -+ CCU_PARENT_HW(pll1_m3d128_57p6), -+ CCU_PARENT_HW(slow_uart1_14p74), -+ CCU_PARENT_HW(slow_uart2_48), -+}; -+CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART0_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart10_clk, uart_clk_parents, APBC_UART10_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART10_CLK_RST, BIT(0), 0); -+ -+CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, BIT(0), 0); -+ -+static const struct clk_parent_data pwm_parents[] = { -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_NAME(osc_32k), -+}; -+CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST, BIT(0), 0); -+ -+static const struct clk_parent_data i2s_bclk_parents[] = { -+ CCU_PARENT_NAME(vctcxo_1m), -+ CCU_PARENT_HW(i2s_bclk), -+}; -+CCU_MUX_DEFINE(spi0_i2s_bclk, i2s_bclk_parents, APBC_SSP0_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(spi1_i2s_bclk, i2s_bclk_parents, APBC_SSP1_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(spi3_i2s_bclk, i2s_bclk_parents, APBC_SSP3_CLK_RST, 3, 1, 0); -+ -+static const struct clk_parent_data spi0_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(spi0_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(spi0_clk, spi0_parents, APBC_SSP0_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data spi1_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(spi1_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(spi1_clk, spi1_parents, APBC_SSP1_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data spi3_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(spi3_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(spi3_clk, spi3_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(spi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(spi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP1_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(spi3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, BIT(0), 0); -+ -+ -+CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc_32k), APBC_RTC_CLK_RST, -+ BIT(7) | BIT(1), 0); -+CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT(0), 0); -+ -+static const struct clk_parent_data twsi_parents[] = { -+ CCU_PARENT_HW(pll1_d78_31p5), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d40_61p44), -+}; -+CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(twsi8_clk, twsi_parents, APBC_TWSI8_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI8_CLK_RST, BIT(0), 0); -+ -+static const struct clk_parent_data timer_parents[] = { -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_NAME(osc_32k), -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_NAME(vctcxo_3m), -+ CCU_PARENT_NAME(vctcxo_1m), -+}; -+CCU_MUX_GATE_DEFINE(timers0_clk, timer_parents, APBC_TIMERS0_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers3_clk, timer_parents, APBC_TIMERS3_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers4_clk, timer_parents, APBC_TIMERS4_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers5_clk, timer_parents, APBC_TIMERS5_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers6_clk, timer_parents, APBC_TIMERS6_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers7_clk, timer_parents, APBC_TIMERS7_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(timers0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS3_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS4_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS5_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS6_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS7_CLK_RST, BIT(0), 0); -+ -+CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT(0), 0); -+ -+CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_RST, BIT(0), 0); -+ -+/* -+ * When i2s_bclk is selected as the parent clock of sspa, -+ * the hardware requires bit3 to be set -+ */ -+ -+CCU_MUX_DEFINE(i2s0_i2s_bclk, i2s_bclk_parents, APBC_SSPA0_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(i2s1_i2s_bclk, i2s_bclk_parents, APBC_SSPA1_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(i2s2_i2s_bclk, i2s_bclk_parents, APBC_SSPA2_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(i2s3_i2s_bclk, i2s_bclk_parents, APBC_SSPA3_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(i2s4_i2s_bclk, i2s_bclk_parents, APBC_SSPA4_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(i2s5_i2s_bclk, i2s_bclk_parents, APBC_SSPA5_CLK_RST, 3, 1, 0); -+ -+static const struct clk_parent_data i2s0_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(i2s0_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(i2s0_clk, i2s0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data i2s1_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(i2s1_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(i2s1_clk, i2s1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data i2s2_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(i2s2_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(i2s2_clk, i2s2_parents, APBC_SSPA2_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data i2s3_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(i2s3_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(i2s3_clk, i2s3_parents, APBC_SSPA3_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data i2s4_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(i2s4_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(i2s4_clk, i2s4_parents, APBC_SSPA4_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data i2s5_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(i2s5_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(i2s5_clk, i2s5_parents, APBC_SSPA5_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(i2s0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(i2s1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(i2s2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA2_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(i2s3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA3_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(i2s4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA4_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(i2s5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA5_CLK_RST, BIT(0), 0); -+ -+CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(ir0_clk, CCU_PARENT_HW(apb_clk), APBC_IR0_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(ir1_clk, CCU_PARENT_HW(apb_clk), APBC_IR1_CLK_RST, BIT(1), 0); -+ -+CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(0), 0); -+ -+CCU_GATE_DEFINE(ipc_ap2rcpu_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(ipc_ap2rcpu_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0); -+ -+static const struct clk_parent_data can_parents[] = { -+ CCU_PARENT_HW(pll6_20), -+ CCU_PARENT_HW(pll6_40), -+ CCU_PARENT_HW(pll6_80), -+}; -+CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(can1_clk, can_parents, APBC_CAN1_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(can2_clk, can_parents, APBC_CAN2_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(can3_clk, can_parents, APBC_CAN3_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(can4_clk, can_parents, APBC_CAN4_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(can1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN1_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(can2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN2_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(can3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN3_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(can4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN4_CLK_RST, BIT(0), 0); -+/* APBC clocks end */ -+ -+/* APMU clocks start */ -+static const struct clk_parent_data axi_clk_parents[] = { -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d6_409p6), -+}; -+CCU_MUX_DIV_FC_DEFINE(axi_clk, axi_clk_parents, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), 0, 1, 0); -+ -+static const struct clk_parent_data cci550_clk_parents[] = { -+ CCU_PARENT_HW(pll1_d10_245p76), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll7_d3), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll7_d2), -+}; -+CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL, 8, 2, BIT(12), 0, 3, -+ CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data cpu_c0_clk_parents[] = { -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll3_d2), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll2_d2), -+ CCU_PARENT_HW(pll3_d1), -+}; -+CCU_MUX_DIV_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL, -+ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data cpu_c1_clk_parents[] = { -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll4_d2), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll2_d2), -+ CCU_PARENT_HW(pll4_d1), -+}; -+CCU_MUX_DIV_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL, -+ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data cpu_c2_clk_parents[] = { -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll5_d2), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll2_d2), -+ CCU_PARENT_HW(pll5_d1), -+}; -+CCU_MUX_DIV_FC_DEFINE(cpu_c2_core_clk, cpu_c2_clk_parents, APMU_CPU_C2_CLK_CTRL, -+ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data cpu_c3_clk_parents[] = { -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll8_d2), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll2_d2), -+ CCU_PARENT_HW(pll8_d1), -+}; -+CCU_MUX_DIV_FC_DEFINE(cpu_c3_core_clk, cpu_c3_clk_parents, APMU_CPU_C3_CLK_CTRL, -+ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data ccic2phy_parents[] = { -+ CCU_PARENT_HW(pll1_d24_102p4), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+}; -+CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0); -+ -+static const struct clk_parent_data ccic3phy_parents[] = { -+ CCU_PARENT_HW(pll1_d24_102p4), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+}; -+CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0); -+ -+static const struct clk_parent_data csi_parents[] = { -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll2_d2), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15), -+ 16, 3, BIT(4), 0); -+ -+static const struct clk_parent_data isp_bus_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d10_245p76), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23), -+ 21, 2, BIT(17), 0); -+ -+CCU_GATE_DEFINE(d1p_1228p8, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMU_CLK_GATE_CTRL, BIT(31), 0); -+CCU_GATE_DEFINE(d1p_819p2, CCU_PARENT_HW(pll1_d3_819p2), APMU_PMU_CLK_GATE_CTRL, BIT(30), 0); -+CCU_GATE_DEFINE(d1p_614p4, CCU_PARENT_HW(pll1_d4_614p4), APMU_PMU_CLK_GATE_CTRL, BIT(29), 0); -+CCU_GATE_DEFINE(d1p_491p52, CCU_PARENT_HW(pll1_d5_491p52), APMU_PMU_CLK_GATE_CTRL, BIT(28), 0); -+CCU_GATE_DEFINE(d1p_409p6, CCU_PARENT_HW(pll1_d6_409p6), APMU_PMU_CLK_GATE_CTRL, BIT(27), 0); -+CCU_GATE_DEFINE(d1p_307p2, CCU_PARENT_HW(pll1_d8_307p2), APMU_PMU_CLK_GATE_CTRL, BIT(26), 0); -+CCU_GATE_DEFINE(d1p_245p76, CCU_PARENT_HW(pll1_d10_245p76), APMU_PMU_CLK_GATE_CTRL, BIT(22), 0); -+ -+static const struct clk_parent_data v2d_parents[] = { -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d4_614p4), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28), 12, 2, -+ BIT(8), 0); -+ -+static const struct clk_parent_data dsiesc_parents[] = { -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+ CCU_PARENT_HW(pll1_d52_47p26), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d32_76p8), -+}; -+CCU_MUX_GATE_DEFINE(dsi_esc_clk, dsiesc_parents, APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0); -+ -+CCU_GATE_DEFINE(lcd_hclk, CCU_PARENT_HW(axi_clk), APMU_LCD_CLK_RES_CTRL1, BIT(5), 0); -+ -+static const struct clk_parent_data lcd_dsc_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d10_245p76), -+ CCU_PARENT_HW(pll7_d5), -+ CCU_PARENT_HW(pll2_d7), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+ CCU_PARENT_HW(pll2_d8), -+}; -+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_dsc_clk, lcd_dsc_parents, APMU_LCD_CLK_RES_CTRL2, -+ APMU_LCD_CLK_RES_CTRL1, 25, 3, BIT(26), 29, 3, BIT(14), 0); -+ -+static const struct clk_parent_data lcdpx_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d10_245p76), -+ CCU_PARENT_HW(pll7_d5), -+ CCU_PARENT_HW(pll2_d7), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+ CCU_PARENT_HW(pll2_d8), -+}; -+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_pxclk, lcdpx_parents, APMU_LCD_CLK_RES_CTRL2, -+ APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(30), 21, 3, BIT(16), 0); -+ -+static const struct clk_parent_data lcdmclk_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d8_307p2), -+}; -+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_mclk, lcdmclk_parents, APMU_LCD_CLK_RES_CTRL2, -+ APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0); -+ -+static const struct clk_parent_data ccic_4x_parents[] = { -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll2_d2), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES_CTRL, 18, 3, -+ BIT(15), 23, 2, BIT(4), 0); -+ -+static const struct clk_parent_data ccic1phy_parents[] = { -+ CCU_PARENT_HW(pll1_d24_102p4), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+}; -+CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0); -+ -+ -+static const struct clk_parent_data sc2hclk_parents[] = { -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll2_d4), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(sc2_hclk, sc2hclk_parents, APMU_CCIC_CLK_RES_CTRL, 10, 3, -+ BIT(16), 8, 2, BIT(3), 0); -+ -+CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(axi_clk), APMU_SDH0_CLK_RES_CTRL, BIT(3), 0); -+static const struct clk_parent_data sdh01_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll2_d8), -+ CCU_PARENT_HW(pll2_d5), -+ CCU_PARENT_NAME(reserved_clk), -+ CCU_PARENT_NAME(reserved_clk), -+ CCU_PARENT_HW(pll1_dx), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL, 8, 3, -+ BIT(11), 5, 3, BIT(4), 0); -+CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL, 8, 3, -+ BIT(11), 5, 3, BIT(4), 0); -+static const struct clk_parent_data sdh2_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll2_d8), -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_NAME(reserved_clk), -+ CCU_PARENT_NAME(reserved_clk), -+ CCU_PARENT_HW(pll1_dx), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, -+ BIT(11), 5, 3, BIT(4), 0); -+ -+CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(0), 0); -+CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(4), 0); -+CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); -+CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(12), 0); -+CCU_GATE_DEFINE(usb3_portd_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(16), 0); -+ -+static const struct clk_parent_data qspi_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll2_d8), -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d10_245p76), -+ CCU_PARENT_NAME(reserved_clk), -+ CCU_PARENT_HW(pll1_dx), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_NAME(reserved_clk), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL, 9, 3, -+ BIT(12), 6, 3, BIT(4), 0); -+CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(axi_clk), APMU_QSPI_CLK_RES_CTRL, BIT(3), 0); -+ -+CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(axi_clk), APMU_DMA_CLK_RES_CTRL, BIT(3), 0); -+ -+static const struct clk_parent_data aes_wtm_parents[] = { -+ CCU_PARENT_HW(pll1_d12_204p8), -+ CCU_PARENT_HW(pll1_d24_102p4), -+}; -+CCU_MUX_GATE_DEFINE(aes_wtm_clk, aes_wtm_parents, APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0); -+ -+static const struct clk_parent_data vpu_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll2_d5), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13, 3, -+ BIT(21), 10, 3, BIT(3), 0); -+ -+CCU_GATE_DEFINE(dtc_clk, CCU_PARENT_HW(axi_clk), APMU_DTC_CLK_RES_CTRL, BIT(3), 0); -+ -+static const struct clk_parent_data gpu_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll2_d5), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12, 3, -+ BIT(15), 18, 3, BIT(4), 0); -+ -+CCU_GATE_DEFINE(mc_ahb_clk, CCU_PARENT_HW(axi_clk), APMU_PMUA_MC_CTRL, BIT(1), 0); -+ -+static const struct clk_parent_data top_parents[] = { -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll3_d4), -+ CCU_PARENT_HW(pll6_d5), -+ CCU_PARENT_HW(pll7_d4), -+ CCU_PARENT_HW(pll6_d4), -+ CCU_PARENT_HW(pll7_d3), -+ CCU_PARENT_HW(pll6_d3), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(top_dclk, top_parents, APMU_TOP_DCLK_CTRL, 5, 3, -+ BIT(8), 2, 3, BIT(1), 0); -+ -+static const struct clk_parent_data ucie_parents[] = { -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll3_d4), -+ CCU_PARENT_HW(pll6_d5), -+ CCU_PARENT_HW(pll7_d4), -+ CCU_PARENT_HW(pll6_d4), -+}; -+CCU_MUX_GATE_DEFINE(ucie_clk, ucie_parents, APMU_UCIE_CTRL, 4, 3, BIT(0), 0); -+CCU_GATE_DEFINE(ucie_sbclk, CCU_PARENT_HW(axi_clk), APMU_UCIE_CTRL, BIT(8), 0); -+ -+static const struct clk_parent_data rcpu_clk_parents[] = { -+ CCU_PARENT_HW(pll1_aud_245p7), -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d6_409p6), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, -+ 4, 3, BIT(15), 7, 3, BIT(12), 0); -+ -+static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+ CCU_PARENT_HW(pll1_d52_47p26), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d32_76p8), -+}; -+CCU_MUX_GATE_DEFINE(dsi4ln2_dsi_esc_clk, dsi4ln2_dsi_esc_parents, APMU_LCD_CLK_RES_CTRL3, -+ 0, 1, BIT(2), 0); -+ -+static const struct clk_parent_data dsi4ln2_lcd_dsc_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll7_d5), -+ CCU_PARENT_HW(pll6_d6), -+ CCU_PARENT_HW(pll2_d7), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+}; -+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_dsc_clk, dsi4ln2_lcd_dsc_parents, -+ APMU_LCD_CLK_RES_CTRL4, APMU_LCD_CLK_RES_CTRL3, -+ 25, 3, BIT(26), 29, 3, BIT(14), 0); -+ -+static const struct clk_parent_data dsi4ln2_lcdpx_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll7_d5), -+ CCU_PARENT_HW(pll6_d6), -+ CCU_PARENT_HW(pll2_d7), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+ CCU_PARENT_HW(pll2_d8), -+}; -+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_pxclk, dsi4ln2_lcdpx_parents, APMU_LCD_CLK_RES_CTRL4, -+ APMU_LCD_CLK_RES_CTRL3, 17, 3, BIT(30), 21, 3, BIT(16), 0); -+ -+static const struct clk_parent_data dsi4ln2_lcd_mclk_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d8_307p2), -+}; -+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_mclk, dsi4ln2_lcd_mclk_parents, APMU_LCD_CLK_RES_CTRL4, -+ APMU_LCD_CLK_RES_CTRL3, 1, 4, BIT(29), 5, 3, BIT(0), 0); -+ -+static const struct clk_parent_data dpu_aclk_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll2_d4), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(dsi4ln2_dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, -+ 2, 3, BIT(30), 5, 3, BIT(1), 0); -+ -+CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, 17, 3, BIT(31), -+ 20, 3, BIT(16), 0); -+ -+static const struct clk_parent_data ufs_aclk_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll2_d4), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8), -+ 2, 3, BIT(1), 0); -+ -+static const struct clk_parent_data edp0_pclk_parents[] = { -+ CCU_PARENT_HW(lcd_pxclk), -+ CCU_PARENT_NAME(external_clk), -+}; -+CCU_MUX_GATE_DEFINE(edp0_pxclk, edp0_pclk_parents, APMU_LCD_EDP_CTRL, 2, 1, BIT(1), 0); -+ -+static const struct clk_parent_data edp1_pclk_parents[] = { -+ CCU_PARENT_HW(dsi4ln2_lcd_pxclk), -+ CCU_PARENT_NAME(external_clk), -+}; -+CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); -+ -+CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); -+CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); -+CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); -+CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); -+CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); -+CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); -+CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); -+CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); -+CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); -+CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); -+ -+static const struct clk_parent_data emac_1588_parents[] = { -+ CCU_PARENT_NAME(vctcxo_24m), -+ CCU_PARENT_HW(pll2_d24_125), -+}; -+ -+CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0); -+CCU_GATE_FLAGS_DEFINE(emac0_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC0_CLK_RES_CTRL, -+ BIT(14), true, 0); -+CCU_MUX_DEFINE(emac0_1588_clk, emac_1588_parents, APMU_EMAC0_CLK_RES_CTRL, 15, 1, 0); -+CCU_GATE_DEFINE(emac0_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC0_CLK_RES_CTRL, -+ BIT(8), 0); -+CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0); -+CCU_GATE_FLAGS_DEFINE(emac1_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC1_CLK_RES_CTRL, -+ BIT(14), true, 0); -+CCU_MUX_DEFINE(emac1_1588_clk, emac_1588_parents, APMU_EMAC1_CLK_RES_CTRL, 15, 1, 0); -+CCU_GATE_DEFINE(emac1_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC1_CLK_RES_CTRL, -+ BIT(8), 0); -+CCU_GATE_DEFINE(emac2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC2_CLK_RES_CTRL, BIT(0), 0); -+CCU_GATE_FLAGS_DEFINE(emac2_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC2_CLK_RES_CTRL, -+ BIT(14), true, 0); -+CCU_MUX_DEFINE(emac2_1588_clk, emac_1588_parents, APMU_EMAC2_CLK_RES_CTRL, 15, 1, 0); -+CCU_GATE_DEFINE(emac2_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC2_CLK_RES_CTRL, -+ BIT(8), 0); -+ -+static const struct clk_parent_data espi_sclk_src_parents[] = { -+ CCU_PARENT_HW(pll2_20), -+ CCU_PARENT_HW(pll2_25), -+ CCU_PARENT_HW(pll2_33), -+ CCU_PARENT_HW(pll2_50), -+ CCU_PARENT_HW(pll2_66), -+}; -+CCU_MUX_DEFINE(espi_sclk_src, espi_sclk_src_parents, APMU_ESPI_CLK_RES_CTRL, 4, 3, 0); -+ -+static const struct clk_parent_data espi_sclk_parents[] = { -+ CCU_PARENT_NAME(external_clk), -+ CCU_PARENT_HW(espi_sclk_src), -+}; -+CCU_MUX_GATE_DEFINE(espi_sclk, espi_sclk_parents, APMU_ESPI_CLK_RES_CTRL, 7, 1, BIT(3), 0); -+ -+CCU_GATE_DEFINE(espi_mclk, CCU_PARENT_HW(axi_clk), APMU_ESPI_CLK_RES_CTRL, BIT(1), 0); -+ -+CCU_FACTOR_DEFINE(cam_src1_clk, CCU_PARENT_HW(pll1_d6_409p6), 15, 1); -+CCU_FACTOR_DEFINE(cam_src2_clk, CCU_PARENT_HW(pll2_d5), 25, 1); -+CCU_FACTOR_DEFINE(cam_src3_clk, CCU_PARENT_HW(pll2_d6), 20, 1); -+CCU_FACTOR_DEFINE(cam_src4_clk, CCU_PARENT_HW(pll1_d6_409p6), 16, 1); -+ -+static const struct clk_parent_data isim_vclk_parents[] = { -+ CCU_PARENT_HW(cam_src1_clk), -+ CCU_PARENT_HW(cam_src2_clk), -+ CCU_PARENT_HW(cam_src3_clk), -+ CCU_PARENT_HW(cam_src4_clk), -+}; -+CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out0, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 3, 4, -+ 1, 2, BIT(0), 0); -+CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out1, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 11, 4, -+ 9, 2, BIT(8), 0); -+CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out2, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 19, 4, -+ 17, 2, BIT(16), 0); -+CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 27, 4, -+ 25, 2, BIT(24), 0); -+/* APMU clocks end */ -+ -+/* DCIU clocks start */ -+CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); -+CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); -+CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); -+CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); -+/* DCIU clocks end */ -+ -+static struct clk_hw *k3_ccu_pll_hws[] = { -+ [CLK_PLL1] = &pll1.common.hw, -+ [CLK_PLL2] = &pll2.common.hw, -+ [CLK_PLL3] = &pll3.common.hw, -+ [CLK_PLL4] = &pll4.common.hw, -+ [CLK_PLL5] = &pll5.common.hw, -+ [CLK_PLL6] = &pll6.common.hw, -+ [CLK_PLL7] = &pll7.common.hw, -+ [CLK_PLL8] = &pll8.common.hw, -+ [CLK_PLL1_D2] = &pll1_d2.common.hw, -+ [CLK_PLL1_D3] = &pll1_d3.common.hw, -+ [CLK_PLL1_D4] = &pll1_d4.common.hw, -+ [CLK_PLL1_D5] = &pll1_d5.common.hw, -+ [CLK_PLL1_D6] = &pll1_d6.common.hw, -+ [CLK_PLL1_D7] = &pll1_d7.common.hw, -+ [CLK_PLL1_D8] = &pll1_d8.common.hw, -+ [CLK_PLL1_DX] = &pll1_dx.common.hw, -+ [CLK_PLL1_D64] = &pll1_d64_38p4.common.hw, -+ [CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw, -+ [CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw, -+ [CLK_PLL2_D1] = &pll2_d1.common.hw, -+ [CLK_PLL2_D2] = &pll2_d2.common.hw, -+ [CLK_PLL2_D3] = &pll2_d3.common.hw, -+ [CLK_PLL2_D4] = &pll2_d4.common.hw, -+ [CLK_PLL2_D5] = &pll2_d5.common.hw, -+ [CLK_PLL2_D6] = &pll2_d6.common.hw, -+ [CLK_PLL2_D7] = &pll2_d7.common.hw, -+ [CLK_PLL2_D8] = &pll2_d8.common.hw, -+ [CLK_PLL2_66] = &pll2_66.common.hw, -+ [CLK_PLL2_33] = &pll2_33.common.hw, -+ [CLK_PLL2_50] = &pll2_50.common.hw, -+ [CLK_PLL2_25] = &pll2_25.common.hw, -+ [CLK_PLL2_20] = &pll2_20.common.hw, -+ [CLK_PLL2_D24_125] = &pll2_d24_125.common.hw, -+ [CLK_PLL2_D120_25] = &pll2_d120_25.common.hw, -+ [CLK_PLL3_D1] = &pll3_d1.common.hw, -+ [CLK_PLL3_D2] = &pll3_d2.common.hw, -+ [CLK_PLL3_D3] = &pll3_d3.common.hw, -+ [CLK_PLL3_D4] = &pll3_d4.common.hw, -+ [CLK_PLL3_D5] = &pll3_d5.common.hw, -+ [CLK_PLL3_D6] = &pll3_d6.common.hw, -+ [CLK_PLL3_D7] = &pll3_d7.common.hw, -+ [CLK_PLL3_D8] = &pll3_d8.common.hw, -+ [CLK_PLL4_D1] = &pll4_d1.common.hw, -+ [CLK_PLL4_D2] = &pll4_d2.common.hw, -+ [CLK_PLL4_D3] = &pll4_d3.common.hw, -+ [CLK_PLL4_D4] = &pll4_d4.common.hw, -+ [CLK_PLL4_D5] = &pll4_d5.common.hw, -+ [CLK_PLL4_D6] = &pll4_d6.common.hw, -+ [CLK_PLL4_D7] = &pll4_d7.common.hw, -+ [CLK_PLL4_D8] = &pll4_d8.common.hw, -+ [CLK_PLL5_D1] = &pll5_d1.common.hw, -+ [CLK_PLL5_D2] = &pll5_d2.common.hw, -+ [CLK_PLL5_D3] = &pll5_d3.common.hw, -+ [CLK_PLL5_D4] = &pll5_d4.common.hw, -+ [CLK_PLL5_D5] = &pll5_d5.common.hw, -+ [CLK_PLL5_D6] = &pll5_d6.common.hw, -+ [CLK_PLL5_D7] = &pll5_d7.common.hw, -+ [CLK_PLL5_D8] = &pll5_d8.common.hw, -+ [CLK_PLL6_D1] = &pll6_d1.common.hw, -+ [CLK_PLL6_D2] = &pll6_d2.common.hw, -+ [CLK_PLL6_D3] = &pll6_d3.common.hw, -+ [CLK_PLL6_D4] = &pll6_d4.common.hw, -+ [CLK_PLL6_D5] = &pll6_d5.common.hw, -+ [CLK_PLL6_D6] = &pll6_d6.common.hw, -+ [CLK_PLL6_D7] = &pll6_d7.common.hw, -+ [CLK_PLL6_D8] = &pll6_d8.common.hw, -+ [CLK_PLL6_80] = &pll6_80.common.hw, -+ [CLK_PLL6_40] = &pll6_40.common.hw, -+ [CLK_PLL6_20] = &pll6_20.common.hw, -+ [CLK_PLL7_D1] = &pll7_d1.common.hw, -+ [CLK_PLL7_D2] = &pll7_d2.common.hw, -+ [CLK_PLL7_D3] = &pll7_d3.common.hw, -+ [CLK_PLL7_D4] = &pll7_d4.common.hw, -+ [CLK_PLL7_D5] = &pll7_d5.common.hw, -+ [CLK_PLL7_D6] = &pll7_d6.common.hw, -+ [CLK_PLL7_D7] = &pll7_d7.common.hw, -+ [CLK_PLL7_D8] = &pll7_d8.common.hw, -+ [CLK_PLL8_D1] = &pll8_d1.common.hw, -+ [CLK_PLL8_D2] = &pll8_d2.common.hw, -+ [CLK_PLL8_D3] = &pll8_d3.common.hw, -+ [CLK_PLL8_D4] = &pll8_d4.common.hw, -+ [CLK_PLL8_D5] = &pll8_d5.common.hw, -+ [CLK_PLL8_D6] = &pll8_d6.common.hw, -+ [CLK_PLL8_D7] = &pll8_d7.common.hw, -+ [CLK_PLL8_D8] = &pll8_d8.common.hw, -+}; -+ -+static const struct spacemit_ccu_data k3_ccu_pll_data = { -+ /* The APBS CCU implements PLLs, but no resets */ -+ .hws = k3_ccu_pll_hws, -+ .num = ARRAY_SIZE(k3_ccu_pll_hws), -+}; -+ -+static struct clk_hw *k3_ccu_mpmu_hws[] = { -+ [CLK_MPMU_PLL1_307P2] = &pll1_d8_307p2.common.hw, -+ [CLK_MPMU_PLL1_76P8] = &pll1_d32_76p8.common.hw, -+ [CLK_MPMU_PLL1_61P44] = &pll1_d40_61p44.common.hw, -+ [CLK_MPMU_PLL1_153P6] = &pll1_d16_153p6.common.hw, -+ [CLK_MPMU_PLL1_102P4] = &pll1_d24_102p4.common.hw, -+ [CLK_MPMU_PLL1_51P2] = &pll1_d48_51p2.common.hw, -+ [CLK_MPMU_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw, -+ [CLK_MPMU_PLL1_57P6] = &pll1_m3d128_57p6.common.hw, -+ [CLK_MPMU_PLL1_25P6] = &pll1_d96_25p6.common.hw, -+ [CLK_MPMU_PLL1_12P8] = &pll1_d192_12p8.common.hw, -+ [CLK_MPMU_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw, -+ [CLK_MPMU_PLL1_6P4] = &pll1_d384_6p4.common.hw, -+ [CLK_MPMU_PLL1_3P2] = &pll1_d768_3p2.common.hw, -+ [CLK_MPMU_PLL1_1P6] = &pll1_d1536_1p6.common.hw, -+ [CLK_MPMU_PLL1_0P8] = &pll1_d3072_0p8.common.hw, -+ [CLK_MPMU_PLL1_409P6] = &pll1_d6_409p6.common.hw, -+ [CLK_MPMU_PLL1_204P8] = &pll1_d12_204p8.common.hw, -+ [CLK_MPMU_PLL1_491] = &pll1_d5_491p52.common.hw, -+ [CLK_MPMU_PLL1_245P76] = &pll1_d10_245p76.common.hw, -+ [CLK_MPMU_PLL1_614] = &pll1_d4_614p4.common.hw, -+ [CLK_MPMU_PLL1_47P26] = &pll1_d52_47p26.common.hw, -+ [CLK_MPMU_PLL1_31P5] = &pll1_d78_31p5.common.hw, -+ [CLK_MPMU_PLL1_819] = &pll1_d3_819p2.common.hw, -+ [CLK_MPMU_PLL1_1228] = &pll1_d2_1228p8.common.hw, -+ [CLK_MPMU_APB] = &apb_clk.common.hw, -+ [CLK_MPMU_SLOW_UART] = &slow_uart.common.hw, -+ [CLK_MPMU_SLOW_UART1] = &slow_uart1_14p74.common.hw, -+ [CLK_MPMU_SLOW_UART2] = &slow_uart2_48.common.hw, -+ [CLK_MPMU_WDT] = &wdt_clk.common.hw, -+ [CLK_MPMU_WDT_BUS] = &wdt_bus_clk.common.hw, -+ [CLK_MPMU_RIPC] = &r_ipc_clk.common.hw, -+ [CLK_MPMU_I2S_153P6] = &i2s_153p6.common.hw, -+ [CLK_MPMU_I2S_153P6_BASE] = &i2s_153p6_base.common.hw, -+ [CLK_MPMU_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw, -+ [CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw, -+ [CLK_MPMU_I2S_BCLK] = &i2s_bclk.common.hw, -+ [CLK_MPMU_I2S0_SYSCLK_SEL] = &i2s0_sysclk_sel.common.hw, -+ [CLK_MPMU_I2S2_SYSCLK_SEL] = &i2s2_sysclk_sel.common.hw, -+ [CLK_MPMU_I2S3_SYSCLK_SEL] = &i2s3_sysclk_sel.common.hw, -+ [CLK_MPMU_I2S4_SYSCLK_SEL] = &i2s4_sysclk_sel.common.hw, -+ [CLK_MPMU_I2S5_SYSCLK_SEL] = &i2s5_sysclk_sel.common.hw, -+ [CLK_MPMU_I2S0_SYSCLK_DIV] = &i2s0_sysclk_div.common.hw, -+ [CLK_MPMU_I2S2_SYSCLK_DIV] = &i2s2_sysclk_div.common.hw, -+ [CLK_MPMU_I2S3_SYSCLK_DIV] = &i2s3_sysclk_div.common.hw, -+ [CLK_MPMU_I2S4_SYSCLK_DIV] = &i2s4_sysclk_div.common.hw, -+ [CLK_MPMU_I2S5_SYSCLK_DIV] = &i2s5_sysclk_div.common.hw, -+ [CLK_MPMU_I2S0_SYSCLK] = &i2s0_sysclk.common.hw, -+ [CLK_MPMU_I2S2_SYSCLK] = &i2s2_sysclk.common.hw, -+ [CLK_MPMU_I2S3_SYSCLK] = &i2s3_sysclk.common.hw, -+ [CLK_MPMU_I2S4_SYSCLK] = &i2s4_sysclk.common.hw, -+ [CLK_MPMU_I2S5_SYSCLK] = &i2s5_sysclk.common.hw, -+}; -+ -+static const struct spacemit_ccu_data k3_ccu_mpmu_data = { -+ .reset_name = "k3-mpmu-reset", -+ .hws = k3_ccu_mpmu_hws, -+ .num = ARRAY_SIZE(k3_ccu_mpmu_hws), -+}; -+ -+static struct clk_hw *k3_ccu_apbc_hws[] = { -+ [CLK_APBC_UART0] = &uart0_clk.common.hw, -+ [CLK_APBC_UART2] = &uart2_clk.common.hw, -+ [CLK_APBC_UART3] = &uart3_clk.common.hw, -+ [CLK_APBC_UART4] = &uart4_clk.common.hw, -+ [CLK_APBC_UART5] = &uart5_clk.common.hw, -+ [CLK_APBC_UART6] = &uart6_clk.common.hw, -+ [CLK_APBC_UART7] = &uart7_clk.common.hw, -+ [CLK_APBC_UART8] = &uart8_clk.common.hw, -+ [CLK_APBC_UART9] = &uart9_clk.common.hw, -+ [CLK_APBC_UART10] = &uart10_clk.common.hw, -+ [CLK_APBC_UART0_BUS] = &uart0_bus_clk.common.hw, -+ [CLK_APBC_UART2_BUS] = &uart2_bus_clk.common.hw, -+ [CLK_APBC_UART3_BUS] = &uart3_bus_clk.common.hw, -+ [CLK_APBC_UART4_BUS] = &uart4_bus_clk.common.hw, -+ [CLK_APBC_UART5_BUS] = &uart5_bus_clk.common.hw, -+ [CLK_APBC_UART6_BUS] = &uart6_bus_clk.common.hw, -+ [CLK_APBC_UART7_BUS] = &uart7_bus_clk.common.hw, -+ [CLK_APBC_UART8_BUS] = &uart8_bus_clk.common.hw, -+ [CLK_APBC_UART9_BUS] = &uart9_bus_clk.common.hw, -+ [CLK_APBC_UART10_BUS] = &uart10_bus_clk.common.hw, -+ [CLK_APBC_GPIO] = &gpio_clk.common.hw, -+ [CLK_APBC_GPIO_BUS] = &gpio_bus_clk.common.hw, -+ [CLK_APBC_PWM0] = &pwm0_clk.common.hw, -+ [CLK_APBC_PWM1] = &pwm1_clk.common.hw, -+ [CLK_APBC_PWM2] = &pwm2_clk.common.hw, -+ [CLK_APBC_PWM3] = &pwm3_clk.common.hw, -+ [CLK_APBC_PWM4] = &pwm4_clk.common.hw, -+ [CLK_APBC_PWM5] = &pwm5_clk.common.hw, -+ [CLK_APBC_PWM6] = &pwm6_clk.common.hw, -+ [CLK_APBC_PWM7] = &pwm7_clk.common.hw, -+ [CLK_APBC_PWM8] = &pwm8_clk.common.hw, -+ [CLK_APBC_PWM9] = &pwm9_clk.common.hw, -+ [CLK_APBC_PWM10] = &pwm10_clk.common.hw, -+ [CLK_APBC_PWM11] = &pwm11_clk.common.hw, -+ [CLK_APBC_PWM12] = &pwm12_clk.common.hw, -+ [CLK_APBC_PWM13] = &pwm13_clk.common.hw, -+ [CLK_APBC_PWM14] = &pwm14_clk.common.hw, -+ [CLK_APBC_PWM15] = &pwm15_clk.common.hw, -+ [CLK_APBC_PWM16] = &pwm16_clk.common.hw, -+ [CLK_APBC_PWM17] = &pwm17_clk.common.hw, -+ [CLK_APBC_PWM18] = &pwm18_clk.common.hw, -+ [CLK_APBC_PWM19] = &pwm19_clk.common.hw, -+ [CLK_APBC_PWM0_BUS] = &pwm0_bus_clk.common.hw, -+ [CLK_APBC_PWM1_BUS] = &pwm1_bus_clk.common.hw, -+ [CLK_APBC_PWM2_BUS] = &pwm2_bus_clk.common.hw, -+ [CLK_APBC_PWM3_BUS] = &pwm3_bus_clk.common.hw, -+ [CLK_APBC_PWM4_BUS] = &pwm4_bus_clk.common.hw, -+ [CLK_APBC_PWM5_BUS] = &pwm5_bus_clk.common.hw, -+ [CLK_APBC_PWM6_BUS] = &pwm6_bus_clk.common.hw, -+ [CLK_APBC_PWM7_BUS] = &pwm7_bus_clk.common.hw, -+ [CLK_APBC_PWM8_BUS] = &pwm8_bus_clk.common.hw, -+ [CLK_APBC_PWM9_BUS] = &pwm9_bus_clk.common.hw, -+ [CLK_APBC_PWM10_BUS] = &pwm10_bus_clk.common.hw, -+ [CLK_APBC_PWM11_BUS] = &pwm11_bus_clk.common.hw, -+ [CLK_APBC_PWM12_BUS] = &pwm12_bus_clk.common.hw, -+ [CLK_APBC_PWM13_BUS] = &pwm13_bus_clk.common.hw, -+ [CLK_APBC_PWM14_BUS] = &pwm14_bus_clk.common.hw, -+ [CLK_APBC_PWM15_BUS] = &pwm15_bus_clk.common.hw, -+ [CLK_APBC_PWM16_BUS] = &pwm16_bus_clk.common.hw, -+ [CLK_APBC_PWM17_BUS] = &pwm17_bus_clk.common.hw, -+ [CLK_APBC_PWM18_BUS] = &pwm18_bus_clk.common.hw, -+ [CLK_APBC_PWM19_BUS] = &pwm19_bus_clk.common.hw, -+ [CLK_APBC_SPI0_I2S_BCLK] = &spi0_i2s_bclk.common.hw, -+ [CLK_APBC_SPI1_I2S_BCLK] = &spi1_i2s_bclk.common.hw, -+ [CLK_APBC_SPI3_I2S_BCLK] = &spi3_i2s_bclk.common.hw, -+ [CLK_APBC_SPI0] = &spi0_clk.common.hw, -+ [CLK_APBC_SPI1] = &spi1_clk.common.hw, -+ [CLK_APBC_SPI3] = &spi3_clk.common.hw, -+ [CLK_APBC_SPI0_BUS] = &spi0_bus_clk.common.hw, -+ [CLK_APBC_SPI1_BUS] = &spi1_bus_clk.common.hw, -+ [CLK_APBC_SPI3_BUS] = &spi3_bus_clk.common.hw, -+ [CLK_APBC_RTC] = &rtc_clk.common.hw, -+ [CLK_APBC_RTC_BUS] = &rtc_bus_clk.common.hw, -+ [CLK_APBC_TWSI0] = &twsi0_clk.common.hw, -+ [CLK_APBC_TWSI1] = &twsi1_clk.common.hw, -+ [CLK_APBC_TWSI2] = &twsi2_clk.common.hw, -+ [CLK_APBC_TWSI4] = &twsi4_clk.common.hw, -+ [CLK_APBC_TWSI5] = &twsi5_clk.common.hw, -+ [CLK_APBC_TWSI6] = &twsi6_clk.common.hw, -+ [CLK_APBC_TWSI8] = &twsi8_clk.common.hw, -+ [CLK_APBC_TWSI0_BUS] = &twsi0_bus_clk.common.hw, -+ [CLK_APBC_TWSI1_BUS] = &twsi1_bus_clk.common.hw, -+ [CLK_APBC_TWSI2_BUS] = &twsi2_bus_clk.common.hw, -+ [CLK_APBC_TWSI4_BUS] = &twsi4_bus_clk.common.hw, -+ [CLK_APBC_TWSI5_BUS] = &twsi5_bus_clk.common.hw, -+ [CLK_APBC_TWSI6_BUS] = &twsi6_bus_clk.common.hw, -+ [CLK_APBC_TWSI8_BUS] = &twsi8_bus_clk.common.hw, -+ [CLK_APBC_TIMERS0] = &timers0_clk.common.hw, -+ [CLK_APBC_TIMERS1] = &timers1_clk.common.hw, -+ [CLK_APBC_TIMERS2] = &timers2_clk.common.hw, -+ [CLK_APBC_TIMERS3] = &timers3_clk.common.hw, -+ [CLK_APBC_TIMERS4] = &timers4_clk.common.hw, -+ [CLK_APBC_TIMERS5] = &timers5_clk.common.hw, -+ [CLK_APBC_TIMERS6] = &timers6_clk.common.hw, -+ [CLK_APBC_TIMERS7] = &timers7_clk.common.hw, -+ [CLK_APBC_TIMERS0_BUS] = &timers0_bus_clk.common.hw, -+ [CLK_APBC_TIMERS1_BUS] = &timers1_bus_clk.common.hw, -+ [CLK_APBC_TIMERS2_BUS] = &timers2_bus_clk.common.hw, -+ [CLK_APBC_TIMERS3_BUS] = &timers3_bus_clk.common.hw, -+ [CLK_APBC_TIMERS4_BUS] = &timers4_bus_clk.common.hw, -+ [CLK_APBC_TIMERS5_BUS] = &timers5_bus_clk.common.hw, -+ [CLK_APBC_TIMERS6_BUS] = &timers6_bus_clk.common.hw, -+ [CLK_APBC_TIMERS7_BUS] = &timers7_bus_clk.common.hw, -+ [CLK_APBC_AIB] = &aib_clk.common.hw, -+ [CLK_APBC_AIB_BUS] = &aib_bus_clk.common.hw, -+ [CLK_APBC_ONEWIRE] = &onewire_clk.common.hw, -+ [CLK_APBC_ONEWIRE_BUS] = &onewire_bus_clk.common.hw, -+ [CLK_APBC_I2S0_BCLK] = &i2s0_i2s_bclk.common.hw, -+ [CLK_APBC_I2S1_BCLK] = &i2s1_i2s_bclk.common.hw, -+ [CLK_APBC_I2S2_BCLK] = &i2s2_i2s_bclk.common.hw, -+ [CLK_APBC_I2S3_BCLK] = &i2s3_i2s_bclk.common.hw, -+ [CLK_APBC_I2S4_BCLK] = &i2s4_i2s_bclk.common.hw, -+ [CLK_APBC_I2S5_BCLK] = &i2s5_i2s_bclk.common.hw, -+ [CLK_APBC_I2S0] = &i2s0_clk.common.hw, -+ [CLK_APBC_I2S1] = &i2s1_clk.common.hw, -+ [CLK_APBC_I2S2] = &i2s2_clk.common.hw, -+ [CLK_APBC_I2S3] = &i2s3_clk.common.hw, -+ [CLK_APBC_I2S4] = &i2s4_clk.common.hw, -+ [CLK_APBC_I2S5] = &i2s5_clk.common.hw, -+ [CLK_APBC_I2S0_BUS] = &i2s0_bus_clk.common.hw, -+ [CLK_APBC_I2S1_BUS] = &i2s1_bus_clk.common.hw, -+ [CLK_APBC_I2S2_BUS] = &i2s2_bus_clk.common.hw, -+ [CLK_APBC_I2S3_BUS] = &i2s3_bus_clk.common.hw, -+ [CLK_APBC_I2S4_BUS] = &i2s4_bus_clk.common.hw, -+ [CLK_APBC_I2S5_BUS] = &i2s5_bus_clk.common.hw, -+ [CLK_APBC_DRO] = &dro_clk.common.hw, -+ [CLK_APBC_IR0] = &ir0_clk.common.hw, -+ [CLK_APBC_IR1] = &ir1_clk.common.hw, -+ [CLK_APBC_TSEN] = &tsen_clk.common.hw, -+ [CLK_APBC_TSEN_BUS] = &tsen_bus_clk.common.hw, -+ [CLK_APBC_IPC_AP2RCPU] = &ipc_ap2rcpu_clk.common.hw, -+ [CLK_APBC_IPC_AP2RCPU_BUS] = &ipc_ap2rcpu_bus_clk.common.hw, -+ [CLK_APBC_CAN0] = &can0_clk.common.hw, -+ [CLK_APBC_CAN1] = &can1_clk.common.hw, -+ [CLK_APBC_CAN2] = &can2_clk.common.hw, -+ [CLK_APBC_CAN3] = &can3_clk.common.hw, -+ [CLK_APBC_CAN4] = &can4_clk.common.hw, -+ [CLK_APBC_CAN0_BUS] = &can0_bus_clk.common.hw, -+ [CLK_APBC_CAN1_BUS] = &can1_bus_clk.common.hw, -+ [CLK_APBC_CAN2_BUS] = &can2_bus_clk.common.hw, -+ [CLK_APBC_CAN3_BUS] = &can3_bus_clk.common.hw, -+ [CLK_APBC_CAN4_BUS] = &can4_bus_clk.common.hw, -+}; -+ -+static const struct spacemit_ccu_data k3_ccu_apbc_data = { -+ .reset_name = "k3-apbc-reset", -+ .hws = k3_ccu_apbc_hws, -+ .num = ARRAY_SIZE(k3_ccu_apbc_hws), -+}; -+ -+static struct clk_hw *k3_ccu_apmu_hws[] = { -+ [CLK_APMU_AXICLK] = &axi_clk.common.hw, -+ [CLK_APMU_CCI550] = &cci550_clk.common.hw, -+ [CLK_APMU_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw, -+ [CLK_APMU_CPU_C1_CORE] = &cpu_c1_core_clk.common.hw, -+ [CLK_APMU_CPU_C2_CORE] = &cpu_c2_core_clk.common.hw, -+ [CLK_APMU_CPU_C3_CORE] = &cpu_c3_core_clk.common.hw, -+ [CLK_APMU_CCIC2PHY] = &ccic2phy_clk.common.hw, -+ [CLK_APMU_CCIC3PHY] = &ccic3phy_clk.common.hw, -+ [CLK_APMU_CSI] = &csi_clk.common.hw, -+ [CLK_APMU_ISP_BUS] = &isp_bus_clk.common.hw, -+ [CLK_APMU_D1P_1228P8] = &d1p_1228p8.common.hw, -+ [CLK_APMU_D1P_819P2] = &d1p_819p2.common.hw, -+ [CLK_APMU_D1P_614P4] = &d1p_614p4.common.hw, -+ [CLK_APMU_D1P_491P52] = &d1p_491p52.common.hw, -+ [CLK_APMU_D1P_409P6] = &d1p_409p6.common.hw, -+ [CLK_APMU_D1P_307P2] = &d1p_307p2.common.hw, -+ [CLK_APMU_D1P_245P76] = &d1p_245p76.common.hw, -+ [CLK_APMU_V2D] = &v2d_clk.common.hw, -+ [CLK_APMU_DSI_ESC] = &dsi_esc_clk.common.hw, -+ [CLK_APMU_LCD_HCLK] = &lcd_hclk.common.hw, -+ [CLK_APMU_LCD_DSC] = &lcd_dsc_clk.common.hw, -+ [CLK_APMU_LCD_PXCLK] = &lcd_pxclk.common.hw, -+ [CLK_APMU_LCD_MCLK] = &lcd_mclk.common.hw, -+ [CLK_APMU_CCIC_4X] = &ccic_4x_clk.common.hw, -+ [CLK_APMU_CCIC1PHY] = &ccic1phy_clk.common.hw, -+ [CLK_APMU_SC2_HCLK] = &sc2_hclk.common.hw, -+ [CLK_APMU_SDH_AXI] = &sdh_axi_aclk.common.hw, -+ [CLK_APMU_SDH0] = &sdh0_clk.common.hw, -+ [CLK_APMU_SDH1] = &sdh1_clk.common.hw, -+ [CLK_APMU_SDH2] = &sdh2_clk.common.hw, -+ [CLK_APMU_USB2_BUS] = &usb2_bus_clk.common.hw, -+ [CLK_APMU_USB3_PORTA_BUS] = &usb3_porta_bus_clk.common.hw, -+ [CLK_APMU_USB3_PORTB_BUS] = &usb3_portb_bus_clk.common.hw, -+ [CLK_APMU_USB3_PORTC_BUS] = &usb3_portc_bus_clk.common.hw, -+ [CLK_APMU_USB3_PORTD_BUS] = &usb3_portd_bus_clk.common.hw, -+ [CLK_APMU_QSPI] = &qspi_clk.common.hw, -+ [CLK_APMU_QSPI_BUS] = &qspi_bus_clk.common.hw, -+ [CLK_APMU_DMA] = &dma_clk.common.hw, -+ [CLK_APMU_AES_WTM] = &aes_wtm_clk.common.hw, -+ [CLK_APMU_VPU] = &vpu_clk.common.hw, -+ [CLK_APMU_DTC] = &dtc_clk.common.hw, -+ [CLK_APMU_GPU] = &gpu_clk.common.hw, -+ [CLK_APMU_MC_AHB] = &mc_ahb_clk.common.hw, -+ [CLK_APMU_TOP_DCLK] = &top_dclk.common.hw, -+ [CLK_APMU_UCIE] = &ucie_clk.common.hw, -+ [CLK_APMU_UCIE_SBCLK] = &ucie_sbclk.common.hw, -+ [CLK_APMU_RCPU] = &rcpu_clk.common.hw, -+ [CLK_APMU_DSI4LN2_DSI_ESC] = &dsi4ln2_dsi_esc_clk.common.hw, -+ [CLK_APMU_DSI4LN2_LCD_DSC] = &dsi4ln2_lcd_dsc_clk.common.hw, -+ [CLK_APMU_DSI4LN2_LCD_PXCLK] = &dsi4ln2_lcd_pxclk.common.hw, -+ [CLK_APMU_DSI4LN2_LCD_MCLK] = &dsi4ln2_lcd_mclk.common.hw, -+ [CLK_APMU_DSI4LN2_DPU_ACLK] = &dsi4ln2_dpu_aclk.common.hw, -+ [CLK_APMU_DPU_ACLK] = &dpu_aclk.common.hw, -+ [CLK_APMU_UFS_ACLK] = &ufs_aclk.common.hw, -+ [CLK_APMU_EDP0_PXCLK] = &edp0_pxclk.common.hw, -+ [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, -+ [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, -+ [CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw, -+ [CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw, -+ [CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw, -+ [CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw, -+ [CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw, -+ [CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw, -+ [CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw, -+ [CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw, -+ [CLK_APMU_EMAC0_RGMII_TX] = &emac0_rgmii_tx_clk.common.hw, -+ [CLK_APMU_EMAC1_BUS] = &emac1_bus_clk.common.hw, -+ [CLK_APMU_EMAC1_REF] = &emac1_ref_clk.common.hw, -+ [CLK_APMU_EMAC1_1588] = &emac1_1588_clk.common.hw, -+ [CLK_APMU_EMAC1_RGMII_TX] = &emac1_rgmii_tx_clk.common.hw, -+ [CLK_APMU_EMAC2_BUS] = &emac2_bus_clk.common.hw, -+ [CLK_APMU_EMAC2_REF] = &emac2_ref_clk.common.hw, -+ [CLK_APMU_EMAC2_1588] = &emac2_1588_clk.common.hw, -+ [CLK_APMU_EMAC2_RGMII_TX] = &emac2_rgmii_tx_clk.common.hw, -+ [CLK_APMU_ESPI_SCLK_SRC] = &espi_sclk_src.common.hw, -+ [CLK_APMU_ESPI_SCLK] = &espi_sclk.common.hw, -+ [CLK_APMU_ESPI_MCLK] = &espi_mclk.common.hw, -+ [CLK_APMU_CAM_SRC1] = &cam_src1_clk.common.hw, -+ [CLK_APMU_CAM_SRC2] = &cam_src2_clk.common.hw, -+ [CLK_APMU_CAM_SRC3] = &cam_src3_clk.common.hw, -+ [CLK_APMU_CAM_SRC4] = &cam_src4_clk.common.hw, -+ [CLK_APMU_ISIM_VCLK0] = &isim_vclk_out0.common.hw, -+ [CLK_APMU_ISIM_VCLK1] = &isim_vclk_out1.common.hw, -+ [CLK_APMU_ISIM_VCLK2] = &isim_vclk_out2.common.hw, -+ [CLK_APMU_ISIM_VCLK3] = &isim_vclk_out3.common.hw, -+}; -+ -+static const struct spacemit_ccu_data k3_ccu_apmu_data = { -+ .reset_name = "k3-apmu-reset", -+ .hws = k3_ccu_apmu_hws, -+ .num = ARRAY_SIZE(k3_ccu_apmu_hws), -+}; -+ -+static struct clk_hw *k3_ccu_dciu_hws[] = { -+ [CLK_DCIU_HDMA] = &hdma_clk.common.hw, -+ [CLK_DCIU_DMA350] = &dma350_clk.common.hw, -+ [CLK_DCIU_C2_TCM_PIPE] = &c2_tcm_pipe_clk.common.hw, -+ [CLK_DCIU_C3_TCM_PIPE] = &c3_tcm_pipe_clk.common.hw, -+}; -+ -+static const struct spacemit_ccu_data k3_ccu_dciu_data = { -+ .reset_name = "k3-dciu-reset", -+ .hws = k3_ccu_dciu_hws, -+ .num = ARRAY_SIZE(k3_ccu_dciu_hws), -+}; -+ -+static const struct of_device_id of_k3_ccu_match[] = { -+ { -+ .compatible = "spacemit,k3-pll", -+ .data = &k3_ccu_pll_data, -+ }, -+ { -+ .compatible = "spacemit,k3-syscon-mpmu", -+ .data = &k3_ccu_mpmu_data, -+ }, -+ { -+ .compatible = "spacemit,k3-syscon-apbc", -+ .data = &k3_ccu_apbc_data, -+ }, -+ { -+ .compatible = "spacemit,k3-syscon-apmu", -+ .data = &k3_ccu_apmu_data, -+ }, -+ { -+ .compatible = "spacemit,k3-syscon-dciu", -+ .data = &k3_ccu_dciu_data, -+ }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_k3_ccu_match); -+ -+static int k3_ccu_probe(struct platform_device *pdev) -+{ -+ return spacemit_ccu_probe(pdev, "spacemit,k3-pll"); -+} -+ -+static struct platform_driver k3_ccu_driver = { -+ .driver = { -+ .name = "spacemit,k3-ccu", -+ .of_match_table = of_k3_ccu_match, -+ }, -+ .probe = k3_ccu_probe, -+}; -+module_platform_driver(k3_ccu_driver); -+ -+MODULE_IMPORT_NS("CLK_SPACEMIT"); -+MODULE_DESCRIPTION("SpacemiT K3 CCU driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch b/SPECS/linux-lts-kmhv2/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch new file mode 100644 index 0000000000..326c078c60 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch @@ -0,0 +1,363 @@ +From 1928fc1030c03e43f009ef60762dac1829c39b0c Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 20 Jan 2026 19:10:51 +0800 +Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: Extract common K1 reset code + +Extract the common reset controller code from the K1 driver into +separate reset-spacemit-common.{c,h} files to prepare for additional +SpacemiT SoCs that share the same reset controller architecture. + +The common code includes handlers for reset assert and deassert +operations and probing for auxiliary bus devices. + +Changes during extraction: +- Module ownership: Use dev->driver->owner instead of THIS_MODULE in + spacemit_reset_controller_register() to correctly reference the + calling driver's module. +- Rename spacemit_reset_ids to spacemit_k1_reset_ids. +- Define new namespace "RESET_SPACEMIT" for the exported common + functions (spacemit_reset_probe) and update K1 driver to import it. + +This prepares for additional SpacemiT SoCs (K3) that share the same reset +controller architecture. + +Reviewed-by: Alex Elder +Signed-off-by: Guodong Xu +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] +Signed-off-by: Philipp Zabel +(cherry picked from commit aba86f7bff0bfd6956aff9bbbfb0c6ea6d56809e) +Signed-off-by: Han Gao +--- + drivers/reset/spacemit/Kconfig | 17 ++- + drivers/reset/spacemit/Makefile | 2 + + .../reset/spacemit/reset-spacemit-common.c | 77 +++++++++++++ + .../reset/spacemit/reset-spacemit-common.h | 42 +++++++ + drivers/reset/spacemit/reset-spacemit-k1.c | 107 ++---------------- + 5 files changed, 144 insertions(+), 101 deletions(-) + create mode 100644 drivers/reset/spacemit/reset-spacemit-common.c + create mode 100644 drivers/reset/spacemit/reset-spacemit-common.h + +diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig +index 552884e8b72a..56a4858b30e1 100644 +--- a/drivers/reset/spacemit/Kconfig ++++ b/drivers/reset/spacemit/Kconfig +@@ -1,10 +1,20 @@ + # SPDX-License-Identifier: GPL-2.0-only + +-config RESET_SPACEMIT_K1 +- tristate "SpacemiT K1 reset driver" ++menu "Reset support for SpacemiT platforms" + depends on ARCH_SPACEMIT || COMPILE_TEST +- depends on SPACEMIT_K1_CCU ++ ++config RESET_SPACEMIT_COMMON ++ tristate + select AUXILIARY_BUS ++ help ++ Common reset controller infrastructure for SpacemiT SoCs. ++ This provides shared code and helper functions used by ++ reset drivers for various SpacemiT SoC families. ++ ++config RESET_SPACEMIT_K1 ++ tristate "Support for SpacemiT K1 SoC" ++ depends on SPACEMIT_K1_CCU ++ select RESET_SPACEMIT_COMMON + default SPACEMIT_K1_CCU + help + Support for reset controller in SpacemiT K1 SoC. +@@ -12,3 +22,4 @@ config RESET_SPACEMIT_K1 + unit (CCU) driver to provide reset control functionality + for various peripherals and subsystems in the SoC. + ++endmenu +diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile +index 34e3350136bb..0b056e8661ec 100644 +--- a/drivers/reset/spacemit/Makefile ++++ b/drivers/reset/spacemit/Makefile +@@ -1,2 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_RESET_SPACEMIT_COMMON) += reset-spacemit-common.o ++ + obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o +diff --git a/drivers/reset/spacemit/reset-spacemit-common.c b/drivers/reset/spacemit/reset-spacemit-common.c +new file mode 100644 +index 000000000000..0626633a5e7d +--- /dev/null ++++ b/drivers/reset/spacemit/reset-spacemit-common.c +@@ -0,0 +1,77 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++/* SpacemiT reset controller driver - common implementation */ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include "reset-spacemit-common.h" ++ ++static int spacemit_reset_update(struct reset_controller_dev *rcdev, ++ unsigned long id, bool assert) ++{ ++ struct ccu_reset_controller *controller; ++ const struct ccu_reset_data *data; ++ u32 mask; ++ u32 val; ++ ++ controller = container_of(rcdev, struct ccu_reset_controller, rcdev); ++ data = &controller->data->reset_data[id]; ++ mask = data->assert_mask | data->deassert_mask; ++ val = assert ? data->assert_mask : data->deassert_mask; ++ ++ return regmap_update_bits(controller->regmap, data->offset, mask, val); ++} ++ ++static int spacemit_reset_assert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ return spacemit_reset_update(rcdev, id, true); ++} ++ ++static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ return spacemit_reset_update(rcdev, id, false); ++} ++ ++static const struct reset_control_ops spacemit_reset_control_ops = { ++ .assert = spacemit_reset_assert, ++ .deassert = spacemit_reset_deassert, ++}; ++ ++static int spacemit_reset_controller_register(struct device *dev, ++ struct ccu_reset_controller *controller) ++{ ++ struct reset_controller_dev *rcdev = &controller->rcdev; ++ ++ rcdev->ops = &spacemit_reset_control_ops; ++ rcdev->owner = dev->driver->owner; ++ rcdev->of_node = dev->of_node; ++ rcdev->nr_resets = controller->data->count; ++ ++ return devm_reset_controller_register(dev, &controller->rcdev); ++} ++ ++int spacemit_reset_probe(struct auxiliary_device *adev, ++ const struct auxiliary_device_id *id) ++{ ++ struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev); ++ struct ccu_reset_controller *controller; ++ struct device *dev = &adev->dev; ++ ++ controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); ++ if (!controller) ++ return -ENOMEM; ++ controller->data = (const struct ccu_reset_controller_data *)id->driver_data; ++ controller->regmap = rdev->regmap; ++ ++ return spacemit_reset_controller_register(dev, controller); ++} ++EXPORT_SYMBOL_NS_GPL(spacemit_reset_probe, "RESET_SPACEMIT"); ++ ++MODULE_DESCRIPTION("SpacemiT reset controller driver - common code"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/reset/spacemit/reset-spacemit-common.h b/drivers/reset/spacemit/reset-spacemit-common.h +new file mode 100644 +index 000000000000..ffaf2f86eb39 +--- /dev/null ++++ b/drivers/reset/spacemit/reset-spacemit-common.h +@@ -0,0 +1,42 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * SpacemiT reset controller driver - common definitions ++ */ ++ ++#ifndef _RESET_SPACEMIT_COMMON_H_ ++#define _RESET_SPACEMIT_COMMON_H_ ++ ++#include ++#include ++#include ++#include ++ ++struct ccu_reset_data { ++ u32 offset; ++ u32 assert_mask; ++ u32 deassert_mask; ++}; ++ ++struct ccu_reset_controller_data { ++ const struct ccu_reset_data *reset_data; /* array */ ++ size_t count; ++}; ++ ++struct ccu_reset_controller { ++ struct reset_controller_dev rcdev; ++ const struct ccu_reset_controller_data *data; ++ struct regmap *regmap; ++}; ++ ++#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ ++ { \ ++ .offset = (_offset), \ ++ .assert_mask = (_assert_mask), \ ++ .deassert_mask = (_deassert_mask), \ ++ } ++ ++/* Common probe function */ ++int spacemit_reset_probe(struct auxiliary_device *adev, ++ const struct auxiliary_device_id *id); ++ ++#endif /* _RESET_SPACEMIT_COMMON_H_ */ +diff --git a/drivers/reset/spacemit/reset-spacemit-k1.c b/drivers/reset/spacemit/reset-spacemit-k1.c +index cc7fd1f8750d..8f3b5329ea5f 100644 +--- a/drivers/reset/spacemit/reset-spacemit-k1.c ++++ b/drivers/reset/spacemit/reset-spacemit-k1.c +@@ -1,41 +1,13 @@ + // SPDX-License-Identifier: GPL-2.0-only + +-/* SpacemiT reset controller driver */ ++/* SpacemiT K1 reset controller driver */ + +-#include +-#include +-#include + #include +-#include +-#include +-#include + +-#include + #include ++#include + +-struct ccu_reset_data { +- u32 offset; +- u32 assert_mask; +- u32 deassert_mask; +-}; +- +-struct ccu_reset_controller_data { +- const struct ccu_reset_data *reset_data; /* array */ +- size_t count; +-}; +- +-struct ccu_reset_controller { +- struct reset_controller_dev rcdev; +- const struct ccu_reset_controller_data *data; +- struct regmap *regmap; +-}; +- +-#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ +- { \ +- .offset = (_offset), \ +- .assert_mask = (_assert_mask), \ +- .deassert_mask = (_deassert_mask), \ +- } ++#include "reset-spacemit-common.h" + + static const struct ccu_reset_data k1_mpmu_resets[] = { + [RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), +@@ -214,91 +186,30 @@ static const struct ccu_reset_controller_data k1_apbc2_reset_data = { + .count = ARRAY_SIZE(k1_apbc2_resets), + }; + +-static int spacemit_reset_update(struct reset_controller_dev *rcdev, +- unsigned long id, bool assert) +-{ +- struct ccu_reset_controller *controller; +- const struct ccu_reset_data *data; +- u32 mask; +- u32 val; +- +- controller = container_of(rcdev, struct ccu_reset_controller, rcdev); +- data = &controller->data->reset_data[id]; +- mask = data->assert_mask | data->deassert_mask; +- val = assert ? data->assert_mask : data->deassert_mask; +- +- return regmap_update_bits(controller->regmap, data->offset, mask, val); +-} +- +-static int spacemit_reset_assert(struct reset_controller_dev *rcdev, +- unsigned long id) +-{ +- return spacemit_reset_update(rcdev, id, true); +-} +- +-static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, +- unsigned long id) +-{ +- return spacemit_reset_update(rcdev, id, false); +-} +- +-static const struct reset_control_ops spacemit_reset_control_ops = { +- .assert = spacemit_reset_assert, +- .deassert = spacemit_reset_deassert, +-}; +- +-static int spacemit_reset_controller_register(struct device *dev, +- struct ccu_reset_controller *controller) +-{ +- struct reset_controller_dev *rcdev = &controller->rcdev; +- +- rcdev->ops = &spacemit_reset_control_ops; +- rcdev->owner = THIS_MODULE; +- rcdev->of_node = dev->of_node; +- rcdev->nr_resets = controller->data->count; +- +- return devm_reset_controller_register(dev, &controller->rcdev); +-} +- +-static int spacemit_reset_probe(struct auxiliary_device *adev, +- const struct auxiliary_device_id *id) +-{ +- struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev); +- struct ccu_reset_controller *controller; +- struct device *dev = &adev->dev; +- +- controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); +- if (!controller) +- return -ENOMEM; +- controller->data = (const struct ccu_reset_controller_data *)id->driver_data; +- controller->regmap = rdev->regmap; +- +- return spacemit_reset_controller_register(dev, controller); +-} +- + #define K1_AUX_DEV_ID(_unit) \ + { \ + .name = "spacemit_ccu.k1-" #_unit "-reset", \ + .driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ + } + +-static const struct auxiliary_device_id spacemit_reset_ids[] = { ++static const struct auxiliary_device_id spacemit_k1_reset_ids[] = { + K1_AUX_DEV_ID(mpmu), + K1_AUX_DEV_ID(apbc), + K1_AUX_DEV_ID(apmu), + K1_AUX_DEV_ID(rcpu), + K1_AUX_DEV_ID(rcpu2), + K1_AUX_DEV_ID(apbc2), +- { }, ++ { /* sentinel */ } + }; +-MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids); ++MODULE_DEVICE_TABLE(auxiliary, spacemit_k1_reset_ids); + + static struct auxiliary_driver spacemit_k1_reset_driver = { + .probe = spacemit_reset_probe, +- .id_table = spacemit_reset_ids, ++ .id_table = spacemit_k1_reset_ids, + }; + module_auxiliary_driver(spacemit_k1_reset_driver); + ++MODULE_IMPORT_NS("RESET_SPACEMIT"); + MODULE_AUTHOR("Alex Elder "); +-MODULE_DESCRIPTION("SpacemiT reset controller driver"); ++MODULE_DESCRIPTION("SpacemiT K1 reset controller driver"); + MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0124-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch b/SPECS/linux-lts-kmhv2/0124-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch deleted file mode 100644 index 5ef22ef32b..0000000000 --- a/SPECS/linux-lts-kmhv2/0124-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch +++ /dev/null @@ -1,235 +0,0 @@ -From 6eb7dce00142b5381c54a88e02ba870e0aebb1c9 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 20 Jan 2026 19:10:49 +0800 -Subject: [PATCH 124/467] UPSTREAM: dt-bindings: soc: spacemit: Add K3 reset - support and IDs - -Update the spacemit,k1-syscon.yaml binding to document K3 SoC reset -support. - -K3 reset devices are registered at runtime as auxiliary devices by the -K3 CCU driver. Since K3 reuses the K1 syscon binding, there is no separate -YAML binding file for K3 resets. - -Update #reset-cells description to document where reset IDs are defined. - -Acked-by: Alex Elder -Acked-by: Krzysztof Kozlowski -Signed-off-by: Guodong Xu -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] -Signed-off-by: Philipp Zabel -(cherry picked from commit 216e0a5e98e5f0f02a818884e8acf340892cecae) -Signed-off-by: Han Gao ---- - .../soc/spacemit/spacemit,k1-syscon.yaml | 8 +- - .../dt-bindings/reset/spacemit,k3-resets.h | 171 ++++++++++++++++++ - 2 files changed, 178 insertions(+), 1 deletion(-) - create mode 100644 include/dt-bindings/reset/spacemit,k3-resets.h - -diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml -index d87131da30bc..d3a7c93c3c54 100644 ---- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml -+++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml -@@ -10,7 +10,7 @@ maintainers: - - Haylen Chu - - description: -- System controllers found on SpacemiT K1 SoC, which are capable of -+ System controllers found on SpacemiT K1/K3 SoC, which are capable of - clock, reset and power-management functions. - - properties: -@@ -51,6 +51,12 @@ properties: - - "#reset-cells": - const: 1 -+ description: | -+ ID of the reset controller line. Valid IDs are defined in corresponding -+ files: -+ -+ For SpacemiT K1, see include/dt-bindings/clock/spacemit,k1-syscon.h -+ For SpacemiT K3, see include/dt-bindings/reset/spacemit,k3-resets.h - - required: - - compatible -diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h -new file mode 100644 -index 000000000000..79ac1c22b7b5 ---- /dev/null -+++ b/include/dt-bindings/reset/spacemit,k3-resets.h -@@ -0,0 +1,171 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd -+ */ -+ -+#ifndef _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ -+#define _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ -+ -+/* MPMU resets */ -+#define RESET_MPMU_WDT 0 -+#define RESET_MPMU_RIPC 1 -+ -+/* APBC resets */ -+#define RESET_APBC_UART0 0 -+#define RESET_APBC_UART2 1 -+#define RESET_APBC_UART3 2 -+#define RESET_APBC_UART4 3 -+#define RESET_APBC_UART5 4 -+#define RESET_APBC_UART6 5 -+#define RESET_APBC_UART7 6 -+#define RESET_APBC_UART8 7 -+#define RESET_APBC_UART9 8 -+#define RESET_APBC_UART10 9 -+#define RESET_APBC_GPIO 10 -+#define RESET_APBC_PWM0 11 -+#define RESET_APBC_PWM1 12 -+#define RESET_APBC_PWM2 13 -+#define RESET_APBC_PWM3 14 -+#define RESET_APBC_PWM4 15 -+#define RESET_APBC_PWM5 16 -+#define RESET_APBC_PWM6 17 -+#define RESET_APBC_PWM7 18 -+#define RESET_APBC_PWM8 19 -+#define RESET_APBC_PWM9 20 -+#define RESET_APBC_PWM10 21 -+#define RESET_APBC_PWM11 22 -+#define RESET_APBC_PWM12 23 -+#define RESET_APBC_PWM13 24 -+#define RESET_APBC_PWM14 25 -+#define RESET_APBC_PWM15 26 -+#define RESET_APBC_PWM16 27 -+#define RESET_APBC_PWM17 28 -+#define RESET_APBC_PWM18 29 -+#define RESET_APBC_PWM19 30 -+#define RESET_APBC_SPI0 31 -+#define RESET_APBC_SPI1 32 -+#define RESET_APBC_SPI3 33 -+#define RESET_APBC_RTC 34 -+#define RESET_APBC_TWSI0 35 -+#define RESET_APBC_TWSI1 36 -+#define RESET_APBC_TWSI2 37 -+#define RESET_APBC_TWSI4 38 -+#define RESET_APBC_TWSI5 39 -+#define RESET_APBC_TWSI6 40 -+#define RESET_APBC_TWSI8 41 -+#define RESET_APBC_TIMERS0 42 -+#define RESET_APBC_TIMERS1 43 -+#define RESET_APBC_TIMERS2 44 -+#define RESET_APBC_TIMERS3 45 -+#define RESET_APBC_TIMERS4 46 -+#define RESET_APBC_TIMERS5 47 -+#define RESET_APBC_TIMERS6 48 -+#define RESET_APBC_TIMERS7 49 -+#define RESET_APBC_AIB 50 -+#define RESET_APBC_ONEWIRE 51 -+#define RESET_APBC_I2S0 52 -+#define RESET_APBC_I2S1 53 -+#define RESET_APBC_I2S2 54 -+#define RESET_APBC_I2S3 55 -+#define RESET_APBC_I2S4 56 -+#define RESET_APBC_I2S5 57 -+#define RESET_APBC_DRO 58 -+#define RESET_APBC_IR0 59 -+#define RESET_APBC_IR1 60 -+#define RESET_APBC_TSEN 61 -+#define RESET_IPC_AP2AUD 62 -+#define RESET_APBC_CAN0 63 -+#define RESET_APBC_CAN1 64 -+#define RESET_APBC_CAN2 65 -+#define RESET_APBC_CAN3 66 -+#define RESET_APBC_CAN4 67 -+ -+/* APMU resets */ -+#define RESET_APMU_CSI 0 -+#define RESET_APMU_CCIC2PHY 1 -+#define RESET_APMU_CCIC3PHY 2 -+#define RESET_APMU_ISP_CIBUS 3 -+#define RESET_APMU_DSI_ESC 4 -+#define RESET_APMU_LCD 5 -+#define RESET_APMU_V2D 6 -+#define RESET_APMU_LCD_MCLK 7 -+#define RESET_APMU_LCD_DSCCLK 8 -+#define RESET_APMU_SC2_HCLK 9 -+#define RESET_APMU_CCIC_4X 10 -+#define RESET_APMU_CCIC1_PHY 11 -+#define RESET_APMU_SDH_AXI 12 -+#define RESET_APMU_SDH0 13 -+#define RESET_APMU_SDH1 14 -+#define RESET_APMU_SDH2 15 -+#define RESET_APMU_USB2 16 -+#define RESET_APMU_USB3_PORTA 17 -+#define RESET_APMU_USB3_PORTB 18 -+#define RESET_APMU_USB3_PORTC 19 -+#define RESET_APMU_USB3_PORTD 20 -+#define RESET_APMU_QSPI 21 -+#define RESET_APMU_QSPI_BUS 22 -+#define RESET_APMU_DMA 23 -+#define RESET_APMU_AES_WTM 24 -+#define RESET_APMU_MCB_DCLK 25 -+#define RESET_APMU_MCB_ACLK 26 -+#define RESET_APMU_VPU 27 -+#define RESET_APMU_DTC 28 -+#define RESET_APMU_GPU 29 -+#define RESET_APMU_ALZO 30 -+#define RESET_APMU_MC 31 -+#define RESET_APMU_CPU0_POP 32 -+#define RESET_APMU_CPU0_SW 33 -+#define RESET_APMU_CPU1_POP 34 -+#define RESET_APMU_CPU1_SW 35 -+#define RESET_APMU_CPU2_POP 36 -+#define RESET_APMU_CPU2_SW 37 -+#define RESET_APMU_CPU3_POP 38 -+#define RESET_APMU_CPU3_SW 39 -+#define RESET_APMU_C0_MPSUB_SW 40 -+#define RESET_APMU_CPU4_POP 41 -+#define RESET_APMU_CPU4_SW 42 -+#define RESET_APMU_CPU5_POP 43 -+#define RESET_APMU_CPU5_SW 44 -+#define RESET_APMU_CPU6_POP 45 -+#define RESET_APMU_CPU6_SW 46 -+#define RESET_APMU_CPU7_POP 47 -+#define RESET_APMU_CPU7_SW 48 -+#define RESET_APMU_C1_MPSUB_SW 49 -+#define RESET_APMU_MPSUB_DBG 50 -+#define RESET_APMU_UCIE 51 -+#define RESET_APMU_RCPU 52 -+#define RESET_APMU_DSI4LN2_ESCCLK 53 -+#define RESET_APMU_DSI4LN2_LCD_SW 54 -+#define RESET_APMU_DSI4LN2_LCD_MCLK 55 -+#define RESET_APMU_DSI4LN2_LCD_DSCCLK 56 -+#define RESET_APMU_DSI4LN2_DPU_ACLK 57 -+#define RESET_APMU_DPU_ACLK 58 -+#define RESET_APMU_UFS_ACLK 59 -+#define RESET_APMU_EDP0 60 -+#define RESET_APMU_EDP1 61 -+#define RESET_APMU_PCIE_PORTA 62 -+#define RESET_APMU_PCIE_PORTB 63 -+#define RESET_APMU_PCIE_PORTC 64 -+#define RESET_APMU_PCIE_PORTD 65 -+#define RESET_APMU_PCIE_PORTE 66 -+#define RESET_APMU_EMAC0 67 -+#define RESET_APMU_EMAC1 68 -+#define RESET_APMU_EMAC2 69 -+#define RESET_APMU_ESPI_MCLK 70 -+#define RESET_APMU_ESPI_SCLK 71 -+ -+/* DCIU resets*/ -+#define RESET_DCIU_HDMA 0 -+#define RESET_DCIU_DMA350 1 -+#define RESET_DCIU_DMA350_0 2 -+#define RESET_DCIU_DMA350_1 3 -+#define RESET_DCIU_AXIDMA0 4 -+#define RESET_DCIU_AXIDMA1 5 -+#define RESET_DCIU_AXIDMA2 6 -+#define RESET_DCIU_AXIDMA3 7 -+#define RESET_DCIU_AXIDMA4 8 -+#define RESET_DCIU_AXIDMA5 9 -+#define RESET_DCIU_AXIDMA6 10 -+#define RESET_DCIU_AXIDMA7 11 -+ -+#endif /* _DT_BINDINGS_RESET_SPACEMIT_K3_H_ */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch b/SPECS/linux-lts-kmhv2/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch new file mode 100644 index 0000000000..3e39a6ab56 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch @@ -0,0 +1,299 @@ +From ba7026a22c43e830be9a0dccce75c3867b2bcaad Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 20 Jan 2026 19:10:52 +0800 +Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: Add SpacemiT K3 reset driver + +Add support for the SpacemiT K3 SoC reset controller. The K3 reset +driver reuses the common reset controller code and provides K3-specific +reset data for devices managed by the following units: + + - MPMU (Main Power Management Unit) + - APBC (APB clock unit) + - APMU (Application Subsystem Power Management Unit) + - DCIU (DMA Control and Interface Unit) + +Acked-by: Alex Elder +Signed-off-by: Guodong Xu +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] +Signed-off-by: Philipp Zabel +(cherry picked from commit 938ce3b16582657e67f3bd8a7efa59089c467c90) +Signed-off-by: Han Gao +--- + drivers/reset/spacemit/Kconfig | 11 + + drivers/reset/spacemit/Makefile | 1 + + drivers/reset/spacemit/reset-spacemit-k3.c | 233 +++++++++++++++++++++ + 3 files changed, 245 insertions(+) + create mode 100644 drivers/reset/spacemit/reset-spacemit-k3.c + +diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig +index 56a4858b30e1..545d6b41c6ca 100644 +--- a/drivers/reset/spacemit/Kconfig ++++ b/drivers/reset/spacemit/Kconfig +@@ -22,4 +22,15 @@ config RESET_SPACEMIT_K1 + unit (CCU) driver to provide reset control functionality + for various peripherals and subsystems in the SoC. + ++config RESET_SPACEMIT_K3 ++ tristate "Support for SpacemiT K3 SoC" ++ depends on SPACEMIT_K3_CCU ++ select RESET_SPACEMIT_COMMON ++ default SPACEMIT_K3_CCU ++ help ++ Support for reset controller in SpacemiT K3 SoC. ++ This driver works with the SpacemiT K3 clock controller ++ unit (CCU) driver to provide reset control functionality ++ for various peripherals and subsystems in the SoC. ++ + endmenu +diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile +index 0b056e8661ec..00669132c6ac 100644 +--- a/drivers/reset/spacemit/Makefile ++++ b/drivers/reset/spacemit/Makefile +@@ -2,3 +2,4 @@ + obj-$(CONFIG_RESET_SPACEMIT_COMMON) += reset-spacemit-common.o + + obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o ++obj-$(CONFIG_RESET_SPACEMIT_K3) += reset-spacemit-k3.o +diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c +new file mode 100644 +index 000000000000..e9e32e4c1ba5 +--- /dev/null ++++ b/drivers/reset/spacemit/reset-spacemit-k3.c +@@ -0,0 +1,233 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++/* SpacemiT K3 reset controller driver */ ++ ++#include ++ ++#include ++#include ++ ++#include "reset-spacemit-common.h" ++ ++static const struct ccu_reset_data k3_mpmu_resets[] = { ++ [RESET_MPMU_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), ++ [RESET_MPMU_RIPC] = RESET_DATA(MPMU_RIPCCR, BIT(2), 0), ++}; ++ ++static const struct ccu_reset_controller_data k3_mpmu_reset_data = { ++ .reset_data = k3_mpmu_resets, ++ .count = ARRAY_SIZE(k3_mpmu_resets), ++}; ++ ++static const struct ccu_reset_data k3_apbc_resets[] = { ++ [RESET_APBC_UART0] = RESET_DATA(APBC_UART0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART10] = RESET_DATA(APBC_UART10_CLK_RST, BIT(2), 0), ++ [RESET_APBC_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), 0), ++ [RESET_APBC_SPI0] = RESET_DATA(APBC_SSP0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_SPI1] = RESET_DATA(APBC_SSP1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_SPI3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS0] = RESET_DATA(APBC_TIMERS0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS3] = RESET_DATA(APBC_TIMERS3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS4] = RESET_DATA(APBC_TIMERS4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS5] = RESET_DATA(APBC_TIMERS5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS6] = RESET_DATA(APBC_TIMERS6_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS7] = RESET_DATA(APBC_TIMERS7_CLK_RST, BIT(2), 0), ++ [RESET_APBC_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), ++ [RESET_APBC_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S2] = RESET_DATA(APBC_SSPA2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S3] = RESET_DATA(APBC_SSPA3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S4] = RESET_DATA(APBC_SSPA4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S5] = RESET_DATA(APBC_SSPA5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), ++ [RESET_APBC_IR0] = RESET_DATA(APBC_IR0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_IR1] = RESET_DATA(APBC_IR1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), ++ [RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN1] = RESET_DATA(APBC_CAN1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN2] = RESET_DATA(APBC_CAN2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN3] = RESET_DATA(APBC_CAN3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN4] = RESET_DATA(APBC_CAN4_CLK_RST, BIT(2), 0), ++}; ++ ++static const struct ccu_reset_controller_data k3_apbc_reset_data = { ++ .reset_data = k3_apbc_resets, ++ .count = ARRAY_SIZE(k3_apbc_resets), ++}; ++ ++static const struct ccu_reset_data k3_apmu_resets[] = { ++ [RESET_APMU_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_APMU_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), ++ [RESET_APMU_ISP_CIBUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), ++ [RESET_APMU_DSI_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), ++ [RESET_APMU_LCD] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), ++ [RESET_APMU_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), ++ [RESET_APMU_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), ++ [RESET_APMU_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(15)), ++ [RESET_APMU_SC2_HCLK] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_APMU_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(1)|BIT(2)|BIT(3)), ++ [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(5)|BIT(6)|BIT(7)), ++ [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(9)|BIT(10)|BIT(11)), ++ [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(13)|BIT(14)|BIT(15)), ++ [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(17)|BIT(18)|BIT(19)), ++ [RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_AES_WTM] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), ++ [RESET_APMU_MCB_DCLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_MCB_ACLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_DTC] = RESET_DATA(APMU_DTC_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), ++ [RESET_APMU_CPU0_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(0), 0), ++ [RESET_APMU_CPU0_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(1), 0), ++ [RESET_APMU_CPU1_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(3), 0), ++ [RESET_APMU_CPU1_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(4), 0), ++ [RESET_APMU_CPU2_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(6), 0), ++ [RESET_APMU_CPU2_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(7), 0), ++ [RESET_APMU_CPU3_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(9), 0), ++ [RESET_APMU_CPU3_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(10), 0), ++ [RESET_APMU_C0_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(12), 0), ++ [RESET_APMU_CPU4_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(16), 0), ++ [RESET_APMU_CPU4_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(17), 0), ++ [RESET_APMU_CPU5_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(19), 0), ++ [RESET_APMU_CPU5_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(20), 0), ++ [RESET_APMU_CPU6_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(22), 0), ++ [RESET_APMU_CPU6_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(23), 0), ++ [RESET_APMU_CPU7_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(25), 0), ++ [RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), ++ [RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), ++ [RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), ++ [RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL, ++ BIT(1) | BIT(2) | BIT(3), 0), ++ [RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, ++ BIT(3) | BIT(2) | BIT(0)), ++ [RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)), ++ [RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)), ++ [RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)), ++ [RESET_APMU_DSI4LN2_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(15)), ++ [RESET_APMU_DSI4LN2_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(0)), ++ [RESET_APMU_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(15)), ++ [RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), ++ [RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), ++ [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_ESPI_MCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_ESPI_SCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(2)), ++}; ++ ++static const struct ccu_reset_controller_data k3_apmu_reset_data = { ++ .reset_data = k3_apmu_resets, ++ .count = ARRAY_SIZE(k3_apmu_resets), ++}; ++ ++static const struct ccu_reset_data k3_dciu_resets[] = { ++ [RESET_DCIU_HDMA] = RESET_DATA(DCIU_DMASYS_RSTN, 0, BIT(0)), ++ [RESET_DCIU_DMA350] = RESET_DATA(DCIU_DMASYS_SDMA_RSTN, 0, BIT(0)), ++ [RESET_DCIU_DMA350_0] = RESET_DATA(DCIU_DMASYS_S0_RSTN, 0, BIT(0)), ++ [RESET_DCIU_DMA350_1] = RESET_DATA(DCIU_DMASYS_S1_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA0] = RESET_DATA(DCIU_DMASYS_A0_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA1] = RESET_DATA(DCIU_DMASYS_A1_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA2] = RESET_DATA(DCIU_DMASYS_A2_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA3] = RESET_DATA(DCIU_DMASYS_A3_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA4] = RESET_DATA(DCIU_DMASYS_A4_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA5] = RESET_DATA(DCIU_DMASYS_A5_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA6] = RESET_DATA(DCIU_DMASYS_A6_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA7] = RESET_DATA(DCIU_DMASYS_A7_RSTN, 0, BIT(0)), ++}; ++ ++static const struct ccu_reset_controller_data k3_dciu_reset_data = { ++ .reset_data = k3_dciu_resets, ++ .count = ARRAY_SIZE(k3_dciu_resets), ++}; ++ ++#define K3_AUX_DEV_ID(_unit) \ ++ { \ ++ .name = "spacemit_ccu.k3-" #_unit "-reset", \ ++ .driver_data = (kernel_ulong_t)&k3_ ## _unit ## _reset_data, \ ++ } ++ ++static const struct auxiliary_device_id spacemit_k3_reset_ids[] = { ++ K3_AUX_DEV_ID(mpmu), ++ K3_AUX_DEV_ID(apbc), ++ K3_AUX_DEV_ID(apmu), ++ K3_AUX_DEV_ID(dciu), ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(auxiliary, spacemit_k3_reset_ids); ++ ++static struct auxiliary_driver spacemit_k3_reset_driver = { ++ .probe = spacemit_reset_probe, ++ .id_table = spacemit_k3_reset_ids, ++}; ++module_auxiliary_driver(spacemit_k3_reset_driver); ++ ++MODULE_IMPORT_NS("RESET_SPACEMIT"); ++MODULE_AUTHOR("Guodong Xu "); ++MODULE_DESCRIPTION("SpacemiT K3 reset controller driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch b/SPECS/linux-lts-kmhv2/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch new file mode 100644 index 0000000000..87f1321e5c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch @@ -0,0 +1,36 @@ +From 69b50555993d0e015534df599be1be5f756f84ea Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 6 Jan 2026 11:09:32 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: gpio: spacemit: add compatible + name for K3 SoC + +Add new compatible string for SpacemiT K3 SoC's GPIO controller. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260106-02-k3-gpio-v3-1-4800c214810b@gentoo.org +Signed-off-by: Bartosz Golaszewski +(cherry picked from commit 48033e4c677be4e3f131df454d44a5d1fb1b334f) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml +index 83e0b2d14c9f..24d22d95665f 100644 +--- a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml ++++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml +@@ -19,7 +19,9 @@ properties: + pattern: "^gpio@[0-9a-f]+$" + + compatible: +- const: spacemit,k1-gpio ++ enum: ++ - spacemit,k1-gpio ++ - spacemit,k3-gpio + + reg: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0125-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch b/SPECS/linux-lts-kmhv2/0125-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch deleted file mode 100644 index afc9137c09..0000000000 --- a/SPECS/linux-lts-kmhv2/0125-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 9049262f9ac3ca9c394670007ce66ff407629b3d Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 20 Jan 2026 19:10:50 +0800 -Subject: [PATCH 125/467] UPSTREAM: reset: Create subdirectory for SpacemiT - drivers - -Create a dedicated subdirectory for SpacemiT reset drivers to allow -for better organization as support for more SoCs is added. - -Move the existing K1 reset driver into this new directory and rename -it to reset-spacemit-k1.c. - -Rename the Kconfig symbol to RESET_SPACEMIT_K1 and update its default -from ARCH_SPACEMIT to SPACEMIT_K1_CCU. The reset driver depends on the -clock driver to register reset devices as an auxiliary device, so the -default should reflect this dependency. - -Also sort the drivers/reset/Kconfig entries alphabetically. - -Reviewed-by: Alex Elder -Signed-off-by: Guodong Xu -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] -Signed-off-by: Philipp Zabel -(cherry picked from commit 2875b4b5d2657ff2fd979103d88e9afcae51481c) -Signed-off-by: Han Gao ---- - drivers/reset/Kconfig | 12 ++---------- - drivers/reset/Makefile | 2 +- - drivers/reset/spacemit/Kconfig | 14 ++++++++++++++ - drivers/reset/spacemit/Makefile | 2 ++ - .../reset-spacemit-k1.c} | 0 - 5 files changed, 19 insertions(+), 11 deletions(-) - create mode 100644 drivers/reset/spacemit/Kconfig - create mode 100644 drivers/reset/spacemit/Makefile - rename drivers/reset/{reset-spacemit.c => spacemit/reset-spacemit-k1.c} (100%) - -diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig -index b3b9e0f9d8c4..096f57fb7ccf 100644 ---- a/drivers/reset/Kconfig -+++ b/drivers/reset/Kconfig -@@ -286,15 +286,6 @@ config RESET_SOCFPGA - This enables the reset driver for the SoCFPGA ARMv7 platforms. This - driver gets initialized early during platform init calls. - --config RESET_SPACEMIT -- tristate "SpacemiT reset driver" -- depends on ARCH_SPACEMIT || COMPILE_TEST -- select AUXILIARY_BUS -- default ARCH_SPACEMIT -- help -- This enables the reset controller driver for SpacemiT SoCs, -- including the K1. -- - config RESET_SUNPLUS - bool "Sunplus SoCs Reset Driver" if COMPILE_TEST - default ARCH_SUNPLUS -@@ -393,9 +384,10 @@ config RESET_ZYNQMP - This enables the reset controller driver for Xilinx ZynqMP SoCs. - - source "drivers/reset/amlogic/Kconfig" -+source "drivers/reset/hisilicon/Kconfig" -+source "drivers/reset/spacemit/Kconfig" - source "drivers/reset/starfive/Kconfig" - source "drivers/reset/sti/Kconfig" --source "drivers/reset/hisilicon/Kconfig" - source "drivers/reset/tegra/Kconfig" - - endif -diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile -index f7934f9fb90b..e0934ab7153c 100644 ---- a/drivers/reset/Makefile -+++ b/drivers/reset/Makefile -@@ -2,6 +2,7 @@ - obj-y += core.o - obj-y += amlogic/ - obj-y += hisilicon/ -+obj-y += spacemit/ - obj-y += starfive/ - obj-y += sti/ - obj-y += tegra/ -@@ -37,7 +38,6 @@ obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o - obj-$(CONFIG_RESET_SCMI) += reset-scmi.o - obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o - obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o --obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o - obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o - obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o - obj-$(CONFIG_RESET_TH1520) += reset-th1520.o -diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig -new file mode 100644 -index 000000000000..552884e8b72a ---- /dev/null -+++ b/drivers/reset/spacemit/Kconfig -@@ -0,0 +1,14 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config RESET_SPACEMIT_K1 -+ tristate "SpacemiT K1 reset driver" -+ depends on ARCH_SPACEMIT || COMPILE_TEST -+ depends on SPACEMIT_K1_CCU -+ select AUXILIARY_BUS -+ default SPACEMIT_K1_CCU -+ help -+ Support for reset controller in SpacemiT K1 SoC. -+ This driver works with the SpacemiT K1 clock controller -+ unit (CCU) driver to provide reset control functionality -+ for various peripherals and subsystems in the SoC. -+ -diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile -new file mode 100644 -index 000000000000..34e3350136bb ---- /dev/null -+++ b/drivers/reset/spacemit/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o -diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/spacemit/reset-spacemit-k1.c -similarity index 100% -rename from drivers/reset/reset-spacemit.c -rename to drivers/reset/spacemit/reset-spacemit-k1.c --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch b/SPECS/linux-lts-kmhv2/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch new file mode 100644 index 0000000000..7b6a45b12a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch @@ -0,0 +1,316 @@ +From 409dadffdee997565a81b01180b046890adbdd47 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 6 Jan 2026 11:09:33 +0800 +Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit: Add GPIO support for K3 SoC + +SpacemiT K3 SoC has changed gpio register layout while comparing +with previous generation, the register offset and bank offset +need to be adjusted, introduce a compatible data to extend the +driver to support this. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260106-02-k3-gpio-v3-2-4800c214810b@gentoo.org +Signed-off-by: Bartosz Golaszewski +(cherry picked from commit da64eb51595bc6073b2fb69c2a3859bba93ed75a) +Signed-off-by: Han Gao +--- + drivers/gpio/gpio-spacemit-k1.c | 163 +++++++++++++++++++++++--------- + 1 file changed, 117 insertions(+), 46 deletions(-) + +diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c +index eb66a15c002f..8f570a1a4894 100644 +--- a/drivers/gpio/gpio-spacemit-k1.c ++++ b/drivers/gpio/gpio-spacemit-k1.c +@@ -15,29 +15,37 @@ + #include + #include + +-/* register offset */ +-#define SPACEMIT_GPLR 0x00 /* port level - R */ +-#define SPACEMIT_GPDR 0x0c /* port direction - R/W */ +-#define SPACEMIT_GPSR 0x18 /* port set - W */ +-#define SPACEMIT_GPCR 0x24 /* port clear - W */ +-#define SPACEMIT_GRER 0x30 /* port rising edge R/W */ +-#define SPACEMIT_GFER 0x3c /* port falling edge R/W */ +-#define SPACEMIT_GEDR 0x48 /* edge detect status - R/W1C */ +-#define SPACEMIT_GSDR 0x54 /* (set) direction - W */ +-#define SPACEMIT_GCDR 0x60 /* (clear) direction - W */ +-#define SPACEMIT_GSRER 0x6c /* (set) rising edge detect enable - W */ +-#define SPACEMIT_GCRER 0x78 /* (clear) rising edge detect enable - W */ +-#define SPACEMIT_GSFER 0x84 /* (set) falling edge detect enable - W */ +-#define SPACEMIT_GCFER 0x90 /* (clear) falling edge detect enable - W */ +-#define SPACEMIT_GAPMASK 0x9c /* interrupt mask , 0 disable, 1 enable - R/W */ +- + #define SPACEMIT_NR_BANKS 4 + #define SPACEMIT_NR_GPIOS_PER_BANK 32 + + #define to_spacemit_gpio_bank(x) container_of((x), struct spacemit_gpio_bank, gc) ++#define to_spacemit_gpio_regs(gb) ((gb)->sg->data->offsets) ++ ++enum spacemit_gpio_registers { ++ SPACEMIT_GPLR, /* port level - R */ ++ SPACEMIT_GPDR, /* port direction - R/W */ ++ SPACEMIT_GPSR, /* port set - W */ ++ SPACEMIT_GPCR, /* port clear - W */ ++ SPACEMIT_GRER, /* port rising edge R/W */ ++ SPACEMIT_GFER, /* port falling edge R/W */ ++ SPACEMIT_GEDR, /* edge detect status - R/W1C */ ++ SPACEMIT_GSDR, /* (set) direction - W */ ++ SPACEMIT_GCDR, /* (clear) direction - W */ ++ SPACEMIT_GSRER, /* (set) rising edge detect enable - W */ ++ SPACEMIT_GCRER, /* (clear) rising edge detect enable - W */ ++ SPACEMIT_GSFER, /* (set) falling edge detect enable - W */ ++ SPACEMIT_GCFER, /* (clear) falling edge detect enable - W */ ++ SPACEMIT_GAPMASK, /* interrupt mask , 0 disable, 1 enable - R/W */ ++ SPACEMIT_GCPMASK, /* interrupt mask for K3 */ ++}; + + struct spacemit_gpio; + ++struct spacemit_gpio_data { ++ const unsigned int *offsets; ++ u32 bank_offsets[SPACEMIT_NR_BANKS]; ++}; ++ + struct spacemit_gpio_bank { + struct gpio_generic_chip chip; + struct spacemit_gpio *sg; +@@ -49,9 +57,22 @@ struct spacemit_gpio_bank { + + struct spacemit_gpio { + struct device *dev; ++ const struct spacemit_gpio_data *data; + struct spacemit_gpio_bank sgb[SPACEMIT_NR_BANKS]; + }; + ++static u32 spacemit_gpio_read(struct spacemit_gpio_bank *gb, ++ enum spacemit_gpio_registers reg) ++{ ++ return readl(gb->base + to_spacemit_gpio_regs(gb)[reg]); ++} ++ ++static void spacemit_gpio_write(struct spacemit_gpio_bank *gb, ++ enum spacemit_gpio_registers reg, u32 val) ++{ ++ writel(val, gb->base + to_spacemit_gpio_regs(gb)[reg]); ++} ++ + static u32 spacemit_gpio_bank_index(struct spacemit_gpio_bank *gb) + { + return (u32)(gb - gb->sg->sgb); +@@ -63,10 +84,10 @@ static irqreturn_t spacemit_gpio_irq_handler(int irq, void *dev_id) + unsigned long pending; + u32 n, gedr; + +- gedr = readl(gb->base + SPACEMIT_GEDR); ++ gedr = spacemit_gpio_read(gb, SPACEMIT_GEDR); + if (!gedr) + return IRQ_NONE; +- writel(gedr, gb->base + SPACEMIT_GEDR); ++ spacemit_gpio_write(gb, SPACEMIT_GEDR, gedr); + + pending = gedr & gb->irq_mask; + if (!pending) +@@ -82,7 +103,7 @@ static void spacemit_gpio_irq_ack(struct irq_data *d) + { + struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d); + +- writel(BIT(irqd_to_hwirq(d)), gb->base + SPACEMIT_GEDR); ++ spacemit_gpio_write(gb, SPACEMIT_GEDR, BIT(irqd_to_hwirq(d))); + } + + static void spacemit_gpio_irq_mask(struct irq_data *d) +@@ -91,13 +112,13 @@ static void spacemit_gpio_irq_mask(struct irq_data *d) + u32 bit = BIT(irqd_to_hwirq(d)); + + gb->irq_mask &= ~bit; +- writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK); ++ spacemit_gpio_write(gb, SPACEMIT_GAPMASK, gb->irq_mask); + + if (bit & gb->irq_rising_edge) +- writel(bit, gb->base + SPACEMIT_GCRER); ++ spacemit_gpio_write(gb, SPACEMIT_GCRER, bit); + + if (bit & gb->irq_falling_edge) +- writel(bit, gb->base + SPACEMIT_GCFER); ++ spacemit_gpio_write(gb, SPACEMIT_GCFER, bit); + } + + static void spacemit_gpio_irq_unmask(struct irq_data *d) +@@ -108,12 +129,12 @@ static void spacemit_gpio_irq_unmask(struct irq_data *d) + gb->irq_mask |= bit; + + if (bit & gb->irq_rising_edge) +- writel(bit, gb->base + SPACEMIT_GSRER); ++ spacemit_gpio_write(gb, SPACEMIT_GSRER, bit); + + if (bit & gb->irq_falling_edge) +- writel(bit, gb->base + SPACEMIT_GSFER); ++ spacemit_gpio_write(gb, SPACEMIT_GSFER, bit); + +- writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK); ++ spacemit_gpio_write(gb, SPACEMIT_GAPMASK, gb->irq_mask); + } + + static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int type) +@@ -123,18 +144,18 @@ static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int type) + + if (type & IRQ_TYPE_EDGE_RISING) { + gb->irq_rising_edge |= bit; +- writel(bit, gb->base + SPACEMIT_GSRER); ++ spacemit_gpio_write(gb, SPACEMIT_GSRER, bit); + } else { + gb->irq_rising_edge &= ~bit; +- writel(bit, gb->base + SPACEMIT_GCRER); ++ spacemit_gpio_write(gb, SPACEMIT_GCRER, bit); + } + + if (type & IRQ_TYPE_EDGE_FALLING) { + gb->irq_falling_edge |= bit; +- writel(bit, gb->base + SPACEMIT_GSFER); ++ spacemit_gpio_write(gb, SPACEMIT_GSFER, bit); + } else { + gb->irq_falling_edge &= ~bit; +- writel(bit, gb->base + SPACEMIT_GCFER); ++ spacemit_gpio_write(gb, SPACEMIT_GCFER, bit); + } + + return 0; +@@ -179,15 +200,16 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + struct device *dev = sg->dev; + struct gpio_irq_chip *girq; + void __iomem *dat, *set, *clr, *dirin, *dirout; +- int ret, bank_base[] = { 0x0, 0x4, 0x8, 0x100 }; ++ int ret; + +- gb->base = regs + bank_base[index]; ++ gb->base = regs + sg->data->bank_offsets[index]; ++ gb->sg = sg; + +- dat = gb->base + SPACEMIT_GPLR; +- set = gb->base + SPACEMIT_GPSR; +- clr = gb->base + SPACEMIT_GPCR; +- dirin = gb->base + SPACEMIT_GCDR; +- dirout = gb->base + SPACEMIT_GSDR; ++ dat = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPLR]; ++ set = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPSR]; ++ clr = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPCR]; ++ dirin = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GCDR]; ++ dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GSDR]; + + config = (struct gpio_generic_chip_config) { + .dev = dev, +@@ -206,8 +228,6 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + if (ret) + return dev_err_probe(dev, ret, "failed to init gpio chip\n"); + +- gb->sg = sg; +- + gc->label = dev_name(dev); + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; +@@ -223,13 +243,13 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + gpio_irq_chip_set_chip(girq, &spacemit_gpio_chip); + + /* Disable Interrupt */ +- writel(0, gb->base + SPACEMIT_GAPMASK); ++ spacemit_gpio_write(gb, SPACEMIT_GAPMASK, 0); + /* Disable Edge Detection Settings */ +- writel(0x0, gb->base + SPACEMIT_GRER); +- writel(0x0, gb->base + SPACEMIT_GFER); ++ spacemit_gpio_write(gb, SPACEMIT_GRER, 0x0); ++ spacemit_gpio_write(gb, SPACEMIT_GFER, 0x0); + /* Clear Interrupt */ +- writel(0xffffffff, gb->base + SPACEMIT_GCRER); +- writel(0xffffffff, gb->base + SPACEMIT_GCFER); ++ spacemit_gpio_write(gb, SPACEMIT_GCRER, 0xffffffff); ++ spacemit_gpio_write(gb, SPACEMIT_GCFER, 0xffffffff); + + ret = devm_request_threaded_irq(dev, irq, NULL, + spacemit_gpio_irq_handler, +@@ -260,6 +280,10 @@ static int spacemit_gpio_probe(struct platform_device *pdev) + if (!sg) + return -ENOMEM; + ++ sg->data = of_device_get_match_data(dev); ++ if (!sg->data) ++ return dev_err_probe(dev, -EINVAL, "No available compatible data."); ++ + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); +@@ -287,8 +311,55 @@ static int spacemit_gpio_probe(struct platform_device *pdev) + return 0; + } + ++static const unsigned int spacemit_gpio_k1_offsets[] = { ++ [SPACEMIT_GPLR] = 0x00, ++ [SPACEMIT_GPDR] = 0x0c, ++ [SPACEMIT_GPSR] = 0x18, ++ [SPACEMIT_GPCR] = 0x24, ++ [SPACEMIT_GRER] = 0x30, ++ [SPACEMIT_GFER] = 0x3c, ++ [SPACEMIT_GEDR] = 0x48, ++ [SPACEMIT_GSDR] = 0x54, ++ [SPACEMIT_GCDR] = 0x60, ++ [SPACEMIT_GSRER] = 0x6c, ++ [SPACEMIT_GCRER] = 0x78, ++ [SPACEMIT_GSFER] = 0x84, ++ [SPACEMIT_GCFER] = 0x90, ++ [SPACEMIT_GAPMASK] = 0x9c, ++ [SPACEMIT_GCPMASK] = 0xA8, ++}; ++ ++static const unsigned int spacemit_gpio_k3_offsets[] = { ++ [SPACEMIT_GPLR] = 0x0, ++ [SPACEMIT_GPDR] = 0x4, ++ [SPACEMIT_GPSR] = 0x8, ++ [SPACEMIT_GPCR] = 0xc, ++ [SPACEMIT_GRER] = 0x10, ++ [SPACEMIT_GFER] = 0x14, ++ [SPACEMIT_GEDR] = 0x18, ++ [SPACEMIT_GSDR] = 0x1c, ++ [SPACEMIT_GCDR] = 0x20, ++ [SPACEMIT_GSRER] = 0x24, ++ [SPACEMIT_GCRER] = 0x28, ++ [SPACEMIT_GSFER] = 0x2c, ++ [SPACEMIT_GCFER] = 0x30, ++ [SPACEMIT_GAPMASK] = 0x34, ++ [SPACEMIT_GCPMASK] = 0x38, ++}; ++ ++static const struct spacemit_gpio_data k1_gpio_data = { ++ .offsets = spacemit_gpio_k1_offsets, ++ .bank_offsets = { 0x0, 0x4, 0x8, 0x100 }, ++}; ++ ++static const struct spacemit_gpio_data k3_gpio_data = { ++ .offsets = spacemit_gpio_k3_offsets, ++ .bank_offsets = { 0x0, 0x40, 0x80, 0x100 }, ++}; ++ + static const struct of_device_id spacemit_gpio_dt_ids[] = { +- { .compatible = "spacemit,k1-gpio" }, ++ { .compatible = "spacemit,k1-gpio", .data = &k1_gpio_data }, ++ { .compatible = "spacemit,k3-gpio", .data = &k3_gpio_data }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, spacemit_gpio_dt_ids); +@@ -296,12 +367,12 @@ MODULE_DEVICE_TABLE(of, spacemit_gpio_dt_ids); + static struct platform_driver spacemit_gpio_driver = { + .probe = spacemit_gpio_probe, + .driver = { +- .name = "k1-gpio", ++ .name = "spacemit-gpio", + .of_match_table = spacemit_gpio_dt_ids, + }, + }; + module_platform_driver(spacemit_gpio_driver); + + MODULE_AUTHOR("Yixun Lan "); +-MODULE_DESCRIPTION("GPIO driver for SpacemiT K1 SoC"); ++MODULE_DESCRIPTION("GPIO driver for SpacemiT K1/K3 SoC"); + MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0126-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch b/SPECS/linux-lts-kmhv2/0126-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch deleted file mode 100644 index 9da72b5533..0000000000 --- a/SPECS/linux-lts-kmhv2/0126-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch +++ /dev/null @@ -1,364 +0,0 @@ -From dd53659d917a2ad7245d28a312b4a386f3f4d730 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 20 Jan 2026 19:10:51 +0800 -Subject: [PATCH 126/467] UPSTREAM: reset: spacemit: Extract common K1 reset - code - -Extract the common reset controller code from the K1 driver into -separate reset-spacemit-common.{c,h} files to prepare for additional -SpacemiT SoCs that share the same reset controller architecture. - -The common code includes handlers for reset assert and deassert -operations and probing for auxiliary bus devices. - -Changes during extraction: -- Module ownership: Use dev->driver->owner instead of THIS_MODULE in - spacemit_reset_controller_register() to correctly reference the - calling driver's module. -- Rename spacemit_reset_ids to spacemit_k1_reset_ids. -- Define new namespace "RESET_SPACEMIT" for the exported common - functions (spacemit_reset_probe) and update K1 driver to import it. - -This prepares for additional SpacemiT SoCs (K3) that share the same reset -controller architecture. - -Reviewed-by: Alex Elder -Signed-off-by: Guodong Xu -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] -Signed-off-by: Philipp Zabel -(cherry picked from commit aba86f7bff0bfd6956aff9bbbfb0c6ea6d56809e) -Signed-off-by: Han Gao ---- - drivers/reset/spacemit/Kconfig | 17 ++- - drivers/reset/spacemit/Makefile | 2 + - .../reset/spacemit/reset-spacemit-common.c | 77 +++++++++++++ - .../reset/spacemit/reset-spacemit-common.h | 42 +++++++ - drivers/reset/spacemit/reset-spacemit-k1.c | 107 ++---------------- - 5 files changed, 144 insertions(+), 101 deletions(-) - create mode 100644 drivers/reset/spacemit/reset-spacemit-common.c - create mode 100644 drivers/reset/spacemit/reset-spacemit-common.h - -diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig -index 552884e8b72a..56a4858b30e1 100644 ---- a/drivers/reset/spacemit/Kconfig -+++ b/drivers/reset/spacemit/Kconfig -@@ -1,10 +1,20 @@ - # SPDX-License-Identifier: GPL-2.0-only - --config RESET_SPACEMIT_K1 -- tristate "SpacemiT K1 reset driver" -+menu "Reset support for SpacemiT platforms" - depends on ARCH_SPACEMIT || COMPILE_TEST -- depends on SPACEMIT_K1_CCU -+ -+config RESET_SPACEMIT_COMMON -+ tristate - select AUXILIARY_BUS -+ help -+ Common reset controller infrastructure for SpacemiT SoCs. -+ This provides shared code and helper functions used by -+ reset drivers for various SpacemiT SoC families. -+ -+config RESET_SPACEMIT_K1 -+ tristate "Support for SpacemiT K1 SoC" -+ depends on SPACEMIT_K1_CCU -+ select RESET_SPACEMIT_COMMON - default SPACEMIT_K1_CCU - help - Support for reset controller in SpacemiT K1 SoC. -@@ -12,3 +22,4 @@ config RESET_SPACEMIT_K1 - unit (CCU) driver to provide reset control functionality - for various peripherals and subsystems in the SoC. - -+endmenu -diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile -index 34e3350136bb..0b056e8661ec 100644 ---- a/drivers/reset/spacemit/Makefile -+++ b/drivers/reset/spacemit/Makefile -@@ -1,2 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_RESET_SPACEMIT_COMMON) += reset-spacemit-common.o -+ - obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o -diff --git a/drivers/reset/spacemit/reset-spacemit-common.c b/drivers/reset/spacemit/reset-spacemit-common.c -new file mode 100644 -index 000000000000..0626633a5e7d ---- /dev/null -+++ b/drivers/reset/spacemit/reset-spacemit-common.c -@@ -0,0 +1,77 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+/* SpacemiT reset controller driver - common implementation */ -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "reset-spacemit-common.h" -+ -+static int spacemit_reset_update(struct reset_controller_dev *rcdev, -+ unsigned long id, bool assert) -+{ -+ struct ccu_reset_controller *controller; -+ const struct ccu_reset_data *data; -+ u32 mask; -+ u32 val; -+ -+ controller = container_of(rcdev, struct ccu_reset_controller, rcdev); -+ data = &controller->data->reset_data[id]; -+ mask = data->assert_mask | data->deassert_mask; -+ val = assert ? data->assert_mask : data->deassert_mask; -+ -+ return regmap_update_bits(controller->regmap, data->offset, mask, val); -+} -+ -+static int spacemit_reset_assert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ return spacemit_reset_update(rcdev, id, true); -+} -+ -+static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ return spacemit_reset_update(rcdev, id, false); -+} -+ -+static const struct reset_control_ops spacemit_reset_control_ops = { -+ .assert = spacemit_reset_assert, -+ .deassert = spacemit_reset_deassert, -+}; -+ -+static int spacemit_reset_controller_register(struct device *dev, -+ struct ccu_reset_controller *controller) -+{ -+ struct reset_controller_dev *rcdev = &controller->rcdev; -+ -+ rcdev->ops = &spacemit_reset_control_ops; -+ rcdev->owner = dev->driver->owner; -+ rcdev->of_node = dev->of_node; -+ rcdev->nr_resets = controller->data->count; -+ -+ return devm_reset_controller_register(dev, &controller->rcdev); -+} -+ -+int spacemit_reset_probe(struct auxiliary_device *adev, -+ const struct auxiliary_device_id *id) -+{ -+ struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev); -+ struct ccu_reset_controller *controller; -+ struct device *dev = &adev->dev; -+ -+ controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); -+ if (!controller) -+ return -ENOMEM; -+ controller->data = (const struct ccu_reset_controller_data *)id->driver_data; -+ controller->regmap = rdev->regmap; -+ -+ return spacemit_reset_controller_register(dev, controller); -+} -+EXPORT_SYMBOL_NS_GPL(spacemit_reset_probe, "RESET_SPACEMIT"); -+ -+MODULE_DESCRIPTION("SpacemiT reset controller driver - common code"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/reset/spacemit/reset-spacemit-common.h b/drivers/reset/spacemit/reset-spacemit-common.h -new file mode 100644 -index 000000000000..ffaf2f86eb39 ---- /dev/null -+++ b/drivers/reset/spacemit/reset-spacemit-common.h -@@ -0,0 +1,42 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * SpacemiT reset controller driver - common definitions -+ */ -+ -+#ifndef _RESET_SPACEMIT_COMMON_H_ -+#define _RESET_SPACEMIT_COMMON_H_ -+ -+#include -+#include -+#include -+#include -+ -+struct ccu_reset_data { -+ u32 offset; -+ u32 assert_mask; -+ u32 deassert_mask; -+}; -+ -+struct ccu_reset_controller_data { -+ const struct ccu_reset_data *reset_data; /* array */ -+ size_t count; -+}; -+ -+struct ccu_reset_controller { -+ struct reset_controller_dev rcdev; -+ const struct ccu_reset_controller_data *data; -+ struct regmap *regmap; -+}; -+ -+#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ -+ { \ -+ .offset = (_offset), \ -+ .assert_mask = (_assert_mask), \ -+ .deassert_mask = (_deassert_mask), \ -+ } -+ -+/* Common probe function */ -+int spacemit_reset_probe(struct auxiliary_device *adev, -+ const struct auxiliary_device_id *id); -+ -+#endif /* _RESET_SPACEMIT_COMMON_H_ */ -diff --git a/drivers/reset/spacemit/reset-spacemit-k1.c b/drivers/reset/spacemit/reset-spacemit-k1.c -index cc7fd1f8750d..8f3b5329ea5f 100644 ---- a/drivers/reset/spacemit/reset-spacemit-k1.c -+++ b/drivers/reset/spacemit/reset-spacemit-k1.c -@@ -1,41 +1,13 @@ - // SPDX-License-Identifier: GPL-2.0-only - --/* SpacemiT reset controller driver */ -+/* SpacemiT K1 reset controller driver */ - --#include --#include --#include - #include --#include --#include --#include - --#include - #include -+#include - --struct ccu_reset_data { -- u32 offset; -- u32 assert_mask; -- u32 deassert_mask; --}; -- --struct ccu_reset_controller_data { -- const struct ccu_reset_data *reset_data; /* array */ -- size_t count; --}; -- --struct ccu_reset_controller { -- struct reset_controller_dev rcdev; -- const struct ccu_reset_controller_data *data; -- struct regmap *regmap; --}; -- --#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ -- { \ -- .offset = (_offset), \ -- .assert_mask = (_assert_mask), \ -- .deassert_mask = (_deassert_mask), \ -- } -+#include "reset-spacemit-common.h" - - static const struct ccu_reset_data k1_mpmu_resets[] = { - [RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), -@@ -214,91 +186,30 @@ static const struct ccu_reset_controller_data k1_apbc2_reset_data = { - .count = ARRAY_SIZE(k1_apbc2_resets), - }; - --static int spacemit_reset_update(struct reset_controller_dev *rcdev, -- unsigned long id, bool assert) --{ -- struct ccu_reset_controller *controller; -- const struct ccu_reset_data *data; -- u32 mask; -- u32 val; -- -- controller = container_of(rcdev, struct ccu_reset_controller, rcdev); -- data = &controller->data->reset_data[id]; -- mask = data->assert_mask | data->deassert_mask; -- val = assert ? data->assert_mask : data->deassert_mask; -- -- return regmap_update_bits(controller->regmap, data->offset, mask, val); --} -- --static int spacemit_reset_assert(struct reset_controller_dev *rcdev, -- unsigned long id) --{ -- return spacemit_reset_update(rcdev, id, true); --} -- --static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, -- unsigned long id) --{ -- return spacemit_reset_update(rcdev, id, false); --} -- --static const struct reset_control_ops spacemit_reset_control_ops = { -- .assert = spacemit_reset_assert, -- .deassert = spacemit_reset_deassert, --}; -- --static int spacemit_reset_controller_register(struct device *dev, -- struct ccu_reset_controller *controller) --{ -- struct reset_controller_dev *rcdev = &controller->rcdev; -- -- rcdev->ops = &spacemit_reset_control_ops; -- rcdev->owner = THIS_MODULE; -- rcdev->of_node = dev->of_node; -- rcdev->nr_resets = controller->data->count; -- -- return devm_reset_controller_register(dev, &controller->rcdev); --} -- --static int spacemit_reset_probe(struct auxiliary_device *adev, -- const struct auxiliary_device_id *id) --{ -- struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev); -- struct ccu_reset_controller *controller; -- struct device *dev = &adev->dev; -- -- controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); -- if (!controller) -- return -ENOMEM; -- controller->data = (const struct ccu_reset_controller_data *)id->driver_data; -- controller->regmap = rdev->regmap; -- -- return spacemit_reset_controller_register(dev, controller); --} -- - #define K1_AUX_DEV_ID(_unit) \ - { \ - .name = "spacemit_ccu.k1-" #_unit "-reset", \ - .driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ - } - --static const struct auxiliary_device_id spacemit_reset_ids[] = { -+static const struct auxiliary_device_id spacemit_k1_reset_ids[] = { - K1_AUX_DEV_ID(mpmu), - K1_AUX_DEV_ID(apbc), - K1_AUX_DEV_ID(apmu), - K1_AUX_DEV_ID(rcpu), - K1_AUX_DEV_ID(rcpu2), - K1_AUX_DEV_ID(apbc2), -- { }, -+ { /* sentinel */ } - }; --MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids); -+MODULE_DEVICE_TABLE(auxiliary, spacemit_k1_reset_ids); - - static struct auxiliary_driver spacemit_k1_reset_driver = { - .probe = spacemit_reset_probe, -- .id_table = spacemit_reset_ids, -+ .id_table = spacemit_k1_reset_ids, - }; - module_auxiliary_driver(spacemit_k1_reset_driver); - -+MODULE_IMPORT_NS("RESET_SPACEMIT"); - MODULE_AUTHOR("Alex Elder "); --MODULE_DESCRIPTION("SpacemiT reset controller driver"); -+MODULE_DESCRIPTION("SpacemiT K1 reset controller driver"); - MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0127-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch b/SPECS/linux-lts-kmhv2/0127-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch deleted file mode 100644 index 437a1f8811..0000000000 --- a/SPECS/linux-lts-kmhv2/0127-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch +++ /dev/null @@ -1,300 +0,0 @@ -From fd89e8eec8bc5d871ccade81be1d4cd0d0b54ae1 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 20 Jan 2026 19:10:52 +0800 -Subject: [PATCH 127/467] UPSTREAM: reset: spacemit: Add SpacemiT K3 reset - driver - -Add support for the SpacemiT K3 SoC reset controller. The K3 reset -driver reuses the common reset controller code and provides K3-specific -reset data for devices managed by the following units: - - - MPMU (Main Power Management Unit) - - APBC (APB clock unit) - - APMU (Application Subsystem Power Management Unit) - - DCIU (DMA Control and Interface Unit) - -Acked-by: Alex Elder -Signed-off-by: Guodong Xu -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] -Signed-off-by: Philipp Zabel -(cherry picked from commit 938ce3b16582657e67f3bd8a7efa59089c467c90) -Signed-off-by: Han Gao ---- - drivers/reset/spacemit/Kconfig | 11 + - drivers/reset/spacemit/Makefile | 1 + - drivers/reset/spacemit/reset-spacemit-k3.c | 233 +++++++++++++++++++++ - 3 files changed, 245 insertions(+) - create mode 100644 drivers/reset/spacemit/reset-spacemit-k3.c - -diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig -index 56a4858b30e1..545d6b41c6ca 100644 ---- a/drivers/reset/spacemit/Kconfig -+++ b/drivers/reset/spacemit/Kconfig -@@ -22,4 +22,15 @@ config RESET_SPACEMIT_K1 - unit (CCU) driver to provide reset control functionality - for various peripherals and subsystems in the SoC. - -+config RESET_SPACEMIT_K3 -+ tristate "Support for SpacemiT K3 SoC" -+ depends on SPACEMIT_K3_CCU -+ select RESET_SPACEMIT_COMMON -+ default SPACEMIT_K3_CCU -+ help -+ Support for reset controller in SpacemiT K3 SoC. -+ This driver works with the SpacemiT K3 clock controller -+ unit (CCU) driver to provide reset control functionality -+ for various peripherals and subsystems in the SoC. -+ - endmenu -diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile -index 0b056e8661ec..00669132c6ac 100644 ---- a/drivers/reset/spacemit/Makefile -+++ b/drivers/reset/spacemit/Makefile -@@ -2,3 +2,4 @@ - obj-$(CONFIG_RESET_SPACEMIT_COMMON) += reset-spacemit-common.o - - obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o -+obj-$(CONFIG_RESET_SPACEMIT_K3) += reset-spacemit-k3.o -diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c -new file mode 100644 -index 000000000000..e9e32e4c1ba5 ---- /dev/null -+++ b/drivers/reset/spacemit/reset-spacemit-k3.c -@@ -0,0 +1,233 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+/* SpacemiT K3 reset controller driver */ -+ -+#include -+ -+#include -+#include -+ -+#include "reset-spacemit-common.h" -+ -+static const struct ccu_reset_data k3_mpmu_resets[] = { -+ [RESET_MPMU_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), -+ [RESET_MPMU_RIPC] = RESET_DATA(MPMU_RIPCCR, BIT(2), 0), -+}; -+ -+static const struct ccu_reset_controller_data k3_mpmu_reset_data = { -+ .reset_data = k3_mpmu_resets, -+ .count = ARRAY_SIZE(k3_mpmu_resets), -+}; -+ -+static const struct ccu_reset_data k3_apbc_resets[] = { -+ [RESET_APBC_UART0] = RESET_DATA(APBC_UART0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART10] = RESET_DATA(APBC_UART10_CLK_RST, BIT(2), 0), -+ [RESET_APBC_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), 0), -+ [RESET_APBC_SPI0] = RESET_DATA(APBC_SSP0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_SPI1] = RESET_DATA(APBC_SSP1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_SPI3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), -+ [RESET_APBC_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS0] = RESET_DATA(APBC_TIMERS0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS3] = RESET_DATA(APBC_TIMERS3_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS4] = RESET_DATA(APBC_TIMERS4_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS5] = RESET_DATA(APBC_TIMERS5_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS6] = RESET_DATA(APBC_TIMERS6_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS7] = RESET_DATA(APBC_TIMERS7_CLK_RST, BIT(2), 0), -+ [RESET_APBC_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), -+ [RESET_APBC_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), -+ [RESET_APBC_I2S0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_I2S1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_I2S2] = RESET_DATA(APBC_SSPA2_CLK_RST, BIT(2), 0), -+ [RESET_APBC_I2S3] = RESET_DATA(APBC_SSPA3_CLK_RST, BIT(2), 0), -+ [RESET_APBC_I2S4] = RESET_DATA(APBC_SSPA4_CLK_RST, BIT(2), 0), -+ [RESET_APBC_I2S5] = RESET_DATA(APBC_SSPA5_CLK_RST, BIT(2), 0), -+ [RESET_APBC_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), -+ [RESET_APBC_IR0] = RESET_DATA(APBC_IR0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_IR1] = RESET_DATA(APBC_IR1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), -+ [RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), -+ [RESET_APBC_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_CAN1] = RESET_DATA(APBC_CAN1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_CAN2] = RESET_DATA(APBC_CAN2_CLK_RST, BIT(2), 0), -+ [RESET_APBC_CAN3] = RESET_DATA(APBC_CAN3_CLK_RST, BIT(2), 0), -+ [RESET_APBC_CAN4] = RESET_DATA(APBC_CAN4_CLK_RST, BIT(2), 0), -+}; -+ -+static const struct ccu_reset_controller_data k3_apbc_reset_data = { -+ .reset_data = k3_apbc_resets, -+ .count = ARRAY_SIZE(k3_apbc_resets), -+}; -+ -+static const struct ccu_reset_data k3_apmu_resets[] = { -+ [RESET_APMU_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), -+ [RESET_APMU_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), -+ [RESET_APMU_ISP_CIBUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), -+ [RESET_APMU_DSI_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), -+ [RESET_APMU_LCD] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), -+ [RESET_APMU_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), -+ [RESET_APMU_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), -+ [RESET_APMU_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(15)), -+ [RESET_APMU_SC2_HCLK] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), -+ [RESET_APMU_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -+ BIT(1)|BIT(2)|BIT(3)), -+ [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -+ BIT(5)|BIT(6)|BIT(7)), -+ [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -+ BIT(9)|BIT(10)|BIT(11)), -+ [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -+ BIT(13)|BIT(14)|BIT(15)), -+ [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -+ BIT(17)|BIT(18)|BIT(19)), -+ [RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_AES_WTM] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), -+ [RESET_APMU_MCB_DCLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_MCB_ACLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_DTC] = RESET_DATA(APMU_DTC_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), -+ [RESET_APMU_CPU0_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(0), 0), -+ [RESET_APMU_CPU0_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(1), 0), -+ [RESET_APMU_CPU1_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(3), 0), -+ [RESET_APMU_CPU1_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(4), 0), -+ [RESET_APMU_CPU2_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(6), 0), -+ [RESET_APMU_CPU2_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(7), 0), -+ [RESET_APMU_CPU3_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(9), 0), -+ [RESET_APMU_CPU3_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(10), 0), -+ [RESET_APMU_C0_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(12), 0), -+ [RESET_APMU_CPU4_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(16), 0), -+ [RESET_APMU_CPU4_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(17), 0), -+ [RESET_APMU_CPU5_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(19), 0), -+ [RESET_APMU_CPU5_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(20), 0), -+ [RESET_APMU_CPU6_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(22), 0), -+ [RESET_APMU_CPU6_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(23), 0), -+ [RESET_APMU_CPU7_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(25), 0), -+ [RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), -+ [RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), -+ [RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), -+ [RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL, -+ BIT(1) | BIT(2) | BIT(3), 0), -+ [RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, -+ BIT(3) | BIT(2) | BIT(0)), -+ [RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)), -+ [RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)), -+ [RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)), -+ [RESET_APMU_DSI4LN2_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(15)), -+ [RESET_APMU_DSI4LN2_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(0)), -+ [RESET_APMU_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(15)), -+ [RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), -+ [RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), -+ [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, -+ BIT(5) | BIT(4) | BIT(3)), -+ [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, -+ BIT(5) | BIT(4) | BIT(3)), -+ [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, -+ BIT(5) | BIT(4) | BIT(3)), -+ [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, -+ BIT(5) | BIT(4) | BIT(3)), -+ [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, -+ BIT(5) | BIT(4) | BIT(3)), -+ [RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_ESPI_MCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_ESPI_SCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(2)), -+}; -+ -+static const struct ccu_reset_controller_data k3_apmu_reset_data = { -+ .reset_data = k3_apmu_resets, -+ .count = ARRAY_SIZE(k3_apmu_resets), -+}; -+ -+static const struct ccu_reset_data k3_dciu_resets[] = { -+ [RESET_DCIU_HDMA] = RESET_DATA(DCIU_DMASYS_RSTN, 0, BIT(0)), -+ [RESET_DCIU_DMA350] = RESET_DATA(DCIU_DMASYS_SDMA_RSTN, 0, BIT(0)), -+ [RESET_DCIU_DMA350_0] = RESET_DATA(DCIU_DMASYS_S0_RSTN, 0, BIT(0)), -+ [RESET_DCIU_DMA350_1] = RESET_DATA(DCIU_DMASYS_S1_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA0] = RESET_DATA(DCIU_DMASYS_A0_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA1] = RESET_DATA(DCIU_DMASYS_A1_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA2] = RESET_DATA(DCIU_DMASYS_A2_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA3] = RESET_DATA(DCIU_DMASYS_A3_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA4] = RESET_DATA(DCIU_DMASYS_A4_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA5] = RESET_DATA(DCIU_DMASYS_A5_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA6] = RESET_DATA(DCIU_DMASYS_A6_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA7] = RESET_DATA(DCIU_DMASYS_A7_RSTN, 0, BIT(0)), -+}; -+ -+static const struct ccu_reset_controller_data k3_dciu_reset_data = { -+ .reset_data = k3_dciu_resets, -+ .count = ARRAY_SIZE(k3_dciu_resets), -+}; -+ -+#define K3_AUX_DEV_ID(_unit) \ -+ { \ -+ .name = "spacemit_ccu.k3-" #_unit "-reset", \ -+ .driver_data = (kernel_ulong_t)&k3_ ## _unit ## _reset_data, \ -+ } -+ -+static const struct auxiliary_device_id spacemit_k3_reset_ids[] = { -+ K3_AUX_DEV_ID(mpmu), -+ K3_AUX_DEV_ID(apbc), -+ K3_AUX_DEV_ID(apmu), -+ K3_AUX_DEV_ID(dciu), -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(auxiliary, spacemit_k3_reset_ids); -+ -+static struct auxiliary_driver spacemit_k3_reset_driver = { -+ .probe = spacemit_reset_probe, -+ .id_table = spacemit_k3_reset_ids, -+}; -+module_auxiliary_driver(spacemit_k3_reset_driver); -+ -+MODULE_IMPORT_NS("RESET_SPACEMIT"); -+MODULE_AUTHOR("Guodong Xu "); -+MODULE_DESCRIPTION("SpacemiT K3 reset controller driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch b/SPECS/linux-lts-kmhv2/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch new file mode 100644 index 0000000000..a2882d0c20 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch @@ -0,0 +1,64 @@ +From ea85c56c78cbe48a0e645e57bb5d0151fa6f9bfa Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Tue, 20 Jan 2026 18:00:01 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Disable ETH PHY sleep + mode for OrangePi + +On the SpacemiT K1 platform, the MAC can't read statistics when the PHY +clock stops. Disable Link Down Power Saving Mode for the YT8531C PHY on +OrangePi R2S and RV2 boards to avoid reading statistics timeout logs. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260120100001.1285624-2-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit 5164e95565d3fd508ca8a95351323f5716dfb695) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts | 2 ++ + arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 2 ++ + 2 files changed, 4 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index 58098c4a2aab..de75f6aac740 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -52,6 +52,7 @@ mdio-bus { + + rgmii0: phy@1 { + reg = <0x1>; ++ motorcomm,auto-sleep-disabled; + }; + }; + }; +@@ -75,6 +76,7 @@ mdio-bus { + + rgmii1: phy@1 { + reg = <0x1>; ++ motorcomm,auto-sleep-disabled; + }; + }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 41dc8e35e6eb..7b7331cb3c72 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -54,6 +54,7 @@ mdio-bus { + + rgmii0: phy@1 { + reg = <0x1>; ++ motorcomm,auto-sleep-disabled; + }; + }; + }; +@@ -77,6 +78,7 @@ mdio-bus { + + rgmii1: phy@1 { + reg = <0x1>; ++ motorcomm,auto-sleep-disabled; + }; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch b/SPECS/linux-lts-kmhv2/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch new file mode 100644 index 0000000000..412075183b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch @@ -0,0 +1,33 @@ +From 8731712faebb3034f523e3ed6e95191f5e47a01b Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:10 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: clock: thead,th1520-clk-ap: Add + ID for C910 bus clock + +Add binding ID for C910 bus clock, which takes CLK_C910 as parent and is +essential for C910 cluster's operation. + +Acked-by: Conor Dooley +Signed-off-by: Yao Zi +Signed-off-by: Drew Fustini +(cherry picked from commit 5f352125f8a0bc906dff8419a2377903012d7f35) +Signed-off-by: Han Gao +--- + include/dt-bindings/clock/thead,th1520-clk-ap.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h +index 09a9aa7b3ab1..68b35cc61204 100644 +--- a/include/dt-bindings/clock/thead,th1520-clk-ap.h ++++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h +@@ -93,6 +93,7 @@ + #define CLK_SRAM3 83 + #define CLK_PLL_GMAC_100M 84 + #define CLK_UART_SCLK 85 ++#define CLK_C910_BUS 86 + + /* VO clocks */ + #define CLK_AXI4_VO_ACLK 0 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0128-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch b/SPECS/linux-lts-kmhv2/0128-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch deleted file mode 100644 index cdf007650e..0000000000 --- a/SPECS/linux-lts-kmhv2/0128-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e384f721e2318cd682396313c94562368356bdec Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 6 Jan 2026 11:09:32 +0800 -Subject: [PATCH 128/467] UPSTREAM: dt-bindings: gpio: spacemit: add compatible - name for K3 SoC - -Add new compatible string for SpacemiT K3 SoC's GPIO controller. - -Acked-by: Krzysztof Kozlowski -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260106-02-k3-gpio-v3-1-4800c214810b@gentoo.org -Signed-off-by: Bartosz Golaszewski -(cherry picked from commit 48033e4c677be4e3f131df454d44a5d1fb1b334f) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml -index 83e0b2d14c9f..24d22d95665f 100644 ---- a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml -+++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml -@@ -19,7 +19,9 @@ properties: - pattern: "^gpio@[0-9a-f]+$" - - compatible: -- const: spacemit,k1-gpio -+ enum: -+ - spacemit,k1-gpio -+ - spacemit,k3-gpio - - reg: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch b/SPECS/linux-lts-kmhv2/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch new file mode 100644 index 0000000000..e28d1d6f4f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch @@ -0,0 +1,62 @@ +From 43765d604a0ac503f549b2772fc89a67b6df8779 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:12 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Add C910 bus clock + +This divider takes c910_clk as parent and is essential for the C910 +cluster to operate, thus is marked as CLK_IS_CRITICAL. + +Reviewed-by: Drew Fustini +Signed-off-by: Yao Zi +Signed-off-by: Drew Fustini +(cherry picked from commit b436f8a82aaa3bd54cb79b1219d94a99f7351d33) +Signed-off-by: Han Gao +--- + drivers/clk/thead/clk-th1520-ap.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c +index d870f0c665f8..b820d47387bb 100644 +--- a/drivers/clk/thead/clk-th1520-ap.c ++++ b/drivers/clk/thead/clk-th1520-ap.c +@@ -539,6 +539,20 @@ static struct ccu_mux c910_clk = { + .mux = TH_CCU_MUX("c910", c910_parents, 0, 1), + }; + ++static struct ccu_div c910_bus_clk = { ++ .enable = BIT(7), ++ .div_en = BIT(11), ++ .div = TH_CCU_DIV_FLAGS(8, 3, 0), ++ .common = { ++ .clkid = CLK_C910_BUS, ++ .cfg0 = 0x100, ++ .hw.init = CLK_HW_INIT_HW("c910-bus", ++ &c910_clk.mux.hw, ++ &ccu_div_ops, ++ CLK_IS_CRITICAL), ++ }, ++}; ++ + static const struct clk_parent_data ahb2_cpusys_parents[] = { + { .hw = &gmac_pll_clk.common.hw }, + { .index = 0 } +@@ -1051,6 +1065,7 @@ static struct ccu_common *th1520_pll_clks[] = { + }; + + static struct ccu_common *th1520_div_clks[] = { ++ &c910_bus_clk.common, + &ahb2_cpusys_hclk.common, + &apb3_cpusys_pclk.common, + &axi4_cpusys2_aclk.common, +@@ -1194,7 +1209,7 @@ static const struct th1520_plat_data th1520_ap_platdata = { + .th1520_mux_clks = th1520_mux_clks, + .th1520_gate_clks = th1520_gate_clks, + +- .nr_clks = CLK_UART_SCLK + 1, ++ .nr_clks = CLK_C910_BUS + 1, + + .nr_pll_clks = ARRAY_SIZE(th1520_pll_clks), + .nr_div_clks = ARRAY_SIZE(th1520_div_clks), +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0129-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch b/SPECS/linux-lts-kmhv2/0129-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch deleted file mode 100644 index 8f4194d8bf..0000000000 --- a/SPECS/linux-lts-kmhv2/0129-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch +++ /dev/null @@ -1,316 +0,0 @@ -From a0fdf97c15b11ba0954d550993bad54d718c63e2 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 6 Jan 2026 11:09:33 +0800 -Subject: [PATCH 129/467] UPSTREAM: gpio: spacemit: Add GPIO support for K3 SoC - -SpacemiT K3 SoC has changed gpio register layout while comparing -with previous generation, the register offset and bank offset -need to be adjusted, introduce a compatible data to extend the -driver to support this. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260106-02-k3-gpio-v3-2-4800c214810b@gentoo.org -Signed-off-by: Bartosz Golaszewski -(cherry picked from commit da64eb51595bc6073b2fb69c2a3859bba93ed75a) -Signed-off-by: Han Gao ---- - drivers/gpio/gpio-spacemit-k1.c | 163 +++++++++++++++++++++++--------- - 1 file changed, 117 insertions(+), 46 deletions(-) - -diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c -index eb66a15c002f..8f570a1a4894 100644 ---- a/drivers/gpio/gpio-spacemit-k1.c -+++ b/drivers/gpio/gpio-spacemit-k1.c -@@ -15,29 +15,37 @@ - #include - #include - --/* register offset */ --#define SPACEMIT_GPLR 0x00 /* port level - R */ --#define SPACEMIT_GPDR 0x0c /* port direction - R/W */ --#define SPACEMIT_GPSR 0x18 /* port set - W */ --#define SPACEMIT_GPCR 0x24 /* port clear - W */ --#define SPACEMIT_GRER 0x30 /* port rising edge R/W */ --#define SPACEMIT_GFER 0x3c /* port falling edge R/W */ --#define SPACEMIT_GEDR 0x48 /* edge detect status - R/W1C */ --#define SPACEMIT_GSDR 0x54 /* (set) direction - W */ --#define SPACEMIT_GCDR 0x60 /* (clear) direction - W */ --#define SPACEMIT_GSRER 0x6c /* (set) rising edge detect enable - W */ --#define SPACEMIT_GCRER 0x78 /* (clear) rising edge detect enable - W */ --#define SPACEMIT_GSFER 0x84 /* (set) falling edge detect enable - W */ --#define SPACEMIT_GCFER 0x90 /* (clear) falling edge detect enable - W */ --#define SPACEMIT_GAPMASK 0x9c /* interrupt mask , 0 disable, 1 enable - R/W */ -- - #define SPACEMIT_NR_BANKS 4 - #define SPACEMIT_NR_GPIOS_PER_BANK 32 - - #define to_spacemit_gpio_bank(x) container_of((x), struct spacemit_gpio_bank, gc) -+#define to_spacemit_gpio_regs(gb) ((gb)->sg->data->offsets) -+ -+enum spacemit_gpio_registers { -+ SPACEMIT_GPLR, /* port level - R */ -+ SPACEMIT_GPDR, /* port direction - R/W */ -+ SPACEMIT_GPSR, /* port set - W */ -+ SPACEMIT_GPCR, /* port clear - W */ -+ SPACEMIT_GRER, /* port rising edge R/W */ -+ SPACEMIT_GFER, /* port falling edge R/W */ -+ SPACEMIT_GEDR, /* edge detect status - R/W1C */ -+ SPACEMIT_GSDR, /* (set) direction - W */ -+ SPACEMIT_GCDR, /* (clear) direction - W */ -+ SPACEMIT_GSRER, /* (set) rising edge detect enable - W */ -+ SPACEMIT_GCRER, /* (clear) rising edge detect enable - W */ -+ SPACEMIT_GSFER, /* (set) falling edge detect enable - W */ -+ SPACEMIT_GCFER, /* (clear) falling edge detect enable - W */ -+ SPACEMIT_GAPMASK, /* interrupt mask , 0 disable, 1 enable - R/W */ -+ SPACEMIT_GCPMASK, /* interrupt mask for K3 */ -+}; - - struct spacemit_gpio; - -+struct spacemit_gpio_data { -+ const unsigned int *offsets; -+ u32 bank_offsets[SPACEMIT_NR_BANKS]; -+}; -+ - struct spacemit_gpio_bank { - struct gpio_generic_chip chip; - struct spacemit_gpio *sg; -@@ -49,9 +57,22 @@ struct spacemit_gpio_bank { - - struct spacemit_gpio { - struct device *dev; -+ const struct spacemit_gpio_data *data; - struct spacemit_gpio_bank sgb[SPACEMIT_NR_BANKS]; - }; - -+static u32 spacemit_gpio_read(struct spacemit_gpio_bank *gb, -+ enum spacemit_gpio_registers reg) -+{ -+ return readl(gb->base + to_spacemit_gpio_regs(gb)[reg]); -+} -+ -+static void spacemit_gpio_write(struct spacemit_gpio_bank *gb, -+ enum spacemit_gpio_registers reg, u32 val) -+{ -+ writel(val, gb->base + to_spacemit_gpio_regs(gb)[reg]); -+} -+ - static u32 spacemit_gpio_bank_index(struct spacemit_gpio_bank *gb) - { - return (u32)(gb - gb->sg->sgb); -@@ -63,10 +84,10 @@ static irqreturn_t spacemit_gpio_irq_handler(int irq, void *dev_id) - unsigned long pending; - u32 n, gedr; - -- gedr = readl(gb->base + SPACEMIT_GEDR); -+ gedr = spacemit_gpio_read(gb, SPACEMIT_GEDR); - if (!gedr) - return IRQ_NONE; -- writel(gedr, gb->base + SPACEMIT_GEDR); -+ spacemit_gpio_write(gb, SPACEMIT_GEDR, gedr); - - pending = gedr & gb->irq_mask; - if (!pending) -@@ -82,7 +103,7 @@ static void spacemit_gpio_irq_ack(struct irq_data *d) - { - struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d); - -- writel(BIT(irqd_to_hwirq(d)), gb->base + SPACEMIT_GEDR); -+ spacemit_gpio_write(gb, SPACEMIT_GEDR, BIT(irqd_to_hwirq(d))); - } - - static void spacemit_gpio_irq_mask(struct irq_data *d) -@@ -91,13 +112,13 @@ static void spacemit_gpio_irq_mask(struct irq_data *d) - u32 bit = BIT(irqd_to_hwirq(d)); - - gb->irq_mask &= ~bit; -- writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK); -+ spacemit_gpio_write(gb, SPACEMIT_GAPMASK, gb->irq_mask); - - if (bit & gb->irq_rising_edge) -- writel(bit, gb->base + SPACEMIT_GCRER); -+ spacemit_gpio_write(gb, SPACEMIT_GCRER, bit); - - if (bit & gb->irq_falling_edge) -- writel(bit, gb->base + SPACEMIT_GCFER); -+ spacemit_gpio_write(gb, SPACEMIT_GCFER, bit); - } - - static void spacemit_gpio_irq_unmask(struct irq_data *d) -@@ -108,12 +129,12 @@ static void spacemit_gpio_irq_unmask(struct irq_data *d) - gb->irq_mask |= bit; - - if (bit & gb->irq_rising_edge) -- writel(bit, gb->base + SPACEMIT_GSRER); -+ spacemit_gpio_write(gb, SPACEMIT_GSRER, bit); - - if (bit & gb->irq_falling_edge) -- writel(bit, gb->base + SPACEMIT_GSFER); -+ spacemit_gpio_write(gb, SPACEMIT_GSFER, bit); - -- writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK); -+ spacemit_gpio_write(gb, SPACEMIT_GAPMASK, gb->irq_mask); - } - - static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int type) -@@ -123,18 +144,18 @@ static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int type) - - if (type & IRQ_TYPE_EDGE_RISING) { - gb->irq_rising_edge |= bit; -- writel(bit, gb->base + SPACEMIT_GSRER); -+ spacemit_gpio_write(gb, SPACEMIT_GSRER, bit); - } else { - gb->irq_rising_edge &= ~bit; -- writel(bit, gb->base + SPACEMIT_GCRER); -+ spacemit_gpio_write(gb, SPACEMIT_GCRER, bit); - } - - if (type & IRQ_TYPE_EDGE_FALLING) { - gb->irq_falling_edge |= bit; -- writel(bit, gb->base + SPACEMIT_GSFER); -+ spacemit_gpio_write(gb, SPACEMIT_GSFER, bit); - } else { - gb->irq_falling_edge &= ~bit; -- writel(bit, gb->base + SPACEMIT_GCFER); -+ spacemit_gpio_write(gb, SPACEMIT_GCFER, bit); - } - - return 0; -@@ -179,15 +200,16 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - struct device *dev = sg->dev; - struct gpio_irq_chip *girq; - void __iomem *dat, *set, *clr, *dirin, *dirout; -- int ret, bank_base[] = { 0x0, 0x4, 0x8, 0x100 }; -+ int ret; - -- gb->base = regs + bank_base[index]; -+ gb->base = regs + sg->data->bank_offsets[index]; -+ gb->sg = sg; - -- dat = gb->base + SPACEMIT_GPLR; -- set = gb->base + SPACEMIT_GPSR; -- clr = gb->base + SPACEMIT_GPCR; -- dirin = gb->base + SPACEMIT_GCDR; -- dirout = gb->base + SPACEMIT_GSDR; -+ dat = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPLR]; -+ set = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPSR]; -+ clr = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPCR]; -+ dirin = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GCDR]; -+ dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GSDR]; - - config = (struct gpio_generic_chip_config) { - .dev = dev, -@@ -206,8 +228,6 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - if (ret) - return dev_err_probe(dev, ret, "failed to init gpio chip\n"); - -- gb->sg = sg; -- - gc->label = dev_name(dev); - gc->request = gpiochip_generic_request; - gc->free = gpiochip_generic_free; -@@ -223,13 +243,13 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - gpio_irq_chip_set_chip(girq, &spacemit_gpio_chip); - - /* Disable Interrupt */ -- writel(0, gb->base + SPACEMIT_GAPMASK); -+ spacemit_gpio_write(gb, SPACEMIT_GAPMASK, 0); - /* Disable Edge Detection Settings */ -- writel(0x0, gb->base + SPACEMIT_GRER); -- writel(0x0, gb->base + SPACEMIT_GFER); -+ spacemit_gpio_write(gb, SPACEMIT_GRER, 0x0); -+ spacemit_gpio_write(gb, SPACEMIT_GFER, 0x0); - /* Clear Interrupt */ -- writel(0xffffffff, gb->base + SPACEMIT_GCRER); -- writel(0xffffffff, gb->base + SPACEMIT_GCFER); -+ spacemit_gpio_write(gb, SPACEMIT_GCRER, 0xffffffff); -+ spacemit_gpio_write(gb, SPACEMIT_GCFER, 0xffffffff); - - ret = devm_request_threaded_irq(dev, irq, NULL, - spacemit_gpio_irq_handler, -@@ -260,6 +280,10 @@ static int spacemit_gpio_probe(struct platform_device *pdev) - if (!sg) - return -ENOMEM; - -+ sg->data = of_device_get_match_data(dev); -+ if (!sg->data) -+ return dev_err_probe(dev, -EINVAL, "No available compatible data."); -+ - regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); -@@ -287,8 +311,55 @@ static int spacemit_gpio_probe(struct platform_device *pdev) - return 0; - } - -+static const unsigned int spacemit_gpio_k1_offsets[] = { -+ [SPACEMIT_GPLR] = 0x00, -+ [SPACEMIT_GPDR] = 0x0c, -+ [SPACEMIT_GPSR] = 0x18, -+ [SPACEMIT_GPCR] = 0x24, -+ [SPACEMIT_GRER] = 0x30, -+ [SPACEMIT_GFER] = 0x3c, -+ [SPACEMIT_GEDR] = 0x48, -+ [SPACEMIT_GSDR] = 0x54, -+ [SPACEMIT_GCDR] = 0x60, -+ [SPACEMIT_GSRER] = 0x6c, -+ [SPACEMIT_GCRER] = 0x78, -+ [SPACEMIT_GSFER] = 0x84, -+ [SPACEMIT_GCFER] = 0x90, -+ [SPACEMIT_GAPMASK] = 0x9c, -+ [SPACEMIT_GCPMASK] = 0xA8, -+}; -+ -+static const unsigned int spacemit_gpio_k3_offsets[] = { -+ [SPACEMIT_GPLR] = 0x0, -+ [SPACEMIT_GPDR] = 0x4, -+ [SPACEMIT_GPSR] = 0x8, -+ [SPACEMIT_GPCR] = 0xc, -+ [SPACEMIT_GRER] = 0x10, -+ [SPACEMIT_GFER] = 0x14, -+ [SPACEMIT_GEDR] = 0x18, -+ [SPACEMIT_GSDR] = 0x1c, -+ [SPACEMIT_GCDR] = 0x20, -+ [SPACEMIT_GSRER] = 0x24, -+ [SPACEMIT_GCRER] = 0x28, -+ [SPACEMIT_GSFER] = 0x2c, -+ [SPACEMIT_GCFER] = 0x30, -+ [SPACEMIT_GAPMASK] = 0x34, -+ [SPACEMIT_GCPMASK] = 0x38, -+}; -+ -+static const struct spacemit_gpio_data k1_gpio_data = { -+ .offsets = spacemit_gpio_k1_offsets, -+ .bank_offsets = { 0x0, 0x4, 0x8, 0x100 }, -+}; -+ -+static const struct spacemit_gpio_data k3_gpio_data = { -+ .offsets = spacemit_gpio_k3_offsets, -+ .bank_offsets = { 0x0, 0x40, 0x80, 0x100 }, -+}; -+ - static const struct of_device_id spacemit_gpio_dt_ids[] = { -- { .compatible = "spacemit,k1-gpio" }, -+ { .compatible = "spacemit,k1-gpio", .data = &k1_gpio_data }, -+ { .compatible = "spacemit,k3-gpio", .data = &k3_gpio_data }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, spacemit_gpio_dt_ids); -@@ -296,12 +367,12 @@ MODULE_DEVICE_TABLE(of, spacemit_gpio_dt_ids); - static struct platform_driver spacemit_gpio_driver = { - .probe = spacemit_gpio_probe, - .driver = { -- .name = "k1-gpio", -+ .name = "spacemit-gpio", - .of_match_table = spacemit_gpio_dt_ids, - }, - }; - module_platform_driver(spacemit_gpio_driver); - - MODULE_AUTHOR("Yixun Lan "); --MODULE_DESCRIPTION("GPIO driver for SpacemiT K1 SoC"); -+MODULE_DESCRIPTION("GPIO driver for SpacemiT K1/K3 SoC"); - MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch b/SPECS/linux-lts-kmhv2/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch new file mode 100644 index 0000000000..0f3eeb5de1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch @@ -0,0 +1,275 @@ +From 00eda1e45b3379884782a9a27d245fcff13f8772 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:13 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Support setting PLL + rates + +TH1520 ships several PLLs that could operate in either integer or +fractional mode. However, the TRM only lists a few configuration whose +stability is considered guaranteed. + +Add a table-lookup rate determination logic to support PLL rate setting, +and fill up frequency-configuration tables for AP-subsystem PLLs. + +Reviewed-by: Drew Fustini +Signed-off-by: Yao Zi +Signed-off-by: Drew Fustini +(cherry picked from commit 238cc6316a885765fd52a6dc65b9ca4e47647b1e) +Signed-off-by: Han Gao +--- + drivers/clk/thead/clk-th1520-ap.c | 142 ++++++++++++++++++++++++++++++ + 1 file changed, 142 insertions(+) + +diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c +index b820d47387bb..bf8e80c39a9e 100644 +--- a/drivers/clk/thead/clk-th1520-ap.c ++++ b/drivers/clk/thead/clk-th1520-ap.c +@@ -22,6 +22,7 @@ + #define TH1520_PLL_REFDIV GENMASK(5, 0) + #define TH1520_PLL_BYPASS BIT(30) + #define TH1520_PLL_VCO_RST BIT(29) ++#define TH1520_PLL_DACPD BIT(25) + #define TH1520_PLL_DSMPD BIT(24) + #define TH1520_PLL_FRAC GENMASK(23, 0) + #define TH1520_PLL_FRAC_BITS 24 +@@ -72,9 +73,19 @@ struct ccu_div { + struct ccu_common common; + }; + ++struct ccu_pll_cfg { ++ unsigned long freq; ++ u32 fbdiv; ++ u32 frac; ++ u32 postdiv1; ++ u32 postdiv2; ++}; ++ + struct ccu_pll { + struct ccu_common common; + u32 lock_sts_mask; ++ int cfgnum; ++ const struct ccu_pll_cfg *cfgs; + }; + + #define TH_CCU_ARG(_shift, _width) \ +@@ -391,17 +402,102 @@ static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw, + return rate; + } + ++static const struct ccu_pll_cfg *ccu_pll_lookup_best_cfg(struct ccu_pll *pll, ++ unsigned long rate) ++{ ++ unsigned long best_delta = ULONG_MAX; ++ const struct ccu_pll_cfg *best_cfg; ++ int i; ++ ++ for (i = 0; i < pll->cfgnum; i++) { ++ const struct ccu_pll_cfg *cfg = &pll->cfgs[i]; ++ unsigned long delta; ++ ++ delta = abs_diff(cfg->freq, rate); ++ if (delta < best_delta) { ++ best_delta = delta; ++ best_cfg = cfg; ++ } ++ } ++ ++ return best_cfg; ++} ++ ++static int ccu_pll_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ ++ req->rate = ccu_pll_lookup_best_cfg(pll, req->rate)->freq; ++ ++ return 0; ++} ++ ++static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ const struct ccu_pll_cfg *cfg; ++ ++ cfg = ccu_pll_lookup_best_cfg(pll, rate); ++ ++ ccu_pll_disable(hw); ++ ++ regmap_write(pll->common.map, pll->common.cfg0, ++ FIELD_PREP(TH1520_PLL_REFDIV, 1) | ++ FIELD_PREP(TH1520_PLL_FBDIV, cfg->fbdiv) | ++ FIELD_PREP(TH1520_PLL_POSTDIV1, cfg->postdiv1) | ++ FIELD_PREP(TH1520_PLL_POSTDIV2, cfg->postdiv2)); ++ ++ regmap_update_bits(pll->common.map, pll->common.cfg1, ++ TH1520_PLL_DACPD | TH1520_PLL_DSMPD | ++ TH1520_PLL_FRAC, ++ cfg->frac ? cfg->frac : ++ TH1520_PLL_DACPD | TH1520_PLL_DSMPD); ++ ++ return ccu_pll_enable(hw); ++} ++ + static const struct clk_ops clk_pll_ops = { + .disable = ccu_pll_disable, + .enable = ccu_pll_enable, + .is_enabled = ccu_pll_is_enabled, + .recalc_rate = ccu_pll_recalc_rate, ++ .determine_rate = ccu_pll_determine_rate, ++ .set_rate = ccu_pll_set_rate, + }; + + static const struct clk_parent_data osc_24m_clk[] = { + { .index = 0 } + }; + ++static const struct ccu_pll_cfg cpu_pll_cfgs[] = { ++ { 125000000, 125, 0, 6, 4 }, ++ { 200000000, 125, 0, 5, 3 }, ++ { 300000000, 125, 0, 5, 2 }, ++ { 400000000, 100, 0, 3, 2 }, ++ { 500000000, 125, 0, 6, 1 }, ++ { 600000000, 125, 0, 5, 1 }, ++ { 702000000, 117, 0, 4, 1 }, ++ { 800000000, 100, 0, 3, 1 }, ++ { 900000000, 75, 0, 2, 1 }, ++ { 1000000000, 125, 0, 3, 1 }, ++ { 1104000000, 92, 0, 2, 1 }, ++ { 1200000000, 100, 0, 2, 1 }, ++ { 1296000000, 108, 0, 2, 1 }, ++ { 1404000000, 117, 0, 2, 1 }, ++ { 1500000000, 125, 0, 2, 1 }, ++ { 1608000000, 67, 0, 1, 1 }, ++ { 1704000000, 71, 0, 1, 1 }, ++ { 1800000000, 75, 0, 1, 1 }, ++ { 1896000000, 79, 0, 1, 1 }, ++ { 1992000000, 83, 0, 1, 1 }, ++ { 2112000000, 88, 0, 1, 1 }, ++ { 2208000000, 92, 0, 1, 1 }, ++ { 2304000000, 96, 0, 1, 1 }, ++ { 2400000000, 100, 0, 1, 1 }, ++}; ++ + static struct ccu_pll cpu_pll0_clk = { + .common = { + .clkid = CLK_CPU_PLL0, +@@ -413,6 +509,8 @@ static struct ccu_pll cpu_pll0_clk = { + CLK_IS_CRITICAL), + }, + .lock_sts_mask = BIT(1), ++ .cfgnum = ARRAY_SIZE(cpu_pll_cfgs), ++ .cfgs = cpu_pll_cfgs, + }; + + static struct ccu_pll cpu_pll1_clk = { +@@ -426,6 +524,16 @@ static struct ccu_pll cpu_pll1_clk = { + CLK_IS_CRITICAL), + }, + .lock_sts_mask = BIT(4), ++ .cfgnum = ARRAY_SIZE(cpu_pll_cfgs), ++ .cfgs = cpu_pll_cfgs, ++}; ++ ++static const struct ccu_pll_cfg gmac_pll_cfg = { ++ .freq = 1000000000, ++ .fbdiv = 125, ++ .frac = 0, ++ .postdiv1 = 3, ++ .postdiv2 = 1, + }; + + static struct ccu_pll gmac_pll_clk = { +@@ -439,6 +547,8 @@ static struct ccu_pll gmac_pll_clk = { + CLK_IS_CRITICAL), + }, + .lock_sts_mask = BIT(3), ++ .cfgnum = 1, ++ .cfgs = &gmac_pll_cfg, + }; + + static const struct clk_hw *gmac_pll_clk_parent[] = { +@@ -449,6 +559,14 @@ static const struct clk_parent_data gmac_pll_clk_pd[] = { + { .hw = &gmac_pll_clk.common.hw } + }; + ++static const struct ccu_pll_cfg video_pll_cfg = { ++ .freq = 792000000, ++ .fbdiv = 99, ++ .frac = 0, ++ .postdiv1 = 3, ++ .postdiv2 = 1, ++}; ++ + static struct ccu_pll video_pll_clk = { + .common = { + .clkid = CLK_VIDEO_PLL, +@@ -460,6 +578,8 @@ static struct ccu_pll video_pll_clk = { + CLK_IS_CRITICAL), + }, + .lock_sts_mask = BIT(7), ++ .cfgnum = 1, ++ .cfgs = &video_pll_cfg, + }; + + static const struct clk_hw *video_pll_clk_parent[] = { +@@ -470,6 +590,14 @@ static const struct clk_parent_data video_pll_clk_pd[] = { + { .hw = &video_pll_clk.common.hw } + }; + ++static const struct ccu_pll_cfg dpu_pll_cfg = { ++ .freq = 1188000000, ++ .fbdiv = 99, ++ .frac = 0, ++ .postdiv1 = 2, ++ .postdiv2 = 1, ++}; ++ + static struct ccu_pll dpu0_pll_clk = { + .common = { + .clkid = CLK_DPU0_PLL, +@@ -481,6 +609,8 @@ static struct ccu_pll dpu0_pll_clk = { + 0), + }, + .lock_sts_mask = BIT(8), ++ .cfgnum = 1, ++ .cfgs = &dpu_pll_cfg, + }; + + static const struct clk_hw *dpu0_pll_clk_parent[] = { +@@ -498,12 +628,22 @@ static struct ccu_pll dpu1_pll_clk = { + 0), + }, + .lock_sts_mask = BIT(9), ++ .cfgnum = 1, ++ .cfgs = &dpu_pll_cfg, + }; + + static const struct clk_hw *dpu1_pll_clk_parent[] = { + &dpu1_pll_clk.common.hw + }; + ++static const struct ccu_pll_cfg tee_pll_cfg = { ++ .freq = 792000000, ++ .fbdiv = 99, ++ .frac = 0, ++ .postdiv1 = 3, ++ .postdiv2 = 1, ++}; ++ + static struct ccu_pll tee_pll_clk = { + .common = { + .clkid = CLK_TEE_PLL, +@@ -515,6 +655,8 @@ static struct ccu_pll tee_pll_clk = { + CLK_IS_CRITICAL), + }, + .lock_sts_mask = BIT(10), ++ .cfgnum = 1, ++ .cfgs = &tee_pll_cfg, + }; + + static const struct clk_parent_data c910_i0_parents[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0130-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch b/SPECS/linux-lts-kmhv2/0130-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch deleted file mode 100644 index 0383823803..0000000000 --- a/SPECS/linux-lts-kmhv2/0130-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 1a7c7e7ba083e58a4ccc3b3fa45b63089ffb6cf2 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Tue, 20 Jan 2026 18:00:01 +0800 -Subject: [PATCH 130/467] UPSTREAM: riscv: dts: spacemit: Disable ETH PHY sleep - mode for OrangePi - -On the SpacemiT K1 platform, the MAC can't read statistics when the PHY -clock stops. Disable Link Down Power Saving Mode for the YT8531C PHY on -OrangePi R2S and RV2 boards to avoid reading statistics timeout logs. - -Signed-off-by: Chukun Pan -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260120100001.1285624-2-amadeus@jmu.edu.cn -Signed-off-by: Yixun Lan -(cherry picked from commit 5164e95565d3fd508ca8a95351323f5716dfb695) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts | 2 ++ - arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 2 ++ - 2 files changed, 4 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -index 58098c4a2aab..de75f6aac740 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -@@ -52,6 +52,7 @@ mdio-bus { - - rgmii0: phy@1 { - reg = <0x1>; -+ motorcomm,auto-sleep-disabled; - }; - }; - }; -@@ -75,6 +76,7 @@ mdio-bus { - - rgmii1: phy@1 { - reg = <0x1>; -+ motorcomm,auto-sleep-disabled; - }; - }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 41dc8e35e6eb..7b7331cb3c72 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -54,6 +54,7 @@ mdio-bus { - - rgmii0: phy@1 { - reg = <0x1>; -+ motorcomm,auto-sleep-disabled; - }; - }; - }; -@@ -77,6 +78,7 @@ mdio-bus { - - rgmii1: phy@1 { - reg = <0x1>; -+ motorcomm,auto-sleep-disabled; - }; - }; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch b/SPECS/linux-lts-kmhv2/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch new file mode 100644 index 0000000000..2518407886 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch @@ -0,0 +1,50 @@ +From 17338e1f386a810ea7bbe685d7cf3953dae6a51f Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:14 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Add macro to define + multiplexers with flags + +The new macro, TH_CCU_MUX_FLAGS, extends TH_CCU_MUX macro by adding two +parameters to specify clock flags and multiplexer flags. + +Reviewed-by: Drew Fustini +Signed-off-by: Yao Zi +Signed-off-by: Drew Fustini +(cherry picked from commit 5dbee3503771a36464e0b39a420475a727911c83) +Signed-off-by: Han Gao +--- + drivers/clk/thead/clk-th1520-ap.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c +index bf8e80c39a9e..79f001a047b2 100644 +--- a/drivers/clk/thead/clk-th1520-ap.c ++++ b/drivers/clk/thead/clk-th1520-ap.c +@@ -101,17 +101,22 @@ struct ccu_pll { + .flags = _flags, \ + } + +-#define TH_CCU_MUX(_name, _parents, _shift, _width) \ ++#define TH_CCU_MUX_FLAGS(_name, _parents, _shift, _width, _flags, \ ++ _mux_flags) \ + { \ + .mask = GENMASK(_width - 1, 0), \ + .shift = _shift, \ ++ .flags = _mux_flags, \ + .hw.init = CLK_HW_INIT_PARENTS_DATA( \ + _name, \ + _parents, \ + &clk_mux_ops, \ +- 0), \ ++ _flags), \ + } + ++#define TH_CCU_MUX(_name, _parents, _shift, _width) \ ++ TH_CCU_MUX_FLAGS(_name, _parents, _shift, _width, 0, 0) ++ + #define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _bit, _flags) \ + struct ccu_gate _struct = { \ + .clkid = _clkid, \ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0131-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch b/SPECS/linux-lts-kmhv2/0131-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch deleted file mode 100644 index 3201f9018c..0000000000 --- a/SPECS/linux-lts-kmhv2/0131-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 9a01370936360c3ee7d656548a3f36e7749b5924 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:10 +0000 -Subject: [PATCH 131/467] UPSTREAM: dt-bindings: clock: thead,th1520-clk-ap: - Add ID for C910 bus clock - -Add binding ID for C910 bus clock, which takes CLK_C910 as parent and is -essential for C910 cluster's operation. - -Acked-by: Conor Dooley -Signed-off-by: Yao Zi -Signed-off-by: Drew Fustini -(cherry picked from commit 5f352125f8a0bc906dff8419a2377903012d7f35) -Signed-off-by: Han Gao ---- - include/dt-bindings/clock/thead,th1520-clk-ap.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h -index 09a9aa7b3ab1..68b35cc61204 100644 ---- a/include/dt-bindings/clock/thead,th1520-clk-ap.h -+++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h -@@ -93,6 +93,7 @@ - #define CLK_SRAM3 83 - #define CLK_PLL_GMAC_100M 84 - #define CLK_UART_SCLK 85 -+#define CLK_C910_BUS 86 - - /* VO clocks */ - #define CLK_AXI4_VO_ACLK 0 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0132-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch b/SPECS/linux-lts-kmhv2/0132-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch deleted file mode 100644 index ef29245e54..0000000000 --- a/SPECS/linux-lts-kmhv2/0132-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch +++ /dev/null @@ -1,62 +0,0 @@ -From b5d944cf3ab3b20841cc2e504d8b66be87592c96 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:12 +0000 -Subject: [PATCH 132/467] UPSTREAM: clk: thead: th1520-ap: Add C910 bus clock - -This divider takes c910_clk as parent and is essential for the C910 -cluster to operate, thus is marked as CLK_IS_CRITICAL. - -Reviewed-by: Drew Fustini -Signed-off-by: Yao Zi -Signed-off-by: Drew Fustini -(cherry picked from commit b436f8a82aaa3bd54cb79b1219d94a99f7351d33) -Signed-off-by: Han Gao ---- - drivers/clk/thead/clk-th1520-ap.c | 17 ++++++++++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - -diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c -index d870f0c665f8..b820d47387bb 100644 ---- a/drivers/clk/thead/clk-th1520-ap.c -+++ b/drivers/clk/thead/clk-th1520-ap.c -@@ -539,6 +539,20 @@ static struct ccu_mux c910_clk = { - .mux = TH_CCU_MUX("c910", c910_parents, 0, 1), - }; - -+static struct ccu_div c910_bus_clk = { -+ .enable = BIT(7), -+ .div_en = BIT(11), -+ .div = TH_CCU_DIV_FLAGS(8, 3, 0), -+ .common = { -+ .clkid = CLK_C910_BUS, -+ .cfg0 = 0x100, -+ .hw.init = CLK_HW_INIT_HW("c910-bus", -+ &c910_clk.mux.hw, -+ &ccu_div_ops, -+ CLK_IS_CRITICAL), -+ }, -+}; -+ - static const struct clk_parent_data ahb2_cpusys_parents[] = { - { .hw = &gmac_pll_clk.common.hw }, - { .index = 0 } -@@ -1051,6 +1065,7 @@ static struct ccu_common *th1520_pll_clks[] = { - }; - - static struct ccu_common *th1520_div_clks[] = { -+ &c910_bus_clk.common, - &ahb2_cpusys_hclk.common, - &apb3_cpusys_pclk.common, - &axi4_cpusys2_aclk.common, -@@ -1194,7 +1209,7 @@ static const struct th1520_plat_data th1520_ap_platdata = { - .th1520_mux_clks = th1520_mux_clks, - .th1520_gate_clks = th1520_gate_clks, - -- .nr_clks = CLK_UART_SCLK + 1, -+ .nr_clks = CLK_C910_BUS + 1, - - .nr_pll_clks = ARRAY_SIZE(th1520_pll_clks), - .nr_div_clks = ARRAY_SIZE(th1520_div_clks), --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch b/SPECS/linux-lts-kmhv2/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch new file mode 100644 index 0000000000..5e088a3818 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch @@ -0,0 +1,240 @@ +From fc08e30c489223facf41c8c180c1d3685bad9ee9 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:15 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Support CPU frequency + scaling + +On TH1520 SoC, c910_clk feeds the CPU cluster. It could be glitchlessly +reparented to one of the two PLLs: either to cpu_pll0 indirectly through +c910_i0_clk, or to cpu_pll1 directly. + +To achieve glitchless rate change, customized clock operations are +implemented for c910_clk: on rate change, the PLL not currently in use +is configured to the requested rate first, then c910_clk reparents to +it. + +Additionally, c910_bus_clk, which in turn takes c910_clk as parent, +has a frequency limit of 750MHz. A clock notifier is registered on +c910_clk to adjust c910_bus_clk on c910_clk rate change. + +Reviewed-by: Drew Fustini +Signed-off-by: Yao Zi +Signed-off-by: Drew Fustini +(cherry picked from commit baf4fc7c03bd0f68c768cfe27829674bd060c6b4) +Signed-off-by: Han Gao +--- + drivers/clk/thead/clk-th1520-ap.c | 148 +++++++++++++++++++++++++++++- + 1 file changed, 146 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c +index 79f001a047b2..3a6847f1c950 100644 +--- a/drivers/clk/thead/clk-th1520-ap.c ++++ b/drivers/clk/thead/clk-th1520-ap.c +@@ -7,9 +7,11 @@ + + #include + #include ++#include + #include + #include + #include ++#include + #include + #include + #include +@@ -34,6 +36,9 @@ + #define TH1520_PLL_LOCK_TIMEOUT_US 44 + #define TH1520_PLL_STABLE_DELAY_US 30 + ++/* c910_bus_clk must be kept below 750MHz for stability */ ++#define TH1520_C910_BUS_MAX_RATE (750 * 1000 * 1000) ++ + struct ccu_internal { + u8 shift; + u8 width; +@@ -472,6 +477,72 @@ static const struct clk_ops clk_pll_ops = { + .set_rate = ccu_pll_set_rate, + }; + ++/* ++ * c910_clk could be reparented glitchlessly for DVFS. There are two parents, ++ * - c910_i0_clk, derived from cpu_pll0_clk or osc_24m. ++ * - cpu_pll1_clk, which provides the exact same set of rates as cpu_pll0_clk. ++ * ++ * During rate setting, always forward the request to the unused parent, and ++ * then switch c910_clk to it to avoid glitch. ++ */ ++static u8 c910_clk_get_parent(struct clk_hw *hw) ++{ ++ return clk_mux_ops.get_parent(hw); ++} ++ ++static int c910_clk_set_parent(struct clk_hw *hw, u8 index) ++{ ++ return clk_mux_ops.set_parent(hw, index); ++} ++ ++static unsigned long c910_clk_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ return parent_rate; ++} ++ ++static int c910_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ u8 alt_parent_index = !c910_clk_get_parent(hw); ++ struct clk_hw *alt_parent; ++ ++ alt_parent = clk_hw_get_parent_by_index(hw, alt_parent_index); ++ ++ req->rate = clk_hw_round_rate(alt_parent, req->rate); ++ req->best_parent_hw = alt_parent; ++ req->best_parent_rate = req->rate; ++ ++ return 0; ++} ++ ++static int c910_clk_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ return -EOPNOTSUPP; ++} ++ ++static int c910_clk_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate, u8 index) ++{ ++ struct clk_hw *parent = clk_hw_get_parent_by_index(hw, index); ++ ++ clk_set_rate(parent->clk, parent_rate); ++ ++ c910_clk_set_parent(hw, index); ++ ++ return 0; ++} ++ ++static const struct clk_ops c910_clk_ops = { ++ .get_parent = c910_clk_get_parent, ++ .set_parent = c910_clk_set_parent, ++ .recalc_rate = c910_clk_recalc_rate, ++ .determine_rate = c910_clk_determine_rate, ++ .set_rate = c910_clk_set_rate, ++ .set_rate_and_parent = c910_clk_set_rate_and_parent, ++}; ++ + static const struct clk_parent_data osc_24m_clk[] = { + { .index = 0 } + }; +@@ -672,7 +743,8 @@ static const struct clk_parent_data c910_i0_parents[] = { + static struct ccu_mux c910_i0_clk = { + .clkid = CLK_C910_I0, + .reg = 0x100, +- .mux = TH_CCU_MUX("c910-i0", c910_i0_parents, 1, 1), ++ .mux = TH_CCU_MUX_FLAGS("c910-i0", c910_i0_parents, 1, 1, ++ CLK_SET_RATE_PARENT, CLK_MUX_ROUND_CLOSEST), + }; + + static const struct clk_parent_data c910_parents[] = { +@@ -683,7 +755,14 @@ static const struct clk_parent_data c910_parents[] = { + static struct ccu_mux c910_clk = { + .clkid = CLK_C910, + .reg = 0x100, +- .mux = TH_CCU_MUX("c910", c910_parents, 0, 1), ++ .mux = { ++ .mask = BIT(0), ++ .shift = 0, ++ .hw.init = CLK_HW_INIT_PARENTS_DATA("c910", ++ c910_parents, ++ &c910_clk_ops, ++ CLK_SET_RATE_PARENT), ++ }, + }; + + static struct ccu_div c910_bus_clk = { +@@ -1372,11 +1451,69 @@ static const struct th1520_plat_data th1520_vo_platdata = { + .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks), + }; + ++/* ++ * Maintain clock rate of c910_bus_clk below TH1520_C910_BUS_MAX_RATE (750MHz) ++ * when its parent, c910_clk, changes the rate. ++ * ++ * Additionally, TRM is unclear about c910_bus_clk behavior when the divisor is ++ * set below 2, thus we should ensure the new divisor stays in (2, MAXDIVISOR). ++ */ ++static unsigned long c910_bus_clk_divisor(struct ccu_div *cd, ++ unsigned long parent_rate) ++{ ++ return clamp(DIV_ROUND_UP(parent_rate, TH1520_C910_BUS_MAX_RATE), ++ 2U, 1U << cd->div.width); ++} ++ ++static int c910_clk_notifier_cb(struct notifier_block *nb, ++ unsigned long action, void *data) ++{ ++ struct clk_notifier_data *cnd = data; ++ unsigned long new_divisor, ref_rate; ++ ++ if (action != PRE_RATE_CHANGE && action != POST_RATE_CHANGE) ++ return NOTIFY_DONE; ++ ++ new_divisor = c910_bus_clk_divisor(&c910_bus_clk, cnd->new_rate); ++ ++ if (cnd->new_rate > cnd->old_rate) { ++ /* ++ * Scaling up. Adjust c910_bus_clk divisor ++ * - before c910_clk rate change to ensure the constraints ++ * aren't broken after scaling to higher rates, ++ * - after c910_clk rate change to keep c910_bus_clk as high as ++ * possible ++ */ ++ ref_rate = action == PRE_RATE_CHANGE ? ++ cnd->old_rate : cnd->new_rate; ++ clk_set_rate(c910_bus_clk.common.hw.clk, ++ ref_rate / new_divisor); ++ } else if (cnd->new_rate < cnd->old_rate && ++ action == POST_RATE_CHANGE) { ++ /* ++ * Scaling down. Adjust c910_bus_clk divisor only after ++ * c910_clk rate change to keep c910_bus_clk as high as ++ * possible, Scaling down never breaks the constraints. ++ */ ++ clk_set_rate(c910_bus_clk.common.hw.clk, ++ cnd->new_rate / new_divisor); ++ } else { ++ return NOTIFY_DONE; ++ } ++ ++ return NOTIFY_OK; ++} ++ ++static struct notifier_block c910_clk_notifier = { ++ .notifier_call = c910_clk_notifier_cb, ++}; ++ + static int th1520_clk_probe(struct platform_device *pdev) + { + const struct th1520_plat_data *plat_data; + struct device *dev = &pdev->dev; + struct clk_hw_onecell_data *priv; ++ struct clk *notifier_clk; + + struct regmap *map; + void __iomem *base; +@@ -1463,6 +1600,13 @@ static int th1520_clk_probe(struct platform_device *pdev) + ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw); + if (ret) + return ret; ++ ++ notifier_clk = devm_clk_hw_get_clk(dev, &c910_clk.mux.hw, ++ "dvfs"); ++ ret = devm_clk_notifier_register(dev, notifier_clk, ++ &c910_clk_notifier); ++ if (ret) ++ return ret; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0133-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch b/SPECS/linux-lts-kmhv2/0133-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch deleted file mode 100644 index af622a6e0c..0000000000 --- a/SPECS/linux-lts-kmhv2/0133-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch +++ /dev/null @@ -1,275 +0,0 @@ -From 3107f6db39bfccf7730194c3fb729357945bf743 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:13 +0000 -Subject: [PATCH 133/467] UPSTREAM: clk: thead: th1520-ap: Support setting PLL - rates - -TH1520 ships several PLLs that could operate in either integer or -fractional mode. However, the TRM only lists a few configuration whose -stability is considered guaranteed. - -Add a table-lookup rate determination logic to support PLL rate setting, -and fill up frequency-configuration tables for AP-subsystem PLLs. - -Reviewed-by: Drew Fustini -Signed-off-by: Yao Zi -Signed-off-by: Drew Fustini -(cherry picked from commit 238cc6316a885765fd52a6dc65b9ca4e47647b1e) -Signed-off-by: Han Gao ---- - drivers/clk/thead/clk-th1520-ap.c | 142 ++++++++++++++++++++++++++++++ - 1 file changed, 142 insertions(+) - -diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c -index b820d47387bb..bf8e80c39a9e 100644 ---- a/drivers/clk/thead/clk-th1520-ap.c -+++ b/drivers/clk/thead/clk-th1520-ap.c -@@ -22,6 +22,7 @@ - #define TH1520_PLL_REFDIV GENMASK(5, 0) - #define TH1520_PLL_BYPASS BIT(30) - #define TH1520_PLL_VCO_RST BIT(29) -+#define TH1520_PLL_DACPD BIT(25) - #define TH1520_PLL_DSMPD BIT(24) - #define TH1520_PLL_FRAC GENMASK(23, 0) - #define TH1520_PLL_FRAC_BITS 24 -@@ -72,9 +73,19 @@ struct ccu_div { - struct ccu_common common; - }; - -+struct ccu_pll_cfg { -+ unsigned long freq; -+ u32 fbdiv; -+ u32 frac; -+ u32 postdiv1; -+ u32 postdiv2; -+}; -+ - struct ccu_pll { - struct ccu_common common; - u32 lock_sts_mask; -+ int cfgnum; -+ const struct ccu_pll_cfg *cfgs; - }; - - #define TH_CCU_ARG(_shift, _width) \ -@@ -391,17 +402,102 @@ static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw, - return rate; - } - -+static const struct ccu_pll_cfg *ccu_pll_lookup_best_cfg(struct ccu_pll *pll, -+ unsigned long rate) -+{ -+ unsigned long best_delta = ULONG_MAX; -+ const struct ccu_pll_cfg *best_cfg; -+ int i; -+ -+ for (i = 0; i < pll->cfgnum; i++) { -+ const struct ccu_pll_cfg *cfg = &pll->cfgs[i]; -+ unsigned long delta; -+ -+ delta = abs_diff(cfg->freq, rate); -+ if (delta < best_delta) { -+ best_delta = delta; -+ best_cfg = cfg; -+ } -+ } -+ -+ return best_cfg; -+} -+ -+static int ccu_pll_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ -+ req->rate = ccu_pll_lookup_best_cfg(pll, req->rate)->freq; -+ -+ return 0; -+} -+ -+static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ const struct ccu_pll_cfg *cfg; -+ -+ cfg = ccu_pll_lookup_best_cfg(pll, rate); -+ -+ ccu_pll_disable(hw); -+ -+ regmap_write(pll->common.map, pll->common.cfg0, -+ FIELD_PREP(TH1520_PLL_REFDIV, 1) | -+ FIELD_PREP(TH1520_PLL_FBDIV, cfg->fbdiv) | -+ FIELD_PREP(TH1520_PLL_POSTDIV1, cfg->postdiv1) | -+ FIELD_PREP(TH1520_PLL_POSTDIV2, cfg->postdiv2)); -+ -+ regmap_update_bits(pll->common.map, pll->common.cfg1, -+ TH1520_PLL_DACPD | TH1520_PLL_DSMPD | -+ TH1520_PLL_FRAC, -+ cfg->frac ? cfg->frac : -+ TH1520_PLL_DACPD | TH1520_PLL_DSMPD); -+ -+ return ccu_pll_enable(hw); -+} -+ - static const struct clk_ops clk_pll_ops = { - .disable = ccu_pll_disable, - .enable = ccu_pll_enable, - .is_enabled = ccu_pll_is_enabled, - .recalc_rate = ccu_pll_recalc_rate, -+ .determine_rate = ccu_pll_determine_rate, -+ .set_rate = ccu_pll_set_rate, - }; - - static const struct clk_parent_data osc_24m_clk[] = { - { .index = 0 } - }; - -+static const struct ccu_pll_cfg cpu_pll_cfgs[] = { -+ { 125000000, 125, 0, 6, 4 }, -+ { 200000000, 125, 0, 5, 3 }, -+ { 300000000, 125, 0, 5, 2 }, -+ { 400000000, 100, 0, 3, 2 }, -+ { 500000000, 125, 0, 6, 1 }, -+ { 600000000, 125, 0, 5, 1 }, -+ { 702000000, 117, 0, 4, 1 }, -+ { 800000000, 100, 0, 3, 1 }, -+ { 900000000, 75, 0, 2, 1 }, -+ { 1000000000, 125, 0, 3, 1 }, -+ { 1104000000, 92, 0, 2, 1 }, -+ { 1200000000, 100, 0, 2, 1 }, -+ { 1296000000, 108, 0, 2, 1 }, -+ { 1404000000, 117, 0, 2, 1 }, -+ { 1500000000, 125, 0, 2, 1 }, -+ { 1608000000, 67, 0, 1, 1 }, -+ { 1704000000, 71, 0, 1, 1 }, -+ { 1800000000, 75, 0, 1, 1 }, -+ { 1896000000, 79, 0, 1, 1 }, -+ { 1992000000, 83, 0, 1, 1 }, -+ { 2112000000, 88, 0, 1, 1 }, -+ { 2208000000, 92, 0, 1, 1 }, -+ { 2304000000, 96, 0, 1, 1 }, -+ { 2400000000, 100, 0, 1, 1 }, -+}; -+ - static struct ccu_pll cpu_pll0_clk = { - .common = { - .clkid = CLK_CPU_PLL0, -@@ -413,6 +509,8 @@ static struct ccu_pll cpu_pll0_clk = { - CLK_IS_CRITICAL), - }, - .lock_sts_mask = BIT(1), -+ .cfgnum = ARRAY_SIZE(cpu_pll_cfgs), -+ .cfgs = cpu_pll_cfgs, - }; - - static struct ccu_pll cpu_pll1_clk = { -@@ -426,6 +524,16 @@ static struct ccu_pll cpu_pll1_clk = { - CLK_IS_CRITICAL), - }, - .lock_sts_mask = BIT(4), -+ .cfgnum = ARRAY_SIZE(cpu_pll_cfgs), -+ .cfgs = cpu_pll_cfgs, -+}; -+ -+static const struct ccu_pll_cfg gmac_pll_cfg = { -+ .freq = 1000000000, -+ .fbdiv = 125, -+ .frac = 0, -+ .postdiv1 = 3, -+ .postdiv2 = 1, - }; - - static struct ccu_pll gmac_pll_clk = { -@@ -439,6 +547,8 @@ static struct ccu_pll gmac_pll_clk = { - CLK_IS_CRITICAL), - }, - .lock_sts_mask = BIT(3), -+ .cfgnum = 1, -+ .cfgs = &gmac_pll_cfg, - }; - - static const struct clk_hw *gmac_pll_clk_parent[] = { -@@ -449,6 +559,14 @@ static const struct clk_parent_data gmac_pll_clk_pd[] = { - { .hw = &gmac_pll_clk.common.hw } - }; - -+static const struct ccu_pll_cfg video_pll_cfg = { -+ .freq = 792000000, -+ .fbdiv = 99, -+ .frac = 0, -+ .postdiv1 = 3, -+ .postdiv2 = 1, -+}; -+ - static struct ccu_pll video_pll_clk = { - .common = { - .clkid = CLK_VIDEO_PLL, -@@ -460,6 +578,8 @@ static struct ccu_pll video_pll_clk = { - CLK_IS_CRITICAL), - }, - .lock_sts_mask = BIT(7), -+ .cfgnum = 1, -+ .cfgs = &video_pll_cfg, - }; - - static const struct clk_hw *video_pll_clk_parent[] = { -@@ -470,6 +590,14 @@ static const struct clk_parent_data video_pll_clk_pd[] = { - { .hw = &video_pll_clk.common.hw } - }; - -+static const struct ccu_pll_cfg dpu_pll_cfg = { -+ .freq = 1188000000, -+ .fbdiv = 99, -+ .frac = 0, -+ .postdiv1 = 2, -+ .postdiv2 = 1, -+}; -+ - static struct ccu_pll dpu0_pll_clk = { - .common = { - .clkid = CLK_DPU0_PLL, -@@ -481,6 +609,8 @@ static struct ccu_pll dpu0_pll_clk = { - 0), - }, - .lock_sts_mask = BIT(8), -+ .cfgnum = 1, -+ .cfgs = &dpu_pll_cfg, - }; - - static const struct clk_hw *dpu0_pll_clk_parent[] = { -@@ -498,12 +628,22 @@ static struct ccu_pll dpu1_pll_clk = { - 0), - }, - .lock_sts_mask = BIT(9), -+ .cfgnum = 1, -+ .cfgs = &dpu_pll_cfg, - }; - - static const struct clk_hw *dpu1_pll_clk_parent[] = { - &dpu1_pll_clk.common.hw - }; - -+static const struct ccu_pll_cfg tee_pll_cfg = { -+ .freq = 792000000, -+ .fbdiv = 99, -+ .frac = 0, -+ .postdiv1 = 3, -+ .postdiv2 = 1, -+}; -+ - static struct ccu_pll tee_pll_clk = { - .common = { - .clkid = CLK_TEE_PLL, -@@ -515,6 +655,8 @@ static struct ccu_pll tee_pll_clk = { - CLK_IS_CRITICAL), - }, - .lock_sts_mask = BIT(10), -+ .cfgnum = 1, -+ .cfgs = &tee_pll_cfg, - }; - - static const struct clk_parent_data c910_i0_parents[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch b/SPECS/linux-lts-kmhv2/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch new file mode 100644 index 0000000000..ee84bea6d5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch @@ -0,0 +1,33 @@ +From 216580fd5ff0f2f9d1b045a0eebd53199b169c09 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sun, 1 Feb 2026 18:00:01 +0800 +Subject: [RUYI PATCH] UPSTREAM: net: spacemit: display phy driver information + +Print the PHY driver used and interrupt status after connection. + +Signed-off-by: Chukun Pan +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/20260201100001.33102-1-amadeus@jmu.edu.cn +Signed-off-by: Jakub Kicinski +(cherry picked from commit fd102acfd362de60a941d24f0836278d839b9391) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/spacemit/k1_emac.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c +index d64ca7bbda9e..52c0c00a471f 100644 +--- a/drivers/net/ethernet/spacemit/k1_emac.c ++++ b/drivers/net/ethernet/spacemit/k1_emac.c +@@ -1757,6 +1757,8 @@ static int emac_phy_connect(struct net_device *ndev) + + emac_update_delay_line(priv); + ++ phy_attached_info(phydev); ++ + err_node_put: + of_node_put(np); + return ret; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0134-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch b/SPECS/linux-lts-kmhv2/0134-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch deleted file mode 100644 index bb158844fe..0000000000 --- a/SPECS/linux-lts-kmhv2/0134-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 94cd6930cd62b37d3a5be5f99c38418227dadc53 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:14 +0000 -Subject: [PATCH 134/467] UPSTREAM: clk: thead: th1520-ap: Add macro to define - multiplexers with flags - -The new macro, TH_CCU_MUX_FLAGS, extends TH_CCU_MUX macro by adding two -parameters to specify clock flags and multiplexer flags. - -Reviewed-by: Drew Fustini -Signed-off-by: Yao Zi -Signed-off-by: Drew Fustini -(cherry picked from commit 5dbee3503771a36464e0b39a420475a727911c83) -Signed-off-by: Han Gao ---- - drivers/clk/thead/clk-th1520-ap.c | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c -index bf8e80c39a9e..79f001a047b2 100644 ---- a/drivers/clk/thead/clk-th1520-ap.c -+++ b/drivers/clk/thead/clk-th1520-ap.c -@@ -101,17 +101,22 @@ struct ccu_pll { - .flags = _flags, \ - } - --#define TH_CCU_MUX(_name, _parents, _shift, _width) \ -+#define TH_CCU_MUX_FLAGS(_name, _parents, _shift, _width, _flags, \ -+ _mux_flags) \ - { \ - .mask = GENMASK(_width - 1, 0), \ - .shift = _shift, \ -+ .flags = _mux_flags, \ - .hw.init = CLK_HW_INIT_PARENTS_DATA( \ - _name, \ - _parents, \ - &clk_mux_ops, \ -- 0), \ -+ _flags), \ - } - -+#define TH_CCU_MUX(_name, _parents, _shift, _width) \ -+ TH_CCU_MUX_FLAGS(_name, _parents, _shift, _width, 0, 0) -+ - #define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _bit, _flags) \ - struct ccu_gate _struct = { \ - .clkid = _clkid, \ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch b/SPECS/linux-lts-kmhv2/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch new file mode 100644 index 0000000000..71279bcd12 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch @@ -0,0 +1,73 @@ +From a000c3124b2434f1d7da679574181a5b8295c9b8 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 27 Jan 2026 10:58:49 +0800 +Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit-k1: Use PDR for pin direction, + not SDR/CDR + +On the SpacemiT GPIO controller, the direction control register PDR is +readable and writable [1]. Therefore, implement direction control by +using PDR as dirout, and don't mark it as unreadable. + +The original implementation, using SDR as dirout and CDR as dirin, is +not actually a supported configuration by gpio-mmio. The hardware +supports changing the direction of some pins atomically by writing a +value with the corresponding bits set to SDR (set as output) or to CDR +(set as input). However, gpio-mmio does not actually handle this. + +Using only PDR as dirout to match the expectations of gpio-mmio. This +also allows us to avoid clobbering potentially important GPIO direction +configurations set by pre-Linux boot stages. + +Found while trying to add PCIe support to OrangePi RV2, where the +regulator (controlled by GPIO 116) turns off on boot while some other +GPIO pin in the same bank is touched, which is not desirable. + +Link: https://developer.spacemit.com/documentation?token=Rn9Kw3iFHirAMgkIpTAcV2Arnkf#18.4-gpio # [1] +Fixes: d00553240ef8 ("gpio: spacemit: add support for K1 SoC") +Signed-off-by: Vivian Wang +Reviewed-by: Troy Mitchell +Link: https://patch.msgid.link/20260127-gpio-spacemit-k1-pdr-v1-1-bb868a517dbc@iscas.ac.cn +Signed-off-by: Bartosz Golaszewski +(cherry picked from commit aa7e37fd770bafaaf856ab77735296955b93e377) +Signed-off-by: Han Gao +--- + drivers/gpio/gpio-spacemit-k1.c | 9 +++------ + 1 file changed, 3 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c +index 8f570a1a4894..dbd2e81094b9 100644 +--- a/drivers/gpio/gpio-spacemit-k1.c ++++ b/drivers/gpio/gpio-spacemit-k1.c +@@ -199,7 +199,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + struct gpio_chip *gc = &gb->chip.gc; + struct device *dev = sg->dev; + struct gpio_irq_chip *girq; +- void __iomem *dat, *set, *clr, *dirin, *dirout; ++ void __iomem *dat, *set, *clr, *dirout; + int ret; + + gb->base = regs + sg->data->bank_offsets[index]; +@@ -208,8 +208,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + dat = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPLR]; + set = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPSR]; + clr = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPCR]; +- dirin = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GCDR]; +- dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GSDR]; ++ dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPDR]; + + config = (struct gpio_generic_chip_config) { + .dev = dev, +@@ -218,9 +217,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + .set = set, + .clr = clr, + .dirout = dirout, +- .dirin = dirin, +- .flags = GPIO_GENERIC_UNREADABLE_REG_SET | +- GPIO_GENERIC_UNREADABLE_REG_DIR, ++ .flags = GPIO_GENERIC_UNREADABLE_REG_SET, + }; + + /* This registers 32 GPIO lines per bank */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0135-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch b/SPECS/linux-lts-kmhv2/0135-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch deleted file mode 100644 index 4e6527f2d0..0000000000 --- a/SPECS/linux-lts-kmhv2/0135-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch +++ /dev/null @@ -1,240 +0,0 @@ -From 67a3e5cab266ebbe091c06fb4f79f60e0d87455f Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:15 +0000 -Subject: [PATCH 135/467] UPSTREAM: clk: thead: th1520-ap: Support CPU - frequency scaling - -On TH1520 SoC, c910_clk feeds the CPU cluster. It could be glitchlessly -reparented to one of the two PLLs: either to cpu_pll0 indirectly through -c910_i0_clk, or to cpu_pll1 directly. - -To achieve glitchless rate change, customized clock operations are -implemented for c910_clk: on rate change, the PLL not currently in use -is configured to the requested rate first, then c910_clk reparents to -it. - -Additionally, c910_bus_clk, which in turn takes c910_clk as parent, -has a frequency limit of 750MHz. A clock notifier is registered on -c910_clk to adjust c910_bus_clk on c910_clk rate change. - -Reviewed-by: Drew Fustini -Signed-off-by: Yao Zi -Signed-off-by: Drew Fustini -(cherry picked from commit baf4fc7c03bd0f68c768cfe27829674bd060c6b4) -Signed-off-by: Han Gao ---- - drivers/clk/thead/clk-th1520-ap.c | 148 +++++++++++++++++++++++++++++- - 1 file changed, 146 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c -index 79f001a047b2..3a6847f1c950 100644 ---- a/drivers/clk/thead/clk-th1520-ap.c -+++ b/drivers/clk/thead/clk-th1520-ap.c -@@ -7,9 +7,11 @@ - - #include - #include -+#include - #include - #include - #include -+#include - #include - #include - #include -@@ -34,6 +36,9 @@ - #define TH1520_PLL_LOCK_TIMEOUT_US 44 - #define TH1520_PLL_STABLE_DELAY_US 30 - -+/* c910_bus_clk must be kept below 750MHz for stability */ -+#define TH1520_C910_BUS_MAX_RATE (750 * 1000 * 1000) -+ - struct ccu_internal { - u8 shift; - u8 width; -@@ -472,6 +477,72 @@ static const struct clk_ops clk_pll_ops = { - .set_rate = ccu_pll_set_rate, - }; - -+/* -+ * c910_clk could be reparented glitchlessly for DVFS. There are two parents, -+ * - c910_i0_clk, derived from cpu_pll0_clk or osc_24m. -+ * - cpu_pll1_clk, which provides the exact same set of rates as cpu_pll0_clk. -+ * -+ * During rate setting, always forward the request to the unused parent, and -+ * then switch c910_clk to it to avoid glitch. -+ */ -+static u8 c910_clk_get_parent(struct clk_hw *hw) -+{ -+ return clk_mux_ops.get_parent(hw); -+} -+ -+static int c910_clk_set_parent(struct clk_hw *hw, u8 index) -+{ -+ return clk_mux_ops.set_parent(hw, index); -+} -+ -+static unsigned long c910_clk_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ return parent_rate; -+} -+ -+static int c910_clk_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ u8 alt_parent_index = !c910_clk_get_parent(hw); -+ struct clk_hw *alt_parent; -+ -+ alt_parent = clk_hw_get_parent_by_index(hw, alt_parent_index); -+ -+ req->rate = clk_hw_round_rate(alt_parent, req->rate); -+ req->best_parent_hw = alt_parent; -+ req->best_parent_rate = req->rate; -+ -+ return 0; -+} -+ -+static int c910_clk_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ return -EOPNOTSUPP; -+} -+ -+static int c910_clk_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate, u8 index) -+{ -+ struct clk_hw *parent = clk_hw_get_parent_by_index(hw, index); -+ -+ clk_set_rate(parent->clk, parent_rate); -+ -+ c910_clk_set_parent(hw, index); -+ -+ return 0; -+} -+ -+static const struct clk_ops c910_clk_ops = { -+ .get_parent = c910_clk_get_parent, -+ .set_parent = c910_clk_set_parent, -+ .recalc_rate = c910_clk_recalc_rate, -+ .determine_rate = c910_clk_determine_rate, -+ .set_rate = c910_clk_set_rate, -+ .set_rate_and_parent = c910_clk_set_rate_and_parent, -+}; -+ - static const struct clk_parent_data osc_24m_clk[] = { - { .index = 0 } - }; -@@ -672,7 +743,8 @@ static const struct clk_parent_data c910_i0_parents[] = { - static struct ccu_mux c910_i0_clk = { - .clkid = CLK_C910_I0, - .reg = 0x100, -- .mux = TH_CCU_MUX("c910-i0", c910_i0_parents, 1, 1), -+ .mux = TH_CCU_MUX_FLAGS("c910-i0", c910_i0_parents, 1, 1, -+ CLK_SET_RATE_PARENT, CLK_MUX_ROUND_CLOSEST), - }; - - static const struct clk_parent_data c910_parents[] = { -@@ -683,7 +755,14 @@ static const struct clk_parent_data c910_parents[] = { - static struct ccu_mux c910_clk = { - .clkid = CLK_C910, - .reg = 0x100, -- .mux = TH_CCU_MUX("c910", c910_parents, 0, 1), -+ .mux = { -+ .mask = BIT(0), -+ .shift = 0, -+ .hw.init = CLK_HW_INIT_PARENTS_DATA("c910", -+ c910_parents, -+ &c910_clk_ops, -+ CLK_SET_RATE_PARENT), -+ }, - }; - - static struct ccu_div c910_bus_clk = { -@@ -1372,11 +1451,69 @@ static const struct th1520_plat_data th1520_vo_platdata = { - .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks), - }; - -+/* -+ * Maintain clock rate of c910_bus_clk below TH1520_C910_BUS_MAX_RATE (750MHz) -+ * when its parent, c910_clk, changes the rate. -+ * -+ * Additionally, TRM is unclear about c910_bus_clk behavior when the divisor is -+ * set below 2, thus we should ensure the new divisor stays in (2, MAXDIVISOR). -+ */ -+static unsigned long c910_bus_clk_divisor(struct ccu_div *cd, -+ unsigned long parent_rate) -+{ -+ return clamp(DIV_ROUND_UP(parent_rate, TH1520_C910_BUS_MAX_RATE), -+ 2U, 1U << cd->div.width); -+} -+ -+static int c910_clk_notifier_cb(struct notifier_block *nb, -+ unsigned long action, void *data) -+{ -+ struct clk_notifier_data *cnd = data; -+ unsigned long new_divisor, ref_rate; -+ -+ if (action != PRE_RATE_CHANGE && action != POST_RATE_CHANGE) -+ return NOTIFY_DONE; -+ -+ new_divisor = c910_bus_clk_divisor(&c910_bus_clk, cnd->new_rate); -+ -+ if (cnd->new_rate > cnd->old_rate) { -+ /* -+ * Scaling up. Adjust c910_bus_clk divisor -+ * - before c910_clk rate change to ensure the constraints -+ * aren't broken after scaling to higher rates, -+ * - after c910_clk rate change to keep c910_bus_clk as high as -+ * possible -+ */ -+ ref_rate = action == PRE_RATE_CHANGE ? -+ cnd->old_rate : cnd->new_rate; -+ clk_set_rate(c910_bus_clk.common.hw.clk, -+ ref_rate / new_divisor); -+ } else if (cnd->new_rate < cnd->old_rate && -+ action == POST_RATE_CHANGE) { -+ /* -+ * Scaling down. Adjust c910_bus_clk divisor only after -+ * c910_clk rate change to keep c910_bus_clk as high as -+ * possible, Scaling down never breaks the constraints. -+ */ -+ clk_set_rate(c910_bus_clk.common.hw.clk, -+ cnd->new_rate / new_divisor); -+ } else { -+ return NOTIFY_DONE; -+ } -+ -+ return NOTIFY_OK; -+} -+ -+static struct notifier_block c910_clk_notifier = { -+ .notifier_call = c910_clk_notifier_cb, -+}; -+ - static int th1520_clk_probe(struct platform_device *pdev) - { - const struct th1520_plat_data *plat_data; - struct device *dev = &pdev->dev; - struct clk_hw_onecell_data *priv; -+ struct clk *notifier_clk; - - struct regmap *map; - void __iomem *base; -@@ -1463,6 +1600,13 @@ static int th1520_clk_probe(struct platform_device *pdev) - ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw); - if (ret) - return ret; -+ -+ notifier_clk = devm_clk_hw_get_clk(dev, &c910_clk.mux.hw, -+ "dvfs"); -+ ret = devm_clk_notifier_register(dev, notifier_clk, -+ &c910_clk_notifier); -+ if (ret) -+ return ret; - } - - ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch b/SPECS/linux-lts-kmhv2/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch new file mode 100644 index 0000000000..315761b942 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch @@ -0,0 +1,37 @@ +From 9a9a68a7eddae8077db583fd6db0e31a7e837eab Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Fri, 26 Dec 2025 11:32:27 -0600 +Subject: [RUYI PATCH] UPSTREAM: phy: Kconfig: spacemit: add COMMON_CLK + dependency + +The SpacemiT PCIe PHY driver depends on the common clock framework. +Not specifying that led to a failure when doing a COMPILE_TEST build +for the SPARC architecture. + +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202512251903.sTVZgg6c-lkp@intel.com/ +Signed-off-by: Alex Elder +Reviewed-by: Javier Martinez Canillas +Link: https://patch.msgid.link/20251226173228.2020411-1-elder@riscstar.com +Signed-off-by: Vinod Koul +(cherry picked from commit 8df20813eb01fe29b4507fd470d73675bda3e1dd) +Signed-off-by: Han Gao +--- + drivers/phy/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index 95ee47f0fbc7..88ea9af445b1 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -104,6 +104,7 @@ config PHY_NXP_PTN3222 + config PHY_SPACEMIT_K1_PCIE + tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC" + depends on ARCH_SPACEMIT || COMPILE_TEST ++ depends on COMMON_CLK + depends on HAS_IOMEM + depends on OF + select GENERIC_PHY +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch b/SPECS/linux-lts-kmhv2/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch new file mode 100644 index 0000000000..661b7fce58 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch @@ -0,0 +1,34 @@ +From 13956aef479172118fb402bab2ecea2f30a4a744 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 25 Dec 2025 15:46:32 +0800 +Subject: [RUYI PATCH] UPSTREAM: mfd: Kconfig: Default MFD_SPACEMIT_P1 to 'm' + if ARCH_SPACEMIT + +The default value of the P1 sub-device depends on the value +of P1, so P1 should have a default value here. + +Signed-off-by: Troy Mitchell +Acked-by: Alex Elder +Link: https://patch.msgid.link/20251225-p1-kconfig-fix-v4-2-44b6728117c1@linux.spacemit.com +Signed-off-by: Lee Jones +(cherry picked from commit 9d1e2d5f2b24a24b32aca451d6a7feb081ad5a62) +Signed-off-by: Han Gao +--- + drivers/mfd/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig +index b0264352790e..8295e7871d70 100644 +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -1270,6 +1270,7 @@ config MFD_SPACEMIT_P1 + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on I2C + select MFD_SIMPLE_MFD_I2C ++ default m if ARCH_SPACEMIT + help + This option supports the I2C-based SpacemiT P1 PMIC, which + contains regulators, a power switch, GPIOs, an RTC, and more. +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0136-UPSTREAM-net-spacemit-display-phy-driver-information.patch b/SPECS/linux-lts-kmhv2/0136-UPSTREAM-net-spacemit-display-phy-driver-information.patch deleted file mode 100644 index 756971bff5..0000000000 --- a/SPECS/linux-lts-kmhv2/0136-UPSTREAM-net-spacemit-display-phy-driver-information.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 20d3fa165cbcd3a84876fcbfe8f012363c75cfa0 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sun, 1 Feb 2026 18:00:01 +0800 -Subject: [PATCH 136/467] UPSTREAM: net: spacemit: display phy driver - information - -Print the PHY driver used and interrupt status after connection. - -Signed-off-by: Chukun Pan -Reviewed-by: Andrew Lunn -Link: https://patch.msgid.link/20260201100001.33102-1-amadeus@jmu.edu.cn -Signed-off-by: Jakub Kicinski -(cherry picked from commit fd102acfd362de60a941d24f0836278d839b9391) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/spacemit/k1_emac.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c -index d64ca7bbda9e..52c0c00a471f 100644 ---- a/drivers/net/ethernet/spacemit/k1_emac.c -+++ b/drivers/net/ethernet/spacemit/k1_emac.c -@@ -1757,6 +1757,8 @@ static int emac_phy_connect(struct net_device *ndev) - - emac_update_delay_line(priv); - -+ phy_attached_info(phydev); -+ - err_node_put: - of_node_put(np); - return ret; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0137-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch b/SPECS/linux-lts-kmhv2/0137-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch deleted file mode 100644 index 96d941c0e6..0000000000 --- a/SPECS/linux-lts-kmhv2/0137-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch +++ /dev/null @@ -1,73 +0,0 @@ -From b747ec1922a3e8649cc3e23e2e18038cb693ff9d Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 27 Jan 2026 10:58:49 +0800 -Subject: [PATCH 137/467] UPSTREAM: gpio: spacemit-k1: Use PDR for pin - direction, not SDR/CDR - -On the SpacemiT GPIO controller, the direction control register PDR is -readable and writable [1]. Therefore, implement direction control by -using PDR as dirout, and don't mark it as unreadable. - -The original implementation, using SDR as dirout and CDR as dirin, is -not actually a supported configuration by gpio-mmio. The hardware -supports changing the direction of some pins atomically by writing a -value with the corresponding bits set to SDR (set as output) or to CDR -(set as input). However, gpio-mmio does not actually handle this. - -Using only PDR as dirout to match the expectations of gpio-mmio. This -also allows us to avoid clobbering potentially important GPIO direction -configurations set by pre-Linux boot stages. - -Found while trying to add PCIe support to OrangePi RV2, where the -regulator (controlled by GPIO 116) turns off on boot while some other -GPIO pin in the same bank is touched, which is not desirable. - -Link: https://developer.spacemit.com/documentation?token=Rn9Kw3iFHirAMgkIpTAcV2Arnkf#18.4-gpio # [1] -Fixes: d00553240ef8 ("gpio: spacemit: add support for K1 SoC") -Signed-off-by: Vivian Wang -Reviewed-by: Troy Mitchell -Link: https://patch.msgid.link/20260127-gpio-spacemit-k1-pdr-v1-1-bb868a517dbc@iscas.ac.cn -Signed-off-by: Bartosz Golaszewski -(cherry picked from commit aa7e37fd770bafaaf856ab77735296955b93e377) -Signed-off-by: Han Gao ---- - drivers/gpio/gpio-spacemit-k1.c | 9 +++------ - 1 file changed, 3 insertions(+), 6 deletions(-) - -diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c -index 8f570a1a4894..dbd2e81094b9 100644 ---- a/drivers/gpio/gpio-spacemit-k1.c -+++ b/drivers/gpio/gpio-spacemit-k1.c -@@ -199,7 +199,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - struct gpio_chip *gc = &gb->chip.gc; - struct device *dev = sg->dev; - struct gpio_irq_chip *girq; -- void __iomem *dat, *set, *clr, *dirin, *dirout; -+ void __iomem *dat, *set, *clr, *dirout; - int ret; - - gb->base = regs + sg->data->bank_offsets[index]; -@@ -208,8 +208,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - dat = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPLR]; - set = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPSR]; - clr = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPCR]; -- dirin = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GCDR]; -- dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GSDR]; -+ dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPDR]; - - config = (struct gpio_generic_chip_config) { - .dev = dev, -@@ -218,9 +217,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - .set = set, - .clr = clr, - .dirout = dirout, -- .dirin = dirin, -- .flags = GPIO_GENERIC_UNREADABLE_REG_SET | -- GPIO_GENERIC_UNREADABLE_REG_DIR, -+ .flags = GPIO_GENERIC_UNREADABLE_REG_SET, - }; - - /* This registers 32 GPIO lines per bank */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch b/SPECS/linux-lts-kmhv2/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch new file mode 100644 index 0000000000..f0ab6e429d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch @@ -0,0 +1,33 @@ +From c37e910069a44317c77ac4d11b37028e5c7a3473 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 23 Dec 2025 10:24:51 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: sdhci: add reset support + +Request two reset line explicitly for SDHCI controller. + +Reviewed-by: Javier Martinez Canillas +Link: https://lore.kernel.org/r/20251223-07-k1-sdhci-reset-v2-3-5b8248cfc522@gentoo.org +Signed-off-by: Yixun Lan +(cherry picked from commit 7689c2d1bb1f53b170af79007d0611b43f232f05) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 0a884947fda4..529ec68e9c23 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -1201,6 +1201,9 @@ emmc: mmc@d4281000 { + clocks = <&syscon_apmu CLK_SDH_AXI>, + <&syscon_apmu CLK_SDH2>; + clock-names = "core", "io"; ++ resets = <&syscon_apmu RESET_SDH_AXI>, ++ <&syscon_apmu RESET_SDH2>; ++ reset-names = "axi", "sdh"; + interrupts = <101>; + status = "disabled"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch b/SPECS/linux-lts-kmhv2/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch new file mode 100644 index 0000000000..d3ca21faa5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch @@ -0,0 +1,52 @@ +From cbbdae1821a5dd4f90a95e88d5c536f2421da1b6 Mon Sep 17 00:00:00 2001 +From: Charles Mirabile +Date: Mon, 3 Nov 2025 11:18:13 -0500 +Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Fix call to + __plic_toggle() in M-Mode code path + +The code path for M-Mode linux that disables interrupts for other contexts +was missed when refactoring __plic_toggle(). + +Since the new version caches updates to the state for the primary context, +its use in this codepath is no longer desireable even if it could be made +correct. + +Replace the calls to __plic_toggle() with a loop that simply disables all +of the interrupts in groups of 32 with a direct mmio write. + +Fixes: 14ff9e54dd14 ("irqchip/sifive-plic: Cache the interrupt enable state") +Reported-by: kernel test robot +Signed-off-by: Charles Mirabile +Signed-off-by: Thomas Gleixner +Link: https://patch.msgid.link/20251103161813.2437427-1-cmirabil@redhat.com +Closes: https://lore.kernel.org/oe-kbuild-all/202510271316.AQM7gCCy-lkp@intel.com/ +(cherry picked from commit a045359e72455c4fd178fbedbf398f8df7da97e7) +Signed-off-by: Han Gao +--- + drivers/irqchip/irq-sifive-plic.c | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c +index b6ea38e24af3..53e446117599 100644 +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -684,12 +684,11 @@ static int plic_probe(struct fwnode_handle *fwnode) + if (parent_hwirq != RV_IRQ_EXT) { + /* Disable S-mode enable bits if running in M-mode. */ + if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { +- void __iomem *enable_base = priv->regs + +- CONTEXT_ENABLE_BASE + +- i * CONTEXT_ENABLE_SIZE; ++ u32 __iomem *enable_base = priv->regs + CONTEXT_ENABLE_BASE + ++ i * CONTEXT_ENABLE_SIZE; + +- for (hwirq = 1; hwirq <= nr_irqs; hwirq++) +- __plic_toggle(enable_base, hwirq, 0); ++ for (int j = 0; j <= nr_irqs / 32; j++) ++ writel(0, enable_base + j); + } + continue; + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0138-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch b/SPECS/linux-lts-kmhv2/0138-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch deleted file mode 100644 index 2865bd4d90..0000000000 --- a/SPECS/linux-lts-kmhv2/0138-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 333c560956b18cc11cf301ba2198e261c02c7e73 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Fri, 26 Dec 2025 11:32:27 -0600 -Subject: [PATCH 138/467] UPSTREAM: phy: Kconfig: spacemit: add COMMON_CLK - dependency - -The SpacemiT PCIe PHY driver depends on the common clock framework. -Not specifying that led to a failure when doing a COMPILE_TEST build -for the SPARC architecture. - -Reported-by: kernel test robot -Closes: https://lore.kernel.org/oe-kbuild-all/202512251903.sTVZgg6c-lkp@intel.com/ -Signed-off-by: Alex Elder -Reviewed-by: Javier Martinez Canillas -Link: https://patch.msgid.link/20251226173228.2020411-1-elder@riscstar.com -Signed-off-by: Vinod Koul -(cherry picked from commit 8df20813eb01fe29b4507fd470d73675bda3e1dd) -Signed-off-by: Han Gao ---- - drivers/phy/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig -index 95ee47f0fbc7..88ea9af445b1 100644 ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -104,6 +104,7 @@ config PHY_NXP_PTN3222 - config PHY_SPACEMIT_K1_PCIE - tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC" - depends on ARCH_SPACEMIT || COMPILE_TEST -+ depends on COMMON_CLK - depends on HAS_IOMEM - depends on OF - select GENERIC_PHY --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch b/SPECS/linux-lts-kmhv2/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch new file mode 100644 index 0000000000..a2ed1e4b8d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch @@ -0,0 +1,41 @@ +From d25027971bf83bf11dd914b3ce914fa9ada558c4 Mon Sep 17 00:00:00 2001 +From: Yangyu Chen +Date: Wed, 4 Feb 2026 01:21:48 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: + sifive,plic: Clarify the riscv,ndev meaning in PLIC + +In PLIC, interrupt source 0 is reserved and should not be used. +Therefore, the valid interrupt sources are from 1 to riscv,ndev +inclusive. + +Update the documentation to clarify this point. + +[ tglx: Fixup subject prefix ] + +Signed-off-by: Yangyu Chen +Signed-off-by: Thomas Gleixner +Link: https://patch.msgid.link/tencent_720A4669773B1EE15EC720869C35C2F0490A@qq.com +(cherry picked from commit 889588d750506d86ba16ae3b968b5ffc5937d5f8) +Signed-off-by: Han Gao +--- + .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +index 234cdc2a1a26..8ff5dda648f6 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml ++++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +@@ -105,7 +105,9 @@ properties: + riscv,ndev: + $ref: /schemas/types.yaml#/definitions/uint32 + description: +- Specifies how many external interrupts are supported by this controller. ++ Specifies how many external (device) interrupts are supported by this ++ controller. Note that source 0 is reserved in PLIC, so the valid ++ interrupt sources are 1 to riscv,ndev inclusive. + + clocks: true + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0139-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch b/SPECS/linux-lts-kmhv2/0139-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch deleted file mode 100644 index 437a02c89d..0000000000 --- a/SPECS/linux-lts-kmhv2/0139-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0eab8250c33a6d8337f71d836737b0f27ac47f13 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 25 Dec 2025 15:46:32 +0800 -Subject: [PATCH 139/467] UPSTREAM: mfd: Kconfig: Default MFD_SPACEMIT_P1 to - 'm' if ARCH_SPACEMIT - -The default value of the P1 sub-device depends on the value -of P1, so P1 should have a default value here. - -Signed-off-by: Troy Mitchell -Acked-by: Alex Elder -Link: https://patch.msgid.link/20251225-p1-kconfig-fix-v4-2-44b6728117c1@linux.spacemit.com -Signed-off-by: Lee Jones -(cherry picked from commit 9d1e2d5f2b24a24b32aca451d6a7feb081ad5a62) -Signed-off-by: Han Gao ---- - drivers/mfd/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig -index b0264352790e..8295e7871d70 100644 ---- a/drivers/mfd/Kconfig -+++ b/drivers/mfd/Kconfig -@@ -1270,6 +1270,7 @@ config MFD_SPACEMIT_P1 - depends on ARCH_SPACEMIT || COMPILE_TEST - depends on I2C - select MFD_SIMPLE_MFD_I2C -+ default m if ARCH_SPACEMIT - help - This option supports the I2C-based SpacemiT P1 PMIC, which - contains regulators, a power switch, GPIOs, an RTC, and more. --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch b/SPECS/linux-lts-kmhv2/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch new file mode 100644 index 0000000000..b6309ec5fd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch @@ -0,0 +1,229 @@ +From 8c3cf0715b0fdf641d78f56c2a4a207b6fb93525 Mon Sep 17 00:00:00 2001 +From: Thomas Gleixner +Date: Tue, 3 Feb 2026 20:16:12 +0100 +Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Handle number of hardware + interrupts correctly + +The driver is handling the number of hardware interrupts inconsistently. + +The reason is that the firmware enumerates the maximum number of device +interrupts, but the actual number of hardware interrupts is one more +because hardware interrupt 0 is reserved. + +There are two loop variants where this matters: + + 1) Iterating over the device interrupts + + for (irq = 1; irq < total_irqs; irq++) + + 2) Iterating over the number of interrupt register groups + + for (grp = 0; grp < irq_groups; grp++) + +The current code stores the number of device interrupts and that requires +to write the loops as: + + 1) for (irq = 1; irq <= device_irqs; irq++) + + 2) for (grp = 0; grp < DIV_ROUND_UP(device_irqs + 1); grp++) + +But the code gets it wrong all over the place. Just fixing up the +conditions and off by ones is not a sustainable solution as the next changes +will reintroduce the same bugs over and over. + +Sanitize it by storing the total number of hardware interrupts during probe +and precalculating the number of groups. To future proof it mark +priv::total_irqs __private, provide a correct iterator macro and adjust the +code to this. + +Marking it private allows sparse (C=1 build) to catch direct access to this +member: + + drivers/irqchip/irq-sifive-plic.c:270:9: warning: dereference of noderef expression + +That should prevent at least the most obvious future damage in that area. + +Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation") +Reported-by: Yangyu Chen +Signed-off-by: Thomas Gleixner +Tested-by: Yangyu Chen +Link: https://patch.msgid.link/87ikcd36i9.ffs@tglx +(cherry picked from commit 42e025b719c128bdf8ff88584589a1e4a2448c81) +Signed-off-by: Han Gao +--- + drivers/irqchip/irq-sifive-plic.c | 82 +++++++++++++++++-------------- + 1 file changed, 45 insertions(+), 37 deletions(-) + +diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c +index 53e446117599..f255fa044764 100644 +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -68,15 +68,17 @@ + #define PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM 1 + + struct plic_priv { +- struct fwnode_handle *fwnode; +- struct cpumask lmask; +- struct irq_domain *irqdomain; +- void __iomem *regs; +- unsigned long plic_quirks; +- unsigned int nr_irqs; +- unsigned long *prio_save; +- u32 gsi_base; +- int acpi_plic_id; ++ struct fwnode_handle *fwnode; ++ struct cpumask lmask; ++ struct irq_domain *irqdomain; ++ void __iomem *regs; ++ unsigned long plic_quirks; ++ /* device interrupts + 1 to compensate for the reserved hwirq 0 */ ++ unsigned int __private total_irqs; ++ unsigned int irq_groups; ++ unsigned long *prio_save; ++ u32 gsi_base; ++ int acpi_plic_id; + }; + + struct plic_handler { +@@ -91,6 +93,12 @@ struct plic_handler { + u32 *enable_save; + struct plic_priv *priv; + }; ++ ++/* ++ * Macro to deal with the insanity of hardware interrupt 0 being reserved */ ++#define for_each_device_irq(iter, priv) \ ++ for (unsigned int iter = 1; iter < ACCESS_PRIVATE(priv, total_irqs); iter++) ++ + static int plic_parent_irq __ro_after_init; + static bool plic_global_setup_done __ro_after_init; + static DEFINE_PER_CPU(struct plic_handler, plic_handlers); +@@ -262,14 +270,11 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type) + + static int plic_irq_suspend(void) + { +- struct plic_priv *priv; +- +- priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; ++ struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; + +- /* irq ID 0 is reserved */ +- for (unsigned int i = 1; i < priv->nr_irqs; i++) { +- __assign_bit(i, priv->prio_save, +- readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID)); ++ for_each_device_irq(irq, priv) { ++ __assign_bit(irq, priv->prio_save, ++ readl(priv->regs + PRIORITY_BASE + irq * PRIORITY_PER_ID)); + } + + return 0; +@@ -277,18 +282,15 @@ static int plic_irq_suspend(void) + + static void plic_irq_resume(void) + { +- unsigned int i, index, cpu; ++ struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; ++ unsigned int index, cpu; + unsigned long flags; + u32 __iomem *reg; +- struct plic_priv *priv; +- +- priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; + +- /* irq ID 0 is reserved */ +- for (i = 1; i < priv->nr_irqs; i++) { +- index = BIT_WORD(i); +- writel((priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0, +- priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID); ++ for_each_device_irq(irq, priv) { ++ index = BIT_WORD(irq); ++ writel((priv->prio_save[index] & BIT_MASK(irq)) ? 1 : 0, ++ priv->regs + PRIORITY_BASE + irq * PRIORITY_PER_ID); + } + + for_each_present_cpu(cpu) { +@@ -298,7 +300,7 @@ static void plic_irq_resume(void) + continue; + + raw_spin_lock_irqsave(&handler->enable_lock, flags); +- for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { ++ for (unsigned int i = 0; i < priv->irq_groups; i++) { + reg = handler->enable_base + i * sizeof(u32); + writel(handler->enable_save[i], reg); + } +@@ -432,7 +434,7 @@ static u32 cp100_isolate_pending_irq(int nr_irq_groups, struct plic_handler *han + + static irq_hw_number_t cp100_get_hwirq(struct plic_handler *handler, void __iomem *claim) + { +- int nr_irq_groups = DIV_ROUND_UP(handler->priv->nr_irqs, 32); ++ int nr_irq_groups = handler->priv->irq_groups; + u32 __iomem *enable = handler->enable_base; + irq_hw_number_t hwirq = 0; + u32 iso_mask; +@@ -615,7 +617,6 @@ static int plic_probe(struct fwnode_handle *fwnode) + struct plic_handler *handler; + u32 nr_irqs, parent_hwirq; + struct plic_priv *priv; +- irq_hw_number_t hwirq; + void __iomem *regs; + int id, context_id; + u32 gsi_base; +@@ -648,7 +649,16 @@ static int plic_probe(struct fwnode_handle *fwnode) + + priv->fwnode = fwnode; + priv->plic_quirks = plic_quirks; +- priv->nr_irqs = nr_irqs; ++ /* ++ * The firmware provides the number of device interrupts. As ++ * hardware interrupt 0 is reserved, the number of total interrupts ++ * is nr_irqs + 1. ++ */ ++ nr_irqs++; ++ ACCESS_PRIVATE(priv, total_irqs) = nr_irqs; ++ /* Precalculate the number of register groups */ ++ priv->irq_groups = DIV_ROUND_UP(nr_irqs, 32); ++ + priv->regs = regs; + priv->gsi_base = gsi_base; + priv->acpi_plic_id = id; +@@ -687,7 +697,7 @@ static int plic_probe(struct fwnode_handle *fwnode) + u32 __iomem *enable_base = priv->regs + CONTEXT_ENABLE_BASE + + i * CONTEXT_ENABLE_SIZE; + +- for (int j = 0; j <= nr_irqs / 32; j++) ++ for (int j = 0; j < priv->irq_groups; j++) + writel(0, enable_base + j); + } + continue; +@@ -719,23 +729,21 @@ static int plic_probe(struct fwnode_handle *fwnode) + context_id * CONTEXT_ENABLE_SIZE; + handler->priv = priv; + +- handler->enable_save = kcalloc(DIV_ROUND_UP(nr_irqs, 32), +- sizeof(*handler->enable_save), GFP_KERNEL); ++ handler->enable_save = kcalloc(priv->irq_groups, sizeof(*handler->enable_save), ++ GFP_KERNEL); + if (!handler->enable_save) { + error = -ENOMEM; + goto fail_cleanup_contexts; + } + done: +- for (hwirq = 1; hwirq <= nr_irqs; hwirq++) { ++ for_each_device_irq(hwirq, priv) { + plic_toggle(handler, hwirq, 0); +- writel(1, priv->regs + PRIORITY_BASE + +- hwirq * PRIORITY_PER_ID); ++ writel(1, priv->regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID); + } + nr_handlers++; + } + +- priv->irqdomain = irq_domain_create_linear(fwnode, nr_irqs + 1, +- &plic_irqdomain_ops, priv); ++ priv->irqdomain = irq_domain_create_linear(fwnode, nr_irqs, &plic_irqdomain_ops, priv); + if (WARN_ON(!priv->irqdomain)) { + error = -ENOMEM; + goto fail_cleanup_contexts; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0140-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch b/SPECS/linux-lts-kmhv2/0140-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch deleted file mode 100644 index 07df5e5f9d..0000000000 --- a/SPECS/linux-lts-kmhv2/0140-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch +++ /dev/null @@ -1,34 +0,0 @@ -From dded14b2f88c749f0ee43ce0475efa38aab240b7 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 23 Dec 2025 10:24:51 +0800 -Subject: [PATCH 140/467] UPSTREAM: riscv: dts: spacemit: sdhci: add reset - support - -Request two reset line explicitly for SDHCI controller. - -Reviewed-by: Javier Martinez Canillas -Link: https://lore.kernel.org/r/20251223-07-k1-sdhci-reset-v2-3-5b8248cfc522@gentoo.org -Signed-off-by: Yixun Lan -(cherry picked from commit 7689c2d1bb1f53b170af79007d0611b43f232f05) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 0a884947fda4..529ec68e9c23 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -1201,6 +1201,9 @@ emmc: mmc@d4281000 { - clocks = <&syscon_apmu CLK_SDH_AXI>, - <&syscon_apmu CLK_SDH2>; - clock-names = "core", "io"; -+ resets = <&syscon_apmu RESET_SDH_AXI>, -+ <&syscon_apmu RESET_SDH2>; -+ reset-names = "axi", "sdh"; - interrupts = <101>; - status = "disabled"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch b/SPECS/linux-lts-kmhv2/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch new file mode 100644 index 0000000000..ec4bffaa6b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch @@ -0,0 +1,145 @@ +From fd2ed2a093642f9ae52054344b23d1c512e4d4b6 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Fri, 9 Jan 2026 19:34:30 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: dwc: Use multiple iATU windows for + mapping large bridge windows and DMA ranges + +The DWC driver tries to use a single iATU region for mapping the individual +entries of the bridge window and DMA range. If a bridge window/DMA range is +larger than the iATU inbound/outbound window size, then the mapping will +fail. + +Hence, avoid this failure by using multiple iATU windows to map the whole +region. If the region runs out of iATU windows, then return failure. + +Signed-off-by: Charles Mirabile +Signed-off-by: Samuel Holland +Co-developed-by: Randolph Lin +Signed-off-by: Randolph Lin +[mani: reworded description, minor code cleanup] +Signed-off-by: Manivannan Sadhasivam +Reviewed-by: Niklas Cassel +Reviewed-by: Frank Li +Acked-by: Charles Mirabile +Link: https://patch.msgid.link/20260109113430.2767264-1-randolph@andestech.com +(cherry picked from commit e9a5415adb209f86a05e55b850127ada82e070f1) +Signed-off-by: Han Gao +--- + .../pci/controller/dwc/pcie-designware-host.c | 74 ++++++++++++++----- + 1 file changed, 57 insertions(+), 17 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c +index 48e4a887bb1b..993858fd0529 100644 +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -887,29 +887,50 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) + + i = 0; + resource_list_for_each_entry(entry, &pp->bridge->windows) { ++ resource_size_t res_size; ++ + if (resource_type(entry->res) != IORESOURCE_MEM) + continue; + +- if (pci->num_ob_windows <= ++i) ++ if (pci->num_ob_windows <= i + 1) + break; + +- atu.index = i; + atu.type = PCIE_ATU_TYPE_MEM; + atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset; + atu.pci_addr = entry->res->start - entry->offset; + + /* Adjust iATU size if MSG TLP region was allocated before */ + if (pp->msg_res && pp->msg_res->parent == entry->res) +- atu.size = resource_size(entry->res) - ++ res_size = resource_size(entry->res) - + resource_size(pp->msg_res); + else +- atu.size = resource_size(entry->res); ++ res_size = resource_size(entry->res); ++ ++ while (res_size > 0) { ++ /* ++ * Return failure if we run out of windows in the ++ * middle. Otherwise, we would end up only partially ++ * mapping a single resource. ++ */ ++ if (pci->num_ob_windows <= ++i) { ++ dev_err(pci->dev, "Exhausted outbound windows for region: %pr\n", ++ entry->res); ++ return -ENOMEM; ++ } + +- ret = dw_pcie_prog_outbound_atu(pci, &atu); +- if (ret) { +- dev_err(pci->dev, "Failed to set MEM range %pr\n", +- entry->res); +- return ret; ++ atu.index = i; ++ atu.size = MIN(pci->region_limit + 1, res_size); ++ ++ ret = dw_pcie_prog_outbound_atu(pci, &atu); ++ if (ret) { ++ dev_err(pci->dev, "Failed to set MEM range %pr\n", ++ entry->res); ++ return ret; ++ } ++ ++ atu.parent_bus_addr += atu.size; ++ atu.pci_addr += atu.size; ++ res_size -= atu.size; + } + } + +@@ -947,20 +968,39 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) + + i = 0; + resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { ++ resource_size_t res_start, res_size, window_size; ++ + if (resource_type(entry->res) != IORESOURCE_MEM) + continue; + + if (pci->num_ib_windows <= i) + break; + +- ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, +- entry->res->start, +- entry->res->start - entry->offset, +- resource_size(entry->res)); +- if (ret) { +- dev_err(pci->dev, "Failed to set DMA range %pr\n", +- entry->res); +- return ret; ++ res_size = resource_size(entry->res); ++ res_start = entry->res->start; ++ while (res_size > 0) { ++ /* ++ * Return failure if we run out of windows in the ++ * middle. Otherwise, we would end up only partially ++ * mapping a single resource. ++ */ ++ if (pci->num_ib_windows <= i) { ++ dev_err(pci->dev, "Exhausted inbound windows for region: %pr\n", ++ entry->res); ++ return -ENOMEM; ++ } ++ ++ window_size = MIN(pci->region_limit + 1, res_size); ++ ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, res_start, ++ res_start - entry->offset, window_size); ++ if (ret) { ++ dev_err(pci->dev, "Failed to set DMA range %pr\n", ++ entry->res); ++ return ret; ++ } ++ ++ res_start += window_size; ++ res_size -= window_size; + } + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0141-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch b/SPECS/linux-lts-kmhv2/0141-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch deleted file mode 100644 index c0f3a9e111..0000000000 --- a/SPECS/linux-lts-kmhv2/0141-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch +++ /dev/null @@ -1,52 +0,0 @@ -From f58e9a459a7b6b435352438dc53508ab2626a69a Mon Sep 17 00:00:00 2001 -From: Charles Mirabile -Date: Mon, 3 Nov 2025 11:18:13 -0500 -Subject: [PATCH 141/467] UPSTREAM: irqchip/sifive-plic: Fix call to - __plic_toggle() in M-Mode code path - -The code path for M-Mode linux that disables interrupts for other contexts -was missed when refactoring __plic_toggle(). - -Since the new version caches updates to the state for the primary context, -its use in this codepath is no longer desireable even if it could be made -correct. - -Replace the calls to __plic_toggle() with a loop that simply disables all -of the interrupts in groups of 32 with a direct mmio write. - -Fixes: 14ff9e54dd14 ("irqchip/sifive-plic: Cache the interrupt enable state") -Reported-by: kernel test robot -Signed-off-by: Charles Mirabile -Signed-off-by: Thomas Gleixner -Link: https://patch.msgid.link/20251103161813.2437427-1-cmirabil@redhat.com -Closes: https://lore.kernel.org/oe-kbuild-all/202510271316.AQM7gCCy-lkp@intel.com/ -(cherry picked from commit a045359e72455c4fd178fbedbf398f8df7da97e7) -Signed-off-by: Han Gao ---- - drivers/irqchip/irq-sifive-plic.c | 9 ++++----- - 1 file changed, 4 insertions(+), 5 deletions(-) - -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index b6ea38e24af3..53e446117599 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -684,12 +684,11 @@ static int plic_probe(struct fwnode_handle *fwnode) - if (parent_hwirq != RV_IRQ_EXT) { - /* Disable S-mode enable bits if running in M-mode. */ - if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { -- void __iomem *enable_base = priv->regs + -- CONTEXT_ENABLE_BASE + -- i * CONTEXT_ENABLE_SIZE; -+ u32 __iomem *enable_base = priv->regs + CONTEXT_ENABLE_BASE + -+ i * CONTEXT_ENABLE_SIZE; - -- for (hwirq = 1; hwirq <= nr_irqs; hwirq++) -- __plic_toggle(enable_base, hwirq, 0); -+ for (int j = 0; j <= nr_irqs / 32; j++) -+ writel(0, enable_base + j); - } - continue; - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0142-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch b/SPECS/linux-lts-kmhv2/0142-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch deleted file mode 100644 index 7916a81092..0000000000 --- a/SPECS/linux-lts-kmhv2/0142-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch +++ /dev/null @@ -1,41 +0,0 @@ -From bf88342cbbf18edbfbf27a30b622622f47dd21d1 Mon Sep 17 00:00:00 2001 -From: Yangyu Chen -Date: Wed, 4 Feb 2026 01:21:48 +0800 -Subject: [PATCH 142/467] UPSTREAM: dt-bindings: interrupt-controller: - sifive,plic: Clarify the riscv,ndev meaning in PLIC - -In PLIC, interrupt source 0 is reserved and should not be used. -Therefore, the valid interrupt sources are from 1 to riscv,ndev -inclusive. - -Update the documentation to clarify this point. - -[ tglx: Fixup subject prefix ] - -Signed-off-by: Yangyu Chen -Signed-off-by: Thomas Gleixner -Link: https://patch.msgid.link/tencent_720A4669773B1EE15EC720869C35C2F0490A@qq.com -(cherry picked from commit 889588d750506d86ba16ae3b968b5ffc5937d5f8) -Signed-off-by: Han Gao ---- - .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml -index 234cdc2a1a26..8ff5dda648f6 100644 ---- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml -+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml -@@ -105,7 +105,9 @@ properties: - riscv,ndev: - $ref: /schemas/types.yaml#/definitions/uint32 - description: -- Specifies how many external interrupts are supported by this controller. -+ Specifies how many external (device) interrupts are supported by this -+ controller. Note that source 0 is reserved in PLIC, so the valid -+ interrupt sources are 1 to riscv,ndev inclusive. - - clocks: true - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch b/SPECS/linux-lts-kmhv2/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch new file mode 100644 index 0000000000..35a46d601c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch @@ -0,0 +1,32 @@ +From b88d7d9315cd6748d47a8ced520004d8f68ec0fc Mon Sep 17 00:00:00 2001 +From: Thomas Gerner +Date: Tue, 20 Jan 2026 09:59:26 +0100 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: th1520: Fix typo + +This fixes a simple typo in the TH1520 SPI0 for group3 pins: +QSPI0 is misspelled QSPI1. + +Signed-off-by: Thomas Gerner +Signed-off-by: Linus Walleij +(cherry picked from commit 304c3ebcaff36560d76e3030ba0839e629635f47) +Signed-off-by: Han Gao +--- + drivers/pinctrl/pinctrl-th1520.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c +index e641bad6728c..83e9c9f77370 100644 +--- a/drivers/pinctrl/pinctrl-th1520.c ++++ b/drivers/pinctrl/pinctrl-th1520.c +@@ -287,7 +287,7 @@ static const struct pinctrl_pin_desc th1520_group3_pins[] = { + TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(6, QSPI0_D1_MISO, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(7, QSPI0_D2_WP, QSPI, PWM, I2S, GPIO, ____, ____, 0), +- TH1520_PAD(8, QSPI1_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0), ++ TH1520_PAD(8, QSPI0_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0), + TH1520_PAD(9, I2C2_SCL, I2C, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(10, I2C2_SDA, I2C, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(11, I2C3_SCL, I2C, ____, ____, GPIO, ____, ____, 0), +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch b/SPECS/linux-lts-kmhv2/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch new file mode 100644 index 0000000000..88cfd245f1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch @@ -0,0 +1,73 @@ +From e3974191639e3270eddc65bb437b729a750e5dc7 Mon Sep 17 00:00:00 2001 +From: Manikandan K Pillai +Date: Sat, 8 Nov 2025 22:02:56 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Add module support for platform + controller driver + +Add support for building PCI cadence platforms as a module. + +Signed-off-by: Manikandan K Pillai +Signed-off-by: Manivannan Sadhasivam +Link: https://patch.msgid.link/20251108140305.1120117-2-hans.zhang@cixtech.com +(cherry picked from commit 611627a4e5e4af7b96aab4f10d130f6a8a615020) +Signed-off-by: Han Gao +--- + drivers/pci/controller/cadence/Kconfig | 6 +++--- + drivers/pci/controller/cadence/pcie-cadence-plat.c | 5 ++++- + drivers/pci/controller/cadence/pcie-cadence.c | 1 + + 3 files changed, 8 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig +index 02a639e55fd8..0b96499ae354 100644 +--- a/drivers/pci/controller/cadence/Kconfig ++++ b/drivers/pci/controller/cadence/Kconfig +@@ -19,10 +19,10 @@ config PCIE_CADENCE_EP + select PCIE_CADENCE + + config PCIE_CADENCE_PLAT +- bool ++ tristate + + config PCIE_CADENCE_PLAT_HOST +- bool "Cadence platform PCIe controller (host mode)" ++ tristate "Cadence platform PCIe controller (host mode)" + depends on OF + select PCIE_CADENCE_HOST + select PCIE_CADENCE_PLAT +@@ -32,7 +32,7 @@ config PCIE_CADENCE_PLAT_HOST + vendors SoCs. + + config PCIE_CADENCE_PLAT_EP +- bool "Cadence platform PCIe controller (endpoint mode)" ++ tristate "Cadence platform PCIe controller (endpoint mode)" + depends on OF + depends on PCI_ENDPOINT + select PCIE_CADENCE_EP +diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c +index 0456845dabb9..ebd5c3afdfcd 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence-plat.c ++++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c +@@ -177,4 +177,7 @@ static struct platform_driver cdns_plat_pcie_driver = { + .probe = cdns_plat_pcie_probe, + .shutdown = cdns_plat_pcie_shutdown, + }; +-builtin_platform_driver(cdns_plat_pcie_driver); ++module_platform_driver(cdns_plat_pcie_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Cadence PCIe controller platform driver"); +diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c +index d614452861f7..fb88a7ade412 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence.c ++++ b/drivers/pci/controller/cadence/pcie-cadence.c +@@ -293,6 +293,7 @@ const struct dev_pm_ops cdns_pcie_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, + cdns_pcie_resume_noirq) + }; ++EXPORT_SYMBOL_GPL(cdns_pcie_pm_ops); + + MODULE_LICENSE("GPL"); + MODULE_DESCRIPTION("Cadence PCIe controller driver"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0143-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch b/SPECS/linux-lts-kmhv2/0143-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch deleted file mode 100644 index 127a04cfa3..0000000000 --- a/SPECS/linux-lts-kmhv2/0143-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch +++ /dev/null @@ -1,229 +0,0 @@ -From f5a054d7440d709d61511cb7a4d626b59ba00bf3 Mon Sep 17 00:00:00 2001 -From: Thomas Gleixner -Date: Tue, 3 Feb 2026 20:16:12 +0100 -Subject: [PATCH 143/467] UPSTREAM: irqchip/sifive-plic: Handle number of - hardware interrupts correctly - -The driver is handling the number of hardware interrupts inconsistently. - -The reason is that the firmware enumerates the maximum number of device -interrupts, but the actual number of hardware interrupts is one more -because hardware interrupt 0 is reserved. - -There are two loop variants where this matters: - - 1) Iterating over the device interrupts - - for (irq = 1; irq < total_irqs; irq++) - - 2) Iterating over the number of interrupt register groups - - for (grp = 0; grp < irq_groups; grp++) - -The current code stores the number of device interrupts and that requires -to write the loops as: - - 1) for (irq = 1; irq <= device_irqs; irq++) - - 2) for (grp = 0; grp < DIV_ROUND_UP(device_irqs + 1); grp++) - -But the code gets it wrong all over the place. Just fixing up the -conditions and off by ones is not a sustainable solution as the next changes -will reintroduce the same bugs over and over. - -Sanitize it by storing the total number of hardware interrupts during probe -and precalculating the number of groups. To future proof it mark -priv::total_irqs __private, provide a correct iterator macro and adjust the -code to this. - -Marking it private allows sparse (C=1 build) to catch direct access to this -member: - - drivers/irqchip/irq-sifive-plic.c:270:9: warning: dereference of noderef expression - -That should prevent at least the most obvious future damage in that area. - -Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation") -Reported-by: Yangyu Chen -Signed-off-by: Thomas Gleixner -Tested-by: Yangyu Chen -Link: https://patch.msgid.link/87ikcd36i9.ffs@tglx -(cherry picked from commit 42e025b719c128bdf8ff88584589a1e4a2448c81) -Signed-off-by: Han Gao ---- - drivers/irqchip/irq-sifive-plic.c | 82 +++++++++++++++++-------------- - 1 file changed, 45 insertions(+), 37 deletions(-) - -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index 53e446117599..f255fa044764 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -68,15 +68,17 @@ - #define PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM 1 - - struct plic_priv { -- struct fwnode_handle *fwnode; -- struct cpumask lmask; -- struct irq_domain *irqdomain; -- void __iomem *regs; -- unsigned long plic_quirks; -- unsigned int nr_irqs; -- unsigned long *prio_save; -- u32 gsi_base; -- int acpi_plic_id; -+ struct fwnode_handle *fwnode; -+ struct cpumask lmask; -+ struct irq_domain *irqdomain; -+ void __iomem *regs; -+ unsigned long plic_quirks; -+ /* device interrupts + 1 to compensate for the reserved hwirq 0 */ -+ unsigned int __private total_irqs; -+ unsigned int irq_groups; -+ unsigned long *prio_save; -+ u32 gsi_base; -+ int acpi_plic_id; - }; - - struct plic_handler { -@@ -91,6 +93,12 @@ struct plic_handler { - u32 *enable_save; - struct plic_priv *priv; - }; -+ -+/* -+ * Macro to deal with the insanity of hardware interrupt 0 being reserved */ -+#define for_each_device_irq(iter, priv) \ -+ for (unsigned int iter = 1; iter < ACCESS_PRIVATE(priv, total_irqs); iter++) -+ - static int plic_parent_irq __ro_after_init; - static bool plic_global_setup_done __ro_after_init; - static DEFINE_PER_CPU(struct plic_handler, plic_handlers); -@@ -262,14 +270,11 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type) - - static int plic_irq_suspend(void) - { -- struct plic_priv *priv; -- -- priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; -+ struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; - -- /* irq ID 0 is reserved */ -- for (unsigned int i = 1; i < priv->nr_irqs; i++) { -- __assign_bit(i, priv->prio_save, -- readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID)); -+ for_each_device_irq(irq, priv) { -+ __assign_bit(irq, priv->prio_save, -+ readl(priv->regs + PRIORITY_BASE + irq * PRIORITY_PER_ID)); - } - - return 0; -@@ -277,18 +282,15 @@ static int plic_irq_suspend(void) - - static void plic_irq_resume(void) - { -- unsigned int i, index, cpu; -+ struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; -+ unsigned int index, cpu; - unsigned long flags; - u32 __iomem *reg; -- struct plic_priv *priv; -- -- priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; - -- /* irq ID 0 is reserved */ -- for (i = 1; i < priv->nr_irqs; i++) { -- index = BIT_WORD(i); -- writel((priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0, -- priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID); -+ for_each_device_irq(irq, priv) { -+ index = BIT_WORD(irq); -+ writel((priv->prio_save[index] & BIT_MASK(irq)) ? 1 : 0, -+ priv->regs + PRIORITY_BASE + irq * PRIORITY_PER_ID); - } - - for_each_present_cpu(cpu) { -@@ -298,7 +300,7 @@ static void plic_irq_resume(void) - continue; - - raw_spin_lock_irqsave(&handler->enable_lock, flags); -- for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { -+ for (unsigned int i = 0; i < priv->irq_groups; i++) { - reg = handler->enable_base + i * sizeof(u32); - writel(handler->enable_save[i], reg); - } -@@ -432,7 +434,7 @@ static u32 cp100_isolate_pending_irq(int nr_irq_groups, struct plic_handler *han - - static irq_hw_number_t cp100_get_hwirq(struct plic_handler *handler, void __iomem *claim) - { -- int nr_irq_groups = DIV_ROUND_UP(handler->priv->nr_irqs, 32); -+ int nr_irq_groups = handler->priv->irq_groups; - u32 __iomem *enable = handler->enable_base; - irq_hw_number_t hwirq = 0; - u32 iso_mask; -@@ -615,7 +617,6 @@ static int plic_probe(struct fwnode_handle *fwnode) - struct plic_handler *handler; - u32 nr_irqs, parent_hwirq; - struct plic_priv *priv; -- irq_hw_number_t hwirq; - void __iomem *regs; - int id, context_id; - u32 gsi_base; -@@ -648,7 +649,16 @@ static int plic_probe(struct fwnode_handle *fwnode) - - priv->fwnode = fwnode; - priv->plic_quirks = plic_quirks; -- priv->nr_irqs = nr_irqs; -+ /* -+ * The firmware provides the number of device interrupts. As -+ * hardware interrupt 0 is reserved, the number of total interrupts -+ * is nr_irqs + 1. -+ */ -+ nr_irqs++; -+ ACCESS_PRIVATE(priv, total_irqs) = nr_irqs; -+ /* Precalculate the number of register groups */ -+ priv->irq_groups = DIV_ROUND_UP(nr_irqs, 32); -+ - priv->regs = regs; - priv->gsi_base = gsi_base; - priv->acpi_plic_id = id; -@@ -687,7 +697,7 @@ static int plic_probe(struct fwnode_handle *fwnode) - u32 __iomem *enable_base = priv->regs + CONTEXT_ENABLE_BASE + - i * CONTEXT_ENABLE_SIZE; - -- for (int j = 0; j <= nr_irqs / 32; j++) -+ for (int j = 0; j < priv->irq_groups; j++) - writel(0, enable_base + j); - } - continue; -@@ -719,23 +729,21 @@ static int plic_probe(struct fwnode_handle *fwnode) - context_id * CONTEXT_ENABLE_SIZE; - handler->priv = priv; - -- handler->enable_save = kcalloc(DIV_ROUND_UP(nr_irqs, 32), -- sizeof(*handler->enable_save), GFP_KERNEL); -+ handler->enable_save = kcalloc(priv->irq_groups, sizeof(*handler->enable_save), -+ GFP_KERNEL); - if (!handler->enable_save) { - error = -ENOMEM; - goto fail_cleanup_contexts; - } - done: -- for (hwirq = 1; hwirq <= nr_irqs; hwirq++) { -+ for_each_device_irq(hwirq, priv) { - plic_toggle(handler, hwirq, 0); -- writel(1, priv->regs + PRIORITY_BASE + -- hwirq * PRIORITY_PER_ID); -+ writel(1, priv->regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID); - } - nr_handlers++; - } - -- priv->irqdomain = irq_domain_create_linear(fwnode, nr_irqs + 1, -- &plic_irqdomain_ops, priv); -+ priv->irqdomain = irq_domain_create_linear(fwnode, nr_irqs, &plic_irqdomain_ops, priv); - if (WARN_ON(!priv->irqdomain)) { - error = -ENOMEM; - goto fail_cleanup_contexts; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch b/SPECS/linux-lts-kmhv2/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch new file mode 100644 index 0000000000..53a32a761a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch @@ -0,0 +1,508 @@ +From 3918539e5418b2d1151b2a2e086601ded67796a3 Mon Sep 17 00:00:00 2001 +From: Manikandan K Pillai +Date: Sat, 8 Nov 2025 22:02:57 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Split PCIe controller header + file + +Split the Cadence PCIe header file by moving the Legacy (LGA) controller +register definitions to a separate header file for support of next +generation PCIe controller architecture. + +Signed-off-by: Manikandan K Pillai +Signed-off-by: Manivannan Sadhasivam +Link: https://patch.msgid.link/20251108140305.1120117-3-hans.zhang@cixtech.com +(cherry picked from commit 3977be25f5fd973cad6bed810ac1045ba8cfbfa6) +Signed-off-by: Han Gao +--- + .../cadence/pcie-cadence-lga-regs.h | 230 ++++++++++++++++++ + drivers/pci/controller/cadence/pcie-cadence.h | 222 +---------------- + 2 files changed, 232 insertions(+), 220 deletions(-) + create mode 100644 drivers/pci/controller/cadence/pcie-cadence-lga-regs.h + +diff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h +new file mode 100644 +index 000000000000..857b2140c5d2 +--- /dev/null ++++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h +@@ -0,0 +1,230 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Cadence PCIe controller driver. ++ * ++ * Copyright (c) 2017 Cadence ++ * Author: Cyrille Pitchen ++ */ ++#ifndef _PCIE_CADENCE_LGA_REGS_H ++#define _PCIE_CADENCE_LGA_REGS_H ++ ++#include ++ ++/* Parameters for the waiting for link up routine */ ++#define LINK_WAIT_MAX_RETRIES 10 ++#define LINK_WAIT_USLEEP_MIN 90000 ++#define LINK_WAIT_USLEEP_MAX 100000 ++ ++/* Local Management Registers */ ++#define CDNS_PCIE_LM_BASE 0x00100000 ++ ++/* Vendor ID Register */ ++#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) ++#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) ++#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 ++#define CDNS_PCIE_LM_ID_VENDOR(vid) \ ++ (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) ++#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) ++#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 ++#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ ++ (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) ++ ++/* Root Port Requester ID Register */ ++#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) ++#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) ++#define CDNS_PCIE_LM_RP_RID_SHIFT 0 ++#define CDNS_PCIE_LM_RP_RID_(rid) \ ++ (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) ++ ++/* Endpoint Bus and Device Number Register */ ++#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022C) ++#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) ++#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 ++#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) ++#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 ++ ++/* Endpoint Function f BAR b Configuration Registers */ ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ ++ (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn)) ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ ++ (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ ++ (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) ++#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ ++ (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn)) ++#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ ++ (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) ++#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ ++ (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ ++ (GENMASK(4, 0) << ((b) * 8)) ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ ++ (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ ++ (GENMASK(7, 5) << ((b) * 8)) ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ ++ (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) ++ ++/* Endpoint Function Configuration Register */ ++#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02C0) ++ ++/* Root Complex BAR Configuration Register */ ++#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ ++ (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ ++ (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ ++ (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ ++ (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) ++#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) ++#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 ++#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) ++#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) ++#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 ++#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) ++#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) ++ ++/* BAR control values applicable to both Endpoint Function and Root Complex */ ++#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 ++#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 ++#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 ++#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 ++#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 ++#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 ++ ++#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ ++ (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) ++#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ ++ (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) ++#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ ++ (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) ++#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ ++ (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) ++#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ ++ (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) ++#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ ++ (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) ++#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ ++ (((aperture) - 2) << ((bar) * 8)) ++ ++/* PTM Control Register */ ++#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0DA8) ++#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) ++ ++/* ++ * Endpoint Function Registers (PCI configuration space for endpoint functions) ++ */ ++#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) ++ ++#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 ++#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xB0 ++#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xC0 ++#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 ++ ++/* Endpoint PF Registers */ ++#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) ++#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) ++ ++/* Root Port Registers (PCI configuration space for the root port function) */ ++#define CDNS_PCIE_RP_BASE 0x00200000 ++#define CDNS_PCIE_RP_CAP_OFFSET 0xC0 ++ ++/* Address Translation Registers */ ++#define CDNS_PCIE_AT_BASE 0x00400000 ++ ++/* Region r Outbound AXI to PCIe Address Translation Register 0 */ ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ ++ (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1F) * 0x0020) ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ ++ (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ ++ (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ ++ (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) ++ ++/* Region r Outbound AXI to PCIe Address Translation Register 1 */ ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ ++ (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1F) * 0x0020) ++ ++/* Region r Outbound PCIe Descriptor Register 0 */ ++#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ ++ (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1F) * 0x0020) ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xA ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xB ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xC ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xD ++/* Bit 23 MUST be set in RC mode. */ ++#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) ++#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) ++#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ ++ (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) ++ ++/* Region r Outbound PCIe Descriptor Register 1 */ ++#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ ++ (CDNS_PCIE_AT_BASE + 0x000C + ((r) & 0x1F) * 0x0020) ++#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) ++#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ ++ ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) ++ ++/* Region r AXI Region Base Address Register 0 */ ++#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ ++ (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1F) * 0x0020) ++#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) ++#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ ++ (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) ++ ++/* Region r AXI Region Base Address Register 1 */ ++#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ ++ (CDNS_PCIE_AT_BASE + 0x001C + ((r) & 0x1F) * 0x0020) ++ ++/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ ++#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ ++ (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) ++#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) ++#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ ++ (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) ++#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ ++ (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) ++ ++/* AXI link down register */ ++#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) ++ ++/* LTSSM Capabilities register */ ++#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) ++#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) ++#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 ++#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ ++ (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ ++ CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) ++ ++#define CDNS_PCIE_RP_MAX_IB 0x3 ++#define CDNS_PCIE_MAX_OB 32 ++ ++/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ ++#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ ++ (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) ++#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ ++ (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) ++ ++/* Normal/Vendor specific message access: offset inside some outbound region */ ++#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) ++#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ ++ (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) ++#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) ++#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ ++ (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) ++#define CDNS_PCIE_MSG_NO_DATA BIT(16) ++ ++#endif /* _PCIE_CADENCE_LGA_REGS_H */ +diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h +index 23ccad0a31f2..23aa64df1980 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence.h ++++ b/drivers/pci/controller/cadence/pcie-cadence.h +@@ -7,211 +7,11 @@ + #define _PCIE_CADENCE_H + + #include ++#include + #include + #include + #include +- +-/* Parameters for the waiting for link up routine */ +-#define LINK_WAIT_MAX_RETRIES 10 +-#define LINK_WAIT_USLEEP_MIN 90000 +-#define LINK_WAIT_USLEEP_MAX 100000 +- +-/* +- * Local Management Registers +- */ +-#define CDNS_PCIE_LM_BASE 0x00100000 +- +-/* Vendor ID Register */ +-#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) +-#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) +-#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 +-#define CDNS_PCIE_LM_ID_VENDOR(vid) \ +- (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) +-#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) +-#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 +-#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ +- (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) +- +-/* Root Port Requester ID Register */ +-#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) +-#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) +-#define CDNS_PCIE_LM_RP_RID_SHIFT 0 +-#define CDNS_PCIE_LM_RP_RID_(rid) \ +- (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) +- +-/* Endpoint Bus and Device Number Register */ +-#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) +-#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) +-#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 +-#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) +-#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 +- +-/* Endpoint Function f BAR b Configuration Registers */ +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ +- (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn)) +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ +- (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ +- (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) +-#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ +- (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn)) +-#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ +- (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) +-#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ +- (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ +- (GENMASK(4, 0) << ((b) * 8)) +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ +- (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ +- (GENMASK(7, 5) << ((b) * 8)) +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ +- (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) +- +-/* Endpoint Function Configuration Register */ +-#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) +- +-/* Root Complex BAR Configuration Register */ +-#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ +- (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ +- (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ +- (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ +- (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) +-#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) +-#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 +-#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) +-#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) +-#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 +-#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) +-#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) +- +-/* BAR control values applicable to both Endpoint Function and Root Complex */ +-#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 +-#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 +-#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 +-#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 +-#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 +-#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 +- +-#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ +- (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) +-#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ +- (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) +-#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ +- (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) +-#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ +- (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) +-#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ +- (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) +-#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ +- (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) +-#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ +- (((aperture) - 2) << ((bar) * 8)) +- +-/* PTM Control Register */ +-#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8) +-#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) +- +-/* +- * Endpoint Function Registers (PCI configuration space for endpoint functions) +- */ +-#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) +- +-/* +- * Endpoint PF Registers +- */ +-#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) +-#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) +- +-/* +- * Root Port Registers (PCI configuration space for the root port function) +- */ +-#define CDNS_PCIE_RP_BASE 0x00200000 +-#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 +- +-/* +- * Address Translation Registers +- */ +-#define CDNS_PCIE_AT_BASE 0x00400000 +- +-/* Region r Outbound AXI to PCIe Address Translation Register 0 */ +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ +- (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ +- (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ +- (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ +- (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) +- +-/* Region r Outbound AXI to PCIe Address Translation Register 1 */ +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ +- (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) +- +-/* Region r Outbound PCIe Descriptor Register 0 */ +-#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ +- (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd +-/* Bit 23 MUST be set in RC mode. */ +-#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) +-#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) +-#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ +- (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) +- +-/* Region r Outbound PCIe Descriptor Register 1 */ +-#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ +- (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) +-#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) +-#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ +- ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) +- +-/* Region r AXI Region Base Address Register 0 */ +-#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ +- (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) +-#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) +-#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ +- (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) +- +-/* Region r AXI Region Base Address Register 1 */ +-#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ +- (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) +- +-/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ +-#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ +- (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) +-#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) +-#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ +- (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) +-#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ +- (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) +- +-/* AXI link down register */ +-#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) +- +-/* LTSSM Capabilities register */ +-#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) +-#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) +-#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 +-#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ +- (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ +- CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) ++#include "pcie-cadence-lga-regs.h" + + enum cdns_pcie_rp_bar { + RP_BAR_UNDEFINED = -1, +@@ -220,29 +20,11 @@ enum cdns_pcie_rp_bar { + RP_NO_BAR + }; + +-#define CDNS_PCIE_RP_MAX_IB 0x3 +-#define CDNS_PCIE_MAX_OB 32 +- + struct cdns_pcie_rp_ib_bar { + u64 size; + bool free; + }; + +-/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ +-#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ +- (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) +-#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ +- (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) +- +-/* Normal/Vendor specific message access: offset inside some outbound region */ +-#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) +-#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ +- (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) +-#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) +-#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ +- (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) +-#define CDNS_PCIE_MSG_DATA BIT(16) +- + struct cdns_pcie; + + struct cdns_pcie_ops { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0144-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch b/SPECS/linux-lts-kmhv2/0144-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch deleted file mode 100644 index eedd218a03..0000000000 --- a/SPECS/linux-lts-kmhv2/0144-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch +++ /dev/null @@ -1,145 +0,0 @@ -From 24b2064ff98e5d2c22d87bc0a86ee411e19fa6bb Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 9 Jan 2026 19:34:30 +0800 -Subject: [PATCH 144/467] UPSTREAM: PCI: dwc: Use multiple iATU windows for - mapping large bridge windows and DMA ranges - -The DWC driver tries to use a single iATU region for mapping the individual -entries of the bridge window and DMA range. If a bridge window/DMA range is -larger than the iATU inbound/outbound window size, then the mapping will -fail. - -Hence, avoid this failure by using multiple iATU windows to map the whole -region. If the region runs out of iATU windows, then return failure. - -Signed-off-by: Charles Mirabile -Signed-off-by: Samuel Holland -Co-developed-by: Randolph Lin -Signed-off-by: Randolph Lin -[mani: reworded description, minor code cleanup] -Signed-off-by: Manivannan Sadhasivam -Reviewed-by: Niklas Cassel -Reviewed-by: Frank Li -Acked-by: Charles Mirabile -Link: https://patch.msgid.link/20260109113430.2767264-1-randolph@andestech.com -(cherry picked from commit e9a5415adb209f86a05e55b850127ada82e070f1) -Signed-off-by: Han Gao ---- - .../pci/controller/dwc/pcie-designware-host.c | 74 ++++++++++++++----- - 1 file changed, 57 insertions(+), 17 deletions(-) - -diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c -index 48e4a887bb1b..993858fd0529 100644 ---- a/drivers/pci/controller/dwc/pcie-designware-host.c -+++ b/drivers/pci/controller/dwc/pcie-designware-host.c -@@ -887,29 +887,50 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) - - i = 0; - resource_list_for_each_entry(entry, &pp->bridge->windows) { -+ resource_size_t res_size; -+ - if (resource_type(entry->res) != IORESOURCE_MEM) - continue; - -- if (pci->num_ob_windows <= ++i) -+ if (pci->num_ob_windows <= i + 1) - break; - -- atu.index = i; - atu.type = PCIE_ATU_TYPE_MEM; - atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset; - atu.pci_addr = entry->res->start - entry->offset; - - /* Adjust iATU size if MSG TLP region was allocated before */ - if (pp->msg_res && pp->msg_res->parent == entry->res) -- atu.size = resource_size(entry->res) - -+ res_size = resource_size(entry->res) - - resource_size(pp->msg_res); - else -- atu.size = resource_size(entry->res); -+ res_size = resource_size(entry->res); -+ -+ while (res_size > 0) { -+ /* -+ * Return failure if we run out of windows in the -+ * middle. Otherwise, we would end up only partially -+ * mapping a single resource. -+ */ -+ if (pci->num_ob_windows <= ++i) { -+ dev_err(pci->dev, "Exhausted outbound windows for region: %pr\n", -+ entry->res); -+ return -ENOMEM; -+ } - -- ret = dw_pcie_prog_outbound_atu(pci, &atu); -- if (ret) { -- dev_err(pci->dev, "Failed to set MEM range %pr\n", -- entry->res); -- return ret; -+ atu.index = i; -+ atu.size = MIN(pci->region_limit + 1, res_size); -+ -+ ret = dw_pcie_prog_outbound_atu(pci, &atu); -+ if (ret) { -+ dev_err(pci->dev, "Failed to set MEM range %pr\n", -+ entry->res); -+ return ret; -+ } -+ -+ atu.parent_bus_addr += atu.size; -+ atu.pci_addr += atu.size; -+ res_size -= atu.size; - } - } - -@@ -947,20 +968,39 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) - - i = 0; - resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { -+ resource_size_t res_start, res_size, window_size; -+ - if (resource_type(entry->res) != IORESOURCE_MEM) - continue; - - if (pci->num_ib_windows <= i) - break; - -- ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, -- entry->res->start, -- entry->res->start - entry->offset, -- resource_size(entry->res)); -- if (ret) { -- dev_err(pci->dev, "Failed to set DMA range %pr\n", -- entry->res); -- return ret; -+ res_size = resource_size(entry->res); -+ res_start = entry->res->start; -+ while (res_size > 0) { -+ /* -+ * Return failure if we run out of windows in the -+ * middle. Otherwise, we would end up only partially -+ * mapping a single resource. -+ */ -+ if (pci->num_ib_windows <= i) { -+ dev_err(pci->dev, "Exhausted inbound windows for region: %pr\n", -+ entry->res); -+ return -ENOMEM; -+ } -+ -+ window_size = MIN(pci->region_limit + 1, res_size); -+ ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, res_start, -+ res_start - entry->offset, window_size); -+ if (ret) { -+ dev_err(pci->dev, "Failed to set DMA range %pr\n", -+ entry->res); -+ return ret; -+ } -+ -+ res_start += window_size; -+ res_size -= window_size; - } - } - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch b/SPECS/linux-lts-kmhv2/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch new file mode 100644 index 0000000000..666272aa6c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch @@ -0,0 +1,731 @@ +From 4fb7d19f2e7e5112722787c8f89b8ca56f6943be Mon Sep 17 00:00:00 2001 +From: Manikandan K Pillai +Date: Sat, 8 Nov 2025 22:02:58 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Move PCIe RP common functions to + a separate file + +Move the Cadence PCIe controller RP common functions into a separate file. +The common library functions are split from legacy PCIe RP controller +functions to a separate file. + +Signed-off-by: Manikandan K Pillai +[mani: removed the unused variable] +Signed-off-by: Manivannan Sadhasivam +Link: https://patch.msgid.link/20251108140305.1120117-4-hans.zhang@cixtech.com +(cherry picked from commit b80a7b4713c967479752ea4801eb1d1933093f58) +Signed-off-by: Han Gao +--- + drivers/pci/controller/cadence/Makefile | 10 +- + .../cadence/pcie-cadence-host-common.c | 288 ++++++++++++++++++ + .../cadence/pcie-cadence-host-common.h | 46 +++ + .../controller/cadence/pcie-cadence-host.c | 278 +---------------- + 4 files changed, 349 insertions(+), 273 deletions(-) + create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common.c + create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common.h + +diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile +index 5e23f8539ecc..91ffdbfd3aaa 100644 +--- a/drivers/pci/controller/cadence/Makefile ++++ b/drivers/pci/controller/cadence/Makefile +@@ -1,7 +1,11 @@ + # SPDX-License-Identifier: GPL-2.0 +-obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o +-obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o +-obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o ++pcie-cadence-mod-y := pcie-cadence.o ++pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o ++pcie-cadence-ep-mod-y := pcie-cadence-ep.o ++ ++obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o ++obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o ++obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o + obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o + obj-$(CONFIG_PCI_J721E) += pci-j721e.o + obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o +diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c +new file mode 100644 +index 000000000000..15415d7f35ee +--- /dev/null ++++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c +@@ -0,0 +1,288 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Cadence PCIe host controller library. ++ * ++ * Copyright (c) 2017 Cadence ++ * Author: Cyrille Pitchen ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-cadence.h" ++#include "pcie-cadence-host-common.h" ++ ++#define LINK_RETRAIN_TIMEOUT HZ ++ ++u64 bar_max_size[] = { ++ [RP_BAR0] = _ULL(128 * SZ_2G), ++ [RP_BAR1] = SZ_2G, ++ [RP_NO_BAR] = _BITULL(63), ++}; ++EXPORT_SYMBOL_GPL(bar_max_size); ++ ++int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) ++{ ++ u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; ++ unsigned long end_jiffies; ++ u16 lnk_stat; ++ ++ /* Wait for link training to complete. Exit after timeout. */ ++ end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; ++ do { ++ lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); ++ if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) ++ break; ++ usleep_range(0, 1000); ++ } while (time_before(jiffies, end_jiffies)); ++ ++ if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) ++ return 0; ++ ++ return -ETIMEDOUT; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_host_training_complete); ++ ++int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie, ++ cdns_pcie_linkup_func pcie_link_up) ++{ ++ struct device *dev = pcie->dev; ++ int retries; ++ ++ /* Check if the link is up or not */ ++ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { ++ if (pcie_link_up(pcie)) { ++ dev_info(dev, "Link up\n"); ++ return 0; ++ } ++ usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); ++ } ++ ++ return -ETIMEDOUT; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_host_wait_for_link); ++ ++int cdns_pcie_retrain(struct cdns_pcie *pcie, ++ cdns_pcie_linkup_func pcie_link_up) ++{ ++ u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; ++ u16 lnk_stat, lnk_ctl; ++ int ret = 0; ++ ++ /* ++ * Set retrain bit if current speed is 2.5 GB/s, ++ * but the PCIe root port support is > 2.5 GB/s. ++ */ ++ ++ lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + ++ PCI_EXP_LNKCAP)); ++ if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) ++ return ret; ++ ++ lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); ++ if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { ++ lnk_ctl = cdns_pcie_rp_readw(pcie, ++ pcie_cap_off + PCI_EXP_LNKCTL); ++ lnk_ctl |= PCI_EXP_LNKCTL_RL; ++ cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, ++ lnk_ctl); ++ ++ ret = cdns_pcie_host_training_complete(pcie); ++ if (ret) ++ return ret; ++ ++ ret = cdns_pcie_host_wait_for_link(pcie, pcie_link_up); ++ } ++ return ret; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_retrain); ++ ++int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, ++ cdns_pcie_linkup_func pcie_link_up) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ int ret; ++ ++ ret = cdns_pcie_host_wait_for_link(pcie, pcie_link_up); ++ ++ /* ++ * Retrain link for Gen2 training defect ++ * if quirk flag is set. ++ */ ++ if (!ret && rc->quirk_retrain_flag) ++ ret = cdns_pcie_retrain(pcie, pcie_link_up); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link); ++ ++enum cdns_pcie_rp_bar ++cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) ++{ ++ enum cdns_pcie_rp_bar bar, sel_bar; ++ ++ sel_bar = RP_BAR_UNDEFINED; ++ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { ++ if (!rc->avail_ib_bar[bar]) ++ continue; ++ ++ if (size <= bar_max_size[bar]) { ++ if (sel_bar == RP_BAR_UNDEFINED) { ++ sel_bar = bar; ++ continue; ++ } ++ ++ if (bar_max_size[bar] < bar_max_size[sel_bar]) ++ sel_bar = bar; ++ } ++ } ++ ++ return sel_bar; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_host_find_min_bar); ++ ++enum cdns_pcie_rp_bar ++cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) ++{ ++ enum cdns_pcie_rp_bar bar, sel_bar; ++ ++ sel_bar = RP_BAR_UNDEFINED; ++ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { ++ if (!rc->avail_ib_bar[bar]) ++ continue; ++ ++ if (size >= bar_max_size[bar]) { ++ if (sel_bar == RP_BAR_UNDEFINED) { ++ sel_bar = bar; ++ continue; ++ } ++ ++ if (bar_max_size[bar] > bar_max_size[sel_bar]) ++ sel_bar = bar; ++ } ++ } ++ ++ return sel_bar; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_host_find_max_bar); ++ ++int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, ++ const struct list_head *b) ++{ ++ struct resource_entry *entry1, *entry2; ++ ++ entry1 = container_of(a, struct resource_entry, node); ++ entry2 = container_of(b, struct resource_entry, node); ++ ++ return resource_size(entry2->res) - resource_size(entry1->res); ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_host_dma_ranges_cmp); ++ ++int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, ++ struct resource_entry *entry, ++ cdns_pcie_host_bar_ib_cfg pci_host_ib_config) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ struct device *dev = pcie->dev; ++ u64 cpu_addr, size, winsize; ++ enum cdns_pcie_rp_bar bar; ++ unsigned long flags; ++ int ret; ++ ++ cpu_addr = entry->res->start; ++ flags = entry->res->flags; ++ size = resource_size(entry->res); ++ ++ while (size > 0) { ++ /* ++ * Try to find a minimum BAR whose size is greater than ++ * or equal to the remaining resource_entry size. This will ++ * fail if the size of each of the available BARs is less than ++ * the remaining resource_entry size. ++ * ++ * If a minimum BAR is found, IB ATU will be configured and ++ * exited. ++ */ ++ bar = cdns_pcie_host_find_min_bar(rc, size); ++ if (bar != RP_BAR_UNDEFINED) { ++ ret = pci_host_ib_config(rc, bar, cpu_addr, size, flags); ++ if (ret) ++ dev_err(dev, "IB BAR: %d config failed\n", bar); ++ return ret; ++ } ++ ++ /* ++ * If the control reaches here, it would mean the remaining ++ * resource_entry size cannot be fitted in a single BAR. So we ++ * find a maximum BAR whose size is less than or equal to the ++ * remaining resource_entry size and split the resource entry ++ * so that part of resource entry is fitted inside the maximum ++ * BAR. The remaining size would be fitted during the next ++ * iteration of the loop. ++ * ++ * If a maximum BAR is not found, there is no way we can fit ++ * this resource_entry, so we error out. ++ */ ++ bar = cdns_pcie_host_find_max_bar(rc, size); ++ if (bar == RP_BAR_UNDEFINED) { ++ dev_err(dev, "No free BAR to map cpu_addr %llx\n", ++ cpu_addr); ++ return -EINVAL; ++ } ++ ++ winsize = bar_max_size[bar]; ++ ret = pci_host_ib_config(rc, bar, cpu_addr, winsize, flags); ++ if (ret) { ++ dev_err(dev, "IB BAR: %d config failed\n", bar); ++ return ret; ++ } ++ ++ size -= winsize; ++ cpu_addr += winsize; ++ } ++ ++ return 0; ++} ++ ++int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc, ++ cdns_pcie_host_bar_ib_cfg pci_host_ib_config) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ struct device *dev = pcie->dev; ++ struct device_node *np = dev->of_node; ++ struct pci_host_bridge *bridge; ++ struct resource_entry *entry; ++ u32 no_bar_nbits = 32; ++ int err; ++ ++ bridge = pci_host_bridge_from_priv(rc); ++ if (!bridge) ++ return -ENOMEM; ++ ++ if (list_empty(&bridge->dma_ranges)) { ++ of_property_read_u32(np, "cdns,no-bar-match-nbits", ++ &no_bar_nbits); ++ err = pci_host_ib_config(rc, RP_NO_BAR, 0x0, (u64)1 << no_bar_nbits, 0); ++ if (err) ++ dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); ++ return err; ++ } ++ ++ list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); ++ ++ resource_list_for_each_entry(entry, &bridge->dma_ranges) { ++ err = cdns_pcie_host_bar_config(rc, entry, pci_host_ib_config); ++ if (err) { ++ dev_err(dev, "Fail to configure IB using dma-ranges\n"); ++ return err; ++ } ++ } ++ ++ return 0; ++} ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Cadence PCIe host controller driver"); +diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.h b/drivers/pci/controller/cadence/pcie-cadence-host-common.h +new file mode 100644 +index 000000000000..fe7d4202a8b6 +--- /dev/null ++++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.h +@@ -0,0 +1,46 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Cadence PCIe Host controller driver. ++ * ++ * Copyright (c) 2017 Cadence ++ * Author: Cyrille Pitchen ++ */ ++#ifndef _PCIE_CADENCE_HOST_COMMON_H ++#define _PCIE_CADENCE_HOST_COMMON_H ++ ++#include ++#include ++ ++extern u64 bar_max_size[]; ++ ++typedef int (*cdns_pcie_host_bar_ib_cfg)(struct cdns_pcie_rc *, ++ enum cdns_pcie_rp_bar, ++ u64, ++ u64, ++ unsigned long); ++typedef bool (*cdns_pcie_linkup_func)(struct cdns_pcie *); ++ ++int cdns_pcie_host_training_complete(struct cdns_pcie *pcie); ++int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie, ++ cdns_pcie_linkup_func pcie_link_up); ++int cdns_pcie_retrain(struct cdns_pcie *pcie, cdns_pcie_linkup_func pcie_linkup_func); ++int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, ++ cdns_pcie_linkup_func pcie_link_up); ++enum cdns_pcie_rp_bar ++cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size); ++enum cdns_pcie_rp_bar ++cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size); ++int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, ++ const struct list_head *b); ++int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, ++ enum cdns_pcie_rp_bar bar, ++ u64 cpu_addr, ++ u64 size, ++ unsigned long flags); ++int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, ++ struct resource_entry *entry, ++ cdns_pcie_host_bar_ib_cfg pci_host_ib_config); ++int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc, ++ cdns_pcie_host_bar_ib_cfg pci_host_ib_config); ++ ++#endif /* _PCIE_CADENCE_HOST_COMMON_H */ +diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c +index fffd63d6665e..db3154c1eccb 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence-host.c ++++ b/drivers/pci/controller/cadence/pcie-cadence-host.c +@@ -12,14 +12,7 @@ + #include + + #include "pcie-cadence.h" +- +-#define LINK_RETRAIN_TIMEOUT HZ +- +-static u64 bar_max_size[] = { +- [RP_BAR0] = _ULL(128 * SZ_2G), +- [RP_BAR1] = SZ_2G, +- [RP_NO_BAR] = _BITULL(63), +-}; ++#include "pcie-cadence-host-common.h" + + static u8 bar_aperture_mask[] = { + [RP_BAR0] = 0x1F, +@@ -81,77 +74,6 @@ static struct pci_ops cdns_pcie_host_ops = { + .write = pci_generic_config_write, + }; + +-static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) +-{ +- u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; +- unsigned long end_jiffies; +- u16 lnk_stat; +- +- /* Wait for link training to complete. Exit after timeout. */ +- end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; +- do { +- lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); +- if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) +- break; +- usleep_range(0, 1000); +- } while (time_before(jiffies, end_jiffies)); +- +- if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) +- return 0; +- +- return -ETIMEDOUT; +-} +- +-static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +-{ +- struct device *dev = pcie->dev; +- int retries; +- +- /* Check if the link is up or not */ +- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { +- if (cdns_pcie_link_up(pcie)) { +- dev_info(dev, "Link up\n"); +- return 0; +- } +- usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); +- } +- +- return -ETIMEDOUT; +-} +- +-static int cdns_pcie_retrain(struct cdns_pcie *pcie) +-{ +- u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; +- u16 lnk_stat, lnk_ctl; +- int ret = 0; +- +- /* +- * Set retrain bit if current speed is 2.5 GB/s, +- * but the PCIe root port support is > 2.5 GB/s. +- */ +- +- lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + +- PCI_EXP_LNKCAP)); +- if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) +- return ret; +- +- lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); +- if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { +- lnk_ctl = cdns_pcie_rp_readw(pcie, +- pcie_cap_off + PCI_EXP_LNKCTL); +- lnk_ctl |= PCI_EXP_LNKCTL_RL; +- cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, +- lnk_ctl); +- +- ret = cdns_pcie_host_training_complete(pcie); +- if (ret) +- return ret; +- +- ret = cdns_pcie_host_wait_for_link(pcie); +- } +- return ret; +-} +- + static void cdns_pcie_host_disable_ptm_response(struct cdns_pcie *pcie) + { + u32 val; +@@ -168,23 +90,6 @@ static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie) + cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN); + } + +-static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) +-{ +- struct cdns_pcie *pcie = &rc->pcie; +- int ret; +- +- ret = cdns_pcie_host_wait_for_link(pcie); +- +- /* +- * Retrain link for Gen2 training defect +- * if quirk flag is set. +- */ +- if (!ret && rc->quirk_retrain_flag) +- ret = cdns_pcie_retrain(pcie); +- +- return ret; +-} +- + static void cdns_pcie_host_deinit_root_port(struct cdns_pcie_rc *rc) + { + struct cdns_pcie *pcie = &rc->pcie; +@@ -245,10 +150,11 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) + return 0; + } + +-static int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, +- enum cdns_pcie_rp_bar bar, +- u64 cpu_addr, u64 size, +- unsigned long flags) ++int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, ++ enum cdns_pcie_rp_bar bar, ++ u64 cpu_addr, ++ u64 size, ++ unsigned long flags) + { + struct cdns_pcie *pcie = &rc->pcie; + u32 addr0, addr1, aperture, value; +@@ -290,137 +196,6 @@ static int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, + return 0; + } + +-static enum cdns_pcie_rp_bar +-cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) +-{ +- enum cdns_pcie_rp_bar bar, sel_bar; +- +- sel_bar = RP_BAR_UNDEFINED; +- for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { +- if (!rc->avail_ib_bar[bar]) +- continue; +- +- if (size <= bar_max_size[bar]) { +- if (sel_bar == RP_BAR_UNDEFINED) { +- sel_bar = bar; +- continue; +- } +- +- if (bar_max_size[bar] < bar_max_size[sel_bar]) +- sel_bar = bar; +- } +- } +- +- return sel_bar; +-} +- +-static enum cdns_pcie_rp_bar +-cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) +-{ +- enum cdns_pcie_rp_bar bar, sel_bar; +- +- sel_bar = RP_BAR_UNDEFINED; +- for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { +- if (!rc->avail_ib_bar[bar]) +- continue; +- +- if (size >= bar_max_size[bar]) { +- if (sel_bar == RP_BAR_UNDEFINED) { +- sel_bar = bar; +- continue; +- } +- +- if (bar_max_size[bar] > bar_max_size[sel_bar]) +- sel_bar = bar; +- } +- } +- +- return sel_bar; +-} +- +-static int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, +- struct resource_entry *entry) +-{ +- u64 cpu_addr, pci_addr, size, winsize; +- struct cdns_pcie *pcie = &rc->pcie; +- struct device *dev = pcie->dev; +- enum cdns_pcie_rp_bar bar; +- unsigned long flags; +- int ret; +- +- cpu_addr = entry->res->start; +- pci_addr = entry->res->start - entry->offset; +- flags = entry->res->flags; +- size = resource_size(entry->res); +- +- if (entry->offset) { +- dev_err(dev, "PCI addr: %llx must be equal to CPU addr: %llx\n", +- pci_addr, cpu_addr); +- return -EINVAL; +- } +- +- while (size > 0) { +- /* +- * Try to find a minimum BAR whose size is greater than +- * or equal to the remaining resource_entry size. This will +- * fail if the size of each of the available BARs is less than +- * the remaining resource_entry size. +- * If a minimum BAR is found, IB ATU will be configured and +- * exited. +- */ +- bar = cdns_pcie_host_find_min_bar(rc, size); +- if (bar != RP_BAR_UNDEFINED) { +- ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, +- size, flags); +- if (ret) +- dev_err(dev, "IB BAR: %d config failed\n", bar); +- return ret; +- } +- +- /* +- * If the control reaches here, it would mean the remaining +- * resource_entry size cannot be fitted in a single BAR. So we +- * find a maximum BAR whose size is less than or equal to the +- * remaining resource_entry size and split the resource entry +- * so that part of resource entry is fitted inside the maximum +- * BAR. The remaining size would be fitted during the next +- * iteration of the loop. +- * If a maximum BAR is not found, there is no way we can fit +- * this resource_entry, so we error out. +- */ +- bar = cdns_pcie_host_find_max_bar(rc, size); +- if (bar == RP_BAR_UNDEFINED) { +- dev_err(dev, "No free BAR to map cpu_addr %llx\n", +- cpu_addr); +- return -EINVAL; +- } +- +- winsize = bar_max_size[bar]; +- ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, winsize, +- flags); +- if (ret) { +- dev_err(dev, "IB BAR: %d config failed\n", bar); +- return ret; +- } +- +- size -= winsize; +- cpu_addr += winsize; +- } +- +- return 0; +-} +- +-static int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, +- const struct list_head *b) +-{ +- struct resource_entry *entry1, *entry2; +- +- entry1 = container_of(a, struct resource_entry, node); +- entry2 = container_of(b, struct resource_entry, node); +- +- return resource_size(entry2->res) - resource_size(entry1->res); +-} +- + static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) + { + struct cdns_pcie *pcie = &rc->pcie; +@@ -447,43 +222,6 @@ static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) + } + } + +-static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc) +-{ +- struct cdns_pcie *pcie = &rc->pcie; +- struct device *dev = pcie->dev; +- struct device_node *np = dev->of_node; +- struct pci_host_bridge *bridge; +- struct resource_entry *entry; +- u32 no_bar_nbits = 32; +- int err; +- +- bridge = pci_host_bridge_from_priv(rc); +- if (!bridge) +- return -ENOMEM; +- +- if (list_empty(&bridge->dma_ranges)) { +- of_property_read_u32(np, "cdns,no-bar-match-nbits", +- &no_bar_nbits); +- err = cdns_pcie_host_bar_ib_config(rc, RP_NO_BAR, 0x0, +- (u64)1 << no_bar_nbits, 0); +- if (err) +- dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); +- return err; +- } +- +- list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); +- +- resource_list_for_each_entry(entry, &bridge->dma_ranges) { +- err = cdns_pcie_host_bar_config(rc, entry); +- if (err) { +- dev_err(dev, "Fail to configure IB using dma-ranges\n"); +- return err; +- } +- } +- +- return 0; +-} +- + static void cdns_pcie_host_deinit_address_translation(struct cdns_pcie_rc *rc) + { + struct cdns_pcie *pcie = &rc->pcie; +@@ -561,7 +299,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) + r++; + } + +- return cdns_pcie_host_map_dma_ranges(rc); ++ return cdns_pcie_host_map_dma_ranges(rc, cdns_pcie_host_bar_ib_config); + } + + static void cdns_pcie_host_deinit(struct cdns_pcie_rc *rc) +@@ -607,7 +345,7 @@ int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) + return ret; + } + +- ret = cdns_pcie_host_start_link(rc); ++ ret = cdns_pcie_host_start_link(rc, cdns_pcie_link_up); + if (ret) + dev_dbg(dev, "PCIe link never came up\n"); + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0145-UPSTREAM-pinctrl-th1520-Fix-typo.patch b/SPECS/linux-lts-kmhv2/0145-UPSTREAM-pinctrl-th1520-Fix-typo.patch deleted file mode 100644 index 84781c827a..0000000000 --- a/SPECS/linux-lts-kmhv2/0145-UPSTREAM-pinctrl-th1520-Fix-typo.patch +++ /dev/null @@ -1,32 +0,0 @@ -From d007ff0d047d973067f05a3f9898c1c1822af330 Mon Sep 17 00:00:00 2001 -From: Thomas Gerner -Date: Tue, 20 Jan 2026 09:59:26 +0100 -Subject: [PATCH 145/467] UPSTREAM: pinctrl: th1520: Fix typo - -This fixes a simple typo in the TH1520 SPI0 for group3 pins: -QSPI0 is misspelled QSPI1. - -Signed-off-by: Thomas Gerner -Signed-off-by: Linus Walleij -(cherry picked from commit 304c3ebcaff36560d76e3030ba0839e629635f47) -Signed-off-by: Han Gao ---- - drivers/pinctrl/pinctrl-th1520.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c -index e641bad6728c..83e9c9f77370 100644 ---- a/drivers/pinctrl/pinctrl-th1520.c -+++ b/drivers/pinctrl/pinctrl-th1520.c -@@ -287,7 +287,7 @@ static const struct pinctrl_pin_desc th1520_group3_pins[] = { - TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0), - TH1520_PAD(6, QSPI0_D1_MISO, QSPI, PWM, I2S, GPIO, ____, ____, 0), - TH1520_PAD(7, QSPI0_D2_WP, QSPI, PWM, I2S, GPIO, ____, ____, 0), -- TH1520_PAD(8, QSPI1_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0), -+ TH1520_PAD(8, QSPI0_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0), - TH1520_PAD(9, I2C2_SCL, I2C, UART, ____, GPIO, ____, ____, 0), - TH1520_PAD(10, I2C2_SDA, I2C, UART, ____, GPIO, ____, ____, 0), - TH1520_PAD(11, I2C3_SCL, I2C, ____, ____, GPIO, ____, ____, 0), --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0146-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch b/SPECS/linux-lts-kmhv2/0146-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch deleted file mode 100644 index e1d681e245..0000000000 --- a/SPECS/linux-lts-kmhv2/0146-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch +++ /dev/null @@ -1,73 +0,0 @@ -From cf8e9527657f4fc6aa823772be5089f8172402c7 Mon Sep 17 00:00:00 2001 -From: Manikandan K Pillai -Date: Sat, 8 Nov 2025 22:02:56 +0800 -Subject: [PATCH 146/467] UPSTREAM: PCI: cadence: Add module support for - platform controller driver - -Add support for building PCI cadence platforms as a module. - -Signed-off-by: Manikandan K Pillai -Signed-off-by: Manivannan Sadhasivam -Link: https://patch.msgid.link/20251108140305.1120117-2-hans.zhang@cixtech.com -(cherry picked from commit 611627a4e5e4af7b96aab4f10d130f6a8a615020) -Signed-off-by: Han Gao ---- - drivers/pci/controller/cadence/Kconfig | 6 +++--- - drivers/pci/controller/cadence/pcie-cadence-plat.c | 5 ++++- - drivers/pci/controller/cadence/pcie-cadence.c | 1 + - 3 files changed, 8 insertions(+), 4 deletions(-) - -diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig -index 02a639e55fd8..0b96499ae354 100644 ---- a/drivers/pci/controller/cadence/Kconfig -+++ b/drivers/pci/controller/cadence/Kconfig -@@ -19,10 +19,10 @@ config PCIE_CADENCE_EP - select PCIE_CADENCE - - config PCIE_CADENCE_PLAT -- bool -+ tristate - - config PCIE_CADENCE_PLAT_HOST -- bool "Cadence platform PCIe controller (host mode)" -+ tristate "Cadence platform PCIe controller (host mode)" - depends on OF - select PCIE_CADENCE_HOST - select PCIE_CADENCE_PLAT -@@ -32,7 +32,7 @@ config PCIE_CADENCE_PLAT_HOST - vendors SoCs. - - config PCIE_CADENCE_PLAT_EP -- bool "Cadence platform PCIe controller (endpoint mode)" -+ tristate "Cadence platform PCIe controller (endpoint mode)" - depends on OF - depends on PCI_ENDPOINT - select PCIE_CADENCE_EP -diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c -index 0456845dabb9..ebd5c3afdfcd 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence-plat.c -+++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c -@@ -177,4 +177,7 @@ static struct platform_driver cdns_plat_pcie_driver = { - .probe = cdns_plat_pcie_probe, - .shutdown = cdns_plat_pcie_shutdown, - }; --builtin_platform_driver(cdns_plat_pcie_driver); -+module_platform_driver(cdns_plat_pcie_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Cadence PCIe controller platform driver"); -diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c -index d614452861f7..fb88a7ade412 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence.c -+++ b/drivers/pci/controller/cadence/pcie-cadence.c -@@ -293,6 +293,7 @@ const struct dev_pm_ops cdns_pcie_pm_ops = { - NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, - cdns_pcie_resume_noirq) - }; -+EXPORT_SYMBOL_GPL(cdns_pcie_pm_ops); - - MODULE_LICENSE("GPL"); - MODULE_DESCRIPTION("Cadence PCIe controller driver"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch b/SPECS/linux-lts-kmhv2/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch new file mode 100644 index 0000000000..c0c607ce23 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch @@ -0,0 +1,1127 @@ +From 169a3b6c0054a1a90e9a56316ce2530a6e1d21ad Mon Sep 17 00:00:00 2001 +From: Manikandan K Pillai +Date: Sat, 8 Nov 2025 22:02:59 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Add support for High Perf + Architecture (HPA) controller + +Add support for Cadence PCIe RP configuration for High Performance +Architecture (HPA) controllers. The Cadence High Performance controllers +are the latest PCIe controllers that have support for DMA, optional IDE +and updated register set. Add a common library for High Performance +Architecture (HPA) PCIe controllers. + +Signed-off-by: Manikandan K Pillai +Signed-off-by: Manivannan Sadhasivam +[bhelgaas: squash https://lore.kernel.org/r/20251120093518.2760492-1-jiapeng.chong@linux.alibaba.com, +squash https://lore.kernel.org/all/52abaad8-a43e-4e29-93d7-86a3245692c3@cixtech.com/] +Signed-off-by: Bjorn Helgaas +Link: https://patch.msgid.link/20251108140305.1120117-5-hans.zhang@cixtech.com +(cherry picked from commit 8babd8afe58a65c8d3cb9b5a6a8d24d4f93033ab) +Signed-off-by: Han Gao +--- + drivers/pci/controller/cadence/Makefile | 4 +- + .../cadence/pcie-cadence-host-hpa.c | 368 ++++++++++++++++++ + .../cadence/pcie-cadence-hpa-regs.h | 193 +++++++++ + .../pci/controller/cadence/pcie-cadence-hpa.c | 167 ++++++++ + .../controller/cadence/pcie-cadence-plat.c | 4 - + drivers/pci/controller/cadence/pcie-cadence.c | 11 + + drivers/pci/controller/cadence/pcie-cadence.h | 187 ++++++++- + 7 files changed, 913 insertions(+), 21 deletions(-) + create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-hpa.c + create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h + create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa.c + +diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile +index 91ffdbfd3aaa..30189045a166 100644 +--- a/drivers/pci/controller/cadence/Makefile ++++ b/drivers/pci/controller/cadence/Makefile +@@ -1,6 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0 +-pcie-cadence-mod-y := pcie-cadence.o +-pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o ++pcie-cadence-mod-y := pcie-cadence-hpa.o pcie-cadence.o ++pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o pcie-cadence-host-hpa.o + pcie-cadence-ep-mod-y := pcie-cadence-ep.o + + obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o +diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c +new file mode 100644 +index 000000000000..0f540bed58e8 +--- /dev/null ++++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c +@@ -0,0 +1,368 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Cadence PCIe host controller driver. ++ * ++ * Copyright (c) 2024, Cadence Design Systems ++ * Author: Manikandan K Pillai ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-cadence.h" ++#include "pcie-cadence-host-common.h" ++ ++static u8 bar_aperture_mask[] = { ++ [RP_BAR0] = 0x3F, ++ [RP_BAR1] = 0x3F, ++}; ++ ++void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, ++ int where) ++{ ++ struct pci_host_bridge *bridge = pci_find_host_bridge(bus); ++ struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); ++ struct cdns_pcie *pcie = &rc->pcie; ++ unsigned int busn = bus->number; ++ u32 addr0, desc0, desc1, ctrl0; ++ u32 regval; ++ ++ if (pci_is_root_bus(bus)) { ++ /* ++ * Only the root port (devfn == 0) is connected to this bus. ++ * All other PCI devices are behind some bridge hence on another ++ * bus. ++ */ ++ if (devfn) ++ return NULL; ++ ++ return pcie->reg_base + (where & 0xfff); ++ } ++ ++ /* Clear AXI link-down status */ ++ regval = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN, ++ (regval & ~GENMASK(0, 0))); ++ ++ /* Update Output registers for AXI region 0 */ ++ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(12) | ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) | ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(busn); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), addr0); ++ ++ desc1 = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0)); ++ desc1 &= ~CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK; ++ desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); ++ ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; ++ ++ if (busn == bridge->busnr + 1) ++ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0; ++ else ++ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1; ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), desc0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), ctrl0); ++ ++ return rc->cfg_base + (where & 0xfff); ++} ++ ++static struct pci_ops cdns_pcie_hpa_host_ops = { ++ .map_bus = cdns_pci_hpa_map_bus, ++ .read = pci_generic_config_read, ++ .write = pci_generic_config_write, ++}; ++ ++static void cdns_pcie_hpa_host_enable_ptm_response(struct cdns_pcie *pcie) ++{ ++ u32 val; ++ ++ val = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL, ++ val | CDNS_PCIE_HPA_LM_PTM_CTRL_PTMRSEN); ++} ++ ++static int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc, ++ enum cdns_pcie_rp_bar bar, ++ u64 cpu_addr, u64 size, ++ unsigned long flags) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ u32 addr0, addr1, aperture, value; ++ ++ if (!rc->avail_ib_bar[bar]) ++ return -ENODEV; ++ ++ rc->avail_ib_bar[bar] = false; ++ ++ aperture = ilog2(size); ++ if (bar == RP_NO_BAR) { ++ addr0 = CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(aperture) | ++ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); ++ addr1 = upper_32_bits(cpu_addr); ++ } else { ++ addr0 = lower_32_bits(cpu_addr); ++ addr1 = upper_32_bits(cpu_addr); ++ } ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, ++ CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar), addr0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, ++ CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar), addr1); ++ ++ if (bar == RP_NO_BAR) ++ bar = (enum cdns_pcie_rp_bar)BAR_0; ++ ++ value = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_BAR_CFG); ++ value &= ~(HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) | ++ HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) | ++ HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) | ++ HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) | ++ HPA_LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 7)); ++ if (size + cpu_addr >= SZ_4G) { ++ value |= HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar); ++ if ((flags & IORESOURCE_PREFETCH)) ++ value |= HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar); ++ } else { ++ value |= HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar); ++ if ((flags & IORESOURCE_PREFETCH)) ++ value |= HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar); ++ } ++ ++ value |= HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_BAR_CFG, value); ++ ++ return 0; ++} ++ ++static int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ u32 value, ctrl; ++ ++ /* ++ * Set the root port BAR configuration register: ++ * - disable both BAR0 and BAR1 ++ * - enable Prefetchable Memory Base and Limit registers in type 1 ++ * config space (64 bits) ++ * - enable IO Base and Limit registers in type 1 config ++ * space (32 bits) ++ */ ++ ++ ctrl = CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED; ++ value = CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) | ++ CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) | ++ CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE | ++ CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS | ++ CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE | ++ CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS; ++ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, ++ CDNS_PCIE_HPA_LM_RC_BAR_CFG, value); ++ ++ if (rc->vendor_id != 0xffff) ++ cdns_pcie_hpa_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id); ++ ++ if (rc->device_id != 0xffff) ++ cdns_pcie_hpa_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); ++ ++ cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_REVISION, 0); ++ cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_PROG, 0); ++ cdns_pcie_hpa_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); ++ ++ /* Enable bus mastering */ ++ value = cdns_pcie_hpa_readl(pcie, REG_BANK_RP, PCI_COMMAND); ++ value |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_RP, PCI_COMMAND, value); ++ return 0; ++} ++ ++static void cdns_pcie_hpa_create_region_for_cfg(struct cdns_pcie_rc *rc) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc); ++ struct resource *cfg_res = rc->cfg_res; ++ struct resource_entry *entry; ++ u64 cpu_addr = cfg_res->start; ++ u32 addr0, addr1, desc1; ++ int busnr = 0; ++ ++ entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); ++ if (entry) ++ busnr = entry->res->start; ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_TAG_MANAGEMENT, 0x01000000); ++ /* ++ * Reserve region 0 for PCI configure space accesses: ++ * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by ++ * cdns_pci_map_bus(), other region registers are set here once for all ++ */ ++ desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), 0x0); ++ /* Type-1 CFG */ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), 0x05000000); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); ++ ++ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(12) | ++ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); ++ addr1 = upper_32_bits(cpu_addr); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), addr0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), addr1); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), 0x06000000); ++} ++ ++static int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc *rc) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc); ++ struct resource_entry *entry; ++ int r = 0, busnr = 0; ++ ++ if (!rc->ecam_supported) ++ cdns_pcie_hpa_create_region_for_cfg(rc); ++ ++ entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); ++ if (entry) ++ busnr = entry->res->start; ++ ++ r++; ++ if (pcie->msg_res) { ++ cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, busnr, 0, r, ++ pcie->msg_res->start); ++ ++ r++; ++ } ++ resource_list_for_each_entry(entry, &bridge->windows) { ++ struct resource *res = entry->res; ++ u64 pci_addr = res->start - entry->offset; ++ ++ if (resource_type(res) == IORESOURCE_IO) ++ cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, ++ true, ++ pci_pio_to_address(res->start), ++ pci_addr, ++ resource_size(res)); ++ else ++ cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, ++ false, ++ res->start, ++ pci_addr, ++ resource_size(res)); ++ ++ r++; ++ } ++ ++ if (rc->no_inbound_map) ++ return 0; ++ else ++ return cdns_pcie_host_map_dma_ranges(rc, cdns_pcie_hpa_host_bar_ib_config); ++} ++ ++static int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc) ++{ ++ int err; ++ ++ err = cdns_pcie_hpa_host_init_root_port(rc); ++ if (err) ++ return err; ++ ++ return cdns_pcie_hpa_host_init_address_translation(rc); ++} ++ ++int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ struct device *dev = rc->pcie.dev; ++ int ret; ++ ++ if (rc->quirk_detect_quiet_flag) ++ cdns_pcie_hpa_detect_quiet_min_delay_set(&rc->pcie); ++ ++ cdns_pcie_hpa_host_enable_ptm_response(pcie); ++ ++ ret = cdns_pcie_start_link(pcie); ++ if (ret) { ++ dev_err(dev, "Failed to start link\n"); ++ return ret; ++ } ++ ++ ret = cdns_pcie_host_wait_for_link(pcie, cdns_pcie_hpa_link_up); ++ if (ret) ++ dev_dbg(dev, "PCIe link never came up\n"); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup); ++ ++int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) ++{ ++ struct device *dev = rc->pcie.dev; ++ struct platform_device *pdev = to_platform_device(dev); ++ struct pci_host_bridge *bridge; ++ enum cdns_pcie_rp_bar bar; ++ struct cdns_pcie *pcie; ++ struct resource *res; ++ int ret; ++ ++ bridge = pci_host_bridge_from_priv(rc); ++ if (!bridge) ++ return -ENOMEM; ++ ++ pcie = &rc->pcie; ++ pcie->is_rc = true; ++ ++ if (!pcie->reg_base) { ++ pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg"); ++ if (IS_ERR(pcie->reg_base)) { ++ dev_err(dev, "missing \"reg\"\n"); ++ return PTR_ERR(pcie->reg_base); ++ } ++ } ++ ++ /* ECAM config space is remapped at glue layer */ ++ if (!rc->cfg_base) { ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); ++ rc->cfg_base = devm_pci_remap_cfg_resource(dev, res); ++ if (IS_ERR(rc->cfg_base)) ++ return PTR_ERR(rc->cfg_base); ++ rc->cfg_res = res; ++ } ++ ++ /* Put EROM Bar aperture to 0 */ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_EROM, 0x0); ++ ++ ret = cdns_pcie_hpa_host_link_setup(rc); ++ if (ret) ++ return ret; ++ ++ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) ++ rc->avail_ib_bar[bar] = true; ++ ++ ret = cdns_pcie_hpa_host_init(rc); ++ if (ret) ++ return ret; ++ ++ if (!bridge->ops) ++ bridge->ops = &cdns_pcie_hpa_host_ops; ++ ++ return pci_host_probe(bridge); ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_setup); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Cadence PCIe host controller driver"); +diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h +new file mode 100644 +index 000000000000..026e131600de +--- /dev/null ++++ b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h +@@ -0,0 +1,193 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Cadence PCIe controller driver. ++ * ++ * Copyright (c) 2024, Cadence Design Systems ++ * Author: Manikandan K Pillai ++ */ ++#ifndef _PCIE_CADENCE_HPA_REGS_H ++#define _PCIE_CADENCE_HPA_REGS_H ++ ++#include ++#include ++#include ++#include ++#include ++ ++/* High Performance Architecture (HPA) PCIe controller registers */ ++#define CDNS_PCIE_HPA_IP_REG_BANK 0x01000000 ++#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x01003C00 ++#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0x02020000 ++ ++/* Address Translation Registers */ ++#define CDNS_PCIE_HPA_AXI_SLAVE 0x03000000 ++#define CDNS_PCIE_HPA_AXI_MASTER 0x03002000 ++ ++/* Root Port register base address */ ++#define CDNS_PCIE_HPA_RP_BASE 0x0 ++ ++#define CDNS_PCIE_HPA_LM_ID 0x1420 ++ ++/* Endpoint Function BARs */ ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \ ++ (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \ ++ CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn)) ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) (0x4000 * (pfn)) ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) ((0x4000 * (pfn)) + 0x04) ++#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \ ++ (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \ ++ CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn)) ++#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) ((0x4000 * (vfn)) + 0x08) ++#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) ((0x4000 * (vfn)) + 0x0C) ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \ ++ (GENMASK(5, 0) << (0x4 + (f) * 10)) ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ ++ (((a) << (4 + ((b) * 10))) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))) ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \ ++ (GENMASK(3, 0) << ((f) * 10)) ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ ++ (((c) << ((b) * 10)) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))) ++ ++/* Endpoint Function Configuration Register */ ++#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG 0x02C0 ++ ++/* Root Complex BAR Configuration Register */ ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG 0x14 ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(9, 4) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ ++ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK, a) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(3, 0) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \ ++ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(19, 14) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ ++ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK, a) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(13, 10) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \ ++ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c) ++ ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(20) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(21) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE BIT(22) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS BIT(23) ++ ++/* BAR control values applicable to both Endpoint Function and Root Complex */ ++#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED 0x0 ++#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS 0x3 ++#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS 0x1 ++#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x9 ++#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS 0x5 ++#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0xD ++ ++#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ ++ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10)) ++#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ ++ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10)) ++#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ ++ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10)) ++#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ ++ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10)) ++#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ ++ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10)) ++#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ ++ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10)) ++#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture) \ ++ (((aperture) - 7) << (((bar) * 10) + 4)) ++ ++#define CDNS_PCIE_HPA_LM_PTM_CTRL 0x0520 ++#define CDNS_PCIE_HPA_LM_PTM_CTRL_PTMRSEN BIT(17) ++ ++/* Root Port Registers PCI config space for root port function */ ++#define CDNS_PCIE_HPA_RP_CAP_OFFSET 0xC0 ++ ++/* Region r Outbound AXI to PCIe Address Translation Register 0 */ ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) (0x1010 + ((r) & 0x1F) * 0x0080) ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ ++ (((nbits) - 1) & CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(23, 16) ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK, devfn) ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(31, 24) ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK, bus) ++ ++/* Region r Outbound AXI to PCIe Address Translation Register 1 */ ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) (0x1014 + ((r) & 0x1F) * 0x0080) ++ ++/* Region r Outbound PCIe Descriptor Register */ ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) (0x1008 + ((r) & 0x1F) * 0x0080) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(28, 24) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10) ++ ++/* Region r Outbound PCIe Descriptor Register */ ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) (0x100C + ((r) & 0x1F) * 0x0080) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK GENMASK(31, 24) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK, bus) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK GENMASK(23, 16) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK, devfn) ++ ++#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) (0x1018 + ((r) & 0x1F) * 0x0080) ++#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26) ++#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25) ++ ++/* Region r AXI Region Base Address Register 0 */ ++#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) (0x1000 + ((r) & 0x1F) * 0x0080) ++#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) ++#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ ++ (((nbits) - 1) & CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) ++ ++/* Region r AXI Region Base Address Register 1 */ ++#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) (0x1004 + ((r) & 0x1F) * 0x0080) ++ ++/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ ++#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) (((bar) * 0x0008)) ++#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) ++#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ ++ (((nbits) - 1) & CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK) ++#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) (0x04 + ((bar) * 0x0008)) ++ ++/* AXI link down register */ ++#define CDNS_PCIE_HPA_AT_LINKDOWN 0x04 ++ ++/* ++ * Physical Layer Configuration Register 0 ++ * This register contains the parameters required for functional setup ++ * of Physical Layer. ++ */ ++#define CDNS_PCIE_HPA_PHY_LAYER_CFG0 0x0400 ++#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK GENMASK(26, 24) ++#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \ ++ FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK, delay) ++#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK GENMASK(27, 27) ++ ++#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0 0x0420 ++ ++#define CDNS_PCIE_HPA_RP_MAX_IB 0x3 ++#define CDNS_PCIE_HPA_MAX_OB 15 ++ ++/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ ++#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) (((fn) * 0x0080) + ((bar) * 0x0008)) ++#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) (0x4 + ((fn) * 0x0080) + ((bar) * 0x0008)) ++ ++/* Miscellaneous offsets definitions */ ++#define CDNS_PCIE_HPA_TAG_MANAGEMENT 0x0 ++#define CDNS_PCIE_HPA_SLAVE_RESP 0x100 ++ ++#define I_ROOT_PORT_REQ_ID_REG 0x141c ++#define LM_HAL_SBSA_CTRL 0x1170 ++ ++#define I_PCIE_BUS_NUMBERS (CDNS_PCIE_HPA_RP_BASE + 0x18) ++#define CDNS_PCIE_EROM 0x18 ++#endif /* _PCIE_CADENCE_HPA_REGS_H */ +diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-hpa.c +new file mode 100644 +index 000000000000..f60a16938265 +--- /dev/null ++++ b/drivers/pci/controller/cadence/pcie-cadence-hpa.c +@@ -0,0 +1,167 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Cadence PCIe controller driver. ++ * ++ * Copyright (c) 2024, Cadence Design Systems ++ * Author: Manikandan K Pillai ++ */ ++#include ++#include ++ ++#include "pcie-cadence.h" ++ ++bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie) ++{ ++ u32 pl_reg_val; ++ ++ pl_reg_val = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_DBG_STS_REG0); ++ if (pl_reg_val & GENMASK(0, 0)) ++ return true; ++ return false; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_hpa_link_up); ++ ++void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie) ++{ ++ u32 delay = 0x3; ++ u32 ltssm_control_cap; ++ ++ /* Set the LTSSM Detect Quiet state min. delay to 2ms */ ++ ltssm_control_cap = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, ++ CDNS_PCIE_HPA_PHY_LAYER_CFG0); ++ ltssm_control_cap = ((ltssm_control_cap & ++ ~CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK) | ++ CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay)); ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, ++ CDNS_PCIE_HPA_PHY_LAYER_CFG0, ltssm_control_cap); ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_hpa_detect_quiet_min_delay_set); ++ ++void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, ++ u32 r, bool is_io, ++ u64 cpu_addr, u64 pci_addr, size_t size) ++{ ++ /* ++ * roundup_pow_of_two() returns an unsigned long, which is not suited ++ * for 64bit values ++ */ ++ u64 sz = 1ULL << fls64(size - 1); ++ int nbits = ilog2(sz); ++ u32 addr0, addr1, desc0, desc1, ctrl0; ++ ++ if (nbits < 8) ++ nbits = 8; ++ ++ /* Set the PCI address */ ++ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) | ++ (lower_32_bits(pci_addr) & GENMASK(31, 8)); ++ addr1 = upper_32_bits(pci_addr); ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), addr0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), addr1); ++ ++ /* Set the PCIe header descriptor */ ++ if (is_io) ++ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO; ++ else ++ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM; ++ desc1 = 0; ++ ctrl0 = 0; ++ ++ /* ++ * Whether Bit [26] is set or not inside DESC0 register of the outbound ++ * PCIe descriptor, the PCI function number must be set into ++ * Bits [31:24] of DESC1 anyway. ++ * ++ * In Root Complex mode, the function number is always 0 but in Endpoint ++ * mode, the PCIe controller may support more than one function. This ++ * function number needs to be set properly into the outbound PCIe ++ * descriptor. ++ * ++ * Besides, setting Bit [26] is mandatory when in Root Complex mode: ++ * then the driver must provide the bus, resp. device, number in ++ * Bits [31:24] of DESC1, resp. Bits[23:16] of DESC0. Like the function ++ * number, the device number is always 0 in Root Complex mode. ++ * ++ * However when in Endpoint mode, we can clear Bit [26] of DESC0, hence ++ * the PCIe controller will use the captured values for the bus and ++ * device numbers. ++ */ ++ if (pcie->is_rc) { ++ /* The device and function numbers are always 0 */ ++ desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); ++ ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; ++ } else { ++ /* ++ * Use captured values for bus and device numbers but still ++ * need to set the function number ++ */ ++ desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); ++ } ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); ++ ++ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | ++ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); ++ addr1 = upper_32_bits(cpu_addr); ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region); ++ ++void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, ++ u8 busnr, u8 fn, ++ u32 r, u64 cpu_addr) ++{ ++ u32 addr0, addr1, desc0, desc1, ctrl0; ++ ++ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG; ++ desc1 = 0; ++ ctrl0 = 0; ++ ++ /* See cdns_pcie_set_outbound_region() comments above */ ++ if (pcie->is_rc) { ++ desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); ++ ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; ++ } else { ++ desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); ++ } ++ ++ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(17) | ++ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); ++ addr1 = upper_32_bits(cpu_addr); ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region_for_normal_msg); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Cadence PCIe controller driver"); +diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c +index ebd5c3afdfcd..b067a3296dd3 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence-plat.c ++++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c +@@ -22,10 +22,6 @@ struct cdns_plat_pcie { + struct cdns_pcie *pcie; + }; + +-struct cdns_plat_pcie_of_data { +- bool is_rc; +-}; +- + static const struct of_device_id cdns_plat_pcie_of_match[]; + + static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) +diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c +index fb88a7ade412..a1eada56edba 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence.c ++++ b/drivers/pci/controller/cadence/pcie-cadence.c +@@ -23,6 +23,17 @@ u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) + } + EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability); + ++bool cdns_pcie_linkup(struct cdns_pcie *pcie) ++{ ++ u32 pl_reg_val; ++ ++ pl_reg_val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE); ++ if (pl_reg_val & GENMASK(0, 0)) ++ return true; ++ return false; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_linkup); ++ + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) + { + u32 delay = 0x3; +diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h +index 23aa64df1980..277f3706a4f4 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence.h ++++ b/drivers/pci/controller/cadence/pcie-cadence.h +@@ -12,6 +12,7 @@ + #include + #include + #include "pcie-cadence-lga-regs.h" ++#include "pcie-cadence-hpa-regs.h" + + enum cdns_pcie_rp_bar { + RP_BAR_UNDEFINED = -1, +@@ -26,18 +27,57 @@ struct cdns_pcie_rp_ib_bar { + }; + + struct cdns_pcie; ++struct cdns_pcie_rc; ++ ++enum cdns_pcie_reg_bank { ++ REG_BANK_RP, ++ REG_BANK_IP_REG, ++ REG_BANK_IP_CFG_CTRL_REG, ++ REG_BANK_AXI_MASTER_COMMON, ++ REG_BANK_AXI_MASTER, ++ REG_BANK_AXI_SLAVE, ++ REG_BANK_AXI_HLS, ++ REG_BANK_AXI_RAS, ++ REG_BANK_AXI_DTI, ++ REG_BANKS_MAX, ++}; + + struct cdns_pcie_ops { +- int (*start_link)(struct cdns_pcie *pcie); +- void (*stop_link)(struct cdns_pcie *pcie); +- bool (*link_up)(struct cdns_pcie *pcie); ++ int (*start_link)(struct cdns_pcie *pcie); ++ void (*stop_link)(struct cdns_pcie *pcie); ++ bool (*link_up)(struct cdns_pcie *pcie); + u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); + }; + ++/** ++ * struct cdns_plat_pcie_of_data - Register bank offset for a platform ++ * @is_rc: controller is a RC ++ * @ip_reg_bank_offset: ip register bank start offset ++ * @ip_cfg_ctrl_reg_offset: ip config control register start offset ++ * @axi_mstr_common_offset: AXI master common register start offset ++ * @axi_slave_offset: AXI slave start offset ++ * @axi_master_offset: AXI master start offset ++ * @axi_hls_offset: AXI HLS offset start ++ * @axi_ras_offset: AXI RAS offset ++ * @axi_dti_offset: AXI DTI offset ++ */ ++struct cdns_plat_pcie_of_data { ++ u32 is_rc:1; ++ u32 ip_reg_bank_offset; ++ u32 ip_cfg_ctrl_reg_offset; ++ u32 axi_mstr_common_offset; ++ u32 axi_slave_offset; ++ u32 axi_master_offset; ++ u32 axi_hls_offset; ++ u32 axi_ras_offset; ++ u32 axi_dti_offset; ++}; ++ + /** + * struct cdns_pcie - private data for Cadence PCIe controller drivers + * @reg_base: IO mapped register base + * @mem_res: start/end offsets in the physical system memory to map PCI accesses ++ * @msg_res: Region for send message to map PCI accesses + * @dev: PCIe controller + * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint. + * @phy_count: number of supported PHY devices +@@ -45,16 +85,19 @@ struct cdns_pcie_ops { + * @link: list of pointers to corresponding device link representations + * @ops: Platform-specific ops to control various inputs from Cadence PCIe + * wrapper ++ * @cdns_pcie_reg_offsets: Register bank offsets for different SoC + */ + struct cdns_pcie { +- void __iomem *reg_base; +- struct resource *mem_res; +- struct device *dev; +- bool is_rc; +- int phy_count; +- struct phy **phy; +- struct device_link **link; +- const struct cdns_pcie_ops *ops; ++ void __iomem *reg_base; ++ struct resource *mem_res; ++ struct resource *msg_res; ++ struct device *dev; ++ bool is_rc; ++ int phy_count; ++ struct phy **phy; ++ struct device_link **link; ++ const struct cdns_pcie_ops *ops; ++ const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; + }; + + /** +@@ -70,6 +113,8 @@ struct cdns_pcie { + * available + * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 + * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk ++ * @ecam_supported: Whether the ECAM is supported ++ * @no_inbound_map: Whether inbound mapping is supported + */ + struct cdns_pcie_rc { + struct cdns_pcie pcie; +@@ -80,6 +125,8 @@ struct cdns_pcie_rc { + bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; + unsigned int quirk_retrain_flag:1; + unsigned int quirk_detect_quiet_flag:1; ++ unsigned int ecam_supported:1; ++ unsigned int no_inbound_map:1; + }; + + /** +@@ -132,6 +179,43 @@ struct cdns_pcie_ep { + unsigned int quirk_disable_flr:1; + }; + ++static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_pcie_reg_bank bank) ++{ ++ u32 offset = 0x0; ++ ++ switch (bank) { ++ case REG_BANK_RP: ++ offset = 0; ++ break; ++ case REG_BANK_IP_REG: ++ offset = pcie->cdns_pcie_reg_offsets->ip_reg_bank_offset; ++ break; ++ case REG_BANK_IP_CFG_CTRL_REG: ++ offset = pcie->cdns_pcie_reg_offsets->ip_cfg_ctrl_reg_offset; ++ break; ++ case REG_BANK_AXI_MASTER_COMMON: ++ offset = pcie->cdns_pcie_reg_offsets->axi_mstr_common_offset; ++ break; ++ case REG_BANK_AXI_MASTER: ++ offset = pcie->cdns_pcie_reg_offsets->axi_master_offset; ++ break; ++ case REG_BANK_AXI_SLAVE: ++ offset = pcie->cdns_pcie_reg_offsets->axi_slave_offset; ++ break; ++ case REG_BANK_AXI_HLS: ++ offset = pcie->cdns_pcie_reg_offsets->axi_hls_offset; ++ break; ++ case REG_BANK_AXI_RAS: ++ offset = pcie->cdns_pcie_reg_offsets->axi_ras_offset; ++ break; ++ case REG_BANK_AXI_DTI: ++ offset = pcie->cdns_pcie_reg_offsets->axi_dti_offset; ++ break; ++ default: ++ break; ++ } ++ return offset; ++} + + /* Register access */ + static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) +@@ -144,6 +228,27 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) + return readl(pcie->reg_base + reg); + } + ++static inline void cdns_pcie_hpa_writel(struct cdns_pcie *pcie, ++ enum cdns_pcie_reg_bank bank, ++ u32 reg, ++ u32 value) ++{ ++ u32 offset = cdns_reg_bank_to_off(pcie, bank); ++ ++ reg += offset; ++ writel(value, pcie->reg_base + reg); ++} ++ ++static inline u32 cdns_pcie_hpa_readl(struct cdns_pcie *pcie, ++ enum cdns_pcie_reg_bank bank, ++ u32 reg) ++{ ++ u32 offset = cdns_reg_bank_to_off(pcie, bank); ++ ++ reg += offset; ++ return readl(pcie->reg_base + reg); ++} ++ + static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) + { + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); +@@ -233,6 +338,29 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) + return cdns_pcie_read_sz(addr, 0x2); + } + ++static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie, ++ u32 reg, u8 value) ++{ ++ void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; ++ ++ cdns_pcie_write_sz(addr, 0x1, value); ++} ++ ++static inline void cdns_pcie_hpa_rp_writew(struct cdns_pcie *pcie, ++ u32 reg, u16 value) ++{ ++ void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; ++ ++ cdns_pcie_write_sz(addr, 0x2, value); ++} ++ ++static inline u16 cdns_pcie_hpa_rp_readw(struct cdns_pcie *pcie, u32 reg) ++{ ++ void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; ++ ++ return cdns_pcie_read_sz(addr, 0x2); ++} ++ + /* Endpoint Function register access */ + static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, + u32 reg, u8 value) +@@ -297,6 +425,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); + void cdns_pcie_host_disable(struct cdns_pcie_rc *rc); + void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where); ++int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc); + #else + static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) + { +@@ -313,6 +442,11 @@ static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) + return 0; + } + ++static inline int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) ++{ ++ return 0; ++} ++ + static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc) + { + } +@@ -327,6 +461,7 @@ static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int d + #if IS_ENABLED(CONFIG_PCIE_CADENCE_EP) + int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); + void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep); ++int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep); + #else + static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) + { +@@ -336,10 +471,17 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) + static inline void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep) + { + } ++ ++static inline int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep) ++{ ++ return 0; ++} ++ + #endif + +-u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); +-u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); ++u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); ++u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); ++bool cdns_pcie_linkup(struct cdns_pcie *pcie); + + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); + +@@ -353,8 +495,23 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, + + void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); + void cdns_pcie_disable_phy(struct cdns_pcie *pcie); +-int cdns_pcie_enable_phy(struct cdns_pcie *pcie); +-int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); ++int cdns_pcie_enable_phy(struct cdns_pcie *pcie); ++int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); ++void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie); ++void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, ++ u32 r, bool is_io, ++ u64 cpu_addr, u64 pci_addr, size_t size); ++void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, ++ u8 busnr, u8 fn, ++ u32 r, u64 cpu_addr); ++int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc); ++void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, ++ int where); ++int cdns_pcie_hpa_host_start_link(struct cdns_pcie_rc *rc); ++int cdns_pcie_hpa_start_link(struct cdns_pcie *pcie); ++void cdns_pcie_hpa_stop_link(struct cdns_pcie *pcie); ++bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie); ++ + extern const struct dev_pm_ops cdns_pcie_pm_ops; + + #endif /* _PCIE_CADENCE_H */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0147-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch b/SPECS/linux-lts-kmhv2/0147-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch deleted file mode 100644 index 1f7191cbd3..0000000000 --- a/SPECS/linux-lts-kmhv2/0147-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch +++ /dev/null @@ -1,508 +0,0 @@ -From c11c8fffc2a4398eef7883769b12ef9c7e9d39ea Mon Sep 17 00:00:00 2001 -From: Manikandan K Pillai -Date: Sat, 8 Nov 2025 22:02:57 +0800 -Subject: [PATCH 147/467] UPSTREAM: PCI: cadence: Split PCIe controller header - file - -Split the Cadence PCIe header file by moving the Legacy (LGA) controller -register definitions to a separate header file for support of next -generation PCIe controller architecture. - -Signed-off-by: Manikandan K Pillai -Signed-off-by: Manivannan Sadhasivam -Link: https://patch.msgid.link/20251108140305.1120117-3-hans.zhang@cixtech.com -(cherry picked from commit 3977be25f5fd973cad6bed810ac1045ba8cfbfa6) -Signed-off-by: Han Gao ---- - .../cadence/pcie-cadence-lga-regs.h | 230 ++++++++++++++++++ - drivers/pci/controller/cadence/pcie-cadence.h | 222 +---------------- - 2 files changed, 232 insertions(+), 220 deletions(-) - create mode 100644 drivers/pci/controller/cadence/pcie-cadence-lga-regs.h - -diff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h -new file mode 100644 -index 000000000000..857b2140c5d2 ---- /dev/null -+++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h -@@ -0,0 +1,230 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Cadence PCIe controller driver. -+ * -+ * Copyright (c) 2017 Cadence -+ * Author: Cyrille Pitchen -+ */ -+#ifndef _PCIE_CADENCE_LGA_REGS_H -+#define _PCIE_CADENCE_LGA_REGS_H -+ -+#include -+ -+/* Parameters for the waiting for link up routine */ -+#define LINK_WAIT_MAX_RETRIES 10 -+#define LINK_WAIT_USLEEP_MIN 90000 -+#define LINK_WAIT_USLEEP_MAX 100000 -+ -+/* Local Management Registers */ -+#define CDNS_PCIE_LM_BASE 0x00100000 -+ -+/* Vendor ID Register */ -+#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) -+#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) -+#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 -+#define CDNS_PCIE_LM_ID_VENDOR(vid) \ -+ (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) -+#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) -+#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 -+#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ -+ (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) -+ -+/* Root Port Requester ID Register */ -+#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) -+#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) -+#define CDNS_PCIE_LM_RP_RID_SHIFT 0 -+#define CDNS_PCIE_LM_RP_RID_(rid) \ -+ (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) -+ -+/* Endpoint Bus and Device Number Register */ -+#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022C) -+#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) -+#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 -+#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) -+#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 -+ -+/* Endpoint Function f BAR b Configuration Registers */ -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ -+ (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn)) -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ -+ (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ -+ (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) -+#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ -+ (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn)) -+#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ -+ (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) -+#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ -+ (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ -+ (GENMASK(4, 0) << ((b) * 8)) -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ -+ (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ -+ (GENMASK(7, 5) << ((b) * 8)) -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ -+ (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) -+ -+/* Endpoint Function Configuration Register */ -+#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02C0) -+ -+/* Root Complex BAR Configuration Register */ -+#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ -+ (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ -+ (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ -+ (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ -+ (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) -+#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) -+#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 -+#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) -+#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) -+#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 -+#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) -+#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) -+ -+/* BAR control values applicable to both Endpoint Function and Root Complex */ -+#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 -+#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 -+#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 -+#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 -+#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 -+#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 -+ -+#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ -+ (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) -+#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ -+ (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) -+#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ -+ (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) -+#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ -+ (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) -+#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ -+ (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) -+#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ -+ (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) -+#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ -+ (((aperture) - 2) << ((bar) * 8)) -+ -+/* PTM Control Register */ -+#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0DA8) -+#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) -+ -+/* -+ * Endpoint Function Registers (PCI configuration space for endpoint functions) -+ */ -+#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) -+ -+#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -+#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xB0 -+#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xC0 -+#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 -+ -+/* Endpoint PF Registers */ -+#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) -+#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) -+ -+/* Root Port Registers (PCI configuration space for the root port function) */ -+#define CDNS_PCIE_RP_BASE 0x00200000 -+#define CDNS_PCIE_RP_CAP_OFFSET 0xC0 -+ -+/* Address Translation Registers */ -+#define CDNS_PCIE_AT_BASE 0x00400000 -+ -+/* Region r Outbound AXI to PCIe Address Translation Register 0 */ -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ -+ (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1F) * 0x0020) -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ -+ (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ -+ (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ -+ (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) -+ -+/* Region r Outbound AXI to PCIe Address Translation Register 1 */ -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ -+ (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1F) * 0x0020) -+ -+/* Region r Outbound PCIe Descriptor Register 0 */ -+#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ -+ (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1F) * 0x0020) -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xA -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xB -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xC -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xD -+/* Bit 23 MUST be set in RC mode. */ -+#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) -+#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) -+#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ -+ (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) -+ -+/* Region r Outbound PCIe Descriptor Register 1 */ -+#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ -+ (CDNS_PCIE_AT_BASE + 0x000C + ((r) & 0x1F) * 0x0020) -+#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) -+#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ -+ ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) -+ -+/* Region r AXI Region Base Address Register 0 */ -+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ -+ (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1F) * 0x0020) -+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) -+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ -+ (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) -+ -+/* Region r AXI Region Base Address Register 1 */ -+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ -+ (CDNS_PCIE_AT_BASE + 0x001C + ((r) & 0x1F) * 0x0020) -+ -+/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ -+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ -+ (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) -+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) -+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ -+ (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) -+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ -+ (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) -+ -+/* AXI link down register */ -+#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) -+ -+/* LTSSM Capabilities register */ -+#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) -+#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) -+#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 -+#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ -+ (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ -+ CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) -+ -+#define CDNS_PCIE_RP_MAX_IB 0x3 -+#define CDNS_PCIE_MAX_OB 32 -+ -+/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ -+#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ -+ (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) -+#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ -+ (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) -+ -+/* Normal/Vendor specific message access: offset inside some outbound region */ -+#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) -+#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ -+ (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) -+#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) -+#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ -+ (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) -+#define CDNS_PCIE_MSG_NO_DATA BIT(16) -+ -+#endif /* _PCIE_CADENCE_LGA_REGS_H */ -diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h -index 23ccad0a31f2..23aa64df1980 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence.h -+++ b/drivers/pci/controller/cadence/pcie-cadence.h -@@ -7,211 +7,11 @@ - #define _PCIE_CADENCE_H - - #include -+#include - #include - #include - #include -- --/* Parameters for the waiting for link up routine */ --#define LINK_WAIT_MAX_RETRIES 10 --#define LINK_WAIT_USLEEP_MIN 90000 --#define LINK_WAIT_USLEEP_MAX 100000 -- --/* -- * Local Management Registers -- */ --#define CDNS_PCIE_LM_BASE 0x00100000 -- --/* Vendor ID Register */ --#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) --#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) --#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 --#define CDNS_PCIE_LM_ID_VENDOR(vid) \ -- (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) --#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) --#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 --#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ -- (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) -- --/* Root Port Requester ID Register */ --#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) --#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) --#define CDNS_PCIE_LM_RP_RID_SHIFT 0 --#define CDNS_PCIE_LM_RP_RID_(rid) \ -- (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) -- --/* Endpoint Bus and Device Number Register */ --#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) --#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) --#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 --#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) --#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 -- --/* Endpoint Function f BAR b Configuration Registers */ --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ -- (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn)) --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ -- (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ -- (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) --#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ -- (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn)) --#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ -- (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) --#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ -- (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ -- (GENMASK(4, 0) << ((b) * 8)) --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ -- (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ -- (GENMASK(7, 5) << ((b) * 8)) --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ -- (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) -- --/* Endpoint Function Configuration Register */ --#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) -- --/* Root Complex BAR Configuration Register */ --#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ -- (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ -- (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ -- (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ -- (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) --#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) --#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 --#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) --#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) --#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 --#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) --#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) -- --/* BAR control values applicable to both Endpoint Function and Root Complex */ --#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 --#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 --#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 --#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 --#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 --#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 -- --#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ -- (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) --#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ -- (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) --#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ -- (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) --#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ -- (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) --#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ -- (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) --#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ -- (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) --#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ -- (((aperture) - 2) << ((bar) * 8)) -- --/* PTM Control Register */ --#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8) --#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) -- --/* -- * Endpoint Function Registers (PCI configuration space for endpoint functions) -- */ --#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) -- --/* -- * Endpoint PF Registers -- */ --#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) --#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) -- --/* -- * Root Port Registers (PCI configuration space for the root port function) -- */ --#define CDNS_PCIE_RP_BASE 0x00200000 --#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 -- --/* -- * Address Translation Registers -- */ --#define CDNS_PCIE_AT_BASE 0x00400000 -- --/* Region r Outbound AXI to PCIe Address Translation Register 0 */ --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ -- (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ -- (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ -- (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ -- (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) -- --/* Region r Outbound AXI to PCIe Address Translation Register 1 */ --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ -- (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) -- --/* Region r Outbound PCIe Descriptor Register 0 */ --#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ -- (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd --/* Bit 23 MUST be set in RC mode. */ --#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) --#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) --#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ -- (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) -- --/* Region r Outbound PCIe Descriptor Register 1 */ --#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ -- (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) --#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) --#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ -- ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) -- --/* Region r AXI Region Base Address Register 0 */ --#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ -- (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) --#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) --#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ -- (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) -- --/* Region r AXI Region Base Address Register 1 */ --#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ -- (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) -- --/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ --#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ -- (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) --#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) --#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ -- (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) --#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ -- (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) -- --/* AXI link down register */ --#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) -- --/* LTSSM Capabilities register */ --#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) --#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) --#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 --#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ -- (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ -- CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) -+#include "pcie-cadence-lga-regs.h" - - enum cdns_pcie_rp_bar { - RP_BAR_UNDEFINED = -1, -@@ -220,29 +20,11 @@ enum cdns_pcie_rp_bar { - RP_NO_BAR - }; - --#define CDNS_PCIE_RP_MAX_IB 0x3 --#define CDNS_PCIE_MAX_OB 32 -- - struct cdns_pcie_rp_ib_bar { - u64 size; - bool free; - }; - --/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ --#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ -- (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) --#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ -- (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) -- --/* Normal/Vendor specific message access: offset inside some outbound region */ --#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) --#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ -- (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) --#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) --#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ -- (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) --#define CDNS_PCIE_MSG_DATA BIT(16) -- - struct cdns_pcie; - - struct cdns_pcie_ops { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch b/SPECS/linux-lts-kmhv2/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch new file mode 100644 index 0000000000..45d4cc96d9 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch @@ -0,0 +1,38 @@ +From 668b64875b3a39ad0c809fd84baba5596b3f93c1 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:49:55 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use phylink's interface mode + for set_clk_tx_rate() + +imx_dwmac_set_clk_tx_rate() is passed the interface mode from phylink +which will be the same as plat_dat->phy_interface. Use the passed-in +interface mode rather than plat_dat->phy_interface. + +Reviewed-by: Maxime Chevallier +Tested-by: Maxime Chevallier +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt4N-0000000ChoM-1llp@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit dec568a36f9b16f0334aed8e95ec4225606830cc) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index 4268b9987237..147fa08d5b6e 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -195,9 +195,6 @@ static void imx_dwmac_exit(struct platform_device *pdev, void *priv) + static int imx_dwmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, + phy_interface_t interface, int speed) + { +- struct imx_priv_data *dwmac = bsp_priv; +- +- interface = dwmac->plat_dat->phy_interface; + if (interface == PHY_INTERFACE_MODE_RMII || + interface == PHY_INTERFACE_MODE_MII) + return 0; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0148-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch b/SPECS/linux-lts-kmhv2/0148-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch deleted file mode 100644 index 297fc9341d..0000000000 --- a/SPECS/linux-lts-kmhv2/0148-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch +++ /dev/null @@ -1,731 +0,0 @@ -From a8c954c135b4ad338d55143da55d606909cfffb3 Mon Sep 17 00:00:00 2001 -From: Manikandan K Pillai -Date: Sat, 8 Nov 2025 22:02:58 +0800 -Subject: [PATCH 148/467] UPSTREAM: PCI: cadence: Move PCIe RP common functions - to a separate file - -Move the Cadence PCIe controller RP common functions into a separate file. -The common library functions are split from legacy PCIe RP controller -functions to a separate file. - -Signed-off-by: Manikandan K Pillai -[mani: removed the unused variable] -Signed-off-by: Manivannan Sadhasivam -Link: https://patch.msgid.link/20251108140305.1120117-4-hans.zhang@cixtech.com -(cherry picked from commit b80a7b4713c967479752ea4801eb1d1933093f58) -Signed-off-by: Han Gao ---- - drivers/pci/controller/cadence/Makefile | 10 +- - .../cadence/pcie-cadence-host-common.c | 288 ++++++++++++++++++ - .../cadence/pcie-cadence-host-common.h | 46 +++ - .../controller/cadence/pcie-cadence-host.c | 278 +---------------- - 4 files changed, 349 insertions(+), 273 deletions(-) - create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common.c - create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common.h - -diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile -index 5e23f8539ecc..91ffdbfd3aaa 100644 ---- a/drivers/pci/controller/cadence/Makefile -+++ b/drivers/pci/controller/cadence/Makefile -@@ -1,7 +1,11 @@ - # SPDX-License-Identifier: GPL-2.0 --obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o --obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o --obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o -+pcie-cadence-mod-y := pcie-cadence.o -+pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o -+pcie-cadence-ep-mod-y := pcie-cadence-ep.o -+ -+obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o -+obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o -+obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o - obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o - obj-$(CONFIG_PCI_J721E) += pci-j721e.o - obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o -diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c -new file mode 100644 -index 000000000000..15415d7f35ee ---- /dev/null -+++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c -@@ -0,0 +1,288 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Cadence PCIe host controller library. -+ * -+ * Copyright (c) 2017 Cadence -+ * Author: Cyrille Pitchen -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pcie-cadence.h" -+#include "pcie-cadence-host-common.h" -+ -+#define LINK_RETRAIN_TIMEOUT HZ -+ -+u64 bar_max_size[] = { -+ [RP_BAR0] = _ULL(128 * SZ_2G), -+ [RP_BAR1] = SZ_2G, -+ [RP_NO_BAR] = _BITULL(63), -+}; -+EXPORT_SYMBOL_GPL(bar_max_size); -+ -+int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) -+{ -+ u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; -+ unsigned long end_jiffies; -+ u16 lnk_stat; -+ -+ /* Wait for link training to complete. Exit after timeout. */ -+ end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; -+ do { -+ lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); -+ if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) -+ break; -+ usleep_range(0, 1000); -+ } while (time_before(jiffies, end_jiffies)); -+ -+ if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) -+ return 0; -+ -+ return -ETIMEDOUT; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_host_training_complete); -+ -+int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie, -+ cdns_pcie_linkup_func pcie_link_up) -+{ -+ struct device *dev = pcie->dev; -+ int retries; -+ -+ /* Check if the link is up or not */ -+ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { -+ if (pcie_link_up(pcie)) { -+ dev_info(dev, "Link up\n"); -+ return 0; -+ } -+ usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); -+ } -+ -+ return -ETIMEDOUT; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_host_wait_for_link); -+ -+int cdns_pcie_retrain(struct cdns_pcie *pcie, -+ cdns_pcie_linkup_func pcie_link_up) -+{ -+ u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; -+ u16 lnk_stat, lnk_ctl; -+ int ret = 0; -+ -+ /* -+ * Set retrain bit if current speed is 2.5 GB/s, -+ * but the PCIe root port support is > 2.5 GB/s. -+ */ -+ -+ lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + -+ PCI_EXP_LNKCAP)); -+ if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) -+ return ret; -+ -+ lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); -+ if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { -+ lnk_ctl = cdns_pcie_rp_readw(pcie, -+ pcie_cap_off + PCI_EXP_LNKCTL); -+ lnk_ctl |= PCI_EXP_LNKCTL_RL; -+ cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, -+ lnk_ctl); -+ -+ ret = cdns_pcie_host_training_complete(pcie); -+ if (ret) -+ return ret; -+ -+ ret = cdns_pcie_host_wait_for_link(pcie, pcie_link_up); -+ } -+ return ret; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_retrain); -+ -+int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, -+ cdns_pcie_linkup_func pcie_link_up) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ int ret; -+ -+ ret = cdns_pcie_host_wait_for_link(pcie, pcie_link_up); -+ -+ /* -+ * Retrain link for Gen2 training defect -+ * if quirk flag is set. -+ */ -+ if (!ret && rc->quirk_retrain_flag) -+ ret = cdns_pcie_retrain(pcie, pcie_link_up); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link); -+ -+enum cdns_pcie_rp_bar -+cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) -+{ -+ enum cdns_pcie_rp_bar bar, sel_bar; -+ -+ sel_bar = RP_BAR_UNDEFINED; -+ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { -+ if (!rc->avail_ib_bar[bar]) -+ continue; -+ -+ if (size <= bar_max_size[bar]) { -+ if (sel_bar == RP_BAR_UNDEFINED) { -+ sel_bar = bar; -+ continue; -+ } -+ -+ if (bar_max_size[bar] < bar_max_size[sel_bar]) -+ sel_bar = bar; -+ } -+ } -+ -+ return sel_bar; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_host_find_min_bar); -+ -+enum cdns_pcie_rp_bar -+cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) -+{ -+ enum cdns_pcie_rp_bar bar, sel_bar; -+ -+ sel_bar = RP_BAR_UNDEFINED; -+ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { -+ if (!rc->avail_ib_bar[bar]) -+ continue; -+ -+ if (size >= bar_max_size[bar]) { -+ if (sel_bar == RP_BAR_UNDEFINED) { -+ sel_bar = bar; -+ continue; -+ } -+ -+ if (bar_max_size[bar] > bar_max_size[sel_bar]) -+ sel_bar = bar; -+ } -+ } -+ -+ return sel_bar; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_host_find_max_bar); -+ -+int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, -+ const struct list_head *b) -+{ -+ struct resource_entry *entry1, *entry2; -+ -+ entry1 = container_of(a, struct resource_entry, node); -+ entry2 = container_of(b, struct resource_entry, node); -+ -+ return resource_size(entry2->res) - resource_size(entry1->res); -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_host_dma_ranges_cmp); -+ -+int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, -+ struct resource_entry *entry, -+ cdns_pcie_host_bar_ib_cfg pci_host_ib_config) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ struct device *dev = pcie->dev; -+ u64 cpu_addr, size, winsize; -+ enum cdns_pcie_rp_bar bar; -+ unsigned long flags; -+ int ret; -+ -+ cpu_addr = entry->res->start; -+ flags = entry->res->flags; -+ size = resource_size(entry->res); -+ -+ while (size > 0) { -+ /* -+ * Try to find a minimum BAR whose size is greater than -+ * or equal to the remaining resource_entry size. This will -+ * fail if the size of each of the available BARs is less than -+ * the remaining resource_entry size. -+ * -+ * If a minimum BAR is found, IB ATU will be configured and -+ * exited. -+ */ -+ bar = cdns_pcie_host_find_min_bar(rc, size); -+ if (bar != RP_BAR_UNDEFINED) { -+ ret = pci_host_ib_config(rc, bar, cpu_addr, size, flags); -+ if (ret) -+ dev_err(dev, "IB BAR: %d config failed\n", bar); -+ return ret; -+ } -+ -+ /* -+ * If the control reaches here, it would mean the remaining -+ * resource_entry size cannot be fitted in a single BAR. So we -+ * find a maximum BAR whose size is less than or equal to the -+ * remaining resource_entry size and split the resource entry -+ * so that part of resource entry is fitted inside the maximum -+ * BAR. The remaining size would be fitted during the next -+ * iteration of the loop. -+ * -+ * If a maximum BAR is not found, there is no way we can fit -+ * this resource_entry, so we error out. -+ */ -+ bar = cdns_pcie_host_find_max_bar(rc, size); -+ if (bar == RP_BAR_UNDEFINED) { -+ dev_err(dev, "No free BAR to map cpu_addr %llx\n", -+ cpu_addr); -+ return -EINVAL; -+ } -+ -+ winsize = bar_max_size[bar]; -+ ret = pci_host_ib_config(rc, bar, cpu_addr, winsize, flags); -+ if (ret) { -+ dev_err(dev, "IB BAR: %d config failed\n", bar); -+ return ret; -+ } -+ -+ size -= winsize; -+ cpu_addr += winsize; -+ } -+ -+ return 0; -+} -+ -+int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc, -+ cdns_pcie_host_bar_ib_cfg pci_host_ib_config) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ struct device *dev = pcie->dev; -+ struct device_node *np = dev->of_node; -+ struct pci_host_bridge *bridge; -+ struct resource_entry *entry; -+ u32 no_bar_nbits = 32; -+ int err; -+ -+ bridge = pci_host_bridge_from_priv(rc); -+ if (!bridge) -+ return -ENOMEM; -+ -+ if (list_empty(&bridge->dma_ranges)) { -+ of_property_read_u32(np, "cdns,no-bar-match-nbits", -+ &no_bar_nbits); -+ err = pci_host_ib_config(rc, RP_NO_BAR, 0x0, (u64)1 << no_bar_nbits, 0); -+ if (err) -+ dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); -+ return err; -+ } -+ -+ list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); -+ -+ resource_list_for_each_entry(entry, &bridge->dma_ranges) { -+ err = cdns_pcie_host_bar_config(rc, entry, pci_host_ib_config); -+ if (err) { -+ dev_err(dev, "Fail to configure IB using dma-ranges\n"); -+ return err; -+ } -+ } -+ -+ return 0; -+} -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Cadence PCIe host controller driver"); -diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.h b/drivers/pci/controller/cadence/pcie-cadence-host-common.h -new file mode 100644 -index 000000000000..fe7d4202a8b6 ---- /dev/null -+++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.h -@@ -0,0 +1,46 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Cadence PCIe Host controller driver. -+ * -+ * Copyright (c) 2017 Cadence -+ * Author: Cyrille Pitchen -+ */ -+#ifndef _PCIE_CADENCE_HOST_COMMON_H -+#define _PCIE_CADENCE_HOST_COMMON_H -+ -+#include -+#include -+ -+extern u64 bar_max_size[]; -+ -+typedef int (*cdns_pcie_host_bar_ib_cfg)(struct cdns_pcie_rc *, -+ enum cdns_pcie_rp_bar, -+ u64, -+ u64, -+ unsigned long); -+typedef bool (*cdns_pcie_linkup_func)(struct cdns_pcie *); -+ -+int cdns_pcie_host_training_complete(struct cdns_pcie *pcie); -+int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie, -+ cdns_pcie_linkup_func pcie_link_up); -+int cdns_pcie_retrain(struct cdns_pcie *pcie, cdns_pcie_linkup_func pcie_linkup_func); -+int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, -+ cdns_pcie_linkup_func pcie_link_up); -+enum cdns_pcie_rp_bar -+cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size); -+enum cdns_pcie_rp_bar -+cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size); -+int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, -+ const struct list_head *b); -+int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, -+ enum cdns_pcie_rp_bar bar, -+ u64 cpu_addr, -+ u64 size, -+ unsigned long flags); -+int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, -+ struct resource_entry *entry, -+ cdns_pcie_host_bar_ib_cfg pci_host_ib_config); -+int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc, -+ cdns_pcie_host_bar_ib_cfg pci_host_ib_config); -+ -+#endif /* _PCIE_CADENCE_HOST_COMMON_H */ -diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c -index fffd63d6665e..db3154c1eccb 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence-host.c -+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c -@@ -12,14 +12,7 @@ - #include - - #include "pcie-cadence.h" -- --#define LINK_RETRAIN_TIMEOUT HZ -- --static u64 bar_max_size[] = { -- [RP_BAR0] = _ULL(128 * SZ_2G), -- [RP_BAR1] = SZ_2G, -- [RP_NO_BAR] = _BITULL(63), --}; -+#include "pcie-cadence-host-common.h" - - static u8 bar_aperture_mask[] = { - [RP_BAR0] = 0x1F, -@@ -81,77 +74,6 @@ static struct pci_ops cdns_pcie_host_ops = { - .write = pci_generic_config_write, - }; - --static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) --{ -- u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; -- unsigned long end_jiffies; -- u16 lnk_stat; -- -- /* Wait for link training to complete. Exit after timeout. */ -- end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; -- do { -- lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); -- if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) -- break; -- usleep_range(0, 1000); -- } while (time_before(jiffies, end_jiffies)); -- -- if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) -- return 0; -- -- return -ETIMEDOUT; --} -- --static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) --{ -- struct device *dev = pcie->dev; -- int retries; -- -- /* Check if the link is up or not */ -- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { -- if (cdns_pcie_link_up(pcie)) { -- dev_info(dev, "Link up\n"); -- return 0; -- } -- usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); -- } -- -- return -ETIMEDOUT; --} -- --static int cdns_pcie_retrain(struct cdns_pcie *pcie) --{ -- u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; -- u16 lnk_stat, lnk_ctl; -- int ret = 0; -- -- /* -- * Set retrain bit if current speed is 2.5 GB/s, -- * but the PCIe root port support is > 2.5 GB/s. -- */ -- -- lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + -- PCI_EXP_LNKCAP)); -- if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) -- return ret; -- -- lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); -- if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { -- lnk_ctl = cdns_pcie_rp_readw(pcie, -- pcie_cap_off + PCI_EXP_LNKCTL); -- lnk_ctl |= PCI_EXP_LNKCTL_RL; -- cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, -- lnk_ctl); -- -- ret = cdns_pcie_host_training_complete(pcie); -- if (ret) -- return ret; -- -- ret = cdns_pcie_host_wait_for_link(pcie); -- } -- return ret; --} -- - static void cdns_pcie_host_disable_ptm_response(struct cdns_pcie *pcie) - { - u32 val; -@@ -168,23 +90,6 @@ static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie) - cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN); - } - --static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) --{ -- struct cdns_pcie *pcie = &rc->pcie; -- int ret; -- -- ret = cdns_pcie_host_wait_for_link(pcie); -- -- /* -- * Retrain link for Gen2 training defect -- * if quirk flag is set. -- */ -- if (!ret && rc->quirk_retrain_flag) -- ret = cdns_pcie_retrain(pcie); -- -- return ret; --} -- - static void cdns_pcie_host_deinit_root_port(struct cdns_pcie_rc *rc) - { - struct cdns_pcie *pcie = &rc->pcie; -@@ -245,10 +150,11 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) - return 0; - } - --static int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, -- enum cdns_pcie_rp_bar bar, -- u64 cpu_addr, u64 size, -- unsigned long flags) -+int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, -+ enum cdns_pcie_rp_bar bar, -+ u64 cpu_addr, -+ u64 size, -+ unsigned long flags) - { - struct cdns_pcie *pcie = &rc->pcie; - u32 addr0, addr1, aperture, value; -@@ -290,137 +196,6 @@ static int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, - return 0; - } - --static enum cdns_pcie_rp_bar --cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) --{ -- enum cdns_pcie_rp_bar bar, sel_bar; -- -- sel_bar = RP_BAR_UNDEFINED; -- for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { -- if (!rc->avail_ib_bar[bar]) -- continue; -- -- if (size <= bar_max_size[bar]) { -- if (sel_bar == RP_BAR_UNDEFINED) { -- sel_bar = bar; -- continue; -- } -- -- if (bar_max_size[bar] < bar_max_size[sel_bar]) -- sel_bar = bar; -- } -- } -- -- return sel_bar; --} -- --static enum cdns_pcie_rp_bar --cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) --{ -- enum cdns_pcie_rp_bar bar, sel_bar; -- -- sel_bar = RP_BAR_UNDEFINED; -- for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { -- if (!rc->avail_ib_bar[bar]) -- continue; -- -- if (size >= bar_max_size[bar]) { -- if (sel_bar == RP_BAR_UNDEFINED) { -- sel_bar = bar; -- continue; -- } -- -- if (bar_max_size[bar] > bar_max_size[sel_bar]) -- sel_bar = bar; -- } -- } -- -- return sel_bar; --} -- --static int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, -- struct resource_entry *entry) --{ -- u64 cpu_addr, pci_addr, size, winsize; -- struct cdns_pcie *pcie = &rc->pcie; -- struct device *dev = pcie->dev; -- enum cdns_pcie_rp_bar bar; -- unsigned long flags; -- int ret; -- -- cpu_addr = entry->res->start; -- pci_addr = entry->res->start - entry->offset; -- flags = entry->res->flags; -- size = resource_size(entry->res); -- -- if (entry->offset) { -- dev_err(dev, "PCI addr: %llx must be equal to CPU addr: %llx\n", -- pci_addr, cpu_addr); -- return -EINVAL; -- } -- -- while (size > 0) { -- /* -- * Try to find a minimum BAR whose size is greater than -- * or equal to the remaining resource_entry size. This will -- * fail if the size of each of the available BARs is less than -- * the remaining resource_entry size. -- * If a minimum BAR is found, IB ATU will be configured and -- * exited. -- */ -- bar = cdns_pcie_host_find_min_bar(rc, size); -- if (bar != RP_BAR_UNDEFINED) { -- ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, -- size, flags); -- if (ret) -- dev_err(dev, "IB BAR: %d config failed\n", bar); -- return ret; -- } -- -- /* -- * If the control reaches here, it would mean the remaining -- * resource_entry size cannot be fitted in a single BAR. So we -- * find a maximum BAR whose size is less than or equal to the -- * remaining resource_entry size and split the resource entry -- * so that part of resource entry is fitted inside the maximum -- * BAR. The remaining size would be fitted during the next -- * iteration of the loop. -- * If a maximum BAR is not found, there is no way we can fit -- * this resource_entry, so we error out. -- */ -- bar = cdns_pcie_host_find_max_bar(rc, size); -- if (bar == RP_BAR_UNDEFINED) { -- dev_err(dev, "No free BAR to map cpu_addr %llx\n", -- cpu_addr); -- return -EINVAL; -- } -- -- winsize = bar_max_size[bar]; -- ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, winsize, -- flags); -- if (ret) { -- dev_err(dev, "IB BAR: %d config failed\n", bar); -- return ret; -- } -- -- size -= winsize; -- cpu_addr += winsize; -- } -- -- return 0; --} -- --static int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, -- const struct list_head *b) --{ -- struct resource_entry *entry1, *entry2; -- -- entry1 = container_of(a, struct resource_entry, node); -- entry2 = container_of(b, struct resource_entry, node); -- -- return resource_size(entry2->res) - resource_size(entry1->res); --} -- - static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) - { - struct cdns_pcie *pcie = &rc->pcie; -@@ -447,43 +222,6 @@ static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) - } - } - --static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc) --{ -- struct cdns_pcie *pcie = &rc->pcie; -- struct device *dev = pcie->dev; -- struct device_node *np = dev->of_node; -- struct pci_host_bridge *bridge; -- struct resource_entry *entry; -- u32 no_bar_nbits = 32; -- int err; -- -- bridge = pci_host_bridge_from_priv(rc); -- if (!bridge) -- return -ENOMEM; -- -- if (list_empty(&bridge->dma_ranges)) { -- of_property_read_u32(np, "cdns,no-bar-match-nbits", -- &no_bar_nbits); -- err = cdns_pcie_host_bar_ib_config(rc, RP_NO_BAR, 0x0, -- (u64)1 << no_bar_nbits, 0); -- if (err) -- dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); -- return err; -- } -- -- list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); -- -- resource_list_for_each_entry(entry, &bridge->dma_ranges) { -- err = cdns_pcie_host_bar_config(rc, entry); -- if (err) { -- dev_err(dev, "Fail to configure IB using dma-ranges\n"); -- return err; -- } -- } -- -- return 0; --} -- - static void cdns_pcie_host_deinit_address_translation(struct cdns_pcie_rc *rc) - { - struct cdns_pcie *pcie = &rc->pcie; -@@ -561,7 +299,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) - r++; - } - -- return cdns_pcie_host_map_dma_ranges(rc); -+ return cdns_pcie_host_map_dma_ranges(rc, cdns_pcie_host_bar_ib_config); - } - - static void cdns_pcie_host_deinit(struct cdns_pcie_rc *rc) -@@ -607,7 +345,7 @@ int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) - return ret; - } - -- ret = cdns_pcie_host_start_link(rc); -+ ret = cdns_pcie_host_start_link(rc, cdns_pcie_link_up); - if (ret) - dev_dbg(dev, "PCIe link never came up\n"); - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch b/SPECS/linux-lts-kmhv2/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch new file mode 100644 index 0000000000..e6e34a7195 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch @@ -0,0 +1,52 @@ +From 821bb874c9ee51f801501a53f0bfaff22992f2fb Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:00 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: s32: move PHY_INTF_SEL_x + definitions out of the way + +S32's PHY_INTF_SEL_x definitions conflict with those for the dwmac +cores as they use a different bitmapping. Add a S32 prefix so that +they are unique. + +Signed-off-by: Russell King (Oracle) +Reviewed-by: Maxime Chevallier +Reviewed-by: Jan Petrous (OSS) +Link: https://patch.msgid.link/E1vFt4S-0000000ChoS-2Ahi@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit 553f23d1953527eb277efa902cd498131b2527e1) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +index ee095ac13203..2b7ad64bfdf7 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +@@ -24,10 +24,10 @@ + #define GMAC_INTF_RATE_125M 125000000 /* 125MHz */ + + /* SoC PHY interface control register */ +-#define PHY_INTF_SEL_MII 0x00 +-#define PHY_INTF_SEL_SGMII 0x01 +-#define PHY_INTF_SEL_RGMII 0x02 +-#define PHY_INTF_SEL_RMII 0x08 ++#define S32_PHY_INTF_SEL_MII 0x00 ++#define S32_PHY_INTF_SEL_SGMII 0x01 ++#define S32_PHY_INTF_SEL_RGMII 0x02 ++#define S32_PHY_INTF_SEL_RMII 0x08 + + struct s32_priv_data { + void __iomem *ioaddr; +@@ -40,7 +40,7 @@ struct s32_priv_data { + + static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac) + { +- writel(PHY_INTF_SEL_RGMII, gmac->ctrl_sts); ++ writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); + + dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode)); + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0149-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch b/SPECS/linux-lts-kmhv2/0149-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch deleted file mode 100644 index 44809270c8..0000000000 --- a/SPECS/linux-lts-kmhv2/0149-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch +++ /dev/null @@ -1,1127 +0,0 @@ -From 22b6ed1bca264e8e9b80d9630a7c430722561bec Mon Sep 17 00:00:00 2001 -From: Manikandan K Pillai -Date: Sat, 8 Nov 2025 22:02:59 +0800 -Subject: [PATCH 149/467] UPSTREAM: PCI: cadence: Add support for High Perf - Architecture (HPA) controller - -Add support for Cadence PCIe RP configuration for High Performance -Architecture (HPA) controllers. The Cadence High Performance controllers -are the latest PCIe controllers that have support for DMA, optional IDE -and updated register set. Add a common library for High Performance -Architecture (HPA) PCIe controllers. - -Signed-off-by: Manikandan K Pillai -Signed-off-by: Manivannan Sadhasivam -[bhelgaas: squash https://lore.kernel.org/r/20251120093518.2760492-1-jiapeng.chong@linux.alibaba.com, -squash https://lore.kernel.org/all/52abaad8-a43e-4e29-93d7-86a3245692c3@cixtech.com/] -Signed-off-by: Bjorn Helgaas -Link: https://patch.msgid.link/20251108140305.1120117-5-hans.zhang@cixtech.com -(cherry picked from commit 8babd8afe58a65c8d3cb9b5a6a8d24d4f93033ab) -Signed-off-by: Han Gao ---- - drivers/pci/controller/cadence/Makefile | 4 +- - .../cadence/pcie-cadence-host-hpa.c | 368 ++++++++++++++++++ - .../cadence/pcie-cadence-hpa-regs.h | 193 +++++++++ - .../pci/controller/cadence/pcie-cadence-hpa.c | 167 ++++++++ - .../controller/cadence/pcie-cadence-plat.c | 4 - - drivers/pci/controller/cadence/pcie-cadence.c | 11 + - drivers/pci/controller/cadence/pcie-cadence.h | 187 ++++++++- - 7 files changed, 913 insertions(+), 21 deletions(-) - create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-hpa.c - create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h - create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa.c - -diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile -index 91ffdbfd3aaa..30189045a166 100644 ---- a/drivers/pci/controller/cadence/Makefile -+++ b/drivers/pci/controller/cadence/Makefile -@@ -1,6 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0 --pcie-cadence-mod-y := pcie-cadence.o --pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o -+pcie-cadence-mod-y := pcie-cadence-hpa.o pcie-cadence.o -+pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o pcie-cadence-host-hpa.o - pcie-cadence-ep-mod-y := pcie-cadence-ep.o - - obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o -diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c -new file mode 100644 -index 000000000000..0f540bed58e8 ---- /dev/null -+++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c -@@ -0,0 +1,368 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Cadence PCIe host controller driver. -+ * -+ * Copyright (c) 2024, Cadence Design Systems -+ * Author: Manikandan K Pillai -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pcie-cadence.h" -+#include "pcie-cadence-host-common.h" -+ -+static u8 bar_aperture_mask[] = { -+ [RP_BAR0] = 0x3F, -+ [RP_BAR1] = 0x3F, -+}; -+ -+void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, -+ int where) -+{ -+ struct pci_host_bridge *bridge = pci_find_host_bridge(bus); -+ struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); -+ struct cdns_pcie *pcie = &rc->pcie; -+ unsigned int busn = bus->number; -+ u32 addr0, desc0, desc1, ctrl0; -+ u32 regval; -+ -+ if (pci_is_root_bus(bus)) { -+ /* -+ * Only the root port (devfn == 0) is connected to this bus. -+ * All other PCI devices are behind some bridge hence on another -+ * bus. -+ */ -+ if (devfn) -+ return NULL; -+ -+ return pcie->reg_base + (where & 0xfff); -+ } -+ -+ /* Clear AXI link-down status */ -+ regval = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN, -+ (regval & ~GENMASK(0, 0))); -+ -+ /* Update Output registers for AXI region 0 */ -+ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(12) | -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) | -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(busn); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), addr0); -+ -+ desc1 = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0)); -+ desc1 &= ~CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK; -+ desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); -+ ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; -+ -+ if (busn == bridge->busnr + 1) -+ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0; -+ else -+ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1; -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), desc0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), ctrl0); -+ -+ return rc->cfg_base + (where & 0xfff); -+} -+ -+static struct pci_ops cdns_pcie_hpa_host_ops = { -+ .map_bus = cdns_pci_hpa_map_bus, -+ .read = pci_generic_config_read, -+ .write = pci_generic_config_write, -+}; -+ -+static void cdns_pcie_hpa_host_enable_ptm_response(struct cdns_pcie *pcie) -+{ -+ u32 val; -+ -+ val = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL, -+ val | CDNS_PCIE_HPA_LM_PTM_CTRL_PTMRSEN); -+} -+ -+static int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc, -+ enum cdns_pcie_rp_bar bar, -+ u64 cpu_addr, u64 size, -+ unsigned long flags) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ u32 addr0, addr1, aperture, value; -+ -+ if (!rc->avail_ib_bar[bar]) -+ return -ENODEV; -+ -+ rc->avail_ib_bar[bar] = false; -+ -+ aperture = ilog2(size); -+ if (bar == RP_NO_BAR) { -+ addr0 = CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(aperture) | -+ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); -+ addr1 = upper_32_bits(cpu_addr); -+ } else { -+ addr0 = lower_32_bits(cpu_addr); -+ addr1 = upper_32_bits(cpu_addr); -+ } -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, -+ CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar), addr0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, -+ CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar), addr1); -+ -+ if (bar == RP_NO_BAR) -+ bar = (enum cdns_pcie_rp_bar)BAR_0; -+ -+ value = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_BAR_CFG); -+ value &= ~(HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) | -+ HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) | -+ HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) | -+ HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) | -+ HPA_LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 7)); -+ if (size + cpu_addr >= SZ_4G) { -+ value |= HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar); -+ if ((flags & IORESOURCE_PREFETCH)) -+ value |= HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar); -+ } else { -+ value |= HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar); -+ if ((flags & IORESOURCE_PREFETCH)) -+ value |= HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar); -+ } -+ -+ value |= HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_BAR_CFG, value); -+ -+ return 0; -+} -+ -+static int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ u32 value, ctrl; -+ -+ /* -+ * Set the root port BAR configuration register: -+ * - disable both BAR0 and BAR1 -+ * - enable Prefetchable Memory Base and Limit registers in type 1 -+ * config space (64 bits) -+ * - enable IO Base and Limit registers in type 1 config -+ * space (32 bits) -+ */ -+ -+ ctrl = CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED; -+ value = CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) | -+ CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) | -+ CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE | -+ CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS | -+ CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE | -+ CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS; -+ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, -+ CDNS_PCIE_HPA_LM_RC_BAR_CFG, value); -+ -+ if (rc->vendor_id != 0xffff) -+ cdns_pcie_hpa_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id); -+ -+ if (rc->device_id != 0xffff) -+ cdns_pcie_hpa_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); -+ -+ cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_REVISION, 0); -+ cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_PROG, 0); -+ cdns_pcie_hpa_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); -+ -+ /* Enable bus mastering */ -+ value = cdns_pcie_hpa_readl(pcie, REG_BANK_RP, PCI_COMMAND); -+ value |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_RP, PCI_COMMAND, value); -+ return 0; -+} -+ -+static void cdns_pcie_hpa_create_region_for_cfg(struct cdns_pcie_rc *rc) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc); -+ struct resource *cfg_res = rc->cfg_res; -+ struct resource_entry *entry; -+ u64 cpu_addr = cfg_res->start; -+ u32 addr0, addr1, desc1; -+ int busnr = 0; -+ -+ entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); -+ if (entry) -+ busnr = entry->res->start; -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_TAG_MANAGEMENT, 0x01000000); -+ /* -+ * Reserve region 0 for PCI configure space accesses: -+ * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by -+ * cdns_pci_map_bus(), other region registers are set here once for all -+ */ -+ desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), 0x0); -+ /* Type-1 CFG */ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), 0x05000000); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); -+ -+ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(12) | -+ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); -+ addr1 = upper_32_bits(cpu_addr); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), addr0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), addr1); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), 0x06000000); -+} -+ -+static int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc *rc) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc); -+ struct resource_entry *entry; -+ int r = 0, busnr = 0; -+ -+ if (!rc->ecam_supported) -+ cdns_pcie_hpa_create_region_for_cfg(rc); -+ -+ entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); -+ if (entry) -+ busnr = entry->res->start; -+ -+ r++; -+ if (pcie->msg_res) { -+ cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, busnr, 0, r, -+ pcie->msg_res->start); -+ -+ r++; -+ } -+ resource_list_for_each_entry(entry, &bridge->windows) { -+ struct resource *res = entry->res; -+ u64 pci_addr = res->start - entry->offset; -+ -+ if (resource_type(res) == IORESOURCE_IO) -+ cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, -+ true, -+ pci_pio_to_address(res->start), -+ pci_addr, -+ resource_size(res)); -+ else -+ cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, -+ false, -+ res->start, -+ pci_addr, -+ resource_size(res)); -+ -+ r++; -+ } -+ -+ if (rc->no_inbound_map) -+ return 0; -+ else -+ return cdns_pcie_host_map_dma_ranges(rc, cdns_pcie_hpa_host_bar_ib_config); -+} -+ -+static int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc) -+{ -+ int err; -+ -+ err = cdns_pcie_hpa_host_init_root_port(rc); -+ if (err) -+ return err; -+ -+ return cdns_pcie_hpa_host_init_address_translation(rc); -+} -+ -+int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ struct device *dev = rc->pcie.dev; -+ int ret; -+ -+ if (rc->quirk_detect_quiet_flag) -+ cdns_pcie_hpa_detect_quiet_min_delay_set(&rc->pcie); -+ -+ cdns_pcie_hpa_host_enable_ptm_response(pcie); -+ -+ ret = cdns_pcie_start_link(pcie); -+ if (ret) { -+ dev_err(dev, "Failed to start link\n"); -+ return ret; -+ } -+ -+ ret = cdns_pcie_host_wait_for_link(pcie, cdns_pcie_hpa_link_up); -+ if (ret) -+ dev_dbg(dev, "PCIe link never came up\n"); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup); -+ -+int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) -+{ -+ struct device *dev = rc->pcie.dev; -+ struct platform_device *pdev = to_platform_device(dev); -+ struct pci_host_bridge *bridge; -+ enum cdns_pcie_rp_bar bar; -+ struct cdns_pcie *pcie; -+ struct resource *res; -+ int ret; -+ -+ bridge = pci_host_bridge_from_priv(rc); -+ if (!bridge) -+ return -ENOMEM; -+ -+ pcie = &rc->pcie; -+ pcie->is_rc = true; -+ -+ if (!pcie->reg_base) { -+ pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg"); -+ if (IS_ERR(pcie->reg_base)) { -+ dev_err(dev, "missing \"reg\"\n"); -+ return PTR_ERR(pcie->reg_base); -+ } -+ } -+ -+ /* ECAM config space is remapped at glue layer */ -+ if (!rc->cfg_base) { -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); -+ rc->cfg_base = devm_pci_remap_cfg_resource(dev, res); -+ if (IS_ERR(rc->cfg_base)) -+ return PTR_ERR(rc->cfg_base); -+ rc->cfg_res = res; -+ } -+ -+ /* Put EROM Bar aperture to 0 */ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_EROM, 0x0); -+ -+ ret = cdns_pcie_hpa_host_link_setup(rc); -+ if (ret) -+ return ret; -+ -+ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) -+ rc->avail_ib_bar[bar] = true; -+ -+ ret = cdns_pcie_hpa_host_init(rc); -+ if (ret) -+ return ret; -+ -+ if (!bridge->ops) -+ bridge->ops = &cdns_pcie_hpa_host_ops; -+ -+ return pci_host_probe(bridge); -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_setup); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Cadence PCIe host controller driver"); -diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h -new file mode 100644 -index 000000000000..026e131600de ---- /dev/null -+++ b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h -@@ -0,0 +1,193 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Cadence PCIe controller driver. -+ * -+ * Copyright (c) 2024, Cadence Design Systems -+ * Author: Manikandan K Pillai -+ */ -+#ifndef _PCIE_CADENCE_HPA_REGS_H -+#define _PCIE_CADENCE_HPA_REGS_H -+ -+#include -+#include -+#include -+#include -+#include -+ -+/* High Performance Architecture (HPA) PCIe controller registers */ -+#define CDNS_PCIE_HPA_IP_REG_BANK 0x01000000 -+#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x01003C00 -+#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0x02020000 -+ -+/* Address Translation Registers */ -+#define CDNS_PCIE_HPA_AXI_SLAVE 0x03000000 -+#define CDNS_PCIE_HPA_AXI_MASTER 0x03002000 -+ -+/* Root Port register base address */ -+#define CDNS_PCIE_HPA_RP_BASE 0x0 -+ -+#define CDNS_PCIE_HPA_LM_ID 0x1420 -+ -+/* Endpoint Function BARs */ -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \ -+ (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \ -+ CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn)) -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) (0x4000 * (pfn)) -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) ((0x4000 * (pfn)) + 0x04) -+#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \ -+ (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \ -+ CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn)) -+#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) ((0x4000 * (vfn)) + 0x08) -+#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) ((0x4000 * (vfn)) + 0x0C) -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \ -+ (GENMASK(5, 0) << (0x4 + (f) * 10)) -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ -+ (((a) << (4 + ((b) * 10))) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))) -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \ -+ (GENMASK(3, 0) << ((f) * 10)) -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ -+ (((c) << ((b) * 10)) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))) -+ -+/* Endpoint Function Configuration Register */ -+#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG 0x02C0 -+ -+/* Root Complex BAR Configuration Register */ -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG 0x14 -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(9, 4) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ -+ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK, a) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(3, 0) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \ -+ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(19, 14) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ -+ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK, a) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(13, 10) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \ -+ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c) -+ -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(20) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(21) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE BIT(22) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS BIT(23) -+ -+/* BAR control values applicable to both Endpoint Function and Root Complex */ -+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED 0x0 -+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS 0x3 -+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS 0x1 -+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x9 -+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS 0x5 -+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0xD -+ -+#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ -+ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10)) -+#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ -+ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10)) -+#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ -+ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10)) -+#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ -+ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10)) -+#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ -+ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10)) -+#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ -+ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10)) -+#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture) \ -+ (((aperture) - 7) << (((bar) * 10) + 4)) -+ -+#define CDNS_PCIE_HPA_LM_PTM_CTRL 0x0520 -+#define CDNS_PCIE_HPA_LM_PTM_CTRL_PTMRSEN BIT(17) -+ -+/* Root Port Registers PCI config space for root port function */ -+#define CDNS_PCIE_HPA_RP_CAP_OFFSET 0xC0 -+ -+/* Region r Outbound AXI to PCIe Address Translation Register 0 */ -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) (0x1010 + ((r) & 0x1F) * 0x0080) -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ -+ (((nbits) - 1) & CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(23, 16) -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK, devfn) -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(31, 24) -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK, bus) -+ -+/* Region r Outbound AXI to PCIe Address Translation Register 1 */ -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) (0x1014 + ((r) & 0x1F) * 0x0080) -+ -+/* Region r Outbound PCIe Descriptor Register */ -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) (0x1008 + ((r) & 0x1F) * 0x0080) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(28, 24) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10) -+ -+/* Region r Outbound PCIe Descriptor Register */ -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) (0x100C + ((r) & 0x1F) * 0x0080) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK GENMASK(31, 24) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK, bus) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK GENMASK(23, 16) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK, devfn) -+ -+#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) (0x1018 + ((r) & 0x1F) * 0x0080) -+#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26) -+#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25) -+ -+/* Region r AXI Region Base Address Register 0 */ -+#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) (0x1000 + ((r) & 0x1F) * 0x0080) -+#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) -+#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ -+ (((nbits) - 1) & CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) -+ -+/* Region r AXI Region Base Address Register 1 */ -+#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) (0x1004 + ((r) & 0x1F) * 0x0080) -+ -+/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ -+#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) (((bar) * 0x0008)) -+#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) -+#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ -+ (((nbits) - 1) & CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK) -+#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) (0x04 + ((bar) * 0x0008)) -+ -+/* AXI link down register */ -+#define CDNS_PCIE_HPA_AT_LINKDOWN 0x04 -+ -+/* -+ * Physical Layer Configuration Register 0 -+ * This register contains the parameters required for functional setup -+ * of Physical Layer. -+ */ -+#define CDNS_PCIE_HPA_PHY_LAYER_CFG0 0x0400 -+#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK GENMASK(26, 24) -+#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \ -+ FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK, delay) -+#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK GENMASK(27, 27) -+ -+#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0 0x0420 -+ -+#define CDNS_PCIE_HPA_RP_MAX_IB 0x3 -+#define CDNS_PCIE_HPA_MAX_OB 15 -+ -+/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ -+#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) (((fn) * 0x0080) + ((bar) * 0x0008)) -+#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) (0x4 + ((fn) * 0x0080) + ((bar) * 0x0008)) -+ -+/* Miscellaneous offsets definitions */ -+#define CDNS_PCIE_HPA_TAG_MANAGEMENT 0x0 -+#define CDNS_PCIE_HPA_SLAVE_RESP 0x100 -+ -+#define I_ROOT_PORT_REQ_ID_REG 0x141c -+#define LM_HAL_SBSA_CTRL 0x1170 -+ -+#define I_PCIE_BUS_NUMBERS (CDNS_PCIE_HPA_RP_BASE + 0x18) -+#define CDNS_PCIE_EROM 0x18 -+#endif /* _PCIE_CADENCE_HPA_REGS_H */ -diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-hpa.c -new file mode 100644 -index 000000000000..f60a16938265 ---- /dev/null -+++ b/drivers/pci/controller/cadence/pcie-cadence-hpa.c -@@ -0,0 +1,167 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Cadence PCIe controller driver. -+ * -+ * Copyright (c) 2024, Cadence Design Systems -+ * Author: Manikandan K Pillai -+ */ -+#include -+#include -+ -+#include "pcie-cadence.h" -+ -+bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie) -+{ -+ u32 pl_reg_val; -+ -+ pl_reg_val = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_DBG_STS_REG0); -+ if (pl_reg_val & GENMASK(0, 0)) -+ return true; -+ return false; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_link_up); -+ -+void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie) -+{ -+ u32 delay = 0x3; -+ u32 ltssm_control_cap; -+ -+ /* Set the LTSSM Detect Quiet state min. delay to 2ms */ -+ ltssm_control_cap = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, -+ CDNS_PCIE_HPA_PHY_LAYER_CFG0); -+ ltssm_control_cap = ((ltssm_control_cap & -+ ~CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK) | -+ CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay)); -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, -+ CDNS_PCIE_HPA_PHY_LAYER_CFG0, ltssm_control_cap); -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_detect_quiet_min_delay_set); -+ -+void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, -+ u32 r, bool is_io, -+ u64 cpu_addr, u64 pci_addr, size_t size) -+{ -+ /* -+ * roundup_pow_of_two() returns an unsigned long, which is not suited -+ * for 64bit values -+ */ -+ u64 sz = 1ULL << fls64(size - 1); -+ int nbits = ilog2(sz); -+ u32 addr0, addr1, desc0, desc1, ctrl0; -+ -+ if (nbits < 8) -+ nbits = 8; -+ -+ /* Set the PCI address */ -+ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) | -+ (lower_32_bits(pci_addr) & GENMASK(31, 8)); -+ addr1 = upper_32_bits(pci_addr); -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), addr0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), addr1); -+ -+ /* Set the PCIe header descriptor */ -+ if (is_io) -+ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO; -+ else -+ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM; -+ desc1 = 0; -+ ctrl0 = 0; -+ -+ /* -+ * Whether Bit [26] is set or not inside DESC0 register of the outbound -+ * PCIe descriptor, the PCI function number must be set into -+ * Bits [31:24] of DESC1 anyway. -+ * -+ * In Root Complex mode, the function number is always 0 but in Endpoint -+ * mode, the PCIe controller may support more than one function. This -+ * function number needs to be set properly into the outbound PCIe -+ * descriptor. -+ * -+ * Besides, setting Bit [26] is mandatory when in Root Complex mode: -+ * then the driver must provide the bus, resp. device, number in -+ * Bits [31:24] of DESC1, resp. Bits[23:16] of DESC0. Like the function -+ * number, the device number is always 0 in Root Complex mode. -+ * -+ * However when in Endpoint mode, we can clear Bit [26] of DESC0, hence -+ * the PCIe controller will use the captured values for the bus and -+ * device numbers. -+ */ -+ if (pcie->is_rc) { -+ /* The device and function numbers are always 0 */ -+ desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); -+ ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; -+ } else { -+ /* -+ * Use captured values for bus and device numbers but still -+ * need to set the function number -+ */ -+ desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); -+ } -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); -+ -+ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | -+ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); -+ addr1 = upper_32_bits(cpu_addr); -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region); -+ -+void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, -+ u8 busnr, u8 fn, -+ u32 r, u64 cpu_addr) -+{ -+ u32 addr0, addr1, desc0, desc1, ctrl0; -+ -+ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG; -+ desc1 = 0; -+ ctrl0 = 0; -+ -+ /* See cdns_pcie_set_outbound_region() comments above */ -+ if (pcie->is_rc) { -+ desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); -+ ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; -+ } else { -+ desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); -+ } -+ -+ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(17) | -+ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); -+ addr1 = upper_32_bits(cpu_addr); -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region_for_normal_msg); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Cadence PCIe controller driver"); -diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c -index ebd5c3afdfcd..b067a3296dd3 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence-plat.c -+++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c -@@ -22,10 +22,6 @@ struct cdns_plat_pcie { - struct cdns_pcie *pcie; - }; - --struct cdns_plat_pcie_of_data { -- bool is_rc; --}; -- - static const struct of_device_id cdns_plat_pcie_of_match[]; - - static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) -diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c -index fb88a7ade412..a1eada56edba 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence.c -+++ b/drivers/pci/controller/cadence/pcie-cadence.c -@@ -23,6 +23,17 @@ u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) - } - EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability); - -+bool cdns_pcie_linkup(struct cdns_pcie *pcie) -+{ -+ u32 pl_reg_val; -+ -+ pl_reg_val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE); -+ if (pl_reg_val & GENMASK(0, 0)) -+ return true; -+ return false; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_linkup); -+ - void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) - { - u32 delay = 0x3; -diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h -index 23aa64df1980..277f3706a4f4 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence.h -+++ b/drivers/pci/controller/cadence/pcie-cadence.h -@@ -12,6 +12,7 @@ - #include - #include - #include "pcie-cadence-lga-regs.h" -+#include "pcie-cadence-hpa-regs.h" - - enum cdns_pcie_rp_bar { - RP_BAR_UNDEFINED = -1, -@@ -26,18 +27,57 @@ struct cdns_pcie_rp_ib_bar { - }; - - struct cdns_pcie; -+struct cdns_pcie_rc; -+ -+enum cdns_pcie_reg_bank { -+ REG_BANK_RP, -+ REG_BANK_IP_REG, -+ REG_BANK_IP_CFG_CTRL_REG, -+ REG_BANK_AXI_MASTER_COMMON, -+ REG_BANK_AXI_MASTER, -+ REG_BANK_AXI_SLAVE, -+ REG_BANK_AXI_HLS, -+ REG_BANK_AXI_RAS, -+ REG_BANK_AXI_DTI, -+ REG_BANKS_MAX, -+}; - - struct cdns_pcie_ops { -- int (*start_link)(struct cdns_pcie *pcie); -- void (*stop_link)(struct cdns_pcie *pcie); -- bool (*link_up)(struct cdns_pcie *pcie); -+ int (*start_link)(struct cdns_pcie *pcie); -+ void (*stop_link)(struct cdns_pcie *pcie); -+ bool (*link_up)(struct cdns_pcie *pcie); - u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); - }; - -+/** -+ * struct cdns_plat_pcie_of_data - Register bank offset for a platform -+ * @is_rc: controller is a RC -+ * @ip_reg_bank_offset: ip register bank start offset -+ * @ip_cfg_ctrl_reg_offset: ip config control register start offset -+ * @axi_mstr_common_offset: AXI master common register start offset -+ * @axi_slave_offset: AXI slave start offset -+ * @axi_master_offset: AXI master start offset -+ * @axi_hls_offset: AXI HLS offset start -+ * @axi_ras_offset: AXI RAS offset -+ * @axi_dti_offset: AXI DTI offset -+ */ -+struct cdns_plat_pcie_of_data { -+ u32 is_rc:1; -+ u32 ip_reg_bank_offset; -+ u32 ip_cfg_ctrl_reg_offset; -+ u32 axi_mstr_common_offset; -+ u32 axi_slave_offset; -+ u32 axi_master_offset; -+ u32 axi_hls_offset; -+ u32 axi_ras_offset; -+ u32 axi_dti_offset; -+}; -+ - /** - * struct cdns_pcie - private data for Cadence PCIe controller drivers - * @reg_base: IO mapped register base - * @mem_res: start/end offsets in the physical system memory to map PCI accesses -+ * @msg_res: Region for send message to map PCI accesses - * @dev: PCIe controller - * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint. - * @phy_count: number of supported PHY devices -@@ -45,16 +85,19 @@ struct cdns_pcie_ops { - * @link: list of pointers to corresponding device link representations - * @ops: Platform-specific ops to control various inputs from Cadence PCIe - * wrapper -+ * @cdns_pcie_reg_offsets: Register bank offsets for different SoC - */ - struct cdns_pcie { -- void __iomem *reg_base; -- struct resource *mem_res; -- struct device *dev; -- bool is_rc; -- int phy_count; -- struct phy **phy; -- struct device_link **link; -- const struct cdns_pcie_ops *ops; -+ void __iomem *reg_base; -+ struct resource *mem_res; -+ struct resource *msg_res; -+ struct device *dev; -+ bool is_rc; -+ int phy_count; -+ struct phy **phy; -+ struct device_link **link; -+ const struct cdns_pcie_ops *ops; -+ const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; - }; - - /** -@@ -70,6 +113,8 @@ struct cdns_pcie { - * available - * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 - * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk -+ * @ecam_supported: Whether the ECAM is supported -+ * @no_inbound_map: Whether inbound mapping is supported - */ - struct cdns_pcie_rc { - struct cdns_pcie pcie; -@@ -80,6 +125,8 @@ struct cdns_pcie_rc { - bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; - unsigned int quirk_retrain_flag:1; - unsigned int quirk_detect_quiet_flag:1; -+ unsigned int ecam_supported:1; -+ unsigned int no_inbound_map:1; - }; - - /** -@@ -132,6 +179,43 @@ struct cdns_pcie_ep { - unsigned int quirk_disable_flr:1; - }; - -+static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_pcie_reg_bank bank) -+{ -+ u32 offset = 0x0; -+ -+ switch (bank) { -+ case REG_BANK_RP: -+ offset = 0; -+ break; -+ case REG_BANK_IP_REG: -+ offset = pcie->cdns_pcie_reg_offsets->ip_reg_bank_offset; -+ break; -+ case REG_BANK_IP_CFG_CTRL_REG: -+ offset = pcie->cdns_pcie_reg_offsets->ip_cfg_ctrl_reg_offset; -+ break; -+ case REG_BANK_AXI_MASTER_COMMON: -+ offset = pcie->cdns_pcie_reg_offsets->axi_mstr_common_offset; -+ break; -+ case REG_BANK_AXI_MASTER: -+ offset = pcie->cdns_pcie_reg_offsets->axi_master_offset; -+ break; -+ case REG_BANK_AXI_SLAVE: -+ offset = pcie->cdns_pcie_reg_offsets->axi_slave_offset; -+ break; -+ case REG_BANK_AXI_HLS: -+ offset = pcie->cdns_pcie_reg_offsets->axi_hls_offset; -+ break; -+ case REG_BANK_AXI_RAS: -+ offset = pcie->cdns_pcie_reg_offsets->axi_ras_offset; -+ break; -+ case REG_BANK_AXI_DTI: -+ offset = pcie->cdns_pcie_reg_offsets->axi_dti_offset; -+ break; -+ default: -+ break; -+ } -+ return offset; -+} - - /* Register access */ - static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) -@@ -144,6 +228,27 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) - return readl(pcie->reg_base + reg); - } - -+static inline void cdns_pcie_hpa_writel(struct cdns_pcie *pcie, -+ enum cdns_pcie_reg_bank bank, -+ u32 reg, -+ u32 value) -+{ -+ u32 offset = cdns_reg_bank_to_off(pcie, bank); -+ -+ reg += offset; -+ writel(value, pcie->reg_base + reg); -+} -+ -+static inline u32 cdns_pcie_hpa_readl(struct cdns_pcie *pcie, -+ enum cdns_pcie_reg_bank bank, -+ u32 reg) -+{ -+ u32 offset = cdns_reg_bank_to_off(pcie, bank); -+ -+ reg += offset; -+ return readl(pcie->reg_base + reg); -+} -+ - static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) - { - void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); -@@ -233,6 +338,29 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) - return cdns_pcie_read_sz(addr, 0x2); - } - -+static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie, -+ u32 reg, u8 value) -+{ -+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; -+ -+ cdns_pcie_write_sz(addr, 0x1, value); -+} -+ -+static inline void cdns_pcie_hpa_rp_writew(struct cdns_pcie *pcie, -+ u32 reg, u16 value) -+{ -+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; -+ -+ cdns_pcie_write_sz(addr, 0x2, value); -+} -+ -+static inline u16 cdns_pcie_hpa_rp_readw(struct cdns_pcie *pcie, u32 reg) -+{ -+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; -+ -+ return cdns_pcie_read_sz(addr, 0x2); -+} -+ - /* Endpoint Function register access */ - static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, - u32 reg, u8 value) -@@ -297,6 +425,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); - void cdns_pcie_host_disable(struct cdns_pcie_rc *rc); - void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, - int where); -+int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc); - #else - static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) - { -@@ -313,6 +442,11 @@ static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) - return 0; - } - -+static inline int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) -+{ -+ return 0; -+} -+ - static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc) - { - } -@@ -327,6 +461,7 @@ static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int d - #if IS_ENABLED(CONFIG_PCIE_CADENCE_EP) - int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); - void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep); -+int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep); - #else - static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) - { -@@ -336,10 +471,17 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) - static inline void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep) - { - } -+ -+static inline int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep) -+{ -+ return 0; -+} -+ - #endif - --u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); --u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); -+u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); -+u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); -+bool cdns_pcie_linkup(struct cdns_pcie *pcie); - - void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); - -@@ -353,8 +495,23 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, - - void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); - void cdns_pcie_disable_phy(struct cdns_pcie *pcie); --int cdns_pcie_enable_phy(struct cdns_pcie *pcie); --int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); -+int cdns_pcie_enable_phy(struct cdns_pcie *pcie); -+int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); -+void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie); -+void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, -+ u32 r, bool is_io, -+ u64 cpu_addr, u64 pci_addr, size_t size); -+void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, -+ u8 busnr, u8 fn, -+ u32 r, u64 cpu_addr); -+int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc); -+void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, -+ int where); -+int cdns_pcie_hpa_host_start_link(struct cdns_pcie_rc *rc); -+int cdns_pcie_hpa_start_link(struct cdns_pcie *pcie); -+void cdns_pcie_hpa_stop_link(struct cdns_pcie *pcie); -+bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie); -+ - extern const struct dev_pm_ops cdns_pcie_pm_ops; - - #endif /* _PCIE_CADENCE_H */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch b/SPECS/linux-lts-kmhv2/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch new file mode 100644 index 0000000000..2109b174e4 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch @@ -0,0 +1,44 @@ +From 90e4dd06e790973bb6661abbcb3f3e584ec56f1e Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:05 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: add phy_intf_sel and ACTPHYIF + definitions + +Add definitions for the active PHY interface found in DMA hardware +feature register 0, and also used to configure the core in multi- +interface designs via phy_intf_sel. + +Signed-off-by: Russell King (Oracle) +Reviewed-by: Maxime Chevallier +Link: https://patch.msgid.link/E1vFt4X-0000000ChoY-30p9@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit 4a4692e9091867dd413764c7d81f09e8109a233a) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/common.h | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h +index acd7719506b6..a14df4269292 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/common.h ++++ b/drivers/net/ethernet/stmicro/stmmac/common.h +@@ -314,6 +314,16 @@ struct stmmac_safety_stats { + #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ + #define DEFAULT_DMA_PBL 8 + ++/* phy_intf_sel_i and ACTPHYIF encodings */ ++#define PHY_INTF_SEL_GMII_MII 0 ++#define PHY_INTF_SEL_RGMII 1 ++#define PHY_INTF_SEL_SGMII 2 ++#define PHY_INTF_SEL_TBI 3 ++#define PHY_INTF_SEL_RMII 4 ++#define PHY_INTF_SEL_RTBI 5 ++#define PHY_INTF_SEL_SMII 6 ++#define PHY_INTF_SEL_REVMII 7 ++ + /* MSI defines */ + #define STMMAC_MSI_VEC_MAX 32 + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch b/SPECS/linux-lts-kmhv2/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch new file mode 100644 index 0000000000..9a20bd485f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch @@ -0,0 +1,68 @@ +From 624275e49ff1dc397c4e821f30d8afcc4c8f621e Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:10 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: add stmmac_get_phy_intf_sel() + +Provide a function to translate the PHY interface mode to the +phy_intf_sel pin configuration for dwmac1000 and dwmac4 cores that +support multiple interfaces. We currently handle MII, GMII, RGMII, +SGMII, RMII and REVMII, but not TBI, RTBI nor SMII as drivers do not +appear to use these three and the driver doesn't currently support +these. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt4c-0000000Choe-3SII@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit b459790d3fd6d7ead31182ae0cd8632fe79deed6) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 + + .../net/ethernet/stmicro/stmmac/stmmac_main.c | 20 +++++++++++++++++++ + 2 files changed, 21 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h +index 865531d6cd3b..a628b5039448 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h +@@ -395,6 +395,7 @@ void stmmac_ptp_register(struct stmmac_priv *priv); + void stmmac_ptp_unregister(struct stmmac_priv *priv); + int stmmac_xdp_open(struct net_device *dev); + void stmmac_xdp_release(struct net_device *dev); ++int stmmac_get_phy_intf_sel(phy_interface_t interface); + int stmmac_resume(struct device *dev); + int stmmac_suspend(struct device *dev); + void stmmac_dvr_remove(struct device *dev); +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +index 41b270a48630..efe313a59b33 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +@@ -3035,6 +3035,26 @@ static void stmmac_check_ether_addr(struct stmmac_priv *priv) + } + } + ++int stmmac_get_phy_intf_sel(phy_interface_t interface) ++{ ++ int phy_intf_sel = -EINVAL; ++ ++ if (interface == PHY_INTERFACE_MODE_MII || ++ interface == PHY_INTERFACE_MODE_GMII) ++ phy_intf_sel = PHY_INTF_SEL_GMII_MII; ++ else if (phy_interface_mode_is_rgmii(interface)) ++ phy_intf_sel = PHY_INTF_SEL_RGMII; ++ else if (interface == PHY_INTERFACE_MODE_SGMII) ++ phy_intf_sel = PHY_INTF_SEL_SGMII; ++ else if (interface == PHY_INTERFACE_MODE_RMII) ++ phy_intf_sel = PHY_INTF_SEL_RMII; ++ else if (interface == PHY_INTERFACE_MODE_REVMII) ++ phy_intf_sel = PHY_INTF_SEL_REVMII; ++ ++ return phy_intf_sel; ++} ++EXPORT_SYMBOL_GPL(stmmac_get_phy_intf_sel); ++ + /** + * stmmac_init_dma_engine - DMA init. + * @priv: driver private structure +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0150-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch b/SPECS/linux-lts-kmhv2/0150-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch deleted file mode 100644 index 58b32f5050..0000000000 --- a/SPECS/linux-lts-kmhv2/0150-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 3fc48954f60468b378e31495b8a6b8c77c81f5f1 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:49:55 +0000 -Subject: [PATCH 150/467] UPSTREAM: net: stmmac: imx: use phylink's interface - mode for set_clk_tx_rate() - -imx_dwmac_set_clk_tx_rate() is passed the interface mode from phylink -which will be the same as plat_dat->phy_interface. Use the passed-in -interface mode rather than plat_dat->phy_interface. - -Reviewed-by: Maxime Chevallier -Tested-by: Maxime Chevallier -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt4N-0000000ChoM-1llp@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit dec568a36f9b16f0334aed8e95ec4225606830cc) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index 4268b9987237..147fa08d5b6e 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -195,9 +195,6 @@ static void imx_dwmac_exit(struct platform_device *pdev, void *priv) - static int imx_dwmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, - phy_interface_t interface, int speed) - { -- struct imx_priv_data *dwmac = bsp_priv; -- -- interface = dwmac->plat_dat->phy_interface; - if (interface == PHY_INTERFACE_MODE_RMII || - interface == PHY_INTERFACE_MODE_MII) - return 0; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch b/SPECS/linux-lts-kmhv2/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch new file mode 100644 index 0000000000..b7fa7e6a46 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch @@ -0,0 +1,90 @@ +From f194dd514161599163226c56b2674969caea19ca Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:15 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: add support for configuring the + phy_intf_sel inputs + +When dwmac is synthesised with support for multiple PHY interfaces, the +core provides phy_intf_sel inputs, sampled on reset, to configure the +PHY facing interface. Use stmmac_get_phy_intf_sel() in core code to +determine the dwmac phy_intf_sel input value, and provide a new +platform method called with this value just before we issue a soft +reset to the dwmac core. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt4h-0000000Chos-3wxX@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit 1b6aa81c85621d6b55099906585ff09a477203b8) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/stmmac_main.c | 34 +++++++++++++++++++ + include/linux/stmmac.h | 1 + + 2 files changed, 35 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +index efe313a59b33..0f7fda75f7fe 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +@@ -3055,6 +3055,36 @@ int stmmac_get_phy_intf_sel(phy_interface_t interface) + } + EXPORT_SYMBOL_GPL(stmmac_get_phy_intf_sel); + ++static int stmmac_prereset_configure(struct stmmac_priv *priv) ++{ ++ struct plat_stmmacenet_data *plat_dat = priv->plat; ++ phy_interface_t interface; ++ int phy_intf_sel, ret; ++ ++ if (!plat_dat->set_phy_intf_sel) ++ return 0; ++ ++ interface = plat_dat->phy_interface; ++ phy_intf_sel = stmmac_get_phy_intf_sel(interface); ++ if (phy_intf_sel < 0) { ++ netdev_err(priv->dev, ++ "failed to get phy_intf_sel for %s: %pe\n", ++ phy_modes(interface), ERR_PTR(phy_intf_sel)); ++ return phy_intf_sel; ++ } ++ ++ ret = plat_dat->set_phy_intf_sel(plat_dat->bsp_priv, phy_intf_sel); ++ if (ret == -EINVAL) ++ netdev_err(priv->dev, "platform does not support %s\n", ++ phy_modes(interface)); ++ else if (ret < 0) ++ netdev_err(priv->dev, ++ "platform failed to set interface %s: %pe\n", ++ phy_modes(interface), ERR_PTR(ret)); ++ ++ return ret; ++} ++ + /** + * stmmac_init_dma_engine - DMA init. + * @priv: driver private structure +@@ -3081,6 +3111,10 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) + if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) + priv->plat->dma_cfg->atds = 1; + ++ ret = stmmac_prereset_configure(priv); ++ if (ret) ++ return ret; ++ + ret = stmmac_reset(priv, priv->ioaddr); + if (ret) { + netdev_err(priv->dev, "Failed to reset the dma\n"); +diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h +index 7e989d0edead..8cbac4559f96 100644 +--- a/include/linux/stmmac.h ++++ b/include/linux/stmmac.h +@@ -250,6 +250,7 @@ struct plat_stmmacenet_data { + struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; + void (*get_interfaces)(struct stmmac_priv *priv, void *bsp_priv, + unsigned long *interfaces); ++ int (*set_phy_intf_sel)(void *priv, u8 phy_intf_sel); + int (*set_clk_tx_rate)(void *priv, struct clk *clk_tx_i, + phy_interface_t interface, int speed); + void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0151-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch b/SPECS/linux-lts-kmhv2/0151-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch deleted file mode 100644 index ddbd2ddb3b..0000000000 --- a/SPECS/linux-lts-kmhv2/0151-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 1d729e5a3d02a0b30f4cc2145934e9ad02a2593c Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:00 +0000 -Subject: [PATCH 151/467] UPSTREAM: net: stmmac: s32: move PHY_INTF_SEL_x - definitions out of the way - -S32's PHY_INTF_SEL_x definitions conflict with those for the dwmac -cores as they use a different bitmapping. Add a S32 prefix so that -they are unique. - -Signed-off-by: Russell King (Oracle) -Reviewed-by: Maxime Chevallier -Reviewed-by: Jan Petrous (OSS) -Link: https://patch.msgid.link/E1vFt4S-0000000ChoS-2Ahi@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit 553f23d1953527eb277efa902cd498131b2527e1) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c -index ee095ac13203..2b7ad64bfdf7 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c -@@ -24,10 +24,10 @@ - #define GMAC_INTF_RATE_125M 125000000 /* 125MHz */ - - /* SoC PHY interface control register */ --#define PHY_INTF_SEL_MII 0x00 --#define PHY_INTF_SEL_SGMII 0x01 --#define PHY_INTF_SEL_RGMII 0x02 --#define PHY_INTF_SEL_RMII 0x08 -+#define S32_PHY_INTF_SEL_MII 0x00 -+#define S32_PHY_INTF_SEL_SGMII 0x01 -+#define S32_PHY_INTF_SEL_RGMII 0x02 -+#define S32_PHY_INTF_SEL_RMII 0x08 - - struct s32_priv_data { - void __iomem *ioaddr; -@@ -40,7 +40,7 @@ struct s32_priv_data { - - static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac) - { -- writel(PHY_INTF_SEL_RGMII, gmac->ctrl_sts); -+ writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); - - dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode)); - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0152-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch b/SPECS/linux-lts-kmhv2/0152-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch deleted file mode 100644 index 89b1cdbb0e..0000000000 --- a/SPECS/linux-lts-kmhv2/0152-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 5ac0d54cbe08eb88695ec8feda51f1e2f957ee10 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:05 +0000 -Subject: [PATCH 152/467] UPSTREAM: net: stmmac: add phy_intf_sel and ACTPHYIF - definitions - -Add definitions for the active PHY interface found in DMA hardware -feature register 0, and also used to configure the core in multi- -interface designs via phy_intf_sel. - -Signed-off-by: Russell King (Oracle) -Reviewed-by: Maxime Chevallier -Link: https://patch.msgid.link/E1vFt4X-0000000ChoY-30p9@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit 4a4692e9091867dd413764c7d81f09e8109a233a) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/common.h | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h -index acd7719506b6..a14df4269292 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/common.h -+++ b/drivers/net/ethernet/stmicro/stmmac/common.h -@@ -314,6 +314,16 @@ struct stmmac_safety_stats { - #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ - #define DEFAULT_DMA_PBL 8 - -+/* phy_intf_sel_i and ACTPHYIF encodings */ -+#define PHY_INTF_SEL_GMII_MII 0 -+#define PHY_INTF_SEL_RGMII 1 -+#define PHY_INTF_SEL_SGMII 2 -+#define PHY_INTF_SEL_TBI 3 -+#define PHY_INTF_SEL_RMII 4 -+#define PHY_INTF_SEL_RTBI 5 -+#define PHY_INTF_SEL_SMII 6 -+#define PHY_INTF_SEL_REVMII 7 -+ - /* MSI defines */ - #define STMMAC_MSI_VEC_MAX 32 - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch b/SPECS/linux-lts-kmhv2/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch new file mode 100644 index 0000000000..9563df2a93 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch @@ -0,0 +1,70 @@ +From 89d282d18f9a93cdff176ee6469c67a8b11cb528 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:21 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: convert to PHY_INTF_SEL_xxx + +Convert dwmac-imx to use the PHY_INTF_SEL_xxx definitions rather than +constants via: +- ensuring that the prefix for the MASK and value definitions is the + same. +- using FIELD_PREP() to shift the PHY_INTF_SEL_xxx definition to the + appropriate bitfield. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt4n-0000000Choy-0IeG@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit 8233cc439779eac1d2682d334c1aa6bb6d95120c) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 23 ++++++++++++------- + 1 file changed, 15 insertions(+), 8 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index 147fa08d5b6e..4fbee59e7337 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -23,18 +23,25 @@ + #include "stmmac_platform.h" + + #define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16) +-#define GPR_ENET_QOS_INTF_SEL_MII (0x0 << 16) +-#define GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 16) +-#define GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 16) ++#define GPR_ENET_QOS_INTF_SEL_MASK GENMASK(20, 16) ++#define GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ ++ PHY_INTF_SEL_GMII_MII) ++#define GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ ++ PHY_INTF_SEL_RMII) ++#define GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ ++ PHY_INTF_SEL_RGMII) + #define GPR_ENET_QOS_CLK_GEN_EN (0x1 << 19) + #define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20) + #define GPR_ENET_QOS_RGMII_EN (0x1 << 21) + + #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0) +-#define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1) +-#define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1) +-#define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1) +-#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1) ++#define MX93_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(3, 1) ++#define MX93_GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ ++ PHY_INTF_SEL_GMII_MII) ++#define MX93_GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ ++ PHY_INTF_SEL_RMII) ++#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ ++ PHY_INTF_SEL_RGMII) + #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) + #define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0) + #define MX93_GPR_CLK_SEL_OFFSET (4) +@@ -241,7 +248,7 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode) + if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface)) + return; + +- iface &= MX93_GPR_ENET_QOS_INTF_MASK; ++ iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; + if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII) + return; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0153-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch b/SPECS/linux-lts-kmhv2/0153-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch deleted file mode 100644 index 7628db8ba4..0000000000 --- a/SPECS/linux-lts-kmhv2/0153-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 43838e019c5010025e2e2c06687a7e97c3153717 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:10 +0000 -Subject: [PATCH 153/467] UPSTREAM: net: stmmac: add stmmac_get_phy_intf_sel() - -Provide a function to translate the PHY interface mode to the -phy_intf_sel pin configuration for dwmac1000 and dwmac4 cores that -support multiple interfaces. We currently handle MII, GMII, RGMII, -SGMII, RMII and REVMII, but not TBI, RTBI nor SMII as drivers do not -appear to use these three and the driver doesn't currently support -these. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt4c-0000000Choe-3SII@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit b459790d3fd6d7ead31182ae0cd8632fe79deed6) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 + - .../net/ethernet/stmicro/stmmac/stmmac_main.c | 20 +++++++++++++++++++ - 2 files changed, 21 insertions(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h -index 865531d6cd3b..a628b5039448 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h -@@ -395,6 +395,7 @@ void stmmac_ptp_register(struct stmmac_priv *priv); - void stmmac_ptp_unregister(struct stmmac_priv *priv); - int stmmac_xdp_open(struct net_device *dev); - void stmmac_xdp_release(struct net_device *dev); -+int stmmac_get_phy_intf_sel(phy_interface_t interface); - int stmmac_resume(struct device *dev); - int stmmac_suspend(struct device *dev); - void stmmac_dvr_remove(struct device *dev); -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -index 41b270a48630..efe313a59b33 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -3035,6 +3035,26 @@ static void stmmac_check_ether_addr(struct stmmac_priv *priv) - } - } - -+int stmmac_get_phy_intf_sel(phy_interface_t interface) -+{ -+ int phy_intf_sel = -EINVAL; -+ -+ if (interface == PHY_INTERFACE_MODE_MII || -+ interface == PHY_INTERFACE_MODE_GMII) -+ phy_intf_sel = PHY_INTF_SEL_GMII_MII; -+ else if (phy_interface_mode_is_rgmii(interface)) -+ phy_intf_sel = PHY_INTF_SEL_RGMII; -+ else if (interface == PHY_INTERFACE_MODE_SGMII) -+ phy_intf_sel = PHY_INTF_SEL_SGMII; -+ else if (interface == PHY_INTERFACE_MODE_RMII) -+ phy_intf_sel = PHY_INTF_SEL_RMII; -+ else if (interface == PHY_INTERFACE_MODE_REVMII) -+ phy_intf_sel = PHY_INTF_SEL_REVMII; -+ -+ return phy_intf_sel; -+} -+EXPORT_SYMBOL_GPL(stmmac_get_phy_intf_sel); -+ - /** - * stmmac_init_dma_engine - DMA init. - * @priv: driver private structure --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch b/SPECS/linux-lts-kmhv2/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch new file mode 100644 index 0000000000..3546e04959 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch @@ -0,0 +1,151 @@ +From cc8ade8e3e83180c2b2c2458f61161c29f310f53 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:26 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use FIELD_PREP()/FIELD_GET() + for PHY_INTF_SEL_x + +Use FIELD_PREP()/FIELD_GET() in the functions to construct the PHY +interface selection bitfield or to extract its value. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt4s-0000000Chp4-0kwf@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit d73c1dccfb9909f0e2d517af887fe414ab421cea) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 44 +++++++++---------- + 1 file changed, 20 insertions(+), 24 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index 4fbee59e7337..f1cfccd4269c 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -24,24 +24,12 @@ + + #define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16) + #define GPR_ENET_QOS_INTF_SEL_MASK GENMASK(20, 16) +-#define GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ +- PHY_INTF_SEL_GMII_MII) +-#define GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ +- PHY_INTF_SEL_RMII) +-#define GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ +- PHY_INTF_SEL_RGMII) + #define GPR_ENET_QOS_CLK_GEN_EN (0x1 << 19) + #define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20) + #define GPR_ENET_QOS_RGMII_EN (0x1 << 21) + + #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0) + #define MX93_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(3, 1) +-#define MX93_GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ +- PHY_INTF_SEL_GMII_MII) +-#define MX93_GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ +- PHY_INTF_SEL_RMII) +-#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ +- PHY_INTF_SEL_RGMII) + #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) + #define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0) + #define MX93_GPR_CLK_SEL_OFFSET (4) +@@ -77,22 +65,24 @@ struct imx_priv_data { + static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + { + struct imx_priv_data *dwmac = plat_dat->bsp_priv; ++ u8 phy_intf_sel; + int val; + + switch (plat_dat->phy_interface) { + case PHY_INTERFACE_MODE_MII: +- val = GPR_ENET_QOS_INTF_SEL_MII; ++ phy_intf_sel = PHY_INTF_SEL_GMII_MII; ++ val = 0; + break; + case PHY_INTERFACE_MODE_RMII: +- val = GPR_ENET_QOS_INTF_SEL_RMII; +- val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL); ++ phy_intf_sel = PHY_INTF_SEL_RMII; ++ val = dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: +- val = GPR_ENET_QOS_INTF_SEL_RGMII | +- GPR_ENET_QOS_RGMII_EN; ++ phy_intf_sel = PHY_INTF_SEL_RGMII; ++ val = GPR_ENET_QOS_RGMII_EN; + break; + default: + pr_debug("imx dwmac doesn't support %s interface\n", +@@ -100,7 +90,9 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + return -EINVAL; + } + +- val |= GPR_ENET_QOS_CLK_GEN_EN; ++ val |= FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | ++ GPR_ENET_QOS_CLK_GEN_EN; ++ + return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, + GPR_ENET_QOS_INTF_MODE_MASK, val); + }; +@@ -117,11 +109,12 @@ imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + { + struct imx_priv_data *dwmac = plat_dat->bsp_priv; ++ u8 phy_intf_sel; + int val, ret; + + switch (plat_dat->phy_interface) { + case PHY_INTERFACE_MODE_MII: +- val = MX93_GPR_ENET_QOS_INTF_SEL_MII; ++ phy_intf_sel = PHY_INTF_SEL_GMII_MII; + break; + case PHY_INTERFACE_MODE_RMII: + if (dwmac->rmii_refclk_ext) { +@@ -132,13 +125,13 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + if (ret) + return ret; + } +- val = MX93_GPR_ENET_QOS_INTF_SEL_RMII; ++ phy_intf_sel = PHY_INTF_SEL_RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: +- val = MX93_GPR_ENET_QOS_INTF_SEL_RGMII; ++ phy_intf_sel = PHY_INTF_SEL_RGMII; + break; + default: + dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n", +@@ -146,7 +139,9 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + return -EINVAL; + } + +- val |= MX93_GPR_ENET_QOS_CLK_GEN_EN; ++ val = FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | ++ MX93_GPR_ENET_QOS_CLK_GEN_EN; ++ + return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, + MX93_GPR_ENET_QOS_INTF_MODE_MASK, val); + }; +@@ -248,8 +243,8 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode) + if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface)) + return; + +- iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; +- if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII) ++ if (FIELD_GET(MX93_GPR_ENET_QOS_INTF_SEL_MASK, iface) != ++ PHY_INTF_SEL_RGMII) + return; + + old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG); +@@ -262,6 +257,7 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode) + readl(dwmac->base_addr + MAC_CTRL_REG); + + usleep_range(10, 20); ++ iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; + iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN; + regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, + MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0154-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch b/SPECS/linux-lts-kmhv2/0154-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch deleted file mode 100644 index e57e4171fb..0000000000 --- a/SPECS/linux-lts-kmhv2/0154-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch +++ /dev/null @@ -1,90 +0,0 @@ -From ea8b437fd179a8f307c0e49128898b0424718763 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:15 +0000 -Subject: [PATCH 154/467] UPSTREAM: net: stmmac: add support for configuring - the phy_intf_sel inputs - -When dwmac is synthesised with support for multiple PHY interfaces, the -core provides phy_intf_sel inputs, sampled on reset, to configure the -PHY facing interface. Use stmmac_get_phy_intf_sel() in core code to -determine the dwmac phy_intf_sel input value, and provide a new -platform method called with this value just before we issue a soft -reset to the dwmac core. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt4h-0000000Chos-3wxX@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit 1b6aa81c85621d6b55099906585ff09a477203b8) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/stmmac_main.c | 34 +++++++++++++++++++ - include/linux/stmmac.h | 1 + - 2 files changed, 35 insertions(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -index efe313a59b33..0f7fda75f7fe 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -3055,6 +3055,36 @@ int stmmac_get_phy_intf_sel(phy_interface_t interface) - } - EXPORT_SYMBOL_GPL(stmmac_get_phy_intf_sel); - -+static int stmmac_prereset_configure(struct stmmac_priv *priv) -+{ -+ struct plat_stmmacenet_data *plat_dat = priv->plat; -+ phy_interface_t interface; -+ int phy_intf_sel, ret; -+ -+ if (!plat_dat->set_phy_intf_sel) -+ return 0; -+ -+ interface = plat_dat->phy_interface; -+ phy_intf_sel = stmmac_get_phy_intf_sel(interface); -+ if (phy_intf_sel < 0) { -+ netdev_err(priv->dev, -+ "failed to get phy_intf_sel for %s: %pe\n", -+ phy_modes(interface), ERR_PTR(phy_intf_sel)); -+ return phy_intf_sel; -+ } -+ -+ ret = plat_dat->set_phy_intf_sel(plat_dat->bsp_priv, phy_intf_sel); -+ if (ret == -EINVAL) -+ netdev_err(priv->dev, "platform does not support %s\n", -+ phy_modes(interface)); -+ else if (ret < 0) -+ netdev_err(priv->dev, -+ "platform failed to set interface %s: %pe\n", -+ phy_modes(interface), ERR_PTR(ret)); -+ -+ return ret; -+} -+ - /** - * stmmac_init_dma_engine - DMA init. - * @priv: driver private structure -@@ -3081,6 +3111,10 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) - if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) - priv->plat->dma_cfg->atds = 1; - -+ ret = stmmac_prereset_configure(priv); -+ if (ret) -+ return ret; -+ - ret = stmmac_reset(priv, priv->ioaddr); - if (ret) { - netdev_err(priv->dev, "Failed to reset the dma\n"); -diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h -index 7e989d0edead..8cbac4559f96 100644 ---- a/include/linux/stmmac.h -+++ b/include/linux/stmmac.h -@@ -250,6 +250,7 @@ struct plat_stmmacenet_data { - struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; - void (*get_interfaces)(struct stmmac_priv *priv, void *bsp_priv, - unsigned long *interfaces); -+ int (*set_phy_intf_sel)(void *priv, u8 phy_intf_sel); - int (*set_clk_tx_rate)(void *priv, struct clk *clk_tx_i, - phy_interface_t interface, int speed); - void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch b/SPECS/linux-lts-kmhv2/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch new file mode 100644 index 0000000000..133ab7846d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch @@ -0,0 +1,140 @@ +From c242a53cab013ff50b42785236d0b703b63c9e37 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:31 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use + stmmac_get_phy_intf_sel() + +i.MX implementations other than IMX8DXL involve setting the dwmac core +phy_intf_sel input. Use stmmac_get_phy_intf_sel() to decode the PHY +interface mode to the phy_intf_sel value, validating the result, and +passing it into the implementation specific .set_intf_mode() method +rather than each .set_intf_mode() method doing this. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt4x-0000000ChpA-1Edr@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit c012710c14a70dfa21691e2542d18dd4b621c518) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 43 +++++++++++-------- + 1 file changed, 25 insertions(+), 18 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index f1cfccd4269c..dc28486a7af0 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -45,7 +45,8 @@ struct imx_dwmac_ops { + bool mac_rgmii_txclk_auto_adj; + + int (*fix_soc_reset)(struct stmmac_priv *priv, void __iomem *ioaddr); +- int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat); ++ int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat, ++ u8 phy_intf_sel); + void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); + }; + +@@ -62,26 +63,23 @@ struct imx_priv_data { + struct plat_stmmacenet_data *plat_dat; + }; + +-static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) ++static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, ++ u8 phy_intf_sel) + { + struct imx_priv_data *dwmac = plat_dat->bsp_priv; +- u8 phy_intf_sel; + int val; + + switch (plat_dat->phy_interface) { + case PHY_INTERFACE_MODE_MII: +- phy_intf_sel = PHY_INTF_SEL_GMII_MII; + val = 0; + break; + case PHY_INTERFACE_MODE_RMII: +- phy_intf_sel = PHY_INTF_SEL_RMII; + val = dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: +- phy_intf_sel = PHY_INTF_SEL_RGMII; + val = GPR_ENET_QOS_RGMII_EN; + break; + default: +@@ -98,7 +96,8 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + }; + + static int +-imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) ++imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat, ++ u8 phy_intf_sel) + { + int ret = 0; + +@@ -106,16 +105,13 @@ imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + return ret; + } + +-static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) ++static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat, ++ u8 phy_intf_sel) + { + struct imx_priv_data *dwmac = plat_dat->bsp_priv; +- u8 phy_intf_sel; + int val, ret; + + switch (plat_dat->phy_interface) { +- case PHY_INTERFACE_MODE_MII: +- phy_intf_sel = PHY_INTF_SEL_GMII_MII; +- break; + case PHY_INTERFACE_MODE_RMII: + if (dwmac->rmii_refclk_ext) { + ret = regmap_clear_bits(dwmac->intf_regmap, +@@ -125,13 +121,12 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + if (ret) + return ret; + } +- phy_intf_sel = PHY_INTF_SEL_RMII; + break; ++ case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: +- phy_intf_sel = PHY_INTF_SEL_RGMII; + break; + default: + dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n", +@@ -176,12 +171,24 @@ static int imx_dwmac_init(struct platform_device *pdev, void *priv) + { + struct plat_stmmacenet_data *plat_dat; + struct imx_priv_data *dwmac = priv; +- int ret; +- +- plat_dat = dwmac->plat_dat; ++ phy_interface_t interface; ++ int phy_intf_sel, ret; + + if (dwmac->ops->set_intf_mode) { +- ret = dwmac->ops->set_intf_mode(plat_dat); ++ plat_dat = dwmac->plat_dat; ++ interface = plat_dat->phy_interface; ++ ++ phy_intf_sel = stmmac_get_phy_intf_sel(interface); ++ if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && ++ phy_intf_sel != PHY_INTF_SEL_RGMII && ++ phy_intf_sel != PHY_INTF_SEL_RMII) { ++ dev_dbg(dwmac->dev, ++ "imx dwmac doesn't support %s interface\n", ++ phy_modes(interface)); ++ return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; ++ } ++ ++ ret = dwmac->ops->set_intf_mode(plat_dat, phy_intf_sel); + if (ret) + return ret; + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0155-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch b/SPECS/linux-lts-kmhv2/0155-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch deleted file mode 100644 index 4686086a36..0000000000 --- a/SPECS/linux-lts-kmhv2/0155-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 298cb039696cadbf544bfbe91d55631386fabfa1 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:21 +0000 -Subject: [PATCH 155/467] UPSTREAM: net: stmmac: imx: convert to - PHY_INTF_SEL_xxx - -Convert dwmac-imx to use the PHY_INTF_SEL_xxx definitions rather than -constants via: -- ensuring that the prefix for the MASK and value definitions is the - same. -- using FIELD_PREP() to shift the PHY_INTF_SEL_xxx definition to the - appropriate bitfield. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt4n-0000000Choy-0IeG@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit 8233cc439779eac1d2682d334c1aa6bb6d95120c) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 23 ++++++++++++------- - 1 file changed, 15 insertions(+), 8 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index 147fa08d5b6e..4fbee59e7337 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -23,18 +23,25 @@ - #include "stmmac_platform.h" - - #define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16) --#define GPR_ENET_QOS_INTF_SEL_MII (0x0 << 16) --#define GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 16) --#define GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 16) -+#define GPR_ENET_QOS_INTF_SEL_MASK GENMASK(20, 16) -+#define GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ -+ PHY_INTF_SEL_GMII_MII) -+#define GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ -+ PHY_INTF_SEL_RMII) -+#define GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ -+ PHY_INTF_SEL_RGMII) - #define GPR_ENET_QOS_CLK_GEN_EN (0x1 << 19) - #define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20) - #define GPR_ENET_QOS_RGMII_EN (0x1 << 21) - - #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0) --#define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1) --#define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1) --#define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1) --#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1) -+#define MX93_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(3, 1) -+#define MX93_GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ -+ PHY_INTF_SEL_GMII_MII) -+#define MX93_GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ -+ PHY_INTF_SEL_RMII) -+#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ -+ PHY_INTF_SEL_RGMII) - #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) - #define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0) - #define MX93_GPR_CLK_SEL_OFFSET (4) -@@ -241,7 +248,7 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode) - if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface)) - return; - -- iface &= MX93_GPR_ENET_QOS_INTF_MASK; -+ iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; - if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII) - return; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch b/SPECS/linux-lts-kmhv2/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch new file mode 100644 index 0000000000..cc5171568d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch @@ -0,0 +1,114 @@ +From 38044c901de858463843f7c8cfab808a34627f56 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:36 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: simplify set_intf_mode() + implementations + +Simplify the set_intf_mode() implementations, testing the phy_intf_sel +value rather than the PHY interface mode. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt52-0000000ChpG-1bsd@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit 35103babce3036058cd9ed8674c98e9ab397d715) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 67 ++++++------------- + 1 file changed, 19 insertions(+), 48 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index dc28486a7af0..d69be9de4468 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -67,29 +67,15 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, + u8 phy_intf_sel) + { + struct imx_priv_data *dwmac = plat_dat->bsp_priv; +- int val; +- +- switch (plat_dat->phy_interface) { +- case PHY_INTERFACE_MODE_MII: +- val = 0; +- break; +- case PHY_INTERFACE_MODE_RMII: +- val = dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL; +- break; +- case PHY_INTERFACE_MODE_RGMII: +- case PHY_INTERFACE_MODE_RGMII_ID: +- case PHY_INTERFACE_MODE_RGMII_RXID: +- case PHY_INTERFACE_MODE_RGMII_TXID: +- val = GPR_ENET_QOS_RGMII_EN; +- break; +- default: +- pr_debug("imx dwmac doesn't support %s interface\n", +- phy_modes(plat_dat->phy_interface)); +- return -EINVAL; +- } ++ unsigned int val; + +- val |= FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | +- GPR_ENET_QOS_CLK_GEN_EN; ++ val = FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | ++ GPR_ENET_QOS_CLK_GEN_EN; ++ ++ if (phy_intf_sel == PHY_INTF_SEL_RMII && !dwmac->rmii_refclk_ext) ++ val |= GPR_ENET_QOS_CLK_TX_CLK_SEL; ++ else if (phy_intf_sel == PHY_INTF_SEL_RGMII) ++ val |= GPR_ENET_QOS_RGMII_EN; + + return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, + GPR_ENET_QOS_INTF_MODE_MASK, val); +@@ -99,39 +85,24 @@ static int + imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat, + u8 phy_intf_sel) + { +- int ret = 0; +- + /* TBD: depends on imx8dxl scu interfaces to be upstreamed */ +- return ret; ++ return 0; + } + + static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat, + u8 phy_intf_sel) + { + struct imx_priv_data *dwmac = plat_dat->bsp_priv; +- int val, ret; +- +- switch (plat_dat->phy_interface) { +- case PHY_INTERFACE_MODE_RMII: +- if (dwmac->rmii_refclk_ext) { +- ret = regmap_clear_bits(dwmac->intf_regmap, +- dwmac->intf_reg_off + +- MX93_GPR_CLK_SEL_OFFSET, +- MX93_GPR_ENET_QOS_CLK_SEL_MASK); +- if (ret) +- return ret; +- } +- break; +- case PHY_INTERFACE_MODE_MII: +- case PHY_INTERFACE_MODE_RGMII: +- case PHY_INTERFACE_MODE_RGMII_ID: +- case PHY_INTERFACE_MODE_RGMII_RXID: +- case PHY_INTERFACE_MODE_RGMII_TXID: +- break; +- default: +- dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n", +- phy_modes(plat_dat->phy_interface)); +- return -EINVAL; ++ unsigned int val; ++ int ret; ++ ++ if (phy_intf_sel == PHY_INTF_SEL_RMII && dwmac->rmii_refclk_ext) { ++ ret = regmap_clear_bits(dwmac->intf_regmap, ++ dwmac->intf_reg_off + ++ MX93_GPR_CLK_SEL_OFFSET, ++ MX93_GPR_ENET_QOS_CLK_SEL_MASK); ++ if (ret) ++ return ret; + } + + val = FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch b/SPECS/linux-lts-kmhv2/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch new file mode 100644 index 0000000000..7f2c908494 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch @@ -0,0 +1,100 @@ +From 3c89184f3302aafeabc618409bf916aa970f4f16 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:41 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: cleanup arguments for + set_intf_mode() method + +Pass the imx_priv_data instead of the plat_stmmacenet_data into the +set_intf_mode() SoC specific methods. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt57-0000000ChpL-25kS@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit 38cd4e84b369c11680966fdea129e11dbb28a6ec) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 22 +++++++------------ + 1 file changed, 8 insertions(+), 14 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index d69be9de4468..ae1b73e1bcb2 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -39,14 +39,15 @@ + #define RMII_RESET_SPEED (0x3 << 14) + #define CTRL_SPEED_MASK GENMASK(15, 14) + ++struct imx_priv_data; ++ + struct imx_dwmac_ops { + u32 addr_width; + u32 flags; + bool mac_rgmii_txclk_auto_adj; + + int (*fix_soc_reset)(struct stmmac_priv *priv, void __iomem *ioaddr); +- int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat, +- u8 phy_intf_sel); ++ int (*set_intf_mode)(struct imx_priv_data *dwmac, u8 phy_intf_sel); + void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); + }; + +@@ -63,10 +64,8 @@ struct imx_priv_data { + struct plat_stmmacenet_data *plat_dat; + }; + +-static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, +- u8 phy_intf_sel) ++static int imx8mp_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) + { +- struct imx_priv_data *dwmac = plat_dat->bsp_priv; + unsigned int val; + + val = FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | +@@ -82,17 +81,14 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, + }; + + static int +-imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat, +- u8 phy_intf_sel) ++imx8dxl_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) + { + /* TBD: depends on imx8dxl scu interfaces to be upstreamed */ + return 0; + } + +-static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat, +- u8 phy_intf_sel) ++static int imx93_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) + { +- struct imx_priv_data *dwmac = plat_dat->bsp_priv; + unsigned int val; + int ret; + +@@ -140,14 +136,12 @@ static int imx_dwmac_clks_config(void *priv, bool enabled) + + static int imx_dwmac_init(struct platform_device *pdev, void *priv) + { +- struct plat_stmmacenet_data *plat_dat; + struct imx_priv_data *dwmac = priv; + phy_interface_t interface; + int phy_intf_sel, ret; + + if (dwmac->ops->set_intf_mode) { +- plat_dat = dwmac->plat_dat; +- interface = plat_dat->phy_interface; ++ interface = dwmac->plat_dat->phy_interface; + + phy_intf_sel = stmmac_get_phy_intf_sel(interface); + if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && +@@ -159,7 +153,7 @@ static int imx_dwmac_init(struct platform_device *pdev, void *priv) + return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; + } + +- ret = dwmac->ops->set_intf_mode(plat_dat, phy_intf_sel); ++ ret = dwmac->ops->set_intf_mode(dwmac, phy_intf_sel); + if (ret) + return ret; + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0156-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch b/SPECS/linux-lts-kmhv2/0156-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch deleted file mode 100644 index ff69081e5a..0000000000 --- a/SPECS/linux-lts-kmhv2/0156-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 96a2fbe70c985e615419f7e5872b429885c2832b Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:26 +0000 -Subject: [PATCH 156/467] UPSTREAM: net: stmmac: imx: use - FIELD_PREP()/FIELD_GET() for PHY_INTF_SEL_x - -Use FIELD_PREP()/FIELD_GET() in the functions to construct the PHY -interface selection bitfield or to extract its value. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt4s-0000000Chp4-0kwf@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit d73c1dccfb9909f0e2d517af887fe414ab421cea) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 44 +++++++++---------- - 1 file changed, 20 insertions(+), 24 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index 4fbee59e7337..f1cfccd4269c 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -24,24 +24,12 @@ - - #define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16) - #define GPR_ENET_QOS_INTF_SEL_MASK GENMASK(20, 16) --#define GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ -- PHY_INTF_SEL_GMII_MII) --#define GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ -- PHY_INTF_SEL_RMII) --#define GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ -- PHY_INTF_SEL_RGMII) - #define GPR_ENET_QOS_CLK_GEN_EN (0x1 << 19) - #define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20) - #define GPR_ENET_QOS_RGMII_EN (0x1 << 21) - - #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0) - #define MX93_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(3, 1) --#define MX93_GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ -- PHY_INTF_SEL_GMII_MII) --#define MX93_GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ -- PHY_INTF_SEL_RMII) --#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ -- PHY_INTF_SEL_RGMII) - #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) - #define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0) - #define MX93_GPR_CLK_SEL_OFFSET (4) -@@ -77,22 +65,24 @@ struct imx_priv_data { - static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - { - struct imx_priv_data *dwmac = plat_dat->bsp_priv; -+ u8 phy_intf_sel; - int val; - - switch (plat_dat->phy_interface) { - case PHY_INTERFACE_MODE_MII: -- val = GPR_ENET_QOS_INTF_SEL_MII; -+ phy_intf_sel = PHY_INTF_SEL_GMII_MII; -+ val = 0; - break; - case PHY_INTERFACE_MODE_RMII: -- val = GPR_ENET_QOS_INTF_SEL_RMII; -- val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL); -+ phy_intf_sel = PHY_INTF_SEL_RMII; -+ val = dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: -- val = GPR_ENET_QOS_INTF_SEL_RGMII | -- GPR_ENET_QOS_RGMII_EN; -+ phy_intf_sel = PHY_INTF_SEL_RGMII; -+ val = GPR_ENET_QOS_RGMII_EN; - break; - default: - pr_debug("imx dwmac doesn't support %s interface\n", -@@ -100,7 +90,9 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - return -EINVAL; - } - -- val |= GPR_ENET_QOS_CLK_GEN_EN; -+ val |= FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | -+ GPR_ENET_QOS_CLK_GEN_EN; -+ - return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, - GPR_ENET_QOS_INTF_MODE_MASK, val); - }; -@@ -117,11 +109,12 @@ imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - { - struct imx_priv_data *dwmac = plat_dat->bsp_priv; -+ u8 phy_intf_sel; - int val, ret; - - switch (plat_dat->phy_interface) { - case PHY_INTERFACE_MODE_MII: -- val = MX93_GPR_ENET_QOS_INTF_SEL_MII; -+ phy_intf_sel = PHY_INTF_SEL_GMII_MII; - break; - case PHY_INTERFACE_MODE_RMII: - if (dwmac->rmii_refclk_ext) { -@@ -132,13 +125,13 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - if (ret) - return ret; - } -- val = MX93_GPR_ENET_QOS_INTF_SEL_RMII; -+ phy_intf_sel = PHY_INTF_SEL_RMII; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: -- val = MX93_GPR_ENET_QOS_INTF_SEL_RGMII; -+ phy_intf_sel = PHY_INTF_SEL_RGMII; - break; - default: - dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n", -@@ -146,7 +139,9 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - return -EINVAL; - } - -- val |= MX93_GPR_ENET_QOS_CLK_GEN_EN; -+ val = FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | -+ MX93_GPR_ENET_QOS_CLK_GEN_EN; -+ - return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, - MX93_GPR_ENET_QOS_INTF_MODE_MASK, val); - }; -@@ -248,8 +243,8 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode) - if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface)) - return; - -- iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; -- if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII) -+ if (FIELD_GET(MX93_GPR_ENET_QOS_INTF_SEL_MASK, iface) != -+ PHY_INTF_SEL_RGMII) - return; - - old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG); -@@ -262,6 +257,7 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode) - readl(dwmac->base_addr + MAC_CTRL_REG); - - usleep_range(10, 20); -+ iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; - iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN; - regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, - MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch b/SPECS/linux-lts-kmhv2/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch new file mode 100644 index 0000000000..20bb16df38 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch @@ -0,0 +1,80 @@ +From e0a6c2e873b5d2ba2e3a62461407c4523f488812 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:46 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use ->set_phy_intf_sel() + +Rather than placing the phy_intf_sel() setup in the ->init() method, +move it to the new ->set_phy_intf_sel() method. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt5C-0000000ChpR-2kAB@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit eaca1a4dc51e5e4979e45a4ad72a1c2a88a80a72) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 38 +++++-------------- + 1 file changed, 10 insertions(+), 28 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index ae1b73e1bcb2..db288fbd5a4d 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -134,36 +134,19 @@ static int imx_dwmac_clks_config(void *priv, bool enabled) + return ret; + } + +-static int imx_dwmac_init(struct platform_device *pdev, void *priv) ++static int imx_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) + { +- struct imx_priv_data *dwmac = priv; +- phy_interface_t interface; +- int phy_intf_sel, ret; +- +- if (dwmac->ops->set_intf_mode) { +- interface = dwmac->plat_dat->phy_interface; +- +- phy_intf_sel = stmmac_get_phy_intf_sel(interface); +- if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && +- phy_intf_sel != PHY_INTF_SEL_RGMII && +- phy_intf_sel != PHY_INTF_SEL_RMII) { +- dev_dbg(dwmac->dev, +- "imx dwmac doesn't support %s interface\n", +- phy_modes(interface)); +- return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; +- } ++ struct imx_priv_data *dwmac = bsp_priv; + +- ret = dwmac->ops->set_intf_mode(dwmac, phy_intf_sel); +- if (ret) +- return ret; +- } ++ if (!dwmac->ops->set_intf_mode) ++ return 0; + +- return 0; +-} ++ if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && ++ phy_intf_sel != PHY_INTF_SEL_RGMII && ++ phy_intf_sel != PHY_INTF_SEL_RMII) ++ return -EINVAL; + +-static void imx_dwmac_exit(struct platform_device *pdev, void *priv) +-{ +- /* nothing to do now */ ++ return dwmac->ops->set_intf_mode(dwmac, phy_intf_sel); + } + + static int imx_dwmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, +@@ -342,8 +325,7 @@ static int imx_dwmac_probe(struct platform_device *pdev) + plat_dat->tx_queues_cfg[i].tbs_en = 1; + + plat_dat->host_dma_width = dwmac->ops->addr_width; +- plat_dat->init = imx_dwmac_init; +- plat_dat->exit = imx_dwmac_exit; ++ plat_dat->set_phy_intf_sel = imx_set_phy_intf_sel; + plat_dat->clks_config = imx_dwmac_clks_config; + plat_dat->bsp_priv = dwmac; + dwmac->plat_dat = plat_dat; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0157-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch b/SPECS/linux-lts-kmhv2/0157-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch deleted file mode 100644 index 948f2ff114..0000000000 --- a/SPECS/linux-lts-kmhv2/0157-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch +++ /dev/null @@ -1,140 +0,0 @@ -From a7b4a86b0a6221000c68f097653ff86de2485ea0 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:31 +0000 -Subject: [PATCH 157/467] UPSTREAM: net: stmmac: imx: use - stmmac_get_phy_intf_sel() - -i.MX implementations other than IMX8DXL involve setting the dwmac core -phy_intf_sel input. Use stmmac_get_phy_intf_sel() to decode the PHY -interface mode to the phy_intf_sel value, validating the result, and -passing it into the implementation specific .set_intf_mode() method -rather than each .set_intf_mode() method doing this. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt4x-0000000ChpA-1Edr@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit c012710c14a70dfa21691e2542d18dd4b621c518) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 43 +++++++++++-------- - 1 file changed, 25 insertions(+), 18 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index f1cfccd4269c..dc28486a7af0 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -45,7 +45,8 @@ struct imx_dwmac_ops { - bool mac_rgmii_txclk_auto_adj; - - int (*fix_soc_reset)(struct stmmac_priv *priv, void __iomem *ioaddr); -- int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat); -+ int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat, -+ u8 phy_intf_sel); - void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); - }; - -@@ -62,26 +63,23 @@ struct imx_priv_data { - struct plat_stmmacenet_data *plat_dat; - }; - --static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) -+static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, -+ u8 phy_intf_sel) - { - struct imx_priv_data *dwmac = plat_dat->bsp_priv; -- u8 phy_intf_sel; - int val; - - switch (plat_dat->phy_interface) { - case PHY_INTERFACE_MODE_MII: -- phy_intf_sel = PHY_INTF_SEL_GMII_MII; - val = 0; - break; - case PHY_INTERFACE_MODE_RMII: -- phy_intf_sel = PHY_INTF_SEL_RMII; - val = dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: -- phy_intf_sel = PHY_INTF_SEL_RGMII; - val = GPR_ENET_QOS_RGMII_EN; - break; - default: -@@ -98,7 +96,8 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - }; - - static int --imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) -+imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat, -+ u8 phy_intf_sel) - { - int ret = 0; - -@@ -106,16 +105,13 @@ imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - return ret; - } - --static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) -+static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat, -+ u8 phy_intf_sel) - { - struct imx_priv_data *dwmac = plat_dat->bsp_priv; -- u8 phy_intf_sel; - int val, ret; - - switch (plat_dat->phy_interface) { -- case PHY_INTERFACE_MODE_MII: -- phy_intf_sel = PHY_INTF_SEL_GMII_MII; -- break; - case PHY_INTERFACE_MODE_RMII: - if (dwmac->rmii_refclk_ext) { - ret = regmap_clear_bits(dwmac->intf_regmap, -@@ -125,13 +121,12 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - if (ret) - return ret; - } -- phy_intf_sel = PHY_INTF_SEL_RMII; - break; -+ case PHY_INTERFACE_MODE_MII: - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: -- phy_intf_sel = PHY_INTF_SEL_RGMII; - break; - default: - dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n", -@@ -176,12 +171,24 @@ static int imx_dwmac_init(struct platform_device *pdev, void *priv) - { - struct plat_stmmacenet_data *plat_dat; - struct imx_priv_data *dwmac = priv; -- int ret; -- -- plat_dat = dwmac->plat_dat; -+ phy_interface_t interface; -+ int phy_intf_sel, ret; - - if (dwmac->ops->set_intf_mode) { -- ret = dwmac->ops->set_intf_mode(plat_dat); -+ plat_dat = dwmac->plat_dat; -+ interface = plat_dat->phy_interface; -+ -+ phy_intf_sel = stmmac_get_phy_intf_sel(interface); -+ if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && -+ phy_intf_sel != PHY_INTF_SEL_RGMII && -+ phy_intf_sel != PHY_INTF_SEL_RMII) { -+ dev_dbg(dwmac->dev, -+ "imx dwmac doesn't support %s interface\n", -+ phy_modes(interface)); -+ return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; -+ } -+ -+ ret = dwmac->ops->set_intf_mode(plat_dat, phy_intf_sel); - if (ret) - return ret; - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0158-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch b/SPECS/linux-lts-kmhv2/0158-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch deleted file mode 100644 index 4fca5088f0..0000000000 --- a/SPECS/linux-lts-kmhv2/0158-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch +++ /dev/null @@ -1,114 +0,0 @@ -From a4d4ff59a90369776a587bea80bb089b9b3ff2e4 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:36 +0000 -Subject: [PATCH 158/467] UPSTREAM: net: stmmac: imx: simplify set_intf_mode() - implementations - -Simplify the set_intf_mode() implementations, testing the phy_intf_sel -value rather than the PHY interface mode. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt52-0000000ChpG-1bsd@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit 35103babce3036058cd9ed8674c98e9ab397d715) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 67 ++++++------------- - 1 file changed, 19 insertions(+), 48 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index dc28486a7af0..d69be9de4468 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -67,29 +67,15 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, - u8 phy_intf_sel) - { - struct imx_priv_data *dwmac = plat_dat->bsp_priv; -- int val; -- -- switch (plat_dat->phy_interface) { -- case PHY_INTERFACE_MODE_MII: -- val = 0; -- break; -- case PHY_INTERFACE_MODE_RMII: -- val = dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL; -- break; -- case PHY_INTERFACE_MODE_RGMII: -- case PHY_INTERFACE_MODE_RGMII_ID: -- case PHY_INTERFACE_MODE_RGMII_RXID: -- case PHY_INTERFACE_MODE_RGMII_TXID: -- val = GPR_ENET_QOS_RGMII_EN; -- break; -- default: -- pr_debug("imx dwmac doesn't support %s interface\n", -- phy_modes(plat_dat->phy_interface)); -- return -EINVAL; -- } -+ unsigned int val; - -- val |= FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | -- GPR_ENET_QOS_CLK_GEN_EN; -+ val = FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | -+ GPR_ENET_QOS_CLK_GEN_EN; -+ -+ if (phy_intf_sel == PHY_INTF_SEL_RMII && !dwmac->rmii_refclk_ext) -+ val |= GPR_ENET_QOS_CLK_TX_CLK_SEL; -+ else if (phy_intf_sel == PHY_INTF_SEL_RGMII) -+ val |= GPR_ENET_QOS_RGMII_EN; - - return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, - GPR_ENET_QOS_INTF_MODE_MASK, val); -@@ -99,39 +85,24 @@ static int - imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat, - u8 phy_intf_sel) - { -- int ret = 0; -- - /* TBD: depends on imx8dxl scu interfaces to be upstreamed */ -- return ret; -+ return 0; - } - - static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat, - u8 phy_intf_sel) - { - struct imx_priv_data *dwmac = plat_dat->bsp_priv; -- int val, ret; -- -- switch (plat_dat->phy_interface) { -- case PHY_INTERFACE_MODE_RMII: -- if (dwmac->rmii_refclk_ext) { -- ret = regmap_clear_bits(dwmac->intf_regmap, -- dwmac->intf_reg_off + -- MX93_GPR_CLK_SEL_OFFSET, -- MX93_GPR_ENET_QOS_CLK_SEL_MASK); -- if (ret) -- return ret; -- } -- break; -- case PHY_INTERFACE_MODE_MII: -- case PHY_INTERFACE_MODE_RGMII: -- case PHY_INTERFACE_MODE_RGMII_ID: -- case PHY_INTERFACE_MODE_RGMII_RXID: -- case PHY_INTERFACE_MODE_RGMII_TXID: -- break; -- default: -- dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n", -- phy_modes(plat_dat->phy_interface)); -- return -EINVAL; -+ unsigned int val; -+ int ret; -+ -+ if (phy_intf_sel == PHY_INTF_SEL_RMII && dwmac->rmii_refclk_ext) { -+ ret = regmap_clear_bits(dwmac->intf_regmap, -+ dwmac->intf_reg_off + -+ MX93_GPR_CLK_SEL_OFFSET, -+ MX93_GPR_ENET_QOS_CLK_SEL_MASK); -+ if (ret) -+ return ret; - } - - val = FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch b/SPECS/linux-lts-kmhv2/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch new file mode 100644 index 0000000000..f73e1f62b4 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch @@ -0,0 +1,59 @@ +From d219e86b2ba446033884ed9b3f3cb9d0edcd98ef Mon Sep 17 00:00:00 2001 +From: Nilay Shroff +Date: Fri, 20 Feb 2026 12:32:27 +0530 +Subject: [RUYI PATCH] UPSTREAM: powerpc/pci: Initialize msi_addr_mask for + OF-created PCI devices + +Recent changes replaced the use of no_64bit_msi with msi_addr_mask. As a +result, msi_addr_mask is now expected to be initialized to DMA_BIT_MASK(64) +when a pci_dev is set up. However, this initialization was missed on +powerpc due to differences in the device initialization path compared to +other (x86) architecture. Due to this, now PCI device probe method fails on +powerpc system. + +On powerpc systems, struct pci_dev instances are created from device tree +nodes via of_create_pci_dev(). Because msi_addr_mask was not initialized +there, it remained zero. Later, during MSI setup, msi_verify_entries() +validates the programmed MSI address against pdev->msi_addr_mask. Since the +mask was not set correctly, the validation fails, causing PCI driver probe +failures for devices on powerpc systems. + +Initialize pdev->msi_addr_mask to DMA_BIT_MASK(64) in of_create_pci_dev() +so that MSI address validation succeeds and device probe works as expected. + +Fixes: 386ced19e9a3 ("PCI/MSI: Convert the boolean no_64bit_msi flag to a DMA address mask") +Signed-off-by: Nilay Shroff +Signed-off-by: Bjorn Helgaas +Tested-by: Venkat Rao Bagalkote +Tested-by: Nam Cao +Reviewed-by: Nam Cao +Reviewed-by: Vivian Wang +Acked-by: Madhavan Srinivasan +Link: https://patch.msgid.link/20260220070239.1693303-2-nilay@linux.ibm.com +(cherry picked from commit 2185904ff8b5da76a4353e5d1236caa78e0d98e3) +Signed-off-by: Han Gao +--- + arch/powerpc/kernel/pci_of_scan.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c +index 756043dd06e9..fb9fbf0d1796 100644 +--- a/arch/powerpc/kernel/pci_of_scan.c ++++ b/arch/powerpc/kernel/pci_of_scan.c +@@ -212,6 +212,13 @@ struct pci_dev *of_create_pci_dev(struct device_node *node, + dev->error_state = pci_channel_io_normal; + dev->dma_mask = 0xffffffff; + ++ /* ++ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit ++ * if MSI (rather than MSI-X) capability does not have ++ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. ++ */ ++ dev->msi_addr_mask = DMA_BIT_MASK(64); ++ + /* Early fixups, before probing the BARs */ + pci_fixup_device(pci_fixup_early, dev); + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0159-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch b/SPECS/linux-lts-kmhv2/0159-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch deleted file mode 100644 index 416094c8bf..0000000000 --- a/SPECS/linux-lts-kmhv2/0159-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 651b057371e02ed78100a1da8b724c5996480add Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:41 +0000 -Subject: [PATCH 159/467] UPSTREAM: net: stmmac: imx: cleanup arguments for - set_intf_mode() method - -Pass the imx_priv_data instead of the plat_stmmacenet_data into the -set_intf_mode() SoC specific methods. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt57-0000000ChpL-25kS@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit 38cd4e84b369c11680966fdea129e11dbb28a6ec) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 22 +++++++------------ - 1 file changed, 8 insertions(+), 14 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index d69be9de4468..ae1b73e1bcb2 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -39,14 +39,15 @@ - #define RMII_RESET_SPEED (0x3 << 14) - #define CTRL_SPEED_MASK GENMASK(15, 14) - -+struct imx_priv_data; -+ - struct imx_dwmac_ops { - u32 addr_width; - u32 flags; - bool mac_rgmii_txclk_auto_adj; - - int (*fix_soc_reset)(struct stmmac_priv *priv, void __iomem *ioaddr); -- int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat, -- u8 phy_intf_sel); -+ int (*set_intf_mode)(struct imx_priv_data *dwmac, u8 phy_intf_sel); - void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); - }; - -@@ -63,10 +64,8 @@ struct imx_priv_data { - struct plat_stmmacenet_data *plat_dat; - }; - --static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, -- u8 phy_intf_sel) -+static int imx8mp_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) - { -- struct imx_priv_data *dwmac = plat_dat->bsp_priv; - unsigned int val; - - val = FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | -@@ -82,17 +81,14 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, - }; - - static int --imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat, -- u8 phy_intf_sel) -+imx8dxl_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) - { - /* TBD: depends on imx8dxl scu interfaces to be upstreamed */ - return 0; - } - --static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat, -- u8 phy_intf_sel) -+static int imx93_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) - { -- struct imx_priv_data *dwmac = plat_dat->bsp_priv; - unsigned int val; - int ret; - -@@ -140,14 +136,12 @@ static int imx_dwmac_clks_config(void *priv, bool enabled) - - static int imx_dwmac_init(struct platform_device *pdev, void *priv) - { -- struct plat_stmmacenet_data *plat_dat; - struct imx_priv_data *dwmac = priv; - phy_interface_t interface; - int phy_intf_sel, ret; - - if (dwmac->ops->set_intf_mode) { -- plat_dat = dwmac->plat_dat; -- interface = plat_dat->phy_interface; -+ interface = dwmac->plat_dat->phy_interface; - - phy_intf_sel = stmmac_get_phy_intf_sel(interface); - if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && -@@ -159,7 +153,7 @@ static int imx_dwmac_init(struct platform_device *pdev, void *priv) - return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; - } - -- ret = dwmac->ops->set_intf_mode(plat_dat, phy_intf_sel); -+ ret = dwmac->ops->set_intf_mode(dwmac, phy_intf_sel); - if (ret) - return ret; - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch b/SPECS/linux-lts-kmhv2/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch new file mode 100644 index 0000000000..e75eecbde3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch @@ -0,0 +1,51 @@ +From 9e9a5cb4c3cd15b6b321a0ec71d41d8318cfd254 Mon Sep 17 00:00:00 2001 +From: Nilay Shroff +Date: Fri, 20 Feb 2026 12:32:28 +0530 +Subject: [RUYI PATCH] UPSTREAM: sparc/PCI: Initialize msi_addr_mask for + OF-created PCI devices + +Recent changes replaced the use of no_64bit_msi with msi_addr_mask, which +is now expected to be initialized to DMA_BIT_MASK(64) during PCI device +setup. On SPARC systems, this initialization was inadvertently missed for +devices instantiated from device tree nodes, leaving msi_addr_mask unset +for OF-created pci_dev instances. As a result, MSI address validation fails +during probe, causing affected devices to fail initialization. + +Initialize pdev->msi_addr_mask to DMA_BIT_MASK(64) in of_create_pci_dev() +so that MSI address validation succeeds and PCI device probing works as +expected. + +Fixes: 386ced19e9a3 ("PCI/MSI: Convert the boolean no_64bit_msi flag to a DMA address mask") +Signed-off-by: Nilay Shroff +Signed-off-by: Bjorn Helgaas +Tested-by: Han Gao # SPARC Enterprise T5220 +Tested-by: Nathaniel Roach # SPARC T5-2 +Reviewed-by: Vivian Wang +Link: https://patch.msgid.link/20260220070239.1693303-3-nilay@linux.ibm.com +(cherry picked from commit 147dae12985947cdb9e1918142f06482c5077a81) +Signed-off-by: Han Gao +--- + arch/sparc/kernel/pci.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c +index b290107170e9..a4815d544781 100644 +--- a/arch/sparc/kernel/pci.c ++++ b/arch/sparc/kernel/pci.c +@@ -355,6 +355,13 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, + dev->error_state = pci_channel_io_normal; + dev->dma_mask = 0xffffffff; + ++ /* ++ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit ++ * if MSI (rather than MSI-X) capability does not have ++ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. ++ */ ++ dev->msi_addr_mask = DMA_BIT_MASK(64); ++ + if (of_node_name_eq(node, "pci")) { + /* a PCI-PCI bridge */ + dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0160-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch b/SPECS/linux-lts-kmhv2/0160-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch deleted file mode 100644 index cb7b7536b5..0000000000 --- a/SPECS/linux-lts-kmhv2/0160-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch +++ /dev/null @@ -1,80 +0,0 @@ -From dd51d5c75d4f912be30523c694e72ffe87fa3d99 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:46 +0000 -Subject: [PATCH 160/467] UPSTREAM: net: stmmac: imx: use ->set_phy_intf_sel() - -Rather than placing the phy_intf_sel() setup in the ->init() method, -move it to the new ->set_phy_intf_sel() method. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt5C-0000000ChpR-2kAB@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit eaca1a4dc51e5e4979e45a4ad72a1c2a88a80a72) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 38 +++++-------------- - 1 file changed, 10 insertions(+), 28 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index ae1b73e1bcb2..db288fbd5a4d 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -134,36 +134,19 @@ static int imx_dwmac_clks_config(void *priv, bool enabled) - return ret; - } - --static int imx_dwmac_init(struct platform_device *pdev, void *priv) -+static int imx_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) - { -- struct imx_priv_data *dwmac = priv; -- phy_interface_t interface; -- int phy_intf_sel, ret; -- -- if (dwmac->ops->set_intf_mode) { -- interface = dwmac->plat_dat->phy_interface; -- -- phy_intf_sel = stmmac_get_phy_intf_sel(interface); -- if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && -- phy_intf_sel != PHY_INTF_SEL_RGMII && -- phy_intf_sel != PHY_INTF_SEL_RMII) { -- dev_dbg(dwmac->dev, -- "imx dwmac doesn't support %s interface\n", -- phy_modes(interface)); -- return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; -- } -+ struct imx_priv_data *dwmac = bsp_priv; - -- ret = dwmac->ops->set_intf_mode(dwmac, phy_intf_sel); -- if (ret) -- return ret; -- } -+ if (!dwmac->ops->set_intf_mode) -+ return 0; - -- return 0; --} -+ if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && -+ phy_intf_sel != PHY_INTF_SEL_RGMII && -+ phy_intf_sel != PHY_INTF_SEL_RMII) -+ return -EINVAL; - --static void imx_dwmac_exit(struct platform_device *pdev, void *priv) --{ -- /* nothing to do now */ -+ return dwmac->ops->set_intf_mode(dwmac, phy_intf_sel); - } - - static int imx_dwmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, -@@ -342,8 +325,7 @@ static int imx_dwmac_probe(struct platform_device *pdev) - plat_dat->tx_queues_cfg[i].tbs_en = 1; - - plat_dat->host_dma_width = dwmac->ops->addr_width; -- plat_dat->init = imx_dwmac_init; -- plat_dat->exit = imx_dwmac_exit; -+ plat_dat->set_phy_intf_sel = imx_set_phy_intf_sel; - plat_dat->clks_config = imx_dwmac_clks_config; - plat_dat->bsp_priv = dwmac; - dwmac->plat_dat = plat_dat; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch b/SPECS/linux-lts-kmhv2/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch new file mode 100644 index 0000000000..9f8cb3b4b0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch @@ -0,0 +1,4919 @@ +From 94993ae18a9db8b1a6f5939a8bfc465712f0e760 Mon Sep 17 00:00:00 2001 +From: Thierry Reding +Date: Wed, 29 Oct 2025 17:33:30 +0100 +Subject: [RUYI PATCH] UPSTREAM: syscore: Pass context data to callbacks + +Several drivers can benefit from registering per-instance data along +with the syscore operations. To achieve this, move the modifiable fields +out of the syscore_ops structure and into a separate struct syscore that +can be registered with the framework. Add a void * driver data field for +drivers to store contextual data that will be passed to the syscore ops. + +Acked-by: Rafael J. Wysocki (Intel) +Signed-off-by: Thierry Reding +(cherry picked from commit a97fbc3ee3e2a536fafaff04f21f45472db71769) +Signed-off-by: Han Gao +--- + arch/arm/mach-exynos/mcpm-exynos.c | 12 ++-- + arch/arm/mach-exynos/suspend.c | 48 +++++++------ + arch/arm/mach-pxa/generic.h | 6 +- + arch/arm/mach-pxa/irq.c | 10 ++- + arch/arm/mach-pxa/mfp-pxa2xx.c | 10 ++- + arch/arm/mach-pxa/mfp-pxa3xx.c | 10 ++- + arch/arm/mach-pxa/pxa25x.c | 4 +- + arch/arm/mach-pxa/pxa27x.c | 4 +- + arch/arm/mach-pxa/pxa3xx.c | 4 +- + arch/arm/mach-pxa/smemc.c | 12 ++-- + arch/arm/mach-s3c/irq-pm-s3c64xx.c | 12 ++-- + arch/arm/mach-s5pv210/pm.c | 10 ++- + arch/arm/mach-versatile/integrator_ap.c | 12 ++-- + arch/arm/mm/cache-b15-rac.c | 12 ++-- + arch/loongarch/kernel/smp.c | 12 ++-- + arch/mips/alchemy/common/dbdma.c | 12 ++-- + arch/mips/alchemy/common/irq.c | 24 ++++--- + arch/mips/alchemy/common/usb.c | 12 ++-- + arch/mips/pci/pci-alchemy.c | 16 +++-- + arch/powerpc/platforms/cell/spu_base.c | 10 ++- + arch/powerpc/platforms/powermac/pic.c | 12 ++-- + arch/powerpc/sysdev/fsl_lbc.c | 12 ++-- + arch/powerpc/sysdev/fsl_pci.c | 12 ++-- + arch/powerpc/sysdev/ipic.c | 12 ++-- + arch/powerpc/sysdev/mpic.c | 14 ++-- + arch/powerpc/sysdev/mpic_timer.c | 10 ++- + arch/sh/mm/pmb.c | 10 ++- + arch/x86/events/amd/ibs.c | 12 ++-- + arch/x86/hyperv/hv_init.c | 12 ++-- + arch/x86/kernel/amd_gart_64.c | 10 ++- + arch/x86/kernel/apic/apic.c | 12 ++-- + arch/x86/kernel/apic/io_apic.c | 17 +++-- + arch/x86/kernel/cpu/aperfmperf.c | 20 +++--- + arch/x86/kernel/cpu/intel_epb.c | 16 +++-- + arch/x86/kernel/cpu/mce/core.c | 14 ++-- + arch/x86/kernel/cpu/microcode/core.c | 15 ++++- + arch/x86/kernel/cpu/mtrr/legacy.c | 12 ++-- + arch/x86/kernel/cpu/umwait.c | 10 ++- + arch/x86/kernel/i8237.c | 10 ++- + arch/x86/kernel/i8259.c | 14 ++-- + arch/x86/kernel/kvm.c | 12 ++-- + drivers/acpi/pci_link.c | 10 ++- + drivers/acpi/sleep.c | 12 ++-- + drivers/base/firmware_loader/main.c | 12 ++-- + drivers/base/syscore.c | 82 ++++++++++++----------- + drivers/bus/mvebu-mbus.c | 16 +++-- + drivers/clk/at91/pmc.c | 12 ++-- + drivers/clk/imx/clk-vf610.c | 12 ++-- + drivers/clk/ingenic/jz4725b-cgu.c | 2 +- + drivers/clk/ingenic/jz4740-cgu.c | 2 +- + drivers/clk/ingenic/jz4755-cgu.c | 2 +- + drivers/clk/ingenic/jz4760-cgu.c | 2 +- + drivers/clk/ingenic/jz4770-cgu.c | 2 +- + drivers/clk/ingenic/jz4780-cgu.c | 2 +- + drivers/clk/ingenic/pm.c | 14 ++-- + drivers/clk/ingenic/pm.h | 2 +- + drivers/clk/ingenic/tcu.c | 12 ++-- + drivers/clk/ingenic/x1000-cgu.c | 2 +- + drivers/clk/ingenic/x1830-cgu.c | 2 +- + drivers/clk/mvebu/common.c | 12 ++-- + drivers/clk/rockchip/clk-rk3288.c | 12 ++-- + drivers/clk/samsung/clk-s5pv210-audss.c | 12 ++-- + drivers/clk/samsung/clk.c | 12 ++-- + drivers/clk/tegra/clk-tegra210.c | 12 ++-- + drivers/clocksource/timer-armada-370-xp.c | 12 ++-- + drivers/cpuidle/cpuidle-psci.c | 12 ++-- + drivers/gpio/gpio-mxc.c | 12 ++-- + drivers/gpio/gpio-pxa.c | 12 ++-- + drivers/gpio/gpio-sa1100.c | 12 ++-- + drivers/hv/vmbus_drv.c | 14 ++-- + drivers/iommu/amd/init.c | 16 +++-- + drivers/iommu/intel/iommu.c | 12 ++-- + drivers/irqchip/exynos-combiner.c | 14 ++-- + drivers/irqchip/irq-armada-370-xp.c | 12 ++-- + drivers/irqchip/irq-bcm7038-l1.c | 12 ++-- + drivers/irqchip/irq-gic-v3-its.c | 12 ++-- + drivers/irqchip/irq-i8259.c | 12 ++-- + drivers/irqchip/irq-imx-gpcv2.c | 16 +++-- + drivers/irqchip/irq-loongson-eiointc.c | 12 ++-- + drivers/irqchip/irq-loongson-htpic.c | 10 ++- + drivers/irqchip/irq-loongson-htvec.c | 12 ++-- + drivers/irqchip/irq-loongson-pch-lpc.c | 12 ++-- + drivers/irqchip/irq-loongson-pch-pic.c | 12 ++-- + drivers/irqchip/irq-mchp-eic.c | 12 ++-- + drivers/irqchip/irq-mst-intc.c | 12 ++-- + drivers/irqchip/irq-mtk-cirq.c | 12 ++-- + drivers/irqchip/irq-renesas-rzg2l.c | 12 ++-- + drivers/irqchip/irq-sa11x0.c | 12 ++-- + drivers/irqchip/irq-sifive-plic.c | 12 ++-- + drivers/irqchip/irq-sun6i-r.c | 18 +++-- + drivers/irqchip/irq-tegra.c | 12 ++-- + drivers/irqchip/irq-vic.c | 12 ++-- + drivers/leds/trigger/ledtrig-cpu.c | 14 ++-- + drivers/macintosh/via-pmu.c | 12 ++-- + drivers/power/reset/sc27xx-poweroff.c | 10 ++- + drivers/sh/clk/core.c | 10 ++- + drivers/sh/intc/core.c | 12 ++-- + drivers/soc/bcm/brcmstb/biuctrl.c | 12 ++-- + drivers/soc/tegra/pmc.c | 17 +++-- + drivers/thermal/intel/intel_hfi.c | 12 ++-- + drivers/xen/xen-acpi-processor.c | 12 ++-- + include/linux/syscore_ops.h | 15 +++-- + kernel/cpu_pm.c | 12 ++-- + kernel/irq/generic-chip.c | 14 ++-- + kernel/irq/pm.c | 11 ++- + kernel/printk/printk.c | 11 ++- + kernel/time/sched_clock.c | 22 ++++-- + kernel/time/timekeeping.c | 22 ++++-- + virt/kvm/kvm_main.c | 18 +++-- + 109 files changed, 898 insertions(+), 470 deletions(-) + +diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c +index fd0dbeb93357..cb7d8a7b14e0 100644 +--- a/arch/arm/mach-exynos/mcpm-exynos.c ++++ b/arch/arm/mach-exynos/mcpm-exynos.c +@@ -215,7 +215,7 @@ static const struct of_device_id exynos_dt_mcpm_match[] = { + {}, + }; + +-static void exynos_mcpm_setup_entry_point(void) ++static void exynos_mcpm_setup_entry_point(void *data) + { + /* + * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr +@@ -228,10 +228,14 @@ static void exynos_mcpm_setup_entry_point(void) + __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8); + } + +-static struct syscore_ops exynos_mcpm_syscore_ops = { ++static const struct syscore_ops exynos_mcpm_syscore_ops = { + .resume = exynos_mcpm_setup_entry_point, + }; + ++static struct syscore exynos_mcpm_syscore = { ++ .ops = &exynos_mcpm_syscore_ops, ++}; ++ + static int __init exynos_mcpm_init(void) + { + struct device_node *node; +@@ -300,9 +304,9 @@ static int __init exynos_mcpm_init(void) + pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i)); + } + +- exynos_mcpm_setup_entry_point(); ++ exynos_mcpm_setup_entry_point(NULL); + +- register_syscore_ops(&exynos_mcpm_syscore_ops); ++ register_syscore(&exynos_mcpm_syscore); + + return ret; + } +diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c +index 150a1e56dcae..22d723553f62 100644 +--- a/arch/arm/mach-exynos/suspend.c ++++ b/arch/arm/mach-exynos/suspend.c +@@ -53,9 +53,9 @@ struct exynos_pm_data { + + void (*pm_prepare)(void); + void (*pm_resume_prepare)(void); +- void (*pm_resume)(void); +- int (*pm_suspend)(void); + int (*cpu_suspend)(unsigned long); ++ ++ const struct syscore_ops *syscore_ops; + }; + + /* Used only on Exynos542x/5800 */ +@@ -376,7 +376,7 @@ static void exynos5420_pm_prepare(void) + } + + +-static int exynos_pm_suspend(void) ++static int exynos_pm_suspend(void *data) + { + exynos_pm_central_suspend(); + +@@ -390,7 +390,7 @@ static int exynos_pm_suspend(void) + return 0; + } + +-static int exynos5420_pm_suspend(void) ++static int exynos5420_pm_suspend(void *data) + { + u32 this_cluster; + +@@ -408,7 +408,7 @@ static int exynos5420_pm_suspend(void) + return 0; + } + +-static void exynos_pm_resume(void) ++static void exynos_pm_resume(void *data) + { + u32 cpuid = read_cpuid_part(); + +@@ -429,7 +429,7 @@ static void exynos_pm_resume(void) + exynos_set_delayed_reset_assertion(true); + } + +-static void exynos3250_pm_resume(void) ++static void exynos3250_pm_resume(void *data) + { + u32 cpuid = read_cpuid_part(); + +@@ -473,7 +473,7 @@ static void exynos5420_prepare_pm_resume(void) + } + } + +-static void exynos5420_pm_resume(void) ++static void exynos5420_pm_resume(void *data) + { + unsigned long tmp; + +@@ -596,41 +596,52 @@ static const struct platform_suspend_ops exynos_suspend_ops = { + .valid = suspend_valid_only_mem, + }; + ++static const struct syscore_ops exynos3250_syscore_ops = { ++ .suspend = exynos_pm_suspend, ++ .resume = exynos3250_pm_resume, ++}; ++ + static const struct exynos_pm_data exynos3250_pm_data = { + .wkup_irq = exynos3250_wkup_irq, + .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), +- .pm_suspend = exynos_pm_suspend, +- .pm_resume = exynos3250_pm_resume, + .pm_prepare = exynos3250_pm_prepare, + .cpu_suspend = exynos3250_cpu_suspend, ++ .syscore_ops = &exynos3250_syscore_ops, ++}; ++ ++static const struct syscore_ops exynos_syscore_ops = { ++ .suspend = exynos_pm_suspend, ++ .resume = exynos_pm_resume, + }; + + static const struct exynos_pm_data exynos4_pm_data = { + .wkup_irq = exynos4_wkup_irq, + .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), +- .pm_suspend = exynos_pm_suspend, +- .pm_resume = exynos_pm_resume, + .pm_prepare = exynos_pm_prepare, + .cpu_suspend = exynos_cpu_suspend, ++ .syscore_ops = &exynos_syscore_ops, + }; + + static const struct exynos_pm_data exynos5250_pm_data = { + .wkup_irq = exynos5250_wkup_irq, + .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), +- .pm_suspend = exynos_pm_suspend, +- .pm_resume = exynos_pm_resume, + .pm_prepare = exynos_pm_prepare, + .cpu_suspend = exynos_cpu_suspend, ++ .syscore_ops = &exynos_syscore_ops, ++}; ++ ++static const struct syscore_ops exynos5420_syscore_ops = { ++ .resume = exynos5420_pm_resume, ++ .suspend = exynos5420_pm_suspend, + }; + + static const struct exynos_pm_data exynos5420_pm_data = { + .wkup_irq = exynos5250_wkup_irq, + .wake_disable_mask = (0x7F << 7) | (0x1F << 1), + .pm_resume_prepare = exynos5420_prepare_pm_resume, +- .pm_resume = exynos5420_pm_resume, +- .pm_suspend = exynos5420_pm_suspend, + .pm_prepare = exynos5420_pm_prepare, + .cpu_suspend = exynos5420_cpu_suspend, ++ .syscore_ops = &exynos5420_syscore_ops, + }; + + static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { +@@ -656,7 +667,7 @@ static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { + { /*sentinel*/ }, + }; + +-static struct syscore_ops exynos_pm_syscore_ops; ++static struct syscore exynos_pm_syscore; + + void __init exynos_pm_init(void) + { +@@ -684,10 +695,9 @@ void __init exynos_pm_init(void) + tmp |= pm_data->wake_disable_mask; + pmu_raw_writel(tmp, S5P_WAKEUP_MASK); + +- exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; +- exynos_pm_syscore_ops.resume = pm_data->pm_resume; ++ exynos_pm_syscore.ops = pm_data->syscore_ops; + +- register_syscore_ops(&exynos_pm_syscore_ops); ++ register_syscore(&exynos_pm_syscore); + suspend_set_ops(&exynos_suspend_ops); + + /* +diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h +index c9c2c46ecead..caad4fca8de3 100644 +--- a/arch/arm/mach-pxa/generic.h ++++ b/arch/arm/mach-pxa/generic.h +@@ -34,9 +34,9 @@ extern void __init pxa27x_map_io(void); + extern void __init pxa3xx_init_irq(void); + extern void __init pxa3xx_map_io(void); + +-extern struct syscore_ops pxa_irq_syscore_ops; +-extern struct syscore_ops pxa2xx_mfp_syscore_ops; +-extern struct syscore_ops pxa3xx_mfp_syscore_ops; ++extern struct syscore pxa_irq_syscore; ++extern struct syscore pxa2xx_mfp_syscore; ++extern struct syscore pxa3xx_mfp_syscore; + + void __init pxa_set_ffuart_info(void *info); + void __init pxa_set_btuart_info(void *info); +diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c +index 5bfce8aa4102..99acebbbf065 100644 +--- a/arch/arm/mach-pxa/irq.c ++++ b/arch/arm/mach-pxa/irq.c +@@ -178,7 +178,7 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) + static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; + static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; + +-static int pxa_irq_suspend(void) ++static int pxa_irq_suspend(void *data) + { + int i; + +@@ -197,7 +197,7 @@ static int pxa_irq_suspend(void) + return 0; + } + +-static void pxa_irq_resume(void) ++static void pxa_irq_resume(void *data) + { + int i; + +@@ -219,11 +219,15 @@ static void pxa_irq_resume(void) + #define pxa_irq_resume NULL + #endif + +-struct syscore_ops pxa_irq_syscore_ops = { ++static const struct syscore_ops pxa_irq_syscore_ops = { + .suspend = pxa_irq_suspend, + .resume = pxa_irq_resume, + }; + ++struct syscore pxa_irq_syscore = { ++ .ops = &pxa_irq_syscore_ops, ++}; ++ + #ifdef CONFIG_OF + static const struct of_device_id intc_ids[] __initconst = { + { .compatible = "marvell,pxa-intc", }, +diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c +index f5a3d890f682..d1347055fbe4 100644 +--- a/arch/arm/mach-pxa/mfp-pxa2xx.c ++++ b/arch/arm/mach-pxa/mfp-pxa2xx.c +@@ -346,7 +346,7 @@ static unsigned long saved_gpdr[4]; + static unsigned long saved_gplr[4]; + static unsigned long saved_pgsr[4]; + +-static int pxa2xx_mfp_suspend(void) ++static int pxa2xx_mfp_suspend(void *data) + { + int i; + +@@ -385,7 +385,7 @@ static int pxa2xx_mfp_suspend(void) + return 0; + } + +-static void pxa2xx_mfp_resume(void) ++static void pxa2xx_mfp_resume(void *data) + { + int i; + +@@ -404,11 +404,15 @@ static void pxa2xx_mfp_resume(void) + #define pxa2xx_mfp_resume NULL + #endif + +-struct syscore_ops pxa2xx_mfp_syscore_ops = { ++static const struct syscore_ops pxa2xx_mfp_syscore_ops = { + .suspend = pxa2xx_mfp_suspend, + .resume = pxa2xx_mfp_resume, + }; + ++struct syscore pxa2xx_mfp_syscore = { ++ .ops = &pxa2xx_mfp_syscore_ops, ++}; ++ + static int __init pxa2xx_mfp_init(void) + { + int i; +diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c +index d16ab7451efe..fe7498fbb62b 100644 +--- a/arch/arm/mach-pxa/mfp-pxa3xx.c ++++ b/arch/arm/mach-pxa/mfp-pxa3xx.c +@@ -27,13 +27,13 @@ + * a pull-down mode if they're an active low chip select, and we're + * just entering standby. + */ +-static int pxa3xx_mfp_suspend(void) ++static int pxa3xx_mfp_suspend(void *data) + { + mfp_config_lpm(); + return 0; + } + +-static void pxa3xx_mfp_resume(void) ++static void pxa3xx_mfp_resume(void *data) + { + mfp_config_run(); + +@@ -49,7 +49,11 @@ static void pxa3xx_mfp_resume(void) + #define pxa3xx_mfp_resume NULL + #endif + +-struct syscore_ops pxa3xx_mfp_syscore_ops = { ++static const struct syscore_ops pxa3xx_mfp_syscore_ops = { + .suspend = pxa3xx_mfp_suspend, + .resume = pxa3xx_mfp_resume, + }; ++ ++struct syscore pxa3xx_mfp_syscore = { ++ .ops = &pxa3xx_mfp_syscore_ops, ++}; +diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c +index 03e34841fc00..70509a599814 100644 +--- a/arch/arm/mach-pxa/pxa25x.c ++++ b/arch/arm/mach-pxa/pxa25x.c +@@ -235,8 +235,8 @@ static int __init pxa25x_init(void) + + pxa25x_init_pm(); + +- register_syscore_ops(&pxa_irq_syscore_ops); +- register_syscore_ops(&pxa2xx_mfp_syscore_ops); ++ register_syscore(&pxa_irq_syscore); ++ register_syscore(&pxa2xx_mfp_syscore); + + if (!of_have_populated_dt()) { + software_node_register(&pxa2xx_gpiochip_node); +diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c +index f8382477d629..ff6361979038 100644 +--- a/arch/arm/mach-pxa/pxa27x.c ++++ b/arch/arm/mach-pxa/pxa27x.c +@@ -337,8 +337,8 @@ static int __init pxa27x_init(void) + + pxa27x_init_pm(); + +- register_syscore_ops(&pxa_irq_syscore_ops); +- register_syscore_ops(&pxa2xx_mfp_syscore_ops); ++ register_syscore(&pxa_irq_syscore); ++ register_syscore(&pxa2xx_mfp_syscore); + + if (!of_have_populated_dt()) { + software_node_register(&pxa2xx_gpiochip_node); +diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c +index 1d1e5713464d..06c578ea658e 100644 +--- a/arch/arm/mach-pxa/pxa3xx.c ++++ b/arch/arm/mach-pxa/pxa3xx.c +@@ -424,8 +424,8 @@ static int __init pxa3xx_init(void) + if (cpu_is_pxa320()) + enable_irq_wake(IRQ_WAKEUP1); + +- register_syscore_ops(&pxa_irq_syscore_ops); +- register_syscore_ops(&pxa3xx_mfp_syscore_ops); ++ register_syscore(&pxa_irq_syscore); ++ register_syscore(&pxa3xx_mfp_syscore); + } + + return ret; +diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c +index 2d2a321d82f8..fb93a8f28356 100644 +--- a/arch/arm/mach-pxa/smemc.c ++++ b/arch/arm/mach-pxa/smemc.c +@@ -18,7 +18,7 @@ static unsigned long msc[2]; + static unsigned long sxcnfg, memclkcfg; + static unsigned long csadrcfg[4]; + +-static int pxa3xx_smemc_suspend(void) ++static int pxa3xx_smemc_suspend(void *data) + { + msc[0] = __raw_readl(MSC0); + msc[1] = __raw_readl(MSC1); +@@ -32,7 +32,7 @@ static int pxa3xx_smemc_suspend(void) + return 0; + } + +-static void pxa3xx_smemc_resume(void) ++static void pxa3xx_smemc_resume(void *data) + { + __raw_writel(msc[0], MSC0); + __raw_writel(msc[1], MSC1); +@@ -46,11 +46,15 @@ static void pxa3xx_smemc_resume(void) + __raw_writel(0x2, CSMSADRCFG); + } + +-static struct syscore_ops smemc_syscore_ops = { ++static const struct syscore_ops smemc_syscore_ops = { + .suspend = pxa3xx_smemc_suspend, + .resume = pxa3xx_smemc_resume, + }; + ++static struct syscore smemc_syscore = { ++ .ops = &smemc_syscore_ops, ++}; ++ + static int __init smemc_init(void) + { + if (cpu_is_pxa3xx()) { +@@ -64,7 +68,7 @@ static int __init smemc_init(void) + */ + __raw_writel(0x2, CSMSADRCFG); + +- register_syscore_ops(&smemc_syscore_ops); ++ register_syscore(&smemc_syscore); + } + + return 0; +diff --git a/arch/arm/mach-s3c/irq-pm-s3c64xx.c b/arch/arm/mach-s3c/irq-pm-s3c64xx.c +index 4a1e935bada1..ab726c595001 100644 +--- a/arch/arm/mach-s3c/irq-pm-s3c64xx.c ++++ b/arch/arm/mach-s3c/irq-pm-s3c64xx.c +@@ -58,7 +58,7 @@ static struct irq_grp_save { + + static u32 irq_uart_mask[SERIAL_SAMSUNG_UARTS]; + +-static int s3c64xx_irq_pm_suspend(void) ++static int s3c64xx_irq_pm_suspend(void *data) + { + struct irq_grp_save *grp = eint_grp_save; + int i; +@@ -79,7 +79,7 @@ static int s3c64xx_irq_pm_suspend(void) + return 0; + } + +-static void s3c64xx_irq_pm_resume(void) ++static void s3c64xx_irq_pm_resume(void *data) + { + struct irq_grp_save *grp = eint_grp_save; + int i; +@@ -100,18 +100,22 @@ static void s3c64xx_irq_pm_resume(void) + S3C_PMDBG("%s: IRQ configuration restored\n", __func__); + } + +-static struct syscore_ops s3c64xx_irq_syscore_ops = { ++static const struct syscore_ops s3c64xx_irq_syscore_ops = { + .suspend = s3c64xx_irq_pm_suspend, + .resume = s3c64xx_irq_pm_resume, + }; + ++static struct syscore s3c64xx_irq_syscore = { ++ .ops = &s3c64xx_irq_syscore_ops, ++}; ++ + static __init int s3c64xx_syscore_init(void) + { + /* Appropriate drivers (pinctrl, uart) handle this when using DT. */ + if (of_have_populated_dt() || !soc_is_s3c64xx()) + return 0; + +- register_syscore_ops(&s3c64xx_irq_syscore_ops); ++ register_syscore(&s3c64xx_irq_syscore); + + return 0; + } +diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c +index 6fa70f787df4..fa270750364c 100644 +--- a/arch/arm/mach-s5pv210/pm.c ++++ b/arch/arm/mach-s5pv210/pm.c +@@ -195,20 +195,24 @@ static const struct platform_suspend_ops s5pv210_suspend_ops = { + /* + * Syscore operations used to delay restore of certain registers. + */ +-static void s5pv210_pm_resume(void) ++static void s5pv210_pm_resume(void *data) + { + s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); + } + +-static struct syscore_ops s5pv210_pm_syscore_ops = { ++static const struct syscore_ops s5pv210_pm_syscore_ops = { + .resume = s5pv210_pm_resume, + }; + ++static struct syscore s5pv210_pm_syscore = { ++ .ops = &s5pv210_pm_syscore_ops, ++}; ++ + /* + * Initialization entry point. + */ + void __init s5pv210_pm_init(void) + { +- register_syscore_ops(&s5pv210_pm_syscore_ops); ++ register_syscore(&s5pv210_pm_syscore); + suspend_set_ops(&s5pv210_suspend_ops); + } +diff --git a/arch/arm/mach-versatile/integrator_ap.c b/arch/arm/mach-versatile/integrator_ap.c +index 4bd6712e9f52..ee90d6619d0d 100644 +--- a/arch/arm/mach-versatile/integrator_ap.c ++++ b/arch/arm/mach-versatile/integrator_ap.c +@@ -63,13 +63,13 @@ static void __init ap_map_io(void) + #ifdef CONFIG_PM + static unsigned long ic_irq_enable; + +-static int irq_suspend(void) ++static int irq_suspend(void *data) + { + ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); + return 0; + } + +-static void irq_resume(void) ++static void irq_resume(void *data) + { + /* disable all irq sources */ + cm_clear_irqs(); +@@ -83,14 +83,18 @@ static void irq_resume(void) + #define irq_resume NULL + #endif + +-static struct syscore_ops irq_syscore_ops = { ++static const struct syscore_ops irq_syscore_ops = { + .suspend = irq_suspend, + .resume = irq_resume, + }; + ++static struct syscore irq_syscore = { ++ .ops = &irq_syscore_ops, ++}; ++ + static int __init irq_syscore_init(void) + { +- register_syscore_ops(&irq_syscore_ops); ++ register_syscore(&irq_syscore); + + return 0; + } +diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c +index 6f63b90f9e1a..e7807356dfab 100644 +--- a/arch/arm/mm/cache-b15-rac.c ++++ b/arch/arm/mm/cache-b15-rac.c +@@ -256,7 +256,7 @@ static int b15_rac_dead_cpu(unsigned int cpu) + return 0; + } + +-static int b15_rac_suspend(void) ++static int b15_rac_suspend(void *data) + { + /* Suspend the read-ahead cache oeprations, forcing our cache + * implementation to fallback to the regular ARMv7 calls. +@@ -271,7 +271,7 @@ static int b15_rac_suspend(void) + return 0; + } + +-static void b15_rac_resume(void) ++static void b15_rac_resume(void *data) + { + /* Coming out of a S3 suspend/resume cycle, the read-ahead cache + * register RAC_CONFIG0_REG will be restored to its default value, make +@@ -282,11 +282,15 @@ static void b15_rac_resume(void) + clear_bit(RAC_SUSPENDED, &b15_rac_flags); + } + +-static struct syscore_ops b15_rac_syscore_ops = { ++static const struct syscore_ops b15_rac_syscore_ops = { + .suspend = b15_rac_suspend, + .resume = b15_rac_resume, + }; + ++static struct syscore b15_rac_syscore = { ++ .ops = &b15_rac_syscore_ops, ++}; ++ + static int __init b15_rac_init(void) + { + struct device_node *dn, *cpu_dn; +@@ -347,7 +351,7 @@ static int __init b15_rac_init(void) + } + + if (IS_ENABLED(CONFIG_PM_SLEEP)) +- register_syscore_ops(&b15_rac_syscore_ops); ++ register_syscore(&b15_rac_syscore); + + spin_lock(&rac_lock); + reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); +diff --git a/arch/loongarch/kernel/smp.c b/arch/loongarch/kernel/smp.c +index 46036d98da75..8b2fcb3fb874 100644 +--- a/arch/loongarch/kernel/smp.c ++++ b/arch/loongarch/kernel/smp.c +@@ -535,28 +535,32 @@ int hibernate_resume_nonboot_cpu_disable(void) + */ + #ifdef CONFIG_PM + +-static int loongson_ipi_suspend(void) ++static int loongson_ipi_suspend(void *data) + { + return 0; + } + +-static void loongson_ipi_resume(void) ++static void loongson_ipi_resume(void *data) + { + iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN); + } + +-static struct syscore_ops loongson_ipi_syscore_ops = { ++static const struct syscore_ops loongson_ipi_syscore_ops = { + .resume = loongson_ipi_resume, + .suspend = loongson_ipi_suspend, + }; + ++static struct syscore loongson_ipi_syscore = { ++ .ops = &loongson_ipi_syscore_ops, ++}; ++ + /* + * Enable boot cpu ipi before enabling nonboot cpus + * during syscore_resume. + */ + static int __init ipi_pm_init(void) + { +- register_syscore_ops(&loongson_ipi_syscore_ops); ++ register_syscore(&loongson_ipi_syscore); + return 0; + } + +diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c +index 6a3c890f7bbf..6c2c2010bbae 100644 +--- a/arch/mips/alchemy/common/dbdma.c ++++ b/arch/mips/alchemy/common/dbdma.c +@@ -982,7 +982,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) + + static unsigned long alchemy_dbdma_pm_data[NUM_DBDMA_CHANS + 1][6]; + +-static int alchemy_dbdma_suspend(void) ++static int alchemy_dbdma_suspend(void *data) + { + int i; + void __iomem *addr; +@@ -1019,7 +1019,7 @@ static int alchemy_dbdma_suspend(void) + return 0; + } + +-static void alchemy_dbdma_resume(void) ++static void alchemy_dbdma_resume(void *data) + { + int i; + void __iomem *addr; +@@ -1044,11 +1044,15 @@ static void alchemy_dbdma_resume(void) + } + } + +-static struct syscore_ops alchemy_dbdma_syscore_ops = { ++static const struct syscore_ops alchemy_dbdma_syscore_ops = { + .suspend = alchemy_dbdma_suspend, + .resume = alchemy_dbdma_resume, + }; + ++static struct syscore alchemy_dbdma_syscore = { ++ .ops = &alchemy_dbdma_syscore_ops, ++}; ++ + static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable) + { + int ret; +@@ -1071,7 +1075,7 @@ static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable) + printk(KERN_ERR "Cannot grab DBDMA interrupt!\n"); + else { + dbdma_initialized = 1; +- register_syscore_ops(&alchemy_dbdma_syscore_ops); ++ register_syscore(&alchemy_dbdma_syscore); + } + + return ret; +diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c +index da9f9220048f..2403afcd2fb9 100644 +--- a/arch/mips/alchemy/common/irq.c ++++ b/arch/mips/alchemy/common/irq.c +@@ -758,7 +758,7 @@ static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d) + wmb(); + } + +-static int alchemy_ic_suspend(void) ++static int alchemy_ic_suspend(void *data) + { + alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), + alchemy_gpic_pmdata); +@@ -767,7 +767,7 @@ static int alchemy_ic_suspend(void) + return 0; + } + +-static void alchemy_ic_resume(void) ++static void alchemy_ic_resume(void *data) + { + alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), + &alchemy_gpic_pmdata[7]); +@@ -775,7 +775,7 @@ static void alchemy_ic_resume(void) + alchemy_gpic_pmdata); + } + +-static int alchemy_gpic_suspend(void) ++static int alchemy_gpic_suspend(void *data) + { + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + int i; +@@ -806,7 +806,7 @@ static int alchemy_gpic_suspend(void) + return 0; + } + +-static void alchemy_gpic_resume(void) ++static void alchemy_gpic_resume(void *data) + { + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + int i; +@@ -837,16 +837,24 @@ static void alchemy_gpic_resume(void) + wmb(); + } + +-static struct syscore_ops alchemy_ic_pmops = { ++static const struct syscore_ops alchemy_ic_pmops = { + .suspend = alchemy_ic_suspend, + .resume = alchemy_ic_resume, + }; + +-static struct syscore_ops alchemy_gpic_pmops = { ++static struct syscore alchemy_ic_pm = { ++ .ops = &alchemy_ic_pmops, ++}; ++ ++static const struct syscore_ops alchemy_gpic_pmops = { + .suspend = alchemy_gpic_suspend, + .resume = alchemy_gpic_resume, + }; + ++static struct syscore alchemy_gpic_pm = { ++ .ops = &alchemy_gpic_pmops, ++}; ++ + /******************************************************************************/ + + /* create chained handlers for the 4 IC requests to the MIPS IRQ ctrl */ +@@ -880,7 +888,7 @@ static void __init au1000_init_irq(struct alchemy_irqmap *map) + + ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR)); + ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR)); +- register_syscore_ops(&alchemy_ic_pmops); ++ register_syscore(&alchemy_ic_pm); + mips_cpu_irq_init(); + + /* register all 64 possible IC0+IC1 irq sources as type "none". +@@ -925,7 +933,7 @@ static void __init alchemy_gpic_init_irq(const struct alchemy_irqmap *dints) + int i; + void __iomem *bank_base; + +- register_syscore_ops(&alchemy_gpic_pmops); ++ register_syscore(&alchemy_gpic_pm); + mips_cpu_irq_init(); + + /* disable & ack all possible interrupt sources */ +diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c +index 5d618547ebf0..a55f32bf517c 100644 +--- a/arch/mips/alchemy/common/usb.c ++++ b/arch/mips/alchemy/common/usb.c +@@ -580,22 +580,26 @@ static void alchemy_usb_pm(int susp) + } + } + +-static int alchemy_usb_suspend(void) ++static int alchemy_usb_suspend(void *data) + { + alchemy_usb_pm(1); + return 0; + } + +-static void alchemy_usb_resume(void) ++static void alchemy_usb_resume(void *data) + { + alchemy_usb_pm(0); + } + +-static struct syscore_ops alchemy_usb_pm_ops = { ++static const struct syscore_ops alchemy_usb_pm_syscore_ops = { + .suspend = alchemy_usb_suspend, + .resume = alchemy_usb_resume, + }; + ++static struct syscore alchemy_usb_pm_syscore = { ++ .ops = &alchemy_usb_pm_syscore_ops, ++}; ++ + static int __init alchemy_usb_init(void) + { + int ret = 0; +@@ -620,7 +624,7 @@ static int __init alchemy_usb_init(void) + } + + if (!ret) +- register_syscore_ops(&alchemy_usb_pm_ops); ++ register_syscore(&alchemy_usb_pm_syscore); + + return ret; + } +diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c +index 58625d1b6465..6bfee0f71803 100644 +--- a/arch/mips/pci/pci-alchemy.c ++++ b/arch/mips/pci/pci-alchemy.c +@@ -304,7 +304,7 @@ static int alchemy_pci_def_idsel(unsigned int devsel, int assert) + } + + /* save PCI controller register contents. */ +-static int alchemy_pci_suspend(void) ++static int alchemy_pci_suspend(void *data) + { + struct alchemy_pci_context *ctx = __alchemy_pci_ctx; + if (!ctx) +@@ -326,7 +326,7 @@ static int alchemy_pci_suspend(void) + return 0; + } + +-static void alchemy_pci_resume(void) ++static void alchemy_pci_resume(void *data) + { + struct alchemy_pci_context *ctx = __alchemy_pci_ctx; + if (!ctx) +@@ -354,9 +354,13 @@ static void alchemy_pci_resume(void) + alchemy_pci_wired_entry(ctx); /* install it */ + } + +-static struct syscore_ops alchemy_pci_pmops = { +- .suspend = alchemy_pci_suspend, +- .resume = alchemy_pci_resume, ++static const struct syscore_ops alchemy_pci_syscore_ops = { ++ .suspend = alchemy_pci_suspend, ++ .resume = alchemy_pci_resume, ++}; ++ ++static struct syscore alchemy_pci_syscore = { ++ .ops = &alchemy_pci_syscore_ops, + }; + + static int alchemy_pci_probe(struct platform_device *pdev) +@@ -478,7 +482,7 @@ static int alchemy_pci_probe(struct platform_device *pdev) + + __alchemy_pci_ctx = ctx; + platform_set_drvdata(pdev, ctx); +- register_syscore_ops(&alchemy_pci_pmops); ++ register_syscore(&alchemy_pci_syscore); + register_pci_controller(&ctx->alchemy_pci_ctrl); + + dev_info(&pdev->dev, "PCI controller at %ld MHz\n", +diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c +index 2c07387201d0..2ddb93df4817 100644 +--- a/arch/powerpc/platforms/cell/spu_base.c ++++ b/arch/powerpc/platforms/cell/spu_base.c +@@ -726,7 +726,7 @@ static inline void crash_register_spus(struct list_head *list) + } + #endif + +-static void spu_shutdown(void) ++static void spu_shutdown(void *data) + { + struct spu *spu; + +@@ -738,10 +738,14 @@ static void spu_shutdown(void) + mutex_unlock(&spu_full_list_mutex); + } + +-static struct syscore_ops spu_syscore_ops = { ++static const struct syscore_ops spu_syscore_ops = { + .shutdown = spu_shutdown, + }; + ++static struct syscore spu_syscore = { ++ .ops = &spu_syscore_ops, ++}; ++ + static int __init init_spu_base(void) + { + int i, ret = 0; +@@ -774,7 +778,7 @@ static int __init init_spu_base(void) + crash_register_spus(&spu_full_list); + mutex_unlock(&spu_full_list_mutex); + spu_add_dev_attr(&dev_attr_stat); +- register_syscore_ops(&spu_syscore_ops); ++ register_syscore(&spu_syscore); + + spu_init_affinity(); + +diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c +index c37783a03d25..1959cc13438f 100644 +--- a/arch/powerpc/platforms/powermac/pic.c ++++ b/arch/powerpc/platforms/powermac/pic.c +@@ -600,7 +600,7 @@ static int pmacpic_find_viaint(void) + return viaint; + } + +-static int pmacpic_suspend(void) ++static int pmacpic_suspend(void *data) + { + int viaint = pmacpic_find_viaint(); + +@@ -621,7 +621,7 @@ static int pmacpic_suspend(void) + return 0; + } + +-static void pmacpic_resume(void) ++static void pmacpic_resume(void *data) + { + int i; + +@@ -634,15 +634,19 @@ static void pmacpic_resume(void) + pmac_unmask_irq(irq_get_irq_data(i)); + } + +-static struct syscore_ops pmacpic_syscore_ops = { ++static const struct syscore_ops pmacpic_syscore_ops = { + .suspend = pmacpic_suspend, + .resume = pmacpic_resume, + }; + ++static struct syscore pmacpic_syscore = { ++ .ops = &pmacpic_syscore_ops, ++}; ++ + static int __init init_pmacpic_syscore(void) + { + if (pmac_irq_hw[0]) +- register_syscore_ops(&pmacpic_syscore_ops); ++ register_syscore(&pmacpic_syscore); + return 0; + } + +diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c +index 217cea150987..7ed07232a69a 100644 +--- a/arch/powerpc/sysdev/fsl_lbc.c ++++ b/arch/powerpc/sysdev/fsl_lbc.c +@@ -350,7 +350,7 @@ static int fsl_lbc_ctrl_probe(struct platform_device *dev) + #ifdef CONFIG_SUSPEND + + /* save lbc registers */ +-static int fsl_lbc_syscore_suspend(void) ++static int fsl_lbc_syscore_suspend(void *data) + { + struct fsl_lbc_ctrl *ctrl; + struct fsl_lbc_regs __iomem *lbc; +@@ -374,7 +374,7 @@ static int fsl_lbc_syscore_suspend(void) + } + + /* restore lbc registers */ +-static void fsl_lbc_syscore_resume(void) ++static void fsl_lbc_syscore_resume(void *data) + { + struct fsl_lbc_ctrl *ctrl; + struct fsl_lbc_regs __iomem *lbc; +@@ -408,10 +408,14 @@ static const struct of_device_id fsl_lbc_match[] = { + }; + + #ifdef CONFIG_SUSPEND +-static struct syscore_ops lbc_syscore_pm_ops = { ++static const struct syscore_ops lbc_syscore_pm_ops = { + .suspend = fsl_lbc_syscore_suspend, + .resume = fsl_lbc_syscore_resume, + }; ++ ++static struct syscore lbc_syscore_pm = { ++ .ops = &lbc_syscore_pm_ops, ++}; + #endif + + static struct platform_driver fsl_lbc_ctrl_driver = { +@@ -425,7 +429,7 @@ static struct platform_driver fsl_lbc_ctrl_driver = { + static int __init fsl_lbc_init(void) + { + #ifdef CONFIG_SUSPEND +- register_syscore_ops(&lbc_syscore_pm_ops); ++ register_syscore(&lbc_syscore_pm); + #endif + return platform_driver_register(&fsl_lbc_ctrl_driver); + } +diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c +index ef7707ea0db7..4e501654cb41 100644 +--- a/arch/powerpc/sysdev/fsl_pci.c ++++ b/arch/powerpc/sysdev/fsl_pci.c +@@ -1258,7 +1258,7 @@ static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) + send_pme_turnoff_message(hose); + } + +-static int fsl_pci_syscore_suspend(void) ++static int fsl_pci_syscore_suspend(void *data) + { + struct pci_controller *hose, *tmp; + +@@ -1291,7 +1291,7 @@ static void fsl_pci_syscore_do_resume(struct pci_controller *hose) + setup_pci_atmu(hose); + } + +-static void fsl_pci_syscore_resume(void) ++static void fsl_pci_syscore_resume(void *data) + { + struct pci_controller *hose, *tmp; + +@@ -1299,10 +1299,14 @@ static void fsl_pci_syscore_resume(void) + fsl_pci_syscore_do_resume(hose); + } + +-static struct syscore_ops pci_syscore_pm_ops = { ++static const struct syscore_ops pci_syscore_pm_ops = { + .suspend = fsl_pci_syscore_suspend, + .resume = fsl_pci_syscore_resume, + }; ++ ++static struct syscore pci_syscore_pm = { ++ .ops = &pci_syscore_pm_ops, ++}; + #endif + + void fsl_pcibios_fixup_phb(struct pci_controller *phb) +@@ -1359,7 +1363,7 @@ static struct platform_driver fsl_pci_driver = { + static int __init fsl_pci_init(void) + { + #ifdef CONFIG_PM_SLEEP +- register_syscore_ops(&pci_syscore_pm_ops); ++ register_syscore(&pci_syscore_pm); + #endif + return platform_driver_register(&fsl_pci_driver); + } +diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c +index 70be2105865d..290ba8427239 100644 +--- a/arch/powerpc/sysdev/ipic.c ++++ b/arch/powerpc/sysdev/ipic.c +@@ -817,7 +817,7 @@ static struct { + u32 sercr; + } ipic_saved_state; + +-static int ipic_suspend(void) ++static int ipic_suspend(void *data) + { + struct ipic *ipic = primary_ipic; + +@@ -848,7 +848,7 @@ static int ipic_suspend(void) + return 0; + } + +-static void ipic_resume(void) ++static void ipic_resume(void *data) + { + struct ipic *ipic = primary_ipic; + +@@ -870,18 +870,22 @@ static void ipic_resume(void) + #define ipic_resume NULL + #endif + +-static struct syscore_ops ipic_syscore_ops = { ++static const struct syscore_ops ipic_syscore_ops = { + .suspend = ipic_suspend, + .resume = ipic_resume, + }; + ++static struct syscore ipic_syscore = { ++ .ops = &ipic_syscore_ops, ++}; ++ + static int __init init_ipic_syscore(void) + { + if (!primary_ipic || !primary_ipic->regs) + return -ENODEV; + + printk(KERN_DEBUG "Registering ipic system core operations\n"); +- register_syscore_ops(&ipic_syscore_ops); ++ register_syscore(&ipic_syscore); + + return 0; + } +diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c +index ad7310bba00b..67e51998d1ae 100644 +--- a/arch/powerpc/sysdev/mpic.c ++++ b/arch/powerpc/sysdev/mpic.c +@@ -1944,7 +1944,7 @@ static void mpic_suspend_one(struct mpic *mpic) + } + } + +-static int mpic_suspend(void) ++static int mpic_suspend(void *data) + { + struct mpic *mpic = mpics; + +@@ -1986,7 +1986,7 @@ static void mpic_resume_one(struct mpic *mpic) + } /* end for loop */ + } + +-static void mpic_resume(void) ++static void mpic_resume(void *data) + { + struct mpic *mpic = mpics; + +@@ -1996,19 +1996,23 @@ static void mpic_resume(void) + } + } + +-static struct syscore_ops mpic_syscore_ops = { ++static const struct syscore_ops mpic_syscore_ops = { + .resume = mpic_resume, + .suspend = mpic_suspend, + }; + ++static struct syscore mpic_syscore = { ++ .ops = &mpic_syscore_ops, ++}; ++ + static int mpic_init_sys(void) + { + int rc; + +- register_syscore_ops(&mpic_syscore_ops); ++ register_syscore(&mpic_syscore); + rc = subsys_system_register(&mpic_subsys, NULL); + if (rc) { +- unregister_syscore_ops(&mpic_syscore_ops); ++ unregister_syscore(&mpic_syscore); + pr_err("mpic: Failed to register subsystem!\n"); + return rc; + } +diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c +index 7166e2e0baaf..60f5b3934b51 100644 +--- a/arch/powerpc/sysdev/mpic_timer.c ++++ b/arch/powerpc/sysdev/mpic_timer.c +@@ -519,7 +519,7 @@ static void __init timer_group_init(struct device_node *np) + kfree(priv); + } + +-static void mpic_timer_resume(void) ++static void mpic_timer_resume(void *data) + { + struct timer_group_priv *priv; + +@@ -535,10 +535,14 @@ static const struct of_device_id mpic_timer_ids[] = { + {}, + }; + +-static struct syscore_ops mpic_timer_syscore_ops = { ++static const struct syscore_ops mpic_timer_syscore_ops = { + .resume = mpic_timer_resume, + }; + ++static struct syscore mpic_timer_syscore = { ++ .ops = &mpic_timer_syscore_ops, ++}; ++ + static int __init mpic_timer_init(void) + { + struct device_node *np = NULL; +@@ -546,7 +550,7 @@ static int __init mpic_timer_init(void) + for_each_matching_node(np, mpic_timer_ids) + timer_group_init(np); + +- register_syscore_ops(&mpic_timer_syscore_ops); ++ register_syscore(&mpic_timer_syscore); + + if (list_empty(&timer_group_list)) + return -ENODEV; +diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c +index 68eb7cc6e564..482eec50f404 100644 +--- a/arch/sh/mm/pmb.c ++++ b/arch/sh/mm/pmb.c +@@ -857,7 +857,7 @@ static int __init pmb_debugfs_init(void) + subsys_initcall(pmb_debugfs_init); + + #ifdef CONFIG_PM +-static void pmb_syscore_resume(void) ++static void pmb_syscore_resume(void *data) + { + struct pmb_entry *pmbe; + int i; +@@ -874,13 +874,17 @@ static void pmb_syscore_resume(void) + read_unlock(&pmb_rwlock); + } + +-static struct syscore_ops pmb_syscore_ops = { ++static const struct syscore_ops pmb_syscore_ops = { + .resume = pmb_syscore_resume, + }; + ++static struct syscore pmb_syscore = { ++ .ops = &pmb_syscore_ops, ++}; ++ + static int __init pmb_sysdev_init(void) + { +- register_syscore_ops(&pmb_syscore_ops); ++ register_syscore(&pmb_syscore); + return 0; + } + subsys_initcall(pmb_sysdev_init); +diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c +index 56918cd91115..23d834e7b565 100644 +--- a/arch/x86/events/amd/ibs.c ++++ b/arch/x86/events/amd/ibs.c +@@ -1719,26 +1719,30 @@ static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu) + + #ifdef CONFIG_PM + +-static int perf_ibs_suspend(void) ++static int perf_ibs_suspend(void *data) + { + clear_APIC_ibs(); + return 0; + } + +-static void perf_ibs_resume(void) ++static void perf_ibs_resume(void *data) + { + ibs_eilvt_setup(); + setup_APIC_ibs(); + } + +-static struct syscore_ops perf_ibs_syscore_ops = { ++static const struct syscore_ops perf_ibs_syscore_ops = { + .resume = perf_ibs_resume, + .suspend = perf_ibs_suspend, + }; + ++static struct syscore perf_ibs_syscore = { ++ .ops = &perf_ibs_syscore_ops, ++}; ++ + static void perf_ibs_pm_init(void) + { +- register_syscore_ops(&perf_ibs_syscore_ops); ++ register_syscore(&perf_ibs_syscore); + } + + #else +diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c +index e890fd37e9c2..085ef4f2e73a 100644 +--- a/arch/x86/hyperv/hv_init.c ++++ b/arch/x86/hyperv/hv_init.c +@@ -351,7 +351,7 @@ static int __init hv_pci_init(void) + return 1; + } + +-static int hv_suspend(void) ++static int hv_suspend(void *data) + { + union hv_x64_msr_hypercall_contents hypercall_msr; + int ret; +@@ -378,7 +378,7 @@ static int hv_suspend(void) + return ret; + } + +-static void hv_resume(void) ++static void hv_resume(void *data) + { + union hv_x64_msr_hypercall_contents hypercall_msr; + int ret; +@@ -405,11 +405,15 @@ static void hv_resume(void) + } + + /* Note: when the ops are called, only CPU0 is online and IRQs are disabled. */ +-static struct syscore_ops hv_syscore_ops = { ++static const struct syscore_ops hv_syscore_ops = { + .suspend = hv_suspend, + .resume = hv_resume, + }; + ++static struct syscore hv_syscore = { ++ .ops = &hv_syscore_ops, ++}; ++ + static void (* __initdata old_setup_percpu_clockev)(void); + + static void __init hv_stimer_setup_percpu_clockev(void) +@@ -569,7 +573,7 @@ void __init hyperv_init(void) + + x86_init.pci.arch_init = hv_pci_init; + +- register_syscore_ops(&hv_syscore_ops); ++ register_syscore(&hv_syscore); + + if (ms_hyperv.priv_high & HV_ACCESS_PARTITION_ID) + hv_get_partition_id(); +diff --git a/arch/x86/kernel/amd_gart_64.c b/arch/x86/kernel/amd_gart_64.c +index 3485d419c2f5..e6e68a31634c 100644 +--- a/arch/x86/kernel/amd_gart_64.c ++++ b/arch/x86/kernel/amd_gart_64.c +@@ -591,7 +591,7 @@ static void gart_fixup_northbridges(void) + } + } + +-static void gart_resume(void) ++static void gart_resume(void *data) + { + pr_info("PCI-DMA: Resuming GART IOMMU\n"); + +@@ -600,11 +600,15 @@ static void gart_resume(void) + enable_gart_translations(); + } + +-static struct syscore_ops gart_syscore_ops = { ++static const struct syscore_ops gart_syscore_ops = { + .resume = gart_resume, + + }; + ++static struct syscore gart_syscore = { ++ .ops = &gart_syscore_ops, ++}; ++ + /* + * Private Northbridge GATT initialization in case we cannot use the + * AGP driver for some reason. +@@ -650,7 +654,7 @@ static __init int init_amd_gatt(struct agp_kern_info *info) + + agp_gatt_table = gatt; + +- register_syscore_ops(&gart_syscore_ops); ++ register_syscore(&gart_syscore); + + flush_gart(); + +diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c +index aa1b0ef5e931..a4431f0d2580 100644 +--- a/arch/x86/kernel/apic/apic.c ++++ b/arch/x86/kernel/apic/apic.c +@@ -2382,7 +2382,7 @@ static struct { + unsigned int apic_cmci; + } apic_pm_state; + +-static int lapic_suspend(void) ++static int lapic_suspend(void *data) + { + unsigned long flags; + int maxlvt; +@@ -2430,7 +2430,7 @@ static int lapic_suspend(void) + return 0; + } + +-static void lapic_resume(void) ++static void lapic_resume(void *data) + { + unsigned int l, h; + unsigned long flags; +@@ -2510,11 +2510,15 @@ static void lapic_resume(void) + * are needed on every CPU up until machine_halt/restart/poweroff. + */ + +-static struct syscore_ops lapic_syscore_ops = { ++static const struct syscore_ops lapic_syscore_ops = { + .resume = lapic_resume, + .suspend = lapic_suspend, + }; + ++static struct syscore lapic_syscore = { ++ .ops = &lapic_syscore_ops, ++}; ++ + static void apic_pm_activate(void) + { + apic_pm_state.active = 1; +@@ -2524,7 +2528,7 @@ static int __init init_lapic_sysfs(void) + { + /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ + if (boot_cpu_has(X86_FEATURE_APIC)) +- register_syscore_ops(&lapic_syscore_ops); ++ register_syscore(&lapic_syscore); + + return 0; + } +diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c +index 5ba2feb2c04c..84e200662ce6 100644 +--- a/arch/x86/kernel/apic/io_apic.c ++++ b/arch/x86/kernel/apic/io_apic.c +@@ -2308,7 +2308,12 @@ static void resume_ioapic_id(int ioapic_idx) + } + } + +-static void ioapic_resume(void) ++static int ioapic_suspend(void *data) ++{ ++ return save_ioapic_entries(); ++} ++ ++static void ioapic_resume(void *data) + { + int ioapic_idx; + +@@ -2318,14 +2323,18 @@ static void ioapic_resume(void) + restore_ioapic_entries(); + } + +-static struct syscore_ops ioapic_syscore_ops = { +- .suspend = save_ioapic_entries, ++static const struct syscore_ops ioapic_syscore_ops = { ++ .suspend = ioapic_suspend, + .resume = ioapic_resume, + }; + ++static struct syscore ioapic_syscore = { ++ .ops = &ioapic_syscore_ops, ++}; ++ + static int __init ioapic_init_ops(void) + { +- register_syscore_ops(&ioapic_syscore_ops); ++ register_syscore(&ioapic_syscore); + + return 0; + } +diff --git a/arch/x86/kernel/cpu/aperfmperf.c b/arch/x86/kernel/cpu/aperfmperf.c +index a315b0627dfb..7ffc78d5ebf2 100644 +--- a/arch/x86/kernel/cpu/aperfmperf.c ++++ b/arch/x86/kernel/cpu/aperfmperf.c +@@ -37,7 +37,7 @@ static DEFINE_PER_CPU_SHARED_ALIGNED(struct aperfmperf, cpu_samples) = { + .seq = SEQCNT_ZERO(cpu_samples.seq) + }; + +-static void init_counter_refs(void) ++static void init_counter_refs(void *data) + { + u64 aperf, mperf; + +@@ -289,16 +289,20 @@ static bool __init intel_set_max_freq_ratio(void) + } + + #ifdef CONFIG_PM_SLEEP +-static struct syscore_ops freq_invariance_syscore_ops = { ++static const struct syscore_ops freq_invariance_syscore_ops = { + .resume = init_counter_refs, + }; + +-static void register_freq_invariance_syscore_ops(void) ++static struct syscore freq_invariance_syscore = { ++ .ops = &freq_invariance_syscore_ops, ++}; ++ ++static void register_freq_invariance_syscore(void) + { +- register_syscore_ops(&freq_invariance_syscore_ops); ++ register_syscore(&freq_invariance_syscore); + } + #else +-static inline void register_freq_invariance_syscore_ops(void) {} ++static inline void register_freq_invariance_syscore(void) {} + #endif + + static void freq_invariance_enable(void) +@@ -308,7 +312,7 @@ static void freq_invariance_enable(void) + return; + } + static_branch_enable_cpuslocked(&arch_scale_freq_key); +- register_freq_invariance_syscore_ops(); ++ register_freq_invariance_syscore(); + pr_info("Estimated ratio of average max frequency by base frequency (times 1024): %llu\n", arch_max_freq_ratio); + } + +@@ -535,7 +539,7 @@ static int __init bp_init_aperfmperf(void) + if (!cpu_feature_enabled(X86_FEATURE_APERFMPERF)) + return 0; + +- init_counter_refs(); ++ init_counter_refs(NULL); + bp_init_freq_invariance(); + return 0; + } +@@ -544,5 +548,5 @@ early_initcall(bp_init_aperfmperf); + void ap_init_aperfmperf(void) + { + if (cpu_feature_enabled(X86_FEATURE_APERFMPERF)) +- init_counter_refs(); ++ init_counter_refs(NULL); + } +diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c +index bc7671f920a7..2c56f8730f59 100644 +--- a/arch/x86/kernel/cpu/intel_epb.c ++++ b/arch/x86/kernel/cpu/intel_epb.c +@@ -75,7 +75,7 @@ static u8 energ_perf_values[] = { + [EPB_INDEX_POWERSAVE] = ENERGY_PERF_BIAS_POWERSAVE, + }; + +-static int intel_epb_save(void) ++static int intel_epb_save(void *data) + { + u64 epb; + +@@ -89,7 +89,7 @@ static int intel_epb_save(void) + return 0; + } + +-static void intel_epb_restore(void) ++static void intel_epb_restore(void *data) + { + u64 val = this_cpu_read(saved_epb); + u64 epb; +@@ -114,11 +114,15 @@ static void intel_epb_restore(void) + wrmsrq(MSR_IA32_ENERGY_PERF_BIAS, (epb & ~EPB_MASK) | val); + } + +-static struct syscore_ops intel_epb_syscore_ops = { ++static const struct syscore_ops intel_epb_syscore_ops = { + .suspend = intel_epb_save, + .resume = intel_epb_restore, + }; + ++static struct syscore intel_epb_syscore = { ++ .ops = &intel_epb_syscore_ops, ++}; ++ + static const char * const energy_perf_strings[] = { + [EPB_INDEX_PERFORMANCE] = "performance", + [EPB_INDEX_BALANCE_PERFORMANCE] = "balance-performance", +@@ -185,7 +189,7 @@ static int intel_epb_online(unsigned int cpu) + { + struct device *cpu_dev = get_cpu_device(cpu); + +- intel_epb_restore(); ++ intel_epb_restore(NULL); + if (!cpuhp_tasks_frozen) + sysfs_merge_group(&cpu_dev->kobj, &intel_epb_attr_group); + +@@ -199,7 +203,7 @@ static int intel_epb_offline(unsigned int cpu) + if (!cpuhp_tasks_frozen) + sysfs_unmerge_group(&cpu_dev->kobj, &intel_epb_attr_group); + +- intel_epb_save(); ++ intel_epb_save(NULL); + return 0; + } + +@@ -230,7 +234,7 @@ static __init int intel_epb_init(void) + if (ret < 0) + goto err_out_online; + +- register_syscore_ops(&intel_epb_syscore_ops); ++ register_syscore(&intel_epb_syscore); + return 0; + + err_out_online: +diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c +index c8b112c6c549..26c98d9002bc 100644 +--- a/arch/x86/kernel/cpu/mce/core.c ++++ b/arch/x86/kernel/cpu/mce/core.c +@@ -2387,13 +2387,13 @@ static void vendor_disable_error_reporting(void) + mce_disable_error_reporting(); + } + +-static int mce_syscore_suspend(void) ++static int mce_syscore_suspend(void *data) + { + vendor_disable_error_reporting(); + return 0; + } + +-static void mce_syscore_shutdown(void) ++static void mce_syscore_shutdown(void *data) + { + vendor_disable_error_reporting(); + } +@@ -2403,7 +2403,7 @@ static void mce_syscore_shutdown(void) + * Only one CPU is active at this time, the others get re-added later using + * CPU hotplug: + */ +-static void mce_syscore_resume(void) ++static void mce_syscore_resume(void *data) + { + __mcheck_cpu_init_generic(); + __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); +@@ -2411,12 +2411,16 @@ static void mce_syscore_resume(void) + cr4_set_bits(X86_CR4_MCE); + } + +-static struct syscore_ops mce_syscore_ops = { ++static const struct syscore_ops mce_syscore_ops = { + .suspend = mce_syscore_suspend, + .shutdown = mce_syscore_shutdown, + .resume = mce_syscore_resume, + }; + ++static struct syscore mce_syscore = { ++ .ops = &mce_syscore_ops, ++}; ++ + /* + * mce_device: Sysfs support + */ +@@ -2817,7 +2821,7 @@ static __init int mcheck_init_device(void) + if (err < 0) + goto err_out_online; + +- register_syscore_ops(&mce_syscore_ops); ++ register_syscore(&mce_syscore); + + return 0; + +diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c +index 539edd6d6dc8..81aa079fad26 100644 +--- a/arch/x86/kernel/cpu/microcode/core.c ++++ b/arch/x86/kernel/cpu/microcode/core.c +@@ -812,8 +812,17 @@ void microcode_bsp_resume(void) + reload_early_microcode(cpu); + } + +-static struct syscore_ops mc_syscore_ops = { +- .resume = microcode_bsp_resume, ++static void microcode_bsp_syscore_resume(void *data) ++{ ++ microcode_bsp_resume(); ++} ++ ++static const struct syscore_ops mc_syscore_ops = { ++ .resume = microcode_bsp_syscore_resume, ++}; ++ ++static struct syscore mc_syscore = { ++ .ops = &mc_syscore_ops, + }; + + static int mc_cpu_online(unsigned int cpu) +@@ -892,7 +901,7 @@ static int __init microcode_init(void) + } + } + +- register_syscore_ops(&mc_syscore_ops); ++ register_syscore(&mc_syscore); + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", + mc_cpu_online, mc_cpu_down_prep); + +diff --git a/arch/x86/kernel/cpu/mtrr/legacy.c b/arch/x86/kernel/cpu/mtrr/legacy.c +index d25882fcf181..2415ffaaf02c 100644 +--- a/arch/x86/kernel/cpu/mtrr/legacy.c ++++ b/arch/x86/kernel/cpu/mtrr/legacy.c +@@ -41,7 +41,7 @@ struct mtrr_value { + + static struct mtrr_value *mtrr_value; + +-static int mtrr_save(void) ++static int mtrr_save(void *data) + { + int i; + +@@ -56,7 +56,7 @@ static int mtrr_save(void) + return 0; + } + +-static void mtrr_restore(void) ++static void mtrr_restore(void *data) + { + int i; + +@@ -69,11 +69,15 @@ static void mtrr_restore(void) + } + } + +-static struct syscore_ops mtrr_syscore_ops = { ++static const struct syscore_ops mtrr_syscore_ops = { + .suspend = mtrr_save, + .resume = mtrr_restore, + }; + ++static struct syscore mtrr_syscore = { ++ .ops = &mtrr_syscore_ops, ++}; ++ + void mtrr_register_syscore(void) + { + mtrr_value = kcalloc(num_var_ranges, sizeof(*mtrr_value), GFP_KERNEL); +@@ -86,5 +90,5 @@ void mtrr_register_syscore(void) + * TBD: is there any system with such CPU which supports + * suspend/resume? If no, we should remove the code. + */ +- register_syscore_ops(&mtrr_syscore_ops); ++ register_syscore(&mtrr_syscore); + } +diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c +index 933fcd7ff250..e4a31c536642 100644 +--- a/arch/x86/kernel/cpu/umwait.c ++++ b/arch/x86/kernel/cpu/umwait.c +@@ -86,15 +86,19 @@ static int umwait_cpu_offline(unsigned int cpu) + * trust the firmware nor does it matter if the same value is written + * again. + */ +-static void umwait_syscore_resume(void) ++static void umwait_syscore_resume(void *data) + { + umwait_update_control_msr(NULL); + } + +-static struct syscore_ops umwait_syscore_ops = { ++static const struct syscore_ops umwait_syscore_ops = { + .resume = umwait_syscore_resume, + }; + ++static struct syscore umwait_syscore = { ++ .ops = &umwait_syscore_ops, ++}; ++ + /* sysfs interface */ + + /* +@@ -226,7 +230,7 @@ static int __init umwait_init(void) + return ret; + } + +- register_syscore_ops(&umwait_syscore_ops); ++ register_syscore(&umwait_syscore); + + /* + * Add umwait control interface. Ignore failure, so at least the +diff --git a/arch/x86/kernel/i8237.c b/arch/x86/kernel/i8237.c +index 2cd124ad9380..896d46b44284 100644 +--- a/arch/x86/kernel/i8237.c ++++ b/arch/x86/kernel/i8237.c +@@ -19,7 +19,7 @@ + * in asm/dma.h. + */ + +-static void i8237A_resume(void) ++static void i8237A_resume(void *data) + { + unsigned long flags; + int i; +@@ -41,10 +41,14 @@ static void i8237A_resume(void) + release_dma_lock(flags); + } + +-static struct syscore_ops i8237_syscore_ops = { ++static const struct syscore_ops i8237_syscore_ops = { + .resume = i8237A_resume, + }; + ++static struct syscore i8237_syscore = { ++ .ops = &i8237_syscore_ops, ++}; ++ + static int __init i8237A_init_ops(void) + { + /* +@@ -70,7 +74,7 @@ static int __init i8237A_init_ops(void) + if (x86_pnpbios_disabled() && dmi_get_bios_year() >= 2017) + return -ENODEV; + +- register_syscore_ops(&i8237_syscore_ops); ++ register_syscore(&i8237_syscore); + return 0; + } + device_initcall(i8237A_init_ops); +diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c +index 2bade73f49e3..f67063df6723 100644 +--- a/arch/x86/kernel/i8259.c ++++ b/arch/x86/kernel/i8259.c +@@ -247,19 +247,19 @@ static void save_ELCR(char *trigger) + trigger[1] = inb(PIC_ELCR2) & 0xDE; + } + +-static void i8259A_resume(void) ++static void i8259A_resume(void *data) + { + init_8259A(i8259A_auto_eoi); + restore_ELCR(irq_trigger); + } + +-static int i8259A_suspend(void) ++static int i8259A_suspend(void *data) + { + save_ELCR(irq_trigger); + return 0; + } + +-static void i8259A_shutdown(void) ++static void i8259A_shutdown(void *data) + { + /* Put the i8259A into a quiescent state that + * the kernel initialization code can get it +@@ -269,12 +269,16 @@ static void i8259A_shutdown(void) + outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ + } + +-static struct syscore_ops i8259_syscore_ops = { ++static const struct syscore_ops i8259_syscore_ops = { + .suspend = i8259A_suspend, + .resume = i8259A_resume, + .shutdown = i8259A_shutdown, + }; + ++static struct syscore i8259_syscore = { ++ .ops = &i8259_syscore_ops, ++}; ++ + static void mask_8259A(void) + { + unsigned long flags; +@@ -444,7 +448,7 @@ EXPORT_SYMBOL(legacy_pic); + static int __init i8259A_init_ops(void) + { + if (legacy_pic == &default_legacy_pic) +- register_syscore_ops(&i8259_syscore_ops); ++ register_syscore(&i8259_syscore); + + return 0; + } +diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c +index b67d7c59dca0..1500852ba03c 100644 +--- a/arch/x86/kernel/kvm.c ++++ b/arch/x86/kernel/kvm.c +@@ -720,7 +720,7 @@ static int kvm_cpu_down_prepare(unsigned int cpu) + + #endif + +-static int kvm_suspend(void) ++static int kvm_suspend(void *data) + { + u64 val = 0; + +@@ -734,7 +734,7 @@ static int kvm_suspend(void) + return 0; + } + +-static void kvm_resume(void) ++static void kvm_resume(void *data) + { + kvm_cpu_online(raw_smp_processor_id()); + +@@ -744,11 +744,15 @@ static void kvm_resume(void) + #endif + } + +-static struct syscore_ops kvm_syscore_ops = { ++static const struct syscore_ops kvm_syscore_ops = { + .suspend = kvm_suspend, + .resume = kvm_resume, + }; + ++static struct syscore kvm_syscore = { ++ .ops = &kvm_syscore_ops, ++}; ++ + static void kvm_pv_guest_cpu_reboot(void *unused) + { + kvm_guest_cpu_offline(true); +@@ -858,7 +862,7 @@ static void __init kvm_guest_init(void) + machine_ops.crash_shutdown = kvm_crash_shutdown; + #endif + +- register_syscore_ops(&kvm_syscore_ops); ++ register_syscore(&kvm_syscore); + + /* + * Hard lockup detection is enabled by default. Disable it, as guests +diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c +index e4560b33b8ad..bed7dc85612e 100644 +--- a/drivers/acpi/pci_link.c ++++ b/drivers/acpi/pci_link.c +@@ -761,7 +761,7 @@ static int acpi_pci_link_resume(struct acpi_pci_link *link) + return 0; + } + +-static void irqrouter_resume(void) ++static void irqrouter_resume(void *data) + { + struct acpi_pci_link *link; + +@@ -888,10 +888,14 @@ static int __init acpi_irq_balance_set(char *str) + + __setup("acpi_irq_balance", acpi_irq_balance_set); + +-static struct syscore_ops irqrouter_syscore_ops = { ++static const struct syscore_ops irqrouter_syscore_ops = { + .resume = irqrouter_resume, + }; + ++static struct syscore irqrouter_syscore = { ++ .ops = &irqrouter_syscore_ops, ++}; ++ + void __init acpi_pci_link_init(void) + { + if (acpi_noirq) +@@ -904,6 +908,6 @@ void __init acpi_pci_link_init(void) + else + acpi_irq_balance = 0; + } +- register_syscore_ops(&irqrouter_syscore_ops); ++ register_syscore(&irqrouter_syscore); + acpi_scan_add_handler(&pci_link_handler); + } +diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c +index 0b7fa4a8c379..1b9579bb97c2 100644 +--- a/drivers/acpi/sleep.c ++++ b/drivers/acpi/sleep.c +@@ -892,13 +892,13 @@ bool acpi_s2idle_wakeup(void) + #ifdef CONFIG_PM_SLEEP + static u32 saved_bm_rld; + +-static int acpi_save_bm_rld(void) ++static int acpi_save_bm_rld(void *data) + { + acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); + return 0; + } + +-static void acpi_restore_bm_rld(void) ++static void acpi_restore_bm_rld(void *data) + { + u32 resumed_bm_rld = 0; + +@@ -909,14 +909,18 @@ static void acpi_restore_bm_rld(void) + acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); + } + +-static struct syscore_ops acpi_sleep_syscore_ops = { ++static const struct syscore_ops acpi_sleep_syscore_ops = { + .suspend = acpi_save_bm_rld, + .resume = acpi_restore_bm_rld, + }; + ++static struct syscore acpi_sleep_syscore = { ++ .ops = &acpi_sleep_syscore_ops, ++}; ++ + static void acpi_sleep_syscore_init(void) + { +- register_syscore_ops(&acpi_sleep_syscore_ops); ++ register_syscore(&acpi_sleep_syscore); + } + #else + static inline void acpi_sleep_syscore_init(void) {} +diff --git a/drivers/base/firmware_loader/main.c b/drivers/base/firmware_loader/main.c +index 6942c62fa59d..8191dbab92c4 100644 +--- a/drivers/base/firmware_loader/main.c ++++ b/drivers/base/firmware_loader/main.c +@@ -1585,16 +1585,20 @@ static int fw_pm_notify(struct notifier_block *notify_block, + } + + /* stop caching firmware once syscore_suspend is reached */ +-static int fw_suspend(void) ++static int fw_suspend(void *data) + { + fw_cache.state = FW_LOADER_NO_CACHE; + return 0; + } + +-static struct syscore_ops fw_syscore_ops = { ++static const struct syscore_ops fw_syscore_ops = { + .suspend = fw_suspend, + }; + ++static struct syscore fw_syscore = { ++ .ops = &fw_syscore_ops, ++}; ++ + static int __init register_fw_pm_ops(void) + { + int ret; +@@ -1610,14 +1614,14 @@ static int __init register_fw_pm_ops(void) + if (ret) + return ret; + +- register_syscore_ops(&fw_syscore_ops); ++ register_syscore(&fw_syscore); + + return ret; + } + + static inline void unregister_fw_pm_ops(void) + { +- unregister_syscore_ops(&fw_syscore_ops); ++ unregister_syscore(&fw_syscore); + unregister_pm_notifier(&fw_cache.pm_notify); + } + #else +diff --git a/drivers/base/syscore.c b/drivers/base/syscore.c +index 13db1f78d2ce..483adb796654 100644 +--- a/drivers/base/syscore.c ++++ b/drivers/base/syscore.c +@@ -11,32 +11,32 @@ + #include + #include + +-static LIST_HEAD(syscore_ops_list); +-static DEFINE_MUTEX(syscore_ops_lock); ++static LIST_HEAD(syscore_list); ++static DEFINE_MUTEX(syscore_lock); + + /** +- * register_syscore_ops - Register a set of system core operations. +- * @ops: System core operations to register. ++ * register_syscore - Register a set of system core operations. ++ * @syscore: System core operations to register. + */ +-void register_syscore_ops(struct syscore_ops *ops) ++void register_syscore(struct syscore *syscore) + { +- mutex_lock(&syscore_ops_lock); +- list_add_tail(&ops->node, &syscore_ops_list); +- mutex_unlock(&syscore_ops_lock); ++ mutex_lock(&syscore_lock); ++ list_add_tail(&syscore->node, &syscore_list); ++ mutex_unlock(&syscore_lock); + } +-EXPORT_SYMBOL_GPL(register_syscore_ops); ++EXPORT_SYMBOL_GPL(register_syscore); + + /** +- * unregister_syscore_ops - Unregister a set of system core operations. +- * @ops: System core operations to unregister. ++ * unregister_syscore - Unregister a set of system core operations. ++ * @syscore: System core operations to unregister. + */ +-void unregister_syscore_ops(struct syscore_ops *ops) ++void unregister_syscore(struct syscore *syscore) + { +- mutex_lock(&syscore_ops_lock); +- list_del(&ops->node); +- mutex_unlock(&syscore_ops_lock); ++ mutex_lock(&syscore_lock); ++ list_del(&syscore->node); ++ mutex_unlock(&syscore_lock); + } +-EXPORT_SYMBOL_GPL(unregister_syscore_ops); ++EXPORT_SYMBOL_GPL(unregister_syscore); + + #ifdef CONFIG_PM_SLEEP + /** +@@ -46,7 +46,7 @@ EXPORT_SYMBOL_GPL(unregister_syscore_ops); + */ + int syscore_suspend(void) + { +- struct syscore_ops *ops; ++ struct syscore *syscore; + int ret = 0; + + trace_suspend_resume(TPS("syscore_suspend"), 0, true); +@@ -59,25 +59,27 @@ int syscore_suspend(void) + WARN_ONCE(!irqs_disabled(), + "Interrupts enabled before system core suspend.\n"); + +- list_for_each_entry_reverse(ops, &syscore_ops_list, node) +- if (ops->suspend) { +- pm_pr_dbg("Calling %pS\n", ops->suspend); +- ret = ops->suspend(); ++ list_for_each_entry_reverse(syscore, &syscore_list, node) ++ if (syscore->ops->suspend) { ++ pm_pr_dbg("Calling %pS\n", syscore->ops->suspend); ++ ret = syscore->ops->suspend(syscore->data); + if (ret) + goto err_out; + WARN_ONCE(!irqs_disabled(), +- "Interrupts enabled after %pS\n", ops->suspend); ++ "Interrupts enabled after %pS\n", ++ syscore->ops->suspend); + } + + trace_suspend_resume(TPS("syscore_suspend"), 0, false); + return 0; + + err_out: +- pr_err("PM: System core suspend callback %pS failed.\n", ops->suspend); ++ pr_err("PM: System core suspend callback %pS failed.\n", ++ syscore->ops->suspend); + +- list_for_each_entry_continue(ops, &syscore_ops_list, node) +- if (ops->resume) +- ops->resume(); ++ list_for_each_entry_continue(syscore, &syscore_list, node) ++ if (syscore->ops->resume) ++ syscore->ops->resume(syscore->data); + + return ret; + } +@@ -90,18 +92,19 @@ EXPORT_SYMBOL_GPL(syscore_suspend); + */ + void syscore_resume(void) + { +- struct syscore_ops *ops; ++ struct syscore *syscore; + + trace_suspend_resume(TPS("syscore_resume"), 0, true); + WARN_ONCE(!irqs_disabled(), + "Interrupts enabled before system core resume.\n"); + +- list_for_each_entry(ops, &syscore_ops_list, node) +- if (ops->resume) { +- pm_pr_dbg("Calling %pS\n", ops->resume); +- ops->resume(); ++ list_for_each_entry(syscore, &syscore_list, node) ++ if (syscore->ops->resume) { ++ pm_pr_dbg("Calling %pS\n", syscore->ops->resume); ++ syscore->ops->resume(syscore->data); + WARN_ONCE(!irqs_disabled(), +- "Interrupts enabled after %pS\n", ops->resume); ++ "Interrupts enabled after %pS\n", ++ syscore->ops->resume); + } + trace_suspend_resume(TPS("syscore_resume"), 0, false); + } +@@ -113,16 +116,17 @@ EXPORT_SYMBOL_GPL(syscore_resume); + */ + void syscore_shutdown(void) + { +- struct syscore_ops *ops; ++ struct syscore *syscore; + +- mutex_lock(&syscore_ops_lock); ++ mutex_lock(&syscore_lock); + +- list_for_each_entry_reverse(ops, &syscore_ops_list, node) +- if (ops->shutdown) { ++ list_for_each_entry_reverse(syscore, &syscore_list, node) ++ if (syscore->ops->shutdown) { + if (initcall_debug) +- pr_info("PM: Calling %pS\n", ops->shutdown); +- ops->shutdown(); ++ pr_info("PM: Calling %pS\n", ++ syscore->ops->shutdown); ++ syscore->ops->shutdown(syscore->data); + } + +- mutex_unlock(&syscore_ops_lock); ++ mutex_unlock(&syscore_lock); + } +diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c +index 00cb792bda18..dd94145c9b22 100644 +--- a/drivers/bus/mvebu-mbus.c ++++ b/drivers/bus/mvebu-mbus.c +@@ -1006,7 +1006,7 @@ static __init int mvebu_mbus_debugfs_init(void) + } + fs_initcall(mvebu_mbus_debugfs_init); + +-static int mvebu_mbus_suspend(void) ++static int mvebu_mbus_suspend(void *data) + { + struct mvebu_mbus_state *s = &mbus_state; + int win; +@@ -1040,7 +1040,7 @@ static int mvebu_mbus_suspend(void) + return 0; + } + +-static void mvebu_mbus_resume(void) ++static void mvebu_mbus_resume(void *data) + { + struct mvebu_mbus_state *s = &mbus_state; + int win; +@@ -1069,9 +1069,13 @@ static void mvebu_mbus_resume(void) + } + } + +-static struct syscore_ops mvebu_mbus_syscore_ops = { +- .suspend = mvebu_mbus_suspend, +- .resume = mvebu_mbus_resume, ++static const struct syscore_ops mvebu_mbus_syscore_ops = { ++ .suspend = mvebu_mbus_suspend, ++ .resume = mvebu_mbus_resume, ++}; ++ ++static struct syscore mvebu_mbus_syscore = { ++ .ops = &mvebu_mbus_syscore_ops, + }; + + static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, +@@ -1118,7 +1122,7 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, + writel(UNIT_SYNC_BARRIER_ALL, + mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF); + +- register_syscore_ops(&mvebu_mbus_syscore_ops); ++ register_syscore(&mvebu_mbus_syscore); + + return 0; + } +diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c +index acf780a81589..2310f6f73162 100644 +--- a/drivers/clk/at91/pmc.c ++++ b/drivers/clk/at91/pmc.c +@@ -115,7 +115,7 @@ struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, + /* Address in SECURAM that say if we suspend to backup mode. */ + static void __iomem *at91_pmc_backup_suspend; + +-static int at91_pmc_suspend(void) ++static int at91_pmc_suspend(void *data) + { + unsigned int backup; + +@@ -129,7 +129,7 @@ static int at91_pmc_suspend(void) + return clk_save_context(); + } + +-static void at91_pmc_resume(void) ++static void at91_pmc_resume(void *data) + { + unsigned int backup; + +@@ -143,11 +143,15 @@ static void at91_pmc_resume(void) + clk_restore_context(); + } + +-static struct syscore_ops pmc_syscore_ops = { ++static const struct syscore_ops pmc_syscore_ops = { + .suspend = at91_pmc_suspend, + .resume = at91_pmc_resume, + }; + ++static struct syscore pmc_syscore = { ++ .ops = &pmc_syscore_ops, ++}; ++ + static const struct of_device_id pmc_dt_ids[] = { + { .compatible = "atmel,sama5d2-pmc" }, + { .compatible = "microchip,sama7g5-pmc", }, +@@ -185,7 +189,7 @@ static int __init pmc_register_ops(void) + return -ENOMEM; + } + +- register_syscore_ops(&pmc_syscore_ops); ++ register_syscore(&pmc_syscore); + + return 0; + } +diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c +index 9e11f1c7c397..41eb38552a9c 100644 +--- a/drivers/clk/imx/clk-vf610.c ++++ b/drivers/clk/imx/clk-vf610.c +@@ -139,7 +139,7 @@ static struct clk * __init vf610_get_fixed_clock( + return clk; + }; + +-static int vf610_clk_suspend(void) ++static int vf610_clk_suspend(void *data) + { + int i; + +@@ -156,7 +156,7 @@ static int vf610_clk_suspend(void) + return 0; + } + +-static void vf610_clk_resume(void) ++static void vf610_clk_resume(void *data) + { + int i; + +@@ -171,11 +171,15 @@ static void vf610_clk_resume(void) + writel_relaxed(ccgr[i], CCM_CCGRx(i)); + } + +-static struct syscore_ops vf610_clk_syscore_ops = { ++static const struct syscore_ops vf610_clk_syscore_ops = { + .suspend = vf610_clk_suspend, + .resume = vf610_clk_resume, + }; + ++static struct syscore vf610_clk_syscore = { ++ .ops = &vf610_clk_syscore_ops, ++}; ++ + static void __init vf610_clocks_init(struct device_node *ccm_node) + { + struct device_node *np; +@@ -462,7 +466,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) + clk_prepare_enable(clk[clks_init_on[i]]); + +- register_syscore_ops(&vf610_clk_syscore_ops); ++ register_syscore(&vf610_clk_syscore); + + /* Add the clocks to provider list */ + clk_data.clks = clk; +diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c +index 590e9c85cb25..94cee44c854f 100644 +--- a/drivers/clk/ingenic/jz4725b-cgu.c ++++ b/drivers/clk/ingenic/jz4725b-cgu.c +@@ -268,6 +268,6 @@ static void __init jz4725b_cgu_init(struct device_node *np) + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init); +diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c +index 3e0a30574ebb..2def3aedc8dd 100644 +--- a/drivers/clk/ingenic/jz4740-cgu.c ++++ b/drivers/clk/ingenic/jz4740-cgu.c +@@ -266,6 +266,6 @@ static void __init jz4740_cgu_init(struct device_node *np) + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init); +diff --git a/drivers/clk/ingenic/jz4755-cgu.c b/drivers/clk/ingenic/jz4755-cgu.c +index f2c2d848dab7..17cf5dcaece9 100644 +--- a/drivers/clk/ingenic/jz4755-cgu.c ++++ b/drivers/clk/ingenic/jz4755-cgu.c +@@ -337,7 +337,7 @@ static void __init jz4755_cgu_init(struct device_node *np) + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + /* + * CGU has some children devices, this is useful for probing children devices +diff --git a/drivers/clk/ingenic/jz4760-cgu.c b/drivers/clk/ingenic/jz4760-cgu.c +index e407f00bd594..372fe4b07992 100644 +--- a/drivers/clk/ingenic/jz4760-cgu.c ++++ b/drivers/clk/ingenic/jz4760-cgu.c +@@ -436,7 +436,7 @@ static void __init jz4760_cgu_init(struct device_node *np) + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + + /* We only probe via devicetree, no need for a platform driver */ +diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c +index 6ae1740367f9..58f1d3bad677 100644 +--- a/drivers/clk/ingenic/jz4770-cgu.c ++++ b/drivers/clk/ingenic/jz4770-cgu.c +@@ -456,7 +456,7 @@ static void __init jz4770_cgu_init(struct device_node *np) + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + + /* We only probe via devicetree, no need for a platform driver */ +diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c +index 07e2f3c5c454..1e88aef7ac0f 100644 +--- a/drivers/clk/ingenic/jz4780-cgu.c ++++ b/drivers/clk/ingenic/jz4780-cgu.c +@@ -803,6 +803,6 @@ static void __init jz4780_cgu_init(struct device_node *np) + return; + } + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init); +diff --git a/drivers/clk/ingenic/pm.c b/drivers/clk/ingenic/pm.c +index 341752b640d2..206d5cf2872f 100644 +--- a/drivers/clk/ingenic/pm.c ++++ b/drivers/clk/ingenic/pm.c +@@ -15,7 +15,7 @@ + + static void __iomem * __maybe_unused ingenic_cgu_base; + +-static int __maybe_unused ingenic_cgu_pm_suspend(void) ++static int __maybe_unused ingenic_cgu_pm_suspend(void *data) + { + u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); + +@@ -24,22 +24,26 @@ static int __maybe_unused ingenic_cgu_pm_suspend(void) + return 0; + } + +-static void __maybe_unused ingenic_cgu_pm_resume(void) ++static void __maybe_unused ingenic_cgu_pm_resume(void *data) + { + u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); + + writel(val & ~LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR); + } + +-static struct syscore_ops __maybe_unused ingenic_cgu_pm_ops = { ++static const struct syscore_ops __maybe_unused ingenic_cgu_pm_ops = { + .suspend = ingenic_cgu_pm_suspend, + .resume = ingenic_cgu_pm_resume, + }; + +-void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu) ++static struct syscore __maybe_unused ingenic_cgu_pm = { ++ .ops = &ingenic_cgu_pm_ops, ++}; ++ ++void ingenic_cgu_register_syscore(struct ingenic_cgu *cgu) + { + if (IS_ENABLED(CONFIG_PM_SLEEP)) { + ingenic_cgu_base = cgu->base; +- register_syscore_ops(&ingenic_cgu_pm_ops); ++ register_syscore(&ingenic_cgu_pm); + } + } +diff --git a/drivers/clk/ingenic/pm.h b/drivers/clk/ingenic/pm.h +index fa7540407b6b..0dcb57dc64cb 100644 +--- a/drivers/clk/ingenic/pm.h ++++ b/drivers/clk/ingenic/pm.h +@@ -7,6 +7,6 @@ + + struct ingenic_cgu; + +-void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu); ++void ingenic_cgu_register_syscore(struct ingenic_cgu *cgu); + + #endif /* DRIVERS_CLK_INGENIC_PM_H */ +diff --git a/drivers/clk/ingenic/tcu.c b/drivers/clk/ingenic/tcu.c +index 7d04ef40b7cf..bc6a51da2072 100644 +--- a/drivers/clk/ingenic/tcu.c ++++ b/drivers/clk/ingenic/tcu.c +@@ -455,7 +455,7 @@ static int __init ingenic_tcu_probe(struct device_node *np) + return ret; + } + +-static int __maybe_unused tcu_pm_suspend(void) ++static int __maybe_unused tcu_pm_suspend(void *data) + { + struct ingenic_tcu *tcu = ingenic_tcu; + +@@ -465,7 +465,7 @@ static int __maybe_unused tcu_pm_suspend(void) + return 0; + } + +-static void __maybe_unused tcu_pm_resume(void) ++static void __maybe_unused tcu_pm_resume(void *data) + { + struct ingenic_tcu *tcu = ingenic_tcu; + +@@ -473,11 +473,15 @@ static void __maybe_unused tcu_pm_resume(void) + clk_enable(tcu->clk); + } + +-static struct syscore_ops __maybe_unused tcu_pm_ops = { ++static const struct syscore_ops __maybe_unused tcu_pm_ops = { + .suspend = tcu_pm_suspend, + .resume = tcu_pm_resume, + }; + ++static struct syscore __maybe_unused tcu_pm = { ++ .ops = &tcu_pm_ops, ++}; ++ + static void __init ingenic_tcu_init(struct device_node *np) + { + int ret = ingenic_tcu_probe(np); +@@ -486,7 +490,7 @@ static void __init ingenic_tcu_init(struct device_node *np) + pr_crit("Failed to initialize TCU clocks: %d\n", ret); + + if (IS_ENABLED(CONFIG_PM_SLEEP)) +- register_syscore_ops(&tcu_pm_ops); ++ register_syscore(&tcu_pm); + } + + CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init); +diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c +index d80886caf393..d89bdfb7c219 100644 +--- a/drivers/clk/ingenic/x1000-cgu.c ++++ b/drivers/clk/ingenic/x1000-cgu.c +@@ -556,7 +556,7 @@ static void __init x1000_cgu_init(struct device_node *np) + return; + } + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + /* + * CGU has some children devices, this is useful for probing children devices +diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c +index 0fd46e50a513..acf856e5009e 100644 +--- a/drivers/clk/ingenic/x1830-cgu.c ++++ b/drivers/clk/ingenic/x1830-cgu.c +@@ -463,7 +463,7 @@ static void __init x1830_cgu_init(struct device_node *np) + return; + } + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + /* + * CGU has some children devices, this is useful for probing children devices +diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c +index 785dbede4835..5adbbd91a6db 100644 +--- a/drivers/clk/mvebu/common.c ++++ b/drivers/clk/mvebu/common.c +@@ -215,22 +215,26 @@ static struct clk *clk_gating_get_src( + return ERR_PTR(-ENODEV); + } + +-static int mvebu_clk_gating_suspend(void) ++static int mvebu_clk_gating_suspend(void *data) + { + ctrl->saved_reg = readl(ctrl->base); + return 0; + } + +-static void mvebu_clk_gating_resume(void) ++static void mvebu_clk_gating_resume(void *data) + { + writel(ctrl->saved_reg, ctrl->base); + } + +-static struct syscore_ops clk_gate_syscore_ops = { ++static const struct syscore_ops clk_gate_syscore_ops = { + .suspend = mvebu_clk_gating_suspend, + .resume = mvebu_clk_gating_resume, + }; + ++static struct syscore clk_gate_syscore = { ++ .ops = &clk_gate_syscore_ops, ++}; ++ + void __init mvebu_clk_gating_setup(struct device_node *np, + const struct clk_gating_soc_desc *desc) + { +@@ -284,7 +288,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, + + of_clk_add_provider(np, clk_gating_get_src, ctrl); + +- register_syscore_ops(&clk_gate_syscore_ops); ++ register_syscore(&clk_gate_syscore); + + return; + gates_out: +diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c +index 0a1e017df7c6..9cf3e1e43b78 100644 +--- a/drivers/clk/rockchip/clk-rk3288.c ++++ b/drivers/clk/rockchip/clk-rk3288.c +@@ -871,7 +871,7 @@ static const int rk3288_saved_cru_reg_ids[] = { + + static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)]; + +-static int rk3288_clk_suspend(void) ++static int rk3288_clk_suspend(void *data) + { + int i, reg_id; + +@@ -906,7 +906,7 @@ static int rk3288_clk_suspend(void) + return 0; + } + +-static void rk3288_clk_resume(void) ++static void rk3288_clk_resume(void *data) + { + int i, reg_id; + +@@ -923,11 +923,15 @@ static void rk3288_clk_shutdown(void) + writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON); + } + +-static struct syscore_ops rk3288_clk_syscore_ops = { ++static const struct syscore_ops rk3288_clk_syscore_ops = { + .suspend = rk3288_clk_suspend, + .resume = rk3288_clk_resume, + }; + ++static struct syscore rk3288_clk_syscore = { ++ .ops = &rk3288_clk_syscore_ops, ++}; ++ + static void __init rk3288_common_init(struct device_node *np, + enum rk3288_variant soc) + { +@@ -976,7 +980,7 @@ static void __init rk3288_common_init(struct device_node *np, + + rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST, + rk3288_clk_shutdown); +- register_syscore_ops(&rk3288_clk_syscore_ops); ++ register_syscore(&rk3288_clk_syscore); + + rockchip_clk_of_add_provider(np, ctx); + } +diff --git a/drivers/clk/samsung/clk-s5pv210-audss.c b/drivers/clk/samsung/clk-s5pv210-audss.c +index b1fd8fac3a4c..c9fcb23de183 100644 +--- a/drivers/clk/samsung/clk-s5pv210-audss.c ++++ b/drivers/clk/samsung/clk-s5pv210-audss.c +@@ -36,7 +36,7 @@ static unsigned long reg_save[][2] = { + {ASS_CLK_GATE, 0}, + }; + +-static int s5pv210_audss_clk_suspend(void) ++static int s5pv210_audss_clk_suspend(void *data) + { + int i; + +@@ -46,7 +46,7 @@ static int s5pv210_audss_clk_suspend(void) + return 0; + } + +-static void s5pv210_audss_clk_resume(void) ++static void s5pv210_audss_clk_resume(void *data) + { + int i; + +@@ -54,10 +54,14 @@ static void s5pv210_audss_clk_resume(void) + writel(reg_save[i][1], reg_base + reg_save[i][0]); + } + +-static struct syscore_ops s5pv210_audss_clk_syscore_ops = { ++static const struct syscore_ops s5pv210_audss_clk_syscore_ops = { + .suspend = s5pv210_audss_clk_suspend, + .resume = s5pv210_audss_clk_resume, + }; ++ ++static struct syscore s5pv210_audss_clk_syscore = { ++ .ops = &s5pv210_audss_clk_syscore_ops, ++}; + #endif /* CONFIG_PM_SLEEP */ + + /* register s5pv210_audss clocks */ +@@ -175,7 +179,7 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev) + } + + #ifdef CONFIG_PM_SLEEP +- register_syscore_ops(&s5pv210_audss_clk_syscore_ops); ++ register_syscore(&s5pv210_audss_clk_syscore); + #endif + + return 0; +diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c +index dbc9925ca8f4..c149ca6c2217 100644 +--- a/drivers/clk/samsung/clk.c ++++ b/drivers/clk/samsung/clk.c +@@ -271,7 +271,7 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, + } + + #ifdef CONFIG_PM_SLEEP +-static int samsung_clk_suspend(void) ++static int samsung_clk_suspend(void *data) + { + struct samsung_clock_reg_cache *reg_cache; + +@@ -284,7 +284,7 @@ static int samsung_clk_suspend(void) + return 0; + } + +-static void samsung_clk_resume(void) ++static void samsung_clk_resume(void *data) + { + struct samsung_clock_reg_cache *reg_cache; + +@@ -293,11 +293,15 @@ static void samsung_clk_resume(void) + reg_cache->rd_num); + } + +-static struct syscore_ops samsung_clk_syscore_ops = { ++static const struct syscore_ops samsung_clk_syscore_ops = { + .suspend = samsung_clk_suspend, + .resume = samsung_clk_resume, + }; + ++static struct syscore samsung_clk_syscore = { ++ .ops = &samsung_clk_syscore_ops, ++}; ++ + void samsung_clk_extended_sleep_init(void __iomem *reg_base, + const unsigned long *rdump, + unsigned long nr_rdump, +@@ -316,7 +320,7 @@ void samsung_clk_extended_sleep_init(void __iomem *reg_base, + panic("could not allocate register dump storage.\n"); + + if (list_empty(&clock_reg_cache_list)) +- register_syscore_ops(&samsung_clk_syscore_ops); ++ register_syscore(&samsung_clk_syscore); + + reg_cache->reg_base = reg_base; + reg_cache->rd_num = nr_rdump; +diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c +index 412902f573b5..504d0ea997a5 100644 +--- a/drivers/clk/tegra/clk-tegra210.c ++++ b/drivers/clk/tegra/clk-tegra210.c +@@ -3444,7 +3444,7 @@ static void tegra210_disable_cpu_clock(u32 cpu) + static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx; + static u32 cpu_softrst_ctx[3]; + +-static int tegra210_clk_suspend(void) ++static int tegra210_clk_suspend(void *data) + { + unsigned int i; + +@@ -3465,7 +3465,7 @@ static int tegra210_clk_suspend(void) + return 0; + } + +-static void tegra210_clk_resume(void) ++static void tegra210_clk_resume(void *data) + { + unsigned int i; + +@@ -3523,13 +3523,17 @@ static void tegra210_cpu_clock_resume(void) + } + #endif + +-static struct syscore_ops tegra_clk_syscore_ops = { ++static const struct syscore_ops tegra_clk_syscore_ops = { + #ifdef CONFIG_PM_SLEEP + .suspend = tegra210_clk_suspend, + .resume = tegra210_clk_resume, + #endif + }; + ++static struct syscore tegra_clk_syscore = { ++ .ops = &tegra_clk_syscore_ops, ++}; ++ + static struct tegra_cpu_car_ops tegra210_cpu_car_ops = { + .wait_for_reset = tegra210_wait_cpu_in_reset, + .disable_clock = tegra210_disable_cpu_clock, +@@ -3813,6 +3817,6 @@ static void __init tegra210_clock_init(struct device_node *np) + + tegra_cpu_car_ops = &tegra210_cpu_car_ops; + +- register_syscore_ops(&tegra_clk_syscore_ops); ++ register_syscore(&tegra_clk_syscore); + } + CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); +diff --git a/drivers/clocksource/timer-armada-370-xp.c b/drivers/clocksource/timer-armada-370-xp.c +index 54284c1c0651..f2b4cc40db93 100644 +--- a/drivers/clocksource/timer-armada-370-xp.c ++++ b/drivers/clocksource/timer-armada-370-xp.c +@@ -207,14 +207,14 @@ static int armada_370_xp_timer_dying_cpu(unsigned int cpu) + + static u32 timer0_ctrl_reg, timer0_local_ctrl_reg; + +-static int armada_370_xp_timer_suspend(void) ++static int armada_370_xp_timer_suspend(void *data) + { + timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF); + timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF); + return 0; + } + +-static void armada_370_xp_timer_resume(void) ++static void armada_370_xp_timer_resume(void *data) + { + writel(0xffffffff, timer_base + TIMER0_VAL_OFF); + writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); +@@ -222,11 +222,15 @@ static void armada_370_xp_timer_resume(void) + writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF); + } + +-static struct syscore_ops armada_370_xp_timer_syscore_ops = { ++static const struct syscore_ops armada_370_xp_timer_syscore_ops = { + .suspend = armada_370_xp_timer_suspend, + .resume = armada_370_xp_timer_resume, + }; + ++static struct syscore armada_370_xp_timer_syscore = { ++ .ops = &armada_370_xp_timer_syscore_ops, ++}; ++ + static unsigned long armada_370_delay_timer_read(void) + { + return ~readl(timer_base + TIMER0_VAL_OFF); +@@ -324,7 +328,7 @@ static int __init armada_370_xp_timer_common_init(struct device_node *np) + return res; + } + +- register_syscore_ops(&armada_370_xp_timer_syscore_ops); ++ register_syscore(&armada_370_xp_timer_syscore); + + return 0; + } +diff --git a/drivers/cpuidle/cpuidle-psci.c b/drivers/cpuidle/cpuidle-psci.c +index b19bc60cc627..3372e1f90561 100644 +--- a/drivers/cpuidle/cpuidle-psci.c ++++ b/drivers/cpuidle/cpuidle-psci.c +@@ -177,26 +177,30 @@ static void psci_idle_syscore_switch(bool suspend) + } + } + +-static int psci_idle_syscore_suspend(void) ++static int psci_idle_syscore_suspend(void *data) + { + psci_idle_syscore_switch(true); + return 0; + } + +-static void psci_idle_syscore_resume(void) ++static void psci_idle_syscore_resume(void *data) + { + psci_idle_syscore_switch(false); + } + +-static struct syscore_ops psci_idle_syscore_ops = { ++static const struct syscore_ops psci_idle_syscore_ops = { + .suspend = psci_idle_syscore_suspend, + .resume = psci_idle_syscore_resume, + }; + ++static struct syscore psci_idle_syscore = { ++ .ops = &psci_idle_syscore_ops, ++}; ++ + static void psci_idle_init_syscore(void) + { + if (psci_cpuidle_use_syscore) +- register_syscore_ops(&psci_idle_syscore_ops); ++ register_syscore(&psci_idle_syscore); + } + + static void psci_idle_init_cpuhp(void) +diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c +index 441ba95b38cf..647b6f4861b7 100644 +--- a/drivers/gpio/gpio-mxc.c ++++ b/drivers/gpio/gpio-mxc.c +@@ -675,7 +675,7 @@ static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { + RUNTIME_PM_OPS(mxc_gpio_runtime_suspend, mxc_gpio_runtime_resume, NULL) + }; + +-static int mxc_gpio_syscore_suspend(void) ++static int mxc_gpio_syscore_suspend(void *data) + { + struct mxc_gpio_port *port; + int ret; +@@ -692,7 +692,7 @@ static int mxc_gpio_syscore_suspend(void) + return 0; + } + +-static void mxc_gpio_syscore_resume(void) ++static void mxc_gpio_syscore_resume(void *data) + { + struct mxc_gpio_port *port; + int ret; +@@ -709,11 +709,15 @@ static void mxc_gpio_syscore_resume(void) + } + } + +-static struct syscore_ops mxc_gpio_syscore_ops = { ++static const struct syscore_ops mxc_gpio_syscore_ops = { + .suspend = mxc_gpio_syscore_suspend, + .resume = mxc_gpio_syscore_resume, + }; + ++static struct syscore mxc_gpio_syscore = { ++ .ops = &mxc_gpio_syscore_ops, ++}; ++ + static struct platform_driver mxc_gpio_driver = { + .driver = { + .name = "gpio-mxc", +@@ -726,7 +730,7 @@ static struct platform_driver mxc_gpio_driver = { + + static int __init gpio_mxc_init(void) + { +- register_syscore_ops(&mxc_gpio_syscore_ops); ++ register_syscore(&mxc_gpio_syscore); + + return platform_driver_register(&mxc_gpio_driver); + } +diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c +index fa22f3faa163..664cf1eef494 100644 +--- a/drivers/gpio/gpio-pxa.c ++++ b/drivers/gpio/gpio-pxa.c +@@ -747,7 +747,7 @@ static int __init pxa_gpio_dt_init(void) + device_initcall(pxa_gpio_dt_init); + + #ifdef CONFIG_PM +-static int pxa_gpio_suspend(void) ++static int pxa_gpio_suspend(void *data) + { + struct pxa_gpio_chip *pchip = pxa_gpio_chip; + struct pxa_gpio_bank *c; +@@ -768,7 +768,7 @@ static int pxa_gpio_suspend(void) + return 0; + } + +-static void pxa_gpio_resume(void) ++static void pxa_gpio_resume(void *data) + { + struct pxa_gpio_chip *pchip = pxa_gpio_chip; + struct pxa_gpio_bank *c; +@@ -792,14 +792,18 @@ static void pxa_gpio_resume(void) + #define pxa_gpio_resume NULL + #endif + +-static struct syscore_ops pxa_gpio_syscore_ops = { ++static const struct syscore_ops pxa_gpio_syscore_ops = { + .suspend = pxa_gpio_suspend, + .resume = pxa_gpio_resume, + }; + ++static struct syscore pxa_gpio_syscore = { ++ .ops = &pxa_gpio_syscore_ops, ++}; ++ + static int __init pxa_gpio_sysinit(void) + { +- register_syscore_ops(&pxa_gpio_syscore_ops); ++ register_syscore(&pxa_gpio_syscore); + return 0; + } + postcore_initcall(pxa_gpio_sysinit); +diff --git a/drivers/gpio/gpio-sa1100.c b/drivers/gpio/gpio-sa1100.c +index 7f6a62f5d1ee..1938ffa2f4f3 100644 +--- a/drivers/gpio/gpio-sa1100.c ++++ b/drivers/gpio/gpio-sa1100.c +@@ -256,7 +256,7 @@ static void sa1100_gpio_handler(struct irq_desc *desc) + } while (mask); + } + +-static int sa1100_gpio_suspend(void) ++static int sa1100_gpio_suspend(void *data) + { + struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip; + +@@ -275,19 +275,23 @@ static int sa1100_gpio_suspend(void) + return 0; + } + +-static void sa1100_gpio_resume(void) ++static void sa1100_gpio_resume(void *data) + { + sa1100_update_edge_regs(&sa1100_gpio_chip); + } + +-static struct syscore_ops sa1100_gpio_syscore_ops = { ++static const struct syscore_ops sa1100_gpio_syscore_ops = { + .suspend = sa1100_gpio_suspend, + .resume = sa1100_gpio_resume, + }; + ++static struct syscore sa1100_gpio_syscore = { ++ .ops = &sa1100_gpio_syscore_ops, ++}; ++ + static int __init sa1100_gpio_init_devicefs(void) + { +- register_syscore_ops(&sa1100_gpio_syscore_ops); ++ register_syscore(&sa1100_gpio_syscore); + return 0; + } + +diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c +index 3ab62277b6be..7000e2a5511f 100644 +--- a/drivers/hv/vmbus_drv.c ++++ b/drivers/hv/vmbus_drv.c +@@ -2861,7 +2861,7 @@ static void hv_crash_handler(struct pt_regs *regs) + hv_synic_disable_regs(cpu); + }; + +-static int hv_synic_suspend(void) ++static int hv_synic_suspend(void *data) + { + /* + * When we reach here, all the non-boot CPUs have been offlined. +@@ -2888,7 +2888,7 @@ static int hv_synic_suspend(void) + return 0; + } + +-static void hv_synic_resume(void) ++static void hv_synic_resume(void *data) + { + hv_synic_enable_regs(0); + +@@ -2900,11 +2900,15 @@ static void hv_synic_resume(void) + } + + /* The callbacks run only on CPU0, with irqs_disabled. */ +-static struct syscore_ops hv_synic_syscore_ops = { ++static const struct syscore_ops hv_synic_syscore_ops = { + .suspend = hv_synic_suspend, + .resume = hv_synic_resume, + }; + ++static struct syscore hv_synic_syscore = { ++ .ops = &hv_synic_syscore_ops, ++}; ++ + static int __init hv_acpi_init(void) + { + int ret; +@@ -2947,7 +2951,7 @@ static int __init hv_acpi_init(void) + hv_setup_kexec_handler(hv_kexec_handler); + hv_setup_crash_handler(hv_crash_handler); + +- register_syscore_ops(&hv_synic_syscore_ops); ++ register_syscore(&hv_synic_syscore); + + return 0; + +@@ -2961,7 +2965,7 @@ static void __exit vmbus_exit(void) + { + int cpu; + +- unregister_syscore_ops(&hv_synic_syscore_ops); ++ unregister_syscore(&hv_synic_syscore); + + hv_remove_kexec_handler(); + hv_remove_crash_handler(); +diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c +index 76efd74124b3..4aa09660804b 100644 +--- a/drivers/iommu/amd/init.c ++++ b/drivers/iommu/amd/init.c +@@ -3050,7 +3050,7 @@ static void disable_iommus(void) + * disable suspend until real resume implemented + */ + +-static void amd_iommu_resume(void) ++static void amd_iommu_resume(void *data) + { + struct amd_iommu *iommu; + +@@ -3064,7 +3064,7 @@ static void amd_iommu_resume(void) + amd_iommu_enable_interrupts(); + } + +-static int amd_iommu_suspend(void) ++static int amd_iommu_suspend(void *data) + { + /* disable IOMMUs to go out of the way for BIOS */ + disable_iommus(); +@@ -3072,11 +3072,15 @@ static int amd_iommu_suspend(void) + return 0; + } + +-static struct syscore_ops amd_iommu_syscore_ops = { ++static const struct syscore_ops amd_iommu_syscore_ops = { + .suspend = amd_iommu_suspend, + .resume = amd_iommu_resume, + }; + ++static struct syscore amd_iommu_syscore = { ++ .ops = &amd_iommu_syscore_ops, ++}; ++ + static void __init free_iommu_resources(void) + { + free_iommu_all(); +@@ -3421,7 +3425,7 @@ static int __init state_next(void) + init_state = IOMMU_ENABLED; + break; + case IOMMU_ENABLED: +- register_syscore_ops(&amd_iommu_syscore_ops); ++ register_syscore(&amd_iommu_syscore); + iommu_snp_enable(); + ret = amd_iommu_init_pci(); + init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; +@@ -3524,12 +3528,12 @@ int __init amd_iommu_enable(void) + + void amd_iommu_disable(void) + { +- amd_iommu_suspend(); ++ amd_iommu_suspend(NULL); + } + + int amd_iommu_reenable(int mode) + { +- amd_iommu_resume(); ++ amd_iommu_resume(NULL); + + return 0; + } +diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c +index 79676188f60f..3d1cacad559b 100644 +--- a/drivers/iommu/intel/iommu.c ++++ b/drivers/iommu/intel/iommu.c +@@ -2305,7 +2305,7 @@ static void iommu_flush_all(void) + } + } + +-static int iommu_suspend(void) ++static int iommu_suspend(void *data) + { + struct dmar_drhd_unit *drhd; + struct intel_iommu *iommu = NULL; +@@ -2332,7 +2332,7 @@ static int iommu_suspend(void) + return 0; + } + +-static void iommu_resume(void) ++static void iommu_resume(void *data) + { + struct dmar_drhd_unit *drhd; + struct intel_iommu *iommu = NULL; +@@ -2363,14 +2363,18 @@ static void iommu_resume(void) + } + } + +-static struct syscore_ops iommu_syscore_ops = { ++static const struct syscore_ops iommu_syscore_ops = { + .resume = iommu_resume, + .suspend = iommu_suspend, + }; + ++static struct syscore iommu_syscore = { ++ .ops = &iommu_syscore_ops, ++}; ++ + static void __init init_iommu_pm_ops(void) + { +- register_syscore_ops(&iommu_syscore_ops); ++ register_syscore(&iommu_syscore); + } + + #else +diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c +index e7dfcf0cda43..495848442b35 100644 +--- a/drivers/irqchip/exynos-combiner.c ++++ b/drivers/irqchip/exynos-combiner.c +@@ -200,12 +200,13 @@ static void __init combiner_init(void __iomem *combiner_base, + + /** + * combiner_suspend - save interrupt combiner state before suspend ++ * @data: syscore context + * + * Save the interrupt enable set register for all combiner groups since + * the state is lost when the system enters into a sleep state. + * + */ +-static int combiner_suspend(void) ++static int combiner_suspend(void *data) + { + int i; + +@@ -218,12 +219,13 @@ static int combiner_suspend(void) + + /** + * combiner_resume - restore interrupt combiner state after resume ++ * @data: syscore context + * + * Restore the interrupt enable set register for all combiner groups since + * the state is lost when the system enters into a sleep state on suspend. + * + */ +-static void combiner_resume(void) ++static void combiner_resume(void *data) + { + int i; + +@@ -240,11 +242,15 @@ static void combiner_resume(void) + #define combiner_resume NULL + #endif + +-static struct syscore_ops combiner_syscore_ops = { ++static const struct syscore_ops combiner_syscore_ops = { + .suspend = combiner_suspend, + .resume = combiner_resume, + }; + ++static struct syscore combiner_syscore = { ++ .ops = &combiner_syscore_ops, ++}; ++ + static int __init combiner_of_init(struct device_node *np, + struct device_node *parent) + { +@@ -264,7 +270,7 @@ static int __init combiner_of_init(struct device_node *np, + + combiner_init(combiner_base, np); + +- register_syscore_ops(&combiner_syscore_ops); ++ register_syscore(&combiner_syscore); + + return 0; + } +diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c +index a44c49e985b7..a4d03a2d1569 100644 +--- a/drivers/irqchip/irq-armada-370-xp.c ++++ b/drivers/irqchip/irq-armada-370-xp.c +@@ -726,7 +726,7 @@ static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs) + } while (1); + } + +-static int mpic_suspend(void) ++static int mpic_suspend(void *data) + { + struct mpic *mpic = mpic_data; + +@@ -735,7 +735,7 @@ static int mpic_suspend(void) + return 0; + } + +-static void mpic_resume(void) ++static void mpic_resume(void *data) + { + struct mpic *mpic = mpic_data; + bool src0, src1; +@@ -788,11 +788,15 @@ static void mpic_resume(void) + mpic_ipi_resume(mpic); + } + +-static struct syscore_ops mpic_syscore_ops = { ++static const struct syscore_ops mpic_syscore_ops = { + .suspend = mpic_suspend, + .resume = mpic_resume, + }; + ++static struct syscore mpic_syscore = { ++ .ops = &mpic_syscore_ops, ++}; ++ + static int __init mpic_map_region(struct device_node *np, int index, + void __iomem **base, phys_addr_t *phys_base) + { +@@ -905,7 +909,7 @@ static int __init mpic_of_init(struct device_node *node, struct device_node *par + mpic_handle_cascade_irq, mpic); + } + +- register_syscore_ops(&mpic_syscore_ops); ++ register_syscore(&mpic_syscore); + + return 0; + } +diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c +index 821b288587ca..674138668f1c 100644 +--- a/drivers/irqchip/irq-bcm7038-l1.c ++++ b/drivers/irqchip/irq-bcm7038-l1.c +@@ -291,7 +291,7 @@ static int bcm7038_l1_init_one(struct device_node *dn, unsigned int idx, + static LIST_HEAD(bcm7038_l1_intcs_list); + static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock); + +-static int bcm7038_l1_suspend(void) ++static int bcm7038_l1_suspend(void *data) + { + struct bcm7038_l1_chip *intc; + int boot_cpu, word; +@@ -317,7 +317,7 @@ static int bcm7038_l1_suspend(void) + return 0; + } + +-static void bcm7038_l1_resume(void) ++static void bcm7038_l1_resume(void *data) + { + struct bcm7038_l1_chip *intc; + int boot_cpu, word; +@@ -338,11 +338,15 @@ static void bcm7038_l1_resume(void) + } + } + +-static struct syscore_ops bcm7038_l1_syscore_ops = { ++static const struct syscore_ops bcm7038_l1_syscore_ops = { + .suspend = bcm7038_l1_suspend, + .resume = bcm7038_l1_resume, + }; + ++static struct syscore bcm7038_l1_syscore = { ++ .ops = &bcm7038_l1_syscore_ops, ++}; ++ + static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on) + { + struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); +@@ -430,7 +434,7 @@ static int bcm7038_l1_probe(struct platform_device *pdev, struct device_node *pa + raw_spin_unlock(&bcm7038_l1_intcs_lock); + + if (list_is_singular(&bcm7038_l1_intcs_list)) +- register_syscore_ops(&bcm7038_l1_syscore_ops); ++ register_syscore(&bcm7038_l1_syscore); + #endif + + pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n", +diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c +index 23158fc8d392..a51e8e6a8181 100644 +--- a/drivers/irqchip/irq-gic-v3-its.c ++++ b/drivers/irqchip/irq-gic-v3-its.c +@@ -4996,7 +4996,7 @@ static void its_enable_quirks(struct its_node *its) + its_quirks, its); + } + +-static int its_save_disable(void) ++static int its_save_disable(void *data) + { + struct its_node *its; + int err = 0; +@@ -5032,7 +5032,7 @@ static int its_save_disable(void) + return err; + } + +-static void its_restore_enable(void) ++static void its_restore_enable(void *data) + { + struct its_node *its; + int ret; +@@ -5092,11 +5092,15 @@ static void its_restore_enable(void) + raw_spin_unlock(&its_lock); + } + +-static struct syscore_ops its_syscore_ops = { ++static const struct syscore_ops its_syscore_ops = { + .suspend = its_save_disable, + .resume = its_restore_enable, + }; + ++static struct syscore its_syscore = { ++ .ops = &its_syscore_ops, ++}; ++ + static void __init __iomem *its_map_one(struct resource *res, int *err) + { + void __iomem *its_base; +@@ -5868,7 +5872,7 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, + } + } + +- register_syscore_ops(&its_syscore_ops); ++ register_syscore(&its_syscore); + + return 0; + } +diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c +index 91b2f587119c..cca77f9948a3 100644 +--- a/drivers/irqchip/irq-i8259.c ++++ b/drivers/irqchip/irq-i8259.c +@@ -202,13 +202,13 @@ static void mask_and_ack_8259A(struct irq_data *d) + } + } + +-static void i8259A_resume(void) ++static void i8259A_resume(void *data) + { + if (i8259A_auto_eoi >= 0) + init_8259A(i8259A_auto_eoi); + } + +-static void i8259A_shutdown(void) ++static void i8259A_shutdown(void *data) + { + /* Put the i8259A into a quiescent state that + * the kernel initialization code can get it +@@ -220,11 +220,15 @@ static void i8259A_shutdown(void) + } + } + +-static struct syscore_ops i8259_syscore_ops = { ++static const struct syscore_ops i8259_syscore_ops = { + .resume = i8259A_resume, + .shutdown = i8259A_shutdown, + }; + ++static struct syscore i8259_syscore = { ++ .ops = &i8259_syscore_ops, ++}; ++ + static void init_8259A(int auto_eoi) + { + unsigned long flags; +@@ -320,7 +324,7 @@ struct irq_domain * __init __init_i8259_irqs(struct device_node *node) + + if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to register cascade interrupt\n"); +- register_syscore_ops(&i8259_syscore_ops); ++ register_syscore(&i8259_syscore); + return domain; + } + +diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c +index b91f5c14b405..04f7ba0657be 100644 +--- a/drivers/irqchip/irq-imx-gpcv2.c ++++ b/drivers/irqchip/irq-imx-gpcv2.c +@@ -33,7 +33,7 @@ static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i) + return cd->gpc_base + cd->cpu2wakeup + i * 4; + } + +-static int gpcv2_wakeup_source_save(void) ++static int gpcv2_wakeup_source_save(void *data) + { + struct gpcv2_irqchip_data *cd; + void __iomem *reg; +@@ -52,7 +52,7 @@ static int gpcv2_wakeup_source_save(void) + return 0; + } + +-static void gpcv2_wakeup_source_restore(void) ++static void gpcv2_wakeup_source_restore(void *data) + { + struct gpcv2_irqchip_data *cd; + int i; +@@ -65,9 +65,13 @@ static void gpcv2_wakeup_source_restore(void) + writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i)); + } + +-static struct syscore_ops imx_gpcv2_syscore_ops = { +- .suspend = gpcv2_wakeup_source_save, +- .resume = gpcv2_wakeup_source_restore, ++static const struct syscore_ops gpcv2_syscore_ops = { ++ .suspend = gpcv2_wakeup_source_save, ++ .resume = gpcv2_wakeup_source_restore, ++}; ++ ++static struct syscore gpcv2_syscore = { ++ .ops = &gpcv2_syscore_ops, + }; + + static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) +@@ -276,7 +280,7 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node, + writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup); + + imx_gpcv2_instance = cd; +- register_syscore_ops(&imx_gpcv2_syscore_ops); ++ register_syscore(&gpcv2_syscore); + + /* + * Clear the OF_POPULATED flag set in of_irq_init so that +diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c +index 39e5a72ccd3c..ad2105685b48 100644 +--- a/drivers/irqchip/irq-loongson-eiointc.c ++++ b/drivers/irqchip/irq-loongson-eiointc.c +@@ -407,21 +407,25 @@ static struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group + return NULL; + } + +-static int eiointc_suspend(void) ++static int eiointc_suspend(void *data) + { + return 0; + } + +-static void eiointc_resume(void) ++static void eiointc_resume(void *data) + { + eiointc_router_init(0); + } + +-static struct syscore_ops eiointc_syscore_ops = { ++static const struct syscore_ops eiointc_syscore_ops = { + .suspend = eiointc_suspend, + .resume = eiointc_resume, + }; + ++static struct syscore eiointc_syscore = { ++ .ops = &eiointc_syscore_ops, ++}; ++ + static int __init pch_pic_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) + { +@@ -540,7 +544,7 @@ static int __init eiointc_init(struct eiointc_priv *priv, int parent_irq, + eiointc_router_init(0); + + if (nr_pics == 1) { +- register_syscore_ops(&eiointc_syscore_ops); ++ register_syscore(&eiointc_syscore); + cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_EIOINTC_STARTING, + "irqchip/loongarch/eiointc:starting", + eiointc_router_init, NULL); +diff --git a/drivers/irqchip/irq-loongson-htpic.c b/drivers/irqchip/irq-loongson-htpic.c +index f4abdf156de7..1c691c4be989 100644 +--- a/drivers/irqchip/irq-loongson-htpic.c ++++ b/drivers/irqchip/irq-loongson-htpic.c +@@ -71,15 +71,19 @@ static void htpic_reg_init(void) + writel(0xffff, htpic->base + HTINT_EN_OFF); + } + +-static void htpic_resume(void) ++static void htpic_resume(void *data) + { + htpic_reg_init(); + } + +-struct syscore_ops htpic_syscore_ops = { ++static const struct syscore_ops htpic_syscore_ops = { + .resume = htpic_resume, + }; + ++static struct syscore htpic_syscore = { ++ .ops = &htpic_syscore_ops, ++}; ++ + static int __init htpic_of_init(struct device_node *node, struct device_node *parent) + { + unsigned int parent_irq[4]; +@@ -130,7 +134,7 @@ static int __init htpic_of_init(struct device_node *node, struct device_node *pa + htpic_irq_dispatch, htpic); + } + +- register_syscore_ops(&htpic_syscore_ops); ++ register_syscore(&htpic_syscore); + + return 0; + +diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c +index d8558eb35044..d2be8e954e92 100644 +--- a/drivers/irqchip/irq-loongson-htvec.c ++++ b/drivers/irqchip/irq-loongson-htvec.c +@@ -159,7 +159,7 @@ static void htvec_reset(struct htvec *priv) + } + } + +-static int htvec_suspend(void) ++static int htvec_suspend(void *data) + { + int i; + +@@ -169,7 +169,7 @@ static int htvec_suspend(void) + return 0; + } + +-static void htvec_resume(void) ++static void htvec_resume(void *data) + { + int i; + +@@ -177,11 +177,15 @@ static void htvec_resume(void) + writel(htvec_priv->saved_vec_en[i], htvec_priv->base + HTVEC_EN_OFF + 4 * i); + } + +-static struct syscore_ops htvec_syscore_ops = { ++static const struct syscore_ops htvec_syscore_ops = { + .suspend = htvec_suspend, + .resume = htvec_resume, + }; + ++static struct syscore htvec_syscore = { ++ .ops = &htvec_syscore_ops, ++}; ++ + static int htvec_init(phys_addr_t addr, unsigned long size, + int num_parents, int parent_irq[], struct fwnode_handle *domain_handle) + { +@@ -214,7 +218,7 @@ static int htvec_init(phys_addr_t addr, unsigned long size, + + htvec_priv = priv; + +- register_syscore_ops(&htvec_syscore_ops); ++ register_syscore(&htvec_syscore); + + return 0; + +diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c +index 912bf50a5c7c..3a125f3e4287 100644 +--- a/drivers/irqchip/irq-loongson-pch-lpc.c ++++ b/drivers/irqchip/irq-loongson-pch-lpc.c +@@ -151,7 +151,7 @@ static int pch_lpc_disabled(struct pch_lpc *priv) + (readl(priv->base + LPC_INT_STS) == 0xffffffff); + } + +-static int pch_lpc_suspend(void) ++static int pch_lpc_suspend(void *data) + { + pch_lpc_priv->saved_reg_ctl = readl(pch_lpc_priv->base + LPC_INT_CTL); + pch_lpc_priv->saved_reg_ena = readl(pch_lpc_priv->base + LPC_INT_ENA); +@@ -159,18 +159,22 @@ static int pch_lpc_suspend(void) + return 0; + } + +-static void pch_lpc_resume(void) ++static void pch_lpc_resume(void *data) + { + writel(pch_lpc_priv->saved_reg_ctl, pch_lpc_priv->base + LPC_INT_CTL); + writel(pch_lpc_priv->saved_reg_ena, pch_lpc_priv->base + LPC_INT_ENA); + writel(pch_lpc_priv->saved_reg_pol, pch_lpc_priv->base + LPC_INT_POL); + } + +-static struct syscore_ops pch_lpc_syscore_ops = { ++static const struct syscore_ops pch_lpc_syscore_ops = { + .suspend = pch_lpc_suspend, + .resume = pch_lpc_resume, + }; + ++static struct syscore pch_lpc_syscore = { ++ .ops = &pch_lpc_syscore_ops, ++}; ++ + int __init pch_lpc_acpi_init(struct irq_domain *parent, + struct acpi_madt_lpc_pic *acpi_pchlpc) + { +@@ -222,7 +226,7 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, + + pch_lpc_priv = priv; + pch_lpc_handle = irq_handle; +- register_syscore_ops(&pch_lpc_syscore_ops); ++ register_syscore(&pch_lpc_syscore); + + return 0; + +diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c +index 62e6bf3a0611..c6b369a974a7 100644 +--- a/drivers/irqchip/irq-loongson-pch-pic.c ++++ b/drivers/irqchip/irq-loongson-pch-pic.c +@@ -278,7 +278,7 @@ static void pch_pic_reset(struct pch_pic *priv) + } + } + +-static int pch_pic_suspend(void) ++static int pch_pic_suspend(void *data) + { + int i, j; + +@@ -296,7 +296,7 @@ static int pch_pic_suspend(void) + return 0; + } + +-static void pch_pic_resume(void) ++static void pch_pic_resume(void *data) + { + int i, j; + +@@ -313,11 +313,15 @@ static void pch_pic_resume(void) + } + } + +-static struct syscore_ops pch_pic_syscore_ops = { ++static const struct syscore_ops pch_pic_syscore_ops = { + .suspend = pch_pic_suspend, + .resume = pch_pic_resume, + }; + ++static struct syscore pch_pic_syscore = { ++ .ops = &pch_pic_syscore_ops, ++}; ++ + static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base, + struct irq_domain *parent_domain, struct fwnode_handle *domain_handle, + u32 gsi_base) +@@ -356,7 +360,7 @@ static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base, + pch_pic_priv[nr_pics++] = priv; + + if (nr_pics == 1) +- register_syscore_ops(&pch_pic_syscore_ops); ++ register_syscore(&pch_pic_syscore); + + return 0; + +diff --git a/drivers/irqchip/irq-mchp-eic.c b/drivers/irqchip/irq-mchp-eic.c +index 979bb86929f8..31093a8ab67c 100644 +--- a/drivers/irqchip/irq-mchp-eic.c ++++ b/drivers/irqchip/irq-mchp-eic.c +@@ -109,7 +109,7 @@ static int mchp_eic_irq_set_wake(struct irq_data *d, unsigned int on) + return 0; + } + +-static int mchp_eic_irq_suspend(void) ++static int mchp_eic_irq_suspend(void *data) + { + unsigned int hwirq; + +@@ -123,7 +123,7 @@ static int mchp_eic_irq_suspend(void) + return 0; + } + +-static void mchp_eic_irq_resume(void) ++static void mchp_eic_irq_resume(void *data) + { + unsigned int hwirq; + +@@ -135,11 +135,15 @@ static void mchp_eic_irq_resume(void) + MCHP_EIC_SCFG(hwirq)); + } + +-static struct syscore_ops mchp_eic_syscore_ops = { ++static const struct syscore_ops mchp_eic_syscore_ops = { + .suspend = mchp_eic_irq_suspend, + .resume = mchp_eic_irq_resume, + }; + ++static struct syscore mchp_eic_syscore = { ++ .ops = &mchp_eic_syscore_ops, ++}; ++ + static struct irq_chip mchp_eic_chip = { + .name = "eic", + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED, +@@ -258,7 +262,7 @@ static int mchp_eic_probe(struct platform_device *pdev, struct device_node *pare + goto clk_unprepare; + } + +- register_syscore_ops(&mchp_eic_syscore_ops); ++ register_syscore(&mchp_eic_syscore); + + pr_info("%pOF: EIC registered, nr_irqs %u\n", node, MCHP_EIC_NIRQ); + +diff --git a/drivers/irqchip/irq-mst-intc.c b/drivers/irqchip/irq-mst-intc.c +index 9643cc3a77d7..7f760f555a76 100644 +--- a/drivers/irqchip/irq-mst-intc.c ++++ b/drivers/irqchip/irq-mst-intc.c +@@ -143,7 +143,7 @@ static void mst_intc_polarity_restore(struct mst_intc_chip_data *cd) + writew_relaxed(cd->saved_polarity_conf[i], addr + i * 4); + } + +-static void mst_irq_resume(void) ++static void mst_irq_resume(void *data) + { + struct mst_intc_chip_data *cd; + +@@ -151,7 +151,7 @@ static void mst_irq_resume(void) + mst_intc_polarity_restore(cd); + } + +-static int mst_irq_suspend(void) ++static int mst_irq_suspend(void *data) + { + struct mst_intc_chip_data *cd; + +@@ -160,14 +160,18 @@ static int mst_irq_suspend(void) + return 0; + } + +-static struct syscore_ops mst_irq_syscore_ops = { ++static const struct syscore_ops mst_irq_syscore_ops = { + .suspend = mst_irq_suspend, + .resume = mst_irq_resume, + }; + ++static struct syscore mst_irq_syscore = { ++ .ops = &mst_irq_syscore_ops, ++}; ++ + static int __init mst_irq_pm_init(void) + { +- register_syscore_ops(&mst_irq_syscore_ops); ++ register_syscore(&mst_irq_syscore); + return 0; + } + late_initcall(mst_irq_pm_init); +diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c +index de481ba340f8..9571f622774e 100644 +--- a/drivers/irqchip/irq-mtk-cirq.c ++++ b/drivers/irqchip/irq-mtk-cirq.c +@@ -199,7 +199,7 @@ static const struct irq_domain_ops cirq_domain_ops = { + }; + + #ifdef CONFIG_PM_SLEEP +-static int mtk_cirq_suspend(void) ++static int mtk_cirq_suspend(void *data) + { + void __iomem *reg; + u32 value, mask; +@@ -257,7 +257,7 @@ static int mtk_cirq_suspend(void) + return 0; + } + +-static void mtk_cirq_resume(void) ++static void mtk_cirq_resume(void *data) + { + void __iomem *reg = mtk_cirq_reg(cirq_data, CIRQ_CONTROL); + u32 value; +@@ -272,14 +272,18 @@ static void mtk_cirq_resume(void) + writel_relaxed(value, reg); + } + +-static struct syscore_ops mtk_cirq_syscore_ops = { ++static const struct syscore_ops mtk_cirq_syscore_ops = { + .suspend = mtk_cirq_suspend, + .resume = mtk_cirq_resume, + }; + ++static struct syscore mtk_cirq_syscore = { ++ .ops = &mtk_cirq_syscore_ops, ++}; ++ + static void mtk_cirq_syscore_init(void) + { +- register_syscore_ops(&mtk_cirq_syscore_ops); ++ register_syscore(&mtk_cirq_syscore); + } + #else + static inline void mtk_cirq_syscore_init(void) {} +diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c +index c938ab159289..eb01d4c5aca7 100644 +--- a/drivers/irqchip/irq-renesas-rzg2l.c ++++ b/drivers/irqchip/irq-renesas-rzg2l.c +@@ -398,7 +398,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); + } + +-static int rzg2l_irqc_irq_suspend(void) ++static int rzg2l_irqc_irq_suspend(void *data) + { + struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; + void __iomem *base = rzg2l_irqc_data->base; +@@ -410,7 +410,7 @@ static int rzg2l_irqc_irq_suspend(void) + return 0; + } + +-static void rzg2l_irqc_irq_resume(void) ++static void rzg2l_irqc_irq_resume(void *data) + { + struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; + void __iomem *base = rzg2l_irqc_data->base; +@@ -425,11 +425,15 @@ static void rzg2l_irqc_irq_resume(void) + writel_relaxed(cache->iitsr, base + IITSR); + } + +-static struct syscore_ops rzg2l_irqc_syscore_ops = { ++static const struct syscore_ops rzg2l_irqc_syscore_ops = { + .suspend = rzg2l_irqc_irq_suspend, + .resume = rzg2l_irqc_irq_resume, + }; + ++static struct syscore rzg2l_irqc_syscore = { ++ .ops = &rzg2l_irqc_syscore_ops, ++}; ++ + static const struct irq_chip rzg2l_irqc_chip = { + .name = "rzg2l-irqc", + .irq_eoi = rzg2l_irqc_eoi, +@@ -577,7 +581,7 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n + return -ENOMEM; + } + +- register_syscore_ops(&rzg2l_irqc_syscore_ops); ++ register_syscore(&rzg2l_irqc_syscore); + + return 0; + } +diff --git a/drivers/irqchip/irq-sa11x0.c b/drivers/irqchip/irq-sa11x0.c +index d8d4dff16276..e5f24c5f3f41 100644 +--- a/drivers/irqchip/irq-sa11x0.c ++++ b/drivers/irqchip/irq-sa11x0.c +@@ -85,7 +85,7 @@ static struct sa1100irq_state { + unsigned int iccr; + } sa1100irq_state; + +-static int sa1100irq_suspend(void) ++static int sa1100irq_suspend(void *data) + { + struct sa1100irq_state *st = &sa1100irq_state; + +@@ -102,7 +102,7 @@ static int sa1100irq_suspend(void) + return 0; + } + +-static void sa1100irq_resume(void) ++static void sa1100irq_resume(void *data) + { + struct sa1100irq_state *st = &sa1100irq_state; + +@@ -114,14 +114,18 @@ static void sa1100irq_resume(void) + } + } + +-static struct syscore_ops sa1100irq_syscore_ops = { ++static const struct syscore_ops sa1100irq_syscore_ops = { + .suspend = sa1100irq_suspend, + .resume = sa1100irq_resume, + }; + ++static struct syscore sa1100irq_syscore = { ++ .ops = &sa1100irq_syscore_ops, ++}; ++ + static int __init sa1100irq_init_devicefs(void) + { +- register_syscore_ops(&sa1100irq_syscore_ops); ++ register_syscore(&sa1100irq_syscore); + return 0; + } + +diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c +index f255fa044764..70058871d2fb 100644 +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -268,7 +268,7 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type) + return IRQ_SET_MASK_OK; + } + +-static int plic_irq_suspend(void) ++static int plic_irq_suspend(void *data) + { + struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; + +@@ -280,7 +280,7 @@ static int plic_irq_suspend(void) + return 0; + } + +-static void plic_irq_resume(void) ++static void plic_irq_resume(void *data) + { + struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; + unsigned int index, cpu; +@@ -308,11 +308,15 @@ static void plic_irq_resume(void) + } + } + +-static struct syscore_ops plic_irq_syscore_ops = { ++static const struct syscore_ops plic_irq_syscore_ops = { + .suspend = plic_irq_suspend, + .resume = plic_irq_resume, + }; + ++static struct syscore plic_irq_syscore = { ++ .ops = &plic_irq_syscore_ops, ++}; ++ + static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) + { +@@ -782,7 +786,7 @@ static int plic_probe(struct fwnode_handle *fwnode) + cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, + "irqchip/sifive/plic:starting", + plic_starting_cpu, plic_dying_cpu); +- register_syscore_ops(&plic_irq_syscore_ops); ++ register_syscore(&plic_irq_syscore); + plic_global_setup_done = true; + } + } +diff --git a/drivers/irqchip/irq-sun6i-r.c b/drivers/irqchip/irq-sun6i-r.c +index 37d4b29763bc..23251831c06e 100644 +--- a/drivers/irqchip/irq-sun6i-r.c ++++ b/drivers/irqchip/irq-sun6i-r.c +@@ -268,7 +268,7 @@ static const struct irq_domain_ops sun6i_r_intc_domain_ops = { + .free = irq_domain_free_irqs_common, + }; + +-static int sun6i_r_intc_suspend(void) ++static int sun6i_r_intc_suspend(void *data) + { + u32 buf[BITS_TO_U32(MAX(SUN6I_NR_TOP_LEVEL_IRQS, SUN6I_NR_MUX_BITS))]; + int i; +@@ -284,7 +284,7 @@ static int sun6i_r_intc_suspend(void) + return 0; + } + +-static void sun6i_r_intc_resume(void) ++static void sun6i_r_intc_resume(void *data) + { + int i; + +@@ -294,17 +294,21 @@ static void sun6i_r_intc_resume(void) + writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i)); + } + +-static void sun6i_r_intc_shutdown(void) ++static void sun6i_r_intc_shutdown(void *data) + { +- sun6i_r_intc_suspend(); ++ sun6i_r_intc_suspend(data); + } + +-static struct syscore_ops sun6i_r_intc_syscore_ops = { ++static const struct syscore_ops sun6i_r_intc_syscore_ops = { + .suspend = sun6i_r_intc_suspend, + .resume = sun6i_r_intc_resume, + .shutdown = sun6i_r_intc_shutdown, + }; + ++static struct syscore sun6i_r_intc_syscore = { ++ .ops = &sun6i_r_intc_syscore_ops, ++}; ++ + static int __init sun6i_r_intc_init(struct device_node *node, + struct device_node *parent, + const struct sun6i_r_intc_variant *v) +@@ -346,10 +350,10 @@ static int __init sun6i_r_intc_init(struct device_node *node, + return -ENOMEM; + } + +- register_syscore_ops(&sun6i_r_intc_syscore_ops); ++ register_syscore(&sun6i_r_intc_syscore); + + sun6i_r_intc_ack_nmi(); +- sun6i_r_intc_resume(); ++ sun6i_r_intc_resume(NULL); + + return 0; + } +diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c +index 66cbb9f77ff3..b6382cf6359a 100644 +--- a/drivers/irqchip/irq-tegra.c ++++ b/drivers/irqchip/irq-tegra.c +@@ -132,7 +132,7 @@ static int tegra_set_wake(struct irq_data *d, unsigned int enable) + return 0; + } + +-static int tegra_ictlr_suspend(void) ++static int tegra_ictlr_suspend(void *data) + { + unsigned long flags; + unsigned int i; +@@ -161,7 +161,7 @@ static int tegra_ictlr_suspend(void) + return 0; + } + +-static void tegra_ictlr_resume(void) ++static void tegra_ictlr_resume(void *data) + { + unsigned long flags; + unsigned int i; +@@ -184,14 +184,18 @@ static void tegra_ictlr_resume(void) + local_irq_restore(flags); + } + +-static struct syscore_ops tegra_ictlr_syscore_ops = { ++static const struct syscore_ops tegra_ictlr_syscore_ops = { + .suspend = tegra_ictlr_suspend, + .resume = tegra_ictlr_resume, + }; + ++static struct syscore tegra_ictlr_syscore = { ++ .ops = &tegra_ictlr_syscore_ops, ++}; ++ + static void tegra_ictlr_syscore_init(void) + { +- register_syscore_ops(&tegra_ictlr_syscore_ops); ++ register_syscore(&tegra_ictlr_syscore); + } + #else + #define tegra_set_wake NULL +diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c +index 2bcdf216a000..e38104c5064e 100644 +--- a/drivers/irqchip/irq-vic.c ++++ b/drivers/irqchip/irq-vic.c +@@ -120,7 +120,7 @@ static void resume_one_vic(struct vic_device *vic) + writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); + } + +-static void vic_resume(void) ++static void vic_resume(void *data) + { + int id; + +@@ -146,7 +146,7 @@ static void suspend_one_vic(struct vic_device *vic) + writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); + } + +-static int vic_suspend(void) ++static int vic_suspend(void *data) + { + int id; + +@@ -156,11 +156,15 @@ static int vic_suspend(void) + return 0; + } + +-static struct syscore_ops vic_syscore_ops = { ++static const struct syscore_ops vic_syscore_ops = { + .suspend = vic_suspend, + .resume = vic_resume, + }; + ++static struct syscore vic_syscore = { ++ .ops = &vic_syscore_ops, ++}; ++ + /** + * vic_pm_init - initcall to register VIC pm + * +@@ -171,7 +175,7 @@ static struct syscore_ops vic_syscore_ops = { + static int __init vic_pm_init(void) + { + if (vic_id > 0) +- register_syscore_ops(&vic_syscore_ops); ++ register_syscore(&vic_syscore); + + return 0; + } +diff --git a/drivers/leds/trigger/ledtrig-cpu.c b/drivers/leds/trigger/ledtrig-cpu.c +index 05848a2fecff..679323c2ccda 100644 +--- a/drivers/leds/trigger/ledtrig-cpu.c ++++ b/drivers/leds/trigger/ledtrig-cpu.c +@@ -94,28 +94,32 @@ void ledtrig_cpu(enum cpu_led_event ledevt) + } + EXPORT_SYMBOL(ledtrig_cpu); + +-static int ledtrig_cpu_syscore_suspend(void) ++static int ledtrig_cpu_syscore_suspend(void *data) + { + ledtrig_cpu(CPU_LED_STOP); + return 0; + } + +-static void ledtrig_cpu_syscore_resume(void) ++static void ledtrig_cpu_syscore_resume(void *data) + { + ledtrig_cpu(CPU_LED_START); + } + +-static void ledtrig_cpu_syscore_shutdown(void) ++static void ledtrig_cpu_syscore_shutdown(void *data) + { + ledtrig_cpu(CPU_LED_HALTED); + } + +-static struct syscore_ops ledtrig_cpu_syscore_ops = { ++static const struct syscore_ops ledtrig_cpu_syscore_ops = { + .shutdown = ledtrig_cpu_syscore_shutdown, + .suspend = ledtrig_cpu_syscore_suspend, + .resume = ledtrig_cpu_syscore_resume, + }; + ++static struct syscore ledtrig_cpu_syscore = { ++ .ops = &ledtrig_cpu_syscore_ops, ++}; ++ + static int ledtrig_online_cpu(unsigned int cpu) + { + ledtrig_cpu(CPU_LED_START); +@@ -157,7 +161,7 @@ static int __init ledtrig_cpu_init(void) + led_trigger_register_simple(trig->name, &trig->_trig); + } + +- register_syscore_ops(&ledtrig_cpu_syscore_ops); ++ register_syscore(&ledtrig_cpu_syscore); + + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "leds/trigger:starting", + ledtrig_online_cpu, ledtrig_prepare_down_cpu); +diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c +index b0f09c70f1ff..5fe47e784d43 100644 +--- a/drivers/macintosh/via-pmu.c ++++ b/drivers/macintosh/via-pmu.c +@@ -2600,7 +2600,7 @@ void pmu_blink(int n) + #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC32) + int pmu_sys_suspended; + +-static int pmu_syscore_suspend(void) ++static int pmu_syscore_suspend(void *data) + { + /* Suspend PMU event interrupts */ + pmu_suspend(); +@@ -2614,7 +2614,7 @@ static int pmu_syscore_suspend(void) + return 0; + } + +-static void pmu_syscore_resume(void) ++static void pmu_syscore_resume(void *data) + { + struct adb_request req; + +@@ -2634,14 +2634,18 @@ static void pmu_syscore_resume(void) + pmu_sys_suspended = 0; + } + +-static struct syscore_ops pmu_syscore_ops = { ++static const struct syscore_ops pmu_syscore_ops = { + .suspend = pmu_syscore_suspend, + .resume = pmu_syscore_resume, + }; + ++static struct syscore pmu_syscore = { ++ .ops = &pmu_syscore_ops, ++}; ++ + static int pmu_syscore_register(void) + { +- register_syscore_ops(&pmu_syscore_ops); ++ register_syscore(&pmu_syscore); + + return 0; + } +diff --git a/drivers/power/reset/sc27xx-poweroff.c b/drivers/power/reset/sc27xx-poweroff.c +index 90287c31992c..393bd1c33b73 100644 +--- a/drivers/power/reset/sc27xx-poweroff.c ++++ b/drivers/power/reset/sc27xx-poweroff.c +@@ -28,7 +28,7 @@ static struct regmap *regmap; + * taking cpus down to avoid racing regmap or spi mutex lock when poweroff + * system through PMIC. + */ +-static void sc27xx_poweroff_shutdown(void) ++static void sc27xx_poweroff_shutdown(void *data) + { + #ifdef CONFIG_HOTPLUG_CPU + int cpu; +@@ -40,10 +40,14 @@ static void sc27xx_poweroff_shutdown(void) + #endif + } + +-static struct syscore_ops poweroff_syscore_ops = { ++static const struct syscore_ops poweroff_syscore_ops = { + .shutdown = sc27xx_poweroff_shutdown, + }; + ++static struct syscore poweroff_syscore = { ++ .ops = &poweroff_syscore_ops, ++}; ++ + static void sc27xx_poweroff_do_poweroff(void) + { + /* Disable the external subsys connection's power firstly */ +@@ -62,7 +66,7 @@ static int sc27xx_poweroff_probe(struct platform_device *pdev) + return -ENODEV; + + pm_power_off = sc27xx_poweroff_do_poweroff; +- register_syscore_ops(&poweroff_syscore_ops); ++ register_syscore(&poweroff_syscore); + return 0; + } + +diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c +index 7a73f5e4a1fc..f02e12dfa5f6 100644 +--- a/drivers/sh/clk/core.c ++++ b/drivers/sh/clk/core.c +@@ -569,7 +569,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) + EXPORT_SYMBOL_GPL(clk_round_rate); + + #ifdef CONFIG_PM +-static void clks_core_resume(void) ++static void clks_core_resume(void *data) + { + struct clk *clkp; + +@@ -588,13 +588,17 @@ static void clks_core_resume(void) + } + } + +-static struct syscore_ops clks_syscore_ops = { ++static const struct syscore_ops clks_syscore_ops = { + .resume = clks_core_resume, + }; + ++static struct syscore clks_syscore = { ++ .ops = &clks_syscore_ops, ++}; ++ + static int __init clk_syscore_init(void) + { +- register_syscore_ops(&clks_syscore_ops); ++ register_syscore(&clks_syscore); + + return 0; + } +diff --git a/drivers/sh/intc/core.c b/drivers/sh/intc/core.c +index ea571eeb3078..3dde703b7766 100644 +--- a/drivers/sh/intc/core.c ++++ b/drivers/sh/intc/core.c +@@ -394,7 +394,7 @@ int __init register_intc_controller(struct intc_desc *desc) + return -ENOMEM; + } + +-static int intc_suspend(void) ++static int intc_suspend(void *data) + { + struct intc_desc_int *d; + +@@ -420,7 +420,7 @@ static int intc_suspend(void) + return 0; + } + +-static void intc_resume(void) ++static void intc_resume(void *data) + { + struct intc_desc_int *d; + +@@ -450,11 +450,15 @@ static void intc_resume(void) + } + } + +-struct syscore_ops intc_syscore_ops = { ++static const struct syscore_ops intc_syscore_ops = { + .suspend = intc_suspend, + .resume = intc_resume, + }; + ++static struct syscore intc_syscore = { ++ .ops = &intc_syscore_ops, ++}; ++ + const struct bus_type intc_subsys = { + .name = "intc", + .dev_name = "intc", +@@ -477,7 +481,7 @@ static int __init register_intc_devs(void) + struct intc_desc_int *d; + int error; + +- register_syscore_ops(&intc_syscore_ops); ++ register_syscore(&intc_syscore); + + error = subsys_system_register(&intc_subsys, NULL); + if (!error) { +diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c +index 364ddbe365c2..bd830649b60d 100644 +--- a/drivers/soc/bcm/brcmstb/biuctrl.c ++++ b/drivers/soc/bcm/brcmstb/biuctrl.c +@@ -298,7 +298,7 @@ static int __init setup_hifcpubiuctrl_regs(struct device_node *np) + #ifdef CONFIG_PM_SLEEP + static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS]; + +-static int brcmstb_cpu_credit_reg_suspend(void) ++static int brcmstb_cpu_credit_reg_suspend(void *data) + { + unsigned int i; + +@@ -311,7 +311,7 @@ static int brcmstb_cpu_credit_reg_suspend(void) + return 0; + } + +-static void brcmstb_cpu_credit_reg_resume(void) ++static void brcmstb_cpu_credit_reg_resume(void *data) + { + unsigned int i; + +@@ -322,10 +322,14 @@ static void brcmstb_cpu_credit_reg_resume(void) + cbc_writel(cpubiuctrl_reg_save[i], i); + } + +-static struct syscore_ops brcmstb_cpu_credit_syscore_ops = { ++static const struct syscore_ops brcmstb_cpu_credit_syscore_ops = { + .suspend = brcmstb_cpu_credit_reg_suspend, + .resume = brcmstb_cpu_credit_reg_resume, + }; ++ ++static struct syscore brcmstb_cpu_credit_syscore = { ++ .ops = &brcmstb_cpu_credit_syscore_ops, ++}; + #endif + + +@@ -354,7 +358,7 @@ static int __init brcmstb_biuctrl_init(void) + a72_b53_rac_enable_all(np); + mcp_a72_b53_set(); + #ifdef CONFIG_PM_SLEEP +- register_syscore_ops(&brcmstb_cpu_credit_syscore_ops); ++ register_syscore(&brcmstb_cpu_credit_syscore); + #endif + ret = 0; + out_put: +diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c +index 034a2a535a1e..93bbebd68001 100644 +--- a/drivers/soc/tegra/pmc.c ++++ b/drivers/soc/tegra/pmc.c +@@ -466,7 +466,7 @@ struct tegra_pmc { + unsigned long *wake_type_dual_edge_map; + unsigned long *wake_sw_status_map; + unsigned long *wake_cntrl_level_map; +- struct syscore_ops syscore; ++ struct syscore syscore; + }; + + static struct tegra_pmc *pmc = &(struct tegra_pmc) { +@@ -3147,7 +3147,7 @@ static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int + } + } + +-static void tegra186_pmc_wake_syscore_resume(void) ++static void tegra186_pmc_wake_syscore_resume(void *data) + { + u32 status, mask; + unsigned int i; +@@ -3160,7 +3160,7 @@ static void tegra186_pmc_wake_syscore_resume(void) + } + } + +-static int tegra186_pmc_wake_syscore_suspend(void) ++static int tegra186_pmc_wake_syscore_suspend(void *data) + { + wke_read_sw_wake_status(pmc); + +@@ -3179,6 +3179,11 @@ static int tegra186_pmc_wake_syscore_suspend(void) + return 0; + } + ++static const struct syscore_ops tegra186_pmc_wake_syscore_ops = { ++ .suspend = tegra186_pmc_wake_syscore_suspend, ++ .resume = tegra186_pmc_wake_syscore_resume, ++}; ++ + #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) + static int tegra_pmc_suspend(struct device *dev) + { +@@ -3829,10 +3834,8 @@ static const struct tegra_pmc_regs tegra186_pmc_regs = { + + static void tegra186_pmc_init(struct tegra_pmc *pmc) + { +- pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; +- pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; +- +- register_syscore_ops(&pmc->syscore); ++ pmc->syscore.ops = &tegra186_pmc_wake_syscore_ops; ++ register_syscore(&pmc->syscore); + } + + static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, +diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c +index bd2fca7dc017..8a2f441cd2ec 100644 +--- a/drivers/thermal/intel/intel_hfi.c ++++ b/drivers/thermal/intel/intel_hfi.c +@@ -592,7 +592,7 @@ static void hfi_disable_instance(void *ptr) + hfi_disable(); + } + +-static void hfi_syscore_resume(void) ++static void hfi_syscore_resume(void *data) + { + /* This code runs only on the boot CPU. */ + struct hfi_cpu_info *info = &per_cpu(hfi_cpu_info, 0); +@@ -603,7 +603,7 @@ static void hfi_syscore_resume(void) + hfi_enable_instance(hfi_instance); + } + +-static int hfi_syscore_suspend(void) ++static int hfi_syscore_suspend(void *data) + { + /* No locking needed. There is no concurrency with CPU offline. */ + hfi_disable(); +@@ -611,11 +611,15 @@ static int hfi_syscore_suspend(void) + return 0; + } + +-static struct syscore_ops hfi_pm_ops = { ++static const struct syscore_ops hfi_pm_ops = { + .resume = hfi_syscore_resume, + .suspend = hfi_syscore_suspend, + }; + ++static struct syscore hfi_pm = { ++ .ops = &hfi_pm_ops, ++}; ++ + static int hfi_thermal_notify(struct notifier_block *nb, unsigned long state, + void *_notify) + { +@@ -710,7 +714,7 @@ void __init intel_hfi_init(void) + if (thermal_genl_register_notifier(&hfi_thermal_nb)) + goto err_nl_notif; + +- register_syscore_ops(&hfi_pm_ops); ++ register_syscore(&hfi_pm); + + return; + +diff --git a/drivers/xen/xen-acpi-processor.c b/drivers/xen/xen-acpi-processor.c +index 520756159d3d..8d1860bd5d57 100644 +--- a/drivers/xen/xen-acpi-processor.c ++++ b/drivers/xen/xen-acpi-processor.c +@@ -492,7 +492,7 @@ static void xen_acpi_processor_resume_worker(struct work_struct *dummy) + pr_info("ACPI data upload failed, error = %d\n", rc); + } + +-static void xen_acpi_processor_resume(void) ++static void xen_acpi_processor_resume(void *data) + { + static DECLARE_WORK(wq, xen_acpi_processor_resume_worker); + +@@ -506,10 +506,14 @@ static void xen_acpi_processor_resume(void) + schedule_work(&wq); + } + +-static struct syscore_ops xap_syscore_ops = { ++static const struct syscore_ops xap_syscore_ops = { + .resume = xen_acpi_processor_resume, + }; + ++static struct syscore xap_syscore = { ++ .ops = &xap_syscore_ops, ++}; ++ + static int __init xen_acpi_processor_init(void) + { + int i; +@@ -560,7 +564,7 @@ static int __init xen_acpi_processor_init(void) + if (rc) + goto err_unregister; + +- register_syscore_ops(&xap_syscore_ops); ++ register_syscore(&xap_syscore); + + return 0; + err_unregister: +@@ -577,7 +581,7 @@ static void __exit xen_acpi_processor_exit(void) + { + int i; + +- unregister_syscore_ops(&xap_syscore_ops); ++ unregister_syscore(&xap_syscore); + bitmap_free(acpi_ids_done); + bitmap_free(acpi_id_present); + bitmap_free(acpi_id_cst_present); +diff --git a/include/linux/syscore_ops.h b/include/linux/syscore_ops.h +index ae4d48e4c970..ac6d71be5c38 100644 +--- a/include/linux/syscore_ops.h ++++ b/include/linux/syscore_ops.h +@@ -11,14 +11,19 @@ + #include + + struct syscore_ops { ++ int (*suspend)(void *data); ++ void (*resume)(void *data); ++ void (*shutdown)(void *data); ++}; ++ ++struct syscore { + struct list_head node; +- int (*suspend)(void); +- void (*resume)(void); +- void (*shutdown)(void); ++ const struct syscore_ops *ops; ++ void *data; + }; + +-extern void register_syscore_ops(struct syscore_ops *ops); +-extern void unregister_syscore_ops(struct syscore_ops *ops); ++extern void register_syscore(struct syscore *syscore); ++extern void unregister_syscore(struct syscore *syscore); + #ifdef CONFIG_PM_SLEEP + extern int syscore_suspend(void); + extern void syscore_resume(void); +diff --git a/kernel/cpu_pm.c b/kernel/cpu_pm.c +index b0f0d15085db..7481fbb947d3 100644 +--- a/kernel/cpu_pm.c ++++ b/kernel/cpu_pm.c +@@ -173,7 +173,7 @@ int cpu_cluster_pm_exit(void) + EXPORT_SYMBOL_GPL(cpu_cluster_pm_exit); + + #ifdef CONFIG_PM +-static int cpu_pm_suspend(void) ++static int cpu_pm_suspend(void *data) + { + int ret; + +@@ -185,20 +185,24 @@ static int cpu_pm_suspend(void) + return ret; + } + +-static void cpu_pm_resume(void) ++static void cpu_pm_resume(void *data) + { + cpu_cluster_pm_exit(); + cpu_pm_exit(); + } + +-static struct syscore_ops cpu_pm_syscore_ops = { ++static const struct syscore_ops cpu_pm_syscore_ops = { + .suspend = cpu_pm_suspend, + .resume = cpu_pm_resume, + }; + ++static struct syscore cpu_pm_syscore = { ++ .ops = &cpu_pm_syscore_ops, ++}; ++ + static int cpu_pm_init(void) + { +- register_syscore_ops(&cpu_pm_syscore_ops); ++ register_syscore(&cpu_pm_syscore); + return 0; + } + core_initcall(cpu_pm_init); +diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c +index bf59e37d650a..3cd0c40282c0 100644 +--- a/kernel/irq/generic-chip.c ++++ b/kernel/irq/generic-chip.c +@@ -650,7 +650,7 @@ static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc) + } + + #ifdef CONFIG_PM +-static int irq_gc_suspend(void) ++static int irq_gc_suspend(void *data) + { + struct irq_chip_generic *gc; + +@@ -670,7 +670,7 @@ static int irq_gc_suspend(void) + return 0; + } + +-static void irq_gc_resume(void) ++static void irq_gc_resume(void *data) + { + struct irq_chip_generic *gc; + +@@ -693,7 +693,7 @@ static void irq_gc_resume(void) + #define irq_gc_resume NULL + #endif + +-static void irq_gc_shutdown(void) ++static void irq_gc_shutdown(void *data) + { + struct irq_chip_generic *gc; + +@@ -709,15 +709,19 @@ static void irq_gc_shutdown(void) + } + } + +-static struct syscore_ops irq_gc_syscore_ops = { ++static const struct syscore_ops irq_gc_syscore_ops = { + .suspend = irq_gc_suspend, + .resume = irq_gc_resume, + .shutdown = irq_gc_shutdown, + }; + ++static struct syscore irq_gc_syscore = { ++ .ops = &irq_gc_syscore_ops, ++}; ++ + static int __init irq_gc_init_ops(void) + { +- register_syscore_ops(&irq_gc_syscore_ops); ++ register_syscore(&irq_gc_syscore); + return 0; + } + device_initcall(irq_gc_init_ops); +diff --git a/kernel/irq/pm.c b/kernel/irq/pm.c +index f7394729cedc..99ff65466d87 100644 +--- a/kernel/irq/pm.c ++++ b/kernel/irq/pm.c +@@ -211,21 +211,26 @@ void rearm_wake_irq(unsigned int irq) + + /** + * irq_pm_syscore_resume - enable interrupt lines early ++ * @data: syscore context + * + * Enable all interrupt lines with %IRQF_EARLY_RESUME set. + */ +-static void irq_pm_syscore_resume(void) ++static void irq_pm_syscore_resume(void *data) + { + resume_irqs(true); + } + +-static struct syscore_ops irq_pm_syscore_ops = { ++static const struct syscore_ops irq_pm_syscore_ops = { + .resume = irq_pm_syscore_resume, + }; + ++static struct syscore irq_pm_syscore = { ++ .ops = &irq_pm_syscore_ops, ++}; ++ + static int __init irq_pm_init_ops(void) + { +- register_syscore_ops(&irq_pm_syscore_ops); ++ register_syscore(&irq_pm_syscore); + return 0; + } + +diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c +index c27fc7fc64eb..70a97290ad90 100644 +--- a/kernel/printk/printk.c ++++ b/kernel/printk/printk.c +@@ -3660,12 +3660,13 @@ static bool legacy_kthread_create(void) + + /** + * printk_kthreads_shutdown - shutdown all threaded printers ++ * @data: syscore context + * + * On system shutdown all threaded printers are stopped. This allows printk + * to transition back to atomic printing, thus providing a robust mechanism + * for the final shutdown/reboot messages to be output. + */ +-static void printk_kthreads_shutdown(void) ++static void printk_kthreads_shutdown(void *data) + { + struct console *con; + +@@ -3687,10 +3688,14 @@ static void printk_kthreads_shutdown(void) + console_list_unlock(); + } + +-static struct syscore_ops printk_syscore_ops = { ++static const struct syscore_ops printk_syscore_ops = { + .shutdown = printk_kthreads_shutdown, + }; + ++static struct syscore printk_syscore = { ++ .ops = &printk_syscore_ops, ++}; ++ + /* + * If appropriate, start nbcon kthreads and set @printk_kthreads_running. + * If any kthreads fail to start, those consoles are unregistered. +@@ -3758,7 +3763,7 @@ static void printk_kthreads_check_locked(void) + + static int __init printk_set_kthreads_ready(void) + { +- register_syscore_ops(&printk_syscore_ops); ++ register_syscore(&printk_syscore); + + console_list_lock(); + printk_kthreads_ready = true; +diff --git a/kernel/time/sched_clock.c b/kernel/time/sched_clock.c +index 425d429906d0..f3aaef695b8c 100644 +--- a/kernel/time/sched_clock.c ++++ b/kernel/time/sched_clock.c +@@ -296,6 +296,11 @@ int sched_clock_suspend(void) + return 0; + } + ++static int sched_clock_syscore_suspend(void *data) ++{ ++ return sched_clock_suspend(); ++} ++ + void sched_clock_resume(void) + { + struct clock_read_data *rd = &cd.read_data[0]; +@@ -305,14 +310,23 @@ void sched_clock_resume(void) + rd->read_sched_clock = cd.actual_read_sched_clock; + } + +-static struct syscore_ops sched_clock_ops = { +- .suspend = sched_clock_suspend, +- .resume = sched_clock_resume, ++static void sched_clock_syscore_resume(void *data) ++{ ++ sched_clock_resume(); ++} ++ ++static const struct syscore_ops sched_clock_syscore_ops = { ++ .suspend = sched_clock_syscore_suspend, ++ .resume = sched_clock_syscore_resume, ++}; ++ ++static struct syscore sched_clock_syscore = { ++ .ops = &sched_clock_syscore_ops, + }; + + static int __init sched_clock_syscore_init(void) + { +- register_syscore_ops(&sched_clock_ops); ++ register_syscore(&sched_clock_syscore); + + return 0; + } +diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c +index c7dcccc5f3d6..c07e562ee4c1 100644 +--- a/kernel/time/timekeeping.c ++++ b/kernel/time/timekeeping.c +@@ -1994,6 +1994,11 @@ void timekeeping_resume(void) + timerfd_resume(); + } + ++static void timekeeping_syscore_resume(void *data) ++{ ++ timekeeping_resume(); ++} ++ + int timekeeping_suspend(void) + { + struct timekeeper *tks = &tk_core.shadow_timekeeper; +@@ -2061,15 +2066,24 @@ int timekeeping_suspend(void) + return 0; + } + ++static int timekeeping_syscore_suspend(void *data) ++{ ++ return timekeeping_suspend(); ++} ++ + /* sysfs resume/suspend bits for timekeeping */ +-static struct syscore_ops timekeeping_syscore_ops = { +- .resume = timekeeping_resume, +- .suspend = timekeeping_suspend, ++static const struct syscore_ops timekeeping_syscore_ops = { ++ .resume = timekeeping_syscore_resume, ++ .suspend = timekeeping_syscore_suspend, ++}; ++ ++static struct syscore timekeeping_syscore = { ++ .ops = &timekeeping_syscore_ops, + }; + + static int __init timekeeping_init_ops(void) + { +- register_syscore_ops(&timekeeping_syscore_ops); ++ register_syscore(&timekeeping_syscore); + return 0; + } + device_initcall(timekeeping_init_ops); +diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c +index 46581554abfb..3ec22d034e73 100644 +--- a/virt/kvm/kvm_main.c ++++ b/virt/kvm/kvm_main.c +@@ -5629,7 +5629,7 @@ static int kvm_offline_cpu(unsigned int cpu) + return 0; + } + +-static void kvm_shutdown(void) ++static void kvm_shutdown(void *data) + { + /* + * Disable hardware virtualization and set kvm_rebooting to indicate +@@ -5647,7 +5647,7 @@ static void kvm_shutdown(void) + on_each_cpu(kvm_disable_virtualization_cpu, NULL, 1); + } + +-static int kvm_suspend(void) ++static int kvm_suspend(void *data) + { + /* + * Secondary CPUs and CPU hotplug are disabled across the suspend/resume +@@ -5664,7 +5664,7 @@ static int kvm_suspend(void) + return 0; + } + +-static void kvm_resume(void) ++static void kvm_resume(void *data) + { + lockdep_assert_not_held(&kvm_usage_lock); + lockdep_assert_irqs_disabled(); +@@ -5672,12 +5672,16 @@ static void kvm_resume(void) + WARN_ON_ONCE(kvm_enable_virtualization_cpu()); + } + +-static struct syscore_ops kvm_syscore_ops = { ++static const struct syscore_ops kvm_syscore_ops = { + .suspend = kvm_suspend, + .resume = kvm_resume, + .shutdown = kvm_shutdown, + }; + ++static struct syscore kvm_syscore = { ++ .ops = &kvm_syscore_ops, ++}; ++ + int kvm_enable_virtualization(void) + { + int r; +@@ -5694,7 +5698,7 @@ int kvm_enable_virtualization(void) + if (r) + goto err_cpuhp; + +- register_syscore_ops(&kvm_syscore_ops); ++ register_syscore(&kvm_syscore); + + /* + * Undo virtualization enabling and bail if the system is going down. +@@ -5716,7 +5720,7 @@ int kvm_enable_virtualization(void) + return 0; + + err_rebooting: +- unregister_syscore_ops(&kvm_syscore_ops); ++ unregister_syscore(&kvm_syscore); + cpuhp_remove_state(CPUHP_AP_KVM_ONLINE); + err_cpuhp: + kvm_arch_disable_virtualization(); +@@ -5732,7 +5736,7 @@ void kvm_disable_virtualization(void) + if (--kvm_usage_count) + return; + +- unregister_syscore_ops(&kvm_syscore_ops); ++ unregister_syscore(&kvm_syscore); + cpuhp_remove_state(CPUHP_AP_KVM_ONLINE); + kvm_arch_disable_virtualization(); + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch b/SPECS/linux-lts-kmhv2/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch new file mode 100644 index 0000000000..778297758c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch @@ -0,0 +1,325 @@ +From dc079d2d3ef26e7fc9ba38e7af9c67873ed5fc55 Mon Sep 17 00:00:00 2001 +From: Nick Hu +Date: Tue, 2 Dec 2025 14:07:41 +0800 +Subject: [RUYI PATCH] UPSTREAM: irqchip/riscv-aplic: Preserve APLIC states + across suspend/resume + +The APLIC states might be reset when the platform enters a low power +state, but the register states are not being preserved and restored, +which prevents interrupt delivery after the platform resumes. +Solve this by adding a syscore ops and a power management notifier to +preserve and restore the APLIC states on suspend and resume. + +[ tglx: Folded the build fix provided by Geert ] + +Signed-off-by: Nick Hu +Signed-off-by: Thomas Gleixner +Reviewed-by: Yong-Xuan Wang +Reviewed-by: Cyan Yang +Reviewed-by: Nutty Liu +Reviewed-by: Anup Patel +Link: https://patch.msgid.link/20251202-preserve-aplic-imsic-v3-2-1844fbf1fe92@sifive.com +(cherry picked from commit 95a8ddde36601d0a645475fb080ed118db59c8c3) +Signed-off-by: Han Gao +--- + drivers/irqchip/irq-riscv-aplic-direct.c | 10 ++ + drivers/irqchip/irq-riscv-aplic-main.c | 170 ++++++++++++++++++++++- + drivers/irqchip/irq-riscv-aplic-main.h | 19 +++ + 3 files changed, 198 insertions(+), 1 deletion(-) + +diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c +index c2a75bf3d20c..5a9650225dd8 100644 +--- a/drivers/irqchip/irq-riscv-aplic-direct.c ++++ b/drivers/irqchip/irq-riscv-aplic-direct.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -171,6 +172,15 @@ static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en) + writel(de, idc->regs + APLIC_IDC_IDELIVERY); + } + ++void aplic_direct_restore_states(struct aplic_priv *priv) ++{ ++ struct aplic_direct *direct = container_of(priv, struct aplic_direct, priv); ++ int cpu; ++ ++ for_each_cpu(cpu, &direct->lmask) ++ aplic_idc_set_delivery(per_cpu_ptr(&aplic_idcs, cpu), true); ++} ++ + static int aplic_direct_dying_cpu(unsigned int cpu) + { + if (aplic_direct_parent_irq) +diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c +index 93e7c51f944a..4495ca26abf5 100644 +--- a/drivers/irqchip/irq-riscv-aplic-main.c ++++ b/drivers/irqchip/irq-riscv-aplic-main.c +@@ -12,10 +12,169 @@ + #include + #include + #include ++#include ++#include + #include ++#include + + #include "irq-riscv-aplic-main.h" + ++static LIST_HEAD(aplics); ++ ++static void aplic_restore_states(struct aplic_priv *priv) ++{ ++ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs; ++ struct aplic_src_ctrl *srcs; ++ void __iomem *regs; ++ u32 nr_irqs, i; ++ ++ regs = priv->regs; ++ writel(saved_regs->domaincfg, regs + APLIC_DOMAINCFG); ++#ifdef CONFIG_RISCV_M_MODE ++ writel(saved_regs->msiaddr, regs + APLIC_xMSICFGADDR); ++ writel(saved_regs->msiaddrh, regs + APLIC_xMSICFGADDRH); ++#endif ++ /* ++ * The sourcecfg[i] has to be restored prior to the target[i], interrupt-pending and ++ * interrupt-enable bits. The AIA specification states that "Whenever interrupt source i is ++ * inactive in an interrupt domain, the corresponding interrupt-pending and interrupt-enable ++ * bits within the domain are read-only zeros, and register target[i] is also read-only ++ * zero." ++ */ ++ nr_irqs = priv->nr_irqs; ++ for (i = 0; i < nr_irqs; i++) { ++ srcs = &priv->saved_hw_regs.srcs[i]; ++ writel(srcs->sourcecfg, regs + APLIC_SOURCECFG_BASE + i * sizeof(u32)); ++ writel(srcs->target, regs + APLIC_TARGET_BASE + i * sizeof(u32)); ++ } ++ ++ for (i = 0; i <= nr_irqs; i += 32) { ++ srcs = &priv->saved_hw_regs.srcs[i]; ++ writel(-1U, regs + APLIC_CLRIE_BASE + (i / 32) * sizeof(u32)); ++ writel(srcs->ie, regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32)); ++ ++ /* Re-trigger the interrupts if it forwards interrupts to target harts by MSIs */ ++ if (!priv->nr_idcs) ++ writel(readl(regs + APLIC_CLRIP_BASE + (i / 32) * sizeof(u32)), ++ regs + APLIC_SETIP_BASE + (i / 32) * sizeof(u32)); ++ } ++ ++ if (priv->nr_idcs) ++ aplic_direct_restore_states(priv); ++} ++ ++static void aplic_save_states(struct aplic_priv *priv) ++{ ++ struct aplic_src_ctrl *srcs; ++ void __iomem *regs; ++ u32 i, nr_irqs; ++ ++ regs = priv->regs; ++ nr_irqs = priv->nr_irqs; ++ /* The valid interrupt source IDs range from 1 to N, where N is priv->nr_irqs */ ++ for (i = 0; i < nr_irqs; i++) { ++ srcs = &priv->saved_hw_regs.srcs[i]; ++ srcs->target = readl(regs + APLIC_TARGET_BASE + i * sizeof(u32)); ++ ++ if (i % 32) ++ continue; ++ ++ srcs->ie = readl(regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32)); ++ } ++ ++ /* Save the nr_irqs bit if needed */ ++ if (!(nr_irqs % 32)) { ++ srcs = &priv->saved_hw_regs.srcs[nr_irqs]; ++ srcs->ie = readl(regs + APLIC_SETIE_BASE + (nr_irqs / 32) * sizeof(u32)); ++ } ++} ++ ++static int aplic_syscore_suspend(void *data) ++{ ++ struct aplic_priv *priv; ++ ++ list_for_each_entry(priv, &aplics, head) ++ aplic_save_states(priv); ++ ++ return 0; ++} ++ ++static void aplic_syscore_resume(void *data) ++{ ++ struct aplic_priv *priv; ++ ++ list_for_each_entry(priv, &aplics, head) ++ aplic_restore_states(priv); ++} ++ ++static struct syscore_ops aplic_syscore_ops = { ++ .suspend = aplic_syscore_suspend, ++ .resume = aplic_syscore_resume, ++}; ++ ++static struct syscore aplic_syscore = { ++ .ops = &aplic_syscore_ops, ++}; ++ ++static int aplic_pm_notifier(struct notifier_block *nb, unsigned long action, void *data) ++{ ++ struct aplic_priv *priv = container_of(nb, struct aplic_priv, genpd_nb); ++ ++ switch (action) { ++ case GENPD_NOTIFY_PRE_OFF: ++ aplic_save_states(priv); ++ break; ++ case GENPD_NOTIFY_ON: ++ aplic_restore_states(priv); ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static void aplic_pm_remove(void *data) ++{ ++ struct aplic_priv *priv = data; ++ struct device *dev = priv->dev; ++ ++ list_del(&priv->head); ++ if (dev->pm_domain) ++ dev_pm_genpd_remove_notifier(dev); ++} ++ ++static int aplic_pm_add(struct device *dev, struct aplic_priv *priv) ++{ ++ struct aplic_src_ctrl *srcs; ++ int ret; ++ ++ srcs = devm_kzalloc(dev, (priv->nr_irqs + 1) * sizeof(*srcs), GFP_KERNEL); ++ if (!srcs) ++ return -ENOMEM; ++ ++ priv->saved_hw_regs.srcs = srcs; ++ list_add(&priv->head, &aplics); ++ if (dev->pm_domain) { ++ priv->genpd_nb.notifier_call = aplic_pm_notifier; ++ ret = dev_pm_genpd_add_notifier(dev, &priv->genpd_nb); ++ if (ret) ++ goto remove_head; ++ ++ ret = devm_pm_runtime_enable(dev); ++ if (ret) ++ goto remove_notifier; ++ } ++ ++ return devm_add_action_or_reset(dev, aplic_pm_remove, priv); ++ ++remove_notifier: ++ dev_pm_genpd_remove_notifier(dev); ++remove_head: ++ list_del(&priv->head); ++ return ret; ++} ++ + void aplic_irq_unmask(struct irq_data *d) + { + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); +@@ -60,6 +219,8 @@ int aplic_irq_set_type(struct irq_data *d, unsigned int type) + sourcecfg += (d->hwirq - 1) * sizeof(u32); + writel(val, sourcecfg); + ++ priv->saved_hw_regs.srcs[d->hwirq - 1].sourcecfg = val; ++ + return 0; + } + +@@ -82,6 +243,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, + + void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) + { ++ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs; + u32 val; + #ifdef CONFIG_RISCV_M_MODE + u32 valh; +@@ -95,6 +257,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) + valh |= FIELD_PREP(APLIC_xMSICFGADDRH_HHXS, priv->msicfg.hhxs); + writel(val, priv->regs + APLIC_xMSICFGADDR); + writel(valh, priv->regs + APLIC_xMSICFGADDRH); ++ saved_regs->msiaddr = val; ++ saved_regs->msiaddrh = valh; + } + #endif + +@@ -106,6 +270,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) + writel(val, priv->regs + APLIC_DOMAINCFG); + if (readl(priv->regs + APLIC_DOMAINCFG) != val) + dev_warn(priv->dev, "unable to write 0x%x in domaincfg\n", val); ++ ++ saved_regs->domaincfg = val; + } + + static void aplic_init_hw_irqs(struct aplic_priv *priv) +@@ -176,7 +342,7 @@ int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem * + /* Setup initial state APLIC interrupts */ + aplic_init_hw_irqs(priv); + +- return 0; ++ return aplic_pm_add(dev, priv); + } + + static int aplic_probe(struct platform_device *pdev) +@@ -209,6 +375,8 @@ static int aplic_probe(struct platform_device *pdev) + if (rc) + dev_err_probe(dev, rc, "failed to setup APLIC in %s mode\n", + msi_mode ? "MSI" : "direct"); ++ else ++ register_syscore(&aplic_syscore); + + #ifdef CONFIG_ACPI + if (!acpi_disabled) +diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-riscv-aplic-main.h +index b0ad8cde69b1..2d8ad7138541 100644 +--- a/drivers/irqchip/irq-riscv-aplic-main.h ++++ b/drivers/irqchip/irq-riscv-aplic-main.h +@@ -23,7 +23,25 @@ struct aplic_msicfg { + u32 lhxw; + }; + ++struct aplic_src_ctrl { ++ u32 sourcecfg; ++ u32 target; ++ u32 ie; ++}; ++ ++struct aplic_saved_regs { ++ u32 domaincfg; ++#ifdef CONFIG_RISCV_M_MODE ++ u32 msiaddr; ++ u32 msiaddrh; ++#endif ++ struct aplic_src_ctrl *srcs; ++}; ++ + struct aplic_priv { ++ struct list_head head; ++ struct notifier_block genpd_nb; ++ struct aplic_saved_regs saved_hw_regs; + struct device *dev; + u32 gsi_base; + u32 nr_irqs; +@@ -40,6 +58,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, + unsigned long *hwirq, unsigned int *type); + void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode); + int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *regs); ++void aplic_direct_restore_states(struct aplic_priv *priv); + int aplic_direct_setup(struct device *dev, void __iomem *regs); + #ifdef CONFIG_RISCV_APLIC_MSI + int aplic_msi_setup(struct device *dev, void __iomem *regs); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0161-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch b/SPECS/linux-lts-kmhv2/0161-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch deleted file mode 100644 index f7ae99a862..0000000000 --- a/SPECS/linux-lts-kmhv2/0161-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch +++ /dev/null @@ -1,59 +0,0 @@ -From d55d880c109f6894dbe383af6cca3b65ebab1537 Mon Sep 17 00:00:00 2001 -From: Nilay Shroff -Date: Fri, 20 Feb 2026 12:32:27 +0530 -Subject: [PATCH 161/467] UPSTREAM: powerpc/pci: Initialize msi_addr_mask for - OF-created PCI devices - -Recent changes replaced the use of no_64bit_msi with msi_addr_mask. As a -result, msi_addr_mask is now expected to be initialized to DMA_BIT_MASK(64) -when a pci_dev is set up. However, this initialization was missed on -powerpc due to differences in the device initialization path compared to -other (x86) architecture. Due to this, now PCI device probe method fails on -powerpc system. - -On powerpc systems, struct pci_dev instances are created from device tree -nodes via of_create_pci_dev(). Because msi_addr_mask was not initialized -there, it remained zero. Later, during MSI setup, msi_verify_entries() -validates the programmed MSI address against pdev->msi_addr_mask. Since the -mask was not set correctly, the validation fails, causing PCI driver probe -failures for devices on powerpc systems. - -Initialize pdev->msi_addr_mask to DMA_BIT_MASK(64) in of_create_pci_dev() -so that MSI address validation succeeds and device probe works as expected. - -Fixes: 386ced19e9a3 ("PCI/MSI: Convert the boolean no_64bit_msi flag to a DMA address mask") -Signed-off-by: Nilay Shroff -Signed-off-by: Bjorn Helgaas -Tested-by: Venkat Rao Bagalkote -Tested-by: Nam Cao -Reviewed-by: Nam Cao -Reviewed-by: Vivian Wang -Acked-by: Madhavan Srinivasan -Link: https://patch.msgid.link/20260220070239.1693303-2-nilay@linux.ibm.com -(cherry picked from commit 2185904ff8b5da76a4353e5d1236caa78e0d98e3) -Signed-off-by: Han Gao ---- - arch/powerpc/kernel/pci_of_scan.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c -index 756043dd06e9..fb9fbf0d1796 100644 ---- a/arch/powerpc/kernel/pci_of_scan.c -+++ b/arch/powerpc/kernel/pci_of_scan.c -@@ -212,6 +212,13 @@ struct pci_dev *of_create_pci_dev(struct device_node *node, - dev->error_state = pci_channel_io_normal; - dev->dma_mask = 0xffffffff; - -+ /* -+ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit -+ * if MSI (rather than MSI-X) capability does not have -+ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. -+ */ -+ dev->msi_addr_mask = DMA_BIT_MASK(64); -+ - /* Early fixups, before probing the BARs */ - pci_fixup_device(pci_fixup_early, dev); - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch b/SPECS/linux-lts-kmhv2/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch new file mode 100644 index 0000000000..9ede52445f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch @@ -0,0 +1,59 @@ +From 9030f2dc70b9b4bd8e20de88dcbbd8afa905d20e Mon Sep 17 00:00:00 2001 +From: Jessica Liu +Date: Tue, 10 Mar 2026 14:16:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: irqchip/riscv-aplic: Do not clear ACPI + dependencies on probe failure + +aplic_probe() calls acpi_dev_clear_dependencies() unconditionally at the +end, even when the preceding setup (MSI or direct mode) has failed. This is +incorrect because if the device failed to probe, it should not be +considered as active and should not clear dependencies for other devices +waiting on it. + +Fix this by returning immediately when the setup fails, skipping the ACPI +dependency cleanup. Also, explicitly return 0 on success instead of relying +on the value of 'rc' to make the success path clear. + +Fixes: 5122e380c23b ("irqchip/riscv-aplic: Add ACPI support") +Signed-off-by: Jessica Liu +Signed-off-by: Thomas Gleixner +Link: https://patch.msgid.link/20260310141600411Fu8H8-GXOOgKISU48Tjgx@zte.com.cn +(cherry picked from commit 620b6ded72a7f0f77be6ec44d0462bb85729ab7a) +Signed-off-by: Han Gao +--- + drivers/irqchip/irq-riscv-aplic-main.c | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c +index 4495ca26abf5..8775f188ea4f 100644 +--- a/drivers/irqchip/irq-riscv-aplic-main.c ++++ b/drivers/irqchip/irq-riscv-aplic-main.c +@@ -372,18 +372,21 @@ static int aplic_probe(struct platform_device *pdev) + rc = aplic_msi_setup(dev, regs); + else + rc = aplic_direct_setup(dev, regs); +- if (rc) ++ ++ if (rc) { + dev_err_probe(dev, rc, "failed to setup APLIC in %s mode\n", + msi_mode ? "MSI" : "direct"); +- else +- register_syscore(&aplic_syscore); ++ return rc; ++ } ++ ++ register_syscore(&aplic_syscore); + + #ifdef CONFIG_ACPI + if (!acpi_disabled) + acpi_dev_clear_dependencies(ACPI_COMPANION(dev)); + #endif + +- return rc; ++ return 0; + } + + static const struct of_device_id aplic_match[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0162-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch b/SPECS/linux-lts-kmhv2/0162-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch deleted file mode 100644 index ee5c00b176..0000000000 --- a/SPECS/linux-lts-kmhv2/0162-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 062318331f0323b6c2cde88974f89889bd3b3983 Mon Sep 17 00:00:00 2001 -From: Nilay Shroff -Date: Fri, 20 Feb 2026 12:32:28 +0530 -Subject: [PATCH 162/467] UPSTREAM: sparc/PCI: Initialize msi_addr_mask for - OF-created PCI devices - -Recent changes replaced the use of no_64bit_msi with msi_addr_mask, which -is now expected to be initialized to DMA_BIT_MASK(64) during PCI device -setup. On SPARC systems, this initialization was inadvertently missed for -devices instantiated from device tree nodes, leaving msi_addr_mask unset -for OF-created pci_dev instances. As a result, MSI address validation fails -during probe, causing affected devices to fail initialization. - -Initialize pdev->msi_addr_mask to DMA_BIT_MASK(64) in of_create_pci_dev() -so that MSI address validation succeeds and PCI device probing works as -expected. - -Fixes: 386ced19e9a3 ("PCI/MSI: Convert the boolean no_64bit_msi flag to a DMA address mask") -Signed-off-by: Nilay Shroff -Signed-off-by: Bjorn Helgaas -Tested-by: Han Gao # SPARC Enterprise T5220 -Tested-by: Nathaniel Roach # SPARC T5-2 -Reviewed-by: Vivian Wang -Link: https://patch.msgid.link/20260220070239.1693303-3-nilay@linux.ibm.com -(cherry picked from commit 147dae12985947cdb9e1918142f06482c5077a81) -Signed-off-by: Han Gao ---- - arch/sparc/kernel/pci.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c -index b290107170e9..a4815d544781 100644 ---- a/arch/sparc/kernel/pci.c -+++ b/arch/sparc/kernel/pci.c -@@ -355,6 +355,13 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, - dev->error_state = pci_channel_io_normal; - dev->dma_mask = 0xffffffff; - -+ /* -+ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit -+ * if MSI (rather than MSI-X) capability does not have -+ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. -+ */ -+ dev->msi_addr_mask = DMA_BIT_MASK(64); -+ - if (of_node_name_eq(node, "pci")) { - /* a PCI-PCI bridge */ - dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch b/SPECS/linux-lts-kmhv2/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch new file mode 100644 index 0000000000..7e5c262b22 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch @@ -0,0 +1,65 @@ +From f0f6537007b57483923b71a9da409d7811b4a6a1 Mon Sep 17 00:00:00 2001 +From: Jessica Liu +Date: Tue, 10 Mar 2026 14:17:31 +0800 +Subject: [RUYI PATCH] UPSTREAM: irqchip/riscv-aplic: Register syscore + operations only once + +Since commit 95a8ddde3660 ("irqchip/riscv-aplic: Preserve APLIC +states across suspend/resume"), when multiple NUMA nodes exist +and AIA is not configured as "none", aplic_probe() is called +multiple times. This leads to register_syscore(&aplic_syscore) +being invoked repeatedly, causing the following Oops: + + list_add double add: new=ffffffffb91461f0, prev=ffffffffb91461f0, next=ffffffffb915c408. + [] __list_add_valid_or_report+0x60/0xc0 + [] register_syscore+0x3e/0x70 + [] aplic_probe+0xc6/0x112 + +Fix this by registering syscore operations only once, using a static +variable aplic_syscore_registered to track registration. + +[ tglx: Trim backtrace properly ] + +Fixes: 95a8ddde3660 ("irqchip/riscv-aplic: Preserve APLIC states across suspend/resume") +Signed-off-by: Jessica Liu +Signed-off-by: Thomas Gleixner +Link: https://patch.msgid.link/20260310141731145xMwLsyvXl9Gw-m6A4VRYj@zte.com.cn +(cherry picked from commit b330fbfd34d7624bec62b99ad88dba2614326a19) +Signed-off-by: Han Gao +--- + drivers/irqchip/irq-riscv-aplic-main.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c +index 8775f188ea4f..9f53979b6962 100644 +--- a/drivers/irqchip/irq-riscv-aplic-main.c ++++ b/drivers/irqchip/irq-riscv-aplic-main.c +@@ -116,6 +116,16 @@ static struct syscore aplic_syscore = { + .ops = &aplic_syscore_ops, + }; + ++static bool aplic_syscore_registered __ro_after_init; ++ ++static void aplic_syscore_init(void) ++{ ++ if (!aplic_syscore_registered) { ++ register_syscore(&aplic_syscore); ++ aplic_syscore_registered = true; ++ } ++} ++ + static int aplic_pm_notifier(struct notifier_block *nb, unsigned long action, void *data) + { + struct aplic_priv *priv = container_of(nb, struct aplic_priv, genpd_nb); +@@ -379,7 +389,7 @@ static int aplic_probe(struct platform_device *pdev) + return rc; + } + +- register_syscore(&aplic_syscore); ++ aplic_syscore_init(); + + #ifdef CONFIG_ACPI + if (!acpi_disabled) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0163-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch b/SPECS/linux-lts-kmhv2/0163-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch deleted file mode 100644 index d62c31b7b3..0000000000 --- a/SPECS/linux-lts-kmhv2/0163-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch +++ /dev/null @@ -1,4919 +0,0 @@ -From 3db4461f56317b6d1205c5f1aa79d971772b0d4d Mon Sep 17 00:00:00 2001 -From: Thierry Reding -Date: Wed, 29 Oct 2025 17:33:30 +0100 -Subject: [PATCH 163/467] UPSTREAM: syscore: Pass context data to callbacks - -Several drivers can benefit from registering per-instance data along -with the syscore operations. To achieve this, move the modifiable fields -out of the syscore_ops structure and into a separate struct syscore that -can be registered with the framework. Add a void * driver data field for -drivers to store contextual data that will be passed to the syscore ops. - -Acked-by: Rafael J. Wysocki (Intel) -Signed-off-by: Thierry Reding -(cherry picked from commit a97fbc3ee3e2a536fafaff04f21f45472db71769) -Signed-off-by: Han Gao ---- - arch/arm/mach-exynos/mcpm-exynos.c | 12 ++-- - arch/arm/mach-exynos/suspend.c | 48 +++++++------ - arch/arm/mach-pxa/generic.h | 6 +- - arch/arm/mach-pxa/irq.c | 10 ++- - arch/arm/mach-pxa/mfp-pxa2xx.c | 10 ++- - arch/arm/mach-pxa/mfp-pxa3xx.c | 10 ++- - arch/arm/mach-pxa/pxa25x.c | 4 +- - arch/arm/mach-pxa/pxa27x.c | 4 +- - arch/arm/mach-pxa/pxa3xx.c | 4 +- - arch/arm/mach-pxa/smemc.c | 12 ++-- - arch/arm/mach-s3c/irq-pm-s3c64xx.c | 12 ++-- - arch/arm/mach-s5pv210/pm.c | 10 ++- - arch/arm/mach-versatile/integrator_ap.c | 12 ++-- - arch/arm/mm/cache-b15-rac.c | 12 ++-- - arch/loongarch/kernel/smp.c | 12 ++-- - arch/mips/alchemy/common/dbdma.c | 12 ++-- - arch/mips/alchemy/common/irq.c | 24 ++++--- - arch/mips/alchemy/common/usb.c | 12 ++-- - arch/mips/pci/pci-alchemy.c | 16 +++-- - arch/powerpc/platforms/cell/spu_base.c | 10 ++- - arch/powerpc/platforms/powermac/pic.c | 12 ++-- - arch/powerpc/sysdev/fsl_lbc.c | 12 ++-- - arch/powerpc/sysdev/fsl_pci.c | 12 ++-- - arch/powerpc/sysdev/ipic.c | 12 ++-- - arch/powerpc/sysdev/mpic.c | 14 ++-- - arch/powerpc/sysdev/mpic_timer.c | 10 ++- - arch/sh/mm/pmb.c | 10 ++- - arch/x86/events/amd/ibs.c | 12 ++-- - arch/x86/hyperv/hv_init.c | 12 ++-- - arch/x86/kernel/amd_gart_64.c | 10 ++- - arch/x86/kernel/apic/apic.c | 12 ++-- - arch/x86/kernel/apic/io_apic.c | 17 +++-- - arch/x86/kernel/cpu/aperfmperf.c | 20 +++--- - arch/x86/kernel/cpu/intel_epb.c | 16 +++-- - arch/x86/kernel/cpu/mce/core.c | 14 ++-- - arch/x86/kernel/cpu/microcode/core.c | 15 ++++- - arch/x86/kernel/cpu/mtrr/legacy.c | 12 ++-- - arch/x86/kernel/cpu/umwait.c | 10 ++- - arch/x86/kernel/i8237.c | 10 ++- - arch/x86/kernel/i8259.c | 14 ++-- - arch/x86/kernel/kvm.c | 12 ++-- - drivers/acpi/pci_link.c | 10 ++- - drivers/acpi/sleep.c | 12 ++-- - drivers/base/firmware_loader/main.c | 12 ++-- - drivers/base/syscore.c | 82 ++++++++++++----------- - drivers/bus/mvebu-mbus.c | 16 +++-- - drivers/clk/at91/pmc.c | 12 ++-- - drivers/clk/imx/clk-vf610.c | 12 ++-- - drivers/clk/ingenic/jz4725b-cgu.c | 2 +- - drivers/clk/ingenic/jz4740-cgu.c | 2 +- - drivers/clk/ingenic/jz4755-cgu.c | 2 +- - drivers/clk/ingenic/jz4760-cgu.c | 2 +- - drivers/clk/ingenic/jz4770-cgu.c | 2 +- - drivers/clk/ingenic/jz4780-cgu.c | 2 +- - drivers/clk/ingenic/pm.c | 14 ++-- - drivers/clk/ingenic/pm.h | 2 +- - drivers/clk/ingenic/tcu.c | 12 ++-- - drivers/clk/ingenic/x1000-cgu.c | 2 +- - drivers/clk/ingenic/x1830-cgu.c | 2 +- - drivers/clk/mvebu/common.c | 12 ++-- - drivers/clk/rockchip/clk-rk3288.c | 12 ++-- - drivers/clk/samsung/clk-s5pv210-audss.c | 12 ++-- - drivers/clk/samsung/clk.c | 12 ++-- - drivers/clk/tegra/clk-tegra210.c | 12 ++-- - drivers/clocksource/timer-armada-370-xp.c | 12 ++-- - drivers/cpuidle/cpuidle-psci.c | 12 ++-- - drivers/gpio/gpio-mxc.c | 12 ++-- - drivers/gpio/gpio-pxa.c | 12 ++-- - drivers/gpio/gpio-sa1100.c | 12 ++-- - drivers/hv/vmbus_drv.c | 14 ++-- - drivers/iommu/amd/init.c | 16 +++-- - drivers/iommu/intel/iommu.c | 12 ++-- - drivers/irqchip/exynos-combiner.c | 14 ++-- - drivers/irqchip/irq-armada-370-xp.c | 12 ++-- - drivers/irqchip/irq-bcm7038-l1.c | 12 ++-- - drivers/irqchip/irq-gic-v3-its.c | 12 ++-- - drivers/irqchip/irq-i8259.c | 12 ++-- - drivers/irqchip/irq-imx-gpcv2.c | 16 +++-- - drivers/irqchip/irq-loongson-eiointc.c | 12 ++-- - drivers/irqchip/irq-loongson-htpic.c | 10 ++- - drivers/irqchip/irq-loongson-htvec.c | 12 ++-- - drivers/irqchip/irq-loongson-pch-lpc.c | 12 ++-- - drivers/irqchip/irq-loongson-pch-pic.c | 12 ++-- - drivers/irqchip/irq-mchp-eic.c | 12 ++-- - drivers/irqchip/irq-mst-intc.c | 12 ++-- - drivers/irqchip/irq-mtk-cirq.c | 12 ++-- - drivers/irqchip/irq-renesas-rzg2l.c | 12 ++-- - drivers/irqchip/irq-sa11x0.c | 12 ++-- - drivers/irqchip/irq-sifive-plic.c | 12 ++-- - drivers/irqchip/irq-sun6i-r.c | 18 +++-- - drivers/irqchip/irq-tegra.c | 12 ++-- - drivers/irqchip/irq-vic.c | 12 ++-- - drivers/leds/trigger/ledtrig-cpu.c | 14 ++-- - drivers/macintosh/via-pmu.c | 12 ++-- - drivers/power/reset/sc27xx-poweroff.c | 10 ++- - drivers/sh/clk/core.c | 10 ++- - drivers/sh/intc/core.c | 12 ++-- - drivers/soc/bcm/brcmstb/biuctrl.c | 12 ++-- - drivers/soc/tegra/pmc.c | 17 +++-- - drivers/thermal/intel/intel_hfi.c | 12 ++-- - drivers/xen/xen-acpi-processor.c | 12 ++-- - include/linux/syscore_ops.h | 15 +++-- - kernel/cpu_pm.c | 12 ++-- - kernel/irq/generic-chip.c | 14 ++-- - kernel/irq/pm.c | 11 ++- - kernel/printk/printk.c | 11 ++- - kernel/time/sched_clock.c | 22 ++++-- - kernel/time/timekeeping.c | 22 ++++-- - virt/kvm/kvm_main.c | 18 +++-- - 109 files changed, 898 insertions(+), 470 deletions(-) - -diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c -index fd0dbeb93357..cb7d8a7b14e0 100644 ---- a/arch/arm/mach-exynos/mcpm-exynos.c -+++ b/arch/arm/mach-exynos/mcpm-exynos.c -@@ -215,7 +215,7 @@ static const struct of_device_id exynos_dt_mcpm_match[] = { - {}, - }; - --static void exynos_mcpm_setup_entry_point(void) -+static void exynos_mcpm_setup_entry_point(void *data) - { - /* - * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr -@@ -228,10 +228,14 @@ static void exynos_mcpm_setup_entry_point(void) - __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8); - } - --static struct syscore_ops exynos_mcpm_syscore_ops = { -+static const struct syscore_ops exynos_mcpm_syscore_ops = { - .resume = exynos_mcpm_setup_entry_point, - }; - -+static struct syscore exynos_mcpm_syscore = { -+ .ops = &exynos_mcpm_syscore_ops, -+}; -+ - static int __init exynos_mcpm_init(void) - { - struct device_node *node; -@@ -300,9 +304,9 @@ static int __init exynos_mcpm_init(void) - pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i)); - } - -- exynos_mcpm_setup_entry_point(); -+ exynos_mcpm_setup_entry_point(NULL); - -- register_syscore_ops(&exynos_mcpm_syscore_ops); -+ register_syscore(&exynos_mcpm_syscore); - - return ret; - } -diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c -index 150a1e56dcae..22d723553f62 100644 ---- a/arch/arm/mach-exynos/suspend.c -+++ b/arch/arm/mach-exynos/suspend.c -@@ -53,9 +53,9 @@ struct exynos_pm_data { - - void (*pm_prepare)(void); - void (*pm_resume_prepare)(void); -- void (*pm_resume)(void); -- int (*pm_suspend)(void); - int (*cpu_suspend)(unsigned long); -+ -+ const struct syscore_ops *syscore_ops; - }; - - /* Used only on Exynos542x/5800 */ -@@ -376,7 +376,7 @@ static void exynos5420_pm_prepare(void) - } - - --static int exynos_pm_suspend(void) -+static int exynos_pm_suspend(void *data) - { - exynos_pm_central_suspend(); - -@@ -390,7 +390,7 @@ static int exynos_pm_suspend(void) - return 0; - } - --static int exynos5420_pm_suspend(void) -+static int exynos5420_pm_suspend(void *data) - { - u32 this_cluster; - -@@ -408,7 +408,7 @@ static int exynos5420_pm_suspend(void) - return 0; - } - --static void exynos_pm_resume(void) -+static void exynos_pm_resume(void *data) - { - u32 cpuid = read_cpuid_part(); - -@@ -429,7 +429,7 @@ static void exynos_pm_resume(void) - exynos_set_delayed_reset_assertion(true); - } - --static void exynos3250_pm_resume(void) -+static void exynos3250_pm_resume(void *data) - { - u32 cpuid = read_cpuid_part(); - -@@ -473,7 +473,7 @@ static void exynos5420_prepare_pm_resume(void) - } - } - --static void exynos5420_pm_resume(void) -+static void exynos5420_pm_resume(void *data) - { - unsigned long tmp; - -@@ -596,41 +596,52 @@ static const struct platform_suspend_ops exynos_suspend_ops = { - .valid = suspend_valid_only_mem, - }; - -+static const struct syscore_ops exynos3250_syscore_ops = { -+ .suspend = exynos_pm_suspend, -+ .resume = exynos3250_pm_resume, -+}; -+ - static const struct exynos_pm_data exynos3250_pm_data = { - .wkup_irq = exynos3250_wkup_irq, - .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), -- .pm_suspend = exynos_pm_suspend, -- .pm_resume = exynos3250_pm_resume, - .pm_prepare = exynos3250_pm_prepare, - .cpu_suspend = exynos3250_cpu_suspend, -+ .syscore_ops = &exynos3250_syscore_ops, -+}; -+ -+static const struct syscore_ops exynos_syscore_ops = { -+ .suspend = exynos_pm_suspend, -+ .resume = exynos_pm_resume, - }; - - static const struct exynos_pm_data exynos4_pm_data = { - .wkup_irq = exynos4_wkup_irq, - .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), -- .pm_suspend = exynos_pm_suspend, -- .pm_resume = exynos_pm_resume, - .pm_prepare = exynos_pm_prepare, - .cpu_suspend = exynos_cpu_suspend, -+ .syscore_ops = &exynos_syscore_ops, - }; - - static const struct exynos_pm_data exynos5250_pm_data = { - .wkup_irq = exynos5250_wkup_irq, - .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), -- .pm_suspend = exynos_pm_suspend, -- .pm_resume = exynos_pm_resume, - .pm_prepare = exynos_pm_prepare, - .cpu_suspend = exynos_cpu_suspend, -+ .syscore_ops = &exynos_syscore_ops, -+}; -+ -+static const struct syscore_ops exynos5420_syscore_ops = { -+ .resume = exynos5420_pm_resume, -+ .suspend = exynos5420_pm_suspend, - }; - - static const struct exynos_pm_data exynos5420_pm_data = { - .wkup_irq = exynos5250_wkup_irq, - .wake_disable_mask = (0x7F << 7) | (0x1F << 1), - .pm_resume_prepare = exynos5420_prepare_pm_resume, -- .pm_resume = exynos5420_pm_resume, -- .pm_suspend = exynos5420_pm_suspend, - .pm_prepare = exynos5420_pm_prepare, - .cpu_suspend = exynos5420_cpu_suspend, -+ .syscore_ops = &exynos5420_syscore_ops, - }; - - static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { -@@ -656,7 +667,7 @@ static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { - { /*sentinel*/ }, - }; - --static struct syscore_ops exynos_pm_syscore_ops; -+static struct syscore exynos_pm_syscore; - - void __init exynos_pm_init(void) - { -@@ -684,10 +695,9 @@ void __init exynos_pm_init(void) - tmp |= pm_data->wake_disable_mask; - pmu_raw_writel(tmp, S5P_WAKEUP_MASK); - -- exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; -- exynos_pm_syscore_ops.resume = pm_data->pm_resume; -+ exynos_pm_syscore.ops = pm_data->syscore_ops; - -- register_syscore_ops(&exynos_pm_syscore_ops); -+ register_syscore(&exynos_pm_syscore); - suspend_set_ops(&exynos_suspend_ops); - - /* -diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h -index c9c2c46ecead..caad4fca8de3 100644 ---- a/arch/arm/mach-pxa/generic.h -+++ b/arch/arm/mach-pxa/generic.h -@@ -34,9 +34,9 @@ extern void __init pxa27x_map_io(void); - extern void __init pxa3xx_init_irq(void); - extern void __init pxa3xx_map_io(void); - --extern struct syscore_ops pxa_irq_syscore_ops; --extern struct syscore_ops pxa2xx_mfp_syscore_ops; --extern struct syscore_ops pxa3xx_mfp_syscore_ops; -+extern struct syscore pxa_irq_syscore; -+extern struct syscore pxa2xx_mfp_syscore; -+extern struct syscore pxa3xx_mfp_syscore; - - void __init pxa_set_ffuart_info(void *info); - void __init pxa_set_btuart_info(void *info); -diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c -index 5bfce8aa4102..99acebbbf065 100644 ---- a/arch/arm/mach-pxa/irq.c -+++ b/arch/arm/mach-pxa/irq.c -@@ -178,7 +178,7 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) - static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; - static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; - --static int pxa_irq_suspend(void) -+static int pxa_irq_suspend(void *data) - { - int i; - -@@ -197,7 +197,7 @@ static int pxa_irq_suspend(void) - return 0; - } - --static void pxa_irq_resume(void) -+static void pxa_irq_resume(void *data) - { - int i; - -@@ -219,11 +219,15 @@ static void pxa_irq_resume(void) - #define pxa_irq_resume NULL - #endif - --struct syscore_ops pxa_irq_syscore_ops = { -+static const struct syscore_ops pxa_irq_syscore_ops = { - .suspend = pxa_irq_suspend, - .resume = pxa_irq_resume, - }; - -+struct syscore pxa_irq_syscore = { -+ .ops = &pxa_irq_syscore_ops, -+}; -+ - #ifdef CONFIG_OF - static const struct of_device_id intc_ids[] __initconst = { - { .compatible = "marvell,pxa-intc", }, -diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c -index f5a3d890f682..d1347055fbe4 100644 ---- a/arch/arm/mach-pxa/mfp-pxa2xx.c -+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c -@@ -346,7 +346,7 @@ static unsigned long saved_gpdr[4]; - static unsigned long saved_gplr[4]; - static unsigned long saved_pgsr[4]; - --static int pxa2xx_mfp_suspend(void) -+static int pxa2xx_mfp_suspend(void *data) - { - int i; - -@@ -385,7 +385,7 @@ static int pxa2xx_mfp_suspend(void) - return 0; - } - --static void pxa2xx_mfp_resume(void) -+static void pxa2xx_mfp_resume(void *data) - { - int i; - -@@ -404,11 +404,15 @@ static void pxa2xx_mfp_resume(void) - #define pxa2xx_mfp_resume NULL - #endif - --struct syscore_ops pxa2xx_mfp_syscore_ops = { -+static const struct syscore_ops pxa2xx_mfp_syscore_ops = { - .suspend = pxa2xx_mfp_suspend, - .resume = pxa2xx_mfp_resume, - }; - -+struct syscore pxa2xx_mfp_syscore = { -+ .ops = &pxa2xx_mfp_syscore_ops, -+}; -+ - static int __init pxa2xx_mfp_init(void) - { - int i; -diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c -index d16ab7451efe..fe7498fbb62b 100644 ---- a/arch/arm/mach-pxa/mfp-pxa3xx.c -+++ b/arch/arm/mach-pxa/mfp-pxa3xx.c -@@ -27,13 +27,13 @@ - * a pull-down mode if they're an active low chip select, and we're - * just entering standby. - */ --static int pxa3xx_mfp_suspend(void) -+static int pxa3xx_mfp_suspend(void *data) - { - mfp_config_lpm(); - return 0; - } - --static void pxa3xx_mfp_resume(void) -+static void pxa3xx_mfp_resume(void *data) - { - mfp_config_run(); - -@@ -49,7 +49,11 @@ static void pxa3xx_mfp_resume(void) - #define pxa3xx_mfp_resume NULL - #endif - --struct syscore_ops pxa3xx_mfp_syscore_ops = { -+static const struct syscore_ops pxa3xx_mfp_syscore_ops = { - .suspend = pxa3xx_mfp_suspend, - .resume = pxa3xx_mfp_resume, - }; -+ -+struct syscore pxa3xx_mfp_syscore = { -+ .ops = &pxa3xx_mfp_syscore_ops, -+}; -diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c -index 03e34841fc00..70509a599814 100644 ---- a/arch/arm/mach-pxa/pxa25x.c -+++ b/arch/arm/mach-pxa/pxa25x.c -@@ -235,8 +235,8 @@ static int __init pxa25x_init(void) - - pxa25x_init_pm(); - -- register_syscore_ops(&pxa_irq_syscore_ops); -- register_syscore_ops(&pxa2xx_mfp_syscore_ops); -+ register_syscore(&pxa_irq_syscore); -+ register_syscore(&pxa2xx_mfp_syscore); - - if (!of_have_populated_dt()) { - software_node_register(&pxa2xx_gpiochip_node); -diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c -index f8382477d629..ff6361979038 100644 ---- a/arch/arm/mach-pxa/pxa27x.c -+++ b/arch/arm/mach-pxa/pxa27x.c -@@ -337,8 +337,8 @@ static int __init pxa27x_init(void) - - pxa27x_init_pm(); - -- register_syscore_ops(&pxa_irq_syscore_ops); -- register_syscore_ops(&pxa2xx_mfp_syscore_ops); -+ register_syscore(&pxa_irq_syscore); -+ register_syscore(&pxa2xx_mfp_syscore); - - if (!of_have_populated_dt()) { - software_node_register(&pxa2xx_gpiochip_node); -diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c -index 1d1e5713464d..06c578ea658e 100644 ---- a/arch/arm/mach-pxa/pxa3xx.c -+++ b/arch/arm/mach-pxa/pxa3xx.c -@@ -424,8 +424,8 @@ static int __init pxa3xx_init(void) - if (cpu_is_pxa320()) - enable_irq_wake(IRQ_WAKEUP1); - -- register_syscore_ops(&pxa_irq_syscore_ops); -- register_syscore_ops(&pxa3xx_mfp_syscore_ops); -+ register_syscore(&pxa_irq_syscore); -+ register_syscore(&pxa3xx_mfp_syscore); - } - - return ret; -diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c -index 2d2a321d82f8..fb93a8f28356 100644 ---- a/arch/arm/mach-pxa/smemc.c -+++ b/arch/arm/mach-pxa/smemc.c -@@ -18,7 +18,7 @@ static unsigned long msc[2]; - static unsigned long sxcnfg, memclkcfg; - static unsigned long csadrcfg[4]; - --static int pxa3xx_smemc_suspend(void) -+static int pxa3xx_smemc_suspend(void *data) - { - msc[0] = __raw_readl(MSC0); - msc[1] = __raw_readl(MSC1); -@@ -32,7 +32,7 @@ static int pxa3xx_smemc_suspend(void) - return 0; - } - --static void pxa3xx_smemc_resume(void) -+static void pxa3xx_smemc_resume(void *data) - { - __raw_writel(msc[0], MSC0); - __raw_writel(msc[1], MSC1); -@@ -46,11 +46,15 @@ static void pxa3xx_smemc_resume(void) - __raw_writel(0x2, CSMSADRCFG); - } - --static struct syscore_ops smemc_syscore_ops = { -+static const struct syscore_ops smemc_syscore_ops = { - .suspend = pxa3xx_smemc_suspend, - .resume = pxa3xx_smemc_resume, - }; - -+static struct syscore smemc_syscore = { -+ .ops = &smemc_syscore_ops, -+}; -+ - static int __init smemc_init(void) - { - if (cpu_is_pxa3xx()) { -@@ -64,7 +68,7 @@ static int __init smemc_init(void) - */ - __raw_writel(0x2, CSMSADRCFG); - -- register_syscore_ops(&smemc_syscore_ops); -+ register_syscore(&smemc_syscore); - } - - return 0; -diff --git a/arch/arm/mach-s3c/irq-pm-s3c64xx.c b/arch/arm/mach-s3c/irq-pm-s3c64xx.c -index 4a1e935bada1..ab726c595001 100644 ---- a/arch/arm/mach-s3c/irq-pm-s3c64xx.c -+++ b/arch/arm/mach-s3c/irq-pm-s3c64xx.c -@@ -58,7 +58,7 @@ static struct irq_grp_save { - - static u32 irq_uart_mask[SERIAL_SAMSUNG_UARTS]; - --static int s3c64xx_irq_pm_suspend(void) -+static int s3c64xx_irq_pm_suspend(void *data) - { - struct irq_grp_save *grp = eint_grp_save; - int i; -@@ -79,7 +79,7 @@ static int s3c64xx_irq_pm_suspend(void) - return 0; - } - --static void s3c64xx_irq_pm_resume(void) -+static void s3c64xx_irq_pm_resume(void *data) - { - struct irq_grp_save *grp = eint_grp_save; - int i; -@@ -100,18 +100,22 @@ static void s3c64xx_irq_pm_resume(void) - S3C_PMDBG("%s: IRQ configuration restored\n", __func__); - } - --static struct syscore_ops s3c64xx_irq_syscore_ops = { -+static const struct syscore_ops s3c64xx_irq_syscore_ops = { - .suspend = s3c64xx_irq_pm_suspend, - .resume = s3c64xx_irq_pm_resume, - }; - -+static struct syscore s3c64xx_irq_syscore = { -+ .ops = &s3c64xx_irq_syscore_ops, -+}; -+ - static __init int s3c64xx_syscore_init(void) - { - /* Appropriate drivers (pinctrl, uart) handle this when using DT. */ - if (of_have_populated_dt() || !soc_is_s3c64xx()) - return 0; - -- register_syscore_ops(&s3c64xx_irq_syscore_ops); -+ register_syscore(&s3c64xx_irq_syscore); - - return 0; - } -diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c -index 6fa70f787df4..fa270750364c 100644 ---- a/arch/arm/mach-s5pv210/pm.c -+++ b/arch/arm/mach-s5pv210/pm.c -@@ -195,20 +195,24 @@ static const struct platform_suspend_ops s5pv210_suspend_ops = { - /* - * Syscore operations used to delay restore of certain registers. - */ --static void s5pv210_pm_resume(void) -+static void s5pv210_pm_resume(void *data) - { - s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); - } - --static struct syscore_ops s5pv210_pm_syscore_ops = { -+static const struct syscore_ops s5pv210_pm_syscore_ops = { - .resume = s5pv210_pm_resume, - }; - -+static struct syscore s5pv210_pm_syscore = { -+ .ops = &s5pv210_pm_syscore_ops, -+}; -+ - /* - * Initialization entry point. - */ - void __init s5pv210_pm_init(void) - { -- register_syscore_ops(&s5pv210_pm_syscore_ops); -+ register_syscore(&s5pv210_pm_syscore); - suspend_set_ops(&s5pv210_suspend_ops); - } -diff --git a/arch/arm/mach-versatile/integrator_ap.c b/arch/arm/mach-versatile/integrator_ap.c -index 4bd6712e9f52..ee90d6619d0d 100644 ---- a/arch/arm/mach-versatile/integrator_ap.c -+++ b/arch/arm/mach-versatile/integrator_ap.c -@@ -63,13 +63,13 @@ static void __init ap_map_io(void) - #ifdef CONFIG_PM - static unsigned long ic_irq_enable; - --static int irq_suspend(void) -+static int irq_suspend(void *data) - { - ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); - return 0; - } - --static void irq_resume(void) -+static void irq_resume(void *data) - { - /* disable all irq sources */ - cm_clear_irqs(); -@@ -83,14 +83,18 @@ static void irq_resume(void) - #define irq_resume NULL - #endif - --static struct syscore_ops irq_syscore_ops = { -+static const struct syscore_ops irq_syscore_ops = { - .suspend = irq_suspend, - .resume = irq_resume, - }; - -+static struct syscore irq_syscore = { -+ .ops = &irq_syscore_ops, -+}; -+ - static int __init irq_syscore_init(void) - { -- register_syscore_ops(&irq_syscore_ops); -+ register_syscore(&irq_syscore); - - return 0; - } -diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c -index 6f63b90f9e1a..e7807356dfab 100644 ---- a/arch/arm/mm/cache-b15-rac.c -+++ b/arch/arm/mm/cache-b15-rac.c -@@ -256,7 +256,7 @@ static int b15_rac_dead_cpu(unsigned int cpu) - return 0; - } - --static int b15_rac_suspend(void) -+static int b15_rac_suspend(void *data) - { - /* Suspend the read-ahead cache oeprations, forcing our cache - * implementation to fallback to the regular ARMv7 calls. -@@ -271,7 +271,7 @@ static int b15_rac_suspend(void) - return 0; - } - --static void b15_rac_resume(void) -+static void b15_rac_resume(void *data) - { - /* Coming out of a S3 suspend/resume cycle, the read-ahead cache - * register RAC_CONFIG0_REG will be restored to its default value, make -@@ -282,11 +282,15 @@ static void b15_rac_resume(void) - clear_bit(RAC_SUSPENDED, &b15_rac_flags); - } - --static struct syscore_ops b15_rac_syscore_ops = { -+static const struct syscore_ops b15_rac_syscore_ops = { - .suspend = b15_rac_suspend, - .resume = b15_rac_resume, - }; - -+static struct syscore b15_rac_syscore = { -+ .ops = &b15_rac_syscore_ops, -+}; -+ - static int __init b15_rac_init(void) - { - struct device_node *dn, *cpu_dn; -@@ -347,7 +351,7 @@ static int __init b15_rac_init(void) - } - - if (IS_ENABLED(CONFIG_PM_SLEEP)) -- register_syscore_ops(&b15_rac_syscore_ops); -+ register_syscore(&b15_rac_syscore); - - spin_lock(&rac_lock); - reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); -diff --git a/arch/loongarch/kernel/smp.c b/arch/loongarch/kernel/smp.c -index 46036d98da75..8b2fcb3fb874 100644 ---- a/arch/loongarch/kernel/smp.c -+++ b/arch/loongarch/kernel/smp.c -@@ -535,28 +535,32 @@ int hibernate_resume_nonboot_cpu_disable(void) - */ - #ifdef CONFIG_PM - --static int loongson_ipi_suspend(void) -+static int loongson_ipi_suspend(void *data) - { - return 0; - } - --static void loongson_ipi_resume(void) -+static void loongson_ipi_resume(void *data) - { - iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN); - } - --static struct syscore_ops loongson_ipi_syscore_ops = { -+static const struct syscore_ops loongson_ipi_syscore_ops = { - .resume = loongson_ipi_resume, - .suspend = loongson_ipi_suspend, - }; - -+static struct syscore loongson_ipi_syscore = { -+ .ops = &loongson_ipi_syscore_ops, -+}; -+ - /* - * Enable boot cpu ipi before enabling nonboot cpus - * during syscore_resume. - */ - static int __init ipi_pm_init(void) - { -- register_syscore_ops(&loongson_ipi_syscore_ops); -+ register_syscore(&loongson_ipi_syscore); - return 0; - } - -diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c -index 6a3c890f7bbf..6c2c2010bbae 100644 ---- a/arch/mips/alchemy/common/dbdma.c -+++ b/arch/mips/alchemy/common/dbdma.c -@@ -982,7 +982,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) - - static unsigned long alchemy_dbdma_pm_data[NUM_DBDMA_CHANS + 1][6]; - --static int alchemy_dbdma_suspend(void) -+static int alchemy_dbdma_suspend(void *data) - { - int i; - void __iomem *addr; -@@ -1019,7 +1019,7 @@ static int alchemy_dbdma_suspend(void) - return 0; - } - --static void alchemy_dbdma_resume(void) -+static void alchemy_dbdma_resume(void *data) - { - int i; - void __iomem *addr; -@@ -1044,11 +1044,15 @@ static void alchemy_dbdma_resume(void) - } - } - --static struct syscore_ops alchemy_dbdma_syscore_ops = { -+static const struct syscore_ops alchemy_dbdma_syscore_ops = { - .suspend = alchemy_dbdma_suspend, - .resume = alchemy_dbdma_resume, - }; - -+static struct syscore alchemy_dbdma_syscore = { -+ .ops = &alchemy_dbdma_syscore_ops, -+}; -+ - static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable) - { - int ret; -@@ -1071,7 +1075,7 @@ static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable) - printk(KERN_ERR "Cannot grab DBDMA interrupt!\n"); - else { - dbdma_initialized = 1; -- register_syscore_ops(&alchemy_dbdma_syscore_ops); -+ register_syscore(&alchemy_dbdma_syscore); - } - - return ret; -diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c -index da9f9220048f..2403afcd2fb9 100644 ---- a/arch/mips/alchemy/common/irq.c -+++ b/arch/mips/alchemy/common/irq.c -@@ -758,7 +758,7 @@ static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d) - wmb(); - } - --static int alchemy_ic_suspend(void) -+static int alchemy_ic_suspend(void *data) - { - alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), - alchemy_gpic_pmdata); -@@ -767,7 +767,7 @@ static int alchemy_ic_suspend(void) - return 0; - } - --static void alchemy_ic_resume(void) -+static void alchemy_ic_resume(void *data) - { - alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), - &alchemy_gpic_pmdata[7]); -@@ -775,7 +775,7 @@ static void alchemy_ic_resume(void) - alchemy_gpic_pmdata); - } - --static int alchemy_gpic_suspend(void) -+static int alchemy_gpic_suspend(void *data) - { - void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); - int i; -@@ -806,7 +806,7 @@ static int alchemy_gpic_suspend(void) - return 0; - } - --static void alchemy_gpic_resume(void) -+static void alchemy_gpic_resume(void *data) - { - void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); - int i; -@@ -837,16 +837,24 @@ static void alchemy_gpic_resume(void) - wmb(); - } - --static struct syscore_ops alchemy_ic_pmops = { -+static const struct syscore_ops alchemy_ic_pmops = { - .suspend = alchemy_ic_suspend, - .resume = alchemy_ic_resume, - }; - --static struct syscore_ops alchemy_gpic_pmops = { -+static struct syscore alchemy_ic_pm = { -+ .ops = &alchemy_ic_pmops, -+}; -+ -+static const struct syscore_ops alchemy_gpic_pmops = { - .suspend = alchemy_gpic_suspend, - .resume = alchemy_gpic_resume, - }; - -+static struct syscore alchemy_gpic_pm = { -+ .ops = &alchemy_gpic_pmops, -+}; -+ - /******************************************************************************/ - - /* create chained handlers for the 4 IC requests to the MIPS IRQ ctrl */ -@@ -880,7 +888,7 @@ static void __init au1000_init_irq(struct alchemy_irqmap *map) - - ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR)); - ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR)); -- register_syscore_ops(&alchemy_ic_pmops); -+ register_syscore(&alchemy_ic_pm); - mips_cpu_irq_init(); - - /* register all 64 possible IC0+IC1 irq sources as type "none". -@@ -925,7 +933,7 @@ static void __init alchemy_gpic_init_irq(const struct alchemy_irqmap *dints) - int i; - void __iomem *bank_base; - -- register_syscore_ops(&alchemy_gpic_pmops); -+ register_syscore(&alchemy_gpic_pm); - mips_cpu_irq_init(); - - /* disable & ack all possible interrupt sources */ -diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c -index 5d618547ebf0..a55f32bf517c 100644 ---- a/arch/mips/alchemy/common/usb.c -+++ b/arch/mips/alchemy/common/usb.c -@@ -580,22 +580,26 @@ static void alchemy_usb_pm(int susp) - } - } - --static int alchemy_usb_suspend(void) -+static int alchemy_usb_suspend(void *data) - { - alchemy_usb_pm(1); - return 0; - } - --static void alchemy_usb_resume(void) -+static void alchemy_usb_resume(void *data) - { - alchemy_usb_pm(0); - } - --static struct syscore_ops alchemy_usb_pm_ops = { -+static const struct syscore_ops alchemy_usb_pm_syscore_ops = { - .suspend = alchemy_usb_suspend, - .resume = alchemy_usb_resume, - }; - -+static struct syscore alchemy_usb_pm_syscore = { -+ .ops = &alchemy_usb_pm_syscore_ops, -+}; -+ - static int __init alchemy_usb_init(void) - { - int ret = 0; -@@ -620,7 +624,7 @@ static int __init alchemy_usb_init(void) - } - - if (!ret) -- register_syscore_ops(&alchemy_usb_pm_ops); -+ register_syscore(&alchemy_usb_pm_syscore); - - return ret; - } -diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c -index 58625d1b6465..6bfee0f71803 100644 ---- a/arch/mips/pci/pci-alchemy.c -+++ b/arch/mips/pci/pci-alchemy.c -@@ -304,7 +304,7 @@ static int alchemy_pci_def_idsel(unsigned int devsel, int assert) - } - - /* save PCI controller register contents. */ --static int alchemy_pci_suspend(void) -+static int alchemy_pci_suspend(void *data) - { - struct alchemy_pci_context *ctx = __alchemy_pci_ctx; - if (!ctx) -@@ -326,7 +326,7 @@ static int alchemy_pci_suspend(void) - return 0; - } - --static void alchemy_pci_resume(void) -+static void alchemy_pci_resume(void *data) - { - struct alchemy_pci_context *ctx = __alchemy_pci_ctx; - if (!ctx) -@@ -354,9 +354,13 @@ static void alchemy_pci_resume(void) - alchemy_pci_wired_entry(ctx); /* install it */ - } - --static struct syscore_ops alchemy_pci_pmops = { -- .suspend = alchemy_pci_suspend, -- .resume = alchemy_pci_resume, -+static const struct syscore_ops alchemy_pci_syscore_ops = { -+ .suspend = alchemy_pci_suspend, -+ .resume = alchemy_pci_resume, -+}; -+ -+static struct syscore alchemy_pci_syscore = { -+ .ops = &alchemy_pci_syscore_ops, - }; - - static int alchemy_pci_probe(struct platform_device *pdev) -@@ -478,7 +482,7 @@ static int alchemy_pci_probe(struct platform_device *pdev) - - __alchemy_pci_ctx = ctx; - platform_set_drvdata(pdev, ctx); -- register_syscore_ops(&alchemy_pci_pmops); -+ register_syscore(&alchemy_pci_syscore); - register_pci_controller(&ctx->alchemy_pci_ctrl); - - dev_info(&pdev->dev, "PCI controller at %ld MHz\n", -diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c -index 2c07387201d0..2ddb93df4817 100644 ---- a/arch/powerpc/platforms/cell/spu_base.c -+++ b/arch/powerpc/platforms/cell/spu_base.c -@@ -726,7 +726,7 @@ static inline void crash_register_spus(struct list_head *list) - } - #endif - --static void spu_shutdown(void) -+static void spu_shutdown(void *data) - { - struct spu *spu; - -@@ -738,10 +738,14 @@ static void spu_shutdown(void) - mutex_unlock(&spu_full_list_mutex); - } - --static struct syscore_ops spu_syscore_ops = { -+static const struct syscore_ops spu_syscore_ops = { - .shutdown = spu_shutdown, - }; - -+static struct syscore spu_syscore = { -+ .ops = &spu_syscore_ops, -+}; -+ - static int __init init_spu_base(void) - { - int i, ret = 0; -@@ -774,7 +778,7 @@ static int __init init_spu_base(void) - crash_register_spus(&spu_full_list); - mutex_unlock(&spu_full_list_mutex); - spu_add_dev_attr(&dev_attr_stat); -- register_syscore_ops(&spu_syscore_ops); -+ register_syscore(&spu_syscore); - - spu_init_affinity(); - -diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c -index c37783a03d25..1959cc13438f 100644 ---- a/arch/powerpc/platforms/powermac/pic.c -+++ b/arch/powerpc/platforms/powermac/pic.c -@@ -600,7 +600,7 @@ static int pmacpic_find_viaint(void) - return viaint; - } - --static int pmacpic_suspend(void) -+static int pmacpic_suspend(void *data) - { - int viaint = pmacpic_find_viaint(); - -@@ -621,7 +621,7 @@ static int pmacpic_suspend(void) - return 0; - } - --static void pmacpic_resume(void) -+static void pmacpic_resume(void *data) - { - int i; - -@@ -634,15 +634,19 @@ static void pmacpic_resume(void) - pmac_unmask_irq(irq_get_irq_data(i)); - } - --static struct syscore_ops pmacpic_syscore_ops = { -+static const struct syscore_ops pmacpic_syscore_ops = { - .suspend = pmacpic_suspend, - .resume = pmacpic_resume, - }; - -+static struct syscore pmacpic_syscore = { -+ .ops = &pmacpic_syscore_ops, -+}; -+ - static int __init init_pmacpic_syscore(void) - { - if (pmac_irq_hw[0]) -- register_syscore_ops(&pmacpic_syscore_ops); -+ register_syscore(&pmacpic_syscore); - return 0; - } - -diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c -index 217cea150987..7ed07232a69a 100644 ---- a/arch/powerpc/sysdev/fsl_lbc.c -+++ b/arch/powerpc/sysdev/fsl_lbc.c -@@ -350,7 +350,7 @@ static int fsl_lbc_ctrl_probe(struct platform_device *dev) - #ifdef CONFIG_SUSPEND - - /* save lbc registers */ --static int fsl_lbc_syscore_suspend(void) -+static int fsl_lbc_syscore_suspend(void *data) - { - struct fsl_lbc_ctrl *ctrl; - struct fsl_lbc_regs __iomem *lbc; -@@ -374,7 +374,7 @@ static int fsl_lbc_syscore_suspend(void) - } - - /* restore lbc registers */ --static void fsl_lbc_syscore_resume(void) -+static void fsl_lbc_syscore_resume(void *data) - { - struct fsl_lbc_ctrl *ctrl; - struct fsl_lbc_regs __iomem *lbc; -@@ -408,10 +408,14 @@ static const struct of_device_id fsl_lbc_match[] = { - }; - - #ifdef CONFIG_SUSPEND --static struct syscore_ops lbc_syscore_pm_ops = { -+static const struct syscore_ops lbc_syscore_pm_ops = { - .suspend = fsl_lbc_syscore_suspend, - .resume = fsl_lbc_syscore_resume, - }; -+ -+static struct syscore lbc_syscore_pm = { -+ .ops = &lbc_syscore_pm_ops, -+}; - #endif - - static struct platform_driver fsl_lbc_ctrl_driver = { -@@ -425,7 +429,7 @@ static struct platform_driver fsl_lbc_ctrl_driver = { - static int __init fsl_lbc_init(void) - { - #ifdef CONFIG_SUSPEND -- register_syscore_ops(&lbc_syscore_pm_ops); -+ register_syscore(&lbc_syscore_pm); - #endif - return platform_driver_register(&fsl_lbc_ctrl_driver); - } -diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c -index ef7707ea0db7..4e501654cb41 100644 ---- a/arch/powerpc/sysdev/fsl_pci.c -+++ b/arch/powerpc/sysdev/fsl_pci.c -@@ -1258,7 +1258,7 @@ static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) - send_pme_turnoff_message(hose); - } - --static int fsl_pci_syscore_suspend(void) -+static int fsl_pci_syscore_suspend(void *data) - { - struct pci_controller *hose, *tmp; - -@@ -1291,7 +1291,7 @@ static void fsl_pci_syscore_do_resume(struct pci_controller *hose) - setup_pci_atmu(hose); - } - --static void fsl_pci_syscore_resume(void) -+static void fsl_pci_syscore_resume(void *data) - { - struct pci_controller *hose, *tmp; - -@@ -1299,10 +1299,14 @@ static void fsl_pci_syscore_resume(void) - fsl_pci_syscore_do_resume(hose); - } - --static struct syscore_ops pci_syscore_pm_ops = { -+static const struct syscore_ops pci_syscore_pm_ops = { - .suspend = fsl_pci_syscore_suspend, - .resume = fsl_pci_syscore_resume, - }; -+ -+static struct syscore pci_syscore_pm = { -+ .ops = &pci_syscore_pm_ops, -+}; - #endif - - void fsl_pcibios_fixup_phb(struct pci_controller *phb) -@@ -1359,7 +1363,7 @@ static struct platform_driver fsl_pci_driver = { - static int __init fsl_pci_init(void) - { - #ifdef CONFIG_PM_SLEEP -- register_syscore_ops(&pci_syscore_pm_ops); -+ register_syscore(&pci_syscore_pm); - #endif - return platform_driver_register(&fsl_pci_driver); - } -diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c -index 70be2105865d..290ba8427239 100644 ---- a/arch/powerpc/sysdev/ipic.c -+++ b/arch/powerpc/sysdev/ipic.c -@@ -817,7 +817,7 @@ static struct { - u32 sercr; - } ipic_saved_state; - --static int ipic_suspend(void) -+static int ipic_suspend(void *data) - { - struct ipic *ipic = primary_ipic; - -@@ -848,7 +848,7 @@ static int ipic_suspend(void) - return 0; - } - --static void ipic_resume(void) -+static void ipic_resume(void *data) - { - struct ipic *ipic = primary_ipic; - -@@ -870,18 +870,22 @@ static void ipic_resume(void) - #define ipic_resume NULL - #endif - --static struct syscore_ops ipic_syscore_ops = { -+static const struct syscore_ops ipic_syscore_ops = { - .suspend = ipic_suspend, - .resume = ipic_resume, - }; - -+static struct syscore ipic_syscore = { -+ .ops = &ipic_syscore_ops, -+}; -+ - static int __init init_ipic_syscore(void) - { - if (!primary_ipic || !primary_ipic->regs) - return -ENODEV; - - printk(KERN_DEBUG "Registering ipic system core operations\n"); -- register_syscore_ops(&ipic_syscore_ops); -+ register_syscore(&ipic_syscore); - - return 0; - } -diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c -index ad7310bba00b..67e51998d1ae 100644 ---- a/arch/powerpc/sysdev/mpic.c -+++ b/arch/powerpc/sysdev/mpic.c -@@ -1944,7 +1944,7 @@ static void mpic_suspend_one(struct mpic *mpic) - } - } - --static int mpic_suspend(void) -+static int mpic_suspend(void *data) - { - struct mpic *mpic = mpics; - -@@ -1986,7 +1986,7 @@ static void mpic_resume_one(struct mpic *mpic) - } /* end for loop */ - } - --static void mpic_resume(void) -+static void mpic_resume(void *data) - { - struct mpic *mpic = mpics; - -@@ -1996,19 +1996,23 @@ static void mpic_resume(void) - } - } - --static struct syscore_ops mpic_syscore_ops = { -+static const struct syscore_ops mpic_syscore_ops = { - .resume = mpic_resume, - .suspend = mpic_suspend, - }; - -+static struct syscore mpic_syscore = { -+ .ops = &mpic_syscore_ops, -+}; -+ - static int mpic_init_sys(void) - { - int rc; - -- register_syscore_ops(&mpic_syscore_ops); -+ register_syscore(&mpic_syscore); - rc = subsys_system_register(&mpic_subsys, NULL); - if (rc) { -- unregister_syscore_ops(&mpic_syscore_ops); -+ unregister_syscore(&mpic_syscore); - pr_err("mpic: Failed to register subsystem!\n"); - return rc; - } -diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c -index 7166e2e0baaf..60f5b3934b51 100644 ---- a/arch/powerpc/sysdev/mpic_timer.c -+++ b/arch/powerpc/sysdev/mpic_timer.c -@@ -519,7 +519,7 @@ static void __init timer_group_init(struct device_node *np) - kfree(priv); - } - --static void mpic_timer_resume(void) -+static void mpic_timer_resume(void *data) - { - struct timer_group_priv *priv; - -@@ -535,10 +535,14 @@ static const struct of_device_id mpic_timer_ids[] = { - {}, - }; - --static struct syscore_ops mpic_timer_syscore_ops = { -+static const struct syscore_ops mpic_timer_syscore_ops = { - .resume = mpic_timer_resume, - }; - -+static struct syscore mpic_timer_syscore = { -+ .ops = &mpic_timer_syscore_ops, -+}; -+ - static int __init mpic_timer_init(void) - { - struct device_node *np = NULL; -@@ -546,7 +550,7 @@ static int __init mpic_timer_init(void) - for_each_matching_node(np, mpic_timer_ids) - timer_group_init(np); - -- register_syscore_ops(&mpic_timer_syscore_ops); -+ register_syscore(&mpic_timer_syscore); - - if (list_empty(&timer_group_list)) - return -ENODEV; -diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c -index 68eb7cc6e564..482eec50f404 100644 ---- a/arch/sh/mm/pmb.c -+++ b/arch/sh/mm/pmb.c -@@ -857,7 +857,7 @@ static int __init pmb_debugfs_init(void) - subsys_initcall(pmb_debugfs_init); - - #ifdef CONFIG_PM --static void pmb_syscore_resume(void) -+static void pmb_syscore_resume(void *data) - { - struct pmb_entry *pmbe; - int i; -@@ -874,13 +874,17 @@ static void pmb_syscore_resume(void) - read_unlock(&pmb_rwlock); - } - --static struct syscore_ops pmb_syscore_ops = { -+static const struct syscore_ops pmb_syscore_ops = { - .resume = pmb_syscore_resume, - }; - -+static struct syscore pmb_syscore = { -+ .ops = &pmb_syscore_ops, -+}; -+ - static int __init pmb_sysdev_init(void) - { -- register_syscore_ops(&pmb_syscore_ops); -+ register_syscore(&pmb_syscore); - return 0; - } - subsys_initcall(pmb_sysdev_init); -diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c -index 56918cd91115..23d834e7b565 100644 ---- a/arch/x86/events/amd/ibs.c -+++ b/arch/x86/events/amd/ibs.c -@@ -1719,26 +1719,30 @@ static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu) - - #ifdef CONFIG_PM - --static int perf_ibs_suspend(void) -+static int perf_ibs_suspend(void *data) - { - clear_APIC_ibs(); - return 0; - } - --static void perf_ibs_resume(void) -+static void perf_ibs_resume(void *data) - { - ibs_eilvt_setup(); - setup_APIC_ibs(); - } - --static struct syscore_ops perf_ibs_syscore_ops = { -+static const struct syscore_ops perf_ibs_syscore_ops = { - .resume = perf_ibs_resume, - .suspend = perf_ibs_suspend, - }; - -+static struct syscore perf_ibs_syscore = { -+ .ops = &perf_ibs_syscore_ops, -+}; -+ - static void perf_ibs_pm_init(void) - { -- register_syscore_ops(&perf_ibs_syscore_ops); -+ register_syscore(&perf_ibs_syscore); - } - - #else -diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c -index e890fd37e9c2..085ef4f2e73a 100644 ---- a/arch/x86/hyperv/hv_init.c -+++ b/arch/x86/hyperv/hv_init.c -@@ -351,7 +351,7 @@ static int __init hv_pci_init(void) - return 1; - } - --static int hv_suspend(void) -+static int hv_suspend(void *data) - { - union hv_x64_msr_hypercall_contents hypercall_msr; - int ret; -@@ -378,7 +378,7 @@ static int hv_suspend(void) - return ret; - } - --static void hv_resume(void) -+static void hv_resume(void *data) - { - union hv_x64_msr_hypercall_contents hypercall_msr; - int ret; -@@ -405,11 +405,15 @@ static void hv_resume(void) - } - - /* Note: when the ops are called, only CPU0 is online and IRQs are disabled. */ --static struct syscore_ops hv_syscore_ops = { -+static const struct syscore_ops hv_syscore_ops = { - .suspend = hv_suspend, - .resume = hv_resume, - }; - -+static struct syscore hv_syscore = { -+ .ops = &hv_syscore_ops, -+}; -+ - static void (* __initdata old_setup_percpu_clockev)(void); - - static void __init hv_stimer_setup_percpu_clockev(void) -@@ -569,7 +573,7 @@ void __init hyperv_init(void) - - x86_init.pci.arch_init = hv_pci_init; - -- register_syscore_ops(&hv_syscore_ops); -+ register_syscore(&hv_syscore); - - if (ms_hyperv.priv_high & HV_ACCESS_PARTITION_ID) - hv_get_partition_id(); -diff --git a/arch/x86/kernel/amd_gart_64.c b/arch/x86/kernel/amd_gart_64.c -index 3485d419c2f5..e6e68a31634c 100644 ---- a/arch/x86/kernel/amd_gart_64.c -+++ b/arch/x86/kernel/amd_gart_64.c -@@ -591,7 +591,7 @@ static void gart_fixup_northbridges(void) - } - } - --static void gart_resume(void) -+static void gart_resume(void *data) - { - pr_info("PCI-DMA: Resuming GART IOMMU\n"); - -@@ -600,11 +600,15 @@ static void gart_resume(void) - enable_gart_translations(); - } - --static struct syscore_ops gart_syscore_ops = { -+static const struct syscore_ops gart_syscore_ops = { - .resume = gart_resume, - - }; - -+static struct syscore gart_syscore = { -+ .ops = &gart_syscore_ops, -+}; -+ - /* - * Private Northbridge GATT initialization in case we cannot use the - * AGP driver for some reason. -@@ -650,7 +654,7 @@ static __init int init_amd_gatt(struct agp_kern_info *info) - - agp_gatt_table = gatt; - -- register_syscore_ops(&gart_syscore_ops); -+ register_syscore(&gart_syscore); - - flush_gart(); - -diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c -index aa1b0ef5e931..a4431f0d2580 100644 ---- a/arch/x86/kernel/apic/apic.c -+++ b/arch/x86/kernel/apic/apic.c -@@ -2382,7 +2382,7 @@ static struct { - unsigned int apic_cmci; - } apic_pm_state; - --static int lapic_suspend(void) -+static int lapic_suspend(void *data) - { - unsigned long flags; - int maxlvt; -@@ -2430,7 +2430,7 @@ static int lapic_suspend(void) - return 0; - } - --static void lapic_resume(void) -+static void lapic_resume(void *data) - { - unsigned int l, h; - unsigned long flags; -@@ -2510,11 +2510,15 @@ static void lapic_resume(void) - * are needed on every CPU up until machine_halt/restart/poweroff. - */ - --static struct syscore_ops lapic_syscore_ops = { -+static const struct syscore_ops lapic_syscore_ops = { - .resume = lapic_resume, - .suspend = lapic_suspend, - }; - -+static struct syscore lapic_syscore = { -+ .ops = &lapic_syscore_ops, -+}; -+ - static void apic_pm_activate(void) - { - apic_pm_state.active = 1; -@@ -2524,7 +2528,7 @@ static int __init init_lapic_sysfs(void) - { - /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ - if (boot_cpu_has(X86_FEATURE_APIC)) -- register_syscore_ops(&lapic_syscore_ops); -+ register_syscore(&lapic_syscore); - - return 0; - } -diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c -index 5ba2feb2c04c..84e200662ce6 100644 ---- a/arch/x86/kernel/apic/io_apic.c -+++ b/arch/x86/kernel/apic/io_apic.c -@@ -2308,7 +2308,12 @@ static void resume_ioapic_id(int ioapic_idx) - } - } - --static void ioapic_resume(void) -+static int ioapic_suspend(void *data) -+{ -+ return save_ioapic_entries(); -+} -+ -+static void ioapic_resume(void *data) - { - int ioapic_idx; - -@@ -2318,14 +2323,18 @@ static void ioapic_resume(void) - restore_ioapic_entries(); - } - --static struct syscore_ops ioapic_syscore_ops = { -- .suspend = save_ioapic_entries, -+static const struct syscore_ops ioapic_syscore_ops = { -+ .suspend = ioapic_suspend, - .resume = ioapic_resume, - }; - -+static struct syscore ioapic_syscore = { -+ .ops = &ioapic_syscore_ops, -+}; -+ - static int __init ioapic_init_ops(void) - { -- register_syscore_ops(&ioapic_syscore_ops); -+ register_syscore(&ioapic_syscore); - - return 0; - } -diff --git a/arch/x86/kernel/cpu/aperfmperf.c b/arch/x86/kernel/cpu/aperfmperf.c -index a315b0627dfb..7ffc78d5ebf2 100644 ---- a/arch/x86/kernel/cpu/aperfmperf.c -+++ b/arch/x86/kernel/cpu/aperfmperf.c -@@ -37,7 +37,7 @@ static DEFINE_PER_CPU_SHARED_ALIGNED(struct aperfmperf, cpu_samples) = { - .seq = SEQCNT_ZERO(cpu_samples.seq) - }; - --static void init_counter_refs(void) -+static void init_counter_refs(void *data) - { - u64 aperf, mperf; - -@@ -289,16 +289,20 @@ static bool __init intel_set_max_freq_ratio(void) - } - - #ifdef CONFIG_PM_SLEEP --static struct syscore_ops freq_invariance_syscore_ops = { -+static const struct syscore_ops freq_invariance_syscore_ops = { - .resume = init_counter_refs, - }; - --static void register_freq_invariance_syscore_ops(void) -+static struct syscore freq_invariance_syscore = { -+ .ops = &freq_invariance_syscore_ops, -+}; -+ -+static void register_freq_invariance_syscore(void) - { -- register_syscore_ops(&freq_invariance_syscore_ops); -+ register_syscore(&freq_invariance_syscore); - } - #else --static inline void register_freq_invariance_syscore_ops(void) {} -+static inline void register_freq_invariance_syscore(void) {} - #endif - - static void freq_invariance_enable(void) -@@ -308,7 +312,7 @@ static void freq_invariance_enable(void) - return; - } - static_branch_enable_cpuslocked(&arch_scale_freq_key); -- register_freq_invariance_syscore_ops(); -+ register_freq_invariance_syscore(); - pr_info("Estimated ratio of average max frequency by base frequency (times 1024): %llu\n", arch_max_freq_ratio); - } - -@@ -535,7 +539,7 @@ static int __init bp_init_aperfmperf(void) - if (!cpu_feature_enabled(X86_FEATURE_APERFMPERF)) - return 0; - -- init_counter_refs(); -+ init_counter_refs(NULL); - bp_init_freq_invariance(); - return 0; - } -@@ -544,5 +548,5 @@ early_initcall(bp_init_aperfmperf); - void ap_init_aperfmperf(void) - { - if (cpu_feature_enabled(X86_FEATURE_APERFMPERF)) -- init_counter_refs(); -+ init_counter_refs(NULL); - } -diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c -index bc7671f920a7..2c56f8730f59 100644 ---- a/arch/x86/kernel/cpu/intel_epb.c -+++ b/arch/x86/kernel/cpu/intel_epb.c -@@ -75,7 +75,7 @@ static u8 energ_perf_values[] = { - [EPB_INDEX_POWERSAVE] = ENERGY_PERF_BIAS_POWERSAVE, - }; - --static int intel_epb_save(void) -+static int intel_epb_save(void *data) - { - u64 epb; - -@@ -89,7 +89,7 @@ static int intel_epb_save(void) - return 0; - } - --static void intel_epb_restore(void) -+static void intel_epb_restore(void *data) - { - u64 val = this_cpu_read(saved_epb); - u64 epb; -@@ -114,11 +114,15 @@ static void intel_epb_restore(void) - wrmsrq(MSR_IA32_ENERGY_PERF_BIAS, (epb & ~EPB_MASK) | val); - } - --static struct syscore_ops intel_epb_syscore_ops = { -+static const struct syscore_ops intel_epb_syscore_ops = { - .suspend = intel_epb_save, - .resume = intel_epb_restore, - }; - -+static struct syscore intel_epb_syscore = { -+ .ops = &intel_epb_syscore_ops, -+}; -+ - static const char * const energy_perf_strings[] = { - [EPB_INDEX_PERFORMANCE] = "performance", - [EPB_INDEX_BALANCE_PERFORMANCE] = "balance-performance", -@@ -185,7 +189,7 @@ static int intel_epb_online(unsigned int cpu) - { - struct device *cpu_dev = get_cpu_device(cpu); - -- intel_epb_restore(); -+ intel_epb_restore(NULL); - if (!cpuhp_tasks_frozen) - sysfs_merge_group(&cpu_dev->kobj, &intel_epb_attr_group); - -@@ -199,7 +203,7 @@ static int intel_epb_offline(unsigned int cpu) - if (!cpuhp_tasks_frozen) - sysfs_unmerge_group(&cpu_dev->kobj, &intel_epb_attr_group); - -- intel_epb_save(); -+ intel_epb_save(NULL); - return 0; - } - -@@ -230,7 +234,7 @@ static __init int intel_epb_init(void) - if (ret < 0) - goto err_out_online; - -- register_syscore_ops(&intel_epb_syscore_ops); -+ register_syscore(&intel_epb_syscore); - return 0; - - err_out_online: -diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c -index 460e90a1a0b1..23bfbc7dfb8e 100644 ---- a/arch/x86/kernel/cpu/mce/core.c -+++ b/arch/x86/kernel/cpu/mce/core.c -@@ -2410,13 +2410,13 @@ static void vendor_disable_error_reporting(void) - mce_disable_error_reporting(); - } - --static int mce_syscore_suspend(void) -+static int mce_syscore_suspend(void *data) - { - vendor_disable_error_reporting(); - return 0; - } - --static void mce_syscore_shutdown(void) -+static void mce_syscore_shutdown(void *data) - { - vendor_disable_error_reporting(); - } -@@ -2426,7 +2426,7 @@ static void mce_syscore_shutdown(void) - * Only one CPU is active at this time, the others get re-added later using - * CPU hotplug: - */ --static void mce_syscore_resume(void) -+static void mce_syscore_resume(void *data) - { - __mcheck_cpu_init_generic(); - __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); -@@ -2434,12 +2434,16 @@ static void mce_syscore_resume(void) - cr4_set_bits(X86_CR4_MCE); - } - --static struct syscore_ops mce_syscore_ops = { -+static const struct syscore_ops mce_syscore_ops = { - .suspend = mce_syscore_suspend, - .shutdown = mce_syscore_shutdown, - .resume = mce_syscore_resume, - }; - -+static struct syscore mce_syscore = { -+ .ops = &mce_syscore_ops, -+}; -+ - /* - * mce_device: Sysfs support - */ -@@ -2840,7 +2844,7 @@ static __init int mcheck_init_device(void) - if (err < 0) - goto err_out_online; - -- register_syscore_ops(&mce_syscore_ops); -+ register_syscore(&mce_syscore); - - return 0; - -diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c -index 539edd6d6dc8..81aa079fad26 100644 ---- a/arch/x86/kernel/cpu/microcode/core.c -+++ b/arch/x86/kernel/cpu/microcode/core.c -@@ -812,8 +812,17 @@ void microcode_bsp_resume(void) - reload_early_microcode(cpu); - } - --static struct syscore_ops mc_syscore_ops = { -- .resume = microcode_bsp_resume, -+static void microcode_bsp_syscore_resume(void *data) -+{ -+ microcode_bsp_resume(); -+} -+ -+static const struct syscore_ops mc_syscore_ops = { -+ .resume = microcode_bsp_syscore_resume, -+}; -+ -+static struct syscore mc_syscore = { -+ .ops = &mc_syscore_ops, - }; - - static int mc_cpu_online(unsigned int cpu) -@@ -892,7 +901,7 @@ static int __init microcode_init(void) - } - } - -- register_syscore_ops(&mc_syscore_ops); -+ register_syscore(&mc_syscore); - cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", - mc_cpu_online, mc_cpu_down_prep); - -diff --git a/arch/x86/kernel/cpu/mtrr/legacy.c b/arch/x86/kernel/cpu/mtrr/legacy.c -index d25882fcf181..2415ffaaf02c 100644 ---- a/arch/x86/kernel/cpu/mtrr/legacy.c -+++ b/arch/x86/kernel/cpu/mtrr/legacy.c -@@ -41,7 +41,7 @@ struct mtrr_value { - - static struct mtrr_value *mtrr_value; - --static int mtrr_save(void) -+static int mtrr_save(void *data) - { - int i; - -@@ -56,7 +56,7 @@ static int mtrr_save(void) - return 0; - } - --static void mtrr_restore(void) -+static void mtrr_restore(void *data) - { - int i; - -@@ -69,11 +69,15 @@ static void mtrr_restore(void) - } - } - --static struct syscore_ops mtrr_syscore_ops = { -+static const struct syscore_ops mtrr_syscore_ops = { - .suspend = mtrr_save, - .resume = mtrr_restore, - }; - -+static struct syscore mtrr_syscore = { -+ .ops = &mtrr_syscore_ops, -+}; -+ - void mtrr_register_syscore(void) - { - mtrr_value = kcalloc(num_var_ranges, sizeof(*mtrr_value), GFP_KERNEL); -@@ -86,5 +90,5 @@ void mtrr_register_syscore(void) - * TBD: is there any system with such CPU which supports - * suspend/resume? If no, we should remove the code. - */ -- register_syscore_ops(&mtrr_syscore_ops); -+ register_syscore(&mtrr_syscore); - } -diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c -index 933fcd7ff250..e4a31c536642 100644 ---- a/arch/x86/kernel/cpu/umwait.c -+++ b/arch/x86/kernel/cpu/umwait.c -@@ -86,15 +86,19 @@ static int umwait_cpu_offline(unsigned int cpu) - * trust the firmware nor does it matter if the same value is written - * again. - */ --static void umwait_syscore_resume(void) -+static void umwait_syscore_resume(void *data) - { - umwait_update_control_msr(NULL); - } - --static struct syscore_ops umwait_syscore_ops = { -+static const struct syscore_ops umwait_syscore_ops = { - .resume = umwait_syscore_resume, - }; - -+static struct syscore umwait_syscore = { -+ .ops = &umwait_syscore_ops, -+}; -+ - /* sysfs interface */ - - /* -@@ -226,7 +230,7 @@ static int __init umwait_init(void) - return ret; - } - -- register_syscore_ops(&umwait_syscore_ops); -+ register_syscore(&umwait_syscore); - - /* - * Add umwait control interface. Ignore failure, so at least the -diff --git a/arch/x86/kernel/i8237.c b/arch/x86/kernel/i8237.c -index 2cd124ad9380..896d46b44284 100644 ---- a/arch/x86/kernel/i8237.c -+++ b/arch/x86/kernel/i8237.c -@@ -19,7 +19,7 @@ - * in asm/dma.h. - */ - --static void i8237A_resume(void) -+static void i8237A_resume(void *data) - { - unsigned long flags; - int i; -@@ -41,10 +41,14 @@ static void i8237A_resume(void) - release_dma_lock(flags); - } - --static struct syscore_ops i8237_syscore_ops = { -+static const struct syscore_ops i8237_syscore_ops = { - .resume = i8237A_resume, - }; - -+static struct syscore i8237_syscore = { -+ .ops = &i8237_syscore_ops, -+}; -+ - static int __init i8237A_init_ops(void) - { - /* -@@ -70,7 +74,7 @@ static int __init i8237A_init_ops(void) - if (x86_pnpbios_disabled() && dmi_get_bios_year() >= 2017) - return -ENODEV; - -- register_syscore_ops(&i8237_syscore_ops); -+ register_syscore(&i8237_syscore); - return 0; - } - device_initcall(i8237A_init_ops); -diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c -index 2bade73f49e3..f67063df6723 100644 ---- a/arch/x86/kernel/i8259.c -+++ b/arch/x86/kernel/i8259.c -@@ -247,19 +247,19 @@ static void save_ELCR(char *trigger) - trigger[1] = inb(PIC_ELCR2) & 0xDE; - } - --static void i8259A_resume(void) -+static void i8259A_resume(void *data) - { - init_8259A(i8259A_auto_eoi); - restore_ELCR(irq_trigger); - } - --static int i8259A_suspend(void) -+static int i8259A_suspend(void *data) - { - save_ELCR(irq_trigger); - return 0; - } - --static void i8259A_shutdown(void) -+static void i8259A_shutdown(void *data) - { - /* Put the i8259A into a quiescent state that - * the kernel initialization code can get it -@@ -269,12 +269,16 @@ static void i8259A_shutdown(void) - outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ - } - --static struct syscore_ops i8259_syscore_ops = { -+static const struct syscore_ops i8259_syscore_ops = { - .suspend = i8259A_suspend, - .resume = i8259A_resume, - .shutdown = i8259A_shutdown, - }; - -+static struct syscore i8259_syscore = { -+ .ops = &i8259_syscore_ops, -+}; -+ - static void mask_8259A(void) - { - unsigned long flags; -@@ -444,7 +448,7 @@ EXPORT_SYMBOL(legacy_pic); - static int __init i8259A_init_ops(void) - { - if (legacy_pic == &default_legacy_pic) -- register_syscore_ops(&i8259_syscore_ops); -+ register_syscore(&i8259_syscore); - - return 0; - } -diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c -index b67d7c59dca0..1500852ba03c 100644 ---- a/arch/x86/kernel/kvm.c -+++ b/arch/x86/kernel/kvm.c -@@ -720,7 +720,7 @@ static int kvm_cpu_down_prepare(unsigned int cpu) - - #endif - --static int kvm_suspend(void) -+static int kvm_suspend(void *data) - { - u64 val = 0; - -@@ -734,7 +734,7 @@ static int kvm_suspend(void) - return 0; - } - --static void kvm_resume(void) -+static void kvm_resume(void *data) - { - kvm_cpu_online(raw_smp_processor_id()); - -@@ -744,11 +744,15 @@ static void kvm_resume(void) - #endif - } - --static struct syscore_ops kvm_syscore_ops = { -+static const struct syscore_ops kvm_syscore_ops = { - .suspend = kvm_suspend, - .resume = kvm_resume, - }; - -+static struct syscore kvm_syscore = { -+ .ops = &kvm_syscore_ops, -+}; -+ - static void kvm_pv_guest_cpu_reboot(void *unused) - { - kvm_guest_cpu_offline(true); -@@ -858,7 +862,7 @@ static void __init kvm_guest_init(void) - machine_ops.crash_shutdown = kvm_crash_shutdown; - #endif - -- register_syscore_ops(&kvm_syscore_ops); -+ register_syscore(&kvm_syscore); - - /* - * Hard lockup detection is enabled by default. Disable it, as guests -diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c -index e4560b33b8ad..bed7dc85612e 100644 ---- a/drivers/acpi/pci_link.c -+++ b/drivers/acpi/pci_link.c -@@ -761,7 +761,7 @@ static int acpi_pci_link_resume(struct acpi_pci_link *link) - return 0; - } - --static void irqrouter_resume(void) -+static void irqrouter_resume(void *data) - { - struct acpi_pci_link *link; - -@@ -888,10 +888,14 @@ static int __init acpi_irq_balance_set(char *str) - - __setup("acpi_irq_balance", acpi_irq_balance_set); - --static struct syscore_ops irqrouter_syscore_ops = { -+static const struct syscore_ops irqrouter_syscore_ops = { - .resume = irqrouter_resume, - }; - -+static struct syscore irqrouter_syscore = { -+ .ops = &irqrouter_syscore_ops, -+}; -+ - void __init acpi_pci_link_init(void) - { - if (acpi_noirq) -@@ -904,6 +908,6 @@ void __init acpi_pci_link_init(void) - else - acpi_irq_balance = 0; - } -- register_syscore_ops(&irqrouter_syscore_ops); -+ register_syscore(&irqrouter_syscore); - acpi_scan_add_handler(&pci_link_handler); - } -diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c -index 0b7fa4a8c379..1b9579bb97c2 100644 ---- a/drivers/acpi/sleep.c -+++ b/drivers/acpi/sleep.c -@@ -892,13 +892,13 @@ bool acpi_s2idle_wakeup(void) - #ifdef CONFIG_PM_SLEEP - static u32 saved_bm_rld; - --static int acpi_save_bm_rld(void) -+static int acpi_save_bm_rld(void *data) - { - acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); - return 0; - } - --static void acpi_restore_bm_rld(void) -+static void acpi_restore_bm_rld(void *data) - { - u32 resumed_bm_rld = 0; - -@@ -909,14 +909,18 @@ static void acpi_restore_bm_rld(void) - acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); - } - --static struct syscore_ops acpi_sleep_syscore_ops = { -+static const struct syscore_ops acpi_sleep_syscore_ops = { - .suspend = acpi_save_bm_rld, - .resume = acpi_restore_bm_rld, - }; - -+static struct syscore acpi_sleep_syscore = { -+ .ops = &acpi_sleep_syscore_ops, -+}; -+ - static void acpi_sleep_syscore_init(void) - { -- register_syscore_ops(&acpi_sleep_syscore_ops); -+ register_syscore(&acpi_sleep_syscore); - } - #else - static inline void acpi_sleep_syscore_init(void) {} -diff --git a/drivers/base/firmware_loader/main.c b/drivers/base/firmware_loader/main.c -index 6942c62fa59d..8191dbab92c4 100644 ---- a/drivers/base/firmware_loader/main.c -+++ b/drivers/base/firmware_loader/main.c -@@ -1585,16 +1585,20 @@ static int fw_pm_notify(struct notifier_block *notify_block, - } - - /* stop caching firmware once syscore_suspend is reached */ --static int fw_suspend(void) -+static int fw_suspend(void *data) - { - fw_cache.state = FW_LOADER_NO_CACHE; - return 0; - } - --static struct syscore_ops fw_syscore_ops = { -+static const struct syscore_ops fw_syscore_ops = { - .suspend = fw_suspend, - }; - -+static struct syscore fw_syscore = { -+ .ops = &fw_syscore_ops, -+}; -+ - static int __init register_fw_pm_ops(void) - { - int ret; -@@ -1610,14 +1614,14 @@ static int __init register_fw_pm_ops(void) - if (ret) - return ret; - -- register_syscore_ops(&fw_syscore_ops); -+ register_syscore(&fw_syscore); - - return ret; - } - - static inline void unregister_fw_pm_ops(void) - { -- unregister_syscore_ops(&fw_syscore_ops); -+ unregister_syscore(&fw_syscore); - unregister_pm_notifier(&fw_cache.pm_notify); - } - #else -diff --git a/drivers/base/syscore.c b/drivers/base/syscore.c -index 13db1f78d2ce..483adb796654 100644 ---- a/drivers/base/syscore.c -+++ b/drivers/base/syscore.c -@@ -11,32 +11,32 @@ - #include - #include - --static LIST_HEAD(syscore_ops_list); --static DEFINE_MUTEX(syscore_ops_lock); -+static LIST_HEAD(syscore_list); -+static DEFINE_MUTEX(syscore_lock); - - /** -- * register_syscore_ops - Register a set of system core operations. -- * @ops: System core operations to register. -+ * register_syscore - Register a set of system core operations. -+ * @syscore: System core operations to register. - */ --void register_syscore_ops(struct syscore_ops *ops) -+void register_syscore(struct syscore *syscore) - { -- mutex_lock(&syscore_ops_lock); -- list_add_tail(&ops->node, &syscore_ops_list); -- mutex_unlock(&syscore_ops_lock); -+ mutex_lock(&syscore_lock); -+ list_add_tail(&syscore->node, &syscore_list); -+ mutex_unlock(&syscore_lock); - } --EXPORT_SYMBOL_GPL(register_syscore_ops); -+EXPORT_SYMBOL_GPL(register_syscore); - - /** -- * unregister_syscore_ops - Unregister a set of system core operations. -- * @ops: System core operations to unregister. -+ * unregister_syscore - Unregister a set of system core operations. -+ * @syscore: System core operations to unregister. - */ --void unregister_syscore_ops(struct syscore_ops *ops) -+void unregister_syscore(struct syscore *syscore) - { -- mutex_lock(&syscore_ops_lock); -- list_del(&ops->node); -- mutex_unlock(&syscore_ops_lock); -+ mutex_lock(&syscore_lock); -+ list_del(&syscore->node); -+ mutex_unlock(&syscore_lock); - } --EXPORT_SYMBOL_GPL(unregister_syscore_ops); -+EXPORT_SYMBOL_GPL(unregister_syscore); - - #ifdef CONFIG_PM_SLEEP - /** -@@ -46,7 +46,7 @@ EXPORT_SYMBOL_GPL(unregister_syscore_ops); - */ - int syscore_suspend(void) - { -- struct syscore_ops *ops; -+ struct syscore *syscore; - int ret = 0; - - trace_suspend_resume(TPS("syscore_suspend"), 0, true); -@@ -59,25 +59,27 @@ int syscore_suspend(void) - WARN_ONCE(!irqs_disabled(), - "Interrupts enabled before system core suspend.\n"); - -- list_for_each_entry_reverse(ops, &syscore_ops_list, node) -- if (ops->suspend) { -- pm_pr_dbg("Calling %pS\n", ops->suspend); -- ret = ops->suspend(); -+ list_for_each_entry_reverse(syscore, &syscore_list, node) -+ if (syscore->ops->suspend) { -+ pm_pr_dbg("Calling %pS\n", syscore->ops->suspend); -+ ret = syscore->ops->suspend(syscore->data); - if (ret) - goto err_out; - WARN_ONCE(!irqs_disabled(), -- "Interrupts enabled after %pS\n", ops->suspend); -+ "Interrupts enabled after %pS\n", -+ syscore->ops->suspend); - } - - trace_suspend_resume(TPS("syscore_suspend"), 0, false); - return 0; - - err_out: -- pr_err("PM: System core suspend callback %pS failed.\n", ops->suspend); -+ pr_err("PM: System core suspend callback %pS failed.\n", -+ syscore->ops->suspend); - -- list_for_each_entry_continue(ops, &syscore_ops_list, node) -- if (ops->resume) -- ops->resume(); -+ list_for_each_entry_continue(syscore, &syscore_list, node) -+ if (syscore->ops->resume) -+ syscore->ops->resume(syscore->data); - - return ret; - } -@@ -90,18 +92,19 @@ EXPORT_SYMBOL_GPL(syscore_suspend); - */ - void syscore_resume(void) - { -- struct syscore_ops *ops; -+ struct syscore *syscore; - - trace_suspend_resume(TPS("syscore_resume"), 0, true); - WARN_ONCE(!irqs_disabled(), - "Interrupts enabled before system core resume.\n"); - -- list_for_each_entry(ops, &syscore_ops_list, node) -- if (ops->resume) { -- pm_pr_dbg("Calling %pS\n", ops->resume); -- ops->resume(); -+ list_for_each_entry(syscore, &syscore_list, node) -+ if (syscore->ops->resume) { -+ pm_pr_dbg("Calling %pS\n", syscore->ops->resume); -+ syscore->ops->resume(syscore->data); - WARN_ONCE(!irqs_disabled(), -- "Interrupts enabled after %pS\n", ops->resume); -+ "Interrupts enabled after %pS\n", -+ syscore->ops->resume); - } - trace_suspend_resume(TPS("syscore_resume"), 0, false); - } -@@ -113,16 +116,17 @@ EXPORT_SYMBOL_GPL(syscore_resume); - */ - void syscore_shutdown(void) - { -- struct syscore_ops *ops; -+ struct syscore *syscore; - -- mutex_lock(&syscore_ops_lock); -+ mutex_lock(&syscore_lock); - -- list_for_each_entry_reverse(ops, &syscore_ops_list, node) -- if (ops->shutdown) { -+ list_for_each_entry_reverse(syscore, &syscore_list, node) -+ if (syscore->ops->shutdown) { - if (initcall_debug) -- pr_info("PM: Calling %pS\n", ops->shutdown); -- ops->shutdown(); -+ pr_info("PM: Calling %pS\n", -+ syscore->ops->shutdown); -+ syscore->ops->shutdown(syscore->data); - } - -- mutex_unlock(&syscore_ops_lock); -+ mutex_unlock(&syscore_lock); - } -diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c -index 00cb792bda18..dd94145c9b22 100644 ---- a/drivers/bus/mvebu-mbus.c -+++ b/drivers/bus/mvebu-mbus.c -@@ -1006,7 +1006,7 @@ static __init int mvebu_mbus_debugfs_init(void) - } - fs_initcall(mvebu_mbus_debugfs_init); - --static int mvebu_mbus_suspend(void) -+static int mvebu_mbus_suspend(void *data) - { - struct mvebu_mbus_state *s = &mbus_state; - int win; -@@ -1040,7 +1040,7 @@ static int mvebu_mbus_suspend(void) - return 0; - } - --static void mvebu_mbus_resume(void) -+static void mvebu_mbus_resume(void *data) - { - struct mvebu_mbus_state *s = &mbus_state; - int win; -@@ -1069,9 +1069,13 @@ static void mvebu_mbus_resume(void) - } - } - --static struct syscore_ops mvebu_mbus_syscore_ops = { -- .suspend = mvebu_mbus_suspend, -- .resume = mvebu_mbus_resume, -+static const struct syscore_ops mvebu_mbus_syscore_ops = { -+ .suspend = mvebu_mbus_suspend, -+ .resume = mvebu_mbus_resume, -+}; -+ -+static struct syscore mvebu_mbus_syscore = { -+ .ops = &mvebu_mbus_syscore_ops, - }; - - static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, -@@ -1118,7 +1122,7 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, - writel(UNIT_SYNC_BARRIER_ALL, - mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF); - -- register_syscore_ops(&mvebu_mbus_syscore_ops); -+ register_syscore(&mvebu_mbus_syscore); - - return 0; - } -diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c -index acf780a81589..2310f6f73162 100644 ---- a/drivers/clk/at91/pmc.c -+++ b/drivers/clk/at91/pmc.c -@@ -115,7 +115,7 @@ struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, - /* Address in SECURAM that say if we suspend to backup mode. */ - static void __iomem *at91_pmc_backup_suspend; - --static int at91_pmc_suspend(void) -+static int at91_pmc_suspend(void *data) - { - unsigned int backup; - -@@ -129,7 +129,7 @@ static int at91_pmc_suspend(void) - return clk_save_context(); - } - --static void at91_pmc_resume(void) -+static void at91_pmc_resume(void *data) - { - unsigned int backup; - -@@ -143,11 +143,15 @@ static void at91_pmc_resume(void) - clk_restore_context(); - } - --static struct syscore_ops pmc_syscore_ops = { -+static const struct syscore_ops pmc_syscore_ops = { - .suspend = at91_pmc_suspend, - .resume = at91_pmc_resume, - }; - -+static struct syscore pmc_syscore = { -+ .ops = &pmc_syscore_ops, -+}; -+ - static const struct of_device_id pmc_dt_ids[] = { - { .compatible = "atmel,sama5d2-pmc" }, - { .compatible = "microchip,sama7g5-pmc", }, -@@ -185,7 +189,7 @@ static int __init pmc_register_ops(void) - return -ENOMEM; - } - -- register_syscore_ops(&pmc_syscore_ops); -+ register_syscore(&pmc_syscore); - - return 0; - } -diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c -index 9e11f1c7c397..41eb38552a9c 100644 ---- a/drivers/clk/imx/clk-vf610.c -+++ b/drivers/clk/imx/clk-vf610.c -@@ -139,7 +139,7 @@ static struct clk * __init vf610_get_fixed_clock( - return clk; - }; - --static int vf610_clk_suspend(void) -+static int vf610_clk_suspend(void *data) - { - int i; - -@@ -156,7 +156,7 @@ static int vf610_clk_suspend(void) - return 0; - } - --static void vf610_clk_resume(void) -+static void vf610_clk_resume(void *data) - { - int i; - -@@ -171,11 +171,15 @@ static void vf610_clk_resume(void) - writel_relaxed(ccgr[i], CCM_CCGRx(i)); - } - --static struct syscore_ops vf610_clk_syscore_ops = { -+static const struct syscore_ops vf610_clk_syscore_ops = { - .suspend = vf610_clk_suspend, - .resume = vf610_clk_resume, - }; - -+static struct syscore vf610_clk_syscore = { -+ .ops = &vf610_clk_syscore_ops, -+}; -+ - static void __init vf610_clocks_init(struct device_node *ccm_node) - { - struct device_node *np; -@@ -462,7 +466,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clk[clks_init_on[i]]); - -- register_syscore_ops(&vf610_clk_syscore_ops); -+ register_syscore(&vf610_clk_syscore); - - /* Add the clocks to provider list */ - clk_data.clks = clk; -diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c -index 590e9c85cb25..94cee44c854f 100644 ---- a/drivers/clk/ingenic/jz4725b-cgu.c -+++ b/drivers/clk/ingenic/jz4725b-cgu.c -@@ -268,6 +268,6 @@ static void __init jz4725b_cgu_init(struct device_node *np) - if (retval) - pr_err("%s: failed to register CGU Clocks\n", __func__); - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init); -diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c -index 3e0a30574ebb..2def3aedc8dd 100644 ---- a/drivers/clk/ingenic/jz4740-cgu.c -+++ b/drivers/clk/ingenic/jz4740-cgu.c -@@ -266,6 +266,6 @@ static void __init jz4740_cgu_init(struct device_node *np) - if (retval) - pr_err("%s: failed to register CGU Clocks\n", __func__); - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init); -diff --git a/drivers/clk/ingenic/jz4755-cgu.c b/drivers/clk/ingenic/jz4755-cgu.c -index f2c2d848dab7..17cf5dcaece9 100644 ---- a/drivers/clk/ingenic/jz4755-cgu.c -+++ b/drivers/clk/ingenic/jz4755-cgu.c -@@ -337,7 +337,7 @@ static void __init jz4755_cgu_init(struct device_node *np) - if (retval) - pr_err("%s: failed to register CGU Clocks\n", __func__); - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - /* - * CGU has some children devices, this is useful for probing children devices -diff --git a/drivers/clk/ingenic/jz4760-cgu.c b/drivers/clk/ingenic/jz4760-cgu.c -index e407f00bd594..372fe4b07992 100644 ---- a/drivers/clk/ingenic/jz4760-cgu.c -+++ b/drivers/clk/ingenic/jz4760-cgu.c -@@ -436,7 +436,7 @@ static void __init jz4760_cgu_init(struct device_node *np) - if (retval) - pr_err("%s: failed to register CGU Clocks\n", __func__); - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - - /* We only probe via devicetree, no need for a platform driver */ -diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c -index 6ae1740367f9..58f1d3bad677 100644 ---- a/drivers/clk/ingenic/jz4770-cgu.c -+++ b/drivers/clk/ingenic/jz4770-cgu.c -@@ -456,7 +456,7 @@ static void __init jz4770_cgu_init(struct device_node *np) - if (retval) - pr_err("%s: failed to register CGU Clocks\n", __func__); - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - - /* We only probe via devicetree, no need for a platform driver */ -diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c -index 07e2f3c5c454..1e88aef7ac0f 100644 ---- a/drivers/clk/ingenic/jz4780-cgu.c -+++ b/drivers/clk/ingenic/jz4780-cgu.c -@@ -803,6 +803,6 @@ static void __init jz4780_cgu_init(struct device_node *np) - return; - } - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init); -diff --git a/drivers/clk/ingenic/pm.c b/drivers/clk/ingenic/pm.c -index 341752b640d2..206d5cf2872f 100644 ---- a/drivers/clk/ingenic/pm.c -+++ b/drivers/clk/ingenic/pm.c -@@ -15,7 +15,7 @@ - - static void __iomem * __maybe_unused ingenic_cgu_base; - --static int __maybe_unused ingenic_cgu_pm_suspend(void) -+static int __maybe_unused ingenic_cgu_pm_suspend(void *data) - { - u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); - -@@ -24,22 +24,26 @@ static int __maybe_unused ingenic_cgu_pm_suspend(void) - return 0; - } - --static void __maybe_unused ingenic_cgu_pm_resume(void) -+static void __maybe_unused ingenic_cgu_pm_resume(void *data) - { - u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); - - writel(val & ~LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR); - } - --static struct syscore_ops __maybe_unused ingenic_cgu_pm_ops = { -+static const struct syscore_ops __maybe_unused ingenic_cgu_pm_ops = { - .suspend = ingenic_cgu_pm_suspend, - .resume = ingenic_cgu_pm_resume, - }; - --void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu) -+static struct syscore __maybe_unused ingenic_cgu_pm = { -+ .ops = &ingenic_cgu_pm_ops, -+}; -+ -+void ingenic_cgu_register_syscore(struct ingenic_cgu *cgu) - { - if (IS_ENABLED(CONFIG_PM_SLEEP)) { - ingenic_cgu_base = cgu->base; -- register_syscore_ops(&ingenic_cgu_pm_ops); -+ register_syscore(&ingenic_cgu_pm); - } - } -diff --git a/drivers/clk/ingenic/pm.h b/drivers/clk/ingenic/pm.h -index fa7540407b6b..0dcb57dc64cb 100644 ---- a/drivers/clk/ingenic/pm.h -+++ b/drivers/clk/ingenic/pm.h -@@ -7,6 +7,6 @@ - - struct ingenic_cgu; - --void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu); -+void ingenic_cgu_register_syscore(struct ingenic_cgu *cgu); - - #endif /* DRIVERS_CLK_INGENIC_PM_H */ -diff --git a/drivers/clk/ingenic/tcu.c b/drivers/clk/ingenic/tcu.c -index 7d04ef40b7cf..bc6a51da2072 100644 ---- a/drivers/clk/ingenic/tcu.c -+++ b/drivers/clk/ingenic/tcu.c -@@ -455,7 +455,7 @@ static int __init ingenic_tcu_probe(struct device_node *np) - return ret; - } - --static int __maybe_unused tcu_pm_suspend(void) -+static int __maybe_unused tcu_pm_suspend(void *data) - { - struct ingenic_tcu *tcu = ingenic_tcu; - -@@ -465,7 +465,7 @@ static int __maybe_unused tcu_pm_suspend(void) - return 0; - } - --static void __maybe_unused tcu_pm_resume(void) -+static void __maybe_unused tcu_pm_resume(void *data) - { - struct ingenic_tcu *tcu = ingenic_tcu; - -@@ -473,11 +473,15 @@ static void __maybe_unused tcu_pm_resume(void) - clk_enable(tcu->clk); - } - --static struct syscore_ops __maybe_unused tcu_pm_ops = { -+static const struct syscore_ops __maybe_unused tcu_pm_ops = { - .suspend = tcu_pm_suspend, - .resume = tcu_pm_resume, - }; - -+static struct syscore __maybe_unused tcu_pm = { -+ .ops = &tcu_pm_ops, -+}; -+ - static void __init ingenic_tcu_init(struct device_node *np) - { - int ret = ingenic_tcu_probe(np); -@@ -486,7 +490,7 @@ static void __init ingenic_tcu_init(struct device_node *np) - pr_crit("Failed to initialize TCU clocks: %d\n", ret); - - if (IS_ENABLED(CONFIG_PM_SLEEP)) -- register_syscore_ops(&tcu_pm_ops); -+ register_syscore(&tcu_pm); - } - - CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init); -diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c -index d80886caf393..d89bdfb7c219 100644 ---- a/drivers/clk/ingenic/x1000-cgu.c -+++ b/drivers/clk/ingenic/x1000-cgu.c -@@ -556,7 +556,7 @@ static void __init x1000_cgu_init(struct device_node *np) - return; - } - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - /* - * CGU has some children devices, this is useful for probing children devices -diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c -index 0fd46e50a513..acf856e5009e 100644 ---- a/drivers/clk/ingenic/x1830-cgu.c -+++ b/drivers/clk/ingenic/x1830-cgu.c -@@ -463,7 +463,7 @@ static void __init x1830_cgu_init(struct device_node *np) - return; - } - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - /* - * CGU has some children devices, this is useful for probing children devices -diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c -index 785dbede4835..5adbbd91a6db 100644 ---- a/drivers/clk/mvebu/common.c -+++ b/drivers/clk/mvebu/common.c -@@ -215,22 +215,26 @@ static struct clk *clk_gating_get_src( - return ERR_PTR(-ENODEV); - } - --static int mvebu_clk_gating_suspend(void) -+static int mvebu_clk_gating_suspend(void *data) - { - ctrl->saved_reg = readl(ctrl->base); - return 0; - } - --static void mvebu_clk_gating_resume(void) -+static void mvebu_clk_gating_resume(void *data) - { - writel(ctrl->saved_reg, ctrl->base); - } - --static struct syscore_ops clk_gate_syscore_ops = { -+static const struct syscore_ops clk_gate_syscore_ops = { - .suspend = mvebu_clk_gating_suspend, - .resume = mvebu_clk_gating_resume, - }; - -+static struct syscore clk_gate_syscore = { -+ .ops = &clk_gate_syscore_ops, -+}; -+ - void __init mvebu_clk_gating_setup(struct device_node *np, - const struct clk_gating_soc_desc *desc) - { -@@ -284,7 +288,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, - - of_clk_add_provider(np, clk_gating_get_src, ctrl); - -- register_syscore_ops(&clk_gate_syscore_ops); -+ register_syscore(&clk_gate_syscore); - - return; - gates_out: -diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 0a1e017df7c6..9cf3e1e43b78 100644 ---- a/drivers/clk/rockchip/clk-rk3288.c -+++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -871,7 +871,7 @@ static const int rk3288_saved_cru_reg_ids[] = { - - static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)]; - --static int rk3288_clk_suspend(void) -+static int rk3288_clk_suspend(void *data) - { - int i, reg_id; - -@@ -906,7 +906,7 @@ static int rk3288_clk_suspend(void) - return 0; - } - --static void rk3288_clk_resume(void) -+static void rk3288_clk_resume(void *data) - { - int i, reg_id; - -@@ -923,11 +923,15 @@ static void rk3288_clk_shutdown(void) - writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON); - } - --static struct syscore_ops rk3288_clk_syscore_ops = { -+static const struct syscore_ops rk3288_clk_syscore_ops = { - .suspend = rk3288_clk_suspend, - .resume = rk3288_clk_resume, - }; - -+static struct syscore rk3288_clk_syscore = { -+ .ops = &rk3288_clk_syscore_ops, -+}; -+ - static void __init rk3288_common_init(struct device_node *np, - enum rk3288_variant soc) - { -@@ -976,7 +980,7 @@ static void __init rk3288_common_init(struct device_node *np, - - rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST, - rk3288_clk_shutdown); -- register_syscore_ops(&rk3288_clk_syscore_ops); -+ register_syscore(&rk3288_clk_syscore); - - rockchip_clk_of_add_provider(np, ctx); - } -diff --git a/drivers/clk/samsung/clk-s5pv210-audss.c b/drivers/clk/samsung/clk-s5pv210-audss.c -index b1fd8fac3a4c..c9fcb23de183 100644 ---- a/drivers/clk/samsung/clk-s5pv210-audss.c -+++ b/drivers/clk/samsung/clk-s5pv210-audss.c -@@ -36,7 +36,7 @@ static unsigned long reg_save[][2] = { - {ASS_CLK_GATE, 0}, - }; - --static int s5pv210_audss_clk_suspend(void) -+static int s5pv210_audss_clk_suspend(void *data) - { - int i; - -@@ -46,7 +46,7 @@ static int s5pv210_audss_clk_suspend(void) - return 0; - } - --static void s5pv210_audss_clk_resume(void) -+static void s5pv210_audss_clk_resume(void *data) - { - int i; - -@@ -54,10 +54,14 @@ static void s5pv210_audss_clk_resume(void) - writel(reg_save[i][1], reg_base + reg_save[i][0]); - } - --static struct syscore_ops s5pv210_audss_clk_syscore_ops = { -+static const struct syscore_ops s5pv210_audss_clk_syscore_ops = { - .suspend = s5pv210_audss_clk_suspend, - .resume = s5pv210_audss_clk_resume, - }; -+ -+static struct syscore s5pv210_audss_clk_syscore = { -+ .ops = &s5pv210_audss_clk_syscore_ops, -+}; - #endif /* CONFIG_PM_SLEEP */ - - /* register s5pv210_audss clocks */ -@@ -175,7 +179,7 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev) - } - - #ifdef CONFIG_PM_SLEEP -- register_syscore_ops(&s5pv210_audss_clk_syscore_ops); -+ register_syscore(&s5pv210_audss_clk_syscore); - #endif - - return 0; -diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c -index dbc9925ca8f4..c149ca6c2217 100644 ---- a/drivers/clk/samsung/clk.c -+++ b/drivers/clk/samsung/clk.c -@@ -271,7 +271,7 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, - } - - #ifdef CONFIG_PM_SLEEP --static int samsung_clk_suspend(void) -+static int samsung_clk_suspend(void *data) - { - struct samsung_clock_reg_cache *reg_cache; - -@@ -284,7 +284,7 @@ static int samsung_clk_suspend(void) - return 0; - } - --static void samsung_clk_resume(void) -+static void samsung_clk_resume(void *data) - { - struct samsung_clock_reg_cache *reg_cache; - -@@ -293,11 +293,15 @@ static void samsung_clk_resume(void) - reg_cache->rd_num); - } - --static struct syscore_ops samsung_clk_syscore_ops = { -+static const struct syscore_ops samsung_clk_syscore_ops = { - .suspend = samsung_clk_suspend, - .resume = samsung_clk_resume, - }; - -+static struct syscore samsung_clk_syscore = { -+ .ops = &samsung_clk_syscore_ops, -+}; -+ - void samsung_clk_extended_sleep_init(void __iomem *reg_base, - const unsigned long *rdump, - unsigned long nr_rdump, -@@ -316,7 +320,7 @@ void samsung_clk_extended_sleep_init(void __iomem *reg_base, - panic("could not allocate register dump storage.\n"); - - if (list_empty(&clock_reg_cache_list)) -- register_syscore_ops(&samsung_clk_syscore_ops); -+ register_syscore(&samsung_clk_syscore); - - reg_cache->reg_base = reg_base; - reg_cache->rd_num = nr_rdump; -diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c -index 412902f573b5..504d0ea997a5 100644 ---- a/drivers/clk/tegra/clk-tegra210.c -+++ b/drivers/clk/tegra/clk-tegra210.c -@@ -3444,7 +3444,7 @@ static void tegra210_disable_cpu_clock(u32 cpu) - static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx; - static u32 cpu_softrst_ctx[3]; - --static int tegra210_clk_suspend(void) -+static int tegra210_clk_suspend(void *data) - { - unsigned int i; - -@@ -3465,7 +3465,7 @@ static int tegra210_clk_suspend(void) - return 0; - } - --static void tegra210_clk_resume(void) -+static void tegra210_clk_resume(void *data) - { - unsigned int i; - -@@ -3523,13 +3523,17 @@ static void tegra210_cpu_clock_resume(void) - } - #endif - --static struct syscore_ops tegra_clk_syscore_ops = { -+static const struct syscore_ops tegra_clk_syscore_ops = { - #ifdef CONFIG_PM_SLEEP - .suspend = tegra210_clk_suspend, - .resume = tegra210_clk_resume, - #endif - }; - -+static struct syscore tegra_clk_syscore = { -+ .ops = &tegra_clk_syscore_ops, -+}; -+ - static struct tegra_cpu_car_ops tegra210_cpu_car_ops = { - .wait_for_reset = tegra210_wait_cpu_in_reset, - .disable_clock = tegra210_disable_cpu_clock, -@@ -3813,6 +3817,6 @@ static void __init tegra210_clock_init(struct device_node *np) - - tegra_cpu_car_ops = &tegra210_cpu_car_ops; - -- register_syscore_ops(&tegra_clk_syscore_ops); -+ register_syscore(&tegra_clk_syscore); - } - CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); -diff --git a/drivers/clocksource/timer-armada-370-xp.c b/drivers/clocksource/timer-armada-370-xp.c -index 54284c1c0651..f2b4cc40db93 100644 ---- a/drivers/clocksource/timer-armada-370-xp.c -+++ b/drivers/clocksource/timer-armada-370-xp.c -@@ -207,14 +207,14 @@ static int armada_370_xp_timer_dying_cpu(unsigned int cpu) - - static u32 timer0_ctrl_reg, timer0_local_ctrl_reg; - --static int armada_370_xp_timer_suspend(void) -+static int armada_370_xp_timer_suspend(void *data) - { - timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF); - timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF); - return 0; - } - --static void armada_370_xp_timer_resume(void) -+static void armada_370_xp_timer_resume(void *data) - { - writel(0xffffffff, timer_base + TIMER0_VAL_OFF); - writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); -@@ -222,11 +222,15 @@ static void armada_370_xp_timer_resume(void) - writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF); - } - --static struct syscore_ops armada_370_xp_timer_syscore_ops = { -+static const struct syscore_ops armada_370_xp_timer_syscore_ops = { - .suspend = armada_370_xp_timer_suspend, - .resume = armada_370_xp_timer_resume, - }; - -+static struct syscore armada_370_xp_timer_syscore = { -+ .ops = &armada_370_xp_timer_syscore_ops, -+}; -+ - static unsigned long armada_370_delay_timer_read(void) - { - return ~readl(timer_base + TIMER0_VAL_OFF); -@@ -324,7 +328,7 @@ static int __init armada_370_xp_timer_common_init(struct device_node *np) - return res; - } - -- register_syscore_ops(&armada_370_xp_timer_syscore_ops); -+ register_syscore(&armada_370_xp_timer_syscore); - - return 0; - } -diff --git a/drivers/cpuidle/cpuidle-psci.c b/drivers/cpuidle/cpuidle-psci.c -index b19bc60cc627..3372e1f90561 100644 ---- a/drivers/cpuidle/cpuidle-psci.c -+++ b/drivers/cpuidle/cpuidle-psci.c -@@ -177,26 +177,30 @@ static void psci_idle_syscore_switch(bool suspend) - } - } - --static int psci_idle_syscore_suspend(void) -+static int psci_idle_syscore_suspend(void *data) - { - psci_idle_syscore_switch(true); - return 0; - } - --static void psci_idle_syscore_resume(void) -+static void psci_idle_syscore_resume(void *data) - { - psci_idle_syscore_switch(false); - } - --static struct syscore_ops psci_idle_syscore_ops = { -+static const struct syscore_ops psci_idle_syscore_ops = { - .suspend = psci_idle_syscore_suspend, - .resume = psci_idle_syscore_resume, - }; - -+static struct syscore psci_idle_syscore = { -+ .ops = &psci_idle_syscore_ops, -+}; -+ - static void psci_idle_init_syscore(void) - { - if (psci_cpuidle_use_syscore) -- register_syscore_ops(&psci_idle_syscore_ops); -+ register_syscore(&psci_idle_syscore); - } - - static void psci_idle_init_cpuhp(void) -diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c -index 441ba95b38cf..647b6f4861b7 100644 ---- a/drivers/gpio/gpio-mxc.c -+++ b/drivers/gpio/gpio-mxc.c -@@ -675,7 +675,7 @@ static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { - RUNTIME_PM_OPS(mxc_gpio_runtime_suspend, mxc_gpio_runtime_resume, NULL) - }; - --static int mxc_gpio_syscore_suspend(void) -+static int mxc_gpio_syscore_suspend(void *data) - { - struct mxc_gpio_port *port; - int ret; -@@ -692,7 +692,7 @@ static int mxc_gpio_syscore_suspend(void) - return 0; - } - --static void mxc_gpio_syscore_resume(void) -+static void mxc_gpio_syscore_resume(void *data) - { - struct mxc_gpio_port *port; - int ret; -@@ -709,11 +709,15 @@ static void mxc_gpio_syscore_resume(void) - } - } - --static struct syscore_ops mxc_gpio_syscore_ops = { -+static const struct syscore_ops mxc_gpio_syscore_ops = { - .suspend = mxc_gpio_syscore_suspend, - .resume = mxc_gpio_syscore_resume, - }; - -+static struct syscore mxc_gpio_syscore = { -+ .ops = &mxc_gpio_syscore_ops, -+}; -+ - static struct platform_driver mxc_gpio_driver = { - .driver = { - .name = "gpio-mxc", -@@ -726,7 +730,7 @@ static struct platform_driver mxc_gpio_driver = { - - static int __init gpio_mxc_init(void) - { -- register_syscore_ops(&mxc_gpio_syscore_ops); -+ register_syscore(&mxc_gpio_syscore); - - return platform_driver_register(&mxc_gpio_driver); - } -diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c -index fa22f3faa163..664cf1eef494 100644 ---- a/drivers/gpio/gpio-pxa.c -+++ b/drivers/gpio/gpio-pxa.c -@@ -747,7 +747,7 @@ static int __init pxa_gpio_dt_init(void) - device_initcall(pxa_gpio_dt_init); - - #ifdef CONFIG_PM --static int pxa_gpio_suspend(void) -+static int pxa_gpio_suspend(void *data) - { - struct pxa_gpio_chip *pchip = pxa_gpio_chip; - struct pxa_gpio_bank *c; -@@ -768,7 +768,7 @@ static int pxa_gpio_suspend(void) - return 0; - } - --static void pxa_gpio_resume(void) -+static void pxa_gpio_resume(void *data) - { - struct pxa_gpio_chip *pchip = pxa_gpio_chip; - struct pxa_gpio_bank *c; -@@ -792,14 +792,18 @@ static void pxa_gpio_resume(void) - #define pxa_gpio_resume NULL - #endif - --static struct syscore_ops pxa_gpio_syscore_ops = { -+static const struct syscore_ops pxa_gpio_syscore_ops = { - .suspend = pxa_gpio_suspend, - .resume = pxa_gpio_resume, - }; - -+static struct syscore pxa_gpio_syscore = { -+ .ops = &pxa_gpio_syscore_ops, -+}; -+ - static int __init pxa_gpio_sysinit(void) - { -- register_syscore_ops(&pxa_gpio_syscore_ops); -+ register_syscore(&pxa_gpio_syscore); - return 0; - } - postcore_initcall(pxa_gpio_sysinit); -diff --git a/drivers/gpio/gpio-sa1100.c b/drivers/gpio/gpio-sa1100.c -index 7f6a62f5d1ee..1938ffa2f4f3 100644 ---- a/drivers/gpio/gpio-sa1100.c -+++ b/drivers/gpio/gpio-sa1100.c -@@ -256,7 +256,7 @@ static void sa1100_gpio_handler(struct irq_desc *desc) - } while (mask); - } - --static int sa1100_gpio_suspend(void) -+static int sa1100_gpio_suspend(void *data) - { - struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip; - -@@ -275,19 +275,23 @@ static int sa1100_gpio_suspend(void) - return 0; - } - --static void sa1100_gpio_resume(void) -+static void sa1100_gpio_resume(void *data) - { - sa1100_update_edge_regs(&sa1100_gpio_chip); - } - --static struct syscore_ops sa1100_gpio_syscore_ops = { -+static const struct syscore_ops sa1100_gpio_syscore_ops = { - .suspend = sa1100_gpio_suspend, - .resume = sa1100_gpio_resume, - }; - -+static struct syscore sa1100_gpio_syscore = { -+ .ops = &sa1100_gpio_syscore_ops, -+}; -+ - static int __init sa1100_gpio_init_devicefs(void) - { -- register_syscore_ops(&sa1100_gpio_syscore_ops); -+ register_syscore(&sa1100_gpio_syscore); - return 0; - } - -diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c -index 3ab62277b6be..7000e2a5511f 100644 ---- a/drivers/hv/vmbus_drv.c -+++ b/drivers/hv/vmbus_drv.c -@@ -2861,7 +2861,7 @@ static void hv_crash_handler(struct pt_regs *regs) - hv_synic_disable_regs(cpu); - }; - --static int hv_synic_suspend(void) -+static int hv_synic_suspend(void *data) - { - /* - * When we reach here, all the non-boot CPUs have been offlined. -@@ -2888,7 +2888,7 @@ static int hv_synic_suspend(void) - return 0; - } - --static void hv_synic_resume(void) -+static void hv_synic_resume(void *data) - { - hv_synic_enable_regs(0); - -@@ -2900,11 +2900,15 @@ static void hv_synic_resume(void) - } - - /* The callbacks run only on CPU0, with irqs_disabled. */ --static struct syscore_ops hv_synic_syscore_ops = { -+static const struct syscore_ops hv_synic_syscore_ops = { - .suspend = hv_synic_suspend, - .resume = hv_synic_resume, - }; - -+static struct syscore hv_synic_syscore = { -+ .ops = &hv_synic_syscore_ops, -+}; -+ - static int __init hv_acpi_init(void) - { - int ret; -@@ -2947,7 +2951,7 @@ static int __init hv_acpi_init(void) - hv_setup_kexec_handler(hv_kexec_handler); - hv_setup_crash_handler(hv_crash_handler); - -- register_syscore_ops(&hv_synic_syscore_ops); -+ register_syscore(&hv_synic_syscore); - - return 0; - -@@ -2961,7 +2965,7 @@ static void __exit vmbus_exit(void) - { - int cpu; - -- unregister_syscore_ops(&hv_synic_syscore_ops); -+ unregister_syscore(&hv_synic_syscore); - - hv_remove_kexec_handler(); - hv_remove_crash_handler(); -diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c -index 76efd74124b3..4aa09660804b 100644 ---- a/drivers/iommu/amd/init.c -+++ b/drivers/iommu/amd/init.c -@@ -3050,7 +3050,7 @@ static void disable_iommus(void) - * disable suspend until real resume implemented - */ - --static void amd_iommu_resume(void) -+static void amd_iommu_resume(void *data) - { - struct amd_iommu *iommu; - -@@ -3064,7 +3064,7 @@ static void amd_iommu_resume(void) - amd_iommu_enable_interrupts(); - } - --static int amd_iommu_suspend(void) -+static int amd_iommu_suspend(void *data) - { - /* disable IOMMUs to go out of the way for BIOS */ - disable_iommus(); -@@ -3072,11 +3072,15 @@ static int amd_iommu_suspend(void) - return 0; - } - --static struct syscore_ops amd_iommu_syscore_ops = { -+static const struct syscore_ops amd_iommu_syscore_ops = { - .suspend = amd_iommu_suspend, - .resume = amd_iommu_resume, - }; - -+static struct syscore amd_iommu_syscore = { -+ .ops = &amd_iommu_syscore_ops, -+}; -+ - static void __init free_iommu_resources(void) - { - free_iommu_all(); -@@ -3421,7 +3425,7 @@ static int __init state_next(void) - init_state = IOMMU_ENABLED; - break; - case IOMMU_ENABLED: -- register_syscore_ops(&amd_iommu_syscore_ops); -+ register_syscore(&amd_iommu_syscore); - iommu_snp_enable(); - ret = amd_iommu_init_pci(); - init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; -@@ -3524,12 +3528,12 @@ int __init amd_iommu_enable(void) - - void amd_iommu_disable(void) - { -- amd_iommu_suspend(); -+ amd_iommu_suspend(NULL); - } - - int amd_iommu_reenable(int mode) - { -- amd_iommu_resume(); -+ amd_iommu_resume(NULL); - - return 0; - } -diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c -index 79676188f60f..3d1cacad559b 100644 ---- a/drivers/iommu/intel/iommu.c -+++ b/drivers/iommu/intel/iommu.c -@@ -2305,7 +2305,7 @@ static void iommu_flush_all(void) - } - } - --static int iommu_suspend(void) -+static int iommu_suspend(void *data) - { - struct dmar_drhd_unit *drhd; - struct intel_iommu *iommu = NULL; -@@ -2332,7 +2332,7 @@ static int iommu_suspend(void) - return 0; - } - --static void iommu_resume(void) -+static void iommu_resume(void *data) - { - struct dmar_drhd_unit *drhd; - struct intel_iommu *iommu = NULL; -@@ -2363,14 +2363,18 @@ static void iommu_resume(void) - } - } - --static struct syscore_ops iommu_syscore_ops = { -+static const struct syscore_ops iommu_syscore_ops = { - .resume = iommu_resume, - .suspend = iommu_suspend, - }; - -+static struct syscore iommu_syscore = { -+ .ops = &iommu_syscore_ops, -+}; -+ - static void __init init_iommu_pm_ops(void) - { -- register_syscore_ops(&iommu_syscore_ops); -+ register_syscore(&iommu_syscore); - } - - #else -diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c -index e7dfcf0cda43..495848442b35 100644 ---- a/drivers/irqchip/exynos-combiner.c -+++ b/drivers/irqchip/exynos-combiner.c -@@ -200,12 +200,13 @@ static void __init combiner_init(void __iomem *combiner_base, - - /** - * combiner_suspend - save interrupt combiner state before suspend -+ * @data: syscore context - * - * Save the interrupt enable set register for all combiner groups since - * the state is lost when the system enters into a sleep state. - * - */ --static int combiner_suspend(void) -+static int combiner_suspend(void *data) - { - int i; - -@@ -218,12 +219,13 @@ static int combiner_suspend(void) - - /** - * combiner_resume - restore interrupt combiner state after resume -+ * @data: syscore context - * - * Restore the interrupt enable set register for all combiner groups since - * the state is lost when the system enters into a sleep state on suspend. - * - */ --static void combiner_resume(void) -+static void combiner_resume(void *data) - { - int i; - -@@ -240,11 +242,15 @@ static void combiner_resume(void) - #define combiner_resume NULL - #endif - --static struct syscore_ops combiner_syscore_ops = { -+static const struct syscore_ops combiner_syscore_ops = { - .suspend = combiner_suspend, - .resume = combiner_resume, - }; - -+static struct syscore combiner_syscore = { -+ .ops = &combiner_syscore_ops, -+}; -+ - static int __init combiner_of_init(struct device_node *np, - struct device_node *parent) - { -@@ -264,7 +270,7 @@ static int __init combiner_of_init(struct device_node *np, - - combiner_init(combiner_base, np); - -- register_syscore_ops(&combiner_syscore_ops); -+ register_syscore(&combiner_syscore); - - return 0; - } -diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c -index a44c49e985b7..a4d03a2d1569 100644 ---- a/drivers/irqchip/irq-armada-370-xp.c -+++ b/drivers/irqchip/irq-armada-370-xp.c -@@ -726,7 +726,7 @@ static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs) - } while (1); - } - --static int mpic_suspend(void) -+static int mpic_suspend(void *data) - { - struct mpic *mpic = mpic_data; - -@@ -735,7 +735,7 @@ static int mpic_suspend(void) - return 0; - } - --static void mpic_resume(void) -+static void mpic_resume(void *data) - { - struct mpic *mpic = mpic_data; - bool src0, src1; -@@ -788,11 +788,15 @@ static void mpic_resume(void) - mpic_ipi_resume(mpic); - } - --static struct syscore_ops mpic_syscore_ops = { -+static const struct syscore_ops mpic_syscore_ops = { - .suspend = mpic_suspend, - .resume = mpic_resume, - }; - -+static struct syscore mpic_syscore = { -+ .ops = &mpic_syscore_ops, -+}; -+ - static int __init mpic_map_region(struct device_node *np, int index, - void __iomem **base, phys_addr_t *phys_base) - { -@@ -905,7 +909,7 @@ static int __init mpic_of_init(struct device_node *node, struct device_node *par - mpic_handle_cascade_irq, mpic); - } - -- register_syscore_ops(&mpic_syscore_ops); -+ register_syscore(&mpic_syscore); - - return 0; - } -diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c -index 821b288587ca..674138668f1c 100644 ---- a/drivers/irqchip/irq-bcm7038-l1.c -+++ b/drivers/irqchip/irq-bcm7038-l1.c -@@ -291,7 +291,7 @@ static int bcm7038_l1_init_one(struct device_node *dn, unsigned int idx, - static LIST_HEAD(bcm7038_l1_intcs_list); - static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock); - --static int bcm7038_l1_suspend(void) -+static int bcm7038_l1_suspend(void *data) - { - struct bcm7038_l1_chip *intc; - int boot_cpu, word; -@@ -317,7 +317,7 @@ static int bcm7038_l1_suspend(void) - return 0; - } - --static void bcm7038_l1_resume(void) -+static void bcm7038_l1_resume(void *data) - { - struct bcm7038_l1_chip *intc; - int boot_cpu, word; -@@ -338,11 +338,15 @@ static void bcm7038_l1_resume(void) - } - } - --static struct syscore_ops bcm7038_l1_syscore_ops = { -+static const struct syscore_ops bcm7038_l1_syscore_ops = { - .suspend = bcm7038_l1_suspend, - .resume = bcm7038_l1_resume, - }; - -+static struct syscore bcm7038_l1_syscore = { -+ .ops = &bcm7038_l1_syscore_ops, -+}; -+ - static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on) - { - struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); -@@ -430,7 +434,7 @@ static int bcm7038_l1_probe(struct platform_device *pdev, struct device_node *pa - raw_spin_unlock(&bcm7038_l1_intcs_lock); - - if (list_is_singular(&bcm7038_l1_intcs_list)) -- register_syscore_ops(&bcm7038_l1_syscore_ops); -+ register_syscore(&bcm7038_l1_syscore); - #endif - - pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n", -diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c -index 23158fc8d392..a51e8e6a8181 100644 ---- a/drivers/irqchip/irq-gic-v3-its.c -+++ b/drivers/irqchip/irq-gic-v3-its.c -@@ -4996,7 +4996,7 @@ static void its_enable_quirks(struct its_node *its) - its_quirks, its); - } - --static int its_save_disable(void) -+static int its_save_disable(void *data) - { - struct its_node *its; - int err = 0; -@@ -5032,7 +5032,7 @@ static int its_save_disable(void) - return err; - } - --static void its_restore_enable(void) -+static void its_restore_enable(void *data) - { - struct its_node *its; - int ret; -@@ -5092,11 +5092,15 @@ static void its_restore_enable(void) - raw_spin_unlock(&its_lock); - } - --static struct syscore_ops its_syscore_ops = { -+static const struct syscore_ops its_syscore_ops = { - .suspend = its_save_disable, - .resume = its_restore_enable, - }; - -+static struct syscore its_syscore = { -+ .ops = &its_syscore_ops, -+}; -+ - static void __init __iomem *its_map_one(struct resource *res, int *err) - { - void __iomem *its_base; -@@ -5868,7 +5872,7 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, - } - } - -- register_syscore_ops(&its_syscore_ops); -+ register_syscore(&its_syscore); - - return 0; - } -diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c -index 91b2f587119c..cca77f9948a3 100644 ---- a/drivers/irqchip/irq-i8259.c -+++ b/drivers/irqchip/irq-i8259.c -@@ -202,13 +202,13 @@ static void mask_and_ack_8259A(struct irq_data *d) - } - } - --static void i8259A_resume(void) -+static void i8259A_resume(void *data) - { - if (i8259A_auto_eoi >= 0) - init_8259A(i8259A_auto_eoi); - } - --static void i8259A_shutdown(void) -+static void i8259A_shutdown(void *data) - { - /* Put the i8259A into a quiescent state that - * the kernel initialization code can get it -@@ -220,11 +220,15 @@ static void i8259A_shutdown(void) - } - } - --static struct syscore_ops i8259_syscore_ops = { -+static const struct syscore_ops i8259_syscore_ops = { - .resume = i8259A_resume, - .shutdown = i8259A_shutdown, - }; - -+static struct syscore i8259_syscore = { -+ .ops = &i8259_syscore_ops, -+}; -+ - static void init_8259A(int auto_eoi) - { - unsigned long flags; -@@ -320,7 +324,7 @@ struct irq_domain * __init __init_i8259_irqs(struct device_node *node) - - if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL)) - pr_err("Failed to register cascade interrupt\n"); -- register_syscore_ops(&i8259_syscore_ops); -+ register_syscore(&i8259_syscore); - return domain; - } - -diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c -index b91f5c14b405..04f7ba0657be 100644 ---- a/drivers/irqchip/irq-imx-gpcv2.c -+++ b/drivers/irqchip/irq-imx-gpcv2.c -@@ -33,7 +33,7 @@ static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i) - return cd->gpc_base + cd->cpu2wakeup + i * 4; - } - --static int gpcv2_wakeup_source_save(void) -+static int gpcv2_wakeup_source_save(void *data) - { - struct gpcv2_irqchip_data *cd; - void __iomem *reg; -@@ -52,7 +52,7 @@ static int gpcv2_wakeup_source_save(void) - return 0; - } - --static void gpcv2_wakeup_source_restore(void) -+static void gpcv2_wakeup_source_restore(void *data) - { - struct gpcv2_irqchip_data *cd; - int i; -@@ -65,9 +65,13 @@ static void gpcv2_wakeup_source_restore(void) - writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i)); - } - --static struct syscore_ops imx_gpcv2_syscore_ops = { -- .suspend = gpcv2_wakeup_source_save, -- .resume = gpcv2_wakeup_source_restore, -+static const struct syscore_ops gpcv2_syscore_ops = { -+ .suspend = gpcv2_wakeup_source_save, -+ .resume = gpcv2_wakeup_source_restore, -+}; -+ -+static struct syscore gpcv2_syscore = { -+ .ops = &gpcv2_syscore_ops, - }; - - static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) -@@ -276,7 +280,7 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node, - writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup); - - imx_gpcv2_instance = cd; -- register_syscore_ops(&imx_gpcv2_syscore_ops); -+ register_syscore(&gpcv2_syscore); - - /* - * Clear the OF_POPULATED flag set in of_irq_init so that -diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c -index 39e5a72ccd3c..ad2105685b48 100644 ---- a/drivers/irqchip/irq-loongson-eiointc.c -+++ b/drivers/irqchip/irq-loongson-eiointc.c -@@ -407,21 +407,25 @@ static struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group - return NULL; - } - --static int eiointc_suspend(void) -+static int eiointc_suspend(void *data) - { - return 0; - } - --static void eiointc_resume(void) -+static void eiointc_resume(void *data) - { - eiointc_router_init(0); - } - --static struct syscore_ops eiointc_syscore_ops = { -+static const struct syscore_ops eiointc_syscore_ops = { - .suspend = eiointc_suspend, - .resume = eiointc_resume, - }; - -+static struct syscore eiointc_syscore = { -+ .ops = &eiointc_syscore_ops, -+}; -+ - static int __init pch_pic_parse_madt(union acpi_subtable_headers *header, - const unsigned long end) - { -@@ -540,7 +544,7 @@ static int __init eiointc_init(struct eiointc_priv *priv, int parent_irq, - eiointc_router_init(0); - - if (nr_pics == 1) { -- register_syscore_ops(&eiointc_syscore_ops); -+ register_syscore(&eiointc_syscore); - cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_EIOINTC_STARTING, - "irqchip/loongarch/eiointc:starting", - eiointc_router_init, NULL); -diff --git a/drivers/irqchip/irq-loongson-htpic.c b/drivers/irqchip/irq-loongson-htpic.c -index f4abdf156de7..1c691c4be989 100644 ---- a/drivers/irqchip/irq-loongson-htpic.c -+++ b/drivers/irqchip/irq-loongson-htpic.c -@@ -71,15 +71,19 @@ static void htpic_reg_init(void) - writel(0xffff, htpic->base + HTINT_EN_OFF); - } - --static void htpic_resume(void) -+static void htpic_resume(void *data) - { - htpic_reg_init(); - } - --struct syscore_ops htpic_syscore_ops = { -+static const struct syscore_ops htpic_syscore_ops = { - .resume = htpic_resume, - }; - -+static struct syscore htpic_syscore = { -+ .ops = &htpic_syscore_ops, -+}; -+ - static int __init htpic_of_init(struct device_node *node, struct device_node *parent) - { - unsigned int parent_irq[4]; -@@ -130,7 +134,7 @@ static int __init htpic_of_init(struct device_node *node, struct device_node *pa - htpic_irq_dispatch, htpic); - } - -- register_syscore_ops(&htpic_syscore_ops); -+ register_syscore(&htpic_syscore); - - return 0; - -diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c -index d8558eb35044..d2be8e954e92 100644 ---- a/drivers/irqchip/irq-loongson-htvec.c -+++ b/drivers/irqchip/irq-loongson-htvec.c -@@ -159,7 +159,7 @@ static void htvec_reset(struct htvec *priv) - } - } - --static int htvec_suspend(void) -+static int htvec_suspend(void *data) - { - int i; - -@@ -169,7 +169,7 @@ static int htvec_suspend(void) - return 0; - } - --static void htvec_resume(void) -+static void htvec_resume(void *data) - { - int i; - -@@ -177,11 +177,15 @@ static void htvec_resume(void) - writel(htvec_priv->saved_vec_en[i], htvec_priv->base + HTVEC_EN_OFF + 4 * i); - } - --static struct syscore_ops htvec_syscore_ops = { -+static const struct syscore_ops htvec_syscore_ops = { - .suspend = htvec_suspend, - .resume = htvec_resume, - }; - -+static struct syscore htvec_syscore = { -+ .ops = &htvec_syscore_ops, -+}; -+ - static int htvec_init(phys_addr_t addr, unsigned long size, - int num_parents, int parent_irq[], struct fwnode_handle *domain_handle) - { -@@ -214,7 +218,7 @@ static int htvec_init(phys_addr_t addr, unsigned long size, - - htvec_priv = priv; - -- register_syscore_ops(&htvec_syscore_ops); -+ register_syscore(&htvec_syscore); - - return 0; - -diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c -index 912bf50a5c7c..3a125f3e4287 100644 ---- a/drivers/irqchip/irq-loongson-pch-lpc.c -+++ b/drivers/irqchip/irq-loongson-pch-lpc.c -@@ -151,7 +151,7 @@ static int pch_lpc_disabled(struct pch_lpc *priv) - (readl(priv->base + LPC_INT_STS) == 0xffffffff); - } - --static int pch_lpc_suspend(void) -+static int pch_lpc_suspend(void *data) - { - pch_lpc_priv->saved_reg_ctl = readl(pch_lpc_priv->base + LPC_INT_CTL); - pch_lpc_priv->saved_reg_ena = readl(pch_lpc_priv->base + LPC_INT_ENA); -@@ -159,18 +159,22 @@ static int pch_lpc_suspend(void) - return 0; - } - --static void pch_lpc_resume(void) -+static void pch_lpc_resume(void *data) - { - writel(pch_lpc_priv->saved_reg_ctl, pch_lpc_priv->base + LPC_INT_CTL); - writel(pch_lpc_priv->saved_reg_ena, pch_lpc_priv->base + LPC_INT_ENA); - writel(pch_lpc_priv->saved_reg_pol, pch_lpc_priv->base + LPC_INT_POL); - } - --static struct syscore_ops pch_lpc_syscore_ops = { -+static const struct syscore_ops pch_lpc_syscore_ops = { - .suspend = pch_lpc_suspend, - .resume = pch_lpc_resume, - }; - -+static struct syscore pch_lpc_syscore = { -+ .ops = &pch_lpc_syscore_ops, -+}; -+ - int __init pch_lpc_acpi_init(struct irq_domain *parent, - struct acpi_madt_lpc_pic *acpi_pchlpc) - { -@@ -222,7 +226,7 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, - - pch_lpc_priv = priv; - pch_lpc_handle = irq_handle; -- register_syscore_ops(&pch_lpc_syscore_ops); -+ register_syscore(&pch_lpc_syscore); - - return 0; - -diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c -index 62e6bf3a0611..c6b369a974a7 100644 ---- a/drivers/irqchip/irq-loongson-pch-pic.c -+++ b/drivers/irqchip/irq-loongson-pch-pic.c -@@ -278,7 +278,7 @@ static void pch_pic_reset(struct pch_pic *priv) - } - } - --static int pch_pic_suspend(void) -+static int pch_pic_suspend(void *data) - { - int i, j; - -@@ -296,7 +296,7 @@ static int pch_pic_suspend(void) - return 0; - } - --static void pch_pic_resume(void) -+static void pch_pic_resume(void *data) - { - int i, j; - -@@ -313,11 +313,15 @@ static void pch_pic_resume(void) - } - } - --static struct syscore_ops pch_pic_syscore_ops = { -+static const struct syscore_ops pch_pic_syscore_ops = { - .suspend = pch_pic_suspend, - .resume = pch_pic_resume, - }; - -+static struct syscore pch_pic_syscore = { -+ .ops = &pch_pic_syscore_ops, -+}; -+ - static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base, - struct irq_domain *parent_domain, struct fwnode_handle *domain_handle, - u32 gsi_base) -@@ -356,7 +360,7 @@ static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base, - pch_pic_priv[nr_pics++] = priv; - - if (nr_pics == 1) -- register_syscore_ops(&pch_pic_syscore_ops); -+ register_syscore(&pch_pic_syscore); - - return 0; - -diff --git a/drivers/irqchip/irq-mchp-eic.c b/drivers/irqchip/irq-mchp-eic.c -index 979bb86929f8..31093a8ab67c 100644 ---- a/drivers/irqchip/irq-mchp-eic.c -+++ b/drivers/irqchip/irq-mchp-eic.c -@@ -109,7 +109,7 @@ static int mchp_eic_irq_set_wake(struct irq_data *d, unsigned int on) - return 0; - } - --static int mchp_eic_irq_suspend(void) -+static int mchp_eic_irq_suspend(void *data) - { - unsigned int hwirq; - -@@ -123,7 +123,7 @@ static int mchp_eic_irq_suspend(void) - return 0; - } - --static void mchp_eic_irq_resume(void) -+static void mchp_eic_irq_resume(void *data) - { - unsigned int hwirq; - -@@ -135,11 +135,15 @@ static void mchp_eic_irq_resume(void) - MCHP_EIC_SCFG(hwirq)); - } - --static struct syscore_ops mchp_eic_syscore_ops = { -+static const struct syscore_ops mchp_eic_syscore_ops = { - .suspend = mchp_eic_irq_suspend, - .resume = mchp_eic_irq_resume, - }; - -+static struct syscore mchp_eic_syscore = { -+ .ops = &mchp_eic_syscore_ops, -+}; -+ - static struct irq_chip mchp_eic_chip = { - .name = "eic", - .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED, -@@ -258,7 +262,7 @@ static int mchp_eic_probe(struct platform_device *pdev, struct device_node *pare - goto clk_unprepare; - } - -- register_syscore_ops(&mchp_eic_syscore_ops); -+ register_syscore(&mchp_eic_syscore); - - pr_info("%pOF: EIC registered, nr_irqs %u\n", node, MCHP_EIC_NIRQ); - -diff --git a/drivers/irqchip/irq-mst-intc.c b/drivers/irqchip/irq-mst-intc.c -index 9643cc3a77d7..7f760f555a76 100644 ---- a/drivers/irqchip/irq-mst-intc.c -+++ b/drivers/irqchip/irq-mst-intc.c -@@ -143,7 +143,7 @@ static void mst_intc_polarity_restore(struct mst_intc_chip_data *cd) - writew_relaxed(cd->saved_polarity_conf[i], addr + i * 4); - } - --static void mst_irq_resume(void) -+static void mst_irq_resume(void *data) - { - struct mst_intc_chip_data *cd; - -@@ -151,7 +151,7 @@ static void mst_irq_resume(void) - mst_intc_polarity_restore(cd); - } - --static int mst_irq_suspend(void) -+static int mst_irq_suspend(void *data) - { - struct mst_intc_chip_data *cd; - -@@ -160,14 +160,18 @@ static int mst_irq_suspend(void) - return 0; - } - --static struct syscore_ops mst_irq_syscore_ops = { -+static const struct syscore_ops mst_irq_syscore_ops = { - .suspend = mst_irq_suspend, - .resume = mst_irq_resume, - }; - -+static struct syscore mst_irq_syscore = { -+ .ops = &mst_irq_syscore_ops, -+}; -+ - static int __init mst_irq_pm_init(void) - { -- register_syscore_ops(&mst_irq_syscore_ops); -+ register_syscore(&mst_irq_syscore); - return 0; - } - late_initcall(mst_irq_pm_init); -diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c -index de481ba340f8..9571f622774e 100644 ---- a/drivers/irqchip/irq-mtk-cirq.c -+++ b/drivers/irqchip/irq-mtk-cirq.c -@@ -199,7 +199,7 @@ static const struct irq_domain_ops cirq_domain_ops = { - }; - - #ifdef CONFIG_PM_SLEEP --static int mtk_cirq_suspend(void) -+static int mtk_cirq_suspend(void *data) - { - void __iomem *reg; - u32 value, mask; -@@ -257,7 +257,7 @@ static int mtk_cirq_suspend(void) - return 0; - } - --static void mtk_cirq_resume(void) -+static void mtk_cirq_resume(void *data) - { - void __iomem *reg = mtk_cirq_reg(cirq_data, CIRQ_CONTROL); - u32 value; -@@ -272,14 +272,18 @@ static void mtk_cirq_resume(void) - writel_relaxed(value, reg); - } - --static struct syscore_ops mtk_cirq_syscore_ops = { -+static const struct syscore_ops mtk_cirq_syscore_ops = { - .suspend = mtk_cirq_suspend, - .resume = mtk_cirq_resume, - }; - -+static struct syscore mtk_cirq_syscore = { -+ .ops = &mtk_cirq_syscore_ops, -+}; -+ - static void mtk_cirq_syscore_init(void) - { -- register_syscore_ops(&mtk_cirq_syscore_ops); -+ register_syscore(&mtk_cirq_syscore); - } - #else - static inline void mtk_cirq_syscore_init(void) {} -diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c -index c938ab159289..eb01d4c5aca7 100644 ---- a/drivers/irqchip/irq-renesas-rzg2l.c -+++ b/drivers/irqchip/irq-renesas-rzg2l.c -@@ -398,7 +398,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) - return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); - } - --static int rzg2l_irqc_irq_suspend(void) -+static int rzg2l_irqc_irq_suspend(void *data) - { - struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; - void __iomem *base = rzg2l_irqc_data->base; -@@ -410,7 +410,7 @@ static int rzg2l_irqc_irq_suspend(void) - return 0; - } - --static void rzg2l_irqc_irq_resume(void) -+static void rzg2l_irqc_irq_resume(void *data) - { - struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; - void __iomem *base = rzg2l_irqc_data->base; -@@ -425,11 +425,15 @@ static void rzg2l_irqc_irq_resume(void) - writel_relaxed(cache->iitsr, base + IITSR); - } - --static struct syscore_ops rzg2l_irqc_syscore_ops = { -+static const struct syscore_ops rzg2l_irqc_syscore_ops = { - .suspend = rzg2l_irqc_irq_suspend, - .resume = rzg2l_irqc_irq_resume, - }; - -+static struct syscore rzg2l_irqc_syscore = { -+ .ops = &rzg2l_irqc_syscore_ops, -+}; -+ - static const struct irq_chip rzg2l_irqc_chip = { - .name = "rzg2l-irqc", - .irq_eoi = rzg2l_irqc_eoi, -@@ -577,7 +581,7 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n - return -ENOMEM; - } - -- register_syscore_ops(&rzg2l_irqc_syscore_ops); -+ register_syscore(&rzg2l_irqc_syscore); - - return 0; - } -diff --git a/drivers/irqchip/irq-sa11x0.c b/drivers/irqchip/irq-sa11x0.c -index d8d4dff16276..e5f24c5f3f41 100644 ---- a/drivers/irqchip/irq-sa11x0.c -+++ b/drivers/irqchip/irq-sa11x0.c -@@ -85,7 +85,7 @@ static struct sa1100irq_state { - unsigned int iccr; - } sa1100irq_state; - --static int sa1100irq_suspend(void) -+static int sa1100irq_suspend(void *data) - { - struct sa1100irq_state *st = &sa1100irq_state; - -@@ -102,7 +102,7 @@ static int sa1100irq_suspend(void) - return 0; - } - --static void sa1100irq_resume(void) -+static void sa1100irq_resume(void *data) - { - struct sa1100irq_state *st = &sa1100irq_state; - -@@ -114,14 +114,18 @@ static void sa1100irq_resume(void) - } - } - --static struct syscore_ops sa1100irq_syscore_ops = { -+static const struct syscore_ops sa1100irq_syscore_ops = { - .suspend = sa1100irq_suspend, - .resume = sa1100irq_resume, - }; - -+static struct syscore sa1100irq_syscore = { -+ .ops = &sa1100irq_syscore_ops, -+}; -+ - static int __init sa1100irq_init_devicefs(void) - { -- register_syscore_ops(&sa1100irq_syscore_ops); -+ register_syscore(&sa1100irq_syscore); - return 0; - } - -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index f255fa044764..70058871d2fb 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -268,7 +268,7 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type) - return IRQ_SET_MASK_OK; - } - --static int plic_irq_suspend(void) -+static int plic_irq_suspend(void *data) - { - struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; - -@@ -280,7 +280,7 @@ static int plic_irq_suspend(void) - return 0; - } - --static void plic_irq_resume(void) -+static void plic_irq_resume(void *data) - { - struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; - unsigned int index, cpu; -@@ -308,11 +308,15 @@ static void plic_irq_resume(void) - } - } - --static struct syscore_ops plic_irq_syscore_ops = { -+static const struct syscore_ops plic_irq_syscore_ops = { - .suspend = plic_irq_suspend, - .resume = plic_irq_resume, - }; - -+static struct syscore plic_irq_syscore = { -+ .ops = &plic_irq_syscore_ops, -+}; -+ - static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq) - { -@@ -782,7 +786,7 @@ static int plic_probe(struct fwnode_handle *fwnode) - cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, - "irqchip/sifive/plic:starting", - plic_starting_cpu, plic_dying_cpu); -- register_syscore_ops(&plic_irq_syscore_ops); -+ register_syscore(&plic_irq_syscore); - plic_global_setup_done = true; - } - } -diff --git a/drivers/irqchip/irq-sun6i-r.c b/drivers/irqchip/irq-sun6i-r.c -index 37d4b29763bc..23251831c06e 100644 ---- a/drivers/irqchip/irq-sun6i-r.c -+++ b/drivers/irqchip/irq-sun6i-r.c -@@ -268,7 +268,7 @@ static const struct irq_domain_ops sun6i_r_intc_domain_ops = { - .free = irq_domain_free_irqs_common, - }; - --static int sun6i_r_intc_suspend(void) -+static int sun6i_r_intc_suspend(void *data) - { - u32 buf[BITS_TO_U32(MAX(SUN6I_NR_TOP_LEVEL_IRQS, SUN6I_NR_MUX_BITS))]; - int i; -@@ -284,7 +284,7 @@ static int sun6i_r_intc_suspend(void) - return 0; - } - --static void sun6i_r_intc_resume(void) -+static void sun6i_r_intc_resume(void *data) - { - int i; - -@@ -294,17 +294,21 @@ static void sun6i_r_intc_resume(void) - writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i)); - } - --static void sun6i_r_intc_shutdown(void) -+static void sun6i_r_intc_shutdown(void *data) - { -- sun6i_r_intc_suspend(); -+ sun6i_r_intc_suspend(data); - } - --static struct syscore_ops sun6i_r_intc_syscore_ops = { -+static const struct syscore_ops sun6i_r_intc_syscore_ops = { - .suspend = sun6i_r_intc_suspend, - .resume = sun6i_r_intc_resume, - .shutdown = sun6i_r_intc_shutdown, - }; - -+static struct syscore sun6i_r_intc_syscore = { -+ .ops = &sun6i_r_intc_syscore_ops, -+}; -+ - static int __init sun6i_r_intc_init(struct device_node *node, - struct device_node *parent, - const struct sun6i_r_intc_variant *v) -@@ -346,10 +350,10 @@ static int __init sun6i_r_intc_init(struct device_node *node, - return -ENOMEM; - } - -- register_syscore_ops(&sun6i_r_intc_syscore_ops); -+ register_syscore(&sun6i_r_intc_syscore); - - sun6i_r_intc_ack_nmi(); -- sun6i_r_intc_resume(); -+ sun6i_r_intc_resume(NULL); - - return 0; - } -diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c -index 66cbb9f77ff3..b6382cf6359a 100644 ---- a/drivers/irqchip/irq-tegra.c -+++ b/drivers/irqchip/irq-tegra.c -@@ -132,7 +132,7 @@ static int tegra_set_wake(struct irq_data *d, unsigned int enable) - return 0; - } - --static int tegra_ictlr_suspend(void) -+static int tegra_ictlr_suspend(void *data) - { - unsigned long flags; - unsigned int i; -@@ -161,7 +161,7 @@ static int tegra_ictlr_suspend(void) - return 0; - } - --static void tegra_ictlr_resume(void) -+static void tegra_ictlr_resume(void *data) - { - unsigned long flags; - unsigned int i; -@@ -184,14 +184,18 @@ static void tegra_ictlr_resume(void) - local_irq_restore(flags); - } - --static struct syscore_ops tegra_ictlr_syscore_ops = { -+static const struct syscore_ops tegra_ictlr_syscore_ops = { - .suspend = tegra_ictlr_suspend, - .resume = tegra_ictlr_resume, - }; - -+static struct syscore tegra_ictlr_syscore = { -+ .ops = &tegra_ictlr_syscore_ops, -+}; -+ - static void tegra_ictlr_syscore_init(void) - { -- register_syscore_ops(&tegra_ictlr_syscore_ops); -+ register_syscore(&tegra_ictlr_syscore); - } - #else - #define tegra_set_wake NULL -diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c -index 2bcdf216a000..e38104c5064e 100644 ---- a/drivers/irqchip/irq-vic.c -+++ b/drivers/irqchip/irq-vic.c -@@ -120,7 +120,7 @@ static void resume_one_vic(struct vic_device *vic) - writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); - } - --static void vic_resume(void) -+static void vic_resume(void *data) - { - int id; - -@@ -146,7 +146,7 @@ static void suspend_one_vic(struct vic_device *vic) - writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); - } - --static int vic_suspend(void) -+static int vic_suspend(void *data) - { - int id; - -@@ -156,11 +156,15 @@ static int vic_suspend(void) - return 0; - } - --static struct syscore_ops vic_syscore_ops = { -+static const struct syscore_ops vic_syscore_ops = { - .suspend = vic_suspend, - .resume = vic_resume, - }; - -+static struct syscore vic_syscore = { -+ .ops = &vic_syscore_ops, -+}; -+ - /** - * vic_pm_init - initcall to register VIC pm - * -@@ -171,7 +175,7 @@ static struct syscore_ops vic_syscore_ops = { - static int __init vic_pm_init(void) - { - if (vic_id > 0) -- register_syscore_ops(&vic_syscore_ops); -+ register_syscore(&vic_syscore); - - return 0; - } -diff --git a/drivers/leds/trigger/ledtrig-cpu.c b/drivers/leds/trigger/ledtrig-cpu.c -index 05848a2fecff..679323c2ccda 100644 ---- a/drivers/leds/trigger/ledtrig-cpu.c -+++ b/drivers/leds/trigger/ledtrig-cpu.c -@@ -94,28 +94,32 @@ void ledtrig_cpu(enum cpu_led_event ledevt) - } - EXPORT_SYMBOL(ledtrig_cpu); - --static int ledtrig_cpu_syscore_suspend(void) -+static int ledtrig_cpu_syscore_suspend(void *data) - { - ledtrig_cpu(CPU_LED_STOP); - return 0; - } - --static void ledtrig_cpu_syscore_resume(void) -+static void ledtrig_cpu_syscore_resume(void *data) - { - ledtrig_cpu(CPU_LED_START); - } - --static void ledtrig_cpu_syscore_shutdown(void) -+static void ledtrig_cpu_syscore_shutdown(void *data) - { - ledtrig_cpu(CPU_LED_HALTED); - } - --static struct syscore_ops ledtrig_cpu_syscore_ops = { -+static const struct syscore_ops ledtrig_cpu_syscore_ops = { - .shutdown = ledtrig_cpu_syscore_shutdown, - .suspend = ledtrig_cpu_syscore_suspend, - .resume = ledtrig_cpu_syscore_resume, - }; - -+static struct syscore ledtrig_cpu_syscore = { -+ .ops = &ledtrig_cpu_syscore_ops, -+}; -+ - static int ledtrig_online_cpu(unsigned int cpu) - { - ledtrig_cpu(CPU_LED_START); -@@ -157,7 +161,7 @@ static int __init ledtrig_cpu_init(void) - led_trigger_register_simple(trig->name, &trig->_trig); - } - -- register_syscore_ops(&ledtrig_cpu_syscore_ops); -+ register_syscore(&ledtrig_cpu_syscore); - - ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "leds/trigger:starting", - ledtrig_online_cpu, ledtrig_prepare_down_cpu); -diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c -index b0f09c70f1ff..5fe47e784d43 100644 ---- a/drivers/macintosh/via-pmu.c -+++ b/drivers/macintosh/via-pmu.c -@@ -2600,7 +2600,7 @@ void pmu_blink(int n) - #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC32) - int pmu_sys_suspended; - --static int pmu_syscore_suspend(void) -+static int pmu_syscore_suspend(void *data) - { - /* Suspend PMU event interrupts */ - pmu_suspend(); -@@ -2614,7 +2614,7 @@ static int pmu_syscore_suspend(void) - return 0; - } - --static void pmu_syscore_resume(void) -+static void pmu_syscore_resume(void *data) - { - struct adb_request req; - -@@ -2634,14 +2634,18 @@ static void pmu_syscore_resume(void) - pmu_sys_suspended = 0; - } - --static struct syscore_ops pmu_syscore_ops = { -+static const struct syscore_ops pmu_syscore_ops = { - .suspend = pmu_syscore_suspend, - .resume = pmu_syscore_resume, - }; - -+static struct syscore pmu_syscore = { -+ .ops = &pmu_syscore_ops, -+}; -+ - static int pmu_syscore_register(void) - { -- register_syscore_ops(&pmu_syscore_ops); -+ register_syscore(&pmu_syscore); - - return 0; - } -diff --git a/drivers/power/reset/sc27xx-poweroff.c b/drivers/power/reset/sc27xx-poweroff.c -index 90287c31992c..393bd1c33b73 100644 ---- a/drivers/power/reset/sc27xx-poweroff.c -+++ b/drivers/power/reset/sc27xx-poweroff.c -@@ -28,7 +28,7 @@ static struct regmap *regmap; - * taking cpus down to avoid racing regmap or spi mutex lock when poweroff - * system through PMIC. - */ --static void sc27xx_poweroff_shutdown(void) -+static void sc27xx_poweroff_shutdown(void *data) - { - #ifdef CONFIG_HOTPLUG_CPU - int cpu; -@@ -40,10 +40,14 @@ static void sc27xx_poweroff_shutdown(void) - #endif - } - --static struct syscore_ops poweroff_syscore_ops = { -+static const struct syscore_ops poweroff_syscore_ops = { - .shutdown = sc27xx_poweroff_shutdown, - }; - -+static struct syscore poweroff_syscore = { -+ .ops = &poweroff_syscore_ops, -+}; -+ - static void sc27xx_poweroff_do_poweroff(void) - { - /* Disable the external subsys connection's power firstly */ -@@ -62,7 +66,7 @@ static int sc27xx_poweroff_probe(struct platform_device *pdev) - return -ENODEV; - - pm_power_off = sc27xx_poweroff_do_poweroff; -- register_syscore_ops(&poweroff_syscore_ops); -+ register_syscore(&poweroff_syscore); - return 0; - } - -diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c -index 7a73f5e4a1fc..f02e12dfa5f6 100644 ---- a/drivers/sh/clk/core.c -+++ b/drivers/sh/clk/core.c -@@ -569,7 +569,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) - EXPORT_SYMBOL_GPL(clk_round_rate); - - #ifdef CONFIG_PM --static void clks_core_resume(void) -+static void clks_core_resume(void *data) - { - struct clk *clkp; - -@@ -588,13 +588,17 @@ static void clks_core_resume(void) - } - } - --static struct syscore_ops clks_syscore_ops = { -+static const struct syscore_ops clks_syscore_ops = { - .resume = clks_core_resume, - }; - -+static struct syscore clks_syscore = { -+ .ops = &clks_syscore_ops, -+}; -+ - static int __init clk_syscore_init(void) - { -- register_syscore_ops(&clks_syscore_ops); -+ register_syscore(&clks_syscore); - - return 0; - } -diff --git a/drivers/sh/intc/core.c b/drivers/sh/intc/core.c -index ea571eeb3078..3dde703b7766 100644 ---- a/drivers/sh/intc/core.c -+++ b/drivers/sh/intc/core.c -@@ -394,7 +394,7 @@ int __init register_intc_controller(struct intc_desc *desc) - return -ENOMEM; - } - --static int intc_suspend(void) -+static int intc_suspend(void *data) - { - struct intc_desc_int *d; - -@@ -420,7 +420,7 @@ static int intc_suspend(void) - return 0; - } - --static void intc_resume(void) -+static void intc_resume(void *data) - { - struct intc_desc_int *d; - -@@ -450,11 +450,15 @@ static void intc_resume(void) - } - } - --struct syscore_ops intc_syscore_ops = { -+static const struct syscore_ops intc_syscore_ops = { - .suspend = intc_suspend, - .resume = intc_resume, - }; - -+static struct syscore intc_syscore = { -+ .ops = &intc_syscore_ops, -+}; -+ - const struct bus_type intc_subsys = { - .name = "intc", - .dev_name = "intc", -@@ -477,7 +481,7 @@ static int __init register_intc_devs(void) - struct intc_desc_int *d; - int error; - -- register_syscore_ops(&intc_syscore_ops); -+ register_syscore(&intc_syscore); - - error = subsys_system_register(&intc_subsys, NULL); - if (!error) { -diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c -index 364ddbe365c2..bd830649b60d 100644 ---- a/drivers/soc/bcm/brcmstb/biuctrl.c -+++ b/drivers/soc/bcm/brcmstb/biuctrl.c -@@ -298,7 +298,7 @@ static int __init setup_hifcpubiuctrl_regs(struct device_node *np) - #ifdef CONFIG_PM_SLEEP - static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS]; - --static int brcmstb_cpu_credit_reg_suspend(void) -+static int brcmstb_cpu_credit_reg_suspend(void *data) - { - unsigned int i; - -@@ -311,7 +311,7 @@ static int brcmstb_cpu_credit_reg_suspend(void) - return 0; - } - --static void brcmstb_cpu_credit_reg_resume(void) -+static void brcmstb_cpu_credit_reg_resume(void *data) - { - unsigned int i; - -@@ -322,10 +322,14 @@ static void brcmstb_cpu_credit_reg_resume(void) - cbc_writel(cpubiuctrl_reg_save[i], i); - } - --static struct syscore_ops brcmstb_cpu_credit_syscore_ops = { -+static const struct syscore_ops brcmstb_cpu_credit_syscore_ops = { - .suspend = brcmstb_cpu_credit_reg_suspend, - .resume = brcmstb_cpu_credit_reg_resume, - }; -+ -+static struct syscore brcmstb_cpu_credit_syscore = { -+ .ops = &brcmstb_cpu_credit_syscore_ops, -+}; - #endif - - -@@ -354,7 +358,7 @@ static int __init brcmstb_biuctrl_init(void) - a72_b53_rac_enable_all(np); - mcp_a72_b53_set(); - #ifdef CONFIG_PM_SLEEP -- register_syscore_ops(&brcmstb_cpu_credit_syscore_ops); -+ register_syscore(&brcmstb_cpu_credit_syscore); - #endif - ret = 0; - out_put: -diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c -index 034a2a535a1e..93bbebd68001 100644 ---- a/drivers/soc/tegra/pmc.c -+++ b/drivers/soc/tegra/pmc.c -@@ -466,7 +466,7 @@ struct tegra_pmc { - unsigned long *wake_type_dual_edge_map; - unsigned long *wake_sw_status_map; - unsigned long *wake_cntrl_level_map; -- struct syscore_ops syscore; -+ struct syscore syscore; - }; - - static struct tegra_pmc *pmc = &(struct tegra_pmc) { -@@ -3147,7 +3147,7 @@ static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int - } - } - --static void tegra186_pmc_wake_syscore_resume(void) -+static void tegra186_pmc_wake_syscore_resume(void *data) - { - u32 status, mask; - unsigned int i; -@@ -3160,7 +3160,7 @@ static void tegra186_pmc_wake_syscore_resume(void) - } - } - --static int tegra186_pmc_wake_syscore_suspend(void) -+static int tegra186_pmc_wake_syscore_suspend(void *data) - { - wke_read_sw_wake_status(pmc); - -@@ -3179,6 +3179,11 @@ static int tegra186_pmc_wake_syscore_suspend(void) - return 0; - } - -+static const struct syscore_ops tegra186_pmc_wake_syscore_ops = { -+ .suspend = tegra186_pmc_wake_syscore_suspend, -+ .resume = tegra186_pmc_wake_syscore_resume, -+}; -+ - #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) - static int tegra_pmc_suspend(struct device *dev) - { -@@ -3829,10 +3834,8 @@ static const struct tegra_pmc_regs tegra186_pmc_regs = { - - static void tegra186_pmc_init(struct tegra_pmc *pmc) - { -- pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; -- pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; -- -- register_syscore_ops(&pmc->syscore); -+ pmc->syscore.ops = &tegra186_pmc_wake_syscore_ops; -+ register_syscore(&pmc->syscore); - } - - static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, -diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c -index bd2fca7dc017..8a2f441cd2ec 100644 ---- a/drivers/thermal/intel/intel_hfi.c -+++ b/drivers/thermal/intel/intel_hfi.c -@@ -592,7 +592,7 @@ static void hfi_disable_instance(void *ptr) - hfi_disable(); - } - --static void hfi_syscore_resume(void) -+static void hfi_syscore_resume(void *data) - { - /* This code runs only on the boot CPU. */ - struct hfi_cpu_info *info = &per_cpu(hfi_cpu_info, 0); -@@ -603,7 +603,7 @@ static void hfi_syscore_resume(void) - hfi_enable_instance(hfi_instance); - } - --static int hfi_syscore_suspend(void) -+static int hfi_syscore_suspend(void *data) - { - /* No locking needed. There is no concurrency with CPU offline. */ - hfi_disable(); -@@ -611,11 +611,15 @@ static int hfi_syscore_suspend(void) - return 0; - } - --static struct syscore_ops hfi_pm_ops = { -+static const struct syscore_ops hfi_pm_ops = { - .resume = hfi_syscore_resume, - .suspend = hfi_syscore_suspend, - }; - -+static struct syscore hfi_pm = { -+ .ops = &hfi_pm_ops, -+}; -+ - static int hfi_thermal_notify(struct notifier_block *nb, unsigned long state, - void *_notify) - { -@@ -710,7 +714,7 @@ void __init intel_hfi_init(void) - if (thermal_genl_register_notifier(&hfi_thermal_nb)) - goto err_nl_notif; - -- register_syscore_ops(&hfi_pm_ops); -+ register_syscore(&hfi_pm); - - return; - -diff --git a/drivers/xen/xen-acpi-processor.c b/drivers/xen/xen-acpi-processor.c -index 520756159d3d..8d1860bd5d57 100644 ---- a/drivers/xen/xen-acpi-processor.c -+++ b/drivers/xen/xen-acpi-processor.c -@@ -492,7 +492,7 @@ static void xen_acpi_processor_resume_worker(struct work_struct *dummy) - pr_info("ACPI data upload failed, error = %d\n", rc); - } - --static void xen_acpi_processor_resume(void) -+static void xen_acpi_processor_resume(void *data) - { - static DECLARE_WORK(wq, xen_acpi_processor_resume_worker); - -@@ -506,10 +506,14 @@ static void xen_acpi_processor_resume(void) - schedule_work(&wq); - } - --static struct syscore_ops xap_syscore_ops = { -+static const struct syscore_ops xap_syscore_ops = { - .resume = xen_acpi_processor_resume, - }; - -+static struct syscore xap_syscore = { -+ .ops = &xap_syscore_ops, -+}; -+ - static int __init xen_acpi_processor_init(void) - { - int i; -@@ -560,7 +564,7 @@ static int __init xen_acpi_processor_init(void) - if (rc) - goto err_unregister; - -- register_syscore_ops(&xap_syscore_ops); -+ register_syscore(&xap_syscore); - - return 0; - err_unregister: -@@ -577,7 +581,7 @@ static void __exit xen_acpi_processor_exit(void) - { - int i; - -- unregister_syscore_ops(&xap_syscore_ops); -+ unregister_syscore(&xap_syscore); - bitmap_free(acpi_ids_done); - bitmap_free(acpi_id_present); - bitmap_free(acpi_id_cst_present); -diff --git a/include/linux/syscore_ops.h b/include/linux/syscore_ops.h -index ae4d48e4c970..ac6d71be5c38 100644 ---- a/include/linux/syscore_ops.h -+++ b/include/linux/syscore_ops.h -@@ -11,14 +11,19 @@ - #include - - struct syscore_ops { -+ int (*suspend)(void *data); -+ void (*resume)(void *data); -+ void (*shutdown)(void *data); -+}; -+ -+struct syscore { - struct list_head node; -- int (*suspend)(void); -- void (*resume)(void); -- void (*shutdown)(void); -+ const struct syscore_ops *ops; -+ void *data; - }; - --extern void register_syscore_ops(struct syscore_ops *ops); --extern void unregister_syscore_ops(struct syscore_ops *ops); -+extern void register_syscore(struct syscore *syscore); -+extern void unregister_syscore(struct syscore *syscore); - #ifdef CONFIG_PM_SLEEP - extern int syscore_suspend(void); - extern void syscore_resume(void); -diff --git a/kernel/cpu_pm.c b/kernel/cpu_pm.c -index b0f0d15085db..7481fbb947d3 100644 ---- a/kernel/cpu_pm.c -+++ b/kernel/cpu_pm.c -@@ -173,7 +173,7 @@ int cpu_cluster_pm_exit(void) - EXPORT_SYMBOL_GPL(cpu_cluster_pm_exit); - - #ifdef CONFIG_PM --static int cpu_pm_suspend(void) -+static int cpu_pm_suspend(void *data) - { - int ret; - -@@ -185,20 +185,24 @@ static int cpu_pm_suspend(void) - return ret; - } - --static void cpu_pm_resume(void) -+static void cpu_pm_resume(void *data) - { - cpu_cluster_pm_exit(); - cpu_pm_exit(); - } - --static struct syscore_ops cpu_pm_syscore_ops = { -+static const struct syscore_ops cpu_pm_syscore_ops = { - .suspend = cpu_pm_suspend, - .resume = cpu_pm_resume, - }; - -+static struct syscore cpu_pm_syscore = { -+ .ops = &cpu_pm_syscore_ops, -+}; -+ - static int cpu_pm_init(void) - { -- register_syscore_ops(&cpu_pm_syscore_ops); -+ register_syscore(&cpu_pm_syscore); - return 0; - } - core_initcall(cpu_pm_init); -diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c -index bf59e37d650a..3cd0c40282c0 100644 ---- a/kernel/irq/generic-chip.c -+++ b/kernel/irq/generic-chip.c -@@ -650,7 +650,7 @@ static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc) - } - - #ifdef CONFIG_PM --static int irq_gc_suspend(void) -+static int irq_gc_suspend(void *data) - { - struct irq_chip_generic *gc; - -@@ -670,7 +670,7 @@ static int irq_gc_suspend(void) - return 0; - } - --static void irq_gc_resume(void) -+static void irq_gc_resume(void *data) - { - struct irq_chip_generic *gc; - -@@ -693,7 +693,7 @@ static void irq_gc_resume(void) - #define irq_gc_resume NULL - #endif - --static void irq_gc_shutdown(void) -+static void irq_gc_shutdown(void *data) - { - struct irq_chip_generic *gc; - -@@ -709,15 +709,19 @@ static void irq_gc_shutdown(void) - } - } - --static struct syscore_ops irq_gc_syscore_ops = { -+static const struct syscore_ops irq_gc_syscore_ops = { - .suspend = irq_gc_suspend, - .resume = irq_gc_resume, - .shutdown = irq_gc_shutdown, - }; - -+static struct syscore irq_gc_syscore = { -+ .ops = &irq_gc_syscore_ops, -+}; -+ - static int __init irq_gc_init_ops(void) - { -- register_syscore_ops(&irq_gc_syscore_ops); -+ register_syscore(&irq_gc_syscore); - return 0; - } - device_initcall(irq_gc_init_ops); -diff --git a/kernel/irq/pm.c b/kernel/irq/pm.c -index f7394729cedc..99ff65466d87 100644 ---- a/kernel/irq/pm.c -+++ b/kernel/irq/pm.c -@@ -211,21 +211,26 @@ void rearm_wake_irq(unsigned int irq) - - /** - * irq_pm_syscore_resume - enable interrupt lines early -+ * @data: syscore context - * - * Enable all interrupt lines with %IRQF_EARLY_RESUME set. - */ --static void irq_pm_syscore_resume(void) -+static void irq_pm_syscore_resume(void *data) - { - resume_irqs(true); - } - --static struct syscore_ops irq_pm_syscore_ops = { -+static const struct syscore_ops irq_pm_syscore_ops = { - .resume = irq_pm_syscore_resume, - }; - -+static struct syscore irq_pm_syscore = { -+ .ops = &irq_pm_syscore_ops, -+}; -+ - static int __init irq_pm_init_ops(void) - { -- register_syscore_ops(&irq_pm_syscore_ops); -+ register_syscore(&irq_pm_syscore); - return 0; - } - -diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c -index c27fc7fc64eb..70a97290ad90 100644 ---- a/kernel/printk/printk.c -+++ b/kernel/printk/printk.c -@@ -3660,12 +3660,13 @@ static bool legacy_kthread_create(void) - - /** - * printk_kthreads_shutdown - shutdown all threaded printers -+ * @data: syscore context - * - * On system shutdown all threaded printers are stopped. This allows printk - * to transition back to atomic printing, thus providing a robust mechanism - * for the final shutdown/reboot messages to be output. - */ --static void printk_kthreads_shutdown(void) -+static void printk_kthreads_shutdown(void *data) - { - struct console *con; - -@@ -3687,10 +3688,14 @@ static void printk_kthreads_shutdown(void) - console_list_unlock(); - } - --static struct syscore_ops printk_syscore_ops = { -+static const struct syscore_ops printk_syscore_ops = { - .shutdown = printk_kthreads_shutdown, - }; - -+static struct syscore printk_syscore = { -+ .ops = &printk_syscore_ops, -+}; -+ - /* - * If appropriate, start nbcon kthreads and set @printk_kthreads_running. - * If any kthreads fail to start, those consoles are unregistered. -@@ -3758,7 +3763,7 @@ static void printk_kthreads_check_locked(void) - - static int __init printk_set_kthreads_ready(void) - { -- register_syscore_ops(&printk_syscore_ops); -+ register_syscore(&printk_syscore); - - console_list_lock(); - printk_kthreads_ready = true; -diff --git a/kernel/time/sched_clock.c b/kernel/time/sched_clock.c -index 425d429906d0..f3aaef695b8c 100644 ---- a/kernel/time/sched_clock.c -+++ b/kernel/time/sched_clock.c -@@ -296,6 +296,11 @@ int sched_clock_suspend(void) - return 0; - } - -+static int sched_clock_syscore_suspend(void *data) -+{ -+ return sched_clock_suspend(); -+} -+ - void sched_clock_resume(void) - { - struct clock_read_data *rd = &cd.read_data[0]; -@@ -305,14 +310,23 @@ void sched_clock_resume(void) - rd->read_sched_clock = cd.actual_read_sched_clock; - } - --static struct syscore_ops sched_clock_ops = { -- .suspend = sched_clock_suspend, -- .resume = sched_clock_resume, -+static void sched_clock_syscore_resume(void *data) -+{ -+ sched_clock_resume(); -+} -+ -+static const struct syscore_ops sched_clock_syscore_ops = { -+ .suspend = sched_clock_syscore_suspend, -+ .resume = sched_clock_syscore_resume, -+}; -+ -+static struct syscore sched_clock_syscore = { -+ .ops = &sched_clock_syscore_ops, - }; - - static int __init sched_clock_syscore_init(void) - { -- register_syscore_ops(&sched_clock_ops); -+ register_syscore(&sched_clock_syscore); - - return 0; - } -diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c -index c7dcccc5f3d6..c07e562ee4c1 100644 ---- a/kernel/time/timekeeping.c -+++ b/kernel/time/timekeeping.c -@@ -1994,6 +1994,11 @@ void timekeeping_resume(void) - timerfd_resume(); - } - -+static void timekeeping_syscore_resume(void *data) -+{ -+ timekeeping_resume(); -+} -+ - int timekeeping_suspend(void) - { - struct timekeeper *tks = &tk_core.shadow_timekeeper; -@@ -2061,15 +2066,24 @@ int timekeeping_suspend(void) - return 0; - } - -+static int timekeeping_syscore_suspend(void *data) -+{ -+ return timekeeping_suspend(); -+} -+ - /* sysfs resume/suspend bits for timekeeping */ --static struct syscore_ops timekeeping_syscore_ops = { -- .resume = timekeeping_resume, -- .suspend = timekeeping_suspend, -+static const struct syscore_ops timekeeping_syscore_ops = { -+ .resume = timekeeping_syscore_resume, -+ .suspend = timekeeping_syscore_suspend, -+}; -+ -+static struct syscore timekeeping_syscore = { -+ .ops = &timekeeping_syscore_ops, - }; - - static int __init timekeeping_init_ops(void) - { -- register_syscore_ops(&timekeeping_syscore_ops); -+ register_syscore(&timekeeping_syscore); - return 0; - } - device_initcall(timekeeping_init_ops); -diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c -index 46581554abfb..3ec22d034e73 100644 ---- a/virt/kvm/kvm_main.c -+++ b/virt/kvm/kvm_main.c -@@ -5629,7 +5629,7 @@ static int kvm_offline_cpu(unsigned int cpu) - return 0; - } - --static void kvm_shutdown(void) -+static void kvm_shutdown(void *data) - { - /* - * Disable hardware virtualization and set kvm_rebooting to indicate -@@ -5647,7 +5647,7 @@ static void kvm_shutdown(void) - on_each_cpu(kvm_disable_virtualization_cpu, NULL, 1); - } - --static int kvm_suspend(void) -+static int kvm_suspend(void *data) - { - /* - * Secondary CPUs and CPU hotplug are disabled across the suspend/resume -@@ -5664,7 +5664,7 @@ static int kvm_suspend(void) - return 0; - } - --static void kvm_resume(void) -+static void kvm_resume(void *data) - { - lockdep_assert_not_held(&kvm_usage_lock); - lockdep_assert_irqs_disabled(); -@@ -5672,12 +5672,16 @@ static void kvm_resume(void) - WARN_ON_ONCE(kvm_enable_virtualization_cpu()); - } - --static struct syscore_ops kvm_syscore_ops = { -+static const struct syscore_ops kvm_syscore_ops = { - .suspend = kvm_suspend, - .resume = kvm_resume, - .shutdown = kvm_shutdown, - }; - -+static struct syscore kvm_syscore = { -+ .ops = &kvm_syscore_ops, -+}; -+ - int kvm_enable_virtualization(void) - { - int r; -@@ -5694,7 +5698,7 @@ int kvm_enable_virtualization(void) - if (r) - goto err_cpuhp; - -- register_syscore_ops(&kvm_syscore_ops); -+ register_syscore(&kvm_syscore); - - /* - * Undo virtualization enabling and bail if the system is going down. -@@ -5716,7 +5720,7 @@ int kvm_enable_virtualization(void) - return 0; - - err_rebooting: -- unregister_syscore_ops(&kvm_syscore_ops); -+ unregister_syscore(&kvm_syscore); - cpuhp_remove_state(CPUHP_AP_KVM_ONLINE); - err_cpuhp: - kvm_arch_disable_virtualization(); -@@ -5732,7 +5736,7 @@ void kvm_disable_virtualization(void) - if (--kvm_usage_count) - return; - -- unregister_syscore_ops(&kvm_syscore_ops); -+ unregister_syscore(&kvm_syscore); - cpuhp_remove_state(CPUHP_AP_KVM_ONLINE); - kvm_arch_disable_virtualization(); - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch b/SPECS/linux-lts-kmhv2/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch new file mode 100644 index 0000000000..edf918ccc1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch @@ -0,0 +1,96 @@ +From 362bcba652bd4b28531fbf93691ef6fba9a852a7 Mon Sep 17 00:00:00 2001 +From: Frank Li +Date: Mon, 29 Sep 2025 10:24:14 -0400 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: add missed compatible string + for arm64 layerscape + +Add missed compatible string for arm64 layerscape platform. Allow these +fallback to fsl,ls1028a-dwc3. + +Remove fallback snps,dwc3 because layerscape dwc3 is not full compatible +with common snps,dwc3 device, a special value gsburstcfg0 need be set when +dma coherence enabled. + +Allow iommus property. + +Change ref to snps,dwc3-common.yaml to use dwc3 flatten library. + +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Frank Li +Link: https://lore.kernel.org/r/20250929-ls_dma_coherence-v5-1-2ebee578eb7e@nxp.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit b9f1c762a4de17d93017fbd12b9941caff6d3078) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/usb/fsl,ls1028a.yaml | 33 ++++++++++--------- + 1 file changed, 18 insertions(+), 15 deletions(-) + +diff --git a/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml b/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml +index a44bdf391887..4784f057264a 100644 +--- a/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml ++++ b/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml +@@ -9,21 +9,19 @@ title: Freescale layerscape SuperSpeed DWC3 USB SoC controller + maintainers: + - Frank Li + +-select: +- properties: +- compatible: +- contains: +- enum: +- - fsl,ls1028a-dwc3 +- required: +- - compatible +- + properties: + compatible: +- items: +- - enum: +- - fsl,ls1028a-dwc3 +- - const: snps,dwc3 ++ oneOf: ++ - items: ++ - enum: ++ - fsl,ls1012a-dwc3 ++ - fsl,ls1043a-dwc3 ++ - fsl,ls1046a-dwc3 ++ - fsl,ls1088a-dwc3 ++ - fsl,ls208xa-dwc3 ++ - fsl,lx2160a-dwc3 ++ - const: fsl,ls1028a-dwc3 ++ - const: fsl,ls1028a-dwc3 + + reg: + maxItems: 1 +@@ -31,6 +29,11 @@ properties: + interrupts: + maxItems: 1 + ++ iommus: ++ maxItems: 1 ++ ++ dma-coherent: true ++ + unevaluatedProperties: false + + required: +@@ -39,14 +42,14 @@ required: + - interrupts + + allOf: +- - $ref: snps,dwc3.yaml# ++ - $ref: snps,dwc3-common.yaml# + + examples: + - | + #include + + usb@fe800000 { +- compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; ++ compatible = "fsl,ls1028a-dwc3"; + reg = <0xfe800000 0x100000>; + interrupts = ; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0164-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch b/SPECS/linux-lts-kmhv2/0164-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch deleted file mode 100644 index 76e29a3422..0000000000 --- a/SPECS/linux-lts-kmhv2/0164-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch +++ /dev/null @@ -1,325 +0,0 @@ -From bb03ede744a1b004dd7ecaebdb891a4d0bc0c559 Mon Sep 17 00:00:00 2001 -From: Nick Hu -Date: Tue, 2 Dec 2025 14:07:41 +0800 -Subject: [PATCH 164/467] UPSTREAM: irqchip/riscv-aplic: Preserve APLIC states - across suspend/resume - -The APLIC states might be reset when the platform enters a low power -state, but the register states are not being preserved and restored, -which prevents interrupt delivery after the platform resumes. -Solve this by adding a syscore ops and a power management notifier to -preserve and restore the APLIC states on suspend and resume. - -[ tglx: Folded the build fix provided by Geert ] - -Signed-off-by: Nick Hu -Signed-off-by: Thomas Gleixner -Reviewed-by: Yong-Xuan Wang -Reviewed-by: Cyan Yang -Reviewed-by: Nutty Liu -Reviewed-by: Anup Patel -Link: https://patch.msgid.link/20251202-preserve-aplic-imsic-v3-2-1844fbf1fe92@sifive.com -(cherry picked from commit 95a8ddde36601d0a645475fb080ed118db59c8c3) -Signed-off-by: Han Gao ---- - drivers/irqchip/irq-riscv-aplic-direct.c | 10 ++ - drivers/irqchip/irq-riscv-aplic-main.c | 170 ++++++++++++++++++++++- - drivers/irqchip/irq-riscv-aplic-main.h | 19 +++ - 3 files changed, 198 insertions(+), 1 deletion(-) - -diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c -index c2a75bf3d20c..5a9650225dd8 100644 ---- a/drivers/irqchip/irq-riscv-aplic-direct.c -+++ b/drivers/irqchip/irq-riscv-aplic-direct.c -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -171,6 +172,15 @@ static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en) - writel(de, idc->regs + APLIC_IDC_IDELIVERY); - } - -+void aplic_direct_restore_states(struct aplic_priv *priv) -+{ -+ struct aplic_direct *direct = container_of(priv, struct aplic_direct, priv); -+ int cpu; -+ -+ for_each_cpu(cpu, &direct->lmask) -+ aplic_idc_set_delivery(per_cpu_ptr(&aplic_idcs, cpu), true); -+} -+ - static int aplic_direct_dying_cpu(unsigned int cpu) - { - if (aplic_direct_parent_irq) -diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c -index 93e7c51f944a..4495ca26abf5 100644 ---- a/drivers/irqchip/irq-riscv-aplic-main.c -+++ b/drivers/irqchip/irq-riscv-aplic-main.c -@@ -12,10 +12,169 @@ - #include - #include - #include -+#include -+#include - #include -+#include - - #include "irq-riscv-aplic-main.h" - -+static LIST_HEAD(aplics); -+ -+static void aplic_restore_states(struct aplic_priv *priv) -+{ -+ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs; -+ struct aplic_src_ctrl *srcs; -+ void __iomem *regs; -+ u32 nr_irqs, i; -+ -+ regs = priv->regs; -+ writel(saved_regs->domaincfg, regs + APLIC_DOMAINCFG); -+#ifdef CONFIG_RISCV_M_MODE -+ writel(saved_regs->msiaddr, regs + APLIC_xMSICFGADDR); -+ writel(saved_regs->msiaddrh, regs + APLIC_xMSICFGADDRH); -+#endif -+ /* -+ * The sourcecfg[i] has to be restored prior to the target[i], interrupt-pending and -+ * interrupt-enable bits. The AIA specification states that "Whenever interrupt source i is -+ * inactive in an interrupt domain, the corresponding interrupt-pending and interrupt-enable -+ * bits within the domain are read-only zeros, and register target[i] is also read-only -+ * zero." -+ */ -+ nr_irqs = priv->nr_irqs; -+ for (i = 0; i < nr_irqs; i++) { -+ srcs = &priv->saved_hw_regs.srcs[i]; -+ writel(srcs->sourcecfg, regs + APLIC_SOURCECFG_BASE + i * sizeof(u32)); -+ writel(srcs->target, regs + APLIC_TARGET_BASE + i * sizeof(u32)); -+ } -+ -+ for (i = 0; i <= nr_irqs; i += 32) { -+ srcs = &priv->saved_hw_regs.srcs[i]; -+ writel(-1U, regs + APLIC_CLRIE_BASE + (i / 32) * sizeof(u32)); -+ writel(srcs->ie, regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32)); -+ -+ /* Re-trigger the interrupts if it forwards interrupts to target harts by MSIs */ -+ if (!priv->nr_idcs) -+ writel(readl(regs + APLIC_CLRIP_BASE + (i / 32) * sizeof(u32)), -+ regs + APLIC_SETIP_BASE + (i / 32) * sizeof(u32)); -+ } -+ -+ if (priv->nr_idcs) -+ aplic_direct_restore_states(priv); -+} -+ -+static void aplic_save_states(struct aplic_priv *priv) -+{ -+ struct aplic_src_ctrl *srcs; -+ void __iomem *regs; -+ u32 i, nr_irqs; -+ -+ regs = priv->regs; -+ nr_irqs = priv->nr_irqs; -+ /* The valid interrupt source IDs range from 1 to N, where N is priv->nr_irqs */ -+ for (i = 0; i < nr_irqs; i++) { -+ srcs = &priv->saved_hw_regs.srcs[i]; -+ srcs->target = readl(regs + APLIC_TARGET_BASE + i * sizeof(u32)); -+ -+ if (i % 32) -+ continue; -+ -+ srcs->ie = readl(regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32)); -+ } -+ -+ /* Save the nr_irqs bit if needed */ -+ if (!(nr_irqs % 32)) { -+ srcs = &priv->saved_hw_regs.srcs[nr_irqs]; -+ srcs->ie = readl(regs + APLIC_SETIE_BASE + (nr_irqs / 32) * sizeof(u32)); -+ } -+} -+ -+static int aplic_syscore_suspend(void *data) -+{ -+ struct aplic_priv *priv; -+ -+ list_for_each_entry(priv, &aplics, head) -+ aplic_save_states(priv); -+ -+ return 0; -+} -+ -+static void aplic_syscore_resume(void *data) -+{ -+ struct aplic_priv *priv; -+ -+ list_for_each_entry(priv, &aplics, head) -+ aplic_restore_states(priv); -+} -+ -+static struct syscore_ops aplic_syscore_ops = { -+ .suspend = aplic_syscore_suspend, -+ .resume = aplic_syscore_resume, -+}; -+ -+static struct syscore aplic_syscore = { -+ .ops = &aplic_syscore_ops, -+}; -+ -+static int aplic_pm_notifier(struct notifier_block *nb, unsigned long action, void *data) -+{ -+ struct aplic_priv *priv = container_of(nb, struct aplic_priv, genpd_nb); -+ -+ switch (action) { -+ case GENPD_NOTIFY_PRE_OFF: -+ aplic_save_states(priv); -+ break; -+ case GENPD_NOTIFY_ON: -+ aplic_restore_states(priv); -+ break; -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+static void aplic_pm_remove(void *data) -+{ -+ struct aplic_priv *priv = data; -+ struct device *dev = priv->dev; -+ -+ list_del(&priv->head); -+ if (dev->pm_domain) -+ dev_pm_genpd_remove_notifier(dev); -+} -+ -+static int aplic_pm_add(struct device *dev, struct aplic_priv *priv) -+{ -+ struct aplic_src_ctrl *srcs; -+ int ret; -+ -+ srcs = devm_kzalloc(dev, (priv->nr_irqs + 1) * sizeof(*srcs), GFP_KERNEL); -+ if (!srcs) -+ return -ENOMEM; -+ -+ priv->saved_hw_regs.srcs = srcs; -+ list_add(&priv->head, &aplics); -+ if (dev->pm_domain) { -+ priv->genpd_nb.notifier_call = aplic_pm_notifier; -+ ret = dev_pm_genpd_add_notifier(dev, &priv->genpd_nb); -+ if (ret) -+ goto remove_head; -+ -+ ret = devm_pm_runtime_enable(dev); -+ if (ret) -+ goto remove_notifier; -+ } -+ -+ return devm_add_action_or_reset(dev, aplic_pm_remove, priv); -+ -+remove_notifier: -+ dev_pm_genpd_remove_notifier(dev); -+remove_head: -+ list_del(&priv->head); -+ return ret; -+} -+ - void aplic_irq_unmask(struct irq_data *d) - { - struct aplic_priv *priv = irq_data_get_irq_chip_data(d); -@@ -60,6 +219,8 @@ int aplic_irq_set_type(struct irq_data *d, unsigned int type) - sourcecfg += (d->hwirq - 1) * sizeof(u32); - writel(val, sourcecfg); - -+ priv->saved_hw_regs.srcs[d->hwirq - 1].sourcecfg = val; -+ - return 0; - } - -@@ -82,6 +243,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, - - void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) - { -+ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs; - u32 val; - #ifdef CONFIG_RISCV_M_MODE - u32 valh; -@@ -95,6 +257,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) - valh |= FIELD_PREP(APLIC_xMSICFGADDRH_HHXS, priv->msicfg.hhxs); - writel(val, priv->regs + APLIC_xMSICFGADDR); - writel(valh, priv->regs + APLIC_xMSICFGADDRH); -+ saved_regs->msiaddr = val; -+ saved_regs->msiaddrh = valh; - } - #endif - -@@ -106,6 +270,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) - writel(val, priv->regs + APLIC_DOMAINCFG); - if (readl(priv->regs + APLIC_DOMAINCFG) != val) - dev_warn(priv->dev, "unable to write 0x%x in domaincfg\n", val); -+ -+ saved_regs->domaincfg = val; - } - - static void aplic_init_hw_irqs(struct aplic_priv *priv) -@@ -176,7 +342,7 @@ int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem * - /* Setup initial state APLIC interrupts */ - aplic_init_hw_irqs(priv); - -- return 0; -+ return aplic_pm_add(dev, priv); - } - - static int aplic_probe(struct platform_device *pdev) -@@ -209,6 +375,8 @@ static int aplic_probe(struct platform_device *pdev) - if (rc) - dev_err_probe(dev, rc, "failed to setup APLIC in %s mode\n", - msi_mode ? "MSI" : "direct"); -+ else -+ register_syscore(&aplic_syscore); - - #ifdef CONFIG_ACPI - if (!acpi_disabled) -diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-riscv-aplic-main.h -index b0ad8cde69b1..2d8ad7138541 100644 ---- a/drivers/irqchip/irq-riscv-aplic-main.h -+++ b/drivers/irqchip/irq-riscv-aplic-main.h -@@ -23,7 +23,25 @@ struct aplic_msicfg { - u32 lhxw; - }; - -+struct aplic_src_ctrl { -+ u32 sourcecfg; -+ u32 target; -+ u32 ie; -+}; -+ -+struct aplic_saved_regs { -+ u32 domaincfg; -+#ifdef CONFIG_RISCV_M_MODE -+ u32 msiaddr; -+ u32 msiaddrh; -+#endif -+ struct aplic_src_ctrl *srcs; -+}; -+ - struct aplic_priv { -+ struct list_head head; -+ struct notifier_block genpd_nb; -+ struct aplic_saved_regs saved_hw_regs; - struct device *dev; - u32 gsi_base; - u32 nr_irqs; -@@ -40,6 +58,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, - unsigned long *hwirq, unsigned int *type); - void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode); - int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *regs); -+void aplic_direct_restore_states(struct aplic_priv *priv); - int aplic_direct_setup(struct device *dev, void __iomem *regs); - #ifdef CONFIG_RISCV_APLIC_MSI - int aplic_msi_setup(struct device *dev, void __iomem *regs); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0165-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch b/SPECS/linux-lts-kmhv2/0165-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch deleted file mode 100644 index 3b32023095..0000000000 --- a/SPECS/linux-lts-kmhv2/0165-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 53ca58e7f8870492ce5c75dda934c60d28026396 Mon Sep 17 00:00:00 2001 -From: Jessica Liu -Date: Tue, 10 Mar 2026 14:16:00 +0800 -Subject: [PATCH 165/467] UPSTREAM: irqchip/riscv-aplic: Do not clear ACPI - dependencies on probe failure - -aplic_probe() calls acpi_dev_clear_dependencies() unconditionally at the -end, even when the preceding setup (MSI or direct mode) has failed. This is -incorrect because if the device failed to probe, it should not be -considered as active and should not clear dependencies for other devices -waiting on it. - -Fix this by returning immediately when the setup fails, skipping the ACPI -dependency cleanup. Also, explicitly return 0 on success instead of relying -on the value of 'rc' to make the success path clear. - -Fixes: 5122e380c23b ("irqchip/riscv-aplic: Add ACPI support") -Signed-off-by: Jessica Liu -Signed-off-by: Thomas Gleixner -Link: https://patch.msgid.link/20260310141600411Fu8H8-GXOOgKISU48Tjgx@zte.com.cn -(cherry picked from commit 620b6ded72a7f0f77be6ec44d0462bb85729ab7a) -Signed-off-by: Han Gao ---- - drivers/irqchip/irq-riscv-aplic-main.c | 11 +++++++---- - 1 file changed, 7 insertions(+), 4 deletions(-) - -diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c -index 4495ca26abf5..8775f188ea4f 100644 ---- a/drivers/irqchip/irq-riscv-aplic-main.c -+++ b/drivers/irqchip/irq-riscv-aplic-main.c -@@ -372,18 +372,21 @@ static int aplic_probe(struct platform_device *pdev) - rc = aplic_msi_setup(dev, regs); - else - rc = aplic_direct_setup(dev, regs); -- if (rc) -+ -+ if (rc) { - dev_err_probe(dev, rc, "failed to setup APLIC in %s mode\n", - msi_mode ? "MSI" : "direct"); -- else -- register_syscore(&aplic_syscore); -+ return rc; -+ } -+ -+ register_syscore(&aplic_syscore); - - #ifdef CONFIG_ACPI - if (!acpi_disabled) - acpi_dev_clear_dependencies(ACPI_COMPANION(dev)); - #endif - -- return rc; -+ return 0; - } - - static const struct of_device_id aplic_match[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch b/SPECS/linux-lts-kmhv2/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch new file mode 100644 index 0000000000..3f06b45545 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch @@ -0,0 +1,135 @@ +From 95da822dbecb61c821f0748e19304ec198992377 Mon Sep 17 00:00:00 2001 +From: Frank Li +Date: Mon, 29 Sep 2025 10:24:15 -0400 +Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: Add software-managed properties for + flattened model + +Add software-managed properties for the flattened model, which does not +need to use device tree properties to pass down information to the +common DWC3 core. + +Add 'properties' in dwc3_probe_data and set default values for existing +users (dwc3-qcom, dwc3-generic-plat). + +No functional changes. + +Acked-by: Thinh Nguyen +Signed-off-by: Frank Li +Link: https://lore.kernel.org/r/20250929-ls_dma_coherence-v5-2-2ebee578eb7e@nxp.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 7298c06d58e23c1c6e60180ab1ce069087ae38e2) +Signed-off-by: Han Gao +--- + drivers/usb/dwc3/core.c | 12 ++++++++++-- + drivers/usb/dwc3/dwc3-generic-plat.c | 1 + + drivers/usb/dwc3/dwc3-qcom.c | 1 + + drivers/usb/dwc3/glue.h | 14 ++++++++++++++ + 4 files changed, 26 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c +index a1f99c3b5f37..dd08b7f5b9a1 100644 +--- a/drivers/usb/dwc3/core.c ++++ b/drivers/usb/dwc3/core.c +@@ -1669,7 +1669,8 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc) + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true); + } + +-static void dwc3_get_software_properties(struct dwc3 *dwc) ++static void dwc3_get_software_properties(struct dwc3 *dwc, ++ const struct dwc3_properties *properties) + { + struct device *tmpdev; + u16 gsbuscfg0_reqinfo; +@@ -1677,6 +1678,12 @@ static void dwc3_get_software_properties(struct dwc3 *dwc) + + dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED; + ++ if (properties->gsbuscfg0_reqinfo != ++ DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) { ++ dwc->gsbuscfg0_reqinfo = properties->gsbuscfg0_reqinfo; ++ return; ++ } ++ + /* + * Iterate over all parent nodes for finding swnode properties + * and non-DT (non-ABI) properties. +@@ -2224,7 +2231,7 @@ int dwc3_core_probe(const struct dwc3_probe_data *data) + + dwc3_get_properties(dwc); + +- dwc3_get_software_properties(dwc); ++ dwc3_get_software_properties(dwc, &data->properties); + + dwc->usb_psy = dwc3_get_usb_power_supply(dwc); + if (IS_ERR(dwc->usb_psy)) +@@ -2374,6 +2381,7 @@ static int dwc3_probe(struct platform_device *pdev) + + probe_data.dwc = dwc; + probe_data.res = res; ++ probe_data.properties = DWC3_DEFAULT_PROPERTIES; + + return dwc3_core_probe(&probe_data); + } +diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c +index f8ad79c08c4e..ba3aec4cb963 100644 +--- a/drivers/usb/dwc3/dwc3-generic-plat.c ++++ b/drivers/usb/dwc3/dwc3-generic-plat.c +@@ -75,6 +75,7 @@ static int dwc3_generic_probe(struct platform_device *pdev) + probe_data.dwc = &dwc3g->dwc; + probe_data.res = res; + probe_data.ignore_clocks_and_resets = true; ++ probe_data.properties = DWC3_DEFAULT_PROPERTIES; + ret = dwc3_core_probe(&probe_data); + if (ret) + return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); +diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c +index ded2ca86670c..9ac75547820d 100644 +--- a/drivers/usb/dwc3/dwc3-qcom.c ++++ b/drivers/usb/dwc3/dwc3-qcom.c +@@ -704,6 +704,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev) + probe_data.dwc = &qcom->dwc; + probe_data.res = &res; + probe_data.ignore_clocks_and_resets = true; ++ probe_data.properties = DWC3_DEFAULT_PROPERTIES; + ret = dwc3_core_probe(&probe_data); + if (ret) { + ret = dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); +diff --git a/drivers/usb/dwc3/glue.h b/drivers/usb/dwc3/glue.h +index 2efd00e763be..cc6e138bd9ef 100644 +--- a/drivers/usb/dwc3/glue.h ++++ b/drivers/usb/dwc3/glue.h +@@ -9,17 +9,31 @@ + #include + #include "core.h" + ++/** ++ * dwc3_properties: DWC3 core properties ++ * @gsbuscfg0_reqinfo: Value to be programmed in the GSBUSCFG0.REQINFO field ++ */ ++struct dwc3_properties { ++ u32 gsbuscfg0_reqinfo; ++}; ++ ++#define DWC3_DEFAULT_PROPERTIES ((struct dwc3_properties){ \ ++ .gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED, \ ++ }) ++ + /** + * dwc3_probe_data: Initialization parameters passed to dwc3_core_probe() + * @dwc: Reference to dwc3 context structure + * @res: resource for the DWC3 core mmio region + * @ignore_clocks_and_resets: clocks and resets defined for the device should + * be ignored by the DWC3 core, as they are managed by the glue ++ * @properties: dwc3 software manage properties + */ + struct dwc3_probe_data { + struct dwc3 *dwc; + struct resource *res; + bool ignore_clocks_and_resets; ++ struct dwc3_properties properties; + }; + + int dwc3_core_probe(const struct dwc3_probe_data *data); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0166-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch b/SPECS/linux-lts-kmhv2/0166-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch deleted file mode 100644 index e1aff8100a..0000000000 --- a/SPECS/linux-lts-kmhv2/0166-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 8ae93b636f92b573aec71e026e1959d7342e76f5 Mon Sep 17 00:00:00 2001 -From: Jessica Liu -Date: Tue, 10 Mar 2026 14:17:31 +0800 -Subject: [PATCH 166/467] UPSTREAM: irqchip/riscv-aplic: Register syscore - operations only once - -Since commit 95a8ddde3660 ("irqchip/riscv-aplic: Preserve APLIC -states across suspend/resume"), when multiple NUMA nodes exist -and AIA is not configured as "none", aplic_probe() is called -multiple times. This leads to register_syscore(&aplic_syscore) -being invoked repeatedly, causing the following Oops: - - list_add double add: new=ffffffffb91461f0, prev=ffffffffb91461f0, next=ffffffffb915c408. - [] __list_add_valid_or_report+0x60/0xc0 - [] register_syscore+0x3e/0x70 - [] aplic_probe+0xc6/0x112 - -Fix this by registering syscore operations only once, using a static -variable aplic_syscore_registered to track registration. - -[ tglx: Trim backtrace properly ] - -Fixes: 95a8ddde3660 ("irqchip/riscv-aplic: Preserve APLIC states across suspend/resume") -Signed-off-by: Jessica Liu -Signed-off-by: Thomas Gleixner -Link: https://patch.msgid.link/20260310141731145xMwLsyvXl9Gw-m6A4VRYj@zte.com.cn -(cherry picked from commit b330fbfd34d7624bec62b99ad88dba2614326a19) -Signed-off-by: Han Gao ---- - drivers/irqchip/irq-riscv-aplic-main.c | 12 +++++++++++- - 1 file changed, 11 insertions(+), 1 deletion(-) - -diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c -index 8775f188ea4f..9f53979b6962 100644 ---- a/drivers/irqchip/irq-riscv-aplic-main.c -+++ b/drivers/irqchip/irq-riscv-aplic-main.c -@@ -116,6 +116,16 @@ static struct syscore aplic_syscore = { - .ops = &aplic_syscore_ops, - }; - -+static bool aplic_syscore_registered __ro_after_init; -+ -+static void aplic_syscore_init(void) -+{ -+ if (!aplic_syscore_registered) { -+ register_syscore(&aplic_syscore); -+ aplic_syscore_registered = true; -+ } -+} -+ - static int aplic_pm_notifier(struct notifier_block *nb, unsigned long action, void *data) - { - struct aplic_priv *priv = container_of(nb, struct aplic_priv, genpd_nb); -@@ -379,7 +389,7 @@ static int aplic_probe(struct platform_device *pdev) - return rc; - } - -- register_syscore(&aplic_syscore); -+ aplic_syscore_init(); - - #ifdef CONFIG_ACPI - if (!acpi_disabled) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch b/SPECS/linux-lts-kmhv2/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch new file mode 100644 index 0000000000..0ff5ac0f10 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch @@ -0,0 +1,63 @@ +From 336f616b6d4b4f53eb9ffdf8822f067ff0820efa Mon Sep 17 00:00:00 2001 +From: Frank Li +Date: Mon, 29 Sep 2025 10:24:16 -0400 +Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: dwc3-generic-plat: Add layerscape + dwc3 support + +Add layerscape dwc3 support by using flatten dwc3 core library. Layerscape +dwc3 need set gsbuscfg0-reqinfo as 0x2222 when dma-coherence set. + +Signed-off-by: Frank Li +Acked-by: Thinh Nguyen +Link: https://lore.kernel.org/r/20250929-ls_dma_coherence-v5-3-2ebee578eb7e@nxp.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 1c97fc901fb6318aca0160da96736d0bc136ddcd) +Signed-off-by: Han Gao +--- + drivers/usb/dwc3/dwc3-generic-plat.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c +index ba3aec4cb963..e869c7de7bc8 100644 +--- a/drivers/usb/dwc3/dwc3-generic-plat.c ++++ b/drivers/usb/dwc3/dwc3-generic-plat.c +@@ -29,6 +29,7 @@ static void dwc3_generic_reset_control_assert(void *data) + + static int dwc3_generic_probe(struct platform_device *pdev) + { ++ const struct dwc3_properties *properties; + struct dwc3_probe_data probe_data = {}; + struct device *dev = &pdev->dev; + struct dwc3_generic *dwc3g; +@@ -75,7 +76,13 @@ static int dwc3_generic_probe(struct platform_device *pdev) + probe_data.dwc = &dwc3g->dwc; + probe_data.res = res; + probe_data.ignore_clocks_and_resets = true; +- probe_data.properties = DWC3_DEFAULT_PROPERTIES; ++ ++ properties = of_device_get_match_data(dev); ++ if (properties) ++ probe_data.properties = *properties; ++ else ++ probe_data.properties = DWC3_DEFAULT_PROPERTIES; ++ + ret = dwc3_core_probe(&probe_data); + if (ret) + return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); +@@ -143,8 +150,13 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { + dwc3_generic_runtime_idle) + }; + ++static const struct dwc3_properties fsl_ls1028_dwc3 = { ++ .gsbuscfg0_reqinfo = 0x2222, ++}; ++ + static const struct of_device_id dwc3_generic_of_match[] = { + { .compatible = "spacemit,k1-dwc3", }, ++ { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch b/SPECS/linux-lts-kmhv2/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch new file mode 100644 index 0000000000..85f93bef67 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch @@ -0,0 +1,124 @@ +From 4b1c4f9c84bda4bcf482c0efe496c3a6648372ca Mon Sep 17 00:00:00 2001 +From: Hang Cao +Date: Wed, 12 Nov 2025 13:53:21 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: Add ESWIN EIC7700 USB + controller + +Add Device Tree binding documentation for the ESWIN EIC7700 +usb controller module. + +Signed-off-by: Senchuan Zhang +Signed-off-by: Hang Cao +Reviewed-by: Rob Herring (Arm) +Link: https://patch.msgid.link/20251112055321.1638-1-caohang@eswincomputing.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit c640a4239db53e077dd5fd20db52fbc8b64f290b) +Signed-off-by: Han Gao +--- + .../bindings/usb/eswin,eic7700-usb.yaml | 94 +++++++++++++++++++ + 1 file changed, 94 insertions(+) + create mode 100644 Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml + +diff --git a/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml +new file mode 100644 +index 000000000000..41c3b1b98991 +--- /dev/null ++++ b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml +@@ -0,0 +1,94 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/usb/eswin,eic7700-usb.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: ESWIN EIC7700 SoC Usb Controller ++ ++maintainers: ++ - Wei Yang ++ - Senchuan Zhang ++ - Hang Cao ++ ++description: ++ The Usb controller on EIC7700 SoC. ++ ++allOf: ++ - $ref: snps,dwc3-common.yaml# ++ ++properties: ++ compatible: ++ const: eswin,eic7700-dwc3 ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ interrupt-names: ++ items: ++ - const: peripheral ++ ++ clocks: ++ maxItems: 3 ++ ++ clock-names: ++ items: ++ - const: aclk ++ - const: cfg ++ - const: usb_en ++ ++ resets: ++ maxItems: 2 ++ ++ reset-names: ++ items: ++ - const: vaux ++ - const: usb_rst ++ ++ eswin,hsp-sp-csr: ++ description: ++ HSP CSR is to control and get status of different high-speed peripherals ++ (such as Ethernet, USB, SATA, etc.) via register, which can tune ++ board-level's parameters of PHY, etc. ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle to HSP Register Controller hsp_sp_csr node. ++ - description: USB bus register offset. ++ - description: AXI low power register offset. ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - interrupts ++ - interrupt-names ++ - resets ++ - reset-names ++ - eswin,hsp-sp-csr ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ usb@50480000 { ++ compatible = "eswin,eic7700-dwc3"; ++ reg = <0x50480000 0x10000>; ++ clocks = <&clock 135>, ++ <&clock 136>, ++ <&hspcrg 18>; ++ clock-names = "aclk", "cfg", "usb_en"; ++ interrupt-parent = <&plic>; ++ interrupts = <85>; ++ interrupt-names = "peripheral"; ++ resets = <&reset 84>, <&hspcrg 2>; ++ reset-names = "vaux", "usb_rst"; ++ dr_mode = "peripheral"; ++ maximum-speed = "high-speed"; ++ phy_type = "utmi"; ++ eswin,hsp-sp-csr = <&hsp_sp_csr 0x800 0x818>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0167-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch b/SPECS/linux-lts-kmhv2/0167-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch deleted file mode 100644 index 9f4bf625b0..0000000000 --- a/SPECS/linux-lts-kmhv2/0167-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch +++ /dev/null @@ -1,96 +0,0 @@ -From c8008d5da7b2415832577084ccba87ecd7a44f39 Mon Sep 17 00:00:00 2001 -From: Frank Li -Date: Mon, 29 Sep 2025 10:24:14 -0400 -Subject: [PATCH 167/467] UPSTREAM: dt-bindings: usb: add missed compatible - string for arm64 layerscape - -Add missed compatible string for arm64 layerscape platform. Allow these -fallback to fsl,ls1028a-dwc3. - -Remove fallback snps,dwc3 because layerscape dwc3 is not full compatible -with common snps,dwc3 device, a special value gsburstcfg0 need be set when -dma coherence enabled. - -Allow iommus property. - -Change ref to snps,dwc3-common.yaml to use dwc3 flatten library. - -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Frank Li -Link: https://lore.kernel.org/r/20250929-ls_dma_coherence-v5-1-2ebee578eb7e@nxp.com -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit b9f1c762a4de17d93017fbd12b9941caff6d3078) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/usb/fsl,ls1028a.yaml | 33 ++++++++++--------- - 1 file changed, 18 insertions(+), 15 deletions(-) - -diff --git a/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml b/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml -index a44bdf391887..4784f057264a 100644 ---- a/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml -+++ b/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml -@@ -9,21 +9,19 @@ title: Freescale layerscape SuperSpeed DWC3 USB SoC controller - maintainers: - - Frank Li - --select: -- properties: -- compatible: -- contains: -- enum: -- - fsl,ls1028a-dwc3 -- required: -- - compatible -- - properties: - compatible: -- items: -- - enum: -- - fsl,ls1028a-dwc3 -- - const: snps,dwc3 -+ oneOf: -+ - items: -+ - enum: -+ - fsl,ls1012a-dwc3 -+ - fsl,ls1043a-dwc3 -+ - fsl,ls1046a-dwc3 -+ - fsl,ls1088a-dwc3 -+ - fsl,ls208xa-dwc3 -+ - fsl,lx2160a-dwc3 -+ - const: fsl,ls1028a-dwc3 -+ - const: fsl,ls1028a-dwc3 - - reg: - maxItems: 1 -@@ -31,6 +29,11 @@ properties: - interrupts: - maxItems: 1 - -+ iommus: -+ maxItems: 1 -+ -+ dma-coherent: true -+ - unevaluatedProperties: false - - required: -@@ -39,14 +42,14 @@ required: - - interrupts - - allOf: -- - $ref: snps,dwc3.yaml# -+ - $ref: snps,dwc3-common.yaml# - - examples: - - | - #include - - usb@fe800000 { -- compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; -+ compatible = "fsl,ls1028a-dwc3"; - reg = <0xfe800000 0x100000>; - interrupts = ; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0168-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch b/SPECS/linux-lts-kmhv2/0168-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch deleted file mode 100644 index 9c997b8d12..0000000000 --- a/SPECS/linux-lts-kmhv2/0168-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch +++ /dev/null @@ -1,135 +0,0 @@ -From ec754531fae0f05264d641470206d128b8955455 Mon Sep 17 00:00:00 2001 -From: Frank Li -Date: Mon, 29 Sep 2025 10:24:15 -0400 -Subject: [PATCH 168/467] UPSTREAM: usb: dwc3: Add software-managed properties - for flattened model - -Add software-managed properties for the flattened model, which does not -need to use device tree properties to pass down information to the -common DWC3 core. - -Add 'properties' in dwc3_probe_data and set default values for existing -users (dwc3-qcom, dwc3-generic-plat). - -No functional changes. - -Acked-by: Thinh Nguyen -Signed-off-by: Frank Li -Link: https://lore.kernel.org/r/20250929-ls_dma_coherence-v5-2-2ebee578eb7e@nxp.com -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit 7298c06d58e23c1c6e60180ab1ce069087ae38e2) -Signed-off-by: Han Gao ---- - drivers/usb/dwc3/core.c | 12 ++++++++++-- - drivers/usb/dwc3/dwc3-generic-plat.c | 1 + - drivers/usb/dwc3/dwc3-qcom.c | 1 + - drivers/usb/dwc3/glue.h | 14 ++++++++++++++ - 4 files changed, 26 insertions(+), 2 deletions(-) - -diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c -index a1f99c3b5f37..dd08b7f5b9a1 100644 ---- a/drivers/usb/dwc3/core.c -+++ b/drivers/usb/dwc3/core.c -@@ -1669,7 +1669,8 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc) - dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true); - } - --static void dwc3_get_software_properties(struct dwc3 *dwc) -+static void dwc3_get_software_properties(struct dwc3 *dwc, -+ const struct dwc3_properties *properties) - { - struct device *tmpdev; - u16 gsbuscfg0_reqinfo; -@@ -1677,6 +1678,12 @@ static void dwc3_get_software_properties(struct dwc3 *dwc) - - dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED; - -+ if (properties->gsbuscfg0_reqinfo != -+ DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) { -+ dwc->gsbuscfg0_reqinfo = properties->gsbuscfg0_reqinfo; -+ return; -+ } -+ - /* - * Iterate over all parent nodes for finding swnode properties - * and non-DT (non-ABI) properties. -@@ -2224,7 +2231,7 @@ int dwc3_core_probe(const struct dwc3_probe_data *data) - - dwc3_get_properties(dwc); - -- dwc3_get_software_properties(dwc); -+ dwc3_get_software_properties(dwc, &data->properties); - - dwc->usb_psy = dwc3_get_usb_power_supply(dwc); - if (IS_ERR(dwc->usb_psy)) -@@ -2374,6 +2381,7 @@ static int dwc3_probe(struct platform_device *pdev) - - probe_data.dwc = dwc; - probe_data.res = res; -+ probe_data.properties = DWC3_DEFAULT_PROPERTIES; - - return dwc3_core_probe(&probe_data); - } -diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c -index f8ad79c08c4e..ba3aec4cb963 100644 ---- a/drivers/usb/dwc3/dwc3-generic-plat.c -+++ b/drivers/usb/dwc3/dwc3-generic-plat.c -@@ -75,6 +75,7 @@ static int dwc3_generic_probe(struct platform_device *pdev) - probe_data.dwc = &dwc3g->dwc; - probe_data.res = res; - probe_data.ignore_clocks_and_resets = true; -+ probe_data.properties = DWC3_DEFAULT_PROPERTIES; - ret = dwc3_core_probe(&probe_data); - if (ret) - return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); -diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c -index ded2ca86670c..9ac75547820d 100644 ---- a/drivers/usb/dwc3/dwc3-qcom.c -+++ b/drivers/usb/dwc3/dwc3-qcom.c -@@ -704,6 +704,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev) - probe_data.dwc = &qcom->dwc; - probe_data.res = &res; - probe_data.ignore_clocks_and_resets = true; -+ probe_data.properties = DWC3_DEFAULT_PROPERTIES; - ret = dwc3_core_probe(&probe_data); - if (ret) { - ret = dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); -diff --git a/drivers/usb/dwc3/glue.h b/drivers/usb/dwc3/glue.h -index 2efd00e763be..cc6e138bd9ef 100644 ---- a/drivers/usb/dwc3/glue.h -+++ b/drivers/usb/dwc3/glue.h -@@ -9,17 +9,31 @@ - #include - #include "core.h" - -+/** -+ * dwc3_properties: DWC3 core properties -+ * @gsbuscfg0_reqinfo: Value to be programmed in the GSBUSCFG0.REQINFO field -+ */ -+struct dwc3_properties { -+ u32 gsbuscfg0_reqinfo; -+}; -+ -+#define DWC3_DEFAULT_PROPERTIES ((struct dwc3_properties){ \ -+ .gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED, \ -+ }) -+ - /** - * dwc3_probe_data: Initialization parameters passed to dwc3_core_probe() - * @dwc: Reference to dwc3 context structure - * @res: resource for the DWC3 core mmio region - * @ignore_clocks_and_resets: clocks and resets defined for the device should - * be ignored by the DWC3 core, as they are managed by the glue -+ * @properties: dwc3 software manage properties - */ - struct dwc3_probe_data { - struct dwc3 *dwc; - struct resource *res; - bool ignore_clocks_and_resets; -+ struct dwc3_properties properties; - }; - - int dwc3_core_probe(const struct dwc3_probe_data *data); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch b/SPECS/linux-lts-kmhv2/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch new file mode 100644 index 0000000000..c664c16a80 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch @@ -0,0 +1,149 @@ +From a2ce6ee9f23da731a7f30c0869f5b48c66d727e1 Mon Sep 17 00:00:00 2001 +From: Hang Cao +Date: Wed, 12 Nov 2025 13:53:45 +0800 +Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: eic7700: Add EIC7700 USB driver + +The EIC7700 instantiates two USB 3.0 DWC3 IPs, each of which is backward +compatible with USB interfaces. It supports Super-speed (5Gb/s), DRD mode, +and compatible with xHCI 1.1, etc. Each of instances supports 16 endpoints +in device's mode and max 64 devices in host's mode. + +This module needs to interact with the NOC via the AXI master bus, thus +requiring some HSP configuration operations to achieve this. Ops include +bus filter, pm signal or status to usb bus and so on. + +Acked-by: Thinh Nguyen +Signed-off-by: Senchuan Zhang +Signed-off-by: Hang Cao +Link: https://patch.msgid.link/20251112055346.1655-1-caohang@eswincomputing.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit e05d28b759c28660c28a36bf0add178edcc3466e) +Signed-off-by: Han Gao +--- + drivers/usb/dwc3/dwc3-generic-plat.c | 71 +++++++++++++++++++++++++--- + 1 file changed, 64 insertions(+), 7 deletions(-) + +diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c +index e869c7de7bc8..e846844e0023 100644 +--- a/drivers/usb/dwc3/dwc3-generic-plat.c ++++ b/drivers/usb/dwc3/dwc3-generic-plat.c +@@ -10,8 +10,16 @@ + #include + #include + #include ++#include ++#include + #include "glue.h" + ++#define EIC7700_HSP_BUS_FILTER_EN BIT(0) ++#define EIC7700_HSP_BUS_CLKEN_GM BIT(9) ++#define EIC7700_HSP_BUS_CLKEN_GS BIT(16) ++#define EIC7700_HSP_AXI_LP_XM_CSYSREQ BIT(0) ++#define EIC7700_HSP_AXI_LP_XS_CSYSREQ BIT(16) ++ + struct dwc3_generic { + struct device *dev; + struct dwc3 dwc; +@@ -20,6 +28,11 @@ struct dwc3_generic { + struct reset_control *resets; + }; + ++struct dwc3_generic_config { ++ int (*init)(struct dwc3_generic *dwc3g); ++ struct dwc3_properties properties; ++}; ++ + #define to_dwc3_generic(d) container_of((d), struct dwc3_generic, dwc) + + static void dwc3_generic_reset_control_assert(void *data) +@@ -27,9 +40,38 @@ static void dwc3_generic_reset_control_assert(void *data) + reset_control_assert(data); + } + ++static int dwc3_eic7700_init(struct dwc3_generic *dwc3g) ++{ ++ struct device *dev = dwc3g->dev; ++ struct regmap *regmap; ++ u32 hsp_usb_axi_lp; ++ u32 hsp_usb_bus; ++ u32 args[2]; ++ u32 val; ++ ++ regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, ++ "eswin,hsp-sp-csr", ++ ARRAY_SIZE(args), args); ++ if (IS_ERR(regmap)) { ++ dev_err(dev, "No hsp-sp-csr phandle specified\n"); ++ return PTR_ERR(regmap); ++ } ++ ++ hsp_usb_bus = args[0]; ++ hsp_usb_axi_lp = args[1]; ++ ++ regmap_read(regmap, hsp_usb_bus, &val); ++ regmap_write(regmap, hsp_usb_bus, val | EIC7700_HSP_BUS_FILTER_EN | ++ EIC7700_HSP_BUS_CLKEN_GM | EIC7700_HSP_BUS_CLKEN_GS); ++ ++ regmap_write(regmap, hsp_usb_axi_lp, EIC7700_HSP_AXI_LP_XM_CSYSREQ | ++ EIC7700_HSP_AXI_LP_XS_CSYSREQ); ++ return 0; ++} ++ + static int dwc3_generic_probe(struct platform_device *pdev) + { +- const struct dwc3_properties *properties; ++ const struct dwc3_generic_config *plat_config; + struct dwc3_probe_data probe_data = {}; + struct device *dev = &pdev->dev; + struct dwc3_generic *dwc3g; +@@ -77,12 +119,21 @@ static int dwc3_generic_probe(struct platform_device *pdev) + probe_data.res = res; + probe_data.ignore_clocks_and_resets = true; + +- properties = of_device_get_match_data(dev); +- if (properties) +- probe_data.properties = *properties; +- else ++ plat_config = of_device_get_match_data(dev); ++ if (!plat_config) { + probe_data.properties = DWC3_DEFAULT_PROPERTIES; ++ goto core_probe; ++ } + ++ probe_data.properties = plat_config->properties; ++ if (plat_config->init) { ++ ret = plat_config->init(dwc3g); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "failed to init platform\n"); ++ } ++ ++core_probe: + ret = dwc3_core_probe(&probe_data); + if (ret) + return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); +@@ -150,13 +201,19 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { + dwc3_generic_runtime_idle) + }; + +-static const struct dwc3_properties fsl_ls1028_dwc3 = { +- .gsbuscfg0_reqinfo = 0x2222, ++static const struct dwc3_generic_config fsl_ls1028_dwc3 = { ++ .properties.gsbuscfg0_reqinfo = 0x2222, ++}; ++ ++static const struct dwc3_generic_config eic7700_dwc3 = { ++ .init = dwc3_eic7700_init, ++ .properties = DWC3_DEFAULT_PROPERTIES, + }; + + static const struct of_device_id dwc3_generic_of_match[] = { + { .compatible = "spacemit,k1-dwc3", }, + { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, ++ { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch b/SPECS/linux-lts-kmhv2/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch new file mode 100644 index 0000000000..0830c4cd17 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch @@ -0,0 +1,58 @@ +From 9acac5b146b312ddb8525d13c2ba273dff6508a0 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 16 Feb 2026 23:26:53 +0800 +Subject: [RUYI PATCH] UPSTREAM: phy: k1-usb: add disconnect function support + +A disconnect status BIT of USB2 PHY need to be cleared, otherwise +it will fail to work properly during next connection when devices +connect to roothub directly. + +Fixes: fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller") +Signed-off-by: Yixun Lan +Reviewed-by: Vladimir Oltean +Link: https://patch.msgid.link/20260216152653.25244-1-dlan@kernel.org +Signed-off-by: Vinod Koul +(cherry picked from commit f0cf0a882a02dcf28547f32264f6fd37e9a7b147) +Signed-off-by: Han Gao +--- + drivers/phy/spacemit/phy-k1-usb2.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c +index 342061380012..9215d0b223b2 100644 +--- a/drivers/phy/spacemit/phy-k1-usb2.c ++++ b/drivers/phy/spacemit/phy-k1-usb2.c +@@ -48,6 +48,9 @@ + #define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */ + #define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */ + ++#define PHY_K1_HS_HOST_DISC 0x40 ++#define PHY_K1_HS_HOST_DISC_CLR BIT(0) ++ + #define PHY_PLL_DIV_CFG 0x98 + #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) + #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) +@@ -142,9 +145,20 @@ static int spacemit_usb2phy_exit(struct phy *phy) + return 0; + } + ++static int spacemit_usb2phy_disconnect(struct phy *phy, int port) ++{ ++ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); ++ ++ regmap_update_bits(sphy->regmap_base, PHY_K1_HS_HOST_DISC, ++ PHY_K1_HS_HOST_DISC_CLR, PHY_K1_HS_HOST_DISC_CLR); ++ ++ return 0; ++} ++ + static const struct phy_ops spacemit_usb2phy_ops = { + .init = spacemit_usb2phy_init, + .exit = spacemit_usb2phy_exit, ++ .disconnect = spacemit_usb2phy_disconnect, + .owner = THIS_MODULE, + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0169-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch b/SPECS/linux-lts-kmhv2/0169-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch deleted file mode 100644 index 5518a57821..0000000000 --- a/SPECS/linux-lts-kmhv2/0169-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 2ad4fd487b3a00d0f606fecc70edc0fe56d6b43e Mon Sep 17 00:00:00 2001 -From: Frank Li -Date: Mon, 29 Sep 2025 10:24:16 -0400 -Subject: [PATCH 169/467] UPSTREAM: usb: dwc3: dwc3-generic-plat: Add - layerscape dwc3 support - -Add layerscape dwc3 support by using flatten dwc3 core library. Layerscape -dwc3 need set gsbuscfg0-reqinfo as 0x2222 when dma-coherence set. - -Signed-off-by: Frank Li -Acked-by: Thinh Nguyen -Link: https://lore.kernel.org/r/20250929-ls_dma_coherence-v5-3-2ebee578eb7e@nxp.com -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit 1c97fc901fb6318aca0160da96736d0bc136ddcd) -Signed-off-by: Han Gao ---- - drivers/usb/dwc3/dwc3-generic-plat.c | 14 +++++++++++++- - 1 file changed, 13 insertions(+), 1 deletion(-) - -diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c -index ba3aec4cb963..e869c7de7bc8 100644 ---- a/drivers/usb/dwc3/dwc3-generic-plat.c -+++ b/drivers/usb/dwc3/dwc3-generic-plat.c -@@ -29,6 +29,7 @@ static void dwc3_generic_reset_control_assert(void *data) - - static int dwc3_generic_probe(struct platform_device *pdev) - { -+ const struct dwc3_properties *properties; - struct dwc3_probe_data probe_data = {}; - struct device *dev = &pdev->dev; - struct dwc3_generic *dwc3g; -@@ -75,7 +76,13 @@ static int dwc3_generic_probe(struct platform_device *pdev) - probe_data.dwc = &dwc3g->dwc; - probe_data.res = res; - probe_data.ignore_clocks_and_resets = true; -- probe_data.properties = DWC3_DEFAULT_PROPERTIES; -+ -+ properties = of_device_get_match_data(dev); -+ if (properties) -+ probe_data.properties = *properties; -+ else -+ probe_data.properties = DWC3_DEFAULT_PROPERTIES; -+ - ret = dwc3_core_probe(&probe_data); - if (ret) - return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); -@@ -143,8 +150,13 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { - dwc3_generic_runtime_idle) - }; - -+static const struct dwc3_properties fsl_ls1028_dwc3 = { -+ .gsbuscfg0_reqinfo = 0x2222, -+}; -+ - static const struct of_device_id dwc3_generic_of_match[] = { - { .compatible = "spacemit,k1-dwc3", }, -+ { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch b/SPECS/linux-lts-kmhv2/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch new file mode 100644 index 0000000000..f563981345 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch @@ -0,0 +1,49 @@ +From 8aba9c8ffd6f7bf33950abcc2bb276254f6749cf Mon Sep 17 00:00:00 2001 +From: Nirmoy Das +Date: Wed, 17 Dec 2025 07:45:28 -0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: Add ASPEED vendor ID to pci_ids.h + +Add PCI_VENDOR_ID_ASPEED to the shared pci_ids.h header and remove the +duplicate local definition from ehci-pci.c. + +This prepares for adding a PCI quirk for ASPEED devices. + +Signed-off-by: Nirmoy Das +Signed-off-by: Bjorn Helgaas +Reviewed-by: Jason Gunthorpe +Link: https://patch.msgid.link/20251217154529.377586-1-nirmoyd@nvidia.com +(cherry picked from commit eeb95c07d5fcaafb1829d5307ce4290cf1dc3190) +Signed-off-by: Han Gao +--- + drivers/usb/host/ehci-pci.c | 1 - + include/linux/pci_ids.h | 2 ++ + 2 files changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c +index 889dc4426271..bd3a63555594 100644 +--- a/drivers/usb/host/ehci-pci.c ++++ b/drivers/usb/host/ehci-pci.c +@@ -21,7 +21,6 @@ static const char hcd_name[] = "ehci-pci"; + /* defined here to avoid adding to pci_ids.h for single instance use */ + #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 + +-#define PCI_VENDOR_ID_ASPEED 0x1a03 + #define PCI_DEVICE_ID_ASPEED_EHCI 0x2603 + + /*-------------------------------------------------------------------------*/ +diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h +index 03b7c0380f71..2b6692a5005f 100644 +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2583,6 +2583,8 @@ + #define PCI_DEVICE_ID_NETRONOME_NFP3800_VF 0x3803 + #define PCI_DEVICE_ID_NETRONOME_NFP6000_VF 0x6003 + ++#define PCI_VENDOR_ID_ASPEED 0x1a03 ++ + #define PCI_VENDOR_ID_QMI 0x1a32 + + #define PCI_VENDOR_ID_AZWAVE 0x1a3b +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0170-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch b/SPECS/linux-lts-kmhv2/0170-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch deleted file mode 100644 index 6b5f344dd1..0000000000 --- a/SPECS/linux-lts-kmhv2/0170-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch +++ /dev/null @@ -1,124 +0,0 @@ -From fd6aed5b51bb1817267103bf54285d06b25b5d2f Mon Sep 17 00:00:00 2001 -From: Hang Cao -Date: Wed, 12 Nov 2025 13:53:21 +0800 -Subject: [PATCH 170/467] UPSTREAM: dt-bindings: usb: Add ESWIN EIC7700 USB - controller - -Add Device Tree binding documentation for the ESWIN EIC7700 -usb controller module. - -Signed-off-by: Senchuan Zhang -Signed-off-by: Hang Cao -Reviewed-by: Rob Herring (Arm) -Link: https://patch.msgid.link/20251112055321.1638-1-caohang@eswincomputing.com -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit c640a4239db53e077dd5fd20db52fbc8b64f290b) -Signed-off-by: Han Gao ---- - .../bindings/usb/eswin,eic7700-usb.yaml | 94 +++++++++++++++++++ - 1 file changed, 94 insertions(+) - create mode 100644 Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml - -diff --git a/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml -new file mode 100644 -index 000000000000..41c3b1b98991 ---- /dev/null -+++ b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml -@@ -0,0 +1,94 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/usb/eswin,eic7700-usb.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: ESWIN EIC7700 SoC Usb Controller -+ -+maintainers: -+ - Wei Yang -+ - Senchuan Zhang -+ - Hang Cao -+ -+description: -+ The Usb controller on EIC7700 SoC. -+ -+allOf: -+ - $ref: snps,dwc3-common.yaml# -+ -+properties: -+ compatible: -+ const: eswin,eic7700-dwc3 -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ interrupt-names: -+ items: -+ - const: peripheral -+ -+ clocks: -+ maxItems: 3 -+ -+ clock-names: -+ items: -+ - const: aclk -+ - const: cfg -+ - const: usb_en -+ -+ resets: -+ maxItems: 2 -+ -+ reset-names: -+ items: -+ - const: vaux -+ - const: usb_rst -+ -+ eswin,hsp-sp-csr: -+ description: -+ HSP CSR is to control and get status of different high-speed peripherals -+ (such as Ethernet, USB, SATA, etc.) via register, which can tune -+ board-level's parameters of PHY, etc. -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ items: -+ - items: -+ - description: phandle to HSP Register Controller hsp_sp_csr node. -+ - description: USB bus register offset. -+ - description: AXI low power register offset. -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - interrupt-names -+ - resets -+ - reset-names -+ - eswin,hsp-sp-csr -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ usb@50480000 { -+ compatible = "eswin,eic7700-dwc3"; -+ reg = <0x50480000 0x10000>; -+ clocks = <&clock 135>, -+ <&clock 136>, -+ <&hspcrg 18>; -+ clock-names = "aclk", "cfg", "usb_en"; -+ interrupt-parent = <&plic>; -+ interrupts = <85>; -+ interrupt-names = "peripheral"; -+ resets = <&reset 84>, <&hspcrg 2>; -+ reset-names = "vaux", "usb_rst"; -+ dr_mode = "peripheral"; -+ maximum-speed = "high-speed"; -+ phy_type = "utmi"; -+ eswin,hsp-sp-csr = <&hsp_sp_csr 0x800 0x818>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch b/SPECS/linux-lts-kmhv2/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch new file mode 100644 index 0000000000..dba743541d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch @@ -0,0 +1,89 @@ +From ebc23bfadb5fbe0d0f28b65fd9c6837238e6e941 Mon Sep 17 00:00:00 2001 +From: Nirmoy Das +Date: Wed, 17 Dec 2025 07:45:29 -0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: Add PCI_BRIDGE_NO_ALIAS quirk for ASPEED + AST1150 + +ASPEED BMC controllers have VGA and USB functions behind a PCIe-to-PCI +bridge that causes them to share the same StreamID: + + [e0]---00.0-[e1-e2]----00.0-[e2]--+-00.0 ASPEED Graphics Family + \-02.0 ASPEED USB Controller + +Both devices get StreamID 0x5e200 due to bridge aliasing, causing the USB +controller to be rejected with 'Aliasing StreamID unsupported'. + +Per ASPEED, the AST1150 doesn't use a real PCI bus and always forwards +the original Requester ID from downstream devices rather than replacing +it with any alias. + +Add a new PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS flag and apply it to the +AST1150. + +Suggested-by: Jason Gunthorpe +Signed-off-by: Nirmoy Das +Signed-off-by: Bjorn Helgaas +Reviewed-by: Robin Murphy +Reviewed-by: Jason Gunthorpe +Link: https://patch.msgid.link/20251217154529.377586-2-nirmoyd@nvidia.com +(cherry picked from commit 550a190494a0d3e933dd6f3b2e9c430f94a30a8c) +Signed-off-by: Han Gao +--- + drivers/pci/quirks.c | 10 ++++++++++ + drivers/pci/search.c | 2 ++ + include/linux/pci.h | 5 +++++ + 3 files changed, 17 insertions(+) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index d32a47e81fcf..481e4186a5c1 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -4481,6 +4481,16 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, + quirk_bridge_cavm_thrx2_pcie_root); + ++/* ++ * AST1150 doesn't use a real PCI bus and always forwards the requester ID ++ * from downstream devices. ++ */ ++static void quirk_aspeed_pci_bridge_no_alias(struct pci_dev *pdev) ++{ ++ pdev->dev_flags |= PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS; ++} ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASPEED, 0x1150, quirk_aspeed_pci_bridge_no_alias); ++ + /* + * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) + * class code. Fix it. +diff --git a/drivers/pci/search.c b/drivers/pci/search.c +index 53840634fbfc..b3c9e3d82201 100644 +--- a/drivers/pci/search.c ++++ b/drivers/pci/search.c +@@ -86,6 +86,8 @@ int pci_for_each_dma_alias(struct pci_dev *pdev, + case PCI_EXP_TYPE_DOWNSTREAM: + continue; + case PCI_EXP_TYPE_PCI_BRIDGE: ++ if (tmp->dev_flags & PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS) ++ continue; + ret = fn(tmp, + PCI_DEVID(tmp->subordinate->number, + PCI_DEVFN(0, 0)), data); +diff --git a/include/linux/pci.h b/include/linux/pci.h +index 3ea77b9c5901..cdf67f5aa239 100644 +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -248,6 +248,11 @@ enum pci_dev_flags { + PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), + /* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */ + PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13), ++ /* ++ * PCIe to PCI bridge does not create RID aliases because the bridge is ++ * integrated with the downstream devices and doesn't use real PCI. ++ */ ++ PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = (__force pci_dev_flags_t) (1 << 14), + }; + + enum pci_irq_reroute_variant { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0171-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch b/SPECS/linux-lts-kmhv2/0171-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch deleted file mode 100644 index 7144558c46..0000000000 --- a/SPECS/linux-lts-kmhv2/0171-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch +++ /dev/null @@ -1,149 +0,0 @@ -From 76caa8b77c6909d2488024da63eb6de0ae401844 Mon Sep 17 00:00:00 2001 -From: Hang Cao -Date: Wed, 12 Nov 2025 13:53:45 +0800 -Subject: [PATCH 171/467] UPSTREAM: usb: dwc3: eic7700: Add EIC7700 USB driver - -The EIC7700 instantiates two USB 3.0 DWC3 IPs, each of which is backward -compatible with USB interfaces. It supports Super-speed (5Gb/s), DRD mode, -and compatible with xHCI 1.1, etc. Each of instances supports 16 endpoints -in device's mode and max 64 devices in host's mode. - -This module needs to interact with the NOC via the AXI master bus, thus -requiring some HSP configuration operations to achieve this. Ops include -bus filter, pm signal or status to usb bus and so on. - -Acked-by: Thinh Nguyen -Signed-off-by: Senchuan Zhang -Signed-off-by: Hang Cao -Link: https://patch.msgid.link/20251112055346.1655-1-caohang@eswincomputing.com -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit e05d28b759c28660c28a36bf0add178edcc3466e) -Signed-off-by: Han Gao ---- - drivers/usb/dwc3/dwc3-generic-plat.c | 71 +++++++++++++++++++++++++--- - 1 file changed, 64 insertions(+), 7 deletions(-) - -diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c -index e869c7de7bc8..e846844e0023 100644 ---- a/drivers/usb/dwc3/dwc3-generic-plat.c -+++ b/drivers/usb/dwc3/dwc3-generic-plat.c -@@ -10,8 +10,16 @@ - #include - #include - #include -+#include -+#include - #include "glue.h" - -+#define EIC7700_HSP_BUS_FILTER_EN BIT(0) -+#define EIC7700_HSP_BUS_CLKEN_GM BIT(9) -+#define EIC7700_HSP_BUS_CLKEN_GS BIT(16) -+#define EIC7700_HSP_AXI_LP_XM_CSYSREQ BIT(0) -+#define EIC7700_HSP_AXI_LP_XS_CSYSREQ BIT(16) -+ - struct dwc3_generic { - struct device *dev; - struct dwc3 dwc; -@@ -20,6 +28,11 @@ struct dwc3_generic { - struct reset_control *resets; - }; - -+struct dwc3_generic_config { -+ int (*init)(struct dwc3_generic *dwc3g); -+ struct dwc3_properties properties; -+}; -+ - #define to_dwc3_generic(d) container_of((d), struct dwc3_generic, dwc) - - static void dwc3_generic_reset_control_assert(void *data) -@@ -27,9 +40,38 @@ static void dwc3_generic_reset_control_assert(void *data) - reset_control_assert(data); - } - -+static int dwc3_eic7700_init(struct dwc3_generic *dwc3g) -+{ -+ struct device *dev = dwc3g->dev; -+ struct regmap *regmap; -+ u32 hsp_usb_axi_lp; -+ u32 hsp_usb_bus; -+ u32 args[2]; -+ u32 val; -+ -+ regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, -+ "eswin,hsp-sp-csr", -+ ARRAY_SIZE(args), args); -+ if (IS_ERR(regmap)) { -+ dev_err(dev, "No hsp-sp-csr phandle specified\n"); -+ return PTR_ERR(regmap); -+ } -+ -+ hsp_usb_bus = args[0]; -+ hsp_usb_axi_lp = args[1]; -+ -+ regmap_read(regmap, hsp_usb_bus, &val); -+ regmap_write(regmap, hsp_usb_bus, val | EIC7700_HSP_BUS_FILTER_EN | -+ EIC7700_HSP_BUS_CLKEN_GM | EIC7700_HSP_BUS_CLKEN_GS); -+ -+ regmap_write(regmap, hsp_usb_axi_lp, EIC7700_HSP_AXI_LP_XM_CSYSREQ | -+ EIC7700_HSP_AXI_LP_XS_CSYSREQ); -+ return 0; -+} -+ - static int dwc3_generic_probe(struct platform_device *pdev) - { -- const struct dwc3_properties *properties; -+ const struct dwc3_generic_config *plat_config; - struct dwc3_probe_data probe_data = {}; - struct device *dev = &pdev->dev; - struct dwc3_generic *dwc3g; -@@ -77,12 +119,21 @@ static int dwc3_generic_probe(struct platform_device *pdev) - probe_data.res = res; - probe_data.ignore_clocks_and_resets = true; - -- properties = of_device_get_match_data(dev); -- if (properties) -- probe_data.properties = *properties; -- else -+ plat_config = of_device_get_match_data(dev); -+ if (!plat_config) { - probe_data.properties = DWC3_DEFAULT_PROPERTIES; -+ goto core_probe; -+ } - -+ probe_data.properties = plat_config->properties; -+ if (plat_config->init) { -+ ret = plat_config->init(dwc3g); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "failed to init platform\n"); -+ } -+ -+core_probe: - ret = dwc3_core_probe(&probe_data); - if (ret) - return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); -@@ -150,13 +201,19 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { - dwc3_generic_runtime_idle) - }; - --static const struct dwc3_properties fsl_ls1028_dwc3 = { -- .gsbuscfg0_reqinfo = 0x2222, -+static const struct dwc3_generic_config fsl_ls1028_dwc3 = { -+ .properties.gsbuscfg0_reqinfo = 0x2222, -+}; -+ -+static const struct dwc3_generic_config eic7700_dwc3 = { -+ .init = dwc3_eic7700_init, -+ .properties = DWC3_DEFAULT_PROPERTIES, - }; - - static const struct of_device_id dwc3_generic_of_match[] = { - { .compatible = "spacemit,k1-dwc3", }, - { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, -+ { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0172-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch b/SPECS/linux-lts-kmhv2/0172-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch deleted file mode 100644 index 324034713f..0000000000 --- a/SPECS/linux-lts-kmhv2/0172-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 7ce945a45771d022307a72be01e01ba8f621f6ae Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 16 Feb 2026 23:26:53 +0800 -Subject: [PATCH 172/467] UPSTREAM: phy: k1-usb: add disconnect function - support - -A disconnect status BIT of USB2 PHY need to be cleared, otherwise -it will fail to work properly during next connection when devices -connect to roothub directly. - -Fixes: fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller") -Signed-off-by: Yixun Lan -Reviewed-by: Vladimir Oltean -Link: https://patch.msgid.link/20260216152653.25244-1-dlan@kernel.org -Signed-off-by: Vinod Koul -(cherry picked from commit f0cf0a882a02dcf28547f32264f6fd37e9a7b147) -Signed-off-by: Han Gao ---- - drivers/phy/spacemit/phy-k1-usb2.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c -index 342061380012..9215d0b223b2 100644 ---- a/drivers/phy/spacemit/phy-k1-usb2.c -+++ b/drivers/phy/spacemit/phy-k1-usb2.c -@@ -48,6 +48,9 @@ - #define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */ - #define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */ - -+#define PHY_K1_HS_HOST_DISC 0x40 -+#define PHY_K1_HS_HOST_DISC_CLR BIT(0) -+ - #define PHY_PLL_DIV_CFG 0x98 - #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) - #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) -@@ -142,9 +145,20 @@ static int spacemit_usb2phy_exit(struct phy *phy) - return 0; - } - -+static int spacemit_usb2phy_disconnect(struct phy *phy, int port) -+{ -+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); -+ -+ regmap_update_bits(sphy->regmap_base, PHY_K1_HS_HOST_DISC, -+ PHY_K1_HS_HOST_DISC_CLR, PHY_K1_HS_HOST_DISC_CLR); -+ -+ return 0; -+} -+ - static const struct phy_ops spacemit_usb2phy_ops = { - .init = spacemit_usb2phy_init, - .exit = spacemit_usb2phy_exit, -+ .disconnect = spacemit_usb2phy_disconnect, - .owner = THIS_MODULE, - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch b/SPECS/linux-lts-kmhv2/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch new file mode 100644 index 0000000000..b717a1f71f --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch @@ -0,0 +1,72 @@ +From 9b54a8b4866b22ba764ced5eadb4df836758c46b Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Mon, 23 Mar 2026 17:43:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: patch: Avoid early phys_to_page() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Similarly to commit 8d09e2d569f6 ("arm64: patching: avoid early +page_to_phys()"), avoid using phys_to_page() for the kernel address case +in patch_map(). + +Since this is called from apply_boot_alternatives() in setup_arch(), and +commit 4267739cabb8 ("arch, mm: consolidate initialization of SPARSE +memory model") has moved sparse_init() to after setup_arch(), +phys_to_page() is not available there yet, and it panics on boot with +SPARSEMEM on RV32, which does not use SPARSEMEM_VMEMMAP. + +Reported-by: Thomas Weißschuh +Closes: https://lore.kernel.org/r/20260223144108-dcace0b9-02e8-4b67-a7ce-f263bed36f26@linutronix.de/ +Fixes: 4267739cabb8 ("arch, mm: consolidate initialization of SPARSE memory model") +Suggested-by: Mike Rapoport +Signed-off-by: Vivian Wang +Acked-by: Mike Rapoport (Microsoft) +Tested-by: Thomas Weißschuh +Link: https://patch.msgid.link/20260310-riscv-sparsemem-alternatives-fix-v1-1-659d5dd257e2@iscas.ac.cn +[pjw@kernel.org: fix the subject line to align with the patch description] +Signed-off-by: Paul Walmsley +(cherry picked from commit 6b60a128c2f43180664a614830f3c529497e0394) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/patch.c | 21 +++++++++++---------- + 1 file changed, 11 insertions(+), 10 deletions(-) + +diff --git a/arch/riscv/kernel/patch.c b/arch/riscv/kernel/patch.c +index db13c9ddf9e3..16b243376f36 100644 +--- a/arch/riscv/kernel/patch.c ++++ b/arch/riscv/kernel/patch.c +@@ -42,19 +42,20 @@ static inline bool is_kernel_exittext(uintptr_t addr) + static __always_inline void *patch_map(void *addr, const unsigned int fixmap) + { + uintptr_t uintaddr = (uintptr_t) addr; +- struct page *page; ++ phys_addr_t phys; + +- if (core_kernel_text(uintaddr) || is_kernel_exittext(uintaddr)) +- page = phys_to_page(__pa_symbol(addr)); +- else if (IS_ENABLED(CONFIG_STRICT_MODULE_RWX)) +- page = vmalloc_to_page(addr); +- else +- return addr; ++ if (core_kernel_text(uintaddr) || is_kernel_exittext(uintaddr)) { ++ phys = __pa_symbol(addr); ++ } else if (IS_ENABLED(CONFIG_STRICT_MODULE_RWX)) { ++ struct page *page = vmalloc_to_page(addr); + +- BUG_ON(!page); ++ BUG_ON(!page); ++ phys = page_to_phys(page) + offset_in_page(addr); ++ } else { ++ return addr; ++ } + +- return (void *)set_fixmap_offset(fixmap, page_to_phys(page) + +- offset_in_page(addr)); ++ return (void *)set_fixmap_offset(fixmap, phys); + } + + static void patch_unmap(int fixmap) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0173-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch b/SPECS/linux-lts-kmhv2/0173-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch deleted file mode 100644 index 33ff2c2664..0000000000 --- a/SPECS/linux-lts-kmhv2/0173-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 6b3c31276fbb62225261d4063f231152756c3c24 Mon Sep 17 00:00:00 2001 -From: Nirmoy Das -Date: Wed, 17 Dec 2025 07:45:28 -0800 -Subject: [PATCH 173/467] UPSTREAM: PCI: Add ASPEED vendor ID to pci_ids.h - -Add PCI_VENDOR_ID_ASPEED to the shared pci_ids.h header and remove the -duplicate local definition from ehci-pci.c. - -This prepares for adding a PCI quirk for ASPEED devices. - -Signed-off-by: Nirmoy Das -Signed-off-by: Bjorn Helgaas -Reviewed-by: Jason Gunthorpe -Link: https://patch.msgid.link/20251217154529.377586-1-nirmoyd@nvidia.com -(cherry picked from commit eeb95c07d5fcaafb1829d5307ce4290cf1dc3190) -Signed-off-by: Han Gao ---- - drivers/usb/host/ehci-pci.c | 1 - - include/linux/pci_ids.h | 2 ++ - 2 files changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c -index 889dc4426271..bd3a63555594 100644 ---- a/drivers/usb/host/ehci-pci.c -+++ b/drivers/usb/host/ehci-pci.c -@@ -21,7 +21,6 @@ static const char hcd_name[] = "ehci-pci"; - /* defined here to avoid adding to pci_ids.h for single instance use */ - #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 - --#define PCI_VENDOR_ID_ASPEED 0x1a03 - #define PCI_DEVICE_ID_ASPEED_EHCI 0x2603 - - /*-------------------------------------------------------------------------*/ -diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h -index 03b7c0380f71..2b6692a5005f 100644 ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -2583,6 +2583,8 @@ - #define PCI_DEVICE_ID_NETRONOME_NFP3800_VF 0x3803 - #define PCI_DEVICE_ID_NETRONOME_NFP6000_VF 0x6003 - -+#define PCI_VENDOR_ID_ASPEED 0x1a03 -+ - #define PCI_VENDOR_ID_QMI 0x1a32 - - #define PCI_VENDOR_ID_AZWAVE 0x1a3b --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch b/SPECS/linux-lts-kmhv2/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch new file mode 100644 index 0000000000..7274ae6b1a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch @@ -0,0 +1,51 @@ +From 6727a0a8b7add2ff9543cd2e8e0f4e29a5a9b89a Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam +Date: Tue, 20 Jan 2026 23:17:44 +0530 +Subject: [RUYI PATCH] UPSTREAM: PCI: dwc: Fail dw_pcie_host_init() if + dw_pcie_wait_for_link() returns -ETIMEDOUT + +The dw_pcie_wait_for_link() API now distinguishes link failures more +precisely: + +-ENODEV: Device not found on the bus. +-EIO: Device found but inactive. +-ETIMEDOUT: Link failed to come up. + +Out of these three errors, only -ETIMEDOUT represents a definitive link +failure since it signals that something is wrong with the link. For the +other two errors, there is a possibility that the link might come up later. +So fail dw_pcie_host_init() if -ETIMEDOUT is returned and skip the failure +otherwise. + +Signed-off-by: Manivannan Sadhasivam +Reviewed-by: Niklas Cassel +Link: https://patch.msgid.link/20260120-pci-dwc-suspend-rework-v4-5-2f32d5082549@oss.qualcomm.com +(cherry picked from commit 86cbb7a81068434fdc1d5afb96d91ab971fb279e) +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c +index 993858fd0529..dbd4b66934df 100644 +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -664,8 +664,13 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) + goto err_remove_edma; + } + +- /* Ignore errors, the link may come up later */ +- dw_pcie_wait_for_link(pci); ++ /* ++ * Only fail on timeout error. Other errors indicate the device may ++ * become available later, so continue without failing. ++ */ ++ ret = dw_pcie_wait_for_link(pci); ++ if (ret == -ETIMEDOUT) ++ goto err_stop_link; + + ret = pci_host_probe(bridge); + if (ret) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0174-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch b/SPECS/linux-lts-kmhv2/0174-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch deleted file mode 100644 index 5c4614e51e..0000000000 --- a/SPECS/linux-lts-kmhv2/0174-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 12f86c495ee4dc708c6b0b172a7518faf4303656 Mon Sep 17 00:00:00 2001 -From: Nirmoy Das -Date: Wed, 17 Dec 2025 07:45:29 -0800 -Subject: [PATCH 174/467] UPSTREAM: PCI: Add PCI_BRIDGE_NO_ALIAS quirk for - ASPEED AST1150 - -ASPEED BMC controllers have VGA and USB functions behind a PCIe-to-PCI -bridge that causes them to share the same StreamID: - - [e0]---00.0-[e1-e2]----00.0-[e2]--+-00.0 ASPEED Graphics Family - \-02.0 ASPEED USB Controller - -Both devices get StreamID 0x5e200 due to bridge aliasing, causing the USB -controller to be rejected with 'Aliasing StreamID unsupported'. - -Per ASPEED, the AST1150 doesn't use a real PCI bus and always forwards -the original Requester ID from downstream devices rather than replacing -it with any alias. - -Add a new PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS flag and apply it to the -AST1150. - -Suggested-by: Jason Gunthorpe -Signed-off-by: Nirmoy Das -Signed-off-by: Bjorn Helgaas -Reviewed-by: Robin Murphy -Reviewed-by: Jason Gunthorpe -Link: https://patch.msgid.link/20251217154529.377586-2-nirmoyd@nvidia.com -(cherry picked from commit 550a190494a0d3e933dd6f3b2e9c430f94a30a8c) -Signed-off-by: Han Gao ---- - drivers/pci/quirks.c | 10 ++++++++++ - drivers/pci/search.c | 2 ++ - include/linux/pci.h | 5 +++++ - 3 files changed, 17 insertions(+) - -diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index d32a47e81fcf..481e4186a5c1 100644 ---- a/drivers/pci/quirks.c -+++ b/drivers/pci/quirks.c -@@ -4481,6 +4481,16 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, - DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, - quirk_bridge_cavm_thrx2_pcie_root); - -+/* -+ * AST1150 doesn't use a real PCI bus and always forwards the requester ID -+ * from downstream devices. -+ */ -+static void quirk_aspeed_pci_bridge_no_alias(struct pci_dev *pdev) -+{ -+ pdev->dev_flags |= PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS; -+} -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASPEED, 0x1150, quirk_aspeed_pci_bridge_no_alias); -+ - /* - * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) - * class code. Fix it. -diff --git a/drivers/pci/search.c b/drivers/pci/search.c -index 53840634fbfc..b3c9e3d82201 100644 ---- a/drivers/pci/search.c -+++ b/drivers/pci/search.c -@@ -86,6 +86,8 @@ int pci_for_each_dma_alias(struct pci_dev *pdev, - case PCI_EXP_TYPE_DOWNSTREAM: - continue; - case PCI_EXP_TYPE_PCI_BRIDGE: -+ if (tmp->dev_flags & PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS) -+ continue; - ret = fn(tmp, - PCI_DEVID(tmp->subordinate->number, - PCI_DEVFN(0, 0)), data); -diff --git a/include/linux/pci.h b/include/linux/pci.h -index 3ea77b9c5901..cdf67f5aa239 100644 ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -248,6 +248,11 @@ enum pci_dev_flags { - PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), - /* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */ - PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13), -+ /* -+ * PCIe to PCI bridge does not create RID aliases because the bridge is -+ * integrated with the downstream devices and doesn't use real PCI. -+ */ -+ PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = (__force pci_dev_flags_t) (1 << 14), - }; - - enum pci_irq_reroute_variant { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch b/SPECS/linux-lts-kmhv2/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch new file mode 100644 index 0000000000..1cc4f9a6b9 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch @@ -0,0 +1,200 @@ +From a21ca9741cdf655d806097dd0285fc759b7550dd Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 20 Mar 2026 11:06:17 +0000 +Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: k3: Decouple composite reset + lines + +Instead of grouping several different reset lines into one composite +reset, decouple them to individual ones which make it more aligned +with underlying hardware. And for DWC USB driver, it will match well +with the number of the reset property in the DT bindings. + +The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, +PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. +Also three reset lines each for UCIE and RCPU block. + +As an agreement with maintainer, the reset IDs has been rearranged as +contiguous number but keep most part unchanged to avoid break patches +which already sent to mailing list. The changes of DT binding header file +and reset driver are merged together as one single commit to avoid +git-bisect breakage. + +Fixes: 938ce3b16582 ("reset: spacemit: Add SpacemiT K3 reset driver") +Fixes: 216e0a5e98e5 ("dt-bindings: soc: spacemit: Add K3 reset support and IDs") +Signed-off-by: Yixun Lan +Reviewed-by: Philipp Zabel +Acked-by: Conor Dooley +Signed-off-by: Philipp Zabel +(cherry picked from commit a0e0c2f8c5f32b675f58e25a9338283cedb5ad2b) +Signed-off-by: Han Gao +--- + drivers/reset/spacemit/reset-spacemit-k3.c | 60 +++++++++++-------- + .../dt-bindings/reset/spacemit,k3-resets.h | 48 +++++++++++---- + 2 files changed, 72 insertions(+), 36 deletions(-) + +diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c +index e9e32e4c1ba5..9841f5e057b2 100644 +--- a/drivers/reset/spacemit/reset-spacemit-k3.c ++++ b/drivers/reset/spacemit/reset-spacemit-k3.c +@@ -112,16 +112,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = { + [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), +- [RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, +- BIT(1)|BIT(2)|BIT(3)), +- [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, +- BIT(5)|BIT(6)|BIT(7)), +- [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, +- BIT(9)|BIT(10)|BIT(11)), +- [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, +- BIT(13)|BIT(14)|BIT(15)), +- [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, +- BIT(17)|BIT(18)|BIT(19)), ++ [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)), ++ [RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)), ++ [RESET_APMU_USB3_A_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(6)), ++ [RESET_APMU_USB3_A_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(7)), ++ [RESET_APMU_USB3_B_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)), ++ [RESET_APMU_USB3_B_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)), ++ [RESET_APMU_USB3_B_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)), ++ [RESET_APMU_USB3_C_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(13)), ++ [RESET_APMU_USB3_C_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(14)), ++ [RESET_APMU_USB3_C_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(15)), ++ [RESET_APMU_USB3_D_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(17)), ++ [RESET_APMU_USB3_D_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(18)), ++ [RESET_APMU_USB3_D_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(19)), + [RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), +@@ -151,10 +156,12 @@ static const struct ccu_reset_data k3_apmu_resets[] = { + [RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), + [RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), + [RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), +- [RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL, +- BIT(1) | BIT(2) | BIT(3), 0), +- [RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, +- BIT(3) | BIT(2) | BIT(0)), ++ [RESET_APMU_UCIE_IP] = RESET_DATA(APMU_UCIE_CTRL, BIT(1), 0), ++ [RESET_APMU_UCIE_HOT] = RESET_DATA(APMU_UCIE_CTRL, BIT(2), 0), ++ [RESET_APMU_UCIE_MON] = RESET_DATA(APMU_UCIE_CTRL, BIT(3), 0), ++ [RESET_APMU_RCPU_AUDIO_SYS] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_RCPU_MCU_CORE] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_APMU_RCPU_AUDIO_APMU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(3)), + [RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)), + [RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)), + [RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)), +@@ -164,16 +171,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = { + [RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), + [RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), +- [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, +- BIT(5) | BIT(4) | BIT(3)), +- [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, +- BIT(5) | BIT(4) | BIT(3)), +- [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, +- BIT(5) | BIT(4) | BIT(3)), +- [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, +- BIT(5) | BIT(4) | BIT(3)), +- [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, +- BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_A_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(3)), ++ [RESET_APMU_PCIE_A_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(4)), ++ [RESET_APMU_PCIE_A_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(5)), ++ [RESET_APMU_PCIE_B_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(3)), ++ [RESET_APMU_PCIE_B_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(4)), ++ [RESET_APMU_PCIE_B_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(5)), ++ [RESET_APMU_PCIE_C_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(3)), ++ [RESET_APMU_PCIE_C_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(4)), ++ [RESET_APMU_PCIE_C_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(5)), ++ [RESET_APMU_PCIE_D_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(3)), ++ [RESET_APMU_PCIE_D_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(4)), ++ [RESET_APMU_PCIE_D_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(5)), ++ [RESET_APMU_PCIE_E_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(3)), ++ [RESET_APMU_PCIE_E_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(4)), ++ [RESET_APMU_PCIE_E_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(5)), + [RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)), +diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h +index 79ac1c22b7b5..dc1ef009ba79 100644 +--- a/include/dt-bindings/reset/spacemit,k3-resets.h ++++ b/include/dt-bindings/reset/spacemit,k3-resets.h +@@ -97,11 +97,11 @@ + #define RESET_APMU_SDH0 13 + #define RESET_APMU_SDH1 14 + #define RESET_APMU_SDH2 15 +-#define RESET_APMU_USB2 16 +-#define RESET_APMU_USB3_PORTA 17 +-#define RESET_APMU_USB3_PORTB 18 +-#define RESET_APMU_USB3_PORTC 19 +-#define RESET_APMU_USB3_PORTD 20 ++#define RESET_APMU_USB2_AHB 16 ++#define RESET_APMU_USB2_VCC 17 ++#define RESET_APMU_USB2_PHY 18 ++#define RESET_APMU_USB3_A_AHB 19 ++#define RESET_APMU_USB3_A_VCC 20 + #define RESET_APMU_QSPI 21 + #define RESET_APMU_QSPI_BUS 22 + #define RESET_APMU_DMA 23 +@@ -132,8 +132,8 @@ + #define RESET_APMU_CPU7_SW 48 + #define RESET_APMU_C1_MPSUB_SW 49 + #define RESET_APMU_MPSUB_DBG 50 +-#define RESET_APMU_UCIE 51 +-#define RESET_APMU_RCPU 52 ++#define RESET_APMU_USB3_A_PHY 51 /* USB3 A */ ++#define RESET_APMU_USB3_B_AHB 52 + #define RESET_APMU_DSI4LN2_ESCCLK 53 + #define RESET_APMU_DSI4LN2_LCD_SW 54 + #define RESET_APMU_DSI4LN2_LCD_MCLK 55 +@@ -143,16 +143,40 @@ + #define RESET_APMU_UFS_ACLK 59 + #define RESET_APMU_EDP0 60 + #define RESET_APMU_EDP1 61 +-#define RESET_APMU_PCIE_PORTA 62 +-#define RESET_APMU_PCIE_PORTB 63 +-#define RESET_APMU_PCIE_PORTC 64 +-#define RESET_APMU_PCIE_PORTD 65 +-#define RESET_APMU_PCIE_PORTE 66 ++#define RESET_APMU_USB3_B_VCC 62 /* USB3 B */ ++#define RESET_APMU_USB3_B_PHY 63 ++#define RESET_APMU_USB3_C_AHB 64 ++#define RESET_APMU_USB3_C_VCC 65 ++#define RESET_APMU_USB3_C_PHY 66 + #define RESET_APMU_EMAC0 67 + #define RESET_APMU_EMAC1 68 + #define RESET_APMU_EMAC2 69 + #define RESET_APMU_ESPI_MCLK 70 + #define RESET_APMU_ESPI_SCLK 71 ++#define RESET_APMU_USB3_D_AHB 72 /* USB3 D */ ++#define RESET_APMU_USB3_D_VCC 73 ++#define RESET_APMU_USB3_D_PHY 74 ++#define RESET_APMU_UCIE_IP 75 ++#define RESET_APMU_UCIE_HOT 76 ++#define RESET_APMU_UCIE_MON 77 ++#define RESET_APMU_RCPU_AUDIO_SYS 78 ++#define RESET_APMU_RCPU_MCU_CORE 79 ++#define RESET_APMU_RCPU_AUDIO_APMU 80 ++#define RESET_APMU_PCIE_A_DBI 81 ++#define RESET_APMU_PCIE_A_SLAVE 82 ++#define RESET_APMU_PCIE_A_MASTER 83 ++#define RESET_APMU_PCIE_B_DBI 84 ++#define RESET_APMU_PCIE_B_SLAVE 85 ++#define RESET_APMU_PCIE_B_MASTER 86 ++#define RESET_APMU_PCIE_C_DBI 87 ++#define RESET_APMU_PCIE_C_SLAVE 88 ++#define RESET_APMU_PCIE_C_MASTER 89 ++#define RESET_APMU_PCIE_D_DBI 90 ++#define RESET_APMU_PCIE_D_SLAVE 91 ++#define RESET_APMU_PCIE_D_MASTER 92 ++#define RESET_APMU_PCIE_E_DBI 93 ++#define RESET_APMU_PCIE_E_SLAVE 94 ++#define RESET_APMU_PCIE_E_MASTER 95 + + /* DCIU resets*/ + #define RESET_DCIU_HDMA 0 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0175-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch b/SPECS/linux-lts-kmhv2/0175-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch deleted file mode 100644 index df952d8560..0000000000 --- a/SPECS/linux-lts-kmhv2/0175-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 8118d162255f24fd2cd5dee126efaea4a5cba952 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Mon, 23 Mar 2026 17:43:47 -0600 -Subject: [PATCH 175/467] UPSTREAM: riscv: patch: Avoid early phys_to_page() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Similarly to commit 8d09e2d569f6 ("arm64: patching: avoid early -page_to_phys()"), avoid using phys_to_page() for the kernel address case -in patch_map(). - -Since this is called from apply_boot_alternatives() in setup_arch(), and -commit 4267739cabb8 ("arch, mm: consolidate initialization of SPARSE -memory model") has moved sparse_init() to after setup_arch(), -phys_to_page() is not available there yet, and it panics on boot with -SPARSEMEM on RV32, which does not use SPARSEMEM_VMEMMAP. - -Reported-by: Thomas Weißschuh -Closes: https://lore.kernel.org/r/20260223144108-dcace0b9-02e8-4b67-a7ce-f263bed36f26@linutronix.de/ -Fixes: 4267739cabb8 ("arch, mm: consolidate initialization of SPARSE memory model") -Suggested-by: Mike Rapoport -Signed-off-by: Vivian Wang -Acked-by: Mike Rapoport (Microsoft) -Tested-by: Thomas Weißschuh -Link: https://patch.msgid.link/20260310-riscv-sparsemem-alternatives-fix-v1-1-659d5dd257e2@iscas.ac.cn -[pjw@kernel.org: fix the subject line to align with the patch description] -Signed-off-by: Paul Walmsley -(cherry picked from commit 6b60a128c2f43180664a614830f3c529497e0394) -Signed-off-by: Han Gao ---- - arch/riscv/kernel/patch.c | 21 +++++++++++---------- - 1 file changed, 11 insertions(+), 10 deletions(-) - -diff --git a/arch/riscv/kernel/patch.c b/arch/riscv/kernel/patch.c -index db13c9ddf9e3..16b243376f36 100644 ---- a/arch/riscv/kernel/patch.c -+++ b/arch/riscv/kernel/patch.c -@@ -42,19 +42,20 @@ static inline bool is_kernel_exittext(uintptr_t addr) - static __always_inline void *patch_map(void *addr, const unsigned int fixmap) - { - uintptr_t uintaddr = (uintptr_t) addr; -- struct page *page; -+ phys_addr_t phys; - -- if (core_kernel_text(uintaddr) || is_kernel_exittext(uintaddr)) -- page = phys_to_page(__pa_symbol(addr)); -- else if (IS_ENABLED(CONFIG_STRICT_MODULE_RWX)) -- page = vmalloc_to_page(addr); -- else -- return addr; -+ if (core_kernel_text(uintaddr) || is_kernel_exittext(uintaddr)) { -+ phys = __pa_symbol(addr); -+ } else if (IS_ENABLED(CONFIG_STRICT_MODULE_RWX)) { -+ struct page *page = vmalloc_to_page(addr); - -- BUG_ON(!page); -+ BUG_ON(!page); -+ phys = page_to_phys(page) + offset_in_page(addr); -+ } else { -+ return addr; -+ } - -- return (void *)set_fixmap_offset(fixmap, page_to_phys(page) + -- offset_in_page(addr)); -+ return (void *)set_fixmap_offset(fixmap, phys); - } - - static void patch_unmap(int fixmap) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch b/SPECS/linux-lts-kmhv2/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch new file mode 100644 index 0000000000..f22e81a3cb --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch @@ -0,0 +1,46 @@ +From 36c2fd3cabf5ec62efb4f91282e7b4afd1034963 Mon Sep 17 00:00:00 2001 +From: Alice Ryhl +Date: Mon, 23 Feb 2026 10:08:25 +0000 +Subject: [RUYI PATCH] UPSTREAM: rust: clk: implement Send and Sync + +These traits are required for drivers to embed the Clk type in their own +data structures because driver data structures are usually required to +be Send. Since the Clk type is thread-safe, implement the relevant +traits. + +Reviewed-by: Daniel Almeida +Reviewed-by: Danilo Krummrich +Acked-by: Viresh Kumar +Reviewed-by: Boqun Feng +Reviewed-by: Gary Guo +Signed-off-by: Alice Ryhl +Acked-by: Brian Masney # Active contributor to clk +Link: https://patch.msgid.link/20260223-clk-send-sync-v5-1-181bf2f35652@google.com +Signed-off-by: Miguel Ojeda +(cherry picked from commit 0c0695a9d8c97f63d71dc890faa6999eef728f57) +Signed-off-by: Han Gao +--- + rust/kernel/clk.rs | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/rust/kernel/clk.rs b/rust/kernel/clk.rs +index 1e6c8c42fb3a..0a290202da69 100644 +--- a/rust/kernel/clk.rs ++++ b/rust/kernel/clk.rs +@@ -129,6 +129,13 @@ mod common_clk { + #[repr(transparent)] + pub struct Clk(*mut bindings::clk); + ++ // SAFETY: It is safe to call `clk_put` on another thread than where `clk_get` was called. ++ unsafe impl Send for Clk {} ++ ++ // SAFETY: It is safe to call any combination of the `&self` methods in parallel, as the ++ // methods are synchronized internally. ++ unsafe impl Sync for Clk {} ++ + impl Clk { + /// Gets [`Clk`] corresponding to a [`Device`] and a connection id. + /// +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0176-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch b/SPECS/linux-lts-kmhv2/0176-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch deleted file mode 100644 index 1bd8a9ebb3..0000000000 --- a/SPECS/linux-lts-kmhv2/0176-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 23cc45c1d179af7b48fdde28d5607b138fb0ca43 Mon Sep 17 00:00:00 2001 -From: Manivannan Sadhasivam -Date: Tue, 20 Jan 2026 23:17:44 +0530 -Subject: [PATCH 176/467] UPSTREAM: PCI: dwc: Fail dw_pcie_host_init() if - dw_pcie_wait_for_link() returns -ETIMEDOUT - -The dw_pcie_wait_for_link() API now distinguishes link failures more -precisely: - --ENODEV: Device not found on the bus. --EIO: Device found but inactive. --ETIMEDOUT: Link failed to come up. - -Out of these three errors, only -ETIMEDOUT represents a definitive link -failure since it signals that something is wrong with the link. For the -other two errors, there is a possibility that the link might come up later. -So fail dw_pcie_host_init() if -ETIMEDOUT is returned and skip the failure -otherwise. - -Signed-off-by: Manivannan Sadhasivam -Reviewed-by: Niklas Cassel -Link: https://patch.msgid.link/20260120-pci-dwc-suspend-rework-v4-5-2f32d5082549@oss.qualcomm.com -(cherry picked from commit 86cbb7a81068434fdc1d5afb96d91ab971fb279e) -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - -diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c -index 993858fd0529..dbd4b66934df 100644 ---- a/drivers/pci/controller/dwc/pcie-designware-host.c -+++ b/drivers/pci/controller/dwc/pcie-designware-host.c -@@ -664,8 +664,13 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) - goto err_remove_edma; - } - -- /* Ignore errors, the link may come up later */ -- dw_pcie_wait_for_link(pci); -+ /* -+ * Only fail on timeout error. Other errors indicate the device may -+ * become available later, so continue without failing. -+ */ -+ ret = dw_pcie_wait_for_link(pci); -+ if (ret == -ETIMEDOUT) -+ goto err_stop_link; - - ret = pci_host_probe(bridge); - if (ret) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch b/SPECS/linux-lts-kmhv2/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch new file mode 100644 index 0000000000..de7554e891 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch @@ -0,0 +1,51 @@ +From 83865522aaf93ce13b4bf32daff035cc0ffb1875 Mon Sep 17 00:00:00 2001 +From: Alice Ryhl +Date: Mon, 23 Feb 2026 10:08:26 +0000 +Subject: [RUYI PATCH] UPSTREAM: tyr: remove impl Send/Sync for TyrData + +Now that clk implements Send and Sync, we no longer need to manually +implement these traits for TyrData. Thus remove the implementations. + +The comment also mentions the regulator. However, the regulator had the +traits added in commit 9a200cbdb543 ("rust: regulator: implement Send +and Sync for Regulator"), which is already in mainline. + +Reviewed-by: Danilo Krummrich +Reviewed-by: Boqun Feng +Reviewed-by: Gary Guo +Reviewed-by: Daniel Almeida +Signed-off-by: Alice Ryhl +Link: https://patch.msgid.link/20260223-clk-send-sync-v5-2-181bf2f35652@google.com +Signed-off-by: Miguel Ojeda +(cherry picked from commit ef90b103e8f767ffc31b1ddfef012358ea873d85) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/tyr/driver.rs | 12 ------------ + 1 file changed, 12 deletions(-) + +diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver.rs +index 0052ebe95719..0b741450724e 100644 +--- a/drivers/gpu/drm/tyr/driver.rs ++++ b/drivers/gpu/drm/tyr/driver.rs +@@ -53,18 +53,6 @@ pub(crate) struct TyrData { + pub(crate) gpu_info: GpuInfo, + } + +-// Both `Clk` and `Regulator` do not implement `Send` or `Sync`, but they +-// should. There are patches on the mailing list to address this, but they have +-// not landed yet. +-// +-// For now, add this workaround so that this patch compiles with the promise +-// that it will be removed in a future patch. +-// +-// SAFETY: This will be removed in a future patch. +-unsafe impl Send for TyrData {} +-// SAFETY: This will be removed in a future patch. +-unsafe impl Sync for TyrData {} +- + fn issue_soft_reset(dev: &Device, iomem: &Devres) -> Result { + regs::GPU_CMD.write(dev, iomem, regs::GPU_CMD_SOFT_RESET)?; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch b/SPECS/linux-lts-kmhv2/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch new file mode 100644 index 0000000000..96d1a40105 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch @@ -0,0 +1,72 @@ +From 196de3c6b4e75a74ef0157f0c59ca867711beb1f Mon Sep 17 00:00:00 2001 +From: Miguel Ojeda +Date: Wed, 21 Jan 2026 19:37:19 +0100 +Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: fix `CLIPPY=1` warning +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The Rust kernel code should be kept `CLIPPY=1`-clean [1]. + +Clippy reports: + + error: this pattern reimplements `Option::unwrap_or` + --> drivers/pwm/pwm_th1520.rs:64:5 + | + 64 | / (match ns.checked_mul(rate_hz) { + 65 | | Some(product) => product, + 66 | | None => u64::MAX, + 67 | | }) / NSEC_PER_SEC_U64 + | |______^ help: replace with: `ns.checked_mul(rate_hz).unwrap_or(u64::MAX)` + | + = help: for further information visit https://rust-lang.github.io/rust-clippy/rust-1.92.0/index.html#manual_unwrap_or + = note: `-D clippy::manual-unwrap-or` implied by `-D warnings` + = help: to override `-D warnings` add `#[allow(clippy::manual_unwrap_or)]` + +Applying the suggestion then triggers: + + error: manual saturating arithmetic + --> drivers/pwm/pwm_th1520.rs:64:5 + | + 64 | ns.checked_mul(rate_hz).unwrap_or(u64::MAX) / NSEC_PER_SEC_U64 + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `saturating_mul`: `ns.saturating_mul(rate_hz)` + | + = help: for further information visit https://rust-lang.github.io/rust-clippy/rust-1.92.0/index.html#manual_saturating_arithmetic + = note: `-D clippy::manual-saturating-arithmetic` implied by `-D warnings` + = help: to override `-D warnings` add `#[allow(clippy::manual_saturating_arithmetic)]` + +Thus fix it by using saturating arithmetic, which simplifies the code +as well. + +Link: https://rust-for-linux.com/contributing#submit-checklist-addendum [1] +Fixes: e03724aac758 ("pwm: Add Rust driver for T-HEAD TH1520 SoC") +Signed-off-by: Miguel Ojeda +Reviewed-by: Danilo Krummrich +Reviewed-by: Michal Wilczynski +Link: https://patch.msgid.link/20260121183719.71659-1-ojeda@kernel.org +Signed-off-by: Uwe Kleine-König +(cherry picked from commit aa8f35172ab66c57d4355a8c4e28d05b44c938e3) +Signed-off-by: Han Gao +--- + drivers/pwm/pwm_th1520.rs | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs +index 955c359b07fb..571db5928356 100644 +--- a/drivers/pwm/pwm_th1520.rs ++++ b/drivers/pwm/pwm_th1520.rs +@@ -62,10 +62,7 @@ const fn th1520_pwm_fp(n: u32) -> usize { + fn ns_to_cycles(ns: u64, rate_hz: u64) -> u64 { + const NSEC_PER_SEC_U64: u64 = time::NSEC_PER_SEC as u64; + +- (match ns.checked_mul(rate_hz) { +- Some(product) => product, +- None => u64::MAX, +- }) / NSEC_PER_SEC_U64 ++ ns.saturating_mul(rate_hz) / NSEC_PER_SEC_U64 + } + + fn cycles_to_ns(cycles: u64, rate_hz: u64) -> u64 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0177-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch b/SPECS/linux-lts-kmhv2/0177-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch deleted file mode 100644 index 659010a91f..0000000000 --- a/SPECS/linux-lts-kmhv2/0177-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch +++ /dev/null @@ -1,200 +0,0 @@ -From 760f735fd91860a199a5219ec9e84def5029f0c6 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 20 Mar 2026 11:06:17 +0000 -Subject: [PATCH 177/467] UPSTREAM: reset: spacemit: k3: Decouple composite - reset lines - -Instead of grouping several different reset lines into one composite -reset, decouple them to individual ones which make it more aligned -with underlying hardware. And for DWC USB driver, it will match well -with the number of the reset property in the DT bindings. - -The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, -PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. -Also three reset lines each for UCIE and RCPU block. - -As an agreement with maintainer, the reset IDs has been rearranged as -contiguous number but keep most part unchanged to avoid break patches -which already sent to mailing list. The changes of DT binding header file -and reset driver are merged together as one single commit to avoid -git-bisect breakage. - -Fixes: 938ce3b16582 ("reset: spacemit: Add SpacemiT K3 reset driver") -Fixes: 216e0a5e98e5 ("dt-bindings: soc: spacemit: Add K3 reset support and IDs") -Signed-off-by: Yixun Lan -Reviewed-by: Philipp Zabel -Acked-by: Conor Dooley -Signed-off-by: Philipp Zabel -(cherry picked from commit a0e0c2f8c5f32b675f58e25a9338283cedb5ad2b) -Signed-off-by: Han Gao ---- - drivers/reset/spacemit/reset-spacemit-k3.c | 60 +++++++++++-------- - .../dt-bindings/reset/spacemit,k3-resets.h | 48 +++++++++++---- - 2 files changed, 72 insertions(+), 36 deletions(-) - -diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c -index e9e32e4c1ba5..9841f5e057b2 100644 ---- a/drivers/reset/spacemit/reset-spacemit-k3.c -+++ b/drivers/reset/spacemit/reset-spacemit-k3.c -@@ -112,16 +112,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = { - [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), -- [RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -- BIT(1)|BIT(2)|BIT(3)), -- [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -- BIT(5)|BIT(6)|BIT(7)), -- [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -- BIT(9)|BIT(10)|BIT(11)), -- [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -- BIT(13)|BIT(14)|BIT(15)), -- [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -- BIT(17)|BIT(18)|BIT(19)), -+ [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)), -+ [RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)), -+ [RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)), -+ [RESET_APMU_USB3_A_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(6)), -+ [RESET_APMU_USB3_A_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(7)), -+ [RESET_APMU_USB3_B_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)), -+ [RESET_APMU_USB3_B_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)), -+ [RESET_APMU_USB3_B_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)), -+ [RESET_APMU_USB3_C_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(13)), -+ [RESET_APMU_USB3_C_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(14)), -+ [RESET_APMU_USB3_C_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(15)), -+ [RESET_APMU_USB3_D_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(17)), -+ [RESET_APMU_USB3_D_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(18)), -+ [RESET_APMU_USB3_D_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(19)), - [RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), - [RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), -@@ -151,10 +156,12 @@ static const struct ccu_reset_data k3_apmu_resets[] = { - [RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), - [RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), - [RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), -- [RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL, -- BIT(1) | BIT(2) | BIT(3), 0), -- [RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, -- BIT(3) | BIT(2) | BIT(0)), -+ [RESET_APMU_UCIE_IP] = RESET_DATA(APMU_UCIE_CTRL, BIT(1), 0), -+ [RESET_APMU_UCIE_HOT] = RESET_DATA(APMU_UCIE_CTRL, BIT(2), 0), -+ [RESET_APMU_UCIE_MON] = RESET_DATA(APMU_UCIE_CTRL, BIT(3), 0), -+ [RESET_APMU_RCPU_AUDIO_SYS] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_RCPU_MCU_CORE] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(2)), -+ [RESET_APMU_RCPU_AUDIO_APMU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(3)), - [RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)), - [RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)), - [RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)), -@@ -164,16 +171,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = { - [RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), - [RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), - [RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), -- [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, -- BIT(5) | BIT(4) | BIT(3)), -- [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, -- BIT(5) | BIT(4) | BIT(3)), -- [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, -- BIT(5) | BIT(4) | BIT(3)), -- [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, -- BIT(5) | BIT(4) | BIT(3)), -- [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, -- BIT(5) | BIT(4) | BIT(3)), -+ [RESET_APMU_PCIE_A_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(3)), -+ [RESET_APMU_PCIE_A_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(4)), -+ [RESET_APMU_PCIE_A_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(5)), -+ [RESET_APMU_PCIE_B_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(3)), -+ [RESET_APMU_PCIE_B_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(4)), -+ [RESET_APMU_PCIE_B_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(5)), -+ [RESET_APMU_PCIE_C_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(3)), -+ [RESET_APMU_PCIE_C_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(4)), -+ [RESET_APMU_PCIE_C_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(5)), -+ [RESET_APMU_PCIE_D_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(3)), -+ [RESET_APMU_PCIE_D_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(4)), -+ [RESET_APMU_PCIE_D_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(5)), -+ [RESET_APMU_PCIE_E_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(3)), -+ [RESET_APMU_PCIE_E_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(4)), -+ [RESET_APMU_PCIE_E_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(5)), - [RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)), -diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h -index 79ac1c22b7b5..dc1ef009ba79 100644 ---- a/include/dt-bindings/reset/spacemit,k3-resets.h -+++ b/include/dt-bindings/reset/spacemit,k3-resets.h -@@ -97,11 +97,11 @@ - #define RESET_APMU_SDH0 13 - #define RESET_APMU_SDH1 14 - #define RESET_APMU_SDH2 15 --#define RESET_APMU_USB2 16 --#define RESET_APMU_USB3_PORTA 17 --#define RESET_APMU_USB3_PORTB 18 --#define RESET_APMU_USB3_PORTC 19 --#define RESET_APMU_USB3_PORTD 20 -+#define RESET_APMU_USB2_AHB 16 -+#define RESET_APMU_USB2_VCC 17 -+#define RESET_APMU_USB2_PHY 18 -+#define RESET_APMU_USB3_A_AHB 19 -+#define RESET_APMU_USB3_A_VCC 20 - #define RESET_APMU_QSPI 21 - #define RESET_APMU_QSPI_BUS 22 - #define RESET_APMU_DMA 23 -@@ -132,8 +132,8 @@ - #define RESET_APMU_CPU7_SW 48 - #define RESET_APMU_C1_MPSUB_SW 49 - #define RESET_APMU_MPSUB_DBG 50 --#define RESET_APMU_UCIE 51 --#define RESET_APMU_RCPU 52 -+#define RESET_APMU_USB3_A_PHY 51 /* USB3 A */ -+#define RESET_APMU_USB3_B_AHB 52 - #define RESET_APMU_DSI4LN2_ESCCLK 53 - #define RESET_APMU_DSI4LN2_LCD_SW 54 - #define RESET_APMU_DSI4LN2_LCD_MCLK 55 -@@ -143,16 +143,40 @@ - #define RESET_APMU_UFS_ACLK 59 - #define RESET_APMU_EDP0 60 - #define RESET_APMU_EDP1 61 --#define RESET_APMU_PCIE_PORTA 62 --#define RESET_APMU_PCIE_PORTB 63 --#define RESET_APMU_PCIE_PORTC 64 --#define RESET_APMU_PCIE_PORTD 65 --#define RESET_APMU_PCIE_PORTE 66 -+#define RESET_APMU_USB3_B_VCC 62 /* USB3 B */ -+#define RESET_APMU_USB3_B_PHY 63 -+#define RESET_APMU_USB3_C_AHB 64 -+#define RESET_APMU_USB3_C_VCC 65 -+#define RESET_APMU_USB3_C_PHY 66 - #define RESET_APMU_EMAC0 67 - #define RESET_APMU_EMAC1 68 - #define RESET_APMU_EMAC2 69 - #define RESET_APMU_ESPI_MCLK 70 - #define RESET_APMU_ESPI_SCLK 71 -+#define RESET_APMU_USB3_D_AHB 72 /* USB3 D */ -+#define RESET_APMU_USB3_D_VCC 73 -+#define RESET_APMU_USB3_D_PHY 74 -+#define RESET_APMU_UCIE_IP 75 -+#define RESET_APMU_UCIE_HOT 76 -+#define RESET_APMU_UCIE_MON 77 -+#define RESET_APMU_RCPU_AUDIO_SYS 78 -+#define RESET_APMU_RCPU_MCU_CORE 79 -+#define RESET_APMU_RCPU_AUDIO_APMU 80 -+#define RESET_APMU_PCIE_A_DBI 81 -+#define RESET_APMU_PCIE_A_SLAVE 82 -+#define RESET_APMU_PCIE_A_MASTER 83 -+#define RESET_APMU_PCIE_B_DBI 84 -+#define RESET_APMU_PCIE_B_SLAVE 85 -+#define RESET_APMU_PCIE_B_MASTER 86 -+#define RESET_APMU_PCIE_C_DBI 87 -+#define RESET_APMU_PCIE_C_SLAVE 88 -+#define RESET_APMU_PCIE_C_MASTER 89 -+#define RESET_APMU_PCIE_D_DBI 90 -+#define RESET_APMU_PCIE_D_SLAVE 91 -+#define RESET_APMU_PCIE_D_MASTER 92 -+#define RESET_APMU_PCIE_E_DBI 93 -+#define RESET_APMU_PCIE_E_SLAVE 94 -+#define RESET_APMU_PCIE_E_MASTER 95 - - /* DCIU resets*/ - #define RESET_DCIU_HDMA 0 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch b/SPECS/linux-lts-kmhv2/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch new file mode 100644 index 0000000000..bfdd63b39b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch @@ -0,0 +1,55 @@ +From b521133241a4f965f50ccf4af99769c36904d779 Mon Sep 17 00:00:00 2001 +From: Alice Ryhl +Date: Mon, 23 Feb 2026 10:08:27 +0000 +Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: remove impl Send/Sync for + Th1520PwmDriverData +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Now that clk implements Send and Sync, we no longer need to manually +implement these traits for Th1520PwmDriverData. Thus remove the +implementations. + +Reviewed-by: Gary Guo +Reviewed-by: Daniel Almeida +Acked-by: Uwe Kleine-König +Reviewed-by: Michal Wilczynski +Signed-off-by: Alice Ryhl +Link: https://patch.msgid.link/20260223-clk-send-sync-v5-3-181bf2f35652@google.com +Signed-off-by: Miguel Ojeda +(cherry picked from commit 96f4e74cab632ea5c7e7fa996a28337283ecca11) +Signed-off-by: Han Gao +--- + drivers/pwm/pwm_th1520.rs | 15 --------------- + 1 file changed, 15 deletions(-) + +diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs +index 571db5928356..5559f4273b3d 100644 +--- a/drivers/pwm/pwm_th1520.rs ++++ b/drivers/pwm/pwm_th1520.rs +@@ -94,21 +94,6 @@ struct Th1520PwmDriverData { + clk: Clk, + } + +-// This `unsafe` implementation is a temporary necessity because the underlying `kernel::clk::Clk` +-// type does not yet expose `Send` and `Sync` implementations. This block should be removed +-// as soon as the clock abstraction provides these guarantees directly. +-// TODO: Remove those unsafe impl's when Clk will support them itself. +- +-// SAFETY: The `devres` framework requires the driver's private data to be `Send` and `Sync`. +-// We can guarantee this because the PWM core synchronizes all callbacks, preventing concurrent +-// access to the contained `iomem` and `clk` resources. +-unsafe impl Send for Th1520PwmDriverData {} +- +-// SAFETY: The same reasoning applies as for `Send`. The PWM core's synchronization +-// guarantees that it is safe for multiple threads to have shared access (`&self`) +-// to the driver data during callbacks. +-unsafe impl Sync for Th1520PwmDriverData {} +- + impl pwm::PwmOps for Th1520PwmDriverData { + type WfHw = Th1520WfHw; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0178-UPSTREAM-rust-clk-implement-Send-and-Sync.patch b/SPECS/linux-lts-kmhv2/0178-UPSTREAM-rust-clk-implement-Send-and-Sync.patch deleted file mode 100644 index 1806623564..0000000000 --- a/SPECS/linux-lts-kmhv2/0178-UPSTREAM-rust-clk-implement-Send-and-Sync.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 1642a007a0a6fae07e706694a837771d62f6a5fd Mon Sep 17 00:00:00 2001 -From: Alice Ryhl -Date: Mon, 23 Feb 2026 10:08:25 +0000 -Subject: [PATCH 178/467] UPSTREAM: rust: clk: implement Send and Sync - -These traits are required for drivers to embed the Clk type in their own -data structures because driver data structures are usually required to -be Send. Since the Clk type is thread-safe, implement the relevant -traits. - -Reviewed-by: Daniel Almeida -Reviewed-by: Danilo Krummrich -Acked-by: Viresh Kumar -Reviewed-by: Boqun Feng -Reviewed-by: Gary Guo -Signed-off-by: Alice Ryhl -Acked-by: Brian Masney # Active contributor to clk -Link: https://patch.msgid.link/20260223-clk-send-sync-v5-1-181bf2f35652@google.com -Signed-off-by: Miguel Ojeda -(cherry picked from commit 0c0695a9d8c97f63d71dc890faa6999eef728f57) -Signed-off-by: Han Gao ---- - rust/kernel/clk.rs | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/rust/kernel/clk.rs b/rust/kernel/clk.rs -index 1e6c8c42fb3a..0a290202da69 100644 ---- a/rust/kernel/clk.rs -+++ b/rust/kernel/clk.rs -@@ -129,6 +129,13 @@ mod common_clk { - #[repr(transparent)] - pub struct Clk(*mut bindings::clk); - -+ // SAFETY: It is safe to call `clk_put` on another thread than where `clk_get` was called. -+ unsafe impl Send for Clk {} -+ -+ // SAFETY: It is safe to call any combination of the `&self` methods in parallel, as the -+ // methods are synchronized internally. -+ unsafe impl Sync for Clk {} -+ - impl Clk { - /// Gets [`Clk`] corresponding to a [`Device`] and a connection id. - /// --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch b/SPECS/linux-lts-kmhv2/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch new file mode 100644 index 0000000000..3373671d06 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch @@ -0,0 +1,49 @@ +From 32264ffa5210859b00dbce09fa640779874438f7 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 5 Mar 2026 15:00:29 +0800 +Subject: [RUYI PATCH] UPSTREAM: net: spacemit: Remove unused buff_addr fields + +These were never used. Just remove them. + +No functional change intended. + +Signed-off-by: Vivian Wang +Link: https://patch.msgid.link/20260305-k1-ethernet-cleanup-buff_addr-v1-1-e978ef119231@iscas.ac.cn +Signed-off-by: Jakub Kicinski +(cherry picked from commit 70eba59f92076d84264762d63d30532685943017) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/spacemit/k1_emac.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c +index 52c0c00a471f..359b409f8203 100644 +--- a/drivers/net/ethernet/spacemit/k1_emac.c ++++ b/drivers/net/ethernet/spacemit/k1_emac.c +@@ -59,7 +59,6 @@ + + struct desc_buf { + u64 dma_addr; +- void *buff_addr; + u16 dma_len; + u8 map_as_page; + }; +@@ -72,7 +71,6 @@ struct emac_tx_desc_buffer { + struct emac_rx_desc_buffer { + struct sk_buff *skb; + u64 dma_addr; +- void *buff_addr; + u16 dma_len; + u8 map_as_page; + }; +@@ -355,7 +353,6 @@ static void emac_free_tx_buf(struct emac_priv *priv, int i) + + buf->dma_addr = 0; + buf->map_as_page = false; +- buf->buff_addr = NULL; + } + + if (tx_buf->skb) { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0179-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch b/SPECS/linux-lts-kmhv2/0179-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch deleted file mode 100644 index 8176cbc5dd..0000000000 --- a/SPECS/linux-lts-kmhv2/0179-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 98d1f3807843d1600d9c0fed44a0c1cfeee7e373 Mon Sep 17 00:00:00 2001 -From: Alice Ryhl -Date: Mon, 23 Feb 2026 10:08:26 +0000 -Subject: [PATCH 179/467] UPSTREAM: tyr: remove impl Send/Sync for TyrData - -Now that clk implements Send and Sync, we no longer need to manually -implement these traits for TyrData. Thus remove the implementations. - -The comment also mentions the regulator. However, the regulator had the -traits added in commit 9a200cbdb543 ("rust: regulator: implement Send -and Sync for Regulator"), which is already in mainline. - -Reviewed-by: Danilo Krummrich -Reviewed-by: Boqun Feng -Reviewed-by: Gary Guo -Reviewed-by: Daniel Almeida -Signed-off-by: Alice Ryhl -Link: https://patch.msgid.link/20260223-clk-send-sync-v5-2-181bf2f35652@google.com -Signed-off-by: Miguel Ojeda -(cherry picked from commit ef90b103e8f767ffc31b1ddfef012358ea873d85) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/tyr/driver.rs | 12 ------------ - 1 file changed, 12 deletions(-) - -diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver.rs -index 0052ebe95719..0b741450724e 100644 ---- a/drivers/gpu/drm/tyr/driver.rs -+++ b/drivers/gpu/drm/tyr/driver.rs -@@ -53,18 +53,6 @@ pub(crate) struct TyrData { - pub(crate) gpu_info: GpuInfo, - } - --// Both `Clk` and `Regulator` do not implement `Send` or `Sync`, but they --// should. There are patches on the mailing list to address this, but they have --// not landed yet. --// --// For now, add this workaround so that this patch compiles with the promise --// that it will be removed in a future patch. --// --// SAFETY: This will be removed in a future patch. --unsafe impl Send for TyrData {} --// SAFETY: This will be removed in a future patch. --unsafe impl Sync for TyrData {} -- - fn issue_soft_reset(dev: &Device, iomem: &Devres) -> Result { - regs::GPU_CMD.write(dev, iomem, regs::GPU_CMD_SOFT_RESET)?; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch b/SPECS/linux-lts-kmhv2/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch new file mode 100644 index 0000000000..9f38d216be --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch @@ -0,0 +1,154 @@ +From c446f352ebab05c2cef0a9835bd9224e19c24ccb Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Mon, 16 Mar 2026 09:00:37 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: net: Add support for Spacemit K3 + dwmac + +The GMAC IP on Spacemit K3 is almost a standard Synopsys DesignWare +MAC (version 5.40a) with some extra clock. + +Add necessary compatible string for this device. + +Signed-off-by: Inochi Amaoto +Reviewed-by: Rob Herring (Arm) +Link: https://patch.msgid.link/20260316010041.164360-2-inochiama@gmail.com +Signed-off-by: Jakub Kicinski +(cherry picked from commit bb30400a566c7a6a9355873344ec63e2c6310e2c) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/net/snps,dwmac.yaml | 2 + + .../bindings/net/spacemit,k3-dwmac.yaml | 102 ++++++++++++++++++ + 2 files changed, 104 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml + +diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +index 658c004e6a5c..eb36cb36a57a 100644 +--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml ++++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +@@ -104,6 +104,7 @@ properties: + - snps,dwmac-5.10a + - snps,dwmac-5.20 + - snps,dwmac-5.30a ++ - snps,dwmac-5.40a + - snps,dwxgmac + - snps,dwxgmac-2.10 + - sophgo,sg2042-dwmac +@@ -649,6 +650,7 @@ allOf: + - snps,dwmac-5.10a + - snps,dwmac-5.20 + - snps,dwmac-5.30a ++ - snps,dwmac-5.40a + - snps,dwxgmac + - snps,dwxgmac-2.10 + - st,spear600-gmac +diff --git a/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml b/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml +new file mode 100644 +index 000000000000..678eccf044f9 +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml +@@ -0,0 +1,102 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/spacemit,k3-dwmac.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Spacemit K3 DWMAC glue layer ++ ++maintainers: ++ - Inochi Amaoto ++ ++select: ++ properties: ++ compatible: ++ contains: ++ const: spacemit,k3-dwmac ++ required: ++ - compatible ++ ++properties: ++ compatible: ++ items: ++ - const: spacemit,k3-dwmac ++ - const: snps,dwmac-5.40a ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: GMAC application clock ++ - description: PTP clock ++ - description: TX clock ++ ++ clock-names: ++ items: ++ - const: stmmaceth ++ - const: ptp_ref ++ - const: tx ++ ++ interrupts: ++ minItems: 1 ++ items: ++ - description: MAC interrupt ++ - description: MAC wake interrupt ++ ++ interrupt-names: ++ minItems: 1 ++ items: ++ - const: macirq ++ - const: eth_wake_irq ++ ++ resets: ++ maxItems: 1 ++ ++ reset-names: ++ const: stmmaceth ++ ++ spacemit,apmu: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle to the syscon node which control the glue register ++ - description: offset of the control register ++ - description: offset of the dline register ++ description: ++ A phandle to syscon with offset to control registers for this MAC ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - interrupts ++ - interrupt-names ++ - resets ++ - reset-names ++ - spacemit,apmu ++ ++allOf: ++ - $ref: snps,dwmac.yaml# ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ ++ ethernet@cac80000 { ++ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; ++ reg = <0xcac80000 0x2000>; ++ clocks = <&syscon_apmu 66>, <&syscon_apmu 68>, ++ <&syscon_apmu 69>; ++ clock-names = "stmmaceth", "ptp_ref", "tx"; ++ interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, <276 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&phy0>; ++ resets = <&syscon_apmu 67>; ++ reset-names = "stmmaceth"; ++ spacemit,apmu = <&syscon_apmu 0x384 0x38c>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0180-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch b/SPECS/linux-lts-kmhv2/0180-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch deleted file mode 100644 index bfcbe3e3d7..0000000000 --- a/SPECS/linux-lts-kmhv2/0180-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 9ca8e005adc28dc70cd2159ee5e1b4357360f8e3 Mon Sep 17 00:00:00 2001 -From: Miguel Ojeda -Date: Wed, 21 Jan 2026 19:37:19 +0100 -Subject: [PATCH 180/467] UPSTREAM: pwm: th1520: fix `CLIPPY=1` warning -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The Rust kernel code should be kept `CLIPPY=1`-clean [1]. - -Clippy reports: - - error: this pattern reimplements `Option::unwrap_or` - --> drivers/pwm/pwm_th1520.rs:64:5 - | - 64 | / (match ns.checked_mul(rate_hz) { - 65 | | Some(product) => product, - 66 | | None => u64::MAX, - 67 | | }) / NSEC_PER_SEC_U64 - | |______^ help: replace with: `ns.checked_mul(rate_hz).unwrap_or(u64::MAX)` - | - = help: for further information visit https://rust-lang.github.io/rust-clippy/rust-1.92.0/index.html#manual_unwrap_or - = note: `-D clippy::manual-unwrap-or` implied by `-D warnings` - = help: to override `-D warnings` add `#[allow(clippy::manual_unwrap_or)]` - -Applying the suggestion then triggers: - - error: manual saturating arithmetic - --> drivers/pwm/pwm_th1520.rs:64:5 - | - 64 | ns.checked_mul(rate_hz).unwrap_or(u64::MAX) / NSEC_PER_SEC_U64 - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `saturating_mul`: `ns.saturating_mul(rate_hz)` - | - = help: for further information visit https://rust-lang.github.io/rust-clippy/rust-1.92.0/index.html#manual_saturating_arithmetic - = note: `-D clippy::manual-saturating-arithmetic` implied by `-D warnings` - = help: to override `-D warnings` add `#[allow(clippy::manual_saturating_arithmetic)]` - -Thus fix it by using saturating arithmetic, which simplifies the code -as well. - -Link: https://rust-for-linux.com/contributing#submit-checklist-addendum [1] -Fixes: e03724aac758 ("pwm: Add Rust driver for T-HEAD TH1520 SoC") -Signed-off-by: Miguel Ojeda -Reviewed-by: Danilo Krummrich -Reviewed-by: Michal Wilczynski -Link: https://patch.msgid.link/20260121183719.71659-1-ojeda@kernel.org -Signed-off-by: Uwe Kleine-König -(cherry picked from commit aa8f35172ab66c57d4355a8c4e28d05b44c938e3) -Signed-off-by: Han Gao ---- - drivers/pwm/pwm_th1520.rs | 5 +---- - 1 file changed, 1 insertion(+), 4 deletions(-) - -diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs -index 955c359b07fb..571db5928356 100644 ---- a/drivers/pwm/pwm_th1520.rs -+++ b/drivers/pwm/pwm_th1520.rs -@@ -62,10 +62,7 @@ const fn th1520_pwm_fp(n: u32) -> usize { - fn ns_to_cycles(ns: u64, rate_hz: u64) -> u64 { - const NSEC_PER_SEC_U64: u64 = time::NSEC_PER_SEC as u64; - -- (match ns.checked_mul(rate_hz) { -- Some(product) => product, -- None => u64::MAX, -- }) / NSEC_PER_SEC_U64 -+ ns.saturating_mul(rate_hz) / NSEC_PER_SEC_U64 - } - - fn cycles_to_ns(cycles: u64, rate_hz: u64) -> u64 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch b/SPECS/linux-lts-kmhv2/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch new file mode 100644 index 0000000000..e0e422ae4b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch @@ -0,0 +1,34 @@ +From 415d3b3b2a8fe07f5d9c84225c47c6f3be8fd827 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Mon, 16 Mar 2026 09:00:38 +0800 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: platform: Add snps,dwmac-5.40a IP + compatible string + +Add compatible string for 5.40a version that can avoid to define some +platform data in the glue layer. + +Signed-off-by: Inochi Amaoto +Reviewed-by: Russell King (Oracle) +Link: https://patch.msgid.link/20260316010041.164360-3-inochiama@gmail.com +Signed-off-by: Jakub Kicinski +(cherry picked from commit d35aa97ea908a17809358a981bef6cd752f2e8a0) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +index 0cb51935c405..3416ca24f623 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -414,6 +414,7 @@ static const char * const stmmac_gmac4_compats[] = { + "snps,dwmac-5.10a", + "snps,dwmac-5.20", + "snps,dwmac-5.30a", ++ "snps,dwmac-5.40a", + NULL + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0181-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch b/SPECS/linux-lts-kmhv2/0181-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch deleted file mode 100644 index 90f301730b..0000000000 --- a/SPECS/linux-lts-kmhv2/0181-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 17144d80f2540d040b45eb32a29a9afc0d23845e Mon Sep 17 00:00:00 2001 -From: Alice Ryhl -Date: Mon, 23 Feb 2026 10:08:27 +0000 -Subject: [PATCH 181/467] UPSTREAM: pwm: th1520: remove impl Send/Sync for - Th1520PwmDriverData -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Now that clk implements Send and Sync, we no longer need to manually -implement these traits for Th1520PwmDriverData. Thus remove the -implementations. - -Reviewed-by: Gary Guo -Reviewed-by: Daniel Almeida -Acked-by: Uwe Kleine-König -Reviewed-by: Michal Wilczynski -Signed-off-by: Alice Ryhl -Link: https://patch.msgid.link/20260223-clk-send-sync-v5-3-181bf2f35652@google.com -Signed-off-by: Miguel Ojeda -(cherry picked from commit 96f4e74cab632ea5c7e7fa996a28337283ecca11) -Signed-off-by: Han Gao ---- - drivers/pwm/pwm_th1520.rs | 15 --------------- - 1 file changed, 15 deletions(-) - -diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs -index 571db5928356..5559f4273b3d 100644 ---- a/drivers/pwm/pwm_th1520.rs -+++ b/drivers/pwm/pwm_th1520.rs -@@ -94,21 +94,6 @@ struct Th1520PwmDriverData { - clk: Clk, - } - --// This `unsafe` implementation is a temporary necessity because the underlying `kernel::clk::Clk` --// type does not yet expose `Send` and `Sync` implementations. This block should be removed --// as soon as the clock abstraction provides these guarantees directly. --// TODO: Remove those unsafe impl's when Clk will support them itself. -- --// SAFETY: The `devres` framework requires the driver's private data to be `Send` and `Sync`. --// We can guarantee this because the PWM core synchronizes all callbacks, preventing concurrent --// access to the contained `iomem` and `clk` resources. --unsafe impl Send for Th1520PwmDriverData {} -- --// SAFETY: The same reasoning applies as for `Send`. The PWM core's synchronization --// guarantees that it is safe for multiple threads to have shared access (`&self`) --// to the driver data during callbacks. --unsafe impl Sync for Th1520PwmDriverData {} -- - impl pwm::PwmOps for Th1520PwmDriverData { - type WfHw = Th1520WfHw; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0182-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch b/SPECS/linux-lts-kmhv2/0182-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch deleted file mode 100644 index 5b71138373..0000000000 --- a/SPECS/linux-lts-kmhv2/0182-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 4a69779f56c915bdce7bc724b34f0efd8a77f9fb Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 5 Mar 2026 15:00:29 +0800 -Subject: [PATCH 182/467] UPSTREAM: net: spacemit: Remove unused buff_addr - fields - -These were never used. Just remove them. - -No functional change intended. - -Signed-off-by: Vivian Wang -Link: https://patch.msgid.link/20260305-k1-ethernet-cleanup-buff_addr-v1-1-e978ef119231@iscas.ac.cn -Signed-off-by: Jakub Kicinski -(cherry picked from commit 70eba59f92076d84264762d63d30532685943017) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/spacemit/k1_emac.c | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c -index 52c0c00a471f..359b409f8203 100644 ---- a/drivers/net/ethernet/spacemit/k1_emac.c -+++ b/drivers/net/ethernet/spacemit/k1_emac.c -@@ -59,7 +59,6 @@ - - struct desc_buf { - u64 dma_addr; -- void *buff_addr; - u16 dma_len; - u8 map_as_page; - }; -@@ -72,7 +71,6 @@ struct emac_tx_desc_buffer { - struct emac_rx_desc_buffer { - struct sk_buff *skb; - u64 dma_addr; -- void *buff_addr; - u16 dma_len; - u8 map_as_page; - }; -@@ -355,7 +353,6 @@ static void emac_free_tx_buf(struct emac_priv *priv, int i) - - buf->dma_addr = 0; - buf->map_as_page = false; -- buf->buff_addr = NULL; - } - - if (tx_buf->skb) { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch b/SPECS/linux-lts-kmhv2/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch new file mode 100644 index 0000000000..e3ca4ecc6c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch @@ -0,0 +1,300 @@ +From 945ce43958e6a4b22a3bf632d66514c6e279d2e9 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Mon, 16 Mar 2026 09:00:39 +0800 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: Add glue layer for Spacemit K3 + SoC + +The ethernet controller on Spacemit K3 SoC is Synopsys DesignWare +MAC (version 5.40a), with the following special points: +1. The rate of the tx clock line is auto changed when the mac speed + rate is changed, and no need for changing the input tx clock. +2. This controller require a extra syscon device to configure the + interface type, enable wake up interrupt and delay configuration + if needed. + +Add Spacemit dwmac driver support on the Spacemit K3 SoC. + +Signed-off-by: Inochi Amaoto +Reviewed-by: Russell King (Oracle) +Link: https://patch.msgid.link/20260316010041.164360-4-inochiama@gmail.com +Signed-off-by: Jakub Kicinski +(cherry picked from commit 30f0ba420ed3fb9a16d55523ae3c1b43a6f00e22) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 + + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + + .../ethernet/stmicro/stmmac/dwmac-spacemit.c | 227 ++++++++++++++++++ + 3 files changed, 240 insertions(+) + create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c + +diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig +index 9507131875b2..3209353b7659 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig ++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig +@@ -206,6 +206,18 @@ config DWMAC_SOPHGO + for the stmmac device driver. This driver is used for the + ethernet controllers on various Sophgo SoCs. + ++config DWMAC_SPACEMIT ++ tristate "Spacemit dwmac support" ++ depends on OF && (ARCH_SPACEMIT || COMPILE_TEST) ++ select MFD_SYSCON ++ default m if ARCH_SPACEMIT ++ help ++ Support for ethernet controllers on Spacemit RISC-V SoCs ++ ++ This selects the Spacemit platform specific glue layer support ++ for the stmmac device driver. This driver is used for the ++ Spacemit K3 ethernet controllers. ++ + config DWMAC_STARFIVE + tristate "StarFive dwmac support" + depends on OF && (ARCH_STARFIVE || COMPILE_TEST) +diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile +index 51e068e26ce4..2a24934f5c43 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Makefile ++++ b/drivers/net/ethernet/stmicro/stmmac/Makefile +@@ -26,6 +26,7 @@ obj-$(CONFIG_DWMAC_RZN1) += dwmac-rzn1.o + obj-$(CONFIG_DWMAC_S32) += dwmac-s32.o + obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o + obj-$(CONFIG_DWMAC_SOPHGO) += dwmac-sophgo.o ++obj-$(CONFIG_DWMAC_SPACEMIT) += dwmac-spacemit.o + obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o + obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o + obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c +new file mode 100644 +index 000000000000..223754cc5c79 +--- /dev/null ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c +@@ -0,0 +1,227 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Spacemit DWMAC platform driver ++ * ++ * Copyright (C) 2026 Inochi Amaoto ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "stmmac_platform.h" ++ ++/* ctrl register bits */ ++#define CTRL_PHY_INTF_RGMII BIT(3) ++#define CTRL_PHY_INTF_MII BIT(4) ++#define CTRL_WAKE_IRQ_EN BIT(9) ++#define CTRL_PHY_IRQ_EN BIT(12) ++ ++/* dline register bits */ ++#define RGMII_RX_DLINE_EN BIT(0) ++#define RGMII_RX_DLINE_STEP GENMASK(5, 4) ++#define RGMII_RX_DLINE_CODE GENMASK(15, 8) ++#define RGMII_TX_DLINE_EN BIT(16) ++#define RGMII_TX_DLINE_STEP GENMASK(21, 20) ++#define RGMII_TX_DLINE_CODE GENMASK(31, 24) ++ ++#define MAX_DLINE_DELAY_CODE 0xff ++#define MAX_WORKED_DELAY 2800 ++/* Note: the delay step value is at 0.1ps */ ++#define K3_DELAY_STEP 367 ++ ++struct spacmit_dwmac { ++ struct regmap *apmu; ++ unsigned int ctrl_offset; ++ unsigned int dline_offset; ++}; ++ ++static int spacemit_dwmac_set_delay(struct spacmit_dwmac *dwmac, ++ unsigned int tx_code, unsigned int rx_code) ++{ ++ unsigned int mask, val; ++ ++ mask = RGMII_TX_DLINE_STEP | RGMII_TX_DLINE_CODE | RGMII_TX_DLINE_EN | ++ RGMII_RX_DLINE_STEP | RGMII_RX_DLINE_CODE | RGMII_RX_DLINE_EN; ++ ++ /* ++ * Since the delay step provided by config 0 is small enough, and ++ * it can cover the range of the valid delay, so there is no needed ++ * to use other step config. ++ */ ++ val = FIELD_PREP(RGMII_TX_DLINE_STEP, 0) | ++ FIELD_PREP(RGMII_TX_DLINE_CODE, tx_code) | RGMII_TX_DLINE_EN | ++ FIELD_PREP(RGMII_RX_DLINE_STEP, 0) | ++ FIELD_PREP(RGMII_RX_DLINE_CODE, rx_code) | RGMII_RX_DLINE_EN; ++ ++ return regmap_update_bits(dwmac->apmu, dwmac->dline_offset, ++ mask, val); ++} ++ ++static int spacemit_dwmac_detected_delay_value(unsigned int delay) ++{ ++ if (delay == 0) ++ return 0; ++ ++ if (delay > MAX_WORKED_DELAY) ++ return -EINVAL; ++ ++ /* ++ * Note K3 require a specific factor for calculate ++ * the delay, in this scenario it is 0.9. So the ++ * formula is code * step / 10 * 0.9 ++ */ ++ return DIV_ROUND_CLOSEST(delay * 10 * 10, K3_DELAY_STEP * 9); ++} ++ ++static int spacemit_dwmac_fix_delay(struct spacmit_dwmac *dwmac, ++ unsigned int tx_delay, ++ unsigned int rx_delay) ++{ ++ int rx_code; ++ int tx_code; ++ ++ rx_code = spacemit_dwmac_detected_delay_value(rx_delay); ++ if (rx_code < 0) ++ return rx_code; ++ ++ tx_code = spacemit_dwmac_detected_delay_value(tx_delay); ++ if (tx_code < 0) ++ return tx_code; ++ ++ return spacemit_dwmac_set_delay(dwmac, tx_code, rx_code); ++} ++ ++static int spacemit_dwmac_update_irq_config(struct spacmit_dwmac *dwmac, ++ struct stmmac_resources *stmmac_res) ++{ ++ unsigned int val = stmmac_res->wol_irq >= 0 ? CTRL_WAKE_IRQ_EN : 0; ++ unsigned int mask = CTRL_WAKE_IRQ_EN; ++ ++ return regmap_update_bits(dwmac->apmu, dwmac->ctrl_offset, ++ mask, val); ++} ++ ++static void spacemit_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, ++ unsigned long *interfaces) ++{ ++ __set_bit(PHY_INTERFACE_MODE_MII, interfaces); ++ __set_bit(PHY_INTERFACE_MODE_RMII, interfaces); ++ phy_interface_set_rgmii(interfaces); ++} ++ ++static int spacemit_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) ++{ ++ unsigned int mask = CTRL_PHY_INTF_MII | CTRL_PHY_INTF_RGMII; ++ struct spacmit_dwmac *dwmac = bsp_priv; ++ unsigned int val = 0; ++ ++ switch (phy_intf_sel) { ++ case PHY_INTF_SEL_GMII_MII: ++ val = CTRL_PHY_INTF_MII; ++ break; ++ ++ case PHY_INTF_SEL_RMII: ++ break; ++ ++ case PHY_INTF_SEL_RGMII: ++ val = CTRL_PHY_INTF_RGMII; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ return regmap_update_bits(dwmac->apmu, dwmac->ctrl_offset, ++ mask, val); ++} ++ ++static int spacemit_dwmac_probe(struct platform_device *pdev) ++{ ++ struct plat_stmmacenet_data *plat_dat; ++ struct stmmac_resources stmmac_res; ++ struct device *dev = &pdev->dev; ++ struct spacmit_dwmac *dwmac; ++ unsigned int offset[2]; ++ struct regmap *apmu; ++ struct clk *clk_tx; ++ u32 rx_delay = 0; ++ u32 tx_delay = 0; ++ int ret; ++ ++ ret = stmmac_get_platform_resources(pdev, &stmmac_res); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "failed to get platform resources\n"); ++ ++ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); ++ if (!dwmac) ++ return -ENOMEM; ++ ++ plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); ++ if (IS_ERR(plat_dat)) ++ return dev_err_probe(dev, PTR_ERR(plat_dat), ++ "failed to parse DT parameters\n"); ++ ++ clk_tx = devm_clk_get_enabled(&pdev->dev, "tx"); ++ if (IS_ERR(clk_tx)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(clk_tx), ++ "failed to get tx clock\n"); ++ ++ apmu = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, ++ "spacemit,apmu", 2, ++ offset); ++ if (IS_ERR(apmu)) ++ return dev_err_probe(dev, PTR_ERR(apmu), ++ "Failed to get apmu regmap\n"); ++ ++ dwmac->apmu = apmu; ++ dwmac->ctrl_offset = offset[0]; ++ dwmac->dline_offset = offset[1]; ++ ++ ret = spacemit_dwmac_update_irq_config(dwmac, &stmmac_res); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to configure irq config\n"); ++ ++ of_property_read_u32(pdev->dev.of_node, "tx-internal-delay-ps", ++ &tx_delay); ++ of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps", ++ &rx_delay); ++ ++ plat_dat->get_interfaces = spacemit_get_interfaces; ++ plat_dat->set_phy_intf_sel = spacemit_set_phy_intf_sel; ++ plat_dat->bsp_priv = dwmac; ++ ++ ret = spacemit_dwmac_fix_delay(dwmac, tx_delay, rx_delay); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to configure delay\n"); ++ ++ return stmmac_dvr_probe(dev, plat_dat, &stmmac_res); ++} ++ ++static const struct of_device_id spacemit_dwmac_match[] = { ++ { .compatible = "spacemit,k3-dwmac" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, spacemit_dwmac_match); ++ ++static struct platform_driver spacemit_dwmac_driver = { ++ .probe = spacemit_dwmac_probe, ++ .remove = stmmac_pltfr_remove, ++ .driver = { ++ .name = "spacemit-dwmac", ++ .pm = &stmmac_pltfr_pm_ops, ++ .of_match_table = spacemit_dwmac_match, ++ }, ++}; ++module_platform_driver(spacemit_dwmac_driver); ++ ++MODULE_AUTHOR("Inochi Amaoto "); ++MODULE_DESCRIPTION("Spacemit DWMAC platform driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch b/SPECS/linux-lts-kmhv2/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch new file mode 100644 index 0000000000..be1102a0eb --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch @@ -0,0 +1,53 @@ +From eaea87333b8ad51ffef8e8e2939c8aedc0c6f5f5 Mon Sep 17 00:00:00 2001 +From: Matt Coster +Date: Fri, 6 Feb 2026 16:02:12 +0000 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Improve handling of unknown + FWCCB commands + +A couple small changes: + - Validate the magic value at the head of FWCCB commands, and + - Mask off the magic value before logging unknown command types to make + them easier to interpret on sight. + +Reviewed-by: Frank Binns +Link: https://patch.msgid.link/20260206-improve-bad-fwccb-cmd-v1-1-831a852ca127@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit c7384288d9266e52cd35aadb1749872caf3c0257) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_ccb.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c +index 2bbdc05a3b97..1ccd3e3dab2b 100644 +--- a/drivers/gpu/drm/imagination/pvr_ccb.c ++++ b/drivers/gpu/drm/imagination/pvr_ccb.c +@@ -135,6 +135,14 @@ pvr_ccb_slot_available_locked(struct pvr_ccb *pvr_ccb, u32 *write_offset) + static void + process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *cmd) + { ++ struct drm_device *drm_dev = from_pvr_device(pvr_dev); ++ ++ if ((cmd->cmd_type & ROGUE_CMD_MAGIC_DWORD_MASK) != ROGUE_CMD_MAGIC_DWORD_SHIFTED) { ++ drm_warn_once(drm_dev, "Received FWCCB command with bad magic value; ignoring (type=0x%08x)\n", ++ cmd->cmd_type); ++ return; ++ } ++ + switch (cmd->cmd_type) { + case ROGUE_FWIF_FWCCB_CMD_REQUEST_GPU_RESTART: + pvr_power_reset(pvr_dev, false); +@@ -150,8 +158,8 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c + break; + + default: +- drm_info(from_pvr_device(pvr_dev), "Received unknown FWCCB command %x\n", +- cmd->cmd_type); ++ drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n", ++ cmd->cmd_type & ~ROGUE_CMD_MAGIC_DWORD_MASK); + break; + } + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0183-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch b/SPECS/linux-lts-kmhv2/0183-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch deleted file mode 100644 index db4eb1efc3..0000000000 --- a/SPECS/linux-lts-kmhv2/0183-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch +++ /dev/null @@ -1,154 +0,0 @@ -From 4a88a11688e5e382e88e35f9cf81a4be6943b420 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Mon, 16 Mar 2026 09:00:37 +0800 -Subject: [PATCH 183/467] UPSTREAM: dt-bindings: net: Add support for Spacemit - K3 dwmac - -The GMAC IP on Spacemit K3 is almost a standard Synopsys DesignWare -MAC (version 5.40a) with some extra clock. - -Add necessary compatible string for this device. - -Signed-off-by: Inochi Amaoto -Reviewed-by: Rob Herring (Arm) -Link: https://patch.msgid.link/20260316010041.164360-2-inochiama@gmail.com -Signed-off-by: Jakub Kicinski -(cherry picked from commit bb30400a566c7a6a9355873344ec63e2c6310e2c) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/net/snps,dwmac.yaml | 2 + - .../bindings/net/spacemit,k3-dwmac.yaml | 102 ++++++++++++++++++ - 2 files changed, 104 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml - -diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -index 658c004e6a5c..eb36cb36a57a 100644 ---- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml -+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -@@ -104,6 +104,7 @@ properties: - - snps,dwmac-5.10a - - snps,dwmac-5.20 - - snps,dwmac-5.30a -+ - snps,dwmac-5.40a - - snps,dwxgmac - - snps,dwxgmac-2.10 - - sophgo,sg2042-dwmac -@@ -649,6 +650,7 @@ allOf: - - snps,dwmac-5.10a - - snps,dwmac-5.20 - - snps,dwmac-5.30a -+ - snps,dwmac-5.40a - - snps,dwxgmac - - snps,dwxgmac-2.10 - - st,spear600-gmac -diff --git a/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml b/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml -new file mode 100644 -index 000000000000..678eccf044f9 ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml -@@ -0,0 +1,102 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/spacemit,k3-dwmac.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Spacemit K3 DWMAC glue layer -+ -+maintainers: -+ - Inochi Amaoto -+ -+select: -+ properties: -+ compatible: -+ contains: -+ const: spacemit,k3-dwmac -+ required: -+ - compatible -+ -+properties: -+ compatible: -+ items: -+ - const: spacemit,k3-dwmac -+ - const: snps,dwmac-5.40a -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: GMAC application clock -+ - description: PTP clock -+ - description: TX clock -+ -+ clock-names: -+ items: -+ - const: stmmaceth -+ - const: ptp_ref -+ - const: tx -+ -+ interrupts: -+ minItems: 1 -+ items: -+ - description: MAC interrupt -+ - description: MAC wake interrupt -+ -+ interrupt-names: -+ minItems: 1 -+ items: -+ - const: macirq -+ - const: eth_wake_irq -+ -+ resets: -+ maxItems: 1 -+ -+ reset-names: -+ const: stmmaceth -+ -+ spacemit,apmu: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ items: -+ - items: -+ - description: phandle to the syscon node which control the glue register -+ - description: offset of the control register -+ - description: offset of the dline register -+ description: -+ A phandle to syscon with offset to control registers for this MAC -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - interrupt-names -+ - resets -+ - reset-names -+ - spacemit,apmu -+ -+allOf: -+ - $ref: snps,dwmac.yaml# -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ -+ ethernet@cac80000 { -+ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; -+ reg = <0xcac80000 0x2000>; -+ clocks = <&syscon_apmu 66>, <&syscon_apmu 68>, -+ <&syscon_apmu 69>; -+ clock-names = "stmmaceth", "ptp_ref", "tx"; -+ interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, <276 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "macirq", "eth_wake_irq"; -+ phy-mode = "rgmii-id"; -+ phy-handle = <&phy0>; -+ resets = <&syscon_apmu 67>; -+ reset-names = "stmmaceth"; -+ spacemit,apmu = <&syscon_apmu 0x384 0x38c>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch b/SPECS/linux-lts-kmhv2/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch new file mode 100644 index 0000000000..d0de8aa1e5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch @@ -0,0 +1,40 @@ +From 74c17747b1c536e207645c2cd6bd1399b9d2ec05 Mon Sep 17 00:00:00 2001 +From: Matt Coster +Date: Fri, 6 Feb 2026 16:02:13 +0000 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Mark FWCCB_CMD_UPDATE_STATS + as known + +Suppress the "unknown type" warning when processing a FWCCB command of +type CMD_UPDATE_STATS which is known but (currently) unused. + +Reviewed-by: Frank Binns +Link: https://patch.msgid.link/20260206-improve-bad-fwccb-cmd-v1-2-831a852ca127@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 4af267ce3441e10198daa52a8cc4b5cb4575d06f) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_ccb.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c +index 1ccd3e3dab2b..da281b5c7055 100644 +--- a/drivers/gpu/drm/imagination/pvr_ccb.c ++++ b/drivers/gpu/drm/imagination/pvr_ccb.c +@@ -157,6 +157,14 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c + pvr_free_list_process_grow_req(pvr_dev, &cmd->cmd_data.cmd_free_list_gs); + break; + ++ case ROGUE_FWIF_FWCCB_CMD_UPDATE_STATS: ++ /* ++ * We currently have no infrastructure for processing these ++ * stats. It may be added in the future, but for now just ++ * suppress the "unknown" warning when receiving this command. ++ */ ++ break; ++ + default: + drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n", + cmd->cmd_type & ~ROGUE_CMD_MAGIC_DWORD_MASK); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0184-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch b/SPECS/linux-lts-kmhv2/0184-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch deleted file mode 100644 index e03a1f861d..0000000000 --- a/SPECS/linux-lts-kmhv2/0184-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch +++ /dev/null @@ -1,34 +0,0 @@ -From c8782bd2669420615c2b9caaadd9a78cd7da0123 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Mon, 16 Mar 2026 09:00:38 +0800 -Subject: [PATCH 184/467] UPSTREAM: net: stmmac: platform: Add snps,dwmac-5.40a - IP compatible string - -Add compatible string for 5.40a version that can avoid to define some -platform data in the glue layer. - -Signed-off-by: Inochi Amaoto -Reviewed-by: Russell King (Oracle) -Link: https://patch.msgid.link/20260316010041.164360-3-inochiama@gmail.com -Signed-off-by: Jakub Kicinski -(cherry picked from commit d35aa97ea908a17809358a981bef6cd752f2e8a0) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -index 0cb51935c405..3416ca24f623 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -@@ -414,6 +414,7 @@ static const char * const stmmac_gmac4_compats[] = { - "snps,dwmac-5.10a", - "snps,dwmac-5.20", - "snps,dwmac-5.30a", -+ "snps,dwmac-5.40a", - NULL - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch b/SPECS/linux-lts-kmhv2/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch new file mode 100644 index 0000000000..50ffd104f5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch @@ -0,0 +1,144 @@ +From 913bf005c8fcc762460c945ae4c4b99a3b30e116 Mon Sep 17 00:00:00 2001 +From: Brajesh Gupta +Date: Fri, 13 Mar 2026 06:38:24 +0000 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Improve firmware power off + for layout_mars config + +In layout_mars HW config, Firmware MCU moved from Sidekick to new Mars +domain so Firmware takes care of powering down Sidekick/Jones and SLC. +Skip checks for those from kernel and check idle bits for Firmware MCU +and system arbiter excluding SOCIF. + +Signed-off-by: Brajesh Gupta +Reviewed-by: Matt Coster +Link: https://patch.msgid.link/20260313-b4-staging-layout_mars_base-v2-1-9e3c251d278e@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 51e39ceeca7e85a3b9ca533502a404eb5f3b0f02) +Signed-off-by: Han Gao +--- + .../gpu/drm/imagination/pvr_fw_startstop.c | 85 +++++++++++++------ + 1 file changed, 57 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c +index dcbb9903e791..6ae0489f7e2e 100644 +--- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c ++++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c +@@ -209,18 +209,32 @@ pvr_fw_stop(struct pvr_device *pvr_dev) + ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN | + ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN); + bool skip_garten_idle = false; ++ u64 layout_mars_value = 0; ++ bool layout_mars = false; ++ bool meta_fw = pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META; + u32 reg_value; + int err; + ++ if (PVR_FEATURE_VALUE(pvr_dev, layout_mars, &layout_mars_value) == 0) ++ layout_mars = layout_mars_value > 0; ++ + /* +- * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. +- * For cores with the LAYOUT_MARS feature, SIDEKICK would have been ++ * For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have been + * powered down by the FW. + */ +- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, +- sidekick_idle_mask, POLL_TIMEOUT_USEC); +- if (err) +- return err; ++ if (!layout_mars) { ++ /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. */ ++ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, ++ sidekick_idle_mask, POLL_TIMEOUT_USEC); ++ if (err) ++ return err; ++ ++ /* Wait for SLC to signal IDLE. */ ++ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, ROGUE_CR_SLC_IDLE_MASKFULL, ++ ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); ++ if (err) ++ return err; ++ } + + /* Unset MTS DM association with threads. */ + pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC, +@@ -270,27 +284,25 @@ pvr_fw_stop(struct pvr_device *pvr_dev) + return err; + + /* +- * Wait for SLC to signal IDLE. +- * For cores with the LAYOUT_MARS feature, SLC would have been powered +- * down by the FW. ++ * For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have been ++ * powered down by the FW. + */ +- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, +- ROGUE_CR_SLC_IDLE_MASKFULL, +- ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); +- if (err) +- return err; ++ if (!layout_mars) { ++ /* Wait for SLC to signal IDLE. */ ++ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, ++ ROGUE_CR_SLC_IDLE_MASKFULL, ++ ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); ++ if (err) ++ return err; + +- /* +- * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. +- * For cores with the LAYOUT_MARS feature, SIDEKICK would have been powered +- * down by the FW. +- */ +- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, +- sidekick_idle_mask, POLL_TIMEOUT_USEC); +- if (err) +- return err; ++ /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. */ ++ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, ++ sidekick_idle_mask, POLL_TIMEOUT_USEC); ++ if (err) ++ return err; ++ } + +- if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META) { ++ if (meta_fw) { + err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, ®_value); + if (err) + return err; +@@ -304,11 +316,28 @@ pvr_fw_stop(struct pvr_device *pvr_dev) + skip_garten_idle = true; + } + +- if (!skip_garten_idle) { +- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, +- ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, +- ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, ++ if (meta_fw || !layout_mars) { ++ if (!skip_garten_idle) { ++ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, ++ ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, ++ ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, ++ POLL_TIMEOUT_USEC); ++ if (err) ++ return err; ++ } ++ } else { ++ /* ++ * As FW core has been moved from SIDEKICK to the new MARS domain, checking ++ * idle bits for CPU & System Arbiter excluding SOCIF which will never be ++ * idle if Host polling on this register ++ */ ++ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_MARS_IDLE, ++ ROGUE_CR_MARS_IDLE_CPU_EN | ++ ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN, ++ ROGUE_CR_MARS_IDLE_CPU_EN | ++ ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN, + POLL_TIMEOUT_USEC); ++ + if (err) + return err; + } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0185-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch b/SPECS/linux-lts-kmhv2/0185-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch deleted file mode 100644 index 2bfbada31b..0000000000 --- a/SPECS/linux-lts-kmhv2/0185-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch +++ /dev/null @@ -1,300 +0,0 @@ -From 837416c6927afd924e7c91dccfb60253d6a9e498 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Mon, 16 Mar 2026 09:00:39 +0800 -Subject: [PATCH 185/467] UPSTREAM: net: stmmac: Add glue layer for Spacemit K3 - SoC - -The ethernet controller on Spacemit K3 SoC is Synopsys DesignWare -MAC (version 5.40a), with the following special points: -1. The rate of the tx clock line is auto changed when the mac speed - rate is changed, and no need for changing the input tx clock. -2. This controller require a extra syscon device to configure the - interface type, enable wake up interrupt and delay configuration - if needed. - -Add Spacemit dwmac driver support on the Spacemit K3 SoC. - -Signed-off-by: Inochi Amaoto -Reviewed-by: Russell King (Oracle) -Link: https://patch.msgid.link/20260316010041.164360-4-inochiama@gmail.com -Signed-off-by: Jakub Kicinski -(cherry picked from commit 30f0ba420ed3fb9a16d55523ae3c1b43a6f00e22) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 + - drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + - .../ethernet/stmicro/stmmac/dwmac-spacemit.c | 227 ++++++++++++++++++ - 3 files changed, 240 insertions(+) - create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c - -diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig -index 9507131875b2..3209353b7659 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig -+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig -@@ -206,6 +206,18 @@ config DWMAC_SOPHGO - for the stmmac device driver. This driver is used for the - ethernet controllers on various Sophgo SoCs. - -+config DWMAC_SPACEMIT -+ tristate "Spacemit dwmac support" -+ depends on OF && (ARCH_SPACEMIT || COMPILE_TEST) -+ select MFD_SYSCON -+ default m if ARCH_SPACEMIT -+ help -+ Support for ethernet controllers on Spacemit RISC-V SoCs -+ -+ This selects the Spacemit platform specific glue layer support -+ for the stmmac device driver. This driver is used for the -+ Spacemit K3 ethernet controllers. -+ - config DWMAC_STARFIVE - tristate "StarFive dwmac support" - depends on OF && (ARCH_STARFIVE || COMPILE_TEST) -diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile -index 51e068e26ce4..2a24934f5c43 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/Makefile -+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile -@@ -26,6 +26,7 @@ obj-$(CONFIG_DWMAC_RZN1) += dwmac-rzn1.o - obj-$(CONFIG_DWMAC_S32) += dwmac-s32.o - obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o - obj-$(CONFIG_DWMAC_SOPHGO) += dwmac-sophgo.o -+obj-$(CONFIG_DWMAC_SPACEMIT) += dwmac-spacemit.o - obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o - obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o - obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c -new file mode 100644 -index 000000000000..223754cc5c79 ---- /dev/null -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c -@@ -0,0 +1,227 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Spacemit DWMAC platform driver -+ * -+ * Copyright (C) 2026 Inochi Amaoto -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "stmmac_platform.h" -+ -+/* ctrl register bits */ -+#define CTRL_PHY_INTF_RGMII BIT(3) -+#define CTRL_PHY_INTF_MII BIT(4) -+#define CTRL_WAKE_IRQ_EN BIT(9) -+#define CTRL_PHY_IRQ_EN BIT(12) -+ -+/* dline register bits */ -+#define RGMII_RX_DLINE_EN BIT(0) -+#define RGMII_RX_DLINE_STEP GENMASK(5, 4) -+#define RGMII_RX_DLINE_CODE GENMASK(15, 8) -+#define RGMII_TX_DLINE_EN BIT(16) -+#define RGMII_TX_DLINE_STEP GENMASK(21, 20) -+#define RGMII_TX_DLINE_CODE GENMASK(31, 24) -+ -+#define MAX_DLINE_DELAY_CODE 0xff -+#define MAX_WORKED_DELAY 2800 -+/* Note: the delay step value is at 0.1ps */ -+#define K3_DELAY_STEP 367 -+ -+struct spacmit_dwmac { -+ struct regmap *apmu; -+ unsigned int ctrl_offset; -+ unsigned int dline_offset; -+}; -+ -+static int spacemit_dwmac_set_delay(struct spacmit_dwmac *dwmac, -+ unsigned int tx_code, unsigned int rx_code) -+{ -+ unsigned int mask, val; -+ -+ mask = RGMII_TX_DLINE_STEP | RGMII_TX_DLINE_CODE | RGMII_TX_DLINE_EN | -+ RGMII_RX_DLINE_STEP | RGMII_RX_DLINE_CODE | RGMII_RX_DLINE_EN; -+ -+ /* -+ * Since the delay step provided by config 0 is small enough, and -+ * it can cover the range of the valid delay, so there is no needed -+ * to use other step config. -+ */ -+ val = FIELD_PREP(RGMII_TX_DLINE_STEP, 0) | -+ FIELD_PREP(RGMII_TX_DLINE_CODE, tx_code) | RGMII_TX_DLINE_EN | -+ FIELD_PREP(RGMII_RX_DLINE_STEP, 0) | -+ FIELD_PREP(RGMII_RX_DLINE_CODE, rx_code) | RGMII_RX_DLINE_EN; -+ -+ return regmap_update_bits(dwmac->apmu, dwmac->dline_offset, -+ mask, val); -+} -+ -+static int spacemit_dwmac_detected_delay_value(unsigned int delay) -+{ -+ if (delay == 0) -+ return 0; -+ -+ if (delay > MAX_WORKED_DELAY) -+ return -EINVAL; -+ -+ /* -+ * Note K3 require a specific factor for calculate -+ * the delay, in this scenario it is 0.9. So the -+ * formula is code * step / 10 * 0.9 -+ */ -+ return DIV_ROUND_CLOSEST(delay * 10 * 10, K3_DELAY_STEP * 9); -+} -+ -+static int spacemit_dwmac_fix_delay(struct spacmit_dwmac *dwmac, -+ unsigned int tx_delay, -+ unsigned int rx_delay) -+{ -+ int rx_code; -+ int tx_code; -+ -+ rx_code = spacemit_dwmac_detected_delay_value(rx_delay); -+ if (rx_code < 0) -+ return rx_code; -+ -+ tx_code = spacemit_dwmac_detected_delay_value(tx_delay); -+ if (tx_code < 0) -+ return tx_code; -+ -+ return spacemit_dwmac_set_delay(dwmac, tx_code, rx_code); -+} -+ -+static int spacemit_dwmac_update_irq_config(struct spacmit_dwmac *dwmac, -+ struct stmmac_resources *stmmac_res) -+{ -+ unsigned int val = stmmac_res->wol_irq >= 0 ? CTRL_WAKE_IRQ_EN : 0; -+ unsigned int mask = CTRL_WAKE_IRQ_EN; -+ -+ return regmap_update_bits(dwmac->apmu, dwmac->ctrl_offset, -+ mask, val); -+} -+ -+static void spacemit_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, -+ unsigned long *interfaces) -+{ -+ __set_bit(PHY_INTERFACE_MODE_MII, interfaces); -+ __set_bit(PHY_INTERFACE_MODE_RMII, interfaces); -+ phy_interface_set_rgmii(interfaces); -+} -+ -+static int spacemit_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) -+{ -+ unsigned int mask = CTRL_PHY_INTF_MII | CTRL_PHY_INTF_RGMII; -+ struct spacmit_dwmac *dwmac = bsp_priv; -+ unsigned int val = 0; -+ -+ switch (phy_intf_sel) { -+ case PHY_INTF_SEL_GMII_MII: -+ val = CTRL_PHY_INTF_MII; -+ break; -+ -+ case PHY_INTF_SEL_RMII: -+ break; -+ -+ case PHY_INTF_SEL_RGMII: -+ val = CTRL_PHY_INTF_RGMII; -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ return regmap_update_bits(dwmac->apmu, dwmac->ctrl_offset, -+ mask, val); -+} -+ -+static int spacemit_dwmac_probe(struct platform_device *pdev) -+{ -+ struct plat_stmmacenet_data *plat_dat; -+ struct stmmac_resources stmmac_res; -+ struct device *dev = &pdev->dev; -+ struct spacmit_dwmac *dwmac; -+ unsigned int offset[2]; -+ struct regmap *apmu; -+ struct clk *clk_tx; -+ u32 rx_delay = 0; -+ u32 tx_delay = 0; -+ int ret; -+ -+ ret = stmmac_get_platform_resources(pdev, &stmmac_res); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "failed to get platform resources\n"); -+ -+ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); -+ if (!dwmac) -+ return -ENOMEM; -+ -+ plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); -+ if (IS_ERR(plat_dat)) -+ return dev_err_probe(dev, PTR_ERR(plat_dat), -+ "failed to parse DT parameters\n"); -+ -+ clk_tx = devm_clk_get_enabled(&pdev->dev, "tx"); -+ if (IS_ERR(clk_tx)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(clk_tx), -+ "failed to get tx clock\n"); -+ -+ apmu = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, -+ "spacemit,apmu", 2, -+ offset); -+ if (IS_ERR(apmu)) -+ return dev_err_probe(dev, PTR_ERR(apmu), -+ "Failed to get apmu regmap\n"); -+ -+ dwmac->apmu = apmu; -+ dwmac->ctrl_offset = offset[0]; -+ dwmac->dline_offset = offset[1]; -+ -+ ret = spacemit_dwmac_update_irq_config(dwmac, &stmmac_res); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to configure irq config\n"); -+ -+ of_property_read_u32(pdev->dev.of_node, "tx-internal-delay-ps", -+ &tx_delay); -+ of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps", -+ &rx_delay); -+ -+ plat_dat->get_interfaces = spacemit_get_interfaces; -+ plat_dat->set_phy_intf_sel = spacemit_set_phy_intf_sel; -+ plat_dat->bsp_priv = dwmac; -+ -+ ret = spacemit_dwmac_fix_delay(dwmac, tx_delay, rx_delay); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to configure delay\n"); -+ -+ return stmmac_dvr_probe(dev, plat_dat, &stmmac_res); -+} -+ -+static const struct of_device_id spacemit_dwmac_match[] = { -+ { .compatible = "spacemit,k3-dwmac" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, spacemit_dwmac_match); -+ -+static struct platform_driver spacemit_dwmac_driver = { -+ .probe = spacemit_dwmac_probe, -+ .remove = stmmac_pltfr_remove, -+ .driver = { -+ .name = "spacemit-dwmac", -+ .pm = &stmmac_pltfr_pm_ops, -+ .of_match_table = spacemit_dwmac_match, -+ }, -+}; -+module_platform_driver(spacemit_dwmac_driver); -+ -+MODULE_AUTHOR("Inochi Amaoto "); -+MODULE_DESCRIPTION("Spacemit DWMAC platform driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0186-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch b/SPECS/linux-lts-kmhv2/0186-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch deleted file mode 100644 index 6e6ee0a8cc..0000000000 --- a/SPECS/linux-lts-kmhv2/0186-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 870f5224fe15bfcd81de45da48168616a0d5c1d5 Mon Sep 17 00:00:00 2001 -From: Matt Coster -Date: Fri, 6 Feb 2026 16:02:12 +0000 -Subject: [PATCH 186/467] UPSTREAM: drm/imagination: Improve handling of - unknown FWCCB commands - -A couple small changes: - - Validate the magic value at the head of FWCCB commands, and - - Mask off the magic value before logging unknown command types to make - them easier to interpret on sight. - -Reviewed-by: Frank Binns -Link: https://patch.msgid.link/20260206-improve-bad-fwccb-cmd-v1-1-831a852ca127@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit c7384288d9266e52cd35aadb1749872caf3c0257) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_ccb.c | 12 ++++++++++-- - 1 file changed, 10 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c -index 2bbdc05a3b97..1ccd3e3dab2b 100644 ---- a/drivers/gpu/drm/imagination/pvr_ccb.c -+++ b/drivers/gpu/drm/imagination/pvr_ccb.c -@@ -135,6 +135,14 @@ pvr_ccb_slot_available_locked(struct pvr_ccb *pvr_ccb, u32 *write_offset) - static void - process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *cmd) - { -+ struct drm_device *drm_dev = from_pvr_device(pvr_dev); -+ -+ if ((cmd->cmd_type & ROGUE_CMD_MAGIC_DWORD_MASK) != ROGUE_CMD_MAGIC_DWORD_SHIFTED) { -+ drm_warn_once(drm_dev, "Received FWCCB command with bad magic value; ignoring (type=0x%08x)\n", -+ cmd->cmd_type); -+ return; -+ } -+ - switch (cmd->cmd_type) { - case ROGUE_FWIF_FWCCB_CMD_REQUEST_GPU_RESTART: - pvr_power_reset(pvr_dev, false); -@@ -150,8 +158,8 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c - break; - - default: -- drm_info(from_pvr_device(pvr_dev), "Received unknown FWCCB command %x\n", -- cmd->cmd_type); -+ drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n", -+ cmd->cmd_type & ~ROGUE_CMD_MAGIC_DWORD_MASK); - break; - } - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch b/SPECS/linux-lts-kmhv2/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch new file mode 100644 index 0000000000..30928dca28 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch @@ -0,0 +1,47 @@ +From 1c4786d466085bd7d5e793bc432f8d9d77048fb9 Mon Sep 17 00:00:00 2001 +From: Brajesh Gupta +Date: Fri, 13 Mar 2026 06:38:25 +0000 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Skip 2nd thread DM + association for non META Firmware + +Only a META firmware can have two threads. + +Signed-off-by: Brajesh Gupta +Reviewed-by: Matt Coster +Link: https://patch.msgid.link/20260313-b4-staging-layout_mars_base-v2-2-9e3c251d278e@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 62a6f98cda4ec75107e96571346349a649fc63d1) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_fw_startstop.c | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c +index 6ae0489f7e2e..e24ed6fc4362 100644 +--- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c ++++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c +@@ -243,12 +243,15 @@ pvr_fw_stop(struct pvr_device *pvr_dev) + pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC, + ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL & + ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK); +- pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, +- ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & +- ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); +- pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, +- ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & +- ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); ++ ++ if (meta_fw) { ++ pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, ++ ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & ++ ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); ++ pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, ++ ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & ++ ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); ++ } + + /* Extra Idle checks. */ + err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_STATUS_MMU, 0, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch b/SPECS/linux-lts-kmhv2/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch new file mode 100644 index 0000000000..74f768a3dd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch @@ -0,0 +1,53 @@ +From 2af0a8e17c8cfcbee59a2a2f6315c394a0342dc5 Mon Sep 17 00:00:00 2001 +From: Alexandru Dadu +Date: Mon, 23 Mar 2026 20:31:28 +0200 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Add missing rogue context + reset reasons + +Update the context reset reason enum with the missing reset reasons in +the 6-11 value gap: + - CDM Mission/safety checksum mismatch; + - TRP checksum mismatch; + - GPU ECC error (corrected, OK); + - GPU ECC error (uncorrected, HWR); + - FW ECC error (corrected, OK); + - FW ECC error (uncorrected, ERR); + +Co-developed-by: Sarah Walker +Signed-off-by: Sarah Walker +Signed-off-by: Alexandru Dadu +Reviewed-by: Matt Coster +Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-1-1a66049a9a65@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit da173557a2b090d7d8c155283ba489a287983ced) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h +index f95acd5a1f8e..869d904e3649 100644 +--- a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h ++++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h +@@ -236,6 +236,18 @@ enum rogue_context_reset_reason { + ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING = 4, + /* Forced reset to ensure scheduling requirements */ + ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH = 5, ++ /* CDM Mission/safety checksum mismatch */ ++ ROGUE_CONTEXT_RESET_REASON_WGP_CHECKSUM = 6, ++ /* TRP checksum mismatch */ ++ ROGUE_CONTEXT_RESET_REASON_TRP_CHECKSUM = 7, ++ /* GPU ECC error (corrected, OK) */ ++ ROGUE_CONTEXT_RESET_REASON_GPU_ECC_OK = 8, ++ /* GPU ECC error (uncorrected, HWR) */ ++ ROGUE_CONTEXT_RESET_REASON_GPU_ECC_HWR = 9, ++ /* FW ECC error (corrected, OK) */ ++ ROGUE_CONTEXT_RESET_REASON_FW_ECC_OK = 10, ++ /* FW ECC error (uncorrected, ERR) */ ++ ROGUE_CONTEXT_RESET_REASON_FW_ECC_ERR = 11, + /* FW Safety watchdog triggered */ + ROGUE_CONTEXT_RESET_REASON_FW_WATCHDOG = 12, + /* FW page fault (no HWR) */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0187-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch b/SPECS/linux-lts-kmhv2/0187-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch deleted file mode 100644 index 46f5bd7d70..0000000000 --- a/SPECS/linux-lts-kmhv2/0187-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 5e86b21fc9e1bab746f921d406840979e1851e0e Mon Sep 17 00:00:00 2001 -From: Matt Coster -Date: Fri, 6 Feb 2026 16:02:13 +0000 -Subject: [PATCH 187/467] UPSTREAM: drm/imagination: Mark - FWCCB_CMD_UPDATE_STATS as known - -Suppress the "unknown type" warning when processing a FWCCB command of -type CMD_UPDATE_STATS which is known but (currently) unused. - -Reviewed-by: Frank Binns -Link: https://patch.msgid.link/20260206-improve-bad-fwccb-cmd-v1-2-831a852ca127@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 4af267ce3441e10198daa52a8cc4b5cb4575d06f) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_ccb.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c -index 1ccd3e3dab2b..da281b5c7055 100644 ---- a/drivers/gpu/drm/imagination/pvr_ccb.c -+++ b/drivers/gpu/drm/imagination/pvr_ccb.c -@@ -157,6 +157,14 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c - pvr_free_list_process_grow_req(pvr_dev, &cmd->cmd_data.cmd_free_list_gs); - break; - -+ case ROGUE_FWIF_FWCCB_CMD_UPDATE_STATS: -+ /* -+ * We currently have no infrastructure for processing these -+ * stats. It may be added in the future, but for now just -+ * suppress the "unknown" warning when receiving this command. -+ */ -+ break; -+ - default: - drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n", - cmd->cmd_type & ~ROGUE_CMD_MAGIC_DWORD_MASK); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch b/SPECS/linux-lts-kmhv2/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch new file mode 100644 index 0000000000..0b560df8fc --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch @@ -0,0 +1,208 @@ +From 3ea351d649da005c14bb7563aff7c5a258116a18 Mon Sep 17 00:00:00 2001 +From: Alexandru Dadu +Date: Mon, 23 Mar 2026 20:31:30 +0200 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Implement handling of context + reset notification + +The firmware will send the context reset notification message as +part of handling hardware recovery (HWR) events deecoding the message +and printing via drm_info(). This eliminates the "Unknown FWCCB command" +message that was previously printed. + +Co-developed-by: Sarah Walker +Signed-off-by: Sarah Walker +Signed-off-by: Alexandru Dadu +Reviewed-by: Matt Coster +Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-3-1a66049a9a65@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit d994acc526c70d40ec9029cfe03d08ee411083c5) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/Makefile | 1 + + drivers/gpu/drm/imagination/pvr_ccb.c | 5 ++ + drivers/gpu/drm/imagination/pvr_dump.c | 113 +++++++++++++++++++++++++ + drivers/gpu/drm/imagination/pvr_dump.h | 17 ++++ + 4 files changed, 136 insertions(+) + create mode 100644 drivers/gpu/drm/imagination/pvr_dump.c + create mode 100644 drivers/gpu/drm/imagination/pvr_dump.h + +diff --git a/drivers/gpu/drm/imagination/Makefile b/drivers/gpu/drm/imagination/Makefile +index 7cca66f00a38..d94a8f592c74 100644 +--- a/drivers/gpu/drm/imagination/Makefile ++++ b/drivers/gpu/drm/imagination/Makefile +@@ -8,6 +8,7 @@ powervr-y := \ + pvr_device.o \ + pvr_device_info.o \ + pvr_drv.o \ ++ pvr_dump.o \ + pvr_free_list.o \ + pvr_fw.o \ + pvr_fw_meta.o \ +diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c +index da281b5c7055..8e8e7c1e0b03 100644 +--- a/drivers/gpu/drm/imagination/pvr_ccb.c ++++ b/drivers/gpu/drm/imagination/pvr_ccb.c +@@ -4,6 +4,7 @@ + #include "pvr_ccb.h" + #include "pvr_device.h" + #include "pvr_drv.h" ++#include "pvr_dump.h" + #include "pvr_free_list.h" + #include "pvr_fw.h" + #include "pvr_gem.h" +@@ -164,6 +165,10 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c + * suppress the "unknown" warning when receiving this command. + */ + break; ++ case ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_NOTIFICATION: ++ pvr_dump_context_reset_notification(pvr_dev, ++ &cmd->cmd_data.cmd_context_reset_notification); ++ break; + + default: + drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n", +diff --git a/drivers/gpu/drm/imagination/pvr_dump.c b/drivers/gpu/drm/imagination/pvr_dump.c +new file mode 100644 +index 000000000000..52e95fce2817 +--- /dev/null ++++ b/drivers/gpu/drm/imagination/pvr_dump.c +@@ -0,0 +1,113 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* Copyright (c) 2026 Imagination Technologies Ltd. */ ++ ++#include "pvr_device.h" ++#include "pvr_dump.h" ++#include "pvr_rogue_fwif.h" ++ ++#include ++#include ++ ++static const char * ++get_reset_reason_desc(enum rogue_context_reset_reason reason) ++{ ++ switch (reason) { ++ case ROGUE_CONTEXT_RESET_REASON_NONE: ++ return "None"; ++ case ROGUE_CONTEXT_RESET_REASON_GUILTY_LOCKUP: ++ return "Guilty lockup"; ++ case ROGUE_CONTEXT_RESET_REASON_INNOCENT_LOCKUP: ++ return "Innocent lockup"; ++ case ROGUE_CONTEXT_RESET_REASON_GUILTY_OVERRUNING: ++ return "Guilty overrunning"; ++ case ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING: ++ return "Innocent overrunning"; ++ case ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH: ++ return "Hard context switch"; ++ case ROGUE_CONTEXT_RESET_REASON_WGP_CHECKSUM: ++ return "CDM Mission/safety checksum mismatch"; ++ case ROGUE_CONTEXT_RESET_REASON_TRP_CHECKSUM: ++ return "TRP checksum mismatch"; ++ case ROGUE_CONTEXT_RESET_REASON_GPU_ECC_OK: ++ return "GPU ECC error (corrected, OK)"; ++ case ROGUE_CONTEXT_RESET_REASON_GPU_ECC_HWR: ++ return "GPU ECC error (uncorrected, HWR)"; ++ case ROGUE_CONTEXT_RESET_REASON_FW_ECC_OK: ++ return "Firmware ECC error (corrected, OK)"; ++ case ROGUE_CONTEXT_RESET_REASON_FW_ECC_ERR: ++ return "Firmware ECC error (uncorrected, ERR)"; ++ case ROGUE_CONTEXT_RESET_REASON_FW_WATCHDOG: ++ return "Firmware watchdog"; ++ case ROGUE_CONTEXT_RESET_REASON_FW_PAGEFAULT: ++ return "Firmware pagefault"; ++ case ROGUE_CONTEXT_RESET_REASON_FW_EXEC_ERR: ++ return "Firmware execution error"; ++ case ROGUE_CONTEXT_RESET_REASON_HOST_WDG_FW_ERR: ++ return "Host watchdog"; ++ case ROGUE_CONTEXT_GEOM_OOM_DISABLED: ++ return "Geometry OOM disabled"; ++ ++ default: ++ return "Unknown"; ++ } ++} ++ ++static const char * ++get_dm_name(u32 dm) ++{ ++ switch (dm) { ++ case PVR_FWIF_DM_GP: ++ return "General purpose"; ++ /* PVR_FWIF_DM_TDM has the same index, but is discriminated by a device feature */ ++ case PVR_FWIF_DM_2D: ++ return "2D or TDM"; ++ case PVR_FWIF_DM_GEOM: ++ return "Geometry"; ++ case PVR_FWIF_DM_FRAG: ++ return "Fragment"; ++ case PVR_FWIF_DM_CDM: ++ return "Compute"; ++ case PVR_FWIF_DM_RAY: ++ return "Raytracing"; ++ case PVR_FWIF_DM_GEOM2: ++ return "Geometry 2"; ++ case PVR_FWIF_DM_GEOM3: ++ return "Geometry 3"; ++ case PVR_FWIF_DM_GEOM4: ++ return "Geometry 4"; ++ ++ default: ++ return "Unknown"; ++ } ++} ++ ++/** ++ * pvr_dump_context_reset_notification() - Handle context reset notification from FW ++ * @pvr_dev: Device pointer. ++ * @data: Data provided by FW. ++ * ++ * This will decode the data structure provided by FW and print the results via drm_info(). ++ */ ++void ++pvr_dump_context_reset_notification(struct pvr_device *pvr_dev, ++ struct rogue_fwif_fwccb_cmd_context_reset_data *data) ++{ ++ struct drm_device *drm_dev = from_pvr_device(pvr_dev); ++ ++ if (data->flags & ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_FLAG_ALL_CTXS) { ++ drm_info(drm_dev, "Received context reset notification for all contexts\n"); ++ } else { ++ drm_info(drm_dev, "Received context reset notification on context %u\n", ++ data->server_common_context_id); ++ } ++ ++ drm_info(drm_dev, " Reset reason=%u (%s)\n", data->reset_reason, ++ get_reset_reason_desc((enum rogue_context_reset_reason)data->reset_reason)); ++ drm_info(drm_dev, " Data Master=%u (%s)\n", data->dm, get_dm_name(data->dm)); ++ drm_info(drm_dev, " Job ref=%u\n", data->reset_job_ref); ++ ++ if (data->flags & ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_FLAG_PF) { ++ drm_info(drm_dev, " Page fault occurred, fault address=%llx\n", ++ data->fault_address); ++ } ++} +diff --git a/drivers/gpu/drm/imagination/pvr_dump.h b/drivers/gpu/drm/imagination/pvr_dump.h +new file mode 100644 +index 000000000000..3c0728c05596 +--- /dev/null ++++ b/drivers/gpu/drm/imagination/pvr_dump.h +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR MIT */ ++/* Copyright (c) 2026 Imagination Technologies Ltd. */ ++ ++#ifndef PVR_DUMP_H ++#define PVR_DUMP_H ++ ++/* Forward declaration from pvr_device.h. */ ++struct pvr_device; ++ ++/* Forward declaration from pvr_rogue_fwif.h. */ ++struct rogue_fwif_fwccb_cmd_context_reset_data; ++ ++void ++pvr_dump_context_reset_notification(struct pvr_device *pvr_dev, ++ struct rogue_fwif_fwccb_cmd_context_reset_data *data); ++ ++#endif /* PVR_DUMP_H */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0188-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch b/SPECS/linux-lts-kmhv2/0188-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch deleted file mode 100644 index c50be1defc..0000000000 --- a/SPECS/linux-lts-kmhv2/0188-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch +++ /dev/null @@ -1,144 +0,0 @@ -From c27b56fa68e0dc9f68c93f5024501db480e2a75f Mon Sep 17 00:00:00 2001 -From: Brajesh Gupta -Date: Fri, 13 Mar 2026 06:38:24 +0000 -Subject: [PATCH 188/467] UPSTREAM: drm/imagination: Improve firmware power off - for layout_mars config - -In layout_mars HW config, Firmware MCU moved from Sidekick to new Mars -domain so Firmware takes care of powering down Sidekick/Jones and SLC. -Skip checks for those from kernel and check idle bits for Firmware MCU -and system arbiter excluding SOCIF. - -Signed-off-by: Brajesh Gupta -Reviewed-by: Matt Coster -Link: https://patch.msgid.link/20260313-b4-staging-layout_mars_base-v2-1-9e3c251d278e@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 51e39ceeca7e85a3b9ca533502a404eb5f3b0f02) -Signed-off-by: Han Gao ---- - .../gpu/drm/imagination/pvr_fw_startstop.c | 85 +++++++++++++------ - 1 file changed, 57 insertions(+), 28 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c -index dcbb9903e791..6ae0489f7e2e 100644 ---- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c -+++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c -@@ -209,18 +209,32 @@ pvr_fw_stop(struct pvr_device *pvr_dev) - ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN | - ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN); - bool skip_garten_idle = false; -+ u64 layout_mars_value = 0; -+ bool layout_mars = false; -+ bool meta_fw = pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META; - u32 reg_value; - int err; - -+ if (PVR_FEATURE_VALUE(pvr_dev, layout_mars, &layout_mars_value) == 0) -+ layout_mars = layout_mars_value > 0; -+ - /* -- * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. -- * For cores with the LAYOUT_MARS feature, SIDEKICK would have been -+ * For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have been - * powered down by the FW. - */ -- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, -- sidekick_idle_mask, POLL_TIMEOUT_USEC); -- if (err) -- return err; -+ if (!layout_mars) { -+ /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. */ -+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, -+ sidekick_idle_mask, POLL_TIMEOUT_USEC); -+ if (err) -+ return err; -+ -+ /* Wait for SLC to signal IDLE. */ -+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, ROGUE_CR_SLC_IDLE_MASKFULL, -+ ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); -+ if (err) -+ return err; -+ } - - /* Unset MTS DM association with threads. */ - pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC, -@@ -270,27 +284,25 @@ pvr_fw_stop(struct pvr_device *pvr_dev) - return err; - - /* -- * Wait for SLC to signal IDLE. -- * For cores with the LAYOUT_MARS feature, SLC would have been powered -- * down by the FW. -+ * For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have been -+ * powered down by the FW. - */ -- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, -- ROGUE_CR_SLC_IDLE_MASKFULL, -- ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); -- if (err) -- return err; -+ if (!layout_mars) { -+ /* Wait for SLC to signal IDLE. */ -+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, -+ ROGUE_CR_SLC_IDLE_MASKFULL, -+ ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); -+ if (err) -+ return err; - -- /* -- * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. -- * For cores with the LAYOUT_MARS feature, SIDEKICK would have been powered -- * down by the FW. -- */ -- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, -- sidekick_idle_mask, POLL_TIMEOUT_USEC); -- if (err) -- return err; -+ /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. */ -+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, -+ sidekick_idle_mask, POLL_TIMEOUT_USEC); -+ if (err) -+ return err; -+ } - -- if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META) { -+ if (meta_fw) { - err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, ®_value); - if (err) - return err; -@@ -304,11 +316,28 @@ pvr_fw_stop(struct pvr_device *pvr_dev) - skip_garten_idle = true; - } - -- if (!skip_garten_idle) { -- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, -- ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, -- ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, -+ if (meta_fw || !layout_mars) { -+ if (!skip_garten_idle) { -+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, -+ ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, -+ ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, -+ POLL_TIMEOUT_USEC); -+ if (err) -+ return err; -+ } -+ } else { -+ /* -+ * As FW core has been moved from SIDEKICK to the new MARS domain, checking -+ * idle bits for CPU & System Arbiter excluding SOCIF which will never be -+ * idle if Host polling on this register -+ */ -+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_MARS_IDLE, -+ ROGUE_CR_MARS_IDLE_CPU_EN | -+ ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN, -+ ROGUE_CR_MARS_IDLE_CPU_EN | -+ ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN, - POLL_TIMEOUT_USEC); -+ - if (err) - return err; - } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0189-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch b/SPECS/linux-lts-kmhv2/0189-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch deleted file mode 100644 index a38db47b95..0000000000 --- a/SPECS/linux-lts-kmhv2/0189-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 5fa9c63710bdd821c67cb83870bd773ad29fb978 Mon Sep 17 00:00:00 2001 -From: Brajesh Gupta -Date: Fri, 13 Mar 2026 06:38:25 +0000 -Subject: [PATCH 189/467] UPSTREAM: drm/imagination: Skip 2nd thread DM - association for non META Firmware - -Only a META firmware can have two threads. - -Signed-off-by: Brajesh Gupta -Reviewed-by: Matt Coster -Link: https://patch.msgid.link/20260313-b4-staging-layout_mars_base-v2-2-9e3c251d278e@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 62a6f98cda4ec75107e96571346349a649fc63d1) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_fw_startstop.c | 15 +++++++++------ - 1 file changed, 9 insertions(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c -index 6ae0489f7e2e..e24ed6fc4362 100644 ---- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c -+++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c -@@ -243,12 +243,15 @@ pvr_fw_stop(struct pvr_device *pvr_dev) - pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC, - ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL & - ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK); -- pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, -- ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & -- ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); -- pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, -- ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & -- ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); -+ -+ if (meta_fw) { -+ pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, -+ ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & -+ ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); -+ pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, -+ ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & -+ ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); -+ } - - /* Extra Idle checks. */ - err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_STATUS_MMU, 0, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch b/SPECS/linux-lts-kmhv2/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch new file mode 100644 index 0000000000..f7d478ada1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch @@ -0,0 +1,37 @@ +From e88d780551651b13977fcb9a0fc500f0edc4ec8d Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:15 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: vendor-prefixes: add verisilicon + +VeriSilicon is a Silicon IP vendor, which is the current owner of +Vivante series video-related IPs and Hantro series video codec IPs. + +Add a vendor prefix for this company. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Acked-by: Rob Herring (Arm) +Signed-off-by: Thomas Zimmermann +Link: https://patch.msgid.link/20260129023922.1527729-2-zhengxingda@iscas.ac.cn +(cherry picked from commit c131d78840d7487e41c3afdc52bb74fd3f8861ef) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml +index 647746e6f75f..d03f700d178e 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml ++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml +@@ -1723,6 +1723,8 @@ patternProperties: + description: Variscite Ltd. + "^vdl,.*": + description: Van der Laan b.v. ++ "^verisilicon,.*": ++ description: VeriSilicon Microelectronics (Shanghai) Co., Ltd. + "^vertexcom,.*": + description: Vertexcom Technologies, Inc. + "^via,.*": +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0190-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch b/SPECS/linux-lts-kmhv2/0190-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch deleted file mode 100644 index 47548d9611..0000000000 --- a/SPECS/linux-lts-kmhv2/0190-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch +++ /dev/null @@ -1,53 +0,0 @@ -From abb8bc1c87a792d8e9fb2ec18bace8773ff287fa Mon Sep 17 00:00:00 2001 -From: Alexandru Dadu -Date: Mon, 23 Mar 2026 20:31:28 +0200 -Subject: [PATCH 190/467] UPSTREAM: drm/imagination: Add missing rogue context - reset reasons - -Update the context reset reason enum with the missing reset reasons in -the 6-11 value gap: - - CDM Mission/safety checksum mismatch; - - TRP checksum mismatch; - - GPU ECC error (corrected, OK); - - GPU ECC error (uncorrected, HWR); - - FW ECC error (corrected, OK); - - FW ECC error (uncorrected, ERR); - -Co-developed-by: Sarah Walker -Signed-off-by: Sarah Walker -Signed-off-by: Alexandru Dadu -Reviewed-by: Matt Coster -Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-1-1a66049a9a65@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit da173557a2b090d7d8c155283ba489a287983ced) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -index f95acd5a1f8e..869d904e3649 100644 ---- a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -@@ -236,6 +236,18 @@ enum rogue_context_reset_reason { - ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING = 4, - /* Forced reset to ensure scheduling requirements */ - ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH = 5, -+ /* CDM Mission/safety checksum mismatch */ -+ ROGUE_CONTEXT_RESET_REASON_WGP_CHECKSUM = 6, -+ /* TRP checksum mismatch */ -+ ROGUE_CONTEXT_RESET_REASON_TRP_CHECKSUM = 7, -+ /* GPU ECC error (corrected, OK) */ -+ ROGUE_CONTEXT_RESET_REASON_GPU_ECC_OK = 8, -+ /* GPU ECC error (uncorrected, HWR) */ -+ ROGUE_CONTEXT_RESET_REASON_GPU_ECC_HWR = 9, -+ /* FW ECC error (corrected, OK) */ -+ ROGUE_CONTEXT_RESET_REASON_FW_ECC_OK = 10, -+ /* FW ECC error (uncorrected, ERR) */ -+ ROGUE_CONTEXT_RESET_REASON_FW_ECC_ERR = 11, - /* FW Safety watchdog triggered */ - ROGUE_CONTEXT_RESET_REASON_FW_WATCHDOG = 12, - /* FW page fault (no HWR) */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch b/SPECS/linux-lts-kmhv2/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch new file mode 100644 index 0000000000..3ab06308e6 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch @@ -0,0 +1,157 @@ +From 0097108abfd8e7e0526f283feef46f9ff85d3019 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:16 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: display: add verisilicon,dc + +Verisilicon has a series of display controllers prefixed with DC and +with self-identification facility like their GC series GPUs. + +Add a device tree binding for it. + +Depends on the specific DC model, it can have either one or two display +outputs, and each display output could be set to DPI signal or "DP" +signal (which seems to be some plain parallel bus to HDMI controllers). + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Thomas Zimmermann +Link: https://patch.msgid.link/20260129023922.1527729-3-zhengxingda@iscas.ac.cn +(cherry picked from commit 5f6965fa1e2ec8ac69e1d448d343a528dc60cdfb) +Signed-off-by: Han Gao +--- + .../bindings/display/verisilicon,dc.yaml | 122 ++++++++++++++++++ + 1 file changed, 122 insertions(+) + create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml + +diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml +new file mode 100644 +index 000000000000..9dc35ab973f2 +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml +@@ -0,0 +1,122 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Verisilicon DC-series display controllers ++ ++maintainers: ++ - Icenowy Zheng ++ ++properties: ++ $nodename: ++ pattern: "^display@[0-9a-f]+$" ++ ++ compatible: ++ items: ++ - enum: ++ - thead,th1520-dc8200 ++ - const: verisilicon,dc # DC IPs have discoverable ID/revision registers ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: DC Core clock ++ - description: DMA AXI bus clock ++ - description: Configuration AHB bus clock ++ - description: Pixel clock of output 0 ++ - description: Pixel clock of output 1 ++ ++ clock-names: ++ items: ++ - const: core ++ - const: axi ++ - const: ahb ++ - const: pix0 ++ - const: pix1 ++ ++ resets: ++ items: ++ - description: DC Core reset ++ - description: DMA AXI bus reset ++ - description: Configuration AHB bus reset ++ ++ reset-names: ++ items: ++ - const: core ++ - const: axi ++ - const: ahb ++ ++ ports: ++ $ref: /schemas/graph.yaml#/properties/ports ++ ++ properties: ++ port@0: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: The first output channel , endpoint 0 should be ++ used for DPI format output and endpoint 1 should be used ++ for DP format output. ++ ++ port@1: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: The second output channel if the DC variant ++ supports. Follow the same endpoint addressing rule with ++ the first port. ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ - ports ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ display@ffef600000 { ++ compatible = "thead,th1520-dc8200", "verisilicon,dc"; ++ reg = <0xff 0xef600000 0x0 0x100000>; ++ interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_vo CLK_DPU_CCLK>, ++ <&clk_vo CLK_DPU_ACLK>, ++ <&clk_vo CLK_DPU_HCLK>, ++ <&clk_vo CLK_DPU_PIXELCLK0>, ++ <&clk_vo CLK_DPU_PIXELCLK1>; ++ clock-names = "core", "axi", "ahb", "pix0", "pix1"; ++ resets = <&rst TH1520_RESET_ID_DPU_CORE>, ++ <&rst TH1520_RESET_ID_DPU_AXI>, ++ <&rst TH1520_RESET_ID_DPU_AHB>; ++ reset-names = "core", "axi", "ahb"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dpu_out_dp1: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&hdmi_in>; ++ }; ++ }; ++ }; ++ }; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0191-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch b/SPECS/linux-lts-kmhv2/0191-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch deleted file mode 100644 index 239f0e4598..0000000000 --- a/SPECS/linux-lts-kmhv2/0191-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch +++ /dev/null @@ -1,208 +0,0 @@ -From 8b9e78b54cb9659d9121ea4bf1e3368763df3af7 Mon Sep 17 00:00:00 2001 -From: Alexandru Dadu -Date: Mon, 23 Mar 2026 20:31:30 +0200 -Subject: [PATCH 191/467] UPSTREAM: drm/imagination: Implement handling of - context reset notification - -The firmware will send the context reset notification message as -part of handling hardware recovery (HWR) events deecoding the message -and printing via drm_info(). This eliminates the "Unknown FWCCB command" -message that was previously printed. - -Co-developed-by: Sarah Walker -Signed-off-by: Sarah Walker -Signed-off-by: Alexandru Dadu -Reviewed-by: Matt Coster -Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-3-1a66049a9a65@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit d994acc526c70d40ec9029cfe03d08ee411083c5) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/Makefile | 1 + - drivers/gpu/drm/imagination/pvr_ccb.c | 5 ++ - drivers/gpu/drm/imagination/pvr_dump.c | 113 +++++++++++++++++++++++++ - drivers/gpu/drm/imagination/pvr_dump.h | 17 ++++ - 4 files changed, 136 insertions(+) - create mode 100644 drivers/gpu/drm/imagination/pvr_dump.c - create mode 100644 drivers/gpu/drm/imagination/pvr_dump.h - -diff --git a/drivers/gpu/drm/imagination/Makefile b/drivers/gpu/drm/imagination/Makefile -index 7cca66f00a38..d94a8f592c74 100644 ---- a/drivers/gpu/drm/imagination/Makefile -+++ b/drivers/gpu/drm/imagination/Makefile -@@ -8,6 +8,7 @@ powervr-y := \ - pvr_device.o \ - pvr_device_info.o \ - pvr_drv.o \ -+ pvr_dump.o \ - pvr_free_list.o \ - pvr_fw.o \ - pvr_fw_meta.o \ -diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c -index da281b5c7055..8e8e7c1e0b03 100644 ---- a/drivers/gpu/drm/imagination/pvr_ccb.c -+++ b/drivers/gpu/drm/imagination/pvr_ccb.c -@@ -4,6 +4,7 @@ - #include "pvr_ccb.h" - #include "pvr_device.h" - #include "pvr_drv.h" -+#include "pvr_dump.h" - #include "pvr_free_list.h" - #include "pvr_fw.h" - #include "pvr_gem.h" -@@ -164,6 +165,10 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c - * suppress the "unknown" warning when receiving this command. - */ - break; -+ case ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_NOTIFICATION: -+ pvr_dump_context_reset_notification(pvr_dev, -+ &cmd->cmd_data.cmd_context_reset_notification); -+ break; - - default: - drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n", -diff --git a/drivers/gpu/drm/imagination/pvr_dump.c b/drivers/gpu/drm/imagination/pvr_dump.c -new file mode 100644 -index 000000000000..52e95fce2817 ---- /dev/null -+++ b/drivers/gpu/drm/imagination/pvr_dump.c -@@ -0,0 +1,113 @@ -+// SPDX-License-Identifier: GPL-2.0 OR MIT -+/* Copyright (c) 2026 Imagination Technologies Ltd. */ -+ -+#include "pvr_device.h" -+#include "pvr_dump.h" -+#include "pvr_rogue_fwif.h" -+ -+#include -+#include -+ -+static const char * -+get_reset_reason_desc(enum rogue_context_reset_reason reason) -+{ -+ switch (reason) { -+ case ROGUE_CONTEXT_RESET_REASON_NONE: -+ return "None"; -+ case ROGUE_CONTEXT_RESET_REASON_GUILTY_LOCKUP: -+ return "Guilty lockup"; -+ case ROGUE_CONTEXT_RESET_REASON_INNOCENT_LOCKUP: -+ return "Innocent lockup"; -+ case ROGUE_CONTEXT_RESET_REASON_GUILTY_OVERRUNING: -+ return "Guilty overrunning"; -+ case ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING: -+ return "Innocent overrunning"; -+ case ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH: -+ return "Hard context switch"; -+ case ROGUE_CONTEXT_RESET_REASON_WGP_CHECKSUM: -+ return "CDM Mission/safety checksum mismatch"; -+ case ROGUE_CONTEXT_RESET_REASON_TRP_CHECKSUM: -+ return "TRP checksum mismatch"; -+ case ROGUE_CONTEXT_RESET_REASON_GPU_ECC_OK: -+ return "GPU ECC error (corrected, OK)"; -+ case ROGUE_CONTEXT_RESET_REASON_GPU_ECC_HWR: -+ return "GPU ECC error (uncorrected, HWR)"; -+ case ROGUE_CONTEXT_RESET_REASON_FW_ECC_OK: -+ return "Firmware ECC error (corrected, OK)"; -+ case ROGUE_CONTEXT_RESET_REASON_FW_ECC_ERR: -+ return "Firmware ECC error (uncorrected, ERR)"; -+ case ROGUE_CONTEXT_RESET_REASON_FW_WATCHDOG: -+ return "Firmware watchdog"; -+ case ROGUE_CONTEXT_RESET_REASON_FW_PAGEFAULT: -+ return "Firmware pagefault"; -+ case ROGUE_CONTEXT_RESET_REASON_FW_EXEC_ERR: -+ return "Firmware execution error"; -+ case ROGUE_CONTEXT_RESET_REASON_HOST_WDG_FW_ERR: -+ return "Host watchdog"; -+ case ROGUE_CONTEXT_GEOM_OOM_DISABLED: -+ return "Geometry OOM disabled"; -+ -+ default: -+ return "Unknown"; -+ } -+} -+ -+static const char * -+get_dm_name(u32 dm) -+{ -+ switch (dm) { -+ case PVR_FWIF_DM_GP: -+ return "General purpose"; -+ /* PVR_FWIF_DM_TDM has the same index, but is discriminated by a device feature */ -+ case PVR_FWIF_DM_2D: -+ return "2D or TDM"; -+ case PVR_FWIF_DM_GEOM: -+ return "Geometry"; -+ case PVR_FWIF_DM_FRAG: -+ return "Fragment"; -+ case PVR_FWIF_DM_CDM: -+ return "Compute"; -+ case PVR_FWIF_DM_RAY: -+ return "Raytracing"; -+ case PVR_FWIF_DM_GEOM2: -+ return "Geometry 2"; -+ case PVR_FWIF_DM_GEOM3: -+ return "Geometry 3"; -+ case PVR_FWIF_DM_GEOM4: -+ return "Geometry 4"; -+ -+ default: -+ return "Unknown"; -+ } -+} -+ -+/** -+ * pvr_dump_context_reset_notification() - Handle context reset notification from FW -+ * @pvr_dev: Device pointer. -+ * @data: Data provided by FW. -+ * -+ * This will decode the data structure provided by FW and print the results via drm_info(). -+ */ -+void -+pvr_dump_context_reset_notification(struct pvr_device *pvr_dev, -+ struct rogue_fwif_fwccb_cmd_context_reset_data *data) -+{ -+ struct drm_device *drm_dev = from_pvr_device(pvr_dev); -+ -+ if (data->flags & ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_FLAG_ALL_CTXS) { -+ drm_info(drm_dev, "Received context reset notification for all contexts\n"); -+ } else { -+ drm_info(drm_dev, "Received context reset notification on context %u\n", -+ data->server_common_context_id); -+ } -+ -+ drm_info(drm_dev, " Reset reason=%u (%s)\n", data->reset_reason, -+ get_reset_reason_desc((enum rogue_context_reset_reason)data->reset_reason)); -+ drm_info(drm_dev, " Data Master=%u (%s)\n", data->dm, get_dm_name(data->dm)); -+ drm_info(drm_dev, " Job ref=%u\n", data->reset_job_ref); -+ -+ if (data->flags & ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_FLAG_PF) { -+ drm_info(drm_dev, " Page fault occurred, fault address=%llx\n", -+ data->fault_address); -+ } -+} -diff --git a/drivers/gpu/drm/imagination/pvr_dump.h b/drivers/gpu/drm/imagination/pvr_dump.h -new file mode 100644 -index 000000000000..3c0728c05596 ---- /dev/null -+++ b/drivers/gpu/drm/imagination/pvr_dump.h -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -+/* Copyright (c) 2026 Imagination Technologies Ltd. */ -+ -+#ifndef PVR_DUMP_H -+#define PVR_DUMP_H -+ -+/* Forward declaration from pvr_device.h. */ -+struct pvr_device; -+ -+/* Forward declaration from pvr_rogue_fwif.h. */ -+struct rogue_fwif_fwccb_cmd_context_reset_data; -+ -+void -+pvr_dump_context_reset_notification(struct pvr_device *pvr_dev, -+ struct rogue_fwif_fwccb_cmd_context_reset_data *data); -+ -+#endif /* PVR_DUMP_H */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch b/SPECS/linux-lts-kmhv2/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch new file mode 100644 index 0000000000..f6b7875e3a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch @@ -0,0 +1,2082 @@ +From 6b2f35b64e7c0486c46921e2bae819b08dc83a72 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:17 +0800 +Subject: [RUYI PATCH] UPSTREAM: drm: verisilicon: add a driver for Verisilicon + display controllers + +This is a from-scratch driver targeting Verisilicon DC-series display +controllers, which feature self-identification functionality like their +GC-series GPUs. + +Only DC8200 is being supported now, and only the main framebuffer is set +up (as the DRM primary plane). Support for more DC models and more +features is my further targets. + +As the display controller is delivered to SoC vendors as a whole part, +this driver does not use component framework and extra bridges inside a +SoC is expected to be implemented as dedicated bridges (this driver +properly supports bridge chaining). + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Tested-by: Han Gao +Tested-by: Michal Wilczynski +Reviewed-by: Thomas Zimmermann +Signed-off-by: Thomas Zimmermann +Link: https://patch.msgid.link/20260129023922.1527729-4-zhengxingda@iscas.ac.cn +(cherry picked from commit dbf21777caa8b8c88c12f7f036b01208fec0d55a) +Signed-off-by: Han Gao +--- + MAINTAINERS | 7 + + drivers/gpu/drm/Kconfig | 2 + + drivers/gpu/drm/Makefile | 1 + + drivers/gpu/drm/verisilicon/Kconfig | 16 + + drivers/gpu/drm/verisilicon/Makefile | 5 + + drivers/gpu/drm/verisilicon/vs_bridge.c | 371 ++++++++++++++++++ + drivers/gpu/drm/verisilicon/vs_bridge.h | 39 ++ + drivers/gpu/drm/verisilicon/vs_bridge_regs.h | 54 +++ + drivers/gpu/drm/verisilicon/vs_crtc.c | 191 +++++++++ + drivers/gpu/drm/verisilicon/vs_crtc.h | 31 ++ + drivers/gpu/drm/verisilicon/vs_crtc_regs.h | 60 +++ + drivers/gpu/drm/verisilicon/vs_dc.c | 207 ++++++++++ + drivers/gpu/drm/verisilicon/vs_dc.h | 38 ++ + drivers/gpu/drm/verisilicon/vs_dc_top_regs.h | 27 ++ + drivers/gpu/drm/verisilicon/vs_drm.c | 182 +++++++++ + drivers/gpu/drm/verisilicon/vs_drm.h | 28 ++ + drivers/gpu/drm/verisilicon/vs_hwdb.c | 150 +++++++ + drivers/gpu/drm/verisilicon/vs_hwdb.h | 29 ++ + drivers/gpu/drm/verisilicon/vs_plane.c | 124 ++++++ + drivers/gpu/drm/verisilicon/vs_plane.h | 72 ++++ + .../gpu/drm/verisilicon/vs_primary_plane.c | 173 ++++++++ + .../drm/verisilicon/vs_primary_plane_regs.h | 53 +++ + 22 files changed, 1860 insertions(+) + create mode 100644 drivers/gpu/drm/verisilicon/Kconfig + create mode 100644 drivers/gpu/drm/verisilicon/Makefile + create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge_regs.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc_regs.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_dc.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_dc.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_top_regs.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_drm.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_drm.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_hwdb.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_hwdb.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_primary_plane.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h + +diff --git a/MAINTAINERS b/MAINTAINERS +index a615f46a6e8d..b50b6c7a9b52 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -8546,6 +8546,13 @@ F: Documentation/devicetree/bindings/display/brcm,bcm2835-*.yaml + F: drivers/gpu/drm/vc4/ + F: include/uapi/drm/vc4_drm.h + ++DRM DRIVERS FOR VERISILICON DISPLAY CONTROLLER IP ++M: Icenowy Zheng ++L: dri-devel@lists.freedesktop.org ++S: Maintained ++F: Documentation/devicetree/bindings/display/verisilicon,dc.yaml ++F: drivers/gpu/drm/verisilicon/ ++ + DRM DRIVERS FOR VIVANTE GPU IP + M: Lucas Stach + R: Russell King +diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig +index ed85d0ceee3b..a0917595d11c 100644 +--- a/drivers/gpu/drm/Kconfig ++++ b/drivers/gpu/drm/Kconfig +@@ -398,6 +398,8 @@ source "drivers/gpu/drm/imagination/Kconfig" + + source "drivers/gpu/drm/tyr/Kconfig" + ++source "drivers/gpu/drm/verisilicon/Kconfig" ++ + config DRM_HYPERV + tristate "DRM Support for Hyper-V synthetic video device" + depends on DRM && PCI && HYPERV_VMBUS +diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile +index b248e64587ed..90eb61d3a823 100644 +--- a/drivers/gpu/drm/Makefile ++++ b/drivers/gpu/drm/Makefile +@@ -235,6 +235,7 @@ obj-y += solomon/ + obj-$(CONFIG_DRM_SPRD) += sprd/ + obj-$(CONFIG_DRM_LOONGSON) += loongson/ + obj-$(CONFIG_DRM_POWERVR) += imagination/ ++obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon/ + + # Ensure drm headers are self-contained and pass kernel-doc + hdrtest-files := \ +diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisilicon/Kconfig +new file mode 100644 +index 000000000000..7cce86ec8603 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/Kconfig +@@ -0,0 +1,16 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++config DRM_VERISILICON_DC ++ tristate "DRM Support for Verisilicon DC-series display controllers" ++ depends on DRM && COMMON_CLK ++ depends on RISCV || COMPILE_TEST ++ select DRM_BRIDGE_CONNECTOR ++ select DRM_CLIENT_SELECTION ++ select DRM_DISPLAY_HELPER ++ select DRM_GEM_DMA_HELPER ++ select DRM_KMS_HELPER ++ select REGMAP_MMIO ++ select VIDEOMODE_HELPERS ++ help ++ Choose this option if you have a SoC with Verisilicon DC-series ++ display controllers. If M is selected, the module will be called ++ verisilicon-dc. +diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile +new file mode 100644 +index 000000000000..fd8d805fbcde +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/Makefile +@@ -0,0 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o ++ ++obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o +diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.c b/drivers/gpu/drm/verisilicon/vs_bridge.c +new file mode 100644 +index 000000000000..2a0ad00a94d6 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_bridge.c +@@ -0,0 +1,371 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_bridge.h" ++#include "vs_bridge_regs.h" ++#include "vs_crtc.h" ++#include "vs_dc.h" ++ ++static int vs_bridge_attach(struct drm_bridge *bridge, ++ struct drm_encoder *encoder, ++ enum drm_bridge_attach_flags flags) ++{ ++ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); ++ ++ return drm_bridge_attach(encoder, vbridge->next_bridge, ++ bridge, flags); ++} ++ ++struct vsdc_dp_format { ++ u32 linux_fmt; ++ bool is_yuv; ++ u32 vsdc_fmt; ++}; ++ ++static struct vsdc_dp_format vsdc_dp_supported_fmts[] = { ++ /* default to RGB888 */ ++ { MEDIA_BUS_FMT_FIXED, false, VSDC_DISP_DP_CONFIG_FMT_RGB888 }, ++ { MEDIA_BUS_FMT_RGB888_1X24, false, VSDC_DISP_DP_CONFIG_FMT_RGB888 }, ++ { MEDIA_BUS_FMT_RGB565_1X16, false, VSDC_DISP_DP_CONFIG_FMT_RGB565 }, ++ { MEDIA_BUS_FMT_RGB666_1X18, false, VSDC_DISP_DP_CONFIG_FMT_RGB666 }, ++ { MEDIA_BUS_FMT_RGB101010_1X30, ++ false, VSDC_DISP_DP_CONFIG_FMT_RGB101010 }, ++ { MEDIA_BUS_FMT_UYVY8_1X16, true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY8 }, ++ { MEDIA_BUS_FMT_UYVY10_1X20, true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY10 }, ++ { MEDIA_BUS_FMT_YUV8_1X24, true, VSDC_DISP_DP_CONFIG_YUV_FMT_YUV8 }, ++ { MEDIA_BUS_FMT_YUV10_1X30, true, VSDC_DISP_DP_CONFIG_YUV_FMT_YUV10 }, ++ { MEDIA_BUS_FMT_UYYVYY8_0_5X24, ++ true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY8 }, ++ { MEDIA_BUS_FMT_UYYVYY10_0_5X30, ++ true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY10 }, ++}; ++ ++static u32 *vs_bridge_atomic_get_output_bus_fmts_dpi(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state, ++ unsigned int *num_output_fmts) ++{ ++ u32 *output_fmts; ++ ++ *num_output_fmts = 2; ++ ++ output_fmts = kcalloc(*num_output_fmts, sizeof(*output_fmts), ++ GFP_KERNEL); ++ if (!output_fmts) ++ return NULL; ++ ++ /* TODO: support more DPI output formats */ ++ output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; ++ output_fmts[1] = MEDIA_BUS_FMT_FIXED; ++ ++ return output_fmts; ++} ++ ++static u32 *vs_bridge_atomic_get_output_bus_fmts_dp(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state, ++ unsigned int *num_output_fmts) ++{ ++ u32 *output_fmts; ++ unsigned int i; ++ ++ *num_output_fmts = ARRAY_SIZE(vsdc_dp_supported_fmts); ++ ++ output_fmts = kcalloc(*num_output_fmts, sizeof(*output_fmts), ++ GFP_KERNEL); ++ if (!output_fmts) ++ return NULL; ++ ++ for (i = 0; i < *num_output_fmts; i++) ++ output_fmts[i] = vsdc_dp_supported_fmts[i].linux_fmt; ++ ++ return output_fmts; ++} ++ ++static bool vs_bridge_out_dp_fmt_supported(u32 out_fmt) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(vsdc_dp_supported_fmts); i++) ++ if (vsdc_dp_supported_fmts[i].linux_fmt == out_fmt) ++ return true; ++ ++ return false; ++} ++ ++static u32 *vs_bridge_atomic_get_input_bus_fmts_dp(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state, ++ u32 output_fmt, ++ unsigned int *num_input_fmts) ++{ ++ if (!vs_bridge_out_dp_fmt_supported(output_fmt)) { ++ *num_input_fmts = 0; ++ return NULL; ++ } ++ ++ return drm_atomic_helper_bridge_propagate_bus_fmt(bridge, bridge_state, ++ crtc_state, ++ conn_state, ++ output_fmt, ++ num_input_fmts); ++} ++ ++static int vs_bridge_atomic_check_dp(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state) ++{ ++ if (!vs_bridge_out_dp_fmt_supported(bridge_state->output_bus_cfg.format)) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static void vs_bridge_enable_common(struct vs_crtc *crtc, ++ struct drm_bridge_state *br_state) ++{ ++ struct vs_dc *dc = crtc->dc; ++ unsigned int output = crtc->id; ++ ++ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_DAT_POL); ++ regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_DE_POL, ++ br_state->output_bus_cfg.flags & ++ DRM_BUS_FLAG_DE_LOW); ++ regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_CLK_POL, ++ br_state->output_bus_cfg.flags & ++ DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); ++ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_DE_EN | ++ VSDC_DISP_PANEL_CONFIG_DAT_EN | ++ VSDC_DISP_PANEL_CONFIG_CLK_EN); ++ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_RUNNING); ++ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, ++ VSDC_DISP_PANEL_START_MULTI_DISP_SYNC); ++ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START, ++ VSDC_DISP_PANEL_START_RUNNING(output)); ++ ++ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), ++ VSDC_DISP_PANEL_CONFIG_EX_COMMIT); ++} ++ ++static void vs_bridge_atomic_enable_dpi(struct drm_bridge *bridge, ++ struct drm_atomic_state *state) ++{ ++ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); ++ struct drm_bridge_state *br_state = ++ drm_atomic_get_new_bridge_state(state, bridge); ++ struct vs_crtc *crtc = vbridge->crtc; ++ struct vs_dc *dc = crtc->dc; ++ unsigned int output = crtc->id; ++ ++ regmap_clear_bits(dc->regs, VSDC_DISP_DP_CONFIG(output), ++ VSDC_DISP_DP_CONFIG_DP_EN); ++ regmap_write(dc->regs, VSDC_DISP_DPI_CONFIG(output), ++ VSDC_DISP_DPI_CONFIG_FMT_RGB888); ++ ++ vs_bridge_enable_common(crtc, br_state); ++} ++ ++static void vs_bridge_atomic_enable_dp(struct drm_bridge *bridge, ++ struct drm_atomic_state *state) ++{ ++ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); ++ struct drm_bridge_state *br_state = ++ drm_atomic_get_new_bridge_state(state, bridge); ++ struct vs_crtc *crtc = vbridge->crtc; ++ struct vs_dc *dc = crtc->dc; ++ unsigned int output = crtc->id; ++ u32 dp_fmt; ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(vsdc_dp_supported_fmts); i++) { ++ if (vsdc_dp_supported_fmts[i].linux_fmt == ++ br_state->output_bus_cfg.format) ++ break; ++ } ++ if (WARN_ON_ONCE(i == ARRAY_SIZE(vsdc_dp_supported_fmts))) ++ return; ++ dp_fmt = vsdc_dp_supported_fmts[i].vsdc_fmt; ++ dp_fmt |= VSDC_DISP_DP_CONFIG_DP_EN; ++ regmap_write(dc->regs, VSDC_DISP_DP_CONFIG(output), dp_fmt); ++ regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_YUV, ++ vsdc_dp_supported_fmts[i].is_yuv); ++ ++ vs_bridge_enable_common(crtc, br_state); ++} ++ ++static void vs_bridge_atomic_disable(struct drm_bridge *bridge, ++ struct drm_atomic_state *state) ++{ ++ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); ++ struct vs_crtc *crtc = vbridge->crtc; ++ struct vs_dc *dc = crtc->dc; ++ unsigned int output = crtc->id; ++ ++ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, ++ VSDC_DISP_PANEL_START_MULTI_DISP_SYNC | ++ VSDC_DISP_PANEL_START_RUNNING(output)); ++ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_RUNNING); ++ ++ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), ++ VSDC_DISP_PANEL_CONFIG_EX_COMMIT); ++} ++ ++static const struct drm_bridge_funcs vs_dpi_bridge_funcs = { ++ .attach = vs_bridge_attach, ++ .atomic_enable = vs_bridge_atomic_enable_dpi, ++ .atomic_disable = vs_bridge_atomic_disable, ++ .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt, ++ .atomic_get_output_bus_fmts = vs_bridge_atomic_get_output_bus_fmts_dpi, ++ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, ++ .atomic_reset = drm_atomic_helper_bridge_reset, ++}; ++ ++static const struct drm_bridge_funcs vs_dp_bridge_funcs = { ++ .attach = vs_bridge_attach, ++ .atomic_enable = vs_bridge_atomic_enable_dp, ++ .atomic_disable = vs_bridge_atomic_disable, ++ .atomic_check = vs_bridge_atomic_check_dp, ++ .atomic_get_input_bus_fmts = vs_bridge_atomic_get_input_bus_fmts_dp, ++ .atomic_get_output_bus_fmts = vs_bridge_atomic_get_output_bus_fmts_dp, ++ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, ++ .atomic_reset = drm_atomic_helper_bridge_reset, ++}; ++ ++static int vs_bridge_detect_output_interface(struct device_node *of_node, ++ unsigned int output) ++{ ++ int ret; ++ struct device_node *remote; ++ ++ remote = of_graph_get_remote_node(of_node, output, ++ VSDC_OUTPUT_INTERFACE_DPI); ++ if (remote) { ++ ret = VSDC_OUTPUT_INTERFACE_DPI; ++ } else { ++ remote = of_graph_get_remote_node(of_node, output, ++ VSDC_OUTPUT_INTERFACE_DP); ++ if (remote) ++ ret = VSDC_OUTPUT_INTERFACE_DP; ++ else ++ ret = -ENODEV; ++ } ++ ++ if (remote) ++ of_node_put(remote); ++ ++ return ret; ++} ++ ++struct vs_bridge *vs_bridge_init(struct drm_device *drm_dev, ++ struct vs_crtc *crtc) ++{ ++ unsigned int output = crtc->id; ++ struct vs_bridge *bridge; ++ struct drm_bridge *next; ++ enum vs_bridge_output_interface intf; ++ const struct drm_bridge_funcs *bridge_funcs; ++ int ret, enctype; ++ ++ intf = vs_bridge_detect_output_interface(drm_dev->dev->of_node, ++ output); ++ if (intf == -ENODEV) { ++ drm_dbg(drm_dev, "Skipping output %u\n", output); ++ return NULL; ++ } ++ ++ next = devm_drm_of_get_bridge(drm_dev->dev, drm_dev->dev->of_node, ++ output, intf); ++ if (IS_ERR(next)) { ++ ret = PTR_ERR(next); ++ if (ret != -EPROBE_DEFER) ++ drm_err(drm_dev, ++ "Cannot get downstream bridge of output %u\n", ++ output); ++ return ERR_PTR(ret); ++ } ++ ++ if (intf == VSDC_OUTPUT_INTERFACE_DPI) ++ bridge_funcs = &vs_dpi_bridge_funcs; ++ else ++ bridge_funcs = &vs_dp_bridge_funcs; ++ ++ bridge = devm_drm_bridge_alloc(drm_dev->dev, struct vs_bridge, base, ++ bridge_funcs); ++ if (IS_ERR(bridge)) ++ return ERR_PTR(PTR_ERR(bridge)); ++ ++ bridge->crtc = crtc; ++ bridge->intf = intf; ++ bridge->next_bridge = next; ++ ++ if (intf == VSDC_OUTPUT_INTERFACE_DPI) ++ enctype = DRM_MODE_ENCODER_DPI; ++ else ++ enctype = DRM_MODE_ENCODER_NONE; ++ ++ bridge->enc = drmm_plain_encoder_alloc(drm_dev, NULL, enctype, NULL); ++ if (IS_ERR(bridge->enc)) { ++ drm_err(drm_dev, ++ "Cannot initialize encoder for output %u\n", output); ++ ret = PTR_ERR(bridge->enc); ++ return ERR_PTR(ret); ++ } ++ ++ bridge->enc->possible_crtcs = drm_crtc_mask(&crtc->base); ++ ++ ret = devm_drm_bridge_add(drm_dev->dev, &bridge->base); ++ if (ret) { ++ drm_err(drm_dev, ++ "Cannot add bridge for output %u\n", output); ++ return ERR_PTR(ret); ++ } ++ ++ ret = drm_bridge_attach(bridge->enc, &bridge->base, NULL, ++ DRM_BRIDGE_ATTACH_NO_CONNECTOR); ++ if (ret) { ++ drm_err(drm_dev, ++ "Cannot attach bridge for output %u\n", output); ++ return ERR_PTR(ret); ++ } ++ ++ bridge->conn = drm_bridge_connector_init(drm_dev, bridge->enc); ++ if (IS_ERR(bridge->conn)) { ++ drm_err(drm_dev, ++ "Cannot create connector for output %u\n", output); ++ ret = PTR_ERR(bridge->conn); ++ return ERR_PTR(ret); ++ } ++ drm_connector_attach_encoder(bridge->conn, bridge->enc); ++ ++ return bridge; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.h b/drivers/gpu/drm/verisilicon/vs_bridge.h +new file mode 100644 +index 000000000000..70fee1749699 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_bridge.h +@@ -0,0 +1,39 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#ifndef _VS_BRIDGE_H_ ++#define _VS_BRIDGE_H_ ++ ++#include ++ ++#include ++#include ++#include ++ ++struct vs_crtc; ++ ++enum vs_bridge_output_interface { ++ VSDC_OUTPUT_INTERFACE_DPI = 0, ++ VSDC_OUTPUT_INTERFACE_DP = 1 ++}; ++ ++struct vs_bridge { ++ struct drm_bridge base; ++ struct drm_encoder *enc; ++ struct drm_connector *conn; ++ ++ struct vs_crtc *crtc; ++ struct drm_bridge *next_bridge; ++ enum vs_bridge_output_interface intf; ++}; ++ ++static inline struct vs_bridge *drm_bridge_to_vs_bridge(struct drm_bridge *bridge) ++{ ++ return container_of(bridge, struct vs_bridge, base); ++} ++ ++struct vs_bridge *vs_bridge_init(struct drm_device *drm_dev, ++ struct vs_crtc *crtc); ++#endif /* _VS_BRIDGE_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_bridge_regs.h b/drivers/gpu/drm/verisilicon/vs_bridge_regs.h +new file mode 100644 +index 000000000000..9eb30e4564be +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_bridge_regs.h +@@ -0,0 +1,54 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_BRIDGE_REGS_H_ ++#define _VS_BRIDGE_REGS_H_ ++ ++#include ++ ++#define VSDC_DISP_PANEL_CONFIG(n) (0x1418 + 0x4 * (n)) ++#define VSDC_DISP_PANEL_CONFIG_DE_EN BIT(0) ++#define VSDC_DISP_PANEL_CONFIG_DE_POL BIT(1) ++#define VSDC_DISP_PANEL_CONFIG_DAT_EN BIT(4) ++#define VSDC_DISP_PANEL_CONFIG_DAT_POL BIT(5) ++#define VSDC_DISP_PANEL_CONFIG_CLK_EN BIT(8) ++#define VSDC_DISP_PANEL_CONFIG_CLK_POL BIT(9) ++#define VSDC_DISP_PANEL_CONFIG_RUNNING BIT(12) ++#define VSDC_DISP_PANEL_CONFIG_GAMMA BIT(13) ++#define VSDC_DISP_PANEL_CONFIG_YUV BIT(16) ++ ++#define VSDC_DISP_DPI_CONFIG(n) (0x14B8 + 0x4 * (n)) ++#define VSDC_DISP_DPI_CONFIG_FMT_MASK GENMASK(2, 0) ++#define VSDC_DISP_DPI_CONFIG_FMT_RGB565 (0) ++#define VSDC_DISP_DPI_CONFIG_FMT_RGB666 (3) ++#define VSDC_DISP_DPI_CONFIG_FMT_RGB888 (5) ++#define VSDC_DISP_DPI_CONFIG_FMT_RGB101010 (6) ++ ++#define VSDC_DISP_PANEL_START 0x1CCC ++#define VSDC_DISP_PANEL_START_RUNNING(n) BIT(n) ++#define VSDC_DISP_PANEL_START_MULTI_DISP_SYNC BIT(3) ++ ++#define VSDC_DISP_DP_CONFIG(n) (0x1CD0 + 0x4 * (n)) ++#define VSDC_DISP_DP_CONFIG_DP_EN BIT(3) ++#define VSDC_DISP_DP_CONFIG_FMT_MASK GENMASK(2, 0) ++#define VSDC_DISP_DP_CONFIG_FMT_RGB565 (0) ++#define VSDC_DISP_DP_CONFIG_FMT_RGB666 (1) ++#define VSDC_DISP_DP_CONFIG_FMT_RGB888 (2) ++#define VSDC_DISP_DP_CONFIG_FMT_RGB101010 (3) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_MASK GENMASK(7, 4) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY8 (2 << 4) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_YUV8 (4 << 4) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY10 (8 << 4) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_YUV10 (10 << 4) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY8 (12 << 4) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY10 (13 << 4) ++ ++#define VSDC_DISP_PANEL_CONFIG_EX(n) (0x2518 + 0x4 * (n)) ++#define VSDC_DISP_PANEL_CONFIG_EX_COMMIT BIT(0) ++ ++#endif /* _VS_BRIDGE_REGS_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisilicon/vs_crtc.c +new file mode 100644 +index 000000000000..f49401713000 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_crtc.c +@@ -0,0 +1,191 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_crtc_regs.h" ++#include "vs_crtc.h" ++#include "vs_dc.h" ++#include "vs_dc_top_regs.h" ++#include "vs_drm.h" ++#include "vs_plane.h" ++ ++static void vs_crtc_atomic_disable(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ unsigned int output = vcrtc->id; ++ ++ drm_crtc_vblank_off(crtc); ++ ++ clk_disable_unprepare(dc->pix_clk[output]); ++} ++ ++static void vs_crtc_atomic_enable(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ unsigned int output = vcrtc->id; ++ ++ drm_WARN_ON(&dc->drm_dev->base, ++ clk_prepare_enable(dc->pix_clk[output])); ++ ++ drm_crtc_vblank_on(crtc); ++} ++ ++static void vs_crtc_mode_set_nofb(struct drm_crtc *crtc) ++{ ++ struct drm_display_mode *mode = &crtc->state->adjusted_mode; ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ unsigned int output = vcrtc->id; ++ ++ regmap_write(dc->regs, VSDC_DISP_HSIZE(output), ++ VSDC_DISP_HSIZE_DISP(mode->hdisplay) | ++ VSDC_DISP_HSIZE_TOTAL(mode->htotal)); ++ regmap_write(dc->regs, VSDC_DISP_VSIZE(output), ++ VSDC_DISP_VSIZE_DISP(mode->vdisplay) | ++ VSDC_DISP_VSIZE_TOTAL(mode->vtotal)); ++ regmap_write(dc->regs, VSDC_DISP_HSYNC(output), ++ VSDC_DISP_HSYNC_START(mode->hsync_start) | ++ VSDC_DISP_HSYNC_END(mode->hsync_end) | ++ VSDC_DISP_HSYNC_EN); ++ if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) ++ regmap_set_bits(dc->regs, VSDC_DISP_HSYNC(output), ++ VSDC_DISP_HSYNC_POL); ++ regmap_write(dc->regs, VSDC_DISP_VSYNC(output), ++ VSDC_DISP_VSYNC_START(mode->vsync_start) | ++ VSDC_DISP_VSYNC_END(mode->vsync_end) | ++ VSDC_DISP_VSYNC_EN); ++ if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) ++ regmap_set_bits(dc->regs, VSDC_DISP_VSYNC(output), ++ VSDC_DISP_VSYNC_POL); ++ ++ WARN_ON(clk_set_rate(dc->pix_clk[output], mode->crtc_clock * 1000)); ++} ++ ++static enum drm_mode_status ++vs_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) ++{ ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ unsigned int output = vcrtc->id; ++ long rate; ++ ++ if (mode->htotal > VSDC_DISP_TIMING_VALUE_MAX) ++ return MODE_BAD_HVALUE; ++ if (mode->vtotal > VSDC_DISP_TIMING_VALUE_MAX) ++ return MODE_BAD_VVALUE; ++ ++ rate = clk_round_rate(dc->pix_clk[output], mode->clock * HZ_PER_KHZ); ++ if (rate <= 0) ++ return MODE_CLOCK_RANGE; ++ ++ return MODE_OK; ++} ++ ++static bool vs_crtc_mode_fixup(struct drm_crtc *crtc, ++ const struct drm_display_mode *m, ++ struct drm_display_mode *adjusted_mode) ++{ ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ unsigned int output = vcrtc->id; ++ long clk_rate; ++ ++ drm_mode_set_crtcinfo(adjusted_mode, 0); ++ ++ /* Feedback the pixel clock to crtc_clock */ ++ clk_rate = adjusted_mode->crtc_clock * HZ_PER_KHZ; ++ clk_rate = clk_round_rate(dc->pix_clk[output], clk_rate); ++ if (clk_rate <= 0) ++ return false; ++ ++ adjusted_mode->crtc_clock = clk_rate / HZ_PER_KHZ; ++ ++ return true; ++} ++ ++static const struct drm_crtc_helper_funcs vs_crtc_helper_funcs = { ++ .atomic_flush = drm_crtc_vblank_atomic_flush, ++ .atomic_enable = vs_crtc_atomic_enable, ++ .atomic_disable = vs_crtc_atomic_disable, ++ .mode_set_nofb = vs_crtc_mode_set_nofb, ++ .mode_valid = vs_crtc_mode_valid, ++ .mode_fixup = vs_crtc_mode_fixup, ++}; ++ ++static int vs_crtc_enable_vblank(struct drm_crtc *crtc) ++{ ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id)); ++ ++ return 0; ++} ++ ++static void vs_crtc_disable_vblank(struct drm_crtc *crtc) ++{ ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_clear_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id)); ++} ++ ++static const struct drm_crtc_funcs vs_crtc_funcs = { ++ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, ++ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, ++ .page_flip = drm_atomic_helper_page_flip, ++ .reset = drm_atomic_helper_crtc_reset, ++ .set_config = drm_atomic_helper_set_config, ++ .enable_vblank = vs_crtc_enable_vblank, ++ .disable_vblank = vs_crtc_disable_vblank, ++}; ++ ++struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, ++ unsigned int output) ++{ ++ struct vs_crtc *vcrtc; ++ struct drm_plane *primary; ++ int ret; ++ ++ vcrtc = drmm_kzalloc(drm_dev, sizeof(*vcrtc), GFP_KERNEL); ++ if (!vcrtc) ++ return ERR_PTR(-ENOMEM); ++ vcrtc->dc = dc; ++ vcrtc->id = output; ++ ++ /* Create our primary plane */ ++ primary = vs_primary_plane_init(drm_dev, dc); ++ if (IS_ERR(primary)) { ++ drm_err(drm_dev, "Couldn't create the primary plane\n"); ++ return ERR_PTR(PTR_ERR(primary)); ++ } ++ ++ ret = drmm_crtc_init_with_planes(drm_dev, &vcrtc->base, ++ primary, ++ NULL, ++ &vs_crtc_funcs, ++ NULL); ++ if (ret) { ++ drm_err(drm_dev, "Couldn't initialize CRTC\n"); ++ return ERR_PTR(ret); ++ } ++ ++ drm_crtc_helper_add(&vcrtc->base, &vs_crtc_helper_funcs); ++ ++ return vcrtc; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.h b/drivers/gpu/drm/verisilicon/vs_crtc.h +new file mode 100644 +index 000000000000..b45580bd99b3 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_crtc.h +@@ -0,0 +1,31 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#ifndef _VS_CRTC_H_ ++#define _VS_CRTC_H_ ++ ++#include ++#include ++ ++#define VSDC_DISP_TIMING_VALUE_MAX BIT_MASK(15) ++ ++struct vs_dc; ++ ++struct vs_crtc { ++ struct drm_crtc base; ++ ++ struct vs_dc *dc; ++ unsigned int id; ++}; ++ ++static inline struct vs_crtc *drm_crtc_to_vs_crtc(struct drm_crtc *crtc) ++{ ++ return container_of(crtc, struct vs_crtc, base); ++} ++ ++struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, ++ unsigned int output); ++ ++#endif /* _VS_CRTC_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h +new file mode 100644 +index 000000000000..c7930e817635 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h +@@ -0,0 +1,60 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_CRTC_REGS_H_ ++#define _VS_CRTC_REGS_H_ ++ ++#include ++ ++#define VSDC_DISP_DITHER_CONFIG(n) (0x1410 + 0x4 * (n)) ++ ++#define VSDC_DISP_DITHER_TABLE_LOW(n) (0x1420 + 0x4 * (n)) ++#define VSDC_DISP_DITHER_TABLE_LOW_DEFAULT 0x7B48F3C0 ++ ++#define VSDC_DISP_DITHER_TABLE_HIGH(n) (0x1428 + 0x4 * (n)) ++#define VSDC_DISP_DITHER_TABLE_HIGH_DEFAULT 0x596AD1E2 ++ ++#define VSDC_DISP_HSIZE(n) (0x1430 + 0x4 * (n)) ++#define VSDC_DISP_HSIZE_DISP_MASK GENMASK(14, 0) ++#define VSDC_DISP_HSIZE_DISP(v) ((v) << 0) ++#define VSDC_DISP_HSIZE_TOTAL_MASK GENMASK(30, 16) ++#define VSDC_DISP_HSIZE_TOTAL(v) ((v) << 16) ++ ++#define VSDC_DISP_HSYNC(n) (0x1438 + 0x4 * (n)) ++#define VSDC_DISP_HSYNC_START_MASK GENMASK(14, 0) ++#define VSDC_DISP_HSYNC_START(v) ((v) << 0) ++#define VSDC_DISP_HSYNC_END_MASK GENMASK(29, 15) ++#define VSDC_DISP_HSYNC_END(v) ((v) << 15) ++#define VSDC_DISP_HSYNC_EN BIT(30) ++#define VSDC_DISP_HSYNC_POL BIT(31) ++ ++#define VSDC_DISP_VSIZE(n) (0x1440 + 0x4 * (n)) ++#define VSDC_DISP_VSIZE_DISP_MASK GENMASK(14, 0) ++#define VSDC_DISP_VSIZE_DISP(v) ((v) << 0) ++#define VSDC_DISP_VSIZE_TOTAL_MASK GENMASK(30, 16) ++#define VSDC_DISP_VSIZE_TOTAL(v) ((v) << 16) ++ ++#define VSDC_DISP_VSYNC(n) (0x1448 + 0x4 * (n)) ++#define VSDC_DISP_VSYNC_START_MASK GENMASK(14, 0) ++#define VSDC_DISP_VSYNC_START(v) ((v) << 0) ++#define VSDC_DISP_VSYNC_END_MASK GENMASK(29, 15) ++#define VSDC_DISP_VSYNC_END(v) ((v) << 15) ++#define VSDC_DISP_VSYNC_EN BIT(30) ++#define VSDC_DISP_VSYNC_POL BIT(31) ++ ++#define VSDC_DISP_CURRENT_LOCATION(n) (0x1450 + 0x4 * (n)) ++ ++#define VSDC_DISP_GAMMA_INDEX(n) (0x1458 + 0x4 * (n)) ++ ++#define VSDC_DISP_GAMMA_DATA(n) (0x1460 + 0x4 * (n)) ++ ++#define VSDC_DISP_IRQ_STA 0x147C ++ ++#define VSDC_DISP_IRQ_EN 0x1480 ++ ++#endif /* _VS_CRTC_REGS_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c +new file mode 100644 +index 000000000000..ba1b3f261a3a +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_dc.c +@@ -0,0 +1,207 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "vs_crtc.h" ++#include "vs_dc.h" ++#include "vs_dc_top_regs.h" ++#include "vs_drm.h" ++#include "vs_hwdb.h" ++ ++static const struct regmap_config vs_dc_regmap_cfg = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = sizeof(u32), ++ /* VSDC_OVL_CONFIG_EX(1) */ ++ .max_register = 0x2544, ++}; ++ ++static const struct of_device_id vs_dc_driver_dt_match[] = { ++ { .compatible = "verisilicon,dc" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, vs_dc_driver_dt_match); ++ ++static irqreturn_t vs_dc_irq_handler(int irq, void *private) ++{ ++ struct vs_dc *dc = private; ++ u32 irqs; ++ ++ regmap_read(dc->regs, VSDC_TOP_IRQ_ACK, &irqs); ++ ++ vs_drm_handle_irq(dc, irqs); ++ ++ return IRQ_HANDLED; ++} ++ ++static int vs_dc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct vs_dc *dc; ++ void __iomem *regs; ++ unsigned int port_count, i; ++ /* pix0/pix1 */ ++ char pixclk_name[5]; ++ int irq, ret; ++ ++ if (!dev->of_node) { ++ dev_err(dev, "can't find DC devices\n"); ++ return -ENODEV; ++ } ++ ++ port_count = of_graph_get_port_count(dev->of_node); ++ if (!port_count) { ++ dev_err(dev, "can't find DC downstream ports\n"); ++ return -ENODEV; ++ } ++ if (port_count > VSDC_MAX_OUTPUTS) { ++ dev_err(dev, "too many DC downstream ports than possible\n"); ++ return -EINVAL; ++ } ++ ++ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(dev, "No suitable DMA available\n"); ++ return ret; ++ } ++ ++ dc = devm_kzalloc(dev, sizeof(*dc), GFP_KERNEL); ++ if (!dc) ++ return -ENOMEM; ++ ++ dc->rsts[0].id = "core"; ++ dc->rsts[1].id = "axi"; ++ dc->rsts[2].id = "ahb"; ++ ++ ret = devm_reset_control_bulk_get_optional_shared(dev, VSDC_RESET_COUNT, ++ dc->rsts); ++ if (ret) { ++ dev_err(dev, "can't get reset lines\n"); ++ return ret; ++ } ++ ++ dc->core_clk = devm_clk_get_enabled(dev, "core"); ++ if (IS_ERR(dc->core_clk)) { ++ dev_err(dev, "can't get core clock\n"); ++ return PTR_ERR(dc->core_clk); ++ } ++ ++ dc->axi_clk = devm_clk_get_enabled(dev, "axi"); ++ if (IS_ERR(dc->axi_clk)) { ++ dev_err(dev, "can't get axi clock\n"); ++ return PTR_ERR(dc->axi_clk); ++ } ++ ++ dc->ahb_clk = devm_clk_get_enabled(dev, "ahb"); ++ if (IS_ERR(dc->ahb_clk)) { ++ dev_err(dev, "can't get ahb clock\n"); ++ return PTR_ERR(dc->ahb_clk); ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(dev, "can't get irq\n"); ++ return irq; ++ } ++ ++ ret = reset_control_bulk_deassert(VSDC_RESET_COUNT, dc->rsts); ++ if (ret) { ++ dev_err(dev, "can't deassert reset lines\n"); ++ return ret; ++ } ++ ++ regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(regs)) { ++ dev_err(dev, "can't map registers"); ++ ret = PTR_ERR(regs); ++ goto err_rst_assert; ++ } ++ ++ dc->regs = devm_regmap_init_mmio(dev, regs, &vs_dc_regmap_cfg); ++ if (IS_ERR(dc->regs)) { ++ ret = PTR_ERR(dc->regs); ++ goto err_rst_assert; ++ } ++ ++ ret = vs_fill_chip_identity(dc->regs, &dc->identity); ++ if (ret) ++ goto err_rst_assert; ++ ++ dev_info(dev, "Found DC%x rev %x customer %x\n", dc->identity.model, ++ dc->identity.revision, dc->identity.customer_id); ++ ++ if (port_count > dc->identity.display_count) { ++ dev_err(dev, "too many downstream ports than HW capability\n"); ++ ret = -EINVAL; ++ goto err_rst_assert; ++ } ++ ++ for (i = 0; i < dc->identity.display_count; i++) { ++ snprintf(pixclk_name, sizeof(pixclk_name), "pix%u", i); ++ dc->pix_clk[i] = devm_clk_get(dev, pixclk_name); ++ if (IS_ERR(dc->pix_clk[i])) { ++ dev_err(dev, "can't get pixel clk %u\n", i); ++ ret = PTR_ERR(dc->pix_clk[i]); ++ goto err_rst_assert; ++ } ++ } ++ ++ ret = devm_request_irq(dev, irq, vs_dc_irq_handler, 0, ++ dev_name(dev), dc); ++ if (ret) { ++ dev_err(dev, "can't request irq\n"); ++ goto err_rst_assert; ++ } ++ ++ dev_set_drvdata(dev, dc); ++ ++ ret = vs_drm_initialize(dc, pdev); ++ if (ret) ++ goto err_rst_assert; ++ ++ return 0; ++ ++err_rst_assert: ++ reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); ++ return ret; ++} ++ ++static void vs_dc_remove(struct platform_device *pdev) ++{ ++ struct vs_dc *dc = dev_get_drvdata(&pdev->dev); ++ ++ vs_drm_finalize(dc); ++ ++ dev_set_drvdata(&pdev->dev, NULL); ++ ++ reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); ++} ++ ++static void vs_dc_shutdown(struct platform_device *pdev) ++{ ++ struct vs_dc *dc = dev_get_drvdata(&pdev->dev); ++ ++ vs_drm_shutdown_handler(dc); ++} ++ ++struct platform_driver vs_dc_platform_driver = { ++ .probe = vs_dc_probe, ++ .remove = vs_dc_remove, ++ .shutdown = vs_dc_shutdown, ++ .driver = { ++ .name = "verisilicon-dc", ++ .of_match_table = vs_dc_driver_dt_match, ++ }, ++}; ++ ++module_platform_driver(vs_dc_platform_driver); ++ ++MODULE_AUTHOR("Icenowy Zheng "); ++MODULE_DESCRIPTION("Verisilicon display controller driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h b/drivers/gpu/drm/verisilicon/vs_dc.h +new file mode 100644 +index 000000000000..ed1016f18758 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_dc.h +@@ -0,0 +1,38 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_DC_H_ ++#define _VS_DC_H_ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include "vs_hwdb.h" ++ ++#define VSDC_MAX_OUTPUTS 2 ++#define VSDC_RESET_COUNT 3 ++ ++struct vs_drm_dev; ++struct vs_crtc; ++ ++struct vs_dc { ++ struct regmap *regs; ++ struct clk *core_clk; ++ struct clk *axi_clk; ++ struct clk *ahb_clk; ++ struct clk *pix_clk[VSDC_MAX_OUTPUTS]; ++ struct reset_control_bulk_data rsts[VSDC_RESET_COUNT]; ++ ++ struct vs_drm_dev *drm_dev; ++ struct vs_chip_identity identity; ++}; ++ ++#endif /* _VS_DC_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h b/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h +new file mode 100644 +index 000000000000..50509bbbff08 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_DC_TOP_H_ ++#define _VS_DC_TOP_H_ ++ ++#include ++ ++#define VSDC_TOP_RST 0x0000 ++ ++#define VSDC_TOP_IRQ_ACK 0x0010 ++#define VSDC_TOP_IRQ_VSYNC(n) BIT(n) ++ ++#define VSDC_TOP_IRQ_EN 0x0014 ++ ++#define VSDC_TOP_CHIP_MODEL 0x0020 ++ ++#define VSDC_TOP_CHIP_REV 0x0024 ++ ++#define VSDC_TOP_CHIP_CUSTOMER_ID 0x0030 ++ ++#endif /* _VS_DC_TOP_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_drm.c b/drivers/gpu/drm/verisilicon/vs_drm.c +new file mode 100644 +index 000000000000..fd259d53f49f +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_drm.c +@@ -0,0 +1,182 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_bridge.h" ++#include "vs_crtc.h" ++#include "vs_dc.h" ++#include "vs_dc_top_regs.h" ++#include "vs_drm.h" ++ ++#define DRIVER_NAME "verisilicon" ++#define DRIVER_DESC "Verisilicon DC-series display controller driver" ++#define DRIVER_MAJOR 1 ++#define DRIVER_MINOR 0 ++ ++static int vs_gem_dumb_create(struct drm_file *file_priv, ++ struct drm_device *drm, ++ struct drm_mode_create_dumb *args) ++{ ++ int ret; ++ ++ /* The hardware wants 128B-aligned pitches for linear buffers. */ ++ ret = drm_mode_size_dumb(drm, args, 128, 0); ++ if (ret) ++ return ret; ++ ++ return drm_gem_dma_dumb_create_internal(file_priv, drm, args); ++} ++ ++DEFINE_DRM_GEM_FOPS(vs_drm_driver_fops); ++ ++static const struct drm_driver vs_drm_driver = { ++ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, ++ .fops = &vs_drm_driver_fops, ++ .name = DRIVER_NAME, ++ .desc = DRIVER_DESC, ++ .major = DRIVER_MAJOR, ++ .minor = DRIVER_MINOR, ++ ++ /* GEM Operations */ ++ DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(vs_gem_dumb_create), ++ DRM_FBDEV_DMA_DRIVER_OPS, ++}; ++ ++static const struct drm_mode_config_funcs vs_mode_config_funcs = { ++ .fb_create = drm_gem_fb_create, ++ .atomic_check = drm_atomic_helper_check, ++ .atomic_commit = drm_atomic_helper_commit, ++}; ++ ++static struct drm_mode_config_helper_funcs vs_mode_config_helper_funcs = { ++ .atomic_commit_tail = drm_atomic_helper_commit_tail, ++}; ++ ++static void vs_mode_config_init(struct drm_device *drm) ++{ ++ drm->mode_config.min_width = 0; ++ drm->mode_config.min_height = 0; ++ drm->mode_config.max_width = 8192; ++ drm->mode_config.max_height = 8192; ++ drm->mode_config.funcs = &vs_mode_config_funcs; ++ drm->mode_config.helper_private = &vs_mode_config_helper_funcs; ++} ++ ++int vs_drm_initialize(struct vs_dc *dc, struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct vs_drm_dev *vdrm; ++ struct drm_device *drm; ++ struct vs_crtc *crtc; ++ struct vs_bridge *bridge; ++ unsigned int i; ++ int ret; ++ ++ vdrm = devm_drm_dev_alloc(dev, &vs_drm_driver, struct vs_drm_dev, base); ++ if (IS_ERR(vdrm)) ++ return PTR_ERR(vdrm); ++ ++ drm = &vdrm->base; ++ vdrm->dc = dc; ++ dc->drm_dev = vdrm; ++ ++ ret = drmm_mode_config_init(drm); ++ if (ret) ++ return ret; ++ ++ /* Remove early framebuffers (ie. simple-framebuffer) */ ++ ret = aperture_remove_all_conflicting_devices(DRIVER_NAME); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < dc->identity.display_count; i++) { ++ crtc = vs_crtc_init(drm, dc, i); ++ if (IS_ERR(crtc)) ++ return PTR_ERR(crtc); ++ ++ bridge = vs_bridge_init(drm, crtc); ++ if (IS_ERR(bridge)) ++ return PTR_ERR(bridge); ++ ++ vdrm->crtcs[i] = crtc; ++ } ++ ++ ret = drm_vblank_init(drm, dc->identity.display_count); ++ if (ret) ++ return ret; ++ ++ vs_mode_config_init(drm); ++ ++ /* Enable connectors polling */ ++ drm_kms_helper_poll_init(drm); ++ ++ drm_mode_config_reset(drm); ++ ++ ret = drm_dev_register(drm, 0); ++ if (ret) ++ goto err_fini_poll; ++ ++ drm_client_setup(drm, NULL); ++ ++ return 0; ++ ++err_fini_poll: ++ drm_kms_helper_poll_fini(drm); ++ return ret; ++} ++ ++void vs_drm_finalize(struct vs_dc *dc) ++{ ++ struct vs_drm_dev *vdrm = dc->drm_dev; ++ struct drm_device *drm = &vdrm->base; ++ ++ drm_dev_unregister(drm); ++ drm_kms_helper_poll_fini(drm); ++ drm_atomic_helper_shutdown(drm); ++ dc->drm_dev = NULL; ++} ++ ++void vs_drm_shutdown_handler(struct vs_dc *dc) ++{ ++ struct vs_drm_dev *vdrm = dc->drm_dev; ++ ++ drm_atomic_helper_shutdown(&vdrm->base); ++} ++ ++void vs_drm_handle_irq(struct vs_dc *dc, u32 irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < dc->identity.display_count; i++) { ++ if (irqs & VSDC_TOP_IRQ_VSYNC(i)) { ++ irqs &= ~VSDC_TOP_IRQ_VSYNC(i); ++ if (dc->drm_dev->crtcs[i]) ++ drm_crtc_handle_vblank(&dc->drm_dev->crtcs[i]->base); ++ } ++ } ++ ++ if (irqs) ++ drm_warn_once(&dc->drm_dev->base, ++ "Unknown Verisilicon DC interrupt 0x%x fired!\n", ++ irqs); ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_drm.h b/drivers/gpu/drm/verisilicon/vs_drm.h +new file mode 100644 +index 000000000000..606338206a42 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_drm.h +@@ -0,0 +1,28 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#ifndef _VS_DRM_H_ ++#define _VS_DRM_H_ ++ ++#include ++#include ++ ++#include ++ ++struct vs_dc; ++ ++struct vs_drm_dev { ++ struct drm_device base; ++ ++ struct vs_dc *dc; ++ struct vs_crtc *crtcs[VSDC_MAX_OUTPUTS]; ++}; ++ ++int vs_drm_initialize(struct vs_dc *dc, struct platform_device *pdev); ++void vs_drm_finalize(struct vs_dc *dc); ++void vs_drm_shutdown_handler(struct vs_dc *dc); ++void vs_drm_handle_irq(struct vs_dc *dc, u32 irqs); ++ ++#endif /* _VS_DRM_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisilicon/vs_hwdb.c +new file mode 100644 +index 000000000000..09336af0900a +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c +@@ -0,0 +1,150 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++ ++#include ++ ++#include "vs_dc_top_regs.h" ++#include "vs_hwdb.h" ++ ++static const u32 vs_formats_array_no_yuv444[] = { ++ DRM_FORMAT_XRGB4444, ++ DRM_FORMAT_XBGR4444, ++ DRM_FORMAT_RGBX4444, ++ DRM_FORMAT_BGRX4444, ++ DRM_FORMAT_ARGB4444, ++ DRM_FORMAT_ABGR4444, ++ DRM_FORMAT_RGBA4444, ++ DRM_FORMAT_BGRA4444, ++ DRM_FORMAT_XRGB1555, ++ DRM_FORMAT_XBGR1555, ++ DRM_FORMAT_RGBX5551, ++ DRM_FORMAT_BGRX5551, ++ DRM_FORMAT_ARGB1555, ++ DRM_FORMAT_ABGR1555, ++ DRM_FORMAT_RGBA5551, ++ DRM_FORMAT_BGRA5551, ++ DRM_FORMAT_RGB565, ++ DRM_FORMAT_BGR565, ++ DRM_FORMAT_XRGB8888, ++ DRM_FORMAT_XBGR8888, ++ DRM_FORMAT_RGBX8888, ++ DRM_FORMAT_BGRX8888, ++ DRM_FORMAT_ARGB8888, ++ DRM_FORMAT_ABGR8888, ++ DRM_FORMAT_RGBA8888, ++ DRM_FORMAT_BGRA8888, ++ DRM_FORMAT_ARGB2101010, ++ DRM_FORMAT_ABGR2101010, ++ DRM_FORMAT_RGBA1010102, ++ DRM_FORMAT_BGRA1010102, ++ /* TODO: non-RGB formats */ ++}; ++ ++static const u32 vs_formats_array_with_yuv444[] = { ++ DRM_FORMAT_XRGB4444, ++ DRM_FORMAT_XBGR4444, ++ DRM_FORMAT_RGBX4444, ++ DRM_FORMAT_BGRX4444, ++ DRM_FORMAT_ARGB4444, ++ DRM_FORMAT_ABGR4444, ++ DRM_FORMAT_RGBA4444, ++ DRM_FORMAT_BGRA4444, ++ DRM_FORMAT_XRGB1555, ++ DRM_FORMAT_XBGR1555, ++ DRM_FORMAT_RGBX5551, ++ DRM_FORMAT_BGRX5551, ++ DRM_FORMAT_ARGB1555, ++ DRM_FORMAT_ABGR1555, ++ DRM_FORMAT_RGBA5551, ++ DRM_FORMAT_BGRA5551, ++ DRM_FORMAT_RGB565, ++ DRM_FORMAT_BGR565, ++ DRM_FORMAT_XRGB8888, ++ DRM_FORMAT_XBGR8888, ++ DRM_FORMAT_RGBX8888, ++ DRM_FORMAT_BGRX8888, ++ DRM_FORMAT_ARGB8888, ++ DRM_FORMAT_ABGR8888, ++ DRM_FORMAT_RGBA8888, ++ DRM_FORMAT_BGRA8888, ++ DRM_FORMAT_ARGB2101010, ++ DRM_FORMAT_ABGR2101010, ++ DRM_FORMAT_RGBA1010102, ++ DRM_FORMAT_BGRA1010102, ++ /* TODO: non-RGB formats */ ++}; ++ ++static const struct vs_formats vs_formats_no_yuv444 = { ++ .array = vs_formats_array_no_yuv444, ++ .num = ARRAY_SIZE(vs_formats_array_no_yuv444) ++}; ++ ++static const struct vs_formats vs_formats_with_yuv444 = { ++ .array = vs_formats_array_with_yuv444, ++ .num = ARRAY_SIZE(vs_formats_array_with_yuv444) ++}; ++ ++static struct vs_chip_identity vs_chip_identities[] = { ++ { ++ .model = 0x8200, ++ .revision = 0x5720, ++ .customer_id = ~0U, ++ ++ .display_count = 2, ++ .formats = &vs_formats_no_yuv444, ++ }, ++ { ++ .model = 0x8200, ++ .revision = 0x5721, ++ .customer_id = 0x30B, ++ ++ .display_count = 2, ++ .formats = &vs_formats_no_yuv444, ++ }, ++ { ++ .model = 0x8200, ++ .revision = 0x5720, ++ .customer_id = 0x310, ++ ++ .display_count = 2, ++ .formats = &vs_formats_with_yuv444, ++ }, ++ { ++ .model = 0x8200, ++ .revision = 0x5720, ++ .customer_id = 0x311, ++ ++ .display_count = 2, ++ .formats = &vs_formats_no_yuv444, ++ }, ++}; ++ ++int vs_fill_chip_identity(struct regmap *regs, ++ struct vs_chip_identity *ident) ++{ ++ u32 model; ++ u32 revision; ++ u32 customer_id; ++ int i; ++ ++ regmap_read(regs, VSDC_TOP_CHIP_MODEL, &model); ++ regmap_read(regs, VSDC_TOP_CHIP_REV, &revision); ++ regmap_read(regs, VSDC_TOP_CHIP_CUSTOMER_ID, &customer_id); ++ ++ for (i = 0; i < ARRAY_SIZE(vs_chip_identities); i++) { ++ if (vs_chip_identities[i].model == model && ++ vs_chip_identities[i].revision == revision && ++ (vs_chip_identities[i].customer_id == customer_id || ++ vs_chip_identities[i].customer_id == ~0U)) { ++ memcpy(ident, &vs_chip_identities[i], sizeof(*ident)); ++ ident->customer_id = customer_id; ++ return 0; ++ } ++ } ++ ++ return -EINVAL; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisilicon/vs_hwdb.h +new file mode 100644 +index 000000000000..92192e4fa086 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h +@@ -0,0 +1,29 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#ifndef _VS_HWDB_H_ ++#define _VS_HWDB_H_ ++ ++#include ++#include ++ ++struct vs_formats { ++ const u32 *array; ++ unsigned int num; ++}; ++ ++struct vs_chip_identity { ++ u32 model; ++ u32 revision; ++ u32 customer_id; ++ ++ u32 display_count; ++ const struct vs_formats *formats; ++}; ++ ++int vs_fill_chip_identity(struct regmap *regs, ++ struct vs_chip_identity *ident); ++ ++#endif /* _VS_HWDB_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_plane.c b/drivers/gpu/drm/verisilicon/vs_plane.c +new file mode 100644 +index 000000000000..2f3953e588a3 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_plane.c +@@ -0,0 +1,124 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "vs_plane.h" ++ ++void drm_format_to_vs_format(u32 drm_format, struct vs_format *vs_format) ++{ ++ switch (drm_format) { ++ case DRM_FORMAT_XRGB4444: ++ case DRM_FORMAT_RGBX4444: ++ case DRM_FORMAT_XBGR4444: ++ case DRM_FORMAT_BGRX4444: ++ vs_format->color = VSDC_COLOR_FORMAT_X4R4G4B4; ++ break; ++ case DRM_FORMAT_ARGB4444: ++ case DRM_FORMAT_RGBA4444: ++ case DRM_FORMAT_ABGR4444: ++ case DRM_FORMAT_BGRA4444: ++ vs_format->color = VSDC_COLOR_FORMAT_A4R4G4B4; ++ break; ++ case DRM_FORMAT_XRGB1555: ++ case DRM_FORMAT_RGBX5551: ++ case DRM_FORMAT_XBGR1555: ++ case DRM_FORMAT_BGRX5551: ++ vs_format->color = VSDC_COLOR_FORMAT_X1R5G5B5; ++ break; ++ case DRM_FORMAT_ARGB1555: ++ case DRM_FORMAT_RGBA5551: ++ case DRM_FORMAT_ABGR1555: ++ case DRM_FORMAT_BGRA5551: ++ vs_format->color = VSDC_COLOR_FORMAT_A1R5G5B5; ++ break; ++ case DRM_FORMAT_RGB565: ++ case DRM_FORMAT_BGR565: ++ vs_format->color = VSDC_COLOR_FORMAT_R5G6B5; ++ break; ++ case DRM_FORMAT_XRGB8888: ++ case DRM_FORMAT_RGBX8888: ++ case DRM_FORMAT_XBGR8888: ++ case DRM_FORMAT_BGRX8888: ++ vs_format->color = VSDC_COLOR_FORMAT_X8R8G8B8; ++ break; ++ case DRM_FORMAT_ARGB8888: ++ case DRM_FORMAT_RGBA8888: ++ case DRM_FORMAT_ABGR8888: ++ case DRM_FORMAT_BGRA8888: ++ vs_format->color = VSDC_COLOR_FORMAT_A8R8G8B8; ++ break; ++ case DRM_FORMAT_ARGB2101010: ++ case DRM_FORMAT_RGBA1010102: ++ case DRM_FORMAT_ABGR2101010: ++ case DRM_FORMAT_BGRA1010102: ++ vs_format->color = VSDC_COLOR_FORMAT_A2R10G10B10; ++ break; ++ default: ++ pr_warn("Unexpected drm format!\n"); ++ } ++ ++ switch (drm_format) { ++ case DRM_FORMAT_RGBX4444: ++ case DRM_FORMAT_RGBA4444: ++ case DRM_FORMAT_RGBX5551: ++ case DRM_FORMAT_RGBA5551: ++ case DRM_FORMAT_RGBX8888: ++ case DRM_FORMAT_RGBA8888: ++ case DRM_FORMAT_RGBA1010102: ++ vs_format->swizzle = VSDC_SWIZZLE_RGBA; ++ break; ++ case DRM_FORMAT_XBGR4444: ++ case DRM_FORMAT_ABGR4444: ++ case DRM_FORMAT_XBGR1555: ++ case DRM_FORMAT_ABGR1555: ++ case DRM_FORMAT_BGR565: ++ case DRM_FORMAT_XBGR8888: ++ case DRM_FORMAT_ABGR8888: ++ case DRM_FORMAT_ABGR2101010: ++ vs_format->swizzle = VSDC_SWIZZLE_ABGR; ++ break; ++ case DRM_FORMAT_BGRX4444: ++ case DRM_FORMAT_BGRA4444: ++ case DRM_FORMAT_BGRX5551: ++ case DRM_FORMAT_BGRA5551: ++ case DRM_FORMAT_BGRX8888: ++ case DRM_FORMAT_BGRA8888: ++ case DRM_FORMAT_BGRA1010102: ++ vs_format->swizzle = VSDC_SWIZZLE_BGRA; ++ break; ++ default: ++ /* N/A for YUV formats */ ++ vs_format->swizzle = VSDC_SWIZZLE_ARGB; ++ } ++ ++ /* N/A for non-YUV formats */ ++ vs_format->uv_swizzle = false; ++} ++ ++dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, ++ const struct drm_rect *src_rect) ++{ ++ struct drm_gem_dma_object *gem; ++ dma_addr_t dma_addr; ++ ++ /* Get the physical address of the buffer in memory */ ++ gem = drm_fb_dma_get_gem_obj(fb, 0); ++ ++ /* Compute the start of the displayed memory */ ++ dma_addr = gem->dma_addr + fb->offsets[0]; ++ ++ /* Fixup framebuffer address for src coordinates */ ++ dma_addr += drm_format_info_min_pitch(fb->format, 0, ++ src_rect->x1 >> 16); ++ dma_addr += (src_rect->y1 >> 16) * fb->pitches[0]; ++ ++ return dma_addr; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_plane.h b/drivers/gpu/drm/verisilicon/vs_plane.h +new file mode 100644 +index 000000000000..41875ea3d66a +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_plane.h +@@ -0,0 +1,72 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_PLANE_H_ ++#define _VS_PLANE_H_ ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#define VSDC_MAKE_PLANE_SIZE(w, h) (((w) & 0x7fff) | (((h) & 0x7fff) << 15)) ++#define VSDC_MAKE_PLANE_POS(x, y) (((x) & 0x7fff) | (((y) & 0x7fff) << 15)) ++ ++struct vs_dc; ++ ++enum vs_color_format { ++ VSDC_COLOR_FORMAT_X4R4G4B4, ++ VSDC_COLOR_FORMAT_A4R4G4B4, ++ VSDC_COLOR_FORMAT_X1R5G5B5, ++ VSDC_COLOR_FORMAT_A1R5G5B5, ++ VSDC_COLOR_FORMAT_R5G6B5, ++ VSDC_COLOR_FORMAT_X8R8G8B8, ++ VSDC_COLOR_FORMAT_A8R8G8B8, ++ VSDC_COLOR_FORMAT_YUY2, ++ VSDC_COLOR_FORMAT_UYVY, ++ VSDC_COLOR_FORMAT_INDEX8, ++ VSDC_COLOR_FORMAT_MONOCHROME, ++ VSDC_COLOR_FORMAT_YV12 = 0xf, ++ VSDC_COLOR_FORMAT_A8, ++ VSDC_COLOR_FORMAT_NV12, ++ VSDC_COLOR_FORMAT_NV16, ++ VSDC_COLOR_FORMAT_RG16, ++ VSDC_COLOR_FORMAT_R8, ++ VSDC_COLOR_FORMAT_NV12_10BIT, ++ VSDC_COLOR_FORMAT_A2R10G10B10, ++ VSDC_COLOR_FORMAT_NV16_10BIT, ++ VSDC_COLOR_FORMAT_INDEX1, ++ VSDC_COLOR_FORMAT_INDEX2, ++ VSDC_COLOR_FORMAT_INDEX4, ++ VSDC_COLOR_FORMAT_P010, ++ VSDC_COLOR_FORMAT_YUV444, ++ VSDC_COLOR_FORMAT_YUV444_10BIT ++}; ++ ++enum vs_swizzle { ++ VSDC_SWIZZLE_ARGB, ++ VSDC_SWIZZLE_RGBA, ++ VSDC_SWIZZLE_ABGR, ++ VSDC_SWIZZLE_BGRA, ++}; ++ ++struct vs_format { ++ enum vs_color_format color; ++ enum vs_swizzle swizzle; ++ bool uv_swizzle; ++}; ++ ++void drm_format_to_vs_format(u32 drm_format, struct vs_format *vs_format); ++dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, ++ const struct drm_rect *src_rect); ++ ++struct drm_plane *vs_primary_plane_init(struct drm_device *dev, struct vs_dc *dc); ++ ++#endif /* _VS_PLANE_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane.c b/drivers/gpu/drm/verisilicon/vs_primary_plane.c +new file mode 100644 +index 000000000000..e8fcb5958615 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_primary_plane.c +@@ -0,0 +1,173 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_crtc.h" ++#include "vs_plane.h" ++#include "vs_dc.h" ++#include "vs_primary_plane_regs.h" ++ ++static int vs_primary_plane_atomic_check(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, ++ plane); ++ struct drm_crtc *crtc = new_plane_state->crtc; ++ struct drm_crtc_state *crtc_state; ++ ++ if (!crtc) ++ return 0; ++ ++ crtc_state = drm_atomic_get_new_crtc_state(state, crtc); ++ if (WARN_ON(!crtc_state)) ++ return -EINVAL; ++ ++ return drm_atomic_helper_check_plane_state(new_plane_state, ++ crtc_state, ++ DRM_PLANE_NO_SCALING, ++ DRM_PLANE_NO_SCALING, ++ false, true); ++} ++ ++static void vs_primary_plane_commit(struct vs_dc *dc, unsigned int output) ++{ ++ regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), ++ VSDC_FB_CONFIG_EX_COMMIT); ++} ++ ++static void vs_primary_plane_atomic_enable(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, ++ plane); ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ unsigned int output = vcrtc->id; ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), ++ VSDC_FB_CONFIG_EX_FB_EN); ++ regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output), ++ VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK, ++ VSDC_FB_CONFIG_EX_DISPLAY_ID(output)); ++ ++ vs_primary_plane_commit(dc, output); ++} ++ ++static void vs_primary_plane_atomic_disable(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_old_plane_state(atomic_state, ++ plane); ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ unsigned int output = vcrtc->id; ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), ++ VSDC_FB_CONFIG_EX_FB_EN); ++ ++ vs_primary_plane_commit(dc, output); ++} ++ ++static void vs_primary_plane_atomic_update(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, ++ plane); ++ struct drm_framebuffer *fb = state->fb; ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_dc *dc; ++ struct vs_crtc *vcrtc; ++ struct vs_format fmt; ++ unsigned int output; ++ dma_addr_t dma_addr; ++ ++ if (!state->visible) { ++ vs_primary_plane_atomic_disable(plane, atomic_state); ++ return; ++ } ++ ++ vcrtc = drm_crtc_to_vs_crtc(crtc); ++ output = vcrtc->id; ++ dc = vcrtc->dc; ++ ++ drm_format_to_vs_format(state->fb->format->format, &fmt); ++ ++ regmap_update_bits(dc->regs, VSDC_FB_CONFIG(output), ++ VSDC_FB_CONFIG_FMT_MASK, ++ VSDC_FB_CONFIG_FMT(fmt.color)); ++ regmap_update_bits(dc->regs, VSDC_FB_CONFIG(output), ++ VSDC_FB_CONFIG_SWIZZLE_MASK, ++ VSDC_FB_CONFIG_SWIZZLE(fmt.swizzle)); ++ regmap_assign_bits(dc->regs, VSDC_FB_CONFIG(output), ++ VSDC_FB_CONFIG_UV_SWIZZLE_EN, fmt.uv_swizzle); ++ ++ dma_addr = vs_fb_get_dma_addr(fb, &state->src); ++ ++ regmap_write(dc->regs, VSDC_FB_ADDRESS(output), ++ lower_32_bits(dma_addr)); ++ regmap_write(dc->regs, VSDC_FB_STRIDE(output), ++ fb->pitches[0]); ++ ++ regmap_write(dc->regs, VSDC_FB_TOP_LEFT(output), ++ VSDC_MAKE_PLANE_POS(state->crtc_x, state->crtc_y)); ++ regmap_write(dc->regs, VSDC_FB_BOTTOM_RIGHT(output), ++ VSDC_MAKE_PLANE_POS(state->crtc_x + state->crtc_w, ++ state->crtc_y + state->crtc_h)); ++ regmap_write(dc->regs, VSDC_FB_SIZE(output), ++ VSDC_MAKE_PLANE_SIZE(state->crtc_w, state->crtc_h)); ++ ++ regmap_write(dc->regs, VSDC_FB_BLEND_CONFIG(output), ++ VSDC_FB_BLEND_CONFIG_BLEND_DISABLE); ++ ++ vs_primary_plane_commit(dc, output); ++} ++ ++static const struct drm_plane_helper_funcs vs_primary_plane_helper_funcs = { ++ .atomic_check = vs_primary_plane_atomic_check, ++ .atomic_update = vs_primary_plane_atomic_update, ++ .atomic_enable = vs_primary_plane_atomic_enable, ++ .atomic_disable = vs_primary_plane_atomic_disable, ++}; ++ ++static const struct drm_plane_funcs vs_primary_plane_funcs = { ++ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, ++ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, ++ .disable_plane = drm_atomic_helper_disable_plane, ++ .reset = drm_atomic_helper_plane_reset, ++ .update_plane = drm_atomic_helper_update_plane, ++}; ++ ++struct drm_plane *vs_primary_plane_init(struct drm_device *drm_dev, struct vs_dc *dc) ++{ ++ struct drm_plane *plane; ++ ++ plane = drmm_universal_plane_alloc(drm_dev, struct drm_plane, dev, 0, ++ &vs_primary_plane_funcs, ++ dc->identity.formats->array, ++ dc->identity.formats->num, ++ NULL, ++ DRM_PLANE_TYPE_PRIMARY, ++ NULL); ++ ++ if (IS_ERR(plane)) ++ return plane; ++ ++ drm_plane_helper_add(plane, &vs_primary_plane_helper_funcs); ++ ++ return plane; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h +new file mode 100644 +index 000000000000..cbb125c46b39 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h +@@ -0,0 +1,53 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_PRIMARY_PLANE_REGS_H_ ++#define _VS_PRIMARY_PLANE_REGS_H_ ++ ++#include ++ ++#define VSDC_FB_ADDRESS(n) (0x1400 + 0x4 * (n)) ++ ++#define VSDC_FB_STRIDE(n) (0x1408 + 0x4 * (n)) ++ ++#define VSDC_FB_CONFIG(n) (0x1518 + 0x4 * (n)) ++#define VSDC_FB_CONFIG_CLEAR_EN BIT(8) ++#define VSDC_FB_CONFIG_ROT_MASK GENMASK(13, 11) ++#define VSDC_FB_CONFIG_ROT(v) ((v) << 11) ++#define VSDC_FB_CONFIG_YUV_SPACE_MASK GENMASK(16, 14) ++#define VSDC_FB_CONFIG_YUV_SPACE(v) ((v) << 14) ++#define VSDC_FB_CONFIG_TILE_MODE_MASK GENMASK(21, 17) ++#define VSDC_FB_CONFIG_TILE_MODE(v) ((v) << 14) ++#define VSDC_FB_CONFIG_SCALE_EN BIT(22) ++#define VSDC_FB_CONFIG_SWIZZLE_MASK GENMASK(24, 23) ++#define VSDC_FB_CONFIG_SWIZZLE(v) ((v) << 23) ++#define VSDC_FB_CONFIG_UV_SWIZZLE_EN BIT(25) ++#define VSDC_FB_CONFIG_FMT_MASK GENMASK(31, 26) ++#define VSDC_FB_CONFIG_FMT(v) ((v) << 26) ++ ++#define VSDC_FB_SIZE(n) (0x1810 + 0x4 * (n)) ++/* Fill with value generated with VSDC_MAKE_PLANE_SIZE(w, h) */ ++ ++#define VSDC_FB_CONFIG_EX(n) (0x1CC0 + 0x4 * (n)) ++#define VSDC_FB_CONFIG_EX_COMMIT BIT(12) ++#define VSDC_FB_CONFIG_EX_FB_EN BIT(13) ++#define VSDC_FB_CONFIG_EX_ZPOS_MASK GENMASK(18, 16) ++#define VSDC_FB_CONFIG_EX_ZPOS(v) ((v) << 16) ++#define VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK GENMASK(19, 19) ++#define VSDC_FB_CONFIG_EX_DISPLAY_ID(v) ((v) << 19) ++ ++#define VSDC_FB_TOP_LEFT(n) (0x24D8 + 0x4 * (n)) ++/* Fill with value generated with VSDC_MAKE_PLANE_POS(x, y) */ ++ ++#define VSDC_FB_BOTTOM_RIGHT(n) (0x24E0 + 0x4 * (n)) ++/* Fill with value generated with VSDC_MAKE_PLANE_POS(x, y) */ ++ ++#define VSDC_FB_BLEND_CONFIG(n) (0x2510 + 0x4 * (n)) ++#define VSDC_FB_BLEND_CONFIG_BLEND_DISABLE BIT(1) ++ ++#endif /* _VS_PRIMARY_PLANE_REGS_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch b/SPECS/linux-lts-kmhv2/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch new file mode 100644 index 0000000000..641e31a30d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch @@ -0,0 +1,153 @@ +From f3c9d099748a9f334530dc8d3b829667282a09e2 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:18 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: display/bridge: add binding for + TH1520 HDMI controller + +T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired +with DesignWare HDMI PHY, with an extra clock gate for HDMI pixel clock +and two reset controls. + +Add a device tree binding to it. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Thomas Zimmermann +Link: https://patch.msgid.link/20260129023922.1527729-5-zhengxingda@iscas.ac.cn +(cherry picked from commit 3d60ff99a78ccd3b72765542dd083b134d6ae4bb) +Signed-off-by: Han Gao +--- + .../display/bridge/thead,th1520-dw-hdmi.yaml | 120 ++++++++++++++++++ + 1 file changed, 120 insertions(+) + create mode 100644 Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml + +diff --git a/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml +new file mode 100644 +index 000000000000..68fff885ce15 +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml +@@ -0,0 +1,120 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/display/bridge/thead,th1520-dw-hdmi.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: T-Head TH1520 DesignWare HDMI TX Encoder ++ ++maintainers: ++ - Icenowy Zheng ++ ++description: ++ The HDMI transmitter is a Synopsys DesignWare HDMI TX controller ++ paired with a DesignWare HDMI Gen2 TX PHY. ++ ++allOf: ++ - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - thead,th1520-dw-hdmi ++ ++ reg-io-width: ++ const: 4 ++ ++ clocks: ++ maxItems: 4 ++ ++ clock-names: ++ items: ++ - const: iahb ++ - const: isfr ++ - const: cec ++ - const: pix ++ ++ resets: ++ items: ++ - description: Main reset ++ - description: Configuration APB reset ++ ++ reset-names: ++ items: ++ - const: main ++ - const: apb ++ ++ ports: ++ $ref: /schemas/graph.yaml#/properties/ports ++ ++ properties: ++ port@0: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: Input port connected to DC8200 DPU "DP" output ++ ++ port@1: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: HDMI output port ++ ++ required: ++ - port@0 ++ - port@1 ++ ++required: ++ - compatible ++ - reg ++ - reg-io-width ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - interrupts ++ - ports ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ hdmi@ffef540000 { ++ compatible = "thead,th1520-dw-hdmi"; ++ reg = <0xff 0xef540000 0x0 0x40000>; ++ reg-io-width = <4>; ++ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_vo CLK_HDMI_PCLK>, ++ <&clk_vo CLK_HDMI_SFR>, ++ <&clk_vo CLK_HDMI_CEC>, ++ <&clk_vo CLK_HDMI_PIXCLK>; ++ clock-names = "iahb", "isfr", "cec", "pix"; ++ resets = <&rst_vo TH1520_RESET_ID_HDMI>, ++ <&rst_vo TH1520_RESET_ID_HDMI_APB>; ++ reset-names = "main", "apb"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ ++ hdmi_in: endpoint { ++ remote-endpoint = <&dpu_out_dp1>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ hdmi_out_conn: endpoint { ++ remote-endpoint = <&hdmi_conn_in>; ++ }; ++ }; ++ }; ++ }; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0192-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch b/SPECS/linux-lts-kmhv2/0192-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch deleted file mode 100644 index feb6510c1b..0000000000 --- a/SPECS/linux-lts-kmhv2/0192-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 34a1f2a285caa0d97a9ec22b7fdad41bc44c6a59 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:15 +0800 -Subject: [PATCH 192/467] UPSTREAM: dt-bindings: vendor-prefixes: add - verisilicon - -VeriSilicon is a Silicon IP vendor, which is the current owner of -Vivante series video-related IPs and Hantro series video codec IPs. - -Add a vendor prefix for this company. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Acked-by: Rob Herring (Arm) -Signed-off-by: Thomas Zimmermann -Link: https://patch.msgid.link/20260129023922.1527729-2-zhengxingda@iscas.ac.cn -(cherry picked from commit c131d78840d7487e41c3afdc52bb74fd3f8861ef) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml -index 647746e6f75f..d03f700d178e 100644 ---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml -+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -1723,6 +1723,8 @@ patternProperties: - description: Variscite Ltd. - "^vdl,.*": - description: Van der Laan b.v. -+ "^verisilicon,.*": -+ description: VeriSilicon Microelectronics (Shanghai) Co., Ltd. - "^vertexcom,.*": - description: Vertexcom Technologies, Inc. - "^via,.*": --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch b/SPECS/linux-lts-kmhv2/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch new file mode 100644 index 0000000000..cf9d00a163 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch @@ -0,0 +1,257 @@ +From 58ad5626c4911a37f2e711c60ae825d55251511b Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:19 +0800 +Subject: [RUYI PATCH] UPSTREAM: drm/bridge: add a driver for T-Head TH1520 + HDMI controller + +T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller (paired +with DesignWare HDMI TX PHY Gen2) that takes the "DP" output from the +display controller. + +Add a driver for this controller utilizing the common DesignWare HDMI +code in the kernel. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Tested-by: Han Gao +Tested-by: Michal Wilczynski +Acked-by: Thomas Zimmermann +Signed-off-by: Thomas Zimmermann +Link: https://patch.msgid.link/20260129023922.1527729-6-zhengxingda@iscas.ac.cn +(cherry picked from commit 96f30ee0fb9db1663eb8fd55c12e4c67da8c4a90) +Signed-off-by: Han Gao +--- + MAINTAINERS | 1 + + drivers/gpu/drm/bridge/Kconfig | 10 ++ + drivers/gpu/drm/bridge/Makefile | 1 + + drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 173 ++++++++++++++++++++++++ + 4 files changed, 185 insertions(+) + create mode 100644 drivers/gpu/drm/bridge/th1520-dw-hdmi.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index b50b6c7a9b52..1509fa6ab229 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -22227,6 +22227,7 @@ F: Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml + F: arch/riscv/boot/dts/thead/ + F: drivers/clk/thead/clk-th1520-ap.c + F: drivers/firmware/thead,th1520-aon.c ++F: drivers/gpu/drm/bridge/th1520-dw-hdmi.c + F: drivers/mailbox/mailbox-th1520.c + F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c + F: drivers/pinctrl/pinctrl-th1520.c +diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig +index a250afd8d662..8e19f5fb9ad7 100644 +--- a/drivers/gpu/drm/bridge/Kconfig ++++ b/drivers/gpu/drm/bridge/Kconfig +@@ -335,6 +335,16 @@ config DRM_THINE_THC63LVD1024 + help + Thine THC63LVD1024 LVDS/parallel converter driver. + ++config DRM_THEAD_TH1520_DW_HDMI ++ tristate "T-Head TH1520 DesignWare HDMI bridge" ++ depends on OF ++ depends on COMMON_CLK ++ depends on ARCH_THEAD || COMPILE_TEST ++ select DRM_DW_HDMI ++ help ++ Choose this to enable support for the internal HDMI bridge found ++ on the T-Head TH1520 SoC. ++ + config DRM_TOSHIBA_TC358762 + tristate "TC358762 DSI/DPI bridge" + depends on OF +diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile +index c7dc03182e59..085b5db45d6f 100644 +--- a/drivers/gpu/drm/bridge/Makefile ++++ b/drivers/gpu/drm/bridge/Makefile +@@ -28,6 +28,7 @@ obj-$(CONFIG_DRM_SII902X) += sii902x.o + obj-$(CONFIG_DRM_SII9234) += sii9234.o + obj-$(CONFIG_DRM_SIMPLE_BRIDGE) += simple-bridge.o + obj-$(CONFIG_DRM_SOLOMON_SSD2825) += ssd2825.o ++obj-$(CONFIG_DRM_THEAD_TH1520_DW_HDMI) += th1520-dw-hdmi.o + obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o + obj-$(CONFIG_DRM_TOSHIBA_TC358762) += tc358762.o + obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o +diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +new file mode 100644 +index 000000000000..389eead5f1c4 +--- /dev/null ++++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +@@ -0,0 +1,173 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on rcar_dw_hdmi.c, which is: ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * Based on imx8mp-hdmi-tx.c, which is: ++ * Copyright (C) 2022 Pengutronix, Lucas Stach ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define TH1520_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */ ++#define TH1520_HDMI_PHY_CKSYMTXCTRL 0x09 /* Clock Symbol and Transmitter Control Register */ ++#define TH1520_HDMI_PHY_VLEVCTRL 0x0e /* Voltage Level Control Register */ ++#define TH1520_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */ ++#define TH1520_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */ ++#define TH1520_HDMI_PHY_TXTERM 0x19 /* Transmission Termination Register */ ++ ++struct th1520_hdmi_phy_params { ++ unsigned long mpixelclock; ++ u16 opmode_pllcfg; ++ u16 pllcurrgmpctrl; ++ u16 plldivctrl; ++ u16 cksymtxctrl; ++ u16 vlevctrl; ++ u16 txterm; ++}; ++ ++static const struct th1520_hdmi_phy_params th1520_hdmi_phy_params[] = { ++ { 35500000, 0x0003, 0x0283, 0x0628, 0x8088, 0x01a0, 0x0007 }, ++ { 44900000, 0x0003, 0x0285, 0x0228, 0x8088, 0x01a0, 0x0007 }, ++ { 71000000, 0x0002, 0x1183, 0x0614, 0x8088, 0x01a0, 0x0007 }, ++ { 90000000, 0x0002, 0x1142, 0x0214, 0x8088, 0x01a0, 0x0007 }, ++ { 121750000, 0x0001, 0x20c0, 0x060a, 0x8088, 0x01a0, 0x0007 }, ++ { 165000000, 0x0001, 0x2080, 0x020a, 0x8088, 0x01a0, 0x0007 }, ++ { 198000000, 0x0000, 0x3040, 0x0605, 0x83c8, 0x0120, 0x0004 }, ++ { 297000000, 0x0000, 0x3041, 0x0205, 0x81dc, 0x0200, 0x0005 }, ++ { 371250000, 0x0640, 0x3041, 0x0205, 0x80f6, 0x0140, 0x0000 }, ++ { 495000000, 0x0640, 0x3080, 0x0005, 0x80f6, 0x0140, 0x0000 }, ++ { 594000000, 0x0640, 0x3080, 0x0005, 0x80fa, 0x01e0, 0x0004 }, ++}; ++ ++struct th1520_hdmi { ++ struct dw_hdmi_plat_data plat_data; ++ struct dw_hdmi *dw_hdmi; ++ struct clk *pixclk; ++ struct reset_control *mainrst, *prst; ++}; ++ ++static enum drm_mode_status ++th1520_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, ++ const struct drm_display_info *info, ++ const struct drm_display_mode *mode) ++{ ++ /* ++ * The maximum supported clock frequency is 594 MHz, as shown in the PHY ++ * parameters table. ++ */ ++ if (mode->clock > 594000) ++ return MODE_CLOCK_HIGH; ++ ++ return MODE_OK; ++} ++ ++static void th1520_hdmi_phy_set_params(struct dw_hdmi *hdmi, ++ const struct th1520_hdmi_phy_params *params) ++{ ++ dw_hdmi_phy_i2c_write(hdmi, params->opmode_pllcfg, ++ TH1520_HDMI_PHY_OPMODE_PLLCFG); ++ dw_hdmi_phy_i2c_write(hdmi, params->pllcurrgmpctrl, ++ TH1520_HDMI_PHY_PLLCURRGMPCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, params->plldivctrl, ++ TH1520_HDMI_PHY_PLLDIVCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, params->vlevctrl, ++ TH1520_HDMI_PHY_VLEVCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, params->cksymtxctrl, ++ TH1520_HDMI_PHY_CKSYMTXCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, params->txterm, ++ TH1520_HDMI_PHY_TXTERM); ++} ++ ++static int th1520_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data, ++ unsigned long mpixelclock) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(th1520_hdmi_phy_params); i++) { ++ if (mpixelclock <= th1520_hdmi_phy_params[i].mpixelclock) { ++ th1520_hdmi_phy_set_params(hdmi, ++ &th1520_hdmi_phy_params[i]); ++ return 0; ++ } ++ } ++ ++ return -EINVAL; ++} ++ ++static int th1520_dw_hdmi_probe(struct platform_device *pdev) ++{ ++ struct th1520_hdmi *hdmi; ++ struct dw_hdmi_plat_data *plat_data; ++ struct device *dev = &pdev->dev; ++ ++ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); ++ if (!hdmi) ++ return -ENOMEM; ++ ++ plat_data = &hdmi->plat_data; ++ ++ hdmi->pixclk = devm_clk_get_enabled(dev, "pix"); ++ if (IS_ERR(hdmi->pixclk)) ++ return dev_err_probe(dev, PTR_ERR(hdmi->pixclk), ++ "Unable to get pixel clock\n"); ++ ++ hdmi->mainrst = devm_reset_control_get_exclusive_deasserted(dev, "main"); ++ if (IS_ERR(hdmi->mainrst)) ++ return dev_err_probe(dev, PTR_ERR(hdmi->mainrst), ++ "Unable to get main reset\n"); ++ ++ hdmi->prst = devm_reset_control_get_exclusive_deasserted(dev, "apb"); ++ if (IS_ERR(hdmi->prst)) ++ return dev_err_probe(dev, PTR_ERR(hdmi->prst), ++ "Unable to get apb reset\n"); ++ ++ plat_data->output_port = 1; ++ plat_data->mode_valid = th1520_hdmi_mode_valid; ++ plat_data->configure_phy = th1520_hdmi_phy_configure; ++ plat_data->priv_data = hdmi; ++ ++ hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); ++ if (IS_ERR(hdmi)) ++ return PTR_ERR(hdmi); ++ ++ platform_set_drvdata(pdev, hdmi); ++ ++ return 0; ++} ++ ++static void th1520_dw_hdmi_remove(struct platform_device *pdev) ++{ ++ struct dw_hdmi *hdmi = platform_get_drvdata(pdev); ++ ++ dw_hdmi_remove(hdmi); ++} ++ ++static const struct of_device_id th1520_dw_hdmi_of_table[] = { ++ { .compatible = "thead,th1520-dw-hdmi" }, ++ { /* Sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, th1520_dw_hdmi_of_table); ++ ++static struct platform_driver th1520_dw_hdmi_platform_driver = { ++ .probe = th1520_dw_hdmi_probe, ++ .remove = th1520_dw_hdmi_remove, ++ .driver = { ++ .name = "th1520-dw-hdmi", ++ .of_match_table = th1520_dw_hdmi_of_table, ++ }, ++}; ++ ++module_platform_driver(th1520_dw_hdmi_platform_driver); ++ ++MODULE_AUTHOR("Icenowy Zheng "); ++MODULE_DESCRIPTION("T-Head TH1520 HDMI Encoder Driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0193-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch b/SPECS/linux-lts-kmhv2/0193-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch deleted file mode 100644 index aa338ea8fe..0000000000 --- a/SPECS/linux-lts-kmhv2/0193-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch +++ /dev/null @@ -1,157 +0,0 @@ -From 0ed3496b3f01c4dd2f8e63571a0b1aaddeb71419 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:16 +0800 -Subject: [PATCH 193/467] UPSTREAM: dt-bindings: display: add verisilicon,dc - -Verisilicon has a series of display controllers prefixed with DC and -with self-identification facility like their GC series GPUs. - -Add a device tree binding for it. - -Depends on the specific DC model, it can have either one or two display -outputs, and each display output could be set to DPI signal or "DP" -signal (which seems to be some plain parallel bus to HDMI controllers). - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Thomas Zimmermann -Link: https://patch.msgid.link/20260129023922.1527729-3-zhengxingda@iscas.ac.cn -(cherry picked from commit 5f6965fa1e2ec8ac69e1d448d343a528dc60cdfb) -Signed-off-by: Han Gao ---- - .../bindings/display/verisilicon,dc.yaml | 122 ++++++++++++++++++ - 1 file changed, 122 insertions(+) - create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml - -diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml -new file mode 100644 -index 000000000000..9dc35ab973f2 ---- /dev/null -+++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml -@@ -0,0 +1,122 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Verisilicon DC-series display controllers -+ -+maintainers: -+ - Icenowy Zheng -+ -+properties: -+ $nodename: -+ pattern: "^display@[0-9a-f]+$" -+ -+ compatible: -+ items: -+ - enum: -+ - thead,th1520-dc8200 -+ - const: verisilicon,dc # DC IPs have discoverable ID/revision registers -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: DC Core clock -+ - description: DMA AXI bus clock -+ - description: Configuration AHB bus clock -+ - description: Pixel clock of output 0 -+ - description: Pixel clock of output 1 -+ -+ clock-names: -+ items: -+ - const: core -+ - const: axi -+ - const: ahb -+ - const: pix0 -+ - const: pix1 -+ -+ resets: -+ items: -+ - description: DC Core reset -+ - description: DMA AXI bus reset -+ - description: Configuration AHB bus reset -+ -+ reset-names: -+ items: -+ - const: core -+ - const: axi -+ - const: ahb -+ -+ ports: -+ $ref: /schemas/graph.yaml#/properties/ports -+ -+ properties: -+ port@0: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: The first output channel , endpoint 0 should be -+ used for DPI format output and endpoint 1 should be used -+ for DP format output. -+ -+ port@1: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: The second output channel if the DC variant -+ supports. Follow the same endpoint addressing rule with -+ the first port. -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - clocks -+ - clock-names -+ - ports -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ display@ffef600000 { -+ compatible = "thead,th1520-dc8200", "verisilicon,dc"; -+ reg = <0xff 0xef600000 0x0 0x100000>; -+ interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_vo CLK_DPU_CCLK>, -+ <&clk_vo CLK_DPU_ACLK>, -+ <&clk_vo CLK_DPU_HCLK>, -+ <&clk_vo CLK_DPU_PIXELCLK0>, -+ <&clk_vo CLK_DPU_PIXELCLK1>; -+ clock-names = "core", "axi", "ahb", "pix0", "pix1"; -+ resets = <&rst TH1520_RESET_ID_DPU_CORE>, -+ <&rst TH1520_RESET_ID_DPU_AXI>, -+ <&rst TH1520_RESET_ID_DPU_AHB>; -+ reset-names = "core", "axi", "ahb"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dpu_out_dp1: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&hdmi_in>; -+ }; -+ }; -+ }; -+ }; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0194-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch b/SPECS/linux-lts-kmhv2/0194-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch deleted file mode 100644 index 8afe0ebfca..0000000000 --- a/SPECS/linux-lts-kmhv2/0194-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch +++ /dev/null @@ -1,2082 +0,0 @@ -From 8c4bdd8a532c94e0c03dff0c3191f51e6d57c008 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:17 +0800 -Subject: [PATCH 194/467] UPSTREAM: drm: verisilicon: add a driver for - Verisilicon display controllers - -This is a from-scratch driver targeting Verisilicon DC-series display -controllers, which feature self-identification functionality like their -GC-series GPUs. - -Only DC8200 is being supported now, and only the main framebuffer is set -up (as the DRM primary plane). Support for more DC models and more -features is my further targets. - -As the display controller is delivered to SoC vendors as a whole part, -this driver does not use component framework and extra bridges inside a -SoC is expected to be implemented as dedicated bridges (this driver -properly supports bridge chaining). - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Tested-by: Han Gao -Tested-by: Michal Wilczynski -Reviewed-by: Thomas Zimmermann -Signed-off-by: Thomas Zimmermann -Link: https://patch.msgid.link/20260129023922.1527729-4-zhengxingda@iscas.ac.cn -(cherry picked from commit dbf21777caa8b8c88c12f7f036b01208fec0d55a) -Signed-off-by: Han Gao ---- - MAINTAINERS | 7 + - drivers/gpu/drm/Kconfig | 2 + - drivers/gpu/drm/Makefile | 1 + - drivers/gpu/drm/verisilicon/Kconfig | 16 + - drivers/gpu/drm/verisilicon/Makefile | 5 + - drivers/gpu/drm/verisilicon/vs_bridge.c | 371 ++++++++++++++++++ - drivers/gpu/drm/verisilicon/vs_bridge.h | 39 ++ - drivers/gpu/drm/verisilicon/vs_bridge_regs.h | 54 +++ - drivers/gpu/drm/verisilicon/vs_crtc.c | 191 +++++++++ - drivers/gpu/drm/verisilicon/vs_crtc.h | 31 ++ - drivers/gpu/drm/verisilicon/vs_crtc_regs.h | 60 +++ - drivers/gpu/drm/verisilicon/vs_dc.c | 207 ++++++++++ - drivers/gpu/drm/verisilicon/vs_dc.h | 38 ++ - drivers/gpu/drm/verisilicon/vs_dc_top_regs.h | 27 ++ - drivers/gpu/drm/verisilicon/vs_drm.c | 182 +++++++++ - drivers/gpu/drm/verisilicon/vs_drm.h | 28 ++ - drivers/gpu/drm/verisilicon/vs_hwdb.c | 150 +++++++ - drivers/gpu/drm/verisilicon/vs_hwdb.h | 29 ++ - drivers/gpu/drm/verisilicon/vs_plane.c | 124 ++++++ - drivers/gpu/drm/verisilicon/vs_plane.h | 72 ++++ - .../gpu/drm/verisilicon/vs_primary_plane.c | 173 ++++++++ - .../drm/verisilicon/vs_primary_plane_regs.h | 53 +++ - 22 files changed, 1860 insertions(+) - create mode 100644 drivers/gpu/drm/verisilicon/Kconfig - create mode 100644 drivers/gpu/drm/verisilicon/Makefile - create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge_regs.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc_regs.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_dc.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_dc.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_top_regs.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_drm.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_drm.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_hwdb.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_hwdb.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_primary_plane.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h - -diff --git a/MAINTAINERS b/MAINTAINERS -index a615f46a6e8d..b50b6c7a9b52 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -8546,6 +8546,13 @@ F: Documentation/devicetree/bindings/display/brcm,bcm2835-*.yaml - F: drivers/gpu/drm/vc4/ - F: include/uapi/drm/vc4_drm.h - -+DRM DRIVERS FOR VERISILICON DISPLAY CONTROLLER IP -+M: Icenowy Zheng -+L: dri-devel@lists.freedesktop.org -+S: Maintained -+F: Documentation/devicetree/bindings/display/verisilicon,dc.yaml -+F: drivers/gpu/drm/verisilicon/ -+ - DRM DRIVERS FOR VIVANTE GPU IP - M: Lucas Stach - R: Russell King -diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig -index ed85d0ceee3b..a0917595d11c 100644 ---- a/drivers/gpu/drm/Kconfig -+++ b/drivers/gpu/drm/Kconfig -@@ -398,6 +398,8 @@ source "drivers/gpu/drm/imagination/Kconfig" - - source "drivers/gpu/drm/tyr/Kconfig" - -+source "drivers/gpu/drm/verisilicon/Kconfig" -+ - config DRM_HYPERV - tristate "DRM Support for Hyper-V synthetic video device" - depends on DRM && PCI && HYPERV_VMBUS -diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile -index b248e64587ed..90eb61d3a823 100644 ---- a/drivers/gpu/drm/Makefile -+++ b/drivers/gpu/drm/Makefile -@@ -235,6 +235,7 @@ obj-y += solomon/ - obj-$(CONFIG_DRM_SPRD) += sprd/ - obj-$(CONFIG_DRM_LOONGSON) += loongson/ - obj-$(CONFIG_DRM_POWERVR) += imagination/ -+obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon/ - - # Ensure drm headers are self-contained and pass kernel-doc - hdrtest-files := \ -diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisilicon/Kconfig -new file mode 100644 -index 000000000000..7cce86ec8603 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/Kconfig -@@ -0,0 +1,16 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+config DRM_VERISILICON_DC -+ tristate "DRM Support for Verisilicon DC-series display controllers" -+ depends on DRM && COMMON_CLK -+ depends on RISCV || COMPILE_TEST -+ select DRM_BRIDGE_CONNECTOR -+ select DRM_CLIENT_SELECTION -+ select DRM_DISPLAY_HELPER -+ select DRM_GEM_DMA_HELPER -+ select DRM_KMS_HELPER -+ select REGMAP_MMIO -+ select VIDEOMODE_HELPERS -+ help -+ Choose this option if you have a SoC with Verisilicon DC-series -+ display controllers. If M is selected, the module will be called -+ verisilicon-dc. -diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile -new file mode 100644 -index 000000000000..fd8d805fbcde ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/Makefile -@@ -0,0 +1,5 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o -+ -+obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o -diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.c b/drivers/gpu/drm/verisilicon/vs_bridge.c -new file mode 100644 -index 000000000000..2a0ad00a94d6 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_bridge.c -@@ -0,0 +1,371 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vs_bridge.h" -+#include "vs_bridge_regs.h" -+#include "vs_crtc.h" -+#include "vs_dc.h" -+ -+static int vs_bridge_attach(struct drm_bridge *bridge, -+ struct drm_encoder *encoder, -+ enum drm_bridge_attach_flags flags) -+{ -+ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); -+ -+ return drm_bridge_attach(encoder, vbridge->next_bridge, -+ bridge, flags); -+} -+ -+struct vsdc_dp_format { -+ u32 linux_fmt; -+ bool is_yuv; -+ u32 vsdc_fmt; -+}; -+ -+static struct vsdc_dp_format vsdc_dp_supported_fmts[] = { -+ /* default to RGB888 */ -+ { MEDIA_BUS_FMT_FIXED, false, VSDC_DISP_DP_CONFIG_FMT_RGB888 }, -+ { MEDIA_BUS_FMT_RGB888_1X24, false, VSDC_DISP_DP_CONFIG_FMT_RGB888 }, -+ { MEDIA_BUS_FMT_RGB565_1X16, false, VSDC_DISP_DP_CONFIG_FMT_RGB565 }, -+ { MEDIA_BUS_FMT_RGB666_1X18, false, VSDC_DISP_DP_CONFIG_FMT_RGB666 }, -+ { MEDIA_BUS_FMT_RGB101010_1X30, -+ false, VSDC_DISP_DP_CONFIG_FMT_RGB101010 }, -+ { MEDIA_BUS_FMT_UYVY8_1X16, true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY8 }, -+ { MEDIA_BUS_FMT_UYVY10_1X20, true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY10 }, -+ { MEDIA_BUS_FMT_YUV8_1X24, true, VSDC_DISP_DP_CONFIG_YUV_FMT_YUV8 }, -+ { MEDIA_BUS_FMT_YUV10_1X30, true, VSDC_DISP_DP_CONFIG_YUV_FMT_YUV10 }, -+ { MEDIA_BUS_FMT_UYYVYY8_0_5X24, -+ true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY8 }, -+ { MEDIA_BUS_FMT_UYYVYY10_0_5X30, -+ true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY10 }, -+}; -+ -+static u32 *vs_bridge_atomic_get_output_bus_fmts_dpi(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ unsigned int *num_output_fmts) -+{ -+ u32 *output_fmts; -+ -+ *num_output_fmts = 2; -+ -+ output_fmts = kcalloc(*num_output_fmts, sizeof(*output_fmts), -+ GFP_KERNEL); -+ if (!output_fmts) -+ return NULL; -+ -+ /* TODO: support more DPI output formats */ -+ output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; -+ output_fmts[1] = MEDIA_BUS_FMT_FIXED; -+ -+ return output_fmts; -+} -+ -+static u32 *vs_bridge_atomic_get_output_bus_fmts_dp(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ unsigned int *num_output_fmts) -+{ -+ u32 *output_fmts; -+ unsigned int i; -+ -+ *num_output_fmts = ARRAY_SIZE(vsdc_dp_supported_fmts); -+ -+ output_fmts = kcalloc(*num_output_fmts, sizeof(*output_fmts), -+ GFP_KERNEL); -+ if (!output_fmts) -+ return NULL; -+ -+ for (i = 0; i < *num_output_fmts; i++) -+ output_fmts[i] = vsdc_dp_supported_fmts[i].linux_fmt; -+ -+ return output_fmts; -+} -+ -+static bool vs_bridge_out_dp_fmt_supported(u32 out_fmt) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(vsdc_dp_supported_fmts); i++) -+ if (vsdc_dp_supported_fmts[i].linux_fmt == out_fmt) -+ return true; -+ -+ return false; -+} -+ -+static u32 *vs_bridge_atomic_get_input_bus_fmts_dp(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ u32 output_fmt, -+ unsigned int *num_input_fmts) -+{ -+ if (!vs_bridge_out_dp_fmt_supported(output_fmt)) { -+ *num_input_fmts = 0; -+ return NULL; -+ } -+ -+ return drm_atomic_helper_bridge_propagate_bus_fmt(bridge, bridge_state, -+ crtc_state, -+ conn_state, -+ output_fmt, -+ num_input_fmts); -+} -+ -+static int vs_bridge_atomic_check_dp(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state) -+{ -+ if (!vs_bridge_out_dp_fmt_supported(bridge_state->output_bus_cfg.format)) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static void vs_bridge_enable_common(struct vs_crtc *crtc, -+ struct drm_bridge_state *br_state) -+{ -+ struct vs_dc *dc = crtc->dc; -+ unsigned int output = crtc->id; -+ -+ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_DAT_POL); -+ regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_DE_POL, -+ br_state->output_bus_cfg.flags & -+ DRM_BUS_FLAG_DE_LOW); -+ regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_CLK_POL, -+ br_state->output_bus_cfg.flags & -+ DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); -+ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_DE_EN | -+ VSDC_DISP_PANEL_CONFIG_DAT_EN | -+ VSDC_DISP_PANEL_CONFIG_CLK_EN); -+ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_RUNNING); -+ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, -+ VSDC_DISP_PANEL_START_MULTI_DISP_SYNC); -+ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START, -+ VSDC_DISP_PANEL_START_RUNNING(output)); -+ -+ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), -+ VSDC_DISP_PANEL_CONFIG_EX_COMMIT); -+} -+ -+static void vs_bridge_atomic_enable_dpi(struct drm_bridge *bridge, -+ struct drm_atomic_state *state) -+{ -+ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); -+ struct drm_bridge_state *br_state = -+ drm_atomic_get_new_bridge_state(state, bridge); -+ struct vs_crtc *crtc = vbridge->crtc; -+ struct vs_dc *dc = crtc->dc; -+ unsigned int output = crtc->id; -+ -+ regmap_clear_bits(dc->regs, VSDC_DISP_DP_CONFIG(output), -+ VSDC_DISP_DP_CONFIG_DP_EN); -+ regmap_write(dc->regs, VSDC_DISP_DPI_CONFIG(output), -+ VSDC_DISP_DPI_CONFIG_FMT_RGB888); -+ -+ vs_bridge_enable_common(crtc, br_state); -+} -+ -+static void vs_bridge_atomic_enable_dp(struct drm_bridge *bridge, -+ struct drm_atomic_state *state) -+{ -+ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); -+ struct drm_bridge_state *br_state = -+ drm_atomic_get_new_bridge_state(state, bridge); -+ struct vs_crtc *crtc = vbridge->crtc; -+ struct vs_dc *dc = crtc->dc; -+ unsigned int output = crtc->id; -+ u32 dp_fmt; -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(vsdc_dp_supported_fmts); i++) { -+ if (vsdc_dp_supported_fmts[i].linux_fmt == -+ br_state->output_bus_cfg.format) -+ break; -+ } -+ if (WARN_ON_ONCE(i == ARRAY_SIZE(vsdc_dp_supported_fmts))) -+ return; -+ dp_fmt = vsdc_dp_supported_fmts[i].vsdc_fmt; -+ dp_fmt |= VSDC_DISP_DP_CONFIG_DP_EN; -+ regmap_write(dc->regs, VSDC_DISP_DP_CONFIG(output), dp_fmt); -+ regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_YUV, -+ vsdc_dp_supported_fmts[i].is_yuv); -+ -+ vs_bridge_enable_common(crtc, br_state); -+} -+ -+static void vs_bridge_atomic_disable(struct drm_bridge *bridge, -+ struct drm_atomic_state *state) -+{ -+ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); -+ struct vs_crtc *crtc = vbridge->crtc; -+ struct vs_dc *dc = crtc->dc; -+ unsigned int output = crtc->id; -+ -+ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, -+ VSDC_DISP_PANEL_START_MULTI_DISP_SYNC | -+ VSDC_DISP_PANEL_START_RUNNING(output)); -+ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_RUNNING); -+ -+ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), -+ VSDC_DISP_PANEL_CONFIG_EX_COMMIT); -+} -+ -+static const struct drm_bridge_funcs vs_dpi_bridge_funcs = { -+ .attach = vs_bridge_attach, -+ .atomic_enable = vs_bridge_atomic_enable_dpi, -+ .atomic_disable = vs_bridge_atomic_disable, -+ .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt, -+ .atomic_get_output_bus_fmts = vs_bridge_atomic_get_output_bus_fmts_dpi, -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_reset = drm_atomic_helper_bridge_reset, -+}; -+ -+static const struct drm_bridge_funcs vs_dp_bridge_funcs = { -+ .attach = vs_bridge_attach, -+ .atomic_enable = vs_bridge_atomic_enable_dp, -+ .atomic_disable = vs_bridge_atomic_disable, -+ .atomic_check = vs_bridge_atomic_check_dp, -+ .atomic_get_input_bus_fmts = vs_bridge_atomic_get_input_bus_fmts_dp, -+ .atomic_get_output_bus_fmts = vs_bridge_atomic_get_output_bus_fmts_dp, -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_reset = drm_atomic_helper_bridge_reset, -+}; -+ -+static int vs_bridge_detect_output_interface(struct device_node *of_node, -+ unsigned int output) -+{ -+ int ret; -+ struct device_node *remote; -+ -+ remote = of_graph_get_remote_node(of_node, output, -+ VSDC_OUTPUT_INTERFACE_DPI); -+ if (remote) { -+ ret = VSDC_OUTPUT_INTERFACE_DPI; -+ } else { -+ remote = of_graph_get_remote_node(of_node, output, -+ VSDC_OUTPUT_INTERFACE_DP); -+ if (remote) -+ ret = VSDC_OUTPUT_INTERFACE_DP; -+ else -+ ret = -ENODEV; -+ } -+ -+ if (remote) -+ of_node_put(remote); -+ -+ return ret; -+} -+ -+struct vs_bridge *vs_bridge_init(struct drm_device *drm_dev, -+ struct vs_crtc *crtc) -+{ -+ unsigned int output = crtc->id; -+ struct vs_bridge *bridge; -+ struct drm_bridge *next; -+ enum vs_bridge_output_interface intf; -+ const struct drm_bridge_funcs *bridge_funcs; -+ int ret, enctype; -+ -+ intf = vs_bridge_detect_output_interface(drm_dev->dev->of_node, -+ output); -+ if (intf == -ENODEV) { -+ drm_dbg(drm_dev, "Skipping output %u\n", output); -+ return NULL; -+ } -+ -+ next = devm_drm_of_get_bridge(drm_dev->dev, drm_dev->dev->of_node, -+ output, intf); -+ if (IS_ERR(next)) { -+ ret = PTR_ERR(next); -+ if (ret != -EPROBE_DEFER) -+ drm_err(drm_dev, -+ "Cannot get downstream bridge of output %u\n", -+ output); -+ return ERR_PTR(ret); -+ } -+ -+ if (intf == VSDC_OUTPUT_INTERFACE_DPI) -+ bridge_funcs = &vs_dpi_bridge_funcs; -+ else -+ bridge_funcs = &vs_dp_bridge_funcs; -+ -+ bridge = devm_drm_bridge_alloc(drm_dev->dev, struct vs_bridge, base, -+ bridge_funcs); -+ if (IS_ERR(bridge)) -+ return ERR_PTR(PTR_ERR(bridge)); -+ -+ bridge->crtc = crtc; -+ bridge->intf = intf; -+ bridge->next_bridge = next; -+ -+ if (intf == VSDC_OUTPUT_INTERFACE_DPI) -+ enctype = DRM_MODE_ENCODER_DPI; -+ else -+ enctype = DRM_MODE_ENCODER_NONE; -+ -+ bridge->enc = drmm_plain_encoder_alloc(drm_dev, NULL, enctype, NULL); -+ if (IS_ERR(bridge->enc)) { -+ drm_err(drm_dev, -+ "Cannot initialize encoder for output %u\n", output); -+ ret = PTR_ERR(bridge->enc); -+ return ERR_PTR(ret); -+ } -+ -+ bridge->enc->possible_crtcs = drm_crtc_mask(&crtc->base); -+ -+ ret = devm_drm_bridge_add(drm_dev->dev, &bridge->base); -+ if (ret) { -+ drm_err(drm_dev, -+ "Cannot add bridge for output %u\n", output); -+ return ERR_PTR(ret); -+ } -+ -+ ret = drm_bridge_attach(bridge->enc, &bridge->base, NULL, -+ DRM_BRIDGE_ATTACH_NO_CONNECTOR); -+ if (ret) { -+ drm_err(drm_dev, -+ "Cannot attach bridge for output %u\n", output); -+ return ERR_PTR(ret); -+ } -+ -+ bridge->conn = drm_bridge_connector_init(drm_dev, bridge->enc); -+ if (IS_ERR(bridge->conn)) { -+ drm_err(drm_dev, -+ "Cannot create connector for output %u\n", output); -+ ret = PTR_ERR(bridge->conn); -+ return ERR_PTR(ret); -+ } -+ drm_connector_attach_encoder(bridge->conn, bridge->enc); -+ -+ return bridge; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.h b/drivers/gpu/drm/verisilicon/vs_bridge.h -new file mode 100644 -index 000000000000..70fee1749699 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_bridge.h -@@ -0,0 +1,39 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#ifndef _VS_BRIDGE_H_ -+#define _VS_BRIDGE_H_ -+ -+#include -+ -+#include -+#include -+#include -+ -+struct vs_crtc; -+ -+enum vs_bridge_output_interface { -+ VSDC_OUTPUT_INTERFACE_DPI = 0, -+ VSDC_OUTPUT_INTERFACE_DP = 1 -+}; -+ -+struct vs_bridge { -+ struct drm_bridge base; -+ struct drm_encoder *enc; -+ struct drm_connector *conn; -+ -+ struct vs_crtc *crtc; -+ struct drm_bridge *next_bridge; -+ enum vs_bridge_output_interface intf; -+}; -+ -+static inline struct vs_bridge *drm_bridge_to_vs_bridge(struct drm_bridge *bridge) -+{ -+ return container_of(bridge, struct vs_bridge, base); -+} -+ -+struct vs_bridge *vs_bridge_init(struct drm_device *drm_dev, -+ struct vs_crtc *crtc); -+#endif /* _VS_BRIDGE_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_bridge_regs.h b/drivers/gpu/drm/verisilicon/vs_bridge_regs.h -new file mode 100644 -index 000000000000..9eb30e4564be ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_bridge_regs.h -@@ -0,0 +1,54 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_BRIDGE_REGS_H_ -+#define _VS_BRIDGE_REGS_H_ -+ -+#include -+ -+#define VSDC_DISP_PANEL_CONFIG(n) (0x1418 + 0x4 * (n)) -+#define VSDC_DISP_PANEL_CONFIG_DE_EN BIT(0) -+#define VSDC_DISP_PANEL_CONFIG_DE_POL BIT(1) -+#define VSDC_DISP_PANEL_CONFIG_DAT_EN BIT(4) -+#define VSDC_DISP_PANEL_CONFIG_DAT_POL BIT(5) -+#define VSDC_DISP_PANEL_CONFIG_CLK_EN BIT(8) -+#define VSDC_DISP_PANEL_CONFIG_CLK_POL BIT(9) -+#define VSDC_DISP_PANEL_CONFIG_RUNNING BIT(12) -+#define VSDC_DISP_PANEL_CONFIG_GAMMA BIT(13) -+#define VSDC_DISP_PANEL_CONFIG_YUV BIT(16) -+ -+#define VSDC_DISP_DPI_CONFIG(n) (0x14B8 + 0x4 * (n)) -+#define VSDC_DISP_DPI_CONFIG_FMT_MASK GENMASK(2, 0) -+#define VSDC_DISP_DPI_CONFIG_FMT_RGB565 (0) -+#define VSDC_DISP_DPI_CONFIG_FMT_RGB666 (3) -+#define VSDC_DISP_DPI_CONFIG_FMT_RGB888 (5) -+#define VSDC_DISP_DPI_CONFIG_FMT_RGB101010 (6) -+ -+#define VSDC_DISP_PANEL_START 0x1CCC -+#define VSDC_DISP_PANEL_START_RUNNING(n) BIT(n) -+#define VSDC_DISP_PANEL_START_MULTI_DISP_SYNC BIT(3) -+ -+#define VSDC_DISP_DP_CONFIG(n) (0x1CD0 + 0x4 * (n)) -+#define VSDC_DISP_DP_CONFIG_DP_EN BIT(3) -+#define VSDC_DISP_DP_CONFIG_FMT_MASK GENMASK(2, 0) -+#define VSDC_DISP_DP_CONFIG_FMT_RGB565 (0) -+#define VSDC_DISP_DP_CONFIG_FMT_RGB666 (1) -+#define VSDC_DISP_DP_CONFIG_FMT_RGB888 (2) -+#define VSDC_DISP_DP_CONFIG_FMT_RGB101010 (3) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_MASK GENMASK(7, 4) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY8 (2 << 4) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_YUV8 (4 << 4) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY10 (8 << 4) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_YUV10 (10 << 4) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY8 (12 << 4) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY10 (13 << 4) -+ -+#define VSDC_DISP_PANEL_CONFIG_EX(n) (0x2518 + 0x4 * (n)) -+#define VSDC_DISP_PANEL_CONFIG_EX_COMMIT BIT(0) -+ -+#endif /* _VS_BRIDGE_REGS_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisilicon/vs_crtc.c -new file mode 100644 -index 000000000000..f49401713000 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_crtc.c -@@ -0,0 +1,191 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "vs_crtc_regs.h" -+#include "vs_crtc.h" -+#include "vs_dc.h" -+#include "vs_dc_top_regs.h" -+#include "vs_drm.h" -+#include "vs_plane.h" -+ -+static void vs_crtc_atomic_disable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ unsigned int output = vcrtc->id; -+ -+ drm_crtc_vblank_off(crtc); -+ -+ clk_disable_unprepare(dc->pix_clk[output]); -+} -+ -+static void vs_crtc_atomic_enable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ unsigned int output = vcrtc->id; -+ -+ drm_WARN_ON(&dc->drm_dev->base, -+ clk_prepare_enable(dc->pix_clk[output])); -+ -+ drm_crtc_vblank_on(crtc); -+} -+ -+static void vs_crtc_mode_set_nofb(struct drm_crtc *crtc) -+{ -+ struct drm_display_mode *mode = &crtc->state->adjusted_mode; -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ unsigned int output = vcrtc->id; -+ -+ regmap_write(dc->regs, VSDC_DISP_HSIZE(output), -+ VSDC_DISP_HSIZE_DISP(mode->hdisplay) | -+ VSDC_DISP_HSIZE_TOTAL(mode->htotal)); -+ regmap_write(dc->regs, VSDC_DISP_VSIZE(output), -+ VSDC_DISP_VSIZE_DISP(mode->vdisplay) | -+ VSDC_DISP_VSIZE_TOTAL(mode->vtotal)); -+ regmap_write(dc->regs, VSDC_DISP_HSYNC(output), -+ VSDC_DISP_HSYNC_START(mode->hsync_start) | -+ VSDC_DISP_HSYNC_END(mode->hsync_end) | -+ VSDC_DISP_HSYNC_EN); -+ if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) -+ regmap_set_bits(dc->regs, VSDC_DISP_HSYNC(output), -+ VSDC_DISP_HSYNC_POL); -+ regmap_write(dc->regs, VSDC_DISP_VSYNC(output), -+ VSDC_DISP_VSYNC_START(mode->vsync_start) | -+ VSDC_DISP_VSYNC_END(mode->vsync_end) | -+ VSDC_DISP_VSYNC_EN); -+ if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) -+ regmap_set_bits(dc->regs, VSDC_DISP_VSYNC(output), -+ VSDC_DISP_VSYNC_POL); -+ -+ WARN_ON(clk_set_rate(dc->pix_clk[output], mode->crtc_clock * 1000)); -+} -+ -+static enum drm_mode_status -+vs_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) -+{ -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ unsigned int output = vcrtc->id; -+ long rate; -+ -+ if (mode->htotal > VSDC_DISP_TIMING_VALUE_MAX) -+ return MODE_BAD_HVALUE; -+ if (mode->vtotal > VSDC_DISP_TIMING_VALUE_MAX) -+ return MODE_BAD_VVALUE; -+ -+ rate = clk_round_rate(dc->pix_clk[output], mode->clock * HZ_PER_KHZ); -+ if (rate <= 0) -+ return MODE_CLOCK_RANGE; -+ -+ return MODE_OK; -+} -+ -+static bool vs_crtc_mode_fixup(struct drm_crtc *crtc, -+ const struct drm_display_mode *m, -+ struct drm_display_mode *adjusted_mode) -+{ -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ unsigned int output = vcrtc->id; -+ long clk_rate; -+ -+ drm_mode_set_crtcinfo(adjusted_mode, 0); -+ -+ /* Feedback the pixel clock to crtc_clock */ -+ clk_rate = adjusted_mode->crtc_clock * HZ_PER_KHZ; -+ clk_rate = clk_round_rate(dc->pix_clk[output], clk_rate); -+ if (clk_rate <= 0) -+ return false; -+ -+ adjusted_mode->crtc_clock = clk_rate / HZ_PER_KHZ; -+ -+ return true; -+} -+ -+static const struct drm_crtc_helper_funcs vs_crtc_helper_funcs = { -+ .atomic_flush = drm_crtc_vblank_atomic_flush, -+ .atomic_enable = vs_crtc_atomic_enable, -+ .atomic_disable = vs_crtc_atomic_disable, -+ .mode_set_nofb = vs_crtc_mode_set_nofb, -+ .mode_valid = vs_crtc_mode_valid, -+ .mode_fixup = vs_crtc_mode_fixup, -+}; -+ -+static int vs_crtc_enable_vblank(struct drm_crtc *crtc) -+{ -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id)); -+ -+ return 0; -+} -+ -+static void vs_crtc_disable_vblank(struct drm_crtc *crtc) -+{ -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_clear_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id)); -+} -+ -+static const struct drm_crtc_funcs vs_crtc_funcs = { -+ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, -+ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, -+ .page_flip = drm_atomic_helper_page_flip, -+ .reset = drm_atomic_helper_crtc_reset, -+ .set_config = drm_atomic_helper_set_config, -+ .enable_vblank = vs_crtc_enable_vblank, -+ .disable_vblank = vs_crtc_disable_vblank, -+}; -+ -+struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, -+ unsigned int output) -+{ -+ struct vs_crtc *vcrtc; -+ struct drm_plane *primary; -+ int ret; -+ -+ vcrtc = drmm_kzalloc(drm_dev, sizeof(*vcrtc), GFP_KERNEL); -+ if (!vcrtc) -+ return ERR_PTR(-ENOMEM); -+ vcrtc->dc = dc; -+ vcrtc->id = output; -+ -+ /* Create our primary plane */ -+ primary = vs_primary_plane_init(drm_dev, dc); -+ if (IS_ERR(primary)) { -+ drm_err(drm_dev, "Couldn't create the primary plane\n"); -+ return ERR_PTR(PTR_ERR(primary)); -+ } -+ -+ ret = drmm_crtc_init_with_planes(drm_dev, &vcrtc->base, -+ primary, -+ NULL, -+ &vs_crtc_funcs, -+ NULL); -+ if (ret) { -+ drm_err(drm_dev, "Couldn't initialize CRTC\n"); -+ return ERR_PTR(ret); -+ } -+ -+ drm_crtc_helper_add(&vcrtc->base, &vs_crtc_helper_funcs); -+ -+ return vcrtc; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.h b/drivers/gpu/drm/verisilicon/vs_crtc.h -new file mode 100644 -index 000000000000..b45580bd99b3 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_crtc.h -@@ -0,0 +1,31 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#ifndef _VS_CRTC_H_ -+#define _VS_CRTC_H_ -+ -+#include -+#include -+ -+#define VSDC_DISP_TIMING_VALUE_MAX BIT_MASK(15) -+ -+struct vs_dc; -+ -+struct vs_crtc { -+ struct drm_crtc base; -+ -+ struct vs_dc *dc; -+ unsigned int id; -+}; -+ -+static inline struct vs_crtc *drm_crtc_to_vs_crtc(struct drm_crtc *crtc) -+{ -+ return container_of(crtc, struct vs_crtc, base); -+} -+ -+struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, -+ unsigned int output); -+ -+#endif /* _VS_CRTC_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h -new file mode 100644 -index 000000000000..c7930e817635 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h -@@ -0,0 +1,60 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_CRTC_REGS_H_ -+#define _VS_CRTC_REGS_H_ -+ -+#include -+ -+#define VSDC_DISP_DITHER_CONFIG(n) (0x1410 + 0x4 * (n)) -+ -+#define VSDC_DISP_DITHER_TABLE_LOW(n) (0x1420 + 0x4 * (n)) -+#define VSDC_DISP_DITHER_TABLE_LOW_DEFAULT 0x7B48F3C0 -+ -+#define VSDC_DISP_DITHER_TABLE_HIGH(n) (0x1428 + 0x4 * (n)) -+#define VSDC_DISP_DITHER_TABLE_HIGH_DEFAULT 0x596AD1E2 -+ -+#define VSDC_DISP_HSIZE(n) (0x1430 + 0x4 * (n)) -+#define VSDC_DISP_HSIZE_DISP_MASK GENMASK(14, 0) -+#define VSDC_DISP_HSIZE_DISP(v) ((v) << 0) -+#define VSDC_DISP_HSIZE_TOTAL_MASK GENMASK(30, 16) -+#define VSDC_DISP_HSIZE_TOTAL(v) ((v) << 16) -+ -+#define VSDC_DISP_HSYNC(n) (0x1438 + 0x4 * (n)) -+#define VSDC_DISP_HSYNC_START_MASK GENMASK(14, 0) -+#define VSDC_DISP_HSYNC_START(v) ((v) << 0) -+#define VSDC_DISP_HSYNC_END_MASK GENMASK(29, 15) -+#define VSDC_DISP_HSYNC_END(v) ((v) << 15) -+#define VSDC_DISP_HSYNC_EN BIT(30) -+#define VSDC_DISP_HSYNC_POL BIT(31) -+ -+#define VSDC_DISP_VSIZE(n) (0x1440 + 0x4 * (n)) -+#define VSDC_DISP_VSIZE_DISP_MASK GENMASK(14, 0) -+#define VSDC_DISP_VSIZE_DISP(v) ((v) << 0) -+#define VSDC_DISP_VSIZE_TOTAL_MASK GENMASK(30, 16) -+#define VSDC_DISP_VSIZE_TOTAL(v) ((v) << 16) -+ -+#define VSDC_DISP_VSYNC(n) (0x1448 + 0x4 * (n)) -+#define VSDC_DISP_VSYNC_START_MASK GENMASK(14, 0) -+#define VSDC_DISP_VSYNC_START(v) ((v) << 0) -+#define VSDC_DISP_VSYNC_END_MASK GENMASK(29, 15) -+#define VSDC_DISP_VSYNC_END(v) ((v) << 15) -+#define VSDC_DISP_VSYNC_EN BIT(30) -+#define VSDC_DISP_VSYNC_POL BIT(31) -+ -+#define VSDC_DISP_CURRENT_LOCATION(n) (0x1450 + 0x4 * (n)) -+ -+#define VSDC_DISP_GAMMA_INDEX(n) (0x1458 + 0x4 * (n)) -+ -+#define VSDC_DISP_GAMMA_DATA(n) (0x1460 + 0x4 * (n)) -+ -+#define VSDC_DISP_IRQ_STA 0x147C -+ -+#define VSDC_DISP_IRQ_EN 0x1480 -+ -+#endif /* _VS_CRTC_REGS_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c -new file mode 100644 -index 000000000000..ba1b3f261a3a ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_dc.c -@@ -0,0 +1,207 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "vs_crtc.h" -+#include "vs_dc.h" -+#include "vs_dc_top_regs.h" -+#include "vs_drm.h" -+#include "vs_hwdb.h" -+ -+static const struct regmap_config vs_dc_regmap_cfg = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = sizeof(u32), -+ /* VSDC_OVL_CONFIG_EX(1) */ -+ .max_register = 0x2544, -+}; -+ -+static const struct of_device_id vs_dc_driver_dt_match[] = { -+ { .compatible = "verisilicon,dc" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, vs_dc_driver_dt_match); -+ -+static irqreturn_t vs_dc_irq_handler(int irq, void *private) -+{ -+ struct vs_dc *dc = private; -+ u32 irqs; -+ -+ regmap_read(dc->regs, VSDC_TOP_IRQ_ACK, &irqs); -+ -+ vs_drm_handle_irq(dc, irqs); -+ -+ return IRQ_HANDLED; -+} -+ -+static int vs_dc_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct vs_dc *dc; -+ void __iomem *regs; -+ unsigned int port_count, i; -+ /* pix0/pix1 */ -+ char pixclk_name[5]; -+ int irq, ret; -+ -+ if (!dev->of_node) { -+ dev_err(dev, "can't find DC devices\n"); -+ return -ENODEV; -+ } -+ -+ port_count = of_graph_get_port_count(dev->of_node); -+ if (!port_count) { -+ dev_err(dev, "can't find DC downstream ports\n"); -+ return -ENODEV; -+ } -+ if (port_count > VSDC_MAX_OUTPUTS) { -+ dev_err(dev, "too many DC downstream ports than possible\n"); -+ return -EINVAL; -+ } -+ -+ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); -+ if (ret) { -+ dev_err(dev, "No suitable DMA available\n"); -+ return ret; -+ } -+ -+ dc = devm_kzalloc(dev, sizeof(*dc), GFP_KERNEL); -+ if (!dc) -+ return -ENOMEM; -+ -+ dc->rsts[0].id = "core"; -+ dc->rsts[1].id = "axi"; -+ dc->rsts[2].id = "ahb"; -+ -+ ret = devm_reset_control_bulk_get_optional_shared(dev, VSDC_RESET_COUNT, -+ dc->rsts); -+ if (ret) { -+ dev_err(dev, "can't get reset lines\n"); -+ return ret; -+ } -+ -+ dc->core_clk = devm_clk_get_enabled(dev, "core"); -+ if (IS_ERR(dc->core_clk)) { -+ dev_err(dev, "can't get core clock\n"); -+ return PTR_ERR(dc->core_clk); -+ } -+ -+ dc->axi_clk = devm_clk_get_enabled(dev, "axi"); -+ if (IS_ERR(dc->axi_clk)) { -+ dev_err(dev, "can't get axi clock\n"); -+ return PTR_ERR(dc->axi_clk); -+ } -+ -+ dc->ahb_clk = devm_clk_get_enabled(dev, "ahb"); -+ if (IS_ERR(dc->ahb_clk)) { -+ dev_err(dev, "can't get ahb clock\n"); -+ return PTR_ERR(dc->ahb_clk); -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) { -+ dev_err(dev, "can't get irq\n"); -+ return irq; -+ } -+ -+ ret = reset_control_bulk_deassert(VSDC_RESET_COUNT, dc->rsts); -+ if (ret) { -+ dev_err(dev, "can't deassert reset lines\n"); -+ return ret; -+ } -+ -+ regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(regs)) { -+ dev_err(dev, "can't map registers"); -+ ret = PTR_ERR(regs); -+ goto err_rst_assert; -+ } -+ -+ dc->regs = devm_regmap_init_mmio(dev, regs, &vs_dc_regmap_cfg); -+ if (IS_ERR(dc->regs)) { -+ ret = PTR_ERR(dc->regs); -+ goto err_rst_assert; -+ } -+ -+ ret = vs_fill_chip_identity(dc->regs, &dc->identity); -+ if (ret) -+ goto err_rst_assert; -+ -+ dev_info(dev, "Found DC%x rev %x customer %x\n", dc->identity.model, -+ dc->identity.revision, dc->identity.customer_id); -+ -+ if (port_count > dc->identity.display_count) { -+ dev_err(dev, "too many downstream ports than HW capability\n"); -+ ret = -EINVAL; -+ goto err_rst_assert; -+ } -+ -+ for (i = 0; i < dc->identity.display_count; i++) { -+ snprintf(pixclk_name, sizeof(pixclk_name), "pix%u", i); -+ dc->pix_clk[i] = devm_clk_get(dev, pixclk_name); -+ if (IS_ERR(dc->pix_clk[i])) { -+ dev_err(dev, "can't get pixel clk %u\n", i); -+ ret = PTR_ERR(dc->pix_clk[i]); -+ goto err_rst_assert; -+ } -+ } -+ -+ ret = devm_request_irq(dev, irq, vs_dc_irq_handler, 0, -+ dev_name(dev), dc); -+ if (ret) { -+ dev_err(dev, "can't request irq\n"); -+ goto err_rst_assert; -+ } -+ -+ dev_set_drvdata(dev, dc); -+ -+ ret = vs_drm_initialize(dc, pdev); -+ if (ret) -+ goto err_rst_assert; -+ -+ return 0; -+ -+err_rst_assert: -+ reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); -+ return ret; -+} -+ -+static void vs_dc_remove(struct platform_device *pdev) -+{ -+ struct vs_dc *dc = dev_get_drvdata(&pdev->dev); -+ -+ vs_drm_finalize(dc); -+ -+ dev_set_drvdata(&pdev->dev, NULL); -+ -+ reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); -+} -+ -+static void vs_dc_shutdown(struct platform_device *pdev) -+{ -+ struct vs_dc *dc = dev_get_drvdata(&pdev->dev); -+ -+ vs_drm_shutdown_handler(dc); -+} -+ -+struct platform_driver vs_dc_platform_driver = { -+ .probe = vs_dc_probe, -+ .remove = vs_dc_remove, -+ .shutdown = vs_dc_shutdown, -+ .driver = { -+ .name = "verisilicon-dc", -+ .of_match_table = vs_dc_driver_dt_match, -+ }, -+}; -+ -+module_platform_driver(vs_dc_platform_driver); -+ -+MODULE_AUTHOR("Icenowy Zheng "); -+MODULE_DESCRIPTION("Verisilicon display controller driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h b/drivers/gpu/drm/verisilicon/vs_dc.h -new file mode 100644 -index 000000000000..ed1016f18758 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_dc.h -@@ -0,0 +1,38 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_DC_H_ -+#define _VS_DC_H_ -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "vs_hwdb.h" -+ -+#define VSDC_MAX_OUTPUTS 2 -+#define VSDC_RESET_COUNT 3 -+ -+struct vs_drm_dev; -+struct vs_crtc; -+ -+struct vs_dc { -+ struct regmap *regs; -+ struct clk *core_clk; -+ struct clk *axi_clk; -+ struct clk *ahb_clk; -+ struct clk *pix_clk[VSDC_MAX_OUTPUTS]; -+ struct reset_control_bulk_data rsts[VSDC_RESET_COUNT]; -+ -+ struct vs_drm_dev *drm_dev; -+ struct vs_chip_identity identity; -+}; -+ -+#endif /* _VS_DC_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h b/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h -new file mode 100644 -index 000000000000..50509bbbff08 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h -@@ -0,0 +1,27 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_DC_TOP_H_ -+#define _VS_DC_TOP_H_ -+ -+#include -+ -+#define VSDC_TOP_RST 0x0000 -+ -+#define VSDC_TOP_IRQ_ACK 0x0010 -+#define VSDC_TOP_IRQ_VSYNC(n) BIT(n) -+ -+#define VSDC_TOP_IRQ_EN 0x0014 -+ -+#define VSDC_TOP_CHIP_MODEL 0x0020 -+ -+#define VSDC_TOP_CHIP_REV 0x0024 -+ -+#define VSDC_TOP_CHIP_CUSTOMER_ID 0x0030 -+ -+#endif /* _VS_DC_TOP_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_drm.c b/drivers/gpu/drm/verisilicon/vs_drm.c -new file mode 100644 -index 000000000000..fd259d53f49f ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_drm.c -@@ -0,0 +1,182 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vs_bridge.h" -+#include "vs_crtc.h" -+#include "vs_dc.h" -+#include "vs_dc_top_regs.h" -+#include "vs_drm.h" -+ -+#define DRIVER_NAME "verisilicon" -+#define DRIVER_DESC "Verisilicon DC-series display controller driver" -+#define DRIVER_MAJOR 1 -+#define DRIVER_MINOR 0 -+ -+static int vs_gem_dumb_create(struct drm_file *file_priv, -+ struct drm_device *drm, -+ struct drm_mode_create_dumb *args) -+{ -+ int ret; -+ -+ /* The hardware wants 128B-aligned pitches for linear buffers. */ -+ ret = drm_mode_size_dumb(drm, args, 128, 0); -+ if (ret) -+ return ret; -+ -+ return drm_gem_dma_dumb_create_internal(file_priv, drm, args); -+} -+ -+DEFINE_DRM_GEM_FOPS(vs_drm_driver_fops); -+ -+static const struct drm_driver vs_drm_driver = { -+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, -+ .fops = &vs_drm_driver_fops, -+ .name = DRIVER_NAME, -+ .desc = DRIVER_DESC, -+ .major = DRIVER_MAJOR, -+ .minor = DRIVER_MINOR, -+ -+ /* GEM Operations */ -+ DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(vs_gem_dumb_create), -+ DRM_FBDEV_DMA_DRIVER_OPS, -+}; -+ -+static const struct drm_mode_config_funcs vs_mode_config_funcs = { -+ .fb_create = drm_gem_fb_create, -+ .atomic_check = drm_atomic_helper_check, -+ .atomic_commit = drm_atomic_helper_commit, -+}; -+ -+static struct drm_mode_config_helper_funcs vs_mode_config_helper_funcs = { -+ .atomic_commit_tail = drm_atomic_helper_commit_tail, -+}; -+ -+static void vs_mode_config_init(struct drm_device *drm) -+{ -+ drm->mode_config.min_width = 0; -+ drm->mode_config.min_height = 0; -+ drm->mode_config.max_width = 8192; -+ drm->mode_config.max_height = 8192; -+ drm->mode_config.funcs = &vs_mode_config_funcs; -+ drm->mode_config.helper_private = &vs_mode_config_helper_funcs; -+} -+ -+int vs_drm_initialize(struct vs_dc *dc, struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct vs_drm_dev *vdrm; -+ struct drm_device *drm; -+ struct vs_crtc *crtc; -+ struct vs_bridge *bridge; -+ unsigned int i; -+ int ret; -+ -+ vdrm = devm_drm_dev_alloc(dev, &vs_drm_driver, struct vs_drm_dev, base); -+ if (IS_ERR(vdrm)) -+ return PTR_ERR(vdrm); -+ -+ drm = &vdrm->base; -+ vdrm->dc = dc; -+ dc->drm_dev = vdrm; -+ -+ ret = drmm_mode_config_init(drm); -+ if (ret) -+ return ret; -+ -+ /* Remove early framebuffers (ie. simple-framebuffer) */ -+ ret = aperture_remove_all_conflicting_devices(DRIVER_NAME); -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < dc->identity.display_count; i++) { -+ crtc = vs_crtc_init(drm, dc, i); -+ if (IS_ERR(crtc)) -+ return PTR_ERR(crtc); -+ -+ bridge = vs_bridge_init(drm, crtc); -+ if (IS_ERR(bridge)) -+ return PTR_ERR(bridge); -+ -+ vdrm->crtcs[i] = crtc; -+ } -+ -+ ret = drm_vblank_init(drm, dc->identity.display_count); -+ if (ret) -+ return ret; -+ -+ vs_mode_config_init(drm); -+ -+ /* Enable connectors polling */ -+ drm_kms_helper_poll_init(drm); -+ -+ drm_mode_config_reset(drm); -+ -+ ret = drm_dev_register(drm, 0); -+ if (ret) -+ goto err_fini_poll; -+ -+ drm_client_setup(drm, NULL); -+ -+ return 0; -+ -+err_fini_poll: -+ drm_kms_helper_poll_fini(drm); -+ return ret; -+} -+ -+void vs_drm_finalize(struct vs_dc *dc) -+{ -+ struct vs_drm_dev *vdrm = dc->drm_dev; -+ struct drm_device *drm = &vdrm->base; -+ -+ drm_dev_unregister(drm); -+ drm_kms_helper_poll_fini(drm); -+ drm_atomic_helper_shutdown(drm); -+ dc->drm_dev = NULL; -+} -+ -+void vs_drm_shutdown_handler(struct vs_dc *dc) -+{ -+ struct vs_drm_dev *vdrm = dc->drm_dev; -+ -+ drm_atomic_helper_shutdown(&vdrm->base); -+} -+ -+void vs_drm_handle_irq(struct vs_dc *dc, u32 irqs) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < dc->identity.display_count; i++) { -+ if (irqs & VSDC_TOP_IRQ_VSYNC(i)) { -+ irqs &= ~VSDC_TOP_IRQ_VSYNC(i); -+ if (dc->drm_dev->crtcs[i]) -+ drm_crtc_handle_vblank(&dc->drm_dev->crtcs[i]->base); -+ } -+ } -+ -+ if (irqs) -+ drm_warn_once(&dc->drm_dev->base, -+ "Unknown Verisilicon DC interrupt 0x%x fired!\n", -+ irqs); -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_drm.h b/drivers/gpu/drm/verisilicon/vs_drm.h -new file mode 100644 -index 000000000000..606338206a42 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_drm.h -@@ -0,0 +1,28 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#ifndef _VS_DRM_H_ -+#define _VS_DRM_H_ -+ -+#include -+#include -+ -+#include -+ -+struct vs_dc; -+ -+struct vs_drm_dev { -+ struct drm_device base; -+ -+ struct vs_dc *dc; -+ struct vs_crtc *crtcs[VSDC_MAX_OUTPUTS]; -+}; -+ -+int vs_drm_initialize(struct vs_dc *dc, struct platform_device *pdev); -+void vs_drm_finalize(struct vs_dc *dc); -+void vs_drm_shutdown_handler(struct vs_dc *dc); -+void vs_drm_handle_irq(struct vs_dc *dc, u32 irqs); -+ -+#endif /* _VS_DRM_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisilicon/vs_hwdb.c -new file mode 100644 -index 000000000000..09336af0900a ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c -@@ -0,0 +1,150 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+ -+#include -+ -+#include "vs_dc_top_regs.h" -+#include "vs_hwdb.h" -+ -+static const u32 vs_formats_array_no_yuv444[] = { -+ DRM_FORMAT_XRGB4444, -+ DRM_FORMAT_XBGR4444, -+ DRM_FORMAT_RGBX4444, -+ DRM_FORMAT_BGRX4444, -+ DRM_FORMAT_ARGB4444, -+ DRM_FORMAT_ABGR4444, -+ DRM_FORMAT_RGBA4444, -+ DRM_FORMAT_BGRA4444, -+ DRM_FORMAT_XRGB1555, -+ DRM_FORMAT_XBGR1555, -+ DRM_FORMAT_RGBX5551, -+ DRM_FORMAT_BGRX5551, -+ DRM_FORMAT_ARGB1555, -+ DRM_FORMAT_ABGR1555, -+ DRM_FORMAT_RGBA5551, -+ DRM_FORMAT_BGRA5551, -+ DRM_FORMAT_RGB565, -+ DRM_FORMAT_BGR565, -+ DRM_FORMAT_XRGB8888, -+ DRM_FORMAT_XBGR8888, -+ DRM_FORMAT_RGBX8888, -+ DRM_FORMAT_BGRX8888, -+ DRM_FORMAT_ARGB8888, -+ DRM_FORMAT_ABGR8888, -+ DRM_FORMAT_RGBA8888, -+ DRM_FORMAT_BGRA8888, -+ DRM_FORMAT_ARGB2101010, -+ DRM_FORMAT_ABGR2101010, -+ DRM_FORMAT_RGBA1010102, -+ DRM_FORMAT_BGRA1010102, -+ /* TODO: non-RGB formats */ -+}; -+ -+static const u32 vs_formats_array_with_yuv444[] = { -+ DRM_FORMAT_XRGB4444, -+ DRM_FORMAT_XBGR4444, -+ DRM_FORMAT_RGBX4444, -+ DRM_FORMAT_BGRX4444, -+ DRM_FORMAT_ARGB4444, -+ DRM_FORMAT_ABGR4444, -+ DRM_FORMAT_RGBA4444, -+ DRM_FORMAT_BGRA4444, -+ DRM_FORMAT_XRGB1555, -+ DRM_FORMAT_XBGR1555, -+ DRM_FORMAT_RGBX5551, -+ DRM_FORMAT_BGRX5551, -+ DRM_FORMAT_ARGB1555, -+ DRM_FORMAT_ABGR1555, -+ DRM_FORMAT_RGBA5551, -+ DRM_FORMAT_BGRA5551, -+ DRM_FORMAT_RGB565, -+ DRM_FORMAT_BGR565, -+ DRM_FORMAT_XRGB8888, -+ DRM_FORMAT_XBGR8888, -+ DRM_FORMAT_RGBX8888, -+ DRM_FORMAT_BGRX8888, -+ DRM_FORMAT_ARGB8888, -+ DRM_FORMAT_ABGR8888, -+ DRM_FORMAT_RGBA8888, -+ DRM_FORMAT_BGRA8888, -+ DRM_FORMAT_ARGB2101010, -+ DRM_FORMAT_ABGR2101010, -+ DRM_FORMAT_RGBA1010102, -+ DRM_FORMAT_BGRA1010102, -+ /* TODO: non-RGB formats */ -+}; -+ -+static const struct vs_formats vs_formats_no_yuv444 = { -+ .array = vs_formats_array_no_yuv444, -+ .num = ARRAY_SIZE(vs_formats_array_no_yuv444) -+}; -+ -+static const struct vs_formats vs_formats_with_yuv444 = { -+ .array = vs_formats_array_with_yuv444, -+ .num = ARRAY_SIZE(vs_formats_array_with_yuv444) -+}; -+ -+static struct vs_chip_identity vs_chip_identities[] = { -+ { -+ .model = 0x8200, -+ .revision = 0x5720, -+ .customer_id = ~0U, -+ -+ .display_count = 2, -+ .formats = &vs_formats_no_yuv444, -+ }, -+ { -+ .model = 0x8200, -+ .revision = 0x5721, -+ .customer_id = 0x30B, -+ -+ .display_count = 2, -+ .formats = &vs_formats_no_yuv444, -+ }, -+ { -+ .model = 0x8200, -+ .revision = 0x5720, -+ .customer_id = 0x310, -+ -+ .display_count = 2, -+ .formats = &vs_formats_with_yuv444, -+ }, -+ { -+ .model = 0x8200, -+ .revision = 0x5720, -+ .customer_id = 0x311, -+ -+ .display_count = 2, -+ .formats = &vs_formats_no_yuv444, -+ }, -+}; -+ -+int vs_fill_chip_identity(struct regmap *regs, -+ struct vs_chip_identity *ident) -+{ -+ u32 model; -+ u32 revision; -+ u32 customer_id; -+ int i; -+ -+ regmap_read(regs, VSDC_TOP_CHIP_MODEL, &model); -+ regmap_read(regs, VSDC_TOP_CHIP_REV, &revision); -+ regmap_read(regs, VSDC_TOP_CHIP_CUSTOMER_ID, &customer_id); -+ -+ for (i = 0; i < ARRAY_SIZE(vs_chip_identities); i++) { -+ if (vs_chip_identities[i].model == model && -+ vs_chip_identities[i].revision == revision && -+ (vs_chip_identities[i].customer_id == customer_id || -+ vs_chip_identities[i].customer_id == ~0U)) { -+ memcpy(ident, &vs_chip_identities[i], sizeof(*ident)); -+ ident->customer_id = customer_id; -+ return 0; -+ } -+ } -+ -+ return -EINVAL; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisilicon/vs_hwdb.h -new file mode 100644 -index 000000000000..92192e4fa086 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h -@@ -0,0 +1,29 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#ifndef _VS_HWDB_H_ -+#define _VS_HWDB_H_ -+ -+#include -+#include -+ -+struct vs_formats { -+ const u32 *array; -+ unsigned int num; -+}; -+ -+struct vs_chip_identity { -+ u32 model; -+ u32 revision; -+ u32 customer_id; -+ -+ u32 display_count; -+ const struct vs_formats *formats; -+}; -+ -+int vs_fill_chip_identity(struct regmap *regs, -+ struct vs_chip_identity *ident); -+ -+#endif /* _VS_HWDB_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_plane.c b/drivers/gpu/drm/verisilicon/vs_plane.c -new file mode 100644 -index 000000000000..2f3953e588a3 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_plane.c -@@ -0,0 +1,124 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "vs_plane.h" -+ -+void drm_format_to_vs_format(u32 drm_format, struct vs_format *vs_format) -+{ -+ switch (drm_format) { -+ case DRM_FORMAT_XRGB4444: -+ case DRM_FORMAT_RGBX4444: -+ case DRM_FORMAT_XBGR4444: -+ case DRM_FORMAT_BGRX4444: -+ vs_format->color = VSDC_COLOR_FORMAT_X4R4G4B4; -+ break; -+ case DRM_FORMAT_ARGB4444: -+ case DRM_FORMAT_RGBA4444: -+ case DRM_FORMAT_ABGR4444: -+ case DRM_FORMAT_BGRA4444: -+ vs_format->color = VSDC_COLOR_FORMAT_A4R4G4B4; -+ break; -+ case DRM_FORMAT_XRGB1555: -+ case DRM_FORMAT_RGBX5551: -+ case DRM_FORMAT_XBGR1555: -+ case DRM_FORMAT_BGRX5551: -+ vs_format->color = VSDC_COLOR_FORMAT_X1R5G5B5; -+ break; -+ case DRM_FORMAT_ARGB1555: -+ case DRM_FORMAT_RGBA5551: -+ case DRM_FORMAT_ABGR1555: -+ case DRM_FORMAT_BGRA5551: -+ vs_format->color = VSDC_COLOR_FORMAT_A1R5G5B5; -+ break; -+ case DRM_FORMAT_RGB565: -+ case DRM_FORMAT_BGR565: -+ vs_format->color = VSDC_COLOR_FORMAT_R5G6B5; -+ break; -+ case DRM_FORMAT_XRGB8888: -+ case DRM_FORMAT_RGBX8888: -+ case DRM_FORMAT_XBGR8888: -+ case DRM_FORMAT_BGRX8888: -+ vs_format->color = VSDC_COLOR_FORMAT_X8R8G8B8; -+ break; -+ case DRM_FORMAT_ARGB8888: -+ case DRM_FORMAT_RGBA8888: -+ case DRM_FORMAT_ABGR8888: -+ case DRM_FORMAT_BGRA8888: -+ vs_format->color = VSDC_COLOR_FORMAT_A8R8G8B8; -+ break; -+ case DRM_FORMAT_ARGB2101010: -+ case DRM_FORMAT_RGBA1010102: -+ case DRM_FORMAT_ABGR2101010: -+ case DRM_FORMAT_BGRA1010102: -+ vs_format->color = VSDC_COLOR_FORMAT_A2R10G10B10; -+ break; -+ default: -+ pr_warn("Unexpected drm format!\n"); -+ } -+ -+ switch (drm_format) { -+ case DRM_FORMAT_RGBX4444: -+ case DRM_FORMAT_RGBA4444: -+ case DRM_FORMAT_RGBX5551: -+ case DRM_FORMAT_RGBA5551: -+ case DRM_FORMAT_RGBX8888: -+ case DRM_FORMAT_RGBA8888: -+ case DRM_FORMAT_RGBA1010102: -+ vs_format->swizzle = VSDC_SWIZZLE_RGBA; -+ break; -+ case DRM_FORMAT_XBGR4444: -+ case DRM_FORMAT_ABGR4444: -+ case DRM_FORMAT_XBGR1555: -+ case DRM_FORMAT_ABGR1555: -+ case DRM_FORMAT_BGR565: -+ case DRM_FORMAT_XBGR8888: -+ case DRM_FORMAT_ABGR8888: -+ case DRM_FORMAT_ABGR2101010: -+ vs_format->swizzle = VSDC_SWIZZLE_ABGR; -+ break; -+ case DRM_FORMAT_BGRX4444: -+ case DRM_FORMAT_BGRA4444: -+ case DRM_FORMAT_BGRX5551: -+ case DRM_FORMAT_BGRA5551: -+ case DRM_FORMAT_BGRX8888: -+ case DRM_FORMAT_BGRA8888: -+ case DRM_FORMAT_BGRA1010102: -+ vs_format->swizzle = VSDC_SWIZZLE_BGRA; -+ break; -+ default: -+ /* N/A for YUV formats */ -+ vs_format->swizzle = VSDC_SWIZZLE_ARGB; -+ } -+ -+ /* N/A for non-YUV formats */ -+ vs_format->uv_swizzle = false; -+} -+ -+dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, -+ const struct drm_rect *src_rect) -+{ -+ struct drm_gem_dma_object *gem; -+ dma_addr_t dma_addr; -+ -+ /* Get the physical address of the buffer in memory */ -+ gem = drm_fb_dma_get_gem_obj(fb, 0); -+ -+ /* Compute the start of the displayed memory */ -+ dma_addr = gem->dma_addr + fb->offsets[0]; -+ -+ /* Fixup framebuffer address for src coordinates */ -+ dma_addr += drm_format_info_min_pitch(fb->format, 0, -+ src_rect->x1 >> 16); -+ dma_addr += (src_rect->y1 >> 16) * fb->pitches[0]; -+ -+ return dma_addr; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_plane.h b/drivers/gpu/drm/verisilicon/vs_plane.h -new file mode 100644 -index 000000000000..41875ea3d66a ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_plane.h -@@ -0,0 +1,72 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_PLANE_H_ -+#define _VS_PLANE_H_ -+ -+#include -+ -+#include -+#include -+#include -+#include -+ -+#define VSDC_MAKE_PLANE_SIZE(w, h) (((w) & 0x7fff) | (((h) & 0x7fff) << 15)) -+#define VSDC_MAKE_PLANE_POS(x, y) (((x) & 0x7fff) | (((y) & 0x7fff) << 15)) -+ -+struct vs_dc; -+ -+enum vs_color_format { -+ VSDC_COLOR_FORMAT_X4R4G4B4, -+ VSDC_COLOR_FORMAT_A4R4G4B4, -+ VSDC_COLOR_FORMAT_X1R5G5B5, -+ VSDC_COLOR_FORMAT_A1R5G5B5, -+ VSDC_COLOR_FORMAT_R5G6B5, -+ VSDC_COLOR_FORMAT_X8R8G8B8, -+ VSDC_COLOR_FORMAT_A8R8G8B8, -+ VSDC_COLOR_FORMAT_YUY2, -+ VSDC_COLOR_FORMAT_UYVY, -+ VSDC_COLOR_FORMAT_INDEX8, -+ VSDC_COLOR_FORMAT_MONOCHROME, -+ VSDC_COLOR_FORMAT_YV12 = 0xf, -+ VSDC_COLOR_FORMAT_A8, -+ VSDC_COLOR_FORMAT_NV12, -+ VSDC_COLOR_FORMAT_NV16, -+ VSDC_COLOR_FORMAT_RG16, -+ VSDC_COLOR_FORMAT_R8, -+ VSDC_COLOR_FORMAT_NV12_10BIT, -+ VSDC_COLOR_FORMAT_A2R10G10B10, -+ VSDC_COLOR_FORMAT_NV16_10BIT, -+ VSDC_COLOR_FORMAT_INDEX1, -+ VSDC_COLOR_FORMAT_INDEX2, -+ VSDC_COLOR_FORMAT_INDEX4, -+ VSDC_COLOR_FORMAT_P010, -+ VSDC_COLOR_FORMAT_YUV444, -+ VSDC_COLOR_FORMAT_YUV444_10BIT -+}; -+ -+enum vs_swizzle { -+ VSDC_SWIZZLE_ARGB, -+ VSDC_SWIZZLE_RGBA, -+ VSDC_SWIZZLE_ABGR, -+ VSDC_SWIZZLE_BGRA, -+}; -+ -+struct vs_format { -+ enum vs_color_format color; -+ enum vs_swizzle swizzle; -+ bool uv_swizzle; -+}; -+ -+void drm_format_to_vs_format(u32 drm_format, struct vs_format *vs_format); -+dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, -+ const struct drm_rect *src_rect); -+ -+struct drm_plane *vs_primary_plane_init(struct drm_device *dev, struct vs_dc *dc); -+ -+#endif /* _VS_PLANE_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane.c b/drivers/gpu/drm/verisilicon/vs_primary_plane.c -new file mode 100644 -index 000000000000..e8fcb5958615 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_primary_plane.c -@@ -0,0 +1,173 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vs_crtc.h" -+#include "vs_plane.h" -+#include "vs_dc.h" -+#include "vs_primary_plane_regs.h" -+ -+static int vs_primary_plane_atomic_check(struct drm_plane *plane, -+ struct drm_atomic_state *state) -+{ -+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, -+ plane); -+ struct drm_crtc *crtc = new_plane_state->crtc; -+ struct drm_crtc_state *crtc_state; -+ -+ if (!crtc) -+ return 0; -+ -+ crtc_state = drm_atomic_get_new_crtc_state(state, crtc); -+ if (WARN_ON(!crtc_state)) -+ return -EINVAL; -+ -+ return drm_atomic_helper_check_plane_state(new_plane_state, -+ crtc_state, -+ DRM_PLANE_NO_SCALING, -+ DRM_PLANE_NO_SCALING, -+ false, true); -+} -+ -+static void vs_primary_plane_commit(struct vs_dc *dc, unsigned int output) -+{ -+ regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), -+ VSDC_FB_CONFIG_EX_COMMIT); -+} -+ -+static void vs_primary_plane_atomic_enable(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, -+ plane); -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ unsigned int output = vcrtc->id; -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), -+ VSDC_FB_CONFIG_EX_FB_EN); -+ regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output), -+ VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK, -+ VSDC_FB_CONFIG_EX_DISPLAY_ID(output)); -+ -+ vs_primary_plane_commit(dc, output); -+} -+ -+static void vs_primary_plane_atomic_disable(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_old_plane_state(atomic_state, -+ plane); -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ unsigned int output = vcrtc->id; -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), -+ VSDC_FB_CONFIG_EX_FB_EN); -+ -+ vs_primary_plane_commit(dc, output); -+} -+ -+static void vs_primary_plane_atomic_update(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, -+ plane); -+ struct drm_framebuffer *fb = state->fb; -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_dc *dc; -+ struct vs_crtc *vcrtc; -+ struct vs_format fmt; -+ unsigned int output; -+ dma_addr_t dma_addr; -+ -+ if (!state->visible) { -+ vs_primary_plane_atomic_disable(plane, atomic_state); -+ return; -+ } -+ -+ vcrtc = drm_crtc_to_vs_crtc(crtc); -+ output = vcrtc->id; -+ dc = vcrtc->dc; -+ -+ drm_format_to_vs_format(state->fb->format->format, &fmt); -+ -+ regmap_update_bits(dc->regs, VSDC_FB_CONFIG(output), -+ VSDC_FB_CONFIG_FMT_MASK, -+ VSDC_FB_CONFIG_FMT(fmt.color)); -+ regmap_update_bits(dc->regs, VSDC_FB_CONFIG(output), -+ VSDC_FB_CONFIG_SWIZZLE_MASK, -+ VSDC_FB_CONFIG_SWIZZLE(fmt.swizzle)); -+ regmap_assign_bits(dc->regs, VSDC_FB_CONFIG(output), -+ VSDC_FB_CONFIG_UV_SWIZZLE_EN, fmt.uv_swizzle); -+ -+ dma_addr = vs_fb_get_dma_addr(fb, &state->src); -+ -+ regmap_write(dc->regs, VSDC_FB_ADDRESS(output), -+ lower_32_bits(dma_addr)); -+ regmap_write(dc->regs, VSDC_FB_STRIDE(output), -+ fb->pitches[0]); -+ -+ regmap_write(dc->regs, VSDC_FB_TOP_LEFT(output), -+ VSDC_MAKE_PLANE_POS(state->crtc_x, state->crtc_y)); -+ regmap_write(dc->regs, VSDC_FB_BOTTOM_RIGHT(output), -+ VSDC_MAKE_PLANE_POS(state->crtc_x + state->crtc_w, -+ state->crtc_y + state->crtc_h)); -+ regmap_write(dc->regs, VSDC_FB_SIZE(output), -+ VSDC_MAKE_PLANE_SIZE(state->crtc_w, state->crtc_h)); -+ -+ regmap_write(dc->regs, VSDC_FB_BLEND_CONFIG(output), -+ VSDC_FB_BLEND_CONFIG_BLEND_DISABLE); -+ -+ vs_primary_plane_commit(dc, output); -+} -+ -+static const struct drm_plane_helper_funcs vs_primary_plane_helper_funcs = { -+ .atomic_check = vs_primary_plane_atomic_check, -+ .atomic_update = vs_primary_plane_atomic_update, -+ .atomic_enable = vs_primary_plane_atomic_enable, -+ .atomic_disable = vs_primary_plane_atomic_disable, -+}; -+ -+static const struct drm_plane_funcs vs_primary_plane_funcs = { -+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, -+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, -+ .disable_plane = drm_atomic_helper_disable_plane, -+ .reset = drm_atomic_helper_plane_reset, -+ .update_plane = drm_atomic_helper_update_plane, -+}; -+ -+struct drm_plane *vs_primary_plane_init(struct drm_device *drm_dev, struct vs_dc *dc) -+{ -+ struct drm_plane *plane; -+ -+ plane = drmm_universal_plane_alloc(drm_dev, struct drm_plane, dev, 0, -+ &vs_primary_plane_funcs, -+ dc->identity.formats->array, -+ dc->identity.formats->num, -+ NULL, -+ DRM_PLANE_TYPE_PRIMARY, -+ NULL); -+ -+ if (IS_ERR(plane)) -+ return plane; -+ -+ drm_plane_helper_add(plane, &vs_primary_plane_helper_funcs); -+ -+ return plane; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h -new file mode 100644 -index 000000000000..cbb125c46b39 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h -@@ -0,0 +1,53 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_PRIMARY_PLANE_REGS_H_ -+#define _VS_PRIMARY_PLANE_REGS_H_ -+ -+#include -+ -+#define VSDC_FB_ADDRESS(n) (0x1400 + 0x4 * (n)) -+ -+#define VSDC_FB_STRIDE(n) (0x1408 + 0x4 * (n)) -+ -+#define VSDC_FB_CONFIG(n) (0x1518 + 0x4 * (n)) -+#define VSDC_FB_CONFIG_CLEAR_EN BIT(8) -+#define VSDC_FB_CONFIG_ROT_MASK GENMASK(13, 11) -+#define VSDC_FB_CONFIG_ROT(v) ((v) << 11) -+#define VSDC_FB_CONFIG_YUV_SPACE_MASK GENMASK(16, 14) -+#define VSDC_FB_CONFIG_YUV_SPACE(v) ((v) << 14) -+#define VSDC_FB_CONFIG_TILE_MODE_MASK GENMASK(21, 17) -+#define VSDC_FB_CONFIG_TILE_MODE(v) ((v) << 14) -+#define VSDC_FB_CONFIG_SCALE_EN BIT(22) -+#define VSDC_FB_CONFIG_SWIZZLE_MASK GENMASK(24, 23) -+#define VSDC_FB_CONFIG_SWIZZLE(v) ((v) << 23) -+#define VSDC_FB_CONFIG_UV_SWIZZLE_EN BIT(25) -+#define VSDC_FB_CONFIG_FMT_MASK GENMASK(31, 26) -+#define VSDC_FB_CONFIG_FMT(v) ((v) << 26) -+ -+#define VSDC_FB_SIZE(n) (0x1810 + 0x4 * (n)) -+/* Fill with value generated with VSDC_MAKE_PLANE_SIZE(w, h) */ -+ -+#define VSDC_FB_CONFIG_EX(n) (0x1CC0 + 0x4 * (n)) -+#define VSDC_FB_CONFIG_EX_COMMIT BIT(12) -+#define VSDC_FB_CONFIG_EX_FB_EN BIT(13) -+#define VSDC_FB_CONFIG_EX_ZPOS_MASK GENMASK(18, 16) -+#define VSDC_FB_CONFIG_EX_ZPOS(v) ((v) << 16) -+#define VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK GENMASK(19, 19) -+#define VSDC_FB_CONFIG_EX_DISPLAY_ID(v) ((v) << 19) -+ -+#define VSDC_FB_TOP_LEFT(n) (0x24D8 + 0x4 * (n)) -+/* Fill with value generated with VSDC_MAKE_PLANE_POS(x, y) */ -+ -+#define VSDC_FB_BOTTOM_RIGHT(n) (0x24E0 + 0x4 * (n)) -+/* Fill with value generated with VSDC_MAKE_PLANE_POS(x, y) */ -+ -+#define VSDC_FB_BLEND_CONFIG(n) (0x2510 + 0x4 * (n)) -+#define VSDC_FB_BLEND_CONFIG_BLEND_DISABLE BIT(1) -+ -+#endif /* _VS_PRIMARY_PLANE_REGS_H_ */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch b/SPECS/linux-lts-kmhv2/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch new file mode 100644 index 0000000000..6f796d9cbc --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch @@ -0,0 +1,103 @@ +From ea4a0e0935587b36a14380693c67c8cd0a9b30f1 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Fri, 6 Feb 2026 10:32:02 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mfd: spacemit,p1: Add individual + regulator supply properties + +Add supply properties that match the P1 PMIC's actual hardware topology +where each buck converter has its own VIN pin and LDO groups share +common input pins. Supply names are defined according to the pinout +names in the P1 datasheet. + +The existing "vin-supply" is dropped from the binding document as the +updated spacemit P1 driver no longer parses it. Only the per-rail names +("vin1-supply", "vin2-supply", ...) are supported. + +Signed-off-by: Guodong Xu +Acked-by: Conor Dooley +Reviewed-by: Alex Elder +Link: https://patch.msgid.link/20260206-spacemit-p1-v4-1-8f695d93811e@riscstar.com +Signed-off-by: Mark Brown +(cherry picked from commit 82ffa9610ba39d3628a9bec968ddc68fe2fe6612) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/mfd/spacemit,p1.yaml | 49 ++++++++++++++++++- + 1 file changed, 47 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml b/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml +index c6593ac6ef6a..c67b1c6e4e4f 100644 +--- a/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml ++++ b/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml +@@ -27,8 +27,41 @@ properties: + interrupts: + maxItems: 1 + +- vin-supply: +- description: Input supply phandle. ++ vin1-supply: ++ description: ++ Power supply for BUCK1. Required if BUCK1 is defined. ++ ++ vin2-supply: ++ description: ++ Power supply for BUCK2. Required if BUCK2 is defined. ++ ++ vin3-supply: ++ description: ++ Power supply for BUCK3. Required if BUCK3 is defined. ++ ++ vin4-supply: ++ description: ++ Power supply for BUCK4. Required if BUCK4 is defined. ++ ++ vin5-supply: ++ description: ++ Power supply for BUCK5. Required if BUCK5 is defined. ++ ++ vin6-supply: ++ description: ++ Power supply for BUCK6. Required if BUCK6 is defined. ++ ++ aldoin-supply: ++ description: ++ Power supply for ALDO1-4. Required if any are defined. ++ ++ dldoin1-supply: ++ description: ++ Power supply for DLDO1-4. Required if any are defined. ++ ++ dldoin2-supply: ++ description: ++ Power supply for DLDO5-7. Required if any are defined. + + regulators: + type: object +@@ -58,6 +91,10 @@ examples: + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; ++ vin1-supply = <®_vcc_5v>; ++ vin5-supply = <®_vcc_5v>; ++ aldoin-supply = <®_vcc_5v>; ++ dldoin1-supply = <&buck5>; + + regulators { + buck1 { +@@ -68,6 +105,14 @@ examples: + regulator-always-on; + }; + ++ buck5: buck5 { ++ regulator-name = "buck5"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ + aldo1 { + regulator-name = "aldo1"; + regulator-min-microvolt = <500000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0195-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch b/SPECS/linux-lts-kmhv2/0195-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch deleted file mode 100644 index 31987352cf..0000000000 --- a/SPECS/linux-lts-kmhv2/0195-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch +++ /dev/null @@ -1,153 +0,0 @@ -From ee91943024b041838f8d48b5875cd8083a8d0945 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:18 +0800 -Subject: [PATCH 195/467] UPSTREAM: dt-bindings: display/bridge: add binding - for TH1520 HDMI controller - -T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired -with DesignWare HDMI PHY, with an extra clock gate for HDMI pixel clock -and two reset controls. - -Add a device tree binding to it. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Thomas Zimmermann -Link: https://patch.msgid.link/20260129023922.1527729-5-zhengxingda@iscas.ac.cn -(cherry picked from commit 3d60ff99a78ccd3b72765542dd083b134d6ae4bb) -Signed-off-by: Han Gao ---- - .../display/bridge/thead,th1520-dw-hdmi.yaml | 120 ++++++++++++++++++ - 1 file changed, 120 insertions(+) - create mode 100644 Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml - -diff --git a/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml -new file mode 100644 -index 000000000000..68fff885ce15 ---- /dev/null -+++ b/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml -@@ -0,0 +1,120 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/display/bridge/thead,th1520-dw-hdmi.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: T-Head TH1520 DesignWare HDMI TX Encoder -+ -+maintainers: -+ - Icenowy Zheng -+ -+description: -+ The HDMI transmitter is a Synopsys DesignWare HDMI TX controller -+ paired with a DesignWare HDMI Gen2 TX PHY. -+ -+allOf: -+ - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - thead,th1520-dw-hdmi -+ -+ reg-io-width: -+ const: 4 -+ -+ clocks: -+ maxItems: 4 -+ -+ clock-names: -+ items: -+ - const: iahb -+ - const: isfr -+ - const: cec -+ - const: pix -+ -+ resets: -+ items: -+ - description: Main reset -+ - description: Configuration APB reset -+ -+ reset-names: -+ items: -+ - const: main -+ - const: apb -+ -+ ports: -+ $ref: /schemas/graph.yaml#/properties/ports -+ -+ properties: -+ port@0: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: Input port connected to DC8200 DPU "DP" output -+ -+ port@1: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: HDMI output port -+ -+ required: -+ - port@0 -+ - port@1 -+ -+required: -+ - compatible -+ - reg -+ - reg-io-width -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ - interrupts -+ - ports -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ hdmi@ffef540000 { -+ compatible = "thead,th1520-dw-hdmi"; -+ reg = <0xff 0xef540000 0x0 0x40000>; -+ reg-io-width = <4>; -+ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_vo CLK_HDMI_PCLK>, -+ <&clk_vo CLK_HDMI_SFR>, -+ <&clk_vo CLK_HDMI_CEC>, -+ <&clk_vo CLK_HDMI_PIXCLK>; -+ clock-names = "iahb", "isfr", "cec", "pix"; -+ resets = <&rst_vo TH1520_RESET_ID_HDMI>, -+ <&rst_vo TH1520_RESET_ID_HDMI_APB>; -+ reset-names = "main", "apb"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ port@0 { -+ reg = <0>; -+ -+ hdmi_in: endpoint { -+ remote-endpoint = <&dpu_out_dp1>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ hdmi_out_conn: endpoint { -+ remote-endpoint = <&hdmi_conn_in>; -+ }; -+ }; -+ }; -+ }; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch b/SPECS/linux-lts-kmhv2/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch new file mode 100644 index 0000000000..c1c7ac83ec --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch @@ -0,0 +1,75 @@ +From 42b7ba3e5273fbdc3ca27c1fb551be6f0eccab97 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Fri, 6 Feb 2026 10:32:03 +0800 +Subject: [RUYI PATCH] UPSTREAM: regulator: spacemit-p1: Update supply names + +Update supply names to match the P1 PMIC's actual hardware pinout where +each buck has an individual VIN pin (vin1-vin6) and LDO groups have +dedicated input pins (aldoin, dldoin1, dldoin2). + +This is an ABI change from the original "vin" and "buck5" supplies. +The P1/PMIC regulator has no consumers in the DTS tree yet. For the two +K1 boards in-tree (BPI-F3 and Jupiter), power settings come from +boot firmware, so a probe failure has minimal impact. + +Signed-off-by: Guodong Xu +Link: https://developer.spacemit.com/documentation?token=T1Btw2BdiiSlSXkAdibcoMetnag +[1] +Reviewed-by: Alex Elder +Link: https://patch.msgid.link/20260206-spacemit-p1-v4-2-8f695d93811e@riscstar.com +Signed-off-by: Mark Brown +(cherry picked from commit fbb4c52ccdcb4a612d2b7f800aa57090eeee16d7) +Signed-off-by: Han Gao +--- + drivers/regulator/spacemit-p1.c | 25 ++++++++++++++----------- + 1 file changed, 14 insertions(+), 11 deletions(-) + +diff --git a/drivers/regulator/spacemit-p1.c b/drivers/regulator/spacemit-p1.c +index 2b585ba01a93..57e6e00a73fa 100644 +--- a/drivers/regulator/spacemit-p1.c ++++ b/drivers/regulator/spacemit-p1.c +@@ -87,13 +87,16 @@ static const struct linear_range p1_ldo_ranges[] = { + } + + #define P1_BUCK_DESC(_n) \ +- P1_REG_DESC(BUCK, buck, _n, "vin", 0x47, BUCK_MASK, 255, p1_buck_ranges) ++ P1_REG_DESC(BUCK, buck, _n, "vin" #_n, 0x47, BUCK_MASK, 255, p1_buck_ranges) + + #define P1_ALDO_DESC(_n) \ +- P1_REG_DESC(ALDO, aldo, _n, "vin", 0x5b, LDO_MASK, 128, p1_ldo_ranges) ++ P1_REG_DESC(ALDO, aldo, _n, "aldoin", 0x5b, LDO_MASK, 128, p1_ldo_ranges) + +-#define P1_DLDO_DESC(_n) \ +- P1_REG_DESC(DLDO, dldo, _n, "buck5", 0x67, LDO_MASK, 128, p1_ldo_ranges) ++#define P1_DLDO1_DESC(_n) \ ++ P1_REG_DESC(DLDO, dldo, _n, "dldoin1", 0x67, LDO_MASK, 128, p1_ldo_ranges) ++ ++#define P1_DLDO2_DESC(_n) \ ++ P1_REG_DESC(DLDO, dldo, _n, "dldoin2", 0x67, LDO_MASK, 128, p1_ldo_ranges) + + static const struct regulator_desc p1_regulator_desc[] = { + P1_BUCK_DESC(1), +@@ -108,13 +111,13 @@ static const struct regulator_desc p1_regulator_desc[] = { + P1_ALDO_DESC(3), + P1_ALDO_DESC(4), + +- P1_DLDO_DESC(1), +- P1_DLDO_DESC(2), +- P1_DLDO_DESC(3), +- P1_DLDO_DESC(4), +- P1_DLDO_DESC(5), +- P1_DLDO_DESC(6), +- P1_DLDO_DESC(7), ++ P1_DLDO1_DESC(1), ++ P1_DLDO1_DESC(2), ++ P1_DLDO1_DESC(3), ++ P1_DLDO1_DESC(4), ++ P1_DLDO2_DESC(5), ++ P1_DLDO2_DESC(6), ++ P1_DLDO2_DESC(7), + }; + + static int p1_regulator_probe(struct platform_device *pdev) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0196-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch b/SPECS/linux-lts-kmhv2/0196-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch deleted file mode 100644 index d96c026cbf..0000000000 --- a/SPECS/linux-lts-kmhv2/0196-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch +++ /dev/null @@ -1,257 +0,0 @@ -From 93ee7e5ff8c14262f2edbaebf59e12ec50ebeac0 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:19 +0800 -Subject: [PATCH 196/467] UPSTREAM: drm/bridge: add a driver for T-Head TH1520 - HDMI controller - -T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller (paired -with DesignWare HDMI TX PHY Gen2) that takes the "DP" output from the -display controller. - -Add a driver for this controller utilizing the common DesignWare HDMI -code in the kernel. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Tested-by: Han Gao -Tested-by: Michal Wilczynski -Acked-by: Thomas Zimmermann -Signed-off-by: Thomas Zimmermann -Link: https://patch.msgid.link/20260129023922.1527729-6-zhengxingda@iscas.ac.cn -(cherry picked from commit 96f30ee0fb9db1663eb8fd55c12e4c67da8c4a90) -Signed-off-by: Han Gao ---- - MAINTAINERS | 1 + - drivers/gpu/drm/bridge/Kconfig | 10 ++ - drivers/gpu/drm/bridge/Makefile | 1 + - drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 173 ++++++++++++++++++++++++ - 4 files changed, 185 insertions(+) - create mode 100644 drivers/gpu/drm/bridge/th1520-dw-hdmi.c - -diff --git a/MAINTAINERS b/MAINTAINERS -index b50b6c7a9b52..1509fa6ab229 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -22227,6 +22227,7 @@ F: Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml - F: arch/riscv/boot/dts/thead/ - F: drivers/clk/thead/clk-th1520-ap.c - F: drivers/firmware/thead,th1520-aon.c -+F: drivers/gpu/drm/bridge/th1520-dw-hdmi.c - F: drivers/mailbox/mailbox-th1520.c - F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c - F: drivers/pinctrl/pinctrl-th1520.c -diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig -index a250afd8d662..8e19f5fb9ad7 100644 ---- a/drivers/gpu/drm/bridge/Kconfig -+++ b/drivers/gpu/drm/bridge/Kconfig -@@ -335,6 +335,16 @@ config DRM_THINE_THC63LVD1024 - help - Thine THC63LVD1024 LVDS/parallel converter driver. - -+config DRM_THEAD_TH1520_DW_HDMI -+ tristate "T-Head TH1520 DesignWare HDMI bridge" -+ depends on OF -+ depends on COMMON_CLK -+ depends on ARCH_THEAD || COMPILE_TEST -+ select DRM_DW_HDMI -+ help -+ Choose this to enable support for the internal HDMI bridge found -+ on the T-Head TH1520 SoC. -+ - config DRM_TOSHIBA_TC358762 - tristate "TC358762 DSI/DPI bridge" - depends on OF -diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile -index c7dc03182e59..085b5db45d6f 100644 ---- a/drivers/gpu/drm/bridge/Makefile -+++ b/drivers/gpu/drm/bridge/Makefile -@@ -28,6 +28,7 @@ obj-$(CONFIG_DRM_SII902X) += sii902x.o - obj-$(CONFIG_DRM_SII9234) += sii9234.o - obj-$(CONFIG_DRM_SIMPLE_BRIDGE) += simple-bridge.o - obj-$(CONFIG_DRM_SOLOMON_SSD2825) += ssd2825.o -+obj-$(CONFIG_DRM_THEAD_TH1520_DW_HDMI) += th1520-dw-hdmi.o - obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o - obj-$(CONFIG_DRM_TOSHIBA_TC358762) += tc358762.o - obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o -diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -new file mode 100644 -index 000000000000..389eead5f1c4 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -@@ -0,0 +1,173 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on rcar_dw_hdmi.c, which is: -+ * Copyright (C) 2016 Renesas Electronics Corporation -+ * Based on imx8mp-hdmi-tx.c, which is: -+ * Copyright (C) 2022 Pengutronix, Lucas Stach -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define TH1520_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */ -+#define TH1520_HDMI_PHY_CKSYMTXCTRL 0x09 /* Clock Symbol and Transmitter Control Register */ -+#define TH1520_HDMI_PHY_VLEVCTRL 0x0e /* Voltage Level Control Register */ -+#define TH1520_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */ -+#define TH1520_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */ -+#define TH1520_HDMI_PHY_TXTERM 0x19 /* Transmission Termination Register */ -+ -+struct th1520_hdmi_phy_params { -+ unsigned long mpixelclock; -+ u16 opmode_pllcfg; -+ u16 pllcurrgmpctrl; -+ u16 plldivctrl; -+ u16 cksymtxctrl; -+ u16 vlevctrl; -+ u16 txterm; -+}; -+ -+static const struct th1520_hdmi_phy_params th1520_hdmi_phy_params[] = { -+ { 35500000, 0x0003, 0x0283, 0x0628, 0x8088, 0x01a0, 0x0007 }, -+ { 44900000, 0x0003, 0x0285, 0x0228, 0x8088, 0x01a0, 0x0007 }, -+ { 71000000, 0x0002, 0x1183, 0x0614, 0x8088, 0x01a0, 0x0007 }, -+ { 90000000, 0x0002, 0x1142, 0x0214, 0x8088, 0x01a0, 0x0007 }, -+ { 121750000, 0x0001, 0x20c0, 0x060a, 0x8088, 0x01a0, 0x0007 }, -+ { 165000000, 0x0001, 0x2080, 0x020a, 0x8088, 0x01a0, 0x0007 }, -+ { 198000000, 0x0000, 0x3040, 0x0605, 0x83c8, 0x0120, 0x0004 }, -+ { 297000000, 0x0000, 0x3041, 0x0205, 0x81dc, 0x0200, 0x0005 }, -+ { 371250000, 0x0640, 0x3041, 0x0205, 0x80f6, 0x0140, 0x0000 }, -+ { 495000000, 0x0640, 0x3080, 0x0005, 0x80f6, 0x0140, 0x0000 }, -+ { 594000000, 0x0640, 0x3080, 0x0005, 0x80fa, 0x01e0, 0x0004 }, -+}; -+ -+struct th1520_hdmi { -+ struct dw_hdmi_plat_data plat_data; -+ struct dw_hdmi *dw_hdmi; -+ struct clk *pixclk; -+ struct reset_control *mainrst, *prst; -+}; -+ -+static enum drm_mode_status -+th1520_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, -+ const struct drm_display_info *info, -+ const struct drm_display_mode *mode) -+{ -+ /* -+ * The maximum supported clock frequency is 594 MHz, as shown in the PHY -+ * parameters table. -+ */ -+ if (mode->clock > 594000) -+ return MODE_CLOCK_HIGH; -+ -+ return MODE_OK; -+} -+ -+static void th1520_hdmi_phy_set_params(struct dw_hdmi *hdmi, -+ const struct th1520_hdmi_phy_params *params) -+{ -+ dw_hdmi_phy_i2c_write(hdmi, params->opmode_pllcfg, -+ TH1520_HDMI_PHY_OPMODE_PLLCFG); -+ dw_hdmi_phy_i2c_write(hdmi, params->pllcurrgmpctrl, -+ TH1520_HDMI_PHY_PLLCURRGMPCTRL); -+ dw_hdmi_phy_i2c_write(hdmi, params->plldivctrl, -+ TH1520_HDMI_PHY_PLLDIVCTRL); -+ dw_hdmi_phy_i2c_write(hdmi, params->vlevctrl, -+ TH1520_HDMI_PHY_VLEVCTRL); -+ dw_hdmi_phy_i2c_write(hdmi, params->cksymtxctrl, -+ TH1520_HDMI_PHY_CKSYMTXCTRL); -+ dw_hdmi_phy_i2c_write(hdmi, params->txterm, -+ TH1520_HDMI_PHY_TXTERM); -+} -+ -+static int th1520_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data, -+ unsigned long mpixelclock) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(th1520_hdmi_phy_params); i++) { -+ if (mpixelclock <= th1520_hdmi_phy_params[i].mpixelclock) { -+ th1520_hdmi_phy_set_params(hdmi, -+ &th1520_hdmi_phy_params[i]); -+ return 0; -+ } -+ } -+ -+ return -EINVAL; -+} -+ -+static int th1520_dw_hdmi_probe(struct platform_device *pdev) -+{ -+ struct th1520_hdmi *hdmi; -+ struct dw_hdmi_plat_data *plat_data; -+ struct device *dev = &pdev->dev; -+ -+ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); -+ if (!hdmi) -+ return -ENOMEM; -+ -+ plat_data = &hdmi->plat_data; -+ -+ hdmi->pixclk = devm_clk_get_enabled(dev, "pix"); -+ if (IS_ERR(hdmi->pixclk)) -+ return dev_err_probe(dev, PTR_ERR(hdmi->pixclk), -+ "Unable to get pixel clock\n"); -+ -+ hdmi->mainrst = devm_reset_control_get_exclusive_deasserted(dev, "main"); -+ if (IS_ERR(hdmi->mainrst)) -+ return dev_err_probe(dev, PTR_ERR(hdmi->mainrst), -+ "Unable to get main reset\n"); -+ -+ hdmi->prst = devm_reset_control_get_exclusive_deasserted(dev, "apb"); -+ if (IS_ERR(hdmi->prst)) -+ return dev_err_probe(dev, PTR_ERR(hdmi->prst), -+ "Unable to get apb reset\n"); -+ -+ plat_data->output_port = 1; -+ plat_data->mode_valid = th1520_hdmi_mode_valid; -+ plat_data->configure_phy = th1520_hdmi_phy_configure; -+ plat_data->priv_data = hdmi; -+ -+ hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); -+ if (IS_ERR(hdmi)) -+ return PTR_ERR(hdmi); -+ -+ platform_set_drvdata(pdev, hdmi); -+ -+ return 0; -+} -+ -+static void th1520_dw_hdmi_remove(struct platform_device *pdev) -+{ -+ struct dw_hdmi *hdmi = platform_get_drvdata(pdev); -+ -+ dw_hdmi_remove(hdmi); -+} -+ -+static const struct of_device_id th1520_dw_hdmi_of_table[] = { -+ { .compatible = "thead,th1520-dw-hdmi" }, -+ { /* Sentinel */ }, -+}; -+MODULE_DEVICE_TABLE(of, th1520_dw_hdmi_of_table); -+ -+static struct platform_driver th1520_dw_hdmi_platform_driver = { -+ .probe = th1520_dw_hdmi_probe, -+ .remove = th1520_dw_hdmi_remove, -+ .driver = { -+ .name = "th1520-dw-hdmi", -+ .of_match_table = th1520_dw_hdmi_of_table, -+ }, -+}; -+ -+module_platform_driver(th1520_dw_hdmi_platform_driver); -+ -+MODULE_AUTHOR("Icenowy Zheng "); -+MODULE_DESCRIPTION("T-Head TH1520 HDMI Encoder Driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch b/SPECS/linux-lts-kmhv2/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch new file mode 100644 index 0000000000..7a0dd9d20a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch @@ -0,0 +1,67 @@ +From a16a762a96646468762203524a13847057523875 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 23 Dec 2025 10:24:50 +0800 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: add reset support + +The SDHCI controller of SpacemiT K1 SoC requires two resets, add +support to explicitly request the reset line and deassert during +initialization phase. Still using devm_xx_get_optional() API to +make the request optional. + +Signed-off-by: Yixun Lan +Reviewed-by: Javier Martinez Canillas +Signed-off-by: Ulf Hansson +(cherry picked from commit 658b716c048684ad13d78280d69b883f181251da) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index 0cc97e23a2f9..a160e1d5d9bd 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + + #include "sdhci.h" +@@ -223,6 +224,21 @@ static inline int spacemit_sdhci_get_clocks(struct device *dev, + return 0; + } + ++static inline int spacemit_sdhci_get_resets(struct device *dev) ++{ ++ struct reset_control *rst; ++ ++ rst = devm_reset_control_get_optional_shared_deasserted(dev, "axi"); ++ if (IS_ERR(rst)) ++ return PTR_ERR(rst); ++ ++ rst = devm_reset_control_get_optional_exclusive_deasserted(dev, "sdh"); ++ if (IS_ERR(rst)) ++ return PTR_ERR(rst); ++ ++ return 0; ++} ++ + static const struct sdhci_ops spacemit_sdhci_ops = { + .get_max_clock = spacemit_sdhci_clk_get_max_clock, + .reset = spacemit_sdhci_reset, +@@ -284,6 +300,10 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) + if (ret) + goto err_pltfm; + ++ ret = spacemit_sdhci_get_resets(dev); ++ if (ret) ++ goto err_pltfm; ++ + ret = sdhci_add_host(host); + if (ret) + goto err_pltfm; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0197-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch b/SPECS/linux-lts-kmhv2/0197-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch deleted file mode 100644 index fd657fca32..0000000000 --- a/SPECS/linux-lts-kmhv2/0197-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch +++ /dev/null @@ -1,103 +0,0 @@ -From d3f0701d0caf105e3dca7e90f7611eb6111ae3e5 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Fri, 6 Feb 2026 10:32:02 +0800 -Subject: [PATCH 197/467] UPSTREAM: dt-bindings: mfd: spacemit,p1: Add - individual regulator supply properties - -Add supply properties that match the P1 PMIC's actual hardware topology -where each buck converter has its own VIN pin and LDO groups share -common input pins. Supply names are defined according to the pinout -names in the P1 datasheet. - -The existing "vin-supply" is dropped from the binding document as the -updated spacemit P1 driver no longer parses it. Only the per-rail names -("vin1-supply", "vin2-supply", ...) are supported. - -Signed-off-by: Guodong Xu -Acked-by: Conor Dooley -Reviewed-by: Alex Elder -Link: https://patch.msgid.link/20260206-spacemit-p1-v4-1-8f695d93811e@riscstar.com -Signed-off-by: Mark Brown -(cherry picked from commit 82ffa9610ba39d3628a9bec968ddc68fe2fe6612) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/mfd/spacemit,p1.yaml | 49 ++++++++++++++++++- - 1 file changed, 47 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml b/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml -index c6593ac6ef6a..c67b1c6e4e4f 100644 ---- a/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml -+++ b/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml -@@ -27,8 +27,41 @@ properties: - interrupts: - maxItems: 1 - -- vin-supply: -- description: Input supply phandle. -+ vin1-supply: -+ description: -+ Power supply for BUCK1. Required if BUCK1 is defined. -+ -+ vin2-supply: -+ description: -+ Power supply for BUCK2. Required if BUCK2 is defined. -+ -+ vin3-supply: -+ description: -+ Power supply for BUCK3. Required if BUCK3 is defined. -+ -+ vin4-supply: -+ description: -+ Power supply for BUCK4. Required if BUCK4 is defined. -+ -+ vin5-supply: -+ description: -+ Power supply for BUCK5. Required if BUCK5 is defined. -+ -+ vin6-supply: -+ description: -+ Power supply for BUCK6. Required if BUCK6 is defined. -+ -+ aldoin-supply: -+ description: -+ Power supply for ALDO1-4. Required if any are defined. -+ -+ dldoin1-supply: -+ description: -+ Power supply for DLDO1-4. Required if any are defined. -+ -+ dldoin2-supply: -+ description: -+ Power supply for DLDO5-7. Required if any are defined. - - regulators: - type: object -@@ -58,6 +91,10 @@ examples: - compatible = "spacemit,p1"; - reg = <0x41>; - interrupts = <64>; -+ vin1-supply = <®_vcc_5v>; -+ vin5-supply = <®_vcc_5v>; -+ aldoin-supply = <®_vcc_5v>; -+ dldoin1-supply = <&buck5>; - - regulators { - buck1 { -@@ -68,6 +105,14 @@ examples: - regulator-always-on; - }; - -+ buck5: buck5 { -+ regulator-name = "buck5"; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ - aldo1 { - regulator-name = "aldo1"; - regulator-min-microvolt = <500000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch b/SPECS/linux-lts-kmhv2/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch new file mode 100644 index 0000000000..271bd70fc5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch @@ -0,0 +1,37 @@ +From 3661bb1bda184323b7f27ca11c4f6aa2453a891b Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 22 Jan 2026 17:37:30 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add support + for K3 SoC + +The SDHCI controller found on SpacemiT K3 SoC share the same IP with +K1 generation, while fixed the broken 64BIT DMA issue. Introduce a +compatible string to enable support for it. + +Acked-by: Rob Herring (Arm) +Signed-off-by: Yixun Lan +Signed-off-by: Ulf Hansson +(cherry picked from commit b4206966e2d48883f04d5a2b2ae6c46b528245d3) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +index 13d9382058fb..383841369fb2 100644 +--- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml ++++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +@@ -14,7 +14,9 @@ allOf: + + properties: + compatible: +- const: spacemit,k1-sdhci ++ enum: ++ - spacemit,k1-sdhci ++ - spacemit,k3-sdhci + + reg: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch b/SPECS/linux-lts-kmhv2/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch new file mode 100644 index 0000000000..067922ab83 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch @@ -0,0 +1,62 @@ +From aef7fb87d55efc5bff2a628b6196c36b7eaf3e12 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 22 Jan 2026 17:37:31 +0800 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: spacemit: Add support for K3 + SoC + +The SDHCI controller found on SpacemiT K3 SoC share the same IP with K1 +generation and introduce a compatible data to denote the change that broken +64BIT DMA issue has been fixed. + +Signed-off-by: Yixun Lan +Signed-off-by: Ulf Hansson +(cherry picked from commit 1e9f43a1dbefd3de45b97545e5773d2b52dc7f02) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 19 +++++++++++++++++-- + 1 file changed, 17 insertions(+), 2 deletions(-) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index a160e1d5d9bd..455656f9842d 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -259,8 +259,20 @@ static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata = { + SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }; + ++static const struct sdhci_pltfm_data spacemit_sdhci_k3_pdata = { ++ .ops = &spacemit_sdhci_ops, ++ .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | ++ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | ++ SDHCI_QUIRK_32BIT_ADMA_SIZE | ++ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | ++ SDHCI_QUIRK_BROKEN_CARD_DETECTION | ++ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, ++}; ++ + static const struct of_device_id spacemit_sdhci_of_match[] = { +- { .compatible = "spacemit,k1-sdhci" }, ++ { .compatible = "spacemit,k1-sdhci", .data = &spacemit_sdhci_k1_pdata }, ++ { .compatible = "spacemit,k3-sdhci", .data = &spacemit_sdhci_k3_pdata }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, spacemit_sdhci_of_match); +@@ -271,10 +283,13 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) + struct spacemit_sdhci_host *sdhst; + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_host *host; ++ const struct sdhci_pltfm_data *data; + struct mmc_host_ops *mops; + int ret; + +- host = sdhci_pltfm_init(pdev, &spacemit_sdhci_k1_pdata, sizeof(*sdhst)); ++ data = of_device_get_match_data(&pdev->dev); ++ ++ host = sdhci_pltfm_init(pdev, data, sizeof(*sdhst)); + if (IS_ERR(host)) + return PTR_ERR(host); + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0198-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch b/SPECS/linux-lts-kmhv2/0198-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch deleted file mode 100644 index 369110a4e9..0000000000 --- a/SPECS/linux-lts-kmhv2/0198-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 9bd75aaa59fb6ab1d9e1b11f9f2ad77f1658b9a4 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Fri, 6 Feb 2026 10:32:03 +0800 -Subject: [PATCH 198/467] UPSTREAM: regulator: spacemit-p1: Update supply names - -Update supply names to match the P1 PMIC's actual hardware pinout where -each buck has an individual VIN pin (vin1-vin6) and LDO groups have -dedicated input pins (aldoin, dldoin1, dldoin2). - -This is an ABI change from the original "vin" and "buck5" supplies. -The P1/PMIC regulator has no consumers in the DTS tree yet. For the two -K1 boards in-tree (BPI-F3 and Jupiter), power settings come from -boot firmware, so a probe failure has minimal impact. - -Signed-off-by: Guodong Xu -Link: https://developer.spacemit.com/documentation?token=T1Btw2BdiiSlSXkAdibcoMetnag -[1] -Reviewed-by: Alex Elder -Link: https://patch.msgid.link/20260206-spacemit-p1-v4-2-8f695d93811e@riscstar.com -Signed-off-by: Mark Brown -(cherry picked from commit fbb4c52ccdcb4a612d2b7f800aa57090eeee16d7) -Signed-off-by: Han Gao ---- - drivers/regulator/spacemit-p1.c | 25 ++++++++++++++----------- - 1 file changed, 14 insertions(+), 11 deletions(-) - -diff --git a/drivers/regulator/spacemit-p1.c b/drivers/regulator/spacemit-p1.c -index 2b585ba01a93..57e6e00a73fa 100644 ---- a/drivers/regulator/spacemit-p1.c -+++ b/drivers/regulator/spacemit-p1.c -@@ -87,13 +87,16 @@ static const struct linear_range p1_ldo_ranges[] = { - } - - #define P1_BUCK_DESC(_n) \ -- P1_REG_DESC(BUCK, buck, _n, "vin", 0x47, BUCK_MASK, 255, p1_buck_ranges) -+ P1_REG_DESC(BUCK, buck, _n, "vin" #_n, 0x47, BUCK_MASK, 255, p1_buck_ranges) - - #define P1_ALDO_DESC(_n) \ -- P1_REG_DESC(ALDO, aldo, _n, "vin", 0x5b, LDO_MASK, 128, p1_ldo_ranges) -+ P1_REG_DESC(ALDO, aldo, _n, "aldoin", 0x5b, LDO_MASK, 128, p1_ldo_ranges) - --#define P1_DLDO_DESC(_n) \ -- P1_REG_DESC(DLDO, dldo, _n, "buck5", 0x67, LDO_MASK, 128, p1_ldo_ranges) -+#define P1_DLDO1_DESC(_n) \ -+ P1_REG_DESC(DLDO, dldo, _n, "dldoin1", 0x67, LDO_MASK, 128, p1_ldo_ranges) -+ -+#define P1_DLDO2_DESC(_n) \ -+ P1_REG_DESC(DLDO, dldo, _n, "dldoin2", 0x67, LDO_MASK, 128, p1_ldo_ranges) - - static const struct regulator_desc p1_regulator_desc[] = { - P1_BUCK_DESC(1), -@@ -108,13 +111,13 @@ static const struct regulator_desc p1_regulator_desc[] = { - P1_ALDO_DESC(3), - P1_ALDO_DESC(4), - -- P1_DLDO_DESC(1), -- P1_DLDO_DESC(2), -- P1_DLDO_DESC(3), -- P1_DLDO_DESC(4), -- P1_DLDO_DESC(5), -- P1_DLDO_DESC(6), -- P1_DLDO_DESC(7), -+ P1_DLDO1_DESC(1), -+ P1_DLDO1_DESC(2), -+ P1_DLDO1_DESC(3), -+ P1_DLDO1_DESC(4), -+ P1_DLDO2_DESC(5), -+ P1_DLDO2_DESC(6), -+ P1_DLDO2_DESC(7), - }; - - static int p1_regulator_probe(struct platform_device *pdev) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch b/SPECS/linux-lts-kmhv2/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch new file mode 100644 index 0000000000..bd29a279bd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch @@ -0,0 +1,90 @@ +From 71fc35504a003f43684f36757050f5c7e1ca7c23 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Sun, 5 Apr 2026 15:41:53 +0000 +Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Add flags for disabling ASPM + capability for broken Root Ports + +Add flags for disabling the ASPM L0s/L1 capability for broken Root Ports +by clearing the corresponding bits in Link Capabilities Register through +the local management bus. This allows ASPM to be disabled on platforms +which don't support it. + +Signed-off-by: Yao Zi +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Helgaas +Tested-by: Han Gao +Tested-by: Chen Wang # Pioneerbox +Reviewed-by: Chen Wang +Link: https://patch.msgid.link/20260405154154.46829-2-me@ziyao.cc +(cherry picked from commit 5ccc76a87f1ec2422811e61be44165bfc9e7cf54) +Signed-off-by: Han Gao +--- + .../controller/cadence/pcie-cadence-host.c | 7 +++++++ + drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++ + 2 files changed, 26 insertions(+) + +diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c +index db3154c1eccb..0bc9e6e90e0e 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence-host.c ++++ b/drivers/pci/controller/cadence/pcie-cadence-host.c +@@ -147,6 +147,13 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) + cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0); + cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); + ++ value = cdns_pcie_rp_readl(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP); ++ if (rc->quirk_broken_aspm_l0s) ++ value &= ~PCI_EXP_LNKCAP_ASPM_L0S; ++ if (rc->quirk_broken_aspm_l1) ++ value &= ~PCI_EXP_LNKCAP_ASPM_L1; ++ cdns_pcie_rp_writel(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP, value); ++ + return 0; + } + +diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h +index 277f3706a4f4..574e9cf4d003 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence.h ++++ b/drivers/pci/controller/cadence/pcie-cadence.h +@@ -115,6 +115,8 @@ struct cdns_pcie { + * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk + * @ecam_supported: Whether the ECAM is supported + * @no_inbound_map: Whether inbound mapping is supported ++ * @quirk_broken_aspm_l0s: Disable ASPM L0s support as quirk ++ * @quirk_broken_aspm_l1: Disable ASPM L1 support as quirk + */ + struct cdns_pcie_rc { + struct cdns_pcie pcie; +@@ -127,6 +129,8 @@ struct cdns_pcie_rc { + unsigned int quirk_detect_quiet_flag:1; + unsigned int ecam_supported:1; + unsigned int no_inbound_map:1; ++ unsigned int quirk_broken_aspm_l0s:1; ++ unsigned int quirk_broken_aspm_l1:1; + }; + + /** +@@ -338,6 +342,21 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) + return cdns_pcie_read_sz(addr, 0x2); + } + ++static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie, ++ u32 reg, u32 value) ++{ ++ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; ++ ++ cdns_pcie_write_sz(addr, 0x4, value); ++} ++ ++static inline u32 cdns_pcie_rp_readl(struct cdns_pcie *pcie, u32 reg) ++{ ++ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; ++ ++ return cdns_pcie_read_sz(addr, 0x4); ++} ++ + static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie, + u32 reg, u8 value) + { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0199-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch b/SPECS/linux-lts-kmhv2/0199-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch deleted file mode 100644 index ac158c2c11..0000000000 --- a/SPECS/linux-lts-kmhv2/0199-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 2d76e75bca7e55bd00d4506359572a867aa1b303 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 23 Dec 2025 10:24:50 +0800 -Subject: [PATCH 199/467] UPSTREAM: mmc: sdhci-of-k1: add reset support - -The SDHCI controller of SpacemiT K1 SoC requires two resets, add -support to explicitly request the reset line and deassert during -initialization phase. Still using devm_xx_get_optional() API to -make the request optional. - -Signed-off-by: Yixun Lan -Reviewed-by: Javier Martinez Canillas -Signed-off-by: Ulf Hansson -(cherry picked from commit 658b716c048684ad13d78280d69b883f181251da) -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index 0cc97e23a2f9..a160e1d5d9bd 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - - #include "sdhci.h" -@@ -223,6 +224,21 @@ static inline int spacemit_sdhci_get_clocks(struct device *dev, - return 0; - } - -+static inline int spacemit_sdhci_get_resets(struct device *dev) -+{ -+ struct reset_control *rst; -+ -+ rst = devm_reset_control_get_optional_shared_deasserted(dev, "axi"); -+ if (IS_ERR(rst)) -+ return PTR_ERR(rst); -+ -+ rst = devm_reset_control_get_optional_exclusive_deasserted(dev, "sdh"); -+ if (IS_ERR(rst)) -+ return PTR_ERR(rst); -+ -+ return 0; -+} -+ - static const struct sdhci_ops spacemit_sdhci_ops = { - .get_max_clock = spacemit_sdhci_clk_get_max_clock, - .reset = spacemit_sdhci_reset, -@@ -284,6 +300,10 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) - if (ret) - goto err_pltfm; - -+ ret = spacemit_sdhci_get_resets(dev); -+ if (ret) -+ goto err_pltfm; -+ - ret = sdhci_add_host(host); - if (ret) - goto err_pltfm; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch b/SPECS/linux-lts-kmhv2/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch new file mode 100644 index 0000000000..863472668a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch @@ -0,0 +1,47 @@ +From b79c6a8e8737f691e21ed1f9492ed9784de03550 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Sun, 5 Apr 2026 15:41:54 +0000 +Subject: [RUYI PATCH] UPSTREAM: PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 + PCIe Root Ports + +Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states +for devicetree platforms") force enables ASPM on all device tree platforms, +the SG2042 Root Ports are breaking as they advertise L0s and L1 +capabilities without supporting them. + +Set ASPM quirks to disable the L0s and L1 capabilities for the Root Ports +so that these broken link states won't be enabled. + +Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042") +Co-developed-by: Inochi Amaoto +Signed-off-by: Inochi Amaoto +Signed-off-by: Yao Zi +[mani: commit log] +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Helgaas +Tested-by: Han Gao +Tested-by: Chen Wang # Pioneerbox +Reviewed-by: Chen Wang +Link: https://patch.msgid.link/20260405154154.46829-3-me@ziyao.cc +(cherry picked from commit 988ef706cdd8a72e61dd90c0d0554eec4df7594a) +Signed-off-by: Han Gao +--- + drivers/pci/controller/cadence/pcie-sg2042.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c +index 0c50c74d03ee..4a2af4d0713e 100644 +--- a/drivers/pci/controller/cadence/pcie-sg2042.c ++++ b/drivers/pci/controller/cadence/pcie-sg2042.c +@@ -48,6 +48,8 @@ static int sg2042_pcie_probe(struct platform_device *pdev) + bridge->child_ops = &sg2042_pcie_child_ops; + + rc = pci_host_bridge_priv(bridge); ++ rc->quirk_broken_aspm_l0s = 1; ++ rc->quirk_broken_aspm_l1 = 1; + pcie = &rc->pcie; + pcie->dev = dev; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0200-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch b/SPECS/linux-lts-kmhv2/0200-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch deleted file mode 100644 index ab4886f545..0000000000 --- a/SPECS/linux-lts-kmhv2/0200-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch +++ /dev/null @@ -1,37 +0,0 @@ -From c062f31f265429d1f2fce4dfb8396648bb008bee Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 22 Jan 2026 17:37:30 +0800 -Subject: [PATCH 200/467] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add - support for K3 SoC - -The SDHCI controller found on SpacemiT K3 SoC share the same IP with -K1 generation, while fixed the broken 64BIT DMA issue. Introduce a -compatible string to enable support for it. - -Acked-by: Rob Herring (Arm) -Signed-off-by: Yixun Lan -Signed-off-by: Ulf Hansson -(cherry picked from commit b4206966e2d48883f04d5a2b2ae6c46b528245d3) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -index 13d9382058fb..383841369fb2 100644 ---- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -+++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -@@ -14,7 +14,9 @@ allOf: - - properties: - compatible: -- const: spacemit,k1-sdhci -+ enum: -+ - spacemit,k1-sdhci -+ - spacemit,k3-sdhci - - reg: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch b/SPECS/linux-lts-kmhv2/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch new file mode 100644 index 0000000000..45d9a8f9de --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch @@ -0,0 +1,51 @@ +From e8797e3dcfc25acbd3f8c8b268ec9d8bd1c28295 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Tue, 10 Mar 2026 00:24:56 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: hwmon: moortec,mr75203: adapt + multipleOf for T-Head TH1520 + +The G and J coefficients provided by T-Head TH1520 manual (which calls +them A and C coefficients and calls H coefficient in the binding as B) +have 1/100 degree Celsius precision (the values are 42.74 and -0.16 +respectively), however the binding currently only allows coefficients as +precise as 100 milli-Celsius (1/10 degree Celsius). + +Change the multipleOf value of these two coefficients to 10 (in the unit +of milli-Celsius) to satisfy the need of TH1520. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Drew Fustini +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20260309162457.4128205-2-zhengxingda@iscas.ac.cn +Signed-off-by: Guenter Roeck +(cherry picked from commit 967ee29c103a44c6e584a5e37401968a69e54a0c) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml +index 56db2292f062..7d57c2934a8a 100644 +--- a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml ++++ b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml +@@ -105,7 +105,7 @@ properties: + G coefficient for temperature equation. + Default for series 5 = 60000 + Default for series 6 = 57400 +- multipleOf: 100 ++ multipleOf: 10 + minimum: 1000 + $ref: /schemas/types.yaml#/definitions/uint32 + +@@ -131,7 +131,7 @@ properties: + J coefficient for temperature equation. + Default for series 5 = -100 + Default for series 6 = 0 +- multipleOf: 100 ++ multipleOf: 10 + maximum: 0 + $ref: /schemas/types.yaml#/definitions/int32 + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0201-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch b/SPECS/linux-lts-kmhv2/0201-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch deleted file mode 100644 index 8b39d10761..0000000000 --- a/SPECS/linux-lts-kmhv2/0201-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch +++ /dev/null @@ -1,62 +0,0 @@ -From bf01dbbc2a84e73472ec8407e03ad78c12a261d7 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 22 Jan 2026 17:37:31 +0800 -Subject: [PATCH 201/467] UPSTREAM: mmc: sdhci-of-k1: spacemit: Add support for - K3 SoC - -The SDHCI controller found on SpacemiT K3 SoC share the same IP with K1 -generation and introduce a compatible data to denote the change that broken -64BIT DMA issue has been fixed. - -Signed-off-by: Yixun Lan -Signed-off-by: Ulf Hansson -(cherry picked from commit 1e9f43a1dbefd3de45b97545e5773d2b52dc7f02) -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 19 +++++++++++++++++-- - 1 file changed, 17 insertions(+), 2 deletions(-) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index a160e1d5d9bd..455656f9842d 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -259,8 +259,20 @@ static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata = { - SDHCI_QUIRK2_PRESET_VALUE_BROKEN, - }; - -+static const struct sdhci_pltfm_data spacemit_sdhci_k3_pdata = { -+ .ops = &spacemit_sdhci_ops, -+ .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | -+ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | -+ SDHCI_QUIRK_32BIT_ADMA_SIZE | -+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | -+ SDHCI_QUIRK_BROKEN_CARD_DETECTION | -+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, -+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, -+}; -+ - static const struct of_device_id spacemit_sdhci_of_match[] = { -- { .compatible = "spacemit,k1-sdhci" }, -+ { .compatible = "spacemit,k1-sdhci", .data = &spacemit_sdhci_k1_pdata }, -+ { .compatible = "spacemit,k3-sdhci", .data = &spacemit_sdhci_k3_pdata }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, spacemit_sdhci_of_match); -@@ -271,10 +283,13 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) - struct spacemit_sdhci_host *sdhst; - struct sdhci_pltfm_host *pltfm_host; - struct sdhci_host *host; -+ const struct sdhci_pltfm_data *data; - struct mmc_host_ops *mops; - int ret; - -- host = sdhci_pltfm_init(pdev, &spacemit_sdhci_k1_pdata, sizeof(*sdhst)); -+ data = of_device_get_match_data(&pdev->dev); -+ -+ host = sdhci_pltfm_init(pdev, data, sizeof(*sdhst)); - if (IS_ERR(host)) - return PTR_ERR(host); - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0202-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch b/SPECS/linux-lts-kmhv2/0202-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch deleted file mode 100644 index f4079da8cb..0000000000 --- a/SPECS/linux-lts-kmhv2/0202-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 666104d46e408b7abf14799de82ab3cefcdf0964 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Sun, 5 Apr 2026 15:41:53 +0000 -Subject: [PATCH 202/467] UPSTREAM: PCI: cadence: Add flags for disabling ASPM - capability for broken Root Ports - -Add flags for disabling the ASPM L0s/L1 capability for broken Root Ports -by clearing the corresponding bits in Link Capabilities Register through -the local management bus. This allows ASPM to be disabled on platforms -which don't support it. - -Signed-off-by: Yao Zi -Signed-off-by: Manivannan Sadhasivam -Signed-off-by: Bjorn Helgaas -Tested-by: Han Gao -Tested-by: Chen Wang # Pioneerbox -Reviewed-by: Chen Wang -Link: https://patch.msgid.link/20260405154154.46829-2-me@ziyao.cc -(cherry picked from commit 5ccc76a87f1ec2422811e61be44165bfc9e7cf54) -Signed-off-by: Han Gao ---- - .../controller/cadence/pcie-cadence-host.c | 7 +++++++ - drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++ - 2 files changed, 26 insertions(+) - -diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c -index db3154c1eccb..0bc9e6e90e0e 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence-host.c -+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c -@@ -147,6 +147,13 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) - cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0); - cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); - -+ value = cdns_pcie_rp_readl(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP); -+ if (rc->quirk_broken_aspm_l0s) -+ value &= ~PCI_EXP_LNKCAP_ASPM_L0S; -+ if (rc->quirk_broken_aspm_l1) -+ value &= ~PCI_EXP_LNKCAP_ASPM_L1; -+ cdns_pcie_rp_writel(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP, value); -+ - return 0; - } - -diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h -index 277f3706a4f4..574e9cf4d003 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence.h -+++ b/drivers/pci/controller/cadence/pcie-cadence.h -@@ -115,6 +115,8 @@ struct cdns_pcie { - * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk - * @ecam_supported: Whether the ECAM is supported - * @no_inbound_map: Whether inbound mapping is supported -+ * @quirk_broken_aspm_l0s: Disable ASPM L0s support as quirk -+ * @quirk_broken_aspm_l1: Disable ASPM L1 support as quirk - */ - struct cdns_pcie_rc { - struct cdns_pcie pcie; -@@ -127,6 +129,8 @@ struct cdns_pcie_rc { - unsigned int quirk_detect_quiet_flag:1; - unsigned int ecam_supported:1; - unsigned int no_inbound_map:1; -+ unsigned int quirk_broken_aspm_l0s:1; -+ unsigned int quirk_broken_aspm_l1:1; - }; - - /** -@@ -338,6 +342,21 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) - return cdns_pcie_read_sz(addr, 0x2); - } - -+static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie, -+ u32 reg, u32 value) -+{ -+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; -+ -+ cdns_pcie_write_sz(addr, 0x4, value); -+} -+ -+static inline u32 cdns_pcie_rp_readl(struct cdns_pcie *pcie, u32 reg) -+{ -+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; -+ -+ return cdns_pcie_read_sz(addr, 0x4); -+} -+ - static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie, - u32 reg, u8 value) - { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch b/SPECS/linux-lts-kmhv2/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch new file mode 100644 index 0000000000..3011e77bd5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch @@ -0,0 +1,116 @@ +From 42218f60a7def59ca6f9513365c5aed9fb77a124 Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Tue, 10 Mar 2026 11:41:12 +0000 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Disable interrupts before + suspending the GPU + +This is an additional safety layer to ensure no accesses to the GPU +registers can be made while it is powered off. + +While we can disable IRQ generation from GPU, META firmware, MIPS +firmware and for safety events, we cannot do the same for the RISC-V +firmware. +To keep a unified approach, once the firmware has completed its power +off sequence, disable IRQs for the while GPU at the kernel level +instead. + +Signed-off-by: Alessio Belle +Reviewed-by: Matt Coster +Link: https://patch.msgid.link/20260310-drain-irqs-before-suspend-v1-2-bf4f9ed68e75@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 74ef7844dd8c27d6b94ebc102bb4677edd3e7696) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_power.c | 33 +++++++++++++++++-------- + 1 file changed, 23 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imagination/pvr_power.c +index a7994457900d..c03bbf139562 100644 +--- a/drivers/gpu/drm/imagination/pvr_power.c ++++ b/drivers/gpu/drm/imagination/pvr_power.c +@@ -91,9 +91,9 @@ pvr_power_request_pwr_off(struct pvr_device *pvr_dev) + static int + pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm_suspend) + { +- if (!hard_reset) { +- int err; ++ int err; + ++ if (!hard_reset) { + cancel_delayed_work_sync(&pvr_dev->watchdog.work); + + err = pvr_power_request_idle(pvr_dev); +@@ -106,33 +106,46 @@ pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm_suspe + } + + if (rpm_suspend) { +- /* Wait for late processing of GPU or firmware IRQs in other cores */ +- synchronize_irq(pvr_dev->irq); ++ /* This also waits for late processing of GPU or firmware IRQs in other cores */ ++ disable_irq(pvr_dev->irq); + } + +- return pvr_fw_stop(pvr_dev); ++ err = pvr_fw_stop(pvr_dev); ++ if (err && rpm_suspend) ++ enable_irq(pvr_dev->irq); ++ ++ return err; + } + + static int +-pvr_power_fw_enable(struct pvr_device *pvr_dev) ++pvr_power_fw_enable(struct pvr_device *pvr_dev, bool rpm_resume) + { + int err; + ++ if (rpm_resume) ++ enable_irq(pvr_dev->irq); ++ + err = pvr_fw_start(pvr_dev); + if (err) +- return err; ++ goto out; + + err = pvr_wait_for_fw_boot(pvr_dev); + if (err) { + drm_err(from_pvr_device(pvr_dev), "Firmware failed to boot\n"); + pvr_fw_stop(pvr_dev); +- return err; ++ goto out; + } + + queue_delayed_work(pvr_dev->sched_wq, &pvr_dev->watchdog.work, + msecs_to_jiffies(WATCHDOG_TIME_MS)); + + return 0; ++ ++out: ++ if (rpm_resume) ++ disable_irq(pvr_dev->irq); ++ ++ return err; + } + + bool +@@ -395,7 +408,7 @@ pvr_power_device_resume(struct device *dev) + goto err_drm_dev_exit; + + if (pvr_dev->fw_dev.booted) { +- err = pvr_power_fw_enable(pvr_dev); ++ err = pvr_power_fw_enable(pvr_dev, true); + if (err) + goto err_power_off; + } +@@ -554,7 +567,7 @@ pvr_power_reset(struct pvr_device *pvr_dev, bool hard_reset) + + pvr_fw_irq_clear(pvr_dev); + +- err = pvr_power_fw_enable(pvr_dev); ++ err = pvr_power_fw_enable(pvr_dev, false); + } + + if (err && hard_reset) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0203-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch b/SPECS/linux-lts-kmhv2/0203-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch deleted file mode 100644 index 9fcf206ede..0000000000 --- a/SPECS/linux-lts-kmhv2/0203-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 97c5f5dec6275526d950871d6697610efd8bbfc9 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Sun, 5 Apr 2026 15:41:54 +0000 -Subject: [PATCH 203/467] UPSTREAM: PCI: sg2042: Avoid L0s and L1 on Sophgo - 2042 PCIe Root Ports - -Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states -for devicetree platforms") force enables ASPM on all device tree platforms, -the SG2042 Root Ports are breaking as they advertise L0s and L1 -capabilities without supporting them. - -Set ASPM quirks to disable the L0s and L1 capabilities for the Root Ports -so that these broken link states won't be enabled. - -Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042") -Co-developed-by: Inochi Amaoto -Signed-off-by: Inochi Amaoto -Signed-off-by: Yao Zi -[mani: commit log] -Signed-off-by: Manivannan Sadhasivam -Signed-off-by: Bjorn Helgaas -Tested-by: Han Gao -Tested-by: Chen Wang # Pioneerbox -Reviewed-by: Chen Wang -Link: https://patch.msgid.link/20260405154154.46829-3-me@ziyao.cc -(cherry picked from commit 988ef706cdd8a72e61dd90c0d0554eec4df7594a) -Signed-off-by: Han Gao ---- - drivers/pci/controller/cadence/pcie-sg2042.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c -index 0c50c74d03ee..4a2af4d0713e 100644 ---- a/drivers/pci/controller/cadence/pcie-sg2042.c -+++ b/drivers/pci/controller/cadence/pcie-sg2042.c -@@ -48,6 +48,8 @@ static int sg2042_pcie_probe(struct platform_device *pdev) - bridge->child_ops = &sg2042_pcie_child_ops; - - rc = pci_host_bridge_priv(bridge); -+ rc->quirk_broken_aspm_l0s = 1; -+ rc->quirk_broken_aspm_l1 = 1; - pcie = &rc->pcie; - pcie->dev = dev; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch b/SPECS/linux-lts-kmhv2/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch new file mode 100644 index 0000000000..97daa0a8b0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch @@ -0,0 +1,104 @@ +From 9714f16b48717549d0332bbcd37661290bf0a765 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:20 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add DPU and HDMI device + tree nodes + +T-Head TH1520 SoC contains a Verisilicon DC8200 display controller +(called DPU in manual) and a Synopsys DesignWare HDMI TX controller. + +Add device tree nodes to them. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Tested-by: Han Gao +Tested-by: Michal Wilczynski +Reviewed-by: Drew Fustini +Reviewed-by: Luca Ceresoli +Signed-off-by: Drew Fustini +(cherry picked from commit 5634f777a6a94db316f9b26c00525320c3b582c2) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 66 +++++++++++++++++++++++++++ + 1 file changed, 66 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index c24d6b779fa4..aa6c9afa1a20 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -555,6 +555,72 @@ clk_vo: clock-controller@ffef528050 { + #clock-cells = <1>; + }; + ++ hdmi: hdmi@ffef540000 { ++ compatible = "thead,th1520-dw-hdmi"; ++ reg = <0xff 0xef540000 0x0 0x40000>; ++ reg-io-width = <4>; ++ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_vo CLK_HDMI_PCLK>, ++ <&clk_vo CLK_HDMI_SFR>, ++ <&clk_vo CLK_HDMI_CEC>, ++ <&clk_vo CLK_HDMI_PIXCLK>; ++ clock-names = "iahb", "isfr", "cec", "pix"; ++ resets = <&rst TH1520_RESET_ID_HDMI>, ++ <&rst TH1520_RESET_ID_HDMI_APB>; ++ reset-names = "main", "apb"; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ hdmi_in: endpoint { ++ remote-endpoint = <&dpu_out_dp1>; ++ }; ++ }; ++ ++ hdmi_out_port: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ ++ dpu: display@ffef600000 { ++ compatible = "thead,th1520-dc8200", "verisilicon,dc"; ++ reg = <0xff 0xef600000 0x0 0x100000>; ++ interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_vo CLK_DPU_CCLK>, ++ <&clk_vo CLK_DPU_ACLK>, ++ <&clk_vo CLK_DPU_HCLK>, ++ <&clk_vo CLK_DPU_PIXELCLK0>, ++ <&clk_vo CLK_DPU_PIXELCLK1>; ++ clock-names = "core", "axi", "ahb", "pix0", "pix1"; ++ resets = <&rst TH1520_RESET_ID_DPU_CORE>, ++ <&rst TH1520_RESET_ID_DPU_AXI>, ++ <&rst TH1520_RESET_ID_DPU_AHB>; ++ reset-names = "core", "axi", "ahb"; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dpu_port1: port@1 { ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dpu_out_dp1: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&hdmi_in>; ++ }; ++ }; ++ }; ++ }; ++ + dmac0: dma-controller@ffefc00000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0xff 0xefc00000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0204-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch b/SPECS/linux-lts-kmhv2/0204-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch deleted file mode 100644 index 2ddec8736f..0000000000 --- a/SPECS/linux-lts-kmhv2/0204-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 9fa99cb8701fa1bb6152da334dca564f23e9f456 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Tue, 10 Mar 2026 00:24:56 +0800 -Subject: [PATCH 204/467] UPSTREAM: dt-bindings: hwmon: moortec,mr75203: adapt - multipleOf for T-Head TH1520 - -The G and J coefficients provided by T-Head TH1520 manual (which calls -them A and C coefficients and calls H coefficient in the binding as B) -have 1/100 degree Celsius precision (the values are 42.74 and -0.16 -respectively), however the binding currently only allows coefficients as -precise as 100 milli-Celsius (1/10 degree Celsius). - -Change the multipleOf value of these two coefficients to 10 (in the unit -of milli-Celsius) to satisfy the need of TH1520. - -Signed-off-by: Icenowy Zheng -Reviewed-by: Drew Fustini -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20260309162457.4128205-2-zhengxingda@iscas.ac.cn -Signed-off-by: Guenter Roeck -(cherry picked from commit 967ee29c103a44c6e584a5e37401968a69e54a0c) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml -index 56db2292f062..7d57c2934a8a 100644 ---- a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml -+++ b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml -@@ -105,7 +105,7 @@ properties: - G coefficient for temperature equation. - Default for series 5 = 60000 - Default for series 6 = 57400 -- multipleOf: 100 -+ multipleOf: 10 - minimum: 1000 - $ref: /schemas/types.yaml#/definitions/uint32 - -@@ -131,7 +131,7 @@ properties: - J coefficient for temperature equation. - Default for series 5 = -100 - Default for series 6 = 0 -- multipleOf: 100 -+ multipleOf: 10 - maximum: 0 - $ref: /schemas/types.yaml#/definitions/int32 - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch b/SPECS/linux-lts-kmhv2/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch new file mode 100644 index 0000000000..df92d3aeea --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch @@ -0,0 +1,70 @@ +From 4633a7a2c68426c3f3fc28382fd6cba7df6134d8 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:21 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: lichee-pi-4a: enable HDMI + +Lichee Pi 4A board features a HDMI Type-A connector connected to the +HDMI TX controller of TH1520 SoC. + +Add a device tree node describing the connector, connect it to the HDMI +controller, and enable everything on this display pipeline. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Tested-by: Han Gao +Tested-by: Michal Wilczynski +Reviewed-by: Luca Ceresoli +Reviewed-by: Drew Fustini +Signed-off-by: Drew Fustini +(cherry picked from commit 9c99a784d9117a192ebf779d4f72ebec435ada97) +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 25 +++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index c58c2085ca92..7cb7d28683bc 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -29,6 +29,17 @@ chosen { + stdout-path = "serial0:115200n8"; + }; + ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + thermal-zones { + cpu-thermal { + polling-delay = <1000>; +@@ -121,6 +132,20 @@ rx-pins { + }; + }; + ++&dpu { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out_port { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0205-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch b/SPECS/linux-lts-kmhv2/0205-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch deleted file mode 100644 index eb78cafb3a..0000000000 --- a/SPECS/linux-lts-kmhv2/0205-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch +++ /dev/null @@ -1,116 +0,0 @@ -From 2575af4e9ef38dd97f241b4be5afd8a68de35365 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Tue, 10 Mar 2026 11:41:12 +0000 -Subject: [PATCH 205/467] UPSTREAM: drm/imagination: Disable interrupts before - suspending the GPU - -This is an additional safety layer to ensure no accesses to the GPU -registers can be made while it is powered off. - -While we can disable IRQ generation from GPU, META firmware, MIPS -firmware and for safety events, we cannot do the same for the RISC-V -firmware. -To keep a unified approach, once the firmware has completed its power -off sequence, disable IRQs for the while GPU at the kernel level -instead. - -Signed-off-by: Alessio Belle -Reviewed-by: Matt Coster -Link: https://patch.msgid.link/20260310-drain-irqs-before-suspend-v1-2-bf4f9ed68e75@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 74ef7844dd8c27d6b94ebc102bb4677edd3e7696) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_power.c | 33 +++++++++++++++++-------- - 1 file changed, 23 insertions(+), 10 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imagination/pvr_power.c -index a7994457900d..c03bbf139562 100644 ---- a/drivers/gpu/drm/imagination/pvr_power.c -+++ b/drivers/gpu/drm/imagination/pvr_power.c -@@ -91,9 +91,9 @@ pvr_power_request_pwr_off(struct pvr_device *pvr_dev) - static int - pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm_suspend) - { -- if (!hard_reset) { -- int err; -+ int err; - -+ if (!hard_reset) { - cancel_delayed_work_sync(&pvr_dev->watchdog.work); - - err = pvr_power_request_idle(pvr_dev); -@@ -106,33 +106,46 @@ pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm_suspe - } - - if (rpm_suspend) { -- /* Wait for late processing of GPU or firmware IRQs in other cores */ -- synchronize_irq(pvr_dev->irq); -+ /* This also waits for late processing of GPU or firmware IRQs in other cores */ -+ disable_irq(pvr_dev->irq); - } - -- return pvr_fw_stop(pvr_dev); -+ err = pvr_fw_stop(pvr_dev); -+ if (err && rpm_suspend) -+ enable_irq(pvr_dev->irq); -+ -+ return err; - } - - static int --pvr_power_fw_enable(struct pvr_device *pvr_dev) -+pvr_power_fw_enable(struct pvr_device *pvr_dev, bool rpm_resume) - { - int err; - -+ if (rpm_resume) -+ enable_irq(pvr_dev->irq); -+ - err = pvr_fw_start(pvr_dev); - if (err) -- return err; -+ goto out; - - err = pvr_wait_for_fw_boot(pvr_dev); - if (err) { - drm_err(from_pvr_device(pvr_dev), "Firmware failed to boot\n"); - pvr_fw_stop(pvr_dev); -- return err; -+ goto out; - } - - queue_delayed_work(pvr_dev->sched_wq, &pvr_dev->watchdog.work, - msecs_to_jiffies(WATCHDOG_TIME_MS)); - - return 0; -+ -+out: -+ if (rpm_resume) -+ disable_irq(pvr_dev->irq); -+ -+ return err; - } - - bool -@@ -395,7 +408,7 @@ pvr_power_device_resume(struct device *dev) - goto err_drm_dev_exit; - - if (pvr_dev->fw_dev.booted) { -- err = pvr_power_fw_enable(pvr_dev); -+ err = pvr_power_fw_enable(pvr_dev, true); - if (err) - goto err_power_off; - } -@@ -554,7 +567,7 @@ pvr_power_reset(struct pvr_device *pvr_dev, bool hard_reset) - - pvr_fw_irq_clear(pvr_dev); - -- err = pvr_power_fw_enable(pvr_dev); -+ err = pvr_power_fw_enable(pvr_dev, false); - } - - if (err && hard_reset) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch b/SPECS/linux-lts-kmhv2/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch new file mode 100644 index 0000000000..dfee292fb6 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch @@ -0,0 +1,39 @@ +From 00020f3b46c3943b6ce714ac17de5fd1573b399b Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Tue, 10 Mar 2026 00:24:57 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: th1520: add coefficients to + the PVT node + +The manual of TH1520 contains a set of coefficients a little different +to the driver default ones. + +Add them to the device tree node of PVT. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Reviewed-by: Drew Fustini +Signed-off-by: Drew Fustini +(cherry picked from commit a7aa874b69460896349985833059a764e688f1d0) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index aa6c9afa1a20..c65b71d9a1b8 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -782,6 +782,10 @@ pvt: pvt@fffff4e000 { + reg-names = "common", "ts", "pd", "vm"; + clocks = <&aonsys_clk>; + #thermal-sensor-cells = <1>; ++ moortec,ts-coeff-g = <42740>; ++ moortec,ts-coeff-h = <220500>; ++ moortec,ts-coeff-j = <(-160)>; ++ moortec,ts-coeff-cal5 = <4094>; + }; + + gpio@fffff52000 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0206-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch b/SPECS/linux-lts-kmhv2/0206-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch deleted file mode 100644 index 279438ed87..0000000000 --- a/SPECS/linux-lts-kmhv2/0206-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 889a08c4fbd66cd2cccce2fe6c281d18a78edf6f Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:20 +0800 -Subject: [PATCH 206/467] UPSTREAM: riscv: dts: thead: add DPU and HDMI device - tree nodes - -T-Head TH1520 SoC contains a Verisilicon DC8200 display controller -(called DPU in manual) and a Synopsys DesignWare HDMI TX controller. - -Add device tree nodes to them. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Tested-by: Han Gao -Tested-by: Michal Wilczynski -Reviewed-by: Drew Fustini -Reviewed-by: Luca Ceresoli -Signed-off-by: Drew Fustini -(cherry picked from commit 5634f777a6a94db316f9b26c00525320c3b582c2) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 66 +++++++++++++++++++++++++++ - 1 file changed, 66 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index c24d6b779fa4..aa6c9afa1a20 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -555,6 +555,72 @@ clk_vo: clock-controller@ffef528050 { - #clock-cells = <1>; - }; - -+ hdmi: hdmi@ffef540000 { -+ compatible = "thead,th1520-dw-hdmi"; -+ reg = <0xff 0xef540000 0x0 0x40000>; -+ reg-io-width = <4>; -+ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_vo CLK_HDMI_PCLK>, -+ <&clk_vo CLK_HDMI_SFR>, -+ <&clk_vo CLK_HDMI_CEC>, -+ <&clk_vo CLK_HDMI_PIXCLK>; -+ clock-names = "iahb", "isfr", "cec", "pix"; -+ resets = <&rst TH1520_RESET_ID_HDMI>, -+ <&rst TH1520_RESET_ID_HDMI_APB>; -+ reset-names = "main", "apb"; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ hdmi_in: endpoint { -+ remote-endpoint = <&dpu_out_dp1>; -+ }; -+ }; -+ -+ hdmi_out_port: port@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ -+ dpu: display@ffef600000 { -+ compatible = "thead,th1520-dc8200", "verisilicon,dc"; -+ reg = <0xff 0xef600000 0x0 0x100000>; -+ interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_vo CLK_DPU_CCLK>, -+ <&clk_vo CLK_DPU_ACLK>, -+ <&clk_vo CLK_DPU_HCLK>, -+ <&clk_vo CLK_DPU_PIXELCLK0>, -+ <&clk_vo CLK_DPU_PIXELCLK1>; -+ clock-names = "core", "axi", "ahb", "pix0", "pix1"; -+ resets = <&rst TH1520_RESET_ID_DPU_CORE>, -+ <&rst TH1520_RESET_ID_DPU_AXI>, -+ <&rst TH1520_RESET_ID_DPU_AHB>; -+ reset-names = "core", "axi", "ahb"; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dpu_port1: port@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dpu_out_dp1: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&hdmi_in>; -+ }; -+ }; -+ }; -+ }; -+ - dmac0: dma-controller@ffefc00000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0xff 0xefc00000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch b/SPECS/linux-lts-kmhv2/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch new file mode 100644 index 0000000000..03da857375 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch @@ -0,0 +1,67 @@ +From 1cce6a25c0cf7aab271eb21e6d8b9ed58ed13b84 Mon Sep 17 00:00:00 2001 +From: Robert Mazur +Date: Wed, 25 Mar 2026 09:18:59 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: beaglev-ahead: enable HDMI + output + +The BeagleV Ahead board includes a micro HDMI connector (Type-D) +wired to the TH1520 SoC's HDMI transmitter. + +Enable the display pipeline by adding the HDMI connector node, +connecting it to the HDMI controller, and activating the DPU +and HDMI nodes. + +Signed-off-by: Robert Mazur +Signed-off-by: Drew Fustini +(cherry picked from commit 74ec3d52c0035b662ec295bef2bbffad68446391) +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-beaglev-ahead.dts | 25 +++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +index 21c33f165ba9..91f3f9b987bc 100644 +--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts ++++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +@@ -75,6 +75,17 @@ led-5 { + label = "led5"; + }; + }; ++ ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "d"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; + }; + + &osc { +@@ -236,6 +247,20 @@ &sdio0 { + status = "okay"; + }; + ++&dpu { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out_port { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch b/SPECS/linux-lts-kmhv2/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch new file mode 100644 index 0000000000..0128ba9bc1 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch @@ -0,0 +1,107 @@ +From d2ce0203a4d1455b03013278280f7ac698fce115 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Sat, 7 Feb 2026 23:08:21 +0800 +Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: move i2c_xfer_msg() + +The upcoming PIO support requires a wait_pio_xfer() helper, which is +invoked from xfer_msg(). + +Since wait_pio_xfer() depends on err_check(), move the definition of +xfer_msg() after err_check() to avoid a forward declaration of +err_check(). + +Reviewed-by: Aurelien Jarno +Reviewed-by: Alex Elder +Signed-off-by: Troy Mitchell +Tested-by: Aurelien Jarno +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20260207-b4-k3-i2c-pio-v7-1-626942d94d91@linux.spacemit.com +(cherry picked from commit 5b74da8e6cf7e2b5aed0836c733238c0fd7235af) +Signed-off-by: Han Gao +--- + drivers/i2c/busses/i2c-k1.c | 62 ++++++++++++++++++------------------- + 1 file changed, 31 insertions(+), 31 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index d0948a16de3e..6787a51e7391 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -305,37 +305,6 @@ static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) + writel(val, i2c->base + SPACEMIT_ICR); + } + +-static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) +-{ +- unsigned long time_left; +- struct i2c_msg *msg; +- +- for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { +- msg = &i2c->msgs[i2c->msg_idx]; +- i2c->msg_buf = msg->buf; +- i2c->unprocessed = msg->len; +- i2c->status = 0; +- +- reinit_completion(&i2c->complete); +- +- spacemit_i2c_start(i2c); +- +- time_left = wait_for_completion_timeout(&i2c->complete, +- i2c->adapt.timeout); +- if (!time_left) { +- dev_err(i2c->dev, "msg completion timeout\n"); +- spacemit_i2c_conditionally_reset_bus(i2c); +- spacemit_i2c_reset(i2c); +- return -ETIMEDOUT; +- } +- +- if (i2c->status & SPACEMIT_SR_ERR) +- return spacemit_i2c_handle_err(i2c); +- } +- +- return 0; +-} +- + static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c) + { + if (i2c->msg_idx != i2c->msg_num - 1) +@@ -419,6 +388,37 @@ static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c) + complete(&i2c->complete); + } + ++static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) ++{ ++ unsigned long time_left; ++ struct i2c_msg *msg; ++ ++ for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { ++ msg = &i2c->msgs[i2c->msg_idx]; ++ i2c->msg_buf = msg->buf; ++ i2c->unprocessed = msg->len; ++ i2c->status = 0; ++ ++ reinit_completion(&i2c->complete); ++ ++ spacemit_i2c_start(i2c); ++ ++ time_left = wait_for_completion_timeout(&i2c->complete, ++ i2c->adapt.timeout); ++ if (!time_left) { ++ dev_err(i2c->dev, "msg completion timeout\n"); ++ spacemit_i2c_conditionally_reset_bus(i2c); ++ spacemit_i2c_reset(i2c); ++ return -ETIMEDOUT; ++ } ++ ++ if (i2c->status & SPACEMIT_SR_ERR) ++ return spacemit_i2c_handle_err(i2c); ++ } ++ ++ return 0; ++} ++ + static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) + { + struct spacemit_i2c_dev *i2c = devid; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0207-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch b/SPECS/linux-lts-kmhv2/0207-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch deleted file mode 100644 index e9c9006b5c..0000000000 --- a/SPECS/linux-lts-kmhv2/0207-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch +++ /dev/null @@ -1,71 +0,0 @@ -From efdb5c77db11f97a43075c7a399a52fb4beeadf1 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:21 +0800 -Subject: [PATCH 207/467] UPSTREAM: riscv: dts: thead: lichee-pi-4a: enable - HDMI - -Lichee Pi 4A board features a HDMI Type-A connector connected to the -HDMI TX controller of TH1520 SoC. - -Add a device tree node describing the connector, connect it to the HDMI -controller, and enable everything on this display pipeline. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Tested-by: Han Gao -Tested-by: Michal Wilczynski -Reviewed-by: Luca Ceresoli -Reviewed-by: Drew Fustini -Signed-off-by: Drew Fustini -(cherry picked from commit 9c99a784d9117a192ebf779d4f72ebec435ada97) -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-lichee-pi-4a.dts | 25 +++++++++++++++++++ - 1 file changed, 25 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -index c58c2085ca92..7cb7d28683bc 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -@@ -29,6 +29,17 @@ chosen { - stdout-path = "serial0:115200n8"; - }; - -+ hdmi-connector { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - thermal-zones { - cpu-thermal { - polling-delay = <1000>; -@@ -121,6 +132,20 @@ rx-pins { - }; - }; - -+&dpu { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out_port { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch b/SPECS/linux-lts-kmhv2/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch new file mode 100644 index 0000000000..34101370a3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch @@ -0,0 +1,487 @@ +From 4fa4815280ddada7e960eb90a9ccccd015916c00 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Sat, 7 Feb 2026 23:08:22 +0800 +Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: introduce pio for k1 + +This patch introduces I2C PIO functionality for the Spacemit K1 SoC, +enabling the use of I2C in atomic context. + +When i2c xfer_atomic is invoked, use_pio is set accordingly. + +Since an atomic context is required, all interrupts are disabled when +operating in PIO mode. Even with interrupts disabled, the bits in the +ISR (Interrupt Status Register) will still be set, so error handling can +be performed by polling the relevant status bits in the ISR. + +Signed-off-by: Troy Mitchell +Tested-by: Aurelien Jarno +Reviewed-by: Aurelien Jarno +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20260207-b4-k3-i2c-pio-v7-2-626942d94d91@linux.spacemit.com +(cherry picked from commit 5dd75dac1b35e5b24f5051d01fc85105adcc2e15) +Signed-off-by: Han Gao +--- + drivers/i2c/busses/i2c-k1.c | 300 +++++++++++++++++++++++++++--------- + 1 file changed, 228 insertions(+), 72 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index 6787a51e7391..afc6bdd68bd4 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -98,6 +98,10 @@ + + #define SPACEMIT_BUS_RESET_CLK_CNT_MAX 9 + ++#define SPACEMIT_WAIT_TIMEOUT 1000 /* ms */ ++#define SPACEMIT_POLL_TIMEOUT 1000 /* us */ ++#define SPACEMIT_POLL_INTERVAL 30 /* us */ ++ + enum spacemit_i2c_state { + SPACEMIT_STATE_IDLE, + SPACEMIT_STATE_START, +@@ -126,6 +130,7 @@ struct spacemit_i2c_dev { + + enum spacemit_i2c_state state; + bool read; ++ bool use_pio; + struct completion complete; + u32 status; + }; +@@ -172,6 +177,14 @@ static int spacemit_i2c_handle_err(struct spacemit_i2c_dev *i2c) + return i2c->status & SPACEMIT_SR_ACKNAK ? -ENXIO : -EIO; + } + ++static inline void spacemit_i2c_delay(struct spacemit_i2c_dev *i2c, unsigned int us) ++{ ++ if (i2c->use_pio) ++ udelay(us); ++ else ++ fsleep(us); ++} ++ + static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c) + { + u32 status; +@@ -183,7 +196,8 @@ static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c) + return; + + spacemit_i2c_reset(i2c); +- usleep_range(10, 20); ++ ++ spacemit_i2c_delay(i2c, 10); + + for (clk_cnt = 0; clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX; clk_cnt++) { + status = readl(i2c->base + SPACEMIT_IBMR); +@@ -212,9 +226,15 @@ static int spacemit_i2c_wait_bus_idle(struct spacemit_i2c_dev *i2c) + if (!(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB))) + return 0; + +- ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, +- val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), +- 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); ++ if (i2c->use_pio) ++ ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, ++ val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), ++ 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); ++ else ++ ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, ++ val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), ++ 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); ++ + if (ret) + spacemit_i2c_reset(i2c); + +@@ -226,7 +246,7 @@ static void spacemit_i2c_check_bus_release(struct spacemit_i2c_dev *i2c) + /* in case bus is not released after transfer completes */ + if (readl(i2c->base + SPACEMIT_ISR) & SPACEMIT_SR_EBB) { + spacemit_i2c_conditionally_reset_bus(i2c); +- usleep_range(90, 150); ++ spacemit_i2c_delay(i2c, 90); + } + } + +@@ -238,25 +258,33 @@ spacemit_i2c_clear_int_status(struct spacemit_i2c_dev *i2c, u32 mask) + + static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) + { +- u32 val; +- +- /* +- * Unmask interrupt bits for all xfer mode: +- * bus error, arbitration loss detected. +- * For transaction complete signal, we use master stop +- * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. +- */ +- val = SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; +- +- /* +- * Unmask interrupt bits for interrupt xfer mode: +- * When IDBR receives a byte, an interrupt is triggered. +- * +- * For the tx empty interrupt, it will be enabled in the +- * i2c_start function. +- * Otherwise, it will cause an erroneous empty interrupt before i2c_start. +- */ +- val |= SPACEMIT_CR_DRFIE; ++ u32 val = 0; ++ ++ if (!i2c->use_pio) { ++ /* ++ * Enable interrupt bits for all xfer mode: ++ * bus error, arbitration loss detected. ++ */ ++ val |= SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; ++ ++ /* ++ * Unmask interrupt bits for interrupt xfer mode: ++ * When IDBR receives a byte, an interrupt is triggered. ++ * ++ * For the tx empty interrupt, it will be enabled in the ++ * i2c_start(). ++ * We don't want a TX empty interrupt until we start ++ * a transfer in i2c_start(). ++ */ ++ val |= SPACEMIT_CR_DRFIE; ++ ++ /* ++ * Enable master stop interrupt bit. ++ * For transaction complete signal, we use master stop ++ * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. ++ */ ++ val |= SPACEMIT_CR_MSDIE; ++ } + + if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) + val |= SPACEMIT_CR_MODE_FAST; +@@ -268,7 +296,7 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) + val |= SPACEMIT_CR_SCLE; + + /* enable master stop detected */ +- val |= SPACEMIT_CR_MSDE | SPACEMIT_CR_MSDIE; ++ val |= SPACEMIT_CR_MSDE; + + writel(val, i2c->base + SPACEMIT_ICR); + +@@ -301,7 +329,12 @@ static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) + /* send start pulse */ + val = readl(i2c->base + SPACEMIT_ICR); + val &= ~SPACEMIT_CR_STOP; +- val |= SPACEMIT_CR_START | SPACEMIT_CR_TB | SPACEMIT_CR_DTEIE; ++ val |= SPACEMIT_CR_START | SPACEMIT_CR_TB; ++ ++ /* Enable the TX empty interrupt */ ++ if (!i2c->use_pio) ++ val |= SPACEMIT_CR_DTEIE; ++ + writel(val, i2c->base + SPACEMIT_ICR); + } + +@@ -316,8 +349,23 @@ static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c) + return !i2c->unprocessed; + } + ++static inline void spacemit_i2c_complete(struct spacemit_i2c_dev *i2c) ++{ ++ /* SPACEMIT_STATE_IDLE avoids triggering the next byte */ ++ i2c->state = SPACEMIT_STATE_IDLE; ++ ++ if (i2c->use_pio) ++ return; ++ ++ complete(&i2c->complete); ++} ++ + static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c) + { ++ /* If there's no space in the IDBR, we're done */ ++ if (!(i2c->status & SPACEMIT_SR_ITE)) ++ return; ++ + /* if transfer completes, SPACEMIT_ISR will handle it */ + if (i2c->status & SPACEMIT_SR_MSD) + return; +@@ -328,16 +376,19 @@ static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c) + return; + } + +- /* SPACEMIT_STATE_IDLE avoids trigger next byte */ +- i2c->state = SPACEMIT_STATE_IDLE; +- complete(&i2c->complete); ++ spacemit_i2c_complete(i2c); + } + + static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c) + { ++ /* If there's nothing in the IDBR, we're done */ ++ if (!(i2c->status & SPACEMIT_SR_IRF)) ++ return; ++ + if (i2c->unprocessed) { + *i2c->msg_buf++ = readl(i2c->base + SPACEMIT_IDBR); + i2c->unprocessed--; ++ return; + } + + /* if transfer completes, SPACEMIT_ISR will handle it */ +@@ -348,9 +399,7 @@ static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c) + if (i2c->unprocessed) + return; + +- /* SPACEMIT_STATE_IDLE avoids trigger next byte */ +- i2c->state = SPACEMIT_STATE_IDLE; +- complete(&i2c->complete); ++ spacemit_i2c_complete(i2c); + } + + static void spacemit_i2c_handle_start(struct spacemit_i2c_dev *i2c) +@@ -384,8 +433,129 @@ static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c) + + spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); + +- i2c->state = SPACEMIT_STATE_IDLE; +- complete(&i2c->complete); ++ spacemit_i2c_complete(i2c); ++} ++ ++static void spacemit_i2c_handle_state(struct spacemit_i2c_dev *i2c) ++{ ++ u32 val; ++ ++ if (i2c->status & SPACEMIT_SR_ERR) ++ goto err_out; ++ ++ switch (i2c->state) { ++ case SPACEMIT_STATE_START: ++ spacemit_i2c_handle_start(i2c); ++ break; ++ case SPACEMIT_STATE_READ: ++ spacemit_i2c_handle_read(i2c); ++ break; ++ case SPACEMIT_STATE_WRITE: ++ spacemit_i2c_handle_write(i2c); ++ break; ++ default: ++ break; ++ } ++ ++ if (i2c->state != SPACEMIT_STATE_IDLE) { ++ val = readl(i2c->base + SPACEMIT_ICR); ++ val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | ++ SPACEMIT_CR_STOP | SPACEMIT_CR_START); ++ val |= SPACEMIT_CR_TB; ++ if (!i2c->use_pio) ++ val |= SPACEMIT_CR_ALDIE; ++ ++ if (spacemit_i2c_is_last_msg(i2c)) { ++ /* trigger next byte with stop */ ++ val |= SPACEMIT_CR_STOP; ++ ++ if (i2c->read) ++ val |= SPACEMIT_CR_ACKNAK; ++ } ++ writel(val, i2c->base + SPACEMIT_ICR); ++ } ++ ++err_out: ++ spacemit_i2c_err_check(i2c); ++} ++ ++/* ++ * In PIO mode, this function is used as a replacement for ++ * wait_for_completion_timeout(), whose return value indicates ++ * the remaining time. ++ * ++ * We do not have a meaningful remaining-time value here, so ++ * return a non-zero value on success to indicate "not timed out". ++ * Returning 1 ensures callers treating the return value as ++ * time_left will not incorrectly report a timeout. ++ */ ++static int spacemit_i2c_wait_pio_xfer(struct spacemit_i2c_dev *i2c) ++{ ++ u32 mask, msec = jiffies_to_msecs(i2c->adapt.timeout); ++ ktime_t timeout = ktime_add_ms(ktime_get(), msec); ++ int ret; ++ ++ mask = SPACEMIT_SR_IRF | SPACEMIT_SR_ITE; ++ ++ do { ++ i2c->status = readl(i2c->base + SPACEMIT_ISR); ++ ++ spacemit_i2c_clear_int_status(i2c, i2c->status); ++ ++ if (i2c->status & mask) ++ spacemit_i2c_handle_state(i2c); ++ else ++ udelay(SPACEMIT_POLL_INTERVAL); ++ } while (i2c->unprocessed && ktime_compare(ktime_get(), timeout) < 0); ++ ++ if (i2c->unprocessed) ++ return 0; ++ ++ if (i2c->read) ++ return 1; ++ ++ /* ++ * If this is the last byte to write of the current message, ++ * we have to wait here. Otherwise, control will proceed directly ++ * to start(), which would overwrite the current data. ++ */ ++ ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, ++ i2c->status, i2c->status & SPACEMIT_SR_ITE, ++ SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT); ++ if (ret) ++ return 0; ++ ++ /* ++ * For writes: in interrupt mode, an ITE (write-empty) interrupt is triggered ++ * after the last byte, and the MSD-related handling takes place there. ++ * In PIO mode, however, we need to explicitly call err_check() to emulate this ++ * step, otherwise the next transfer will fail. ++ */ ++ if (i2c->msg_idx == i2c->msg_num - 1) { ++ mask = SPACEMIT_SR_MSD | SPACEMIT_SR_ERR; ++ /* ++ * In some cases, MSD may not arrive immediately; ++ * wait here to handle that. ++ */ ++ ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, ++ i2c->status, i2c->status & mask, ++ SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT); ++ if (ret) ++ return 0; ++ ++ spacemit_i2c_err_check(i2c); ++ } ++ ++ return 1; ++} ++ ++static int spacemit_i2c_wait_xfer_complete(struct spacemit_i2c_dev *i2c) ++{ ++ if (i2c->use_pio) ++ return spacemit_i2c_wait_pio_xfer(i2c); ++ ++ return wait_for_completion_timeout(&i2c->complete, ++ i2c->adapt.timeout); + } + + static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) +@@ -403,8 +573,8 @@ static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) + + spacemit_i2c_start(i2c); + +- time_left = wait_for_completion_timeout(&i2c->complete, +- i2c->adapt.timeout); ++ time_left = spacemit_i2c_wait_xfer_complete(i2c); ++ + if (!time_left) { + dev_err(i2c->dev, "msg completion timeout\n"); + spacemit_i2c_conditionally_reset_bus(i2c); +@@ -422,7 +592,7 @@ static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) + static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) + { + struct spacemit_i2c_dev *i2c = devid; +- u32 status, val; ++ u32 status; + + status = readl(i2c->base + SPACEMIT_ISR); + if (!status) +@@ -432,41 +602,8 @@ static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) + + spacemit_i2c_clear_int_status(i2c, status); + +- if (i2c->status & SPACEMIT_SR_ERR) +- goto err_out; +- +- val = readl(i2c->base + SPACEMIT_ICR); +- val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | SPACEMIT_CR_STOP | SPACEMIT_CR_START); ++ spacemit_i2c_handle_state(i2c); + +- switch (i2c->state) { +- case SPACEMIT_STATE_START: +- spacemit_i2c_handle_start(i2c); +- break; +- case SPACEMIT_STATE_READ: +- spacemit_i2c_handle_read(i2c); +- break; +- case SPACEMIT_STATE_WRITE: +- spacemit_i2c_handle_write(i2c); +- break; +- default: +- break; +- } +- +- if (i2c->state != SPACEMIT_STATE_IDLE) { +- val |= SPACEMIT_CR_TB | SPACEMIT_CR_ALDIE; +- +- if (spacemit_i2c_is_last_msg(i2c)) { +- /* trigger next byte with stop */ +- val |= SPACEMIT_CR_STOP; +- +- if (i2c->read) +- val |= SPACEMIT_CR_ACKNAK; +- } +- writel(val, i2c->base + SPACEMIT_ICR); +- } +- +-err_out: +- spacemit_i2c_err_check(i2c); + return IRQ_HANDLED; + } + +@@ -475,6 +612,11 @@ static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c) + unsigned long timeout; + int idx = 0, cnt = 0; + ++ if (i2c->use_pio) { ++ i2c->adapt.timeout = msecs_to_jiffies(SPACEMIT_WAIT_TIMEOUT); ++ return; ++ } ++ + for (; idx < i2c->msg_num; idx++) + cnt += (i2c->msgs + idx)->len + 1; + +@@ -487,11 +629,14 @@ static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c) + i2c->adapt.timeout = usecs_to_jiffies(timeout + USEC_PER_SEC / 10) / i2c->msg_num; + } + +-static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) ++static inline int ++spacemit_i2c_xfer_common(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num, bool use_pio) + { + struct spacemit_i2c_dev *i2c = i2c_get_adapdata(adapt); + int ret; + ++ i2c->use_pio = use_pio; ++ + i2c->msgs = msgs; + i2c->msg_num = num; + +@@ -519,6 +664,16 @@ static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, in + return ret < 0 ? ret : num; + } + ++static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) ++{ ++ return spacemit_i2c_xfer_common(adapt, msgs, num, false); ++} ++ ++static int spacemit_i2c_pio_xfer_atomic(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) ++{ ++ return spacemit_i2c_xfer_common(adapt, msgs, num, true); ++} ++ + static u32 spacemit_i2c_func(struct i2c_adapter *adap) + { + return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); +@@ -526,6 +681,7 @@ static u32 spacemit_i2c_func(struct i2c_adapter *adap) + + static const struct i2c_algorithm spacemit_i2c_algo = { + .xfer = spacemit_i2c_xfer, ++ .xfer_atomic = spacemit_i2c_pio_xfer_atomic, + .functionality = spacemit_i2c_func, + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0208-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch b/SPECS/linux-lts-kmhv2/0208-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch deleted file mode 100644 index 4ccee80d92..0000000000 --- a/SPECS/linux-lts-kmhv2/0208-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 9e80c22940c9b510b2ee11be7109bdff5e262886 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Tue, 10 Mar 2026 00:24:57 +0800 -Subject: [PATCH 208/467] UPSTREAM: riscv: dts: thead: th1520: add coefficients - to the PVT node - -The manual of TH1520 contains a set of coefficients a little different -to the driver default ones. - -Add them to the device tree node of PVT. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Reviewed-by: Drew Fustini -Signed-off-by: Drew Fustini -(cherry picked from commit a7aa874b69460896349985833059a764e688f1d0) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index aa6c9afa1a20..c65b71d9a1b8 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -782,6 +782,10 @@ pvt: pvt@fffff4e000 { - reg-names = "common", "ts", "pd", "vm"; - clocks = <&aonsys_clk>; - #thermal-sensor-cells = <1>; -+ moortec,ts-coeff-g = <42740>; -+ moortec,ts-coeff-h = <220500>; -+ moortec,ts-coeff-j = <(-160)>; -+ moortec,ts-coeff-cal5 = <4094>; - }; - - gpio@fffff52000 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch b/SPECS/linux-lts-kmhv2/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch new file mode 100644 index 0000000000..d01da0caa4 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch @@ -0,0 +1,86 @@ +From 55a3d0c1bf77d828f3581b3c07e12d8a25775e1c Mon Sep 17 00:00:00 2001 +From: Junhui Liu +Date: Thu, 12 Mar 2026 16:42:42 +0800 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: return -ENOTSUPP for + unsupported pin configurations + +Return -ENOTSUPP instead of -EINVAL when encountering unsupported pin +configuration parameters. This is more logical and allows the GPIO +subsystem to gracefully handle unsupported parameters via functions like +gpio_set_config_with_argument_optional(), which specifically ignores +-ENOTSUPP but treats others as failure. + +Signed-off-by: Junhui Liu +Reviewed-by: Anand Moon +Reviewed-by: Bartosz Golaszewski +Reviewed-by: Yixun Lan +Signed-off-by: Linus Walleij +(cherry picked from commit c3b0c06b73974d75c640a4ebc8678f8538654e5a) +Signed-off-by: Han Gao +--- + drivers/pinctrl/spacemit/pinctrl-k1.c | 21 ++++++++++++--------- + 1 file changed, 12 insertions(+), 9 deletions(-) + +diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c +index 71390402aaa6..f3c754f78074 100644 +--- a/drivers/pinctrl/spacemit/pinctrl-k1.c ++++ b/drivers/pinctrl/spacemit/pinctrl-k1.c +@@ -674,7 +674,7 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, + arg = 0; + break; + default: +- return -EINVAL; ++ return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); +@@ -740,7 +740,7 @@ static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, + } + break; + default: +- return -EINVAL; ++ return -ENOTSUPP; + } + } + +@@ -814,10 +814,12 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + u32 value; ++ int ret; + +- if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, +- configs, num_configs, &value)) +- return -EINVAL; ++ ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, ++ configs, num_configs, &value); ++ if (ret) ++ return ret; + + return spacemit_pin_set_config(pctrl, pin, value); + } +@@ -831,16 +833,17 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, + const struct spacemit_pin *spin; + const struct group_desc *group; + u32 value; +- int i; ++ int i, ret; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + spin = spacemit_get_pin(pctrl, group->grp.pins[0]); +- if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, +- configs, num_configs, &value)) +- return -EINVAL; ++ ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, ++ configs, num_configs, &value); ++ if (ret) ++ return ret; + + for (i = 0; i < group->grp.npins; i++) + spacemit_pin_set_config(pctrl, group->grp.pins[i], value); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0209-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch b/SPECS/linux-lts-kmhv2/0209-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch deleted file mode 100644 index 58b7193f04..0000000000 --- a/SPECS/linux-lts-kmhv2/0209-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 2c28be0f3ea2c24030f397d840f378703b680aed Mon Sep 17 00:00:00 2001 -From: Robert Mazur -Date: Wed, 25 Mar 2026 09:18:59 +0100 -Subject: [PATCH 209/467] UPSTREAM: riscv: dts: thead: beaglev-ahead: enable - HDMI output - -The BeagleV Ahead board includes a micro HDMI connector (Type-D) -wired to the TH1520 SoC's HDMI transmitter. - -Enable the display pipeline by adding the HDMI connector node, -connecting it to the HDMI controller, and activating the DPU -and HDMI nodes. - -Signed-off-by: Robert Mazur -Signed-off-by: Drew Fustini -(cherry picked from commit 74ec3d52c0035b662ec295bef2bbffad68446391) -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-beaglev-ahead.dts | 25 +++++++++++++++++++ - 1 file changed, 25 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -index 21c33f165ba9..91f3f9b987bc 100644 ---- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -@@ -75,6 +75,17 @@ led-5 { - label = "led5"; - }; - }; -+ -+ hdmi-connector { -+ compatible = "hdmi-connector"; -+ type = "d"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; - }; - - &osc { -@@ -236,6 +247,20 @@ &sdio0 { - status = "okay"; - }; - -+&dpu { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out_port { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch b/SPECS/linux-lts-kmhv2/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch new file mode 100644 index 0000000000..5b07efea54 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch @@ -0,0 +1,37 @@ +From 698e2cf6a0e40c6a445aeefa403bb4ac1b28919a Mon Sep 17 00:00:00 2001 +From: Junhui Liu +Date: Thu, 12 Mar 2026 16:42:43 +0800 +Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit-k1: Add set_config callback + support + +Assign gpiochip_generic_config() to the set_config() callback to support +pin configuration through the GPIO subsystem. This allows users to +configure GPIO pin attributes like pull-up/down when specifying a GPIO +line in the Device Tree. + +Signed-off-by: Junhui Liu +Reviewed-by: Anand Moon +Acked-by: Bartosz Golaszewski +Reviewed-by: Yixun Lan +Signed-off-by: Linus Walleij +(cherry picked from commit 47a9050e678c7929ada33c3f1f28ac4403423181) +Signed-off-by: Han Gao +--- + drivers/gpio/gpio-spacemit-k1.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c +index dbd2e81094b9..5fe813b7f9bb 100644 +--- a/drivers/gpio/gpio-spacemit-k1.c ++++ b/drivers/gpio/gpio-spacemit-k1.c +@@ -228,6 +228,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + gc->label = dev_name(dev); + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; ++ gc->set_config = gpiochip_generic_config; + gc->ngpio = SPACEMIT_NR_GPIOS_PER_BANK; + gc->base = -1; + gc->of_gpio_n_cells = 3; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0210-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch b/SPECS/linux-lts-kmhv2/0210-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch deleted file mode 100644 index b96de6f772..0000000000 --- a/SPECS/linux-lts-kmhv2/0210-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 3ceed31e1551882d64e7fd0770c15f8c1a4c15e9 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Sat, 7 Feb 2026 23:08:21 +0800 -Subject: [PATCH 210/467] UPSTREAM: i2c: spacemit: move i2c_xfer_msg() - -The upcoming PIO support requires a wait_pio_xfer() helper, which is -invoked from xfer_msg(). - -Since wait_pio_xfer() depends on err_check(), move the definition of -xfer_msg() after err_check() to avoid a forward declaration of -err_check(). - -Reviewed-by: Aurelien Jarno -Reviewed-by: Alex Elder -Signed-off-by: Troy Mitchell -Tested-by: Aurelien Jarno -Signed-off-by: Andi Shyti -Link: https://lore.kernel.org/r/20260207-b4-k3-i2c-pio-v7-1-626942d94d91@linux.spacemit.com -(cherry picked from commit 5b74da8e6cf7e2b5aed0836c733238c0fd7235af) -Signed-off-by: Han Gao ---- - drivers/i2c/busses/i2c-k1.c | 62 ++++++++++++++++++------------------- - 1 file changed, 31 insertions(+), 31 deletions(-) - -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index d0948a16de3e..6787a51e7391 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -305,37 +305,6 @@ static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) - writel(val, i2c->base + SPACEMIT_ICR); - } - --static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) --{ -- unsigned long time_left; -- struct i2c_msg *msg; -- -- for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { -- msg = &i2c->msgs[i2c->msg_idx]; -- i2c->msg_buf = msg->buf; -- i2c->unprocessed = msg->len; -- i2c->status = 0; -- -- reinit_completion(&i2c->complete); -- -- spacemit_i2c_start(i2c); -- -- time_left = wait_for_completion_timeout(&i2c->complete, -- i2c->adapt.timeout); -- if (!time_left) { -- dev_err(i2c->dev, "msg completion timeout\n"); -- spacemit_i2c_conditionally_reset_bus(i2c); -- spacemit_i2c_reset(i2c); -- return -ETIMEDOUT; -- } -- -- if (i2c->status & SPACEMIT_SR_ERR) -- return spacemit_i2c_handle_err(i2c); -- } -- -- return 0; --} -- - static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c) - { - if (i2c->msg_idx != i2c->msg_num - 1) -@@ -419,6 +388,37 @@ static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c) - complete(&i2c->complete); - } - -+static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) -+{ -+ unsigned long time_left; -+ struct i2c_msg *msg; -+ -+ for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { -+ msg = &i2c->msgs[i2c->msg_idx]; -+ i2c->msg_buf = msg->buf; -+ i2c->unprocessed = msg->len; -+ i2c->status = 0; -+ -+ reinit_completion(&i2c->complete); -+ -+ spacemit_i2c_start(i2c); -+ -+ time_left = wait_for_completion_timeout(&i2c->complete, -+ i2c->adapt.timeout); -+ if (!time_left) { -+ dev_err(i2c->dev, "msg completion timeout\n"); -+ spacemit_i2c_conditionally_reset_bus(i2c); -+ spacemit_i2c_reset(i2c); -+ return -ETIMEDOUT; -+ } -+ -+ if (i2c->status & SPACEMIT_SR_ERR) -+ return spacemit_i2c_handle_err(i2c); -+ } -+ -+ return 0; -+} -+ - static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) - { - struct spacemit_i2c_dev *i2c = devid; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0211-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch b/SPECS/linux-lts-kmhv2/0211-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch deleted file mode 100644 index 46854f2eb4..0000000000 --- a/SPECS/linux-lts-kmhv2/0211-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch +++ /dev/null @@ -1,487 +0,0 @@ -From 4c5b92d265c0ff7e581b5979bc668b3a0358edba Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Sat, 7 Feb 2026 23:08:22 +0800 -Subject: [PATCH 211/467] UPSTREAM: i2c: spacemit: introduce pio for k1 - -This patch introduces I2C PIO functionality for the Spacemit K1 SoC, -enabling the use of I2C in atomic context. - -When i2c xfer_atomic is invoked, use_pio is set accordingly. - -Since an atomic context is required, all interrupts are disabled when -operating in PIO mode. Even with interrupts disabled, the bits in the -ISR (Interrupt Status Register) will still be set, so error handling can -be performed by polling the relevant status bits in the ISR. - -Signed-off-by: Troy Mitchell -Tested-by: Aurelien Jarno -Reviewed-by: Aurelien Jarno -Signed-off-by: Andi Shyti -Link: https://lore.kernel.org/r/20260207-b4-k3-i2c-pio-v7-2-626942d94d91@linux.spacemit.com -(cherry picked from commit 5dd75dac1b35e5b24f5051d01fc85105adcc2e15) -Signed-off-by: Han Gao ---- - drivers/i2c/busses/i2c-k1.c | 300 +++++++++++++++++++++++++++--------- - 1 file changed, 228 insertions(+), 72 deletions(-) - -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index 6787a51e7391..afc6bdd68bd4 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -98,6 +98,10 @@ - - #define SPACEMIT_BUS_RESET_CLK_CNT_MAX 9 - -+#define SPACEMIT_WAIT_TIMEOUT 1000 /* ms */ -+#define SPACEMIT_POLL_TIMEOUT 1000 /* us */ -+#define SPACEMIT_POLL_INTERVAL 30 /* us */ -+ - enum spacemit_i2c_state { - SPACEMIT_STATE_IDLE, - SPACEMIT_STATE_START, -@@ -126,6 +130,7 @@ struct spacemit_i2c_dev { - - enum spacemit_i2c_state state; - bool read; -+ bool use_pio; - struct completion complete; - u32 status; - }; -@@ -172,6 +177,14 @@ static int spacemit_i2c_handle_err(struct spacemit_i2c_dev *i2c) - return i2c->status & SPACEMIT_SR_ACKNAK ? -ENXIO : -EIO; - } - -+static inline void spacemit_i2c_delay(struct spacemit_i2c_dev *i2c, unsigned int us) -+{ -+ if (i2c->use_pio) -+ udelay(us); -+ else -+ fsleep(us); -+} -+ - static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c) - { - u32 status; -@@ -183,7 +196,8 @@ static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c) - return; - - spacemit_i2c_reset(i2c); -- usleep_range(10, 20); -+ -+ spacemit_i2c_delay(i2c, 10); - - for (clk_cnt = 0; clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX; clk_cnt++) { - status = readl(i2c->base + SPACEMIT_IBMR); -@@ -212,9 +226,15 @@ static int spacemit_i2c_wait_bus_idle(struct spacemit_i2c_dev *i2c) - if (!(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB))) - return 0; - -- ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, -- val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), -- 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); -+ if (i2c->use_pio) -+ ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, -+ val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), -+ 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); -+ else -+ ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, -+ val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), -+ 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); -+ - if (ret) - spacemit_i2c_reset(i2c); - -@@ -226,7 +246,7 @@ static void spacemit_i2c_check_bus_release(struct spacemit_i2c_dev *i2c) - /* in case bus is not released after transfer completes */ - if (readl(i2c->base + SPACEMIT_ISR) & SPACEMIT_SR_EBB) { - spacemit_i2c_conditionally_reset_bus(i2c); -- usleep_range(90, 150); -+ spacemit_i2c_delay(i2c, 90); - } - } - -@@ -238,25 +258,33 @@ spacemit_i2c_clear_int_status(struct spacemit_i2c_dev *i2c, u32 mask) - - static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) - { -- u32 val; -- -- /* -- * Unmask interrupt bits for all xfer mode: -- * bus error, arbitration loss detected. -- * For transaction complete signal, we use master stop -- * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. -- */ -- val = SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; -- -- /* -- * Unmask interrupt bits for interrupt xfer mode: -- * When IDBR receives a byte, an interrupt is triggered. -- * -- * For the tx empty interrupt, it will be enabled in the -- * i2c_start function. -- * Otherwise, it will cause an erroneous empty interrupt before i2c_start. -- */ -- val |= SPACEMIT_CR_DRFIE; -+ u32 val = 0; -+ -+ if (!i2c->use_pio) { -+ /* -+ * Enable interrupt bits for all xfer mode: -+ * bus error, arbitration loss detected. -+ */ -+ val |= SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; -+ -+ /* -+ * Unmask interrupt bits for interrupt xfer mode: -+ * When IDBR receives a byte, an interrupt is triggered. -+ * -+ * For the tx empty interrupt, it will be enabled in the -+ * i2c_start(). -+ * We don't want a TX empty interrupt until we start -+ * a transfer in i2c_start(). -+ */ -+ val |= SPACEMIT_CR_DRFIE; -+ -+ /* -+ * Enable master stop interrupt bit. -+ * For transaction complete signal, we use master stop -+ * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. -+ */ -+ val |= SPACEMIT_CR_MSDIE; -+ } - - if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) - val |= SPACEMIT_CR_MODE_FAST; -@@ -268,7 +296,7 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) - val |= SPACEMIT_CR_SCLE; - - /* enable master stop detected */ -- val |= SPACEMIT_CR_MSDE | SPACEMIT_CR_MSDIE; -+ val |= SPACEMIT_CR_MSDE; - - writel(val, i2c->base + SPACEMIT_ICR); - -@@ -301,7 +329,12 @@ static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) - /* send start pulse */ - val = readl(i2c->base + SPACEMIT_ICR); - val &= ~SPACEMIT_CR_STOP; -- val |= SPACEMIT_CR_START | SPACEMIT_CR_TB | SPACEMIT_CR_DTEIE; -+ val |= SPACEMIT_CR_START | SPACEMIT_CR_TB; -+ -+ /* Enable the TX empty interrupt */ -+ if (!i2c->use_pio) -+ val |= SPACEMIT_CR_DTEIE; -+ - writel(val, i2c->base + SPACEMIT_ICR); - } - -@@ -316,8 +349,23 @@ static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c) - return !i2c->unprocessed; - } - -+static inline void spacemit_i2c_complete(struct spacemit_i2c_dev *i2c) -+{ -+ /* SPACEMIT_STATE_IDLE avoids triggering the next byte */ -+ i2c->state = SPACEMIT_STATE_IDLE; -+ -+ if (i2c->use_pio) -+ return; -+ -+ complete(&i2c->complete); -+} -+ - static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c) - { -+ /* If there's no space in the IDBR, we're done */ -+ if (!(i2c->status & SPACEMIT_SR_ITE)) -+ return; -+ - /* if transfer completes, SPACEMIT_ISR will handle it */ - if (i2c->status & SPACEMIT_SR_MSD) - return; -@@ -328,16 +376,19 @@ static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c) - return; - } - -- /* SPACEMIT_STATE_IDLE avoids trigger next byte */ -- i2c->state = SPACEMIT_STATE_IDLE; -- complete(&i2c->complete); -+ spacemit_i2c_complete(i2c); - } - - static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c) - { -+ /* If there's nothing in the IDBR, we're done */ -+ if (!(i2c->status & SPACEMIT_SR_IRF)) -+ return; -+ - if (i2c->unprocessed) { - *i2c->msg_buf++ = readl(i2c->base + SPACEMIT_IDBR); - i2c->unprocessed--; -+ return; - } - - /* if transfer completes, SPACEMIT_ISR will handle it */ -@@ -348,9 +399,7 @@ static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c) - if (i2c->unprocessed) - return; - -- /* SPACEMIT_STATE_IDLE avoids trigger next byte */ -- i2c->state = SPACEMIT_STATE_IDLE; -- complete(&i2c->complete); -+ spacemit_i2c_complete(i2c); - } - - static void spacemit_i2c_handle_start(struct spacemit_i2c_dev *i2c) -@@ -384,8 +433,129 @@ static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c) - - spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); - -- i2c->state = SPACEMIT_STATE_IDLE; -- complete(&i2c->complete); -+ spacemit_i2c_complete(i2c); -+} -+ -+static void spacemit_i2c_handle_state(struct spacemit_i2c_dev *i2c) -+{ -+ u32 val; -+ -+ if (i2c->status & SPACEMIT_SR_ERR) -+ goto err_out; -+ -+ switch (i2c->state) { -+ case SPACEMIT_STATE_START: -+ spacemit_i2c_handle_start(i2c); -+ break; -+ case SPACEMIT_STATE_READ: -+ spacemit_i2c_handle_read(i2c); -+ break; -+ case SPACEMIT_STATE_WRITE: -+ spacemit_i2c_handle_write(i2c); -+ break; -+ default: -+ break; -+ } -+ -+ if (i2c->state != SPACEMIT_STATE_IDLE) { -+ val = readl(i2c->base + SPACEMIT_ICR); -+ val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | -+ SPACEMIT_CR_STOP | SPACEMIT_CR_START); -+ val |= SPACEMIT_CR_TB; -+ if (!i2c->use_pio) -+ val |= SPACEMIT_CR_ALDIE; -+ -+ if (spacemit_i2c_is_last_msg(i2c)) { -+ /* trigger next byte with stop */ -+ val |= SPACEMIT_CR_STOP; -+ -+ if (i2c->read) -+ val |= SPACEMIT_CR_ACKNAK; -+ } -+ writel(val, i2c->base + SPACEMIT_ICR); -+ } -+ -+err_out: -+ spacemit_i2c_err_check(i2c); -+} -+ -+/* -+ * In PIO mode, this function is used as a replacement for -+ * wait_for_completion_timeout(), whose return value indicates -+ * the remaining time. -+ * -+ * We do not have a meaningful remaining-time value here, so -+ * return a non-zero value on success to indicate "not timed out". -+ * Returning 1 ensures callers treating the return value as -+ * time_left will not incorrectly report a timeout. -+ */ -+static int spacemit_i2c_wait_pio_xfer(struct spacemit_i2c_dev *i2c) -+{ -+ u32 mask, msec = jiffies_to_msecs(i2c->adapt.timeout); -+ ktime_t timeout = ktime_add_ms(ktime_get(), msec); -+ int ret; -+ -+ mask = SPACEMIT_SR_IRF | SPACEMIT_SR_ITE; -+ -+ do { -+ i2c->status = readl(i2c->base + SPACEMIT_ISR); -+ -+ spacemit_i2c_clear_int_status(i2c, i2c->status); -+ -+ if (i2c->status & mask) -+ spacemit_i2c_handle_state(i2c); -+ else -+ udelay(SPACEMIT_POLL_INTERVAL); -+ } while (i2c->unprocessed && ktime_compare(ktime_get(), timeout) < 0); -+ -+ if (i2c->unprocessed) -+ return 0; -+ -+ if (i2c->read) -+ return 1; -+ -+ /* -+ * If this is the last byte to write of the current message, -+ * we have to wait here. Otherwise, control will proceed directly -+ * to start(), which would overwrite the current data. -+ */ -+ ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, -+ i2c->status, i2c->status & SPACEMIT_SR_ITE, -+ SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT); -+ if (ret) -+ return 0; -+ -+ /* -+ * For writes: in interrupt mode, an ITE (write-empty) interrupt is triggered -+ * after the last byte, and the MSD-related handling takes place there. -+ * In PIO mode, however, we need to explicitly call err_check() to emulate this -+ * step, otherwise the next transfer will fail. -+ */ -+ if (i2c->msg_idx == i2c->msg_num - 1) { -+ mask = SPACEMIT_SR_MSD | SPACEMIT_SR_ERR; -+ /* -+ * In some cases, MSD may not arrive immediately; -+ * wait here to handle that. -+ */ -+ ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, -+ i2c->status, i2c->status & mask, -+ SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT); -+ if (ret) -+ return 0; -+ -+ spacemit_i2c_err_check(i2c); -+ } -+ -+ return 1; -+} -+ -+static int spacemit_i2c_wait_xfer_complete(struct spacemit_i2c_dev *i2c) -+{ -+ if (i2c->use_pio) -+ return spacemit_i2c_wait_pio_xfer(i2c); -+ -+ return wait_for_completion_timeout(&i2c->complete, -+ i2c->adapt.timeout); - } - - static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) -@@ -403,8 +573,8 @@ static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) - - spacemit_i2c_start(i2c); - -- time_left = wait_for_completion_timeout(&i2c->complete, -- i2c->adapt.timeout); -+ time_left = spacemit_i2c_wait_xfer_complete(i2c); -+ - if (!time_left) { - dev_err(i2c->dev, "msg completion timeout\n"); - spacemit_i2c_conditionally_reset_bus(i2c); -@@ -422,7 +592,7 @@ static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) - static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) - { - struct spacemit_i2c_dev *i2c = devid; -- u32 status, val; -+ u32 status; - - status = readl(i2c->base + SPACEMIT_ISR); - if (!status) -@@ -432,41 +602,8 @@ static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) - - spacemit_i2c_clear_int_status(i2c, status); - -- if (i2c->status & SPACEMIT_SR_ERR) -- goto err_out; -- -- val = readl(i2c->base + SPACEMIT_ICR); -- val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | SPACEMIT_CR_STOP | SPACEMIT_CR_START); -+ spacemit_i2c_handle_state(i2c); - -- switch (i2c->state) { -- case SPACEMIT_STATE_START: -- spacemit_i2c_handle_start(i2c); -- break; -- case SPACEMIT_STATE_READ: -- spacemit_i2c_handle_read(i2c); -- break; -- case SPACEMIT_STATE_WRITE: -- spacemit_i2c_handle_write(i2c); -- break; -- default: -- break; -- } -- -- if (i2c->state != SPACEMIT_STATE_IDLE) { -- val |= SPACEMIT_CR_TB | SPACEMIT_CR_ALDIE; -- -- if (spacemit_i2c_is_last_msg(i2c)) { -- /* trigger next byte with stop */ -- val |= SPACEMIT_CR_STOP; -- -- if (i2c->read) -- val |= SPACEMIT_CR_ACKNAK; -- } -- writel(val, i2c->base + SPACEMIT_ICR); -- } -- --err_out: -- spacemit_i2c_err_check(i2c); - return IRQ_HANDLED; - } - -@@ -475,6 +612,11 @@ static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c) - unsigned long timeout; - int idx = 0, cnt = 0; - -+ if (i2c->use_pio) { -+ i2c->adapt.timeout = msecs_to_jiffies(SPACEMIT_WAIT_TIMEOUT); -+ return; -+ } -+ - for (; idx < i2c->msg_num; idx++) - cnt += (i2c->msgs + idx)->len + 1; - -@@ -487,11 +629,14 @@ static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c) - i2c->adapt.timeout = usecs_to_jiffies(timeout + USEC_PER_SEC / 10) / i2c->msg_num; - } - --static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) -+static inline int -+spacemit_i2c_xfer_common(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num, bool use_pio) - { - struct spacemit_i2c_dev *i2c = i2c_get_adapdata(adapt); - int ret; - -+ i2c->use_pio = use_pio; -+ - i2c->msgs = msgs; - i2c->msg_num = num; - -@@ -519,6 +664,16 @@ static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, in - return ret < 0 ? ret : num; - } - -+static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) -+{ -+ return spacemit_i2c_xfer_common(adapt, msgs, num, false); -+} -+ -+static int spacemit_i2c_pio_xfer_atomic(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) -+{ -+ return spacemit_i2c_xfer_common(adapt, msgs, num, true); -+} -+ - static u32 spacemit_i2c_func(struct i2c_adapter *adap) - { - return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); -@@ -526,6 +681,7 @@ static u32 spacemit_i2c_func(struct i2c_adapter *adap) - - static const struct i2c_algorithm spacemit_i2c_algo = { - .xfer = spacemit_i2c_xfer, -+ .xfer_atomic = spacemit_i2c_pio_xfer_atomic, - .functionality = spacemit_i2c_func, - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch b/SPECS/linux-lts-kmhv2/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch new file mode 100644 index 0000000000..e3ff5c7bb8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch @@ -0,0 +1,45 @@ +From 8572451bc96b2e6e3f43ce554e3806a5b1c7778c Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 26 Feb 2026 08:17:55 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: pcie: fix missing power + regulator + +The PCIe port require 3.3v power regulator for device to work properly, So +explicitly add it to fix the DT warning: + +arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dtb: pcie@ca400000 (spacemit,k1-pcie): pcie@0: 'vpcie3v3-supply' is a required property + from schema $id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml + +Fixes: 0be016a4b5d1 ("riscv: dts: spacemit: PCIe and PHY-related updates") +Reported-by: Conor Dooley +Link: https://lore.kernel.org/r/20260226-k1-pcie-fix-pwr-v1-1-94b493cd27e5@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 8a9071299dec817a544c0fb48f7302396fafdc4b) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 5971605754b3..51f6c6a774b0 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -305,6 +305,7 @@ &pcie1_phy { + + &pcie1_port { + phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc_3v3>; + }; + + &pcie1 { +@@ -320,6 +321,7 @@ &pcie2_phy { + + &pcie2_port { + phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&pcie_vcc_3v3>; + }; + + &pcie2 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0212-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch b/SPECS/linux-lts-kmhv2/0212-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch deleted file mode 100644 index 829d6bbcd0..0000000000 --- a/SPECS/linux-lts-kmhv2/0212-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch +++ /dev/null @@ -1,86 +0,0 @@ -From b353a7aa6259753c7025aedf18b101189b01e902 Mon Sep 17 00:00:00 2001 -From: Junhui Liu -Date: Thu, 12 Mar 2026 16:42:42 +0800 -Subject: [PATCH 212/467] UPSTREAM: pinctrl: spacemit: return -ENOTSUPP for - unsupported pin configurations - -Return -ENOTSUPP instead of -EINVAL when encountering unsupported pin -configuration parameters. This is more logical and allows the GPIO -subsystem to gracefully handle unsupported parameters via functions like -gpio_set_config_with_argument_optional(), which specifically ignores --ENOTSUPP but treats others as failure. - -Signed-off-by: Junhui Liu -Reviewed-by: Anand Moon -Reviewed-by: Bartosz Golaszewski -Reviewed-by: Yixun Lan -Signed-off-by: Linus Walleij -(cherry picked from commit c3b0c06b73974d75c640a4ebc8678f8538654e5a) -Signed-off-by: Han Gao ---- - drivers/pinctrl/spacemit/pinctrl-k1.c | 21 ++++++++++++--------- - 1 file changed, 12 insertions(+), 9 deletions(-) - -diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c -index 71390402aaa6..f3c754f78074 100644 ---- a/drivers/pinctrl/spacemit/pinctrl-k1.c -+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c -@@ -674,7 +674,7 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, - arg = 0; - break; - default: -- return -EINVAL; -+ return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); -@@ -740,7 +740,7 @@ static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, - } - break; - default: -- return -EINVAL; -+ return -ENOTSUPP; - } - } - -@@ -814,10 +814,12 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, - struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); - u32 value; -+ int ret; - -- if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, -- configs, num_configs, &value)) -- return -EINVAL; -+ ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, -+ configs, num_configs, &value); -+ if (ret) -+ return ret; - - return spacemit_pin_set_config(pctrl, pin, value); - } -@@ -831,16 +833,17 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, - const struct spacemit_pin *spin; - const struct group_desc *group; - u32 value; -- int i; -+ int i, ret; - - group = pinctrl_generic_get_group(pctldev, gsel); - if (!group) - return -EINVAL; - - spin = spacemit_get_pin(pctrl, group->grp.pins[0]); -- if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, -- configs, num_configs, &value)) -- return -EINVAL; -+ ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, -+ configs, num_configs, &value); -+ if (ret) -+ return ret; - - for (i = 0; i < group->grp.npins; i++) - spacemit_pin_set_config(pctrl, group->grp.pins[i], value); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch b/SPECS/linux-lts-kmhv2/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch new file mode 100644 index 0000000000..c1a03ad44a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch @@ -0,0 +1,83 @@ +From d591170d2ed25e8716eb3db09e686e859c5c318b Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Fri, 6 Feb 2026 10:32:04 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Update PMIC supply + properties for BPI-F3 and Jupiter + +Use per-regulator supply names in pmic "spacemit,p1" node to specify +each board's power tree topology and match the updated dt-binding. + +Signed-off-by: Guodong Xu +Reviewed-by: Alex Elder +Link: https://lore.kernel.org/r/20260206-spacemit-p1-v4-3-8f695d93811e@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 108c77b34b929e6bdb7ac9613ed65c90da8bcb9f) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++-- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 12 ++++++++++-- + 2 files changed, 20 insertions(+), 4 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 51f6c6a774b0..ed88507b84e9 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -190,7 +190,15 @@ pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; +- vin-supply = <®_vcc_4v>; ++ vin1-supply = <®_vcc_4v>; ++ vin2-supply = <®_vcc_4v>; ++ vin3-supply = <®_vcc_4v>; ++ vin4-supply = <®_vcc_4v>; ++ vin5-supply = <®_vcc_4v>; ++ vin6-supply = <®_vcc_4v>; ++ aldoin-supply = <®_vcc_4v>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; + + regulators { + buck1 { +@@ -221,7 +229,7 @@ buck4 { + regulator-always-on; + }; + +- buck5 { ++ buck5: buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 800a112d5d70..e2702a781734 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -100,7 +100,15 @@ pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; +- vin-supply = <®_vcc_4v>; ++ vin1-supply = <®_vcc_4v>; ++ vin2-supply = <®_vcc_4v>; ++ vin3-supply = <®_vcc_4v>; ++ vin4-supply = <®_vcc_4v>; ++ vin5-supply = <®_vcc_4v>; ++ vin6-supply = <®_vcc_4v>; ++ aldoin-supply = <®_vcc_4v>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; + + regulators { + buck1 { +@@ -131,7 +139,7 @@ buck4 { + regulator-always-on; + }; + +- buck5 { ++ buck5: buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0213-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch b/SPECS/linux-lts-kmhv2/0213-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch deleted file mode 100644 index 94351bf0cb..0000000000 --- a/SPECS/linux-lts-kmhv2/0213-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch +++ /dev/null @@ -1,37 +0,0 @@ -From d5b0b0437eee5d56c49e36bb6f428b5171ddb716 Mon Sep 17 00:00:00 2001 -From: Junhui Liu -Date: Thu, 12 Mar 2026 16:42:43 +0800 -Subject: [PATCH 213/467] UPSTREAM: gpio: spacemit-k1: Add set_config callback - support - -Assign gpiochip_generic_config() to the set_config() callback to support -pin configuration through the GPIO subsystem. This allows users to -configure GPIO pin attributes like pull-up/down when specifying a GPIO -line in the Device Tree. - -Signed-off-by: Junhui Liu -Reviewed-by: Anand Moon -Acked-by: Bartosz Golaszewski -Reviewed-by: Yixun Lan -Signed-off-by: Linus Walleij -(cherry picked from commit 47a9050e678c7929ada33c3f1f28ac4403423181) -Signed-off-by: Han Gao ---- - drivers/gpio/gpio-spacemit-k1.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c -index dbd2e81094b9..5fe813b7f9bb 100644 ---- a/drivers/gpio/gpio-spacemit-k1.c -+++ b/drivers/gpio/gpio-spacemit-k1.c -@@ -228,6 +228,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - gc->label = dev_name(dev); - gc->request = gpiochip_generic_request; - gc->free = gpiochip_generic_free; -+ gc->set_config = gpiochip_generic_config; - gc->ngpio = SPACEMIT_NR_GPIOS_PER_BANK; - gc->base = -1; - gc->of_gpio_n_cells = 3; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch b/SPECS/linux-lts-kmhv2/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch new file mode 100644 index 0000000000..2dce8101f3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch @@ -0,0 +1,96 @@ +From d068a8147daedba4965fc79a896ad7dcaa91b9e4 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 26 Feb 2026 09:35:00 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: adapt regulator node + name to preferred form + +The preferred node name for fixed-regulators has changed to pattern [1]: + '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$' + +Adjust all SpacemiT DT regulator node names to fix this. + +Reviewed-by: Javier Martinez Canillas +Link: https://lore.kernel.org/r/20240426215147.3138211-1-robh@kernel.org [1] +Link: https://lore.kernel.org/r/20260226-02-k1-regulator-names-v1-1-e87695d50159@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit ec1fb4e55df47ed043ab2ccc6787e39b9d67e49b) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 10 +++++----- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++-- + 2 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index ed88507b84e9..404b69c47b91 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -33,7 +33,7 @@ led1 { + }; + }; + +- pcie_vcc_3v3: pcie-vcc3v3 { ++ pcie_vcc_3v3: regulator-pcie-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "PCIE_VCC3V3"; + regulator-min-microvolt = <3300000>; +@@ -41,7 +41,7 @@ pcie_vcc_3v3: pcie-vcc3v3 { + regulator-always-on; + }; + +- reg_dc_in: dc-in-12v { ++ reg_dc_in: regulator-dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; + regulator-min-microvolt = <12000000>; +@@ -50,7 +50,7 @@ reg_dc_in: dc-in-12v { + regulator-always-on; + }; + +- reg_vcc_4v: vcc-4v { ++ reg_vcc_4v: regulator-vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "vcc_4v"; + regulator-min-microvolt = <4000000>; +@@ -60,7 +60,7 @@ reg_vcc_4v: vcc-4v { + vin-supply = <®_dc_in>; + }; + +- usb3-vbus-5v { ++ regulator-usb3-vbus-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_VBUS"; + regulator-min-microvolt = <5000000>; +@@ -70,7 +70,7 @@ usb3-vbus-5v { + enable-active-high; + }; + +- usb3_hub_5v: usb3-hub-5v { ++ usb3_hub_5v: regulator-usb3-hub-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_HUB"; + regulator-min-microvolt = <5000000>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index e2702a781734..9959c8023ece 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -21,7 +21,7 @@ chosen { + stdout-path = "serial0"; + }; + +- reg_dc_in: dc-in-12v { ++ reg_dc_in: regulator-dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; + regulator-min-microvolt = <12000000>; +@@ -30,7 +30,7 @@ reg_dc_in: dc-in-12v { + regulator-always-on; + }; + +- reg_vcc_4v: vcc-4v { ++ reg_vcc_4v: regulator-vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "vcc_4v"; + regulator-min-microvolt = <4000000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch b/SPECS/linux-lts-kmhv2/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch new file mode 100644 index 0000000000..dd31af6364 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch @@ -0,0 +1,62 @@ +From 3c942f15e5112f8554b39f1c889cb52184bd3e90 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Mon, 9 Mar 2026 11:00:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add 'linux,pci-domain' + to PCIe nodes for K1 + +The SpacemiT K1 SoC has 3 PCIe EP controller nodes. Add the +'linux,pci-domain' property to assign a PCI domain number to +each of the controllers instead of assigning it randomly. + +This creates a stable sysfs path, allowing userspace scripts +to reliably target specific PCIe devices (such as PCIe NICs). + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260309030000.1157040-1-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit 86314111f654310a69c9775e35e263c036031675) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 529ec68e9c23..d2015201f8e5 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -1033,6 +1033,7 @@ pcie-bus { + #size-cells = <2>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, + <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; ++ + pcie0: pcie@ca000000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; +@@ -1044,6 +1045,7 @@ pcie0: pcie@ca000000 { + "atu", + "config", + "link"; ++ linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, +@@ -1087,6 +1089,7 @@ pcie1: pcie@ca400000 { + "atu", + "config", + "link"; ++ linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, +@@ -1130,6 +1133,7 @@ pcie2: pcie@ca800000 { + "atu", + "config", + "link"; ++ linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0214-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch b/SPECS/linux-lts-kmhv2/0214-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch deleted file mode 100644 index af101ace4b..0000000000 --- a/SPECS/linux-lts-kmhv2/0214-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 0b209a13a933458317f10fc48bd50c2986ab96fc Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 26 Feb 2026 08:17:55 +0000 -Subject: [PATCH 214/467] UPSTREAM: riscv: dts: spacemit: pcie: fix missing - power regulator - -The PCIe port require 3.3v power regulator for device to work properly, So -explicitly add it to fix the DT warning: - -arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dtb: pcie@ca400000 (spacemit,k1-pcie): pcie@0: 'vpcie3v3-supply' is a required property - from schema $id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml - -Fixes: 0be016a4b5d1 ("riscv: dts: spacemit: PCIe and PHY-related updates") -Reported-by: Conor Dooley -Link: https://lore.kernel.org/r/20260226-k1-pcie-fix-pwr-v1-1-94b493cd27e5@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit 8a9071299dec817a544c0fb48f7302396fafdc4b) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 5971605754b3..51f6c6a774b0 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -305,6 +305,7 @@ &pcie1_phy { - - &pcie1_port { - phys = <&pcie1_phy>; -+ vpcie3v3-supply = <&pcie_vcc_3v3>; - }; - - &pcie1 { -@@ -320,6 +321,7 @@ &pcie2_phy { - - &pcie2_port { - phys = <&pcie2_phy>; -+ vpcie3v3-supply = <&pcie_vcc_3v3>; - }; - - &pcie2 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch b/SPECS/linux-lts-kmhv2/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch new file mode 100644 index 0000000000..1a6351971a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch @@ -0,0 +1,46 @@ +From e6fddcb8065f3568285549e732cda7618b1e5065 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 4 Mar 2026 07:19:39 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: serial: 8250: spacemit: fix clock + property for K3 SoC + +The UART of SpacemiT K3 SoC has same clock property as K1 generation which +request two clock sources, fix the binding otherwise will get DT check +warnings. + +Acked-by: Greg Kroah-Hartman +Acked-by: Rob Herring (Arm) +Link: https://lore.kernel.org/r/20260304-01-uart-clock-names-v1-1-338483f04a8b@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 606a6b8bca570aa4f838ddd410345a2937bd98eb) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/serial/8250.yaml | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml +index b243afa69a1a..0d4ae9a62f4c 100644 +--- a/Documentation/devicetree/bindings/serial/8250.yaml ++++ b/Documentation/devicetree/bindings/serial/8250.yaml +@@ -63,7 +63,9 @@ allOf: + properties: + compatible: + contains: +- const: spacemit,k1-uart ++ enum: ++ - spacemit,k1-uart ++ - spacemit,k3-uart + then: + properties: + clock-names: +@@ -76,6 +78,7 @@ allOf: + contains: + enum: + - spacemit,k1-uart ++ - spacemit,k3-uart + - nxp,lpc1850-uart + then: + required: +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0215-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch b/SPECS/linux-lts-kmhv2/0215-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch deleted file mode 100644 index 812b0f1ef8..0000000000 --- a/SPECS/linux-lts-kmhv2/0215-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 867d1c8308a1f4fcaa14a9efca280d8e5ca431a1 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Fri, 6 Feb 2026 10:32:04 +0800 -Subject: [PATCH 215/467] UPSTREAM: riscv: dts: spacemit: Update PMIC supply - properties for BPI-F3 and Jupiter - -Use per-regulator supply names in pmic "spacemit,p1" node to specify -each board's power tree topology and match the updated dt-binding. - -Signed-off-by: Guodong Xu -Reviewed-by: Alex Elder -Link: https://lore.kernel.org/r/20260206-spacemit-p1-v4-3-8f695d93811e@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 108c77b34b929e6bdb7ac9613ed65c90da8bcb9f) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++-- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 12 ++++++++++-- - 2 files changed, 20 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 51f6c6a774b0..ed88507b84e9 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -190,7 +190,15 @@ pmic@41 { - compatible = "spacemit,p1"; - reg = <0x41>; - interrupts = <64>; -- vin-supply = <®_vcc_4v>; -+ vin1-supply = <®_vcc_4v>; -+ vin2-supply = <®_vcc_4v>; -+ vin3-supply = <®_vcc_4v>; -+ vin4-supply = <®_vcc_4v>; -+ vin5-supply = <®_vcc_4v>; -+ vin6-supply = <®_vcc_4v>; -+ aldoin-supply = <®_vcc_4v>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; - - regulators { - buck1 { -@@ -221,7 +229,7 @@ buck4 { - regulator-always-on; - }; - -- buck5 { -+ buck5: buck5 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; - regulator-ramp-delay = <5000>; -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 800a112d5d70..e2702a781734 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -100,7 +100,15 @@ pmic@41 { - compatible = "spacemit,p1"; - reg = <0x41>; - interrupts = <64>; -- vin-supply = <®_vcc_4v>; -+ vin1-supply = <®_vcc_4v>; -+ vin2-supply = <®_vcc_4v>; -+ vin3-supply = <®_vcc_4v>; -+ vin4-supply = <®_vcc_4v>; -+ vin5-supply = <®_vcc_4v>; -+ vin6-supply = <®_vcc_4v>; -+ aldoin-supply = <®_vcc_4v>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; - - regulators { - buck1 { -@@ -131,7 +139,7 @@ buck4 { - regulator-always-on; - }; - -- buck5 { -+ buck5: buck5 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; - regulator-ramp-delay = <5000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0216-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch b/SPECS/linux-lts-kmhv2/0216-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch deleted file mode 100644 index 0baf5e0509..0000000000 --- a/SPECS/linux-lts-kmhv2/0216-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 8e847600364cd4fb332c1e6d69b370eab667157b Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 26 Feb 2026 09:35:00 +0000 -Subject: [PATCH 216/467] UPSTREAM: riscv: dts: spacemit: adapt regulator node - name to preferred form - -The preferred node name for fixed-regulators has changed to pattern [1]: - '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$' - -Adjust all SpacemiT DT regulator node names to fix this. - -Reviewed-by: Javier Martinez Canillas -Link: https://lore.kernel.org/r/20240426215147.3138211-1-robh@kernel.org [1] -Link: https://lore.kernel.org/r/20260226-02-k1-regulator-names-v1-1-e87695d50159@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit ec1fb4e55df47ed043ab2ccc6787e39b9d67e49b) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 10 +++++----- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++-- - 2 files changed, 7 insertions(+), 7 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index ed88507b84e9..404b69c47b91 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -33,7 +33,7 @@ led1 { - }; - }; - -- pcie_vcc_3v3: pcie-vcc3v3 { -+ pcie_vcc_3v3: regulator-pcie-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "PCIE_VCC3V3"; - regulator-min-microvolt = <3300000>; -@@ -41,7 +41,7 @@ pcie_vcc_3v3: pcie-vcc3v3 { - regulator-always-on; - }; - -- reg_dc_in: dc-in-12v { -+ reg_dc_in: regulator-dc-in-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_in_12v"; - regulator-min-microvolt = <12000000>; -@@ -50,7 +50,7 @@ reg_dc_in: dc-in-12v { - regulator-always-on; - }; - -- reg_vcc_4v: vcc-4v { -+ reg_vcc_4v: regulator-vcc-4v { - compatible = "regulator-fixed"; - regulator-name = "vcc_4v"; - regulator-min-microvolt = <4000000>; -@@ -60,7 +60,7 @@ reg_vcc_4v: vcc-4v { - vin-supply = <®_dc_in>; - }; - -- usb3-vbus-5v { -+ regulator-usb3-vbus-5v { - compatible = "regulator-fixed"; - regulator-name = "USB30_VBUS"; - regulator-min-microvolt = <5000000>; -@@ -70,7 +70,7 @@ usb3-vbus-5v { - enable-active-high; - }; - -- usb3_hub_5v: usb3-hub-5v { -+ usb3_hub_5v: regulator-usb3-hub-5v { - compatible = "regulator-fixed"; - regulator-name = "USB30_HUB"; - regulator-min-microvolt = <5000000>; -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index e2702a781734..9959c8023ece 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -21,7 +21,7 @@ chosen { - stdout-path = "serial0"; - }; - -- reg_dc_in: dc-in-12v { -+ reg_dc_in: regulator-dc-in-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_in_12v"; - regulator-min-microvolt = <12000000>; -@@ -30,7 +30,7 @@ reg_dc_in: dc-in-12v { - regulator-always-on; - }; - -- reg_vcc_4v: vcc-4v { -+ reg_vcc_4v: regulator-vcc-4v { - compatible = "regulator-fixed"; - regulator-name = "vcc_4v"; - regulator-min-microvolt = <4000000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch b/SPECS/linux-lts-kmhv2/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch new file mode 100644 index 0000000000..d84cac3c6d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch @@ -0,0 +1,126 @@ +From d685ab6d599ba502610b5f425c35683c2c838c0a Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 4 Mar 2026 07:36:42 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add clock tree + +Add clock support to SpacemiT K3 SoC, the clock tree consist of several +blocks which are APBC, APMU, DCIU, MPUM. + +Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-1-50a0aa53a245@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 67072c8cd48c1fbb95cea39239eba5526395fcf5) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++ + 1 file changed, 75 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index b69cf81b5d55..e3d7f3102fd5 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -4,6 +4,7 @@ + * Copyright (c) 2026 Guodong Xu + */ + ++#include + #include + + /dts-v1/; +@@ -398,6 +399,36 @@ core3 { + }; + }; + ++ clocks { ++ vctcxo_1m: clock-1m { ++ compatible = "fixed-clock"; ++ clock-frequency = <1000000>; ++ clock-output-names = "vctcxo_1m"; ++ #clock-cells = <0>; ++ }; ++ ++ vctcxo_24m: clock-24m { ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ clock-output-names = "vctcxo_24m"; ++ #clock-cells = <0>; ++ }; ++ ++ vctcxo_3m: clock-3m { ++ compatible = "fixed-clock"; ++ clock-frequency = <3000000>; ++ clock-output-names = "vctcxo_3m"; ++ #clock-cells = <0>; ++ }; ++ ++ osc_32k: clock-32k { ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++ clock-output-names = "osc_32k"; ++ #clock-cells = <0>; ++ }; ++ }; ++ + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&saplic>; +@@ -406,6 +437,15 @@ soc: soc { + dma-noncoherent; + ranges; + ++ syscon_apbc: system-controller@d4015000 { ++ compatible = "spacemit,k3-syscon-apbc"; ++ reg = <0x0 0xd4015000 0x0 0x1000>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; ++ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ + uart0: serial@d4017000 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017000 0x0 0x100>; +@@ -506,6 +546,41 @@ uart10: serial@d401f000 { + status = "disabled"; + }; + ++ syscon_mpmu: system-controller@d4050000 { ++ compatible = "spacemit,k3-syscon-mpmu"; ++ reg = <0x0 0xd4050000 0x0 0x10000>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; ++ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; ++ #clock-cells = <1>; ++ #power-domain-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ pll: clock-controller@d4090000 { ++ compatible = "spacemit,k3-pll"; ++ reg = <0x0 0xd4090000 0x0 0x10000>; ++ clocks = <&vctcxo_24m>; ++ spacemit,mpmu = <&syscon_mpmu>; ++ #clock-cells = <1>; ++ }; ++ ++ syscon_apmu: system-controller@d4282800 { ++ compatible = "spacemit,k3-syscon-apmu"; ++ reg = <0x0 0xd4282800 0x0 0x400>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; ++ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; ++ #clock-cells = <1>; ++ #power-domain-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_dciu: system-controller@d8440000 { ++ compatible = "spacemit,k3-syscon-dciu"; ++ reg = <0x0 0xd8440000 0x0 0xc000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ + simsic: interrupt-controller@e0400000 { + compatible = "spacemit,k3-imsics", "riscv,imsics"; + reg = <0x0 0xe0400000 0x0 0x200000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0217-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch b/SPECS/linux-lts-kmhv2/0217-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch deleted file mode 100644 index 29c5e0b70c..0000000000 --- a/SPECS/linux-lts-kmhv2/0217-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 6763f6325a6f023a8781d9eda31e4313f90861b7 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 9 Mar 2026 11:00:00 +0800 -Subject: [PATCH 217/467] UPSTREAM: riscv: dts: spacemit: Add - 'linux,pci-domain' to PCIe nodes for K1 - -The SpacemiT K1 SoC has 3 PCIe EP controller nodes. Add the -'linux,pci-domain' property to assign a PCI domain number to -each of the controllers instead of assigning it randomly. - -This creates a stable sysfs path, allowing userspace scripts -to reliably target specific PCIe devices (such as PCIe NICs). - -Signed-off-by: Chukun Pan -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260309030000.1157040-1-amadeus@jmu.edu.cn -Signed-off-by: Yixun Lan -(cherry picked from commit 86314111f654310a69c9775e35e263c036031675) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 529ec68e9c23..d2015201f8e5 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -1033,6 +1033,7 @@ pcie-bus { - #size-cells = <2>; - dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, - <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; -+ - pcie0: pcie@ca000000 { - device_type = "pci"; - compatible = "spacemit,k1-pcie"; -@@ -1044,6 +1045,7 @@ pcie0: pcie@ca000000 { - "atu", - "config", - "link"; -+ linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, -@@ -1087,6 +1089,7 @@ pcie1: pcie@ca400000 { - "atu", - "config", - "link"; -+ linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, -@@ -1130,6 +1133,7 @@ pcie2: pcie@ca800000 { - "atu", - "config", - "link"; -+ linux,pci-domain = <2>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch b/SPECS/linux-lts-kmhv2/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch new file mode 100644 index 0000000000..43081756d0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch @@ -0,0 +1,38 @@ +From 26584036220607376da285b0c0cf42306e1dc824 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 4 Mar 2026 07:36:43 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add pinctrl support + +Populate pinctrl node in Device Tree for SpacemiT K3 SoC, So devices +can request pinctrl resource properly. + +Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-2-50a0aa53a245@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit d8944577496b5b99061d3b2020704fc86ab1f9e6) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index e3d7f3102fd5..6449ab056293 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -536,6 +536,14 @@ uart9: serial@d4017800 { + status = "disabled"; + }; + ++ pinctrl: pinctrl@d401e000 { ++ compatible = "spacemit,k3-pinctrl"; ++ reg = <0x0 0xd401e000 0x0 0x1000>; ++ clocks = <&syscon_apbc CLK_APBC_AIB>, ++ <&syscon_apbc CLK_APBC_AIB_BUS>; ++ clock-names = "func", "bus"; ++ }; ++ + uart10: serial@d401f000 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd401f000 0x0 0x100>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0218-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch b/SPECS/linux-lts-kmhv2/0218-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch deleted file mode 100644 index cbfd5a28a6..0000000000 --- a/SPECS/linux-lts-kmhv2/0218-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 8a9141deb50f0c4e00218a10123b0b9653a96872 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 4 Mar 2026 07:19:39 +0000 -Subject: [PATCH 218/467] UPSTREAM: dt-bindings: serial: 8250: spacemit: fix - clock property for K3 SoC - -The UART of SpacemiT K3 SoC has same clock property as K1 generation which -request two clock sources, fix the binding otherwise will get DT check -warnings. - -Acked-by: Greg Kroah-Hartman -Acked-by: Rob Herring (Arm) -Link: https://lore.kernel.org/r/20260304-01-uart-clock-names-v1-1-338483f04a8b@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit 606a6b8bca570aa4f838ddd410345a2937bd98eb) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/serial/8250.yaml | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml -index b243afa69a1a..0d4ae9a62f4c 100644 ---- a/Documentation/devicetree/bindings/serial/8250.yaml -+++ b/Documentation/devicetree/bindings/serial/8250.yaml -@@ -63,7 +63,9 @@ allOf: - properties: - compatible: - contains: -- const: spacemit,k1-uart -+ enum: -+ - spacemit,k1-uart -+ - spacemit,k3-uart - then: - properties: - clock-names: -@@ -76,6 +78,7 @@ allOf: - contains: - enum: - - spacemit,k1-uart -+ - spacemit,k3-uart - - nxp,lpc1850-uart - then: - required: --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch b/SPECS/linux-lts-kmhv2/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch new file mode 100644 index 0000000000..dae1e8f109 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch @@ -0,0 +1,48 @@ +From d0197dc9c7ce0b6d04f508db631f06668553d958 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 4 Mar 2026 07:36:44 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add GPIO support + +Add GPIO node in the Device Tree, so devices are able to request GPIO +resource properly. + +Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-3-50a0aa53a245@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 20b77926864203e10b85af5276b17c2812d92ec1) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 6449ab056293..3683a1a65362 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -536,6 +536,24 @@ uart9: serial@d4017800 { + status = "disabled"; + }; + ++ gpio: gpio@d4019000 { ++ compatible = "spacemit,k3-gpio"; ++ reg = <0x0 0xd4019000 0x0 0x100>; ++ clocks = <&syscon_apbc CLK_APBC_GPIO>, ++ <&syscon_apbc CLK_APBC_GPIO_BUS>; ++ clock-names = "core", "bus"; ++ gpio-controller; ++ #gpio-cells = <3>; ++ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ gpio-ranges = <&pinctrl 0 0 0 32>, ++ <&pinctrl 1 0 32 32>, ++ <&pinctrl 2 0 64 32>, ++ <&pinctrl 3 0 96 32>; ++ }; ++ + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k3-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0219-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch b/SPECS/linux-lts-kmhv2/0219-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch deleted file mode 100644 index 08aa7a8885..0000000000 --- a/SPECS/linux-lts-kmhv2/0219-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch +++ /dev/null @@ -1,126 +0,0 @@ -From d6d720c6f2938cc35fbb2411f4bcfffe2d3210cc Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 4 Mar 2026 07:36:42 +0000 -Subject: [PATCH 219/467] UPSTREAM: riscv: dts: spacemit: k3: add clock tree - -Add clock support to SpacemiT K3 SoC, the clock tree consist of several -blocks which are APBC, APMU, DCIU, MPUM. - -Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-1-50a0aa53a245@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit 67072c8cd48c1fbb95cea39239eba5526395fcf5) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++ - 1 file changed, 75 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index b69cf81b5d55..e3d7f3102fd5 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -4,6 +4,7 @@ - * Copyright (c) 2026 Guodong Xu - */ - -+#include - #include - - /dts-v1/; -@@ -398,6 +399,36 @@ core3 { - }; - }; - -+ clocks { -+ vctcxo_1m: clock-1m { -+ compatible = "fixed-clock"; -+ clock-frequency = <1000000>; -+ clock-output-names = "vctcxo_1m"; -+ #clock-cells = <0>; -+ }; -+ -+ vctcxo_24m: clock-24m { -+ compatible = "fixed-clock"; -+ clock-frequency = <24000000>; -+ clock-output-names = "vctcxo_24m"; -+ #clock-cells = <0>; -+ }; -+ -+ vctcxo_3m: clock-3m { -+ compatible = "fixed-clock"; -+ clock-frequency = <3000000>; -+ clock-output-names = "vctcxo_3m"; -+ #clock-cells = <0>; -+ }; -+ -+ osc_32k: clock-32k { -+ compatible = "fixed-clock"; -+ clock-frequency = <32000>; -+ clock-output-names = "osc_32k"; -+ #clock-cells = <0>; -+ }; -+ }; -+ - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&saplic>; -@@ -406,6 +437,15 @@ soc: soc { - dma-noncoherent; - ranges; - -+ syscon_apbc: system-controller@d4015000 { -+ compatible = "spacemit,k3-syscon-apbc"; -+ reg = <0x0 0xd4015000 0x0 0x1000>; -+ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; -+ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ - uart0: serial@d4017000 { - compatible = "spacemit,k3-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017000 0x0 0x100>; -@@ -506,6 +546,41 @@ uart10: serial@d401f000 { - status = "disabled"; - }; - -+ syscon_mpmu: system-controller@d4050000 { -+ compatible = "spacemit,k3-syscon-mpmu"; -+ reg = <0x0 0xd4050000 0x0 0x10000>; -+ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; -+ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; -+ #clock-cells = <1>; -+ #power-domain-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ pll: clock-controller@d4090000 { -+ compatible = "spacemit,k3-pll"; -+ reg = <0x0 0xd4090000 0x0 0x10000>; -+ clocks = <&vctcxo_24m>; -+ spacemit,mpmu = <&syscon_mpmu>; -+ #clock-cells = <1>; -+ }; -+ -+ syscon_apmu: system-controller@d4282800 { -+ compatible = "spacemit,k3-syscon-apmu"; -+ reg = <0x0 0xd4282800 0x0 0x400>; -+ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; -+ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; -+ #clock-cells = <1>; -+ #power-domain-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ syscon_dciu: system-controller@d8440000 { -+ compatible = "spacemit,k3-syscon-dciu"; -+ reg = <0x0 0xd8440000 0x0 0xc000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ - simsic: interrupt-controller@e0400000 { - compatible = "spacemit,k3-imsics", "riscv,imsics"; - reg = <0x0 0xe0400000 0x0 0x200000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch b/SPECS/linux-lts-kmhv2/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch new file mode 100644 index 0000000000..581044da67 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch @@ -0,0 +1,206 @@ +From 186d384a785aeb3b664585647bd06ee2009145dd Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 4 Mar 2026 07:36:45 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add full resource to + UART + +Previously the UART rely on external bootloader to initialize clock, +pinctrl and reset, to solve this, explicitly adding those resource in +Device Tree, so UART driver will handle them properly. + +Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-4-50a0aa53a245@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 28a7f755d7c9a4b9c41c12620fb4885f39b554ad) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 ++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 24 +++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 51 ++++++++++++++++---- + 3 files changed, 68 insertions(+), 10 deletions(-) + create mode 100644 arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index b691304d4b74..b098dbd0e7a1 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -5,6 +5,7 @@ + */ + + #include "k3.dtsi" ++#include "k3-pinctrl.dtsi" + + / { + model = "SpacemiT K3 Pico-ITX"; +@@ -25,5 +26,7 @@ memory@100000000 { + }; + + &uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_0_cfg>; + status = "okay"; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +new file mode 100644 +index 000000000000..efb0f1572188 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -0,0 +1,24 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (c) 2026 Yixun Lan ++ */ ++ ++#include ++ ++#define K3_PADCONF(pin, func) (((pin) << 16) | (func)) ++ ++/* Map GPIO pin to each bank's */ ++#define K3_GPIO(x) (x / 32) (x % 32) ++ ++&pinctrl { ++ /omit-if-no-ref/ ++ uart0_0_cfg: uart0-0-cfg { ++ uart0-0-pins { ++ pinmux = , /* uart0 tx */ ++ ; /* uart0 rx */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 3683a1a65362..a3a8ceddabec 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -5,6 +5,7 @@ + */ + + #include ++#include + #include + + /dts-v1/; +@@ -451,7 +452,10 @@ uart0: serial@d4017000 { + reg = <0x0 0xd4017000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART0>, ++ <&syscon_apbc CLK_APBC_UART0_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART0>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -461,7 +465,10 @@ uart2: serial@d4017100 { + reg = <0x0 0xd4017100 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART2>, ++ <&syscon_apbc CLK_APBC_UART2_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART2>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -471,7 +478,10 @@ uart3: serial@d4017200 { + reg = <0x0 0xd4017200 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART3>, ++ <&syscon_apbc CLK_APBC_UART3_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART3>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -481,7 +491,10 @@ uart4: serial@d4017300 { + reg = <0x0 0xd4017300 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART4>, ++ <&syscon_apbc CLK_APBC_UART4_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART4>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -491,7 +504,10 @@ uart5: serial@d4017400 { + reg = <0x0 0xd4017400 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART5>, ++ <&syscon_apbc CLK_APBC_UART5_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART5>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -501,7 +517,10 @@ uart6: serial@d4017500 { + reg = <0x0 0xd4017500 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART6>, ++ <&syscon_apbc CLK_APBC_UART6_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART6>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -511,7 +530,10 @@ uart7: serial@d4017600 { + reg = <0x0 0xd4017600 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART7>, ++ <&syscon_apbc CLK_APBC_UART7_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART7>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -521,7 +543,10 @@ uart8: serial@d4017700 { + reg = <0x0 0xd4017700 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART8>, ++ <&syscon_apbc CLK_APBC_UART8_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART8>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -531,7 +556,10 @@ uart9: serial@d4017800 { + reg = <0x0 0xd4017800 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART9>, ++ <&syscon_apbc CLK_APBC_UART9_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART9>; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -567,7 +595,10 @@ uart10: serial@d401f000 { + reg = <0x0 0xd401f000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART10>, ++ <&syscon_apbc CLK_APBC_UART10_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART10>; + interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch b/SPECS/linux-lts-kmhv2/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch new file mode 100644 index 0000000000..a15e56ca61 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch @@ -0,0 +1,59 @@ +From 8ded8df1d9dccc63760629834a87ae2c8615e042 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 20 Mar 2026 07:15:37 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: dwc3: spacemit: add support + for K3 SoC + +Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC. + +The USB2.0 host controller in K3 SoC actually use DWC3 IP but only support +USB2.0 functionality, thus in the hardware layer, it has only one USB2 PHY. +While in K1 SoC, the USB controller has both USB2 and USB3 Combo PHY +connected, but able to work in a reduced USB2.0 mode which requres only +one USB2 PHY, leaves the USB3 Combo PHY to PCIe controller. So both K1 +and K3 SoC are able to work in the USB2.0 mode which requires one PHY. + +Explicitly reduce number of phy property to minimal one. + +Signed-off-by: Yixun Lan +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260320-02-k3-usb20-support-v2-1-308ea0e44038@kernel.org +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit e7e86965a69d0f6797116e54dda01b56deca71c0) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml +index 0f0b5e061ca1..cc27b363ca79 100644 +--- a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml ++++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml +@@ -27,7 +27,9 @@ allOf: + + properties: + compatible: +- const: spacemit,k1-dwc3 ++ enum: ++ - spacemit,k1-dwc3 ++ - spacemit,k3-dwc3 + + reg: + maxItems: 1 +@@ -42,11 +44,13 @@ properties: + maxItems: 1 + + phys: ++ minItems: 1 + items: + - description: phandle to USB2/HS PHY + - description: phandle to USB3/SS PHY + + phy-names: ++ minItems: 1 + items: + - const: usb2-phy + - const: usb3-phy +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0220-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch b/SPECS/linux-lts-kmhv2/0220-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch deleted file mode 100644 index 7467adfc98..0000000000 --- a/SPECS/linux-lts-kmhv2/0220-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch +++ /dev/null @@ -1,39 +0,0 @@ -From b712bbdcd69a0cf77827e15a2b8d0c593a348c55 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 4 Mar 2026 07:36:43 +0000 -Subject: [PATCH 220/467] UPSTREAM: riscv: dts: spacemit: k3: add pinctrl - support - -Populate pinctrl node in Device Tree for SpacemiT K3 SoC, So devices -can request pinctrl resource properly. - -Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-2-50a0aa53a245@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit d8944577496b5b99061d3b2020704fc86ab1f9e6) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index e3d7f3102fd5..6449ab056293 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -536,6 +536,14 @@ uart9: serial@d4017800 { - status = "disabled"; - }; - -+ pinctrl: pinctrl@d401e000 { -+ compatible = "spacemit,k3-pinctrl"; -+ reg = <0x0 0xd401e000 0x0 0x1000>; -+ clocks = <&syscon_apbc CLK_APBC_AIB>, -+ <&syscon_apbc CLK_APBC_AIB_BUS>; -+ clock-names = "func", "bus"; -+ }; -+ - uart10: serial@d401f000 { - compatible = "spacemit,k3-uart", "intel,xscale-uart"; - reg = <0x0 0xd401f000 0x0 0x100>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0221-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch b/SPECS/linux-lts-kmhv2/0221-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch deleted file mode 100644 index 267f0b7a53..0000000000 --- a/SPECS/linux-lts-kmhv2/0221-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 42bb1ee59c5be1344c00b635eb294286c0516236 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 4 Mar 2026 07:36:44 +0000 -Subject: [PATCH 221/467] UPSTREAM: riscv: dts: spacemit: k3: add GPIO support - -Add GPIO node in the Device Tree, so devices are able to request GPIO -resource properly. - -Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-3-50a0aa53a245@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit 20b77926864203e10b85af5276b17c2812d92ec1) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 6449ab056293..3683a1a65362 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -536,6 +536,24 @@ uart9: serial@d4017800 { - status = "disabled"; - }; - -+ gpio: gpio@d4019000 { -+ compatible = "spacemit,k3-gpio"; -+ reg = <0x0 0xd4019000 0x0 0x100>; -+ clocks = <&syscon_apbc CLK_APBC_GPIO>, -+ <&syscon_apbc CLK_APBC_GPIO_BUS>; -+ clock-names = "core", "bus"; -+ gpio-controller; -+ #gpio-cells = <3>; -+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&saplic>; -+ interrupt-controller; -+ #interrupt-cells = <3>; -+ gpio-ranges = <&pinctrl 0 0 0 32>, -+ <&pinctrl 1 0 32 32>, -+ <&pinctrl 2 0 64 32>, -+ <&pinctrl 3 0 96 32>; -+ }; -+ - pinctrl: pinctrl@d401e000 { - compatible = "spacemit,k3-pinctrl"; - reg = <0x0 0xd401e000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch b/SPECS/linux-lts-kmhv2/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch new file mode 100644 index 0000000000..45a1cbb328 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch @@ -0,0 +1,33 @@ +From 27133a501e88e5b271c1a5c98f2013d1f8dc931a Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 20 Mar 2026 07:15:38 +0000 +Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: dwc3-generic-plat: spacemit: add + support for K3 SoC + +Add support for the DWC3 USB controller which found in SpacemiT K3 SoC. + +Acked-by: Thinh Nguyen +Signed-off-by: Yixun Lan +Link: https://patch.msgid.link/20260320-02-k3-usb20-support-v2-2-308ea0e44038@kernel.org +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit c05cf9d274daf72dc7e433480cf2e0e888f6bd89) +Signed-off-by: Han Gao +--- + drivers/usb/dwc3/dwc3-generic-plat.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c +index e846844e0023..28219968b8b0 100644 +--- a/drivers/usb/dwc3/dwc3-generic-plat.c ++++ b/drivers/usb/dwc3/dwc3-generic-plat.c +@@ -212,6 +212,7 @@ static const struct dwc3_generic_config eic7700_dwc3 = { + + static const struct of_device_id dwc3_generic_of_match[] = { + { .compatible = "spacemit,k1-dwc3", }, ++ { .compatible = "spacemit,k3-dwc3", }, + { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, + { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, + { /* sentinel */ } +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0222-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch b/SPECS/linux-lts-kmhv2/0222-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch deleted file mode 100644 index 5ed83a3077..0000000000 --- a/SPECS/linux-lts-kmhv2/0222-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch +++ /dev/null @@ -1,206 +0,0 @@ -From e189d040b406ed393e4e7d5bf768de16b63cdf18 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 4 Mar 2026 07:36:45 +0000 -Subject: [PATCH 222/467] UPSTREAM: riscv: dts: spacemit: k3: add full resource - to UART - -Previously the UART rely on external bootloader to initialize clock, -pinctrl and reset, to solve this, explicitly adding those resource in -Device Tree, so UART driver will handle them properly. - -Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-4-50a0aa53a245@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit 28a7f755d7c9a4b9c41c12620fb4885f39b554ad) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 ++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 24 +++++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 51 ++++++++++++++++---- - 3 files changed, 68 insertions(+), 10 deletions(-) - create mode 100644 arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index b691304d4b74..b098dbd0e7a1 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -5,6 +5,7 @@ - */ - - #include "k3.dtsi" -+#include "k3-pinctrl.dtsi" - - / { - model = "SpacemiT K3 Pico-ITX"; -@@ -25,5 +26,7 @@ memory@100000000 { - }; - - &uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_0_cfg>; - status = "okay"; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -new file mode 100644 -index 000000000000..efb0f1572188 ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: GPL-2.0 OR MIT -+/* -+ * Copyright (c) 2026 Yixun Lan -+ */ -+ -+#include -+ -+#define K3_PADCONF(pin, func) (((pin) << 16) | (func)) -+ -+/* Map GPIO pin to each bank's */ -+#define K3_GPIO(x) (x / 32) (x % 32) -+ -+&pinctrl { -+ /omit-if-no-ref/ -+ uart0_0_cfg: uart0-0-cfg { -+ uart0-0-pins { -+ pinmux = , /* uart0 tx */ -+ ; /* uart0 rx */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 3683a1a65362..a3a8ceddabec 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -5,6 +5,7 @@ - */ - - #include -+#include - #include - - /dts-v1/; -@@ -451,7 +452,10 @@ uart0: serial@d4017000 { - reg = <0x0 0xd4017000 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART0>, -+ <&syscon_apbc CLK_APBC_UART0_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART0>; - interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -461,7 +465,10 @@ uart2: serial@d4017100 { - reg = <0x0 0xd4017100 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART2>, -+ <&syscon_apbc CLK_APBC_UART2_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART2>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -471,7 +478,10 @@ uart3: serial@d4017200 { - reg = <0x0 0xd4017200 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART3>, -+ <&syscon_apbc CLK_APBC_UART3_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART3>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -481,7 +491,10 @@ uart4: serial@d4017300 { - reg = <0x0 0xd4017300 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART4>, -+ <&syscon_apbc CLK_APBC_UART4_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART4>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -491,7 +504,10 @@ uart5: serial@d4017400 { - reg = <0x0 0xd4017400 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART5>, -+ <&syscon_apbc CLK_APBC_UART5_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART5>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -501,7 +517,10 @@ uart6: serial@d4017500 { - reg = <0x0 0xd4017500 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART6>, -+ <&syscon_apbc CLK_APBC_UART6_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART6>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -511,7 +530,10 @@ uart7: serial@d4017600 { - reg = <0x0 0xd4017600 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART7>, -+ <&syscon_apbc CLK_APBC_UART7_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART7>; - interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -521,7 +543,10 @@ uart8: serial@d4017700 { - reg = <0x0 0xd4017700 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART8>, -+ <&syscon_apbc CLK_APBC_UART8_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART8>; - interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -531,7 +556,10 @@ uart9: serial@d4017800 { - reg = <0x0 0xd4017800 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART9>, -+ <&syscon_apbc CLK_APBC_UART9_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART9>; - interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -567,7 +595,10 @@ uart10: serial@d401f000 { - reg = <0x0 0xd401f000 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART10>, -+ <&syscon_apbc CLK_APBC_UART10_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART10>; - interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch b/SPECS/linux-lts-kmhv2/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch new file mode 100644 index 0000000000..e9139f8f74 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch @@ -0,0 +1,84 @@ +From ec33bc462214da036d45ea0a3822c34e9f3d422b Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Thu, 26 Mar 2026 18:00:10 +0800 +Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: Add optional VBUS regulator support + to SpacemiT K1 + +Some SpacemiT K1 boards (like OrangePi R2S) provide USB VBUS +through a controllable regulator. Add support for the optional +vbus-supply property so the regulator can be properly managed +in host mode instead of left always-on. Note that this doesn't +apply to USB Hub downstream ports with different VBUS supplies. + +The enabled and disabled actions of the regulator are handled +automatically by devm_regulator_get_enable_optional(). + +Signed-off-by: Chukun Pan +Acked-by: Thinh Nguyen +Reviewed-by: Anand Moon +Link: https://patch.msgid.link/20260326100010.3588454-2-amadeus@jmu.edu.cn +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 764c2e6e60bf17910d84e7179fee14129e053b96) +Signed-off-by: Han Gao +--- + drivers/usb/dwc3/dwc3-generic-plat.c | 23 ++++++++++++++++++++++- + 1 file changed, 22 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c +index 28219968b8b0..69b7e6227b3b 100644 +--- a/drivers/usb/dwc3/dwc3-generic-plat.c ++++ b/drivers/usb/dwc3/dwc3-generic-plat.c +@@ -12,6 +12,8 @@ + #include + #include + #include ++#include ++#include + #include "glue.h" + + #define EIC7700_HSP_BUS_FILTER_EN BIT(0) +@@ -69,6 +71,20 @@ static int dwc3_eic7700_init(struct dwc3_generic *dwc3g) + return 0; + } + ++static int dwc3_spacemit_k1_init(struct dwc3_generic *dwc3g) ++{ ++ struct device *dev = dwc3g->dev; ++ ++ if (usb_get_dr_mode(dev) == USB_DR_MODE_HOST) { ++ int ret = devm_regulator_get_enable_optional(dev, "vbus"); ++ ++ if (ret && ret != -ENODEV) ++ return dev_err_probe(dev, ret, "failed to enable VBUS\n"); ++ } ++ ++ return 0; ++} ++ + static int dwc3_generic_probe(struct platform_device *pdev) + { + const struct dwc3_generic_config *plat_config; +@@ -201,6 +217,11 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { + dwc3_generic_runtime_idle) + }; + ++static const struct dwc3_generic_config spacemit_k1_dwc3 = { ++ .init = dwc3_spacemit_k1_init, ++ .properties = DWC3_DEFAULT_PROPERTIES, ++}; ++ + static const struct dwc3_generic_config fsl_ls1028_dwc3 = { + .properties.gsbuscfg0_reqinfo = 0x2222, + }; +@@ -211,7 +232,7 @@ static const struct dwc3_generic_config eic7700_dwc3 = { + }; + + static const struct of_device_id dwc3_generic_of_match[] = { +- { .compatible = "spacemit,k1-dwc3", }, ++ { .compatible = "spacemit,k1-dwc3", &spacemit_k1_dwc3}, + { .compatible = "spacemit,k3-dwc3", }, + { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, + { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0223-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch b/SPECS/linux-lts-kmhv2/0223-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch deleted file mode 100644 index 11ec0b2493..0000000000 --- a/SPECS/linux-lts-kmhv2/0223-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 65d15c8340d9e4aa40a623ff2449950059808d92 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 20 Mar 2026 07:15:37 +0000 -Subject: [PATCH 223/467] UPSTREAM: dt-bindings: usb: dwc3: spacemit: add - support for K3 SoC - -Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC. - -The USB2.0 host controller in K3 SoC actually use DWC3 IP but only support -USB2.0 functionality, thus in the hardware layer, it has only one USB2 PHY. -While in K1 SoC, the USB controller has both USB2 and USB3 Combo PHY -connected, but able to work in a reduced USB2.0 mode which requres only -one USB2 PHY, leaves the USB3 Combo PHY to PCIe controller. So both K1 -and K3 SoC are able to work in the USB2.0 mode which requires one PHY. - -Explicitly reduce number of phy property to minimal one. - -Signed-off-by: Yixun Lan -Acked-by: Conor Dooley -Link: https://patch.msgid.link/20260320-02-k3-usb20-support-v2-1-308ea0e44038@kernel.org -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit e7e86965a69d0f6797116e54dda01b56deca71c0) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml -index 0f0b5e061ca1..cc27b363ca79 100644 ---- a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml -+++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml -@@ -27,7 +27,9 @@ allOf: - - properties: - compatible: -- const: spacemit,k1-dwc3 -+ enum: -+ - spacemit,k1-dwc3 -+ - spacemit,k3-dwc3 - - reg: - maxItems: 1 -@@ -42,11 +44,13 @@ properties: - maxItems: 1 - - phys: -+ minItems: 1 - items: - - description: phandle to USB2/HS PHY - - description: phandle to USB3/SS PHY - - phy-names: -+ minItems: 1 - items: - - const: usb2-phy - - const: usb3-phy --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch b/SPECS/linux-lts-kmhv2/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch new file mode 100644 index 0000000000..4c498e66d6 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch @@ -0,0 +1,148 @@ +From feb6ae05030bda7ec7a43a8384cfdffc80d33e30 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Wed, 18 Mar 2026 18:00:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: reorder phy nodes for K1 + +Reorder the PHY nodes of USB and PCIe to the correct positions based on +the register address. This improves the readability and maintainability +of the DT. No functional change is introduced by this reordering. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260318100000.3934516-1-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit eac600d5cc42b04e799fb65169b8f4060773381b) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 108 +++++++++++++-------------- + 1 file changed, 54 insertions(+), 54 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index d2015201f8e5..f0bad6855c97 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -359,6 +359,60 @@ syscon_rcpu2: system-controller@c0888000 { + #reset-cells = <1>; + }; + ++ usbphy2: phy@c0a30000 { ++ compatible = "spacemit,k1-usb2-phy"; ++ reg = <0x0 0xc0a30000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_USB30>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ combo_phy: phy@c0b10000 { ++ compatible = "spacemit,k1-combo-phy"; ++ reg = <0x0 0xc0b10000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>, ++ <&syscon_apmu CLK_PCIE0_DBI>, ++ <&syscon_apmu CLK_PCIE0_MASTER>, ++ <&syscon_apmu CLK_PCIE0_SLAVE>; ++ clock-names = "refclk", ++ "dbi", ++ "mstr", ++ "slv"; ++ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, ++ <&syscon_apmu RESET_PCIE0_DBI>, ++ <&syscon_apmu RESET_PCIE0_MASTER>, ++ <&syscon_apmu RESET_PCIE0_SLAVE>; ++ reset-names = "phy", ++ "dbi", ++ "mstr", ++ "slv"; ++ #phy-cells = <1>; ++ spacemit,apmu = <&syscon_apmu>; ++ status = "disabled"; ++ }; ++ ++ pcie1_phy: phy@c0c10000 { ++ compatible = "spacemit,k1-pcie-phy"; ++ reg = <0x0 0xc0c10000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>; ++ clock-names = "refclk"; ++ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; ++ reset-names = "phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie2_phy: phy@c0d10000 { ++ compatible = "spacemit,k1-pcie-phy"; ++ reg = <0x0 0xc0d10000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>; ++ clock-names = "refclk"; ++ resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; ++ reset-names = "phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@d4010800 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd4010800 0x0 0x38>; +@@ -429,60 +483,6 @@ i2c5: i2c@d4013800 { + status = "disabled"; + }; + +- usbphy2: phy@c0a30000 { +- compatible = "spacemit,k1-usb2-phy"; +- reg = <0x0 0xc0a30000 0x0 0x200>; +- clocks = <&syscon_apmu CLK_USB30>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- combo_phy: phy@c0b10000 { +- compatible = "spacemit,k1-combo-phy"; +- reg = <0x0 0xc0b10000 0x0 0x1000>; +- clocks = <&vctcxo_24m>, +- <&syscon_apmu CLK_PCIE0_DBI>, +- <&syscon_apmu CLK_PCIE0_MASTER>, +- <&syscon_apmu CLK_PCIE0_SLAVE>; +- clock-names = "refclk", +- "dbi", +- "mstr", +- "slv"; +- resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, +- <&syscon_apmu RESET_PCIE0_DBI>, +- <&syscon_apmu RESET_PCIE0_MASTER>, +- <&syscon_apmu RESET_PCIE0_SLAVE>; +- reset-names = "phy", +- "dbi", +- "mstr", +- "slv"; +- #phy-cells = <1>; +- spacemit,apmu = <&syscon_apmu>; +- status = "disabled"; +- }; +- +- pcie1_phy: phy@c0c10000 { +- compatible = "spacemit,k1-pcie-phy"; +- reg = <0x0 0xc0c10000 0x0 0x1000>; +- clocks = <&vctcxo_24m>; +- clock-names = "refclk"; +- resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; +- reset-names = "phy"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- pcie2_phy: phy@c0d10000 { +- compatible = "spacemit,k1-pcie-phy"; +- reg = <0x0 0xc0d10000 0x0 0x1000>; +- clocks = <&vctcxo_24m>; +- clock-names = "refclk"; +- resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; +- reset-names = "phy"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k1-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch b/SPECS/linux-lts-kmhv2/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch new file mode 100644 index 0000000000..7d60f42287 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch @@ -0,0 +1,42 @@ +From 9c90526d6c53498c2b0fce296ea54822274f4e03 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Sun, 22 Mar 2026 21:25:01 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: drop incorrect pinctrl + for combo PHY + +The combo PHY on the Banana Pi F3 is used for the USB 3.0 port. The high +speed differential lanes are always configured as such, and do not +require a pinctrl entry. + +The existing pinctrl entry only configures PCIe secondary pins, which +are unused for USB and instead routed to the MIPI CSI1 connector. + +Remove this incorrect pinctrl entry. + +Fixes: 0be016a4b5d1b9 ("riscv: dts: spacemit: PCIe and PHY-related updates") +Signed-off-by: Aurelien Jarno +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260322202502.2205755-1-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit c68360c0d636dae71f766b7b296ddfcf2827ccc7) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 404b69c47b91..5790d927b93d 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -81,8 +81,6 @@ usb3_hub_5v: regulator-usb3-hub-5v { + }; + + &combo_phy { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_3_cfg>; + status = "okay"; + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0224-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch b/SPECS/linux-lts-kmhv2/0224-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch deleted file mode 100644 index dc96a39982..0000000000 --- a/SPECS/linux-lts-kmhv2/0224-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch +++ /dev/null @@ -1,33 +0,0 @@ -From d139bb98d6afd681a1d2b0a68a1986ce01b0e4b7 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 20 Mar 2026 07:15:38 +0000 -Subject: [PATCH 224/467] UPSTREAM: usb: dwc3: dwc3-generic-plat: spacemit: add - support for K3 SoC - -Add support for the DWC3 USB controller which found in SpacemiT K3 SoC. - -Acked-by: Thinh Nguyen -Signed-off-by: Yixun Lan -Link: https://patch.msgid.link/20260320-02-k3-usb20-support-v2-2-308ea0e44038@kernel.org -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit c05cf9d274daf72dc7e433480cf2e0e888f6bd89) -Signed-off-by: Han Gao ---- - drivers/usb/dwc3/dwc3-generic-plat.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c -index e846844e0023..28219968b8b0 100644 ---- a/drivers/usb/dwc3/dwc3-generic-plat.c -+++ b/drivers/usb/dwc3/dwc3-generic-plat.c -@@ -212,6 +212,7 @@ static const struct dwc3_generic_config eic7700_dwc3 = { - - static const struct of_device_id dwc3_generic_of_match[] = { - { .compatible = "spacemit,k1-dwc3", }, -+ { .compatible = "spacemit,k3-dwc3", }, - { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, - { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, - { /* sentinel */ } --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch b/SPECS/linux-lts-kmhv2/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch new file mode 100644 index 0000000000..daa6d30ac8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch @@ -0,0 +1,241 @@ +From f1fd9849a3a86e6e7567394bcfbd7e80314e1925 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 26 Mar 2026 09:46:17 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add ethernet device for + K3 + +Add all ethernet device nodes for K3 SoC. + +Signed-off-by: Inochi Amaoto +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326014617.1011732-1-inochiama@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 74657a376960252e248089e518cfaaf813906989) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 20 ++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 34 ++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 117 +++++++++++++++++++ + 3 files changed, 171 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index b098dbd0e7a1..504fe6bd46b2 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -3,6 +3,7 @@ + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Guodong Xu + */ ++#include + + #include "k3.dtsi" + #include "k3-pinctrl.dtsi" +@@ -12,6 +13,7 @@ / { + compatible = "spacemit,k3-pico-itx", "spacemit,k3"; + + aliases { ++ ethernet0 = ð0; + serial0 = &uart0; + }; + +@@ -25,6 +27,24 @@ memory@100000000 { + }; + }; + ++ð0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&phy0>; ++ status = "okay"; ++ ++ mdio { ++ phy0: phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <10000>; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index efb0f1572188..a7b5d10c332e 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -11,6 +11,40 @@ + #define K3_GPIO(x) (x / 32) (x % 32) + + &pinctrl { ++ gmac0_rgmii_0_cfg: gmac0-rgmii-0-cfg { ++ gmac0-rgmii-0-pins { ++ pinmux = , /* gmac0_rxdv */ ++ , /* gmac0_rx_d0 */ ++ , /* gmac0_rx_d1 */ ++ , /* gmac0_rx_clk */ ++ , /* gmac0_rx_d2 */ ++ , /* gmac0_rx_d3 */ ++ , /* gmac0_tx_d0 */ ++ , /* gmac0_tx_d1 */ ++ , /* gmac0_tx_clk */ ++ , /* gmac0_tx_d2 */ ++ , /* gmac0_tx_d3 */ ++ , /* gmac0_tx_en */ ++ , /* gmac0_mdc */ ++ ; /* gmac0_mdio */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ power-source = <1800>; ++ }; ++ ++ }; ++ ++ gmac0_phy_0_cfg: gmac0-phy-0-cfg { ++ gmac0-phy-0-pins { ++ pinmux = ; /* gmac0_int */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ power-source = <1800>; ++ }; ++ }; ++ + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index a3a8ceddabec..5f4818cd5d6d 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -438,6 +438,123 @@ soc: soc { + dma-noncoherent; + ranges; + ++ eth0: ethernet@cac80000 { ++ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; ++ reg = <0x0 0xcac80000 0x0 0x2000>; ++ clocks = <&syscon_apmu CLK_APMU_EMAC0_BUS>, ++ <&syscon_apmu CLK_APMU_EMAC0_1588>, ++ <&syscon_apmu CLK_APMU_EMAC0_RGMII_TX>; ++ clock-names = "stmmaceth", "ptp_ref", "tx"; ++ interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, ++ <276 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ resets = <&syscon_apmu RESET_APMU_EMAC0>; ++ reset-names = "stmmaceth"; ++ rx-fifo-depth = <8192>; ++ tx-fifo-depth = <8192>; ++ snps,multicast-filter-bins = <64>; ++ snps,perfect-filter-entries = <32>; ++ snps,aal; ++ snps,tso; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ snps,force_sf_dma_mode; ++ snps,axi-config = <&gmac0_axi_setup>; ++ spacemit,apmu = <&syscon_apmu 0x3e4 0x3e8>; ++ status = "disabled"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ gmac0_axi_setup: stmmac-axi-config { ++ snps,wr_osr_lmt = <0xf>; ++ snps,rd_osr_lmt = <0xf>; ++ /* max axi burst len is 256 */ ++ snps,blen = <256 128 64 32 16 0 0>; ++ }; ++ }; ++ ++ eth1: ethernet@cac82000 { ++ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; ++ reg = <0x0 0xcac82000 0x0 0x2000>; ++ clocks = <&syscon_apmu CLK_APMU_EMAC1_BUS>, ++ <&syscon_apmu CLK_APMU_EMAC1_1588>, ++ <&syscon_apmu CLK_APMU_EMAC1_RGMII_TX>; ++ clock-names = "stmmaceth", "ptp_ref", "tx"; ++ interrupts = <133 IRQ_TYPE_LEVEL_HIGH>, ++ <277 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ resets = <&syscon_apmu RESET_APMU_EMAC1>; ++ reset-names = "stmmaceth"; ++ rx-fifo-depth = <8192>; ++ tx-fifo-depth = <8192>; ++ snps,multicast-filter-bins = <64>; ++ snps,perfect-filter-entries = <32>; ++ snps,aal; ++ snps,tso; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ snps,force_sf_dma_mode; ++ snps,axi-config = <&gmac1_axi_setup>; ++ spacemit,apmu = <&syscon_apmu 0x3ec 0x3f0>; ++ status = "disabled"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ gmac1_axi_setup: stmmac-axi-config { ++ snps,wr_osr_lmt = <0xf>; ++ snps,rd_osr_lmt = <0xf>; ++ /* max axi burst len is 256 */ ++ snps,blen = <256 128 64 32 16 0 0>; ++ }; ++ }; ++ ++ eth2: ethernet@cac8e000 { ++ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; ++ reg = <0x0 0xcac8e000 0x0 0x2000>; ++ clocks = <&syscon_apmu CLK_APMU_EMAC2_BUS>, ++ <&syscon_apmu CLK_APMU_EMAC2_1588>, ++ <&syscon_apmu CLK_APMU_EMAC2_RGMII_TX>; ++ clock-names = "stmmaceth", "ptp_ref", "tx"; ++ interrupts = <130 IRQ_TYPE_LEVEL_HIGH>, ++ <278 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ resets = <&syscon_apmu RESET_APMU_EMAC2>; ++ reset-names = "stmmaceth"; ++ rx-fifo-depth = <4096>; ++ tx-fifo-depth = <4096>; ++ snps,multicast-filter-bins = <64>; ++ snps,perfect-filter-entries = <32>; ++ snps,aal; ++ snps,tso; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ snps,force_sf_dma_mode; ++ snps,axi-config = <&gmac2_axi_setup>; ++ spacemit,apmu = <&syscon_apmu 0x248 0x24c>; ++ status = "disabled"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ gmac2_axi_setup: stmmac-axi-config { ++ snps,wr_osr_lmt = <0xf>; ++ snps,rd_osr_lmt = <0xf>; ++ /* max axi burst len is 256 */ ++ snps,blen = <256 128 64 32 16 0 0>; ++ }; ++ }; ++ + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0225-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch b/SPECS/linux-lts-kmhv2/0225-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch deleted file mode 100644 index 2b7267977c..0000000000 --- a/SPECS/linux-lts-kmhv2/0225-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 9990dc7ec3ce2387190d0ea86d2050589b85cd73 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Thu, 26 Mar 2026 18:00:10 +0800 -Subject: [PATCH 225/467] UPSTREAM: usb: dwc3: Add optional VBUS regulator - support to SpacemiT K1 - -Some SpacemiT K1 boards (like OrangePi R2S) provide USB VBUS -through a controllable regulator. Add support for the optional -vbus-supply property so the regulator can be properly managed -in host mode instead of left always-on. Note that this doesn't -apply to USB Hub downstream ports with different VBUS supplies. - -The enabled and disabled actions of the regulator are handled -automatically by devm_regulator_get_enable_optional(). - -Signed-off-by: Chukun Pan -Acked-by: Thinh Nguyen -Reviewed-by: Anand Moon -Link: https://patch.msgid.link/20260326100010.3588454-2-amadeus@jmu.edu.cn -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit 764c2e6e60bf17910d84e7179fee14129e053b96) -Signed-off-by: Han Gao ---- - drivers/usb/dwc3/dwc3-generic-plat.c | 23 ++++++++++++++++++++++- - 1 file changed, 22 insertions(+), 1 deletion(-) - -diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c -index 28219968b8b0..69b7e6227b3b 100644 ---- a/drivers/usb/dwc3/dwc3-generic-plat.c -+++ b/drivers/usb/dwc3/dwc3-generic-plat.c -@@ -12,6 +12,8 @@ - #include - #include - #include -+#include -+#include - #include "glue.h" - - #define EIC7700_HSP_BUS_FILTER_EN BIT(0) -@@ -69,6 +71,20 @@ static int dwc3_eic7700_init(struct dwc3_generic *dwc3g) - return 0; - } - -+static int dwc3_spacemit_k1_init(struct dwc3_generic *dwc3g) -+{ -+ struct device *dev = dwc3g->dev; -+ -+ if (usb_get_dr_mode(dev) == USB_DR_MODE_HOST) { -+ int ret = devm_regulator_get_enable_optional(dev, "vbus"); -+ -+ if (ret && ret != -ENODEV) -+ return dev_err_probe(dev, ret, "failed to enable VBUS\n"); -+ } -+ -+ return 0; -+} -+ - static int dwc3_generic_probe(struct platform_device *pdev) - { - const struct dwc3_generic_config *plat_config; -@@ -201,6 +217,11 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { - dwc3_generic_runtime_idle) - }; - -+static const struct dwc3_generic_config spacemit_k1_dwc3 = { -+ .init = dwc3_spacemit_k1_init, -+ .properties = DWC3_DEFAULT_PROPERTIES, -+}; -+ - static const struct dwc3_generic_config fsl_ls1028_dwc3 = { - .properties.gsbuscfg0_reqinfo = 0x2222, - }; -@@ -211,7 +232,7 @@ static const struct dwc3_generic_config eic7700_dwc3 = { - }; - - static const struct of_device_id dwc3_generic_of_match[] = { -- { .compatible = "spacemit,k1-dwc3", }, -+ { .compatible = "spacemit,k1-dwc3", &spacemit_k1_dwc3}, - { .compatible = "spacemit,k3-dwc3", }, - { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, - { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch b/SPECS/linux-lts-kmhv2/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch new file mode 100644 index 0000000000..0ef10a2c37 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch @@ -0,0 +1,60 @@ +From 22e068c1b0db347abe57240b5f4e6aea284b400a Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 26 Mar 2026 19:35:29 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add LEDs for Milk-V + Jupiter board + +The Milk-V Jupiter board provides support for two LEDs through the front +panel header. The "Power LED" indicates the system is running, and the +"HDD LED" shows disk activity. Configure the corresponding LED triggers +accordingly. + +Caveats: +- The LEDs are driven through a 4.7k series resistor, making them + quite faint. +- The disk activity trigger requires a storage controller on the M.2 or + PCIe interface. That said, it matches the purpose and the vendor + kernel. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326183745.1370642-2-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 334e64abacd3df4005de80b082d0dbf02b453c76) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 9959c8023ece..3cd83c5924e4 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -21,6 +21,23 @@ chosen { + stdout-path = "serial0"; + }; + ++ leds { ++ compatible = "gpio-leds"; ++ ++ led1 { ++ label = "pwr-led"; ++ gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-on"; ++ default-state = "on"; ++ }; ++ ++ led2 { ++ label = "hdd-led"; ++ gpios = <&gpio K1_GPIO(92) GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "disk-activity"; ++ }; ++ }; ++ + reg_dc_in: regulator-dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0226-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch b/SPECS/linux-lts-kmhv2/0226-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch deleted file mode 100644 index a511212ed8..0000000000 --- a/SPECS/linux-lts-kmhv2/0226-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch +++ /dev/null @@ -1,149 +0,0 @@ -From eed2d8946ef831dead32e3b9c4d588b283ae1195 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Wed, 18 Mar 2026 18:00:00 +0800 -Subject: [PATCH 226/467] UPSTREAM: riscv: dts: spacemit: reorder phy nodes for - K1 - -Reorder the PHY nodes of USB and PCIe to the correct positions based on -the register address. This improves the readability and maintainability -of the DT. No functional change is introduced by this reordering. - -Signed-off-by: Chukun Pan -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260318100000.3934516-1-amadeus@jmu.edu.cn -Signed-off-by: Yixun Lan -(cherry picked from commit eac600d5cc42b04e799fb65169b8f4060773381b) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 108 +++++++++++++-------------- - 1 file changed, 54 insertions(+), 54 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index d2015201f8e5..f0bad6855c97 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -359,6 +359,60 @@ syscon_rcpu2: system-controller@c0888000 { - #reset-cells = <1>; - }; - -+ usbphy2: phy@c0a30000 { -+ compatible = "spacemit,k1-usb2-phy"; -+ reg = <0x0 0xc0a30000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_USB30>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ combo_phy: phy@c0b10000 { -+ compatible = "spacemit,k1-combo-phy"; -+ reg = <0x0 0xc0b10000 0x0 0x1000>; -+ clocks = <&vctcxo_24m>, -+ <&syscon_apmu CLK_PCIE0_DBI>, -+ <&syscon_apmu CLK_PCIE0_MASTER>, -+ <&syscon_apmu CLK_PCIE0_SLAVE>; -+ clock-names = "refclk", -+ "dbi", -+ "mstr", -+ "slv"; -+ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, -+ <&syscon_apmu RESET_PCIE0_DBI>, -+ <&syscon_apmu RESET_PCIE0_MASTER>, -+ <&syscon_apmu RESET_PCIE0_SLAVE>; -+ reset-names = "phy", -+ "dbi", -+ "mstr", -+ "slv"; -+ #phy-cells = <1>; -+ spacemit,apmu = <&syscon_apmu>; -+ status = "disabled"; -+ }; -+ -+ pcie1_phy: phy@c0c10000 { -+ compatible = "spacemit,k1-pcie-phy"; -+ reg = <0x0 0xc0c10000 0x0 0x1000>; -+ clocks = <&vctcxo_24m>; -+ clock-names = "refclk"; -+ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; -+ reset-names = "phy"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ pcie2_phy: phy@c0d10000 { -+ compatible = "spacemit,k1-pcie-phy"; -+ reg = <0x0 0xc0d10000 0x0 0x1000>; -+ clocks = <&vctcxo_24m>; -+ clock-names = "refclk"; -+ resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; -+ reset-names = "phy"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - i2c0: i2c@d4010800 { - compatible = "spacemit,k1-i2c"; - reg = <0x0 0xd4010800 0x0 0x38>; -@@ -429,60 +483,6 @@ i2c5: i2c@d4013800 { - status = "disabled"; - }; - -- usbphy2: phy@c0a30000 { -- compatible = "spacemit,k1-usb2-phy"; -- reg = <0x0 0xc0a30000 0x0 0x200>; -- clocks = <&syscon_apmu CLK_USB30>; -- #phy-cells = <0>; -- status = "disabled"; -- }; -- -- combo_phy: phy@c0b10000 { -- compatible = "spacemit,k1-combo-phy"; -- reg = <0x0 0xc0b10000 0x0 0x1000>; -- clocks = <&vctcxo_24m>, -- <&syscon_apmu CLK_PCIE0_DBI>, -- <&syscon_apmu CLK_PCIE0_MASTER>, -- <&syscon_apmu CLK_PCIE0_SLAVE>; -- clock-names = "refclk", -- "dbi", -- "mstr", -- "slv"; -- resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, -- <&syscon_apmu RESET_PCIE0_DBI>, -- <&syscon_apmu RESET_PCIE0_MASTER>, -- <&syscon_apmu RESET_PCIE0_SLAVE>; -- reset-names = "phy", -- "dbi", -- "mstr", -- "slv"; -- #phy-cells = <1>; -- spacemit,apmu = <&syscon_apmu>; -- status = "disabled"; -- }; -- -- pcie1_phy: phy@c0c10000 { -- compatible = "spacemit,k1-pcie-phy"; -- reg = <0x0 0xc0c10000 0x0 0x1000>; -- clocks = <&vctcxo_24m>; -- clock-names = "refclk"; -- resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; -- reset-names = "phy"; -- #phy-cells = <0>; -- status = "disabled"; -- }; -- -- pcie2_phy: phy@c0d10000 { -- compatible = "spacemit,k1-pcie-phy"; -- reg = <0x0 0xc0d10000 0x0 0x1000>; -- clocks = <&vctcxo_24m>; -- clock-names = "refclk"; -- resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; -- reset-names = "phy"; -- #phy-cells = <0>; -- status = "disabled"; -- }; -- - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k1-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch b/SPECS/linux-lts-kmhv2/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch new file mode 100644 index 0000000000..d1757910da --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch @@ -0,0 +1,61 @@ +From fd0cc30ddc8df5ecd44ae759b0d7ba0d8b5140c5 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 26 Mar 2026 19:35:30 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add 24c04 eeprom on + Milk-V Jupiter + +The Milk-V Jupiter board includes a 24c04 eeprom on the i2c2 bus. The +eeprom contains an ONIE TLV table, which on the board I tested only +provides a product-name entry. Expose it via an onie,tlv-layout nvmem +layout. + +The eeprom is marked as read-only since its contents are not supposed to +be modified. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326183745.1370642-3-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 77156216f1d0f57e1cfce3452410db20468edca4) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 3cd83c5924e4..bd48208a370c 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -108,6 +108,28 @@ &pdma { + status = "okay"; + }; + ++&i2c2 { ++ pinctrl-0 = <&i2c2_0_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ eeprom@50 { ++ compatible = "atmel,24c04"; ++ reg = <0x50>; ++ vcc-supply = <&buck3_1v8>; /* EEPROM_VCC18 */ ++ pagesize = <16>; ++ read-only; ++ size = <512>; ++ ++ nvmem-layout { ++ compatible = "onie,tlv-layout"; ++ ++ product-name { ++ }; ++ }; ++ }; ++}; ++ + &i2c8 { + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0227-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch b/SPECS/linux-lts-kmhv2/0227-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch deleted file mode 100644 index d629f7d904..0000000000 --- a/SPECS/linux-lts-kmhv2/0227-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 16fa682f25aa8efc5b297d6efcaaf5d684c6fd7b Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Sun, 22 Mar 2026 21:25:01 +0100 -Subject: [PATCH 227/467] UPSTREAM: riscv: dts: spacemit: drop incorrect - pinctrl for combo PHY - -The combo PHY on the Banana Pi F3 is used for the USB 3.0 port. The high -speed differential lanes are always configured as such, and do not -require a pinctrl entry. - -The existing pinctrl entry only configures PCIe secondary pins, which -are unused for USB and instead routed to the MIPI CSI1 connector. - -Remove this incorrect pinctrl entry. - -Fixes: 0be016a4b5d1b9 ("riscv: dts: spacemit: PCIe and PHY-related updates") -Signed-off-by: Aurelien Jarno -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260322202502.2205755-1-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit c68360c0d636dae71f766b7b296ddfcf2827ccc7) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 404b69c47b91..5790d927b93d 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -81,8 +81,6 @@ usb3_hub_5v: regulator-usb3-hub-5v { - }; - - &combo_phy { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_3_cfg>; - status = "okay"; - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0228-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch b/SPECS/linux-lts-kmhv2/0228-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch deleted file mode 100644 index aca0bf2ca8..0000000000 --- a/SPECS/linux-lts-kmhv2/0228-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 03c170ac39ef66094f9171ed83e48fcf67edc777 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Thu, 26 Mar 2026 09:46:17 +0800 -Subject: [PATCH 228/467] UPSTREAM: riscv: dts: spacemit: Add ethernet device - for K3 - -Add all ethernet device nodes for K3 SoC. - -Signed-off-by: Inochi Amaoto -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326014617.1011732-1-inochiama@gmail.com -Signed-off-by: Yixun Lan -(cherry picked from commit 74657a376960252e248089e518cfaaf813906989) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 20 ++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 34 ++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 117 +++++++++++++++++++ - 3 files changed, 171 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index b098dbd0e7a1..504fe6bd46b2 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -3,6 +3,7 @@ - * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd - * Copyright (c) 2026 Guodong Xu - */ -+#include - - #include "k3.dtsi" - #include "k3-pinctrl.dtsi" -@@ -12,6 +13,7 @@ / { - compatible = "spacemit,k3-pico-itx", "spacemit,k3"; - - aliases { -+ ethernet0 = ð0; - serial0 = &uart0; - }; - -@@ -25,6 +27,24 @@ memory@100000000 { - }; - }; - -+ð0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <&phy0>; -+ status = "okay"; -+ -+ mdio { -+ phy0: phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <10000>; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_0_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index efb0f1572188..a7b5d10c332e 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -11,6 +11,40 @@ - #define K3_GPIO(x) (x / 32) (x % 32) - - &pinctrl { -+ gmac0_rgmii_0_cfg: gmac0-rgmii-0-cfg { -+ gmac0-rgmii-0-pins { -+ pinmux = , /* gmac0_rxdv */ -+ , /* gmac0_rx_d0 */ -+ , /* gmac0_rx_d1 */ -+ , /* gmac0_rx_clk */ -+ , /* gmac0_rx_d2 */ -+ , /* gmac0_rx_d3 */ -+ , /* gmac0_tx_d0 */ -+ , /* gmac0_tx_d1 */ -+ , /* gmac0_tx_clk */ -+ , /* gmac0_tx_d2 */ -+ , /* gmac0_tx_d3 */ -+ , /* gmac0_tx_en */ -+ , /* gmac0_mdc */ -+ ; /* gmac0_mdio */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ power-source = <1800>; -+ }; -+ -+ }; -+ -+ gmac0_phy_0_cfg: gmac0-phy-0-cfg { -+ gmac0-phy-0-pins { -+ pinmux = ; /* gmac0_int */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ power-source = <1800>; -+ }; -+ }; -+ - /omit-if-no-ref/ - uart0_0_cfg: uart0-0-cfg { - uart0-0-pins { -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index a3a8ceddabec..5f4818cd5d6d 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -438,6 +438,123 @@ soc: soc { - dma-noncoherent; - ranges; - -+ eth0: ethernet@cac80000 { -+ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; -+ reg = <0x0 0xcac80000 0x0 0x2000>; -+ clocks = <&syscon_apmu CLK_APMU_EMAC0_BUS>, -+ <&syscon_apmu CLK_APMU_EMAC0_1588>, -+ <&syscon_apmu CLK_APMU_EMAC0_RGMII_TX>; -+ clock-names = "stmmaceth", "ptp_ref", "tx"; -+ interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, -+ <276 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "macirq", "eth_wake_irq"; -+ resets = <&syscon_apmu RESET_APMU_EMAC0>; -+ reset-names = "stmmaceth"; -+ rx-fifo-depth = <8192>; -+ tx-fifo-depth = <8192>; -+ snps,multicast-filter-bins = <64>; -+ snps,perfect-filter-entries = <32>; -+ snps,aal; -+ snps,tso; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ snps,force_sf_dma_mode; -+ snps,axi-config = <&gmac0_axi_setup>; -+ spacemit,apmu = <&syscon_apmu 0x3e4 0x3e8>; -+ status = "disabled"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ gmac0_axi_setup: stmmac-axi-config { -+ snps,wr_osr_lmt = <0xf>; -+ snps,rd_osr_lmt = <0xf>; -+ /* max axi burst len is 256 */ -+ snps,blen = <256 128 64 32 16 0 0>; -+ }; -+ }; -+ -+ eth1: ethernet@cac82000 { -+ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; -+ reg = <0x0 0xcac82000 0x0 0x2000>; -+ clocks = <&syscon_apmu CLK_APMU_EMAC1_BUS>, -+ <&syscon_apmu CLK_APMU_EMAC1_1588>, -+ <&syscon_apmu CLK_APMU_EMAC1_RGMII_TX>; -+ clock-names = "stmmaceth", "ptp_ref", "tx"; -+ interrupts = <133 IRQ_TYPE_LEVEL_HIGH>, -+ <277 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "macirq", "eth_wake_irq"; -+ resets = <&syscon_apmu RESET_APMU_EMAC1>; -+ reset-names = "stmmaceth"; -+ rx-fifo-depth = <8192>; -+ tx-fifo-depth = <8192>; -+ snps,multicast-filter-bins = <64>; -+ snps,perfect-filter-entries = <32>; -+ snps,aal; -+ snps,tso; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ snps,force_sf_dma_mode; -+ snps,axi-config = <&gmac1_axi_setup>; -+ spacemit,apmu = <&syscon_apmu 0x3ec 0x3f0>; -+ status = "disabled"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ gmac1_axi_setup: stmmac-axi-config { -+ snps,wr_osr_lmt = <0xf>; -+ snps,rd_osr_lmt = <0xf>; -+ /* max axi burst len is 256 */ -+ snps,blen = <256 128 64 32 16 0 0>; -+ }; -+ }; -+ -+ eth2: ethernet@cac8e000 { -+ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; -+ reg = <0x0 0xcac8e000 0x0 0x2000>; -+ clocks = <&syscon_apmu CLK_APMU_EMAC2_BUS>, -+ <&syscon_apmu CLK_APMU_EMAC2_1588>, -+ <&syscon_apmu CLK_APMU_EMAC2_RGMII_TX>; -+ clock-names = "stmmaceth", "ptp_ref", "tx"; -+ interrupts = <130 IRQ_TYPE_LEVEL_HIGH>, -+ <278 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "macirq", "eth_wake_irq"; -+ resets = <&syscon_apmu RESET_APMU_EMAC2>; -+ reset-names = "stmmaceth"; -+ rx-fifo-depth = <4096>; -+ tx-fifo-depth = <4096>; -+ snps,multicast-filter-bins = <64>; -+ snps,perfect-filter-entries = <32>; -+ snps,aal; -+ snps,tso; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ snps,force_sf_dma_mode; -+ snps,axi-config = <&gmac2_axi_setup>; -+ spacemit,apmu = <&syscon_apmu 0x248 0x24c>; -+ status = "disabled"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ gmac2_axi_setup: stmmac-axi-config { -+ snps,wr_osr_lmt = <0xf>; -+ snps,rd_osr_lmt = <0xf>; -+ /* max axi burst len is 256 */ -+ snps,blen = <256 128 64 32 16 0 0>; -+ }; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k3-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch b/SPECS/linux-lts-kmhv2/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch new file mode 100644 index 0000000000..d6371cd157 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch @@ -0,0 +1,37 @@ +From 82fab0710b5af85d582db37f1628e0efe0783003 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 26 Mar 2026 19:35:31 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add i2c aliases on + Milk-V Jupiter + +Add i2c aliases for i2c2 and i2c8 on Milk-V Jupiter. This is useful to +keep a stable number for the /dev entries after loading the i2c-dev +module. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326183745.1370642-4-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 7af5edec73d5d69618541f91600adeb6f35b7d17) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index bd48208a370c..836311c3f035 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -15,6 +15,8 @@ aliases { + ethernet0 = ð0; + ethernet1 = ð1; + serial0 = &uart0; ++ i2c2 = &i2c2; ++ i2c8 = &i2c8; + }; + + chosen { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0229-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch b/SPECS/linux-lts-kmhv2/0229-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch deleted file mode 100644 index 7a250b9fd2..0000000000 --- a/SPECS/linux-lts-kmhv2/0229-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch +++ /dev/null @@ -1,60 +0,0 @@ -From f028688afe776c5820cff9effa08a9558b3e27e7 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Thu, 26 Mar 2026 19:35:29 +0100 -Subject: [PATCH 229/467] UPSTREAM: riscv: dts: spacemit: add LEDs for Milk-V - Jupiter board - -The Milk-V Jupiter board provides support for two LEDs through the front -panel header. The "Power LED" indicates the system is running, and the -"HDD LED" shows disk activity. Configure the corresponding LED triggers -accordingly. - -Caveats: -- The LEDs are driven through a 4.7k series resistor, making them - quite faint. -- The disk activity trigger requires a storage controller on the M.2 or - PCIe interface. That said, it matches the purpose and the vendor - kernel. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326183745.1370642-2-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit 334e64abacd3df4005de80b082d0dbf02b453c76) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 9959c8023ece..3cd83c5924e4 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -21,6 +21,23 @@ chosen { - stdout-path = "serial0"; - }; - -+ leds { -+ compatible = "gpio-leds"; -+ -+ led1 { -+ label = "pwr-led"; -+ gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "default-on"; -+ default-state = "on"; -+ }; -+ -+ led2 { -+ label = "hdd-led"; -+ gpios = <&gpio K1_GPIO(92) GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "disk-activity"; -+ }; -+ }; -+ - reg_dc_in: regulator-dc-in-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_in_12v"; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch b/SPECS/linux-lts-kmhv2/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch new file mode 100644 index 0000000000..7da7a14692 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch @@ -0,0 +1,95 @@ +From 8cd168c0e1c6761c9dc36dba489883961c115b69 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 26 Mar 2026 19:35:32 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable QSPI and add SPI + NOR on Milk-V Jupiter + +Add the QSPI controller node for the Milk-V Jupiter board and describe +the attached SPI NOR flash (GD25Q64E). + +The flash supports a frequency up to 133MHz (80 MHz for reads), and the +SoC supports a frequency up to 104 MHz. However tests have shown that +the flash is not reliably detected above 26.5 MHz, consistent with +frequency used in the vendor kernel. Therefore, use this frequency. + +The m25p,fast-read properties is taken from the vendor kernel, and the +GD25Q64E datasheet confirms tha the fast read opcodes are supported. + +Add a corresponding flash partition layout, matching the layout and the +names used in the vendor U-Boot. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326183745.1370642-5-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 2829823956f0f590f5c6b4eafed2dab7a96f69b3) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 43 ++++++++++++++++++- + 1 file changed, 42 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 836311c3f035..bac6438c6753 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -173,7 +173,7 @@ buck3_1v8: buck3 { + regulator-always-on; + }; + +- buck4 { ++ buck4_3v3: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; +@@ -256,6 +256,47 @@ dldo7 { + }; + }; + ++&qspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi_cfg>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <26500000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; ++ vcc-supply = <&buck4_3v3>; /* QSPI_VCC1833 */ ++ m25p,fast-read; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bootinfo@0 { ++ reg = <0x0 0x10000>; ++ }; ++ private@10000 { ++ reg = <0x10000 0x10000>; ++ }; ++ fsbl@20000 { ++ reg = <0x20000 0x40000>; ++ }; ++ env@60000 { ++ reg = <0x60000 0x10000>; ++ }; ++ opensbi@70000 { ++ reg = <0x70000 0x30000>; ++ }; ++ uboot@a00000 { ++ reg = <0xa0000 0x760000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0230-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch b/SPECS/linux-lts-kmhv2/0230-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch deleted file mode 100644 index 526c0f8b8d..0000000000 --- a/SPECS/linux-lts-kmhv2/0230-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 33c5fad73ed5d84207033735a7ebe3c7f3a3401b Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Thu, 26 Mar 2026 19:35:30 +0100 -Subject: [PATCH 230/467] UPSTREAM: riscv: dts: spacemit: add 24c04 eeprom on - Milk-V Jupiter - -The Milk-V Jupiter board includes a 24c04 eeprom on the i2c2 bus. The -eeprom contains an ONIE TLV table, which on the board I tested only -provides a product-name entry. Expose it via an onie,tlv-layout nvmem -layout. - -The eeprom is marked as read-only since its contents are not supposed to -be modified. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326183745.1370642-3-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit 77156216f1d0f57e1cfce3452410db20468edca4) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 22 +++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 3cd83c5924e4..bd48208a370c 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -108,6 +108,28 @@ &pdma { - status = "okay"; - }; - -+&i2c2 { -+ pinctrl-0 = <&i2c2_0_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ eeprom@50 { -+ compatible = "atmel,24c04"; -+ reg = <0x50>; -+ vcc-supply = <&buck3_1v8>; /* EEPROM_VCC18 */ -+ pagesize = <16>; -+ read-only; -+ size = <512>; -+ -+ nvmem-layout { -+ compatible = "onie,tlv-layout"; -+ -+ product-name { -+ }; -+ }; -+ }; -+}; -+ - &i2c8 { - pinctrl-0 = <&i2c8_cfg>; - pinctrl-names = "default"; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch b/SPECS/linux-lts-kmhv2/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch new file mode 100644 index 0000000000..ab6defa852 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch @@ -0,0 +1,112 @@ +From 7c97859e0dc8e3a13976fbd8fa3512d2a6469e32 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 26 Mar 2026 19:35:33 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable USB 3 ports on + Milk-V Jupiter + +Enable the DWC3 USB 3.0 controller (USB#2 port in the K1 datasheet) and +its associated combo_phy (USB 3 PHY) and usbphy2 (USB 2 PHY) on the +Milk-V Jupiter board. + +The board uses a VLI VL817 hub, providing four ports. Two are routed to +the 3.0 type-A connectors, and two to the F_USB3 front USB header. The +hub requires two separate 5V power supplies: one for the hub itself and +one for the USB connectors. Add an always-on regulator sourcing 5V from +the DC-IN input, along with two GPIO-controlled fixed regulators to +manage the hub and connectors power supplies. + +Note that the board also provides four USB 2.0 ports (two via type-A +connectors and two via the F_USB2 front USB header), but these are +handled by a different controller (USB#1 port in the K1 datasheet). + +Signed-off-by: Aurelien Jarno +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326183745.1370642-6-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit dce01d8585a22f708b5f1eb621cacd9878258ac8) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 62 +++++++++++++++++++ + 1 file changed, 62 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index bac6438c6753..8eeaf2631b71 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -58,6 +58,41 @@ reg_vcc_4v: regulator-vcc-4v { + regulator-always-on; + vin-supply = <®_dc_in>; + }; ++ ++ reg_vcc_5v: regulator-vcc-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <®_dc_in>; ++ }; ++ ++ regulator-usb3-vbus-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB30_VBUS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ vin-supply = <®_vcc_5v>; ++ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ usb3_hub_5v: regulator-usb3-hub-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB30_HUB"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <®_vcc_5v>; ++ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++}; ++ ++&combo_phy { ++ status = "okay"; + }; + + ð0 { +@@ -302,3 +337,30 @@ &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub_2_0: hub@1 { ++ compatible = "usb2109,2817"; ++ reg = <0x1>; ++ vdd-supply = <&usb3_hub_5v>; ++ peer-hub = <&hub_3_0>; ++ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; ++ }; ++ ++ hub_3_0: hub@2 { ++ compatible = "usb2109,817"; ++ reg = <0x2>; ++ vdd-supply = <&usb3_hub_5v>; ++ peer-hub = <&hub_2_0>; ++ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0231-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch b/SPECS/linux-lts-kmhv2/0231-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch deleted file mode 100644 index bf9e8fcaf8..0000000000 --- a/SPECS/linux-lts-kmhv2/0231-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 91f109859aa003662be934a38045864d35c9ba4b Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Thu, 26 Mar 2026 19:35:31 +0100 -Subject: [PATCH 231/467] UPSTREAM: riscv: dts: spacemit: add i2c aliases on - Milk-V Jupiter - -Add i2c aliases for i2c2 and i2c8 on Milk-V Jupiter. This is useful to -keep a stable number for the /dev entries after loading the i2c-dev -module. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326183745.1370642-4-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit 7af5edec73d5d69618541f91600adeb6f35b7d17) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index bd48208a370c..836311c3f035 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -15,6 +15,8 @@ aliases { - ethernet0 = ð0; - ethernet1 = ð1; - serial0 = &uart0; -+ i2c2 = &i2c2; -+ i2c8 = &i2c8; - }; - - chosen { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch b/SPECS/linux-lts-kmhv2/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch new file mode 100644 index 0000000000..37c7e74275 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch @@ -0,0 +1,86 @@ +From a6af60e5b4b61218cbfe45507b2a9c0740b13741 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 26 Mar 2026 19:35:34 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable PCIe ports on + Milk-V Jupiter + +Enable the two PCIe controller along with and their associated PHY. They +are routed to the M.2 M-key connector and to the PCIe x8 slot. + +Add an always-on regulator sourcing 3.3V from the DC-IN input, to power +the PCIe ports. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326183745.1370642-7-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 2b8bd26bbfcdeb1a06127dcd8f9101080133f2a1) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 42 +++++++++++++++++++ + 1 file changed, 42 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 8eeaf2631b71..afaad59e6bce 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -40,6 +40,16 @@ led2 { + }; + }; + ++ pcie_vcc_3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie_vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <®_dc_in>; ++ }; ++ + reg_dc_in: regulator-dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; +@@ -291,6 +301,38 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++}; ++ ++&pcie1 { ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++}; ++ ++&pcie2 { ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++ status = "okay"; ++}; ++ + &qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch b/SPECS/linux-lts-kmhv2/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch new file mode 100644 index 0000000000..636cc98729 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch @@ -0,0 +1,39 @@ +From ffb258a6f70ad79ca6c7b0a4c04cd38fbdd33471 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 25 Mar 2026 09:49:24 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: i2c: spacemit: k3: Add compatible + +Add a compatible string for the I2C controller found in SpacemiT K3 SoC +which use same I2C IP as K1, so make it fallback to K1 compatible. + +Signed-off-by: Yixun Lan +Acked-by: Conor Dooley +Reviewed-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260325-02-k3-i2c-v1-1-78f29c83d9ac@kernel.org +Signed-off-by: Andi Shyti +(cherry picked from commit 4f1e5c967231fefcd04290396724d519961ecffb) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml +index 5896fb120501..8c04c675b25e 100644 +--- a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml ++++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml +@@ -14,7 +14,11 @@ allOf: + + properties: + compatible: +- const: spacemit,k1-i2c ++ oneOf: ++ - items: ++ - const: spacemit,k3-i2c ++ - const: spacemit,k1-i2c ++ - const: spacemit,k1-i2c + + reg: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0232-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch b/SPECS/linux-lts-kmhv2/0232-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch deleted file mode 100644 index f3c36b8033..0000000000 --- a/SPECS/linux-lts-kmhv2/0232-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch +++ /dev/null @@ -1,95 +0,0 @@ -From da2e8b5f724f182ad77cb1d9607a06367e832eb8 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Thu, 26 Mar 2026 19:35:32 +0100 -Subject: [PATCH 232/467] UPSTREAM: riscv: dts: spacemit: enable QSPI and add - SPI NOR on Milk-V Jupiter - -Add the QSPI controller node for the Milk-V Jupiter board and describe -the attached SPI NOR flash (GD25Q64E). - -The flash supports a frequency up to 133MHz (80 MHz for reads), and the -SoC supports a frequency up to 104 MHz. However tests have shown that -the flash is not reliably detected above 26.5 MHz, consistent with -frequency used in the vendor kernel. Therefore, use this frequency. - -The m25p,fast-read properties is taken from the vendor kernel, and the -GD25Q64E datasheet confirms tha the fast read opcodes are supported. - -Add a corresponding flash partition layout, matching the layout and the -names used in the vendor U-Boot. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326183745.1370642-5-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit 2829823956f0f590f5c6b4eafed2dab7a96f69b3) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 43 ++++++++++++++++++- - 1 file changed, 42 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 836311c3f035..bac6438c6753 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -173,7 +173,7 @@ buck3_1v8: buck3 { - regulator-always-on; - }; - -- buck4 { -+ buck4_3v3: buck4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <5000>; -@@ -256,6 +256,47 @@ dldo7 { - }; - }; - -+&qspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qspi_cfg>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <26500000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ vcc-supply = <&buck4_3v3>; /* QSPI_VCC1833 */ -+ m25p,fast-read; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ bootinfo@0 { -+ reg = <0x0 0x10000>; -+ }; -+ private@10000 { -+ reg = <0x10000 0x10000>; -+ }; -+ fsbl@20000 { -+ reg = <0x20000 0x40000>; -+ }; -+ env@60000 { -+ reg = <0x60000 0x10000>; -+ }; -+ opensbi@70000 { -+ reg = <0x70000 0x30000>; -+ }; -+ uboot@a00000 { -+ reg = <0xa0000 0x760000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch b/SPECS/linux-lts-kmhv2/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch new file mode 100644 index 0000000000..4fa6b0eb20 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch @@ -0,0 +1,154 @@ +From 2e5ff84331e9d469cf732e06694632b4d7f0a64e Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 27 Mar 2026 11:40:40 +0000 +Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: k3: Add i2c nodes + +Populate all I2C devicetree nodes for SpacemiT K3 SoC. The controller of +i2c3 is reserved for secure domain, and not available from Linux. The +controller of i2c7 simply doesn't exist from hardware perspective, as +vendor directly name the i2c controller used for PMIC as i2c8. + +Reviewed-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260327-02-k3-i2c-v2-1-2119c0918868@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit cb322cbffb1e70b4ca1be7955ed19fe486de8295) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 100 +++++++++++++++++++++++++++ + 1 file changed, 100 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 5f4818cd5d6d..815debd16409 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -555,6 +555,76 @@ gmac2_axi_setup: stmmac-axi-config { + }; + }; + ++ i2c0: i2c@d4010800 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd4010800 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI0>, ++ <&syscon_apbc CLK_APBC_TWSI0_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI0>; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@d4011000 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd4011000 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI1>, ++ <&syscon_apbc CLK_APBC_TWSI1_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI1>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@d4012000 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd4012000 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI2>, ++ <&syscon_apbc CLK_APBC_TWSI2_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI2>; ++ status = "disabled"; ++ }; ++ ++ i2c4: i2c@d4012800 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd4012800 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI4>, ++ <&syscon_apbc CLK_APBC_TWSI4_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI4>; ++ status = "disabled"; ++ }; ++ ++ i2c5: i2c@d4013800 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd4013800 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI5>, ++ <&syscon_apbc CLK_APBC_TWSI5_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI5>; ++ status = "disabled"; ++ }; ++ + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; +@@ -681,6 +751,20 @@ uart9: serial@d4017800 { + status = "disabled"; + }; + ++ i2c6: i2c@d4018800 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd4018800 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI6>, ++ <&syscon_apbc CLK_APBC_TWSI6_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI6>; ++ status = "disabled"; ++ }; ++ + gpio: gpio@d4019000 { + compatible = "spacemit,k3-gpio"; + reg = <0x0 0xd4019000 0x0 0x100>; +@@ -699,6 +783,20 @@ gpio: gpio@d4019000 { + <&pinctrl 3 0 96 32>; + }; + ++ i2c8: i2c@d401d800 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd401d800 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI8>, ++ <&syscon_apbc CLK_APBC_TWSI8_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI8>; ++ status = "disabled"; ++ }; ++ + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k3-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x1000>; +@@ -794,6 +892,8 @@ clint: timer@e081c000 { + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + ++ /* sec_i2c3: 0xf0614000, not available from Linux */ ++ + mimsic: interrupt-controller@f1000000 { + compatible = "spacemit,k3-imsics", "riscv,imsics"; + reg = <0x0 0xf1000000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0233-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch b/SPECS/linux-lts-kmhv2/0233-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch deleted file mode 100644 index e1e2fcd5ce..0000000000 --- a/SPECS/linux-lts-kmhv2/0233-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 8618f21bd007f6291498d88d9392d4f15cd10805 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Thu, 26 Mar 2026 19:35:33 +0100 -Subject: [PATCH 233/467] UPSTREAM: riscv: dts: spacemit: enable USB 3 ports on - Milk-V Jupiter - -Enable the DWC3 USB 3.0 controller (USB#2 port in the K1 datasheet) and -its associated combo_phy (USB 3 PHY) and usbphy2 (USB 2 PHY) on the -Milk-V Jupiter board. - -The board uses a VLI VL817 hub, providing four ports. Two are routed to -the 3.0 type-A connectors, and two to the F_USB3 front USB header. The -hub requires two separate 5V power supplies: one for the hub itself and -one for the USB connectors. Add an always-on regulator sourcing 5V from -the DC-IN input, along with two GPIO-controlled fixed regulators to -manage the hub and connectors power supplies. - -Note that the board also provides four USB 2.0 ports (two via type-A -connectors and two via the F_USB2 front USB header), but these are -handled by a different controller (USB#1 port in the K1 datasheet). - -Signed-off-by: Aurelien Jarno -Reviewed-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326183745.1370642-6-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit dce01d8585a22f708b5f1eb621cacd9878258ac8) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 62 +++++++++++++++++++ - 1 file changed, 62 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index bac6438c6753..8eeaf2631b71 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -58,6 +58,41 @@ reg_vcc_4v: regulator-vcc-4v { - regulator-always-on; - vin-supply = <®_dc_in>; - }; -+ -+ reg_vcc_5v: regulator-vcc-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_5v"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <®_dc_in>; -+ }; -+ -+ regulator-usb3-vbus-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "USB30_VBUS"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ vin-supply = <®_vcc_5v>; -+ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ usb3_hub_5v: regulator-usb3-hub-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "USB30_HUB"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <®_vcc_5v>; -+ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+}; -+ -+&combo_phy { -+ status = "okay"; - }; - - ð0 { -@@ -302,3 +337,30 @@ &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ hub_2_0: hub@1 { -+ compatible = "usb2109,2817"; -+ reg = <0x1>; -+ vdd-supply = <&usb3_hub_5v>; -+ peer-hub = <&hub_3_0>; -+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; -+ }; -+ -+ hub_3_0: hub@2 { -+ compatible = "usb2109,817"; -+ reg = <0x2>; -+ vdd-supply = <&usb3_hub_5v>; -+ peer-hub = <&hub_2_0>; -+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch b/SPECS/linux-lts-kmhv2/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch new file mode 100644 index 0000000000..fec47cecd6 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch @@ -0,0 +1,200 @@ +From 7602638398631706b3b851eeb82562691d9fbf20 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 27 Mar 2026 11:51:18 +0000 +Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: k3: add P1 PMIC + regulator tree + +Add the P1 PMIC's regulator topology tree for pico-itx board. + +Link: https://lore.kernel.org/r/20260327-02-k3-i2c-v2-1-9c6b374470c6@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit af62a095eb0c3359d477b55ef72d2afd94c83c8f) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 147 +++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 11 ++ + 2 files changed, 158 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 504fe6bd46b2..4486dc1fe114 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -25,6 +25,153 @@ memory@100000000 { + device_type = "memory"; + reg = <0x1 0x00000000 0x4 0x00000000>; + }; ++ ++ reg_aux_vcc5v: regulator-aux-vcc5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "AUX_VCC5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++}; ++ ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8_cfg>; ++ status = "okay"; ++ ++ p1@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; ++ vin1-supply = <®_aux_vcc5v>; ++ vin2-supply = <®_aux_vcc5v>; ++ vin3-supply = <®_aux_vcc5v>; ++ vin4-supply = <®_aux_vcc5v>; ++ vin5-supply = <®_aux_vcc5v>; ++ vin6-supply = <®_aux_vcc5v>; ++ aldoin-supply = <®_aux_vcc5v>; ++ dldoin1-supply = <&buck4>; ++ dldoin2-supply = <&buck4>; ++ ++ regulators { ++ buck1: buck1 { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2: buck2 { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3: buck3 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4: buck4 { ++ regulator-min-microvolt = <2100000>; ++ regulator-max-microvolt = <2100000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6: buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <500000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1: aldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ aldo2: aldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ aldo3: aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4: aldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo1: dldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo2: dldo2 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo3: dldo3 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo4: dldo4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ }; ++ ++ dldo5: dldo5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo6: dldo6 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo7: dldo7 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ }; ++ }; + }; + + ð0 { +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index a7b5d10c332e..23899d3f308a 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -45,6 +45,17 @@ gmac0-phy-0-pins { + }; + }; + ++ /omit-if-no-ref/ ++ i2c8_cfg: i2c8-cfg { ++ i2c8-pins { ++ pinmux = , /* i2c8 scl */ ++ ; /* i2c8 sda */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0234-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch b/SPECS/linux-lts-kmhv2/0234-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch deleted file mode 100644 index 7bf6a68c5f..0000000000 --- a/SPECS/linux-lts-kmhv2/0234-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 29c798bc348079c4005d8f1237132733e5fefd2a Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Thu, 26 Mar 2026 19:35:34 +0100 -Subject: [PATCH 234/467] UPSTREAM: riscv: dts: spacemit: enable PCIe ports on - Milk-V Jupiter - -Enable the two PCIe controller along with and their associated PHY. They -are routed to the M.2 M-key connector and to the PCIe x8 slot. - -Add an always-on regulator sourcing 3.3V from the DC-IN input, to power -the PCIe ports. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326183745.1370642-7-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit 2b8bd26bbfcdeb1a06127dcd8f9101080133f2a1) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 42 +++++++++++++++++++ - 1 file changed, 42 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 8eeaf2631b71..afaad59e6bce 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -40,6 +40,16 @@ led2 { - }; - }; - -+ pcie_vcc_3v3: regulator-pcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie_vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <®_dc_in>; -+ }; -+ - reg_dc_in: regulator-dc-in-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_in_12v"; -@@ -291,6 +301,38 @@ dldo7 { - }; - }; - -+&pcie1_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_3_cfg>; -+ status = "okay"; -+}; -+ -+&pcie1_port { -+ phys = <&pcie1_phy>; -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+}; -+ -+&pcie1 { -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+ status = "okay"; -+}; -+ -+&pcie2_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_4_cfg>; -+ status = "okay"; -+}; -+ -+&pcie2_port { -+ phys = <&pcie2_phy>; -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+}; -+ -+&pcie2 { -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+ status = "okay"; -+}; -+ - &qspi { - pinctrl-names = "default"; - pinctrl-0 = <&qspi_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0235-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch b/SPECS/linux-lts-kmhv2/0235-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch deleted file mode 100644 index e9b0909fb8..0000000000 --- a/SPECS/linux-lts-kmhv2/0235-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 06a529a2e71c9d5cfdfe39c8829383f4535447af Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 25 Mar 2026 09:49:24 +0000 -Subject: [PATCH 235/467] UPSTREAM: dt-bindings: i2c: spacemit: k3: Add - compatible - -Add a compatible string for the I2C controller found in SpacemiT K3 SoC -which use same I2C IP as K1, so make it fallback to K1 compatible. - -Signed-off-by: Yixun Lan -Acked-by: Conor Dooley -Reviewed-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260325-02-k3-i2c-v1-1-78f29c83d9ac@kernel.org -Signed-off-by: Andi Shyti -(cherry picked from commit 4f1e5c967231fefcd04290396724d519961ecffb) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml -index 5896fb120501..8c04c675b25e 100644 ---- a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml -+++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml -@@ -14,7 +14,11 @@ allOf: - - properties: - compatible: -- const: spacemit,k1-i2c -+ oneOf: -+ - items: -+ - const: spacemit,k3-i2c -+ - const: spacemit,k1-i2c -+ - const: spacemit,k1-i2c - - reg: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch b/SPECS/linux-lts-kmhv2/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch new file mode 100644 index 0000000000..dc246bac07 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch @@ -0,0 +1,50 @@ +From e2f15b90c20c9acc8b6524640ad61e8dd279261b Mon Sep 17 00:00:00 2001 +From: Chen Pei +Date: Tue, 17 Mar 2026 11:48:47 +0800 +Subject: [RUYI PATCH] UPSTREAM: perf symbol: Add RISCV case in get_plt_sizes + +According to RISC-V psABI specification, the PLT (Program Linkage Table) +has the following layout: +- The first PLT entry occupies two 16-byte entries (32 bytes total) +- Subsequent PLT entries take up 16 bytes each + +This aligns with the binutils-gdb implementation which defines the same +PLT sizes for RISC-V architecture. + +Update get_plt_sizes() to set plt_header_size=32 and plt_entry_size=16 +for EM_RISCV, matching the architecture's standard ABI. + +Since AARCH64, LOONGARCH, and RISCV have the same PLT size definition, +they are merged together. + +Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc +Link: https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=bfd/elfnn-riscv.c + +Signed-off-by: Chen Pei +Reviewed-by: Guo Ren +Signed-off-by: Namhyung Kim +(cherry picked from commit 616cd6047cbf736d93808f652086dd10a836005f) +Signed-off-by: Han Gao +--- + tools/perf/util/symbol-elf.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c +index 9602cc51dcc6..dedeb0a25b80 100644 +--- a/tools/perf/util/symbol-elf.c ++++ b/tools/perf/util/symbol-elf.c +@@ -372,10 +372,8 @@ static bool get_plt_sizes(struct dso *dso, GElf_Ehdr *ehdr, GElf_Shdr *shdr_plt, + *plt_entry_size = 12; + return true; + case EM_AARCH64: +- *plt_header_size = 32; +- *plt_entry_size = 16; +- return true; + case EM_LOONGARCH: ++ case EM_RISCV: + *plt_header_size = 32; + *plt_entry_size = 16; + return true; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0236-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch b/SPECS/linux-lts-kmhv2/0236-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch deleted file mode 100644 index bcae7bdbb6..0000000000 --- a/SPECS/linux-lts-kmhv2/0236-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch +++ /dev/null @@ -1,154 +0,0 @@ -From 51e77bd033c67ea1bad41c8dc364dc87af69176a Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 27 Mar 2026 11:40:40 +0000 -Subject: [PATCH 236/467] UPSTREAM: dts: riscv: spacemit: k3: Add i2c nodes - -Populate all I2C devicetree nodes for SpacemiT K3 SoC. The controller of -i2c3 is reserved for secure domain, and not available from Linux. The -controller of i2c7 simply doesn't exist from hardware perspective, as -vendor directly name the i2c controller used for PMIC as i2c8. - -Reviewed-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260327-02-k3-i2c-v2-1-2119c0918868@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit cb322cbffb1e70b4ca1be7955ed19fe486de8295) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 100 +++++++++++++++++++++++++++ - 1 file changed, 100 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 5f4818cd5d6d..815debd16409 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -555,6 +555,76 @@ gmac2_axi_setup: stmmac-axi-config { - }; - }; - -+ i2c0: i2c@d4010800 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd4010800 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI0>, -+ <&syscon_apbc CLK_APBC_TWSI0_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI0>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@d4011000 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd4011000 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI1>, -+ <&syscon_apbc CLK_APBC_TWSI1_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI1>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@d4012000 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd4012000 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI2>, -+ <&syscon_apbc CLK_APBC_TWSI2_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI2>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@d4012800 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd4012800 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI4>, -+ <&syscon_apbc CLK_APBC_TWSI4_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI4>; -+ status = "disabled"; -+ }; -+ -+ i2c5: i2c@d4013800 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd4013800 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI5>, -+ <&syscon_apbc CLK_APBC_TWSI5_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI5>; -+ status = "disabled"; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k3-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; -@@ -681,6 +751,20 @@ uart9: serial@d4017800 { - status = "disabled"; - }; - -+ i2c6: i2c@d4018800 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd4018800 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI6>, -+ <&syscon_apbc CLK_APBC_TWSI6_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI6>; -+ status = "disabled"; -+ }; -+ - gpio: gpio@d4019000 { - compatible = "spacemit,k3-gpio"; - reg = <0x0 0xd4019000 0x0 0x100>; -@@ -699,6 +783,20 @@ gpio: gpio@d4019000 { - <&pinctrl 3 0 96 32>; - }; - -+ i2c8: i2c@d401d800 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd401d800 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI8>, -+ <&syscon_apbc CLK_APBC_TWSI8_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI8>; -+ status = "disabled"; -+ }; -+ - pinctrl: pinctrl@d401e000 { - compatible = "spacemit,k3-pinctrl"; - reg = <0x0 0xd401e000 0x0 0x1000>; -@@ -794,6 +892,8 @@ clint: timer@e081c000 { - <&cpu7_intc 3>, <&cpu7_intc 7>; - }; - -+ /* sec_i2c3: 0xf0614000, not available from Linux */ -+ - mimsic: interrupt-controller@f1000000 { - compatible = "spacemit,k3-imsics", "riscv,imsics"; - reg = <0x0 0xf1000000 0x0 0x10000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch b/SPECS/linux-lts-kmhv2/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch new file mode 100644 index 0000000000..4135dc8422 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch @@ -0,0 +1,51 @@ +From 88b461165ff138a8bc16b7a3d1540a19c8a3710e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= +Date: Sat, 4 Apr 2026 18:42:40 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: Simplify assignment for UTS_MACHINE +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The BITS variable conveniently allows to simplify the assignment for +UTS_MACHINE. + +Signed-off-by: Uwe Kleine-König (The Capable Hub) +Link: https://patch.msgid.link/20260313164012.1153936-2-u.kleine-koenig@baylibre.com +Signed-off-by: Paul Walmsley +(cherry picked from commit c8d0c36d852ccd7caf9d5a44f3090f80a060c28d) +Signed-off-by: Han Gao +--- + arch/riscv/Makefile | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 4c6de57f65ef..775b5faa4b2e 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -28,7 +28,6 @@ endif + export BITS + ifeq ($(CONFIG_ARCH_RV64I),y) + BITS := 64 +- UTS_MACHINE := riscv64 + + KBUILD_CFLAGS += -mabi=lp64 + KBUILD_AFLAGS += -mabi=lp64 +@@ -39,13 +38,14 @@ ifeq ($(CONFIG_ARCH_RV64I),y) + -Cno-redzone + else + BITS := 32 +- UTS_MACHINE := riscv32 + + KBUILD_CFLAGS += -mabi=ilp32 + KBUILD_AFLAGS += -mabi=ilp32 + KBUILD_LDFLAGS += -melf32lriscv + endif + ++UTS_MACHINE := riscv$(BITS) ++ + # LLVM has an issue with target-features and LTO: https://github.com/llvm/llvm-project/issues/59350 + # Ensure it is aware of linker relaxation with LTO, otherwise relocations may + # be incorrect: https://github.com/llvm/llvm-project/issues/65090 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0237-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch b/SPECS/linux-lts-kmhv2/0237-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch deleted file mode 100644 index 2dbc249507..0000000000 --- a/SPECS/linux-lts-kmhv2/0237-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch +++ /dev/null @@ -1,200 +0,0 @@ -From 3d90cd2fe817a9d87061b1aaf12ab04d512bb830 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 27 Mar 2026 11:51:18 +0000 -Subject: [PATCH 237/467] UPSTREAM: dts: riscv: spacemit: k3: add P1 PMIC - regulator tree - -Add the P1 PMIC's regulator topology tree for pico-itx board. - -Link: https://lore.kernel.org/r/20260327-02-k3-i2c-v2-1-9c6b374470c6@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit af62a095eb0c3359d477b55ef72d2afd94c83c8f) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 147 +++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 11 ++ - 2 files changed, 158 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index 504fe6bd46b2..4486dc1fe114 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -25,6 +25,153 @@ memory@100000000 { - device_type = "memory"; - reg = <0x1 0x00000000 0x4 0x00000000>; - }; -+ -+ reg_aux_vcc5v: regulator-aux-vcc5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "AUX_VCC5V"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+}; -+ -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+ -+ p1@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; -+ vin1-supply = <®_aux_vcc5v>; -+ vin2-supply = <®_aux_vcc5v>; -+ vin3-supply = <®_aux_vcc5v>; -+ vin4-supply = <®_aux_vcc5v>; -+ vin5-supply = <®_aux_vcc5v>; -+ vin6-supply = <®_aux_vcc5v>; -+ aldoin-supply = <®_aux_vcc5v>; -+ dldoin1-supply = <&buck4>; -+ dldoin2-supply = <&buck4>; -+ -+ regulators { -+ buck1: buck1 { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2: buck2 { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3: buck3 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4: buck4 { -+ regulator-min-microvolt = <2100000>; -+ regulator-max-microvolt = <2100000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6: buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <500000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1: aldo1 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ aldo2: aldo2 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ aldo3: aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4: aldo4 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo1: dldo1 { -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo2: dldo2 { -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo3: dldo3 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo4: dldo4 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ }; -+ -+ dldo5: dldo5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo6: dldo6 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo7: dldo7 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ }; -+ }; - }; - - ð0 { -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index a7b5d10c332e..23899d3f308a 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -45,6 +45,17 @@ gmac0-phy-0-pins { - }; - }; - -+ /omit-if-no-ref/ -+ i2c8_cfg: i2c8-cfg { -+ i2c8-pins { -+ pinmux = , /* i2c8 scl */ -+ ; /* i2c8 sda */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ - /omit-if-no-ref/ - uart0_0_cfg: uart0-0-cfg { - uart0-0-pins { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch b/SPECS/linux-lts-kmhv2/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch new file mode 100644 index 0000000000..c12445faca --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch @@ -0,0 +1,36 @@ +From f64acae7865de9be5e3490b46bc253b9e0d8464e Mon Sep 17 00:00:00 2001 +From: Austin Kim +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: increase COMMAND_LINE_SIZE value to + 2048 + +SoC people may send many parameters to configure the drivers via kernel +command line. If COMMAND_LINE_SIZE is not enough, they may go through +unexpected error. + +To avoid the potential pain, we had better increase COMMAND_LINE_SIZE. + +Signed-off-by: Austin Kim +Link: https://patch.msgid.link/aW3gFmOlA/Z4kmfJ@adminpc-PowerEdge-R7525 +Signed-off-by: Paul Walmsley +(cherry picked from commit 580e626dd0304b4cafb2a5d21c6f0401b44f0ffb) +Signed-off-by: Han Gao +--- + arch/riscv/include/uapi/asm/setup.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/include/uapi/asm/setup.h b/arch/riscv/include/uapi/asm/setup.h +index 66b13a522880..eb4f0209c696 100644 +--- a/arch/riscv/include/uapi/asm/setup.h ++++ b/arch/riscv/include/uapi/asm/setup.h +@@ -3,6 +3,6 @@ + #ifndef _UAPI_ASM_RISCV_SETUP_H + #define _UAPI_ASM_RISCV_SETUP_H + +-#define COMMAND_LINE_SIZE 1024 ++#define COMMAND_LINE_SIZE 2048 + + #endif /* _UAPI_ASM_RISCV_SETUP_H */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0238-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch b/SPECS/linux-lts-kmhv2/0238-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch deleted file mode 100644 index 050b3605d2..0000000000 --- a/SPECS/linux-lts-kmhv2/0238-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 648a8870dbad32008ba12e159e37944eb9d7180e Mon Sep 17 00:00:00 2001 -From: Chen Pei -Date: Tue, 17 Mar 2026 11:48:47 +0800 -Subject: [PATCH 238/467] UPSTREAM: perf symbol: Add RISCV case in - get_plt_sizes - -According to RISC-V psABI specification, the PLT (Program Linkage Table) -has the following layout: -- The first PLT entry occupies two 16-byte entries (32 bytes total) -- Subsequent PLT entries take up 16 bytes each - -This aligns with the binutils-gdb implementation which defines the same -PLT sizes for RISC-V architecture. - -Update get_plt_sizes() to set plt_header_size=32 and plt_entry_size=16 -for EM_RISCV, matching the architecture's standard ABI. - -Since AARCH64, LOONGARCH, and RISCV have the same PLT size definition, -they are merged together. - -Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc -Link: https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=bfd/elfnn-riscv.c - -Signed-off-by: Chen Pei -Reviewed-by: Guo Ren -Signed-off-by: Namhyung Kim -(cherry picked from commit 616cd6047cbf736d93808f652086dd10a836005f) -Signed-off-by: Han Gao ---- - tools/perf/util/symbol-elf.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - -diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c -index 9602cc51dcc6..dedeb0a25b80 100644 ---- a/tools/perf/util/symbol-elf.c -+++ b/tools/perf/util/symbol-elf.c -@@ -372,10 +372,8 @@ static bool get_plt_sizes(struct dso *dso, GElf_Ehdr *ehdr, GElf_Shdr *shdr_plt, - *plt_entry_size = 12; - return true; - case EM_AARCH64: -- *plt_header_size = 32; -- *plt_entry_size = 16; -- return true; - case EM_LOONGARCH: -+ case EM_RISCV: - *plt_header_size = 32; - *plt_entry_size = 16; - return true; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch b/SPECS/linux-lts-kmhv2/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch new file mode 100644 index 0000000000..53eb710553 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch @@ -0,0 +1,49 @@ +From 50da2d0c20ed5daeac5e56fc3b173a315118dc29 Mon Sep 17 00:00:00 2001 +From: Yufeng Wang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: acpi: update FADT revision check to 6.6 + +ACPI 6.6 is required for RISC-V as it introduces RISC-V specific +tables such as RHCT (RISC-V Hart Capabilities Table) and +RIMT (RISC-V I/O Mapping Table). + +Update the FADT revision check from 6.5 to 6.6 and remove +the TODO comment since ACPI 6.6 has been officially released. + +Signed-off-by: Yufeng Wang +Reviewed-by: Sunil V L +Acked-by: Heinrich Schuchardt +Reviewed-by: Yao Zi +Link: https://patch.msgid.link/20260305091433.83983-1-r4o5m6e8o@163.com +Signed-off-by: Paul Walmsley +(cherry picked from commit dd598449338212f9262424fa67e40b5643ab6c06) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/acpi.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c +index 71698ee11621..ff681db9f4f1 100644 +--- a/arch/riscv/kernel/acpi.c ++++ b/arch/riscv/kernel/acpi.c +@@ -85,12 +85,12 @@ static int __init acpi_fadt_sanity_check(void) + * The revision in the table header is the FADT's Major revision. The + * FADT also has a minor revision, which is stored in the FADT itself. + * +- * TODO: Currently, we check for 6.5 as the minimum version to check +- * for HW_REDUCED flag. However, once RISC-V updates are released in +- * the ACPI spec, we need to update this check for exact minor revision ++ * ACPI 6.6 is required for RISC-V as it introduces RISC-V specific ++ * tables such as RHCT (RISC-V Hart Capabilities Table) and RIMT ++ * (RISC-V I/O Mapping Table). + */ +- if (table->revision < 6 || (table->revision == 6 && fadt->minor_revision < 5)) +- pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 6.5+\n", ++ if (table->revision < 6 || (table->revision == 6 && fadt->minor_revision < 6)) ++ pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 6.6+\n", + table->revision, fadt->minor_revision); + + if (!(fadt->flags & ACPI_FADT_HW_REDUCED)) { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0239-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch b/SPECS/linux-lts-kmhv2/0239-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch deleted file mode 100644 index 9fe6fe1315..0000000000 --- a/SPECS/linux-lts-kmhv2/0239-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch +++ /dev/null @@ -1,51 +0,0 @@ -From f61f4c49f48046edb4ce0352be894de34dfcd5a3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= -Date: Sat, 4 Apr 2026 18:42:40 -0600 -Subject: [PATCH 239/467] UPSTREAM: riscv: Simplify assignment for UTS_MACHINE -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The BITS variable conveniently allows to simplify the assignment for -UTS_MACHINE. - -Signed-off-by: Uwe Kleine-König (The Capable Hub) -Link: https://patch.msgid.link/20260313164012.1153936-2-u.kleine-koenig@baylibre.com -Signed-off-by: Paul Walmsley -(cherry picked from commit c8d0c36d852ccd7caf9d5a44f3090f80a060c28d) -Signed-off-by: Han Gao ---- - arch/riscv/Makefile | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile -index 4c6de57f65ef..775b5faa4b2e 100644 ---- a/arch/riscv/Makefile -+++ b/arch/riscv/Makefile -@@ -28,7 +28,6 @@ endif - export BITS - ifeq ($(CONFIG_ARCH_RV64I),y) - BITS := 64 -- UTS_MACHINE := riscv64 - - KBUILD_CFLAGS += -mabi=lp64 - KBUILD_AFLAGS += -mabi=lp64 -@@ -39,13 +38,14 @@ ifeq ($(CONFIG_ARCH_RV64I),y) - -Cno-redzone - else - BITS := 32 -- UTS_MACHINE := riscv32 - - KBUILD_CFLAGS += -mabi=ilp32 - KBUILD_AFLAGS += -mabi=ilp32 - KBUILD_LDFLAGS += -melf32lriscv - endif - -+UTS_MACHINE := riscv$(BITS) -+ - # LLVM has an issue with target-features and LTO: https://github.com/llvm/llvm-project/issues/59350 - # Ensure it is aware of linker relaxation with LTO, otherwise relocations may - # be incorrect: https://github.com/llvm/llvm-project/issues/65090 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch b/SPECS/linux-lts-kmhv2/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch new file mode 100644 index 0000000000..03b0b8232a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch @@ -0,0 +1,35 @@ +From 527bf47071201cafeeb74ad89ac94e5d61eb3691 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: mm: WARN_ON() for bad addresses in + vmemmap_populate() + +Similarly to the same check in arch/arm64/mm/mmu.c, in +vmemmap_populate(), add a warning for start and end being outside of the +range of vmemmap. + +Signed-off-by: Vivian Wang +Link: https://patch.msgid.link/20260309-riscv-sparsemem-vmemmap-limits-v1-1-f40efe18e3cd@iscas.ac.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit b0217d97eeeaca199eff23102b3fa72ea8c4ddea) +Signed-off-by: Han Gao +--- + arch/riscv/mm/init.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index ee40ca01ac66..8f4e7e505906 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -1486,6 +1486,8 @@ int __meminit vmemmap_check_pmd(pmd_t *pmdp, int node, + int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, + struct vmem_altmap *altmap) + { ++ WARN_ON((start < VMEMMAP_START) || (end > VMEMMAP_END)); ++ + /* + * Note that SPARSEMEM_VMEMMAP is only selected for rv64 and that we + * can't use hugepage mappings for 2-level page table because in case of +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch b/SPECS/linux-lts-kmhv2/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch new file mode 100644 index 0000000000..d8e8ef3623 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch @@ -0,0 +1,50 @@ +From 21223e48716232b52be9719f8d4361bc9f82af59 Mon Sep 17 00:00:00 2001 +From: Yufeng Wang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: enable HAVE_IOREMAP_PROT + +RISC-V has implemented pte_pgprot() and selects GENERIC_IOREMAP, +which provides a generic ioremap_prot() implementation. Enable +HAVE_IOREMAP_PROT to activate generic_access_phys() support, which +is useful for debugging (e.g., accessing /dev/mem via gdb). + +Also update the architecture support documentation accordingly. + +Signed-off-by: Yufeng Wang +Link: https://patch.msgid.link/20260306112734.108186-1-r4o5m6e8o@163.com +Signed-off-by: Paul Walmsley +(cherry picked from commit d1f014012571323f3857873d94c2abf9343ef62d) +Signed-off-by: Han Gao +--- + Documentation/features/vm/ioremap_prot/arch-support.txt | 2 +- + arch/riscv/Kconfig | 1 + + 2 files changed, 2 insertions(+), 1 deletion(-) + +diff --git a/Documentation/features/vm/ioremap_prot/arch-support.txt b/Documentation/features/vm/ioremap_prot/arch-support.txt +index 1638c2cb17f1..c0a2d8f56046 100644 +--- a/Documentation/features/vm/ioremap_prot/arch-support.txt ++++ b/Documentation/features/vm/ioremap_prot/arch-support.txt +@@ -20,7 +20,7 @@ + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | +- | riscv: | TODO | ++ | riscv: | ok | + | s390: | ok | + | sh: | ok | + | sparc: | TODO | +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index fadec20b87a8..9c43346fabcd 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -113,6 +113,7 @@ config RISCV + select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO && 64BIT + select GENERIC_IDLE_POLL_SETUP + select GENERIC_IOREMAP if MMU ++ select HAVE_IOREMAP_PROT if MMU + select GENERIC_IRQ_IPI if SMP + select GENERIC_IRQ_IPI_MUX if SMP + select GENERIC_IRQ_MULTI_HANDLER +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0240-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch b/SPECS/linux-lts-kmhv2/0240-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch deleted file mode 100644 index 35ec7040c2..0000000000 --- a/SPECS/linux-lts-kmhv2/0240-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 3d0d22f6281de4b039180e5e5096041117526be7 Mon Sep 17 00:00:00 2001 -From: Austin Kim -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 240/467] UPSTREAM: riscv: increase COMMAND_LINE_SIZE value to - 2048 - -SoC people may send many parameters to configure the drivers via kernel -command line. If COMMAND_LINE_SIZE is not enough, they may go through -unexpected error. - -To avoid the potential pain, we had better increase COMMAND_LINE_SIZE. - -Signed-off-by: Austin Kim -Link: https://patch.msgid.link/aW3gFmOlA/Z4kmfJ@adminpc-PowerEdge-R7525 -Signed-off-by: Paul Walmsley -(cherry picked from commit 580e626dd0304b4cafb2a5d21c6f0401b44f0ffb) -Signed-off-by: Han Gao ---- - arch/riscv/include/uapi/asm/setup.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/include/uapi/asm/setup.h b/arch/riscv/include/uapi/asm/setup.h -index 66b13a522880..eb4f0209c696 100644 ---- a/arch/riscv/include/uapi/asm/setup.h -+++ b/arch/riscv/include/uapi/asm/setup.h -@@ -3,6 +3,6 @@ - #ifndef _UAPI_ASM_RISCV_SETUP_H - #define _UAPI_ASM_RISCV_SETUP_H - --#define COMMAND_LINE_SIZE 1024 -+#define COMMAND_LINE_SIZE 2048 - - #endif /* _UAPI_ASM_RISCV_SETUP_H */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0241-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch b/SPECS/linux-lts-kmhv2/0241-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch deleted file mode 100644 index 0a4ec4eaf8..0000000000 --- a/SPECS/linux-lts-kmhv2/0241-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch +++ /dev/null @@ -1,50 +0,0 @@ -From 40f9fb3f9445f0a2bab1227aad457b443ce8c21f Mon Sep 17 00:00:00 2001 -From: Yufeng Wang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 241/467] UPSTREAM: riscv: acpi: update FADT revision check to - 6.6 - -ACPI 6.6 is required for RISC-V as it introduces RISC-V specific -tables such as RHCT (RISC-V Hart Capabilities Table) and -RIMT (RISC-V I/O Mapping Table). - -Update the FADT revision check from 6.5 to 6.6 and remove -the TODO comment since ACPI 6.6 has been officially released. - -Signed-off-by: Yufeng Wang -Reviewed-by: Sunil V L -Acked-by: Heinrich Schuchardt -Reviewed-by: Yao Zi -Link: https://patch.msgid.link/20260305091433.83983-1-r4o5m6e8o@163.com -Signed-off-by: Paul Walmsley -(cherry picked from commit dd598449338212f9262424fa67e40b5643ab6c06) -Signed-off-by: Han Gao ---- - arch/riscv/kernel/acpi.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c -index 71698ee11621..ff681db9f4f1 100644 ---- a/arch/riscv/kernel/acpi.c -+++ b/arch/riscv/kernel/acpi.c -@@ -85,12 +85,12 @@ static int __init acpi_fadt_sanity_check(void) - * The revision in the table header is the FADT's Major revision. The - * FADT also has a minor revision, which is stored in the FADT itself. - * -- * TODO: Currently, we check for 6.5 as the minimum version to check -- * for HW_REDUCED flag. However, once RISC-V updates are released in -- * the ACPI spec, we need to update this check for exact minor revision -+ * ACPI 6.6 is required for RISC-V as it introduces RISC-V specific -+ * tables such as RHCT (RISC-V Hart Capabilities Table) and RIMT -+ * (RISC-V I/O Mapping Table). - */ -- if (table->revision < 6 || (table->revision == 6 && fadt->minor_revision < 5)) -- pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 6.5+\n", -+ if (table->revision < 6 || (table->revision == 6 && fadt->minor_revision < 6)) -+ pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 6.6+\n", - table->revision, fadt->minor_revision); - - if (!(fadt->flags & ACPI_FADT_HW_REDUCED)) { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0241-UPSTREAM-string-provide-strends.patch b/SPECS/linux-lts-kmhv2/0241-UPSTREAM-string-provide-strends.patch new file mode 100644 index 0000000000..1647db78f8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0241-UPSTREAM-string-provide-strends.patch @@ -0,0 +1,79 @@ +From 94b2dc80662df98e75c5893573a98c832aa7b104 Mon Sep 17 00:00:00 2001 +From: Bartosz Golaszewski +Date: Wed, 12 Nov 2025 14:55:30 +0100 +Subject: [RUYI PATCH] UPSTREAM: string: provide strends() + +Implement a function for checking if a string ends with a different +string and add its kunit test cases. + +Acked-by: Linus Walleij +Link: https://lore.kernel.org/r/20251112-gpio-shared-v4-1-b51f97b1abd8@linaro.org +Signed-off-by: Bartosz Golaszewski +(cherry picked from commit 197b3f3c70d61ff1c7ca24f66d567e06fe8ed3d9) +Signed-off-by: Han Gao +--- + include/linux/string.h | 18 ++++++++++++++++++ + lib/tests/string_kunit.c | 13 +++++++++++++ + 2 files changed, 31 insertions(+) + +diff --git a/include/linux/string.h b/include/linux/string.h +index fdd3442c6bcb..929d05d1247c 100644 +--- a/include/linux/string.h ++++ b/include/linux/string.h +@@ -562,4 +562,22 @@ static inline bool strstarts(const char *str, const char *prefix) + return strncmp(str, prefix, strlen(prefix)) == 0; + } + ++/** ++ * strends - Check if a string ends with another string. ++ * @str - NULL-terminated string to check against @suffix ++ * @suffix - NULL-terminated string defining the suffix to look for in @str ++ * ++ * Returns: ++ * True if @str ends with @suffix. False in all other cases. ++ */ ++static inline bool strends(const char *str, const char *suffix) ++{ ++ unsigned int str_len = strlen(str), suffix_len = strlen(suffix); ++ ++ if (str_len < suffix_len) ++ return false; ++ ++ return !(strcmp(str + str_len - suffix_len, suffix)); ++} ++ + #endif /* _LINUX_STRING_H_ */ +diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c +index 0ed7448a26d3..f9a8e557ba77 100644 +--- a/lib/tests/string_kunit.c ++++ b/lib/tests/string_kunit.c +@@ -602,6 +602,18 @@ static void string_test_memtostr(struct kunit *test) + KUNIT_EXPECT_EQ(test, dest[7], '\0'); + } + ++static void string_test_strends(struct kunit *test) ++{ ++ KUNIT_EXPECT_TRUE(test, strends("foo-bar", "bar")); ++ KUNIT_EXPECT_TRUE(test, strends("foo-bar", "-bar")); ++ KUNIT_EXPECT_TRUE(test, strends("foobar", "foobar")); ++ KUNIT_EXPECT_TRUE(test, strends("foobar", "")); ++ KUNIT_EXPECT_FALSE(test, strends("bar", "foobar")); ++ KUNIT_EXPECT_FALSE(test, strends("", "foo")); ++ KUNIT_EXPECT_FALSE(test, strends("foobar", "ba")); ++ KUNIT_EXPECT_TRUE(test, strends("", "")); ++} ++ + static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_memset16), + KUNIT_CASE(string_test_memset32), +@@ -623,6 +635,7 @@ static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_strlcat), + KUNIT_CASE(string_test_strtomem), + KUNIT_CASE(string_test_memtostr), ++ KUNIT_CASE(string_test_strends), + {} + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts-kmhv2/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch new file mode 100644 index 0000000000..98ac349bfa --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -0,0 +1,91 @@ +From 79e2cd89898e36fdb3d1714bbd7988fb286c84c7 Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for + strlen() + +Add a KUnit test for strlen() to verify correctness across +different string lengths and memory alignments. Use vmalloc() +to place the NUL character at the page boundary to ensure +over-reads are detected. + +Suggested-by: Kees Cook +Signed-off-by: Feng Jiang +Reviewed-by: Kees Cook +Link: https://patch.msgid.link/20260130025018.172925-2-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit ae45f896a40a07449d9b45d0395fb7245fdd75fc) +Signed-off-by: Han Gao +--- + lib/tests/string_kunit.c | 30 ++++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c +index f9a8e557ba77..26962118768e 100644 +--- a/lib/tests/string_kunit.c ++++ b/lib/tests/string_kunit.c +@@ -6,10 +6,12 @@ + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + + #include ++#include + #include + #include + #include + #include ++#include + + #define STRCMP_LARGE_BUF_LEN 2048 + #define STRCMP_CHANGE_POINT 1337 +@@ -17,6 +19,9 @@ + #define STRCMP_TEST_EXPECT_LOWER(test, fn, ...) KUNIT_EXPECT_LT(test, fn(__VA_ARGS__), 0) + #define STRCMP_TEST_EXPECT_GREATER(test, fn, ...) KUNIT_EXPECT_GT(test, fn(__VA_ARGS__), 0) + ++#define STRING_TEST_MAX_LEN 128 ++#define STRING_TEST_MAX_OFFSET 16 ++ + static void string_test_memset16(struct kunit *test) + { + unsigned i, j, k; +@@ -104,6 +109,30 @@ static void string_test_memset64(struct kunit *test) + } + } + ++static void string_test_strlen(struct kunit *test) ++{ ++ size_t buf_size; ++ char *buf, *s; ++ ++ buf_size = PAGE_ALIGN(STRING_TEST_MAX_LEN + STRING_TEST_MAX_OFFSET + 1); ++ buf = vmalloc(buf_size); ++ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); ++ ++ memset(buf, 'A', buf_size); ++ ++ for (size_t offset = 0; offset < STRING_TEST_MAX_OFFSET; offset++) { ++ for (size_t len = 0; len <= STRING_TEST_MAX_LEN; len++) { ++ s = buf + buf_size - 1 - offset - len; ++ s[len] = '\0'; ++ KUNIT_EXPECT_EQ_MSG(test, strlen(s), len, ++ "offset:%zu len:%zu", offset, len); ++ s[len] = 'A'; ++ } ++ } ++ ++ vfree(buf); ++} ++ + static void string_test_strchr(struct kunit *test) + { + const char *test_string = "abcdefghijkl"; +@@ -618,6 +647,7 @@ static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_memset16), + KUNIT_CASE(string_test_memset32), + KUNIT_CASE(string_test_memset64), ++ KUNIT_CASE(string_test_strlen), + KUNIT_CASE(string_test_strchr), + KUNIT_CASE(string_test_strnchr), + KUNIT_CASE(string_test_strspn), +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0242-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch b/SPECS/linux-lts-kmhv2/0242-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch deleted file mode 100644 index f514478c34..0000000000 --- a/SPECS/linux-lts-kmhv2/0242-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch +++ /dev/null @@ -1,35 +0,0 @@ -From a0fb9210411d1e9cf24e0002bf7eab0d439012ce Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 242/467] UPSTREAM: riscv: mm: WARN_ON() for bad addresses in - vmemmap_populate() - -Similarly to the same check in arch/arm64/mm/mmu.c, in -vmemmap_populate(), add a warning for start and end being outside of the -range of vmemmap. - -Signed-off-by: Vivian Wang -Link: https://patch.msgid.link/20260309-riscv-sparsemem-vmemmap-limits-v1-1-f40efe18e3cd@iscas.ac.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit b0217d97eeeaca199eff23102b3fa72ea8c4ddea) -Signed-off-by: Han Gao ---- - arch/riscv/mm/init.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index d85efe74a4b6..a7d0cde6536b 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -1461,6 +1461,8 @@ int __meminit vmemmap_check_pmd(pmd_t *pmdp, int node, - int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, - struct vmem_altmap *altmap) - { -+ WARN_ON((start < VMEMMAP_START) || (end > VMEMMAP_END)); -+ - /* - * Note that SPARSEMEM_VMEMMAP is only selected for rv64 and that we - * can't use hugepage mappings for 2-level page table because in case of --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts-kmhv2/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch new file mode 100644 index 0000000000..cf2e77deb8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -0,0 +1,79 @@ +From 902bdb8bb0a0f55816f458cf513b52da08e503fb Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for + strnlen() + +Add a KUnit test for strnlen() to verify correctness across +different string lengths and memory alignments. Use vmalloc() +to place the NUL character at the page boundary to ensure +over-reads are detected. + +Suggested-by: Andy Shevchenko +Suggested-by: Kees Cook +Signed-off-by: Feng Jiang +Reviewed-by: Kees Cook +Link: https://patch.msgid.link/20260130025018.172925-3-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit 263dca234e5cc12aa8b434592ceb655538bf4ea4) +Signed-off-by: Han Gao +--- + lib/tests/string_kunit.c | 35 +++++++++++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c +index 26962118768e..1c2d57e05624 100644 +--- a/lib/tests/string_kunit.c ++++ b/lib/tests/string_kunit.c +@@ -133,6 +133,40 @@ static void string_test_strlen(struct kunit *test) + vfree(buf); + } + ++static void string_test_strnlen(struct kunit *test) ++{ ++ size_t buf_size; ++ char *buf, *s; ++ ++ buf_size = PAGE_ALIGN(STRING_TEST_MAX_LEN + STRING_TEST_MAX_OFFSET + 1); ++ buf = vmalloc(buf_size); ++ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); ++ ++ memset(buf, 'A', buf_size); ++ ++ for (size_t offset = 0; offset < STRING_TEST_MAX_OFFSET; offset++) { ++ for (size_t len = 0; len <= STRING_TEST_MAX_LEN; len++) { ++ s = buf + buf_size - 1 - offset - len; ++ s[len] = '\0'; ++ ++ if (len > 0) ++ KUNIT_EXPECT_EQ(test, strnlen(s, len - 1), len - 1); ++ if (len > 1) ++ KUNIT_EXPECT_EQ(test, strnlen(s, len - 2), len - 2); ++ ++ KUNIT_EXPECT_EQ(test, strnlen(s, len), len); ++ ++ KUNIT_EXPECT_EQ(test, strnlen(s, len + 1), len); ++ KUNIT_EXPECT_EQ(test, strnlen(s, len + 2), len); ++ KUNIT_EXPECT_EQ(test, strnlen(s, len + 10), len); ++ ++ s[len] = 'A'; ++ } ++ } ++ ++ vfree(buf); ++} ++ + static void string_test_strchr(struct kunit *test) + { + const char *test_string = "abcdefghijkl"; +@@ -648,6 +682,7 @@ static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_memset32), + KUNIT_CASE(string_test_memset64), + KUNIT_CASE(string_test_strlen), ++ KUNIT_CASE(string_test_strnlen), + KUNIT_CASE(string_test_strchr), + KUNIT_CASE(string_test_strnchr), + KUNIT_CASE(string_test_strspn), +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0243-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch b/SPECS/linux-lts-kmhv2/0243-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch deleted file mode 100644 index f3074ab38b..0000000000 --- a/SPECS/linux-lts-kmhv2/0243-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 91dae5c9d0216f41e065a75837f17dc7e99d545e Mon Sep 17 00:00:00 2001 -From: Yufeng Wang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 243/467] UPSTREAM: riscv: enable HAVE_IOREMAP_PROT - -RISC-V has implemented pte_pgprot() and selects GENERIC_IOREMAP, -which provides a generic ioremap_prot() implementation. Enable -HAVE_IOREMAP_PROT to activate generic_access_phys() support, which -is useful for debugging (e.g., accessing /dev/mem via gdb). - -Also update the architecture support documentation accordingly. - -Signed-off-by: Yufeng Wang -Link: https://patch.msgid.link/20260306112734.108186-1-r4o5m6e8o@163.com -Signed-off-by: Paul Walmsley -(cherry picked from commit d1f014012571323f3857873d94c2abf9343ef62d) -Signed-off-by: Han Gao ---- - Documentation/features/vm/ioremap_prot/arch-support.txt | 2 +- - arch/riscv/Kconfig | 1 + - 2 files changed, 2 insertions(+), 1 deletion(-) - -diff --git a/Documentation/features/vm/ioremap_prot/arch-support.txt b/Documentation/features/vm/ioremap_prot/arch-support.txt -index 1638c2cb17f1..c0a2d8f56046 100644 ---- a/Documentation/features/vm/ioremap_prot/arch-support.txt -+++ b/Documentation/features/vm/ioremap_prot/arch-support.txt -@@ -20,7 +20,7 @@ - | openrisc: | TODO | - | parisc: | TODO | - | powerpc: | ok | -- | riscv: | TODO | -+ | riscv: | ok | - | s390: | ok | - | sh: | ok | - | sparc: | TODO | -diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index fadec20b87a8..9c43346fabcd 100644 ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -113,6 +113,7 @@ config RISCV - select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO && 64BIT - select GENERIC_IDLE_POLL_SETUP - select GENERIC_IOREMAP if MMU -+ select HAVE_IOREMAP_PROT if MMU - select GENERIC_IRQ_IPI if SMP - select GENERIC_IRQ_IPI_MUX if SMP - select GENERIC_IRQ_MULTI_HANDLER --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts-kmhv2/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch new file mode 100644 index 0000000000..b303a23ddc --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -0,0 +1,74 @@ +From a35e09fa31b7cc0d163e681b2acef99edf7f626b Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for + strrchr() + +Add a KUnit test for strrchr() to verify correctness across +different string lengths and memory alignments. Use vmalloc() +to place the NUL character at the page boundary to ensure +over-reads are detected. + +Suggested-by: Kees Cook +Signed-off-by: Feng Jiang +Reviewed-by: Kees Cook +Link: https://patch.msgid.link/20260130025018.172925-4-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit 27b2810a4a3dcd1545ec8bafc82f967eda591c47) +Signed-off-by: Han Gao +--- + lib/tests/string_kunit.c | 31 +++++++++++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c +index 1c2d57e05624..2bed641e1eae 100644 +--- a/lib/tests/string_kunit.c ++++ b/lib/tests/string_kunit.c +@@ -190,6 +190,36 @@ static void string_test_strchr(struct kunit *test) + KUNIT_ASSERT_NULL(test, result); + } + ++static void string_test_strrchr(struct kunit *test) ++{ ++ size_t buf_size; ++ char *buf, *s; ++ ++ buf_size = PAGE_ALIGN(STRING_TEST_MAX_LEN + STRING_TEST_MAX_OFFSET + 1); ++ buf = vmalloc(buf_size); ++ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); ++ ++ memset(buf, 'A', buf_size); ++ ++ for (size_t offset = 0; offset < STRING_TEST_MAX_OFFSET; offset++) { ++ for (size_t len = 0; len <= STRING_TEST_MAX_LEN; len++) { ++ s = buf + buf_size - 1 - offset - len; ++ s[len] = '\0'; ++ ++ KUNIT_EXPECT_PTR_EQ(test, strrchr(s, 'Z'), NULL); ++ ++ if (len > 0) ++ KUNIT_EXPECT_PTR_EQ(test, strrchr(s, 'A'), s + len - 1); ++ else ++ KUNIT_EXPECT_PTR_EQ(test, strrchr(s, 'A'), NULL); ++ ++ s[len] = 'A'; ++ } ++ } ++ ++ vfree(buf); ++} ++ + static void string_test_strnchr(struct kunit *test) + { + const char *test_string = "abcdefghijkl"; +@@ -685,6 +715,7 @@ static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_strnlen), + KUNIT_CASE(string_test_strchr), + KUNIT_CASE(string_test_strnchr), ++ KUNIT_CASE(string_test_strrchr), + KUNIT_CASE(string_test_strspn), + KUNIT_CASE(string_test_strcmp), + KUNIT_CASE(string_test_strcmp_long_strings), +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0244-UPSTREAM-string-provide-strends.patch b/SPECS/linux-lts-kmhv2/0244-UPSTREAM-string-provide-strends.patch deleted file mode 100644 index a94ffb8092..0000000000 --- a/SPECS/linux-lts-kmhv2/0244-UPSTREAM-string-provide-strends.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 51707af489a55246eec9dc64f9b85831e0fd4706 Mon Sep 17 00:00:00 2001 -From: Bartosz Golaszewski -Date: Wed, 12 Nov 2025 14:55:30 +0100 -Subject: [PATCH 244/467] UPSTREAM: string: provide strends() - -Implement a function for checking if a string ends with a different -string and add its kunit test cases. - -Acked-by: Linus Walleij -Link: https://lore.kernel.org/r/20251112-gpio-shared-v4-1-b51f97b1abd8@linaro.org -Signed-off-by: Bartosz Golaszewski -(cherry picked from commit 197b3f3c70d61ff1c7ca24f66d567e06fe8ed3d9) -Signed-off-by: Han Gao ---- - include/linux/string.h | 18 ++++++++++++++++++ - lib/tests/string_kunit.c | 13 +++++++++++++ - 2 files changed, 31 insertions(+) - -diff --git a/include/linux/string.h b/include/linux/string.h -index fdd3442c6bcb..929d05d1247c 100644 ---- a/include/linux/string.h -+++ b/include/linux/string.h -@@ -562,4 +562,22 @@ static inline bool strstarts(const char *str, const char *prefix) - return strncmp(str, prefix, strlen(prefix)) == 0; - } - -+/** -+ * strends - Check if a string ends with another string. -+ * @str - NULL-terminated string to check against @suffix -+ * @suffix - NULL-terminated string defining the suffix to look for in @str -+ * -+ * Returns: -+ * True if @str ends with @suffix. False in all other cases. -+ */ -+static inline bool strends(const char *str, const char *suffix) -+{ -+ unsigned int str_len = strlen(str), suffix_len = strlen(suffix); -+ -+ if (str_len < suffix_len) -+ return false; -+ -+ return !(strcmp(str + str_len - suffix_len, suffix)); -+} -+ - #endif /* _LINUX_STRING_H_ */ -diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c -index 0ed7448a26d3..f9a8e557ba77 100644 ---- a/lib/tests/string_kunit.c -+++ b/lib/tests/string_kunit.c -@@ -602,6 +602,18 @@ static void string_test_memtostr(struct kunit *test) - KUNIT_EXPECT_EQ(test, dest[7], '\0'); - } - -+static void string_test_strends(struct kunit *test) -+{ -+ KUNIT_EXPECT_TRUE(test, strends("foo-bar", "bar")); -+ KUNIT_EXPECT_TRUE(test, strends("foo-bar", "-bar")); -+ KUNIT_EXPECT_TRUE(test, strends("foobar", "foobar")); -+ KUNIT_EXPECT_TRUE(test, strends("foobar", "")); -+ KUNIT_EXPECT_FALSE(test, strends("bar", "foobar")); -+ KUNIT_EXPECT_FALSE(test, strends("", "foo")); -+ KUNIT_EXPECT_FALSE(test, strends("foobar", "ba")); -+ KUNIT_EXPECT_TRUE(test, strends("", "")); -+} -+ - static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_memset16), - KUNIT_CASE(string_test_memset32), -@@ -623,6 +635,7 @@ static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_strlcat), - KUNIT_CASE(string_test_strtomem), - KUNIT_CASE(string_test_memtostr), -+ KUNIT_CASE(string_test_strends), - {} - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0245-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts-kmhv2/0245-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch deleted file mode 100644 index 97e4def775..0000000000 --- a/SPECS/linux-lts-kmhv2/0245-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ /dev/null @@ -1,91 +0,0 @@ -From a0ea3d9866b712d229e263440d46912dd67c4437 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 245/467] UPSTREAM: lib/string_kunit: add correctness test for - strlen() - -Add a KUnit test for strlen() to verify correctness across -different string lengths and memory alignments. Use vmalloc() -to place the NUL character at the page boundary to ensure -over-reads are detected. - -Suggested-by: Kees Cook -Signed-off-by: Feng Jiang -Reviewed-by: Kees Cook -Link: https://patch.msgid.link/20260130025018.172925-2-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit ae45f896a40a07449d9b45d0395fb7245fdd75fc) -Signed-off-by: Han Gao ---- - lib/tests/string_kunit.c | 30 ++++++++++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - -diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c -index f9a8e557ba77..26962118768e 100644 ---- a/lib/tests/string_kunit.c -+++ b/lib/tests/string_kunit.c -@@ -6,10 +6,12 @@ - #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - - #include -+#include - #include - #include - #include - #include -+#include - - #define STRCMP_LARGE_BUF_LEN 2048 - #define STRCMP_CHANGE_POINT 1337 -@@ -17,6 +19,9 @@ - #define STRCMP_TEST_EXPECT_LOWER(test, fn, ...) KUNIT_EXPECT_LT(test, fn(__VA_ARGS__), 0) - #define STRCMP_TEST_EXPECT_GREATER(test, fn, ...) KUNIT_EXPECT_GT(test, fn(__VA_ARGS__), 0) - -+#define STRING_TEST_MAX_LEN 128 -+#define STRING_TEST_MAX_OFFSET 16 -+ - static void string_test_memset16(struct kunit *test) - { - unsigned i, j, k; -@@ -104,6 +109,30 @@ static void string_test_memset64(struct kunit *test) - } - } - -+static void string_test_strlen(struct kunit *test) -+{ -+ size_t buf_size; -+ char *buf, *s; -+ -+ buf_size = PAGE_ALIGN(STRING_TEST_MAX_LEN + STRING_TEST_MAX_OFFSET + 1); -+ buf = vmalloc(buf_size); -+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); -+ -+ memset(buf, 'A', buf_size); -+ -+ for (size_t offset = 0; offset < STRING_TEST_MAX_OFFSET; offset++) { -+ for (size_t len = 0; len <= STRING_TEST_MAX_LEN; len++) { -+ s = buf + buf_size - 1 - offset - len; -+ s[len] = '\0'; -+ KUNIT_EXPECT_EQ_MSG(test, strlen(s), len, -+ "offset:%zu len:%zu", offset, len); -+ s[len] = 'A'; -+ } -+ } -+ -+ vfree(buf); -+} -+ - static void string_test_strchr(struct kunit *test) - { - const char *test_string = "abcdefghijkl"; -@@ -618,6 +647,7 @@ static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_memset16), - KUNIT_CASE(string_test_memset32), - KUNIT_CASE(string_test_memset64), -+ KUNIT_CASE(string_test_strlen), - KUNIT_CASE(string_test_strchr), - KUNIT_CASE(string_test_strnchr), - KUNIT_CASE(string_test_strspn), --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch b/SPECS/linux-lts-kmhv2/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch new file mode 100644 index 0000000000..8ed6b57c83 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch @@ -0,0 +1,256 @@ +From 3157c725cd7a5774a6e772aee7c537b7bc65a90e Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add performance benchmark + for strlen() + +Introduce a benchmarking framework to the string_kunit test suite to +measure the execution efficiency of string functions. + +The implementation is inspired by crc_benchmark(), measuring throughput +(MB/s) and latency (ns/call) across a range of string lengths. It +includes a warm-up phase, disables preemption during measurement, and +uses a fixed seed for reproducible results. + +This framework allows for comparing different implementations (e.g., +generic C vs. architecture-optimized assembly) within the KUnit +environment. + +Initially, provide a benchmark for strlen(). + +Suggested-by: Andy Shevchenko +Suggested-by: Eric Biggers +Signed-off-by: Feng Jiang +Reviewed-by: Kees Cook +Link: https://patch.msgid.link/20260130025018.172925-5-jiangfeng@kylinos.cn +[pjw@kernel.org: fixed a checkpatch issue] +Signed-off-by: Paul Walmsley +(cherry picked from commit 0020240a431187628e2636284023e63b9b7a2aa1) +Signed-off-by: Han Gao +--- + lib/Kconfig.debug | 11 +++ + lib/tests/string_kunit.c | 160 +++++++++++++++++++++++++++++++++++++++ + 2 files changed, 171 insertions(+) + +diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug +index 21cd68084e46..a4d1ce2f4600 100644 +--- a/lib/Kconfig.debug ++++ b/lib/Kconfig.debug +@@ -2446,6 +2446,17 @@ config STRING_HELPERS_KUNIT_TEST + depends on KUNIT + default KUNIT_ALL_TESTS + ++config STRING_KUNIT_BENCH ++ bool "Benchmark string functions at runtime" ++ depends on STRING_KUNIT_TEST ++ help ++ Enable performance measurement for string functions. ++ ++ This measures the execution efficiency of string functions ++ during the KUnit test run. ++ ++ If unsure, say N. ++ + config FFS_KUNIT_TEST + tristate "KUnit test ffs-family functions at runtime" if !KUNIT_ALL_TESTS + depends on KUNIT +diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c +index 2bed641e1eae..cd5837373427 100644 +--- a/lib/tests/string_kunit.c ++++ b/lib/tests/string_kunit.c +@@ -6,11 +6,17 @@ + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + + #include ++#include ++#include ++#include + #include + #include ++#include + #include + #include + #include ++#include ++#include + #include + + #define STRCMP_LARGE_BUF_LEN 2048 +@@ -22,6 +28,9 @@ + #define STRING_TEST_MAX_LEN 128 + #define STRING_TEST_MAX_OFFSET 16 + ++#define STRING_BENCH_SEED 888 ++#define STRING_BENCH_WORKLOAD (1 * MEGA) ++ + static void string_test_memset16(struct kunit *test) + { + unsigned i, j, k; +@@ -707,6 +716,156 @@ static void string_test_strends(struct kunit *test) + KUNIT_EXPECT_TRUE(test, strends("", "")); + } + ++#if IS_ENABLED(CONFIG_STRING_KUNIT_BENCH) ++/* Target string lengths for benchmarking */ ++static const size_t bench_lens[] = { ++ 0, 1, 7, 8, 16, 31, 64, 127, 512, 1024, 3173, 4096, ++}; ++ ++/** ++ * alloc_max_bench_buffer() - Allocate buffer for the max test case. ++ * @test: KUnit context for managed allocation. ++ * @lens: Array of lengths used in the benchmark cases. ++ * @count: Number of elements in the @lens array. ++ * @buf_len: [out] Pointer to store the actually allocated buffer ++ * size (including NUL character). ++ * ++ * Return: Pointer to the allocated memory, or NULL on failure. ++ */ ++static void *alloc_max_bench_buffer(struct kunit *test, const size_t *lens, ++ size_t count, size_t *buf_len) ++{ ++ size_t max_len = 0; ++ void *buf; ++ ++ for (size_t i = 0; i < count; i++) ++ max_len = max(lens[i], max_len); ++ ++ /* Add space for NUL character */ ++ max_len += 1; ++ ++ buf = kunit_kzalloc(test, max_len, GFP_KERNEL); ++ if (!buf) ++ return NULL; ++ ++ if (buf_len) ++ *buf_len = max_len; ++ ++ return buf; ++} ++ ++/** ++ * fill_random_string() - Populate a buffer with a random NUL-terminated string. ++ * @buf: Buffer to fill. ++ * @len: Length of the buffer in bytes. ++ * ++ * Fills the buffer with random non-NUL bytes and ensures the string is ++ * properly NUL-terminated. ++ */ ++static void fill_random_string(char *buf, size_t len) ++{ ++ struct rnd_state state; ++ ++ if (!buf || !len) ++ return; ++ ++ /* Use a fixed seed to ensure deterministic benchmark results */ ++ prandom_seed_state(&state, STRING_BENCH_SEED); ++ prandom_bytes_state(&state, buf, len); ++ ++ /* Replace NUL characters to avoid early string termination */ ++ for (size_t i = 0; i < len; i++) { ++ if (buf[i] == '\0') ++ buf[i] = 0x01; ++ } ++ ++ buf[len - 1] = '\0'; ++} ++ ++/** ++ * STRING_BENCH() - Benchmark string functions. ++ * @iters: Number of iterations to run. ++ * @func: Function to benchmark. ++ * @...: Variable arguments passed to @func. ++ * ++ * Disables preemption and measures the total time in nanoseconds to execute ++ * @func(@__VA_ARGS__) for @iters times, including a small warm-up phase. ++ * ++ * Context: Disables preemption during measurement. ++ * Return: Total execution time in nanoseconds (u64). ++ */ ++#define STRING_BENCH(iters, func, ...) \ ++({ \ ++ /* Volatile function pointer prevents dead code elimination */ \ ++ typeof(func) (* volatile __func) = (func); \ ++ size_t __bn_iters = (iters); \ ++ size_t __bn_warm_iters; \ ++ u64 __bn_t; \ ++ \ ++ /* Use 10% of the given iterations (maximum 50) to warm up */ \ ++ __bn_warm_iters = max(__bn_iters / 10, 50U); \ ++ \ ++ for (size_t __bn_i = 0; __bn_i < __bn_warm_iters; __bn_i++) \ ++ (void)__func(__VA_ARGS__); \ ++ \ ++ preempt_disable(); \ ++ __bn_t = ktime_get_ns(); \ ++ for (size_t __bn_i = 0; __bn_i < __bn_iters; __bn_i++) \ ++ (void)__func(__VA_ARGS__); \ ++ __bn_t = ktime_get_ns() - __bn_t; \ ++ preempt_enable(); \ ++ __bn_t; \ ++}) ++ ++/** ++ * STRING_BENCH_BUF() - Benchmark harness for single-buffer functions. ++ * @test: KUnit context. ++ * @buf_name: Local char * variable name to be defined. ++ * @buf_size: Local size_t variable name to be defined. ++ * @func: Function to benchmark. ++ * @...: Extra arguments for @func. ++ * ++ * Prepares a randomized, NUL-terminated buffer and iterates through lengths ++ * in bench_lens, defining @buf_name and @buf_size in each loop. ++ */ ++#define STRING_BENCH_BUF(test, buf_name, buf_size, func, ...) \ ++do { \ ++ size_t _bn_i, _bn_iters, _bn_size = 0; \ ++ u64 _bn_t, _bn_mbps = 0, _bn_lat = 0; \ ++ char *_bn_buf; \ ++ \ ++ _bn_buf = alloc_max_bench_buffer(test, bench_lens, \ ++ ARRAY_SIZE(bench_lens), &_bn_size); \ ++ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, _bn_buf); \ ++ \ ++ fill_random_string(_bn_buf, _bn_size); \ ++ \ ++ for (_bn_i = 0; _bn_i < ARRAY_SIZE(bench_lens); _bn_i++) { \ ++ size_t buf_size = bench_lens[_bn_i]; \ ++ char *buf_name = _bn_buf + _bn_size - buf_size - 1; \ ++ _bn_iters = STRING_BENCH_WORKLOAD / max(buf_size, 1U); \ ++ \ ++ _bn_t = STRING_BENCH(_bn_iters, func, ##__VA_ARGS__); \ ++ if (_bn_t > 0) { \ ++ _bn_mbps = (u64)(buf_size) * _bn_iters * \ ++ (NSEC_PER_SEC / MEGA); \ ++ _bn_mbps = div64_u64(_bn_mbps, _bn_t); \ ++ _bn_lat = div64_u64(_bn_t, _bn_iters); \ ++ } \ ++ kunit_info(test, "len=%zu: %llu MB/s (%llu ns/call)\n", \ ++ buf_size, _bn_mbps, _bn_lat); \ ++ } \ ++} while (0) ++#else ++#define STRING_BENCH_BUF(test, buf_name, buf_size, func, ...) \ ++ kunit_skip(test, "not enabled") ++#endif /* IS_ENABLED(CONFIG_STRING_KUNIT_BENCH) */ ++ ++static void string_bench_strlen(struct kunit *test) ++{ ++ STRING_BENCH_BUF(test, buf, len, strlen, buf); ++} ++ + static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_memset16), + KUNIT_CASE(string_test_memset32), +@@ -732,6 +891,7 @@ static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_strtomem), + KUNIT_CASE(string_test_memtostr), + KUNIT_CASE(string_test_strends), ++ KUNIT_CASE(string_bench_strlen), + {} + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0246-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts-kmhv2/0246-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch deleted file mode 100644 index b070b96048..0000000000 --- a/SPECS/linux-lts-kmhv2/0246-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 7d205ff17788553db4370fc8017670aeff19fe77 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 246/467] UPSTREAM: lib/string_kunit: add correctness test for - strnlen() - -Add a KUnit test for strnlen() to verify correctness across -different string lengths and memory alignments. Use vmalloc() -to place the NUL character at the page boundary to ensure -over-reads are detected. - -Suggested-by: Andy Shevchenko -Suggested-by: Kees Cook -Signed-off-by: Feng Jiang -Reviewed-by: Kees Cook -Link: https://patch.msgid.link/20260130025018.172925-3-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit 263dca234e5cc12aa8b434592ceb655538bf4ea4) -Signed-off-by: Han Gao ---- - lib/tests/string_kunit.c | 35 +++++++++++++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - -diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c -index 26962118768e..1c2d57e05624 100644 ---- a/lib/tests/string_kunit.c -+++ b/lib/tests/string_kunit.c -@@ -133,6 +133,40 @@ static void string_test_strlen(struct kunit *test) - vfree(buf); - } - -+static void string_test_strnlen(struct kunit *test) -+{ -+ size_t buf_size; -+ char *buf, *s; -+ -+ buf_size = PAGE_ALIGN(STRING_TEST_MAX_LEN + STRING_TEST_MAX_OFFSET + 1); -+ buf = vmalloc(buf_size); -+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); -+ -+ memset(buf, 'A', buf_size); -+ -+ for (size_t offset = 0; offset < STRING_TEST_MAX_OFFSET; offset++) { -+ for (size_t len = 0; len <= STRING_TEST_MAX_LEN; len++) { -+ s = buf + buf_size - 1 - offset - len; -+ s[len] = '\0'; -+ -+ if (len > 0) -+ KUNIT_EXPECT_EQ(test, strnlen(s, len - 1), len - 1); -+ if (len > 1) -+ KUNIT_EXPECT_EQ(test, strnlen(s, len - 2), len - 2); -+ -+ KUNIT_EXPECT_EQ(test, strnlen(s, len), len); -+ -+ KUNIT_EXPECT_EQ(test, strnlen(s, len + 1), len); -+ KUNIT_EXPECT_EQ(test, strnlen(s, len + 2), len); -+ KUNIT_EXPECT_EQ(test, strnlen(s, len + 10), len); -+ -+ s[len] = 'A'; -+ } -+ } -+ -+ vfree(buf); -+} -+ - static void string_test_strchr(struct kunit *test) - { - const char *test_string = "abcdefghijkl"; -@@ -648,6 +682,7 @@ static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_memset32), - KUNIT_CASE(string_test_memset64), - KUNIT_CASE(string_test_strlen), -+ KUNIT_CASE(string_test_strnlen), - KUNIT_CASE(string_test_strchr), - KUNIT_CASE(string_test_strnchr), - KUNIT_CASE(string_test_strspn), --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch b/SPECS/linux-lts-kmhv2/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch new file mode 100644 index 0000000000..8a4b47a942 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch @@ -0,0 +1,66 @@ +From d4f3b19d0ba9850b6052f6adfda81bdd61650371 Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: extend benchmarks to + strnlen() and chr searches + +Extend the string benchmarking suite to include strnlen(), strchr(), +and strrchr(). + +For character search functions strchr() and strrchr(), the benchmark +targets the NUL character. This ensures the entire string is scanned, +providing a consistent measure of full-length processing efficiency +comparable to strlen(). + +Suggested-by: Andy Shevchenko +Suggested-by: Eric Biggers +Signed-off-by: Feng Jiang +Acked-by: Andy Shevchenko +Reviewed-by: Kees Cook +Link: https://patch.msgid.link/20260130025018.172925-6-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit e73bcb3708a69369d506e5bc6a63d4fc13d8e28a) +Signed-off-by: Han Gao +--- + lib/tests/string_kunit.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c +index cd5837373427..0819ace5b027 100644 +--- a/lib/tests/string_kunit.c ++++ b/lib/tests/string_kunit.c +@@ -866,6 +866,21 @@ static void string_bench_strlen(struct kunit *test) + STRING_BENCH_BUF(test, buf, len, strlen, buf); + } + ++static void string_bench_strnlen(struct kunit *test) ++{ ++ STRING_BENCH_BUF(test, buf, len, strnlen, buf, len); ++} ++ ++static void string_bench_strchr(struct kunit *test) ++{ ++ STRING_BENCH_BUF(test, buf, len, strchr, buf, '\0'); ++} ++ ++static void string_bench_strrchr(struct kunit *test) ++{ ++ STRING_BENCH_BUF(test, buf, len, strrchr, buf, '\0'); ++} ++ + static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_memset16), + KUNIT_CASE(string_test_memset32), +@@ -892,6 +907,9 @@ static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_memtostr), + KUNIT_CASE(string_test_strends), + KUNIT_CASE(string_bench_strlen), ++ KUNIT_CASE(string_bench_strnlen), ++ KUNIT_CASE(string_bench_strchr), ++ KUNIT_CASE(string_bench_strrchr), + {} + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0247-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts-kmhv2/0247-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch deleted file mode 100644 index ce8b0f8a5b..0000000000 --- a/SPECS/linux-lts-kmhv2/0247-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 0a17629f949ff3604a42f6cbe6c0609a51050633 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 247/467] UPSTREAM: lib/string_kunit: add correctness test for - strrchr() - -Add a KUnit test for strrchr() to verify correctness across -different string lengths and memory alignments. Use vmalloc() -to place the NUL character at the page boundary to ensure -over-reads are detected. - -Suggested-by: Kees Cook -Signed-off-by: Feng Jiang -Reviewed-by: Kees Cook -Link: https://patch.msgid.link/20260130025018.172925-4-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit 27b2810a4a3dcd1545ec8bafc82f967eda591c47) -Signed-off-by: Han Gao ---- - lib/tests/string_kunit.c | 31 +++++++++++++++++++++++++++++++ - 1 file changed, 31 insertions(+) - -diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c -index 1c2d57e05624..2bed641e1eae 100644 ---- a/lib/tests/string_kunit.c -+++ b/lib/tests/string_kunit.c -@@ -190,6 +190,36 @@ static void string_test_strchr(struct kunit *test) - KUNIT_ASSERT_NULL(test, result); - } - -+static void string_test_strrchr(struct kunit *test) -+{ -+ size_t buf_size; -+ char *buf, *s; -+ -+ buf_size = PAGE_ALIGN(STRING_TEST_MAX_LEN + STRING_TEST_MAX_OFFSET + 1); -+ buf = vmalloc(buf_size); -+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); -+ -+ memset(buf, 'A', buf_size); -+ -+ for (size_t offset = 0; offset < STRING_TEST_MAX_OFFSET; offset++) { -+ for (size_t len = 0; len <= STRING_TEST_MAX_LEN; len++) { -+ s = buf + buf_size - 1 - offset - len; -+ s[len] = '\0'; -+ -+ KUNIT_EXPECT_PTR_EQ(test, strrchr(s, 'Z'), NULL); -+ -+ if (len > 0) -+ KUNIT_EXPECT_PTR_EQ(test, strrchr(s, 'A'), s + len - 1); -+ else -+ KUNIT_EXPECT_PTR_EQ(test, strrchr(s, 'A'), NULL); -+ -+ s[len] = 'A'; -+ } -+ } -+ -+ vfree(buf); -+} -+ - static void string_test_strnchr(struct kunit *test) - { - const char *test_string = "abcdefghijkl"; -@@ -685,6 +715,7 @@ static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_strnlen), - KUNIT_CASE(string_test_strchr), - KUNIT_CASE(string_test_strnchr), -+ KUNIT_CASE(string_test_strrchr), - KUNIT_CASE(string_test_strspn), - KUNIT_CASE(string_test_strcmp), - KUNIT_CASE(string_test_strcmp_long_strings), --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch b/SPECS/linux-lts-kmhv2/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch new file mode 100644 index 0000000000..da2b0c30de --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch @@ -0,0 +1,252 @@ +From d7fce76a1ce208fab598335c38ae8071bb4d893d Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strnlen() implementation + +Add an optimized strnlen() implementation for RISC-V. This version +includes a generic optimization and a Zbb-powered optimization using +the 'orc.b' instruction, derived from the strlen() implementation. + +Benchmark results (QEMU TCG, rv64): + Length | Original (MB/s) | Optimized (MB/s) | Improvement + -------|-----------------|------------------|------------ + 16 B | 179 | 309 | +72.6% + 512 B | 347 | 1562 | +350.1% + 4096 B | 356 | 1878 | +427.5% + +Suggested-by: Qingfang Deng +Signed-off-by: Feng Jiang +Link: https://patch.msgid.link/20260130025018.172925-7-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit 5ba15d419fab848a3813eb56bbcad00e291fbc49) +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/string.h | 3 + + arch/riscv/lib/Makefile | 1 + + arch/riscv/lib/strnlen.S | 164 ++++++++++++++++++++++++++++++++ + arch/riscv/purgatory/Makefile | 5 +- + 4 files changed, 172 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/lib/strnlen.S + +diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h +index 5ba77f60bf0b..16634d67c217 100644 +--- a/arch/riscv/include/asm/string.h ++++ b/arch/riscv/include/asm/string.h +@@ -28,6 +28,9 @@ extern asmlinkage __kernel_size_t strlen(const char *); + + #define __HAVE_ARCH_STRNCMP + extern asmlinkage int strncmp(const char *cs, const char *ct, size_t count); ++ ++#define __HAVE_ARCH_STRNLEN ++extern asmlinkage __kernel_size_t strnlen(const char *, size_t); + #endif + + /* For those files which don't want to check by kasan. */ +diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile +index bbc031124974..0969d8136df0 100644 +--- a/arch/riscv/lib/Makefile ++++ b/arch/riscv/lib/Makefile +@@ -7,6 +7,7 @@ ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) + lib-y += strcmp.o + lib-y += strlen.o + lib-y += strncmp.o ++lib-y += strnlen.o + endif + lib-y += csum.o + ifeq ($(CONFIG_MMU), y) +diff --git a/arch/riscv/lib/strnlen.S b/arch/riscv/lib/strnlen.S +new file mode 100644 +index 000000000000..53afa7b5b314 +--- /dev/null ++++ b/arch/riscv/lib/strnlen.S +@@ -0,0 +1,164 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* ++ * Base on arch/riscv/lib/strlen.S ++ * ++ * Copyright (C) Feng Jiang ++ */ ++ ++#include ++#include ++#include ++#include ++ ++/* size_t strnlen(const char *s, size_t count) */ ++SYM_FUNC_START(strnlen) ++ ++ __ALTERNATIVE_CFG("nop", "j strnlen_zbb", 0, RISCV_ISA_EXT_ZBB, ++ IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) ++ ++ ++ /* ++ * Returns ++ * a0 - String length ++ * ++ * Parameters ++ * a0 - String to measure ++ * a1 - Max length of string ++ * ++ * Clobbers ++ * t0, t1, t2 ++ */ ++ addi t1, a0, -1 ++ add t2, a0, a1 ++1: ++ addi t1, t1, 1 ++ beq t1, t2, 2f ++ lbu t0, 0(t1) ++ bnez t0, 1b ++2: ++ sub a0, t1, a0 ++ ret ++ ++ ++/* ++ * Variant of strnlen using the ZBB extension if available ++ */ ++#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) ++strnlen_zbb: ++ ++#ifdef CONFIG_CPU_BIG_ENDIAN ++# define CZ clz ++# define SHIFT sll ++#else ++# define CZ ctz ++# define SHIFT srl ++#endif ++ ++.option push ++.option arch,+zbb ++ ++ /* ++ * Returns ++ * a0 - String length ++ * ++ * Parameters ++ * a0 - String to measure ++ * a1 - Max length of string ++ * ++ * Clobbers ++ * t0, t1, t2, t3, t4 ++ */ ++ ++ /* If maxlen is 0, return 0. */ ++ beqz a1, 3f ++ ++ /* Number of irrelevant bytes in the first word. */ ++ andi t2, a0, SZREG-1 ++ ++ /* Align pointer. */ ++ andi t0, a0, -SZREG ++ ++ li t3, SZREG ++ sub t3, t3, t2 ++ slli t2, t2, 3 ++ ++ /* Aligned boundary. */ ++ add t4, a0, a1 ++ andi t4, t4, -SZREG ++ ++ /* Get the first word. */ ++ REG_L t1, 0(t0) ++ ++ /* ++ * Shift away the partial data we loaded to remove the irrelevant bytes ++ * preceding the string with the effect of adding NUL bytes at the ++ * end of the string's first word. ++ */ ++ SHIFT t1, t1, t2 ++ ++ /* Convert non-NUL into 0xff and NUL into 0x00. */ ++ orc.b t1, t1 ++ ++ /* Convert non-NUL into 0x00 and NUL into 0xff. */ ++ not t1, t1 ++ ++ /* ++ * Search for the first set bit (corresponding to a NUL byte in the ++ * original chunk). ++ */ ++ CZ t1, t1 ++ ++ /* ++ * The first chunk is special: compare against the number ++ * of valid bytes in this chunk. ++ */ ++ srli a0, t1, 3 ++ ++ /* Limit the result by maxlen. */ ++ minu a0, a0, a1 ++ ++ bgtu t3, a0, 2f ++ ++ /* Prepare for the word comparison loop. */ ++ addi t2, t0, SZREG ++ li t3, -1 ++ ++ /* ++ * Our critical loop is 4 instructions and processes data in ++ * 4 byte or 8 byte chunks. ++ */ ++ .p2align 3 ++1: ++ REG_L t1, SZREG(t0) ++ addi t0, t0, SZREG ++ orc.b t1, t1 ++ bgeu t0, t4, 4f ++ beq t1, t3, 1b ++4: ++ not t1, t1 ++ CZ t1, t1 ++ srli t1, t1, 3 ++ ++ /* Get number of processed bytes. */ ++ sub t2, t0, t2 ++ ++ /* Add number of characters in the first word. */ ++ add a0, a0, t2 ++ ++ /* Add number of characters in the last word. */ ++ add a0, a0, t1 ++ ++ /* Ensure the final result does not exceed maxlen. */ ++ minu a0, a0, a1 ++2: ++ ret ++3: ++ mv a0, a1 ++ ret ++ ++.option pop ++#endif ++SYM_FUNC_END(strnlen) ++SYM_FUNC_ALIAS(__pi_strnlen, strnlen) ++EXPORT_SYMBOL(strnlen) +diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile +index 530e497ca2f9..d7c0533108be 100644 +--- a/arch/riscv/purgatory/Makefile ++++ b/arch/riscv/purgatory/Makefile +@@ -2,7 +2,7 @@ + + purgatory-y := purgatory.o sha256.o entry.o string.o ctype.o memcpy.o memset.o + ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) +-purgatory-y += strcmp.o strlen.o strncmp.o ++purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o + endif + + targets += $(purgatory-y) +@@ -32,6 +32,9 @@ $(obj)/strncmp.o: $(srctree)/arch/riscv/lib/strncmp.S FORCE + $(obj)/sha256.o: $(srctree)/lib/crypto/sha256.c FORCE + $(call if_changed_rule,cc_o_c) + ++$(obj)/strnlen.o: $(srctree)/arch/riscv/lib/strnlen.S FORCE ++ $(call if_changed_rule,as_o_S) ++ + CFLAGS_sha256.o := -D__DISABLE_EXPORTS -D__NO_FORTIFY + CFLAGS_string.o := -D__DISABLE_EXPORTS + CFLAGS_ctype.o := -D__DISABLE_EXPORTS +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0248-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch b/SPECS/linux-lts-kmhv2/0248-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch deleted file mode 100644 index 52ac6d1a18..0000000000 --- a/SPECS/linux-lts-kmhv2/0248-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch +++ /dev/null @@ -1,256 +0,0 @@ -From 1b38e17c75d77d3173ec154a74233c0c19c8f8f1 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 248/467] UPSTREAM: lib/string_kunit: add performance benchmark - for strlen() - -Introduce a benchmarking framework to the string_kunit test suite to -measure the execution efficiency of string functions. - -The implementation is inspired by crc_benchmark(), measuring throughput -(MB/s) and latency (ns/call) across a range of string lengths. It -includes a warm-up phase, disables preemption during measurement, and -uses a fixed seed for reproducible results. - -This framework allows for comparing different implementations (e.g., -generic C vs. architecture-optimized assembly) within the KUnit -environment. - -Initially, provide a benchmark for strlen(). - -Suggested-by: Andy Shevchenko -Suggested-by: Eric Biggers -Signed-off-by: Feng Jiang -Reviewed-by: Kees Cook -Link: https://patch.msgid.link/20260130025018.172925-5-jiangfeng@kylinos.cn -[pjw@kernel.org: fixed a checkpatch issue] -Signed-off-by: Paul Walmsley -(cherry picked from commit 0020240a431187628e2636284023e63b9b7a2aa1) -Signed-off-by: Han Gao ---- - lib/Kconfig.debug | 11 +++ - lib/tests/string_kunit.c | 160 +++++++++++++++++++++++++++++++++++++++ - 2 files changed, 171 insertions(+) - -diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug -index 21cd68084e46..a4d1ce2f4600 100644 ---- a/lib/Kconfig.debug -+++ b/lib/Kconfig.debug -@@ -2446,6 +2446,17 @@ config STRING_HELPERS_KUNIT_TEST - depends on KUNIT - default KUNIT_ALL_TESTS - -+config STRING_KUNIT_BENCH -+ bool "Benchmark string functions at runtime" -+ depends on STRING_KUNIT_TEST -+ help -+ Enable performance measurement for string functions. -+ -+ This measures the execution efficiency of string functions -+ during the KUnit test run. -+ -+ If unsure, say N. -+ - config FFS_KUNIT_TEST - tristate "KUnit test ffs-family functions at runtime" if !KUNIT_ALL_TESTS - depends on KUNIT -diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c -index 2bed641e1eae..cd5837373427 100644 ---- a/lib/tests/string_kunit.c -+++ b/lib/tests/string_kunit.c -@@ -6,11 +6,17 @@ - #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - - #include -+#include -+#include -+#include - #include - #include -+#include - #include - #include - #include -+#include -+#include - #include - - #define STRCMP_LARGE_BUF_LEN 2048 -@@ -22,6 +28,9 @@ - #define STRING_TEST_MAX_LEN 128 - #define STRING_TEST_MAX_OFFSET 16 - -+#define STRING_BENCH_SEED 888 -+#define STRING_BENCH_WORKLOAD (1 * MEGA) -+ - static void string_test_memset16(struct kunit *test) - { - unsigned i, j, k; -@@ -707,6 +716,156 @@ static void string_test_strends(struct kunit *test) - KUNIT_EXPECT_TRUE(test, strends("", "")); - } - -+#if IS_ENABLED(CONFIG_STRING_KUNIT_BENCH) -+/* Target string lengths for benchmarking */ -+static const size_t bench_lens[] = { -+ 0, 1, 7, 8, 16, 31, 64, 127, 512, 1024, 3173, 4096, -+}; -+ -+/** -+ * alloc_max_bench_buffer() - Allocate buffer for the max test case. -+ * @test: KUnit context for managed allocation. -+ * @lens: Array of lengths used in the benchmark cases. -+ * @count: Number of elements in the @lens array. -+ * @buf_len: [out] Pointer to store the actually allocated buffer -+ * size (including NUL character). -+ * -+ * Return: Pointer to the allocated memory, or NULL on failure. -+ */ -+static void *alloc_max_bench_buffer(struct kunit *test, const size_t *lens, -+ size_t count, size_t *buf_len) -+{ -+ size_t max_len = 0; -+ void *buf; -+ -+ for (size_t i = 0; i < count; i++) -+ max_len = max(lens[i], max_len); -+ -+ /* Add space for NUL character */ -+ max_len += 1; -+ -+ buf = kunit_kzalloc(test, max_len, GFP_KERNEL); -+ if (!buf) -+ return NULL; -+ -+ if (buf_len) -+ *buf_len = max_len; -+ -+ return buf; -+} -+ -+/** -+ * fill_random_string() - Populate a buffer with a random NUL-terminated string. -+ * @buf: Buffer to fill. -+ * @len: Length of the buffer in bytes. -+ * -+ * Fills the buffer with random non-NUL bytes and ensures the string is -+ * properly NUL-terminated. -+ */ -+static void fill_random_string(char *buf, size_t len) -+{ -+ struct rnd_state state; -+ -+ if (!buf || !len) -+ return; -+ -+ /* Use a fixed seed to ensure deterministic benchmark results */ -+ prandom_seed_state(&state, STRING_BENCH_SEED); -+ prandom_bytes_state(&state, buf, len); -+ -+ /* Replace NUL characters to avoid early string termination */ -+ for (size_t i = 0; i < len; i++) { -+ if (buf[i] == '\0') -+ buf[i] = 0x01; -+ } -+ -+ buf[len - 1] = '\0'; -+} -+ -+/** -+ * STRING_BENCH() - Benchmark string functions. -+ * @iters: Number of iterations to run. -+ * @func: Function to benchmark. -+ * @...: Variable arguments passed to @func. -+ * -+ * Disables preemption and measures the total time in nanoseconds to execute -+ * @func(@__VA_ARGS__) for @iters times, including a small warm-up phase. -+ * -+ * Context: Disables preemption during measurement. -+ * Return: Total execution time in nanoseconds (u64). -+ */ -+#define STRING_BENCH(iters, func, ...) \ -+({ \ -+ /* Volatile function pointer prevents dead code elimination */ \ -+ typeof(func) (* volatile __func) = (func); \ -+ size_t __bn_iters = (iters); \ -+ size_t __bn_warm_iters; \ -+ u64 __bn_t; \ -+ \ -+ /* Use 10% of the given iterations (maximum 50) to warm up */ \ -+ __bn_warm_iters = max(__bn_iters / 10, 50U); \ -+ \ -+ for (size_t __bn_i = 0; __bn_i < __bn_warm_iters; __bn_i++) \ -+ (void)__func(__VA_ARGS__); \ -+ \ -+ preempt_disable(); \ -+ __bn_t = ktime_get_ns(); \ -+ for (size_t __bn_i = 0; __bn_i < __bn_iters; __bn_i++) \ -+ (void)__func(__VA_ARGS__); \ -+ __bn_t = ktime_get_ns() - __bn_t; \ -+ preempt_enable(); \ -+ __bn_t; \ -+}) -+ -+/** -+ * STRING_BENCH_BUF() - Benchmark harness for single-buffer functions. -+ * @test: KUnit context. -+ * @buf_name: Local char * variable name to be defined. -+ * @buf_size: Local size_t variable name to be defined. -+ * @func: Function to benchmark. -+ * @...: Extra arguments for @func. -+ * -+ * Prepares a randomized, NUL-terminated buffer and iterates through lengths -+ * in bench_lens, defining @buf_name and @buf_size in each loop. -+ */ -+#define STRING_BENCH_BUF(test, buf_name, buf_size, func, ...) \ -+do { \ -+ size_t _bn_i, _bn_iters, _bn_size = 0; \ -+ u64 _bn_t, _bn_mbps = 0, _bn_lat = 0; \ -+ char *_bn_buf; \ -+ \ -+ _bn_buf = alloc_max_bench_buffer(test, bench_lens, \ -+ ARRAY_SIZE(bench_lens), &_bn_size); \ -+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, _bn_buf); \ -+ \ -+ fill_random_string(_bn_buf, _bn_size); \ -+ \ -+ for (_bn_i = 0; _bn_i < ARRAY_SIZE(bench_lens); _bn_i++) { \ -+ size_t buf_size = bench_lens[_bn_i]; \ -+ char *buf_name = _bn_buf + _bn_size - buf_size - 1; \ -+ _bn_iters = STRING_BENCH_WORKLOAD / max(buf_size, 1U); \ -+ \ -+ _bn_t = STRING_BENCH(_bn_iters, func, ##__VA_ARGS__); \ -+ if (_bn_t > 0) { \ -+ _bn_mbps = (u64)(buf_size) * _bn_iters * \ -+ (NSEC_PER_SEC / MEGA); \ -+ _bn_mbps = div64_u64(_bn_mbps, _bn_t); \ -+ _bn_lat = div64_u64(_bn_t, _bn_iters); \ -+ } \ -+ kunit_info(test, "len=%zu: %llu MB/s (%llu ns/call)\n", \ -+ buf_size, _bn_mbps, _bn_lat); \ -+ } \ -+} while (0) -+#else -+#define STRING_BENCH_BUF(test, buf_name, buf_size, func, ...) \ -+ kunit_skip(test, "not enabled") -+#endif /* IS_ENABLED(CONFIG_STRING_KUNIT_BENCH) */ -+ -+static void string_bench_strlen(struct kunit *test) -+{ -+ STRING_BENCH_BUF(test, buf, len, strlen, buf); -+} -+ - static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_memset16), - KUNIT_CASE(string_test_memset32), -@@ -732,6 +891,7 @@ static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_strtomem), - KUNIT_CASE(string_test_memtostr), - KUNIT_CASE(string_test_strends), -+ KUNIT_CASE(string_bench_strlen), - {} - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch b/SPECS/linux-lts-kmhv2/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch new file mode 100644 index 0000000000..82e732ebcb --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch @@ -0,0 +1,129 @@ +From 2f4c1bb28db6a3485cd348d5484cabeee5afb672 Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strchr() implementation + +Add an assembly implementation of strchr() for RISC-V. + +By eliminating stack frame management (prologue/epilogue) and optimizing +the function entries, the assembly version provides significant relative +gains for short strings where the fixed overhead of the C function is +most prominent. As string length increases, performance converges with +the generic C implementation. + +Benchmark results (QEMU TCG, rv64): + Length | Original (MB/s) | Optimized (MB/s) | Improvement + -------|-----------------|------------------|------------ + 1 B | 21 | 22 | +4.8% + 7 B | 113 | 121 | +7.1% + 16 B | 195 | 202 | +3.6% + 512 B | 376 | 389 | +3.5% + 4096 B | 394 | 393 | -0.3% + +Signed-off-by: Feng Jiang +Tested-by: Joel Stanley +Link: https://patch.msgid.link/20260130025018.172925-8-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit adf542133960d402f63c976b00e46be4d986d4c3) +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/string.h | 3 +++ + arch/riscv/lib/Makefile | 1 + + arch/riscv/lib/strchr.S | 35 +++++++++++++++++++++++++++++++++ + arch/riscv/purgatory/Makefile | 5 ++++- + 4 files changed, 43 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/lib/strchr.S + +diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h +index 16634d67c217..ca3ade82b124 100644 +--- a/arch/riscv/include/asm/string.h ++++ b/arch/riscv/include/asm/string.h +@@ -31,6 +31,9 @@ extern asmlinkage int strncmp(const char *cs, const char *ct, size_t count); + + #define __HAVE_ARCH_STRNLEN + extern asmlinkage __kernel_size_t strnlen(const char *, size_t); ++ ++#define __HAVE_ARCH_STRCHR ++extern asmlinkage char *strchr(const char *, int); + #endif + + /* For those files which don't want to check by kasan. */ +diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile +index 0969d8136df0..b7f804dce1c3 100644 +--- a/arch/riscv/lib/Makefile ++++ b/arch/riscv/lib/Makefile +@@ -8,6 +8,7 @@ lib-y += strcmp.o + lib-y += strlen.o + lib-y += strncmp.o + lib-y += strnlen.o ++lib-y += strchr.o + endif + lib-y += csum.o + ifeq ($(CONFIG_MMU), y) +diff --git a/arch/riscv/lib/strchr.S b/arch/riscv/lib/strchr.S +new file mode 100644 +index 000000000000..48c3a9da53e3 +--- /dev/null ++++ b/arch/riscv/lib/strchr.S +@@ -0,0 +1,35 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* ++ * Copyright (C) 2025 Feng Jiang ++ */ ++ ++#include ++#include ++ ++/* char *strchr(const char *s, int c) */ ++SYM_FUNC_START(strchr) ++ /* ++ * Parameters ++ * a0 - The string to be searched ++ * a1 - The character to search for ++ * ++ * Returns ++ * a0 - Address of first occurrence of 'c' or 0 ++ * ++ * Clobbers ++ * t0 ++ */ ++ andi a1, a1, 0xff ++1: ++ lbu t0, 0(a0) ++ beq t0, a1, 2f ++ addi a0, a0, 1 ++ bnez t0, 1b ++ li a0, 0 ++2: ++ ret ++SYM_FUNC_END(strchr) ++ ++SYM_FUNC_ALIAS_WEAK(__pi_strchr, strchr) ++EXPORT_SYMBOL(strchr) +diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile +index d7c0533108be..e7b3d748c913 100644 +--- a/arch/riscv/purgatory/Makefile ++++ b/arch/riscv/purgatory/Makefile +@@ -2,7 +2,7 @@ + + purgatory-y := purgatory.o sha256.o entry.o string.o ctype.o memcpy.o memset.o + ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) +-purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o ++purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o strchr.o + endif + + targets += $(purgatory-y) +@@ -35,6 +35,9 @@ $(obj)/sha256.o: $(srctree)/lib/crypto/sha256.c FORCE + $(obj)/strnlen.o: $(srctree)/arch/riscv/lib/strnlen.S FORCE + $(call if_changed_rule,as_o_S) + ++$(obj)/strchr.o: $(srctree)/arch/riscv/lib/strchr.S FORCE ++ $(call if_changed_rule,as_o_S) ++ + CFLAGS_sha256.o := -D__DISABLE_EXPORTS -D__NO_FORTIFY + CFLAGS_string.o := -D__DISABLE_EXPORTS + CFLAGS_ctype.o := -D__DISABLE_EXPORTS +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0249-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch b/SPECS/linux-lts-kmhv2/0249-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch deleted file mode 100644 index dfda66cc5e..0000000000 --- a/SPECS/linux-lts-kmhv2/0249-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch +++ /dev/null @@ -1,66 +0,0 @@ -From d0124b59c28b2a764db245d8be9fc383ac7e7933 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 249/467] UPSTREAM: lib/string_kunit: extend benchmarks to - strnlen() and chr searches - -Extend the string benchmarking suite to include strnlen(), strchr(), -and strrchr(). - -For character search functions strchr() and strrchr(), the benchmark -targets the NUL character. This ensures the entire string is scanned, -providing a consistent measure of full-length processing efficiency -comparable to strlen(). - -Suggested-by: Andy Shevchenko -Suggested-by: Eric Biggers -Signed-off-by: Feng Jiang -Acked-by: Andy Shevchenko -Reviewed-by: Kees Cook -Link: https://patch.msgid.link/20260130025018.172925-6-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit e73bcb3708a69369d506e5bc6a63d4fc13d8e28a) -Signed-off-by: Han Gao ---- - lib/tests/string_kunit.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c -index cd5837373427..0819ace5b027 100644 ---- a/lib/tests/string_kunit.c -+++ b/lib/tests/string_kunit.c -@@ -866,6 +866,21 @@ static void string_bench_strlen(struct kunit *test) - STRING_BENCH_BUF(test, buf, len, strlen, buf); - } - -+static void string_bench_strnlen(struct kunit *test) -+{ -+ STRING_BENCH_BUF(test, buf, len, strnlen, buf, len); -+} -+ -+static void string_bench_strchr(struct kunit *test) -+{ -+ STRING_BENCH_BUF(test, buf, len, strchr, buf, '\0'); -+} -+ -+static void string_bench_strrchr(struct kunit *test) -+{ -+ STRING_BENCH_BUF(test, buf, len, strrchr, buf, '\0'); -+} -+ - static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_memset16), - KUNIT_CASE(string_test_memset32), -@@ -892,6 +907,9 @@ static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_memtostr), - KUNIT_CASE(string_test_strends), - KUNIT_CASE(string_bench_strlen), -+ KUNIT_CASE(string_bench_strnlen), -+ KUNIT_CASE(string_bench_strchr), -+ KUNIT_CASE(string_bench_strrchr), - {} - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch b/SPECS/linux-lts-kmhv2/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch new file mode 100644 index 0000000000..4a1a619b26 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch @@ -0,0 +1,130 @@ +From 7a1bef3a9306a7c4cd45d233b4965356c86f23d4 Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strrchr() implementation + +Add an assembly implementation of strrchr() for RISC-V. + +This implementation minimizes instruction count and avoids unnecessary +memory access to the stack. The performance benefits are most visible +on small workloads (1-16 bytes) where the architectural savings in +function overhead outweigh the execution time of the scan loop. + +Benchmark results (QEMU TCG, rv64): + Length | Original (MB/s) | Optimized (MB/s) | Improvement + -------|-----------------|------------------|------------ + 1 B | 20 | 21 | +5.0% + 7 B | 111 | 120 | +8.1% + 16 B | 189 | 199 | +5.3% + 512 B | 361 | 382 | +5.8% + 4096 B | 388 | 391 | +0.8% + +Signed-off-by: Feng Jiang +Tested-by: Joel Stanley +Link: https://patch.msgid.link/20260130025018.172925-9-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit bef64bcb940269a503d12eb1bc180d1aa9adf74d) +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/string.h | 3 +++ + arch/riscv/lib/Makefile | 1 + + arch/riscv/lib/strrchr.S | 37 +++++++++++++++++++++++++++++++++ + arch/riscv/purgatory/Makefile | 5 ++++- + 4 files changed, 45 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/lib/strrchr.S + +diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h +index ca3ade82b124..764ffe8f6479 100644 +--- a/arch/riscv/include/asm/string.h ++++ b/arch/riscv/include/asm/string.h +@@ -34,6 +34,9 @@ extern asmlinkage __kernel_size_t strnlen(const char *, size_t); + + #define __HAVE_ARCH_STRCHR + extern asmlinkage char *strchr(const char *, int); ++ ++#define __HAVE_ARCH_STRRCHR ++extern asmlinkage char *strrchr(const char *, int); + #endif + + /* For those files which don't want to check by kasan. */ +diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile +index b7f804dce1c3..735d0b665536 100644 +--- a/arch/riscv/lib/Makefile ++++ b/arch/riscv/lib/Makefile +@@ -9,6 +9,7 @@ lib-y += strlen.o + lib-y += strncmp.o + lib-y += strnlen.o + lib-y += strchr.o ++lib-y += strrchr.o + endif + lib-y += csum.o + ifeq ($(CONFIG_MMU), y) +diff --git a/arch/riscv/lib/strrchr.S b/arch/riscv/lib/strrchr.S +new file mode 100644 +index 000000000000..ac58b20ca21d +--- /dev/null ++++ b/arch/riscv/lib/strrchr.S +@@ -0,0 +1,37 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* ++ * Copyright (C) 2025 Feng Jiang ++ */ ++ ++#include ++#include ++ ++/* char *strrchr(const char *s, int c) */ ++SYM_FUNC_START(strrchr) ++ /* ++ * Parameters ++ * a0 - The string to be searched ++ * a1 - The character to seaerch for ++ * ++ * Returns ++ * a0 - Address of last occurrence of 'c' or 0 ++ * ++ * Clobbers ++ * t0, t1 ++ */ ++ andi a1, a1, 0xff ++ mv t1, a0 ++ li a0, 0 ++1: ++ lbu t0, 0(t1) ++ bne t0, a1, 2f ++ mv a0, t1 ++2: ++ addi t1, t1, 1 ++ bnez t0, 1b ++ ret ++SYM_FUNC_END(strrchr) ++ ++SYM_FUNC_ALIAS_WEAK(__pi_strrchr, strrchr) ++EXPORT_SYMBOL(strrchr) +diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile +index e7b3d748c913..b0358a78f11a 100644 +--- a/arch/riscv/purgatory/Makefile ++++ b/arch/riscv/purgatory/Makefile +@@ -2,7 +2,7 @@ + + purgatory-y := purgatory.o sha256.o entry.o string.o ctype.o memcpy.o memset.o + ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) +-purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o strchr.o ++purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o strchr.o strrchr.o + endif + + targets += $(purgatory-y) +@@ -38,6 +38,9 @@ $(obj)/strnlen.o: $(srctree)/arch/riscv/lib/strnlen.S FORCE + $(obj)/strchr.o: $(srctree)/arch/riscv/lib/strchr.S FORCE + $(call if_changed_rule,as_o_S) + ++$(obj)/strrchr.o: $(srctree)/arch/riscv/lib/strrchr.S FORCE ++ $(call if_changed_rule,as_o_S) ++ + CFLAGS_sha256.o := -D__DISABLE_EXPORTS -D__NO_FORTIFY + CFLAGS_string.o := -D__DISABLE_EXPORTS + CFLAGS_ctype.o := -D__DISABLE_EXPORTS +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch b/SPECS/linux-lts-kmhv2/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch new file mode 100644 index 0000000000..a11233ee84 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch @@ -0,0 +1,52 @@ +From 0bd7f056d6569dc61e0cc65e7eaab3c9d9d1e879 Mon Sep 17 00:00:00 2001 +From: Vincent Guittot +Date: Fri, 21 Nov 2025 17:49:18 +0100 +Subject: [RUYI PATCH] UPSTREAM: PCI: dwc: Add register and bitfield + definitions + +Add register and bitfield definitions: + + - GEN3_RELATED_OFF_EQ_PHASE_2_3 field of GEN3_RELATED_OFF + + - Coherency control registers + +Signed-off-by: Vincent Guittot +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Helgaas +Reviewed-by: Frank Li +Link: https://patch.msgid.link/20251121164920.2008569-3-vincent.guittot@linaro.org +(cherry picked from commit 045ad2c623d607f2c7720e2b8fcda675d96f7381) +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-designware.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h +index aa27211b68dd..295e113189b7 100644 +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -123,6 +123,7 @@ + + #define GEN3_RELATED_OFF 0x890 + #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) ++#define GEN3_RELATED_OFF_EQ_PHASE_2_3 BIT(9) + #define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13) + #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) + #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 +@@ -140,6 +141,13 @@ + #define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA GENMASK(13, 10) + #define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA GENMASK(17, 14) + ++#define COHERENCY_CONTROL_1_OFF 0x8E0 ++#define CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK GENMASK(31, 2) ++#define CFG_MEMTYPE_VALUE BIT(0) ++ ++#define COHERENCY_CONTROL_2_OFF 0x8E4 ++#define COHERENCY_CONTROL_3_OFF 0x8E8 ++ + #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 + #define PORT_MLTI_UPCFG_SUPPORT BIT(7) + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0250-UPSTREAM-riscv-lib-add-strnlen-implementation.patch b/SPECS/linux-lts-kmhv2/0250-UPSTREAM-riscv-lib-add-strnlen-implementation.patch deleted file mode 100644 index c5b7f485ce..0000000000 --- a/SPECS/linux-lts-kmhv2/0250-UPSTREAM-riscv-lib-add-strnlen-implementation.patch +++ /dev/null @@ -1,252 +0,0 @@ -From c90c1b627d1a7bfa2d85045606e6db6a1224dbe2 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 250/467] UPSTREAM: riscv: lib: add strnlen() implementation - -Add an optimized strnlen() implementation for RISC-V. This version -includes a generic optimization and a Zbb-powered optimization using -the 'orc.b' instruction, derived from the strlen() implementation. - -Benchmark results (QEMU TCG, rv64): - Length | Original (MB/s) | Optimized (MB/s) | Improvement - -------|-----------------|------------------|------------ - 16 B | 179 | 309 | +72.6% - 512 B | 347 | 1562 | +350.1% - 4096 B | 356 | 1878 | +427.5% - -Suggested-by: Qingfang Deng -Signed-off-by: Feng Jiang -Link: https://patch.msgid.link/20260130025018.172925-7-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit 5ba15d419fab848a3813eb56bbcad00e291fbc49) -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/string.h | 3 + - arch/riscv/lib/Makefile | 1 + - arch/riscv/lib/strnlen.S | 164 ++++++++++++++++++++++++++++++++ - arch/riscv/purgatory/Makefile | 5 +- - 4 files changed, 172 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/lib/strnlen.S - -diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h -index 5ba77f60bf0b..16634d67c217 100644 ---- a/arch/riscv/include/asm/string.h -+++ b/arch/riscv/include/asm/string.h -@@ -28,6 +28,9 @@ extern asmlinkage __kernel_size_t strlen(const char *); - - #define __HAVE_ARCH_STRNCMP - extern asmlinkage int strncmp(const char *cs, const char *ct, size_t count); -+ -+#define __HAVE_ARCH_STRNLEN -+extern asmlinkage __kernel_size_t strnlen(const char *, size_t); - #endif - - /* For those files which don't want to check by kasan. */ -diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile -index bbc031124974..0969d8136df0 100644 ---- a/arch/riscv/lib/Makefile -+++ b/arch/riscv/lib/Makefile -@@ -7,6 +7,7 @@ ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) - lib-y += strcmp.o - lib-y += strlen.o - lib-y += strncmp.o -+lib-y += strnlen.o - endif - lib-y += csum.o - ifeq ($(CONFIG_MMU), y) -diff --git a/arch/riscv/lib/strnlen.S b/arch/riscv/lib/strnlen.S -new file mode 100644 -index 000000000000..53afa7b5b314 ---- /dev/null -+++ b/arch/riscv/lib/strnlen.S -@@ -0,0 +1,164 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* -+ * Base on arch/riscv/lib/strlen.S -+ * -+ * Copyright (C) Feng Jiang -+ */ -+ -+#include -+#include -+#include -+#include -+ -+/* size_t strnlen(const char *s, size_t count) */ -+SYM_FUNC_START(strnlen) -+ -+ __ALTERNATIVE_CFG("nop", "j strnlen_zbb", 0, RISCV_ISA_EXT_ZBB, -+ IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) -+ -+ -+ /* -+ * Returns -+ * a0 - String length -+ * -+ * Parameters -+ * a0 - String to measure -+ * a1 - Max length of string -+ * -+ * Clobbers -+ * t0, t1, t2 -+ */ -+ addi t1, a0, -1 -+ add t2, a0, a1 -+1: -+ addi t1, t1, 1 -+ beq t1, t2, 2f -+ lbu t0, 0(t1) -+ bnez t0, 1b -+2: -+ sub a0, t1, a0 -+ ret -+ -+ -+/* -+ * Variant of strnlen using the ZBB extension if available -+ */ -+#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) -+strnlen_zbb: -+ -+#ifdef CONFIG_CPU_BIG_ENDIAN -+# define CZ clz -+# define SHIFT sll -+#else -+# define CZ ctz -+# define SHIFT srl -+#endif -+ -+.option push -+.option arch,+zbb -+ -+ /* -+ * Returns -+ * a0 - String length -+ * -+ * Parameters -+ * a0 - String to measure -+ * a1 - Max length of string -+ * -+ * Clobbers -+ * t0, t1, t2, t3, t4 -+ */ -+ -+ /* If maxlen is 0, return 0. */ -+ beqz a1, 3f -+ -+ /* Number of irrelevant bytes in the first word. */ -+ andi t2, a0, SZREG-1 -+ -+ /* Align pointer. */ -+ andi t0, a0, -SZREG -+ -+ li t3, SZREG -+ sub t3, t3, t2 -+ slli t2, t2, 3 -+ -+ /* Aligned boundary. */ -+ add t4, a0, a1 -+ andi t4, t4, -SZREG -+ -+ /* Get the first word. */ -+ REG_L t1, 0(t0) -+ -+ /* -+ * Shift away the partial data we loaded to remove the irrelevant bytes -+ * preceding the string with the effect of adding NUL bytes at the -+ * end of the string's first word. -+ */ -+ SHIFT t1, t1, t2 -+ -+ /* Convert non-NUL into 0xff and NUL into 0x00. */ -+ orc.b t1, t1 -+ -+ /* Convert non-NUL into 0x00 and NUL into 0xff. */ -+ not t1, t1 -+ -+ /* -+ * Search for the first set bit (corresponding to a NUL byte in the -+ * original chunk). -+ */ -+ CZ t1, t1 -+ -+ /* -+ * The first chunk is special: compare against the number -+ * of valid bytes in this chunk. -+ */ -+ srli a0, t1, 3 -+ -+ /* Limit the result by maxlen. */ -+ minu a0, a0, a1 -+ -+ bgtu t3, a0, 2f -+ -+ /* Prepare for the word comparison loop. */ -+ addi t2, t0, SZREG -+ li t3, -1 -+ -+ /* -+ * Our critical loop is 4 instructions and processes data in -+ * 4 byte or 8 byte chunks. -+ */ -+ .p2align 3 -+1: -+ REG_L t1, SZREG(t0) -+ addi t0, t0, SZREG -+ orc.b t1, t1 -+ bgeu t0, t4, 4f -+ beq t1, t3, 1b -+4: -+ not t1, t1 -+ CZ t1, t1 -+ srli t1, t1, 3 -+ -+ /* Get number of processed bytes. */ -+ sub t2, t0, t2 -+ -+ /* Add number of characters in the first word. */ -+ add a0, a0, t2 -+ -+ /* Add number of characters in the last word. */ -+ add a0, a0, t1 -+ -+ /* Ensure the final result does not exceed maxlen. */ -+ minu a0, a0, a1 -+2: -+ ret -+3: -+ mv a0, a1 -+ ret -+ -+.option pop -+#endif -+SYM_FUNC_END(strnlen) -+SYM_FUNC_ALIAS(__pi_strnlen, strnlen) -+EXPORT_SYMBOL(strnlen) -diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile -index 530e497ca2f9..d7c0533108be 100644 ---- a/arch/riscv/purgatory/Makefile -+++ b/arch/riscv/purgatory/Makefile -@@ -2,7 +2,7 @@ - - purgatory-y := purgatory.o sha256.o entry.o string.o ctype.o memcpy.o memset.o - ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) --purgatory-y += strcmp.o strlen.o strncmp.o -+purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o - endif - - targets += $(purgatory-y) -@@ -32,6 +32,9 @@ $(obj)/strncmp.o: $(srctree)/arch/riscv/lib/strncmp.S FORCE - $(obj)/sha256.o: $(srctree)/lib/crypto/sha256.c FORCE - $(call if_changed_rule,cc_o_c) - -+$(obj)/strnlen.o: $(srctree)/arch/riscv/lib/strnlen.S FORCE -+ $(call if_changed_rule,as_o_S) -+ - CFLAGS_sha256.o := -D__DISABLE_EXPORTS -D__NO_FORTIFY - CFLAGS_string.o := -D__DISABLE_EXPORTS - CFLAGS_ctype.o := -D__DISABLE_EXPORTS --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch b/SPECS/linux-lts-kmhv2/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch new file mode 100644 index 0000000000..9b9454daa8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch @@ -0,0 +1,100 @@ +From 22c3a93bf61eb47e3b47fd1cbfb9bed064b5de81 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Wed, 29 Apr 2026 09:38:47 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: move hw constraints from + hw_params to startup + +Hardware constraints should be applied in the startup callback rather +than hw_params, as hw_params may be called too late for the constraints +to take effect properly. + +Move the channel count and format constraints for I2S and DSP_A/DSP_B +modes into a new startup callback. This also tightens the I2S mode +channel constraint from 1-2 to exactly 2, matching the actual hardware +behavior. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260429-k3-i2s-v1-2-2fe99db11ecb@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit 6b4afbaaa342eaa52172e0be5ef8d1fcbf9ff460) +Signed-off-by: Han Gao +--- + sound/soc/spacemit/k1_i2s.c | 45 ++++++++++++++++++++++++++----------- + 1 file changed, 32 insertions(+), 13 deletions(-) + +diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c +index abc439b53e3d..331668b979fd 100644 +--- a/sound/soc/spacemit/k1_i2s.c ++++ b/sound/soc/spacemit/k1_i2s.c +@@ -106,6 +106,37 @@ static void spacemit_i2s_init(struct spacemit_i2s_dev *i2s) + writel(0, i2s->base + SSINTEN); + } + ++static int spacemit_i2s_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct spacemit_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); ++ ++ switch (i2s->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ snd_pcm_hw_constraint_minmax(substream->runtime, ++ SNDRV_PCM_HW_PARAM_CHANNELS, ++ 2, 2); ++ snd_pcm_hw_constraint_mask64(substream->runtime, ++ SNDRV_PCM_HW_PARAM_FORMAT, ++ SNDRV_PCM_FMTBIT_S16_LE); ++ break; ++ case SND_SOC_DAIFMT_DSP_A: ++ case SND_SOC_DAIFMT_DSP_B: ++ snd_pcm_hw_constraint_minmax(substream->runtime, ++ SNDRV_PCM_HW_PARAM_CHANNELS, ++ 1, 1); ++ snd_pcm_hw_constraint_mask64(substream->runtime, ++ SNDRV_PCM_HW_PARAM_FORMAT, ++ SNDRV_PCM_FMTBIT_S32_LE); ++ break; ++ default: ++ dev_dbg(i2s->dev, "unexpected format type"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ + static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +@@ -157,22 +188,9 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, + dma_data->maxburst = 32; + dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + } +- +- snd_pcm_hw_constraint_minmax(substream->runtime, +- SNDRV_PCM_HW_PARAM_CHANNELS, +- 1, 2); +- snd_pcm_hw_constraint_mask64(substream->runtime, +- SNDRV_PCM_HW_PARAM_FORMAT, +- SNDRV_PCM_FMTBIT_S16_LE); + break; + case SND_SOC_DAIFMT_DSP_A: + case SND_SOC_DAIFMT_DSP_B: +- snd_pcm_hw_constraint_minmax(substream->runtime, +- SNDRV_PCM_HW_PARAM_CHANNELS, +- 1, 1); +- snd_pcm_hw_constraint_mask64(substream->runtime, +- SNDRV_PCM_HW_PARAM_FORMAT, +- SNDRV_PCM_FMTBIT_S32_LE); + break; + default: + dev_dbg(i2s->dev, "unexpected format type"); +@@ -303,6 +321,7 @@ static int spacemit_i2s_dai_remove(struct snd_soc_dai *dai) + static const struct snd_soc_dai_ops spacemit_i2s_dai_ops = { + .probe = spacemit_i2s_dai_probe, + .remove = spacemit_i2s_dai_remove, ++ .startup = spacemit_i2s_startup, + .hw_params = spacemit_i2s_hw_params, + .set_sysclk = spacemit_i2s_set_sysclk, + .set_fmt = spacemit_i2s_set_fmt, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0251-UPSTREAM-riscv-lib-add-strchr-implementation.patch b/SPECS/linux-lts-kmhv2/0251-UPSTREAM-riscv-lib-add-strchr-implementation.patch deleted file mode 100644 index 11242e7cf1..0000000000 --- a/SPECS/linux-lts-kmhv2/0251-UPSTREAM-riscv-lib-add-strchr-implementation.patch +++ /dev/null @@ -1,129 +0,0 @@ -From d70c03b9f8f7b1f45dfa6d3b248cd26e173574bf Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 251/467] UPSTREAM: riscv: lib: add strchr() implementation - -Add an assembly implementation of strchr() for RISC-V. - -By eliminating stack frame management (prologue/epilogue) and optimizing -the function entries, the assembly version provides significant relative -gains for short strings where the fixed overhead of the C function is -most prominent. As string length increases, performance converges with -the generic C implementation. - -Benchmark results (QEMU TCG, rv64): - Length | Original (MB/s) | Optimized (MB/s) | Improvement - -------|-----------------|------------------|------------ - 1 B | 21 | 22 | +4.8% - 7 B | 113 | 121 | +7.1% - 16 B | 195 | 202 | +3.6% - 512 B | 376 | 389 | +3.5% - 4096 B | 394 | 393 | -0.3% - -Signed-off-by: Feng Jiang -Tested-by: Joel Stanley -Link: https://patch.msgid.link/20260130025018.172925-8-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit adf542133960d402f63c976b00e46be4d986d4c3) -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/string.h | 3 +++ - arch/riscv/lib/Makefile | 1 + - arch/riscv/lib/strchr.S | 35 +++++++++++++++++++++++++++++++++ - arch/riscv/purgatory/Makefile | 5 ++++- - 4 files changed, 43 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/lib/strchr.S - -diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h -index 16634d67c217..ca3ade82b124 100644 ---- a/arch/riscv/include/asm/string.h -+++ b/arch/riscv/include/asm/string.h -@@ -31,6 +31,9 @@ extern asmlinkage int strncmp(const char *cs, const char *ct, size_t count); - - #define __HAVE_ARCH_STRNLEN - extern asmlinkage __kernel_size_t strnlen(const char *, size_t); -+ -+#define __HAVE_ARCH_STRCHR -+extern asmlinkage char *strchr(const char *, int); - #endif - - /* For those files which don't want to check by kasan. */ -diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile -index 0969d8136df0..b7f804dce1c3 100644 ---- a/arch/riscv/lib/Makefile -+++ b/arch/riscv/lib/Makefile -@@ -8,6 +8,7 @@ lib-y += strcmp.o - lib-y += strlen.o - lib-y += strncmp.o - lib-y += strnlen.o -+lib-y += strchr.o - endif - lib-y += csum.o - ifeq ($(CONFIG_MMU), y) -diff --git a/arch/riscv/lib/strchr.S b/arch/riscv/lib/strchr.S -new file mode 100644 -index 000000000000..48c3a9da53e3 ---- /dev/null -+++ b/arch/riscv/lib/strchr.S -@@ -0,0 +1,35 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* -+ * Copyright (C) 2025 Feng Jiang -+ */ -+ -+#include -+#include -+ -+/* char *strchr(const char *s, int c) */ -+SYM_FUNC_START(strchr) -+ /* -+ * Parameters -+ * a0 - The string to be searched -+ * a1 - The character to search for -+ * -+ * Returns -+ * a0 - Address of first occurrence of 'c' or 0 -+ * -+ * Clobbers -+ * t0 -+ */ -+ andi a1, a1, 0xff -+1: -+ lbu t0, 0(a0) -+ beq t0, a1, 2f -+ addi a0, a0, 1 -+ bnez t0, 1b -+ li a0, 0 -+2: -+ ret -+SYM_FUNC_END(strchr) -+ -+SYM_FUNC_ALIAS_WEAK(__pi_strchr, strchr) -+EXPORT_SYMBOL(strchr) -diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile -index d7c0533108be..e7b3d748c913 100644 ---- a/arch/riscv/purgatory/Makefile -+++ b/arch/riscv/purgatory/Makefile -@@ -2,7 +2,7 @@ - - purgatory-y := purgatory.o sha256.o entry.o string.o ctype.o memcpy.o memset.o - ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) --purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o -+purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o strchr.o - endif - - targets += $(purgatory-y) -@@ -35,6 +35,9 @@ $(obj)/sha256.o: $(srctree)/lib/crypto/sha256.c FORCE - $(obj)/strnlen.o: $(srctree)/arch/riscv/lib/strnlen.S FORCE - $(call if_changed_rule,as_o_S) - -+$(obj)/strchr.o: $(srctree)/arch/riscv/lib/strchr.S FORCE -+ $(call if_changed_rule,as_o_S) -+ - CFLAGS_sha256.o := -D__DISABLE_EXPORTS -D__NO_FORTIFY - CFLAGS_string.o := -D__DISABLE_EXPORTS - CFLAGS_ctype.o := -D__DISABLE_EXPORTS --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch b/SPECS/linux-lts-kmhv2/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch new file mode 100644 index 0000000000..a235db3255 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch @@ -0,0 +1,38 @@ +From b81d7e8285e49c07fa31cdb599fdeedddec0fb3c Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Wed, 29 Apr 2026 09:38:48 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: adjust FIFO trigger threshold + to half FIFO size + +Set both TX and RX FIFO trigger thresholds (TFT/RFT) to 0xF (half of +the 32-entry FIFO) instead of 5. This provides better DMA efficiency +by allowing more data to accumulate before triggering a DMA request, +reducing the number of DMA transactions needed. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260429-k3-i2s-v1-3-2fe99db11ecb@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit 03dcb5b68a96b51157ec2d17042fa2f0106828ae) +Signed-off-by: Han Gao +--- + sound/soc/spacemit/k1_i2s.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c +index 331668b979fd..b48c57bede37 100644 +--- a/sound/soc/spacemit/k1_i2s.c ++++ b/sound/soc/spacemit/k1_i2s.c +@@ -93,8 +93,8 @@ static void spacemit_i2s_init(struct spacemit_i2s_dev *i2s) + u32 sscr_val, sspsp_val, ssfcr_val, ssrwt_val; + + sscr_val = SSCR_TRAIL | SSCR_FRF_PSP; +- ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 5) | +- FIELD_PREP(SSFCR_FIELD_RFT, 5) | ++ ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 0xF) | ++ FIELD_PREP(SSFCR_FIELD_RFT, 0xF) | + SSFCR_RSRE | SSFCR_TSRE; + ssrwt_val = SSRWT_RWOT; + sspsp_val = SSPSP_SFRMP; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0252-UPSTREAM-riscv-lib-add-strrchr-implementation.patch b/SPECS/linux-lts-kmhv2/0252-UPSTREAM-riscv-lib-add-strrchr-implementation.patch deleted file mode 100644 index bbb8905d30..0000000000 --- a/SPECS/linux-lts-kmhv2/0252-UPSTREAM-riscv-lib-add-strrchr-implementation.patch +++ /dev/null @@ -1,130 +0,0 @@ -From d06ce21328bc140c9a983924c52277ee37808254 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 252/467] UPSTREAM: riscv: lib: add strrchr() implementation - -Add an assembly implementation of strrchr() for RISC-V. - -This implementation minimizes instruction count and avoids unnecessary -memory access to the stack. The performance benefits are most visible -on small workloads (1-16 bytes) where the architectural savings in -function overhead outweigh the execution time of the scan loop. - -Benchmark results (QEMU TCG, rv64): - Length | Original (MB/s) | Optimized (MB/s) | Improvement - -------|-----------------|------------------|------------ - 1 B | 20 | 21 | +5.0% - 7 B | 111 | 120 | +8.1% - 16 B | 189 | 199 | +5.3% - 512 B | 361 | 382 | +5.8% - 4096 B | 388 | 391 | +0.8% - -Signed-off-by: Feng Jiang -Tested-by: Joel Stanley -Link: https://patch.msgid.link/20260130025018.172925-9-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit bef64bcb940269a503d12eb1bc180d1aa9adf74d) -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/string.h | 3 +++ - arch/riscv/lib/Makefile | 1 + - arch/riscv/lib/strrchr.S | 37 +++++++++++++++++++++++++++++++++ - arch/riscv/purgatory/Makefile | 5 ++++- - 4 files changed, 45 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/lib/strrchr.S - -diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h -index ca3ade82b124..764ffe8f6479 100644 ---- a/arch/riscv/include/asm/string.h -+++ b/arch/riscv/include/asm/string.h -@@ -34,6 +34,9 @@ extern asmlinkage __kernel_size_t strnlen(const char *, size_t); - - #define __HAVE_ARCH_STRCHR - extern asmlinkage char *strchr(const char *, int); -+ -+#define __HAVE_ARCH_STRRCHR -+extern asmlinkage char *strrchr(const char *, int); - #endif - - /* For those files which don't want to check by kasan. */ -diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile -index b7f804dce1c3..735d0b665536 100644 ---- a/arch/riscv/lib/Makefile -+++ b/arch/riscv/lib/Makefile -@@ -9,6 +9,7 @@ lib-y += strlen.o - lib-y += strncmp.o - lib-y += strnlen.o - lib-y += strchr.o -+lib-y += strrchr.o - endif - lib-y += csum.o - ifeq ($(CONFIG_MMU), y) -diff --git a/arch/riscv/lib/strrchr.S b/arch/riscv/lib/strrchr.S -new file mode 100644 -index 000000000000..ac58b20ca21d ---- /dev/null -+++ b/arch/riscv/lib/strrchr.S -@@ -0,0 +1,37 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* -+ * Copyright (C) 2025 Feng Jiang -+ */ -+ -+#include -+#include -+ -+/* char *strrchr(const char *s, int c) */ -+SYM_FUNC_START(strrchr) -+ /* -+ * Parameters -+ * a0 - The string to be searched -+ * a1 - The character to seaerch for -+ * -+ * Returns -+ * a0 - Address of last occurrence of 'c' or 0 -+ * -+ * Clobbers -+ * t0, t1 -+ */ -+ andi a1, a1, 0xff -+ mv t1, a0 -+ li a0, 0 -+1: -+ lbu t0, 0(t1) -+ bne t0, a1, 2f -+ mv a0, t1 -+2: -+ addi t1, t1, 1 -+ bnez t0, 1b -+ ret -+SYM_FUNC_END(strrchr) -+ -+SYM_FUNC_ALIAS_WEAK(__pi_strrchr, strrchr) -+EXPORT_SYMBOL(strrchr) -diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile -index e7b3d748c913..b0358a78f11a 100644 ---- a/arch/riscv/purgatory/Makefile -+++ b/arch/riscv/purgatory/Makefile -@@ -2,7 +2,7 @@ - - purgatory-y := purgatory.o sha256.o entry.o string.o ctype.o memcpy.o memset.o - ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) --purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o strchr.o -+purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o strchr.o strrchr.o - endif - - targets += $(purgatory-y) -@@ -38,6 +38,9 @@ $(obj)/strnlen.o: $(srctree)/arch/riscv/lib/strnlen.S FORCE - $(obj)/strchr.o: $(srctree)/arch/riscv/lib/strchr.S FORCE - $(call if_changed_rule,as_o_S) - -+$(obj)/strrchr.o: $(srctree)/arch/riscv/lib/strrchr.S FORCE -+ $(call if_changed_rule,as_o_S) -+ - CFLAGS_sha256.o := -D__DISABLE_EXPORTS -D__NO_FORTIFY - CFLAGS_string.o := -D__DISABLE_EXPORTS - CFLAGS_ctype.o := -D__DISABLE_EXPORTS --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0253-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch b/SPECS/linux-lts-kmhv2/0253-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch deleted file mode 100644 index 139a305f3e..0000000000 --- a/SPECS/linux-lts-kmhv2/0253-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 8d6883e557feae1df51a14f0a3008c5104978a75 Mon Sep 17 00:00:00 2001 -From: Vincent Guittot -Date: Fri, 21 Nov 2025 17:49:18 +0100 -Subject: [PATCH 253/467] UPSTREAM: PCI: dwc: Add register and bitfield - definitions - -Add register and bitfield definitions: - - - GEN3_RELATED_OFF_EQ_PHASE_2_3 field of GEN3_RELATED_OFF - - - Coherency control registers - -Signed-off-by: Vincent Guittot -Signed-off-by: Manivannan Sadhasivam -Signed-off-by: Bjorn Helgaas -Reviewed-by: Frank Li -Link: https://patch.msgid.link/20251121164920.2008569-3-vincent.guittot@linaro.org -(cherry picked from commit 045ad2c623d607f2c7720e2b8fcda675d96f7381) -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/pcie-designware.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h -index aa27211b68dd..295e113189b7 100644 ---- a/drivers/pci/controller/dwc/pcie-designware.h -+++ b/drivers/pci/controller/dwc/pcie-designware.h -@@ -123,6 +123,7 @@ - - #define GEN3_RELATED_OFF 0x890 - #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) -+#define GEN3_RELATED_OFF_EQ_PHASE_2_3 BIT(9) - #define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13) - #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) - #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 -@@ -140,6 +141,13 @@ - #define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA GENMASK(13, 10) - #define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA GENMASK(17, 14) - -+#define COHERENCY_CONTROL_1_OFF 0x8E0 -+#define CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK GENMASK(31, 2) -+#define CFG_MEMTYPE_VALUE BIT(0) -+ -+#define COHERENCY_CONTROL_2_OFF 0x8E4 -+#define COHERENCY_CONTROL_3_OFF 0x8E8 -+ - #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 - #define PORT_MLTI_UPCFG_SUPPORT BIT(7) - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch b/SPECS/linux-lts-kmhv2/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch new file mode 100644 index 0000000000..dbc1d4ed46 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch @@ -0,0 +1,43 @@ +From 42cd6879691919aaf3200276ed71a8c7f081bf8f Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 14 Oct 2025 13:10:28 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: reset: thead,th1520-reset: Remove + non-VO-subsystem resets + +Registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} belong to AP +reset controller, not the VO one which is documented as +"thead,th1520-reset" and is the only reset controller supported for +TH1520 for now. + +Let's remove the IDs, leaving them to be implemented by AP-subsystem +reset controller in the future. + +Fixes: 30e7573babdc ("dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller") +Signed-off-by: Yao Zi +Acked-by: Rob Herring (Arm) +Reviewed-by: Drew Fustini +Acked-by: Guo Ren +Signed-off-by: Philipp Zabel +(cherry picked from commit 5334eb9de76c74e24821aae89e111e27398b5add) +Signed-off-by: Han Gao +--- + include/dt-bindings/reset/thead,th1520-reset.h | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h +index ee799286c175..e51d6314d131 100644 +--- a/include/dt-bindings/reset/thead,th1520-reset.h ++++ b/include/dt-bindings/reset/thead,th1520-reset.h +@@ -9,9 +9,6 @@ + + #define TH1520_RESET_ID_GPU 0 + #define TH1520_RESET_ID_GPU_CLKGEN 1 +-#define TH1520_RESET_ID_NPU 2 +-#define TH1520_RESET_ID_WDT0 3 +-#define TH1520_RESET_ID_WDT1 4 + #define TH1520_RESET_ID_DPU_AHB 5 + #define TH1520_RESET_ID_DPU_AXI 6 + #define TH1520_RESET_ID_DPU_CORE 7 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0254-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch b/SPECS/linux-lts-kmhv2/0254-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch deleted file mode 100644 index 802aad400b..0000000000 --- a/SPECS/linux-lts-kmhv2/0254-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 0b98034970a41ebd870d94873762f355265308b5 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Wed, 29 Apr 2026 09:38:47 +0800 -Subject: [PATCH 254/467] UPSTREAM: ASoC: spacemit: move hw constraints from - hw_params to startup - -Hardware constraints should be applied in the startup callback rather -than hw_params, as hw_params may be called too late for the constraints -to take effect properly. - -Move the channel count and format constraints for I2S and DSP_A/DSP_B -modes into a new startup callback. This also tightens the I2S mode -channel constraint from 1-2 to exactly 2, matching the actual hardware -behavior. - -Signed-off-by: Troy Mitchell -Link: https://patch.msgid.link/20260429-k3-i2s-v1-2-2fe99db11ecb@linux.spacemit.com -Signed-off-by: Mark Brown -(cherry picked from commit 6b4afbaaa342eaa52172e0be5ef8d1fcbf9ff460) -Signed-off-by: Han Gao ---- - sound/soc/spacemit/k1_i2s.c | 45 ++++++++++++++++++++++++++----------- - 1 file changed, 32 insertions(+), 13 deletions(-) - -diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c -index abc439b53e3d..331668b979fd 100644 ---- a/sound/soc/spacemit/k1_i2s.c -+++ b/sound/soc/spacemit/k1_i2s.c -@@ -106,6 +106,37 @@ static void spacemit_i2s_init(struct spacemit_i2s_dev *i2s) - writel(0, i2s->base + SSINTEN); - } - -+static int spacemit_i2s_startup(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct spacemit_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); -+ -+ switch (i2s->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_I2S: -+ snd_pcm_hw_constraint_minmax(substream->runtime, -+ SNDRV_PCM_HW_PARAM_CHANNELS, -+ 2, 2); -+ snd_pcm_hw_constraint_mask64(substream->runtime, -+ SNDRV_PCM_HW_PARAM_FORMAT, -+ SNDRV_PCM_FMTBIT_S16_LE); -+ break; -+ case SND_SOC_DAIFMT_DSP_A: -+ case SND_SOC_DAIFMT_DSP_B: -+ snd_pcm_hw_constraint_minmax(substream->runtime, -+ SNDRV_PCM_HW_PARAM_CHANNELS, -+ 1, 1); -+ snd_pcm_hw_constraint_mask64(substream->runtime, -+ SNDRV_PCM_HW_PARAM_FORMAT, -+ SNDRV_PCM_FMTBIT_S32_LE); -+ break; -+ default: -+ dev_dbg(i2s->dev, "unexpected format type"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ - static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, - struct snd_soc_dai *dai) -@@ -157,22 +188,9 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, - dma_data->maxburst = 32; - dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - } -- -- snd_pcm_hw_constraint_minmax(substream->runtime, -- SNDRV_PCM_HW_PARAM_CHANNELS, -- 1, 2); -- snd_pcm_hw_constraint_mask64(substream->runtime, -- SNDRV_PCM_HW_PARAM_FORMAT, -- SNDRV_PCM_FMTBIT_S16_LE); - break; - case SND_SOC_DAIFMT_DSP_A: - case SND_SOC_DAIFMT_DSP_B: -- snd_pcm_hw_constraint_minmax(substream->runtime, -- SNDRV_PCM_HW_PARAM_CHANNELS, -- 1, 1); -- snd_pcm_hw_constraint_mask64(substream->runtime, -- SNDRV_PCM_HW_PARAM_FORMAT, -- SNDRV_PCM_FMTBIT_S32_LE); - break; - default: - dev_dbg(i2s->dev, "unexpected format type"); -@@ -303,6 +321,7 @@ static int spacemit_i2s_dai_remove(struct snd_soc_dai *dai) - static const struct snd_soc_dai_ops spacemit_i2s_dai_ops = { - .probe = spacemit_i2s_dai_probe, - .remove = spacemit_i2s_dai_remove, -+ .startup = spacemit_i2s_startup, - .hw_params = spacemit_i2s_hw_params, - .set_sysclk = spacemit_i2s_set_sysclk, - .set_fmt = spacemit_i2s_set_fmt, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch b/SPECS/linux-lts-kmhv2/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch new file mode 100644 index 0000000000..20d4cb4ce7 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch @@ -0,0 +1,277 @@ +From 729fb80f40c116319af3f00f273cb56718995e42 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 14 Oct 2025 13:10:29 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: reset: thead,th1520-reset: Add + controllers for more subsys + +TH1520 SoC is divided into several subsystems, most of them have +distinct reset controllers. Let's document reset controllers other than +the one for VO subsystem and IDs for their reset signals. + +Signed-off-by: Yao Zi +Acked-by: Rob Herring (Arm) +Reviewed-by: Drew Fustini +Acked-by: Guo Ren +Signed-off-by: Philipp Zabel +(cherry picked from commit a35ac6f3bdb135debc8e1ff599d0009bc64dc329) +Signed-off-by: Han Gao +--- + .../bindings/reset/thead,th1520-reset.yaml | 8 +- + .../dt-bindings/reset/thead,th1520-reset.h | 216 ++++++++++++++++++ + 2 files changed, 223 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml +index f2e91d0add7a..7b5053c177fe 100644 +--- a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml ++++ b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml +@@ -16,7 +16,13 @@ maintainers: + properties: + compatible: + enum: +- - thead,th1520-reset ++ - thead,th1520-reset # Reset controller for VO subsystem ++ - thead,th1520-reset-ao ++ - thead,th1520-reset-ap ++ - thead,th1520-reset-dsp ++ - thead,th1520-reset-misc ++ - thead,th1520-reset-vi ++ - thead,th1520-reset-vp + + reg: + maxItems: 1 +diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h +index e51d6314d131..ba6805b6b12a 100644 +--- a/include/dt-bindings/reset/thead,th1520-reset.h ++++ b/include/dt-bindings/reset/thead,th1520-reset.h +@@ -7,6 +7,200 @@ + #ifndef _DT_BINDINGS_TH1520_RESET_H + #define _DT_BINDINGS_TH1520_RESET_H + ++/* AO Subsystem */ ++#define TH1520_RESET_ID_SYSTEM 0 ++#define TH1520_RESET_ID_RTC_APB 1 ++#define TH1520_RESET_ID_RTC_REF 2 ++#define TH1520_RESET_ID_AOGPIO_DB 3 ++#define TH1520_RESET_ID_AOGPIO_APB 4 ++#define TH1520_RESET_ID_AOI2C_APB 5 ++#define TH1520_RESET_ID_PVT_APB 6 ++#define TH1520_RESET_ID_E902_CORE 7 ++#define TH1520_RESET_ID_E902_HAD 8 ++#define TH1520_RESET_ID_AOTIMER_APB 9 ++#define TH1520_RESET_ID_AOTIMER_CORE 10 ++#define TH1520_RESET_ID_AOWDT_APB 11 ++#define TH1520_RESET_ID_APSYS 12 ++#define TH1520_RESET_ID_NPUSYS 13 ++#define TH1520_RESET_ID_DDRSYS 14 ++#define TH1520_RESET_ID_AXI_AP2CP 15 ++#define TH1520_RESET_ID_AXI_CP2AP 16 ++#define TH1520_RESET_ID_AXI_CP2SRAM 17 ++#define TH1520_RESET_ID_AUDSYS_CORE 18 ++#define TH1520_RESET_ID_AUDSYS_IOPMP 19 ++#define TH1520_RESET_ID_AUDSYS 20 ++#define TH1520_RESET_ID_DSP0 21 ++#define TH1520_RESET_ID_DSP1 22 ++#define TH1520_RESET_ID_GPU_MODULE 23 ++#define TH1520_RESET_ID_VDEC 24 ++#define TH1520_RESET_ID_VENC 25 ++#define TH1520_RESET_ID_ADC_APB 26 ++#define TH1520_RESET_ID_AUDGPIO_DB 27 ++#define TH1520_RESET_ID_AUDGPIO_APB 28 ++#define TH1520_RESET_ID_AOUART_IF 29 ++#define TH1520_RESET_ID_AOUART_APB 30 ++#define TH1520_RESET_ID_SRAM_AXI_P0 31 ++#define TH1520_RESET_ID_SRAM_AXI_P1 32 ++#define TH1520_RESET_ID_SRAM_AXI_P2 33 ++#define TH1520_RESET_ID_SRAM_AXI_P3 34 ++#define TH1520_RESET_ID_SRAM_AXI_P4 35 ++#define TH1520_RESET_ID_SRAM_AXI_CORE 36 ++#define TH1520_RESET_ID_SE 37 ++ ++/* AP Subsystem */ ++#define TH1520_RESET_ID_BROM 0 ++#define TH1520_RESET_ID_C910_TOP 1 ++#define TH1520_RESET_ID_NPU 2 ++#define TH1520_RESET_ID_WDT0 3 ++#define TH1520_RESET_ID_WDT1 4 ++#define TH1520_RESET_ID_C910_C0 5 ++#define TH1520_RESET_ID_C910_C1 6 ++#define TH1520_RESET_ID_C910_C2 7 ++#define TH1520_RESET_ID_C910_C3 8 ++#define TH1520_RESET_ID_CHIP_DBG_CORE 9 ++#define TH1520_RESET_ID_CHIP_DBG_AXI 10 ++#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI 11 ++#define TH1520_RESET_ID_AXI4_CPUSYS2_APB 12 ++#define TH1520_RESET_ID_X2H_CPUSYS 13 ++#define TH1520_RESET_ID_AHB2_CPUSYS 14 ++#define TH1520_RESET_ID_APB3_CPUSYS 15 ++#define TH1520_RESET_ID_MBOX0_APB 16 ++#define TH1520_RESET_ID_MBOX1_APB 17 ++#define TH1520_RESET_ID_MBOX2_APB 18 ++#define TH1520_RESET_ID_MBOX3_APB 19 ++#define TH1520_RESET_ID_TIMER0_APB 20 ++#define TH1520_RESET_ID_TIMER0_CORE 21 ++#define TH1520_RESET_ID_TIMER1_APB 22 ++#define TH1520_RESET_ID_TIMER1_CORE 23 ++#define TH1520_RESET_ID_PERISYS_AHB 24 ++#define TH1520_RESET_ID_PERISYS_APB1 25 ++#define TH1520_RESET_ID_PERISYS_APB2 26 ++#define TH1520_RESET_ID_GMAC0_APB 27 ++#define TH1520_RESET_ID_GMAC0_AHB 28 ++#define TH1520_RESET_ID_GMAC0_CLKGEN 29 ++#define TH1520_RESET_ID_GMAC0_AXI 30 ++#define TH1520_RESET_ID_UART0_APB 31 ++#define TH1520_RESET_ID_UART0_IF 32 ++#define TH1520_RESET_ID_UART1_APB 33 ++#define TH1520_RESET_ID_UART1_IF 34 ++#define TH1520_RESET_ID_UART2_APB 35 ++#define TH1520_RESET_ID_UART2_IF 36 ++#define TH1520_RESET_ID_UART3_APB 37 ++#define TH1520_RESET_ID_UART3_IF 38 ++#define TH1520_RESET_ID_UART4_APB 39 ++#define TH1520_RESET_ID_UART4_IF 40 ++#define TH1520_RESET_ID_UART5_APB 41 ++#define TH1520_RESET_ID_UART5_IF 42 ++#define TH1520_RESET_ID_QSPI0_IF 43 ++#define TH1520_RESET_ID_QSPI0_APB 44 ++#define TH1520_RESET_ID_QSPI1_IF 45 ++#define TH1520_RESET_ID_QSPI1_APB 46 ++#define TH1520_RESET_ID_SPI_IF 47 ++#define TH1520_RESET_ID_SPI_APB 48 ++#define TH1520_RESET_ID_I2C0_APB 49 ++#define TH1520_RESET_ID_I2C0_CORE 50 ++#define TH1520_RESET_ID_I2C1_APB 51 ++#define TH1520_RESET_ID_I2C1_CORE 52 ++#define TH1520_RESET_ID_I2C2_APB 53 ++#define TH1520_RESET_ID_I2C2_CORE 54 ++#define TH1520_RESET_ID_I2C3_APB 55 ++#define TH1520_RESET_ID_I2C3_CORE 56 ++#define TH1520_RESET_ID_I2C4_APB 57 ++#define TH1520_RESET_ID_I2C4_CORE 58 ++#define TH1520_RESET_ID_I2C5_APB 59 ++#define TH1520_RESET_ID_I2C5_CORE 60 ++#define TH1520_RESET_ID_GPIO0_DB 61 ++#define TH1520_RESET_ID_GPIO0_APB 62 ++#define TH1520_RESET_ID_GPIO1_DB 63 ++#define TH1520_RESET_ID_GPIO1_APB 64 ++#define TH1520_RESET_ID_GPIO2_DB 65 ++#define TH1520_RESET_ID_GPIO2_APB 66 ++#define TH1520_RESET_ID_PWM_COUNTER 67 ++#define TH1520_RESET_ID_PWM_APB 68 ++#define TH1520_RESET_ID_PADCTRL0_APB 69 ++#define TH1520_RESET_ID_CPU2PERI_X2H 70 ++#define TH1520_RESET_ID_CPU2AON_X2H 71 ++#define TH1520_RESET_ID_AON2CPU_A2X 72 ++#define TH1520_RESET_ID_NPUSYS_AXI 73 ++#define TH1520_RESET_ID_NPUSYS_AXI_APB 74 ++#define TH1520_RESET_ID_CPU2VP_X2P 75 ++#define TH1520_RESET_ID_CPU2VI_X2H 76 ++#define TH1520_RESET_ID_BMU_AXI 77 ++#define TH1520_RESET_ID_BMU_APB 78 ++#define TH1520_RESET_ID_DMAC_CPUSYS_AXI 79 ++#define TH1520_RESET_ID_DMAC_CPUSYS_AHB 80 ++#define TH1520_RESET_ID_SPINLOCK 81 ++#define TH1520_RESET_ID_CFG2TEE 82 ++#define TH1520_RESET_ID_DSMART 83 ++#define TH1520_RESET_ID_GPIO3_DB 84 ++#define TH1520_RESET_ID_GPIO3_APB 85 ++#define TH1520_RESET_ID_PERI_I2S 86 ++#define TH1520_RESET_ID_PERI_APB3 87 ++#define TH1520_RESET_ID_PERI2PERI1_APB 88 ++#define TH1520_RESET_ID_VPSYS_APB 89 ++#define TH1520_RESET_ID_PERISYS_APB4 90 ++#define TH1520_RESET_ID_GMAC1_APB 91 ++#define TH1520_RESET_ID_GMAC1_AHB 92 ++#define TH1520_RESET_ID_GMAC1_CLKGEN 93 ++#define TH1520_RESET_ID_GMAC1_AXI 94 ++#define TH1520_RESET_ID_GMAC_AXI 95 ++#define TH1520_RESET_ID_GMAC_AXI_APB 96 ++#define TH1520_RESET_ID_PADCTRL1_APB 97 ++#define TH1520_RESET_ID_VOSYS_AXI 98 ++#define TH1520_RESET_ID_VOSYS_AXI_APB 99 ++#define TH1520_RESET_ID_VOSYS_AXI_X2X 100 ++#define TH1520_RESET_ID_MISC2VP_X2X 101 ++#define TH1520_RESET_ID_DSPSYS 102 ++#define TH1520_RESET_ID_VISYS 103 ++#define TH1520_RESET_ID_VOSYS 104 ++#define TH1520_RESET_ID_VPSYS 105 ++ ++/* DSP Subsystem */ ++#define TH1520_RESET_ID_X2X_DSP1 0 ++#define TH1520_RESET_ID_X2X_DSP0 1 ++#define TH1520_RESET_ID_X2X_SLAVE_DSP1 2 ++#define TH1520_RESET_ID_X2X_SLAVE_DSP0 3 ++#define TH1520_RESET_ID_DSP0_CORE 4 ++#define TH1520_RESET_ID_DSP0_DEBUG 5 ++#define TH1520_RESET_ID_DSP0_APB 6 ++#define TH1520_RESET_ID_DSP1_CORE 7 ++#define TH1520_RESET_ID_DSP1_DEBUG 8 ++#define TH1520_RESET_ID_DSP1_APB 9 ++#define TH1520_RESET_ID_DSPSYS_APB 10 ++#define TH1520_RESET_ID_AXI4_DSPSYS_SLV 11 ++#define TH1520_RESET_ID_AXI4_DSPSYS 12 ++#define TH1520_RESET_ID_AXI4_DSP_RS 13 ++ ++/* MISC Subsystem */ ++#define TH1520_RESET_ID_EMMC_SDIO_CLKGEN 0 ++#define TH1520_RESET_ID_EMMC 1 ++#define TH1520_RESET_ID_MISCSYS_AXI 2 ++#define TH1520_RESET_ID_MISCSYS_AXI_APB 3 ++#define TH1520_RESET_ID_SDIO0 4 ++#define TH1520_RESET_ID_SDIO1 5 ++#define TH1520_RESET_ID_USB3_APB 6 ++#define TH1520_RESET_ID_USB3_PHY 7 ++#define TH1520_RESET_ID_USB3_VCC 8 ++ ++/* VI Subsystem */ ++#define TH1520_RESET_ID_ISP0 0 ++#define TH1520_RESET_ID_ISP1 1 ++#define TH1520_RESET_ID_CSI0_APB 2 ++#define TH1520_RESET_ID_CSI1_APB 3 ++#define TH1520_RESET_ID_CSI2_APB 4 ++#define TH1520_RESET_ID_MIPI_FIFO 5 ++#define TH1520_RESET_ID_ISP_VENC_APB 6 ++#define TH1520_RESET_ID_VIPRE_APB 7 ++#define TH1520_RESET_ID_VIPRE_AXI 8 ++#define TH1520_RESET_ID_DW200_APB 9 ++#define TH1520_RESET_ID_VISYS3_AXI 10 ++#define TH1520_RESET_ID_VISYS2_AXI 11 ++#define TH1520_RESET_ID_VISYS1_AXI 12 ++#define TH1520_RESET_ID_VISYS_AXI 13 ++#define TH1520_RESET_ID_VISYS_APB 14 ++#define TH1520_RESET_ID_ISP_VENC_AXI 15 ++ ++/* VO Subsystem */ + #define TH1520_RESET_ID_GPU 0 + #define TH1520_RESET_ID_GPU_CLKGEN 1 + #define TH1520_RESET_ID_DPU_AHB 5 +@@ -16,5 +210,27 @@ + #define TH1520_RESET_ID_DSI1_APB 9 + #define TH1520_RESET_ID_HDMI 10 + #define TH1520_RESET_ID_HDMI_APB 11 ++#define TH1520_RESET_ID_VOAXI 12 ++#define TH1520_RESET_ID_VOAXI_APB 13 ++#define TH1520_RESET_ID_X2H_DPU_AXI 14 ++#define TH1520_RESET_ID_X2H_DPU_AHB 15 ++#define TH1520_RESET_ID_X2H_DPU1_AXI 16 ++#define TH1520_RESET_ID_X2H_DPU1_AHB 17 ++ ++/* VP Subsystem */ ++#define TH1520_RESET_ID_VPSYS_AXI_APB 0 ++#define TH1520_RESET_ID_VPSYS_AXI 1 ++#define TH1520_RESET_ID_FCE_APB 2 ++#define TH1520_RESET_ID_FCE_CORE 3 ++#define TH1520_RESET_ID_FCE_X2X_MASTER 4 ++#define TH1520_RESET_ID_FCE_X2X_SLAVE 5 ++#define TH1520_RESET_ID_G2D_APB 6 ++#define TH1520_RESET_ID_G2D_ACLK 7 ++#define TH1520_RESET_ID_G2D_CORE 8 ++#define TH1520_RESET_ID_VDEC_APB 9 ++#define TH1520_RESET_ID_VDEC_ACLK 10 ++#define TH1520_RESET_ID_VDEC_CORE 11 ++#define TH1520_RESET_ID_VENC_APB 12 ++#define TH1520_RESET_ID_VENC_CORE 13 + + #endif /* _DT_BINDINGS_TH1520_RESET_H */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0255-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch b/SPECS/linux-lts-kmhv2/0255-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch deleted file mode 100644 index 1e9bf3e407..0000000000 --- a/SPECS/linux-lts-kmhv2/0255-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch +++ /dev/null @@ -1,38 +0,0 @@ -From ef5e4c0292bbb0c8ac2209001b6adcdb0ee1fc37 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Wed, 29 Apr 2026 09:38:48 +0800 -Subject: [PATCH 255/467] UPSTREAM: ASoC: spacemit: adjust FIFO trigger - threshold to half FIFO size - -Set both TX and RX FIFO trigger thresholds (TFT/RFT) to 0xF (half of -the 32-entry FIFO) instead of 5. This provides better DMA efficiency -by allowing more data to accumulate before triggering a DMA request, -reducing the number of DMA transactions needed. - -Signed-off-by: Troy Mitchell -Link: https://patch.msgid.link/20260429-k3-i2s-v1-3-2fe99db11ecb@linux.spacemit.com -Signed-off-by: Mark Brown -(cherry picked from commit 03dcb5b68a96b51157ec2d17042fa2f0106828ae) -Signed-off-by: Han Gao ---- - sound/soc/spacemit/k1_i2s.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c -index 331668b979fd..b48c57bede37 100644 ---- a/sound/soc/spacemit/k1_i2s.c -+++ b/sound/soc/spacemit/k1_i2s.c -@@ -93,8 +93,8 @@ static void spacemit_i2s_init(struct spacemit_i2s_dev *i2s) - u32 sscr_val, sspsp_val, ssfcr_val, ssrwt_val; - - sscr_val = SSCR_TRAIL | SSCR_FRF_PSP; -- ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 5) | -- FIELD_PREP(SSFCR_FIELD_RFT, 5) | -+ ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 0xF) | -+ FIELD_PREP(SSFCR_FIELD_RFT, 0xF) | - SSFCR_RSRE | SSFCR_TSRE; - ssrwt_val = SSRWT_RWOT; - sspsp_val = SSPSP_SFRMP; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch b/SPECS/linux-lts-kmhv2/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch new file mode 100644 index 0000000000..46e0cf3948 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch @@ -0,0 +1,124 @@ +From 822ec8590fdd9c6e8152814eca6d64a56660f962 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 14 Oct 2025 13:10:30 +0000 +Subject: [RUYI PATCH] UPSTREAM: reset: th1520: Prepare for supporting multiple + controllers + +TH1520 SoC is divided into several subsystems, shipping distinct reset +controllers with similar control logic. Let's make reset signal mapping +a data structure specific to one compatible to prepare for introduction +of more reset controllers in the future. + +Signed-off-by: Yao Zi +Acked-by: Guo Ren +Reviewed-by: Drew Fustini +Signed-off-by: Philipp Zabel +(cherry picked from commit 0040d9eac391bacefcb0c748cf32c8fe5900b13b) +Signed-off-by: Han Gao +--- + drivers/reset/reset-th1520.c | 42 +++++++++++++++++++++++++----------- + 1 file changed, 30 insertions(+), 12 deletions(-) + +diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c +index 14d964a9c6b6..2b65a95ed021 100644 +--- a/drivers/reset/reset-th1520.c ++++ b/drivers/reset/reset-th1520.c +@@ -29,14 +29,20 @@ + #define TH1520_HDMI_SW_MAIN_RST BIT(0) + #define TH1520_HDMI_SW_PRST BIT(1) + ++struct th1520_reset_map { ++ u32 bit; ++ u32 reg; ++}; ++ + struct th1520_reset_priv { + struct reset_controller_dev rcdev; + struct regmap *map; ++ const struct th1520_reset_map *resets; + }; + +-struct th1520_reset_map { +- u32 bit; +- u32 reg; ++struct th1520_reset_data { ++ const struct th1520_reset_map *resets; ++ size_t num; + }; + + static const struct th1520_reset_map th1520_resets[] = { +@@ -90,7 +96,7 @@ static int th1520_reset_assert(struct reset_controller_dev *rcdev, + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); + const struct th1520_reset_map *reset; + +- reset = &th1520_resets[id]; ++ reset = &priv->resets[id]; + + return regmap_update_bits(priv->map, reset->reg, reset->bit, 0); + } +@@ -101,7 +107,7 @@ static int th1520_reset_deassert(struct reset_controller_dev *rcdev, + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); + const struct th1520_reset_map *reset; + +- reset = &th1520_resets[id]; ++ reset = &priv->resets[id]; + + return regmap_update_bits(priv->map, reset->reg, reset->bit, + reset->bit); +@@ -120,11 +126,14 @@ static const struct regmap_config th1520_reset_regmap_config = { + + static int th1520_reset_probe(struct platform_device *pdev) + { ++ const struct th1520_reset_data *data; + struct device *dev = &pdev->dev; + struct th1520_reset_priv *priv; + void __iomem *base; + int ret; + ++ data = device_get_match_data(dev); ++ + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; +@@ -138,22 +147,31 @@ static int th1520_reset_probe(struct platform_device *pdev) + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + +- /* Initialize GPU resets to asserted state */ +- ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, +- TH1520_GPU_RST_CFG_MASK, 0); +- if (ret) +- return ret; ++ if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) { ++ /* Initialize GPU resets to asserted state */ ++ ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, ++ TH1520_GPU_RST_CFG_MASK, 0); ++ if (ret) ++ return ret; ++ } + + priv->rcdev.owner = THIS_MODULE; +- priv->rcdev.nr_resets = ARRAY_SIZE(th1520_resets); ++ priv->rcdev.nr_resets = data->num; + priv->rcdev.ops = &th1520_reset_ops; + priv->rcdev.of_node = dev->of_node; + ++ priv->resets = data->resets; ++ + return devm_reset_controller_register(dev, &priv->rcdev); + } + ++static const struct th1520_reset_data th1520_reset_data = { ++ .resets = th1520_resets, ++ .num = ARRAY_SIZE(th1520_resets), ++}; ++ + static const struct of_device_id th1520_reset_match[] = { +- { .compatible = "thead,th1520-reset" }, ++ { .compatible = "thead,th1520-reset", .data = &th1520_reset_data }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, th1520_reset_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0256-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch b/SPECS/linux-lts-kmhv2/0256-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch deleted file mode 100644 index 069e0e55c6..0000000000 --- a/SPECS/linux-lts-kmhv2/0256-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 70c964d224ef054526b245c614230ab634b0bde7 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Tue, 14 Oct 2025 13:10:28 +0000 -Subject: [PATCH 256/467] UPSTREAM: dt-bindings: reset: thead,th1520-reset: - Remove non-VO-subsystem resets - -Registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} belong to AP -reset controller, not the VO one which is documented as -"thead,th1520-reset" and is the only reset controller supported for -TH1520 for now. - -Let's remove the IDs, leaving them to be implemented by AP-subsystem -reset controller in the future. - -Fixes: 30e7573babdc ("dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller") -Signed-off-by: Yao Zi -Acked-by: Rob Herring (Arm) -Reviewed-by: Drew Fustini -Acked-by: Guo Ren -Signed-off-by: Philipp Zabel -(cherry picked from commit 5334eb9de76c74e24821aae89e111e27398b5add) -Signed-off-by: Han Gao ---- - include/dt-bindings/reset/thead,th1520-reset.h | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h -index ee799286c175..e51d6314d131 100644 ---- a/include/dt-bindings/reset/thead,th1520-reset.h -+++ b/include/dt-bindings/reset/thead,th1520-reset.h -@@ -9,9 +9,6 @@ - - #define TH1520_RESET_ID_GPU 0 - #define TH1520_RESET_ID_GPU_CLKGEN 1 --#define TH1520_RESET_ID_NPU 2 --#define TH1520_RESET_ID_WDT0 3 --#define TH1520_RESET_ID_WDT1 4 - #define TH1520_RESET_ID_DPU_AHB 5 - #define TH1520_RESET_ID_DPU_AXI 6 - #define TH1520_RESET_ID_DPU_CORE 7 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch b/SPECS/linux-lts-kmhv2/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch new file mode 100644 index 0000000000..7a6c0e9f96 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch @@ -0,0 +1,856 @@ +From 34aaa4adc6171c1a972e81edbb9861406d7dfa83 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 14 Oct 2025 13:10:31 +0000 +Subject: [RUYI PATCH] UPSTREAM: reset: th1520: Support reset controllers in + more subsystems + +Introduce reset controllers for AP, MISC, VI, VP and DSP subsystems and +add their reset signal mappings. + +Signed-off-by: Yao Zi +Reviewed-by: Drew Fustini +Acked-by: Guo Ren +Signed-off-by: Philipp Zabel +(cherry picked from commit da91533c2b7a569b272b8271f0b2c407f86407ed) +Signed-off-by: Han Gao +--- + drivers/reset/reset-th1520.c | 793 +++++++++++++++++++++++++++++++++++ + 1 file changed, 793 insertions(+) + +diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c +index 2b65a95ed021..fd32e991c4cb 100644 +--- a/drivers/reset/reset-th1520.c ++++ b/drivers/reset/reset-th1520.c +@@ -11,6 +11,85 @@ + + #include + ++ /* register offset in RSTGEN_R */ ++#define TH1520_BROM_RST_CFG 0x0 ++#define TH1520_C910_RST_CFG 0x4 ++#define TH1520_CHIP_DBG_RST_CFG 0xc ++#define TH1520_AXI4_CPUSYS2_RST_CFG 0x10 ++#define TH1520_X2H_CPUSYS_RST_CFG 0x18 ++#define TH1520_AHB2_CPUSYS_RST_CFG 0x1c ++#define TH1520_APB3_CPUSYS_RST_CFG 0x20 ++#define TH1520_MBOX0_RST_CFG 0x24 ++#define TH1520_MBOX1_RST_CFG 0x28 ++#define TH1520_MBOX2_RST_CFG 0x2c ++#define TH1520_MBOX3_RST_CFG 0x30 ++#define TH1520_WDT0_RST_CFG 0x34 ++#define TH1520_WDT1_RST_CFG 0x38 ++#define TH1520_TIMER0_RST_CFG 0x3c ++#define TH1520_TIMER1_RST_CFG 0x40 ++#define TH1520_PERISYS_AHB_RST_CFG 0x44 ++#define TH1520_PERISYS_APB1_RST_CFG 0x48 ++#define TH1520_PERISYS_APB2_RST_CFG 0x4c ++#define TH1520_GMAC0_RST_CFG 0x68 ++#define TH1520_UART0_RST_CFG 0x70 ++#define TH1520_UART1_RST_CFG 0x74 ++#define TH1520_UART2_RST_CFG 0x78 ++#define TH1520_UART3_RST_CFG 0x7c ++#define TH1520_UART4_RST_CFG 0x80 ++#define TH1520_UART5_RST_CFG 0x84 ++#define TH1520_QSPI0_RST_CFG 0x8c ++#define TH1520_QSPI1_RST_CFG 0x90 ++#define TH1520_SPI_RST_CFG 0x94 ++#define TH1520_I2C0_RST_CFG 0x98 ++#define TH1520_I2C1_RST_CFG 0x9c ++#define TH1520_I2C2_RST_CFG 0xa0 ++#define TH1520_I2C3_RST_CFG 0xa4 ++#define TH1520_I2C4_RST_CFG 0xa8 ++#define TH1520_I2C5_RST_CFG 0xac ++#define TH1520_GPIO0_RST_CFG 0xb0 ++#define TH1520_GPIO1_RST_CFG 0xb4 ++#define TH1520_GPIO2_RST_CFG 0xb8 ++#define TH1520_PWM_RST_CFG 0xc0 ++#define TH1520_PADCTRL0_APSYS_RST_CFG 0xc4 ++#define TH1520_CPU2PERI_X2H_RST_CFG 0xcc ++#define TH1520_CPU2AON_X2H_RST_CFG 0xe4 ++#define TH1520_AON2CPU_A2X_RST_CFG 0xfc ++#define TH1520_NPUSYS_AXI_RST_CFG 0x128 ++#define TH1520_CPU2VP_X2P_RST_CFG 0x12c ++#define TH1520_CPU2VI_X2H_RST_CFG 0x138 ++#define TH1520_BMU_C910_RST_CFG 0x148 ++#define TH1520_DMAC_CPUSYS_RST_CFG 0x14c ++#define TH1520_SPINLOCK_RST_CFG 0x178 ++#define TH1520_CFG2TEE_X2H_RST_CFG 0x188 ++#define TH1520_DSMART_RST_CFG 0x18c ++#define TH1520_GPIO3_RST_CFG 0x1a8 ++#define TH1520_I2S_RST_CFG 0x1ac ++#define TH1520_IMG_NNA_RST_CFG 0x1b0 ++#define TH1520_PERI_APB3_RST_CFG 0x1dc ++#define TH1520_VP_SUBSYS_RST_CFG 0x1ec ++#define TH1520_PERISYS_APB4_RST_CFG 0x1f8 ++#define TH1520_GMAC1_RST_CFG 0x204 ++#define TH1520_GMAC_AXI_RST_CFG 0x208 ++#define TH1520_PADCTRL1_APSYS_RST_CFG 0x20c ++#define TH1520_VOSYS_AXI_RST_CFG 0x210 ++#define TH1520_VOSYS_X2X_RST_CFG 0x214 ++#define TH1520_MISC2VP_X2X_RST_CFG 0x218 ++#define TH1520_SUBSYS_RST_CFG 0x220 ++ ++ /* register offset in DSP_REGMAP */ ++#define TH1520_DSPSYS_RST_CFG 0x0 ++ ++ /* register offset in MISCSYS_REGMAP */ ++#define TH1520_EMMC_RST_CFG 0x0 ++#define TH1520_MISCSYS_AXI_RST_CFG 0x8 ++#define TH1520_SDIO0_RST_CFG 0xc ++#define TH1520_SDIO1_RST_CFG 0x10 ++#define TH1520_USB3_DRD_RST_CFG 0x14 ++ ++ /* register offset in VISYS_REGMAP */ ++#define TH1520_VISYS_RST_CFG 0x0 ++#define TH1520_VISYS_2_RST_CFG 0x4 ++ + /* register offset in VOSYS_REGMAP */ + #define TH1520_GPU_RST_CFG 0x0 + #define TH1520_GPU_RST_CFG_MASK GENMASK(1, 0) +@@ -18,6 +97,8 @@ + #define TH1520_DSI0_RST_CFG 0x8 + #define TH1520_DSI1_RST_CFG 0xc + #define TH1520_HDMI_RST_CFG 0x14 ++#define TH1520_AXI4_VO_DW_AXI_RST_CFG 0x18 ++#define TH1520_X2H_X4_VOSYS_DW_RST_CFG 0x20 + + /* register values */ + #define TH1520_GPU_SW_GPU_RST BIT(0) +@@ -29,6 +110,13 @@ + #define TH1520_HDMI_SW_MAIN_RST BIT(0) + #define TH1520_HDMI_SW_PRST BIT(1) + ++ /* register offset in VPSYS_REGMAP */ ++#define TH1520_AXIBUS_RST_CFG 0x0 ++#define TH1520_FCE_RST_CFG 0x4 ++#define TH1520_G2D_RST_CFG 0x8 ++#define TH1520_VDEC_RST_CFG 0xc ++#define TH1520_VENC_RST_CFG 0x10 ++ + struct th1520_reset_map { + u32 bit; + u32 reg; +@@ -82,6 +170,681 @@ static const struct th1520_reset_map th1520_resets[] = { + .bit = TH1520_HDMI_SW_PRST, + .reg = TH1520_HDMI_RST_CFG, + }, ++ [TH1520_RESET_ID_VOAXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VOAXI_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2H_DPU_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2H_DPU_AHB] = { ++ .bit = BIT(1), ++ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2H_DPU1_AXI] = { ++ .bit = BIT(2), ++ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2H_DPU1_AHB] = { ++ .bit = BIT(3), ++ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, ++ }, ++}; ++ ++static const struct th1520_reset_map th1520_ap_resets[] = { ++ [TH1520_RESET_ID_BROM] = { ++ .bit = BIT(0), ++ .reg = TH1520_BROM_RST_CFG, ++ }, ++ [TH1520_RESET_ID_C910_TOP] = { ++ .bit = BIT(0), ++ .reg = TH1520_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_NPU] = { ++ .bit = BIT(0), ++ .reg = TH1520_IMG_NNA_RST_CFG, ++ }, ++ [TH1520_RESET_ID_WDT0] = { ++ .bit = BIT(0), ++ .reg = TH1520_WDT0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_WDT1] = { ++ .bit = BIT(0), ++ .reg = TH1520_WDT1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_C910_C0] = { ++ .bit = BIT(1), ++ .reg = TH1520_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_C910_C1] = { ++ .bit = BIT(2), ++ .reg = TH1520_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_C910_C2] = { ++ .bit = BIT(3), ++ .reg = TH1520_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_C910_C3] = { ++ .bit = BIT(4), ++ .reg = TH1520_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CHIP_DBG_CORE] = { ++ .bit = BIT(0), ++ .reg = TH1520_CHIP_DBG_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CHIP_DBG_AXI] = { ++ .bit = BIT(1), ++ .reg = TH1520_CHIP_DBG_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AXI4_CPUSYS2_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_AXI4_CPUSYS2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AXI4_CPUSYS2_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_AXI4_CPUSYS2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2H_CPUSYS] = { ++ .bit = BIT(0), ++ .reg = TH1520_X2H_CPUSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AHB2_CPUSYS] = { ++ .bit = BIT(0), ++ .reg = TH1520_AHB2_CPUSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_APB3_CPUSYS] = { ++ .bit = BIT(0), ++ .reg = TH1520_APB3_CPUSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MBOX0_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_MBOX0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MBOX1_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_MBOX1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MBOX2_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_MBOX2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MBOX3_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_MBOX3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_TIMER0_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_TIMER0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_TIMER0_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_TIMER0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_TIMER1_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_TIMER1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_TIMER1_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_TIMER1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERISYS_AHB] = { ++ .bit = BIT(0), ++ .reg = TH1520_PERISYS_AHB_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERISYS_APB1] = { ++ .bit = BIT(0), ++ .reg = TH1520_PERISYS_APB1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERISYS_APB2] = { ++ .bit = BIT(0), ++ .reg = TH1520_PERISYS_APB2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC0_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_GMAC0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC0_AHB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GMAC0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC0_CLKGEN] = { ++ .bit = BIT(2), ++ .reg = TH1520_GMAC0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC0_AXI] = { ++ .bit = BIT(3), ++ .reg = TH1520_GMAC0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART0_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_UART0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART0_IF] = { ++ .bit = BIT(1), ++ .reg = TH1520_UART0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART1_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_UART1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART1_IF] = { ++ .bit = BIT(1), ++ .reg = TH1520_UART1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART2_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_UART2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART2_IF] = { ++ .bit = BIT(1), ++ .reg = TH1520_UART2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART3_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_UART3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART3_IF] = { ++ .bit = BIT(1), ++ .reg = TH1520_UART3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART4_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_UART4_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART4_IF] = { ++ .bit = BIT(1), ++ .reg = TH1520_UART4_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART5_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_UART5_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART5_IF] = { ++ .bit = BIT(1), ++ .reg = TH1520_UART5_RST_CFG, ++ }, ++ [TH1520_RESET_ID_QSPI0_IF] = { ++ .bit = BIT(0), ++ .reg = TH1520_QSPI0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_QSPI0_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_QSPI0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_QSPI1_IF] = { ++ .bit = BIT(0), ++ .reg = TH1520_QSPI1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_QSPI1_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_QSPI1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_SPI_IF] = { ++ .bit = BIT(0), ++ .reg = TH1520_SPI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_SPI_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_SPI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C0_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2C0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C0_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_I2C0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C1_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2C1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C1_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_I2C1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C2_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2C2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C2_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_I2C2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C3_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2C3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C3_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_I2C3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C4_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2C4_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C4_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_I2C4_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C5_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2C5_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C5_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_I2C5_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO0_DB] = { ++ .bit = BIT(0), ++ .reg = TH1520_GPIO0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO0_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GPIO0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO1_DB] = { ++ .bit = BIT(0), ++ .reg = TH1520_GPIO1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO1_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GPIO1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO2_DB] = { ++ .bit = BIT(0), ++ .reg = TH1520_GPIO2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO2_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GPIO2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PWM_COUNTER] = { ++ .bit = BIT(0), ++ .reg = TH1520_PWM_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PWM_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_PWM_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PADCTRL0_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_PADCTRL0_APSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CPU2PERI_X2H] = { ++ .bit = BIT(1), ++ .reg = TH1520_CPU2PERI_X2H_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CPU2AON_X2H] = { ++ .bit = BIT(0), ++ .reg = TH1520_CPU2AON_X2H_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AON2CPU_A2X] = { ++ .bit = BIT(0), ++ .reg = TH1520_AON2CPU_A2X_RST_CFG, ++ }, ++ [TH1520_RESET_ID_NPUSYS_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_NPUSYS_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_NPUSYS_AXI_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_NPUSYS_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CPU2VP_X2P] = { ++ .bit = BIT(0), ++ .reg = TH1520_CPU2VP_X2P_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CPU2VI_X2H] = { ++ .bit = BIT(0), ++ .reg = TH1520_CPU2VI_X2H_RST_CFG, ++ }, ++ [TH1520_RESET_ID_BMU_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_BMU_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_BMU_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_BMU_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DMAC_CPUSYS_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_DMAC_CPUSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DMAC_CPUSYS_AHB] = { ++ .bit = BIT(1), ++ .reg = TH1520_DMAC_CPUSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_SPINLOCK] = { ++ .bit = BIT(0), ++ .reg = TH1520_SPINLOCK_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CFG2TEE] = { ++ .bit = BIT(0), ++ .reg = TH1520_CFG2TEE_X2H_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSMART] = { ++ .bit = BIT(0), ++ .reg = TH1520_DSMART_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO3_DB] = { ++ .bit = BIT(0), ++ .reg = TH1520_GPIO3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO3_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GPIO3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERI_I2S] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2S_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERI_APB3] = { ++ .bit = BIT(0), ++ .reg = TH1520_PERI_APB3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERI2PERI1_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_PERI_APB3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VPSYS_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_VP_SUBSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERISYS_APB4] = { ++ .bit = BIT(0), ++ .reg = TH1520_PERISYS_APB4_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC1_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_GMAC1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC1_AHB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GMAC1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC1_CLKGEN] = { ++ .bit = BIT(2), ++ .reg = TH1520_GMAC1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC1_AXI] = { ++ .bit = BIT(3), ++ .reg = TH1520_GMAC1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_GMAC_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC_AXI_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GMAC_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PADCTRL1_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_PADCTRL1_APSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VOSYS_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_VOSYS_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VOSYS_AXI_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_VOSYS_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VOSYS_AXI_X2X] = { ++ .bit = BIT(0), ++ .reg = TH1520_VOSYS_X2X_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MISC2VP_X2X] = { ++ .bit = BIT(0), ++ .reg = TH1520_MISC2VP_X2X_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSPSYS] = { ++ .bit = BIT(0), ++ .reg = TH1520_SUBSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VISYS] = { ++ .bit = BIT(1), ++ .reg = TH1520_SUBSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VOSYS] = { ++ .bit = BIT(2), ++ .reg = TH1520_SUBSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VPSYS] = { ++ .bit = BIT(3), ++ .reg = TH1520_SUBSYS_RST_CFG, ++ }, ++}; ++ ++static const struct th1520_reset_map th1520_dsp_resets[] = { ++ [TH1520_RESET_ID_X2X_DSP1] = { ++ .bit = BIT(0), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2X_DSP0] = { ++ .bit = BIT(1), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2X_SLAVE_DSP1] = { ++ .bit = BIT(2), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2X_SLAVE_DSP0] = { ++ .bit = BIT(3), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSP0_CORE] = { ++ .bit = BIT(8), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSP0_DEBUG] = { ++ .bit = BIT(9), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSP0_APB] = { ++ .bit = BIT(10), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSP1_CORE] = { ++ .bit = BIT(12), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSP1_DEBUG] = { ++ .bit = BIT(13), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSP1_APB] = { ++ .bit = BIT(14), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSPSYS_APB] = { ++ .bit = BIT(16), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AXI4_DSPSYS_SLV] = { ++ .bit = BIT(20), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AXI4_DSPSYS] = { ++ .bit = BIT(24), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AXI4_DSP_RS] = { ++ .bit = BIT(26), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++}; ++ ++static const struct th1520_reset_map th1520_misc_resets[] = { ++ [TH1520_RESET_ID_EMMC_SDIO_CLKGEN] = { ++ .bit = BIT(0), ++ .reg = TH1520_EMMC_RST_CFG, ++ }, ++ [TH1520_RESET_ID_EMMC] = { ++ .bit = BIT(1), ++ .reg = TH1520_EMMC_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MISCSYS_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_MISCSYS_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MISCSYS_AXI_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_MISCSYS_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_SDIO0] = { ++ .bit = BIT(0), ++ .reg = TH1520_SDIO0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_SDIO1] = { ++ .bit = BIT(1), ++ .reg = TH1520_SDIO1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_USB3_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_USB3_DRD_RST_CFG, ++ }, ++ [TH1520_RESET_ID_USB3_PHY] = { ++ .bit = BIT(1), ++ .reg = TH1520_USB3_DRD_RST_CFG, ++ }, ++ [TH1520_RESET_ID_USB3_VCC] = { ++ .bit = BIT(2), ++ .reg = TH1520_USB3_DRD_RST_CFG, ++ }, ++}; ++ ++static const struct th1520_reset_map th1520_vi_resets[] = { ++ [TH1520_RESET_ID_ISP0] = { ++ .bit = BIT(0), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_ISP1] = { ++ .bit = BIT(4), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CSI0_APB] = { ++ .bit = BIT(16), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CSI1_APB] = { ++ .bit = BIT(17), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CSI2_APB] = { ++ .bit = BIT(18), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MIPI_FIFO] = { ++ .bit = BIT(20), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_ISP_VENC_APB] = { ++ .bit = BIT(24), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VIPRE_APB] = { ++ .bit = BIT(28), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VIPRE_AXI] = { ++ .bit = BIT(29), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DW200_APB] = { ++ .bit = BIT(31), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VISYS3_AXI] = { ++ .bit = BIT(8), ++ .reg = TH1520_VISYS_2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VISYS2_AXI] = { ++ .bit = BIT(9), ++ .reg = TH1520_VISYS_2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VISYS1_AXI] = { ++ .bit = BIT(10), ++ .reg = TH1520_VISYS_2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VISYS_AXI] = { ++ .bit = BIT(12), ++ .reg = TH1520_VISYS_2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VISYS_APB] = { ++ .bit = BIT(16), ++ .reg = TH1520_VISYS_2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_ISP_VENC_AXI] = { ++ .bit = BIT(20), ++ .reg = TH1520_VISYS_2_RST_CFG, ++ }, ++}; ++ ++static const struct th1520_reset_map th1520_vp_resets[] = { ++ [TH1520_RESET_ID_VPSYS_AXI_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_AXIBUS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VPSYS_AXI] = { ++ .bit = BIT(1), ++ .reg = TH1520_AXIBUS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_FCE_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_FCE_RST_CFG, ++ }, ++ [TH1520_RESET_ID_FCE_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_FCE_RST_CFG, ++ }, ++ [TH1520_RESET_ID_FCE_X2X_MASTER] = { ++ .bit = BIT(4), ++ .reg = TH1520_FCE_RST_CFG, ++ }, ++ [TH1520_RESET_ID_FCE_X2X_SLAVE] = { ++ .bit = BIT(5), ++ .reg = TH1520_FCE_RST_CFG, ++ }, ++ [TH1520_RESET_ID_G2D_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_G2D_RST_CFG, ++ }, ++ [TH1520_RESET_ID_G2D_ACLK] = { ++ .bit = BIT(1), ++ .reg = TH1520_G2D_RST_CFG, ++ }, ++ [TH1520_RESET_ID_G2D_CORE] = { ++ .bit = BIT(2), ++ .reg = TH1520_G2D_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VDEC_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_VDEC_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VDEC_ACLK] = { ++ .bit = BIT(1), ++ .reg = TH1520_VDEC_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VDEC_CORE] = { ++ .bit = BIT(2), ++ .reg = TH1520_VDEC_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VENC_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_VENC_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VENC_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_VENC_RST_CFG, ++ }, + }; + + static inline struct th1520_reset_priv * +@@ -170,8 +933,38 @@ static const struct th1520_reset_data th1520_reset_data = { + .num = ARRAY_SIZE(th1520_resets), + }; + ++static const struct th1520_reset_data th1520_ap_reset_data = { ++ .resets = th1520_ap_resets, ++ .num = ARRAY_SIZE(th1520_ap_resets), ++}; ++ ++static const struct th1520_reset_data th1520_dsp_reset_data = { ++ .resets = th1520_dsp_resets, ++ .num = ARRAY_SIZE(th1520_dsp_resets), ++}; ++ ++static const struct th1520_reset_data th1520_misc_reset_data = { ++ .resets = th1520_misc_resets, ++ .num = ARRAY_SIZE(th1520_misc_resets), ++}; ++ ++static const struct th1520_reset_data th1520_vi_reset_data = { ++ .resets = th1520_vi_resets, ++ .num = ARRAY_SIZE(th1520_vi_resets), ++}; ++ ++static const struct th1520_reset_data th1520_vp_reset_data = { ++ .resets = th1520_vp_resets, ++ .num = ARRAY_SIZE(th1520_vp_resets), ++}; ++ + static const struct of_device_id th1520_reset_match[] = { + { .compatible = "thead,th1520-reset", .data = &th1520_reset_data }, ++ { .compatible = "thead,th1520-reset-ap", .data = &th1520_ap_reset_data }, ++ { .compatible = "thead,th1520-reset-dsp", .data = &th1520_dsp_reset_data }, ++ { .compatible = "thead,th1520-reset-misc", .data = &th1520_misc_reset_data }, ++ { .compatible = "thead,th1520-reset-vi", .data = &th1520_vi_reset_data }, ++ { .compatible = "thead,th1520-reset-vp", .data = &th1520_vp_reset_data }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, th1520_reset_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0257-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch b/SPECS/linux-lts-kmhv2/0257-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch deleted file mode 100644 index 1cbde5c75c..0000000000 --- a/SPECS/linux-lts-kmhv2/0257-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch +++ /dev/null @@ -1,277 +0,0 @@ -From 184187292f9161178cb3c60ba9bc5998781517ec Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Tue, 14 Oct 2025 13:10:29 +0000 -Subject: [PATCH 257/467] UPSTREAM: dt-bindings: reset: thead,th1520-reset: Add - controllers for more subsys - -TH1520 SoC is divided into several subsystems, most of them have -distinct reset controllers. Let's document reset controllers other than -the one for VO subsystem and IDs for their reset signals. - -Signed-off-by: Yao Zi -Acked-by: Rob Herring (Arm) -Reviewed-by: Drew Fustini -Acked-by: Guo Ren -Signed-off-by: Philipp Zabel -(cherry picked from commit a35ac6f3bdb135debc8e1ff599d0009bc64dc329) -Signed-off-by: Han Gao ---- - .../bindings/reset/thead,th1520-reset.yaml | 8 +- - .../dt-bindings/reset/thead,th1520-reset.h | 216 ++++++++++++++++++ - 2 files changed, 223 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml -index f2e91d0add7a..7b5053c177fe 100644 ---- a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml -+++ b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml -@@ -16,7 +16,13 @@ maintainers: - properties: - compatible: - enum: -- - thead,th1520-reset -+ - thead,th1520-reset # Reset controller for VO subsystem -+ - thead,th1520-reset-ao -+ - thead,th1520-reset-ap -+ - thead,th1520-reset-dsp -+ - thead,th1520-reset-misc -+ - thead,th1520-reset-vi -+ - thead,th1520-reset-vp - - reg: - maxItems: 1 -diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h -index e51d6314d131..ba6805b6b12a 100644 ---- a/include/dt-bindings/reset/thead,th1520-reset.h -+++ b/include/dt-bindings/reset/thead,th1520-reset.h -@@ -7,6 +7,200 @@ - #ifndef _DT_BINDINGS_TH1520_RESET_H - #define _DT_BINDINGS_TH1520_RESET_H - -+/* AO Subsystem */ -+#define TH1520_RESET_ID_SYSTEM 0 -+#define TH1520_RESET_ID_RTC_APB 1 -+#define TH1520_RESET_ID_RTC_REF 2 -+#define TH1520_RESET_ID_AOGPIO_DB 3 -+#define TH1520_RESET_ID_AOGPIO_APB 4 -+#define TH1520_RESET_ID_AOI2C_APB 5 -+#define TH1520_RESET_ID_PVT_APB 6 -+#define TH1520_RESET_ID_E902_CORE 7 -+#define TH1520_RESET_ID_E902_HAD 8 -+#define TH1520_RESET_ID_AOTIMER_APB 9 -+#define TH1520_RESET_ID_AOTIMER_CORE 10 -+#define TH1520_RESET_ID_AOWDT_APB 11 -+#define TH1520_RESET_ID_APSYS 12 -+#define TH1520_RESET_ID_NPUSYS 13 -+#define TH1520_RESET_ID_DDRSYS 14 -+#define TH1520_RESET_ID_AXI_AP2CP 15 -+#define TH1520_RESET_ID_AXI_CP2AP 16 -+#define TH1520_RESET_ID_AXI_CP2SRAM 17 -+#define TH1520_RESET_ID_AUDSYS_CORE 18 -+#define TH1520_RESET_ID_AUDSYS_IOPMP 19 -+#define TH1520_RESET_ID_AUDSYS 20 -+#define TH1520_RESET_ID_DSP0 21 -+#define TH1520_RESET_ID_DSP1 22 -+#define TH1520_RESET_ID_GPU_MODULE 23 -+#define TH1520_RESET_ID_VDEC 24 -+#define TH1520_RESET_ID_VENC 25 -+#define TH1520_RESET_ID_ADC_APB 26 -+#define TH1520_RESET_ID_AUDGPIO_DB 27 -+#define TH1520_RESET_ID_AUDGPIO_APB 28 -+#define TH1520_RESET_ID_AOUART_IF 29 -+#define TH1520_RESET_ID_AOUART_APB 30 -+#define TH1520_RESET_ID_SRAM_AXI_P0 31 -+#define TH1520_RESET_ID_SRAM_AXI_P1 32 -+#define TH1520_RESET_ID_SRAM_AXI_P2 33 -+#define TH1520_RESET_ID_SRAM_AXI_P3 34 -+#define TH1520_RESET_ID_SRAM_AXI_P4 35 -+#define TH1520_RESET_ID_SRAM_AXI_CORE 36 -+#define TH1520_RESET_ID_SE 37 -+ -+/* AP Subsystem */ -+#define TH1520_RESET_ID_BROM 0 -+#define TH1520_RESET_ID_C910_TOP 1 -+#define TH1520_RESET_ID_NPU 2 -+#define TH1520_RESET_ID_WDT0 3 -+#define TH1520_RESET_ID_WDT1 4 -+#define TH1520_RESET_ID_C910_C0 5 -+#define TH1520_RESET_ID_C910_C1 6 -+#define TH1520_RESET_ID_C910_C2 7 -+#define TH1520_RESET_ID_C910_C3 8 -+#define TH1520_RESET_ID_CHIP_DBG_CORE 9 -+#define TH1520_RESET_ID_CHIP_DBG_AXI 10 -+#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI 11 -+#define TH1520_RESET_ID_AXI4_CPUSYS2_APB 12 -+#define TH1520_RESET_ID_X2H_CPUSYS 13 -+#define TH1520_RESET_ID_AHB2_CPUSYS 14 -+#define TH1520_RESET_ID_APB3_CPUSYS 15 -+#define TH1520_RESET_ID_MBOX0_APB 16 -+#define TH1520_RESET_ID_MBOX1_APB 17 -+#define TH1520_RESET_ID_MBOX2_APB 18 -+#define TH1520_RESET_ID_MBOX3_APB 19 -+#define TH1520_RESET_ID_TIMER0_APB 20 -+#define TH1520_RESET_ID_TIMER0_CORE 21 -+#define TH1520_RESET_ID_TIMER1_APB 22 -+#define TH1520_RESET_ID_TIMER1_CORE 23 -+#define TH1520_RESET_ID_PERISYS_AHB 24 -+#define TH1520_RESET_ID_PERISYS_APB1 25 -+#define TH1520_RESET_ID_PERISYS_APB2 26 -+#define TH1520_RESET_ID_GMAC0_APB 27 -+#define TH1520_RESET_ID_GMAC0_AHB 28 -+#define TH1520_RESET_ID_GMAC0_CLKGEN 29 -+#define TH1520_RESET_ID_GMAC0_AXI 30 -+#define TH1520_RESET_ID_UART0_APB 31 -+#define TH1520_RESET_ID_UART0_IF 32 -+#define TH1520_RESET_ID_UART1_APB 33 -+#define TH1520_RESET_ID_UART1_IF 34 -+#define TH1520_RESET_ID_UART2_APB 35 -+#define TH1520_RESET_ID_UART2_IF 36 -+#define TH1520_RESET_ID_UART3_APB 37 -+#define TH1520_RESET_ID_UART3_IF 38 -+#define TH1520_RESET_ID_UART4_APB 39 -+#define TH1520_RESET_ID_UART4_IF 40 -+#define TH1520_RESET_ID_UART5_APB 41 -+#define TH1520_RESET_ID_UART5_IF 42 -+#define TH1520_RESET_ID_QSPI0_IF 43 -+#define TH1520_RESET_ID_QSPI0_APB 44 -+#define TH1520_RESET_ID_QSPI1_IF 45 -+#define TH1520_RESET_ID_QSPI1_APB 46 -+#define TH1520_RESET_ID_SPI_IF 47 -+#define TH1520_RESET_ID_SPI_APB 48 -+#define TH1520_RESET_ID_I2C0_APB 49 -+#define TH1520_RESET_ID_I2C0_CORE 50 -+#define TH1520_RESET_ID_I2C1_APB 51 -+#define TH1520_RESET_ID_I2C1_CORE 52 -+#define TH1520_RESET_ID_I2C2_APB 53 -+#define TH1520_RESET_ID_I2C2_CORE 54 -+#define TH1520_RESET_ID_I2C3_APB 55 -+#define TH1520_RESET_ID_I2C3_CORE 56 -+#define TH1520_RESET_ID_I2C4_APB 57 -+#define TH1520_RESET_ID_I2C4_CORE 58 -+#define TH1520_RESET_ID_I2C5_APB 59 -+#define TH1520_RESET_ID_I2C5_CORE 60 -+#define TH1520_RESET_ID_GPIO0_DB 61 -+#define TH1520_RESET_ID_GPIO0_APB 62 -+#define TH1520_RESET_ID_GPIO1_DB 63 -+#define TH1520_RESET_ID_GPIO1_APB 64 -+#define TH1520_RESET_ID_GPIO2_DB 65 -+#define TH1520_RESET_ID_GPIO2_APB 66 -+#define TH1520_RESET_ID_PWM_COUNTER 67 -+#define TH1520_RESET_ID_PWM_APB 68 -+#define TH1520_RESET_ID_PADCTRL0_APB 69 -+#define TH1520_RESET_ID_CPU2PERI_X2H 70 -+#define TH1520_RESET_ID_CPU2AON_X2H 71 -+#define TH1520_RESET_ID_AON2CPU_A2X 72 -+#define TH1520_RESET_ID_NPUSYS_AXI 73 -+#define TH1520_RESET_ID_NPUSYS_AXI_APB 74 -+#define TH1520_RESET_ID_CPU2VP_X2P 75 -+#define TH1520_RESET_ID_CPU2VI_X2H 76 -+#define TH1520_RESET_ID_BMU_AXI 77 -+#define TH1520_RESET_ID_BMU_APB 78 -+#define TH1520_RESET_ID_DMAC_CPUSYS_AXI 79 -+#define TH1520_RESET_ID_DMAC_CPUSYS_AHB 80 -+#define TH1520_RESET_ID_SPINLOCK 81 -+#define TH1520_RESET_ID_CFG2TEE 82 -+#define TH1520_RESET_ID_DSMART 83 -+#define TH1520_RESET_ID_GPIO3_DB 84 -+#define TH1520_RESET_ID_GPIO3_APB 85 -+#define TH1520_RESET_ID_PERI_I2S 86 -+#define TH1520_RESET_ID_PERI_APB3 87 -+#define TH1520_RESET_ID_PERI2PERI1_APB 88 -+#define TH1520_RESET_ID_VPSYS_APB 89 -+#define TH1520_RESET_ID_PERISYS_APB4 90 -+#define TH1520_RESET_ID_GMAC1_APB 91 -+#define TH1520_RESET_ID_GMAC1_AHB 92 -+#define TH1520_RESET_ID_GMAC1_CLKGEN 93 -+#define TH1520_RESET_ID_GMAC1_AXI 94 -+#define TH1520_RESET_ID_GMAC_AXI 95 -+#define TH1520_RESET_ID_GMAC_AXI_APB 96 -+#define TH1520_RESET_ID_PADCTRL1_APB 97 -+#define TH1520_RESET_ID_VOSYS_AXI 98 -+#define TH1520_RESET_ID_VOSYS_AXI_APB 99 -+#define TH1520_RESET_ID_VOSYS_AXI_X2X 100 -+#define TH1520_RESET_ID_MISC2VP_X2X 101 -+#define TH1520_RESET_ID_DSPSYS 102 -+#define TH1520_RESET_ID_VISYS 103 -+#define TH1520_RESET_ID_VOSYS 104 -+#define TH1520_RESET_ID_VPSYS 105 -+ -+/* DSP Subsystem */ -+#define TH1520_RESET_ID_X2X_DSP1 0 -+#define TH1520_RESET_ID_X2X_DSP0 1 -+#define TH1520_RESET_ID_X2X_SLAVE_DSP1 2 -+#define TH1520_RESET_ID_X2X_SLAVE_DSP0 3 -+#define TH1520_RESET_ID_DSP0_CORE 4 -+#define TH1520_RESET_ID_DSP0_DEBUG 5 -+#define TH1520_RESET_ID_DSP0_APB 6 -+#define TH1520_RESET_ID_DSP1_CORE 7 -+#define TH1520_RESET_ID_DSP1_DEBUG 8 -+#define TH1520_RESET_ID_DSP1_APB 9 -+#define TH1520_RESET_ID_DSPSYS_APB 10 -+#define TH1520_RESET_ID_AXI4_DSPSYS_SLV 11 -+#define TH1520_RESET_ID_AXI4_DSPSYS 12 -+#define TH1520_RESET_ID_AXI4_DSP_RS 13 -+ -+/* MISC Subsystem */ -+#define TH1520_RESET_ID_EMMC_SDIO_CLKGEN 0 -+#define TH1520_RESET_ID_EMMC 1 -+#define TH1520_RESET_ID_MISCSYS_AXI 2 -+#define TH1520_RESET_ID_MISCSYS_AXI_APB 3 -+#define TH1520_RESET_ID_SDIO0 4 -+#define TH1520_RESET_ID_SDIO1 5 -+#define TH1520_RESET_ID_USB3_APB 6 -+#define TH1520_RESET_ID_USB3_PHY 7 -+#define TH1520_RESET_ID_USB3_VCC 8 -+ -+/* VI Subsystem */ -+#define TH1520_RESET_ID_ISP0 0 -+#define TH1520_RESET_ID_ISP1 1 -+#define TH1520_RESET_ID_CSI0_APB 2 -+#define TH1520_RESET_ID_CSI1_APB 3 -+#define TH1520_RESET_ID_CSI2_APB 4 -+#define TH1520_RESET_ID_MIPI_FIFO 5 -+#define TH1520_RESET_ID_ISP_VENC_APB 6 -+#define TH1520_RESET_ID_VIPRE_APB 7 -+#define TH1520_RESET_ID_VIPRE_AXI 8 -+#define TH1520_RESET_ID_DW200_APB 9 -+#define TH1520_RESET_ID_VISYS3_AXI 10 -+#define TH1520_RESET_ID_VISYS2_AXI 11 -+#define TH1520_RESET_ID_VISYS1_AXI 12 -+#define TH1520_RESET_ID_VISYS_AXI 13 -+#define TH1520_RESET_ID_VISYS_APB 14 -+#define TH1520_RESET_ID_ISP_VENC_AXI 15 -+ -+/* VO Subsystem */ - #define TH1520_RESET_ID_GPU 0 - #define TH1520_RESET_ID_GPU_CLKGEN 1 - #define TH1520_RESET_ID_DPU_AHB 5 -@@ -16,5 +210,27 @@ - #define TH1520_RESET_ID_DSI1_APB 9 - #define TH1520_RESET_ID_HDMI 10 - #define TH1520_RESET_ID_HDMI_APB 11 -+#define TH1520_RESET_ID_VOAXI 12 -+#define TH1520_RESET_ID_VOAXI_APB 13 -+#define TH1520_RESET_ID_X2H_DPU_AXI 14 -+#define TH1520_RESET_ID_X2H_DPU_AHB 15 -+#define TH1520_RESET_ID_X2H_DPU1_AXI 16 -+#define TH1520_RESET_ID_X2H_DPU1_AHB 17 -+ -+/* VP Subsystem */ -+#define TH1520_RESET_ID_VPSYS_AXI_APB 0 -+#define TH1520_RESET_ID_VPSYS_AXI 1 -+#define TH1520_RESET_ID_FCE_APB 2 -+#define TH1520_RESET_ID_FCE_CORE 3 -+#define TH1520_RESET_ID_FCE_X2X_MASTER 4 -+#define TH1520_RESET_ID_FCE_X2X_SLAVE 5 -+#define TH1520_RESET_ID_G2D_APB 6 -+#define TH1520_RESET_ID_G2D_ACLK 7 -+#define TH1520_RESET_ID_G2D_CORE 8 -+#define TH1520_RESET_ID_VDEC_APB 9 -+#define TH1520_RESET_ID_VDEC_ACLK 10 -+#define TH1520_RESET_ID_VDEC_CORE 11 -+#define TH1520_RESET_ID_VENC_APB 12 -+#define TH1520_RESET_ID_VENC_CORE 13 - - #endif /* _DT_BINDINGS_TH1520_RESET_H */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch b/SPECS/linux-lts-kmhv2/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch new file mode 100644 index 0000000000..0509d7a26d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch @@ -0,0 +1,91 @@ +From 9edafc5f3980e8fcb1a7a18a54466898f1279c14 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 14 Oct 2025 13:10:32 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add reset controllers of + more subsystems for TH1520 + +Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The +one for AO subsystem is marked as reserved, since it may be used by AON +firmware. + +Reviewed-by: Drew Fustini +Signed-off-by: Yao Zi +Signed-off-by: Drew Fustini +(cherry picked from commit d8a174babf649346b6dad6784ae1e9bc8417af71) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++ + 1 file changed, 37 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index c65b71d9a1b8..5e91dc1d2b9b 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -289,6 +289,12 @@ clint: timer@ffdc000000 { + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + ++ rst_vi: reset-controller@ffe4040100 { ++ compatible = "thead,th1520-reset-vi"; ++ reg = <0xff 0xe4040100 0x0 0x8>; ++ #reset-cells = <1>; ++ }; ++ + spi0: spi@ffe700c000 { + compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; + reg = <0xff 0xe700c000 0x0 0x1000>; +@@ -521,6 +527,18 @@ pwm: pwm@ffec01c000 { + #pwm-cells = <3>; + }; + ++ rst_misc: reset-controller@ffec02c000 { ++ compatible = "thead,th1520-reset-misc"; ++ reg = <0xff 0xec02c000 0x0 0x18>; ++ #reset-cells = <1>; ++ }; ++ ++ rst_vp: reset-controller@ffecc30000 { ++ compatible = "thead,th1520-reset-vp"; ++ reg = <0xff 0xecc30000 0x0 0x14>; ++ #reset-cells = <1>; ++ }; ++ + clk: clock-controller@ffef010000 { + compatible = "thead,th1520-clk-ap"; + reg = <0xff 0xef010000 0x0 0x1000>; +@@ -528,6 +546,18 @@ clk: clock-controller@ffef010000 { + #clock-cells = <1>; + }; + ++ rst_ap: reset-controller@ffef014000 { ++ compatible = "thead,th1520-reset-ap"; ++ reg = <0xff 0xef014000 0x0 0x1000>; ++ #reset-cells = <1>; ++ }; ++ ++ rst_dsp: reset-controller@ffef040028 { ++ compatible = "thead,th1520-reset-dsp"; ++ reg = <0xff 0xef040028 0x0 0x4>; ++ #reset-cells = <1>; ++ }; ++ + gpu: gpu@ffef400000 { + compatible = "thead,th1520-gpu", "img,img-bxm-4-64", + "img,img-rogue"; +@@ -766,6 +796,13 @@ aogpio: gpio-controller@0 { + }; + }; + ++ rst_ao: reset-controller@fffff44000 { ++ compatible = "thead,th1520-reset-ao"; ++ reg = <0xff 0xfff44000 0x0 0x2000>; ++ #reset-cells = <1>; ++ status = "reserved"; ++ }; ++ + padctrl_aosys: pinctrl@fffff4a000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xfff4a000 0x0 0x2000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch b/SPECS/linux-lts-kmhv2/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch new file mode 100644 index 0000000000..983dd64913 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch @@ -0,0 +1,39 @@ +From 5f50d2a328f7b2daa106bafdb1d4a794f52fbdb4 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 24 Apr 2026 16:20:32 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: mark top_dclk as + CLK_IS_CRITICAL + +top_dclk is the DDR bus clock. If it is gated by clk_disable_unused, +all memory-mapped bus transactions cease to function, causing DMA +engines to hang and general system instability. + +Mark it CLK_IS_CRITICAL so the CCF never gates it during the +unused clock sweep. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Reviewed-by: Brian Masney +Signed-off-by: Troy Mitchell +Signed-off-by: Stephen Boyd +(cherry picked from commit 3e75021f615ceee8562e6455c335936b39929ffb) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index e98afd59f05c..bb8b75bdbdb3 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -846,7 +846,7 @@ static const struct clk_parent_data top_parents[] = { + CCU_PARENT_HW(pll6_d3), + }; + CCU_MUX_DIV_GATE_FC_DEFINE(top_dclk, top_parents, APMU_TOP_DCLK_CTRL, 5, 3, +- BIT(8), 2, 3, BIT(1), 0); ++ BIT(8), 2, 3, BIT(1), CLK_IS_CRITICAL); + + static const struct clk_parent_data ucie_parents[] = { + CCU_PARENT_HW(pll1_d8_307p2), +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0258-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch b/SPECS/linux-lts-kmhv2/0258-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch deleted file mode 100644 index 350dce55d4..0000000000 --- a/SPECS/linux-lts-kmhv2/0258-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch +++ /dev/null @@ -1,124 +0,0 @@ -From db3838d594378909391879da3362ce86ec33cc81 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Tue, 14 Oct 2025 13:10:30 +0000 -Subject: [PATCH 258/467] UPSTREAM: reset: th1520: Prepare for supporting - multiple controllers - -TH1520 SoC is divided into several subsystems, shipping distinct reset -controllers with similar control logic. Let's make reset signal mapping -a data structure specific to one compatible to prepare for introduction -of more reset controllers in the future. - -Signed-off-by: Yao Zi -Acked-by: Guo Ren -Reviewed-by: Drew Fustini -Signed-off-by: Philipp Zabel -(cherry picked from commit 0040d9eac391bacefcb0c748cf32c8fe5900b13b) -Signed-off-by: Han Gao ---- - drivers/reset/reset-th1520.c | 42 +++++++++++++++++++++++++----------- - 1 file changed, 30 insertions(+), 12 deletions(-) - -diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c -index 14d964a9c6b6..2b65a95ed021 100644 ---- a/drivers/reset/reset-th1520.c -+++ b/drivers/reset/reset-th1520.c -@@ -29,14 +29,20 @@ - #define TH1520_HDMI_SW_MAIN_RST BIT(0) - #define TH1520_HDMI_SW_PRST BIT(1) - -+struct th1520_reset_map { -+ u32 bit; -+ u32 reg; -+}; -+ - struct th1520_reset_priv { - struct reset_controller_dev rcdev; - struct regmap *map; -+ const struct th1520_reset_map *resets; - }; - --struct th1520_reset_map { -- u32 bit; -- u32 reg; -+struct th1520_reset_data { -+ const struct th1520_reset_map *resets; -+ size_t num; - }; - - static const struct th1520_reset_map th1520_resets[] = { -@@ -90,7 +96,7 @@ static int th1520_reset_assert(struct reset_controller_dev *rcdev, - struct th1520_reset_priv *priv = to_th1520_reset(rcdev); - const struct th1520_reset_map *reset; - -- reset = &th1520_resets[id]; -+ reset = &priv->resets[id]; - - return regmap_update_bits(priv->map, reset->reg, reset->bit, 0); - } -@@ -101,7 +107,7 @@ static int th1520_reset_deassert(struct reset_controller_dev *rcdev, - struct th1520_reset_priv *priv = to_th1520_reset(rcdev); - const struct th1520_reset_map *reset; - -- reset = &th1520_resets[id]; -+ reset = &priv->resets[id]; - - return regmap_update_bits(priv->map, reset->reg, reset->bit, - reset->bit); -@@ -120,11 +126,14 @@ static const struct regmap_config th1520_reset_regmap_config = { - - static int th1520_reset_probe(struct platform_device *pdev) - { -+ const struct th1520_reset_data *data; - struct device *dev = &pdev->dev; - struct th1520_reset_priv *priv; - void __iomem *base; - int ret; - -+ data = device_get_match_data(dev); -+ - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; -@@ -138,22 +147,31 @@ static int th1520_reset_probe(struct platform_device *pdev) - if (IS_ERR(priv->map)) - return PTR_ERR(priv->map); - -- /* Initialize GPU resets to asserted state */ -- ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, -- TH1520_GPU_RST_CFG_MASK, 0); -- if (ret) -- return ret; -+ if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) { -+ /* Initialize GPU resets to asserted state */ -+ ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, -+ TH1520_GPU_RST_CFG_MASK, 0); -+ if (ret) -+ return ret; -+ } - - priv->rcdev.owner = THIS_MODULE; -- priv->rcdev.nr_resets = ARRAY_SIZE(th1520_resets); -+ priv->rcdev.nr_resets = data->num; - priv->rcdev.ops = &th1520_reset_ops; - priv->rcdev.of_node = dev->of_node; - -+ priv->resets = data->resets; -+ - return devm_reset_controller_register(dev, &priv->rcdev); - } - -+static const struct th1520_reset_data th1520_reset_data = { -+ .resets = th1520_resets, -+ .num = ARRAY_SIZE(th1520_resets), -+}; -+ - static const struct of_device_id th1520_reset_match[] = { -- { .compatible = "thead,th1520-reset" }, -+ { .compatible = "thead,th1520-reset", .data = &th1520_reset_data }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, th1520_reset_match); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch b/SPECS/linux-lts-kmhv2/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch new file mode 100644 index 0000000000..b11d06885a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch @@ -0,0 +1,53 @@ +From a7739f1ea5fb20b796b4b1d3758fd44635a40ea9 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Wed, 29 Apr 2026 17:00:50 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: fix RX DMA params not set when + TX is running + +When TX is already running (SSCR_SSE is set), the hw_params callback +returns early before setting up DMA parameters for the RX stream. This +prevents the capture path from configuring its DMA data properly. + +Move the SSCR_SSE check after DMA parameter setup and format +constraints, so both TX and RX streams get their DMA configuration +regardless of whether the hardware is already enabled. The early return +now only skips the register writes that would disrupt an active stream. + +Fixes: fce217449075 ("ASoC: spacemit: add i2s support for K1 SoC") +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260429-k1-i2s-fix-v2-1-8d67835aaddc@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit ec0611868f2fcf29e4c2bebdc6702d3e1f272fec) +Signed-off-by: Han Gao +--- + sound/soc/spacemit/k1_i2s.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c +index b48c57bede37..03cca5d84503 100644 +--- a/sound/soc/spacemit/k1_i2s.c ++++ b/sound/soc/spacemit/k1_i2s.c +@@ -148,10 +148,6 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, + u32 val; + int ret; + +- val = readl(i2s->base + SSCR); +- if (val & SSCR_SSE) +- return 0; +- + dma_data = &i2s->playback_dma_data; + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) +@@ -199,6 +195,9 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, + } + + val = readl(i2s->base + SSCR); ++ if (val & SSCR_SSE) ++ return 0; ++ + val &= ~SSCR_DW_32BYTE; + val |= data_width; + writel(val, i2s->base + SSCR); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0259-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch b/SPECS/linux-lts-kmhv2/0259-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch deleted file mode 100644 index 6e02a295c5..0000000000 --- a/SPECS/linux-lts-kmhv2/0259-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch +++ /dev/null @@ -1,856 +0,0 @@ -From 8109a7f9d10f1d9ce7e0ee5a3f63993d591d8673 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Tue, 14 Oct 2025 13:10:31 +0000 -Subject: [PATCH 259/467] UPSTREAM: reset: th1520: Support reset controllers in - more subsystems - -Introduce reset controllers for AP, MISC, VI, VP and DSP subsystems and -add their reset signal mappings. - -Signed-off-by: Yao Zi -Reviewed-by: Drew Fustini -Acked-by: Guo Ren -Signed-off-by: Philipp Zabel -(cherry picked from commit da91533c2b7a569b272b8271f0b2c407f86407ed) -Signed-off-by: Han Gao ---- - drivers/reset/reset-th1520.c | 793 +++++++++++++++++++++++++++++++++++ - 1 file changed, 793 insertions(+) - -diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c -index 2b65a95ed021..fd32e991c4cb 100644 ---- a/drivers/reset/reset-th1520.c -+++ b/drivers/reset/reset-th1520.c -@@ -11,6 +11,85 @@ - - #include - -+ /* register offset in RSTGEN_R */ -+#define TH1520_BROM_RST_CFG 0x0 -+#define TH1520_C910_RST_CFG 0x4 -+#define TH1520_CHIP_DBG_RST_CFG 0xc -+#define TH1520_AXI4_CPUSYS2_RST_CFG 0x10 -+#define TH1520_X2H_CPUSYS_RST_CFG 0x18 -+#define TH1520_AHB2_CPUSYS_RST_CFG 0x1c -+#define TH1520_APB3_CPUSYS_RST_CFG 0x20 -+#define TH1520_MBOX0_RST_CFG 0x24 -+#define TH1520_MBOX1_RST_CFG 0x28 -+#define TH1520_MBOX2_RST_CFG 0x2c -+#define TH1520_MBOX3_RST_CFG 0x30 -+#define TH1520_WDT0_RST_CFG 0x34 -+#define TH1520_WDT1_RST_CFG 0x38 -+#define TH1520_TIMER0_RST_CFG 0x3c -+#define TH1520_TIMER1_RST_CFG 0x40 -+#define TH1520_PERISYS_AHB_RST_CFG 0x44 -+#define TH1520_PERISYS_APB1_RST_CFG 0x48 -+#define TH1520_PERISYS_APB2_RST_CFG 0x4c -+#define TH1520_GMAC0_RST_CFG 0x68 -+#define TH1520_UART0_RST_CFG 0x70 -+#define TH1520_UART1_RST_CFG 0x74 -+#define TH1520_UART2_RST_CFG 0x78 -+#define TH1520_UART3_RST_CFG 0x7c -+#define TH1520_UART4_RST_CFG 0x80 -+#define TH1520_UART5_RST_CFG 0x84 -+#define TH1520_QSPI0_RST_CFG 0x8c -+#define TH1520_QSPI1_RST_CFG 0x90 -+#define TH1520_SPI_RST_CFG 0x94 -+#define TH1520_I2C0_RST_CFG 0x98 -+#define TH1520_I2C1_RST_CFG 0x9c -+#define TH1520_I2C2_RST_CFG 0xa0 -+#define TH1520_I2C3_RST_CFG 0xa4 -+#define TH1520_I2C4_RST_CFG 0xa8 -+#define TH1520_I2C5_RST_CFG 0xac -+#define TH1520_GPIO0_RST_CFG 0xb0 -+#define TH1520_GPIO1_RST_CFG 0xb4 -+#define TH1520_GPIO2_RST_CFG 0xb8 -+#define TH1520_PWM_RST_CFG 0xc0 -+#define TH1520_PADCTRL0_APSYS_RST_CFG 0xc4 -+#define TH1520_CPU2PERI_X2H_RST_CFG 0xcc -+#define TH1520_CPU2AON_X2H_RST_CFG 0xe4 -+#define TH1520_AON2CPU_A2X_RST_CFG 0xfc -+#define TH1520_NPUSYS_AXI_RST_CFG 0x128 -+#define TH1520_CPU2VP_X2P_RST_CFG 0x12c -+#define TH1520_CPU2VI_X2H_RST_CFG 0x138 -+#define TH1520_BMU_C910_RST_CFG 0x148 -+#define TH1520_DMAC_CPUSYS_RST_CFG 0x14c -+#define TH1520_SPINLOCK_RST_CFG 0x178 -+#define TH1520_CFG2TEE_X2H_RST_CFG 0x188 -+#define TH1520_DSMART_RST_CFG 0x18c -+#define TH1520_GPIO3_RST_CFG 0x1a8 -+#define TH1520_I2S_RST_CFG 0x1ac -+#define TH1520_IMG_NNA_RST_CFG 0x1b0 -+#define TH1520_PERI_APB3_RST_CFG 0x1dc -+#define TH1520_VP_SUBSYS_RST_CFG 0x1ec -+#define TH1520_PERISYS_APB4_RST_CFG 0x1f8 -+#define TH1520_GMAC1_RST_CFG 0x204 -+#define TH1520_GMAC_AXI_RST_CFG 0x208 -+#define TH1520_PADCTRL1_APSYS_RST_CFG 0x20c -+#define TH1520_VOSYS_AXI_RST_CFG 0x210 -+#define TH1520_VOSYS_X2X_RST_CFG 0x214 -+#define TH1520_MISC2VP_X2X_RST_CFG 0x218 -+#define TH1520_SUBSYS_RST_CFG 0x220 -+ -+ /* register offset in DSP_REGMAP */ -+#define TH1520_DSPSYS_RST_CFG 0x0 -+ -+ /* register offset in MISCSYS_REGMAP */ -+#define TH1520_EMMC_RST_CFG 0x0 -+#define TH1520_MISCSYS_AXI_RST_CFG 0x8 -+#define TH1520_SDIO0_RST_CFG 0xc -+#define TH1520_SDIO1_RST_CFG 0x10 -+#define TH1520_USB3_DRD_RST_CFG 0x14 -+ -+ /* register offset in VISYS_REGMAP */ -+#define TH1520_VISYS_RST_CFG 0x0 -+#define TH1520_VISYS_2_RST_CFG 0x4 -+ - /* register offset in VOSYS_REGMAP */ - #define TH1520_GPU_RST_CFG 0x0 - #define TH1520_GPU_RST_CFG_MASK GENMASK(1, 0) -@@ -18,6 +97,8 @@ - #define TH1520_DSI0_RST_CFG 0x8 - #define TH1520_DSI1_RST_CFG 0xc - #define TH1520_HDMI_RST_CFG 0x14 -+#define TH1520_AXI4_VO_DW_AXI_RST_CFG 0x18 -+#define TH1520_X2H_X4_VOSYS_DW_RST_CFG 0x20 - - /* register values */ - #define TH1520_GPU_SW_GPU_RST BIT(0) -@@ -29,6 +110,13 @@ - #define TH1520_HDMI_SW_MAIN_RST BIT(0) - #define TH1520_HDMI_SW_PRST BIT(1) - -+ /* register offset in VPSYS_REGMAP */ -+#define TH1520_AXIBUS_RST_CFG 0x0 -+#define TH1520_FCE_RST_CFG 0x4 -+#define TH1520_G2D_RST_CFG 0x8 -+#define TH1520_VDEC_RST_CFG 0xc -+#define TH1520_VENC_RST_CFG 0x10 -+ - struct th1520_reset_map { - u32 bit; - u32 reg; -@@ -82,6 +170,681 @@ static const struct th1520_reset_map th1520_resets[] = { - .bit = TH1520_HDMI_SW_PRST, - .reg = TH1520_HDMI_RST_CFG, - }, -+ [TH1520_RESET_ID_VOAXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VOAXI_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2H_DPU_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2H_DPU_AHB] = { -+ .bit = BIT(1), -+ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2H_DPU1_AXI] = { -+ .bit = BIT(2), -+ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2H_DPU1_AHB] = { -+ .bit = BIT(3), -+ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, -+ }, -+}; -+ -+static const struct th1520_reset_map th1520_ap_resets[] = { -+ [TH1520_RESET_ID_BROM] = { -+ .bit = BIT(0), -+ .reg = TH1520_BROM_RST_CFG, -+ }, -+ [TH1520_RESET_ID_C910_TOP] = { -+ .bit = BIT(0), -+ .reg = TH1520_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_NPU] = { -+ .bit = BIT(0), -+ .reg = TH1520_IMG_NNA_RST_CFG, -+ }, -+ [TH1520_RESET_ID_WDT0] = { -+ .bit = BIT(0), -+ .reg = TH1520_WDT0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_WDT1] = { -+ .bit = BIT(0), -+ .reg = TH1520_WDT1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_C910_C0] = { -+ .bit = BIT(1), -+ .reg = TH1520_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_C910_C1] = { -+ .bit = BIT(2), -+ .reg = TH1520_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_C910_C2] = { -+ .bit = BIT(3), -+ .reg = TH1520_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_C910_C3] = { -+ .bit = BIT(4), -+ .reg = TH1520_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CHIP_DBG_CORE] = { -+ .bit = BIT(0), -+ .reg = TH1520_CHIP_DBG_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CHIP_DBG_AXI] = { -+ .bit = BIT(1), -+ .reg = TH1520_CHIP_DBG_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AXI4_CPUSYS2_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_AXI4_CPUSYS2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AXI4_CPUSYS2_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_AXI4_CPUSYS2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2H_CPUSYS] = { -+ .bit = BIT(0), -+ .reg = TH1520_X2H_CPUSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AHB2_CPUSYS] = { -+ .bit = BIT(0), -+ .reg = TH1520_AHB2_CPUSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_APB3_CPUSYS] = { -+ .bit = BIT(0), -+ .reg = TH1520_APB3_CPUSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MBOX0_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_MBOX0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MBOX1_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_MBOX1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MBOX2_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_MBOX2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MBOX3_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_MBOX3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_TIMER0_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_TIMER0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_TIMER0_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_TIMER0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_TIMER1_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_TIMER1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_TIMER1_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_TIMER1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERISYS_AHB] = { -+ .bit = BIT(0), -+ .reg = TH1520_PERISYS_AHB_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERISYS_APB1] = { -+ .bit = BIT(0), -+ .reg = TH1520_PERISYS_APB1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERISYS_APB2] = { -+ .bit = BIT(0), -+ .reg = TH1520_PERISYS_APB2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC0_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_GMAC0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC0_AHB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GMAC0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC0_CLKGEN] = { -+ .bit = BIT(2), -+ .reg = TH1520_GMAC0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC0_AXI] = { -+ .bit = BIT(3), -+ .reg = TH1520_GMAC0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART0_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_UART0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART0_IF] = { -+ .bit = BIT(1), -+ .reg = TH1520_UART0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART1_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_UART1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART1_IF] = { -+ .bit = BIT(1), -+ .reg = TH1520_UART1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART2_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_UART2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART2_IF] = { -+ .bit = BIT(1), -+ .reg = TH1520_UART2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART3_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_UART3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART3_IF] = { -+ .bit = BIT(1), -+ .reg = TH1520_UART3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART4_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_UART4_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART4_IF] = { -+ .bit = BIT(1), -+ .reg = TH1520_UART4_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART5_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_UART5_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART5_IF] = { -+ .bit = BIT(1), -+ .reg = TH1520_UART5_RST_CFG, -+ }, -+ [TH1520_RESET_ID_QSPI0_IF] = { -+ .bit = BIT(0), -+ .reg = TH1520_QSPI0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_QSPI0_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_QSPI0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_QSPI1_IF] = { -+ .bit = BIT(0), -+ .reg = TH1520_QSPI1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_QSPI1_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_QSPI1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_SPI_IF] = { -+ .bit = BIT(0), -+ .reg = TH1520_SPI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_SPI_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_SPI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C0_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2C0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C0_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_I2C0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C1_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2C1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C1_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_I2C1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C2_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2C2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C2_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_I2C2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C3_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2C3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C3_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_I2C3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C4_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2C4_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C4_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_I2C4_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C5_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2C5_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C5_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_I2C5_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO0_DB] = { -+ .bit = BIT(0), -+ .reg = TH1520_GPIO0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO0_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GPIO0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO1_DB] = { -+ .bit = BIT(0), -+ .reg = TH1520_GPIO1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO1_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GPIO1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO2_DB] = { -+ .bit = BIT(0), -+ .reg = TH1520_GPIO2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO2_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GPIO2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PWM_COUNTER] = { -+ .bit = BIT(0), -+ .reg = TH1520_PWM_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PWM_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_PWM_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PADCTRL0_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_PADCTRL0_APSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CPU2PERI_X2H] = { -+ .bit = BIT(1), -+ .reg = TH1520_CPU2PERI_X2H_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CPU2AON_X2H] = { -+ .bit = BIT(0), -+ .reg = TH1520_CPU2AON_X2H_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AON2CPU_A2X] = { -+ .bit = BIT(0), -+ .reg = TH1520_AON2CPU_A2X_RST_CFG, -+ }, -+ [TH1520_RESET_ID_NPUSYS_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_NPUSYS_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_NPUSYS_AXI_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_NPUSYS_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CPU2VP_X2P] = { -+ .bit = BIT(0), -+ .reg = TH1520_CPU2VP_X2P_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CPU2VI_X2H] = { -+ .bit = BIT(0), -+ .reg = TH1520_CPU2VI_X2H_RST_CFG, -+ }, -+ [TH1520_RESET_ID_BMU_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_BMU_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_BMU_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_BMU_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DMAC_CPUSYS_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_DMAC_CPUSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DMAC_CPUSYS_AHB] = { -+ .bit = BIT(1), -+ .reg = TH1520_DMAC_CPUSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_SPINLOCK] = { -+ .bit = BIT(0), -+ .reg = TH1520_SPINLOCK_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CFG2TEE] = { -+ .bit = BIT(0), -+ .reg = TH1520_CFG2TEE_X2H_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSMART] = { -+ .bit = BIT(0), -+ .reg = TH1520_DSMART_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO3_DB] = { -+ .bit = BIT(0), -+ .reg = TH1520_GPIO3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO3_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GPIO3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERI_I2S] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2S_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERI_APB3] = { -+ .bit = BIT(0), -+ .reg = TH1520_PERI_APB3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERI2PERI1_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_PERI_APB3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VPSYS_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_VP_SUBSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERISYS_APB4] = { -+ .bit = BIT(0), -+ .reg = TH1520_PERISYS_APB4_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC1_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_GMAC1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC1_AHB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GMAC1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC1_CLKGEN] = { -+ .bit = BIT(2), -+ .reg = TH1520_GMAC1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC1_AXI] = { -+ .bit = BIT(3), -+ .reg = TH1520_GMAC1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_GMAC_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC_AXI_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GMAC_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PADCTRL1_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_PADCTRL1_APSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VOSYS_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_VOSYS_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VOSYS_AXI_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_VOSYS_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VOSYS_AXI_X2X] = { -+ .bit = BIT(0), -+ .reg = TH1520_VOSYS_X2X_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MISC2VP_X2X] = { -+ .bit = BIT(0), -+ .reg = TH1520_MISC2VP_X2X_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSPSYS] = { -+ .bit = BIT(0), -+ .reg = TH1520_SUBSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VISYS] = { -+ .bit = BIT(1), -+ .reg = TH1520_SUBSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VOSYS] = { -+ .bit = BIT(2), -+ .reg = TH1520_SUBSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VPSYS] = { -+ .bit = BIT(3), -+ .reg = TH1520_SUBSYS_RST_CFG, -+ }, -+}; -+ -+static const struct th1520_reset_map th1520_dsp_resets[] = { -+ [TH1520_RESET_ID_X2X_DSP1] = { -+ .bit = BIT(0), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2X_DSP0] = { -+ .bit = BIT(1), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2X_SLAVE_DSP1] = { -+ .bit = BIT(2), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2X_SLAVE_DSP0] = { -+ .bit = BIT(3), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSP0_CORE] = { -+ .bit = BIT(8), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSP0_DEBUG] = { -+ .bit = BIT(9), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSP0_APB] = { -+ .bit = BIT(10), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSP1_CORE] = { -+ .bit = BIT(12), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSP1_DEBUG] = { -+ .bit = BIT(13), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSP1_APB] = { -+ .bit = BIT(14), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSPSYS_APB] = { -+ .bit = BIT(16), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AXI4_DSPSYS_SLV] = { -+ .bit = BIT(20), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AXI4_DSPSYS] = { -+ .bit = BIT(24), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AXI4_DSP_RS] = { -+ .bit = BIT(26), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+}; -+ -+static const struct th1520_reset_map th1520_misc_resets[] = { -+ [TH1520_RESET_ID_EMMC_SDIO_CLKGEN] = { -+ .bit = BIT(0), -+ .reg = TH1520_EMMC_RST_CFG, -+ }, -+ [TH1520_RESET_ID_EMMC] = { -+ .bit = BIT(1), -+ .reg = TH1520_EMMC_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MISCSYS_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_MISCSYS_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MISCSYS_AXI_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_MISCSYS_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_SDIO0] = { -+ .bit = BIT(0), -+ .reg = TH1520_SDIO0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_SDIO1] = { -+ .bit = BIT(1), -+ .reg = TH1520_SDIO1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_USB3_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_USB3_DRD_RST_CFG, -+ }, -+ [TH1520_RESET_ID_USB3_PHY] = { -+ .bit = BIT(1), -+ .reg = TH1520_USB3_DRD_RST_CFG, -+ }, -+ [TH1520_RESET_ID_USB3_VCC] = { -+ .bit = BIT(2), -+ .reg = TH1520_USB3_DRD_RST_CFG, -+ }, -+}; -+ -+static const struct th1520_reset_map th1520_vi_resets[] = { -+ [TH1520_RESET_ID_ISP0] = { -+ .bit = BIT(0), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_ISP1] = { -+ .bit = BIT(4), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CSI0_APB] = { -+ .bit = BIT(16), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CSI1_APB] = { -+ .bit = BIT(17), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CSI2_APB] = { -+ .bit = BIT(18), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MIPI_FIFO] = { -+ .bit = BIT(20), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_ISP_VENC_APB] = { -+ .bit = BIT(24), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VIPRE_APB] = { -+ .bit = BIT(28), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VIPRE_AXI] = { -+ .bit = BIT(29), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DW200_APB] = { -+ .bit = BIT(31), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VISYS3_AXI] = { -+ .bit = BIT(8), -+ .reg = TH1520_VISYS_2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VISYS2_AXI] = { -+ .bit = BIT(9), -+ .reg = TH1520_VISYS_2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VISYS1_AXI] = { -+ .bit = BIT(10), -+ .reg = TH1520_VISYS_2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VISYS_AXI] = { -+ .bit = BIT(12), -+ .reg = TH1520_VISYS_2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VISYS_APB] = { -+ .bit = BIT(16), -+ .reg = TH1520_VISYS_2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_ISP_VENC_AXI] = { -+ .bit = BIT(20), -+ .reg = TH1520_VISYS_2_RST_CFG, -+ }, -+}; -+ -+static const struct th1520_reset_map th1520_vp_resets[] = { -+ [TH1520_RESET_ID_VPSYS_AXI_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_AXIBUS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VPSYS_AXI] = { -+ .bit = BIT(1), -+ .reg = TH1520_AXIBUS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_FCE_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_FCE_RST_CFG, -+ }, -+ [TH1520_RESET_ID_FCE_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_FCE_RST_CFG, -+ }, -+ [TH1520_RESET_ID_FCE_X2X_MASTER] = { -+ .bit = BIT(4), -+ .reg = TH1520_FCE_RST_CFG, -+ }, -+ [TH1520_RESET_ID_FCE_X2X_SLAVE] = { -+ .bit = BIT(5), -+ .reg = TH1520_FCE_RST_CFG, -+ }, -+ [TH1520_RESET_ID_G2D_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_G2D_RST_CFG, -+ }, -+ [TH1520_RESET_ID_G2D_ACLK] = { -+ .bit = BIT(1), -+ .reg = TH1520_G2D_RST_CFG, -+ }, -+ [TH1520_RESET_ID_G2D_CORE] = { -+ .bit = BIT(2), -+ .reg = TH1520_G2D_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VDEC_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_VDEC_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VDEC_ACLK] = { -+ .bit = BIT(1), -+ .reg = TH1520_VDEC_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VDEC_CORE] = { -+ .bit = BIT(2), -+ .reg = TH1520_VDEC_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VENC_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_VENC_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VENC_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_VENC_RST_CFG, -+ }, - }; - - static inline struct th1520_reset_priv * -@@ -170,8 +933,38 @@ static const struct th1520_reset_data th1520_reset_data = { - .num = ARRAY_SIZE(th1520_resets), - }; - -+static const struct th1520_reset_data th1520_ap_reset_data = { -+ .resets = th1520_ap_resets, -+ .num = ARRAY_SIZE(th1520_ap_resets), -+}; -+ -+static const struct th1520_reset_data th1520_dsp_reset_data = { -+ .resets = th1520_dsp_resets, -+ .num = ARRAY_SIZE(th1520_dsp_resets), -+}; -+ -+static const struct th1520_reset_data th1520_misc_reset_data = { -+ .resets = th1520_misc_resets, -+ .num = ARRAY_SIZE(th1520_misc_resets), -+}; -+ -+static const struct th1520_reset_data th1520_vi_reset_data = { -+ .resets = th1520_vi_resets, -+ .num = ARRAY_SIZE(th1520_vi_resets), -+}; -+ -+static const struct th1520_reset_data th1520_vp_reset_data = { -+ .resets = th1520_vp_resets, -+ .num = ARRAY_SIZE(th1520_vp_resets), -+}; -+ - static const struct of_device_id th1520_reset_match[] = { - { .compatible = "thead,th1520-reset", .data = &th1520_reset_data }, -+ { .compatible = "thead,th1520-reset-ap", .data = &th1520_ap_reset_data }, -+ { .compatible = "thead,th1520-reset-dsp", .data = &th1520_dsp_reset_data }, -+ { .compatible = "thead,th1520-reset-misc", .data = &th1520_misc_reset_data }, -+ { .compatible = "thead,th1520-reset-vi", .data = &th1520_vi_reset_data }, -+ { .compatible = "thead,th1520-reset-vp", .data = &th1520_vp_reset_data }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, th1520_reset_match); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch b/SPECS/linux-lts-kmhv2/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch new file mode 100644 index 0000000000..23a5e1bf51 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch @@ -0,0 +1,46 @@ +From 2c946683705fc6706119c588fd5499c0c91b2369 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 26 Dec 2025 16:31:59 +0800 +Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: drop useless spaces + +Previously, the I2C driver had an extra leading space in column 0 of +included header lines. This commit removes the redundant whitespace. + +Signed-off-by: Troy Mitchell +Reviewed-by: Alex Elder +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20251226-k1-i2c-ilcr-v5-1-b5807b7dd0e6@linux.spacemit.com +(cherry picked from commit 7b5073f9897f67af58b5bf17232bf60fc42e7ecd) +Signed-off-by: Han Gao +--- + drivers/i2c/busses/i2c-k1.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index afc6bdd68bd4..9152cf436bea 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -4,13 +4,13 @@ + */ + + #include +- #include +- #include +- #include +- #include +- #include +- #include +- #include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + + /* spacemit i2c registers */ + #define SPACEMIT_ICR 0x0 /* Control register */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0260-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch b/SPECS/linux-lts-kmhv2/0260-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch deleted file mode 100644 index ebe12f51cf..0000000000 --- a/SPECS/linux-lts-kmhv2/0260-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 58993e46afb677069983e73a6be1ea0562b65730 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Tue, 14 Oct 2025 13:10:32 +0000 -Subject: [PATCH 260/467] UPSTREAM: riscv: dts: thead: Add reset controllers of - more subsystems for TH1520 - -Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The -one for AO subsystem is marked as reserved, since it may be used by AON -firmware. - -Reviewed-by: Drew Fustini -Signed-off-by: Yao Zi -Signed-off-by: Drew Fustini -(cherry picked from commit d8a174babf649346b6dad6784ae1e9bc8417af71) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++ - 1 file changed, 37 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index c65b71d9a1b8..5e91dc1d2b9b 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -289,6 +289,12 @@ clint: timer@ffdc000000 { - <&cpu3_intc 3>, <&cpu3_intc 7>; - }; - -+ rst_vi: reset-controller@ffe4040100 { -+ compatible = "thead,th1520-reset-vi"; -+ reg = <0xff 0xe4040100 0x0 0x8>; -+ #reset-cells = <1>; -+ }; -+ - spi0: spi@ffe700c000 { - compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; - reg = <0xff 0xe700c000 0x0 0x1000>; -@@ -521,6 +527,18 @@ pwm: pwm@ffec01c000 { - #pwm-cells = <3>; - }; - -+ rst_misc: reset-controller@ffec02c000 { -+ compatible = "thead,th1520-reset-misc"; -+ reg = <0xff 0xec02c000 0x0 0x18>; -+ #reset-cells = <1>; -+ }; -+ -+ rst_vp: reset-controller@ffecc30000 { -+ compatible = "thead,th1520-reset-vp"; -+ reg = <0xff 0xecc30000 0x0 0x14>; -+ #reset-cells = <1>; -+ }; -+ - clk: clock-controller@ffef010000 { - compatible = "thead,th1520-clk-ap"; - reg = <0xff 0xef010000 0x0 0x1000>; -@@ -528,6 +546,18 @@ clk: clock-controller@ffef010000 { - #clock-cells = <1>; - }; - -+ rst_ap: reset-controller@ffef014000 { -+ compatible = "thead,th1520-reset-ap"; -+ reg = <0xff 0xef014000 0x0 0x1000>; -+ #reset-cells = <1>; -+ }; -+ -+ rst_dsp: reset-controller@ffef040028 { -+ compatible = "thead,th1520-reset-dsp"; -+ reg = <0xff 0xef040028 0x0 0x4>; -+ #reset-cells = <1>; -+ }; -+ - gpu: gpu@ffef400000 { - compatible = "thead,th1520-gpu", "img,img-bxm-4-64", - "img,img-rogue"; -@@ -766,6 +796,13 @@ aogpio: gpio-controller@0 { - }; - }; - -+ rst_ao: reset-controller@fffff44000 { -+ compatible = "thead,th1520-reset-ao"; -+ reg = <0xff 0xfff44000 0x0 0x2000>; -+ #reset-cells = <1>; -+ status = "reserved"; -+ }; -+ - padctrl_aosys: pinctrl@fffff4a000 { - compatible = "thead,th1520-pinctrl"; - reg = <0xff 0xfff4a000 0x0 0x2000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch b/SPECS/linux-lts-kmhv2/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch new file mode 100644 index 0000000000..dbb5d3dfe0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch @@ -0,0 +1,40 @@ +From fa80698856016bcd983f8ac31a38e4f108170879 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:49 +0100 +Subject: [RUYI PATCH] UPSTREAM: clk: at91: pmc: #undef field_{get,prep}() + before definition + +Prepare for the advent of globally available common field_get() and +field_prep() macros by undefining the symbols before defining local +variants. This prevents redefinition warnings from the C preprocessor +when introducing the common macros later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Alexandre Belloni +Acked-by: Stephen Boyd +Acked-by: Claudiu Beznea +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit dbfe51513aae6bace00cc390e11cb486a64a63d2) +Signed-off-by: Han Gao +--- + drivers/clk/at91/pmc.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h +index 5daa32c4cf25..78a87d31463e 100644 +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -117,7 +117,9 @@ struct at91_clk_pms { + unsigned int parent; + }; + ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) ++#undef field_prep + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + + #define ndck(a, s) (a[s - 1].id + 1) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0261-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch b/SPECS/linux-lts-kmhv2/0261-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch deleted file mode 100644 index 7b49003d10..0000000000 --- a/SPECS/linux-lts-kmhv2/0261-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 15b0da3632a0e43073d2d2875332dc913c17ce30 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Fri, 24 Apr 2026 16:20:32 +0800 -Subject: [PATCH 261/467] UPSTREAM: clk: spacemit: k3: mark top_dclk as - CLK_IS_CRITICAL - -top_dclk is the DDR bus clock. If it is gated by clk_disable_unused, -all memory-mapped bus transactions cease to function, causing DMA -engines to hang and general system instability. - -Mark it CLK_IS_CRITICAL so the CCF never gates it during the -unused clock sweep. - -Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") -Reviewed-by: Brian Masney -Signed-off-by: Troy Mitchell -Signed-off-by: Stephen Boyd -(cherry picked from commit 3e75021f615ceee8562e6455c335936b39929ffb) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index e98afd59f05c..bb8b75bdbdb3 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -846,7 +846,7 @@ static const struct clk_parent_data top_parents[] = { - CCU_PARENT_HW(pll6_d3), - }; - CCU_MUX_DIV_GATE_FC_DEFINE(top_dclk, top_parents, APMU_TOP_DCLK_CTRL, 5, 3, -- BIT(8), 2, 3, BIT(1), 0); -+ BIT(8), 2, 3, BIT(1), CLK_IS_CRITICAL); - - static const struct clk_parent_data ucie_parents[] = { - CCU_PARENT_HW(pll1_d8_307p2), --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0262-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch b/SPECS/linux-lts-kmhv2/0262-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch deleted file mode 100644 index 3d3549d028..0000000000 --- a/SPECS/linux-lts-kmhv2/0262-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch +++ /dev/null @@ -1,53 +0,0 @@ -From d025cd979cf997c3b4e7096ac8dddcdd81e4c90c Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Wed, 29 Apr 2026 17:00:50 +0800 -Subject: [PATCH 262/467] UPSTREAM: ASoC: spacemit: fix RX DMA params not set - when TX is running - -When TX is already running (SSCR_SSE is set), the hw_params callback -returns early before setting up DMA parameters for the RX stream. This -prevents the capture path from configuring its DMA data properly. - -Move the SSCR_SSE check after DMA parameter setup and format -constraints, so both TX and RX streams get their DMA configuration -regardless of whether the hardware is already enabled. The early return -now only skips the register writes that would disrupt an active stream. - -Fixes: fce217449075 ("ASoC: spacemit: add i2s support for K1 SoC") -Signed-off-by: Troy Mitchell -Link: https://patch.msgid.link/20260429-k1-i2s-fix-v2-1-8d67835aaddc@linux.spacemit.com -Signed-off-by: Mark Brown -(cherry picked from commit ec0611868f2fcf29e4c2bebdc6702d3e1f272fec) -Signed-off-by: Han Gao ---- - sound/soc/spacemit/k1_i2s.c | 7 +++---- - 1 file changed, 3 insertions(+), 4 deletions(-) - -diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c -index b48c57bede37..03cca5d84503 100644 ---- a/sound/soc/spacemit/k1_i2s.c -+++ b/sound/soc/spacemit/k1_i2s.c -@@ -148,10 +148,6 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, - u32 val; - int ret; - -- val = readl(i2s->base + SSCR); -- if (val & SSCR_SSE) -- return 0; -- - dma_data = &i2s->playback_dma_data; - - if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) -@@ -199,6 +195,9 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, - } - - val = readl(i2s->base + SSCR); -+ if (val & SSCR_SSE) -+ return 0; -+ - val &= ~SSCR_DW_32BYTE; - val |= data_width; - writel(val, i2s->base + SSCR); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch b/SPECS/linux-lts-kmhv2/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch new file mode 100644 index 0000000000..28c2c8a5db --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch @@ -0,0 +1,36 @@ +From 0443b117c46d5530b02f66cefa36882031ef8c7f Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:50 +0100 +Subject: [RUYI PATCH] UPSTREAM: crypto: qat - #undef field_get() before local + definition + +Prepare for the advent of a globally available common field_get() macro +by undefining the symbol before defining a local variant. This prevents +redefinition warnings from the C preprocessor when introducing the common +macro later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Giovanni Cabiddu +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 7996cbdb3f8472bc4286c776d3fa39cf0c20237a) +Signed-off-by: Han Gao +--- + drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c +index 69295a9ddf0a..6186fafb4a7b 100644 +--- a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c ++++ b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c +@@ -11,6 +11,7 @@ + * pm_scnprint_table(), making it not compile time constant, so the compile + * asserts from FIELD_GET() or u32_get_bits() won't be fulfilled. + */ ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + + #define PM_INFO_MAX_KEY_LEN 21 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch b/SPECS/linux-lts-kmhv2/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch new file mode 100644 index 0000000000..5bd7f8e544 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch @@ -0,0 +1,36 @@ +From 8d1903d76c78fd4c3f54ccb47a84b23de8c65c5a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:51 +0100 +Subject: [RUYI PATCH] UPSTREAM: EDAC/ie31200: #undef field_get() before local + definition + +Prepare for the advent of a globally available common field_get() macro +by undefining the symbol before defining a local variant. This prevents +redefinition warnings from the C preprocessor when introducing the common +macro later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Qiuxu Zhuo +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit d51b09a0feb63029be64226502cbcf53adc434b0) +Signed-off-by: Han Gao +--- + drivers/edac/ie31200_edac.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c +index 5a080ab65476..72290f430126 100644 +--- a/drivers/edac/ie31200_edac.c ++++ b/drivers/edac/ie31200_edac.c +@@ -140,6 +140,7 @@ + #define IE31200_CAPID0_ECC BIT(1) + + /* Non-constant mask variant of FIELD_GET() */ ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + + static int nr_channels; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0263-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch b/SPECS/linux-lts-kmhv2/0263-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch deleted file mode 100644 index 8c37a3b093..0000000000 --- a/SPECS/linux-lts-kmhv2/0263-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 695a3cc0b23ff691c0498a95c87551886e34dd5e Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Fri, 26 Dec 2025 16:31:59 +0800 -Subject: [PATCH 263/467] UPSTREAM: i2c: spacemit: drop useless spaces - -Previously, the I2C driver had an extra leading space in column 0 of -included header lines. This commit removes the redundant whitespace. - -Signed-off-by: Troy Mitchell -Reviewed-by: Alex Elder -Signed-off-by: Andi Shyti -Link: https://lore.kernel.org/r/20251226-k1-i2c-ilcr-v5-1-b5807b7dd0e6@linux.spacemit.com -(cherry picked from commit 7b5073f9897f67af58b5bf17232bf60fc42e7ecd) -Signed-off-by: Han Gao ---- - drivers/i2c/busses/i2c-k1.c | 14 +++++++------- - 1 file changed, 7 insertions(+), 7 deletions(-) - -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index afc6bdd68bd4..9152cf436bea 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -4,13 +4,13 @@ - */ - - #include -- #include -- #include -- #include -- #include -- #include -- #include -- #include -+#include -+#include -+#include -+#include -+#include -+#include -+#include - - /* spacemit i2c registers */ - #define SPACEMIT_ICR 0x0 /* Control register */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0264-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch b/SPECS/linux-lts-kmhv2/0264-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch deleted file mode 100644 index 0936955312..0000000000 --- a/SPECS/linux-lts-kmhv2/0264-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 03331389d49d55c643b7b13c9dcfefff41959a64 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:49 +0100 -Subject: [PATCH 264/467] UPSTREAM: clk: at91: pmc: #undef field_{get,prep}() - before definition - -Prepare for the advent of globally available common field_get() and -field_prep() macros by undefining the symbols before defining local -variants. This prevents redefinition warnings from the C preprocessor -when introducing the common macros later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Alexandre Belloni -Acked-by: Stephen Boyd -Acked-by: Claudiu Beznea -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit dbfe51513aae6bace00cc390e11cb486a64a63d2) -Signed-off-by: Han Gao ---- - drivers/clk/at91/pmc.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h -index 5daa32c4cf25..78a87d31463e 100644 ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -117,7 +117,9 @@ struct at91_clk_pms { - unsigned int parent; - }; - -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -+#undef field_prep - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - - #define ndck(a, s) (a[s - 1].id + 1) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch b/SPECS/linux-lts-kmhv2/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch new file mode 100644 index 0000000000..8d05fa846c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch @@ -0,0 +1,38 @@ +From 8490549e86aef53fa8416d6accaa31283186c10b Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:52 +0100 +Subject: [RUYI PATCH] UPSTREAM: gpio: aspeed: #undef field_{get,prep}() before + local definition + +Prepare for the advent of globally available common field_get() and +field_prep() macros by undefining the symbols before defining local +variants. This prevents redefinition warnings from the C preprocessor +when introducing the common macros later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Bartosz Golaszewski +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit d1e1a7271e97bf679d355777a10fa8c0dc259b86) +Signed-off-by: Han Gao +--- + drivers/gpio/gpio-aspeed.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c +index 3da37a0fda3f..6255b2080a41 100644 +--- a/drivers/gpio/gpio-aspeed.c ++++ b/drivers/gpio/gpio-aspeed.c +@@ -32,7 +32,9 @@ + #include "gpiolib.h" + + /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) ++#undef field_prep + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + + #define GPIO_G7_IRQ_STS_BASE 0x100 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0265-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch b/SPECS/linux-lts-kmhv2/0265-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch deleted file mode 100644 index 1b6177367f..0000000000 --- a/SPECS/linux-lts-kmhv2/0265-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 392241b97a7350e89982e3083de87d916d7823fe Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:50 +0100 -Subject: [PATCH 265/467] UPSTREAM: crypto: qat - #undef field_get() before - local definition - -Prepare for the advent of a globally available common field_get() macro -by undefining the symbol before defining a local variant. This prevents -redefinition warnings from the C preprocessor when introducing the common -macro later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Giovanni Cabiddu -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 7996cbdb3f8472bc4286c776d3fa39cf0c20237a) -Signed-off-by: Han Gao ---- - drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c -index 69295a9ddf0a..6186fafb4a7b 100644 ---- a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c -+++ b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c -@@ -11,6 +11,7 @@ - * pm_scnprint_table(), making it not compile time constant, so the compile - * asserts from FIELD_GET() or u32_get_bits() won't be fulfilled. - */ -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) - - #define PM_INFO_MAX_KEY_LEN 21 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch b/SPECS/linux-lts-kmhv2/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch new file mode 100644 index 0000000000..7595552488 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch @@ -0,0 +1,36 @@ +From 2fda7cbf1f4289cbb26b12faf98ad22cbbf1c6b6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:53 +0100 +Subject: [RUYI PATCH] UPSTREAM: iio: dac: ad3530r: #undef field_prep() before + local definition + +Prepare for the advent of a globally available common field_prep() macro +by undefining the symbol before defining a local variant. This prevents +redefinition warnings from the C preprocessor when introducing the common +macro later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Jonathan Cameron +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 27856d2b2b0f259ba261a3e3e028cc75a70ae817) +Signed-off-by: Han Gao +--- + drivers/iio/dac/ad3530r.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c +index 6134613777b8..5684d11137f2 100644 +--- a/drivers/iio/dac/ad3530r.c ++++ b/drivers/iio/dac/ad3530r.c +@@ -54,6 +54,7 @@ + #define AD3531R_MAX_CHANNELS 4 + + /* Non-constant mask variant of FIELD_PREP() */ ++#undef field_prep + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + + enum ad3530r_mode { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0266-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch b/SPECS/linux-lts-kmhv2/0266-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch deleted file mode 100644 index d0db5deaca..0000000000 --- a/SPECS/linux-lts-kmhv2/0266-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 6bfc62473ec56ec0afab933ca32873fe718bc7f2 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:51 +0100 -Subject: [PATCH 266/467] UPSTREAM: EDAC/ie31200: #undef field_get() before - local definition - -Prepare for the advent of a globally available common field_get() macro -by undefining the symbol before defining a local variant. This prevents -redefinition warnings from the C preprocessor when introducing the common -macro later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Qiuxu Zhuo -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit d51b09a0feb63029be64226502cbcf53adc434b0) -Signed-off-by: Han Gao ---- - drivers/edac/ie31200_edac.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c -index 5a080ab65476..72290f430126 100644 ---- a/drivers/edac/ie31200_edac.c -+++ b/drivers/edac/ie31200_edac.c -@@ -140,6 +140,7 @@ - #define IE31200_CAPID0_ECC BIT(1) - - /* Non-constant mask variant of FIELD_GET() */ -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) - - static int nr_channels; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch b/SPECS/linux-lts-kmhv2/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch new file mode 100644 index 0000000000..9deec2c78e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch @@ -0,0 +1,38 @@ +From a31ca7ca552212b34bea5cb3fcf52759dc2a28a0 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:54 +0100 +Subject: [RUYI PATCH] UPSTREAM: iio: mlx90614: #undef field_{get,prep}() + before local definition + +Prepare for the advent of globally available common field_get() and +field_prep() macros by undefining the symbols before defining local +variants. This prevents redefinition warnings from the C preprocessor +when introducing the common macros later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Jonathan Cameron +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 8a838dabf145818e67b304997c21a055dd5943dc) +Signed-off-by: Han Gao +--- + drivers/iio/temperature/mlx90614.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/iio/temperature/mlx90614.c b/drivers/iio/temperature/mlx90614.c +index 8a44a00bfd5e..de5615fdb396 100644 +--- a/drivers/iio/temperature/mlx90614.c ++++ b/drivers/iio/temperature/mlx90614.c +@@ -69,7 +69,9 @@ + #define MLX90614_CONST_FIR 0x7 /* Fixed value for FIR part of low pass filter */ + + /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) ++#undef field_prep + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + + struct mlx_chip_info { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0267-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch b/SPECS/linux-lts-kmhv2/0267-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch deleted file mode 100644 index 61221b73a7..0000000000 --- a/SPECS/linux-lts-kmhv2/0267-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 137405298c4f5336043e5c49266ff25e7485e66c Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:52 +0100 -Subject: [PATCH 267/467] UPSTREAM: gpio: aspeed: #undef field_{get,prep}() - before local definition - -Prepare for the advent of globally available common field_get() and -field_prep() macros by undefining the symbols before defining local -variants. This prevents redefinition warnings from the C preprocessor -when introducing the common macros later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Bartosz Golaszewski -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit d1e1a7271e97bf679d355777a10fa8c0dc259b86) -Signed-off-by: Han Gao ---- - drivers/gpio/gpio-aspeed.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c -index 3da37a0fda3f..6255b2080a41 100644 ---- a/drivers/gpio/gpio-aspeed.c -+++ b/drivers/gpio/gpio-aspeed.c -@@ -32,7 +32,9 @@ - #include "gpiolib.h" - - /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -+#undef field_prep - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - - #define GPIO_G7_IRQ_STS_BASE 0x100 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch b/SPECS/linux-lts-kmhv2/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch new file mode 100644 index 0000000000..747d0f1115 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch @@ -0,0 +1,38 @@ +From 92ba8033d4f60d619ebeb8f1f465e68d66004e81 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:55 +0100 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: ma35: #undef field_{get,prep}() + before local definition + +Prepare for the advent of globally available common field_get() and +field_prep() macros by undefining the symbols before defining local +variants. This prevents redefinition warnings from the C preprocessor +when introducing the common macros later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Linus Walleij +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 2fc00c008e9043ca66b711cc0df78a4d94da2e34) +Signed-off-by: Han Gao +--- + drivers/pinctrl/nuvoton/pinctrl-ma35.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c +index cdad01d68a37..925dd717c9de 100644 +--- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c ++++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c +@@ -82,7 +82,9 @@ + #define MVOLT_3300 1 + + /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) ++#undef field_prep + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + + static const char * const gpio_group_name[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0268-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch b/SPECS/linux-lts-kmhv2/0268-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch deleted file mode 100644 index 85b6350ba6..0000000000 --- a/SPECS/linux-lts-kmhv2/0268-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch +++ /dev/null @@ -1,36 +0,0 @@ -From fa6237d944a588964130114d731d4b7480bb020d Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:53 +0100 -Subject: [PATCH 268/467] UPSTREAM: iio: dac: ad3530r: #undef field_prep() - before local definition - -Prepare for the advent of a globally available common field_prep() macro -by undefining the symbol before defining a local variant. This prevents -redefinition warnings from the C preprocessor when introducing the common -macro later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Jonathan Cameron -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 27856d2b2b0f259ba261a3e3e028cc75a70ae817) -Signed-off-by: Han Gao ---- - drivers/iio/dac/ad3530r.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c -index 6134613777b8..5684d11137f2 100644 ---- a/drivers/iio/dac/ad3530r.c -+++ b/drivers/iio/dac/ad3530r.c -@@ -54,6 +54,7 @@ - #define AD3531R_MAX_CHANNELS 4 - - /* Non-constant mask variant of FIELD_PREP() */ -+#undef field_prep - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - - enum ad3530r_mode { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch b/SPECS/linux-lts-kmhv2/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch new file mode 100644 index 0000000000..a8085f2c11 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch @@ -0,0 +1,36 @@ +From f43d3afeb48fc78d1fa9aec7aaaefdf6964e4b6c Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:56 +0100 +Subject: [RUYI PATCH] UPSTREAM: soc: renesas: rz-sysc: #undef field_get() + before local definition + +Prepare for the advent of a globally available common field_get() macro +by undefining the symbol before defining a local variant. This prevents +redefinition warnings from the C preprocessor when introducing the common +macro later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Claudiu Beznea +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 138ab44108fad96c22b381ebfb6936ab9787aedc) +Signed-off-by: Han Gao +--- + drivers/soc/renesas/rz-sysc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c +index 19c1e666279b..a1487195dc87 100644 +--- a/drivers/soc/renesas/rz-sysc.c ++++ b/drivers/soc/renesas/rz-sysc.c +@@ -16,6 +16,7 @@ + + #include "rz-sysc.h" + ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + + /** +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch b/SPECS/linux-lts-kmhv2/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch new file mode 100644 index 0000000000..ae69b76f2a --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch @@ -0,0 +1,38 @@ +From a743678cdf95c66206f1cefd74ad8f2e3157f680 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:57 +0100 +Subject: [RUYI PATCH] UPSTREAM: ALSA: usb-audio: #undef field_{get,prep}() + before local definition + +Prepare for the advent of globally available common field_get() and +field_prep() macros by undefining the symbols before defining local +variants. This prevents redefinition warnings from the C preprocessor +when introducing the common macros later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Takashi Iwai +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 85a8ff11853110e59396f97b3239db40cc89e08c) +Signed-off-by: Han Gao +--- + sound/usb/mixer_quirks.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c +index 7126a2cf9e79..bf8f97d43299 100644 +--- a/sound/usb/mixer_quirks.c ++++ b/sound/usb/mixer_quirks.c +@@ -3309,7 +3309,9 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) + #define RME_DIGIFACE_INVERT BIT(31) + + /* Nonconst helpers */ ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) ++#undef field_prep + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + + static int snd_rme_digiface_write_reg(struct snd_kcontrol *kcontrol, int item, u16 mask, u16 val) +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0269-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch b/SPECS/linux-lts-kmhv2/0269-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch deleted file mode 100644 index 98a708ccec..0000000000 --- a/SPECS/linux-lts-kmhv2/0269-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 37980b18b9c919ed290f5d9d31476b4b92d67a1d Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:54 +0100 -Subject: [PATCH 269/467] UPSTREAM: iio: mlx90614: #undef field_{get,prep}() - before local definition - -Prepare for the advent of globally available common field_get() and -field_prep() macros by undefining the symbols before defining local -variants. This prevents redefinition warnings from the C preprocessor -when introducing the common macros later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Jonathan Cameron -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 8a838dabf145818e67b304997c21a055dd5943dc) -Signed-off-by: Han Gao ---- - drivers/iio/temperature/mlx90614.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/iio/temperature/mlx90614.c b/drivers/iio/temperature/mlx90614.c -index 8a44a00bfd5e..de5615fdb396 100644 ---- a/drivers/iio/temperature/mlx90614.c -+++ b/drivers/iio/temperature/mlx90614.c -@@ -69,7 +69,9 @@ - #define MLX90614_CONST_FIR 0x7 /* Fixed value for FIR part of low pass filter */ - - /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -+#undef field_prep - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - - struct mlx_chip_info { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch b/SPECS/linux-lts-kmhv2/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch new file mode 100644 index 0000000000..9a78322adf --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch @@ -0,0 +1,111 @@ +From c59127e75e8cf8ce74f12bd0fe0bb2574674fbe4 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:00 +0100 +Subject: [RUYI PATCH] UPSTREAM: bitfield: Add less-checking + __FIELD_{GET,PREP}() + +The BUILD_BUG_ON_MSG() check against "~0ull" works only with "unsigned +(long) long" _mask types. For constant masks, that condition is usually +met, as GENMASK() yields an UL value. The few places where the +constant mask is stored in an intermediate variable were fixed by +changing the variable type to u64 (see e.g. [1] and [2]). + +However, for non-constant masks, smaller unsigned types should be valid, +too, but currently lead to "result of comparison of constant +18446744073709551615 with expression of type ... is always +false"-warnings with clang and W=1. + +Hence refactor the __BF_FIELD_CHECK() helper, and factor out +__FIELD_{GET,PREP}(). The later lack the single problematic check, but +are otherwise identical to FIELD_{GET,PREP}(), and are intended to be +used in the fully non-const variants later. + +[1] commit 5c667d5a5a3ec166 ("clk: sp7021: Adjust width of _m in + HWM_FIELD_PREP()") +[2] commit cfd6fb45cfaf46fa ("crypto: ccree - avoid out-of-range + warnings from clang") + +Signed-off-by: Geert Uytterhoeven +Link: https://git.kernel.org/torvalds/c/5c667d5a5a3ec166 [1] +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 2a6c045640c38a407a39cd40c3c4d8dd2fd89aa8) +Signed-off-by: Han Gao +--- + include/linux/bitfield.h | 36 ++++++++++++++++++++++++++++-------- + 1 file changed, 28 insertions(+), 8 deletions(-) + +diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h +index 5355f8f806a9..bf8e0ae4b5b4 100644 +--- a/include/linux/bitfield.h ++++ b/include/linux/bitfield.h +@@ -60,7 +60,7 @@ + + #define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x)) + +-#define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \ ++#define __BF_FIELD_CHECK_MASK(_mask, _val, _pfx) \ + ({ \ + BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ + _pfx "mask is not constant"); \ +@@ -69,13 +69,33 @@ + ~((_mask) >> __bf_shf(_mask)) & \ + (0 + (_val)) : 0, \ + _pfx "value too large for the field"); \ +- BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \ +- __bf_cast_unsigned(_reg, ~0ull), \ +- _pfx "type of reg too small for mask"); \ + __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \ + (1ULL << __bf_shf(_mask))); \ + }) + ++#define __BF_FIELD_CHECK_REG(mask, reg, pfx) \ ++ BUILD_BUG_ON_MSG(__bf_cast_unsigned(mask, mask) > \ ++ __bf_cast_unsigned(reg, ~0ull), \ ++ pfx "type of reg too small for mask") ++ ++#define __BF_FIELD_CHECK(mask, reg, val, pfx) \ ++ ({ \ ++ __BF_FIELD_CHECK_MASK(mask, val, pfx); \ ++ __BF_FIELD_CHECK_REG(mask, reg, pfx); \ ++ }) ++ ++#define __FIELD_PREP(mask, val, pfx) \ ++ ({ \ ++ __BF_FIELD_CHECK_MASK(mask, val, pfx); \ ++ ((typeof(mask))(val) << __bf_shf(mask)) & (mask); \ ++ }) ++ ++#define __FIELD_GET(mask, reg, pfx) \ ++ ({ \ ++ __BF_FIELD_CHECK_MASK(mask, 0U, pfx); \ ++ (typeof(mask))(((reg) & (mask)) >> __bf_shf(mask)); \ ++ }) ++ + /** + * FIELD_MAX() - produce the maximum value representable by a field + * @_mask: shifted mask defining the field's length and position +@@ -112,8 +132,8 @@ + */ + #define FIELD_PREP(_mask, _val) \ + ({ \ +- __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ +- ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ ++ __BF_FIELD_CHECK_REG(_mask, 0ULL, "FIELD_PREP: "); \ ++ __FIELD_PREP(_mask, _val, "FIELD_PREP: "); \ + }) + + #define __BF_CHECK_POW2(n) BUILD_BUG_ON_ZERO(((n) & ((n) - 1)) != 0) +@@ -152,8 +172,8 @@ + */ + #define FIELD_GET(_mask, _reg) \ + ({ \ +- __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \ +- (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ ++ __BF_FIELD_CHECK_REG(_mask, _reg, "FIELD_GET: "); \ ++ __FIELD_GET(_mask, _reg, "FIELD_GET: "); \ + }) + + /** +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0270-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch b/SPECS/linux-lts-kmhv2/0270-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch deleted file mode 100644 index ead3cb8e47..0000000000 --- a/SPECS/linux-lts-kmhv2/0270-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 5ec1150af9a71fda593306905af42d92479e2e05 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:55 +0100 -Subject: [PATCH 270/467] UPSTREAM: pinctrl: ma35: #undef field_{get,prep}() - before local definition - -Prepare for the advent of globally available common field_get() and -field_prep() macros by undefining the symbols before defining local -variants. This prevents redefinition warnings from the C preprocessor -when introducing the common macros later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Linus Walleij -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 2fc00c008e9043ca66b711cc0df78a4d94da2e34) -Signed-off-by: Han Gao ---- - drivers/pinctrl/nuvoton/pinctrl-ma35.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c -index cdad01d68a37..925dd717c9de 100644 ---- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c -+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c -@@ -82,7 +82,9 @@ - #define MVOLT_3300 1 - - /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -+#undef field_prep - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - - static const char * const gpio_group_name[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch b/SPECS/linux-lts-kmhv2/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch new file mode 100644 index 0000000000..68212a5dda --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch @@ -0,0 +1,122 @@ +From 9508a0e99753a0d15b30509ead3b2314fe5d2572 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:01 +0100 +Subject: [RUYI PATCH] UPSTREAM: bitfield: Add non-constant field_{prep,get}() + helpers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The existing FIELD_{GET,PREP}() macros are limited to compile-time +constants. However, it is very common to prepare or extract bitfield +elements where the bitfield mask is not a compile-time constant. + +To avoid this limitation, the AT91 clock driver and several other +drivers already have their own non-const field_{prep,get}() macros. +Make them available for general use by adding them to +, and improve them slightly: + 1. Avoid evaluating macro parameters more than once, + 2. Replace "ffs() - 1" by "__ffs()", + 3. Support 64-bit use on 32-bit architectures, + 4. Wire field_{get,prep}() to FIELD_{GET,PREP}() when mask is + actually constant. + +This is deliberately not merged into the existing FIELD_{GET,PREP}() +macros, as people expressed the desire to keep stricter variants for +increased safety, or for performance critical paths. + +Yury: use __mask withing new macros. + +Signed-off-by: Geert Uytterhoeven +Acked-by: Alexandre Belloni +Acked-by: Jonathan Cameron +Acked-by: Crt Mori +Acked-by: Nuno Sá +Acked-by: Richard Genoud +Reviewed-by: Andy Shevchenko +Reviewed-by: Yury Norov (NVIDIA) +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit c1c6ab80b25c8db1e2ef5ae3ac8075d2c242ae13) +Signed-off-by: Han Gao +--- + include/linux/bitfield.h | 59 ++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 59 insertions(+) + +diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h +index bf8e0ae4b5b4..126dc5b380af 100644 +--- a/include/linux/bitfield.h ++++ b/include/linux/bitfield.h +@@ -17,6 +17,7 @@ + * FIELD_{GET,PREP} macros take as first parameter shifted mask + * from which they extract the base mask and shift amount. + * Mask must be a compilation time constant. ++ * field_{get,prep} are variants that take a non-const mask. + * + * Example: + * +@@ -240,4 +241,62 @@ __MAKE_OP(64) + #undef __MAKE_OP + #undef ____MAKE_OP + ++#define __field_prep(mask, val) \ ++ ({ \ ++ __auto_type __mask = (mask); \ ++ typeof(__mask) __val = (val); \ ++ unsigned int __shift = BITS_PER_TYPE(__mask) <= 32 ? \ ++ __ffs(__mask) : __ffs64(__mask); \ ++ (__val << __shift) & __mask; \ ++ }) ++ ++#define __field_get(mask, reg) \ ++ ({ \ ++ __auto_type __mask = (mask); \ ++ typeof(__mask) __reg = (reg); \ ++ unsigned int __shift = BITS_PER_TYPE(__mask) <= 32 ? \ ++ __ffs(__mask) : __ffs64(__mask); \ ++ (__reg & __mask) >> __shift; \ ++ }) ++ ++/** ++ * field_prep() - prepare a bitfield element ++ * @mask: shifted mask defining the field's length and position, must be ++ * non-zero ++ * @val: value to put in the field ++ * ++ * Return: field value masked and shifted to its final destination ++ * ++ * field_prep() masks and shifts up the value. The result should be ++ * combined with other fields of the bitfield using logical OR. ++ * Unlike FIELD_PREP(), @mask is not limited to a compile-time constant. ++ * Typical usage patterns are a value stored in a table, or calculated by ++ * shifting a constant by a variable number of bits. ++ * If you want to ensure that @mask is a compile-time constant, please use ++ * FIELD_PREP() directly instead. ++ */ ++#define field_prep(mask, val) \ ++ (__builtin_constant_p(mask) ? __FIELD_PREP(mask, val, "field_prep: ") \ ++ : __field_prep(mask, val)) ++ ++/** ++ * field_get() - extract a bitfield element ++ * @mask: shifted mask defining the field's length and position, must be ++ * non-zero ++ * @reg: value of entire bitfield ++ * ++ * Return: extracted field value ++ * ++ * field_get() extracts the field specified by @mask from the ++ * bitfield passed in as @reg by masking and shifting it down. ++ * Unlike FIELD_GET(), @mask is not limited to a compile-time constant. ++ * Typical usage patterns are a value stored in a table, or calculated by ++ * shifting a constant by a variable number of bits. ++ * If you want to ensure that @mask is a compile-time constant, please use ++ * FIELD_GET() directly instead. ++ */ ++#define field_get(mask, reg) \ ++ (__builtin_constant_p(mask) ? __FIELD_GET(mask, reg, "field_get: ") \ ++ : __field_get(mask, reg)) ++ + #endif +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0271-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch b/SPECS/linux-lts-kmhv2/0271-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch deleted file mode 100644 index a86fd11345..0000000000 --- a/SPECS/linux-lts-kmhv2/0271-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 189ddb8df1658f8de6447a903b626df7170869eb Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:56 +0100 -Subject: [PATCH 271/467] UPSTREAM: soc: renesas: rz-sysc: #undef field_get() - before local definition - -Prepare for the advent of a globally available common field_get() macro -by undefining the symbol before defining a local variant. This prevents -redefinition warnings from the C preprocessor when introducing the common -macro later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Claudiu Beznea -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 138ab44108fad96c22b381ebfb6936ab9787aedc) -Signed-off-by: Han Gao ---- - drivers/soc/renesas/rz-sysc.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c -index 19c1e666279b..a1487195dc87 100644 ---- a/drivers/soc/renesas/rz-sysc.c -+++ b/drivers/soc/renesas/rz-sysc.c -@@ -16,6 +16,7 @@ - - #include "rz-sysc.h" - -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) - - /** --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0272-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch b/SPECS/linux-lts-kmhv2/0272-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch deleted file mode 100644 index 42d41b0ad2..0000000000 --- a/SPECS/linux-lts-kmhv2/0272-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 6293531e707d6e8a2b3ad5606ee2ed0e96173a30 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:57 +0100 -Subject: [PATCH 272/467] UPSTREAM: ALSA: usb-audio: #undef field_{get,prep}() - before local definition - -Prepare for the advent of globally available common field_get() and -field_prep() macros by undefining the symbols before defining local -variants. This prevents redefinition warnings from the C preprocessor -when introducing the common macros later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Takashi Iwai -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 85a8ff11853110e59396f97b3239db40cc89e08c) -Signed-off-by: Han Gao ---- - sound/usb/mixer_quirks.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c -index 7126a2cf9e79..bf8f97d43299 100644 ---- a/sound/usb/mixer_quirks.c -+++ b/sound/usb/mixer_quirks.c -@@ -3309,7 +3309,9 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) - #define RME_DIGIFACE_INVERT BIT(31) - - /* Nonconst helpers */ -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -+#undef field_prep - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - - static int snd_rme_digiface_write_reg(struct snd_kcontrol *kcontrol, int item, u16 mask, u16 val) --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch b/SPECS/linux-lts-kmhv2/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch new file mode 100644 index 0000000000..5f249092c8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch @@ -0,0 +1,52 @@ +From 7ab27d3da88e00fd0367baf7b18fb5484ac4fd65 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:02 +0100 +Subject: [RUYI PATCH] UPSTREAM: clk: at91: Convert to common + field_{get,prep}() helpers + +Drop the driver-specific field_get() and field_prep() macros, in favor +of the globally available variants from . + +Signed-off-by: Geert Uytterhoeven +Acked-by: Alexandre Belloni +Acked-by: Stephen Boyd +Acked-by: Claudiu Beznea +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 0f8407a1f1c795c417e4c7750654a6024a3ec68b) +Signed-off-by: Han Gao +--- + drivers/clk/at91/clk-peripheral.c | 1 + + drivers/clk/at91/pmc.h | 5 ----- + 2 files changed, 1 insertion(+), 5 deletions(-) + +diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c +index e700f40fd87f..e7208c47268b 100644 +--- a/drivers/clk/at91/clk-peripheral.c ++++ b/drivers/clk/at91/clk-peripheral.c +@@ -3,6 +3,7 @@ + * Copyright (C) 2013 Boris BREZILLON + */ + ++#include + #include + #include + #include +diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h +index 78a87d31463e..543d7aee8d24 100644 +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -117,11 +117,6 @@ struct at91_clk_pms { + unsigned int parent; + }; + +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +-#undef field_prep +-#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +- + #define ndck(a, s) (a[s - 1].id + 1) + #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0273-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch b/SPECS/linux-lts-kmhv2/0273-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch deleted file mode 100644 index 616035b685..0000000000 --- a/SPECS/linux-lts-kmhv2/0273-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch +++ /dev/null @@ -1,111 +0,0 @@ -From 61e3d11ff249dabbd495ec0164ee8a1425826bb9 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:00 +0100 -Subject: [PATCH 273/467] UPSTREAM: bitfield: Add less-checking - __FIELD_{GET,PREP}() - -The BUILD_BUG_ON_MSG() check against "~0ull" works only with "unsigned -(long) long" _mask types. For constant masks, that condition is usually -met, as GENMASK() yields an UL value. The few places where the -constant mask is stored in an intermediate variable were fixed by -changing the variable type to u64 (see e.g. [1] and [2]). - -However, for non-constant masks, smaller unsigned types should be valid, -too, but currently lead to "result of comparison of constant -18446744073709551615 with expression of type ... is always -false"-warnings with clang and W=1. - -Hence refactor the __BF_FIELD_CHECK() helper, and factor out -__FIELD_{GET,PREP}(). The later lack the single problematic check, but -are otherwise identical to FIELD_{GET,PREP}(), and are intended to be -used in the fully non-const variants later. - -[1] commit 5c667d5a5a3ec166 ("clk: sp7021: Adjust width of _m in - HWM_FIELD_PREP()") -[2] commit cfd6fb45cfaf46fa ("crypto: ccree - avoid out-of-range - warnings from clang") - -Signed-off-by: Geert Uytterhoeven -Link: https://git.kernel.org/torvalds/c/5c667d5a5a3ec166 [1] -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 2a6c045640c38a407a39cd40c3c4d8dd2fd89aa8) -Signed-off-by: Han Gao ---- - include/linux/bitfield.h | 36 ++++++++++++++++++++++++++++-------- - 1 file changed, 28 insertions(+), 8 deletions(-) - -diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h -index 5355f8f806a9..bf8e0ae4b5b4 100644 ---- a/include/linux/bitfield.h -+++ b/include/linux/bitfield.h -@@ -60,7 +60,7 @@ - - #define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x)) - --#define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \ -+#define __BF_FIELD_CHECK_MASK(_mask, _val, _pfx) \ - ({ \ - BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ - _pfx "mask is not constant"); \ -@@ -69,13 +69,33 @@ - ~((_mask) >> __bf_shf(_mask)) & \ - (0 + (_val)) : 0, \ - _pfx "value too large for the field"); \ -- BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \ -- __bf_cast_unsigned(_reg, ~0ull), \ -- _pfx "type of reg too small for mask"); \ - __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \ - (1ULL << __bf_shf(_mask))); \ - }) - -+#define __BF_FIELD_CHECK_REG(mask, reg, pfx) \ -+ BUILD_BUG_ON_MSG(__bf_cast_unsigned(mask, mask) > \ -+ __bf_cast_unsigned(reg, ~0ull), \ -+ pfx "type of reg too small for mask") -+ -+#define __BF_FIELD_CHECK(mask, reg, val, pfx) \ -+ ({ \ -+ __BF_FIELD_CHECK_MASK(mask, val, pfx); \ -+ __BF_FIELD_CHECK_REG(mask, reg, pfx); \ -+ }) -+ -+#define __FIELD_PREP(mask, val, pfx) \ -+ ({ \ -+ __BF_FIELD_CHECK_MASK(mask, val, pfx); \ -+ ((typeof(mask))(val) << __bf_shf(mask)) & (mask); \ -+ }) -+ -+#define __FIELD_GET(mask, reg, pfx) \ -+ ({ \ -+ __BF_FIELD_CHECK_MASK(mask, 0U, pfx); \ -+ (typeof(mask))(((reg) & (mask)) >> __bf_shf(mask)); \ -+ }) -+ - /** - * FIELD_MAX() - produce the maximum value representable by a field - * @_mask: shifted mask defining the field's length and position -@@ -112,8 +132,8 @@ - */ - #define FIELD_PREP(_mask, _val) \ - ({ \ -- __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ -- ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ -+ __BF_FIELD_CHECK_REG(_mask, 0ULL, "FIELD_PREP: "); \ -+ __FIELD_PREP(_mask, _val, "FIELD_PREP: "); \ - }) - - #define __BF_CHECK_POW2(n) BUILD_BUG_ON_ZERO(((n) & ((n) - 1)) != 0) -@@ -152,8 +172,8 @@ - */ - #define FIELD_GET(_mask, _reg) \ - ({ \ -- __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \ -- (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ -+ __BF_FIELD_CHECK_REG(_mask, _reg, "FIELD_GET: "); \ -+ __FIELD_GET(_mask, _reg, "FIELD_GET: "); \ - }) - - /** --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch b/SPECS/linux-lts-kmhv2/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch new file mode 100644 index 0000000000..ad7e2a30bc --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch @@ -0,0 +1,46 @@ +From e7cc1307805b330990170342cd2e17a4790cae37 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:03 +0100 +Subject: [RUYI PATCH] UPSTREAM: crypto: qat - convert to common field_get() + helper + +Drop the driver-specific field_get() macro, in favor of the globally +available variant from . + +Signed-off-by: Geert Uytterhoeven +Acked-by: Giovanni Cabiddu +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 350f06c9e2c97aca009fa10e8636ecf297ccd330) +Signed-off-by: Han Gao +--- + drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c | 9 +-------- + 1 file changed, 1 insertion(+), 8 deletions(-) + +diff --git a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c +index 6186fafb4a7b..4ccc94ed9493 100644 +--- a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c ++++ b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c +@@ -1,19 +1,12 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* Copyright(c) 2025 Intel Corporation */ ++#include + #include + #include + #include + + #include "adf_pm_dbgfs_utils.h" + +-/* +- * This is needed because a variable is used to index the mask at +- * pm_scnprint_table(), making it not compile time constant, so the compile +- * asserts from FIELD_GET() or u32_get_bits() won't be fulfilled. +- */ +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +- + #define PM_INFO_MAX_KEY_LEN 21 + + static int pm_scnprint_table(char *buff, const struct pm_status_row *table, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch b/SPECS/linux-lts-kmhv2/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch new file mode 100644 index 0000000000..15800bac47 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch @@ -0,0 +1,44 @@ +From 435c6fcc72eff501ecd29fabd2fedec939c67aa6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:04 +0100 +Subject: [RUYI PATCH] UPSTREAM: EDAC/ie31200: Convert to common field_get() + helper + +Drop the driver-specific field_get() macro, in favor of the globally +available variant from . + +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Qiuxu Zhuo +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 331a1457d8d5d233435633fcea116abeb775c4b4) +Signed-off-by: Han Gao +--- + drivers/edac/ie31200_edac.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c +index 72290f430126..dfc9a9cecd74 100644 +--- a/drivers/edac/ie31200_edac.c ++++ b/drivers/edac/ie31200_edac.c +@@ -44,6 +44,7 @@ + * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. + */ + ++#include + #include + #include + #include +@@ -139,10 +140,6 @@ + #define IE31200_CAPID0_DDPCD BIT(6) + #define IE31200_CAPID0_ECC BIT(1) + +-/* Non-constant mask variant of FIELD_GET() */ +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +- + static int nr_channels; + static struct pci_dev *mci_pdev; + static int ie31200_registered = 1; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0274-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch b/SPECS/linux-lts-kmhv2/0274-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch deleted file mode 100644 index 7c6fbc972f..0000000000 --- a/SPECS/linux-lts-kmhv2/0274-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch +++ /dev/null @@ -1,122 +0,0 @@ -From e7e8f944057ad724dd477ac753b3c5b9c451fdcb Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:01 +0100 -Subject: [PATCH 274/467] UPSTREAM: bitfield: Add non-constant - field_{prep,get}() helpers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The existing FIELD_{GET,PREP}() macros are limited to compile-time -constants. However, it is very common to prepare or extract bitfield -elements where the bitfield mask is not a compile-time constant. - -To avoid this limitation, the AT91 clock driver and several other -drivers already have their own non-const field_{prep,get}() macros. -Make them available for general use by adding them to -, and improve them slightly: - 1. Avoid evaluating macro parameters more than once, - 2. Replace "ffs() - 1" by "__ffs()", - 3. Support 64-bit use on 32-bit architectures, - 4. Wire field_{get,prep}() to FIELD_{GET,PREP}() when mask is - actually constant. - -This is deliberately not merged into the existing FIELD_{GET,PREP}() -macros, as people expressed the desire to keep stricter variants for -increased safety, or for performance critical paths. - -Yury: use __mask withing new macros. - -Signed-off-by: Geert Uytterhoeven -Acked-by: Alexandre Belloni -Acked-by: Jonathan Cameron -Acked-by: Crt Mori -Acked-by: Nuno Sá -Acked-by: Richard Genoud -Reviewed-by: Andy Shevchenko -Reviewed-by: Yury Norov (NVIDIA) -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit c1c6ab80b25c8db1e2ef5ae3ac8075d2c242ae13) -Signed-off-by: Han Gao ---- - include/linux/bitfield.h | 59 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 59 insertions(+) - -diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h -index bf8e0ae4b5b4..126dc5b380af 100644 ---- a/include/linux/bitfield.h -+++ b/include/linux/bitfield.h -@@ -17,6 +17,7 @@ - * FIELD_{GET,PREP} macros take as first parameter shifted mask - * from which they extract the base mask and shift amount. - * Mask must be a compilation time constant. -+ * field_{get,prep} are variants that take a non-const mask. - * - * Example: - * -@@ -240,4 +241,62 @@ __MAKE_OP(64) - #undef __MAKE_OP - #undef ____MAKE_OP - -+#define __field_prep(mask, val) \ -+ ({ \ -+ __auto_type __mask = (mask); \ -+ typeof(__mask) __val = (val); \ -+ unsigned int __shift = BITS_PER_TYPE(__mask) <= 32 ? \ -+ __ffs(__mask) : __ffs64(__mask); \ -+ (__val << __shift) & __mask; \ -+ }) -+ -+#define __field_get(mask, reg) \ -+ ({ \ -+ __auto_type __mask = (mask); \ -+ typeof(__mask) __reg = (reg); \ -+ unsigned int __shift = BITS_PER_TYPE(__mask) <= 32 ? \ -+ __ffs(__mask) : __ffs64(__mask); \ -+ (__reg & __mask) >> __shift; \ -+ }) -+ -+/** -+ * field_prep() - prepare a bitfield element -+ * @mask: shifted mask defining the field's length and position, must be -+ * non-zero -+ * @val: value to put in the field -+ * -+ * Return: field value masked and shifted to its final destination -+ * -+ * field_prep() masks and shifts up the value. The result should be -+ * combined with other fields of the bitfield using logical OR. -+ * Unlike FIELD_PREP(), @mask is not limited to a compile-time constant. -+ * Typical usage patterns are a value stored in a table, or calculated by -+ * shifting a constant by a variable number of bits. -+ * If you want to ensure that @mask is a compile-time constant, please use -+ * FIELD_PREP() directly instead. -+ */ -+#define field_prep(mask, val) \ -+ (__builtin_constant_p(mask) ? __FIELD_PREP(mask, val, "field_prep: ") \ -+ : __field_prep(mask, val)) -+ -+/** -+ * field_get() - extract a bitfield element -+ * @mask: shifted mask defining the field's length and position, must be -+ * non-zero -+ * @reg: value of entire bitfield -+ * -+ * Return: extracted field value -+ * -+ * field_get() extracts the field specified by @mask from the -+ * bitfield passed in as @reg by masking and shifting it down. -+ * Unlike FIELD_GET(), @mask is not limited to a compile-time constant. -+ * Typical usage patterns are a value stored in a table, or calculated by -+ * shifting a constant by a variable number of bits. -+ * If you want to ensure that @mask is a compile-time constant, please use -+ * FIELD_GET() directly instead. -+ */ -+#define field_get(mask, reg) \ -+ (__builtin_constant_p(mask) ? __FIELD_GET(mask, reg, "field_get: ") \ -+ : __field_get(mask, reg)) -+ - #endif --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0275-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch b/SPECS/linux-lts-kmhv2/0275-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch deleted file mode 100644 index 5b6ce03e18..0000000000 --- a/SPECS/linux-lts-kmhv2/0275-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch +++ /dev/null @@ -1,52 +0,0 @@ -From ee4a40739254d7da1f8363a89f53765733b99b28 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:02 +0100 -Subject: [PATCH 275/467] UPSTREAM: clk: at91: Convert to common - field_{get,prep}() helpers - -Drop the driver-specific field_get() and field_prep() macros, in favor -of the globally available variants from . - -Signed-off-by: Geert Uytterhoeven -Acked-by: Alexandre Belloni -Acked-by: Stephen Boyd -Acked-by: Claudiu Beznea -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 0f8407a1f1c795c417e4c7750654a6024a3ec68b) -Signed-off-by: Han Gao ---- - drivers/clk/at91/clk-peripheral.c | 1 + - drivers/clk/at91/pmc.h | 5 ----- - 2 files changed, 1 insertion(+), 5 deletions(-) - -diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c -index e700f40fd87f..e7208c47268b 100644 ---- a/drivers/clk/at91/clk-peripheral.c -+++ b/drivers/clk/at91/clk-peripheral.c -@@ -3,6 +3,7 @@ - * Copyright (C) 2013 Boris BREZILLON - */ - -+#include - #include - #include - #include -diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h -index 78a87d31463e..543d7aee8d24 100644 ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -117,11 +117,6 @@ struct at91_clk_pms { - unsigned int parent; - }; - --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) --#undef field_prep --#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -- - #define ndck(a, s) (a[s - 1].id + 1) - #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch b/SPECS/linux-lts-kmhv2/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch new file mode 100644 index 0000000000..8bbf1a93ec --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch @@ -0,0 +1,45 @@ +From d812b182981498ab3054a3c64531710d096f4e8a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:05 +0100 +Subject: [RUYI PATCH] UPSTREAM: gpio: aspeed: Convert to common + field_{get,prep}() helpers + +Drop the driver-specific field_get() and field_prep() macros, in favor +of the globally available variants from . + +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 2ef26ba8192c6ef49dd9ed1a95f990c438085517) +Signed-off-by: Han Gao +--- + drivers/gpio/gpio-aspeed.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c +index 6255b2080a41..37f2543e3909 100644 +--- a/drivers/gpio/gpio-aspeed.c ++++ b/drivers/gpio/gpio-aspeed.c +@@ -5,6 +5,7 @@ + * Joel Stanley + */ + ++#include + #include + #include + #include +@@ -31,12 +32,6 @@ + #include + #include "gpiolib.h" + +-/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +-#undef field_prep +-#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +- + #define GPIO_G7_IRQ_STS_BASE 0x100 + #define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4) + #define GPIO_G7_CTRL_REG_BASE 0x180 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0276-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch b/SPECS/linux-lts-kmhv2/0276-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch deleted file mode 100644 index 98b12e48bb..0000000000 --- a/SPECS/linux-lts-kmhv2/0276-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 7a384b9f65e72b723c2c45d4d331ac597edb9b2a Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:03 +0100 -Subject: [PATCH 276/467] UPSTREAM: crypto: qat - convert to common field_get() - helper - -Drop the driver-specific field_get() macro, in favor of the globally -available variant from . - -Signed-off-by: Geert Uytterhoeven -Acked-by: Giovanni Cabiddu -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 350f06c9e2c97aca009fa10e8636ecf297ccd330) -Signed-off-by: Han Gao ---- - drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c | 9 +-------- - 1 file changed, 1 insertion(+), 8 deletions(-) - -diff --git a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c -index 6186fafb4a7b..4ccc94ed9493 100644 ---- a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c -+++ b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c -@@ -1,19 +1,12 @@ - // SPDX-License-Identifier: GPL-2.0-only - /* Copyright(c) 2025 Intel Corporation */ -+#include - #include - #include - #include - - #include "adf_pm_dbgfs_utils.h" - --/* -- * This is needed because a variable is used to index the mask at -- * pm_scnprint_table(), making it not compile time constant, so the compile -- * asserts from FIELD_GET() or u32_get_bits() won't be fulfilled. -- */ --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -- - #define PM_INFO_MAX_KEY_LEN 21 - - static int pm_scnprint_table(char *buff, const struct pm_status_row *table, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch b/SPECS/linux-lts-kmhv2/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch new file mode 100644 index 0000000000..0c7f9de5cc --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch @@ -0,0 +1,36 @@ +From 8c762e56b97e2dfa47081feffdf43f03d3f977e5 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:06 +0100 +Subject: [RUYI PATCH] UPSTREAM: iio: dac: Convert to common field_prep() + helper + +Drop the driver-specific field_prep() macro, in favor of the globally +available variant from . + +Signed-off-by: Geert Uytterhoeven +Acked-by: Jonathan Cameron +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 54bfd90ca3b41567cbfdac2f633ae329eb3a665a) +Signed-off-by: Han Gao +--- + drivers/iio/dac/ad3530r.c | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c +index 5684d11137f2..b97b46090d80 100644 +--- a/drivers/iio/dac/ad3530r.c ++++ b/drivers/iio/dac/ad3530r.c +@@ -53,10 +53,6 @@ + #define AD3530R_MAX_CHANNELS 8 + #define AD3531R_MAX_CHANNELS 4 + +-/* Non-constant mask variant of FIELD_PREP() */ +-#undef field_prep +-#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +- + enum ad3530r_mode { + AD3530R_NORMAL_OP, + AD3530R_POWERDOWN_1K, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0277-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch b/SPECS/linux-lts-kmhv2/0277-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch deleted file mode 100644 index 137572c73d..0000000000 --- a/SPECS/linux-lts-kmhv2/0277-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch +++ /dev/null @@ -1,44 +0,0 @@ -From ce4af8fd49443cd868f89dbe502bbcca49cd05dd Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:04 +0100 -Subject: [PATCH 277/467] UPSTREAM: EDAC/ie31200: Convert to common field_get() - helper - -Drop the driver-specific field_get() macro, in favor of the globally -available variant from . - -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Qiuxu Zhuo -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 331a1457d8d5d233435633fcea116abeb775c4b4) -Signed-off-by: Han Gao ---- - drivers/edac/ie31200_edac.c | 5 +---- - 1 file changed, 1 insertion(+), 4 deletions(-) - -diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c -index 72290f430126..dfc9a9cecd74 100644 ---- a/drivers/edac/ie31200_edac.c -+++ b/drivers/edac/ie31200_edac.c -@@ -44,6 +44,7 @@ - * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. - */ - -+#include - #include - #include - #include -@@ -139,10 +140,6 @@ - #define IE31200_CAPID0_DDPCD BIT(6) - #define IE31200_CAPID0_ECC BIT(1) - --/* Non-constant mask variant of FIELD_GET() */ --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -- - static int nr_channels; - static struct pci_dev *mci_pdev; - static int ie31200_registered = 1; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch b/SPECS/linux-lts-kmhv2/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch new file mode 100644 index 0000000000..5dec21e9bb --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch @@ -0,0 +1,47 @@ +From c7ea1c7ee160166a1ed64ca27681872c97335904 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:07 +0100 +Subject: [RUYI PATCH] UPSTREAM: iio: mlx90614: Convert to common + field_{get,prep}() helpers + +Drop the driver-specific field_get() and field_prep() macros, in favor +of the globally available variants from . + +Signed-off-by: Geert Uytterhoeven +Acked-by: Jonathan Cameron +Acked-by: Crt Mori +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 1fe1c28a108e4953f083c0106575ee0eccc296ae) +Signed-off-by: Han Gao +--- + drivers/iio/temperature/mlx90614.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +diff --git a/drivers/iio/temperature/mlx90614.c b/drivers/iio/temperature/mlx90614.c +index de5615fdb396..1ad21b73e1b4 100644 +--- a/drivers/iio/temperature/mlx90614.c ++++ b/drivers/iio/temperature/mlx90614.c +@@ -22,6 +22,7 @@ + * the "wakeup" GPIO is not given, power management will be disabled. + */ + ++#include + #include + #include + #include +@@ -68,12 +69,6 @@ + #define MLX90614_CONST_SCALE 20 /* Scale in milliKelvin (0.02 * 1000) */ + #define MLX90614_CONST_FIR 0x7 /* Fixed value for FIR part of low pass filter */ + +-/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +-#undef field_prep +-#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +- + struct mlx_chip_info { + /* EEPROM offsets with 16-bit data, MSB first */ + /* emissivity correction coefficient */ +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0278-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch b/SPECS/linux-lts-kmhv2/0278-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch deleted file mode 100644 index 071ded89ee..0000000000 --- a/SPECS/linux-lts-kmhv2/0278-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 60aa83cc5e5af809b2fd0c7b94edda8ab4da2eb1 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:05 +0100 -Subject: [PATCH 278/467] UPSTREAM: gpio: aspeed: Convert to common - field_{get,prep}() helpers - -Drop the driver-specific field_get() and field_prep() macros, in favor -of the globally available variants from . - -Signed-off-by: Geert Uytterhoeven -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 2ef26ba8192c6ef49dd9ed1a95f990c438085517) -Signed-off-by: Han Gao ---- - drivers/gpio/gpio-aspeed.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - -diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c -index 6255b2080a41..37f2543e3909 100644 ---- a/drivers/gpio/gpio-aspeed.c -+++ b/drivers/gpio/gpio-aspeed.c -@@ -5,6 +5,7 @@ - * Joel Stanley - */ - -+#include - #include - #include - #include -@@ -31,12 +32,6 @@ - #include - #include "gpiolib.h" - --/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) --#undef field_prep --#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -- - #define GPIO_G7_IRQ_STS_BASE 0x100 - #define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4) - #define GPIO_G7_CTRL_REG_BASE 0x180 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch b/SPECS/linux-lts-kmhv2/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch new file mode 100644 index 0000000000..d757b43507 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch @@ -0,0 +1,38 @@ +From 2cbda24297eace09de563cb06455c5936a00088e Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:08 +0100 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: ma35: Convert to common + field_{get,prep}() helpers + +Drop the driver-specific field_get() and field_prep() macros, in favor +of the globally available variants from . + +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Linus Walleij +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit bb0e7fda87753a973cb4a86c22905b1177f00d4e) +Signed-off-by: Han Gao +--- + drivers/pinctrl/nuvoton/pinctrl-ma35.c | 6 ------ + 1 file changed, 6 deletions(-) + +diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c +index 925dd717c9de..8d71dc53cc1d 100644 +--- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c ++++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c +@@ -81,12 +81,6 @@ + #define MVOLT_1800 0 + #define MVOLT_3300 1 + +-/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +-#undef field_prep +-#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +- + static const char * const gpio_group_name[] = { + "gpioa", "gpiob", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", + "gpioh", "gpioi", "gpioj", "gpiok", "gpiol", "gpiom", "gpion", +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0279-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch b/SPECS/linux-lts-kmhv2/0279-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch deleted file mode 100644 index 36b95a7cc1..0000000000 --- a/SPECS/linux-lts-kmhv2/0279-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 762f69a712f2a14242aa86c29e0cefe82355d45e Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:06 +0100 -Subject: [PATCH 279/467] UPSTREAM: iio: dac: Convert to common field_prep() - helper - -Drop the driver-specific field_prep() macro, in favor of the globally -available variant from . - -Signed-off-by: Geert Uytterhoeven -Acked-by: Jonathan Cameron -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 54bfd90ca3b41567cbfdac2f633ae329eb3a665a) -Signed-off-by: Han Gao ---- - drivers/iio/dac/ad3530r.c | 4 ---- - 1 file changed, 4 deletions(-) - -diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c -index 5684d11137f2..b97b46090d80 100644 ---- a/drivers/iio/dac/ad3530r.c -+++ b/drivers/iio/dac/ad3530r.c -@@ -53,10 +53,6 @@ - #define AD3530R_MAX_CHANNELS 8 - #define AD3531R_MAX_CHANNELS 4 - --/* Non-constant mask variant of FIELD_PREP() */ --#undef field_prep --#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -- - enum ad3530r_mode { - AD3530R_NORMAL_OP, - AD3530R_POWERDOWN_1K, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch b/SPECS/linux-lts-kmhv2/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch new file mode 100644 index 0000000000..f9d9f0c492 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch @@ -0,0 +1,43 @@ +From 8833c4b417190dce1a91dbf31da82221a266f133 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:09 +0100 +Subject: [RUYI PATCH] UPSTREAM: soc: renesas: rz-sysc: Convert to common + field_get() helper + +Drop the driver-specific field_get() macro, in favor of the globally +available variant from . + +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Claudiu Beznea +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 610c4408a2f7a09a00f656459e762ee1e21bbd7b) +Signed-off-by: Han Gao +--- + drivers/soc/renesas/rz-sysc.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c +index a1487195dc87..ae727d9c8cc5 100644 +--- a/drivers/soc/renesas/rz-sysc.c ++++ b/drivers/soc/renesas/rz-sysc.c +@@ -5,6 +5,7 @@ + * Copyright (C) 2024 Renesas Electronics Corp. + */ + ++#include + #include + #include + #include +@@ -16,9 +17,6 @@ + + #include "rz-sysc.h" + +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +- + /** + * struct rz_sysc - RZ SYSC private data structure + * @base: SYSC base address +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch b/SPECS/linux-lts-kmhv2/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch new file mode 100644 index 0000000000..9e36e61789 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch @@ -0,0 +1,38 @@ +From d565f3b6ace21a51f62812c86add16af8553952d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:10 +0100 +Subject: [RUYI PATCH] UPSTREAM: ALSA: usb-audio: Convert to common + field_{get,prep}() helpers + +Drop the driver-specific field_get() and field_prep() macros, in favor +of the globally available variants from . + +Signed-off-by: Geert Uytterhoeven +Acked-by: Takashi Iwai +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit b1cff2f4b2391a13bd3e9263502072df1ee5d035) +Signed-off-by: Han Gao +--- + sound/usb/mixer_quirks.c | 6 ------ + 1 file changed, 6 deletions(-) + +diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c +index bf8f97d43299..6069d9267c6c 100644 +--- a/sound/usb/mixer_quirks.c ++++ b/sound/usb/mixer_quirks.c +@@ -3308,12 +3308,6 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) + #define RME_DIGIFACE_REGISTER(reg, mask) (((reg) << 16) | (mask)) + #define RME_DIGIFACE_INVERT BIT(31) + +-/* Nonconst helpers */ +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +-#undef field_prep +-#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +- + static int snd_rme_digiface_write_reg(struct snd_kcontrol *kcontrol, int item, u16 mask, u16 val) + { + struct usb_mixer_elem_list *list = snd_kcontrol_chip(kcontrol); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0280-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch b/SPECS/linux-lts-kmhv2/0280-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch deleted file mode 100644 index 88ee4da2de..0000000000 --- a/SPECS/linux-lts-kmhv2/0280-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 2ddc0140e0d67f1413257af9982a7bc533c450f1 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:07 +0100 -Subject: [PATCH 280/467] UPSTREAM: iio: mlx90614: Convert to common - field_{get,prep}() helpers - -Drop the driver-specific field_get() and field_prep() macros, in favor -of the globally available variants from . - -Signed-off-by: Geert Uytterhoeven -Acked-by: Jonathan Cameron -Acked-by: Crt Mori -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 1fe1c28a108e4953f083c0106575ee0eccc296ae) -Signed-off-by: Han Gao ---- - drivers/iio/temperature/mlx90614.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - -diff --git a/drivers/iio/temperature/mlx90614.c b/drivers/iio/temperature/mlx90614.c -index de5615fdb396..1ad21b73e1b4 100644 ---- a/drivers/iio/temperature/mlx90614.c -+++ b/drivers/iio/temperature/mlx90614.c -@@ -22,6 +22,7 @@ - * the "wakeup" GPIO is not given, power management will be disabled. - */ - -+#include - #include - #include - #include -@@ -68,12 +69,6 @@ - #define MLX90614_CONST_SCALE 20 /* Scale in milliKelvin (0.02 * 1000) */ - #define MLX90614_CONST_FIR 0x7 /* Fixed value for FIR part of low pass filter */ - --/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) --#undef field_prep --#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -- - struct mlx_chip_info { - /* EEPROM offsets with 16-bit data, MSB first */ - /* emissivity correction coefficient */ --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch b/SPECS/linux-lts-kmhv2/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch new file mode 100644 index 0000000000..383627c806 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch @@ -0,0 +1,129 @@ +From 019a7bd0c854f0ec67ae6e379c46f05ccf4be4dd Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:13 +0100 +Subject: [RUYI PATCH] UPSTREAM: clk: renesas: Use bitfield helpers + +Use the FIELD_{GET,PREP}() and field_{get,prep}() helpers for const +respective non-const bitfields, instead of open-coding the same +operations. + +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Stephen Boyd +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 3937b05bb78f3ad1e8887b91b9a97ea05ac0a4a8) +Signed-off-by: Han Gao +--- + drivers/clk/renesas/clk-div6.c | 6 +++--- + drivers/clk/renesas/rcar-gen3-cpg.c | 15 +++++---------- + drivers/clk/renesas/rcar-gen4-cpg.c | 9 +++------ + 3 files changed, 11 insertions(+), 19 deletions(-) + +diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c +index 3abd6e5400ad..f7b827b5e9b2 100644 +--- a/drivers/clk/renesas/clk-div6.c ++++ b/drivers/clk/renesas/clk-div6.c +@@ -7,6 +7,7 @@ + * Contact: Laurent Pinchart + */ + ++#include + #include + #include + #include +@@ -171,8 +172,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) + if (clock->src_mask == 0) + return 0; + +- hw_index = (readl(clock->reg) & clock->src_mask) >> +- __ffs(clock->src_mask); ++ hw_index = field_get(clock->src_mask, readl(clock->reg)); + for (i = 0; i < clk_hw_get_num_parents(hw); i++) { + if (clock->parents[i] == hw_index) + return i; +@@ -191,7 +191,7 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) + if (index >= clk_hw_get_num_parents(hw)) + return -EINVAL; + +- src = clock->parents[index] << __ffs(clock->src_mask); ++ src = field_prep(clock->src_mask, clock->parents[index]); + writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg); + return 0; + } +diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c +index 10ae20489df9..b954278ddd9d 100644 +--- a/drivers/clk/renesas/rcar-gen3-cpg.c ++++ b/drivers/clk/renesas/rcar-gen3-cpg.c +@@ -54,10 +54,8 @@ static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, + { + struct cpg_pll_clk *pll_clk = to_pll_clk(hw); + unsigned int mult; +- u32 val; + +- val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; +- mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; ++ mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1; + + return parent_rate * mult * pll_clk->fixed_mult; + } +@@ -94,7 +92,7 @@ static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, + + val = readl(pll_clk->pllcr_reg); + val &= ~CPG_PLLnCR_STC_MASK; +- val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK); ++ val |= FIELD_PREP(CPG_PLLnCR_STC_MASK, mult - 1); + writel(val, pll_clk->pllcr_reg); + + for (i = 1000; i; i--) { +@@ -176,11 +174,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) + { + struct cpg_z_clk *zclk = to_z_clk(hw); +- unsigned int mult; +- u32 val; +- +- val = readl(zclk->reg) & zclk->mask; +- mult = 32 - (val >> __ffs(zclk->mask)); ++ unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, + 32 * zclk->fixed_div); +@@ -231,7 +225,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, + if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) + return -EBUSY; + +- cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); ++ cpg_reg_modify(zclk->reg, zclk->mask, ++ field_prep(zclk->mask, 32 - mult)); + + /* + * Set KICK bit in FRQCRB to update hardware setting and wait for +diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c +index fb9a876aaba5..db3a0b8ef2b9 100644 +--- a/drivers/clk/renesas/rcar-gen4-cpg.c ++++ b/drivers/clk/renesas/rcar-gen4-cpg.c +@@ -279,11 +279,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) + { + struct cpg_z_clk *zclk = to_z_clk(hw); +- unsigned int mult; +- u32 val; +- +- val = readl(zclk->reg) & zclk->mask; +- mult = 32 - (val >> __ffs(zclk->mask)); ++ unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, + 32 * zclk->fixed_div); +@@ -334,7 +330,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, + if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) + return -EBUSY; + +- cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); ++ cpg_reg_modify(zclk->reg, zclk->mask, ++ field_prep(zclk->mask, 32 - mult)); + + /* + * Set KICK bit in FRQCRB to update hardware setting and wait for +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0281-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch b/SPECS/linux-lts-kmhv2/0281-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch deleted file mode 100644 index f9a128bab3..0000000000 --- a/SPECS/linux-lts-kmhv2/0281-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 0eb5bae05723a59adbe4e3bbbab9ba880ecd2177 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:08 +0100 -Subject: [PATCH 281/467] UPSTREAM: pinctrl: ma35: Convert to common - field_{get,prep}() helpers - -Drop the driver-specific field_get() and field_prep() macros, in favor -of the globally available variants from . - -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Linus Walleij -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit bb0e7fda87753a973cb4a86c22905b1177f00d4e) -Signed-off-by: Han Gao ---- - drivers/pinctrl/nuvoton/pinctrl-ma35.c | 6 ------ - 1 file changed, 6 deletions(-) - -diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c -index 925dd717c9de..8d71dc53cc1d 100644 ---- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c -+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c -@@ -81,12 +81,6 @@ - #define MVOLT_1800 0 - #define MVOLT_3300 1 - --/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) --#undef field_prep --#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -- - static const char * const gpio_group_name[] = { - "gpioa", "gpiob", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", - "gpioh", "gpioi", "gpioj", "gpiok", "gpiol", "gpiom", "gpion", --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch b/SPECS/linux-lts-kmhv2/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch new file mode 100644 index 0000000000..4685894400 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch @@ -0,0 +1,40 @@ +From 23fef80ff6550ef4d1ece307b5c601d37a1fe71c Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:14 +0100 +Subject: [RUYI PATCH] UPSTREAM: soc: renesas: Use bitfield helpers + +Use the field_get() helper, instead of open-coding the same operation. + +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit c604cb5fdf0f569a9ce344a37a79958c3841396e) +Signed-off-by: Han Gao +--- + drivers/soc/renesas/renesas-soc.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c +index 1eb52356b996..ee4f17bb4db4 100644 +--- a/drivers/soc/renesas/renesas-soc.c ++++ b/drivers/soc/renesas/renesas-soc.c +@@ -5,6 +5,7 @@ + * Copyright (C) 2014-2016 Glider bvba + */ + ++#include + #include + #include + #include +@@ -524,8 +525,7 @@ static int __init renesas_soc_init(void) + eshi, eslo); + } + +- if (soc->id && +- ((product & id->mask) >> __ffs(id->mask)) != soc->id) { ++ if (soc->id && field_get(id->mask, product) != soc->id) { + pr_warn("SoC mismatch (product = 0x%x)\n", product); + ret = -ENODEV; + goto free_soc_dev_attr; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0282-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch b/SPECS/linux-lts-kmhv2/0282-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch deleted file mode 100644 index 53220f5a78..0000000000 --- a/SPECS/linux-lts-kmhv2/0282-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 8f99a7fa8c497ef1e8a0fc31678125daf8f04aef Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:09 +0100 -Subject: [PATCH 282/467] UPSTREAM: soc: renesas: rz-sysc: Convert to common - field_get() helper - -Drop the driver-specific field_get() macro, in favor of the globally -available variant from . - -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Claudiu Beznea -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 610c4408a2f7a09a00f656459e762ee1e21bbd7b) -Signed-off-by: Han Gao ---- - drivers/soc/renesas/rz-sysc.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - -diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c -index a1487195dc87..ae727d9c8cc5 100644 ---- a/drivers/soc/renesas/rz-sysc.c -+++ b/drivers/soc/renesas/rz-sysc.c -@@ -5,6 +5,7 @@ - * Copyright (C) 2024 Renesas Electronics Corp. - */ - -+#include - #include - #include - #include -@@ -16,9 +17,6 @@ - - #include "rz-sysc.h" - --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -- - /** - * struct rz_sysc - RZ SYSC private data structure - * @base: SYSC base address --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0283-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch b/SPECS/linux-lts-kmhv2/0283-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch deleted file mode 100644 index 2ff6a0b412..0000000000 --- a/SPECS/linux-lts-kmhv2/0283-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch +++ /dev/null @@ -1,38 +0,0 @@ -From a254a77e47af456314d9166e8c477362f99da854 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:10 +0100 -Subject: [PATCH 283/467] UPSTREAM: ALSA: usb-audio: Convert to common - field_{get,prep}() helpers - -Drop the driver-specific field_get() and field_prep() macros, in favor -of the globally available variants from . - -Signed-off-by: Geert Uytterhoeven -Acked-by: Takashi Iwai -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit b1cff2f4b2391a13bd3e9263502072df1ee5d035) -Signed-off-by: Han Gao ---- - sound/usb/mixer_quirks.c | 6 ------ - 1 file changed, 6 deletions(-) - -diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c -index bf8f97d43299..6069d9267c6c 100644 ---- a/sound/usb/mixer_quirks.c -+++ b/sound/usb/mixer_quirks.c -@@ -3308,12 +3308,6 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) - #define RME_DIGIFACE_REGISTER(reg, mask) (((reg) << 16) | (mask)) - #define RME_DIGIFACE_INVERT BIT(31) - --/* Nonconst helpers */ --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) --#undef field_prep --#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -- - static int snd_rme_digiface_write_reg(struct snd_kcontrol *kcontrol, int item, u16 mask, u16 val) - { - struct usb_mixer_elem_list *list = snd_kcontrol_chip(kcontrol); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch b/SPECS/linux-lts-kmhv2/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch new file mode 100644 index 0000000000..45f824af71 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch @@ -0,0 +1,96 @@ +From 56a298b59d7189961a4e6a04e449718ff2944c21 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 19 Mar 2026 07:51:03 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: Add support for Terminus + FE1.1s USB2.0 Hub controller + +Terminus FE1.1s is USB2.0 protocol compliant 4-port USB HUB, It support +MTT (Multiple Transaction Translator) mode, the upstream port supports +high-speed 480MHz and full-speed 12MHz modes, also has integrated 5V to +3.3V, 1.8V regulator and Power-On-Reset circuit. + +Introduce the DT binding for it. + +Link: https://terminus-usa.com/wp-content/uploads/2024/06/FE1.1s-Product-Brief-Rev.-2.0-2023.pdf [1] +Signed-off-by: Yixun Lan +Reviewed-by: Rob Herring (Arm) +Link: https://patch.msgid.link/20260319-03-usb-hub-fe1-v2-1-e4e26809dd7d@kernel.org +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit e972256f256c5ae908e15e2c6880f9144fbcae93) +Signed-off-by: Han Gao +--- + .../bindings/usb/terminus,fe11.yaml | 62 +++++++++++++++++++ + 1 file changed, 62 insertions(+) + create mode 100644 Documentation/devicetree/bindings/usb/terminus,fe11.yaml + +diff --git a/Documentation/devicetree/bindings/usb/terminus,fe11.yaml b/Documentation/devicetree/bindings/usb/terminus,fe11.yaml +new file mode 100644 +index 000000000000..645f97d73807 +--- /dev/null ++++ b/Documentation/devicetree/bindings/usb/terminus,fe11.yaml +@@ -0,0 +1,62 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/usb/terminus,fe11.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Terminus FE1.1/1.1S USB 2.0 Hub Controller ++ ++maintainers: ++ - Yixun Lan ++ ++allOf: ++ - $ref: usb-hub.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - usb1a40,0101 ++ ++ reg: true ++ ++ reset-gpios: ++ description: ++ GPIO controlling the RESET#. ++ ++ vdd-supply: ++ description: ++ Regulator supply to the hub, one of 3.3V or 5V can be chosen. ++ ++ ports: ++ $ref: /schemas/graph.yaml#/properties/ports ++ ++ patternProperties: ++ '^port@': ++ $ref: /schemas/graph.yaml#/properties/port ++ ++ properties: ++ reg: ++ minimum: 1 ++ maximum: 4 ++ ++required: ++ - compatible ++ - reg ++ - vdd-supply ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ usb { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hub@1 { ++ compatible = "usb1a40,0101"; ++ reg = <1>; ++ reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; ++ vdd-supply = <&vcc_5v>; ++ }; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0284-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch b/SPECS/linux-lts-kmhv2/0284-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch deleted file mode 100644 index c4a78ea5e6..0000000000 --- a/SPECS/linux-lts-kmhv2/0284-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch +++ /dev/null @@ -1,129 +0,0 @@ -From 40419cc775df729cfc32aee2a6b02c853ad42dd1 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:13 +0100 -Subject: [PATCH 284/467] UPSTREAM: clk: renesas: Use bitfield helpers - -Use the FIELD_{GET,PREP}() and field_{get,prep}() helpers for const -respective non-const bitfields, instead of open-coding the same -operations. - -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Stephen Boyd -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 3937b05bb78f3ad1e8887b91b9a97ea05ac0a4a8) -Signed-off-by: Han Gao ---- - drivers/clk/renesas/clk-div6.c | 6 +++--- - drivers/clk/renesas/rcar-gen3-cpg.c | 15 +++++---------- - drivers/clk/renesas/rcar-gen4-cpg.c | 9 +++------ - 3 files changed, 11 insertions(+), 19 deletions(-) - -diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c -index 3abd6e5400ad..f7b827b5e9b2 100644 ---- a/drivers/clk/renesas/clk-div6.c -+++ b/drivers/clk/renesas/clk-div6.c -@@ -7,6 +7,7 @@ - * Contact: Laurent Pinchart - */ - -+#include - #include - #include - #include -@@ -171,8 +172,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) - if (clock->src_mask == 0) - return 0; - -- hw_index = (readl(clock->reg) & clock->src_mask) >> -- __ffs(clock->src_mask); -+ hw_index = field_get(clock->src_mask, readl(clock->reg)); - for (i = 0; i < clk_hw_get_num_parents(hw); i++) { - if (clock->parents[i] == hw_index) - return i; -@@ -191,7 +191,7 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) - if (index >= clk_hw_get_num_parents(hw)) - return -EINVAL; - -- src = clock->parents[index] << __ffs(clock->src_mask); -+ src = field_prep(clock->src_mask, clock->parents[index]); - writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg); - return 0; - } -diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c -index 10ae20489df9..b954278ddd9d 100644 ---- a/drivers/clk/renesas/rcar-gen3-cpg.c -+++ b/drivers/clk/renesas/rcar-gen3-cpg.c -@@ -54,10 +54,8 @@ static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, - { - struct cpg_pll_clk *pll_clk = to_pll_clk(hw); - unsigned int mult; -- u32 val; - -- val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; -- mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; -+ mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1; - - return parent_rate * mult * pll_clk->fixed_mult; - } -@@ -94,7 +92,7 @@ static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, - - val = readl(pll_clk->pllcr_reg); - val &= ~CPG_PLLnCR_STC_MASK; -- val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK); -+ val |= FIELD_PREP(CPG_PLLnCR_STC_MASK, mult - 1); - writel(val, pll_clk->pllcr_reg); - - for (i = 1000; i; i--) { -@@ -176,11 +174,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) - { - struct cpg_z_clk *zclk = to_z_clk(hw); -- unsigned int mult; -- u32 val; -- -- val = readl(zclk->reg) & zclk->mask; -- mult = 32 - (val >> __ffs(zclk->mask)); -+ unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); - - return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, - 32 * zclk->fixed_div); -@@ -231,7 +225,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, - if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) - return -EBUSY; - -- cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); -+ cpg_reg_modify(zclk->reg, zclk->mask, -+ field_prep(zclk->mask, 32 - mult)); - - /* - * Set KICK bit in FRQCRB to update hardware setting and wait for -diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c -index fb9a876aaba5..db3a0b8ef2b9 100644 ---- a/drivers/clk/renesas/rcar-gen4-cpg.c -+++ b/drivers/clk/renesas/rcar-gen4-cpg.c -@@ -279,11 +279,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) - { - struct cpg_z_clk *zclk = to_z_clk(hw); -- unsigned int mult; -- u32 val; -- -- val = readl(zclk->reg) & zclk->mask; -- mult = 32 - (val >> __ffs(zclk->mask)); -+ unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); - - return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, - 32 * zclk->fixed_div); -@@ -334,7 +330,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, - if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) - return -EBUSY; - -- cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); -+ cpg_reg_modify(zclk->reg, zclk->mask, -+ field_prep(zclk->mask, 32 - mult)); - - /* - * Set KICK bit in FRQCRB to update hardware setting and wait for --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch b/SPECS/linux-lts-kmhv2/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch new file mode 100644 index 0000000000..d9fcc7fdbd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch @@ -0,0 +1,57 @@ +From 7cc16fe69696bb942fb6f1b9a227fd74082707ae Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 19 Mar 2026 07:51:04 +0000 +Subject: [RUYI PATCH] UPSTREAM: usb: misc: onboard_usb_dev: Add Terminus + FE1.1s USB2.0 Hub (1a40:0101) + +Terminus FE1.1s is USB2.0 protocol compliant 4-port USB HUB, It support +MTT (Multiple Transaction Translator) mode, the upstream port supports +high-speed 480MHz and full-speed 12MHz modes, also it has integrated 5V +to 3.3V/1.8V regulator and Power-On-Reset circuit. + +Link: https://terminus-usa.com/wp-content/uploads/2024/06/FE1.1s-Product-Brief-Rev.-2.0-2023.pdf [1] +Signed-off-by: Yixun Lan +Link: https://patch.msgid.link/20260319-03-usb-hub-fe1-v2-2-e4e26809dd7d@kernel.org +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 00b4fe5be06aecd6426930de86b7cffc2330f4b8) +Signed-off-by: Han Gao +--- + drivers/usb/misc/onboard_usb_dev.c | 2 ++ + drivers/usb/misc/onboard_usb_dev.h | 1 + + 2 files changed, 3 insertions(+) + +diff --git a/drivers/usb/misc/onboard_usb_dev.c b/drivers/usb/misc/onboard_usb_dev.c +index 41360a7591e5..40b2ebf45a9a 100644 +--- a/drivers/usb/misc/onboard_usb_dev.c ++++ b/drivers/usb/misc/onboard_usb_dev.c +@@ -570,6 +570,7 @@ static struct platform_driver onboard_dev_driver = { + #define VENDOR_ID_MICROCHIP 0x0424 + #define VENDOR_ID_PARADE 0x1da0 + #define VENDOR_ID_REALTEK 0x0bda ++#define VENDOR_ID_TERMINUS 0x1a40 + #define VENDOR_ID_TI 0x0451 + #define VENDOR_ID_VIA 0x2109 + #define VENDOR_ID_XMOS 0x20B1 +@@ -673,6 +674,7 @@ static const struct usb_device_id onboard_dev_id_table[] = { + { USB_DEVICE(VENDOR_ID_REALTEK, 0x0414) }, /* RTS5414 USB 3.2 HUB */ + { USB_DEVICE(VENDOR_ID_REALTEK, 0x5414) }, /* RTS5414 USB 2.1 HUB */ + { USB_DEVICE(VENDOR_ID_REALTEK, 0x0179) }, /* RTL8188ETV 2.4GHz WiFi */ ++ { USB_DEVICE(VENDOR_ID_TERMINUS, 0x0101) }, /* Terminus FE1.1s 2.0 HUB */ + { USB_DEVICE(VENDOR_ID_TI, 0x8025) }, /* TI USB8020B 3.0 HUB */ + { USB_DEVICE(VENDOR_ID_TI, 0x8027) }, /* TI USB8020B 2.0 HUB */ + { USB_DEVICE(VENDOR_ID_TI, 0x8140) }, /* TI USB8041 3.0 HUB */ +diff --git a/drivers/usb/misc/onboard_usb_dev.h b/drivers/usb/misc/onboard_usb_dev.h +index c1462be5526d..be234b5a97bb 100644 +--- a/drivers/usb/misc/onboard_usb_dev.h ++++ b/drivers/usb/misc/onboard_usb_dev.h +@@ -146,6 +146,7 @@ static const struct of_device_id onboard_dev_match[] = { + { .compatible = "usbbda,5411", .data = &realtek_rts5411_data, }, + { .compatible = "usbbda,414", .data = &realtek_rts5411_data, }, + { .compatible = "usbbda,5414", .data = &realtek_rts5411_data, }, ++ { .compatible = "usb1a40,0101", .data = &vialab_vl817_data, }, + { .compatible = "usb1da0,5511", .data = ¶de_ps5511_data, }, + { .compatible = "usb1da0,55a1", .data = ¶de_ps5511_data, }, + { .compatible = "usb2109,817", .data = &vialab_vl817_data, }, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch b/SPECS/linux-lts-kmhv2/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch new file mode 100644 index 0000000000..366e334f76 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch @@ -0,0 +1,96 @@ +From 3df7916fd6c198c8e58d6d4914ab06ebca3918bc Mon Sep 17 00:00:00 2001 +From: Nathan Chancellor +Date: Wed, 29 Apr 2026 20:38:17 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: Define + __riscv_copy_{,vec_}{words,bytes}_unaligned() using SYM_TYPED_FUNC_START + +After commit 67bdd7b01387 ("riscv: Split out measure_cycles() for +reuse") and commit c03ad15f7cf6 ("riscv: Reuse measure_cycles() in +check_vector_unaligned_access()"), there are CFI failure when booting +kernels with CONFIG_CFI=y: + + CFI failure at measure_cycles+0x38/0xe0 (target: __riscv_copy_words_unaligned+0x0/0x50; expected type: ...) + CFI failure at measure_cycles+0x38/0xe0 (target: __riscv_copy_vec_words_unaligned+0x0/0x24; expected type: ...) + +The __riscv_copy_*_unaligned() functions are now called indirectly but +they are not defined with SYM_TYPED_FUNC_START, which is required for +assembly functions called indirectly from C to pass CFI checking. Switch +to SYM_TYPED_FUNC_START to clear up the CFI failures. + +Fixes: 67bdd7b01387 ("riscv: Split out measure_cycles() for reuse") +Fixes: c03ad15f7cf6 ("riscv: Reuse measure_cycles() in check_vector_unaligned_access()") +Signed-off-by: Nathan Chancellor +Reviewed-by: Sami Tolvanen +Reviewed-by: Nam Cao +Link: https://patch.msgid.link/20260406-measure_cycles-cfi-failure-v1-1-03e0234ae02f@kernel.org +Signed-off-by: Paul Walmsley +(cherry picked from commit f2abc305aa93f5b12d5c929d7a9c1cf7d7fee8af) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/copy-unaligned.S | 5 +++-- + arch/riscv/kernel/vec-copy-unaligned.S | 5 +++-- + 2 files changed, 6 insertions(+), 4 deletions(-) + +diff --git a/arch/riscv/kernel/copy-unaligned.S b/arch/riscv/kernel/copy-unaligned.S +index 2b3d9398c113..90f3549621f7 100644 +--- a/arch/riscv/kernel/copy-unaligned.S ++++ b/arch/riscv/kernel/copy-unaligned.S +@@ -1,6 +1,7 @@ + /* SPDX-License-Identifier: GPL-2.0 */ + /* Copyright (C) 2023 Rivos Inc. */ + ++#include + #include + #include + +@@ -9,7 +10,7 @@ + /* void __riscv_copy_words_unaligned(void *, const void *, size_t) */ + /* Performs a memcpy without aligning buffers, using word loads and stores. */ + /* Note: The size is truncated to a multiple of 8 * SZREG */ +-SYM_FUNC_START(__riscv_copy_words_unaligned) ++SYM_TYPED_FUNC_START(__riscv_copy_words_unaligned) + andi a4, a2, ~((8*SZREG)-1) + beqz a4, 2f + add a3, a1, a4 +@@ -41,7 +42,7 @@ SYM_FUNC_END(__riscv_copy_words_unaligned) + /* void __riscv_copy_bytes_unaligned(void *, const void *, size_t) */ + /* Performs a memcpy without aligning buffers, using only byte accesses. */ + /* Note: The size is truncated to a multiple of 8 */ +-SYM_FUNC_START(__riscv_copy_bytes_unaligned) ++SYM_TYPED_FUNC_START(__riscv_copy_bytes_unaligned) + andi a4, a2, ~(8-1) + beqz a4, 2f + add a3, a1, a4 +diff --git a/arch/riscv/kernel/vec-copy-unaligned.S b/arch/riscv/kernel/vec-copy-unaligned.S +index 7ce4de6f6e69..361039f7b944 100644 +--- a/arch/riscv/kernel/vec-copy-unaligned.S ++++ b/arch/riscv/kernel/vec-copy-unaligned.S +@@ -2,6 +2,7 @@ + /* Copyright (C) 2024 Rivos Inc. */ + + #include ++#include + #include + #include + +@@ -16,7 +17,7 @@ + /* void __riscv_copy_vec_words_unaligned(void *, const void *, size_t) */ + /* Performs a memcpy without aligning buffers, using word loads and stores. */ + /* Note: The size is truncated to a multiple of WORD_EEW */ +-SYM_FUNC_START(__riscv_copy_vec_words_unaligned) ++SYM_TYPED_FUNC_START(__riscv_copy_vec_words_unaligned) + andi a4, a2, ~(WORD_EEW-1) + beqz a4, 2f + add a3, a1, a4 +@@ -38,7 +39,7 @@ SYM_FUNC_END(__riscv_copy_vec_words_unaligned) + /* void __riscv_copy_vec_bytes_unaligned(void *, const void *, size_t) */ + /* Performs a memcpy without aligning buffers, using only byte accesses. */ + /* Note: The size is truncated to a multiple of 8 */ +-SYM_FUNC_START(__riscv_copy_vec_bytes_unaligned) ++SYM_TYPED_FUNC_START(__riscv_copy_vec_bytes_unaligned) + andi a4, a2, ~(8-1) + beqz a4, 2f + add a3, a1, a4 +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0285-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch b/SPECS/linux-lts-kmhv2/0285-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch deleted file mode 100644 index d10c6a26d4..0000000000 --- a/SPECS/linux-lts-kmhv2/0285-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch +++ /dev/null @@ -1,40 +0,0 @@ -From fbb168fdc7492006a9f7780a6ec49834031eea6e Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:14 +0100 -Subject: [PATCH 285/467] UPSTREAM: soc: renesas: Use bitfield helpers - -Use the field_get() helper, instead of open-coding the same operation. - -Signed-off-by: Geert Uytterhoeven -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit c604cb5fdf0f569a9ce344a37a79958c3841396e) -Signed-off-by: Han Gao ---- - drivers/soc/renesas/renesas-soc.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c -index 1eb52356b996..ee4f17bb4db4 100644 ---- a/drivers/soc/renesas/renesas-soc.c -+++ b/drivers/soc/renesas/renesas-soc.c -@@ -5,6 +5,7 @@ - * Copyright (C) 2014-2016 Glider bvba - */ - -+#include - #include - #include - #include -@@ -524,8 +525,7 @@ static int __init renesas_soc_init(void) - eshi, eslo); - } - -- if (soc->id && -- ((product & id->mask) >> __ffs(id->mask)) != soc->id) { -+ if (soc->id && field_get(id->mask, product) != soc->id) { - pr_warn("SoC mismatch (product = 0x%x)\n", product); - ret = -ENODEV; - goto free_soc_dev_attr; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0286-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch b/SPECS/linux-lts-kmhv2/0286-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch deleted file mode 100644 index 0a3a2a1e7d..0000000000 --- a/SPECS/linux-lts-kmhv2/0286-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 42fe4e15f9f853b366dfddb9cd5fdda93c07db7b Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 19 Mar 2026 07:51:03 +0000 -Subject: [PATCH 286/467] UPSTREAM: dt-bindings: usb: Add support for Terminus - FE1.1s USB2.0 Hub controller - -Terminus FE1.1s is USB2.0 protocol compliant 4-port USB HUB, It support -MTT (Multiple Transaction Translator) mode, the upstream port supports -high-speed 480MHz and full-speed 12MHz modes, also has integrated 5V to -3.3V, 1.8V regulator and Power-On-Reset circuit. - -Introduce the DT binding for it. - -Link: https://terminus-usa.com/wp-content/uploads/2024/06/FE1.1s-Product-Brief-Rev.-2.0-2023.pdf [1] -Signed-off-by: Yixun Lan -Reviewed-by: Rob Herring (Arm) -Link: https://patch.msgid.link/20260319-03-usb-hub-fe1-v2-1-e4e26809dd7d@kernel.org -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit e972256f256c5ae908e15e2c6880f9144fbcae93) -Signed-off-by: Han Gao ---- - .../bindings/usb/terminus,fe11.yaml | 62 +++++++++++++++++++ - 1 file changed, 62 insertions(+) - create mode 100644 Documentation/devicetree/bindings/usb/terminus,fe11.yaml - -diff --git a/Documentation/devicetree/bindings/usb/terminus,fe11.yaml b/Documentation/devicetree/bindings/usb/terminus,fe11.yaml -new file mode 100644 -index 000000000000..645f97d73807 ---- /dev/null -+++ b/Documentation/devicetree/bindings/usb/terminus,fe11.yaml -@@ -0,0 +1,62 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/usb/terminus,fe11.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Terminus FE1.1/1.1S USB 2.0 Hub Controller -+ -+maintainers: -+ - Yixun Lan -+ -+allOf: -+ - $ref: usb-hub.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - usb1a40,0101 -+ -+ reg: true -+ -+ reset-gpios: -+ description: -+ GPIO controlling the RESET#. -+ -+ vdd-supply: -+ description: -+ Regulator supply to the hub, one of 3.3V or 5V can be chosen. -+ -+ ports: -+ $ref: /schemas/graph.yaml#/properties/ports -+ -+ patternProperties: -+ '^port@': -+ $ref: /schemas/graph.yaml#/properties/port -+ -+ properties: -+ reg: -+ minimum: 1 -+ maximum: 4 -+ -+required: -+ - compatible -+ - reg -+ - vdd-supply -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ usb { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hub@1 { -+ compatible = "usb1a40,0101"; -+ reg = <1>; -+ reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; -+ vdd-supply = <&vcc_5v>; -+ }; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch b/SPECS/linux-lts-kmhv2/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch new file mode 100644 index 0000000000..74474ab04e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch @@ -0,0 +1,39 @@ +From 2eae98ea7476677c8119a80ff9bf50c8a3600315 Mon Sep 17 00:00:00 2001 +From: Zhengyu He +Date: Thu, 21 May 2026 22:44:45 +0800 +Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: support SpacemiT + K3 + +Add the SpacemiT K3 QSPI compatible to the fsl-qspi binding. + +K3 and K1 use the same QSPI controller, so document the K3 compatible +with "spacemit,k1-qspi" as fallback. + +Signed-off-by: Cody Kang +Signed-off-by: Zhengyu He +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-1-52bce26e5fd8@gmail.com +Signed-off-by: Mark Brown +(cherry picked from commit 27cd2dde35b2c3b8659fa18f6a935c61fedee5c1) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml +index 1d10cfbad86c..504df31a4f90 100644 +--- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml ++++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml +@@ -20,6 +20,9 @@ properties: + - fsl,ls1021a-qspi + - fsl,ls2080a-qspi + - spacemit,k1-qspi ++ - items: ++ - const: spacemit,k3-qspi ++ - const: spacemit,k1-qspi + - items: + - enum: + - fsl,ls1043a-qspi +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch b/SPECS/linux-lts-kmhv2/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch new file mode 100644 index 0000000000..cee092d499 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch @@ -0,0 +1,45 @@ +From 4f4bff270953588decae0547de96ac02939beaad Mon Sep 17 00:00:00 2001 +From: Jiakai Xu +Date: Sun, 17 May 2026 12:44:14 +0000 +Subject: [RUYI PATCH] UPSTREAM: RISC-V: KVM: Fix NULL pointer dereference in + SBI v0.1 SEND_IPI handler + +The SBI v0.1 SEND_IPI handler iterates over the hart mask and calls +kvm_get_vcpu_by_id() to find the target vcpu for each set bit. When a +guest provides a hart mask containing bits for non-existent vcpu_ids, +kvm_get_vcpu_by_id() returns NULL, which is then unconditionally +dereferenced by kvm_riscv_vcpu_set_interrupt(), causing a kernel crash. + +Fix this by adding a NULL check before dereferencing the return value. +If the target vcpu is not found, skip it and continue processing the +remaining valid harts. + +Fixes: a046c2d8578c ("RISC-V: KVM: Reorganize SBI code by moving SBI v0.1 to its own file") +Signed-off-by: Jiakai Xu +Signed-off-by: Jiakai Xu +Assisted-by: OpenClaw:DeepSeek-V3.2 +Reviewed-by: Anup Patel +Link: https://lore.kernel.org/r/20260517124414.420919-1-xujiakai2025@iscas.ac.cn +Signed-off-by: Anup Patel +(cherry picked from commit fdb69d401967fd88d27982a7e4984b2a3a4f0314) +Signed-off-by: Han Gao +--- + arch/riscv/kvm/vcpu_sbi_v01.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c +index 368dfddd23d9..b6aef0e5ea57 100644 +--- a/arch/riscv/kvm/vcpu_sbi_v01.c ++++ b/arch/riscv/kvm/vcpu_sbi_v01.c +@@ -56,6 +56,8 @@ static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, + + for_each_set_bit(i, &hmask, BITS_PER_LONG) { + rvcpu = kvm_get_vcpu_by_id(vcpu->kvm, i); ++ if (!rvcpu) ++ continue; + ret = kvm_riscv_vcpu_set_interrupt(rvcpu, IRQ_VS_SOFT); + if (ret < 0) + break; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0287-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch b/SPECS/linux-lts-kmhv2/0287-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch deleted file mode 100644 index c3ed343dd6..0000000000 --- a/SPECS/linux-lts-kmhv2/0287-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 6004bf7f9a93b484f6869e38172fbf3543cd888a Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 19 Mar 2026 07:51:04 +0000 -Subject: [PATCH 287/467] UPSTREAM: usb: misc: onboard_usb_dev: Add Terminus - FE1.1s USB2.0 Hub (1a40:0101) - -Terminus FE1.1s is USB2.0 protocol compliant 4-port USB HUB, It support -MTT (Multiple Transaction Translator) mode, the upstream port supports -high-speed 480MHz and full-speed 12MHz modes, also it has integrated 5V -to 3.3V/1.8V regulator and Power-On-Reset circuit. - -Link: https://terminus-usa.com/wp-content/uploads/2024/06/FE1.1s-Product-Brief-Rev.-2.0-2023.pdf [1] -Signed-off-by: Yixun Lan -Link: https://patch.msgid.link/20260319-03-usb-hub-fe1-v2-2-e4e26809dd7d@kernel.org -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit 00b4fe5be06aecd6426930de86b7cffc2330f4b8) -Signed-off-by: Han Gao ---- - drivers/usb/misc/onboard_usb_dev.c | 2 ++ - drivers/usb/misc/onboard_usb_dev.h | 1 + - 2 files changed, 3 insertions(+) - -diff --git a/drivers/usb/misc/onboard_usb_dev.c b/drivers/usb/misc/onboard_usb_dev.c -index 41360a7591e5..40b2ebf45a9a 100644 ---- a/drivers/usb/misc/onboard_usb_dev.c -+++ b/drivers/usb/misc/onboard_usb_dev.c -@@ -570,6 +570,7 @@ static struct platform_driver onboard_dev_driver = { - #define VENDOR_ID_MICROCHIP 0x0424 - #define VENDOR_ID_PARADE 0x1da0 - #define VENDOR_ID_REALTEK 0x0bda -+#define VENDOR_ID_TERMINUS 0x1a40 - #define VENDOR_ID_TI 0x0451 - #define VENDOR_ID_VIA 0x2109 - #define VENDOR_ID_XMOS 0x20B1 -@@ -673,6 +674,7 @@ static const struct usb_device_id onboard_dev_id_table[] = { - { USB_DEVICE(VENDOR_ID_REALTEK, 0x0414) }, /* RTS5414 USB 3.2 HUB */ - { USB_DEVICE(VENDOR_ID_REALTEK, 0x5414) }, /* RTS5414 USB 2.1 HUB */ - { USB_DEVICE(VENDOR_ID_REALTEK, 0x0179) }, /* RTL8188ETV 2.4GHz WiFi */ -+ { USB_DEVICE(VENDOR_ID_TERMINUS, 0x0101) }, /* Terminus FE1.1s 2.0 HUB */ - { USB_DEVICE(VENDOR_ID_TI, 0x8025) }, /* TI USB8020B 3.0 HUB */ - { USB_DEVICE(VENDOR_ID_TI, 0x8027) }, /* TI USB8020B 2.0 HUB */ - { USB_DEVICE(VENDOR_ID_TI, 0x8140) }, /* TI USB8041 3.0 HUB */ -diff --git a/drivers/usb/misc/onboard_usb_dev.h b/drivers/usb/misc/onboard_usb_dev.h -index c1462be5526d..be234b5a97bb 100644 ---- a/drivers/usb/misc/onboard_usb_dev.h -+++ b/drivers/usb/misc/onboard_usb_dev.h -@@ -146,6 +146,7 @@ static const struct of_device_id onboard_dev_match[] = { - { .compatible = "usbbda,5411", .data = &realtek_rts5411_data, }, - { .compatible = "usbbda,414", .data = &realtek_rts5411_data, }, - { .compatible = "usbbda,5414", .data = &realtek_rts5411_data, }, -+ { .compatible = "usb1a40,0101", .data = &vialab_vl817_data, }, - { .compatible = "usb1da0,5511", .data = ¶de_ps5511_data, }, - { .compatible = "usb1da0,55a1", .data = ¶de_ps5511_data, }, - { .compatible = "usb2109,817", .data = &vialab_vl817_data, }, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch b/SPECS/linux-lts-kmhv2/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch new file mode 100644 index 0000000000..e7deac9aea --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch @@ -0,0 +1,108 @@ +From bb40d8362ee33eb3d7341201cc0193113631e03c Mon Sep 17 00:00:00 2001 +From: Huan He +Date: Sun, 19 Oct 2025 19:52:38 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: sdhci-of-dwcmshc: Add Eswin + EIC7700 + +EIC7700 use Synopsys dwcmshc IP for SD/eMMC controllers. +Add Eswin EIC7700 support in sdhci-of-dwcmshc.yaml. + +Signed-off-by: Huan He +Reviewed-by: Conor Dooley +Signed-off-by: Ulf Hansson +(cherry picked from commit 30009a21f257a02feea7a7708ef3d0118e7f824a) +Signed-off-by: Han Gao +--- + .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 57 +++++++++++++++++-- + 1 file changed, 51 insertions(+), 6 deletions(-) + +diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +index f882219a0a26..7e7c55dc2440 100644 +--- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml ++++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +@@ -30,6 +30,7 @@ properties: + - sophgo,sg2002-dwcmshc + - sophgo,sg2042-dwcmshc + - thead,th1520-dwcmshc ++ - eswin,eic7700-dwcmshc + + reg: + maxItems: 1 +@@ -52,17 +53,30 @@ properties: + maxItems: 5 + + reset-names: +- items: +- - const: core +- - const: bus +- - const: axi +- - const: block +- - const: timer ++ maxItems: 5 + + rockchip,txclk-tapnum: + description: Specify the number of delay for tx sampling. + $ref: /schemas/types.yaml#/definitions/uint8 + ++ eswin,hsp-sp-csr: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: Phandle to HSP(High-Speed Peripheral) device ++ - description: Offset of the stability status register for internal ++ clock. ++ - description: Offset of the stability register for host regulator ++ voltage. ++ description: ++ HSP CSR is to control and get status of different high-speed peripherals ++ (such as Ethernet, USB, SATA, etc.) via register, which can tune ++ board-level's parameters of PHY, etc. ++ ++ eswin,drive-impedance-ohms: ++ description: Specifies the drive impedance in Ohm. ++ enum: [33, 40, 50, 66, 100] ++ + required: + - compatible + - reg +@@ -110,6 +124,37 @@ allOf: + - const: block + - const: timer + ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: eswin,eic7700-dwcmshc ++ then: ++ properties: ++ resets: ++ minItems: 4 ++ maxItems: 4 ++ reset-names: ++ items: ++ - const: axi ++ - const: phy ++ - const: prstn ++ - const: txrx ++ required: ++ - eswin,hsp-sp-csr ++ - eswin,drive-impedance-ohms ++ else: ++ properties: ++ resets: ++ maxItems: 5 ++ reset-names: ++ items: ++ - const: core ++ - const: bus ++ - const: axi ++ - const: block ++ - const: timer ++ + - if: + properties: + compatible: +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0288-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch b/SPECS/linux-lts-kmhv2/0288-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch deleted file mode 100644 index 1d01c9a2ed..0000000000 --- a/SPECS/linux-lts-kmhv2/0288-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch +++ /dev/null @@ -1,96 +0,0 @@ -From ed5a7f0bdca54d386d2e845f3ebadc8b204c271c Mon Sep 17 00:00:00 2001 -From: Nathan Chancellor -Date: Wed, 29 Apr 2026 20:38:17 -0600 -Subject: [PATCH 288/467] UPSTREAM: riscv: Define - __riscv_copy_{,vec_}{words,bytes}_unaligned() using SYM_TYPED_FUNC_START - -After commit 67bdd7b01387 ("riscv: Split out measure_cycles() for -reuse") and commit c03ad15f7cf6 ("riscv: Reuse measure_cycles() in -check_vector_unaligned_access()"), there are CFI failure when booting -kernels with CONFIG_CFI=y: - - CFI failure at measure_cycles+0x38/0xe0 (target: __riscv_copy_words_unaligned+0x0/0x50; expected type: ...) - CFI failure at measure_cycles+0x38/0xe0 (target: __riscv_copy_vec_words_unaligned+0x0/0x24; expected type: ...) - -The __riscv_copy_*_unaligned() functions are now called indirectly but -they are not defined with SYM_TYPED_FUNC_START, which is required for -assembly functions called indirectly from C to pass CFI checking. Switch -to SYM_TYPED_FUNC_START to clear up the CFI failures. - -Fixes: 67bdd7b01387 ("riscv: Split out measure_cycles() for reuse") -Fixes: c03ad15f7cf6 ("riscv: Reuse measure_cycles() in check_vector_unaligned_access()") -Signed-off-by: Nathan Chancellor -Reviewed-by: Sami Tolvanen -Reviewed-by: Nam Cao -Link: https://patch.msgid.link/20260406-measure_cycles-cfi-failure-v1-1-03e0234ae02f@kernel.org -Signed-off-by: Paul Walmsley -(cherry picked from commit f2abc305aa93f5b12d5c929d7a9c1cf7d7fee8af) -Signed-off-by: Han Gao ---- - arch/riscv/kernel/copy-unaligned.S | 5 +++-- - arch/riscv/kernel/vec-copy-unaligned.S | 5 +++-- - 2 files changed, 6 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/kernel/copy-unaligned.S b/arch/riscv/kernel/copy-unaligned.S -index 2b3d9398c113..90f3549621f7 100644 ---- a/arch/riscv/kernel/copy-unaligned.S -+++ b/arch/riscv/kernel/copy-unaligned.S -@@ -1,6 +1,7 @@ - /* SPDX-License-Identifier: GPL-2.0 */ - /* Copyright (C) 2023 Rivos Inc. */ - -+#include - #include - #include - -@@ -9,7 +10,7 @@ - /* void __riscv_copy_words_unaligned(void *, const void *, size_t) */ - /* Performs a memcpy without aligning buffers, using word loads and stores. */ - /* Note: The size is truncated to a multiple of 8 * SZREG */ --SYM_FUNC_START(__riscv_copy_words_unaligned) -+SYM_TYPED_FUNC_START(__riscv_copy_words_unaligned) - andi a4, a2, ~((8*SZREG)-1) - beqz a4, 2f - add a3, a1, a4 -@@ -41,7 +42,7 @@ SYM_FUNC_END(__riscv_copy_words_unaligned) - /* void __riscv_copy_bytes_unaligned(void *, const void *, size_t) */ - /* Performs a memcpy without aligning buffers, using only byte accesses. */ - /* Note: The size is truncated to a multiple of 8 */ --SYM_FUNC_START(__riscv_copy_bytes_unaligned) -+SYM_TYPED_FUNC_START(__riscv_copy_bytes_unaligned) - andi a4, a2, ~(8-1) - beqz a4, 2f - add a3, a1, a4 -diff --git a/arch/riscv/kernel/vec-copy-unaligned.S b/arch/riscv/kernel/vec-copy-unaligned.S -index 7ce4de6f6e69..361039f7b944 100644 ---- a/arch/riscv/kernel/vec-copy-unaligned.S -+++ b/arch/riscv/kernel/vec-copy-unaligned.S -@@ -2,6 +2,7 @@ - /* Copyright (C) 2024 Rivos Inc. */ - - #include -+#include - #include - #include - -@@ -16,7 +17,7 @@ - /* void __riscv_copy_vec_words_unaligned(void *, const void *, size_t) */ - /* Performs a memcpy without aligning buffers, using word loads and stores. */ - /* Note: The size is truncated to a multiple of WORD_EEW */ --SYM_FUNC_START(__riscv_copy_vec_words_unaligned) -+SYM_TYPED_FUNC_START(__riscv_copy_vec_words_unaligned) - andi a4, a2, ~(WORD_EEW-1) - beqz a4, 2f - add a3, a1, a4 -@@ -38,7 +39,7 @@ SYM_FUNC_END(__riscv_copy_vec_words_unaligned) - /* void __riscv_copy_vec_bytes_unaligned(void *, const void *, size_t) */ - /* Performs a memcpy without aligning buffers, using only byte accesses. */ - /* Note: The size is truncated to a multiple of 8 */ --SYM_FUNC_START(__riscv_copy_vec_bytes_unaligned) -+SYM_TYPED_FUNC_START(__riscv_copy_vec_bytes_unaligned) - andi a4, a2, ~(8-1) - beqz a4, 2f - add a3, a1, a4 --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch b/SPECS/linux-lts-kmhv2/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch new file mode 100644 index 0000000000..ca470143dd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch @@ -0,0 +1,614 @@ +From 09f0d19162ff660efb7b93fd764ae93f6d004129 Mon Sep 17 00:00:00 2001 +From: Huan He +Date: Sun, 19 Oct 2025 19:53:16 +0800 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-dwcmshc: Add support for Eswin + EIC7700 + +Add support for the mmc controller in the Eswin EIC7700 with the new +compatible "eswin,eic7700-dwcmshc". Implement custom sdhci_ops for +set_clock, reset, set_uhs_signaling, platform_execute_tuning. + +Signed-off-by: Huan He +Acked-by: Adrian Hunter +Signed-off-by: Ulf Hansson +(cherry picked from commit 32b2633219d3509d8174737bb0a8afa060e55655) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 502 +++++++++++++++++++++++++++- + 1 file changed, 491 insertions(+), 11 deletions(-) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index 5b7ffc359414..dfad61f332c4 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -19,8 +20,11 @@ + #include + #include + #include ++#include + #include + #include ++#include ++#include + + #include "sdhci-pltfm.h" + #include "cqhci.h" +@@ -39,6 +43,7 @@ + #define DWCMSHC_CARD_IS_EMMC BIT(0) + #define DWCMSHC_ENHANCED_STROBE BIT(8) + #define DWCMSHC_EMMC_ATCTRL 0x40 ++#define DWCMSHC_AT_STAT 0x44 + /* Tuning and auto-tuning fields in AT_CTRL_R control register */ + #define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */ + #define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */ +@@ -194,6 +199,19 @@ + #define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */ + #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */ + ++/* PHY DLL offset setting register */ ++#define PHY_DLL_OFFST_R (DWC_MSHC_PTR_PHY_R + 0x29) ++/* DLL LBT setting register */ ++#define PHY_DLLBT_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x2c) ++/* DLL Status register */ ++#define PHY_DLL_STATUS_R (DWC_MSHC_PTR_PHY_R + 0x2e) ++#define DLL_LOCK_STS BIT(0)/* DLL is locked and ready */ ++/* ++ * Captures the value of DLL's lock error status information. Value is valid ++ * only when LOCK_STS is set. ++ */ ++#define DLL_ERROR_STS BIT(1) ++ + #define FLAG_IO_FIXED_1V8 BIT(0) + + #define BOUNDARY_OK(addr, len) \ +@@ -206,6 +224,31 @@ + /* SMC call for BlueField-3 eMMC RST_N */ + #define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007 + ++/* Eswin specific Registers */ ++#define EIC7700_CARD_CLK_STABLE BIT(28) ++#define EIC7700_INT_BCLK_STABLE BIT(16) ++#define EIC7700_INT_ACLK_STABLE BIT(8) ++#define EIC7700_INT_TMCLK_STABLE BIT(0) ++#define EIC7700_INT_CLK_STABLE (EIC7700_CARD_CLK_STABLE | \ ++ EIC7700_INT_ACLK_STABLE | \ ++ EIC7700_INT_BCLK_STABLE | \ ++ EIC7700_INT_TMCLK_STABLE) ++#define EIC7700_HOST_VAL_STABLE BIT(0) ++ ++/* strength definition */ ++#define PHYCTRL_DR_33OHM 0xee ++#define PHYCTRL_DR_40OHM 0xcc ++#define PHYCTRL_DR_50OHM 0x88 ++#define PHYCTRL_DR_66OHM 0x44 ++#define PHYCTRL_DR_100OHM 0x00 ++ ++#define MAX_PHASE_CODE 0xff ++#define TUNING_RANGE_THRESHOLD 40 ++#define PHY_CLK_MAX_DELAY_MASK 0x7f ++#define PHY_DELAY_CODE_MAX 0x7f ++#define PHY_DELAY_CODE_EMMC 0x17 ++#define PHY_DELAY_CODE_SD 0x55 ++ + enum dwcmshc_rk_type { + DWCMSHC_RK3568, + DWCMSHC_RK3588, +@@ -217,6 +260,11 @@ struct rk35xx_priv { + u8 txclk_tapnum; + }; + ++struct eic7700_priv { ++ struct reset_control *reset; ++ unsigned int drive_impedance; ++}; ++ + #define DWCMSHC_MAX_OTHER_CLKS 3 + + struct dwcmshc_priv { +@@ -238,6 +286,17 @@ struct dwcmshc_pltfm_data { + void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); + }; + ++static void dwcmshc_enable_card_clk(struct sdhci_host *host) ++{ ++ u16 ctrl; ++ ++ ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) { ++ ctrl |= SDHCI_CLOCK_CARD_EN; ++ sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); ++ } ++} ++ + static int dwcmshc_get_enable_other_clks(struct device *dev, + struct dwcmshc_priv *priv, + int num_clks, +@@ -1120,6 +1179,411 @@ static int sg2042_init(struct device *dev, struct sdhci_host *host, + ARRAY_SIZE(clk_ids), clk_ids); + } + ++static void sdhci_eic7700_set_clock(struct sdhci_host *host, unsigned int clock) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ u16 clk; ++ ++ host->mmc->actual_clock = clock; ++ ++ if (clock == 0) { ++ sdhci_set_clock(host, clock); ++ return; ++ } ++ ++ clk_set_rate(pltfm_host->clk, clock); ++ ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ clk |= SDHCI_CLOCK_INT_EN; ++ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); ++ ++ dwcmshc_enable_card_clk(host); ++} ++ ++static void sdhci_eic7700_config_phy_delay(struct sdhci_host *host, int delay) ++{ ++ delay &= PHY_CLK_MAX_DELAY_MASK; ++ ++ /* phy clk delay line config */ ++ sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); ++ sdhci_writeb(host, delay, PHY_SDCLKDL_DC_R); ++ sdhci_writeb(host, 0x0, PHY_SDCLKDL_CNFG_R); ++} ++ ++static void sdhci_eic7700_config_phy(struct sdhci_host *host) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); ++ u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; ++ struct eic7700_priv *priv = dwc_priv->priv; ++ unsigned int val, drv; ++ ++ drv = FIELD_PREP(PHY_CNFG_PAD_SP_MASK, priv->drive_impedance & 0xF); ++ drv |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, (priv->drive_impedance >> 4) & 0xF); ++ ++ if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { ++ val = sdhci_readw(host, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); ++ val |= DWCMSHC_CARD_IS_EMMC; ++ sdhci_writew(host, val, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); ++ } ++ ++ /* reset phy, config phy's pad */ ++ sdhci_writel(host, drv | ~PHY_CNFG_RSTN_DEASSERT, PHY_CNFG_R); ++ ++ /* configure phy pads */ ++ val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); ++ val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); ++ val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); ++ val |= PHY_PAD_RXSEL_1V8; ++ sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); ++ sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); ++ sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); ++ ++ /* Clock PAD Setting */ ++ val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); ++ val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); ++ sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); ++ ++ /* PHY strobe PAD setting (EMMC only) */ ++ if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { ++ val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); ++ val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); ++ val |= PHY_PAD_RXSEL_1V8; ++ sdhci_writew(host, val, PHY_STBPAD_CNFG_R); ++ } ++ usleep_range(2000, 3000); ++ sdhci_writel(host, drv | PHY_CNFG_RSTN_DEASSERT, PHY_CNFG_R); ++ sdhci_eic7700_config_phy_delay(host, dwc_priv->delay_line); ++} ++ ++static void sdhci_eic7700_reset(struct sdhci_host *host, u8 mask) ++{ ++ sdhci_reset(host, mask); ++ ++ /* after reset all, the phy's config will be clear */ ++ if (mask == SDHCI_RESET_ALL) ++ sdhci_eic7700_config_phy(host); ++} ++ ++static int sdhci_eic7700_reset_init(struct device *dev, struct eic7700_priv *priv) ++{ ++ int ret; ++ ++ priv->reset = devm_reset_control_array_get_optional_exclusive(dev); ++ if (IS_ERR(priv->reset)) { ++ ret = PTR_ERR(priv->reset); ++ dev_err(dev, "failed to get reset control %d\n", ret); ++ return ret; ++ } ++ ++ ret = reset_control_assert(priv->reset); ++ if (ret) { ++ dev_err(dev, "Failed to assert reset signals: %d\n", ret); ++ return ret; ++ } ++ usleep_range(2000, 2100); ++ ret = reset_control_deassert(priv->reset); ++ if (ret) { ++ dev_err(dev, "Failed to deassert reset signals: %d\n", ret); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++static unsigned int eic7700_convert_drive_impedance_ohm(struct device *dev, unsigned int dr_ohm) ++{ ++ switch (dr_ohm) { ++ case 100: ++ return PHYCTRL_DR_100OHM; ++ case 66: ++ return PHYCTRL_DR_66OHM; ++ case 50: ++ return PHYCTRL_DR_50OHM; ++ case 40: ++ return PHYCTRL_DR_40OHM; ++ case 33: ++ return PHYCTRL_DR_33OHM; ++ } ++ ++ dev_warn(dev, "Invalid value %u for drive-impedance-ohms.\n", dr_ohm); ++ return PHYCTRL_DR_50OHM; ++} ++ ++static int sdhci_eic7700_delay_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); ++ int delay_min = -1; ++ int delay_max = -1; ++ int cmd_error = 0; ++ int delay = 0; ++ int i = 0; ++ int ret; ++ ++ for (i = 0; i <= PHY_DELAY_CODE_MAX; i++) { ++ sdhci_eic7700_config_phy_delay(host, i); ++ ret = mmc_send_tuning(host->mmc, opcode, &cmd_error); ++ if (ret) { ++ host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); ++ usleep_range(200, 210); ++ if (delay_min != -1 && delay_max != -1) ++ break; ++ } else { ++ if (delay_min == -1) { ++ delay_min = i; ++ continue; ++ } else { ++ delay_max = i; ++ continue; ++ } ++ } ++ } ++ if (delay_min == -1 && delay_max == -1) { ++ pr_err("%s: delay code tuning failed!\n", mmc_hostname(host->mmc)); ++ sdhci_eic7700_config_phy_delay(host, dwc_priv->delay_line); ++ return ret; ++ } ++ ++ delay = (delay_min + delay_max) / 2; ++ sdhci_eic7700_config_phy_delay(host, delay); ++ ++ return 0; ++} ++ ++static int sdhci_eic7700_phase_code_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); ++ u32 sd_caps = MMC_CAP2_NO_MMC | MMC_CAP2_NO_SDIO; ++ int phase_code = -1; ++ int code_range = -1; ++ bool is_sd = false; ++ int code_min = -1; ++ int code_max = -1; ++ int cmd_error = 0; ++ int ret = 0; ++ int i = 0; ++ ++ if ((host->mmc->caps2 & sd_caps) == sd_caps) ++ is_sd = true; ++ ++ for (i = 0; i <= MAX_PHASE_CODE; i++) { ++ /* Centered Phase code */ ++ sdhci_writew(host, i, priv->vendor_specific_area1 + DWCMSHC_AT_STAT); ++ ret = mmc_send_tuning(host->mmc, opcode, &cmd_error); ++ host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); ++ ++ if (ret) { ++ /* SD specific range tracking */ ++ if (is_sd && code_min != -1 && code_max != -1) { ++ if (code_max - code_min > code_range) { ++ code_range = code_max - code_min; ++ phase_code = (code_min + code_max) / 2; ++ if (code_range > TUNING_RANGE_THRESHOLD) ++ break; ++ } ++ code_min = -1; ++ code_max = -1; ++ } ++ /* EMMC breaks after first valid range */ ++ if (!is_sd && code_min != -1 && code_max != -1) ++ break; ++ } else { ++ /* Track valid phase code range */ ++ if (code_min == -1) { ++ code_min = i; ++ if (!is_sd) ++ continue; ++ } ++ code_max = i; ++ if (is_sd && i == MAX_PHASE_CODE) { ++ if (code_max - code_min > code_range) { ++ code_range = code_max - code_min; ++ phase_code = (code_min + code_max) / 2; ++ } ++ } ++ } ++ } ++ ++ /* Handle tuning failure case */ ++ if ((is_sd && phase_code == -1) || ++ (!is_sd && code_min == -1 && code_max == -1)) { ++ pr_err("%s: phase code tuning failed!\n", mmc_hostname(host->mmc)); ++ sdhci_writew(host, 0, priv->vendor_specific_area1 + DWCMSHC_AT_STAT); ++ return -EIO; ++ } ++ if (!is_sd) ++ phase_code = (code_min + code_max) / 2; ++ ++ sdhci_writew(host, phase_code, priv->vendor_specific_area1 + DWCMSHC_AT_STAT); ++ ++ /* SD specific final verification */ ++ if (is_sd) { ++ ret = mmc_send_tuning(host->mmc, opcode, &cmd_error); ++ host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); ++ if (ret) { ++ pr_err("%s: Final phase code 0x%x verification failed!\n", ++ mmc_hostname(host->mmc), phase_code); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int sdhci_eic7700_executing_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); ++ u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; ++ int ret = 0; ++ u16 ctrl; ++ u32 val; ++ ++ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); ++ ctrl &= ~SDHCI_CTRL_TUNED_CLK; ++ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); ++ ++ val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); ++ val |= AT_CTRL_SW_TUNE_EN; ++ sdhci_writew(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); ++ ++ sdhci_writew(host, 0, priv->vendor_specific_area1 + DWCMSHC_AT_STAT); ++ sdhci_writew(host, 0x0, SDHCI_CMD_DATA); ++ ++ if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { ++ ret = sdhci_eic7700_delay_tuning(host, opcode); ++ if (ret) ++ return ret; ++ } ++ ++ ret = sdhci_eic7700_phase_code_tuning(host, opcode); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void sdhci_eic7700_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); ++ u8 status; ++ u32 val; ++ int ret; ++ ++ dwcmshc_set_uhs_signaling(host, timing); ++ ++ /* here need make dll locked when in hs400 at 200MHz */ ++ if (timing == MMC_TIMING_MMC_HS400 && host->clock == 200000000) { ++ val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); ++ val &= ~(FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY)); ++ /* 2-cycle latency */ ++ val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, 0x2); ++ sdhci_writew(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); ++ ++ sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) | ++ 0x3, PHY_DLL_CNFG1_R);/* DLL wait cycle input */ ++ /* DLL jump step input */ ++ sdhci_writeb(host, 0x02, PHY_DLL_CNFG2_R); ++ sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, ++ PHY_DLLDL_CNFG_SLV_INPSEL), PHY_DLLDL_CNFG_R); ++ /* Sets the value of DLL's offset input */ ++ sdhci_writeb(host, 0x00, PHY_DLL_OFFST_R); ++ /* ++ * Sets the value of DLL's olbt loadval input. Controls the Ibt ++ * timer's timeout value at which DLL runs a revalidation cycle. ++ */ ++ sdhci_writew(host, 0xffff, PHY_DLLBT_CNFG_R); ++ sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); ++ usleep_range(100, 110); ++ ++ ret = read_poll_timeout(sdhci_readb, status, status & DLL_LOCK_STS, 100, 1000000, ++ false, host, PHY_DLL_STATUS_R); ++ if (ret) { ++ pr_err("%s: DLL lock timeout! status: 0x%x\n", ++ mmc_hostname(host->mmc), status); ++ return; ++ } ++ ++ status = sdhci_readb(host, PHY_DLL_STATUS_R); ++ if (status & DLL_ERROR_STS) { ++ pr_err("%s: DLL lock failed!err_status:0x%x\n", ++ mmc_hostname(host->mmc), status); ++ } ++ } ++} ++ ++static void sdhci_eic7700_set_uhs_wrapper(struct sdhci_host *host, unsigned int timing) ++{ ++ u32 sd_caps = MMC_CAP2_NO_MMC | MMC_CAP2_NO_SDIO; ++ ++ if ((host->mmc->caps2 & sd_caps) == sd_caps) ++ sdhci_set_uhs_signaling(host, timing); ++ else ++ sdhci_eic7700_set_uhs_signaling(host, timing); ++} ++ ++static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) ++{ ++ u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; ++ unsigned int val, hsp_int_status, hsp_pwr_ctrl; ++ struct of_phandle_args args; ++ struct eic7700_priv *priv; ++ struct regmap *hsp_regmap; ++ int ret; ++ ++ priv = devm_kzalloc(dev, sizeof(struct eic7700_priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ dwc_priv->priv = priv; ++ ++ ret = sdhci_eic7700_reset_init(dev, dwc_priv->priv); ++ if (ret) { ++ dev_err(dev, "failed to reset\n"); ++ return ret; ++ } ++ ++ ret = of_parse_phandle_with_fixed_args(dev->of_node, "eswin,hsp-sp-csr", 2, 0, &args); ++ if (ret) { ++ dev_err(dev, "Fail to parse 'eswin,hsp-sp-csr' phandle (%d)\n", ret); ++ return ret; ++ } ++ ++ hsp_regmap = syscon_node_to_regmap(args.np); ++ if (IS_ERR(hsp_regmap)) { ++ dev_err(dev, "Failed to get regmap for 'eswin,hsp-sp-csr'\n"); ++ of_node_put(args.np); ++ return PTR_ERR(hsp_regmap); ++ } ++ hsp_int_status = args.args[0]; ++ hsp_pwr_ctrl = args.args[1]; ++ of_node_put(args.np); ++ /* ++ * Assert clock stability: write EIC7700_INT_CLK_STABLE to hsp_int_status. ++ * This signals to the eMMC controller that platform clocks (card, ACLK, ++ * BCLK, TMCLK) are enabled and stable. ++ */ ++ regmap_write(hsp_regmap, hsp_int_status, EIC7700_INT_CLK_STABLE); ++ /* ++ * Assert voltage stability: write EIC7700_HOST_VAL_STABLE to hsp_pwr_ctrl. ++ * This signals that VDD is stable and permits transition to high-speed ++ * modes (e.g., UHS-I). ++ */ ++ regmap_write(hsp_regmap, hsp_pwr_ctrl, EIC7700_HOST_VAL_STABLE); ++ ++ if ((host->mmc->caps2 & emmc_caps) == emmc_caps) ++ dwc_priv->delay_line = PHY_DELAY_CODE_EMMC; ++ else ++ dwc_priv->delay_line = PHY_DELAY_CODE_SD; ++ ++ if (!of_property_read_u32(dev->of_node, "eswin,drive-impedance-ohms", &val)) ++ priv->drive_impedance = eic7700_convert_drive_impedance_ohm(dev, val); ++ return 0; ++} ++ + static const struct sdhci_ops sdhci_dwcmshc_ops = { + .set_clock = sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, +@@ -1194,6 +1658,18 @@ static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { + .platform_execute_tuning = th1520_execute_tuning, + }; + ++static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { ++ .set_clock = sdhci_eic7700_set_clock, ++ .get_max_clock = sdhci_pltfm_clk_get_max_clock, ++ .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, ++ .set_bus_width = sdhci_set_bus_width, ++ .reset = sdhci_eic7700_reset, ++ .set_uhs_signaling = sdhci_eic7700_set_uhs_wrapper, ++ .set_power = sdhci_set_power_and_bus_voltage, ++ .irq = dwcmshc_cqe_irq_handler, ++ .platform_execute_tuning = sdhci_eic7700_executing_tuning, ++}; ++ + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_ops, +@@ -1263,6 +1739,17 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { + .init = sg2042_init, + }; + ++static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = { ++ .pdata = { ++ .ops = &sdhci_dwcmshc_eic7700_ops, ++ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | ++ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | ++ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, ++ }, ++ .init = eic7700_init, ++}; ++ + static const struct cqhci_host_ops dwcmshc_cqhci_ops = { + .enable = dwcmshc_sdhci_cqe_enable, + .disable = sdhci_cqe_disable, +@@ -1363,6 +1850,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { + .compatible = "sophgo,sg2042-dwcmshc", + .data = &sdhci_dwcmshc_sg2042_pdata, + }, ++ { ++ .compatible = "eswin,eic7700-dwcmshc", ++ .data = &sdhci_dwcmshc_eic7700_pdata, ++ }, + {}, + }; + MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); +@@ -1595,17 +2086,6 @@ static int dwcmshc_resume(struct device *dev) + return ret; + } + +-static void dwcmshc_enable_card_clk(struct sdhci_host *host) +-{ +- u16 ctrl; +- +- ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); +- if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) { +- ctrl |= SDHCI_CLOCK_CARD_EN; +- sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); +- } +-} +- + static int dwcmshc_runtime_suspend(struct device *dev) + { + struct sdhci_host *host = dev_get_drvdata(dev); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0289-UPSTREAM-riscv-mm-Fixup-no5lvl-failure-when-vaddr-is.patch b/SPECS/linux-lts-kmhv2/0289-UPSTREAM-riscv-mm-Fixup-no5lvl-failure-when-vaddr-is.patch deleted file mode 100644 index 66787c96fb..0000000000 --- a/SPECS/linux-lts-kmhv2/0289-UPSTREAM-riscv-mm-Fixup-no5lvl-failure-when-vaddr-is.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 3de0647d68580730c9dea18c73c0c4298eeaea58 Mon Sep 17 00:00:00 2001 -From: "Guo Ren (Alibaba DAMO Academy)" -Date: Sun, 25 Jan 2026 00:52:12 -0500 -Subject: [PATCH 289/467] UPSTREAM: riscv: mm: Fixup no5lvl failure when vaddr - is invalid -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Unlike no4lvl, no5lvl still continues to detect satp, which -requires va=pa mapping. When pa=0x800000000000, no5lvl -would fail in Sv48 mode due to an illegal VA value of -0x800000000000. - -So, prevent detecting the satp flow for no5lvl, when -vaddr is invalid. Add the is_vaddr_valid() function for -checking. - -Fixes: 26e7aacb83df ("riscv: Allow to downgrade paging mode from the command line") -Cc: Alexandre Ghiti -Cc: Björn Töpel -Signed-off-by: Guo Ren (Alibaba DAMO Academy) -Tested-by: Fangyu Yu -Link: https://patch.msgid.link/20260125055212.433163-1-guoren@kernel.org -[pjw@kernel.org: cleaned up commit message] -Signed-off-by: Paul Walmsley -(cherry picked from commit db909bd7986c10da074917af3dae83a60fa65093) -Signed-off-by: Han Gao ---- - arch/riscv/mm/init.c | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index a7d0cde6536b..8f4e7e505906 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -852,6 +852,27 @@ static void __init set_mmap_rnd_bits_max(void) - mmap_rnd_bits_max = MMAP_VA_BITS - PAGE_SHIFT - 3; - } - -+static bool __init is_vaddr_valid(unsigned long va) -+{ -+ unsigned long up = 0; -+ -+ switch (satp_mode) { -+ case SATP_MODE_39: -+ up = 1UL << 38; -+ break; -+ case SATP_MODE_48: -+ up = 1UL << 47; -+ break; -+ case SATP_MODE_57: -+ up = 1UL << 56; -+ break; -+ default: -+ return false; -+ } -+ -+ return (va < up) || (va >= (ULONG_MAX - up + 1)); -+} -+ - /* - * There is a simple way to determine if 4-level is supported by the - * underlying hardware: establish 1:1 mapping in 4-level page table mode -@@ -893,6 +914,9 @@ static __init void set_satp_mode(uintptr_t dtb_pa) - set_satp_mode_pmd + PMD_SIZE, - PMD_SIZE, PAGE_KERNEL_EXEC); - retry: -+ if (!is_vaddr_valid(set_satp_mode_pmd)) -+ goto out; -+ - create_pgd_mapping(early_pg_dir, - set_satp_mode_pmd, - pgtable_l5_enabled ? -@@ -915,6 +939,7 @@ static __init void set_satp_mode(uintptr_t dtb_pa) - disable_pgtable_l4(); - } - -+out: - memset(early_pg_dir, 0, PAGE_SIZE); - memset(early_p4d, 0, PAGE_SIZE); - memset(early_pud, 0, PAGE_SIZE); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch b/SPECS/linux-lts-kmhv2/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch new file mode 100644 index 0000000000..8991fa572e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch @@ -0,0 +1,45 @@ +From eec5a961f5c9f3a5b4a99624544700e30ae02323 Mon Sep 17 00:00:00 2001 +From: Huan He +Date: Wed, 14 Jan 2026 20:21:41 +0800 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-dwcmshc: Fix init for AXI clock + for Eswin EIC7700 + +Accessing the High-Speed registers requires the AXI clock to be enabled. + +Signed-off-by: Huan He +Acked-by: Adrian Hunter +Fixes: 32b2633219d3 ("mmc: sdhci-of-dwcmshc: Add support for Eswin EIC7700") +Signed-off-by: Ulf Hansson +(cherry picked from commit fd9809ec6704db0c162b4510b11f877ec7b72065) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index dfad61f332c4..2ce2626a7993 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -1529,6 +1529,7 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm + { + u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; + unsigned int val, hsp_int_status, hsp_pwr_ctrl; ++ static const char * const clk_ids[] = {"axi"}; + struct of_phandle_args args; + struct eic7700_priv *priv; + struct regmap *hsp_regmap; +@@ -1546,6 +1547,11 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm + return ret; + } + ++ ret = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, ++ ARRAY_SIZE(clk_ids), clk_ids); ++ if (ret) ++ return ret; ++ + ret = of_parse_phandle_with_fixed_args(dev->of_node, "eswin,hsp-sp-csr", 2, 0, &args); + if (ret) { + dev_err(dev, "Fail to parse 'eswin,hsp-sp-csr' phandle (%d)\n", ret); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0290-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch b/SPECS/linux-lts-kmhv2/0290-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch deleted file mode 100644 index 9e5685bd91..0000000000 --- a/SPECS/linux-lts-kmhv2/0290-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch +++ /dev/null @@ -1,39 +0,0 @@ -From b163c53eda4a5dd98999c324051fbec43d33e6d9 Mon Sep 17 00:00:00 2001 -From: Zhengyu He -Date: Thu, 21 May 2026 22:44:45 +0800 -Subject: [PATCH 290/467] UPSTREAM: spi: dt-bindings: fsl-qspi: support - SpacemiT K3 - -Add the SpacemiT K3 QSPI compatible to the fsl-qspi binding. - -K3 and K1 use the same QSPI controller, so document the K3 compatible -with "spacemit,k1-qspi" as fallback. - -Signed-off-by: Cody Kang -Signed-off-by: Zhengyu He -Acked-by: Conor Dooley -Link: https://patch.msgid.link/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-1-52bce26e5fd8@gmail.com -Signed-off-by: Mark Brown -(cherry picked from commit 27cd2dde35b2c3b8659fa18f6a935c61fedee5c1) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml -index 1d10cfbad86c..504df31a4f90 100644 ---- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml -+++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml -@@ -20,6 +20,9 @@ properties: - - fsl,ls1021a-qspi - - fsl,ls2080a-qspi - - spacemit,k1-qspi -+ - items: -+ - const: spacemit,k3-qspi -+ - const: spacemit,k1-qspi - - items: - - enum: - - fsl,ls1043a-qspi --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0291-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch b/SPECS/linux-lts-kmhv2/0291-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch deleted file mode 100644 index 1e760e063a..0000000000 --- a/SPECS/linux-lts-kmhv2/0291-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch +++ /dev/null @@ -1,45 +0,0 @@ -From ffdb403e8aa1eacebe47a4796578523b663508ee Mon Sep 17 00:00:00 2001 -From: Jiakai Xu -Date: Sun, 17 May 2026 12:44:14 +0000 -Subject: [PATCH 291/467] UPSTREAM: RISC-V: KVM: Fix NULL pointer dereference - in SBI v0.1 SEND_IPI handler - -The SBI v0.1 SEND_IPI handler iterates over the hart mask and calls -kvm_get_vcpu_by_id() to find the target vcpu for each set bit. When a -guest provides a hart mask containing bits for non-existent vcpu_ids, -kvm_get_vcpu_by_id() returns NULL, which is then unconditionally -dereferenced by kvm_riscv_vcpu_set_interrupt(), causing a kernel crash. - -Fix this by adding a NULL check before dereferencing the return value. -If the target vcpu is not found, skip it and continue processing the -remaining valid harts. - -Fixes: a046c2d8578c ("RISC-V: KVM: Reorganize SBI code by moving SBI v0.1 to its own file") -Signed-off-by: Jiakai Xu -Signed-off-by: Jiakai Xu -Assisted-by: OpenClaw:DeepSeek-V3.2 -Reviewed-by: Anup Patel -Link: https://lore.kernel.org/r/20260517124414.420919-1-xujiakai2025@iscas.ac.cn -Signed-off-by: Anup Patel -(cherry picked from commit fdb69d401967fd88d27982a7e4984b2a3a4f0314) -Signed-off-by: Han Gao ---- - arch/riscv/kvm/vcpu_sbi_v01.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c -index 368dfddd23d9..b6aef0e5ea57 100644 ---- a/arch/riscv/kvm/vcpu_sbi_v01.c -+++ b/arch/riscv/kvm/vcpu_sbi_v01.c -@@ -56,6 +56,8 @@ static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, - - for_each_set_bit(i, &hmask, BITS_PER_LONG) { - rvcpu = kvm_get_vcpu_by_id(vcpu->kvm, i); -+ if (!rvcpu) -+ continue; - ret = kvm_riscv_vcpu_set_interrupt(rvcpu, IRQ_VS_SOFT); - if (ret < 0) - break; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch b/SPECS/linux-lts-kmhv2/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch new file mode 100644 index 0000000000..25b1fd7b47 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch @@ -0,0 +1,35 @@ +From 3cd03e009502a385f88e1102cb0517e2f25f455c Mon Sep 17 00:00:00 2001 +From: Huan He +Date: Wed, 14 Jan 2026 20:22:56 +0800 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-dwcmshc: Fix DMA 128MB boundary + for Eswin EIC7700 + +This DWC MSHC has a 128MB limitation where the data buffer size and start +address must not exceed the 128MB boundary. Registering the missing +'adma_write_desc' callback function. + +Signed-off-by: Huan He +Acked-by: Adrian Hunter +Fixes: 32b2633219d3 ("mmc: sdhci-of-dwcmshc: Add support for Eswin EIC7700") +Signed-off-by: Ulf Hansson +(cherry picked from commit 5cfc828502cbd0c827113bdb5694c2658af2c37c) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index 2ce2626a7993..90aa146a1be3 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -1673,6 +1673,7 @@ static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { + .set_uhs_signaling = sdhci_eic7700_set_uhs_wrapper, + .set_power = sdhci_set_power_and_bus_voltage, + .irq = dwcmshc_cqe_irq_handler, ++ .adma_write_desc = dwcmshc_adma_write_desc, + .platform_execute_tuning = sdhci_eic7700_executing_tuning, + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch b/SPECS/linux-lts-kmhv2/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch index 6ce60cb539..c72f779250 100644 --- a/SPECS/linux-lts-kmhv2/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch +++ b/SPECS/linux-lts-kmhv2/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch @@ -1,7 +1,7 @@ -From a609d4433c7a1614a618e8aa8e2eab96362fefac Mon Sep 17 00:00:00 2001 +From 07935065ada83928cfb96ceab6a5ec204787eed5 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:36 +0100 -Subject: [PATCH 292/467] FROMGIT: drm/imagination: Count paired job fence as +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Count paired job fence as dependency in prepare_job() The DRM scheduler's prepare_job() callback counts the remaining diff --git a/SPECS/linux-lts-kmhv2/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch b/SPECS/linux-lts-kmhv2/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch index 02e01dee82..26a9e98208 100644 --- a/SPECS/linux-lts-kmhv2/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch +++ b/SPECS/linux-lts-kmhv2/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch @@ -1,8 +1,8 @@ -From 9290d92ea555570942074fc606d13eb4d3bbf981 Mon Sep 17 00:00:00 2001 +From cc7e1eff70086b94e4cc0442c78e493d14ea2a91 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:37 +0100 -Subject: [PATCH 293/467] FROMGIT: drm/imagination: Fit paired fragment job in - the correct CCCB +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Fit paired fragment job in the + correct CCCB For geometry jobs with a paired fragment job, at the moment, the DRM scheduler's prepare_job() callback: diff --git a/SPECS/linux-lts-kmhv2/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch b/SPECS/linux-lts-kmhv2/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch index 585fa629fa..ef8b49eec6 100644 --- a/SPECS/linux-lts-kmhv2/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch +++ b/SPECS/linux-lts-kmhv2/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch @@ -1,8 +1,8 @@ -From 9a88a3b7b00b1c31c53573cb70a52e28c6a93a00 Mon Sep 17 00:00:00 2001 +From a64a810c6fa9b9f608d345c1c8fddcb487bf750a Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:38 +0100 -Subject: [PATCH 294/467] FROMGIT: drm/imagination: Skip check on paired job - fence during job submission +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Skip check on paired job fence + during job submission While submitting a paired fragment job, there is no need to manually look for, and skip, the paired job fence, as the existing logic to diff --git a/SPECS/linux-lts-kmhv2/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch b/SPECS/linux-lts-kmhv2/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch index eee3351fd4..9cc27fddc4 100644 --- a/SPECS/linux-lts-kmhv2/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch +++ b/SPECS/linux-lts-kmhv2/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch @@ -1,7 +1,7 @@ -From f20230f3dc06eafd26b5cd6d132c0cca76331d33 Mon Sep 17 00:00:00 2001 +From 37bce3dfda3d6bfd8120dd4ca4ce59da566ffd8c Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:39 +0100 -Subject: [PATCH 295/467] FROMGIT: drm/imagination: Rename +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Rename pvr_queue_fence_is_ufo_backed() to reflect usage This function is only used by the synchronization code to figure out if diff --git a/SPECS/linux-lts-kmhv2/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch b/SPECS/linux-lts-kmhv2/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch index d4492c8980..726a6e00f1 100644 --- a/SPECS/linux-lts-kmhv2/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch +++ b/SPECS/linux-lts-kmhv2/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch @@ -1,7 +1,7 @@ -From d480bfc6a4ff28539bca859b78544e8a3762c85e Mon Sep 17 00:00:00 2001 +From 1b5c97a61b1f397f31c97959e50a7bafe4997757 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:40 +0100 -Subject: [PATCH 296/467] FROMGIT: drm/imagination: Rename fence returned by +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Rename fence returned by pvr_queue_job_arm() Rename from done_fence to finished_fence, both because the function diff --git a/SPECS/linux-lts-kmhv2/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch b/SPECS/linux-lts-kmhv2/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch index 4e1d0d7c5d..aaa07dc5cb 100644 --- a/SPECS/linux-lts-kmhv2/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch +++ b/SPECS/linux-lts-kmhv2/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch @@ -1,8 +1,8 @@ -From 24d18b49f8c07b709700ed96d89d8612d2fb5668 Mon Sep 17 00:00:00 2001 +From 03aa10e9329f54737669ec56c2b2ab66eac2f987 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:41 +0100 -Subject: [PATCH 297/467] FROMGIT: drm/imagination: Move repeated job fence - check to its own function +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Move repeated job fence check + to its own function This should make the code slightly clearer. diff --git a/SPECS/linux-lts-kmhv2/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch b/SPECS/linux-lts-kmhv2/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch index 6b4300cbe2..c27054fa2d 100644 --- a/SPECS/linux-lts-kmhv2/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch +++ b/SPECS/linux-lts-kmhv2/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch @@ -1,7 +1,7 @@ -From 9f3709e29e576a8943a5c7b99d82d4a0293cc32f Mon Sep 17 00:00:00 2001 +From de6096b77f0bf0bf39ff10bd616f13c5e0945d58 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:42 +0100 -Subject: [PATCH 298/467] FROMGIT: drm/imagination: Update check to skip +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Update check to skip prepare_job() for fragment jobs By the time prepare_job() is called on a paired fragment job, the paired diff --git a/SPECS/linux-lts-kmhv2/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch b/SPECS/linux-lts-kmhv2/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch index fcc409d926..e093399458 100644 --- a/SPECS/linux-lts-kmhv2/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch +++ b/SPECS/linux-lts-kmhv2/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch @@ -1,7 +1,7 @@ -From b1bc1325baa32b8ced34662415894d905572c0e3 Mon Sep 17 00:00:00 2001 +From fea5671abc67fb18ac13ed5ac838464e6ac1d034 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:43 +0100 -Subject: [PATCH 299/467] FROMGIT: drm/imagination: Minor improvements to job +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Minor improvements to job submission code documentation Mixed list of clarifications and typo fixes. diff --git a/SPECS/linux-lts-kmhv2/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch b/SPECS/linux-lts-kmhv2/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch index 3e227cd8fa..ed087c87c3 100644 --- a/SPECS/linux-lts-kmhv2/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch +++ b/SPECS/linux-lts-kmhv2/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch @@ -1,7 +1,7 @@ -From 347d0feb0828177c85358f21ba7942d4d10abb3f Mon Sep 17 00:00:00 2001 +From d6e9674d63435e685b8f714dd05c6d76d0cd3383 Mon Sep 17 00:00:00 2001 From: Li Guan Date: Thu, 14 May 2026 02:07:21 +0800 -Subject: [PATCH 300/467] FROMGIT: perf riscv: Fix discarded const qualifier in +Subject: [RUYI PATCH] FROMGIT: perf riscv: Fix discarded const qualifier in _get_field() The assignment of strrchr() return values to non-const char * variables diff --git a/SPECS/linux-lts-kmhv2/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch b/SPECS/linux-lts-kmhv2/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch index d4d9cf39fa..df45fcf2dc 100644 --- a/SPECS/linux-lts-kmhv2/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch +++ b/SPECS/linux-lts-kmhv2/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch @@ -1,7 +1,7 @@ -From c04270e93a53b96a6f98611da3684d1fb609b347 Mon Sep 17 00:00:00 2001 +From 9312f5952083473da163ade5c4b5f0cd1170caf2 Mon Sep 17 00:00:00 2001 From: "Guo Ren (Alibaba DAMO Academy)" Date: Tue, 21 Apr 2026 10:31:40 -0400 -Subject: [PATCH 301/467] FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE +Subject: [RUYI PATCH] FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup The early version of XuanTie C910 core has a store merge buffer diff --git a/SPECS/linux-lts-kmhv2/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch b/SPECS/linux-lts-kmhv2/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch index eb1ea9ea73..747ee38919 100644 --- a/SPECS/linux-lts-kmhv2/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch +++ b/SPECS/linux-lts-kmhv2/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch @@ -1,7 +1,7 @@ -From f8ed95adec720bc723ed825f8d90a76e3b3b0a12 Mon Sep 17 00:00:00 2001 +From 4c835b4cf54a8879850b5743cbe7d75d2b218c9c Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 1 Apr 2026 01:56:57 +0800 -Subject: [PATCH 302/467] FROMLIST: PCI: Add per-device flag to disable native +Subject: [RUYI PATCH] FROMLIST: PCI: Add per-device flag to disable native PCIe port services Add PCI_DEV_FLAGS_NO_PORT_SERVICES to allow quirks to prevent the PCIe diff --git a/SPECS/linux-lts-kmhv2/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch b/SPECS/linux-lts-kmhv2/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch index 4f0837e1d9..58cd59ae0c 100644 --- a/SPECS/linux-lts-kmhv2/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch +++ b/SPECS/linux-lts-kmhv2/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch @@ -1,8 +1,8 @@ -From 283d1e50a78cf88b9bc5a76ae2e1ce0163dc502a Mon Sep 17 00:00:00 2001 +From cfb56bdda1f734ba778e001d5436e62217a69a3c Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 1 Apr 2026 01:56:58 +0800 -Subject: [PATCH 303/467] FROMLIST: PCI: Add quirk to disable PCIe port - services on Sophgo SG2042 +Subject: [RUYI PATCH] FROMLIST: PCI: Add quirk to disable PCIe port services + on Sophgo SG2042 SG2042's PCIe root ports [1f1c:2042] fail to deliver MSI interrupts to downstream devices when native port services are enabled. Devices under diff --git a/SPECS/linux-lts-kmhv2/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch b/SPECS/linux-lts-kmhv2/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch index 3533acb885..92052a71a6 100644 --- a/SPECS/linux-lts-kmhv2/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch +++ b/SPECS/linux-lts-kmhv2/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch @@ -1,8 +1,8 @@ -From 5061c065b398815d41839dbd6c2d13c2213c2d99 Mon Sep 17 00:00:00 2001 +From ef760574ea2b96b482691e4b76ea4544d2b04231 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Thu, 18 Sep 2025 13:58:56 -0700 -Subject: [PATCH 304/467] FROMLIST: PCI: Release BAR0 of an integrated bridge - to allow GPU BAR resize +Subject: [RUYI PATCH] FROMLIST: PCI: Release BAR0 of an integrated bridge to + allow GPU BAR resize MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch b/SPECS/linux-lts-kmhv2/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch index 41052b1644..826058c0bf 100644 --- a/SPECS/linux-lts-kmhv2/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch +++ b/SPECS/linux-lts-kmhv2/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch @@ -1,7 +1,7 @@ -From 930af6ff12384f1fc15fbeaba533c8791537aafb Mon Sep 17 00:00:00 2001 +From 1f52ff4a8952f2dcd39f984b094e0d3ba4227bcd Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 29 Jun 2024 13:22:46 +0800 -Subject: [PATCH 305/467] BACKPORT: FROMLIST: drm/ttm: save the device's DMA +Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: save the device's DMA coherency status in ttm_device Currently TTM utilizes cached memory regardless of whether the device diff --git a/SPECS/linux-lts-kmhv2/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch b/SPECS/linux-lts-kmhv2/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch index 7dbe06800d..bb46fa248c 100644 --- a/SPECS/linux-lts-kmhv2/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch +++ b/SPECS/linux-lts-kmhv2/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch @@ -1,7 +1,7 @@ -From 6b19f0c2ff8d4334e8350b2aba256942682560f0 Mon Sep 17 00:00:00 2001 +From 555ac6aeaf274981371546928300e152ff7ac153 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 29 Jun 2024 13:22:47 +0800 -Subject: [PATCH 306/467] BACKPORT: FROMLIST: drm/ttm: downgrade cached to +Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: downgrade cached to write_combined when snooping not available As we can now acquire the presence of the full DMA coherency (snooping diff --git a/SPECS/linux-lts-kmhv2/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch b/SPECS/linux-lts-kmhv2/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch index a7e829871e..58e516d738 100644 --- a/SPECS/linux-lts-kmhv2/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch +++ b/SPECS/linux-lts-kmhv2/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch @@ -1,8 +1,8 @@ -From 09dc9193b8a9859bdfcf7826fcef126692322cfa Mon Sep 17 00:00:00 2001 +From 5911aa5fe93310aba068d9a4361bc5827ce35b62 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 20 Nov 2025 13:14:16 +0000 -Subject: [PATCH 307/467] FROMLIST: NFU: riscv: dts: thead: Add CPU clock and - OPP table for TH1520 +Subject: [RUYI PATCH] FROMLIST: NFU: riscv: dts: thead: Add CPU clock and OPP + table for TH1520 Add operating point table for CPU cores, and wire up clocks for CPU nodes. diff --git a/SPECS/linux-lts-kmhv2/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch b/SPECS/linux-lts-kmhv2/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch index 1556101b34..207ec24976 100644 --- a/SPECS/linux-lts-kmhv2/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch +++ b/SPECS/linux-lts-kmhv2/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch @@ -1,7 +1,7 @@ -From fb63a586880480ca4a13569a25a63f4aecf4dc1c Mon Sep 17 00:00:00 2001 +From 1331a7f7caf771503583f18f7576c01b13e887ec Mon Sep 17 00:00:00 2001 From: Asuna Yang Date: Tue, 30 Dec 2025 17:47:54 +0100 -Subject: [PATCH 308/467] FROMLIST: rust: export BINDGEN_TARGET from a separate +Subject: [RUYI PATCH] FROMLIST: rust: export BINDGEN_TARGET from a separate Makefile A subsequent commit will add a new function `bindgen-option` to @@ -29,7 +29,7 @@ Signed-off-by: Han Gao create mode 100644 scripts/Makefile.rust diff --git a/Makefile b/Makefile -index dc63a98489a5..895fd1827580 100644 +index 5087bd6183dd..e5901ed88254 100644 --- a/Makefile +++ b/Makefile @@ -724,9 +724,10 @@ ifneq ($(findstring clang,$(CC_VERSION_TEXT)),) diff --git a/SPECS/linux-lts-kmhv2/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch b/SPECS/linux-lts-kmhv2/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch index 1346386899..99ff4e9cc0 100644 --- a/SPECS/linux-lts-kmhv2/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch +++ b/SPECS/linux-lts-kmhv2/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch @@ -1,8 +1,8 @@ -From 68a1f8f93b448edbae9513aa35f8fdfd2d0c9d10 Mon Sep 17 00:00:00 2001 +From 22c8be25d1ed7a76f36d5f1d30f0c61faa68b951 Mon Sep 17 00:00:00 2001 From: Asuna Yang Date: Tue, 30 Dec 2025 17:47:55 +0100 -Subject: [PATCH 309/467] FROMLIST: rust: generate a fatal error if - BINDGEN_TARGET is undefined +Subject: [RUYI PATCH] FROMLIST: rust: generate a fatal error if BINDGEN_TARGET + is undefined Generate a friendly fatal error if the target triplet is undefined for bindgen, rather than having the compiler generate obscure error messages diff --git a/SPECS/linux-lts-kmhv2/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch b/SPECS/linux-lts-kmhv2/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch index 73dc849cc5..f14c7c2ccd 100644 --- a/SPECS/linux-lts-kmhv2/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch +++ b/SPECS/linux-lts-kmhv2/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch @@ -1,7 +1,7 @@ -From e4594d4716d61ca97443e9a44af78e400c9462f9 Mon Sep 17 00:00:00 2001 +From 0bae0d06c2aca802becde0cd7d5cb153390dcd4d Mon Sep 17 00:00:00 2001 From: Asuna Yang Date: Tue, 30 Dec 2025 17:47:56 +0100 -Subject: [PATCH 310/467] FROMLIST: rust: add a Kconfig function to test for +Subject: [RUYI PATCH] FROMLIST: rust: add a Kconfig function to test for support of bindgen options Add a new `bindgen-backend-option` Kconfig function to test whether the diff --git a/SPECS/linux-lts-kmhv2/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch b/SPECS/linux-lts-kmhv2/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch index 89093b0689..22dad26c59 100644 --- a/SPECS/linux-lts-kmhv2/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch +++ b/SPECS/linux-lts-kmhv2/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch @@ -1,8 +1,8 @@ -From 4a0cd79c6b96ef6fc06137c6845d2d4f679efee9 Mon Sep 17 00:00:00 2001 +From bdb364df3673e4e729a0e33788d91c7ace67e22e Mon Sep 17 00:00:00 2001 From: Asuna Yang Date: Tue, 30 Dec 2025 17:47:57 +0100 -Subject: [PATCH 311/467] FROMLIST: RISC-V: handle extension configs for - bindgen, re-enable gcc + rust builds +Subject: [RUYI PATCH] FROMLIST: RISC-V: handle extension configs for bindgen, + re-enable gcc + rust builds Commit 33549fcf37ec ("RISC-V: disallow gcc + rust builds") disabled GCC + Rust builds for RISC-V due to differences in extension handling diff --git a/SPECS/linux-lts-kmhv2/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch b/SPECS/linux-lts-kmhv2/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch index 26ee47ecbd..cde256c3dd 100644 --- a/SPECS/linux-lts-kmhv2/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch +++ b/SPECS/linux-lts-kmhv2/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch @@ -1,7 +1,7 @@ -From 159388b0a2e5ca3f2f88124a933d969ed86fbeba Mon Sep 17 00:00:00 2001 +From 6b99e40ab4ea69deb0bef324e4a5160a020862f2 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sun, 21 Dec 2025 16:20:26 +0800 -Subject: [PATCH 312/467] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add reset +Subject: [RUYI PATCH] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add reset support The SpacemiT SDHCI controller has two reset lines, one connect to AXI bus diff --git a/SPECS/linux-lts-kmhv2/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch b/SPECS/linux-lts-kmhv2/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch index d14424b2c5..27e125777e 100644 --- a/SPECS/linux-lts-kmhv2/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch +++ b/SPECS/linux-lts-kmhv2/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch @@ -1,8 +1,8 @@ -From 8d7a4704394936b4c6294288c8ef99b5d613a2b5 Mon Sep 17 00:00:00 2001 +From e4c3413f71ca577a9344235a8e76978b9df6b41d Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 3 Nov 2025 00:02:00 +0100 -Subject: [PATCH 313/467] FROMLIST: mfd: simple-mfd-i2c: add a reboot cell for - the SpacemiT P1 chip +Subject: [RUYI PATCH] FROMLIST: mfd: simple-mfd-i2c: add a reboot cell for the + SpacemiT P1 chip Add a "spacemit-p1-reboot" cell for the SpacemiT P1 chip. diff --git a/SPECS/linux-lts-kmhv2/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch b/SPECS/linux-lts-kmhv2/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch index 6dfcd96600..2e6395db50 100644 --- a/SPECS/linux-lts-kmhv2/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch +++ b/SPECS/linux-lts-kmhv2/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch @@ -1,7 +1,7 @@ -From 454712fedf570ad8e52defdca4d86a789ae66c49 Mon Sep 17 00:00:00 2001 +From 976f3a509c35b7b5a88d9f5f44f15301bbfef945 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 8 Jan 2026 16:38:54 +0800 -Subject: [PATCH 314/467] FROMLIST: regulator: spacemit: MFD_SPACEMIT_P1 as +Subject: [RUYI PATCH] FROMLIST: regulator: spacemit: MFD_SPACEMIT_P1 as dependencies REGULATOR_SPACEMIT_P1 is a subdevice of P1 and should depend on diff --git a/SPECS/linux-lts-kmhv2/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch b/SPECS/linux-lts-kmhv2/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch index e05b43ffa7..a28f57c29e 100644 --- a/SPECS/linux-lts-kmhv2/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch +++ b/SPECS/linux-lts-kmhv2/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch @@ -1,7 +1,7 @@ -From 2364564dbaafd4e805bbea77f317865dd5622725 Mon Sep 17 00:00:00 2001 +From f7a63859a84191dd8619e6a34c9bf4d6664dcf23 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 8 Jan 2026 16:38:56 +0800 -Subject: [PATCH 315/467] FROMLIST: rtc: spacemit: default module when +Subject: [RUYI PATCH] FROMLIST: rtc: spacemit: default module when MFD_SPACEMIT_P1 is enabled The RTC driver defaulted to the same value as MFD_SPACEMIT_P1, which diff --git a/SPECS/linux-lts-kmhv2/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch b/SPECS/linux-lts-kmhv2/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch index 1418affeb4..6981bb7c1e 100644 --- a/SPECS/linux-lts-kmhv2/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch +++ b/SPECS/linux-lts-kmhv2/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch @@ -1,8 +1,7 @@ -From a1ffb3d0ac5dd81cbe0345aa8213f747b7560145 Mon Sep 17 00:00:00 2001 +From 2a9661946f61c576e2b7534403eae881deb90a82 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Sat, 2 May 2026 21:30:51 -0400 -Subject: [PATCH 316/467] FROMLIST: spi: dt-bindings: add SpacemiT K1 SPI - support +Subject: [RUYI PATCH] FROMLIST: spi: dt-bindings: add SpacemiT K1 SPI support Add support for the SPI controller implemented by the SpacemiT K1 SoC. diff --git a/SPECS/linux-lts-kmhv2/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch b/SPECS/linux-lts-kmhv2/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch index 4359fe4be8..0ee0c336df 100644 --- a/SPECS/linux-lts-kmhv2/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch +++ b/SPECS/linux-lts-kmhv2/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch @@ -1,7 +1,7 @@ -From 63948c550b2a578e8e796c78af7e572c4b02c041 Mon Sep 17 00:00:00 2001 +From 36ae899198d9231685aaf77e1dbcd6d51b0c9a76 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Sat, 2 May 2026 21:30:52 -0400 -Subject: [PATCH 317/467] FROMLIST: spi: spacemit: introduce SpacemiT K1 SPI +Subject: [RUYI PATCH] FROMLIST: spi: spacemit: introduce SpacemiT K1 SPI controller driver This patch introduces the driver for the SPI controller found in the diff --git a/SPECS/linux-lts-kmhv2/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch b/SPECS/linux-lts-kmhv2/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch index 0b7dc30a96..e4a7aa5c83 100644 --- a/SPECS/linux-lts-kmhv2/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch +++ b/SPECS/linux-lts-kmhv2/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch @@ -1,8 +1,8 @@ -From 6d39268afdf29820170db1c0b7f7b3d785ed0795 Mon Sep 17 00:00:00 2001 +From e61e5b8803d80c43b4959f8e4b6e863d1730fe51 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Sat, 2 May 2026 21:30:53 -0400 -Subject: [PATCH 318/467] FROMLIST: riscv: dts: spacemit: define a SPI - controller node +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: define a SPI controller + node Define a node for the fourth SoC SPI controller (number 3) on the SpacemiT K1 SoC. diff --git a/SPECS/linux-lts-kmhv2/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch b/SPECS/linux-lts-kmhv2/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch index ff0f94f63b..7bd9ac4c2d 100644 --- a/SPECS/linux-lts-kmhv2/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch +++ b/SPECS/linux-lts-kmhv2/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch @@ -1,8 +1,8 @@ -From 28a0a1dcd7e90cf89bf17b18faf7da6856e72983 Mon Sep 17 00:00:00 2001 +From 7769d31e702d0f09a02488efb2a7b55c42255417 Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Mon, 27 Apr 2026 15:15:15 +0800 -Subject: [PATCH 319/467] FROMLIST: dt-bindings: thermal: Add SpacemiT K1 - thermal sensor +Subject: [RUYI PATCH] FROMLIST: dt-bindings: thermal: Add SpacemiT K1 thermal + sensor Document the SpacemiT K1 Thermal Sensor, which supports monitoring temperatures for five zones: soc, package, gpu, cluster0, diff --git a/SPECS/linux-lts-kmhv2/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch b/SPECS/linux-lts-kmhv2/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch index 7b249b4f9e..0a1aad818b 100644 --- a/SPECS/linux-lts-kmhv2/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch +++ b/SPECS/linux-lts-kmhv2/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch @@ -1,7 +1,7 @@ -From 28919e9eba67c4c3ff61ca30861fad9fbcf74dca Mon Sep 17 00:00:00 2001 +From e87ee0243fcb7c4480eb9766f9800d4905e11b24 Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Mon, 27 Apr 2026 15:15:16 +0800 -Subject: [PATCH 320/467] FROMLIST: thermal: spacemit: k1: Add thermal sensor +Subject: [RUYI PATCH] FROMLIST: thermal: spacemit: k1: Add thermal sensor support The thermal sensor on K1 supports monitoring five temperature zones. diff --git a/SPECS/linux-lts-kmhv2/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch b/SPECS/linux-lts-kmhv2/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch index e7612aa962..6ad93704d4 100644 --- a/SPECS/linux-lts-kmhv2/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch +++ b/SPECS/linux-lts-kmhv2/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch @@ -1,8 +1,8 @@ -From 620eb1089f29269e2b8d8cb733ae93bd8bf2b73a Mon Sep 17 00:00:00 2001 +From 99bf7248cb67723d749134575afb9fcb3425bccd Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Mon, 27 Apr 2026 15:15:17 +0800 -Subject: [PATCH 321/467] FROMLIST: riscv: dts: spacemit: Add thermal sensor - for K1 SoC +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add thermal sensor for + K1 SoC Include the Thermal Sensor node in the SpacemiT K1 dtsi with definitions for registers, clocks, and interrupts. diff --git a/SPECS/linux-lts-kmhv2/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch b/SPECS/linux-lts-kmhv2/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch index 59ab5c280e..560b162481 100644 --- a/SPECS/linux-lts-kmhv2/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch +++ b/SPECS/linux-lts-kmhv2/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch @@ -1,7 +1,7 @@ -From 9b48aded2603c80a65f27877a0ac7d5d6c21f77b Mon Sep 17 00:00:00 2001 +From 83a04d13a39350e2059289ae74da6a837187c63e Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 3 Mar 2026 17:24:21 +0800 -Subject: [PATCH 322/467] FROMLIST: net: spacemit: Free rings of memory after +Subject: [RUYI PATCH] FROMLIST: net: spacemit: Free rings of memory after unmapping DMA In emac_free_{tx,rx}_resources, call dma_free_coherent() to unmap DMA diff --git a/SPECS/linux-lts-kmhv2/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch b/SPECS/linux-lts-kmhv2/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch index 3dea49628f..5a383caca0 100644 --- a/SPECS/linux-lts-kmhv2/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch +++ b/SPECS/linux-lts-kmhv2/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch @@ -1,8 +1,7 @@ -From 52f87bf6d6ba5fb8c57374827a76e0cfdaa332f4 Mon Sep 17 00:00:00 2001 +From 0615284b82b82ee1dc7ccbc7146e31afa8bbbc9f Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 3 Mar 2026 13:29:45 +0800 -Subject: [PATCH 323/467] FROMLIST: riscv: mm: Extract helper - mark_new_valid_map() +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Extract helper mark_new_valid_map() In preparation of a future patch using the same mechanism for non-vmalloc addresses, extract the mark_new_valid_map() helper from diff --git a/SPECS/linux-lts-kmhv2/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch b/SPECS/linux-lts-kmhv2/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch index e67a8f5e7c..24cfe28e1b 100644 --- a/SPECS/linux-lts-kmhv2/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch +++ b/SPECS/linux-lts-kmhv2/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch @@ -1,8 +1,8 @@ -From 8417f8da2a6a1f07550805e452db0d0ebe5c568a Mon Sep 17 00:00:00 2001 +From a6ee02e2ad7a759a5906206b87b7525c1ac580e4 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 3 Mar 2026 13:29:46 +0800 -Subject: [PATCH 324/467] FROMLIST: riscv: kfence: Call mark_new_valid_map() - for kfence_unprotect() +Subject: [RUYI PATCH] FROMLIST: riscv: kfence: Call mark_new_valid_map() for + kfence_unprotect() In kfence_protect_page(), which kfence_unprotect() calls, we cannot send IPIs to other CPUs to ask them to flush TLB. This may lead to those CPUs diff --git a/SPECS/linux-lts-kmhv2/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch b/SPECS/linux-lts-kmhv2/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch index de6f2fb9c4..a75c6a24b4 100644 --- a/SPECS/linux-lts-kmhv2/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch +++ b/SPECS/linux-lts-kmhv2/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch @@ -1,7 +1,7 @@ -From 99970ee4696d11a17cec30bcbaae18f61ca484e0 Mon Sep 17 00:00:00 2001 +From 0ff2687ed24d31a6e1dcee2c1fd287112688dabe Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 3 Mar 2026 13:29:47 +0800 -Subject: [PATCH 325/467] FROMLIST: riscv: mm: Rename new_vmalloc into +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Rename new_vmalloc into new_valid_map_cpus Since this mechanism is now used for the kfence pool, which comes from diff --git a/SPECS/linux-lts-kmhv2/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch b/SPECS/linux-lts-kmhv2/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch index 4e1aa9308b..6e8c075234 100644 --- a/SPECS/linux-lts-kmhv2/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch +++ b/SPECS/linux-lts-kmhv2/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch @@ -1,7 +1,7 @@ -From de070642f61aec41c533f778ceb930d16a10c18b Mon Sep 17 00:00:00 2001 +From e7c9b52a88814781a9b973a8bc5d43cb3655f869 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 3 Mar 2026 13:29:48 +0800 -Subject: [PATCH 326/467] FROMLIST: riscv: mm: Use the bitmap API for +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Use the bitmap API for new_valid_map_cpus The bitmap was defined with incorrect size. Fix it by using the proper diff --git a/SPECS/linux-lts-kmhv2/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch b/SPECS/linux-lts-kmhv2/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch index 5c74f6500e..9d00d9a51f 100644 --- a/SPECS/linux-lts-kmhv2/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch +++ b/SPECS/linux-lts-kmhv2/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch @@ -1,7 +1,7 @@ -From 4ffd4c28732d478d17dffb2e85279d7eca746271 Mon Sep 17 00:00:00 2001 +From 0236a57f077395bd67012bf4e9d33ba23ecdedd5 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 3 Mar 2026 13:29:49 +0800 -Subject: [PATCH 327/467] FROMLIST: riscv: mm: Unconditionally sfence.vma for +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Unconditionally sfence.vma for spurious fault Svvptc does not guarantee that it's safe to just return here. Since we diff --git a/SPECS/linux-lts-kmhv2/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch b/SPECS/linux-lts-kmhv2/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch index 43c7534f17..113e960802 100644 --- a/SPECS/linux-lts-kmhv2/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch +++ b/SPECS/linux-lts-kmhv2/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch @@ -1,8 +1,8 @@ -From bba7975767efba6ca778e4283bcfd050aa140145 Mon Sep 17 00:00:00 2001 +From 1bee6d3eac2cd34b39a8ce2c3e590aaf2f4f38f1 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 5 Mar 2026 01:00:51 +0000 -Subject: [PATCH 328/467] FROMLIST: dt-bindings: phy: spacemit: k3: add USB2 - PHY support +Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: spacemit: k3: add USB2 PHY + support Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP of USB2 PHY mostly shares the same functionalities with K1 SoC, while has diff --git a/SPECS/linux-lts-kmhv2/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch b/SPECS/linux-lts-kmhv2/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch index 1d3d66b5ab..309f8ea1b2 100644 --- a/SPECS/linux-lts-kmhv2/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch +++ b/SPECS/linux-lts-kmhv2/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch @@ -1,7 +1,7 @@ -From 0ad076c041bad32acd43346053a2e901e8f92fe6 Mon Sep 17 00:00:00 2001 +From e42b13b733fe6bf35801da4dd939e98421377976 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 5 Mar 2026 01:00:52 +0000 -Subject: [PATCH 329/467] FROMLIST: phy: k1-usb: k3: add USB2 PHY support +Subject: [RUYI PATCH] FROMLIST: phy: k1-usb: k3: add USB2 PHY support Add USB2 PHY support for SpacemiT K3 SoC. diff --git a/SPECS/linux-lts-kmhv2/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch b/SPECS/linux-lts-kmhv2/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch index 3e745bddcc..f84dd26276 100644 --- a/SPECS/linux-lts-kmhv2/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch +++ b/SPECS/linux-lts-kmhv2/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch @@ -1,7 +1,7 @@ -From 23c19485341345cc9ae14d6943205d5dec3eb56e Mon Sep 17 00:00:00 2001 +From 313a26d3fa86f65c2c9bcfdaa1d325594d4d3960 Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Fri, 10 Apr 2026 15:58:22 +0800 -Subject: [PATCH 330/467] FROMLIST: cpufreq: dt-platdev: Add SpacemiT K1 SoC to +Subject: [RUYI PATCH] FROMLIST: cpufreq: dt-platdev: Add SpacemiT K1 SoC to the allowlist The SpacemiT K1 SoC uses standard device tree based CPU frequency diff --git a/SPECS/linux-lts-kmhv2/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch b/SPECS/linux-lts-kmhv2/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch index 4dea3b010e..ab37eecf22 100644 --- a/SPECS/linux-lts-kmhv2/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch +++ b/SPECS/linux-lts-kmhv2/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch @@ -1,8 +1,8 @@ -From 2dd9746124535df6e29c3f1b6ac66084412c1e34 Mon Sep 17 00:00:00 2001 +From 76023519e9da3b79768d23f7ffe1a08e230674bd Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Fri, 10 Apr 2026 15:58:23 +0800 -Subject: [PATCH 331/467] FROMLIST: riscv: dts: spacemit: Add cpu scaling for - K1 SoC +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add cpu scaling for K1 + SoC Add Operating Performance Points (OPP) tables and CPU clock properties for the two clusters in the SpacemiT K1 SoC. diff --git a/SPECS/linux-lts-kmhv2/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch b/SPECS/linux-lts-kmhv2/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch index 6f2c86a077..a5d6058fa5 100644 --- a/SPECS/linux-lts-kmhv2/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch +++ b/SPECS/linux-lts-kmhv2/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch @@ -1,7 +1,7 @@ -From 84df59a45f81e8ef941f44d41c695a0186bc324d Mon Sep 17 00:00:00 2001 +From b71c8252ef37bceafb077b1ac8b79eb81f094356 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Mon, 9 Mar 2026 19:09:38 +0800 -Subject: [PATCH 332/467] FROMLIST: riscv: mm: Define DIRECT_MAP_PHYSMEM_END +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Define DIRECT_MAP_PHYSMEM_END On RISC-V, the actual mappable range of physical address space is dependent on the current MMU mode i.e. satp_mode (See diff --git a/SPECS/linux-lts-kmhv2/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch b/SPECS/linux-lts-kmhv2/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch index ffdaa4ceaf..3cac36fd67 100644 --- a/SPECS/linux-lts-kmhv2/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch +++ b/SPECS/linux-lts-kmhv2/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch @@ -1,8 +1,7 @@ -From e9080d8837f54bf02fccf98d737de780bbba0ca0 Mon Sep 17 00:00:00 2001 +From 3d54bf791cf5017cc96bc5222094dc98fb50e585 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 01:56:09 +0800 -Subject: [PATCH 333/467] FROMLIST: drm: verisilicon: add max cursor size to - HWDB +Subject: [RUYI PATCH] FROMLIST: drm: verisilicon: add max cursor size to HWDB Different display controller variants support different maximum cursor size. All known DC8200 variants support both 32x32 and 64x64, but some diff --git a/SPECS/linux-lts-kmhv2/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch b/SPECS/linux-lts-kmhv2/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch index efa9ea2a66..0430f73844 100644 --- a/SPECS/linux-lts-kmhv2/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch +++ b/SPECS/linux-lts-kmhv2/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch @@ -1,7 +1,7 @@ -From 2bd08175bb99fd7bbb5cb6b7fdd965ec4ba85dc8 Mon Sep 17 00:00:00 2001 +From 5b2cb452135b05fe65a5440fa7f2e39d9b28d5f3 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 01:56:10 +0800 -Subject: [PATCH 334/467] FROMLIST: drm: verisilicon: add support for cursor +Subject: [RUYI PATCH] FROMLIST: drm: verisilicon: add support for cursor planes Verisilicon display controllers support hardware cursors per output diff --git a/SPECS/linux-lts-kmhv2/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch b/SPECS/linux-lts-kmhv2/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch index a0682cc71a..6d1f390fdf 100644 --- a/SPECS/linux-lts-kmhv2/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch +++ b/SPECS/linux-lts-kmhv2/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch @@ -1,7 +1,7 @@ -From cfebf812bf3cf178789e8e4b6e59b083c727c04a Mon Sep 17 00:00:00 2001 +From 7670121cc9020d50b0705929db01a06e18578be0 Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Mon, 27 Apr 2026 09:32:10 +0800 -Subject: [PATCH 335/467] FROMLIST: riscv: add UltraRISC SoC family Kconfig +Subject: [RUYI PATCH] FROMLIST: riscv: add UltraRISC SoC family Kconfig support The first SoC in the UltraRISC series is UR-DP1000, containing octa diff --git a/SPECS/linux-lts-kmhv2/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch b/SPECS/linux-lts-kmhv2/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch index 3b43f26e44..e2d8d4c7b2 100644 --- a/SPECS/linux-lts-kmhv2/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch +++ b/SPECS/linux-lts-kmhv2/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch @@ -1,7 +1,7 @@ -From e5f3fecea63d9f7a27e40543136978db11aaa96e Mon Sep 17 00:00:00 2001 +From 7bdcfb039d0ab0b746a0ee44a449149463a7b94e Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Mon, 27 Apr 2026 09:32:11 +0800 -Subject: [PATCH 336/467] FROMLIST: dt-bindings: PCI: Add UltraRISC DP1000 PCIe +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. diff --git a/SPECS/linux-lts-kmhv2/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch b/SPECS/linux-lts-kmhv2/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch index 7be27531fb..520f243b8f 100644 --- a/SPECS/linux-lts-kmhv2/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch +++ b/SPECS/linux-lts-kmhv2/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch @@ -1,8 +1,8 @@ -From 5bcc18d72b72bff66068705f1f27ce4557a42f48 Mon Sep 17 00:00:00 2001 +From 4263860bea4eb50e8c9cce4769c096e144fd0400 Mon Sep 17 00:00:00 2001 From: Xincheng Zhang Date: Mon, 27 Apr 2026 09:32:12 +0800 -Subject: [PATCH 337/467] FROMLIST: PCI: ultrarisc: Add UltraRISC DP1000 PCIe - Root Complex driver +Subject: [RUYI PATCH] FROMLIST: PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root + Complex driver Add DP1000 SoC PCIe Root Complex driver. diff --git a/SPECS/linux-lts-kmhv2/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch b/SPECS/linux-lts-kmhv2/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch index ec329324ac..43fcf3979b 100644 --- a/SPECS/linux-lts-kmhv2/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch +++ b/SPECS/linux-lts-kmhv2/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch @@ -1,8 +1,8 @@ -From 886ed98a1e1397b695753fffcc8263183552c408 Mon Sep 17 00:00:00 2001 +From 7215c59bd1680f8f694982585919d6ec01c2e009 Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Tue, 28 Apr 2026 13:26:26 +0800 -Subject: [PATCH 338/467] FROMLIST: serial: 8250_dwlib: move DesignWare - register definitions to header +Subject: [RUYI PATCH] FROMLIST: serial: 8250_dwlib: move DesignWare register + definitions to header Move the DW_UART_* register offsets and CPR bit/field definitions from 8250_dwlib.c into 8250_dwlib.h so they can be shared by 8250_dw and diff --git a/SPECS/linux-lts-kmhv2/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch b/SPECS/linux-lts-kmhv2/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch index 130d9f9ba9..361bfc6547 100644 --- a/SPECS/linux-lts-kmhv2/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch +++ b/SPECS/linux-lts-kmhv2/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch @@ -1,8 +1,8 @@ -From 42a71ab9826c831f05fc6ceba6e355108b57394e Mon Sep 17 00:00:00 2001 +From 6180d1c44da7f8a61ffe42b1aa5f7fed0db947c5 Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Tue, 28 Apr 2026 13:26:27 +0800 -Subject: [PATCH 339/467] FROMLIST: serial: 8250_dw: build Renesas RZN1 CPR - value from DW_UART_CPR_* definitions +Subject: [RUYI PATCH] FROMLIST: serial: 8250_dw: build Renesas RZN1 CPR value + from DW_UART_CPR_* definitions Replace the magic CPR value for Renesas RZ/N1 with a composition using DW_UART_CPR_* bit/field definitions and FIELD_PREP_CONST(). diff --git a/SPECS/linux-lts-kmhv2/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch b/SPECS/linux-lts-kmhv2/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch index 7595c4aa93..2d2f322fc8 100644 --- a/SPECS/linux-lts-kmhv2/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch +++ b/SPECS/linux-lts-kmhv2/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch @@ -1,7 +1,7 @@ -From 236f493127f843659bf2a955a31f416c1f8239bf Mon Sep 17 00:00:00 2001 +From 0b0183bf49240d8f6c2d66b6eaff2fe17c541d19 Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Tue, 28 Apr 2026 13:26:28 +0800 -Subject: [PATCH 340/467] FROMLIST: dt-bindings: serial: snps-dw-apb-uart: Add +Subject: [RUYI PATCH] FROMLIST: dt-bindings: serial: snps-dw-apb-uart: Add UltraRISC DP1000 UART UltraRISC DP1000 integrates a Synopsys DesignWare APB UART, but it does diff --git a/SPECS/linux-lts-kmhv2/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch b/SPECS/linux-lts-kmhv2/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch index 35aee10ecf..710885bf79 100644 --- a/SPECS/linux-lts-kmhv2/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch +++ b/SPECS/linux-lts-kmhv2/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch @@ -1,7 +1,7 @@ -From 406c8fb8927861192219fce3ae1613ad4a1e0f0e Mon Sep 17 00:00:00 2001 +From 07e647f6d38a2395768391b1126d6af257685679 Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Tue, 28 Apr 2026 13:26:29 +0800 -Subject: [PATCH 341/467] FROMLIST: serial: 8250_dw: Use a fixed CPR value for +Subject: [RUYI PATCH] FROMLIST: serial: 8250_dw: Use a fixed CPR value for UltraRISC DP1000 UART The UltraRISC DP1000 UART does not provide the standard CPR register used diff --git a/SPECS/linux-lts-kmhv2/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch b/SPECS/linux-lts-kmhv2/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch index 0f7ba1cddb..e964c8cfd5 100644 --- a/SPECS/linux-lts-kmhv2/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch +++ b/SPECS/linux-lts-kmhv2/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch @@ -1,8 +1,8 @@ -From 1c12aaa685ca33a5f2a5de71d4290b7374d1266c Mon Sep 17 00:00:00 2001 +From 53a9a6f9561ecf77c64e14e718b3c6677e450356 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Tue, 17 Mar 2026 16:48:06 +0800 -Subject: [PATCH 342/467] FROMLIST: riscv: disable local interrupts and stop - other CPUs before reboot/shutdown +Subject: [RUYI PATCH] FROMLIST: riscv: disable local interrupts and stop other + CPUs before reboot/shutdown Currently, the RISC-V implementation of machine_restart(), machine_halt(), and machine_power_off() invokes the kernel teardown chains (e.g., diff --git a/SPECS/linux-lts-kmhv2/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch b/SPECS/linux-lts-kmhv2/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch index 4858ae86ef..baf487668c 100644 --- a/SPECS/linux-lts-kmhv2/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch +++ b/SPECS/linux-lts-kmhv2/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch @@ -1,8 +1,8 @@ -From ccbeae62330c25b6ad110b82754b6ef592620f48 Mon Sep 17 00:00:00 2001 +From c3dbfd57b9930def2f6e386d4a107127d798a89e Mon Sep 17 00:00:00 2001 From: Felix Gu Date: Sat, 21 Mar 2026 03:12:10 +0800 -Subject: [PATCH 343/467] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix error check - on dw_hdmi_probe() return value +Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix error check on + dw_hdmi_probe() return value The error check after calling dw_hdmi_probe() was incorrectly checking the struct pointer hdmi instead of the probe result hdmi->dw_hdmi. diff --git a/SPECS/linux-lts-kmhv2/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch b/SPECS/linux-lts-kmhv2/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch index 98f6f2d216..107fa9a940 100644 --- a/SPECS/linux-lts-kmhv2/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch +++ b/SPECS/linux-lts-kmhv2/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch @@ -1,7 +1,7 @@ -From a97ea68639336a5b8e0fdb9e4c6983351f80d0a9 Mon Sep 17 00:00:00 2001 +From e4498bef7d35202c1d4fff03e1f738c01c63141b Mon Sep 17 00:00:00 2001 From: Felix Gu Date: Sat, 21 Mar 2026 03:12:11 +0800 -Subject: [PATCH 344/467] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix remove() +Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix remove() callback This driver stores struct th1520_hdmi * in platform drvdata, but diff --git a/SPECS/linux-lts-kmhv2/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux-lts-kmhv2/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch index f3db0b293e..f320d51fd9 100644 --- a/SPECS/linux-lts-kmhv2/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch +++ b/SPECS/linux-lts-kmhv2/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch @@ -1,8 +1,8 @@ -From 166375a08d14e14a8b6eb3f9258fcba57cb866dc Mon Sep 17 00:00:00 2001 +From b6fedd583f0486d6ff23a73e611445adac11b2b7 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Tue, 7 Apr 2026 23:28:14 +0800 -Subject: [PATCH 345/467] FROMLIST: riscv: dts: spacemit: Enable i2c8 adapter - for OrangePi RV2 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Enable i2c8 adapter for + OrangePi RV2 The adapter is used to access the SpacemiT P1 PMIC present in this board. diff --git a/SPECS/linux-lts-kmhv2/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux-lts-kmhv2/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch index 917a05e075..d8cc2b7e7f 100644 --- a/SPECS/linux-lts-kmhv2/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch +++ b/SPECS/linux-lts-kmhv2/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch @@ -1,7 +1,7 @@ -From 604976f3e404c825a56845e3b4bd0137fc436656 Mon Sep 17 00:00:00 2001 +From 8a8b83695e5206dc768419823d357d36066dcc1a Mon Sep 17 00:00:00 2001 From: Han Gao Date: Tue, 7 Apr 2026 23:28:15 +0800 -Subject: [PATCH 346/467] FROMLIST: riscv: dts: spacemit: Define the P1 PMIC +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2 Define the DC power input and the 4v power as fixed regulator supplies. diff --git a/SPECS/linux-lts-kmhv2/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch b/SPECS/linux-lts-kmhv2/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch index cb5590d8b9..2eece049ed 100644 --- a/SPECS/linux-lts-kmhv2/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch +++ b/SPECS/linux-lts-kmhv2/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch @@ -1,7 +1,7 @@ -From f555e0c21e1df43b0df0074068872e999f825c2b Mon Sep 17 00:00:00 2001 +From be6360dcda59815d23e91c2273c7af8ee688b197 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Tue, 7 Apr 2026 23:28:16 +0800 -Subject: [PATCH 347/467] FROMLIST: riscv: dts: spacemit: Enable USB3.0/PCIe on +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2 Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the diff --git a/SPECS/linux-lts-kmhv2/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch b/SPECS/linux-lts-kmhv2/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch index b8175caff4..ec194d2c76 100644 --- a/SPECS/linux-lts-kmhv2/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch +++ b/SPECS/linux-lts-kmhv2/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch @@ -1,7 +1,7 @@ -From 737838a83cfda4cb3b3cf4a600489972c9b23a6d Mon Sep 17 00:00:00 2001 +From 35352343154bd3b77a7ce708b33610ead4fa645b Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 18 May 2026 11:32:41 +0800 -Subject: [PATCH 348/467] FROMLIST: dt-bindings: dmaengine: Add SpacemiT K3 DMA +Subject: [RUYI PATCH] FROMLIST: dt-bindings: dmaengine: Add SpacemiT K3 DMA compatible string Add the "spacemit,k3-pdma" compatible string for the SpacemiT K3 SoC. diff --git a/SPECS/linux-lts-kmhv2/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch b/SPECS/linux-lts-kmhv2/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch index 71e53cff3d..2671371cc9 100644 --- a/SPECS/linux-lts-kmhv2/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch +++ b/SPECS/linux-lts-kmhv2/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch @@ -1,7 +1,7 @@ -From 5f2df0c7e8305b8b19caa95ac987d272196435e5 Mon Sep 17 00:00:00 2001 +From 086a8550aad82551854f105777656e655e68512f Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 18 May 2026 11:32:42 +0800 -Subject: [PATCH 349/467] FROMLIST: dmaengine: mmp_pdma: refactor DRCMR access +Subject: [RUYI PATCH] FROMLIST: dmaengine: mmp_pdma: refactor DRCMR access with helper function Refactor the DRCMR macro into a helper function mmp_pdma_get_drcmr() diff --git a/SPECS/linux-lts-kmhv2/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch b/SPECS/linux-lts-kmhv2/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch index 8c3206e558..db3d534951 100644 --- a/SPECS/linux-lts-kmhv2/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch +++ b/SPECS/linux-lts-kmhv2/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch @@ -1,8 +1,7 @@ -From 84f3de67f834507b179cd81bf093f799203f394a Mon Sep 17 00:00:00 2001 +From e077c02ed73be7f8782ceacc9a2f7dd9396857b0 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 18 May 2026 11:32:43 +0800 -Subject: [PATCH 350/467] FROMLIST: dmaengine: mmp_pdma: add SpacemiT K3 - support +Subject: [RUYI PATCH] FROMLIST: dmaengine: mmp_pdma: add SpacemiT K3 support SpacemiT K3 reuses most of the PDMA IP design found on K1, with one difference being the extended DRCMR base address. Add "spacemit,k3-pdma" diff --git a/SPECS/linux-lts-kmhv2/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch b/SPECS/linux-lts-kmhv2/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch index 22e28c9866..3b955dda90 100644 --- a/SPECS/linux-lts-kmhv2/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch +++ b/SPECS/linux-lts-kmhv2/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch @@ -1,8 +1,8 @@ -From 35c22cf7e41f72e6b806aa58d4e48f88725f6c79 Mon Sep 17 00:00:00 2001 +From 21b7895de7539f827659bef3d905b99563ac4277 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Mon, 18 May 2026 11:32:44 +0800 -Subject: [PATCH 351/467] FROMLIST: riscv: dts: spacemit: Add PDMA controller - node for K3 SoC +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add PDMA controller node + for K3 SoC Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC. The PDMA controller provides general-purpose DMA capabilities for various diff --git a/SPECS/linux-lts-kmhv2/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch b/SPECS/linux-lts-kmhv2/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch index dbfadcecc7..505c1fcf8b 100644 --- a/SPECS/linux-lts-kmhv2/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch +++ b/SPECS/linux-lts-kmhv2/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch @@ -1,7 +1,7 @@ -From de29158aef7f0ff1a48fb23a0fed37c1d80cd812 Mon Sep 17 00:00:00 2001 +From e45053fa3fb846fee16140a46bfca3810a696d3a Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 1 Apr 2026 01:12:47 +0800 -Subject: [PATCH 352/467] FROMLIST: dt-bindings: pci: sophgo: Add dma-coherent +Subject: [RUYI PATCH] FROMLIST: dt-bindings: pci: sophgo: Add dma-coherent property for SG2042 Add dma-coherent as an allowed property in the SG2042 PCIe host diff --git a/SPECS/linux-lts-kmhv2/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch b/SPECS/linux-lts-kmhv2/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch index 9b7fdd2999..59e22401d2 100644 --- a/SPECS/linux-lts-kmhv2/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch +++ b/SPECS/linux-lts-kmhv2/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch @@ -1,8 +1,8 @@ -From 14a4dab155f695a1b19f164b9eeee33c118daf70 Mon Sep 17 00:00:00 2001 +From 4edb2b9deb6868de278295f9df339eb66e2dc5e6 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 1 Apr 2026 01:12:48 +0800 -Subject: [PATCH 353/467] FROMLIST: riscv: dts: sophgo: Add dma-coherent to - SG2042 PCIe controllers +Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: Add dma-coherent to SG2042 + PCIe controllers SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent diff --git a/SPECS/linux-lts-kmhv2/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch b/SPECS/linux-lts-kmhv2/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch index 618303a1e3..54ce584981 100644 --- a/SPECS/linux-lts-kmhv2/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch +++ b/SPECS/linux-lts-kmhv2/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch @@ -1,7 +1,7 @@ -From 4d9c7d6292f64242b0740b0768cab12a1a481731 Mon Sep 17 00:00:00 2001 +From 4d5cd4b1f6fe26dc668fffd055e5d01af826c026 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Tue, 31 Mar 2026 15:37:22 +0800 -Subject: [PATCH 354/467] FROMLIST: riscv: mm: fix SWIOTLB initialization for +Subject: [RUYI PATCH] FROMLIST: riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB On RISC-V platforms where the entire physical memory (DRAM) resides diff --git a/SPECS/linux-lts-kmhv2/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch b/SPECS/linux-lts-kmhv2/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch index 4200dc10cc..223d5a699f 100644 --- a/SPECS/linux-lts-kmhv2/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch +++ b/SPECS/linux-lts-kmhv2/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch @@ -1,7 +1,7 @@ -From 2dc1b2a77fff1059529b2bbe0401aebebcef36b6 Mon Sep 17 00:00:00 2001 +From 1e089bd4441c081e557a84db781ccfe5f79b5601 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Wed, 25 Mar 2026 13:46:08 +0530 -Subject: [PATCH 355/467] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Add +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Add vcc5v0_sys regulator for Banana Pi F3 Define the system 5V fixed regulator (vcc5v0_sys) supplied by the diff --git a/SPECS/linux-lts-kmhv2/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch b/SPECS/linux-lts-kmhv2/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch index 8ff016743a..5fda255af1 100644 --- a/SPECS/linux-lts-kmhv2/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch +++ b/SPECS/linux-lts-kmhv2/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch @@ -1,8 +1,8 @@ -From 9d3523b5cb45cb30a771f227a10b7c0231a04cca Mon Sep 17 00:00:00 2001 +From 9927a583ce5c19e8befcb7ed40a6238c53f79b35 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Wed, 25 Mar 2026 13:46:09 +0530 -Subject: [PATCH 356/467] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: - Update USB regulator on onboard usb and lable +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Update + USB regulator on onboard usb and lable Update the USB regulator labels to align with the board schematics and power hierarchy. This change renames the regulator to reg_5v_vbus and diff --git a/SPECS/linux-lts-kmhv2/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch b/SPECS/linux-lts-kmhv2/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch index ea69bfa145..a3dbb529e4 100644 --- a/SPECS/linux-lts-kmhv2/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch +++ b/SPECS/linux-lts-kmhv2/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch @@ -1,8 +1,8 @@ -From c7a2f9b4d3c4915e78cf4248387543db008498e7 Mon Sep 17 00:00:00 2001 +From c3e497dbbb78a87638bd90cab0bd7540fd683d89 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Wed, 25 Mar 2026 13:46:10 +0530 -Subject: [PATCH 357/467] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: - Correct USB hub power hierarchy +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Correct + USB hub power hierarchy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch b/SPECS/linux-lts-kmhv2/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch index eb490256c2..39245052d3 100644 --- a/SPECS/linux-lts-kmhv2/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch +++ b/SPECS/linux-lts-kmhv2/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch @@ -1,7 +1,7 @@ -From 630ef2347457f4560466095f5ad84c7b3acb944a Mon Sep 17 00:00:00 2001 +From a19f30eaeebdca312c928a1bd82a354ba9ce2e8e Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 26 Apr 2026 09:34:48 +0800 -Subject: [PATCH 358/467] FROMLIST: riscv: dts: sophgo: sg2044: use hex for CPU +Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: sg2044: use hex for CPU unit address Previous the CPU unit address cpu of sg2044 use decimal, it is diff --git a/SPECS/linux-lts-kmhv2/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch b/SPECS/linux-lts-kmhv2/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch index ae30ede27c..56f743e220 100644 --- a/SPECS/linux-lts-kmhv2/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch +++ b/SPECS/linux-lts-kmhv2/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch @@ -1,7 +1,7 @@ -From 067a2a1c8ce433461ac63ad6029f55a9ec8e23e5 Mon Sep 17 00:00:00 2001 +From 1e554a628178f25ce798d80c22f6e32c9013f918 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 26 Apr 2026 09:34:49 +0800 -Subject: [PATCH 359/467] FROMLIST: riscv: dts: sophgo: sg2042: use hex for CPU +Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: sg2042: use hex for CPU unit address Previous the CPU unit address cpu of sg2042 use decimal, it is diff --git a/SPECS/linux-lts-kmhv2/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch b/SPECS/linux-lts-kmhv2/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch index 671d17f19a..3978b9eca3 100644 --- a/SPECS/linux-lts-kmhv2/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch +++ b/SPECS/linux-lts-kmhv2/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch @@ -1,8 +1,8 @@ -From 7874ddbe01ccbe13b5a4828243511becf3108c87 Mon Sep 17 00:00:00 2001 +From 344151a10b042115f283ccb3ceb2241243f4f16a Mon Sep 17 00:00:00 2001 From: Nam Cao Date: Tue, 7 Apr 2026 14:06:39 +0200 -Subject: [PATCH 360/467] FROMLIST: riscv: Fix fast_unaligned_access_speed_key - not getting initialized +Subject: [RUYI PATCH] FROMLIST: riscv: Fix fast_unaligned_access_speed_key not + getting initialized The static key fast_unaligned_access_speed_key is supposed to be initialized after check_unaligned_access_all_cpus() has been completed. diff --git a/SPECS/linux-lts-kmhv2/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch b/SPECS/linux-lts-kmhv2/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch index 032ecea051..4ca22126b9 100644 --- a/SPECS/linux-lts-kmhv2/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch +++ b/SPECS/linux-lts-kmhv2/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch @@ -1,8 +1,8 @@ -From 32a650e4403e9cc5000554982cacf78cf1e8d147 Mon Sep 17 00:00:00 2001 +From 6f609eb72f740d3d3be5b596fca48b7d76f3a181 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 8 Apr 2026 00:01:43 +0800 -Subject: [PATCH 361/467] FROMLIST: riscv: dts: sophgo: reduce SG2042 MSI count - to 16 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: reduce SG2042 MSI count to + 16 The SG2042 MSI controller has one 32-bit doorbell register, and each bit corresponds to an interrupt. At a glance, it seems that the MSI diff --git a/SPECS/linux-lts-kmhv2/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch b/SPECS/linux-lts-kmhv2/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch index 81da872e3d..fe8f74bcb4 100644 --- a/SPECS/linux-lts-kmhv2/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch +++ b/SPECS/linux-lts-kmhv2/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch @@ -1,7 +1,7 @@ -From 4d5d4944086158dd4169828c2d3596f2ec8291f4 Mon Sep 17 00:00:00 2001 +From a42a4931c6355f9aec78b37eacf4e7f01afaa772 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 28 Apr 2026 10:46:50 +0000 -Subject: [PATCH 362/467] FROMLIST: dt-bindings: pwm: marvell,pxa-pwm: Add +Subject: [RUYI PATCH] FROMLIST: dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K3 PWM support The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1 diff --git a/SPECS/linux-lts-kmhv2/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch b/SPECS/linux-lts-kmhv2/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch index 0516614297..8346eff059 100644 --- a/SPECS/linux-lts-kmhv2/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch +++ b/SPECS/linux-lts-kmhv2/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch @@ -1,7 +1,7 @@ -From 9f3707cb456d37931f9025ad6d4c4f1e44e27460 Mon Sep 17 00:00:00 2001 +From 2173dcb3b9c7cd083216f7561ca2c80cc779e6c3 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 28 Apr 2026 10:46:51 +0000 -Subject: [PATCH 363/467] FROMLIST: pwm: pxa: Add optional bus clock +Subject: [RUYI PATCH] FROMLIST: pwm: pxa: Add optional bus clock Add one secondary optional bus clock for the PWM PXA driver, also keep it compatible with old single clock. diff --git a/SPECS/linux-lts-kmhv2/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch b/SPECS/linux-lts-kmhv2/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch index d409c0ae6f..169b4e07b6 100644 --- a/SPECS/linux-lts-kmhv2/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch +++ b/SPECS/linux-lts-kmhv2/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch @@ -1,7 +1,7 @@ -From 6240fb17598cbb164c6964e57937b0e241213797 Mon Sep 17 00:00:00 2001 +From a9afe33a20c57d9588e3a723da69fe92572f5726 Mon Sep 17 00:00:00 2001 From: Chen Pei Date: Thu, 9 Apr 2026 19:47:36 +0800 -Subject: [PATCH 364/467] FROMLIST: riscv: ftrace: select +Subject: [RUYI PATCH] FROMLIST: riscv: ftrace: select HAVE_BUILDTIME_MCOUNT_SORT RISC-V already satisfies all prerequisites for build-time mcount sorting: diff --git a/SPECS/linux-lts-kmhv2/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch b/SPECS/linux-lts-kmhv2/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch index 0c063dad19..63660577e2 100644 --- a/SPECS/linux-lts-kmhv2/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch +++ b/SPECS/linux-lts-kmhv2/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch @@ -1,8 +1,8 @@ -From 198b6af6a42ee5ace108899f8074347faeed4504 Mon Sep 17 00:00:00 2001 +From 62c0719d1e7faf6136869e6f6da6b1f069f63523 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 18 May 2026 18:00:30 +0800 -Subject: [PATCH 365/467] FROMLIST: riscv: dts: spacemit: enable USB3 on - OrangePi R2S +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable USB3 on OrangePi + R2S Enable the DWC3 USB3.0 controller and its associated PHY on the OrangePi R2S. The USB regulator provides VBUS for USB2 and USB3 diff --git a/SPECS/linux-lts-kmhv2/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch b/SPECS/linux-lts-kmhv2/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch index 2398e5b545..84486826fc 100644 --- a/SPECS/linux-lts-kmhv2/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch +++ b/SPECS/linux-lts-kmhv2/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch @@ -1,7 +1,7 @@ -From 1810a45e1f7eb932747edb129c2cc22f50a85617 Mon Sep 17 00:00:00 2001 +From 5d9676891cd5d6a9735391e8b346e75d7f6559c9 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 28 Apr 2026 10:57:29 +0000 -Subject: [PATCH 366/467] FROMLIST: dts: riscv: spacemit: correct 32k clock +Subject: [RUYI PATCH] FROMLIST: dts: riscv: spacemit: correct 32k clock frequency The 32k oscillator's clock frequency is actually 32768Hz, so correct it. diff --git a/SPECS/linux-lts-kmhv2/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch b/SPECS/linux-lts-kmhv2/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch index e142c9f76a..ae80025a53 100644 --- a/SPECS/linux-lts-kmhv2/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch +++ b/SPECS/linux-lts-kmhv2/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch @@ -1,7 +1,7 @@ -From d0fad1ec15d004a802d36b225277a28831021f52 Mon Sep 17 00:00:00 2001 +From 50c5274eb867073ad2b53bef51e6d9d19aa9ac2a Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 7 May 2026 15:33:09 +0800 -Subject: [PATCH 367/467] FROMLIST: ASoC: dt-bindings: add SpacemiT K3 SoC +Subject: [RUYI PATCH] FROMLIST: ASoC: dt-bindings: add SpacemiT K3 SoC compatible Add the spacemit,k3-i2s compatible string for the K3 SoC I2S diff --git a/SPECS/linux-lts-kmhv2/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch b/SPECS/linux-lts-kmhv2/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch index 872f1859cf..f0c06195d2 100644 --- a/SPECS/linux-lts-kmhv2/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch +++ b/SPECS/linux-lts-kmhv2/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch @@ -1,7 +1,7 @@ -From fdabd394ccbcb3a01600534aae7a6a5b2c4adf5d Mon Sep 17 00:00:00 2001 +From ff69086b4bd33d60ba9c418d37ac92992aae8876 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 7 May 2026 15:33:10 +0800 -Subject: [PATCH 368/467] FROMLIST: ASoC: spacemit: add K3 SoC support with +Subject: [RUYI PATCH] FROMLIST: ASoC: spacemit: add K3 SoC support with additional clocks Add support for the SpacemiT K3 SoC I2S controller, which shares the diff --git a/SPECS/linux-lts-kmhv2/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch b/SPECS/linux-lts-kmhv2/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch index 0fc85b0aa1..7eaa0d4690 100644 --- a/SPECS/linux-lts-kmhv2/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch +++ b/SPECS/linux-lts-kmhv2/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch @@ -1,7 +1,7 @@ -From 71e5ec3830b135ac33f67234ab3560e96b244d65 Mon Sep 17 00:00:00 2001 +From 0151c24b6a7cffec1479bc57a27443328f1d2fef Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 7 May 2026 18:31:42 +0800 -Subject: [PATCH 369/467] FROMLIST: ASoC: soc-dai: add shared BCLK clock for +Subject: [RUYI PATCH] FROMLIST: ASoC: soc-dai: add shared BCLK clock for cross-DAI rate constraints Add a bclk field to struct snd_soc_dai and a helper function diff --git a/SPECS/linux-lts-kmhv2/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch b/SPECS/linux-lts-kmhv2/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch index 8633e3a2c1..b2112c73cc 100644 --- a/SPECS/linux-lts-kmhv2/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch +++ b/SPECS/linux-lts-kmhv2/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch @@ -1,8 +1,8 @@ -From eafa7c60eb86e4ce51877b8dedcc634a13188bcf Mon Sep 17 00:00:00 2001 +From 811d7e0186f2cec4b5ebbd7506439ef84e15a0ff Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 7 May 2026 18:31:43 +0800 -Subject: [PATCH 370/467] FROMLIST: ASoC: soc-pcm: constrain hw_params when - DAIs share the same BCLK +Subject: [RUYI PATCH] FROMLIST: ASoC: soc-pcm: constrain hw_params when DAIs + share the same BCLK When multiple CPU DAIs on the same sound card share the same physical BCLK, add a hw_rule during PCM open that constrains the sample rate so diff --git a/SPECS/linux-lts-kmhv2/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch b/SPECS/linux-lts-kmhv2/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch index df88e6dc93..ff936b2c7c 100644 --- a/SPECS/linux-lts-kmhv2/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch +++ b/SPECS/linux-lts-kmhv2/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch @@ -1,7 +1,7 @@ -From 87485a6e8c2da82863181097d7d37ba1ebc90eb9 Mon Sep 17 00:00:00 2001 +From ab006e609e125b2253d6016108a7ac52e642a192 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 7 May 2026 18:31:44 +0800 -Subject: [PATCH 371/467] FROMLIST: ASoC: spacemit: declare shared BCLK for +Subject: [RUYI PATCH] FROMLIST: ASoC: spacemit: declare shared BCLK for cross-DAI rate constraint On SpacemiT K3, multiple I2S controllers share the same physical BCLK diff --git a/SPECS/linux-lts-kmhv2/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch b/SPECS/linux-lts-kmhv2/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch index 54669c5f23..26e3e584c6 100644 --- a/SPECS/linux-lts-kmhv2/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch +++ b/SPECS/linux-lts-kmhv2/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch @@ -1,8 +1,8 @@ -From ff1bd9de50fd99b0b63391ed7079a66e92f5fb02 Mon Sep 17 00:00:00 2001 +From fd1098639a4174a54cfc40a6fe40bbcb9569aee6 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 5 May 2026 09:53:34 -0400 -Subject: [PATCH 372/467] FROMLIST: spi: spacemit: add u64 cast to NSEC_PER_SEC - to avoid 32-bit overflow +Subject: [RUYI PATCH] FROMLIST: spi: spacemit: add u64 cast to NSEC_PER_SEC to + avoid 32-bit overflow NSEC_PER_SEC expands to the long constant 1000000000L, so NSEC_PER_SEC * BITS_PER_BYTE (8 * 10^9) overflows on 32-bit-long architectures diff --git a/SPECS/linux-lts-kmhv2/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch b/SPECS/linux-lts-kmhv2/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch index 06e80d2111..1ec5840379 100644 --- a/SPECS/linux-lts-kmhv2/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch +++ b/SPECS/linux-lts-kmhv2/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch @@ -1,7 +1,7 @@ -From eb891952a841254f3564aa2b534dd235469daaa5 Mon Sep 17 00:00:00 2001 +From 70157c501907a5cde732fdf89f3f458d3aba2959 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:16:59 +0800 -Subject: [PATCH 373/467] FROMLIST: dt-bindings: clock: thead: add TH1520 MISC +Subject: [RUYI PATCH] FROMLIST: dt-bindings: clock: thead: add TH1520 MISC subsys clock controller TH1520 has a subsystem clock controller called MISC_SUBSYS in its diff --git a/SPECS/linux-lts-kmhv2/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch b/SPECS/linux-lts-kmhv2/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch index 381e497d96..4e7272cafb 100644 --- a/SPECS/linux-lts-kmhv2/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch +++ b/SPECS/linux-lts-kmhv2/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch @@ -1,7 +1,7 @@ -From beef94a59a428c2ee10412cd8414e2f4022aa76c Mon Sep 17 00:00:00 2001 +From ff7baa8d99b3acfa161a96f9d572688e8fbfb14f Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:00 +0800 -Subject: [PATCH 374/467] FROMLIST: clk: thead: th1520-ap: add support for MISC +Subject: [RUYI PATCH] FROMLIST: clk: thead: th1520-ap: add support for MISC subsys clocks The TH1520 SoC contains a MISC_SUBSYS clock controller, which allows diff --git a/SPECS/linux-lts-kmhv2/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch b/SPECS/linux-lts-kmhv2/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch index dc3399e4cb..5712f59936 100644 --- a/SPECS/linux-lts-kmhv2/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch +++ b/SPECS/linux-lts-kmhv2/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch @@ -1,7 +1,7 @@ -From 225dd81ab8f245421e354bac14e6182025c41df1 Mon Sep 17 00:00:00 2001 +From 25858e77df3fb64d1db8a210aa513630aa172761 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:01 +0800 -Subject: [PATCH 375/467] FROMLIST: riscv: dts: thead: add device tree node for +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device tree node for MISC clock controller The MISC_SUBSYS clock controller on TH1520 SoC is a clock controller diff --git a/SPECS/linux-lts-kmhv2/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch b/SPECS/linux-lts-kmhv2/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch index b7ae4ae866..d6fc48cce2 100644 --- a/SPECS/linux-lts-kmhv2/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch +++ b/SPECS/linux-lts-kmhv2/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch @@ -1,7 +1,7 @@ -From 1f883f8b2aaf90f81e9cc3e07c5d07d624331025 Mon Sep 17 00:00:00 2001 +From bf1bce6b58599f811e5d960528b05a56606c6198 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:02 +0800 -Subject: [PATCH 376/467] FROMLIST: dt-bindings: phy: add binding for T-Head +Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: add binding for T-Head TH1520 USB PHY The TH1520 SoC features a Synopsys USB 3.0 FemtoPHY with some custom diff --git a/SPECS/linux-lts-kmhv2/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch b/SPECS/linux-lts-kmhv2/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch index 08e62a086f..f37bec7b80 100644 --- a/SPECS/linux-lts-kmhv2/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch +++ b/SPECS/linux-lts-kmhv2/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch @@ -1,7 +1,7 @@ -From dcb5013bc09740ec69367c77d4a4947ec96f20ed Mon Sep 17 00:00:00 2001 +From 6836defb3d09054866bd4165ee60f3bcd6135b07 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:03 +0800 -Subject: [PATCH 377/467] FROMLIST: phy: add a driver for T-Head TH1520 USB PHY +Subject: [RUYI PATCH] FROMLIST: phy: add a driver for T-Head TH1520 USB PHY The USB PHY on T-Head TH1520 SoC is a Synopsys USB 3.0 FemtoPHY, with some PHY parameters exported as another system controller along with it. diff --git a/SPECS/linux-lts-kmhv2/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch b/SPECS/linux-lts-kmhv2/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch index ce28cb8915..01b5e27c73 100644 --- a/SPECS/linux-lts-kmhv2/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch +++ b/SPECS/linux-lts-kmhv2/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch @@ -1,7 +1,7 @@ -From 762073e75c3906c685bc8388091a72f59d6e33f5 Mon Sep 17 00:00:00 2001 +From 2be6de531146e3cb05e762c17c5d087a15b3ad2d Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:04 +0800 -Subject: [PATCH 378/467] FROMLIST: riscv: dts: thead: add device nodes for USB +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device nodes for USB The TH1520 SoC contains a Synopsys DesignWare Cores SuperSpeed USB3.0 Dual Role Device controller in addition to a USB2+USB3 combo PHY based diff --git a/SPECS/linux-lts-kmhv2/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch b/SPECS/linux-lts-kmhv2/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch index 42750a360c..bd9aea764d 100644 --- a/SPECS/linux-lts-kmhv2/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch +++ b/SPECS/linux-lts-kmhv2/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch @@ -1,7 +1,7 @@ -From 1ecd168027599967fe95397ece7faa754e5f5e39 Mon Sep 17 00:00:00 2001 +From b2708e5bb25843313bbb63f5c6417d756f0ce5e0 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:05 +0800 -Subject: [PATCH 379/467] FROMLIST: dt-bindings: gpio: dwapb: allow GPIO hogs +Subject: [RUYI PATCH] FROMLIST: dt-bindings: gpio: dwapb: allow GPIO hogs GPIO hogs are described in the gpio.txt binding as automatic default GPIO configuration items. diff --git a/SPECS/linux-lts-kmhv2/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch b/SPECS/linux-lts-kmhv2/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch index a57fbf8f5b..00f4949ecd 100644 --- a/SPECS/linux-lts-kmhv2/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch +++ b/SPECS/linux-lts-kmhv2/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch @@ -1,7 +1,7 @@ -From 49426bc2f4eec81986cedeb4485276ce9681a724 Mon Sep 17 00:00:00 2001 +From d114c66e2f27fb7d5c538f14399ab98ce4960f83 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:06 +0800 -Subject: [PATCH 380/467] FROMLIST: dt-bindings: usb: vialab,vl817: allow ports +Subject: [RUYI PATCH] FROMLIST: dt-bindings: usb: vialab,vl817: allow ports property As a USB hub device, VL817 can surely be connected to external USB diff --git a/SPECS/linux-lts-kmhv2/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch b/SPECS/linux-lts-kmhv2/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch index d00e626d15..16cdfd9cbf 100644 --- a/SPECS/linux-lts-kmhv2/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch +++ b/SPECS/linux-lts-kmhv2/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch @@ -1,7 +1,7 @@ -From 6dcc9b3c4294c90622f68260717fcf8f07891f3b Mon Sep 17 00:00:00 2001 +From f92fde63364be52d61f1457466f5b1697b0e9b09 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:07 +0800 -Subject: [PATCH 381/467] FROMLIST: riscv: dts: thead: lpi4a: sort nodes +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: lpi4a: sort nodes Although "D" and "H" are earlier in the alphabet than "P", the DPU and HDMI nodes were added after PADCTRL node in the Lichee Pi 4A device tree. diff --git a/SPECS/linux-lts-kmhv2/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch b/SPECS/linux-lts-kmhv2/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch index e9b32dab3d..e70fcfd352 100644 --- a/SPECS/linux-lts-kmhv2/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch +++ b/SPECS/linux-lts-kmhv2/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch @@ -1,7 +1,7 @@ -From 9ce853f956a1bebf43c4053c02a67914c6fd8b50 Mon Sep 17 00:00:00 2001 +From 235225ebc673fe3cf62d79eb1936fb0ef9b3aa52 Mon Sep 17 00:00:00 2001 From: Thomas Bonnefille Date: Thu, 7 May 2026 16:17:08 +0800 -Subject: [PATCH 382/467] FROMLIST: riscv: dts: thead: Add TH1520 I2C nodes +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Add TH1520 I2C nodes Add nodes for the six I2C on the T-Head TH1520 RISCV SoC. diff --git a/SPECS/linux-lts-kmhv2/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch b/SPECS/linux-lts-kmhv2/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch index 5c45f4179f..6905dfac60 100644 --- a/SPECS/linux-lts-kmhv2/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch +++ b/SPECS/linux-lts-kmhv2/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch @@ -1,7 +1,7 @@ -From b4e786b2f0c59be9a66614adc05dff50460e5292 Mon Sep 17 00:00:00 2001 +From e7621614a1d93b84b3994cc4e147e2f5f24e8b8c Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Thu, 7 May 2026 16:17:09 +0800 -Subject: [PATCH 383/467] FROMLIST: riscv: dts: thead: Add Lichee Pi 4A IO +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Add Lichee Pi 4A IO expansions Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the diff --git a/SPECS/linux-lts-kmhv2/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch b/SPECS/linux-lts-kmhv2/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch index 5fc96a0c1d..f1e49e1290 100644 --- a/SPECS/linux-lts-kmhv2/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch +++ b/SPECS/linux-lts-kmhv2/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch @@ -1,8 +1,8 @@ -From e65c217e4f180a09599dcf963d7917ca8f2dce56 Mon Sep 17 00:00:00 2001 +From 0b1e399727d5ebc0f998864161be37205403f479 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:10 +0800 -Subject: [PATCH 384/467] FROMLIST: riscv: dts: thead: enable USB3 ports on - Lichee Pi 4A +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: enable USB3 ports on Lichee + Pi 4A The Lichee Pi 4A board features an onboard VIA VL817 hub connected to the SoC's USB3 as upstream and 4 USB-3.0-capable Type-A ports as diff --git a/SPECS/linux-lts-kmhv2/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch b/SPECS/linux-lts-kmhv2/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch index c128317cc7..9a32cb3ce3 100644 --- a/SPECS/linux-lts-kmhv2/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch +++ b/SPECS/linux-lts-kmhv2/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch @@ -1,8 +1,8 @@ -From 74fce4ca0259a2fb6f07e9a9db0da7a4b6d187ad Mon Sep 17 00:00:00 2001 +From 52e6648f05a98b5daa57d14ffbc7a8f17e0a2e70 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 11 May 2026 13:11:08 +0200 -Subject: [PATCH 385/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add - PMIC and power infrastructure +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add PMIC + and power infrastructure Enable i2c8 and add the connected SpacemiT P1 PMIC with its related regulators for the board's power infrastructure and voltage regulation support. diff --git a/SPECS/linux-lts-kmhv2/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch b/SPECS/linux-lts-kmhv2/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch index 7c213bac42..27c61ac393 100644 --- a/SPECS/linux-lts-kmhv2/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch +++ b/SPECS/linux-lts-kmhv2/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch @@ -1,8 +1,8 @@ -From 46e98f453443e84d2c39d1a192493f63035cb983 Mon Sep 17 00:00:00 2001 +From 766c66afb264021498a9385a2332b05c2ab32653 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 11 May 2026 13:11:09 +0200 -Subject: [PATCH 386/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add - 24c04 eeprom +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add 24c04 + eeprom Enable i2c2 and add the connected 24c04 EEPROM. diff --git a/SPECS/linux-lts-kmhv2/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch b/SPECS/linux-lts-kmhv2/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch index 93c6f40848..bb1a850bdd 100644 --- a/SPECS/linux-lts-kmhv2/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch +++ b/SPECS/linux-lts-kmhv2/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch @@ -1,7 +1,7 @@ -From 75a37f9d516eb90b20c532be235d4a9752fba6be Mon Sep 17 00:00:00 2001 +From c117a7fcd7c10d4f8235ca033fe3b09674838cc2 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 11 May 2026 13:11:10 +0200 -Subject: [PATCH 387/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable QSPI and add SPI NOR Add the QSPI controller node and describe the attached SPI NOR flash diff --git a/SPECS/linux-lts-kmhv2/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch b/SPECS/linux-lts-kmhv2/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch index aa1fefae14..e2dbb68dfc 100644 --- a/SPECS/linux-lts-kmhv2/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch +++ b/SPECS/linux-lts-kmhv2/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch @@ -1,7 +1,7 @@ -From 74f565b6e699c8ec0bd9138b54c7af5f73b625e3 Mon Sep 17 00:00:00 2001 +From a94156daa45213f4dfc1d6f6cc6a3f25b4e635c1 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 11 May 2026 13:11:11 +0200 -Subject: [PATCH 388/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable USB 3 ports Enable the DWC3 USB 3.0 controller, its associated combo_phy (USB 3 PHY) diff --git a/SPECS/linux-lts-kmhv2/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch b/SPECS/linux-lts-kmhv2/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch index 4d368a61b1..23832d06b8 100644 --- a/SPECS/linux-lts-kmhv2/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch +++ b/SPECS/linux-lts-kmhv2/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch @@ -1,7 +1,7 @@ -From b2f775e8f1fe4ec525455361eadc7df47250a44b Mon Sep 17 00:00:00 2001 +From 349e55f2df85d45315a64261930482121af299e5 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 11 May 2026 13:11:12 +0200 -Subject: [PATCH 389/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable PCIe ports Enable the two PCIe controller along with and their associated PHYs. They diff --git a/SPECS/linux-lts-kmhv2/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch b/SPECS/linux-lts-kmhv2/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch index ee53b03556..2a721e03c5 100644 --- a/SPECS/linux-lts-kmhv2/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch +++ b/SPECS/linux-lts-kmhv2/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch @@ -1,7 +1,7 @@ -From d3e09b27f344f7b9353cf66a5884e1eaa20cc2d9 Mon Sep 17 00:00:00 2001 +From 9a43c78660975e06c30cbaf943e981dd50feee99 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 11 May 2026 13:11:13 +0200 -Subject: [PATCH 390/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: set +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: set default console baud rate Allow serial output with the same uboot/opensbi settings so the diff --git a/SPECS/linux-lts-kmhv2/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch b/SPECS/linux-lts-kmhv2/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch index 5e1bb550cd..e480697ecf 100644 --- a/SPECS/linux-lts-kmhv2/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch +++ b/SPECS/linux-lts-kmhv2/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch @@ -1,7 +1,7 @@ -From 17640c2f952d4636e28f6c91c28cad7c0cbcfeb5 Mon Sep 17 00:00:00 2001 +From 19e0459a70fb9e1c62f2eb097e72e73136997ccd Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 21 May 2026 00:24:41 +0000 -Subject: [PATCH 391/467] FROMLIST: riscv: dts: spacemit: k3: Add pwm support +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add pwm support Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents the pinctrl info which would easily help to enable them in future. diff --git a/SPECS/linux-lts-kmhv2/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch b/SPECS/linux-lts-kmhv2/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch index ded1d721e2..dfea8b63a1 100644 --- a/SPECS/linux-lts-kmhv2/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch +++ b/SPECS/linux-lts-kmhv2/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch @@ -1,8 +1,7 @@ -From 8a3c697d67f26e7001badacbe651347af98734fc Mon Sep 17 00:00:00 2001 +From 990e07e7b25d9ad6863585a17875fd32e9b194ed Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Sun, 10 May 2026 18:54:21 +0200 -Subject: [PATCH 392/467] FROMLIST: riscv: use sysfs_emit in - cpu_show_ghostwrite +Subject: [RUYI PATCH] FROMLIST: riscv: use sysfs_emit in cpu_show_ghostwrite Replace sprintf() with sysfs_emit() in cpu_show_ghostwrite(), which is preferred for formatting sysfs output because it provides safer bounds diff --git a/SPECS/linux-lts-kmhv2/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch b/SPECS/linux-lts-kmhv2/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch index 0f04216c5b..61c699fb6b 100644 --- a/SPECS/linux-lts-kmhv2/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch +++ b/SPECS/linux-lts-kmhv2/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch @@ -1,8 +1,8 @@ -From 5a543b79cba1602b35c7bf4c272f6c1082403ec9 Mon Sep 17 00:00:00 2001 +From 5feeaceeac1d83b0bc4b52a476972edb0633b9b1 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 11 May 2026 02:59:09 +0000 -Subject: [PATCH 393/467] FROMLIST: clk: spacemit: k3: Switch to pll2_d6 as - parent for PCIe clock +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Switch to pll2_d6 as parent + for PCIe clock According to SpacemiT updated docs, the PCIe master and slave clock's parent is the pll2_d6 clock, so fix it. diff --git a/SPECS/linux-lts-kmhv2/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch b/SPECS/linux-lts-kmhv2/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch index 1709d97c4d..cec142274b 100644 --- a/SPECS/linux-lts-kmhv2/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch +++ b/SPECS/linux-lts-kmhv2/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch @@ -1,7 +1,7 @@ -From e8eb8752ce8b21f83609892d2702ada2791d6878 Mon Sep 17 00:00:00 2001 +From e7889702a01dfeefc13f75527701150067033d27 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 11 May 2026 02:59:10 +0000 -Subject: [PATCH 394/467] FROMLIST: clk: spacemit: k3: Fix PCIe clock register +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Fix PCIe clock register offset The offset of PCIe Clock CTRL register for port B and C controller was diff --git a/SPECS/linux-lts-kmhv2/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch b/SPECS/linux-lts-kmhv2/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch index 40b18595f7..8c7de819c6 100644 --- a/SPECS/linux-lts-kmhv2/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch +++ b/SPECS/linux-lts-kmhv2/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch @@ -1,8 +1,8 @@ -From 71cbe41aa3e3af9d8f5d8e6ecd78f702cebb6de4 Mon Sep 17 00:00:00 2001 +From 81e7dee63c57fbbbf525e3b3e475ac4463f4be56 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 11 May 2026 02:59:11 +0000 -Subject: [PATCH 395/467] FROMLIST: dt-bindings: soc: spacemit: k3: Add PCIe - DBI clock IDs +Subject: [RUYI PATCH] FROMLIST: dt-bindings: soc: spacemit: k3: Add PCIe DBI + clock IDs Add clock IDs of PCIe DBI (Data Bus Interface) clock. diff --git a/SPECS/linux-lts-kmhv2/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch b/SPECS/linux-lts-kmhv2/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch index 77b2c6bba2..b1757a1b9e 100644 --- a/SPECS/linux-lts-kmhv2/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch +++ b/SPECS/linux-lts-kmhv2/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch @@ -1,7 +1,7 @@ -From f93186e43511bbaed54be71b65d9a4479244fd07 Mon Sep 17 00:00:00 2001 +From 2e07351b454e444fdff46836d26d0ca8f0f1d241 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 11 May 2026 02:59:12 +0000 -Subject: [PATCH 396/467] FROMLIST: clk: spacemit: k3: Add PCIe DBI clock +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Add PCIe DBI clock Add PCIe DBI (Data Bus Interface) clock which was missing, This will support PCIe driver to explicitly request and enable all clocks that diff --git a/SPECS/linux-lts-kmhv2/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch b/SPECS/linux-lts-kmhv2/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch index 498e072354..3c8f831c46 100644 --- a/SPECS/linux-lts-kmhv2/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch +++ b/SPECS/linux-lts-kmhv2/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch @@ -1,8 +1,8 @@ -From 6ff2a06cb85f689598ffa5ccd38fc8fe6b494f5f Mon Sep 17 00:00:00 2001 +From 1e42639469619e69ed0fe533281513ebbf8fb45f Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 9 May 2026 18:00:00 +0800 -Subject: [PATCH 397/467] FROMLIST: riscv: dts: spacemit: enable eMMC for - OrangePi RV2 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable eMMC for OrangePi + RV2 The OrangePi RV2 board has one eMMC slot, so enable eMMC. Tested using a 16 GiB AJTD4R eMMC module. diff --git a/SPECS/linux-lts-kmhv2/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch b/SPECS/linux-lts-kmhv2/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch index e24ba9833d..f786ba93a4 100644 --- a/SPECS/linux-lts-kmhv2/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch +++ b/SPECS/linux-lts-kmhv2/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch @@ -1,7 +1,7 @@ -From 1dffaef4daca33ae971decf2ae555fde6d43ccd1 Mon Sep 17 00:00:00 2001 +From 952ad4c278b4a099d4fbcabc3b23304339f3277a Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 8 May 2026 15:25:24 +0800 -Subject: [PATCH 398/467] FROMLIST: i2c: spacemit: configure ILCR/IWCR for +Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: configure ILCR/IWCR for accurate SCL frequency The SpacemiT I2C controller's SCL (Serial Clock Line) frequency for diff --git a/SPECS/linux-lts-kmhv2/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch b/SPECS/linux-lts-kmhv2/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch index ca4e9fec31..7e3a638bb7 100644 --- a/SPECS/linux-lts-kmhv2/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch +++ b/SPECS/linux-lts-kmhv2/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch @@ -1,7 +1,7 @@ -From dbd9d83cae62b43735c4ed79553380f3d33cf666 Mon Sep 17 00:00:00 2001 +From 362a9bc03d8080d38e5ea64ba2c39884e945e945 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 8 May 2026 15:25:25 +0800 -Subject: [PATCH 399/467] FROMLIST: i2c: spacemit: drop warning when +Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: drop warning when clock-frequency property is absent The clock-frequency property is optional according to the DT binding. diff --git a/SPECS/linux-lts-kmhv2/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch b/SPECS/linux-lts-kmhv2/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch index 62f24cc91b..837fc9207b 100644 --- a/SPECS/linux-lts-kmhv2/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch +++ b/SPECS/linux-lts-kmhv2/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch @@ -1,8 +1,8 @@ -From d7f231111494d8c2ec36cad45aabe28d70c55167 Mon Sep 17 00:00:00 2001 +From 56ba1d8c335d661163b9d3b1d870a9e07dd575cc Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Mon, 11 May 2026 10:53:56 +0200 -Subject: [PATCH 400/467] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add - pinctrl support for voltage switching +Subject: [RUYI PATCH] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add pinctrl + support for voltage switching Document pinctrl properties to support voltage-dependent pin configuration switching for UHS-I SD card modes. diff --git a/SPECS/linux-lts-kmhv2/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch b/SPECS/linux-lts-kmhv2/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch index f52dc6e418..5583dc6077 100644 --- a/SPECS/linux-lts-kmhv2/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch +++ b/SPECS/linux-lts-kmhv2/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch @@ -1,7 +1,7 @@ -From 59062924d61974dd50fb52db1a6267bdd0e9caa5 Mon Sep 17 00:00:00 2001 +From a164c67f524d96eea999938772b0e7664cf8432d Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Mon, 11 May 2026 10:53:57 +0200 -Subject: [PATCH 401/467] FROMLIST: mmc: sdhci-of-k1: enable essential clock +Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: enable essential clock infrastructure for SD operation Ensure SD card pins receive clock signals by enabling pad clock diff --git a/SPECS/linux-lts-kmhv2/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch b/SPECS/linux-lts-kmhv2/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch index 98058cb5ec..d77d4b7d8e 100644 --- a/SPECS/linux-lts-kmhv2/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch +++ b/SPECS/linux-lts-kmhv2/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch @@ -1,7 +1,7 @@ -From 6bff1487d38af8eca2467da0d9f7b7e22ef8941d Mon Sep 17 00:00:00 2001 +From 7104b26621a3b8b7a0f213f846d4e94f40cbd6ef Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Mon, 11 May 2026 10:53:58 +0200 -Subject: [PATCH 402/467] FROMLIST: mmc: sdhci-of-k1: add regulator and pinctrl +Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: add regulator and pinctrl voltage switching support Add voltage switching infrastructure for UHS-I modes by integrating both diff --git a/SPECS/linux-lts-kmhv2/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch b/SPECS/linux-lts-kmhv2/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch index 763c405e53..a431dd69fd 100644 --- a/SPECS/linux-lts-kmhv2/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch +++ b/SPECS/linux-lts-kmhv2/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch @@ -1,8 +1,8 @@ -From 7a0c2f9d8bc3d427aff7d62359f74e8a21ecb98f Mon Sep 17 00:00:00 2001 +From 88c16045a194f9da4ac3d1e41104c2bc67bef52f Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Mon, 11 May 2026 10:53:59 +0200 -Subject: [PATCH 403/467] FROMLIST: mmc: sdhci-of-k1: add comprehensive SDR - tuning support +Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: add comprehensive SDR tuning + support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts-kmhv2/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch b/SPECS/linux-lts-kmhv2/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch index 0efaca8eaf..acee11c137 100644 --- a/SPECS/linux-lts-kmhv2/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch +++ b/SPECS/linux-lts-kmhv2/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch @@ -1,7 +1,7 @@ -From 81aae30b2ea47630a098bc16822c4b8ce486f96b Mon Sep 17 00:00:00 2001 +From c7ea3695cea289291e871b1d5ee24585b4b969ad Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Fri, 15 May 2026 12:48:59 +0200 -Subject: [PATCH 404/467] FROMLIST: riscv: dts: spacemit: k1: add SD card +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1: add SD card controller and pinctrl support Add SD card controller infrastructure for SpacemiT K1 SoC with complete diff --git a/SPECS/linux-lts-kmhv2/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch b/SPECS/linux-lts-kmhv2/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch index fb0555d636..ba6141397e 100644 --- a/SPECS/linux-lts-kmhv2/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch +++ b/SPECS/linux-lts-kmhv2/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch @@ -1,8 +1,8 @@ -From 0d69badbae2aa8cfd8dceca3cf87987d79f9a61e Mon Sep 17 00:00:00 2001 +From 43968e62edda768281d634a038212b96befc49e5 Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Fri, 15 May 2026 12:49:00 +0200 -Subject: [PATCH 405/467] FROMLIST: riscv: dts: spacemit: k1-orangepi-rv2: add - SD card support with UHS modes +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-orangepi-rv2: add SD + card support with UHS modes Add complete SD card controller support with UHS high-speed modes. diff --git a/SPECS/linux-lts-kmhv2/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch b/SPECS/linux-lts-kmhv2/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch index 76ff2fbb1d..5173364a60 100644 --- a/SPECS/linux-lts-kmhv2/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch +++ b/SPECS/linux-lts-kmhv2/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch @@ -1,8 +1,8 @@ -From f2d8d59f6d99fa77ef4d8ba4fd987daeff28eab5 Mon Sep 17 00:00:00 2001 +From 139e0716fdfe2ce733d52f88221f1b6727235cf7 Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Fri, 15 May 2026 12:49:01 +0200 -Subject: [PATCH 406/467] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: add - SD card support with UHS modes +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: add SD + card support with UHS modes Add complete SD card controller support with UHS high-speed modes. diff --git a/SPECS/linux-lts-kmhv2/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch b/SPECS/linux-lts-kmhv2/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch index 998c64454d..fc44499a76 100644 --- a/SPECS/linux-lts-kmhv2/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch +++ b/SPECS/linux-lts-kmhv2/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch @@ -1,7 +1,7 @@ -From f96189263aef32389c97389eb3235827e96b5a5d Mon Sep 17 00:00:00 2001 +From 25997e10bcbb4842cd8f7f69db1754a807b4515b Mon Sep 17 00:00:00 2001 From: Trevor Gamblin Date: Fri, 15 May 2026 12:49:02 +0200 -Subject: [PATCH 407/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add SD +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add SD card support with UHS modes Update the Muse Pi Pro devicetree with SD card support to match what diff --git a/SPECS/linux-lts-kmhv2/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch b/SPECS/linux-lts-kmhv2/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch index 4a176d39a7..5f154ddf37 100644 --- a/SPECS/linux-lts-kmhv2/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch +++ b/SPECS/linux-lts-kmhv2/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch @@ -1,7 +1,7 @@ -From a366a6ddd2d146abfc8ac12c6d57701a94a7c725 Mon Sep 17 00:00:00 2001 +From 30f59c0f689a00390e4183a7b58ec3108d1d55a8 Mon Sep 17 00:00:00 2001 From: Thomas Gerner Date: Thu, 14 May 2026 20:32:01 +0200 -Subject: [PATCH 408/467] FROMLIST: riscv: dts: thead: Enable wifi on the +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Enable wifi on the BeagleV-Ahead The BeagleV-Ahead board uses an AP6203BM WiFi chip from AMPAK Technology diff --git a/SPECS/linux-lts-kmhv2/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch b/SPECS/linux-lts-kmhv2/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch index 52300d9fdd..d8e8c34faf 100644 --- a/SPECS/linux-lts-kmhv2/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch +++ b/SPECS/linux-lts-kmhv2/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch @@ -1,8 +1,8 @@ -From 5eb58bc515879ba41b74f3e37a8bdc20196e4ed0 Mon Sep 17 00:00:00 2001 +From d02e702da21996ccb557b91e5cb594f6c76e0025 Mon Sep 17 00:00:00 2001 From: Florian Schmaus Date: Tue, 12 May 2026 08:32:31 +0200 -Subject: [PATCH 409/467] FROMLIST: riscv: module: Use generic cmp_int() - instead of custom cmp_3way() +Subject: [RUYI PATCH] FROMLIST: riscv: module: Use generic cmp_int() instead + of custom cmp_3way() The module-sections.c file defines a custom cmp_3way() macro to perform 3-way comparisons during relocation sorting. diff --git a/SPECS/linux-lts-kmhv2/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch b/SPECS/linux-lts-kmhv2/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch index 78445b0fd9..616724be18 100644 --- a/SPECS/linux-lts-kmhv2/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch +++ b/SPECS/linux-lts-kmhv2/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch @@ -1,8 +1,8 @@ -From 2cba62c648b6d8eaad866c02dec48f863e787414 Mon Sep 17 00:00:00 2001 +From 41705cbe35101c7de961fb93f3c0d01b4f424bd3 Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Tue, 12 May 2026 19:20:35 +0200 -Subject: [PATCH 410/467] FROMLIST: riscv: propagate insert_resource result - from add_resource +Subject: [RUYI PATCH] FROMLIST: riscv: propagate insert_resource result from + add_resource Currently, add_resource() returns 1 on success, even though its callers only check for negative values. Instead, propagate the insert_resource() diff --git a/SPECS/linux-lts-kmhv2/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch b/SPECS/linux-lts-kmhv2/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch index 43182331d6..d8ae0df53d 100644 --- a/SPECS/linux-lts-kmhv2/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch +++ b/SPECS/linux-lts-kmhv2/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch @@ -1,7 +1,7 @@ -From 42583ca7d256f65f3ea896a2719f5e5a76a3ab57 Mon Sep 17 00:00:00 2001 +From a380dc5ba876575445cbffdd6abae226725a9fce Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 17 May 2026 09:48:36 +0800 -Subject: [PATCH 411/467] FROMLIST: PCI: spacemit-k1: Add device data support +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add device data support To reuse the K1 PCIe driver logic for K3 PCIe controller, add device data to handle the K1 specific logic and make room for the incoming diff --git a/SPECS/linux-lts-kmhv2/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch b/SPECS/linux-lts-kmhv2/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch index c7cc73fe1f..b4cf2fd137 100644 --- a/SPECS/linux-lts-kmhv2/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch +++ b/SPECS/linux-lts-kmhv2/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch @@ -1,7 +1,7 @@ -From 641cdd56986dd7dd9d5ffec8b4a316e528313390 Mon Sep 17 00:00:00 2001 +From 291d83131cb1a80661bf10272be1b0aab99fb39d Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 17 May 2026 09:48:37 +0800 -Subject: [PATCH 412/467] FROMLIST: PCI: spacemit-k1: Add multiple PHY handles +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add multiple PHY handles support The PCIe controller on Spacemit K3 may use multiple PHYs at the diff --git a/SPECS/linux-lts-kmhv2/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch b/SPECS/linux-lts-kmhv2/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch index e8c8226d5d..d0085e05ec 100644 --- a/SPECS/linux-lts-kmhv2/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch +++ b/SPECS/linux-lts-kmhv2/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch @@ -1,8 +1,8 @@ -From ff7b3a40f58430d7040609bb6beb23f080eb3bec Mon Sep 17 00:00:00 2001 +From e1caa735029246df2abdcf416ccc274ca3ff53d5 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 17 May 2026 09:48:38 +0800 -Subject: [PATCH 413/467] FROMLIST: dt-bindings: PCI: snps,dw-pcie: Add - msi-parent for MSI handle check +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: snps,dw-pcie: Add msi-parent + for MSI handle check The IMSIC device on RISC-V based system does not require ID remapping for MSI. So this device only needs "msi-parent" diff --git a/SPECS/linux-lts-kmhv2/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch b/SPECS/linux-lts-kmhv2/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch index a9f880b0b2..ce7568b3bb 100644 --- a/SPECS/linux-lts-kmhv2/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch +++ b/SPECS/linux-lts-kmhv2/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch @@ -1,8 +1,8 @@ -From b71db7acd338b565ebfa25fdafffccc306c3f667 Mon Sep 17 00:00:00 2001 +From f9aab33c4cd724380b176901c11e9b2d5dbe7b6f Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 17 May 2026 09:48:39 +0800 -Subject: [PATCH 414/467] FROMLIST: dt-bindings: PCI: spacemit: Introduce - Spacemit K3 PCIe host controller +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: spacemit: Introduce Spacemit + K3 PCIe host controller Add binding support for the PCIe controller on the SpacemiT K3 SoC. This controller is almost a standard Synopsys DesignWare PCIe IP, diff --git a/SPECS/linux-lts-kmhv2/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch b/SPECS/linux-lts-kmhv2/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch index 94610a7b9a..66e63181b2 100644 --- a/SPECS/linux-lts-kmhv2/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch +++ b/SPECS/linux-lts-kmhv2/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch @@ -1,7 +1,7 @@ -From 099bfd3e55205ace595ca828ce5afae419eefaf7 Mon Sep 17 00:00:00 2001 +From 28a3c6b229dbe4b76f568ab83a3d0405809c7f1b Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 17 May 2026 09:48:40 +0800 -Subject: [PATCH 415/467] FROMLIST: PCI: spacemit-k1: Add Spacemit K3 PCIe host +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add Spacemit K3 PCIe host controller support The PCIe controller on Spacemit K3 is almost a standard Synopsys diff --git a/SPECS/linux-lts-kmhv2/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch b/SPECS/linux-lts-kmhv2/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch index 416a37403f..80bd621ef2 100644 --- a/SPECS/linux-lts-kmhv2/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch +++ b/SPECS/linux-lts-kmhv2/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch @@ -1,8 +1,8 @@ -From 2d3f6de67eb533903d80677a6a462979c87143b9 Mon Sep 17 00:00:00 2001 +From e933fb1426b50978196a70b05655d5cb7a3bcb76 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 16 May 2026 16:00:30 +0800 -Subject: [PATCH 416/467] FROMLIST: riscv: dts: spacemit: enable QSPI for - OrangePi RV2 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable QSPI for OrangePi + RV2 Enable the QSPI controller and the XM25QU128C SPI NOR flash on the OrangePi RV2 board. Add a flash partition layout from vendor UBoot. diff --git a/SPECS/linux-lts-kmhv2/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch b/SPECS/linux-lts-kmhv2/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch index c6980ac2dd..7ce6604711 100644 --- a/SPECS/linux-lts-kmhv2/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch +++ b/SPECS/linux-lts-kmhv2/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch @@ -1,7 +1,7 @@ -From c77834df77a830ed52e78558f67b5e02fa4379f9 Mon Sep 17 00:00:00 2001 +From 9ffbd34c853c426d82f3daf0bb7512fc1b08d611 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 18 May 2026 02:58:36 +0000 -Subject: [PATCH 417/467] FROMLIST: clk: spacemit: k3: fix USB2 bus clock +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix USB2 bus clock According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus clock enable bit was wrongly swapped, the correct one should be: diff --git a/SPECS/linux-lts-kmhv2/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch b/SPECS/linux-lts-kmhv2/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch index 350548f91c..ef6c5cfcb2 100644 --- a/SPECS/linux-lts-kmhv2/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch +++ b/SPECS/linux-lts-kmhv2/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch @@ -1,7 +1,7 @@ -From a9788cf9dae7cfe18b553bd1ae42afe7ef003b45 Mon Sep 17 00:00:00 2001 +From d420aa127fcbe63635453a4103d4d013e9027703 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 18 May 2026 02:58:37 +0000 -Subject: [PATCH 418/467] FROMLIST: reset: spacemit: k3: fix USB2 ahb reset +Subject: [RUYI PATCH] FROMLIST: reset: spacemit: k3: fix USB2 ahb reset According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus clock enable bit was wrongly swapped, the correct one should be: diff --git a/SPECS/linux-lts-kmhv2/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch b/SPECS/linux-lts-kmhv2/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch index 48fdd3cc67..05b9ee6eb7 100644 --- a/SPECS/linux-lts-kmhv2/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch +++ b/SPECS/linux-lts-kmhv2/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch @@ -1,7 +1,7 @@ -From 4224b1f1d490ae209fbb371252179c523d1733f9 Mon Sep 17 00:00:00 2001 +From cf3c64c0e469dac06db3606b299ff2b6be12345c Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 18 May 2026 20:58:16 +0000 -Subject: [PATCH 419/467] FROMLIST: dts: riscv: spacemit: k3: Fix I/O power +Subject: [RUYI PATCH] FROMLIST: dts: riscv: spacemit: k3: Fix I/O power settings SpacemiT K3 SoC support dual-voltage I/O power domain, while initially diff --git a/SPECS/linux-lts-kmhv2/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts-kmhv2/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch index 65aa7a68b9..5640477b61 100644 --- a/SPECS/linux-lts-kmhv2/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch +++ b/SPECS/linux-lts-kmhv2/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch @@ -1,8 +1,8 @@ -From ad3f20a31772c6ad7ebc8fa7c75029764a774a46 Mon Sep 17 00:00:00 2001 +From 24e92b2f714ec09b1217533e18d18a7a1416d52f Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:35 +0200 -Subject: [PATCH 420/467] FROMLIST: riscv: dts: spacemit: set console baud rate - on Milk-V Jupiter +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on + Milk-V Jupiter Because the default console's baud rate is not set, defconfig kernels do not have any serial output on this platform. Set the baud rate to diff --git a/SPECS/linux-lts-kmhv2/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch b/SPECS/linux-lts-kmhv2/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch index 6e6cedf534..f35dbf7a0b 100644 --- a/SPECS/linux-lts-kmhv2/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch +++ b/SPECS/linux-lts-kmhv2/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch @@ -1,8 +1,8 @@ -From 430637bb4afb74146c8c8829d0da513b6bd4c91e Mon Sep 17 00:00:00 2001 +From 8422624a96d6035950f1902cc537f1e7d2a4c281 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:36 +0200 -Subject: [PATCH 421/467] FROMLIST: riscv: dts: spacemit: sort aliases on - Milk-V Jupiter +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: sort aliases on Milk-V + Jupiter Before adding more aliases, just sort them. diff --git a/SPECS/linux-lts-kmhv2/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch b/SPECS/linux-lts-kmhv2/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch index 2dba11e059..ebf0663617 100644 --- a/SPECS/linux-lts-kmhv2/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch +++ b/SPECS/linux-lts-kmhv2/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch @@ -1,7 +1,7 @@ -From 5128b77b7248e5ff6e789388a31e1d4980db9625 Mon Sep 17 00:00:00 2001 +From 72311926929a84047a95c07cdcaf0f7211764d88 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:37 +0200 -Subject: [PATCH 422/467] FROMLIST: riscv: dts: spacemit: enable eMMC on Milk-V +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable eMMC on Milk-V Jupiter The Milk-V Jupiter board has a connector for an eMMC module. Add an diff --git a/SPECS/linux-lts-kmhv2/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch b/SPECS/linux-lts-kmhv2/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch index 8563b02bad..7b0fee89d3 100644 --- a/SPECS/linux-lts-kmhv2/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch +++ b/SPECS/linux-lts-kmhv2/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch @@ -1,8 +1,8 @@ -From e4c393d2cacfe99846fc5b646d0e38cbe35f4d0b Mon Sep 17 00:00:00 2001 +From 629f9f3c4e0f9cca344b52a02ceedd2e91ab9756 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:38 +0200 -Subject: [PATCH 423/467] FROMLIST: riscv: dts: spacemit: enable SD card - support on Milk-V Jupiter +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable SD card support + on Milk-V Jupiter Add complete SD card controller support with UHS high-speed modes. diff --git a/SPECS/linux-lts-kmhv2/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch b/SPECS/linux-lts-kmhv2/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch index b8e8229208..c52a677920 100644 --- a/SPECS/linux-lts-kmhv2/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch +++ b/SPECS/linux-lts-kmhv2/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch @@ -1,7 +1,7 @@ -From 9b3916fc9b9300620706c675eef564914105dc63 Mon Sep 17 00:00:00 2001 +From 396d9a81ca85057f4a8bc7ad711b684dcffafb06 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:39 +0200 -Subject: [PATCH 424/467] FROMLIST: riscv: dts: spacemit: fix uboot partition +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: fix uboot partition offset on Milk-V Jupiter Correct the uboot partition node name to match its actual offset. diff --git a/SPECS/linux-lts-kmhv2/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch b/SPECS/linux-lts-kmhv2/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch index 67c3e016f4..3cee4760cd 100644 --- a/SPECS/linux-lts-kmhv2/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch +++ b/SPECS/linux-lts-kmhv2/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch @@ -1,8 +1,8 @@ -From 79d41f5abc296c99b6a3b3418eb3600e2082a9e3 Mon Sep 17 00:00:00 2001 +From 98c6ddea13512cec403705f0e1898daa262466b1 Mon Sep 17 00:00:00 2001 From: Zhengyu He Date: Thu, 21 May 2026 22:44:46 +0800 -Subject: [PATCH 425/467] FROMLIST: riscv: dts: spacemit: add QSPI support for - K3 Pico-ITX +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: add QSPI support for K3 + Pico-ITX Add K3 QSPI controller node into k3.dtsi, and add related pinmux configuration. diff --git a/SPECS/linux-lts-kmhv2/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch b/SPECS/linux-lts-kmhv2/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch index e4ca4afdfc..2df47fbbeb 100644 --- a/SPECS/linux-lts-kmhv2/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch +++ b/SPECS/linux-lts-kmhv2/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch @@ -1,7 +1,7 @@ -From f8132c56be19ef8420d61eee66dc7352ecdd3ded Mon Sep 17 00:00:00 2001 +From 4188a3bf42259d212c5d61101e694a2dc05e3dd4 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 20 May 2026 00:40:07 +0800 -Subject: [PATCH 426/467] FROMLIST: pinctrl: spacemit: fix NULL check in +Subject: [RUYI PATCH] FROMLIST: pinctrl: spacemit: fix NULL check in spacemit_pin_set_config spacemit_pin_set_config() looks up the per-pin descriptor with diff --git a/SPECS/linux-lts-kmhv2/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch b/SPECS/linux-lts-kmhv2/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch index 02c7c4c58f..950680a506 100644 --- a/SPECS/linux-lts-kmhv2/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch +++ b/SPECS/linux-lts-kmhv2/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch @@ -1,7 +1,7 @@ -From 9255f275eddde413b57b043618f6838db76a010c Mon Sep 17 00:00:00 2001 +From 2e0cced73e82d39a2fd99776f4972c20778cd27b Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 20 May 2026 00:55:46 +0800 -Subject: [PATCH 427/467] FROMLIST: riscv: unconditionally select +Subject: [RUYI PATCH] FROMLIST: riscv: unconditionally select ARCH_KEEP_MEMBLOCK Select ARCH_KEEP_MEMBLOCK unconditionally. kexec requires memblock diff --git a/SPECS/linux-lts-kmhv2/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch b/SPECS/linux-lts-kmhv2/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch index 309e71bdd7..c4ff341f5d 100644 --- a/SPECS/linux-lts-kmhv2/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch +++ b/SPECS/linux-lts-kmhv2/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch @@ -1,8 +1,8 @@ -From 20deb98d0307212f2ae260f532f5c40944d5cfd4 Mon Sep 17 00:00:00 2001 +From 3c28d26c50aa548e866a1681ca068993386a91c3 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 20 May 2026 01:06:41 +0800 -Subject: [PATCH 428/467] FROMLIST: riscv: kexec_file: Constrain segment - placement to direct map +Subject: [RUYI PATCH] FROMLIST: riscv: kexec_file: Constrain segment placement + to direct map When kexec_file_load places segments with buf_max=ULONG_MAX and top_down=true, they land at the highest available physical addresses. diff --git a/SPECS/linux-lts-kmhv2/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch b/SPECS/linux-lts-kmhv2/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch index 970ceb6e88..35f6ab7227 100644 --- a/SPECS/linux-lts-kmhv2/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch +++ b/SPECS/linux-lts-kmhv2/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch @@ -1,7 +1,7 @@ -From f0bf64c6e64658862d7fd2f298df04c873197db3 Mon Sep 17 00:00:00 2001 +From 66203a4e0eefa5812e80d8953dd2e958bbeaa89b Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 20 May 2026 23:45:27 +0000 -Subject: [PATCH 429/467] FROMLIST: dt-bindings: riscv: spacemit: Add K3 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: riscv: spacemit: Add K3 CoM260-IFX board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 diff --git a/SPECS/linux-lts-kmhv2/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch b/SPECS/linux-lts-kmhv2/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch index 2679db01b7..30fcfb32cb 100644 --- a/SPECS/linux-lts-kmhv2/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch +++ b/SPECS/linux-lts-kmhv2/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch @@ -1,8 +1,8 @@ -From c7390a2a3f64b04ffd7c0a83d5e8e49be1607158 Mon Sep 17 00:00:00 2001 +From 204ddf86a80e19378811ebf324fd4e8474fa0834 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 20 May 2026 23:45:28 +0000 -Subject: [PATCH 430/467] FROMLIST: riscv: dts: spacemit: k3: Initial support - for CoM260-IFX board +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Initial support for + CoM260-IFX board The K3 CoM260-IFX board combine with one 260 pins "Gold Finger" computer module with a carrier board. The module integrates the K3 SoC, LPDDR5, diff --git a/SPECS/linux-lts-kmhv2/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch b/SPECS/linux-lts-kmhv2/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch index e7f194e629..70f7cc89e9 100644 --- a/SPECS/linux-lts-kmhv2/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch +++ b/SPECS/linux-lts-kmhv2/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch @@ -1,8 +1,8 @@ -From d2737c5027f8388399e5428feeb50be212faf26b Mon Sep 17 00:00:00 2001 +From 78d249e0f67dafbf778883d6990fcb4c34638969 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 20 May 2026 18:00:00 +0800 -Subject: [PATCH 431/467] FROMLIST: riscv: dts: spacemit: enable PMIC on - OrangePi R2S +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable PMIC on OrangePi + R2S Enable the i2c8 interface and add the connected SpacemiT P1 PMIC and its associated regulators to support voltage regulation on the board. diff --git a/SPECS/linux-lts-kmhv2/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts-kmhv2/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch index 1717fb80dd..5e9e4db788 100644 --- a/SPECS/linux-lts-kmhv2/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch +++ b/SPECS/linux-lts-kmhv2/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch @@ -1,8 +1,8 @@ -From db15fe493d454f8d6639f751b051418ca4ffa796 Mon Sep 17 00:00:00 2001 +From 6aa02cc299f6c36d323e193ab8c1f6118e33d3f9 Mon Sep 17 00:00:00 2001 From: Jennifer Berringer Date: Wed, 20 May 2026 07:11:50 -0400 -Subject: [PATCH 432/467] FROMLIST: riscv: dts: spacemit: set console baud rate - on OrangePi RV2 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on + OrangePi RV2 Set the baud rate to 115200, matching what is used by U-Boot on this platform so that the console is usable even when console options are not diff --git a/SPECS/linux-lts-kmhv2/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch b/SPECS/linux-lts-kmhv2/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch index 19747d8e29..cd9e99e6c3 100644 --- a/SPECS/linux-lts-kmhv2/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch +++ b/SPECS/linux-lts-kmhv2/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch @@ -1,7 +1,7 @@ -From e61fb83553f88a67832eb605add845486af0407c Mon Sep 17 00:00:00 2001 +From 82b7ff76828e1cb4e0a7b4cf12583f33f99e37bc Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Mon, 25 May 2026 12:23:29 +0800 -Subject: [PATCH 433/467] FROMLIST: riscv: mm: Call mark_new_valid_map() after +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Call mark_new_valid_map() after hotplugging vmemmap section_activate() creates new mappings in the vmemmap range without diff --git a/SPECS/linux-lts-kmhv2/0434-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch b/SPECS/linux-lts-kmhv2/0434-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch new file mode 100644 index 0000000000..de078902a8 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0434-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch @@ -0,0 +1,99 @@ +From 39f4f9ff2f7384331b347a162c95587733dbc042 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 26 May 2026 15:22:58 -0400 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add Ziccrse + extension for X100 cores + +Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse +provides a forward progress guarantee on LR/SC sequences in main +memory regions with cacheability and coherence PMAs. + +The SpacemiT X100 core supports it per the SpacemiT K3 hardware +specification. + +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260526-k3-ziccrse-v1-1-c759792ca3a3@riscstar.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 5b17612fe58e..ed046714a7ac 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -36,7 +36,7 @@ cpu_0: cpu@0 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -77,7 +77,7 @@ cpu_1: cpu@1 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -118,7 +118,7 @@ cpu_2: cpu@2 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -159,7 +159,7 @@ cpu_3: cpu@3 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -200,7 +200,7 @@ cpu_4: cpu@4 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -241,7 +241,7 @@ cpu_5: cpu@5 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -282,7 +282,7 @@ cpu_6: cpu@6 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -323,7 +323,7 @@ cpu_7: cpu@7 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0434-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch b/SPECS/linux-lts-kmhv2/0434-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch deleted file mode 100644 index 5d85c8b043..0000000000 --- a/SPECS/linux-lts-kmhv2/0434-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch +++ /dev/null @@ -1,50 +0,0 @@ -From f1a862c276fa513a0c9ccc9835a65f55feeb22d6 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Mon, 24 Nov 2025 20:38:44 +0800 -Subject: [PATCH 434/467] XUANTIE: riscv: dts: th1520: add licheepi4a 16g - support - -From: https://github.com/revyos/th1520-linux-kernel/commit/01a510898e41e704bee1fe58a2c0c0a29cb96548 - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/Makefile | 1 + - .../boot/dts/thead/th1520-lichee-pi-4a-16g.dts | 18 ++++++++++++++++++ - 2 files changed, 19 insertions(+) - create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts - -diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile -index b55a17127c2b..281849e71ccb 100644 ---- a/arch/riscv/boot/dts/thead/Makefile -+++ b/arch/riscv/boot/dts/thead/Makefile -@@ -1,2 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb -+dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a-16g.dtb -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts -new file mode 100644 -index 000000000000..a3a991baf716 ---- /dev/null -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts -@@ -0,0 +1,18 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2023 Han Gao -+ */ -+ -+/dts-v1/; -+ -+#include "th1520-lichee-pi-4a.dts" -+ -+/ { -+ model = "Sipeed Lichee Pi 4A 16G"; -+ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x00000000 0x4 0x00000000>; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0435-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch b/SPECS/linux-lts-kmhv2/0435-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch new file mode 100644 index 0000000000..3c0a31840b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0435-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch @@ -0,0 +1,52 @@ +From 5bf0a7bd6d1da26628096529743d98bfd1be37e1 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 28 May 2026 19:38:39 +0800 +Subject: [RUYI PATCH] FROMLIST: RISC-V: KVM: Enhance the logging check for mmu + mapping + +When enabling dirty ring, the dirty bitmap is disable, and the logging +check is always false as the RISC-V architecture does not select +"NEED_KVM_DIRTY_RING_WITH_BITMAP". Although the dirty log is recorded +since the write path already trying to add the dirty log, the logic for +logging check is broken and some side effect will occurs. + +Enhance the logging check for mmu mapping so it can check both the dirty +ring and the dirty bitmap. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260528113840.2629186-1-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/kvm/mmu.c | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c +index 58f5f3536ffd..a0d9c113258e 100644 +--- a/arch/riscv/kvm/mmu.c ++++ b/arch/riscv/kvm/mmu.c +@@ -157,9 +157,8 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, + enum kvm_mr_change change) + { + /* +- * At this point memslot has been committed and there is an +- * allocated dirty_bitmap[], dirty pages will be tracked while +- * the memory slot is write protected. ++ * At this point memslot has been committed and dirty pages will be ++ * tracked while the memory slot is write protected. + */ + if (change != KVM_MR_DELETE && new->flags & KVM_MEM_LOG_DIRTY_PAGES) + mmu_wp_memory_region(kvm, new->id); +@@ -314,8 +313,8 @@ int kvm_riscv_mmu_map(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot, + struct vm_area_struct *vma; + struct kvm *kvm = vcpu->kvm; + struct kvm_mmu_memory_cache *pcache = &vcpu->arch.mmu_page_cache; +- bool logging = (memslot->dirty_bitmap && +- !(memslot->flags & KVM_MEM_READONLY)) ? true : false; ++ bool logging = kvm_slot_dirty_track_enabled(memslot) && ++ !(memslot->flags & KVM_MEM_READONLY); + unsigned long vma_pagesize, mmu_seq; + struct kvm_gstage gstage; + struct page *page; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0435-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch b/SPECS/linux-lts-kmhv2/0435-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch deleted file mode 100644 index 4ffd3a5571..0000000000 --- a/SPECS/linux-lts-kmhv2/0435-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 48c328f5e19a84fb0c038a92a3aecb8167523082 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 14 May 2025 08:16:15 +0800 -Subject: [PATCH 435/467] REVYOS: riscv: dts: th1520: rename thead to xuantie - -Signed-off-by: Han Gao -[Icenowy: preserve the original compatible to allow Linux to match] -Signed-off-by: Icenowy Zheng ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index e44010810c07..f85d93227170 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -286,7 +286,7 @@ stmmac_axi_config: stmmac-axi-config { - }; - - aon: aon { -- compatible = "thead,th1520-aon"; -+ compatible = "xuantie,th1520-aon", "thead,th1520-aon"; - mboxes = <&mbox_910t 1>; - mbox-names = "aon"; - resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0436-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch b/SPECS/linux-lts-kmhv2/0436-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch new file mode 100644 index 0000000000..3af359443c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0436-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch @@ -0,0 +1,75 @@ +From 1089052df50a4781f12e65e68f2cfeb75dca9d84 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Tue, 2 Jun 2026 18:00:00 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable PCIe on OrangePi + R2S + +Enable the two RTL8125 network controllers and corresponding +PHYs connected via the PCIe controllers on the OrangePi R2S. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20260602100000.2402784-1-amadeus@jmu.edu.cn +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-r2s.dts | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index b13a8d6a2670..919e5b451109 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -23,6 +23,14 @@ chosen { + stdout-path = "serial0"; + }; + ++ pcie_vcc3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie_vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + vcc4v0: regulator-vcc4v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0"; +@@ -228,6 +236,36 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie2 { ++ status = "okay"; ++}; ++ + &pdma { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0436-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch b/SPECS/linux-lts-kmhv2/0436-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch deleted file mode 100644 index ba1a3a3e56..0000000000 --- a/SPECS/linux-lts-kmhv2/0436-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch +++ /dev/null @@ -1,44 +0,0 @@ -From e973bd6b6cca07542eeec6f28391bf5e9bf49ef3 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 14 May 2025 08:27:18 +0800 -Subject: [PATCH 436/467] REVYOS: riscv: dts: th1520: add xuantie,th1520-mbox-r - -Signed-off-by: Han Gao -[Icenowy: remove the interrupt-controller property] -Signed-off-by: Icenowy Zheng ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index f85d93227170..ab681cf850d1 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -292,6 +292,24 @@ aon: aon { - resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; - reset-names = "gpu-clkgen"; - #power-domain-cells = <1>; -+ opensbi-mboxes = <&mbox_910r>; -+ status = "okay"; -+ }; -+ -+ mbox_910r: mbox@ffefc53000 { -+ compatible = "xuantie,th1520-mbox-r"; -+ reg = <0xff 0xefc53000 0x0 0x4000>, -+ <0xff 0xefc3f000 0x0 0x1000>, -+ <0xff 0xefc47000 0x0 0x1000>, -+ <0xff 0xefc4f000 0x0 0x1000>; -+ reg-names = "local_base", -+ "remote_icu0", -+ "remote_icu1", -+ "remote_icu2"; -+ clocks = <&clk CLK_PERI_APB_PCLK>; -+ clock-names = "ipg"; -+ icu_cpu_id = <3>; -+ #mbox-cells = <2>; - }; - - soc { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0437-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch b/SPECS/linux-lts-kmhv2/0437-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch new file mode 100644 index 0000000000..0150c1e446 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0437-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch @@ -0,0 +1,105 @@ +From 63031abd1c4c52dfc3b406612721eff99c69ed49 Mon Sep 17 00:00:00 2001 +From: Wang Yechao +Date: Thu, 4 Jun 2026 14:55:10 +0800 +Subject: [RUYI PATCH] FROMLIST: iommu/riscv: Add dependency between iommu and + devices + +Commit 9156585280f1 ("ACPI: RIMT: Add dependency between iommu and +devices") adds the dependency between iommu and devices on ACPI +systems. On devicetree systems, the incorrect removal order also +occurs. + +It can be reproduced on the QEMU RISC-V machine if the kernel enables +IOMMU_DMA: + +[ 635.081530] e1000e: EEE TX LPI TIMER: 00000000 +[ 656.100306] rcu: INFO: rcu_sched self-detected stall on CPU +[ 656.101374] rcu: 5-....: (5250 ticks this GP) idle=d774/1/0x4000000000000000 softirq=5173/5185 fqs=2625 +[ 656.102237] rcu: (t=5251 jiffies g=36825 q=101 ncpus=16) +[ 656.103801] CPU: 5 UID: 0 PID: 1958 Comm: reboot Tainted: G W 7.1.0-rc5 #31 PREEMPTLAZY +[ 656.104127] Tainted: [W]=WARN +[ 656.104182] Hardware name: QEMU QEMU Virtual Machine, BIOS 2.7 02/02/2022 +[ 656.104339] epc : riscv_iommu_cmd_sync.constprop.0+0xb8/0x148 +[ 656.105352] ra : riscv_iommu_cmd_sync.constprop.0+0xa8/0x148 +[ 656.105433] epc : ffffffff807ca980 ra : ffffffff807ca970 sp : ff60000085dbf960 +[ 656.105475] gp : ffffffff81e0d798 tp : ff60000084b58e00 t0 : ffffffff80021048 +[ 656.105514] t1 : ff60000081b18400 t2 : 45203a6530303031 s0 : ff60000085dbf9c0 +[ 656.105554] s1 : 00000098c92a567c a0 : 00000098c03986f0 a1 : ff60000085dbf970 +[ 656.105594] a2 : 000024bb5cac6aee a3 : ff200000004f1000 a4 : ff6000008140a040 +[ 656.105632] a5 : 0000000000000669 a6 : 0000000000000000 a7 : 00000000ffffa000 +[ 656.105669] s2 : 0000000000000000 s3 : 00000098c0398308 s4 : 000000000000066a +[ 656.105706] s5 : 0000000008f0d180 s6 : 000000a8d08b8de9 s7 : 0000000000001fff +[ 656.105743] s8 : ff6000008140a040 s9 : ff6000008484cb00 s10: ff200000005cc000 +[ 656.105781] s11: ff600000814652a0 t3 : 000000f000000000 t4 : 0000000000000000 +[ 656.105845] t5 : 0000000000000003 t6 : ff600000841666b0 ssp : 0000000000000000 +[ 656.105883] status: 0000000200000120 badaddr: 0000000000000000 cause: 8000000000000005 +[ 656.106072] riscv_iommu_cmd_sync.constprop.0+0xb8/0x148 +[ 656.106321] riscv_iommu_iotlb_inval+0x120/0x160 +[ 656.106373] riscv_iommu_iotlb_sync+0x48/0x60 +[ 656.106422] __iommu_dma_unmap+0xca/0xf8 +[ 656.106470] iommu_dma_unmap_phys+0x58/0xc8 +[ 656.106517] dma_unmap_phys+0x15c/0x248 +[ 656.106564] dma_unmap_page_attrs+0x1e/0x30 +[ 656.106915] e1000_clean_rx_ring+0x1d2/0x200 [e1000e] +[ 656.107668] e1000e_down+0x168/0x1c8 [e1000e] +[ 656.107995] e1000e_pm_freeze+0x94/0x128 [e1000e] +[ 656.108328] e1000_shutdown+0x28/0x48 [e1000e] +[ 656.108652] pci_device_shutdown+0x34/0x48 +[ 656.108706] device_shutdown+0x104/0x1e8 +[ 656.108752] kernel_restart+0x46/0xb8 +[ 656.108797] __do_sys_reboot+0xc0/0x1c8 +[ 656.108840] __riscv_sys_reboot+0x22/0x38 +[ 656.108882] do_trap_ecall_u+0x236/0x3f8 +[ 656.108947] handle_exception+0x15a/0x166 + +So move the device link into the iommu driver to fix both ACPI and +devicetree systems. + +Fixes: 488ffbf18171 ("iommu/riscv: Paging domain support") +Signed-off-by: Wang Yechao +Link: https://lore.kernel.org/r/20260604145510898G2kTwM2Pr25QE5H8T4Wh6@zte.com.cn +Signed-off-by: Han Gao +--- + drivers/acpi/riscv/rimt.c | 7 ------- + drivers/iommu/riscv/iommu.c | 7 +++++++ + 2 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/acpi/riscv/rimt.c b/drivers/acpi/riscv/rimt.c +index 8eaa8731bddd..7f423405e5ef 100644 +--- a/drivers/acpi/riscv/rimt.c ++++ b/drivers/acpi/riscv/rimt.c +@@ -263,13 +263,6 @@ static int rimt_iommu_xlate(struct device *dev, struct acpi_rimt_node *node, u32 + if (!rimt_fwnode) + return -EPROBE_DEFER; + +- /* +- * EPROBE_DEFER ensures IOMMU is probed before the devices that +- * depend on them. During shutdown, however, the IOMMU may be removed +- * first, leading to issues. To avoid this, a device link is added +- * which enforces the correct removal order. +- */ +- device_link_add(dev, rimt_fwnode->dev, DL_FLAG_AUTOREMOVE_CONSUMER); + return acpi_iommu_fwspec_init(dev, deviceid, rimt_fwnode); + } + +diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c +index de286563bd44..07ae3c4ec38e 100644 +--- a/drivers/iommu/riscv/iommu.c ++++ b/drivers/iommu/riscv/iommu.c +@@ -1598,6 +1598,13 @@ static struct iommu_device *riscv_iommu_probe_device(struct device *dev) + + dev_iommu_priv_set(dev, info); + ++ /* ++ * During shutdown, however, the IOMMU may be removed first, leading ++ * to issues. To avoid this, a device link is added which enforces ++ * the correct removal order. ++ */ ++ device_link_add(dev, fwspec->iommu_fwnode->dev, DL_FLAG_AUTOREMOVE_CONSUMER); ++ + return &iommu->iommu; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0437-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch b/SPECS/linux-lts-kmhv2/0437-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch deleted file mode 100644 index 3913520ac4..0000000000 --- a/SPECS/linux-lts-kmhv2/0437-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 58b84bc14138597b9031f9e8d047b52130e77045 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 19 Nov 2023 21:13:31 +0800 -Subject: [PATCH 437/467] SOPHGO: dt-bindings: nvmem: Add SG2044 eFuse - controller - -Sophgo SG2044 uses eFuses used to store factory-programmed data -such as ROM patch, public keys and other factory information. - -Signed-off-by: Inochi Amaoto ---- - .../bindings/nvmem/sophgo,efuse.yaml | 61 +++++++++++++++++++ - 1 file changed, 61 insertions(+) - create mode 100644 Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml - -diff --git a/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml -new file mode 100644 -index 000000000000..d4bffe2724ac ---- /dev/null -+++ b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml -@@ -0,0 +1,61 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/nvmem/sophgo,efuse.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Sophgo SoC eFuse-based NVMEM -+ -+description: -+ Sophgo SoCs contain factory-programmed eFuses used to store ROM patch, -+ public key and other factory information. -+ -+maintainers: -+ - Inochi Amaoto -+ -+allOf: -+ - $ref: nvmem.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - sophgo,sg2044-efuse -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 1 -+ items: -+ - description: Core clock -+ - description: APB clock -+ -+ clock-names: -+ minItems: 1 -+ items: -+ - const: core -+ - const: apb -+ -+ resets: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ efuse@40000000 { -+ compatible = "sophgo,sg2044-efuse"; -+ reg = <0x40000000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&clk 0>, -+ <&clk 1>; -+ clock-names = "core", "apb"; -+ }; -+ -+... --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0438-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch b/SPECS/linux-lts-kmhv2/0438-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch deleted file mode 100644 index 7a5c632111..0000000000 --- a/SPECS/linux-lts-kmhv2/0438-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 6ac29107a01f6a190188cc8c4ed3d8f9ac21c834 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 19 Nov 2023 21:13:32 +0800 -Subject: [PATCH 438/467] SOPHGO: nvmem: Add Sophgo SG2044 eFuse driver - -Sophgo SoCs such as SG2044 contain eFuses used to store -factory-programmed data. - -As for SG2044, HW automatically loads the eFuse content -into shadow registers which are organized as 32bit values -exposed as MMIO. - -Signed-off-by: Inochi Amaoto ---- - drivers/nvmem/Kconfig | 12 +++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/sophgo-efuse.c | 176 +++++++++++++++++++++++++++++++++++ - 3 files changed, 190 insertions(+) - create mode 100644 drivers/nvmem/sophgo-efuse.c - -diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig -index 11b098705ec6..42f46eb0462a 100644 ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -356,6 +356,18 @@ config NVMEM_SNVS_LPGPR - This driver can also be built as a module. If so, the module - will be called nvmem-snvs-lpgpr. - -+config NVMEM_SOPHGO_EFUSE -+ tristate "Sophgo eFuse support" -+ depends on ARCH_SOPHGO || COMPILE_TEST -+ default ARCH_SOPHGO -+ help -+ Say y here to enable support for reading eFuses on Sophgo SoCs -+ such as the CV1800B. These are e.g. used to store factory programmed -+ calibration data required for the builtin ethernet PHY. -+ -+ This driver can also be built as a module. If so, the module will -+ be called nvmem-sophgo-efuse. -+ - config NVMEM_SPMI_SDAM - tristate "SPMI SDAM Support" - depends on SPMI -diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile -index 70a4464dcb1e..6cc324aaa757 100644 ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -70,6 +70,8 @@ obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o - nvmem-sc27xx-efuse-y := sc27xx-efuse.o - obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o - nvmem_snvs_lpgpr-y := snvs_lpgpr.o -+obj-$(CONFIG_NVMEM_SOPHGO_EFUSE) += nvmem-sophgo-efuse.o -+nvmem-sophgo-efuse-y := sophgo-efuse.o - obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o - nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o - obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o -diff --git a/drivers/nvmem/sophgo-efuse.c b/drivers/nvmem/sophgo-efuse.c -new file mode 100644 -index 000000000000..5f90adaf8e4f ---- /dev/null -+++ b/drivers/nvmem/sophgo-efuse.c -@@ -0,0 +1,176 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Sophgo SoC eFuse driver -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define SG2044_EFUSE_CONTENT_SIZE 0x400 -+ -+#define SG2044_EFUSE_MD 0x000 -+#define SG2044_EFUSE_ADR 0x004 -+#define SG2044_EFUSE_RD_DATA 0x00c -+ -+#define SG2044_EFUSE_MODE GENMASK(1, 0) -+#define SG2044_EFUSE_MODE_READ 2 -+ -+#define SG2044_EFUSE_BOOT_DONE BIT(7) -+#define SG2044_BOOT_TIMEOUT 10000 -+ -+#define SG2044_EFUSE_ADR_ADDR GENMASK(7, 0) -+ -+#define SG2044_EFUSE_ALIGN 4 -+ -+struct sophgo_efuses { -+ void __iomem *base; -+ struct clk_bulk_data *clks; -+ int num_clks; -+ struct mutex mutex; -+}; -+ -+static int sg2044_efuse_wait_mode(struct sophgo_efuses *efuse) -+{ -+ u32 value; -+ -+ return readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, -+ FIELD_GET(SG2044_EFUSE_MODE, value) == 0, -+ 1, SG2044_BOOT_TIMEOUT); -+} -+ -+static int sg2044_efuse_set_mode(struct sophgo_efuses *efuse, int mode) -+{ -+ u32 val = readl(efuse->base + SG2044_EFUSE_MD); -+ -+ val &= ~SG2044_EFUSE_MODE; -+ val |= FIELD_PREP(SG2044_EFUSE_MODE, mode); -+ -+ writel(val, efuse->base + SG2044_EFUSE_MD); -+ -+ return sg2044_efuse_wait_mode(efuse); -+} -+ -+static u32 sg2044_efuses_read_strip(struct sophgo_efuses *efuse, -+ unsigned int offset, u32 *strip) -+{ -+ u32 val = FIELD_PREP(SG2044_EFUSE_ADR_ADDR, offset); -+ int ret; -+ -+ guard(mutex)(&efuse->mutex); -+ -+ writel(val, efuse->base + SG2044_EFUSE_ADR); -+ -+ ret = sg2044_efuse_set_mode(efuse, SG2044_EFUSE_MODE_READ); -+ if (ret < 0) -+ return ret; -+ -+ *strip = readl(efuse->base + SG2044_EFUSE_RD_DATA); -+ -+ return 0; -+} -+ -+static int sg2044_efuses_read(void *context, unsigned int offset, void *val, -+ size_t bytes) -+{ -+ struct sophgo_efuses *efuse = context; -+ unsigned int start, start_offset, end, i; -+ u32 value; -+ u8 *buf; -+ int ret; -+ -+ start = rounddown(offset, SG2044_EFUSE_ALIGN); -+ end = roundup(offset + bytes, SG2044_EFUSE_ALIGN); -+ start_offset = offset - start; -+ -+ start /= SG2044_EFUSE_ALIGN; -+ end /= SG2044_EFUSE_ALIGN; -+ -+ ret = readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, -+ (value & SG2044_EFUSE_BOOT_DONE), -+ 1, SG2044_BOOT_TIMEOUT); -+ if (ret < 0) -+ return ret; -+ -+ buf = kzalloc(end - start, GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ for (i = start; i < end; i++) { -+ ret = sg2044_efuses_read_strip(efuse, i, &value); -+ if (ret) -+ goto failed; -+ -+ memcpy(&buf[(i - start) * 4], &value, SG2044_EFUSE_ALIGN); -+ } -+ -+ memcpy(val, buf + start_offset, bytes); -+ -+failed: -+ kfree(buf); -+ -+ return ret; -+} -+ -+static int sophgo_efuses_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct sophgo_efuses *efuse; -+ struct nvmem_config config = { -+ .dev = &pdev->dev, -+ .add_legacy_fixed_of_cells = true, -+ .read_only = true, -+ .reg_read = sg2044_efuses_read, -+ .stride = 1, -+ .word_size = 1, -+ .name = "sophgo-efuse", -+ .id = NVMEM_DEVID_AUTO, -+ .root_only = true, -+ }; -+ -+ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); -+ if (!efuse) -+ return -ENOMEM; -+ -+ efuse->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(efuse->base)) -+ return PTR_ERR(efuse->base); -+ -+ efuse->num_clks = devm_clk_bulk_get_all_enabled(&pdev->dev, &efuse->clks); -+ if (efuse->num_clks < 0) -+ return dev_err_probe(dev, efuse->num_clks, "failed to get clocks\n"); -+ -+ config.priv = efuse; -+ config.size = SG2044_EFUSE_CONTENT_SIZE; -+ -+ return PTR_ERR_OR_ZERO(devm_nvmem_register(config.dev, &config)); -+} -+ -+static const struct of_device_id sophgo_efuses_of_match[] = { -+ { .compatible = "sophgo,sg2044-efuse", }, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(of, sophgo_efuses_of_match); -+ -+static struct platform_driver sophgo_efuses_driver = { -+ .driver = { -+ .name = "sophgo_efuse", -+ .of_match_table = sophgo_efuses_of_match, -+ }, -+ .probe = sophgo_efuses_probe, -+}; -+ -+module_platform_driver(sophgo_efuses_driver); -+ -+MODULE_AUTHOR("Inochi Amaoto "); -+MODULE_DESCRIPTION("Sophgo efuse driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0438-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch b/SPECS/linux-lts-kmhv2/0438-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch new file mode 100644 index 0000000000..19a9ca6539 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0438-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch @@ -0,0 +1,49 @@ +From 202c07f948325a5c584ae346de90b289bd86b125 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Mon, 24 Nov 2025 20:38:44 +0800 +Subject: [RUYI PATCH] XUANTIE: riscv: dts: th1520: add licheepi4a 16g support + +From: https://github.com/revyos/th1520-linux-kernel/commit/01a510898e41e704bee1fe58a2c0c0a29cb96548 + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/Makefile | 1 + + .../boot/dts/thead/th1520-lichee-pi-4a-16g.dts | 18 ++++++++++++++++++ + 2 files changed, 19 insertions(+) + create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts + +diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile +index b55a17127c2b..281849e71ccb 100644 +--- a/arch/riscv/boot/dts/thead/Makefile ++++ b/arch/riscv/boot/dts/thead/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb ++dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a-16g.dtb +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts +new file mode 100644 +index 000000000000..a3a991baf716 +--- /dev/null ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts +@@ -0,0 +1,18 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 Han Gao ++ */ ++ ++/dts-v1/; ++ ++#include "th1520-lichee-pi-4a.dts" ++ ++/ { ++ model = "Sipeed Lichee Pi 4A 16G"; ++ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x00000000 0x4 0x00000000>; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0439-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch b/SPECS/linux-lts-kmhv2/0439-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch new file mode 100644 index 0000000000..1c294c8a28 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0439-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch @@ -0,0 +1,28 @@ +From 7b0831ac6fa2e8db34c9c89d4e02bf2aa105fab3 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 14 May 2025 08:16:15 +0800 +Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: rename thead to xuantie + +Signed-off-by: Han Gao +[Icenowy: preserve the original compatible to allow Linux to match] +Signed-off-by: Icenowy Zheng +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index e44010810c07..f85d93227170 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -286,7 +286,7 @@ stmmac_axi_config: stmmac-axi-config { + }; + + aon: aon { +- compatible = "thead,th1520-aon"; ++ compatible = "xuantie,th1520-aon", "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0439-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch b/SPECS/linux-lts-kmhv2/0439-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch deleted file mode 100644 index 13be292227..0000000000 --- a/SPECS/linux-lts-kmhv2/0439-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 067900c6efeb7cfec72358b2de3190c383988fb7 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Thu, 5 Dec 2024 13:24:13 +0800 -Subject: [PATCH 439/467] SOPHGO: riscv: dts: sophgo: sg2044: Add eFUSE device - -Add eFUSE controller node for SG2044. - -Signed-off-by: Inochi Amaoto ---- - arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ - arch/riscv/boot/dts/sophgo/sg2044.dtsi | 12 ++++++++++++ - 2 files changed, 16 insertions(+) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -index fed3d9a384a0..1b506972d465 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -@@ -36,6 +36,10 @@ &emmc { - status = "okay"; - }; - -+&efuse0 { -+ status = "okay"; -+}; -+ - &gmac0 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; -diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -index 320c4d1d08e6..9577aae08f7f 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -@@ -408,6 +408,18 @@ sd: mmc@703000b000 { - status = "disabled"; - }; - -+ efuse0: efuse@7040000000 { -+ compatible = "sophgo,sg2044-efuse"; -+ reg = <0x70 0x40000000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&clk CLK_GATE_EFUSE>, -+ <&clk CLK_GATE_APB_EFUSE>; -+ clock-names = "core", "apb"; -+ resets = <&rst RST_EFUSE0>; -+ status = "disabled"; -+ }; -+ - i2c0: i2c@7040005000 { - compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; - reg = <0x70 0x40005000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0440-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch b/SPECS/linux-lts-kmhv2/0440-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch new file mode 100644 index 0000000000..757ee92472 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0440-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch @@ -0,0 +1,44 @@ +From 1fa033781168266e279c276df269822336f8d946 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 14 May 2025 08:27:18 +0800 +Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: add xuantie,th1520-mbox-r + +Signed-off-by: Han Gao +[Icenowy: remove the interrupt-controller property] +Signed-off-by: Icenowy Zheng +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index f85d93227170..ab681cf850d1 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -292,6 +292,24 @@ aon: aon { + resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; + reset-names = "gpu-clkgen"; + #power-domain-cells = <1>; ++ opensbi-mboxes = <&mbox_910r>; ++ status = "okay"; ++ }; ++ ++ mbox_910r: mbox@ffefc53000 { ++ compatible = "xuantie,th1520-mbox-r"; ++ reg = <0xff 0xefc53000 0x0 0x4000>, ++ <0xff 0xefc3f000 0x0 0x1000>, ++ <0xff 0xefc47000 0x0 0x1000>, ++ <0xff 0xefc4f000 0x0 0x1000>; ++ reg-names = "local_base", ++ "remote_icu0", ++ "remote_icu1", ++ "remote_icu2"; ++ clocks = <&clk CLK_PERI_APB_PCLK>; ++ clock-names = "ipg"; ++ icu_cpu_id = <3>; ++ #mbox-cells = <2>; + }; + + soc { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0440-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch b/SPECS/linux-lts-kmhv2/0440-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch deleted file mode 100644 index 4dd1171275..0000000000 --- a/SPECS/linux-lts-kmhv2/0440-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 819aa39c2d1a6d2c6cbde41fb83516b927d08626 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Sun, 28 Dec 2025 23:02:15 +0800 -Subject: [PATCH 440/467] SOPHGO: dts: sg2044: Modify pcie bar address - -FROM: https://github.com/sophgo/linux-riscv/commit/efddc3e2d3d57b27054415afb522100e6dce8692 - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2044.dtsi | 28 +++++++++++++------------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -index 9577aae08f7f..f1377ee8e149 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -@@ -36,7 +36,7 @@ pcie0: pcie@6c00000000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x00000000 0x0 0x00001000>, - <0x6c 0x00300000 0x0 0x00004000>, -- <0x48 0x00000000 0x0 0x00001000>, -+ <0x50 0x00000000 0x0 0x00001000>, - <0x6c 0x000c0000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -51,11 +51,11 @@ pcie0: pcie@6c00000000 { - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, - <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, -- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, -- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x54 0x00000000 0x54 0x00000000 0x4 0x00000000>, -+ <0x03000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>; - status = "disabled"; - - pcie_intc0: interrupt-controller { -@@ -89,8 +89,8 @@ pcie1: pcie@6c00400000 { - ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>, - <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>, -- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, -- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x44 0x00000000 0x44 0x00000000 0x4 0x00000000>, -+ <0x03000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>; - status = "disabled"; - - pcie_intc1: interrupt-controller { -@@ -106,7 +106,7 @@ pcie2: pcie@6c04000000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x04000000 0x0 0x00001000>, - <0x6c 0x04300000 0x0 0x00004000>, -- <0x58 0x00000000 0x0 0x00001000>, -+ <0x7c 0x00000000 0x0 0x00001000>, - <0x6c 0x040c0000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -121,11 +121,11 @@ pcie2: pcie@6c04000000 { - <0 0 0 3 &pcie_intc2 2>, - <0 0 0 4 &pcie_intc2 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x7c 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>, - <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>, -- <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>, -- <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x7d 0x00000000 0x7d 0x00000000 0x1 0x00000000>, -+ <0x03000000 0x7c 0x80000000 0x7c 0x80000000 0x0 0x80000000>; - status = "disabled"; - - pcie_intc2: interrupt-controller { -@@ -141,7 +141,7 @@ pcie3: pcie@6c04400000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x04400000 0x0 0x00001000>, - <0x6c 0x04700000 0x0 0x00004000>, -- <0x50 0x00000000 0x0 0x00001000>, -+ <0x78 0x00000000 0x0 0x00001000>, - <0x6c 0x04780000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -156,11 +156,11 @@ pcie3: pcie@6c04400000 { - <0 0 0 3 &pcie_intc3 2>, - <0 0 0 4 &pcie_intc3 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x78 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>, - <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>, -- <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>, -- <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x79 0x00000000 0x79 0x00000000 0x1 0x00000000>, -+ <0x03000000 0x78 0x80000000 0x78 0x80000000 0x0 0x80000000>; - status = "disabled"; - - pcie_intc3: interrupt-controller { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0441-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch b/SPECS/linux-lts-kmhv2/0441-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch new file mode 100644 index 0000000000..79f21e68df --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0441-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch @@ -0,0 +1,84 @@ +From 40d9d7d4261e84ef42987558481248dd8a8a89b0 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 19 Nov 2023 21:13:31 +0800 +Subject: [RUYI PATCH] SOPHGO: dt-bindings: nvmem: Add SG2044 eFuse controller + +Sophgo SG2044 uses eFuses used to store factory-programmed data +such as ROM patch, public keys and other factory information. + +Signed-off-by: Inochi Amaoto +--- + .../bindings/nvmem/sophgo,efuse.yaml | 61 +++++++++++++++++++ + 1 file changed, 61 insertions(+) + create mode 100644 Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml + +diff --git a/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml +new file mode 100644 +index 000000000000..d4bffe2724ac +--- /dev/null ++++ b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml +@@ -0,0 +1,61 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/nvmem/sophgo,efuse.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Sophgo SoC eFuse-based NVMEM ++ ++description: ++ Sophgo SoCs contain factory-programmed eFuses used to store ROM patch, ++ public key and other factory information. ++ ++maintainers: ++ - Inochi Amaoto ++ ++allOf: ++ - $ref: nvmem.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - sophgo,sg2044-efuse ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 1 ++ items: ++ - description: Core clock ++ - description: APB clock ++ ++ clock-names: ++ minItems: 1 ++ items: ++ - const: core ++ - const: apb ++ ++ resets: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ efuse@40000000 { ++ compatible = "sophgo,sg2044-efuse"; ++ reg = <0x40000000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&clk 0>, ++ <&clk 1>; ++ clock-names = "core", "apb"; ++ }; ++ ++... +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0441-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch b/SPECS/linux-lts-kmhv2/0441-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch deleted file mode 100644 index 23c3d7b4f9..0000000000 --- a/SPECS/linux-lts-kmhv2/0441-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch +++ /dev/null @@ -1,30 +0,0 @@ -From c9a6181747df1dd9980ccca9e4e34a51afc1f1db Mon Sep 17 00:00:00 2001 -From: Xiaoguang Xing -Date: Mon, 22 Jan 2024 10:31:30 +0800 -Subject: [PATCH 441/467] SOPHGO: riscv: sg2042: errata: Replace thead cache - clean with flush - -FROM: https://github.com/sophgo/linux-riscv/commit/9f8fdd99aae6ae8f037ad9c80b968de7c4252a65 - -Signed-off-by: Xiaoguang Xing -Signed-off-by: Han Gao ---- - arch/riscv/errata/thead/errata.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c -index fbe46f2fa8fb..9be8c45f4531 100644 ---- a/arch/riscv/errata/thead/errata.c -+++ b/arch/riscv/errata/thead/errata.c -@@ -67,7 +67,7 @@ static bool errata_probe_mae(unsigned int stage, - * 0000000 11001 00000 000 00000 0001011 - */ - #define THEAD_INVAL_A0 ".long 0x02a5000b" --#define THEAD_CLEAN_A0 ".long 0x0295000b" -+#define THEAD_CLEAN_A0 ".long 0x02b5000b" - #define THEAD_FLUSH_A0 ".long 0x02b5000b" - #define THEAD_SYNC_S ".long 0x0190000b" - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0442-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch b/SPECS/linux-lts-kmhv2/0442-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch deleted file mode 100644 index ff15f677fa..0000000000 --- a/SPECS/linux-lts-kmhv2/0442-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 5d179609e5c15e909b3700913113fa6b03c0cb53 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Fri, 24 Oct 2025 15:59:17 +0800 -Subject: [PATCH 442/467] REVYSR: dt-bindings: net: ultrarisc,dp1000-gmac: Add - support for Ultrarisc DP1000 GMAC - -The GMAC IP on DP1000 is a standard Synopsys DesignWare MAC -(version 5.10a). - -Add necessary compatible string for this device. - -Signed-off-by: Han Gao -Signed-off-by: Han Gao -FROM: https://github.com/RevySR/linux/commit/5eda7fb5c988909f44edab38678cd124a9a5b98f -Signed-off-by: Han Gao ---- - .../devicetree/bindings/net/snps,dwmac.yaml | 1 + - .../bindings/net/ultrarisc,dp1000-gmac.yaml | 89 +++++++++++++++++++ - 2 files changed, 90 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml - -diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -index eb36cb36a57a..a8a45b844335 100644 ---- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml -+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -@@ -113,6 +113,7 @@ properties: - - starfive,jh7110-dwmac - - tesla,fsd-ethqos - - thead,th1520-gmac -+ - ultrarisc,dp1000-gmac - - reg: - minItems: 1 -diff --git a/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml -new file mode 100644 -index 000000000000..ace5c4058cc9 ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml -@@ -0,0 +1,89 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/ultrarisc,dp1000-gmac.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Ultrarisc dp1000 glue layer -+ -+maintainers: -+ - Han Gao -+ -+select: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - ultrarisc,dp1000-gmac -+ required: -+ - compatible -+ -+properties: -+ compatible: -+ oneOf: -+ - items: -+ - const: ultrarisc,dp1000-gmac -+ - const: snps,dwmac-5.10a -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: GMAC main clock -+ - description: PTP clock -+ - description: TX clock -+ -+ clock-names: -+ items: -+ - const: stmmaceth -+ -+ dma-noncoherent: true -+ -+ interrupts: -+ maxItems: 1 -+ -+ interrupt-names: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - interrupt-names -+ -+allOf: -+ - $ref: snps,dwmac.yaml# -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ -+ ethernet1@38000000 { -+ clocks = <&csr_clk>; -+ clock-names = "stmmaceth"; -+ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; -+ interrupt-parent = <0x01>; -+ interrupts = <84>; -+ interrupt-names = "macirq"; -+ reg = <0x00 0x38000000 0x00 0x1000000>; -+ local-mac-address = [ff ff ff ff ff ff]; -+ phy-mode = "rgmii"; -+ max-speed = <1000>; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ phy-handle = <&phy0>; -+ mdio { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ compatible = "snps,dwmac-mdio"; -+ phy0: phy@0{ -+ reg = <0x00>; -+ status = "okay"; -+ }; -+ }; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch b/SPECS/linux-lts-kmhv2/0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch new file mode 100644 index 0000000000..2ebd4453f3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch @@ -0,0 +1,241 @@ +From e96eabf82535fd6f2fc338f3f5af2fb50721a459 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 19 Nov 2023 21:13:32 +0800 +Subject: [RUYI PATCH] SOPHGO: nvmem: Add Sophgo SG2044 eFuse driver + +Sophgo SoCs such as SG2044 contain eFuses used to store +factory-programmed data. + +As for SG2044, HW automatically loads the eFuse content +into shadow registers which are organized as 32bit values +exposed as MMIO. + +Signed-off-by: Inochi Amaoto +--- + drivers/nvmem/Kconfig | 12 +++ + drivers/nvmem/Makefile | 2 + + drivers/nvmem/sophgo-efuse.c | 176 +++++++++++++++++++++++++++++++++++ + 3 files changed, 190 insertions(+) + create mode 100644 drivers/nvmem/sophgo-efuse.c + +diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig +index 11b098705ec6..42f46eb0462a 100644 +--- a/drivers/nvmem/Kconfig ++++ b/drivers/nvmem/Kconfig +@@ -356,6 +356,18 @@ config NVMEM_SNVS_LPGPR + This driver can also be built as a module. If so, the module + will be called nvmem-snvs-lpgpr. + ++config NVMEM_SOPHGO_EFUSE ++ tristate "Sophgo eFuse support" ++ depends on ARCH_SOPHGO || COMPILE_TEST ++ default ARCH_SOPHGO ++ help ++ Say y here to enable support for reading eFuses on Sophgo SoCs ++ such as the CV1800B. These are e.g. used to store factory programmed ++ calibration data required for the builtin ethernet PHY. ++ ++ This driver can also be built as a module. If so, the module will ++ be called nvmem-sophgo-efuse. ++ + config NVMEM_SPMI_SDAM + tristate "SPMI SDAM Support" + depends on SPMI +diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile +index 70a4464dcb1e..6cc324aaa757 100644 +--- a/drivers/nvmem/Makefile ++++ b/drivers/nvmem/Makefile +@@ -70,6 +70,8 @@ obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o + nvmem-sc27xx-efuse-y := sc27xx-efuse.o + obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o + nvmem_snvs_lpgpr-y := snvs_lpgpr.o ++obj-$(CONFIG_NVMEM_SOPHGO_EFUSE) += nvmem-sophgo-efuse.o ++nvmem-sophgo-efuse-y := sophgo-efuse.o + obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o + nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o + obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o +diff --git a/drivers/nvmem/sophgo-efuse.c b/drivers/nvmem/sophgo-efuse.c +new file mode 100644 +index 000000000000..5f90adaf8e4f +--- /dev/null ++++ b/drivers/nvmem/sophgo-efuse.c +@@ -0,0 +1,176 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Sophgo SoC eFuse driver ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SG2044_EFUSE_CONTENT_SIZE 0x400 ++ ++#define SG2044_EFUSE_MD 0x000 ++#define SG2044_EFUSE_ADR 0x004 ++#define SG2044_EFUSE_RD_DATA 0x00c ++ ++#define SG2044_EFUSE_MODE GENMASK(1, 0) ++#define SG2044_EFUSE_MODE_READ 2 ++ ++#define SG2044_EFUSE_BOOT_DONE BIT(7) ++#define SG2044_BOOT_TIMEOUT 10000 ++ ++#define SG2044_EFUSE_ADR_ADDR GENMASK(7, 0) ++ ++#define SG2044_EFUSE_ALIGN 4 ++ ++struct sophgo_efuses { ++ void __iomem *base; ++ struct clk_bulk_data *clks; ++ int num_clks; ++ struct mutex mutex; ++}; ++ ++static int sg2044_efuse_wait_mode(struct sophgo_efuses *efuse) ++{ ++ u32 value; ++ ++ return readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, ++ FIELD_GET(SG2044_EFUSE_MODE, value) == 0, ++ 1, SG2044_BOOT_TIMEOUT); ++} ++ ++static int sg2044_efuse_set_mode(struct sophgo_efuses *efuse, int mode) ++{ ++ u32 val = readl(efuse->base + SG2044_EFUSE_MD); ++ ++ val &= ~SG2044_EFUSE_MODE; ++ val |= FIELD_PREP(SG2044_EFUSE_MODE, mode); ++ ++ writel(val, efuse->base + SG2044_EFUSE_MD); ++ ++ return sg2044_efuse_wait_mode(efuse); ++} ++ ++static u32 sg2044_efuses_read_strip(struct sophgo_efuses *efuse, ++ unsigned int offset, u32 *strip) ++{ ++ u32 val = FIELD_PREP(SG2044_EFUSE_ADR_ADDR, offset); ++ int ret; ++ ++ guard(mutex)(&efuse->mutex); ++ ++ writel(val, efuse->base + SG2044_EFUSE_ADR); ++ ++ ret = sg2044_efuse_set_mode(efuse, SG2044_EFUSE_MODE_READ); ++ if (ret < 0) ++ return ret; ++ ++ *strip = readl(efuse->base + SG2044_EFUSE_RD_DATA); ++ ++ return 0; ++} ++ ++static int sg2044_efuses_read(void *context, unsigned int offset, void *val, ++ size_t bytes) ++{ ++ struct sophgo_efuses *efuse = context; ++ unsigned int start, start_offset, end, i; ++ u32 value; ++ u8 *buf; ++ int ret; ++ ++ start = rounddown(offset, SG2044_EFUSE_ALIGN); ++ end = roundup(offset + bytes, SG2044_EFUSE_ALIGN); ++ start_offset = offset - start; ++ ++ start /= SG2044_EFUSE_ALIGN; ++ end /= SG2044_EFUSE_ALIGN; ++ ++ ret = readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, ++ (value & SG2044_EFUSE_BOOT_DONE), ++ 1, SG2044_BOOT_TIMEOUT); ++ if (ret < 0) ++ return ret; ++ ++ buf = kzalloc(end - start, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ for (i = start; i < end; i++) { ++ ret = sg2044_efuses_read_strip(efuse, i, &value); ++ if (ret) ++ goto failed; ++ ++ memcpy(&buf[(i - start) * 4], &value, SG2044_EFUSE_ALIGN); ++ } ++ ++ memcpy(val, buf + start_offset, bytes); ++ ++failed: ++ kfree(buf); ++ ++ return ret; ++} ++ ++static int sophgo_efuses_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct sophgo_efuses *efuse; ++ struct nvmem_config config = { ++ .dev = &pdev->dev, ++ .add_legacy_fixed_of_cells = true, ++ .read_only = true, ++ .reg_read = sg2044_efuses_read, ++ .stride = 1, ++ .word_size = 1, ++ .name = "sophgo-efuse", ++ .id = NVMEM_DEVID_AUTO, ++ .root_only = true, ++ }; ++ ++ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); ++ if (!efuse) ++ return -ENOMEM; ++ ++ efuse->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(efuse->base)) ++ return PTR_ERR(efuse->base); ++ ++ efuse->num_clks = devm_clk_bulk_get_all_enabled(&pdev->dev, &efuse->clks); ++ if (efuse->num_clks < 0) ++ return dev_err_probe(dev, efuse->num_clks, "failed to get clocks\n"); ++ ++ config.priv = efuse; ++ config.size = SG2044_EFUSE_CONTENT_SIZE; ++ ++ return PTR_ERR_OR_ZERO(devm_nvmem_register(config.dev, &config)); ++} ++ ++static const struct of_device_id sophgo_efuses_of_match[] = { ++ { .compatible = "sophgo,sg2044-efuse", }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, sophgo_efuses_of_match); ++ ++static struct platform_driver sophgo_efuses_driver = { ++ .driver = { ++ .name = "sophgo_efuse", ++ .of_match_table = sophgo_efuses_of_match, ++ }, ++ .probe = sophgo_efuses_probe, ++}; ++ ++module_platform_driver(sophgo_efuses_driver); ++ ++MODULE_AUTHOR("Inochi Amaoto "); ++MODULE_DESCRIPTION("Sophgo efuse driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0443-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch b/SPECS/linux-lts-kmhv2/0443-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch deleted file mode 100644 index 86078006ad..0000000000 --- a/SPECS/linux-lts-kmhv2/0443-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch +++ /dev/null @@ -1,27 +0,0 @@ -From f541fa0b3dbdffb41fa000bff4a473af0b9f662b Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Fri, 24 Oct 2025 17:00:37 +0800 -Subject: [PATCH 443/467] REVYSR: net: stmmac: add support for dwmac 5.10a - -Signed-off-by: Han Gao -FROM: https://github.com/RevySR/linux/commit/5bc2d2af06ccd13675b8d4751226fb56bc8ee6df -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -index b9218c07eb6b..a27b2bc177af 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -@@ -59,6 +59,7 @@ static const struct of_device_id dwmac_generic_match[] = { - { .compatible = "snps,dwmac-3.72a"}, - { .compatible = "snps,dwmac-4.00"}, - { .compatible = "snps,dwmac-4.10a"}, -+ { .compatible = "snps,dwmac-5.10a"}, - { .compatible = "snps,dwmac"}, - { .compatible = "snps,dwxgmac-2.10"}, - { .compatible = "snps,dwxgmac"}, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch b/SPECS/linux-lts-kmhv2/0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch new file mode 100644 index 0000000000..ca1a921e5d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch @@ -0,0 +1,54 @@ +From 973bb367e07f78196b1e441326cbdef6c366955f Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 5 Dec 2024 13:24:13 +0800 +Subject: [RUYI PATCH] SOPHGO: riscv: dts: sophgo: sg2044: Add eFUSE device + +Add eFUSE controller node for SG2044. + +Signed-off-by: Inochi Amaoto +--- + arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ + arch/riscv/boot/dts/sophgo/sg2044.dtsi | 12 ++++++++++++ + 2 files changed, 16 insertions(+) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +index fed3d9a384a0..1b506972d465 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts ++++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +@@ -36,6 +36,10 @@ &emmc { + status = "okay"; + }; + ++&efuse0 { ++ status = "okay"; ++}; ++ + &gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; +diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +index 320c4d1d08e6..9577aae08f7f 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +@@ -408,6 +408,18 @@ sd: mmc@703000b000 { + status = "disabled"; + }; + ++ efuse0: efuse@7040000000 { ++ compatible = "sophgo,sg2044-efuse"; ++ reg = <0x70 0x40000000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&clk CLK_GATE_EFUSE>, ++ <&clk CLK_GATE_APB_EFUSE>; ++ clock-names = "core", "apb"; ++ resets = <&rst RST_EFUSE0>; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@7040005000 { + compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; + reg = <0x70 0x40005000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0444-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch b/SPECS/linux-lts-kmhv2/0444-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch deleted file mode 100644 index e1c1a55eec..0000000000 --- a/SPECS/linux-lts-kmhv2/0444-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch +++ /dev/null @@ -1,579 +0,0 @@ -From b77880a0dbc2004c552fb776369d9ee9c2e82477 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Fri, 16 May 2025 11:12:26 +0800 -Subject: [PATCH 444/467] RVCK: riscv:dts: add dp1000.dts for UltraRIsc DP1000 - SoC - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/8fa6586e8607e8f2b9bbf701a6cf282b29dac1f7 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/Makefile | 1 + - arch/riscv/boot/dts/ultrarisc/Makefile | 2 + - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 536 +++++++++++++++++++++++ - 3 files changed, 539 insertions(+) - create mode 100644 arch/riscv/boot/dts/ultrarisc/Makefile - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000.dts - -diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile -index 3763d199c70a..297b30243037 100644 ---- a/arch/riscv/boot/dts/Makefile -+++ b/arch/riscv/boot/dts/Makefile -@@ -10,3 +10,4 @@ subdir-y += sophgo - subdir-y += spacemit - subdir-y += starfive - subdir-y += thead -+subdir-y += ultrarisc -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -new file mode 100644 -index 000000000000..c27f490e2b99 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+dtb-y += dp1000.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -new file mode 100644 -index 000000000000..3eb811f73aa8 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -0,0 +1,536 @@ -+/* -+* SPDX-License-Identifier: GPL-2.0+ -+* -+* Copyright (c) 2019-2022 UltraRisc,Inc -+* -+*/ -+ -+/dts-v1/; -+ -+/ { -+ #address-cells = <0x02>; -+ #size-cells = <0x02>; -+ compatible = "ultrarisc,dp1000"; -+ model = "ultrarisc,dp1000"; -+ -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS1,115200"; -+ stdout-path = &uart1; -+ }; -+ -+ cpus { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ timebase-frequency = <10000000>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ reg = <0x00>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu0_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ reg = <0x1>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu1_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ reg = <0x2>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu2_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ reg = <0x3>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu3_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu4: cpu@4 { -+ device_type = "cpu"; -+ reg = <0x10>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu4_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu5: cpu@5 { -+ device_type = "cpu"; -+ reg = <0x11>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu5_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu6: cpu@6 { -+ device_type = "cpu"; -+ reg = <0x12>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ -+ clock-frequency = <2000000000>; -+ -+ cpu6_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu7: cpu@7 { -+ device_type = "cpu"; -+ reg = <0x13>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu7_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00 0x80000000 0x4 0x00000000>; -+ }; -+ -+ soc { -+ #address-cells = <0x02>; -+ #size-cells = <0x02>; -+ compatible = "simple-bus"; -+ ranges; -+ -+ clocks { -+ compatible = "simple-bus"; -+ u-boot,dm-pre-reloc; -+ device_clk: device_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <62500000>; -+ #clock-cells = <0>; -+ }; -+ csr_clk: csr_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <250000000>; -+ #clock-cells = <0>; -+ }; -+ }; -+ -+ clint: clint@8000000 { -+ compatible = "riscv,clint0"; -+ interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, -+ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -+ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -+ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -+ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -+ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -+ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -+ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; -+ reg = <0x00 0x8000000 0x00 0x100000>; -+ }; -+ -+ plic: plic@9000000 { -+ #interrupt-cells = <1>; -+ #address-cells = <0>; -+ phandle = <0x01>; -+ compatible = "ultrarisc,dp1000-plic"; -+ interrupt-controller; -+ interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, -+ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -+ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -+ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -+ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -+ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -+ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -+ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; -+ reg = <0x00 0x9000000 0x00 0x4000000>; -+ riscv,max-priority = <0x07>; -+ riscv,ndev = <160>; -+ }; -+ -+ uart0: serial@20300000 { -+ interrupt-parent = <0x01>; -+ interrupts = <17>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20300000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart1: serial@20310000 { -+ interrupt-parent = <0x01>; -+ interrupts = <18>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20310000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart2: serial@20400000 { -+ interrupt-parent = <0x01>; -+ interrupts = <25>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20400000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart3: serial@20410000 { -+ interrupt-parent = <0x01>; -+ interrupts = <26>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20410000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ spi0: spi@20320000 { -+ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ status = "okay"; -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ reg = <0x0 0x20320000 0x0 0x1000>; -+ interrupt-parent = <0x01>; -+ interrupts = <19>; -+ clocks = <&device_clk>; -+ clock-names = "device_clk"; -+ num-cs = <3>; -+ spi-max-frequency = <62500000>; -+ mmc0: mmc@0 { -+ compatible = "mmc-spi-slot"; -+ spi-max-frequency = <15625000>; -+ reg = <0x00>; -+ voltage-ranges = <3300 3300>; -+ disable-wp; -+ }; -+ }; -+ -+ spi1: spi@20420000 { -+ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ status = "okay"; -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ reg = <0x0 0x20420000 0x0 0x1000>; -+ interrupt-parent = <0x01>; -+ interrupts = <27>; -+ clocks = <&device_clk>; -+ clock-names = "device_clk"; -+ num-cs = <3>; -+ spi-max-frequency = <62500000>; -+ }; -+ -+ i2c0: i2c@20330000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20330000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <20>; -+ }; -+ -+ i2c1: i2c@20340000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20340000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <21>; -+ }; -+ -+ i2c2: i2c@20430000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20430000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <28>; -+ }; -+ -+ i2c3: i2c@20440000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20440000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <29>; -+ }; -+ -+ wdt0: watchdog@20210000 { -+ compatible = "snps,dw-wdt"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20210000 0x0 0x100>; -+ interrupt-parent = <0x01>; -+ interrupts = <33>; -+ clocks = <&device_clk>; -+ }; -+ -+ timer0: timer@20220000 { -+ compatible = "snps,dw-apb-timer"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20220000 0x0 0x100>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <35>; -+ status = "okay"; -+ }; -+ -+ timer1: timer@20230000 { -+ compatible = "snps,dw-apb-timer"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20230000 0x0 0x100>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <36>; -+ status = "okay"; -+ }; -+ -+ gpio: gpio@20200000 { -+ compatible = "snps,dw-apb-gpio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20200000 0x0 0x1000>; -+ clocks = <&csr_clk>, <&device_clk>; -+ clock-names = "bus", "db"; -+ status = "okay"; -+ -+ porta: gpio-port@0 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <0>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <16>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ interrupt-parent = <0x01>; -+ interrupts = <34>; -+ }; -+ -+ portb: gpio-port@1 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <1>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ -+ portc: gpio-port@2 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <2>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ -+ portd: gpio-port@3 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <3>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ }; -+ -+ ethernet1@38000000 { -+ clocks = <&csr_clk>; -+ clock-names = "stmmaceth"; -+ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; -+ interrupt-parent = <0x01>; -+ interrupts = <84>; -+ interrupt-names = "macirq"; -+ reg = <0x00 0x38000000 0x00 0x1000000>; -+ local-mac-address = [ff ff ff ff ff ff]; -+ phy-mode = "rgmii"; -+ max-speed = <1000>; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ phy-handle = <&phy0>; -+ mdio { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ compatible = "snps,dwmac-mdio"; -+ phy0: phy@0{ -+ phandle = <0x04>; -+ reg = <0x00>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ dmac: dma-controller@39000000 { -+ compatible = "snps,axi-dma-1.01a"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x39000000 0x0 0x400>; -+ clocks = <&device_clk>, <&device_clk>; -+ clock-names = "core-clk", "cfgr-clk"; -+ interrupt-parent = <0x01>; -+ interrupts = <152>; -+ #dma-cells = <1>; -+ dma-channels = <8>; -+ snps,dma-masters = <1>; -+ snps,data-width = <4>; -+ snps,block-size = <512 512 512 512 512 512 512 512>; -+ snps,priority = <0 1 2 3 4 5 6 7>; -+ snps,axi-max-burst-len = <256>; -+ }; -+ -+ pcie_x16: pcie@21000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x21000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x4fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <16>; -+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <43>, <44>, <45>, <46>, <47>, <48>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, -+ <0x0 0x0 0x0 0x2 &plic 45>, -+ <0x0 0x0 0x0 0x3 &plic 46>, -+ <0x0 0x0 0x0 0x4 &plic 47>; -+ }; -+ -+ pcie_x4a: pcie@23000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x23000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x6fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <4>; -+ ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <63>, <64>, <65>, <66>, <67>, <68>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, -+ <0x0 0x0 0x0 0x2 &plic 65>, -+ <0x0 0x0 0x0 0x3 &plic 66>, -+ <0x0 0x0 0x0 0x4 &plic 67>; -+ }; -+ -+ pcie_x4b: pcie@24000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x24000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x7fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <4>; -+ ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <73>, <74>, <75>, <76>, <77>, <78>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, -+ <0x0 0x0 0x0 0x2 &plic 75>, -+ <0x0 0x0 0x0 0x3 &plic 76>, -+ <0x0 0x0 0x0 0x4 &plic 77>; -+ }; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch b/SPECS/linux-lts-kmhv2/0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch new file mode 100644 index 0000000000..7551151403 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch @@ -0,0 +1,102 @@ +From e2ed9e487c648247b91a25cef6515dc2a54aba85 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Sun, 28 Dec 2025 23:02:15 +0800 +Subject: [RUYI PATCH] SOPHGO: dts: sg2044: Modify pcie bar address + +FROM: https://github.com/sophgo/linux-riscv/commit/efddc3e2d3d57b27054415afb522100e6dce8692 + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2044.dtsi | 28 +++++++++++++------------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +index 9577aae08f7f..f1377ee8e149 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +@@ -36,7 +36,7 @@ pcie0: pcie@6c00000000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x00000000 0x0 0x00001000>, + <0x6c 0x00300000 0x0 0x00004000>, +- <0x48 0x00000000 0x0 0x00001000>, ++ <0x50 0x00000000 0x0 0x00001000>, + <0x6c 0x000c0000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -51,11 +51,11 @@ pcie0: pcie@6c00000000 { + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, + <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, +- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, +- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x54 0x00000000 0x54 0x00000000 0x4 0x00000000>, ++ <0x03000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>; + status = "disabled"; + + pcie_intc0: interrupt-controller { +@@ -89,8 +89,8 @@ pcie1: pcie@6c00400000 { + ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>, + <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>, +- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, +- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x44 0x00000000 0x44 0x00000000 0x4 0x00000000>, ++ <0x03000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>; + status = "disabled"; + + pcie_intc1: interrupt-controller { +@@ -106,7 +106,7 @@ pcie2: pcie@6c04000000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x04000000 0x0 0x00001000>, + <0x6c 0x04300000 0x0 0x00004000>, +- <0x58 0x00000000 0x0 0x00001000>, ++ <0x7c 0x00000000 0x0 0x00001000>, + <0x6c 0x040c0000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -121,11 +121,11 @@ pcie2: pcie@6c04000000 { + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x7c 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>, + <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>, +- <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>, +- <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x7d 0x00000000 0x7d 0x00000000 0x1 0x00000000>, ++ <0x03000000 0x7c 0x80000000 0x7c 0x80000000 0x0 0x80000000>; + status = "disabled"; + + pcie_intc2: interrupt-controller { +@@ -141,7 +141,7 @@ pcie3: pcie@6c04400000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x04400000 0x0 0x00001000>, + <0x6c 0x04700000 0x0 0x00004000>, +- <0x50 0x00000000 0x0 0x00001000>, ++ <0x78 0x00000000 0x0 0x00001000>, + <0x6c 0x04780000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -156,11 +156,11 @@ pcie3: pcie@6c04400000 { + <0 0 0 3 &pcie_intc3 2>, + <0 0 0 4 &pcie_intc3 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x78 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>, + <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>, +- <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>, +- <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x79 0x00000000 0x79 0x00000000 0x1 0x00000000>, ++ <0x03000000 0x78 0x80000000 0x78 0x80000000 0x0 0x80000000>; + status = "disabled"; + + pcie_intc3: interrupt-controller { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0445-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch b/SPECS/linux-lts-kmhv2/0445-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch deleted file mode 100644 index 2a78270fd1..0000000000 --- a/SPECS/linux-lts-kmhv2/0445-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch +++ /dev/null @@ -1,881 +0,0 @@ -From 29f4764a9f5c2daf1ba382864a626abb65b50d8f Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Fri, 17 Jan 2025 19:34:48 +0800 -Subject: [PATCH 445/467] RVCK: pinctrl: add pinctrl dirver for UltraRisc - DP1000 - -support pinmux and pinconf for UltraRisc DP1000 SoC - -Signed-off-by: Jia Wang -Signed-off-by: Yanteng Si -FROM: https://github.com/RVCK-Project/rvck/commit/2fdd7d95fb0408b67353ea82e378773ebfe39ade -Signed-off-by: Han Gao ---- - drivers/pinctrl/Kconfig | 1 + - drivers/pinctrl/Makefile | 1 + - drivers/pinctrl/ultrarisc/Kconfig | 20 + - drivers/pinctrl/ultrarisc/Makefile | 4 + - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 122 +++++ - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 503 ++++++++++++++++++ - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 78 +++ - .../dt-bindings/pinctrl/ur-dp1000-pinctrl.h | 65 +++ - 8 files changed, 794 insertions(+) - create mode 100644 drivers/pinctrl/ultrarisc/Kconfig - create mode 100644 drivers/pinctrl/ultrarisc/Makefile - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h - create mode 100644 include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h - -diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig -index 4f8507ebbdac..b4ba4fb72f10 100644 ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -712,5 +712,6 @@ source "drivers/pinctrl/ti/Kconfig" - source "drivers/pinctrl/uniphier/Kconfig" - source "drivers/pinctrl/visconti/Kconfig" - source "drivers/pinctrl/vt8500/Kconfig" -+source "drivers/pinctrl/ultrarisc/Kconfig" - - endif -diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile -index e0cfb9b7c99b..32f0d988e505 100644 ---- a/drivers/pinctrl/Makefile -+++ b/drivers/pinctrl/Makefile -@@ -95,3 +95,4 @@ obj-y += ti/ - obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ - obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ - obj-$(CONFIG_ARCH_VT8500) += vt8500/ -+obj-$(CONFIG_ARCH_ULTRARISC) += ultrarisc/ -diff --git a/drivers/pinctrl/ultrarisc/Kconfig b/drivers/pinctrl/ultrarisc/Kconfig -new file mode 100644 -index 000000000000..e4db80843bea ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/Kconfig -@@ -0,0 +1,20 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config PINCTRL_ULTRARISC -+ bool -+ depends on OF -+ select PINMUX -+ select GENERIC_PINCTRL_GROUPS -+ select GENERIC_PINCONF -+ select GENERIC_PINMUX_FUNCTIONS -+ select GPIOLIB -+ select IRQ_DOMAIN_HIERARCHY -+ select MFD_SYSCON -+ -+config PINCTRL_ULTRARISC_DP1000 -+ tristate "Pinctrl driver of UltraRisc DP1000" -+ select PINCTRL_ULTRARISC -+ depends on OF && HAS_IOMEM -+ help -+ This driver configures the UltraRisc DP1000 SoC's pinctrl -+ subsystem. -diff --git a/drivers/pinctrl/ultrarisc/Makefile b/drivers/pinctrl/ultrarisc/Makefile -new file mode 100644 -index 000000000000..5bf3f449d59b ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+obj-$(CONFIG_PINCTRL_ULTRARISC) += pinctrl-ultrarisc.o -+obj-$(CONFIG_PINCTRL_ULTRARISC_DP1000) += pinctrl-ultrarisc-dp1000.o -\ No newline at end of file -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -new file mode 100644 -index 000000000000..217f671fe63a ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -0,0 +1,122 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc DP1000 pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../pinctrl-utils.h" -+#include "../pinmux.h" -+#include "../core.h" -+#include "../devicetree.h" -+ -+#include "pinctrl-ultrarisc.h" -+ -+static const struct pinctrl_pin_desc ur_dp1000_pins[] = { -+ // PA -+ PINCTRL_PIN(0, "PA0"), -+ PINCTRL_PIN(1, "PA1"), -+ PINCTRL_PIN(2, "PA2"), -+ PINCTRL_PIN(3, "PA3"), -+ PINCTRL_PIN(4, "PA4"), -+ PINCTRL_PIN(5, "PA5"), -+ PINCTRL_PIN(6, "PA6"), -+ PINCTRL_PIN(7, "PA7"), -+ PINCTRL_PIN(8, "PA8"), -+ PINCTRL_PIN(9, "PA9"), -+ PINCTRL_PIN(10, "PA10"), -+ PINCTRL_PIN(11, "PA11"), -+ PINCTRL_PIN(12, "PA12"), -+ PINCTRL_PIN(13, "PA13"), -+ PINCTRL_PIN(14, "PA14"), -+ PINCTRL_PIN(15, "PA15"), -+ // PB -+ PINCTRL_PIN(16, "PB0"), -+ PINCTRL_PIN(17, "PB1"), -+ PINCTRL_PIN(18, "PB2"), -+ PINCTRL_PIN(19, "PB3"), -+ PINCTRL_PIN(20, "PB4"), -+ PINCTRL_PIN(21, "PB5"), -+ PINCTRL_PIN(22, "PB6"), -+ PINCTRL_PIN(23, "PB7"), -+ // PC -+ PINCTRL_PIN(24, "PC0"), -+ PINCTRL_PIN(25, "PC1"), -+ PINCTRL_PIN(26, "PC2"), -+ PINCTRL_PIN(27, "PC3"), -+ PINCTRL_PIN(28, "PC4"), -+ PINCTRL_PIN(29, "PC5"), -+ PINCTRL_PIN(30, "PC6"), -+ PINCTRL_PIN(31, "PC7"), -+ // PD -+ PINCTRL_PIN(32, "PD0"), -+ PINCTRL_PIN(33, "PD1"), -+ PINCTRL_PIN(34, "PD2"), -+ PINCTRL_PIN(35, "PD3"), -+ PINCTRL_PIN(36, "PD4"), -+ PINCTRL_PIN(37, "PD5"), -+ PINCTRL_PIN(38, "PD6"), -+ PINCTRL_PIN(39, "PD7"), -+ // LPC -+ PINCTRL_PIN(40, "LPC0"), -+ PINCTRL_PIN(41, "LPC1"), -+ PINCTRL_PIN(42, "LPC2"), -+ PINCTRL_PIN(43, "LPC3"), -+ PINCTRL_PIN(44, "LPC4"), -+ PINCTRL_PIN(45, "LPC5"), -+ PINCTRL_PIN(46, "LPC6"), -+ PINCTRL_PIN(47, "LPC7"), -+ PINCTRL_PIN(48, "LPC8"), -+ PINCTRL_PIN(49, "LPC9"), -+ PINCTRL_PIN(50, "LPC10"), -+ PINCTRL_PIN(51, "LPC11"), -+ PINCTRL_PIN(52, "LPC12"), -+}; -+ -+static struct ur_pinctrl_match_data ur_dp1000_match_data = { -+ .pins = ur_dp1000_pins, -+ .npins = ARRAY_SIZE(ur_dp1000_pins), -+ .offset = 0x2c0, -+ .ports = { -+ {"A", 16, 0x2c0, 0x310}, -+ {"B", 8, 0x2c4, 0x318}, -+ {"C", 8, 0x2c8, 0x31c}, -+ {"D", 8, 0x2cc, 0x320}, -+ {"LPC", 13, 0x2d0, 0x324}, -+ }, -+}; -+ -+enum ur_dp1000_port_list { -+ PORT_A = 0, -+ PORT_B, -+ PORT_C, -+ PORT_D, -+ PORT_LPC -+}; -+ -+ -+static const struct of_device_id ur_pinctrl_of_match[] = { -+ { .compatible = "ultrarisc,dp1000-pinctrl", .data = &ur_dp1000_match_data, }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, ur_pinctrl_of_match); -+ -+static struct platform_driver ur_pinctrl_driver = { -+ .driver = { -+ .name = "ultrarisc-pinctrl-dp1000", -+ .of_match_table = ur_pinctrl_of_match, -+ }, -+ .probe = ur_pinctrl_probe, -+ .remove = ur_pinctrl_remove, -+}; -+ -+module_platform_driver(ur_pinctrl_driver); -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -new file mode 100644 -index 000000000000..667d59e0ac6e ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -0,0 +1,503 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../pinctrl-utils.h" -+#include "../pinmux.h" -+#include "../core.h" -+#include "../devicetree.h" -+ -+#include "pinctrl-ultrarisc.h" -+ -+static int ur_pin_to_desc(struct pinctrl_dev *pctldev, struct ur_pin_val *pin_val) -+{ -+ int index = 0; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ const struct ur_pinctrl_match_data *ur_match_data = ur_pinctrl->match_data; -+ -+ for (int i = 0; i < pin_val->port; i++) -+ index += ur_match_data->ports[i].npins; -+ index += pin_val->pin; -+ dev_dbg(pctldev->dev, "port %d pin %d index %d\n", pin_val->port, pin_val->pin, index); -+ return index; -+} -+ -+static int ur_subnode_to_pin(struct pinctrl_dev *pctldev, -+ const char *name, -+ enum pinctrl_map_type type, -+ struct device_node *np, -+ int **pins, -+ struct ur_pin_val **pin_val, -+ int *pin_num) -+{ -+ struct ur_pin_val *pin_vals; -+ int rows; -+ int ret = -EINVAL; -+ int *group_pins; -+ const char **pgnames; -+ -+ dev_dbg(pctldev->dev, "pinctrl node %s\n", np->name); -+ rows = pinctrl_count_index_with_args(np, name); -+ if (rows < 0) { -+ dev_err(pctldev->dev, "%s count is invalid %d\n", name, rows); -+ return rows; -+ } -+ -+ pin_vals = devm_kcalloc(pctldev->dev, rows, sizeof(*pin_vals), GFP_KERNEL); -+ if (!pin_vals) { -+ return -ENOMEM; -+ } -+ -+ group_pins = devm_kcalloc(pctldev->dev, rows, sizeof(*group_pins), GFP_KERNEL); -+ if (!group_pins) { -+ ret = -ENOMEM; -+ goto free_pin_vals; -+ } -+ -+ pgnames = devm_kzalloc(pctldev->dev, sizeof(*pgnames), GFP_KERNEL); -+ if (!pgnames) { -+ ret = -ENOMEM; -+ goto free_pins; -+ } -+ -+ for (int i = 0; i < rows; i++) { -+ struct of_phandle_args pin_args; -+ -+ ret = pinctrl_parse_index_with_args(np, name, i, &pin_args); -+ if (ret) { -+ dev_err(pctldev->dev, "parse args of %s index %d failed\n", name, i); -+ goto free_pgnames; -+ } -+ -+ if (pin_args.args_count < 3) { -+ dev_err(pctldev->dev, "invalid args_count(%d) of %s index %d/%d\n", -+ pin_args.args_count, name, i, rows); -+ ret = -EINVAL; -+ goto free_pgnames; -+ } -+ pin_vals[i].port = pin_args.args[0]; -+ pin_vals[i].pin = pin_args.args[1]; -+ pin_vals[i].mode = pin_args.args[2]; -+ -+ dev_dbg(pctldev->dev, "found a pinctrl: port=%d pin=%d val=0x%x\n", -+ pin_vals[i].port, pin_vals[i].pin, pin_vals[i].mode); -+ -+ group_pins[i] = ur_pin_to_desc(pctldev, &pin_vals[i]); -+ } -+ -+ dev_dbg(pctldev->dev, "get an pinmux of %s\n", np->name); -+ -+ ret = pinctrl_generic_add_group(pctldev, np->name, group_pins, rows, pin_vals); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "add group %s failed\n", np->name); -+ goto free_pgnames; -+ } -+ -+ *pgnames = np->name; -+ ret = pinmux_generic_add_function(pctldev, np->name, pgnames, 1, NULL); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "add function %s failed\n", np->name); -+ goto free_group; -+ } -+ -+ dev_dbg(pctldev->dev, "add group and function of %s\n", np->name); -+ -+ *pins = group_pins; -+ *pin_val = pin_vals; -+ *pin_num = rows; -+ -+ return 0; -+ -+free_group: -+ pinctrl_generic_remove_group(pctldev, ret); -+free_pgnames: -+ devm_kfree(pctldev->dev, pgnames); -+free_pins: -+ devm_kfree(pctldev->dev, group_pins); -+free_pin_vals: -+ devm_kfree(pctldev->dev, pin_vals); -+ return ret; -+} -+ -+static int ur_pinmux_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map *map) -+{ -+ int ret; -+ int *pins; -+ struct ur_pin_val *pin_vals; -+ int pin_num; -+ -+ ret = ur_subnode_to_pin(pctldev, PINMUX_PROP_NAME, PIN_MAP_TYPE_MUX_GROUP, -+ np, &pins, &pin_vals, &pin_num); -+ if (ret) { -+ dev_err(pctldev->dev, "get pinmux data %s failed\n", np->name); -+ return ret; -+ } -+ -+ map->type = PIN_MAP_TYPE_MUX_GROUP; -+ map->data.mux.group = np->name; -+ map->data.mux.function = np->name; -+ -+ dev_dbg(pctldev->dev, "type=%d, mux.group=%s, mux.function=%s\n", -+ map->type, map->data.mux.group, map->data.mux.function); -+ -+ return 0; -+} -+ -+static int ur_pinconf_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map *map) -+{ -+ int ret; -+ int *pins; -+ struct ur_pin_val *pin; -+ int pin_num; -+ -+ ret = ur_subnode_to_pin(pctldev, PINCONF_PROP_NAME, PIN_MAP_TYPE_CONFIGS_GROUP, -+ np, &pins, &pin, &pin_num); -+ if (ret) { -+ dev_err(pctldev->dev, "get pinconf data %s failed\n", np->name); -+ return ret; -+ } -+ -+ dev_dbg(pctldev->dev, "get an pinconf of %s\n", np->name); -+ map->type = PIN_MAP_TYPE_CONFIGS_GROUP; -+ map->data.configs.group_or_pin = np->name; -+ map->data.configs.configs = (unsigned long *)pin; -+ map->data.configs.num_configs = pin_num; -+ -+ dev_dbg(pctldev->dev, "type=%d, config.group_or_pin=%s, configs.num_config=%d\n", -+ map->type, map->data.configs.group_or_pin, map->data.configs.num_configs); -+ -+ return 0; -+} -+ -+static int ur_dt_node_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map **map, -+ unsigned int *num_maps) -+{ -+ int ret; -+ bool mux_present = false, conf_present = false; -+ struct pinctrl_map *new_map; -+ unsigned int map_num = 0, prop_count = 0; -+ -+ //device_get_named_child_node(pctldev->dev, np->name); -+ if (of_property_present(np, PINMUX_PROP_NAME)) { -+ mux_present = true; -+ prop_count++; -+ } -+ if (of_property_present(np, PINCONF_PROP_NAME)) { -+ conf_present = true; -+ prop_count++; -+ } -+ -+ if (!prop_count) { -+ dev_err(pctldev->dev, "no pinctrl node(%d) in %s\n", prop_count, np->name); -+ return -EINVAL; -+ } -+ -+ new_map = devm_kmalloc_array(pctldev->dev, prop_count, sizeof(**map), GFP_KERNEL); -+ if (!new_map) -+ return -ENOMEM; -+ -+ *map = new_map; -+ if (mux_present) { -+ ret = ur_pinmux_to_map(pctldev, np, new_map); -+ if (!ret) { -+ new_map++; -+ map_num++; -+ } -+ } -+ if (conf_present) { -+ ret = ur_pinconf_to_map(pctldev, np, new_map); -+ if (!ret) -+ map_num++; -+ } -+ -+ if (!map_num) { -+ dev_err(pctldev->dev, "no pinctrl info of %s failed\n", np->name); -+ goto free_map; -+ } -+ *num_maps = map_num; -+ -+ return 0; -+ -+free_map: -+ devm_kfree(pctldev->dev, new_map); -+ return ret; -+} -+ -+static void ur_dt_free_map(struct pinctrl_dev *pctldev, -+ struct pinctrl_map *map, unsigned int num_maps) -+{ -+ if (map) -+ devm_kfree(pctldev->dev, map); -+} -+ -+static void ur_pin_dbg_show(struct pinctrl_dev *pctldev, -+ struct seq_file *s, unsigned int offset) -+{ -+ seq_printf(s, "%s", dev_name(pctldev->dev)); -+} -+ -+static const struct pinctrl_ops ur_pinctrl_ops = { -+ .get_groups_count = pinctrl_generic_get_group_count, -+ .get_group_name = pinctrl_generic_get_group_name, -+ .get_group_pins = pinctrl_generic_get_group_pins, -+ .dt_node_to_map = ur_dt_node_to_map, -+ .dt_free_map = ur_dt_free_map, -+ .pin_dbg_show = ur_pin_dbg_show, -+}; -+ -+static int ur_set_pin_mux(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) -+{ -+ unsigned long flag; -+ //bool clear_mode = false; -+ void __iomem *reg; -+ u32 val; -+ const struct ur_port_desc *port; -+ -+ port = &pin_ctrl->match_data->ports[pin_vals->port]; -+ -+ reg = pin_ctrl->base + port->func_offset; -+ -+ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); -+ val = readl_relaxed(reg); -+ val &= ~((UR_FUNC0 | UR_FUNC1)<pin); -+ val |= (pin_vals->mode << pin_vals->pin); -+ writel_relaxed(val, reg); -+ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); -+ -+ return 0; -+} -+ -+static int ur_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, -+ unsigned int group_selector) -+{ -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ struct group_desc *ur_group; -+ struct ur_pin_val *pin_vals; -+ -+ dev_dbg(pctldev->dev, "set mux: func_selector=%d, group_selector=%d\n", -+ func_selector, group_selector); -+ ur_group = pinctrl_generic_get_group(pctldev, group_selector); -+ if (!ur_group) { -+ dev_err(pctldev->dev, "get group %d failed\n", group_selector); -+ return -EINVAL; -+ } -+ -+ dev_dbg(pctldev->dev, "get group %s, num_pins=%zu\n", ur_group->grp.name, ur_group->grp.npins); -+ pin_vals = ur_group->data; -+ if (!pin_vals) { -+ dev_err(pctldev->dev, "data of %s is invalid\n", ur_group->grp.name); -+ return -EINVAL; -+ } -+ -+ for (int i = 0; i < ur_group->grp.npins; i++) -+ ur_set_pin_mux(ur_pinctrl, &pin_vals[i]); -+ -+ return 0; -+} -+ -+static const struct pinmux_ops ur_pinmux_ops = { -+ .get_functions_count = pinmux_generic_get_function_count, -+ .get_function_name = pinmux_generic_get_function_name, -+ .get_function_groups = pinmux_generic_get_function_groups, -+ .set_mux = ur_set_mux, -+ .strict = true, -+}; -+ -+#define UR_CONF_BIT_PER_PIN (4) -+#define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) -+static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) -+{ -+ const struct ur_port_desc *port_desc; -+ unsigned long flag; -+ void __iomem *reg; -+ u32 val, conf; -+ -+ port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; -+ reg = pin_ctrl->base + port_desc->conf_offset; -+ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); -+ reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; -+ dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); -+ -+ conf = pin_vals->conf << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN); -+ dev_dbg(pin_ctrl->dev, "pinconf conf=0x%x\n", conf); -+ -+ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); -+ val = readl_relaxed(reg); -+ val &= ~(UR_BIAS_MASK << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN)); -+ val |= conf; -+ writel_relaxed(val, reg); -+ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); -+ dev_dbg(pin_ctrl->dev, "pinconf val=0x%x\n", val); -+ -+ return 0; -+} -+ -+static int ur_pin_config_get(struct pinctrl_dev *pctldev, -+ unsigned int pin, -+ unsigned long *config) -+{ -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d\n", __func__, __LINE__, pin); -+ // TODO: this is call by pinconf-generic -+ return -EOPNOTSUPP; -+} -+ -+static int ur_pin_config_set(struct pinctrl_dev *pctldev, -+ unsigned int pin, -+ unsigned long *configs, -+ unsigned int num_configs) -+{ -+ struct ur_pin_val *pin_conf; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", -+ __func__, __LINE__, pin, num_configs); -+ pin_conf = (struct ur_pin_val *)configs; -+ for (int i = 0; i < num_configs; i++) { -+ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -+ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ } -+ return 0; -+} -+ -+static int ur_pin_config_group_get(struct pinctrl_dev *pctldev, -+ unsigned selector, -+ unsigned long *config) -+{ -+ dev_dbg(pctldev->dev, "%s(%d): selector=%d, config=0x%lx\n", -+ __func__, __LINE__, selector, *config); -+ return -EOPNOTSUPP; -+} -+ -+static int ur_pin_config_group_set(struct pinctrl_dev *pctldev, -+ unsigned int selector, -+ unsigned long *configs, -+ unsigned int num_configs) -+{ -+ struct group_desc *ur_group; -+ struct ur_pin_val *pin_conf; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ -+ dev_dbg(pctldev->dev, "%s(%d): selector=%d, num_configs=%d\n", -+ __func__, __LINE__, selector, num_configs); -+ ur_group = pinctrl_generic_get_group(pctldev, selector); -+ if (!ur_group) { -+ dev_err(pctldev->dev, "Cannot get group by selector %d\n", selector); -+ return -EINVAL; -+ } -+ -+ dev_dbg(pctldev->dev, "get pinconf group %s\n", ur_group->grp.name); -+ pin_conf = (struct ur_pin_val *)configs; -+ for (int i = 0; i < num_configs; i++) { -+ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -+ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ } -+ return 0; -+} -+ -+static const struct pinconf_ops ur_pinconf_ops = { -+ .pin_config_get = ur_pin_config_get, -+ .pin_config_set = ur_pin_config_set, -+ .pin_config_group_get = ur_pin_config_group_get, -+ .pin_config_group_set = ur_pin_config_group_set, -+#ifdef CONFIG_GENERIC_PINCONF -+ .is_generic = true, -+#endif -+}; -+ -+int ur_pinctrl_probe(struct platform_device *pdev) -+{ -+ struct pinctrl_desc *ur_pinctrl_desc; -+ const struct ur_pinctrl_match_data *pins_data; -+ struct ur_pinctrl *ur_pinctrl; -+ int ret; -+ -+ pins_data = of_device_get_match_data(&pdev->dev); -+ if (!pins_data) -+ return -ENODEV; -+ -+ ur_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl_desc), GFP_KERNEL); -+ if (!ur_pinctrl_desc) { -+ dev_err(&pdev->dev, "pinctrl desc alloc failed\n"); -+ return -ENOMEM; -+ } -+ -+ ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); -+ if (!ur_pinctrl) { -+ dev_err(&pdev->dev, "pinctrl alloc failed\n"); -+ ret = -ENOMEM; -+ goto free_pinctrl_desc; -+ } -+ struct resource *res; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ dev_dbg(&pdev->dev, "iomem start=0x%llx\n", res->start); -+ ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(ur_pinctrl->base)) { -+ dev_err(&pdev->dev, "get ioremap resource failed\n"); -+ ret = -EINVAL; -+ goto free_pinctrl_desc; -+ } -+ dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); -+ ur_pinctrl_desc->name = dev_name(&pdev->dev); -+ ur_pinctrl_desc->owner = THIS_MODULE; -+ ur_pinctrl_desc->pins = pins_data->pins; -+ ur_pinctrl_desc->npins = pins_data->npins; -+ ur_pinctrl_desc->pctlops = &ur_pinctrl_ops; -+ ur_pinctrl_desc->pmxops = &ur_pinmux_ops; -+ ur_pinctrl_desc->confops = &ur_pinconf_ops; -+ -+ ur_pinctrl->dev = &pdev->dev; -+ ur_pinctrl->match_data = pins_data; -+ ur_pinctrl->pctl_desc = ur_pinctrl_desc; -+ raw_spin_lock_init(&ur_pinctrl->lock); -+ mutex_init(&ur_pinctrl->mutex); -+ -+ ret = devm_pinctrl_register_and_init(&pdev->dev, ur_pinctrl_desc, -+ ur_pinctrl, &ur_pinctrl->pctl_dev); -+ if (ret) { -+ dev_err(&pdev->dev, "pinctrl register failed\n"); -+ goto free_pinctrl; -+ } -+ -+ platform_set_drvdata(pdev, ur_pinctrl); -+ -+ return pinctrl_enable(ur_pinctrl->pctl_dev); -+ -+free_pinctrl: -+ devm_kfree(&pdev->dev, ur_pinctrl); -+free_pinctrl_desc: -+ devm_kfree(&pdev->dev, ur_pinctrl_desc); -+ return ret; -+} -+ -+ -+void ur_pinctrl_remove(struct platform_device *pdev) -+{ -+ struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); -+ -+ if (ur_pinctrl->pctl_dev) -+ devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); -+} -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -new file mode 100644 -index 000000000000..eec621bf8b05 ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -@@ -0,0 +1,78 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#ifndef __PINCTRL_ULTRARISC_H__ -+#define __PINCTRL_ULTRARISC_H__ -+ -+#include -+#include -+ -+#define PINMUX_PROP_NAME "pinctrl-pins" -+#define PINCONF_PROP_NAME "pinconf-pins" -+ -+struct ur_pin_conf { -+ u16 pull; -+ u16 drive; -+}; -+ -+struct ur_pin_val { -+ u32 port; -+ u32 pin; -+ union { -+ u32 mode; -+ u32 conf; -+ }; -+#define UR_FUNC_DEF 0 -+#define UR_FUNC0 1 -+#define UR_FUNC1 0x10000 -+ -+#define UR_BIAS_MASK 0x0000000F -+#define UR_PULL_MASK 0x0C -+#define UR_PULL_DIS 0 -+#define UR_PULL_UP 1 -+#define UR_PULL_DOWN 2 -+#define UR_DRIVE_MASK 0x03 -+}; -+ -+struct ur_port_desc { -+ char *name; -+ u32 npins; -+ u32 func_offset; -+ u32 conf_offset; -+}; -+ -+struct ur_pinctrl_match_data { -+ const struct pinctrl_pin_desc *pins; -+ u32 npins; -+ u32 offset; -+ //u32 conf_offset[]; -+ struct ur_port_desc ports[]; -+}; -+ -+ -+struct ur_pinctrl { -+ struct device *dev; -+ struct pinctrl_dev *pctl_dev; -+ struct pinctrl_desc *pctl_desc; -+ void __iomem *base; -+ unsigned int ngroups; -+ const char **grp_names; -+ unsigned int nbanks; -+ const struct ur_pinctrl_match_data *match_data; -+ struct regmap *regmap; -+ raw_spinlock_t lock; -+ struct mutex mutex; -+ struct pinctrl_pin_desc *pins; -+ u32 npins; -+ u32 pkg; -+}; -+ -+int ur_pinctrl_probe(struct platform_device *pdev); -+void ur_pinctrl_remove(struct platform_device *pdev); -+ -+#endif -diff --git a/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h -new file mode 100644 -index 000000000000..5bec446e2411 ---- /dev/null -+++ b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc DP1000 pinctrl header -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#ifndef __UR_DP1000_PINCTRL_H__ -+#define __UR_DP1000_PINCTRL_H__ -+ -+#define UR_DP1000_IOMUX_A 0x0 -+#define UR_DP1000_IOMUX_B 0x1 -+#define UR_DP1000_IOMUX_C 0x2 -+#define UR_DP1000_IOMUX_D 0x3 -+#define UR_DP1000_IOMUX_LPC 0x4 -+ -+#define UR_FUNC_DEF 0 -+#define UR_FUNC0 1 -+#define UR_FUNC1 0x10000 -+ -+/** -+ * port: 'A' 'B' 'C' -+ * Pin in the port -+ * pin: -+ * PA: 0 - 15 -+ * PB-PD: 0 - 7 -+ * func: -+ * UR_FUNC_DEF: default -+ * UR_FUNC0: func0 -+ * UR_FUNC1: func1 -+ */ -+#define UR_DP1000_IOPAD(port, pin, func) (port) (pin) (func) -+ -+/** -+ * Configure pull up/down resistor of the IO pin -+ * UR_PULL_DIS: disable pull-up and pull-down -+ * UR_PULL_UP: enable pull-up -+ * UR_PULL_DOWN: enable pull-down -+ */ -+#define UR_PULL_DIS 0 -+#define UR_PULL_UP 1 -+#define UR_PULL_DOWN 2 -+/** -+ * Configure drive strength of the IO pin -+ * UR_DRIVE_DEF: default value, reset value is 2 -+ * UR_DRIVE_0: 20mA -+ * UR_DRIVE_1: 27mA -+ * UR_DIRVE_2: 33mA -+ * UR_DRIVE_3: 40mA -+ */ -+#define UR_DRIVE_DEF 2 -+#define UR_DRIVE_0 0 -+#define UR_DRIVE_1 1 -+#define UR_DRIVE_2 2 -+#define UR_DRIVE_3 3 -+ -+/** -+ * Combine the pull-up/down resistor and drive strength -+ * pull: UR_PULL_DIS, UR_PULL_UP, UR_PULL_DOWN -+ * drive: UR_DRIVE_DEF, UR_DRIVE_0, UR_DRIVE_1, UR_DRIVE_2, UR_DRIVE_3 -+ */ -+#define UR_DP1000_BIAS(pull, drive) (((pull)<<2) + (drive)) -+ -+#endif --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch b/SPECS/linux-lts-kmhv2/0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch new file mode 100644 index 0000000000..8f80489e78 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch @@ -0,0 +1,30 @@ +From 90bc96384294bf251a26f5f518765309821b8cd2 Mon Sep 17 00:00:00 2001 +From: Xiaoguang Xing +Date: Mon, 22 Jan 2024 10:31:30 +0800 +Subject: [RUYI PATCH] SOPHGO: riscv: sg2042: errata: Replace thead cache clean + with flush + +FROM: https://github.com/sophgo/linux-riscv/commit/9f8fdd99aae6ae8f037ad9c80b968de7c4252a65 + +Signed-off-by: Xiaoguang Xing +Signed-off-by: Han Gao +--- + arch/riscv/errata/thead/errata.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c +index fbe46f2fa8fb..9be8c45f4531 100644 +--- a/arch/riscv/errata/thead/errata.c ++++ b/arch/riscv/errata/thead/errata.c +@@ -67,7 +67,7 @@ static bool errata_probe_mae(unsigned int stage, + * 0000000 11001 00000 000 00000 0001011 + */ + #define THEAD_INVAL_A0 ".long 0x02a5000b" +-#define THEAD_CLEAN_A0 ".long 0x0295000b" ++#define THEAD_CLEAN_A0 ".long 0x02b5000b" + #define THEAD_FLUSH_A0 ".long 0x02b5000b" + #define THEAD_SYNC_S ".long 0x0190000b" + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch b/SPECS/linux-lts-kmhv2/0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch new file mode 100644 index 0000000000..5ca806b352 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch @@ -0,0 +1,131 @@ +From 283120c06a7de7f2b98715726a766cbef2459707 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Fri, 24 Oct 2025 15:59:17 +0800 +Subject: [RUYI PATCH] REVYSR: dt-bindings: net: ultrarisc,dp1000-gmac: Add + support for Ultrarisc DP1000 GMAC + +The GMAC IP on DP1000 is a standard Synopsys DesignWare MAC +(version 5.10a). + +Add necessary compatible string for this device. + +Signed-off-by: Han Gao +Signed-off-by: Han Gao +FROM: https://github.com/RevySR/linux/commit/5eda7fb5c988909f44edab38678cd124a9a5b98f +Signed-off-by: Han Gao +--- + .../devicetree/bindings/net/snps,dwmac.yaml | 1 + + .../bindings/net/ultrarisc,dp1000-gmac.yaml | 89 +++++++++++++++++++ + 2 files changed, 90 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml + +diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +index eb36cb36a57a..a8a45b844335 100644 +--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml ++++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +@@ -113,6 +113,7 @@ properties: + - starfive,jh7110-dwmac + - tesla,fsd-ethqos + - thead,th1520-gmac ++ - ultrarisc,dp1000-gmac + + reg: + minItems: 1 +diff --git a/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml +new file mode 100644 +index 000000000000..ace5c4058cc9 +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml +@@ -0,0 +1,89 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/ultrarisc,dp1000-gmac.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Ultrarisc dp1000 glue layer ++ ++maintainers: ++ - Han Gao ++ ++select: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - ultrarisc,dp1000-gmac ++ required: ++ - compatible ++ ++properties: ++ compatible: ++ oneOf: ++ - items: ++ - const: ultrarisc,dp1000-gmac ++ - const: snps,dwmac-5.10a ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: GMAC main clock ++ - description: PTP clock ++ - description: TX clock ++ ++ clock-names: ++ items: ++ - const: stmmaceth ++ ++ dma-noncoherent: true ++ ++ interrupts: ++ maxItems: 1 ++ ++ interrupt-names: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - interrupts ++ - interrupt-names ++ ++allOf: ++ - $ref: snps,dwmac.yaml# ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ ++ ethernet1@38000000 { ++ clocks = <&csr_clk>; ++ clock-names = "stmmaceth"; ++ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; ++ interrupt-parent = <0x01>; ++ interrupts = <84>; ++ interrupt-names = "macirq"; ++ reg = <0x00 0x38000000 0x00 0x1000000>; ++ local-mac-address = [ff ff ff ff ff ff]; ++ phy-mode = "rgmii"; ++ max-speed = <1000>; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ phy-handle = <&phy0>; ++ mdio { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ compatible = "snps,dwmac-mdio"; ++ phy0: phy@0{ ++ reg = <0x00>; ++ status = "okay"; ++ }; ++ }; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0446-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch b/SPECS/linux-lts-kmhv2/0446-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch deleted file mode 100644 index 4e043bafce..0000000000 --- a/SPECS/linux-lts-kmhv2/0446-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch +++ /dev/null @@ -1,237 +0,0 @@ -From 182a5e8e69bcf91baec912e83b948dfda780e9e5 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 16 Jun 2025 10:25:31 +0800 -Subject: [PATCH 446/467] RVCK: dts: add pinctrl dtsi/dts for UltraRisc DP1000 - -The newly added dtsi/dts is used to describe the pinctrl -configuration of the UltraRisc DP1000-EVB mainboard. - -Do not involve functional changes. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/e00864f9706198f8b278551217c048a140cbe39f -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 2 +- - .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 141 ++++++++++++++++++ - .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 52 +++++++ - 3 files changed, 194 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index c27f490e2b99..ef70e28e0b65 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,2 +1,2 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-y += dp1000.dtb -+dtb-y += dp1000.dtb dp1000-evb-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -new file mode 100644 -index 000000000000..be898b6df6fb ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -0,0 +1,141 @@ -+#include -+ -+/ { -+ -+ soc { -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -new file mode 100644 -index 000000000000..5ec9a39e8c34 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -0,0 +1,52 @@ -+/* -+* SPDX-License-Identifier: GPL-2.0+ -+* -+* Copyright (c) 2019-2022 UltraRisc,Inc -+* -+*/ -+ -+#include "dp1000.dts" -+#include "dp1000-evb-pinctrl.dtsi" -+#include -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch b/SPECS/linux-lts-kmhv2/0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch new file mode 100644 index 0000000000..271d5db9ac --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch @@ -0,0 +1,27 @@ +From 10d617cd5ad42153be1aa390de90e0cdd8376340 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Fri, 24 Oct 2025 17:00:37 +0800 +Subject: [RUYI PATCH] REVYSR: net: stmmac: add support for dwmac 5.10a + +Signed-off-by: Han Gao +FROM: https://github.com/RevySR/linux/commit/5bc2d2af06ccd13675b8d4751226fb56bc8ee6df +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c +index b9218c07eb6b..a27b2bc177af 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c +@@ -59,6 +59,7 @@ static const struct of_device_id dwmac_generic_match[] = { + { .compatible = "snps,dwmac-3.72a"}, + { .compatible = "snps,dwmac-4.00"}, + { .compatible = "snps,dwmac-4.10a"}, ++ { .compatible = "snps,dwmac-5.10a"}, + { .compatible = "snps,dwmac"}, + { .compatible = "snps,dwxgmac-2.10"}, + { .compatible = "snps,dwxgmac"}, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0447-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch b/SPECS/linux-lts-kmhv2/0447-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch deleted file mode 100644 index c8897fb4ae..0000000000 --- a/SPECS/linux-lts-kmhv2/0447-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch +++ /dev/null @@ -1,251 +0,0 @@ -From 2faa790be1496587400ee51ba2cb7b112892e54d Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 4 Sep 2025 16:31:30 +0800 -Subject: [PATCH 447/467] RVCK: riscv: dp1000: dts: add the dts of UltraRISC - dp1000-mo-v1 board - -adds the necessary device tree files for the UltraRISC -dp1000-mo-v1 board. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/1186c972f5908717ab186cea67403c74ea03cde1 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 4 +- - .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 146 ++++++++++++++++++ - .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 60 +++++++ - 3 files changed, 209 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index ef70e28e0b65..9eac56549340 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,2 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-y += dp1000.dtb dp1000-evb-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -new file mode 100644 -index 000000000000..e82fcf2901ab ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -@@ -0,0 +1,146 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+ -+/ { -+ -+ soc { -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -new file mode 100644 -index 000000000000..a74714629566 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include "dp1000.dts" -+#include "dp1000-mo-pinctrl.dtsi" -+#include -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ -+ rtc@32 { -+ compatible = "whwave,sd3078"; -+ reg = <0x32>; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0448-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch b/SPECS/linux-lts-kmhv2/0448-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch deleted file mode 100644 index e3ebcd1989..0000000000 --- a/SPECS/linux-lts-kmhv2/0448-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch +++ /dev/null @@ -1,111 +0,0 @@ -From c88f25eebc30016da836312d9bdf40c93746a6ae Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 9 Sep 2025 15:45:52 +0800 -Subject: [PATCH 448/467] RVCK: riscv: dp1000: dts: Move mmc0 node from SoC to - board DTS - -The mmc0 node (mmc-spi-slot) is a board-level peripheral -specific to the UltraRISC DP1000 EVB V1.0, not part of the -base SoC. Move it from the SoC-level dp1000.dts to the -board-specific dp1000-evb-v1.dts to maintain proper device -tree hierarchy between SoC core and board-specific components. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/c719099661103786c877036840568c38f3d083a9 -Signed-off-by: Han Gao ---- - .../boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 9 +++++++-- - arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 16 +++++++++++----- - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 15 +++------------ - 3 files changed, 21 insertions(+), 19 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -index be898b6df6fb..e82fcf2901ab 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -1,3 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ - #include - - / { -@@ -63,8 +68,8 @@ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) - - uart0_pins: uart0_pins { - pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) - >; - - pinconf-pins = < -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 5ec9a39e8c34..34622a33e63b 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -1,9 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0 - /* --* SPDX-License-Identifier: GPL-2.0+ --* --* Copyright (c) 2019-2022 UltraRisc,Inc --* --*/ -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ - - #include "dp1000.dts" - #include "dp1000-evb-pinctrl.dtsi" -@@ -27,6 +25,14 @@ &i2c3 { - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; -+ -+ mmc0: mmc@0 { -+ compatible = "mmc-spi-slot"; -+ spi-max-frequency = <15625000>; -+ reg = <0x00>; -+ voltage-ranges = <3300 3300>; -+ disable-wp; -+ }; - }; - - &spi1 { -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 3eb811f73aa8..23a983d6a4c8 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -1,9 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0 - /* --* SPDX-License-Identifier: GPL-2.0+ --* --* Copyright (c) 2019-2022 UltraRisc,Inc --* --*/ -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ - - /dts-v1/; - -@@ -261,13 +259,6 @@ spi0: spi@20320000 { - clock-names = "device_clk"; - num-cs = <3>; - spi-max-frequency = <62500000>; -- mmc0: mmc@0 { -- compatible = "mmc-spi-slot"; -- spi-max-frequency = <15625000>; -- reg = <0x00>; -- voltage-ranges = <3300 3300>; -- disable-wp; -- }; - }; - - spi1: spi@20420000 { --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch b/SPECS/linux-lts-kmhv2/0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch new file mode 100644 index 0000000000..9de39c75e0 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch @@ -0,0 +1,578 @@ +From 99ea7fd4bd1ccf2910170d8c84c997b33c948537 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 16 May 2025 11:12:26 +0800 +Subject: [RUYI PATCH] RVCK: riscv:dts: add dp1000.dts for UltraRIsc DP1000 SoC + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/8fa6586e8607e8f2b9bbf701a6cf282b29dac1f7 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/Makefile | 1 + + arch/riscv/boot/dts/ultrarisc/Makefile | 2 + + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 536 +++++++++++++++++++++++ + 3 files changed, 539 insertions(+) + create mode 100644 arch/riscv/boot/dts/ultrarisc/Makefile + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000.dts + +diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile +index 3763d199c70a..297b30243037 100644 +--- a/arch/riscv/boot/dts/Makefile ++++ b/arch/riscv/boot/dts/Makefile +@@ -10,3 +10,4 @@ subdir-y += sophgo + subdir-y += spacemit + subdir-y += starfive + subdir-y += thead ++subdir-y += ultrarisc +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +new file mode 100644 +index 000000000000..c27f490e2b99 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtb-y += dp1000.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +new file mode 100644 +index 000000000000..3eb811f73aa8 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +@@ -0,0 +1,536 @@ ++/* ++* SPDX-License-Identifier: GPL-2.0+ ++* ++* Copyright (c) 2019-2022 UltraRisc,Inc ++* ++*/ ++ ++/dts-v1/; ++ ++/ { ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ compatible = "ultrarisc,dp1000"; ++ model = "ultrarisc,dp1000"; ++ ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS1,115200"; ++ stdout-path = &uart1; ++ }; ++ ++ cpus { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ timebase-frequency = <10000000>; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ reg = <0x00>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu0_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ reg = <0x1>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu1_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu2: cpu@2 { ++ device_type = "cpu"; ++ reg = <0x2>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu2_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu3: cpu@3 { ++ device_type = "cpu"; ++ reg = <0x3>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu3_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu4: cpu@4 { ++ device_type = "cpu"; ++ reg = <0x10>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu4_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu5: cpu@5 { ++ device_type = "cpu"; ++ reg = <0x11>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu5_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu6: cpu@6 { ++ device_type = "cpu"; ++ reg = <0x12>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ ++ clock-frequency = <2000000000>; ++ ++ cpu6_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu7: cpu@7 { ++ device_type = "cpu"; ++ reg = <0x13>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu7_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ }; ++ ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x00 0x80000000 0x4 0x00000000>; ++ }; ++ ++ soc { ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ compatible = "simple-bus"; ++ ranges; ++ ++ clocks { ++ compatible = "simple-bus"; ++ u-boot,dm-pre-reloc; ++ device_clk: device_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <62500000>; ++ #clock-cells = <0>; ++ }; ++ csr_clk: csr_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <250000000>; ++ #clock-cells = <0>; ++ }; ++ }; ++ ++ clint: clint@8000000 { ++ compatible = "riscv,clint0"; ++ interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, ++ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, ++ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, ++ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, ++ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, ++ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, ++ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, ++ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; ++ reg = <0x00 0x8000000 0x00 0x100000>; ++ }; ++ ++ plic: plic@9000000 { ++ #interrupt-cells = <1>; ++ #address-cells = <0>; ++ phandle = <0x01>; ++ compatible = "ultrarisc,dp1000-plic"; ++ interrupt-controller; ++ interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, ++ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, ++ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, ++ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, ++ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, ++ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, ++ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, ++ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; ++ reg = <0x00 0x9000000 0x00 0x4000000>; ++ riscv,max-priority = <0x07>; ++ riscv,ndev = <160>; ++ }; ++ ++ uart0: serial@20300000 { ++ interrupt-parent = <0x01>; ++ interrupts = <17>; ++ clock-frequency = <62500000>; ++ current-speed = <115200>; ++ reg = <0x00 0x20300000 0x00 0x10000>; ++ compatible = "ultrarisc,dp1000-uart","ns16550"; ++ reg-offset = <0x0>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart1: serial@20310000 { ++ interrupt-parent = <0x01>; ++ interrupts = <18>; ++ clock-frequency = <62500000>; ++ current-speed = <115200>; ++ reg = <0x00 0x20310000 0x00 0x10000>; ++ compatible = "ultrarisc,dp1000-uart","ns16550"; ++ reg-offset = <0x0>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart2: serial@20400000 { ++ interrupt-parent = <0x01>; ++ interrupts = <25>; ++ clock-frequency = <62500000>; ++ current-speed = <115200>; ++ reg = <0x00 0x20400000 0x00 0x10000>; ++ compatible = "ultrarisc,dp1000-uart","ns16550"; ++ reg-offset = <0x0>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart3: serial@20410000 { ++ interrupt-parent = <0x01>; ++ interrupts = <26>; ++ clock-frequency = <62500000>; ++ current-speed = <115200>; ++ reg = <0x00 0x20410000 0x00 0x10000>; ++ compatible = "ultrarisc,dp1000-uart","ns16550"; ++ reg-offset = <0x0>; ++ reg-shift = <0x02>; ++ }; ++ ++ spi0: spi@20320000 { ++ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; ++ status = "okay"; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ reg = <0x0 0x20320000 0x0 0x1000>; ++ interrupt-parent = <0x01>; ++ interrupts = <19>; ++ clocks = <&device_clk>; ++ clock-names = "device_clk"; ++ num-cs = <3>; ++ spi-max-frequency = <62500000>; ++ mmc0: mmc@0 { ++ compatible = "mmc-spi-slot"; ++ spi-max-frequency = <15625000>; ++ reg = <0x00>; ++ voltage-ranges = <3300 3300>; ++ disable-wp; ++ }; ++ }; ++ ++ spi1: spi@20420000 { ++ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; ++ status = "okay"; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ reg = <0x0 0x20420000 0x0 0x1000>; ++ interrupt-parent = <0x01>; ++ interrupts = <27>; ++ clocks = <&device_clk>; ++ clock-names = "device_clk"; ++ num-cs = <3>; ++ spi-max-frequency = <62500000>; ++ }; ++ ++ i2c0: i2c@20330000{ ++ compatible = "snps,designware-i2c"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20330000 0x0 0x100>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <20>; ++ }; ++ ++ i2c1: i2c@20340000{ ++ compatible = "snps,designware-i2c"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20340000 0x0 0x100>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <21>; ++ }; ++ ++ i2c2: i2c@20430000{ ++ compatible = "snps,designware-i2c"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20430000 0x0 0x100>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <28>; ++ }; ++ ++ i2c3: i2c@20440000{ ++ compatible = "snps,designware-i2c"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20440000 0x0 0x100>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <29>; ++ }; ++ ++ wdt0: watchdog@20210000 { ++ compatible = "snps,dw-wdt"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20210000 0x0 0x100>; ++ interrupt-parent = <0x01>; ++ interrupts = <33>; ++ clocks = <&device_clk>; ++ }; ++ ++ timer0: timer@20220000 { ++ compatible = "snps,dw-apb-timer"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20220000 0x0 0x100>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <35>; ++ status = "okay"; ++ }; ++ ++ timer1: timer@20230000 { ++ compatible = "snps,dw-apb-timer"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20230000 0x0 0x100>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <36>; ++ status = "okay"; ++ }; ++ ++ gpio: gpio@20200000 { ++ compatible = "snps,dw-apb-gpio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20200000 0x0 0x1000>; ++ clocks = <&csr_clk>, <&device_clk>; ++ clock-names = "bus", "db"; ++ status = "okay"; ++ ++ porta: gpio-port@0 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <16>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupt-parent = <0x01>; ++ interrupts = <34>; ++ }; ++ ++ portb: gpio-port@1 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <1>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ }; ++ ++ portc: gpio-port@2 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <2>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ }; ++ ++ portd: gpio-port@3 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <3>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ }; ++ }; ++ ++ ethernet1@38000000 { ++ clocks = <&csr_clk>; ++ clock-names = "stmmaceth"; ++ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; ++ interrupt-parent = <0x01>; ++ interrupts = <84>; ++ interrupt-names = "macirq"; ++ reg = <0x00 0x38000000 0x00 0x1000000>; ++ local-mac-address = [ff ff ff ff ff ff]; ++ phy-mode = "rgmii"; ++ max-speed = <1000>; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ phy-handle = <&phy0>; ++ mdio { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ compatible = "snps,dwmac-mdio"; ++ phy0: phy@0{ ++ phandle = <0x04>; ++ reg = <0x00>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ dmac: dma-controller@39000000 { ++ compatible = "snps,axi-dma-1.01a"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x39000000 0x0 0x400>; ++ clocks = <&device_clk>, <&device_clk>; ++ clock-names = "core-clk", "cfgr-clk"; ++ interrupt-parent = <0x01>; ++ interrupts = <152>; ++ #dma-cells = <1>; ++ dma-channels = <8>; ++ snps,dma-masters = <1>; ++ snps,data-width = <4>; ++ snps,block-size = <512 512 512 512 512 512 512 512>; ++ snps,priority = <0 1 2 3 4 5 6 7>; ++ snps,axi-max-burst-len = <256>; ++ }; ++ ++ pcie_x16: pcie@21000000 { ++ compatible = "ultrarisc,dw-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x21000000 0x0 0x01000000>, /* IP registers */ ++ <0x0 0x4fff0000 0x0 0x00010000>; /* Configuration space */ ++ reg-names = "dbi", "config"; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <16>; ++ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ ++ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ ++ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ max-link-speed = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <43>, <44>, <45>, <46>, <47>, <48>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, ++ <0x0 0x0 0x0 0x2 &plic 45>, ++ <0x0 0x0 0x0 0x3 &plic 46>, ++ <0x0 0x0 0x0 0x4 &plic 47>; ++ }; ++ ++ pcie_x4a: pcie@23000000 { ++ compatible = "ultrarisc,dw-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x23000000 0x0 0x01000000>, /* IP registers */ ++ <0x0 0x6fff0000 0x0 0x00010000>; /* Configuration space */ ++ reg-names = "dbi", "config"; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <4>; ++ ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ ++ <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ ++ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ max-link-speed = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <63>, <64>, <65>, <66>, <67>, <68>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, ++ <0x0 0x0 0x0 0x2 &plic 65>, ++ <0x0 0x0 0x0 0x3 &plic 66>, ++ <0x0 0x0 0x0 0x4 &plic 67>; ++ }; ++ ++ pcie_x4b: pcie@24000000 { ++ compatible = "ultrarisc,dw-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x24000000 0x0 0x01000000>, /* IP registers */ ++ <0x0 0x7fff0000 0x0 0x00010000>; /* Configuration space */ ++ reg-names = "dbi", "config"; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <4>; ++ ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ ++ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ ++ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ max-link-speed = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <73>, <74>, <75>, <76>, <77>, <78>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, ++ <0x0 0x0 0x0 0x2 &plic 75>, ++ <0x0 0x0 0x0 0x3 &plic 76>, ++ <0x0 0x0 0x0 0x4 &plic 77>; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch b/SPECS/linux-lts-kmhv2/0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch new file mode 100644 index 0000000000..fad0cc8ffd --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch @@ -0,0 +1,880 @@ +From 709a5329d0c5e869292d0fb40e080d1e280adb51 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 17 Jan 2025 19:34:48 +0800 +Subject: [RUYI PATCH] RVCK: pinctrl: add pinctrl dirver for UltraRisc DP1000 + +support pinmux and pinconf for UltraRisc DP1000 SoC + +Signed-off-by: Jia Wang +Signed-off-by: Yanteng Si +FROM: https://github.com/RVCK-Project/rvck/commit/2fdd7d95fb0408b67353ea82e378773ebfe39ade +Signed-off-by: Han Gao +--- + drivers/pinctrl/Kconfig | 1 + + drivers/pinctrl/Makefile | 1 + + drivers/pinctrl/ultrarisc/Kconfig | 20 + + drivers/pinctrl/ultrarisc/Makefile | 4 + + .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 122 +++++ + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 503 ++++++++++++++++++ + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 78 +++ + .../dt-bindings/pinctrl/ur-dp1000-pinctrl.h | 65 +++ + 8 files changed, 794 insertions(+) + create mode 100644 drivers/pinctrl/ultrarisc/Kconfig + create mode 100644 drivers/pinctrl/ultrarisc/Makefile + create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c + create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c + create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h + create mode 100644 include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h + +diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig +index 4f8507ebbdac..b4ba4fb72f10 100644 +--- a/drivers/pinctrl/Kconfig ++++ b/drivers/pinctrl/Kconfig +@@ -712,5 +712,6 @@ source "drivers/pinctrl/ti/Kconfig" + source "drivers/pinctrl/uniphier/Kconfig" + source "drivers/pinctrl/visconti/Kconfig" + source "drivers/pinctrl/vt8500/Kconfig" ++source "drivers/pinctrl/ultrarisc/Kconfig" + + endif +diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile +index e0cfb9b7c99b..32f0d988e505 100644 +--- a/drivers/pinctrl/Makefile ++++ b/drivers/pinctrl/Makefile +@@ -95,3 +95,4 @@ obj-y += ti/ + obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ + obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ + obj-$(CONFIG_ARCH_VT8500) += vt8500/ ++obj-$(CONFIG_ARCH_ULTRARISC) += ultrarisc/ +diff --git a/drivers/pinctrl/ultrarisc/Kconfig b/drivers/pinctrl/ultrarisc/Kconfig +new file mode 100644 +index 000000000000..e4db80843bea +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/Kconfig +@@ -0,0 +1,20 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config PINCTRL_ULTRARISC ++ bool ++ depends on OF ++ select PINMUX ++ select GENERIC_PINCTRL_GROUPS ++ select GENERIC_PINCONF ++ select GENERIC_PINMUX_FUNCTIONS ++ select GPIOLIB ++ select IRQ_DOMAIN_HIERARCHY ++ select MFD_SYSCON ++ ++config PINCTRL_ULTRARISC_DP1000 ++ tristate "Pinctrl driver of UltraRisc DP1000" ++ select PINCTRL_ULTRARISC ++ depends on OF && HAS_IOMEM ++ help ++ This driver configures the UltraRisc DP1000 SoC's pinctrl ++ subsystem. +diff --git a/drivers/pinctrl/ultrarisc/Makefile b/drivers/pinctrl/ultrarisc/Makefile +new file mode 100644 +index 000000000000..5bf3f449d59b +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/Makefile +@@ -0,0 +1,4 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++obj-$(CONFIG_PINCTRL_ULTRARISC) += pinctrl-ultrarisc.o ++obj-$(CONFIG_PINCTRL_ULTRARISC_DP1000) += pinctrl-ultrarisc-dp1000.o +\ No newline at end of file +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +new file mode 100644 +index 000000000000..217f671fe63a +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +@@ -0,0 +1,122 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* UltraRisc DP1000 pinctrl driver ++ * ++ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../pinctrl-utils.h" ++#include "../pinmux.h" ++#include "../core.h" ++#include "../devicetree.h" ++ ++#include "pinctrl-ultrarisc.h" ++ ++static const struct pinctrl_pin_desc ur_dp1000_pins[] = { ++ // PA ++ PINCTRL_PIN(0, "PA0"), ++ PINCTRL_PIN(1, "PA1"), ++ PINCTRL_PIN(2, "PA2"), ++ PINCTRL_PIN(3, "PA3"), ++ PINCTRL_PIN(4, "PA4"), ++ PINCTRL_PIN(5, "PA5"), ++ PINCTRL_PIN(6, "PA6"), ++ PINCTRL_PIN(7, "PA7"), ++ PINCTRL_PIN(8, "PA8"), ++ PINCTRL_PIN(9, "PA9"), ++ PINCTRL_PIN(10, "PA10"), ++ PINCTRL_PIN(11, "PA11"), ++ PINCTRL_PIN(12, "PA12"), ++ PINCTRL_PIN(13, "PA13"), ++ PINCTRL_PIN(14, "PA14"), ++ PINCTRL_PIN(15, "PA15"), ++ // PB ++ PINCTRL_PIN(16, "PB0"), ++ PINCTRL_PIN(17, "PB1"), ++ PINCTRL_PIN(18, "PB2"), ++ PINCTRL_PIN(19, "PB3"), ++ PINCTRL_PIN(20, "PB4"), ++ PINCTRL_PIN(21, "PB5"), ++ PINCTRL_PIN(22, "PB6"), ++ PINCTRL_PIN(23, "PB7"), ++ // PC ++ PINCTRL_PIN(24, "PC0"), ++ PINCTRL_PIN(25, "PC1"), ++ PINCTRL_PIN(26, "PC2"), ++ PINCTRL_PIN(27, "PC3"), ++ PINCTRL_PIN(28, "PC4"), ++ PINCTRL_PIN(29, "PC5"), ++ PINCTRL_PIN(30, "PC6"), ++ PINCTRL_PIN(31, "PC7"), ++ // PD ++ PINCTRL_PIN(32, "PD0"), ++ PINCTRL_PIN(33, "PD1"), ++ PINCTRL_PIN(34, "PD2"), ++ PINCTRL_PIN(35, "PD3"), ++ PINCTRL_PIN(36, "PD4"), ++ PINCTRL_PIN(37, "PD5"), ++ PINCTRL_PIN(38, "PD6"), ++ PINCTRL_PIN(39, "PD7"), ++ // LPC ++ PINCTRL_PIN(40, "LPC0"), ++ PINCTRL_PIN(41, "LPC1"), ++ PINCTRL_PIN(42, "LPC2"), ++ PINCTRL_PIN(43, "LPC3"), ++ PINCTRL_PIN(44, "LPC4"), ++ PINCTRL_PIN(45, "LPC5"), ++ PINCTRL_PIN(46, "LPC6"), ++ PINCTRL_PIN(47, "LPC7"), ++ PINCTRL_PIN(48, "LPC8"), ++ PINCTRL_PIN(49, "LPC9"), ++ PINCTRL_PIN(50, "LPC10"), ++ PINCTRL_PIN(51, "LPC11"), ++ PINCTRL_PIN(52, "LPC12"), ++}; ++ ++static struct ur_pinctrl_match_data ur_dp1000_match_data = { ++ .pins = ur_dp1000_pins, ++ .npins = ARRAY_SIZE(ur_dp1000_pins), ++ .offset = 0x2c0, ++ .ports = { ++ {"A", 16, 0x2c0, 0x310}, ++ {"B", 8, 0x2c4, 0x318}, ++ {"C", 8, 0x2c8, 0x31c}, ++ {"D", 8, 0x2cc, 0x320}, ++ {"LPC", 13, 0x2d0, 0x324}, ++ }, ++}; ++ ++enum ur_dp1000_port_list { ++ PORT_A = 0, ++ PORT_B, ++ PORT_C, ++ PORT_D, ++ PORT_LPC ++}; ++ ++ ++static const struct of_device_id ur_pinctrl_of_match[] = { ++ { .compatible = "ultrarisc,dp1000-pinctrl", .data = &ur_dp1000_match_data, }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ur_pinctrl_of_match); ++ ++static struct platform_driver ur_pinctrl_driver = { ++ .driver = { ++ .name = "ultrarisc-pinctrl-dp1000", ++ .of_match_table = ur_pinctrl_of_match, ++ }, ++ .probe = ur_pinctrl_probe, ++ .remove = ur_pinctrl_remove, ++}; ++ ++module_platform_driver(ur_pinctrl_driver); +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +new file mode 100644 +index 000000000000..667d59e0ac6e +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +@@ -0,0 +1,503 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* UltraRisc pinctrl driver ++ * ++ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../pinctrl-utils.h" ++#include "../pinmux.h" ++#include "../core.h" ++#include "../devicetree.h" ++ ++#include "pinctrl-ultrarisc.h" ++ ++static int ur_pin_to_desc(struct pinctrl_dev *pctldev, struct ur_pin_val *pin_val) ++{ ++ int index = 0; ++ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ const struct ur_pinctrl_match_data *ur_match_data = ur_pinctrl->match_data; ++ ++ for (int i = 0; i < pin_val->port; i++) ++ index += ur_match_data->ports[i].npins; ++ index += pin_val->pin; ++ dev_dbg(pctldev->dev, "port %d pin %d index %d\n", pin_val->port, pin_val->pin, index); ++ return index; ++} ++ ++static int ur_subnode_to_pin(struct pinctrl_dev *pctldev, ++ const char *name, ++ enum pinctrl_map_type type, ++ struct device_node *np, ++ int **pins, ++ struct ur_pin_val **pin_val, ++ int *pin_num) ++{ ++ struct ur_pin_val *pin_vals; ++ int rows; ++ int ret = -EINVAL; ++ int *group_pins; ++ const char **pgnames; ++ ++ dev_dbg(pctldev->dev, "pinctrl node %s\n", np->name); ++ rows = pinctrl_count_index_with_args(np, name); ++ if (rows < 0) { ++ dev_err(pctldev->dev, "%s count is invalid %d\n", name, rows); ++ return rows; ++ } ++ ++ pin_vals = devm_kcalloc(pctldev->dev, rows, sizeof(*pin_vals), GFP_KERNEL); ++ if (!pin_vals) { ++ return -ENOMEM; ++ } ++ ++ group_pins = devm_kcalloc(pctldev->dev, rows, sizeof(*group_pins), GFP_KERNEL); ++ if (!group_pins) { ++ ret = -ENOMEM; ++ goto free_pin_vals; ++ } ++ ++ pgnames = devm_kzalloc(pctldev->dev, sizeof(*pgnames), GFP_KERNEL); ++ if (!pgnames) { ++ ret = -ENOMEM; ++ goto free_pins; ++ } ++ ++ for (int i = 0; i < rows; i++) { ++ struct of_phandle_args pin_args; ++ ++ ret = pinctrl_parse_index_with_args(np, name, i, &pin_args); ++ if (ret) { ++ dev_err(pctldev->dev, "parse args of %s index %d failed\n", name, i); ++ goto free_pgnames; ++ } ++ ++ if (pin_args.args_count < 3) { ++ dev_err(pctldev->dev, "invalid args_count(%d) of %s index %d/%d\n", ++ pin_args.args_count, name, i, rows); ++ ret = -EINVAL; ++ goto free_pgnames; ++ } ++ pin_vals[i].port = pin_args.args[0]; ++ pin_vals[i].pin = pin_args.args[1]; ++ pin_vals[i].mode = pin_args.args[2]; ++ ++ dev_dbg(pctldev->dev, "found a pinctrl: port=%d pin=%d val=0x%x\n", ++ pin_vals[i].port, pin_vals[i].pin, pin_vals[i].mode); ++ ++ group_pins[i] = ur_pin_to_desc(pctldev, &pin_vals[i]); ++ } ++ ++ dev_dbg(pctldev->dev, "get an pinmux of %s\n", np->name); ++ ++ ret = pinctrl_generic_add_group(pctldev, np->name, group_pins, rows, pin_vals); ++ if (ret < 0) { ++ dev_err(pctldev->dev, "add group %s failed\n", np->name); ++ goto free_pgnames; ++ } ++ ++ *pgnames = np->name; ++ ret = pinmux_generic_add_function(pctldev, np->name, pgnames, 1, NULL); ++ if (ret < 0) { ++ dev_err(pctldev->dev, "add function %s failed\n", np->name); ++ goto free_group; ++ } ++ ++ dev_dbg(pctldev->dev, "add group and function of %s\n", np->name); ++ ++ *pins = group_pins; ++ *pin_val = pin_vals; ++ *pin_num = rows; ++ ++ return 0; ++ ++free_group: ++ pinctrl_generic_remove_group(pctldev, ret); ++free_pgnames: ++ devm_kfree(pctldev->dev, pgnames); ++free_pins: ++ devm_kfree(pctldev->dev, group_pins); ++free_pin_vals: ++ devm_kfree(pctldev->dev, pin_vals); ++ return ret; ++} ++ ++static int ur_pinmux_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *np, ++ struct pinctrl_map *map) ++{ ++ int ret; ++ int *pins; ++ struct ur_pin_val *pin_vals; ++ int pin_num; ++ ++ ret = ur_subnode_to_pin(pctldev, PINMUX_PROP_NAME, PIN_MAP_TYPE_MUX_GROUP, ++ np, &pins, &pin_vals, &pin_num); ++ if (ret) { ++ dev_err(pctldev->dev, "get pinmux data %s failed\n", np->name); ++ return ret; ++ } ++ ++ map->type = PIN_MAP_TYPE_MUX_GROUP; ++ map->data.mux.group = np->name; ++ map->data.mux.function = np->name; ++ ++ dev_dbg(pctldev->dev, "type=%d, mux.group=%s, mux.function=%s\n", ++ map->type, map->data.mux.group, map->data.mux.function); ++ ++ return 0; ++} ++ ++static int ur_pinconf_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *np, ++ struct pinctrl_map *map) ++{ ++ int ret; ++ int *pins; ++ struct ur_pin_val *pin; ++ int pin_num; ++ ++ ret = ur_subnode_to_pin(pctldev, PINCONF_PROP_NAME, PIN_MAP_TYPE_CONFIGS_GROUP, ++ np, &pins, &pin, &pin_num); ++ if (ret) { ++ dev_err(pctldev->dev, "get pinconf data %s failed\n", np->name); ++ return ret; ++ } ++ ++ dev_dbg(pctldev->dev, "get an pinconf of %s\n", np->name); ++ map->type = PIN_MAP_TYPE_CONFIGS_GROUP; ++ map->data.configs.group_or_pin = np->name; ++ map->data.configs.configs = (unsigned long *)pin; ++ map->data.configs.num_configs = pin_num; ++ ++ dev_dbg(pctldev->dev, "type=%d, config.group_or_pin=%s, configs.num_config=%d\n", ++ map->type, map->data.configs.group_or_pin, map->data.configs.num_configs); ++ ++ return 0; ++} ++ ++static int ur_dt_node_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *np, ++ struct pinctrl_map **map, ++ unsigned int *num_maps) ++{ ++ int ret; ++ bool mux_present = false, conf_present = false; ++ struct pinctrl_map *new_map; ++ unsigned int map_num = 0, prop_count = 0; ++ ++ //device_get_named_child_node(pctldev->dev, np->name); ++ if (of_property_present(np, PINMUX_PROP_NAME)) { ++ mux_present = true; ++ prop_count++; ++ } ++ if (of_property_present(np, PINCONF_PROP_NAME)) { ++ conf_present = true; ++ prop_count++; ++ } ++ ++ if (!prop_count) { ++ dev_err(pctldev->dev, "no pinctrl node(%d) in %s\n", prop_count, np->name); ++ return -EINVAL; ++ } ++ ++ new_map = devm_kmalloc_array(pctldev->dev, prop_count, sizeof(**map), GFP_KERNEL); ++ if (!new_map) ++ return -ENOMEM; ++ ++ *map = new_map; ++ if (mux_present) { ++ ret = ur_pinmux_to_map(pctldev, np, new_map); ++ if (!ret) { ++ new_map++; ++ map_num++; ++ } ++ } ++ if (conf_present) { ++ ret = ur_pinconf_to_map(pctldev, np, new_map); ++ if (!ret) ++ map_num++; ++ } ++ ++ if (!map_num) { ++ dev_err(pctldev->dev, "no pinctrl info of %s failed\n", np->name); ++ goto free_map; ++ } ++ *num_maps = map_num; ++ ++ return 0; ++ ++free_map: ++ devm_kfree(pctldev->dev, new_map); ++ return ret; ++} ++ ++static void ur_dt_free_map(struct pinctrl_dev *pctldev, ++ struct pinctrl_map *map, unsigned int num_maps) ++{ ++ if (map) ++ devm_kfree(pctldev->dev, map); ++} ++ ++static void ur_pin_dbg_show(struct pinctrl_dev *pctldev, ++ struct seq_file *s, unsigned int offset) ++{ ++ seq_printf(s, "%s", dev_name(pctldev->dev)); ++} ++ ++static const struct pinctrl_ops ur_pinctrl_ops = { ++ .get_groups_count = pinctrl_generic_get_group_count, ++ .get_group_name = pinctrl_generic_get_group_name, ++ .get_group_pins = pinctrl_generic_get_group_pins, ++ .dt_node_to_map = ur_dt_node_to_map, ++ .dt_free_map = ur_dt_free_map, ++ .pin_dbg_show = ur_pin_dbg_show, ++}; ++ ++static int ur_set_pin_mux(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) ++{ ++ unsigned long flag; ++ //bool clear_mode = false; ++ void __iomem *reg; ++ u32 val; ++ const struct ur_port_desc *port; ++ ++ port = &pin_ctrl->match_data->ports[pin_vals->port]; ++ ++ reg = pin_ctrl->base + port->func_offset; ++ ++ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); ++ val = readl_relaxed(reg); ++ val &= ~((UR_FUNC0 | UR_FUNC1)<pin); ++ val |= (pin_vals->mode << pin_vals->pin); ++ writel_relaxed(val, reg); ++ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); ++ ++ return 0; ++} ++ ++static int ur_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, ++ unsigned int group_selector) ++{ ++ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ struct group_desc *ur_group; ++ struct ur_pin_val *pin_vals; ++ ++ dev_dbg(pctldev->dev, "set mux: func_selector=%d, group_selector=%d\n", ++ func_selector, group_selector); ++ ur_group = pinctrl_generic_get_group(pctldev, group_selector); ++ if (!ur_group) { ++ dev_err(pctldev->dev, "get group %d failed\n", group_selector); ++ return -EINVAL; ++ } ++ ++ dev_dbg(pctldev->dev, "get group %s, num_pins=%zu\n", ur_group->grp.name, ur_group->grp.npins); ++ pin_vals = ur_group->data; ++ if (!pin_vals) { ++ dev_err(pctldev->dev, "data of %s is invalid\n", ur_group->grp.name); ++ return -EINVAL; ++ } ++ ++ for (int i = 0; i < ur_group->grp.npins; i++) ++ ur_set_pin_mux(ur_pinctrl, &pin_vals[i]); ++ ++ return 0; ++} ++ ++static const struct pinmux_ops ur_pinmux_ops = { ++ .get_functions_count = pinmux_generic_get_function_count, ++ .get_function_name = pinmux_generic_get_function_name, ++ .get_function_groups = pinmux_generic_get_function_groups, ++ .set_mux = ur_set_mux, ++ .strict = true, ++}; ++ ++#define UR_CONF_BIT_PER_PIN (4) ++#define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) ++static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) ++{ ++ const struct ur_port_desc *port_desc; ++ unsigned long flag; ++ void __iomem *reg; ++ u32 val, conf; ++ ++ port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; ++ reg = pin_ctrl->base + port_desc->conf_offset; ++ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); ++ reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; ++ dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); ++ ++ conf = pin_vals->conf << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN); ++ dev_dbg(pin_ctrl->dev, "pinconf conf=0x%x\n", conf); ++ ++ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); ++ val = readl_relaxed(reg); ++ val &= ~(UR_BIAS_MASK << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN)); ++ val |= conf; ++ writel_relaxed(val, reg); ++ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); ++ dev_dbg(pin_ctrl->dev, "pinconf val=0x%x\n", val); ++ ++ return 0; ++} ++ ++static int ur_pin_config_get(struct pinctrl_dev *pctldev, ++ unsigned int pin, ++ unsigned long *config) ++{ ++ dev_dbg(pctldev->dev, "%s(%d): pin=%d\n", __func__, __LINE__, pin); ++ // TODO: this is call by pinconf-generic ++ return -EOPNOTSUPP; ++} ++ ++static int ur_pin_config_set(struct pinctrl_dev *pctldev, ++ unsigned int pin, ++ unsigned long *configs, ++ unsigned int num_configs) ++{ ++ struct ur_pin_val *pin_conf; ++ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ ++ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", ++ __func__, __LINE__, pin, num_configs); ++ pin_conf = (struct ur_pin_val *)configs; ++ for (int i = 0; i < num_configs; i++) { ++ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", ++ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); ++ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); ++ } ++ return 0; ++} ++ ++static int ur_pin_config_group_get(struct pinctrl_dev *pctldev, ++ unsigned selector, ++ unsigned long *config) ++{ ++ dev_dbg(pctldev->dev, "%s(%d): selector=%d, config=0x%lx\n", ++ __func__, __LINE__, selector, *config); ++ return -EOPNOTSUPP; ++} ++ ++static int ur_pin_config_group_set(struct pinctrl_dev *pctldev, ++ unsigned int selector, ++ unsigned long *configs, ++ unsigned int num_configs) ++{ ++ struct group_desc *ur_group; ++ struct ur_pin_val *pin_conf; ++ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ ++ dev_dbg(pctldev->dev, "%s(%d): selector=%d, num_configs=%d\n", ++ __func__, __LINE__, selector, num_configs); ++ ur_group = pinctrl_generic_get_group(pctldev, selector); ++ if (!ur_group) { ++ dev_err(pctldev->dev, "Cannot get group by selector %d\n", selector); ++ return -EINVAL; ++ } ++ ++ dev_dbg(pctldev->dev, "get pinconf group %s\n", ur_group->grp.name); ++ pin_conf = (struct ur_pin_val *)configs; ++ for (int i = 0; i < num_configs; i++) { ++ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", ++ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); ++ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); ++ } ++ return 0; ++} ++ ++static const struct pinconf_ops ur_pinconf_ops = { ++ .pin_config_get = ur_pin_config_get, ++ .pin_config_set = ur_pin_config_set, ++ .pin_config_group_get = ur_pin_config_group_get, ++ .pin_config_group_set = ur_pin_config_group_set, ++#ifdef CONFIG_GENERIC_PINCONF ++ .is_generic = true, ++#endif ++}; ++ ++int ur_pinctrl_probe(struct platform_device *pdev) ++{ ++ struct pinctrl_desc *ur_pinctrl_desc; ++ const struct ur_pinctrl_match_data *pins_data; ++ struct ur_pinctrl *ur_pinctrl; ++ int ret; ++ ++ pins_data = of_device_get_match_data(&pdev->dev); ++ if (!pins_data) ++ return -ENODEV; ++ ++ ur_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl_desc), GFP_KERNEL); ++ if (!ur_pinctrl_desc) { ++ dev_err(&pdev->dev, "pinctrl desc alloc failed\n"); ++ return -ENOMEM; ++ } ++ ++ ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); ++ if (!ur_pinctrl) { ++ dev_err(&pdev->dev, "pinctrl alloc failed\n"); ++ ret = -ENOMEM; ++ goto free_pinctrl_desc; ++ } ++ struct resource *res; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dev_dbg(&pdev->dev, "iomem start=0x%llx\n", res->start); ++ ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(ur_pinctrl->base)) { ++ dev_err(&pdev->dev, "get ioremap resource failed\n"); ++ ret = -EINVAL; ++ goto free_pinctrl_desc; ++ } ++ dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); ++ ur_pinctrl_desc->name = dev_name(&pdev->dev); ++ ur_pinctrl_desc->owner = THIS_MODULE; ++ ur_pinctrl_desc->pins = pins_data->pins; ++ ur_pinctrl_desc->npins = pins_data->npins; ++ ur_pinctrl_desc->pctlops = &ur_pinctrl_ops; ++ ur_pinctrl_desc->pmxops = &ur_pinmux_ops; ++ ur_pinctrl_desc->confops = &ur_pinconf_ops; ++ ++ ur_pinctrl->dev = &pdev->dev; ++ ur_pinctrl->match_data = pins_data; ++ ur_pinctrl->pctl_desc = ur_pinctrl_desc; ++ raw_spin_lock_init(&ur_pinctrl->lock); ++ mutex_init(&ur_pinctrl->mutex); ++ ++ ret = devm_pinctrl_register_and_init(&pdev->dev, ur_pinctrl_desc, ++ ur_pinctrl, &ur_pinctrl->pctl_dev); ++ if (ret) { ++ dev_err(&pdev->dev, "pinctrl register failed\n"); ++ goto free_pinctrl; ++ } ++ ++ platform_set_drvdata(pdev, ur_pinctrl); ++ ++ return pinctrl_enable(ur_pinctrl->pctl_dev); ++ ++free_pinctrl: ++ devm_kfree(&pdev->dev, ur_pinctrl); ++free_pinctrl_desc: ++ devm_kfree(&pdev->dev, ur_pinctrl_desc); ++ return ret; ++} ++ ++ ++void ur_pinctrl_remove(struct platform_device *pdev) ++{ ++ struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); ++ ++ if (ur_pinctrl->pctl_dev) ++ devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); ++} +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +new file mode 100644 +index 000000000000..eec621bf8b05 +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +@@ -0,0 +1,78 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* UltraRisc pinctrl driver ++ * ++ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#ifndef __PINCTRL_ULTRARISC_H__ ++#define __PINCTRL_ULTRARISC_H__ ++ ++#include ++#include ++ ++#define PINMUX_PROP_NAME "pinctrl-pins" ++#define PINCONF_PROP_NAME "pinconf-pins" ++ ++struct ur_pin_conf { ++ u16 pull; ++ u16 drive; ++}; ++ ++struct ur_pin_val { ++ u32 port; ++ u32 pin; ++ union { ++ u32 mode; ++ u32 conf; ++ }; ++#define UR_FUNC_DEF 0 ++#define UR_FUNC0 1 ++#define UR_FUNC1 0x10000 ++ ++#define UR_BIAS_MASK 0x0000000F ++#define UR_PULL_MASK 0x0C ++#define UR_PULL_DIS 0 ++#define UR_PULL_UP 1 ++#define UR_PULL_DOWN 2 ++#define UR_DRIVE_MASK 0x03 ++}; ++ ++struct ur_port_desc { ++ char *name; ++ u32 npins; ++ u32 func_offset; ++ u32 conf_offset; ++}; ++ ++struct ur_pinctrl_match_data { ++ const struct pinctrl_pin_desc *pins; ++ u32 npins; ++ u32 offset; ++ //u32 conf_offset[]; ++ struct ur_port_desc ports[]; ++}; ++ ++ ++struct ur_pinctrl { ++ struct device *dev; ++ struct pinctrl_dev *pctl_dev; ++ struct pinctrl_desc *pctl_desc; ++ void __iomem *base; ++ unsigned int ngroups; ++ const char **grp_names; ++ unsigned int nbanks; ++ const struct ur_pinctrl_match_data *match_data; ++ struct regmap *regmap; ++ raw_spinlock_t lock; ++ struct mutex mutex; ++ struct pinctrl_pin_desc *pins; ++ u32 npins; ++ u32 pkg; ++}; ++ ++int ur_pinctrl_probe(struct platform_device *pdev); ++void ur_pinctrl_remove(struct platform_device *pdev); ++ ++#endif +diff --git a/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h +new file mode 100644 +index 000000000000..5bec446e2411 +--- /dev/null ++++ b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h +@@ -0,0 +1,65 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* UltraRisc DP1000 pinctrl header ++ * ++ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#ifndef __UR_DP1000_PINCTRL_H__ ++#define __UR_DP1000_PINCTRL_H__ ++ ++#define UR_DP1000_IOMUX_A 0x0 ++#define UR_DP1000_IOMUX_B 0x1 ++#define UR_DP1000_IOMUX_C 0x2 ++#define UR_DP1000_IOMUX_D 0x3 ++#define UR_DP1000_IOMUX_LPC 0x4 ++ ++#define UR_FUNC_DEF 0 ++#define UR_FUNC0 1 ++#define UR_FUNC1 0x10000 ++ ++/** ++ * port: 'A' 'B' 'C' ++ * Pin in the port ++ * pin: ++ * PA: 0 - 15 ++ * PB-PD: 0 - 7 ++ * func: ++ * UR_FUNC_DEF: default ++ * UR_FUNC0: func0 ++ * UR_FUNC1: func1 ++ */ ++#define UR_DP1000_IOPAD(port, pin, func) (port) (pin) (func) ++ ++/** ++ * Configure pull up/down resistor of the IO pin ++ * UR_PULL_DIS: disable pull-up and pull-down ++ * UR_PULL_UP: enable pull-up ++ * UR_PULL_DOWN: enable pull-down ++ */ ++#define UR_PULL_DIS 0 ++#define UR_PULL_UP 1 ++#define UR_PULL_DOWN 2 ++/** ++ * Configure drive strength of the IO pin ++ * UR_DRIVE_DEF: default value, reset value is 2 ++ * UR_DRIVE_0: 20mA ++ * UR_DRIVE_1: 27mA ++ * UR_DIRVE_2: 33mA ++ * UR_DRIVE_3: 40mA ++ */ ++#define UR_DRIVE_DEF 2 ++#define UR_DRIVE_0 0 ++#define UR_DRIVE_1 1 ++#define UR_DRIVE_2 2 ++#define UR_DRIVE_3 3 ++ ++/** ++ * Combine the pull-up/down resistor and drive strength ++ * pull: UR_PULL_DIS, UR_PULL_UP, UR_PULL_DOWN ++ * drive: UR_DRIVE_DEF, UR_DRIVE_0, UR_DRIVE_1, UR_DRIVE_2, UR_DRIVE_3 ++ */ ++#define UR_DP1000_BIAS(pull, drive) (((pull)<<2) + (drive)) ++ ++#endif +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0449-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch b/SPECS/linux-lts-kmhv2/0449-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch deleted file mode 100644 index 67053738ec..0000000000 --- a/SPECS/linux-lts-kmhv2/0449-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch +++ /dev/null @@ -1,78 +0,0 @@ -From b8a01535a0fbc907f912f8d76412850ef78416a8 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 18 Sep 2025 10:44:01 +0800 -Subject: [PATCH 449/467] RVCK: riscv: dp1000: plic: add plic early init - supports - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - -------------------------------------------------- - -Add PLIC early init supports and remove invalid -timer nodes in dp1000.dts. - -Signed-off-by: Jia Wang -From: https://github.com/RVCK-Project/rvck/commit/9e4cfbdf46fad772cc002c53b9e295cda600e9c5 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 25 ++---------------------- - drivers/irqchip/irq-sifive-plic.c | 1 + - 2 files changed, 3 insertions(+), 23 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 23a983d6a4c8..4a2dae602693 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -164,6 +164,7 @@ device_clk: device_clk { - clock-frequency = <62500000>; - #clock-cells = <0>; - }; -+ - csr_clk: csr_clk { - compatible = "fixed-clock"; - clock-frequency = <250000000>; -@@ -333,29 +334,7 @@ wdt0: watchdog@20210000 { - interrupts = <33>; - clocks = <&device_clk>; - }; -- -- timer0: timer@20220000 { -- compatible = "snps,dw-apb-timer"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x20220000 0x0 0x100>; -- clocks = <&device_clk>; -- interrupt-parent = <0x01>; -- interrupts = <35>; -- status = "okay"; -- }; -- -- timer1: timer@20230000 { -- compatible = "snps,dw-apb-timer"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x20230000 0x0 0x100>; -- clocks = <&device_clk>; -- interrupt-parent = <0x01>; -- interrupts = <36>; -- status = "okay"; -- }; -- -+ - gpio: gpio@20200000 { - compatible = "snps,dw-apb-gpio"; - #address-cells = <1>; -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index 70058871d2fb..007a4668f9e5 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -846,3 +846,4 @@ static int __init plic_early_probe(struct device_node *node, - } - - IRQCHIP_DECLARE(riscv, "allwinner,sun20i-d1-plic", plic_early_probe); -+IRQCHIP_DECLARE(ultrarisc_dp1000_plic, "ultrarisc,dp1000-plic", plic_early_probe); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch b/SPECS/linux-lts-kmhv2/0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch new file mode 100644 index 0000000000..935589d38c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch @@ -0,0 +1,237 @@ +From c3b99eaa70d3c031fe29c503b85abb31e02d50a4 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Mon, 16 Jun 2025 10:25:31 +0800 +Subject: [RUYI PATCH] RVCK: dts: add pinctrl dtsi/dts for UltraRisc DP1000 + +The newly added dtsi/dts is used to describe the pinctrl +configuration of the UltraRisc DP1000-EVB mainboard. + +Do not involve functional changes. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/e00864f9706198f8b278551217c048a140cbe39f +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 2 +- + .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 141 ++++++++++++++++++ + .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 52 +++++++ + 3 files changed, 194 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index c27f490e2b99..ef70e28e0b65 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,2 +1,2 @@ + # SPDX-License-Identifier: GPL-2.0 +-dtb-y += dp1000.dtb ++dtb-y += dp1000.dtb dp1000-evb-v1.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +new file mode 100644 +index 000000000000..be898b6df6fb +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +@@ -0,0 +1,141 @@ ++#include ++ ++/ { ++ ++ soc { ++ pmx0: pinmux@11081000 { ++ compatible = "ultrarisc,dp1000-pinctrl"; ++ reg = <0x0 0x11081000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #pinctrl-cells = <2>; ++ pinctrl-single,register-width = <32>; ++ pinctrl-single,function-mask = <0x3ff>; ++ pinctrl-use-default; ++ ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +new file mode 100644 +index 000000000000..5ec9a39e8c34 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +@@ -0,0 +1,52 @@ ++/* ++* SPDX-License-Identifier: GPL-2.0+ ++* ++* Copyright (c) 2019-2022 UltraRisc,Inc ++* ++*/ ++ ++#include "dp1000.dts" ++#include "dp1000-evb-pinctrl.dtsi" ++#include ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0450-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch b/SPECS/linux-lts-kmhv2/0450-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch deleted file mode 100644 index fbb0fe8e41..0000000000 --- a/SPECS/linux-lts-kmhv2/0450-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch +++ /dev/null @@ -1,85 +0,0 @@ -From c2b729c99b333e2485660b66669d1415bfd256bb Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 10 Nov 2025 16:11:12 +0800 -Subject: [PATCH 450/467] RVCK: riscv: dp1000: dts: Move chosen node from - common to board-specific DTS - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -This commit moves the chosen node configuration from the -common dp1000.dts file to the respective board-specific -DTS files. - -This change allows each board to specify its own console -configuration while keeping the common SoC definitions clean. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/db5745be89ee881ff18a7ded0bcff1c2f495becf -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 7 +++++++ - arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 7 +++++++ - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 7 +------ - 3 files changed, 15 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 34622a33e63b..34d024a083fc 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -7,6 +7,13 @@ - #include "dp1000-evb-pinctrl.dtsi" - #include - -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS1,115200"; -+ stdout-path = &uart1; -+ }; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -index a74714629566..8c532e5b71a3 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -7,6 +7,13 @@ - #include "dp1000-mo-pinctrl.dtsi" - #include - -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS0,115200"; -+ stdout-path = &uart0; -+ }; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 4a2dae602693..128293c0af1f 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -10,12 +10,7 @@ / { - #size-cells = <0x02>; - compatible = "ultrarisc,dp1000"; - model = "ultrarisc,dp1000"; -- -- chosen { -- bootargs = "earlycon=sbi console=ttyS1,115200"; -- stdout-path = &uart1; -- }; -- -+ - cpus { - #address-cells = <0x01>; - #size-cells = <0x00>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0451-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch b/SPECS/linux-lts-kmhv2/0451-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch deleted file mode 100644 index bd085b039a..0000000000 --- a/SPECS/linux-lts-kmhv2/0451-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch +++ /dev/null @@ -1,677 +0,0 @@ -From 03de28a6f7321aa6b3f914c0547661e9c15e62cc Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 11 Nov 2025 17:03:37 +0800 -Subject: [PATCH 451/467] RVCK: dts: riscv: ultrarisc: Refactor DP1000 device - tree files - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Add gpio-ranges property to all gpio/portX nodes. -This property maps GPIO lines to pin controller pins, -ensuring proper GPIO pin allocation and management. - -Convert dp1000.dts to a common include file (dp1000.dtsi) and update -the board-specific DTS files to include it. This refactoring allows -for better code reuse across different DP1000-based boards (EVB, MO, -and Titan variants) while maintaining board-specific configurations. - -The changes include: -- Renaming dp1000.dts to dp1000.dtsi -- Updating board-specific DTS files to include the common .dtsi -- Adjusting Makefile to reflect these changes -- Updating pinctrl files for all board variants - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/f9d4926fccee70f72d11e11dfa11b99f59caa947 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 1 - - .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 261 +++++++++--------- - .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 1 - - .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 261 +++++++++--------- - .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 1 - - .../dts/ultrarisc/{dp1000.dts => dp1000.dtsi} | 15 + - 6 files changed, 263 insertions(+), 277 deletions(-) - rename arch/riscv/boot/dts/ultrarisc/{dp1000.dts => dp1000.dtsi} (96%) - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index 9eac56549340..22c03b44b2f8 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,4 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -index e82fcf2901ab..e2c09d5bdb20 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -4,143 +4,130 @@ - */ - - #include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ UR_DP1000_IOMUX_D 6 UR_FUNC1 -+ UR_DP1000_IOMUX_D 7 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; - --/ { -- -- soc { -- pmx0: pinmux@11081000 { -- compatible = "ultrarisc,dp1000-pinctrl"; -- reg = <0x0 0x11081000 0x0 0x1000>; -- #address-cells = <1>; -- #size-cells = <0>; -- #pinctrl-cells = <2>; -- pinctrl-single,register-width = <32>; -- pinctrl-single,function-mask = <0x3ff>; -- pinctrl-use-default; -- -- i2c0_pins: i2c0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c1_pins: i2c1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c2_pins: i2c2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c3_pins: i2c3_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart0_pins: uart0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart1_pins: uart1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart2_pins: uart2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi0_pins: spi0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi1_pins: spi1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- }; -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; - }; - }; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 34d024a083fc..46fe457b5f52 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -3,7 +3,6 @@ - * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. - */ - --#include "dp1000.dts" - #include "dp1000-evb-pinctrl.dtsi" - #include - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -index e82fcf2901ab..85b013f66bbd 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -@@ -4,143 +4,130 @@ - */ - - #include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ UR_DP1000_IOMUX_D 6 UR_FUNC1 -+ UR_DP1000_IOMUX_D 7 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; - --/ { -- -- soc { -- pmx0: pinmux@11081000 { -- compatible = "ultrarisc,dp1000-pinctrl"; -- reg = <0x0 0x11081000 0x0 0x1000>; -- #address-cells = <1>; -- #size-cells = <0>; -- #pinctrl-cells = <2>; -- pinctrl-single,register-width = <32>; -- pinctrl-single,function-mask = <0x3ff>; -- pinctrl-use-default; -- -- i2c0_pins: i2c0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c1_pins: i2c1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c2_pins: i2c2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c3_pins: i2c3_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart0_pins: uart0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart1_pins: uart1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart2_pins: uart2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi0_pins: spi0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi1_pins: spi1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- }; -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; - }; - }; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -index 8c532e5b71a3..dc057cbaf59b 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -3,7 +3,6 @@ - * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. - */ - --#include "dp1000.dts" - #include "dp1000-mo-pinctrl.dtsi" - #include - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -similarity index 96% -rename from arch/riscv/boot/dts/ultrarisc/dp1000.dts -rename to arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index 128293c0af1f..a25e87e15553 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -330,6 +330,17 @@ wdt0: watchdog@20210000 { - clocks = <&device_clk>; - }; - -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ }; -+ - gpio: gpio@20200000 { - compatible = "snps,dw-apb-gpio"; - #address-cells = <1>; -@@ -349,6 +360,7 @@ porta: gpio-port@0 { - #interrupt-cells = <2>; - interrupt-parent = <0x01>; - interrupts = <34>; -+ gpio-ranges = <&pmx0 0 0 16>; - }; - - portb: gpio-port@1 { -@@ -357,6 +369,7 @@ portb: gpio-port@1 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 16 0 8>; - }; - - portc: gpio-port@2 { -@@ -365,6 +378,7 @@ portc: gpio-port@2 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 24 0 8>; - }; - - portd: gpio-port@3 { -@@ -373,6 +387,7 @@ portd: gpio-port@3 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 32 0 8>; - }; - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch b/SPECS/linux-lts-kmhv2/0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch new file mode 100644 index 0000000000..dfeb639386 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch @@ -0,0 +1,251 @@ +From 6e08f5227680fcb9eef599c73c6a48dbba8d8f66 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Thu, 4 Sep 2025 16:31:30 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: add the dts of UltraRISC + dp1000-mo-v1 board + +adds the necessary device tree files for the UltraRISC +dp1000-mo-v1 board. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/1186c972f5908717ab186cea67403c74ea03cde1 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 4 +- + .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 146 ++++++++++++++++++ + .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 60 +++++++ + 3 files changed, 209 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index ef70e28e0b65..9eac56549340 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,2 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 +-dtb-y += dp1000.dtb dp1000-evb-v1.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +new file mode 100644 +index 000000000000..e82fcf2901ab +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +@@ -0,0 +1,146 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include ++ ++/ { ++ ++ soc { ++ pmx0: pinmux@11081000 { ++ compatible = "ultrarisc,dp1000-pinctrl"; ++ reg = <0x0 0x11081000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #pinctrl-cells = <2>; ++ pinctrl-single,register-width = <32>; ++ pinctrl-single,function-mask = <0x3ff>; ++ pinctrl-use-default; ++ ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +new file mode 100644 +index 000000000000..a74714629566 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +@@ -0,0 +1,60 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000.dts" ++#include "dp1000-mo-pinctrl.dtsi" ++#include ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ ++ rtc@32 { ++ compatible = "whwave,sd3078"; ++ reg = <0x32>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch b/SPECS/linux-lts-kmhv2/0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch new file mode 100644 index 0000000000..ee76518537 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch @@ -0,0 +1,111 @@ +From b9ce7c71ab1aae741d95ad74bd380256a79a7de3 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 9 Sep 2025 15:45:52 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: Move mmc0 node from SoC to + board DTS + +The mmc0 node (mmc-spi-slot) is a board-level peripheral +specific to the UltraRISC DP1000 EVB V1.0, not part of the +base SoC. Move it from the SoC-level dp1000.dts to the +board-specific dp1000-evb-v1.dts to maintain proper device +tree hierarchy between SoC core and board-specific components. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/c719099661103786c877036840568c38f3d083a9 +Signed-off-by: Han Gao +--- + .../boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 9 +++++++-- + arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 16 +++++++++++----- + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 15 +++------------ + 3 files changed, 21 insertions(+), 19 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +index be898b6df6fb..e82fcf2901ab 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +@@ -1,3 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ + #include + + / { +@@ -63,8 +68,8 @@ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) + + uart0_pins: uart0_pins { + pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) + >; + + pinconf-pins = < +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +index 5ec9a39e8c34..34622a33e63b 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +@@ -1,9 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0 + /* +-* SPDX-License-Identifier: GPL-2.0+ +-* +-* Copyright (c) 2019-2022 UltraRisc,Inc +-* +-*/ ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ + + #include "dp1000.dts" + #include "dp1000-evb-pinctrl.dtsi" +@@ -27,6 +25,14 @@ &i2c3 { + &spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; ++ ++ mmc0: mmc@0 { ++ compatible = "mmc-spi-slot"; ++ spi-max-frequency = <15625000>; ++ reg = <0x00>; ++ voltage-ranges = <3300 3300>; ++ disable-wp; ++ }; + }; + + &spi1 { +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +index 3eb811f73aa8..23a983d6a4c8 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +@@ -1,9 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0 + /* +-* SPDX-License-Identifier: GPL-2.0+ +-* +-* Copyright (c) 2019-2022 UltraRisc,Inc +-* +-*/ ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ + + /dts-v1/; + +@@ -261,13 +259,6 @@ spi0: spi@20320000 { + clock-names = "device_clk"; + num-cs = <3>; + spi-max-frequency = <62500000>; +- mmc0: mmc@0 { +- compatible = "mmc-spi-slot"; +- spi-max-frequency = <15625000>; +- reg = <0x00>; +- voltage-ranges = <3300 3300>; +- disable-wp; +- }; + }; + + spi1: spi@20420000 { +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0452-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch b/SPECS/linux-lts-kmhv2/0452-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch deleted file mode 100644 index 0bc0730651..0000000000 --- a/SPECS/linux-lts-kmhv2/0452-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 9990048297fff986d79fe3f64e82e5f0856461e4 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Wed, 12 Nov 2025 15:43:27 +0800 -Subject: [PATCH 452/467] RVCK: riscv: pinctrl: ultrarisc: Implement pin - configuration support - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Update ur_pin_config_set() to use the new configuration handling logic. -This allows the driver to properly handle standard Linux kernel pin -configuration parameters such as PIN_CONFIG_BIAS_PULL_UP, -PIN_CONFIG_BIAS_PULL_DOWN, etc. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/d094389a972a4b03d04b77a47c19f5c9c9fb0627 -Signed-off-by: Han Gao ---- - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 + - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 83 +++++++++++++++++-- - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 2 +- - 3 files changed, 77 insertions(+), 9 deletions(-) - -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -index 217f671fe63a..6a7496a465d8 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -86,6 +86,7 @@ static struct ur_pinctrl_match_data ur_dp1000_match_data = { - .pins = ur_dp1000_pins, - .npins = ARRAY_SIZE(ur_dp1000_pins), - .offset = 0x2c0, -+ .num_ports = 5, - .ports = { - {"A", 16, 0x2c0, 0x310}, - {"B", 8, 0x2c4, 0x318}, -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -index 667d59e0ac6e..edaeca881af7 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -326,6 +326,58 @@ static const struct pinmux_ops ur_pinmux_ops = { - - #define UR_CONF_BIT_PER_PIN (4) - #define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) -+ -+static int ur_pin_num_to_port_pin(const struct ur_pinctrl_match_data *match_data, -+ struct ur_pin_val *pin_val, u32 pin_num) -+{ -+ const struct ur_port_desc *port_desc; -+ -+ for (int i = 0; i < match_data->num_ports; i++) { -+ port_desc = &match_data->ports[i]; -+ if (pin_num < port_desc->npins) { -+ pin_val->port = i; -+ pin_val->pin = pin_num; -+ pin_val->conf = 0; -+ return 0; -+ } -+ pin_num -= port_desc->npins; -+ } -+ return -EINVAL; -+} -+ -+static int ur_config_to_pin_val(struct ur_pinctrl *pin_ctrl, -+ struct ur_pin_val *pin_vals, -+ unsigned long *config) -+{ -+ enum pin_config_param param = pinconf_to_config_param(*config); -+ u32 arg = pinconf_to_config_argument(*config); -+ -+ dev_dbg(pin_ctrl->dev, "%s(%d): config_to_pin_val: param=%d, arg=0x%x\n", -+ __func__, __LINE__, param, arg); -+ -+ switch (param) { -+ case PIN_CONFIG_BIAS_DISABLE: -+ pin_vals->conf &= ~UR_BIAS_MASK; -+ break; -+ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: -+ pin_vals->conf &= ~(UR_PULL_DOWN | UR_PULL_UP); -+ break; -+ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: -+ case PIN_CONFIG_BIAS_PULL_DOWN: -+ pin_vals->conf |= UR_PULL_DOWN; -+ break; -+ case PIN_CONFIG_BIAS_PULL_UP: -+ pin_vals->conf |= UR_PULL_UP; -+ break; -+ case PIN_CONFIG_DRIVE_PUSH_PULL: -+ case PIN_CONFIG_PERSIST_STATE: -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ return 0; -+} -+ - static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) - { - const struct ur_port_desc *port_desc; -@@ -334,8 +386,11 @@ static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_v - u32 val, conf; - - port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; -+ dev_dbg(pin_ctrl->dev, "set pinconf port=%d pin=%d conf=0x%x\n", -+ pin_vals->port, pin_vals->pin, pin_vals->conf); - reg = pin_ctrl->base + port_desc->conf_offset; -- dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); -+ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, conf_offset=0x%x, reg=0x%llx\n", -+ (u64)pin_ctrl->base, port_desc->conf_offset, (u64)reg); - reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; - dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); - -@@ -367,16 +422,28 @@ static int ur_pin_config_set(struct pinctrl_dev *pctldev, - unsigned long *configs, - unsigned int num_configs) - { -- struct ur_pin_val *pin_conf; -+ struct ur_pin_val pin_val; - struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ int ret; -+ -+ ret = ur_pin_num_to_port_pin(ur_pinctrl->match_data, &pin_val, pin); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "invalid pin number %d\n", pin); -+ return ret; -+ } -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d, port=%d, pin=%d\n", -+ __func__, __LINE__, pin, num_configs, pin_val.port, pin_val.pin); - -- dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", -- __func__, __LINE__, pin, num_configs); -- pin_conf = (struct ur_pin_val *)configs; - for (int i = 0; i < num_configs; i++) { -- dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -- i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -- ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ ret = ur_config_to_pin_val(ur_pinctrl, &pin_val, &configs[i]); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "invalid config 0x%lx\n", configs[i]); -+ return ret; -+ } -+ -+ dev_dbg(pctldev->dev, "%s(%d): port=%d, pin=%d, conf=0x%x\n", -+ __func__, __LINE__, pin_val.port, pin_val.pin, pin_val.conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_val); - } - return 0; - } -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -index eec621bf8b05..728b2111def0 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -@@ -50,7 +50,7 @@ struct ur_pinctrl_match_data { - const struct pinctrl_pin_desc *pins; - u32 npins; - u32 offset; -- //u32 conf_offset[]; -+ u32 num_ports; - struct ur_port_desc ports[]; - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch b/SPECS/linux-lts-kmhv2/0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch new file mode 100644 index 0000000000..2e0d7ad5ce --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch @@ -0,0 +1,77 @@ +From 2e69e921113ca412333654bea99e8cde384f3780 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Thu, 18 Sep 2025 10:44:01 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dp1000: plic: add plic early init supports + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +------------------------------------------------- + +Add PLIC early init supports and remove invalid +timer nodes in dp1000.dts. + +Signed-off-by: Jia Wang +From: https://github.com/RVCK-Project/rvck/commit/9e4cfbdf46fad772cc002c53b9e295cda600e9c5 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 25 ++---------------------- + drivers/irqchip/irq-sifive-plic.c | 1 + + 2 files changed, 3 insertions(+), 23 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +index 23a983d6a4c8..4a2dae602693 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +@@ -164,6 +164,7 @@ device_clk: device_clk { + clock-frequency = <62500000>; + #clock-cells = <0>; + }; ++ + csr_clk: csr_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; +@@ -333,29 +334,7 @@ wdt0: watchdog@20210000 { + interrupts = <33>; + clocks = <&device_clk>; + }; +- +- timer0: timer@20220000 { +- compatible = "snps,dw-apb-timer"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x20220000 0x0 0x100>; +- clocks = <&device_clk>; +- interrupt-parent = <0x01>; +- interrupts = <35>; +- status = "okay"; +- }; +- +- timer1: timer@20230000 { +- compatible = "snps,dw-apb-timer"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x20230000 0x0 0x100>; +- clocks = <&device_clk>; +- interrupt-parent = <0x01>; +- interrupts = <36>; +- status = "okay"; +- }; +- ++ + gpio: gpio@20200000 { + compatible = "snps,dw-apb-gpio"; + #address-cells = <1>; +diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c +index 70058871d2fb..007a4668f9e5 100644 +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -846,3 +846,4 @@ static int __init plic_early_probe(struct device_node *node, + } + + IRQCHIP_DECLARE(riscv, "allwinner,sun20i-d1-plic", plic_early_probe); ++IRQCHIP_DECLARE(ultrarisc_dp1000_plic, "ultrarisc,dp1000-plic", plic_early_probe); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0453-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch b/SPECS/linux-lts-kmhv2/0453-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch deleted file mode 100644 index 1eed92849d..0000000000 --- a/SPECS/linux-lts-kmhv2/0453-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch +++ /dev/null @@ -1,364 +0,0 @@ -From fbad2c8916d16de5ce5963b7dcc776529371ad4c Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 18 Nov 2025 13:48:49 +0800 -Subject: [PATCH 453/467] RVCK: riscv: dts: dp1000: add dts/dtsi for Milk-V - Titan board based on UltraRISC DP1000 SoC - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Add dp1000-titan-v1.dts and dp1000-titan-pinctrl.dtsi for the Milk-V Titan -board. The Titan board is designed by Milk-V and is based on the UltraRISC -DP1000 SoC. These device tree files provide the initial support for the -board, including pinctrl and basic peripheral configuration. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/edab885e252d0442ccf52b2b554934138b82b2ec -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 1 + - .../dts/ultrarisc/dp1000-titan-pinctrl.dtsi | 173 ++++++++++++++++++ - .../boot/dts/ultrarisc/dp1000-titan-v1.dts | 139 ++++++++++++++ - 3 files changed, 313 insertions(+) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index 22c03b44b2f8..df8efe1a3ed7 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-titan-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi -new file mode 100644 -index 000000000000..35429e539832 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi -@@ -0,0 +1,173 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart3_pins: uart3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 6 UR_FUNC0 -+ UR_DP1000_IOMUX_C 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ UR_DP1000_IOMUX_A 4 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ gpios_pin: gpios_pin { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 10 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 11 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 14 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 15 UR_FUNC_DEF -+ -+ UR_DP1000_IOMUX_B 0 UR_FUNC_DEF -+ UR_DP1000_IOMUX_B 1 UR_FUNC_DEF -+ UR_DP1000_IOMUX_B 2 UR_FUNC_DEF -+ -+ UR_DP1000_IOMUX_D 6 UR_FUNC_DEF -+ UR_DP1000_IOMUX_D 7 UR_FUNC_DEF -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 10 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 11 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 14 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 15 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ -+ UR_DP1000_IOMUX_B 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts -new file mode 100644 -index 000000000000..2cbdfa2ad813 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts -@@ -0,0 +1,139 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include "dp1000-titan-pinctrl.dtsi" -+#include -+#include -+#include -+#include -+ -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS0,115200"; -+ stdout-path = &uart0; -+ }; -+ -+ gpio-poweroff { -+ compatible = "gpio-poweroff"; -+ gpios = <&portb 0 GPIO_ACTIVE_LOW>; -+ active-delay-ms = <100>; -+ line-name = "power-off"; -+ status = "okay"; -+ }; -+ -+ gpio-restart { -+ compatible = "gpio-restart"; -+ gpios = <&portb 1 GPIO_ACTIVE_LOW>; -+ active-delay-ms = <100>; -+ line-name = "reset-system"; -+ status = "okay"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ -+ key-wakeup { -+ label = "Wake-Up"; -+ gpios = <&porta 14 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ linux,input-type = ; -+ debounce-interval = <10>; -+ wakeup-source; -+ wakeup-event-action = ; -+ }; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ -+ rtc@68 { -+ compatible = "st,m41t11"; -+ reg = <0x68>; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart3_pins>; -+}; -+ -+&porta { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpios_pin>; -+ -+ i2c1-mux-hog { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ /* LOW: DCDC(U6) connect MCU(EC) -+ * HIGH: DCDC(U6) connect CPU -+ */ -+ output-low; -+ line-name = "gpio-mux-dcdc"; -+ }; -+ -+ i2c3-mux-hog { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_LOW>; -+ /* LOW: CPU i2c3 connect nvme -+ * HIGH: CPU i2c3 connect pciex16 -+ */ -+ output-low; -+ line-name = "gpio-mux-i2c3"; -+ }; -+ -+ uart0-mux-hog { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ /* LOW: uart_debug connect BMC -+ * HIGH: uart_debug connect CPU -+ */ -+ output-high; -+ line-name = "gpio-mux-debug"; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0454-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch b/SPECS/linux-lts-kmhv2/0454-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch deleted file mode 100644 index 600e84fb7f..0000000000 --- a/SPECS/linux-lts-kmhv2/0454-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch +++ /dev/null @@ -1,77 +0,0 @@ -From a5bc9efc302578399318b126b9ad08dc8f2925c9 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Mon, 23 Feb 2026 14:35:29 +0800 -Subject: [PATCH 454/467] REVYSR: pinctrl: ultrarisc: cleanup probe&remove - -Signed-off-by: Han Gao ---- - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 - - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 22 +++---------------- - 2 files changed, 3 insertions(+), 20 deletions(-) - -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -index 6a7496a465d8..0ead138c9d1f 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -117,7 +117,6 @@ static struct platform_driver ur_pinctrl_driver = { - .of_match_table = ur_pinctrl_of_match, - }, - .probe = ur_pinctrl_probe, -- .remove = ur_pinctrl_remove, - }; - - module_platform_driver(ur_pinctrl_driver); -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -index edaeca881af7..cdd7160f3183 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -514,8 +514,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); - if (!ur_pinctrl) { - dev_err(&pdev->dev, "pinctrl alloc failed\n"); -- ret = -ENOMEM; -- goto free_pinctrl_desc; -+ return -ENOMEM; - } - struct resource *res; - -@@ -524,8 +523,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(ur_pinctrl->base)) { - dev_err(&pdev->dev, "get ioremap resource failed\n"); -- ret = -EINVAL; -- goto free_pinctrl_desc; -+ return -EINVAL; - } - dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); - ur_pinctrl_desc->name = dev_name(&pdev->dev); -@@ -546,25 +544,11 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl, &ur_pinctrl->pctl_dev); - if (ret) { - dev_err(&pdev->dev, "pinctrl register failed\n"); -- goto free_pinctrl; -+ return ret; - } - - platform_set_drvdata(pdev, ur_pinctrl); - - return pinctrl_enable(ur_pinctrl->pctl_dev); -- --free_pinctrl: -- devm_kfree(&pdev->dev, ur_pinctrl); --free_pinctrl_desc: -- devm_kfree(&pdev->dev, ur_pinctrl_desc); -- return ret; - } - -- --void ur_pinctrl_remove(struct platform_device *pdev) --{ -- struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); -- -- if (ur_pinctrl->pctl_dev) -- devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); --} --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch b/SPECS/linux-lts-kmhv2/0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch new file mode 100644 index 0000000000..87e90bc15e --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch @@ -0,0 +1,85 @@ +From c95a87c3fe519649f8470396461cd19be68bb138 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Mon, 10 Nov 2025 16:11:12 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: Move chosen node from common + to board-specific DTS + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +-------------------------------- + +This commit moves the chosen node configuration from the +common dp1000.dts file to the respective board-specific +DTS files. + +This change allows each board to specify its own console +configuration while keeping the common SoC definitions clean. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/db5745be89ee881ff18a7ded0bcff1c2f495becf +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 7 +++++++ + arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 7 +++++++ + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 7 +------ + 3 files changed, 15 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +index 34622a33e63b..34d024a083fc 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +@@ -7,6 +7,13 @@ + #include "dp1000-evb-pinctrl.dtsi" + #include + ++/ { ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS1,115200"; ++ stdout-path = &uart1; ++ }; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +index a74714629566..8c532e5b71a3 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +@@ -7,6 +7,13 @@ + #include "dp1000-mo-pinctrl.dtsi" + #include + ++/ { ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS0,115200"; ++ stdout-path = &uart0; ++ }; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +index 4a2dae602693..128293c0af1f 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +@@ -10,12 +10,7 @@ / { + #size-cells = <0x02>; + compatible = "ultrarisc,dp1000"; + model = "ultrarisc,dp1000"; +- +- chosen { +- bootargs = "earlycon=sbi console=ttyS1,115200"; +- stdout-path = &uart1; +- }; +- ++ + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0455-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch b/SPECS/linux-lts-kmhv2/0455-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch deleted file mode 100644 index 02ee603e78..0000000000 --- a/SPECS/linux-lts-kmhv2/0455-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch +++ /dev/null @@ -1,46 +0,0 @@ -From e8065f872b91db0f8430308a5dd01266928a98d9 Mon Sep 17 00:00:00 2001 -From: U2FsdGVkX1 -Date: Sun, 29 Mar 2026 15:31:14 +0000 -Subject: [PATCH 455/467] REVYSR: riscv: dp1000: dts: use ultrarisc,dp1000-pcie - for PCIe nodes - -Signed-off-by: U2FsdGVkX1 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index a25e87e15553..78e0cda1fcb9 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -436,7 +436,7 @@ dmac: dma-controller@39000000 { - }; - - pcie_x16: pcie@21000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; -@@ -462,7 +462,7 @@ pcie_x16: pcie@21000000 { - }; - - pcie_x4a: pcie@23000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; -@@ -488,7 +488,7 @@ pcie_x4a: pcie@23000000 { - }; - - pcie_x4b: pcie@24000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch b/SPECS/linux-lts-kmhv2/0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch new file mode 100644 index 0000000000..47458b4dd9 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch @@ -0,0 +1,677 @@ +From efed87f8a357dd6937ae5011627de96daf2e7029 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 11 Nov 2025 17:03:37 +0800 +Subject: [RUYI PATCH] RVCK: dts: riscv: ultrarisc: Refactor DP1000 device tree + files + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +-------------------------------- + +Add gpio-ranges property to all gpio/portX nodes. +This property maps GPIO lines to pin controller pins, +ensuring proper GPIO pin allocation and management. + +Convert dp1000.dts to a common include file (dp1000.dtsi) and update +the board-specific DTS files to include it. This refactoring allows +for better code reuse across different DP1000-based boards (EVB, MO, +and Titan variants) while maintaining board-specific configurations. + +The changes include: +- Renaming dp1000.dts to dp1000.dtsi +- Updating board-specific DTS files to include the common .dtsi +- Adjusting Makefile to reflect these changes +- Updating pinctrl files for all board variants + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/f9d4926fccee70f72d11e11dfa11b99f59caa947 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 1 - + .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 261 +++++++++--------- + .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 1 - + .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 261 +++++++++--------- + .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 1 - + .../dts/ultrarisc/{dp1000.dts => dp1000.dtsi} | 15 + + 6 files changed, 263 insertions(+), 277 deletions(-) + rename arch/riscv/boot/dts/ultrarisc/{dp1000.dts => dp1000.dtsi} (96%) + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index 9eac56549340..22c03b44b2f8 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,4 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +index e82fcf2901ab..e2c09d5bdb20 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +@@ -4,143 +4,130 @@ + */ + + #include ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 12 UR_FUNC0 ++ UR_DP1000_IOMUX_A 13 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 6 UR_FUNC0 ++ UR_DP1000_IOMUX_B 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 0 UR_FUNC0 ++ UR_DP1000_IOMUX_C 1 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 2 UR_FUNC0 ++ UR_DP1000_IOMUX_C 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 8 UR_FUNC1 ++ UR_DP1000_IOMUX_A 9 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 4 UR_FUNC0 ++ UR_DP1000_IOMUX_B 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 4 UR_FUNC0 ++ UR_DP1000_IOMUX_C 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_D 0 UR_FUNC1 ++ UR_DP1000_IOMUX_D 1 UR_FUNC1 ++ UR_DP1000_IOMUX_D 2 UR_FUNC1 ++ UR_DP1000_IOMUX_D 3 UR_FUNC1 ++ UR_DP1000_IOMUX_D 4 UR_FUNC1 ++ UR_DP1000_IOMUX_D 5 UR_FUNC1 ++ UR_DP1000_IOMUX_D 6 UR_FUNC1 ++ UR_DP1000_IOMUX_D 7 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; + +-/ { +- +- soc { +- pmx0: pinmux@11081000 { +- compatible = "ultrarisc,dp1000-pinctrl"; +- reg = <0x0 0x11081000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <2>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x3ff>; +- pinctrl-use-default; +- +- i2c0_pins: i2c0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c1_pins: i2c1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c2_pins: i2c2_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c3_pins: i2c3_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart0_pins: uart0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart1_pins: uart1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart2_pins: uart2_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- spi0_pins: spi0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- spi1_pins: spi1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- }; ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 0 UR_FUNC0 ++ UR_DP1000_IOMUX_A 1 UR_FUNC0 ++ UR_DP1000_IOMUX_A 2 UR_FUNC0 ++ UR_DP1000_IOMUX_A 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; + }; + }; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +index 34d024a083fc..46fe457b5f52 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +@@ -3,7 +3,6 @@ + * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +-#include "dp1000.dts" + #include "dp1000-evb-pinctrl.dtsi" + #include + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +index e82fcf2901ab..85b013f66bbd 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +@@ -4,143 +4,130 @@ + */ + + #include ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 12 UR_FUNC0 ++ UR_DP1000_IOMUX_A 13 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 6 UR_FUNC0 ++ UR_DP1000_IOMUX_B 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 0 UR_FUNC0 ++ UR_DP1000_IOMUX_C 1 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 2 UR_FUNC0 ++ UR_DP1000_IOMUX_C 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 8 UR_FUNC1 ++ UR_DP1000_IOMUX_A 9 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 4 UR_FUNC0 ++ UR_DP1000_IOMUX_B 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 4 UR_FUNC0 ++ UR_DP1000_IOMUX_C 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_D 0 UR_FUNC1 ++ UR_DP1000_IOMUX_D 1 UR_FUNC1 ++ UR_DP1000_IOMUX_D 2 UR_FUNC1 ++ UR_DP1000_IOMUX_D 3 UR_FUNC1 ++ UR_DP1000_IOMUX_D 4 UR_FUNC1 ++ UR_DP1000_IOMUX_D 5 UR_FUNC1 ++ UR_DP1000_IOMUX_D 6 UR_FUNC1 ++ UR_DP1000_IOMUX_D 7 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; + +-/ { +- +- soc { +- pmx0: pinmux@11081000 { +- compatible = "ultrarisc,dp1000-pinctrl"; +- reg = <0x0 0x11081000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <2>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x3ff>; +- pinctrl-use-default; +- +- i2c0_pins: i2c0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c1_pins: i2c1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c2_pins: i2c2_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c3_pins: i2c3_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart0_pins: uart0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart1_pins: uart1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart2_pins: uart2_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- spi0_pins: spi0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- spi1_pins: spi1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- }; ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 0 UR_FUNC0 ++ UR_DP1000_IOMUX_A 1 UR_FUNC0 ++ UR_DP1000_IOMUX_A 2 UR_FUNC0 ++ UR_DP1000_IOMUX_A 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; + }; + }; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +index 8c532e5b71a3..dc057cbaf59b 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +@@ -3,7 +3,6 @@ + * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +-#include "dp1000.dts" + #include "dp1000-mo-pinctrl.dtsi" + #include + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +similarity index 96% +rename from arch/riscv/boot/dts/ultrarisc/dp1000.dts +rename to arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +index 128293c0af1f..a25e87e15553 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +@@ -330,6 +330,17 @@ wdt0: watchdog@20210000 { + clocks = <&device_clk>; + }; + ++ pmx0: pinmux@11081000 { ++ compatible = "ultrarisc,dp1000-pinctrl"; ++ reg = <0x0 0x11081000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #pinctrl-cells = <2>; ++ pinctrl-single,register-width = <32>; ++ pinctrl-single,function-mask = <0x3ff>; ++ pinctrl-use-default; ++ }; ++ + gpio: gpio@20200000 { + compatible = "snps,dw-apb-gpio"; + #address-cells = <1>; +@@ -349,6 +360,7 @@ porta: gpio-port@0 { + #interrupt-cells = <2>; + interrupt-parent = <0x01>; + interrupts = <34>; ++ gpio-ranges = <&pmx0 0 0 16>; + }; + + portb: gpio-port@1 { +@@ -357,6 +369,7 @@ portb: gpio-port@1 { + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 16 0 8>; + }; + + portc: gpio-port@2 { +@@ -365,6 +378,7 @@ portc: gpio-port@2 { + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 24 0 8>; + }; + + portd: gpio-port@3 { +@@ -373,6 +387,7 @@ portd: gpio-port@3 { + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 32 0 8>; + }; + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch b/SPECS/linux-lts-kmhv2/0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch new file mode 100644 index 0000000000..ebf2263e4c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch @@ -0,0 +1,166 @@ +From bae8242b84b2c9409608fced96e355aa782dfcd8 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Wed, 12 Nov 2025 15:43:27 +0800 +Subject: [RUYI PATCH] RVCK: riscv: pinctrl: ultrarisc: Implement pin + configuration support + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +-------------------------------- + +Update ur_pin_config_set() to use the new configuration handling logic. +This allows the driver to properly handle standard Linux kernel pin +configuration parameters such as PIN_CONFIG_BIAS_PULL_UP, +PIN_CONFIG_BIAS_PULL_DOWN, etc. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/d094389a972a4b03d04b77a47c19f5c9c9fb0627 +Signed-off-by: Han Gao +--- + .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 + + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 83 +++++++++++++++++-- + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 2 +- + 3 files changed, 77 insertions(+), 9 deletions(-) + +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +index 217f671fe63a..6a7496a465d8 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +@@ -86,6 +86,7 @@ static struct ur_pinctrl_match_data ur_dp1000_match_data = { + .pins = ur_dp1000_pins, + .npins = ARRAY_SIZE(ur_dp1000_pins), + .offset = 0x2c0, ++ .num_ports = 5, + .ports = { + {"A", 16, 0x2c0, 0x310}, + {"B", 8, 0x2c4, 0x318}, +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +index 667d59e0ac6e..edaeca881af7 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +@@ -326,6 +326,58 @@ static const struct pinmux_ops ur_pinmux_ops = { + + #define UR_CONF_BIT_PER_PIN (4) + #define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) ++ ++static int ur_pin_num_to_port_pin(const struct ur_pinctrl_match_data *match_data, ++ struct ur_pin_val *pin_val, u32 pin_num) ++{ ++ const struct ur_port_desc *port_desc; ++ ++ for (int i = 0; i < match_data->num_ports; i++) { ++ port_desc = &match_data->ports[i]; ++ if (pin_num < port_desc->npins) { ++ pin_val->port = i; ++ pin_val->pin = pin_num; ++ pin_val->conf = 0; ++ return 0; ++ } ++ pin_num -= port_desc->npins; ++ } ++ return -EINVAL; ++} ++ ++static int ur_config_to_pin_val(struct ur_pinctrl *pin_ctrl, ++ struct ur_pin_val *pin_vals, ++ unsigned long *config) ++{ ++ enum pin_config_param param = pinconf_to_config_param(*config); ++ u32 arg = pinconf_to_config_argument(*config); ++ ++ dev_dbg(pin_ctrl->dev, "%s(%d): config_to_pin_val: param=%d, arg=0x%x\n", ++ __func__, __LINE__, param, arg); ++ ++ switch (param) { ++ case PIN_CONFIG_BIAS_DISABLE: ++ pin_vals->conf &= ~UR_BIAS_MASK; ++ break; ++ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: ++ pin_vals->conf &= ~(UR_PULL_DOWN | UR_PULL_UP); ++ break; ++ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: ++ case PIN_CONFIG_BIAS_PULL_DOWN: ++ pin_vals->conf |= UR_PULL_DOWN; ++ break; ++ case PIN_CONFIG_BIAS_PULL_UP: ++ pin_vals->conf |= UR_PULL_UP; ++ break; ++ case PIN_CONFIG_DRIVE_PUSH_PULL: ++ case PIN_CONFIG_PERSIST_STATE: ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ return 0; ++} ++ + static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) + { + const struct ur_port_desc *port_desc; +@@ -334,8 +386,11 @@ static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_v + u32 val, conf; + + port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; ++ dev_dbg(pin_ctrl->dev, "set pinconf port=%d pin=%d conf=0x%x\n", ++ pin_vals->port, pin_vals->pin, pin_vals->conf); + reg = pin_ctrl->base + port_desc->conf_offset; +- dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); ++ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, conf_offset=0x%x, reg=0x%llx\n", ++ (u64)pin_ctrl->base, port_desc->conf_offset, (u64)reg); + reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; + dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); + +@@ -367,16 +422,28 @@ static int ur_pin_config_set(struct pinctrl_dev *pctldev, + unsigned long *configs, + unsigned int num_configs) + { +- struct ur_pin_val *pin_conf; ++ struct ur_pin_val pin_val; + struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ int ret; ++ ++ ret = ur_pin_num_to_port_pin(ur_pinctrl->match_data, &pin_val, pin); ++ if (ret < 0) { ++ dev_err(pctldev->dev, "invalid pin number %d\n", pin); ++ return ret; ++ } ++ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d, port=%d, pin=%d\n", ++ __func__, __LINE__, pin, num_configs, pin_val.port, pin_val.pin); + +- dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", +- __func__, __LINE__, pin, num_configs); +- pin_conf = (struct ur_pin_val *)configs; + for (int i = 0; i < num_configs; i++) { +- dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", +- i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); +- ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); ++ ret = ur_config_to_pin_val(ur_pinctrl, &pin_val, &configs[i]); ++ if (ret < 0) { ++ dev_err(pctldev->dev, "invalid config 0x%lx\n", configs[i]); ++ return ret; ++ } ++ ++ dev_dbg(pctldev->dev, "%s(%d): port=%d, pin=%d, conf=0x%x\n", ++ __func__, __LINE__, pin_val.port, pin_val.pin, pin_val.conf); ++ ur_set_pin_conf(ur_pinctrl, &pin_val); + } + return 0; + } +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +index eec621bf8b05..728b2111def0 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +@@ -50,7 +50,7 @@ struct ur_pinctrl_match_data { + const struct pinctrl_pin_desc *pins; + u32 npins; + u32 offset; +- //u32 conf_offset[]; ++ u32 num_ports; + struct ur_port_desc ports[]; + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0456-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch b/SPECS/linux-lts-kmhv2/0456-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch deleted file mode 100644 index cff95295c4..0000000000 --- a/SPECS/linux-lts-kmhv2/0456-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch +++ /dev/null @@ -1,451 +0,0 @@ -From 02e4c1a0f94cd44c90eee6410e5cf4484bb234a2 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 13 Feb 2025 15:50:12 +0800 -Subject: [PATCH 456/467] ULTRARISC: hwmon: add corepvt driver of UltraRISC - DP1000 - -From: https://github.com/ultrarisc/linux-6.8.0/commit/2cb818e1179844847d3be752b978a4ee7e633bc3 - -UltraRISC Corepvt driver supports cluster voltage -and core temperature detection - -Signed-off-by: Jia Wang -Signed-off-by: Han Gao ---- - drivers/hwmon/Kconfig | 9 + - drivers/hwmon/Makefile | 1 + - drivers/hwmon/corepvt-ultrarisc.c | 390 ++++++++++++++++++++++++++++++ - 3 files changed, 400 insertions(+) - create mode 100644 drivers/hwmon/corepvt-ultrarisc.c - -diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig -index 2a71b6e834b0..2a44030c7796 100644 ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -503,6 +503,15 @@ config SENSORS_CHIPCAP2 - To compile this driver as a module, choose M here: the module - will be called chipcap2. - -+config SENSORS_COREPVT_ULTRARISC -+ tristate "UltraRISC Core Voltage, Temperature sensor driver" -+ help -+ If you say yes here you get support for UltraRISC Core PVT sensor -+ embedded into the SoC. -+ -+ This driver can also be built as a module. If so, the module will be -+ called corepvt-ultrarisc. -+ - config SENSORS_CORSAIR_CPRO - tristate "Corsair Commander Pro controller" - depends on HID -diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile -index 73b2abdcc6dd..6cf5fac80b7b 100644 ---- a/drivers/hwmon/Makefile -+++ b/drivers/hwmon/Makefile -@@ -61,6 +61,7 @@ obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o - obj-$(CONFIG_SENSORS_BT1_PVT) += bt1-pvt.o - obj-$(CONFIG_SENSORS_CGBC) += cgbc-hwmon.o - obj-$(CONFIG_SENSORS_CHIPCAP2) += chipcap2.o -+obj-$(CONFIG_SENSORS_COREPVT_ULTRARISC) += corepvt-ultrarisc.o - obj-$(CONFIG_SENSORS_CORETEMP) += coretemp.o - obj-$(CONFIG_SENSORS_CORSAIR_CPRO) += corsair-cpro.o - obj-$(CONFIG_SENSORS_CORSAIR_PSU) += corsair-psu.o -diff --git a/drivers/hwmon/corepvt-ultrarisc.c b/drivers/hwmon/corepvt-ultrarisc.c -new file mode 100644 -index 000000000000..3674eedefbda ---- /dev/null -+++ b/drivers/hwmon/corepvt-ultrarisc.c -@@ -0,0 +1,390 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Driver for UltraRISC Core PVT -+ * -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define COREPVT_CHL_OFFSET 0x1000 -+#define COREPVT_REG_CIR 0x0 -+#define COREPVT_REG_PSCR 0x04 -+#define COREPVT_REG_CFDR 0x08 -+#define COREPVT_REG_DOR 0x0C -+#define COREPVT_REG_ICR 0x10 -+#define COREPVT_REG_IER 0x14 -+#define COREPVT_REG_IMSR 0x18 -+#define COREPVT_REG_IRSR 0x1C -+ -+#define PVT_MAX_CHANNEL 64 -+#define PVT_TRIM_DEFAULT 0x7 -+ -+struct corepvt_channel_config { -+ const char *label; -+ u32 trim; -+}; -+ -+struct corepvt_cal_data { -+ u32 val_offset; -+ u32 val_lsb; -+}; -+ -+struct corepvt_data { -+ const struct hwmon_chip_info *chip_info; -+ u64 temp_chl_mask; -+ u64 vol_chl_mask; -+}; -+ -+struct corepvt_hwmon { -+ struct device *dev; -+ struct device *hwmon; -+ -+ void __iomem *regs; -+ int irq; -+ int clk_freq; -+ int channels; -+ const struct hwmon_chip_info *chip_info; -+ struct corepvt_channel_config config[PVT_MAX_CHANNEL]; -+ const struct corepvt_data *pvt_data; -+ raw_spinlock_t lock; -+}; -+ -+#define COREPVT_VOLTAGE_DATA_BASE 2065100 /* 2065.1 */ -+#define COREPVT_VOLTAGE_LSB 1682 /* 1.682 mV */ -+#define COREPVT_TEMP_DATA_BASE 27049000 /* 2704.9 */ -+#define COREPVT_TEMP_LSB 22632 /* 2.2632 Celsius */ -+ -+static int corepvt_read_vol(struct corepvt_hwmon *pvt, -+ int channel, long *val) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ u32 dout; -+ u32 chl_offset = 0; -+ -+ // Assume that the voltage channel is continuous -+ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ *val = ((long)dout * 1000 - COREPVT_VOLTAGE_DATA_BASE) / COREPVT_VOLTAGE_LSB; -+ -+ return 0; -+} -+ -+static int corepvt_read_temp(struct corepvt_hwmon *pvt, -+ int channel, long *val) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ u32 dout; -+ u32 chl_offset = 0; -+ -+ // Assume that the temperature channel is continuous -+ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ *val = ((long)dout * 10000 - COREPVT_TEMP_DATA_BASE) * 1000 / COREPVT_TEMP_LSB; -+ -+ return 0; -+} -+ -+static umode_t corepvt_is_visible(const void *drvdata, enum hwmon_sensor_types type, -+ u32 attr, int channel) -+{ -+ const struct corepvt_hwmon *pvt = drvdata; -+ -+ if (channel >= pvt->channels) -+ return 0; -+ -+ switch (type) { -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_input: -+ case hwmon_in_label: -+ return 0444; -+ } -+ break; -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_input: -+ case hwmon_temp_type: -+ case hwmon_temp_label: -+ return 0444; -+ } -+ break; -+ default: -+ return 0; -+ } -+ -+ return 0; -+} -+ -+static int corepvt_read(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long *val) -+{ -+ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); -+ -+ switch (type) { -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_input: -+ return corepvt_read_vol(pvt, channel, val); -+ } -+ break; -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_type: -+ *val = 1; -+ return 0; -+ case hwmon_temp_input: -+ return corepvt_read_temp(pvt, channel, val); -+ } -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ return -ENODATA; -+} -+ -+static int corepvt_read_string(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, const char **str) -+{ -+ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); -+ u32 chl_offset = 0; -+ -+ switch (type) { -+ case hwmon_in: -+ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); -+ break; -+ case hwmon_temp: -+ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); -+ break; -+ default: -+ return -ENODATA; -+ break; -+ } -+ -+ *str = pvt->config[channel + chl_offset].label; -+ -+ return 0; -+} -+ -+/* -+ * corepvt init process: -+ * 1. config SETUP time, should be 10us, set PSCR register -+ * 2. config CLKIN, should be 4MHz, set CFDR register -+ * 3. (TODO)config interrupt, set ICR/IER/IMSR/IRSR -+ * 4. config TRIM and enable PVT, set CIR -+ */ -+static int corepvt_init(struct corepvt_hwmon *pvt) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ /* -+ * SETUP time 10us = 100KHz -+ * PSCR = CLK_FREQ / 100KHz -+ */ -+ u32 pscr_val = pvt->clk_freq / 100000; -+ /* -+ * CFDR = CLK_FREQ / 4MHz / 2 -+ */ -+ u32 cfdr_val = pvt->clk_freq / 8000000; -+ /* -+ * CIR: -+ * bit[0]: PU_VTDC, set 1 to enable pvt -+ * bit[5:2]: TRIM -+ */ -+ u32 cir_val; -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ for (int i = 0; i < pvt->channels; i++) { -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * i; -+ cir_val = (pvt->config[i].trim << 2) | 0x01; -+ writel_relaxed(pscr_val, chl_base + COREPVT_REG_PSCR); -+ writel_relaxed(cfdr_val, chl_base + COREPVT_REG_CFDR); -+ writel_relaxed(cir_val, chl_base + COREPVT_REG_CIR); -+ } -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ return 0; -+} -+ -+static const struct hwmon_ops corepvt_hwmon_ops = { -+ .is_visible = corepvt_is_visible, -+ .read = corepvt_read, -+ .read_string = corepvt_read_string, -+}; -+ -+static int corepvt_probe_channel_from_dt(struct platform_device *pdev, struct corepvt_hwmon *pvt) -+{ -+ struct device_node *child; -+ int ret; -+ u32 channel; -+ const char *label; -+ u32 trim; -+ -+ for_each_child_of_node(pdev->dev.of_node, child) { -+ if (!of_node_name_eq(child, "channel")) -+ continue; -+ -+ ret = of_property_read_u32(child, "reg", &channel); -+ if (ret) -+ goto node_put; -+ -+ ret = of_property_read_string(child, "label", &label); -+ if (ret) -+ goto node_put; -+ -+ if (of_property_present(child, "trim")) -+ of_property_read_u32(child, "trim", &trim); -+ else -+ trim = PVT_TRIM_DEFAULT; -+ -+ pvt->config[channel].label = label; -+ pvt->config[channel].trim = trim; -+ } -+ -+ return 0; -+ -+node_put: -+ of_node_put(child); -+ return ret; -+} -+ -+static int corepvt_probe(struct platform_device *pdev) -+{ -+ struct corepvt_hwmon *pvt; -+ const struct corepvt_data *pvt_data; -+ int ret; -+ -+ pvt = devm_kzalloc(&pdev->dev, sizeof(*pvt), GFP_KERNEL); -+ if (!pvt) -+ return -ENOMEM; -+ -+ pvt->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(pvt->regs)) { -+ dev_err(&pdev->dev, "get ioremap resource failed\n"); -+ ret = -EINVAL; -+ goto free_pvt; -+ } -+ -+ if (device_property_present(&pdev->dev, "interrupts")) -+ pvt->irq = platform_get_irq(pdev, 0); -+ -+ ret = device_property_read_u32(&pdev->dev, "clock-frequency", &pvt->clk_freq); -+ if (ret) { -+ dev_err(&pdev->dev, "get clock-frequency failed\n"); -+ goto free_pvt; -+ } -+ -+ ret = device_property_read_u32(&pdev->dev, "channels", &pvt->channels); -+ if (ret) { -+ dev_err(&pdev->dev, "get channels failed\n"); -+ goto free_pvt; -+ } -+ -+ pvt_data = device_get_match_data(&pdev->dev); -+ if (!pvt_data) { -+ dev_err(&pdev->dev, "No chip info found\n"); -+ ret = -ENODATA; -+ goto free_pvt; -+ } -+ -+ pvt->dev = &pdev->dev; -+ pvt->chip_info = pvt_data->chip_info; -+ pvt->pvt_data = pvt_data; -+ -+ if (pdev->dev.of_node) { -+ ret = corepvt_probe_channel_from_dt(pdev, pvt); -+ if (ret) -+ dev_warn(&pdev->dev, "WARN: probe channel failed\n"); -+ } -+ -+ pvt->hwmon = devm_hwmon_device_register_with_info(&pdev->dev, "corepvt_ultrarisc", -+ pvt, pvt->chip_info, -+ NULL); -+ if (IS_ERR(pvt->hwmon)) { -+ dev_err(&pdev->dev, "register hwmon failed(%ld)\n", PTR_ERR(pvt->hwmon)); -+ ret = -EINVAL; -+ goto free_pvt; -+ } -+ -+ pvt->dev = &pdev->dev; -+ raw_spin_lock_init(&pvt->lock); -+ -+ // Config and enable corepvt -+ corepvt_init(pvt); -+ -+ return 0; -+ -+free_pvt: -+ devm_kfree(&pdev->dev, pvt); -+ return ret; -+} -+ -+static const struct hwmon_channel_info * const ur_dp1000_channel_info[] = { -+ HWMON_CHANNEL_INFO(temp, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL), -+ HWMON_CHANNEL_INFO(in, -+ HWMON_I_INPUT | HWMON_I_LABEL, -+ HWMON_I_INPUT | HWMON_I_LABEL), -+ NULL -+}; -+ -+static const struct hwmon_chip_info ur_dp1000_chip_info = { -+ .ops = &corepvt_hwmon_ops, -+ .info = ur_dp1000_channel_info, -+}; -+ -+static struct corepvt_data ur_dp1000_pvt_data = { -+ .chip_info = &ur_dp1000_chip_info, -+ .temp_chl_mask = GENMASK_ULL(10, 0), -+ .vol_chl_mask = GENMASK_ULL(12, 11) -+}; -+ -+static const struct of_device_id corepvt_of_match[] = { -+ { .compatible = "ultrarisc,dp1000-pvt", .data = &ur_dp1000_pvt_data }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, corepvt_of_match); -+ -+static struct platform_driver corepvt_driver = { -+ .probe = corepvt_probe, -+ .driver = { -+ .name = "corepvt-ultrarisc", -+ .of_match_table = corepvt_of_match -+ } -+}; -+module_platform_driver(corepvt_driver); -+ -+MODULE_AUTHOR("Jia Wang "); -+MODULE_DESCRIPTION("corepvt-ultrarisc driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0457-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch b/SPECS/linux-lts-kmhv2/0457-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch deleted file mode 100644 index 6ef6c25e68..0000000000 --- a/SPECS/linux-lts-kmhv2/0457-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch +++ /dev/null @@ -1,732 +0,0 @@ -From f1121d3ef4c87b156c91316132e05476fc6b3bf4 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Sun, 12 Apr 2026 02:50:03 +0800 -Subject: [PATCH 457/467] RUYI: SYNC: riscv: dts: dp1000: Update dp1000.dtsi - -FROM: https://github.com/ultrarisc/linux-6.8.0/commit/b4a00f2f96a9c7d8d550259292fd19568fe9beec - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 521 ++++++++++++++++++++-- - 1 file changed, 489 insertions(+), 32 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index 78e0cda1fcb9..7b7016618dcd 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -22,121 +22,491 @@ cpu0: cpu@0 { - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache0>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu0_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache0: l2-cache0 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu1: cpu@1 { - device_type = "cpu"; - reg = <0x1>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache1>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu1_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache1: l2-cache1 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu2: cpu@2 { - device_type = "cpu"; - reg = <0x2>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache2>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu2_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache2: l2-cache2 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu3: cpu@3 { - device_type = "cpu"; - reg = <0x3>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache3>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu3_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache3: l2-cache3 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu4: cpu@4 { - device_type = "cpu"; - reg = <0x10>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache4>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu4_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache4: l2-cache4 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu5: cpu@5 { - device_type = "cpu"; - reg = <0x11>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache5>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu5_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache5: l2-cache5 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu6: cpu@6 { - device_type = "cpu"; - reg = <0x12>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; -- - clock-frequency = <2000000000>; -- -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache6>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu6_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache6: l2-cache6 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu7: cpu@7 { - device_type = "cpu"; - reg = <0x13>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache7>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu7_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache7: l2-cache7 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; -+ }; -+ -+ cpu-map { -+ cluster0: cluster0 { -+ core0 { -+ cpu = <&cpu0>; -+ }; -+ core1 { -+ cpu = <&cpu1>; -+ }; -+ core2 { -+ cpu = <&cpu2>; -+ }; -+ core3 { -+ cpu = <&cpu3>; -+ }; -+ -+ cluster0_l3: l3-cache0 { -+ /* L3 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 4MB -+ * per-cluster. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <3>; -+ cache-size = <0x400000>; -+ cache-sets = <0x1000>; -+ cache-unified; -+ next-level-cache = <&l4_cache>; -+ }; -+ }; -+ -+ cluster1: cluster1 { -+ core0 { -+ cpu = <&cpu4>; -+ }; -+ core1 { -+ cpu = <&cpu5>; -+ }; -+ core2 { -+ cpu = <&cpu6>; -+ }; -+ core3 { -+ cpu = <&cpu7>; -+ }; -+ cluster1_l3: l3-cache1 { -+ /* L3 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 4MB -+ * per-cluster. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <3>; -+ cache-size = <0x400000>; -+ cache-sets = <0x1000>; -+ cache-unified; -+ next-level-cache = <&l4_cache>; -+ }; -+ }; - }; - }; - -@@ -150,6 +520,20 @@ soc { - #size-cells = <0x02>; - compatible = "simple-bus"; - ranges; -+ -+ l4_cache: l4-cache { -+ /* L4 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 16MB -+ * shared by the SoC. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <4>; -+ cache-size = <0x1000000>; -+ cache-sets = <0x4000>; -+ cache-unified; -+ }; - - clocks { - compatible = "simple-bus"; -@@ -160,6 +544,12 @@ device_clk: device_clk { - #clock-cells = <0>; - }; - -+ timer_clk: timer_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <50000000>; -+ #clock-cells = <0>; -+ }; -+ - csr_clk: csr_clk { - compatible = "fixed-clock"; - clock-frequency = <250000000>; -@@ -170,35 +560,102 @@ csr_clk: csr_clk { - clint: clint@8000000 { - compatible = "riscv,clint0"; - interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, -- <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -- <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -- <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -- <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -- <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -- <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -- <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; -+ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -+ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -+ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -+ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -+ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -+ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -+ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; - reg = <0x00 0x8000000 0x00 0x100000>; - }; -- -+ - plic: plic@9000000 { - #interrupt-cells = <1>; - #address-cells = <0>; -- phandle = <0x01>; -- compatible = "ultrarisc,dp1000-plic"; -+ compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; - interrupt-controller; - interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, -- <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -- <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -- <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -- <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -- <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -- <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -- <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; -+ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -+ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -+ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -+ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -+ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -+ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -+ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; - reg = <0x00 0x9000000 0x00 0x4000000>; - riscv,max-priority = <0x07>; - riscv,ndev = <160>; - }; -- -+ -+ core_pvt: pvt@110D0000 { -+ compatible = "ultrarisc,dp1000-pvt"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x00 0x110D0000 0x00 0x0000D000>; -+ clock-frequency = <250000000>; -+ channels = <13>; -+ -+ #thermal-sensor-cells = <1>; -+ channel@0 { -+ label = "Core temp0"; -+ reg = <0>; -+ }; -+ -+ channel@1 { -+ label = "Core temp1"; -+ reg = <1>; -+ }; -+ -+ channel@2 { -+ label = "Core temp2"; -+ reg = <2>; -+ }; -+ -+ channel@3 { -+ label = "Core temp3"; -+ reg = <3>; -+ }; -+ -+ channel@4 { -+ label = "Core temp4"; -+ reg = <4>; -+ }; -+ -+ channel@5 { -+ label = "Core temp5"; -+ reg = <5>; -+ }; -+ channel@6 { -+ label = "Core temp6"; -+ reg = <6>; -+ }; -+ channel@7 { -+ label = "Core temp7"; -+ reg = <7>; -+ }; -+ channel@8 { -+ label = "Core temp8"; -+ reg = <8>; -+ }; -+ channel@9 { -+ label = "Core temp9"; -+ reg = <9>; -+ }; -+ channel@10 { -+ label = "Core temp10"; -+ reg = <10>; -+ }; -+ channel@11 { -+ label = "Cluster0 voltage"; -+ reg = <11>; -+ }; -+ channel@12 { -+ label = "Cluster1 voltage"; -+ reg = <12>; -+ }; -+ }; -+ - uart0: serial@20300000 { - interrupt-parent = <0x01>; - interrupts = <17>; -@@ -244,7 +701,7 @@ uart3: serial@20410000 { - }; - - spi0: spi@20320000 { -- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ compatible = "snps,dw-apb-ssi"; - status = "okay"; - #address-cells = <0x01>; - #size-cells = <0x00>; -@@ -258,7 +715,7 @@ spi0: spi@20320000 { - }; - - spi1: spi@20420000 { -- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ compatible = "snps,dw-apb-ssi"; - status = "okay"; - #address-cells = <0x01>; - #size-cells = <0x00>; -@@ -449,11 +906,11 @@ pcie_x16: pcie@21000000 { - num-lanes = <16>; - ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -- max-link-speed = <4>; -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <16>; - interrupt-parent = <&plic>; -- interrupts = <43>, <44>, <45>, <46>, <47>, <48>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <43>, <44>, <45>, <46>, <47>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, - <0x0 0x0 0x0 0x2 &plic 45>, -@@ -475,11 +932,11 @@ pcie_x4a: pcie@23000000 { - num-lanes = <4>; - ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ - max-link-speed = <4>; - interrupt-parent = <&plic>; -- interrupts = <63>, <64>, <65>, <66>, <67>, <68>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <63>, <64>, <65>, <66>, <67>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, - <0x0 0x0 0x0 0x2 &plic 65>, -@@ -501,11 +958,11 @@ pcie_x4b: pcie@24000000 { - num-lanes = <4>; - ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ - max-link-speed = <4>; - interrupt-parent = <&plic>; -- interrupts = <73>, <74>, <75>, <76>, <77>, <78>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <73>, <74>, <75>, <76>, <77>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, - <0x0 0x0 0x0 0x2 &plic 75>, --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch b/SPECS/linux-lts-kmhv2/0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch new file mode 100644 index 0000000000..ca0081cabf --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch @@ -0,0 +1,364 @@ +From 90a72c61206582a7f4df5b88119e6602cbafc201 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 18 Nov 2025 13:48:49 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dts: dp1000: add dts/dtsi for Milk-V Titan + board based on UltraRISC DP1000 SoC + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +-------------------------------- + +Add dp1000-titan-v1.dts and dp1000-titan-pinctrl.dtsi for the Milk-V Titan +board. The Titan board is designed by Milk-V and is based on the UltraRISC +DP1000 SoC. These device tree files provide the initial support for the +board, including pinctrl and basic peripheral configuration. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/edab885e252d0442ccf52b2b554934138b82b2ec +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 1 + + .../dts/ultrarisc/dp1000-titan-pinctrl.dtsi | 173 ++++++++++++++++++ + .../boot/dts/ultrarisc/dp1000-titan-v1.dts | 139 ++++++++++++++ + 3 files changed, 313 insertions(+) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index 22c03b44b2f8..df8efe1a3ed7 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-titan-v1.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi +new file mode 100644 +index 000000000000..35429e539832 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi +@@ -0,0 +1,173 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 12 UR_FUNC0 ++ UR_DP1000_IOMUX_A 13 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 6 UR_FUNC0 ++ UR_DP1000_IOMUX_B 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 0 UR_FUNC0 ++ UR_DP1000_IOMUX_C 1 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 2 UR_FUNC0 ++ UR_DP1000_IOMUX_C 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 8 UR_FUNC1 ++ UR_DP1000_IOMUX_A 9 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 4 UR_FUNC0 ++ UR_DP1000_IOMUX_B 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 4 UR_FUNC0 ++ UR_DP1000_IOMUX_C 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart3_pins: uart3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 6 UR_FUNC0 ++ UR_DP1000_IOMUX_C 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_D 0 UR_FUNC1 ++ UR_DP1000_IOMUX_D 1 UR_FUNC1 ++ UR_DP1000_IOMUX_D 2 UR_FUNC1 ++ UR_DP1000_IOMUX_D 3 UR_FUNC1 ++ UR_DP1000_IOMUX_D 4 UR_FUNC1 ++ UR_DP1000_IOMUX_D 5 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 0 UR_FUNC0 ++ UR_DP1000_IOMUX_A 1 UR_FUNC0 ++ UR_DP1000_IOMUX_A 2 UR_FUNC0 ++ UR_DP1000_IOMUX_A 3 UR_FUNC0 ++ UR_DP1000_IOMUX_A 4 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ gpios_pin: gpios_pin { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 10 UR_FUNC_DEF ++ UR_DP1000_IOMUX_A 11 UR_FUNC_DEF ++ UR_DP1000_IOMUX_A 14 UR_FUNC_DEF ++ UR_DP1000_IOMUX_A 15 UR_FUNC_DEF ++ ++ UR_DP1000_IOMUX_B 0 UR_FUNC_DEF ++ UR_DP1000_IOMUX_B 1 UR_FUNC_DEF ++ UR_DP1000_IOMUX_B 2 UR_FUNC_DEF ++ ++ UR_DP1000_IOMUX_D 6 UR_FUNC_DEF ++ UR_DP1000_IOMUX_D 7 UR_FUNC_DEF ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 10 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 11 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 14 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 15 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ ++ UR_DP1000_IOMUX_B 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ ++ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts +new file mode 100644 +index 000000000000..2cbdfa2ad813 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts +@@ -0,0 +1,139 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000-titan-pinctrl.dtsi" ++#include ++#include ++#include ++#include ++ ++/ { ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS0,115200"; ++ stdout-path = &uart0; ++ }; ++ ++ gpio-poweroff { ++ compatible = "gpio-poweroff"; ++ gpios = <&portb 0 GPIO_ACTIVE_LOW>; ++ active-delay-ms = <100>; ++ line-name = "power-off"; ++ status = "okay"; ++ }; ++ ++ gpio-restart { ++ compatible = "gpio-restart"; ++ gpios = <&portb 1 GPIO_ACTIVE_LOW>; ++ active-delay-ms = <100>; ++ line-name = "reset-system"; ++ status = "okay"; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ key-wakeup { ++ label = "Wake-Up"; ++ gpios = <&porta 14 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ linux,input-type = ; ++ debounce-interval = <10>; ++ wakeup-source; ++ wakeup-event-action = ; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ ++ rtc@68 { ++ compatible = "st,m41t11"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++}; ++ ++&porta { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpios_pin>; ++ ++ i2c1-mux-hog { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ /* LOW: DCDC(U6) connect MCU(EC) ++ * HIGH: DCDC(U6) connect CPU ++ */ ++ output-low; ++ line-name = "gpio-mux-dcdc"; ++ }; ++ ++ i2c3-mux-hog { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_LOW>; ++ /* LOW: CPU i2c3 connect nvme ++ * HIGH: CPU i2c3 connect pciex16 ++ */ ++ output-low; ++ line-name = "gpio-mux-i2c3"; ++ }; ++ ++ uart0-mux-hog { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ /* LOW: uart_debug connect BMC ++ * HIGH: uart_debug connect CPU ++ */ ++ output-high; ++ line-name = "gpio-mux-debug"; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch b/SPECS/linux-lts-kmhv2/0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch new file mode 100644 index 0000000000..7b6568d84b --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch @@ -0,0 +1,77 @@ +From ad2ca89827235515c3cfea8822ac22544a6f79f1 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Mon, 23 Feb 2026 14:35:29 +0800 +Subject: [RUYI PATCH] REVYSR: pinctrl: ultrarisc: cleanup probe&remove + +Signed-off-by: Han Gao +--- + .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 - + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 22 +++---------------- + 2 files changed, 3 insertions(+), 20 deletions(-) + +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +index 6a7496a465d8..0ead138c9d1f 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +@@ -117,7 +117,6 @@ static struct platform_driver ur_pinctrl_driver = { + .of_match_table = ur_pinctrl_of_match, + }, + .probe = ur_pinctrl_probe, +- .remove = ur_pinctrl_remove, + }; + + module_platform_driver(ur_pinctrl_driver); +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +index edaeca881af7..cdd7160f3183 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +@@ -514,8 +514,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) + ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); + if (!ur_pinctrl) { + dev_err(&pdev->dev, "pinctrl alloc failed\n"); +- ret = -ENOMEM; +- goto free_pinctrl_desc; ++ return -ENOMEM; + } + struct resource *res; + +@@ -524,8 +523,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) + ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ur_pinctrl->base)) { + dev_err(&pdev->dev, "get ioremap resource failed\n"); +- ret = -EINVAL; +- goto free_pinctrl_desc; ++ return -EINVAL; + } + dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); + ur_pinctrl_desc->name = dev_name(&pdev->dev); +@@ -546,25 +544,11 @@ int ur_pinctrl_probe(struct platform_device *pdev) + ur_pinctrl, &ur_pinctrl->pctl_dev); + if (ret) { + dev_err(&pdev->dev, "pinctrl register failed\n"); +- goto free_pinctrl; ++ return ret; + } + + platform_set_drvdata(pdev, ur_pinctrl); + + return pinctrl_enable(ur_pinctrl->pctl_dev); +- +-free_pinctrl: +- devm_kfree(&pdev->dev, ur_pinctrl); +-free_pinctrl_desc: +- devm_kfree(&pdev->dev, ur_pinctrl_desc); +- return ret; + } + +- +-void ur_pinctrl_remove(struct platform_device *pdev) +-{ +- struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); +- +- if (ur_pinctrl->pctl_dev) +- devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); +-} +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0458-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch b/SPECS/linux-lts-kmhv2/0458-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch deleted file mode 100644 index 7a4dc86808..0000000000 --- a/SPECS/linux-lts-kmhv2/0458-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch +++ /dev/null @@ -1,102 +0,0 @@ -From da670b3d82267098c5ec850e11e6810ba6c0141b Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sat, 24 Jan 2026 08:48:53 +0800 -Subject: [PATCH 458/467] RUYI: riscv: dts: spacemit: k3: Add USB2.0 support - -FROM: https://github.com/spacemit-com/linux/commit/6f1578894e4484f8a6724aceff099d2e90450e10 - -The USB2.0 controller on Pico-ITX board connnect to a Terminus FE1.1 Hub -which fully USB2.0 protocol compliant and provides 4 ports. - -Signed-off-by: Yixun Lan -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 25 ++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++ - 2 files changed, 56 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index 61cbf924830b..ac965ec83f2c 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -33,6 +33,15 @@ reg_aux_vcc5v: regulator-aux-vcc5v { - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -+ -+ aux_vcc3v3: regulator-aux-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "AUX_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ - }; - - &i2c8 { -@@ -255,3 +264,19 @@ &uart0 { - pinctrl-0 = <&uart0_0_cfg>; - status = "okay"; - }; -+ -+&usb2_host { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ hub@1 { -+ compatible = "usb1a40,0101"; -+ reg = <1>; -+ vdd-supply = <&aux_vcc3v3>; -+ }; -+}; -+ -+&usb2_phy { -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 5b17612fe58e..66dcabd0a815 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -637,6 +637,37 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ usb2_host: usb@c0a00000 { -+ compatible = "spacemit,k3-dwc3"; -+ reg = <0x0 0xc0a00000 0x0 0x10000>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ clock-names = "usbdrd30"; -+ resets = <&syscon_apmu RESET_APMU_USB2_AHB>, -+ <&syscon_apmu RESET_APMU_USB2_VCC>, -+ <&syscon_apmu RESET_APMU_USB2_PHY>; -+ reset-names = "ahb", "vcc", "phy"; -+ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&saplic>; -+ phys = <&usb2_phy>; -+ phy-names = "usb2-phy"; -+ phy_type = "utmi"; -+ snps,dis_enblslpm_quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ dr_mode = "host"; -+ maximum-speed = "high-speed"; -+ status = "disabled"; -+ }; -+ -+ usb2_phy: phy@c0a20000 { -+ compatible = "spacemit,k3-usb2-phy"; -+ reg = <0x0 0xc0a20000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k3-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch b/SPECS/linux-lts-kmhv2/0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch new file mode 100644 index 0000000000..3ab0a8fab6 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch @@ -0,0 +1,46 @@ +From 3a0ec292f418c3f0ec2630531aeab29eea263f22 Mon Sep 17 00:00:00 2001 +From: U2FsdGVkX1 +Date: Sun, 29 Mar 2026 15:31:14 +0000 +Subject: [RUYI PATCH] REVYSR: riscv: dp1000: dts: use ultrarisc,dp1000-pcie + for PCIe nodes + +Signed-off-by: U2FsdGVkX1 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +index a25e87e15553..78e0cda1fcb9 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +@@ -436,7 +436,7 @@ dmac: dma-controller@39000000 { + }; + + pcie_x16: pcie@21000000 { +- compatible = "ultrarisc,dw-pcie"; ++ compatible = "ultrarisc,dp1000-pcie"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; +@@ -462,7 +462,7 @@ pcie_x16: pcie@21000000 { + }; + + pcie_x4a: pcie@23000000 { +- compatible = "ultrarisc,dw-pcie"; ++ compatible = "ultrarisc,dp1000-pcie"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; +@@ -488,7 +488,7 @@ pcie_x4a: pcie@23000000 { + }; + + pcie_x4b: pcie@24000000 { +- compatible = "ultrarisc,dw-pcie"; ++ compatible = "ultrarisc,dp1000-pcie"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0459-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch b/SPECS/linux-lts-kmhv2/0459-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch deleted file mode 100644 index fb68ebb141..0000000000 --- a/SPECS/linux-lts-kmhv2/0459-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch +++ /dev/null @@ -1,145 +0,0 @@ -From a778bb9a14663755014caabaaa245eba24561659 Mon Sep 17 00:00:00 2001 -From: Zhang Meng -Date: Mon, 5 Jan 2026 20:05:04 +0800 -Subject: [PATCH 459/467] SPACEMIT: riscv: uaccess: don't use vector if buffer - is not cacheable - -FROM: https://github.com/spacemit-com/linux-6.18/commit/9168f7e0c6bfdcfa3b6a64a4d45e3cd68a81618f - -Change-Id: I040d597ee246777767f7be747fa9202154524538 -[ Vivian: Rebase and move check into enter_vector_usercopy ] -Signed-off-by: Vivian Wang -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/uaccess.h | 5 +++ - arch/riscv/lib/Makefile | 1 + - arch/riscv/lib/riscv_v_helpers.c | 5 +++ - arch/riscv/lib/uaccess_cache_check.c | 65 ++++++++++++++++++++++++++++ - 4 files changed, 76 insertions(+) - create mode 100644 arch/riscv/lib/uaccess_cache_check.c - -diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h -index 6aef591a6bfc..b028208b05ec 100644 ---- a/arch/riscv/include/asm/uaccess.h -+++ b/arch/riscv/include/asm/uaccess.h -@@ -487,6 +487,11 @@ static inline void user_access_restore(unsigned long enabled) { } - if (__asm_copy_from_user_sum_enabled(_dst, _src, _len)) \ - goto label; - -+/* Memory cacheability check for vector uaccess optimization */ -+#ifdef CONFIG_RISCV_ISA_V -+int is_cacheable_safe(const void *addr); -+#endif -+ - #else /* CONFIG_MMU */ - #include - #endif /* CONFIG_MMU */ -diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile -index 735d0b665536..43fe69db9803 100644 ---- a/arch/riscv/lib/Makefile -+++ b/arch/riscv/lib/Makefile -@@ -14,6 +14,7 @@ endif - lib-y += csum.o - ifeq ($(CONFIG_MMU), y) - lib-$(CONFIG_RISCV_ISA_V) += uaccess_vector.o -+lib-$(CONFIG_RISCV_ISA_V) += uaccess_cache_check.o - endif - lib-$(CONFIG_MMU) += uaccess.o - lib-$(CONFIG_64BIT) += tishift.o -diff --git a/arch/riscv/lib/riscv_v_helpers.c b/arch/riscv/lib/riscv_v_helpers.c -index 7bbdfc6d4552..7ab2cea280f8 100644 ---- a/arch/riscv/lib/riscv_v_helpers.c -+++ b/arch/riscv/lib/riscv_v_helpers.c -@@ -8,6 +8,7 @@ - - #include - #include -+#include - - #ifdef CONFIG_MMU - #include -@@ -28,6 +29,10 @@ asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n, - if (!may_use_simd()) - goto fallback; - -+ /* HACK */ -+ if (!is_cacheable_safe(dst) || !is_cacheable_safe(src)) -+ goto fallback; -+ - kernel_vector_begin(); - remain = enable_sum ? __asm_vector_usercopy(dst, src, n) : - __asm_vector_usercopy_sum_enabled(dst, src, n); -diff --git a/arch/riscv/lib/uaccess_cache_check.c b/arch/riscv/lib/uaccess_cache_check.c -new file mode 100644 -index 000000000000..0b0996fa2d37 ---- /dev/null -+++ b/arch/riscv/lib/uaccess_cache_check.c -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Memory cacheability check for RISC-V uaccess optimization -+ * -+ * This file provides a C function that can be called from assembly -+ * to determine if a buffer is cacheable before using vector instructions. -+ */ -+ -+#include -+#include -+#include -+ -+/** -+ * is_cacheable_safe - Check if memory buffer is cacheable -+ * @addr: Virtual address to check (kernel or user space) -+ * -+ * Returns: 1 if cacheable, 0 if non-cacheable -+ * -+ * This function is designed to be called from assembly code in uaccess.S -+ * to determine if vector instructions are safe to use for memory copy. -+ * -+ * Non-cacheable memory (device IO, DMA coherent buffers) should not use -+ * vector instructions as they may cause cache coherency issues. -+ * -+ * Handles both kernel and user space addresses safely: -+ * - Kernel direct mapping: Always cacheable -+ * - Kernel vmalloc: Check VM flags -+ * - User space: Check page table (most are cacheable) -+ * - ioremap/DMA: Non-cacheable -+ */ -+int is_cacheable_safe(const void *addr) -+{ -+ unsigned long vaddr = (unsigned long)addr; -+ -+ /* Kernel direct mapped memory - always cacheable */ -+ if (virt_addr_valid(addr)) -+ return 1; -+ -+ if (vaddr < TASK_SIZE) { -+ /* -+ * User space address, Determine it as a cacheable buffer, -+ * maybe not safe!! -+ */ -+ return 1; -+ } -+ -+ /* Check if it's a vmalloc region (kernel virtual address) */ -+ if (is_vmalloc_addr(addr)) { -+ struct vm_struct *vm; -+ -+ vm = find_vm_area(addr); -+ if (!vm) -+ return 0; -+ -+ /* Exclude ioremap and DMA coherent buffers */ -+ if (vm->flags & (VM_IOREMAP | VM_DMA_COHERENT)) -+ return 0; -+ -+ /* Normal vmalloc - cacheable */ -+ return 1; -+ } -+ -+ /* Unknown kernel region - assume non-cacheable for safety */ -+ return 0; -+} --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0460-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch b/SPECS/linux-lts-kmhv2/0460-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch deleted file mode 100644 index 7e8d2c8137..0000000000 --- a/SPECS/linux-lts-kmhv2/0460-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch +++ /dev/null @@ -1,90 +0,0 @@ -From b29e3da058bfbb22e49d731df4e66c5998bd6324 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 13 Feb 2026 09:01:58 +0800 -Subject: [PATCH 460/467] RUYI: dt-bindings: phy: Add Spacemit K3 USB3/PCIe - comb phy support - -The USB3/PCIe comb PHY on the K3 is a complex PHY group that -can provide multiple phy for both PCIe and USB controller. -Its mux configuration is controlled by the APMU syscon device. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - .../bindings/phy/spacemit,k3-combo-phy.yaml | 64 +++++++++++++++++++ - 1 file changed, 64 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml -new file mode 100644 -index 000000000000..eafc753b7e9b ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml -@@ -0,0 +1,64 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Spacemit K3 PCIE/USB3 Comb PHY -+ -+maintainers: -+ - Inochi Amaoto -+ -+properties: -+ compatible: -+ const: spacemit,k3-combo-phy -+ -+ reg: -+ maxItems: 1 -+ -+ "#phy-cells": -+ const: 2 -+ description: -+ The first one is phy id, the second one is phy type. -+ -+ spacemit,apb-spare: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: -+ Phandle to APB SPARE system controller interface, used for -+ PHY calibration. -+ -+ spacemit,apmu: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ items: -+ - items: -+ - description: phandle of APMU syscon -+ - description: configuration of the PHY lanes -+ description: | -+ Phandle to control PHY mux configuration. The configuration -+ is described as follows: -+ bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode -+ bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode -+ bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode -+ bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode -+ bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode -+ -+ The bit[3:0] is only valid when bit 4 is 1. -+ -+required: -+ - compatible -+ - reg -+ - "#phy-cells" -+ - spacemit,apb-spare -+ - spacemit,apmu -+ -+additionalProperties: false -+ -+examples: -+ - | -+ phy@81d00000 { -+ compatible = "spacemit,k3-combo-phy"; -+ reg = <0x81d00000 0x600000>; -+ #phy-cells = <2>; -+ spacemit,apb-spare = <&apb_spare>; -+ spacemit,apmu = <&apmu 0x00>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch b/SPECS/linux-lts-kmhv2/0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch new file mode 100644 index 0000000000..732de29759 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch @@ -0,0 +1,450 @@ +From 3091a1fa3451d492041d5cc22aeb46f67edaf469 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Thu, 13 Feb 2025 15:50:12 +0800 +Subject: [RUYI PATCH] ULTRARISC: hwmon: add corepvt driver of UltraRISC DP1000 + +From: https://github.com/ultrarisc/linux-6.8.0/commit/2cb818e1179844847d3be752b978a4ee7e633bc3 + +UltraRISC Corepvt driver supports cluster voltage +and core temperature detection + +Signed-off-by: Jia Wang +Signed-off-by: Han Gao +--- + drivers/hwmon/Kconfig | 9 + + drivers/hwmon/Makefile | 1 + + drivers/hwmon/corepvt-ultrarisc.c | 390 ++++++++++++++++++++++++++++++ + 3 files changed, 400 insertions(+) + create mode 100644 drivers/hwmon/corepvt-ultrarisc.c + +diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig +index 2a71b6e834b0..2a44030c7796 100644 +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -503,6 +503,15 @@ config SENSORS_CHIPCAP2 + To compile this driver as a module, choose M here: the module + will be called chipcap2. + ++config SENSORS_COREPVT_ULTRARISC ++ tristate "UltraRISC Core Voltage, Temperature sensor driver" ++ help ++ If you say yes here you get support for UltraRISC Core PVT sensor ++ embedded into the SoC. ++ ++ This driver can also be built as a module. If so, the module will be ++ called corepvt-ultrarisc. ++ + config SENSORS_CORSAIR_CPRO + tristate "Corsair Commander Pro controller" + depends on HID +diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile +index 73b2abdcc6dd..6cf5fac80b7b 100644 +--- a/drivers/hwmon/Makefile ++++ b/drivers/hwmon/Makefile +@@ -61,6 +61,7 @@ obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o + obj-$(CONFIG_SENSORS_BT1_PVT) += bt1-pvt.o + obj-$(CONFIG_SENSORS_CGBC) += cgbc-hwmon.o + obj-$(CONFIG_SENSORS_CHIPCAP2) += chipcap2.o ++obj-$(CONFIG_SENSORS_COREPVT_ULTRARISC) += corepvt-ultrarisc.o + obj-$(CONFIG_SENSORS_CORETEMP) += coretemp.o + obj-$(CONFIG_SENSORS_CORSAIR_CPRO) += corsair-cpro.o + obj-$(CONFIG_SENSORS_CORSAIR_PSU) += corsair-psu.o +diff --git a/drivers/hwmon/corepvt-ultrarisc.c b/drivers/hwmon/corepvt-ultrarisc.c +new file mode 100644 +index 000000000000..3674eedefbda +--- /dev/null ++++ b/drivers/hwmon/corepvt-ultrarisc.c +@@ -0,0 +1,390 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Driver for UltraRISC Core PVT ++ * ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define COREPVT_CHL_OFFSET 0x1000 ++#define COREPVT_REG_CIR 0x0 ++#define COREPVT_REG_PSCR 0x04 ++#define COREPVT_REG_CFDR 0x08 ++#define COREPVT_REG_DOR 0x0C ++#define COREPVT_REG_ICR 0x10 ++#define COREPVT_REG_IER 0x14 ++#define COREPVT_REG_IMSR 0x18 ++#define COREPVT_REG_IRSR 0x1C ++ ++#define PVT_MAX_CHANNEL 64 ++#define PVT_TRIM_DEFAULT 0x7 ++ ++struct corepvt_channel_config { ++ const char *label; ++ u32 trim; ++}; ++ ++struct corepvt_cal_data { ++ u32 val_offset; ++ u32 val_lsb; ++}; ++ ++struct corepvt_data { ++ const struct hwmon_chip_info *chip_info; ++ u64 temp_chl_mask; ++ u64 vol_chl_mask; ++}; ++ ++struct corepvt_hwmon { ++ struct device *dev; ++ struct device *hwmon; ++ ++ void __iomem *regs; ++ int irq; ++ int clk_freq; ++ int channels; ++ const struct hwmon_chip_info *chip_info; ++ struct corepvt_channel_config config[PVT_MAX_CHANNEL]; ++ const struct corepvt_data *pvt_data; ++ raw_spinlock_t lock; ++}; ++ ++#define COREPVT_VOLTAGE_DATA_BASE 2065100 /* 2065.1 */ ++#define COREPVT_VOLTAGE_LSB 1682 /* 1.682 mV */ ++#define COREPVT_TEMP_DATA_BASE 27049000 /* 2704.9 */ ++#define COREPVT_TEMP_LSB 22632 /* 2.2632 Celsius */ ++ ++static int corepvt_read_vol(struct corepvt_hwmon *pvt, ++ int channel, long *val) ++{ ++ void __iomem *chl_base; ++ unsigned long flag; ++ u32 dout; ++ u32 chl_offset = 0; ++ ++ // Assume that the voltage channel is continuous ++ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); ++ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); ++ ++ raw_spin_lock_irqsave(&pvt->lock, flag); ++ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); ++ raw_spin_unlock_irqrestore(&pvt->lock, flag); ++ ++ *val = ((long)dout * 1000 - COREPVT_VOLTAGE_DATA_BASE) / COREPVT_VOLTAGE_LSB; ++ ++ return 0; ++} ++ ++static int corepvt_read_temp(struct corepvt_hwmon *pvt, ++ int channel, long *val) ++{ ++ void __iomem *chl_base; ++ unsigned long flag; ++ u32 dout; ++ u32 chl_offset = 0; ++ ++ // Assume that the temperature channel is continuous ++ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); ++ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); ++ ++ raw_spin_lock_irqsave(&pvt->lock, flag); ++ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); ++ raw_spin_unlock_irqrestore(&pvt->lock, flag); ++ ++ *val = ((long)dout * 10000 - COREPVT_TEMP_DATA_BASE) * 1000 / COREPVT_TEMP_LSB; ++ ++ return 0; ++} ++ ++static umode_t corepvt_is_visible(const void *drvdata, enum hwmon_sensor_types type, ++ u32 attr, int channel) ++{ ++ const struct corepvt_hwmon *pvt = drvdata; ++ ++ if (channel >= pvt->channels) ++ return 0; ++ ++ switch (type) { ++ case hwmon_in: ++ switch (attr) { ++ case hwmon_in_input: ++ case hwmon_in_label: ++ return 0444; ++ } ++ break; ++ case hwmon_temp: ++ switch (attr) { ++ case hwmon_temp_input: ++ case hwmon_temp_type: ++ case hwmon_temp_label: ++ return 0444; ++ } ++ break; ++ default: ++ return 0; ++ } ++ ++ return 0; ++} ++ ++static int corepvt_read(struct device *dev, enum hwmon_sensor_types type, ++ u32 attr, int channel, long *val) ++{ ++ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); ++ ++ switch (type) { ++ case hwmon_in: ++ switch (attr) { ++ case hwmon_in_input: ++ return corepvt_read_vol(pvt, channel, val); ++ } ++ break; ++ case hwmon_temp: ++ switch (attr) { ++ case hwmon_temp_type: ++ *val = 1; ++ return 0; ++ case hwmon_temp_input: ++ return corepvt_read_temp(pvt, channel, val); ++ } ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return -ENODATA; ++} ++ ++static int corepvt_read_string(struct device *dev, enum hwmon_sensor_types type, ++ u32 attr, int channel, const char **str) ++{ ++ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); ++ u32 chl_offset = 0; ++ ++ switch (type) { ++ case hwmon_in: ++ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); ++ break; ++ case hwmon_temp: ++ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); ++ break; ++ default: ++ return -ENODATA; ++ break; ++ } ++ ++ *str = pvt->config[channel + chl_offset].label; ++ ++ return 0; ++} ++ ++/* ++ * corepvt init process: ++ * 1. config SETUP time, should be 10us, set PSCR register ++ * 2. config CLKIN, should be 4MHz, set CFDR register ++ * 3. (TODO)config interrupt, set ICR/IER/IMSR/IRSR ++ * 4. config TRIM and enable PVT, set CIR ++ */ ++static int corepvt_init(struct corepvt_hwmon *pvt) ++{ ++ void __iomem *chl_base; ++ unsigned long flag; ++ /* ++ * SETUP time 10us = 100KHz ++ * PSCR = CLK_FREQ / 100KHz ++ */ ++ u32 pscr_val = pvt->clk_freq / 100000; ++ /* ++ * CFDR = CLK_FREQ / 4MHz / 2 ++ */ ++ u32 cfdr_val = pvt->clk_freq / 8000000; ++ /* ++ * CIR: ++ * bit[0]: PU_VTDC, set 1 to enable pvt ++ * bit[5:2]: TRIM ++ */ ++ u32 cir_val; ++ ++ raw_spin_lock_irqsave(&pvt->lock, flag); ++ for (int i = 0; i < pvt->channels; i++) { ++ chl_base = pvt->regs + COREPVT_CHL_OFFSET * i; ++ cir_val = (pvt->config[i].trim << 2) | 0x01; ++ writel_relaxed(pscr_val, chl_base + COREPVT_REG_PSCR); ++ writel_relaxed(cfdr_val, chl_base + COREPVT_REG_CFDR); ++ writel_relaxed(cir_val, chl_base + COREPVT_REG_CIR); ++ } ++ raw_spin_unlock_irqrestore(&pvt->lock, flag); ++ ++ return 0; ++} ++ ++static const struct hwmon_ops corepvt_hwmon_ops = { ++ .is_visible = corepvt_is_visible, ++ .read = corepvt_read, ++ .read_string = corepvt_read_string, ++}; ++ ++static int corepvt_probe_channel_from_dt(struct platform_device *pdev, struct corepvt_hwmon *pvt) ++{ ++ struct device_node *child; ++ int ret; ++ u32 channel; ++ const char *label; ++ u32 trim; ++ ++ for_each_child_of_node(pdev->dev.of_node, child) { ++ if (!of_node_name_eq(child, "channel")) ++ continue; ++ ++ ret = of_property_read_u32(child, "reg", &channel); ++ if (ret) ++ goto node_put; ++ ++ ret = of_property_read_string(child, "label", &label); ++ if (ret) ++ goto node_put; ++ ++ if (of_property_present(child, "trim")) ++ of_property_read_u32(child, "trim", &trim); ++ else ++ trim = PVT_TRIM_DEFAULT; ++ ++ pvt->config[channel].label = label; ++ pvt->config[channel].trim = trim; ++ } ++ ++ return 0; ++ ++node_put: ++ of_node_put(child); ++ return ret; ++} ++ ++static int corepvt_probe(struct platform_device *pdev) ++{ ++ struct corepvt_hwmon *pvt; ++ const struct corepvt_data *pvt_data; ++ int ret; ++ ++ pvt = devm_kzalloc(&pdev->dev, sizeof(*pvt), GFP_KERNEL); ++ if (!pvt) ++ return -ENOMEM; ++ ++ pvt->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(pvt->regs)) { ++ dev_err(&pdev->dev, "get ioremap resource failed\n"); ++ ret = -EINVAL; ++ goto free_pvt; ++ } ++ ++ if (device_property_present(&pdev->dev, "interrupts")) ++ pvt->irq = platform_get_irq(pdev, 0); ++ ++ ret = device_property_read_u32(&pdev->dev, "clock-frequency", &pvt->clk_freq); ++ if (ret) { ++ dev_err(&pdev->dev, "get clock-frequency failed\n"); ++ goto free_pvt; ++ } ++ ++ ret = device_property_read_u32(&pdev->dev, "channels", &pvt->channels); ++ if (ret) { ++ dev_err(&pdev->dev, "get channels failed\n"); ++ goto free_pvt; ++ } ++ ++ pvt_data = device_get_match_data(&pdev->dev); ++ if (!pvt_data) { ++ dev_err(&pdev->dev, "No chip info found\n"); ++ ret = -ENODATA; ++ goto free_pvt; ++ } ++ ++ pvt->dev = &pdev->dev; ++ pvt->chip_info = pvt_data->chip_info; ++ pvt->pvt_data = pvt_data; ++ ++ if (pdev->dev.of_node) { ++ ret = corepvt_probe_channel_from_dt(pdev, pvt); ++ if (ret) ++ dev_warn(&pdev->dev, "WARN: probe channel failed\n"); ++ } ++ ++ pvt->hwmon = devm_hwmon_device_register_with_info(&pdev->dev, "corepvt_ultrarisc", ++ pvt, pvt->chip_info, ++ NULL); ++ if (IS_ERR(pvt->hwmon)) { ++ dev_err(&pdev->dev, "register hwmon failed(%ld)\n", PTR_ERR(pvt->hwmon)); ++ ret = -EINVAL; ++ goto free_pvt; ++ } ++ ++ pvt->dev = &pdev->dev; ++ raw_spin_lock_init(&pvt->lock); ++ ++ // Config and enable corepvt ++ corepvt_init(pvt); ++ ++ return 0; ++ ++free_pvt: ++ devm_kfree(&pdev->dev, pvt); ++ return ret; ++} ++ ++static const struct hwmon_channel_info * const ur_dp1000_channel_info[] = { ++ HWMON_CHANNEL_INFO(temp, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL), ++ HWMON_CHANNEL_INFO(in, ++ HWMON_I_INPUT | HWMON_I_LABEL, ++ HWMON_I_INPUT | HWMON_I_LABEL), ++ NULL ++}; ++ ++static const struct hwmon_chip_info ur_dp1000_chip_info = { ++ .ops = &corepvt_hwmon_ops, ++ .info = ur_dp1000_channel_info, ++}; ++ ++static struct corepvt_data ur_dp1000_pvt_data = { ++ .chip_info = &ur_dp1000_chip_info, ++ .temp_chl_mask = GENMASK_ULL(10, 0), ++ .vol_chl_mask = GENMASK_ULL(12, 11) ++}; ++ ++static const struct of_device_id corepvt_of_match[] = { ++ { .compatible = "ultrarisc,dp1000-pvt", .data = &ur_dp1000_pvt_data }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, corepvt_of_match); ++ ++static struct platform_driver corepvt_driver = { ++ .probe = corepvt_probe, ++ .driver = { ++ .name = "corepvt-ultrarisc", ++ .of_match_table = corepvt_of_match ++ } ++}; ++module_platform_driver(corepvt_driver); ++ ++MODULE_AUTHOR("Jia Wang "); ++MODULE_DESCRIPTION("corepvt-ultrarisc driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch b/SPECS/linux-lts-kmhv2/0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch new file mode 100644 index 0000000000..0582b1d016 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch @@ -0,0 +1,732 @@ +From 817a4331068207be97f31dbe87e3512e92b549de Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Sun, 12 Apr 2026 02:50:03 +0800 +Subject: [RUYI PATCH] RUYI: SYNC: riscv: dts: dp1000: Update dp1000.dtsi + +FROM: https://github.com/ultrarisc/linux-6.8.0/commit/b4a00f2f96a9c7d8d550259292fd19568fe9beec + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 521 ++++++++++++++++++++-- + 1 file changed, 489 insertions(+), 32 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +index 78e0cda1fcb9..7b7016618dcd 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +@@ -22,121 +22,491 @@ cpu0: cpu@0 { + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache0>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu0_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache0: l2-cache0 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; + }; ++ + cpu1: cpu@1 { + device_type = "cpu"; + reg = <0x1>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache1>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu1_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache1: l2-cache1 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; + }; ++ + cpu2: cpu@2 { + device_type = "cpu"; + reg = <0x2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache2>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu2_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache2: l2-cache2 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; + }; ++ + cpu3: cpu@3 { + device_type = "cpu"; + reg = <0x3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache3>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu3_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache3: l2-cache3 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; + }; ++ + cpu4: cpu@4 { + device_type = "cpu"; + reg = <0x10>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache4>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu4_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache4: l2-cache4 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; + }; ++ + cpu5: cpu@5 { + device_type = "cpu"; + reg = <0x11>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache5>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu5_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache5: l2-cache5 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; + }; ++ + cpu6: cpu@6 { + device_type = "cpu"; + reg = <0x12>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; +- + clock-frequency = <2000000000>; +- ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache6>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu6_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache6: l2-cache6 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; + }; ++ + cpu7: cpu@7 { + device_type = "cpu"; + reg = <0x13>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache7>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu7_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache7: l2-cache7 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; ++ }; ++ ++ cpu-map { ++ cluster0: cluster0 { ++ core0 { ++ cpu = <&cpu0>; ++ }; ++ core1 { ++ cpu = <&cpu1>; ++ }; ++ core2 { ++ cpu = <&cpu2>; ++ }; ++ core3 { ++ cpu = <&cpu3>; ++ }; ++ ++ cluster0_l3: l3-cache0 { ++ /* L3 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 4MB ++ * per-cluster. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <3>; ++ cache-size = <0x400000>; ++ cache-sets = <0x1000>; ++ cache-unified; ++ next-level-cache = <&l4_cache>; ++ }; ++ }; ++ ++ cluster1: cluster1 { ++ core0 { ++ cpu = <&cpu4>; ++ }; ++ core1 { ++ cpu = <&cpu5>; ++ }; ++ core2 { ++ cpu = <&cpu6>; ++ }; ++ core3 { ++ cpu = <&cpu7>; ++ }; ++ cluster1_l3: l3-cache1 { ++ /* L3 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 4MB ++ * per-cluster. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <3>; ++ cache-size = <0x400000>; ++ cache-sets = <0x1000>; ++ cache-unified; ++ next-level-cache = <&l4_cache>; ++ }; ++ }; + }; + }; + +@@ -150,6 +520,20 @@ soc { + #size-cells = <0x02>; + compatible = "simple-bus"; + ranges; ++ ++ l4_cache: l4-cache { ++ /* L4 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 16MB ++ * shared by the SoC. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <4>; ++ cache-size = <0x1000000>; ++ cache-sets = <0x4000>; ++ cache-unified; ++ }; + + clocks { + compatible = "simple-bus"; +@@ -160,6 +544,12 @@ device_clk: device_clk { + #clock-cells = <0>; + }; + ++ timer_clk: timer_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <50000000>; ++ #clock-cells = <0>; ++ }; ++ + csr_clk: csr_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; +@@ -170,35 +560,102 @@ csr_clk: csr_clk { + clint: clint@8000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, +- <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, +- <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, +- <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, +- <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, +- <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, +- <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, +- <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; ++ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, ++ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, ++ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, ++ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, ++ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, ++ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, ++ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; + reg = <0x00 0x8000000 0x00 0x100000>; + }; +- ++ + plic: plic@9000000 { + #interrupt-cells = <1>; + #address-cells = <0>; +- phandle = <0x01>; +- compatible = "ultrarisc,dp1000-plic"; ++ compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; + interrupt-controller; + interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, +- <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, +- <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, +- <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, +- <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, +- <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, +- <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, +- <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; ++ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, ++ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, ++ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, ++ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, ++ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, ++ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, ++ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; + reg = <0x00 0x9000000 0x00 0x4000000>; + riscv,max-priority = <0x07>; + riscv,ndev = <160>; + }; +- ++ ++ core_pvt: pvt@110D0000 { ++ compatible = "ultrarisc,dp1000-pvt"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x00 0x110D0000 0x00 0x0000D000>; ++ clock-frequency = <250000000>; ++ channels = <13>; ++ ++ #thermal-sensor-cells = <1>; ++ channel@0 { ++ label = "Core temp0"; ++ reg = <0>; ++ }; ++ ++ channel@1 { ++ label = "Core temp1"; ++ reg = <1>; ++ }; ++ ++ channel@2 { ++ label = "Core temp2"; ++ reg = <2>; ++ }; ++ ++ channel@3 { ++ label = "Core temp3"; ++ reg = <3>; ++ }; ++ ++ channel@4 { ++ label = "Core temp4"; ++ reg = <4>; ++ }; ++ ++ channel@5 { ++ label = "Core temp5"; ++ reg = <5>; ++ }; ++ channel@6 { ++ label = "Core temp6"; ++ reg = <6>; ++ }; ++ channel@7 { ++ label = "Core temp7"; ++ reg = <7>; ++ }; ++ channel@8 { ++ label = "Core temp8"; ++ reg = <8>; ++ }; ++ channel@9 { ++ label = "Core temp9"; ++ reg = <9>; ++ }; ++ channel@10 { ++ label = "Core temp10"; ++ reg = <10>; ++ }; ++ channel@11 { ++ label = "Cluster0 voltage"; ++ reg = <11>; ++ }; ++ channel@12 { ++ label = "Cluster1 voltage"; ++ reg = <12>; ++ }; ++ }; ++ + uart0: serial@20300000 { + interrupt-parent = <0x01>; + interrupts = <17>; +@@ -244,7 +701,7 @@ uart3: serial@20410000 { + }; + + spi0: spi@20320000 { +- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; ++ compatible = "snps,dw-apb-ssi"; + status = "okay"; + #address-cells = <0x01>; + #size-cells = <0x00>; +@@ -258,7 +715,7 @@ spi0: spi@20320000 { + }; + + spi1: spi@20420000 { +- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; ++ compatible = "snps,dw-apb-ssi"; + status = "okay"; + #address-cells = <0x01>; + #size-cells = <0x00>; +@@ -449,11 +906,11 @@ pcie_x16: pcie@21000000 { + num-lanes = <16>; + ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ +- <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ +- max-link-speed = <4>; ++ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ ++ max-link-speed = <16>; + interrupt-parent = <&plic>; +- interrupts = <43>, <44>, <45>, <46>, <47>, <48>; +- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupts = <43>, <44>, <45>, <46>, <47>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, +@@ -475,11 +932,11 @@ pcie_x4a: pcie@23000000 { + num-lanes = <4>; + ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ + <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ +- <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ + max-link-speed = <4>; + interrupt-parent = <&plic>; +- interrupts = <63>, <64>, <65>, <66>, <67>, <68>; +- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupts = <63>, <64>, <65>, <66>, <67>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, + <0x0 0x0 0x0 0x2 &plic 65>, +@@ -501,11 +958,11 @@ pcie_x4b: pcie@24000000 { + num-lanes = <4>; + ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ +- <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ + max-link-speed = <4>; + interrupt-parent = <&plic>; +- interrupts = <73>, <74>, <75>, <76>, <77>, <78>; +- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupts = <73>, <74>, <75>, <76>, <77>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, + <0x0 0x0 0x0 0x2 &plic 75>, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0461-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch b/SPECS/linux-lts-kmhv2/0461-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch deleted file mode 100644 index 5fcf731d24..0000000000 --- a/SPECS/linux-lts-kmhv2/0461-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch +++ /dev/null @@ -1,730 +0,0 @@ -From d562b4d41d3ea85b9696fdce97dcf47fc485046b Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 13 Feb 2026 09:09:58 +0800 -Subject: [PATCH 461/467] RUYI: phy: spacemit: Add USB3/PCIe comb PHY driver - for Spacemit K3 - -The comb PHY on K3 requires to configure a syscon device for the -right mux configuration. And it requires calibration before any -usage. - -Add USB3/PCIe comb PHY driver for Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - drivers/phy/spacemit/Kconfig | 16 ++ - drivers/phy/spacemit/Makefile | 2 + - drivers/phy/spacemit/phy-k3-combo.c | 252 ++++++++++++++++++ - drivers/phy/spacemit/phy-k3-common.c | 372 +++++++++++++++++++++++++++ - drivers/phy/spacemit/phy-k3-common.h | 27 ++ - 5 files changed, 669 insertions(+) - create mode 100644 drivers/phy/spacemit/phy-k3-combo.c - create mode 100644 drivers/phy/spacemit/phy-k3-common.c - create mode 100644 drivers/phy/spacemit/phy-k3-common.h - -diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig -index 0136aee2e8a2..9a1e25592f25 100644 ---- a/drivers/phy/spacemit/Kconfig -+++ b/drivers/phy/spacemit/Kconfig -@@ -11,3 +11,19 @@ config PHY_SPACEMIT_K1_USB2 - help - Enable this to support K1 USB 2.0 PHY driver. This driver takes care of - enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. -+ -+config PHY_SPACEMIT_K3_COMMON_OPS -+ tristate -+ select MFD_SYSCON -+ select GENERIC_PHY -+ -+config PHY_SPACEMIT_K3_COMBO_PHY -+ tristate "SpacemiT K3 USB3/PCIe PHY support" -+ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF -+ depends on COMMON_CLK -+ select PHY_SPACEMIT_K3_COMMON_OPS -+ help -+ Enable this to support K3 USB3/PCIe combo PHY driver. This -+ driver takes care of enabling and clock setup and will be used -+ by K3 dwc3 driver. -+ If unsure, say N. -diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile -index fec0b425a948..df9b609d066f 100644 ---- a/drivers/phy/spacemit/Makefile -+++ b/drivers/phy/spacemit/Makefile -@@ -1,2 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0-only - obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o -+obj-$(CONFIG_PHY_SPACEMIT_K3_COMBO_PHY) += phy-k3-combo.o -+obj-$(CONFIG_PHY_SPACEMIT_K3_COMMON_OPS) += phy-k3-common.o -diff --git a/drivers/phy/spacemit/phy-k3-combo.c b/drivers/phy/spacemit/phy-k3-combo.c -new file mode 100644 -index 000000000000..abd0aad18893 ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-combo.c -@@ -0,0 +1,252 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * phy-k3-usb3.c - SpacemiT K3 Type-C Orientation Switch Driver -+ * -+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "phy-k3-common.h" -+ -+/* -+ * The PCIE/USB Subsystem on SpacemiT K3 have 3 single lane PIPE3 PHYs -+ * (PHY2/3/4) shared by PCIE PortC/D and USB3 PortB/C/D. -+ * -+ * PMUA_PCIE_SUBSYS_MGMT[4:0] -+ * -+ * bit4 = 0 : PCIe A X8 mode, all 8 lanes dedicated to PCIe Port A -+ * 1 : PHY lanes shared between PCIe or USB according to [3:0] -+ * -+ * All PHY matrix combinations according to [4:0]: -+ * -+ * 0x0X : PCIe-A X8 -+ * 0x10 : PCIe-C x2 (PHY2+PHY3) + PCIe-D x1 (PHY4) -+ * 0x11 : PCIe-C x2 (PHY2+PHY3) + USB-D (PHY4) -+ * 0x12 : PCIe-C x1 (PHY2) + USB-C (PHY3) -+ * 0x13 : PCIe-C x1 (PHY2) + USB-C (PHY3) + USB-D (PHY4) -+ * 0x14 : PCIe-C x1 (PHY3) + USB-B (PHY2) -+ * 0x15 : PCIe-C x1 (PHY3) + USB-B (PHY2) + USB-D (PHY4) -+ * 0x16 : USB-B (PHY2) + USB-C (PHY3) + PCIe D x1 (PHY4) -+ * 0x17 : USB-B (PHY2) + USB-C (PHY3) + USB-D (PHY4) -+ * -+ * So any USB Port B/C/D operation requires PCIe A X8 mode to be disabled. -+ */ -+#define PMUA_PCIE_SUBSYS_MGMT 0x1d8 -+#define PU_MATRIX_CONF_MASK GENMASK(4, 0) -+ -+#define COMBPHY_MAX_SUBPHYS 6 -+ -+struct k3_combo_phy { -+ struct device *dev; -+ struct k3_lane_group groups[COMBPHY_MAX_SUBPHYS]; -+ void __iomem *base; -+ struct regmap *apb_spare; -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group0 = { -+ .lanes = 2, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x0, 0x400 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group1 = { -+ .lanes = 2, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x100000, 0x100400 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group2 = { -+ .lanes = 1, -+ .config = 0x14, -+ .mask = 0x14, -+ .offsets = { -+ 0x200000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group3 = { -+ .lanes = 1, -+ .config = 0x12, -+ .mask = 0x12, -+ .offsets = { -+ 0x300000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group4 = { -+ .lanes = 1, -+ .config = 0x11, -+ .mask = 0x11, -+ .offsets = { -+ 0x400000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group5 = { -+ .lanes = 1, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x500000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data *k3_combphy_lane_datas[] = { -+ &k3_combphy_lane_group0, -+ &k3_combphy_lane_group1, -+ &k3_combphy_lane_group2, -+ &k3_combphy_lane_group3, -+ &k3_combphy_lane_group4, -+ &k3_combphy_lane_group5, -+}; -+ -+static int k3_combo_phy_init_lanes(struct k3_combo_phy *phy, unsigned int config) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(k3_combphy_lane_datas); i++) { -+ const struct k3_phy_lane_group_data *data = k3_combphy_lane_datas[i]; -+ struct k3_lane_group *lg = &phy->groups[i]; -+ const struct phy_ops *ops; -+ bool is_usb; -+ -+ is_usb = (data->mask & config) == data->config; -+ if (is_usb) -+ ops = &k3_usb3_phy_ops; -+ else -+ ops = &k3_pcie_phy_ops; -+ -+ dev_dbg(phy->dev, "phy %d is %s\n", i, is_usb ? "usb" : "pcie"); -+ -+ lg->phy = devm_phy_create(phy->dev, NULL, ops); -+ if (IS_ERR(lg->phy)) -+ return PTR_ERR(lg->phy); -+ -+ lg->is_pcie = !is_usb; -+ lg->data = data; -+ lg->base = phy->base; -+ phy_set_drvdata(lg->phy, lg); -+ } -+ -+ return 0; -+} -+ -+static int k3_combo_phy_update_config(struct regmap *apmu, unsigned int config) -+{ -+ if (config & ~PU_MATRIX_CONF_MASK) -+ return -EINVAL; -+ -+ return regmap_update_bits(apmu, PMUA_PCIE_SUBSYS_MGMT, PU_MATRIX_CONF_MASK, config); -+} -+ -+static struct phy *k3_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) -+{ -+ struct k3_combo_phy *phy = dev_get_drvdata(dev); -+ struct k3_lane_group *lg; -+ -+ if (args->args_count != 2) { -+ dev_err(dev, "Invalid number of arguments\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ if (args->args[0] >= ARRAY_SIZE(k3_combphy_lane_datas)) { -+ dev_err(dev, "Invalid PHY id\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ lg = &phy->groups[args->args[0]]; -+ -+ if ((lg->is_pcie && args->args[1] != PHY_TYPE_PCIE) || -+ (!lg->is_pcie && args->args[1] != PHY_TYPE_USB3)) { -+ dev_err(dev, "Invalid PHY mode\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ return lg->phy; -+} -+ -+static int k3_combo_phy_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct device_node *node = dev->of_node; -+ struct phy_provider *provider; -+ struct k3_combo_phy *phy; -+ struct regmap *apmu; -+ u32 config = 0; -+ int ret; -+ -+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); -+ if (!phy) -+ return -ENOMEM; -+ -+ phy->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(phy->base)) -+ return PTR_ERR(phy->base); -+ -+ phy->apb_spare = syscon_regmap_lookup_by_phandle(node, "spacemit,apb-spare"); -+ if (IS_ERR(phy->apb_spare)) -+ return dev_err_probe(dev, PTR_ERR(phy->apb_spare), -+ "Failed to fine APB SPARE syscon"); -+ -+ apmu = syscon_regmap_lookup_by_phandle_args(node, "spacemit,apmu", 1, &config); -+ if (IS_ERR(apmu)) -+ return dev_err_probe(dev, PTR_ERR(apmu), -+ "Failed to find APMU syscon"); -+ -+ ret = k3_combo_phy_update_config(apmu, config); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to set lane configuration"); -+ -+ phy->dev = dev; -+ platform_set_drvdata(pdev, phy); -+ -+ ret = k3_phy_calibrate(phy->apb_spare); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to calibrate phy"); -+ -+ ret = k3_combo_phy_init_lanes(phy, config); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to init lanes"); -+ -+ provider = devm_of_phy_provider_register(dev, k3_combo_phy_xlate); -+ if (IS_ERR(provider)) -+ return dev_err_probe(dev, PTR_ERR(provider), -+ "Failed to register provider\n"); -+ -+ return 0; -+} -+ -+static const struct of_device_id k3_combo_phy_of_match[] = { -+ { .compatible = "spacemit,k3-combo-phy" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, k3_combo_phy_of_match); -+ -+static struct platform_driver k3_combo_phy_driver = { -+ .probe = k3_combo_phy_probe, -+ .driver = { -+ .name = "spacemit,k3-combo-phy", -+ .of_match_table = k3_combo_phy_of_match, -+ }, -+}; -+module_platform_driver(k3_combo_phy_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K3 USB3/PCIe combo PHY driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/phy/spacemit/phy-k3-common.c b/drivers/phy/spacemit/phy-k3-common.c -new file mode 100644 -index 000000000000..840524cbe533 ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-common.c -@@ -0,0 +1,372 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "phy-k3-common.h" -+ -+/* PHY Registers */ -+#define PHY_VERSION 0x0 -+ -+#define PHY_RESET_CFG 0x04 -+ -+#define PHY_RESET_RXBUF_RST BIT(0) -+#define PHY_RESET_SOFT_RST_PCS BIT(1) -+#define PHY_RESET_SOFT_RST_AHB BIT(2) -+#define PHY_RESET_EN_SD_AFTER_LOCK BIT(6) -+ -+#define PHY_CLK_CFG 0x08 -+ -+#define PHY_CLK_PLL_READY BIT(0) -+#define PHY_CLK_TXCLK_INV BIT(2) -+#define PHY_CLK_RXCLK_EN BIT(3) -+#define PHY_CLK_TXCLK_EN BIT(4) -+#define PHY_CLK_PCLK_EN BIT(5) -+#define PHY_CLK_PIPE_PCLK_EN BIT(6) -+#define PHY_CLK_REFCLK_FREQ GENMASK(10, 7) -+#define PHY_CLK_REFCLK_24M 2 -+#define PHY_CLK_SW_INIT_DONE BIT(11) -+#define PHY_CLK_PU_SSC_OUT BIT(23) -+ -+#define PHY_MODE_CFG 0x0C -+ -+#define PHY_MODE_PCIE_INT_EN BIT(0) -+#define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8) -+#define PHY_MODE_LFPS_TPERIOD_USB 3 -+ -+#define PHY_PU_SEL 0x40 -+ -+#define PHY_PU_CFG_STATUS BIT(9) -+#define PHY_PU_OVRD_STATUS BIT(10) -+ -+#define PHY_PU_CK_REG 0x54 -+ -+#define PHY_PU_REFCLK_100 BIT(25) -+ -+#define PHY_PLL_REG1 0x58 -+ -+#define PHY_PLL_FREF_SEL GENMASK(15, 13) -+#define PHY_PLL_FREF_24M 0x1 -+#define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24) -+#define PHY_PLL_SSC_5000PPM 0xa -+#define PHY_PLL_SSC_MODE GENMASK(29, 28) -+#define PHY_PLL_SSC_MODE_CENTER_SPREAD 0 -+#define PHY_PLL_SSC_MODE_UP_SPREAD 1 -+#define PHY_PLL_SSC_MODE_DOWN_SPREAD 2 -+#define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3 -+ -+#define PHY_PLL_REG2 0x5c -+ -+#define PHY_PLL_SEL_REF100 BIT(21) -+ -+/* PHY RX Register Definitions */ -+#define PHY_RX_REG_A 0x60 -+ -+#define PHY_RX_REG0_RLOAD BIT(4) -+#define PHY_RX_REG1_RTERM GENMASK(11, 8) -+#define PHY_RX_REG1_RC_CALI GENMASK(15, 12) -+#define PHY_RX_REG2_CSEL GENMASK(19, 16) -+#define PHY_RX_REG2_FORCE_CSEL BIT(20) -+#define PHY_RX_REG2_PSEL GENMASK(23, 21) -+#define PHY_RX_REG3_I_LOAD GENMASK(26, 24) -+#define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27) -+#define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28) -+#define PHY_RX_REG3_RDEG1 GENMASK(31, 30) -+ -+#define PHY_RX_REG_B 0x64 -+ -+#define PHY_RX_REGB_MASK GENMASK(23, 0) -+ -+#define PHY_RX_REG4_RDEG2 GENMASK(2, 1) -+#define PHY_RX_REG4_ENVOS BIT(4) -+#define PHY_RX_REG4_RTERM_SEL BIT(5) -+#define PHY_RX_REG4_MANUAL_CFG BIT(7) -+#define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8) -+#define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12) -+#define PHY_RX_REG6_H1_REG GENMASK(19, 16) -+#define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20) -+#define PHY_RX_REG6_BYPASS_ADPT BIT(22) -+ -+#define PHY_ADPT_CFG0 0x140 -+#define PHY_ADPT_AFE_RST_OVRD_EN BIT(1) -+#define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4) -+ -+#define PHY_RXEQ_TIME 0xb4 -+#define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21) -+#define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22) -+#define PHY_RXEQ_TIME_AMP_SOC_650M 0 -+#define PHY_RXEQ_TIME_AMP_SOC_800M 1 -+#define PHY_RXEQ_TIME_AMP_SOC_870M 2 -+#define PHY_RXEQ_TIME_AMP_SOC_900M 3 -+#define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24) -+ -+#define PCIE_PU_ADDR_CLK_CFG 0x0008 -+#define PHY_CLK_PLL_READY BIT(0) -+#define PCIE_INITAL_TIMER GENMASK(6, 3) -+#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) -+#define CFG_SW_PHY_INIT_DONE BIT(11) -+ -+/* Lane RX/TX configuration (per‑lane, at lane_base) */ -+#define PCIE_RX_REG1 0x050 -+#define PCIE_TX_REG1 0x064 -+ -+#define PCIE_PLL_TIMEOUT 500000 -+#define PCIE_POLL_DELAY 500 -+ -+static int k3_usb3phy_init_single(struct k3_lane_group *lg, void __iomem *base) -+{ -+ struct phy *phy = lg->phy; -+ u32 val, tmp; -+ int ret; -+ -+ /* Do not wait CDR lock before sampling data */ -+ val = readl(base + PHY_RESET_CFG); -+ val = u32_replace_bits(val, 0, PHY_RESET_EN_SD_AFTER_LOCK); -+ writel(val, base + PHY_RESET_CFG); -+ -+ /* Power down 100MHz refclk buffer */ -+ val = readl(base + PHY_PU_CK_REG); -+ val = u32_replace_bits(val, 0, PHY_PU_REFCLK_100); -+ writel(val, base + PHY_PU_CK_REG); -+ -+ /* Program PLL REG1 configure the SSC */ -+ val = FIELD_PREP(PHY_PLL_SSC_MODE, PHY_PLL_SSC_MODE_DOWN_SPREAD1) | -+ FIELD_PREP(PHY_PLL_SSC_DEP_SEL, PHY_PLL_SSC_5000PPM) | -+ FIELD_PREP(PHY_PLL_FREF_SEL, PHY_PLL_FREF_24M); -+ writel(val, base + PHY_PLL_REG1); -+ -+ /* Un-select 100MHz PLL reference */ -+ val = readl(base + PHY_PLL_REG2); -+ val = u32_replace_bits(val, 0, PHY_PLL_SEL_REF100); -+ writel(val, base + PHY_PLL_REG2); -+ -+ /* USB LFPS period configuration */ -+ val = readl(base + PHY_MODE_CFG); -+ val = u32_replace_bits(val, PHY_MODE_LFPS_TPERIOD_USB, PHY_MODE_LFPS_TPERIOD); -+ writel(val, base + PHY_MODE_CFG); -+ -+ /* Force AFE adaptation reset */ -+ val = readl(base + PHY_ADPT_CFG0); -+ val |= PHY_ADPT_AFE_RST_OVRD_EN | PHY_ADPT_AFE_RST_OVRD_VAL; -+ writel(val, base + PHY_ADPT_CFG0); -+ -+ /* Override driver amplitude value to 900m */ -+ val = readl(base + PHY_RXEQ_TIME); -+ val |= PHY_RXEQ_TIME_OVRD_AMP_SOC; -+ val = u32_replace_bits(val, PHY_RXEQ_TIME_AMP_SOC_900M, PHY_RXEQ_TIME_CFG_AMP_SOC); -+ writel(val, base + PHY_RXEQ_TIME); -+ -+ /* Configure RX parameters */ -+ val = PHY_RX_REG0_RLOAD | -+ FIELD_PREP(PHY_RX_REG1_RTERM, 0x8) | -+ FIELD_PREP(PHY_RX_REG1_RC_CALI, 0x7) | -+ FIELD_PREP(PHY_RX_REG2_CSEL, 0x8) | -+ PHY_RX_REG2_FORCE_CSEL | -+ FIELD_PREP(PHY_RX_REG2_PSEL, 0x4) | -+ FIELD_PREP(PHY_RX_REG3_I_LOAD, 0x7) | -+ PHY_RX_REG3_SEL_CBOOST_CODE | -+ FIELD_PREP(PHY_RX_REG3_ADJ_BIAS, 0x1) | -+ FIELD_PREP(PHY_RX_REG3_RDEG1, 0x3); -+ writel(val, base + PHY_RX_REG_A); -+ -+ val = readl(base + PHY_RX_REG_B); -+ tmp = FIELD_PREP(PHY_RX_REG4_RDEG2, 0x2) | -+ PHY_RX_REG4_ENVOS | PHY_RX_REG4_RTERM_SEL | PHY_RX_REG4_MANUAL_CFG | -+ FIELD_PREP(PHY_RX_REG5_RCELL_VCM, 0x8) | -+ FIELD_PREP(PHY_RX_REG5_RCELL_BIAS, 0x8) | -+ FIELD_PREP(PHY_RX_REG6_H1_REG, 0x8) | -+ FIELD_PREP(PHY_RX_REG6_ADAPT_GAIN, 0x2); -+ val = u32_replace_bits(val, tmp, PHY_RX_REGB_MASK); -+ writel(val, base + PHY_RX_REG_B); -+ -+ /* -+ * Inform PHY that all PLL-related configuration is done. -+ * PLL will not start locking until PHY_CLK_SW_INIT_DONE is set. -+ */ -+ val = PHY_CLK_SW_INIT_DONE | PHY_CLK_PU_SSC_OUT | -+ FIELD_PREP(PHY_CLK_REFCLK_FREQ, PHY_CLK_REFCLK_24M) | -+ PHY_CLK_RXCLK_EN | PHY_CLK_TXCLK_EN | -+ PHY_CLK_PCLK_EN | PHY_CLK_PIPE_PCLK_EN; -+ writel(val, base + PHY_CLK_CFG); -+ -+ ret = readl_poll_timeout(base + PHY_CLK_CFG, val, -+ (val & PHY_CLK_PLL_READY), -+ PCIE_POLL_DELAY, PCIE_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(&phy->dev, "PHY PLL polling timeout\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int k3_usb3phy_init(struct phy *phy) -+{ -+ struct k3_lane_group *lg = phy_get_drvdata(phy); -+ int ret, i; -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ ret = k3_usb3phy_init_single(lg, lg->base + lg->data->offsets[i]); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+const struct phy_ops k3_usb3_phy_ops = { -+ .init = k3_usb3phy_init, -+ .owner = THIS_MODULE, -+}; -+EXPORT_SYMBOL_GPL(k3_usb3_phy_ops); -+ -+static int k3_pcie_phy_init(struct phy *phy) -+{ -+ struct k3_lane_group *lg = phy_get_drvdata(phy); -+ void __iomem *phy_base = lg->base + lg->data->offsets[0]; -+ u32 val; -+ int ret; -+ int i; -+ -+ val = readl(phy_base + PHY_PLL_REG1); -+ val = u32_replace_bits(val, 0x2, GENMASK(15, 12)); -+ writel(val, phy_base + PHY_PLL_REG1); -+ -+ val = readl(phy_base + PHY_PLL_REG2); -+ val = u32_replace_bits(val, 0, BIT(21)); -+ writel(val, phy_base + PHY_PLL_REG2); -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ void __iomem *lane_base = lg->base + lg->data->offsets[i]; -+ -+ val = readl(lane_base + PCIE_RX_REG1); -+ val = u32_replace_bits(val, 0, 0x3); -+ writel(val, lane_base + PCIE_RX_REG1); -+ } -+ -+ val = readl(phy_base + PHY_PLL_REG2); -+ val |= BIT(20); -+ writel(val, phy_base + PHY_PLL_REG2); -+ -+ writel(0x00006505, phy_base + PCIE_RX_REG1); -+ -+ /* pll_reg1 of lane0, disable SSC: pll[27:24] = 0 */ -+ val = readl(phy_base + PHY_PLL_REG1); -+ val = u32_replace_bits(val, 0, GENMASK(27, 24)); -+ writel(val, phy_base + PHY_PLL_REG1); -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ void __iomem *lane_base = lg->base + lg->data->offsets[i]; -+ -+ /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */ -+ val = readl(lane_base + PHY_PU_SEL); -+ val = u32_replace_bits(val, 1, BIT(13)); -+ writel(val, lane_base + PHY_PU_SEL); -+ -+ /* disable en_sample_data_after_cdr_locked */ -+ val = readl(lane_base + PHY_RESET_CFG); -+ val = u32_replace_bits(val, 0, BIT(6)); -+ writel(val, lane_base + PHY_RESET_CFG); -+ -+ /* Dynamic Lock */ -+ val = readl(lane_base + PHY_MODE_CFG); -+ val = u32_replace_bits(val, 1, BIT(2)); -+ writel(val, lane_base + PHY_MODE_CFG); -+ -+ val = FIELD_PREP(GENMASK(7, 0), 0x10) | -+ FIELD_PREP(GENMASK(15, 8), 0x78) | -+ FIELD_PREP(GENMASK(23, 16), 0x98) | -+ FIELD_PREP(GENMASK(31, 24), 0xdf); -+ writel(val, lane_base + PHY_RX_REG_A); -+ -+ val = readl(lane_base + PHY_RX_REG_B); -+ val &= ~PHY_RX_REGB_MASK; -+ val |= FIELD_PREP(GENMASK(7, 0), 0xb4) | -+ FIELD_PREP(GENMASK(15, 8), 0x88) | -+ FIELD_PREP(GENMASK(23, 16), 0x28); -+ writel(val, lane_base + PHY_RX_REG_B); -+ -+ /* Set init done */ -+ val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG); -+ val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE); -+ writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG); -+ } -+ -+ ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val, -+ (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY, -+ PCIE_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(&lg->phy->dev, "PHY PLL lock timeout\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+const struct phy_ops k3_pcie_phy_ops = { -+ .init = k3_pcie_phy_init, -+ .owner = THIS_MODULE, -+}; -+EXPORT_SYMBOL_GPL(k3_pcie_phy_ops); -+ -+/* PHY rcal init requires APB_SPARE regmap access */ -+ -+#define APB_SPARE_PU_CAL 0x178 -+#define PU_CAL BIT(17) -+ -+#define APB_SPARE_RCAL_HSIO 0x17c -+#define APB_SPARE_PU_CAL_DONE BIT(8) -+#define RCAL_OVRD_PTRIM GENMASK(23, 20) -+#define RCAL_OVRD_NTRIM GENMASK(27, 24) -+#define RCAL_OVRD_PTRIM_EN BIT(28) -+#define RCAL_OVRD_NTRIM_EN BIT(29) -+#define RCAL_OVRD_STABLE_VAL BIT(30) -+#define RCAL_OVRD_STABLE_EN BIT(31) -+ -+#define RCAL_OVRD_TRIM_EN (RCAL_OVRD_NTRIM_EN | RCAL_OVRD_PTRIM_EN) -+#define RCAL_OVRD_TRIM_MASK (RCAL_OVRD_NTRIM | RCAL_OVRD_PTRIM) -+ -+#define PU_CAL_TIMEOUT 2000000 -+ -+static DEFINE_MUTEX(calibrate_lock); -+ -+int k3_phy_calibrate(struct regmap *apb_spare) -+{ -+ unsigned int val = 0; -+ int ret; -+ -+ guard(mutex)(&calibrate_lock); -+ -+ regmap_read(apb_spare, APB_SPARE_RCAL_HSIO, &val); -+ if (val & APB_SPARE_PU_CAL_DONE) -+ return 0; -+ -+ regmap_update_bits(apb_spare, APB_SPARE_PU_CAL, PU_CAL, -+ PU_CAL); -+ -+ ret = regmap_read_poll_timeout(apb_spare, APB_SPARE_RCAL_HSIO, -+ val, (val & APB_SPARE_PU_CAL_DONE), PCIE_POLL_DELAY, -+ PU_CAL_TIMEOUT); -+ -+ if (ret) -+ regmap_update_bits(apb_spare, APB_SPARE_RCAL_HSIO, -+ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | -+ RCAL_OVRD_TRIM_MASK | RCAL_OVRD_STABLE_EN, -+ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | -+ FIELD_PREP(RCAL_OVRD_NTRIM, 0x6) | -+ FIELD_PREP(RCAL_OVRD_PTRIM, 0xa) | -+ RCAL_OVRD_STABLE_EN); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(k3_phy_calibrate); -+ -+MODULE_DESCRIPTION("SpacemiT K3 PHY common ops"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/phy/spacemit/phy-k3-common.h b/drivers/phy/spacemit/phy-k3-common.h -new file mode 100644 -index 000000000000..49009c3c313a ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-common.h -@@ -0,0 +1,27 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef _PHY_K3_COMMON_H -+#define _PHY_K3_COMMON_H -+ -+#include -+ -+struct k3_phy_lane_group_data { -+ u32 lanes; -+ u8 config; -+ u8 mask; -+ u32 offsets[] __counted_by(lanes); -+}; -+ -+struct k3_lane_group { -+ const struct k3_phy_lane_group_data *data; -+ void __iomem *base; -+ struct phy *phy; -+ bool is_pcie; -+}; -+ -+extern const struct phy_ops k3_pcie_phy_ops; -+extern const struct phy_ops k3_usb3_phy_ops; -+ -+int k3_phy_calibrate(struct regmap *apb_spare); -+ -+#endif --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch b/SPECS/linux-lts-kmhv2/0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch new file mode 100644 index 0000000000..f7231a5dd3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch @@ -0,0 +1,102 @@ +From 360a4acac1e14c683370c4ffa8f3e85733ca0207 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Sat, 24 Jan 2026 08:48:53 +0800 +Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: Add USB2.0 support + +FROM: https://github.com/spacemit-com/linux/commit/6f1578894e4484f8a6724aceff099d2e90450e10 + +The USB2.0 controller on Pico-ITX board connnect to a Terminus FE1.1 Hub +which fully USB2.0 protocol compliant and provides 4 ports. + +Signed-off-by: Yixun Lan +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 25 ++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++ + 2 files changed, 56 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 61cbf924830b..ac965ec83f2c 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -33,6 +33,15 @@ reg_aux_vcc5v: regulator-aux-vcc5v { + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; ++ ++ aux_vcc3v3: regulator-aux-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "AUX_VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + }; + + &i2c8 { +@@ -255,3 +264,19 @@ &uart0 { + pinctrl-0 = <&uart0_0_cfg>; + status = "okay"; + }; ++ ++&usb2_host { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub@1 { ++ compatible = "usb1a40,0101"; ++ reg = <1>; ++ vdd-supply = <&aux_vcc3v3>; ++ }; ++}; ++ ++&usb2_phy { ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index ed046714a7ac..1b86c872accb 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -637,6 +637,37 @@ pdma: dma-controller@d4000000 { + status = "disabled"; + }; + ++ usb2_host: usb@c0a00000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0xc0a00000 0x0 0x10000>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB2_AHB>, ++ <&syscon_apmu RESET_APMU_USB2_VCC>, ++ <&syscon_apmu RESET_APMU_USB2_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ phys = <&usb2_phy>; ++ phy-names = "usb2-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ dr_mode = "host"; ++ maximum-speed = "high-speed"; ++ status = "disabled"; ++ }; ++ ++ usb2_phy: phy@c0a20000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0xc0a20000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0462-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch b/SPECS/linux-lts-kmhv2/0462-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch deleted file mode 100644 index bf914252d4..0000000000 --- a/SPECS/linux-lts-kmhv2/0462-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 115adac703e8d0d67045f2ed4fe1a495ab4b5448 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 27 Feb 2026 09:46:06 +0800 -Subject: [PATCH 462/467] RUYI: riscv: dts: spacemit: k3: add USB controller - and USB phy support - -Add all USB device node to the Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++ - 2 files changed, 55 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index ac965ec83f2c..acfbb5029c15 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -183,6 +183,11 @@ dldo7: dldo7 { - }; - }; - -+&combophy { -+ spacemit,apmu = <&syscon_apmu 0x11>; -+ status = "okay"; -+}; -+ - ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; -@@ -280,3 +285,11 @@ hub@1 { - &usb2_phy { - status = "okay"; - }; -+ -+&usb3d_u2phy { -+ status = "okay"; -+}; -+ -+&usb3d { -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 66dcabd0a815..130828ca3b43 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -7,6 +7,7 @@ - #include - #include - #include -+#include - - /dts-v1/; - -@@ -637,6 +638,47 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ usb3d: usb@81a00000 { -+ compatible = "spacemit,k3-dwc3"; -+ reg = <0x0 0x81a00000 0x0 0x10000>; -+ interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&saplic>; -+ clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; -+ clock-names = "usbdrd30"; -+ resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, -+ <&syscon_apmu RESET_APMU_USB3_D_VCC>, -+ <&syscon_apmu RESET_APMU_USB3_D_PHY>; -+ reset-names = "ahb", "vcc", "phy"; -+ phys = <&usb3d_u2phy>, -+ <&combophy 4 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi"; -+ snps,dis_enblslpm_quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ snps,parkmode-disable-ss-quirk; -+ dr_mode = "host"; -+ status = "disabled"; -+ }; -+ -+ usb3d_u2phy: phy@81b00000 { -+ compatible = "spacemit,k3-usb2-phy"; -+ reg = <0x0 0x81b00000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ combophy: phy@81d00000 { -+ compatible = "spacemit,k3-combo-phy"; -+ reg = <0x0 0x81d00000 0x0 0x600000>; -+ #phy-cells = <2>; -+ spacemit,apb-spare = <&pll>; -+ status = "disabled"; -+ }; -+ - usb2_host: usb@c0a00000 { - compatible = "spacemit,k3-dwc3"; - reg = <0x0 0xc0a00000 0x0 0x10000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0463-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch b/SPECS/linux-lts-kmhv2/0463-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch deleted file mode 100644 index e319ecab6f..0000000000 --- a/SPECS/linux-lts-kmhv2/0463-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch +++ /dev/null @@ -1,261 +0,0 @@ -From 14ecb0eaa2ab52030c7f36a293df59f07bdc1bb0 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Tue, 24 Mar 2026 11:06:24 +0800 -Subject: [PATCH 463/467] RUYI: riscv: dts: spacemit: k3: Add PCIe device node - -Add all PCIe device node for Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 ++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 150 +++++++++++++++++++ - 3 files changed, 212 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index acfbb5029c15..f24ada15f182 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -264,6 +264,35 @@ uboot@210000 { - }; - }; - -+&pcie0_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie0_0_cfg>; -+ phys = <&combophy 0 PHY_TYPE_PCIE>, -+ <&combophy 1 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0", "pcie-phy1"; -+ num-lanes = <4>; -+ status = "okay"; -+}; -+ -+&pcie2_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_cfg>; -+ phys = <&combophy 2 PHY_TYPE_PCIE>, -+ <&combophy 3 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0", "pcie-phy1"; -+ num-lanes = <2>; -+ status = "okay"; -+}; -+ -+&pcie4_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie4_0_cfg>; -+ phys = <&combophy 5 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0"; -+ num-lanes = <1>; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_0_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index 846d5e8cc783..5a817610101b 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -710,4 +710,37 @@ uart0-0-pins { - drive-strength = <25>; - }; - }; -+ -+ pcie0_0_cfg: pcie0-0-cfg { -+ pcie0-0-pins { -+ pinmux = , /* pcie0 perst */ -+ ; /* pcie0 clkreq */ -+ -+ bias-pull-up = <1>; -+ drive-strength = <33>; -+ power-source = <1800>; -+ }; -+ }; -+ -+ pcie2_0_cfg: pcie2-0-cfg { -+ pcie2-0-pins { -+ pinmux = , /* pcie2 perst */ -+ ; /* pcie2 clkreq */ -+ -+ drive-strength = <38>; -+ power-source = <3300>; -+ }; -+ }; -+ -+ pcie4_0_cfg: pcie4-0-cfg { -+ pcie4-0-pins { -+ pinmux = , /* pcie4 perst */ -+ , /* pcie4 wake */ -+ ; /* pcie4 clkreq */ -+ -+ bias-pull-up = <1>; -+ drive-strength = <33>; -+ power-source = <1800>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 130828ca3b43..6adfbd505e9e 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -638,6 +638,156 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ pcie0_rc: pcie@80000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80000000 0x0 0x00001000>, -+ <0x0 0x80100000 0x0 0x00001000>, -+ <0x0 0x80300000 0x0 0x00003f20>, -+ <0x11 0x00000000 0x0 0x00010000>, -+ <0x0 0x82900000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTA_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTA_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTA_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_A_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_A_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_A_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ linux,pci-domain = <0>; -+ spacemit,apmu = <&syscon_apmu 0x1f0>; -+ status = "disabled"; -+ }; -+ -+ pcie1_rc: pcie@80400000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80400000 0x0 0x00001000>, -+ <0x0 0x80500000 0x0 0x00001000>, -+ <0x0 0x80700000 0x0 0x00003f20>, -+ <0x11 0x80000000 0x0 0x00010000>, -+ <0x0 0x82c00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTB_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTB_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTB_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00010000 0x11 0x80010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x80110000 0x11 0x80110000 0x0 0x7fef0000>, -+ <0x43000000 0x16 0x00000000 0x16 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_B_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_B_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_B_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ linux,pci-domain = <1>; -+ spacemit,apmu = <&syscon_apmu 0x1d0>; -+ status = "disabled"; -+ }; -+ -+ pcie2_rc: pcie@80800000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80800000 0x0 0x00001000>, -+ <0x0 0x80900000 0x0 0x00001000>, -+ <0x0 0x80b00000 0x0 0x00003f20>, -+ <0x12 0x00000000 0x0 0x00010000>, -+ <0x0 0x82d00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTC_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTC_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTC_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00000000 0x12 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x12 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x15 0x00000000 0x15 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_C_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_C_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_C_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <2>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1c8>; -+ status = "disabled"; -+ }; -+ -+ pcie3_rc: pcie@80c00000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80c00000 0x0 0x00001000>, -+ <0x0 0x80d00000 0x0 0x00001000>, -+ <0x0 0x80f00000 0x0 0x00003f20>, -+ <0x12 0x80000000 0x0 0x00010000>, -+ <0x0 0x82a00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTD_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTD_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTD_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00010000 0x12 0x80010000 0x0 0x100000>, -+ <0x02000000 0x0 0x80110000 0x12 0x80110000 0x0 0x3fef0000>, -+ <0x43000000 0x14 0x00000000 0x14 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_D_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_D_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_D_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <3>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1e0>; -+ status = "disabled"; -+ }; -+ -+ pcie4_rc: pcie@81000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x81000000 0x0 0x00001000>, -+ <0x0 0x81100000 0x0 0x00001000>, -+ <0x0 0x81300000 0x0 0x00003f20>, -+ <0x12 0xc0000000 0x0 0x00010000>, -+ <0x0 0x82b00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTE_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTE_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTE_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00000000 0x12 0xc0010000 0x0 0x100000>, -+ <0x02000000 0x0 0xc0110000 0x12 0xc0110000 0x0 0x3fef0000>, -+ <0x43000000 0x13 0x00000000 0x13 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_E_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_E_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_E_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <4>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1e8>; -+ status = "disabled"; -+ }; -+ - usb3d: usb@81a00000 { - compatible = "spacemit,k3-dwc3"; - reg = <0x0 0x81a00000 0x0 0x10000>; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch b/SPECS/linux-lts-kmhv2/0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch new file mode 100644 index 0000000000..7871de10b3 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch @@ -0,0 +1,145 @@ +From 8b65d5e0ae467754eccf77dddcd58ae11ea35cdd Mon Sep 17 00:00:00 2001 +From: Zhang Meng +Date: Mon, 5 Jan 2026 20:05:04 +0800 +Subject: [RUYI PATCH] SPACEMIT: riscv: uaccess: don't use vector if buffer is + not cacheable + +FROM: https://github.com/spacemit-com/linux-6.18/commit/9168f7e0c6bfdcfa3b6a64a4d45e3cd68a81618f + +Change-Id: I040d597ee246777767f7be747fa9202154524538 +[ Vivian: Rebase and move check into enter_vector_usercopy ] +Signed-off-by: Vivian Wang +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/uaccess.h | 5 +++ + arch/riscv/lib/Makefile | 1 + + arch/riscv/lib/riscv_v_helpers.c | 5 +++ + arch/riscv/lib/uaccess_cache_check.c | 65 ++++++++++++++++++++++++++++ + 4 files changed, 76 insertions(+) + create mode 100644 arch/riscv/lib/uaccess_cache_check.c + +diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h +index 6aef591a6bfc..b028208b05ec 100644 +--- a/arch/riscv/include/asm/uaccess.h ++++ b/arch/riscv/include/asm/uaccess.h +@@ -487,6 +487,11 @@ static inline void user_access_restore(unsigned long enabled) { } + if (__asm_copy_from_user_sum_enabled(_dst, _src, _len)) \ + goto label; + ++/* Memory cacheability check for vector uaccess optimization */ ++#ifdef CONFIG_RISCV_ISA_V ++int is_cacheable_safe(const void *addr); ++#endif ++ + #else /* CONFIG_MMU */ + #include + #endif /* CONFIG_MMU */ +diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile +index 735d0b665536..43fe69db9803 100644 +--- a/arch/riscv/lib/Makefile ++++ b/arch/riscv/lib/Makefile +@@ -14,6 +14,7 @@ endif + lib-y += csum.o + ifeq ($(CONFIG_MMU), y) + lib-$(CONFIG_RISCV_ISA_V) += uaccess_vector.o ++lib-$(CONFIG_RISCV_ISA_V) += uaccess_cache_check.o + endif + lib-$(CONFIG_MMU) += uaccess.o + lib-$(CONFIG_64BIT) += tishift.o +diff --git a/arch/riscv/lib/riscv_v_helpers.c b/arch/riscv/lib/riscv_v_helpers.c +index 7bbdfc6d4552..7ab2cea280f8 100644 +--- a/arch/riscv/lib/riscv_v_helpers.c ++++ b/arch/riscv/lib/riscv_v_helpers.c +@@ -8,6 +8,7 @@ + + #include + #include ++#include + + #ifdef CONFIG_MMU + #include +@@ -28,6 +29,10 @@ asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n, + if (!may_use_simd()) + goto fallback; + ++ /* HACK */ ++ if (!is_cacheable_safe(dst) || !is_cacheable_safe(src)) ++ goto fallback; ++ + kernel_vector_begin(); + remain = enable_sum ? __asm_vector_usercopy(dst, src, n) : + __asm_vector_usercopy_sum_enabled(dst, src, n); +diff --git a/arch/riscv/lib/uaccess_cache_check.c b/arch/riscv/lib/uaccess_cache_check.c +new file mode 100644 +index 000000000000..0b0996fa2d37 +--- /dev/null ++++ b/arch/riscv/lib/uaccess_cache_check.c +@@ -0,0 +1,65 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Memory cacheability check for RISC-V uaccess optimization ++ * ++ * This file provides a C function that can be called from assembly ++ * to determine if a buffer is cacheable before using vector instructions. ++ */ ++ ++#include ++#include ++#include ++ ++/** ++ * is_cacheable_safe - Check if memory buffer is cacheable ++ * @addr: Virtual address to check (kernel or user space) ++ * ++ * Returns: 1 if cacheable, 0 if non-cacheable ++ * ++ * This function is designed to be called from assembly code in uaccess.S ++ * to determine if vector instructions are safe to use for memory copy. ++ * ++ * Non-cacheable memory (device IO, DMA coherent buffers) should not use ++ * vector instructions as they may cause cache coherency issues. ++ * ++ * Handles both kernel and user space addresses safely: ++ * - Kernel direct mapping: Always cacheable ++ * - Kernel vmalloc: Check VM flags ++ * - User space: Check page table (most are cacheable) ++ * - ioremap/DMA: Non-cacheable ++ */ ++int is_cacheable_safe(const void *addr) ++{ ++ unsigned long vaddr = (unsigned long)addr; ++ ++ /* Kernel direct mapped memory - always cacheable */ ++ if (virt_addr_valid(addr)) ++ return 1; ++ ++ if (vaddr < TASK_SIZE) { ++ /* ++ * User space address, Determine it as a cacheable buffer, ++ * maybe not safe!! ++ */ ++ return 1; ++ } ++ ++ /* Check if it's a vmalloc region (kernel virtual address) */ ++ if (is_vmalloc_addr(addr)) { ++ struct vm_struct *vm; ++ ++ vm = find_vm_area(addr); ++ if (!vm) ++ return 0; ++ ++ /* Exclude ioremap and DMA coherent buffers */ ++ if (vm->flags & (VM_IOREMAP | VM_DMA_COHERENT)) ++ return 0; ++ ++ /* Normal vmalloc - cacheable */ ++ return 1; ++ } ++ ++ /* Unknown kernel region - assume non-cacheable for safety */ ++ return 0; ++} +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0464-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch b/SPECS/linux-lts-kmhv2/0464-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch deleted file mode 100644 index cd7020b4ac..0000000000 --- a/SPECS/linux-lts-kmhv2/0464-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch +++ /dev/null @@ -1,34 +0,0 @@ -From a36a6a20bb6a9f93f79425be30e4469453576929 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 20 May 2026 23:28:15 +0800 -Subject: [PATCH 464/467] RUYI: PCI: add SpacemiT vendor id and its K3 device - id to pci_ids - -The SpacemiT K3 chip's root complex needs to be listed in the allowlist -of rtw89 driver to allow 36-bit DMA. - -Add the vendor and device IDs to pci_ids.h header file. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - include/linux/pci_ids.h | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h -index 7c01548a6ddb..e5a5700f7c8c 100644 ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -2643,6 +2643,9 @@ - #define PCI_VENDOR_ID_SUNIX 0x1fd4 - #define PCI_DEVICE_ID_SUNIX_1999 0x1999 - -+#define PCI_VENDOR_ID_SPACEMIT 0x201f -+#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 -+ - #define PCI_VENDOR_ID_HINT 0x3388 - #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch b/SPECS/linux-lts-kmhv2/0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch new file mode 100644 index 0000000000..2a03ed4e12 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch @@ -0,0 +1,90 @@ +From 675808049c603e6935816557a160a1d7f6eb5495 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 13 Feb 2026 09:01:58 +0800 +Subject: [RUYI PATCH] RUYI: dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb + phy support + +The USB3/PCIe comb PHY on the K3 is a complex PHY group that +can provide multiple phy for both PCIe and USB controller. +Its mux configuration is controlled by the APMU syscon device. + +Signed-off-by: Inochi Amaoto +Signed-off-by: Han Gao +--- + .../bindings/phy/spacemit,k3-combo-phy.yaml | 64 +++++++++++++++++++ + 1 file changed, 64 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml +new file mode 100644 +index 000000000000..eafc753b7e9b +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml +@@ -0,0 +1,64 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Spacemit K3 PCIE/USB3 Comb PHY ++ ++maintainers: ++ - Inochi Amaoto ++ ++properties: ++ compatible: ++ const: spacemit,k3-combo-phy ++ ++ reg: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 2 ++ description: ++ The first one is phy id, the second one is phy type. ++ ++ spacemit,apb-spare: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: ++ Phandle to APB SPARE system controller interface, used for ++ PHY calibration. ++ ++ spacemit,apmu: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle of APMU syscon ++ - description: configuration of the PHY lanes ++ description: | ++ Phandle to control PHY mux configuration. The configuration ++ is described as follows: ++ bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode ++ bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode ++ bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode ++ bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode ++ bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode ++ ++ The bit[3:0] is only valid when bit 4 is 1. ++ ++required: ++ - compatible ++ - reg ++ - "#phy-cells" ++ - spacemit,apb-spare ++ - spacemit,apmu ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@81d00000 { ++ compatible = "spacemit,k3-combo-phy"; ++ reg = <0x81d00000 0x600000>; ++ #phy-cells = <2>; ++ spacemit,apb-spare = <&apb_spare>; ++ spacemit,apmu = <&apmu 0x00>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch b/SPECS/linux-lts-kmhv2/0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch new file mode 100644 index 0000000000..4c1686add5 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch @@ -0,0 +1,730 @@ +From 4ee622c1f03b3a5e9d6df7f54f612202f9462d8c Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 13 Feb 2026 09:09:58 +0800 +Subject: [RUYI PATCH] RUYI: phy: spacemit: Add USB3/PCIe comb PHY driver for + Spacemit K3 + +The comb PHY on K3 requires to configure a syscon device for the +right mux configuration. And it requires calibration before any +usage. + +Add USB3/PCIe comb PHY driver for Spacemit K3. + +Signed-off-by: Inochi Amaoto +Signed-off-by: Han Gao +--- + drivers/phy/spacemit/Kconfig | 16 ++ + drivers/phy/spacemit/Makefile | 2 + + drivers/phy/spacemit/phy-k3-combo.c | 252 ++++++++++++++++++ + drivers/phy/spacemit/phy-k3-common.c | 372 +++++++++++++++++++++++++++ + drivers/phy/spacemit/phy-k3-common.h | 27 ++ + 5 files changed, 669 insertions(+) + create mode 100644 drivers/phy/spacemit/phy-k3-combo.c + create mode 100644 drivers/phy/spacemit/phy-k3-common.c + create mode 100644 drivers/phy/spacemit/phy-k3-common.h + +diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig +index 0136aee2e8a2..9a1e25592f25 100644 +--- a/drivers/phy/spacemit/Kconfig ++++ b/drivers/phy/spacemit/Kconfig +@@ -11,3 +11,19 @@ config PHY_SPACEMIT_K1_USB2 + help + Enable this to support K1 USB 2.0 PHY driver. This driver takes care of + enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. ++ ++config PHY_SPACEMIT_K3_COMMON_OPS ++ tristate ++ select MFD_SYSCON ++ select GENERIC_PHY ++ ++config PHY_SPACEMIT_K3_COMBO_PHY ++ tristate "SpacemiT K3 USB3/PCIe PHY support" ++ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF ++ depends on COMMON_CLK ++ select PHY_SPACEMIT_K3_COMMON_OPS ++ help ++ Enable this to support K3 USB3/PCIe combo PHY driver. This ++ driver takes care of enabling and clock setup and will be used ++ by K3 dwc3 driver. ++ If unsure, say N. +diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile +index fec0b425a948..df9b609d066f 100644 +--- a/drivers/phy/spacemit/Makefile ++++ b/drivers/phy/spacemit/Makefile +@@ -1,2 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o ++obj-$(CONFIG_PHY_SPACEMIT_K3_COMBO_PHY) += phy-k3-combo.o ++obj-$(CONFIG_PHY_SPACEMIT_K3_COMMON_OPS) += phy-k3-common.o +diff --git a/drivers/phy/spacemit/phy-k3-combo.c b/drivers/phy/spacemit/phy-k3-combo.c +new file mode 100644 +index 000000000000..abd0aad18893 +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-combo.c +@@ -0,0 +1,252 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * phy-k3-usb3.c - SpacemiT K3 Type-C Orientation Switch Driver ++ * ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-k3-common.h" ++ ++/* ++ * The PCIE/USB Subsystem on SpacemiT K3 have 3 single lane PIPE3 PHYs ++ * (PHY2/3/4) shared by PCIE PortC/D and USB3 PortB/C/D. ++ * ++ * PMUA_PCIE_SUBSYS_MGMT[4:0] ++ * ++ * bit4 = 0 : PCIe A X8 mode, all 8 lanes dedicated to PCIe Port A ++ * 1 : PHY lanes shared between PCIe or USB according to [3:0] ++ * ++ * All PHY matrix combinations according to [4:0]: ++ * ++ * 0x0X : PCIe-A X8 ++ * 0x10 : PCIe-C x2 (PHY2+PHY3) + PCIe-D x1 (PHY4) ++ * 0x11 : PCIe-C x2 (PHY2+PHY3) + USB-D (PHY4) ++ * 0x12 : PCIe-C x1 (PHY2) + USB-C (PHY3) ++ * 0x13 : PCIe-C x1 (PHY2) + USB-C (PHY3) + USB-D (PHY4) ++ * 0x14 : PCIe-C x1 (PHY3) + USB-B (PHY2) ++ * 0x15 : PCIe-C x1 (PHY3) + USB-B (PHY2) + USB-D (PHY4) ++ * 0x16 : USB-B (PHY2) + USB-C (PHY3) + PCIe D x1 (PHY4) ++ * 0x17 : USB-B (PHY2) + USB-C (PHY3) + USB-D (PHY4) ++ * ++ * So any USB Port B/C/D operation requires PCIe A X8 mode to be disabled. ++ */ ++#define PMUA_PCIE_SUBSYS_MGMT 0x1d8 ++#define PU_MATRIX_CONF_MASK GENMASK(4, 0) ++ ++#define COMBPHY_MAX_SUBPHYS 6 ++ ++struct k3_combo_phy { ++ struct device *dev; ++ struct k3_lane_group groups[COMBPHY_MAX_SUBPHYS]; ++ void __iomem *base; ++ struct regmap *apb_spare; ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group0 = { ++ .lanes = 2, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x0, 0x400 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group1 = { ++ .lanes = 2, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x100000, 0x100400 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group2 = { ++ .lanes = 1, ++ .config = 0x14, ++ .mask = 0x14, ++ .offsets = { ++ 0x200000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group3 = { ++ .lanes = 1, ++ .config = 0x12, ++ .mask = 0x12, ++ .offsets = { ++ 0x300000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group4 = { ++ .lanes = 1, ++ .config = 0x11, ++ .mask = 0x11, ++ .offsets = { ++ 0x400000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group5 = { ++ .lanes = 1, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x500000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data *k3_combphy_lane_datas[] = { ++ &k3_combphy_lane_group0, ++ &k3_combphy_lane_group1, ++ &k3_combphy_lane_group2, ++ &k3_combphy_lane_group3, ++ &k3_combphy_lane_group4, ++ &k3_combphy_lane_group5, ++}; ++ ++static int k3_combo_phy_init_lanes(struct k3_combo_phy *phy, unsigned int config) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(k3_combphy_lane_datas); i++) { ++ const struct k3_phy_lane_group_data *data = k3_combphy_lane_datas[i]; ++ struct k3_lane_group *lg = &phy->groups[i]; ++ const struct phy_ops *ops; ++ bool is_usb; ++ ++ is_usb = (data->mask & config) == data->config; ++ if (is_usb) ++ ops = &k3_usb3_phy_ops; ++ else ++ ops = &k3_pcie_phy_ops; ++ ++ dev_dbg(phy->dev, "phy %d is %s\n", i, is_usb ? "usb" : "pcie"); ++ ++ lg->phy = devm_phy_create(phy->dev, NULL, ops); ++ if (IS_ERR(lg->phy)) ++ return PTR_ERR(lg->phy); ++ ++ lg->is_pcie = !is_usb; ++ lg->data = data; ++ lg->base = phy->base; ++ phy_set_drvdata(lg->phy, lg); ++ } ++ ++ return 0; ++} ++ ++static int k3_combo_phy_update_config(struct regmap *apmu, unsigned int config) ++{ ++ if (config & ~PU_MATRIX_CONF_MASK) ++ return -EINVAL; ++ ++ return regmap_update_bits(apmu, PMUA_PCIE_SUBSYS_MGMT, PU_MATRIX_CONF_MASK, config); ++} ++ ++static struct phy *k3_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) ++{ ++ struct k3_combo_phy *phy = dev_get_drvdata(dev); ++ struct k3_lane_group *lg; ++ ++ if (args->args_count != 2) { ++ dev_err(dev, "Invalid number of arguments\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (args->args[0] >= ARRAY_SIZE(k3_combphy_lane_datas)) { ++ dev_err(dev, "Invalid PHY id\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ lg = &phy->groups[args->args[0]]; ++ ++ if ((lg->is_pcie && args->args[1] != PHY_TYPE_PCIE) || ++ (!lg->is_pcie && args->args[1] != PHY_TYPE_USB3)) { ++ dev_err(dev, "Invalid PHY mode\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ return lg->phy; ++} ++ ++static int k3_combo_phy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct phy_provider *provider; ++ struct k3_combo_phy *phy; ++ struct regmap *apmu; ++ u32 config = 0; ++ int ret; ++ ++ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); ++ if (!phy) ++ return -ENOMEM; ++ ++ phy->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(phy->base)) ++ return PTR_ERR(phy->base); ++ ++ phy->apb_spare = syscon_regmap_lookup_by_phandle(node, "spacemit,apb-spare"); ++ if (IS_ERR(phy->apb_spare)) ++ return dev_err_probe(dev, PTR_ERR(phy->apb_spare), ++ "Failed to fine APB SPARE syscon"); ++ ++ apmu = syscon_regmap_lookup_by_phandle_args(node, "spacemit,apmu", 1, &config); ++ if (IS_ERR(apmu)) ++ return dev_err_probe(dev, PTR_ERR(apmu), ++ "Failed to find APMU syscon"); ++ ++ ret = k3_combo_phy_update_config(apmu, config); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to set lane configuration"); ++ ++ phy->dev = dev; ++ platform_set_drvdata(pdev, phy); ++ ++ ret = k3_phy_calibrate(phy->apb_spare); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to calibrate phy"); ++ ++ ret = k3_combo_phy_init_lanes(phy, config); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to init lanes"); ++ ++ provider = devm_of_phy_provider_register(dev, k3_combo_phy_xlate); ++ if (IS_ERR(provider)) ++ return dev_err_probe(dev, PTR_ERR(provider), ++ "Failed to register provider\n"); ++ ++ return 0; ++} ++ ++static const struct of_device_id k3_combo_phy_of_match[] = { ++ { .compatible = "spacemit,k3-combo-phy" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, k3_combo_phy_of_match); ++ ++static struct platform_driver k3_combo_phy_driver = { ++ .probe = k3_combo_phy_probe, ++ .driver = { ++ .name = "spacemit,k3-combo-phy", ++ .of_match_table = k3_combo_phy_of_match, ++ }, ++}; ++module_platform_driver(k3_combo_phy_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K3 USB3/PCIe combo PHY driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/phy/spacemit/phy-k3-common.c b/drivers/phy/spacemit/phy-k3-common.c +new file mode 100644 +index 000000000000..840524cbe533 +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-common.c +@@ -0,0 +1,372 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-k3-common.h" ++ ++/* PHY Registers */ ++#define PHY_VERSION 0x0 ++ ++#define PHY_RESET_CFG 0x04 ++ ++#define PHY_RESET_RXBUF_RST BIT(0) ++#define PHY_RESET_SOFT_RST_PCS BIT(1) ++#define PHY_RESET_SOFT_RST_AHB BIT(2) ++#define PHY_RESET_EN_SD_AFTER_LOCK BIT(6) ++ ++#define PHY_CLK_CFG 0x08 ++ ++#define PHY_CLK_PLL_READY BIT(0) ++#define PHY_CLK_TXCLK_INV BIT(2) ++#define PHY_CLK_RXCLK_EN BIT(3) ++#define PHY_CLK_TXCLK_EN BIT(4) ++#define PHY_CLK_PCLK_EN BIT(5) ++#define PHY_CLK_PIPE_PCLK_EN BIT(6) ++#define PHY_CLK_REFCLK_FREQ GENMASK(10, 7) ++#define PHY_CLK_REFCLK_24M 2 ++#define PHY_CLK_SW_INIT_DONE BIT(11) ++#define PHY_CLK_PU_SSC_OUT BIT(23) ++ ++#define PHY_MODE_CFG 0x0C ++ ++#define PHY_MODE_PCIE_INT_EN BIT(0) ++#define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8) ++#define PHY_MODE_LFPS_TPERIOD_USB 3 ++ ++#define PHY_PU_SEL 0x40 ++ ++#define PHY_PU_CFG_STATUS BIT(9) ++#define PHY_PU_OVRD_STATUS BIT(10) ++ ++#define PHY_PU_CK_REG 0x54 ++ ++#define PHY_PU_REFCLK_100 BIT(25) ++ ++#define PHY_PLL_REG1 0x58 ++ ++#define PHY_PLL_FREF_SEL GENMASK(15, 13) ++#define PHY_PLL_FREF_24M 0x1 ++#define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24) ++#define PHY_PLL_SSC_5000PPM 0xa ++#define PHY_PLL_SSC_MODE GENMASK(29, 28) ++#define PHY_PLL_SSC_MODE_CENTER_SPREAD 0 ++#define PHY_PLL_SSC_MODE_UP_SPREAD 1 ++#define PHY_PLL_SSC_MODE_DOWN_SPREAD 2 ++#define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3 ++ ++#define PHY_PLL_REG2 0x5c ++ ++#define PHY_PLL_SEL_REF100 BIT(21) ++ ++/* PHY RX Register Definitions */ ++#define PHY_RX_REG_A 0x60 ++ ++#define PHY_RX_REG0_RLOAD BIT(4) ++#define PHY_RX_REG1_RTERM GENMASK(11, 8) ++#define PHY_RX_REG1_RC_CALI GENMASK(15, 12) ++#define PHY_RX_REG2_CSEL GENMASK(19, 16) ++#define PHY_RX_REG2_FORCE_CSEL BIT(20) ++#define PHY_RX_REG2_PSEL GENMASK(23, 21) ++#define PHY_RX_REG3_I_LOAD GENMASK(26, 24) ++#define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27) ++#define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28) ++#define PHY_RX_REG3_RDEG1 GENMASK(31, 30) ++ ++#define PHY_RX_REG_B 0x64 ++ ++#define PHY_RX_REGB_MASK GENMASK(23, 0) ++ ++#define PHY_RX_REG4_RDEG2 GENMASK(2, 1) ++#define PHY_RX_REG4_ENVOS BIT(4) ++#define PHY_RX_REG4_RTERM_SEL BIT(5) ++#define PHY_RX_REG4_MANUAL_CFG BIT(7) ++#define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8) ++#define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12) ++#define PHY_RX_REG6_H1_REG GENMASK(19, 16) ++#define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20) ++#define PHY_RX_REG6_BYPASS_ADPT BIT(22) ++ ++#define PHY_ADPT_CFG0 0x140 ++#define PHY_ADPT_AFE_RST_OVRD_EN BIT(1) ++#define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4) ++ ++#define PHY_RXEQ_TIME 0xb4 ++#define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21) ++#define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22) ++#define PHY_RXEQ_TIME_AMP_SOC_650M 0 ++#define PHY_RXEQ_TIME_AMP_SOC_800M 1 ++#define PHY_RXEQ_TIME_AMP_SOC_870M 2 ++#define PHY_RXEQ_TIME_AMP_SOC_900M 3 ++#define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24) ++ ++#define PCIE_PU_ADDR_CLK_CFG 0x0008 ++#define PHY_CLK_PLL_READY BIT(0) ++#define PCIE_INITAL_TIMER GENMASK(6, 3) ++#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) ++#define CFG_SW_PHY_INIT_DONE BIT(11) ++ ++/* Lane RX/TX configuration (per‑lane, at lane_base) */ ++#define PCIE_RX_REG1 0x050 ++#define PCIE_TX_REG1 0x064 ++ ++#define PCIE_PLL_TIMEOUT 500000 ++#define PCIE_POLL_DELAY 500 ++ ++static int k3_usb3phy_init_single(struct k3_lane_group *lg, void __iomem *base) ++{ ++ struct phy *phy = lg->phy; ++ u32 val, tmp; ++ int ret; ++ ++ /* Do not wait CDR lock before sampling data */ ++ val = readl(base + PHY_RESET_CFG); ++ val = u32_replace_bits(val, 0, PHY_RESET_EN_SD_AFTER_LOCK); ++ writel(val, base + PHY_RESET_CFG); ++ ++ /* Power down 100MHz refclk buffer */ ++ val = readl(base + PHY_PU_CK_REG); ++ val = u32_replace_bits(val, 0, PHY_PU_REFCLK_100); ++ writel(val, base + PHY_PU_CK_REG); ++ ++ /* Program PLL REG1 configure the SSC */ ++ val = FIELD_PREP(PHY_PLL_SSC_MODE, PHY_PLL_SSC_MODE_DOWN_SPREAD1) | ++ FIELD_PREP(PHY_PLL_SSC_DEP_SEL, PHY_PLL_SSC_5000PPM) | ++ FIELD_PREP(PHY_PLL_FREF_SEL, PHY_PLL_FREF_24M); ++ writel(val, base + PHY_PLL_REG1); ++ ++ /* Un-select 100MHz PLL reference */ ++ val = readl(base + PHY_PLL_REG2); ++ val = u32_replace_bits(val, 0, PHY_PLL_SEL_REF100); ++ writel(val, base + PHY_PLL_REG2); ++ ++ /* USB LFPS period configuration */ ++ val = readl(base + PHY_MODE_CFG); ++ val = u32_replace_bits(val, PHY_MODE_LFPS_TPERIOD_USB, PHY_MODE_LFPS_TPERIOD); ++ writel(val, base + PHY_MODE_CFG); ++ ++ /* Force AFE adaptation reset */ ++ val = readl(base + PHY_ADPT_CFG0); ++ val |= PHY_ADPT_AFE_RST_OVRD_EN | PHY_ADPT_AFE_RST_OVRD_VAL; ++ writel(val, base + PHY_ADPT_CFG0); ++ ++ /* Override driver amplitude value to 900m */ ++ val = readl(base + PHY_RXEQ_TIME); ++ val |= PHY_RXEQ_TIME_OVRD_AMP_SOC; ++ val = u32_replace_bits(val, PHY_RXEQ_TIME_AMP_SOC_900M, PHY_RXEQ_TIME_CFG_AMP_SOC); ++ writel(val, base + PHY_RXEQ_TIME); ++ ++ /* Configure RX parameters */ ++ val = PHY_RX_REG0_RLOAD | ++ FIELD_PREP(PHY_RX_REG1_RTERM, 0x8) | ++ FIELD_PREP(PHY_RX_REG1_RC_CALI, 0x7) | ++ FIELD_PREP(PHY_RX_REG2_CSEL, 0x8) | ++ PHY_RX_REG2_FORCE_CSEL | ++ FIELD_PREP(PHY_RX_REG2_PSEL, 0x4) | ++ FIELD_PREP(PHY_RX_REG3_I_LOAD, 0x7) | ++ PHY_RX_REG3_SEL_CBOOST_CODE | ++ FIELD_PREP(PHY_RX_REG3_ADJ_BIAS, 0x1) | ++ FIELD_PREP(PHY_RX_REG3_RDEG1, 0x3); ++ writel(val, base + PHY_RX_REG_A); ++ ++ val = readl(base + PHY_RX_REG_B); ++ tmp = FIELD_PREP(PHY_RX_REG4_RDEG2, 0x2) | ++ PHY_RX_REG4_ENVOS | PHY_RX_REG4_RTERM_SEL | PHY_RX_REG4_MANUAL_CFG | ++ FIELD_PREP(PHY_RX_REG5_RCELL_VCM, 0x8) | ++ FIELD_PREP(PHY_RX_REG5_RCELL_BIAS, 0x8) | ++ FIELD_PREP(PHY_RX_REG6_H1_REG, 0x8) | ++ FIELD_PREP(PHY_RX_REG6_ADAPT_GAIN, 0x2); ++ val = u32_replace_bits(val, tmp, PHY_RX_REGB_MASK); ++ writel(val, base + PHY_RX_REG_B); ++ ++ /* ++ * Inform PHY that all PLL-related configuration is done. ++ * PLL will not start locking until PHY_CLK_SW_INIT_DONE is set. ++ */ ++ val = PHY_CLK_SW_INIT_DONE | PHY_CLK_PU_SSC_OUT | ++ FIELD_PREP(PHY_CLK_REFCLK_FREQ, PHY_CLK_REFCLK_24M) | ++ PHY_CLK_RXCLK_EN | PHY_CLK_TXCLK_EN | ++ PHY_CLK_PCLK_EN | PHY_CLK_PIPE_PCLK_EN; ++ writel(val, base + PHY_CLK_CFG); ++ ++ ret = readl_poll_timeout(base + PHY_CLK_CFG, val, ++ (val & PHY_CLK_PLL_READY), ++ PCIE_POLL_DELAY, PCIE_PLL_TIMEOUT); ++ if (ret) { ++ dev_err(&phy->dev, "PHY PLL polling timeout\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int k3_usb3phy_init(struct phy *phy) ++{ ++ struct k3_lane_group *lg = phy_get_drvdata(phy); ++ int ret, i; ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ ret = k3_usb3phy_init_single(lg, lg->base + lg->data->offsets[i]); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++const struct phy_ops k3_usb3_phy_ops = { ++ .init = k3_usb3phy_init, ++ .owner = THIS_MODULE, ++}; ++EXPORT_SYMBOL_GPL(k3_usb3_phy_ops); ++ ++static int k3_pcie_phy_init(struct phy *phy) ++{ ++ struct k3_lane_group *lg = phy_get_drvdata(phy); ++ void __iomem *phy_base = lg->base + lg->data->offsets[0]; ++ u32 val; ++ int ret; ++ int i; ++ ++ val = readl(phy_base + PHY_PLL_REG1); ++ val = u32_replace_bits(val, 0x2, GENMASK(15, 12)); ++ writel(val, phy_base + PHY_PLL_REG1); ++ ++ val = readl(phy_base + PHY_PLL_REG2); ++ val = u32_replace_bits(val, 0, BIT(21)); ++ writel(val, phy_base + PHY_PLL_REG2); ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ void __iomem *lane_base = lg->base + lg->data->offsets[i]; ++ ++ val = readl(lane_base + PCIE_RX_REG1); ++ val = u32_replace_bits(val, 0, 0x3); ++ writel(val, lane_base + PCIE_RX_REG1); ++ } ++ ++ val = readl(phy_base + PHY_PLL_REG2); ++ val |= BIT(20); ++ writel(val, phy_base + PHY_PLL_REG2); ++ ++ writel(0x00006505, phy_base + PCIE_RX_REG1); ++ ++ /* pll_reg1 of lane0, disable SSC: pll[27:24] = 0 */ ++ val = readl(phy_base + PHY_PLL_REG1); ++ val = u32_replace_bits(val, 0, GENMASK(27, 24)); ++ writel(val, phy_base + PHY_PLL_REG1); ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ void __iomem *lane_base = lg->base + lg->data->offsets[i]; ++ ++ /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */ ++ val = readl(lane_base + PHY_PU_SEL); ++ val = u32_replace_bits(val, 1, BIT(13)); ++ writel(val, lane_base + PHY_PU_SEL); ++ ++ /* disable en_sample_data_after_cdr_locked */ ++ val = readl(lane_base + PHY_RESET_CFG); ++ val = u32_replace_bits(val, 0, BIT(6)); ++ writel(val, lane_base + PHY_RESET_CFG); ++ ++ /* Dynamic Lock */ ++ val = readl(lane_base + PHY_MODE_CFG); ++ val = u32_replace_bits(val, 1, BIT(2)); ++ writel(val, lane_base + PHY_MODE_CFG); ++ ++ val = FIELD_PREP(GENMASK(7, 0), 0x10) | ++ FIELD_PREP(GENMASK(15, 8), 0x78) | ++ FIELD_PREP(GENMASK(23, 16), 0x98) | ++ FIELD_PREP(GENMASK(31, 24), 0xdf); ++ writel(val, lane_base + PHY_RX_REG_A); ++ ++ val = readl(lane_base + PHY_RX_REG_B); ++ val &= ~PHY_RX_REGB_MASK; ++ val |= FIELD_PREP(GENMASK(7, 0), 0xb4) | ++ FIELD_PREP(GENMASK(15, 8), 0x88) | ++ FIELD_PREP(GENMASK(23, 16), 0x28); ++ writel(val, lane_base + PHY_RX_REG_B); ++ ++ /* Set init done */ ++ val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG); ++ val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE); ++ writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG); ++ } ++ ++ ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val, ++ (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY, ++ PCIE_PLL_TIMEOUT); ++ if (ret) { ++ dev_err(&lg->phy->dev, "PHY PLL lock timeout\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++const struct phy_ops k3_pcie_phy_ops = { ++ .init = k3_pcie_phy_init, ++ .owner = THIS_MODULE, ++}; ++EXPORT_SYMBOL_GPL(k3_pcie_phy_ops); ++ ++/* PHY rcal init requires APB_SPARE regmap access */ ++ ++#define APB_SPARE_PU_CAL 0x178 ++#define PU_CAL BIT(17) ++ ++#define APB_SPARE_RCAL_HSIO 0x17c ++#define APB_SPARE_PU_CAL_DONE BIT(8) ++#define RCAL_OVRD_PTRIM GENMASK(23, 20) ++#define RCAL_OVRD_NTRIM GENMASK(27, 24) ++#define RCAL_OVRD_PTRIM_EN BIT(28) ++#define RCAL_OVRD_NTRIM_EN BIT(29) ++#define RCAL_OVRD_STABLE_VAL BIT(30) ++#define RCAL_OVRD_STABLE_EN BIT(31) ++ ++#define RCAL_OVRD_TRIM_EN (RCAL_OVRD_NTRIM_EN | RCAL_OVRD_PTRIM_EN) ++#define RCAL_OVRD_TRIM_MASK (RCAL_OVRD_NTRIM | RCAL_OVRD_PTRIM) ++ ++#define PU_CAL_TIMEOUT 2000000 ++ ++static DEFINE_MUTEX(calibrate_lock); ++ ++int k3_phy_calibrate(struct regmap *apb_spare) ++{ ++ unsigned int val = 0; ++ int ret; ++ ++ guard(mutex)(&calibrate_lock); ++ ++ regmap_read(apb_spare, APB_SPARE_RCAL_HSIO, &val); ++ if (val & APB_SPARE_PU_CAL_DONE) ++ return 0; ++ ++ regmap_update_bits(apb_spare, APB_SPARE_PU_CAL, PU_CAL, ++ PU_CAL); ++ ++ ret = regmap_read_poll_timeout(apb_spare, APB_SPARE_RCAL_HSIO, ++ val, (val & APB_SPARE_PU_CAL_DONE), PCIE_POLL_DELAY, ++ PU_CAL_TIMEOUT); ++ ++ if (ret) ++ regmap_update_bits(apb_spare, APB_SPARE_RCAL_HSIO, ++ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | ++ RCAL_OVRD_TRIM_MASK | RCAL_OVRD_STABLE_EN, ++ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | ++ FIELD_PREP(RCAL_OVRD_NTRIM, 0x6) | ++ FIELD_PREP(RCAL_OVRD_PTRIM, 0xa) | ++ RCAL_OVRD_STABLE_EN); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(k3_phy_calibrate); ++ ++MODULE_DESCRIPTION("SpacemiT K3 PHY common ops"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/phy/spacemit/phy-k3-common.h b/drivers/phy/spacemit/phy-k3-common.h +new file mode 100644 +index 000000000000..49009c3c313a +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-common.h +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef _PHY_K3_COMMON_H ++#define _PHY_K3_COMMON_H ++ ++#include ++ ++struct k3_phy_lane_group_data { ++ u32 lanes; ++ u8 config; ++ u8 mask; ++ u32 offsets[] __counted_by(lanes); ++}; ++ ++struct k3_lane_group { ++ const struct k3_phy_lane_group_data *data; ++ void __iomem *base; ++ struct phy *phy; ++ bool is_pcie; ++}; ++ ++extern const struct phy_ops k3_pcie_phy_ops; ++extern const struct phy_ops k3_usb3_phy_ops; ++ ++int k3_phy_calibrate(struct regmap *apb_spare); ++ ++#endif +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0465-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch b/SPECS/linux-lts-kmhv2/0465-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch deleted file mode 100644 index 00f7e5801c..0000000000 --- a/SPECS/linux-lts-kmhv2/0465-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch +++ /dev/null @@ -1,36 +0,0 @@ -From df6fd4d5556ae9ac72a7fe88d7ac07abeaaaa7d5 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 20 May 2026 23:29:46 +0800 -Subject: [PATCH 465/467] RUYI: wifi: rtw89: pci: add SpacemiT K3 to 36-bit DMA - allowlist - -The SpacemiT K3 platform has no system memory in the 32-bit address -space, and it's verified that the chip works well with 36-bit DMA of -RTL8852BE. - -Add it to the 36-bit DMA allowlist of rtw89_pci. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - drivers/net/wireless/realtek/rtw89/pci.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c -index 6be1849b0c4d..5058ebadb604 100644 ---- a/drivers/net/wireless/realtek/rtw89/pci.c -+++ b/drivers/net/wireless/realtek/rtw89/pci.c -@@ -3295,6 +3295,10 @@ static bool rtw89_pci_is_dac_compatible_bridge(struct rtw89_dev *rtwdev) - if (bridge->device == 0x2806) - return true; - break; -+ case PCI_VENDOR_ID_SPACEMIT: -+ if (bridge->device == PCI_DEVICE_ID_SPACEMIT_K3) -+ return true; -+ break; - } - - return false; --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0466-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch b/SPECS/linux-lts-kmhv2/0466-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch deleted file mode 100644 index e3e07666c1..0000000000 --- a/SPECS/linux-lts-kmhv2/0466-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 1cae45d935c7ce67a69b1440b362c73b5ce1446c Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Tue, 19 May 2026 19:57:52 +0800 -Subject: [PATCH 466/467] RUYI: drm/amdgpu: disable dynamic PCIe speed switch - on SpacemiT K3 - -The dynamic speed switch functionality seems to be broken on SpacemiT -K3, and leads to frequent GPU crashes at least with Polaris GPUs. - -Disable dynamic speed switch on this platform. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -index c22aea46efcd..c69fd0b66dd4 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -@@ -1867,6 +1867,14 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev) - */ - static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev) - { -+ struct pci_dev *parent = adev->pdev; -+ static const struct pci_device_id broken_devids[] = { -+ /* SpacemiT K3 */ -+ { PCI_DEVICE(PCI_VENDOR_ID_SPACEMIT, -+ PCI_DEVICE_ID_SPACEMIT_K3) }, -+ {} -+ }; -+ - #if IS_ENABLED(CONFIG_X86) - struct cpuinfo_x86 *c = &cpu_data(0); - -@@ -1877,6 +1885,17 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device - if (c->x86_vendor == X86_VENDOR_INTEL) - return false; - #endif -+ /* skip upstream/downstream switches internal to dGPU */ -+ while (parent->vendor == PCI_VENDOR_ID_ATI) { -+ parent = pci_upstream_bridge(parent); -+ } -+ -+ if (!parent) -+ return true; -+ -+ if (pci_match_id(broken_devids, parent)) -+ return false; -+ - return true; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch b/SPECS/linux-lts-kmhv2/0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch new file mode 100644 index 0000000000..ce8ce857a9 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch @@ -0,0 +1,106 @@ +From 448b7e9c38ae27c10f2aa343886ce7c2b8243f8d Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 27 Feb 2026 09:46:06 +0800 +Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: add USB controller and + USB phy support + +Add all USB device node to the Spacemit K3. + +Signed-off-by: Inochi Amaoto +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++ + 2 files changed, 55 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index ac965ec83f2c..acfbb5029c15 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -183,6 +183,11 @@ dldo7: dldo7 { + }; + }; + ++&combophy { ++ spacemit,apmu = <&syscon_apmu 0x11>; ++ status = "okay"; ++}; ++ + ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; +@@ -280,3 +285,11 @@ hub@1 { + &usb2_phy { + status = "okay"; + }; ++ ++&usb3d_u2phy { ++ status = "okay"; ++}; ++ ++&usb3d { ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 1b86c872accb..e73e6838f6b0 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + + /dts-v1/; + +@@ -637,6 +638,47 @@ pdma: dma-controller@d4000000 { + status = "disabled"; + }; + ++ usb3d: usb@81a00000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0x81a00000 0x0 0x10000>; ++ interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, ++ <&syscon_apmu RESET_APMU_USB3_D_VCC>, ++ <&syscon_apmu RESET_APMU_USB3_D_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ phys = <&usb3d_u2phy>, ++ <&combophy 4 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,parkmode-disable-ss-quirk; ++ dr_mode = "host"; ++ status = "disabled"; ++ }; ++ ++ usb3d_u2phy: phy@81b00000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0x81b00000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ combophy: phy@81d00000 { ++ compatible = "spacemit,k3-combo-phy"; ++ reg = <0x0 0x81d00000 0x0 0x600000>; ++ #phy-cells = <2>; ++ spacemit,apb-spare = <&pll>; ++ status = "disabled"; ++ }; ++ + usb2_host: usb@c0a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0xc0a00000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch b/SPECS/linux-lts-kmhv2/0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch new file mode 100644 index 0000000000..76aa9565cc --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch @@ -0,0 +1,261 @@ +From 3e1379ca2b2ca099c8a0a6900f9be381e48213c6 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Tue, 24 Mar 2026 11:06:24 +0800 +Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: Add PCIe device node + +Add all PCIe device node for Spacemit K3. + +Signed-off-by: Inochi Amaoto +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 ++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 150 +++++++++++++++++++ + 3 files changed, 212 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index acfbb5029c15..f24ada15f182 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -264,6 +264,35 @@ uboot@210000 { + }; + }; + ++&pcie0_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_0_cfg>; ++ phys = <&combophy 0 PHY_TYPE_PCIE>, ++ <&combophy 1 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0", "pcie-phy1"; ++ num-lanes = <4>; ++ status = "okay"; ++}; ++ ++&pcie2_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_cfg>; ++ phys = <&combophy 2 PHY_TYPE_PCIE>, ++ <&combophy 3 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0", "pcie-phy1"; ++ num-lanes = <2>; ++ status = "okay"; ++}; ++ ++&pcie4_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie4_0_cfg>; ++ phys = <&combophy 5 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0"; ++ num-lanes = <1>; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 846d5e8cc783..5a817610101b 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -710,4 +710,37 @@ uart0-0-pins { + drive-strength = <25>; + }; + }; ++ ++ pcie0_0_cfg: pcie0-0-cfg { ++ pcie0-0-pins { ++ pinmux = , /* pcie0 perst */ ++ ; /* pcie0 clkreq */ ++ ++ bias-pull-up = <1>; ++ drive-strength = <33>; ++ power-source = <1800>; ++ }; ++ }; ++ ++ pcie2_0_cfg: pcie2-0-cfg { ++ pcie2-0-pins { ++ pinmux = , /* pcie2 perst */ ++ ; /* pcie2 clkreq */ ++ ++ drive-strength = <38>; ++ power-source = <3300>; ++ }; ++ }; ++ ++ pcie4_0_cfg: pcie4-0-cfg { ++ pcie4-0-pins { ++ pinmux = , /* pcie4 perst */ ++ , /* pcie4 wake */ ++ ; /* pcie4 clkreq */ ++ ++ bias-pull-up = <1>; ++ drive-strength = <33>; ++ power-source = <1800>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index e73e6838f6b0..9552089c7c73 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -638,6 +638,156 @@ pdma: dma-controller@d4000000 { + status = "disabled"; + }; + ++ pcie0_rc: pcie@80000000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80000000 0x0 0x00001000>, ++ <0x0 0x80100000 0x0 0x00001000>, ++ <0x0 0x80300000 0x0 0x00003f20>, ++ <0x11 0x00000000 0x0 0x00010000>, ++ <0x0 0x82900000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTA_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTA_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTA_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, ++ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_A_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_A_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_A_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ linux,pci-domain = <0>; ++ spacemit,apmu = <&syscon_apmu 0x1f0>; ++ status = "disabled"; ++ }; ++ ++ pcie1_rc: pcie@80400000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80400000 0x0 0x00001000>, ++ <0x0 0x80500000 0x0 0x00001000>, ++ <0x0 0x80700000 0x0 0x00003f20>, ++ <0x11 0x80000000 0x0 0x00010000>, ++ <0x0 0x82c00000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTB_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTB_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTB_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00010000 0x11 0x80010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x80110000 0x11 0x80110000 0x0 0x7fef0000>, ++ <0x43000000 0x16 0x00000000 0x16 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_B_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_B_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_B_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ linux,pci-domain = <1>; ++ spacemit,apmu = <&syscon_apmu 0x1d0>; ++ status = "disabled"; ++ }; ++ ++ pcie2_rc: pcie@80800000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80800000 0x0 0x00001000>, ++ <0x0 0x80900000 0x0 0x00001000>, ++ <0x0 0x80b00000 0x0 0x00003f20>, ++ <0x12 0x00000000 0x0 0x00010000>, ++ <0x0 0x82d00000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTC_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTC_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTC_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x00 0x00000000 0x12 0x00010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00110000 0x12 0x00110000 0x0 0x7fef0000>, ++ <0x43000000 0x15 0x00000000 0x15 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_C_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_C_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_C_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <2>; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1c8>; ++ status = "disabled"; ++ }; ++ ++ pcie3_rc: pcie@80c00000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80c00000 0x0 0x00001000>, ++ <0x0 0x80d00000 0x0 0x00001000>, ++ <0x0 0x80f00000 0x0 0x00003f20>, ++ <0x12 0x80000000 0x0 0x00010000>, ++ <0x0 0x82a00000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTD_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTD_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTD_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00010000 0x12 0x80010000 0x0 0x100000>, ++ <0x02000000 0x0 0x80110000 0x12 0x80110000 0x0 0x3fef0000>, ++ <0x43000000 0x14 0x00000000 0x14 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_D_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_D_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_D_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <3>; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1e0>; ++ status = "disabled"; ++ }; ++ ++ pcie4_rc: pcie@81000000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x81000000 0x0 0x00001000>, ++ <0x0 0x81100000 0x0 0x00001000>, ++ <0x0 0x81300000 0x0 0x00003f20>, ++ <0x12 0xc0000000 0x0 0x00010000>, ++ <0x0 0x82b00000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTE_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTE_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTE_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00000000 0x12 0xc0010000 0x0 0x100000>, ++ <0x02000000 0x0 0xc0110000 0x12 0xc0110000 0x0 0x3fef0000>, ++ <0x43000000 0x13 0x00000000 0x13 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_E_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_E_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_E_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <4>; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1e8>; ++ status = "disabled"; ++ }; ++ + usb3d: usb@81a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0x81a00000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0467-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch b/SPECS/linux-lts-kmhv2/0467-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch deleted file mode 100644 index 654f9a8c87..0000000000 --- a/SPECS/linux-lts-kmhv2/0467-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch +++ /dev/null @@ -1,50 +0,0 @@ -From d56459ef2dadb714f51cfba37b08e7cec2640ea1 Mon Sep 17 00:00:00 2001 -From: Zhang Meng -Date: Wed, 4 Feb 2026 08:54:40 +0800 -Subject: [PATCH 467/467] RVCK: driver: clk: k3: keep some system based clock - always on - -FROM: https://github.com/RVCK-Project/rvck/pull/213 - -community inclusion -category: bugfix -bugzilla: https://github.com/RVCK-Project/rvck/issues/212 - --------------------------------- - -The hdma clk is used by some component of CCI bus, it should -be keep always on, regardless of whether hdma enabled. - -The rcpu clk should be always on because it is running backround. - -Signed-off-by: Zhang Meng -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index 03de04144963..6acde3b76b7b 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -866,7 +866,7 @@ static const struct clk_parent_data rcpu_clk_parents[] = { - CCU_PARENT_HW(pll1_d6_409p6), - }; - CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, -- 4, 3, BIT(15), 7, 3, BIT(12), 0); -+ 4, 3, BIT(15), 7, 3, BIT(12), CLK_IS_CRITICAL); - - static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { - CCU_PARENT_HW(pll1_d48_51p2_ap), -@@ -1026,7 +1026,7 @@ CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CT - /* APMU clocks end */ - - /* DCIU clocks start */ --CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); -+CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), CLK_IS_CRITICAL); - CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); - CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); - CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); --- -2.53.0 - diff --git a/SPECS/linux-lts-kmhv2/0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch b/SPECS/linux-lts-kmhv2/0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch new file mode 100644 index 0000000000..9a9326a3e9 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch @@ -0,0 +1,34 @@ +From 88fa19733f8dc09f9c51bf41ded9c4d68c722b88 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Wed, 20 May 2026 23:28:15 +0800 +Subject: [RUYI PATCH] RUYI: PCI: add SpacemiT vendor id and its K3 device id + to pci_ids + +The SpacemiT K3 chip's root complex needs to be listed in the allowlist +of rtw89 driver to allow 36-bit DMA. + +Add the vendor and device IDs to pci_ids.h header file. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Han Gao +--- + include/linux/pci_ids.h | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h +index 7c01548a6ddb..e5a5700f7c8c 100644 +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2643,6 +2643,9 @@ + #define PCI_VENDOR_ID_SUNIX 0x1fd4 + #define PCI_DEVICE_ID_SUNIX_1999 0x1999 + ++#define PCI_VENDOR_ID_SPACEMIT 0x201f ++#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 ++ + #define PCI_VENDOR_ID_HINT 0x3388 + #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch b/SPECS/linux-lts-kmhv2/0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch new file mode 100644 index 0000000000..e0b9eb8766 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch @@ -0,0 +1,36 @@ +From e57bb71611315a5153d479c9e82b806ab76de1fb Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Wed, 20 May 2026 23:29:46 +0800 +Subject: [RUYI PATCH] RUYI: wifi: rtw89: pci: add SpacemiT K3 to 36-bit DMA + allowlist + +The SpacemiT K3 platform has no system memory in the 32-bit address +space, and it's verified that the chip works well with 36-bit DMA of +RTL8852BE. + +Add it to the 36-bit DMA allowlist of rtw89_pci. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Han Gao +--- + drivers/net/wireless/realtek/rtw89/pci.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c +index 6be1849b0c4d..5058ebadb604 100644 +--- a/drivers/net/wireless/realtek/rtw89/pci.c ++++ b/drivers/net/wireless/realtek/rtw89/pci.c +@@ -3295,6 +3295,10 @@ static bool rtw89_pci_is_dac_compatible_bridge(struct rtw89_dev *rtwdev) + if (bridge->device == 0x2806) + return true; + break; ++ case PCI_VENDOR_ID_SPACEMIT: ++ if (bridge->device == PCI_DEVICE_ID_SPACEMIT_K3) ++ return true; ++ break; + } + + return false; +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch b/SPECS/linux-lts-kmhv2/0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch new file mode 100644 index 0000000000..00daab299c --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch @@ -0,0 +1,57 @@ +From 50eb8f06ed16e79d0840e5c58220ae05cac7dbb1 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Tue, 19 May 2026 19:57:52 +0800 +Subject: [RUYI PATCH] RUYI: drm/amdgpu: disable dynamic PCIe speed switch on + SpacemiT K3 + +The dynamic speed switch functionality seems to be broken on SpacemiT +K3, and leads to frequent GPU crashes at least with Polaris GPUs. + +Disable dynamic speed switch on this platform. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Han Gao +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index c22aea46efcd..b54f7cdd0ce8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1867,6 +1867,14 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev) + */ + static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev) + { ++ struct pci_dev *parent = adev->pdev; ++ static const struct pci_device_id broken_devids[] = { ++ /* SpacemiT K3 */ ++ { PCI_DEVICE(PCI_VENDOR_ID_SPACEMIT, ++ PCI_DEVICE_ID_SPACEMIT_K3) }, ++ {} ++ }; ++ + #if IS_ENABLED(CONFIG_X86) + struct cpuinfo_x86 *c = &cpu_data(0); + +@@ -1877,6 +1885,17 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device + if (c->x86_vendor == X86_VENDOR_INTEL) + return false; + #endif ++ /* skip upstream/downstream switches internal to dGPU */ ++ while (parent && parent->vendor == PCI_VENDOR_ID_ATI) { ++ parent = pci_upstream_bridge(parent); ++ } ++ ++ if (!parent) ++ return true; ++ ++ if (pci_match_id(broken_devids, parent)) ++ return false; ++ + return true; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch b/SPECS/linux-lts-kmhv2/0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch new file mode 100644 index 0000000000..daa05c9c8d --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch @@ -0,0 +1,50 @@ +From c0f35dd9ad2ce894ee2fef94f5ac86216d03ef46 Mon Sep 17 00:00:00 2001 +From: Zhang Meng +Date: Wed, 4 Feb 2026 08:54:40 +0800 +Subject: [RUYI PATCH] RVCK: driver: clk: k3: keep some system based clock + always on + +FROM: https://github.com/RVCK-Project/rvck/pull/213 + +community inclusion +category: bugfix +bugzilla: https://github.com/RVCK-Project/rvck/issues/212 + +-------------------------------- + +The hdma clk is used by some component of CCI bus, it should +be keep always on, regardless of whether hdma enabled. + +The rcpu clk should be always on because it is running backround. + +Signed-off-by: Zhang Meng +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 03de04144963..6acde3b76b7b 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -866,7 +866,7 @@ static const struct clk_parent_data rcpu_clk_parents[] = { + CCU_PARENT_HW(pll1_d6_409p6), + }; + CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, +- 4, 3, BIT(15), 7, 3, BIT(12), 0); ++ 4, 3, BIT(15), 7, 3, BIT(12), CLK_IS_CRITICAL); + + static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { + CCU_PARENT_HW(pll1_d48_51p2_ap), +@@ -1026,7 +1026,7 @@ CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CT + /* APMU clocks end */ + + /* DCIU clocks start */ +-CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); ++CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), CLK_IS_CRITICAL); + CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); + CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); + CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch b/SPECS/linux-lts-kmhv2/0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch new file mode 100644 index 0000000000..5c6f644043 --- /dev/null +++ b/SPECS/linux-lts-kmhv2/0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch @@ -0,0 +1,65 @@ +From af2e3f98ce75fe961163f67f323465d95ce082d9 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 28 May 2026 14:18:23 +0800 +Subject: [RUYI PATCH] RUYI: mmc: sdhci-of-dwcmshc: Add support for SG2042 FPGA + variant + +Add support for a testing variant of the SG2042 SDHCI controller without +PHY reset and without the "timer" clock. + +Signed-off-by: Vivian Wang +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index 90aa146a1be3..292940d9c45b 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -1664,6 +1664,16 @@ static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { + .platform_execute_tuning = th1520_execute_tuning, + }; + ++static const struct sdhci_ops sdhci_dwcmshc_sg2042_fpga_ops = { ++ .set_clock = sdhci_set_clock, ++ .set_bus_width = sdhci_set_bus_width, ++ .set_uhs_signaling = dwcmshc_set_uhs_signaling, ++ .get_max_clock = dwcmshc_get_max_clock, ++ .reset = sdhci_reset, ++ .adma_write_desc = dwcmshc_adma_write_desc, ++ .platform_execute_tuning = th1520_execute_tuning, ++}; ++ + static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { + .set_clock = sdhci_eic7700_set_clock, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, +@@ -1746,6 +1756,14 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { + .init = sg2042_init, + }; + ++static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_fpga_pdata = { ++ .pdata = { ++ .ops = &sdhci_dwcmshc_sg2042_fpga_ops, ++ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, ++ }, ++}; ++ + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_eic7700_ops, +@@ -1857,6 +1875,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { + .compatible = "sophgo,sg2042-dwcmshc", + .data = &sdhci_dwcmshc_sg2042_pdata, + }, ++ { ++ .compatible = "sophgo,sg2042-fpga-dwcmshc", ++ .data = &sdhci_dwcmshc_sg2042_fpga_pdata, ++ }, + { + .compatible = "eswin,eic7700-dwcmshc", + .data = &sdhci_dwcmshc_eic7700_pdata, +-- +2.53.0 + diff --git a/SPECS/linux-lts-kmhv2/linux-lts-kmhv2.spec b/SPECS/linux-lts-kmhv2/linux-lts-kmhv2.spec index 7de8368e54..438672f8d8 100644 --- a/SPECS/linux-lts-kmhv2/linux-lts-kmhv2.spec +++ b/SPECS/linux-lts-kmhv2/linux-lts-kmhv2.spec @@ -23,14 +23,15 @@ %global kernel_make_flags LD=ld.bfd KBUILD_BUILD_VERSION=%{release} Name: linux-lts-kmhv2 -Version: 6.18.33 +Version: 6.18.34 Release: %autorelease Summary: The Linux lts Kernel License: GPL-2.0-only URL: https://www.kernel.org/ -#!RemoteAsset: sha256:6f16ff302599f6fe34742890322cf0775703105fbd8767449682fca6af0fb782 +#!RemoteAsset: sha256:640c4732fb42842166db97e032c1fe7e5ff72c85a8982c75b40f74be3555d760 Source0: https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-%{version}.tar.xz Source1: config.%{_arch} +Source2: series ExclusiveArch: riscv64 @@ -74,477 +75,7 @@ Requires(post): kernel-install Requires(postun): kernel-install %patchlist -0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch -0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch -0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch -0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch -0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch -0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch -0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch -0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch -0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch 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+0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch +0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch +0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch +0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch +0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch +0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch +0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch +0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch +0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch +0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch +0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch +0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch +0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch +0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch +0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch +0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch +0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch +0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch +0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch +0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch +0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch +0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch +0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch +0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch +0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch +0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch +0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch +0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch +0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch +0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch +0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch +0001-XIANGSHAN-Flush-all-tlb-in-set_pte.patch +0002-XIANGSHAN-Add-two-sbi-calls.patch +0003-XIANGSHAN-Add-workaround-to-retry-when-access-fault.patch diff --git a/SPECS/linux-lts/0001-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch b/SPECS/linux-lts/0001-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch deleted file mode 100644 index 5a3619f868..0000000000 --- a/SPECS/linux-lts/0001-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch +++ /dev/null @@ -1,65 +0,0 @@ -From fc295beff7031f45a9ab9984a426817f27ed21fe Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 28 May 2026 14:18:23 +0800 -Subject: [PATCH] RUYI: mmc: sdhci-of-dwcmshc: Add support for SG2042 FPGA - variant - -Add support for a testing variant of the SG2042 SDHCI controller without -PHY reset and without the "timer" clock. - -[ Vivian: Adjust context for 6.18 ] -Signed-off-by: Vivian Wang ---- - drivers/mmc/host/sdhci-of-dwcmshc.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c -index 5b7ffc359414..9f3482b2a311 100644 ---- a/drivers/mmc/host/sdhci-of-dwcmshc.c -+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c -@@ -1194,6 +1194,16 @@ static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { - .platform_execute_tuning = th1520_execute_tuning, - }; - -+static const struct sdhci_ops sdhci_dwcmshc_sg2042_fpga_ops = { -+ .set_clock = sdhci_set_clock, -+ .set_bus_width = sdhci_set_bus_width, -+ .set_uhs_signaling = dwcmshc_set_uhs_signaling, -+ .get_max_clock = dwcmshc_get_max_clock, -+ .reset = sdhci_reset, -+ .adma_write_desc = dwcmshc_adma_write_desc, -+ .platform_execute_tuning = th1520_execute_tuning, -+}; -+ - static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = { - .pdata = { - .ops = &sdhci_dwcmshc_ops, -@@ -1263,6 +1273,14 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { - .init = sg2042_init, - }; - -+static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_fpga_pdata = { -+ .pdata = { -+ .ops = &sdhci_dwcmshc_sg2042_fpga_ops, -+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, -+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, -+ }, -+}; -+ - static const struct cqhci_host_ops dwcmshc_cqhci_ops = { - .enable = dwcmshc_sdhci_cqe_enable, - .disable = sdhci_cqe_disable, -@@ -1363,6 +1381,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { - .compatible = "sophgo,sg2042-dwcmshc", - .data = &sdhci_dwcmshc_sg2042_pdata, - }, -+ { -+ .compatible = "sophgo,sg2042-fpga-dwcmshc", -+ .data = &sdhci_dwcmshc_sg2042_fpga_pdata, -+ }, - {}, - }; - MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); --- -2.54.0 - diff --git a/SPECS/linux-lts/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch b/SPECS/linux-lts/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch index 5a44481abf..dd82e46153 100644 --- a/SPECS/linux-lts/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch +++ b/SPECS/linux-lts/0001-UPSTREAM-drm-ttm-add-pgprot-handling-for-RISC-V.patch @@ -1,7 +1,7 @@ -From 68f4d24c96b911ab659b964add869d541d519b43 Mon Sep 17 00:00:00 2001 +From e8197b44ac58d76565180793e59b2ff39d0ff8a1 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 5 Dec 2025 10:42:07 +0800 -Subject: [PATCH 001/467] UPSTREAM: drm/ttm: add pgprot handling for RISC-V +Subject: [RUYI PATCH] UPSTREAM: drm/ttm: add pgprot handling for RISC-V MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch b/SPECS/linux-lts/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch index c7224a0b81..b8cb7f6ff0 100644 --- a/SPECS/linux-lts/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch +++ b/SPECS/linux-lts/0002-UPSTREAM-riscv-sophgo-dts-add-PCIe-controllers-for-S.patch @@ -1,8 +1,8 @@ -From a6570cc0fbc912cd59b63b6cc0e3dfb0e74e8d08 Mon Sep 17 00:00:00 2001 +From 172fa2e5a76c1351ea1bb6903e1d03944ce8a778 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:33:43 +0800 -Subject: [PATCH 002/467] UPSTREAM: riscv: sophgo: dts: add PCIe controllers - for SG2042 +Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: add PCIe controllers for + SG2042 Add PCIe controller nodes in DTS for Sophgo SG2042. Default they are disabled. diff --git a/SPECS/linux-lts/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch b/SPECS/linux-lts/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch index 7528086c94..43e4f49e7c 100644 --- a/SPECS/linux-lts/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch +++ b/SPECS/linux-lts/0003-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-PioneerBox.patch @@ -1,8 +1,7 @@ -From a2b3dccf02d815c4cbbaa8ea797f337204196c30 Mon Sep 17 00:00:00 2001 +From eb8e783adc4036ef80be48cfc8469b4be20fb577 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:34:05 +0800 -Subject: [PATCH 003/467] UPSTREAM: riscv: sophgo: dts: enable PCIe for - PioneerBox +Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: enable PCIe for PioneerBox Enable PCIe controllers for PioneerBox, which uses SG2042 SoC. diff --git a/SPECS/linux-lts/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch b/SPECS/linux-lts/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch index 4191eceda0..46b8b479dc 100644 --- a/SPECS/linux-lts/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch +++ b/SPECS/linux-lts/0004-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch @@ -1,7 +1,7 @@ -From ea11e07b03ac17c6cc757dd58c1097140d35647f Mon Sep 17 00:00:00 2001 +From 97f3ca4bfb8cf08fc5f01da48adbd2e295d9bf62 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:39:22 +0800 -Subject: [PATCH 004/467] UPSTREAM: riscv: sophgo: dts: enable PCIe for +Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X Enable PCIe controllers for Sophgo SG2042_EVB_V1.X board, diff --git a/SPECS/linux-lts/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch b/SPECS/linux-lts/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch index fa69fdde31..118243db74 100644 --- a/SPECS/linux-lts/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch +++ b/SPECS/linux-lts/0005-UPSTREAM-riscv-sophgo-dts-enable-PCIe-for-SG2042_EVB.patch @@ -1,7 +1,7 @@ -From 85ca5757d41f28ceee07c296a8562fc8ee987444 Mon Sep 17 00:00:00 2001 +From adfc1b75ef3710cc675487e2d856fe811e92c9cf Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 20 Oct 2025 11:40:09 +0800 -Subject: [PATCH 005/467] UPSTREAM: riscv: sophgo: dts: enable PCIe for +Subject: [RUYI PATCH] UPSTREAM: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0 Enable PCIe controllers for Sophgo SG2042_EVB_V2.0 board, diff --git a/SPECS/linux-lts/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch b/SPECS/linux-lts/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch index 434e018363..0105843995 100644 --- a/SPECS/linux-lts/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch +++ b/SPECS/linux-lts/0006-UPSTREAM-riscv-dts-sophgo-Add-SPI-NOR-node-for-SG204.patch @@ -1,7 +1,7 @@ -From 6655e6812bc952f6ca617368b081df8ab2f94dc0 Mon Sep 17 00:00:00 2001 +From 0fe3f721fe45c7b4cfd9c65eaea2e94c7d05d05a Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:50 +0800 -Subject: [PATCH 006/467] UPSTREAM: riscv: dts: sophgo: Add SPI NOR node for +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Add SPI NOR node for SG2042 Add SPI NOR controller node for SG2042 diff --git a/SPECS/linux-lts/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch b/SPECS/linux-lts/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch index a2068d8a3f..e7d51ad4e9 100644 --- a/SPECS/linux-lts/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch +++ b/SPECS/linux-lts/0007-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-Pi.patch @@ -1,7 +1,7 @@ -From 15e5a76787a30da2ef62756cfd195210851cf09f Mon Sep 17 00:00:00 2001 +From 9e5ebf3bb03d5951a1ac6273a557a7d3b42aaf5d Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:51 +0800 -Subject: [PATCH 007/467] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for PioneerBox Enable SPI NOR node for PioneerBox device tree diff --git a/SPECS/linux-lts/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch b/SPECS/linux-lts/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch index dea06361cb..0353c0d45c 100644 --- a/SPECS/linux-lts/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch +++ b/SPECS/linux-lts/0008-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch @@ -1,7 +1,7 @@ -From d1a07634e134fcadea2caad89fcdcf622e23a136 Mon Sep 17 00:00:00 2001 +From ca6b4bc1ae282908399370569de96b507b11a199 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:52 +0800 -Subject: [PATCH 008/467] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1 Enable SPI NOR node for SG2042_EVB_V1 device tree diff --git a/SPECS/linux-lts/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch b/SPECS/linux-lts/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch index 9584149d3e..849dbb07fb 100644 --- a/SPECS/linux-lts/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch +++ b/SPECS/linux-lts/0009-UPSTREAM-riscv-dts-sophgo-Enable-SPI-NOR-node-for-SG.patch @@ -1,7 +1,7 @@ -From 53f32e5b4fe4b9f2bd8fecbf74e973f6b8c32c42 Mon Sep 17 00:00:00 2001 +From ef69ecb5f71cc9ec10bbe973e96dec13a22d83c5 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:53 +0800 -Subject: [PATCH 009/467] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2 Enable SPI NOR node for SG2042_EVB_V2 device tree diff --git a/SPECS/linux-lts/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch b/SPECS/linux-lts/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch index 176f1f72fa..f9aa138c7a 100644 --- a/SPECS/linux-lts/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch +++ b/SPECS/linux-lts/0010-UPSTREAM-dt-bindings-net-sophgo-sg2044-dwmac-add-phy.patch @@ -1,8 +1,8 @@ -From fa290cfeb4782f7d5f70c9bfc7c9a45a8d783bba Mon Sep 17 00:00:00 2001 +From 4cec01963100499caa46c4c97acb3d80549132f6 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Fri, 14 Nov 2025 08:38:03 +0800 -Subject: [PATCH 010/467] UPSTREAM: dt-bindings: net: sophgo,sg2044-dwmac: add - phy mode restriction +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: net: sophgo,sg2044-dwmac: add phy + mode restriction As the ethernet controller of SG2044 and SG2042 only supports RGMII phy. Add phy-mode property to restrict the value. diff --git a/SPECS/linux-lts/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch b/SPECS/linux-lts/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch index eab71a2128..d0b72dcb45 100644 --- a/SPECS/linux-lts/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch +++ b/SPECS/linux-lts/0011-UPSTREAM-perf-vendor-events-riscv-add-T-HEAD-C920V2-.patch @@ -1,7 +1,7 @@ -From 5d275d4fdc0ad5140b356cbcb753365217315b31 Mon Sep 17 00:00:00 2001 +From 97f62d7522d266af5df939fe3f50a0e365d78d37 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 14 Oct 2025 09:48:29 +0800 -Subject: [PATCH 011/467] UPSTREAM: perf vendor events riscv: add T-HEAD C920V2 +Subject: [RUYI PATCH] UPSTREAM: perf vendor events riscv: add T-HEAD C920V2 JSON support T-HEAD C920 has a V2 iteration, which supports Sscompmf. The V2 diff --git a/SPECS/linux-lts/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch b/SPECS/linux-lts/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch index a79f509cec..de2b418bcf 100644 --- a/SPECS/linux-lts/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch +++ b/SPECS/linux-lts/0012-UPSTREAM-rust-macros-Add-support-for-imports_ns-to-m.patch @@ -1,8 +1,8 @@ -From 367f56da193fa8ee4a1896f1086d913d2ce34435 Mon Sep 17 00:00:00 2001 +From e140a5124e38afd1d68eb3c9da0a96a9bc0c1fd8 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:32 +0100 -Subject: [PATCH 012/467] UPSTREAM: rust: macros: Add support for 'imports_ns' - to module! +Subject: [RUYI PATCH] UPSTREAM: rust: macros: Add support for 'imports_ns' to + module! MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch b/SPECS/linux-lts/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch index 03d9743457..a4878efc8e 100644 --- a/SPECS/linux-lts/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch +++ b/SPECS/linux-lts/0013-UPSTREAM-pwm-Export-pwmchip_release-for-external-use.patch @@ -1,8 +1,7 @@ -From 21c80df86a56778bb86caf30236f44822c7c78ab Mon Sep 17 00:00:00 2001 +From 6eec5416f899b995199e6a78acdba366552fe74b Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:01 +0200 -Subject: [PATCH 013/467] UPSTREAM: pwm: Export `pwmchip_release` for external - use +Subject: [RUYI PATCH] UPSTREAM: pwm: Export `pwmchip_release` for external use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch b/SPECS/linux-lts/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch index 1bc49e3700..3a11557826 100644 --- a/SPECS/linux-lts/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch +++ b/SPECS/linux-lts/0014-UPSTREAM-rust-pwm-Add-Kconfig-and-basic-data-structu.patch @@ -1,7 +1,7 @@ -From 7012d45ae8771935292a62a8dcaa765c6adb7f56 Mon Sep 17 00:00:00 2001 +From dc77d3e5fd4e58d58519c452e5ab3a3dc0d30352 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:02 +0200 -Subject: [PATCH 014/467] UPSTREAM: rust: pwm: Add Kconfig and basic data +Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Add Kconfig and basic data structures MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 diff --git a/SPECS/linux-lts/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch b/SPECS/linux-lts/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch index b977783a21..ae5c79af9d 100644 --- a/SPECS/linux-lts/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch +++ b/SPECS/linux-lts/0015-UPSTREAM-rust-pwm-Add-complete-abstraction-layer.patch @@ -1,7 +1,7 @@ -From df53f3655e6b9bf34d2b0af69746d7e7efcf5c82 Mon Sep 17 00:00:00 2001 +From fad4bc85d938d1fa411bfc7c09b2c327dc21cad2 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:03 +0200 -Subject: [PATCH 015/467] UPSTREAM: rust: pwm: Add complete abstraction layer +Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Add complete abstraction layer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch b/SPECS/linux-lts/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch index 40837d9bee..abdc4b8594 100644 --- a/SPECS/linux-lts/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch +++ b/SPECS/linux-lts/0016-UPSTREAM-rust-pwm-Add-module_pwm_platform_driver-mac.patch @@ -1,7 +1,7 @@ -From 5ad798527f4b4099b19ab390304846d618b490fb Mon Sep 17 00:00:00 2001 +From a8369a239ce03856b5d63e39d5c92586c0641c18 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:33 +0100 -Subject: [PATCH 016/467] UPSTREAM: rust: pwm: Add module_pwm_platform_driver! +Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Add module_pwm_platform_driver! macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 diff --git a/SPECS/linux-lts/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch b/SPECS/linux-lts/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch index 8a537db5b7..a2e4a4474c 100644 --- a/SPECS/linux-lts/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch +++ b/SPECS/linux-lts/0017-UPSTREAM-rust-pwm-Drop-wrapping-of-PWM-polarity-and-.patch @@ -1,8 +1,8 @@ -From 07a4233a04f77fea6255070d799f8158192c7896 Mon Sep 17 00:00:00 2001 +From 0bed1f7ddadef9191b85230b6f078bf48a1ddfc1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 25 Oct 2025 14:23:56 +0200 -Subject: [PATCH 017/467] UPSTREAM: rust: pwm: Drop wrapping of PWM polarity - and state +Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Drop wrapping of PWM polarity and + state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch b/SPECS/linux-lts/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch index 1bf1f84011..aaf7682aaf 100644 --- a/SPECS/linux-lts/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch +++ b/SPECS/linux-lts/0018-UPSTREAM-rust-pwm-Fix-broken-intra-doc-link.patch @@ -1,7 +1,7 @@ -From 124a1875f86fff16688c63594e8e073464b6f4dd Mon Sep 17 00:00:00 2001 +From ce0cfe6521836f8d1bff1dbb1dd784f8dbe2f0f1 Mon Sep 17 00:00:00 2001 From: Miguel Ojeda Date: Wed, 29 Oct 2025 19:19:40 +0100 -Subject: [PATCH 018/467] UPSTREAM: rust: pwm: Fix broken intra-doc link +Subject: [RUYI PATCH] UPSTREAM: rust: pwm: Fix broken intra-doc link MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch b/SPECS/linux-lts/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch index 6d68bf4ad8..4a1351eb60 100644 --- a/SPECS/linux-lts/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch +++ b/SPECS/linux-lts/0019-UPSTREAM-pwm-Add-Rust-driver-for-T-HEAD-TH1520-SoC.patch @@ -1,7 +1,7 @@ -From 5c016dc78cc84fad38fbee81b56b42b02313be87 Mon Sep 17 00:00:00 2001 +From 323a18dcdb57c3c4a56d687fff097af3249b0fe3 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:04 +0200 -Subject: [PATCH 019/467] UPSTREAM: pwm: Add Rust driver for T-HEAD TH1520 SoC +Subject: [RUYI PATCH] UPSTREAM: pwm: Add Rust driver for T-HEAD TH1520 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch b/SPECS/linux-lts/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch index 7e8f6f69f9..72b7b6e552 100644 --- a/SPECS/linux-lts/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch +++ b/SPECS/linux-lts/0020-UPSTREAM-dt-bindings-pwm-thead-Add-T-HEAD-TH1520-PWM.patch @@ -1,8 +1,8 @@ -From 75682c170513cae6790cdc8c45c039ae28ac86a8 Mon Sep 17 00:00:00 2001 +From 1ff5f22be0212ca408aa7b7fb452742a1c0e44d8 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:05 +0200 -Subject: [PATCH 020/467] UPSTREAM: dt-bindings: pwm: thead: Add T-HEAD TH1520 - PWM controller +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pwm: thead: Add T-HEAD TH1520 PWM + controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch b/SPECS/linux-lts/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch index 2822d39394..b045d4a3cf 100644 --- a/SPECS/linux-lts/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch +++ b/SPECS/linux-lts/0021-UPSTREAM-pwm-Fix-Rust-formatting.patch @@ -1,7 +1,7 @@ -From 16e23a75ada51fa0c1e922c0c532193c2465a324 Mon Sep 17 00:00:00 2001 +From d512570ff756b751d74f27121ccd6784be182855 Mon Sep 17 00:00:00 2001 From: Miguel Ojeda Date: Wed, 29 Oct 2025 19:25:02 +0100 -Subject: [PATCH 021/467] UPSTREAM: pwm: Fix Rust formatting +Subject: [RUYI PATCH] UPSTREAM: pwm: Fix Rust formatting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch b/SPECS/linux-lts/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch index e395108a1d..06d4f3cc31 100644 --- a/SPECS/linux-lts/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch +++ b/SPECS/linux-lts/0022-UPSTREAM-pwm-th1520-Fix-clippy-warning-for-redundant.patch @@ -1,8 +1,8 @@ -From 24db3f421ffa17c4b9c6a3a054c6cb6d164a3645 Mon Sep 17 00:00:00 2001 +From b8e48fd0e9516c83f6a6193730b5d042ed5263bd Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:35 +0100 -Subject: [PATCH 022/467] UPSTREAM: pwm: th1520: Fix clippy warning for - redundant struct field init +Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: Fix clippy warning for redundant + struct field init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch b/SPECS/linux-lts/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch index b5b15a3878..b4384ef364 100644 --- a/SPECS/linux-lts/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch +++ b/SPECS/linux-lts/0023-UPSTREAM-pwm-th1520-Use-module_pwm_platform_driver-m.patch @@ -1,8 +1,8 @@ -From 0e92472e39f3b94fbd120e69f625a2b4d5ade50d Mon Sep 17 00:00:00 2001 +From e4ad935868f5592d06155265261be5934f1821ec Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 28 Oct 2025 13:22:34 +0100 -Subject: [PATCH 023/467] UPSTREAM: pwm: th1520: Use - module_pwm_platform_driver! macro +Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: Use module_pwm_platform_driver! + macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch b/SPECS/linux-lts/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch index 5f7489ce32..f01d4fe843 100644 --- a/SPECS/linux-lts/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch +++ b/SPECS/linux-lts/0024-UPSTREAM-pwm-th1520-Fix-missing-Kconfig-dependencies.patch @@ -1,8 +1,7 @@ -From 0580c630050cf90e3e014a44e421a8876ab2c452 Mon Sep 17 00:00:00 2001 +From 04ac502626ab9c23c88cb52a8447f2a6d6871231 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Tue, 9 Dec 2025 21:06:03 +0100 -Subject: [PATCH 024/467] UPSTREAM: pwm: th1520: Fix missing Kconfig - dependencies +Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: Fix missing Kconfig dependencies MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch b/SPECS/linux-lts/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch index 7f73a0b809..4f6592382a 100644 --- a/SPECS/linux-lts/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch +++ b/SPECS/linux-lts/0025-UPSTREAM-riscv-dts-thead-add-xtheadvector-to-the-th1.patch @@ -1,7 +1,7 @@ -From 95091d9394da630c87c6cfa3824b397f4eee2f73 Mon Sep 17 00:00:00 2001 +From c413ed4426b184f8cb2304ff2897825e2a215871 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 19 Sep 2025 04:44:47 +0800 -Subject: [PATCH 025/467] UPSTREAM: riscv: dts: thead: add xtheadvector to the +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add xtheadvector to the th1520 devicetree The th1520 support xtheadvector [1] so it can be included in the diff --git a/SPECS/linux-lts/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch b/SPECS/linux-lts/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch index c199f87111..645a855fa1 100644 --- a/SPECS/linux-lts/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch +++ b/SPECS/linux-lts/0026-UPSTREAM-riscv-dts-thead-add-ziccrse-for-th1520.patch @@ -1,7 +1,7 @@ -From ce397038e6fdb45ea0afe6fc74d6710bb294ef61 Mon Sep 17 00:00:00 2001 +From d86f79c2f13ca9a4c232cce2f5dd5020f18a9656 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 19 Sep 2025 04:44:48 +0800 -Subject: [PATCH 026/467] UPSTREAM: riscv: dts: thead: add ziccrse for th1520 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add ziccrse for th1520 Existing rv64 hardware conforms to the rva20 profile. diff --git a/SPECS/linux-lts/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch b/SPECS/linux-lts/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch index 756d021b59..02c41e4add 100644 --- a/SPECS/linux-lts/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch +++ b/SPECS/linux-lts/0027-UPSTREAM-riscv-dts-thead-add-zfh-for-th1520.patch @@ -1,7 +1,7 @@ -From bc00f9a0bbb6c14f199943da7ff9f30859dee923 Mon Sep 17 00:00:00 2001 +From 6c54c277dfd8b9c53a91aac3aa08d80a40eef35d Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 19 Sep 2025 04:44:49 +0800 -Subject: [PATCH 027/467] UPSTREAM: riscv: dts: thead: add zfh for th1520 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add zfh for th1520 th1520 support Zfh ISA extension. It supports the same RISC-V extensions as SG2042. diff --git a/SPECS/linux-lts/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch b/SPECS/linux-lts/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch index 6dc799bdb4..1da5ef41e5 100644 --- a/SPECS/linux-lts/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch +++ b/SPECS/linux-lts/0028-UPSTREAM-riscv-dts-thead-Add-PWM-controller-node.patch @@ -1,7 +1,7 @@ -From ccee5be0d66e8a00cbb23864ba081c741a37e009 Mon Sep 17 00:00:00 2001 +From 3ca9f9c1f974516ed56055f86fe810e70234d2e0 Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:06 +0200 -Subject: [PATCH 028/467] UPSTREAM: riscv: dts: thead: Add PWM controller node +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add PWM controller node Add the Device Tree node for the T-HEAD TH1520 SoC's PWM controller. diff --git a/SPECS/linux-lts/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch b/SPECS/linux-lts/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch index 4d0f44e4d2..16a6ff7a16 100644 --- a/SPECS/linux-lts/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch +++ b/SPECS/linux-lts/0029-UPSTREAM-riscv-dts-thead-Add-PWM-fan-and-thermal-con.patch @@ -1,7 +1,7 @@ -From 6e4ddc5ab60b81304d73eac230c5c2d9b641f114 Mon Sep 17 00:00:00 2001 +From 34e6c9de17b9ff861746760bfc9334e3fc3060cb Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Thu, 16 Oct 2025 15:38:07 +0200 -Subject: [PATCH 029/467] UPSTREAM: riscv: dts: thead: Add PWM fan and thermal +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add PWM fan and thermal control Add Device Tree nodes to enable a PWM controlled fan and it's associated diff --git a/SPECS/linux-lts/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch b/SPECS/linux-lts/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch index b61a71c164..073023bb11 100644 --- a/SPECS/linux-lts/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch +++ b/SPECS/linux-lts/0030-UPSTREAM-dt-bindings-vendor-prefixes-Add-UltraRISC.patch @@ -1,7 +1,7 @@ -From 177d1708f10af38636c322a58f9e71637e3553b3 Mon Sep 17 00:00:00 2001 +From 185f8436e47e0844df0a0d25fbb995a69a565fd1 Mon Sep 17 00:00:00 2001 From: Lucas Zampieri Date: Fri, 24 Oct 2025 09:36:40 +0100 -Subject: [PATCH 030/467] UPSTREAM: dt-bindings: vendor-prefixes: Add UltraRISC +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: vendor-prefixes: Add UltraRISC Add vendor prefix for UltraRISC Technology Co., Ltd. diff --git a/SPECS/linux-lts/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch b/SPECS/linux-lts/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch index 6ba2aa9b16..a9e42fff55 100644 --- a/SPECS/linux-lts/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch +++ b/SPECS/linux-lts/0031-UPSTREAM-dt-bindings-interrupt-controller-Add-UltraR.patch @@ -1,7 +1,7 @@ -From 1cb2556af5d85298241d0bccaeab5658801c313a Mon Sep 17 00:00:00 2001 +From 38033dfbe309976053db7684228a93e90a76f54f Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Fri, 24 Oct 2025 09:36:41 +0100 -Subject: [PATCH 031/467] UPSTREAM: dt-bindings: interrupt-controller: Add +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: Add UltraRISC DP1000 PLIC Add compatible strings for the PLIC found in UltraRISC DP1000 SoC. diff --git a/SPECS/linux-lts/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch b/SPECS/linux-lts/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch index cd328f7134..c47e05232b 100644 --- a/SPECS/linux-lts/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch +++ b/SPECS/linux-lts/0032-UPSTREAM-irqchip-sifive-plic-Cache-the-interrupt-ena.patch @@ -1,7 +1,7 @@ -From 58300649d94886f078c9ae5211d5e73fdb5d86dd Mon Sep 17 00:00:00 2001 +From 3f8b27c28b0516d4675130d799e52fe0e47cc190 Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Fri, 24 Oct 2025 09:36:42 +0100 -Subject: [PATCH 032/467] UPSTREAM: irqchip/sifive-plic: Cache the interrupt +Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Cache the interrupt enable state Optimize the PLIC driver by maintaining the interrupt enable state in the diff --git a/SPECS/linux-lts/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch b/SPECS/linux-lts/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch index 849bb391aa..35bf32dde3 100644 --- a/SPECS/linux-lts/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch +++ b/SPECS/linux-lts/0033-UPSTREAM-irqchip-sifive-plic-Add-support-for-UltraRI.patch @@ -1,8 +1,8 @@ -From 47ff9167559df87c4792972c083b403e13935fed Mon Sep 17 00:00:00 2001 +From 4ef8a6c6a0ad3046bd79c8e7ba68b55f65faba37 Mon Sep 17 00:00:00 2001 From: Charles Mirabile Date: Fri, 24 Oct 2025 09:36:43 +0100 -Subject: [PATCH 033/467] UPSTREAM: irqchip/sifive-plic: Add support for - UltraRISC DP1000 PLIC +Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Add support for UltraRISC + DP1000 PLIC Add a new compatible for the plic found in UltraRISC DP1000 with a quirk to work around a known hardware bug with IRQ claiming in the UR-CP100 cores. diff --git a/SPECS/linux-lts/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch b/SPECS/linux-lts/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch index d396f1c218..d80cdc947a 100644 --- a/SPECS/linux-lts/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch +++ b/SPECS/linux-lts/0034-UPSTREAM-riscv-cpu_ops_sbi-smp_processor_id-returns-.patch @@ -1,8 +1,8 @@ -From 44af92527d4da6d483b4439b15fafb8133938613 Mon Sep 17 00:00:00 2001 +From 88d1fb14b13933d5016b00a18582e2c2dec28c29 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 2 Jan 2026 14:58:39 +0000 -Subject: [PATCH 034/467] UPSTREAM: riscv: cpu_ops_sbi: smp_processor_id() - returns int, not unsigned int +Subject: [RUYI PATCH] UPSTREAM: riscv: cpu_ops_sbi: smp_processor_id() returns + int, not unsigned int The print in sbi_cpu_stop() assumes smp_processor_id() returns an unsigned int, when it is actually an int. Fix the format string to diff --git a/SPECS/linux-lts/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch b/SPECS/linux-lts/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch index 5bf082acbe..8df22862a6 100644 --- a/SPECS/linux-lts/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch +++ b/SPECS/linux-lts/0035-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch @@ -1,8 +1,8 @@ -From 5b142274eb87250e655c690bfa35b94fa0c7e37d Mon Sep 17 00:00:00 2001 +From b73688a2f1f8a16a7bb9609da304ebfd1dd7f968 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:29:59 -0500 -Subject: [PATCH 035/467] UPSTREAM: spi: dt-bindings: fsl-qspi: support - SpacemiT K1 +Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: support SpacemiT + K1 Add the SpacemiT K1 SoC QSPI IP to the list of supported hardware. This is the first non-Freescale device represented here. It has a nearly diff --git a/SPECS/linux-lts/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch b/SPECS/linux-lts/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch index df87b1b4de..398331aef3 100644 --- a/SPECS/linux-lts/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch +++ b/SPECS/linux-lts/0036-UPSTREAM-spi-dt-bindings-fsl-qspi-add-optional-reset.patch @@ -1,7 +1,7 @@ -From 3ac3b07de446afd26f22edb65a08e995d1e10394 Mon Sep 17 00:00:00 2001 +From 10c6bee274527e1fa5cf933eade792a8269bfa6e Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:00 -0500 -Subject: [PATCH 036/467] UPSTREAM: spi: dt-bindings: fsl-qspi: add optional +Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: add optional resets Allow two resets to be defined to support the SpacemiT K1 SoC QSPI IP. diff --git a/SPECS/linux-lts/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch b/SPECS/linux-lts/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch index 8cf653eea4..cb7815d689 100644 --- a/SPECS/linux-lts/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch +++ b/SPECS/linux-lts/0037-UPSTREAM-spi-fsl-qspi-add-optional-reset-support.patch @@ -1,7 +1,7 @@ -From 2383a4b7bd0919af694b0148ac45bfa98b5c3e5e Mon Sep 17 00:00:00 2001 +From eef2e7554dce124c0d27d06663f545ebf8b06b4f Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:01 -0500 -Subject: [PATCH 037/467] UPSTREAM: spi: fsl-qspi: add optional reset support +Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: add optional reset support Add support for one or more optional exclusive resets. These simply need to be deasserted at probe time, and can remain that way for the life of the diff --git a/SPECS/linux-lts/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch b/SPECS/linux-lts/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch index 5790e35633..78d52fb913 100644 --- a/SPECS/linux-lts/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch +++ b/SPECS/linux-lts/0038-UPSTREAM-spi-fsl-qspi-switch-predicates-to-bool.patch @@ -1,7 +1,7 @@ -From 6c4d84191d4a646424af4fd8f0bfa0cb6a8b88a5 Mon Sep 17 00:00:00 2001 +From 01d5441431b796aa0c7bef71294e87584b3a7ac2 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:02 -0500 -Subject: [PATCH 038/467] UPSTREAM: spi: fsl-qspi: switch predicates to bool +Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: switch predicates to bool Change all the needs_*() functions so they are no longer inline, and return bool rather than int. diff --git a/SPECS/linux-lts/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch b/SPECS/linux-lts/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch index 2a0208b72d..2a381e6fb3 100644 --- a/SPECS/linux-lts/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch +++ b/SPECS/linux-lts/0039-UPSTREAM-spi-fsl-qspi-add-a-clock-disable-quirk.patch @@ -1,7 +1,7 @@ -From df1020f14b967f34e7183e2820998cf3ae06f448 Mon Sep 17 00:00:00 2001 +From 513e5c7ca8e7b4847c1a9fa9328ecc1da6e03ca4 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:03 -0500 -Subject: [PATCH 039/467] UPSTREAM: spi: fsl-qspi: add a clock disable quirk +Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: add a clock disable quirk The SpacemiT K1 SoC QSPI implementation needs to avoid shutting off the clock when changing its rate. Add a new quirk to indicate that disabling diff --git a/SPECS/linux-lts/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch b/SPECS/linux-lts/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch index 25af899158..c71778c496 100644 --- a/SPECS/linux-lts/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch +++ b/SPECS/linux-lts/0040-UPSTREAM-spi-fsl-qspi-introduce-sfa_size-devtype-dat.patch @@ -1,8 +1,7 @@ -From 5ee33dac7a10929555229bc766263ba35d9f130b Mon Sep 17 00:00:00 2001 +From a5d94c358a562e2cf863fff92b78f0ee109abf10 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:04 -0500 -Subject: [PATCH 040/467] UPSTREAM: spi: fsl-qspi: introduce sfa_size devtype - data +Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: introduce sfa_size devtype data In fsl_qspi_default_setup(), four registers define the size of blocks of data to written to each of four chips that comprise SPI NOR flash storage. diff --git a/SPECS/linux-lts/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch b/SPECS/linux-lts/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch index 2b3039720f..f9a55c89ea 100644 --- a/SPECS/linux-lts/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch +++ b/SPECS/linux-lts/0041-UPSTREAM-spi-fsl-qspi-support-the-SpacemiT-K1-SoC.patch @@ -1,7 +1,7 @@ -From a8bec413546fceae68a0a397e5a6838e88544773 Mon Sep 17 00:00:00 2001 +From 014a6255ae46191c6eae14aa9de40535b4226ff0 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:05 -0500 -Subject: [PATCH 041/467] UPSTREAM: spi: fsl-qspi: support the SpacemiT K1 SoC +Subject: [RUYI PATCH] UPSTREAM: spi: fsl-qspi: support the SpacemiT K1 SoC Allow the SPI_FSL_QUADSPI Kconfig option to be selected if ARCH_SPACEMIT enabled. diff --git a/SPECS/linux-lts/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch b/SPECS/linux-lts/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch index 6059a178c4..8ad45c9e57 100644 --- a/SPECS/linux-lts/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch +++ b/SPECS/linux-lts/0042-UPSTREAM-dt-bindings-pci-spacemit-Introduce-PCIe-hos.patch @@ -1,7 +1,7 @@ -From da811b95eb6cac6d2befd327921dfa943928d913 Mon Sep 17 00:00:00 2001 +From 0d6c9d0a071fcea507cb2b62195d329fbfd4e3fa Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 13 Nov 2025 15:45:35 -0600 -Subject: [PATCH 042/467] UPSTREAM: dt-bindings: pci: spacemit: Introduce PCIe +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pci: spacemit: Introduce PCIe host controller Add the Devicetree binding for the PCIe Root Complex found on the SpacemiT diff --git a/SPECS/linux-lts/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch b/SPECS/linux-lts/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch index c6df251f89..15f880c23c 100644 --- a/SPECS/linux-lts/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch +++ b/SPECS/linux-lts/0043-UPSTREAM-PCI-spacemit-Add-SpacemiT-PCIe-host-driver.patch @@ -1,8 +1,7 @@ -From 2cd4c603d19ce303b9a474892adb6f0982e1a630 Mon Sep 17 00:00:00 2001 +From e886894eecb01fde7c6d687a520c00f8f8c6577b Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 13 Nov 2025 15:45:37 -0600 -Subject: [PATCH 043/467] UPSTREAM: PCI: spacemit: Add SpacemiT PCIe host - driver +Subject: [RUYI PATCH] UPSTREAM: PCI: spacemit: Add SpacemiT PCIe host driver Introduce a driver for the PCIe host controller found in the SpacemiT K1 SoC. The hardware is derived from the Synopsys DesignWare PCIe IP. The diff --git a/SPECS/linux-lts/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch b/SPECS/linux-lts/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch index 1485b4db34..9f87089128 100644 --- a/SPECS/linux-lts/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch +++ b/SPECS/linux-lts/0044-UPSTREAM-ASoC-dt-bindings-Add-bindings-for-SpacemiT-.patch @@ -1,8 +1,8 @@ -From 13a1831ca9975f970aa93217ef8f0d78be839558 Mon Sep 17 00:00:00 2001 +From dd167e5e356efc521fea95cca3dab9214d112f2f Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 17 Oct 2025 11:16:17 +0800 -Subject: [PATCH 044/467] UPSTREAM: ASoC: dt-bindings: Add bindings for - SpacemiT K1 +Subject: [RUYI PATCH] UPSTREAM: ASoC: dt-bindings: Add bindings for SpacemiT + K1 Add dt-binding for the i2s driver of SpacemiT's K1 SoC. diff --git a/SPECS/linux-lts/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch b/SPECS/linux-lts/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch index 7ac964a344..79edb29c56 100644 --- a/SPECS/linux-lts/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch +++ b/SPECS/linux-lts/0045-UPSTREAM-ASoC-spacemit-add-i2s-support-for-K1-SoC.patch @@ -1,7 +1,7 @@ -From 80ddb8319d498df366ee69857ac128f3a759fa09 Mon Sep 17 00:00:00 2001 +From f80e4dd0f340bda7a0c1d1cbcb59d4a346aa00dd Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 17 Oct 2025 11:16:18 +0800 -Subject: [PATCH 045/467] UPSTREAM: ASoC: spacemit: add i2s support for K1 SoC +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: add i2s support for K1 SoC Add ASoC platform driver for the SpacemiT K1 SoC full-duplex I2S controller. diff --git a/SPECS/linux-lts/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch b/SPECS/linux-lts/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch index 9821983f58..0efa4da8f2 100644 --- a/SPECS/linux-lts/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch +++ b/SPECS/linux-lts/0046-UPSTREAM-riscv-dts-spacemit-add-UART-pinctrl-combina.patch @@ -1,7 +1,7 @@ -From f28219b541a910d335af7fc7097a19a6e07b8712 Mon Sep 17 00:00:00 2001 +From affb820dfce75897605fbf89105fc1537a97d75b Mon Sep 17 00:00:00 2001 From: Hendrik Hamerlinck Date: Wed, 17 Sep 2025 08:59:07 +0200 -Subject: [PATCH 046/467] UPSTREAM: riscv: dts: spacemit: add UART pinctrl +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add UART pinctrl combinations Add UART pinctrl configurations based on the SoC datasheet and the diff --git a/SPECS/linux-lts/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch b/SPECS/linux-lts/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch index 548745b649..0351d09704 100644 --- a/SPECS/linux-lts/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch +++ b/SPECS/linux-lts/0047-UPSTREAM-riscv-dts-spacemit-enable-the-i2c8-adapter.patch @@ -1,8 +1,7 @@ -From 3f8785742d64517f721a7a1a9e35822265ad85a4 Mon Sep 17 00:00:00 2001 +From 1df92e173f9dd68d0498d92fb07c15a5b2ddf8eb Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:54 -0500 -Subject: [PATCH 047/467] UPSTREAM: riscv: dts: spacemit: enable the i2c8 - adapter +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable the i2c8 adapter Define properties for the I2C adapter that provides access to the SpacemiT P1 PMIC. Enable this adapter on the Banana Pi BPI-F3. diff --git a/SPECS/linux-lts/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch b/SPECS/linux-lts/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch index f309738c32..3b5e57ed41 100644 --- a/SPECS/linux-lts/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch +++ b/SPECS/linux-lts/0048-UPSTREAM-riscv-dts-spacemit-define-fixed-regulators.patch @@ -1,8 +1,7 @@ -From 60174cdbef524e4485dec91e48413d76da328022 Mon Sep 17 00:00:00 2001 +From b0c37d9383e9fff2cfae5d13e29a5b2fd134e33b Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:55 -0500 -Subject: [PATCH 048/467] UPSTREAM: riscv: dts: spacemit: define fixed - regulators +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define fixed regulators Define the DC power input and the 4v power as fixed supplies in the Banana Pi BPI-F3. diff --git a/SPECS/linux-lts/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch b/SPECS/linux-lts/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch index 0d1ed9ad79..4b13e15e20 100644 --- a/SPECS/linux-lts/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch +++ b/SPECS/linux-lts/0049-UPSTREAM-riscv-dts-spacemit-define-regulator-constra.patch @@ -1,7 +1,7 @@ -From 43691716fd0d18bd887592bb3f1a7dc63e9b49be Mon Sep 17 00:00:00 2001 +From 7fc9ff12b887fdc874ebb28f553e807648b6a4d4 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 25 Aug 2025 12:20:56 -0500 -Subject: [PATCH 049/467] UPSTREAM: riscv: dts: spacemit: define regulator +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define regulator constraints Define basic constraints for the regulators in the SpacemiT P1 PMIC, diff --git a/SPECS/linux-lts/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch b/SPECS/linux-lts/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch index 4266d9d06e..c64be604a7 100644 --- a/SPECS/linux-lts/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch +++ b/SPECS/linux-lts/0050-UPSTREAM-riscv-dts-spacemit-enable-the-i2c2-adapter-.patch @@ -1,8 +1,8 @@ -From 3d02f5d734bb489dc5c101affd5ad99687ffaffd Mon Sep 17 00:00:00 2001 +From a276be6d58f16c9c62bd6c0f76f6b2133fcfff5b Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 26 Sep 2025 19:54:37 +0200 -Subject: [PATCH 050/467] UPSTREAM: riscv: dts: spacemit: enable the i2c2 - adapter on BPI-F3 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable the i2c2 adapter + on BPI-F3 Define properties for the I2C adapter, and enable it on the BPI-F3. It will be used by the 24c02 eeprom. diff --git a/SPECS/linux-lts/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch b/SPECS/linux-lts/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch index feedcc216d..5c72618d50 100644 --- a/SPECS/linux-lts/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch +++ b/SPECS/linux-lts/0051-UPSTREAM-riscv-dts-spacemit-add-24c02-eeprom-on-BPI-.patch @@ -1,7 +1,7 @@ -From dc2d05a9865f35af5203640dc5f517c300667ae2 Mon Sep 17 00:00:00 2001 +From c34d30a8bde9d30953c0d83f0fa993d925f5e038 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 26 Sep 2025 19:54:38 +0200 -Subject: [PATCH 051/467] UPSTREAM: riscv: dts: spacemit: add 24c02 eeprom on +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add 24c02 eeprom on BPI-F3 The BPI-F3 board includes a 24c02 eeprom, that stores the MAC addresses diff --git a/SPECS/linux-lts/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch b/SPECS/linux-lts/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch index 3c9f8346f3..3e089bc47b 100644 --- a/SPECS/linux-lts/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch +++ b/SPECS/linux-lts/0052-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-BPI-F.patch @@ -1,7 +1,7 @@ -From 583c054150ac0bc72eb5f38eba8088468c3e93b5 Mon Sep 17 00:00:00 2001 +From d0ff2694bd729289ac0e0a95bd0ad9c82b10cbe1 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 26 Sep 2025 19:54:39 +0200 -Subject: [PATCH 052/467] UPSTREAM: riscv: dts: spacemit: add i2c aliases on +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add i2c aliases on BPI-F3 Add i2c aliases for i2c2 and i2c8 on BPI-F3. This is useful to keep a diff --git a/SPECS/linux-lts/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch b/SPECS/linux-lts/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch index 6ed1f8203d..2f6950c455 100644 --- a/SPECS/linux-lts/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch +++ b/SPECS/linux-lts/0053-UPSTREAM-riscv-dts-spacemit-add-Ethernet-and-PDMA-to.patch @@ -1,8 +1,8 @@ -From 84af2f4907b4dfc470ac41d11760d57cd7907927 Mon Sep 17 00:00:00 2001 +From 13fa4b662d56827d91fb4cbc78cbaf44253e90c9 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Wed, 22 Oct 2025 20:18:38 +0000 -Subject: [PATCH 053/467] UPSTREAM: riscv: dts: spacemit: add Ethernet and PDMA - to OrangePi RV2 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add Ethernet and PDMA to + OrangePi RV2 The OrangePi RV2 board ships two RGMII ethernet ports. Each has an external Motorcomm YT8531C PHY attached, the PHY uses GPIO diff --git a/SPECS/linux-lts/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch b/SPECS/linux-lts/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch index 2b5114e787..e1ebb490cb 100644 --- a/SPECS/linux-lts/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch +++ b/SPECS/linux-lts/0054-UPSTREAM-riscv-dts-spacemit-add-MusePi-Pro-board-dev.patch @@ -1,7 +1,7 @@ -From 0c5f1b6c12c4797ce96d82ce0bc35941b7d11848 Mon Sep 17 00:00:00 2001 +From 3dafd093bd3316afd9db38030ed61ebb2382f469 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 23 Oct 2025 15:28:30 +0800 -Subject: [PATCH 054/467] UPSTREAM: riscv: dts: spacemit: add MusePi Pro board +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add MusePi Pro board device tree Add initial device tree support for the MusePi Pro board [1]. diff --git a/SPECS/linux-lts/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch b/SPECS/linux-lts/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch index b802662e55..1d90bd8999 100644 --- a/SPECS/linux-lts/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch +++ b/SPECS/linux-lts/0055-UPSTREAM-riscv-dts-spacemit-enable-K1-SoC-QSPI-on-BP.patch @@ -1,7 +1,7 @@ -From 31318a05caadf4e7a9d89bf5c11a7e4bb248e835 Mon Sep 17 00:00:00 2001 +From ba2b866292f1f2f274ff75a54e87fe7bc5dad3e2 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:06 -0500 -Subject: [PATCH 055/467] UPSTREAM: riscv: dts: spacemit: enable K1 SoC QSPI on +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable K1 SoC QSPI on BPI-F3 Define DTS nodes to enable support for QSPI on the K1 SoC, including the diff --git a/SPECS/linux-lts/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch b/SPECS/linux-lts/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch index fdb81df0ad..6288d13917 100644 --- a/SPECS/linux-lts/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch +++ b/SPECS/linux-lts/0056-UPSTREAM-riscv-dts-spacemit-Add-OrangePi-R2S-board-d.patch @@ -1,8 +1,8 @@ -From bb2450948146eabe3ab427e20f97b58aca4b1d6c Mon Sep 17 00:00:00 2001 +From 24c1c297e0c77c81c2e3a9ed9690f3e133986a22 Mon Sep 17 00:00:00 2001 From: Michael Opdenacker Date: Wed, 12 Nov 2025 04:44:42 +0000 -Subject: [PATCH 056/467] UPSTREAM: riscv: dts: spacemit: Add OrangePi R2S - board device tree +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add OrangePi R2S board + device tree Add initial device tree support for the OrangePi RV2 board [1], which is marketed as using the Ky X1 SoC but is identical in die and package diff --git a/SPECS/linux-lts/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch b/SPECS/linux-lts/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch index 8604ed55e1..d6b11da6e5 100644 --- a/SPECS/linux-lts/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch +++ b/SPECS/linux-lts/0057-UPSTREAM-riscv-dts-spacemit-reorder-i2c2-node.patch @@ -1,7 +1,7 @@ -From baea402c4353408511c0a1dd49a95a3a6cefa14c Mon Sep 17 00:00:00 2001 +From 1831ac73812e9bb0337b60cf0cbe5e61baaf4769 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 5 Nov 2025 11:37:43 +0800 -Subject: [PATCH 057/467] UPSTREAM: riscv: dts: spacemit: reorder i2c2 node +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: reorder i2c2 node Reorder the i2c2 node to its correct position according to its register address.This improves the readability and maintainability diff --git a/SPECS/linux-lts/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch b/SPECS/linux-lts/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch index ae0c476561..128376f03e 100644 --- a/SPECS/linux-lts/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch +++ b/SPECS/linux-lts/0058-UPSTREAM-riscv-dts-spacemit-define-all-missing-I2C-c.patch @@ -1,8 +1,8 @@ -From c45c776b556de646db335514a310bf0caf45e297 Mon Sep 17 00:00:00 2001 +From 30931c3912167e96f982909390b4cb13d61548d5 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 5 Nov 2025 11:37:44 +0800 -Subject: [PATCH 058/467] UPSTREAM: riscv: dts: spacemit: define all missing - I2C controller nodes +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: define all missing I2C + controller nodes SpacemiT K1 SoC is equipped with a total of nine I2C controllers, ranging from I2C0 to I2C8. diff --git a/SPECS/linux-lts/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch b/SPECS/linux-lts/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch index 9df139c76a..637f8129fd 100644 --- a/SPECS/linux-lts/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch +++ b/SPECS/linux-lts/0059-UPSTREAM-rtc-spacemit-MFD_SPACEMIT_P1-as-dependencie.patch @@ -1,8 +1,7 @@ -From 70f112bf88bec82aeedec4c778bcd4f3232a0765 Mon Sep 17 00:00:00 2001 +From 915b04c620188a1aac7cc9e8481bd1dc3069817d Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Tue, 18 Nov 2025 14:08:06 +0800 -Subject: [PATCH 059/467] UPSTREAM: rtc: spacemit: MFD_SPACEMIT_P1 as - dependencies +Subject: [RUYI PATCH] UPSTREAM: rtc: spacemit: MFD_SPACEMIT_P1 as dependencies RTC_DRV_SPACEMIT_P1 is a subdevice of P1 and should depend on MFD_SPACEMIT_P1 rather than selecting it directly. Using 'select' diff --git a/SPECS/linux-lts/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch b/SPECS/linux-lts/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch index 8c75b3d1d7..8765e4955a 100644 --- a/SPECS/linux-lts/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch +++ b/SPECS/linux-lts/0060-UPSTREAM-mfd-simple-mfd-i2c-Remove-select-I2C_K1-fro.patch @@ -1,8 +1,8 @@ -From 5428e4b1551b578c73d4dbb8ca29e15132ed6cc3 Mon Sep 17 00:00:00 2001 +From 6069d468c347c12814556df14bbe53dade5799be Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Mon, 27 Oct 2025 13:48:05 +0800 -Subject: [PATCH 060/467] UPSTREAM: mfd: simple-mfd-i2c: Remove select I2C_K1 - from MFD_SPACEMIT_P1 +Subject: [RUYI PATCH] UPSTREAM: mfd: simple-mfd-i2c: Remove select I2C_K1 from + MFD_SPACEMIT_P1 select will force a symbol to a specific value without considering its dependencies. As a result, the i2c-k1 driver will fail to build diff --git a/SPECS/linux-lts/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch b/SPECS/linux-lts/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch index e03efac6a9..29f66cd23f 100644 --- a/SPECS/linux-lts/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch +++ b/SPECS/linux-lts/0061-UPSTREAM-driver-reset-spacemit-p1-add-driver-for-pow.patch @@ -1,7 +1,7 @@ -From d7b622bee8767fa7990914aca5f7df68b486ec3a Mon Sep 17 00:00:00 2001 +From eef8f9cc817fec7a4c2229a9b9ee475a0efcf53b Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 3 Nov 2025 00:01:59 +0100 -Subject: [PATCH 061/467] UPSTREAM: driver: reset: spacemit-p1: add driver for +Subject: [RUYI PATCH] UPSTREAM: driver: reset: spacemit-p1: add driver for poweroff/reboot This driver implements poweroff/reboot support for the SpacemiT P1 PMIC diff --git a/SPECS/linux-lts/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch b/SPECS/linux-lts/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch index e1ec6c0a80..9e03454da1 100644 --- a/SPECS/linux-lts/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch +++ b/SPECS/linux-lts/0062-UPSTREAM-riscv-remove-irqflags.h-inclusion-in-asm-bi.patch @@ -1,7 +1,7 @@ -From 689210eca440a1f4fbcfb711fec8d91331cea13e Mon Sep 17 00:00:00 2001 +From a33608232c9c99d13d018635c30ee0ff1983de7e Mon Sep 17 00:00:00 2001 From: Yunhui Cui Date: Tue, 16 Dec 2025 09:47:19 +0800 -Subject: [PATCH 062/467] UPSTREAM: riscv: remove irqflags.h inclusion in +Subject: [RUYI PATCH] UPSTREAM: riscv: remove irqflags.h inclusion in asm/bitops.h The arch/riscv/include/asm/bitops.h does not functionally require diff --git a/SPECS/linux-lts/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch b/SPECS/linux-lts/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch index 4191f8109c..0fb3f34661 100644 --- a/SPECS/linux-lts/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch +++ b/SPECS/linux-lts/0063-UPSTREAM-riscv-atomic.h-use-RISCV_FULL_BARRIER-in-_a.patch @@ -1,7 +1,7 @@ -From c7f82d8c41148f7827e892b69de32cfc5f5b6ac8 Mon Sep 17 00:00:00 2001 +From 34f41ea98d21a5605f1d5973259656f6e6557de0 Mon Sep 17 00:00:00 2001 From: Zongmin Zhou Date: Thu, 20 Nov 2025 17:58:31 +0800 -Subject: [PATCH 063/467] UPSTREAM: riscv/atomic.h: use RISCV_FULL_BARRIER in +Subject: [RUYI PATCH] UPSTREAM: riscv/atomic.h: use RISCV_FULL_BARRIER in _arch_atomic* function. Replace the same code with the pre-defined macro diff --git a/SPECS/linux-lts/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch b/SPECS/linux-lts/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch index 81b4d9efe4..0604111102 100644 --- a/SPECS/linux-lts/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch +++ b/SPECS/linux-lts/0064-UPSTREAM-drm-dumb-buffers-Sanitize-output-on-errors.patch @@ -1,7 +1,7 @@ -From 11ee08759592cbf595fbbc34aab1f2e631fcaaf1 Mon Sep 17 00:00:00 2001 +From 8030689f50a72fc225dd6c31ad77d6b868549463 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 21 Aug 2025 10:17:08 +0200 -Subject: [PATCH 064/467] UPSTREAM: drm/dumb-buffers: Sanitize output on errors +Subject: [RUYI PATCH] UPSTREAM: drm/dumb-buffers: Sanitize output on errors The ioctls MODE_CREATE_DUMB and MODE_MAP_DUMB return results into a memory buffer supplied by user space. On errors, it is possible that diff --git a/SPECS/linux-lts/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch b/SPECS/linux-lts/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch index a51677cd2c..c249232713 100644 --- a/SPECS/linux-lts/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch +++ b/SPECS/linux-lts/0065-UPSTREAM-drm-dumb-buffers-Provide-helper-to-set-pitc.patch @@ -1,8 +1,8 @@ -From ffc2daa0d4924fb2007651922cc6c14f597aff80 Mon Sep 17 00:00:00 2001 +From cf1dda8a91f6866dead5cfac3205be1ea706a065 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Thu, 21 Aug 2025 10:17:09 +0200 -Subject: [PATCH 065/467] UPSTREAM: drm/dumb-buffers: Provide helper to set - pitch and size +Subject: [RUYI PATCH] UPSTREAM: drm/dumb-buffers: Provide helper to set pitch + and size Add drm_modes_size_dumb(), a helper to calculate the dumb-buffer scanline pitch and allocation size. Implementations of struct diff --git a/SPECS/linux-lts/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch b/SPECS/linux-lts/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch new file mode 100644 index 0000000000..d3d98f5867 --- /dev/null +++ b/SPECS/linux-lts/0066-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch @@ -0,0 +1,72 @@ +From 5a54ac19c87347a2165595055cab86383cefac4f Mon Sep 17 00:00:00 2001 +From: Thomas Zimmermann +Date: Tue, 16 Sep 2025 10:36:22 +0200 +Subject: [RUYI PATCH] UPSTREAM: drm/hypervdrm: Use vblank timer + +HyperV's virtual hardware does not provide vblank interrupts. Use a +vblank timer to simulate the interrupt. Rate-limits the display's +update frequency to the display-mode settings. Avoids excessive CPU +overhead with compositors that do not rate-limit their output. + +Signed-off-by: Thomas Zimmermann +Reviewed-by: Javier Martinez Canillas +Tested-by: Michael Kelley +Tested-by: Prasanna Kumar T S M +Link: https://lore.kernel.org/r/20250916083816.30275-5-tzimmermann@suse.de +(cherry picked from commit 52e6b198833411564e0b9ce6e96bbd3d72f961e7) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/hyperv/hyperv_drm_modeset.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c +index 945b9482bcb3..6e6eb1c12a68 100644 +--- a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c ++++ b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c +@@ -19,6 +19,8 @@ + #include + #include + #include ++#include ++#include + + #include "hyperv_drm.h" + +@@ -111,11 +113,15 @@ static void hyperv_crtc_helper_atomic_enable(struct drm_crtc *crtc, + crtc_state->mode.hdisplay, + crtc_state->mode.vdisplay, + plane_state->fb->pitches[0]); ++ ++ drm_crtc_vblank_on(crtc); + } + + static const struct drm_crtc_helper_funcs hyperv_crtc_helper_funcs = { + .atomic_check = drm_crtc_helper_atomic_check, ++ .atomic_flush = drm_crtc_vblank_atomic_flush, + .atomic_enable = hyperv_crtc_helper_atomic_enable, ++ .atomic_disable = drm_crtc_vblank_atomic_disable, + }; + + static const struct drm_crtc_funcs hyperv_crtc_funcs = { +@@ -125,6 +131,7 @@ static const struct drm_crtc_funcs hyperv_crtc_funcs = { + .page_flip = drm_atomic_helper_page_flip, + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, ++ DRM_CRTC_VBLANK_TIMER_FUNCS, + }; + + static int hyperv_plane_atomic_check(struct drm_plane *plane, +@@ -321,6 +328,10 @@ int hyperv_mode_config_init(struct hyperv_drm_device *hv) + return ret; + } + ++ ret = drm_vblank_init(dev, 1); ++ if (ret) ++ return ret; ++ + drm_mode_config_reset(dev); + + return 0; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0066-UPSTREAM-drm-vblank-Add-vblank-timer.patch b/SPECS/linux-lts/0066-UPSTREAM-drm-vblank-Add-vblank-timer.patch deleted file mode 100644 index 9ae7a30e23..0000000000 --- a/SPECS/linux-lts/0066-UPSTREAM-drm-vblank-Add-vblank-timer.patch +++ /dev/null @@ -1,533 +0,0 @@ -From e7f0684e97837281f337a4249384ae7efd8c3fc0 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Tue, 16 Sep 2025 10:36:19 +0200 -Subject: [PATCH 066/467] UPSTREAM: drm/vblank: Add vblank timer - -The vblank timer simulates a vblank interrupt for hardware without -support. Rate-limits the display update frequency. - -DRM drivers for hardware without vblank support apply display updates -ASAP. A vblank event informs DRM clients of the completed update. -Userspace compositors immediately schedule the next update, which -creates significant load on virtualization outputs. Display updates -are usually fast on virtualization outputs, as their framebuffers are -in regular system memory and there's no hardware vblank interrupt to -throttle the update rate. - -The vblank timer is a HR timer that signals the vblank in software. -It limits the update frequency of a DRM driver similar to a hardware -vblank interrupt. The timer is not synchronized to the actual vblank -interval of the display. - -The code has been adopted from vkms, which added the funtionality -in commit 3a0709928b17 ("drm/vkms: Add vblank events simulated by -hrtimers"). - -The new implementation is part of the existing vblank support, -which sets up the timer automatically. Drivers only have to start -and cancel the vblank timer as part of enabling and disabling the -CRTC. The new vblank helper library provides callbacks for struct -drm_crtc_funcs. - -The standard way for handling vblank is to call drm_crtc_handle_vblank(). -Drivers that require additional processing, such as vkms, can init -handle_vblank_timeout in struct drm_crtc_helper_funcs to refer to -their timeout handler. - -There's a possible deadlock between drm_crtc_handle_vblank() and -hrtimer_cancel(). [1] The implementation avoids to call hrtimer_cancel() -directly and instead signals to the timer function to not restart -itself. - -v4: -- fix possible race condition between timeout and atomic commit (Michael) -v3: -- avoid deadlock when cancelling timer (Ville, Lyude) -v2: -- implement vblank timer entirely in vblank helpers -- downgrade overrun warning to debug -- fix docs - -Signed-off-by: Thomas Zimmermann -Tested-by: Louis Chauvet -Reviewed-by: Louis Chauvet -Reviewed-by: Javier Martinez Canillas -Tested-by: Michael Kelley -Link: https://lore.kernel.org/all/20250510094757.4174662-1-zengheng4@huawei.com/ # [1] -Link: https://lore.kernel.org/r/20250916083816.30275-2-tzimmermann@suse.de -(cherry picked from commit 74afeb8128502a529041a2566febd26053a7be11) -Signed-off-by: Han Gao ---- - Documentation/gpu/drm-kms-helpers.rst | 12 ++ - drivers/gpu/drm/Makefile | 3 +- - drivers/gpu/drm/drm_vblank.c | 172 ++++++++++++++++++++++- - drivers/gpu/drm/drm_vblank_helper.c | 96 +++++++++++++ - include/drm/drm_modeset_helper_vtables.h | 12 ++ - include/drm/drm_vblank.h | 32 +++++ - include/drm/drm_vblank_helper.h | 33 +++++ - 7 files changed, 357 insertions(+), 3 deletions(-) - create mode 100644 drivers/gpu/drm/drm_vblank_helper.c - create mode 100644 include/drm/drm_vblank_helper.h - -diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst -index 5139705089f2..781129f78b06 100644 ---- a/Documentation/gpu/drm-kms-helpers.rst -+++ b/Documentation/gpu/drm-kms-helpers.rst -@@ -92,6 +92,18 @@ GEM Atomic Helper Reference - .. kernel-doc:: drivers/gpu/drm/drm_gem_atomic_helper.c - :export: - -+VBLANK Helper Reference -+----------------------- -+ -+.. kernel-doc:: drivers/gpu/drm/drm_vblank_helper.c -+ :doc: overview -+ -+.. kernel-doc:: include/drm/drm_vblank_helper.h -+ :internal: -+ -+.. kernel-doc:: drivers/gpu/drm/drm_vblank_helper.c -+ :export: -+ - Simple KMS Helper Reference - =========================== - -diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile -index 742f0d590c5a..b248e64587ed 100644 ---- a/drivers/gpu/drm/Makefile -+++ b/drivers/gpu/drm/Makefile -@@ -152,7 +152,8 @@ drm_kms_helper-y := \ - drm_plane_helper.o \ - drm_probe_helper.o \ - drm_self_refresh_helper.o \ -- drm_simple_kms_helper.o -+ drm_simple_kms_helper.o \ -+ drm_vblank_helper.o - drm_kms_helper-$(CONFIG_DRM_PANEL_BRIDGE) += bridge/panel.o - drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fb_helper.o - obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o -diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c -index 46f59883183d..61e211fd3c9c 100644 ---- a/drivers/gpu/drm/drm_vblank.c -+++ b/drivers/gpu/drm/drm_vblank.c -@@ -136,8 +136,17 @@ - * vblanks after a timer has expired, which can be configured through the - * ``vblankoffdelay`` module parameter. - * -- * Drivers for hardware without support for vertical-blanking interrupts -- * must not call drm_vblank_init(). For such drivers, atomic helpers will -+ * Drivers for hardware without support for vertical-blanking interrupts can -+ * use DRM vblank timers to send vblank events at the rate of the current -+ * display mode's refresh. While not synchronized to the hardware's -+ * vertical-blanking regions, the timer helps DRM clients and compositors to -+ * adapt their update cycle to the display output. Drivers should set up -+ * vblanking as usual, but call drm_crtc_vblank_start_timer() and -+ * drm_crtc_vblank_cancel_timer() as part of their atomic mode setting. -+ * See also DRM vblank helpers for more information. -+ * -+ * Drivers without support for vertical-blanking interrupts nor timers must -+ * not call drm_vblank_init(). For these drivers, atomic helpers will - * automatically generate fake vblank events as part of the display update. - * This functionality also can be controlled by the driver by enabling and - * disabling struct drm_crtc_state.no_vblank. -@@ -508,6 +517,9 @@ static void drm_vblank_init_release(struct drm_device *dev, void *ptr) - drm_WARN_ON(dev, READ_ONCE(vblank->enabled) && - drm_core_check_feature(dev, DRIVER_MODESET)); - -+ if (vblank->vblank_timer.crtc) -+ hrtimer_cancel(&vblank->vblank_timer.timer); -+ - drm_vblank_destroy_worker(vblank); - timer_delete_sync(&vblank->disable_timer); - } -@@ -2162,3 +2174,159 @@ int drm_crtc_queue_sequence_ioctl(struct drm_device *dev, void *data, - return ret; - } - -+/* -+ * VBLANK timer -+ */ -+ -+static enum hrtimer_restart drm_vblank_timer_function(struct hrtimer *timer) -+{ -+ struct drm_vblank_crtc_timer *vtimer = -+ container_of(timer, struct drm_vblank_crtc_timer, timer); -+ struct drm_crtc *crtc = vtimer->crtc; -+ const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; -+ struct drm_device *dev = crtc->dev; -+ unsigned long flags; -+ ktime_t interval; -+ u64 ret_overrun; -+ bool succ; -+ -+ spin_lock_irqsave(&vtimer->interval_lock, flags); -+ interval = vtimer->interval; -+ spin_unlock_irqrestore(&vtimer->interval_lock, flags); -+ -+ if (!interval) -+ return HRTIMER_NORESTART; -+ -+ ret_overrun = hrtimer_forward_now(&vtimer->timer, interval); -+ if (ret_overrun != 1) -+ drm_dbg_vbl(dev, "vblank timer overrun\n"); -+ -+ if (crtc_funcs->handle_vblank_timeout) -+ succ = crtc_funcs->handle_vblank_timeout(crtc); -+ else -+ succ = drm_crtc_handle_vblank(crtc); -+ if (!succ) -+ return HRTIMER_NORESTART; -+ -+ return HRTIMER_RESTART; -+} -+ -+/** -+ * drm_crtc_vblank_start_timer - Starts the vblank timer on the given CRTC -+ * @crtc: the CRTC -+ * -+ * Drivers should call this function from their CRTC's enable_vblank -+ * function to start a vblank timer. The timer will fire after the duration -+ * of a full frame. drm_crtc_vblank_cancel_timer() disables a running timer. -+ * -+ * Returns: -+ * 0 on success, or a negative errno code otherwise. -+ */ -+int drm_crtc_vblank_start_timer(struct drm_crtc *crtc) -+{ -+ struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); -+ struct drm_vblank_crtc_timer *vtimer = &vblank->vblank_timer; -+ unsigned long flags; -+ -+ if (!vtimer->crtc) { -+ /* -+ * Set up the data structures on the first invocation. -+ */ -+ vtimer->crtc = crtc; -+ spin_lock_init(&vtimer->interval_lock); -+ hrtimer_setup(&vtimer->timer, drm_vblank_timer_function, -+ CLOCK_MONOTONIC, HRTIMER_MODE_REL); -+ } else { -+ /* -+ * Timer should not be active. If it is, wait for the -+ * previous cancel operations to finish. -+ */ -+ while (hrtimer_active(&vtimer->timer)) -+ hrtimer_try_to_cancel(&vtimer->timer); -+ } -+ -+ drm_calc_timestamping_constants(crtc, &crtc->mode); -+ -+ spin_lock_irqsave(&vtimer->interval_lock, flags); -+ vtimer->interval = ns_to_ktime(vblank->framedur_ns); -+ spin_unlock_irqrestore(&vtimer->interval_lock, flags); -+ -+ hrtimer_start(&vtimer->timer, vtimer->interval, HRTIMER_MODE_REL); -+ -+ return 0; -+} -+EXPORT_SYMBOL(drm_crtc_vblank_start_timer); -+ -+/** -+ * drm_crtc_vblank_start_timer - Cancels the given CRTC's vblank timer -+ * @crtc: the CRTC -+ * -+ * Drivers should call this function from their CRTC's disable_vblank -+ * function to stop a vblank timer. -+ */ -+void drm_crtc_vblank_cancel_timer(struct drm_crtc *crtc) -+{ -+ struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); -+ struct drm_vblank_crtc_timer *vtimer = &vblank->vblank_timer; -+ unsigned long flags; -+ -+ /* -+ * Calling hrtimer_cancel() can result in a deadlock with DRM's -+ * vblank_time_lime_lock and hrtimers' softirq_expiry_lock. So -+ * clear interval and indicate cancellation. The timer function -+ * will cancel itself on the next invocation. -+ */ -+ -+ spin_lock_irqsave(&vtimer->interval_lock, flags); -+ vtimer->interval = 0; -+ spin_unlock_irqrestore(&vtimer->interval_lock, flags); -+ -+ hrtimer_try_to_cancel(&vtimer->timer); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_cancel_timer); -+ -+/** -+ * drm_crtc_vblank_get_vblank_timeout - Returns the vblank timeout -+ * @crtc: The CRTC -+ * @vblank_time: Returns the next vblank timestamp -+ * -+ * The helper drm_crtc_vblank_get_vblank_timeout() returns the next vblank -+ * timestamp of the CRTC's vblank timer according to the timer's expiry -+ * time. -+ */ -+void drm_crtc_vblank_get_vblank_timeout(struct drm_crtc *crtc, ktime_t *vblank_time) -+{ -+ struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); -+ struct drm_vblank_crtc_timer *vtimer = &vblank->vblank_timer; -+ u64 cur_count; -+ ktime_t cur_time; -+ -+ if (!READ_ONCE(vblank->enabled)) { -+ *vblank_time = ktime_get(); -+ return; -+ } -+ -+ /* -+ * A concurrent vblank timeout could update the expires field before -+ * we compare it with the vblank time. Hence we'd compare the old -+ * expiry time to the new vblank time; deducing the timer had already -+ * expired. Reread until we get consistent values from both fields. -+ */ -+ do { -+ cur_count = drm_crtc_vblank_count_and_time(crtc, &cur_time); -+ *vblank_time = READ_ONCE(vtimer->timer.node.expires); -+ } while (cur_count != drm_crtc_vblank_count_and_time(crtc, &cur_time)); -+ -+ if (drm_WARN_ON(crtc->dev, !ktime_compare(*vblank_time, cur_time))) -+ return; /* Already expired */ -+ -+ /* -+ * To prevent races we roll the hrtimer forward before we do any -+ * interrupt processing - this is how real hw works (the interrupt -+ * is only generated after all the vblank registers are updated) -+ * and what the vblank core expects. Therefore we need to always -+ * correct the timestamp by one frame. -+ */ -+ *vblank_time = ktime_sub(*vblank_time, vtimer->interval); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_get_vblank_timeout); -diff --git a/drivers/gpu/drm/drm_vblank_helper.c b/drivers/gpu/drm/drm_vblank_helper.c -new file mode 100644 -index 000000000000..f94d1e706191 ---- /dev/null -+++ b/drivers/gpu/drm/drm_vblank_helper.c -@@ -0,0 +1,96 @@ -+// SPDX-License-Identifier: MIT -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/** -+ * DOC: overview -+ * -+ * The vblank helper library provides functions for supporting vertical -+ * blanking in DRM drivers. -+ * -+ * For vblank timers, several callback implementations are available. -+ * Drivers enable support for vblank timers by setting the vblank callbacks -+ * in struct &drm_crtc_funcs to the helpers provided by this library. The -+ * initializer macro DRM_CRTC_VBLANK_TIMER_FUNCS does this conveniently. -+ * -+ * Once the driver enables vblank support with drm_vblank_init(), each -+ * CRTC's vblank timer fires according to the programmed display mode. By -+ * default, the vblank timer invokes drm_crtc_handle_vblank(). Drivers with -+ * more specific requirements can set their own handler function in -+ * struct &drm_crtc_helper_funcs.handle_vblank_timeout. -+ */ -+ -+/* -+ * VBLANK timer -+ */ -+ -+/** -+ * drm_crtc_vblank_helper_enable_vblank_timer - Implements struct &drm_crtc_funcs.enable_vblank -+ * @crtc: The CRTC -+ * -+ * The helper drm_crtc_vblank_helper_enable_vblank_timer() implements -+ * enable_vblank of struct drm_crtc_helper_funcs for CRTCs that require -+ * a VBLANK timer. It sets up the timer on the first invocation. The -+ * started timer expires after the current frame duration. See struct -+ * &drm_vblank_crtc.framedur_ns. -+ * -+ * See also struct &drm_crtc_helper_funcs.enable_vblank. -+ * -+ * Returns: -+ * 0 on success, or a negative errno code otherwise. -+ */ -+int drm_crtc_vblank_helper_enable_vblank_timer(struct drm_crtc *crtc) -+{ -+ return drm_crtc_vblank_start_timer(crtc); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_helper_enable_vblank_timer); -+ -+/** -+ * drm_crtc_vblank_helper_disable_vblank_timer - Implements struct &drm_crtc_funcs.disable_vblank -+ * @crtc: The CRTC -+ * -+ * The helper drm_crtc_vblank_helper_disable_vblank_timer() implements -+ * disable_vblank of struct drm_crtc_funcs for CRTCs that require a -+ * VBLANK timer. -+ * -+ * See also struct &drm_crtc_helper_funcs.disable_vblank. -+ */ -+void drm_crtc_vblank_helper_disable_vblank_timer(struct drm_crtc *crtc) -+{ -+ drm_crtc_vblank_cancel_timer(crtc); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_helper_disable_vblank_timer); -+ -+/** -+ * drm_crtc_vblank_helper_get_vblank_timestamp_from_timer - -+ * Implements struct &drm_crtc_funcs.get_vblank_timestamp -+ * @crtc: The CRTC -+ * @max_error: Maximum acceptable error -+ * @vblank_time: Returns the next vblank timestamp -+ * @in_vblank_irq: True is called from drm_crtc_handle_vblank() -+ * -+ * The helper drm_crtc_helper_get_vblank_timestamp_from_timer() implements -+ * get_vblank_timestamp of struct drm_crtc_funcs for CRTCs that require a -+ * VBLANK timer. It returns the timestamp according to the timer's expiry -+ * time. -+ * -+ * See also struct &drm_crtc_funcs.get_vblank_timestamp. -+ * -+ * Returns: -+ * True on success, or false otherwise. -+ */ -+bool drm_crtc_vblank_helper_get_vblank_timestamp_from_timer(struct drm_crtc *crtc, -+ int *max_error, -+ ktime_t *vblank_time, -+ bool in_vblank_irq) -+{ -+ drm_crtc_vblank_get_vblank_timeout(crtc, vblank_time); -+ -+ return true; -+} -+EXPORT_SYMBOL(drm_crtc_vblank_helper_get_vblank_timestamp_from_timer); -diff --git a/include/drm/drm_modeset_helper_vtables.h b/include/drm/drm_modeset_helper_vtables.h -index ce7c7aeac887..fe32854b7ffe 100644 ---- a/include/drm/drm_modeset_helper_vtables.h -+++ b/include/drm/drm_modeset_helper_vtables.h -@@ -490,6 +490,18 @@ struct drm_crtc_helper_funcs { - bool in_vblank_irq, int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode); -+ -+ /** -+ * @handle_vblank_timeout: Handles timeouts of the vblank timer. -+ * -+ * Called by CRTC's the vblank timer on each timeout. Semantics is -+ * equivalient to drm_crtc_handle_vblank(). Implementations should -+ * invoke drm_crtc_handle_vblank() as part of processing the timeout. -+ * -+ * This callback is optional. If unset, the vblank timer invokes -+ * drm_crtc_handle_vblank() directly. -+ */ -+ bool (*handle_vblank_timeout)(struct drm_crtc *crtc); - }; - - /** -diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h -index 151ab1e85b1b..ffa564d79638 100644 ---- a/include/drm/drm_vblank.h -+++ b/include/drm/drm_vblank.h -@@ -25,6 +25,7 @@ - #define _DRM_VBLANK_H_ - - #include -+#include - #include - #include - #include -@@ -103,6 +104,28 @@ struct drm_vblank_crtc_config { - bool disable_immediate; - }; - -+/** -+ * struct drm_vblank_crtc_timer - vblank timer for a CRTC -+ */ -+struct drm_vblank_crtc_timer { -+ /** -+ * @timer: The vblank's high-resolution timer -+ */ -+ struct hrtimer timer; -+ /** -+ * @interval_lock: Protects @interval -+ */ -+ spinlock_t interval_lock; -+ /** -+ * @interval: Duration between two vblanks -+ */ -+ ktime_t interval; -+ /** -+ * @crtc: The timer's CRTC -+ */ -+ struct drm_crtc *crtc; -+}; -+ - /** - * struct drm_vblank_crtc - vblank tracking for a CRTC - * -@@ -254,6 +277,11 @@ struct drm_vblank_crtc { - * cancelled. - */ - wait_queue_head_t work_wait_queue; -+ -+ /** -+ * @vblank_timer: Holds the state of the vblank timer -+ */ -+ struct drm_vblank_crtc_timer vblank_timer; - }; - - struct drm_vblank_crtc *drm_crtc_vblank_crtc(struct drm_crtc *crtc); -@@ -290,6 +318,10 @@ wait_queue_head_t *drm_crtc_vblank_waitqueue(struct drm_crtc *crtc); - void drm_crtc_set_max_vblank_count(struct drm_crtc *crtc, - u32 max_vblank_count); - -+int drm_crtc_vblank_start_timer(struct drm_crtc *crtc); -+void drm_crtc_vblank_cancel_timer(struct drm_crtc *crtc); -+void drm_crtc_vblank_get_vblank_timeout(struct drm_crtc *crtc, ktime_t *vblank_time); -+ - /* - * Helpers for struct drm_crtc_funcs - */ -diff --git a/include/drm/drm_vblank_helper.h b/include/drm/drm_vblank_helper.h -new file mode 100644 -index 000000000000..74a971d0cfba ---- /dev/null -+++ b/include/drm/drm_vblank_helper.h -@@ -0,0 +1,33 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef _DRM_VBLANK_HELPER_H_ -+#define _DRM_VBLANK_HELPER_H_ -+ -+#include -+#include -+ -+struct drm_crtc; -+ -+/* -+ * VBLANK timer -+ */ -+ -+int drm_crtc_vblank_helper_enable_vblank_timer(struct drm_crtc *crtc); -+void drm_crtc_vblank_helper_disable_vblank_timer(struct drm_crtc *crtc); -+bool drm_crtc_vblank_helper_get_vblank_timestamp_from_timer(struct drm_crtc *crtc, -+ int *max_error, -+ ktime_t *vblank_time, -+ bool in_vblank_irq); -+ -+/** -+ * DRM_CRTC_VBLANK_TIMER_FUNCS - Default implementation for VBLANK timers -+ * -+ * This macro initializes struct &drm_crtc_funcs to default helpers for -+ * VBLANK timers. -+ */ -+#define DRM_CRTC_VBLANK_TIMER_FUNCS \ -+ .enable_vblank = drm_crtc_vblank_helper_enable_vblank_timer, \ -+ .disable_vblank = drm_crtc_vblank_helper_disable_vblank_timer, \ -+ .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp_from_timer -+ -+#endif --- -2.53.0 - diff --git a/SPECS/linux-lts/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch b/SPECS/linux-lts/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch new file mode 100644 index 0000000000..d6a9555b97 --- /dev/null +++ b/SPECS/linux-lts/0067-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch @@ -0,0 +1,200 @@ +From 82e88d4cfa7af6b1ae6ffc952a7d1903d2c8e3ea Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 29 Jan 2026 09:56:06 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI/MSI: Convert the boolean no_64bit_msi flag + to a DMA address mask + +Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but +implement less than 64 address bits. This breaks on platforms where such +a device is assigned an MSI address higher than what's supported. + +Currently, no_64bit_msi bit is set for these devices, meaning that only +32-bit MSI addresses are allowed for them. However, on some platforms the +MSI doorbell address is above the 32-bit limit but within the addressable +range of the device. + +As a first step to enable MSI on those combinations of devices and +platforms, convert the boolean no_64bit_msi flag to a DMA mask and fixup +the affected usage sites: + + - no_64bit_msi = 1 -> msi_addr_mask = DMA_BIT_MASK(32) + - no_64bit_msi = 0 -> msi_addr_mask = DMA_BIT_MASK(64) + - if (no_64bit_msi) -> if (msi_addr_mask < DMA_BIT_MASK(64)) + +Since no values other than DMA_BIT_MASK(32) and DMA_BIT_MASK(64) are used, +this is functionally equivalent. + +This prepares for changing the binary decision between 32 and 64 bit to a +DMA mask based decision which allows to support systems which have a DMA +address space less than 64bit but a MSI doorbell address above the 32-bit +limit. + +[ tglx: Massaged changelog ] + +Signed-off-by: Vivian Wang +Signed-off-by: Thomas Gleixner +Reviewed-by: Brett Creeley # ionic +Reviewed-by: Thomas Gleixner +Acked-by: Takashi Iwai # sound +Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-1-70da998f2750@iscas.ac.cn +(cherry picked from commit 386ced19e9a348e8131d20f009e692fa8fcc4568) +Signed-off-by: Han Gao +--- + arch/powerpc/platforms/powernv/pci-ioda.c | 2 +- + arch/powerpc/platforms/pseries/msi.c | 4 ++-- + drivers/gpu/drm/radeon/radeon_irq_kms.c | 2 +- + drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 2 +- + drivers/pci/msi/msi.c | 2 +- + drivers/pci/msi/pcidev_msi.c | 2 +- + drivers/pci/probe.c | 7 +++++++ + include/linux/pci.h | 8 +++++++- + sound/hda/controllers/intel.c | 2 +- + 9 files changed, 22 insertions(+), 9 deletions(-) + +diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c +index b0c1d9d16fb5..1c78fdfb7b03 100644 +--- a/arch/powerpc/platforms/powernv/pci-ioda.c ++++ b/arch/powerpc/platforms/powernv/pci-ioda.c +@@ -1666,7 +1666,7 @@ static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, + return -ENXIO; + + /* Force 32-bit MSI on some broken devices */ +- if (dev->no_64bit_msi) ++ if (dev->msi_addr_mask < DMA_BIT_MASK(64)) + is_64 = 0; + + /* Assign XIVE to PE */ +diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c +index 56f17296545a..67bc001688c6 100644 +--- a/arch/powerpc/platforms/pseries/msi.c ++++ b/arch/powerpc/platforms/pseries/msi.c +@@ -388,7 +388,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type, + */ + again: + if (type == PCI_CAP_ID_MSI) { +- if (pdev->no_64bit_msi) { ++ if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) { + rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec); + if (rc < 0) { + /* +@@ -414,7 +414,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type, + if (use_32bit_msi_hack && rc > 0) + rtas_hack_32bit_msi_gen2(pdev); + } else { +- if (pdev->no_64bit_msi) ++ if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) + rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSIX_FN, nvec); + else + rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec); +diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c +index 9961251b44ba..d550554a6f3f 100644 +--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c ++++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c +@@ -252,7 +252,7 @@ static bool radeon_msi_ok(struct radeon_device *rdev) + */ + if (rdev->family < CHIP_BONAIRE) { + dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n"); +- rdev->pdev->no_64bit_msi = 1; ++ rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32); + } + + /* force MSI on */ +diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c +index 70d86c5f52fb..0671deae9a28 100644 +--- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c ++++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c +@@ -331,7 +331,7 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + + #ifdef CONFIG_PPC64 + /* Ensure MSI/MSI-X interrupts lie within addressable physical memory */ +- pdev->no_64bit_msi = 1; ++ pdev->msi_addr_mask = DMA_BIT_MASK(32); + #endif + + err = ionic_setup_one(ionic); +diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c +index e010ecd9f90d..fb9a42bec62e 100644 +--- a/drivers/pci/msi/msi.c ++++ b/drivers/pci/msi/msi.c +@@ -322,7 +322,7 @@ static int msi_verify_entries(struct pci_dev *dev) + { + struct msi_desc *entry; + +- if (!dev->no_64bit_msi) ++ if (dev->msi_addr_mask == DMA_BIT_MASK(64)) + return 0; + + msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) { +diff --git a/drivers/pci/msi/pcidev_msi.c b/drivers/pci/msi/pcidev_msi.c +index 5520aff53b56..0b0346813092 100644 +--- a/drivers/pci/msi/pcidev_msi.c ++++ b/drivers/pci/msi/pcidev_msi.c +@@ -24,7 +24,7 @@ void pci_msi_init(struct pci_dev *dev) + } + + if (!(ctrl & PCI_MSI_FLAGS_64BIT)) +- dev->no_64bit_msi = 1; ++ dev->msi_addr_mask = DMA_BIT_MASK(32); + } + + void pci_msix_init(struct pci_dev *dev) +diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c +index 4e4e38e62691..0a3b0df92fc2 100644 +--- a/drivers/pci/probe.c ++++ b/drivers/pci/probe.c +@@ -2026,6 +2026,13 @@ int pci_setup_device(struct pci_dev *dev) + */ + dev->dma_mask = 0xffffffff; + ++ /* ++ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit ++ * if MSI (rather than MSI-X) capability does not have ++ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. ++ */ ++ dev->msi_addr_mask = DMA_BIT_MASK(64); ++ + dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), + dev->bus->number, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn)); +diff --git a/include/linux/pci.h b/include/linux/pci.h +index 89f5a4290b6e..3ea77b9c5901 100644 +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -377,6 +377,13 @@ struct pci_dev { + 0xffffffff. You only need to change + this if your device has broken DMA + or supports 64-bit transfers. */ ++ u64 msi_addr_mask; /* Mask of the bits of bus address for ++ MSI that this device implements. ++ Normally set based on device ++ capabilities. You only need to ++ change this if your device claims ++ to support 64-bit MSI but implements ++ fewer than 64 address bits. */ + + struct device_dma_parameters dma_parms; + +@@ -442,7 +449,6 @@ struct pci_dev { + + unsigned int is_busmaster:1; /* Is busmaster */ + unsigned int no_msi:1; /* May not use MSI */ +- unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ + unsigned int block_cfg_access:1; /* Config space access blocked */ + unsigned int broken_parity_status:1; /* Generates false positive parity */ + unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ +diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c +index 98367b87d801..44781b87d58e 100644 +--- a/sound/hda/controllers/intel.c ++++ b/sound/hda/controllers/intel.c +@@ -1907,7 +1907,7 @@ static int azx_first_init(struct azx *chip) + + if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { + dev_dbg(card->dev, "Disabling 64bit MSI\n"); +- pci->no_64bit_msi = true; ++ pci->msi_addr_mask = DMA_BIT_MASK(32); + } + + pci_set_master(pci); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0067-UPSTREAM-drm-vblank-Add-CRTC-helpers-for-simple-use-.patch b/SPECS/linux-lts/0067-UPSTREAM-drm-vblank-Add-CRTC-helpers-for-simple-use-.patch deleted file mode 100644 index 7253e51186..0000000000 --- a/SPECS/linux-lts/0067-UPSTREAM-drm-vblank-Add-CRTC-helpers-for-simple-use-.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 583cfbbf548a142881ed47ae9a5e1ab10a4ddbb6 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Tue, 16 Sep 2025 10:36:20 +0200 -Subject: [PATCH 067/467] UPSTREAM: drm/vblank: Add CRTC helpers for simple use - cases - -Implement atomic_flush, atomic_enable and atomic_disable of struct -drm_crtc_helper_funcs for vblank handling. Driver with no further -requirements can use these functions instead of adding their own. -Also simplifies the use of vblank timers. - -The code has been adopted from vkms, which added the funtionality -in commit 3a0709928b17 ("drm/vkms: Add vblank events simulated by -hrtimers"). - -v3: -- mention vkms (Javier) -v2: -- fix docs - -Signed-off-by: Thomas Zimmermann -Reviewed-by: Javier Martinez Canillas -Tested-by: Michael Kelley -Link: https://lore.kernel.org/r/20250916083816.30275-3-tzimmermann@suse.de -(cherry picked from commit d54dbb5963bdbdf8559903fe2b2343e871adcb30) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/drm_vblank_helper.c | 80 +++++++++++++++++++++++++++++ - include/drm/drm_vblank_helper.h | 23 +++++++++ - 2 files changed, 103 insertions(+) - -diff --git a/drivers/gpu/drm/drm_vblank_helper.c b/drivers/gpu/drm/drm_vblank_helper.c -index f94d1e706191..a04a6ba1b0ca 100644 ---- a/drivers/gpu/drm/drm_vblank_helper.c -+++ b/drivers/gpu/drm/drm_vblank_helper.c -@@ -1,5 +1,6 @@ - // SPDX-License-Identifier: MIT - -+#include - #include - #include - #include -@@ -17,6 +18,12 @@ - * Drivers enable support for vblank timers by setting the vblank callbacks - * in struct &drm_crtc_funcs to the helpers provided by this library. The - * initializer macro DRM_CRTC_VBLANK_TIMER_FUNCS does this conveniently. -+ * The driver further has to send the VBLANK event from its atomic_flush -+ * callback and control vblank from the CRTC's atomic_enable and atomic_disable -+ * callbacks. The callbacks are located in struct &drm_crtc_helper_funcs. -+ * The vblank helper library provides implementations of these callbacks -+ * for drivers without further requirements. The initializer macro -+ * DRM_CRTC_HELPER_VBLANK_FUNCS sets them coveniently. - * - * Once the driver enables vblank support with drm_vblank_init(), each - * CRTC's vblank timer fires according to the programmed display mode. By -@@ -25,6 +32,79 @@ - * struct &drm_crtc_helper_funcs.handle_vblank_timeout. - */ - -+/* -+ * VBLANK helpers -+ */ -+ -+/** -+ * drm_crtc_vblank_atomic_flush - -+ * Implements struct &drm_crtc_helper_funcs.atomic_flush -+ * @crtc: The CRTC -+ * @state: The atomic state to apply -+ * -+ * The helper drm_crtc_vblank_atomic_flush() implements atomic_flush of -+ * struct drm_crtc_helper_funcs for CRTCs that only need to send out a -+ * VBLANK event. -+ * -+ * See also struct &drm_crtc_helper_funcs.atomic_flush. -+ */ -+void drm_crtc_vblank_atomic_flush(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct drm_device *dev = crtc->dev; -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); -+ struct drm_pending_vblank_event *event; -+ -+ spin_lock_irq(&dev->event_lock); -+ -+ event = crtc_state->event; -+ crtc_state->event = NULL; -+ -+ if (event) { -+ if (drm_crtc_vblank_get(crtc) == 0) -+ drm_crtc_arm_vblank_event(crtc, event); -+ else -+ drm_crtc_send_vblank_event(crtc, event); -+ } -+ -+ spin_unlock_irq(&dev->event_lock); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_atomic_flush); -+ -+/** -+ * drm_crtc_vblank_atomic_enable - Implements struct &drm_crtc_helper_funcs.atomic_enable -+ * @crtc: The CRTC -+ * @state: The atomic state -+ * -+ * The helper drm_crtc_vblank_atomic_enable() implements atomic_enable -+ * of struct drm_crtc_helper_funcs for CRTCs the only need to enable VBLANKs. -+ * -+ * See also struct &drm_crtc_helper_funcs.atomic_enable. -+ */ -+void drm_crtc_vblank_atomic_enable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ drm_crtc_vblank_on(crtc); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_atomic_enable); -+ -+/** -+ * drm_crtc_vblank_atomic_disable - Implements struct &drm_crtc_helper_funcs.atomic_disable -+ * @crtc: The CRTC -+ * @state: The atomic state -+ * -+ * The helper drm_crtc_vblank_atomic_disable() implements atomic_disable -+ * of struct drm_crtc_helper_funcs for CRTCs the only need to disable VBLANKs. -+ * -+ * See also struct &drm_crtc_funcs.atomic_disable. -+ */ -+void drm_crtc_vblank_atomic_disable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ drm_crtc_vblank_off(crtc); -+} -+EXPORT_SYMBOL(drm_crtc_vblank_atomic_disable); -+ - /* - * VBLANK timer - */ -diff --git a/include/drm/drm_vblank_helper.h b/include/drm/drm_vblank_helper.h -index 74a971d0cfba..fcd8a9b35846 100644 ---- a/include/drm/drm_vblank_helper.h -+++ b/include/drm/drm_vblank_helper.h -@@ -6,8 +6,31 @@ - #include - #include - -+struct drm_atomic_state; - struct drm_crtc; - -+/* -+ * VBLANK helpers -+ */ -+ -+void drm_crtc_vblank_atomic_flush(struct drm_crtc *crtc, -+ struct drm_atomic_state *state); -+void drm_crtc_vblank_atomic_enable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state); -+void drm_crtc_vblank_atomic_disable(struct drm_crtc *crtc, -+ struct drm_atomic_state *crtc_state); -+ -+/** -+ * DRM_CRTC_HELPER_VBLANK_FUNCS - Default implementation for VBLANK helpers -+ * -+ * This macro initializes struct &drm_crtc_helper_funcs to default helpers -+ * for VBLANK handling. -+ */ -+#define DRM_CRTC_HELPER_VBLANK_FUNCS \ -+ .atomic_flush = drm_crtc_vblank_atomic_flush, \ -+ .atomic_enable = drm_crtc_vblank_atomic_enable, \ -+ .atomic_disable = drm_crtc_vblank_atomic_disable -+ - /* - * VBLANK timer - */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch b/SPECS/linux-lts/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch new file mode 100644 index 0000000000..46bc6278e3 --- /dev/null +++ b/SPECS/linux-lts/0068-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch @@ -0,0 +1,52 @@ +From 4f4b809bc01cd7d00cf117b7e99a2a2b18a9d9f9 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 29 Jan 2026 09:56:07 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI/MSI: Check the device specific address + mask in msi_verify_entries() + +Instead of a 32-bit/64-bit dichotomy, check the MSI address against +the device specific address mask. + +This allows platforms with an MSI doorbell address above the 32-bit limit +to work with devices without full 64-bit MSI address support, as long as +the doorbell is within the addressable range of the device. + +[ tglx: Massaged changelog ] + +Signed-off-by: Vivian Wang +Signed-off-by: Thomas Gleixner +Reviewed-by: Thomas Gleixner +Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-2-70da998f2750@iscas.ac.cn +(cherry picked from commit 52f0d862f595a2fa18ef44532619a080c24fe4cb) +Signed-off-by: Han Gao +--- + drivers/pci/msi/msi.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c +index fb9a42bec62e..e2412175d7af 100644 +--- a/drivers/pci/msi/msi.c ++++ b/drivers/pci/msi/msi.c +@@ -321,14 +321,16 @@ static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, + static int msi_verify_entries(struct pci_dev *dev) + { + struct msi_desc *entry; ++ u64 address; + + if (dev->msi_addr_mask == DMA_BIT_MASK(64)) + return 0; + + msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) { +- if (entry->msg.address_hi) { +- pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n", +- entry->msg.address_hi, entry->msg.address_lo); ++ address = (u64)entry->msg.address_hi << 32 | entry->msg.address_lo; ++ if (address & ~dev->msi_addr_mask) { ++ pci_err(dev, "arch assigned 64-bit MSI address %#llx above device MSI address mask %#llx\n", ++ address, dev->msi_addr_mask); + break; + } + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0068-UPSTREAM-drm-vkms-Convert-to-DRM-s-vblank-timer.patch b/SPECS/linux-lts/0068-UPSTREAM-drm-vkms-Convert-to-DRM-s-vblank-timer.patch deleted file mode 100644 index 6dbce8b177..0000000000 --- a/SPECS/linux-lts/0068-UPSTREAM-drm-vkms-Convert-to-DRM-s-vblank-timer.patch +++ /dev/null @@ -1,172 +0,0 @@ -From 5c2dba8da42db8a451df4751fdd00dea997959e4 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Tue, 16 Sep 2025 10:36:21 +0200 -Subject: [PATCH 068/467] UPSTREAM: drm/vkms: Convert to DRM's vblank timer - -Replace vkms' vblank timer with the DRM implementation. The DRM -code is identical in concept, but differs in implementation. - -Vblank timers are covered in vblank helpers and initializer macros, -so remove the corresponding hrtimer in struct vkms_output. The -vblank timer calls vkms' custom timeout code via handle_vblank_timeout -in struct drm_crtc_helper_funcs. - -Signed-off-by: Thomas Zimmermann -Tested-by: Louis Chauvet -Reviewed-by: Louis Chauvet -Reviewed-by: Javier Martinez Canillas -Link: https://lore.kernel.org/r/20250916083816.30275-4-tzimmermann@suse.de -(cherry picked from commit 02e2681ffe1addde1fc8c35d05657b16bfa79613) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/vkms/vkms_crtc.c | 83 +++----------------------------- - drivers/gpu/drm/vkms/vkms_drv.h | 2 - - 2 files changed, 7 insertions(+), 78 deletions(-) - -diff --git a/drivers/gpu/drm/vkms/vkms_crtc.c b/drivers/gpu/drm/vkms/vkms_crtc.c -index e60573e0f3e9..bd79f24686dc 100644 ---- a/drivers/gpu/drm/vkms/vkms_crtc.c -+++ b/drivers/gpu/drm/vkms/vkms_crtc.c -@@ -7,25 +7,18 @@ - #include - #include - #include -+#include - - #include "vkms_drv.h" - --static enum hrtimer_restart vkms_vblank_simulate(struct hrtimer *timer) -+static bool vkms_crtc_handle_vblank_timeout(struct drm_crtc *crtc) - { -- struct vkms_output *output = container_of(timer, struct vkms_output, -- vblank_hrtimer); -- struct drm_crtc *crtc = &output->crtc; -+ struct vkms_output *output = drm_crtc_to_vkms_output(crtc); - struct vkms_crtc_state *state; -- u64 ret_overrun; - bool ret, fence_cookie; - - fence_cookie = dma_fence_begin_signalling(); - -- ret_overrun = hrtimer_forward_now(&output->vblank_hrtimer, -- output->period_ns); -- if (ret_overrun != 1) -- pr_warn("%s: vblank timer overrun\n", __func__); -- - spin_lock(&output->lock); - ret = drm_crtc_handle_vblank(crtc); - if (!ret) -@@ -57,55 +50,6 @@ static enum hrtimer_restart vkms_vblank_simulate(struct hrtimer *timer) - - dma_fence_end_signalling(fence_cookie); - -- return HRTIMER_RESTART; --} -- --static int vkms_enable_vblank(struct drm_crtc *crtc) --{ -- struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); -- struct vkms_output *out = drm_crtc_to_vkms_output(crtc); -- -- hrtimer_setup(&out->vblank_hrtimer, &vkms_vblank_simulate, CLOCK_MONOTONIC, -- HRTIMER_MODE_REL); -- out->period_ns = ktime_set(0, vblank->framedur_ns); -- hrtimer_start(&out->vblank_hrtimer, out->period_ns, HRTIMER_MODE_REL); -- -- return 0; --} -- --static void vkms_disable_vblank(struct drm_crtc *crtc) --{ -- struct vkms_output *out = drm_crtc_to_vkms_output(crtc); -- -- hrtimer_cancel(&out->vblank_hrtimer); --} -- --static bool vkms_get_vblank_timestamp(struct drm_crtc *crtc, -- int *max_error, ktime_t *vblank_time, -- bool in_vblank_irq) --{ -- struct vkms_output *output = drm_crtc_to_vkms_output(crtc); -- struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); -- -- if (!READ_ONCE(vblank->enabled)) { -- *vblank_time = ktime_get(); -- return true; -- } -- -- *vblank_time = READ_ONCE(output->vblank_hrtimer.node.expires); -- -- if (WARN_ON(*vblank_time == vblank->time)) -- return true; -- -- /* -- * To prevent races we roll the hrtimer forward before we do any -- * interrupt processing - this is how real hw works (the interrupt is -- * only generated after all the vblank registers are updated) and what -- * the vblank core expects. Therefore we need to always correct the -- * timestampe by one frame. -- */ -- *vblank_time -= output->period_ns; -- - return true; - } - -@@ -159,9 +103,7 @@ static const struct drm_crtc_funcs vkms_crtc_funcs = { - .reset = vkms_atomic_crtc_reset, - .atomic_duplicate_state = vkms_atomic_crtc_duplicate_state, - .atomic_destroy_state = vkms_atomic_crtc_destroy_state, -- .enable_vblank = vkms_enable_vblank, -- .disable_vblank = vkms_disable_vblank, -- .get_vblank_timestamp = vkms_get_vblank_timestamp, -+ DRM_CRTC_VBLANK_TIMER_FUNCS, - .get_crc_sources = vkms_get_crc_sources, - .set_crc_source = vkms_set_crc_source, - .verify_crc_source = vkms_verify_crc_source, -@@ -213,18 +155,6 @@ static int vkms_crtc_atomic_check(struct drm_crtc *crtc, - return 0; - } - --static void vkms_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_atomic_state *state) --{ -- drm_crtc_vblank_on(crtc); --} -- --static void vkms_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_atomic_state *state) --{ -- drm_crtc_vblank_off(crtc); --} -- - static void vkms_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_atomic_state *state) - __acquires(&vkms_output->lock) -@@ -265,8 +195,9 @@ static const struct drm_crtc_helper_funcs vkms_crtc_helper_funcs = { - .atomic_check = vkms_crtc_atomic_check, - .atomic_begin = vkms_crtc_atomic_begin, - .atomic_flush = vkms_crtc_atomic_flush, -- .atomic_enable = vkms_crtc_atomic_enable, -- .atomic_disable = vkms_crtc_atomic_disable, -+ .atomic_enable = drm_crtc_vblank_atomic_enable, -+ .atomic_disable = drm_crtc_vblank_atomic_disable, -+ .handle_vblank_timeout = vkms_crtc_handle_vblank_timeout, - }; - - struct vkms_output *vkms_crtc_init(struct drm_device *dev, struct drm_plane *primary, -diff --git a/drivers/gpu/drm/vkms/vkms_drv.h b/drivers/gpu/drm/vkms/vkms_drv.h -index 8013c31efe3b..fb9711e1c6fb 100644 ---- a/drivers/gpu/drm/vkms/vkms_drv.h -+++ b/drivers/gpu/drm/vkms/vkms_drv.h -@@ -215,8 +215,6 @@ struct vkms_output { - struct drm_crtc crtc; - struct drm_writeback_connector wb_connector; - struct drm_encoder wb_encoder; -- struct hrtimer vblank_hrtimer; -- ktime_t period_ns; - struct workqueue_struct *composer_workq; - spinlock_t lock; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0069-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch b/SPECS/linux-lts/0069-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch deleted file mode 100644 index 0ad15ed0ef..0000000000 --- a/SPECS/linux-lts/0069-UPSTREAM-drm-hypervdrm-Use-vblank-timer.patch +++ /dev/null @@ -1,72 +0,0 @@ -From e0e2839348f82a4bba9e9a4c7f122ed62ae7b0e1 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Tue, 16 Sep 2025 10:36:22 +0200 -Subject: [PATCH 069/467] UPSTREAM: drm/hypervdrm: Use vblank timer - -HyperV's virtual hardware does not provide vblank interrupts. Use a -vblank timer to simulate the interrupt. Rate-limits the display's -update frequency to the display-mode settings. Avoids excessive CPU -overhead with compositors that do not rate-limit their output. - -Signed-off-by: Thomas Zimmermann -Reviewed-by: Javier Martinez Canillas -Tested-by: Michael Kelley -Tested-by: Prasanna Kumar T S M -Link: https://lore.kernel.org/r/20250916083816.30275-5-tzimmermann@suse.de -(cherry picked from commit 52e6b198833411564e0b9ce6e96bbd3d72f961e7) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/hyperv/hyperv_drm_modeset.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c -index 945b9482bcb3..6e6eb1c12a68 100644 ---- a/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c -+++ b/drivers/gpu/drm/hyperv/hyperv_drm_modeset.c -@@ -19,6 +19,8 @@ - #include - #include - #include -+#include -+#include - - #include "hyperv_drm.h" - -@@ -111,11 +113,15 @@ static void hyperv_crtc_helper_atomic_enable(struct drm_crtc *crtc, - crtc_state->mode.hdisplay, - crtc_state->mode.vdisplay, - plane_state->fb->pitches[0]); -+ -+ drm_crtc_vblank_on(crtc); - } - - static const struct drm_crtc_helper_funcs hyperv_crtc_helper_funcs = { - .atomic_check = drm_crtc_helper_atomic_check, -+ .atomic_flush = drm_crtc_vblank_atomic_flush, - .atomic_enable = hyperv_crtc_helper_atomic_enable, -+ .atomic_disable = drm_crtc_vblank_atomic_disable, - }; - - static const struct drm_crtc_funcs hyperv_crtc_funcs = { -@@ -125,6 +131,7 @@ static const struct drm_crtc_funcs hyperv_crtc_funcs = { - .page_flip = drm_atomic_helper_page_flip, - .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, -+ DRM_CRTC_VBLANK_TIMER_FUNCS, - }; - - static int hyperv_plane_atomic_check(struct drm_plane *plane, -@@ -321,6 +328,10 @@ int hyperv_mode_config_init(struct hyperv_drm_device *hv) - return ret; - } - -+ ret = drm_vblank_init(dev, 1); -+ if (ret) -+ return ret; -+ - drm_mode_config_reset(dev); - - return 0; --- -2.53.0 - diff --git a/SPECS/linux-lts/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch b/SPECS/linux-lts/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch new file mode 100644 index 0000000000..02e46aef2a --- /dev/null +++ b/SPECS/linux-lts/0069-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch @@ -0,0 +1,74 @@ +From 9dcbec59b17ddb9befc7e35efebe9f69ebeb2745 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 29 Jan 2026 09:56:08 +0800 +Subject: [RUYI PATCH] UPSTREAM: drm/radeon: Make MSI address limit based on + the device DMA limit +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The radeon driver restricts the MSI message address for devices older than +the BONAIR generation to 32-bit MSI addresses due to the former +restrictions of the PCI/MSI code which only allowed either 32-bit or full +64-bit address range. + +This does not work on platforms which have a MSI doorbell address above the +32-bit boundary but do not support the full 64 bit address range. + +The PCI/MSI core converted this binary decision to a DMA_BIT_MASK() based +decision, which allows to describe the device limitations precisely. + +Convert the driver to provide the exact DMA address limitations to the +PCI/MSI core. That allows devices which do not support the full 64-bit +address space to work on platforms which have a MSI doorbell address above +the 32-bit limit as long as it is within the hardware's addressable range. + +[ tglx: Massage changelog ] + +Signed-off-by: Vivian Wang +Signed-off-by: Thomas Gleixner +Reviewed-by: Christian König +Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-3-70da998f2750@iscas.ac.cn +(cherry picked from commit 617562bbe12df796fc21df5fbf262eadf083a90f) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/radeon/radeon_device.c | 1 + + drivers/gpu/drm/radeon/radeon_irq_kms.c | 10 ---------- + 2 files changed, 1 insertion(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c +index 9e35b14e2bf0..92a3e3ee673c 100644 +--- a/drivers/gpu/drm/radeon/radeon_device.c ++++ b/drivers/gpu/drm/radeon/radeon_device.c +@@ -1374,6 +1374,7 @@ int radeon_device_init(struct radeon_device *rdev, + pr_warn("radeon: No suitable DMA available\n"); + return r; + } ++ rdev->pdev->msi_addr_mask = DMA_BIT_MASK(dma_bits); + rdev->need_swiotlb = drm_need_swiotlb(dma_bits); + + /* Registers mapping */ +diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c +index d550554a6f3f..839d619e5602 100644 +--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c ++++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c +@@ -245,16 +245,6 @@ static bool radeon_msi_ok(struct radeon_device *rdev) + if (rdev->flags & RADEON_IS_AGP) + return false; + +- /* +- * Older chips have a HW limitation, they can only generate 40 bits +- * of address for "64-bit" MSIs which breaks on some platforms, notably +- * IBM POWER servers, so we limit them +- */ +- if (rdev->family < CHIP_BONAIRE) { +- dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n"); +- rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32); +- } +- + /* force MSI on */ + if (radeon_msi == 1) + return true; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch b/SPECS/linux-lts/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch new file mode 100644 index 0000000000..5f8bf385cf --- /dev/null +++ b/SPECS/linux-lts/0070-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch @@ -0,0 +1,65 @@ +From ed396d380559185d5e0dfad4f40fc5cd8c0382d1 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 29 Jan 2026 09:56:09 +0800 +Subject: [RUYI PATCH] UPSTREAM: ALSA: hda/intel: Make MSI address limit based + on the device DMA limit + +The hda/intel driver restricts the MSI message address for devices which do +not advertise full 64-bit DMA address space support to 32-bit due to the +former restrictions of the PCI/MSI code which only allowed either 32-bit or +a full 64-bit address range. + +This does not work on platforms which have a MSI doorbell address above the +32-bit boundary but do not support the full 64 bit address range. + +The PCI/MSI core converted this binary decision to a DMA_BIT_MASK() based +decision, which allows to describe the device limitations precisely. + +Convert the driver to provide the exact DMA address limitations to the +PCI/MSI core. That allows devices which do not support the full 64-bit +address space to work on platforms which have a MSI doorbell address above +the 32-bit limit as long as it is within the hardware's addressable range. + +[ tglx: Massage changelog ] + +Signed-off-by: Vivian Wang +Signed-off-by: Thomas Gleixner +Acked-by: Takashi Iwai +Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-4-70da998f2750@iscas.ac.cn +(cherry picked from commit cb9b6f9d2be6bda1b0117b147df40f982ce06888) +Signed-off-by: Han Gao +--- + sound/hda/controllers/intel.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c +index 44781b87d58e..6f89875e7c3c 100644 +--- a/sound/hda/controllers/intel.c ++++ b/sound/hda/controllers/intel.c +@@ -1905,11 +1905,6 @@ static int azx_first_init(struct azx *chip) + chip->gts_present = true; + #endif + +- if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { +- dev_dbg(card->dev, "Disabling 64bit MSI\n"); +- pci->msi_addr_mask = DMA_BIT_MASK(32); +- } +- + pci_set_master(pci); + + gcap = azx_readw(chip, GCAP); +@@ -1960,6 +1955,11 @@ static int azx_first_init(struct azx *chip) + dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); + dma_set_max_seg_size(&pci->dev, UINT_MAX); + ++ if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { ++ dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits); ++ pci->msi_addr_mask = DMA_BIT_MASK(dma_bits); ++ } ++ + /* read number of streams from GCAP register instead of using + * hardcoded value + */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0070-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch b/SPECS/linux-lts/0070-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch deleted file mode 100644 index 443c2abc64..0000000000 --- a/SPECS/linux-lts/0070-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch +++ /dev/null @@ -1,200 +0,0 @@ -From be105cf6e6a53eea68ee3af9b6c42db92be45a34 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 29 Jan 2026 09:56:06 +0800 -Subject: [PATCH 070/467] UPSTREAM: PCI/MSI: Convert the boolean no_64bit_msi - flag to a DMA address mask - -Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but -implement less than 64 address bits. This breaks on platforms where such -a device is assigned an MSI address higher than what's supported. - -Currently, no_64bit_msi bit is set for these devices, meaning that only -32-bit MSI addresses are allowed for them. However, on some platforms the -MSI doorbell address is above the 32-bit limit but within the addressable -range of the device. - -As a first step to enable MSI on those combinations of devices and -platforms, convert the boolean no_64bit_msi flag to a DMA mask and fixup -the affected usage sites: - - - no_64bit_msi = 1 -> msi_addr_mask = DMA_BIT_MASK(32) - - no_64bit_msi = 0 -> msi_addr_mask = DMA_BIT_MASK(64) - - if (no_64bit_msi) -> if (msi_addr_mask < DMA_BIT_MASK(64)) - -Since no values other than DMA_BIT_MASK(32) and DMA_BIT_MASK(64) are used, -this is functionally equivalent. - -This prepares for changing the binary decision between 32 and 64 bit to a -DMA mask based decision which allows to support systems which have a DMA -address space less than 64bit but a MSI doorbell address above the 32-bit -limit. - -[ tglx: Massaged changelog ] - -Signed-off-by: Vivian Wang -Signed-off-by: Thomas Gleixner -Reviewed-by: Brett Creeley # ionic -Reviewed-by: Thomas Gleixner -Acked-by: Takashi Iwai # sound -Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-1-70da998f2750@iscas.ac.cn -(cherry picked from commit 386ced19e9a348e8131d20f009e692fa8fcc4568) -Signed-off-by: Han Gao ---- - arch/powerpc/platforms/powernv/pci-ioda.c | 2 +- - arch/powerpc/platforms/pseries/msi.c | 4 ++-- - drivers/gpu/drm/radeon/radeon_irq_kms.c | 2 +- - drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 2 +- - drivers/pci/msi/msi.c | 2 +- - drivers/pci/msi/pcidev_msi.c | 2 +- - drivers/pci/probe.c | 7 +++++++ - include/linux/pci.h | 8 +++++++- - sound/hda/controllers/intel.c | 2 +- - 9 files changed, 22 insertions(+), 9 deletions(-) - -diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c -index b0c1d9d16fb5..1c78fdfb7b03 100644 ---- a/arch/powerpc/platforms/powernv/pci-ioda.c -+++ b/arch/powerpc/platforms/powernv/pci-ioda.c -@@ -1666,7 +1666,7 @@ static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, - return -ENXIO; - - /* Force 32-bit MSI on some broken devices */ -- if (dev->no_64bit_msi) -+ if (dev->msi_addr_mask < DMA_BIT_MASK(64)) - is_64 = 0; - - /* Assign XIVE to PE */ -diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c -index 56f17296545a..67bc001688c6 100644 ---- a/arch/powerpc/platforms/pseries/msi.c -+++ b/arch/powerpc/platforms/pseries/msi.c -@@ -388,7 +388,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type, - */ - again: - if (type == PCI_CAP_ID_MSI) { -- if (pdev->no_64bit_msi) { -+ if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) { - rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec); - if (rc < 0) { - /* -@@ -414,7 +414,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type, - if (use_32bit_msi_hack && rc > 0) - rtas_hack_32bit_msi_gen2(pdev); - } else { -- if (pdev->no_64bit_msi) -+ if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) - rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSIX_FN, nvec); - else - rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec); -diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c -index 9961251b44ba..d550554a6f3f 100644 ---- a/drivers/gpu/drm/radeon/radeon_irq_kms.c -+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c -@@ -252,7 +252,7 @@ static bool radeon_msi_ok(struct radeon_device *rdev) - */ - if (rdev->family < CHIP_BONAIRE) { - dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n"); -- rdev->pdev->no_64bit_msi = 1; -+ rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32); - } - - /* force MSI on */ -diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c -index 70d86c5f52fb..0671deae9a28 100644 ---- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c -+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c -@@ -331,7 +331,7 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) - - #ifdef CONFIG_PPC64 - /* Ensure MSI/MSI-X interrupts lie within addressable physical memory */ -- pdev->no_64bit_msi = 1; -+ pdev->msi_addr_mask = DMA_BIT_MASK(32); - #endif - - err = ionic_setup_one(ionic); -diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c -index e010ecd9f90d..fb9a42bec62e 100644 ---- a/drivers/pci/msi/msi.c -+++ b/drivers/pci/msi/msi.c -@@ -322,7 +322,7 @@ static int msi_verify_entries(struct pci_dev *dev) - { - struct msi_desc *entry; - -- if (!dev->no_64bit_msi) -+ if (dev->msi_addr_mask == DMA_BIT_MASK(64)) - return 0; - - msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) { -diff --git a/drivers/pci/msi/pcidev_msi.c b/drivers/pci/msi/pcidev_msi.c -index 5520aff53b56..0b0346813092 100644 ---- a/drivers/pci/msi/pcidev_msi.c -+++ b/drivers/pci/msi/pcidev_msi.c -@@ -24,7 +24,7 @@ void pci_msi_init(struct pci_dev *dev) - } - - if (!(ctrl & PCI_MSI_FLAGS_64BIT)) -- dev->no_64bit_msi = 1; -+ dev->msi_addr_mask = DMA_BIT_MASK(32); - } - - void pci_msix_init(struct pci_dev *dev) -diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c -index 4e4e38e62691..0a3b0df92fc2 100644 ---- a/drivers/pci/probe.c -+++ b/drivers/pci/probe.c -@@ -2026,6 +2026,13 @@ int pci_setup_device(struct pci_dev *dev) - */ - dev->dma_mask = 0xffffffff; - -+ /* -+ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit -+ * if MSI (rather than MSI-X) capability does not have -+ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. -+ */ -+ dev->msi_addr_mask = DMA_BIT_MASK(64); -+ - dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), - dev->bus->number, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn)); -diff --git a/include/linux/pci.h b/include/linux/pci.h -index 89f5a4290b6e..3ea77b9c5901 100644 ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -377,6 +377,13 @@ struct pci_dev { - 0xffffffff. You only need to change - this if your device has broken DMA - or supports 64-bit transfers. */ -+ u64 msi_addr_mask; /* Mask of the bits of bus address for -+ MSI that this device implements. -+ Normally set based on device -+ capabilities. You only need to -+ change this if your device claims -+ to support 64-bit MSI but implements -+ fewer than 64 address bits. */ - - struct device_dma_parameters dma_parms; - -@@ -442,7 +449,6 @@ struct pci_dev { - - unsigned int is_busmaster:1; /* Is busmaster */ - unsigned int no_msi:1; /* May not use MSI */ -- unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */ - unsigned int block_cfg_access:1; /* Config space access blocked */ - unsigned int broken_parity_status:1; /* Generates false positive parity */ - unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ -diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c -index 98367b87d801..44781b87d58e 100644 ---- a/sound/hda/controllers/intel.c -+++ b/sound/hda/controllers/intel.c -@@ -1907,7 +1907,7 @@ static int azx_first_init(struct azx *chip) - - if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { - dev_dbg(card->dev, "Disabling 64bit MSI\n"); -- pci->no_64bit_msi = true; -+ pci->msi_addr_mask = DMA_BIT_MASK(32); - } - - pci_set_master(pci); --- -2.53.0 - diff --git a/SPECS/linux-lts/0071-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch b/SPECS/linux-lts/0071-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch deleted file mode 100644 index c99a180597..0000000000 --- a/SPECS/linux-lts/0071-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 76e89b16cb73690ff25af12682731fc117be5c3e Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 29 Jan 2026 09:56:07 +0800 -Subject: [PATCH 071/467] UPSTREAM: PCI/MSI: Check the device specific address - mask in msi_verify_entries() - -Instead of a 32-bit/64-bit dichotomy, check the MSI address against -the device specific address mask. - -This allows platforms with an MSI doorbell address above the 32-bit limit -to work with devices without full 64-bit MSI address support, as long as -the doorbell is within the addressable range of the device. - -[ tglx: Massaged changelog ] - -Signed-off-by: Vivian Wang -Signed-off-by: Thomas Gleixner -Reviewed-by: Thomas Gleixner -Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-2-70da998f2750@iscas.ac.cn -(cherry picked from commit 52f0d862f595a2fa18ef44532619a080c24fe4cb) -Signed-off-by: Han Gao ---- - drivers/pci/msi/msi.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - -diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c -index fb9a42bec62e..e2412175d7af 100644 ---- a/drivers/pci/msi/msi.c -+++ b/drivers/pci/msi/msi.c -@@ -321,14 +321,16 @@ static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, - static int msi_verify_entries(struct pci_dev *dev) - { - struct msi_desc *entry; -+ u64 address; - - if (dev->msi_addr_mask == DMA_BIT_MASK(64)) - return 0; - - msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) { -- if (entry->msg.address_hi) { -- pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n", -- entry->msg.address_hi, entry->msg.address_lo); -+ address = (u64)entry->msg.address_hi << 32 | entry->msg.address_lo; -+ if (address & ~dev->msi_addr_mask) { -+ pci_err(dev, "arch assigned 64-bit MSI address %#llx above device MSI address mask %#llx\n", -+ address, dev->msi_addr_mask); - break; - } - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch b/SPECS/linux-lts/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch new file mode 100644 index 0000000000..9eb8c66514 --- /dev/null +++ b/SPECS/linux-lts/0071-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch @@ -0,0 +1,64 @@ +From f4bd9635e84e4d37d8e56a08bbd43581faeddc96 Mon Sep 17 00:00:00 2001 +From: Michael Orlitzky +Date: Wed, 7 Jan 2026 06:29:22 -0500 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: enable hardware clock + (RTC) on the Milk-V Pioneer + +These boards have a working hardware clock if you put a CR-1220 +battery in them. We enable it using information from a 6.1.x vendor +kernel. + +Reviewed-by: Chen Wang +Signed-off-by: Michael Orlitzky +Link: https://lore.kernel.org/r/20260107112922.20013-2-michael@orlitzky.com +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +Signed-off-by: Chen Wang +(cherry picked from commit 9e81c522680db5998c872fb91ff7877cf3d8ff42) +Signed-off-by: Han Gao +--- + .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 21 +++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +index 54d8386bf9c0..ecf8c1e29079 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts ++++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +@@ -52,6 +52,17 @@ &emmc { + status = "okay"; + }; + ++&i2c0 { ++ pinctrl-0 = <&i2c0_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ rtc: rtc@68 { ++ compatible = "dallas,ds1307"; ++ reg = <0x68>; ++ }; ++}; ++ + &i2c1 { + pinctrl-0 = <&i2c1_cfg>; + pinctrl-names = "default"; +@@ -89,6 +100,16 @@ sdhci-emmc-rst-pwr-pins { + }; + }; + ++ i2c0_cfg: i2c0-cfg { ++ i2c0-pins { ++ pinmux = , ++ ; ++ bias-pull-up; ++ drive-strength-microamp = <26800>; ++ input-schmitt-enable; ++ }; ++ }; ++ + i2c1_cfg: i2c1-cfg { + i2c1-pins { + pinmux = , +-- +2.53.0 + diff --git a/SPECS/linux-lts/0072-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch b/SPECS/linux-lts/0072-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch deleted file mode 100644 index 3eaeffad7c..0000000000 --- a/SPECS/linux-lts/0072-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch +++ /dev/null @@ -1,74 +0,0 @@ -From ad4fb64413f53de6281889e26345c8138c8057f0 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 29 Jan 2026 09:56:08 +0800 -Subject: [PATCH 072/467] UPSTREAM: drm/radeon: Make MSI address limit based on - the device DMA limit -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The radeon driver restricts the MSI message address for devices older than -the BONAIR generation to 32-bit MSI addresses due to the former -restrictions of the PCI/MSI code which only allowed either 32-bit or full -64-bit address range. - -This does not work on platforms which have a MSI doorbell address above the -32-bit boundary but do not support the full 64 bit address range. - -The PCI/MSI core converted this binary decision to a DMA_BIT_MASK() based -decision, which allows to describe the device limitations precisely. - -Convert the driver to provide the exact DMA address limitations to the -PCI/MSI core. That allows devices which do not support the full 64-bit -address space to work on platforms which have a MSI doorbell address above -the 32-bit limit as long as it is within the hardware's addressable range. - -[ tglx: Massage changelog ] - -Signed-off-by: Vivian Wang -Signed-off-by: Thomas Gleixner -Reviewed-by: Christian König -Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-3-70da998f2750@iscas.ac.cn -(cherry picked from commit 617562bbe12df796fc21df5fbf262eadf083a90f) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/radeon/radeon_device.c | 1 + - drivers/gpu/drm/radeon/radeon_irq_kms.c | 10 ---------- - 2 files changed, 1 insertion(+), 10 deletions(-) - -diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c -index 9e35b14e2bf0..92a3e3ee673c 100644 ---- a/drivers/gpu/drm/radeon/radeon_device.c -+++ b/drivers/gpu/drm/radeon/radeon_device.c -@@ -1374,6 +1374,7 @@ int radeon_device_init(struct radeon_device *rdev, - pr_warn("radeon: No suitable DMA available\n"); - return r; - } -+ rdev->pdev->msi_addr_mask = DMA_BIT_MASK(dma_bits); - rdev->need_swiotlb = drm_need_swiotlb(dma_bits); - - /* Registers mapping */ -diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c -index d550554a6f3f..839d619e5602 100644 ---- a/drivers/gpu/drm/radeon/radeon_irq_kms.c -+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c -@@ -245,16 +245,6 @@ static bool radeon_msi_ok(struct radeon_device *rdev) - if (rdev->flags & RADEON_IS_AGP) - return false; - -- /* -- * Older chips have a HW limitation, they can only generate 40 bits -- * of address for "64-bit" MSIs which breaks on some platforms, notably -- * IBM POWER servers, so we limit them -- */ -- if (rdev->family < CHIP_BONAIRE) { -- dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n"); -- rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32); -- } -- - /* force MSI on */ - if (radeon_msi == 1) - return true; --- -2.53.0 - diff --git a/SPECS/linux-lts/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch b/SPECS/linux-lts/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch new file mode 100644 index 0000000000..0d1f78cb37 --- /dev/null +++ b/SPECS/linux-lts/0072-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch @@ -0,0 +1,654 @@ +From 4a0cc33492f3fc8e642380ddcf6f355a4ec6cfc1 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Tue, 13 Jan 2026 10:38:26 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: Move PLIC and CLINT node + into CPU dtsi + +As we have a separate CPU dtsi file, move the PLIC and CLINT +node to the CPU dtsi file. This will make the sg2042.dtsi focus +on peripheral devices, and make the CPU dtsi force CPU related +devices. + +Reviewed-by: Chen Wang +Link: https://lore.kernel.org/r/20260113023828.790136-1-inochiama@gmail.com +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +Signed-off-by: Chen Wang +(cherry picked from commit 5e6836e735f9c9c5e8e1d1dce02dfed5fe566e8f) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 305 ++++++++++++++++++++ + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 303 ------------------- + 2 files changed, 305 insertions(+), 303 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +index 94a4b71acad3..509488eee432 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +@@ -2189,4 +2189,309 @@ l2_cache15: cache-controller-15 { + cache-unified; + }; + }; ++ ++ soc { ++ intc: interrupt-controller@7090000000 { ++ compatible = "sophgo,sg2042-plic", "thead,c900-plic"; ++ #address-cells = <0>; ++ #interrupt-cells = <2>; ++ reg = <0x00000070 0x90000000 0x00000000 0x04000000>; ++ interrupt-controller; ++ interrupts-extended = ++ <&cpu0_intc 11>, <&cpu0_intc 9>, ++ <&cpu1_intc 11>, <&cpu1_intc 9>, ++ <&cpu2_intc 11>, <&cpu2_intc 9>, ++ <&cpu3_intc 11>, <&cpu3_intc 9>, ++ <&cpu4_intc 11>, <&cpu4_intc 9>, ++ <&cpu5_intc 11>, <&cpu5_intc 9>, ++ <&cpu6_intc 11>, <&cpu6_intc 9>, ++ <&cpu7_intc 11>, <&cpu7_intc 9>, ++ <&cpu8_intc 11>, <&cpu8_intc 9>, ++ <&cpu9_intc 11>, <&cpu9_intc 9>, ++ <&cpu10_intc 11>, <&cpu10_intc 9>, ++ <&cpu11_intc 11>, <&cpu11_intc 9>, ++ <&cpu12_intc 11>, <&cpu12_intc 9>, ++ <&cpu13_intc 11>, <&cpu13_intc 9>, ++ <&cpu14_intc 11>, <&cpu14_intc 9>, ++ <&cpu15_intc 11>, <&cpu15_intc 9>, ++ <&cpu16_intc 11>, <&cpu16_intc 9>, ++ <&cpu17_intc 11>, <&cpu17_intc 9>, ++ <&cpu18_intc 11>, <&cpu18_intc 9>, ++ <&cpu19_intc 11>, <&cpu19_intc 9>, ++ <&cpu20_intc 11>, <&cpu20_intc 9>, ++ <&cpu21_intc 11>, <&cpu21_intc 9>, ++ <&cpu22_intc 11>, <&cpu22_intc 9>, ++ <&cpu23_intc 11>, <&cpu23_intc 9>, ++ <&cpu24_intc 11>, <&cpu24_intc 9>, ++ <&cpu25_intc 11>, <&cpu25_intc 9>, ++ <&cpu26_intc 11>, <&cpu26_intc 9>, ++ <&cpu27_intc 11>, <&cpu27_intc 9>, ++ <&cpu28_intc 11>, <&cpu28_intc 9>, ++ <&cpu29_intc 11>, <&cpu29_intc 9>, ++ <&cpu30_intc 11>, <&cpu30_intc 9>, ++ <&cpu31_intc 11>, <&cpu31_intc 9>, ++ <&cpu32_intc 11>, <&cpu32_intc 9>, ++ <&cpu33_intc 11>, <&cpu33_intc 9>, ++ <&cpu34_intc 11>, <&cpu34_intc 9>, ++ <&cpu35_intc 11>, <&cpu35_intc 9>, ++ <&cpu36_intc 11>, <&cpu36_intc 9>, ++ <&cpu37_intc 11>, <&cpu37_intc 9>, ++ <&cpu38_intc 11>, <&cpu38_intc 9>, ++ <&cpu39_intc 11>, <&cpu39_intc 9>, ++ <&cpu40_intc 11>, <&cpu40_intc 9>, ++ <&cpu41_intc 11>, <&cpu41_intc 9>, ++ <&cpu42_intc 11>, <&cpu42_intc 9>, ++ <&cpu43_intc 11>, <&cpu43_intc 9>, ++ <&cpu44_intc 11>, <&cpu44_intc 9>, ++ <&cpu45_intc 11>, <&cpu45_intc 9>, ++ <&cpu46_intc 11>, <&cpu46_intc 9>, ++ <&cpu47_intc 11>, <&cpu47_intc 9>, ++ <&cpu48_intc 11>, <&cpu48_intc 9>, ++ <&cpu49_intc 11>, <&cpu49_intc 9>, ++ <&cpu50_intc 11>, <&cpu50_intc 9>, ++ <&cpu51_intc 11>, <&cpu51_intc 9>, ++ <&cpu52_intc 11>, <&cpu52_intc 9>, ++ <&cpu53_intc 11>, <&cpu53_intc 9>, ++ <&cpu54_intc 11>, <&cpu54_intc 9>, ++ <&cpu55_intc 11>, <&cpu55_intc 9>, ++ <&cpu56_intc 11>, <&cpu56_intc 9>, ++ <&cpu57_intc 11>, <&cpu57_intc 9>, ++ <&cpu58_intc 11>, <&cpu58_intc 9>, ++ <&cpu59_intc 11>, <&cpu59_intc 9>, ++ <&cpu60_intc 11>, <&cpu60_intc 9>, ++ <&cpu61_intc 11>, <&cpu61_intc 9>, ++ <&cpu62_intc 11>, <&cpu62_intc 9>, ++ <&cpu63_intc 11>, <&cpu63_intc 9>; ++ riscv,ndev = <224>; ++ }; ++ ++ clint_mswi: interrupt-controller@7094000000 { ++ compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; ++ reg = <0x00000070 0x94000000 0x00000000 0x00004000>; ++ interrupts-extended = <&cpu0_intc 3>, ++ <&cpu1_intc 3>, ++ <&cpu2_intc 3>, ++ <&cpu3_intc 3>, ++ <&cpu4_intc 3>, ++ <&cpu5_intc 3>, ++ <&cpu6_intc 3>, ++ <&cpu7_intc 3>, ++ <&cpu8_intc 3>, ++ <&cpu9_intc 3>, ++ <&cpu10_intc 3>, ++ <&cpu11_intc 3>, ++ <&cpu12_intc 3>, ++ <&cpu13_intc 3>, ++ <&cpu14_intc 3>, ++ <&cpu15_intc 3>, ++ <&cpu16_intc 3>, ++ <&cpu17_intc 3>, ++ <&cpu18_intc 3>, ++ <&cpu19_intc 3>, ++ <&cpu20_intc 3>, ++ <&cpu21_intc 3>, ++ <&cpu22_intc 3>, ++ <&cpu23_intc 3>, ++ <&cpu24_intc 3>, ++ <&cpu25_intc 3>, ++ <&cpu26_intc 3>, ++ <&cpu27_intc 3>, ++ <&cpu28_intc 3>, ++ <&cpu29_intc 3>, ++ <&cpu30_intc 3>, ++ <&cpu31_intc 3>, ++ <&cpu32_intc 3>, ++ <&cpu33_intc 3>, ++ <&cpu34_intc 3>, ++ <&cpu35_intc 3>, ++ <&cpu36_intc 3>, ++ <&cpu37_intc 3>, ++ <&cpu38_intc 3>, ++ <&cpu39_intc 3>, ++ <&cpu40_intc 3>, ++ <&cpu41_intc 3>, ++ <&cpu42_intc 3>, ++ <&cpu43_intc 3>, ++ <&cpu44_intc 3>, ++ <&cpu45_intc 3>, ++ <&cpu46_intc 3>, ++ <&cpu47_intc 3>, ++ <&cpu48_intc 3>, ++ <&cpu49_intc 3>, ++ <&cpu50_intc 3>, ++ <&cpu51_intc 3>, ++ <&cpu52_intc 3>, ++ <&cpu53_intc 3>, ++ <&cpu54_intc 3>, ++ <&cpu55_intc 3>, ++ <&cpu56_intc 3>, ++ <&cpu57_intc 3>, ++ <&cpu58_intc 3>, ++ <&cpu59_intc 3>, ++ <&cpu60_intc 3>, ++ <&cpu61_intc 3>, ++ <&cpu62_intc 3>, ++ <&cpu63_intc 3>; ++ }; ++ ++ clint_mtimer0: timer@70ac004000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu0_intc 7>, ++ <&cpu1_intc 7>, ++ <&cpu2_intc 7>, ++ <&cpu3_intc 7>; ++ }; ++ ++ clint_mtimer1: timer@70ac014000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu4_intc 7>, ++ <&cpu5_intc 7>, ++ <&cpu6_intc 7>, ++ <&cpu7_intc 7>; ++ }; ++ ++ clint_mtimer2: timer@70ac024000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu8_intc 7>, ++ <&cpu9_intc 7>, ++ <&cpu10_intc 7>, ++ <&cpu11_intc 7>; ++ }; ++ ++ clint_mtimer3: timer@70ac034000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu12_intc 7>, ++ <&cpu13_intc 7>, ++ <&cpu14_intc 7>, ++ <&cpu15_intc 7>; ++ }; ++ ++ clint_mtimer4: timer@70ac044000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu16_intc 7>, ++ <&cpu17_intc 7>, ++ <&cpu18_intc 7>, ++ <&cpu19_intc 7>; ++ }; ++ ++ clint_mtimer5: timer@70ac054000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu20_intc 7>, ++ <&cpu21_intc 7>, ++ <&cpu22_intc 7>, ++ <&cpu23_intc 7>; ++ }; ++ ++ clint_mtimer6: timer@70ac064000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu24_intc 7>, ++ <&cpu25_intc 7>, ++ <&cpu26_intc 7>, ++ <&cpu27_intc 7>; ++ }; ++ ++ clint_mtimer7: timer@70ac074000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu28_intc 7>, ++ <&cpu29_intc 7>, ++ <&cpu30_intc 7>, ++ <&cpu31_intc 7>; ++ }; ++ ++ clint_mtimer8: timer@70ac084000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu32_intc 7>, ++ <&cpu33_intc 7>, ++ <&cpu34_intc 7>, ++ <&cpu35_intc 7>; ++ }; ++ ++ clint_mtimer9: timer@70ac094000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu36_intc 7>, ++ <&cpu37_intc 7>, ++ <&cpu38_intc 7>, ++ <&cpu39_intc 7>; ++ }; ++ ++ clint_mtimer10: timer@70ac0a4000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu40_intc 7>, ++ <&cpu41_intc 7>, ++ <&cpu42_intc 7>, ++ <&cpu43_intc 7>; ++ }; ++ ++ clint_mtimer11: timer@70ac0b4000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu44_intc 7>, ++ <&cpu45_intc 7>, ++ <&cpu46_intc 7>, ++ <&cpu47_intc 7>; ++ }; ++ ++ clint_mtimer12: timer@70ac0c4000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu48_intc 7>, ++ <&cpu49_intc 7>, ++ <&cpu50_intc 7>, ++ <&cpu51_intc 7>; ++ }; ++ ++ clint_mtimer13: timer@70ac0d4000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu52_intc 7>, ++ <&cpu53_intc 7>, ++ <&cpu54_intc 7>, ++ <&cpu55_intc 7>; ++ }; ++ ++ clint_mtimer14: timer@70ac0e4000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu56_intc 7>, ++ <&cpu57_intc 7>, ++ <&cpu58_intc 7>, ++ <&cpu59_intc 7>; ++ }; ++ ++ clint_mtimer15: timer@70ac0f4000 { ++ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; ++ reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; ++ reg-names = "mtimecmp"; ++ interrupts-extended = <&cpu60_intc 7>, ++ <&cpu61_intc 7>, ++ <&cpu62_intc 7>, ++ <&cpu63_intc 7>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +index ec99da39150f..e6891f95d479 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +@@ -352,309 +352,6 @@ pcie_rc3: pcie@7062800000 { + status = "disabled"; + }; + +- clint_mswi: interrupt-controller@7094000000 { +- compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; +- reg = <0x00000070 0x94000000 0x00000000 0x00004000>; +- interrupts-extended = <&cpu0_intc 3>, +- <&cpu1_intc 3>, +- <&cpu2_intc 3>, +- <&cpu3_intc 3>, +- <&cpu4_intc 3>, +- <&cpu5_intc 3>, +- <&cpu6_intc 3>, +- <&cpu7_intc 3>, +- <&cpu8_intc 3>, +- <&cpu9_intc 3>, +- <&cpu10_intc 3>, +- <&cpu11_intc 3>, +- <&cpu12_intc 3>, +- <&cpu13_intc 3>, +- <&cpu14_intc 3>, +- <&cpu15_intc 3>, +- <&cpu16_intc 3>, +- <&cpu17_intc 3>, +- <&cpu18_intc 3>, +- <&cpu19_intc 3>, +- <&cpu20_intc 3>, +- <&cpu21_intc 3>, +- <&cpu22_intc 3>, +- <&cpu23_intc 3>, +- <&cpu24_intc 3>, +- <&cpu25_intc 3>, +- <&cpu26_intc 3>, +- <&cpu27_intc 3>, +- <&cpu28_intc 3>, +- <&cpu29_intc 3>, +- <&cpu30_intc 3>, +- <&cpu31_intc 3>, +- <&cpu32_intc 3>, +- <&cpu33_intc 3>, +- <&cpu34_intc 3>, +- <&cpu35_intc 3>, +- <&cpu36_intc 3>, +- <&cpu37_intc 3>, +- <&cpu38_intc 3>, +- <&cpu39_intc 3>, +- <&cpu40_intc 3>, +- <&cpu41_intc 3>, +- <&cpu42_intc 3>, +- <&cpu43_intc 3>, +- <&cpu44_intc 3>, +- <&cpu45_intc 3>, +- <&cpu46_intc 3>, +- <&cpu47_intc 3>, +- <&cpu48_intc 3>, +- <&cpu49_intc 3>, +- <&cpu50_intc 3>, +- <&cpu51_intc 3>, +- <&cpu52_intc 3>, +- <&cpu53_intc 3>, +- <&cpu54_intc 3>, +- <&cpu55_intc 3>, +- <&cpu56_intc 3>, +- <&cpu57_intc 3>, +- <&cpu58_intc 3>, +- <&cpu59_intc 3>, +- <&cpu60_intc 3>, +- <&cpu61_intc 3>, +- <&cpu62_intc 3>, +- <&cpu63_intc 3>; +- }; +- +- clint_mtimer0: timer@70ac004000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu0_intc 7>, +- <&cpu1_intc 7>, +- <&cpu2_intc 7>, +- <&cpu3_intc 7>; +- }; +- +- clint_mtimer1: timer@70ac014000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu4_intc 7>, +- <&cpu5_intc 7>, +- <&cpu6_intc 7>, +- <&cpu7_intc 7>; +- }; +- +- clint_mtimer2: timer@70ac024000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu8_intc 7>, +- <&cpu9_intc 7>, +- <&cpu10_intc 7>, +- <&cpu11_intc 7>; +- }; +- +- clint_mtimer3: timer@70ac034000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu12_intc 7>, +- <&cpu13_intc 7>, +- <&cpu14_intc 7>, +- <&cpu15_intc 7>; +- }; +- +- clint_mtimer4: timer@70ac044000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu16_intc 7>, +- <&cpu17_intc 7>, +- <&cpu18_intc 7>, +- <&cpu19_intc 7>; +- }; +- +- clint_mtimer5: timer@70ac054000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu20_intc 7>, +- <&cpu21_intc 7>, +- <&cpu22_intc 7>, +- <&cpu23_intc 7>; +- }; +- +- clint_mtimer6: timer@70ac064000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu24_intc 7>, +- <&cpu25_intc 7>, +- <&cpu26_intc 7>, +- <&cpu27_intc 7>; +- }; +- +- clint_mtimer7: timer@70ac074000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu28_intc 7>, +- <&cpu29_intc 7>, +- <&cpu30_intc 7>, +- <&cpu31_intc 7>; +- }; +- +- clint_mtimer8: timer@70ac084000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu32_intc 7>, +- <&cpu33_intc 7>, +- <&cpu34_intc 7>, +- <&cpu35_intc 7>; +- }; +- +- clint_mtimer9: timer@70ac094000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu36_intc 7>, +- <&cpu37_intc 7>, +- <&cpu38_intc 7>, +- <&cpu39_intc 7>; +- }; +- +- clint_mtimer10: timer@70ac0a4000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu40_intc 7>, +- <&cpu41_intc 7>, +- <&cpu42_intc 7>, +- <&cpu43_intc 7>; +- }; +- +- clint_mtimer11: timer@70ac0b4000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu44_intc 7>, +- <&cpu45_intc 7>, +- <&cpu46_intc 7>, +- <&cpu47_intc 7>; +- }; +- +- clint_mtimer12: timer@70ac0c4000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu48_intc 7>, +- <&cpu49_intc 7>, +- <&cpu50_intc 7>, +- <&cpu51_intc 7>; +- }; +- +- clint_mtimer13: timer@70ac0d4000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu52_intc 7>, +- <&cpu53_intc 7>, +- <&cpu54_intc 7>, +- <&cpu55_intc 7>; +- }; +- +- clint_mtimer14: timer@70ac0e4000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu56_intc 7>, +- <&cpu57_intc 7>, +- <&cpu58_intc 7>, +- <&cpu59_intc 7>; +- }; +- +- clint_mtimer15: timer@70ac0f4000 { +- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; +- reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; +- reg-names = "mtimecmp"; +- interrupts-extended = <&cpu60_intc 7>, +- <&cpu61_intc 7>, +- <&cpu62_intc 7>, +- <&cpu63_intc 7>; +- }; +- +- intc: interrupt-controller@7090000000 { +- compatible = "sophgo,sg2042-plic", "thead,c900-plic"; +- #address-cells = <0>; +- #interrupt-cells = <2>; +- reg = <0x00000070 0x90000000 0x00000000 0x04000000>; +- interrupt-controller; +- interrupts-extended = +- <&cpu0_intc 11>, <&cpu0_intc 9>, +- <&cpu1_intc 11>, <&cpu1_intc 9>, +- <&cpu2_intc 11>, <&cpu2_intc 9>, +- <&cpu3_intc 11>, <&cpu3_intc 9>, +- <&cpu4_intc 11>, <&cpu4_intc 9>, +- <&cpu5_intc 11>, <&cpu5_intc 9>, +- <&cpu6_intc 11>, <&cpu6_intc 9>, +- <&cpu7_intc 11>, <&cpu7_intc 9>, +- <&cpu8_intc 11>, <&cpu8_intc 9>, +- <&cpu9_intc 11>, <&cpu9_intc 9>, +- <&cpu10_intc 11>, <&cpu10_intc 9>, +- <&cpu11_intc 11>, <&cpu11_intc 9>, +- <&cpu12_intc 11>, <&cpu12_intc 9>, +- <&cpu13_intc 11>, <&cpu13_intc 9>, +- <&cpu14_intc 11>, <&cpu14_intc 9>, +- <&cpu15_intc 11>, <&cpu15_intc 9>, +- <&cpu16_intc 11>, <&cpu16_intc 9>, +- <&cpu17_intc 11>, <&cpu17_intc 9>, +- <&cpu18_intc 11>, <&cpu18_intc 9>, +- <&cpu19_intc 11>, <&cpu19_intc 9>, +- <&cpu20_intc 11>, <&cpu20_intc 9>, +- <&cpu21_intc 11>, <&cpu21_intc 9>, +- <&cpu22_intc 11>, <&cpu22_intc 9>, +- <&cpu23_intc 11>, <&cpu23_intc 9>, +- <&cpu24_intc 11>, <&cpu24_intc 9>, +- <&cpu25_intc 11>, <&cpu25_intc 9>, +- <&cpu26_intc 11>, <&cpu26_intc 9>, +- <&cpu27_intc 11>, <&cpu27_intc 9>, +- <&cpu28_intc 11>, <&cpu28_intc 9>, +- <&cpu29_intc 11>, <&cpu29_intc 9>, +- <&cpu30_intc 11>, <&cpu30_intc 9>, +- <&cpu31_intc 11>, <&cpu31_intc 9>, +- <&cpu32_intc 11>, <&cpu32_intc 9>, +- <&cpu33_intc 11>, <&cpu33_intc 9>, +- <&cpu34_intc 11>, <&cpu34_intc 9>, +- <&cpu35_intc 11>, <&cpu35_intc 9>, +- <&cpu36_intc 11>, <&cpu36_intc 9>, +- <&cpu37_intc 11>, <&cpu37_intc 9>, +- <&cpu38_intc 11>, <&cpu38_intc 9>, +- <&cpu39_intc 11>, <&cpu39_intc 9>, +- <&cpu40_intc 11>, <&cpu40_intc 9>, +- <&cpu41_intc 11>, <&cpu41_intc 9>, +- <&cpu42_intc 11>, <&cpu42_intc 9>, +- <&cpu43_intc 11>, <&cpu43_intc 9>, +- <&cpu44_intc 11>, <&cpu44_intc 9>, +- <&cpu45_intc 11>, <&cpu45_intc 9>, +- <&cpu46_intc 11>, <&cpu46_intc 9>, +- <&cpu47_intc 11>, <&cpu47_intc 9>, +- <&cpu48_intc 11>, <&cpu48_intc 9>, +- <&cpu49_intc 11>, <&cpu49_intc 9>, +- <&cpu50_intc 11>, <&cpu50_intc 9>, +- <&cpu51_intc 11>, <&cpu51_intc 9>, +- <&cpu52_intc 11>, <&cpu52_intc 9>, +- <&cpu53_intc 11>, <&cpu53_intc 9>, +- <&cpu54_intc 11>, <&cpu54_intc 9>, +- <&cpu55_intc 11>, <&cpu55_intc 9>, +- <&cpu56_intc 11>, <&cpu56_intc 9>, +- <&cpu57_intc 11>, <&cpu57_intc 9>, +- <&cpu58_intc 11>, <&cpu58_intc 9>, +- <&cpu59_intc 11>, <&cpu59_intc 9>, +- <&cpu60_intc 11>, <&cpu60_intc 9>, +- <&cpu61_intc 11>, <&cpu61_intc 9>, +- <&cpu62_intc 11>, <&cpu62_intc 9>, +- <&cpu63_intc 11>, <&cpu63_intc 9>; +- riscv,ndev = <224>; +- }; +- + rstgen: reset-controller@7030013000 { + compatible = "sophgo,sg2042-reset"; + reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0073-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch b/SPECS/linux-lts/0073-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch deleted file mode 100644 index ff05d9aa86..0000000000 --- a/SPECS/linux-lts/0073-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 749d96eafd7fb34b9586ad8b894f76b4c121a47a Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 29 Jan 2026 09:56:09 +0800 -Subject: [PATCH 073/467] UPSTREAM: ALSA: hda/intel: Make MSI address limit - based on the device DMA limit - -The hda/intel driver restricts the MSI message address for devices which do -not advertise full 64-bit DMA address space support to 32-bit due to the -former restrictions of the PCI/MSI code which only allowed either 32-bit or -a full 64-bit address range. - -This does not work on platforms which have a MSI doorbell address above the -32-bit boundary but do not support the full 64 bit address range. - -The PCI/MSI core converted this binary decision to a DMA_BIT_MASK() based -decision, which allows to describe the device limitations precisely. - -Convert the driver to provide the exact DMA address limitations to the -PCI/MSI core. That allows devices which do not support the full 64-bit -address space to work on platforms which have a MSI doorbell address above -the 32-bit limit as long as it is within the hardware's addressable range. - -[ tglx: Massage changelog ] - -Signed-off-by: Vivian Wang -Signed-off-by: Thomas Gleixner -Acked-by: Takashi Iwai -Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-4-70da998f2750@iscas.ac.cn -(cherry picked from commit cb9b6f9d2be6bda1b0117b147df40f982ce06888) -Signed-off-by: Han Gao ---- - sound/hda/controllers/intel.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c -index 44781b87d58e..6f89875e7c3c 100644 ---- a/sound/hda/controllers/intel.c -+++ b/sound/hda/controllers/intel.c -@@ -1905,11 +1905,6 @@ static int azx_first_init(struct azx *chip) - chip->gts_present = true; - #endif - -- if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { -- dev_dbg(card->dev, "Disabling 64bit MSI\n"); -- pci->msi_addr_mask = DMA_BIT_MASK(32); -- } -- - pci_set_master(pci); - - gcap = azx_readw(chip, GCAP); -@@ -1960,6 +1955,11 @@ static int azx_first_init(struct azx *chip) - dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); - dma_set_max_seg_size(&pci->dev, UINT_MAX); - -+ if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { -+ dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits); -+ pci->msi_addr_mask = DMA_BIT_MASK(dma_bits); -+ } -+ - /* read number of streams from GCAP register instead of using - * hardcoded value - */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch b/SPECS/linux-lts/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch new file mode 100644 index 0000000000..0d20c75013 --- /dev/null +++ b/SPECS/linux-lts/0073-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch @@ -0,0 +1,216 @@ +From 05c376f7568773671fcd81b7cc92e365126410d0 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Tue, 13 Jan 2026 10:38:27 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: fix the node order of + SG2042 peripheral + +In sg2042.dtsi, some peripheral device node does not follow the +address order. Reorder them in ascending order by address. + +Reviewed-by: Chen Wang +Link: https://lore.kernel.org/r/20260113023828.790136-2-inochiama@gmail.com +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +Signed-off-by: Chen Wang +(cherry picked from commit ebb87dd74c34a76e1e93041e9329cf9269be35ed) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 176 ++++++++++++------------- + 1 file changed, 88 insertions(+), 88 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +index e6891f95d479..9fddf3f0b3b9 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +@@ -264,94 +264,6 @@ clkgen: clock-controller@7030012000 { + #clock-cells = <1>; + }; + +- pcie_rc0: pcie@7060000000 { +- compatible = "sophgo,sg2042-pcie-host"; +- device_type = "pci"; +- reg = <0x70 0x60000000 0x0 0x00800000>, +- <0x40 0x00000000 0x0 0x00001000>; +- reg-names = "reg", "cfg"; +- linux,pci-domain = <0>; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, +- <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, +- <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, +- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, +- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; +- bus-range = <0x0 0xff>; +- vendor-id = <0x1f1c>; +- device-id = <0x2042>; +- cdns,no-bar-match-nbits = <48>; +- msi-parent = <&msi>; +- status = "disabled"; +- }; +- +- pcie_rc1: pcie@7060800000 { +- compatible = "sophgo,sg2042-pcie-host"; +- device_type = "pci"; +- reg = <0x70 0x60800000 0x0 0x00800000>, +- <0x44 0x00000000 0x0 0x00001000>; +- reg-names = "reg", "cfg"; +- linux,pci-domain = <1>; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, +- <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, +- <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, +- <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, +- <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; +- bus-range = <0x0 0xff>; +- vendor-id = <0x1f1c>; +- device-id = <0x2042>; +- cdns,no-bar-match-nbits = <48>; +- msi-parent = <&msi>; +- status = "disabled"; +- }; +- +- pcie_rc2: pcie@7062000000 { +- compatible = "sophgo,sg2042-pcie-host"; +- device_type = "pci"; +- reg = <0x70 0x62000000 0x0 0x00800000>, +- <0x48 0x00000000 0x0 0x00001000>; +- reg-names = "reg", "cfg"; +- linux,pci-domain = <2>; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, +- <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, +- <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, +- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, +- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; +- bus-range = <0x0 0xff>; +- vendor-id = <0x1f1c>; +- device-id = <0x2042>; +- cdns,no-bar-match-nbits = <48>; +- msi-parent = <&msi>; +- status = "disabled"; +- }; +- +- pcie_rc3: pcie@7062800000 { +- compatible = "sophgo,sg2042-pcie-host"; +- device_type = "pci"; +- reg = <0x70 0x62800000 0x0 0x00800000>, +- <0x4c 0x00000000 0x0 0x00001000>; +- reg-names = "reg", "cfg"; +- linux,pci-domain = <3>; +- #address-cells = <3>; +- #size-cells = <2>; +- ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, +- <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, +- <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, +- <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, +- <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; +- bus-range = <0x0 0xff>; +- vendor-id = <0x1f1c>; +- device-id = <0x2042>; +- cdns,no-bar-match-nbits = <48>; +- msi-parent = <&msi>; +- status = "disabled"; +- }; +- + rstgen: reset-controller@7030013000 { + compatible = "sophgo,sg2042-reset"; + reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; +@@ -486,5 +398,93 @@ sd: mmc@704002b000 { + "timer"; + status = "disabled"; + }; ++ ++ pcie_rc0: pcie@7060000000 { ++ compatible = "sophgo,sg2042-pcie-host"; ++ device_type = "pci"; ++ reg = <0x70 0x60000000 0x0 0x00800000>, ++ <0x40 0x00000000 0x0 0x00001000>; ++ reg-names = "reg", "cfg"; ++ linux,pci-domain = <0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, ++ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; ++ bus-range = <0x0 0xff>; ++ vendor-id = <0x1f1c>; ++ device-id = <0x2042>; ++ cdns,no-bar-match-nbits = <48>; ++ msi-parent = <&msi>; ++ status = "disabled"; ++ }; ++ ++ pcie_rc1: pcie@7060800000 { ++ compatible = "sophgo,sg2042-pcie-host"; ++ device_type = "pci"; ++ reg = <0x70 0x60800000 0x0 0x00800000>, ++ <0x44 0x00000000 0x0 0x00001000>; ++ reg-names = "reg", "cfg"; ++ linux,pci-domain = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, ++ <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; ++ bus-range = <0x0 0xff>; ++ vendor-id = <0x1f1c>; ++ device-id = <0x2042>; ++ cdns,no-bar-match-nbits = <48>; ++ msi-parent = <&msi>; ++ status = "disabled"; ++ }; ++ ++ pcie_rc2: pcie@7062000000 { ++ compatible = "sophgo,sg2042-pcie-host"; ++ device_type = "pci"; ++ reg = <0x70 0x62000000 0x0 0x00800000>, ++ <0x48 0x00000000 0x0 0x00001000>; ++ reg-names = "reg", "cfg"; ++ linux,pci-domain = <2>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, ++ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, ++ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; ++ bus-range = <0x0 0xff>; ++ vendor-id = <0x1f1c>; ++ device-id = <0x2042>; ++ cdns,no-bar-match-nbits = <48>; ++ msi-parent = <&msi>; ++ status = "disabled"; ++ }; ++ ++ pcie_rc3: pcie@7062800000 { ++ compatible = "sophgo,sg2042-pcie-host"; ++ device_type = "pci"; ++ reg = <0x70 0x62800000 0x0 0x00800000>, ++ <0x4c 0x00000000 0x0 0x00001000>; ++ reg-names = "reg", "cfg"; ++ linux,pci-domain = <3>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, ++ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, ++ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, ++ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; ++ bus-range = <0x0 0xff>; ++ vendor-id = <0x1f1c>; ++ device-id = <0x2042>; ++ cdns,no-bar-match-nbits = <48>; ++ msi-parent = <&msi>; ++ status = "disabled"; ++ }; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0074-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch b/SPECS/linux-lts/0074-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch deleted file mode 100644 index 37197af0cf..0000000000 --- a/SPECS/linux-lts/0074-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 30a1d9c76630cd4198787ef0603dd4921f1559cf Mon Sep 17 00:00:00 2001 -From: Michael Orlitzky -Date: Wed, 7 Jan 2026 06:29:22 -0500 -Subject: [PATCH 074/467] UPSTREAM: riscv: dts: sophgo: enable hardware clock - (RTC) on the Milk-V Pioneer - -These boards have a working hardware clock if you put a CR-1220 -battery in them. We enable it using information from a 6.1.x vendor -kernel. - -Reviewed-by: Chen Wang -Signed-off-by: Michael Orlitzky -Link: https://lore.kernel.org/r/20260107112922.20013-2-michael@orlitzky.com -Signed-off-by: Inochi Amaoto -Signed-off-by: Chen Wang -Signed-off-by: Chen Wang -(cherry picked from commit 9e81c522680db5998c872fb91ff7877cf3d8ff42) -Signed-off-by: Han Gao ---- - .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 21 +++++++++++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts -index 54d8386bf9c0..ecf8c1e29079 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts -+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts -@@ -52,6 +52,17 @@ &emmc { - status = "okay"; - }; - -+&i2c0 { -+ pinctrl-0 = <&i2c0_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ rtc: rtc@68 { -+ compatible = "dallas,ds1307"; -+ reg = <0x68>; -+ }; -+}; -+ - &i2c1 { - pinctrl-0 = <&i2c1_cfg>; - pinctrl-names = "default"; -@@ -89,6 +100,16 @@ sdhci-emmc-rst-pwr-pins { - }; - }; - -+ i2c0_cfg: i2c0-cfg { -+ i2c0-pins { -+ pinmux = , -+ ; -+ bias-pull-up; -+ drive-strength-microamp = <26800>; -+ input-schmitt-enable; -+ }; -+ }; -+ - i2c1_cfg: i2c1-cfg { - i2c1-pins { - pinmux = , --- -2.53.0 - diff --git a/SPECS/linux-lts/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux-lts/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch new file mode 100644 index 0000000000..5f97d6ec8f --- /dev/null +++ b/SPECS/linux-lts/0074-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch @@ -0,0 +1,38 @@ +From 7b375e6d39b2d52853eaff4e1f70555adadc5253 Mon Sep 17 00:00:00 2001 +From: Javier Martinez Canillas +Date: Sat, 6 Dec 2025 14:44:53 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Enable i2c8 adapter for + Milk-V Jupiter + +The adapter is used to access the SpacemiT P1 PMIC present in this board. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20251206134532.1741648-2-javierm@redhat.com +Signed-off-by: Yixun Lan +(cherry picked from commit f33ccc2316304f3a71e40e53f1568e75042b0a4b) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 28afd39b28da..aa425f02c1f4 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -72,6 +72,12 @@ &pdma { + status = "okay"; + }; + ++&i2c8 { ++ pinctrl-0 = <&i2c8_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0075-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch b/SPECS/linux-lts/0075-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch deleted file mode 100644 index bf6b8b20f9..0000000000 --- a/SPECS/linux-lts/0075-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch +++ /dev/null @@ -1,654 +0,0 @@ -From e07dd958a1dd608e75f5d83068968406cf2c73a1 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Tue, 13 Jan 2026 10:38:26 +0800 -Subject: [PATCH 075/467] UPSTREAM: riscv: dts: sophgo: Move PLIC and CLINT - node into CPU dtsi - -As we have a separate CPU dtsi file, move the PLIC and CLINT -node to the CPU dtsi file. This will make the sg2042.dtsi focus -on peripheral devices, and make the CPU dtsi force CPU related -devices. - -Reviewed-by: Chen Wang -Link: https://lore.kernel.org/r/20260113023828.790136-1-inochiama@gmail.com -Signed-off-by: Inochi Amaoto -Signed-off-by: Chen Wang -Signed-off-by: Chen Wang -(cherry picked from commit 5e6836e735f9c9c5e8e1d1dce02dfed5fe566e8f) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 305 ++++++++++++++++++++ - arch/riscv/boot/dts/sophgo/sg2042.dtsi | 303 ------------------- - 2 files changed, 305 insertions(+), 303 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -index 94a4b71acad3..509488eee432 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -@@ -2189,4 +2189,309 @@ l2_cache15: cache-controller-15 { - cache-unified; - }; - }; -+ -+ soc { -+ intc: interrupt-controller@7090000000 { -+ compatible = "sophgo,sg2042-plic", "thead,c900-plic"; -+ #address-cells = <0>; -+ #interrupt-cells = <2>; -+ reg = <0x00000070 0x90000000 0x00000000 0x04000000>; -+ interrupt-controller; -+ interrupts-extended = -+ <&cpu0_intc 11>, <&cpu0_intc 9>, -+ <&cpu1_intc 11>, <&cpu1_intc 9>, -+ <&cpu2_intc 11>, <&cpu2_intc 9>, -+ <&cpu3_intc 11>, <&cpu3_intc 9>, -+ <&cpu4_intc 11>, <&cpu4_intc 9>, -+ <&cpu5_intc 11>, <&cpu5_intc 9>, -+ <&cpu6_intc 11>, <&cpu6_intc 9>, -+ <&cpu7_intc 11>, <&cpu7_intc 9>, -+ <&cpu8_intc 11>, <&cpu8_intc 9>, -+ <&cpu9_intc 11>, <&cpu9_intc 9>, -+ <&cpu10_intc 11>, <&cpu10_intc 9>, -+ <&cpu11_intc 11>, <&cpu11_intc 9>, -+ <&cpu12_intc 11>, <&cpu12_intc 9>, -+ <&cpu13_intc 11>, <&cpu13_intc 9>, -+ <&cpu14_intc 11>, <&cpu14_intc 9>, -+ <&cpu15_intc 11>, <&cpu15_intc 9>, -+ <&cpu16_intc 11>, <&cpu16_intc 9>, -+ <&cpu17_intc 11>, <&cpu17_intc 9>, -+ <&cpu18_intc 11>, <&cpu18_intc 9>, -+ <&cpu19_intc 11>, <&cpu19_intc 9>, -+ <&cpu20_intc 11>, <&cpu20_intc 9>, -+ <&cpu21_intc 11>, <&cpu21_intc 9>, -+ <&cpu22_intc 11>, <&cpu22_intc 9>, -+ <&cpu23_intc 11>, <&cpu23_intc 9>, -+ <&cpu24_intc 11>, <&cpu24_intc 9>, -+ <&cpu25_intc 11>, <&cpu25_intc 9>, -+ <&cpu26_intc 11>, <&cpu26_intc 9>, -+ <&cpu27_intc 11>, <&cpu27_intc 9>, -+ <&cpu28_intc 11>, <&cpu28_intc 9>, -+ <&cpu29_intc 11>, <&cpu29_intc 9>, -+ <&cpu30_intc 11>, <&cpu30_intc 9>, -+ <&cpu31_intc 11>, <&cpu31_intc 9>, -+ <&cpu32_intc 11>, <&cpu32_intc 9>, -+ <&cpu33_intc 11>, <&cpu33_intc 9>, -+ <&cpu34_intc 11>, <&cpu34_intc 9>, -+ <&cpu35_intc 11>, <&cpu35_intc 9>, -+ <&cpu36_intc 11>, <&cpu36_intc 9>, -+ <&cpu37_intc 11>, <&cpu37_intc 9>, -+ <&cpu38_intc 11>, <&cpu38_intc 9>, -+ <&cpu39_intc 11>, <&cpu39_intc 9>, -+ <&cpu40_intc 11>, <&cpu40_intc 9>, -+ <&cpu41_intc 11>, <&cpu41_intc 9>, -+ <&cpu42_intc 11>, <&cpu42_intc 9>, -+ <&cpu43_intc 11>, <&cpu43_intc 9>, -+ <&cpu44_intc 11>, <&cpu44_intc 9>, -+ <&cpu45_intc 11>, <&cpu45_intc 9>, -+ <&cpu46_intc 11>, <&cpu46_intc 9>, -+ <&cpu47_intc 11>, <&cpu47_intc 9>, -+ <&cpu48_intc 11>, <&cpu48_intc 9>, -+ <&cpu49_intc 11>, <&cpu49_intc 9>, -+ <&cpu50_intc 11>, <&cpu50_intc 9>, -+ <&cpu51_intc 11>, <&cpu51_intc 9>, -+ <&cpu52_intc 11>, <&cpu52_intc 9>, -+ <&cpu53_intc 11>, <&cpu53_intc 9>, -+ <&cpu54_intc 11>, <&cpu54_intc 9>, -+ <&cpu55_intc 11>, <&cpu55_intc 9>, -+ <&cpu56_intc 11>, <&cpu56_intc 9>, -+ <&cpu57_intc 11>, <&cpu57_intc 9>, -+ <&cpu58_intc 11>, <&cpu58_intc 9>, -+ <&cpu59_intc 11>, <&cpu59_intc 9>, -+ <&cpu60_intc 11>, <&cpu60_intc 9>, -+ <&cpu61_intc 11>, <&cpu61_intc 9>, -+ <&cpu62_intc 11>, <&cpu62_intc 9>, -+ <&cpu63_intc 11>, <&cpu63_intc 9>; -+ riscv,ndev = <224>; -+ }; -+ -+ clint_mswi: interrupt-controller@7094000000 { -+ compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; -+ reg = <0x00000070 0x94000000 0x00000000 0x00004000>; -+ interrupts-extended = <&cpu0_intc 3>, -+ <&cpu1_intc 3>, -+ <&cpu2_intc 3>, -+ <&cpu3_intc 3>, -+ <&cpu4_intc 3>, -+ <&cpu5_intc 3>, -+ <&cpu6_intc 3>, -+ <&cpu7_intc 3>, -+ <&cpu8_intc 3>, -+ <&cpu9_intc 3>, -+ <&cpu10_intc 3>, -+ <&cpu11_intc 3>, -+ <&cpu12_intc 3>, -+ <&cpu13_intc 3>, -+ <&cpu14_intc 3>, -+ <&cpu15_intc 3>, -+ <&cpu16_intc 3>, -+ <&cpu17_intc 3>, -+ <&cpu18_intc 3>, -+ <&cpu19_intc 3>, -+ <&cpu20_intc 3>, -+ <&cpu21_intc 3>, -+ <&cpu22_intc 3>, -+ <&cpu23_intc 3>, -+ <&cpu24_intc 3>, -+ <&cpu25_intc 3>, -+ <&cpu26_intc 3>, -+ <&cpu27_intc 3>, -+ <&cpu28_intc 3>, -+ <&cpu29_intc 3>, -+ <&cpu30_intc 3>, -+ <&cpu31_intc 3>, -+ <&cpu32_intc 3>, -+ <&cpu33_intc 3>, -+ <&cpu34_intc 3>, -+ <&cpu35_intc 3>, -+ <&cpu36_intc 3>, -+ <&cpu37_intc 3>, -+ <&cpu38_intc 3>, -+ <&cpu39_intc 3>, -+ <&cpu40_intc 3>, -+ <&cpu41_intc 3>, -+ <&cpu42_intc 3>, -+ <&cpu43_intc 3>, -+ <&cpu44_intc 3>, -+ <&cpu45_intc 3>, -+ <&cpu46_intc 3>, -+ <&cpu47_intc 3>, -+ <&cpu48_intc 3>, -+ <&cpu49_intc 3>, -+ <&cpu50_intc 3>, -+ <&cpu51_intc 3>, -+ <&cpu52_intc 3>, -+ <&cpu53_intc 3>, -+ <&cpu54_intc 3>, -+ <&cpu55_intc 3>, -+ <&cpu56_intc 3>, -+ <&cpu57_intc 3>, -+ <&cpu58_intc 3>, -+ <&cpu59_intc 3>, -+ <&cpu60_intc 3>, -+ <&cpu61_intc 3>, -+ <&cpu62_intc 3>, -+ <&cpu63_intc 3>; -+ }; -+ -+ clint_mtimer0: timer@70ac004000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu0_intc 7>, -+ <&cpu1_intc 7>, -+ <&cpu2_intc 7>, -+ <&cpu3_intc 7>; -+ }; -+ -+ clint_mtimer1: timer@70ac014000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu4_intc 7>, -+ <&cpu5_intc 7>, -+ <&cpu6_intc 7>, -+ <&cpu7_intc 7>; -+ }; -+ -+ clint_mtimer2: timer@70ac024000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu8_intc 7>, -+ <&cpu9_intc 7>, -+ <&cpu10_intc 7>, -+ <&cpu11_intc 7>; -+ }; -+ -+ clint_mtimer3: timer@70ac034000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu12_intc 7>, -+ <&cpu13_intc 7>, -+ <&cpu14_intc 7>, -+ <&cpu15_intc 7>; -+ }; -+ -+ clint_mtimer4: timer@70ac044000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu16_intc 7>, -+ <&cpu17_intc 7>, -+ <&cpu18_intc 7>, -+ <&cpu19_intc 7>; -+ }; -+ -+ clint_mtimer5: timer@70ac054000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu20_intc 7>, -+ <&cpu21_intc 7>, -+ <&cpu22_intc 7>, -+ <&cpu23_intc 7>; -+ }; -+ -+ clint_mtimer6: timer@70ac064000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu24_intc 7>, -+ <&cpu25_intc 7>, -+ <&cpu26_intc 7>, -+ <&cpu27_intc 7>; -+ }; -+ -+ clint_mtimer7: timer@70ac074000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu28_intc 7>, -+ <&cpu29_intc 7>, -+ <&cpu30_intc 7>, -+ <&cpu31_intc 7>; -+ }; -+ -+ clint_mtimer8: timer@70ac084000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu32_intc 7>, -+ <&cpu33_intc 7>, -+ <&cpu34_intc 7>, -+ <&cpu35_intc 7>; -+ }; -+ -+ clint_mtimer9: timer@70ac094000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu36_intc 7>, -+ <&cpu37_intc 7>, -+ <&cpu38_intc 7>, -+ <&cpu39_intc 7>; -+ }; -+ -+ clint_mtimer10: timer@70ac0a4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu40_intc 7>, -+ <&cpu41_intc 7>, -+ <&cpu42_intc 7>, -+ <&cpu43_intc 7>; -+ }; -+ -+ clint_mtimer11: timer@70ac0b4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu44_intc 7>, -+ <&cpu45_intc 7>, -+ <&cpu46_intc 7>, -+ <&cpu47_intc 7>; -+ }; -+ -+ clint_mtimer12: timer@70ac0c4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu48_intc 7>, -+ <&cpu49_intc 7>, -+ <&cpu50_intc 7>, -+ <&cpu51_intc 7>; -+ }; -+ -+ clint_mtimer13: timer@70ac0d4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu52_intc 7>, -+ <&cpu53_intc 7>, -+ <&cpu54_intc 7>, -+ <&cpu55_intc 7>; -+ }; -+ -+ clint_mtimer14: timer@70ac0e4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu56_intc 7>, -+ <&cpu57_intc 7>, -+ <&cpu58_intc 7>, -+ <&cpu59_intc 7>; -+ }; -+ -+ clint_mtimer15: timer@70ac0f4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu60_intc 7>, -+ <&cpu61_intc 7>, -+ <&cpu62_intc 7>, -+ <&cpu63_intc 7>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -index ec99da39150f..e6891f95d479 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -@@ -352,309 +352,6 @@ pcie_rc3: pcie@7062800000 { - status = "disabled"; - }; - -- clint_mswi: interrupt-controller@7094000000 { -- compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; -- reg = <0x00000070 0x94000000 0x00000000 0x00004000>; -- interrupts-extended = <&cpu0_intc 3>, -- <&cpu1_intc 3>, -- <&cpu2_intc 3>, -- <&cpu3_intc 3>, -- <&cpu4_intc 3>, -- <&cpu5_intc 3>, -- <&cpu6_intc 3>, -- <&cpu7_intc 3>, -- <&cpu8_intc 3>, -- <&cpu9_intc 3>, -- <&cpu10_intc 3>, -- <&cpu11_intc 3>, -- <&cpu12_intc 3>, -- <&cpu13_intc 3>, -- <&cpu14_intc 3>, -- <&cpu15_intc 3>, -- <&cpu16_intc 3>, -- <&cpu17_intc 3>, -- <&cpu18_intc 3>, -- <&cpu19_intc 3>, -- <&cpu20_intc 3>, -- <&cpu21_intc 3>, -- <&cpu22_intc 3>, -- <&cpu23_intc 3>, -- <&cpu24_intc 3>, -- <&cpu25_intc 3>, -- <&cpu26_intc 3>, -- <&cpu27_intc 3>, -- <&cpu28_intc 3>, -- <&cpu29_intc 3>, -- <&cpu30_intc 3>, -- <&cpu31_intc 3>, -- <&cpu32_intc 3>, -- <&cpu33_intc 3>, -- <&cpu34_intc 3>, -- <&cpu35_intc 3>, -- <&cpu36_intc 3>, -- <&cpu37_intc 3>, -- <&cpu38_intc 3>, -- <&cpu39_intc 3>, -- <&cpu40_intc 3>, -- <&cpu41_intc 3>, -- <&cpu42_intc 3>, -- <&cpu43_intc 3>, -- <&cpu44_intc 3>, -- <&cpu45_intc 3>, -- <&cpu46_intc 3>, -- <&cpu47_intc 3>, -- <&cpu48_intc 3>, -- <&cpu49_intc 3>, -- <&cpu50_intc 3>, -- <&cpu51_intc 3>, -- <&cpu52_intc 3>, -- <&cpu53_intc 3>, -- <&cpu54_intc 3>, -- <&cpu55_intc 3>, -- <&cpu56_intc 3>, -- <&cpu57_intc 3>, -- <&cpu58_intc 3>, -- <&cpu59_intc 3>, -- <&cpu60_intc 3>, -- <&cpu61_intc 3>, -- <&cpu62_intc 3>, -- <&cpu63_intc 3>; -- }; -- -- clint_mtimer0: timer@70ac004000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu0_intc 7>, -- <&cpu1_intc 7>, -- <&cpu2_intc 7>, -- <&cpu3_intc 7>; -- }; -- -- clint_mtimer1: timer@70ac014000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu4_intc 7>, -- <&cpu5_intc 7>, -- <&cpu6_intc 7>, -- <&cpu7_intc 7>; -- }; -- -- clint_mtimer2: timer@70ac024000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu8_intc 7>, -- <&cpu9_intc 7>, -- <&cpu10_intc 7>, -- <&cpu11_intc 7>; -- }; -- -- clint_mtimer3: timer@70ac034000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu12_intc 7>, -- <&cpu13_intc 7>, -- <&cpu14_intc 7>, -- <&cpu15_intc 7>; -- }; -- -- clint_mtimer4: timer@70ac044000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu16_intc 7>, -- <&cpu17_intc 7>, -- <&cpu18_intc 7>, -- <&cpu19_intc 7>; -- }; -- -- clint_mtimer5: timer@70ac054000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu20_intc 7>, -- <&cpu21_intc 7>, -- <&cpu22_intc 7>, -- <&cpu23_intc 7>; -- }; -- -- clint_mtimer6: timer@70ac064000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu24_intc 7>, -- <&cpu25_intc 7>, -- <&cpu26_intc 7>, -- <&cpu27_intc 7>; -- }; -- -- clint_mtimer7: timer@70ac074000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu28_intc 7>, -- <&cpu29_intc 7>, -- <&cpu30_intc 7>, -- <&cpu31_intc 7>; -- }; -- -- clint_mtimer8: timer@70ac084000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu32_intc 7>, -- <&cpu33_intc 7>, -- <&cpu34_intc 7>, -- <&cpu35_intc 7>; -- }; -- -- clint_mtimer9: timer@70ac094000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu36_intc 7>, -- <&cpu37_intc 7>, -- <&cpu38_intc 7>, -- <&cpu39_intc 7>; -- }; -- -- clint_mtimer10: timer@70ac0a4000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu40_intc 7>, -- <&cpu41_intc 7>, -- <&cpu42_intc 7>, -- <&cpu43_intc 7>; -- }; -- -- clint_mtimer11: timer@70ac0b4000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu44_intc 7>, -- <&cpu45_intc 7>, -- <&cpu46_intc 7>, -- <&cpu47_intc 7>; -- }; -- -- clint_mtimer12: timer@70ac0c4000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu48_intc 7>, -- <&cpu49_intc 7>, -- <&cpu50_intc 7>, -- <&cpu51_intc 7>; -- }; -- -- clint_mtimer13: timer@70ac0d4000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu52_intc 7>, -- <&cpu53_intc 7>, -- <&cpu54_intc 7>, -- <&cpu55_intc 7>; -- }; -- -- clint_mtimer14: timer@70ac0e4000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu56_intc 7>, -- <&cpu57_intc 7>, -- <&cpu58_intc 7>, -- <&cpu59_intc 7>; -- }; -- -- clint_mtimer15: timer@70ac0f4000 { -- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -- reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; -- reg-names = "mtimecmp"; -- interrupts-extended = <&cpu60_intc 7>, -- <&cpu61_intc 7>, -- <&cpu62_intc 7>, -- <&cpu63_intc 7>; -- }; -- -- intc: interrupt-controller@7090000000 { -- compatible = "sophgo,sg2042-plic", "thead,c900-plic"; -- #address-cells = <0>; -- #interrupt-cells = <2>; -- reg = <0x00000070 0x90000000 0x00000000 0x04000000>; -- interrupt-controller; -- interrupts-extended = -- <&cpu0_intc 11>, <&cpu0_intc 9>, -- <&cpu1_intc 11>, <&cpu1_intc 9>, -- <&cpu2_intc 11>, <&cpu2_intc 9>, -- <&cpu3_intc 11>, <&cpu3_intc 9>, -- <&cpu4_intc 11>, <&cpu4_intc 9>, -- <&cpu5_intc 11>, <&cpu5_intc 9>, -- <&cpu6_intc 11>, <&cpu6_intc 9>, -- <&cpu7_intc 11>, <&cpu7_intc 9>, -- <&cpu8_intc 11>, <&cpu8_intc 9>, -- <&cpu9_intc 11>, <&cpu9_intc 9>, -- <&cpu10_intc 11>, <&cpu10_intc 9>, -- <&cpu11_intc 11>, <&cpu11_intc 9>, -- <&cpu12_intc 11>, <&cpu12_intc 9>, -- <&cpu13_intc 11>, <&cpu13_intc 9>, -- <&cpu14_intc 11>, <&cpu14_intc 9>, -- <&cpu15_intc 11>, <&cpu15_intc 9>, -- <&cpu16_intc 11>, <&cpu16_intc 9>, -- <&cpu17_intc 11>, <&cpu17_intc 9>, -- <&cpu18_intc 11>, <&cpu18_intc 9>, -- <&cpu19_intc 11>, <&cpu19_intc 9>, -- <&cpu20_intc 11>, <&cpu20_intc 9>, -- <&cpu21_intc 11>, <&cpu21_intc 9>, -- <&cpu22_intc 11>, <&cpu22_intc 9>, -- <&cpu23_intc 11>, <&cpu23_intc 9>, -- <&cpu24_intc 11>, <&cpu24_intc 9>, -- <&cpu25_intc 11>, <&cpu25_intc 9>, -- <&cpu26_intc 11>, <&cpu26_intc 9>, -- <&cpu27_intc 11>, <&cpu27_intc 9>, -- <&cpu28_intc 11>, <&cpu28_intc 9>, -- <&cpu29_intc 11>, <&cpu29_intc 9>, -- <&cpu30_intc 11>, <&cpu30_intc 9>, -- <&cpu31_intc 11>, <&cpu31_intc 9>, -- <&cpu32_intc 11>, <&cpu32_intc 9>, -- <&cpu33_intc 11>, <&cpu33_intc 9>, -- <&cpu34_intc 11>, <&cpu34_intc 9>, -- <&cpu35_intc 11>, <&cpu35_intc 9>, -- <&cpu36_intc 11>, <&cpu36_intc 9>, -- <&cpu37_intc 11>, <&cpu37_intc 9>, -- <&cpu38_intc 11>, <&cpu38_intc 9>, -- <&cpu39_intc 11>, <&cpu39_intc 9>, -- <&cpu40_intc 11>, <&cpu40_intc 9>, -- <&cpu41_intc 11>, <&cpu41_intc 9>, -- <&cpu42_intc 11>, <&cpu42_intc 9>, -- <&cpu43_intc 11>, <&cpu43_intc 9>, -- <&cpu44_intc 11>, <&cpu44_intc 9>, -- <&cpu45_intc 11>, <&cpu45_intc 9>, -- <&cpu46_intc 11>, <&cpu46_intc 9>, -- <&cpu47_intc 11>, <&cpu47_intc 9>, -- <&cpu48_intc 11>, <&cpu48_intc 9>, -- <&cpu49_intc 11>, <&cpu49_intc 9>, -- <&cpu50_intc 11>, <&cpu50_intc 9>, -- <&cpu51_intc 11>, <&cpu51_intc 9>, -- <&cpu52_intc 11>, <&cpu52_intc 9>, -- <&cpu53_intc 11>, <&cpu53_intc 9>, -- <&cpu54_intc 11>, <&cpu54_intc 9>, -- <&cpu55_intc 11>, <&cpu55_intc 9>, -- <&cpu56_intc 11>, <&cpu56_intc 9>, -- <&cpu57_intc 11>, <&cpu57_intc 9>, -- <&cpu58_intc 11>, <&cpu58_intc 9>, -- <&cpu59_intc 11>, <&cpu59_intc 9>, -- <&cpu60_intc 11>, <&cpu60_intc 9>, -- <&cpu61_intc 11>, <&cpu61_intc 9>, -- <&cpu62_intc 11>, <&cpu62_intc 9>, -- <&cpu63_intc 11>, <&cpu63_intc 9>; -- riscv,ndev = <224>; -- }; -- - rstgen: reset-controller@7030013000 { - compatible = "sophgo,sg2042-reset"; - reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch b/SPECS/linux-lts/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch new file mode 100644 index 0000000000..1a8e836f5a --- /dev/null +++ b/SPECS/linux-lts/0075-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch @@ -0,0 +1,51 @@ +From 4274a55a8dac98543297e2416ea7c7f40c4f641a Mon Sep 17 00:00:00 2001 +From: Javier Martinez Canillas +Date: Sat, 6 Dec 2025 14:44:54 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Define fixed regulators + for Milk-V Jupiter + +Define the DC power input and the 4v power as fixed regulator supplies. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20251206134532.1741648-3-javierm@redhat.com +Signed-off-by: Yixun Lan +(cherry picked from commit ae9d03f8aec76c1bff21083b67c211238d7c57b1) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index aa425f02c1f4..5babed4d7094 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -20,6 +20,25 @@ aliases { + chosen { + stdout-path = "serial0"; + }; ++ ++ reg_dc_in: dc-in-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_in_12v"; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_vcc_4v: vcc-4v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_4v"; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <®_dc_in>; ++ }; + }; + + ð0 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0076-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch b/SPECS/linux-lts/0076-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch deleted file mode 100644 index 568815bda9..0000000000 --- a/SPECS/linux-lts/0076-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch +++ /dev/null @@ -1,216 +0,0 @@ -From bc212a22b04c56496e4f069f7f3fca8cffd37025 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Tue, 13 Jan 2026 10:38:27 +0800 -Subject: [PATCH 076/467] UPSTREAM: riscv: dts: sophgo: fix the node order of - SG2042 peripheral - -In sg2042.dtsi, some peripheral device node does not follow the -address order. Reorder them in ascending order by address. - -Reviewed-by: Chen Wang -Link: https://lore.kernel.org/r/20260113023828.790136-2-inochiama@gmail.com -Signed-off-by: Inochi Amaoto -Signed-off-by: Chen Wang -Signed-off-by: Chen Wang -(cherry picked from commit ebb87dd74c34a76e1e93041e9329cf9269be35ed) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042.dtsi | 176 ++++++++++++------------- - 1 file changed, 88 insertions(+), 88 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -index e6891f95d479..9fddf3f0b3b9 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -@@ -264,94 +264,6 @@ clkgen: clock-controller@7030012000 { - #clock-cells = <1>; - }; - -- pcie_rc0: pcie@7060000000 { -- compatible = "sophgo,sg2042-pcie-host"; -- device_type = "pci"; -- reg = <0x70 0x60000000 0x0 0x00800000>, -- <0x40 0x00000000 0x0 0x00001000>; -- reg-names = "reg", "cfg"; -- linux,pci-domain = <0>; -- #address-cells = <3>; -- #size-cells = <2>; -- ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, -- <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, -- <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, -- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, -- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; -- bus-range = <0x0 0xff>; -- vendor-id = <0x1f1c>; -- device-id = <0x2042>; -- cdns,no-bar-match-nbits = <48>; -- msi-parent = <&msi>; -- status = "disabled"; -- }; -- -- pcie_rc1: pcie@7060800000 { -- compatible = "sophgo,sg2042-pcie-host"; -- device_type = "pci"; -- reg = <0x70 0x60800000 0x0 0x00800000>, -- <0x44 0x00000000 0x0 0x00001000>; -- reg-names = "reg", "cfg"; -- linux,pci-domain = <1>; -- #address-cells = <3>; -- #size-cells = <2>; -- ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, -- <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, -- <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, -- <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, -- <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; -- bus-range = <0x0 0xff>; -- vendor-id = <0x1f1c>; -- device-id = <0x2042>; -- cdns,no-bar-match-nbits = <48>; -- msi-parent = <&msi>; -- status = "disabled"; -- }; -- -- pcie_rc2: pcie@7062000000 { -- compatible = "sophgo,sg2042-pcie-host"; -- device_type = "pci"; -- reg = <0x70 0x62000000 0x0 0x00800000>, -- <0x48 0x00000000 0x0 0x00001000>; -- reg-names = "reg", "cfg"; -- linux,pci-domain = <2>; -- #address-cells = <3>; -- #size-cells = <2>; -- ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, -- <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, -- <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, -- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, -- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; -- bus-range = <0x0 0xff>; -- vendor-id = <0x1f1c>; -- device-id = <0x2042>; -- cdns,no-bar-match-nbits = <48>; -- msi-parent = <&msi>; -- status = "disabled"; -- }; -- -- pcie_rc3: pcie@7062800000 { -- compatible = "sophgo,sg2042-pcie-host"; -- device_type = "pci"; -- reg = <0x70 0x62800000 0x0 0x00800000>, -- <0x4c 0x00000000 0x0 0x00001000>; -- reg-names = "reg", "cfg"; -- linux,pci-domain = <3>; -- #address-cells = <3>; -- #size-cells = <2>; -- ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, -- <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, -- <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, -- <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, -- <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; -- bus-range = <0x0 0xff>; -- vendor-id = <0x1f1c>; -- device-id = <0x2042>; -- cdns,no-bar-match-nbits = <48>; -- msi-parent = <&msi>; -- status = "disabled"; -- }; -- - rstgen: reset-controller@7030013000 { - compatible = "sophgo,sg2042-reset"; - reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; -@@ -486,5 +398,93 @@ sd: mmc@704002b000 { - "timer"; - status = "disabled"; - }; -+ -+ pcie_rc0: pcie@7060000000 { -+ compatible = "sophgo,sg2042-pcie-host"; -+ device_type = "pci"; -+ reg = <0x70 0x60000000 0x0 0x00800000>, -+ <0x40 0x00000000 0x0 0x00001000>; -+ reg-names = "reg", "cfg"; -+ linux,pci-domain = <0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, -+ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, -+ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, -+ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, -+ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; -+ bus-range = <0x0 0xff>; -+ vendor-id = <0x1f1c>; -+ device-id = <0x2042>; -+ cdns,no-bar-match-nbits = <48>; -+ msi-parent = <&msi>; -+ status = "disabled"; -+ }; -+ -+ pcie_rc1: pcie@7060800000 { -+ compatible = "sophgo,sg2042-pcie-host"; -+ device_type = "pci"; -+ reg = <0x70 0x60800000 0x0 0x00800000>, -+ <0x44 0x00000000 0x0 0x00001000>; -+ reg-names = "reg", "cfg"; -+ linux,pci-domain = <1>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, -+ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, -+ <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, -+ <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, -+ <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; -+ bus-range = <0x0 0xff>; -+ vendor-id = <0x1f1c>; -+ device-id = <0x2042>; -+ cdns,no-bar-match-nbits = <48>; -+ msi-parent = <&msi>; -+ status = "disabled"; -+ }; -+ -+ pcie_rc2: pcie@7062000000 { -+ compatible = "sophgo,sg2042-pcie-host"; -+ device_type = "pci"; -+ reg = <0x70 0x62000000 0x0 0x00800000>, -+ <0x48 0x00000000 0x0 0x00001000>; -+ reg-names = "reg", "cfg"; -+ linux,pci-domain = <2>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, -+ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, -+ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, -+ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, -+ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; -+ bus-range = <0x0 0xff>; -+ vendor-id = <0x1f1c>; -+ device-id = <0x2042>; -+ cdns,no-bar-match-nbits = <48>; -+ msi-parent = <&msi>; -+ status = "disabled"; -+ }; -+ -+ pcie_rc3: pcie@7062800000 { -+ compatible = "sophgo,sg2042-pcie-host"; -+ device_type = "pci"; -+ reg = <0x70 0x62800000 0x0 0x00800000>, -+ <0x4c 0x00000000 0x0 0x00001000>; -+ reg-names = "reg", "cfg"; -+ linux,pci-domain = <3>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, -+ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, -+ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, -+ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, -+ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; -+ bus-range = <0x0 0xff>; -+ vendor-id = <0x1f1c>; -+ device-id = <0x2042>; -+ cdns,no-bar-match-nbits = <48>; -+ msi-parent = <&msi>; -+ status = "disabled"; -+ }; - }; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux-lts/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch new file mode 100644 index 0000000000..1be8407564 --- /dev/null +++ b/SPECS/linux-lts/0076-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch @@ -0,0 +1,145 @@ +From 0af31fdff636f13c96b48c14fe2dce73dbf55dfd Mon Sep 17 00:00:00 2001 +From: Javier Martinez Canillas +Date: Sat, 6 Dec 2025 14:44:55 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Define the P1 PMIC + regulators for Milk-V Jupiter + +Define the SpacemiT P1 PMIC voltage regulators and their constraints. + +The power management hardware design on the Milk-V Jupiter is identical to +the Banana Pi BPI-F3, so the DT Nodes were taken from k1-bananapi-f3.dts. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20251206134532.1741648-4-javierm@redhat.com +Signed-off-by: Yixun Lan +(cherry picked from commit 7d307daa12b15a97269f577d5dcf50518758b568) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 110 ++++++++++++++++++ + 1 file changed, 110 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 5babed4d7094..800a112d5d70 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -95,6 +95,116 @@ &i2c8 { + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; + status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ vin-supply = <®_vcc_4v>; ++ ++ regulators { ++ buck1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3_1v8: buck3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ aldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ dldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo7 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ }; ++ }; + }; + + &uart0 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch b/SPECS/linux-lts/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch new file mode 100644 index 0000000000..51bfee722a --- /dev/null +++ b/SPECS/linux-lts/0077-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch @@ -0,0 +1,152 @@ +From 0cb6f99b1dee1c78c2cb66de8612480e505be4b7 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Thu, 18 Dec 2025 09:12:27 -0600 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: Add SpacemiT + PCIe/combo PHY + +Add the Device Tree binding for the PCIe/USB 3.0 combo PHY found in +the SpacemiT K1 SoC. This is one of three PCIe PHYs, and is unusual +in that only the combo PHY can perform a calibration step needed to +determine settings used by the other two PCIe PHYs. + +Calibration must be done with the combo PHY in PCIe mode, and to allow +this to occur independent of the eventual use for the PHY (PCIe or USB) +some PCIe-related properties must be supplied: clocks; resets; and a +syscon phandle. + +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Alex Elder +Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1] +Tested-by: Yixun Lan +Link: https://patch.msgid.link/20251218151235.454997-2-elder@riscstar.com +Signed-off-by: Vinod Koul +(cherry picked from commit f6194de7df023ecfd5156caf8e2762487be07ef7) +Signed-off-by: Han Gao +--- + .../bindings/phy/spacemit,k1-combo-phy.yaml | 114 ++++++++++++++++++ + 1 file changed, 114 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml +new file mode 100644 +index 000000000000..b59476cd78b5 +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml +@@ -0,0 +1,114 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 PCIe/USB3 Combo PHY ++ ++maintainers: ++ - Alex Elder ++ ++description: > ++ Of the three PHYs on the SpacemiT K1 SoC capable of being used for ++ PCIe, one is a combo PHY that can also be configured for use by a ++ USB 3 controller. Using PCIe or USB 3 is a board design decision. ++ ++ The combo PHY is also the only PCIe PHY that is able to determine ++ PCIe calibration values to use, and this must be determined before ++ the other two PCIe PHYs can be used. This calibration must be ++ performed with the combo PHY in PCIe mode, and is this is done ++ when the combo PHY is probed. ++ ++ The combo PHY uses an external oscillator as a reference clock. ++ During normal operation, the PCIe or USB port driver is responsible ++ for ensuring all other clocks needed by a PHY are enabled, and all ++ resets affecting the PHY are deasserted. However, for the combo ++ PHY to perform calibration independent of whether it's later used ++ for PCIe or USB, all PCIe mode clocks and resets must be defined. ++ ++properties: ++ compatible: ++ const: spacemit,k1-combo-phy ++ ++ reg: ++ items: ++ - description: PHY control registers ++ ++ clocks: ++ items: ++ - description: External oscillator used by the PHY PLL ++ - description: DWC PCIe Data Bus Interface (DBI) clock ++ - description: DWC PCIe application AXI-bus Master interface clock ++ - description: DWC PCIe application AXI-bus slave interface clock ++ ++ clock-names: ++ items: ++ - const: refclk ++ - const: dbi ++ - const: mstr ++ - const: slv ++ ++ resets: ++ items: ++ - description: PHY reset; remains deasserted after initialization ++ - description: DWC PCIe Data Bus Interface (DBI) reset ++ - description: DWC PCIe application AXI-bus Master interface reset ++ - description: DWC PCIe application AXI-bus slave interface reset ++ ++ reset-names: ++ items: ++ - const: phy ++ - const: dbi ++ - const: mstr ++ - const: slv ++ ++ spacemit,apmu: ++ description: ++ A phandle that refers to the APMU system controller, whose ++ regmap is used in setting the mode ++ $ref: /schemas/types.yaml#/definitions/phandle ++ ++ "#phy-cells": ++ const: 1 ++ description: ++ The argument value (PHY_TYPE_PCIE or PHY_TYPE_USB3) determines ++ whether the PHY operates in PCIe or USB3 mode. ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - spacemit,apmu ++ - "#phy-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ phy@c0b10000 { ++ compatible = "spacemit,k1-combo-phy"; ++ reg = <0xc0b10000 0x1000>; ++ clocks = <&vctcxo_24m>, ++ <&syscon_apmu CLK_PCIE0_DBI>, ++ <&syscon_apmu CLK_PCIE0_MASTER>, ++ <&syscon_apmu CLK_PCIE0_SLAVE>; ++ clock-names = "refclk", ++ "dbi", ++ "mstr", ++ "slv"; ++ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, ++ <&syscon_apmu RESET_PCIE0_DBI>, ++ <&syscon_apmu RESET_PCIE0_MASTER>, ++ <&syscon_apmu RESET_PCIE0_SLAVE>; ++ reset-names = "phy", ++ "dbi", ++ "mstr", ++ "slv"; ++ spacemit,apmu = <&syscon_apmu>; ++ #phy-cells = <1>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0077-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux-lts/0077-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch deleted file mode 100644 index 7f626bb434..0000000000 --- a/SPECS/linux-lts/0077-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 424c28f6634db764db1cd2faa2f13e276f698b61 Mon Sep 17 00:00:00 2001 -From: Javier Martinez Canillas -Date: Sat, 6 Dec 2025 14:44:53 +0100 -Subject: [PATCH 077/467] UPSTREAM: riscv: dts: spacemit: Enable i2c8 adapter - for Milk-V Jupiter - -The adapter is used to access the SpacemiT P1 PMIC present in this board. - -Signed-off-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20251206134532.1741648-2-javierm@redhat.com -Signed-off-by: Yixun Lan -(cherry picked from commit f33ccc2316304f3a71e40e53f1568e75042b0a4b) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 28afd39b28da..aa425f02c1f4 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -72,6 +72,12 @@ &pdma { - status = "okay"; - }; - -+&i2c8 { -+ pinctrl-0 = <&i2c8_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch b/SPECS/linux-lts/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch new file mode 100644 index 0000000000..9b069cb469 --- /dev/null +++ b/SPECS/linux-lts/0078-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch @@ -0,0 +1,103 @@ +From 69d5a6d06db546fbe5f911a20eff130b7eb44927 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Thu, 18 Dec 2025 09:12:28 -0600 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: Introduce PCIe PHY + +Add the Device Tree binding for two PCIe PHYs present on the SpacemiT +K1 SoC. These PHYs are dependent on a separate combo PHY, which +determines at probe time the calibration values used by the PCIe-only +PHYs. + +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Alex Elder +Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1] +Tested-by: Yixun Lan +Link: https://patch.msgid.link/20251218151235.454997-3-elder@riscstar.com +Signed-off-by: Vinod Koul +(cherry picked from commit 326a278a3682d390269699f68e597b5ef5a57d26) +Signed-off-by: Han Gao +--- + .../bindings/phy/spacemit,k1-pcie-phy.yaml | 71 +++++++++++++++++++ + 1 file changed, 71 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml +new file mode 100644 +index 000000000000..019b28349be7 +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml +@@ -0,0 +1,71 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 PCIe PHY ++ ++maintainers: ++ - Alex Elder ++ ++description: > ++ Two PHYs on the SpacemiT K1 SoC used for only for PCIe. These ++ PHYs must be configured using calibration values that are ++ determined by a third "combo PHY". The combo PHY determines ++ these calibration values during probe so they can be used for ++ the two PCIe-only PHYs. ++ ++ The PHY uses an external oscillator as a reference clock. During ++ normal operation, the PCIe host driver is responsible for ensuring ++ all other clocks needed by a PHY are enabled, and all resets ++ affecting the PHY are deasserted. ++ ++properties: ++ compatible: ++ const: spacemit,k1-pcie-phy ++ ++ reg: ++ items: ++ - description: PHY control registers ++ ++ clocks: ++ items: ++ - description: External oscillator used by the PHY PLL ++ ++ clock-names: ++ const: refclk ++ ++ resets: ++ items: ++ - description: PHY reset; remains deasserted after initialization ++ ++ reset-names: ++ const: phy ++ ++ "#phy-cells": ++ const: 0 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - "#phy-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ phy@c0c10000 { ++ compatible = "spacemit,k1-pcie-phy"; ++ reg = <0xc0c10000 0x1000>; ++ clocks = <&vctcxo_24m>; ++ clock-names = "refclk"; ++ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; ++ reset-names = "phy"; ++ #phy-cells = <0>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0078-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch b/SPECS/linux-lts/0078-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch deleted file mode 100644 index 707ca5b47b..0000000000 --- a/SPECS/linux-lts/0078-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 02cddb709249c02e0e30f24ad102a5b7190d26c2 Mon Sep 17 00:00:00 2001 -From: Javier Martinez Canillas -Date: Sat, 6 Dec 2025 14:44:54 +0100 -Subject: [PATCH 078/467] UPSTREAM: riscv: dts: spacemit: Define fixed - regulators for Milk-V Jupiter - -Define the DC power input and the 4v power as fixed regulator supplies. - -Signed-off-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20251206134532.1741648-3-javierm@redhat.com -Signed-off-by: Yixun Lan -(cherry picked from commit ae9d03f8aec76c1bff21083b67c211238d7c57b1) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index aa425f02c1f4..5babed4d7094 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -20,6 +20,25 @@ aliases { - chosen { - stdout-path = "serial0"; - }; -+ -+ reg_dc_in: dc-in-12v { -+ compatible = "regulator-fixed"; -+ regulator-name = "dc_in_12v"; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_vcc_4v: vcc-4v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_4v"; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <®_dc_in>; -+ }; - }; - - ð0 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch b/SPECS/linux-lts/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch new file mode 100644 index 0000000000..78fc295801 --- /dev/null +++ b/SPECS/linux-lts/0079-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch @@ -0,0 +1,758 @@ +From ec3144e3a9c21e5c60712fe8b72eb68e9f8c120f Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Thu, 18 Dec 2025 09:12:29 -0600 +Subject: [RUYI PATCH] UPSTREAM: phy: spacemit: Introduce PCIe/combo PHY + +Introduce a driver that supports three PHYs found on the SpacemiT +K1 SoC. The first PHY is a combo PHY that can be configured for +use for either USB 3 or PCIe. The other two PHYs support PCIe +only. + +All three PHYs must be programmed with an 8 bit receiver termination +value, which must be determined dynamically. Only the combo PHY is +able to determine this value. The combo PHY performs a special +calibration step at probe time to discover this, and that value is +used to program each PHY that operates in PCIe mode. The combo +PHY must therefore be probed before either of the PCIe-only PHYs +will be used. + +Each PHY has an internal PLL driven from an external oscillator. +This PLL started when the PHY is first initialized, and stays +on thereafter. + +During normal operation, the USB or PCIe driver using the PHY must +ensure (other) clocks and resets are set up properly. + +However PCIe mode clocks are enabled and resets are de-asserted +temporarily by this driver to perform the calibration step on the +combo PHY. + +Tested-by: Junzhong Pan +Signed-off-by: Alex Elder +Reviewed-by: Neil Armstrong +Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1] +Tested-by: Yixun Lan +Link: https://patch.msgid.link/20251218151235.454997-4-elder@riscstar.com +Signed-off-by: Vinod Koul +(cherry picked from commit 57e920b92724dd568526990c04e79ed54241c5fc) +Signed-off-by: Han Gao +--- + drivers/phy/Kconfig | 11 + + drivers/phy/Makefile | 1 + + drivers/phy/phy-spacemit-k1-pcie.c | 670 +++++++++++++++++++++++++++++ + 3 files changed, 682 insertions(+) + create mode 100644 drivers/phy/phy-spacemit-k1-pcie.c + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index 678dd0452f0a..1984c2e56122 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -101,6 +101,17 @@ config PHY_NXP_PTN3222 + schemes. It supports all three USB 2.0 data rates: Low Speed, Full + Speed and High Speed. + ++config PHY_SPACEMIT_K1_PCIE ++ tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC" ++ depends on ARCH_SPACEMIT || COMPILE_TEST ++ depends on HAS_IOMEM ++ depends on OF ++ select GENERIC_PHY ++ default ARCH_SPACEMIT ++ help ++ Enable support for the PCIe and USB 3 combo PHY and two ++ PCIe-only PHYs used in the SpacemiT K1 SoC. ++ + source "drivers/phy/allwinner/Kconfig" + source "drivers/phy/amlogic/Kconfig" + source "drivers/phy/broadcom/Kconfig" +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index bfb27fb5a494..a206133a3515 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o + obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o + obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o + obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o ++obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-spacemit-k1-pcie.o + obj-y += allwinner/ \ + amlogic/ \ + broadcom/ \ +diff --git a/drivers/phy/phy-spacemit-k1-pcie.c b/drivers/phy/phy-spacemit-k1-pcie.c +new file mode 100644 +index 000000000000..75477bea7f70 +--- /dev/null ++++ b/drivers/phy/phy-spacemit-k1-pcie.c +@@ -0,0 +1,670 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * SpacemiT K1 PCIe and PCIe/USB 3 combo PHY driver ++ * ++ * Copyright (C) 2025 by RISCstar Solutions Corporation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* ++ * Three PCIe ports are supported in the SpacemiT K1 SoC, and this driver ++ * supports their PHYs. ++ * ++ * The PHY for PCIe port A is different from the PHYs for ports B and C: ++ * - It has one lane, while ports B and C have two ++ * - It is a combo PHY can be used for PCIe or USB 3 ++ * - It can automatically calibrate PCIe TX and RX termination settings ++ * ++ * The PHY functionality for PCIe ports B and C is identical: ++ * - They have two PCIe lanes (but can be restricted to 1 via device tree) ++ * - They are used for PCIe only ++ * - They are configured using TX and RX values computed for port A ++ * ++ * A given board is designed to use the combo PHY for either PCIe or USB 3. ++ * Whether the combo PHY is configured for PCIe or USB 3 is specified in ++ * device tree using a phandle plus an argument. The argument indicates ++ * the type (either PHY_TYPE_PCIE or PHY_TYPE_USB3). ++ * ++ * Each PHY has a reset that it gets and deasserts during initialization. ++ * Each depends also on other clocks and resets provided by the controller ++ * hardware (PCIe or USB) it is associated with. The controller drivers ++ * are required to enable any clocks and de-assert any resets that affect ++ * PHY operation. In addition each PHY implements an internal PLL, driven ++ * by an external (24 MHz) oscillator. ++ * ++ * PCIe PHYs must be programmed with RX and TX calibration values. The ++ * combo PHY is the only one that can determine these values. They are ++ * determined by temporarily enabling the combo PHY in PCIe mode at probe ++ * time (if necessary). This calibration only needs to be done once, and ++ * when it has completed the TX and RX values are saved. ++ * ++ * To allow the combo PHY to be enabled for calibration, the resets and ++ * clocks it uses in PCIe mode must be supplied. ++ */ ++ ++struct k1_pcie_phy { ++ struct device *dev; /* PHY provider device */ ++ struct phy *phy; ++ void __iomem *regs; ++ u32 pcie_lanes; /* Max (1 or 2) unless limited by DT */ ++ struct clk *pll; ++ struct clk_hw pll_hw; /* Private PLL clock */ ++ ++ /* The remaining fields are only used for the combo PHY */ ++ u32 type; /* PHY_TYPE_PCIE or PHY_TYPE_USB3 */ ++ struct regmap *pmu; /* MMIO regmap (no errors) */ ++}; ++ ++#define CALIBRATION_TIMEOUT 500000 /* For combo PHY (usec) */ ++#define PLL_TIMEOUT 500000 /* For PHY PLL lock (usec) */ ++#define POLL_DELAY 500 /* Time between polls (usec) */ ++ ++/* Selecting the combo PHY operating mode requires APMU regmap access */ ++#define SYSCON_APMU "spacemit,apmu" ++ ++/* PMU space, for selecting between PCIe and USB 3 mode (combo PHY only) */ ++ ++#define PMUA_USB_PHY_CTRL0 0x0110 ++#define COMBO_PHY_SEL BIT(3) /* 0: PCIe; 1: USB 3 */ ++ ++#define PCIE_CLK_RES_CTRL 0x03cc ++#define PCIE_APP_HOLD_PHY_RST BIT(30) ++ ++/* PHY register space */ ++ ++/* Offset between lane 0 and lane 1 registers when there are two */ ++#define PHY_LANE_OFFSET 0x0400 ++ ++/* PHY PLL configuration */ ++#define PCIE_PU_ADDR_CLK_CFG 0x0008 ++#define PLL_READY BIT(0) /* read-only */ ++#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) ++#define TIMER_ADJ_USB 0x2 ++#define TIMER_ADJ_PCIE 0x6 ++#define CFG_SW_PHY_INIT_DONE BIT(11) /* We set after PLL config */ ++ ++#define PCIE_RC_DONE_STATUS 0x0018 ++#define CFG_FORCE_RCV_RETRY BIT(10) /* Used for PCIe */ ++ ++/* PCIe PHY lane calibration; assumes 24MHz input clock */ ++#define PCIE_RC_CAL_REG2 0x0020 ++#define RC_CAL_TOGGLE BIT(22) ++#define CLKSEL GENMASK(31, 29) ++#define CLKSEL_24M 0x3 ++ ++/* Additional PHY PLL configuration (USB 3 and PCIe) */ ++#define PCIE_PU_PLL_1 0x0048 ++#define REF_100_WSSC BIT(12) /* 1: input is 100MHz, SSC */ ++#define FREF_SEL GENMASK(15, 13) ++#define FREF_24M 0x1 ++#define SSC_DEP_SEL GENMASK(19, 16) ++#define SSC_DEP_NONE 0x0 ++#define SSC_DEP_5000PPM 0xa ++ ++/* PCIe PHY configuration */ ++#define PCIE_PU_PLL_2 0x004c ++#define GEN_REF100 BIT(4) /* 1: generate 100MHz clk */ ++ ++#define PCIE_RX_REG1 0x0050 ++#define EN_RTERM BIT(3) ++#define AFE_RTERM_REG GENMASK(11, 8) ++ ++#define PCIE_RX_REG2 0x0054 ++#define RX_RTERM_SEL BIT(5) /* 0: use AFE_RTERM_REG value */ ++ ++#define PCIE_LTSSM_DIS_ENTRY 0x005c ++#define CFG_REFCLK_MODE GENMASK(9, 8) ++#define RFCLK_MODE_DRIVER 0x1 ++#define OVRD_REFCLK_MODE BIT(10) /* 1: use CFG_RFCLK_MODE */ ++ ++#define PCIE_TX_REG1 0x0064 ++#define TX_RTERM_REG GENMASK(15, 12) ++#define TX_RTERM_SEL BIT(25) /* 1: use TX_RTERM_REG */ ++ ++/* Zeroed for the combo PHY operating in USB mode */ ++#define USB3_TEST_CTRL 0x0068 ++ ++/* PHY calibration values, determined by the combo PHY at probe time */ ++#define PCIE_RCAL_RESULT 0x0084 /* Port A PHY only */ ++#define RTERM_VALUE_RX GENMASK(3, 0) ++#define RTERM_VALUE_TX GENMASK(7, 4) ++#define R_TUNE_DONE BIT(10) ++ ++static u32 k1_phy_rterm = ~0; /* Invalid initial value */ ++ ++/* Save the RX and TX receiver termination values */ ++static void k1_phy_rterm_set(u32 val) ++{ ++ k1_phy_rterm = val & (RTERM_VALUE_RX | RTERM_VALUE_TX); ++} ++ ++static bool k1_phy_rterm_valid(void) ++{ ++ /* Valid if no bits outside those we care about are set */ ++ return !(k1_phy_rterm & ~(RTERM_VALUE_RX | RTERM_VALUE_TX)); ++} ++ ++static u32 k1_phy_rterm_rx(void) ++{ ++ return FIELD_GET(RTERM_VALUE_RX, k1_phy_rterm); ++} ++ ++static u32 k1_phy_rterm_tx(void) ++{ ++ return FIELD_GET(RTERM_VALUE_TX, k1_phy_rterm); ++} ++ ++/* Only the combo PHY has a PMU pointer defined */ ++static bool k1_phy_port_a(struct k1_pcie_phy *k1_phy) ++{ ++ return !!k1_phy->pmu; ++} ++ ++/* The PLL clocks are driven by the external oscillator */ ++static const struct clk_parent_data k1_pcie_phy_data[] = { ++ { .fw_name = "refclk", }, ++}; ++ ++static struct k1_pcie_phy *clk_hw_to_k1_phy(struct clk_hw *clk_hw) ++{ ++ return container_of(clk_hw, struct k1_pcie_phy, pll_hw); ++} ++ ++/* USB mode only works on the combo PHY, which has only one lane */ ++static void k1_pcie_phy_pll_prepare_usb(struct k1_pcie_phy *k1_phy) ++{ ++ void __iomem *regs = k1_phy->regs; ++ u32 val; ++ ++ val = readl(regs + PCIE_PU_ADDR_CLK_CFG); ++ val &= ~CFG_INTERNAL_TIMER_ADJ; ++ val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_USB); ++ writel(val, regs + PCIE_PU_ADDR_CLK_CFG); ++ ++ val = readl(regs + PCIE_PU_PLL_1); ++ val &= ~SSC_DEP_SEL; ++ val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_5000PPM); ++ writel(val, regs + PCIE_PU_PLL_1); ++} ++ ++/* Perform PCIe-specific register updates before starting the PLL clock */ ++static void k1_pcie_phy_pll_prepare_pcie(struct k1_pcie_phy *k1_phy) ++{ ++ void __iomem *regs = k1_phy->regs; ++ u32 val; ++ u32 i; ++ ++ for (i = 0; i < k1_phy->pcie_lanes; i++) { ++ val = readl(regs + PCIE_PU_ADDR_CLK_CFG); ++ val &= ~CFG_INTERNAL_TIMER_ADJ; ++ val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_PCIE); ++ writel(val, regs + PCIE_PU_ADDR_CLK_CFG); ++ ++ regs += PHY_LANE_OFFSET; /* Next lane */ ++ } ++ ++ regs = k1_phy->regs; ++ val = readl(regs + PCIE_RC_DONE_STATUS); ++ val |= CFG_FORCE_RCV_RETRY; ++ writel(val, regs + PCIE_RC_DONE_STATUS); ++ ++ val = readl(regs + PCIE_PU_PLL_1); ++ val &= ~SSC_DEP_SEL; ++ val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_NONE); ++ writel(val, regs + PCIE_PU_PLL_1); ++ ++ val = readl(regs + PCIE_PU_PLL_2); ++ val |= GEN_REF100; /* Enable 100 MHz PLL output clock */ ++ writel(val, regs + PCIE_PU_PLL_2); ++} ++ ++static int k1_pcie_phy_pll_prepare(struct clk_hw *clk_hw) ++{ ++ struct k1_pcie_phy *k1_phy = clk_hw_to_k1_phy(clk_hw); ++ void __iomem *regs = k1_phy->regs; ++ u32 val; ++ u32 i; ++ ++ if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3) ++ k1_pcie_phy_pll_prepare_usb(k1_phy); ++ else ++ k1_pcie_phy_pll_prepare_pcie(k1_phy); ++ ++ /* ++ * Disable 100 MHz input reference with spread-spectrum ++ * clocking and select the 24 MHz clock input frequency ++ */ ++ val = readl(regs + PCIE_PU_PLL_1); ++ val &= ~REF_100_WSSC; ++ val &= ~FREF_SEL; ++ val |= FIELD_PREP(FREF_SEL, FREF_24M); ++ writel(val, regs + PCIE_PU_PLL_1); ++ ++ /* Mark PLL configuration done on all lanes */ ++ for (i = 0; i < k1_phy->pcie_lanes; i++) { ++ val = readl(regs + PCIE_PU_ADDR_CLK_CFG); ++ val |= CFG_SW_PHY_INIT_DONE; ++ writel(val, regs + PCIE_PU_ADDR_CLK_CFG); ++ ++ regs += PHY_LANE_OFFSET; /* Next lane */ ++ } ++ ++ /* ++ * Wait for indication the PHY PLL is locked. Lanes for ports ++ * B and C share a PLL, so it's enough to sample just lane 0. ++ */ ++ return readl_poll_timeout(k1_phy->regs + PCIE_PU_ADDR_CLK_CFG, ++ val, val & PLL_READY, ++ POLL_DELAY, PLL_TIMEOUT); ++} ++ ++/* Prepare implies enable, and once enabled, it's always on */ ++static const struct clk_ops k1_pcie_phy_pll_ops = { ++ .prepare = k1_pcie_phy_pll_prepare, ++}; ++ ++/* We represent the PHY PLL as a private clock */ ++static int k1_pcie_phy_pll_setup(struct k1_pcie_phy *k1_phy) ++{ ++ struct clk_hw *hw = &k1_phy->pll_hw; ++ struct device *dev = k1_phy->dev; ++ struct clk_init_data init = { }; ++ char *name; ++ int ret; ++ ++ name = kasprintf(GFP_KERNEL, "pcie%u_phy_pll", k1_phy->phy->id); ++ if (!name) ++ return -ENOMEM; ++ ++ init.name = name; ++ init.ops = &k1_pcie_phy_pll_ops; ++ init.parent_data = k1_pcie_phy_data; ++ init.num_parents = ARRAY_SIZE(k1_pcie_phy_data); ++ ++ hw->init = &init; ++ ++ ret = devm_clk_hw_register(dev, hw); ++ ++ kfree(name); /* __clk_register() duplicates the name we provide */ ++ ++ if (ret) ++ return ret; ++ ++ k1_phy->pll = devm_clk_hw_get_clk(dev, hw, "pll"); ++ if (IS_ERR(k1_phy->pll)) ++ return PTR_ERR(k1_phy->pll); ++ ++ return 0; ++} ++ ++/* Select PCIe or USB 3 mode for the combo PHY. */ ++static void k1_combo_phy_sel(struct k1_pcie_phy *k1_phy, bool usb) ++{ ++ struct regmap *pmu = k1_phy->pmu; ++ ++ /* Only change it if it's not already in the desired state */ ++ if (!regmap_test_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL) == usb) ++ regmap_assign_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL, usb); ++} ++ ++static void k1_pcie_phy_init_pcie(struct k1_pcie_phy *k1_phy) ++{ ++ u32 rx_rterm = k1_phy_rterm_rx(); ++ u32 tx_rterm = k1_phy_rterm_tx(); ++ void __iomem *regs; ++ u32 val; ++ int i; ++ ++ /* For the combo PHY, set PHY to PCIe mode */ ++ if (k1_phy_port_a(k1_phy)) ++ k1_combo_phy_sel(k1_phy, false); ++ ++ regs = k1_phy->regs; ++ for (i = 0; i < k1_phy->pcie_lanes; i++) { ++ val = readl(regs + PCIE_RX_REG1); ++ ++ /* Set RX analog front-end receiver termination value */ ++ val &= ~AFE_RTERM_REG; ++ val |= FIELD_PREP(AFE_RTERM_REG, rx_rterm); ++ ++ /* And enable refclock receiver termination */ ++ val |= EN_RTERM; ++ writel(val, regs + PCIE_RX_REG1); ++ ++ val = readl(regs + PCIE_RX_REG2); ++ /* Use PCIE_RX_REG1 AFE_RTERM_REG value */ ++ val &= ~RX_RTERM_SEL; ++ writel(val, regs + PCIE_RX_REG2); ++ ++ val = readl(regs + PCIE_TX_REG1); ++ ++ /* Set TX driver termination value */ ++ val &= ~TX_RTERM_REG; ++ val |= FIELD_PREP(TX_RTERM_REG, tx_rterm); ++ ++ /* Use PCIE_TX_REG1 TX_RTERM_REG value */ ++ val |= TX_RTERM_SEL; ++ writel(val, regs + PCIE_TX_REG1); ++ ++ /* Set the input clock to 24 MHz, and clear RC_CAL_TOGGLE */ ++ val = readl(regs + PCIE_RC_CAL_REG2); ++ val &= CLKSEL; ++ val |= FIELD_PREP(CLKSEL, CLKSEL_24M); ++ val &= ~RC_CAL_TOGGLE; ++ writel(val, regs + PCIE_RC_CAL_REG2); ++ ++ /* Now trigger recalibration by setting RC_CAL_TOGGLE again */ ++ val |= RC_CAL_TOGGLE; ++ writel(val, regs + PCIE_RC_CAL_REG2); ++ ++ val = readl(regs + PCIE_LTSSM_DIS_ENTRY); ++ /* Override the reference clock; set to refclk driver mode */ ++ val |= OVRD_REFCLK_MODE; ++ val &= ~CFG_REFCLK_MODE; ++ val |= FIELD_PREP(CFG_REFCLK_MODE, RFCLK_MODE_DRIVER); ++ writel(val, regs + PCIE_LTSSM_DIS_ENTRY); ++ ++ regs += PHY_LANE_OFFSET; /* Next lane */ ++ } ++} ++ ++/* Only called for combo PHY */ ++static void k1_pcie_phy_init_usb(struct k1_pcie_phy *k1_phy) ++{ ++ k1_combo_phy_sel(k1_phy, true); ++ ++ /* We're not doing any testing */ ++ writel(0, k1_phy->regs + USB3_TEST_CTRL); ++} ++ ++static int k1_pcie_phy_init(struct phy *phy) ++{ ++ struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy); ++ ++ /* Note: port type is only valid for port A (both checks needed) */ ++ if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3) ++ k1_pcie_phy_init_usb(k1_phy); ++ else ++ k1_pcie_phy_init_pcie(k1_phy); ++ ++ ++ return clk_prepare_enable(k1_phy->pll); ++} ++ ++static int k1_pcie_phy_exit(struct phy *phy) ++{ ++ struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy); ++ ++ clk_disable_unprepare(k1_phy->pll); ++ ++ return 0; ++} ++ ++static const struct phy_ops k1_pcie_phy_ops = { ++ .init = k1_pcie_phy_init, ++ .exit = k1_pcie_phy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++/* ++ * Get values needed for calibrating PHYs operating in PCIe mode. Only ++ * the combo PHY is able to do this, and its calibration values are used ++ * for configuring all PCIe PHYs. ++ * ++ * We always need to de-assert the "global" reset on the combo PHY, ++ * because the USB driver depends on it. If used for PCIe, that driver ++ * will (also) de-assert this, but by leaving it de-asserted for the ++ * combo PHY, the USB driver doesn't have to do this. Note: although ++ * SpacemiT refers to this as the global reset, we name the "phy" reset. ++ * ++ * In addition, we guarantee the APP_HOLD_PHY_RESET bit is clear for the ++ * combo PHY, so the USB driver doesn't have to manage that either. The ++ * PCIe driver is free to change this bit for normal operation. ++ * ++ * Calibration only needs to be done once. It's possible calibration has ++ * already completed (e.g., it might have happened in the boot loader, or ++ * -EPROBE_DEFER might result in this function being called again). So we ++ * check that early too, to avoid doing it more than once. ++ * ++ * Otherwise we temporarily power up the PHY using the PCIe app clocks ++ * and resets, wait for the hardware to indicate calibration is done, ++ * grab the value, then shut the PHY down again. ++ */ ++static int k1_pcie_combo_phy_calibrate(struct k1_pcie_phy *k1_phy) ++{ ++ struct reset_control_bulk_data resets[] = { ++ { .id = "dbi", }, ++ { .id = "mstr", }, ++ { .id = "slv", }, ++ }; ++ struct clk_bulk_data clocks[] = { ++ { .id = "dbi", }, ++ { .id = "mstr", }, ++ { .id = "slv", }, ++ }; ++ struct device *dev = k1_phy->dev; ++ int ret = 0; ++ int val; ++ ++ /* Nothing to do if we already set the receiver termination value */ ++ if (k1_phy_rterm_valid()) ++ return 0; ++ ++ /* ++ * We also guarantee the APP_HOLD_PHY_RESET bit is clear. We can ++ * leave this bit clear even if an error happens below. ++ */ ++ regmap_assign_bits(k1_phy->pmu, PCIE_CLK_RES_CTRL, ++ PCIE_APP_HOLD_PHY_RST, false); ++ ++ /* If the calibration already completed (e.g. by U-Boot), we're done */ ++ val = readl(k1_phy->regs + PCIE_RCAL_RESULT); ++ if (val & R_TUNE_DONE) ++ goto out_tune_done; ++ ++ /* Put the PHY into PCIe mode */ ++ k1_combo_phy_sel(k1_phy, false); ++ ++ /* Get and enable the PCIe app clocks */ ++ ret = clk_bulk_get(dev, ARRAY_SIZE(clocks), clocks); ++ if (ret < 0) ++ goto out_tune_done; ++ ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); ++ if (ret) ++ goto out_put_clocks; ++ ++ /* Get the PCIe application resets (not the PHY reset) */ ++ ret = reset_control_bulk_get_shared(dev, ARRAY_SIZE(resets), resets); ++ if (ret) ++ goto out_disable_clocks; ++ ++ /* De-assert the PCIe application resets */ ++ ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets); ++ if (ret) ++ goto out_put_resets; ++ ++ /* ++ * This is the core activity here. Wait for the hardware to ++ * signal that it has completed calibration/tuning. Once it ++ * has, the register value will contain the values we'll ++ * use to configure PCIe PHYs. ++ */ ++ ret = readl_poll_timeout(k1_phy->regs + PCIE_RCAL_RESULT, ++ val, val & R_TUNE_DONE, ++ POLL_DELAY, CALIBRATION_TIMEOUT); ++ ++ /* Clean up. We're done with the resets and clocks */ ++ reset_control_bulk_assert(ARRAY_SIZE(resets), resets); ++out_put_resets: ++ reset_control_bulk_put(ARRAY_SIZE(resets), resets); ++out_disable_clocks: ++ clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); ++out_put_clocks: ++ clk_bulk_put(ARRAY_SIZE(clocks), clocks); ++out_tune_done: ++ /* If we got the value without timing out, set k1_phy_rterm */ ++ if (!ret) ++ k1_phy_rterm_set(val); ++ ++ return ret; ++} ++ ++static struct phy * ++k1_pcie_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) ++{ ++ struct k1_pcie_phy *k1_phy = dev_get_drvdata(dev); ++ u32 type; ++ ++ /* The argument specifying the PHY mode is required */ ++ if (args->args_count != 1) ++ return ERR_PTR(-EINVAL); ++ ++ /* We only support PCIe and USB 3 mode */ ++ type = args->args[0]; ++ if (type != PHY_TYPE_PCIE && type != PHY_TYPE_USB3) ++ return ERR_PTR(-EINVAL); ++ ++ /* This PHY can only be used once */ ++ if (k1_phy->type != PHY_NONE) ++ return ERR_PTR(-EBUSY); ++ ++ k1_phy->type = type; ++ ++ return k1_phy->phy; ++} ++ ++/* Use the maximum number of PCIe lanes unless limited by device tree */ ++static u32 k1_pcie_num_lanes(struct k1_pcie_phy *k1_phy, bool port_a) ++{ ++ struct device *dev = k1_phy->dev; ++ u32 count = 0; ++ u32 max; ++ int ret; ++ ++ ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &count); ++ if (count == 1) ++ return 1; ++ ++ if (count == 2 && !port_a) ++ return 2; ++ ++ max = port_a ? 1 : 2; ++ if (ret != -EINVAL) ++ dev_warn(dev, "bad lane count %u for port; using %u\n", ++ count, max); ++ ++ return max; ++} ++ ++static int k1_pcie_combo_phy_probe(struct k1_pcie_phy *k1_phy) ++{ ++ struct device *dev = k1_phy->dev; ++ struct regmap *regmap; ++ int ret; ++ ++ /* Setting the PHY mode requires access to the PMU regmap */ ++ regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), SYSCON_APMU); ++ if (IS_ERR(regmap)) ++ return dev_err_probe(dev, PTR_ERR(regmap), "failed to get PMU\n"); ++ k1_phy->pmu = regmap; ++ ++ ret = k1_pcie_combo_phy_calibrate(k1_phy); ++ if (ret) ++ return dev_err_probe(dev, ret, "calibration failed\n"); ++ ++ /* Needed by k1_pcie_combo_phy_xlate(), which also sets k1_phy->type */ ++ dev_set_drvdata(dev, k1_phy); ++ ++ return 0; ++} ++ ++static int k1_pcie_phy_probe(struct platform_device *pdev) ++{ ++ struct phy *(*xlate)(struct device *dev, ++ const struct of_phandle_args *args); ++ struct device *dev = &pdev->dev; ++ struct reset_control *phy_reset; ++ struct phy_provider *provider; ++ struct k1_pcie_phy *k1_phy; ++ bool probing_port_a; ++ int ret; ++ ++ xlate = of_device_get_match_data(dev); ++ probing_port_a = xlate == k1_pcie_combo_phy_xlate; ++ ++ /* Only the combo PHY can calibrate, so it must probe first */ ++ if (!k1_phy_rterm_valid() && !probing_port_a) ++ return -EPROBE_DEFER; ++ ++ k1_phy = devm_kzalloc(dev, sizeof(*k1_phy), GFP_KERNEL); ++ if (!k1_phy) ++ return -ENOMEM; ++ k1_phy->dev = dev; ++ ++ k1_phy->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(k1_phy->regs)) ++ return dev_err_probe(dev, PTR_ERR(k1_phy->regs), ++ "error mapping registers\n"); ++ ++ /* De-assert the PHY (global) reset and leave it that way */ ++ phy_reset = devm_reset_control_get_exclusive_deasserted(dev, "phy"); ++ if (IS_ERR(phy_reset)) ++ return PTR_ERR(phy_reset); ++ ++ if (probing_port_a) { ++ ret = k1_pcie_combo_phy_probe(k1_phy); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "error probing combo phy\n"); ++ } ++ ++ k1_phy->pcie_lanes = k1_pcie_num_lanes(k1_phy, probing_port_a); ++ ++ k1_phy->phy = devm_phy_create(dev, NULL, &k1_pcie_phy_ops); ++ if (IS_ERR(k1_phy->phy)) ++ return dev_err_probe(dev, PTR_ERR(k1_phy->phy), ++ "error creating phy\n"); ++ phy_set_drvdata(k1_phy->phy, k1_phy); ++ ++ ret = k1_pcie_phy_pll_setup(k1_phy); ++ if (ret) ++ return dev_err_probe(dev, ret, "error initializing clock\n"); ++ ++ provider = devm_of_phy_provider_register(dev, xlate); ++ if (IS_ERR(provider)) ++ return dev_err_probe(dev, PTR_ERR(provider), ++ "error registering provider\n"); ++ return 0; ++} ++ ++static const struct of_device_id k1_pcie_phy_of_match[] = { ++ { .compatible = "spacemit,k1-combo-phy", k1_pcie_combo_phy_xlate, }, ++ { .compatible = "spacemit,k1-pcie-phy", of_phy_simple_xlate, }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, k1_pcie_phy_of_match); ++ ++static struct platform_driver k1_pcie_phy_driver = { ++ .probe = k1_pcie_phy_probe, ++ .driver = { ++ .of_match_table = k1_pcie_phy_of_match, ++ .name = "spacemit-k1-pcie-phy", ++ } ++}; ++module_platform_driver(k1_pcie_phy_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K1 PCIe and USB 3 PHY driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0079-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux-lts/0079-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch deleted file mode 100644 index 2215cfd65e..0000000000 --- a/SPECS/linux-lts/0079-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch +++ /dev/null @@ -1,145 +0,0 @@ -From 160cf483f6a088e178a125f0e3a1e3013726ce5c Mon Sep 17 00:00:00 2001 -From: Javier Martinez Canillas -Date: Sat, 6 Dec 2025 14:44:55 +0100 -Subject: [PATCH 079/467] UPSTREAM: riscv: dts: spacemit: Define the P1 PMIC - regulators for Milk-V Jupiter - -Define the SpacemiT P1 PMIC voltage regulators and their constraints. - -The power management hardware design on the Milk-V Jupiter is identical to -the Banana Pi BPI-F3, so the DT Nodes were taken from k1-bananapi-f3.dts. - -Signed-off-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20251206134532.1741648-4-javierm@redhat.com -Signed-off-by: Yixun Lan -(cherry picked from commit 7d307daa12b15a97269f577d5dcf50518758b568) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 110 ++++++++++++++++++ - 1 file changed, 110 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 5babed4d7094..800a112d5d70 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -95,6 +95,116 @@ &i2c8 { - pinctrl-0 = <&i2c8_cfg>; - pinctrl-names = "default"; - status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin-supply = <®_vcc_4v>; -+ -+ regulators { -+ buck1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3_1v8: buck3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ aldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ dldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo7 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ }; -+ }; - }; - - &uart0 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0080-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch b/SPECS/linux-lts/0080-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch deleted file mode 100644 index 4511c729d0..0000000000 --- a/SPECS/linux-lts/0080-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch +++ /dev/null @@ -1,152 +0,0 @@ -From 506b6beaa759b6c9a08da251acd900242abbc6db Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Thu, 18 Dec 2025 09:12:27 -0600 -Subject: [PATCH 080/467] UPSTREAM: dt-bindings: phy: spacemit: Add SpacemiT - PCIe/combo PHY - -Add the Device Tree binding for the PCIe/USB 3.0 combo PHY found in -the SpacemiT K1 SoC. This is one of three PCIe PHYs, and is unusual -in that only the combo PHY can perform a calibration step needed to -determine settings used by the other two PCIe PHYs. - -Calibration must be done with the combo PHY in PCIe mode, and to allow -this to occur independent of the eventual use for the PHY (PCIe or USB) -some PCIe-related properties must be supplied: clocks; resets; and a -syscon phandle. - -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Alex Elder -Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1] -Tested-by: Yixun Lan -Link: https://patch.msgid.link/20251218151235.454997-2-elder@riscstar.com -Signed-off-by: Vinod Koul -(cherry picked from commit f6194de7df023ecfd5156caf8e2762487be07ef7) -Signed-off-by: Han Gao ---- - .../bindings/phy/spacemit,k1-combo-phy.yaml | 114 ++++++++++++++++++ - 1 file changed, 114 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml -new file mode 100644 -index 000000000000..b59476cd78b5 ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml -@@ -0,0 +1,114 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K1 PCIe/USB3 Combo PHY -+ -+maintainers: -+ - Alex Elder -+ -+description: > -+ Of the three PHYs on the SpacemiT K1 SoC capable of being used for -+ PCIe, one is a combo PHY that can also be configured for use by a -+ USB 3 controller. Using PCIe or USB 3 is a board design decision. -+ -+ The combo PHY is also the only PCIe PHY that is able to determine -+ PCIe calibration values to use, and this must be determined before -+ the other two PCIe PHYs can be used. This calibration must be -+ performed with the combo PHY in PCIe mode, and is this is done -+ when the combo PHY is probed. -+ -+ The combo PHY uses an external oscillator as a reference clock. -+ During normal operation, the PCIe or USB port driver is responsible -+ for ensuring all other clocks needed by a PHY are enabled, and all -+ resets affecting the PHY are deasserted. However, for the combo -+ PHY to perform calibration independent of whether it's later used -+ for PCIe or USB, all PCIe mode clocks and resets must be defined. -+ -+properties: -+ compatible: -+ const: spacemit,k1-combo-phy -+ -+ reg: -+ items: -+ - description: PHY control registers -+ -+ clocks: -+ items: -+ - description: External oscillator used by the PHY PLL -+ - description: DWC PCIe Data Bus Interface (DBI) clock -+ - description: DWC PCIe application AXI-bus Master interface clock -+ - description: DWC PCIe application AXI-bus slave interface clock -+ -+ clock-names: -+ items: -+ - const: refclk -+ - const: dbi -+ - const: mstr -+ - const: slv -+ -+ resets: -+ items: -+ - description: PHY reset; remains deasserted after initialization -+ - description: DWC PCIe Data Bus Interface (DBI) reset -+ - description: DWC PCIe application AXI-bus Master interface reset -+ - description: DWC PCIe application AXI-bus slave interface reset -+ -+ reset-names: -+ items: -+ - const: phy -+ - const: dbi -+ - const: mstr -+ - const: slv -+ -+ spacemit,apmu: -+ description: -+ A phandle that refers to the APMU system controller, whose -+ regmap is used in setting the mode -+ $ref: /schemas/types.yaml#/definitions/phandle -+ -+ "#phy-cells": -+ const: 1 -+ description: -+ The argument value (PHY_TYPE_PCIE or PHY_TYPE_USB3) determines -+ whether the PHY operates in PCIe or USB3 mode. -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ - spacemit,apmu -+ - "#phy-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ phy@c0b10000 { -+ compatible = "spacemit,k1-combo-phy"; -+ reg = <0xc0b10000 0x1000>; -+ clocks = <&vctcxo_24m>, -+ <&syscon_apmu CLK_PCIE0_DBI>, -+ <&syscon_apmu CLK_PCIE0_MASTER>, -+ <&syscon_apmu CLK_PCIE0_SLAVE>; -+ clock-names = "refclk", -+ "dbi", -+ "mstr", -+ "slv"; -+ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, -+ <&syscon_apmu RESET_PCIE0_DBI>, -+ <&syscon_apmu RESET_PCIE0_MASTER>, -+ <&syscon_apmu RESET_PCIE0_SLAVE>; -+ reset-names = "phy", -+ "dbi", -+ "mstr", -+ "slv"; -+ spacemit,apmu = <&syscon_apmu>; -+ #phy-cells = <1>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch b/SPECS/linux-lts/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch new file mode 100644 index 0000000000..4a013ca623 --- /dev/null +++ b/SPECS/linux-lts/0080-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch @@ -0,0 +1,41 @@ +From 1fce0749e1bf54d192dde74d2c105f51a35ab4d4 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Thu, 18 Dec 2025 09:12:30 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add a PCIe regulator + +Define a 3.3v fixed voltage regulator to be used by PCIe on the +Banana Pi BPI-F3. On this platform, this regulator is always on. + +Signed-off-by: Alex Elder +Reviewed-by: Yixun Lan +Tested-by: Yixun Lan +Link: https://lore.kernel.org/r/20251218151235.454997-5-elder@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 73a6c811fa0d07078c9e1eaecea76ce26fb5f10e) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 02f218a16318..71f48454ba47 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -33,6 +33,14 @@ led1 { + }; + }; + ++ pcie_vcc_3v3: pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PCIE_VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + reg_dc_in: dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0081-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch b/SPECS/linux-lts/0081-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch deleted file mode 100644 index db99c863ec..0000000000 --- a/SPECS/linux-lts/0081-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 3cd6a40bb10240022a2201bf5616dd9ed857f053 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Thu, 18 Dec 2025 09:12:28 -0600 -Subject: [PATCH 081/467] UPSTREAM: dt-bindings: phy: spacemit: Introduce PCIe - PHY - -Add the Device Tree binding for two PCIe PHYs present on the SpacemiT -K1 SoC. These PHYs are dependent on a separate combo PHY, which -determines at probe time the calibration values used by the PCIe-only -PHYs. - -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Alex Elder -Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1] -Tested-by: Yixun Lan -Link: https://patch.msgid.link/20251218151235.454997-3-elder@riscstar.com -Signed-off-by: Vinod Koul -(cherry picked from commit 326a278a3682d390269699f68e597b5ef5a57d26) -Signed-off-by: Han Gao ---- - .../bindings/phy/spacemit,k1-pcie-phy.yaml | 71 +++++++++++++++++++ - 1 file changed, 71 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml -new file mode 100644 -index 000000000000..019b28349be7 ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml -@@ -0,0 +1,71 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K1 PCIe PHY -+ -+maintainers: -+ - Alex Elder -+ -+description: > -+ Two PHYs on the SpacemiT K1 SoC used for only for PCIe. These -+ PHYs must be configured using calibration values that are -+ determined by a third "combo PHY". The combo PHY determines -+ these calibration values during probe so they can be used for -+ the two PCIe-only PHYs. -+ -+ The PHY uses an external oscillator as a reference clock. During -+ normal operation, the PCIe host driver is responsible for ensuring -+ all other clocks needed by a PHY are enabled, and all resets -+ affecting the PHY are deasserted. -+ -+properties: -+ compatible: -+ const: spacemit,k1-pcie-phy -+ -+ reg: -+ items: -+ - description: PHY control registers -+ -+ clocks: -+ items: -+ - description: External oscillator used by the PHY PLL -+ -+ clock-names: -+ const: refclk -+ -+ resets: -+ items: -+ - description: PHY reset; remains deasserted after initialization -+ -+ reset-names: -+ const: phy -+ -+ "#phy-cells": -+ const: 0 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ - "#phy-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ phy@c0c10000 { -+ compatible = "spacemit,k1-pcie-phy"; -+ reg = <0xc0c10000 0x1000>; -+ clocks = <&vctcxo_24m>; -+ clock-names = "refclk"; -+ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; -+ reset-names = "phy"; -+ #phy-cells = <0>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch b/SPECS/linux-lts/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch new file mode 100644 index 0000000000..ba9f3b4975 --- /dev/null +++ b/SPECS/linux-lts/0081-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch @@ -0,0 +1,331 @@ +From cca8801247fe6e5967002d5519f537917e6a9bf5 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Thu, 18 Dec 2025 09:12:31 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: PCIe and PHY-related + updates + +Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC. + +Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3 +board. The combo PHY is used for USB on this board, and that will be +enabled when USB 3 support is accepted. + +The combo PHY must perform a calibration step to determine configuration +values used by the PCIe-only PHYs. As a result, it must be enabled if +either of the other two PHYs is enabled. + +Signed-off-by: Alex Elder +Reviewed-by: Yixun Lan +Tested-by: Yixun Lan +Link: https://lore.kernel.org/r/20251218151235.454997-6-elder@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 0be016a4b5d1b927de04e2e7a0a2bce51aacbfff) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 36 ++++ + arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 33 ++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 176 ++++++++++++++++++ + 3 files changed, 245 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 71f48454ba47..3f10efd925dc 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -61,6 +61,12 @@ reg_vcc_4v: vcc-4v { + }; + }; + ++&combo_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_3_cfg>; ++ status = "okay"; ++}; ++ + &emmc { + bus-width = <8>; + mmc-hs400-1_8v; +@@ -272,6 +278,36 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++}; ++ ++&pcie1 { ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++}; ++ ++&pcie2 { ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +index e922e05ff856..b13dcb10f4d6 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +@@ -530,6 +530,39 @@ uart9-2-pins { + }; + }; + ++ pcie0_3_cfg: pcie0-3-cfg { ++ pcie0-3-pins { ++ pinmux = , /* PERST# */ ++ , /* WAKE# */ ++ ; /* CLKREQ# */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <21>; ++ }; ++ }; ++ ++ pcie1_3_cfg: pcie1-3-cfg { ++ pcie1-3-pins { ++ pinmux = , /* PERST# */ ++ , /* WAKE# */ ++ ; /* CLKREQ# */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <21>; ++ }; ++ }; ++ ++ pcie2_4_cfg: pcie2-4-cfg { ++ pcie2-4-pins { ++ pinmux = , /* PERST# */ ++ , /* WAKE# */ ++ ; /* CLKREQ# */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <21>; ++ }; ++ }; ++ + pwm14_1_cfg: pwm14-1-cfg { + pwm14-1-pins { + pinmux = ; +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 7818ca4979b6..86d1db14e2ee 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -4,6 +4,7 @@ + */ + + #include ++#include + + /dts-v1/; + / { +@@ -423,6 +424,52 @@ i2c5: i2c@d4013800 { + status = "disabled"; + }; + ++ combo_phy: phy@c0b10000 { ++ compatible = "spacemit,k1-combo-phy"; ++ reg = <0x0 0xc0b10000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>, ++ <&syscon_apmu CLK_PCIE0_DBI>, ++ <&syscon_apmu CLK_PCIE0_MASTER>, ++ <&syscon_apmu CLK_PCIE0_SLAVE>; ++ clock-names = "refclk", ++ "dbi", ++ "mstr", ++ "slv"; ++ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, ++ <&syscon_apmu RESET_PCIE0_DBI>, ++ <&syscon_apmu RESET_PCIE0_MASTER>, ++ <&syscon_apmu RESET_PCIE0_SLAVE>; ++ reset-names = "phy", ++ "dbi", ++ "mstr", ++ "slv"; ++ #phy-cells = <1>; ++ spacemit,apmu = <&syscon_apmu>; ++ status = "disabled"; ++ }; ++ ++ pcie1_phy: phy@c0c10000 { ++ compatible = "spacemit,k1-pcie-phy"; ++ reg = <0x0 0xc0c10000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>; ++ clock-names = "refclk"; ++ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; ++ reset-names = "phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie2_phy: phy@c0d10000 { ++ compatible = "spacemit,k1-pcie-phy"; ++ reg = <0x0 0xc0d10000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>; ++ clock-names = "refclk"; ++ resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; ++ reset-names = "phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k1-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; +@@ -969,6 +1016,135 @@ pcie-bus { + #size-cells = <2>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, + <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; ++ pcie0: pcie@ca000000 { ++ device_type = "pci"; ++ compatible = "spacemit,k1-pcie"; ++ reg = <0x0 0xca000000 0x0 0x00001000>, ++ <0x0 0xca300000 0x0 0x0001ff24>, ++ <0x0 0x8f000000 0x0 0x00002000>, ++ <0x0 0xc0b20000 0x0 0x00001000>; ++ reg-names = "dbi", ++ "atu", ++ "config", ++ "link"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, ++ <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>; ++ interrupts = <141>; ++ interrupt-names = "msi"; ++ clocks = <&syscon_apmu CLK_PCIE0_DBI>, ++ <&syscon_apmu CLK_PCIE0_MASTER>, ++ <&syscon_apmu CLK_PCIE0_SLAVE>; ++ clock-names = "dbi", ++ "mstr", ++ "slv"; ++ resets = <&syscon_apmu RESET_PCIE0_DBI>, ++ <&syscon_apmu RESET_PCIE0_MASTER>, ++ <&syscon_apmu RESET_PCIE0_SLAVE>; ++ reset-names = "dbi", ++ "mstr", ++ "slv"; ++ spacemit,apmu = <&syscon_apmu 0x03cc>; ++ status = "disabled"; ++ ++ pcie0_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ ++ pcie1: pcie@ca400000 { ++ device_type = "pci"; ++ compatible = "spacemit,k1-pcie"; ++ reg = <0x0 0xca400000 0x0 0x00001000>, ++ <0x0 0xca700000 0x0 0x0001ff24>, ++ <0x0 0x9f000000 0x0 0x00002000>, ++ <0x0 0xc0c20000 0x0 0x00001000>; ++ reg-names = "dbi", ++ "atu", ++ "config", ++ "link"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, ++ <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>; ++ interrupts = <142>; ++ interrupt-names = "msi"; ++ clocks = <&syscon_apmu CLK_PCIE1_DBI>, ++ <&syscon_apmu CLK_PCIE1_MASTER>, ++ <&syscon_apmu CLK_PCIE1_SLAVE>; ++ clock-names = "dbi", ++ "mstr", ++ "slv"; ++ resets = <&syscon_apmu RESET_PCIE1_DBI>, ++ <&syscon_apmu RESET_PCIE1_MASTER>, ++ <&syscon_apmu RESET_PCIE1_SLAVE>; ++ reset-names = "dbi", ++ "mstr", ++ "slv"; ++ spacemit,apmu = <&syscon_apmu 0x3d4>; ++ status = "disabled"; ++ ++ pcie1_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; ++ ++ pcie2: pcie@ca800000 { ++ device_type = "pci"; ++ compatible = "spacemit,k1-pcie"; ++ reg = <0x0 0xca800000 0x0 0x00001000>, ++ <0x0 0xcab00000 0x0 0x0001ff24>, ++ <0x0 0xb7000000 0x0 0x00002000>, ++ <0x0 0xc0d20000 0x0 0x00001000>; ++ reg-names = "dbi", ++ "atu", ++ "config", ++ "link"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, ++ <0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>; ++ interrupts = <143>; ++ interrupt-names = "msi"; ++ clocks = <&syscon_apmu CLK_PCIE2_DBI>, ++ <&syscon_apmu CLK_PCIE2_MASTER>, ++ <&syscon_apmu CLK_PCIE2_SLAVE>; ++ clock-names = "dbi", ++ "mstr", ++ "slv"; ++ resets = <&syscon_apmu RESET_PCIE2_DBI>, ++ <&syscon_apmu RESET_PCIE2_MASTER>, ++ <&syscon_apmu RESET_PCIE2_SLAVE>; ++ reset-names = "dbi", ++ "mstr", ++ "slv"; ++ spacemit,apmu = <&syscon_apmu 0x3dc>; ++ status = "disabled"; ++ ++ pcie2_port: pcie@0 { ++ device_type = "pci"; ++ compatible = "pciclass,0604"; ++ reg = <0x0 0x0 0x0 0x0 0x0>; ++ bus-range = <0x01 0xff>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ }; ++ }; + }; + + storage-bus { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch b/SPECS/linux-lts/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch new file mode 100644 index 0000000000..c158eae42a --- /dev/null +++ b/SPECS/linux-lts/0082-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch @@ -0,0 +1,38 @@ +From f388858d4abee4592cdb3e48a66ed3c681b5801f Mon Sep 17 00:00:00 2001 +From: Encrow Thorne +Date: Tue, 30 Dec 2025 23:06:51 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: i2c: spacemit: add optional + resets + +The I2C controller requires a reset to ensure it starts from a clean state. + +Add the 'resets' property to support this hardware requirement. + +Signed-off-by: Encrow Thorne +Reviewed-by: Troy Mitchell +Acked-by: Rob Herring (Arm) +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20251230150653.42097-1-jyc0019@gmail.com +(cherry picked from commit ad0876a84631fee7b0ad4cd8118b9696aa566671) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml +index b7220fff2235..5896fb120501 100644 +--- a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml ++++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml +@@ -41,6 +41,9 @@ properties: + default: 400000 + maximum: 3300000 + ++ resets: ++ maxItems: 1 ++ + required: + - compatible + - reg +-- +2.53.0 + diff --git a/SPECS/linux-lts/0082-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch b/SPECS/linux-lts/0082-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch deleted file mode 100644 index 10a079192b..0000000000 --- a/SPECS/linux-lts/0082-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch +++ /dev/null @@ -1,758 +0,0 @@ -From 096da94e3a5fd9f1512f24b16feafb77786b5dfc Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Thu, 18 Dec 2025 09:12:29 -0600 -Subject: [PATCH 082/467] UPSTREAM: phy: spacemit: Introduce PCIe/combo PHY - -Introduce a driver that supports three PHYs found on the SpacemiT -K1 SoC. The first PHY is a combo PHY that can be configured for -use for either USB 3 or PCIe. The other two PHYs support PCIe -only. - -All three PHYs must be programmed with an 8 bit receiver termination -value, which must be determined dynamically. Only the combo PHY is -able to determine this value. The combo PHY performs a special -calibration step at probe time to discover this, and that value is -used to program each PHY that operates in PCIe mode. The combo -PHY must therefore be probed before either of the PCIe-only PHYs -will be used. - -Each PHY has an internal PLL driven from an external oscillator. -This PLL started when the PHY is first initialized, and stays -on thereafter. - -During normal operation, the USB or PCIe driver using the PHY must -ensure (other) clocks and resets are set up properly. - -However PCIe mode clocks are enabled and resets are de-asserted -temporarily by this driver to perform the calibration step on the -combo PHY. - -Tested-by: Junzhong Pan -Signed-off-by: Alex Elder -Reviewed-by: Neil Armstrong -Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1] -Tested-by: Yixun Lan -Link: https://patch.msgid.link/20251218151235.454997-4-elder@riscstar.com -Signed-off-by: Vinod Koul -(cherry picked from commit 57e920b92724dd568526990c04e79ed54241c5fc) -Signed-off-by: Han Gao ---- - drivers/phy/Kconfig | 11 + - drivers/phy/Makefile | 1 + - drivers/phy/phy-spacemit-k1-pcie.c | 670 +++++++++++++++++++++++++++++ - 3 files changed, 682 insertions(+) - create mode 100644 drivers/phy/phy-spacemit-k1-pcie.c - -diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig -index 678dd0452f0a..1984c2e56122 100644 ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -101,6 +101,17 @@ config PHY_NXP_PTN3222 - schemes. It supports all three USB 2.0 data rates: Low Speed, Full - Speed and High Speed. - -+config PHY_SPACEMIT_K1_PCIE -+ tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC" -+ depends on ARCH_SPACEMIT || COMPILE_TEST -+ depends on HAS_IOMEM -+ depends on OF -+ select GENERIC_PHY -+ default ARCH_SPACEMIT -+ help -+ Enable support for the PCIe and USB 3 combo PHY and two -+ PCIe-only PHYs used in the SpacemiT K1 SoC. -+ - source "drivers/phy/allwinner/Kconfig" - source "drivers/phy/amlogic/Kconfig" - source "drivers/phy/broadcom/Kconfig" -diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile -index bfb27fb5a494..a206133a3515 100644 ---- a/drivers/phy/Makefile -+++ b/drivers/phy/Makefile -@@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o - obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o - obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o - obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o -+obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-spacemit-k1-pcie.o - obj-y += allwinner/ \ - amlogic/ \ - broadcom/ \ -diff --git a/drivers/phy/phy-spacemit-k1-pcie.c b/drivers/phy/phy-spacemit-k1-pcie.c -new file mode 100644 -index 000000000000..75477bea7f70 ---- /dev/null -+++ b/drivers/phy/phy-spacemit-k1-pcie.c -@@ -0,0 +1,670 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * SpacemiT K1 PCIe and PCIe/USB 3 combo PHY driver -+ * -+ * Copyright (C) 2025 by RISCstar Solutions Corporation. All rights reserved. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* -+ * Three PCIe ports are supported in the SpacemiT K1 SoC, and this driver -+ * supports their PHYs. -+ * -+ * The PHY for PCIe port A is different from the PHYs for ports B and C: -+ * - It has one lane, while ports B and C have two -+ * - It is a combo PHY can be used for PCIe or USB 3 -+ * - It can automatically calibrate PCIe TX and RX termination settings -+ * -+ * The PHY functionality for PCIe ports B and C is identical: -+ * - They have two PCIe lanes (but can be restricted to 1 via device tree) -+ * - They are used for PCIe only -+ * - They are configured using TX and RX values computed for port A -+ * -+ * A given board is designed to use the combo PHY for either PCIe or USB 3. -+ * Whether the combo PHY is configured for PCIe or USB 3 is specified in -+ * device tree using a phandle plus an argument. The argument indicates -+ * the type (either PHY_TYPE_PCIE or PHY_TYPE_USB3). -+ * -+ * Each PHY has a reset that it gets and deasserts during initialization. -+ * Each depends also on other clocks and resets provided by the controller -+ * hardware (PCIe or USB) it is associated with. The controller drivers -+ * are required to enable any clocks and de-assert any resets that affect -+ * PHY operation. In addition each PHY implements an internal PLL, driven -+ * by an external (24 MHz) oscillator. -+ * -+ * PCIe PHYs must be programmed with RX and TX calibration values. The -+ * combo PHY is the only one that can determine these values. They are -+ * determined by temporarily enabling the combo PHY in PCIe mode at probe -+ * time (if necessary). This calibration only needs to be done once, and -+ * when it has completed the TX and RX values are saved. -+ * -+ * To allow the combo PHY to be enabled for calibration, the resets and -+ * clocks it uses in PCIe mode must be supplied. -+ */ -+ -+struct k1_pcie_phy { -+ struct device *dev; /* PHY provider device */ -+ struct phy *phy; -+ void __iomem *regs; -+ u32 pcie_lanes; /* Max (1 or 2) unless limited by DT */ -+ struct clk *pll; -+ struct clk_hw pll_hw; /* Private PLL clock */ -+ -+ /* The remaining fields are only used for the combo PHY */ -+ u32 type; /* PHY_TYPE_PCIE or PHY_TYPE_USB3 */ -+ struct regmap *pmu; /* MMIO regmap (no errors) */ -+}; -+ -+#define CALIBRATION_TIMEOUT 500000 /* For combo PHY (usec) */ -+#define PLL_TIMEOUT 500000 /* For PHY PLL lock (usec) */ -+#define POLL_DELAY 500 /* Time between polls (usec) */ -+ -+/* Selecting the combo PHY operating mode requires APMU regmap access */ -+#define SYSCON_APMU "spacemit,apmu" -+ -+/* PMU space, for selecting between PCIe and USB 3 mode (combo PHY only) */ -+ -+#define PMUA_USB_PHY_CTRL0 0x0110 -+#define COMBO_PHY_SEL BIT(3) /* 0: PCIe; 1: USB 3 */ -+ -+#define PCIE_CLK_RES_CTRL 0x03cc -+#define PCIE_APP_HOLD_PHY_RST BIT(30) -+ -+/* PHY register space */ -+ -+/* Offset between lane 0 and lane 1 registers when there are two */ -+#define PHY_LANE_OFFSET 0x0400 -+ -+/* PHY PLL configuration */ -+#define PCIE_PU_ADDR_CLK_CFG 0x0008 -+#define PLL_READY BIT(0) /* read-only */ -+#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) -+#define TIMER_ADJ_USB 0x2 -+#define TIMER_ADJ_PCIE 0x6 -+#define CFG_SW_PHY_INIT_DONE BIT(11) /* We set after PLL config */ -+ -+#define PCIE_RC_DONE_STATUS 0x0018 -+#define CFG_FORCE_RCV_RETRY BIT(10) /* Used for PCIe */ -+ -+/* PCIe PHY lane calibration; assumes 24MHz input clock */ -+#define PCIE_RC_CAL_REG2 0x0020 -+#define RC_CAL_TOGGLE BIT(22) -+#define CLKSEL GENMASK(31, 29) -+#define CLKSEL_24M 0x3 -+ -+/* Additional PHY PLL configuration (USB 3 and PCIe) */ -+#define PCIE_PU_PLL_1 0x0048 -+#define REF_100_WSSC BIT(12) /* 1: input is 100MHz, SSC */ -+#define FREF_SEL GENMASK(15, 13) -+#define FREF_24M 0x1 -+#define SSC_DEP_SEL GENMASK(19, 16) -+#define SSC_DEP_NONE 0x0 -+#define SSC_DEP_5000PPM 0xa -+ -+/* PCIe PHY configuration */ -+#define PCIE_PU_PLL_2 0x004c -+#define GEN_REF100 BIT(4) /* 1: generate 100MHz clk */ -+ -+#define PCIE_RX_REG1 0x0050 -+#define EN_RTERM BIT(3) -+#define AFE_RTERM_REG GENMASK(11, 8) -+ -+#define PCIE_RX_REG2 0x0054 -+#define RX_RTERM_SEL BIT(5) /* 0: use AFE_RTERM_REG value */ -+ -+#define PCIE_LTSSM_DIS_ENTRY 0x005c -+#define CFG_REFCLK_MODE GENMASK(9, 8) -+#define RFCLK_MODE_DRIVER 0x1 -+#define OVRD_REFCLK_MODE BIT(10) /* 1: use CFG_RFCLK_MODE */ -+ -+#define PCIE_TX_REG1 0x0064 -+#define TX_RTERM_REG GENMASK(15, 12) -+#define TX_RTERM_SEL BIT(25) /* 1: use TX_RTERM_REG */ -+ -+/* Zeroed for the combo PHY operating in USB mode */ -+#define USB3_TEST_CTRL 0x0068 -+ -+/* PHY calibration values, determined by the combo PHY at probe time */ -+#define PCIE_RCAL_RESULT 0x0084 /* Port A PHY only */ -+#define RTERM_VALUE_RX GENMASK(3, 0) -+#define RTERM_VALUE_TX GENMASK(7, 4) -+#define R_TUNE_DONE BIT(10) -+ -+static u32 k1_phy_rterm = ~0; /* Invalid initial value */ -+ -+/* Save the RX and TX receiver termination values */ -+static void k1_phy_rterm_set(u32 val) -+{ -+ k1_phy_rterm = val & (RTERM_VALUE_RX | RTERM_VALUE_TX); -+} -+ -+static bool k1_phy_rterm_valid(void) -+{ -+ /* Valid if no bits outside those we care about are set */ -+ return !(k1_phy_rterm & ~(RTERM_VALUE_RX | RTERM_VALUE_TX)); -+} -+ -+static u32 k1_phy_rterm_rx(void) -+{ -+ return FIELD_GET(RTERM_VALUE_RX, k1_phy_rterm); -+} -+ -+static u32 k1_phy_rterm_tx(void) -+{ -+ return FIELD_GET(RTERM_VALUE_TX, k1_phy_rterm); -+} -+ -+/* Only the combo PHY has a PMU pointer defined */ -+static bool k1_phy_port_a(struct k1_pcie_phy *k1_phy) -+{ -+ return !!k1_phy->pmu; -+} -+ -+/* The PLL clocks are driven by the external oscillator */ -+static const struct clk_parent_data k1_pcie_phy_data[] = { -+ { .fw_name = "refclk", }, -+}; -+ -+static struct k1_pcie_phy *clk_hw_to_k1_phy(struct clk_hw *clk_hw) -+{ -+ return container_of(clk_hw, struct k1_pcie_phy, pll_hw); -+} -+ -+/* USB mode only works on the combo PHY, which has only one lane */ -+static void k1_pcie_phy_pll_prepare_usb(struct k1_pcie_phy *k1_phy) -+{ -+ void __iomem *regs = k1_phy->regs; -+ u32 val; -+ -+ val = readl(regs + PCIE_PU_ADDR_CLK_CFG); -+ val &= ~CFG_INTERNAL_TIMER_ADJ; -+ val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_USB); -+ writel(val, regs + PCIE_PU_ADDR_CLK_CFG); -+ -+ val = readl(regs + PCIE_PU_PLL_1); -+ val &= ~SSC_DEP_SEL; -+ val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_5000PPM); -+ writel(val, regs + PCIE_PU_PLL_1); -+} -+ -+/* Perform PCIe-specific register updates before starting the PLL clock */ -+static void k1_pcie_phy_pll_prepare_pcie(struct k1_pcie_phy *k1_phy) -+{ -+ void __iomem *regs = k1_phy->regs; -+ u32 val; -+ u32 i; -+ -+ for (i = 0; i < k1_phy->pcie_lanes; i++) { -+ val = readl(regs + PCIE_PU_ADDR_CLK_CFG); -+ val &= ~CFG_INTERNAL_TIMER_ADJ; -+ val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_PCIE); -+ writel(val, regs + PCIE_PU_ADDR_CLK_CFG); -+ -+ regs += PHY_LANE_OFFSET; /* Next lane */ -+ } -+ -+ regs = k1_phy->regs; -+ val = readl(regs + PCIE_RC_DONE_STATUS); -+ val |= CFG_FORCE_RCV_RETRY; -+ writel(val, regs + PCIE_RC_DONE_STATUS); -+ -+ val = readl(regs + PCIE_PU_PLL_1); -+ val &= ~SSC_DEP_SEL; -+ val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_NONE); -+ writel(val, regs + PCIE_PU_PLL_1); -+ -+ val = readl(regs + PCIE_PU_PLL_2); -+ val |= GEN_REF100; /* Enable 100 MHz PLL output clock */ -+ writel(val, regs + PCIE_PU_PLL_2); -+} -+ -+static int k1_pcie_phy_pll_prepare(struct clk_hw *clk_hw) -+{ -+ struct k1_pcie_phy *k1_phy = clk_hw_to_k1_phy(clk_hw); -+ void __iomem *regs = k1_phy->regs; -+ u32 val; -+ u32 i; -+ -+ if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3) -+ k1_pcie_phy_pll_prepare_usb(k1_phy); -+ else -+ k1_pcie_phy_pll_prepare_pcie(k1_phy); -+ -+ /* -+ * Disable 100 MHz input reference with spread-spectrum -+ * clocking and select the 24 MHz clock input frequency -+ */ -+ val = readl(regs + PCIE_PU_PLL_1); -+ val &= ~REF_100_WSSC; -+ val &= ~FREF_SEL; -+ val |= FIELD_PREP(FREF_SEL, FREF_24M); -+ writel(val, regs + PCIE_PU_PLL_1); -+ -+ /* Mark PLL configuration done on all lanes */ -+ for (i = 0; i < k1_phy->pcie_lanes; i++) { -+ val = readl(regs + PCIE_PU_ADDR_CLK_CFG); -+ val |= CFG_SW_PHY_INIT_DONE; -+ writel(val, regs + PCIE_PU_ADDR_CLK_CFG); -+ -+ regs += PHY_LANE_OFFSET; /* Next lane */ -+ } -+ -+ /* -+ * Wait for indication the PHY PLL is locked. Lanes for ports -+ * B and C share a PLL, so it's enough to sample just lane 0. -+ */ -+ return readl_poll_timeout(k1_phy->regs + PCIE_PU_ADDR_CLK_CFG, -+ val, val & PLL_READY, -+ POLL_DELAY, PLL_TIMEOUT); -+} -+ -+/* Prepare implies enable, and once enabled, it's always on */ -+static const struct clk_ops k1_pcie_phy_pll_ops = { -+ .prepare = k1_pcie_phy_pll_prepare, -+}; -+ -+/* We represent the PHY PLL as a private clock */ -+static int k1_pcie_phy_pll_setup(struct k1_pcie_phy *k1_phy) -+{ -+ struct clk_hw *hw = &k1_phy->pll_hw; -+ struct device *dev = k1_phy->dev; -+ struct clk_init_data init = { }; -+ char *name; -+ int ret; -+ -+ name = kasprintf(GFP_KERNEL, "pcie%u_phy_pll", k1_phy->phy->id); -+ if (!name) -+ return -ENOMEM; -+ -+ init.name = name; -+ init.ops = &k1_pcie_phy_pll_ops; -+ init.parent_data = k1_pcie_phy_data; -+ init.num_parents = ARRAY_SIZE(k1_pcie_phy_data); -+ -+ hw->init = &init; -+ -+ ret = devm_clk_hw_register(dev, hw); -+ -+ kfree(name); /* __clk_register() duplicates the name we provide */ -+ -+ if (ret) -+ return ret; -+ -+ k1_phy->pll = devm_clk_hw_get_clk(dev, hw, "pll"); -+ if (IS_ERR(k1_phy->pll)) -+ return PTR_ERR(k1_phy->pll); -+ -+ return 0; -+} -+ -+/* Select PCIe or USB 3 mode for the combo PHY. */ -+static void k1_combo_phy_sel(struct k1_pcie_phy *k1_phy, bool usb) -+{ -+ struct regmap *pmu = k1_phy->pmu; -+ -+ /* Only change it if it's not already in the desired state */ -+ if (!regmap_test_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL) == usb) -+ regmap_assign_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL, usb); -+} -+ -+static void k1_pcie_phy_init_pcie(struct k1_pcie_phy *k1_phy) -+{ -+ u32 rx_rterm = k1_phy_rterm_rx(); -+ u32 tx_rterm = k1_phy_rterm_tx(); -+ void __iomem *regs; -+ u32 val; -+ int i; -+ -+ /* For the combo PHY, set PHY to PCIe mode */ -+ if (k1_phy_port_a(k1_phy)) -+ k1_combo_phy_sel(k1_phy, false); -+ -+ regs = k1_phy->regs; -+ for (i = 0; i < k1_phy->pcie_lanes; i++) { -+ val = readl(regs + PCIE_RX_REG1); -+ -+ /* Set RX analog front-end receiver termination value */ -+ val &= ~AFE_RTERM_REG; -+ val |= FIELD_PREP(AFE_RTERM_REG, rx_rterm); -+ -+ /* And enable refclock receiver termination */ -+ val |= EN_RTERM; -+ writel(val, regs + PCIE_RX_REG1); -+ -+ val = readl(regs + PCIE_RX_REG2); -+ /* Use PCIE_RX_REG1 AFE_RTERM_REG value */ -+ val &= ~RX_RTERM_SEL; -+ writel(val, regs + PCIE_RX_REG2); -+ -+ val = readl(regs + PCIE_TX_REG1); -+ -+ /* Set TX driver termination value */ -+ val &= ~TX_RTERM_REG; -+ val |= FIELD_PREP(TX_RTERM_REG, tx_rterm); -+ -+ /* Use PCIE_TX_REG1 TX_RTERM_REG value */ -+ val |= TX_RTERM_SEL; -+ writel(val, regs + PCIE_TX_REG1); -+ -+ /* Set the input clock to 24 MHz, and clear RC_CAL_TOGGLE */ -+ val = readl(regs + PCIE_RC_CAL_REG2); -+ val &= CLKSEL; -+ val |= FIELD_PREP(CLKSEL, CLKSEL_24M); -+ val &= ~RC_CAL_TOGGLE; -+ writel(val, regs + PCIE_RC_CAL_REG2); -+ -+ /* Now trigger recalibration by setting RC_CAL_TOGGLE again */ -+ val |= RC_CAL_TOGGLE; -+ writel(val, regs + PCIE_RC_CAL_REG2); -+ -+ val = readl(regs + PCIE_LTSSM_DIS_ENTRY); -+ /* Override the reference clock; set to refclk driver mode */ -+ val |= OVRD_REFCLK_MODE; -+ val &= ~CFG_REFCLK_MODE; -+ val |= FIELD_PREP(CFG_REFCLK_MODE, RFCLK_MODE_DRIVER); -+ writel(val, regs + PCIE_LTSSM_DIS_ENTRY); -+ -+ regs += PHY_LANE_OFFSET; /* Next lane */ -+ } -+} -+ -+/* Only called for combo PHY */ -+static void k1_pcie_phy_init_usb(struct k1_pcie_phy *k1_phy) -+{ -+ k1_combo_phy_sel(k1_phy, true); -+ -+ /* We're not doing any testing */ -+ writel(0, k1_phy->regs + USB3_TEST_CTRL); -+} -+ -+static int k1_pcie_phy_init(struct phy *phy) -+{ -+ struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy); -+ -+ /* Note: port type is only valid for port A (both checks needed) */ -+ if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3) -+ k1_pcie_phy_init_usb(k1_phy); -+ else -+ k1_pcie_phy_init_pcie(k1_phy); -+ -+ -+ return clk_prepare_enable(k1_phy->pll); -+} -+ -+static int k1_pcie_phy_exit(struct phy *phy) -+{ -+ struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy); -+ -+ clk_disable_unprepare(k1_phy->pll); -+ -+ return 0; -+} -+ -+static const struct phy_ops k1_pcie_phy_ops = { -+ .init = k1_pcie_phy_init, -+ .exit = k1_pcie_phy_exit, -+ .owner = THIS_MODULE, -+}; -+ -+/* -+ * Get values needed for calibrating PHYs operating in PCIe mode. Only -+ * the combo PHY is able to do this, and its calibration values are used -+ * for configuring all PCIe PHYs. -+ * -+ * We always need to de-assert the "global" reset on the combo PHY, -+ * because the USB driver depends on it. If used for PCIe, that driver -+ * will (also) de-assert this, but by leaving it de-asserted for the -+ * combo PHY, the USB driver doesn't have to do this. Note: although -+ * SpacemiT refers to this as the global reset, we name the "phy" reset. -+ * -+ * In addition, we guarantee the APP_HOLD_PHY_RESET bit is clear for the -+ * combo PHY, so the USB driver doesn't have to manage that either. The -+ * PCIe driver is free to change this bit for normal operation. -+ * -+ * Calibration only needs to be done once. It's possible calibration has -+ * already completed (e.g., it might have happened in the boot loader, or -+ * -EPROBE_DEFER might result in this function being called again). So we -+ * check that early too, to avoid doing it more than once. -+ * -+ * Otherwise we temporarily power up the PHY using the PCIe app clocks -+ * and resets, wait for the hardware to indicate calibration is done, -+ * grab the value, then shut the PHY down again. -+ */ -+static int k1_pcie_combo_phy_calibrate(struct k1_pcie_phy *k1_phy) -+{ -+ struct reset_control_bulk_data resets[] = { -+ { .id = "dbi", }, -+ { .id = "mstr", }, -+ { .id = "slv", }, -+ }; -+ struct clk_bulk_data clocks[] = { -+ { .id = "dbi", }, -+ { .id = "mstr", }, -+ { .id = "slv", }, -+ }; -+ struct device *dev = k1_phy->dev; -+ int ret = 0; -+ int val; -+ -+ /* Nothing to do if we already set the receiver termination value */ -+ if (k1_phy_rterm_valid()) -+ return 0; -+ -+ /* -+ * We also guarantee the APP_HOLD_PHY_RESET bit is clear. We can -+ * leave this bit clear even if an error happens below. -+ */ -+ regmap_assign_bits(k1_phy->pmu, PCIE_CLK_RES_CTRL, -+ PCIE_APP_HOLD_PHY_RST, false); -+ -+ /* If the calibration already completed (e.g. by U-Boot), we're done */ -+ val = readl(k1_phy->regs + PCIE_RCAL_RESULT); -+ if (val & R_TUNE_DONE) -+ goto out_tune_done; -+ -+ /* Put the PHY into PCIe mode */ -+ k1_combo_phy_sel(k1_phy, false); -+ -+ /* Get and enable the PCIe app clocks */ -+ ret = clk_bulk_get(dev, ARRAY_SIZE(clocks), clocks); -+ if (ret < 0) -+ goto out_tune_done; -+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); -+ if (ret) -+ goto out_put_clocks; -+ -+ /* Get the PCIe application resets (not the PHY reset) */ -+ ret = reset_control_bulk_get_shared(dev, ARRAY_SIZE(resets), resets); -+ if (ret) -+ goto out_disable_clocks; -+ -+ /* De-assert the PCIe application resets */ -+ ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets); -+ if (ret) -+ goto out_put_resets; -+ -+ /* -+ * This is the core activity here. Wait for the hardware to -+ * signal that it has completed calibration/tuning. Once it -+ * has, the register value will contain the values we'll -+ * use to configure PCIe PHYs. -+ */ -+ ret = readl_poll_timeout(k1_phy->regs + PCIE_RCAL_RESULT, -+ val, val & R_TUNE_DONE, -+ POLL_DELAY, CALIBRATION_TIMEOUT); -+ -+ /* Clean up. We're done with the resets and clocks */ -+ reset_control_bulk_assert(ARRAY_SIZE(resets), resets); -+out_put_resets: -+ reset_control_bulk_put(ARRAY_SIZE(resets), resets); -+out_disable_clocks: -+ clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); -+out_put_clocks: -+ clk_bulk_put(ARRAY_SIZE(clocks), clocks); -+out_tune_done: -+ /* If we got the value without timing out, set k1_phy_rterm */ -+ if (!ret) -+ k1_phy_rterm_set(val); -+ -+ return ret; -+} -+ -+static struct phy * -+k1_pcie_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) -+{ -+ struct k1_pcie_phy *k1_phy = dev_get_drvdata(dev); -+ u32 type; -+ -+ /* The argument specifying the PHY mode is required */ -+ if (args->args_count != 1) -+ return ERR_PTR(-EINVAL); -+ -+ /* We only support PCIe and USB 3 mode */ -+ type = args->args[0]; -+ if (type != PHY_TYPE_PCIE && type != PHY_TYPE_USB3) -+ return ERR_PTR(-EINVAL); -+ -+ /* This PHY can only be used once */ -+ if (k1_phy->type != PHY_NONE) -+ return ERR_PTR(-EBUSY); -+ -+ k1_phy->type = type; -+ -+ return k1_phy->phy; -+} -+ -+/* Use the maximum number of PCIe lanes unless limited by device tree */ -+static u32 k1_pcie_num_lanes(struct k1_pcie_phy *k1_phy, bool port_a) -+{ -+ struct device *dev = k1_phy->dev; -+ u32 count = 0; -+ u32 max; -+ int ret; -+ -+ ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &count); -+ if (count == 1) -+ return 1; -+ -+ if (count == 2 && !port_a) -+ return 2; -+ -+ max = port_a ? 1 : 2; -+ if (ret != -EINVAL) -+ dev_warn(dev, "bad lane count %u for port; using %u\n", -+ count, max); -+ -+ return max; -+} -+ -+static int k1_pcie_combo_phy_probe(struct k1_pcie_phy *k1_phy) -+{ -+ struct device *dev = k1_phy->dev; -+ struct regmap *regmap; -+ int ret; -+ -+ /* Setting the PHY mode requires access to the PMU regmap */ -+ regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), SYSCON_APMU); -+ if (IS_ERR(regmap)) -+ return dev_err_probe(dev, PTR_ERR(regmap), "failed to get PMU\n"); -+ k1_phy->pmu = regmap; -+ -+ ret = k1_pcie_combo_phy_calibrate(k1_phy); -+ if (ret) -+ return dev_err_probe(dev, ret, "calibration failed\n"); -+ -+ /* Needed by k1_pcie_combo_phy_xlate(), which also sets k1_phy->type */ -+ dev_set_drvdata(dev, k1_phy); -+ -+ return 0; -+} -+ -+static int k1_pcie_phy_probe(struct platform_device *pdev) -+{ -+ struct phy *(*xlate)(struct device *dev, -+ const struct of_phandle_args *args); -+ struct device *dev = &pdev->dev; -+ struct reset_control *phy_reset; -+ struct phy_provider *provider; -+ struct k1_pcie_phy *k1_phy; -+ bool probing_port_a; -+ int ret; -+ -+ xlate = of_device_get_match_data(dev); -+ probing_port_a = xlate == k1_pcie_combo_phy_xlate; -+ -+ /* Only the combo PHY can calibrate, so it must probe first */ -+ if (!k1_phy_rterm_valid() && !probing_port_a) -+ return -EPROBE_DEFER; -+ -+ k1_phy = devm_kzalloc(dev, sizeof(*k1_phy), GFP_KERNEL); -+ if (!k1_phy) -+ return -ENOMEM; -+ k1_phy->dev = dev; -+ -+ k1_phy->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(k1_phy->regs)) -+ return dev_err_probe(dev, PTR_ERR(k1_phy->regs), -+ "error mapping registers\n"); -+ -+ /* De-assert the PHY (global) reset and leave it that way */ -+ phy_reset = devm_reset_control_get_exclusive_deasserted(dev, "phy"); -+ if (IS_ERR(phy_reset)) -+ return PTR_ERR(phy_reset); -+ -+ if (probing_port_a) { -+ ret = k1_pcie_combo_phy_probe(k1_phy); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "error probing combo phy\n"); -+ } -+ -+ k1_phy->pcie_lanes = k1_pcie_num_lanes(k1_phy, probing_port_a); -+ -+ k1_phy->phy = devm_phy_create(dev, NULL, &k1_pcie_phy_ops); -+ if (IS_ERR(k1_phy->phy)) -+ return dev_err_probe(dev, PTR_ERR(k1_phy->phy), -+ "error creating phy\n"); -+ phy_set_drvdata(k1_phy->phy, k1_phy); -+ -+ ret = k1_pcie_phy_pll_setup(k1_phy); -+ if (ret) -+ return dev_err_probe(dev, ret, "error initializing clock\n"); -+ -+ provider = devm_of_phy_provider_register(dev, xlate); -+ if (IS_ERR(provider)) -+ return dev_err_probe(dev, PTR_ERR(provider), -+ "error registering provider\n"); -+ return 0; -+} -+ -+static const struct of_device_id k1_pcie_phy_of_match[] = { -+ { .compatible = "spacemit,k1-combo-phy", k1_pcie_combo_phy_xlate, }, -+ { .compatible = "spacemit,k1-pcie-phy", of_phy_simple_xlate, }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, k1_pcie_phy_of_match); -+ -+static struct platform_driver k1_pcie_phy_driver = { -+ .probe = k1_pcie_phy_probe, -+ .driver = { -+ .of_match_table = k1_pcie_phy_of_match, -+ .name = "spacemit-k1-pcie-phy", -+ } -+}; -+module_platform_driver(k1_pcie_phy_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K1 PCIe and USB 3 PHY driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0083-UPSTREAM-i2c-k1-add-reset-support.patch b/SPECS/linux-lts/0083-UPSTREAM-i2c-k1-add-reset-support.patch new file mode 100644 index 0000000000..8df67ed42a --- /dev/null +++ b/SPECS/linux-lts/0083-UPSTREAM-i2c-k1-add-reset-support.patch @@ -0,0 +1,56 @@ +From ed3b67eff1ecc6048f6b6a76bff5a97ff2abb964 Mon Sep 17 00:00:00 2001 +From: Encrow Thorne +Date: Tue, 30 Dec 2025 23:06:52 +0800 +Subject: [RUYI PATCH] UPSTREAM: i2c: k1: add reset support + +The K1 I2C controller provides a reset line that needs to be deasserted +before the controller can be accessed. + +Add reset support to the driver to ensure the controller starts in the +required state. + +Signed-off-by: Encrow Thorne +Reviewed-by: Troy Mitchell +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20251230150653.42097-2-jyc0019@gmail.com +(cherry picked from commit b96259551b337225bb0e7afb3452b98435dd8b81) +Signed-off-by: Han Gao +--- + drivers/i2c/busses/i2c-k1.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index 8ef6d5d1927b..d0948a16de3e 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++ #include + + /* spacemit i2c registers */ + #define SPACEMIT_ICR 0x0 /* Control register */ +@@ -534,6 +535,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + struct device *dev = &pdev->dev; + struct device_node *of_node = pdev->dev.of_node; + struct spacemit_i2c_dev *i2c; ++ struct reset_control *rst; + int ret; + + i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); +@@ -578,6 +580,11 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); + ++ rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); ++ if (IS_ERR(rst)) ++ return dev_err_probe(dev, PTR_ERR(rst), ++ "failed to acquire deasserted reset\n"); ++ + spacemit_i2c_reset(i2c); + + i2c_set_adapdata(&i2c->adapt, i2c); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0083-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch b/SPECS/linux-lts/0083-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch deleted file mode 100644 index f3892b1a9e..0000000000 --- a/SPECS/linux-lts/0083-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch +++ /dev/null @@ -1,41 +0,0 @@ -From d4491d4d3cdceae1b08777accb31e16fced2cedf Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Thu, 18 Dec 2025 09:12:30 -0600 -Subject: [PATCH 083/467] UPSTREAM: riscv: dts: spacemit: Add a PCIe regulator - -Define a 3.3v fixed voltage regulator to be used by PCIe on the -Banana Pi BPI-F3. On this platform, this regulator is always on. - -Signed-off-by: Alex Elder -Reviewed-by: Yixun Lan -Tested-by: Yixun Lan -Link: https://lore.kernel.org/r/20251218151235.454997-5-elder@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 73a6c811fa0d07078c9e1eaecea76ce26fb5f10e) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 02f218a16318..71f48454ba47 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -33,6 +33,14 @@ led1 { - }; - }; - -+ pcie_vcc_3v3: pcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "PCIE_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ - reg_dc_in: dc-in-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_in_12v"; --- -2.53.0 - diff --git a/SPECS/linux-lts/0084-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch b/SPECS/linux-lts/0084-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch deleted file mode 100644 index 0ce1356ac4..0000000000 --- a/SPECS/linux-lts/0084-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch +++ /dev/null @@ -1,331 +0,0 @@ -From 18a1bfdbf520d71a0a3013e286a6cb9152dca8b4 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Thu, 18 Dec 2025 09:12:31 -0600 -Subject: [PATCH 084/467] UPSTREAM: riscv: dts: spacemit: PCIe and PHY-related - updates - -Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC. - -Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3 -board. The combo PHY is used for USB on this board, and that will be -enabled when USB 3 support is accepted. - -The combo PHY must perform a calibration step to determine configuration -values used by the PCIe-only PHYs. As a result, it must be enabled if -either of the other two PHYs is enabled. - -Signed-off-by: Alex Elder -Reviewed-by: Yixun Lan -Tested-by: Yixun Lan -Link: https://lore.kernel.org/r/20251218151235.454997-6-elder@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 0be016a4b5d1b927de04e2e7a0a2bce51aacbfff) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 36 ++++ - arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 33 ++++ - arch/riscv/boot/dts/spacemit/k1.dtsi | 176 ++++++++++++++++++ - 3 files changed, 245 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 71f48454ba47..3f10efd925dc 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -61,6 +61,12 @@ reg_vcc_4v: vcc-4v { - }; - }; - -+&combo_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie0_3_cfg>; -+ status = "okay"; -+}; -+ - &emmc { - bus-width = <8>; - mmc-hs400-1_8v; -@@ -272,6 +278,36 @@ dldo7 { - }; - }; - -+&pcie1_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_3_cfg>; -+ status = "okay"; -+}; -+ -+&pcie1_port { -+ phys = <&pcie1_phy>; -+}; -+ -+&pcie1 { -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+ status = "okay"; -+}; -+ -+&pcie2_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_4_cfg>; -+ status = "okay"; -+}; -+ -+&pcie2_port { -+ phys = <&pcie2_phy>; -+}; -+ -+&pcie2 { -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -index e922e05ff856..b13dcb10f4d6 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -@@ -530,6 +530,39 @@ uart9-2-pins { - }; - }; - -+ pcie0_3_cfg: pcie0-3-cfg { -+ pcie0-3-pins { -+ pinmux = , /* PERST# */ -+ , /* WAKE# */ -+ ; /* CLKREQ# */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <21>; -+ }; -+ }; -+ -+ pcie1_3_cfg: pcie1-3-cfg { -+ pcie1-3-pins { -+ pinmux = , /* PERST# */ -+ , /* WAKE# */ -+ ; /* CLKREQ# */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <21>; -+ }; -+ }; -+ -+ pcie2_4_cfg: pcie2-4-cfg { -+ pcie2-4-pins { -+ pinmux = , /* PERST# */ -+ , /* WAKE# */ -+ ; /* CLKREQ# */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <21>; -+ }; -+ }; -+ - pwm14_1_cfg: pwm14-1-cfg { - pwm14-1-pins { - pinmux = ; -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 7818ca4979b6..86d1db14e2ee 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -4,6 +4,7 @@ - */ - - #include -+#include - - /dts-v1/; - / { -@@ -423,6 +424,52 @@ i2c5: i2c@d4013800 { - status = "disabled"; - }; - -+ combo_phy: phy@c0b10000 { -+ compatible = "spacemit,k1-combo-phy"; -+ reg = <0x0 0xc0b10000 0x0 0x1000>; -+ clocks = <&vctcxo_24m>, -+ <&syscon_apmu CLK_PCIE0_DBI>, -+ <&syscon_apmu CLK_PCIE0_MASTER>, -+ <&syscon_apmu CLK_PCIE0_SLAVE>; -+ clock-names = "refclk", -+ "dbi", -+ "mstr", -+ "slv"; -+ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, -+ <&syscon_apmu RESET_PCIE0_DBI>, -+ <&syscon_apmu RESET_PCIE0_MASTER>, -+ <&syscon_apmu RESET_PCIE0_SLAVE>; -+ reset-names = "phy", -+ "dbi", -+ "mstr", -+ "slv"; -+ #phy-cells = <1>; -+ spacemit,apmu = <&syscon_apmu>; -+ status = "disabled"; -+ }; -+ -+ pcie1_phy: phy@c0c10000 { -+ compatible = "spacemit,k1-pcie-phy"; -+ reg = <0x0 0xc0c10000 0x0 0x1000>; -+ clocks = <&vctcxo_24m>; -+ clock-names = "refclk"; -+ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; -+ reset-names = "phy"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ pcie2_phy: phy@c0d10000 { -+ compatible = "spacemit,k1-pcie-phy"; -+ reg = <0x0 0xc0d10000 0x0 0x1000>; -+ clocks = <&vctcxo_24m>; -+ clock-names = "refclk"; -+ resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; -+ reset-names = "phy"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k1-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; -@@ -969,6 +1016,135 @@ pcie-bus { - #size-cells = <2>; - dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, - <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; -+ pcie0: pcie@ca000000 { -+ device_type = "pci"; -+ compatible = "spacemit,k1-pcie"; -+ reg = <0x0 0xca000000 0x0 0x00001000>, -+ <0x0 0xca300000 0x0 0x0001ff24>, -+ <0x0 0x8f000000 0x0 0x00002000>, -+ <0x0 0xc0b20000 0x0 0x00001000>; -+ reg-names = "dbi", -+ "atu", -+ "config", -+ "link"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, -+ <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>; -+ interrupts = <141>; -+ interrupt-names = "msi"; -+ clocks = <&syscon_apmu CLK_PCIE0_DBI>, -+ <&syscon_apmu CLK_PCIE0_MASTER>, -+ <&syscon_apmu CLK_PCIE0_SLAVE>; -+ clock-names = "dbi", -+ "mstr", -+ "slv"; -+ resets = <&syscon_apmu RESET_PCIE0_DBI>, -+ <&syscon_apmu RESET_PCIE0_MASTER>, -+ <&syscon_apmu RESET_PCIE0_SLAVE>; -+ reset-names = "dbi", -+ "mstr", -+ "slv"; -+ spacemit,apmu = <&syscon_apmu 0x03cc>; -+ status = "disabled"; -+ -+ pcie0_port: pcie@0 { -+ device_type = "pci"; -+ compatible = "pciclass,0604"; -+ reg = <0x0 0x0 0x0 0x0 0x0>; -+ bus-range = <0x01 0xff>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ }; -+ }; -+ -+ pcie1: pcie@ca400000 { -+ device_type = "pci"; -+ compatible = "spacemit,k1-pcie"; -+ reg = <0x0 0xca400000 0x0 0x00001000>, -+ <0x0 0xca700000 0x0 0x0001ff24>, -+ <0x0 0x9f000000 0x0 0x00002000>, -+ <0x0 0xc0c20000 0x0 0x00001000>; -+ reg-names = "dbi", -+ "atu", -+ "config", -+ "link"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, -+ <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>; -+ interrupts = <142>; -+ interrupt-names = "msi"; -+ clocks = <&syscon_apmu CLK_PCIE1_DBI>, -+ <&syscon_apmu CLK_PCIE1_MASTER>, -+ <&syscon_apmu CLK_PCIE1_SLAVE>; -+ clock-names = "dbi", -+ "mstr", -+ "slv"; -+ resets = <&syscon_apmu RESET_PCIE1_DBI>, -+ <&syscon_apmu RESET_PCIE1_MASTER>, -+ <&syscon_apmu RESET_PCIE1_SLAVE>; -+ reset-names = "dbi", -+ "mstr", -+ "slv"; -+ spacemit,apmu = <&syscon_apmu 0x3d4>; -+ status = "disabled"; -+ -+ pcie1_port: pcie@0 { -+ device_type = "pci"; -+ compatible = "pciclass,0604"; -+ reg = <0x0 0x0 0x0 0x0 0x0>; -+ bus-range = <0x01 0xff>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ }; -+ }; -+ -+ pcie2: pcie@ca800000 { -+ device_type = "pci"; -+ compatible = "spacemit,k1-pcie"; -+ reg = <0x0 0xca800000 0x0 0x00001000>, -+ <0x0 0xcab00000 0x0 0x0001ff24>, -+ <0x0 0xb7000000 0x0 0x00002000>, -+ <0x0 0xc0d20000 0x0 0x00001000>; -+ reg-names = "dbi", -+ "atu", -+ "config", -+ "link"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, -+ <0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>, -+ <0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>; -+ interrupts = <143>; -+ interrupt-names = "msi"; -+ clocks = <&syscon_apmu CLK_PCIE2_DBI>, -+ <&syscon_apmu CLK_PCIE2_MASTER>, -+ <&syscon_apmu CLK_PCIE2_SLAVE>; -+ clock-names = "dbi", -+ "mstr", -+ "slv"; -+ resets = <&syscon_apmu RESET_PCIE2_DBI>, -+ <&syscon_apmu RESET_PCIE2_MASTER>, -+ <&syscon_apmu RESET_PCIE2_SLAVE>; -+ reset-names = "dbi", -+ "mstr", -+ "slv"; -+ spacemit,apmu = <&syscon_apmu 0x3dc>; -+ status = "disabled"; -+ -+ pcie2_port: pcie@0 { -+ device_type = "pci"; -+ compatible = "pciclass,0604"; -+ reg = <0x0 0x0 0x0 0x0 0x0>; -+ bus-range = <0x01 0xff>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ }; -+ }; - }; - - storage-bus { --- -2.53.0 - diff --git a/SPECS/linux-lts/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch b/SPECS/linux-lts/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch new file mode 100644 index 0000000000..19f85450fa --- /dev/null +++ b/SPECS/linux-lts/0084-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch @@ -0,0 +1,87 @@ +From 3aa8e6c84101edb3c499478758e4a82cc230af36 Mon Sep 17 00:00:00 2001 +From: Encrow Thorne +Date: Tue, 30 Dec 2025 23:06:53 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add reset property + +Add resets property to K1 I2C node. + +Signed-off-by: Encrow Thorne +Link: https://lore.kernel.org/r/20251230150653.42097-3-jyc0019@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 7d6fe7e381d2912300df06e1a7e7a6f6a9269af0) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 86d1db14e2ee..4c045da95d72 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -368,6 +368,7 @@ i2c0: i2c@d4010800 { + <&syscon_apbc CLK_TWSI0_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI0>; + interrupts = <36>; + status = "disabled"; + }; +@@ -381,6 +382,7 @@ i2c1: i2c@d4011000 { + <&syscon_apbc CLK_TWSI1_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI1>; + interrupts = <37>; + status = "disabled"; + }; +@@ -394,6 +396,7 @@ i2c2: i2c@d4012000 { + <&syscon_apbc CLK_TWSI2_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI2>; + interrupts = <38>; + status = "disabled"; + }; +@@ -407,6 +410,7 @@ i2c4: i2c@d4012800 { + <&syscon_apbc CLK_TWSI4_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI4>; + interrupts = <40>; + status = "disabled"; + }; +@@ -420,6 +424,7 @@ i2c5: i2c@d4013800 { + <&syscon_apbc CLK_TWSI5_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI5>; + interrupts = <41>; + status = "disabled"; + }; +@@ -490,6 +495,7 @@ i2c6: i2c@d4018800 { + <&syscon_apbc CLK_TWSI6_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI6>; + interrupts = <70>; + status = "disabled"; + }; +@@ -593,6 +599,7 @@ i2c7: i2c@d401d000 { + <&syscon_apbc CLK_TWSI7_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI7>; + interrupts = <18>; + status = "disabled"; + }; +@@ -606,6 +613,7 @@ i2c8: i2c@d401d800 { + <&syscon_apbc CLK_TWSI8_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_TWSI8>; + interrupts = <19>; + status = "disabled"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0085-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch b/SPECS/linux-lts/0085-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch deleted file mode 100644 index 55238bb179..0000000000 --- a/SPECS/linux-lts/0085-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 76c5487f89e7e980c33e0ff5153a4b508e920406 Mon Sep 17 00:00:00 2001 -From: Encrow Thorne -Date: Tue, 30 Dec 2025 23:06:51 +0800 -Subject: [PATCH 085/467] UPSTREAM: dt-bindings: i2c: spacemit: add optional - resets - -The I2C controller requires a reset to ensure it starts from a clean state. - -Add the 'resets' property to support this hardware requirement. - -Signed-off-by: Encrow Thorne -Reviewed-by: Troy Mitchell -Acked-by: Rob Herring (Arm) -Signed-off-by: Andi Shyti -Link: https://lore.kernel.org/r/20251230150653.42097-1-jyc0019@gmail.com -(cherry picked from commit ad0876a84631fee7b0ad4cd8118b9696aa566671) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml -index b7220fff2235..5896fb120501 100644 ---- a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml -+++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml -@@ -41,6 +41,9 @@ properties: - default: 400000 - maximum: 3300000 - -+ resets: -+ maxItems: 1 -+ - required: - - compatible - - reg --- -2.53.0 - diff --git a/SPECS/linux-lts/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch b/SPECS/linux-lts/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch new file mode 100644 index 0000000000..eae9b4c51d --- /dev/null +++ b/SPECS/linux-lts/0085-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch @@ -0,0 +1,69 @@ +From 9d8fbb22b0d4fc7ec75661abcee3d71ca556f67a Mon Sep 17 00:00:00 2001 +From: Ze Huang +Date: Fri, 17 Oct 2025 22:49:52 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: phy: spacemit: add K1 USB2 PHY + +Add support for USB2 PHY found on SpacemiT K1 SoC. + +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Ze Huang +Tested-by: Aurelien Jarno +Tested-by: Junzhong Pan +Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-1-7cf9ea2477a1@linux.dev +Signed-off-by: Vinod Koul +(cherry picked from commit 61b84d5b20af2a4c9944972202c1386026598928) +Signed-off-by: Han Gao +--- + .../bindings/phy/spacemit,usb2-phy.yaml | 40 +++++++++++++++++++ + 1 file changed, 40 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml +new file mode 100644 +index 000000000000..43eaca90d88c +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml +@@ -0,0 +1,40 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 SoC USB 2.0 PHY ++ ++maintainers: ++ - Ze Huang ++ ++properties: ++ compatible: ++ const: spacemit,k1-usb2-phy ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 0 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - "#phy-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ usb-phy@c09c0000 { ++ compatible = "spacemit,k1-usb2-phy"; ++ reg = <0xc09c0000 0x200>; ++ clocks = <&syscon_apmu 15>; ++ #phy-cells = <0>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0086-UPSTREAM-i2c-k1-add-reset-support.patch b/SPECS/linux-lts/0086-UPSTREAM-i2c-k1-add-reset-support.patch deleted file mode 100644 index a444fe362e..0000000000 --- a/SPECS/linux-lts/0086-UPSTREAM-i2c-k1-add-reset-support.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 22ab3f10aeaedca84e6ca2414362223f5873ce76 Mon Sep 17 00:00:00 2001 -From: Encrow Thorne -Date: Tue, 30 Dec 2025 23:06:52 +0800 -Subject: [PATCH 086/467] UPSTREAM: i2c: k1: add reset support - -The K1 I2C controller provides a reset line that needs to be deasserted -before the controller can be accessed. - -Add reset support to the driver to ensure the controller starts in the -required state. - -Signed-off-by: Encrow Thorne -Reviewed-by: Troy Mitchell -Signed-off-by: Andi Shyti -Link: https://lore.kernel.org/r/20251230150653.42097-2-jyc0019@gmail.com -(cherry picked from commit b96259551b337225bb0e7afb3452b98435dd8b81) -Signed-off-by: Han Gao ---- - drivers/i2c/busses/i2c-k1.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index 8ef6d5d1927b..d0948a16de3e 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+ #include - - /* spacemit i2c registers */ - #define SPACEMIT_ICR 0x0 /* Control register */ -@@ -534,6 +535,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - struct device *dev = &pdev->dev; - struct device_node *of_node = pdev->dev.of_node; - struct spacemit_i2c_dev *i2c; -+ struct reset_control *rst; - int ret; - - i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); -@@ -578,6 +580,11 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); - -+ rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); -+ if (IS_ERR(rst)) -+ return dev_err_probe(dev, PTR_ERR(rst), -+ "failed to acquire deasserted reset\n"); -+ - spacemit_i2c_reset(i2c); - - i2c_set_adapdata(&i2c->adapt, i2c); --- -2.53.0 - diff --git a/SPECS/linux-lts/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch b/SPECS/linux-lts/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch new file mode 100644 index 0000000000..dd0a27e19d --- /dev/null +++ b/SPECS/linux-lts/0086-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch @@ -0,0 +1,297 @@ +From 6fe75e59d1834ffff41681bcd52b6a1a83446f3e Mon Sep 17 00:00:00 2001 +From: Ze Huang +Date: Fri, 17 Oct 2025 22:49:53 +0800 +Subject: [RUYI PATCH] UPSTREAM: phy: spacemit: support K1 USB2.0 PHY + controller + +The SpacemiT K1 SoC includes three USB ports: + +- One USB2.0 OTG port +- One USB2.0 host-only port +- One USB3.0 port with an integrated USB2.0 DRD interface + +Each of these ports is connected to a USB2.0 PHY responsible for USB2 +transmission. + +This commit adds support for the SpacemiT K1 USB2.0 PHY, which is +compliant with the USB 2.0 specification and supports both 8-bit 60MHz +and 16-bit 30MHz parallel interfaces. + +Signed-off-by: Ze Huang +Tested-by: Aurelien Jarno +Tested-by: Junzhong Pan +Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-2-7cf9ea2477a1@linux.dev +Signed-off-by: Vinod Koul +(cherry picked from commit fe4bc1a08638309b6be1af37210930b856908eb7) +Signed-off-by: Han Gao +--- + drivers/phy/Kconfig | 1 + + drivers/phy/Makefile | 1 + + drivers/phy/spacemit/Kconfig | 13 ++ + drivers/phy/spacemit/Makefile | 2 + + drivers/phy/spacemit/phy-k1-usb2.c | 200 +++++++++++++++++++++++++++++ + 5 files changed, 217 insertions(+) + create mode 100644 drivers/phy/spacemit/Kconfig + create mode 100644 drivers/phy/spacemit/Makefile + create mode 100644 drivers/phy/spacemit/phy-k1-usb2.c + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index 1984c2e56122..95ee47f0fbc7 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -134,6 +134,7 @@ source "drivers/phy/rockchip/Kconfig" + source "drivers/phy/samsung/Kconfig" + source "drivers/phy/socionext/Kconfig" + source "drivers/phy/sophgo/Kconfig" ++source "drivers/phy/spacemit/Kconfig" + source "drivers/phy/st/Kconfig" + source "drivers/phy/starfive/Kconfig" + source "drivers/phy/sunplus/Kconfig" +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index a206133a3515..950dd4f14372 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -37,6 +37,7 @@ obj-y += allwinner/ \ + samsung/ \ + socionext/ \ + sophgo/ \ ++ spacemit/ \ + st/ \ + starfive/ \ + sunplus/ \ +diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig +new file mode 100644 +index 000000000000..0136aee2e8a2 +--- /dev/null ++++ b/drivers/phy/spacemit/Kconfig +@@ -0,0 +1,13 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++# ++# Phy drivers for SpacemiT platforms ++# ++config PHY_SPACEMIT_K1_USB2 ++ tristate "SpacemiT K1 USB 2.0 PHY support" ++ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF ++ depends on COMMON_CLK ++ depends on USB_COMMON ++ select GENERIC_PHY ++ help ++ Enable this to support K1 USB 2.0 PHY driver. This driver takes care of ++ enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. +diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile +new file mode 100644 +index 000000000000..fec0b425a948 +--- /dev/null ++++ b/drivers/phy/spacemit/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o +diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c +new file mode 100644 +index 000000000000..342061380012 +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k1-usb2.c +@@ -0,0 +1,200 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * SpacemiT K1 USB 2.0 PHY driver ++ * ++ * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd ++ * Copyright (C) 2025 Ze Huang ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PHY_RST_MODE_CTRL 0x04 ++#define PHY_PLL_RDY BIT(0) ++#define PHY_CLK_CDR_EN BIT(1) ++#define PHY_CLK_PLL_EN BIT(2) ++#define PHY_CLK_MAC_EN BIT(3) ++#define PHY_MAC_RSTN BIT(5) ++#define PHY_CDR_RSTN BIT(6) ++#define PHY_PLL_RSTN BIT(7) ++/* ++ * hs line state sel (Bit 13): ++ * - 1 (Default): Internal HS line state is set to 01 when usb_hs_tx_en is valid. ++ * - 0: Internal HS line state is always driven by usb_hs_lstate. ++ * ++ * fs line state sel (Bit 14): ++ * - 1 (Default): FS line state is determined by the output data ++ * (usb_fs_datain/b). ++ * - 0: FS line state is always determined by the input data (dmo/dpo). ++ */ ++#define PHY_HS_LINE_TX_MODE BIT(13) ++#define PHY_FS_LINE_TX_MODE BIT(14) ++ ++#define PHY_INIT_MODE_BITS (PHY_FS_LINE_TX_MODE | PHY_HS_LINE_TX_MODE) ++#define PHY_CLK_ENABLE_BITS (PHY_CLK_PLL_EN | PHY_CLK_CDR_EN | \ ++ PHY_CLK_MAC_EN) ++#define PHY_DEASSERT_RST_BITS (PHY_PLL_RSTN | PHY_CDR_RSTN | \ ++ PHY_MAC_RSTN) ++ ++#define PHY_TX_HOST_CTRL 0x10 ++#define PHY_HST_DISC_AUTO_CLR BIT(2) /* autoclear hs host disc when re-connect */ ++ ++#define PHY_HSTXP_HW_CTRL 0x34 ++#define PHY_HSTXP_RSTN BIT(2) /* generate reset for clock hstxp */ ++#define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */ ++#define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */ ++ ++#define PHY_PLL_DIV_CFG 0x98 ++#define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) ++#define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) ++#define PHY_FDIV_FRACT_20_21 BIT(12) /* fdiv_reg<21>, <20>, bit21 == bit20 */ ++/* ++ * freq_sel<1:0> ++ * if ref clk freq=24.0MHz-->freq_sel<2:0> == 3b'001, then internal divider value == 80 ++ */ ++#define PHY_FDIV_FRACT_0_1 GENMASK(14, 13) ++/* ++ * pll divider value selection ++ * 1: divider value will choose internal default value ,dependent on freq_sel<1:0> ++ * 0: divider value will be over ride by fdiv_reg<21:0> ++ */ ++#define PHY_DIV_LOCAL_EN BIT(15) ++ ++#define PHY_SEL_FREQ_24MHZ 0x01 ++#define FDIV_REG_MASK (PHY_FDIV_FRACT_20_21 | PHY_FDIV_FRACT_16_19 | \ ++ PHY_FDIV_FRACT_8_15) ++#define FDIV_REG_VAL 0x1ec4 /* 0x100 selects 24MHz, rest are default */ ++ ++#define K1_USB2PHY_RESET_TIME_MS 50 ++ ++struct spacemit_usb2phy { ++ struct phy *phy; ++ struct clk *clk; ++ struct regmap *regmap_base; ++}; ++ ++static const struct regmap_config phy_regmap_config = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ .max_register = 0x200, ++}; ++ ++static int spacemit_usb2phy_init(struct phy *phy) ++{ ++ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); ++ struct regmap *map = sphy->regmap_base; ++ u32 val; ++ int ret; ++ ++ ret = clk_enable(sphy->clk); ++ if (ret) { ++ dev_err(&phy->dev, "failed to enable clock\n"); ++ clk_disable(sphy->clk); ++ return ret; ++ } ++ ++ /* ++ * make sure the usb controller is not under reset process before ++ * any configuration ++ */ ++ usleep_range(150, 200); ++ ++ /* 24M ref clk */ ++ val = FIELD_PREP(FDIV_REG_MASK, FDIV_REG_VAL) | ++ FIELD_PREP(PHY_FDIV_FRACT_0_1, PHY_SEL_FREQ_24MHZ) | ++ PHY_DIV_LOCAL_EN; ++ regmap_write(map, PHY_PLL_DIV_CFG, val); ++ ++ ret = regmap_read_poll_timeout(map, PHY_RST_MODE_CTRL, val, ++ (val & PHY_PLL_RDY), ++ 500, K1_USB2PHY_RESET_TIME_MS * 1000); ++ if (ret) { ++ dev_err(&phy->dev, "wait PLLREADY timeout\n"); ++ clk_disable(sphy->clk); ++ return ret; ++ } ++ ++ /* release usb2 phy internal reset and enable clock gating */ ++ val = (PHY_INIT_MODE_BITS | PHY_CLK_ENABLE_BITS | PHY_DEASSERT_RST_BITS); ++ regmap_write(map, PHY_RST_MODE_CTRL, val); ++ ++ val = (PHY_HSTXP_RSTN | PHY_CLK_HSTXP_EN | PHY_HSTXP_MODE); ++ regmap_write(map, PHY_HSTXP_HW_CTRL, val); ++ ++ /* auto clear host disc */ ++ regmap_update_bits(map, PHY_TX_HOST_CTRL, PHY_HST_DISC_AUTO_CLR, ++ PHY_HST_DISC_AUTO_CLR); ++ ++ return 0; ++} ++ ++static int spacemit_usb2phy_exit(struct phy *phy) ++{ ++ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); ++ ++ clk_disable(sphy->clk); ++ ++ return 0; ++} ++ ++static const struct phy_ops spacemit_usb2phy_ops = { ++ .init = spacemit_usb2phy_init, ++ .exit = spacemit_usb2phy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++static int spacemit_usb2phy_probe(struct platform_device *pdev) ++{ ++ struct phy_provider *phy_provider; ++ struct device *dev = &pdev->dev; ++ struct spacemit_usb2phy *sphy; ++ void __iomem *base; ++ ++ sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); ++ if (!sphy) ++ return -ENOMEM; ++ ++ sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL); ++ if (IS_ERR(sphy->clk)) ++ return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ sphy->regmap_base = devm_regmap_init_mmio(dev, base, &phy_regmap_config); ++ if (IS_ERR(sphy->regmap_base)) ++ return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n"); ++ ++ sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops); ++ if (IS_ERR(sphy->phy)) ++ return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); ++ ++ phy_set_drvdata(sphy->phy, sphy); ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static const struct of_device_id spacemit_usb2phy_dt_match[] = { ++ { .compatible = "spacemit,k1-usb2-phy", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); ++ ++static struct platform_driver spacemit_usb2_phy_driver = { ++ .probe = spacemit_usb2phy_probe, ++ .driver = { ++ .name = "spacemit-usb2-phy", ++ .of_match_table = spacemit_usb2phy_dt_match, ++ }, ++}; ++module_platform_driver(spacemit_usb2_phy_driver); ++ ++MODULE_DESCRIPTION("Spacemit USB 2.0 PHY driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch b/SPECS/linux-lts/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch new file mode 100644 index 0000000000..dc4568a151 --- /dev/null +++ b/SPECS/linux-lts/0087-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch @@ -0,0 +1,44 @@ +From 11169d35e4ee7faf38d3e24da227dd6ca781964d Mon Sep 17 00:00:00 2001 +From: Ze Huang +Date: Sun, 11 Jan 2026 14:41:02 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add USB2 PHY node for K1 + +K1's DWC3 USB 3.0 controller requires two separate PHYs to function: +the USB 3.0 combophy (for SuperSpeed) and a USB 2.0 PHY (for High-Speed, +Full-Speed, etc.). + +Add node for this second USB 2.0 PHY (usbphy2). + +Tested-by: Aurelien Jarno +Signed-off-by: Ze Huang +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-1-f5ebd546e904@linux.dev +Signed-off-by: Yixun Lan +(cherry picked from commit 9d591fef025d5008f23ab339a10006b151150578) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 4c045da95d72..dfabda5ed4fa 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -429,6 +429,14 @@ i2c5: i2c@d4013800 { + status = "disabled"; + }; + ++ usbphy2: phy@c0a30000 { ++ compatible = "spacemit,k1-usb2-phy"; ++ reg = <0x0 0xc0a30000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_USB30>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + combo_phy: phy@c0b10000 { + compatible = "spacemit,k1-combo-phy"; + reg = <0x0 0xc0b10000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0087-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch b/SPECS/linux-lts/0087-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch deleted file mode 100644 index 3792ddbbb7..0000000000 --- a/SPECS/linux-lts/0087-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 44a7ef4342a13da4cdca6f3bde4e71312846a07f Mon Sep 17 00:00:00 2001 -From: Encrow Thorne -Date: Tue, 30 Dec 2025 23:06:53 +0800 -Subject: [PATCH 087/467] UPSTREAM: riscv: dts: spacemit: add reset property - -Add resets property to K1 I2C node. - -Signed-off-by: Encrow Thorne -Link: https://lore.kernel.org/r/20251230150653.42097-3-jyc0019@gmail.com -Signed-off-by: Yixun Lan -(cherry picked from commit 7d6fe7e381d2912300df06e1a7e7a6f6a9269af0) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 86d1db14e2ee..4c045da95d72 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -368,6 +368,7 @@ i2c0: i2c@d4010800 { - <&syscon_apbc CLK_TWSI0_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI0>; - interrupts = <36>; - status = "disabled"; - }; -@@ -381,6 +382,7 @@ i2c1: i2c@d4011000 { - <&syscon_apbc CLK_TWSI1_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI1>; - interrupts = <37>; - status = "disabled"; - }; -@@ -394,6 +396,7 @@ i2c2: i2c@d4012000 { - <&syscon_apbc CLK_TWSI2_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI2>; - interrupts = <38>; - status = "disabled"; - }; -@@ -407,6 +410,7 @@ i2c4: i2c@d4012800 { - <&syscon_apbc CLK_TWSI4_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI4>; - interrupts = <40>; - status = "disabled"; - }; -@@ -420,6 +424,7 @@ i2c5: i2c@d4013800 { - <&syscon_apbc CLK_TWSI5_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI5>; - interrupts = <41>; - status = "disabled"; - }; -@@ -490,6 +495,7 @@ i2c6: i2c@d4018800 { - <&syscon_apbc CLK_TWSI6_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI6>; - interrupts = <70>; - status = "disabled"; - }; -@@ -593,6 +599,7 @@ i2c7: i2c@d401d000 { - <&syscon_apbc CLK_TWSI7_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI7>; - interrupts = <18>; - status = "disabled"; - }; -@@ -606,6 +613,7 @@ i2c8: i2c@d401d800 { - <&syscon_apbc CLK_TWSI8_BUS>; - clock-names = "func", "bus"; - clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_TWSI8>; - interrupts = <19>; - status = "disabled"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0088-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch b/SPECS/linux-lts/0088-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch deleted file mode 100644 index 77424cfb1a..0000000000 --- a/SPECS/linux-lts/0088-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch +++ /dev/null @@ -1,69 +0,0 @@ -From e521f4b92c204c0a9d6242ff41c3c872440dbab8 Mon Sep 17 00:00:00 2001 -From: Ze Huang -Date: Fri, 17 Oct 2025 22:49:52 +0800 -Subject: [PATCH 088/467] UPSTREAM: dt-bindings: phy: spacemit: add K1 USB2 PHY - -Add support for USB2 PHY found on SpacemiT K1 SoC. - -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Ze Huang -Tested-by: Aurelien Jarno -Tested-by: Junzhong Pan -Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-1-7cf9ea2477a1@linux.dev -Signed-off-by: Vinod Koul -(cherry picked from commit 61b84d5b20af2a4c9944972202c1386026598928) -Signed-off-by: Han Gao ---- - .../bindings/phy/spacemit,usb2-phy.yaml | 40 +++++++++++++++++++ - 1 file changed, 40 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -new file mode 100644 -index 000000000000..43eaca90d88c ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -@@ -0,0 +1,40 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K1 SoC USB 2.0 PHY -+ -+maintainers: -+ - Ze Huang -+ -+properties: -+ compatible: -+ const: spacemit,k1-usb2-phy -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ maxItems: 1 -+ -+ "#phy-cells": -+ const: 0 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - "#phy-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ usb-phy@c09c0000 { -+ compatible = "spacemit,k1-usb2-phy"; -+ reg = <0xc09c0000 0x200>; -+ clocks = <&syscon_apmu 15>; -+ #phy-cells = <0>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch b/SPECS/linux-lts/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch new file mode 100644 index 0000000000..f327e7bfc3 --- /dev/null +++ b/SPECS/linux-lts/0088-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch @@ -0,0 +1,59 @@ +From f38cd0cdcf8e8fecf3db47eb57caf5849e92aa36 Mon Sep 17 00:00:00 2001 +From: Ze Huang +Date: Sun, 11 Jan 2026 14:41:03 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add DWC3 USB 3.0 + controller node for K1 + +Add node for the Synopsys DWC3 USB 3.0 host controller on the K1 SoC. +The controller resides on the 'storage-bus' and uses its DMA +translations. + +Tested-by: Aurelien Jarno +Signed-off-by: Ze Huang +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-2-f5ebd546e904@linux.dev +Signed-off-by: Yixun Lan +(cherry picked from commit 6e8dcd141833a23d7117fe16896f6d5dfdb2e112) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index dfabda5ed4fa..137fc26ddc29 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -1170,6 +1170,30 @@ storage-bus { + #size-cells = <2>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; + ++ usb_dwc3: usb@c0a00000 { ++ compatible = "spacemit,k1-dwc3"; ++ reg = <0x0 0xc0a00000 0x0 0x10000>; ++ clocks = <&syscon_apmu CLK_USB30>; ++ clock-names = "usbdrd30"; ++ interrupts = <125>; ++ phys = <&usbphy2>, <&combo_phy PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi"; ++ resets = <&syscon_apmu RESET_USB30_AHB>, ++ <&syscon_apmu RESET_USB30_VCC>, ++ <&syscon_apmu RESET_USB30_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ reset-delay = <2>; ++ snps,hsphy_interface = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,dis_rxdet_inp3_quirk; ++ status = "disabled"; ++ }; ++ + emmc: mmc@d4281000 { + compatible = "spacemit,k1-sdhci"; + reg = <0x0 0xd4281000 0x0 0x200>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0089-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch b/SPECS/linux-lts/0089-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch deleted file mode 100644 index 5dc7268528..0000000000 --- a/SPECS/linux-lts/0089-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch +++ /dev/null @@ -1,297 +0,0 @@ -From fcc3def145a5601559279ba46a849f87baebfb1e Mon Sep 17 00:00:00 2001 -From: Ze Huang -Date: Fri, 17 Oct 2025 22:49:53 +0800 -Subject: [PATCH 089/467] UPSTREAM: phy: spacemit: support K1 USB2.0 PHY - controller - -The SpacemiT K1 SoC includes three USB ports: - -- One USB2.0 OTG port -- One USB2.0 host-only port -- One USB3.0 port with an integrated USB2.0 DRD interface - -Each of these ports is connected to a USB2.0 PHY responsible for USB2 -transmission. - -This commit adds support for the SpacemiT K1 USB2.0 PHY, which is -compliant with the USB 2.0 specification and supports both 8-bit 60MHz -and 16-bit 30MHz parallel interfaces. - -Signed-off-by: Ze Huang -Tested-by: Aurelien Jarno -Tested-by: Junzhong Pan -Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-2-7cf9ea2477a1@linux.dev -Signed-off-by: Vinod Koul -(cherry picked from commit fe4bc1a08638309b6be1af37210930b856908eb7) -Signed-off-by: Han Gao ---- - drivers/phy/Kconfig | 1 + - drivers/phy/Makefile | 1 + - drivers/phy/spacemit/Kconfig | 13 ++ - drivers/phy/spacemit/Makefile | 2 + - drivers/phy/spacemit/phy-k1-usb2.c | 200 +++++++++++++++++++++++++++++ - 5 files changed, 217 insertions(+) - create mode 100644 drivers/phy/spacemit/Kconfig - create mode 100644 drivers/phy/spacemit/Makefile - create mode 100644 drivers/phy/spacemit/phy-k1-usb2.c - -diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig -index 1984c2e56122..95ee47f0fbc7 100644 ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -134,6 +134,7 @@ source "drivers/phy/rockchip/Kconfig" - source "drivers/phy/samsung/Kconfig" - source "drivers/phy/socionext/Kconfig" - source "drivers/phy/sophgo/Kconfig" -+source "drivers/phy/spacemit/Kconfig" - source "drivers/phy/st/Kconfig" - source "drivers/phy/starfive/Kconfig" - source "drivers/phy/sunplus/Kconfig" -diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile -index a206133a3515..950dd4f14372 100644 ---- a/drivers/phy/Makefile -+++ b/drivers/phy/Makefile -@@ -37,6 +37,7 @@ obj-y += allwinner/ \ - samsung/ \ - socionext/ \ - sophgo/ \ -+ spacemit/ \ - st/ \ - starfive/ \ - sunplus/ \ -diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig -new file mode 100644 -index 000000000000..0136aee2e8a2 ---- /dev/null -+++ b/drivers/phy/spacemit/Kconfig -@@ -0,0 +1,13 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+# -+# Phy drivers for SpacemiT platforms -+# -+config PHY_SPACEMIT_K1_USB2 -+ tristate "SpacemiT K1 USB 2.0 PHY support" -+ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF -+ depends on COMMON_CLK -+ depends on USB_COMMON -+ select GENERIC_PHY -+ help -+ Enable this to support K1 USB 2.0 PHY driver. This driver takes care of -+ enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. -diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile -new file mode 100644 -index 000000000000..fec0b425a948 ---- /dev/null -+++ b/drivers/phy/spacemit/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o -diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c -new file mode 100644 -index 000000000000..342061380012 ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k1-usb2.c -@@ -0,0 +1,200 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * SpacemiT K1 USB 2.0 PHY driver -+ * -+ * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd -+ * Copyright (C) 2025 Ze Huang -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define PHY_RST_MODE_CTRL 0x04 -+#define PHY_PLL_RDY BIT(0) -+#define PHY_CLK_CDR_EN BIT(1) -+#define PHY_CLK_PLL_EN BIT(2) -+#define PHY_CLK_MAC_EN BIT(3) -+#define PHY_MAC_RSTN BIT(5) -+#define PHY_CDR_RSTN BIT(6) -+#define PHY_PLL_RSTN BIT(7) -+/* -+ * hs line state sel (Bit 13): -+ * - 1 (Default): Internal HS line state is set to 01 when usb_hs_tx_en is valid. -+ * - 0: Internal HS line state is always driven by usb_hs_lstate. -+ * -+ * fs line state sel (Bit 14): -+ * - 1 (Default): FS line state is determined by the output data -+ * (usb_fs_datain/b). -+ * - 0: FS line state is always determined by the input data (dmo/dpo). -+ */ -+#define PHY_HS_LINE_TX_MODE BIT(13) -+#define PHY_FS_LINE_TX_MODE BIT(14) -+ -+#define PHY_INIT_MODE_BITS (PHY_FS_LINE_TX_MODE | PHY_HS_LINE_TX_MODE) -+#define PHY_CLK_ENABLE_BITS (PHY_CLK_PLL_EN | PHY_CLK_CDR_EN | \ -+ PHY_CLK_MAC_EN) -+#define PHY_DEASSERT_RST_BITS (PHY_PLL_RSTN | PHY_CDR_RSTN | \ -+ PHY_MAC_RSTN) -+ -+#define PHY_TX_HOST_CTRL 0x10 -+#define PHY_HST_DISC_AUTO_CLR BIT(2) /* autoclear hs host disc when re-connect */ -+ -+#define PHY_HSTXP_HW_CTRL 0x34 -+#define PHY_HSTXP_RSTN BIT(2) /* generate reset for clock hstxp */ -+#define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */ -+#define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */ -+ -+#define PHY_PLL_DIV_CFG 0x98 -+#define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) -+#define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) -+#define PHY_FDIV_FRACT_20_21 BIT(12) /* fdiv_reg<21>, <20>, bit21 == bit20 */ -+/* -+ * freq_sel<1:0> -+ * if ref clk freq=24.0MHz-->freq_sel<2:0> == 3b'001, then internal divider value == 80 -+ */ -+#define PHY_FDIV_FRACT_0_1 GENMASK(14, 13) -+/* -+ * pll divider value selection -+ * 1: divider value will choose internal default value ,dependent on freq_sel<1:0> -+ * 0: divider value will be over ride by fdiv_reg<21:0> -+ */ -+#define PHY_DIV_LOCAL_EN BIT(15) -+ -+#define PHY_SEL_FREQ_24MHZ 0x01 -+#define FDIV_REG_MASK (PHY_FDIV_FRACT_20_21 | PHY_FDIV_FRACT_16_19 | \ -+ PHY_FDIV_FRACT_8_15) -+#define FDIV_REG_VAL 0x1ec4 /* 0x100 selects 24MHz, rest are default */ -+ -+#define K1_USB2PHY_RESET_TIME_MS 50 -+ -+struct spacemit_usb2phy { -+ struct phy *phy; -+ struct clk *clk; -+ struct regmap *regmap_base; -+}; -+ -+static const struct regmap_config phy_regmap_config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .max_register = 0x200, -+}; -+ -+static int spacemit_usb2phy_init(struct phy *phy) -+{ -+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); -+ struct regmap *map = sphy->regmap_base; -+ u32 val; -+ int ret; -+ -+ ret = clk_enable(sphy->clk); -+ if (ret) { -+ dev_err(&phy->dev, "failed to enable clock\n"); -+ clk_disable(sphy->clk); -+ return ret; -+ } -+ -+ /* -+ * make sure the usb controller is not under reset process before -+ * any configuration -+ */ -+ usleep_range(150, 200); -+ -+ /* 24M ref clk */ -+ val = FIELD_PREP(FDIV_REG_MASK, FDIV_REG_VAL) | -+ FIELD_PREP(PHY_FDIV_FRACT_0_1, PHY_SEL_FREQ_24MHZ) | -+ PHY_DIV_LOCAL_EN; -+ regmap_write(map, PHY_PLL_DIV_CFG, val); -+ -+ ret = regmap_read_poll_timeout(map, PHY_RST_MODE_CTRL, val, -+ (val & PHY_PLL_RDY), -+ 500, K1_USB2PHY_RESET_TIME_MS * 1000); -+ if (ret) { -+ dev_err(&phy->dev, "wait PLLREADY timeout\n"); -+ clk_disable(sphy->clk); -+ return ret; -+ } -+ -+ /* release usb2 phy internal reset and enable clock gating */ -+ val = (PHY_INIT_MODE_BITS | PHY_CLK_ENABLE_BITS | PHY_DEASSERT_RST_BITS); -+ regmap_write(map, PHY_RST_MODE_CTRL, val); -+ -+ val = (PHY_HSTXP_RSTN | PHY_CLK_HSTXP_EN | PHY_HSTXP_MODE); -+ regmap_write(map, PHY_HSTXP_HW_CTRL, val); -+ -+ /* auto clear host disc */ -+ regmap_update_bits(map, PHY_TX_HOST_CTRL, PHY_HST_DISC_AUTO_CLR, -+ PHY_HST_DISC_AUTO_CLR); -+ -+ return 0; -+} -+ -+static int spacemit_usb2phy_exit(struct phy *phy) -+{ -+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); -+ -+ clk_disable(sphy->clk); -+ -+ return 0; -+} -+ -+static const struct phy_ops spacemit_usb2phy_ops = { -+ .init = spacemit_usb2phy_init, -+ .exit = spacemit_usb2phy_exit, -+ .owner = THIS_MODULE, -+}; -+ -+static int spacemit_usb2phy_probe(struct platform_device *pdev) -+{ -+ struct phy_provider *phy_provider; -+ struct device *dev = &pdev->dev; -+ struct spacemit_usb2phy *sphy; -+ void __iomem *base; -+ -+ sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); -+ if (!sphy) -+ return -ENOMEM; -+ -+ sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL); -+ if (IS_ERR(sphy->clk)) -+ return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); -+ -+ base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ sphy->regmap_base = devm_regmap_init_mmio(dev, base, &phy_regmap_config); -+ if (IS_ERR(sphy->regmap_base)) -+ return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n"); -+ -+ sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops); -+ if (IS_ERR(sphy->phy)) -+ return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); -+ -+ phy_set_drvdata(sphy->phy, sphy); -+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id spacemit_usb2phy_dt_match[] = { -+ { .compatible = "spacemit,k1-usb2-phy", }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); -+ -+static struct platform_driver spacemit_usb2_phy_driver = { -+ .probe = spacemit_usb2phy_probe, -+ .driver = { -+ .name = "spacemit-usb2-phy", -+ .of_match_table = spacemit_usb2phy_dt_match, -+ }, -+}; -+module_platform_driver(spacemit_usb2_phy_driver); -+ -+MODULE_DESCRIPTION("Spacemit USB 2.0 PHY driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch b/SPECS/linux-lts/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch new file mode 100644 index 0000000000..ada9b260b3 --- /dev/null +++ b/SPECS/linux-lts/0089-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch @@ -0,0 +1,88 @@ +From 35bdc15291717adfaa52c4c9d060b5da8fac5ddf Mon Sep 17 00:00:00 2001 +From: Ze Huang +Date: Sun, 11 Jan 2026 14:41:04 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Enable USB3.0 on + BananaPi-F3 + +Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the +Banana Pi F3 board. + +The board utilizes a VLI VL817 hub, which requires two separate power +supplies: one VBUS and one for hub itself. Add two GPIO-controlled +fixed-regulators to manage this. + +Tested-by: Aurelien Jarno +Signed-off-by: Ze Huang +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-3-f5ebd546e904@linux.dev +Signed-off-by: Yixun Lan +(cherry picked from commit c7e62c4eea026d42d192a0b86ce7313086ef2093) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 46 +++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 3f10efd925dc..5971605754b3 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -59,6 +59,25 @@ reg_vcc_4v: vcc-4v { + regulator-always-on; + vin-supply = <®_dc_in>; + }; ++ ++ usb3-vbus-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB30_VBUS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ usb3_hub_5v: usb3-hub-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB30_HUB"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; + }; + + &combo_phy { +@@ -313,3 +332,30 @@ &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub_2_0: hub@1 { ++ compatible = "usb2109,2817"; ++ reg = <0x1>; ++ vdd-supply = <&usb3_hub_5v>; ++ peer-hub = <&hub_3_0>; ++ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; ++ }; ++ ++ hub_3_0: hub@2 { ++ compatible = "usb2109,817"; ++ reg = <0x2>; ++ vdd-supply = <&usb3_hub_5v>; ++ peer-hub = <&hub_2_0>; ++ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch b/SPECS/linux-lts/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch new file mode 100644 index 0000000000..3e646a9468 --- /dev/null +++ b/SPECS/linux-lts/0090-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch @@ -0,0 +1,44 @@ +From 58100bb2e0beb94bf6f7d14ee1fbc0ba755686ab Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 2 Jan 2026 15:00:22 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pinctrl: spacemit: convert drive + strength to schema format + +In order to better extend the pinctrl support for future new SoC, convert +drive strength setting from free form text to more standard schema format. + +Signed-off-by: Yixun Lan +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Linus Walleij +(cherry picked from commit c3efac0592f88ab48c8eef028268e6514908be51) +Signed-off-by: Han Gao +--- + .../bindings/pinctrl/spacemit,k1-pinctrl.yaml | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +index d80e88aa07b4..609d7db97822 100644 +--- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml ++++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +@@ -72,10 +72,14 @@ patternProperties: + enum: [ 0, 1 ] + + drive-strength: +- description: | +- typical current when output high level. +- 1.8V output: 11, 21, 32, 42 (mA) +- 3.3V output: 7, 10, 13, 16, 19, 23, 26, 29 (mA) ++ description: ++ typical current (in mA) when the output at high level. ++ oneOf: ++ - enum: [ 11, 21, 32, 42 ] ++ description: For K1 SoC, 1.8V voltage output ++ ++ - enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ] ++ description: For K1 SoC, 3.3V voltage output + + input-schmitt: + description: | +-- +2.53.0 + diff --git a/SPECS/linux-lts/0090-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch b/SPECS/linux-lts/0090-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch deleted file mode 100644 index 091c89cba7..0000000000 --- a/SPECS/linux-lts/0090-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 70d873fa83fb580cdd0722e586b71f7d82918b64 Mon Sep 17 00:00:00 2001 -From: Ze Huang -Date: Sun, 11 Jan 2026 14:41:02 +0800 -Subject: [PATCH 090/467] UPSTREAM: riscv: dts: spacemit: Add USB2 PHY node for - K1 - -K1's DWC3 USB 3.0 controller requires two separate PHYs to function: -the USB 3.0 combophy (for SuperSpeed) and a USB 2.0 PHY (for High-Speed, -Full-Speed, etc.). - -Add node for this second USB 2.0 PHY (usbphy2). - -Tested-by: Aurelien Jarno -Signed-off-by: Ze Huang -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-1-f5ebd546e904@linux.dev -Signed-off-by: Yixun Lan -(cherry picked from commit 9d591fef025d5008f23ab339a10006b151150578) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 4c045da95d72..dfabda5ed4fa 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -429,6 +429,14 @@ i2c5: i2c@d4013800 { - status = "disabled"; - }; - -+ usbphy2: phy@c0a30000 { -+ compatible = "spacemit,k1-usb2-phy"; -+ reg = <0x0 0xc0a30000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_USB30>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - combo_phy: phy@c0b10000 { - compatible = "spacemit,k1-combo-phy"; - reg = <0x0 0xc0b10000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch b/SPECS/linux-lts/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch new file mode 100644 index 0000000000..39afc5d902 --- /dev/null +++ b/SPECS/linux-lts/0091-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch @@ -0,0 +1,51 @@ +From 2038df152864bcab073a9afa519466c854b79d21 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 2 Jan 2026 15:00:23 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pinctrl: spacemit: add K3 SoC + support + +Add new compatible string for SpacemiT K3 SoC, the pinctrl IP shares +almost same logic with previous K1 generation, but has different register +offset and pin configuration, for example the drive strength and +schmitter trigger settings has been changed. + +Signed-off-by: Yixun Lan +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Linus Walleij +(cherry picked from commit 5adaa1a8c08839617e5a6385fe05a8baa63e355f) +Signed-off-by: Han Gao +--- + .../bindings/pinctrl/spacemit,k1-pinctrl.yaml | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +index 609d7db97822..9a76cffcbaee 100644 +--- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml ++++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +@@ -11,7 +11,9 @@ maintainers: + + properties: + compatible: +- const: spacemit,k1-pinctrl ++ enum: ++ - spacemit,k1-pinctrl ++ - spacemit,k3-pinctrl + + reg: + items: +@@ -81,6 +83,12 @@ patternProperties: + - enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ] + description: For K1 SoC, 3.3V voltage output + ++ - enum: [ 2, 4, 6, 7, 9, 11, 13, 14, 21, 23, 25, 26, 28, 30, 31, 33 ] ++ description: For K3 SoC, 1.8V voltage output ++ ++ - enum: [ 3, 5, 7, 9, 11, 13, 15, 17, 25, 27, 29, 31, 33, 35, 37, 38 ] ++ description: For K3 SoC, 1.8V voltage output ++ + input-schmitt: + description: | + typical threshold for schmitt trigger. +-- +2.53.0 + diff --git a/SPECS/linux-lts/0091-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch b/SPECS/linux-lts/0091-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch deleted file mode 100644 index f42a890268..0000000000 --- a/SPECS/linux-lts/0091-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch +++ /dev/null @@ -1,59 +0,0 @@ -From b30b757a7e4570e7923bf3fcebcf0ff34a42b70c Mon Sep 17 00:00:00 2001 -From: Ze Huang -Date: Sun, 11 Jan 2026 14:41:03 +0800 -Subject: [PATCH 091/467] UPSTREAM: riscv: dts: spacemit: Add DWC3 USB 3.0 - controller node for K1 - -Add node for the Synopsys DWC3 USB 3.0 host controller on the K1 SoC. -The controller resides on the 'storage-bus' and uses its DMA -translations. - -Tested-by: Aurelien Jarno -Signed-off-by: Ze Huang -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-2-f5ebd546e904@linux.dev -Signed-off-by: Yixun Lan -(cherry picked from commit 6e8dcd141833a23d7117fe16896f6d5dfdb2e112) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 24 ++++++++++++++++++++++++ - 1 file changed, 24 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index dfabda5ed4fa..137fc26ddc29 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -1170,6 +1170,30 @@ storage-bus { - #size-cells = <2>; - dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; - -+ usb_dwc3: usb@c0a00000 { -+ compatible = "spacemit,k1-dwc3"; -+ reg = <0x0 0xc0a00000 0x0 0x10000>; -+ clocks = <&syscon_apmu CLK_USB30>; -+ clock-names = "usbdrd30"; -+ interrupts = <125>; -+ phys = <&usbphy2>, <&combo_phy PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi"; -+ resets = <&syscon_apmu RESET_USB30_AHB>, -+ <&syscon_apmu RESET_USB30_VCC>, -+ <&syscon_apmu RESET_USB30_PHY>; -+ reset-names = "ahb", "vcc", "phy"; -+ reset-delay = <2>; -+ snps,hsphy_interface = "utmi"; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ snps,dis_rxdet_inp3_quirk; -+ status = "disabled"; -+ }; -+ - emmc: mmc@d4281000 { - compatible = "spacemit,k1-sdhci"; - reg = <0x0 0xd4281000 0x0 0x200>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch b/SPECS/linux-lts/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch new file mode 100644 index 0000000000..36707ca688 --- /dev/null +++ b/SPECS/linux-lts/0092-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch @@ -0,0 +1,448 @@ +From fa64b4a9c989f85c6522c5cb06ef127c6dab3d27 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 2 Jan 2026 15:00:24 +0800 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: k3: add initial pin support + +For the pinctrl IP of SpacemiT's K3 SoC, it has different register offset +comparing with previous SoC generation, so introduce a function to do the +pin to offset mapping. Also add all the pinctrl data. + +Signed-off-by: Yixun Lan +Signed-off-by: Linus Walleij +(cherry picked from commit 7412311c4655497b6ab6dd7b802f9390f0f57dc7) +Signed-off-by: Han Gao +--- + drivers/pinctrl/spacemit/Kconfig | 4 +- + drivers/pinctrl/spacemit/pinctrl-k1.c | 354 +++++++++++++++++++++++++- + 2 files changed, 352 insertions(+), 6 deletions(-) + +diff --git a/drivers/pinctrl/spacemit/Kconfig b/drivers/pinctrl/spacemit/Kconfig +index d6f6017fd097..c021d51033d1 100644 +--- a/drivers/pinctrl/spacemit/Kconfig ++++ b/drivers/pinctrl/spacemit/Kconfig +@@ -4,7 +4,7 @@ + # + + config PINCTRL_SPACEMIT_K1 +- bool "SpacemiT K1 SoC Pinctrl driver" ++ bool "SpacemiT K1/K3 SoC Pinctrl driver" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on OF + default ARCH_SPACEMIT +@@ -12,7 +12,7 @@ config PINCTRL_SPACEMIT_K1 + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help +- Say Y to select the pinctrl driver for K1 SoC. ++ Say Y to select the pinctrl driver for K1/K3 SoC. + This pin controller allows selecting the mux function for + each pin. This driver can also be built as a module called + pinctrl-k1. +diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c +index 33af9b5791c1..441817f539e3 100644 +--- a/drivers/pinctrl/spacemit/pinctrl-k1.c ++++ b/drivers/pinctrl/spacemit/pinctrl-k1.c +@@ -66,6 +66,7 @@ struct spacemit_pinctrl_data { + const struct pinctrl_pin_desc *pins; + const struct spacemit_pin *data; + u16 npins; ++ unsigned int (*pin_to_offset)(unsigned int pin); + }; + + struct spacemit_pin_mux_config { +@@ -79,7 +80,7 @@ struct spacemit_pin_drv_strength { + }; + + /* map pin id to pinctrl register offset, refer MFPR definition */ +-static unsigned int spacemit_pin_to_offset(unsigned int pin) ++static unsigned int spacemit_k1_pin_to_offset(unsigned int pin) + { + unsigned int offset = 0; + +@@ -124,10 +125,17 @@ static unsigned int spacemit_pin_to_offset(unsigned int pin) + return offset << 2; + } + ++static unsigned int spacemit_k3_pin_to_offset(unsigned int pin) ++{ ++ unsigned int offset = pin > 130 ? (pin + 2) : pin; ++ ++ return offset << 2; ++} ++ + static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, + unsigned int pin) + { +- return pctrl->regs + spacemit_pin_to_offset(pin); ++ return pctrl->regs + pctrl->data->pin_to_offset(pin); + } + + static u16 spacemit_dt_get_pin(u32 value) +@@ -177,7 +185,7 @@ static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev, + void __iomem *reg; + u32 value; + +- seq_printf(seq, "offset: 0x%04x ", spacemit_pin_to_offset(pin)); ++ seq_printf(seq, "offset: 0x%04x ", pctrl->data->pin_to_offset(pin)); + seq_printf(seq, "type: %s ", io_type_desc[type]); + + reg = spacemit_pin_to_reg(pctrl, pin); +@@ -1042,10 +1050,348 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { + .pins = k1_pin_desc, + .data = k1_pin_data, + .npins = ARRAY_SIZE(k1_pin_desc), ++ .pin_to_offset = spacemit_k1_pin_to_offset, ++}; ++ ++static const struct pinctrl_pin_desc k3_pin_desc[] = { ++ PINCTRL_PIN(0, "GPIO_00"), ++ PINCTRL_PIN(1, "GPIO_01"), ++ PINCTRL_PIN(2, "GPIO_02"), ++ PINCTRL_PIN(3, "GPIO_03"), ++ PINCTRL_PIN(4, "GPIO_04"), ++ PINCTRL_PIN(5, "GPIO_05"), ++ PINCTRL_PIN(6, "GPIO_06"), ++ PINCTRL_PIN(7, "GPIO_07"), ++ PINCTRL_PIN(8, "GPIO_08"), ++ PINCTRL_PIN(9, "GPIO_09"), ++ PINCTRL_PIN(10, "GPIO_10"), ++ PINCTRL_PIN(11, "GPIO_11"), ++ PINCTRL_PIN(12, "GPIO_12"), ++ PINCTRL_PIN(13, "GPIO_13"), ++ PINCTRL_PIN(14, "GPIO_14"), ++ PINCTRL_PIN(15, "GPIO_15"), ++ PINCTRL_PIN(16, "GPIO_16"), ++ PINCTRL_PIN(17, "GPIO_17"), ++ PINCTRL_PIN(18, "GPIO_18"), ++ PINCTRL_PIN(19, "GPIO_19"), ++ PINCTRL_PIN(20, "GPIO_20"), ++ PINCTRL_PIN(21, "GPIO_21"), ++ PINCTRL_PIN(22, "GPIO_22"), ++ PINCTRL_PIN(23, "GPIO_23"), ++ PINCTRL_PIN(24, "GPIO_24"), ++ PINCTRL_PIN(25, "GPIO_25"), ++ PINCTRL_PIN(26, "GPIO_26"), ++ PINCTRL_PIN(27, "GPIO_27"), ++ PINCTRL_PIN(28, "GPIO_28"), ++ PINCTRL_PIN(29, "GPIO_29"), ++ PINCTRL_PIN(30, "GPIO_30"), ++ PINCTRL_PIN(31, "GPIO_31"), ++ PINCTRL_PIN(32, "GPIO_32"), ++ PINCTRL_PIN(33, "GPIO_33"), ++ PINCTRL_PIN(34, "GPIO_34"), ++ PINCTRL_PIN(35, "GPIO_35"), ++ PINCTRL_PIN(36, "GPIO_36"), ++ PINCTRL_PIN(37, "GPIO_37"), ++ PINCTRL_PIN(38, "GPIO_38"), ++ PINCTRL_PIN(39, "GPIO_39"), ++ PINCTRL_PIN(40, "GPIO_40"), ++ PINCTRL_PIN(41, "GPIO_41"), ++ PINCTRL_PIN(42, "GPIO_42"), ++ PINCTRL_PIN(43, "GPIO_43"), ++ PINCTRL_PIN(44, "GPIO_44"), ++ PINCTRL_PIN(45, "GPIO_45"), ++ PINCTRL_PIN(46, "GPIO_46"), ++ PINCTRL_PIN(47, "GPIO_47"), ++ PINCTRL_PIN(48, "GPIO_48"), ++ PINCTRL_PIN(49, "GPIO_49"), ++ PINCTRL_PIN(50, "GPIO_50"), ++ PINCTRL_PIN(51, "GPIO_51"), ++ PINCTRL_PIN(52, "GPIO_52"), ++ PINCTRL_PIN(53, "GPIO_53"), ++ PINCTRL_PIN(54, "GPIO_54"), ++ PINCTRL_PIN(55, "GPIO_55"), ++ PINCTRL_PIN(56, "GPIO_56"), ++ PINCTRL_PIN(57, "GPIO_57"), ++ PINCTRL_PIN(58, "GPIO_58"), ++ PINCTRL_PIN(59, "GPIO_59"), ++ PINCTRL_PIN(60, "GPIO_60"), ++ PINCTRL_PIN(61, "GPIO_61"), ++ PINCTRL_PIN(62, "GPIO_62"), ++ PINCTRL_PIN(63, "GPIO_63"), ++ PINCTRL_PIN(64, "GPIO_64"), ++ PINCTRL_PIN(65, "GPIO_65"), ++ PINCTRL_PIN(66, "GPIO_66"), ++ PINCTRL_PIN(67, "GPIO_67"), ++ PINCTRL_PIN(68, "GPIO_68"), ++ PINCTRL_PIN(69, "GPIO_69"), ++ PINCTRL_PIN(70, "GPIO_70"), ++ PINCTRL_PIN(71, "GPIO_71"), ++ PINCTRL_PIN(72, "GPIO_72"), ++ PINCTRL_PIN(73, "GPIO_73"), ++ PINCTRL_PIN(74, "GPIO_74"), ++ PINCTRL_PIN(75, "GPIO_75"), ++ PINCTRL_PIN(76, "GPIO_76"), ++ PINCTRL_PIN(77, "GPIO_77"), ++ PINCTRL_PIN(78, "GPIO_78"), ++ PINCTRL_PIN(79, "GPIO_79"), ++ PINCTRL_PIN(80, "GPIO_80"), ++ PINCTRL_PIN(81, "GPIO_81"), ++ PINCTRL_PIN(82, "GPIO_82"), ++ PINCTRL_PIN(83, "GPIO_83"), ++ PINCTRL_PIN(84, "GPIO_84"), ++ PINCTRL_PIN(85, "GPIO_85"), ++ PINCTRL_PIN(86, "GPIO_86"), ++ PINCTRL_PIN(87, "GPIO_87"), ++ PINCTRL_PIN(88, "GPIO_88"), ++ PINCTRL_PIN(89, "GPIO_89"), ++ PINCTRL_PIN(90, "GPIO_90"), ++ PINCTRL_PIN(91, "GPIO_91"), ++ PINCTRL_PIN(92, "GPIO_92"), ++ PINCTRL_PIN(93, "GPIO_93"), ++ PINCTRL_PIN(94, "GPIO_94"), ++ PINCTRL_PIN(95, "GPIO_95"), ++ PINCTRL_PIN(96, "GPIO_96"), ++ PINCTRL_PIN(97, "GPIO_97"), ++ PINCTRL_PIN(98, "GPIO_98"), ++ PINCTRL_PIN(99, "GPIO_99"), ++ PINCTRL_PIN(100, "GPIO_100"), ++ PINCTRL_PIN(101, "GPIO_101"), ++ PINCTRL_PIN(102, "GPIO_102"), ++ PINCTRL_PIN(103, "GPIO_103"), ++ PINCTRL_PIN(104, "GPIO_104"), ++ PINCTRL_PIN(105, "GPIO_105"), ++ PINCTRL_PIN(106, "GPIO_106"), ++ PINCTRL_PIN(107, "GPIO_107"), ++ PINCTRL_PIN(108, "GPIO_108"), ++ PINCTRL_PIN(109, "GPIO_109"), ++ PINCTRL_PIN(110, "GPIO_110"), ++ PINCTRL_PIN(111, "GPIO_111"), ++ PINCTRL_PIN(112, "GPIO_112"), ++ PINCTRL_PIN(113, "GPIO_113"), ++ PINCTRL_PIN(114, "GPIO_114"), ++ PINCTRL_PIN(115, "GPIO_115"), ++ PINCTRL_PIN(116, "GPIO_116"), ++ PINCTRL_PIN(117, "GPIO_117"), ++ PINCTRL_PIN(118, "GPIO_118"), ++ PINCTRL_PIN(119, "GPIO_119"), ++ PINCTRL_PIN(120, "GPIO_120"), ++ PINCTRL_PIN(121, "GPIO_121"), ++ PINCTRL_PIN(122, "GPIO_122"), ++ PINCTRL_PIN(123, "GPIO_123"), ++ PINCTRL_PIN(124, "GPIO_124"), ++ PINCTRL_PIN(125, "GPIO_125"), ++ PINCTRL_PIN(126, "GPIO_126"), ++ PINCTRL_PIN(127, "GPIO_127"), ++ PINCTRL_PIN(128, "PWR_SCL"), ++ PINCTRL_PIN(129, "PWR_SDA"), ++ PINCTRL_PIN(130, "VCXO_EN"), ++ PINCTRL_PIN(131, "PMIC_INT_N"), ++ PINCTRL_PIN(132, "MMC1_DAT3"), ++ PINCTRL_PIN(133, "MMC1_DAT2"), ++ PINCTRL_PIN(134, "MMC1_DAT1"), ++ PINCTRL_PIN(135, "MMC1_DAT0"), ++ PINCTRL_PIN(136, "MMC1_CMD"), ++ PINCTRL_PIN(137, "MMC1_CLK"), ++ PINCTRL_PIN(138, "QSPI_DAT0"), ++ PINCTRL_PIN(139, "QSPI_DAT1"), ++ PINCTRL_PIN(140, "QSPI_DAT2"), ++ PINCTRL_PIN(141, "QSPI_DAT3"), ++ PINCTRL_PIN(142, "QSPI_CS0"), ++ PINCTRL_PIN(143, "QSPI_CS1"), ++ PINCTRL_PIN(144, "QSPI_CLK"), ++ PINCTRL_PIN(145, "PRI_TDI"), ++ PINCTRL_PIN(146, "PRI_TMS"), ++ PINCTRL_PIN(147, "PRI_TCK"), ++ PINCTRL_PIN(148, "PRI_TDO"), ++ PINCTRL_PIN(149, "PWR_SSP_SCLK"), ++ PINCTRL_PIN(150, "PWR_SSP_FRM"), ++ PINCTRL_PIN(151, "PWR_SSP_TXD"), ++ PINCTRL_PIN(152, "PWR_SSP_RXD"), ++}; ++ ++static const struct spacemit_pin k3_pin_data[ARRAY_SIZE(k3_pin_desc)] = { ++ /* GPIO1 bank */ ++ K1_FUNC_PIN(0, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(1, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(2, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(3, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(4, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(5, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(6, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(7, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(8, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(9, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(10, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(11, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(12, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(13, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(14, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(15, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(16, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(17, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(18, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(19, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(20, 0, IO_TYPE_EXTERNAL), ++ ++ /* GPIO2 bank */ ++ K1_FUNC_PIN(21, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(22, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(23, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(24, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(25, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(26, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(27, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(28, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(29, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(30, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(31, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(32, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(33, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(34, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(35, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(36, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(37, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(38, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(39, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(40, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(41, 0, IO_TYPE_EXTERNAL), ++ ++ /* GPIO3 bank */ ++ K1_FUNC_PIN(42, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(43, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(44, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(45, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(46, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(47, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(48, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(49, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(50, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(51, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(52, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(53, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(54, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(55, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(56, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(57, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(58, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(59, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(60, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(61, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(62, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(63, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(64, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(65, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(66, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(67, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(68, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(69, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(70, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(71, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(72, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(73, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(74, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(75, 0, IO_TYPE_1V8), ++ ++ /* GPIO4 bank */ ++ K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(81, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(82, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(83, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(84, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(85, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(86, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(87, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(88, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(89, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(90, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(91, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(92, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(93, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(94, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(95, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(96, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(97, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(98, 0, IO_TYPE_EXTERNAL), ++ ++ /* GPIO5 bank */ ++ K1_FUNC_PIN(99, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(100, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(101, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(102, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(103, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(104, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(105, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(106, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(107, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(108, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(109, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(110, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(111, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(112, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(113, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(114, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(115, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(116, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(117, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(118, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(119, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(120, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(121, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(122, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(123, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(124, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(125, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(126, 0, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(127, 0, IO_TYPE_EXTERNAL), ++ ++ /* PMIC */ ++ K1_FUNC_PIN(128, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(129, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(130, 0, IO_TYPE_1V8), ++ K1_FUNC_PIN(131, 0, IO_TYPE_1V8), ++ ++ /* SD/MMC1 */ ++ K1_FUNC_PIN(132, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(133, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(134, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(135, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(136, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(137, 1, IO_TYPE_EXTERNAL), ++ ++ /* QSPI */ ++ K1_FUNC_PIN(138, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(139, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(140, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(141, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(142, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(143, 1, IO_TYPE_EXTERNAL), ++ K1_FUNC_PIN(144, 1, IO_TYPE_EXTERNAL), ++ ++ /* PMIC */ ++ K1_FUNC_PIN(145, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(146, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(147, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(148, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(149, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(150, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(151, 1, IO_TYPE_1V8), ++ K1_FUNC_PIN(152, 1, IO_TYPE_1V8), ++}; ++ ++static const struct spacemit_pinctrl_data k3_pinctrl_data = { ++ .pins = k3_pin_desc, ++ .data = k3_pin_data, ++ .npins = ARRAY_SIZE(k3_pin_desc), ++ .pin_to_offset = spacemit_k3_pin_to_offset, + }; + + static const struct of_device_id k1_pinctrl_ids[] = { + { .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data }, ++ { .compatible = "spacemit,k3-pinctrl", .data = &k3_pinctrl_data }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, k1_pinctrl_ids); +@@ -1061,5 +1407,5 @@ static struct platform_driver k1_pinctrl_driver = { + builtin_platform_driver(k1_pinctrl_driver); + + MODULE_AUTHOR("Yixun Lan "); +-MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1 SoC"); ++MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1/K3 SoC"); + MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0092-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch b/SPECS/linux-lts/0092-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch deleted file mode 100644 index 072d73ce93..0000000000 --- a/SPECS/linux-lts/0092-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 3f32c9b526efb54621fa05106172ff0a751d71c5 Mon Sep 17 00:00:00 2001 -From: Ze Huang -Date: Sun, 11 Jan 2026 14:41:04 +0800 -Subject: [PATCH 092/467] UPSTREAM: riscv: dts: spacemit: Enable USB3.0 on - BananaPi-F3 - -Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the -Banana Pi F3 board. - -The board utilizes a VLI VL817 hub, which requires two separate power -supplies: one VBUS and one for hub itself. Add two GPIO-controlled -fixed-regulators to manage this. - -Tested-by: Aurelien Jarno -Signed-off-by: Ze Huang -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-3-f5ebd546e904@linux.dev -Signed-off-by: Yixun Lan -(cherry picked from commit c7e62c4eea026d42d192a0b86ce7313086ef2093) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 46 +++++++++++++++++++ - 1 file changed, 46 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 3f10efd925dc..5971605754b3 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -59,6 +59,25 @@ reg_vcc_4v: vcc-4v { - regulator-always-on; - vin-supply = <®_dc_in>; - }; -+ -+ usb3-vbus-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "USB30_VBUS"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ usb3_hub_5v: usb3-hub-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "USB30_HUB"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; - }; - - &combo_phy { -@@ -313,3 +332,30 @@ &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ hub_2_0: hub@1 { -+ compatible = "usb2109,2817"; -+ reg = <0x1>; -+ vdd-supply = <&usb3_hub_5v>; -+ peer-hub = <&hub_3_0>; -+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; -+ }; -+ -+ hub_3_0: hub@2 { -+ compatible = "usb2109,817"; -+ reg = <0x2>; -+ vdd-supply = <&usb3_hub_5v>; -+ peer-hub = <&hub_2_0>; -+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0093-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch b/SPECS/linux-lts/0093-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch deleted file mode 100644 index 90c3f81528..0000000000 --- a/SPECS/linux-lts/0093-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch +++ /dev/null @@ -1,44 +0,0 @@ -From a74398cd1206eaac108f02079a5c123a819062fc Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 2 Jan 2026 15:00:22 +0800 -Subject: [PATCH 093/467] UPSTREAM: dt-bindings: pinctrl: spacemit: convert - drive strength to schema format - -In order to better extend the pinctrl support for future new SoC, convert -drive strength setting from free form text to more standard schema format. - -Signed-off-by: Yixun Lan -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Linus Walleij -(cherry picked from commit c3efac0592f88ab48c8eef028268e6514908be51) -Signed-off-by: Han Gao ---- - .../bindings/pinctrl/spacemit,k1-pinctrl.yaml | 12 ++++++++---- - 1 file changed, 8 insertions(+), 4 deletions(-) - -diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -index d80e88aa07b4..609d7db97822 100644 ---- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -+++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -@@ -72,10 +72,14 @@ patternProperties: - enum: [ 0, 1 ] - - drive-strength: -- description: | -- typical current when output high level. -- 1.8V output: 11, 21, 32, 42 (mA) -- 3.3V output: 7, 10, 13, 16, 19, 23, 26, 29 (mA) -+ description: -+ typical current (in mA) when the output at high level. -+ oneOf: -+ - enum: [ 11, 21, 32, 42 ] -+ description: For K1 SoC, 1.8V voltage output -+ -+ - enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ] -+ description: For K1 SoC, 3.3V voltage output - - input-schmitt: - description: | --- -2.53.0 - diff --git a/SPECS/linux-lts/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch b/SPECS/linux-lts/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch new file mode 100644 index 0000000000..1885c27345 --- /dev/null +++ b/SPECS/linux-lts/0093-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch @@ -0,0 +1,325 @@ +From 57250a2d8e90085ff17ab7670d16519f41b64f28 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 2 Jan 2026 15:00:25 +0800 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: k3: adjust drive strength + and schmitter trigger + +K3 SoC expand drive strength to 4 bits which support even larger +settings table comparing to old SoC generation. Also schmitter trigger +setting is changed to 1 bit. + +Signed-off-by: Yixun Lan +Signed-off-by: Linus Walleij +(cherry picked from commit 3f20bdf7151834547a85231c28538f49601481ee) +Signed-off-by: Han Gao +--- + drivers/pinctrl/spacemit/pinctrl-k1.c | 163 ++++++++++++++++++-------- + 1 file changed, 116 insertions(+), 47 deletions(-) + +diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c +index 441817f539e3..07267c5f0f44 100644 +--- a/drivers/pinctrl/spacemit/pinctrl-k1.c ++++ b/drivers/pinctrl/spacemit/pinctrl-k1.c +@@ -24,11 +24,12 @@ + #include "pinctrl-k1.h" + + /* +- * +---------+----------+-----------+--------+--------+----------+--------+ +- * | pull | drive | schmitter | slew | edge | strong | mux | +- * | up/down | strength | trigger | rate | detect | pull | mode | +- * +---------+----------+-----------+--------+--------+----------+--------+ +- * 3 bits 3 bits 2 bits 1 bit 3 bits 1 bit 3 bits ++ * | pull | drive | schmitter | slew | edge | strong | mux | ++ * SoC | up/down | strength | trigger | rate | detect | pull | mode | ++ *-----+---------+----------+-----------+-------+--------+--------+--------+ ++ * K1 | 3 bits | 3 bits | 2 bits | 1 bit | 3 bits | 1 bit | 3 bits | ++ *-----+---------+----------+-----------+-------+--------+--------+--------+ ++ * K3 | 3 bits | 4 bits | 1 bits | 1 bit | 3 bits | 1 bit | 3 bits | + */ + + #define PAD_MUX GENMASK(2, 0) +@@ -38,12 +39,29 @@ + #define PAD_EDGE_CLEAR BIT(6) + #define PAD_SLEW_RATE GENMASK(12, 11) + #define PAD_SLEW_RATE_EN BIT(7) +-#define PAD_SCHMITT GENMASK(9, 8) +-#define PAD_DRIVE GENMASK(12, 10) ++#define PAD_SCHMITT_K1 GENMASK(9, 8) ++#define PAD_DRIVE_K1 GENMASK(12, 10) ++#define PAD_SCHMITT_K3 BIT(8) ++#define PAD_DRIVE_K3 GENMASK(12, 9) + #define PAD_PULLDOWN BIT(13) + #define PAD_PULLUP BIT(14) + #define PAD_PULL_EN BIT(15) + ++struct spacemit_pin_drv_strength { ++ u8 val; ++ u32 mA; ++}; ++ ++struct spacemit_pinctrl_dconf { ++ u64 schmitt_mask; ++ u64 drive_mask; ++ ++ struct spacemit_pin_drv_strength *ds_1v8_tbl; ++ size_t ds_1v8_tbl_num; ++ struct spacemit_pin_drv_strength *ds_3v3_tbl; ++ size_t ds_3v3_tbl_num; ++}; ++ + struct spacemit_pin { + u16 pin; + u16 flags; +@@ -67,6 +85,7 @@ struct spacemit_pinctrl_data { + const struct spacemit_pin *data; + u16 npins; + unsigned int (*pin_to_offset)(unsigned int pin); ++ const struct spacemit_pinctrl_dconf *dconf; + }; + + struct spacemit_pin_mux_config { +@@ -74,11 +93,6 @@ struct spacemit_pin_mux_config { + u32 config; + }; + +-struct spacemit_pin_drv_strength { +- u8 val; +- u32 mA; +-}; +- + /* map pin id to pinctrl register offset, refer MFPR definition */ + static unsigned int spacemit_k1_pin_to_offset(unsigned int pin) + { +@@ -193,23 +207,70 @@ static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev, + seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value); + } + +-/* use IO high level output current as the table */ +-static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = { +- { 0, 11 }, +- { 2, 21 }, +- { 4, 32 }, +- { 6, 42 }, ++static const struct spacemit_pinctrl_dconf k1_drive_conf = { ++ .drive_mask = PAD_DRIVE_K1, ++ .schmitt_mask = PAD_SCHMITT_K1, ++ .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) { ++ { 0, 11 }, ++ { 2, 21 }, ++ { 4, 32 }, ++ { 6, 42 }, ++ }, ++ .ds_1v8_tbl_num = 4, ++ .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) { ++ { 0, 7 }, ++ { 2, 10 }, ++ { 4, 13 }, ++ { 6, 16 }, ++ { 1, 19 }, ++ { 3, 23 }, ++ { 5, 26 }, ++ { 7, 29 }, ++ }, ++ .ds_3v3_tbl_num = 8, + }; + +-static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = { +- { 0, 7 }, +- { 2, 10 }, +- { 4, 13 }, +- { 6, 16 }, +- { 1, 19 }, +- { 3, 23 }, +- { 5, 26 }, +- { 7, 29 }, ++static const struct spacemit_pinctrl_dconf k3_drive_conf = { ++ .drive_mask = PAD_DRIVE_K3, ++ .schmitt_mask = PAD_SCHMITT_K3, ++ .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) { ++ { 0, 2 }, ++ { 1, 4 }, ++ { 2, 6 }, ++ { 3, 7 }, ++ { 4, 9 }, ++ { 5, 11 }, ++ { 6, 13 }, ++ { 7, 14 }, ++ { 8, 21 }, ++ { 9, 23 }, ++ { 10, 25 }, ++ { 11, 26 }, ++ { 12, 28 }, ++ { 13, 30 }, ++ { 14, 31 }, ++ { 15, 33 }, ++ }, ++ .ds_1v8_tbl_num = 16, ++ .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) { ++ { 0, 3 }, ++ { 1, 5 }, ++ { 2, 7 }, ++ { 3, 9 }, ++ { 4, 11 }, ++ { 5, 13 }, ++ { 6, 15 }, ++ { 7, 17 }, ++ { 8, 25 }, ++ { 9, 27 }, ++ { 10, 29 }, ++ { 11, 31 }, ++ { 12, 33 }, ++ { 13, 35 }, ++ { 14, 37 }, ++ { 15, 38 }, ++ }, ++ .ds_3v3_tbl_num = 16, + }; + + static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl, +@@ -237,16 +298,17 @@ static inline u32 spacemit_get_ds_mA(struct spacemit_pin_drv_strength *tbl, + } + + static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type, ++ const struct spacemit_pinctrl_dconf *dconf, + u32 mA) + { + switch (type) { + case IO_TYPE_1V8: +- return spacemit_get_ds_value(spacemit_ds_1v8_tbl, +- ARRAY_SIZE(spacemit_ds_1v8_tbl), ++ return spacemit_get_ds_value(dconf->ds_1v8_tbl, ++ dconf->ds_1v8_tbl_num, + mA); + case IO_TYPE_3V3: +- return spacemit_get_ds_value(spacemit_ds_3v3_tbl, +- ARRAY_SIZE(spacemit_ds_3v3_tbl), ++ return spacemit_get_ds_value(dconf->ds_3v3_tbl, ++ dconf->ds_3v3_tbl_num, + mA); + default: + return 0; +@@ -254,16 +316,17 @@ static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type, + } + + static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type, ++ const struct spacemit_pinctrl_dconf *dconf, + u32 value) + { + switch (type) { + case IO_TYPE_1V8: +- return spacemit_get_ds_mA(spacemit_ds_1v8_tbl, +- ARRAY_SIZE(spacemit_ds_1v8_tbl), +- value & 0x6); ++ return spacemit_get_ds_mA(dconf->ds_1v8_tbl, ++ dconf->ds_1v8_tbl_num, ++ value); + case IO_TYPE_3V3: +- return spacemit_get_ds_mA(spacemit_ds_3v3_tbl, +- ARRAY_SIZE(spacemit_ds_3v3_tbl), ++ return spacemit_get_ds_mA(dconf->ds_3v3_tbl, ++ dconf->ds_3v3_tbl_num, + value); + default: + return 0; +@@ -510,6 +573,7 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, + #define ENABLE_DRV_STRENGTH BIT(1) + #define ENABLE_SLEW_RATE BIT(2) + static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, ++ const struct spacemit_pinctrl_dconf *dconf, + unsigned long *configs, + unsigned int num_configs, + u32 *value) +@@ -547,8 +611,8 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, + drv_strength = arg; + break; + case PIN_CONFIG_INPUT_SCHMITT: +- v &= ~PAD_SCHMITT; +- v |= FIELD_PREP(PAD_SCHMITT, arg); ++ v &= ~dconf->schmitt_mask; ++ v |= (arg << __ffs(dconf->schmitt_mask)) & dconf->schmitt_mask; + break; + case PIN_CONFIG_POWER_SOURCE: + voltage = arg; +@@ -584,10 +648,10 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, + } + } + +- val = spacemit_get_driver_strength(type, drv_strength); ++ val = spacemit_get_driver_strength(type, dconf, drv_strength); + +- v &= ~PAD_DRIVE; +- v |= FIELD_PREP(PAD_DRIVE, val); ++ v &= ~dconf->drive_mask; ++ v |= (val << __ffs(dconf->drive_mask)) & dconf->drive_mask; + } + + if (flag & ENABLE_SLEW_RATE) { +@@ -637,7 +701,8 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + u32 value; + +- if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) ++ if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, ++ configs, num_configs, &value)) + return -EINVAL; + + return spacemit_pin_set_config(pctrl, pin, value); +@@ -659,7 +724,8 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, + return -EINVAL; + + spin = spacemit_get_pin(pctrl, group->grp.pins[0]); +- if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) ++ if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, ++ configs, num_configs, &value)) + return -EINVAL; + + for (i = 0; i < group->grp.npins; i++) +@@ -693,6 +759,7 @@ static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *seq, unsigned int pin) + { + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); ++ const struct spacemit_pinctrl_dconf *dconf = pctrl->data->dconf; + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin); + void __iomem *reg = spacemit_pin_to_reg(pctrl, pin); +@@ -703,17 +770,17 @@ static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev, + + seq_printf(seq, ", io type (%s)", io_type_desc[type]); + +- tmp = FIELD_GET(PAD_DRIVE, value); ++ tmp = (value & dconf->drive_mask) >> __ffs(dconf->drive_mask); + if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) { +- mA = spacemit_get_drive_strength_mA(type, tmp); ++ mA = spacemit_get_drive_strength_mA(type, dconf, tmp); + seq_printf(seq, ", drive strength (%d mA)", mA); + } + + /* drive strength depend on power source, so show all values */ + if (type == IO_TYPE_EXTERNAL) + seq_printf(seq, ", drive strength (%d or %d mA)", +- spacemit_get_drive_strength_mA(IO_TYPE_1V8, tmp), +- spacemit_get_drive_strength_mA(IO_TYPE_3V3, tmp)); ++ spacemit_get_drive_strength_mA(IO_TYPE_1V8, dconf, tmp), ++ spacemit_get_drive_strength_mA(IO_TYPE_3V3, dconf, tmp)); + + seq_printf(seq, ", register (0x%04x)", value); + } +@@ -1051,6 +1118,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { + .data = k1_pin_data, + .npins = ARRAY_SIZE(k1_pin_desc), + .pin_to_offset = spacemit_k1_pin_to_offset, ++ .dconf = &k1_drive_conf, + }; + + static const struct pinctrl_pin_desc k3_pin_desc[] = { +@@ -1387,6 +1455,7 @@ static const struct spacemit_pinctrl_data k3_pinctrl_data = { + .data = k3_pin_data, + .npins = ARRAY_SIZE(k3_pin_desc), + .pin_to_offset = spacemit_k3_pin_to_offset, ++ .dconf = &k3_drive_conf, + }; + + static const struct of_device_id k1_pinctrl_ids[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch b/SPECS/linux-lts/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch deleted file mode 100644 index 7ec035b202..0000000000 --- a/SPECS/linux-lts/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 37ffcc8cf5dbf1d1553b54b67b39e8f7728b2714 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 2 Jan 2026 15:00:23 +0800 -Subject: [PATCH 094/467] UPSTREAM: dt-bindings: pinctrl: spacemit: add K3 SoC - support - -Add new compatible string for SpacemiT K3 SoC, the pinctrl IP shares -almost same logic with previous K1 generation, but has different register -offset and pin configuration, for example the drive strength and -schmitter trigger settings has been changed. - -Signed-off-by: Yixun Lan -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Linus Walleij -(cherry picked from commit 5adaa1a8c08839617e5a6385fe05a8baa63e355f) -Signed-off-by: Han Gao ---- - .../bindings/pinctrl/spacemit,k1-pinctrl.yaml | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -index 609d7db97822..9a76cffcbaee 100644 ---- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -+++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -@@ -11,7 +11,9 @@ maintainers: - - properties: - compatible: -- const: spacemit,k1-pinctrl -+ enum: -+ - spacemit,k1-pinctrl -+ - spacemit,k3-pinctrl - - reg: - items: -@@ -81,6 +83,12 @@ patternProperties: - - enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ] - description: For K1 SoC, 3.3V voltage output - -+ - enum: [ 2, 4, 6, 7, 9, 11, 13, 14, 21, 23, 25, 26, 28, 30, 31, 33 ] -+ description: For K3 SoC, 1.8V voltage output -+ -+ - enum: [ 3, 5, 7, 9, 11, 13, 15, 17, 25, 27, 29, 31, 33, 35, 37, 38 ] -+ description: For K3 SoC, 1.8V voltage output -+ - input-schmitt: - description: | - typical threshold for schmitt trigger. --- -2.53.0 - diff --git a/SPECS/linux-lts/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch b/SPECS/linux-lts/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch new file mode 100644 index 0000000000..b203991c2d --- /dev/null +++ b/SPECS/linux-lts/0094-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch @@ -0,0 +1,49 @@ +From f3a4b85d5279965fc53d7163a005b2e64ff1327a Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 14:42:38 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: pinctrl: spacemit: add syscon + property + +In order to access the protected IO power domain registers, a valid +unlock sequence must be performed by writing the required keys to the +AIB Secure Access Register (ASAR). + +The ASAR register resides within the APBC register address space. +A corresponding syscon property is added to allow the pinctrl driver +to access this register. + +Signed-off-by: Troy Mitchell +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Linus Walleij +(cherry picked from commit e817f0223d78818cd6c0e3480355c9a9cfbc0096) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +index 9a76cffcbaee..141dcedb81fb 100644 +--- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml ++++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml +@@ -32,6 +32,10 @@ properties: + resets: + maxItems: 1 + ++ spacemit,apbc: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: Phandle to syscon that access the protected register ++ + patternProperties: + '-cfg$': + type: object +@@ -138,6 +142,7 @@ examples: + clocks = <&syscon_apbc 42>, + <&syscon_apbc 94>; + clock-names = "func", "bus"; ++ spacemit,apbc = <&syscon_apbc>; + + uart0_2_cfg: uart0-2-cfg { + uart0-2-pins { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0095-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch b/SPECS/linux-lts/0095-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch deleted file mode 100644 index a3919c7994..0000000000 --- a/SPECS/linux-lts/0095-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch +++ /dev/null @@ -1,449 +0,0 @@ -From 33f3e51747fc087ba55c240d5d94baeb18d26db3 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 2 Jan 2026 15:00:24 +0800 -Subject: [PATCH 095/467] UPSTREAM: pinctrl: spacemit: k3: add initial pin - support - -For the pinctrl IP of SpacemiT's K3 SoC, it has different register offset -comparing with previous SoC generation, so introduce a function to do the -pin to offset mapping. Also add all the pinctrl data. - -Signed-off-by: Yixun Lan -Signed-off-by: Linus Walleij -(cherry picked from commit 7412311c4655497b6ab6dd7b802f9390f0f57dc7) -Signed-off-by: Han Gao ---- - drivers/pinctrl/spacemit/Kconfig | 4 +- - drivers/pinctrl/spacemit/pinctrl-k1.c | 354 +++++++++++++++++++++++++- - 2 files changed, 352 insertions(+), 6 deletions(-) - -diff --git a/drivers/pinctrl/spacemit/Kconfig b/drivers/pinctrl/spacemit/Kconfig -index d6f6017fd097..c021d51033d1 100644 ---- a/drivers/pinctrl/spacemit/Kconfig -+++ b/drivers/pinctrl/spacemit/Kconfig -@@ -4,7 +4,7 @@ - # - - config PINCTRL_SPACEMIT_K1 -- bool "SpacemiT K1 SoC Pinctrl driver" -+ bool "SpacemiT K1/K3 SoC Pinctrl driver" - depends on ARCH_SPACEMIT || COMPILE_TEST - depends on OF - default ARCH_SPACEMIT -@@ -12,7 +12,7 @@ config PINCTRL_SPACEMIT_K1 - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF - help -- Say Y to select the pinctrl driver for K1 SoC. -+ Say Y to select the pinctrl driver for K1/K3 SoC. - This pin controller allows selecting the mux function for - each pin. This driver can also be built as a module called - pinctrl-k1. -diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c -index 33af9b5791c1..441817f539e3 100644 ---- a/drivers/pinctrl/spacemit/pinctrl-k1.c -+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c -@@ -66,6 +66,7 @@ struct spacemit_pinctrl_data { - const struct pinctrl_pin_desc *pins; - const struct spacemit_pin *data; - u16 npins; -+ unsigned int (*pin_to_offset)(unsigned int pin); - }; - - struct spacemit_pin_mux_config { -@@ -79,7 +80,7 @@ struct spacemit_pin_drv_strength { - }; - - /* map pin id to pinctrl register offset, refer MFPR definition */ --static unsigned int spacemit_pin_to_offset(unsigned int pin) -+static unsigned int spacemit_k1_pin_to_offset(unsigned int pin) - { - unsigned int offset = 0; - -@@ -124,10 +125,17 @@ static unsigned int spacemit_pin_to_offset(unsigned int pin) - return offset << 2; - } - -+static unsigned int spacemit_k3_pin_to_offset(unsigned int pin) -+{ -+ unsigned int offset = pin > 130 ? (pin + 2) : pin; -+ -+ return offset << 2; -+} -+ - static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, - unsigned int pin) - { -- return pctrl->regs + spacemit_pin_to_offset(pin); -+ return pctrl->regs + pctrl->data->pin_to_offset(pin); - } - - static u16 spacemit_dt_get_pin(u32 value) -@@ -177,7 +185,7 @@ static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev, - void __iomem *reg; - u32 value; - -- seq_printf(seq, "offset: 0x%04x ", spacemit_pin_to_offset(pin)); -+ seq_printf(seq, "offset: 0x%04x ", pctrl->data->pin_to_offset(pin)); - seq_printf(seq, "type: %s ", io_type_desc[type]); - - reg = spacemit_pin_to_reg(pctrl, pin); -@@ -1042,10 +1050,348 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { - .pins = k1_pin_desc, - .data = k1_pin_data, - .npins = ARRAY_SIZE(k1_pin_desc), -+ .pin_to_offset = spacemit_k1_pin_to_offset, -+}; -+ -+static const struct pinctrl_pin_desc k3_pin_desc[] = { -+ PINCTRL_PIN(0, "GPIO_00"), -+ PINCTRL_PIN(1, "GPIO_01"), -+ PINCTRL_PIN(2, "GPIO_02"), -+ PINCTRL_PIN(3, "GPIO_03"), -+ PINCTRL_PIN(4, "GPIO_04"), -+ PINCTRL_PIN(5, "GPIO_05"), -+ PINCTRL_PIN(6, "GPIO_06"), -+ PINCTRL_PIN(7, "GPIO_07"), -+ PINCTRL_PIN(8, "GPIO_08"), -+ PINCTRL_PIN(9, "GPIO_09"), -+ PINCTRL_PIN(10, "GPIO_10"), -+ PINCTRL_PIN(11, "GPIO_11"), -+ PINCTRL_PIN(12, "GPIO_12"), -+ PINCTRL_PIN(13, "GPIO_13"), -+ PINCTRL_PIN(14, "GPIO_14"), -+ PINCTRL_PIN(15, "GPIO_15"), -+ PINCTRL_PIN(16, "GPIO_16"), -+ PINCTRL_PIN(17, "GPIO_17"), -+ PINCTRL_PIN(18, "GPIO_18"), -+ PINCTRL_PIN(19, "GPIO_19"), -+ PINCTRL_PIN(20, "GPIO_20"), -+ PINCTRL_PIN(21, "GPIO_21"), -+ PINCTRL_PIN(22, "GPIO_22"), -+ PINCTRL_PIN(23, "GPIO_23"), -+ PINCTRL_PIN(24, "GPIO_24"), -+ PINCTRL_PIN(25, "GPIO_25"), -+ PINCTRL_PIN(26, "GPIO_26"), -+ PINCTRL_PIN(27, "GPIO_27"), -+ PINCTRL_PIN(28, "GPIO_28"), -+ PINCTRL_PIN(29, "GPIO_29"), -+ PINCTRL_PIN(30, "GPIO_30"), -+ PINCTRL_PIN(31, "GPIO_31"), -+ PINCTRL_PIN(32, "GPIO_32"), -+ PINCTRL_PIN(33, "GPIO_33"), -+ PINCTRL_PIN(34, "GPIO_34"), -+ PINCTRL_PIN(35, "GPIO_35"), -+ PINCTRL_PIN(36, "GPIO_36"), -+ PINCTRL_PIN(37, "GPIO_37"), -+ PINCTRL_PIN(38, "GPIO_38"), -+ PINCTRL_PIN(39, "GPIO_39"), -+ PINCTRL_PIN(40, "GPIO_40"), -+ PINCTRL_PIN(41, "GPIO_41"), -+ PINCTRL_PIN(42, "GPIO_42"), -+ PINCTRL_PIN(43, "GPIO_43"), -+ PINCTRL_PIN(44, "GPIO_44"), -+ PINCTRL_PIN(45, "GPIO_45"), -+ PINCTRL_PIN(46, "GPIO_46"), -+ PINCTRL_PIN(47, "GPIO_47"), -+ PINCTRL_PIN(48, "GPIO_48"), -+ PINCTRL_PIN(49, "GPIO_49"), -+ PINCTRL_PIN(50, "GPIO_50"), -+ PINCTRL_PIN(51, "GPIO_51"), -+ PINCTRL_PIN(52, "GPIO_52"), -+ PINCTRL_PIN(53, "GPIO_53"), -+ PINCTRL_PIN(54, "GPIO_54"), -+ PINCTRL_PIN(55, "GPIO_55"), -+ PINCTRL_PIN(56, "GPIO_56"), -+ PINCTRL_PIN(57, "GPIO_57"), -+ PINCTRL_PIN(58, "GPIO_58"), -+ PINCTRL_PIN(59, "GPIO_59"), -+ PINCTRL_PIN(60, "GPIO_60"), -+ PINCTRL_PIN(61, "GPIO_61"), -+ PINCTRL_PIN(62, "GPIO_62"), -+ PINCTRL_PIN(63, "GPIO_63"), -+ PINCTRL_PIN(64, "GPIO_64"), -+ PINCTRL_PIN(65, "GPIO_65"), -+ PINCTRL_PIN(66, "GPIO_66"), -+ PINCTRL_PIN(67, "GPIO_67"), -+ PINCTRL_PIN(68, "GPIO_68"), -+ PINCTRL_PIN(69, "GPIO_69"), -+ PINCTRL_PIN(70, "GPIO_70"), -+ PINCTRL_PIN(71, "GPIO_71"), -+ PINCTRL_PIN(72, "GPIO_72"), -+ PINCTRL_PIN(73, "GPIO_73"), -+ PINCTRL_PIN(74, "GPIO_74"), -+ PINCTRL_PIN(75, "GPIO_75"), -+ PINCTRL_PIN(76, "GPIO_76"), -+ PINCTRL_PIN(77, "GPIO_77"), -+ PINCTRL_PIN(78, "GPIO_78"), -+ PINCTRL_PIN(79, "GPIO_79"), -+ PINCTRL_PIN(80, "GPIO_80"), -+ PINCTRL_PIN(81, "GPIO_81"), -+ PINCTRL_PIN(82, "GPIO_82"), -+ PINCTRL_PIN(83, "GPIO_83"), -+ PINCTRL_PIN(84, "GPIO_84"), -+ PINCTRL_PIN(85, "GPIO_85"), -+ PINCTRL_PIN(86, "GPIO_86"), -+ PINCTRL_PIN(87, "GPIO_87"), -+ PINCTRL_PIN(88, "GPIO_88"), -+ PINCTRL_PIN(89, "GPIO_89"), -+ PINCTRL_PIN(90, "GPIO_90"), -+ PINCTRL_PIN(91, "GPIO_91"), -+ PINCTRL_PIN(92, "GPIO_92"), -+ PINCTRL_PIN(93, "GPIO_93"), -+ PINCTRL_PIN(94, "GPIO_94"), -+ PINCTRL_PIN(95, "GPIO_95"), -+ PINCTRL_PIN(96, "GPIO_96"), -+ PINCTRL_PIN(97, "GPIO_97"), -+ PINCTRL_PIN(98, "GPIO_98"), -+ PINCTRL_PIN(99, "GPIO_99"), -+ PINCTRL_PIN(100, "GPIO_100"), -+ PINCTRL_PIN(101, "GPIO_101"), -+ PINCTRL_PIN(102, "GPIO_102"), -+ PINCTRL_PIN(103, "GPIO_103"), -+ PINCTRL_PIN(104, "GPIO_104"), -+ PINCTRL_PIN(105, "GPIO_105"), -+ PINCTRL_PIN(106, "GPIO_106"), -+ PINCTRL_PIN(107, "GPIO_107"), -+ PINCTRL_PIN(108, "GPIO_108"), -+ PINCTRL_PIN(109, "GPIO_109"), -+ PINCTRL_PIN(110, "GPIO_110"), -+ PINCTRL_PIN(111, "GPIO_111"), -+ PINCTRL_PIN(112, "GPIO_112"), -+ PINCTRL_PIN(113, "GPIO_113"), -+ PINCTRL_PIN(114, "GPIO_114"), -+ PINCTRL_PIN(115, "GPIO_115"), -+ PINCTRL_PIN(116, "GPIO_116"), -+ PINCTRL_PIN(117, "GPIO_117"), -+ PINCTRL_PIN(118, "GPIO_118"), -+ PINCTRL_PIN(119, "GPIO_119"), -+ PINCTRL_PIN(120, "GPIO_120"), -+ PINCTRL_PIN(121, "GPIO_121"), -+ PINCTRL_PIN(122, "GPIO_122"), -+ PINCTRL_PIN(123, "GPIO_123"), -+ PINCTRL_PIN(124, "GPIO_124"), -+ PINCTRL_PIN(125, "GPIO_125"), -+ PINCTRL_PIN(126, "GPIO_126"), -+ PINCTRL_PIN(127, "GPIO_127"), -+ PINCTRL_PIN(128, "PWR_SCL"), -+ PINCTRL_PIN(129, "PWR_SDA"), -+ PINCTRL_PIN(130, "VCXO_EN"), -+ PINCTRL_PIN(131, "PMIC_INT_N"), -+ PINCTRL_PIN(132, "MMC1_DAT3"), -+ PINCTRL_PIN(133, "MMC1_DAT2"), -+ PINCTRL_PIN(134, "MMC1_DAT1"), -+ PINCTRL_PIN(135, "MMC1_DAT0"), -+ PINCTRL_PIN(136, "MMC1_CMD"), -+ PINCTRL_PIN(137, "MMC1_CLK"), -+ PINCTRL_PIN(138, "QSPI_DAT0"), -+ PINCTRL_PIN(139, "QSPI_DAT1"), -+ PINCTRL_PIN(140, "QSPI_DAT2"), -+ PINCTRL_PIN(141, "QSPI_DAT3"), -+ PINCTRL_PIN(142, "QSPI_CS0"), -+ PINCTRL_PIN(143, "QSPI_CS1"), -+ PINCTRL_PIN(144, "QSPI_CLK"), -+ PINCTRL_PIN(145, "PRI_TDI"), -+ PINCTRL_PIN(146, "PRI_TMS"), -+ PINCTRL_PIN(147, "PRI_TCK"), -+ PINCTRL_PIN(148, "PRI_TDO"), -+ PINCTRL_PIN(149, "PWR_SSP_SCLK"), -+ PINCTRL_PIN(150, "PWR_SSP_FRM"), -+ PINCTRL_PIN(151, "PWR_SSP_TXD"), -+ PINCTRL_PIN(152, "PWR_SSP_RXD"), -+}; -+ -+static const struct spacemit_pin k3_pin_data[ARRAY_SIZE(k3_pin_desc)] = { -+ /* GPIO1 bank */ -+ K1_FUNC_PIN(0, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(1, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(2, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(3, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(4, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(5, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(6, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(7, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(8, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(9, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(10, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(11, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(12, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(13, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(14, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(15, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(16, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(17, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(18, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(19, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(20, 0, IO_TYPE_EXTERNAL), -+ -+ /* GPIO2 bank */ -+ K1_FUNC_PIN(21, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(22, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(23, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(24, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(25, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(26, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(27, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(28, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(29, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(30, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(31, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(32, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(33, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(34, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(35, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(36, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(37, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(38, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(39, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(40, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(41, 0, IO_TYPE_EXTERNAL), -+ -+ /* GPIO3 bank */ -+ K1_FUNC_PIN(42, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(43, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(44, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(45, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(46, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(47, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(48, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(49, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(50, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(51, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(52, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(53, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(54, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(55, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(56, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(57, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(58, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(59, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(60, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(61, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(62, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(63, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(64, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(65, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(66, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(67, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(68, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(69, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(70, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(71, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(72, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(73, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(74, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(75, 0, IO_TYPE_1V8), -+ -+ /* GPIO4 bank */ -+ K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(81, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(82, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(83, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(84, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(85, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(86, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(87, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(88, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(89, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(90, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(91, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(92, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(93, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(94, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(95, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(96, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(97, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(98, 0, IO_TYPE_EXTERNAL), -+ -+ /* GPIO5 bank */ -+ K1_FUNC_PIN(99, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(100, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(101, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(102, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(103, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(104, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(105, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(106, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(107, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(108, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(109, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(110, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(111, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(112, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(113, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(114, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(115, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(116, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(117, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(118, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(119, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(120, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(121, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(122, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(123, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(124, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(125, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(126, 0, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(127, 0, IO_TYPE_EXTERNAL), -+ -+ /* PMIC */ -+ K1_FUNC_PIN(128, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(129, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(130, 0, IO_TYPE_1V8), -+ K1_FUNC_PIN(131, 0, IO_TYPE_1V8), -+ -+ /* SD/MMC1 */ -+ K1_FUNC_PIN(132, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(133, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(134, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(135, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(136, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(137, 1, IO_TYPE_EXTERNAL), -+ -+ /* QSPI */ -+ K1_FUNC_PIN(138, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(139, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(140, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(141, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(142, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(143, 1, IO_TYPE_EXTERNAL), -+ K1_FUNC_PIN(144, 1, IO_TYPE_EXTERNAL), -+ -+ /* PMIC */ -+ K1_FUNC_PIN(145, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(146, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(147, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(148, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(149, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(150, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(151, 1, IO_TYPE_1V8), -+ K1_FUNC_PIN(152, 1, IO_TYPE_1V8), -+}; -+ -+static const struct spacemit_pinctrl_data k3_pinctrl_data = { -+ .pins = k3_pin_desc, -+ .data = k3_pin_data, -+ .npins = ARRAY_SIZE(k3_pin_desc), -+ .pin_to_offset = spacemit_k3_pin_to_offset, - }; - - static const struct of_device_id k1_pinctrl_ids[] = { - { .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data }, -+ { .compatible = "spacemit,k3-pinctrl", .data = &k3_pinctrl_data }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, k1_pinctrl_ids); -@@ -1061,5 +1407,5 @@ static struct platform_driver k1_pinctrl_driver = { - builtin_platform_driver(k1_pinctrl_driver); - - MODULE_AUTHOR("Yixun Lan "); --MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1 SoC"); -+MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1/K3 SoC"); - MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch b/SPECS/linux-lts/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch new file mode 100644 index 0000000000..377503eb76 --- /dev/null +++ b/SPECS/linux-lts/0095-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch @@ -0,0 +1,263 @@ +From 0a07233b0f550ed136cd45130d55ac5e079fc795 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 14:42:39 +0800 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: support I/O power domain + configuration + +Dual-voltage GPIO banks default to 3.3V operation. Even when a bank is +externally supplied with 1.8V, the internal logic remains in the 3.3V +domain, leading to functional failures. + +Add support for programming the IO domain power control registers to +allow explicit configuration for 1.8V operation. + +These registers are secure due to hardware safety constraints. +Specifically, configuring the domain for 1.8V while externally supplying +3.3V causes back-powering and potential pin damage. Consequently, access +requires unlocking the AIB Secure Access Register (ASAR) in the APBC +block before any read or write operation. + +Signed-off-by: Troy Mitchell +Signed-off-by: Linus Walleij +(cherry picked from commit 450e2487d5a28260f70ad7fbf3060e7f8304203d) +Signed-off-by: Han Gao +--- + drivers/pinctrl/spacemit/pinctrl-k1.c | 129 +++++++++++++++++++++++++- + 1 file changed, 126 insertions(+), 3 deletions(-) + +diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c +index 07267c5f0f44..71390402aaa6 100644 +--- a/drivers/pinctrl/spacemit/pinctrl-k1.c ++++ b/drivers/pinctrl/spacemit/pinctrl-k1.c +@@ -7,8 +7,10 @@ + #include + #include + #include ++#include + #include + #include ++#include + #include + #include + +@@ -47,6 +49,27 @@ + #define PAD_PULLUP BIT(14) + #define PAD_PULL_EN BIT(15) + ++#define IO_PWR_DOMAIN_OFFSET 0x800 ++ ++#define IO_PWR_DOMAIN_GPIO2_Kx 0x0c ++#define IO_PWR_DOMAIN_MMC_Kx 0x1c ++ ++#define IO_PWR_DOMAIN_GPIO3_K1 0x10 ++#define IO_PWR_DOMAIN_QSPI_K1 0x20 ++ ++#define IO_PWR_DOMAIN_GPIO1_K3 0x04 ++#define IO_PWR_DOMAIN_GPIO5_K3 0x10 ++#define IO_PWR_DOMAIN_GPIO4_K3 0x20 ++#define IO_PWR_DOMAIN_QSPI_K3 0x2c ++ ++#define IO_PWR_DOMAIN_V18EN BIT(2) ++ ++#define APBC_ASFAR 0x50 ++#define APBC_ASSAR 0x54 ++ ++#define APBC_ASFAR_AKEY 0xbaba ++#define APBC_ASSAR_AKEY 0xeb10 ++ + struct spacemit_pin_drv_strength { + u8 val; + u32 mA; +@@ -78,6 +101,8 @@ struct spacemit_pinctrl { + raw_spinlock_t lock; + + void __iomem *regs; ++ ++ struct regmap *regmap_apbc; + }; + + struct spacemit_pinctrl_data { +@@ -85,6 +110,7 @@ struct spacemit_pinctrl_data { + const struct spacemit_pin *data; + u16 npins; + unsigned int (*pin_to_offset)(unsigned int pin); ++ unsigned int (*pin_to_io_pd_offset)(unsigned int pin); + const struct spacemit_pinctrl_dconf *dconf; + }; + +@@ -146,6 +172,56 @@ static unsigned int spacemit_k3_pin_to_offset(unsigned int pin) + return offset << 2; + } + ++static unsigned int spacemit_k1_pin_to_io_pd_offset(unsigned int pin) ++{ ++ unsigned int offset = 0; ++ ++ switch (pin) { ++ case 47 ... 52: ++ offset = IO_PWR_DOMAIN_GPIO3_K1; ++ break; ++ case 75 ... 80: ++ offset = IO_PWR_DOMAIN_GPIO2_Kx; ++ break; ++ case 98 ... 103: ++ offset = IO_PWR_DOMAIN_QSPI_K1; ++ break; ++ case 104 ... 109: ++ offset = IO_PWR_DOMAIN_MMC_Kx; ++ break; ++ } ++ ++ return offset; ++} ++ ++static unsigned int spacemit_k3_pin_to_io_pd_offset(unsigned int pin) ++{ ++ unsigned int offset = 0; ++ ++ switch (pin) { ++ case 0 ... 20: ++ offset = IO_PWR_DOMAIN_GPIO1_K3; ++ break; ++ case 21 ... 41: ++ offset = IO_PWR_DOMAIN_GPIO2_Kx; ++ break; ++ case 76 ... 98: ++ offset = IO_PWR_DOMAIN_GPIO4_K3; ++ break; ++ case 99 ... 127: ++ offset = IO_PWR_DOMAIN_GPIO5_K3; ++ break; ++ case 132 ... 137: ++ offset = IO_PWR_DOMAIN_MMC_Kx; ++ break; ++ case 138 ... 144: ++ offset = IO_PWR_DOMAIN_QSPI_K3; ++ break; ++ } ++ ++ return offset; ++} ++ + static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, + unsigned int pin) + { +@@ -365,6 +441,42 @@ static int spacemit_pctrl_check_power(struct pinctrl_dev *pctldev, + return 0; + } + ++static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl, ++ const struct spacemit_pin *spin, ++ const enum spacemit_pin_io_type type) ++{ ++ u32 offset, val = 0; ++ ++ if (!pctrl->regmap_apbc) ++ return; ++ ++ offset = pctrl->data->pin_to_io_pd_offset(spin->pin); ++ ++ /* Other bits are reserved so don't need to save them */ ++ if (type == IO_TYPE_1V8) ++ val = IO_PWR_DOMAIN_V18EN; ++ ++ /* ++ * IO power domain registers are protected and cannot be accessed ++ * directly. Before performing any read or write to the IO power ++ * domain registers, an explicit unlock sequence must be issued ++ * via the AIB Secure Access Register (ASAR). ++ * ++ * The unlock sequence allows exactly one subsequent access to the ++ * IO power domain registers. After that access completes, the ASAR ++ * keys are automatically cleared, and the registers become locked ++ * again. ++ * ++ * This mechanism ensures that IO power domain configuration is ++ * performed intentionally, as incorrect voltage settings may ++ * result in functional failures or hardware damage. ++ */ ++ regmap_write(pctrl->regmap_apbc, APBC_ASFAR, APBC_ASFAR_AKEY); ++ regmap_write(pctrl->regmap_apbc, APBC_ASSAR, APBC_ASSAR_AKEY); ++ ++ writel_relaxed(val, pctrl->regs + IO_PWR_DOMAIN_OFFSET + offset); ++} ++ + static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, +@@ -572,7 +684,8 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, + + #define ENABLE_DRV_STRENGTH BIT(1) + #define ENABLE_SLEW_RATE BIT(2) +-static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, ++static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, ++ const struct spacemit_pin *spin, + const struct spacemit_pinctrl_dconf *dconf, + unsigned long *configs, + unsigned int num_configs, +@@ -646,6 +759,7 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, + default: + return -EINVAL; + } ++ spacemit_set_io_pwr_domain(pctrl, spin, type); + } + + val = spacemit_get_driver_strength(type, dconf, drv_strength); +@@ -701,7 +815,7 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + u32 value; + +- if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, ++ if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, + configs, num_configs, &value)) + return -EINVAL; + +@@ -724,7 +838,7 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, + return -EINVAL; + + spin = spacemit_get_pin(pctrl, group->grp.pins[0]); +- if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, ++ if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, + configs, num_configs, &value)) + return -EINVAL; + +@@ -795,6 +909,7 @@ static const struct pinconf_ops spacemit_pinconf_ops = { + + static int spacemit_pinctrl_probe(struct platform_device *pdev) + { ++ struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct spacemit_pinctrl *pctrl; + struct clk *func_clk, *bus_clk; +@@ -816,6 +931,12 @@ static int spacemit_pinctrl_probe(struct platform_device *pdev) + if (IS_ERR(pctrl->regs)) + return PTR_ERR(pctrl->regs); + ++ pctrl->regmap_apbc = syscon_regmap_lookup_by_phandle(np, "spacemit,apbc"); ++ if (IS_ERR(pctrl->regmap_apbc)) { ++ dev_warn(dev, "no syscon found, disable power voltage switch functionality\n"); ++ pctrl->regmap_apbc = NULL; ++ } ++ + func_clk = devm_clk_get_enabled(dev, "func"); + if (IS_ERR(func_clk)) + return dev_err_probe(dev, PTR_ERR(func_clk), "failed to get func clock\n"); +@@ -1118,6 +1239,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { + .data = k1_pin_data, + .npins = ARRAY_SIZE(k1_pin_desc), + .pin_to_offset = spacemit_k1_pin_to_offset, ++ .pin_to_io_pd_offset = spacemit_k1_pin_to_io_pd_offset, + .dconf = &k1_drive_conf, + }; + +@@ -1455,6 +1577,7 @@ static const struct spacemit_pinctrl_data k3_pinctrl_data = { + .data = k3_pin_data, + .npins = ARRAY_SIZE(k3_pin_desc), + .pin_to_offset = spacemit_k3_pin_to_offset, ++ .pin_to_io_pd_offset = spacemit_k3_pin_to_io_pd_offset, + .dconf = &k3_drive_conf, + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0096-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch b/SPECS/linux-lts/0096-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch deleted file mode 100644 index 02226d7349..0000000000 --- a/SPECS/linux-lts/0096-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch +++ /dev/null @@ -1,325 +0,0 @@ -From 407a2b9253b9c3e753302f3a24021c64b468be47 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 2 Jan 2026 15:00:25 +0800 -Subject: [PATCH 096/467] UPSTREAM: pinctrl: spacemit: k3: adjust drive - strength and schmitter trigger - -K3 SoC expand drive strength to 4 bits which support even larger -settings table comparing to old SoC generation. Also schmitter trigger -setting is changed to 1 bit. - -Signed-off-by: Yixun Lan -Signed-off-by: Linus Walleij -(cherry picked from commit 3f20bdf7151834547a85231c28538f49601481ee) -Signed-off-by: Han Gao ---- - drivers/pinctrl/spacemit/pinctrl-k1.c | 163 ++++++++++++++++++-------- - 1 file changed, 116 insertions(+), 47 deletions(-) - -diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c -index 441817f539e3..07267c5f0f44 100644 ---- a/drivers/pinctrl/spacemit/pinctrl-k1.c -+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c -@@ -24,11 +24,12 @@ - #include "pinctrl-k1.h" - - /* -- * +---------+----------+-----------+--------+--------+----------+--------+ -- * | pull | drive | schmitter | slew | edge | strong | mux | -- * | up/down | strength | trigger | rate | detect | pull | mode | -- * +---------+----------+-----------+--------+--------+----------+--------+ -- * 3 bits 3 bits 2 bits 1 bit 3 bits 1 bit 3 bits -+ * | pull | drive | schmitter | slew | edge | strong | mux | -+ * SoC | up/down | strength | trigger | rate | detect | pull | mode | -+ *-----+---------+----------+-----------+-------+--------+--------+--------+ -+ * K1 | 3 bits | 3 bits | 2 bits | 1 bit | 3 bits | 1 bit | 3 bits | -+ *-----+---------+----------+-----------+-------+--------+--------+--------+ -+ * K3 | 3 bits | 4 bits | 1 bits | 1 bit | 3 bits | 1 bit | 3 bits | - */ - - #define PAD_MUX GENMASK(2, 0) -@@ -38,12 +39,29 @@ - #define PAD_EDGE_CLEAR BIT(6) - #define PAD_SLEW_RATE GENMASK(12, 11) - #define PAD_SLEW_RATE_EN BIT(7) --#define PAD_SCHMITT GENMASK(9, 8) --#define PAD_DRIVE GENMASK(12, 10) -+#define PAD_SCHMITT_K1 GENMASK(9, 8) -+#define PAD_DRIVE_K1 GENMASK(12, 10) -+#define PAD_SCHMITT_K3 BIT(8) -+#define PAD_DRIVE_K3 GENMASK(12, 9) - #define PAD_PULLDOWN BIT(13) - #define PAD_PULLUP BIT(14) - #define PAD_PULL_EN BIT(15) - -+struct spacemit_pin_drv_strength { -+ u8 val; -+ u32 mA; -+}; -+ -+struct spacemit_pinctrl_dconf { -+ u64 schmitt_mask; -+ u64 drive_mask; -+ -+ struct spacemit_pin_drv_strength *ds_1v8_tbl; -+ size_t ds_1v8_tbl_num; -+ struct spacemit_pin_drv_strength *ds_3v3_tbl; -+ size_t ds_3v3_tbl_num; -+}; -+ - struct spacemit_pin { - u16 pin; - u16 flags; -@@ -67,6 +85,7 @@ struct spacemit_pinctrl_data { - const struct spacemit_pin *data; - u16 npins; - unsigned int (*pin_to_offset)(unsigned int pin); -+ const struct spacemit_pinctrl_dconf *dconf; - }; - - struct spacemit_pin_mux_config { -@@ -74,11 +93,6 @@ struct spacemit_pin_mux_config { - u32 config; - }; - --struct spacemit_pin_drv_strength { -- u8 val; -- u32 mA; --}; -- - /* map pin id to pinctrl register offset, refer MFPR definition */ - static unsigned int spacemit_k1_pin_to_offset(unsigned int pin) - { -@@ -193,23 +207,70 @@ static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev, - seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value); - } - --/* use IO high level output current as the table */ --static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = { -- { 0, 11 }, -- { 2, 21 }, -- { 4, 32 }, -- { 6, 42 }, -+static const struct spacemit_pinctrl_dconf k1_drive_conf = { -+ .drive_mask = PAD_DRIVE_K1, -+ .schmitt_mask = PAD_SCHMITT_K1, -+ .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) { -+ { 0, 11 }, -+ { 2, 21 }, -+ { 4, 32 }, -+ { 6, 42 }, -+ }, -+ .ds_1v8_tbl_num = 4, -+ .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) { -+ { 0, 7 }, -+ { 2, 10 }, -+ { 4, 13 }, -+ { 6, 16 }, -+ { 1, 19 }, -+ { 3, 23 }, -+ { 5, 26 }, -+ { 7, 29 }, -+ }, -+ .ds_3v3_tbl_num = 8, - }; - --static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = { -- { 0, 7 }, -- { 2, 10 }, -- { 4, 13 }, -- { 6, 16 }, -- { 1, 19 }, -- { 3, 23 }, -- { 5, 26 }, -- { 7, 29 }, -+static const struct spacemit_pinctrl_dconf k3_drive_conf = { -+ .drive_mask = PAD_DRIVE_K3, -+ .schmitt_mask = PAD_SCHMITT_K3, -+ .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) { -+ { 0, 2 }, -+ { 1, 4 }, -+ { 2, 6 }, -+ { 3, 7 }, -+ { 4, 9 }, -+ { 5, 11 }, -+ { 6, 13 }, -+ { 7, 14 }, -+ { 8, 21 }, -+ { 9, 23 }, -+ { 10, 25 }, -+ { 11, 26 }, -+ { 12, 28 }, -+ { 13, 30 }, -+ { 14, 31 }, -+ { 15, 33 }, -+ }, -+ .ds_1v8_tbl_num = 16, -+ .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) { -+ { 0, 3 }, -+ { 1, 5 }, -+ { 2, 7 }, -+ { 3, 9 }, -+ { 4, 11 }, -+ { 5, 13 }, -+ { 6, 15 }, -+ { 7, 17 }, -+ { 8, 25 }, -+ { 9, 27 }, -+ { 10, 29 }, -+ { 11, 31 }, -+ { 12, 33 }, -+ { 13, 35 }, -+ { 14, 37 }, -+ { 15, 38 }, -+ }, -+ .ds_3v3_tbl_num = 16, - }; - - static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl, -@@ -237,16 +298,17 @@ static inline u32 spacemit_get_ds_mA(struct spacemit_pin_drv_strength *tbl, - } - - static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type, -+ const struct spacemit_pinctrl_dconf *dconf, - u32 mA) - { - switch (type) { - case IO_TYPE_1V8: -- return spacemit_get_ds_value(spacemit_ds_1v8_tbl, -- ARRAY_SIZE(spacemit_ds_1v8_tbl), -+ return spacemit_get_ds_value(dconf->ds_1v8_tbl, -+ dconf->ds_1v8_tbl_num, - mA); - case IO_TYPE_3V3: -- return spacemit_get_ds_value(spacemit_ds_3v3_tbl, -- ARRAY_SIZE(spacemit_ds_3v3_tbl), -+ return spacemit_get_ds_value(dconf->ds_3v3_tbl, -+ dconf->ds_3v3_tbl_num, - mA); - default: - return 0; -@@ -254,16 +316,17 @@ static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type, - } - - static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type, -+ const struct spacemit_pinctrl_dconf *dconf, - u32 value) - { - switch (type) { - case IO_TYPE_1V8: -- return spacemit_get_ds_mA(spacemit_ds_1v8_tbl, -- ARRAY_SIZE(spacemit_ds_1v8_tbl), -- value & 0x6); -+ return spacemit_get_ds_mA(dconf->ds_1v8_tbl, -+ dconf->ds_1v8_tbl_num, -+ value); - case IO_TYPE_3V3: -- return spacemit_get_ds_mA(spacemit_ds_3v3_tbl, -- ARRAY_SIZE(spacemit_ds_3v3_tbl), -+ return spacemit_get_ds_mA(dconf->ds_3v3_tbl, -+ dconf->ds_3v3_tbl_num, - value); - default: - return 0; -@@ -510,6 +573,7 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, - #define ENABLE_DRV_STRENGTH BIT(1) - #define ENABLE_SLEW_RATE BIT(2) - static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, -+ const struct spacemit_pinctrl_dconf *dconf, - unsigned long *configs, - unsigned int num_configs, - u32 *value) -@@ -547,8 +611,8 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, - drv_strength = arg; - break; - case PIN_CONFIG_INPUT_SCHMITT: -- v &= ~PAD_SCHMITT; -- v |= FIELD_PREP(PAD_SCHMITT, arg); -+ v &= ~dconf->schmitt_mask; -+ v |= (arg << __ffs(dconf->schmitt_mask)) & dconf->schmitt_mask; - break; - case PIN_CONFIG_POWER_SOURCE: - voltage = arg; -@@ -584,10 +648,10 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, - } - } - -- val = spacemit_get_driver_strength(type, drv_strength); -+ val = spacemit_get_driver_strength(type, dconf, drv_strength); - -- v &= ~PAD_DRIVE; -- v |= FIELD_PREP(PAD_DRIVE, val); -+ v &= ~dconf->drive_mask; -+ v |= (val << __ffs(dconf->drive_mask)) & dconf->drive_mask; - } - - if (flag & ENABLE_SLEW_RATE) { -@@ -637,7 +701,8 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, - const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); - u32 value; - -- if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) -+ if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, -+ configs, num_configs, &value)) - return -EINVAL; - - return spacemit_pin_set_config(pctrl, pin, value); -@@ -659,7 +724,8 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, - return -EINVAL; - - spin = spacemit_get_pin(pctrl, group->grp.pins[0]); -- if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) -+ if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, -+ configs, num_configs, &value)) - return -EINVAL; - - for (i = 0; i < group->grp.npins; i++) -@@ -693,6 +759,7 @@ static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *seq, unsigned int pin) - { - struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); -+ const struct spacemit_pinctrl_dconf *dconf = pctrl->data->dconf; - const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); - enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin); - void __iomem *reg = spacemit_pin_to_reg(pctrl, pin); -@@ -703,17 +770,17 @@ static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev, - - seq_printf(seq, ", io type (%s)", io_type_desc[type]); - -- tmp = FIELD_GET(PAD_DRIVE, value); -+ tmp = (value & dconf->drive_mask) >> __ffs(dconf->drive_mask); - if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) { -- mA = spacemit_get_drive_strength_mA(type, tmp); -+ mA = spacemit_get_drive_strength_mA(type, dconf, tmp); - seq_printf(seq, ", drive strength (%d mA)", mA); - } - - /* drive strength depend on power source, so show all values */ - if (type == IO_TYPE_EXTERNAL) - seq_printf(seq, ", drive strength (%d or %d mA)", -- spacemit_get_drive_strength_mA(IO_TYPE_1V8, tmp), -- spacemit_get_drive_strength_mA(IO_TYPE_3V3, tmp)); -+ spacemit_get_drive_strength_mA(IO_TYPE_1V8, dconf, tmp), -+ spacemit_get_drive_strength_mA(IO_TYPE_3V3, dconf, tmp)); - - seq_printf(seq, ", register (0x%04x)", value); - } -@@ -1051,6 +1118,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { - .data = k1_pin_data, - .npins = ARRAY_SIZE(k1_pin_desc), - .pin_to_offset = spacemit_k1_pin_to_offset, -+ .dconf = &k1_drive_conf, - }; - - static const struct pinctrl_pin_desc k3_pin_desc[] = { -@@ -1387,6 +1455,7 @@ static const struct spacemit_pinctrl_data k3_pinctrl_data = { - .data = k3_pin_data, - .npins = ARRAY_SIZE(k3_pin_desc), - .pin_to_offset = spacemit_k3_pin_to_offset, -+ .dconf = &k3_drive_conf, - }; - - static const struct of_device_id k1_pinctrl_ids[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch b/SPECS/linux-lts/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch new file mode 100644 index 0000000000..8f6837bba8 --- /dev/null +++ b/SPECS/linux-lts/0096-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch @@ -0,0 +1,48 @@ +From 404911e71521a30847ea8198f0e48c7d6c92dac5 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 14:42:40 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: pinctrl: update register + and IO power + +Change the size of the reg register to 0x1000 to match the hardware. +This register range covers the IO power domain's register addresses. + +The IO power domain registers are protected. In order to access the +protected IO power domain registers, a valid unlock sequence must be +performed by writing the required keys to the AIB Secure Access Register +(ASAR). + +The ASAR register resides within the APBC register address space. +A corresponding syscon property `spacemit,apbc` is added to allow +the pinctrl driver to access this register. + +Signed-off-by: Troy Mitchell +Acked-by: Linus Walleij +Link: https://lore.kernel.org/r/20260108-kx-pinctrl-aib-io-pwr-domain-v2-3-6bcb46146e53@linux.spacemit.com +Signed-off-by: Yixun Lan +(cherry picked from commit 4083d8d6c0aa445fc440d70a5258351c47547ee2) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 137fc26ddc29..e22a5f030fa2 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -628,10 +628,11 @@ i2c8: i2c@d401d800 { + + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k1-pinctrl"; +- reg = <0x0 0xd401e000 0x0 0x400>; ++ reg = <0x0 0xd401e000 0x0 0x1000>; + clocks = <&syscon_apbc CLK_AIB>, + <&syscon_apbc CLK_AIB_BUS>; + clock-names = "func", "bus"; ++ spacemit,apbc = <&syscon_apbc>; + }; + + pwm8: pwm@d4020000 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0097-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch b/SPECS/linux-lts/0097-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch deleted file mode 100644 index 6328b7b073..0000000000 --- a/SPECS/linux-lts/0097-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 9c53bc78545cc3c695e01922464a71c887179572 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 8 Jan 2026 14:42:38 +0800 -Subject: [PATCH 097/467] UPSTREAM: dt-bindings: pinctrl: spacemit: add syscon - property - -In order to access the protected IO power domain registers, a valid -unlock sequence must be performed by writing the required keys to the -AIB Secure Access Register (ASAR). - -The ASAR register resides within the APBC register address space. -A corresponding syscon property is added to allow the pinctrl driver -to access this register. - -Signed-off-by: Troy Mitchell -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Linus Walleij -(cherry picked from commit e817f0223d78818cd6c0e3480355c9a9cfbc0096) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -index 9a76cffcbaee..141dcedb81fb 100644 ---- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -+++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml -@@ -32,6 +32,10 @@ properties: - resets: - maxItems: 1 - -+ spacemit,apbc: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: Phandle to syscon that access the protected register -+ - patternProperties: - '-cfg$': - type: object -@@ -138,6 +142,7 @@ examples: - clocks = <&syscon_apbc 42>, - <&syscon_apbc 94>; - clock-names = "func", "bus"; -+ spacemit,apbc = <&syscon_apbc>; - - uart0_2_cfg: uart0-2-cfg { - uart0-2-pins { --- -2.53.0 - diff --git a/SPECS/linux-lts/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch b/SPECS/linux-lts/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch new file mode 100644 index 0000000000..9c1db3eb89 --- /dev/null +++ b/SPECS/linux-lts/0097-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch @@ -0,0 +1,78 @@ +From 33a192939d2dd110bc17a0f1c65a5c654c617d16 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 25 Dec 2025 14:24:20 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: update ratified version of + h, svinval, svnapot, svpbmt + +The descriptions for h, svinval, svnapot, and svpbmt extensions currently +reference the "20191213 version of the privileged ISA specification". +While an Unprivileged ISA document exists with that date, there is no +corresponding ratified Privileged ISA specification. + +These extensions were ratified in the RISC-V Instruction Set Manual, +Volume II: Privileged Architecture, Version 20211203. Update the +descriptions to reference the correct specification version. + +RISC-V International hosts a website [1] for ratified specifications. +Following the "Ratified ISA Specifications", historical versions of +Volume II Privileged ISA can be found. + +Link: https://riscv.org/specifications/ratified/ [1] +Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") +Acked-by: Conor Dooley +Signed-off-by: Guodong Xu +Signed-off-by: Conor Dooley +(cherry picked from commit fff010c776f715904ba0823bb347eac00dccffa2) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/extensions.yaml | 19 +++++++++++-------- + 1 file changed, 11 insertions(+), 8 deletions(-) + +diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml +index 543ac94718e8..aa38809ecf06 100644 +--- a/Documentation/devicetree/bindings/riscv/extensions.yaml ++++ b/Documentation/devicetree/bindings/riscv/extensions.yaml +@@ -117,8 +117,9 @@ properties: + + - const: h + description: +- The standard H extension for hypervisors as ratified in the 20191213 +- version of the privileged ISA specification. ++ The standard H extension for hypervisors as ratified in the RISC-V ++ Instruction Set Manual, Volume II Privileged Architecture, ++ Document Version 20211203. + + # multi-letter extensions, sorted alphanumerically + - const: smaia +@@ -202,20 +203,22 @@ properties: + - const: svinval + description: + The standard Svinval supervisor-level extension for fine-grained +- address-translation cache invalidation as ratified in the 20191213 +- version of the privileged ISA specification. ++ address-translation cache invalidation as ratified in the RISC-V ++ Instruction Set Manual, Volume II Privileged Architecture, ++ Document Version 20211203. + + - const: svnapot + description: + The standard Svnapot supervisor-level extensions for napot +- translation contiguity as ratified in the 20191213 version of the +- privileged ISA specification. ++ translation contiguity as ratified in the RISC-V Instruction Set ++ Manual, Volume II Privileged Architecture, Document Version ++ 20211203. + + - const: svpbmt + description: + The standard Svpbmt supervisor-level extensions for page-based +- memory types as ratified in the 20191213 version of the privileged +- ISA specification. ++ memory types as ratified in the RISC-V Instruction Set Manual, ++ Volume II Privileged Architecture, Document Version 20211203. + + - const: svvptc + description: +-- +2.53.0 + diff --git a/SPECS/linux-lts/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch b/SPECS/linux-lts/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch new file mode 100644 index 0000000000..03b356c1c3 --- /dev/null +++ b/SPECS/linux-lts/0098-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch @@ -0,0 +1,91 @@ +From 8b082ec91bd4cfaf11f3a1b69d1b66ea599ba3f1 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Sat, 10 Jan 2026 13:18:18 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add B ISA extension + description + +Add description of the single-letter B extension for Bit Manipulation. +B is mandatory for RVA23U64. + +The B extension is ratified in the 20240411 version of the unprivileged +ISA specification. According to the ratified spec, the B standard +extension comprises instructions provided by the Zba, Zbb, and Zbs +extensions. + +Add two-way dependency check to enforce that B implies Zba/Zbb/Zbs; and +when Zba/Zbb/Zbs (all of them) are specified, then B must be added too. + +The reason why B/Zba/Zbb/Zbs must coexist at the same time is that +unlike other single-letter extensions, B was ratified (Apr/2024) much +later than its component extensions Zba/Zbb/Zbs (Jun/2021). + +When "b" is specified, zba/zbb/zbs must be present to ensure +backward compatibility with existing software and kernels that only +look for the explicit component strings. + +When all three components zba/zbb/zbs are specified, "b" should also be +present. Making "b" mandatory when all three components are present. + +Existing devicetrees with zba/zbb/zbs but without "b" will generate +warnings that can be fixed in follow-up patches. + +Signed-off-by: Guodong Xu +Signed-off-by: Conor Dooley +(cherry picked from commit 0cdb7fc1879b1b858463125630f4dd5af6b111ad) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/extensions.yaml | 31 +++++++++++++++++++ + 1 file changed, 31 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml +index aa38809ecf06..36afd1cc42cf 100644 +--- a/Documentation/devicetree/bindings/riscv/extensions.yaml ++++ b/Documentation/devicetree/bindings/riscv/extensions.yaml +@@ -109,6 +109,13 @@ properties: + The standard C extension for compressed instructions, as ratified in + the 20191213 version of the unprivileged ISA specification. + ++ - const: b ++ description: ++ The standard B extension for bit manipulation instructions, as ++ ratified in the 20240411 version of the unprivileged ISA ++ specification. The B standard extension comprises instructions ++ provided by the Zba, Zbb, and Zbs extensions. ++ + - const: v + description: + The standard V extension for vector operations, as ratified +@@ -727,6 +734,30 @@ properties: + then: + contains: + const: f ++ # B comprises Zba, Zbb, and Zbs ++ - if: ++ contains: ++ const: b ++ then: ++ allOf: ++ - contains: ++ const: zba ++ - contains: ++ const: zbb ++ - contains: ++ const: zbs ++ # Zba, Zbb, Zbs together require B ++ - if: ++ allOf: ++ - contains: ++ const: zba ++ - contains: ++ const: zbb ++ - contains: ++ const: zbs ++ then: ++ contains: ++ const: b + # Zcb depends on Zca + - if: + contains: +-- +2.53.0 + diff --git a/SPECS/linux-lts/0098-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch b/SPECS/linux-lts/0098-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch deleted file mode 100644 index 220390317f..0000000000 --- a/SPECS/linux-lts/0098-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch +++ /dev/null @@ -1,263 +0,0 @@ -From 4d7b192ae28c8fd62c4887c36d1d2daf3d5537ab Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 8 Jan 2026 14:42:39 +0800 -Subject: [PATCH 098/467] UPSTREAM: pinctrl: spacemit: support I/O power domain - configuration - -Dual-voltage GPIO banks default to 3.3V operation. Even when a bank is -externally supplied with 1.8V, the internal logic remains in the 3.3V -domain, leading to functional failures. - -Add support for programming the IO domain power control registers to -allow explicit configuration for 1.8V operation. - -These registers are secure due to hardware safety constraints. -Specifically, configuring the domain for 1.8V while externally supplying -3.3V causes back-powering and potential pin damage. Consequently, access -requires unlocking the AIB Secure Access Register (ASAR) in the APBC -block before any read or write operation. - -Signed-off-by: Troy Mitchell -Signed-off-by: Linus Walleij -(cherry picked from commit 450e2487d5a28260f70ad7fbf3060e7f8304203d) -Signed-off-by: Han Gao ---- - drivers/pinctrl/spacemit/pinctrl-k1.c | 129 +++++++++++++++++++++++++- - 1 file changed, 126 insertions(+), 3 deletions(-) - -diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c -index 07267c5f0f44..71390402aaa6 100644 ---- a/drivers/pinctrl/spacemit/pinctrl-k1.c -+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c -@@ -7,8 +7,10 @@ - #include - #include - #include -+#include - #include - #include -+#include - #include - #include - -@@ -47,6 +49,27 @@ - #define PAD_PULLUP BIT(14) - #define PAD_PULL_EN BIT(15) - -+#define IO_PWR_DOMAIN_OFFSET 0x800 -+ -+#define IO_PWR_DOMAIN_GPIO2_Kx 0x0c -+#define IO_PWR_DOMAIN_MMC_Kx 0x1c -+ -+#define IO_PWR_DOMAIN_GPIO3_K1 0x10 -+#define IO_PWR_DOMAIN_QSPI_K1 0x20 -+ -+#define IO_PWR_DOMAIN_GPIO1_K3 0x04 -+#define IO_PWR_DOMAIN_GPIO5_K3 0x10 -+#define IO_PWR_DOMAIN_GPIO4_K3 0x20 -+#define IO_PWR_DOMAIN_QSPI_K3 0x2c -+ -+#define IO_PWR_DOMAIN_V18EN BIT(2) -+ -+#define APBC_ASFAR 0x50 -+#define APBC_ASSAR 0x54 -+ -+#define APBC_ASFAR_AKEY 0xbaba -+#define APBC_ASSAR_AKEY 0xeb10 -+ - struct spacemit_pin_drv_strength { - u8 val; - u32 mA; -@@ -78,6 +101,8 @@ struct spacemit_pinctrl { - raw_spinlock_t lock; - - void __iomem *regs; -+ -+ struct regmap *regmap_apbc; - }; - - struct spacemit_pinctrl_data { -@@ -85,6 +110,7 @@ struct spacemit_pinctrl_data { - const struct spacemit_pin *data; - u16 npins; - unsigned int (*pin_to_offset)(unsigned int pin); -+ unsigned int (*pin_to_io_pd_offset)(unsigned int pin); - const struct spacemit_pinctrl_dconf *dconf; - }; - -@@ -146,6 +172,56 @@ static unsigned int spacemit_k3_pin_to_offset(unsigned int pin) - return offset << 2; - } - -+static unsigned int spacemit_k1_pin_to_io_pd_offset(unsigned int pin) -+{ -+ unsigned int offset = 0; -+ -+ switch (pin) { -+ case 47 ... 52: -+ offset = IO_PWR_DOMAIN_GPIO3_K1; -+ break; -+ case 75 ... 80: -+ offset = IO_PWR_DOMAIN_GPIO2_Kx; -+ break; -+ case 98 ... 103: -+ offset = IO_PWR_DOMAIN_QSPI_K1; -+ break; -+ case 104 ... 109: -+ offset = IO_PWR_DOMAIN_MMC_Kx; -+ break; -+ } -+ -+ return offset; -+} -+ -+static unsigned int spacemit_k3_pin_to_io_pd_offset(unsigned int pin) -+{ -+ unsigned int offset = 0; -+ -+ switch (pin) { -+ case 0 ... 20: -+ offset = IO_PWR_DOMAIN_GPIO1_K3; -+ break; -+ case 21 ... 41: -+ offset = IO_PWR_DOMAIN_GPIO2_Kx; -+ break; -+ case 76 ... 98: -+ offset = IO_PWR_DOMAIN_GPIO4_K3; -+ break; -+ case 99 ... 127: -+ offset = IO_PWR_DOMAIN_GPIO5_K3; -+ break; -+ case 132 ... 137: -+ offset = IO_PWR_DOMAIN_MMC_Kx; -+ break; -+ case 138 ... 144: -+ offset = IO_PWR_DOMAIN_QSPI_K3; -+ break; -+ } -+ -+ return offset; -+} -+ - static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, - unsigned int pin) - { -@@ -365,6 +441,42 @@ static int spacemit_pctrl_check_power(struct pinctrl_dev *pctldev, - return 0; - } - -+static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl, -+ const struct spacemit_pin *spin, -+ const enum spacemit_pin_io_type type) -+{ -+ u32 offset, val = 0; -+ -+ if (!pctrl->regmap_apbc) -+ return; -+ -+ offset = pctrl->data->pin_to_io_pd_offset(spin->pin); -+ -+ /* Other bits are reserved so don't need to save them */ -+ if (type == IO_TYPE_1V8) -+ val = IO_PWR_DOMAIN_V18EN; -+ -+ /* -+ * IO power domain registers are protected and cannot be accessed -+ * directly. Before performing any read or write to the IO power -+ * domain registers, an explicit unlock sequence must be issued -+ * via the AIB Secure Access Register (ASAR). -+ * -+ * The unlock sequence allows exactly one subsequent access to the -+ * IO power domain registers. After that access completes, the ASAR -+ * keys are automatically cleared, and the registers become locked -+ * again. -+ * -+ * This mechanism ensures that IO power domain configuration is -+ * performed intentionally, as incorrect voltage settings may -+ * result in functional failures or hardware damage. -+ */ -+ regmap_write(pctrl->regmap_apbc, APBC_ASFAR, APBC_ASFAR_AKEY); -+ regmap_write(pctrl->regmap_apbc, APBC_ASSAR, APBC_ASSAR_AKEY); -+ -+ writel_relaxed(val, pctrl->regs + IO_PWR_DOMAIN_OFFSET + offset); -+} -+ - static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **maps, -@@ -572,7 +684,8 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, - - #define ENABLE_DRV_STRENGTH BIT(1) - #define ENABLE_SLEW_RATE BIT(2) --static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, -+static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, -+ const struct spacemit_pin *spin, - const struct spacemit_pinctrl_dconf *dconf, - unsigned long *configs, - unsigned int num_configs, -@@ -646,6 +759,7 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, - default: - return -EINVAL; - } -+ spacemit_set_io_pwr_domain(pctrl, spin, type); - } - - val = spacemit_get_driver_strength(type, dconf, drv_strength); -@@ -701,7 +815,7 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, - const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); - u32 value; - -- if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, -+ if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, - configs, num_configs, &value)) - return -EINVAL; - -@@ -724,7 +838,7 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, - return -EINVAL; - - spin = spacemit_get_pin(pctrl, group->grp.pins[0]); -- if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf, -+ if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, - configs, num_configs, &value)) - return -EINVAL; - -@@ -795,6 +909,7 @@ static const struct pinconf_ops spacemit_pinconf_ops = { - - static int spacemit_pinctrl_probe(struct platform_device *pdev) - { -+ struct device_node *np = pdev->dev.of_node; - struct device *dev = &pdev->dev; - struct spacemit_pinctrl *pctrl; - struct clk *func_clk, *bus_clk; -@@ -816,6 +931,12 @@ static int spacemit_pinctrl_probe(struct platform_device *pdev) - if (IS_ERR(pctrl->regs)) - return PTR_ERR(pctrl->regs); - -+ pctrl->regmap_apbc = syscon_regmap_lookup_by_phandle(np, "spacemit,apbc"); -+ if (IS_ERR(pctrl->regmap_apbc)) { -+ dev_warn(dev, "no syscon found, disable power voltage switch functionality\n"); -+ pctrl->regmap_apbc = NULL; -+ } -+ - func_clk = devm_clk_get_enabled(dev, "func"); - if (IS_ERR(func_clk)) - return dev_err_probe(dev, PTR_ERR(func_clk), "failed to get func clock\n"); -@@ -1118,6 +1239,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = { - .data = k1_pin_data, - .npins = ARRAY_SIZE(k1_pin_desc), - .pin_to_offset = spacemit_k1_pin_to_offset, -+ .pin_to_io_pd_offset = spacemit_k1_pin_to_io_pd_offset, - .dconf = &k1_drive_conf, - }; - -@@ -1455,6 +1577,7 @@ static const struct spacemit_pinctrl_data k3_pinctrl_data = { - .data = k3_pin_data, - .npins = ARRAY_SIZE(k3_pin_desc), - .pin_to_offset = spacemit_k3_pin_to_offset, -+ .pin_to_io_pd_offset = spacemit_k3_pin_to_io_pd_offset, - .dconf = &k3_drive_conf, - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch b/SPECS/linux-lts/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch new file mode 100644 index 0000000000..f6b09dc50b --- /dev/null +++ b/SPECS/linux-lts/0099-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch @@ -0,0 +1,131 @@ +From 293192824603c354264f56113a64fc91d889d750 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Sat, 10 Jan 2026 13:18:19 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add descriptions for + Za64rs, Ziccamoa, Ziccif, and Zicclsm + +Add descriptions for four extensions: Za64rs, Ziccamoa, Ziccif, and +Zicclsm. These extensions are ratified in RISC-V Profiles Version 1.0 +(commit b1d806605f87 "Updated to ratified state."). + +They are introduced as new extension names for existing features and +regulate implementation details for RISC-V Profile compliance. According +to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, they are +mandatory for the following profiles: + + - za64rs: Mandatory in RVA22U64, RVA23U64 + - ziccamoa: Mandatory in RVA20U64, RVA22U64, RVA23U64 + - ziccif: Mandatory in RVA20U64, RVA22U64, RVA23U64 + - zicclsm: Mandatory in RVA20U64, RVA22U64, RVA23U64 + +Ziccrse specifies the main memory must support "RsrvEventual", which is +one (totally there are four) of the support level for Load-Reserved/ +Store-Conditional (LR/SC) atomic instructions. Thus it depends on Zalrsc. + +Ziccamoa specifies the main memory must support AMOArithmetic, among the +four levels of PMA support defined for AMOs in the A extension. Thus it +depends on Zaamo. + +Za64rs defines reservation sets are contiguous, naturally aligned, and a +maximum of 64 bytes. Za64rs is consumed by two extensions: Zalrsc and +Zawrs. Zawrs itself depends on Zalrsc too. + +Based on the relationship that "A" = Zaamo + Zalrsc, add the following +dependencies checks: + Za64rs -> Zalrsc or A + Ziccrse -> Zalrsc or A + Ziccamoa -> Zaamo or A + +Signed-off-by: Guodong Xu +Acked-by: Conor Dooley +Signed-off-by: Conor Dooley +(cherry picked from commit b321256a4f36227e0c1ae54e8c6c48524dcba83d) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/extensions.yaml | 49 +++++++++++++++++++ + 1 file changed, 49 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml +index 36afd1cc42cf..bebbd7797d49 100644 +--- a/Documentation/devicetree/bindings/riscv/extensions.yaml ++++ b/Documentation/devicetree/bindings/riscv/extensions.yaml +@@ -234,6 +234,12 @@ properties: + as ratified at commit 4a69197e5617 ("Update to ratified state") of + riscv-svvptc. + ++ - const: za64rs ++ description: ++ The standard Za64rs extension for reservation set size of at most ++ 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit ++ b1d806605f87 ("Updated to ratified state.") ++ + - const: zaamo + description: | + The standard Zaamo extension for atomic memory operations as +@@ -370,6 +376,27 @@ properties: + in commit 64074bc ("Update version numbers for Zfh/Zfinx") of + riscv-isa-manual. + ++ - const: ziccamoa ++ description: ++ The standard Ziccamoa extension for main memory (cacheability and ++ coherence) must support all atomics in A, as ratified in RISC-V ++ Profiles Version 1.0, with commit b1d806605f87 ("Updated to ++ ratified state.") ++ ++ - const: ziccif ++ description: ++ The standard Ziccif extension for main memory (cacheability and ++ coherence) instruction fetch atomicity, as ratified in RISC-V ++ Profiles Version 1.0, with commit b1d806605f87 ("Updated to ++ ratified state.") ++ ++ - const: zicclsm ++ description: ++ The standard Zicclsm extension for main memory (cacheability and ++ coherence) must support misaligned loads and stores, as ratified ++ in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated ++ to ratified state.") ++ + - const: ziccrse + description: + The standard Ziccrse extension which provides forward progress +@@ -758,6 +785,18 @@ properties: + then: + contains: + const: b ++ # Za64rs and Ziccrse depend on Zalrsc or A ++ - if: ++ contains: ++ anyOf: ++ - const: za64rs ++ - const: ziccrse ++ then: ++ oneOf: ++ - contains: ++ const: zalrsc ++ - contains: ++ const: a + # Zcb depends on Zca + - if: + contains: +@@ -799,6 +838,16 @@ properties: + then: + contains: + const: f ++ # Ziccamoa depends on Zaamo or A ++ - if: ++ contains: ++ const: ziccamoa ++ then: ++ oneOf: ++ - contains: ++ const: zaamo ++ - contains: ++ const: a + # Zvfbfmin depends on V or Zve32f + - if: + contains: +-- +2.53.0 + diff --git a/SPECS/linux-lts/0099-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch b/SPECS/linux-lts/0099-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch deleted file mode 100644 index 678fbcc0c7..0000000000 --- a/SPECS/linux-lts/0099-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 5379340efd812454feda9bf0ebc36dad03992fda Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 8 Jan 2026 14:42:40 +0800 -Subject: [PATCH 099/467] UPSTREAM: riscv: dts: spacemit: pinctrl: update - register and IO power - -Change the size of the reg register to 0x1000 to match the hardware. -This register range covers the IO power domain's register addresses. - -The IO power domain registers are protected. In order to access the -protected IO power domain registers, a valid unlock sequence must be -performed by writing the required keys to the AIB Secure Access Register -(ASAR). - -The ASAR register resides within the APBC register address space. -A corresponding syscon property `spacemit,apbc` is added to allow -the pinctrl driver to access this register. - -Signed-off-by: Troy Mitchell -Acked-by: Linus Walleij -Link: https://lore.kernel.org/r/20260108-kx-pinctrl-aib-io-pwr-domain-v2-3-6bcb46146e53@linux.spacemit.com -Signed-off-by: Yixun Lan -(cherry picked from commit 4083d8d6c0aa445fc440d70a5258351c47547ee2) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 137fc26ddc29..e22a5f030fa2 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -628,10 +628,11 @@ i2c8: i2c@d401d800 { - - pinctrl: pinctrl@d401e000 { - compatible = "spacemit,k1-pinctrl"; -- reg = <0x0 0xd401e000 0x0 0x400>; -+ reg = <0x0 0xd401e000 0x0 0x1000>; - clocks = <&syscon_apbc CLK_AIB>, - <&syscon_apbc CLK_AIB_BUS>; - clock-names = "func", "bus"; -+ spacemit,apbc = <&syscon_apbc>; - }; - - pwm8: pwm@d4020000 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch b/SPECS/linux-lts/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch new file mode 100644 index 0000000000..347e39618f --- /dev/null +++ b/SPECS/linux-lts/0100-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch @@ -0,0 +1,89 @@ +From 9f1f119c5d51420861951a5660e8714b87fcf2ce Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Sat, 10 Jan 2026 13:18:20 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add Ssccptr, Sscounterenw, + Sstvala, Sstvecd, Ssu64xl + +Add descriptions for five new extensions: Ssccptr, Sscounterenw, Sstvala, +Sstvecd, and Ssu64xl. These extensions are ratified in RISC-V Profiles +Version 1.0 (commit b1d806605f87 "Updated to ratified state."). + +They are introduced as new extension names for existing features and +regulate implementation details for RISC-V Profile compliance. According +to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, their +requirement status are: + + - Ssccptr: Mandatory in RVA20S64, RVA22S64, RVA23S64 + - Sscounterenw: Mandatory in RVA22S64, RVA23S64 + - Sstvala: Mandatory in RVA20S64, RVA22S64, RVA23S64 + - Sstvecd: Mandatory in RVA20S64, RVA22S64, RVA23S64 + - Ssu64xl: Optional in RVA20S64, RVA22S64; Mandatory in RVA23S64 + +Signed-off-by: Guodong Xu +Acked-by: Conor Dooley +Signed-off-by: Conor Dooley +(cherry picked from commit c712413333f8e19cc3de4e9cd1a3ed8a53169cc9) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/extensions.yaml | 32 +++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml +index bebbd7797d49..81cff2e5b06f 100644 +--- a/Documentation/devicetree/bindings/riscv/extensions.yaml ++++ b/Documentation/devicetree/bindings/riscv/extensions.yaml +@@ -161,12 +161,26 @@ properties: + behavioural changes to interrupts as frozen at commit ccbddab + ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + ++ - const: ssccptr ++ description: | ++ The standard Ssccptr extension for main memory (cacheability and ++ coherence) hardware page-table reads, as ratified in RISC-V ++ Profiles Version 1.0, with commit b1d806605f87 ("Updated to ++ ratified state.") ++ + - const: sscofpmf + description: | + The standard Sscofpmf supervisor-level extension for count overflow + and mode-based filtering as ratified at commit 01d1df0 ("Add ability + to manually trigger workflow. (#2)") of riscv-count-overflow. + ++ - const: sscounterenw ++ description: | ++ The standard Sscounterenw extension for support writable enables ++ in scounteren for any supported counter, as ratified in RISC-V ++ Profiles Version 1.0, with commit b1d806605f87 ("Updated to ++ ratified state.") ++ + - const: ssnpm + description: | + The standard Ssnpm extension for next-mode pointer masking as +@@ -179,6 +193,24 @@ properties: + ratified at commit 3f9ed34 ("Add ability to manually trigger + workflow. (#2)") of riscv-time-compare. + ++ - const: sstvala ++ description: | ++ The standard Sstvala extension for stval provides all needed values ++ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 ++ ("Updated to ratified state.") ++ ++ - const: sstvecd ++ description: | ++ The standard Sstvecd extension for stvec supports Direct mode as ++ ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 ++ ("Updated to ratified state.") ++ ++ - const: ssu64xl ++ description: | ++ The standard Ssu64xl extension for UXLEN=64 must be supported, as ++ ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 ++ ("Updated to ratified state.") ++ + - const: svade + description: | + The standard Svade supervisor-level extension for SW-managed PTE A/D +-- +2.53.0 + diff --git a/SPECS/linux-lts/0100-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch b/SPECS/linux-lts/0100-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch deleted file mode 100644 index 3f371e8651..0000000000 --- a/SPECS/linux-lts/0100-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch +++ /dev/null @@ -1,78 +0,0 @@ -From bd353c8584ce96ff556b222bfcbd29bbce5d0a16 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 25 Dec 2025 14:24:20 +0800 -Subject: [PATCH 100/467] UPSTREAM: dt-bindings: riscv: update ratified version - of h, svinval, svnapot, svpbmt - -The descriptions for h, svinval, svnapot, and svpbmt extensions currently -reference the "20191213 version of the privileged ISA specification". -While an Unprivileged ISA document exists with that date, there is no -corresponding ratified Privileged ISA specification. - -These extensions were ratified in the RISC-V Instruction Set Manual, -Volume II: Privileged Architecture, Version 20211203. Update the -descriptions to reference the correct specification version. - -RISC-V International hosts a website [1] for ratified specifications. -Following the "Ratified ISA Specifications", historical versions of -Volume II Privileged ISA can be found. - -Link: https://riscv.org/specifications/ratified/ [1] -Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") -Acked-by: Conor Dooley -Signed-off-by: Guodong Xu -Signed-off-by: Conor Dooley -(cherry picked from commit fff010c776f715904ba0823bb347eac00dccffa2) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/riscv/extensions.yaml | 19 +++++++++++-------- - 1 file changed, 11 insertions(+), 8 deletions(-) - -diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml -index 543ac94718e8..aa38809ecf06 100644 ---- a/Documentation/devicetree/bindings/riscv/extensions.yaml -+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml -@@ -117,8 +117,9 @@ properties: - - - const: h - description: -- The standard H extension for hypervisors as ratified in the 20191213 -- version of the privileged ISA specification. -+ The standard H extension for hypervisors as ratified in the RISC-V -+ Instruction Set Manual, Volume II Privileged Architecture, -+ Document Version 20211203. - - # multi-letter extensions, sorted alphanumerically - - const: smaia -@@ -202,20 +203,22 @@ properties: - - const: svinval - description: - The standard Svinval supervisor-level extension for fine-grained -- address-translation cache invalidation as ratified in the 20191213 -- version of the privileged ISA specification. -+ address-translation cache invalidation as ratified in the RISC-V -+ Instruction Set Manual, Volume II Privileged Architecture, -+ Document Version 20211203. - - - const: svnapot - description: - The standard Svnapot supervisor-level extensions for napot -- translation contiguity as ratified in the 20191213 version of the -- privileged ISA specification. -+ translation contiguity as ratified in the RISC-V Instruction Set -+ Manual, Volume II Privileged Architecture, Document Version -+ 20211203. - - - const: svpbmt - description: - The standard Svpbmt supervisor-level extensions for page-based -- memory types as ratified in the 20191213 version of the privileged -- ISA specification. -+ memory types as ratified in the RISC-V Instruction Set Manual, -+ Volume II Privileged Architecture, Document Version 20211203. - - - const: svvptc - description: --- -2.53.0 - diff --git a/SPECS/linux-lts/0101-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch b/SPECS/linux-lts/0101-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch deleted file mode 100644 index 3298ffafa4..0000000000 --- a/SPECS/linux-lts/0101-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch +++ /dev/null @@ -1,91 +0,0 @@ -From b7ad5620e1cca351de602305d9722ab055f70643 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Sat, 10 Jan 2026 13:18:18 +0800 -Subject: [PATCH 101/467] UPSTREAM: dt-bindings: riscv: Add B ISA extension - description - -Add description of the single-letter B extension for Bit Manipulation. -B is mandatory for RVA23U64. - -The B extension is ratified in the 20240411 version of the unprivileged -ISA specification. According to the ratified spec, the B standard -extension comprises instructions provided by the Zba, Zbb, and Zbs -extensions. - -Add two-way dependency check to enforce that B implies Zba/Zbb/Zbs; and -when Zba/Zbb/Zbs (all of them) are specified, then B must be added too. - -The reason why B/Zba/Zbb/Zbs must coexist at the same time is that -unlike other single-letter extensions, B was ratified (Apr/2024) much -later than its component extensions Zba/Zbb/Zbs (Jun/2021). - -When "b" is specified, zba/zbb/zbs must be present to ensure -backward compatibility with existing software and kernels that only -look for the explicit component strings. - -When all three components zba/zbb/zbs are specified, "b" should also be -present. Making "b" mandatory when all three components are present. - -Existing devicetrees with zba/zbb/zbs but without "b" will generate -warnings that can be fixed in follow-up patches. - -Signed-off-by: Guodong Xu -Signed-off-by: Conor Dooley -(cherry picked from commit 0cdb7fc1879b1b858463125630f4dd5af6b111ad) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/riscv/extensions.yaml | 31 +++++++++++++++++++ - 1 file changed, 31 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml -index aa38809ecf06..36afd1cc42cf 100644 ---- a/Documentation/devicetree/bindings/riscv/extensions.yaml -+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml -@@ -109,6 +109,13 @@ properties: - The standard C extension for compressed instructions, as ratified in - the 20191213 version of the unprivileged ISA specification. - -+ - const: b -+ description: -+ The standard B extension for bit manipulation instructions, as -+ ratified in the 20240411 version of the unprivileged ISA -+ specification. The B standard extension comprises instructions -+ provided by the Zba, Zbb, and Zbs extensions. -+ - - const: v - description: - The standard V extension for vector operations, as ratified -@@ -727,6 +734,30 @@ properties: - then: - contains: - const: f -+ # B comprises Zba, Zbb, and Zbs -+ - if: -+ contains: -+ const: b -+ then: -+ allOf: -+ - contains: -+ const: zba -+ - contains: -+ const: zbb -+ - contains: -+ const: zbs -+ # Zba, Zbb, Zbs together require B -+ - if: -+ allOf: -+ - contains: -+ const: zba -+ - contains: -+ const: zbb -+ - contains: -+ const: zbs -+ then: -+ contains: -+ const: b - # Zcb depends on Zca - - if: - contains: --- -2.53.0 - diff --git a/SPECS/linux-lts/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch b/SPECS/linux-lts/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch new file mode 100644 index 0000000000..f4ee934072 --- /dev/null +++ b/SPECS/linux-lts/0101-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch @@ -0,0 +1,118 @@ +From 1642e810c6656b4e941561a7bb884e733c44a2f6 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Sat, 10 Jan 2026 13:18:21 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: Add Sha and its comprised + extensions + +Add descriptions for the Sha extension and the seven extensions it +comprises: Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, +and Ssstateen. + +Sha is ratified in the RVA23 Profiles Version 1.0 (commit 0273f3c921b6 +"rva23/rvb23 ratified") as a new profile-defined extension that captures +the full set of features that are mandated to be supported along with +the H extension. + +Extensions Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, +and Ssstateen are ratified in the RISC-V Profiles Version 1.0 (commit +b1d806605f87 "Updated to ratified state"). + +The requirement status for Sha and its comprised extension in RISC-V +Profiles are: + - Sha: Mandatory in RVA23S64 + - H: Optional in RVA22S64; Mandatory in RVA23S64 + - Shcounterenw: Optional in RVA22S64; Mandatory in RVA23S64 + - Shgatpa: Optional in RVA22S64; Mandatory in RVA23S64 + - Shtvala: Optional in RVA22S64; Mandatory in RVA23S64 + - Shvsatpa: Optional in RVA22S64; Mandatory in RVA23S64 + - Shvstvala: Optional in RVA22S64; Mandatory in RVA23S64 + - Shvstvecd: Optional in RVA22S64; Mandatory in RVA23S64 + - Ssstateen: Optional in RVA22S64; Mandatory in RVA23S64 + +Signed-off-by: Guodong Xu +Acked-by: Conor Dooley +Signed-off-by: Conor Dooley +(cherry picked from commit 89febd6a02768200fcfc86ee57f1ece632805bff) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/extensions.yaml | 57 +++++++++++++++++++ + 1 file changed, 57 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml +index 81cff2e5b06f..abe72eaa6c59 100644 +--- a/Documentation/devicetree/bindings/riscv/extensions.yaml ++++ b/Documentation/devicetree/bindings/riscv/extensions.yaml +@@ -129,6 +129,57 @@ properties: + Document Version 20211203. + + # multi-letter extensions, sorted alphanumerically ++ - const: sha ++ description: | ++ The standard Sha extension for augmented hypervisor extension as ++ ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6 ++ ("rva23/rvb23 ratified"). ++ ++ Sha captures the full set of features that are mandated to be ++ supported along with the H extension. Sha comprises the following ++ extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, ++ Shvstvecd, and Ssstateen. ++ ++ - const: shcounterenw ++ description: | ++ The standard Shcounterenw extension for support writable enables ++ in hcounteren for any supported counter, as ratified in RISC-V ++ Profiles Version 1.0, with commit b1d806605f87 ("Updated to ++ ratified state.") ++ ++ - const: shgatpa ++ description: | ++ The standard Shgatpa extension indicates that for each supported ++ virtual memory scheme SvNN supported in satp, the corresponding ++ hgatp SvNNx4 mode must be supported. The hgatp mode Bare must ++ also be supported. It is ratified in RISC-V Profiles Version 1.0, ++ with commit b1d806605f87 ("Updated to ratified state.") ++ ++ - const: shtvala ++ description: | ++ The standard Shtvala extension for htval be written with the ++ faulting guest physical address in all circumstances permitted by ++ the ISA. It is ratified in RISC-V Profiles Version 1.0, with ++ commit b1d806605f87 ("Updated to ratified state.") ++ ++ - const: shvsatpa ++ description: | ++ The standard Shvsatpa extension for vsatp supporting all translation ++ modes supported in satp, as ratified in RISC-V Profiles Version 1.0, ++ with commit b1d806605f87 ("Updated to ratified state.") ++ ++ - const: shvstvala ++ description: | ++ The standard Shvstvala extension for vstval provides all needed ++ values as ratified in RISC-V Profiles Version 1.0, with commit ++ b1d806605f87 ("Updated to ratified state.") ++ ++ - const: shvstvecd ++ description: | ++ The standard Shvstvecd extension for vstvec supporting Direct mode, ++ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 ++ ("Updated to ratified state.") ++ + - const: smaia + description: | + The standard Smaia supervisor-level extension for the advanced +@@ -187,6 +238,12 @@ properties: + ratified at commit d70011dde6c2 ("Update to ratified state") + of riscv-j-extension. + ++ - const: ssstateen ++ description: | ++ The standard Ssstateen extension for supervisor-mode view of the ++ state-enable extension, as ratified in RISC-V Profiles Version 1.0, ++ with commit b1d806605f87 ("Updated to ratified state.") ++ + - const: sstc + description: | + The standard Sstc supervisor-level extension for time compare as +-- +2.53.0 + diff --git a/SPECS/linux-lts/0102-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch b/SPECS/linux-lts/0102-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch deleted file mode 100644 index 10b2fa9c6e..0000000000 --- a/SPECS/linux-lts/0102-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 40de97191a9ea8701aed74a3c0772761a8046235 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Sat, 10 Jan 2026 13:18:19 +0800 -Subject: [PATCH 102/467] UPSTREAM: dt-bindings: riscv: Add descriptions for - Za64rs, Ziccamoa, Ziccif, and Zicclsm - -Add descriptions for four extensions: Za64rs, Ziccamoa, Ziccif, and -Zicclsm. These extensions are ratified in RISC-V Profiles Version 1.0 -(commit b1d806605f87 "Updated to ratified state."). - -They are introduced as new extension names for existing features and -regulate implementation details for RISC-V Profile compliance. According -to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, they are -mandatory for the following profiles: - - - za64rs: Mandatory in RVA22U64, RVA23U64 - - ziccamoa: Mandatory in RVA20U64, RVA22U64, RVA23U64 - - ziccif: Mandatory in RVA20U64, RVA22U64, RVA23U64 - - zicclsm: Mandatory in RVA20U64, RVA22U64, RVA23U64 - -Ziccrse specifies the main memory must support "RsrvEventual", which is -one (totally there are four) of the support level for Load-Reserved/ -Store-Conditional (LR/SC) atomic instructions. Thus it depends on Zalrsc. - -Ziccamoa specifies the main memory must support AMOArithmetic, among the -four levels of PMA support defined for AMOs in the A extension. Thus it -depends on Zaamo. - -Za64rs defines reservation sets are contiguous, naturally aligned, and a -maximum of 64 bytes. Za64rs is consumed by two extensions: Zalrsc and -Zawrs. Zawrs itself depends on Zalrsc too. - -Based on the relationship that "A" = Zaamo + Zalrsc, add the following -dependencies checks: - Za64rs -> Zalrsc or A - Ziccrse -> Zalrsc or A - Ziccamoa -> Zaamo or A - -Signed-off-by: Guodong Xu -Acked-by: Conor Dooley -Signed-off-by: Conor Dooley -(cherry picked from commit b321256a4f36227e0c1ae54e8c6c48524dcba83d) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/riscv/extensions.yaml | 49 +++++++++++++++++++ - 1 file changed, 49 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml -index 36afd1cc42cf..bebbd7797d49 100644 ---- a/Documentation/devicetree/bindings/riscv/extensions.yaml -+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml -@@ -234,6 +234,12 @@ properties: - as ratified at commit 4a69197e5617 ("Update to ratified state") of - riscv-svvptc. - -+ - const: za64rs -+ description: -+ The standard Za64rs extension for reservation set size of at most -+ 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit -+ b1d806605f87 ("Updated to ratified state.") -+ - - const: zaamo - description: | - The standard Zaamo extension for atomic memory operations as -@@ -370,6 +376,27 @@ properties: - in commit 64074bc ("Update version numbers for Zfh/Zfinx") of - riscv-isa-manual. - -+ - const: ziccamoa -+ description: -+ The standard Ziccamoa extension for main memory (cacheability and -+ coherence) must support all atomics in A, as ratified in RISC-V -+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to -+ ratified state.") -+ -+ - const: ziccif -+ description: -+ The standard Ziccif extension for main memory (cacheability and -+ coherence) instruction fetch atomicity, as ratified in RISC-V -+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to -+ ratified state.") -+ -+ - const: zicclsm -+ description: -+ The standard Zicclsm extension for main memory (cacheability and -+ coherence) must support misaligned loads and stores, as ratified -+ in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated -+ to ratified state.") -+ - - const: ziccrse - description: - The standard Ziccrse extension which provides forward progress -@@ -758,6 +785,18 @@ properties: - then: - contains: - const: b -+ # Za64rs and Ziccrse depend on Zalrsc or A -+ - if: -+ contains: -+ anyOf: -+ - const: za64rs -+ - const: ziccrse -+ then: -+ oneOf: -+ - contains: -+ const: zalrsc -+ - contains: -+ const: a - # Zcb depends on Zca - - if: - contains: -@@ -799,6 +838,16 @@ properties: - then: - contains: - const: f -+ # Ziccamoa depends on Zaamo or A -+ - if: -+ contains: -+ const: ziccamoa -+ then: -+ oneOf: -+ - contains: -+ const: zaamo -+ - contains: -+ const: a - # Zvfbfmin depends on V or Zve32f - - if: - contains: --- -2.53.0 - diff --git a/SPECS/linux-lts/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch b/SPECS/linux-lts/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch new file mode 100644 index 0000000000..7eef93f3d7 --- /dev/null +++ b/SPECS/linux-lts/0102-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch @@ -0,0 +1,868 @@ +From 815614b3265facda28aaa4572e120d8f049a9c79 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 07:18:59 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: sophgo: sg2044: Add "b" ISA + extension + +"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs +(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency +checking rule is now enforced, which requires that when zba, zbb, and zbs +are all specified, "b" must be added as well. Failing to do this will +cause dtbs_check schema check warnings. + +According to uabi.rst, as a single-letter extension, "b" should be added +after "c" in canonical order. + +Update sg2044-cpus.dtsi to conform to this rule. + +Signed-off-by: Guodong Xu +Reviewed-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-3-254dd61cf947@riscstar.com +Signed-off-by: Inochi Amaoto +Signed-off-by: Chen Wang +Signed-off-by: Chen Wang +(cherry picked from commit f16ae81b80ca4e721f4c4ed1f28390115f7721eb) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 256 ++++++++++---------- + 1 file changed, 128 insertions(+), 128 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +index 523799a1a8b8..3135409c2149 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +@@ -24,10 +24,10 @@ cpu0: cpu@0 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache0>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -60,10 +60,10 @@ cpu1: cpu@1 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache0>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -96,10 +96,10 @@ cpu2: cpu@2 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache0>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -132,10 +132,10 @@ cpu3: cpu@3 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache0>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -168,10 +168,10 @@ cpu4: cpu@4 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache1>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -204,10 +204,10 @@ cpu5: cpu@5 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache1>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -240,10 +240,10 @@ cpu6: cpu@6 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache1>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -276,10 +276,10 @@ cpu7: cpu@7 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache1>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -312,10 +312,10 @@ cpu8: cpu@8 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache2>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -348,10 +348,10 @@ cpu9: cpu@9 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache2>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -384,10 +384,10 @@ cpu10: cpu@10 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache2>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -420,10 +420,10 @@ cpu11: cpu@11 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache2>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -456,10 +456,10 @@ cpu12: cpu@12 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache3>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -492,10 +492,10 @@ cpu13: cpu@13 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache3>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -528,10 +528,10 @@ cpu14: cpu@14 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache3>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -564,10 +564,10 @@ cpu15: cpu@15 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache3>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -600,10 +600,10 @@ cpu16: cpu@16 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache4>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -636,10 +636,10 @@ cpu17: cpu@17 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache4>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -672,10 +672,10 @@ cpu18: cpu@18 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache4>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -708,10 +708,10 @@ cpu19: cpu@19 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache4>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -744,10 +744,10 @@ cpu20: cpu@20 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache5>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -780,10 +780,10 @@ cpu21: cpu@21 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache5>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -816,10 +816,10 @@ cpu22: cpu@22 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache5>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -852,10 +852,10 @@ cpu23: cpu@23 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache5>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -888,10 +888,10 @@ cpu24: cpu@24 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache6>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -924,10 +924,10 @@ cpu25: cpu@25 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache6>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -960,10 +960,10 @@ cpu26: cpu@26 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache6>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -996,10 +996,10 @@ cpu27: cpu@27 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache6>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1032,10 +1032,10 @@ cpu28: cpu@28 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache7>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1068,10 +1068,10 @@ cpu29: cpu@29 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache7>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1104,10 +1104,10 @@ cpu30: cpu@30 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache7>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1140,10 +1140,10 @@ cpu31: cpu@31 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache7>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1176,10 +1176,10 @@ cpu32: cpu@32 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache8>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1212,10 +1212,10 @@ cpu33: cpu@33 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache8>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1248,10 +1248,10 @@ cpu34: cpu@34 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache8>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1284,10 +1284,10 @@ cpu35: cpu@35 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache8>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1320,10 +1320,10 @@ cpu36: cpu@36 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache9>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1356,10 +1356,10 @@ cpu37: cpu@37 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache9>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1392,10 +1392,10 @@ cpu38: cpu@38 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache9>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1428,10 +1428,10 @@ cpu39: cpu@39 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache9>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1464,10 +1464,10 @@ cpu40: cpu@40 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache10>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1500,10 +1500,10 @@ cpu41: cpu@41 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache10>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1536,10 +1536,10 @@ cpu42: cpu@42 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache10>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1572,10 +1572,10 @@ cpu43: cpu@43 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache10>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1608,10 +1608,10 @@ cpu44: cpu@44 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache11>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1644,10 +1644,10 @@ cpu45: cpu@45 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache11>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1680,10 +1680,10 @@ cpu46: cpu@46 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache11>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1716,10 +1716,10 @@ cpu47: cpu@47 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache11>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1752,10 +1752,10 @@ cpu48: cpu@48 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache12>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1788,10 +1788,10 @@ cpu49: cpu@49 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache12>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1824,10 +1824,10 @@ cpu50: cpu@50 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache12>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1860,10 +1860,10 @@ cpu51: cpu@51 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache12>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1896,10 +1896,10 @@ cpu52: cpu@52 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache13>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1932,10 +1932,10 @@ cpu53: cpu@53 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache13>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -1968,10 +1968,10 @@ cpu54: cpu@54 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache13>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2004,10 +2004,10 @@ cpu55: cpu@55 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache13>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2040,10 +2040,10 @@ cpu56: cpu@56 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache14>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2076,10 +2076,10 @@ cpu57: cpu@57 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache14>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2112,10 +2112,10 @@ cpu58: cpu@58 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache14>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2148,10 +2148,10 @@ cpu59: cpu@59 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache14>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2184,10 +2184,10 @@ cpu60: cpu@60 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache15>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2220,10 +2220,10 @@ cpu61: cpu@61 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache15>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2256,10 +2256,10 @@ cpu62: cpu@62 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache15>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +@@ -2292,10 +2292,10 @@ cpu63: cpu@63 { + device_type = "cpu"; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2_cache15>; +- riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdcbv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", +- "v", "sscofpmf", "sstc", ++ "b", "v", "sscofpmf", "sstc", + "svinval", "svnapot", "svpbmt", + "zawrs", "zba", "zbb", "zbc", + "zbs", "zca", "zcb", "zcd", +-- +2.53.0 + diff --git a/SPECS/linux-lts/0103-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch b/SPECS/linux-lts/0103-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch deleted file mode 100644 index 8f9f20a577..0000000000 --- a/SPECS/linux-lts/0103-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch +++ /dev/null @@ -1,89 +0,0 @@ -From cb41ade08efabd7980780c3df13115056b7d5bbe Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Sat, 10 Jan 2026 13:18:20 +0800 -Subject: [PATCH 103/467] UPSTREAM: dt-bindings: riscv: Add Ssccptr, - Sscounterenw, Sstvala, Sstvecd, Ssu64xl - -Add descriptions for five new extensions: Ssccptr, Sscounterenw, Sstvala, -Sstvecd, and Ssu64xl. These extensions are ratified in RISC-V Profiles -Version 1.0 (commit b1d806605f87 "Updated to ratified state."). - -They are introduced as new extension names for existing features and -regulate implementation details for RISC-V Profile compliance. According -to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, their -requirement status are: - - - Ssccptr: Mandatory in RVA20S64, RVA22S64, RVA23S64 - - Sscounterenw: Mandatory in RVA22S64, RVA23S64 - - Sstvala: Mandatory in RVA20S64, RVA22S64, RVA23S64 - - Sstvecd: Mandatory in RVA20S64, RVA22S64, RVA23S64 - - Ssu64xl: Optional in RVA20S64, RVA22S64; Mandatory in RVA23S64 - -Signed-off-by: Guodong Xu -Acked-by: Conor Dooley -Signed-off-by: Conor Dooley -(cherry picked from commit c712413333f8e19cc3de4e9cd1a3ed8a53169cc9) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/riscv/extensions.yaml | 32 +++++++++++++++++++ - 1 file changed, 32 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml -index bebbd7797d49..81cff2e5b06f 100644 ---- a/Documentation/devicetree/bindings/riscv/extensions.yaml -+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml -@@ -161,12 +161,26 @@ properties: - behavioural changes to interrupts as frozen at commit ccbddab - ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. - -+ - const: ssccptr -+ description: | -+ The standard Ssccptr extension for main memory (cacheability and -+ coherence) hardware page-table reads, as ratified in RISC-V -+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to -+ ratified state.") -+ - - const: sscofpmf - description: | - The standard Sscofpmf supervisor-level extension for count overflow - and mode-based filtering as ratified at commit 01d1df0 ("Add ability - to manually trigger workflow. (#2)") of riscv-count-overflow. - -+ - const: sscounterenw -+ description: | -+ The standard Sscounterenw extension for support writable enables -+ in scounteren for any supported counter, as ratified in RISC-V -+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to -+ ratified state.") -+ - - const: ssnpm - description: | - The standard Ssnpm extension for next-mode pointer masking as -@@ -179,6 +193,24 @@ properties: - ratified at commit 3f9ed34 ("Add ability to manually trigger - workflow. (#2)") of riscv-time-compare. - -+ - const: sstvala -+ description: | -+ The standard Sstvala extension for stval provides all needed values -+ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 -+ ("Updated to ratified state.") -+ -+ - const: sstvecd -+ description: | -+ The standard Sstvecd extension for stvec supports Direct mode as -+ ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 -+ ("Updated to ratified state.") -+ -+ - const: ssu64xl -+ description: | -+ The standard Ssu64xl extension for UXLEN=64 must be supported, as -+ ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 -+ ("Updated to ratified state.") -+ - - const: svade - description: | - The standard Svade supervisor-level extension for SW-managed PTE A/D --- -2.53.0 - diff --git a/SPECS/linux-lts/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch b/SPECS/linux-lts/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch new file mode 100644 index 0000000000..1f0aba5728 --- /dev/null +++ b/SPECS/linux-lts/0103-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch @@ -0,0 +1,130 @@ +From 039b44e9b855295ac8945486ffea47d65240d000 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 07:19:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k1: Add "b" ISA + extension + +"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs +(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency +checking rule is now enforced, which requires that when zba, zbb, and zbs +are all specified, "b" must be added as well. Failing to do this will +cause dtbs_check schema check warnings. + +According to uabi.rst, as a single-letter extension, "b" should be added +after "c" in canonical order. + +Update k1.dtsi to conform to this rule. + +Signed-off-by: Guodong Xu +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-4-254dd61cf947@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 4168630825f95bf57729dad46d2a097096e73e4d) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 32 ++++++++++++++-------------- + 1 file changed, 16 insertions(+), 16 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index e22a5f030fa2..0a884947fda4 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -54,9 +54,9 @@ cpu_0: cpu@0 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <0>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -84,9 +84,9 @@ cpu_1: cpu@1 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <1>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -114,9 +114,9 @@ cpu_2: cpu@2 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <2>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -144,9 +144,9 @@ cpu_3: cpu@3 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <3>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -174,9 +174,9 @@ cpu_4: cpu@4 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <4>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -204,9 +204,9 @@ cpu_5: cpu@5 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <5>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -234,9 +234,9 @@ cpu_6: cpu@6 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <6>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +@@ -264,9 +264,9 @@ cpu_7: cpu@7 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <7>; +- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; ++ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; +- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicond", "zicsr", + "zifencei", "zihintpause", "zihpm", "zfh", "zba", + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", +-- +2.53.0 + diff --git a/SPECS/linux-lts/0104-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch b/SPECS/linux-lts/0104-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch deleted file mode 100644 index 6613221727..0000000000 --- a/SPECS/linux-lts/0104-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 76d1441d889e836547a5be7be06231426dd50fc7 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Sat, 10 Jan 2026 13:18:21 +0800 -Subject: [PATCH 104/467] UPSTREAM: dt-bindings: riscv: Add Sha and its - comprised extensions - -Add descriptions for the Sha extension and the seven extensions it -comprises: Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, -and Ssstateen. - -Sha is ratified in the RVA23 Profiles Version 1.0 (commit 0273f3c921b6 -"rva23/rvb23 ratified") as a new profile-defined extension that captures -the full set of features that are mandated to be supported along with -the H extension. - -Extensions Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, -and Ssstateen are ratified in the RISC-V Profiles Version 1.0 (commit -b1d806605f87 "Updated to ratified state"). - -The requirement status for Sha and its comprised extension in RISC-V -Profiles are: - - Sha: Mandatory in RVA23S64 - - H: Optional in RVA22S64; Mandatory in RVA23S64 - - Shcounterenw: Optional in RVA22S64; Mandatory in RVA23S64 - - Shgatpa: Optional in RVA22S64; Mandatory in RVA23S64 - - Shtvala: Optional in RVA22S64; Mandatory in RVA23S64 - - Shvsatpa: Optional in RVA22S64; Mandatory in RVA23S64 - - Shvstvala: Optional in RVA22S64; Mandatory in RVA23S64 - - Shvstvecd: Optional in RVA22S64; Mandatory in RVA23S64 - - Ssstateen: Optional in RVA22S64; Mandatory in RVA23S64 - -Signed-off-by: Guodong Xu -Acked-by: Conor Dooley -Signed-off-by: Conor Dooley -(cherry picked from commit 89febd6a02768200fcfc86ee57f1ece632805bff) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/riscv/extensions.yaml | 57 +++++++++++++++++++ - 1 file changed, 57 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml -index 81cff2e5b06f..abe72eaa6c59 100644 ---- a/Documentation/devicetree/bindings/riscv/extensions.yaml -+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml -@@ -129,6 +129,57 @@ properties: - Document Version 20211203. - - # multi-letter extensions, sorted alphanumerically -+ - const: sha -+ description: | -+ The standard Sha extension for augmented hypervisor extension as -+ ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6 -+ ("rva23/rvb23 ratified"). -+ -+ Sha captures the full set of features that are mandated to be -+ supported along with the H extension. Sha comprises the following -+ extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, -+ Shvstvecd, and Ssstateen. -+ -+ - const: shcounterenw -+ description: | -+ The standard Shcounterenw extension for support writable enables -+ in hcounteren for any supported counter, as ratified in RISC-V -+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to -+ ratified state.") -+ -+ - const: shgatpa -+ description: | -+ The standard Shgatpa extension indicates that for each supported -+ virtual memory scheme SvNN supported in satp, the corresponding -+ hgatp SvNNx4 mode must be supported. The hgatp mode Bare must -+ also be supported. It is ratified in RISC-V Profiles Version 1.0, -+ with commit b1d806605f87 ("Updated to ratified state.") -+ -+ - const: shtvala -+ description: | -+ The standard Shtvala extension for htval be written with the -+ faulting guest physical address in all circumstances permitted by -+ the ISA. It is ratified in RISC-V Profiles Version 1.0, with -+ commit b1d806605f87 ("Updated to ratified state.") -+ -+ - const: shvsatpa -+ description: | -+ The standard Shvsatpa extension for vsatp supporting all translation -+ modes supported in satp, as ratified in RISC-V Profiles Version 1.0, -+ with commit b1d806605f87 ("Updated to ratified state.") -+ -+ - const: shvstvala -+ description: | -+ The standard Shvstvala extension for vstval provides all needed -+ values as ratified in RISC-V Profiles Version 1.0, with commit -+ b1d806605f87 ("Updated to ratified state.") -+ -+ - const: shvstvecd -+ description: | -+ The standard Shvstvecd extension for vstvec supporting Direct mode, -+ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 -+ ("Updated to ratified state.") -+ - - const: smaia - description: | - The standard Smaia supervisor-level extension for the advanced -@@ -187,6 +238,12 @@ properties: - ratified at commit d70011dde6c2 ("Update to ratified state") - of riscv-j-extension. - -+ - const: ssstateen -+ description: | -+ The standard Ssstateen extension for supervisor-mode view of the -+ state-enable extension, as ratified in RISC-V Profiles Version 1.0, -+ with commit b1d806605f87 ("Updated to ratified state.") -+ - - const: sstc - description: | - The standard Sstc supervisor-level extension for time compare as --- -2.53.0 - diff --git a/SPECS/linux-lts/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch b/SPECS/linux-lts/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch new file mode 100644 index 0000000000..8f2845d570 --- /dev/null +++ b/SPECS/linux-lts/0104-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch @@ -0,0 +1,48 @@ +From 3a49674fb8ec24236b9a789e322ccc05b66c4d65 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:40 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: add SpacemiT X100 CPU + compatible + +Add compatible string for the SpacemiT X100 core. [1] + +The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100 +supports the RISC-V vector and hypervisor extensions and all mandatory +extersions as required by the RVA23U64 and RVA23S64 profiles, per the +definition in 'RVA23 Profile, Version 1.0'. [2] + +From a microarchieture viewpoint, the X100 features a 4-issue +out-of-order pipeline. + +X100 is used in SpacemiT K3 SoC. + +Acked-by: Paul Walmsley +Acked-by: Krzysztof Kozlowski +Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] +Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2] +Reviewed-by: Yixun Lan +Reviewed-by: Heinrich Schuchardt +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-1-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 81a52103b90f5cddc41c34f633c014a956236abc) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml +index 153d0dac57fb..a86819565394 100644 +--- a/Documentation/devicetree/bindings/riscv/cpus.yaml ++++ b/Documentation/devicetree/bindings/riscv/cpus.yaml +@@ -60,6 +60,7 @@ properties: + - sifive,u7 + - sifive,u74 + - sifive,u74-mc ++ - spacemit,x100 + - spacemit,x60 + - thead,c906 + - thead,c908 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch b/SPECS/linux-lts/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch new file mode 100644 index 0000000000..10acec0266 --- /dev/null +++ b/SPECS/linux-lts/0105-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch @@ -0,0 +1,32 @@ +From 9e4be2e7c734325e83668eba93f9e2dbc1220efa Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:41 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: timer: add SpacemiT K3 CLINT + +Add compatible string for SpacemiT K3 CLINT. + +Acked-by: Conor Dooley +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-2-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 6cdeb30db4d8faf9f1fa7ab863d91d36a584716d) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml +index d85a1a088b35..63165939465a 100644 +--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml ++++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml +@@ -33,6 +33,7 @@ properties: + - eswin,eic7700-clint # ESWIN EIC7700 + - sifive,fu540-c000-clint # SiFive FU540 + - spacemit,k1-clint # SpacemiT K1 ++ - spacemit,k3-clint # SpacemiT K3 + - starfive,jh7100-clint # StarFive JH7100 + - starfive,jh7110-clint # StarFive JH7110 + - starfive,jh8100-clint # StarFive JH8100 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0105-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch b/SPECS/linux-lts/0105-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch deleted file mode 100644 index fb246009b4..0000000000 --- a/SPECS/linux-lts/0105-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch +++ /dev/null @@ -1,868 +0,0 @@ -From 0fd7679a286d8f4656076076047b3c5627b87815 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 07:18:59 +0800 -Subject: [PATCH 105/467] UPSTREAM: riscv: dts: sophgo: sg2044: Add "b" ISA - extension - -"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs -(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency -checking rule is now enforced, which requires that when zba, zbb, and zbs -are all specified, "b" must be added as well. Failing to do this will -cause dtbs_check schema check warnings. - -According to uabi.rst, as a single-letter extension, "b" should be added -after "c" in canonical order. - -Update sg2044-cpus.dtsi to conform to this rule. - -Signed-off-by: Guodong Xu -Reviewed-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-3-254dd61cf947@riscstar.com -Signed-off-by: Inochi Amaoto -Signed-off-by: Chen Wang -Signed-off-by: Chen Wang -(cherry picked from commit f16ae81b80ca4e721f4c4ed1f28390115f7721eb) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 256 ++++++++++---------- - 1 file changed, 128 insertions(+), 128 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -index 523799a1a8b8..3135409c2149 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -@@ -24,10 +24,10 @@ cpu0: cpu@0 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache0>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -60,10 +60,10 @@ cpu1: cpu@1 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache0>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -96,10 +96,10 @@ cpu2: cpu@2 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache0>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -132,10 +132,10 @@ cpu3: cpu@3 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache0>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -168,10 +168,10 @@ cpu4: cpu@4 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache1>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -204,10 +204,10 @@ cpu5: cpu@5 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache1>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -240,10 +240,10 @@ cpu6: cpu@6 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache1>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -276,10 +276,10 @@ cpu7: cpu@7 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache1>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -312,10 +312,10 @@ cpu8: cpu@8 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache2>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -348,10 +348,10 @@ cpu9: cpu@9 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache2>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -384,10 +384,10 @@ cpu10: cpu@10 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache2>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -420,10 +420,10 @@ cpu11: cpu@11 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache2>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -456,10 +456,10 @@ cpu12: cpu@12 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache3>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -492,10 +492,10 @@ cpu13: cpu@13 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache3>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -528,10 +528,10 @@ cpu14: cpu@14 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache3>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -564,10 +564,10 @@ cpu15: cpu@15 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache3>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -600,10 +600,10 @@ cpu16: cpu@16 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache4>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -636,10 +636,10 @@ cpu17: cpu@17 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache4>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -672,10 +672,10 @@ cpu18: cpu@18 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache4>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -708,10 +708,10 @@ cpu19: cpu@19 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache4>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -744,10 +744,10 @@ cpu20: cpu@20 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache5>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -780,10 +780,10 @@ cpu21: cpu@21 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache5>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -816,10 +816,10 @@ cpu22: cpu@22 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache5>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -852,10 +852,10 @@ cpu23: cpu@23 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache5>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -888,10 +888,10 @@ cpu24: cpu@24 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache6>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -924,10 +924,10 @@ cpu25: cpu@25 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache6>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -960,10 +960,10 @@ cpu26: cpu@26 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache6>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -996,10 +996,10 @@ cpu27: cpu@27 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache6>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1032,10 +1032,10 @@ cpu28: cpu@28 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache7>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1068,10 +1068,10 @@ cpu29: cpu@29 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache7>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1104,10 +1104,10 @@ cpu30: cpu@30 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache7>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1140,10 +1140,10 @@ cpu31: cpu@31 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache7>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1176,10 +1176,10 @@ cpu32: cpu@32 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache8>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1212,10 +1212,10 @@ cpu33: cpu@33 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache8>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1248,10 +1248,10 @@ cpu34: cpu@34 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache8>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1284,10 +1284,10 @@ cpu35: cpu@35 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache8>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1320,10 +1320,10 @@ cpu36: cpu@36 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache9>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1356,10 +1356,10 @@ cpu37: cpu@37 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache9>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1392,10 +1392,10 @@ cpu38: cpu@38 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache9>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1428,10 +1428,10 @@ cpu39: cpu@39 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache9>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1464,10 +1464,10 @@ cpu40: cpu@40 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache10>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1500,10 +1500,10 @@ cpu41: cpu@41 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache10>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1536,10 +1536,10 @@ cpu42: cpu@42 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache10>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1572,10 +1572,10 @@ cpu43: cpu@43 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache10>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1608,10 +1608,10 @@ cpu44: cpu@44 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache11>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1644,10 +1644,10 @@ cpu45: cpu@45 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache11>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1680,10 +1680,10 @@ cpu46: cpu@46 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache11>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1716,10 +1716,10 @@ cpu47: cpu@47 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache11>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1752,10 +1752,10 @@ cpu48: cpu@48 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache12>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1788,10 +1788,10 @@ cpu49: cpu@49 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache12>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1824,10 +1824,10 @@ cpu50: cpu@50 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache12>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1860,10 +1860,10 @@ cpu51: cpu@51 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache12>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1896,10 +1896,10 @@ cpu52: cpu@52 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache13>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1932,10 +1932,10 @@ cpu53: cpu@53 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache13>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -1968,10 +1968,10 @@ cpu54: cpu@54 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache13>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2004,10 +2004,10 @@ cpu55: cpu@55 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache13>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2040,10 +2040,10 @@ cpu56: cpu@56 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache14>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2076,10 +2076,10 @@ cpu57: cpu@57 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache14>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2112,10 +2112,10 @@ cpu58: cpu@58 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache14>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2148,10 +2148,10 @@ cpu59: cpu@59 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache14>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2184,10 +2184,10 @@ cpu60: cpu@60 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache15>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2220,10 +2220,10 @@ cpu61: cpu@61 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache15>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2256,10 +2256,10 @@ cpu62: cpu@62 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache15>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", -@@ -2292,10 +2292,10 @@ cpu63: cpu@63 { - device_type = "cpu"; - mmu-type = "riscv,sv48"; - next-level-cache = <&l2_cache15>; -- riscv,isa = "rv64imafdcv"; -+ riscv,isa = "rv64imafdcbv"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -- "v", "sscofpmf", "sstc", -+ "b", "v", "sscofpmf", "sstc", - "svinval", "svnapot", "svpbmt", - "zawrs", "zba", "zbb", "zbc", - "zbs", "zca", "zcb", "zcd", --- -2.53.0 - diff --git a/SPECS/linux-lts/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch b/SPECS/linux-lts/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch new file mode 100644 index 0000000000..f8b908b4e1 --- /dev/null +++ b/SPECS/linux-lts/0106-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch @@ -0,0 +1,33 @@ +From 57ea95edd2da52d808cbd5a6d874d1cb368dea05 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:42 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: add + SpacemiT K3 APLIC + +Add compatible string for SpacemiT K3 APLIC. + +Acked-by: Conor Dooley +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-3-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 60490ca6d54b6f0a00223a4fe59bb180bb1538bf) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +index bef00521d5da..0718071444d2 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml ++++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +@@ -28,6 +28,7 @@ properties: + items: + - enum: + - qemu,aplic ++ - spacemit,k3-aplic + - const: riscv,aplic + + reg: +-- +2.53.0 + diff --git a/SPECS/linux-lts/0106-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch b/SPECS/linux-lts/0106-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch deleted file mode 100644 index 8190f7f0ca..0000000000 --- a/SPECS/linux-lts/0106-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch +++ /dev/null @@ -1,130 +0,0 @@ -From adaead5f6b5ea0e1fd34595fb5fe60ad48dd0471 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 07:19:00 +0800 -Subject: [PATCH 106/467] UPSTREAM: riscv: dts: spacemit: k1: Add "b" ISA - extension - -"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs -(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency -checking rule is now enforced, which requires that when zba, zbb, and zbs -are all specified, "b" must be added as well. Failing to do this will -cause dtbs_check schema check warnings. - -According to uabi.rst, as a single-letter extension, "b" should be added -after "c" in canonical order. - -Update k1.dtsi to conform to this rule. - -Signed-off-by: Guodong Xu -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-4-254dd61cf947@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 4168630825f95bf57729dad46d2a097096e73e4d) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 32 ++++++++++++++-------------- - 1 file changed, 16 insertions(+), 16 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index e22a5f030fa2..0a884947fda4 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -54,9 +54,9 @@ cpu_0: cpu@0 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <0>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -84,9 +84,9 @@ cpu_1: cpu@1 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <1>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -114,9 +114,9 @@ cpu_2: cpu@2 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <2>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -144,9 +144,9 @@ cpu_3: cpu@3 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <3>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -174,9 +174,9 @@ cpu_4: cpu@4 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <4>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -204,9 +204,9 @@ cpu_5: cpu@5 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <5>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -234,9 +234,9 @@ cpu_6: cpu@6 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <6>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", -@@ -264,9 +264,9 @@ cpu_7: cpu@7 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <7>; -- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; -+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; -- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", --- -2.53.0 - diff --git a/SPECS/linux-lts/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch b/SPECS/linux-lts/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch new file mode 100644 index 0000000000..9699a897cf --- /dev/null +++ b/SPECS/linux-lts/0107-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch @@ -0,0 +1,33 @@ +From 7d7a00a794501c279b94f46e44c33a60cc0ecf71 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:43 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: add + SpacemiT K3 IMSIC + +Add compatible string for SpacemiT K3 IMSIC. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-4-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit a716729a3ce1055efab477030235777d2be0852b) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/interrupt-controller/riscv,imsics.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml +index c23b5c09fdb9..feec122bddde 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml ++++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml +@@ -48,6 +48,7 @@ properties: + items: + - enum: + - qemu,imsics ++ - spacemit,k3-imsics + - const: riscv,imsics + + reg: +-- +2.53.0 + diff --git a/SPECS/linux-lts/0107-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch b/SPECS/linux-lts/0107-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch deleted file mode 100644 index 809cf69223..0000000000 --- a/SPECS/linux-lts/0107-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 8e1a61160ad52213d592d47106334dc60232a82b Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:40 +0800 -Subject: [PATCH 107/467] UPSTREAM: dt-bindings: riscv: add SpacemiT X100 CPU - compatible - -Add compatible string for the SpacemiT X100 core. [1] - -The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100 -supports the RISC-V vector and hypervisor extensions and all mandatory -extersions as required by the RVA23U64 and RVA23S64 profiles, per the -definition in 'RVA23 Profile, Version 1.0'. [2] - -From a microarchieture viewpoint, the X100 features a 4-issue -out-of-order pipeline. - -X100 is used in SpacemiT K3 SoC. - -Acked-by: Paul Walmsley -Acked-by: Krzysztof Kozlowski -Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] -Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2] -Reviewed-by: Yixun Lan -Reviewed-by: Heinrich Schuchardt -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-1-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 81a52103b90f5cddc41c34f633c014a956236abc) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml -index 153d0dac57fb..a86819565394 100644 ---- a/Documentation/devicetree/bindings/riscv/cpus.yaml -+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml -@@ -60,6 +60,7 @@ properties: - - sifive,u7 - - sifive,u74 - - sifive,u74-mc -+ - spacemit,x100 - - spacemit,x60 - - thead,c906 - - thead,c908 --- -2.53.0 - diff --git a/SPECS/linux-lts/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch b/SPECS/linux-lts/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch new file mode 100644 index 0000000000..0f66a78fa3 --- /dev/null +++ b/SPECS/linux-lts/0108-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch @@ -0,0 +1,46 @@ +From 90385ee4dee92d3b318cb4a03b5de245c87b06f2 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:44 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: riscv: spacemit: add K3 and + Pico-ITX board bindings + +Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX +which is a 2.5-inch single-board computer. + +Acked-by: Conor Dooley +Reviewed-by: Yixun Lan +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-5-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 7cb5fafc180f6e188af7943d6b162051f22490fc) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml +index c56b62a6299a..eca403a8e49e 100644 +--- a/Documentation/devicetree/bindings/riscv/spacemit.yaml ++++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml +@@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# + title: SpacemiT SoC-based boards + + maintainers: ++ - Guodong Xu + - Yangyu Chen + - Yixun Lan + +@@ -24,6 +25,10 @@ properties: + - milkv,jupiter + - xunlong,orangepi-rv2 + - const: spacemit,k1 ++ - items: ++ - enum: ++ - spacemit,k3-pico-itx ++ - const: spacemit,k3 + + additionalProperties: true + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0108-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch b/SPECS/linux-lts/0108-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch deleted file mode 100644 index 8b1c7bc20d..0000000000 --- a/SPECS/linux-lts/0108-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 7095ed807e459baec17231d727e1e5399c4753c7 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:41 +0800 -Subject: [PATCH 108/467] UPSTREAM: dt-bindings: timer: add SpacemiT K3 CLINT - -Add compatible string for SpacemiT K3 CLINT. - -Acked-by: Conor Dooley -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-2-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 6cdeb30db4d8faf9f1fa7ab863d91d36a584716d) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml -index d85a1a088b35..63165939465a 100644 ---- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml -+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml -@@ -33,6 +33,7 @@ properties: - - eswin,eic7700-clint # ESWIN EIC7700 - - sifive,fu540-c000-clint # SiFive FU540 - - spacemit,k1-clint # SpacemiT K1 -+ - spacemit,k3-clint # SpacemiT K3 - - starfive,jh7100-clint # StarFive JH7100 - - starfive,jh7110-clint # StarFive JH7110 - - starfive,jh8100-clint # StarFive JH8100 --- -2.53.0 - diff --git a/SPECS/linux-lts/0109-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch b/SPECS/linux-lts/0109-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch deleted file mode 100644 index 3257d1e8d2..0000000000 --- a/SPECS/linux-lts/0109-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch +++ /dev/null @@ -1,33 +0,0 @@ -From a5bf205e23df3a195f132f1b23867635454771e9 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:42 +0800 -Subject: [PATCH 109/467] UPSTREAM: dt-bindings: interrupt-controller: add - SpacemiT K3 APLIC - -Add compatible string for SpacemiT K3 APLIC. - -Acked-by: Conor Dooley -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-3-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 60490ca6d54b6f0a00223a4fe59bb180bb1538bf) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml -index bef00521d5da..0718071444d2 100644 ---- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml -+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml -@@ -28,6 +28,7 @@ properties: - items: - - enum: - - qemu,aplic -+ - spacemit,k3-aplic - - const: riscv,aplic - - reg: --- -2.53.0 - diff --git a/SPECS/linux-lts/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch b/SPECS/linux-lts/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch new file mode 100644 index 0000000000..f038974db6 --- /dev/null +++ b/SPECS/linux-lts/0109-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch @@ -0,0 +1,608 @@ +From b4a0b52d7cdbe329b44301f63847faf1c8631060 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:45 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add initial support for + K3 SoC + +SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant. +Add nodes of uarts, timer and interrupt-controllers. Also add M-mode +APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware +topology and ready for potential firmware usage. + +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-6-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 56f37e391a626f964615ee5939710eff212b621f) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 578 +++++++++++++++++++++++++++ + 1 file changed, 578 insertions(+) + create mode 100644 arch/riscv/boot/dts/spacemit/k3.dtsi + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +new file mode 100644 +index 000000000000..b69cf81b5d55 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -0,0 +1,578 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ * Copyright (c) 2026 Guodong Xu ++ */ ++ ++#include ++ ++/dts-v1/; ++ ++/ { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ model = "SpacemiT K3"; ++ compatible = "spacemit,k3"; ++ ++ cpus: cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ timebase-frequency = <24000000>; ++ ++ cpu_0: cpu@0 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <0>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache0>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu0_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_1: cpu@1 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <1>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache0>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu1_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_2: cpu@2 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <2>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache0>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu2_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_3: cpu@3 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <3>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache0>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu3_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_4: cpu@4 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <4>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache1>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu4_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_5: cpu@5 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <5>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache1>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu5_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_6: cpu@6 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <6>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache1>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu6_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ cpu_7: cpu@7 { ++ compatible = "spacemit,x100", "riscv"; ++ device_type = "cpu"; ++ reg = <7>; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", ++ "sha", "shcounterenw", "shgatpa", "shtvala", ++ "shvsatpa", "shvstvala", "shvstvecd", "smaia", ++ "smstateen", "ssaia", "ssccptr", "sscofpmf", ++ "sscounterenw", "ssnpm", "ssstateen", "sstc", ++ "sstvala", "sstvecd", "ssu64xl", "svade", ++ "svinval", "svnapot", "svpbmt", "za64rs", ++ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", ++ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", ++ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", ++ "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "zicond", "zicsr", "zifencei", "zihintntl", ++ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", ++ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", ++ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", ++ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", ++ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; ++ i-cache-block-size = <64>; ++ i-cache-size = <65536>; ++ i-cache-sets = <256>; ++ d-cache-block-size = <64>; ++ d-cache-size = <65536>; ++ d-cache-sets = <256>; ++ next-level-cache = <&l2_cache1>; ++ mmu-type = "riscv,sv39"; ++ ++ cpu7_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ l2_cache0: cache-controller-0 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <4194304>; ++ cache-sets = <4096>; ++ cache-unified; ++ }; ++ ++ l2_cache1: cache-controller-1 { ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <4194304>; ++ cache-sets = <4096>; ++ cache-unified; ++ }; ++ ++ cpu-map { ++ cluster0 { ++ core0 { ++ cpu = <&cpu_0>; ++ }; ++ core1 { ++ cpu = <&cpu_1>; ++ }; ++ core2 { ++ cpu = <&cpu_2>; ++ }; ++ core3 { ++ cpu = <&cpu_3>; ++ }; ++ }; ++ ++ cluster1 { ++ core0 { ++ cpu = <&cpu_4>; ++ }; ++ core1 { ++ cpu = <&cpu_5>; ++ }; ++ core2 { ++ cpu = <&cpu_6>; ++ }; ++ core3 { ++ cpu = <&cpu_7>; ++ }; ++ }; ++ }; ++ }; ++ ++ soc: soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&saplic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ dma-noncoherent; ++ ranges; ++ ++ uart0: serial@d4017000 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@d4017100 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017100 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@d4017200 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017200 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@d4017300 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017300 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart5: serial@d4017400 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017400 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart6: serial@d4017500 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017500 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart7: serial@d4017600 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017600 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart8: serial@d4017700 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017700 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart9: serial@d4017800 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd4017800 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ uart10: serial@d401f000 { ++ compatible = "spacemit,k3-uart", "intel,xscale-uart"; ++ reg = <0x0 0xd401f000 0x0 0x100>; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ clock-frequency = <14700000>; ++ interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ ++ simsic: interrupt-controller@e0400000 { ++ compatible = "spacemit,k3-imsics", "riscv,imsics"; ++ reg = <0x0 0xe0400000 0x0 0x200000>; ++ #interrupt-cells = <0>; ++ #msi-cells = <0>; ++ interrupt-controller; ++ interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, ++ <&cpu2_intc 9>, <&cpu3_intc 9>, ++ <&cpu4_intc 9>, <&cpu5_intc 9>, ++ <&cpu6_intc 9>, <&cpu7_intc 9>; ++ msi-controller; ++ riscv,guest-index-bits = <6>; ++ riscv,hart-index-bits = <4>; ++ riscv,num-guest-ids = <511>; ++ riscv,num-ids = <511>; ++ }; ++ ++ saplic: interrupt-controller@e0804000 { ++ compatible = "spacemit,k3-aplic", "riscv,aplic"; ++ reg = <0x0 0xe0804000 0x0 0x4000>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ msi-parent = <&simsic>; ++ riscv,num-sources = <512>; ++ }; ++ ++ clint: timer@e081c000 { ++ compatible = "spacemit,k3-clint", "sifive,clint0"; ++ reg = <0x0 0xe081c000 0x0 0x4000>; ++ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, ++ <&cpu1_intc 3>, <&cpu1_intc 7>, ++ <&cpu2_intc 3>, <&cpu2_intc 7>, ++ <&cpu3_intc 3>, <&cpu3_intc 7>, ++ <&cpu4_intc 3>, <&cpu4_intc 7>, ++ <&cpu5_intc 3>, <&cpu5_intc 7>, ++ <&cpu6_intc 3>, <&cpu6_intc 7>, ++ <&cpu7_intc 3>, <&cpu7_intc 7>; ++ }; ++ ++ mimsic: interrupt-controller@f1000000 { ++ compatible = "spacemit,k3-imsics", "riscv,imsics"; ++ reg = <0x0 0xf1000000 0x0 0x10000>; ++ #interrupt-cells = <0>; ++ #msi-cells = <0>; ++ interrupt-controller; ++ interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, ++ <&cpu2_intc 11>, <&cpu3_intc 11>, ++ <&cpu4_intc 11>, <&cpu5_intc 11>, ++ <&cpu6_intc 11>, <&cpu7_intc 11>; ++ msi-controller; ++ riscv,guest-index-bits = <6>; ++ riscv,hart-index-bits = <4>; ++ riscv,num-guest-ids = <511>; ++ riscv,num-ids = <511>; ++ status = "reserved"; ++ }; ++ ++ maplic: interrupt-controller@f1800000 { ++ compatible = "spacemit,k3-aplic", "riscv,aplic"; ++ reg = <0x0 0xf1800000 0x0 0x4000>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ msi-parent = <&mimsic>; ++ riscv,children = <&saplic>; ++ riscv,delegation = <&saplic 1 512>; ++ riscv,num-sources = <512>; ++ status = "reserved"; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0110-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch b/SPECS/linux-lts/0110-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch deleted file mode 100644 index 1568e712e5..0000000000 --- a/SPECS/linux-lts/0110-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch +++ /dev/null @@ -1,33 +0,0 @@ -From d63371e2a5c8738aa915c7d56267e1a929c22dba Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:43 +0800 -Subject: [PATCH 110/467] UPSTREAM: dt-bindings: interrupt-controller: add - SpacemiT K3 IMSIC - -Add compatible string for SpacemiT K3 IMSIC. - -Acked-by: Krzysztof Kozlowski -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-4-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit a716729a3ce1055efab477030235777d2be0852b) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/interrupt-controller/riscv,imsics.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml -index c23b5c09fdb9..feec122bddde 100644 ---- a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml -+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml -@@ -48,6 +48,7 @@ properties: - items: - - enum: - - qemu,imsics -+ - spacemit,k3-imsics - - const: riscv,imsics - - reg: --- -2.53.0 - diff --git a/SPECS/linux-lts/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch b/SPECS/linux-lts/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch new file mode 100644 index 0000000000..f252517e9d --- /dev/null +++ b/SPECS/linux-lts/0110-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch @@ -0,0 +1,70 @@ +From 377151dae3f25558fd27556e52c4f0854c988c8b Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Thu, 15 Jan 2026 14:51:46 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add K3 Pico-ITX board + support + +K3 Pico-ITX is a 2.5-inch single-board computer equipted with a SpacemiT +K3 SoC. + +This minimal device tree enables booting into a serial console with UART +output. + +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-7-6990ac9f4308@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 7a61318049861b777f098d7148d892d7dc79b010) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/Makefile | 1 + + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++++++++++++++++++ + 2 files changed, 30 insertions(+) + create mode 100644 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts + +diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile +index 95889e7269d1..7e2b87702571 100644 +--- a/arch/riscv/boot/dts/spacemit/Makefile ++++ b/arch/riscv/boot/dts/spacemit/Makefile +@@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb ++dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +new file mode 100644 +index 000000000000..b691304d4b74 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ * Copyright (c) 2026 Guodong Xu ++ */ ++ ++#include "k3.dtsi" ++ ++/ { ++ model = "SpacemiT K3 Pico-ITX"; ++ compatible = "spacemit,k3-pico-itx", "spacemit,k3"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0"; ++ }; ++ ++ memory@100000000 { ++ device_type = "memory"; ++ reg = <0x1 0x00000000 0x4 0x00000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch b/SPECS/linux-lts/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch new file mode 100644 index 0000000000..ec9ea29ffd --- /dev/null +++ b/SPECS/linux-lts/0111-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch @@ -0,0 +1,53 @@ +From 2503ec0c2acbeba44796cf9a39cd65176b1b41b8 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 19 Dec 2025 09:28:18 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: Hide common clock driver from + user controller + +Since the common clock driver is only a dependency for other spacemit +clock driver, it should not be enabled individually, so hide this in +the Kconfig UI and let other spacemit clock driver select it. + +Signed-off-by: Inochi Amaoto +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20251219012819.440972-3-inochiama@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 99735a742f7e9a3e7f4cb6c58edf1b38101e7657) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/Kconfig | 14 ++++++-------- + 1 file changed, 6 insertions(+), 8 deletions(-) + +diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig +index 3854f6ae6d0e..3351e8bc801d 100644 +--- a/drivers/clk/spacemit/Kconfig ++++ b/drivers/clk/spacemit/Kconfig +@@ -1,19 +1,17 @@ + # SPDX-License-Identifier: GPL-2.0-only + +-config SPACEMIT_CCU +- tristate "Clock support for SpacemiT SoCs" ++menu "Clock support for SpacemiT platforms" + depends on ARCH_SPACEMIT || COMPILE_TEST ++ ++config SPACEMIT_CCU ++ tristate + select AUXILIARY_BUS + select MFD_SYSCON +- help +- Say Y to enable clock controller unit support for SpacemiT SoCs. +- +-if SPACEMIT_CCU + + config SPACEMIT_K1_CCU + tristate "Support for SpacemiT K1 SoC" +- depends on ARCH_SPACEMIT || COMPILE_TEST ++ select SPACEMIT_CCU + help + Support for clock controller unit in SpacemiT K1 SoC. + +-endif ++endmenu +-- +2.53.0 + diff --git a/SPECS/linux-lts/0111-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch b/SPECS/linux-lts/0111-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch deleted file mode 100644 index 38620c5098..0000000000 --- a/SPECS/linux-lts/0111-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch +++ /dev/null @@ -1,46 +0,0 @@ -From f7c8a235eb0f117b1a38380fced43d1f12ce6a90 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:44 +0800 -Subject: [PATCH 111/467] UPSTREAM: dt-bindings: riscv: spacemit: add K3 and - Pico-ITX board bindings - -Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX -which is a 2.5-inch single-board computer. - -Acked-by: Conor Dooley -Reviewed-by: Yixun Lan -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-5-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 7cb5fafc180f6e188af7943d6b162051f22490fc) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml -index c56b62a6299a..eca403a8e49e 100644 ---- a/Documentation/devicetree/bindings/riscv/spacemit.yaml -+++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml -@@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# - title: SpacemiT SoC-based boards - - maintainers: -+ - Guodong Xu - - Yangyu Chen - - Yixun Lan - -@@ -24,6 +25,10 @@ properties: - - milkv,jupiter - - xunlong,orangepi-rv2 - - const: spacemit,k1 -+ - items: -+ - enum: -+ - spacemit,k3-pico-itx -+ - const: spacemit,k3 - - additionalProperties: true - --- -2.53.0 - diff --git a/SPECS/linux-lts/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch b/SPECS/linux-lts/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch new file mode 100644 index 0000000000..02f0837e38 --- /dev/null +++ b/SPECS/linux-lts/0112-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch @@ -0,0 +1,73 @@ +From 5fd55e32b05d7b1c89471933925ea500ab96dc8f Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 19 Dec 2025 21:52:08 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: prepare common ccu header + +In order to prepare adding clock driver for new K3 SoC, extract generic +code to a separate common ccu header file, so they are not defined +in K1 SoC-specific file, and then can be shared by all clock drivers. + +Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-1-badf635993d3@gentoo.org +Reviewed-by: Alex Elder +Signed-off-by: Yixun Lan +(cherry picked from commit 2b7a02c322922a37cc5fc15d055b794cc2193062) +Signed-off-by: Han Gao +--- + include/soc/spacemit/ccu.h | 21 +++++++++++++++++++++ + include/soc/spacemit/k1-syscon.h | 12 +----------- + 2 files changed, 22 insertions(+), 11 deletions(-) + create mode 100644 include/soc/spacemit/ccu.h + +diff --git a/include/soc/spacemit/ccu.h b/include/soc/spacemit/ccu.h +new file mode 100644 +index 000000000000..84dcdecccc05 +--- /dev/null ++++ b/include/soc/spacemit/ccu.h +@@ -0,0 +1,21 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef __SOC_SPACEMIT_CCU_H__ ++#define __SOC_SPACEMIT_CCU_H__ ++ ++#include ++#include ++ ++/* Auxiliary device used to represent a CCU reset controller */ ++struct spacemit_ccu_adev { ++ struct auxiliary_device adev; ++ struct regmap *regmap; ++}; ++ ++static inline struct spacemit_ccu_adev * ++to_spacemit_ccu_adev(struct auxiliary_device *adev) ++{ ++ return container_of(adev, struct spacemit_ccu_adev, adev); ++} ++ ++#endif /* __SOC_SPACEMIT_CCU_H__ */ +diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-syscon.h +index 354751562c55..0be7a2e8d445 100644 +--- a/include/soc/spacemit/k1-syscon.h ++++ b/include/soc/spacemit/k1-syscon.h +@@ -5,17 +5,7 @@ + #ifndef __SOC_K1_SYSCON_H__ + #define __SOC_K1_SYSCON_H__ + +-/* Auxiliary device used to represent a CCU reset controller */ +-struct spacemit_ccu_adev { +- struct auxiliary_device adev; +- struct regmap *regmap; +-}; +- +-static inline struct spacemit_ccu_adev * +-to_spacemit_ccu_adev(struct auxiliary_device *adev) +-{ +- return container_of(adev, struct spacemit_ccu_adev, adev); +-} ++#include "ccu.h" + + /* APBS register offset */ + #define APBS_PLL1_SWCR1 0x100 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0112-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch b/SPECS/linux-lts/0112-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch deleted file mode 100644 index 238312a7d2..0000000000 --- a/SPECS/linux-lts/0112-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch +++ /dev/null @@ -1,608 +0,0 @@ -From fe51e7041e2aff1c2d9c8aa9847ccab8ca54a056 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:45 +0800 -Subject: [PATCH 112/467] UPSTREAM: riscv: dts: spacemit: add initial support - for K3 SoC - -SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant. -Add nodes of uarts, timer and interrupt-controllers. Also add M-mode -APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware -topology and ready for potential firmware usage. - -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-6-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 56f37e391a626f964615ee5939710eff212b621f) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 578 +++++++++++++++++++++++++++ - 1 file changed, 578 insertions(+) - create mode 100644 arch/riscv/boot/dts/spacemit/k3.dtsi - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -new file mode 100644 -index 000000000000..b69cf81b5d55 ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -0,0 +1,578 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd -+ * Copyright (c) 2026 Guodong Xu -+ */ -+ -+#include -+ -+/dts-v1/; -+ -+/ { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ model = "SpacemiT K3"; -+ compatible = "spacemit,k3"; -+ -+ cpus: cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ timebase-frequency = <24000000>; -+ -+ cpu_0: cpu@0 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <0>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache0>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu0_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_1: cpu@1 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <1>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache0>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu1_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_2: cpu@2 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <2>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache0>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu2_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_3: cpu@3 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <3>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache0>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu3_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_4: cpu@4 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <4>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache1>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu4_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_5: cpu@5 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <5>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache1>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu5_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_6: cpu@6 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <6>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache1>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu6_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ cpu_7: cpu@7 { -+ compatible = "spacemit,x100", "riscv"; -+ device_type = "cpu"; -+ reg = <7>; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", -+ "sha", "shcounterenw", "shgatpa", "shtvala", -+ "shvsatpa", "shvstvala", "shvstvecd", "smaia", -+ "smstateen", "ssaia", "ssccptr", "sscofpmf", -+ "sscounterenw", "ssnpm", "ssstateen", "sstc", -+ "sstvala", "sstvecd", "ssu64xl", "svade", -+ "svinval", "svnapot", "svpbmt", "za64rs", -+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca", -+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin", -+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", -+ "ziccamoa", "ziccif", "zicclsm", "zicntr", -+ "zicond", "zicsr", "zifencei", "zihintntl", -+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb", -+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", -+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", -+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", -+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <256>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <256>; -+ next-level-cache = <&l2_cache1>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu7_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ l2_cache0: cache-controller-0 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <4194304>; -+ cache-sets = <4096>; -+ cache-unified; -+ }; -+ -+ l2_cache1: cache-controller-1 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <4194304>; -+ cache-sets = <4096>; -+ cache-unified; -+ }; -+ -+ cpu-map { -+ cluster0 { -+ core0 { -+ cpu = <&cpu_0>; -+ }; -+ core1 { -+ cpu = <&cpu_1>; -+ }; -+ core2 { -+ cpu = <&cpu_2>; -+ }; -+ core3 { -+ cpu = <&cpu_3>; -+ }; -+ }; -+ -+ cluster1 { -+ core0 { -+ cpu = <&cpu_4>; -+ }; -+ core1 { -+ cpu = <&cpu_5>; -+ }; -+ core2 { -+ cpu = <&cpu_6>; -+ }; -+ core3 { -+ cpu = <&cpu_7>; -+ }; -+ }; -+ }; -+ }; -+ -+ soc: soc { -+ compatible = "simple-bus"; -+ interrupt-parent = <&saplic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ dma-noncoherent; -+ ranges; -+ -+ uart0: serial@d4017000 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017000 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@d4017100 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017100 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart3: serial@d4017200 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017200 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart4: serial@d4017300 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017300 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart5: serial@d4017400 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017400 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart6: serial@d4017500 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017500 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart7: serial@d4017600 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017600 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart8: serial@d4017700 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017700 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart9: serial@d4017800 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd4017800 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ uart10: serial@d401f000 { -+ compatible = "spacemit,k3-uart", "intel,xscale-uart"; -+ reg = <0x0 0xd401f000 0x0 0x100>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ clock-frequency = <14700000>; -+ interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ simsic: interrupt-controller@e0400000 { -+ compatible = "spacemit,k3-imsics", "riscv,imsics"; -+ reg = <0x0 0xe0400000 0x0 0x200000>; -+ #interrupt-cells = <0>; -+ #msi-cells = <0>; -+ interrupt-controller; -+ interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, -+ <&cpu2_intc 9>, <&cpu3_intc 9>, -+ <&cpu4_intc 9>, <&cpu5_intc 9>, -+ <&cpu6_intc 9>, <&cpu7_intc 9>; -+ msi-controller; -+ riscv,guest-index-bits = <6>; -+ riscv,hart-index-bits = <4>; -+ riscv,num-guest-ids = <511>; -+ riscv,num-ids = <511>; -+ }; -+ -+ saplic: interrupt-controller@e0804000 { -+ compatible = "spacemit,k3-aplic", "riscv,aplic"; -+ reg = <0x0 0xe0804000 0x0 0x4000>; -+ #interrupt-cells = <2>; -+ interrupt-controller; -+ msi-parent = <&simsic>; -+ riscv,num-sources = <512>; -+ }; -+ -+ clint: timer@e081c000 { -+ compatible = "spacemit,k3-clint", "sifive,clint0"; -+ reg = <0x0 0xe081c000 0x0 0x4000>; -+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, -+ <&cpu1_intc 3>, <&cpu1_intc 7>, -+ <&cpu2_intc 3>, <&cpu2_intc 7>, -+ <&cpu3_intc 3>, <&cpu3_intc 7>, -+ <&cpu4_intc 3>, <&cpu4_intc 7>, -+ <&cpu5_intc 3>, <&cpu5_intc 7>, -+ <&cpu6_intc 3>, <&cpu6_intc 7>, -+ <&cpu7_intc 3>, <&cpu7_intc 7>; -+ }; -+ -+ mimsic: interrupt-controller@f1000000 { -+ compatible = "spacemit,k3-imsics", "riscv,imsics"; -+ reg = <0x0 0xf1000000 0x0 0x10000>; -+ #interrupt-cells = <0>; -+ #msi-cells = <0>; -+ interrupt-controller; -+ interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, -+ <&cpu2_intc 11>, <&cpu3_intc 11>, -+ <&cpu4_intc 11>, <&cpu5_intc 11>, -+ <&cpu6_intc 11>, <&cpu7_intc 11>; -+ msi-controller; -+ riscv,guest-index-bits = <6>; -+ riscv,hart-index-bits = <4>; -+ riscv,num-guest-ids = <511>; -+ riscv,num-ids = <511>; -+ status = "reserved"; -+ }; -+ -+ maplic: interrupt-controller@f1800000 { -+ compatible = "spacemit,k3-aplic", "riscv,aplic"; -+ reg = <0x0 0xf1800000 0x0 0x4000>; -+ #interrupt-cells = <2>; -+ interrupt-controller; -+ msi-parent = <&mimsic>; -+ riscv,children = <&saplic>; -+ riscv,delegation = <&saplic 1 512>; -+ riscv,num-sources = <512>; -+ status = "reserved"; -+ }; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch b/SPECS/linux-lts/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch new file mode 100644 index 0000000000..07bf26b3d3 --- /dev/null +++ b/SPECS/linux-lts/0113-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch @@ -0,0 +1,463 @@ +From 882ae01390f0d71acbaa666ad62660f1690558cb Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 19 Dec 2025 08:07:23 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: extract common ccu functions + +Refactor the probe function of SpacemiT's clock, and extract a common ccu +file, so new clock driver added in the future can share the same code, +which would lower the burden of maintenance. Since this commit changes the +module name from spacemit_ccu_k1 to spacemit_ccu where the auxiliary device +registered, the auxiliary device id need to be adjusted. Idea of the patch +comes from the review of K3 clock driver, please refer to this disucssion[1] +for more detail. + +This change will introduce a runtime break to reset driver, and will be +fixed in follow-up commit: +ecff77f7c041 ("reset: spacemit: fix auxiliary device id") + +Link: https://lore.kernel.org/all/aTo8sCPpVM1o9PKX@pie/ [1] +Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-2-badf635993d3@gentoo.org +Suggested-by: Yao Zi +Reviewed-by: Alex Elder +Signed-off-by: Yixun Lan +(cherry picked from commit 99669468d24ce21be12f3751e7381c47ab2c9ecd) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k1.c | 179 +----------------------------- + drivers/clk/spacemit/ccu_common.c | 171 ++++++++++++++++++++++++++++ + drivers/clk/spacemit/ccu_common.h | 10 ++ + 3 files changed, 186 insertions(+), 174 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c +index 01d9485b615d..02c792a73759 100644 +--- a/drivers/clk/spacemit/ccu-k1.c ++++ b/drivers/clk/spacemit/ccu-k1.c +@@ -5,15 +5,10 @@ + */ + + #include +-#include + #include +-#include +-#include +-#include + #include + #include + #include +-#include + #include + + #include "ccu_common.h" +@@ -23,14 +18,6 @@ + + #include + +-struct spacemit_ccu_data { +- const char *reset_name; +- struct clk_hw **hws; +- size_t num; +-}; +- +-static DEFINE_IDA(auxiliary_ids); +- + /* APBS clocks start, APBS region contains and only contains all PLL clocks */ + + /* +@@ -1001,167 +988,6 @@ static const struct spacemit_ccu_data k1_ccu_apbc2_data = { + .reset_name = "apbc2-reset", + }; + +-static int spacemit_ccu_register(struct device *dev, +- struct regmap *regmap, +- struct regmap *lock_regmap, +- const struct spacemit_ccu_data *data) +-{ +- struct clk_hw_onecell_data *clk_data; +- int i, ret; +- +- /* Nothing to do if the CCU does not implement any clocks */ +- if (!data->hws) +- return 0; +- +- clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), +- GFP_KERNEL); +- if (!clk_data) +- return -ENOMEM; +- +- clk_data->num = data->num; +- +- for (i = 0; i < data->num; i++) { +- struct clk_hw *hw = data->hws[i]; +- struct ccu_common *common; +- const char *name; +- +- if (!hw) { +- clk_data->hws[i] = ERR_PTR(-ENOENT); +- continue; +- } +- +- name = hw->init->name; +- +- common = hw_to_ccu_common(hw); +- common->regmap = regmap; +- common->lock_regmap = lock_regmap; +- +- ret = devm_clk_hw_register(dev, hw); +- if (ret) { +- dev_err(dev, "Cannot register clock %d - %s\n", +- i, name); +- return ret; +- } +- +- clk_data->hws[i] = hw; +- } +- +- ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); +- if (ret) +- dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); +- +- return ret; +-} +- +-static void spacemit_cadev_release(struct device *dev) +-{ +- struct auxiliary_device *adev = to_auxiliary_dev(dev); +- +- ida_free(&auxiliary_ids, adev->id); +- kfree(to_spacemit_ccu_adev(adev)); +-} +- +-static void spacemit_adev_unregister(void *data) +-{ +- struct auxiliary_device *adev = data; +- +- auxiliary_device_delete(adev); +- auxiliary_device_uninit(adev); +-} +- +-static int spacemit_ccu_reset_register(struct device *dev, +- struct regmap *regmap, +- const char *reset_name) +-{ +- struct spacemit_ccu_adev *cadev; +- struct auxiliary_device *adev; +- int ret; +- +- /* Nothing to do if the CCU does not implement a reset controller */ +- if (!reset_name) +- return 0; +- +- cadev = kzalloc(sizeof(*cadev), GFP_KERNEL); +- if (!cadev) +- return -ENOMEM; +- +- cadev->regmap = regmap; +- +- adev = &cadev->adev; +- adev->name = reset_name; +- adev->dev.parent = dev; +- adev->dev.release = spacemit_cadev_release; +- adev->dev.of_node = dev->of_node; +- ret = ida_alloc(&auxiliary_ids, GFP_KERNEL); +- if (ret < 0) +- goto err_free_cadev; +- adev->id = ret; +- +- ret = auxiliary_device_init(adev); +- if (ret) +- goto err_free_aux_id; +- +- ret = auxiliary_device_add(adev); +- if (ret) { +- auxiliary_device_uninit(adev); +- return ret; +- } +- +- return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); +- +-err_free_aux_id: +- ida_free(&auxiliary_ids, adev->id); +-err_free_cadev: +- kfree(cadev); +- +- return ret; +-} +- +-static int k1_ccu_probe(struct platform_device *pdev) +-{ +- struct regmap *base_regmap, *lock_regmap = NULL; +- const struct spacemit_ccu_data *data; +- struct device *dev = &pdev->dev; +- int ret; +- +- base_regmap = device_node_to_regmap(dev->of_node); +- if (IS_ERR(base_regmap)) +- return dev_err_probe(dev, PTR_ERR(base_regmap), +- "failed to get regmap\n"); +- +- /* +- * The lock status of PLLs locate in MPMU region, while PLLs themselves +- * are in APBS region. Reference to MPMU syscon is required to check PLL +- * status. +- */ +- if (of_device_is_compatible(dev->of_node, "spacemit,k1-pll")) { +- struct device_node *mpmu = of_parse_phandle(dev->of_node, +- "spacemit,mpmu", 0); +- if (!mpmu) +- return dev_err_probe(dev, -ENODEV, +- "Cannot parse MPMU region\n"); +- +- lock_regmap = device_node_to_regmap(mpmu); +- of_node_put(mpmu); +- +- if (IS_ERR(lock_regmap)) +- return dev_err_probe(dev, PTR_ERR(lock_regmap), +- "failed to get lock regmap\n"); +- } +- +- data = of_device_get_match_data(dev); +- +- ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); +- if (ret) +- return dev_err_probe(dev, ret, "failed to register clocks\n"); +- +- ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); +- if (ret) +- return dev_err_probe(dev, ret, "failed to register resets\n"); +- +- return 0; +-} +- + static const struct of_device_id of_k1_ccu_match[] = { + { + .compatible = "spacemit,k1-pll", +@@ -1195,6 +1021,11 @@ static const struct of_device_id of_k1_ccu_match[] = { + }; + MODULE_DEVICE_TABLE(of, of_k1_ccu_match); + ++static int k1_ccu_probe(struct platform_device *pdev) ++{ ++ return spacemit_ccu_probe(pdev, "spacemit,k1-pll"); ++} ++ + static struct platform_driver k1_ccu_driver = { + .driver = { + .name = "spacemit,k1-ccu", +diff --git a/drivers/clk/spacemit/ccu_common.c b/drivers/clk/spacemit/ccu_common.c +index 4412c4104dab..5f05b17f8452 100644 +--- a/drivers/clk/spacemit/ccu_common.c ++++ b/drivers/clk/spacemit/ccu_common.c +@@ -1,6 +1,177 @@ + // SPDX-License-Identifier: GPL-2.0-only + ++#include ++#include ++#include + #include ++#include ++#include ++#include ++ ++#include "ccu_common.h" ++ ++static DEFINE_IDA(auxiliary_ids); ++static int spacemit_ccu_register(struct device *dev, ++ struct regmap *regmap, ++ struct regmap *lock_regmap, ++ const struct spacemit_ccu_data *data) ++{ ++ struct clk_hw_onecell_data *clk_data; ++ int i, ret; ++ ++ /* Nothing to do if the CCU does not implement any clocks */ ++ if (!data->hws) ++ return 0; ++ ++ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), ++ GFP_KERNEL); ++ if (!clk_data) ++ return -ENOMEM; ++ ++ clk_data->num = data->num; ++ ++ for (i = 0; i < data->num; i++) { ++ struct clk_hw *hw = data->hws[i]; ++ struct ccu_common *common; ++ const char *name; ++ ++ if (!hw) { ++ clk_data->hws[i] = ERR_PTR(-ENOENT); ++ continue; ++ } ++ ++ name = hw->init->name; ++ ++ common = hw_to_ccu_common(hw); ++ common->regmap = regmap; ++ common->lock_regmap = lock_regmap; ++ ++ ret = devm_clk_hw_register(dev, hw); ++ if (ret) { ++ dev_err(dev, "Cannot register clock %d - %s\n", ++ i, name); ++ return ret; ++ } ++ ++ clk_data->hws[i] = hw; ++ } ++ ++ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); ++ if (ret) ++ dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); ++ ++ return ret; ++} ++ ++static void spacemit_cadev_release(struct device *dev) ++{ ++ struct auxiliary_device *adev = to_auxiliary_dev(dev); ++ ++ ida_free(&auxiliary_ids, adev->id); ++ kfree(to_spacemit_ccu_adev(adev)); ++} ++ ++static void spacemit_adev_unregister(void *data) ++{ ++ struct auxiliary_device *adev = data; ++ ++ auxiliary_device_delete(adev); ++ auxiliary_device_uninit(adev); ++} ++ ++static int spacemit_ccu_reset_register(struct device *dev, ++ struct regmap *regmap, ++ const char *reset_name) ++{ ++ struct spacemit_ccu_adev *cadev; ++ struct auxiliary_device *adev; ++ int ret; ++ ++ /* Nothing to do if the CCU does not implement a reset controller */ ++ if (!reset_name) ++ return 0; ++ ++ cadev = kzalloc(sizeof(*cadev), GFP_KERNEL); ++ if (!cadev) ++ return -ENOMEM; ++ ++ cadev->regmap = regmap; ++ ++ adev = &cadev->adev; ++ adev->name = reset_name; ++ adev->dev.parent = dev; ++ adev->dev.release = spacemit_cadev_release; ++ adev->dev.of_node = dev->of_node; ++ ret = ida_alloc(&auxiliary_ids, GFP_KERNEL); ++ if (ret < 0) ++ goto err_free_cadev; ++ adev->id = ret; ++ ++ ret = auxiliary_device_init(adev); ++ if (ret) ++ goto err_free_aux_id; ++ ++ ret = auxiliary_device_add(adev); ++ if (ret) { ++ auxiliary_device_uninit(adev); ++ return ret; ++ } ++ ++ return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); ++ ++err_free_aux_id: ++ ida_free(&auxiliary_ids, adev->id); ++err_free_cadev: ++ kfree(cadev); ++ ++ return ret; ++} ++ ++int spacemit_ccu_probe(struct platform_device *pdev, const char *compat) ++{ ++ struct regmap *base_regmap, *lock_regmap = NULL; ++ const struct spacemit_ccu_data *data; ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ base_regmap = device_node_to_regmap(dev->of_node); ++ if (IS_ERR(base_regmap)) ++ return dev_err_probe(dev, PTR_ERR(base_regmap), ++ "failed to get regmap\n"); ++ ++ /* ++ * The lock status of PLLs locate in MPMU region, while PLLs themselves ++ * are in APBS region. Reference to MPMU syscon is required to check PLL ++ * status. ++ */ ++ if (compat && of_device_is_compatible(dev->of_node, compat)) { ++ struct device_node *mpmu = of_parse_phandle(dev->of_node, ++ "spacemit,mpmu", 0); ++ if (!mpmu) ++ return dev_err_probe(dev, -ENODEV, ++ "Cannot parse MPMU region\n"); ++ ++ lock_regmap = device_node_to_regmap(mpmu); ++ of_node_put(mpmu); ++ ++ if (IS_ERR(lock_regmap)) ++ return dev_err_probe(dev, PTR_ERR(lock_regmap), ++ "failed to get lock regmap\n"); ++ } ++ ++ data = of_device_get_match_data(dev); ++ ++ ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to register clocks\n"); ++ ++ ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to register resets\n"); ++ ++ return 0; ++} ++EXPORT_SYMBOL_NS_GPL(spacemit_ccu_probe, "CLK_SPACEMIT"); + + MODULE_DESCRIPTION("SpacemiT CCU common clock driver"); + MODULE_LICENSE("GPL"); +diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h +index da72f3836e0b..7ae244b5eace 100644 +--- a/drivers/clk/spacemit/ccu_common.h ++++ b/drivers/clk/spacemit/ccu_common.h +@@ -7,6 +7,8 @@ + #ifndef _CCU_COMMON_H_ + #define _CCU_COMMON_H_ + ++#include ++#include + #include + + struct ccu_common { +@@ -36,6 +38,12 @@ static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) + return container_of(hw, struct ccu_common, hw); + } + ++struct spacemit_ccu_data { ++ const char *reset_name; ++ struct clk_hw **hws; ++ size_t num; ++}; ++ + #define ccu_read(c, reg) \ + ({ \ + u32 tmp; \ +@@ -45,4 +53,6 @@ static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) + #define ccu_update(c, reg, mask, val) \ + regmap_update_bits((c)->regmap, (c)->reg_##reg, mask, val) + ++int spacemit_ccu_probe(struct platform_device *pdev, const char *compat); ++ + #endif /* _CCU_COMMON_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0113-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch b/SPECS/linux-lts/0113-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch deleted file mode 100644 index b8abaeb4f2..0000000000 --- a/SPECS/linux-lts/0113-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch +++ /dev/null @@ -1,70 +0,0 @@ -From fcd998b46e6d0b3681c7f4192cb27b126e034191 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Thu, 15 Jan 2026 14:51:46 +0800 -Subject: [PATCH 113/467] UPSTREAM: riscv: dts: spacemit: add K3 Pico-ITX board - support - -K3 Pico-ITX is a 2.5-inch single-board computer equipted with a SpacemiT -K3 SoC. - -This minimal device tree enables booting into a serial console with UART -output. - -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-7-6990ac9f4308@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 7a61318049861b777f098d7148d892d7dc79b010) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/Makefile | 1 + - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++++++++++++++++++ - 2 files changed, 30 insertions(+) - create mode 100644 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts - -diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile -index 95889e7269d1..7e2b87702571 100644 ---- a/arch/riscv/boot/dts/spacemit/Makefile -+++ b/arch/riscv/boot/dts/spacemit/Makefile -@@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb -+dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -new file mode 100644 -index 000000000000..b691304d4b74 ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd -+ * Copyright (c) 2026 Guodong Xu -+ */ -+ -+#include "k3.dtsi" -+ -+/ { -+ model = "SpacemiT K3 Pico-ITX"; -+ compatible = "spacemit,k3-pico-itx", "spacemit,k3"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0"; -+ }; -+ -+ memory@100000000 { -+ device_type = "memory"; -+ reg = <0x1 0x00000000 0x4 0x00000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0114-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch b/SPECS/linux-lts/0114-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch deleted file mode 100644 index ec4fc1255f..0000000000 --- a/SPECS/linux-lts/0114-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 0e02ccc906b37757be6723a81e0e8d49131246c6 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 19 Dec 2025 09:28:18 +0800 -Subject: [PATCH 114/467] UPSTREAM: clk: spacemit: Hide common clock driver - from user controller - -Since the common clock driver is only a dependency for other spacemit -clock driver, it should not be enabled individually, so hide this in -the Kconfig UI and let other spacemit clock driver select it. - -Signed-off-by: Inochi Amaoto -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20251219012819.440972-3-inochiama@gmail.com -Signed-off-by: Yixun Lan -(cherry picked from commit 99735a742f7e9a3e7f4cb6c58edf1b38101e7657) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/Kconfig | 14 ++++++-------- - 1 file changed, 6 insertions(+), 8 deletions(-) - -diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig -index 3854f6ae6d0e..3351e8bc801d 100644 ---- a/drivers/clk/spacemit/Kconfig -+++ b/drivers/clk/spacemit/Kconfig -@@ -1,19 +1,17 @@ - # SPDX-License-Identifier: GPL-2.0-only - --config SPACEMIT_CCU -- tristate "Clock support for SpacemiT SoCs" -+menu "Clock support for SpacemiT platforms" - depends on ARCH_SPACEMIT || COMPILE_TEST -+ -+config SPACEMIT_CCU -+ tristate - select AUXILIARY_BUS - select MFD_SYSCON -- help -- Say Y to enable clock controller unit support for SpacemiT SoCs. -- --if SPACEMIT_CCU - - config SPACEMIT_K1_CCU - tristate "Support for SpacemiT K1 SoC" -- depends on ARCH_SPACEMIT || COMPILE_TEST -+ select SPACEMIT_CCU - help - Support for clock controller unit in SpacemiT K1 SoC. - --endif -+endmenu --- -2.53.0 - diff --git a/SPECS/linux-lts/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch b/SPECS/linux-lts/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch new file mode 100644 index 0000000000..195fb33162 --- /dev/null +++ b/SPECS/linux-lts/0114-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch @@ -0,0 +1,79 @@ +From 597e2f7d18294ec1b59dc52d5be6ac61f4ef6075 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Sat, 3 Jan 2026 14:14:36 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: add platform SoC prefix to + reset name + +This change is needed for adding future new SpacemiT K3 reset driver. + +Since both K1 and K3 reset code register via the same module which its +name changed to spacemit_ccu, it's necessary to encode the platform/SoC +in the reset auxiliary device name to distinguish them, otherwise two +reset drivers will claim to support same "compatible" auxiliary device +even in the case of only one CCU clock driver got registered, which in +the end lead to a broken reset driver. + +This change will introduce a runtime break to reset driver, and will be +fixed in follow-up commit: +ecff77f7c041 ("reset: spacemit: fix auxiliary device id") + +Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-3-badf635993d3@gentoo.org +Reviewed-by: Alex Elder +Signed-off-by: Yixun Lan +(cherry picked from commit 0664a46f93e2fb2f75fa05b5f08949600cce88f9) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k1.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c +index 02c792a73759..dee14d25f75d 100644 +--- a/drivers/clk/spacemit/ccu-k1.c ++++ b/drivers/clk/spacemit/ccu-k1.c +@@ -789,7 +789,7 @@ static struct clk_hw *k1_ccu_mpmu_hws[] = { + }; + + static const struct spacemit_ccu_data k1_ccu_mpmu_data = { +- .reset_name = "mpmu-reset", ++ .reset_name = "k1-mpmu-reset", + .hws = k1_ccu_mpmu_hws, + .num = ARRAY_SIZE(k1_ccu_mpmu_hws), + }; +@@ -900,7 +900,7 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { + }; + + static const struct spacemit_ccu_data k1_ccu_apbc_data = { +- .reset_name = "apbc-reset", ++ .reset_name = "k1-apbc-reset", + .hws = k1_ccu_apbc_hws, + .num = ARRAY_SIZE(k1_ccu_apbc_hws), + }; +@@ -971,21 +971,21 @@ static struct clk_hw *k1_ccu_apmu_hws[] = { + }; + + static const struct spacemit_ccu_data k1_ccu_apmu_data = { +- .reset_name = "apmu-reset", ++ .reset_name = "k1-apmu-reset", + .hws = k1_ccu_apmu_hws, + .num = ARRAY_SIZE(k1_ccu_apmu_hws), + }; + + static const struct spacemit_ccu_data k1_ccu_rcpu_data = { +- .reset_name = "rcpu-reset", ++ .reset_name = "k1-rcpu-reset", + }; + + static const struct spacemit_ccu_data k1_ccu_rcpu2_data = { +- .reset_name = "rcpu2-reset", ++ .reset_name = "k1-rcpu2-reset", + }; + + static const struct spacemit_ccu_data k1_ccu_apbc2_data = { +- .reset_name = "apbc2-reset", ++ .reset_name = "k1-apbc2-reset", + }; + + static const struct of_device_id of_k1_ccu_match[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0115-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch b/SPECS/linux-lts/0115-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch deleted file mode 100644 index 8a5722dcf6..0000000000 --- a/SPECS/linux-lts/0115-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 771281a6b5e7596444e45eefb3739c0fdc34a300 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 19 Dec 2025 21:52:08 +0800 -Subject: [PATCH 115/467] UPSTREAM: clk: spacemit: prepare common ccu header - -In order to prepare adding clock driver for new K3 SoC, extract generic -code to a separate common ccu header file, so they are not defined -in K1 SoC-specific file, and then can be shared by all clock drivers. - -Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-1-badf635993d3@gentoo.org -Reviewed-by: Alex Elder -Signed-off-by: Yixun Lan -(cherry picked from commit 2b7a02c322922a37cc5fc15d055b794cc2193062) -Signed-off-by: Han Gao ---- - include/soc/spacemit/ccu.h | 21 +++++++++++++++++++++ - include/soc/spacemit/k1-syscon.h | 12 +----------- - 2 files changed, 22 insertions(+), 11 deletions(-) - create mode 100644 include/soc/spacemit/ccu.h - -diff --git a/include/soc/spacemit/ccu.h b/include/soc/spacemit/ccu.h -new file mode 100644 -index 000000000000..84dcdecccc05 ---- /dev/null -+++ b/include/soc/spacemit/ccu.h -@@ -0,0 +1,21 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef __SOC_SPACEMIT_CCU_H__ -+#define __SOC_SPACEMIT_CCU_H__ -+ -+#include -+#include -+ -+/* Auxiliary device used to represent a CCU reset controller */ -+struct spacemit_ccu_adev { -+ struct auxiliary_device adev; -+ struct regmap *regmap; -+}; -+ -+static inline struct spacemit_ccu_adev * -+to_spacemit_ccu_adev(struct auxiliary_device *adev) -+{ -+ return container_of(adev, struct spacemit_ccu_adev, adev); -+} -+ -+#endif /* __SOC_SPACEMIT_CCU_H__ */ -diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-syscon.h -index 354751562c55..0be7a2e8d445 100644 ---- a/include/soc/spacemit/k1-syscon.h -+++ b/include/soc/spacemit/k1-syscon.h -@@ -5,17 +5,7 @@ - #ifndef __SOC_K1_SYSCON_H__ - #define __SOC_K1_SYSCON_H__ - --/* Auxiliary device used to represent a CCU reset controller */ --struct spacemit_ccu_adev { -- struct auxiliary_device adev; -- struct regmap *regmap; --}; -- --static inline struct spacemit_ccu_adev * --to_spacemit_ccu_adev(struct auxiliary_device *adev) --{ -- return container_of(adev, struct spacemit_ccu_adev, adev); --} -+#include "ccu.h" - - /* APBS register offset */ - #define APBS_PLL1_SWCR1 0x100 --- -2.53.0 - diff --git a/SPECS/linux-lts/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch b/SPECS/linux-lts/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch new file mode 100644 index 0000000000..1bbdfdf4b9 --- /dev/null +++ b/SPECS/linux-lts/0115-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch @@ -0,0 +1,43 @@ +From 195ce637ead66f8aff72ecf491637b937ab32985 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 19 Dec 2025 05:34:39 +0800 +Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: fix auxiliary device id + +Due to the auxiliary register procedure moved to ccu common module where +the module name changed to spacemit_ccu, then the reset auxiliary device +register id also need to be adjusted in order to prepare for adding new +K3 reset driver, otherwise two reset drivers will claim to support same +"compatible" auxiliary device. + +In order to prevent the reset driver breakage, this commit is necessary +as a post-fix for changes introduced by two patches below, and should be +merged with them to make the patch series runtime bisectable. +("clk: spacemit: add platform SoC prefix to reset name") +("clk: spacemit: extract common ccu functions") + +Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-4-badf635993d3@gentoo.org +Acked-by: Philipp Zabel +Reviewed-by: Alex Elder +Signed-off-by: Yixun Lan +(cherry picked from commit ecff77f7c04141cc18ee2482936c96117060c0f2) +Signed-off-by: Han Gao +--- + drivers/reset/reset-spacemit.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/reset-spacemit.c +index e1272aff28f7..cc7fd1f8750d 100644 +--- a/drivers/reset/reset-spacemit.c ++++ b/drivers/reset/reset-spacemit.c +@@ -278,7 +278,7 @@ static int spacemit_reset_probe(struct auxiliary_device *adev, + + #define K1_AUX_DEV_ID(_unit) \ + { \ +- .name = "spacemit_ccu_k1." #_unit "-reset", \ ++ .name = "spacemit_ccu.k1-" #_unit "-reset", \ + .driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0116-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch b/SPECS/linux-lts/0116-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch deleted file mode 100644 index 1d0ba908ed..0000000000 --- a/SPECS/linux-lts/0116-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch +++ /dev/null @@ -1,463 +0,0 @@ -From 4884ecab8b7bfb72589924db174968f01edb5910 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 19 Dec 2025 08:07:23 +0800 -Subject: [PATCH 116/467] UPSTREAM: clk: spacemit: extract common ccu functions - -Refactor the probe function of SpacemiT's clock, and extract a common ccu -file, so new clock driver added in the future can share the same code, -which would lower the burden of maintenance. Since this commit changes the -module name from spacemit_ccu_k1 to spacemit_ccu where the auxiliary device -registered, the auxiliary device id need to be adjusted. Idea of the patch -comes from the review of K3 clock driver, please refer to this disucssion[1] -for more detail. - -This change will introduce a runtime break to reset driver, and will be -fixed in follow-up commit: -ecff77f7c041 ("reset: spacemit: fix auxiliary device id") - -Link: https://lore.kernel.org/all/aTo8sCPpVM1o9PKX@pie/ [1] -Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-2-badf635993d3@gentoo.org -Suggested-by: Yao Zi -Reviewed-by: Alex Elder -Signed-off-by: Yixun Lan -(cherry picked from commit 99669468d24ce21be12f3751e7381c47ab2c9ecd) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k1.c | 179 +----------------------------- - drivers/clk/spacemit/ccu_common.c | 171 ++++++++++++++++++++++++++++ - drivers/clk/spacemit/ccu_common.h | 10 ++ - 3 files changed, 186 insertions(+), 174 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c -index 01d9485b615d..02c792a73759 100644 ---- a/drivers/clk/spacemit/ccu-k1.c -+++ b/drivers/clk/spacemit/ccu-k1.c -@@ -5,15 +5,10 @@ - */ - - #include --#include - #include --#include --#include --#include - #include - #include - #include --#include - #include - - #include "ccu_common.h" -@@ -23,14 +18,6 @@ - - #include - --struct spacemit_ccu_data { -- const char *reset_name; -- struct clk_hw **hws; -- size_t num; --}; -- --static DEFINE_IDA(auxiliary_ids); -- - /* APBS clocks start, APBS region contains and only contains all PLL clocks */ - - /* -@@ -1001,167 +988,6 @@ static const struct spacemit_ccu_data k1_ccu_apbc2_data = { - .reset_name = "apbc2-reset", - }; - --static int spacemit_ccu_register(struct device *dev, -- struct regmap *regmap, -- struct regmap *lock_regmap, -- const struct spacemit_ccu_data *data) --{ -- struct clk_hw_onecell_data *clk_data; -- int i, ret; -- -- /* Nothing to do if the CCU does not implement any clocks */ -- if (!data->hws) -- return 0; -- -- clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), -- GFP_KERNEL); -- if (!clk_data) -- return -ENOMEM; -- -- clk_data->num = data->num; -- -- for (i = 0; i < data->num; i++) { -- struct clk_hw *hw = data->hws[i]; -- struct ccu_common *common; -- const char *name; -- -- if (!hw) { -- clk_data->hws[i] = ERR_PTR(-ENOENT); -- continue; -- } -- -- name = hw->init->name; -- -- common = hw_to_ccu_common(hw); -- common->regmap = regmap; -- common->lock_regmap = lock_regmap; -- -- ret = devm_clk_hw_register(dev, hw); -- if (ret) { -- dev_err(dev, "Cannot register clock %d - %s\n", -- i, name); -- return ret; -- } -- -- clk_data->hws[i] = hw; -- } -- -- ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); -- if (ret) -- dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); -- -- return ret; --} -- --static void spacemit_cadev_release(struct device *dev) --{ -- struct auxiliary_device *adev = to_auxiliary_dev(dev); -- -- ida_free(&auxiliary_ids, adev->id); -- kfree(to_spacemit_ccu_adev(adev)); --} -- --static void spacemit_adev_unregister(void *data) --{ -- struct auxiliary_device *adev = data; -- -- auxiliary_device_delete(adev); -- auxiliary_device_uninit(adev); --} -- --static int spacemit_ccu_reset_register(struct device *dev, -- struct regmap *regmap, -- const char *reset_name) --{ -- struct spacemit_ccu_adev *cadev; -- struct auxiliary_device *adev; -- int ret; -- -- /* Nothing to do if the CCU does not implement a reset controller */ -- if (!reset_name) -- return 0; -- -- cadev = kzalloc(sizeof(*cadev), GFP_KERNEL); -- if (!cadev) -- return -ENOMEM; -- -- cadev->regmap = regmap; -- -- adev = &cadev->adev; -- adev->name = reset_name; -- adev->dev.parent = dev; -- adev->dev.release = spacemit_cadev_release; -- adev->dev.of_node = dev->of_node; -- ret = ida_alloc(&auxiliary_ids, GFP_KERNEL); -- if (ret < 0) -- goto err_free_cadev; -- adev->id = ret; -- -- ret = auxiliary_device_init(adev); -- if (ret) -- goto err_free_aux_id; -- -- ret = auxiliary_device_add(adev); -- if (ret) { -- auxiliary_device_uninit(adev); -- return ret; -- } -- -- return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); -- --err_free_aux_id: -- ida_free(&auxiliary_ids, adev->id); --err_free_cadev: -- kfree(cadev); -- -- return ret; --} -- --static int k1_ccu_probe(struct platform_device *pdev) --{ -- struct regmap *base_regmap, *lock_regmap = NULL; -- const struct spacemit_ccu_data *data; -- struct device *dev = &pdev->dev; -- int ret; -- -- base_regmap = device_node_to_regmap(dev->of_node); -- if (IS_ERR(base_regmap)) -- return dev_err_probe(dev, PTR_ERR(base_regmap), -- "failed to get regmap\n"); -- -- /* -- * The lock status of PLLs locate in MPMU region, while PLLs themselves -- * are in APBS region. Reference to MPMU syscon is required to check PLL -- * status. -- */ -- if (of_device_is_compatible(dev->of_node, "spacemit,k1-pll")) { -- struct device_node *mpmu = of_parse_phandle(dev->of_node, -- "spacemit,mpmu", 0); -- if (!mpmu) -- return dev_err_probe(dev, -ENODEV, -- "Cannot parse MPMU region\n"); -- -- lock_regmap = device_node_to_regmap(mpmu); -- of_node_put(mpmu); -- -- if (IS_ERR(lock_regmap)) -- return dev_err_probe(dev, PTR_ERR(lock_regmap), -- "failed to get lock regmap\n"); -- } -- -- data = of_device_get_match_data(dev); -- -- ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); -- if (ret) -- return dev_err_probe(dev, ret, "failed to register clocks\n"); -- -- ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); -- if (ret) -- return dev_err_probe(dev, ret, "failed to register resets\n"); -- -- return 0; --} -- - static const struct of_device_id of_k1_ccu_match[] = { - { - .compatible = "spacemit,k1-pll", -@@ -1195,6 +1021,11 @@ static const struct of_device_id of_k1_ccu_match[] = { - }; - MODULE_DEVICE_TABLE(of, of_k1_ccu_match); - -+static int k1_ccu_probe(struct platform_device *pdev) -+{ -+ return spacemit_ccu_probe(pdev, "spacemit,k1-pll"); -+} -+ - static struct platform_driver k1_ccu_driver = { - .driver = { - .name = "spacemit,k1-ccu", -diff --git a/drivers/clk/spacemit/ccu_common.c b/drivers/clk/spacemit/ccu_common.c -index 4412c4104dab..5f05b17f8452 100644 ---- a/drivers/clk/spacemit/ccu_common.c -+++ b/drivers/clk/spacemit/ccu_common.c -@@ -1,6 +1,177 @@ - // SPDX-License-Identifier: GPL-2.0-only - -+#include -+#include -+#include - #include -+#include -+#include -+#include -+ -+#include "ccu_common.h" -+ -+static DEFINE_IDA(auxiliary_ids); -+static int spacemit_ccu_register(struct device *dev, -+ struct regmap *regmap, -+ struct regmap *lock_regmap, -+ const struct spacemit_ccu_data *data) -+{ -+ struct clk_hw_onecell_data *clk_data; -+ int i, ret; -+ -+ /* Nothing to do if the CCU does not implement any clocks */ -+ if (!data->hws) -+ return 0; -+ -+ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), -+ GFP_KERNEL); -+ if (!clk_data) -+ return -ENOMEM; -+ -+ clk_data->num = data->num; -+ -+ for (i = 0; i < data->num; i++) { -+ struct clk_hw *hw = data->hws[i]; -+ struct ccu_common *common; -+ const char *name; -+ -+ if (!hw) { -+ clk_data->hws[i] = ERR_PTR(-ENOENT); -+ continue; -+ } -+ -+ name = hw->init->name; -+ -+ common = hw_to_ccu_common(hw); -+ common->regmap = regmap; -+ common->lock_regmap = lock_regmap; -+ -+ ret = devm_clk_hw_register(dev, hw); -+ if (ret) { -+ dev_err(dev, "Cannot register clock %d - %s\n", -+ i, name); -+ return ret; -+ } -+ -+ clk_data->hws[i] = hw; -+ } -+ -+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); -+ if (ret) -+ dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); -+ -+ return ret; -+} -+ -+static void spacemit_cadev_release(struct device *dev) -+{ -+ struct auxiliary_device *adev = to_auxiliary_dev(dev); -+ -+ ida_free(&auxiliary_ids, adev->id); -+ kfree(to_spacemit_ccu_adev(adev)); -+} -+ -+static void spacemit_adev_unregister(void *data) -+{ -+ struct auxiliary_device *adev = data; -+ -+ auxiliary_device_delete(adev); -+ auxiliary_device_uninit(adev); -+} -+ -+static int spacemit_ccu_reset_register(struct device *dev, -+ struct regmap *regmap, -+ const char *reset_name) -+{ -+ struct spacemit_ccu_adev *cadev; -+ struct auxiliary_device *adev; -+ int ret; -+ -+ /* Nothing to do if the CCU does not implement a reset controller */ -+ if (!reset_name) -+ return 0; -+ -+ cadev = kzalloc(sizeof(*cadev), GFP_KERNEL); -+ if (!cadev) -+ return -ENOMEM; -+ -+ cadev->regmap = regmap; -+ -+ adev = &cadev->adev; -+ adev->name = reset_name; -+ adev->dev.parent = dev; -+ adev->dev.release = spacemit_cadev_release; -+ adev->dev.of_node = dev->of_node; -+ ret = ida_alloc(&auxiliary_ids, GFP_KERNEL); -+ if (ret < 0) -+ goto err_free_cadev; -+ adev->id = ret; -+ -+ ret = auxiliary_device_init(adev); -+ if (ret) -+ goto err_free_aux_id; -+ -+ ret = auxiliary_device_add(adev); -+ if (ret) { -+ auxiliary_device_uninit(adev); -+ return ret; -+ } -+ -+ return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); -+ -+err_free_aux_id: -+ ida_free(&auxiliary_ids, adev->id); -+err_free_cadev: -+ kfree(cadev); -+ -+ return ret; -+} -+ -+int spacemit_ccu_probe(struct platform_device *pdev, const char *compat) -+{ -+ struct regmap *base_regmap, *lock_regmap = NULL; -+ const struct spacemit_ccu_data *data; -+ struct device *dev = &pdev->dev; -+ int ret; -+ -+ base_regmap = device_node_to_regmap(dev->of_node); -+ if (IS_ERR(base_regmap)) -+ return dev_err_probe(dev, PTR_ERR(base_regmap), -+ "failed to get regmap\n"); -+ -+ /* -+ * The lock status of PLLs locate in MPMU region, while PLLs themselves -+ * are in APBS region. Reference to MPMU syscon is required to check PLL -+ * status. -+ */ -+ if (compat && of_device_is_compatible(dev->of_node, compat)) { -+ struct device_node *mpmu = of_parse_phandle(dev->of_node, -+ "spacemit,mpmu", 0); -+ if (!mpmu) -+ return dev_err_probe(dev, -ENODEV, -+ "Cannot parse MPMU region\n"); -+ -+ lock_regmap = device_node_to_regmap(mpmu); -+ of_node_put(mpmu); -+ -+ if (IS_ERR(lock_regmap)) -+ return dev_err_probe(dev, PTR_ERR(lock_regmap), -+ "failed to get lock regmap\n"); -+ } -+ -+ data = of_device_get_match_data(dev); -+ -+ ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to register clocks\n"); -+ -+ ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to register resets\n"); -+ -+ return 0; -+} -+EXPORT_SYMBOL_NS_GPL(spacemit_ccu_probe, "CLK_SPACEMIT"); - - MODULE_DESCRIPTION("SpacemiT CCU common clock driver"); - MODULE_LICENSE("GPL"); -diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h -index da72f3836e0b..7ae244b5eace 100644 ---- a/drivers/clk/spacemit/ccu_common.h -+++ b/drivers/clk/spacemit/ccu_common.h -@@ -7,6 +7,8 @@ - #ifndef _CCU_COMMON_H_ - #define _CCU_COMMON_H_ - -+#include -+#include - #include - - struct ccu_common { -@@ -36,6 +38,12 @@ static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) - return container_of(hw, struct ccu_common, hw); - } - -+struct spacemit_ccu_data { -+ const char *reset_name; -+ struct clk_hw **hws; -+ size_t num; -+}; -+ - #define ccu_read(c, reg) \ - ({ \ - u32 tmp; \ -@@ -45,4 +53,6 @@ static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) - #define ccu_update(c, reg, mask, val) \ - regmap_update_bits((c)->regmap, (c)->reg_##reg, mask, val) - -+int spacemit_ccu_probe(struct platform_device *pdev, const char *compat); -+ - #endif /* _CCU_COMMON_H_ */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch b/SPECS/linux-lts/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch new file mode 100644 index 0000000000..eb8a0da4ac --- /dev/null +++ b/SPECS/linux-lts/0116-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch @@ -0,0 +1,519 @@ +From 4887997f9fc66c19a62763d21f3beb9036a5470b Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Sat, 1 Nov 2025 20:56:42 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: soc: spacemit: k3: add clock + support + +Add compatible strings for clock drivers to support Spacemit K3 SoC, +also includes all the defined clock IDs. + +The SpacemiT K3 SoC clock IP is scattered over several different blocks, +which are APBC, APBS, APMU, DCIU, MPMU, all of them are capable of +generating clock and reset signals. APMU and MPMU have additional Power +Domain management functionality. + +Following is a brief list that shows devices managed in each block: + +APBC: UART, GPIO, PWM, SPI, TIMER, I2S, IR, DR, TSEN, IPC, CAN +APBS: various PPL clocks control +APMU: CCI, CPU, CSI, ISP, LCD, USB, QSPI, DMA, VPU, GPU, DSI, PCIe, EMAC.. +DCID: SRAM, DMA, TCM +MPMU: various PLL1 derived clocks, UART, WATCHDOG, I2S + +Link: https://lore.kernel.org/r/20260108-k3-clk-v5-1-42a11b74ad58@gentoo.org +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Yixun Lan +(cherry picked from commit efe897b557e211a09f51d749eae5eca933e8bf56) +Signed-off-by: Han Gao +--- + .../bindings/clock/spacemit,k1-pll.yaml | 9 +- + .../soc/spacemit/spacemit,k1-syscon.yaml | 14 +- + .../dt-bindings/clock/spacemit,k3-clocks.h | 390 ++++++++++++++++++ + 3 files changed, 408 insertions(+), 5 deletions(-) + create mode 100644 include/dt-bindings/clock/spacemit,k3-clocks.h + +diff --git a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml +index 06bafd68c00a..cddf6a56dac0 100644 +--- a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml ++++ b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml +@@ -4,14 +4,16 @@ + $id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# + +-title: SpacemiT K1 PLL ++title: SpacemiT K1/K3 PLL + + maintainers: + - Haylen Chu + + properties: + compatible: +- const: spacemit,k1-pll ++ enum: ++ - spacemit,k1-pll ++ - spacemit,k3-pll + + reg: + maxItems: 1 +@@ -28,7 +30,8 @@ properties: + "#clock-cells": + const: 1 + description: +- See for valid indices. ++ For K1 SoC, check for valid indices. ++ For K3 SoC, check for valid indices. + + required: + - compatible +diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +index 133a391ee68c..d87131da30bc 100644 +--- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml ++++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +@@ -4,7 +4,7 @@ + $id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# + +-title: SpacemiT K1 SoC System Controller ++title: SpacemiT K1/K3 SoC System Controller + + maintainers: + - Haylen Chu +@@ -22,6 +22,10 @@ properties: + - spacemit,k1-syscon-rcpu + - spacemit,k1-syscon-rcpu2 + - spacemit,k1-syscon-apbc2 ++ - spacemit,k3-syscon-apbc ++ - spacemit,k3-syscon-apmu ++ - spacemit,k3-syscon-dciu ++ - spacemit,k3-syscon-mpmu + + reg: + maxItems: 1 +@@ -39,7 +43,8 @@ properties: + "#clock-cells": + const: 1 + description: +- See for valid indices. ++ For K1 SoC, check for valid indices. ++ For K3 SoC, check for valid indices. + + "#power-domain-cells": + const: 1 +@@ -60,6 +65,8 @@ allOf: + enum: + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu ++ - spacemit,k3-syscon-apmu ++ - spacemit,k3-syscon-mpmu + then: + required: + - "#power-domain-cells" +@@ -74,6 +81,9 @@ allOf: + - spacemit,k1-syscon-apbc + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu ++ - spacemit,k3-syscon-apbc ++ - spacemit,k3-syscon-apmu ++ - spacemit,k3-syscon-mpmu + then: + required: + - clocks +diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h +new file mode 100644 +index 000000000000..b22336f3ae40 +--- /dev/null ++++ b/include/dt-bindings/clock/spacemit,k3-clocks.h +@@ -0,0 +1,390 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ ++ ++#ifndef _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ ++#define _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ ++ ++/* APBS (PLL) clocks */ ++#define CLK_PLL1 0 ++#define CLK_PLL2 1 ++#define CLK_PLL3 2 ++#define CLK_PLL4 3 ++#define CLK_PLL5 4 ++#define CLK_PLL6 5 ++#define CLK_PLL7 6 ++#define CLK_PLL8 7 ++#define CLK_PLL1_D2 8 ++#define CLK_PLL1_D3 9 ++#define CLK_PLL1_D4 10 ++#define CLK_PLL1_D5 11 ++#define CLK_PLL1_D6 12 ++#define CLK_PLL1_D7 13 ++#define CLK_PLL1_D8 14 ++#define CLK_PLL1_DX 15 ++#define CLK_PLL1_D64 16 ++#define CLK_PLL1_D10_AUD 17 ++#define CLK_PLL1_D100_AUD 18 ++#define CLK_PLL2_D1 19 ++#define CLK_PLL2_D2 20 ++#define CLK_PLL2_D3 21 ++#define CLK_PLL2_D4 22 ++#define CLK_PLL2_D5 23 ++#define CLK_PLL2_D6 24 ++#define CLK_PLL2_D7 25 ++#define CLK_PLL2_D8 26 ++#define CLK_PLL2_66 27 ++#define CLK_PLL2_33 28 ++#define CLK_PLL2_50 29 ++#define CLK_PLL2_25 30 ++#define CLK_PLL2_20 31 ++#define CLK_PLL2_D24_125 32 ++#define CLK_PLL2_D120_25 33 ++#define CLK_PLL3_D1 34 ++#define CLK_PLL3_D2 35 ++#define CLK_PLL3_D3 36 ++#define CLK_PLL3_D4 37 ++#define CLK_PLL3_D5 38 ++#define CLK_PLL3_D6 39 ++#define CLK_PLL3_D7 40 ++#define CLK_PLL3_D8 41 ++#define CLK_PLL4_D1 42 ++#define CLK_PLL4_D2 43 ++#define CLK_PLL4_D3 44 ++#define CLK_PLL4_D4 45 ++#define CLK_PLL4_D5 46 ++#define CLK_PLL4_D6 47 ++#define CLK_PLL4_D7 48 ++#define CLK_PLL4_D8 49 ++#define CLK_PLL5_D1 50 ++#define CLK_PLL5_D2 51 ++#define CLK_PLL5_D3 52 ++#define CLK_PLL5_D4 53 ++#define CLK_PLL5_D5 54 ++#define CLK_PLL5_D6 55 ++#define CLK_PLL5_D7 56 ++#define CLK_PLL5_D8 57 ++#define CLK_PLL6_D1 58 ++#define CLK_PLL6_D2 59 ++#define CLK_PLL6_D3 60 ++#define CLK_PLL6_D4 61 ++#define CLK_PLL6_D5 62 ++#define CLK_PLL6_D6 63 ++#define CLK_PLL6_D7 64 ++#define CLK_PLL6_D8 65 ++#define CLK_PLL6_80 66 ++#define CLK_PLL6_40 67 ++#define CLK_PLL6_20 68 ++#define CLK_PLL7_D1 69 ++#define CLK_PLL7_D2 70 ++#define CLK_PLL7_D3 71 ++#define CLK_PLL7_D4 72 ++#define CLK_PLL7_D5 73 ++#define CLK_PLL7_D6 74 ++#define CLK_PLL7_D7 75 ++#define CLK_PLL7_D8 76 ++#define CLK_PLL8_D1 77 ++#define CLK_PLL8_D2 78 ++#define CLK_PLL8_D3 79 ++#define CLK_PLL8_D4 80 ++#define CLK_PLL8_D5 81 ++#define CLK_PLL8_D6 82 ++#define CLK_PLL8_D7 83 ++#define CLK_PLL8_D8 84 ++ ++/* MPMU clocks */ ++#define CLK_MPMU_PLL1_307P2 0 ++#define CLK_MPMU_PLL1_76P8 1 ++#define CLK_MPMU_PLL1_61P44 2 ++#define CLK_MPMU_PLL1_153P6 3 ++#define CLK_MPMU_PLL1_102P4 4 ++#define CLK_MPMU_PLL1_51P2 5 ++#define CLK_MPMU_PLL1_51P2_AP 6 ++#define CLK_MPMU_PLL1_57P6 7 ++#define CLK_MPMU_PLL1_25P6 8 ++#define CLK_MPMU_PLL1_12P8 9 ++#define CLK_MPMU_PLL1_12P8_WDT 10 ++#define CLK_MPMU_PLL1_6P4 11 ++#define CLK_MPMU_PLL1_3P2 12 ++#define CLK_MPMU_PLL1_1P6 13 ++#define CLK_MPMU_PLL1_0P8 14 ++#define CLK_MPMU_PLL1_409P6 15 ++#define CLK_MPMU_PLL1_204P8 16 ++#define CLK_MPMU_PLL1_491 17 ++#define CLK_MPMU_PLL1_245P76 18 ++#define CLK_MPMU_PLL1_614 19 ++#define CLK_MPMU_PLL1_47P26 20 ++#define CLK_MPMU_PLL1_31P5 21 ++#define CLK_MPMU_PLL1_819 22 ++#define CLK_MPMU_PLL1_1228 23 ++#define CLK_MPMU_APB 24 ++#define CLK_MPMU_SLOW_UART 25 ++#define CLK_MPMU_SLOW_UART1 26 ++#define CLK_MPMU_SLOW_UART2 27 ++#define CLK_MPMU_WDT 28 ++#define CLK_MPMU_WDT_BUS 29 ++#define CLK_MPMU_RIPC 30 ++#define CLK_MPMU_I2S_153P6 31 ++#define CLK_MPMU_I2S_153P6_BASE 32 ++#define CLK_MPMU_I2S_SYSCLK_SRC 33 ++#define CLK_MPMU_I2S1_SYSCLK 34 ++#define CLK_MPMU_I2S_BCLK 35 ++#define CLK_MPMU_I2S0_SYSCLK_SEL 36 ++#define CLK_MPMU_I2S2_SYSCLK_SEL 37 ++#define CLK_MPMU_I2S3_SYSCLK_SEL 38 ++#define CLK_MPMU_I2S4_SYSCLK_SEL 39 ++#define CLK_MPMU_I2S5_SYSCLK_SEL 40 ++#define CLK_MPMU_I2S0_SYSCLK_DIV 41 ++#define CLK_MPMU_I2S2_SYSCLK_DIV 42 ++#define CLK_MPMU_I2S3_SYSCLK_DIV 43 ++#define CLK_MPMU_I2S4_SYSCLK_DIV 44 ++#define CLK_MPMU_I2S5_SYSCLK_DIV 45 ++#define CLK_MPMU_I2S0_SYSCLK 46 ++#define CLK_MPMU_I2S2_SYSCLK 47 ++#define CLK_MPMU_I2S3_SYSCLK 48 ++#define CLK_MPMU_I2S4_SYSCLK 49 ++#define CLK_MPMU_I2S5_SYSCLK 50 ++ ++/* APBC clocks */ ++#define CLK_APBC_UART0 0 ++#define CLK_APBC_UART2 1 ++#define CLK_APBC_UART3 2 ++#define CLK_APBC_UART4 3 ++#define CLK_APBC_UART5 4 ++#define CLK_APBC_UART6 5 ++#define CLK_APBC_UART7 6 ++#define CLK_APBC_UART8 7 ++#define CLK_APBC_UART9 8 ++#define CLK_APBC_UART10 9 ++#define CLK_APBC_UART0_BUS 10 ++#define CLK_APBC_UART2_BUS 11 ++#define CLK_APBC_UART3_BUS 12 ++#define CLK_APBC_UART4_BUS 13 ++#define CLK_APBC_UART5_BUS 14 ++#define CLK_APBC_UART6_BUS 15 ++#define CLK_APBC_UART7_BUS 16 ++#define CLK_APBC_UART8_BUS 17 ++#define CLK_APBC_UART9_BUS 18 ++#define CLK_APBC_UART10_BUS 19 ++#define CLK_APBC_GPIO 20 ++#define CLK_APBC_GPIO_BUS 21 ++#define CLK_APBC_PWM0 22 ++#define CLK_APBC_PWM1 23 ++#define CLK_APBC_PWM2 24 ++#define CLK_APBC_PWM3 25 ++#define CLK_APBC_PWM4 26 ++#define CLK_APBC_PWM5 27 ++#define CLK_APBC_PWM6 28 ++#define CLK_APBC_PWM7 29 ++#define CLK_APBC_PWM8 30 ++#define CLK_APBC_PWM9 31 ++#define CLK_APBC_PWM10 32 ++#define CLK_APBC_PWM11 33 ++#define CLK_APBC_PWM12 34 ++#define CLK_APBC_PWM13 35 ++#define CLK_APBC_PWM14 36 ++#define CLK_APBC_PWM15 37 ++#define CLK_APBC_PWM16 38 ++#define CLK_APBC_PWM17 39 ++#define CLK_APBC_PWM18 40 ++#define CLK_APBC_PWM19 41 ++#define CLK_APBC_PWM0_BUS 42 ++#define CLK_APBC_PWM1_BUS 43 ++#define CLK_APBC_PWM2_BUS 44 ++#define CLK_APBC_PWM3_BUS 45 ++#define CLK_APBC_PWM4_BUS 46 ++#define CLK_APBC_PWM5_BUS 47 ++#define CLK_APBC_PWM6_BUS 48 ++#define CLK_APBC_PWM7_BUS 49 ++#define CLK_APBC_PWM8_BUS 50 ++#define CLK_APBC_PWM9_BUS 51 ++#define CLK_APBC_PWM10_BUS 52 ++#define CLK_APBC_PWM11_BUS 53 ++#define CLK_APBC_PWM12_BUS 54 ++#define CLK_APBC_PWM13_BUS 55 ++#define CLK_APBC_PWM14_BUS 56 ++#define CLK_APBC_PWM15_BUS 57 ++#define CLK_APBC_PWM16_BUS 58 ++#define CLK_APBC_PWM17_BUS 59 ++#define CLK_APBC_PWM18_BUS 60 ++#define CLK_APBC_PWM19_BUS 61 ++#define CLK_APBC_SPI0_I2S_BCLK 62 ++#define CLK_APBC_SPI1_I2S_BCLK 63 ++#define CLK_APBC_SPI3_I2S_BCLK 64 ++#define CLK_APBC_SPI0 65 ++#define CLK_APBC_SPI1 66 ++#define CLK_APBC_SPI3 67 ++#define CLK_APBC_SPI0_BUS 68 ++#define CLK_APBC_SPI1_BUS 69 ++#define CLK_APBC_SPI3_BUS 70 ++#define CLK_APBC_RTC 71 ++#define CLK_APBC_RTC_BUS 72 ++#define CLK_APBC_TWSI0 73 ++#define CLK_APBC_TWSI1 74 ++#define CLK_APBC_TWSI2 75 ++#define CLK_APBC_TWSI4 76 ++#define CLK_APBC_TWSI5 77 ++#define CLK_APBC_TWSI6 78 ++#define CLK_APBC_TWSI8 79 ++#define CLK_APBC_TWSI0_BUS 80 ++#define CLK_APBC_TWSI1_BUS 81 ++#define CLK_APBC_TWSI2_BUS 82 ++#define CLK_APBC_TWSI4_BUS 83 ++#define CLK_APBC_TWSI5_BUS 84 ++#define CLK_APBC_TWSI6_BUS 85 ++#define CLK_APBC_TWSI8_BUS 86 ++#define CLK_APBC_TIMERS0 87 ++#define CLK_APBC_TIMERS1 88 ++#define CLK_APBC_TIMERS2 89 ++#define CLK_APBC_TIMERS3 90 ++#define CLK_APBC_TIMERS4 91 ++#define CLK_APBC_TIMERS5 92 ++#define CLK_APBC_TIMERS6 93 ++#define CLK_APBC_TIMERS7 94 ++#define CLK_APBC_TIMERS0_BUS 95 ++#define CLK_APBC_TIMERS1_BUS 96 ++#define CLK_APBC_TIMERS2_BUS 97 ++#define CLK_APBC_TIMERS3_BUS 98 ++#define CLK_APBC_TIMERS4_BUS 99 ++#define CLK_APBC_TIMERS5_BUS 100 ++#define CLK_APBC_TIMERS6_BUS 101 ++#define CLK_APBC_TIMERS7_BUS 102 ++#define CLK_APBC_AIB 103 ++#define CLK_APBC_AIB_BUS 104 ++#define CLK_APBC_ONEWIRE 105 ++#define CLK_APBC_ONEWIRE_BUS 106 ++#define CLK_APBC_I2S0_BCLK 107 ++#define CLK_APBC_I2S1_BCLK 108 ++#define CLK_APBC_I2S2_BCLK 109 ++#define CLK_APBC_I2S3_BCLK 110 ++#define CLK_APBC_I2S4_BCLK 111 ++#define CLK_APBC_I2S5_BCLK 112 ++#define CLK_APBC_I2S0 113 ++#define CLK_APBC_I2S1 114 ++#define CLK_APBC_I2S2 115 ++#define CLK_APBC_I2S3 116 ++#define CLK_APBC_I2S4 117 ++#define CLK_APBC_I2S5 118 ++#define CLK_APBC_I2S0_BUS 119 ++#define CLK_APBC_I2S1_BUS 120 ++#define CLK_APBC_I2S2_BUS 121 ++#define CLK_APBC_I2S3_BUS 122 ++#define CLK_APBC_I2S4_BUS 123 ++#define CLK_APBC_I2S5_BUS 124 ++#define CLK_APBC_DRO 125 ++#define CLK_APBC_IR0 126 ++#define CLK_APBC_IR1 127 ++#define CLK_APBC_TSEN 128 ++#define CLK_APBC_TSEN_BUS 129 ++#define CLK_APBC_IPC_AP2RCPU 130 ++#define CLK_APBC_IPC_AP2RCPU_BUS 131 ++#define CLK_APBC_CAN0 132 ++#define CLK_APBC_CAN1 133 ++#define CLK_APBC_CAN2 134 ++#define CLK_APBC_CAN3 135 ++#define CLK_APBC_CAN4 136 ++#define CLK_APBC_CAN0_BUS 137 ++#define CLK_APBC_CAN1_BUS 138 ++#define CLK_APBC_CAN2_BUS 139 ++#define CLK_APBC_CAN3_BUS 140 ++#define CLK_APBC_CAN4_BUS 141 ++ ++/* APMU clocks */ ++#define CLK_APMU_AXICLK 0 ++#define CLK_APMU_CCI550 1 ++#define CLK_APMU_CPU_C0_CORE 2 ++#define CLK_APMU_CPU_C1_CORE 3 ++#define CLK_APMU_CPU_C2_CORE 4 ++#define CLK_APMU_CPU_C3_CORE 5 ++#define CLK_APMU_CCIC2PHY 6 ++#define CLK_APMU_CCIC3PHY 7 ++#define CLK_APMU_CSI 8 ++#define CLK_APMU_ISP_BUS 9 ++#define CLK_APMU_D1P_1228P8 10 ++#define CLK_APMU_D1P_819P2 11 ++#define CLK_APMU_D1P_614P4 12 ++#define CLK_APMU_D1P_491P52 13 ++#define CLK_APMU_D1P_409P6 14 ++#define CLK_APMU_D1P_307P2 15 ++#define CLK_APMU_D1P_245P76 16 ++#define CLK_APMU_V2D 17 ++#define CLK_APMU_DSI_ESC 18 ++#define CLK_APMU_LCD_HCLK 19 ++#define CLK_APMU_LCD_DSC 20 ++#define CLK_APMU_LCD_PXCLK 21 ++#define CLK_APMU_LCD_MCLK 22 ++#define CLK_APMU_CCIC_4X 23 ++#define CLK_APMU_CCIC1PHY 24 ++#define CLK_APMU_SC2_HCLK 25 ++#define CLK_APMU_SDH_AXI 26 ++#define CLK_APMU_SDH0 27 ++#define CLK_APMU_SDH1 28 ++#define CLK_APMU_SDH2 29 ++#define CLK_APMU_USB2_BUS 30 ++#define CLK_APMU_USB3_PORTA_BUS 31 ++#define CLK_APMU_USB3_PORTB_BUS 32 ++#define CLK_APMU_USB3_PORTC_BUS 33 ++#define CLK_APMU_USB3_PORTD_BUS 34 ++#define CLK_APMU_QSPI 35 ++#define CLK_APMU_QSPI_BUS 36 ++#define CLK_APMU_DMA 37 ++#define CLK_APMU_AES_WTM 38 ++#define CLK_APMU_VPU 39 ++#define CLK_APMU_DTC 40 ++#define CLK_APMU_GPU 41 ++#define CLK_APMU_MC_AHB 42 ++#define CLK_APMU_TOP_DCLK 43 ++#define CLK_APMU_UCIE 44 ++#define CLK_APMU_UCIE_SBCLK 45 ++#define CLK_APMU_RCPU 46 ++#define CLK_APMU_DSI4LN2_DSI_ESC 47 ++#define CLK_APMU_DSI4LN2_LCD_DSC 48 ++#define CLK_APMU_DSI4LN2_LCD_PXCLK 49 ++#define CLK_APMU_DSI4LN2_LCD_MCLK 50 ++#define CLK_APMU_DSI4LN2_DPU_ACLK 51 ++#define CLK_APMU_DPU_ACLK 52 ++#define CLK_APMU_UFS_ACLK 53 ++#define CLK_APMU_EDP0_PXCLK 54 ++#define CLK_APMU_EDP1_PXCLK 55 ++#define CLK_APMU_PCIE_PORTA_MSTE 56 ++#define CLK_APMU_PCIE_PORTA_SLV 57 ++#define CLK_APMU_PCIE_PORTB_MSTE 58 ++#define CLK_APMU_PCIE_PORTB_SLV 59 ++#define CLK_APMU_PCIE_PORTC_MSTE 60 ++#define CLK_APMU_PCIE_PORTC_SLV 61 ++#define CLK_APMU_PCIE_PORTD_MSTE 62 ++#define CLK_APMU_PCIE_PORTD_SLV 63 ++#define CLK_APMU_PCIE_PORTE_MSTE 64 ++#define CLK_APMU_PCIE_PORTE_SLV 65 ++#define CLK_APMU_EMAC0_BUS 66 ++#define CLK_APMU_EMAC0_REF 67 ++#define CLK_APMU_EMAC0_1588 68 ++#define CLK_APMU_EMAC0_RGMII_TX 69 ++#define CLK_APMU_EMAC1_BUS 70 ++#define CLK_APMU_EMAC1_REF 71 ++#define CLK_APMU_EMAC1_1588 72 ++#define CLK_APMU_EMAC1_RGMII_TX 73 ++#define CLK_APMU_EMAC2_BUS 74 ++#define CLK_APMU_EMAC2_REF 75 ++#define CLK_APMU_EMAC2_1588 76 ++#define CLK_APMU_EMAC2_RGMII_TX 77 ++#define CLK_APMU_ESPI_SCLK_SRC 78 ++#define CLK_APMU_ESPI_SCLK 79 ++#define CLK_APMU_ESPI_MCLK 80 ++#define CLK_APMU_CAM_SRC1 81 ++#define CLK_APMU_CAM_SRC2 82 ++#define CLK_APMU_CAM_SRC3 83 ++#define CLK_APMU_CAM_SRC4 84 ++#define CLK_APMU_ISIM_VCLK0 85 ++#define CLK_APMU_ISIM_VCLK1 86 ++#define CLK_APMU_ISIM_VCLK2 87 ++#define CLK_APMU_ISIM_VCLK3 88 ++ ++/* DCIU clocks */ ++#define CLK_DCIU_HDMA 0 ++#define CLK_DCIU_DMA350 1 ++#define CLK_DCIU_C2_TCM_PIPE 2 ++#define CLK_DCIU_C3_TCM_PIPE 3 ++ ++#endif /* _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0117-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch b/SPECS/linux-lts/0117-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch deleted file mode 100644 index 72381976e0..0000000000 --- a/SPECS/linux-lts/0117-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 7c0b4de9221472ba52db151507973c2e67c7f5c2 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sat, 3 Jan 2026 14:14:36 +0800 -Subject: [PATCH 117/467] UPSTREAM: clk: spacemit: add platform SoC prefix to - reset name - -This change is needed for adding future new SpacemiT K3 reset driver. - -Since both K1 and K3 reset code register via the same module which its -name changed to spacemit_ccu, it's necessary to encode the platform/SoC -in the reset auxiliary device name to distinguish them, otherwise two -reset drivers will claim to support same "compatible" auxiliary device -even in the case of only one CCU clock driver got registered, which in -the end lead to a broken reset driver. - -This change will introduce a runtime break to reset driver, and will be -fixed in follow-up commit: -ecff77f7c041 ("reset: spacemit: fix auxiliary device id") - -Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-3-badf635993d3@gentoo.org -Reviewed-by: Alex Elder -Signed-off-by: Yixun Lan -(cherry picked from commit 0664a46f93e2fb2f75fa05b5f08949600cce88f9) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k1.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c -index 02c792a73759..dee14d25f75d 100644 ---- a/drivers/clk/spacemit/ccu-k1.c -+++ b/drivers/clk/spacemit/ccu-k1.c -@@ -789,7 +789,7 @@ static struct clk_hw *k1_ccu_mpmu_hws[] = { - }; - - static const struct spacemit_ccu_data k1_ccu_mpmu_data = { -- .reset_name = "mpmu-reset", -+ .reset_name = "k1-mpmu-reset", - .hws = k1_ccu_mpmu_hws, - .num = ARRAY_SIZE(k1_ccu_mpmu_hws), - }; -@@ -900,7 +900,7 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { - }; - - static const struct spacemit_ccu_data k1_ccu_apbc_data = { -- .reset_name = "apbc-reset", -+ .reset_name = "k1-apbc-reset", - .hws = k1_ccu_apbc_hws, - .num = ARRAY_SIZE(k1_ccu_apbc_hws), - }; -@@ -971,21 +971,21 @@ static struct clk_hw *k1_ccu_apmu_hws[] = { - }; - - static const struct spacemit_ccu_data k1_ccu_apmu_data = { -- .reset_name = "apmu-reset", -+ .reset_name = "k1-apmu-reset", - .hws = k1_ccu_apmu_hws, - .num = ARRAY_SIZE(k1_ccu_apmu_hws), - }; - - static const struct spacemit_ccu_data k1_ccu_rcpu_data = { -- .reset_name = "rcpu-reset", -+ .reset_name = "k1-rcpu-reset", - }; - - static const struct spacemit_ccu_data k1_ccu_rcpu2_data = { -- .reset_name = "rcpu2-reset", -+ .reset_name = "k1-rcpu2-reset", - }; - - static const struct spacemit_ccu_data k1_ccu_apbc2_data = { -- .reset_name = "apbc2-reset", -+ .reset_name = "k1-apbc2-reset", - }; - - static const struct of_device_id of_k1_ccu_match[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch b/SPECS/linux-lts/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch new file mode 100644 index 0000000000..3bd158963f --- /dev/null +++ b/SPECS/linux-lts/0117-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch @@ -0,0 +1,101 @@ +From f461f20d8d5d33bdf1d9fa07acf5a6337f03e57c Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 31 Oct 2025 20:40:46 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: ccu_mix: add inverted enable + gate clock + +K3 SoC has the clock IP which support to write value 0 for enabling the +clock, while write 1 for disabling it, thus the enable BIT is inverted. +So, introduce a flag to support the inverted gate clock. + +Link: https://lore.kernel.org/r/20260108-k3-clk-v5-2-42a11b74ad58@gentoo.org +Signed-off-by: Yixun Lan +(cherry picked from commit ace73b7e27633ec770cfb24cd4ff42c24815a9aa) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu_mix.c | 12 ++++++++---- + drivers/clk/spacemit/ccu_mix.h | 12 ++++++++++++ + 2 files changed, 20 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu_mix.c b/drivers/clk/spacemit/ccu_mix.c +index 9a3fc9ea1ce5..a8b407049bf4 100644 +--- a/drivers/clk/spacemit/ccu_mix.c ++++ b/drivers/clk/spacemit/ccu_mix.c +@@ -16,17 +16,19 @@ + static void ccu_gate_disable(struct clk_hw *hw) + { + struct ccu_mix *mix = hw_to_ccu_mix(hw); ++ struct ccu_gate_config *gate = &mix->gate; ++ u32 val = gate->inverted ? gate->mask : 0; + +- ccu_update(&mix->common, ctrl, mix->gate.mask, 0); ++ ccu_update(&mix->common, ctrl, gate->mask, val); + } + + static int ccu_gate_enable(struct clk_hw *hw) + { + struct ccu_mix *mix = hw_to_ccu_mix(hw); + struct ccu_gate_config *gate = &mix->gate; ++ u32 val = gate->inverted ? 0 : gate->mask; + +- ccu_update(&mix->common, ctrl, gate->mask, gate->mask); +- ++ ccu_update(&mix->common, ctrl, gate->mask, val); + return 0; + } + +@@ -34,8 +36,10 @@ static int ccu_gate_is_enabled(struct clk_hw *hw) + { + struct ccu_mix *mix = hw_to_ccu_mix(hw); + struct ccu_gate_config *gate = &mix->gate; ++ u32 tmp = ccu_read(&mix->common, ctrl) & gate->mask; ++ u32 val = gate->inverted ? 0 : gate->mask; + +- return (ccu_read(&mix->common, ctrl) & gate->mask) == gate->mask; ++ return !!(tmp == val); + } + + static unsigned long ccu_factor_recalc_rate(struct clk_hw *hw, +diff --git a/drivers/clk/spacemit/ccu_mix.h b/drivers/clk/spacemit/ccu_mix.h +index 54d40cd39b27..8a70cf151461 100644 +--- a/drivers/clk/spacemit/ccu_mix.h ++++ b/drivers/clk/spacemit/ccu_mix.h +@@ -16,9 +16,11 @@ + * + * @mask: Mask to enable the gate. Some clocks may have more than one bit + * set in this field. ++ * @inverted: Enable bit is inverted, 1 - disable clock, 0 - enable clock + */ + struct ccu_gate_config { + u32 mask; ++ bool inverted; + }; + + struct ccu_factor_config { +@@ -48,6 +50,7 @@ struct ccu_mix { + #define CCU_FACTOR_INIT(_div, _mul) { .div = _div, .mul = _mul } + #define CCU_MUX_INIT(_shift, _width) { .shift = _shift, .width = _width } + #define CCU_DIV_INIT(_shift, _width) { .shift = _shift, .width = _width } ++#define CCU_GATE_FLAGS_INIT(_mask, _inverted) { .mask = _mask, .inverted = _inverted } + + #define CCU_PARENT_HW(_parent) { .hw = &_parent.common.hw } + #define CCU_PARENT_NAME(_name) { .fw_name = #_name } +@@ -101,6 +104,15 @@ static struct ccu_mix _name = { \ + } \ + } + ++#define CCU_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _inverted, _flags) \ ++static struct ccu_mix _name = { \ ++ .gate = CCU_GATE_FLAGS_INIT(_mask_gate, _inverted), \ ++ .common = { \ ++ .reg_ctrl = _reg_ctrl, \ ++ CCU_MIX_INITHW(_name, _parent, spacemit_ccu_gate_ops, _flags), \ ++ } \ ++} ++ + #define CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \ + _mul, _flags) \ + static struct ccu_mix _name = { \ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch b/SPECS/linux-lts/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch new file mode 100644 index 0000000000..6dfcedf96e --- /dev/null +++ b/SPECS/linux-lts/0118-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch @@ -0,0 +1,285 @@ +From a7ce4c7a2f5e9b248b21befc2f291b0d3ae3b195 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 27 Oct 2025 21:41:24 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: ccu_pll: add plla type clock + +Introduce a new clock PLLA for SpacemiT's K3 SoC which has a different +register layout comparing to previous PPL type. And, It is configured +by swcr1, swcr3 and swcr2 BIT[15:8]. + +Link: https://lore.kernel.org/r/20260108-k3-clk-v5-3-42a11b74ad58@gentoo.org +Signed-off-by: Yixun Lan +(cherry picked from commit 3a086236c600739d6653c0405d86aff7d6f03c06) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu_common.h | 1 + + drivers/clk/spacemit/ccu_pll.c | 118 ++++++++++++++++++++++++++++++ + drivers/clk/spacemit/ccu_pll.h | 57 ++++++++++++--- + 3 files changed, 166 insertions(+), 10 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h +index 7ae244b5eace..8691698e007d 100644 +--- a/drivers/clk/spacemit/ccu_common.h ++++ b/drivers/clk/spacemit/ccu_common.h +@@ -26,6 +26,7 @@ struct ccu_common { + /* For PLL */ + struct { + u32 reg_swcr1; ++ u32 reg_swcr2; + u32 reg_swcr3; + }; + }; +diff --git a/drivers/clk/spacemit/ccu_pll.c b/drivers/clk/spacemit/ccu_pll.c +index 76d0244873d8..d4066a0ed452 100644 +--- a/drivers/clk/spacemit/ccu_pll.c ++++ b/drivers/clk/spacemit/ccu_pll.c +@@ -17,6 +17,9 @@ + #define PLL_SWCR3_EN ((u32)BIT(31)) + #define PLL_SWCR3_MASK GENMASK(30, 0) + ++#define PLLA_SWCR2_EN ((u32)BIT(16)) ++#define PLLA_SWCR2_MASK GENMASK(15, 8) ++ + static const struct ccu_pll_rate_tbl *ccu_pll_lookup_best_rate(struct ccu_pll *pll, + unsigned long rate) + { +@@ -148,6 +151,110 @@ static int ccu_pll_init(struct clk_hw *hw) + return 0; + } + ++static const struct ccu_pll_rate_tbl *ccu_plla_lookup_matched_entry(struct ccu_pll *pll) ++{ ++ struct ccu_pll_config *config = &pll->config; ++ const struct ccu_pll_rate_tbl *entry; ++ u32 i, swcr1, swcr2, swcr3; ++ ++ swcr1 = ccu_read(&pll->common, swcr1); ++ swcr2 = ccu_read(&pll->common, swcr2); ++ swcr2 &= PLLA_SWCR2_MASK; ++ swcr3 = ccu_read(&pll->common, swcr3); ++ ++ for (i = 0; i < config->tbl_num; i++) { ++ entry = &config->rate_tbl[i]; ++ ++ if (swcr1 == entry->swcr1 && ++ swcr2 == entry->swcr2 && ++ swcr3 == entry->swcr3) ++ return entry; ++ } ++ ++ return NULL; ++} ++ ++static void ccu_plla_update_param(struct ccu_pll *pll, const struct ccu_pll_rate_tbl *entry) ++{ ++ struct ccu_common *common = &pll->common; ++ ++ regmap_write(common->regmap, common->reg_swcr1, entry->swcr1); ++ regmap_write(common->regmap, common->reg_swcr3, entry->swcr3); ++ ccu_update(common, swcr2, PLLA_SWCR2_MASK, entry->swcr2); ++} ++ ++static int ccu_plla_is_enabled(struct clk_hw *hw) ++{ ++ struct ccu_common *common = hw_to_ccu_common(hw); ++ ++ return ccu_read(common, swcr2) & PLLA_SWCR2_EN; ++} ++ ++static int ccu_plla_enable(struct clk_hw *hw) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ struct ccu_common *common = &pll->common; ++ unsigned int tmp; ++ ++ ccu_update(common, swcr2, PLLA_SWCR2_EN, PLLA_SWCR2_EN); ++ ++ /* check lock status */ ++ return regmap_read_poll_timeout_atomic(common->lock_regmap, ++ pll->config.reg_lock, ++ tmp, ++ tmp & pll->config.mask_lock, ++ PLL_DELAY_US, PLL_TIMEOUT_US); ++} ++ ++static void ccu_plla_disable(struct clk_hw *hw) ++{ ++ struct ccu_common *common = hw_to_ccu_common(hw); ++ ++ ccu_update(common, swcr2, PLLA_SWCR2_EN, 0); ++} ++ ++/* ++ * PLLAs must be gated before changing rate, which is ensured by ++ * flag CLK_SET_RATE_GATE. ++ */ ++static int ccu_plla_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ const struct ccu_pll_rate_tbl *entry; ++ ++ entry = ccu_pll_lookup_best_rate(pll, rate); ++ ccu_plla_update_param(pll, entry); ++ ++ return 0; ++} ++ ++static unsigned long ccu_plla_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ const struct ccu_pll_rate_tbl *entry; ++ ++ entry = ccu_plla_lookup_matched_entry(pll); ++ ++ WARN_ON_ONCE(!entry); ++ ++ return entry ? entry->rate : 0; ++} ++ ++static int ccu_plla_init(struct clk_hw *hw) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ ++ if (ccu_plla_lookup_matched_entry(pll)) ++ return 0; ++ ++ ccu_plla_disable(hw); ++ ccu_plla_update_param(pll, &pll->config.rate_tbl[0]); ++ ++ return 0; ++} ++ + const struct clk_ops spacemit_ccu_pll_ops = { + .init = ccu_pll_init, + .enable = ccu_pll_enable, +@@ -158,3 +265,14 @@ const struct clk_ops spacemit_ccu_pll_ops = { + .is_enabled = ccu_pll_is_enabled, + }; + EXPORT_SYMBOL_NS_GPL(spacemit_ccu_pll_ops, "CLK_SPACEMIT"); ++ ++const struct clk_ops spacemit_ccu_plla_ops = { ++ .init = ccu_plla_init, ++ .enable = ccu_plla_enable, ++ .disable = ccu_plla_disable, ++ .set_rate = ccu_plla_set_rate, ++ .recalc_rate = ccu_plla_recalc_rate, ++ .determine_rate = ccu_pll_determine_rate, ++ .is_enabled = ccu_plla_is_enabled, ++}; ++EXPORT_SYMBOL_NS_GPL(spacemit_ccu_plla_ops, "CLK_SPACEMIT"); +diff --git a/drivers/clk/spacemit/ccu_pll.h b/drivers/clk/spacemit/ccu_pll.h +index 0592f4c3068c..e41db5c97c1a 100644 +--- a/drivers/clk/spacemit/ccu_pll.h ++++ b/drivers/clk/spacemit/ccu_pll.h +@@ -16,14 +16,31 @@ + * configuration. + * + * @rate: PLL rate +- * @swcr1: Register value of PLLX_SW1_CTRL (PLLx_SWCR1). +- * @swcr3: Register value of the PLLx_SW3_CTRL's lowest 31 bits of +- * PLLx_SW3_CTRL (PLLx_SWCR3). This highest bit is for enabling +- * the PLL and not contained in this field. ++ * @swcr1: Value of register PLLx_SW1_CTRL. ++ * @swcr2: Value of register PLLAx_SW2_CTRL. ++ * @swcr3: value of register PLLx_SW3_CTRL. ++ * ++ * See below tables for the register used in PPL/PPLA clocks ++ * ++ * Regular PLL type ++ * | Enable | swcr3 | PLLx_SW3_CTRL - BIT[31] | ++ * ----------------------------------------------- ++ * | Config | swcr1 | PLLx_SW1_CTRL - BIT[31:0] | ++ * | | swcr2 | Not used | ++ * | | swcr3 | PLLx_SW3_CTRL - BIT[30:0] | ++ * ++ * Special PLL type A ++ * | Enable | swcr2 | PLLAx_SW2_CTRL - BIT[16] | ++ * ----------------------------------------------- ++ * | Config | swcr1 | PLLAx_SW1_CTRL - BIT[31:0] | ++ * | | swcr2 | PLLAx_SW2_CTRL - BIT[15:8] | ++ * | | swcr3 | PLLAx_SW3_CTRL - BIT[31:0] | ++ * + */ + struct ccu_pll_rate_tbl { + unsigned long rate; + u32 swcr1; ++ u32 swcr2; + u32 swcr3; + }; + +@@ -36,11 +53,19 @@ struct ccu_pll_config { + + #define CCU_PLL_RATE(_rate, _swcr1, _swcr3) \ + { \ +- .rate = _rate, \ ++ .rate = _rate, \ + .swcr1 = _swcr1, \ + .swcr3 = _swcr3, \ + } + ++#define CCU_PLLA_RATE(_rate, _swcr1, _swcr2, _swcr3) \ ++ { \ ++ .rate = _rate, \ ++ .swcr1 = _swcr1, \ ++ .swcr2 = _swcr2, \ ++ .swcr3 = _swcr3, \ ++ } ++ + struct ccu_pll { + struct ccu_common common; + struct ccu_pll_config config; +@@ -54,26 +79,37 @@ struct ccu_pll { + .mask_lock = (_mask_lock), \ + } + +-#define CCU_PLL_HWINIT(_name, _flags) \ ++#define CCU_PLL_COMMON_HWINIT(_name, _ops, _flags) \ + (&(struct clk_init_data) { \ + .name = #_name, \ +- .ops = &spacemit_ccu_pll_ops, \ ++ .ops = _ops, \ + .parent_data = &(struct clk_parent_data) { .index = 0 }, \ + .num_parents = 1, \ + .flags = _flags, \ + }) + +-#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \ +- _mask_lock, _flags) \ ++#define CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ ++ _reg_lock, _mask_lock, _ops, _flags) \ + static struct ccu_pll _name = { \ + .config = CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock), \ + .common = { \ + .reg_swcr1 = _reg_swcr1, \ ++ .reg_swcr2 = _reg_swcr2, \ + .reg_swcr3 = _reg_swcr3, \ +- .hw.init = CCU_PLL_HWINIT(_name, _flags) \ ++ .hw.init = CCU_PLL_COMMON_HWINIT(_name, _ops, _flags) \ + } \ + } + ++#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \ ++ _mask_lock, _flags) \ ++ CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, 0, _reg_swcr3, \ ++ _reg_lock, _mask_lock, &spacemit_ccu_pll_ops, _flags) ++ ++#define CCU_PLLA_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ ++ _reg_lock, _mask_lock, _flags) \ ++ CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ ++ _reg_lock, _mask_lock, &spacemit_ccu_plla_ops, _flags) ++ + static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw) + { + struct ccu_common *common = hw_to_ccu_common(hw); +@@ -82,5 +118,6 @@ static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw) + } + + extern const struct clk_ops spacemit_ccu_pll_ops; ++extern const struct clk_ops spacemit_ccu_plla_ops; + + #endif +-- +2.53.0 + diff --git a/SPECS/linux-lts/0118-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch b/SPECS/linux-lts/0118-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch deleted file mode 100644 index 42dc66ad65..0000000000 --- a/SPECS/linux-lts/0118-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 316e5feca8326de2fcdcb6a5ad36fbdbf7b12758 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 19 Dec 2025 05:34:39 +0800 -Subject: [PATCH 118/467] UPSTREAM: reset: spacemit: fix auxiliary device id - -Due to the auxiliary register procedure moved to ccu common module where -the module name changed to spacemit_ccu, then the reset auxiliary device -register id also need to be adjusted in order to prepare for adding new -K3 reset driver, otherwise two reset drivers will claim to support same -"compatible" auxiliary device. - -In order to prevent the reset driver breakage, this commit is necessary -as a post-fix for changes introduced by two patches below, and should be -merged with them to make the patch series runtime bisectable. -("clk: spacemit: add platform SoC prefix to reset name") -("clk: spacemit: extract common ccu functions") - -Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-4-badf635993d3@gentoo.org -Acked-by: Philipp Zabel -Reviewed-by: Alex Elder -Signed-off-by: Yixun Lan -(cherry picked from commit ecff77f7c04141cc18ee2482936c96117060c0f2) -Signed-off-by: Han Gao ---- - drivers/reset/reset-spacemit.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/reset-spacemit.c -index e1272aff28f7..cc7fd1f8750d 100644 ---- a/drivers/reset/reset-spacemit.c -+++ b/drivers/reset/reset-spacemit.c -@@ -278,7 +278,7 @@ static int spacemit_reset_probe(struct auxiliary_device *adev, - - #define K1_AUX_DEV_ID(_unit) \ - { \ -- .name = "spacemit_ccu_k1." #_unit "-reset", \ -+ .name = "spacemit_ccu.k1-" #_unit "-reset", \ - .driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ - } - --- -2.53.0 - diff --git a/SPECS/linux-lts/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch b/SPECS/linux-lts/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch new file mode 100644 index 0000000000..8ce677d1e4 --- /dev/null +++ b/SPECS/linux-lts/0119-UPSTREAM-clk-spacemit-k3-extract-common-header.patch @@ -0,0 +1,299 @@ +From 22c56093a5cbcc8d011f81d4523ee8160d5caa5f Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Sat, 20 Dec 2025 21:28:15 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: extract common header + +Extracting common header file, which will be shared by clock and reset +drivers. So will make it easy to add reset driver for K3 SoC later. + +Link: https://lore.kernel.org/r/20260108-k3-clk-v5-4-42a11b74ad58@gentoo.org +Signed-off-by: Yixun Lan +(cherry picked from commit 091d19cc24018f2bd783e932fb2403cb7a2bdb3c) +Signed-off-by: Han Gao +--- + include/soc/spacemit/k3-syscon.h | 273 +++++++++++++++++++++++++++++++ + 1 file changed, 273 insertions(+) + create mode 100644 include/soc/spacemit/k3-syscon.h + +diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h +new file mode 100644 +index 000000000000..0299bea065a0 +--- /dev/null ++++ b/include/soc/spacemit/k3-syscon.h +@@ -0,0 +1,273 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* SpacemiT clock and reset driver definitions for the K3 SoC */ ++ ++#ifndef __SOC_K3_SYSCON_H__ ++#define __SOC_K3_SYSCON_H__ ++ ++#include "ccu.h" ++ ++/* APBS register offset */ ++#define APBS_PLL1_SWCR1 0x100 ++#define APBS_PLL1_SWCR2 0x104 ++#define APBS_PLL1_SWCR3 0x108 ++#define APBS_PLL2_SWCR1 0x118 ++#define APBS_PLL2_SWCR2 0x11c ++#define APBS_PLL2_SWCR3 0x120 ++#define APBS_PLL3_SWCR1 0x124 ++#define APBS_PLL3_SWCR2 0x128 ++#define APBS_PLL3_SWCR3 0x12c ++#define APBS_PLL4_SWCR1 0x130 ++#define APBS_PLL4_SWCR2 0x134 ++#define APBS_PLL4_SWCR3 0x138 ++#define APBS_PLL5_SWCR1 0x13c ++#define APBS_PLL5_SWCR2 0x140 ++#define APBS_PLL5_SWCR3 0x144 ++#define APBS_PLL6_SWCR1 0x148 ++#define APBS_PLL6_SWCR2 0x14c ++#define APBS_PLL6_SWCR3 0x150 ++#define APBS_PLL7_SWCR1 0x158 ++#define APBS_PLL7_SWCR2 0x15c ++#define APBS_PLL7_SWCR3 0x160 ++#define APBS_PLL8_SWCR1 0x180 ++#define APBS_PLL8_SWCR2 0x184 ++#define APBS_PLL8_SWCR3 0x188 ++ ++/* MPMU register offset */ ++#define MPMU_FCCR 0x0008 ++#define MPMU_POSR 0x0010 ++#define POSR_PLL1_LOCK BIT(24) ++#define POSR_PLL2_LOCK BIT(25) ++#define POSR_PLL3_LOCK BIT(26) ++#define POSR_PLL4_LOCK BIT(27) ++#define POSR_PLL5_LOCK BIT(28) ++#define POSR_PLL6_LOCK BIT(29) ++#define POSR_PLL7_LOCK BIT(30) ++#define POSR_PLL8_LOCK BIT(31) ++#define MPMU_SUCCR 0x0014 ++#define MPMU_ISCCR 0x0044 ++#define MPMU_WDTPCR 0x0200 ++#define MPMU_RIPCCR 0x0210 ++#define MPMU_ACGR 0x1024 ++#define MPMU_APBCSCR 0x1050 ++#define MPMU_SUCCR_1 0x10b0 ++ ++#define MPMU_I2S0_SYSCLK 0x1100 ++#define MPMU_I2S2_SYSCLK 0x1104 ++#define MPMU_I2S3_SYSCLK 0x1108 ++#define MPMU_I2S4_SYSCLK 0x110c ++#define MPMU_I2S5_SYSCLK 0x1110 ++#define MPMU_I2S_SYSCLK_CTRL 0x1114 ++ ++/* APBC register offset */ ++#define APBC_UART0_CLK_RST 0x00 ++#define APBC_UART2_CLK_RST 0x04 ++#define APBC_GPIO_CLK_RST 0x08 ++#define APBC_PWM0_CLK_RST 0x0c ++#define APBC_PWM1_CLK_RST 0x10 ++#define APBC_PWM2_CLK_RST 0x14 ++#define APBC_PWM3_CLK_RST 0x18 ++#define APBC_TWSI8_CLK_RST 0x20 ++#define APBC_UART3_CLK_RST 0x24 ++#define APBC_RTC_CLK_RST 0x28 ++#define APBC_TWSI0_CLK_RST 0x2c ++#define APBC_TWSI1_CLK_RST 0x30 ++#define APBC_TIMERS0_CLK_RST 0x34 ++#define APBC_TWSI2_CLK_RST 0x38 ++#define APBC_AIB_CLK_RST 0x3c ++#define APBC_TWSI4_CLK_RST 0x40 ++#define APBC_TIMERS1_CLK_RST 0x44 ++#define APBC_ONEWIRE_CLK_RST 0x48 ++#define APBC_TWSI5_CLK_RST 0x4c ++#define APBC_DRO_CLK_RST 0x58 ++#define APBC_IR0_CLK_RST 0x5c ++#define APBC_IR1_CLK_RST 0x1c ++#define APBC_TWSI6_CLK_RST 0x60 ++#define APBC_COUNTER_CLK_SEL 0x64 ++#define APBC_TSEN_CLK_RST 0x6c ++#define APBC_UART4_CLK_RST 0x70 ++#define APBC_UART5_CLK_RST 0x74 ++#define APBC_UART6_CLK_RST 0x78 ++#define APBC_SSP3_CLK_RST 0x7c ++#define APBC_SSPA0_CLK_RST 0x80 ++#define APBC_SSPA1_CLK_RST 0x84 ++#define APBC_SSPA2_CLK_RST 0x88 ++#define APBC_SSPA3_CLK_RST 0x8c ++#define APBC_IPC_AP2AUD_CLK_RST 0x90 ++#define APBC_UART7_CLK_RST 0x94 ++#define APBC_UART8_CLK_RST 0x98 ++#define APBC_UART9_CLK_RST 0x9c ++#define APBC_CAN0_CLK_RST 0xa0 ++#define APBC_CAN1_CLK_RST 0xa4 ++#define APBC_PWM4_CLK_RST 0xa8 ++#define APBC_PWM5_CLK_RST 0xac ++#define APBC_PWM6_CLK_RST 0xb0 ++#define APBC_PWM7_CLK_RST 0xb4 ++#define APBC_PWM8_CLK_RST 0xb8 ++#define APBC_PWM9_CLK_RST 0xbc ++#define APBC_PWM10_CLK_RST 0xc0 ++#define APBC_PWM11_CLK_RST 0xc4 ++#define APBC_PWM12_CLK_RST 0xc8 ++#define APBC_PWM13_CLK_RST 0xcc ++#define APBC_PWM14_CLK_RST 0xd0 ++#define APBC_PWM15_CLK_RST 0xd4 ++#define APBC_PWM16_CLK_RST 0xd8 ++#define APBC_PWM17_CLK_RST 0xdc ++#define APBC_PWM18_CLK_RST 0xe0 ++#define APBC_PWM19_CLK_RST 0xe4 ++#define APBC_TIMERS2_CLK_RST 0x11c ++#define APBC_TIMERS3_CLK_RST 0x120 ++#define APBC_TIMERS4_CLK_RST 0x124 ++#define APBC_TIMERS5_CLK_RST 0x128 ++#define APBC_TIMERS6_CLK_RST 0x12c ++#define APBC_TIMERS7_CLK_RST 0x130 ++ ++#define APBC_CAN2_CLK_RST 0x148 ++#define APBC_CAN3_CLK_RST 0x14c ++#define APBC_CAN4_CLK_RST 0x150 ++#define APBC_UART10_CLK_RST 0x154 ++#define APBC_SSP0_CLK_RST 0x158 ++#define APBC_SSP1_CLK_RST 0x15c ++#define APBC_SSPA4_CLK_RST 0x160 ++#define APBC_SSPA5_CLK_RST 0x164 ++ ++/* APMU register offset */ ++#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 ++#define APMU_ISP_CLK_RES_CTRL 0x038 ++#define APMU_PMU_CLK_GATE_CTRL 0x040 ++#define APMU_LCD_CLK_RES_CTRL1 0x044 ++#define APMU_LCD_SPI_CLK_RES_CTRL 0x048 ++#define APMU_LCD_CLK_RES_CTRL2 0x04c ++#define APMU_CCIC_CLK_RES_CTRL 0x050 ++#define APMU_SDH0_CLK_RES_CTRL 0x054 ++#define APMU_SDH1_CLK_RES_CTRL 0x058 ++#define APMU_USB_CLK_RES_CTRL 0x05c ++#define APMU_QSPI_CLK_RES_CTRL 0x060 ++#define APMU_DMA_CLK_RES_CTRL 0x064 ++#define APMU_AES_CLK_RES_CTRL 0x068 ++#define APMU_MCB_CLK_RES_CTRL 0x06c ++#define APMU_VPU_CLK_RES_CTRL 0x0a4 ++#define APMU_DTC_CLK_RES_CTRL 0x0ac ++#define APMU_GPU_CLK_RES_CTRL 0x0cc ++#define APMU_SDH2_CLK_RES_CTRL 0x0e0 ++#define APMU_PMUA_MC_CTRL 0x0e8 ++#define APMU_PMU_CC2_AP 0x100 ++#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 ++#define APMU_UCIE_CTRL 0x11c ++#define APMU_RCPU_CLK_RES_CTRL 0x14c ++#define APMU_TOP_DCLK_CTRL 0x158 ++#define APMU_LCD_EDP_CTRL 0x23c ++#define APMU_UFS_CLK_RES_CTRL 0x268 ++#define APMU_LCD_CLK_RES_CTRL3 0x26c ++#define APMU_LCD_CLK_RES_CTRL4 0x270 ++#define APMU_LCD_CLK_RES_CTRL5 0x274 ++#define APMU_CCI550_CLK_CTRL 0x300 ++#define APMU_ACLK_CLK_CTRL 0x388 ++#define APMU_CPU_C0_CLK_CTRL 0x38C ++#define APMU_CPU_C1_CLK_CTRL 0x390 ++#define APMU_CPU_C2_CLK_CTRL 0x394 ++#define APMU_CPU_C3_CLK_CTRL 0x208 ++#define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 ++#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 ++#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 ++#define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 ++#define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 ++#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 ++#define APMU_EMAC1_CLK_RES_CTRL 0x3ec ++#define APMU_EMAC2_CLK_RES_CTRL 0x248 ++#define APMU_ESPI_CLK_RES_CTRL 0x240 ++#define APMU_SNR_ISIM_VCLK_CTRL 0x3f8 ++ ++/* DCIU register offsets */ ++#define DCIU_DMASYS_CLK_EN 0x234 ++#define DCIU_DMASYS_SDMA_CLK_EN 0x238 ++#define DCIU_C2_TCM_PIPE_CLK 0x244 ++#define DCIU_C3_TCM_PIPE_CLK 0x248 ++ ++#define DCIU_DMASYS_S0_RSTN 0x204 ++#define DCIU_DMASYS_S1_RSTN 0x208 ++#define DCIU_DMASYS_A0_RSTN 0x20C ++#define DCIU_DMASYS_A1_RSTN 0x210 ++#define DCIU_DMASYS_A2_RSTN 0x214 ++#define DCIU_DMASYS_A3_RSTN 0x218 ++#define DCIU_DMASYS_A4_RSTN 0x21C ++#define DCIU_DMASYS_A5_RSTN 0x220 ++#define DCIU_DMASYS_A6_RSTN 0x224 ++#define DCIU_DMASYS_A7_RSTN 0x228 ++#define DCIU_DMASYS_RSTN 0x22C ++#define DCIU_DMASYS_SDMA_RSTN 0x230 ++ ++/* RCPU SYSCTRL register offsets */ ++#define RCPU_CAN_CLK_RST 0x4c ++#define RCPU_CAN1_CLK_RST 0xF0 ++#define RCPU_CAN2_CLK_RST 0xF4 ++#define RCPU_CAN3_CLK_RST 0xF8 ++#define RCPU_CAN4_CLK_RST 0xFC ++#define RCPU_IRC_CLK_RST 0x48 ++#define RCPU_IRC1_CLK_RST 0xEC ++#define RCPU_GMAC_CLK_RST 0xE4 ++#define RCPU_ESPI_CLK_RST 0xDC ++#define RCPU_AUDIO_I2S0_SYS_CLK_CTRL 0x70 ++#define RCPU_AUDIO_I2S1_SYS_CLK_CTRL 0x44 ++ ++/* RCPU UARTCTRL register offsets */ ++#define RCPU1_UART0_CLK_RST 0x00 ++#define RCPU1_UART1_CLK_RST 0x04 ++#define RCPU1_UART2_CLK_RST 0x08 ++#define RCPU1_UART3_CLK_RST 0x0c ++#define RCPU1_UART4_CLK_RST 0x10 ++#define RCPU1_UART5_CLK_RST 0x14 ++ ++/* RCPU I2SCTRL register offsets */ ++#define RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL 0x60 ++#define RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL 0x64 ++#define RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL 0x68 ++#define RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL 0x6C ++ ++#define RCPU2_AUDIO_I2S2_SYS_CLK_CTRL 0x44 ++#define RCPU2_AUDIO_I2S3_SYS_CLK_CTRL 0x54 ++ ++/* RCPU SPICTRL register offsets */ ++#define RCPU3_SSP0_CLK_RST 0x00 ++#define RCPU3_SSP1_CLK_RST 0x04 ++#define RCPU3_PWR_SSP_CLK_RST 0x08 ++ ++/* RCPU I2CCTRL register offsets */ ++#define RCPU4_I2C0_CLK_RST 0x00 ++#define RCPU4_I2C1_CLK_RST 0x04 ++#define RCPU4_PWR_I2C_CLK_RST 0x08 ++ ++/* RPMU register offsets */ ++#define RCPU5_AON_PER_CLK_RST_CTRL 0x2C ++#define RCPU5_TIMER1_CLK_RST 0x4C ++#define RCPU5_TIMER2_CLK_RST 0x70 ++#define RCPU5_TIMER3_CLK_RST 0x78 ++#define RCPU5_TIMER4_CLK_RST 0x7C ++#define RCPU5_GPIO_AND_EDGE_CLK_RST 0x74 ++#define RCPU5_RCPU_BUS_CLK_CTRL 0xC0 ++#define RCPU5_RT24_CORE0_CLK_CTRL 0xC4 ++#define RCPU5_RT24_CORE1_CLK_CTRL 0xC8 ++#define RCPU5_RT24_CORE0_SW_RESET 0xCC ++#define RCPU5_RT24_CORE1_SW_RESET 0xD0 ++ ++/* RCPU PWMCTRL register offsets */ ++#define RCPU6_PWM0_CLK_RST 0x00 ++#define RCPU6_PWM1_CLK_RST 0x04 ++#define RCPU6_PWM2_CLK_RST 0x08 ++#define RCPU6_PWM3_CLK_RST 0x0c ++#define RCPU6_PWM4_CLK_RST 0x10 ++#define RCPU6_PWM5_CLK_RST 0x14 ++#define RCPU6_PWM6_CLK_RST 0x18 ++#define RCPU6_PWM7_CLK_RST 0x1c ++#define RCPU6_PWM8_CLK_RST 0x20 ++#define RCPU6_PWM9_CLK_RST 0x24 ++ ++/* APBC2 SEC register offsets */ ++#define APBC2_UART1_CLK_RST 0x00 ++#define APBC2_SSP2_CLK_RST 0x04 ++#define APBC2_TWSI3_CLK_RST 0x08 ++#define APBC2_RTC_CLK_RST 0x0c ++#define APBC2_TIMERS_CLK_RST 0x10 ++#define APBC2_GPIO_CLK_RST 0x1c ++ ++#endif /* __SOC_K3_SYSCON_H__ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0119-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch b/SPECS/linux-lts/0119-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch deleted file mode 100644 index 5b56ed2c06..0000000000 --- a/SPECS/linux-lts/0119-UPSTREAM-dt-bindings-soc-spacemit-k3-add-clock-suppo.patch +++ /dev/null @@ -1,519 +0,0 @@ -From 57bc7378dba997a6f4714c6180bf65bbaf53dccb Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sat, 1 Nov 2025 20:56:42 +0800 -Subject: [PATCH 119/467] UPSTREAM: dt-bindings: soc: spacemit: k3: add clock - support - -Add compatible strings for clock drivers to support Spacemit K3 SoC, -also includes all the defined clock IDs. - -The SpacemiT K3 SoC clock IP is scattered over several different blocks, -which are APBC, APBS, APMU, DCIU, MPMU, all of them are capable of -generating clock and reset signals. APMU and MPMU have additional Power -Domain management functionality. - -Following is a brief list that shows devices managed in each block: - -APBC: UART, GPIO, PWM, SPI, TIMER, I2S, IR, DR, TSEN, IPC, CAN -APBS: various PPL clocks control -APMU: CCI, CPU, CSI, ISP, LCD, USB, QSPI, DMA, VPU, GPU, DSI, PCIe, EMAC.. -DCID: SRAM, DMA, TCM -MPMU: various PLL1 derived clocks, UART, WATCHDOG, I2S - -Link: https://lore.kernel.org/r/20260108-k3-clk-v5-1-42a11b74ad58@gentoo.org -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Yixun Lan -(cherry picked from commit efe897b557e211a09f51d749eae5eca933e8bf56) -Signed-off-by: Han Gao ---- - .../bindings/clock/spacemit,k1-pll.yaml | 9 +- - .../soc/spacemit/spacemit,k1-syscon.yaml | 14 +- - .../dt-bindings/clock/spacemit,k3-clocks.h | 390 ++++++++++++++++++ - 3 files changed, 408 insertions(+), 5 deletions(-) - create mode 100644 include/dt-bindings/clock/spacemit,k3-clocks.h - -diff --git a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml -index 06bafd68c00a..cddf6a56dac0 100644 ---- a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml -+++ b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml -@@ -4,14 +4,16 @@ - $id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml# - $schema: http://devicetree.org/meta-schemas/core.yaml# - --title: SpacemiT K1 PLL -+title: SpacemiT K1/K3 PLL - - maintainers: - - Haylen Chu - - properties: - compatible: -- const: spacemit,k1-pll -+ enum: -+ - spacemit,k1-pll -+ - spacemit,k3-pll - - reg: - maxItems: 1 -@@ -28,7 +30,8 @@ properties: - "#clock-cells": - const: 1 - description: -- See for valid indices. -+ For K1 SoC, check for valid indices. -+ For K3 SoC, check for valid indices. - - required: - - compatible -diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml -index 133a391ee68c..d87131da30bc 100644 ---- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml -+++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml -@@ -4,7 +4,7 @@ - $id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml# - $schema: http://devicetree.org/meta-schemas/core.yaml# - --title: SpacemiT K1 SoC System Controller -+title: SpacemiT K1/K3 SoC System Controller - - maintainers: - - Haylen Chu -@@ -22,6 +22,10 @@ properties: - - spacemit,k1-syscon-rcpu - - spacemit,k1-syscon-rcpu2 - - spacemit,k1-syscon-apbc2 -+ - spacemit,k3-syscon-apbc -+ - spacemit,k3-syscon-apmu -+ - spacemit,k3-syscon-dciu -+ - spacemit,k3-syscon-mpmu - - reg: - maxItems: 1 -@@ -39,7 +43,8 @@ properties: - "#clock-cells": - const: 1 - description: -- See for valid indices. -+ For K1 SoC, check for valid indices. -+ For K3 SoC, check for valid indices. - - "#power-domain-cells": - const: 1 -@@ -60,6 +65,8 @@ allOf: - enum: - - spacemit,k1-syscon-apmu - - spacemit,k1-syscon-mpmu -+ - spacemit,k3-syscon-apmu -+ - spacemit,k3-syscon-mpmu - then: - required: - - "#power-domain-cells" -@@ -74,6 +81,9 @@ allOf: - - spacemit,k1-syscon-apbc - - spacemit,k1-syscon-apmu - - spacemit,k1-syscon-mpmu -+ - spacemit,k3-syscon-apbc -+ - spacemit,k3-syscon-apmu -+ - spacemit,k3-syscon-mpmu - then: - required: - - clocks -diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h -new file mode 100644 -index 000000000000..b22336f3ae40 ---- /dev/null -+++ b/include/dt-bindings/clock/spacemit,k3-clocks.h -@@ -0,0 +1,390 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd -+ */ -+ -+#ifndef _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ -+#define _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ -+ -+/* APBS (PLL) clocks */ -+#define CLK_PLL1 0 -+#define CLK_PLL2 1 -+#define CLK_PLL3 2 -+#define CLK_PLL4 3 -+#define CLK_PLL5 4 -+#define CLK_PLL6 5 -+#define CLK_PLL7 6 -+#define CLK_PLL8 7 -+#define CLK_PLL1_D2 8 -+#define CLK_PLL1_D3 9 -+#define CLK_PLL1_D4 10 -+#define CLK_PLL1_D5 11 -+#define CLK_PLL1_D6 12 -+#define CLK_PLL1_D7 13 -+#define CLK_PLL1_D8 14 -+#define CLK_PLL1_DX 15 -+#define CLK_PLL1_D64 16 -+#define CLK_PLL1_D10_AUD 17 -+#define CLK_PLL1_D100_AUD 18 -+#define CLK_PLL2_D1 19 -+#define CLK_PLL2_D2 20 -+#define CLK_PLL2_D3 21 -+#define CLK_PLL2_D4 22 -+#define CLK_PLL2_D5 23 -+#define CLK_PLL2_D6 24 -+#define CLK_PLL2_D7 25 -+#define CLK_PLL2_D8 26 -+#define CLK_PLL2_66 27 -+#define CLK_PLL2_33 28 -+#define CLK_PLL2_50 29 -+#define CLK_PLL2_25 30 -+#define CLK_PLL2_20 31 -+#define CLK_PLL2_D24_125 32 -+#define CLK_PLL2_D120_25 33 -+#define CLK_PLL3_D1 34 -+#define CLK_PLL3_D2 35 -+#define CLK_PLL3_D3 36 -+#define CLK_PLL3_D4 37 -+#define CLK_PLL3_D5 38 -+#define CLK_PLL3_D6 39 -+#define CLK_PLL3_D7 40 -+#define CLK_PLL3_D8 41 -+#define CLK_PLL4_D1 42 -+#define CLK_PLL4_D2 43 -+#define CLK_PLL4_D3 44 -+#define CLK_PLL4_D4 45 -+#define CLK_PLL4_D5 46 -+#define CLK_PLL4_D6 47 -+#define CLK_PLL4_D7 48 -+#define CLK_PLL4_D8 49 -+#define CLK_PLL5_D1 50 -+#define CLK_PLL5_D2 51 -+#define CLK_PLL5_D3 52 -+#define CLK_PLL5_D4 53 -+#define CLK_PLL5_D5 54 -+#define CLK_PLL5_D6 55 -+#define CLK_PLL5_D7 56 -+#define CLK_PLL5_D8 57 -+#define CLK_PLL6_D1 58 -+#define CLK_PLL6_D2 59 -+#define CLK_PLL6_D3 60 -+#define CLK_PLL6_D4 61 -+#define CLK_PLL6_D5 62 -+#define CLK_PLL6_D6 63 -+#define CLK_PLL6_D7 64 -+#define CLK_PLL6_D8 65 -+#define CLK_PLL6_80 66 -+#define CLK_PLL6_40 67 -+#define CLK_PLL6_20 68 -+#define CLK_PLL7_D1 69 -+#define CLK_PLL7_D2 70 -+#define CLK_PLL7_D3 71 -+#define CLK_PLL7_D4 72 -+#define CLK_PLL7_D5 73 -+#define CLK_PLL7_D6 74 -+#define CLK_PLL7_D7 75 -+#define CLK_PLL7_D8 76 -+#define CLK_PLL8_D1 77 -+#define CLK_PLL8_D2 78 -+#define CLK_PLL8_D3 79 -+#define CLK_PLL8_D4 80 -+#define CLK_PLL8_D5 81 -+#define CLK_PLL8_D6 82 -+#define CLK_PLL8_D7 83 -+#define CLK_PLL8_D8 84 -+ -+/* MPMU clocks */ -+#define CLK_MPMU_PLL1_307P2 0 -+#define CLK_MPMU_PLL1_76P8 1 -+#define CLK_MPMU_PLL1_61P44 2 -+#define CLK_MPMU_PLL1_153P6 3 -+#define CLK_MPMU_PLL1_102P4 4 -+#define CLK_MPMU_PLL1_51P2 5 -+#define CLK_MPMU_PLL1_51P2_AP 6 -+#define CLK_MPMU_PLL1_57P6 7 -+#define CLK_MPMU_PLL1_25P6 8 -+#define CLK_MPMU_PLL1_12P8 9 -+#define CLK_MPMU_PLL1_12P8_WDT 10 -+#define CLK_MPMU_PLL1_6P4 11 -+#define CLK_MPMU_PLL1_3P2 12 -+#define CLK_MPMU_PLL1_1P6 13 -+#define CLK_MPMU_PLL1_0P8 14 -+#define CLK_MPMU_PLL1_409P6 15 -+#define CLK_MPMU_PLL1_204P8 16 -+#define CLK_MPMU_PLL1_491 17 -+#define CLK_MPMU_PLL1_245P76 18 -+#define CLK_MPMU_PLL1_614 19 -+#define CLK_MPMU_PLL1_47P26 20 -+#define CLK_MPMU_PLL1_31P5 21 -+#define CLK_MPMU_PLL1_819 22 -+#define CLK_MPMU_PLL1_1228 23 -+#define CLK_MPMU_APB 24 -+#define CLK_MPMU_SLOW_UART 25 -+#define CLK_MPMU_SLOW_UART1 26 -+#define CLK_MPMU_SLOW_UART2 27 -+#define CLK_MPMU_WDT 28 -+#define CLK_MPMU_WDT_BUS 29 -+#define CLK_MPMU_RIPC 30 -+#define CLK_MPMU_I2S_153P6 31 -+#define CLK_MPMU_I2S_153P6_BASE 32 -+#define CLK_MPMU_I2S_SYSCLK_SRC 33 -+#define CLK_MPMU_I2S1_SYSCLK 34 -+#define CLK_MPMU_I2S_BCLK 35 -+#define CLK_MPMU_I2S0_SYSCLK_SEL 36 -+#define CLK_MPMU_I2S2_SYSCLK_SEL 37 -+#define CLK_MPMU_I2S3_SYSCLK_SEL 38 -+#define CLK_MPMU_I2S4_SYSCLK_SEL 39 -+#define CLK_MPMU_I2S5_SYSCLK_SEL 40 -+#define CLK_MPMU_I2S0_SYSCLK_DIV 41 -+#define CLK_MPMU_I2S2_SYSCLK_DIV 42 -+#define CLK_MPMU_I2S3_SYSCLK_DIV 43 -+#define CLK_MPMU_I2S4_SYSCLK_DIV 44 -+#define CLK_MPMU_I2S5_SYSCLK_DIV 45 -+#define CLK_MPMU_I2S0_SYSCLK 46 -+#define CLK_MPMU_I2S2_SYSCLK 47 -+#define CLK_MPMU_I2S3_SYSCLK 48 -+#define CLK_MPMU_I2S4_SYSCLK 49 -+#define CLK_MPMU_I2S5_SYSCLK 50 -+ -+/* APBC clocks */ -+#define CLK_APBC_UART0 0 -+#define CLK_APBC_UART2 1 -+#define CLK_APBC_UART3 2 -+#define CLK_APBC_UART4 3 -+#define CLK_APBC_UART5 4 -+#define CLK_APBC_UART6 5 -+#define CLK_APBC_UART7 6 -+#define CLK_APBC_UART8 7 -+#define CLK_APBC_UART9 8 -+#define CLK_APBC_UART10 9 -+#define CLK_APBC_UART0_BUS 10 -+#define CLK_APBC_UART2_BUS 11 -+#define CLK_APBC_UART3_BUS 12 -+#define CLK_APBC_UART4_BUS 13 -+#define CLK_APBC_UART5_BUS 14 -+#define CLK_APBC_UART6_BUS 15 -+#define CLK_APBC_UART7_BUS 16 -+#define CLK_APBC_UART8_BUS 17 -+#define CLK_APBC_UART9_BUS 18 -+#define CLK_APBC_UART10_BUS 19 -+#define CLK_APBC_GPIO 20 -+#define CLK_APBC_GPIO_BUS 21 -+#define CLK_APBC_PWM0 22 -+#define CLK_APBC_PWM1 23 -+#define CLK_APBC_PWM2 24 -+#define CLK_APBC_PWM3 25 -+#define CLK_APBC_PWM4 26 -+#define CLK_APBC_PWM5 27 -+#define CLK_APBC_PWM6 28 -+#define CLK_APBC_PWM7 29 -+#define CLK_APBC_PWM8 30 -+#define CLK_APBC_PWM9 31 -+#define CLK_APBC_PWM10 32 -+#define CLK_APBC_PWM11 33 -+#define CLK_APBC_PWM12 34 -+#define CLK_APBC_PWM13 35 -+#define CLK_APBC_PWM14 36 -+#define CLK_APBC_PWM15 37 -+#define CLK_APBC_PWM16 38 -+#define CLK_APBC_PWM17 39 -+#define CLK_APBC_PWM18 40 -+#define CLK_APBC_PWM19 41 -+#define CLK_APBC_PWM0_BUS 42 -+#define CLK_APBC_PWM1_BUS 43 -+#define CLK_APBC_PWM2_BUS 44 -+#define CLK_APBC_PWM3_BUS 45 -+#define CLK_APBC_PWM4_BUS 46 -+#define CLK_APBC_PWM5_BUS 47 -+#define CLK_APBC_PWM6_BUS 48 -+#define CLK_APBC_PWM7_BUS 49 -+#define CLK_APBC_PWM8_BUS 50 -+#define CLK_APBC_PWM9_BUS 51 -+#define CLK_APBC_PWM10_BUS 52 -+#define CLK_APBC_PWM11_BUS 53 -+#define CLK_APBC_PWM12_BUS 54 -+#define CLK_APBC_PWM13_BUS 55 -+#define CLK_APBC_PWM14_BUS 56 -+#define CLK_APBC_PWM15_BUS 57 -+#define CLK_APBC_PWM16_BUS 58 -+#define CLK_APBC_PWM17_BUS 59 -+#define CLK_APBC_PWM18_BUS 60 -+#define CLK_APBC_PWM19_BUS 61 -+#define CLK_APBC_SPI0_I2S_BCLK 62 -+#define CLK_APBC_SPI1_I2S_BCLK 63 -+#define CLK_APBC_SPI3_I2S_BCLK 64 -+#define CLK_APBC_SPI0 65 -+#define CLK_APBC_SPI1 66 -+#define CLK_APBC_SPI3 67 -+#define CLK_APBC_SPI0_BUS 68 -+#define CLK_APBC_SPI1_BUS 69 -+#define CLK_APBC_SPI3_BUS 70 -+#define CLK_APBC_RTC 71 -+#define CLK_APBC_RTC_BUS 72 -+#define CLK_APBC_TWSI0 73 -+#define CLK_APBC_TWSI1 74 -+#define CLK_APBC_TWSI2 75 -+#define CLK_APBC_TWSI4 76 -+#define CLK_APBC_TWSI5 77 -+#define CLK_APBC_TWSI6 78 -+#define CLK_APBC_TWSI8 79 -+#define CLK_APBC_TWSI0_BUS 80 -+#define CLK_APBC_TWSI1_BUS 81 -+#define CLK_APBC_TWSI2_BUS 82 -+#define CLK_APBC_TWSI4_BUS 83 -+#define CLK_APBC_TWSI5_BUS 84 -+#define CLK_APBC_TWSI6_BUS 85 -+#define CLK_APBC_TWSI8_BUS 86 -+#define CLK_APBC_TIMERS0 87 -+#define CLK_APBC_TIMERS1 88 -+#define CLK_APBC_TIMERS2 89 -+#define CLK_APBC_TIMERS3 90 -+#define CLK_APBC_TIMERS4 91 -+#define CLK_APBC_TIMERS5 92 -+#define CLK_APBC_TIMERS6 93 -+#define CLK_APBC_TIMERS7 94 -+#define CLK_APBC_TIMERS0_BUS 95 -+#define CLK_APBC_TIMERS1_BUS 96 -+#define CLK_APBC_TIMERS2_BUS 97 -+#define CLK_APBC_TIMERS3_BUS 98 -+#define CLK_APBC_TIMERS4_BUS 99 -+#define CLK_APBC_TIMERS5_BUS 100 -+#define CLK_APBC_TIMERS6_BUS 101 -+#define CLK_APBC_TIMERS7_BUS 102 -+#define CLK_APBC_AIB 103 -+#define CLK_APBC_AIB_BUS 104 -+#define CLK_APBC_ONEWIRE 105 -+#define CLK_APBC_ONEWIRE_BUS 106 -+#define CLK_APBC_I2S0_BCLK 107 -+#define CLK_APBC_I2S1_BCLK 108 -+#define CLK_APBC_I2S2_BCLK 109 -+#define CLK_APBC_I2S3_BCLK 110 -+#define CLK_APBC_I2S4_BCLK 111 -+#define CLK_APBC_I2S5_BCLK 112 -+#define CLK_APBC_I2S0 113 -+#define CLK_APBC_I2S1 114 -+#define CLK_APBC_I2S2 115 -+#define CLK_APBC_I2S3 116 -+#define CLK_APBC_I2S4 117 -+#define CLK_APBC_I2S5 118 -+#define CLK_APBC_I2S0_BUS 119 -+#define CLK_APBC_I2S1_BUS 120 -+#define CLK_APBC_I2S2_BUS 121 -+#define CLK_APBC_I2S3_BUS 122 -+#define CLK_APBC_I2S4_BUS 123 -+#define CLK_APBC_I2S5_BUS 124 -+#define CLK_APBC_DRO 125 -+#define CLK_APBC_IR0 126 -+#define CLK_APBC_IR1 127 -+#define CLK_APBC_TSEN 128 -+#define CLK_APBC_TSEN_BUS 129 -+#define CLK_APBC_IPC_AP2RCPU 130 -+#define CLK_APBC_IPC_AP2RCPU_BUS 131 -+#define CLK_APBC_CAN0 132 -+#define CLK_APBC_CAN1 133 -+#define CLK_APBC_CAN2 134 -+#define CLK_APBC_CAN3 135 -+#define CLK_APBC_CAN4 136 -+#define CLK_APBC_CAN0_BUS 137 -+#define CLK_APBC_CAN1_BUS 138 -+#define CLK_APBC_CAN2_BUS 139 -+#define CLK_APBC_CAN3_BUS 140 -+#define CLK_APBC_CAN4_BUS 141 -+ -+/* APMU clocks */ -+#define CLK_APMU_AXICLK 0 -+#define CLK_APMU_CCI550 1 -+#define CLK_APMU_CPU_C0_CORE 2 -+#define CLK_APMU_CPU_C1_CORE 3 -+#define CLK_APMU_CPU_C2_CORE 4 -+#define CLK_APMU_CPU_C3_CORE 5 -+#define CLK_APMU_CCIC2PHY 6 -+#define CLK_APMU_CCIC3PHY 7 -+#define CLK_APMU_CSI 8 -+#define CLK_APMU_ISP_BUS 9 -+#define CLK_APMU_D1P_1228P8 10 -+#define CLK_APMU_D1P_819P2 11 -+#define CLK_APMU_D1P_614P4 12 -+#define CLK_APMU_D1P_491P52 13 -+#define CLK_APMU_D1P_409P6 14 -+#define CLK_APMU_D1P_307P2 15 -+#define CLK_APMU_D1P_245P76 16 -+#define CLK_APMU_V2D 17 -+#define CLK_APMU_DSI_ESC 18 -+#define CLK_APMU_LCD_HCLK 19 -+#define CLK_APMU_LCD_DSC 20 -+#define CLK_APMU_LCD_PXCLK 21 -+#define CLK_APMU_LCD_MCLK 22 -+#define CLK_APMU_CCIC_4X 23 -+#define CLK_APMU_CCIC1PHY 24 -+#define CLK_APMU_SC2_HCLK 25 -+#define CLK_APMU_SDH_AXI 26 -+#define CLK_APMU_SDH0 27 -+#define CLK_APMU_SDH1 28 -+#define CLK_APMU_SDH2 29 -+#define CLK_APMU_USB2_BUS 30 -+#define CLK_APMU_USB3_PORTA_BUS 31 -+#define CLK_APMU_USB3_PORTB_BUS 32 -+#define CLK_APMU_USB3_PORTC_BUS 33 -+#define CLK_APMU_USB3_PORTD_BUS 34 -+#define CLK_APMU_QSPI 35 -+#define CLK_APMU_QSPI_BUS 36 -+#define CLK_APMU_DMA 37 -+#define CLK_APMU_AES_WTM 38 -+#define CLK_APMU_VPU 39 -+#define CLK_APMU_DTC 40 -+#define CLK_APMU_GPU 41 -+#define CLK_APMU_MC_AHB 42 -+#define CLK_APMU_TOP_DCLK 43 -+#define CLK_APMU_UCIE 44 -+#define CLK_APMU_UCIE_SBCLK 45 -+#define CLK_APMU_RCPU 46 -+#define CLK_APMU_DSI4LN2_DSI_ESC 47 -+#define CLK_APMU_DSI4LN2_LCD_DSC 48 -+#define CLK_APMU_DSI4LN2_LCD_PXCLK 49 -+#define CLK_APMU_DSI4LN2_LCD_MCLK 50 -+#define CLK_APMU_DSI4LN2_DPU_ACLK 51 -+#define CLK_APMU_DPU_ACLK 52 -+#define CLK_APMU_UFS_ACLK 53 -+#define CLK_APMU_EDP0_PXCLK 54 -+#define CLK_APMU_EDP1_PXCLK 55 -+#define CLK_APMU_PCIE_PORTA_MSTE 56 -+#define CLK_APMU_PCIE_PORTA_SLV 57 -+#define CLK_APMU_PCIE_PORTB_MSTE 58 -+#define CLK_APMU_PCIE_PORTB_SLV 59 -+#define CLK_APMU_PCIE_PORTC_MSTE 60 -+#define CLK_APMU_PCIE_PORTC_SLV 61 -+#define CLK_APMU_PCIE_PORTD_MSTE 62 -+#define CLK_APMU_PCIE_PORTD_SLV 63 -+#define CLK_APMU_PCIE_PORTE_MSTE 64 -+#define CLK_APMU_PCIE_PORTE_SLV 65 -+#define CLK_APMU_EMAC0_BUS 66 -+#define CLK_APMU_EMAC0_REF 67 -+#define CLK_APMU_EMAC0_1588 68 -+#define CLK_APMU_EMAC0_RGMII_TX 69 -+#define CLK_APMU_EMAC1_BUS 70 -+#define CLK_APMU_EMAC1_REF 71 -+#define CLK_APMU_EMAC1_1588 72 -+#define CLK_APMU_EMAC1_RGMII_TX 73 -+#define CLK_APMU_EMAC2_BUS 74 -+#define CLK_APMU_EMAC2_REF 75 -+#define CLK_APMU_EMAC2_1588 76 -+#define CLK_APMU_EMAC2_RGMII_TX 77 -+#define CLK_APMU_ESPI_SCLK_SRC 78 -+#define CLK_APMU_ESPI_SCLK 79 -+#define CLK_APMU_ESPI_MCLK 80 -+#define CLK_APMU_CAM_SRC1 81 -+#define CLK_APMU_CAM_SRC2 82 -+#define CLK_APMU_CAM_SRC3 83 -+#define CLK_APMU_CAM_SRC4 84 -+#define CLK_APMU_ISIM_VCLK0 85 -+#define CLK_APMU_ISIM_VCLK1 86 -+#define CLK_APMU_ISIM_VCLK2 87 -+#define CLK_APMU_ISIM_VCLK3 88 -+ -+/* DCIU clocks */ -+#define CLK_DCIU_HDMA 0 -+#define CLK_DCIU_DMA350 1 -+#define CLK_DCIU_C2_TCM_PIPE 2 -+#define CLK_DCIU_C3_TCM_PIPE 3 -+ -+#endif /* _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0120-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch b/SPECS/linux-lts/0120-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch deleted file mode 100644 index 5c1f5ce5c7..0000000000 --- a/SPECS/linux-lts/0120-UPSTREAM-clk-spacemit-ccu_mix-add-inverted-enable-ga.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 963fb293372d266d46bee16fa3f3b74d277c8831 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 31 Oct 2025 20:40:46 +0800 -Subject: [PATCH 120/467] UPSTREAM: clk: spacemit: ccu_mix: add inverted enable - gate clock - -K3 SoC has the clock IP which support to write value 0 for enabling the -clock, while write 1 for disabling it, thus the enable BIT is inverted. -So, introduce a flag to support the inverted gate clock. - -Link: https://lore.kernel.org/r/20260108-k3-clk-v5-2-42a11b74ad58@gentoo.org -Signed-off-by: Yixun Lan -(cherry picked from commit ace73b7e27633ec770cfb24cd4ff42c24815a9aa) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu_mix.c | 12 ++++++++---- - drivers/clk/spacemit/ccu_mix.h | 12 ++++++++++++ - 2 files changed, 20 insertions(+), 4 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu_mix.c b/drivers/clk/spacemit/ccu_mix.c -index 9a3fc9ea1ce5..a8b407049bf4 100644 ---- a/drivers/clk/spacemit/ccu_mix.c -+++ b/drivers/clk/spacemit/ccu_mix.c -@@ -16,17 +16,19 @@ - static void ccu_gate_disable(struct clk_hw *hw) - { - struct ccu_mix *mix = hw_to_ccu_mix(hw); -+ struct ccu_gate_config *gate = &mix->gate; -+ u32 val = gate->inverted ? gate->mask : 0; - -- ccu_update(&mix->common, ctrl, mix->gate.mask, 0); -+ ccu_update(&mix->common, ctrl, gate->mask, val); - } - - static int ccu_gate_enable(struct clk_hw *hw) - { - struct ccu_mix *mix = hw_to_ccu_mix(hw); - struct ccu_gate_config *gate = &mix->gate; -+ u32 val = gate->inverted ? 0 : gate->mask; - -- ccu_update(&mix->common, ctrl, gate->mask, gate->mask); -- -+ ccu_update(&mix->common, ctrl, gate->mask, val); - return 0; - } - -@@ -34,8 +36,10 @@ static int ccu_gate_is_enabled(struct clk_hw *hw) - { - struct ccu_mix *mix = hw_to_ccu_mix(hw); - struct ccu_gate_config *gate = &mix->gate; -+ u32 tmp = ccu_read(&mix->common, ctrl) & gate->mask; -+ u32 val = gate->inverted ? 0 : gate->mask; - -- return (ccu_read(&mix->common, ctrl) & gate->mask) == gate->mask; -+ return !!(tmp == val); - } - - static unsigned long ccu_factor_recalc_rate(struct clk_hw *hw, -diff --git a/drivers/clk/spacemit/ccu_mix.h b/drivers/clk/spacemit/ccu_mix.h -index 54d40cd39b27..8a70cf151461 100644 ---- a/drivers/clk/spacemit/ccu_mix.h -+++ b/drivers/clk/spacemit/ccu_mix.h -@@ -16,9 +16,11 @@ - * - * @mask: Mask to enable the gate. Some clocks may have more than one bit - * set in this field. -+ * @inverted: Enable bit is inverted, 1 - disable clock, 0 - enable clock - */ - struct ccu_gate_config { - u32 mask; -+ bool inverted; - }; - - struct ccu_factor_config { -@@ -48,6 +50,7 @@ struct ccu_mix { - #define CCU_FACTOR_INIT(_div, _mul) { .div = _div, .mul = _mul } - #define CCU_MUX_INIT(_shift, _width) { .shift = _shift, .width = _width } - #define CCU_DIV_INIT(_shift, _width) { .shift = _shift, .width = _width } -+#define CCU_GATE_FLAGS_INIT(_mask, _inverted) { .mask = _mask, .inverted = _inverted } - - #define CCU_PARENT_HW(_parent) { .hw = &_parent.common.hw } - #define CCU_PARENT_NAME(_name) { .fw_name = #_name } -@@ -101,6 +104,15 @@ static struct ccu_mix _name = { \ - } \ - } - -+#define CCU_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _inverted, _flags) \ -+static struct ccu_mix _name = { \ -+ .gate = CCU_GATE_FLAGS_INIT(_mask_gate, _inverted), \ -+ .common = { \ -+ .reg_ctrl = _reg_ctrl, \ -+ CCU_MIX_INITHW(_name, _parent, spacemit_ccu_gate_ops, _flags), \ -+ } \ -+} -+ - #define CCU_FACTOR_GATE_FLAGS_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \ - _mul, _flags) \ - static struct ccu_mix _name = { \ --- -2.53.0 - diff --git a/SPECS/linux-lts/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch b/SPECS/linux-lts/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch new file mode 100644 index 0000000000..ca7b6c2396 --- /dev/null +++ b/SPECS/linux-lts/0120-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch @@ -0,0 +1,1541 @@ +From 878e4e3217cc3b8b51d6d5480b8c6c8120d47144 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Sun, 2 Nov 2025 21:17:17 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: add the clock tree + +Add clock support to SpacemiT K3 SoC, the clock tree consist of several +blocks which are APBC, APBS, APMU, DCIU, MPUM. + +Link: https://lore.kernel.org/r/20260108-k3-clk-v5-5-42a11b74ad58@gentoo.org +Signed-off-by: Yixun Lan +(cherry picked from commit e371a77255b837f5d64c9d2520f87e41ea5350b9) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/Kconfig | 6 + + drivers/clk/spacemit/Makefile | 3 + + drivers/clk/spacemit/ccu-k3.c | 1487 +++++++++++++++++++++++++++++++++ + 3 files changed, 1496 insertions(+) + create mode 100644 drivers/clk/spacemit/ccu-k3.c + +diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig +index 3351e8bc801d..4ebe6aaa1980 100644 +--- a/drivers/clk/spacemit/Kconfig ++++ b/drivers/clk/spacemit/Kconfig +@@ -14,4 +14,10 @@ config SPACEMIT_K1_CCU + help + Support for clock controller unit in SpacemiT K1 SoC. + ++config SPACEMIT_K3_CCU ++ tristate "Support for SpacemiT K3 SoC" ++ select SPACEMIT_CCU ++ help ++ Support for clock controller unit in SpacemiT K3 SoC. ++ + endmenu +diff --git a/drivers/clk/spacemit/Makefile b/drivers/clk/spacemit/Makefile +index ad2bf315109b..0925eda384b4 100644 +--- a/drivers/clk/spacemit/Makefile ++++ b/drivers/clk/spacemit/Makefile +@@ -8,3 +8,6 @@ spacemit-ccu-y += ccu_ddn.o + + obj-$(CONFIG_SPACEMIT_K1_CCU) += spacemit-ccu-k1.o + spacemit-ccu-k1-y += ccu-k1.o ++ ++obj-$(CONFIG_SPACEMIT_K3_CCU) += spacemit-ccu-k3.o ++spacemit-ccu-k3-y += ccu-k3.o +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +new file mode 100644 +index 000000000000..e98afd59f05c +--- /dev/null ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -0,0 +1,1487 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "ccu_common.h" ++#include "ccu_pll.h" ++#include "ccu_mix.h" ++#include "ccu_ddn.h" ++ ++#include ++ ++/* APBS clocks start, APBS region contains and only contains all PLL clocks */ ++ ++/* ++ * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for ++ * peripherals. ++ */ ++static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = { ++ CCU_PLLA_RATE(2457600000UL, 0x0b330ccc, 0x0000cd00, 0xa0558989), ++}; ++ ++static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { ++ CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c), ++}; ++ ++static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = { ++ CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), ++}; ++ ++static const struct ccu_pll_rate_tbl pll4_rate_tbl[] = { ++ CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), ++}; ++ ++static const struct ccu_pll_rate_tbl pll5_rate_tbl[] = { ++ CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), ++}; ++ ++static const struct ccu_pll_rate_tbl pll6_rate_tbl[] = { ++ CCU_PLLA_RATE(3200000000UL, 0x0b422aaa, 0x0000ab00, 0xa0558e8e), ++}; ++ ++static const struct ccu_pll_rate_tbl pll7_rate_tbl[] = { ++ CCU_PLLA_RATE(2800000000UL, 0x0b3a1555, 0x00005500, 0xa0558b8b), ++}; ++ ++static const struct ccu_pll_rate_tbl pll8_rate_tbl[] = { ++ CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), ++}; ++ ++CCU_PLLA_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR2, APBS_PLL1_SWCR3, ++ MPMU_POSR, POSR_PLL1_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2, APBS_PLL2_SWCR3, ++ MPMU_POSR, POSR_PLL2_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR2, APBS_PLL3_SWCR3, ++ MPMU_POSR, POSR_PLL3_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll4, pll4_rate_tbl, APBS_PLL4_SWCR1, APBS_PLL4_SWCR2, APBS_PLL4_SWCR3, ++ MPMU_POSR, POSR_PLL4_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll5, pll5_rate_tbl, APBS_PLL5_SWCR1, APBS_PLL5_SWCR2, APBS_PLL5_SWCR3, ++ MPMU_POSR, POSR_PLL5_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll6, pll6_rate_tbl, APBS_PLL6_SWCR1, APBS_PLL6_SWCR2, APBS_PLL6_SWCR3, ++ MPMU_POSR, POSR_PLL6_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll7, pll7_rate_tbl, APBS_PLL7_SWCR1, APBS_PLL7_SWCR2, APBS_PLL7_SWCR3, ++ MPMU_POSR, POSR_PLL7_LOCK, CLK_SET_RATE_GATE); ++CCU_PLLA_DEFINE(pll8, pll8_rate_tbl, APBS_PLL8_SWCR1, APBS_PLL8_SWCR2, APBS_PLL8_SWCR3, ++ MPMU_POSR, POSR_PLL8_LOCK, CLK_SET_RATE_GATE); ++ ++CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1, ++ CLK_IS_CRITICAL); ++CCU_DIV_GATE_DEFINE(pll1_dx, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, 23, 5, BIT(22), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(31), 64, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(21), 10, 1); ++CCU_FACTOR_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1_aud_245p7), 10, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1); ++CCU_FACTOR_DEFINE(pll2_66, CCU_PARENT_HW(pll2_d5), 9, 1); ++CCU_FACTOR_DEFINE(pll2_33, CCU_PARENT_HW(pll2_66), 2, 1); ++CCU_FACTOR_DEFINE(pll2_50, CCU_PARENT_HW(pll2_d5), 12, 1); ++CCU_FACTOR_DEFINE(pll2_25, CCU_PARENT_HW(pll2_50), 2, 1); ++CCU_FACTOR_DEFINE(pll2_20, CCU_PARENT_HW(pll2_d5), 30, 1); ++CCU_FACTOR_DEFINE(pll2_d24_125, CCU_PARENT_HW(pll2_d3), 8, 1); ++CCU_FACTOR_DEFINE(pll2_d120_25, CCU_PARENT_HW(pll2_d3), 40, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll4_d1, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d2, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d3, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d4, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d5, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d6, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d7, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll4_d8, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll5_d1, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d2, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d3, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d4, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d5, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d6, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d7, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll5_d8, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll6_d1, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d2, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d3, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d4, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d5, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d6, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d7, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll6_d8, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(7), 8, 1); ++CCU_FACTOR_DEFINE(pll6_80, CCU_PARENT_HW(pll6_d5), 8, 1); ++CCU_FACTOR_DEFINE(pll6_40, CCU_PARENT_HW(pll6_d5), 16, 1); ++CCU_FACTOR_DEFINE(pll6_20, CCU_PARENT_HW(pll6_d5), 32, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll7_d1, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d2, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d3, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d4, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d5, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d6, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d7, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll7_d8, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(7), 8, 1); ++ ++CCU_FACTOR_GATE_DEFINE(pll8_d1, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(0), 1, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d2, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(1), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d3, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(2), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d4, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(3), 4, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d5, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(4), 5, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d6, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(5), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d7, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(6), 7, 1); ++CCU_FACTOR_GATE_DEFINE(pll8_d8, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(7), 8, 1); ++/* APBS clocks end */ ++ ++/* MPMU clocks start */ ++CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13), 0); ++CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1); ++CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1); ++CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(12), 3, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(7), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(11), 6, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(8), 16, 3); ++CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(4), 12, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(3), 24, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(19), 24, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(2), 48, 1); ++ ++CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1); ++CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1); ++CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1); ++ ++CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1); ++ ++CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1); ++ ++CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0); ++CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(10), 13, 1); ++CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6), 39, 2); ++ ++CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0); ++ ++CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0); ++ ++static const struct clk_parent_data apb_parents[] = { ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d24_102p4), ++}; ++CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0); ++ ++CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc_32k), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED); ++CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 2, 0); ++CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 2, 0); ++ ++CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0); ++CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), 0); ++ ++CCU_GATE_DEFINE(r_ipc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, BIT(0), 0); ++ ++CCU_FACTOR_DEFINE(i2s_153p6, CCU_PARENT_HW(pll1_d8_307p2), 2, 1); ++ ++static const struct clk_parent_data i2s_153p6_base_parents[] = { ++ CCU_PARENT_HW(i2s_153p6), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DEFINE(i2s_153p6_base, i2s_153p6_base_parents, MPMU_FCCR, 29, 1, 0); ++ ++static const struct clk_parent_data i2s_sysclk_src_parents[] = { ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(i2s_153p6_base), ++}; ++CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0); ++ ++CCU_DDN_DEFINE(i2s1_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0); ++ ++CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s1_sysclk), MPMU_ISCCR, 27, 2, BIT(29), 0); ++ ++static const struct clk_parent_data i2s_sysclk_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_NAME(vctcxo_24m), ++ CCU_PARENT_HW(pll2_d5), ++ CCU_PARENT_NAME(vctcxo_24m), ++}; ++CCU_MUX_DEFINE(i2s0_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 0, 2, 0); ++CCU_MUX_DEFINE(i2s2_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 4, 2, 0); ++CCU_MUX_DEFINE(i2s3_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 12, 2, 0); ++CCU_MUX_DEFINE(i2s4_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 16, 2, 0); ++CCU_MUX_DEFINE(i2s5_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 20, 2, 0); ++ ++CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 1, 0); ++CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 1, 0); ++ ++static const struct clk_parent_data i2s2_sysclk_parents[] = { ++ CCU_PARENT_HW(i2s1_sysclk), ++ CCU_PARENT_HW(i2s2_sysclk_div), ++}; ++CCU_GATE_DEFINE(i2s0_sysclk, CCU_PARENT_HW(i2s0_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(2), 0); ++CCU_MUX_GATE_DEFINE(i2s2_sysclk, i2s2_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 8, 1, BIT(6), 0); ++CCU_GATE_DEFINE(i2s3_sysclk, CCU_PARENT_HW(i2s3_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(14), 0); ++CCU_GATE_DEFINE(i2s4_sysclk, CCU_PARENT_HW(i2s4_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(18), 0); ++CCU_GATE_DEFINE(i2s5_sysclk, CCU_PARENT_HW(i2s5_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(22), 0); ++/* MPMU clocks end */ ++ ++/* APBC clocks start */ ++static const struct clk_parent_data uart_clk_parents[] = { ++ CCU_PARENT_HW(pll1_m3d128_57p6), ++ CCU_PARENT_HW(slow_uart1_14p74), ++ CCU_PARENT_HW(slow_uart2_48), ++}; ++CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(uart10_clk, uart_clk_parents, APBC_UART10_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(uart10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART10_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data pwm_parents[] = { ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_NAME(osc_32k), ++}; ++CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data i2s_bclk_parents[] = { ++ CCU_PARENT_NAME(vctcxo_1m), ++ CCU_PARENT_HW(i2s_bclk), ++}; ++CCU_MUX_DEFINE(spi0_i2s_bclk, i2s_bclk_parents, APBC_SSP0_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(spi1_i2s_bclk, i2s_bclk_parents, APBC_SSP1_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(spi3_i2s_bclk, i2s_bclk_parents, APBC_SSP3_CLK_RST, 3, 1, 0); ++ ++static const struct clk_parent_data spi0_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(spi0_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(spi0_clk, spi0_parents, APBC_SSP0_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data spi1_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(spi1_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(spi1_clk, spi1_parents, APBC_SSP1_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data spi3_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(spi3_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(spi3_clk, spi3_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(spi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(spi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(spi3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, BIT(0), 0); ++ ++ ++CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc_32k), APBC_RTC_CLK_RST, ++ BIT(7) | BIT(1), 0); ++CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data twsi_parents[] = { ++ CCU_PARENT_HW(pll1_d78_31p5), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d40_61p44), ++}; ++CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(twsi8_clk, twsi_parents, APBC_TWSI8_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI8_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data timer_parents[] = { ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_NAME(osc_32k), ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_NAME(vctcxo_3m), ++ CCU_PARENT_NAME(vctcxo_1m), ++}; ++CCU_MUX_GATE_DEFINE(timers0_clk, timer_parents, APBC_TIMERS0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers3_clk, timer_parents, APBC_TIMERS3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers4_clk, timer_parents, APBC_TIMERS4_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers5_clk, timer_parents, APBC_TIMERS5_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers6_clk, timer_parents, APBC_TIMERS6_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(timers7_clk, timer_parents, APBC_TIMERS7_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(timers0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS5_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS6_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(timers7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS7_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_RST, BIT(0), 0); ++ ++/* ++ * When i2s_bclk is selected as the parent clock of sspa, ++ * the hardware requires bit3 to be set ++ */ ++ ++CCU_MUX_DEFINE(i2s0_i2s_bclk, i2s_bclk_parents, APBC_SSPA0_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s1_i2s_bclk, i2s_bclk_parents, APBC_SSPA1_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s2_i2s_bclk, i2s_bclk_parents, APBC_SSPA2_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s3_i2s_bclk, i2s_bclk_parents, APBC_SSPA3_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s4_i2s_bclk, i2s_bclk_parents, APBC_SSPA4_CLK_RST, 3, 1, 0); ++CCU_MUX_DEFINE(i2s5_i2s_bclk, i2s_bclk_parents, APBC_SSPA5_CLK_RST, 3, 1, 0); ++ ++static const struct clk_parent_data i2s0_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s0_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s0_clk, i2s0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s1_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s1_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s1_clk, i2s1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s2_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s2_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s2_clk, i2s2_parents, APBC_SSPA2_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s3_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s3_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s3_clk, i2s3_parents, APBC_SSPA3_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s4_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s4_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s4_clk, i2s4_parents, APBC_SSPA4_CLK_RST, 4, 3, BIT(1), 0); ++ ++static const struct clk_parent_data i2s5_parents[] = { ++ CCU_PARENT_HW(pll1_d384_6p4), ++ CCU_PARENT_HW(pll1_d192_12p8), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d48_51p2), ++ CCU_PARENT_HW(pll1_d768_3p2), ++ CCU_PARENT_HW(pll1_d1536_1p6), ++ CCU_PARENT_HW(pll1_d3072_0p8), ++ CCU_PARENT_HW(i2s5_i2s_bclk), ++}; ++CCU_MUX_GATE_DEFINE(i2s5_clk, i2s5_parents, APBC_SSPA5_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(i2s0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA4_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(i2s5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA5_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(ir0_clk, CCU_PARENT_HW(apb_clk), APBC_IR0_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(ir1_clk, CCU_PARENT_HW(apb_clk), APBC_IR1_CLK_RST, BIT(1), 0); ++ ++CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(0), 0); ++ ++CCU_GATE_DEFINE(ipc_ap2rcpu_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0); ++CCU_GATE_DEFINE(ipc_ap2rcpu_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0); ++ ++static const struct clk_parent_data can_parents[] = { ++ CCU_PARENT_HW(pll6_20), ++ CCU_PARENT_HW(pll6_40), ++ CCU_PARENT_HW(pll6_80), ++}; ++CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(can1_clk, can_parents, APBC_CAN1_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(can2_clk, can_parents, APBC_CAN2_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(can3_clk, can_parents, APBC_CAN3_CLK_RST, 4, 3, BIT(1), 0); ++CCU_MUX_GATE_DEFINE(can4_clk, can_parents, APBC_CAN4_CLK_RST, 4, 3, BIT(1), 0); ++ ++CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN0_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(can1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN1_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(can2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN2_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(can3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN3_CLK_RST, BIT(0), 0); ++CCU_GATE_DEFINE(can4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN4_CLK_RST, BIT(0), 0); ++/* APBC clocks end */ ++ ++/* APMU clocks start */ ++static const struct clk_parent_data axi_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++}; ++CCU_MUX_DIV_FC_DEFINE(axi_clk, axi_clk_parents, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), 0, 1, 0); ++ ++static const struct clk_parent_data cci550_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll7_d3), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll7_d2), ++}; ++CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL, 8, 2, BIT(12), 0, 3, ++ CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c0_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll3_d2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll3_d1), ++}; ++CCU_MUX_DIV_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL, ++ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c1_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll4_d2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll4_d1), ++}; ++CCU_MUX_DIV_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL, ++ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c2_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll5_d2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll5_d1), ++}; ++CCU_MUX_DIV_FC_DEFINE(cpu_c2_core_clk, cpu_c2_clk_parents, APMU_CPU_C2_CLK_CTRL, ++ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data cpu_c3_clk_parents[] = { ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll8_d2), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll8_d1), ++}; ++CCU_MUX_DIV_FC_DEFINE(cpu_c3_core_clk, cpu_c3_clk_parents, APMU_CPU_C3_CLK_CTRL, ++ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data ccic2phy_parents[] = { ++ CCU_PARENT_HW(pll1_d24_102p4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0); ++ ++static const struct clk_parent_data ccic3phy_parents[] = { ++ CCU_PARENT_HW(pll1_d24_102p4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0); ++ ++static const struct clk_parent_data csi_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15), ++ 16, 3, BIT(4), 0); ++ ++static const struct clk_parent_data isp_bus_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d10_245p76), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23), ++ 21, 2, BIT(17), 0); ++ ++CCU_GATE_DEFINE(d1p_1228p8, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMU_CLK_GATE_CTRL, BIT(31), 0); ++CCU_GATE_DEFINE(d1p_819p2, CCU_PARENT_HW(pll1_d3_819p2), APMU_PMU_CLK_GATE_CTRL, BIT(30), 0); ++CCU_GATE_DEFINE(d1p_614p4, CCU_PARENT_HW(pll1_d4_614p4), APMU_PMU_CLK_GATE_CTRL, BIT(29), 0); ++CCU_GATE_DEFINE(d1p_491p52, CCU_PARENT_HW(pll1_d5_491p52), APMU_PMU_CLK_GATE_CTRL, BIT(28), 0); ++CCU_GATE_DEFINE(d1p_409p6, CCU_PARENT_HW(pll1_d6_409p6), APMU_PMU_CLK_GATE_CTRL, BIT(27), 0); ++CCU_GATE_DEFINE(d1p_307p2, CCU_PARENT_HW(pll1_d8_307p2), APMU_PMU_CLK_GATE_CTRL, BIT(26), 0); ++CCU_GATE_DEFINE(d1p_245p76, CCU_PARENT_HW(pll1_d10_245p76), APMU_PMU_CLK_GATE_CTRL, BIT(22), 0); ++ ++static const struct clk_parent_data v2d_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d4_614p4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28), 12, 2, ++ BIT(8), 0); ++ ++static const struct clk_parent_data dsiesc_parents[] = { ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll1_d52_47p26), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d32_76p8), ++}; ++CCU_MUX_GATE_DEFINE(dsi_esc_clk, dsiesc_parents, APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0); ++ ++CCU_GATE_DEFINE(lcd_hclk, CCU_PARENT_HW(axi_clk), APMU_LCD_CLK_RES_CTRL1, BIT(5), 0); ++ ++static const struct clk_parent_data lcd_dsc_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_HW(pll7_d5), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll2_d8), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_dsc_clk, lcd_dsc_parents, APMU_LCD_CLK_RES_CTRL2, ++ APMU_LCD_CLK_RES_CTRL1, 25, 3, BIT(26), 29, 3, BIT(14), 0); ++ ++static const struct clk_parent_data lcdpx_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_HW(pll7_d5), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll2_d8), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_pxclk, lcdpx_parents, APMU_LCD_CLK_RES_CTRL2, ++ APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(30), 21, 3, BIT(16), 0); ++ ++static const struct clk_parent_data lcdmclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_mclk, lcdmclk_parents, APMU_LCD_CLK_RES_CTRL2, ++ APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0); ++ ++static const struct clk_parent_data ccic_4x_parents[] = { ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll2_d2), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES_CTRL, 18, 3, ++ BIT(15), 23, 2, BIT(4), 0); ++ ++static const struct clk_parent_data ccic1phy_parents[] = { ++ CCU_PARENT_HW(pll1_d24_102p4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0); ++ ++ ++static const struct clk_parent_data sc2hclk_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll2_d4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(sc2_hclk, sc2hclk_parents, APMU_CCIC_CLK_RES_CTRL, 10, 3, ++ BIT(16), 8, 2, BIT(3), 0); ++ ++CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(axi_clk), APMU_SDH0_CLK_RES_CTRL, BIT(3), 0); ++static const struct clk_parent_data sdh01_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d8), ++ CCU_PARENT_HW(pll2_d5), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_HW(pll1_dx), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL, 8, 3, ++ BIT(11), 5, 3, BIT(4), 0); ++CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL, 8, 3, ++ BIT(11), 5, 3, BIT(4), 0); ++static const struct clk_parent_data sdh2_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll2_d8), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_HW(pll1_dx), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, ++ BIT(11), 5, 3, BIT(4), 0); ++ ++CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(4), 0); ++CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); ++CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(12), 0); ++CCU_GATE_DEFINE(usb3_portd_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(16), 0); ++ ++static const struct clk_parent_data qspi_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll2_d8), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d10_245p76), ++ CCU_PARENT_NAME(reserved_clk), ++ CCU_PARENT_HW(pll1_dx), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_NAME(reserved_clk), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL, 9, 3, ++ BIT(12), 6, 3, BIT(4), 0); ++CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(axi_clk), APMU_QSPI_CLK_RES_CTRL, BIT(3), 0); ++ ++CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(axi_clk), APMU_DMA_CLK_RES_CTRL, BIT(3), 0); ++ ++static const struct clk_parent_data aes_wtm_parents[] = { ++ CCU_PARENT_HW(pll1_d12_204p8), ++ CCU_PARENT_HW(pll1_d24_102p4), ++}; ++CCU_MUX_GATE_DEFINE(aes_wtm_clk, aes_wtm_parents, APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0); ++ ++static const struct clk_parent_data vpu_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll2_d5), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13, 3, ++ BIT(21), 10, 3, BIT(3), 0); ++ ++CCU_GATE_DEFINE(dtc_clk, CCU_PARENT_HW(axi_clk), APMU_DTC_CLK_RES_CTRL, BIT(3), 0); ++ ++static const struct clk_parent_data gpu_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d3_819p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d2_1228p8), ++ CCU_PARENT_HW(pll2_d3), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll2_d5), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12, 3, ++ BIT(15), 18, 3, BIT(4), 0); ++ ++CCU_GATE_DEFINE(mc_ahb_clk, CCU_PARENT_HW(axi_clk), APMU_PMUA_MC_CTRL, BIT(1), 0); ++ ++static const struct clk_parent_data top_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll3_d4), ++ CCU_PARENT_HW(pll6_d5), ++ CCU_PARENT_HW(pll7_d4), ++ CCU_PARENT_HW(pll6_d4), ++ CCU_PARENT_HW(pll7_d3), ++ CCU_PARENT_HW(pll6_d3), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(top_dclk, top_parents, APMU_TOP_DCLK_CTRL, 5, 3, ++ BIT(8), 2, 3, BIT(1), 0); ++ ++static const struct clk_parent_data ucie_parents[] = { ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll3_d4), ++ CCU_PARENT_HW(pll6_d5), ++ CCU_PARENT_HW(pll7_d4), ++ CCU_PARENT_HW(pll6_d4), ++}; ++CCU_MUX_GATE_DEFINE(ucie_clk, ucie_parents, APMU_UCIE_CTRL, 4, 3, BIT(0), 0); ++CCU_GATE_DEFINE(ucie_sbclk, CCU_PARENT_HW(axi_clk), APMU_UCIE_CTRL, BIT(8), 0); ++ ++static const struct clk_parent_data rcpu_clk_parents[] = { ++ CCU_PARENT_HW(pll1_aud_245p7), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d6_409p6), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, ++ 4, 3, BIT(15), 7, 3, BIT(12), 0); ++ ++static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll1_d52_47p26), ++ CCU_PARENT_HW(pll1_d96_25p6), ++ CCU_PARENT_HW(pll1_d32_76p8), ++}; ++CCU_MUX_GATE_DEFINE(dsi4ln2_dsi_esc_clk, dsi4ln2_dsi_esc_parents, APMU_LCD_CLK_RES_CTRL3, ++ 0, 1, BIT(2), 0); ++ ++static const struct clk_parent_data dsi4ln2_lcd_dsc_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll7_d5), ++ CCU_PARENT_HW(pll6_d6), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_dsc_clk, dsi4ln2_lcd_dsc_parents, ++ APMU_LCD_CLK_RES_CTRL4, APMU_LCD_CLK_RES_CTRL3, ++ 25, 3, BIT(26), 29, 3, BIT(14), 0); ++ ++static const struct clk_parent_data dsi4ln2_lcdpx_parents[] = { ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll7_d5), ++ CCU_PARENT_HW(pll6_d6), ++ CCU_PARENT_HW(pll2_d7), ++ CCU_PARENT_HW(pll2_d4), ++ CCU_PARENT_HW(pll1_d48_51p2_ap), ++ CCU_PARENT_HW(pll2_d8), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_pxclk, dsi4ln2_lcdpx_parents, APMU_LCD_CLK_RES_CTRL4, ++ APMU_LCD_CLK_RES_CTRL3, 17, 3, BIT(30), 21, 3, BIT(16), 0); ++ ++static const struct clk_parent_data dsi4ln2_lcd_mclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++}; ++CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_mclk, dsi4ln2_lcd_mclk_parents, APMU_LCD_CLK_RES_CTRL4, ++ APMU_LCD_CLK_RES_CTRL3, 1, 4, BIT(29), 5, 3, BIT(0), 0); ++ ++static const struct clk_parent_data dpu_aclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll2_d4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(dsi4ln2_dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, ++ 2, 3, BIT(30), 5, 3, BIT(1), 0); ++ ++CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, 17, 3, BIT(31), ++ 20, 3, BIT(16), 0); ++ ++static const struct clk_parent_data ufs_aclk_parents[] = { ++ CCU_PARENT_HW(pll1_d6_409p6), ++ CCU_PARENT_HW(pll1_d5_491p52), ++ CCU_PARENT_HW(pll1_d4_614p4), ++ CCU_PARENT_HW(pll1_d8_307p2), ++ CCU_PARENT_HW(pll2_d4), ++}; ++CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8), ++ 2, 3, BIT(1), 0); ++ ++static const struct clk_parent_data edp0_pclk_parents[] = { ++ CCU_PARENT_HW(lcd_pxclk), ++ CCU_PARENT_NAME(external_clk), ++}; ++CCU_MUX_GATE_DEFINE(edp0_pxclk, edp0_pclk_parents, APMU_LCD_EDP_CTRL, 2, 1, BIT(1), 0); ++ ++static const struct clk_parent_data edp1_pclk_parents[] = { ++ CCU_PARENT_HW(dsi4ln2_lcd_pxclk), ++ CCU_PARENT_NAME(external_clk), ++}; ++CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); ++ ++CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); ++CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); ++CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); ++CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); ++CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); ++CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); ++CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); ++CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); ++CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); ++CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); ++ ++static const struct clk_parent_data emac_1588_parents[] = { ++ CCU_PARENT_NAME(vctcxo_24m), ++ CCU_PARENT_HW(pll2_d24_125), ++}; ++ ++CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_FLAGS_DEFINE(emac0_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC0_CLK_RES_CTRL, ++ BIT(14), true, 0); ++CCU_MUX_DEFINE(emac0_1588_clk, emac_1588_parents, APMU_EMAC0_CLK_RES_CTRL, 15, 1, 0); ++CCU_GATE_DEFINE(emac0_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC0_CLK_RES_CTRL, ++ BIT(8), 0); ++CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_FLAGS_DEFINE(emac1_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC1_CLK_RES_CTRL, ++ BIT(14), true, 0); ++CCU_MUX_DEFINE(emac1_1588_clk, emac_1588_parents, APMU_EMAC1_CLK_RES_CTRL, 15, 1, 0); ++CCU_GATE_DEFINE(emac1_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC1_CLK_RES_CTRL, ++ BIT(8), 0); ++CCU_GATE_DEFINE(emac2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC2_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_FLAGS_DEFINE(emac2_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC2_CLK_RES_CTRL, ++ BIT(14), true, 0); ++CCU_MUX_DEFINE(emac2_1588_clk, emac_1588_parents, APMU_EMAC2_CLK_RES_CTRL, 15, 1, 0); ++CCU_GATE_DEFINE(emac2_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC2_CLK_RES_CTRL, ++ BIT(8), 0); ++ ++static const struct clk_parent_data espi_sclk_src_parents[] = { ++ CCU_PARENT_HW(pll2_20), ++ CCU_PARENT_HW(pll2_25), ++ CCU_PARENT_HW(pll2_33), ++ CCU_PARENT_HW(pll2_50), ++ CCU_PARENT_HW(pll2_66), ++}; ++CCU_MUX_DEFINE(espi_sclk_src, espi_sclk_src_parents, APMU_ESPI_CLK_RES_CTRL, 4, 3, 0); ++ ++static const struct clk_parent_data espi_sclk_parents[] = { ++ CCU_PARENT_NAME(external_clk), ++ CCU_PARENT_HW(espi_sclk_src), ++}; ++CCU_MUX_GATE_DEFINE(espi_sclk, espi_sclk_parents, APMU_ESPI_CLK_RES_CTRL, 7, 1, BIT(3), 0); ++ ++CCU_GATE_DEFINE(espi_mclk, CCU_PARENT_HW(axi_clk), APMU_ESPI_CLK_RES_CTRL, BIT(1), 0); ++ ++CCU_FACTOR_DEFINE(cam_src1_clk, CCU_PARENT_HW(pll1_d6_409p6), 15, 1); ++CCU_FACTOR_DEFINE(cam_src2_clk, CCU_PARENT_HW(pll2_d5), 25, 1); ++CCU_FACTOR_DEFINE(cam_src3_clk, CCU_PARENT_HW(pll2_d6), 20, 1); ++CCU_FACTOR_DEFINE(cam_src4_clk, CCU_PARENT_HW(pll1_d6_409p6), 16, 1); ++ ++static const struct clk_parent_data isim_vclk_parents[] = { ++ CCU_PARENT_HW(cam_src1_clk), ++ CCU_PARENT_HW(cam_src2_clk), ++ CCU_PARENT_HW(cam_src3_clk), ++ CCU_PARENT_HW(cam_src4_clk), ++}; ++CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out0, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 3, 4, ++ 1, 2, BIT(0), 0); ++CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out1, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 11, 4, ++ 9, 2, BIT(8), 0); ++CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out2, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 19, 4, ++ 17, 2, BIT(16), 0); ++CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 27, 4, ++ 25, 2, BIT(24), 0); ++/* APMU clocks end */ ++ ++/* DCIU clocks start */ ++CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); ++CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); ++CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); ++CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); ++/* DCIU clocks end */ ++ ++static struct clk_hw *k3_ccu_pll_hws[] = { ++ [CLK_PLL1] = &pll1.common.hw, ++ [CLK_PLL2] = &pll2.common.hw, ++ [CLK_PLL3] = &pll3.common.hw, ++ [CLK_PLL4] = &pll4.common.hw, ++ [CLK_PLL5] = &pll5.common.hw, ++ [CLK_PLL6] = &pll6.common.hw, ++ [CLK_PLL7] = &pll7.common.hw, ++ [CLK_PLL8] = &pll8.common.hw, ++ [CLK_PLL1_D2] = &pll1_d2.common.hw, ++ [CLK_PLL1_D3] = &pll1_d3.common.hw, ++ [CLK_PLL1_D4] = &pll1_d4.common.hw, ++ [CLK_PLL1_D5] = &pll1_d5.common.hw, ++ [CLK_PLL1_D6] = &pll1_d6.common.hw, ++ [CLK_PLL1_D7] = &pll1_d7.common.hw, ++ [CLK_PLL1_D8] = &pll1_d8.common.hw, ++ [CLK_PLL1_DX] = &pll1_dx.common.hw, ++ [CLK_PLL1_D64] = &pll1_d64_38p4.common.hw, ++ [CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw, ++ [CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw, ++ [CLK_PLL2_D1] = &pll2_d1.common.hw, ++ [CLK_PLL2_D2] = &pll2_d2.common.hw, ++ [CLK_PLL2_D3] = &pll2_d3.common.hw, ++ [CLK_PLL2_D4] = &pll2_d4.common.hw, ++ [CLK_PLL2_D5] = &pll2_d5.common.hw, ++ [CLK_PLL2_D6] = &pll2_d6.common.hw, ++ [CLK_PLL2_D7] = &pll2_d7.common.hw, ++ [CLK_PLL2_D8] = &pll2_d8.common.hw, ++ [CLK_PLL2_66] = &pll2_66.common.hw, ++ [CLK_PLL2_33] = &pll2_33.common.hw, ++ [CLK_PLL2_50] = &pll2_50.common.hw, ++ [CLK_PLL2_25] = &pll2_25.common.hw, ++ [CLK_PLL2_20] = &pll2_20.common.hw, ++ [CLK_PLL2_D24_125] = &pll2_d24_125.common.hw, ++ [CLK_PLL2_D120_25] = &pll2_d120_25.common.hw, ++ [CLK_PLL3_D1] = &pll3_d1.common.hw, ++ [CLK_PLL3_D2] = &pll3_d2.common.hw, ++ [CLK_PLL3_D3] = &pll3_d3.common.hw, ++ [CLK_PLL3_D4] = &pll3_d4.common.hw, ++ [CLK_PLL3_D5] = &pll3_d5.common.hw, ++ [CLK_PLL3_D6] = &pll3_d6.common.hw, ++ [CLK_PLL3_D7] = &pll3_d7.common.hw, ++ [CLK_PLL3_D8] = &pll3_d8.common.hw, ++ [CLK_PLL4_D1] = &pll4_d1.common.hw, ++ [CLK_PLL4_D2] = &pll4_d2.common.hw, ++ [CLK_PLL4_D3] = &pll4_d3.common.hw, ++ [CLK_PLL4_D4] = &pll4_d4.common.hw, ++ [CLK_PLL4_D5] = &pll4_d5.common.hw, ++ [CLK_PLL4_D6] = &pll4_d6.common.hw, ++ [CLK_PLL4_D7] = &pll4_d7.common.hw, ++ [CLK_PLL4_D8] = &pll4_d8.common.hw, ++ [CLK_PLL5_D1] = &pll5_d1.common.hw, ++ [CLK_PLL5_D2] = &pll5_d2.common.hw, ++ [CLK_PLL5_D3] = &pll5_d3.common.hw, ++ [CLK_PLL5_D4] = &pll5_d4.common.hw, ++ [CLK_PLL5_D5] = &pll5_d5.common.hw, ++ [CLK_PLL5_D6] = &pll5_d6.common.hw, ++ [CLK_PLL5_D7] = &pll5_d7.common.hw, ++ [CLK_PLL5_D8] = &pll5_d8.common.hw, ++ [CLK_PLL6_D1] = &pll6_d1.common.hw, ++ [CLK_PLL6_D2] = &pll6_d2.common.hw, ++ [CLK_PLL6_D3] = &pll6_d3.common.hw, ++ [CLK_PLL6_D4] = &pll6_d4.common.hw, ++ [CLK_PLL6_D5] = &pll6_d5.common.hw, ++ [CLK_PLL6_D6] = &pll6_d6.common.hw, ++ [CLK_PLL6_D7] = &pll6_d7.common.hw, ++ [CLK_PLL6_D8] = &pll6_d8.common.hw, ++ [CLK_PLL6_80] = &pll6_80.common.hw, ++ [CLK_PLL6_40] = &pll6_40.common.hw, ++ [CLK_PLL6_20] = &pll6_20.common.hw, ++ [CLK_PLL7_D1] = &pll7_d1.common.hw, ++ [CLK_PLL7_D2] = &pll7_d2.common.hw, ++ [CLK_PLL7_D3] = &pll7_d3.common.hw, ++ [CLK_PLL7_D4] = &pll7_d4.common.hw, ++ [CLK_PLL7_D5] = &pll7_d5.common.hw, ++ [CLK_PLL7_D6] = &pll7_d6.common.hw, ++ [CLK_PLL7_D7] = &pll7_d7.common.hw, ++ [CLK_PLL7_D8] = &pll7_d8.common.hw, ++ [CLK_PLL8_D1] = &pll8_d1.common.hw, ++ [CLK_PLL8_D2] = &pll8_d2.common.hw, ++ [CLK_PLL8_D3] = &pll8_d3.common.hw, ++ [CLK_PLL8_D4] = &pll8_d4.common.hw, ++ [CLK_PLL8_D5] = &pll8_d5.common.hw, ++ [CLK_PLL8_D6] = &pll8_d6.common.hw, ++ [CLK_PLL8_D7] = &pll8_d7.common.hw, ++ [CLK_PLL8_D8] = &pll8_d8.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_pll_data = { ++ /* The APBS CCU implements PLLs, but no resets */ ++ .hws = k3_ccu_pll_hws, ++ .num = ARRAY_SIZE(k3_ccu_pll_hws), ++}; ++ ++static struct clk_hw *k3_ccu_mpmu_hws[] = { ++ [CLK_MPMU_PLL1_307P2] = &pll1_d8_307p2.common.hw, ++ [CLK_MPMU_PLL1_76P8] = &pll1_d32_76p8.common.hw, ++ [CLK_MPMU_PLL1_61P44] = &pll1_d40_61p44.common.hw, ++ [CLK_MPMU_PLL1_153P6] = &pll1_d16_153p6.common.hw, ++ [CLK_MPMU_PLL1_102P4] = &pll1_d24_102p4.common.hw, ++ [CLK_MPMU_PLL1_51P2] = &pll1_d48_51p2.common.hw, ++ [CLK_MPMU_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw, ++ [CLK_MPMU_PLL1_57P6] = &pll1_m3d128_57p6.common.hw, ++ [CLK_MPMU_PLL1_25P6] = &pll1_d96_25p6.common.hw, ++ [CLK_MPMU_PLL1_12P8] = &pll1_d192_12p8.common.hw, ++ [CLK_MPMU_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw, ++ [CLK_MPMU_PLL1_6P4] = &pll1_d384_6p4.common.hw, ++ [CLK_MPMU_PLL1_3P2] = &pll1_d768_3p2.common.hw, ++ [CLK_MPMU_PLL1_1P6] = &pll1_d1536_1p6.common.hw, ++ [CLK_MPMU_PLL1_0P8] = &pll1_d3072_0p8.common.hw, ++ [CLK_MPMU_PLL1_409P6] = &pll1_d6_409p6.common.hw, ++ [CLK_MPMU_PLL1_204P8] = &pll1_d12_204p8.common.hw, ++ [CLK_MPMU_PLL1_491] = &pll1_d5_491p52.common.hw, ++ [CLK_MPMU_PLL1_245P76] = &pll1_d10_245p76.common.hw, ++ [CLK_MPMU_PLL1_614] = &pll1_d4_614p4.common.hw, ++ [CLK_MPMU_PLL1_47P26] = &pll1_d52_47p26.common.hw, ++ [CLK_MPMU_PLL1_31P5] = &pll1_d78_31p5.common.hw, ++ [CLK_MPMU_PLL1_819] = &pll1_d3_819p2.common.hw, ++ [CLK_MPMU_PLL1_1228] = &pll1_d2_1228p8.common.hw, ++ [CLK_MPMU_APB] = &apb_clk.common.hw, ++ [CLK_MPMU_SLOW_UART] = &slow_uart.common.hw, ++ [CLK_MPMU_SLOW_UART1] = &slow_uart1_14p74.common.hw, ++ [CLK_MPMU_SLOW_UART2] = &slow_uart2_48.common.hw, ++ [CLK_MPMU_WDT] = &wdt_clk.common.hw, ++ [CLK_MPMU_WDT_BUS] = &wdt_bus_clk.common.hw, ++ [CLK_MPMU_RIPC] = &r_ipc_clk.common.hw, ++ [CLK_MPMU_I2S_153P6] = &i2s_153p6.common.hw, ++ [CLK_MPMU_I2S_153P6_BASE] = &i2s_153p6_base.common.hw, ++ [CLK_MPMU_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw, ++ [CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw, ++ [CLK_MPMU_I2S_BCLK] = &i2s_bclk.common.hw, ++ [CLK_MPMU_I2S0_SYSCLK_SEL] = &i2s0_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S2_SYSCLK_SEL] = &i2s2_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S3_SYSCLK_SEL] = &i2s3_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S4_SYSCLK_SEL] = &i2s4_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S5_SYSCLK_SEL] = &i2s5_sysclk_sel.common.hw, ++ [CLK_MPMU_I2S0_SYSCLK_DIV] = &i2s0_sysclk_div.common.hw, ++ [CLK_MPMU_I2S2_SYSCLK_DIV] = &i2s2_sysclk_div.common.hw, ++ [CLK_MPMU_I2S3_SYSCLK_DIV] = &i2s3_sysclk_div.common.hw, ++ [CLK_MPMU_I2S4_SYSCLK_DIV] = &i2s4_sysclk_div.common.hw, ++ [CLK_MPMU_I2S5_SYSCLK_DIV] = &i2s5_sysclk_div.common.hw, ++ [CLK_MPMU_I2S0_SYSCLK] = &i2s0_sysclk.common.hw, ++ [CLK_MPMU_I2S2_SYSCLK] = &i2s2_sysclk.common.hw, ++ [CLK_MPMU_I2S3_SYSCLK] = &i2s3_sysclk.common.hw, ++ [CLK_MPMU_I2S4_SYSCLK] = &i2s4_sysclk.common.hw, ++ [CLK_MPMU_I2S5_SYSCLK] = &i2s5_sysclk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_mpmu_data = { ++ .reset_name = "k3-mpmu-reset", ++ .hws = k3_ccu_mpmu_hws, ++ .num = ARRAY_SIZE(k3_ccu_mpmu_hws), ++}; ++ ++static struct clk_hw *k3_ccu_apbc_hws[] = { ++ [CLK_APBC_UART0] = &uart0_clk.common.hw, ++ [CLK_APBC_UART2] = &uart2_clk.common.hw, ++ [CLK_APBC_UART3] = &uart3_clk.common.hw, ++ [CLK_APBC_UART4] = &uart4_clk.common.hw, ++ [CLK_APBC_UART5] = &uart5_clk.common.hw, ++ [CLK_APBC_UART6] = &uart6_clk.common.hw, ++ [CLK_APBC_UART7] = &uart7_clk.common.hw, ++ [CLK_APBC_UART8] = &uart8_clk.common.hw, ++ [CLK_APBC_UART9] = &uart9_clk.common.hw, ++ [CLK_APBC_UART10] = &uart10_clk.common.hw, ++ [CLK_APBC_UART0_BUS] = &uart0_bus_clk.common.hw, ++ [CLK_APBC_UART2_BUS] = &uart2_bus_clk.common.hw, ++ [CLK_APBC_UART3_BUS] = &uart3_bus_clk.common.hw, ++ [CLK_APBC_UART4_BUS] = &uart4_bus_clk.common.hw, ++ [CLK_APBC_UART5_BUS] = &uart5_bus_clk.common.hw, ++ [CLK_APBC_UART6_BUS] = &uart6_bus_clk.common.hw, ++ [CLK_APBC_UART7_BUS] = &uart7_bus_clk.common.hw, ++ [CLK_APBC_UART8_BUS] = &uart8_bus_clk.common.hw, ++ [CLK_APBC_UART9_BUS] = &uart9_bus_clk.common.hw, ++ [CLK_APBC_UART10_BUS] = &uart10_bus_clk.common.hw, ++ [CLK_APBC_GPIO] = &gpio_clk.common.hw, ++ [CLK_APBC_GPIO_BUS] = &gpio_bus_clk.common.hw, ++ [CLK_APBC_PWM0] = &pwm0_clk.common.hw, ++ [CLK_APBC_PWM1] = &pwm1_clk.common.hw, ++ [CLK_APBC_PWM2] = &pwm2_clk.common.hw, ++ [CLK_APBC_PWM3] = &pwm3_clk.common.hw, ++ [CLK_APBC_PWM4] = &pwm4_clk.common.hw, ++ [CLK_APBC_PWM5] = &pwm5_clk.common.hw, ++ [CLK_APBC_PWM6] = &pwm6_clk.common.hw, ++ [CLK_APBC_PWM7] = &pwm7_clk.common.hw, ++ [CLK_APBC_PWM8] = &pwm8_clk.common.hw, ++ [CLK_APBC_PWM9] = &pwm9_clk.common.hw, ++ [CLK_APBC_PWM10] = &pwm10_clk.common.hw, ++ [CLK_APBC_PWM11] = &pwm11_clk.common.hw, ++ [CLK_APBC_PWM12] = &pwm12_clk.common.hw, ++ [CLK_APBC_PWM13] = &pwm13_clk.common.hw, ++ [CLK_APBC_PWM14] = &pwm14_clk.common.hw, ++ [CLK_APBC_PWM15] = &pwm15_clk.common.hw, ++ [CLK_APBC_PWM16] = &pwm16_clk.common.hw, ++ [CLK_APBC_PWM17] = &pwm17_clk.common.hw, ++ [CLK_APBC_PWM18] = &pwm18_clk.common.hw, ++ [CLK_APBC_PWM19] = &pwm19_clk.common.hw, ++ [CLK_APBC_PWM0_BUS] = &pwm0_bus_clk.common.hw, ++ [CLK_APBC_PWM1_BUS] = &pwm1_bus_clk.common.hw, ++ [CLK_APBC_PWM2_BUS] = &pwm2_bus_clk.common.hw, ++ [CLK_APBC_PWM3_BUS] = &pwm3_bus_clk.common.hw, ++ [CLK_APBC_PWM4_BUS] = &pwm4_bus_clk.common.hw, ++ [CLK_APBC_PWM5_BUS] = &pwm5_bus_clk.common.hw, ++ [CLK_APBC_PWM6_BUS] = &pwm6_bus_clk.common.hw, ++ [CLK_APBC_PWM7_BUS] = &pwm7_bus_clk.common.hw, ++ [CLK_APBC_PWM8_BUS] = &pwm8_bus_clk.common.hw, ++ [CLK_APBC_PWM9_BUS] = &pwm9_bus_clk.common.hw, ++ [CLK_APBC_PWM10_BUS] = &pwm10_bus_clk.common.hw, ++ [CLK_APBC_PWM11_BUS] = &pwm11_bus_clk.common.hw, ++ [CLK_APBC_PWM12_BUS] = &pwm12_bus_clk.common.hw, ++ [CLK_APBC_PWM13_BUS] = &pwm13_bus_clk.common.hw, ++ [CLK_APBC_PWM14_BUS] = &pwm14_bus_clk.common.hw, ++ [CLK_APBC_PWM15_BUS] = &pwm15_bus_clk.common.hw, ++ [CLK_APBC_PWM16_BUS] = &pwm16_bus_clk.common.hw, ++ [CLK_APBC_PWM17_BUS] = &pwm17_bus_clk.common.hw, ++ [CLK_APBC_PWM18_BUS] = &pwm18_bus_clk.common.hw, ++ [CLK_APBC_PWM19_BUS] = &pwm19_bus_clk.common.hw, ++ [CLK_APBC_SPI0_I2S_BCLK] = &spi0_i2s_bclk.common.hw, ++ [CLK_APBC_SPI1_I2S_BCLK] = &spi1_i2s_bclk.common.hw, ++ [CLK_APBC_SPI3_I2S_BCLK] = &spi3_i2s_bclk.common.hw, ++ [CLK_APBC_SPI0] = &spi0_clk.common.hw, ++ [CLK_APBC_SPI1] = &spi1_clk.common.hw, ++ [CLK_APBC_SPI3] = &spi3_clk.common.hw, ++ [CLK_APBC_SPI0_BUS] = &spi0_bus_clk.common.hw, ++ [CLK_APBC_SPI1_BUS] = &spi1_bus_clk.common.hw, ++ [CLK_APBC_SPI3_BUS] = &spi3_bus_clk.common.hw, ++ [CLK_APBC_RTC] = &rtc_clk.common.hw, ++ [CLK_APBC_RTC_BUS] = &rtc_bus_clk.common.hw, ++ [CLK_APBC_TWSI0] = &twsi0_clk.common.hw, ++ [CLK_APBC_TWSI1] = &twsi1_clk.common.hw, ++ [CLK_APBC_TWSI2] = &twsi2_clk.common.hw, ++ [CLK_APBC_TWSI4] = &twsi4_clk.common.hw, ++ [CLK_APBC_TWSI5] = &twsi5_clk.common.hw, ++ [CLK_APBC_TWSI6] = &twsi6_clk.common.hw, ++ [CLK_APBC_TWSI8] = &twsi8_clk.common.hw, ++ [CLK_APBC_TWSI0_BUS] = &twsi0_bus_clk.common.hw, ++ [CLK_APBC_TWSI1_BUS] = &twsi1_bus_clk.common.hw, ++ [CLK_APBC_TWSI2_BUS] = &twsi2_bus_clk.common.hw, ++ [CLK_APBC_TWSI4_BUS] = &twsi4_bus_clk.common.hw, ++ [CLK_APBC_TWSI5_BUS] = &twsi5_bus_clk.common.hw, ++ [CLK_APBC_TWSI6_BUS] = &twsi6_bus_clk.common.hw, ++ [CLK_APBC_TWSI8_BUS] = &twsi8_bus_clk.common.hw, ++ [CLK_APBC_TIMERS0] = &timers0_clk.common.hw, ++ [CLK_APBC_TIMERS1] = &timers1_clk.common.hw, ++ [CLK_APBC_TIMERS2] = &timers2_clk.common.hw, ++ [CLK_APBC_TIMERS3] = &timers3_clk.common.hw, ++ [CLK_APBC_TIMERS4] = &timers4_clk.common.hw, ++ [CLK_APBC_TIMERS5] = &timers5_clk.common.hw, ++ [CLK_APBC_TIMERS6] = &timers6_clk.common.hw, ++ [CLK_APBC_TIMERS7] = &timers7_clk.common.hw, ++ [CLK_APBC_TIMERS0_BUS] = &timers0_bus_clk.common.hw, ++ [CLK_APBC_TIMERS1_BUS] = &timers1_bus_clk.common.hw, ++ [CLK_APBC_TIMERS2_BUS] = &timers2_bus_clk.common.hw, ++ [CLK_APBC_TIMERS3_BUS] = &timers3_bus_clk.common.hw, ++ [CLK_APBC_TIMERS4_BUS] = &timers4_bus_clk.common.hw, ++ [CLK_APBC_TIMERS5_BUS] = &timers5_bus_clk.common.hw, ++ [CLK_APBC_TIMERS6_BUS] = &timers6_bus_clk.common.hw, ++ [CLK_APBC_TIMERS7_BUS] = &timers7_bus_clk.common.hw, ++ [CLK_APBC_AIB] = &aib_clk.common.hw, ++ [CLK_APBC_AIB_BUS] = &aib_bus_clk.common.hw, ++ [CLK_APBC_ONEWIRE] = &onewire_clk.common.hw, ++ [CLK_APBC_ONEWIRE_BUS] = &onewire_bus_clk.common.hw, ++ [CLK_APBC_I2S0_BCLK] = &i2s0_i2s_bclk.common.hw, ++ [CLK_APBC_I2S1_BCLK] = &i2s1_i2s_bclk.common.hw, ++ [CLK_APBC_I2S2_BCLK] = &i2s2_i2s_bclk.common.hw, ++ [CLK_APBC_I2S3_BCLK] = &i2s3_i2s_bclk.common.hw, ++ [CLK_APBC_I2S4_BCLK] = &i2s4_i2s_bclk.common.hw, ++ [CLK_APBC_I2S5_BCLK] = &i2s5_i2s_bclk.common.hw, ++ [CLK_APBC_I2S0] = &i2s0_clk.common.hw, ++ [CLK_APBC_I2S1] = &i2s1_clk.common.hw, ++ [CLK_APBC_I2S2] = &i2s2_clk.common.hw, ++ [CLK_APBC_I2S3] = &i2s3_clk.common.hw, ++ [CLK_APBC_I2S4] = &i2s4_clk.common.hw, ++ [CLK_APBC_I2S5] = &i2s5_clk.common.hw, ++ [CLK_APBC_I2S0_BUS] = &i2s0_bus_clk.common.hw, ++ [CLK_APBC_I2S1_BUS] = &i2s1_bus_clk.common.hw, ++ [CLK_APBC_I2S2_BUS] = &i2s2_bus_clk.common.hw, ++ [CLK_APBC_I2S3_BUS] = &i2s3_bus_clk.common.hw, ++ [CLK_APBC_I2S4_BUS] = &i2s4_bus_clk.common.hw, ++ [CLK_APBC_I2S5_BUS] = &i2s5_bus_clk.common.hw, ++ [CLK_APBC_DRO] = &dro_clk.common.hw, ++ [CLK_APBC_IR0] = &ir0_clk.common.hw, ++ [CLK_APBC_IR1] = &ir1_clk.common.hw, ++ [CLK_APBC_TSEN] = &tsen_clk.common.hw, ++ [CLK_APBC_TSEN_BUS] = &tsen_bus_clk.common.hw, ++ [CLK_APBC_IPC_AP2RCPU] = &ipc_ap2rcpu_clk.common.hw, ++ [CLK_APBC_IPC_AP2RCPU_BUS] = &ipc_ap2rcpu_bus_clk.common.hw, ++ [CLK_APBC_CAN0] = &can0_clk.common.hw, ++ [CLK_APBC_CAN1] = &can1_clk.common.hw, ++ [CLK_APBC_CAN2] = &can2_clk.common.hw, ++ [CLK_APBC_CAN3] = &can3_clk.common.hw, ++ [CLK_APBC_CAN4] = &can4_clk.common.hw, ++ [CLK_APBC_CAN0_BUS] = &can0_bus_clk.common.hw, ++ [CLK_APBC_CAN1_BUS] = &can1_bus_clk.common.hw, ++ [CLK_APBC_CAN2_BUS] = &can2_bus_clk.common.hw, ++ [CLK_APBC_CAN3_BUS] = &can3_bus_clk.common.hw, ++ [CLK_APBC_CAN4_BUS] = &can4_bus_clk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_apbc_data = { ++ .reset_name = "k3-apbc-reset", ++ .hws = k3_ccu_apbc_hws, ++ .num = ARRAY_SIZE(k3_ccu_apbc_hws), ++}; ++ ++static struct clk_hw *k3_ccu_apmu_hws[] = { ++ [CLK_APMU_AXICLK] = &axi_clk.common.hw, ++ [CLK_APMU_CCI550] = &cci550_clk.common.hw, ++ [CLK_APMU_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw, ++ [CLK_APMU_CPU_C1_CORE] = &cpu_c1_core_clk.common.hw, ++ [CLK_APMU_CPU_C2_CORE] = &cpu_c2_core_clk.common.hw, ++ [CLK_APMU_CPU_C3_CORE] = &cpu_c3_core_clk.common.hw, ++ [CLK_APMU_CCIC2PHY] = &ccic2phy_clk.common.hw, ++ [CLK_APMU_CCIC3PHY] = &ccic3phy_clk.common.hw, ++ [CLK_APMU_CSI] = &csi_clk.common.hw, ++ [CLK_APMU_ISP_BUS] = &isp_bus_clk.common.hw, ++ [CLK_APMU_D1P_1228P8] = &d1p_1228p8.common.hw, ++ [CLK_APMU_D1P_819P2] = &d1p_819p2.common.hw, ++ [CLK_APMU_D1P_614P4] = &d1p_614p4.common.hw, ++ [CLK_APMU_D1P_491P52] = &d1p_491p52.common.hw, ++ [CLK_APMU_D1P_409P6] = &d1p_409p6.common.hw, ++ [CLK_APMU_D1P_307P2] = &d1p_307p2.common.hw, ++ [CLK_APMU_D1P_245P76] = &d1p_245p76.common.hw, ++ [CLK_APMU_V2D] = &v2d_clk.common.hw, ++ [CLK_APMU_DSI_ESC] = &dsi_esc_clk.common.hw, ++ [CLK_APMU_LCD_HCLK] = &lcd_hclk.common.hw, ++ [CLK_APMU_LCD_DSC] = &lcd_dsc_clk.common.hw, ++ [CLK_APMU_LCD_PXCLK] = &lcd_pxclk.common.hw, ++ [CLK_APMU_LCD_MCLK] = &lcd_mclk.common.hw, ++ [CLK_APMU_CCIC_4X] = &ccic_4x_clk.common.hw, ++ [CLK_APMU_CCIC1PHY] = &ccic1phy_clk.common.hw, ++ [CLK_APMU_SC2_HCLK] = &sc2_hclk.common.hw, ++ [CLK_APMU_SDH_AXI] = &sdh_axi_aclk.common.hw, ++ [CLK_APMU_SDH0] = &sdh0_clk.common.hw, ++ [CLK_APMU_SDH1] = &sdh1_clk.common.hw, ++ [CLK_APMU_SDH2] = &sdh2_clk.common.hw, ++ [CLK_APMU_USB2_BUS] = &usb2_bus_clk.common.hw, ++ [CLK_APMU_USB3_PORTA_BUS] = &usb3_porta_bus_clk.common.hw, ++ [CLK_APMU_USB3_PORTB_BUS] = &usb3_portb_bus_clk.common.hw, ++ [CLK_APMU_USB3_PORTC_BUS] = &usb3_portc_bus_clk.common.hw, ++ [CLK_APMU_USB3_PORTD_BUS] = &usb3_portd_bus_clk.common.hw, ++ [CLK_APMU_QSPI] = &qspi_clk.common.hw, ++ [CLK_APMU_QSPI_BUS] = &qspi_bus_clk.common.hw, ++ [CLK_APMU_DMA] = &dma_clk.common.hw, ++ [CLK_APMU_AES_WTM] = &aes_wtm_clk.common.hw, ++ [CLK_APMU_VPU] = &vpu_clk.common.hw, ++ [CLK_APMU_DTC] = &dtc_clk.common.hw, ++ [CLK_APMU_GPU] = &gpu_clk.common.hw, ++ [CLK_APMU_MC_AHB] = &mc_ahb_clk.common.hw, ++ [CLK_APMU_TOP_DCLK] = &top_dclk.common.hw, ++ [CLK_APMU_UCIE] = &ucie_clk.common.hw, ++ [CLK_APMU_UCIE_SBCLK] = &ucie_sbclk.common.hw, ++ [CLK_APMU_RCPU] = &rcpu_clk.common.hw, ++ [CLK_APMU_DSI4LN2_DSI_ESC] = &dsi4ln2_dsi_esc_clk.common.hw, ++ [CLK_APMU_DSI4LN2_LCD_DSC] = &dsi4ln2_lcd_dsc_clk.common.hw, ++ [CLK_APMU_DSI4LN2_LCD_PXCLK] = &dsi4ln2_lcd_pxclk.common.hw, ++ [CLK_APMU_DSI4LN2_LCD_MCLK] = &dsi4ln2_lcd_mclk.common.hw, ++ [CLK_APMU_DSI4LN2_DPU_ACLK] = &dsi4ln2_dpu_aclk.common.hw, ++ [CLK_APMU_DPU_ACLK] = &dpu_aclk.common.hw, ++ [CLK_APMU_UFS_ACLK] = &ufs_aclk.common.hw, ++ [CLK_APMU_EDP0_PXCLK] = &edp0_pxclk.common.hw, ++ [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, ++ [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw, ++ [CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw, ++ [CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw, ++ [CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw, ++ [CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw, ++ [CLK_APMU_EMAC0_RGMII_TX] = &emac0_rgmii_tx_clk.common.hw, ++ [CLK_APMU_EMAC1_BUS] = &emac1_bus_clk.common.hw, ++ [CLK_APMU_EMAC1_REF] = &emac1_ref_clk.common.hw, ++ [CLK_APMU_EMAC1_1588] = &emac1_1588_clk.common.hw, ++ [CLK_APMU_EMAC1_RGMII_TX] = &emac1_rgmii_tx_clk.common.hw, ++ [CLK_APMU_EMAC2_BUS] = &emac2_bus_clk.common.hw, ++ [CLK_APMU_EMAC2_REF] = &emac2_ref_clk.common.hw, ++ [CLK_APMU_EMAC2_1588] = &emac2_1588_clk.common.hw, ++ [CLK_APMU_EMAC2_RGMII_TX] = &emac2_rgmii_tx_clk.common.hw, ++ [CLK_APMU_ESPI_SCLK_SRC] = &espi_sclk_src.common.hw, ++ [CLK_APMU_ESPI_SCLK] = &espi_sclk.common.hw, ++ [CLK_APMU_ESPI_MCLK] = &espi_mclk.common.hw, ++ [CLK_APMU_CAM_SRC1] = &cam_src1_clk.common.hw, ++ [CLK_APMU_CAM_SRC2] = &cam_src2_clk.common.hw, ++ [CLK_APMU_CAM_SRC3] = &cam_src3_clk.common.hw, ++ [CLK_APMU_CAM_SRC4] = &cam_src4_clk.common.hw, ++ [CLK_APMU_ISIM_VCLK0] = &isim_vclk_out0.common.hw, ++ [CLK_APMU_ISIM_VCLK1] = &isim_vclk_out1.common.hw, ++ [CLK_APMU_ISIM_VCLK2] = &isim_vclk_out2.common.hw, ++ [CLK_APMU_ISIM_VCLK3] = &isim_vclk_out3.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_apmu_data = { ++ .reset_name = "k3-apmu-reset", ++ .hws = k3_ccu_apmu_hws, ++ .num = ARRAY_SIZE(k3_ccu_apmu_hws), ++}; ++ ++static struct clk_hw *k3_ccu_dciu_hws[] = { ++ [CLK_DCIU_HDMA] = &hdma_clk.common.hw, ++ [CLK_DCIU_DMA350] = &dma350_clk.common.hw, ++ [CLK_DCIU_C2_TCM_PIPE] = &c2_tcm_pipe_clk.common.hw, ++ [CLK_DCIU_C3_TCM_PIPE] = &c3_tcm_pipe_clk.common.hw, ++}; ++ ++static const struct spacemit_ccu_data k3_ccu_dciu_data = { ++ .reset_name = "k3-dciu-reset", ++ .hws = k3_ccu_dciu_hws, ++ .num = ARRAY_SIZE(k3_ccu_dciu_hws), ++}; ++ ++static const struct of_device_id of_k3_ccu_match[] = { ++ { ++ .compatible = "spacemit,k3-pll", ++ .data = &k3_ccu_pll_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-mpmu", ++ .data = &k3_ccu_mpmu_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-apbc", ++ .data = &k3_ccu_apbc_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-apmu", ++ .data = &k3_ccu_apmu_data, ++ }, ++ { ++ .compatible = "spacemit,k3-syscon-dciu", ++ .data = &k3_ccu_dciu_data, ++ }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, of_k3_ccu_match); ++ ++static int k3_ccu_probe(struct platform_device *pdev) ++{ ++ return spacemit_ccu_probe(pdev, "spacemit,k3-pll"); ++} ++ ++static struct platform_driver k3_ccu_driver = { ++ .driver = { ++ .name = "spacemit,k3-ccu", ++ .of_match_table = of_k3_ccu_match, ++ }, ++ .probe = k3_ccu_probe, ++}; ++module_platform_driver(k3_ccu_driver); ++ ++MODULE_IMPORT_NS("CLK_SPACEMIT"); ++MODULE_DESCRIPTION("SpacemiT K3 CCU driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0121-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch b/SPECS/linux-lts/0121-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch deleted file mode 100644 index 31fdf94a99..0000000000 --- a/SPECS/linux-lts/0121-UPSTREAM-clk-spacemit-ccu_pll-add-plla-type-clock.patch +++ /dev/null @@ -1,285 +0,0 @@ -From 8a1339992d26116b2566f2ad5313da25901e4b2a Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 27 Oct 2025 21:41:24 +0800 -Subject: [PATCH 121/467] UPSTREAM: clk: spacemit: ccu_pll: add plla type clock - -Introduce a new clock PLLA for SpacemiT's K3 SoC which has a different -register layout comparing to previous PPL type. And, It is configured -by swcr1, swcr3 and swcr2 BIT[15:8]. - -Link: https://lore.kernel.org/r/20260108-k3-clk-v5-3-42a11b74ad58@gentoo.org -Signed-off-by: Yixun Lan -(cherry picked from commit 3a086236c600739d6653c0405d86aff7d6f03c06) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu_common.h | 1 + - drivers/clk/spacemit/ccu_pll.c | 118 ++++++++++++++++++++++++++++++ - drivers/clk/spacemit/ccu_pll.h | 57 ++++++++++++--- - 3 files changed, 166 insertions(+), 10 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h -index 7ae244b5eace..8691698e007d 100644 ---- a/drivers/clk/spacemit/ccu_common.h -+++ b/drivers/clk/spacemit/ccu_common.h -@@ -26,6 +26,7 @@ struct ccu_common { - /* For PLL */ - struct { - u32 reg_swcr1; -+ u32 reg_swcr2; - u32 reg_swcr3; - }; - }; -diff --git a/drivers/clk/spacemit/ccu_pll.c b/drivers/clk/spacemit/ccu_pll.c -index 76d0244873d8..d4066a0ed452 100644 ---- a/drivers/clk/spacemit/ccu_pll.c -+++ b/drivers/clk/spacemit/ccu_pll.c -@@ -17,6 +17,9 @@ - #define PLL_SWCR3_EN ((u32)BIT(31)) - #define PLL_SWCR3_MASK GENMASK(30, 0) - -+#define PLLA_SWCR2_EN ((u32)BIT(16)) -+#define PLLA_SWCR2_MASK GENMASK(15, 8) -+ - static const struct ccu_pll_rate_tbl *ccu_pll_lookup_best_rate(struct ccu_pll *pll, - unsigned long rate) - { -@@ -148,6 +151,110 @@ static int ccu_pll_init(struct clk_hw *hw) - return 0; - } - -+static const struct ccu_pll_rate_tbl *ccu_plla_lookup_matched_entry(struct ccu_pll *pll) -+{ -+ struct ccu_pll_config *config = &pll->config; -+ const struct ccu_pll_rate_tbl *entry; -+ u32 i, swcr1, swcr2, swcr3; -+ -+ swcr1 = ccu_read(&pll->common, swcr1); -+ swcr2 = ccu_read(&pll->common, swcr2); -+ swcr2 &= PLLA_SWCR2_MASK; -+ swcr3 = ccu_read(&pll->common, swcr3); -+ -+ for (i = 0; i < config->tbl_num; i++) { -+ entry = &config->rate_tbl[i]; -+ -+ if (swcr1 == entry->swcr1 && -+ swcr2 == entry->swcr2 && -+ swcr3 == entry->swcr3) -+ return entry; -+ } -+ -+ return NULL; -+} -+ -+static void ccu_plla_update_param(struct ccu_pll *pll, const struct ccu_pll_rate_tbl *entry) -+{ -+ struct ccu_common *common = &pll->common; -+ -+ regmap_write(common->regmap, common->reg_swcr1, entry->swcr1); -+ regmap_write(common->regmap, common->reg_swcr3, entry->swcr3); -+ ccu_update(common, swcr2, PLLA_SWCR2_MASK, entry->swcr2); -+} -+ -+static int ccu_plla_is_enabled(struct clk_hw *hw) -+{ -+ struct ccu_common *common = hw_to_ccu_common(hw); -+ -+ return ccu_read(common, swcr2) & PLLA_SWCR2_EN; -+} -+ -+static int ccu_plla_enable(struct clk_hw *hw) -+{ -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ struct ccu_common *common = &pll->common; -+ unsigned int tmp; -+ -+ ccu_update(common, swcr2, PLLA_SWCR2_EN, PLLA_SWCR2_EN); -+ -+ /* check lock status */ -+ return regmap_read_poll_timeout_atomic(common->lock_regmap, -+ pll->config.reg_lock, -+ tmp, -+ tmp & pll->config.mask_lock, -+ PLL_DELAY_US, PLL_TIMEOUT_US); -+} -+ -+static void ccu_plla_disable(struct clk_hw *hw) -+{ -+ struct ccu_common *common = hw_to_ccu_common(hw); -+ -+ ccu_update(common, swcr2, PLLA_SWCR2_EN, 0); -+} -+ -+/* -+ * PLLAs must be gated before changing rate, which is ensured by -+ * flag CLK_SET_RATE_GATE. -+ */ -+static int ccu_plla_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ const struct ccu_pll_rate_tbl *entry; -+ -+ entry = ccu_pll_lookup_best_rate(pll, rate); -+ ccu_plla_update_param(pll, entry); -+ -+ return 0; -+} -+ -+static unsigned long ccu_plla_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ const struct ccu_pll_rate_tbl *entry; -+ -+ entry = ccu_plla_lookup_matched_entry(pll); -+ -+ WARN_ON_ONCE(!entry); -+ -+ return entry ? entry->rate : 0; -+} -+ -+static int ccu_plla_init(struct clk_hw *hw) -+{ -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ -+ if (ccu_plla_lookup_matched_entry(pll)) -+ return 0; -+ -+ ccu_plla_disable(hw); -+ ccu_plla_update_param(pll, &pll->config.rate_tbl[0]); -+ -+ return 0; -+} -+ - const struct clk_ops spacemit_ccu_pll_ops = { - .init = ccu_pll_init, - .enable = ccu_pll_enable, -@@ -158,3 +265,14 @@ const struct clk_ops spacemit_ccu_pll_ops = { - .is_enabled = ccu_pll_is_enabled, - }; - EXPORT_SYMBOL_NS_GPL(spacemit_ccu_pll_ops, "CLK_SPACEMIT"); -+ -+const struct clk_ops spacemit_ccu_plla_ops = { -+ .init = ccu_plla_init, -+ .enable = ccu_plla_enable, -+ .disable = ccu_plla_disable, -+ .set_rate = ccu_plla_set_rate, -+ .recalc_rate = ccu_plla_recalc_rate, -+ .determine_rate = ccu_pll_determine_rate, -+ .is_enabled = ccu_plla_is_enabled, -+}; -+EXPORT_SYMBOL_NS_GPL(spacemit_ccu_plla_ops, "CLK_SPACEMIT"); -diff --git a/drivers/clk/spacemit/ccu_pll.h b/drivers/clk/spacemit/ccu_pll.h -index 0592f4c3068c..e41db5c97c1a 100644 ---- a/drivers/clk/spacemit/ccu_pll.h -+++ b/drivers/clk/spacemit/ccu_pll.h -@@ -16,14 +16,31 @@ - * configuration. - * - * @rate: PLL rate -- * @swcr1: Register value of PLLX_SW1_CTRL (PLLx_SWCR1). -- * @swcr3: Register value of the PLLx_SW3_CTRL's lowest 31 bits of -- * PLLx_SW3_CTRL (PLLx_SWCR3). This highest bit is for enabling -- * the PLL and not contained in this field. -+ * @swcr1: Value of register PLLx_SW1_CTRL. -+ * @swcr2: Value of register PLLAx_SW2_CTRL. -+ * @swcr3: value of register PLLx_SW3_CTRL. -+ * -+ * See below tables for the register used in PPL/PPLA clocks -+ * -+ * Regular PLL type -+ * | Enable | swcr3 | PLLx_SW3_CTRL - BIT[31] | -+ * ----------------------------------------------- -+ * | Config | swcr1 | PLLx_SW1_CTRL - BIT[31:0] | -+ * | | swcr2 | Not used | -+ * | | swcr3 | PLLx_SW3_CTRL - BIT[30:0] | -+ * -+ * Special PLL type A -+ * | Enable | swcr2 | PLLAx_SW2_CTRL - BIT[16] | -+ * ----------------------------------------------- -+ * | Config | swcr1 | PLLAx_SW1_CTRL - BIT[31:0] | -+ * | | swcr2 | PLLAx_SW2_CTRL - BIT[15:8] | -+ * | | swcr3 | PLLAx_SW3_CTRL - BIT[31:0] | -+ * - */ - struct ccu_pll_rate_tbl { - unsigned long rate; - u32 swcr1; -+ u32 swcr2; - u32 swcr3; - }; - -@@ -36,11 +53,19 @@ struct ccu_pll_config { - - #define CCU_PLL_RATE(_rate, _swcr1, _swcr3) \ - { \ -- .rate = _rate, \ -+ .rate = _rate, \ - .swcr1 = _swcr1, \ - .swcr3 = _swcr3, \ - } - -+#define CCU_PLLA_RATE(_rate, _swcr1, _swcr2, _swcr3) \ -+ { \ -+ .rate = _rate, \ -+ .swcr1 = _swcr1, \ -+ .swcr2 = _swcr2, \ -+ .swcr3 = _swcr3, \ -+ } -+ - struct ccu_pll { - struct ccu_common common; - struct ccu_pll_config config; -@@ -54,26 +79,37 @@ struct ccu_pll { - .mask_lock = (_mask_lock), \ - } - --#define CCU_PLL_HWINIT(_name, _flags) \ -+#define CCU_PLL_COMMON_HWINIT(_name, _ops, _flags) \ - (&(struct clk_init_data) { \ - .name = #_name, \ -- .ops = &spacemit_ccu_pll_ops, \ -+ .ops = _ops, \ - .parent_data = &(struct clk_parent_data) { .index = 0 }, \ - .num_parents = 1, \ - .flags = _flags, \ - }) - --#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \ -- _mask_lock, _flags) \ -+#define CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ -+ _reg_lock, _mask_lock, _ops, _flags) \ - static struct ccu_pll _name = { \ - .config = CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock), \ - .common = { \ - .reg_swcr1 = _reg_swcr1, \ -+ .reg_swcr2 = _reg_swcr2, \ - .reg_swcr3 = _reg_swcr3, \ -- .hw.init = CCU_PLL_HWINIT(_name, _flags) \ -+ .hw.init = CCU_PLL_COMMON_HWINIT(_name, _ops, _flags) \ - } \ - } - -+#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \ -+ _mask_lock, _flags) \ -+ CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, 0, _reg_swcr3, \ -+ _reg_lock, _mask_lock, &spacemit_ccu_pll_ops, _flags) -+ -+#define CCU_PLLA_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ -+ _reg_lock, _mask_lock, _flags) \ -+ CCU_PLL_X_DEFINE(_name, _table, _reg_swcr1, _reg_swcr2, _reg_swcr3, \ -+ _reg_lock, _mask_lock, &spacemit_ccu_plla_ops, _flags) -+ - static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw) - { - struct ccu_common *common = hw_to_ccu_common(hw); -@@ -82,5 +118,6 @@ static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw) - } - - extern const struct clk_ops spacemit_ccu_pll_ops; -+extern const struct clk_ops spacemit_ccu_plla_ops; - - #endif --- -2.53.0 - diff --git a/SPECS/linux-lts/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch b/SPECS/linux-lts/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch new file mode 100644 index 0000000000..c049403590 --- /dev/null +++ b/SPECS/linux-lts/0121-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch @@ -0,0 +1,235 @@ +From c8b8aab18243d5ad3ee4a6b980f1448aee344adb Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 20 Jan 2026 19:10:49 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: soc: spacemit: Add K3 reset + support and IDs + +Update the spacemit,k1-syscon.yaml binding to document K3 SoC reset +support. + +K3 reset devices are registered at runtime as auxiliary devices by the +K3 CCU driver. Since K3 reuses the K1 syscon binding, there is no separate +YAML binding file for K3 resets. + +Update #reset-cells description to document where reset IDs are defined. + +Acked-by: Alex Elder +Acked-by: Krzysztof Kozlowski +Signed-off-by: Guodong Xu +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] +Signed-off-by: Philipp Zabel +(cherry picked from commit 216e0a5e98e5f0f02a818884e8acf340892cecae) +Signed-off-by: Han Gao +--- + .../soc/spacemit/spacemit,k1-syscon.yaml | 8 +- + .../dt-bindings/reset/spacemit,k3-resets.h | 171 ++++++++++++++++++ + 2 files changed, 178 insertions(+), 1 deletion(-) + create mode 100644 include/dt-bindings/reset/spacemit,k3-resets.h + +diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +index d87131da30bc..d3a7c93c3c54 100644 +--- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml ++++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +@@ -10,7 +10,7 @@ maintainers: + - Haylen Chu + + description: +- System controllers found on SpacemiT K1 SoC, which are capable of ++ System controllers found on SpacemiT K1/K3 SoC, which are capable of + clock, reset and power-management functions. + + properties: +@@ -51,6 +51,12 @@ properties: + + "#reset-cells": + const: 1 ++ description: | ++ ID of the reset controller line. Valid IDs are defined in corresponding ++ files: ++ ++ For SpacemiT K1, see include/dt-bindings/clock/spacemit,k1-syscon.h ++ For SpacemiT K3, see include/dt-bindings/reset/spacemit,k3-resets.h + + required: + - compatible +diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h +new file mode 100644 +index 000000000000..79ac1c22b7b5 +--- /dev/null ++++ b/include/dt-bindings/reset/spacemit,k3-resets.h +@@ -0,0 +1,171 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ ++ ++#ifndef _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ ++#define _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ ++ ++/* MPMU resets */ ++#define RESET_MPMU_WDT 0 ++#define RESET_MPMU_RIPC 1 ++ ++/* APBC resets */ ++#define RESET_APBC_UART0 0 ++#define RESET_APBC_UART2 1 ++#define RESET_APBC_UART3 2 ++#define RESET_APBC_UART4 3 ++#define RESET_APBC_UART5 4 ++#define RESET_APBC_UART6 5 ++#define RESET_APBC_UART7 6 ++#define RESET_APBC_UART8 7 ++#define RESET_APBC_UART9 8 ++#define RESET_APBC_UART10 9 ++#define RESET_APBC_GPIO 10 ++#define RESET_APBC_PWM0 11 ++#define RESET_APBC_PWM1 12 ++#define RESET_APBC_PWM2 13 ++#define RESET_APBC_PWM3 14 ++#define RESET_APBC_PWM4 15 ++#define RESET_APBC_PWM5 16 ++#define RESET_APBC_PWM6 17 ++#define RESET_APBC_PWM7 18 ++#define RESET_APBC_PWM8 19 ++#define RESET_APBC_PWM9 20 ++#define RESET_APBC_PWM10 21 ++#define RESET_APBC_PWM11 22 ++#define RESET_APBC_PWM12 23 ++#define RESET_APBC_PWM13 24 ++#define RESET_APBC_PWM14 25 ++#define RESET_APBC_PWM15 26 ++#define RESET_APBC_PWM16 27 ++#define RESET_APBC_PWM17 28 ++#define RESET_APBC_PWM18 29 ++#define RESET_APBC_PWM19 30 ++#define RESET_APBC_SPI0 31 ++#define RESET_APBC_SPI1 32 ++#define RESET_APBC_SPI3 33 ++#define RESET_APBC_RTC 34 ++#define RESET_APBC_TWSI0 35 ++#define RESET_APBC_TWSI1 36 ++#define RESET_APBC_TWSI2 37 ++#define RESET_APBC_TWSI4 38 ++#define RESET_APBC_TWSI5 39 ++#define RESET_APBC_TWSI6 40 ++#define RESET_APBC_TWSI8 41 ++#define RESET_APBC_TIMERS0 42 ++#define RESET_APBC_TIMERS1 43 ++#define RESET_APBC_TIMERS2 44 ++#define RESET_APBC_TIMERS3 45 ++#define RESET_APBC_TIMERS4 46 ++#define RESET_APBC_TIMERS5 47 ++#define RESET_APBC_TIMERS6 48 ++#define RESET_APBC_TIMERS7 49 ++#define RESET_APBC_AIB 50 ++#define RESET_APBC_ONEWIRE 51 ++#define RESET_APBC_I2S0 52 ++#define RESET_APBC_I2S1 53 ++#define RESET_APBC_I2S2 54 ++#define RESET_APBC_I2S3 55 ++#define RESET_APBC_I2S4 56 ++#define RESET_APBC_I2S5 57 ++#define RESET_APBC_DRO 58 ++#define RESET_APBC_IR0 59 ++#define RESET_APBC_IR1 60 ++#define RESET_APBC_TSEN 61 ++#define RESET_IPC_AP2AUD 62 ++#define RESET_APBC_CAN0 63 ++#define RESET_APBC_CAN1 64 ++#define RESET_APBC_CAN2 65 ++#define RESET_APBC_CAN3 66 ++#define RESET_APBC_CAN4 67 ++ ++/* APMU resets */ ++#define RESET_APMU_CSI 0 ++#define RESET_APMU_CCIC2PHY 1 ++#define RESET_APMU_CCIC3PHY 2 ++#define RESET_APMU_ISP_CIBUS 3 ++#define RESET_APMU_DSI_ESC 4 ++#define RESET_APMU_LCD 5 ++#define RESET_APMU_V2D 6 ++#define RESET_APMU_LCD_MCLK 7 ++#define RESET_APMU_LCD_DSCCLK 8 ++#define RESET_APMU_SC2_HCLK 9 ++#define RESET_APMU_CCIC_4X 10 ++#define RESET_APMU_CCIC1_PHY 11 ++#define RESET_APMU_SDH_AXI 12 ++#define RESET_APMU_SDH0 13 ++#define RESET_APMU_SDH1 14 ++#define RESET_APMU_SDH2 15 ++#define RESET_APMU_USB2 16 ++#define RESET_APMU_USB3_PORTA 17 ++#define RESET_APMU_USB3_PORTB 18 ++#define RESET_APMU_USB3_PORTC 19 ++#define RESET_APMU_USB3_PORTD 20 ++#define RESET_APMU_QSPI 21 ++#define RESET_APMU_QSPI_BUS 22 ++#define RESET_APMU_DMA 23 ++#define RESET_APMU_AES_WTM 24 ++#define RESET_APMU_MCB_DCLK 25 ++#define RESET_APMU_MCB_ACLK 26 ++#define RESET_APMU_VPU 27 ++#define RESET_APMU_DTC 28 ++#define RESET_APMU_GPU 29 ++#define RESET_APMU_ALZO 30 ++#define RESET_APMU_MC 31 ++#define RESET_APMU_CPU0_POP 32 ++#define RESET_APMU_CPU0_SW 33 ++#define RESET_APMU_CPU1_POP 34 ++#define RESET_APMU_CPU1_SW 35 ++#define RESET_APMU_CPU2_POP 36 ++#define RESET_APMU_CPU2_SW 37 ++#define RESET_APMU_CPU3_POP 38 ++#define RESET_APMU_CPU3_SW 39 ++#define RESET_APMU_C0_MPSUB_SW 40 ++#define RESET_APMU_CPU4_POP 41 ++#define RESET_APMU_CPU4_SW 42 ++#define RESET_APMU_CPU5_POP 43 ++#define RESET_APMU_CPU5_SW 44 ++#define RESET_APMU_CPU6_POP 45 ++#define RESET_APMU_CPU6_SW 46 ++#define RESET_APMU_CPU7_POP 47 ++#define RESET_APMU_CPU7_SW 48 ++#define RESET_APMU_C1_MPSUB_SW 49 ++#define RESET_APMU_MPSUB_DBG 50 ++#define RESET_APMU_UCIE 51 ++#define RESET_APMU_RCPU 52 ++#define RESET_APMU_DSI4LN2_ESCCLK 53 ++#define RESET_APMU_DSI4LN2_LCD_SW 54 ++#define RESET_APMU_DSI4LN2_LCD_MCLK 55 ++#define RESET_APMU_DSI4LN2_LCD_DSCCLK 56 ++#define RESET_APMU_DSI4LN2_DPU_ACLK 57 ++#define RESET_APMU_DPU_ACLK 58 ++#define RESET_APMU_UFS_ACLK 59 ++#define RESET_APMU_EDP0 60 ++#define RESET_APMU_EDP1 61 ++#define RESET_APMU_PCIE_PORTA 62 ++#define RESET_APMU_PCIE_PORTB 63 ++#define RESET_APMU_PCIE_PORTC 64 ++#define RESET_APMU_PCIE_PORTD 65 ++#define RESET_APMU_PCIE_PORTE 66 ++#define RESET_APMU_EMAC0 67 ++#define RESET_APMU_EMAC1 68 ++#define RESET_APMU_EMAC2 69 ++#define RESET_APMU_ESPI_MCLK 70 ++#define RESET_APMU_ESPI_SCLK 71 ++ ++/* DCIU resets*/ ++#define RESET_DCIU_HDMA 0 ++#define RESET_DCIU_DMA350 1 ++#define RESET_DCIU_DMA350_0 2 ++#define RESET_DCIU_DMA350_1 3 ++#define RESET_DCIU_AXIDMA0 4 ++#define RESET_DCIU_AXIDMA1 5 ++#define RESET_DCIU_AXIDMA2 6 ++#define RESET_DCIU_AXIDMA3 7 ++#define RESET_DCIU_AXIDMA4 8 ++#define RESET_DCIU_AXIDMA5 9 ++#define RESET_DCIU_AXIDMA6 10 ++#define RESET_DCIU_AXIDMA7 11 ++ ++#endif /* _DT_BINDINGS_RESET_SPACEMIT_K3_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0122-UPSTREAM-clk-spacemit-k3-extract-common-header.patch b/SPECS/linux-lts/0122-UPSTREAM-clk-spacemit-k3-extract-common-header.patch deleted file mode 100644 index deefe5b921..0000000000 --- a/SPECS/linux-lts/0122-UPSTREAM-clk-spacemit-k3-extract-common-header.patch +++ /dev/null @@ -1,299 +0,0 @@ -From 3b39ff3c0baef35c207ed2fe3f34137a9a874573 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sat, 20 Dec 2025 21:28:15 +0800 -Subject: [PATCH 122/467] UPSTREAM: clk: spacemit: k3: extract common header - -Extracting common header file, which will be shared by clock and reset -drivers. So will make it easy to add reset driver for K3 SoC later. - -Link: https://lore.kernel.org/r/20260108-k3-clk-v5-4-42a11b74ad58@gentoo.org -Signed-off-by: Yixun Lan -(cherry picked from commit 091d19cc24018f2bd783e932fb2403cb7a2bdb3c) -Signed-off-by: Han Gao ---- - include/soc/spacemit/k3-syscon.h | 273 +++++++++++++++++++++++++++++++ - 1 file changed, 273 insertions(+) - create mode 100644 include/soc/spacemit/k3-syscon.h - -diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h -new file mode 100644 -index 000000000000..0299bea065a0 ---- /dev/null -+++ b/include/soc/spacemit/k3-syscon.h -@@ -0,0 +1,273 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* SpacemiT clock and reset driver definitions for the K3 SoC */ -+ -+#ifndef __SOC_K3_SYSCON_H__ -+#define __SOC_K3_SYSCON_H__ -+ -+#include "ccu.h" -+ -+/* APBS register offset */ -+#define APBS_PLL1_SWCR1 0x100 -+#define APBS_PLL1_SWCR2 0x104 -+#define APBS_PLL1_SWCR3 0x108 -+#define APBS_PLL2_SWCR1 0x118 -+#define APBS_PLL2_SWCR2 0x11c -+#define APBS_PLL2_SWCR3 0x120 -+#define APBS_PLL3_SWCR1 0x124 -+#define APBS_PLL3_SWCR2 0x128 -+#define APBS_PLL3_SWCR3 0x12c -+#define APBS_PLL4_SWCR1 0x130 -+#define APBS_PLL4_SWCR2 0x134 -+#define APBS_PLL4_SWCR3 0x138 -+#define APBS_PLL5_SWCR1 0x13c -+#define APBS_PLL5_SWCR2 0x140 -+#define APBS_PLL5_SWCR3 0x144 -+#define APBS_PLL6_SWCR1 0x148 -+#define APBS_PLL6_SWCR2 0x14c -+#define APBS_PLL6_SWCR3 0x150 -+#define APBS_PLL7_SWCR1 0x158 -+#define APBS_PLL7_SWCR2 0x15c -+#define APBS_PLL7_SWCR3 0x160 -+#define APBS_PLL8_SWCR1 0x180 -+#define APBS_PLL8_SWCR2 0x184 -+#define APBS_PLL8_SWCR3 0x188 -+ -+/* MPMU register offset */ -+#define MPMU_FCCR 0x0008 -+#define MPMU_POSR 0x0010 -+#define POSR_PLL1_LOCK BIT(24) -+#define POSR_PLL2_LOCK BIT(25) -+#define POSR_PLL3_LOCK BIT(26) -+#define POSR_PLL4_LOCK BIT(27) -+#define POSR_PLL5_LOCK BIT(28) -+#define POSR_PLL6_LOCK BIT(29) -+#define POSR_PLL7_LOCK BIT(30) -+#define POSR_PLL8_LOCK BIT(31) -+#define MPMU_SUCCR 0x0014 -+#define MPMU_ISCCR 0x0044 -+#define MPMU_WDTPCR 0x0200 -+#define MPMU_RIPCCR 0x0210 -+#define MPMU_ACGR 0x1024 -+#define MPMU_APBCSCR 0x1050 -+#define MPMU_SUCCR_1 0x10b0 -+ -+#define MPMU_I2S0_SYSCLK 0x1100 -+#define MPMU_I2S2_SYSCLK 0x1104 -+#define MPMU_I2S3_SYSCLK 0x1108 -+#define MPMU_I2S4_SYSCLK 0x110c -+#define MPMU_I2S5_SYSCLK 0x1110 -+#define MPMU_I2S_SYSCLK_CTRL 0x1114 -+ -+/* APBC register offset */ -+#define APBC_UART0_CLK_RST 0x00 -+#define APBC_UART2_CLK_RST 0x04 -+#define APBC_GPIO_CLK_RST 0x08 -+#define APBC_PWM0_CLK_RST 0x0c -+#define APBC_PWM1_CLK_RST 0x10 -+#define APBC_PWM2_CLK_RST 0x14 -+#define APBC_PWM3_CLK_RST 0x18 -+#define APBC_TWSI8_CLK_RST 0x20 -+#define APBC_UART3_CLK_RST 0x24 -+#define APBC_RTC_CLK_RST 0x28 -+#define APBC_TWSI0_CLK_RST 0x2c -+#define APBC_TWSI1_CLK_RST 0x30 -+#define APBC_TIMERS0_CLK_RST 0x34 -+#define APBC_TWSI2_CLK_RST 0x38 -+#define APBC_AIB_CLK_RST 0x3c -+#define APBC_TWSI4_CLK_RST 0x40 -+#define APBC_TIMERS1_CLK_RST 0x44 -+#define APBC_ONEWIRE_CLK_RST 0x48 -+#define APBC_TWSI5_CLK_RST 0x4c -+#define APBC_DRO_CLK_RST 0x58 -+#define APBC_IR0_CLK_RST 0x5c -+#define APBC_IR1_CLK_RST 0x1c -+#define APBC_TWSI6_CLK_RST 0x60 -+#define APBC_COUNTER_CLK_SEL 0x64 -+#define APBC_TSEN_CLK_RST 0x6c -+#define APBC_UART4_CLK_RST 0x70 -+#define APBC_UART5_CLK_RST 0x74 -+#define APBC_UART6_CLK_RST 0x78 -+#define APBC_SSP3_CLK_RST 0x7c -+#define APBC_SSPA0_CLK_RST 0x80 -+#define APBC_SSPA1_CLK_RST 0x84 -+#define APBC_SSPA2_CLK_RST 0x88 -+#define APBC_SSPA3_CLK_RST 0x8c -+#define APBC_IPC_AP2AUD_CLK_RST 0x90 -+#define APBC_UART7_CLK_RST 0x94 -+#define APBC_UART8_CLK_RST 0x98 -+#define APBC_UART9_CLK_RST 0x9c -+#define APBC_CAN0_CLK_RST 0xa0 -+#define APBC_CAN1_CLK_RST 0xa4 -+#define APBC_PWM4_CLK_RST 0xa8 -+#define APBC_PWM5_CLK_RST 0xac -+#define APBC_PWM6_CLK_RST 0xb0 -+#define APBC_PWM7_CLK_RST 0xb4 -+#define APBC_PWM8_CLK_RST 0xb8 -+#define APBC_PWM9_CLK_RST 0xbc -+#define APBC_PWM10_CLK_RST 0xc0 -+#define APBC_PWM11_CLK_RST 0xc4 -+#define APBC_PWM12_CLK_RST 0xc8 -+#define APBC_PWM13_CLK_RST 0xcc -+#define APBC_PWM14_CLK_RST 0xd0 -+#define APBC_PWM15_CLK_RST 0xd4 -+#define APBC_PWM16_CLK_RST 0xd8 -+#define APBC_PWM17_CLK_RST 0xdc -+#define APBC_PWM18_CLK_RST 0xe0 -+#define APBC_PWM19_CLK_RST 0xe4 -+#define APBC_TIMERS2_CLK_RST 0x11c -+#define APBC_TIMERS3_CLK_RST 0x120 -+#define APBC_TIMERS4_CLK_RST 0x124 -+#define APBC_TIMERS5_CLK_RST 0x128 -+#define APBC_TIMERS6_CLK_RST 0x12c -+#define APBC_TIMERS7_CLK_RST 0x130 -+ -+#define APBC_CAN2_CLK_RST 0x148 -+#define APBC_CAN3_CLK_RST 0x14c -+#define APBC_CAN4_CLK_RST 0x150 -+#define APBC_UART10_CLK_RST 0x154 -+#define APBC_SSP0_CLK_RST 0x158 -+#define APBC_SSP1_CLK_RST 0x15c -+#define APBC_SSPA4_CLK_RST 0x160 -+#define APBC_SSPA5_CLK_RST 0x164 -+ -+/* APMU register offset */ -+#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 -+#define APMU_ISP_CLK_RES_CTRL 0x038 -+#define APMU_PMU_CLK_GATE_CTRL 0x040 -+#define APMU_LCD_CLK_RES_CTRL1 0x044 -+#define APMU_LCD_SPI_CLK_RES_CTRL 0x048 -+#define APMU_LCD_CLK_RES_CTRL2 0x04c -+#define APMU_CCIC_CLK_RES_CTRL 0x050 -+#define APMU_SDH0_CLK_RES_CTRL 0x054 -+#define APMU_SDH1_CLK_RES_CTRL 0x058 -+#define APMU_USB_CLK_RES_CTRL 0x05c -+#define APMU_QSPI_CLK_RES_CTRL 0x060 -+#define APMU_DMA_CLK_RES_CTRL 0x064 -+#define APMU_AES_CLK_RES_CTRL 0x068 -+#define APMU_MCB_CLK_RES_CTRL 0x06c -+#define APMU_VPU_CLK_RES_CTRL 0x0a4 -+#define APMU_DTC_CLK_RES_CTRL 0x0ac -+#define APMU_GPU_CLK_RES_CTRL 0x0cc -+#define APMU_SDH2_CLK_RES_CTRL 0x0e0 -+#define APMU_PMUA_MC_CTRL 0x0e8 -+#define APMU_PMU_CC2_AP 0x100 -+#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 -+#define APMU_UCIE_CTRL 0x11c -+#define APMU_RCPU_CLK_RES_CTRL 0x14c -+#define APMU_TOP_DCLK_CTRL 0x158 -+#define APMU_LCD_EDP_CTRL 0x23c -+#define APMU_UFS_CLK_RES_CTRL 0x268 -+#define APMU_LCD_CLK_RES_CTRL3 0x26c -+#define APMU_LCD_CLK_RES_CTRL4 0x270 -+#define APMU_LCD_CLK_RES_CTRL5 0x274 -+#define APMU_CCI550_CLK_CTRL 0x300 -+#define APMU_ACLK_CLK_CTRL 0x388 -+#define APMU_CPU_C0_CLK_CTRL 0x38C -+#define APMU_CPU_C1_CLK_CTRL 0x390 -+#define APMU_CPU_C2_CLK_CTRL 0x394 -+#define APMU_CPU_C3_CLK_CTRL 0x208 -+#define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 -+#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 -+#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 -+#define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 -+#define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 -+#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 -+#define APMU_EMAC1_CLK_RES_CTRL 0x3ec -+#define APMU_EMAC2_CLK_RES_CTRL 0x248 -+#define APMU_ESPI_CLK_RES_CTRL 0x240 -+#define APMU_SNR_ISIM_VCLK_CTRL 0x3f8 -+ -+/* DCIU register offsets */ -+#define DCIU_DMASYS_CLK_EN 0x234 -+#define DCIU_DMASYS_SDMA_CLK_EN 0x238 -+#define DCIU_C2_TCM_PIPE_CLK 0x244 -+#define DCIU_C3_TCM_PIPE_CLK 0x248 -+ -+#define DCIU_DMASYS_S0_RSTN 0x204 -+#define DCIU_DMASYS_S1_RSTN 0x208 -+#define DCIU_DMASYS_A0_RSTN 0x20C -+#define DCIU_DMASYS_A1_RSTN 0x210 -+#define DCIU_DMASYS_A2_RSTN 0x214 -+#define DCIU_DMASYS_A3_RSTN 0x218 -+#define DCIU_DMASYS_A4_RSTN 0x21C -+#define DCIU_DMASYS_A5_RSTN 0x220 -+#define DCIU_DMASYS_A6_RSTN 0x224 -+#define DCIU_DMASYS_A7_RSTN 0x228 -+#define DCIU_DMASYS_RSTN 0x22C -+#define DCIU_DMASYS_SDMA_RSTN 0x230 -+ -+/* RCPU SYSCTRL register offsets */ -+#define RCPU_CAN_CLK_RST 0x4c -+#define RCPU_CAN1_CLK_RST 0xF0 -+#define RCPU_CAN2_CLK_RST 0xF4 -+#define RCPU_CAN3_CLK_RST 0xF8 -+#define RCPU_CAN4_CLK_RST 0xFC -+#define RCPU_IRC_CLK_RST 0x48 -+#define RCPU_IRC1_CLK_RST 0xEC -+#define RCPU_GMAC_CLK_RST 0xE4 -+#define RCPU_ESPI_CLK_RST 0xDC -+#define RCPU_AUDIO_I2S0_SYS_CLK_CTRL 0x70 -+#define RCPU_AUDIO_I2S1_SYS_CLK_CTRL 0x44 -+ -+/* RCPU UARTCTRL register offsets */ -+#define RCPU1_UART0_CLK_RST 0x00 -+#define RCPU1_UART1_CLK_RST 0x04 -+#define RCPU1_UART2_CLK_RST 0x08 -+#define RCPU1_UART3_CLK_RST 0x0c -+#define RCPU1_UART4_CLK_RST 0x10 -+#define RCPU1_UART5_CLK_RST 0x14 -+ -+/* RCPU I2SCTRL register offsets */ -+#define RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL 0x60 -+#define RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL 0x64 -+#define RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL 0x68 -+#define RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL 0x6C -+ -+#define RCPU2_AUDIO_I2S2_SYS_CLK_CTRL 0x44 -+#define RCPU2_AUDIO_I2S3_SYS_CLK_CTRL 0x54 -+ -+/* RCPU SPICTRL register offsets */ -+#define RCPU3_SSP0_CLK_RST 0x00 -+#define RCPU3_SSP1_CLK_RST 0x04 -+#define RCPU3_PWR_SSP_CLK_RST 0x08 -+ -+/* RCPU I2CCTRL register offsets */ -+#define RCPU4_I2C0_CLK_RST 0x00 -+#define RCPU4_I2C1_CLK_RST 0x04 -+#define RCPU4_PWR_I2C_CLK_RST 0x08 -+ -+/* RPMU register offsets */ -+#define RCPU5_AON_PER_CLK_RST_CTRL 0x2C -+#define RCPU5_TIMER1_CLK_RST 0x4C -+#define RCPU5_TIMER2_CLK_RST 0x70 -+#define RCPU5_TIMER3_CLK_RST 0x78 -+#define RCPU5_TIMER4_CLK_RST 0x7C -+#define RCPU5_GPIO_AND_EDGE_CLK_RST 0x74 -+#define RCPU5_RCPU_BUS_CLK_CTRL 0xC0 -+#define RCPU5_RT24_CORE0_CLK_CTRL 0xC4 -+#define RCPU5_RT24_CORE1_CLK_CTRL 0xC8 -+#define RCPU5_RT24_CORE0_SW_RESET 0xCC -+#define RCPU5_RT24_CORE1_SW_RESET 0xD0 -+ -+/* RCPU PWMCTRL register offsets */ -+#define RCPU6_PWM0_CLK_RST 0x00 -+#define RCPU6_PWM1_CLK_RST 0x04 -+#define RCPU6_PWM2_CLK_RST 0x08 -+#define RCPU6_PWM3_CLK_RST 0x0c -+#define RCPU6_PWM4_CLK_RST 0x10 -+#define RCPU6_PWM5_CLK_RST 0x14 -+#define RCPU6_PWM6_CLK_RST 0x18 -+#define RCPU6_PWM7_CLK_RST 0x1c -+#define RCPU6_PWM8_CLK_RST 0x20 -+#define RCPU6_PWM9_CLK_RST 0x24 -+ -+/* APBC2 SEC register offsets */ -+#define APBC2_UART1_CLK_RST 0x00 -+#define APBC2_SSP2_CLK_RST 0x04 -+#define APBC2_TWSI3_CLK_RST 0x08 -+#define APBC2_RTC_CLK_RST 0x0c -+#define APBC2_TIMERS_CLK_RST 0x10 -+#define APBC2_GPIO_CLK_RST 0x1c -+ -+#endif /* __SOC_K3_SYSCON_H__ */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch b/SPECS/linux-lts/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch new file mode 100644 index 0000000000..6775e0de91 --- /dev/null +++ b/SPECS/linux-lts/0122-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch @@ -0,0 +1,124 @@ +From f58dcbda59da2a11300427e92f4c1abb7c6898f7 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 20 Jan 2026 19:10:50 +0800 +Subject: [RUYI PATCH] UPSTREAM: reset: Create subdirectory for SpacemiT + drivers + +Create a dedicated subdirectory for SpacemiT reset drivers to allow +for better organization as support for more SoCs is added. + +Move the existing K1 reset driver into this new directory and rename +it to reset-spacemit-k1.c. + +Rename the Kconfig symbol to RESET_SPACEMIT_K1 and update its default +from ARCH_SPACEMIT to SPACEMIT_K1_CCU. The reset driver depends on the +clock driver to register reset devices as an auxiliary device, so the +default should reflect this dependency. + +Also sort the drivers/reset/Kconfig entries alphabetically. + +Reviewed-by: Alex Elder +Signed-off-by: Guodong Xu +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] +Signed-off-by: Philipp Zabel +(cherry picked from commit 2875b4b5d2657ff2fd979103d88e9afcae51481c) +Signed-off-by: Han Gao +--- + drivers/reset/Kconfig | 12 ++---------- + drivers/reset/Makefile | 2 +- + drivers/reset/spacemit/Kconfig | 14 ++++++++++++++ + drivers/reset/spacemit/Makefile | 2 ++ + .../reset-spacemit-k1.c} | 0 + 5 files changed, 19 insertions(+), 11 deletions(-) + create mode 100644 drivers/reset/spacemit/Kconfig + create mode 100644 drivers/reset/spacemit/Makefile + rename drivers/reset/{reset-spacemit.c => spacemit/reset-spacemit-k1.c} (100%) + +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index b3b9e0f9d8c4..096f57fb7ccf 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -286,15 +286,6 @@ config RESET_SOCFPGA + This enables the reset driver for the SoCFPGA ARMv7 platforms. This + driver gets initialized early during platform init calls. + +-config RESET_SPACEMIT +- tristate "SpacemiT reset driver" +- depends on ARCH_SPACEMIT || COMPILE_TEST +- select AUXILIARY_BUS +- default ARCH_SPACEMIT +- help +- This enables the reset controller driver for SpacemiT SoCs, +- including the K1. +- + config RESET_SUNPLUS + bool "Sunplus SoCs Reset Driver" if COMPILE_TEST + default ARCH_SUNPLUS +@@ -393,9 +384,10 @@ config RESET_ZYNQMP + This enables the reset controller driver for Xilinx ZynqMP SoCs. + + source "drivers/reset/amlogic/Kconfig" ++source "drivers/reset/hisilicon/Kconfig" ++source "drivers/reset/spacemit/Kconfig" + source "drivers/reset/starfive/Kconfig" + source "drivers/reset/sti/Kconfig" +-source "drivers/reset/hisilicon/Kconfig" + source "drivers/reset/tegra/Kconfig" + + endif +diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile +index f7934f9fb90b..e0934ab7153c 100644 +--- a/drivers/reset/Makefile ++++ b/drivers/reset/Makefile +@@ -2,6 +2,7 @@ + obj-y += core.o + obj-y += amlogic/ + obj-y += hisilicon/ ++obj-y += spacemit/ + obj-y += starfive/ + obj-y += sti/ + obj-y += tegra/ +@@ -37,7 +38,6 @@ obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o + obj-$(CONFIG_RESET_SCMI) += reset-scmi.o + obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o + obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o +-obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o + obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o + obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o + obj-$(CONFIG_RESET_TH1520) += reset-th1520.o +diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig +new file mode 100644 +index 000000000000..552884e8b72a +--- /dev/null ++++ b/drivers/reset/spacemit/Kconfig +@@ -0,0 +1,14 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config RESET_SPACEMIT_K1 ++ tristate "SpacemiT K1 reset driver" ++ depends on ARCH_SPACEMIT || COMPILE_TEST ++ depends on SPACEMIT_K1_CCU ++ select AUXILIARY_BUS ++ default SPACEMIT_K1_CCU ++ help ++ Support for reset controller in SpacemiT K1 SoC. ++ This driver works with the SpacemiT K1 clock controller ++ unit (CCU) driver to provide reset control functionality ++ for various peripherals and subsystems in the SoC. ++ +diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile +new file mode 100644 +index 000000000000..34e3350136bb +--- /dev/null ++++ b/drivers/reset/spacemit/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o +diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/spacemit/reset-spacemit-k1.c +similarity index 100% +rename from drivers/reset/reset-spacemit.c +rename to drivers/reset/spacemit/reset-spacemit-k1.c +-- +2.53.0 + diff --git a/SPECS/linux-lts/0123-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch b/SPECS/linux-lts/0123-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch deleted file mode 100644 index 606059384f..0000000000 --- a/SPECS/linux-lts/0123-UPSTREAM-clk-spacemit-k3-add-the-clock-tree.patch +++ /dev/null @@ -1,1541 +0,0 @@ -From 762b40db00f83f963c11e08eb0a8b6a4ed8d3e58 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sun, 2 Nov 2025 21:17:17 +0800 -Subject: [PATCH 123/467] UPSTREAM: clk: spacemit: k3: add the clock tree - -Add clock support to SpacemiT K3 SoC, the clock tree consist of several -blocks which are APBC, APBS, APMU, DCIU, MPUM. - -Link: https://lore.kernel.org/r/20260108-k3-clk-v5-5-42a11b74ad58@gentoo.org -Signed-off-by: Yixun Lan -(cherry picked from commit e371a77255b837f5d64c9d2520f87e41ea5350b9) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/Kconfig | 6 + - drivers/clk/spacemit/Makefile | 3 + - drivers/clk/spacemit/ccu-k3.c | 1487 +++++++++++++++++++++++++++++++++ - 3 files changed, 1496 insertions(+) - create mode 100644 drivers/clk/spacemit/ccu-k3.c - -diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig -index 3351e8bc801d..4ebe6aaa1980 100644 ---- a/drivers/clk/spacemit/Kconfig -+++ b/drivers/clk/spacemit/Kconfig -@@ -14,4 +14,10 @@ config SPACEMIT_K1_CCU - help - Support for clock controller unit in SpacemiT K1 SoC. - -+config SPACEMIT_K3_CCU -+ tristate "Support for SpacemiT K3 SoC" -+ select SPACEMIT_CCU -+ help -+ Support for clock controller unit in SpacemiT K3 SoC. -+ - endmenu -diff --git a/drivers/clk/spacemit/Makefile b/drivers/clk/spacemit/Makefile -index ad2bf315109b..0925eda384b4 100644 ---- a/drivers/clk/spacemit/Makefile -+++ b/drivers/clk/spacemit/Makefile -@@ -8,3 +8,6 @@ spacemit-ccu-y += ccu_ddn.o - - obj-$(CONFIG_SPACEMIT_K1_CCU) += spacemit-ccu-k1.o - spacemit-ccu-k1-y += ccu-k1.o -+ -+obj-$(CONFIG_SPACEMIT_K3_CCU) += spacemit-ccu-k3.o -+spacemit-ccu-k3-y += ccu-k3.o -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -new file mode 100644 -index 000000000000..e98afd59f05c ---- /dev/null -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -0,0 +1,1487 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "ccu_common.h" -+#include "ccu_pll.h" -+#include "ccu_mix.h" -+#include "ccu_ddn.h" -+ -+#include -+ -+/* APBS clocks start, APBS region contains and only contains all PLL clocks */ -+ -+/* -+ * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for -+ * peripherals. -+ */ -+static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = { -+ CCU_PLLA_RATE(2457600000UL, 0x0b330ccc, 0x0000cd00, 0xa0558989), -+}; -+ -+static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { -+ CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c), -+}; -+ -+static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = { -+ CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), -+}; -+ -+static const struct ccu_pll_rate_tbl pll4_rate_tbl[] = { -+ CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), -+}; -+ -+static const struct ccu_pll_rate_tbl pll5_rate_tbl[] = { -+ CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), -+}; -+ -+static const struct ccu_pll_rate_tbl pll6_rate_tbl[] = { -+ CCU_PLLA_RATE(3200000000UL, 0x0b422aaa, 0x0000ab00, 0xa0558e8e), -+}; -+ -+static const struct ccu_pll_rate_tbl pll7_rate_tbl[] = { -+ CCU_PLLA_RATE(2800000000UL, 0x0b3a1555, 0x00005500, 0xa0558b8b), -+}; -+ -+static const struct ccu_pll_rate_tbl pll8_rate_tbl[] = { -+ CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), -+}; -+ -+CCU_PLLA_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR2, APBS_PLL1_SWCR3, -+ MPMU_POSR, POSR_PLL1_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2, APBS_PLL2_SWCR3, -+ MPMU_POSR, POSR_PLL2_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR2, APBS_PLL3_SWCR3, -+ MPMU_POSR, POSR_PLL3_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll4, pll4_rate_tbl, APBS_PLL4_SWCR1, APBS_PLL4_SWCR2, APBS_PLL4_SWCR3, -+ MPMU_POSR, POSR_PLL4_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll5, pll5_rate_tbl, APBS_PLL5_SWCR1, APBS_PLL5_SWCR2, APBS_PLL5_SWCR3, -+ MPMU_POSR, POSR_PLL5_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll6, pll6_rate_tbl, APBS_PLL6_SWCR1, APBS_PLL6_SWCR2, APBS_PLL6_SWCR3, -+ MPMU_POSR, POSR_PLL6_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll7, pll7_rate_tbl, APBS_PLL7_SWCR1, APBS_PLL7_SWCR2, APBS_PLL7_SWCR3, -+ MPMU_POSR, POSR_PLL7_LOCK, CLK_SET_RATE_GATE); -+CCU_PLLA_DEFINE(pll8, pll8_rate_tbl, APBS_PLL8_SWCR1, APBS_PLL8_SWCR2, APBS_PLL8_SWCR3, -+ MPMU_POSR, POSR_PLL8_LOCK, CLK_SET_RATE_GATE); -+ -+CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1, -+ CLK_IS_CRITICAL); -+CCU_DIV_GATE_DEFINE(pll1_dx, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, 23, 5, BIT(22), 0); -+CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(31), 64, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(21), 10, 1); -+CCU_FACTOR_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1_aud_245p7), 10, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1); -+CCU_FACTOR_DEFINE(pll2_66, CCU_PARENT_HW(pll2_d5), 9, 1); -+CCU_FACTOR_DEFINE(pll2_33, CCU_PARENT_HW(pll2_66), 2, 1); -+CCU_FACTOR_DEFINE(pll2_50, CCU_PARENT_HW(pll2_d5), 12, 1); -+CCU_FACTOR_DEFINE(pll2_25, CCU_PARENT_HW(pll2_50), 2, 1); -+CCU_FACTOR_DEFINE(pll2_20, CCU_PARENT_HW(pll2_d5), 30, 1); -+CCU_FACTOR_DEFINE(pll2_d24_125, CCU_PARENT_HW(pll2_d3), 8, 1); -+CCU_FACTOR_DEFINE(pll2_d120_25, CCU_PARENT_HW(pll2_d3), 40, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(7), 8, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll4_d1, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d2, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d3, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d4, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d5, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d6, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d7, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll4_d8, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(7), 8, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll5_d1, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d2, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d3, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d4, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d5, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d6, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d7, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll5_d8, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(7), 8, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll6_d1, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d2, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d3, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d4, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d5, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d6, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d7, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll6_d8, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(7), 8, 1); -+CCU_FACTOR_DEFINE(pll6_80, CCU_PARENT_HW(pll6_d5), 8, 1); -+CCU_FACTOR_DEFINE(pll6_40, CCU_PARENT_HW(pll6_d5), 16, 1); -+CCU_FACTOR_DEFINE(pll6_20, CCU_PARENT_HW(pll6_d5), 32, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll7_d1, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d2, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d3, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d4, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d5, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d6, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d7, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll7_d8, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(7), 8, 1); -+ -+CCU_FACTOR_GATE_DEFINE(pll8_d1, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(0), 1, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d2, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(1), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d3, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(2), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d4, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(3), 4, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d5, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(4), 5, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d6, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(5), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d7, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(6), 7, 1); -+CCU_FACTOR_GATE_DEFINE(pll8_d8, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(7), 8, 1); -+/* APBS clocks end */ -+ -+/* MPMU clocks start */ -+CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13), 0); -+CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1); -+CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1); -+CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(12), 3, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(7), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(11), 6, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(8), 16, 3); -+CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(4), 12, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(3), 24, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(19), 24, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(2), 48, 1); -+ -+CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1); -+CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1); -+CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1); -+ -+CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0); -+CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1); -+ -+CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0); -+CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1); -+ -+CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0); -+CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(10), 13, 1); -+CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6), 39, 2); -+ -+CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0); -+ -+CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0); -+ -+static const struct clk_parent_data apb_parents[] = { -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d24_102p4), -+}; -+CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0); -+ -+CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc_32k), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED); -+CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 2, 0); -+CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 2, 0); -+ -+CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0); -+CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), 0); -+ -+CCU_GATE_DEFINE(r_ipc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, BIT(0), 0); -+ -+CCU_FACTOR_DEFINE(i2s_153p6, CCU_PARENT_HW(pll1_d8_307p2), 2, 1); -+ -+static const struct clk_parent_data i2s_153p6_base_parents[] = { -+ CCU_PARENT_HW(i2s_153p6), -+ CCU_PARENT_HW(pll1_d8_307p2), -+}; -+CCU_MUX_DEFINE(i2s_153p6_base, i2s_153p6_base_parents, MPMU_FCCR, 29, 1, 0); -+ -+static const struct clk_parent_data i2s_sysclk_src_parents[] = { -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(i2s_153p6_base), -+}; -+CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0); -+ -+CCU_DDN_DEFINE(i2s1_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0); -+ -+CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s1_sysclk), MPMU_ISCCR, 27, 2, BIT(29), 0); -+ -+static const struct clk_parent_data i2s_sysclk_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_NAME(vctcxo_24m), -+ CCU_PARENT_HW(pll2_d5), -+ CCU_PARENT_NAME(vctcxo_24m), -+}; -+CCU_MUX_DEFINE(i2s0_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 0, 2, 0); -+CCU_MUX_DEFINE(i2s2_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 4, 2, 0); -+CCU_MUX_DEFINE(i2s3_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 12, 2, 0); -+CCU_MUX_DEFINE(i2s4_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 16, 2, 0); -+CCU_MUX_DEFINE(i2s5_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 20, 2, 0); -+ -+CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 1, 0); -+CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 1, 0); -+CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 1, 0); -+CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 1, 0); -+CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 1, 0); -+ -+static const struct clk_parent_data i2s2_sysclk_parents[] = { -+ CCU_PARENT_HW(i2s1_sysclk), -+ CCU_PARENT_HW(i2s2_sysclk_div), -+}; -+CCU_GATE_DEFINE(i2s0_sysclk, CCU_PARENT_HW(i2s0_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(2), 0); -+CCU_MUX_GATE_DEFINE(i2s2_sysclk, i2s2_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 8, 1, BIT(6), 0); -+CCU_GATE_DEFINE(i2s3_sysclk, CCU_PARENT_HW(i2s3_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(14), 0); -+CCU_GATE_DEFINE(i2s4_sysclk, CCU_PARENT_HW(i2s4_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(18), 0); -+CCU_GATE_DEFINE(i2s5_sysclk, CCU_PARENT_HW(i2s5_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(22), 0); -+/* MPMU clocks end */ -+ -+/* APBC clocks start */ -+static const struct clk_parent_data uart_clk_parents[] = { -+ CCU_PARENT_HW(pll1_m3d128_57p6), -+ CCU_PARENT_HW(slow_uart1_14p74), -+ CCU_PARENT_HW(slow_uart2_48), -+}; -+CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART0_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(uart10_clk, uart_clk_parents, APBC_UART10_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(uart10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART10_CLK_RST, BIT(0), 0); -+ -+CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, BIT(0), 0); -+ -+static const struct clk_parent_data pwm_parents[] = { -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_NAME(osc_32k), -+}; -+CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST, BIT(0), 0); -+ -+static const struct clk_parent_data i2s_bclk_parents[] = { -+ CCU_PARENT_NAME(vctcxo_1m), -+ CCU_PARENT_HW(i2s_bclk), -+}; -+CCU_MUX_DEFINE(spi0_i2s_bclk, i2s_bclk_parents, APBC_SSP0_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(spi1_i2s_bclk, i2s_bclk_parents, APBC_SSP1_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(spi3_i2s_bclk, i2s_bclk_parents, APBC_SSP3_CLK_RST, 3, 1, 0); -+ -+static const struct clk_parent_data spi0_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(spi0_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(spi0_clk, spi0_parents, APBC_SSP0_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data spi1_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(spi1_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(spi1_clk, spi1_parents, APBC_SSP1_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data spi3_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(spi3_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(spi3_clk, spi3_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(spi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(spi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP1_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(spi3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, BIT(0), 0); -+ -+ -+CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc_32k), APBC_RTC_CLK_RST, -+ BIT(7) | BIT(1), 0); -+CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT(0), 0); -+ -+static const struct clk_parent_data twsi_parents[] = { -+ CCU_PARENT_HW(pll1_d78_31p5), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d40_61p44), -+}; -+CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(twsi8_clk, twsi_parents, APBC_TWSI8_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI8_CLK_RST, BIT(0), 0); -+ -+static const struct clk_parent_data timer_parents[] = { -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_NAME(osc_32k), -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_NAME(vctcxo_3m), -+ CCU_PARENT_NAME(vctcxo_1m), -+}; -+CCU_MUX_GATE_DEFINE(timers0_clk, timer_parents, APBC_TIMERS0_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers3_clk, timer_parents, APBC_TIMERS3_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers4_clk, timer_parents, APBC_TIMERS4_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers5_clk, timer_parents, APBC_TIMERS5_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers6_clk, timer_parents, APBC_TIMERS6_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(timers7_clk, timer_parents, APBC_TIMERS7_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(timers0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS3_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS4_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS5_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS6_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(timers7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS7_CLK_RST, BIT(0), 0); -+ -+CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT(0), 0); -+ -+CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_RST, BIT(0), 0); -+ -+/* -+ * When i2s_bclk is selected as the parent clock of sspa, -+ * the hardware requires bit3 to be set -+ */ -+ -+CCU_MUX_DEFINE(i2s0_i2s_bclk, i2s_bclk_parents, APBC_SSPA0_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(i2s1_i2s_bclk, i2s_bclk_parents, APBC_SSPA1_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(i2s2_i2s_bclk, i2s_bclk_parents, APBC_SSPA2_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(i2s3_i2s_bclk, i2s_bclk_parents, APBC_SSPA3_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(i2s4_i2s_bclk, i2s_bclk_parents, APBC_SSPA4_CLK_RST, 3, 1, 0); -+CCU_MUX_DEFINE(i2s5_i2s_bclk, i2s_bclk_parents, APBC_SSPA5_CLK_RST, 3, 1, 0); -+ -+static const struct clk_parent_data i2s0_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(i2s0_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(i2s0_clk, i2s0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data i2s1_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(i2s1_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(i2s1_clk, i2s1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data i2s2_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(i2s2_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(i2s2_clk, i2s2_parents, APBC_SSPA2_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data i2s3_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(i2s3_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(i2s3_clk, i2s3_parents, APBC_SSPA3_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data i2s4_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(i2s4_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(i2s4_clk, i2s4_parents, APBC_SSPA4_CLK_RST, 4, 3, BIT(1), 0); -+ -+static const struct clk_parent_data i2s5_parents[] = { -+ CCU_PARENT_HW(pll1_d384_6p4), -+ CCU_PARENT_HW(pll1_d192_12p8), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d48_51p2), -+ CCU_PARENT_HW(pll1_d768_3p2), -+ CCU_PARENT_HW(pll1_d1536_1p6), -+ CCU_PARENT_HW(pll1_d3072_0p8), -+ CCU_PARENT_HW(i2s5_i2s_bclk), -+}; -+CCU_MUX_GATE_DEFINE(i2s5_clk, i2s5_parents, APBC_SSPA5_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(i2s0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(i2s1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(i2s2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA2_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(i2s3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA3_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(i2s4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA4_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(i2s5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA5_CLK_RST, BIT(0), 0); -+ -+CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(ir0_clk, CCU_PARENT_HW(apb_clk), APBC_IR0_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(ir1_clk, CCU_PARENT_HW(apb_clk), APBC_IR1_CLK_RST, BIT(1), 0); -+ -+CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(0), 0); -+ -+CCU_GATE_DEFINE(ipc_ap2rcpu_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0); -+CCU_GATE_DEFINE(ipc_ap2rcpu_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0); -+ -+static const struct clk_parent_data can_parents[] = { -+ CCU_PARENT_HW(pll6_20), -+ CCU_PARENT_HW(pll6_40), -+ CCU_PARENT_HW(pll6_80), -+}; -+CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(can1_clk, can_parents, APBC_CAN1_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(can2_clk, can_parents, APBC_CAN2_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(can3_clk, can_parents, APBC_CAN3_CLK_RST, 4, 3, BIT(1), 0); -+CCU_MUX_GATE_DEFINE(can4_clk, can_parents, APBC_CAN4_CLK_RST, 4, 3, BIT(1), 0); -+ -+CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN0_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(can1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN1_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(can2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN2_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(can3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN3_CLK_RST, BIT(0), 0); -+CCU_GATE_DEFINE(can4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN4_CLK_RST, BIT(0), 0); -+/* APBC clocks end */ -+ -+/* APMU clocks start */ -+static const struct clk_parent_data axi_clk_parents[] = { -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d6_409p6), -+}; -+CCU_MUX_DIV_FC_DEFINE(axi_clk, axi_clk_parents, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), 0, 1, 0); -+ -+static const struct clk_parent_data cci550_clk_parents[] = { -+ CCU_PARENT_HW(pll1_d10_245p76), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll7_d3), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll7_d2), -+}; -+CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL, 8, 2, BIT(12), 0, 3, -+ CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data cpu_c0_clk_parents[] = { -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll3_d2), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll2_d2), -+ CCU_PARENT_HW(pll3_d1), -+}; -+CCU_MUX_DIV_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL, -+ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data cpu_c1_clk_parents[] = { -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll4_d2), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll2_d2), -+ CCU_PARENT_HW(pll4_d1), -+}; -+CCU_MUX_DIV_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL, -+ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data cpu_c2_clk_parents[] = { -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll5_d2), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll2_d2), -+ CCU_PARENT_HW(pll5_d1), -+}; -+CCU_MUX_DIV_FC_DEFINE(cpu_c2_core_clk, cpu_c2_clk_parents, APMU_CPU_C2_CLK_CTRL, -+ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data cpu_c3_clk_parents[] = { -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll8_d2), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll2_d2), -+ CCU_PARENT_HW(pll8_d1), -+}; -+CCU_MUX_DIV_FC_DEFINE(cpu_c3_core_clk, cpu_c3_clk_parents, APMU_CPU_C3_CLK_CTRL, -+ 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data ccic2phy_parents[] = { -+ CCU_PARENT_HW(pll1_d24_102p4), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+}; -+CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0); -+ -+static const struct clk_parent_data ccic3phy_parents[] = { -+ CCU_PARENT_HW(pll1_d24_102p4), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+}; -+CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0); -+ -+static const struct clk_parent_data csi_parents[] = { -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll2_d2), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15), -+ 16, 3, BIT(4), 0); -+ -+static const struct clk_parent_data isp_bus_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d10_245p76), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23), -+ 21, 2, BIT(17), 0); -+ -+CCU_GATE_DEFINE(d1p_1228p8, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMU_CLK_GATE_CTRL, BIT(31), 0); -+CCU_GATE_DEFINE(d1p_819p2, CCU_PARENT_HW(pll1_d3_819p2), APMU_PMU_CLK_GATE_CTRL, BIT(30), 0); -+CCU_GATE_DEFINE(d1p_614p4, CCU_PARENT_HW(pll1_d4_614p4), APMU_PMU_CLK_GATE_CTRL, BIT(29), 0); -+CCU_GATE_DEFINE(d1p_491p52, CCU_PARENT_HW(pll1_d5_491p52), APMU_PMU_CLK_GATE_CTRL, BIT(28), 0); -+CCU_GATE_DEFINE(d1p_409p6, CCU_PARENT_HW(pll1_d6_409p6), APMU_PMU_CLK_GATE_CTRL, BIT(27), 0); -+CCU_GATE_DEFINE(d1p_307p2, CCU_PARENT_HW(pll1_d8_307p2), APMU_PMU_CLK_GATE_CTRL, BIT(26), 0); -+CCU_GATE_DEFINE(d1p_245p76, CCU_PARENT_HW(pll1_d10_245p76), APMU_PMU_CLK_GATE_CTRL, BIT(22), 0); -+ -+static const struct clk_parent_data v2d_parents[] = { -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d4_614p4), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28), 12, 2, -+ BIT(8), 0); -+ -+static const struct clk_parent_data dsiesc_parents[] = { -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+ CCU_PARENT_HW(pll1_d52_47p26), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d32_76p8), -+}; -+CCU_MUX_GATE_DEFINE(dsi_esc_clk, dsiesc_parents, APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0); -+ -+CCU_GATE_DEFINE(lcd_hclk, CCU_PARENT_HW(axi_clk), APMU_LCD_CLK_RES_CTRL1, BIT(5), 0); -+ -+static const struct clk_parent_data lcd_dsc_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d10_245p76), -+ CCU_PARENT_HW(pll7_d5), -+ CCU_PARENT_HW(pll2_d7), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+ CCU_PARENT_HW(pll2_d8), -+}; -+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_dsc_clk, lcd_dsc_parents, APMU_LCD_CLK_RES_CTRL2, -+ APMU_LCD_CLK_RES_CTRL1, 25, 3, BIT(26), 29, 3, BIT(14), 0); -+ -+static const struct clk_parent_data lcdpx_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d10_245p76), -+ CCU_PARENT_HW(pll7_d5), -+ CCU_PARENT_HW(pll2_d7), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+ CCU_PARENT_HW(pll2_d8), -+}; -+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_pxclk, lcdpx_parents, APMU_LCD_CLK_RES_CTRL2, -+ APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(30), 21, 3, BIT(16), 0); -+ -+static const struct clk_parent_data lcdmclk_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d8_307p2), -+}; -+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_mclk, lcdmclk_parents, APMU_LCD_CLK_RES_CTRL2, -+ APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0); -+ -+static const struct clk_parent_data ccic_4x_parents[] = { -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll2_d2), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES_CTRL, 18, 3, -+ BIT(15), 23, 2, BIT(4), 0); -+ -+static const struct clk_parent_data ccic1phy_parents[] = { -+ CCU_PARENT_HW(pll1_d24_102p4), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+}; -+CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0); -+ -+ -+static const struct clk_parent_data sc2hclk_parents[] = { -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll2_d4), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(sc2_hclk, sc2hclk_parents, APMU_CCIC_CLK_RES_CTRL, 10, 3, -+ BIT(16), 8, 2, BIT(3), 0); -+ -+CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(axi_clk), APMU_SDH0_CLK_RES_CTRL, BIT(3), 0); -+static const struct clk_parent_data sdh01_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll2_d8), -+ CCU_PARENT_HW(pll2_d5), -+ CCU_PARENT_NAME(reserved_clk), -+ CCU_PARENT_NAME(reserved_clk), -+ CCU_PARENT_HW(pll1_dx), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL, 8, 3, -+ BIT(11), 5, 3, BIT(4), 0); -+CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL, 8, 3, -+ BIT(11), 5, 3, BIT(4), 0); -+static const struct clk_parent_data sdh2_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll2_d8), -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_NAME(reserved_clk), -+ CCU_PARENT_NAME(reserved_clk), -+ CCU_PARENT_HW(pll1_dx), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, -+ BIT(11), 5, 3, BIT(4), 0); -+ -+CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(0), 0); -+CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(4), 0); -+CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); -+CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(12), 0); -+CCU_GATE_DEFINE(usb3_portd_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(16), 0); -+ -+static const struct clk_parent_data qspi_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll2_d8), -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d10_245p76), -+ CCU_PARENT_NAME(reserved_clk), -+ CCU_PARENT_HW(pll1_dx), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_NAME(reserved_clk), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL, 9, 3, -+ BIT(12), 6, 3, BIT(4), 0); -+CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(axi_clk), APMU_QSPI_CLK_RES_CTRL, BIT(3), 0); -+ -+CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(axi_clk), APMU_DMA_CLK_RES_CTRL, BIT(3), 0); -+ -+static const struct clk_parent_data aes_wtm_parents[] = { -+ CCU_PARENT_HW(pll1_d12_204p8), -+ CCU_PARENT_HW(pll1_d24_102p4), -+}; -+CCU_MUX_GATE_DEFINE(aes_wtm_clk, aes_wtm_parents, APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0); -+ -+static const struct clk_parent_data vpu_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll2_d5), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13, 3, -+ BIT(21), 10, 3, BIT(3), 0); -+ -+CCU_GATE_DEFINE(dtc_clk, CCU_PARENT_HW(axi_clk), APMU_DTC_CLK_RES_CTRL, BIT(3), 0); -+ -+static const struct clk_parent_data gpu_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d3_819p2), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d2_1228p8), -+ CCU_PARENT_HW(pll2_d3), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll2_d5), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12, 3, -+ BIT(15), 18, 3, BIT(4), 0); -+ -+CCU_GATE_DEFINE(mc_ahb_clk, CCU_PARENT_HW(axi_clk), APMU_PMUA_MC_CTRL, BIT(1), 0); -+ -+static const struct clk_parent_data top_parents[] = { -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll3_d4), -+ CCU_PARENT_HW(pll6_d5), -+ CCU_PARENT_HW(pll7_d4), -+ CCU_PARENT_HW(pll6_d4), -+ CCU_PARENT_HW(pll7_d3), -+ CCU_PARENT_HW(pll6_d3), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(top_dclk, top_parents, APMU_TOP_DCLK_CTRL, 5, 3, -+ BIT(8), 2, 3, BIT(1), 0); -+ -+static const struct clk_parent_data ucie_parents[] = { -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll3_d4), -+ CCU_PARENT_HW(pll6_d5), -+ CCU_PARENT_HW(pll7_d4), -+ CCU_PARENT_HW(pll6_d4), -+}; -+CCU_MUX_GATE_DEFINE(ucie_clk, ucie_parents, APMU_UCIE_CTRL, 4, 3, BIT(0), 0); -+CCU_GATE_DEFINE(ucie_sbclk, CCU_PARENT_HW(axi_clk), APMU_UCIE_CTRL, BIT(8), 0); -+ -+static const struct clk_parent_data rcpu_clk_parents[] = { -+ CCU_PARENT_HW(pll1_aud_245p7), -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d6_409p6), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, -+ 4, 3, BIT(15), 7, 3, BIT(12), 0); -+ -+static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+ CCU_PARENT_HW(pll1_d52_47p26), -+ CCU_PARENT_HW(pll1_d96_25p6), -+ CCU_PARENT_HW(pll1_d32_76p8), -+}; -+CCU_MUX_GATE_DEFINE(dsi4ln2_dsi_esc_clk, dsi4ln2_dsi_esc_parents, APMU_LCD_CLK_RES_CTRL3, -+ 0, 1, BIT(2), 0); -+ -+static const struct clk_parent_data dsi4ln2_lcd_dsc_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll7_d5), -+ CCU_PARENT_HW(pll6_d6), -+ CCU_PARENT_HW(pll2_d7), -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+}; -+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_dsc_clk, dsi4ln2_lcd_dsc_parents, -+ APMU_LCD_CLK_RES_CTRL4, APMU_LCD_CLK_RES_CTRL3, -+ 25, 3, BIT(26), 29, 3, BIT(14), 0); -+ -+static const struct clk_parent_data dsi4ln2_lcdpx_parents[] = { -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll7_d5), -+ CCU_PARENT_HW(pll6_d6), -+ CCU_PARENT_HW(pll2_d7), -+ CCU_PARENT_HW(pll2_d4), -+ CCU_PARENT_HW(pll1_d48_51p2_ap), -+ CCU_PARENT_HW(pll2_d8), -+}; -+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_pxclk, dsi4ln2_lcdpx_parents, APMU_LCD_CLK_RES_CTRL4, -+ APMU_LCD_CLK_RES_CTRL3, 17, 3, BIT(30), 21, 3, BIT(16), 0); -+ -+static const struct clk_parent_data dsi4ln2_lcd_mclk_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d8_307p2), -+}; -+CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_mclk, dsi4ln2_lcd_mclk_parents, APMU_LCD_CLK_RES_CTRL4, -+ APMU_LCD_CLK_RES_CTRL3, 1, 4, BIT(29), 5, 3, BIT(0), 0); -+ -+static const struct clk_parent_data dpu_aclk_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll2_d4), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(dsi4ln2_dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, -+ 2, 3, BIT(30), 5, 3, BIT(1), 0); -+ -+CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, 17, 3, BIT(31), -+ 20, 3, BIT(16), 0); -+ -+static const struct clk_parent_data ufs_aclk_parents[] = { -+ CCU_PARENT_HW(pll1_d6_409p6), -+ CCU_PARENT_HW(pll1_d5_491p52), -+ CCU_PARENT_HW(pll1_d4_614p4), -+ CCU_PARENT_HW(pll1_d8_307p2), -+ CCU_PARENT_HW(pll2_d4), -+}; -+CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8), -+ 2, 3, BIT(1), 0); -+ -+static const struct clk_parent_data edp0_pclk_parents[] = { -+ CCU_PARENT_HW(lcd_pxclk), -+ CCU_PARENT_NAME(external_clk), -+}; -+CCU_MUX_GATE_DEFINE(edp0_pxclk, edp0_pclk_parents, APMU_LCD_EDP_CTRL, 2, 1, BIT(1), 0); -+ -+static const struct clk_parent_data edp1_pclk_parents[] = { -+ CCU_PARENT_HW(dsi4ln2_lcd_pxclk), -+ CCU_PARENT_NAME(external_clk), -+}; -+CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); -+ -+CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); -+CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); -+CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); -+CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); -+CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); -+CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); -+CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); -+CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); -+CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); -+CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); -+ -+static const struct clk_parent_data emac_1588_parents[] = { -+ CCU_PARENT_NAME(vctcxo_24m), -+ CCU_PARENT_HW(pll2_d24_125), -+}; -+ -+CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0); -+CCU_GATE_FLAGS_DEFINE(emac0_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC0_CLK_RES_CTRL, -+ BIT(14), true, 0); -+CCU_MUX_DEFINE(emac0_1588_clk, emac_1588_parents, APMU_EMAC0_CLK_RES_CTRL, 15, 1, 0); -+CCU_GATE_DEFINE(emac0_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC0_CLK_RES_CTRL, -+ BIT(8), 0); -+CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0); -+CCU_GATE_FLAGS_DEFINE(emac1_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC1_CLK_RES_CTRL, -+ BIT(14), true, 0); -+CCU_MUX_DEFINE(emac1_1588_clk, emac_1588_parents, APMU_EMAC1_CLK_RES_CTRL, 15, 1, 0); -+CCU_GATE_DEFINE(emac1_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC1_CLK_RES_CTRL, -+ BIT(8), 0); -+CCU_GATE_DEFINE(emac2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC2_CLK_RES_CTRL, BIT(0), 0); -+CCU_GATE_FLAGS_DEFINE(emac2_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC2_CLK_RES_CTRL, -+ BIT(14), true, 0); -+CCU_MUX_DEFINE(emac2_1588_clk, emac_1588_parents, APMU_EMAC2_CLK_RES_CTRL, 15, 1, 0); -+CCU_GATE_DEFINE(emac2_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC2_CLK_RES_CTRL, -+ BIT(8), 0); -+ -+static const struct clk_parent_data espi_sclk_src_parents[] = { -+ CCU_PARENT_HW(pll2_20), -+ CCU_PARENT_HW(pll2_25), -+ CCU_PARENT_HW(pll2_33), -+ CCU_PARENT_HW(pll2_50), -+ CCU_PARENT_HW(pll2_66), -+}; -+CCU_MUX_DEFINE(espi_sclk_src, espi_sclk_src_parents, APMU_ESPI_CLK_RES_CTRL, 4, 3, 0); -+ -+static const struct clk_parent_data espi_sclk_parents[] = { -+ CCU_PARENT_NAME(external_clk), -+ CCU_PARENT_HW(espi_sclk_src), -+}; -+CCU_MUX_GATE_DEFINE(espi_sclk, espi_sclk_parents, APMU_ESPI_CLK_RES_CTRL, 7, 1, BIT(3), 0); -+ -+CCU_GATE_DEFINE(espi_mclk, CCU_PARENT_HW(axi_clk), APMU_ESPI_CLK_RES_CTRL, BIT(1), 0); -+ -+CCU_FACTOR_DEFINE(cam_src1_clk, CCU_PARENT_HW(pll1_d6_409p6), 15, 1); -+CCU_FACTOR_DEFINE(cam_src2_clk, CCU_PARENT_HW(pll2_d5), 25, 1); -+CCU_FACTOR_DEFINE(cam_src3_clk, CCU_PARENT_HW(pll2_d6), 20, 1); -+CCU_FACTOR_DEFINE(cam_src4_clk, CCU_PARENT_HW(pll1_d6_409p6), 16, 1); -+ -+static const struct clk_parent_data isim_vclk_parents[] = { -+ CCU_PARENT_HW(cam_src1_clk), -+ CCU_PARENT_HW(cam_src2_clk), -+ CCU_PARENT_HW(cam_src3_clk), -+ CCU_PARENT_HW(cam_src4_clk), -+}; -+CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out0, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 3, 4, -+ 1, 2, BIT(0), 0); -+CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out1, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 11, 4, -+ 9, 2, BIT(8), 0); -+CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out2, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 19, 4, -+ 17, 2, BIT(16), 0); -+CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 27, 4, -+ 25, 2, BIT(24), 0); -+/* APMU clocks end */ -+ -+/* DCIU clocks start */ -+CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); -+CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); -+CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); -+CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); -+/* DCIU clocks end */ -+ -+static struct clk_hw *k3_ccu_pll_hws[] = { -+ [CLK_PLL1] = &pll1.common.hw, -+ [CLK_PLL2] = &pll2.common.hw, -+ [CLK_PLL3] = &pll3.common.hw, -+ [CLK_PLL4] = &pll4.common.hw, -+ [CLK_PLL5] = &pll5.common.hw, -+ [CLK_PLL6] = &pll6.common.hw, -+ [CLK_PLL7] = &pll7.common.hw, -+ [CLK_PLL8] = &pll8.common.hw, -+ [CLK_PLL1_D2] = &pll1_d2.common.hw, -+ [CLK_PLL1_D3] = &pll1_d3.common.hw, -+ [CLK_PLL1_D4] = &pll1_d4.common.hw, -+ [CLK_PLL1_D5] = &pll1_d5.common.hw, -+ [CLK_PLL1_D6] = &pll1_d6.common.hw, -+ [CLK_PLL1_D7] = &pll1_d7.common.hw, -+ [CLK_PLL1_D8] = &pll1_d8.common.hw, -+ [CLK_PLL1_DX] = &pll1_dx.common.hw, -+ [CLK_PLL1_D64] = &pll1_d64_38p4.common.hw, -+ [CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw, -+ [CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw, -+ [CLK_PLL2_D1] = &pll2_d1.common.hw, -+ [CLK_PLL2_D2] = &pll2_d2.common.hw, -+ [CLK_PLL2_D3] = &pll2_d3.common.hw, -+ [CLK_PLL2_D4] = &pll2_d4.common.hw, -+ [CLK_PLL2_D5] = &pll2_d5.common.hw, -+ [CLK_PLL2_D6] = &pll2_d6.common.hw, -+ [CLK_PLL2_D7] = &pll2_d7.common.hw, -+ [CLK_PLL2_D8] = &pll2_d8.common.hw, -+ [CLK_PLL2_66] = &pll2_66.common.hw, -+ [CLK_PLL2_33] = &pll2_33.common.hw, -+ [CLK_PLL2_50] = &pll2_50.common.hw, -+ [CLK_PLL2_25] = &pll2_25.common.hw, -+ [CLK_PLL2_20] = &pll2_20.common.hw, -+ [CLK_PLL2_D24_125] = &pll2_d24_125.common.hw, -+ [CLK_PLL2_D120_25] = &pll2_d120_25.common.hw, -+ [CLK_PLL3_D1] = &pll3_d1.common.hw, -+ [CLK_PLL3_D2] = &pll3_d2.common.hw, -+ [CLK_PLL3_D3] = &pll3_d3.common.hw, -+ [CLK_PLL3_D4] = &pll3_d4.common.hw, -+ [CLK_PLL3_D5] = &pll3_d5.common.hw, -+ [CLK_PLL3_D6] = &pll3_d6.common.hw, -+ [CLK_PLL3_D7] = &pll3_d7.common.hw, -+ [CLK_PLL3_D8] = &pll3_d8.common.hw, -+ [CLK_PLL4_D1] = &pll4_d1.common.hw, -+ [CLK_PLL4_D2] = &pll4_d2.common.hw, -+ [CLK_PLL4_D3] = &pll4_d3.common.hw, -+ [CLK_PLL4_D4] = &pll4_d4.common.hw, -+ [CLK_PLL4_D5] = &pll4_d5.common.hw, -+ [CLK_PLL4_D6] = &pll4_d6.common.hw, -+ [CLK_PLL4_D7] = &pll4_d7.common.hw, -+ [CLK_PLL4_D8] = &pll4_d8.common.hw, -+ [CLK_PLL5_D1] = &pll5_d1.common.hw, -+ [CLK_PLL5_D2] = &pll5_d2.common.hw, -+ [CLK_PLL5_D3] = &pll5_d3.common.hw, -+ [CLK_PLL5_D4] = &pll5_d4.common.hw, -+ [CLK_PLL5_D5] = &pll5_d5.common.hw, -+ [CLK_PLL5_D6] = &pll5_d6.common.hw, -+ [CLK_PLL5_D7] = &pll5_d7.common.hw, -+ [CLK_PLL5_D8] = &pll5_d8.common.hw, -+ [CLK_PLL6_D1] = &pll6_d1.common.hw, -+ [CLK_PLL6_D2] = &pll6_d2.common.hw, -+ [CLK_PLL6_D3] = &pll6_d3.common.hw, -+ [CLK_PLL6_D4] = &pll6_d4.common.hw, -+ [CLK_PLL6_D5] = &pll6_d5.common.hw, -+ [CLK_PLL6_D6] = &pll6_d6.common.hw, -+ [CLK_PLL6_D7] = &pll6_d7.common.hw, -+ [CLK_PLL6_D8] = &pll6_d8.common.hw, -+ [CLK_PLL6_80] = &pll6_80.common.hw, -+ [CLK_PLL6_40] = &pll6_40.common.hw, -+ [CLK_PLL6_20] = &pll6_20.common.hw, -+ [CLK_PLL7_D1] = &pll7_d1.common.hw, -+ [CLK_PLL7_D2] = &pll7_d2.common.hw, -+ [CLK_PLL7_D3] = &pll7_d3.common.hw, -+ [CLK_PLL7_D4] = &pll7_d4.common.hw, -+ [CLK_PLL7_D5] = &pll7_d5.common.hw, -+ [CLK_PLL7_D6] = &pll7_d6.common.hw, -+ [CLK_PLL7_D7] = &pll7_d7.common.hw, -+ [CLK_PLL7_D8] = &pll7_d8.common.hw, -+ [CLK_PLL8_D1] = &pll8_d1.common.hw, -+ [CLK_PLL8_D2] = &pll8_d2.common.hw, -+ [CLK_PLL8_D3] = &pll8_d3.common.hw, -+ [CLK_PLL8_D4] = &pll8_d4.common.hw, -+ [CLK_PLL8_D5] = &pll8_d5.common.hw, -+ [CLK_PLL8_D6] = &pll8_d6.common.hw, -+ [CLK_PLL8_D7] = &pll8_d7.common.hw, -+ [CLK_PLL8_D8] = &pll8_d8.common.hw, -+}; -+ -+static const struct spacemit_ccu_data k3_ccu_pll_data = { -+ /* The APBS CCU implements PLLs, but no resets */ -+ .hws = k3_ccu_pll_hws, -+ .num = ARRAY_SIZE(k3_ccu_pll_hws), -+}; -+ -+static struct clk_hw *k3_ccu_mpmu_hws[] = { -+ [CLK_MPMU_PLL1_307P2] = &pll1_d8_307p2.common.hw, -+ [CLK_MPMU_PLL1_76P8] = &pll1_d32_76p8.common.hw, -+ [CLK_MPMU_PLL1_61P44] = &pll1_d40_61p44.common.hw, -+ [CLK_MPMU_PLL1_153P6] = &pll1_d16_153p6.common.hw, -+ [CLK_MPMU_PLL1_102P4] = &pll1_d24_102p4.common.hw, -+ [CLK_MPMU_PLL1_51P2] = &pll1_d48_51p2.common.hw, -+ [CLK_MPMU_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw, -+ [CLK_MPMU_PLL1_57P6] = &pll1_m3d128_57p6.common.hw, -+ [CLK_MPMU_PLL1_25P6] = &pll1_d96_25p6.common.hw, -+ [CLK_MPMU_PLL1_12P8] = &pll1_d192_12p8.common.hw, -+ [CLK_MPMU_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw, -+ [CLK_MPMU_PLL1_6P4] = &pll1_d384_6p4.common.hw, -+ [CLK_MPMU_PLL1_3P2] = &pll1_d768_3p2.common.hw, -+ [CLK_MPMU_PLL1_1P6] = &pll1_d1536_1p6.common.hw, -+ [CLK_MPMU_PLL1_0P8] = &pll1_d3072_0p8.common.hw, -+ [CLK_MPMU_PLL1_409P6] = &pll1_d6_409p6.common.hw, -+ [CLK_MPMU_PLL1_204P8] = &pll1_d12_204p8.common.hw, -+ [CLK_MPMU_PLL1_491] = &pll1_d5_491p52.common.hw, -+ [CLK_MPMU_PLL1_245P76] = &pll1_d10_245p76.common.hw, -+ [CLK_MPMU_PLL1_614] = &pll1_d4_614p4.common.hw, -+ [CLK_MPMU_PLL1_47P26] = &pll1_d52_47p26.common.hw, -+ [CLK_MPMU_PLL1_31P5] = &pll1_d78_31p5.common.hw, -+ [CLK_MPMU_PLL1_819] = &pll1_d3_819p2.common.hw, -+ [CLK_MPMU_PLL1_1228] = &pll1_d2_1228p8.common.hw, -+ [CLK_MPMU_APB] = &apb_clk.common.hw, -+ [CLK_MPMU_SLOW_UART] = &slow_uart.common.hw, -+ [CLK_MPMU_SLOW_UART1] = &slow_uart1_14p74.common.hw, -+ [CLK_MPMU_SLOW_UART2] = &slow_uart2_48.common.hw, -+ [CLK_MPMU_WDT] = &wdt_clk.common.hw, -+ [CLK_MPMU_WDT_BUS] = &wdt_bus_clk.common.hw, -+ [CLK_MPMU_RIPC] = &r_ipc_clk.common.hw, -+ [CLK_MPMU_I2S_153P6] = &i2s_153p6.common.hw, -+ [CLK_MPMU_I2S_153P6_BASE] = &i2s_153p6_base.common.hw, -+ [CLK_MPMU_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw, -+ [CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw, -+ [CLK_MPMU_I2S_BCLK] = &i2s_bclk.common.hw, -+ [CLK_MPMU_I2S0_SYSCLK_SEL] = &i2s0_sysclk_sel.common.hw, -+ [CLK_MPMU_I2S2_SYSCLK_SEL] = &i2s2_sysclk_sel.common.hw, -+ [CLK_MPMU_I2S3_SYSCLK_SEL] = &i2s3_sysclk_sel.common.hw, -+ [CLK_MPMU_I2S4_SYSCLK_SEL] = &i2s4_sysclk_sel.common.hw, -+ [CLK_MPMU_I2S5_SYSCLK_SEL] = &i2s5_sysclk_sel.common.hw, -+ [CLK_MPMU_I2S0_SYSCLK_DIV] = &i2s0_sysclk_div.common.hw, -+ [CLK_MPMU_I2S2_SYSCLK_DIV] = &i2s2_sysclk_div.common.hw, -+ [CLK_MPMU_I2S3_SYSCLK_DIV] = &i2s3_sysclk_div.common.hw, -+ [CLK_MPMU_I2S4_SYSCLK_DIV] = &i2s4_sysclk_div.common.hw, -+ [CLK_MPMU_I2S5_SYSCLK_DIV] = &i2s5_sysclk_div.common.hw, -+ [CLK_MPMU_I2S0_SYSCLK] = &i2s0_sysclk.common.hw, -+ [CLK_MPMU_I2S2_SYSCLK] = &i2s2_sysclk.common.hw, -+ [CLK_MPMU_I2S3_SYSCLK] = &i2s3_sysclk.common.hw, -+ [CLK_MPMU_I2S4_SYSCLK] = &i2s4_sysclk.common.hw, -+ [CLK_MPMU_I2S5_SYSCLK] = &i2s5_sysclk.common.hw, -+}; -+ -+static const struct spacemit_ccu_data k3_ccu_mpmu_data = { -+ .reset_name = "k3-mpmu-reset", -+ .hws = k3_ccu_mpmu_hws, -+ .num = ARRAY_SIZE(k3_ccu_mpmu_hws), -+}; -+ -+static struct clk_hw *k3_ccu_apbc_hws[] = { -+ [CLK_APBC_UART0] = &uart0_clk.common.hw, -+ [CLK_APBC_UART2] = &uart2_clk.common.hw, -+ [CLK_APBC_UART3] = &uart3_clk.common.hw, -+ [CLK_APBC_UART4] = &uart4_clk.common.hw, -+ [CLK_APBC_UART5] = &uart5_clk.common.hw, -+ [CLK_APBC_UART6] = &uart6_clk.common.hw, -+ [CLK_APBC_UART7] = &uart7_clk.common.hw, -+ [CLK_APBC_UART8] = &uart8_clk.common.hw, -+ [CLK_APBC_UART9] = &uart9_clk.common.hw, -+ [CLK_APBC_UART10] = &uart10_clk.common.hw, -+ [CLK_APBC_UART0_BUS] = &uart0_bus_clk.common.hw, -+ [CLK_APBC_UART2_BUS] = &uart2_bus_clk.common.hw, -+ [CLK_APBC_UART3_BUS] = &uart3_bus_clk.common.hw, -+ [CLK_APBC_UART4_BUS] = &uart4_bus_clk.common.hw, -+ [CLK_APBC_UART5_BUS] = &uart5_bus_clk.common.hw, -+ [CLK_APBC_UART6_BUS] = &uart6_bus_clk.common.hw, -+ [CLK_APBC_UART7_BUS] = &uart7_bus_clk.common.hw, -+ [CLK_APBC_UART8_BUS] = &uart8_bus_clk.common.hw, -+ [CLK_APBC_UART9_BUS] = &uart9_bus_clk.common.hw, -+ [CLK_APBC_UART10_BUS] = &uart10_bus_clk.common.hw, -+ [CLK_APBC_GPIO] = &gpio_clk.common.hw, -+ [CLK_APBC_GPIO_BUS] = &gpio_bus_clk.common.hw, -+ [CLK_APBC_PWM0] = &pwm0_clk.common.hw, -+ [CLK_APBC_PWM1] = &pwm1_clk.common.hw, -+ [CLK_APBC_PWM2] = &pwm2_clk.common.hw, -+ [CLK_APBC_PWM3] = &pwm3_clk.common.hw, -+ [CLK_APBC_PWM4] = &pwm4_clk.common.hw, -+ [CLK_APBC_PWM5] = &pwm5_clk.common.hw, -+ [CLK_APBC_PWM6] = &pwm6_clk.common.hw, -+ [CLK_APBC_PWM7] = &pwm7_clk.common.hw, -+ [CLK_APBC_PWM8] = &pwm8_clk.common.hw, -+ [CLK_APBC_PWM9] = &pwm9_clk.common.hw, -+ [CLK_APBC_PWM10] = &pwm10_clk.common.hw, -+ [CLK_APBC_PWM11] = &pwm11_clk.common.hw, -+ [CLK_APBC_PWM12] = &pwm12_clk.common.hw, -+ [CLK_APBC_PWM13] = &pwm13_clk.common.hw, -+ [CLK_APBC_PWM14] = &pwm14_clk.common.hw, -+ [CLK_APBC_PWM15] = &pwm15_clk.common.hw, -+ [CLK_APBC_PWM16] = &pwm16_clk.common.hw, -+ [CLK_APBC_PWM17] = &pwm17_clk.common.hw, -+ [CLK_APBC_PWM18] = &pwm18_clk.common.hw, -+ [CLK_APBC_PWM19] = &pwm19_clk.common.hw, -+ [CLK_APBC_PWM0_BUS] = &pwm0_bus_clk.common.hw, -+ [CLK_APBC_PWM1_BUS] = &pwm1_bus_clk.common.hw, -+ [CLK_APBC_PWM2_BUS] = &pwm2_bus_clk.common.hw, -+ [CLK_APBC_PWM3_BUS] = &pwm3_bus_clk.common.hw, -+ [CLK_APBC_PWM4_BUS] = &pwm4_bus_clk.common.hw, -+ [CLK_APBC_PWM5_BUS] = &pwm5_bus_clk.common.hw, -+ [CLK_APBC_PWM6_BUS] = &pwm6_bus_clk.common.hw, -+ [CLK_APBC_PWM7_BUS] = &pwm7_bus_clk.common.hw, -+ [CLK_APBC_PWM8_BUS] = &pwm8_bus_clk.common.hw, -+ [CLK_APBC_PWM9_BUS] = &pwm9_bus_clk.common.hw, -+ [CLK_APBC_PWM10_BUS] = &pwm10_bus_clk.common.hw, -+ [CLK_APBC_PWM11_BUS] = &pwm11_bus_clk.common.hw, -+ [CLK_APBC_PWM12_BUS] = &pwm12_bus_clk.common.hw, -+ [CLK_APBC_PWM13_BUS] = &pwm13_bus_clk.common.hw, -+ [CLK_APBC_PWM14_BUS] = &pwm14_bus_clk.common.hw, -+ [CLK_APBC_PWM15_BUS] = &pwm15_bus_clk.common.hw, -+ [CLK_APBC_PWM16_BUS] = &pwm16_bus_clk.common.hw, -+ [CLK_APBC_PWM17_BUS] = &pwm17_bus_clk.common.hw, -+ [CLK_APBC_PWM18_BUS] = &pwm18_bus_clk.common.hw, -+ [CLK_APBC_PWM19_BUS] = &pwm19_bus_clk.common.hw, -+ [CLK_APBC_SPI0_I2S_BCLK] = &spi0_i2s_bclk.common.hw, -+ [CLK_APBC_SPI1_I2S_BCLK] = &spi1_i2s_bclk.common.hw, -+ [CLK_APBC_SPI3_I2S_BCLK] = &spi3_i2s_bclk.common.hw, -+ [CLK_APBC_SPI0] = &spi0_clk.common.hw, -+ [CLK_APBC_SPI1] = &spi1_clk.common.hw, -+ [CLK_APBC_SPI3] = &spi3_clk.common.hw, -+ [CLK_APBC_SPI0_BUS] = &spi0_bus_clk.common.hw, -+ [CLK_APBC_SPI1_BUS] = &spi1_bus_clk.common.hw, -+ [CLK_APBC_SPI3_BUS] = &spi3_bus_clk.common.hw, -+ [CLK_APBC_RTC] = &rtc_clk.common.hw, -+ [CLK_APBC_RTC_BUS] = &rtc_bus_clk.common.hw, -+ [CLK_APBC_TWSI0] = &twsi0_clk.common.hw, -+ [CLK_APBC_TWSI1] = &twsi1_clk.common.hw, -+ [CLK_APBC_TWSI2] = &twsi2_clk.common.hw, -+ [CLK_APBC_TWSI4] = &twsi4_clk.common.hw, -+ [CLK_APBC_TWSI5] = &twsi5_clk.common.hw, -+ [CLK_APBC_TWSI6] = &twsi6_clk.common.hw, -+ [CLK_APBC_TWSI8] = &twsi8_clk.common.hw, -+ [CLK_APBC_TWSI0_BUS] = &twsi0_bus_clk.common.hw, -+ [CLK_APBC_TWSI1_BUS] = &twsi1_bus_clk.common.hw, -+ [CLK_APBC_TWSI2_BUS] = &twsi2_bus_clk.common.hw, -+ [CLK_APBC_TWSI4_BUS] = &twsi4_bus_clk.common.hw, -+ [CLK_APBC_TWSI5_BUS] = &twsi5_bus_clk.common.hw, -+ [CLK_APBC_TWSI6_BUS] = &twsi6_bus_clk.common.hw, -+ [CLK_APBC_TWSI8_BUS] = &twsi8_bus_clk.common.hw, -+ [CLK_APBC_TIMERS0] = &timers0_clk.common.hw, -+ [CLK_APBC_TIMERS1] = &timers1_clk.common.hw, -+ [CLK_APBC_TIMERS2] = &timers2_clk.common.hw, -+ [CLK_APBC_TIMERS3] = &timers3_clk.common.hw, -+ [CLK_APBC_TIMERS4] = &timers4_clk.common.hw, -+ [CLK_APBC_TIMERS5] = &timers5_clk.common.hw, -+ [CLK_APBC_TIMERS6] = &timers6_clk.common.hw, -+ [CLK_APBC_TIMERS7] = &timers7_clk.common.hw, -+ [CLK_APBC_TIMERS0_BUS] = &timers0_bus_clk.common.hw, -+ [CLK_APBC_TIMERS1_BUS] = &timers1_bus_clk.common.hw, -+ [CLK_APBC_TIMERS2_BUS] = &timers2_bus_clk.common.hw, -+ [CLK_APBC_TIMERS3_BUS] = &timers3_bus_clk.common.hw, -+ [CLK_APBC_TIMERS4_BUS] = &timers4_bus_clk.common.hw, -+ [CLK_APBC_TIMERS5_BUS] = &timers5_bus_clk.common.hw, -+ [CLK_APBC_TIMERS6_BUS] = &timers6_bus_clk.common.hw, -+ [CLK_APBC_TIMERS7_BUS] = &timers7_bus_clk.common.hw, -+ [CLK_APBC_AIB] = &aib_clk.common.hw, -+ [CLK_APBC_AIB_BUS] = &aib_bus_clk.common.hw, -+ [CLK_APBC_ONEWIRE] = &onewire_clk.common.hw, -+ [CLK_APBC_ONEWIRE_BUS] = &onewire_bus_clk.common.hw, -+ [CLK_APBC_I2S0_BCLK] = &i2s0_i2s_bclk.common.hw, -+ [CLK_APBC_I2S1_BCLK] = &i2s1_i2s_bclk.common.hw, -+ [CLK_APBC_I2S2_BCLK] = &i2s2_i2s_bclk.common.hw, -+ [CLK_APBC_I2S3_BCLK] = &i2s3_i2s_bclk.common.hw, -+ [CLK_APBC_I2S4_BCLK] = &i2s4_i2s_bclk.common.hw, -+ [CLK_APBC_I2S5_BCLK] = &i2s5_i2s_bclk.common.hw, -+ [CLK_APBC_I2S0] = &i2s0_clk.common.hw, -+ [CLK_APBC_I2S1] = &i2s1_clk.common.hw, -+ [CLK_APBC_I2S2] = &i2s2_clk.common.hw, -+ [CLK_APBC_I2S3] = &i2s3_clk.common.hw, -+ [CLK_APBC_I2S4] = &i2s4_clk.common.hw, -+ [CLK_APBC_I2S5] = &i2s5_clk.common.hw, -+ [CLK_APBC_I2S0_BUS] = &i2s0_bus_clk.common.hw, -+ [CLK_APBC_I2S1_BUS] = &i2s1_bus_clk.common.hw, -+ [CLK_APBC_I2S2_BUS] = &i2s2_bus_clk.common.hw, -+ [CLK_APBC_I2S3_BUS] = &i2s3_bus_clk.common.hw, -+ [CLK_APBC_I2S4_BUS] = &i2s4_bus_clk.common.hw, -+ [CLK_APBC_I2S5_BUS] = &i2s5_bus_clk.common.hw, -+ [CLK_APBC_DRO] = &dro_clk.common.hw, -+ [CLK_APBC_IR0] = &ir0_clk.common.hw, -+ [CLK_APBC_IR1] = &ir1_clk.common.hw, -+ [CLK_APBC_TSEN] = &tsen_clk.common.hw, -+ [CLK_APBC_TSEN_BUS] = &tsen_bus_clk.common.hw, -+ [CLK_APBC_IPC_AP2RCPU] = &ipc_ap2rcpu_clk.common.hw, -+ [CLK_APBC_IPC_AP2RCPU_BUS] = &ipc_ap2rcpu_bus_clk.common.hw, -+ [CLK_APBC_CAN0] = &can0_clk.common.hw, -+ [CLK_APBC_CAN1] = &can1_clk.common.hw, -+ [CLK_APBC_CAN2] = &can2_clk.common.hw, -+ [CLK_APBC_CAN3] = &can3_clk.common.hw, -+ [CLK_APBC_CAN4] = &can4_clk.common.hw, -+ [CLK_APBC_CAN0_BUS] = &can0_bus_clk.common.hw, -+ [CLK_APBC_CAN1_BUS] = &can1_bus_clk.common.hw, -+ [CLK_APBC_CAN2_BUS] = &can2_bus_clk.common.hw, -+ [CLK_APBC_CAN3_BUS] = &can3_bus_clk.common.hw, -+ [CLK_APBC_CAN4_BUS] = &can4_bus_clk.common.hw, -+}; -+ -+static const struct spacemit_ccu_data k3_ccu_apbc_data = { -+ .reset_name = "k3-apbc-reset", -+ .hws = k3_ccu_apbc_hws, -+ .num = ARRAY_SIZE(k3_ccu_apbc_hws), -+}; -+ -+static struct clk_hw *k3_ccu_apmu_hws[] = { -+ [CLK_APMU_AXICLK] = &axi_clk.common.hw, -+ [CLK_APMU_CCI550] = &cci550_clk.common.hw, -+ [CLK_APMU_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw, -+ [CLK_APMU_CPU_C1_CORE] = &cpu_c1_core_clk.common.hw, -+ [CLK_APMU_CPU_C2_CORE] = &cpu_c2_core_clk.common.hw, -+ [CLK_APMU_CPU_C3_CORE] = &cpu_c3_core_clk.common.hw, -+ [CLK_APMU_CCIC2PHY] = &ccic2phy_clk.common.hw, -+ [CLK_APMU_CCIC3PHY] = &ccic3phy_clk.common.hw, -+ [CLK_APMU_CSI] = &csi_clk.common.hw, -+ [CLK_APMU_ISP_BUS] = &isp_bus_clk.common.hw, -+ [CLK_APMU_D1P_1228P8] = &d1p_1228p8.common.hw, -+ [CLK_APMU_D1P_819P2] = &d1p_819p2.common.hw, -+ [CLK_APMU_D1P_614P4] = &d1p_614p4.common.hw, -+ [CLK_APMU_D1P_491P52] = &d1p_491p52.common.hw, -+ [CLK_APMU_D1P_409P6] = &d1p_409p6.common.hw, -+ [CLK_APMU_D1P_307P2] = &d1p_307p2.common.hw, -+ [CLK_APMU_D1P_245P76] = &d1p_245p76.common.hw, -+ [CLK_APMU_V2D] = &v2d_clk.common.hw, -+ [CLK_APMU_DSI_ESC] = &dsi_esc_clk.common.hw, -+ [CLK_APMU_LCD_HCLK] = &lcd_hclk.common.hw, -+ [CLK_APMU_LCD_DSC] = &lcd_dsc_clk.common.hw, -+ [CLK_APMU_LCD_PXCLK] = &lcd_pxclk.common.hw, -+ [CLK_APMU_LCD_MCLK] = &lcd_mclk.common.hw, -+ [CLK_APMU_CCIC_4X] = &ccic_4x_clk.common.hw, -+ [CLK_APMU_CCIC1PHY] = &ccic1phy_clk.common.hw, -+ [CLK_APMU_SC2_HCLK] = &sc2_hclk.common.hw, -+ [CLK_APMU_SDH_AXI] = &sdh_axi_aclk.common.hw, -+ [CLK_APMU_SDH0] = &sdh0_clk.common.hw, -+ [CLK_APMU_SDH1] = &sdh1_clk.common.hw, -+ [CLK_APMU_SDH2] = &sdh2_clk.common.hw, -+ [CLK_APMU_USB2_BUS] = &usb2_bus_clk.common.hw, -+ [CLK_APMU_USB3_PORTA_BUS] = &usb3_porta_bus_clk.common.hw, -+ [CLK_APMU_USB3_PORTB_BUS] = &usb3_portb_bus_clk.common.hw, -+ [CLK_APMU_USB3_PORTC_BUS] = &usb3_portc_bus_clk.common.hw, -+ [CLK_APMU_USB3_PORTD_BUS] = &usb3_portd_bus_clk.common.hw, -+ [CLK_APMU_QSPI] = &qspi_clk.common.hw, -+ [CLK_APMU_QSPI_BUS] = &qspi_bus_clk.common.hw, -+ [CLK_APMU_DMA] = &dma_clk.common.hw, -+ [CLK_APMU_AES_WTM] = &aes_wtm_clk.common.hw, -+ [CLK_APMU_VPU] = &vpu_clk.common.hw, -+ [CLK_APMU_DTC] = &dtc_clk.common.hw, -+ [CLK_APMU_GPU] = &gpu_clk.common.hw, -+ [CLK_APMU_MC_AHB] = &mc_ahb_clk.common.hw, -+ [CLK_APMU_TOP_DCLK] = &top_dclk.common.hw, -+ [CLK_APMU_UCIE] = &ucie_clk.common.hw, -+ [CLK_APMU_UCIE_SBCLK] = &ucie_sbclk.common.hw, -+ [CLK_APMU_RCPU] = &rcpu_clk.common.hw, -+ [CLK_APMU_DSI4LN2_DSI_ESC] = &dsi4ln2_dsi_esc_clk.common.hw, -+ [CLK_APMU_DSI4LN2_LCD_DSC] = &dsi4ln2_lcd_dsc_clk.common.hw, -+ [CLK_APMU_DSI4LN2_LCD_PXCLK] = &dsi4ln2_lcd_pxclk.common.hw, -+ [CLK_APMU_DSI4LN2_LCD_MCLK] = &dsi4ln2_lcd_mclk.common.hw, -+ [CLK_APMU_DSI4LN2_DPU_ACLK] = &dsi4ln2_dpu_aclk.common.hw, -+ [CLK_APMU_DPU_ACLK] = &dpu_aclk.common.hw, -+ [CLK_APMU_UFS_ACLK] = &ufs_aclk.common.hw, -+ [CLK_APMU_EDP0_PXCLK] = &edp0_pxclk.common.hw, -+ [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, -+ [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, -+ [CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw, -+ [CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw, -+ [CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw, -+ [CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw, -+ [CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw, -+ [CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw, -+ [CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw, -+ [CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw, -+ [CLK_APMU_EMAC0_RGMII_TX] = &emac0_rgmii_tx_clk.common.hw, -+ [CLK_APMU_EMAC1_BUS] = &emac1_bus_clk.common.hw, -+ [CLK_APMU_EMAC1_REF] = &emac1_ref_clk.common.hw, -+ [CLK_APMU_EMAC1_1588] = &emac1_1588_clk.common.hw, -+ [CLK_APMU_EMAC1_RGMII_TX] = &emac1_rgmii_tx_clk.common.hw, -+ [CLK_APMU_EMAC2_BUS] = &emac2_bus_clk.common.hw, -+ [CLK_APMU_EMAC2_REF] = &emac2_ref_clk.common.hw, -+ [CLK_APMU_EMAC2_1588] = &emac2_1588_clk.common.hw, -+ [CLK_APMU_EMAC2_RGMII_TX] = &emac2_rgmii_tx_clk.common.hw, -+ [CLK_APMU_ESPI_SCLK_SRC] = &espi_sclk_src.common.hw, -+ [CLK_APMU_ESPI_SCLK] = &espi_sclk.common.hw, -+ [CLK_APMU_ESPI_MCLK] = &espi_mclk.common.hw, -+ [CLK_APMU_CAM_SRC1] = &cam_src1_clk.common.hw, -+ [CLK_APMU_CAM_SRC2] = &cam_src2_clk.common.hw, -+ [CLK_APMU_CAM_SRC3] = &cam_src3_clk.common.hw, -+ [CLK_APMU_CAM_SRC4] = &cam_src4_clk.common.hw, -+ [CLK_APMU_ISIM_VCLK0] = &isim_vclk_out0.common.hw, -+ [CLK_APMU_ISIM_VCLK1] = &isim_vclk_out1.common.hw, -+ [CLK_APMU_ISIM_VCLK2] = &isim_vclk_out2.common.hw, -+ [CLK_APMU_ISIM_VCLK3] = &isim_vclk_out3.common.hw, -+}; -+ -+static const struct spacemit_ccu_data k3_ccu_apmu_data = { -+ .reset_name = "k3-apmu-reset", -+ .hws = k3_ccu_apmu_hws, -+ .num = ARRAY_SIZE(k3_ccu_apmu_hws), -+}; -+ -+static struct clk_hw *k3_ccu_dciu_hws[] = { -+ [CLK_DCIU_HDMA] = &hdma_clk.common.hw, -+ [CLK_DCIU_DMA350] = &dma350_clk.common.hw, -+ [CLK_DCIU_C2_TCM_PIPE] = &c2_tcm_pipe_clk.common.hw, -+ [CLK_DCIU_C3_TCM_PIPE] = &c3_tcm_pipe_clk.common.hw, -+}; -+ -+static const struct spacemit_ccu_data k3_ccu_dciu_data = { -+ .reset_name = "k3-dciu-reset", -+ .hws = k3_ccu_dciu_hws, -+ .num = ARRAY_SIZE(k3_ccu_dciu_hws), -+}; -+ -+static const struct of_device_id of_k3_ccu_match[] = { -+ { -+ .compatible = "spacemit,k3-pll", -+ .data = &k3_ccu_pll_data, -+ }, -+ { -+ .compatible = "spacemit,k3-syscon-mpmu", -+ .data = &k3_ccu_mpmu_data, -+ }, -+ { -+ .compatible = "spacemit,k3-syscon-apbc", -+ .data = &k3_ccu_apbc_data, -+ }, -+ { -+ .compatible = "spacemit,k3-syscon-apmu", -+ .data = &k3_ccu_apmu_data, -+ }, -+ { -+ .compatible = "spacemit,k3-syscon-dciu", -+ .data = &k3_ccu_dciu_data, -+ }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_k3_ccu_match); -+ -+static int k3_ccu_probe(struct platform_device *pdev) -+{ -+ return spacemit_ccu_probe(pdev, "spacemit,k3-pll"); -+} -+ -+static struct platform_driver k3_ccu_driver = { -+ .driver = { -+ .name = "spacemit,k3-ccu", -+ .of_match_table = of_k3_ccu_match, -+ }, -+ .probe = k3_ccu_probe, -+}; -+module_platform_driver(k3_ccu_driver); -+ -+MODULE_IMPORT_NS("CLK_SPACEMIT"); -+MODULE_DESCRIPTION("SpacemiT K3 CCU driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch b/SPECS/linux-lts/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch new file mode 100644 index 0000000000..326c078c60 --- /dev/null +++ b/SPECS/linux-lts/0123-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch @@ -0,0 +1,363 @@ +From 1928fc1030c03e43f009ef60762dac1829c39b0c Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 20 Jan 2026 19:10:51 +0800 +Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: Extract common K1 reset code + +Extract the common reset controller code from the K1 driver into +separate reset-spacemit-common.{c,h} files to prepare for additional +SpacemiT SoCs that share the same reset controller architecture. + +The common code includes handlers for reset assert and deassert +operations and probing for auxiliary bus devices. + +Changes during extraction: +- Module ownership: Use dev->driver->owner instead of THIS_MODULE in + spacemit_reset_controller_register() to correctly reference the + calling driver's module. +- Rename spacemit_reset_ids to spacemit_k1_reset_ids. +- Define new namespace "RESET_SPACEMIT" for the exported common + functions (spacemit_reset_probe) and update K1 driver to import it. + +This prepares for additional SpacemiT SoCs (K3) that share the same reset +controller architecture. + +Reviewed-by: Alex Elder +Signed-off-by: Guodong Xu +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] +Signed-off-by: Philipp Zabel +(cherry picked from commit aba86f7bff0bfd6956aff9bbbfb0c6ea6d56809e) +Signed-off-by: Han Gao +--- + drivers/reset/spacemit/Kconfig | 17 ++- + drivers/reset/spacemit/Makefile | 2 + + .../reset/spacemit/reset-spacemit-common.c | 77 +++++++++++++ + .../reset/spacemit/reset-spacemit-common.h | 42 +++++++ + drivers/reset/spacemit/reset-spacemit-k1.c | 107 ++---------------- + 5 files changed, 144 insertions(+), 101 deletions(-) + create mode 100644 drivers/reset/spacemit/reset-spacemit-common.c + create mode 100644 drivers/reset/spacemit/reset-spacemit-common.h + +diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig +index 552884e8b72a..56a4858b30e1 100644 +--- a/drivers/reset/spacemit/Kconfig ++++ b/drivers/reset/spacemit/Kconfig +@@ -1,10 +1,20 @@ + # SPDX-License-Identifier: GPL-2.0-only + +-config RESET_SPACEMIT_K1 +- tristate "SpacemiT K1 reset driver" ++menu "Reset support for SpacemiT platforms" + depends on ARCH_SPACEMIT || COMPILE_TEST +- depends on SPACEMIT_K1_CCU ++ ++config RESET_SPACEMIT_COMMON ++ tristate + select AUXILIARY_BUS ++ help ++ Common reset controller infrastructure for SpacemiT SoCs. ++ This provides shared code and helper functions used by ++ reset drivers for various SpacemiT SoC families. ++ ++config RESET_SPACEMIT_K1 ++ tristate "Support for SpacemiT K1 SoC" ++ depends on SPACEMIT_K1_CCU ++ select RESET_SPACEMIT_COMMON + default SPACEMIT_K1_CCU + help + Support for reset controller in SpacemiT K1 SoC. +@@ -12,3 +22,4 @@ config RESET_SPACEMIT_K1 + unit (CCU) driver to provide reset control functionality + for various peripherals and subsystems in the SoC. + ++endmenu +diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile +index 34e3350136bb..0b056e8661ec 100644 +--- a/drivers/reset/spacemit/Makefile ++++ b/drivers/reset/spacemit/Makefile +@@ -1,2 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_RESET_SPACEMIT_COMMON) += reset-spacemit-common.o ++ + obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o +diff --git a/drivers/reset/spacemit/reset-spacemit-common.c b/drivers/reset/spacemit/reset-spacemit-common.c +new file mode 100644 +index 000000000000..0626633a5e7d +--- /dev/null ++++ b/drivers/reset/spacemit/reset-spacemit-common.c +@@ -0,0 +1,77 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++/* SpacemiT reset controller driver - common implementation */ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include "reset-spacemit-common.h" ++ ++static int spacemit_reset_update(struct reset_controller_dev *rcdev, ++ unsigned long id, bool assert) ++{ ++ struct ccu_reset_controller *controller; ++ const struct ccu_reset_data *data; ++ u32 mask; ++ u32 val; ++ ++ controller = container_of(rcdev, struct ccu_reset_controller, rcdev); ++ data = &controller->data->reset_data[id]; ++ mask = data->assert_mask | data->deassert_mask; ++ val = assert ? data->assert_mask : data->deassert_mask; ++ ++ return regmap_update_bits(controller->regmap, data->offset, mask, val); ++} ++ ++static int spacemit_reset_assert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ return spacemit_reset_update(rcdev, id, true); ++} ++ ++static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ return spacemit_reset_update(rcdev, id, false); ++} ++ ++static const struct reset_control_ops spacemit_reset_control_ops = { ++ .assert = spacemit_reset_assert, ++ .deassert = spacemit_reset_deassert, ++}; ++ ++static int spacemit_reset_controller_register(struct device *dev, ++ struct ccu_reset_controller *controller) ++{ ++ struct reset_controller_dev *rcdev = &controller->rcdev; ++ ++ rcdev->ops = &spacemit_reset_control_ops; ++ rcdev->owner = dev->driver->owner; ++ rcdev->of_node = dev->of_node; ++ rcdev->nr_resets = controller->data->count; ++ ++ return devm_reset_controller_register(dev, &controller->rcdev); ++} ++ ++int spacemit_reset_probe(struct auxiliary_device *adev, ++ const struct auxiliary_device_id *id) ++{ ++ struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev); ++ struct ccu_reset_controller *controller; ++ struct device *dev = &adev->dev; ++ ++ controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); ++ if (!controller) ++ return -ENOMEM; ++ controller->data = (const struct ccu_reset_controller_data *)id->driver_data; ++ controller->regmap = rdev->regmap; ++ ++ return spacemit_reset_controller_register(dev, controller); ++} ++EXPORT_SYMBOL_NS_GPL(spacemit_reset_probe, "RESET_SPACEMIT"); ++ ++MODULE_DESCRIPTION("SpacemiT reset controller driver - common code"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/reset/spacemit/reset-spacemit-common.h b/drivers/reset/spacemit/reset-spacemit-common.h +new file mode 100644 +index 000000000000..ffaf2f86eb39 +--- /dev/null ++++ b/drivers/reset/spacemit/reset-spacemit-common.h +@@ -0,0 +1,42 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * SpacemiT reset controller driver - common definitions ++ */ ++ ++#ifndef _RESET_SPACEMIT_COMMON_H_ ++#define _RESET_SPACEMIT_COMMON_H_ ++ ++#include ++#include ++#include ++#include ++ ++struct ccu_reset_data { ++ u32 offset; ++ u32 assert_mask; ++ u32 deassert_mask; ++}; ++ ++struct ccu_reset_controller_data { ++ const struct ccu_reset_data *reset_data; /* array */ ++ size_t count; ++}; ++ ++struct ccu_reset_controller { ++ struct reset_controller_dev rcdev; ++ const struct ccu_reset_controller_data *data; ++ struct regmap *regmap; ++}; ++ ++#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ ++ { \ ++ .offset = (_offset), \ ++ .assert_mask = (_assert_mask), \ ++ .deassert_mask = (_deassert_mask), \ ++ } ++ ++/* Common probe function */ ++int spacemit_reset_probe(struct auxiliary_device *adev, ++ const struct auxiliary_device_id *id); ++ ++#endif /* _RESET_SPACEMIT_COMMON_H_ */ +diff --git a/drivers/reset/spacemit/reset-spacemit-k1.c b/drivers/reset/spacemit/reset-spacemit-k1.c +index cc7fd1f8750d..8f3b5329ea5f 100644 +--- a/drivers/reset/spacemit/reset-spacemit-k1.c ++++ b/drivers/reset/spacemit/reset-spacemit-k1.c +@@ -1,41 +1,13 @@ + // SPDX-License-Identifier: GPL-2.0-only + +-/* SpacemiT reset controller driver */ ++/* SpacemiT K1 reset controller driver */ + +-#include +-#include +-#include + #include +-#include +-#include +-#include + +-#include + #include ++#include + +-struct ccu_reset_data { +- u32 offset; +- u32 assert_mask; +- u32 deassert_mask; +-}; +- +-struct ccu_reset_controller_data { +- const struct ccu_reset_data *reset_data; /* array */ +- size_t count; +-}; +- +-struct ccu_reset_controller { +- struct reset_controller_dev rcdev; +- const struct ccu_reset_controller_data *data; +- struct regmap *regmap; +-}; +- +-#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ +- { \ +- .offset = (_offset), \ +- .assert_mask = (_assert_mask), \ +- .deassert_mask = (_deassert_mask), \ +- } ++#include "reset-spacemit-common.h" + + static const struct ccu_reset_data k1_mpmu_resets[] = { + [RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), +@@ -214,91 +186,30 @@ static const struct ccu_reset_controller_data k1_apbc2_reset_data = { + .count = ARRAY_SIZE(k1_apbc2_resets), + }; + +-static int spacemit_reset_update(struct reset_controller_dev *rcdev, +- unsigned long id, bool assert) +-{ +- struct ccu_reset_controller *controller; +- const struct ccu_reset_data *data; +- u32 mask; +- u32 val; +- +- controller = container_of(rcdev, struct ccu_reset_controller, rcdev); +- data = &controller->data->reset_data[id]; +- mask = data->assert_mask | data->deassert_mask; +- val = assert ? data->assert_mask : data->deassert_mask; +- +- return regmap_update_bits(controller->regmap, data->offset, mask, val); +-} +- +-static int spacemit_reset_assert(struct reset_controller_dev *rcdev, +- unsigned long id) +-{ +- return spacemit_reset_update(rcdev, id, true); +-} +- +-static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, +- unsigned long id) +-{ +- return spacemit_reset_update(rcdev, id, false); +-} +- +-static const struct reset_control_ops spacemit_reset_control_ops = { +- .assert = spacemit_reset_assert, +- .deassert = spacemit_reset_deassert, +-}; +- +-static int spacemit_reset_controller_register(struct device *dev, +- struct ccu_reset_controller *controller) +-{ +- struct reset_controller_dev *rcdev = &controller->rcdev; +- +- rcdev->ops = &spacemit_reset_control_ops; +- rcdev->owner = THIS_MODULE; +- rcdev->of_node = dev->of_node; +- rcdev->nr_resets = controller->data->count; +- +- return devm_reset_controller_register(dev, &controller->rcdev); +-} +- +-static int spacemit_reset_probe(struct auxiliary_device *adev, +- const struct auxiliary_device_id *id) +-{ +- struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev); +- struct ccu_reset_controller *controller; +- struct device *dev = &adev->dev; +- +- controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); +- if (!controller) +- return -ENOMEM; +- controller->data = (const struct ccu_reset_controller_data *)id->driver_data; +- controller->regmap = rdev->regmap; +- +- return spacemit_reset_controller_register(dev, controller); +-} +- + #define K1_AUX_DEV_ID(_unit) \ + { \ + .name = "spacemit_ccu.k1-" #_unit "-reset", \ + .driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ + } + +-static const struct auxiliary_device_id spacemit_reset_ids[] = { ++static const struct auxiliary_device_id spacemit_k1_reset_ids[] = { + K1_AUX_DEV_ID(mpmu), + K1_AUX_DEV_ID(apbc), + K1_AUX_DEV_ID(apmu), + K1_AUX_DEV_ID(rcpu), + K1_AUX_DEV_ID(rcpu2), + K1_AUX_DEV_ID(apbc2), +- { }, ++ { /* sentinel */ } + }; +-MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids); ++MODULE_DEVICE_TABLE(auxiliary, spacemit_k1_reset_ids); + + static struct auxiliary_driver spacemit_k1_reset_driver = { + .probe = spacemit_reset_probe, +- .id_table = spacemit_reset_ids, ++ .id_table = spacemit_k1_reset_ids, + }; + module_auxiliary_driver(spacemit_k1_reset_driver); + ++MODULE_IMPORT_NS("RESET_SPACEMIT"); + MODULE_AUTHOR("Alex Elder "); +-MODULE_DESCRIPTION("SpacemiT reset controller driver"); ++MODULE_DESCRIPTION("SpacemiT K1 reset controller driver"); + MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0124-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch b/SPECS/linux-lts/0124-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch deleted file mode 100644 index 5ef22ef32b..0000000000 --- a/SPECS/linux-lts/0124-UPSTREAM-dt-bindings-soc-spacemit-Add-K3-reset-suppo.patch +++ /dev/null @@ -1,235 +0,0 @@ -From 6eb7dce00142b5381c54a88e02ba870e0aebb1c9 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 20 Jan 2026 19:10:49 +0800 -Subject: [PATCH 124/467] UPSTREAM: dt-bindings: soc: spacemit: Add K3 reset - support and IDs - -Update the spacemit,k1-syscon.yaml binding to document K3 SoC reset -support. - -K3 reset devices are registered at runtime as auxiliary devices by the -K3 CCU driver. Since K3 reuses the K1 syscon binding, there is no separate -YAML binding file for K3 resets. - -Update #reset-cells description to document where reset IDs are defined. - -Acked-by: Alex Elder -Acked-by: Krzysztof Kozlowski -Signed-off-by: Guodong Xu -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] -Signed-off-by: Philipp Zabel -(cherry picked from commit 216e0a5e98e5f0f02a818884e8acf340892cecae) -Signed-off-by: Han Gao ---- - .../soc/spacemit/spacemit,k1-syscon.yaml | 8 +- - .../dt-bindings/reset/spacemit,k3-resets.h | 171 ++++++++++++++++++ - 2 files changed, 178 insertions(+), 1 deletion(-) - create mode 100644 include/dt-bindings/reset/spacemit,k3-resets.h - -diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml -index d87131da30bc..d3a7c93c3c54 100644 ---- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml -+++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml -@@ -10,7 +10,7 @@ maintainers: - - Haylen Chu - - description: -- System controllers found on SpacemiT K1 SoC, which are capable of -+ System controllers found on SpacemiT K1/K3 SoC, which are capable of - clock, reset and power-management functions. - - properties: -@@ -51,6 +51,12 @@ properties: - - "#reset-cells": - const: 1 -+ description: | -+ ID of the reset controller line. Valid IDs are defined in corresponding -+ files: -+ -+ For SpacemiT K1, see include/dt-bindings/clock/spacemit,k1-syscon.h -+ For SpacemiT K3, see include/dt-bindings/reset/spacemit,k3-resets.h - - required: - - compatible -diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h -new file mode 100644 -index 000000000000..79ac1c22b7b5 ---- /dev/null -+++ b/include/dt-bindings/reset/spacemit,k3-resets.h -@@ -0,0 +1,171 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd -+ */ -+ -+#ifndef _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ -+#define _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ -+ -+/* MPMU resets */ -+#define RESET_MPMU_WDT 0 -+#define RESET_MPMU_RIPC 1 -+ -+/* APBC resets */ -+#define RESET_APBC_UART0 0 -+#define RESET_APBC_UART2 1 -+#define RESET_APBC_UART3 2 -+#define RESET_APBC_UART4 3 -+#define RESET_APBC_UART5 4 -+#define RESET_APBC_UART6 5 -+#define RESET_APBC_UART7 6 -+#define RESET_APBC_UART8 7 -+#define RESET_APBC_UART9 8 -+#define RESET_APBC_UART10 9 -+#define RESET_APBC_GPIO 10 -+#define RESET_APBC_PWM0 11 -+#define RESET_APBC_PWM1 12 -+#define RESET_APBC_PWM2 13 -+#define RESET_APBC_PWM3 14 -+#define RESET_APBC_PWM4 15 -+#define RESET_APBC_PWM5 16 -+#define RESET_APBC_PWM6 17 -+#define RESET_APBC_PWM7 18 -+#define RESET_APBC_PWM8 19 -+#define RESET_APBC_PWM9 20 -+#define RESET_APBC_PWM10 21 -+#define RESET_APBC_PWM11 22 -+#define RESET_APBC_PWM12 23 -+#define RESET_APBC_PWM13 24 -+#define RESET_APBC_PWM14 25 -+#define RESET_APBC_PWM15 26 -+#define RESET_APBC_PWM16 27 -+#define RESET_APBC_PWM17 28 -+#define RESET_APBC_PWM18 29 -+#define RESET_APBC_PWM19 30 -+#define RESET_APBC_SPI0 31 -+#define RESET_APBC_SPI1 32 -+#define RESET_APBC_SPI3 33 -+#define RESET_APBC_RTC 34 -+#define RESET_APBC_TWSI0 35 -+#define RESET_APBC_TWSI1 36 -+#define RESET_APBC_TWSI2 37 -+#define RESET_APBC_TWSI4 38 -+#define RESET_APBC_TWSI5 39 -+#define RESET_APBC_TWSI6 40 -+#define RESET_APBC_TWSI8 41 -+#define RESET_APBC_TIMERS0 42 -+#define RESET_APBC_TIMERS1 43 -+#define RESET_APBC_TIMERS2 44 -+#define RESET_APBC_TIMERS3 45 -+#define RESET_APBC_TIMERS4 46 -+#define RESET_APBC_TIMERS5 47 -+#define RESET_APBC_TIMERS6 48 -+#define RESET_APBC_TIMERS7 49 -+#define RESET_APBC_AIB 50 -+#define RESET_APBC_ONEWIRE 51 -+#define RESET_APBC_I2S0 52 -+#define RESET_APBC_I2S1 53 -+#define RESET_APBC_I2S2 54 -+#define RESET_APBC_I2S3 55 -+#define RESET_APBC_I2S4 56 -+#define RESET_APBC_I2S5 57 -+#define RESET_APBC_DRO 58 -+#define RESET_APBC_IR0 59 -+#define RESET_APBC_IR1 60 -+#define RESET_APBC_TSEN 61 -+#define RESET_IPC_AP2AUD 62 -+#define RESET_APBC_CAN0 63 -+#define RESET_APBC_CAN1 64 -+#define RESET_APBC_CAN2 65 -+#define RESET_APBC_CAN3 66 -+#define RESET_APBC_CAN4 67 -+ -+/* APMU resets */ -+#define RESET_APMU_CSI 0 -+#define RESET_APMU_CCIC2PHY 1 -+#define RESET_APMU_CCIC3PHY 2 -+#define RESET_APMU_ISP_CIBUS 3 -+#define RESET_APMU_DSI_ESC 4 -+#define RESET_APMU_LCD 5 -+#define RESET_APMU_V2D 6 -+#define RESET_APMU_LCD_MCLK 7 -+#define RESET_APMU_LCD_DSCCLK 8 -+#define RESET_APMU_SC2_HCLK 9 -+#define RESET_APMU_CCIC_4X 10 -+#define RESET_APMU_CCIC1_PHY 11 -+#define RESET_APMU_SDH_AXI 12 -+#define RESET_APMU_SDH0 13 -+#define RESET_APMU_SDH1 14 -+#define RESET_APMU_SDH2 15 -+#define RESET_APMU_USB2 16 -+#define RESET_APMU_USB3_PORTA 17 -+#define RESET_APMU_USB3_PORTB 18 -+#define RESET_APMU_USB3_PORTC 19 -+#define RESET_APMU_USB3_PORTD 20 -+#define RESET_APMU_QSPI 21 -+#define RESET_APMU_QSPI_BUS 22 -+#define RESET_APMU_DMA 23 -+#define RESET_APMU_AES_WTM 24 -+#define RESET_APMU_MCB_DCLK 25 -+#define RESET_APMU_MCB_ACLK 26 -+#define RESET_APMU_VPU 27 -+#define RESET_APMU_DTC 28 -+#define RESET_APMU_GPU 29 -+#define RESET_APMU_ALZO 30 -+#define RESET_APMU_MC 31 -+#define RESET_APMU_CPU0_POP 32 -+#define RESET_APMU_CPU0_SW 33 -+#define RESET_APMU_CPU1_POP 34 -+#define RESET_APMU_CPU1_SW 35 -+#define RESET_APMU_CPU2_POP 36 -+#define RESET_APMU_CPU2_SW 37 -+#define RESET_APMU_CPU3_POP 38 -+#define RESET_APMU_CPU3_SW 39 -+#define RESET_APMU_C0_MPSUB_SW 40 -+#define RESET_APMU_CPU4_POP 41 -+#define RESET_APMU_CPU4_SW 42 -+#define RESET_APMU_CPU5_POP 43 -+#define RESET_APMU_CPU5_SW 44 -+#define RESET_APMU_CPU6_POP 45 -+#define RESET_APMU_CPU6_SW 46 -+#define RESET_APMU_CPU7_POP 47 -+#define RESET_APMU_CPU7_SW 48 -+#define RESET_APMU_C1_MPSUB_SW 49 -+#define RESET_APMU_MPSUB_DBG 50 -+#define RESET_APMU_UCIE 51 -+#define RESET_APMU_RCPU 52 -+#define RESET_APMU_DSI4LN2_ESCCLK 53 -+#define RESET_APMU_DSI4LN2_LCD_SW 54 -+#define RESET_APMU_DSI4LN2_LCD_MCLK 55 -+#define RESET_APMU_DSI4LN2_LCD_DSCCLK 56 -+#define RESET_APMU_DSI4LN2_DPU_ACLK 57 -+#define RESET_APMU_DPU_ACLK 58 -+#define RESET_APMU_UFS_ACLK 59 -+#define RESET_APMU_EDP0 60 -+#define RESET_APMU_EDP1 61 -+#define RESET_APMU_PCIE_PORTA 62 -+#define RESET_APMU_PCIE_PORTB 63 -+#define RESET_APMU_PCIE_PORTC 64 -+#define RESET_APMU_PCIE_PORTD 65 -+#define RESET_APMU_PCIE_PORTE 66 -+#define RESET_APMU_EMAC0 67 -+#define RESET_APMU_EMAC1 68 -+#define RESET_APMU_EMAC2 69 -+#define RESET_APMU_ESPI_MCLK 70 -+#define RESET_APMU_ESPI_SCLK 71 -+ -+/* DCIU resets*/ -+#define RESET_DCIU_HDMA 0 -+#define RESET_DCIU_DMA350 1 -+#define RESET_DCIU_DMA350_0 2 -+#define RESET_DCIU_DMA350_1 3 -+#define RESET_DCIU_AXIDMA0 4 -+#define RESET_DCIU_AXIDMA1 5 -+#define RESET_DCIU_AXIDMA2 6 -+#define RESET_DCIU_AXIDMA3 7 -+#define RESET_DCIU_AXIDMA4 8 -+#define RESET_DCIU_AXIDMA5 9 -+#define RESET_DCIU_AXIDMA6 10 -+#define RESET_DCIU_AXIDMA7 11 -+ -+#endif /* _DT_BINDINGS_RESET_SPACEMIT_K3_H_ */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch b/SPECS/linux-lts/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch new file mode 100644 index 0000000000..3e39a6ab56 --- /dev/null +++ b/SPECS/linux-lts/0124-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch @@ -0,0 +1,299 @@ +From ba7026a22c43e830be9a0dccce75c3867b2bcaad Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 20 Jan 2026 19:10:52 +0800 +Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: Add SpacemiT K3 reset driver + +Add support for the SpacemiT K3 SoC reset controller. The K3 reset +driver reuses the common reset controller code and provides K3-specific +reset data for devices managed by the following units: + + - MPMU (Main Power Management Unit) + - APBC (APB clock unit) + - APMU (Application Subsystem Power Management Unit) + - DCIU (DMA Control and Interface Unit) + +Acked-by: Alex Elder +Signed-off-by: Guodong Xu +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] +Signed-off-by: Philipp Zabel +(cherry picked from commit 938ce3b16582657e67f3bd8a7efa59089c467c90) +Signed-off-by: Han Gao +--- + drivers/reset/spacemit/Kconfig | 11 + + drivers/reset/spacemit/Makefile | 1 + + drivers/reset/spacemit/reset-spacemit-k3.c | 233 +++++++++++++++++++++ + 3 files changed, 245 insertions(+) + create mode 100644 drivers/reset/spacemit/reset-spacemit-k3.c + +diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig +index 56a4858b30e1..545d6b41c6ca 100644 +--- a/drivers/reset/spacemit/Kconfig ++++ b/drivers/reset/spacemit/Kconfig +@@ -22,4 +22,15 @@ config RESET_SPACEMIT_K1 + unit (CCU) driver to provide reset control functionality + for various peripherals and subsystems in the SoC. + ++config RESET_SPACEMIT_K3 ++ tristate "Support for SpacemiT K3 SoC" ++ depends on SPACEMIT_K3_CCU ++ select RESET_SPACEMIT_COMMON ++ default SPACEMIT_K3_CCU ++ help ++ Support for reset controller in SpacemiT K3 SoC. ++ This driver works with the SpacemiT K3 clock controller ++ unit (CCU) driver to provide reset control functionality ++ for various peripherals and subsystems in the SoC. ++ + endmenu +diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile +index 0b056e8661ec..00669132c6ac 100644 +--- a/drivers/reset/spacemit/Makefile ++++ b/drivers/reset/spacemit/Makefile +@@ -2,3 +2,4 @@ + obj-$(CONFIG_RESET_SPACEMIT_COMMON) += reset-spacemit-common.o + + obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o ++obj-$(CONFIG_RESET_SPACEMIT_K3) += reset-spacemit-k3.o +diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c +new file mode 100644 +index 000000000000..e9e32e4c1ba5 +--- /dev/null ++++ b/drivers/reset/spacemit/reset-spacemit-k3.c +@@ -0,0 +1,233 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++/* SpacemiT K3 reset controller driver */ ++ ++#include ++ ++#include ++#include ++ ++#include "reset-spacemit-common.h" ++ ++static const struct ccu_reset_data k3_mpmu_resets[] = { ++ [RESET_MPMU_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), ++ [RESET_MPMU_RIPC] = RESET_DATA(MPMU_RIPCCR, BIT(2), 0), ++}; ++ ++static const struct ccu_reset_controller_data k3_mpmu_reset_data = { ++ .reset_data = k3_mpmu_resets, ++ .count = ARRAY_SIZE(k3_mpmu_resets), ++}; ++ ++static const struct ccu_reset_data k3_apbc_resets[] = { ++ [RESET_APBC_UART0] = RESET_DATA(APBC_UART0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), ++ [RESET_APBC_UART10] = RESET_DATA(APBC_UART10_CLK_RST, BIT(2), 0), ++ [RESET_APBC_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), 0), ++ [RESET_APBC_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), 0), ++ [RESET_APBC_SPI0] = RESET_DATA(APBC_SSP0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_SPI1] = RESET_DATA(APBC_SSP1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_SPI3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS0] = RESET_DATA(APBC_TIMERS0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS3] = RESET_DATA(APBC_TIMERS3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS4] = RESET_DATA(APBC_TIMERS4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS5] = RESET_DATA(APBC_TIMERS5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS6] = RESET_DATA(APBC_TIMERS6_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TIMERS7] = RESET_DATA(APBC_TIMERS7_CLK_RST, BIT(2), 0), ++ [RESET_APBC_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), ++ [RESET_APBC_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S2] = RESET_DATA(APBC_SSPA2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S3] = RESET_DATA(APBC_SSPA3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S4] = RESET_DATA(APBC_SSPA4_CLK_RST, BIT(2), 0), ++ [RESET_APBC_I2S5] = RESET_DATA(APBC_SSPA5_CLK_RST, BIT(2), 0), ++ [RESET_APBC_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), ++ [RESET_APBC_IR0] = RESET_DATA(APBC_IR0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_IR1] = RESET_DATA(APBC_IR1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), ++ [RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN1] = RESET_DATA(APBC_CAN1_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN2] = RESET_DATA(APBC_CAN2_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN3] = RESET_DATA(APBC_CAN3_CLK_RST, BIT(2), 0), ++ [RESET_APBC_CAN4] = RESET_DATA(APBC_CAN4_CLK_RST, BIT(2), 0), ++}; ++ ++static const struct ccu_reset_controller_data k3_apbc_reset_data = { ++ .reset_data = k3_apbc_resets, ++ .count = ARRAY_SIZE(k3_apbc_resets), ++}; ++ ++static const struct ccu_reset_data k3_apmu_resets[] = { ++ [RESET_APMU_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_APMU_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), ++ [RESET_APMU_ISP_CIBUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), ++ [RESET_APMU_DSI_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), ++ [RESET_APMU_LCD] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), ++ [RESET_APMU_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), ++ [RESET_APMU_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), ++ [RESET_APMU_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(15)), ++ [RESET_APMU_SC2_HCLK] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_APMU_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(1)|BIT(2)|BIT(3)), ++ [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(5)|BIT(6)|BIT(7)), ++ [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(9)|BIT(10)|BIT(11)), ++ [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(13)|BIT(14)|BIT(15)), ++ [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, ++ BIT(17)|BIT(18)|BIT(19)), ++ [RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_AES_WTM] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), ++ [RESET_APMU_MCB_DCLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_MCB_ACLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_DTC] = RESET_DATA(APMU_DTC_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), ++ [RESET_APMU_CPU0_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(0), 0), ++ [RESET_APMU_CPU0_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(1), 0), ++ [RESET_APMU_CPU1_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(3), 0), ++ [RESET_APMU_CPU1_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(4), 0), ++ [RESET_APMU_CPU2_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(6), 0), ++ [RESET_APMU_CPU2_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(7), 0), ++ [RESET_APMU_CPU3_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(9), 0), ++ [RESET_APMU_CPU3_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(10), 0), ++ [RESET_APMU_C0_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(12), 0), ++ [RESET_APMU_CPU4_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(16), 0), ++ [RESET_APMU_CPU4_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(17), 0), ++ [RESET_APMU_CPU5_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(19), 0), ++ [RESET_APMU_CPU5_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(20), 0), ++ [RESET_APMU_CPU6_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(22), 0), ++ [RESET_APMU_CPU6_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(23), 0), ++ [RESET_APMU_CPU7_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(25), 0), ++ [RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), ++ [RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), ++ [RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), ++ [RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL, ++ BIT(1) | BIT(2) | BIT(3), 0), ++ [RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, ++ BIT(3) | BIT(2) | BIT(0)), ++ [RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)), ++ [RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)), ++ [RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)), ++ [RESET_APMU_DSI4LN2_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(15)), ++ [RESET_APMU_DSI4LN2_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(0)), ++ [RESET_APMU_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(15)), ++ [RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), ++ [RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), ++ [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, ++ BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_ESPI_MCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_ESPI_SCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(2)), ++}; ++ ++static const struct ccu_reset_controller_data k3_apmu_reset_data = { ++ .reset_data = k3_apmu_resets, ++ .count = ARRAY_SIZE(k3_apmu_resets), ++}; ++ ++static const struct ccu_reset_data k3_dciu_resets[] = { ++ [RESET_DCIU_HDMA] = RESET_DATA(DCIU_DMASYS_RSTN, 0, BIT(0)), ++ [RESET_DCIU_DMA350] = RESET_DATA(DCIU_DMASYS_SDMA_RSTN, 0, BIT(0)), ++ [RESET_DCIU_DMA350_0] = RESET_DATA(DCIU_DMASYS_S0_RSTN, 0, BIT(0)), ++ [RESET_DCIU_DMA350_1] = RESET_DATA(DCIU_DMASYS_S1_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA0] = RESET_DATA(DCIU_DMASYS_A0_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA1] = RESET_DATA(DCIU_DMASYS_A1_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA2] = RESET_DATA(DCIU_DMASYS_A2_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA3] = RESET_DATA(DCIU_DMASYS_A3_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA4] = RESET_DATA(DCIU_DMASYS_A4_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA5] = RESET_DATA(DCIU_DMASYS_A5_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA6] = RESET_DATA(DCIU_DMASYS_A6_RSTN, 0, BIT(0)), ++ [RESET_DCIU_AXIDMA7] = RESET_DATA(DCIU_DMASYS_A7_RSTN, 0, BIT(0)), ++}; ++ ++static const struct ccu_reset_controller_data k3_dciu_reset_data = { ++ .reset_data = k3_dciu_resets, ++ .count = ARRAY_SIZE(k3_dciu_resets), ++}; ++ ++#define K3_AUX_DEV_ID(_unit) \ ++ { \ ++ .name = "spacemit_ccu.k3-" #_unit "-reset", \ ++ .driver_data = (kernel_ulong_t)&k3_ ## _unit ## _reset_data, \ ++ } ++ ++static const struct auxiliary_device_id spacemit_k3_reset_ids[] = { ++ K3_AUX_DEV_ID(mpmu), ++ K3_AUX_DEV_ID(apbc), ++ K3_AUX_DEV_ID(apmu), ++ K3_AUX_DEV_ID(dciu), ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(auxiliary, spacemit_k3_reset_ids); ++ ++static struct auxiliary_driver spacemit_k3_reset_driver = { ++ .probe = spacemit_reset_probe, ++ .id_table = spacemit_k3_reset_ids, ++}; ++module_auxiliary_driver(spacemit_k3_reset_driver); ++ ++MODULE_IMPORT_NS("RESET_SPACEMIT"); ++MODULE_AUTHOR("Guodong Xu "); ++MODULE_DESCRIPTION("SpacemiT K3 reset controller driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch b/SPECS/linux-lts/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch new file mode 100644 index 0000000000..87f1321e5c --- /dev/null +++ b/SPECS/linux-lts/0125-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch @@ -0,0 +1,36 @@ +From 69b50555993d0e015534df599be1be5f756f84ea Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 6 Jan 2026 11:09:32 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: gpio: spacemit: add compatible + name for K3 SoC + +Add new compatible string for SpacemiT K3 SoC's GPIO controller. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260106-02-k3-gpio-v3-1-4800c214810b@gentoo.org +Signed-off-by: Bartosz Golaszewski +(cherry picked from commit 48033e4c677be4e3f131df454d44a5d1fb1b334f) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml +index 83e0b2d14c9f..24d22d95665f 100644 +--- a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml ++++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml +@@ -19,7 +19,9 @@ properties: + pattern: "^gpio@[0-9a-f]+$" + + compatible: +- const: spacemit,k1-gpio ++ enum: ++ - spacemit,k1-gpio ++ - spacemit,k3-gpio + + reg: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0125-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch b/SPECS/linux-lts/0125-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch deleted file mode 100644 index afc9137c09..0000000000 --- a/SPECS/linux-lts/0125-UPSTREAM-reset-Create-subdirectory-for-SpacemiT-driv.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 9049262f9ac3ca9c394670007ce66ff407629b3d Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 20 Jan 2026 19:10:50 +0800 -Subject: [PATCH 125/467] UPSTREAM: reset: Create subdirectory for SpacemiT - drivers - -Create a dedicated subdirectory for SpacemiT reset drivers to allow -for better organization as support for more SoCs is added. - -Move the existing K1 reset driver into this new directory and rename -it to reset-spacemit-k1.c. - -Rename the Kconfig symbol to RESET_SPACEMIT_K1 and update its default -from ARCH_SPACEMIT to SPACEMIT_K1_CCU. The reset driver depends on the -clock driver to register reset devices as an auxiliary device, so the -default should reflect this dependency. - -Also sort the drivers/reset/Kconfig entries alphabetically. - -Reviewed-by: Alex Elder -Signed-off-by: Guodong Xu -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] -Signed-off-by: Philipp Zabel -(cherry picked from commit 2875b4b5d2657ff2fd979103d88e9afcae51481c) -Signed-off-by: Han Gao ---- - drivers/reset/Kconfig | 12 ++---------- - drivers/reset/Makefile | 2 +- - drivers/reset/spacemit/Kconfig | 14 ++++++++++++++ - drivers/reset/spacemit/Makefile | 2 ++ - .../reset-spacemit-k1.c} | 0 - 5 files changed, 19 insertions(+), 11 deletions(-) - create mode 100644 drivers/reset/spacemit/Kconfig - create mode 100644 drivers/reset/spacemit/Makefile - rename drivers/reset/{reset-spacemit.c => spacemit/reset-spacemit-k1.c} (100%) - -diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig -index b3b9e0f9d8c4..096f57fb7ccf 100644 ---- a/drivers/reset/Kconfig -+++ b/drivers/reset/Kconfig -@@ -286,15 +286,6 @@ config RESET_SOCFPGA - This enables the reset driver for the SoCFPGA ARMv7 platforms. This - driver gets initialized early during platform init calls. - --config RESET_SPACEMIT -- tristate "SpacemiT reset driver" -- depends on ARCH_SPACEMIT || COMPILE_TEST -- select AUXILIARY_BUS -- default ARCH_SPACEMIT -- help -- This enables the reset controller driver for SpacemiT SoCs, -- including the K1. -- - config RESET_SUNPLUS - bool "Sunplus SoCs Reset Driver" if COMPILE_TEST - default ARCH_SUNPLUS -@@ -393,9 +384,10 @@ config RESET_ZYNQMP - This enables the reset controller driver for Xilinx ZynqMP SoCs. - - source "drivers/reset/amlogic/Kconfig" -+source "drivers/reset/hisilicon/Kconfig" -+source "drivers/reset/spacemit/Kconfig" - source "drivers/reset/starfive/Kconfig" - source "drivers/reset/sti/Kconfig" --source "drivers/reset/hisilicon/Kconfig" - source "drivers/reset/tegra/Kconfig" - - endif -diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile -index f7934f9fb90b..e0934ab7153c 100644 ---- a/drivers/reset/Makefile -+++ b/drivers/reset/Makefile -@@ -2,6 +2,7 @@ - obj-y += core.o - obj-y += amlogic/ - obj-y += hisilicon/ -+obj-y += spacemit/ - obj-y += starfive/ - obj-y += sti/ - obj-y += tegra/ -@@ -37,7 +38,6 @@ obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o - obj-$(CONFIG_RESET_SCMI) += reset-scmi.o - obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o - obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o --obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o - obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o - obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o - obj-$(CONFIG_RESET_TH1520) += reset-th1520.o -diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig -new file mode 100644 -index 000000000000..552884e8b72a ---- /dev/null -+++ b/drivers/reset/spacemit/Kconfig -@@ -0,0 +1,14 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config RESET_SPACEMIT_K1 -+ tristate "SpacemiT K1 reset driver" -+ depends on ARCH_SPACEMIT || COMPILE_TEST -+ depends on SPACEMIT_K1_CCU -+ select AUXILIARY_BUS -+ default SPACEMIT_K1_CCU -+ help -+ Support for reset controller in SpacemiT K1 SoC. -+ This driver works with the SpacemiT K1 clock controller -+ unit (CCU) driver to provide reset control functionality -+ for various peripherals and subsystems in the SoC. -+ -diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile -new file mode 100644 -index 000000000000..34e3350136bb ---- /dev/null -+++ b/drivers/reset/spacemit/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o -diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/spacemit/reset-spacemit-k1.c -similarity index 100% -rename from drivers/reset/reset-spacemit.c -rename to drivers/reset/spacemit/reset-spacemit-k1.c --- -2.53.0 - diff --git a/SPECS/linux-lts/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch b/SPECS/linux-lts/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch new file mode 100644 index 0000000000..7b6a45b12a --- /dev/null +++ b/SPECS/linux-lts/0126-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch @@ -0,0 +1,316 @@ +From 409dadffdee997565a81b01180b046890adbdd47 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 6 Jan 2026 11:09:33 +0800 +Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit: Add GPIO support for K3 SoC + +SpacemiT K3 SoC has changed gpio register layout while comparing +with previous generation, the register offset and bank offset +need to be adjusted, introduce a compatible data to extend the +driver to support this. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260106-02-k3-gpio-v3-2-4800c214810b@gentoo.org +Signed-off-by: Bartosz Golaszewski +(cherry picked from commit da64eb51595bc6073b2fb69c2a3859bba93ed75a) +Signed-off-by: Han Gao +--- + drivers/gpio/gpio-spacemit-k1.c | 163 +++++++++++++++++++++++--------- + 1 file changed, 117 insertions(+), 46 deletions(-) + +diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c +index eb66a15c002f..8f570a1a4894 100644 +--- a/drivers/gpio/gpio-spacemit-k1.c ++++ b/drivers/gpio/gpio-spacemit-k1.c +@@ -15,29 +15,37 @@ + #include + #include + +-/* register offset */ +-#define SPACEMIT_GPLR 0x00 /* port level - R */ +-#define SPACEMIT_GPDR 0x0c /* port direction - R/W */ +-#define SPACEMIT_GPSR 0x18 /* port set - W */ +-#define SPACEMIT_GPCR 0x24 /* port clear - W */ +-#define SPACEMIT_GRER 0x30 /* port rising edge R/W */ +-#define SPACEMIT_GFER 0x3c /* port falling edge R/W */ +-#define SPACEMIT_GEDR 0x48 /* edge detect status - R/W1C */ +-#define SPACEMIT_GSDR 0x54 /* (set) direction - W */ +-#define SPACEMIT_GCDR 0x60 /* (clear) direction - W */ +-#define SPACEMIT_GSRER 0x6c /* (set) rising edge detect enable - W */ +-#define SPACEMIT_GCRER 0x78 /* (clear) rising edge detect enable - W */ +-#define SPACEMIT_GSFER 0x84 /* (set) falling edge detect enable - W */ +-#define SPACEMIT_GCFER 0x90 /* (clear) falling edge detect enable - W */ +-#define SPACEMIT_GAPMASK 0x9c /* interrupt mask , 0 disable, 1 enable - R/W */ +- + #define SPACEMIT_NR_BANKS 4 + #define SPACEMIT_NR_GPIOS_PER_BANK 32 + + #define to_spacemit_gpio_bank(x) container_of((x), struct spacemit_gpio_bank, gc) ++#define to_spacemit_gpio_regs(gb) ((gb)->sg->data->offsets) ++ ++enum spacemit_gpio_registers { ++ SPACEMIT_GPLR, /* port level - R */ ++ SPACEMIT_GPDR, /* port direction - R/W */ ++ SPACEMIT_GPSR, /* port set - W */ ++ SPACEMIT_GPCR, /* port clear - W */ ++ SPACEMIT_GRER, /* port rising edge R/W */ ++ SPACEMIT_GFER, /* port falling edge R/W */ ++ SPACEMIT_GEDR, /* edge detect status - R/W1C */ ++ SPACEMIT_GSDR, /* (set) direction - W */ ++ SPACEMIT_GCDR, /* (clear) direction - W */ ++ SPACEMIT_GSRER, /* (set) rising edge detect enable - W */ ++ SPACEMIT_GCRER, /* (clear) rising edge detect enable - W */ ++ SPACEMIT_GSFER, /* (set) falling edge detect enable - W */ ++ SPACEMIT_GCFER, /* (clear) falling edge detect enable - W */ ++ SPACEMIT_GAPMASK, /* interrupt mask , 0 disable, 1 enable - R/W */ ++ SPACEMIT_GCPMASK, /* interrupt mask for K3 */ ++}; + + struct spacemit_gpio; + ++struct spacemit_gpio_data { ++ const unsigned int *offsets; ++ u32 bank_offsets[SPACEMIT_NR_BANKS]; ++}; ++ + struct spacemit_gpio_bank { + struct gpio_generic_chip chip; + struct spacemit_gpio *sg; +@@ -49,9 +57,22 @@ struct spacemit_gpio_bank { + + struct spacemit_gpio { + struct device *dev; ++ const struct spacemit_gpio_data *data; + struct spacemit_gpio_bank sgb[SPACEMIT_NR_BANKS]; + }; + ++static u32 spacemit_gpio_read(struct spacemit_gpio_bank *gb, ++ enum spacemit_gpio_registers reg) ++{ ++ return readl(gb->base + to_spacemit_gpio_regs(gb)[reg]); ++} ++ ++static void spacemit_gpio_write(struct spacemit_gpio_bank *gb, ++ enum spacemit_gpio_registers reg, u32 val) ++{ ++ writel(val, gb->base + to_spacemit_gpio_regs(gb)[reg]); ++} ++ + static u32 spacemit_gpio_bank_index(struct spacemit_gpio_bank *gb) + { + return (u32)(gb - gb->sg->sgb); +@@ -63,10 +84,10 @@ static irqreturn_t spacemit_gpio_irq_handler(int irq, void *dev_id) + unsigned long pending; + u32 n, gedr; + +- gedr = readl(gb->base + SPACEMIT_GEDR); ++ gedr = spacemit_gpio_read(gb, SPACEMIT_GEDR); + if (!gedr) + return IRQ_NONE; +- writel(gedr, gb->base + SPACEMIT_GEDR); ++ spacemit_gpio_write(gb, SPACEMIT_GEDR, gedr); + + pending = gedr & gb->irq_mask; + if (!pending) +@@ -82,7 +103,7 @@ static void spacemit_gpio_irq_ack(struct irq_data *d) + { + struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d); + +- writel(BIT(irqd_to_hwirq(d)), gb->base + SPACEMIT_GEDR); ++ spacemit_gpio_write(gb, SPACEMIT_GEDR, BIT(irqd_to_hwirq(d))); + } + + static void spacemit_gpio_irq_mask(struct irq_data *d) +@@ -91,13 +112,13 @@ static void spacemit_gpio_irq_mask(struct irq_data *d) + u32 bit = BIT(irqd_to_hwirq(d)); + + gb->irq_mask &= ~bit; +- writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK); ++ spacemit_gpio_write(gb, SPACEMIT_GAPMASK, gb->irq_mask); + + if (bit & gb->irq_rising_edge) +- writel(bit, gb->base + SPACEMIT_GCRER); ++ spacemit_gpio_write(gb, SPACEMIT_GCRER, bit); + + if (bit & gb->irq_falling_edge) +- writel(bit, gb->base + SPACEMIT_GCFER); ++ spacemit_gpio_write(gb, SPACEMIT_GCFER, bit); + } + + static void spacemit_gpio_irq_unmask(struct irq_data *d) +@@ -108,12 +129,12 @@ static void spacemit_gpio_irq_unmask(struct irq_data *d) + gb->irq_mask |= bit; + + if (bit & gb->irq_rising_edge) +- writel(bit, gb->base + SPACEMIT_GSRER); ++ spacemit_gpio_write(gb, SPACEMIT_GSRER, bit); + + if (bit & gb->irq_falling_edge) +- writel(bit, gb->base + SPACEMIT_GSFER); ++ spacemit_gpio_write(gb, SPACEMIT_GSFER, bit); + +- writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK); ++ spacemit_gpio_write(gb, SPACEMIT_GAPMASK, gb->irq_mask); + } + + static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int type) +@@ -123,18 +144,18 @@ static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int type) + + if (type & IRQ_TYPE_EDGE_RISING) { + gb->irq_rising_edge |= bit; +- writel(bit, gb->base + SPACEMIT_GSRER); ++ spacemit_gpio_write(gb, SPACEMIT_GSRER, bit); + } else { + gb->irq_rising_edge &= ~bit; +- writel(bit, gb->base + SPACEMIT_GCRER); ++ spacemit_gpio_write(gb, SPACEMIT_GCRER, bit); + } + + if (type & IRQ_TYPE_EDGE_FALLING) { + gb->irq_falling_edge |= bit; +- writel(bit, gb->base + SPACEMIT_GSFER); ++ spacemit_gpio_write(gb, SPACEMIT_GSFER, bit); + } else { + gb->irq_falling_edge &= ~bit; +- writel(bit, gb->base + SPACEMIT_GCFER); ++ spacemit_gpio_write(gb, SPACEMIT_GCFER, bit); + } + + return 0; +@@ -179,15 +200,16 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + struct device *dev = sg->dev; + struct gpio_irq_chip *girq; + void __iomem *dat, *set, *clr, *dirin, *dirout; +- int ret, bank_base[] = { 0x0, 0x4, 0x8, 0x100 }; ++ int ret; + +- gb->base = regs + bank_base[index]; ++ gb->base = regs + sg->data->bank_offsets[index]; ++ gb->sg = sg; + +- dat = gb->base + SPACEMIT_GPLR; +- set = gb->base + SPACEMIT_GPSR; +- clr = gb->base + SPACEMIT_GPCR; +- dirin = gb->base + SPACEMIT_GCDR; +- dirout = gb->base + SPACEMIT_GSDR; ++ dat = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPLR]; ++ set = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPSR]; ++ clr = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPCR]; ++ dirin = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GCDR]; ++ dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GSDR]; + + config = (struct gpio_generic_chip_config) { + .dev = dev, +@@ -206,8 +228,6 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + if (ret) + return dev_err_probe(dev, ret, "failed to init gpio chip\n"); + +- gb->sg = sg; +- + gc->label = dev_name(dev); + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; +@@ -223,13 +243,13 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + gpio_irq_chip_set_chip(girq, &spacemit_gpio_chip); + + /* Disable Interrupt */ +- writel(0, gb->base + SPACEMIT_GAPMASK); ++ spacemit_gpio_write(gb, SPACEMIT_GAPMASK, 0); + /* Disable Edge Detection Settings */ +- writel(0x0, gb->base + SPACEMIT_GRER); +- writel(0x0, gb->base + SPACEMIT_GFER); ++ spacemit_gpio_write(gb, SPACEMIT_GRER, 0x0); ++ spacemit_gpio_write(gb, SPACEMIT_GFER, 0x0); + /* Clear Interrupt */ +- writel(0xffffffff, gb->base + SPACEMIT_GCRER); +- writel(0xffffffff, gb->base + SPACEMIT_GCFER); ++ spacemit_gpio_write(gb, SPACEMIT_GCRER, 0xffffffff); ++ spacemit_gpio_write(gb, SPACEMIT_GCFER, 0xffffffff); + + ret = devm_request_threaded_irq(dev, irq, NULL, + spacemit_gpio_irq_handler, +@@ -260,6 +280,10 @@ static int spacemit_gpio_probe(struct platform_device *pdev) + if (!sg) + return -ENOMEM; + ++ sg->data = of_device_get_match_data(dev); ++ if (!sg->data) ++ return dev_err_probe(dev, -EINVAL, "No available compatible data."); ++ + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); +@@ -287,8 +311,55 @@ static int spacemit_gpio_probe(struct platform_device *pdev) + return 0; + } + ++static const unsigned int spacemit_gpio_k1_offsets[] = { ++ [SPACEMIT_GPLR] = 0x00, ++ [SPACEMIT_GPDR] = 0x0c, ++ [SPACEMIT_GPSR] = 0x18, ++ [SPACEMIT_GPCR] = 0x24, ++ [SPACEMIT_GRER] = 0x30, ++ [SPACEMIT_GFER] = 0x3c, ++ [SPACEMIT_GEDR] = 0x48, ++ [SPACEMIT_GSDR] = 0x54, ++ [SPACEMIT_GCDR] = 0x60, ++ [SPACEMIT_GSRER] = 0x6c, ++ [SPACEMIT_GCRER] = 0x78, ++ [SPACEMIT_GSFER] = 0x84, ++ [SPACEMIT_GCFER] = 0x90, ++ [SPACEMIT_GAPMASK] = 0x9c, ++ [SPACEMIT_GCPMASK] = 0xA8, ++}; ++ ++static const unsigned int spacemit_gpio_k3_offsets[] = { ++ [SPACEMIT_GPLR] = 0x0, ++ [SPACEMIT_GPDR] = 0x4, ++ [SPACEMIT_GPSR] = 0x8, ++ [SPACEMIT_GPCR] = 0xc, ++ [SPACEMIT_GRER] = 0x10, ++ [SPACEMIT_GFER] = 0x14, ++ [SPACEMIT_GEDR] = 0x18, ++ [SPACEMIT_GSDR] = 0x1c, ++ [SPACEMIT_GCDR] = 0x20, ++ [SPACEMIT_GSRER] = 0x24, ++ [SPACEMIT_GCRER] = 0x28, ++ [SPACEMIT_GSFER] = 0x2c, ++ [SPACEMIT_GCFER] = 0x30, ++ [SPACEMIT_GAPMASK] = 0x34, ++ [SPACEMIT_GCPMASK] = 0x38, ++}; ++ ++static const struct spacemit_gpio_data k1_gpio_data = { ++ .offsets = spacemit_gpio_k1_offsets, ++ .bank_offsets = { 0x0, 0x4, 0x8, 0x100 }, ++}; ++ ++static const struct spacemit_gpio_data k3_gpio_data = { ++ .offsets = spacemit_gpio_k3_offsets, ++ .bank_offsets = { 0x0, 0x40, 0x80, 0x100 }, ++}; ++ + static const struct of_device_id spacemit_gpio_dt_ids[] = { +- { .compatible = "spacemit,k1-gpio" }, ++ { .compatible = "spacemit,k1-gpio", .data = &k1_gpio_data }, ++ { .compatible = "spacemit,k3-gpio", .data = &k3_gpio_data }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, spacemit_gpio_dt_ids); +@@ -296,12 +367,12 @@ MODULE_DEVICE_TABLE(of, spacemit_gpio_dt_ids); + static struct platform_driver spacemit_gpio_driver = { + .probe = spacemit_gpio_probe, + .driver = { +- .name = "k1-gpio", ++ .name = "spacemit-gpio", + .of_match_table = spacemit_gpio_dt_ids, + }, + }; + module_platform_driver(spacemit_gpio_driver); + + MODULE_AUTHOR("Yixun Lan "); +-MODULE_DESCRIPTION("GPIO driver for SpacemiT K1 SoC"); ++MODULE_DESCRIPTION("GPIO driver for SpacemiT K1/K3 SoC"); + MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0126-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch b/SPECS/linux-lts/0126-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch deleted file mode 100644 index 9da72b5533..0000000000 --- a/SPECS/linux-lts/0126-UPSTREAM-reset-spacemit-Extract-common-K1-reset-code.patch +++ /dev/null @@ -1,364 +0,0 @@ -From dd53659d917a2ad7245d28a312b4a386f3f4d730 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 20 Jan 2026 19:10:51 +0800 -Subject: [PATCH 126/467] UPSTREAM: reset: spacemit: Extract common K1 reset - code - -Extract the common reset controller code from the K1 driver into -separate reset-spacemit-common.{c,h} files to prepare for additional -SpacemiT SoCs that share the same reset controller architecture. - -The common code includes handlers for reset assert and deassert -operations and probing for auxiliary bus devices. - -Changes during extraction: -- Module ownership: Use dev->driver->owner instead of THIS_MODULE in - spacemit_reset_controller_register() to correctly reference the - calling driver's module. -- Rename spacemit_reset_ids to spacemit_k1_reset_ids. -- Define new namespace "RESET_SPACEMIT" for the exported common - functions (spacemit_reset_probe) and update K1 driver to import it. - -This prepares for additional SpacemiT SoCs (K3) that share the same reset -controller architecture. - -Reviewed-by: Alex Elder -Signed-off-by: Guodong Xu -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] -Signed-off-by: Philipp Zabel -(cherry picked from commit aba86f7bff0bfd6956aff9bbbfb0c6ea6d56809e) -Signed-off-by: Han Gao ---- - drivers/reset/spacemit/Kconfig | 17 ++- - drivers/reset/spacemit/Makefile | 2 + - .../reset/spacemit/reset-spacemit-common.c | 77 +++++++++++++ - .../reset/spacemit/reset-spacemit-common.h | 42 +++++++ - drivers/reset/spacemit/reset-spacemit-k1.c | 107 ++---------------- - 5 files changed, 144 insertions(+), 101 deletions(-) - create mode 100644 drivers/reset/spacemit/reset-spacemit-common.c - create mode 100644 drivers/reset/spacemit/reset-spacemit-common.h - -diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig -index 552884e8b72a..56a4858b30e1 100644 ---- a/drivers/reset/spacemit/Kconfig -+++ b/drivers/reset/spacemit/Kconfig -@@ -1,10 +1,20 @@ - # SPDX-License-Identifier: GPL-2.0-only - --config RESET_SPACEMIT_K1 -- tristate "SpacemiT K1 reset driver" -+menu "Reset support for SpacemiT platforms" - depends on ARCH_SPACEMIT || COMPILE_TEST -- depends on SPACEMIT_K1_CCU -+ -+config RESET_SPACEMIT_COMMON -+ tristate - select AUXILIARY_BUS -+ help -+ Common reset controller infrastructure for SpacemiT SoCs. -+ This provides shared code and helper functions used by -+ reset drivers for various SpacemiT SoC families. -+ -+config RESET_SPACEMIT_K1 -+ tristate "Support for SpacemiT K1 SoC" -+ depends on SPACEMIT_K1_CCU -+ select RESET_SPACEMIT_COMMON - default SPACEMIT_K1_CCU - help - Support for reset controller in SpacemiT K1 SoC. -@@ -12,3 +22,4 @@ config RESET_SPACEMIT_K1 - unit (CCU) driver to provide reset control functionality - for various peripherals and subsystems in the SoC. - -+endmenu -diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile -index 34e3350136bb..0b056e8661ec 100644 ---- a/drivers/reset/spacemit/Makefile -+++ b/drivers/reset/spacemit/Makefile -@@ -1,2 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_RESET_SPACEMIT_COMMON) += reset-spacemit-common.o -+ - obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o -diff --git a/drivers/reset/spacemit/reset-spacemit-common.c b/drivers/reset/spacemit/reset-spacemit-common.c -new file mode 100644 -index 000000000000..0626633a5e7d ---- /dev/null -+++ b/drivers/reset/spacemit/reset-spacemit-common.c -@@ -0,0 +1,77 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+/* SpacemiT reset controller driver - common implementation */ -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "reset-spacemit-common.h" -+ -+static int spacemit_reset_update(struct reset_controller_dev *rcdev, -+ unsigned long id, bool assert) -+{ -+ struct ccu_reset_controller *controller; -+ const struct ccu_reset_data *data; -+ u32 mask; -+ u32 val; -+ -+ controller = container_of(rcdev, struct ccu_reset_controller, rcdev); -+ data = &controller->data->reset_data[id]; -+ mask = data->assert_mask | data->deassert_mask; -+ val = assert ? data->assert_mask : data->deassert_mask; -+ -+ return regmap_update_bits(controller->regmap, data->offset, mask, val); -+} -+ -+static int spacemit_reset_assert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ return spacemit_reset_update(rcdev, id, true); -+} -+ -+static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, -+ unsigned long id) -+{ -+ return spacemit_reset_update(rcdev, id, false); -+} -+ -+static const struct reset_control_ops spacemit_reset_control_ops = { -+ .assert = spacemit_reset_assert, -+ .deassert = spacemit_reset_deassert, -+}; -+ -+static int spacemit_reset_controller_register(struct device *dev, -+ struct ccu_reset_controller *controller) -+{ -+ struct reset_controller_dev *rcdev = &controller->rcdev; -+ -+ rcdev->ops = &spacemit_reset_control_ops; -+ rcdev->owner = dev->driver->owner; -+ rcdev->of_node = dev->of_node; -+ rcdev->nr_resets = controller->data->count; -+ -+ return devm_reset_controller_register(dev, &controller->rcdev); -+} -+ -+int spacemit_reset_probe(struct auxiliary_device *adev, -+ const struct auxiliary_device_id *id) -+{ -+ struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev); -+ struct ccu_reset_controller *controller; -+ struct device *dev = &adev->dev; -+ -+ controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); -+ if (!controller) -+ return -ENOMEM; -+ controller->data = (const struct ccu_reset_controller_data *)id->driver_data; -+ controller->regmap = rdev->regmap; -+ -+ return spacemit_reset_controller_register(dev, controller); -+} -+EXPORT_SYMBOL_NS_GPL(spacemit_reset_probe, "RESET_SPACEMIT"); -+ -+MODULE_DESCRIPTION("SpacemiT reset controller driver - common code"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/reset/spacemit/reset-spacemit-common.h b/drivers/reset/spacemit/reset-spacemit-common.h -new file mode 100644 -index 000000000000..ffaf2f86eb39 ---- /dev/null -+++ b/drivers/reset/spacemit/reset-spacemit-common.h -@@ -0,0 +1,42 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * SpacemiT reset controller driver - common definitions -+ */ -+ -+#ifndef _RESET_SPACEMIT_COMMON_H_ -+#define _RESET_SPACEMIT_COMMON_H_ -+ -+#include -+#include -+#include -+#include -+ -+struct ccu_reset_data { -+ u32 offset; -+ u32 assert_mask; -+ u32 deassert_mask; -+}; -+ -+struct ccu_reset_controller_data { -+ const struct ccu_reset_data *reset_data; /* array */ -+ size_t count; -+}; -+ -+struct ccu_reset_controller { -+ struct reset_controller_dev rcdev; -+ const struct ccu_reset_controller_data *data; -+ struct regmap *regmap; -+}; -+ -+#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ -+ { \ -+ .offset = (_offset), \ -+ .assert_mask = (_assert_mask), \ -+ .deassert_mask = (_deassert_mask), \ -+ } -+ -+/* Common probe function */ -+int spacemit_reset_probe(struct auxiliary_device *adev, -+ const struct auxiliary_device_id *id); -+ -+#endif /* _RESET_SPACEMIT_COMMON_H_ */ -diff --git a/drivers/reset/spacemit/reset-spacemit-k1.c b/drivers/reset/spacemit/reset-spacemit-k1.c -index cc7fd1f8750d..8f3b5329ea5f 100644 ---- a/drivers/reset/spacemit/reset-spacemit-k1.c -+++ b/drivers/reset/spacemit/reset-spacemit-k1.c -@@ -1,41 +1,13 @@ - // SPDX-License-Identifier: GPL-2.0-only - --/* SpacemiT reset controller driver */ -+/* SpacemiT K1 reset controller driver */ - --#include --#include --#include - #include --#include --#include --#include - --#include - #include -+#include - --struct ccu_reset_data { -- u32 offset; -- u32 assert_mask; -- u32 deassert_mask; --}; -- --struct ccu_reset_controller_data { -- const struct ccu_reset_data *reset_data; /* array */ -- size_t count; --}; -- --struct ccu_reset_controller { -- struct reset_controller_dev rcdev; -- const struct ccu_reset_controller_data *data; -- struct regmap *regmap; --}; -- --#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ -- { \ -- .offset = (_offset), \ -- .assert_mask = (_assert_mask), \ -- .deassert_mask = (_deassert_mask), \ -- } -+#include "reset-spacemit-common.h" - - static const struct ccu_reset_data k1_mpmu_resets[] = { - [RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), -@@ -214,91 +186,30 @@ static const struct ccu_reset_controller_data k1_apbc2_reset_data = { - .count = ARRAY_SIZE(k1_apbc2_resets), - }; - --static int spacemit_reset_update(struct reset_controller_dev *rcdev, -- unsigned long id, bool assert) --{ -- struct ccu_reset_controller *controller; -- const struct ccu_reset_data *data; -- u32 mask; -- u32 val; -- -- controller = container_of(rcdev, struct ccu_reset_controller, rcdev); -- data = &controller->data->reset_data[id]; -- mask = data->assert_mask | data->deassert_mask; -- val = assert ? data->assert_mask : data->deassert_mask; -- -- return regmap_update_bits(controller->regmap, data->offset, mask, val); --} -- --static int spacemit_reset_assert(struct reset_controller_dev *rcdev, -- unsigned long id) --{ -- return spacemit_reset_update(rcdev, id, true); --} -- --static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, -- unsigned long id) --{ -- return spacemit_reset_update(rcdev, id, false); --} -- --static const struct reset_control_ops spacemit_reset_control_ops = { -- .assert = spacemit_reset_assert, -- .deassert = spacemit_reset_deassert, --}; -- --static int spacemit_reset_controller_register(struct device *dev, -- struct ccu_reset_controller *controller) --{ -- struct reset_controller_dev *rcdev = &controller->rcdev; -- -- rcdev->ops = &spacemit_reset_control_ops; -- rcdev->owner = THIS_MODULE; -- rcdev->of_node = dev->of_node; -- rcdev->nr_resets = controller->data->count; -- -- return devm_reset_controller_register(dev, &controller->rcdev); --} -- --static int spacemit_reset_probe(struct auxiliary_device *adev, -- const struct auxiliary_device_id *id) --{ -- struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev); -- struct ccu_reset_controller *controller; -- struct device *dev = &adev->dev; -- -- controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); -- if (!controller) -- return -ENOMEM; -- controller->data = (const struct ccu_reset_controller_data *)id->driver_data; -- controller->regmap = rdev->regmap; -- -- return spacemit_reset_controller_register(dev, controller); --} -- - #define K1_AUX_DEV_ID(_unit) \ - { \ - .name = "spacemit_ccu.k1-" #_unit "-reset", \ - .driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ - } - --static const struct auxiliary_device_id spacemit_reset_ids[] = { -+static const struct auxiliary_device_id spacemit_k1_reset_ids[] = { - K1_AUX_DEV_ID(mpmu), - K1_AUX_DEV_ID(apbc), - K1_AUX_DEV_ID(apmu), - K1_AUX_DEV_ID(rcpu), - K1_AUX_DEV_ID(rcpu2), - K1_AUX_DEV_ID(apbc2), -- { }, -+ { /* sentinel */ } - }; --MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids); -+MODULE_DEVICE_TABLE(auxiliary, spacemit_k1_reset_ids); - - static struct auxiliary_driver spacemit_k1_reset_driver = { - .probe = spacemit_reset_probe, -- .id_table = spacemit_reset_ids, -+ .id_table = spacemit_k1_reset_ids, - }; - module_auxiliary_driver(spacemit_k1_reset_driver); - -+MODULE_IMPORT_NS("RESET_SPACEMIT"); - MODULE_AUTHOR("Alex Elder "); --MODULE_DESCRIPTION("SpacemiT reset controller driver"); -+MODULE_DESCRIPTION("SpacemiT K1 reset controller driver"); - MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0127-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch b/SPECS/linux-lts/0127-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch deleted file mode 100644 index 437a1f8811..0000000000 --- a/SPECS/linux-lts/0127-UPSTREAM-reset-spacemit-Add-SpacemiT-K3-reset-driver.patch +++ /dev/null @@ -1,300 +0,0 @@ -From fd89e8eec8bc5d871ccade81be1d4cd0d0b54ae1 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 20 Jan 2026 19:10:52 +0800 -Subject: [PATCH 127/467] UPSTREAM: reset: spacemit: Add SpacemiT K3 reset - driver - -Add support for the SpacemiT K3 SoC reset controller. The K3 reset -driver reuses the common reset controller code and provides K3-specific -reset data for devices managed by the following units: - - - MPMU (Main Power Management Unit) - - APBC (APB clock unit) - - APMU (Application Subsystem Power Management Unit) - - DCIU (DMA Control and Interface Unit) - -Acked-by: Alex Elder -Signed-off-by: Guodong Xu -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/spacemit/20260114092742-GYC7933267@gentoo.org/ [1] -Signed-off-by: Philipp Zabel -(cherry picked from commit 938ce3b16582657e67f3bd8a7efa59089c467c90) -Signed-off-by: Han Gao ---- - drivers/reset/spacemit/Kconfig | 11 + - drivers/reset/spacemit/Makefile | 1 + - drivers/reset/spacemit/reset-spacemit-k3.c | 233 +++++++++++++++++++++ - 3 files changed, 245 insertions(+) - create mode 100644 drivers/reset/spacemit/reset-spacemit-k3.c - -diff --git a/drivers/reset/spacemit/Kconfig b/drivers/reset/spacemit/Kconfig -index 56a4858b30e1..545d6b41c6ca 100644 ---- a/drivers/reset/spacemit/Kconfig -+++ b/drivers/reset/spacemit/Kconfig -@@ -22,4 +22,15 @@ config RESET_SPACEMIT_K1 - unit (CCU) driver to provide reset control functionality - for various peripherals and subsystems in the SoC. - -+config RESET_SPACEMIT_K3 -+ tristate "Support for SpacemiT K3 SoC" -+ depends on SPACEMIT_K3_CCU -+ select RESET_SPACEMIT_COMMON -+ default SPACEMIT_K3_CCU -+ help -+ Support for reset controller in SpacemiT K3 SoC. -+ This driver works with the SpacemiT K3 clock controller -+ unit (CCU) driver to provide reset control functionality -+ for various peripherals and subsystems in the SoC. -+ - endmenu -diff --git a/drivers/reset/spacemit/Makefile b/drivers/reset/spacemit/Makefile -index 0b056e8661ec..00669132c6ac 100644 ---- a/drivers/reset/spacemit/Makefile -+++ b/drivers/reset/spacemit/Makefile -@@ -2,3 +2,4 @@ - obj-$(CONFIG_RESET_SPACEMIT_COMMON) += reset-spacemit-common.o - - obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o -+obj-$(CONFIG_RESET_SPACEMIT_K3) += reset-spacemit-k3.o -diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c -new file mode 100644 -index 000000000000..e9e32e4c1ba5 ---- /dev/null -+++ b/drivers/reset/spacemit/reset-spacemit-k3.c -@@ -0,0 +1,233 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+/* SpacemiT K3 reset controller driver */ -+ -+#include -+ -+#include -+#include -+ -+#include "reset-spacemit-common.h" -+ -+static const struct ccu_reset_data k3_mpmu_resets[] = { -+ [RESET_MPMU_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), -+ [RESET_MPMU_RIPC] = RESET_DATA(MPMU_RIPCCR, BIT(2), 0), -+}; -+ -+static const struct ccu_reset_controller_data k3_mpmu_reset_data = { -+ .reset_data = k3_mpmu_resets, -+ .count = ARRAY_SIZE(k3_mpmu_resets), -+}; -+ -+static const struct ccu_reset_data k3_apbc_resets[] = { -+ [RESET_APBC_UART0] = RESET_DATA(APBC_UART0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), -+ [RESET_APBC_UART10] = RESET_DATA(APBC_UART10_CLK_RST, BIT(2), 0), -+ [RESET_APBC_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), 0), -+ [RESET_APBC_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), 0), -+ [RESET_APBC_SPI0] = RESET_DATA(APBC_SSP0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_SPI1] = RESET_DATA(APBC_SSP1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_SPI3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), -+ [RESET_APBC_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS0] = RESET_DATA(APBC_TIMERS0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS3] = RESET_DATA(APBC_TIMERS3_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS4] = RESET_DATA(APBC_TIMERS4_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS5] = RESET_DATA(APBC_TIMERS5_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS6] = RESET_DATA(APBC_TIMERS6_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TIMERS7] = RESET_DATA(APBC_TIMERS7_CLK_RST, BIT(2), 0), -+ [RESET_APBC_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), -+ [RESET_APBC_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), -+ [RESET_APBC_I2S0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_I2S1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_I2S2] = RESET_DATA(APBC_SSPA2_CLK_RST, BIT(2), 0), -+ [RESET_APBC_I2S3] = RESET_DATA(APBC_SSPA3_CLK_RST, BIT(2), 0), -+ [RESET_APBC_I2S4] = RESET_DATA(APBC_SSPA4_CLK_RST, BIT(2), 0), -+ [RESET_APBC_I2S5] = RESET_DATA(APBC_SSPA5_CLK_RST, BIT(2), 0), -+ [RESET_APBC_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), -+ [RESET_APBC_IR0] = RESET_DATA(APBC_IR0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_IR1] = RESET_DATA(APBC_IR1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), -+ [RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), -+ [RESET_APBC_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), -+ [RESET_APBC_CAN1] = RESET_DATA(APBC_CAN1_CLK_RST, BIT(2), 0), -+ [RESET_APBC_CAN2] = RESET_DATA(APBC_CAN2_CLK_RST, BIT(2), 0), -+ [RESET_APBC_CAN3] = RESET_DATA(APBC_CAN3_CLK_RST, BIT(2), 0), -+ [RESET_APBC_CAN4] = RESET_DATA(APBC_CAN4_CLK_RST, BIT(2), 0), -+}; -+ -+static const struct ccu_reset_controller_data k3_apbc_reset_data = { -+ .reset_data = k3_apbc_resets, -+ .count = ARRAY_SIZE(k3_apbc_resets), -+}; -+ -+static const struct ccu_reset_data k3_apmu_resets[] = { -+ [RESET_APMU_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), -+ [RESET_APMU_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), -+ [RESET_APMU_ISP_CIBUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), -+ [RESET_APMU_DSI_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), -+ [RESET_APMU_LCD] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), -+ [RESET_APMU_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), -+ [RESET_APMU_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), -+ [RESET_APMU_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(15)), -+ [RESET_APMU_SC2_HCLK] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), -+ [RESET_APMU_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -+ BIT(1)|BIT(2)|BIT(3)), -+ [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -+ BIT(5)|BIT(6)|BIT(7)), -+ [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -+ BIT(9)|BIT(10)|BIT(11)), -+ [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -+ BIT(13)|BIT(14)|BIT(15)), -+ [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -+ BIT(17)|BIT(18)|BIT(19)), -+ [RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_AES_WTM] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), -+ [RESET_APMU_MCB_DCLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_MCB_ACLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_DTC] = RESET_DATA(APMU_DTC_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), -+ [RESET_APMU_CPU0_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(0), 0), -+ [RESET_APMU_CPU0_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(1), 0), -+ [RESET_APMU_CPU1_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(3), 0), -+ [RESET_APMU_CPU1_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(4), 0), -+ [RESET_APMU_CPU2_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(6), 0), -+ [RESET_APMU_CPU2_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(7), 0), -+ [RESET_APMU_CPU3_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(9), 0), -+ [RESET_APMU_CPU3_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(10), 0), -+ [RESET_APMU_C0_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(12), 0), -+ [RESET_APMU_CPU4_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(16), 0), -+ [RESET_APMU_CPU4_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(17), 0), -+ [RESET_APMU_CPU5_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(19), 0), -+ [RESET_APMU_CPU5_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(20), 0), -+ [RESET_APMU_CPU6_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(22), 0), -+ [RESET_APMU_CPU6_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(23), 0), -+ [RESET_APMU_CPU7_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(25), 0), -+ [RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), -+ [RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), -+ [RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), -+ [RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL, -+ BIT(1) | BIT(2) | BIT(3), 0), -+ [RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, -+ BIT(3) | BIT(2) | BIT(0)), -+ [RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)), -+ [RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)), -+ [RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)), -+ [RESET_APMU_DSI4LN2_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(15)), -+ [RESET_APMU_DSI4LN2_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(0)), -+ [RESET_APMU_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(15)), -+ [RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), -+ [RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), -+ [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, -+ BIT(5) | BIT(4) | BIT(3)), -+ [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, -+ BIT(5) | BIT(4) | BIT(3)), -+ [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, -+ BIT(5) | BIT(4) | BIT(3)), -+ [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, -+ BIT(5) | BIT(4) | BIT(3)), -+ [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, -+ BIT(5) | BIT(4) | BIT(3)), -+ [RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_ESPI_MCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_ESPI_SCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(2)), -+}; -+ -+static const struct ccu_reset_controller_data k3_apmu_reset_data = { -+ .reset_data = k3_apmu_resets, -+ .count = ARRAY_SIZE(k3_apmu_resets), -+}; -+ -+static const struct ccu_reset_data k3_dciu_resets[] = { -+ [RESET_DCIU_HDMA] = RESET_DATA(DCIU_DMASYS_RSTN, 0, BIT(0)), -+ [RESET_DCIU_DMA350] = RESET_DATA(DCIU_DMASYS_SDMA_RSTN, 0, BIT(0)), -+ [RESET_DCIU_DMA350_0] = RESET_DATA(DCIU_DMASYS_S0_RSTN, 0, BIT(0)), -+ [RESET_DCIU_DMA350_1] = RESET_DATA(DCIU_DMASYS_S1_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA0] = RESET_DATA(DCIU_DMASYS_A0_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA1] = RESET_DATA(DCIU_DMASYS_A1_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA2] = RESET_DATA(DCIU_DMASYS_A2_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA3] = RESET_DATA(DCIU_DMASYS_A3_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA4] = RESET_DATA(DCIU_DMASYS_A4_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA5] = RESET_DATA(DCIU_DMASYS_A5_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA6] = RESET_DATA(DCIU_DMASYS_A6_RSTN, 0, BIT(0)), -+ [RESET_DCIU_AXIDMA7] = RESET_DATA(DCIU_DMASYS_A7_RSTN, 0, BIT(0)), -+}; -+ -+static const struct ccu_reset_controller_data k3_dciu_reset_data = { -+ .reset_data = k3_dciu_resets, -+ .count = ARRAY_SIZE(k3_dciu_resets), -+}; -+ -+#define K3_AUX_DEV_ID(_unit) \ -+ { \ -+ .name = "spacemit_ccu.k3-" #_unit "-reset", \ -+ .driver_data = (kernel_ulong_t)&k3_ ## _unit ## _reset_data, \ -+ } -+ -+static const struct auxiliary_device_id spacemit_k3_reset_ids[] = { -+ K3_AUX_DEV_ID(mpmu), -+ K3_AUX_DEV_ID(apbc), -+ K3_AUX_DEV_ID(apmu), -+ K3_AUX_DEV_ID(dciu), -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(auxiliary, spacemit_k3_reset_ids); -+ -+static struct auxiliary_driver spacemit_k3_reset_driver = { -+ .probe = spacemit_reset_probe, -+ .id_table = spacemit_k3_reset_ids, -+}; -+module_auxiliary_driver(spacemit_k3_reset_driver); -+ -+MODULE_IMPORT_NS("RESET_SPACEMIT"); -+MODULE_AUTHOR("Guodong Xu "); -+MODULE_DESCRIPTION("SpacemiT K3 reset controller driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch b/SPECS/linux-lts/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch new file mode 100644 index 0000000000..a2882d0c20 --- /dev/null +++ b/SPECS/linux-lts/0127-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch @@ -0,0 +1,64 @@ +From ea85c56c78cbe48a0e645e57bb5d0151fa6f9bfa Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Tue, 20 Jan 2026 18:00:01 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Disable ETH PHY sleep + mode for OrangePi + +On the SpacemiT K1 platform, the MAC can't read statistics when the PHY +clock stops. Disable Link Down Power Saving Mode for the YT8531C PHY on +OrangePi R2S and RV2 boards to avoid reading statistics timeout logs. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260120100001.1285624-2-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit 5164e95565d3fd508ca8a95351323f5716dfb695) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts | 2 ++ + arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 2 ++ + 2 files changed, 4 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index 58098c4a2aab..de75f6aac740 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -52,6 +52,7 @@ mdio-bus { + + rgmii0: phy@1 { + reg = <0x1>; ++ motorcomm,auto-sleep-disabled; + }; + }; + }; +@@ -75,6 +76,7 @@ mdio-bus { + + rgmii1: phy@1 { + reg = <0x1>; ++ motorcomm,auto-sleep-disabled; + }; + }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 41dc8e35e6eb..7b7331cb3c72 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -54,6 +54,7 @@ mdio-bus { + + rgmii0: phy@1 { + reg = <0x1>; ++ motorcomm,auto-sleep-disabled; + }; + }; + }; +@@ -77,6 +78,7 @@ mdio-bus { + + rgmii1: phy@1 { + reg = <0x1>; ++ motorcomm,auto-sleep-disabled; + }; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch b/SPECS/linux-lts/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch new file mode 100644 index 0000000000..412075183b --- /dev/null +++ b/SPECS/linux-lts/0128-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch @@ -0,0 +1,33 @@ +From 8731712faebb3034f523e3ed6e95191f5e47a01b Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:10 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: clock: thead,th1520-clk-ap: Add + ID for C910 bus clock + +Add binding ID for C910 bus clock, which takes CLK_C910 as parent and is +essential for C910 cluster's operation. + +Acked-by: Conor Dooley +Signed-off-by: Yao Zi +Signed-off-by: Drew Fustini +(cherry picked from commit 5f352125f8a0bc906dff8419a2377903012d7f35) +Signed-off-by: Han Gao +--- + include/dt-bindings/clock/thead,th1520-clk-ap.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h +index 09a9aa7b3ab1..68b35cc61204 100644 +--- a/include/dt-bindings/clock/thead,th1520-clk-ap.h ++++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h +@@ -93,6 +93,7 @@ + #define CLK_SRAM3 83 + #define CLK_PLL_GMAC_100M 84 + #define CLK_UART_SCLK 85 ++#define CLK_C910_BUS 86 + + /* VO clocks */ + #define CLK_AXI4_VO_ACLK 0 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0128-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch b/SPECS/linux-lts/0128-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch deleted file mode 100644 index cdf007650e..0000000000 --- a/SPECS/linux-lts/0128-UPSTREAM-dt-bindings-gpio-spacemit-add-compatible-na.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e384f721e2318cd682396313c94562368356bdec Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 6 Jan 2026 11:09:32 +0800 -Subject: [PATCH 128/467] UPSTREAM: dt-bindings: gpio: spacemit: add compatible - name for K3 SoC - -Add new compatible string for SpacemiT K3 SoC's GPIO controller. - -Acked-by: Krzysztof Kozlowski -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260106-02-k3-gpio-v3-1-4800c214810b@gentoo.org -Signed-off-by: Bartosz Golaszewski -(cherry picked from commit 48033e4c677be4e3f131df454d44a5d1fb1b334f) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml -index 83e0b2d14c9f..24d22d95665f 100644 ---- a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml -+++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml -@@ -19,7 +19,9 @@ properties: - pattern: "^gpio@[0-9a-f]+$" - - compatible: -- const: spacemit,k1-gpio -+ enum: -+ - spacemit,k1-gpio -+ - spacemit,k3-gpio - - reg: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch b/SPECS/linux-lts/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch new file mode 100644 index 0000000000..e28d1d6f4f --- /dev/null +++ b/SPECS/linux-lts/0129-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch @@ -0,0 +1,62 @@ +From 43765d604a0ac503f549b2772fc89a67b6df8779 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:12 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Add C910 bus clock + +This divider takes c910_clk as parent and is essential for the C910 +cluster to operate, thus is marked as CLK_IS_CRITICAL. + +Reviewed-by: Drew Fustini +Signed-off-by: Yao Zi +Signed-off-by: Drew Fustini +(cherry picked from commit b436f8a82aaa3bd54cb79b1219d94a99f7351d33) +Signed-off-by: Han Gao +--- + drivers/clk/thead/clk-th1520-ap.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c +index d870f0c665f8..b820d47387bb 100644 +--- a/drivers/clk/thead/clk-th1520-ap.c ++++ b/drivers/clk/thead/clk-th1520-ap.c +@@ -539,6 +539,20 @@ static struct ccu_mux c910_clk = { + .mux = TH_CCU_MUX("c910", c910_parents, 0, 1), + }; + ++static struct ccu_div c910_bus_clk = { ++ .enable = BIT(7), ++ .div_en = BIT(11), ++ .div = TH_CCU_DIV_FLAGS(8, 3, 0), ++ .common = { ++ .clkid = CLK_C910_BUS, ++ .cfg0 = 0x100, ++ .hw.init = CLK_HW_INIT_HW("c910-bus", ++ &c910_clk.mux.hw, ++ &ccu_div_ops, ++ CLK_IS_CRITICAL), ++ }, ++}; ++ + static const struct clk_parent_data ahb2_cpusys_parents[] = { + { .hw = &gmac_pll_clk.common.hw }, + { .index = 0 } +@@ -1051,6 +1065,7 @@ static struct ccu_common *th1520_pll_clks[] = { + }; + + static struct ccu_common *th1520_div_clks[] = { ++ &c910_bus_clk.common, + &ahb2_cpusys_hclk.common, + &apb3_cpusys_pclk.common, + &axi4_cpusys2_aclk.common, +@@ -1194,7 +1209,7 @@ static const struct th1520_plat_data th1520_ap_platdata = { + .th1520_mux_clks = th1520_mux_clks, + .th1520_gate_clks = th1520_gate_clks, + +- .nr_clks = CLK_UART_SCLK + 1, ++ .nr_clks = CLK_C910_BUS + 1, + + .nr_pll_clks = ARRAY_SIZE(th1520_pll_clks), + .nr_div_clks = ARRAY_SIZE(th1520_div_clks), +-- +2.53.0 + diff --git a/SPECS/linux-lts/0129-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch b/SPECS/linux-lts/0129-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch deleted file mode 100644 index 8f4194d8bf..0000000000 --- a/SPECS/linux-lts/0129-UPSTREAM-gpio-spacemit-Add-GPIO-support-for-K3-SoC.patch +++ /dev/null @@ -1,316 +0,0 @@ -From a0fdf97c15b11ba0954d550993bad54d718c63e2 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 6 Jan 2026 11:09:33 +0800 -Subject: [PATCH 129/467] UPSTREAM: gpio: spacemit: Add GPIO support for K3 SoC - -SpacemiT K3 SoC has changed gpio register layout while comparing -with previous generation, the register offset and bank offset -need to be adjusted, introduce a compatible data to extend the -driver to support this. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260106-02-k3-gpio-v3-2-4800c214810b@gentoo.org -Signed-off-by: Bartosz Golaszewski -(cherry picked from commit da64eb51595bc6073b2fb69c2a3859bba93ed75a) -Signed-off-by: Han Gao ---- - drivers/gpio/gpio-spacemit-k1.c | 163 +++++++++++++++++++++++--------- - 1 file changed, 117 insertions(+), 46 deletions(-) - -diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c -index eb66a15c002f..8f570a1a4894 100644 ---- a/drivers/gpio/gpio-spacemit-k1.c -+++ b/drivers/gpio/gpio-spacemit-k1.c -@@ -15,29 +15,37 @@ - #include - #include - --/* register offset */ --#define SPACEMIT_GPLR 0x00 /* port level - R */ --#define SPACEMIT_GPDR 0x0c /* port direction - R/W */ --#define SPACEMIT_GPSR 0x18 /* port set - W */ --#define SPACEMIT_GPCR 0x24 /* port clear - W */ --#define SPACEMIT_GRER 0x30 /* port rising edge R/W */ --#define SPACEMIT_GFER 0x3c /* port falling edge R/W */ --#define SPACEMIT_GEDR 0x48 /* edge detect status - R/W1C */ --#define SPACEMIT_GSDR 0x54 /* (set) direction - W */ --#define SPACEMIT_GCDR 0x60 /* (clear) direction - W */ --#define SPACEMIT_GSRER 0x6c /* (set) rising edge detect enable - W */ --#define SPACEMIT_GCRER 0x78 /* (clear) rising edge detect enable - W */ --#define SPACEMIT_GSFER 0x84 /* (set) falling edge detect enable - W */ --#define SPACEMIT_GCFER 0x90 /* (clear) falling edge detect enable - W */ --#define SPACEMIT_GAPMASK 0x9c /* interrupt mask , 0 disable, 1 enable - R/W */ -- - #define SPACEMIT_NR_BANKS 4 - #define SPACEMIT_NR_GPIOS_PER_BANK 32 - - #define to_spacemit_gpio_bank(x) container_of((x), struct spacemit_gpio_bank, gc) -+#define to_spacemit_gpio_regs(gb) ((gb)->sg->data->offsets) -+ -+enum spacemit_gpio_registers { -+ SPACEMIT_GPLR, /* port level - R */ -+ SPACEMIT_GPDR, /* port direction - R/W */ -+ SPACEMIT_GPSR, /* port set - W */ -+ SPACEMIT_GPCR, /* port clear - W */ -+ SPACEMIT_GRER, /* port rising edge R/W */ -+ SPACEMIT_GFER, /* port falling edge R/W */ -+ SPACEMIT_GEDR, /* edge detect status - R/W1C */ -+ SPACEMIT_GSDR, /* (set) direction - W */ -+ SPACEMIT_GCDR, /* (clear) direction - W */ -+ SPACEMIT_GSRER, /* (set) rising edge detect enable - W */ -+ SPACEMIT_GCRER, /* (clear) rising edge detect enable - W */ -+ SPACEMIT_GSFER, /* (set) falling edge detect enable - W */ -+ SPACEMIT_GCFER, /* (clear) falling edge detect enable - W */ -+ SPACEMIT_GAPMASK, /* interrupt mask , 0 disable, 1 enable - R/W */ -+ SPACEMIT_GCPMASK, /* interrupt mask for K3 */ -+}; - - struct spacemit_gpio; - -+struct spacemit_gpio_data { -+ const unsigned int *offsets; -+ u32 bank_offsets[SPACEMIT_NR_BANKS]; -+}; -+ - struct spacemit_gpio_bank { - struct gpio_generic_chip chip; - struct spacemit_gpio *sg; -@@ -49,9 +57,22 @@ struct spacemit_gpio_bank { - - struct spacemit_gpio { - struct device *dev; -+ const struct spacemit_gpio_data *data; - struct spacemit_gpio_bank sgb[SPACEMIT_NR_BANKS]; - }; - -+static u32 spacemit_gpio_read(struct spacemit_gpio_bank *gb, -+ enum spacemit_gpio_registers reg) -+{ -+ return readl(gb->base + to_spacemit_gpio_regs(gb)[reg]); -+} -+ -+static void spacemit_gpio_write(struct spacemit_gpio_bank *gb, -+ enum spacemit_gpio_registers reg, u32 val) -+{ -+ writel(val, gb->base + to_spacemit_gpio_regs(gb)[reg]); -+} -+ - static u32 spacemit_gpio_bank_index(struct spacemit_gpio_bank *gb) - { - return (u32)(gb - gb->sg->sgb); -@@ -63,10 +84,10 @@ static irqreturn_t spacemit_gpio_irq_handler(int irq, void *dev_id) - unsigned long pending; - u32 n, gedr; - -- gedr = readl(gb->base + SPACEMIT_GEDR); -+ gedr = spacemit_gpio_read(gb, SPACEMIT_GEDR); - if (!gedr) - return IRQ_NONE; -- writel(gedr, gb->base + SPACEMIT_GEDR); -+ spacemit_gpio_write(gb, SPACEMIT_GEDR, gedr); - - pending = gedr & gb->irq_mask; - if (!pending) -@@ -82,7 +103,7 @@ static void spacemit_gpio_irq_ack(struct irq_data *d) - { - struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d); - -- writel(BIT(irqd_to_hwirq(d)), gb->base + SPACEMIT_GEDR); -+ spacemit_gpio_write(gb, SPACEMIT_GEDR, BIT(irqd_to_hwirq(d))); - } - - static void spacemit_gpio_irq_mask(struct irq_data *d) -@@ -91,13 +112,13 @@ static void spacemit_gpio_irq_mask(struct irq_data *d) - u32 bit = BIT(irqd_to_hwirq(d)); - - gb->irq_mask &= ~bit; -- writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK); -+ spacemit_gpio_write(gb, SPACEMIT_GAPMASK, gb->irq_mask); - - if (bit & gb->irq_rising_edge) -- writel(bit, gb->base + SPACEMIT_GCRER); -+ spacemit_gpio_write(gb, SPACEMIT_GCRER, bit); - - if (bit & gb->irq_falling_edge) -- writel(bit, gb->base + SPACEMIT_GCFER); -+ spacemit_gpio_write(gb, SPACEMIT_GCFER, bit); - } - - static void spacemit_gpio_irq_unmask(struct irq_data *d) -@@ -108,12 +129,12 @@ static void spacemit_gpio_irq_unmask(struct irq_data *d) - gb->irq_mask |= bit; - - if (bit & gb->irq_rising_edge) -- writel(bit, gb->base + SPACEMIT_GSRER); -+ spacemit_gpio_write(gb, SPACEMIT_GSRER, bit); - - if (bit & gb->irq_falling_edge) -- writel(bit, gb->base + SPACEMIT_GSFER); -+ spacemit_gpio_write(gb, SPACEMIT_GSFER, bit); - -- writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK); -+ spacemit_gpio_write(gb, SPACEMIT_GAPMASK, gb->irq_mask); - } - - static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int type) -@@ -123,18 +144,18 @@ static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int type) - - if (type & IRQ_TYPE_EDGE_RISING) { - gb->irq_rising_edge |= bit; -- writel(bit, gb->base + SPACEMIT_GSRER); -+ spacemit_gpio_write(gb, SPACEMIT_GSRER, bit); - } else { - gb->irq_rising_edge &= ~bit; -- writel(bit, gb->base + SPACEMIT_GCRER); -+ spacemit_gpio_write(gb, SPACEMIT_GCRER, bit); - } - - if (type & IRQ_TYPE_EDGE_FALLING) { - gb->irq_falling_edge |= bit; -- writel(bit, gb->base + SPACEMIT_GSFER); -+ spacemit_gpio_write(gb, SPACEMIT_GSFER, bit); - } else { - gb->irq_falling_edge &= ~bit; -- writel(bit, gb->base + SPACEMIT_GCFER); -+ spacemit_gpio_write(gb, SPACEMIT_GCFER, bit); - } - - return 0; -@@ -179,15 +200,16 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - struct device *dev = sg->dev; - struct gpio_irq_chip *girq; - void __iomem *dat, *set, *clr, *dirin, *dirout; -- int ret, bank_base[] = { 0x0, 0x4, 0x8, 0x100 }; -+ int ret; - -- gb->base = regs + bank_base[index]; -+ gb->base = regs + sg->data->bank_offsets[index]; -+ gb->sg = sg; - -- dat = gb->base + SPACEMIT_GPLR; -- set = gb->base + SPACEMIT_GPSR; -- clr = gb->base + SPACEMIT_GPCR; -- dirin = gb->base + SPACEMIT_GCDR; -- dirout = gb->base + SPACEMIT_GSDR; -+ dat = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPLR]; -+ set = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPSR]; -+ clr = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPCR]; -+ dirin = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GCDR]; -+ dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GSDR]; - - config = (struct gpio_generic_chip_config) { - .dev = dev, -@@ -206,8 +228,6 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - if (ret) - return dev_err_probe(dev, ret, "failed to init gpio chip\n"); - -- gb->sg = sg; -- - gc->label = dev_name(dev); - gc->request = gpiochip_generic_request; - gc->free = gpiochip_generic_free; -@@ -223,13 +243,13 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - gpio_irq_chip_set_chip(girq, &spacemit_gpio_chip); - - /* Disable Interrupt */ -- writel(0, gb->base + SPACEMIT_GAPMASK); -+ spacemit_gpio_write(gb, SPACEMIT_GAPMASK, 0); - /* Disable Edge Detection Settings */ -- writel(0x0, gb->base + SPACEMIT_GRER); -- writel(0x0, gb->base + SPACEMIT_GFER); -+ spacemit_gpio_write(gb, SPACEMIT_GRER, 0x0); -+ spacemit_gpio_write(gb, SPACEMIT_GFER, 0x0); - /* Clear Interrupt */ -- writel(0xffffffff, gb->base + SPACEMIT_GCRER); -- writel(0xffffffff, gb->base + SPACEMIT_GCFER); -+ spacemit_gpio_write(gb, SPACEMIT_GCRER, 0xffffffff); -+ spacemit_gpio_write(gb, SPACEMIT_GCFER, 0xffffffff); - - ret = devm_request_threaded_irq(dev, irq, NULL, - spacemit_gpio_irq_handler, -@@ -260,6 +280,10 @@ static int spacemit_gpio_probe(struct platform_device *pdev) - if (!sg) - return -ENOMEM; - -+ sg->data = of_device_get_match_data(dev); -+ if (!sg->data) -+ return dev_err_probe(dev, -EINVAL, "No available compatible data."); -+ - regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); -@@ -287,8 +311,55 @@ static int spacemit_gpio_probe(struct platform_device *pdev) - return 0; - } - -+static const unsigned int spacemit_gpio_k1_offsets[] = { -+ [SPACEMIT_GPLR] = 0x00, -+ [SPACEMIT_GPDR] = 0x0c, -+ [SPACEMIT_GPSR] = 0x18, -+ [SPACEMIT_GPCR] = 0x24, -+ [SPACEMIT_GRER] = 0x30, -+ [SPACEMIT_GFER] = 0x3c, -+ [SPACEMIT_GEDR] = 0x48, -+ [SPACEMIT_GSDR] = 0x54, -+ [SPACEMIT_GCDR] = 0x60, -+ [SPACEMIT_GSRER] = 0x6c, -+ [SPACEMIT_GCRER] = 0x78, -+ [SPACEMIT_GSFER] = 0x84, -+ [SPACEMIT_GCFER] = 0x90, -+ [SPACEMIT_GAPMASK] = 0x9c, -+ [SPACEMIT_GCPMASK] = 0xA8, -+}; -+ -+static const unsigned int spacemit_gpio_k3_offsets[] = { -+ [SPACEMIT_GPLR] = 0x0, -+ [SPACEMIT_GPDR] = 0x4, -+ [SPACEMIT_GPSR] = 0x8, -+ [SPACEMIT_GPCR] = 0xc, -+ [SPACEMIT_GRER] = 0x10, -+ [SPACEMIT_GFER] = 0x14, -+ [SPACEMIT_GEDR] = 0x18, -+ [SPACEMIT_GSDR] = 0x1c, -+ [SPACEMIT_GCDR] = 0x20, -+ [SPACEMIT_GSRER] = 0x24, -+ [SPACEMIT_GCRER] = 0x28, -+ [SPACEMIT_GSFER] = 0x2c, -+ [SPACEMIT_GCFER] = 0x30, -+ [SPACEMIT_GAPMASK] = 0x34, -+ [SPACEMIT_GCPMASK] = 0x38, -+}; -+ -+static const struct spacemit_gpio_data k1_gpio_data = { -+ .offsets = spacemit_gpio_k1_offsets, -+ .bank_offsets = { 0x0, 0x4, 0x8, 0x100 }, -+}; -+ -+static const struct spacemit_gpio_data k3_gpio_data = { -+ .offsets = spacemit_gpio_k3_offsets, -+ .bank_offsets = { 0x0, 0x40, 0x80, 0x100 }, -+}; -+ - static const struct of_device_id spacemit_gpio_dt_ids[] = { -- { .compatible = "spacemit,k1-gpio" }, -+ { .compatible = "spacemit,k1-gpio", .data = &k1_gpio_data }, -+ { .compatible = "spacemit,k3-gpio", .data = &k3_gpio_data }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, spacemit_gpio_dt_ids); -@@ -296,12 +367,12 @@ MODULE_DEVICE_TABLE(of, spacemit_gpio_dt_ids); - static struct platform_driver spacemit_gpio_driver = { - .probe = spacemit_gpio_probe, - .driver = { -- .name = "k1-gpio", -+ .name = "spacemit-gpio", - .of_match_table = spacemit_gpio_dt_ids, - }, - }; - module_platform_driver(spacemit_gpio_driver); - - MODULE_AUTHOR("Yixun Lan "); --MODULE_DESCRIPTION("GPIO driver for SpacemiT K1 SoC"); -+MODULE_DESCRIPTION("GPIO driver for SpacemiT K1/K3 SoC"); - MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch b/SPECS/linux-lts/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch new file mode 100644 index 0000000000..0f3eeb5de1 --- /dev/null +++ b/SPECS/linux-lts/0130-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch @@ -0,0 +1,275 @@ +From 00eda1e45b3379884782a9a27d245fcff13f8772 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:13 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Support setting PLL + rates + +TH1520 ships several PLLs that could operate in either integer or +fractional mode. However, the TRM only lists a few configuration whose +stability is considered guaranteed. + +Add a table-lookup rate determination logic to support PLL rate setting, +and fill up frequency-configuration tables for AP-subsystem PLLs. + +Reviewed-by: Drew Fustini +Signed-off-by: Yao Zi +Signed-off-by: Drew Fustini +(cherry picked from commit 238cc6316a885765fd52a6dc65b9ca4e47647b1e) +Signed-off-by: Han Gao +--- + drivers/clk/thead/clk-th1520-ap.c | 142 ++++++++++++++++++++++++++++++ + 1 file changed, 142 insertions(+) + +diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c +index b820d47387bb..bf8e80c39a9e 100644 +--- a/drivers/clk/thead/clk-th1520-ap.c ++++ b/drivers/clk/thead/clk-th1520-ap.c +@@ -22,6 +22,7 @@ + #define TH1520_PLL_REFDIV GENMASK(5, 0) + #define TH1520_PLL_BYPASS BIT(30) + #define TH1520_PLL_VCO_RST BIT(29) ++#define TH1520_PLL_DACPD BIT(25) + #define TH1520_PLL_DSMPD BIT(24) + #define TH1520_PLL_FRAC GENMASK(23, 0) + #define TH1520_PLL_FRAC_BITS 24 +@@ -72,9 +73,19 @@ struct ccu_div { + struct ccu_common common; + }; + ++struct ccu_pll_cfg { ++ unsigned long freq; ++ u32 fbdiv; ++ u32 frac; ++ u32 postdiv1; ++ u32 postdiv2; ++}; ++ + struct ccu_pll { + struct ccu_common common; + u32 lock_sts_mask; ++ int cfgnum; ++ const struct ccu_pll_cfg *cfgs; + }; + + #define TH_CCU_ARG(_shift, _width) \ +@@ -391,17 +402,102 @@ static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw, + return rate; + } + ++static const struct ccu_pll_cfg *ccu_pll_lookup_best_cfg(struct ccu_pll *pll, ++ unsigned long rate) ++{ ++ unsigned long best_delta = ULONG_MAX; ++ const struct ccu_pll_cfg *best_cfg; ++ int i; ++ ++ for (i = 0; i < pll->cfgnum; i++) { ++ const struct ccu_pll_cfg *cfg = &pll->cfgs[i]; ++ unsigned long delta; ++ ++ delta = abs_diff(cfg->freq, rate); ++ if (delta < best_delta) { ++ best_delta = delta; ++ best_cfg = cfg; ++ } ++ } ++ ++ return best_cfg; ++} ++ ++static int ccu_pll_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ ++ req->rate = ccu_pll_lookup_best_cfg(pll, req->rate)->freq; ++ ++ return 0; ++} ++ ++static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct ccu_pll *pll = hw_to_ccu_pll(hw); ++ const struct ccu_pll_cfg *cfg; ++ ++ cfg = ccu_pll_lookup_best_cfg(pll, rate); ++ ++ ccu_pll_disable(hw); ++ ++ regmap_write(pll->common.map, pll->common.cfg0, ++ FIELD_PREP(TH1520_PLL_REFDIV, 1) | ++ FIELD_PREP(TH1520_PLL_FBDIV, cfg->fbdiv) | ++ FIELD_PREP(TH1520_PLL_POSTDIV1, cfg->postdiv1) | ++ FIELD_PREP(TH1520_PLL_POSTDIV2, cfg->postdiv2)); ++ ++ regmap_update_bits(pll->common.map, pll->common.cfg1, ++ TH1520_PLL_DACPD | TH1520_PLL_DSMPD | ++ TH1520_PLL_FRAC, ++ cfg->frac ? cfg->frac : ++ TH1520_PLL_DACPD | TH1520_PLL_DSMPD); ++ ++ return ccu_pll_enable(hw); ++} ++ + static const struct clk_ops clk_pll_ops = { + .disable = ccu_pll_disable, + .enable = ccu_pll_enable, + .is_enabled = ccu_pll_is_enabled, + .recalc_rate = ccu_pll_recalc_rate, ++ .determine_rate = ccu_pll_determine_rate, ++ .set_rate = ccu_pll_set_rate, + }; + + static const struct clk_parent_data osc_24m_clk[] = { + { .index = 0 } + }; + ++static const struct ccu_pll_cfg cpu_pll_cfgs[] = { ++ { 125000000, 125, 0, 6, 4 }, ++ { 200000000, 125, 0, 5, 3 }, ++ { 300000000, 125, 0, 5, 2 }, ++ { 400000000, 100, 0, 3, 2 }, ++ { 500000000, 125, 0, 6, 1 }, ++ { 600000000, 125, 0, 5, 1 }, ++ { 702000000, 117, 0, 4, 1 }, ++ { 800000000, 100, 0, 3, 1 }, ++ { 900000000, 75, 0, 2, 1 }, ++ { 1000000000, 125, 0, 3, 1 }, ++ { 1104000000, 92, 0, 2, 1 }, ++ { 1200000000, 100, 0, 2, 1 }, ++ { 1296000000, 108, 0, 2, 1 }, ++ { 1404000000, 117, 0, 2, 1 }, ++ { 1500000000, 125, 0, 2, 1 }, ++ { 1608000000, 67, 0, 1, 1 }, ++ { 1704000000, 71, 0, 1, 1 }, ++ { 1800000000, 75, 0, 1, 1 }, ++ { 1896000000, 79, 0, 1, 1 }, ++ { 1992000000, 83, 0, 1, 1 }, ++ { 2112000000, 88, 0, 1, 1 }, ++ { 2208000000, 92, 0, 1, 1 }, ++ { 2304000000, 96, 0, 1, 1 }, ++ { 2400000000, 100, 0, 1, 1 }, ++}; ++ + static struct ccu_pll cpu_pll0_clk = { + .common = { + .clkid = CLK_CPU_PLL0, +@@ -413,6 +509,8 @@ static struct ccu_pll cpu_pll0_clk = { + CLK_IS_CRITICAL), + }, + .lock_sts_mask = BIT(1), ++ .cfgnum = ARRAY_SIZE(cpu_pll_cfgs), ++ .cfgs = cpu_pll_cfgs, + }; + + static struct ccu_pll cpu_pll1_clk = { +@@ -426,6 +524,16 @@ static struct ccu_pll cpu_pll1_clk = { + CLK_IS_CRITICAL), + }, + .lock_sts_mask = BIT(4), ++ .cfgnum = ARRAY_SIZE(cpu_pll_cfgs), ++ .cfgs = cpu_pll_cfgs, ++}; ++ ++static const struct ccu_pll_cfg gmac_pll_cfg = { ++ .freq = 1000000000, ++ .fbdiv = 125, ++ .frac = 0, ++ .postdiv1 = 3, ++ .postdiv2 = 1, + }; + + static struct ccu_pll gmac_pll_clk = { +@@ -439,6 +547,8 @@ static struct ccu_pll gmac_pll_clk = { + CLK_IS_CRITICAL), + }, + .lock_sts_mask = BIT(3), ++ .cfgnum = 1, ++ .cfgs = &gmac_pll_cfg, + }; + + static const struct clk_hw *gmac_pll_clk_parent[] = { +@@ -449,6 +559,14 @@ static const struct clk_parent_data gmac_pll_clk_pd[] = { + { .hw = &gmac_pll_clk.common.hw } + }; + ++static const struct ccu_pll_cfg video_pll_cfg = { ++ .freq = 792000000, ++ .fbdiv = 99, ++ .frac = 0, ++ .postdiv1 = 3, ++ .postdiv2 = 1, ++}; ++ + static struct ccu_pll video_pll_clk = { + .common = { + .clkid = CLK_VIDEO_PLL, +@@ -460,6 +578,8 @@ static struct ccu_pll video_pll_clk = { + CLK_IS_CRITICAL), + }, + .lock_sts_mask = BIT(7), ++ .cfgnum = 1, ++ .cfgs = &video_pll_cfg, + }; + + static const struct clk_hw *video_pll_clk_parent[] = { +@@ -470,6 +590,14 @@ static const struct clk_parent_data video_pll_clk_pd[] = { + { .hw = &video_pll_clk.common.hw } + }; + ++static const struct ccu_pll_cfg dpu_pll_cfg = { ++ .freq = 1188000000, ++ .fbdiv = 99, ++ .frac = 0, ++ .postdiv1 = 2, ++ .postdiv2 = 1, ++}; ++ + static struct ccu_pll dpu0_pll_clk = { + .common = { + .clkid = CLK_DPU0_PLL, +@@ -481,6 +609,8 @@ static struct ccu_pll dpu0_pll_clk = { + 0), + }, + .lock_sts_mask = BIT(8), ++ .cfgnum = 1, ++ .cfgs = &dpu_pll_cfg, + }; + + static const struct clk_hw *dpu0_pll_clk_parent[] = { +@@ -498,12 +628,22 @@ static struct ccu_pll dpu1_pll_clk = { + 0), + }, + .lock_sts_mask = BIT(9), ++ .cfgnum = 1, ++ .cfgs = &dpu_pll_cfg, + }; + + static const struct clk_hw *dpu1_pll_clk_parent[] = { + &dpu1_pll_clk.common.hw + }; + ++static const struct ccu_pll_cfg tee_pll_cfg = { ++ .freq = 792000000, ++ .fbdiv = 99, ++ .frac = 0, ++ .postdiv1 = 3, ++ .postdiv2 = 1, ++}; ++ + static struct ccu_pll tee_pll_clk = { + .common = { + .clkid = CLK_TEE_PLL, +@@ -515,6 +655,8 @@ static struct ccu_pll tee_pll_clk = { + CLK_IS_CRITICAL), + }, + .lock_sts_mask = BIT(10), ++ .cfgnum = 1, ++ .cfgs = &tee_pll_cfg, + }; + + static const struct clk_parent_data c910_i0_parents[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0130-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch b/SPECS/linux-lts/0130-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch deleted file mode 100644 index 0383823803..0000000000 --- a/SPECS/linux-lts/0130-UPSTREAM-riscv-dts-spacemit-Disable-ETH-PHY-sleep-mo.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 1a7c7e7ba083e58a4ccc3b3fa45b63089ffb6cf2 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Tue, 20 Jan 2026 18:00:01 +0800 -Subject: [PATCH 130/467] UPSTREAM: riscv: dts: spacemit: Disable ETH PHY sleep - mode for OrangePi - -On the SpacemiT K1 platform, the MAC can't read statistics when the PHY -clock stops. Disable Link Down Power Saving Mode for the YT8531C PHY on -OrangePi R2S and RV2 boards to avoid reading statistics timeout logs. - -Signed-off-by: Chukun Pan -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260120100001.1285624-2-amadeus@jmu.edu.cn -Signed-off-by: Yixun Lan -(cherry picked from commit 5164e95565d3fd508ca8a95351323f5716dfb695) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts | 2 ++ - arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 2 ++ - 2 files changed, 4 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -index 58098c4a2aab..de75f6aac740 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -@@ -52,6 +52,7 @@ mdio-bus { - - rgmii0: phy@1 { - reg = <0x1>; -+ motorcomm,auto-sleep-disabled; - }; - }; - }; -@@ -75,6 +76,7 @@ mdio-bus { - - rgmii1: phy@1 { - reg = <0x1>; -+ motorcomm,auto-sleep-disabled; - }; - }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 41dc8e35e6eb..7b7331cb3c72 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -54,6 +54,7 @@ mdio-bus { - - rgmii0: phy@1 { - reg = <0x1>; -+ motorcomm,auto-sleep-disabled; - }; - }; - }; -@@ -77,6 +78,7 @@ mdio-bus { - - rgmii1: phy@1 { - reg = <0x1>; -+ motorcomm,auto-sleep-disabled; - }; - }; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch b/SPECS/linux-lts/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch new file mode 100644 index 0000000000..2518407886 --- /dev/null +++ b/SPECS/linux-lts/0131-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch @@ -0,0 +1,50 @@ +From 17338e1f386a810ea7bbe685d7cf3953dae6a51f Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:14 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Add macro to define + multiplexers with flags + +The new macro, TH_CCU_MUX_FLAGS, extends TH_CCU_MUX macro by adding two +parameters to specify clock flags and multiplexer flags. + +Reviewed-by: Drew Fustini +Signed-off-by: Yao Zi +Signed-off-by: Drew Fustini +(cherry picked from commit 5dbee3503771a36464e0b39a420475a727911c83) +Signed-off-by: Han Gao +--- + drivers/clk/thead/clk-th1520-ap.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c +index bf8e80c39a9e..79f001a047b2 100644 +--- a/drivers/clk/thead/clk-th1520-ap.c ++++ b/drivers/clk/thead/clk-th1520-ap.c +@@ -101,17 +101,22 @@ struct ccu_pll { + .flags = _flags, \ + } + +-#define TH_CCU_MUX(_name, _parents, _shift, _width) \ ++#define TH_CCU_MUX_FLAGS(_name, _parents, _shift, _width, _flags, \ ++ _mux_flags) \ + { \ + .mask = GENMASK(_width - 1, 0), \ + .shift = _shift, \ ++ .flags = _mux_flags, \ + .hw.init = CLK_HW_INIT_PARENTS_DATA( \ + _name, \ + _parents, \ + &clk_mux_ops, \ +- 0), \ ++ _flags), \ + } + ++#define TH_CCU_MUX(_name, _parents, _shift, _width) \ ++ TH_CCU_MUX_FLAGS(_name, _parents, _shift, _width, 0, 0) ++ + #define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _bit, _flags) \ + struct ccu_gate _struct = { \ + .clkid = _clkid, \ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0131-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch b/SPECS/linux-lts/0131-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch deleted file mode 100644 index 3201f9018c..0000000000 --- a/SPECS/linux-lts/0131-UPSTREAM-dt-bindings-clock-thead-th1520-clk-ap-Add-I.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 9a01370936360c3ee7d656548a3f36e7749b5924 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:10 +0000 -Subject: [PATCH 131/467] UPSTREAM: dt-bindings: clock: thead,th1520-clk-ap: - Add ID for C910 bus clock - -Add binding ID for C910 bus clock, which takes CLK_C910 as parent and is -essential for C910 cluster's operation. - -Acked-by: Conor Dooley -Signed-off-by: Yao Zi -Signed-off-by: Drew Fustini -(cherry picked from commit 5f352125f8a0bc906dff8419a2377903012d7f35) -Signed-off-by: Han Gao ---- - include/dt-bindings/clock/thead,th1520-clk-ap.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h -index 09a9aa7b3ab1..68b35cc61204 100644 ---- a/include/dt-bindings/clock/thead,th1520-clk-ap.h -+++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h -@@ -93,6 +93,7 @@ - #define CLK_SRAM3 83 - #define CLK_PLL_GMAC_100M 84 - #define CLK_UART_SCLK 85 -+#define CLK_C910_BUS 86 - - /* VO clocks */ - #define CLK_AXI4_VO_ACLK 0 --- -2.53.0 - diff --git a/SPECS/linux-lts/0132-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch b/SPECS/linux-lts/0132-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch deleted file mode 100644 index ef29245e54..0000000000 --- a/SPECS/linux-lts/0132-UPSTREAM-clk-thead-th1520-ap-Add-C910-bus-clock.patch +++ /dev/null @@ -1,62 +0,0 @@ -From b5d944cf3ab3b20841cc2e504d8b66be87592c96 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:12 +0000 -Subject: [PATCH 132/467] UPSTREAM: clk: thead: th1520-ap: Add C910 bus clock - -This divider takes c910_clk as parent and is essential for the C910 -cluster to operate, thus is marked as CLK_IS_CRITICAL. - -Reviewed-by: Drew Fustini -Signed-off-by: Yao Zi -Signed-off-by: Drew Fustini -(cherry picked from commit b436f8a82aaa3bd54cb79b1219d94a99f7351d33) -Signed-off-by: Han Gao ---- - drivers/clk/thead/clk-th1520-ap.c | 17 ++++++++++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - -diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c -index d870f0c665f8..b820d47387bb 100644 ---- a/drivers/clk/thead/clk-th1520-ap.c -+++ b/drivers/clk/thead/clk-th1520-ap.c -@@ -539,6 +539,20 @@ static struct ccu_mux c910_clk = { - .mux = TH_CCU_MUX("c910", c910_parents, 0, 1), - }; - -+static struct ccu_div c910_bus_clk = { -+ .enable = BIT(7), -+ .div_en = BIT(11), -+ .div = TH_CCU_DIV_FLAGS(8, 3, 0), -+ .common = { -+ .clkid = CLK_C910_BUS, -+ .cfg0 = 0x100, -+ .hw.init = CLK_HW_INIT_HW("c910-bus", -+ &c910_clk.mux.hw, -+ &ccu_div_ops, -+ CLK_IS_CRITICAL), -+ }, -+}; -+ - static const struct clk_parent_data ahb2_cpusys_parents[] = { - { .hw = &gmac_pll_clk.common.hw }, - { .index = 0 } -@@ -1051,6 +1065,7 @@ static struct ccu_common *th1520_pll_clks[] = { - }; - - static struct ccu_common *th1520_div_clks[] = { -+ &c910_bus_clk.common, - &ahb2_cpusys_hclk.common, - &apb3_cpusys_pclk.common, - &axi4_cpusys2_aclk.common, -@@ -1194,7 +1209,7 @@ static const struct th1520_plat_data th1520_ap_platdata = { - .th1520_mux_clks = th1520_mux_clks, - .th1520_gate_clks = th1520_gate_clks, - -- .nr_clks = CLK_UART_SCLK + 1, -+ .nr_clks = CLK_C910_BUS + 1, - - .nr_pll_clks = ARRAY_SIZE(th1520_pll_clks), - .nr_div_clks = ARRAY_SIZE(th1520_div_clks), --- -2.53.0 - diff --git a/SPECS/linux-lts/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch b/SPECS/linux-lts/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch new file mode 100644 index 0000000000..5e088a3818 --- /dev/null +++ b/SPECS/linux-lts/0132-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch @@ -0,0 +1,240 @@ +From fc08e30c489223facf41c8c180c1d3685bad9ee9 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:15 +0000 +Subject: [RUYI PATCH] UPSTREAM: clk: thead: th1520-ap: Support CPU frequency + scaling + +On TH1520 SoC, c910_clk feeds the CPU cluster. It could be glitchlessly +reparented to one of the two PLLs: either to cpu_pll0 indirectly through +c910_i0_clk, or to cpu_pll1 directly. + +To achieve glitchless rate change, customized clock operations are +implemented for c910_clk: on rate change, the PLL not currently in use +is configured to the requested rate first, then c910_clk reparents to +it. + +Additionally, c910_bus_clk, which in turn takes c910_clk as parent, +has a frequency limit of 750MHz. A clock notifier is registered on +c910_clk to adjust c910_bus_clk on c910_clk rate change. + +Reviewed-by: Drew Fustini +Signed-off-by: Yao Zi +Signed-off-by: Drew Fustini +(cherry picked from commit baf4fc7c03bd0f68c768cfe27829674bd060c6b4) +Signed-off-by: Han Gao +--- + drivers/clk/thead/clk-th1520-ap.c | 148 +++++++++++++++++++++++++++++- + 1 file changed, 146 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c +index 79f001a047b2..3a6847f1c950 100644 +--- a/drivers/clk/thead/clk-th1520-ap.c ++++ b/drivers/clk/thead/clk-th1520-ap.c +@@ -7,9 +7,11 @@ + + #include + #include ++#include + #include + #include + #include ++#include + #include + #include + #include +@@ -34,6 +36,9 @@ + #define TH1520_PLL_LOCK_TIMEOUT_US 44 + #define TH1520_PLL_STABLE_DELAY_US 30 + ++/* c910_bus_clk must be kept below 750MHz for stability */ ++#define TH1520_C910_BUS_MAX_RATE (750 * 1000 * 1000) ++ + struct ccu_internal { + u8 shift; + u8 width; +@@ -472,6 +477,72 @@ static const struct clk_ops clk_pll_ops = { + .set_rate = ccu_pll_set_rate, + }; + ++/* ++ * c910_clk could be reparented glitchlessly for DVFS. There are two parents, ++ * - c910_i0_clk, derived from cpu_pll0_clk or osc_24m. ++ * - cpu_pll1_clk, which provides the exact same set of rates as cpu_pll0_clk. ++ * ++ * During rate setting, always forward the request to the unused parent, and ++ * then switch c910_clk to it to avoid glitch. ++ */ ++static u8 c910_clk_get_parent(struct clk_hw *hw) ++{ ++ return clk_mux_ops.get_parent(hw); ++} ++ ++static int c910_clk_set_parent(struct clk_hw *hw, u8 index) ++{ ++ return clk_mux_ops.set_parent(hw, index); ++} ++ ++static unsigned long c910_clk_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ return parent_rate; ++} ++ ++static int c910_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ u8 alt_parent_index = !c910_clk_get_parent(hw); ++ struct clk_hw *alt_parent; ++ ++ alt_parent = clk_hw_get_parent_by_index(hw, alt_parent_index); ++ ++ req->rate = clk_hw_round_rate(alt_parent, req->rate); ++ req->best_parent_hw = alt_parent; ++ req->best_parent_rate = req->rate; ++ ++ return 0; ++} ++ ++static int c910_clk_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ return -EOPNOTSUPP; ++} ++ ++static int c910_clk_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate, u8 index) ++{ ++ struct clk_hw *parent = clk_hw_get_parent_by_index(hw, index); ++ ++ clk_set_rate(parent->clk, parent_rate); ++ ++ c910_clk_set_parent(hw, index); ++ ++ return 0; ++} ++ ++static const struct clk_ops c910_clk_ops = { ++ .get_parent = c910_clk_get_parent, ++ .set_parent = c910_clk_set_parent, ++ .recalc_rate = c910_clk_recalc_rate, ++ .determine_rate = c910_clk_determine_rate, ++ .set_rate = c910_clk_set_rate, ++ .set_rate_and_parent = c910_clk_set_rate_and_parent, ++}; ++ + static const struct clk_parent_data osc_24m_clk[] = { + { .index = 0 } + }; +@@ -672,7 +743,8 @@ static const struct clk_parent_data c910_i0_parents[] = { + static struct ccu_mux c910_i0_clk = { + .clkid = CLK_C910_I0, + .reg = 0x100, +- .mux = TH_CCU_MUX("c910-i0", c910_i0_parents, 1, 1), ++ .mux = TH_CCU_MUX_FLAGS("c910-i0", c910_i0_parents, 1, 1, ++ CLK_SET_RATE_PARENT, CLK_MUX_ROUND_CLOSEST), + }; + + static const struct clk_parent_data c910_parents[] = { +@@ -683,7 +755,14 @@ static const struct clk_parent_data c910_parents[] = { + static struct ccu_mux c910_clk = { + .clkid = CLK_C910, + .reg = 0x100, +- .mux = TH_CCU_MUX("c910", c910_parents, 0, 1), ++ .mux = { ++ .mask = BIT(0), ++ .shift = 0, ++ .hw.init = CLK_HW_INIT_PARENTS_DATA("c910", ++ c910_parents, ++ &c910_clk_ops, ++ CLK_SET_RATE_PARENT), ++ }, + }; + + static struct ccu_div c910_bus_clk = { +@@ -1372,11 +1451,69 @@ static const struct th1520_plat_data th1520_vo_platdata = { + .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks), + }; + ++/* ++ * Maintain clock rate of c910_bus_clk below TH1520_C910_BUS_MAX_RATE (750MHz) ++ * when its parent, c910_clk, changes the rate. ++ * ++ * Additionally, TRM is unclear about c910_bus_clk behavior when the divisor is ++ * set below 2, thus we should ensure the new divisor stays in (2, MAXDIVISOR). ++ */ ++static unsigned long c910_bus_clk_divisor(struct ccu_div *cd, ++ unsigned long parent_rate) ++{ ++ return clamp(DIV_ROUND_UP(parent_rate, TH1520_C910_BUS_MAX_RATE), ++ 2U, 1U << cd->div.width); ++} ++ ++static int c910_clk_notifier_cb(struct notifier_block *nb, ++ unsigned long action, void *data) ++{ ++ struct clk_notifier_data *cnd = data; ++ unsigned long new_divisor, ref_rate; ++ ++ if (action != PRE_RATE_CHANGE && action != POST_RATE_CHANGE) ++ return NOTIFY_DONE; ++ ++ new_divisor = c910_bus_clk_divisor(&c910_bus_clk, cnd->new_rate); ++ ++ if (cnd->new_rate > cnd->old_rate) { ++ /* ++ * Scaling up. Adjust c910_bus_clk divisor ++ * - before c910_clk rate change to ensure the constraints ++ * aren't broken after scaling to higher rates, ++ * - after c910_clk rate change to keep c910_bus_clk as high as ++ * possible ++ */ ++ ref_rate = action == PRE_RATE_CHANGE ? ++ cnd->old_rate : cnd->new_rate; ++ clk_set_rate(c910_bus_clk.common.hw.clk, ++ ref_rate / new_divisor); ++ } else if (cnd->new_rate < cnd->old_rate && ++ action == POST_RATE_CHANGE) { ++ /* ++ * Scaling down. Adjust c910_bus_clk divisor only after ++ * c910_clk rate change to keep c910_bus_clk as high as ++ * possible, Scaling down never breaks the constraints. ++ */ ++ clk_set_rate(c910_bus_clk.common.hw.clk, ++ cnd->new_rate / new_divisor); ++ } else { ++ return NOTIFY_DONE; ++ } ++ ++ return NOTIFY_OK; ++} ++ ++static struct notifier_block c910_clk_notifier = { ++ .notifier_call = c910_clk_notifier_cb, ++}; ++ + static int th1520_clk_probe(struct platform_device *pdev) + { + const struct th1520_plat_data *plat_data; + struct device *dev = &pdev->dev; + struct clk_hw_onecell_data *priv; ++ struct clk *notifier_clk; + + struct regmap *map; + void __iomem *base; +@@ -1463,6 +1600,13 @@ static int th1520_clk_probe(struct platform_device *pdev) + ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw); + if (ret) + return ret; ++ ++ notifier_clk = devm_clk_hw_get_clk(dev, &c910_clk.mux.hw, ++ "dvfs"); ++ ret = devm_clk_notifier_register(dev, notifier_clk, ++ &c910_clk_notifier); ++ if (ret) ++ return ret; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0133-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch b/SPECS/linux-lts/0133-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch deleted file mode 100644 index af622a6e0c..0000000000 --- a/SPECS/linux-lts/0133-UPSTREAM-clk-thead-th1520-ap-Support-setting-PLL-rat.patch +++ /dev/null @@ -1,275 +0,0 @@ -From 3107f6db39bfccf7730194c3fb729357945bf743 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:13 +0000 -Subject: [PATCH 133/467] UPSTREAM: clk: thead: th1520-ap: Support setting PLL - rates - -TH1520 ships several PLLs that could operate in either integer or -fractional mode. However, the TRM only lists a few configuration whose -stability is considered guaranteed. - -Add a table-lookup rate determination logic to support PLL rate setting, -and fill up frequency-configuration tables for AP-subsystem PLLs. - -Reviewed-by: Drew Fustini -Signed-off-by: Yao Zi -Signed-off-by: Drew Fustini -(cherry picked from commit 238cc6316a885765fd52a6dc65b9ca4e47647b1e) -Signed-off-by: Han Gao ---- - drivers/clk/thead/clk-th1520-ap.c | 142 ++++++++++++++++++++++++++++++ - 1 file changed, 142 insertions(+) - -diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c -index b820d47387bb..bf8e80c39a9e 100644 ---- a/drivers/clk/thead/clk-th1520-ap.c -+++ b/drivers/clk/thead/clk-th1520-ap.c -@@ -22,6 +22,7 @@ - #define TH1520_PLL_REFDIV GENMASK(5, 0) - #define TH1520_PLL_BYPASS BIT(30) - #define TH1520_PLL_VCO_RST BIT(29) -+#define TH1520_PLL_DACPD BIT(25) - #define TH1520_PLL_DSMPD BIT(24) - #define TH1520_PLL_FRAC GENMASK(23, 0) - #define TH1520_PLL_FRAC_BITS 24 -@@ -72,9 +73,19 @@ struct ccu_div { - struct ccu_common common; - }; - -+struct ccu_pll_cfg { -+ unsigned long freq; -+ u32 fbdiv; -+ u32 frac; -+ u32 postdiv1; -+ u32 postdiv2; -+}; -+ - struct ccu_pll { - struct ccu_common common; - u32 lock_sts_mask; -+ int cfgnum; -+ const struct ccu_pll_cfg *cfgs; - }; - - #define TH_CCU_ARG(_shift, _width) \ -@@ -391,17 +402,102 @@ static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw, - return rate; - } - -+static const struct ccu_pll_cfg *ccu_pll_lookup_best_cfg(struct ccu_pll *pll, -+ unsigned long rate) -+{ -+ unsigned long best_delta = ULONG_MAX; -+ const struct ccu_pll_cfg *best_cfg; -+ int i; -+ -+ for (i = 0; i < pll->cfgnum; i++) { -+ const struct ccu_pll_cfg *cfg = &pll->cfgs[i]; -+ unsigned long delta; -+ -+ delta = abs_diff(cfg->freq, rate); -+ if (delta < best_delta) { -+ best_delta = delta; -+ best_cfg = cfg; -+ } -+ } -+ -+ return best_cfg; -+} -+ -+static int ccu_pll_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ -+ req->rate = ccu_pll_lookup_best_cfg(pll, req->rate)->freq; -+ -+ return 0; -+} -+ -+static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct ccu_pll *pll = hw_to_ccu_pll(hw); -+ const struct ccu_pll_cfg *cfg; -+ -+ cfg = ccu_pll_lookup_best_cfg(pll, rate); -+ -+ ccu_pll_disable(hw); -+ -+ regmap_write(pll->common.map, pll->common.cfg0, -+ FIELD_PREP(TH1520_PLL_REFDIV, 1) | -+ FIELD_PREP(TH1520_PLL_FBDIV, cfg->fbdiv) | -+ FIELD_PREP(TH1520_PLL_POSTDIV1, cfg->postdiv1) | -+ FIELD_PREP(TH1520_PLL_POSTDIV2, cfg->postdiv2)); -+ -+ regmap_update_bits(pll->common.map, pll->common.cfg1, -+ TH1520_PLL_DACPD | TH1520_PLL_DSMPD | -+ TH1520_PLL_FRAC, -+ cfg->frac ? cfg->frac : -+ TH1520_PLL_DACPD | TH1520_PLL_DSMPD); -+ -+ return ccu_pll_enable(hw); -+} -+ - static const struct clk_ops clk_pll_ops = { - .disable = ccu_pll_disable, - .enable = ccu_pll_enable, - .is_enabled = ccu_pll_is_enabled, - .recalc_rate = ccu_pll_recalc_rate, -+ .determine_rate = ccu_pll_determine_rate, -+ .set_rate = ccu_pll_set_rate, - }; - - static const struct clk_parent_data osc_24m_clk[] = { - { .index = 0 } - }; - -+static const struct ccu_pll_cfg cpu_pll_cfgs[] = { -+ { 125000000, 125, 0, 6, 4 }, -+ { 200000000, 125, 0, 5, 3 }, -+ { 300000000, 125, 0, 5, 2 }, -+ { 400000000, 100, 0, 3, 2 }, -+ { 500000000, 125, 0, 6, 1 }, -+ { 600000000, 125, 0, 5, 1 }, -+ { 702000000, 117, 0, 4, 1 }, -+ { 800000000, 100, 0, 3, 1 }, -+ { 900000000, 75, 0, 2, 1 }, -+ { 1000000000, 125, 0, 3, 1 }, -+ { 1104000000, 92, 0, 2, 1 }, -+ { 1200000000, 100, 0, 2, 1 }, -+ { 1296000000, 108, 0, 2, 1 }, -+ { 1404000000, 117, 0, 2, 1 }, -+ { 1500000000, 125, 0, 2, 1 }, -+ { 1608000000, 67, 0, 1, 1 }, -+ { 1704000000, 71, 0, 1, 1 }, -+ { 1800000000, 75, 0, 1, 1 }, -+ { 1896000000, 79, 0, 1, 1 }, -+ { 1992000000, 83, 0, 1, 1 }, -+ { 2112000000, 88, 0, 1, 1 }, -+ { 2208000000, 92, 0, 1, 1 }, -+ { 2304000000, 96, 0, 1, 1 }, -+ { 2400000000, 100, 0, 1, 1 }, -+}; -+ - static struct ccu_pll cpu_pll0_clk = { - .common = { - .clkid = CLK_CPU_PLL0, -@@ -413,6 +509,8 @@ static struct ccu_pll cpu_pll0_clk = { - CLK_IS_CRITICAL), - }, - .lock_sts_mask = BIT(1), -+ .cfgnum = ARRAY_SIZE(cpu_pll_cfgs), -+ .cfgs = cpu_pll_cfgs, - }; - - static struct ccu_pll cpu_pll1_clk = { -@@ -426,6 +524,16 @@ static struct ccu_pll cpu_pll1_clk = { - CLK_IS_CRITICAL), - }, - .lock_sts_mask = BIT(4), -+ .cfgnum = ARRAY_SIZE(cpu_pll_cfgs), -+ .cfgs = cpu_pll_cfgs, -+}; -+ -+static const struct ccu_pll_cfg gmac_pll_cfg = { -+ .freq = 1000000000, -+ .fbdiv = 125, -+ .frac = 0, -+ .postdiv1 = 3, -+ .postdiv2 = 1, - }; - - static struct ccu_pll gmac_pll_clk = { -@@ -439,6 +547,8 @@ static struct ccu_pll gmac_pll_clk = { - CLK_IS_CRITICAL), - }, - .lock_sts_mask = BIT(3), -+ .cfgnum = 1, -+ .cfgs = &gmac_pll_cfg, - }; - - static const struct clk_hw *gmac_pll_clk_parent[] = { -@@ -449,6 +559,14 @@ static const struct clk_parent_data gmac_pll_clk_pd[] = { - { .hw = &gmac_pll_clk.common.hw } - }; - -+static const struct ccu_pll_cfg video_pll_cfg = { -+ .freq = 792000000, -+ .fbdiv = 99, -+ .frac = 0, -+ .postdiv1 = 3, -+ .postdiv2 = 1, -+}; -+ - static struct ccu_pll video_pll_clk = { - .common = { - .clkid = CLK_VIDEO_PLL, -@@ -460,6 +578,8 @@ static struct ccu_pll video_pll_clk = { - CLK_IS_CRITICAL), - }, - .lock_sts_mask = BIT(7), -+ .cfgnum = 1, -+ .cfgs = &video_pll_cfg, - }; - - static const struct clk_hw *video_pll_clk_parent[] = { -@@ -470,6 +590,14 @@ static const struct clk_parent_data video_pll_clk_pd[] = { - { .hw = &video_pll_clk.common.hw } - }; - -+static const struct ccu_pll_cfg dpu_pll_cfg = { -+ .freq = 1188000000, -+ .fbdiv = 99, -+ .frac = 0, -+ .postdiv1 = 2, -+ .postdiv2 = 1, -+}; -+ - static struct ccu_pll dpu0_pll_clk = { - .common = { - .clkid = CLK_DPU0_PLL, -@@ -481,6 +609,8 @@ static struct ccu_pll dpu0_pll_clk = { - 0), - }, - .lock_sts_mask = BIT(8), -+ .cfgnum = 1, -+ .cfgs = &dpu_pll_cfg, - }; - - static const struct clk_hw *dpu0_pll_clk_parent[] = { -@@ -498,12 +628,22 @@ static struct ccu_pll dpu1_pll_clk = { - 0), - }, - .lock_sts_mask = BIT(9), -+ .cfgnum = 1, -+ .cfgs = &dpu_pll_cfg, - }; - - static const struct clk_hw *dpu1_pll_clk_parent[] = { - &dpu1_pll_clk.common.hw - }; - -+static const struct ccu_pll_cfg tee_pll_cfg = { -+ .freq = 792000000, -+ .fbdiv = 99, -+ .frac = 0, -+ .postdiv1 = 3, -+ .postdiv2 = 1, -+}; -+ - static struct ccu_pll tee_pll_clk = { - .common = { - .clkid = CLK_TEE_PLL, -@@ -515,6 +655,8 @@ static struct ccu_pll tee_pll_clk = { - CLK_IS_CRITICAL), - }, - .lock_sts_mask = BIT(10), -+ .cfgnum = 1, -+ .cfgs = &tee_pll_cfg, - }; - - static const struct clk_parent_data c910_i0_parents[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch b/SPECS/linux-lts/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch new file mode 100644 index 0000000000..ee84bea6d5 --- /dev/null +++ b/SPECS/linux-lts/0133-UPSTREAM-net-spacemit-display-phy-driver-information.patch @@ -0,0 +1,33 @@ +From 216580fd5ff0f2f9d1b045a0eebd53199b169c09 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sun, 1 Feb 2026 18:00:01 +0800 +Subject: [RUYI PATCH] UPSTREAM: net: spacemit: display phy driver information + +Print the PHY driver used and interrupt status after connection. + +Signed-off-by: Chukun Pan +Reviewed-by: Andrew Lunn +Link: https://patch.msgid.link/20260201100001.33102-1-amadeus@jmu.edu.cn +Signed-off-by: Jakub Kicinski +(cherry picked from commit fd102acfd362de60a941d24f0836278d839b9391) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/spacemit/k1_emac.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c +index d64ca7bbda9e..52c0c00a471f 100644 +--- a/drivers/net/ethernet/spacemit/k1_emac.c ++++ b/drivers/net/ethernet/spacemit/k1_emac.c +@@ -1757,6 +1757,8 @@ static int emac_phy_connect(struct net_device *ndev) + + emac_update_delay_line(priv); + ++ phy_attached_info(phydev); ++ + err_node_put: + of_node_put(np); + return ret; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0134-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch b/SPECS/linux-lts/0134-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch deleted file mode 100644 index bb158844fe..0000000000 --- a/SPECS/linux-lts/0134-UPSTREAM-clk-thead-th1520-ap-Add-macro-to-define-mul.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 94cd6930cd62b37d3a5be5f99c38418227dadc53 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:14 +0000 -Subject: [PATCH 134/467] UPSTREAM: clk: thead: th1520-ap: Add macro to define - multiplexers with flags - -The new macro, TH_CCU_MUX_FLAGS, extends TH_CCU_MUX macro by adding two -parameters to specify clock flags and multiplexer flags. - -Reviewed-by: Drew Fustini -Signed-off-by: Yao Zi -Signed-off-by: Drew Fustini -(cherry picked from commit 5dbee3503771a36464e0b39a420475a727911c83) -Signed-off-by: Han Gao ---- - drivers/clk/thead/clk-th1520-ap.c | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c -index bf8e80c39a9e..79f001a047b2 100644 ---- a/drivers/clk/thead/clk-th1520-ap.c -+++ b/drivers/clk/thead/clk-th1520-ap.c -@@ -101,17 +101,22 @@ struct ccu_pll { - .flags = _flags, \ - } - --#define TH_CCU_MUX(_name, _parents, _shift, _width) \ -+#define TH_CCU_MUX_FLAGS(_name, _parents, _shift, _width, _flags, \ -+ _mux_flags) \ - { \ - .mask = GENMASK(_width - 1, 0), \ - .shift = _shift, \ -+ .flags = _mux_flags, \ - .hw.init = CLK_HW_INIT_PARENTS_DATA( \ - _name, \ - _parents, \ - &clk_mux_ops, \ -- 0), \ -+ _flags), \ - } - -+#define TH_CCU_MUX(_name, _parents, _shift, _width) \ -+ TH_CCU_MUX_FLAGS(_name, _parents, _shift, _width, 0, 0) -+ - #define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _bit, _flags) \ - struct ccu_gate _struct = { \ - .clkid = _clkid, \ --- -2.53.0 - diff --git a/SPECS/linux-lts/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch b/SPECS/linux-lts/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch new file mode 100644 index 0000000000..71279bcd12 --- /dev/null +++ b/SPECS/linux-lts/0134-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch @@ -0,0 +1,73 @@ +From a000c3124b2434f1d7da679574181a5b8295c9b8 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 27 Jan 2026 10:58:49 +0800 +Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit-k1: Use PDR for pin direction, + not SDR/CDR + +On the SpacemiT GPIO controller, the direction control register PDR is +readable and writable [1]. Therefore, implement direction control by +using PDR as dirout, and don't mark it as unreadable. + +The original implementation, using SDR as dirout and CDR as dirin, is +not actually a supported configuration by gpio-mmio. The hardware +supports changing the direction of some pins atomically by writing a +value with the corresponding bits set to SDR (set as output) or to CDR +(set as input). However, gpio-mmio does not actually handle this. + +Using only PDR as dirout to match the expectations of gpio-mmio. This +also allows us to avoid clobbering potentially important GPIO direction +configurations set by pre-Linux boot stages. + +Found while trying to add PCIe support to OrangePi RV2, where the +regulator (controlled by GPIO 116) turns off on boot while some other +GPIO pin in the same bank is touched, which is not desirable. + +Link: https://developer.spacemit.com/documentation?token=Rn9Kw3iFHirAMgkIpTAcV2Arnkf#18.4-gpio # [1] +Fixes: d00553240ef8 ("gpio: spacemit: add support for K1 SoC") +Signed-off-by: Vivian Wang +Reviewed-by: Troy Mitchell +Link: https://patch.msgid.link/20260127-gpio-spacemit-k1-pdr-v1-1-bb868a517dbc@iscas.ac.cn +Signed-off-by: Bartosz Golaszewski +(cherry picked from commit aa7e37fd770bafaaf856ab77735296955b93e377) +Signed-off-by: Han Gao +--- + drivers/gpio/gpio-spacemit-k1.c | 9 +++------ + 1 file changed, 3 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c +index 8f570a1a4894..dbd2e81094b9 100644 +--- a/drivers/gpio/gpio-spacemit-k1.c ++++ b/drivers/gpio/gpio-spacemit-k1.c +@@ -199,7 +199,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + struct gpio_chip *gc = &gb->chip.gc; + struct device *dev = sg->dev; + struct gpio_irq_chip *girq; +- void __iomem *dat, *set, *clr, *dirin, *dirout; ++ void __iomem *dat, *set, *clr, *dirout; + int ret; + + gb->base = regs + sg->data->bank_offsets[index]; +@@ -208,8 +208,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + dat = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPLR]; + set = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPSR]; + clr = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPCR]; +- dirin = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GCDR]; +- dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GSDR]; ++ dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPDR]; + + config = (struct gpio_generic_chip_config) { + .dev = dev, +@@ -218,9 +217,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + .set = set, + .clr = clr, + .dirout = dirout, +- .dirin = dirin, +- .flags = GPIO_GENERIC_UNREADABLE_REG_SET | +- GPIO_GENERIC_UNREADABLE_REG_DIR, ++ .flags = GPIO_GENERIC_UNREADABLE_REG_SET, + }; + + /* This registers 32 GPIO lines per bank */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0135-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch b/SPECS/linux-lts/0135-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch deleted file mode 100644 index 4e6527f2d0..0000000000 --- a/SPECS/linux-lts/0135-UPSTREAM-clk-thead-th1520-ap-Support-CPU-frequency-s.patch +++ /dev/null @@ -1,240 +0,0 @@ -From 67a3e5cab266ebbe091c06fb4f79f60e0d87455f Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:15 +0000 -Subject: [PATCH 135/467] UPSTREAM: clk: thead: th1520-ap: Support CPU - frequency scaling - -On TH1520 SoC, c910_clk feeds the CPU cluster. It could be glitchlessly -reparented to one of the two PLLs: either to cpu_pll0 indirectly through -c910_i0_clk, or to cpu_pll1 directly. - -To achieve glitchless rate change, customized clock operations are -implemented for c910_clk: on rate change, the PLL not currently in use -is configured to the requested rate first, then c910_clk reparents to -it. - -Additionally, c910_bus_clk, which in turn takes c910_clk as parent, -has a frequency limit of 750MHz. A clock notifier is registered on -c910_clk to adjust c910_bus_clk on c910_clk rate change. - -Reviewed-by: Drew Fustini -Signed-off-by: Yao Zi -Signed-off-by: Drew Fustini -(cherry picked from commit baf4fc7c03bd0f68c768cfe27829674bd060c6b4) -Signed-off-by: Han Gao ---- - drivers/clk/thead/clk-th1520-ap.c | 148 +++++++++++++++++++++++++++++- - 1 file changed, 146 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c -index 79f001a047b2..3a6847f1c950 100644 ---- a/drivers/clk/thead/clk-th1520-ap.c -+++ b/drivers/clk/thead/clk-th1520-ap.c -@@ -7,9 +7,11 @@ - - #include - #include -+#include - #include - #include - #include -+#include - #include - #include - #include -@@ -34,6 +36,9 @@ - #define TH1520_PLL_LOCK_TIMEOUT_US 44 - #define TH1520_PLL_STABLE_DELAY_US 30 - -+/* c910_bus_clk must be kept below 750MHz for stability */ -+#define TH1520_C910_BUS_MAX_RATE (750 * 1000 * 1000) -+ - struct ccu_internal { - u8 shift; - u8 width; -@@ -472,6 +477,72 @@ static const struct clk_ops clk_pll_ops = { - .set_rate = ccu_pll_set_rate, - }; - -+/* -+ * c910_clk could be reparented glitchlessly for DVFS. There are two parents, -+ * - c910_i0_clk, derived from cpu_pll0_clk or osc_24m. -+ * - cpu_pll1_clk, which provides the exact same set of rates as cpu_pll0_clk. -+ * -+ * During rate setting, always forward the request to the unused parent, and -+ * then switch c910_clk to it to avoid glitch. -+ */ -+static u8 c910_clk_get_parent(struct clk_hw *hw) -+{ -+ return clk_mux_ops.get_parent(hw); -+} -+ -+static int c910_clk_set_parent(struct clk_hw *hw, u8 index) -+{ -+ return clk_mux_ops.set_parent(hw, index); -+} -+ -+static unsigned long c910_clk_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ return parent_rate; -+} -+ -+static int c910_clk_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ u8 alt_parent_index = !c910_clk_get_parent(hw); -+ struct clk_hw *alt_parent; -+ -+ alt_parent = clk_hw_get_parent_by_index(hw, alt_parent_index); -+ -+ req->rate = clk_hw_round_rate(alt_parent, req->rate); -+ req->best_parent_hw = alt_parent; -+ req->best_parent_rate = req->rate; -+ -+ return 0; -+} -+ -+static int c910_clk_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ return -EOPNOTSUPP; -+} -+ -+static int c910_clk_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate, u8 index) -+{ -+ struct clk_hw *parent = clk_hw_get_parent_by_index(hw, index); -+ -+ clk_set_rate(parent->clk, parent_rate); -+ -+ c910_clk_set_parent(hw, index); -+ -+ return 0; -+} -+ -+static const struct clk_ops c910_clk_ops = { -+ .get_parent = c910_clk_get_parent, -+ .set_parent = c910_clk_set_parent, -+ .recalc_rate = c910_clk_recalc_rate, -+ .determine_rate = c910_clk_determine_rate, -+ .set_rate = c910_clk_set_rate, -+ .set_rate_and_parent = c910_clk_set_rate_and_parent, -+}; -+ - static const struct clk_parent_data osc_24m_clk[] = { - { .index = 0 } - }; -@@ -672,7 +743,8 @@ static const struct clk_parent_data c910_i0_parents[] = { - static struct ccu_mux c910_i0_clk = { - .clkid = CLK_C910_I0, - .reg = 0x100, -- .mux = TH_CCU_MUX("c910-i0", c910_i0_parents, 1, 1), -+ .mux = TH_CCU_MUX_FLAGS("c910-i0", c910_i0_parents, 1, 1, -+ CLK_SET_RATE_PARENT, CLK_MUX_ROUND_CLOSEST), - }; - - static const struct clk_parent_data c910_parents[] = { -@@ -683,7 +755,14 @@ static const struct clk_parent_data c910_parents[] = { - static struct ccu_mux c910_clk = { - .clkid = CLK_C910, - .reg = 0x100, -- .mux = TH_CCU_MUX("c910", c910_parents, 0, 1), -+ .mux = { -+ .mask = BIT(0), -+ .shift = 0, -+ .hw.init = CLK_HW_INIT_PARENTS_DATA("c910", -+ c910_parents, -+ &c910_clk_ops, -+ CLK_SET_RATE_PARENT), -+ }, - }; - - static struct ccu_div c910_bus_clk = { -@@ -1372,11 +1451,69 @@ static const struct th1520_plat_data th1520_vo_platdata = { - .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks), - }; - -+/* -+ * Maintain clock rate of c910_bus_clk below TH1520_C910_BUS_MAX_RATE (750MHz) -+ * when its parent, c910_clk, changes the rate. -+ * -+ * Additionally, TRM is unclear about c910_bus_clk behavior when the divisor is -+ * set below 2, thus we should ensure the new divisor stays in (2, MAXDIVISOR). -+ */ -+static unsigned long c910_bus_clk_divisor(struct ccu_div *cd, -+ unsigned long parent_rate) -+{ -+ return clamp(DIV_ROUND_UP(parent_rate, TH1520_C910_BUS_MAX_RATE), -+ 2U, 1U << cd->div.width); -+} -+ -+static int c910_clk_notifier_cb(struct notifier_block *nb, -+ unsigned long action, void *data) -+{ -+ struct clk_notifier_data *cnd = data; -+ unsigned long new_divisor, ref_rate; -+ -+ if (action != PRE_RATE_CHANGE && action != POST_RATE_CHANGE) -+ return NOTIFY_DONE; -+ -+ new_divisor = c910_bus_clk_divisor(&c910_bus_clk, cnd->new_rate); -+ -+ if (cnd->new_rate > cnd->old_rate) { -+ /* -+ * Scaling up. Adjust c910_bus_clk divisor -+ * - before c910_clk rate change to ensure the constraints -+ * aren't broken after scaling to higher rates, -+ * - after c910_clk rate change to keep c910_bus_clk as high as -+ * possible -+ */ -+ ref_rate = action == PRE_RATE_CHANGE ? -+ cnd->old_rate : cnd->new_rate; -+ clk_set_rate(c910_bus_clk.common.hw.clk, -+ ref_rate / new_divisor); -+ } else if (cnd->new_rate < cnd->old_rate && -+ action == POST_RATE_CHANGE) { -+ /* -+ * Scaling down. Adjust c910_bus_clk divisor only after -+ * c910_clk rate change to keep c910_bus_clk as high as -+ * possible, Scaling down never breaks the constraints. -+ */ -+ clk_set_rate(c910_bus_clk.common.hw.clk, -+ cnd->new_rate / new_divisor); -+ } else { -+ return NOTIFY_DONE; -+ } -+ -+ return NOTIFY_OK; -+} -+ -+static struct notifier_block c910_clk_notifier = { -+ .notifier_call = c910_clk_notifier_cb, -+}; -+ - static int th1520_clk_probe(struct platform_device *pdev) - { - const struct th1520_plat_data *plat_data; - struct device *dev = &pdev->dev; - struct clk_hw_onecell_data *priv; -+ struct clk *notifier_clk; - - struct regmap *map; - void __iomem *base; -@@ -1463,6 +1600,13 @@ static int th1520_clk_probe(struct platform_device *pdev) - ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw); - if (ret) - return ret; -+ -+ notifier_clk = devm_clk_hw_get_clk(dev, &c910_clk.mux.hw, -+ "dvfs"); -+ ret = devm_clk_notifier_register(dev, notifier_clk, -+ &c910_clk_notifier); -+ if (ret) -+ return ret; - } - - ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); --- -2.53.0 - diff --git a/SPECS/linux-lts/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch b/SPECS/linux-lts/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch new file mode 100644 index 0000000000..315761b942 --- /dev/null +++ b/SPECS/linux-lts/0135-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch @@ -0,0 +1,37 @@ +From 9a9a68a7eddae8077db583fd6db0e31a7e837eab Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Fri, 26 Dec 2025 11:32:27 -0600 +Subject: [RUYI PATCH] UPSTREAM: phy: Kconfig: spacemit: add COMMON_CLK + dependency + +The SpacemiT PCIe PHY driver depends on the common clock framework. +Not specifying that led to a failure when doing a COMPILE_TEST build +for the SPARC architecture. + +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202512251903.sTVZgg6c-lkp@intel.com/ +Signed-off-by: Alex Elder +Reviewed-by: Javier Martinez Canillas +Link: https://patch.msgid.link/20251226173228.2020411-1-elder@riscstar.com +Signed-off-by: Vinod Koul +(cherry picked from commit 8df20813eb01fe29b4507fd470d73675bda3e1dd) +Signed-off-by: Han Gao +--- + drivers/phy/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index 95ee47f0fbc7..88ea9af445b1 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -104,6 +104,7 @@ config PHY_NXP_PTN3222 + config PHY_SPACEMIT_K1_PCIE + tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC" + depends on ARCH_SPACEMIT || COMPILE_TEST ++ depends on COMMON_CLK + depends on HAS_IOMEM + depends on OF + select GENERIC_PHY +-- +2.53.0 + diff --git a/SPECS/linux-lts/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch b/SPECS/linux-lts/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch new file mode 100644 index 0000000000..661b7fce58 --- /dev/null +++ b/SPECS/linux-lts/0136-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch @@ -0,0 +1,34 @@ +From 13956aef479172118fb402bab2ecea2f30a4a744 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 25 Dec 2025 15:46:32 +0800 +Subject: [RUYI PATCH] UPSTREAM: mfd: Kconfig: Default MFD_SPACEMIT_P1 to 'm' + if ARCH_SPACEMIT + +The default value of the P1 sub-device depends on the value +of P1, so P1 should have a default value here. + +Signed-off-by: Troy Mitchell +Acked-by: Alex Elder +Link: https://patch.msgid.link/20251225-p1-kconfig-fix-v4-2-44b6728117c1@linux.spacemit.com +Signed-off-by: Lee Jones +(cherry picked from commit 9d1e2d5f2b24a24b32aca451d6a7feb081ad5a62) +Signed-off-by: Han Gao +--- + drivers/mfd/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig +index b0264352790e..8295e7871d70 100644 +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -1270,6 +1270,7 @@ config MFD_SPACEMIT_P1 + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on I2C + select MFD_SIMPLE_MFD_I2C ++ default m if ARCH_SPACEMIT + help + This option supports the I2C-based SpacemiT P1 PMIC, which + contains regulators, a power switch, GPIOs, an RTC, and more. +-- +2.53.0 + diff --git a/SPECS/linux-lts/0136-UPSTREAM-net-spacemit-display-phy-driver-information.patch b/SPECS/linux-lts/0136-UPSTREAM-net-spacemit-display-phy-driver-information.patch deleted file mode 100644 index 756971bff5..0000000000 --- a/SPECS/linux-lts/0136-UPSTREAM-net-spacemit-display-phy-driver-information.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 20d3fa165cbcd3a84876fcbfe8f012363c75cfa0 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sun, 1 Feb 2026 18:00:01 +0800 -Subject: [PATCH 136/467] UPSTREAM: net: spacemit: display phy driver - information - -Print the PHY driver used and interrupt status after connection. - -Signed-off-by: Chukun Pan -Reviewed-by: Andrew Lunn -Link: https://patch.msgid.link/20260201100001.33102-1-amadeus@jmu.edu.cn -Signed-off-by: Jakub Kicinski -(cherry picked from commit fd102acfd362de60a941d24f0836278d839b9391) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/spacemit/k1_emac.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c -index d64ca7bbda9e..52c0c00a471f 100644 ---- a/drivers/net/ethernet/spacemit/k1_emac.c -+++ b/drivers/net/ethernet/spacemit/k1_emac.c -@@ -1757,6 +1757,8 @@ static int emac_phy_connect(struct net_device *ndev) - - emac_update_delay_line(priv); - -+ phy_attached_info(phydev); -+ - err_node_put: - of_node_put(np); - return ret; --- -2.53.0 - diff --git a/SPECS/linux-lts/0137-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch b/SPECS/linux-lts/0137-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch deleted file mode 100644 index 96d941c0e6..0000000000 --- a/SPECS/linux-lts/0137-UPSTREAM-gpio-spacemit-k1-Use-PDR-for-pin-direction-.patch +++ /dev/null @@ -1,73 +0,0 @@ -From b747ec1922a3e8649cc3e23e2e18038cb693ff9d Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 27 Jan 2026 10:58:49 +0800 -Subject: [PATCH 137/467] UPSTREAM: gpio: spacemit-k1: Use PDR for pin - direction, not SDR/CDR - -On the SpacemiT GPIO controller, the direction control register PDR is -readable and writable [1]. Therefore, implement direction control by -using PDR as dirout, and don't mark it as unreadable. - -The original implementation, using SDR as dirout and CDR as dirin, is -not actually a supported configuration by gpio-mmio. The hardware -supports changing the direction of some pins atomically by writing a -value with the corresponding bits set to SDR (set as output) or to CDR -(set as input). However, gpio-mmio does not actually handle this. - -Using only PDR as dirout to match the expectations of gpio-mmio. This -also allows us to avoid clobbering potentially important GPIO direction -configurations set by pre-Linux boot stages. - -Found while trying to add PCIe support to OrangePi RV2, where the -regulator (controlled by GPIO 116) turns off on boot while some other -GPIO pin in the same bank is touched, which is not desirable. - -Link: https://developer.spacemit.com/documentation?token=Rn9Kw3iFHirAMgkIpTAcV2Arnkf#18.4-gpio # [1] -Fixes: d00553240ef8 ("gpio: spacemit: add support for K1 SoC") -Signed-off-by: Vivian Wang -Reviewed-by: Troy Mitchell -Link: https://patch.msgid.link/20260127-gpio-spacemit-k1-pdr-v1-1-bb868a517dbc@iscas.ac.cn -Signed-off-by: Bartosz Golaszewski -(cherry picked from commit aa7e37fd770bafaaf856ab77735296955b93e377) -Signed-off-by: Han Gao ---- - drivers/gpio/gpio-spacemit-k1.c | 9 +++------ - 1 file changed, 3 insertions(+), 6 deletions(-) - -diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c -index 8f570a1a4894..dbd2e81094b9 100644 ---- a/drivers/gpio/gpio-spacemit-k1.c -+++ b/drivers/gpio/gpio-spacemit-k1.c -@@ -199,7 +199,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - struct gpio_chip *gc = &gb->chip.gc; - struct device *dev = sg->dev; - struct gpio_irq_chip *girq; -- void __iomem *dat, *set, *clr, *dirin, *dirout; -+ void __iomem *dat, *set, *clr, *dirout; - int ret; - - gb->base = regs + sg->data->bank_offsets[index]; -@@ -208,8 +208,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - dat = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPLR]; - set = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPSR]; - clr = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPCR]; -- dirin = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GCDR]; -- dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GSDR]; -+ dirout = gb->base + to_spacemit_gpio_regs(gb)[SPACEMIT_GPDR]; - - config = (struct gpio_generic_chip_config) { - .dev = dev, -@@ -218,9 +217,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - .set = set, - .clr = clr, - .dirout = dirout, -- .dirin = dirin, -- .flags = GPIO_GENERIC_UNREADABLE_REG_SET | -- GPIO_GENERIC_UNREADABLE_REG_DIR, -+ .flags = GPIO_GENERIC_UNREADABLE_REG_SET, - }; - - /* This registers 32 GPIO lines per bank */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch b/SPECS/linux-lts/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch new file mode 100644 index 0000000000..f0ab6e429d --- /dev/null +++ b/SPECS/linux-lts/0137-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch @@ -0,0 +1,33 @@ +From c37e910069a44317c77ac4d11b37028e5c7a3473 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 23 Dec 2025 10:24:51 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: sdhci: add reset support + +Request two reset line explicitly for SDHCI controller. + +Reviewed-by: Javier Martinez Canillas +Link: https://lore.kernel.org/r/20251223-07-k1-sdhci-reset-v2-3-5b8248cfc522@gentoo.org +Signed-off-by: Yixun Lan +(cherry picked from commit 7689c2d1bb1f53b170af79007d0611b43f232f05) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 0a884947fda4..529ec68e9c23 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -1201,6 +1201,9 @@ emmc: mmc@d4281000 { + clocks = <&syscon_apmu CLK_SDH_AXI>, + <&syscon_apmu CLK_SDH2>; + clock-names = "core", "io"; ++ resets = <&syscon_apmu RESET_SDH_AXI>, ++ <&syscon_apmu RESET_SDH2>; ++ reset-names = "axi", "sdh"; + interrupts = <101>; + status = "disabled"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch b/SPECS/linux-lts/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch new file mode 100644 index 0000000000..d3ca21faa5 --- /dev/null +++ b/SPECS/linux-lts/0138-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch @@ -0,0 +1,52 @@ +From cbbdae1821a5dd4f90a95e88d5c536f2421da1b6 Mon Sep 17 00:00:00 2001 +From: Charles Mirabile +Date: Mon, 3 Nov 2025 11:18:13 -0500 +Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Fix call to + __plic_toggle() in M-Mode code path + +The code path for M-Mode linux that disables interrupts for other contexts +was missed when refactoring __plic_toggle(). + +Since the new version caches updates to the state for the primary context, +its use in this codepath is no longer desireable even if it could be made +correct. + +Replace the calls to __plic_toggle() with a loop that simply disables all +of the interrupts in groups of 32 with a direct mmio write. + +Fixes: 14ff9e54dd14 ("irqchip/sifive-plic: Cache the interrupt enable state") +Reported-by: kernel test robot +Signed-off-by: Charles Mirabile +Signed-off-by: Thomas Gleixner +Link: https://patch.msgid.link/20251103161813.2437427-1-cmirabil@redhat.com +Closes: https://lore.kernel.org/oe-kbuild-all/202510271316.AQM7gCCy-lkp@intel.com/ +(cherry picked from commit a045359e72455c4fd178fbedbf398f8df7da97e7) +Signed-off-by: Han Gao +--- + drivers/irqchip/irq-sifive-plic.c | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c +index b6ea38e24af3..53e446117599 100644 +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -684,12 +684,11 @@ static int plic_probe(struct fwnode_handle *fwnode) + if (parent_hwirq != RV_IRQ_EXT) { + /* Disable S-mode enable bits if running in M-mode. */ + if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { +- void __iomem *enable_base = priv->regs + +- CONTEXT_ENABLE_BASE + +- i * CONTEXT_ENABLE_SIZE; ++ u32 __iomem *enable_base = priv->regs + CONTEXT_ENABLE_BASE + ++ i * CONTEXT_ENABLE_SIZE; + +- for (hwirq = 1; hwirq <= nr_irqs; hwirq++) +- __plic_toggle(enable_base, hwirq, 0); ++ for (int j = 0; j <= nr_irqs / 32; j++) ++ writel(0, enable_base + j); + } + continue; + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0138-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch b/SPECS/linux-lts/0138-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch deleted file mode 100644 index 2865bd4d90..0000000000 --- a/SPECS/linux-lts/0138-UPSTREAM-phy-Kconfig-spacemit-add-COMMON_CLK-depende.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 333c560956b18cc11cf301ba2198e261c02c7e73 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Fri, 26 Dec 2025 11:32:27 -0600 -Subject: [PATCH 138/467] UPSTREAM: phy: Kconfig: spacemit: add COMMON_CLK - dependency - -The SpacemiT PCIe PHY driver depends on the common clock framework. -Not specifying that led to a failure when doing a COMPILE_TEST build -for the SPARC architecture. - -Reported-by: kernel test robot -Closes: https://lore.kernel.org/oe-kbuild-all/202512251903.sTVZgg6c-lkp@intel.com/ -Signed-off-by: Alex Elder -Reviewed-by: Javier Martinez Canillas -Link: https://patch.msgid.link/20251226173228.2020411-1-elder@riscstar.com -Signed-off-by: Vinod Koul -(cherry picked from commit 8df20813eb01fe29b4507fd470d73675bda3e1dd) -Signed-off-by: Han Gao ---- - drivers/phy/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig -index 95ee47f0fbc7..88ea9af445b1 100644 ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -104,6 +104,7 @@ config PHY_NXP_PTN3222 - config PHY_SPACEMIT_K1_PCIE - tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC" - depends on ARCH_SPACEMIT || COMPILE_TEST -+ depends on COMMON_CLK - depends on HAS_IOMEM - depends on OF - select GENERIC_PHY --- -2.53.0 - diff --git a/SPECS/linux-lts/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch b/SPECS/linux-lts/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch new file mode 100644 index 0000000000..a2ed1e4b8d --- /dev/null +++ b/SPECS/linux-lts/0139-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch @@ -0,0 +1,41 @@ +From d25027971bf83bf11dd914b3ce914fa9ada558c4 Mon Sep 17 00:00:00 2001 +From: Yangyu Chen +Date: Wed, 4 Feb 2026 01:21:48 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: interrupt-controller: + sifive,plic: Clarify the riscv,ndev meaning in PLIC + +In PLIC, interrupt source 0 is reserved and should not be used. +Therefore, the valid interrupt sources are from 1 to riscv,ndev +inclusive. + +Update the documentation to clarify this point. + +[ tglx: Fixup subject prefix ] + +Signed-off-by: Yangyu Chen +Signed-off-by: Thomas Gleixner +Link: https://patch.msgid.link/tencent_720A4669773B1EE15EC720869C35C2F0490A@qq.com +(cherry picked from commit 889588d750506d86ba16ae3b968b5ffc5937d5f8) +Signed-off-by: Han Gao +--- + .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +index 234cdc2a1a26..8ff5dda648f6 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml ++++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +@@ -105,7 +105,9 @@ properties: + riscv,ndev: + $ref: /schemas/types.yaml#/definitions/uint32 + description: +- Specifies how many external interrupts are supported by this controller. ++ Specifies how many external (device) interrupts are supported by this ++ controller. Note that source 0 is reserved in PLIC, so the valid ++ interrupt sources are 1 to riscv,ndev inclusive. + + clocks: true + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0139-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch b/SPECS/linux-lts/0139-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch deleted file mode 100644 index 437a02c89d..0000000000 --- a/SPECS/linux-lts/0139-UPSTREAM-mfd-Kconfig-Default-MFD_SPACEMIT_P1-to-m-if.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0eab8250c33a6d8337f71d836737b0f27ac47f13 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 25 Dec 2025 15:46:32 +0800 -Subject: [PATCH 139/467] UPSTREAM: mfd: Kconfig: Default MFD_SPACEMIT_P1 to - 'm' if ARCH_SPACEMIT - -The default value of the P1 sub-device depends on the value -of P1, so P1 should have a default value here. - -Signed-off-by: Troy Mitchell -Acked-by: Alex Elder -Link: https://patch.msgid.link/20251225-p1-kconfig-fix-v4-2-44b6728117c1@linux.spacemit.com -Signed-off-by: Lee Jones -(cherry picked from commit 9d1e2d5f2b24a24b32aca451d6a7feb081ad5a62) -Signed-off-by: Han Gao ---- - drivers/mfd/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig -index b0264352790e..8295e7871d70 100644 ---- a/drivers/mfd/Kconfig -+++ b/drivers/mfd/Kconfig -@@ -1270,6 +1270,7 @@ config MFD_SPACEMIT_P1 - depends on ARCH_SPACEMIT || COMPILE_TEST - depends on I2C - select MFD_SIMPLE_MFD_I2C -+ default m if ARCH_SPACEMIT - help - This option supports the I2C-based SpacemiT P1 PMIC, which - contains regulators, a power switch, GPIOs, an RTC, and more. --- -2.53.0 - diff --git a/SPECS/linux-lts/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch b/SPECS/linux-lts/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch new file mode 100644 index 0000000000..b6309ec5fd --- /dev/null +++ b/SPECS/linux-lts/0140-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch @@ -0,0 +1,229 @@ +From 8c3cf0715b0fdf641d78f56c2a4a207b6fb93525 Mon Sep 17 00:00:00 2001 +From: Thomas Gleixner +Date: Tue, 3 Feb 2026 20:16:12 +0100 +Subject: [RUYI PATCH] UPSTREAM: irqchip/sifive-plic: Handle number of hardware + interrupts correctly + +The driver is handling the number of hardware interrupts inconsistently. + +The reason is that the firmware enumerates the maximum number of device +interrupts, but the actual number of hardware interrupts is one more +because hardware interrupt 0 is reserved. + +There are two loop variants where this matters: + + 1) Iterating over the device interrupts + + for (irq = 1; irq < total_irqs; irq++) + + 2) Iterating over the number of interrupt register groups + + for (grp = 0; grp < irq_groups; grp++) + +The current code stores the number of device interrupts and that requires +to write the loops as: + + 1) for (irq = 1; irq <= device_irqs; irq++) + + 2) for (grp = 0; grp < DIV_ROUND_UP(device_irqs + 1); grp++) + +But the code gets it wrong all over the place. Just fixing up the +conditions and off by ones is not a sustainable solution as the next changes +will reintroduce the same bugs over and over. + +Sanitize it by storing the total number of hardware interrupts during probe +and precalculating the number of groups. To future proof it mark +priv::total_irqs __private, provide a correct iterator macro and adjust the +code to this. + +Marking it private allows sparse (C=1 build) to catch direct access to this +member: + + drivers/irqchip/irq-sifive-plic.c:270:9: warning: dereference of noderef expression + +That should prevent at least the most obvious future damage in that area. + +Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation") +Reported-by: Yangyu Chen +Signed-off-by: Thomas Gleixner +Tested-by: Yangyu Chen +Link: https://patch.msgid.link/87ikcd36i9.ffs@tglx +(cherry picked from commit 42e025b719c128bdf8ff88584589a1e4a2448c81) +Signed-off-by: Han Gao +--- + drivers/irqchip/irq-sifive-plic.c | 82 +++++++++++++++++-------------- + 1 file changed, 45 insertions(+), 37 deletions(-) + +diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c +index 53e446117599..f255fa044764 100644 +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -68,15 +68,17 @@ + #define PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM 1 + + struct plic_priv { +- struct fwnode_handle *fwnode; +- struct cpumask lmask; +- struct irq_domain *irqdomain; +- void __iomem *regs; +- unsigned long plic_quirks; +- unsigned int nr_irqs; +- unsigned long *prio_save; +- u32 gsi_base; +- int acpi_plic_id; ++ struct fwnode_handle *fwnode; ++ struct cpumask lmask; ++ struct irq_domain *irqdomain; ++ void __iomem *regs; ++ unsigned long plic_quirks; ++ /* device interrupts + 1 to compensate for the reserved hwirq 0 */ ++ unsigned int __private total_irqs; ++ unsigned int irq_groups; ++ unsigned long *prio_save; ++ u32 gsi_base; ++ int acpi_plic_id; + }; + + struct plic_handler { +@@ -91,6 +93,12 @@ struct plic_handler { + u32 *enable_save; + struct plic_priv *priv; + }; ++ ++/* ++ * Macro to deal with the insanity of hardware interrupt 0 being reserved */ ++#define for_each_device_irq(iter, priv) \ ++ for (unsigned int iter = 1; iter < ACCESS_PRIVATE(priv, total_irqs); iter++) ++ + static int plic_parent_irq __ro_after_init; + static bool plic_global_setup_done __ro_after_init; + static DEFINE_PER_CPU(struct plic_handler, plic_handlers); +@@ -262,14 +270,11 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type) + + static int plic_irq_suspend(void) + { +- struct plic_priv *priv; +- +- priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; ++ struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; + +- /* irq ID 0 is reserved */ +- for (unsigned int i = 1; i < priv->nr_irqs; i++) { +- __assign_bit(i, priv->prio_save, +- readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID)); ++ for_each_device_irq(irq, priv) { ++ __assign_bit(irq, priv->prio_save, ++ readl(priv->regs + PRIORITY_BASE + irq * PRIORITY_PER_ID)); + } + + return 0; +@@ -277,18 +282,15 @@ static int plic_irq_suspend(void) + + static void plic_irq_resume(void) + { +- unsigned int i, index, cpu; ++ struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; ++ unsigned int index, cpu; + unsigned long flags; + u32 __iomem *reg; +- struct plic_priv *priv; +- +- priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; + +- /* irq ID 0 is reserved */ +- for (i = 1; i < priv->nr_irqs; i++) { +- index = BIT_WORD(i); +- writel((priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0, +- priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID); ++ for_each_device_irq(irq, priv) { ++ index = BIT_WORD(irq); ++ writel((priv->prio_save[index] & BIT_MASK(irq)) ? 1 : 0, ++ priv->regs + PRIORITY_BASE + irq * PRIORITY_PER_ID); + } + + for_each_present_cpu(cpu) { +@@ -298,7 +300,7 @@ static void plic_irq_resume(void) + continue; + + raw_spin_lock_irqsave(&handler->enable_lock, flags); +- for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { ++ for (unsigned int i = 0; i < priv->irq_groups; i++) { + reg = handler->enable_base + i * sizeof(u32); + writel(handler->enable_save[i], reg); + } +@@ -432,7 +434,7 @@ static u32 cp100_isolate_pending_irq(int nr_irq_groups, struct plic_handler *han + + static irq_hw_number_t cp100_get_hwirq(struct plic_handler *handler, void __iomem *claim) + { +- int nr_irq_groups = DIV_ROUND_UP(handler->priv->nr_irqs, 32); ++ int nr_irq_groups = handler->priv->irq_groups; + u32 __iomem *enable = handler->enable_base; + irq_hw_number_t hwirq = 0; + u32 iso_mask; +@@ -615,7 +617,6 @@ static int plic_probe(struct fwnode_handle *fwnode) + struct plic_handler *handler; + u32 nr_irqs, parent_hwirq; + struct plic_priv *priv; +- irq_hw_number_t hwirq; + void __iomem *regs; + int id, context_id; + u32 gsi_base; +@@ -648,7 +649,16 @@ static int plic_probe(struct fwnode_handle *fwnode) + + priv->fwnode = fwnode; + priv->plic_quirks = plic_quirks; +- priv->nr_irqs = nr_irqs; ++ /* ++ * The firmware provides the number of device interrupts. As ++ * hardware interrupt 0 is reserved, the number of total interrupts ++ * is nr_irqs + 1. ++ */ ++ nr_irqs++; ++ ACCESS_PRIVATE(priv, total_irqs) = nr_irqs; ++ /* Precalculate the number of register groups */ ++ priv->irq_groups = DIV_ROUND_UP(nr_irqs, 32); ++ + priv->regs = regs; + priv->gsi_base = gsi_base; + priv->acpi_plic_id = id; +@@ -687,7 +697,7 @@ static int plic_probe(struct fwnode_handle *fwnode) + u32 __iomem *enable_base = priv->regs + CONTEXT_ENABLE_BASE + + i * CONTEXT_ENABLE_SIZE; + +- for (int j = 0; j <= nr_irqs / 32; j++) ++ for (int j = 0; j < priv->irq_groups; j++) + writel(0, enable_base + j); + } + continue; +@@ -719,23 +729,21 @@ static int plic_probe(struct fwnode_handle *fwnode) + context_id * CONTEXT_ENABLE_SIZE; + handler->priv = priv; + +- handler->enable_save = kcalloc(DIV_ROUND_UP(nr_irqs, 32), +- sizeof(*handler->enable_save), GFP_KERNEL); ++ handler->enable_save = kcalloc(priv->irq_groups, sizeof(*handler->enable_save), ++ GFP_KERNEL); + if (!handler->enable_save) { + error = -ENOMEM; + goto fail_cleanup_contexts; + } + done: +- for (hwirq = 1; hwirq <= nr_irqs; hwirq++) { ++ for_each_device_irq(hwirq, priv) { + plic_toggle(handler, hwirq, 0); +- writel(1, priv->regs + PRIORITY_BASE + +- hwirq * PRIORITY_PER_ID); ++ writel(1, priv->regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID); + } + nr_handlers++; + } + +- priv->irqdomain = irq_domain_create_linear(fwnode, nr_irqs + 1, +- &plic_irqdomain_ops, priv); ++ priv->irqdomain = irq_domain_create_linear(fwnode, nr_irqs, &plic_irqdomain_ops, priv); + if (WARN_ON(!priv->irqdomain)) { + error = -ENOMEM; + goto fail_cleanup_contexts; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0140-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch b/SPECS/linux-lts/0140-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch deleted file mode 100644 index 07df5e5f9d..0000000000 --- a/SPECS/linux-lts/0140-UPSTREAM-riscv-dts-spacemit-sdhci-add-reset-support.patch +++ /dev/null @@ -1,34 +0,0 @@ -From dded14b2f88c749f0ee43ce0475efa38aab240b7 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 23 Dec 2025 10:24:51 +0800 -Subject: [PATCH 140/467] UPSTREAM: riscv: dts: spacemit: sdhci: add reset - support - -Request two reset line explicitly for SDHCI controller. - -Reviewed-by: Javier Martinez Canillas -Link: https://lore.kernel.org/r/20251223-07-k1-sdhci-reset-v2-3-5b8248cfc522@gentoo.org -Signed-off-by: Yixun Lan -(cherry picked from commit 7689c2d1bb1f53b170af79007d0611b43f232f05) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 0a884947fda4..529ec68e9c23 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -1201,6 +1201,9 @@ emmc: mmc@d4281000 { - clocks = <&syscon_apmu CLK_SDH_AXI>, - <&syscon_apmu CLK_SDH2>; - clock-names = "core", "io"; -+ resets = <&syscon_apmu RESET_SDH_AXI>, -+ <&syscon_apmu RESET_SDH2>; -+ reset-names = "axi", "sdh"; - interrupts = <101>; - status = "disabled"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch b/SPECS/linux-lts/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch new file mode 100644 index 0000000000..ec4bffaa6b --- /dev/null +++ b/SPECS/linux-lts/0141-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch @@ -0,0 +1,145 @@ +From fd2ed2a093642f9ae52054344b23d1c512e4d4b6 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Fri, 9 Jan 2026 19:34:30 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: dwc: Use multiple iATU windows for + mapping large bridge windows and DMA ranges + +The DWC driver tries to use a single iATU region for mapping the individual +entries of the bridge window and DMA range. If a bridge window/DMA range is +larger than the iATU inbound/outbound window size, then the mapping will +fail. + +Hence, avoid this failure by using multiple iATU windows to map the whole +region. If the region runs out of iATU windows, then return failure. + +Signed-off-by: Charles Mirabile +Signed-off-by: Samuel Holland +Co-developed-by: Randolph Lin +Signed-off-by: Randolph Lin +[mani: reworded description, minor code cleanup] +Signed-off-by: Manivannan Sadhasivam +Reviewed-by: Niklas Cassel +Reviewed-by: Frank Li +Acked-by: Charles Mirabile +Link: https://patch.msgid.link/20260109113430.2767264-1-randolph@andestech.com +(cherry picked from commit e9a5415adb209f86a05e55b850127ada82e070f1) +Signed-off-by: Han Gao +--- + .../pci/controller/dwc/pcie-designware-host.c | 74 ++++++++++++++----- + 1 file changed, 57 insertions(+), 17 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c +index 48e4a887bb1b..993858fd0529 100644 +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -887,29 +887,50 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) + + i = 0; + resource_list_for_each_entry(entry, &pp->bridge->windows) { ++ resource_size_t res_size; ++ + if (resource_type(entry->res) != IORESOURCE_MEM) + continue; + +- if (pci->num_ob_windows <= ++i) ++ if (pci->num_ob_windows <= i + 1) + break; + +- atu.index = i; + atu.type = PCIE_ATU_TYPE_MEM; + atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset; + atu.pci_addr = entry->res->start - entry->offset; + + /* Adjust iATU size if MSG TLP region was allocated before */ + if (pp->msg_res && pp->msg_res->parent == entry->res) +- atu.size = resource_size(entry->res) - ++ res_size = resource_size(entry->res) - + resource_size(pp->msg_res); + else +- atu.size = resource_size(entry->res); ++ res_size = resource_size(entry->res); ++ ++ while (res_size > 0) { ++ /* ++ * Return failure if we run out of windows in the ++ * middle. Otherwise, we would end up only partially ++ * mapping a single resource. ++ */ ++ if (pci->num_ob_windows <= ++i) { ++ dev_err(pci->dev, "Exhausted outbound windows for region: %pr\n", ++ entry->res); ++ return -ENOMEM; ++ } + +- ret = dw_pcie_prog_outbound_atu(pci, &atu); +- if (ret) { +- dev_err(pci->dev, "Failed to set MEM range %pr\n", +- entry->res); +- return ret; ++ atu.index = i; ++ atu.size = MIN(pci->region_limit + 1, res_size); ++ ++ ret = dw_pcie_prog_outbound_atu(pci, &atu); ++ if (ret) { ++ dev_err(pci->dev, "Failed to set MEM range %pr\n", ++ entry->res); ++ return ret; ++ } ++ ++ atu.parent_bus_addr += atu.size; ++ atu.pci_addr += atu.size; ++ res_size -= atu.size; + } + } + +@@ -947,20 +968,39 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) + + i = 0; + resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { ++ resource_size_t res_start, res_size, window_size; ++ + if (resource_type(entry->res) != IORESOURCE_MEM) + continue; + + if (pci->num_ib_windows <= i) + break; + +- ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, +- entry->res->start, +- entry->res->start - entry->offset, +- resource_size(entry->res)); +- if (ret) { +- dev_err(pci->dev, "Failed to set DMA range %pr\n", +- entry->res); +- return ret; ++ res_size = resource_size(entry->res); ++ res_start = entry->res->start; ++ while (res_size > 0) { ++ /* ++ * Return failure if we run out of windows in the ++ * middle. Otherwise, we would end up only partially ++ * mapping a single resource. ++ */ ++ if (pci->num_ib_windows <= i) { ++ dev_err(pci->dev, "Exhausted inbound windows for region: %pr\n", ++ entry->res); ++ return -ENOMEM; ++ } ++ ++ window_size = MIN(pci->region_limit + 1, res_size); ++ ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, res_start, ++ res_start - entry->offset, window_size); ++ if (ret) { ++ dev_err(pci->dev, "Failed to set DMA range %pr\n", ++ entry->res); ++ return ret; ++ } ++ ++ res_start += window_size; ++ res_size -= window_size; + } + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0141-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch b/SPECS/linux-lts/0141-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch deleted file mode 100644 index c0f3a9e111..0000000000 --- a/SPECS/linux-lts/0141-UPSTREAM-irqchip-sifive-plic-Fix-call-to-__plic_togg.patch +++ /dev/null @@ -1,52 +0,0 @@ -From f58e9a459a7b6b435352438dc53508ab2626a69a Mon Sep 17 00:00:00 2001 -From: Charles Mirabile -Date: Mon, 3 Nov 2025 11:18:13 -0500 -Subject: [PATCH 141/467] UPSTREAM: irqchip/sifive-plic: Fix call to - __plic_toggle() in M-Mode code path - -The code path for M-Mode linux that disables interrupts for other contexts -was missed when refactoring __plic_toggle(). - -Since the new version caches updates to the state for the primary context, -its use in this codepath is no longer desireable even if it could be made -correct. - -Replace the calls to __plic_toggle() with a loop that simply disables all -of the interrupts in groups of 32 with a direct mmio write. - -Fixes: 14ff9e54dd14 ("irqchip/sifive-plic: Cache the interrupt enable state") -Reported-by: kernel test robot -Signed-off-by: Charles Mirabile -Signed-off-by: Thomas Gleixner -Link: https://patch.msgid.link/20251103161813.2437427-1-cmirabil@redhat.com -Closes: https://lore.kernel.org/oe-kbuild-all/202510271316.AQM7gCCy-lkp@intel.com/ -(cherry picked from commit a045359e72455c4fd178fbedbf398f8df7da97e7) -Signed-off-by: Han Gao ---- - drivers/irqchip/irq-sifive-plic.c | 9 ++++----- - 1 file changed, 4 insertions(+), 5 deletions(-) - -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index b6ea38e24af3..53e446117599 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -684,12 +684,11 @@ static int plic_probe(struct fwnode_handle *fwnode) - if (parent_hwirq != RV_IRQ_EXT) { - /* Disable S-mode enable bits if running in M-mode. */ - if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { -- void __iomem *enable_base = priv->regs + -- CONTEXT_ENABLE_BASE + -- i * CONTEXT_ENABLE_SIZE; -+ u32 __iomem *enable_base = priv->regs + CONTEXT_ENABLE_BASE + -+ i * CONTEXT_ENABLE_SIZE; - -- for (hwirq = 1; hwirq <= nr_irqs; hwirq++) -- __plic_toggle(enable_base, hwirq, 0); -+ for (int j = 0; j <= nr_irqs / 32; j++) -+ writel(0, enable_base + j); - } - continue; - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0142-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch b/SPECS/linux-lts/0142-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch deleted file mode 100644 index 7916a81092..0000000000 --- a/SPECS/linux-lts/0142-UPSTREAM-dt-bindings-interrupt-controller-sifive-pli.patch +++ /dev/null @@ -1,41 +0,0 @@ -From bf88342cbbf18edbfbf27a30b622622f47dd21d1 Mon Sep 17 00:00:00 2001 -From: Yangyu Chen -Date: Wed, 4 Feb 2026 01:21:48 +0800 -Subject: [PATCH 142/467] UPSTREAM: dt-bindings: interrupt-controller: - sifive,plic: Clarify the riscv,ndev meaning in PLIC - -In PLIC, interrupt source 0 is reserved and should not be used. -Therefore, the valid interrupt sources are from 1 to riscv,ndev -inclusive. - -Update the documentation to clarify this point. - -[ tglx: Fixup subject prefix ] - -Signed-off-by: Yangyu Chen -Signed-off-by: Thomas Gleixner -Link: https://patch.msgid.link/tencent_720A4669773B1EE15EC720869C35C2F0490A@qq.com -(cherry picked from commit 889588d750506d86ba16ae3b968b5ffc5937d5f8) -Signed-off-by: Han Gao ---- - .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml -index 234cdc2a1a26..8ff5dda648f6 100644 ---- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml -+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml -@@ -105,7 +105,9 @@ properties: - riscv,ndev: - $ref: /schemas/types.yaml#/definitions/uint32 - description: -- Specifies how many external interrupts are supported by this controller. -+ Specifies how many external (device) interrupts are supported by this -+ controller. Note that source 0 is reserved in PLIC, so the valid -+ interrupt sources are 1 to riscv,ndev inclusive. - - clocks: true - --- -2.53.0 - diff --git a/SPECS/linux-lts/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch b/SPECS/linux-lts/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch new file mode 100644 index 0000000000..35a46d601c --- /dev/null +++ b/SPECS/linux-lts/0142-UPSTREAM-pinctrl-th1520-Fix-typo.patch @@ -0,0 +1,32 @@ +From b88d7d9315cd6748d47a8ced520004d8f68ec0fc Mon Sep 17 00:00:00 2001 +From: Thomas Gerner +Date: Tue, 20 Jan 2026 09:59:26 +0100 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: th1520: Fix typo + +This fixes a simple typo in the TH1520 SPI0 for group3 pins: +QSPI0 is misspelled QSPI1. + +Signed-off-by: Thomas Gerner +Signed-off-by: Linus Walleij +(cherry picked from commit 304c3ebcaff36560d76e3030ba0839e629635f47) +Signed-off-by: Han Gao +--- + drivers/pinctrl/pinctrl-th1520.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c +index e641bad6728c..83e9c9f77370 100644 +--- a/drivers/pinctrl/pinctrl-th1520.c ++++ b/drivers/pinctrl/pinctrl-th1520.c +@@ -287,7 +287,7 @@ static const struct pinctrl_pin_desc th1520_group3_pins[] = { + TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(6, QSPI0_D1_MISO, QSPI, PWM, I2S, GPIO, ____, ____, 0), + TH1520_PAD(7, QSPI0_D2_WP, QSPI, PWM, I2S, GPIO, ____, ____, 0), +- TH1520_PAD(8, QSPI1_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0), ++ TH1520_PAD(8, QSPI0_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0), + TH1520_PAD(9, I2C2_SCL, I2C, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(10, I2C2_SDA, I2C, UART, ____, GPIO, ____, ____, 0), + TH1520_PAD(11, I2C3_SCL, I2C, ____, ____, GPIO, ____, ____, 0), +-- +2.53.0 + diff --git a/SPECS/linux-lts/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch b/SPECS/linux-lts/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch new file mode 100644 index 0000000000..88cfd245f1 --- /dev/null +++ b/SPECS/linux-lts/0143-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch @@ -0,0 +1,73 @@ +From e3974191639e3270eddc65bb437b729a750e5dc7 Mon Sep 17 00:00:00 2001 +From: Manikandan K Pillai +Date: Sat, 8 Nov 2025 22:02:56 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Add module support for platform + controller driver + +Add support for building PCI cadence platforms as a module. + +Signed-off-by: Manikandan K Pillai +Signed-off-by: Manivannan Sadhasivam +Link: https://patch.msgid.link/20251108140305.1120117-2-hans.zhang@cixtech.com +(cherry picked from commit 611627a4e5e4af7b96aab4f10d130f6a8a615020) +Signed-off-by: Han Gao +--- + drivers/pci/controller/cadence/Kconfig | 6 +++--- + drivers/pci/controller/cadence/pcie-cadence-plat.c | 5 ++++- + drivers/pci/controller/cadence/pcie-cadence.c | 1 + + 3 files changed, 8 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig +index 02a639e55fd8..0b96499ae354 100644 +--- a/drivers/pci/controller/cadence/Kconfig ++++ b/drivers/pci/controller/cadence/Kconfig +@@ -19,10 +19,10 @@ config PCIE_CADENCE_EP + select PCIE_CADENCE + + config PCIE_CADENCE_PLAT +- bool ++ tristate + + config PCIE_CADENCE_PLAT_HOST +- bool "Cadence platform PCIe controller (host mode)" ++ tristate "Cadence platform PCIe controller (host mode)" + depends on OF + select PCIE_CADENCE_HOST + select PCIE_CADENCE_PLAT +@@ -32,7 +32,7 @@ config PCIE_CADENCE_PLAT_HOST + vendors SoCs. + + config PCIE_CADENCE_PLAT_EP +- bool "Cadence platform PCIe controller (endpoint mode)" ++ tristate "Cadence platform PCIe controller (endpoint mode)" + depends on OF + depends on PCI_ENDPOINT + select PCIE_CADENCE_EP +diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c +index 0456845dabb9..ebd5c3afdfcd 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence-plat.c ++++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c +@@ -177,4 +177,7 @@ static struct platform_driver cdns_plat_pcie_driver = { + .probe = cdns_plat_pcie_probe, + .shutdown = cdns_plat_pcie_shutdown, + }; +-builtin_platform_driver(cdns_plat_pcie_driver); ++module_platform_driver(cdns_plat_pcie_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Cadence PCIe controller platform driver"); +diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c +index d614452861f7..fb88a7ade412 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence.c ++++ b/drivers/pci/controller/cadence/pcie-cadence.c +@@ -293,6 +293,7 @@ const struct dev_pm_ops cdns_pcie_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, + cdns_pcie_resume_noirq) + }; ++EXPORT_SYMBOL_GPL(cdns_pcie_pm_ops); + + MODULE_LICENSE("GPL"); + MODULE_DESCRIPTION("Cadence PCIe controller driver"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0143-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch b/SPECS/linux-lts/0143-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch deleted file mode 100644 index 127a04cfa3..0000000000 --- a/SPECS/linux-lts/0143-UPSTREAM-irqchip-sifive-plic-Handle-number-of-hardwa.patch +++ /dev/null @@ -1,229 +0,0 @@ -From f5a054d7440d709d61511cb7a4d626b59ba00bf3 Mon Sep 17 00:00:00 2001 -From: Thomas Gleixner -Date: Tue, 3 Feb 2026 20:16:12 +0100 -Subject: [PATCH 143/467] UPSTREAM: irqchip/sifive-plic: Handle number of - hardware interrupts correctly - -The driver is handling the number of hardware interrupts inconsistently. - -The reason is that the firmware enumerates the maximum number of device -interrupts, but the actual number of hardware interrupts is one more -because hardware interrupt 0 is reserved. - -There are two loop variants where this matters: - - 1) Iterating over the device interrupts - - for (irq = 1; irq < total_irqs; irq++) - - 2) Iterating over the number of interrupt register groups - - for (grp = 0; grp < irq_groups; grp++) - -The current code stores the number of device interrupts and that requires -to write the loops as: - - 1) for (irq = 1; irq <= device_irqs; irq++) - - 2) for (grp = 0; grp < DIV_ROUND_UP(device_irqs + 1); grp++) - -But the code gets it wrong all over the place. Just fixing up the -conditions and off by ones is not a sustainable solution as the next changes -will reintroduce the same bugs over and over. - -Sanitize it by storing the total number of hardware interrupts during probe -and precalculating the number of groups. To future proof it mark -priv::total_irqs __private, provide a correct iterator macro and adjust the -code to this. - -Marking it private allows sparse (C=1 build) to catch direct access to this -member: - - drivers/irqchip/irq-sifive-plic.c:270:9: warning: dereference of noderef expression - -That should prevent at least the most obvious future damage in that area. - -Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation") -Reported-by: Yangyu Chen -Signed-off-by: Thomas Gleixner -Tested-by: Yangyu Chen -Link: https://patch.msgid.link/87ikcd36i9.ffs@tglx -(cherry picked from commit 42e025b719c128bdf8ff88584589a1e4a2448c81) -Signed-off-by: Han Gao ---- - drivers/irqchip/irq-sifive-plic.c | 82 +++++++++++++++++-------------- - 1 file changed, 45 insertions(+), 37 deletions(-) - -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index 53e446117599..f255fa044764 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -68,15 +68,17 @@ - #define PLIC_QUIRK_CP100_CLAIM_REGISTER_ERRATUM 1 - - struct plic_priv { -- struct fwnode_handle *fwnode; -- struct cpumask lmask; -- struct irq_domain *irqdomain; -- void __iomem *regs; -- unsigned long plic_quirks; -- unsigned int nr_irqs; -- unsigned long *prio_save; -- u32 gsi_base; -- int acpi_plic_id; -+ struct fwnode_handle *fwnode; -+ struct cpumask lmask; -+ struct irq_domain *irqdomain; -+ void __iomem *regs; -+ unsigned long plic_quirks; -+ /* device interrupts + 1 to compensate for the reserved hwirq 0 */ -+ unsigned int __private total_irqs; -+ unsigned int irq_groups; -+ unsigned long *prio_save; -+ u32 gsi_base; -+ int acpi_plic_id; - }; - - struct plic_handler { -@@ -91,6 +93,12 @@ struct plic_handler { - u32 *enable_save; - struct plic_priv *priv; - }; -+ -+/* -+ * Macro to deal with the insanity of hardware interrupt 0 being reserved */ -+#define for_each_device_irq(iter, priv) \ -+ for (unsigned int iter = 1; iter < ACCESS_PRIVATE(priv, total_irqs); iter++) -+ - static int plic_parent_irq __ro_after_init; - static bool plic_global_setup_done __ro_after_init; - static DEFINE_PER_CPU(struct plic_handler, plic_handlers); -@@ -262,14 +270,11 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type) - - static int plic_irq_suspend(void) - { -- struct plic_priv *priv; -- -- priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; -+ struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; - -- /* irq ID 0 is reserved */ -- for (unsigned int i = 1; i < priv->nr_irqs; i++) { -- __assign_bit(i, priv->prio_save, -- readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID)); -+ for_each_device_irq(irq, priv) { -+ __assign_bit(irq, priv->prio_save, -+ readl(priv->regs + PRIORITY_BASE + irq * PRIORITY_PER_ID)); - } - - return 0; -@@ -277,18 +282,15 @@ static int plic_irq_suspend(void) - - static void plic_irq_resume(void) - { -- unsigned int i, index, cpu; -+ struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; -+ unsigned int index, cpu; - unsigned long flags; - u32 __iomem *reg; -- struct plic_priv *priv; -- -- priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; - -- /* irq ID 0 is reserved */ -- for (i = 1; i < priv->nr_irqs; i++) { -- index = BIT_WORD(i); -- writel((priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0, -- priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID); -+ for_each_device_irq(irq, priv) { -+ index = BIT_WORD(irq); -+ writel((priv->prio_save[index] & BIT_MASK(irq)) ? 1 : 0, -+ priv->regs + PRIORITY_BASE + irq * PRIORITY_PER_ID); - } - - for_each_present_cpu(cpu) { -@@ -298,7 +300,7 @@ static void plic_irq_resume(void) - continue; - - raw_spin_lock_irqsave(&handler->enable_lock, flags); -- for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { -+ for (unsigned int i = 0; i < priv->irq_groups; i++) { - reg = handler->enable_base + i * sizeof(u32); - writel(handler->enable_save[i], reg); - } -@@ -432,7 +434,7 @@ static u32 cp100_isolate_pending_irq(int nr_irq_groups, struct plic_handler *han - - static irq_hw_number_t cp100_get_hwirq(struct plic_handler *handler, void __iomem *claim) - { -- int nr_irq_groups = DIV_ROUND_UP(handler->priv->nr_irqs, 32); -+ int nr_irq_groups = handler->priv->irq_groups; - u32 __iomem *enable = handler->enable_base; - irq_hw_number_t hwirq = 0; - u32 iso_mask; -@@ -615,7 +617,6 @@ static int plic_probe(struct fwnode_handle *fwnode) - struct plic_handler *handler; - u32 nr_irqs, parent_hwirq; - struct plic_priv *priv; -- irq_hw_number_t hwirq; - void __iomem *regs; - int id, context_id; - u32 gsi_base; -@@ -648,7 +649,16 @@ static int plic_probe(struct fwnode_handle *fwnode) - - priv->fwnode = fwnode; - priv->plic_quirks = plic_quirks; -- priv->nr_irqs = nr_irqs; -+ /* -+ * The firmware provides the number of device interrupts. As -+ * hardware interrupt 0 is reserved, the number of total interrupts -+ * is nr_irqs + 1. -+ */ -+ nr_irqs++; -+ ACCESS_PRIVATE(priv, total_irqs) = nr_irqs; -+ /* Precalculate the number of register groups */ -+ priv->irq_groups = DIV_ROUND_UP(nr_irqs, 32); -+ - priv->regs = regs; - priv->gsi_base = gsi_base; - priv->acpi_plic_id = id; -@@ -687,7 +697,7 @@ static int plic_probe(struct fwnode_handle *fwnode) - u32 __iomem *enable_base = priv->regs + CONTEXT_ENABLE_BASE + - i * CONTEXT_ENABLE_SIZE; - -- for (int j = 0; j <= nr_irqs / 32; j++) -+ for (int j = 0; j < priv->irq_groups; j++) - writel(0, enable_base + j); - } - continue; -@@ -719,23 +729,21 @@ static int plic_probe(struct fwnode_handle *fwnode) - context_id * CONTEXT_ENABLE_SIZE; - handler->priv = priv; - -- handler->enable_save = kcalloc(DIV_ROUND_UP(nr_irqs, 32), -- sizeof(*handler->enable_save), GFP_KERNEL); -+ handler->enable_save = kcalloc(priv->irq_groups, sizeof(*handler->enable_save), -+ GFP_KERNEL); - if (!handler->enable_save) { - error = -ENOMEM; - goto fail_cleanup_contexts; - } - done: -- for (hwirq = 1; hwirq <= nr_irqs; hwirq++) { -+ for_each_device_irq(hwirq, priv) { - plic_toggle(handler, hwirq, 0); -- writel(1, priv->regs + PRIORITY_BASE + -- hwirq * PRIORITY_PER_ID); -+ writel(1, priv->regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID); - } - nr_handlers++; - } - -- priv->irqdomain = irq_domain_create_linear(fwnode, nr_irqs + 1, -- &plic_irqdomain_ops, priv); -+ priv->irqdomain = irq_domain_create_linear(fwnode, nr_irqs, &plic_irqdomain_ops, priv); - if (WARN_ON(!priv->irqdomain)) { - error = -ENOMEM; - goto fail_cleanup_contexts; --- -2.53.0 - diff --git a/SPECS/linux-lts/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch b/SPECS/linux-lts/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch new file mode 100644 index 0000000000..53a32a761a --- /dev/null +++ b/SPECS/linux-lts/0144-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch @@ -0,0 +1,508 @@ +From 3918539e5418b2d1151b2a2e086601ded67796a3 Mon Sep 17 00:00:00 2001 +From: Manikandan K Pillai +Date: Sat, 8 Nov 2025 22:02:57 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Split PCIe controller header + file + +Split the Cadence PCIe header file by moving the Legacy (LGA) controller +register definitions to a separate header file for support of next +generation PCIe controller architecture. + +Signed-off-by: Manikandan K Pillai +Signed-off-by: Manivannan Sadhasivam +Link: https://patch.msgid.link/20251108140305.1120117-3-hans.zhang@cixtech.com +(cherry picked from commit 3977be25f5fd973cad6bed810ac1045ba8cfbfa6) +Signed-off-by: Han Gao +--- + .../cadence/pcie-cadence-lga-regs.h | 230 ++++++++++++++++++ + drivers/pci/controller/cadence/pcie-cadence.h | 222 +---------------- + 2 files changed, 232 insertions(+), 220 deletions(-) + create mode 100644 drivers/pci/controller/cadence/pcie-cadence-lga-regs.h + +diff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h +new file mode 100644 +index 000000000000..857b2140c5d2 +--- /dev/null ++++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h +@@ -0,0 +1,230 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Cadence PCIe controller driver. ++ * ++ * Copyright (c) 2017 Cadence ++ * Author: Cyrille Pitchen ++ */ ++#ifndef _PCIE_CADENCE_LGA_REGS_H ++#define _PCIE_CADENCE_LGA_REGS_H ++ ++#include ++ ++/* Parameters for the waiting for link up routine */ ++#define LINK_WAIT_MAX_RETRIES 10 ++#define LINK_WAIT_USLEEP_MIN 90000 ++#define LINK_WAIT_USLEEP_MAX 100000 ++ ++/* Local Management Registers */ ++#define CDNS_PCIE_LM_BASE 0x00100000 ++ ++/* Vendor ID Register */ ++#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) ++#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) ++#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 ++#define CDNS_PCIE_LM_ID_VENDOR(vid) \ ++ (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) ++#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) ++#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 ++#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ ++ (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) ++ ++/* Root Port Requester ID Register */ ++#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) ++#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) ++#define CDNS_PCIE_LM_RP_RID_SHIFT 0 ++#define CDNS_PCIE_LM_RP_RID_(rid) \ ++ (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) ++ ++/* Endpoint Bus and Device Number Register */ ++#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022C) ++#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) ++#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 ++#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) ++#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 ++ ++/* Endpoint Function f BAR b Configuration Registers */ ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ ++ (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn)) ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ ++ (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ ++ (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) ++#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ ++ (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn)) ++#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ ++ (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) ++#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ ++ (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ ++ (GENMASK(4, 0) << ((b) * 8)) ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ ++ (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ ++ (GENMASK(7, 5) << ((b) * 8)) ++#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ ++ (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) ++ ++/* Endpoint Function Configuration Register */ ++#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02C0) ++ ++/* Root Complex BAR Configuration Register */ ++#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ ++ (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ ++ (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ ++ (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) ++#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ ++ (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) ++#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) ++#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 ++#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) ++#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) ++#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 ++#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) ++#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) ++ ++/* BAR control values applicable to both Endpoint Function and Root Complex */ ++#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 ++#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 ++#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 ++#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 ++#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 ++#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 ++ ++#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ ++ (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) ++#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ ++ (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) ++#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ ++ (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) ++#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ ++ (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) ++#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ ++ (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) ++#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ ++ (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) ++#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ ++ (((aperture) - 2) << ((bar) * 8)) ++ ++/* PTM Control Register */ ++#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0DA8) ++#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) ++ ++/* ++ * Endpoint Function Registers (PCI configuration space for endpoint functions) ++ */ ++#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) ++ ++#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 ++#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xB0 ++#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xC0 ++#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 ++ ++/* Endpoint PF Registers */ ++#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) ++#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) ++ ++/* Root Port Registers (PCI configuration space for the root port function) */ ++#define CDNS_PCIE_RP_BASE 0x00200000 ++#define CDNS_PCIE_RP_CAP_OFFSET 0xC0 ++ ++/* Address Translation Registers */ ++#define CDNS_PCIE_AT_BASE 0x00400000 ++ ++/* Region r Outbound AXI to PCIe Address Translation Register 0 */ ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ ++ (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1F) * 0x0020) ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ ++ (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ ++ (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ ++ (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) ++ ++/* Region r Outbound AXI to PCIe Address Translation Register 1 */ ++#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ ++ (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1F) * 0x0020) ++ ++/* Region r Outbound PCIe Descriptor Register 0 */ ++#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ ++ (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1F) * 0x0020) ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xA ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xB ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xC ++#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xD ++/* Bit 23 MUST be set in RC mode. */ ++#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) ++#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) ++#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ ++ (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) ++ ++/* Region r Outbound PCIe Descriptor Register 1 */ ++#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ ++ (CDNS_PCIE_AT_BASE + 0x000C + ((r) & 0x1F) * 0x0020) ++#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) ++#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ ++ ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) ++ ++/* Region r AXI Region Base Address Register 0 */ ++#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ ++ (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1F) * 0x0020) ++#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) ++#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ ++ (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) ++ ++/* Region r AXI Region Base Address Register 1 */ ++#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ ++ (CDNS_PCIE_AT_BASE + 0x001C + ((r) & 0x1F) * 0x0020) ++ ++/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ ++#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ ++ (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) ++#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) ++#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ ++ (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) ++#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ ++ (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) ++ ++/* AXI link down register */ ++#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) ++ ++/* LTSSM Capabilities register */ ++#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) ++#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) ++#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 ++#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ ++ (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ ++ CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) ++ ++#define CDNS_PCIE_RP_MAX_IB 0x3 ++#define CDNS_PCIE_MAX_OB 32 ++ ++/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ ++#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ ++ (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) ++#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ ++ (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) ++ ++/* Normal/Vendor specific message access: offset inside some outbound region */ ++#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) ++#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ ++ (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) ++#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) ++#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ ++ (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) ++#define CDNS_PCIE_MSG_NO_DATA BIT(16) ++ ++#endif /* _PCIE_CADENCE_LGA_REGS_H */ +diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h +index 23ccad0a31f2..23aa64df1980 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence.h ++++ b/drivers/pci/controller/cadence/pcie-cadence.h +@@ -7,211 +7,11 @@ + #define _PCIE_CADENCE_H + + #include ++#include + #include + #include + #include +- +-/* Parameters for the waiting for link up routine */ +-#define LINK_WAIT_MAX_RETRIES 10 +-#define LINK_WAIT_USLEEP_MIN 90000 +-#define LINK_WAIT_USLEEP_MAX 100000 +- +-/* +- * Local Management Registers +- */ +-#define CDNS_PCIE_LM_BASE 0x00100000 +- +-/* Vendor ID Register */ +-#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) +-#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) +-#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 +-#define CDNS_PCIE_LM_ID_VENDOR(vid) \ +- (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) +-#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) +-#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 +-#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ +- (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) +- +-/* Root Port Requester ID Register */ +-#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) +-#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) +-#define CDNS_PCIE_LM_RP_RID_SHIFT 0 +-#define CDNS_PCIE_LM_RP_RID_(rid) \ +- (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) +- +-/* Endpoint Bus and Device Number Register */ +-#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) +-#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) +-#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 +-#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) +-#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 +- +-/* Endpoint Function f BAR b Configuration Registers */ +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ +- (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn)) +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ +- (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ +- (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) +-#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ +- (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn)) +-#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ +- (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) +-#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ +- (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ +- (GENMASK(4, 0) << ((b) * 8)) +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ +- (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ +- (GENMASK(7, 5) << ((b) * 8)) +-#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ +- (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) +- +-/* Endpoint Function Configuration Register */ +-#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) +- +-/* Root Complex BAR Configuration Register */ +-#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ +- (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ +- (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ +- (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) +-#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ +- (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) +-#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) +-#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 +-#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) +-#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) +-#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 +-#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) +-#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) +- +-/* BAR control values applicable to both Endpoint Function and Root Complex */ +-#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 +-#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 +-#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 +-#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 +-#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 +-#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 +- +-#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ +- (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) +-#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ +- (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) +-#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ +- (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) +-#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ +- (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) +-#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ +- (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) +-#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ +- (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) +-#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ +- (((aperture) - 2) << ((bar) * 8)) +- +-/* PTM Control Register */ +-#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8) +-#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) +- +-/* +- * Endpoint Function Registers (PCI configuration space for endpoint functions) +- */ +-#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) +- +-/* +- * Endpoint PF Registers +- */ +-#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) +-#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) +- +-/* +- * Root Port Registers (PCI configuration space for the root port function) +- */ +-#define CDNS_PCIE_RP_BASE 0x00200000 +-#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 +- +-/* +- * Address Translation Registers +- */ +-#define CDNS_PCIE_AT_BASE 0x00400000 +- +-/* Region r Outbound AXI to PCIe Address Translation Register 0 */ +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ +- (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ +- (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ +- (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ +- (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) +- +-/* Region r Outbound AXI to PCIe Address Translation Register 1 */ +-#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ +- (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) +- +-/* Region r Outbound PCIe Descriptor Register 0 */ +-#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ +- (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc +-#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd +-/* Bit 23 MUST be set in RC mode. */ +-#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) +-#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) +-#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ +- (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) +- +-/* Region r Outbound PCIe Descriptor Register 1 */ +-#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ +- (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) +-#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) +-#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ +- ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) +- +-/* Region r AXI Region Base Address Register 0 */ +-#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ +- (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) +-#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) +-#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ +- (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) +- +-/* Region r AXI Region Base Address Register 1 */ +-#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ +- (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) +- +-/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ +-#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ +- (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) +-#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) +-#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ +- (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) +-#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ +- (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) +- +-/* AXI link down register */ +-#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) +- +-/* LTSSM Capabilities register */ +-#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) +-#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) +-#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 +-#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ +- (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ +- CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) ++#include "pcie-cadence-lga-regs.h" + + enum cdns_pcie_rp_bar { + RP_BAR_UNDEFINED = -1, +@@ -220,29 +20,11 @@ enum cdns_pcie_rp_bar { + RP_NO_BAR + }; + +-#define CDNS_PCIE_RP_MAX_IB 0x3 +-#define CDNS_PCIE_MAX_OB 32 +- + struct cdns_pcie_rp_ib_bar { + u64 size; + bool free; + }; + +-/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ +-#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ +- (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) +-#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ +- (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) +- +-/* Normal/Vendor specific message access: offset inside some outbound region */ +-#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) +-#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ +- (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) +-#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) +-#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ +- (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) +-#define CDNS_PCIE_MSG_DATA BIT(16) +- + struct cdns_pcie; + + struct cdns_pcie_ops { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0144-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch b/SPECS/linux-lts/0144-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch deleted file mode 100644 index eedd218a03..0000000000 --- a/SPECS/linux-lts/0144-UPSTREAM-PCI-dwc-Use-multiple-iATU-windows-for-mappi.patch +++ /dev/null @@ -1,145 +0,0 @@ -From 24b2064ff98e5d2c22d87bc0a86ee411e19fa6bb Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 9 Jan 2026 19:34:30 +0800 -Subject: [PATCH 144/467] UPSTREAM: PCI: dwc: Use multiple iATU windows for - mapping large bridge windows and DMA ranges - -The DWC driver tries to use a single iATU region for mapping the individual -entries of the bridge window and DMA range. If a bridge window/DMA range is -larger than the iATU inbound/outbound window size, then the mapping will -fail. - -Hence, avoid this failure by using multiple iATU windows to map the whole -region. If the region runs out of iATU windows, then return failure. - -Signed-off-by: Charles Mirabile -Signed-off-by: Samuel Holland -Co-developed-by: Randolph Lin -Signed-off-by: Randolph Lin -[mani: reworded description, minor code cleanup] -Signed-off-by: Manivannan Sadhasivam -Reviewed-by: Niklas Cassel -Reviewed-by: Frank Li -Acked-by: Charles Mirabile -Link: https://patch.msgid.link/20260109113430.2767264-1-randolph@andestech.com -(cherry picked from commit e9a5415adb209f86a05e55b850127ada82e070f1) -Signed-off-by: Han Gao ---- - .../pci/controller/dwc/pcie-designware-host.c | 74 ++++++++++++++----- - 1 file changed, 57 insertions(+), 17 deletions(-) - -diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c -index 48e4a887bb1b..993858fd0529 100644 ---- a/drivers/pci/controller/dwc/pcie-designware-host.c -+++ b/drivers/pci/controller/dwc/pcie-designware-host.c -@@ -887,29 +887,50 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) - - i = 0; - resource_list_for_each_entry(entry, &pp->bridge->windows) { -+ resource_size_t res_size; -+ - if (resource_type(entry->res) != IORESOURCE_MEM) - continue; - -- if (pci->num_ob_windows <= ++i) -+ if (pci->num_ob_windows <= i + 1) - break; - -- atu.index = i; - atu.type = PCIE_ATU_TYPE_MEM; - atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset; - atu.pci_addr = entry->res->start - entry->offset; - - /* Adjust iATU size if MSG TLP region was allocated before */ - if (pp->msg_res && pp->msg_res->parent == entry->res) -- atu.size = resource_size(entry->res) - -+ res_size = resource_size(entry->res) - - resource_size(pp->msg_res); - else -- atu.size = resource_size(entry->res); -+ res_size = resource_size(entry->res); -+ -+ while (res_size > 0) { -+ /* -+ * Return failure if we run out of windows in the -+ * middle. Otherwise, we would end up only partially -+ * mapping a single resource. -+ */ -+ if (pci->num_ob_windows <= ++i) { -+ dev_err(pci->dev, "Exhausted outbound windows for region: %pr\n", -+ entry->res); -+ return -ENOMEM; -+ } - -- ret = dw_pcie_prog_outbound_atu(pci, &atu); -- if (ret) { -- dev_err(pci->dev, "Failed to set MEM range %pr\n", -- entry->res); -- return ret; -+ atu.index = i; -+ atu.size = MIN(pci->region_limit + 1, res_size); -+ -+ ret = dw_pcie_prog_outbound_atu(pci, &atu); -+ if (ret) { -+ dev_err(pci->dev, "Failed to set MEM range %pr\n", -+ entry->res); -+ return ret; -+ } -+ -+ atu.parent_bus_addr += atu.size; -+ atu.pci_addr += atu.size; -+ res_size -= atu.size; - } - } - -@@ -947,20 +968,39 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) - - i = 0; - resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { -+ resource_size_t res_start, res_size, window_size; -+ - if (resource_type(entry->res) != IORESOURCE_MEM) - continue; - - if (pci->num_ib_windows <= i) - break; - -- ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, -- entry->res->start, -- entry->res->start - entry->offset, -- resource_size(entry->res)); -- if (ret) { -- dev_err(pci->dev, "Failed to set DMA range %pr\n", -- entry->res); -- return ret; -+ res_size = resource_size(entry->res); -+ res_start = entry->res->start; -+ while (res_size > 0) { -+ /* -+ * Return failure if we run out of windows in the -+ * middle. Otherwise, we would end up only partially -+ * mapping a single resource. -+ */ -+ if (pci->num_ib_windows <= i) { -+ dev_err(pci->dev, "Exhausted inbound windows for region: %pr\n", -+ entry->res); -+ return -ENOMEM; -+ } -+ -+ window_size = MIN(pci->region_limit + 1, res_size); -+ ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, res_start, -+ res_start - entry->offset, window_size); -+ if (ret) { -+ dev_err(pci->dev, "Failed to set DMA range %pr\n", -+ entry->res); -+ return ret; -+ } -+ -+ res_start += window_size; -+ res_size -= window_size; - } - } - --- -2.53.0 - diff --git a/SPECS/linux-lts/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch b/SPECS/linux-lts/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch new file mode 100644 index 0000000000..666272aa6c --- /dev/null +++ b/SPECS/linux-lts/0145-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch @@ -0,0 +1,731 @@ +From 4fb7d19f2e7e5112722787c8f89b8ca56f6943be Mon Sep 17 00:00:00 2001 +From: Manikandan K Pillai +Date: Sat, 8 Nov 2025 22:02:58 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Move PCIe RP common functions to + a separate file + +Move the Cadence PCIe controller RP common functions into a separate file. +The common library functions are split from legacy PCIe RP controller +functions to a separate file. + +Signed-off-by: Manikandan K Pillai +[mani: removed the unused variable] +Signed-off-by: Manivannan Sadhasivam +Link: https://patch.msgid.link/20251108140305.1120117-4-hans.zhang@cixtech.com +(cherry picked from commit b80a7b4713c967479752ea4801eb1d1933093f58) +Signed-off-by: Han Gao +--- + drivers/pci/controller/cadence/Makefile | 10 +- + .../cadence/pcie-cadence-host-common.c | 288 ++++++++++++++++++ + .../cadence/pcie-cadence-host-common.h | 46 +++ + .../controller/cadence/pcie-cadence-host.c | 278 +---------------- + 4 files changed, 349 insertions(+), 273 deletions(-) + create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common.c + create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common.h + +diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile +index 5e23f8539ecc..91ffdbfd3aaa 100644 +--- a/drivers/pci/controller/cadence/Makefile ++++ b/drivers/pci/controller/cadence/Makefile +@@ -1,7 +1,11 @@ + # SPDX-License-Identifier: GPL-2.0 +-obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o +-obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o +-obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o ++pcie-cadence-mod-y := pcie-cadence.o ++pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o ++pcie-cadence-ep-mod-y := pcie-cadence-ep.o ++ ++obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o ++obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o ++obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o + obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o + obj-$(CONFIG_PCI_J721E) += pci-j721e.o + obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o +diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c +new file mode 100644 +index 000000000000..15415d7f35ee +--- /dev/null ++++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c +@@ -0,0 +1,288 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Cadence PCIe host controller library. ++ * ++ * Copyright (c) 2017 Cadence ++ * Author: Cyrille Pitchen ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-cadence.h" ++#include "pcie-cadence-host-common.h" ++ ++#define LINK_RETRAIN_TIMEOUT HZ ++ ++u64 bar_max_size[] = { ++ [RP_BAR0] = _ULL(128 * SZ_2G), ++ [RP_BAR1] = SZ_2G, ++ [RP_NO_BAR] = _BITULL(63), ++}; ++EXPORT_SYMBOL_GPL(bar_max_size); ++ ++int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) ++{ ++ u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; ++ unsigned long end_jiffies; ++ u16 lnk_stat; ++ ++ /* Wait for link training to complete. Exit after timeout. */ ++ end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; ++ do { ++ lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); ++ if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) ++ break; ++ usleep_range(0, 1000); ++ } while (time_before(jiffies, end_jiffies)); ++ ++ if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) ++ return 0; ++ ++ return -ETIMEDOUT; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_host_training_complete); ++ ++int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie, ++ cdns_pcie_linkup_func pcie_link_up) ++{ ++ struct device *dev = pcie->dev; ++ int retries; ++ ++ /* Check if the link is up or not */ ++ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { ++ if (pcie_link_up(pcie)) { ++ dev_info(dev, "Link up\n"); ++ return 0; ++ } ++ usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); ++ } ++ ++ return -ETIMEDOUT; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_host_wait_for_link); ++ ++int cdns_pcie_retrain(struct cdns_pcie *pcie, ++ cdns_pcie_linkup_func pcie_link_up) ++{ ++ u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; ++ u16 lnk_stat, lnk_ctl; ++ int ret = 0; ++ ++ /* ++ * Set retrain bit if current speed is 2.5 GB/s, ++ * but the PCIe root port support is > 2.5 GB/s. ++ */ ++ ++ lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + ++ PCI_EXP_LNKCAP)); ++ if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) ++ return ret; ++ ++ lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); ++ if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { ++ lnk_ctl = cdns_pcie_rp_readw(pcie, ++ pcie_cap_off + PCI_EXP_LNKCTL); ++ lnk_ctl |= PCI_EXP_LNKCTL_RL; ++ cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, ++ lnk_ctl); ++ ++ ret = cdns_pcie_host_training_complete(pcie); ++ if (ret) ++ return ret; ++ ++ ret = cdns_pcie_host_wait_for_link(pcie, pcie_link_up); ++ } ++ return ret; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_retrain); ++ ++int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, ++ cdns_pcie_linkup_func pcie_link_up) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ int ret; ++ ++ ret = cdns_pcie_host_wait_for_link(pcie, pcie_link_up); ++ ++ /* ++ * Retrain link for Gen2 training defect ++ * if quirk flag is set. ++ */ ++ if (!ret && rc->quirk_retrain_flag) ++ ret = cdns_pcie_retrain(pcie, pcie_link_up); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link); ++ ++enum cdns_pcie_rp_bar ++cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) ++{ ++ enum cdns_pcie_rp_bar bar, sel_bar; ++ ++ sel_bar = RP_BAR_UNDEFINED; ++ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { ++ if (!rc->avail_ib_bar[bar]) ++ continue; ++ ++ if (size <= bar_max_size[bar]) { ++ if (sel_bar == RP_BAR_UNDEFINED) { ++ sel_bar = bar; ++ continue; ++ } ++ ++ if (bar_max_size[bar] < bar_max_size[sel_bar]) ++ sel_bar = bar; ++ } ++ } ++ ++ return sel_bar; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_host_find_min_bar); ++ ++enum cdns_pcie_rp_bar ++cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) ++{ ++ enum cdns_pcie_rp_bar bar, sel_bar; ++ ++ sel_bar = RP_BAR_UNDEFINED; ++ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { ++ if (!rc->avail_ib_bar[bar]) ++ continue; ++ ++ if (size >= bar_max_size[bar]) { ++ if (sel_bar == RP_BAR_UNDEFINED) { ++ sel_bar = bar; ++ continue; ++ } ++ ++ if (bar_max_size[bar] > bar_max_size[sel_bar]) ++ sel_bar = bar; ++ } ++ } ++ ++ return sel_bar; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_host_find_max_bar); ++ ++int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, ++ const struct list_head *b) ++{ ++ struct resource_entry *entry1, *entry2; ++ ++ entry1 = container_of(a, struct resource_entry, node); ++ entry2 = container_of(b, struct resource_entry, node); ++ ++ return resource_size(entry2->res) - resource_size(entry1->res); ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_host_dma_ranges_cmp); ++ ++int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, ++ struct resource_entry *entry, ++ cdns_pcie_host_bar_ib_cfg pci_host_ib_config) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ struct device *dev = pcie->dev; ++ u64 cpu_addr, size, winsize; ++ enum cdns_pcie_rp_bar bar; ++ unsigned long flags; ++ int ret; ++ ++ cpu_addr = entry->res->start; ++ flags = entry->res->flags; ++ size = resource_size(entry->res); ++ ++ while (size > 0) { ++ /* ++ * Try to find a minimum BAR whose size is greater than ++ * or equal to the remaining resource_entry size. This will ++ * fail if the size of each of the available BARs is less than ++ * the remaining resource_entry size. ++ * ++ * If a minimum BAR is found, IB ATU will be configured and ++ * exited. ++ */ ++ bar = cdns_pcie_host_find_min_bar(rc, size); ++ if (bar != RP_BAR_UNDEFINED) { ++ ret = pci_host_ib_config(rc, bar, cpu_addr, size, flags); ++ if (ret) ++ dev_err(dev, "IB BAR: %d config failed\n", bar); ++ return ret; ++ } ++ ++ /* ++ * If the control reaches here, it would mean the remaining ++ * resource_entry size cannot be fitted in a single BAR. So we ++ * find a maximum BAR whose size is less than or equal to the ++ * remaining resource_entry size and split the resource entry ++ * so that part of resource entry is fitted inside the maximum ++ * BAR. The remaining size would be fitted during the next ++ * iteration of the loop. ++ * ++ * If a maximum BAR is not found, there is no way we can fit ++ * this resource_entry, so we error out. ++ */ ++ bar = cdns_pcie_host_find_max_bar(rc, size); ++ if (bar == RP_BAR_UNDEFINED) { ++ dev_err(dev, "No free BAR to map cpu_addr %llx\n", ++ cpu_addr); ++ return -EINVAL; ++ } ++ ++ winsize = bar_max_size[bar]; ++ ret = pci_host_ib_config(rc, bar, cpu_addr, winsize, flags); ++ if (ret) { ++ dev_err(dev, "IB BAR: %d config failed\n", bar); ++ return ret; ++ } ++ ++ size -= winsize; ++ cpu_addr += winsize; ++ } ++ ++ return 0; ++} ++ ++int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc, ++ cdns_pcie_host_bar_ib_cfg pci_host_ib_config) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ struct device *dev = pcie->dev; ++ struct device_node *np = dev->of_node; ++ struct pci_host_bridge *bridge; ++ struct resource_entry *entry; ++ u32 no_bar_nbits = 32; ++ int err; ++ ++ bridge = pci_host_bridge_from_priv(rc); ++ if (!bridge) ++ return -ENOMEM; ++ ++ if (list_empty(&bridge->dma_ranges)) { ++ of_property_read_u32(np, "cdns,no-bar-match-nbits", ++ &no_bar_nbits); ++ err = pci_host_ib_config(rc, RP_NO_BAR, 0x0, (u64)1 << no_bar_nbits, 0); ++ if (err) ++ dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); ++ return err; ++ } ++ ++ list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); ++ ++ resource_list_for_each_entry(entry, &bridge->dma_ranges) { ++ err = cdns_pcie_host_bar_config(rc, entry, pci_host_ib_config); ++ if (err) { ++ dev_err(dev, "Fail to configure IB using dma-ranges\n"); ++ return err; ++ } ++ } ++ ++ return 0; ++} ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Cadence PCIe host controller driver"); +diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.h b/drivers/pci/controller/cadence/pcie-cadence-host-common.h +new file mode 100644 +index 000000000000..fe7d4202a8b6 +--- /dev/null ++++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.h +@@ -0,0 +1,46 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Cadence PCIe Host controller driver. ++ * ++ * Copyright (c) 2017 Cadence ++ * Author: Cyrille Pitchen ++ */ ++#ifndef _PCIE_CADENCE_HOST_COMMON_H ++#define _PCIE_CADENCE_HOST_COMMON_H ++ ++#include ++#include ++ ++extern u64 bar_max_size[]; ++ ++typedef int (*cdns_pcie_host_bar_ib_cfg)(struct cdns_pcie_rc *, ++ enum cdns_pcie_rp_bar, ++ u64, ++ u64, ++ unsigned long); ++typedef bool (*cdns_pcie_linkup_func)(struct cdns_pcie *); ++ ++int cdns_pcie_host_training_complete(struct cdns_pcie *pcie); ++int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie, ++ cdns_pcie_linkup_func pcie_link_up); ++int cdns_pcie_retrain(struct cdns_pcie *pcie, cdns_pcie_linkup_func pcie_linkup_func); ++int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, ++ cdns_pcie_linkup_func pcie_link_up); ++enum cdns_pcie_rp_bar ++cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size); ++enum cdns_pcie_rp_bar ++cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size); ++int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, ++ const struct list_head *b); ++int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, ++ enum cdns_pcie_rp_bar bar, ++ u64 cpu_addr, ++ u64 size, ++ unsigned long flags); ++int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, ++ struct resource_entry *entry, ++ cdns_pcie_host_bar_ib_cfg pci_host_ib_config); ++int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc, ++ cdns_pcie_host_bar_ib_cfg pci_host_ib_config); ++ ++#endif /* _PCIE_CADENCE_HOST_COMMON_H */ +diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c +index fffd63d6665e..db3154c1eccb 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence-host.c ++++ b/drivers/pci/controller/cadence/pcie-cadence-host.c +@@ -12,14 +12,7 @@ + #include + + #include "pcie-cadence.h" +- +-#define LINK_RETRAIN_TIMEOUT HZ +- +-static u64 bar_max_size[] = { +- [RP_BAR0] = _ULL(128 * SZ_2G), +- [RP_BAR1] = SZ_2G, +- [RP_NO_BAR] = _BITULL(63), +-}; ++#include "pcie-cadence-host-common.h" + + static u8 bar_aperture_mask[] = { + [RP_BAR0] = 0x1F, +@@ -81,77 +74,6 @@ static struct pci_ops cdns_pcie_host_ops = { + .write = pci_generic_config_write, + }; + +-static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) +-{ +- u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; +- unsigned long end_jiffies; +- u16 lnk_stat; +- +- /* Wait for link training to complete. Exit after timeout. */ +- end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; +- do { +- lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); +- if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) +- break; +- usleep_range(0, 1000); +- } while (time_before(jiffies, end_jiffies)); +- +- if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) +- return 0; +- +- return -ETIMEDOUT; +-} +- +-static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +-{ +- struct device *dev = pcie->dev; +- int retries; +- +- /* Check if the link is up or not */ +- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { +- if (cdns_pcie_link_up(pcie)) { +- dev_info(dev, "Link up\n"); +- return 0; +- } +- usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); +- } +- +- return -ETIMEDOUT; +-} +- +-static int cdns_pcie_retrain(struct cdns_pcie *pcie) +-{ +- u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; +- u16 lnk_stat, lnk_ctl; +- int ret = 0; +- +- /* +- * Set retrain bit if current speed is 2.5 GB/s, +- * but the PCIe root port support is > 2.5 GB/s. +- */ +- +- lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + +- PCI_EXP_LNKCAP)); +- if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) +- return ret; +- +- lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); +- if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { +- lnk_ctl = cdns_pcie_rp_readw(pcie, +- pcie_cap_off + PCI_EXP_LNKCTL); +- lnk_ctl |= PCI_EXP_LNKCTL_RL; +- cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, +- lnk_ctl); +- +- ret = cdns_pcie_host_training_complete(pcie); +- if (ret) +- return ret; +- +- ret = cdns_pcie_host_wait_for_link(pcie); +- } +- return ret; +-} +- + static void cdns_pcie_host_disable_ptm_response(struct cdns_pcie *pcie) + { + u32 val; +@@ -168,23 +90,6 @@ static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie) + cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN); + } + +-static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) +-{ +- struct cdns_pcie *pcie = &rc->pcie; +- int ret; +- +- ret = cdns_pcie_host_wait_for_link(pcie); +- +- /* +- * Retrain link for Gen2 training defect +- * if quirk flag is set. +- */ +- if (!ret && rc->quirk_retrain_flag) +- ret = cdns_pcie_retrain(pcie); +- +- return ret; +-} +- + static void cdns_pcie_host_deinit_root_port(struct cdns_pcie_rc *rc) + { + struct cdns_pcie *pcie = &rc->pcie; +@@ -245,10 +150,11 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) + return 0; + } + +-static int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, +- enum cdns_pcie_rp_bar bar, +- u64 cpu_addr, u64 size, +- unsigned long flags) ++int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, ++ enum cdns_pcie_rp_bar bar, ++ u64 cpu_addr, ++ u64 size, ++ unsigned long flags) + { + struct cdns_pcie *pcie = &rc->pcie; + u32 addr0, addr1, aperture, value; +@@ -290,137 +196,6 @@ static int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, + return 0; + } + +-static enum cdns_pcie_rp_bar +-cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) +-{ +- enum cdns_pcie_rp_bar bar, sel_bar; +- +- sel_bar = RP_BAR_UNDEFINED; +- for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { +- if (!rc->avail_ib_bar[bar]) +- continue; +- +- if (size <= bar_max_size[bar]) { +- if (sel_bar == RP_BAR_UNDEFINED) { +- sel_bar = bar; +- continue; +- } +- +- if (bar_max_size[bar] < bar_max_size[sel_bar]) +- sel_bar = bar; +- } +- } +- +- return sel_bar; +-} +- +-static enum cdns_pcie_rp_bar +-cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) +-{ +- enum cdns_pcie_rp_bar bar, sel_bar; +- +- sel_bar = RP_BAR_UNDEFINED; +- for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { +- if (!rc->avail_ib_bar[bar]) +- continue; +- +- if (size >= bar_max_size[bar]) { +- if (sel_bar == RP_BAR_UNDEFINED) { +- sel_bar = bar; +- continue; +- } +- +- if (bar_max_size[bar] > bar_max_size[sel_bar]) +- sel_bar = bar; +- } +- } +- +- return sel_bar; +-} +- +-static int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, +- struct resource_entry *entry) +-{ +- u64 cpu_addr, pci_addr, size, winsize; +- struct cdns_pcie *pcie = &rc->pcie; +- struct device *dev = pcie->dev; +- enum cdns_pcie_rp_bar bar; +- unsigned long flags; +- int ret; +- +- cpu_addr = entry->res->start; +- pci_addr = entry->res->start - entry->offset; +- flags = entry->res->flags; +- size = resource_size(entry->res); +- +- if (entry->offset) { +- dev_err(dev, "PCI addr: %llx must be equal to CPU addr: %llx\n", +- pci_addr, cpu_addr); +- return -EINVAL; +- } +- +- while (size > 0) { +- /* +- * Try to find a minimum BAR whose size is greater than +- * or equal to the remaining resource_entry size. This will +- * fail if the size of each of the available BARs is less than +- * the remaining resource_entry size. +- * If a minimum BAR is found, IB ATU will be configured and +- * exited. +- */ +- bar = cdns_pcie_host_find_min_bar(rc, size); +- if (bar != RP_BAR_UNDEFINED) { +- ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, +- size, flags); +- if (ret) +- dev_err(dev, "IB BAR: %d config failed\n", bar); +- return ret; +- } +- +- /* +- * If the control reaches here, it would mean the remaining +- * resource_entry size cannot be fitted in a single BAR. So we +- * find a maximum BAR whose size is less than or equal to the +- * remaining resource_entry size and split the resource entry +- * so that part of resource entry is fitted inside the maximum +- * BAR. The remaining size would be fitted during the next +- * iteration of the loop. +- * If a maximum BAR is not found, there is no way we can fit +- * this resource_entry, so we error out. +- */ +- bar = cdns_pcie_host_find_max_bar(rc, size); +- if (bar == RP_BAR_UNDEFINED) { +- dev_err(dev, "No free BAR to map cpu_addr %llx\n", +- cpu_addr); +- return -EINVAL; +- } +- +- winsize = bar_max_size[bar]; +- ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, winsize, +- flags); +- if (ret) { +- dev_err(dev, "IB BAR: %d config failed\n", bar); +- return ret; +- } +- +- size -= winsize; +- cpu_addr += winsize; +- } +- +- return 0; +-} +- +-static int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, +- const struct list_head *b) +-{ +- struct resource_entry *entry1, *entry2; +- +- entry1 = container_of(a, struct resource_entry, node); +- entry2 = container_of(b, struct resource_entry, node); +- +- return resource_size(entry2->res) - resource_size(entry1->res); +-} +- + static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) + { + struct cdns_pcie *pcie = &rc->pcie; +@@ -447,43 +222,6 @@ static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) + } + } + +-static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc) +-{ +- struct cdns_pcie *pcie = &rc->pcie; +- struct device *dev = pcie->dev; +- struct device_node *np = dev->of_node; +- struct pci_host_bridge *bridge; +- struct resource_entry *entry; +- u32 no_bar_nbits = 32; +- int err; +- +- bridge = pci_host_bridge_from_priv(rc); +- if (!bridge) +- return -ENOMEM; +- +- if (list_empty(&bridge->dma_ranges)) { +- of_property_read_u32(np, "cdns,no-bar-match-nbits", +- &no_bar_nbits); +- err = cdns_pcie_host_bar_ib_config(rc, RP_NO_BAR, 0x0, +- (u64)1 << no_bar_nbits, 0); +- if (err) +- dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); +- return err; +- } +- +- list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); +- +- resource_list_for_each_entry(entry, &bridge->dma_ranges) { +- err = cdns_pcie_host_bar_config(rc, entry); +- if (err) { +- dev_err(dev, "Fail to configure IB using dma-ranges\n"); +- return err; +- } +- } +- +- return 0; +-} +- + static void cdns_pcie_host_deinit_address_translation(struct cdns_pcie_rc *rc) + { + struct cdns_pcie *pcie = &rc->pcie; +@@ -561,7 +299,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) + r++; + } + +- return cdns_pcie_host_map_dma_ranges(rc); ++ return cdns_pcie_host_map_dma_ranges(rc, cdns_pcie_host_bar_ib_config); + } + + static void cdns_pcie_host_deinit(struct cdns_pcie_rc *rc) +@@ -607,7 +345,7 @@ int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) + return ret; + } + +- ret = cdns_pcie_host_start_link(rc); ++ ret = cdns_pcie_host_start_link(rc, cdns_pcie_link_up); + if (ret) + dev_dbg(dev, "PCIe link never came up\n"); + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0145-UPSTREAM-pinctrl-th1520-Fix-typo.patch b/SPECS/linux-lts/0145-UPSTREAM-pinctrl-th1520-Fix-typo.patch deleted file mode 100644 index 84781c827a..0000000000 --- a/SPECS/linux-lts/0145-UPSTREAM-pinctrl-th1520-Fix-typo.patch +++ /dev/null @@ -1,32 +0,0 @@ -From d007ff0d047d973067f05a3f9898c1c1822af330 Mon Sep 17 00:00:00 2001 -From: Thomas Gerner -Date: Tue, 20 Jan 2026 09:59:26 +0100 -Subject: [PATCH 145/467] UPSTREAM: pinctrl: th1520: Fix typo - -This fixes a simple typo in the TH1520 SPI0 for group3 pins: -QSPI0 is misspelled QSPI1. - -Signed-off-by: Thomas Gerner -Signed-off-by: Linus Walleij -(cherry picked from commit 304c3ebcaff36560d76e3030ba0839e629635f47) -Signed-off-by: Han Gao ---- - drivers/pinctrl/pinctrl-th1520.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1520.c -index e641bad6728c..83e9c9f77370 100644 ---- a/drivers/pinctrl/pinctrl-th1520.c -+++ b/drivers/pinctrl/pinctrl-th1520.c -@@ -287,7 +287,7 @@ static const struct pinctrl_pin_desc th1520_group3_pins[] = { - TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0), - TH1520_PAD(6, QSPI0_D1_MISO, QSPI, PWM, I2S, GPIO, ____, ____, 0), - TH1520_PAD(7, QSPI0_D2_WP, QSPI, PWM, I2S, GPIO, ____, ____, 0), -- TH1520_PAD(8, QSPI1_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0), -+ TH1520_PAD(8, QSPI0_D3_HOLD, QSPI, ____, I2S, GPIO, ____, ____, 0), - TH1520_PAD(9, I2C2_SCL, I2C, UART, ____, GPIO, ____, ____, 0), - TH1520_PAD(10, I2C2_SDA, I2C, UART, ____, GPIO, ____, ____, 0), - TH1520_PAD(11, I2C3_SCL, I2C, ____, ____, GPIO, ____, ____, 0), --- -2.53.0 - diff --git a/SPECS/linux-lts/0146-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch b/SPECS/linux-lts/0146-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch deleted file mode 100644 index e1d681e245..0000000000 --- a/SPECS/linux-lts/0146-UPSTREAM-PCI-cadence-Add-module-support-for-platform.patch +++ /dev/null @@ -1,73 +0,0 @@ -From cf8e9527657f4fc6aa823772be5089f8172402c7 Mon Sep 17 00:00:00 2001 -From: Manikandan K Pillai -Date: Sat, 8 Nov 2025 22:02:56 +0800 -Subject: [PATCH 146/467] UPSTREAM: PCI: cadence: Add module support for - platform controller driver - -Add support for building PCI cadence platforms as a module. - -Signed-off-by: Manikandan K Pillai -Signed-off-by: Manivannan Sadhasivam -Link: https://patch.msgid.link/20251108140305.1120117-2-hans.zhang@cixtech.com -(cherry picked from commit 611627a4e5e4af7b96aab4f10d130f6a8a615020) -Signed-off-by: Han Gao ---- - drivers/pci/controller/cadence/Kconfig | 6 +++--- - drivers/pci/controller/cadence/pcie-cadence-plat.c | 5 ++++- - drivers/pci/controller/cadence/pcie-cadence.c | 1 + - 3 files changed, 8 insertions(+), 4 deletions(-) - -diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig -index 02a639e55fd8..0b96499ae354 100644 ---- a/drivers/pci/controller/cadence/Kconfig -+++ b/drivers/pci/controller/cadence/Kconfig -@@ -19,10 +19,10 @@ config PCIE_CADENCE_EP - select PCIE_CADENCE - - config PCIE_CADENCE_PLAT -- bool -+ tristate - - config PCIE_CADENCE_PLAT_HOST -- bool "Cadence platform PCIe controller (host mode)" -+ tristate "Cadence platform PCIe controller (host mode)" - depends on OF - select PCIE_CADENCE_HOST - select PCIE_CADENCE_PLAT -@@ -32,7 +32,7 @@ config PCIE_CADENCE_PLAT_HOST - vendors SoCs. - - config PCIE_CADENCE_PLAT_EP -- bool "Cadence platform PCIe controller (endpoint mode)" -+ tristate "Cadence platform PCIe controller (endpoint mode)" - depends on OF - depends on PCI_ENDPOINT - select PCIE_CADENCE_EP -diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c -index 0456845dabb9..ebd5c3afdfcd 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence-plat.c -+++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c -@@ -177,4 +177,7 @@ static struct platform_driver cdns_plat_pcie_driver = { - .probe = cdns_plat_pcie_probe, - .shutdown = cdns_plat_pcie_shutdown, - }; --builtin_platform_driver(cdns_plat_pcie_driver); -+module_platform_driver(cdns_plat_pcie_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Cadence PCIe controller platform driver"); -diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c -index d614452861f7..fb88a7ade412 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence.c -+++ b/drivers/pci/controller/cadence/pcie-cadence.c -@@ -293,6 +293,7 @@ const struct dev_pm_ops cdns_pcie_pm_ops = { - NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, - cdns_pcie_resume_noirq) - }; -+EXPORT_SYMBOL_GPL(cdns_pcie_pm_ops); - - MODULE_LICENSE("GPL"); - MODULE_DESCRIPTION("Cadence PCIe controller driver"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch b/SPECS/linux-lts/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch new file mode 100644 index 0000000000..c0c607ce23 --- /dev/null +++ b/SPECS/linux-lts/0146-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch @@ -0,0 +1,1127 @@ +From 169a3b6c0054a1a90e9a56316ce2530a6e1d21ad Mon Sep 17 00:00:00 2001 +From: Manikandan K Pillai +Date: Sat, 8 Nov 2025 22:02:59 +0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Add support for High Perf + Architecture (HPA) controller + +Add support for Cadence PCIe RP configuration for High Performance +Architecture (HPA) controllers. The Cadence High Performance controllers +are the latest PCIe controllers that have support for DMA, optional IDE +and updated register set. Add a common library for High Performance +Architecture (HPA) PCIe controllers. + +Signed-off-by: Manikandan K Pillai +Signed-off-by: Manivannan Sadhasivam +[bhelgaas: squash https://lore.kernel.org/r/20251120093518.2760492-1-jiapeng.chong@linux.alibaba.com, +squash https://lore.kernel.org/all/52abaad8-a43e-4e29-93d7-86a3245692c3@cixtech.com/] +Signed-off-by: Bjorn Helgaas +Link: https://patch.msgid.link/20251108140305.1120117-5-hans.zhang@cixtech.com +(cherry picked from commit 8babd8afe58a65c8d3cb9b5a6a8d24d4f93033ab) +Signed-off-by: Han Gao +--- + drivers/pci/controller/cadence/Makefile | 4 +- + .../cadence/pcie-cadence-host-hpa.c | 368 ++++++++++++++++++ + .../cadence/pcie-cadence-hpa-regs.h | 193 +++++++++ + .../pci/controller/cadence/pcie-cadence-hpa.c | 167 ++++++++ + .../controller/cadence/pcie-cadence-plat.c | 4 - + drivers/pci/controller/cadence/pcie-cadence.c | 11 + + drivers/pci/controller/cadence/pcie-cadence.h | 187 ++++++++- + 7 files changed, 913 insertions(+), 21 deletions(-) + create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-hpa.c + create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h + create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa.c + +diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile +index 91ffdbfd3aaa..30189045a166 100644 +--- a/drivers/pci/controller/cadence/Makefile ++++ b/drivers/pci/controller/cadence/Makefile +@@ -1,6 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0 +-pcie-cadence-mod-y := pcie-cadence.o +-pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o ++pcie-cadence-mod-y := pcie-cadence-hpa.o pcie-cadence.o ++pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o pcie-cadence-host-hpa.o + pcie-cadence-ep-mod-y := pcie-cadence-ep.o + + obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o +diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c +new file mode 100644 +index 000000000000..0f540bed58e8 +--- /dev/null ++++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c +@@ -0,0 +1,368 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Cadence PCIe host controller driver. ++ * ++ * Copyright (c) 2024, Cadence Design Systems ++ * Author: Manikandan K Pillai ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-cadence.h" ++#include "pcie-cadence-host-common.h" ++ ++static u8 bar_aperture_mask[] = { ++ [RP_BAR0] = 0x3F, ++ [RP_BAR1] = 0x3F, ++}; ++ ++void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, ++ int where) ++{ ++ struct pci_host_bridge *bridge = pci_find_host_bridge(bus); ++ struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); ++ struct cdns_pcie *pcie = &rc->pcie; ++ unsigned int busn = bus->number; ++ u32 addr0, desc0, desc1, ctrl0; ++ u32 regval; ++ ++ if (pci_is_root_bus(bus)) { ++ /* ++ * Only the root port (devfn == 0) is connected to this bus. ++ * All other PCI devices are behind some bridge hence on another ++ * bus. ++ */ ++ if (devfn) ++ return NULL; ++ ++ return pcie->reg_base + (where & 0xfff); ++ } ++ ++ /* Clear AXI link-down status */ ++ regval = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN, ++ (regval & ~GENMASK(0, 0))); ++ ++ /* Update Output registers for AXI region 0 */ ++ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(12) | ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) | ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(busn); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), addr0); ++ ++ desc1 = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0)); ++ desc1 &= ~CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK; ++ desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); ++ ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; ++ ++ if (busn == bridge->busnr + 1) ++ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0; ++ else ++ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1; ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), desc0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), ctrl0); ++ ++ return rc->cfg_base + (where & 0xfff); ++} ++ ++static struct pci_ops cdns_pcie_hpa_host_ops = { ++ .map_bus = cdns_pci_hpa_map_bus, ++ .read = pci_generic_config_read, ++ .write = pci_generic_config_write, ++}; ++ ++static void cdns_pcie_hpa_host_enable_ptm_response(struct cdns_pcie *pcie) ++{ ++ u32 val; ++ ++ val = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL, ++ val | CDNS_PCIE_HPA_LM_PTM_CTRL_PTMRSEN); ++} ++ ++static int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc, ++ enum cdns_pcie_rp_bar bar, ++ u64 cpu_addr, u64 size, ++ unsigned long flags) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ u32 addr0, addr1, aperture, value; ++ ++ if (!rc->avail_ib_bar[bar]) ++ return -ENODEV; ++ ++ rc->avail_ib_bar[bar] = false; ++ ++ aperture = ilog2(size); ++ if (bar == RP_NO_BAR) { ++ addr0 = CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(aperture) | ++ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); ++ addr1 = upper_32_bits(cpu_addr); ++ } else { ++ addr0 = lower_32_bits(cpu_addr); ++ addr1 = upper_32_bits(cpu_addr); ++ } ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, ++ CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar), addr0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, ++ CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar), addr1); ++ ++ if (bar == RP_NO_BAR) ++ bar = (enum cdns_pcie_rp_bar)BAR_0; ++ ++ value = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_BAR_CFG); ++ value &= ~(HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) | ++ HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) | ++ HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) | ++ HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) | ++ HPA_LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 7)); ++ if (size + cpu_addr >= SZ_4G) { ++ value |= HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar); ++ if ((flags & IORESOURCE_PREFETCH)) ++ value |= HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar); ++ } else { ++ value |= HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar); ++ if ((flags & IORESOURCE_PREFETCH)) ++ value |= HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar); ++ } ++ ++ value |= HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_BAR_CFG, value); ++ ++ return 0; ++} ++ ++static int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ u32 value, ctrl; ++ ++ /* ++ * Set the root port BAR configuration register: ++ * - disable both BAR0 and BAR1 ++ * - enable Prefetchable Memory Base and Limit registers in type 1 ++ * config space (64 bits) ++ * - enable IO Base and Limit registers in type 1 config ++ * space (32 bits) ++ */ ++ ++ ctrl = CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED; ++ value = CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) | ++ CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) | ++ CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE | ++ CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS | ++ CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE | ++ CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS; ++ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, ++ CDNS_PCIE_HPA_LM_RC_BAR_CFG, value); ++ ++ if (rc->vendor_id != 0xffff) ++ cdns_pcie_hpa_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id); ++ ++ if (rc->device_id != 0xffff) ++ cdns_pcie_hpa_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); ++ ++ cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_REVISION, 0); ++ cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_PROG, 0); ++ cdns_pcie_hpa_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); ++ ++ /* Enable bus mastering */ ++ value = cdns_pcie_hpa_readl(pcie, REG_BANK_RP, PCI_COMMAND); ++ value |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_RP, PCI_COMMAND, value); ++ return 0; ++} ++ ++static void cdns_pcie_hpa_create_region_for_cfg(struct cdns_pcie_rc *rc) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc); ++ struct resource *cfg_res = rc->cfg_res; ++ struct resource_entry *entry; ++ u64 cpu_addr = cfg_res->start; ++ u32 addr0, addr1, desc1; ++ int busnr = 0; ++ ++ entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); ++ if (entry) ++ busnr = entry->res->start; ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_TAG_MANAGEMENT, 0x01000000); ++ /* ++ * Reserve region 0 for PCI configure space accesses: ++ * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by ++ * cdns_pci_map_bus(), other region registers are set here once for all ++ */ ++ desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), 0x0); ++ /* Type-1 CFG */ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), 0x05000000); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); ++ ++ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(12) | ++ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); ++ addr1 = upper_32_bits(cpu_addr); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), addr0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), addr1); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), 0x06000000); ++} ++ ++static int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc *rc) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc); ++ struct resource_entry *entry; ++ int r = 0, busnr = 0; ++ ++ if (!rc->ecam_supported) ++ cdns_pcie_hpa_create_region_for_cfg(rc); ++ ++ entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); ++ if (entry) ++ busnr = entry->res->start; ++ ++ r++; ++ if (pcie->msg_res) { ++ cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, busnr, 0, r, ++ pcie->msg_res->start); ++ ++ r++; ++ } ++ resource_list_for_each_entry(entry, &bridge->windows) { ++ struct resource *res = entry->res; ++ u64 pci_addr = res->start - entry->offset; ++ ++ if (resource_type(res) == IORESOURCE_IO) ++ cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, ++ true, ++ pci_pio_to_address(res->start), ++ pci_addr, ++ resource_size(res)); ++ else ++ cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, ++ false, ++ res->start, ++ pci_addr, ++ resource_size(res)); ++ ++ r++; ++ } ++ ++ if (rc->no_inbound_map) ++ return 0; ++ else ++ return cdns_pcie_host_map_dma_ranges(rc, cdns_pcie_hpa_host_bar_ib_config); ++} ++ ++static int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc) ++{ ++ int err; ++ ++ err = cdns_pcie_hpa_host_init_root_port(rc); ++ if (err) ++ return err; ++ ++ return cdns_pcie_hpa_host_init_address_translation(rc); ++} ++ ++int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc) ++{ ++ struct cdns_pcie *pcie = &rc->pcie; ++ struct device *dev = rc->pcie.dev; ++ int ret; ++ ++ if (rc->quirk_detect_quiet_flag) ++ cdns_pcie_hpa_detect_quiet_min_delay_set(&rc->pcie); ++ ++ cdns_pcie_hpa_host_enable_ptm_response(pcie); ++ ++ ret = cdns_pcie_start_link(pcie); ++ if (ret) { ++ dev_err(dev, "Failed to start link\n"); ++ return ret; ++ } ++ ++ ret = cdns_pcie_host_wait_for_link(pcie, cdns_pcie_hpa_link_up); ++ if (ret) ++ dev_dbg(dev, "PCIe link never came up\n"); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup); ++ ++int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) ++{ ++ struct device *dev = rc->pcie.dev; ++ struct platform_device *pdev = to_platform_device(dev); ++ struct pci_host_bridge *bridge; ++ enum cdns_pcie_rp_bar bar; ++ struct cdns_pcie *pcie; ++ struct resource *res; ++ int ret; ++ ++ bridge = pci_host_bridge_from_priv(rc); ++ if (!bridge) ++ return -ENOMEM; ++ ++ pcie = &rc->pcie; ++ pcie->is_rc = true; ++ ++ if (!pcie->reg_base) { ++ pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg"); ++ if (IS_ERR(pcie->reg_base)) { ++ dev_err(dev, "missing \"reg\"\n"); ++ return PTR_ERR(pcie->reg_base); ++ } ++ } ++ ++ /* ECAM config space is remapped at glue layer */ ++ if (!rc->cfg_base) { ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); ++ rc->cfg_base = devm_pci_remap_cfg_resource(dev, res); ++ if (IS_ERR(rc->cfg_base)) ++ return PTR_ERR(rc->cfg_base); ++ rc->cfg_res = res; ++ } ++ ++ /* Put EROM Bar aperture to 0 */ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_EROM, 0x0); ++ ++ ret = cdns_pcie_hpa_host_link_setup(rc); ++ if (ret) ++ return ret; ++ ++ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) ++ rc->avail_ib_bar[bar] = true; ++ ++ ret = cdns_pcie_hpa_host_init(rc); ++ if (ret) ++ return ret; ++ ++ if (!bridge->ops) ++ bridge->ops = &cdns_pcie_hpa_host_ops; ++ ++ return pci_host_probe(bridge); ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_setup); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Cadence PCIe host controller driver"); +diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h +new file mode 100644 +index 000000000000..026e131600de +--- /dev/null ++++ b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h +@@ -0,0 +1,193 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Cadence PCIe controller driver. ++ * ++ * Copyright (c) 2024, Cadence Design Systems ++ * Author: Manikandan K Pillai ++ */ ++#ifndef _PCIE_CADENCE_HPA_REGS_H ++#define _PCIE_CADENCE_HPA_REGS_H ++ ++#include ++#include ++#include ++#include ++#include ++ ++/* High Performance Architecture (HPA) PCIe controller registers */ ++#define CDNS_PCIE_HPA_IP_REG_BANK 0x01000000 ++#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x01003C00 ++#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0x02020000 ++ ++/* Address Translation Registers */ ++#define CDNS_PCIE_HPA_AXI_SLAVE 0x03000000 ++#define CDNS_PCIE_HPA_AXI_MASTER 0x03002000 ++ ++/* Root Port register base address */ ++#define CDNS_PCIE_HPA_RP_BASE 0x0 ++ ++#define CDNS_PCIE_HPA_LM_ID 0x1420 ++ ++/* Endpoint Function BARs */ ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \ ++ (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \ ++ CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn)) ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) (0x4000 * (pfn)) ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) ((0x4000 * (pfn)) + 0x04) ++#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \ ++ (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \ ++ CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn)) ++#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) ((0x4000 * (vfn)) + 0x08) ++#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) ((0x4000 * (vfn)) + 0x0C) ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \ ++ (GENMASK(5, 0) << (0x4 + (f) * 10)) ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ ++ (((a) << (4 + ((b) * 10))) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))) ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \ ++ (GENMASK(3, 0) << ((f) * 10)) ++#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ ++ (((c) << ((b) * 10)) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))) ++ ++/* Endpoint Function Configuration Register */ ++#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG 0x02C0 ++ ++/* Root Complex BAR Configuration Register */ ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG 0x14 ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(9, 4) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ ++ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK, a) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(3, 0) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \ ++ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(19, 14) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ ++ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK, a) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(13, 10) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \ ++ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c) ++ ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(20) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(21) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE BIT(22) ++#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS BIT(23) ++ ++/* BAR control values applicable to both Endpoint Function and Root Complex */ ++#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED 0x0 ++#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS 0x3 ++#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS 0x1 ++#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x9 ++#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS 0x5 ++#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0xD ++ ++#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ ++ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10)) ++#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ ++ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10)) ++#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ ++ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10)) ++#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ ++ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10)) ++#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ ++ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10)) ++#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ ++ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10)) ++#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture) \ ++ (((aperture) - 7) << (((bar) * 10) + 4)) ++ ++#define CDNS_PCIE_HPA_LM_PTM_CTRL 0x0520 ++#define CDNS_PCIE_HPA_LM_PTM_CTRL_PTMRSEN BIT(17) ++ ++/* Root Port Registers PCI config space for root port function */ ++#define CDNS_PCIE_HPA_RP_CAP_OFFSET 0xC0 ++ ++/* Region r Outbound AXI to PCIe Address Translation Register 0 */ ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) (0x1010 + ((r) & 0x1F) * 0x0080) ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ ++ (((nbits) - 1) & CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(23, 16) ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK, devfn) ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(31, 24) ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK, bus) ++ ++/* Region r Outbound AXI to PCIe Address Translation Register 1 */ ++#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) (0x1014 + ((r) & 0x1F) * 0x0080) ++ ++/* Region r Outbound PCIe Descriptor Register */ ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) (0x1008 + ((r) & 0x1F) * 0x0080) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(28, 24) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10) ++ ++/* Region r Outbound PCIe Descriptor Register */ ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) (0x100C + ((r) & 0x1F) * 0x0080) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK GENMASK(31, 24) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK, bus) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK GENMASK(23, 16) ++#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \ ++ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK, devfn) ++ ++#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) (0x1018 + ((r) & 0x1F) * 0x0080) ++#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26) ++#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25) ++ ++/* Region r AXI Region Base Address Register 0 */ ++#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) (0x1000 + ((r) & 0x1F) * 0x0080) ++#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) ++#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ ++ (((nbits) - 1) & CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) ++ ++/* Region r AXI Region Base Address Register 1 */ ++#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) (0x1004 + ((r) & 0x1F) * 0x0080) ++ ++/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ ++#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) (((bar) * 0x0008)) ++#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) ++#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ ++ (((nbits) - 1) & CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK) ++#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) (0x04 + ((bar) * 0x0008)) ++ ++/* AXI link down register */ ++#define CDNS_PCIE_HPA_AT_LINKDOWN 0x04 ++ ++/* ++ * Physical Layer Configuration Register 0 ++ * This register contains the parameters required for functional setup ++ * of Physical Layer. ++ */ ++#define CDNS_PCIE_HPA_PHY_LAYER_CFG0 0x0400 ++#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK GENMASK(26, 24) ++#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \ ++ FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK, delay) ++#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK GENMASK(27, 27) ++ ++#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0 0x0420 ++ ++#define CDNS_PCIE_HPA_RP_MAX_IB 0x3 ++#define CDNS_PCIE_HPA_MAX_OB 15 ++ ++/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ ++#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) (((fn) * 0x0080) + ((bar) * 0x0008)) ++#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) (0x4 + ((fn) * 0x0080) + ((bar) * 0x0008)) ++ ++/* Miscellaneous offsets definitions */ ++#define CDNS_PCIE_HPA_TAG_MANAGEMENT 0x0 ++#define CDNS_PCIE_HPA_SLAVE_RESP 0x100 ++ ++#define I_ROOT_PORT_REQ_ID_REG 0x141c ++#define LM_HAL_SBSA_CTRL 0x1170 ++ ++#define I_PCIE_BUS_NUMBERS (CDNS_PCIE_HPA_RP_BASE + 0x18) ++#define CDNS_PCIE_EROM 0x18 ++#endif /* _PCIE_CADENCE_HPA_REGS_H */ +diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-hpa.c +new file mode 100644 +index 000000000000..f60a16938265 +--- /dev/null ++++ b/drivers/pci/controller/cadence/pcie-cadence-hpa.c +@@ -0,0 +1,167 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Cadence PCIe controller driver. ++ * ++ * Copyright (c) 2024, Cadence Design Systems ++ * Author: Manikandan K Pillai ++ */ ++#include ++#include ++ ++#include "pcie-cadence.h" ++ ++bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie) ++{ ++ u32 pl_reg_val; ++ ++ pl_reg_val = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_DBG_STS_REG0); ++ if (pl_reg_val & GENMASK(0, 0)) ++ return true; ++ return false; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_hpa_link_up); ++ ++void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie) ++{ ++ u32 delay = 0x3; ++ u32 ltssm_control_cap; ++ ++ /* Set the LTSSM Detect Quiet state min. delay to 2ms */ ++ ltssm_control_cap = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, ++ CDNS_PCIE_HPA_PHY_LAYER_CFG0); ++ ltssm_control_cap = ((ltssm_control_cap & ++ ~CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK) | ++ CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay)); ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, ++ CDNS_PCIE_HPA_PHY_LAYER_CFG0, ltssm_control_cap); ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_hpa_detect_quiet_min_delay_set); ++ ++void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, ++ u32 r, bool is_io, ++ u64 cpu_addr, u64 pci_addr, size_t size) ++{ ++ /* ++ * roundup_pow_of_two() returns an unsigned long, which is not suited ++ * for 64bit values ++ */ ++ u64 sz = 1ULL << fls64(size - 1); ++ int nbits = ilog2(sz); ++ u32 addr0, addr1, desc0, desc1, ctrl0; ++ ++ if (nbits < 8) ++ nbits = 8; ++ ++ /* Set the PCI address */ ++ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) | ++ (lower_32_bits(pci_addr) & GENMASK(31, 8)); ++ addr1 = upper_32_bits(pci_addr); ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), addr0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), addr1); ++ ++ /* Set the PCIe header descriptor */ ++ if (is_io) ++ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO; ++ else ++ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM; ++ desc1 = 0; ++ ctrl0 = 0; ++ ++ /* ++ * Whether Bit [26] is set or not inside DESC0 register of the outbound ++ * PCIe descriptor, the PCI function number must be set into ++ * Bits [31:24] of DESC1 anyway. ++ * ++ * In Root Complex mode, the function number is always 0 but in Endpoint ++ * mode, the PCIe controller may support more than one function. This ++ * function number needs to be set properly into the outbound PCIe ++ * descriptor. ++ * ++ * Besides, setting Bit [26] is mandatory when in Root Complex mode: ++ * then the driver must provide the bus, resp. device, number in ++ * Bits [31:24] of DESC1, resp. Bits[23:16] of DESC0. Like the function ++ * number, the device number is always 0 in Root Complex mode. ++ * ++ * However when in Endpoint mode, we can clear Bit [26] of DESC0, hence ++ * the PCIe controller will use the captured values for the bus and ++ * device numbers. ++ */ ++ if (pcie->is_rc) { ++ /* The device and function numbers are always 0 */ ++ desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); ++ ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; ++ } else { ++ /* ++ * Use captured values for bus and device numbers but still ++ * need to set the function number ++ */ ++ desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); ++ } ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); ++ ++ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | ++ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); ++ addr1 = upper_32_bits(cpu_addr); ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region); ++ ++void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, ++ u8 busnr, u8 fn, ++ u32 r, u64 cpu_addr) ++{ ++ u32 addr0, addr1, desc0, desc1, ctrl0; ++ ++ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG; ++ desc1 = 0; ++ ctrl0 = 0; ++ ++ /* See cdns_pcie_set_outbound_region() comments above */ ++ if (pcie->is_rc) { ++ desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); ++ ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; ++ } else { ++ desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); ++ } ++ ++ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(17) | ++ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); ++ addr1 = upper_32_bits(cpu_addr); ++ ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); ++ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, ++ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region_for_normal_msg); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Cadence PCIe controller driver"); +diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c +index ebd5c3afdfcd..b067a3296dd3 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence-plat.c ++++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c +@@ -22,10 +22,6 @@ struct cdns_plat_pcie { + struct cdns_pcie *pcie; + }; + +-struct cdns_plat_pcie_of_data { +- bool is_rc; +-}; +- + static const struct of_device_id cdns_plat_pcie_of_match[]; + + static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) +diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c +index fb88a7ade412..a1eada56edba 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence.c ++++ b/drivers/pci/controller/cadence/pcie-cadence.c +@@ -23,6 +23,17 @@ u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) + } + EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability); + ++bool cdns_pcie_linkup(struct cdns_pcie *pcie) ++{ ++ u32 pl_reg_val; ++ ++ pl_reg_val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE); ++ if (pl_reg_val & GENMASK(0, 0)) ++ return true; ++ return false; ++} ++EXPORT_SYMBOL_GPL(cdns_pcie_linkup); ++ + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) + { + u32 delay = 0x3; +diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h +index 23aa64df1980..277f3706a4f4 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence.h ++++ b/drivers/pci/controller/cadence/pcie-cadence.h +@@ -12,6 +12,7 @@ + #include + #include + #include "pcie-cadence-lga-regs.h" ++#include "pcie-cadence-hpa-regs.h" + + enum cdns_pcie_rp_bar { + RP_BAR_UNDEFINED = -1, +@@ -26,18 +27,57 @@ struct cdns_pcie_rp_ib_bar { + }; + + struct cdns_pcie; ++struct cdns_pcie_rc; ++ ++enum cdns_pcie_reg_bank { ++ REG_BANK_RP, ++ REG_BANK_IP_REG, ++ REG_BANK_IP_CFG_CTRL_REG, ++ REG_BANK_AXI_MASTER_COMMON, ++ REG_BANK_AXI_MASTER, ++ REG_BANK_AXI_SLAVE, ++ REG_BANK_AXI_HLS, ++ REG_BANK_AXI_RAS, ++ REG_BANK_AXI_DTI, ++ REG_BANKS_MAX, ++}; + + struct cdns_pcie_ops { +- int (*start_link)(struct cdns_pcie *pcie); +- void (*stop_link)(struct cdns_pcie *pcie); +- bool (*link_up)(struct cdns_pcie *pcie); ++ int (*start_link)(struct cdns_pcie *pcie); ++ void (*stop_link)(struct cdns_pcie *pcie); ++ bool (*link_up)(struct cdns_pcie *pcie); + u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); + }; + ++/** ++ * struct cdns_plat_pcie_of_data - Register bank offset for a platform ++ * @is_rc: controller is a RC ++ * @ip_reg_bank_offset: ip register bank start offset ++ * @ip_cfg_ctrl_reg_offset: ip config control register start offset ++ * @axi_mstr_common_offset: AXI master common register start offset ++ * @axi_slave_offset: AXI slave start offset ++ * @axi_master_offset: AXI master start offset ++ * @axi_hls_offset: AXI HLS offset start ++ * @axi_ras_offset: AXI RAS offset ++ * @axi_dti_offset: AXI DTI offset ++ */ ++struct cdns_plat_pcie_of_data { ++ u32 is_rc:1; ++ u32 ip_reg_bank_offset; ++ u32 ip_cfg_ctrl_reg_offset; ++ u32 axi_mstr_common_offset; ++ u32 axi_slave_offset; ++ u32 axi_master_offset; ++ u32 axi_hls_offset; ++ u32 axi_ras_offset; ++ u32 axi_dti_offset; ++}; ++ + /** + * struct cdns_pcie - private data for Cadence PCIe controller drivers + * @reg_base: IO mapped register base + * @mem_res: start/end offsets in the physical system memory to map PCI accesses ++ * @msg_res: Region for send message to map PCI accesses + * @dev: PCIe controller + * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint. + * @phy_count: number of supported PHY devices +@@ -45,16 +85,19 @@ struct cdns_pcie_ops { + * @link: list of pointers to corresponding device link representations + * @ops: Platform-specific ops to control various inputs from Cadence PCIe + * wrapper ++ * @cdns_pcie_reg_offsets: Register bank offsets for different SoC + */ + struct cdns_pcie { +- void __iomem *reg_base; +- struct resource *mem_res; +- struct device *dev; +- bool is_rc; +- int phy_count; +- struct phy **phy; +- struct device_link **link; +- const struct cdns_pcie_ops *ops; ++ void __iomem *reg_base; ++ struct resource *mem_res; ++ struct resource *msg_res; ++ struct device *dev; ++ bool is_rc; ++ int phy_count; ++ struct phy **phy; ++ struct device_link **link; ++ const struct cdns_pcie_ops *ops; ++ const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; + }; + + /** +@@ -70,6 +113,8 @@ struct cdns_pcie { + * available + * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 + * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk ++ * @ecam_supported: Whether the ECAM is supported ++ * @no_inbound_map: Whether inbound mapping is supported + */ + struct cdns_pcie_rc { + struct cdns_pcie pcie; +@@ -80,6 +125,8 @@ struct cdns_pcie_rc { + bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; + unsigned int quirk_retrain_flag:1; + unsigned int quirk_detect_quiet_flag:1; ++ unsigned int ecam_supported:1; ++ unsigned int no_inbound_map:1; + }; + + /** +@@ -132,6 +179,43 @@ struct cdns_pcie_ep { + unsigned int quirk_disable_flr:1; + }; + ++static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_pcie_reg_bank bank) ++{ ++ u32 offset = 0x0; ++ ++ switch (bank) { ++ case REG_BANK_RP: ++ offset = 0; ++ break; ++ case REG_BANK_IP_REG: ++ offset = pcie->cdns_pcie_reg_offsets->ip_reg_bank_offset; ++ break; ++ case REG_BANK_IP_CFG_CTRL_REG: ++ offset = pcie->cdns_pcie_reg_offsets->ip_cfg_ctrl_reg_offset; ++ break; ++ case REG_BANK_AXI_MASTER_COMMON: ++ offset = pcie->cdns_pcie_reg_offsets->axi_mstr_common_offset; ++ break; ++ case REG_BANK_AXI_MASTER: ++ offset = pcie->cdns_pcie_reg_offsets->axi_master_offset; ++ break; ++ case REG_BANK_AXI_SLAVE: ++ offset = pcie->cdns_pcie_reg_offsets->axi_slave_offset; ++ break; ++ case REG_BANK_AXI_HLS: ++ offset = pcie->cdns_pcie_reg_offsets->axi_hls_offset; ++ break; ++ case REG_BANK_AXI_RAS: ++ offset = pcie->cdns_pcie_reg_offsets->axi_ras_offset; ++ break; ++ case REG_BANK_AXI_DTI: ++ offset = pcie->cdns_pcie_reg_offsets->axi_dti_offset; ++ break; ++ default: ++ break; ++ } ++ return offset; ++} + + /* Register access */ + static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) +@@ -144,6 +228,27 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) + return readl(pcie->reg_base + reg); + } + ++static inline void cdns_pcie_hpa_writel(struct cdns_pcie *pcie, ++ enum cdns_pcie_reg_bank bank, ++ u32 reg, ++ u32 value) ++{ ++ u32 offset = cdns_reg_bank_to_off(pcie, bank); ++ ++ reg += offset; ++ writel(value, pcie->reg_base + reg); ++} ++ ++static inline u32 cdns_pcie_hpa_readl(struct cdns_pcie *pcie, ++ enum cdns_pcie_reg_bank bank, ++ u32 reg) ++{ ++ u32 offset = cdns_reg_bank_to_off(pcie, bank); ++ ++ reg += offset; ++ return readl(pcie->reg_base + reg); ++} ++ + static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) + { + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); +@@ -233,6 +338,29 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) + return cdns_pcie_read_sz(addr, 0x2); + } + ++static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie, ++ u32 reg, u8 value) ++{ ++ void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; ++ ++ cdns_pcie_write_sz(addr, 0x1, value); ++} ++ ++static inline void cdns_pcie_hpa_rp_writew(struct cdns_pcie *pcie, ++ u32 reg, u16 value) ++{ ++ void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; ++ ++ cdns_pcie_write_sz(addr, 0x2, value); ++} ++ ++static inline u16 cdns_pcie_hpa_rp_readw(struct cdns_pcie *pcie, u32 reg) ++{ ++ void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; ++ ++ return cdns_pcie_read_sz(addr, 0x2); ++} ++ + /* Endpoint Function register access */ + static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, + u32 reg, u8 value) +@@ -297,6 +425,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); + void cdns_pcie_host_disable(struct cdns_pcie_rc *rc); + void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where); ++int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc); + #else + static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) + { +@@ -313,6 +442,11 @@ static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) + return 0; + } + ++static inline int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) ++{ ++ return 0; ++} ++ + static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc) + { + } +@@ -327,6 +461,7 @@ static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int d + #if IS_ENABLED(CONFIG_PCIE_CADENCE_EP) + int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); + void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep); ++int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep); + #else + static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) + { +@@ -336,10 +471,17 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) + static inline void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep) + { + } ++ ++static inline int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep) ++{ ++ return 0; ++} ++ + #endif + +-u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); +-u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); ++u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); ++u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); ++bool cdns_pcie_linkup(struct cdns_pcie *pcie); + + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); + +@@ -353,8 +495,23 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, + + void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); + void cdns_pcie_disable_phy(struct cdns_pcie *pcie); +-int cdns_pcie_enable_phy(struct cdns_pcie *pcie); +-int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); ++int cdns_pcie_enable_phy(struct cdns_pcie *pcie); ++int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); ++void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie); ++void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, ++ u32 r, bool is_io, ++ u64 cpu_addr, u64 pci_addr, size_t size); ++void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, ++ u8 busnr, u8 fn, ++ u32 r, u64 cpu_addr); ++int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc); ++void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, ++ int where); ++int cdns_pcie_hpa_host_start_link(struct cdns_pcie_rc *rc); ++int cdns_pcie_hpa_start_link(struct cdns_pcie *pcie); ++void cdns_pcie_hpa_stop_link(struct cdns_pcie *pcie); ++bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie); ++ + extern const struct dev_pm_ops cdns_pcie_pm_ops; + + #endif /* _PCIE_CADENCE_H */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0147-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch b/SPECS/linux-lts/0147-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch deleted file mode 100644 index 1f7191cbd3..0000000000 --- a/SPECS/linux-lts/0147-UPSTREAM-PCI-cadence-Split-PCIe-controller-header-fi.patch +++ /dev/null @@ -1,508 +0,0 @@ -From c11c8fffc2a4398eef7883769b12ef9c7e9d39ea Mon Sep 17 00:00:00 2001 -From: Manikandan K Pillai -Date: Sat, 8 Nov 2025 22:02:57 +0800 -Subject: [PATCH 147/467] UPSTREAM: PCI: cadence: Split PCIe controller header - file - -Split the Cadence PCIe header file by moving the Legacy (LGA) controller -register definitions to a separate header file for support of next -generation PCIe controller architecture. - -Signed-off-by: Manikandan K Pillai -Signed-off-by: Manivannan Sadhasivam -Link: https://patch.msgid.link/20251108140305.1120117-3-hans.zhang@cixtech.com -(cherry picked from commit 3977be25f5fd973cad6bed810ac1045ba8cfbfa6) -Signed-off-by: Han Gao ---- - .../cadence/pcie-cadence-lga-regs.h | 230 ++++++++++++++++++ - drivers/pci/controller/cadence/pcie-cadence.h | 222 +---------------- - 2 files changed, 232 insertions(+), 220 deletions(-) - create mode 100644 drivers/pci/controller/cadence/pcie-cadence-lga-regs.h - -diff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h -new file mode 100644 -index 000000000000..857b2140c5d2 ---- /dev/null -+++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h -@@ -0,0 +1,230 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Cadence PCIe controller driver. -+ * -+ * Copyright (c) 2017 Cadence -+ * Author: Cyrille Pitchen -+ */ -+#ifndef _PCIE_CADENCE_LGA_REGS_H -+#define _PCIE_CADENCE_LGA_REGS_H -+ -+#include -+ -+/* Parameters for the waiting for link up routine */ -+#define LINK_WAIT_MAX_RETRIES 10 -+#define LINK_WAIT_USLEEP_MIN 90000 -+#define LINK_WAIT_USLEEP_MAX 100000 -+ -+/* Local Management Registers */ -+#define CDNS_PCIE_LM_BASE 0x00100000 -+ -+/* Vendor ID Register */ -+#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) -+#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) -+#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 -+#define CDNS_PCIE_LM_ID_VENDOR(vid) \ -+ (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) -+#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) -+#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 -+#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ -+ (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) -+ -+/* Root Port Requester ID Register */ -+#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) -+#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) -+#define CDNS_PCIE_LM_RP_RID_SHIFT 0 -+#define CDNS_PCIE_LM_RP_RID_(rid) \ -+ (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) -+ -+/* Endpoint Bus and Device Number Register */ -+#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022C) -+#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) -+#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 -+#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) -+#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 -+ -+/* Endpoint Function f BAR b Configuration Registers */ -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ -+ (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn)) -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ -+ (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ -+ (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) -+#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ -+ (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn)) -+#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ -+ (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) -+#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ -+ (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ -+ (GENMASK(4, 0) << ((b) * 8)) -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ -+ (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ -+ (GENMASK(7, 5) << ((b) * 8)) -+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ -+ (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) -+ -+/* Endpoint Function Configuration Register */ -+#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02C0) -+ -+/* Root Complex BAR Configuration Register */ -+#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ -+ (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ -+ (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ -+ (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) -+#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ -+ (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) -+#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) -+#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 -+#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) -+#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) -+#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 -+#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) -+#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) -+ -+/* BAR control values applicable to both Endpoint Function and Root Complex */ -+#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 -+#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 -+#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 -+#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 -+#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 -+#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 -+ -+#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ -+ (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) -+#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ -+ (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) -+#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ -+ (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) -+#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ -+ (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) -+#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ -+ (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) -+#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ -+ (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) -+#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ -+ (((aperture) - 2) << ((bar) * 8)) -+ -+/* PTM Control Register */ -+#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0DA8) -+#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) -+ -+/* -+ * Endpoint Function Registers (PCI configuration space for endpoint functions) -+ */ -+#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) -+ -+#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -+#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xB0 -+#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xC0 -+#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 -+ -+/* Endpoint PF Registers */ -+#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) -+#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) -+ -+/* Root Port Registers (PCI configuration space for the root port function) */ -+#define CDNS_PCIE_RP_BASE 0x00200000 -+#define CDNS_PCIE_RP_CAP_OFFSET 0xC0 -+ -+/* Address Translation Registers */ -+#define CDNS_PCIE_AT_BASE 0x00400000 -+ -+/* Region r Outbound AXI to PCIe Address Translation Register 0 */ -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ -+ (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1F) * 0x0020) -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ -+ (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ -+ (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ -+ (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) -+ -+/* Region r Outbound AXI to PCIe Address Translation Register 1 */ -+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ -+ (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1F) * 0x0020) -+ -+/* Region r Outbound PCIe Descriptor Register 0 */ -+#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ -+ (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1F) * 0x0020) -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xA -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xB -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xC -+#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xD -+/* Bit 23 MUST be set in RC mode. */ -+#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) -+#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) -+#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ -+ (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) -+ -+/* Region r Outbound PCIe Descriptor Register 1 */ -+#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ -+ (CDNS_PCIE_AT_BASE + 0x000C + ((r) & 0x1F) * 0x0020) -+#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) -+#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ -+ ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) -+ -+/* Region r AXI Region Base Address Register 0 */ -+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ -+ (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1F) * 0x0020) -+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) -+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ -+ (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) -+ -+/* Region r AXI Region Base Address Register 1 */ -+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ -+ (CDNS_PCIE_AT_BASE + 0x001C + ((r) & 0x1F) * 0x0020) -+ -+/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ -+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ -+ (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) -+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) -+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ -+ (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) -+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ -+ (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) -+ -+/* AXI link down register */ -+#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) -+ -+/* LTSSM Capabilities register */ -+#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) -+#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) -+#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 -+#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ -+ (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ -+ CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) -+ -+#define CDNS_PCIE_RP_MAX_IB 0x3 -+#define CDNS_PCIE_MAX_OB 32 -+ -+/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ -+#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ -+ (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) -+#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ -+ (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) -+ -+/* Normal/Vendor specific message access: offset inside some outbound region */ -+#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) -+#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ -+ (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) -+#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) -+#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ -+ (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) -+#define CDNS_PCIE_MSG_NO_DATA BIT(16) -+ -+#endif /* _PCIE_CADENCE_LGA_REGS_H */ -diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h -index 23ccad0a31f2..23aa64df1980 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence.h -+++ b/drivers/pci/controller/cadence/pcie-cadence.h -@@ -7,211 +7,11 @@ - #define _PCIE_CADENCE_H - - #include -+#include - #include - #include - #include -- --/* Parameters for the waiting for link up routine */ --#define LINK_WAIT_MAX_RETRIES 10 --#define LINK_WAIT_USLEEP_MIN 90000 --#define LINK_WAIT_USLEEP_MAX 100000 -- --/* -- * Local Management Registers -- */ --#define CDNS_PCIE_LM_BASE 0x00100000 -- --/* Vendor ID Register */ --#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) --#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) --#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 --#define CDNS_PCIE_LM_ID_VENDOR(vid) \ -- (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) --#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) --#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 --#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ -- (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) -- --/* Root Port Requester ID Register */ --#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) --#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) --#define CDNS_PCIE_LM_RP_RID_SHIFT 0 --#define CDNS_PCIE_LM_RP_RID_(rid) \ -- (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) -- --/* Endpoint Bus and Device Number Register */ --#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) --#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) --#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 --#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) --#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 -- --/* Endpoint Function f BAR b Configuration Registers */ --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ -- (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn)) --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ -- (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ -- (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) --#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ -- (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn)) --#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ -- (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) --#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ -- (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ -- (GENMASK(4, 0) << ((b) * 8)) --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ -- (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ -- (GENMASK(7, 5) << ((b) * 8)) --#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ -- (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) -- --/* Endpoint Function Configuration Register */ --#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) -- --/* Root Complex BAR Configuration Register */ --#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ -- (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ -- (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ -- (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) --#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ -- (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) --#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) --#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 --#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) --#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) --#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 --#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) --#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) -- --/* BAR control values applicable to both Endpoint Function and Root Complex */ --#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 --#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 --#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 --#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 --#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 --#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 -- --#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ -- (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) --#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ -- (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) --#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ -- (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) --#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ -- (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) --#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ -- (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) --#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ -- (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) --#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ -- (((aperture) - 2) << ((bar) * 8)) -- --/* PTM Control Register */ --#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8) --#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) -- --/* -- * Endpoint Function Registers (PCI configuration space for endpoint functions) -- */ --#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) -- --/* -- * Endpoint PF Registers -- */ --#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) --#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) -- --/* -- * Root Port Registers (PCI configuration space for the root port function) -- */ --#define CDNS_PCIE_RP_BASE 0x00200000 --#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 -- --/* -- * Address Translation Registers -- */ --#define CDNS_PCIE_AT_BASE 0x00400000 -- --/* Region r Outbound AXI to PCIe Address Translation Register 0 */ --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ -- (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ -- (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ -- (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ -- (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) -- --/* Region r Outbound AXI to PCIe Address Translation Register 1 */ --#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ -- (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) -- --/* Region r Outbound PCIe Descriptor Register 0 */ --#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ -- (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc --#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd --/* Bit 23 MUST be set in RC mode. */ --#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) --#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) --#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ -- (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) -- --/* Region r Outbound PCIe Descriptor Register 1 */ --#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ -- (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) --#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) --#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ -- ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) -- --/* Region r AXI Region Base Address Register 0 */ --#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ -- (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) --#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) --#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ -- (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) -- --/* Region r AXI Region Base Address Register 1 */ --#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ -- (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) -- --/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ --#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ -- (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) --#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) --#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ -- (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) --#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ -- (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) -- --/* AXI link down register */ --#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) -- --/* LTSSM Capabilities register */ --#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) --#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) --#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 --#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ -- (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ -- CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) -+#include "pcie-cadence-lga-regs.h" - - enum cdns_pcie_rp_bar { - RP_BAR_UNDEFINED = -1, -@@ -220,29 +20,11 @@ enum cdns_pcie_rp_bar { - RP_NO_BAR - }; - --#define CDNS_PCIE_RP_MAX_IB 0x3 --#define CDNS_PCIE_MAX_OB 32 -- - struct cdns_pcie_rp_ib_bar { - u64 size; - bool free; - }; - --/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ --#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ -- (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) --#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ -- (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) -- --/* Normal/Vendor specific message access: offset inside some outbound region */ --#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) --#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ -- (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) --#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) --#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ -- (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) --#define CDNS_PCIE_MSG_DATA BIT(16) -- - struct cdns_pcie; - - struct cdns_pcie_ops { --- -2.53.0 - diff --git a/SPECS/linux-lts/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch b/SPECS/linux-lts/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch new file mode 100644 index 0000000000..45d4cc96d9 --- /dev/null +++ b/SPECS/linux-lts/0147-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch @@ -0,0 +1,38 @@ +From 668b64875b3a39ad0c809fd84baba5596b3f93c1 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:49:55 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use phylink's interface mode + for set_clk_tx_rate() + +imx_dwmac_set_clk_tx_rate() is passed the interface mode from phylink +which will be the same as plat_dat->phy_interface. Use the passed-in +interface mode rather than plat_dat->phy_interface. + +Reviewed-by: Maxime Chevallier +Tested-by: Maxime Chevallier +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt4N-0000000ChoM-1llp@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit dec568a36f9b16f0334aed8e95ec4225606830cc) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index 4268b9987237..147fa08d5b6e 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -195,9 +195,6 @@ static void imx_dwmac_exit(struct platform_device *pdev, void *priv) + static int imx_dwmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, + phy_interface_t interface, int speed) + { +- struct imx_priv_data *dwmac = bsp_priv; +- +- interface = dwmac->plat_dat->phy_interface; + if (interface == PHY_INTERFACE_MODE_RMII || + interface == PHY_INTERFACE_MODE_MII) + return 0; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0148-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch b/SPECS/linux-lts/0148-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch deleted file mode 100644 index 297fc9341d..0000000000 --- a/SPECS/linux-lts/0148-UPSTREAM-PCI-cadence-Move-PCIe-RP-common-functions-t.patch +++ /dev/null @@ -1,731 +0,0 @@ -From a8c954c135b4ad338d55143da55d606909cfffb3 Mon Sep 17 00:00:00 2001 -From: Manikandan K Pillai -Date: Sat, 8 Nov 2025 22:02:58 +0800 -Subject: [PATCH 148/467] UPSTREAM: PCI: cadence: Move PCIe RP common functions - to a separate file - -Move the Cadence PCIe controller RP common functions into a separate file. -The common library functions are split from legacy PCIe RP controller -functions to a separate file. - -Signed-off-by: Manikandan K Pillai -[mani: removed the unused variable] -Signed-off-by: Manivannan Sadhasivam -Link: https://patch.msgid.link/20251108140305.1120117-4-hans.zhang@cixtech.com -(cherry picked from commit b80a7b4713c967479752ea4801eb1d1933093f58) -Signed-off-by: Han Gao ---- - drivers/pci/controller/cadence/Makefile | 10 +- - .../cadence/pcie-cadence-host-common.c | 288 ++++++++++++++++++ - .../cadence/pcie-cadence-host-common.h | 46 +++ - .../controller/cadence/pcie-cadence-host.c | 278 +---------------- - 4 files changed, 349 insertions(+), 273 deletions(-) - create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common.c - create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common.h - -diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile -index 5e23f8539ecc..91ffdbfd3aaa 100644 ---- a/drivers/pci/controller/cadence/Makefile -+++ b/drivers/pci/controller/cadence/Makefile -@@ -1,7 +1,11 @@ - # SPDX-License-Identifier: GPL-2.0 --obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o --obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o --obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o -+pcie-cadence-mod-y := pcie-cadence.o -+pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o -+pcie-cadence-ep-mod-y := pcie-cadence-ep.o -+ -+obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o -+obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o -+obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o - obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o - obj-$(CONFIG_PCI_J721E) += pci-j721e.o - obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o -diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c -new file mode 100644 -index 000000000000..15415d7f35ee ---- /dev/null -+++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c -@@ -0,0 +1,288 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Cadence PCIe host controller library. -+ * -+ * Copyright (c) 2017 Cadence -+ * Author: Cyrille Pitchen -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pcie-cadence.h" -+#include "pcie-cadence-host-common.h" -+ -+#define LINK_RETRAIN_TIMEOUT HZ -+ -+u64 bar_max_size[] = { -+ [RP_BAR0] = _ULL(128 * SZ_2G), -+ [RP_BAR1] = SZ_2G, -+ [RP_NO_BAR] = _BITULL(63), -+}; -+EXPORT_SYMBOL_GPL(bar_max_size); -+ -+int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) -+{ -+ u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; -+ unsigned long end_jiffies; -+ u16 lnk_stat; -+ -+ /* Wait for link training to complete. Exit after timeout. */ -+ end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; -+ do { -+ lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); -+ if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) -+ break; -+ usleep_range(0, 1000); -+ } while (time_before(jiffies, end_jiffies)); -+ -+ if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) -+ return 0; -+ -+ return -ETIMEDOUT; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_host_training_complete); -+ -+int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie, -+ cdns_pcie_linkup_func pcie_link_up) -+{ -+ struct device *dev = pcie->dev; -+ int retries; -+ -+ /* Check if the link is up or not */ -+ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { -+ if (pcie_link_up(pcie)) { -+ dev_info(dev, "Link up\n"); -+ return 0; -+ } -+ usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); -+ } -+ -+ return -ETIMEDOUT; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_host_wait_for_link); -+ -+int cdns_pcie_retrain(struct cdns_pcie *pcie, -+ cdns_pcie_linkup_func pcie_link_up) -+{ -+ u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; -+ u16 lnk_stat, lnk_ctl; -+ int ret = 0; -+ -+ /* -+ * Set retrain bit if current speed is 2.5 GB/s, -+ * but the PCIe root port support is > 2.5 GB/s. -+ */ -+ -+ lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + -+ PCI_EXP_LNKCAP)); -+ if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) -+ return ret; -+ -+ lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); -+ if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { -+ lnk_ctl = cdns_pcie_rp_readw(pcie, -+ pcie_cap_off + PCI_EXP_LNKCTL); -+ lnk_ctl |= PCI_EXP_LNKCTL_RL; -+ cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, -+ lnk_ctl); -+ -+ ret = cdns_pcie_host_training_complete(pcie); -+ if (ret) -+ return ret; -+ -+ ret = cdns_pcie_host_wait_for_link(pcie, pcie_link_up); -+ } -+ return ret; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_retrain); -+ -+int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, -+ cdns_pcie_linkup_func pcie_link_up) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ int ret; -+ -+ ret = cdns_pcie_host_wait_for_link(pcie, pcie_link_up); -+ -+ /* -+ * Retrain link for Gen2 training defect -+ * if quirk flag is set. -+ */ -+ if (!ret && rc->quirk_retrain_flag) -+ ret = cdns_pcie_retrain(pcie, pcie_link_up); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link); -+ -+enum cdns_pcie_rp_bar -+cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) -+{ -+ enum cdns_pcie_rp_bar bar, sel_bar; -+ -+ sel_bar = RP_BAR_UNDEFINED; -+ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { -+ if (!rc->avail_ib_bar[bar]) -+ continue; -+ -+ if (size <= bar_max_size[bar]) { -+ if (sel_bar == RP_BAR_UNDEFINED) { -+ sel_bar = bar; -+ continue; -+ } -+ -+ if (bar_max_size[bar] < bar_max_size[sel_bar]) -+ sel_bar = bar; -+ } -+ } -+ -+ return sel_bar; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_host_find_min_bar); -+ -+enum cdns_pcie_rp_bar -+cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) -+{ -+ enum cdns_pcie_rp_bar bar, sel_bar; -+ -+ sel_bar = RP_BAR_UNDEFINED; -+ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { -+ if (!rc->avail_ib_bar[bar]) -+ continue; -+ -+ if (size >= bar_max_size[bar]) { -+ if (sel_bar == RP_BAR_UNDEFINED) { -+ sel_bar = bar; -+ continue; -+ } -+ -+ if (bar_max_size[bar] > bar_max_size[sel_bar]) -+ sel_bar = bar; -+ } -+ } -+ -+ return sel_bar; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_host_find_max_bar); -+ -+int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, -+ const struct list_head *b) -+{ -+ struct resource_entry *entry1, *entry2; -+ -+ entry1 = container_of(a, struct resource_entry, node); -+ entry2 = container_of(b, struct resource_entry, node); -+ -+ return resource_size(entry2->res) - resource_size(entry1->res); -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_host_dma_ranges_cmp); -+ -+int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, -+ struct resource_entry *entry, -+ cdns_pcie_host_bar_ib_cfg pci_host_ib_config) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ struct device *dev = pcie->dev; -+ u64 cpu_addr, size, winsize; -+ enum cdns_pcie_rp_bar bar; -+ unsigned long flags; -+ int ret; -+ -+ cpu_addr = entry->res->start; -+ flags = entry->res->flags; -+ size = resource_size(entry->res); -+ -+ while (size > 0) { -+ /* -+ * Try to find a minimum BAR whose size is greater than -+ * or equal to the remaining resource_entry size. This will -+ * fail if the size of each of the available BARs is less than -+ * the remaining resource_entry size. -+ * -+ * If a minimum BAR is found, IB ATU will be configured and -+ * exited. -+ */ -+ bar = cdns_pcie_host_find_min_bar(rc, size); -+ if (bar != RP_BAR_UNDEFINED) { -+ ret = pci_host_ib_config(rc, bar, cpu_addr, size, flags); -+ if (ret) -+ dev_err(dev, "IB BAR: %d config failed\n", bar); -+ return ret; -+ } -+ -+ /* -+ * If the control reaches here, it would mean the remaining -+ * resource_entry size cannot be fitted in a single BAR. So we -+ * find a maximum BAR whose size is less than or equal to the -+ * remaining resource_entry size and split the resource entry -+ * so that part of resource entry is fitted inside the maximum -+ * BAR. The remaining size would be fitted during the next -+ * iteration of the loop. -+ * -+ * If a maximum BAR is not found, there is no way we can fit -+ * this resource_entry, so we error out. -+ */ -+ bar = cdns_pcie_host_find_max_bar(rc, size); -+ if (bar == RP_BAR_UNDEFINED) { -+ dev_err(dev, "No free BAR to map cpu_addr %llx\n", -+ cpu_addr); -+ return -EINVAL; -+ } -+ -+ winsize = bar_max_size[bar]; -+ ret = pci_host_ib_config(rc, bar, cpu_addr, winsize, flags); -+ if (ret) { -+ dev_err(dev, "IB BAR: %d config failed\n", bar); -+ return ret; -+ } -+ -+ size -= winsize; -+ cpu_addr += winsize; -+ } -+ -+ return 0; -+} -+ -+int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc, -+ cdns_pcie_host_bar_ib_cfg pci_host_ib_config) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ struct device *dev = pcie->dev; -+ struct device_node *np = dev->of_node; -+ struct pci_host_bridge *bridge; -+ struct resource_entry *entry; -+ u32 no_bar_nbits = 32; -+ int err; -+ -+ bridge = pci_host_bridge_from_priv(rc); -+ if (!bridge) -+ return -ENOMEM; -+ -+ if (list_empty(&bridge->dma_ranges)) { -+ of_property_read_u32(np, "cdns,no-bar-match-nbits", -+ &no_bar_nbits); -+ err = pci_host_ib_config(rc, RP_NO_BAR, 0x0, (u64)1 << no_bar_nbits, 0); -+ if (err) -+ dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); -+ return err; -+ } -+ -+ list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); -+ -+ resource_list_for_each_entry(entry, &bridge->dma_ranges) { -+ err = cdns_pcie_host_bar_config(rc, entry, pci_host_ib_config); -+ if (err) { -+ dev_err(dev, "Fail to configure IB using dma-ranges\n"); -+ return err; -+ } -+ } -+ -+ return 0; -+} -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Cadence PCIe host controller driver"); -diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.h b/drivers/pci/controller/cadence/pcie-cadence-host-common.h -new file mode 100644 -index 000000000000..fe7d4202a8b6 ---- /dev/null -+++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.h -@@ -0,0 +1,46 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Cadence PCIe Host controller driver. -+ * -+ * Copyright (c) 2017 Cadence -+ * Author: Cyrille Pitchen -+ */ -+#ifndef _PCIE_CADENCE_HOST_COMMON_H -+#define _PCIE_CADENCE_HOST_COMMON_H -+ -+#include -+#include -+ -+extern u64 bar_max_size[]; -+ -+typedef int (*cdns_pcie_host_bar_ib_cfg)(struct cdns_pcie_rc *, -+ enum cdns_pcie_rp_bar, -+ u64, -+ u64, -+ unsigned long); -+typedef bool (*cdns_pcie_linkup_func)(struct cdns_pcie *); -+ -+int cdns_pcie_host_training_complete(struct cdns_pcie *pcie); -+int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie, -+ cdns_pcie_linkup_func pcie_link_up); -+int cdns_pcie_retrain(struct cdns_pcie *pcie, cdns_pcie_linkup_func pcie_linkup_func); -+int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc, -+ cdns_pcie_linkup_func pcie_link_up); -+enum cdns_pcie_rp_bar -+cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size); -+enum cdns_pcie_rp_bar -+cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size); -+int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, -+ const struct list_head *b); -+int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, -+ enum cdns_pcie_rp_bar bar, -+ u64 cpu_addr, -+ u64 size, -+ unsigned long flags); -+int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, -+ struct resource_entry *entry, -+ cdns_pcie_host_bar_ib_cfg pci_host_ib_config); -+int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc, -+ cdns_pcie_host_bar_ib_cfg pci_host_ib_config); -+ -+#endif /* _PCIE_CADENCE_HOST_COMMON_H */ -diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c -index fffd63d6665e..db3154c1eccb 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence-host.c -+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c -@@ -12,14 +12,7 @@ - #include - - #include "pcie-cadence.h" -- --#define LINK_RETRAIN_TIMEOUT HZ -- --static u64 bar_max_size[] = { -- [RP_BAR0] = _ULL(128 * SZ_2G), -- [RP_BAR1] = SZ_2G, -- [RP_NO_BAR] = _BITULL(63), --}; -+#include "pcie-cadence-host-common.h" - - static u8 bar_aperture_mask[] = { - [RP_BAR0] = 0x1F, -@@ -81,77 +74,6 @@ static struct pci_ops cdns_pcie_host_ops = { - .write = pci_generic_config_write, - }; - --static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) --{ -- u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; -- unsigned long end_jiffies; -- u16 lnk_stat; -- -- /* Wait for link training to complete. Exit after timeout. */ -- end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; -- do { -- lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); -- if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) -- break; -- usleep_range(0, 1000); -- } while (time_before(jiffies, end_jiffies)); -- -- if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) -- return 0; -- -- return -ETIMEDOUT; --} -- --static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) --{ -- struct device *dev = pcie->dev; -- int retries; -- -- /* Check if the link is up or not */ -- for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { -- if (cdns_pcie_link_up(pcie)) { -- dev_info(dev, "Link up\n"); -- return 0; -- } -- usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); -- } -- -- return -ETIMEDOUT; --} -- --static int cdns_pcie_retrain(struct cdns_pcie *pcie) --{ -- u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; -- u16 lnk_stat, lnk_ctl; -- int ret = 0; -- -- /* -- * Set retrain bit if current speed is 2.5 GB/s, -- * but the PCIe root port support is > 2.5 GB/s. -- */ -- -- lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + -- PCI_EXP_LNKCAP)); -- if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) -- return ret; -- -- lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); -- if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { -- lnk_ctl = cdns_pcie_rp_readw(pcie, -- pcie_cap_off + PCI_EXP_LNKCTL); -- lnk_ctl |= PCI_EXP_LNKCTL_RL; -- cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, -- lnk_ctl); -- -- ret = cdns_pcie_host_training_complete(pcie); -- if (ret) -- return ret; -- -- ret = cdns_pcie_host_wait_for_link(pcie); -- } -- return ret; --} -- - static void cdns_pcie_host_disable_ptm_response(struct cdns_pcie *pcie) - { - u32 val; -@@ -168,23 +90,6 @@ static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie) - cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN); - } - --static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) --{ -- struct cdns_pcie *pcie = &rc->pcie; -- int ret; -- -- ret = cdns_pcie_host_wait_for_link(pcie); -- -- /* -- * Retrain link for Gen2 training defect -- * if quirk flag is set. -- */ -- if (!ret && rc->quirk_retrain_flag) -- ret = cdns_pcie_retrain(pcie); -- -- return ret; --} -- - static void cdns_pcie_host_deinit_root_port(struct cdns_pcie_rc *rc) - { - struct cdns_pcie *pcie = &rc->pcie; -@@ -245,10 +150,11 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) - return 0; - } - --static int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, -- enum cdns_pcie_rp_bar bar, -- u64 cpu_addr, u64 size, -- unsigned long flags) -+int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, -+ enum cdns_pcie_rp_bar bar, -+ u64 cpu_addr, -+ u64 size, -+ unsigned long flags) - { - struct cdns_pcie *pcie = &rc->pcie; - u32 addr0, addr1, aperture, value; -@@ -290,137 +196,6 @@ static int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc, - return 0; - } - --static enum cdns_pcie_rp_bar --cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) --{ -- enum cdns_pcie_rp_bar bar, sel_bar; -- -- sel_bar = RP_BAR_UNDEFINED; -- for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { -- if (!rc->avail_ib_bar[bar]) -- continue; -- -- if (size <= bar_max_size[bar]) { -- if (sel_bar == RP_BAR_UNDEFINED) { -- sel_bar = bar; -- continue; -- } -- -- if (bar_max_size[bar] < bar_max_size[sel_bar]) -- sel_bar = bar; -- } -- } -- -- return sel_bar; --} -- --static enum cdns_pcie_rp_bar --cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) --{ -- enum cdns_pcie_rp_bar bar, sel_bar; -- -- sel_bar = RP_BAR_UNDEFINED; -- for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) { -- if (!rc->avail_ib_bar[bar]) -- continue; -- -- if (size >= bar_max_size[bar]) { -- if (sel_bar == RP_BAR_UNDEFINED) { -- sel_bar = bar; -- continue; -- } -- -- if (bar_max_size[bar] > bar_max_size[sel_bar]) -- sel_bar = bar; -- } -- } -- -- return sel_bar; --} -- --static int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, -- struct resource_entry *entry) --{ -- u64 cpu_addr, pci_addr, size, winsize; -- struct cdns_pcie *pcie = &rc->pcie; -- struct device *dev = pcie->dev; -- enum cdns_pcie_rp_bar bar; -- unsigned long flags; -- int ret; -- -- cpu_addr = entry->res->start; -- pci_addr = entry->res->start - entry->offset; -- flags = entry->res->flags; -- size = resource_size(entry->res); -- -- if (entry->offset) { -- dev_err(dev, "PCI addr: %llx must be equal to CPU addr: %llx\n", -- pci_addr, cpu_addr); -- return -EINVAL; -- } -- -- while (size > 0) { -- /* -- * Try to find a minimum BAR whose size is greater than -- * or equal to the remaining resource_entry size. This will -- * fail if the size of each of the available BARs is less than -- * the remaining resource_entry size. -- * If a minimum BAR is found, IB ATU will be configured and -- * exited. -- */ -- bar = cdns_pcie_host_find_min_bar(rc, size); -- if (bar != RP_BAR_UNDEFINED) { -- ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, -- size, flags); -- if (ret) -- dev_err(dev, "IB BAR: %d config failed\n", bar); -- return ret; -- } -- -- /* -- * If the control reaches here, it would mean the remaining -- * resource_entry size cannot be fitted in a single BAR. So we -- * find a maximum BAR whose size is less than or equal to the -- * remaining resource_entry size and split the resource entry -- * so that part of resource entry is fitted inside the maximum -- * BAR. The remaining size would be fitted during the next -- * iteration of the loop. -- * If a maximum BAR is not found, there is no way we can fit -- * this resource_entry, so we error out. -- */ -- bar = cdns_pcie_host_find_max_bar(rc, size); -- if (bar == RP_BAR_UNDEFINED) { -- dev_err(dev, "No free BAR to map cpu_addr %llx\n", -- cpu_addr); -- return -EINVAL; -- } -- -- winsize = bar_max_size[bar]; -- ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, winsize, -- flags); -- if (ret) { -- dev_err(dev, "IB BAR: %d config failed\n", bar); -- return ret; -- } -- -- size -= winsize; -- cpu_addr += winsize; -- } -- -- return 0; --} -- --static int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, -- const struct list_head *b) --{ -- struct resource_entry *entry1, *entry2; -- -- entry1 = container_of(a, struct resource_entry, node); -- entry2 = container_of(b, struct resource_entry, node); -- -- return resource_size(entry2->res) - resource_size(entry1->res); --} -- - static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) - { - struct cdns_pcie *pcie = &rc->pcie; -@@ -447,43 +222,6 @@ static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) - } - } - --static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc) --{ -- struct cdns_pcie *pcie = &rc->pcie; -- struct device *dev = pcie->dev; -- struct device_node *np = dev->of_node; -- struct pci_host_bridge *bridge; -- struct resource_entry *entry; -- u32 no_bar_nbits = 32; -- int err; -- -- bridge = pci_host_bridge_from_priv(rc); -- if (!bridge) -- return -ENOMEM; -- -- if (list_empty(&bridge->dma_ranges)) { -- of_property_read_u32(np, "cdns,no-bar-match-nbits", -- &no_bar_nbits); -- err = cdns_pcie_host_bar_ib_config(rc, RP_NO_BAR, 0x0, -- (u64)1 << no_bar_nbits, 0); -- if (err) -- dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); -- return err; -- } -- -- list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); -- -- resource_list_for_each_entry(entry, &bridge->dma_ranges) { -- err = cdns_pcie_host_bar_config(rc, entry); -- if (err) { -- dev_err(dev, "Fail to configure IB using dma-ranges\n"); -- return err; -- } -- } -- -- return 0; --} -- - static void cdns_pcie_host_deinit_address_translation(struct cdns_pcie_rc *rc) - { - struct cdns_pcie *pcie = &rc->pcie; -@@ -561,7 +299,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) - r++; - } - -- return cdns_pcie_host_map_dma_ranges(rc); -+ return cdns_pcie_host_map_dma_ranges(rc, cdns_pcie_host_bar_ib_config); - } - - static void cdns_pcie_host_deinit(struct cdns_pcie_rc *rc) -@@ -607,7 +345,7 @@ int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) - return ret; - } - -- ret = cdns_pcie_host_start_link(rc); -+ ret = cdns_pcie_host_start_link(rc, cdns_pcie_link_up); - if (ret) - dev_dbg(dev, "PCIe link never came up\n"); - --- -2.53.0 - diff --git a/SPECS/linux-lts/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch b/SPECS/linux-lts/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch new file mode 100644 index 0000000000..e6e34a7195 --- /dev/null +++ b/SPECS/linux-lts/0148-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch @@ -0,0 +1,52 @@ +From 821bb874c9ee51f801501a53f0bfaff22992f2fb Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:00 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: s32: move PHY_INTF_SEL_x + definitions out of the way + +S32's PHY_INTF_SEL_x definitions conflict with those for the dwmac +cores as they use a different bitmapping. Add a S32 prefix so that +they are unique. + +Signed-off-by: Russell King (Oracle) +Reviewed-by: Maxime Chevallier +Reviewed-by: Jan Petrous (OSS) +Link: https://patch.msgid.link/E1vFt4S-0000000ChoS-2Ahi@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit 553f23d1953527eb277efa902cd498131b2527e1) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +index ee095ac13203..2b7ad64bfdf7 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +@@ -24,10 +24,10 @@ + #define GMAC_INTF_RATE_125M 125000000 /* 125MHz */ + + /* SoC PHY interface control register */ +-#define PHY_INTF_SEL_MII 0x00 +-#define PHY_INTF_SEL_SGMII 0x01 +-#define PHY_INTF_SEL_RGMII 0x02 +-#define PHY_INTF_SEL_RMII 0x08 ++#define S32_PHY_INTF_SEL_MII 0x00 ++#define S32_PHY_INTF_SEL_SGMII 0x01 ++#define S32_PHY_INTF_SEL_RGMII 0x02 ++#define S32_PHY_INTF_SEL_RMII 0x08 + + struct s32_priv_data { + void __iomem *ioaddr; +@@ -40,7 +40,7 @@ struct s32_priv_data { + + static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac) + { +- writel(PHY_INTF_SEL_RGMII, gmac->ctrl_sts); ++ writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); + + dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode)); + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0149-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch b/SPECS/linux-lts/0149-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch deleted file mode 100644 index 44809270c8..0000000000 --- a/SPECS/linux-lts/0149-UPSTREAM-PCI-cadence-Add-support-for-High-Perf-Archi.patch +++ /dev/null @@ -1,1127 +0,0 @@ -From 22b6ed1bca264e8e9b80d9630a7c430722561bec Mon Sep 17 00:00:00 2001 -From: Manikandan K Pillai -Date: Sat, 8 Nov 2025 22:02:59 +0800 -Subject: [PATCH 149/467] UPSTREAM: PCI: cadence: Add support for High Perf - Architecture (HPA) controller - -Add support for Cadence PCIe RP configuration for High Performance -Architecture (HPA) controllers. The Cadence High Performance controllers -are the latest PCIe controllers that have support for DMA, optional IDE -and updated register set. Add a common library for High Performance -Architecture (HPA) PCIe controllers. - -Signed-off-by: Manikandan K Pillai -Signed-off-by: Manivannan Sadhasivam -[bhelgaas: squash https://lore.kernel.org/r/20251120093518.2760492-1-jiapeng.chong@linux.alibaba.com, -squash https://lore.kernel.org/all/52abaad8-a43e-4e29-93d7-86a3245692c3@cixtech.com/] -Signed-off-by: Bjorn Helgaas -Link: https://patch.msgid.link/20251108140305.1120117-5-hans.zhang@cixtech.com -(cherry picked from commit 8babd8afe58a65c8d3cb9b5a6a8d24d4f93033ab) -Signed-off-by: Han Gao ---- - drivers/pci/controller/cadence/Makefile | 4 +- - .../cadence/pcie-cadence-host-hpa.c | 368 ++++++++++++++++++ - .../cadence/pcie-cadence-hpa-regs.h | 193 +++++++++ - .../pci/controller/cadence/pcie-cadence-hpa.c | 167 ++++++++ - .../controller/cadence/pcie-cadence-plat.c | 4 - - drivers/pci/controller/cadence/pcie-cadence.c | 11 + - drivers/pci/controller/cadence/pcie-cadence.h | 187 ++++++++- - 7 files changed, 913 insertions(+), 21 deletions(-) - create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-hpa.c - create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h - create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa.c - -diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile -index 91ffdbfd3aaa..30189045a166 100644 ---- a/drivers/pci/controller/cadence/Makefile -+++ b/drivers/pci/controller/cadence/Makefile -@@ -1,6 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0 --pcie-cadence-mod-y := pcie-cadence.o --pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o -+pcie-cadence-mod-y := pcie-cadence-hpa.o pcie-cadence.o -+pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o pcie-cadence-host-hpa.o - pcie-cadence-ep-mod-y := pcie-cadence-ep.o - - obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o -diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c -new file mode 100644 -index 000000000000..0f540bed58e8 ---- /dev/null -+++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c -@@ -0,0 +1,368 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Cadence PCIe host controller driver. -+ * -+ * Copyright (c) 2024, Cadence Design Systems -+ * Author: Manikandan K Pillai -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pcie-cadence.h" -+#include "pcie-cadence-host-common.h" -+ -+static u8 bar_aperture_mask[] = { -+ [RP_BAR0] = 0x3F, -+ [RP_BAR1] = 0x3F, -+}; -+ -+void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, -+ int where) -+{ -+ struct pci_host_bridge *bridge = pci_find_host_bridge(bus); -+ struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); -+ struct cdns_pcie *pcie = &rc->pcie; -+ unsigned int busn = bus->number; -+ u32 addr0, desc0, desc1, ctrl0; -+ u32 regval; -+ -+ if (pci_is_root_bus(bus)) { -+ /* -+ * Only the root port (devfn == 0) is connected to this bus. -+ * All other PCI devices are behind some bridge hence on another -+ * bus. -+ */ -+ if (devfn) -+ return NULL; -+ -+ return pcie->reg_base + (where & 0xfff); -+ } -+ -+ /* Clear AXI link-down status */ -+ regval = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN, -+ (regval & ~GENMASK(0, 0))); -+ -+ /* Update Output registers for AXI region 0 */ -+ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(12) | -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) | -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(busn); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), addr0); -+ -+ desc1 = cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0)); -+ desc1 &= ~CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK; -+ desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); -+ ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; -+ -+ if (busn == bridge->busnr + 1) -+ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0; -+ else -+ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1; -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), desc0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), ctrl0); -+ -+ return rc->cfg_base + (where & 0xfff); -+} -+ -+static struct pci_ops cdns_pcie_hpa_host_ops = { -+ .map_bus = cdns_pci_hpa_map_bus, -+ .read = pci_generic_config_read, -+ .write = pci_generic_config_write, -+}; -+ -+static void cdns_pcie_hpa_host_enable_ptm_response(struct cdns_pcie *pcie) -+{ -+ u32 val; -+ -+ val = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL, -+ val | CDNS_PCIE_HPA_LM_PTM_CTRL_PTMRSEN); -+} -+ -+static int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc, -+ enum cdns_pcie_rp_bar bar, -+ u64 cpu_addr, u64 size, -+ unsigned long flags) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ u32 addr0, addr1, aperture, value; -+ -+ if (!rc->avail_ib_bar[bar]) -+ return -ENODEV; -+ -+ rc->avail_ib_bar[bar] = false; -+ -+ aperture = ilog2(size); -+ if (bar == RP_NO_BAR) { -+ addr0 = CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(aperture) | -+ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); -+ addr1 = upper_32_bits(cpu_addr); -+ } else { -+ addr0 = lower_32_bits(cpu_addr); -+ addr1 = upper_32_bits(cpu_addr); -+ } -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, -+ CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar), addr0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, -+ CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar), addr1); -+ -+ if (bar == RP_NO_BAR) -+ bar = (enum cdns_pcie_rp_bar)BAR_0; -+ -+ value = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_BAR_CFG); -+ value &= ~(HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) | -+ HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) | -+ HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) | -+ HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) | -+ HPA_LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 7)); -+ if (size + cpu_addr >= SZ_4G) { -+ value |= HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar); -+ if ((flags & IORESOURCE_PREFETCH)) -+ value |= HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar); -+ } else { -+ value |= HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar); -+ if ((flags & IORESOURCE_PREFETCH)) -+ value |= HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar); -+ } -+ -+ value |= HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_BAR_CFG, value); -+ -+ return 0; -+} -+ -+static int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ u32 value, ctrl; -+ -+ /* -+ * Set the root port BAR configuration register: -+ * - disable both BAR0 and BAR1 -+ * - enable Prefetchable Memory Base and Limit registers in type 1 -+ * config space (64 bits) -+ * - enable IO Base and Limit registers in type 1 config -+ * space (32 bits) -+ */ -+ -+ ctrl = CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED; -+ value = CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) | -+ CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) | -+ CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE | -+ CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS | -+ CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE | -+ CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS; -+ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, -+ CDNS_PCIE_HPA_LM_RC_BAR_CFG, value); -+ -+ if (rc->vendor_id != 0xffff) -+ cdns_pcie_hpa_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id); -+ -+ if (rc->device_id != 0xffff) -+ cdns_pcie_hpa_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); -+ -+ cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_REVISION, 0); -+ cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_PROG, 0); -+ cdns_pcie_hpa_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); -+ -+ /* Enable bus mastering */ -+ value = cdns_pcie_hpa_readl(pcie, REG_BANK_RP, PCI_COMMAND); -+ value |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_RP, PCI_COMMAND, value); -+ return 0; -+} -+ -+static void cdns_pcie_hpa_create_region_for_cfg(struct cdns_pcie_rc *rc) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc); -+ struct resource *cfg_res = rc->cfg_res; -+ struct resource_entry *entry; -+ u64 cpu_addr = cfg_res->start; -+ u32 addr0, addr1, desc1; -+ int busnr = 0; -+ -+ entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); -+ if (entry) -+ busnr = entry->res->start; -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_TAG_MANAGEMENT, 0x01000000); -+ /* -+ * Reserve region 0 for PCI configure space accesses: -+ * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by -+ * cdns_pci_map_bus(), other region registers are set here once for all -+ */ -+ desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), 0x0); -+ /* Type-1 CFG */ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), 0x05000000); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); -+ -+ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(12) | -+ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); -+ addr1 = upper_32_bits(cpu_addr); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), addr0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), addr1); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), 0x06000000); -+} -+ -+static int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc *rc) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc); -+ struct resource_entry *entry; -+ int r = 0, busnr = 0; -+ -+ if (!rc->ecam_supported) -+ cdns_pcie_hpa_create_region_for_cfg(rc); -+ -+ entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); -+ if (entry) -+ busnr = entry->res->start; -+ -+ r++; -+ if (pcie->msg_res) { -+ cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, busnr, 0, r, -+ pcie->msg_res->start); -+ -+ r++; -+ } -+ resource_list_for_each_entry(entry, &bridge->windows) { -+ struct resource *res = entry->res; -+ u64 pci_addr = res->start - entry->offset; -+ -+ if (resource_type(res) == IORESOURCE_IO) -+ cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, -+ true, -+ pci_pio_to_address(res->start), -+ pci_addr, -+ resource_size(res)); -+ else -+ cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, -+ false, -+ res->start, -+ pci_addr, -+ resource_size(res)); -+ -+ r++; -+ } -+ -+ if (rc->no_inbound_map) -+ return 0; -+ else -+ return cdns_pcie_host_map_dma_ranges(rc, cdns_pcie_hpa_host_bar_ib_config); -+} -+ -+static int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc) -+{ -+ int err; -+ -+ err = cdns_pcie_hpa_host_init_root_port(rc); -+ if (err) -+ return err; -+ -+ return cdns_pcie_hpa_host_init_address_translation(rc); -+} -+ -+int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc) -+{ -+ struct cdns_pcie *pcie = &rc->pcie; -+ struct device *dev = rc->pcie.dev; -+ int ret; -+ -+ if (rc->quirk_detect_quiet_flag) -+ cdns_pcie_hpa_detect_quiet_min_delay_set(&rc->pcie); -+ -+ cdns_pcie_hpa_host_enable_ptm_response(pcie); -+ -+ ret = cdns_pcie_start_link(pcie); -+ if (ret) { -+ dev_err(dev, "Failed to start link\n"); -+ return ret; -+ } -+ -+ ret = cdns_pcie_host_wait_for_link(pcie, cdns_pcie_hpa_link_up); -+ if (ret) -+ dev_dbg(dev, "PCIe link never came up\n"); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup); -+ -+int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) -+{ -+ struct device *dev = rc->pcie.dev; -+ struct platform_device *pdev = to_platform_device(dev); -+ struct pci_host_bridge *bridge; -+ enum cdns_pcie_rp_bar bar; -+ struct cdns_pcie *pcie; -+ struct resource *res; -+ int ret; -+ -+ bridge = pci_host_bridge_from_priv(rc); -+ if (!bridge) -+ return -ENOMEM; -+ -+ pcie = &rc->pcie; -+ pcie->is_rc = true; -+ -+ if (!pcie->reg_base) { -+ pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg"); -+ if (IS_ERR(pcie->reg_base)) { -+ dev_err(dev, "missing \"reg\"\n"); -+ return PTR_ERR(pcie->reg_base); -+ } -+ } -+ -+ /* ECAM config space is remapped at glue layer */ -+ if (!rc->cfg_base) { -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); -+ rc->cfg_base = devm_pci_remap_cfg_resource(dev, res); -+ if (IS_ERR(rc->cfg_base)) -+ return PTR_ERR(rc->cfg_base); -+ rc->cfg_res = res; -+ } -+ -+ /* Put EROM Bar aperture to 0 */ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_EROM, 0x0); -+ -+ ret = cdns_pcie_hpa_host_link_setup(rc); -+ if (ret) -+ return ret; -+ -+ for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) -+ rc->avail_ib_bar[bar] = true; -+ -+ ret = cdns_pcie_hpa_host_init(rc); -+ if (ret) -+ return ret; -+ -+ if (!bridge->ops) -+ bridge->ops = &cdns_pcie_hpa_host_ops; -+ -+ return pci_host_probe(bridge); -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_setup); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Cadence PCIe host controller driver"); -diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h -new file mode 100644 -index 000000000000..026e131600de ---- /dev/null -+++ b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h -@@ -0,0 +1,193 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Cadence PCIe controller driver. -+ * -+ * Copyright (c) 2024, Cadence Design Systems -+ * Author: Manikandan K Pillai -+ */ -+#ifndef _PCIE_CADENCE_HPA_REGS_H -+#define _PCIE_CADENCE_HPA_REGS_H -+ -+#include -+#include -+#include -+#include -+#include -+ -+/* High Performance Architecture (HPA) PCIe controller registers */ -+#define CDNS_PCIE_HPA_IP_REG_BANK 0x01000000 -+#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x01003C00 -+#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0x02020000 -+ -+/* Address Translation Registers */ -+#define CDNS_PCIE_HPA_AXI_SLAVE 0x03000000 -+#define CDNS_PCIE_HPA_AXI_MASTER 0x03002000 -+ -+/* Root Port register base address */ -+#define CDNS_PCIE_HPA_RP_BASE 0x0 -+ -+#define CDNS_PCIE_HPA_LM_ID 0x1420 -+ -+/* Endpoint Function BARs */ -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \ -+ (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \ -+ CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn)) -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) (0x4000 * (pfn)) -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) ((0x4000 * (pfn)) + 0x04) -+#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \ -+ (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \ -+ CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn)) -+#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) ((0x4000 * (vfn)) + 0x08) -+#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) ((0x4000 * (vfn)) + 0x0C) -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \ -+ (GENMASK(5, 0) << (0x4 + (f) * 10)) -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ -+ (((a) << (4 + ((b) * 10))) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))) -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \ -+ (GENMASK(3, 0) << ((f) * 10)) -+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ -+ (((c) << ((b) * 10)) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))) -+ -+/* Endpoint Function Configuration Register */ -+#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG 0x02C0 -+ -+/* Root Complex BAR Configuration Register */ -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG 0x14 -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(9, 4) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ -+ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK, a) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(3, 0) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \ -+ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(19, 14) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ -+ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK, a) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(13, 10) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \ -+ FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c) -+ -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(20) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(21) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE BIT(22) -+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS BIT(23) -+ -+/* BAR control values applicable to both Endpoint Function and Root Complex */ -+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED 0x0 -+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS 0x3 -+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS 0x1 -+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x9 -+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS 0x5 -+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0xD -+ -+#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ -+ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10)) -+#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ -+ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10)) -+#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ -+ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10)) -+#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ -+ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10)) -+#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ -+ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10)) -+#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ -+ (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10)) -+#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture) \ -+ (((aperture) - 7) << (((bar) * 10) + 4)) -+ -+#define CDNS_PCIE_HPA_LM_PTM_CTRL 0x0520 -+#define CDNS_PCIE_HPA_LM_PTM_CTRL_PTMRSEN BIT(17) -+ -+/* Root Port Registers PCI config space for root port function */ -+#define CDNS_PCIE_HPA_RP_CAP_OFFSET 0xC0 -+ -+/* Region r Outbound AXI to PCIe Address Translation Register 0 */ -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) (0x1010 + ((r) & 0x1F) * 0x0080) -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ -+ (((nbits) - 1) & CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(23, 16) -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK, devfn) -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(31, 24) -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK, bus) -+ -+/* Region r Outbound AXI to PCIe Address Translation Register 1 */ -+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) (0x1014 + ((r) & 0x1F) * 0x0080) -+ -+/* Region r Outbound PCIe Descriptor Register */ -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) (0x1008 + ((r) & 0x1F) * 0x0080) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(28, 24) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10) -+ -+/* Region r Outbound PCIe Descriptor Register */ -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) (0x100C + ((r) & 0x1F) * 0x0080) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK GENMASK(31, 24) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK, bus) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK GENMASK(23, 16) -+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \ -+ FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK, devfn) -+ -+#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) (0x1018 + ((r) & 0x1F) * 0x0080) -+#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26) -+#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25) -+ -+/* Region r AXI Region Base Address Register 0 */ -+#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) (0x1000 + ((r) & 0x1F) * 0x0080) -+#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) -+#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ -+ (((nbits) - 1) & CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) -+ -+/* Region r AXI Region Base Address Register 1 */ -+#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) (0x1004 + ((r) & 0x1F) * 0x0080) -+ -+/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ -+#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) (((bar) * 0x0008)) -+#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) -+#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ -+ (((nbits) - 1) & CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK) -+#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) (0x04 + ((bar) * 0x0008)) -+ -+/* AXI link down register */ -+#define CDNS_PCIE_HPA_AT_LINKDOWN 0x04 -+ -+/* -+ * Physical Layer Configuration Register 0 -+ * This register contains the parameters required for functional setup -+ * of Physical Layer. -+ */ -+#define CDNS_PCIE_HPA_PHY_LAYER_CFG0 0x0400 -+#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK GENMASK(26, 24) -+#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \ -+ FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK, delay) -+#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK GENMASK(27, 27) -+ -+#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0 0x0420 -+ -+#define CDNS_PCIE_HPA_RP_MAX_IB 0x3 -+#define CDNS_PCIE_HPA_MAX_OB 15 -+ -+/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */ -+#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) (((fn) * 0x0080) + ((bar) * 0x0008)) -+#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) (0x4 + ((fn) * 0x0080) + ((bar) * 0x0008)) -+ -+/* Miscellaneous offsets definitions */ -+#define CDNS_PCIE_HPA_TAG_MANAGEMENT 0x0 -+#define CDNS_PCIE_HPA_SLAVE_RESP 0x100 -+ -+#define I_ROOT_PORT_REQ_ID_REG 0x141c -+#define LM_HAL_SBSA_CTRL 0x1170 -+ -+#define I_PCIE_BUS_NUMBERS (CDNS_PCIE_HPA_RP_BASE + 0x18) -+#define CDNS_PCIE_EROM 0x18 -+#endif /* _PCIE_CADENCE_HPA_REGS_H */ -diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa.c b/drivers/pci/controller/cadence/pcie-cadence-hpa.c -new file mode 100644 -index 000000000000..f60a16938265 ---- /dev/null -+++ b/drivers/pci/controller/cadence/pcie-cadence-hpa.c -@@ -0,0 +1,167 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Cadence PCIe controller driver. -+ * -+ * Copyright (c) 2024, Cadence Design Systems -+ * Author: Manikandan K Pillai -+ */ -+#include -+#include -+ -+#include "pcie-cadence.h" -+ -+bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie) -+{ -+ u32 pl_reg_val; -+ -+ pl_reg_val = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_DBG_STS_REG0); -+ if (pl_reg_val & GENMASK(0, 0)) -+ return true; -+ return false; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_link_up); -+ -+void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie) -+{ -+ u32 delay = 0x3; -+ u32 ltssm_control_cap; -+ -+ /* Set the LTSSM Detect Quiet state min. delay to 2ms */ -+ ltssm_control_cap = cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, -+ CDNS_PCIE_HPA_PHY_LAYER_CFG0); -+ ltssm_control_cap = ((ltssm_control_cap & -+ ~CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK) | -+ CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay)); -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, -+ CDNS_PCIE_HPA_PHY_LAYER_CFG0, ltssm_control_cap); -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_detect_quiet_min_delay_set); -+ -+void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, -+ u32 r, bool is_io, -+ u64 cpu_addr, u64 pci_addr, size_t size) -+{ -+ /* -+ * roundup_pow_of_two() returns an unsigned long, which is not suited -+ * for 64bit values -+ */ -+ u64 sz = 1ULL << fls64(size - 1); -+ int nbits = ilog2(sz); -+ u32 addr0, addr1, desc0, desc1, ctrl0; -+ -+ if (nbits < 8) -+ nbits = 8; -+ -+ /* Set the PCI address */ -+ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) | -+ (lower_32_bits(pci_addr) & GENMASK(31, 8)); -+ addr1 = upper_32_bits(pci_addr); -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), addr0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), addr1); -+ -+ /* Set the PCIe header descriptor */ -+ if (is_io) -+ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO; -+ else -+ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM; -+ desc1 = 0; -+ ctrl0 = 0; -+ -+ /* -+ * Whether Bit [26] is set or not inside DESC0 register of the outbound -+ * PCIe descriptor, the PCI function number must be set into -+ * Bits [31:24] of DESC1 anyway. -+ * -+ * In Root Complex mode, the function number is always 0 but in Endpoint -+ * mode, the PCIe controller may support more than one function. This -+ * function number needs to be set properly into the outbound PCIe -+ * descriptor. -+ * -+ * Besides, setting Bit [26] is mandatory when in Root Complex mode: -+ * then the driver must provide the bus, resp. device, number in -+ * Bits [31:24] of DESC1, resp. Bits[23:16] of DESC0. Like the function -+ * number, the device number is always 0 in Root Complex mode. -+ * -+ * However when in Endpoint mode, we can clear Bit [26] of DESC0, hence -+ * the PCIe controller will use the captured values for the bus and -+ * device numbers. -+ */ -+ if (pcie->is_rc) { -+ /* The device and function numbers are always 0 */ -+ desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); -+ ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; -+ } else { -+ /* -+ * Use captured values for bus and device numbers but still -+ * need to set the function number -+ */ -+ desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); -+ } -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); -+ -+ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | -+ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); -+ addr1 = upper_32_bits(cpu_addr); -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region); -+ -+void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, -+ u8 busnr, u8 fn, -+ u32 r, u64 cpu_addr) -+{ -+ u32 addr0, addr1, desc0, desc1, ctrl0; -+ -+ desc0 = CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG; -+ desc1 = 0; -+ ctrl0 = 0; -+ -+ /* See cdns_pcie_set_outbound_region() comments above */ -+ if (pcie->is_rc) { -+ desc1 = CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); -+ ctrl0 = CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; -+ } else { -+ desc1 |= CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); -+ } -+ -+ addr0 = CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(17) | -+ (lower_32_bits(cpu_addr) & GENMASK(31, 8)); -+ addr1 = upper_32_bits(cpu_addr); -+ -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); -+ cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, -+ CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region_for_normal_msg); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Cadence PCIe controller driver"); -diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c -index ebd5c3afdfcd..b067a3296dd3 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence-plat.c -+++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c -@@ -22,10 +22,6 @@ struct cdns_plat_pcie { - struct cdns_pcie *pcie; - }; - --struct cdns_plat_pcie_of_data { -- bool is_rc; --}; -- - static const struct of_device_id cdns_plat_pcie_of_match[]; - - static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) -diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c -index fb88a7ade412..a1eada56edba 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence.c -+++ b/drivers/pci/controller/cadence/pcie-cadence.c -@@ -23,6 +23,17 @@ u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) - } - EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability); - -+bool cdns_pcie_linkup(struct cdns_pcie *pcie) -+{ -+ u32 pl_reg_val; -+ -+ pl_reg_val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE); -+ if (pl_reg_val & GENMASK(0, 0)) -+ return true; -+ return false; -+} -+EXPORT_SYMBOL_GPL(cdns_pcie_linkup); -+ - void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) - { - u32 delay = 0x3; -diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h -index 23aa64df1980..277f3706a4f4 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence.h -+++ b/drivers/pci/controller/cadence/pcie-cadence.h -@@ -12,6 +12,7 @@ - #include - #include - #include "pcie-cadence-lga-regs.h" -+#include "pcie-cadence-hpa-regs.h" - - enum cdns_pcie_rp_bar { - RP_BAR_UNDEFINED = -1, -@@ -26,18 +27,57 @@ struct cdns_pcie_rp_ib_bar { - }; - - struct cdns_pcie; -+struct cdns_pcie_rc; -+ -+enum cdns_pcie_reg_bank { -+ REG_BANK_RP, -+ REG_BANK_IP_REG, -+ REG_BANK_IP_CFG_CTRL_REG, -+ REG_BANK_AXI_MASTER_COMMON, -+ REG_BANK_AXI_MASTER, -+ REG_BANK_AXI_SLAVE, -+ REG_BANK_AXI_HLS, -+ REG_BANK_AXI_RAS, -+ REG_BANK_AXI_DTI, -+ REG_BANKS_MAX, -+}; - - struct cdns_pcie_ops { -- int (*start_link)(struct cdns_pcie *pcie); -- void (*stop_link)(struct cdns_pcie *pcie); -- bool (*link_up)(struct cdns_pcie *pcie); -+ int (*start_link)(struct cdns_pcie *pcie); -+ void (*stop_link)(struct cdns_pcie *pcie); -+ bool (*link_up)(struct cdns_pcie *pcie); - u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); - }; - -+/** -+ * struct cdns_plat_pcie_of_data - Register bank offset for a platform -+ * @is_rc: controller is a RC -+ * @ip_reg_bank_offset: ip register bank start offset -+ * @ip_cfg_ctrl_reg_offset: ip config control register start offset -+ * @axi_mstr_common_offset: AXI master common register start offset -+ * @axi_slave_offset: AXI slave start offset -+ * @axi_master_offset: AXI master start offset -+ * @axi_hls_offset: AXI HLS offset start -+ * @axi_ras_offset: AXI RAS offset -+ * @axi_dti_offset: AXI DTI offset -+ */ -+struct cdns_plat_pcie_of_data { -+ u32 is_rc:1; -+ u32 ip_reg_bank_offset; -+ u32 ip_cfg_ctrl_reg_offset; -+ u32 axi_mstr_common_offset; -+ u32 axi_slave_offset; -+ u32 axi_master_offset; -+ u32 axi_hls_offset; -+ u32 axi_ras_offset; -+ u32 axi_dti_offset; -+}; -+ - /** - * struct cdns_pcie - private data for Cadence PCIe controller drivers - * @reg_base: IO mapped register base - * @mem_res: start/end offsets in the physical system memory to map PCI accesses -+ * @msg_res: Region for send message to map PCI accesses - * @dev: PCIe controller - * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint. - * @phy_count: number of supported PHY devices -@@ -45,16 +85,19 @@ struct cdns_pcie_ops { - * @link: list of pointers to corresponding device link representations - * @ops: Platform-specific ops to control various inputs from Cadence PCIe - * wrapper -+ * @cdns_pcie_reg_offsets: Register bank offsets for different SoC - */ - struct cdns_pcie { -- void __iomem *reg_base; -- struct resource *mem_res; -- struct device *dev; -- bool is_rc; -- int phy_count; -- struct phy **phy; -- struct device_link **link; -- const struct cdns_pcie_ops *ops; -+ void __iomem *reg_base; -+ struct resource *mem_res; -+ struct resource *msg_res; -+ struct device *dev; -+ bool is_rc; -+ int phy_count; -+ struct phy **phy; -+ struct device_link **link; -+ const struct cdns_pcie_ops *ops; -+ const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; - }; - - /** -@@ -70,6 +113,8 @@ struct cdns_pcie { - * available - * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 - * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk -+ * @ecam_supported: Whether the ECAM is supported -+ * @no_inbound_map: Whether inbound mapping is supported - */ - struct cdns_pcie_rc { - struct cdns_pcie pcie; -@@ -80,6 +125,8 @@ struct cdns_pcie_rc { - bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; - unsigned int quirk_retrain_flag:1; - unsigned int quirk_detect_quiet_flag:1; -+ unsigned int ecam_supported:1; -+ unsigned int no_inbound_map:1; - }; - - /** -@@ -132,6 +179,43 @@ struct cdns_pcie_ep { - unsigned int quirk_disable_flr:1; - }; - -+static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_pcie_reg_bank bank) -+{ -+ u32 offset = 0x0; -+ -+ switch (bank) { -+ case REG_BANK_RP: -+ offset = 0; -+ break; -+ case REG_BANK_IP_REG: -+ offset = pcie->cdns_pcie_reg_offsets->ip_reg_bank_offset; -+ break; -+ case REG_BANK_IP_CFG_CTRL_REG: -+ offset = pcie->cdns_pcie_reg_offsets->ip_cfg_ctrl_reg_offset; -+ break; -+ case REG_BANK_AXI_MASTER_COMMON: -+ offset = pcie->cdns_pcie_reg_offsets->axi_mstr_common_offset; -+ break; -+ case REG_BANK_AXI_MASTER: -+ offset = pcie->cdns_pcie_reg_offsets->axi_master_offset; -+ break; -+ case REG_BANK_AXI_SLAVE: -+ offset = pcie->cdns_pcie_reg_offsets->axi_slave_offset; -+ break; -+ case REG_BANK_AXI_HLS: -+ offset = pcie->cdns_pcie_reg_offsets->axi_hls_offset; -+ break; -+ case REG_BANK_AXI_RAS: -+ offset = pcie->cdns_pcie_reg_offsets->axi_ras_offset; -+ break; -+ case REG_BANK_AXI_DTI: -+ offset = pcie->cdns_pcie_reg_offsets->axi_dti_offset; -+ break; -+ default: -+ break; -+ } -+ return offset; -+} - - /* Register access */ - static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) -@@ -144,6 +228,27 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) - return readl(pcie->reg_base + reg); - } - -+static inline void cdns_pcie_hpa_writel(struct cdns_pcie *pcie, -+ enum cdns_pcie_reg_bank bank, -+ u32 reg, -+ u32 value) -+{ -+ u32 offset = cdns_reg_bank_to_off(pcie, bank); -+ -+ reg += offset; -+ writel(value, pcie->reg_base + reg); -+} -+ -+static inline u32 cdns_pcie_hpa_readl(struct cdns_pcie *pcie, -+ enum cdns_pcie_reg_bank bank, -+ u32 reg) -+{ -+ u32 offset = cdns_reg_bank_to_off(pcie, bank); -+ -+ reg += offset; -+ return readl(pcie->reg_base + reg); -+} -+ - static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) - { - void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); -@@ -233,6 +338,29 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) - return cdns_pcie_read_sz(addr, 0x2); - } - -+static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie, -+ u32 reg, u8 value) -+{ -+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; -+ -+ cdns_pcie_write_sz(addr, 0x1, value); -+} -+ -+static inline void cdns_pcie_hpa_rp_writew(struct cdns_pcie *pcie, -+ u32 reg, u16 value) -+{ -+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; -+ -+ cdns_pcie_write_sz(addr, 0x2, value); -+} -+ -+static inline u16 cdns_pcie_hpa_rp_readw(struct cdns_pcie *pcie, u32 reg) -+{ -+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; -+ -+ return cdns_pcie_read_sz(addr, 0x2); -+} -+ - /* Endpoint Function register access */ - static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, - u32 reg, u8 value) -@@ -297,6 +425,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); - void cdns_pcie_host_disable(struct cdns_pcie_rc *rc); - void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, - int where); -+int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc); - #else - static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) - { -@@ -313,6 +442,11 @@ static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) - return 0; - } - -+static inline int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) -+{ -+ return 0; -+} -+ - static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc) - { - } -@@ -327,6 +461,7 @@ static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int d - #if IS_ENABLED(CONFIG_PCIE_CADENCE_EP) - int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); - void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep); -+int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep); - #else - static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) - { -@@ -336,10 +471,17 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) - static inline void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep) - { - } -+ -+static inline int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep) -+{ -+ return 0; -+} -+ - #endif - --u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); --u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); -+u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); -+u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); -+bool cdns_pcie_linkup(struct cdns_pcie *pcie); - - void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); - -@@ -353,8 +495,23 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, - - void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); - void cdns_pcie_disable_phy(struct cdns_pcie *pcie); --int cdns_pcie_enable_phy(struct cdns_pcie *pcie); --int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); -+int cdns_pcie_enable_phy(struct cdns_pcie *pcie); -+int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); -+void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie); -+void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, -+ u32 r, bool is_io, -+ u64 cpu_addr, u64 pci_addr, size_t size); -+void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, -+ u8 busnr, u8 fn, -+ u32 r, u64 cpu_addr); -+int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc); -+void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, -+ int where); -+int cdns_pcie_hpa_host_start_link(struct cdns_pcie_rc *rc); -+int cdns_pcie_hpa_start_link(struct cdns_pcie *pcie); -+void cdns_pcie_hpa_stop_link(struct cdns_pcie *pcie); -+bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie); -+ - extern const struct dev_pm_ops cdns_pcie_pm_ops; - - #endif /* _PCIE_CADENCE_H */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch b/SPECS/linux-lts/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch new file mode 100644 index 0000000000..2109b174e4 --- /dev/null +++ b/SPECS/linux-lts/0149-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch @@ -0,0 +1,44 @@ +From 90e4dd06e790973bb6661abbcb3f3e584ec56f1e Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:05 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: add phy_intf_sel and ACTPHYIF + definitions + +Add definitions for the active PHY interface found in DMA hardware +feature register 0, and also used to configure the core in multi- +interface designs via phy_intf_sel. + +Signed-off-by: Russell King (Oracle) +Reviewed-by: Maxime Chevallier +Link: https://patch.msgid.link/E1vFt4X-0000000ChoY-30p9@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit 4a4692e9091867dd413764c7d81f09e8109a233a) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/common.h | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h +index acd7719506b6..a14df4269292 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/common.h ++++ b/drivers/net/ethernet/stmicro/stmmac/common.h +@@ -314,6 +314,16 @@ struct stmmac_safety_stats { + #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ + #define DEFAULT_DMA_PBL 8 + ++/* phy_intf_sel_i and ACTPHYIF encodings */ ++#define PHY_INTF_SEL_GMII_MII 0 ++#define PHY_INTF_SEL_RGMII 1 ++#define PHY_INTF_SEL_SGMII 2 ++#define PHY_INTF_SEL_TBI 3 ++#define PHY_INTF_SEL_RMII 4 ++#define PHY_INTF_SEL_RTBI 5 ++#define PHY_INTF_SEL_SMII 6 ++#define PHY_INTF_SEL_REVMII 7 ++ + /* MSI defines */ + #define STMMAC_MSI_VEC_MAX 32 + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch b/SPECS/linux-lts/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch new file mode 100644 index 0000000000..9a20bd485f --- /dev/null +++ b/SPECS/linux-lts/0150-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch @@ -0,0 +1,68 @@ +From 624275e49ff1dc397c4e821f30d8afcc4c8f621e Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:10 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: add stmmac_get_phy_intf_sel() + +Provide a function to translate the PHY interface mode to the +phy_intf_sel pin configuration for dwmac1000 and dwmac4 cores that +support multiple interfaces. We currently handle MII, GMII, RGMII, +SGMII, RMII and REVMII, but not TBI, RTBI nor SMII as drivers do not +appear to use these three and the driver doesn't currently support +these. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt4c-0000000Choe-3SII@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit b459790d3fd6d7ead31182ae0cd8632fe79deed6) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 + + .../net/ethernet/stmicro/stmmac/stmmac_main.c | 20 +++++++++++++++++++ + 2 files changed, 21 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h +index 865531d6cd3b..a628b5039448 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h +@@ -395,6 +395,7 @@ void stmmac_ptp_register(struct stmmac_priv *priv); + void stmmac_ptp_unregister(struct stmmac_priv *priv); + int stmmac_xdp_open(struct net_device *dev); + void stmmac_xdp_release(struct net_device *dev); ++int stmmac_get_phy_intf_sel(phy_interface_t interface); + int stmmac_resume(struct device *dev); + int stmmac_suspend(struct device *dev); + void stmmac_dvr_remove(struct device *dev); +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +index 41b270a48630..efe313a59b33 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +@@ -3035,6 +3035,26 @@ static void stmmac_check_ether_addr(struct stmmac_priv *priv) + } + } + ++int stmmac_get_phy_intf_sel(phy_interface_t interface) ++{ ++ int phy_intf_sel = -EINVAL; ++ ++ if (interface == PHY_INTERFACE_MODE_MII || ++ interface == PHY_INTERFACE_MODE_GMII) ++ phy_intf_sel = PHY_INTF_SEL_GMII_MII; ++ else if (phy_interface_mode_is_rgmii(interface)) ++ phy_intf_sel = PHY_INTF_SEL_RGMII; ++ else if (interface == PHY_INTERFACE_MODE_SGMII) ++ phy_intf_sel = PHY_INTF_SEL_SGMII; ++ else if (interface == PHY_INTERFACE_MODE_RMII) ++ phy_intf_sel = PHY_INTF_SEL_RMII; ++ else if (interface == PHY_INTERFACE_MODE_REVMII) ++ phy_intf_sel = PHY_INTF_SEL_REVMII; ++ ++ return phy_intf_sel; ++} ++EXPORT_SYMBOL_GPL(stmmac_get_phy_intf_sel); ++ + /** + * stmmac_init_dma_engine - DMA init. + * @priv: driver private structure +-- +2.53.0 + diff --git a/SPECS/linux-lts/0150-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch b/SPECS/linux-lts/0150-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch deleted file mode 100644 index 58b32f5050..0000000000 --- a/SPECS/linux-lts/0150-UPSTREAM-net-stmmac-imx-use-phylink-s-interface-mode.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 3fc48954f60468b378e31495b8a6b8c77c81f5f1 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:49:55 +0000 -Subject: [PATCH 150/467] UPSTREAM: net: stmmac: imx: use phylink's interface - mode for set_clk_tx_rate() - -imx_dwmac_set_clk_tx_rate() is passed the interface mode from phylink -which will be the same as plat_dat->phy_interface. Use the passed-in -interface mode rather than plat_dat->phy_interface. - -Reviewed-by: Maxime Chevallier -Tested-by: Maxime Chevallier -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt4N-0000000ChoM-1llp@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit dec568a36f9b16f0334aed8e95ec4225606830cc) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index 4268b9987237..147fa08d5b6e 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -195,9 +195,6 @@ static void imx_dwmac_exit(struct platform_device *pdev, void *priv) - static int imx_dwmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, - phy_interface_t interface, int speed) - { -- struct imx_priv_data *dwmac = bsp_priv; -- -- interface = dwmac->plat_dat->phy_interface; - if (interface == PHY_INTERFACE_MODE_RMII || - interface == PHY_INTERFACE_MODE_MII) - return 0; --- -2.53.0 - diff --git a/SPECS/linux-lts/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch b/SPECS/linux-lts/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch new file mode 100644 index 0000000000..b7fa7e6a46 --- /dev/null +++ b/SPECS/linux-lts/0151-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch @@ -0,0 +1,90 @@ +From f194dd514161599163226c56b2674969caea19ca Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:15 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: add support for configuring the + phy_intf_sel inputs + +When dwmac is synthesised with support for multiple PHY interfaces, the +core provides phy_intf_sel inputs, sampled on reset, to configure the +PHY facing interface. Use stmmac_get_phy_intf_sel() in core code to +determine the dwmac phy_intf_sel input value, and provide a new +platform method called with this value just before we issue a soft +reset to the dwmac core. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt4h-0000000Chos-3wxX@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit 1b6aa81c85621d6b55099906585ff09a477203b8) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/stmmac_main.c | 34 +++++++++++++++++++ + include/linux/stmmac.h | 1 + + 2 files changed, 35 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +index efe313a59b33..0f7fda75f7fe 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +@@ -3055,6 +3055,36 @@ int stmmac_get_phy_intf_sel(phy_interface_t interface) + } + EXPORT_SYMBOL_GPL(stmmac_get_phy_intf_sel); + ++static int stmmac_prereset_configure(struct stmmac_priv *priv) ++{ ++ struct plat_stmmacenet_data *plat_dat = priv->plat; ++ phy_interface_t interface; ++ int phy_intf_sel, ret; ++ ++ if (!plat_dat->set_phy_intf_sel) ++ return 0; ++ ++ interface = plat_dat->phy_interface; ++ phy_intf_sel = stmmac_get_phy_intf_sel(interface); ++ if (phy_intf_sel < 0) { ++ netdev_err(priv->dev, ++ "failed to get phy_intf_sel for %s: %pe\n", ++ phy_modes(interface), ERR_PTR(phy_intf_sel)); ++ return phy_intf_sel; ++ } ++ ++ ret = plat_dat->set_phy_intf_sel(plat_dat->bsp_priv, phy_intf_sel); ++ if (ret == -EINVAL) ++ netdev_err(priv->dev, "platform does not support %s\n", ++ phy_modes(interface)); ++ else if (ret < 0) ++ netdev_err(priv->dev, ++ "platform failed to set interface %s: %pe\n", ++ phy_modes(interface), ERR_PTR(ret)); ++ ++ return ret; ++} ++ + /** + * stmmac_init_dma_engine - DMA init. + * @priv: driver private structure +@@ -3081,6 +3111,10 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) + if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) + priv->plat->dma_cfg->atds = 1; + ++ ret = stmmac_prereset_configure(priv); ++ if (ret) ++ return ret; ++ + ret = stmmac_reset(priv, priv->ioaddr); + if (ret) { + netdev_err(priv->dev, "Failed to reset the dma\n"); +diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h +index 7e989d0edead..8cbac4559f96 100644 +--- a/include/linux/stmmac.h ++++ b/include/linux/stmmac.h +@@ -250,6 +250,7 @@ struct plat_stmmacenet_data { + struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; + void (*get_interfaces)(struct stmmac_priv *priv, void *bsp_priv, + unsigned long *interfaces); ++ int (*set_phy_intf_sel)(void *priv, u8 phy_intf_sel); + int (*set_clk_tx_rate)(void *priv, struct clk *clk_tx_i, + phy_interface_t interface, int speed); + void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0151-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch b/SPECS/linux-lts/0151-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch deleted file mode 100644 index ddbd2ddb3b..0000000000 --- a/SPECS/linux-lts/0151-UPSTREAM-net-stmmac-s32-move-PHY_INTF_SEL_x-definiti.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 1d729e5a3d02a0b30f4cc2145934e9ad02a2593c Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:00 +0000 -Subject: [PATCH 151/467] UPSTREAM: net: stmmac: s32: move PHY_INTF_SEL_x - definitions out of the way - -S32's PHY_INTF_SEL_x definitions conflict with those for the dwmac -cores as they use a different bitmapping. Add a S32 prefix so that -they are unique. - -Signed-off-by: Russell King (Oracle) -Reviewed-by: Maxime Chevallier -Reviewed-by: Jan Petrous (OSS) -Link: https://patch.msgid.link/E1vFt4S-0000000ChoS-2Ahi@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit 553f23d1953527eb277efa902cd498131b2527e1) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c -index ee095ac13203..2b7ad64bfdf7 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c -@@ -24,10 +24,10 @@ - #define GMAC_INTF_RATE_125M 125000000 /* 125MHz */ - - /* SoC PHY interface control register */ --#define PHY_INTF_SEL_MII 0x00 --#define PHY_INTF_SEL_SGMII 0x01 --#define PHY_INTF_SEL_RGMII 0x02 --#define PHY_INTF_SEL_RMII 0x08 -+#define S32_PHY_INTF_SEL_MII 0x00 -+#define S32_PHY_INTF_SEL_SGMII 0x01 -+#define S32_PHY_INTF_SEL_RGMII 0x02 -+#define S32_PHY_INTF_SEL_RMII 0x08 - - struct s32_priv_data { - void __iomem *ioaddr; -@@ -40,7 +40,7 @@ struct s32_priv_data { - - static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac) - { -- writel(PHY_INTF_SEL_RGMII, gmac->ctrl_sts); -+ writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts); - - dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode)); - --- -2.53.0 - diff --git a/SPECS/linux-lts/0152-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch b/SPECS/linux-lts/0152-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch deleted file mode 100644 index 89b1cdbb0e..0000000000 --- a/SPECS/linux-lts/0152-UPSTREAM-net-stmmac-add-phy_intf_sel-and-ACTPHYIF-de.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 5ac0d54cbe08eb88695ec8feda51f1e2f957ee10 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:05 +0000 -Subject: [PATCH 152/467] UPSTREAM: net: stmmac: add phy_intf_sel and ACTPHYIF - definitions - -Add definitions for the active PHY interface found in DMA hardware -feature register 0, and also used to configure the core in multi- -interface designs via phy_intf_sel. - -Signed-off-by: Russell King (Oracle) -Reviewed-by: Maxime Chevallier -Link: https://patch.msgid.link/E1vFt4X-0000000ChoY-30p9@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit 4a4692e9091867dd413764c7d81f09e8109a233a) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/common.h | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h -index acd7719506b6..a14df4269292 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/common.h -+++ b/drivers/net/ethernet/stmicro/stmmac/common.h -@@ -314,6 +314,16 @@ struct stmmac_safety_stats { - #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ - #define DEFAULT_DMA_PBL 8 - -+/* phy_intf_sel_i and ACTPHYIF encodings */ -+#define PHY_INTF_SEL_GMII_MII 0 -+#define PHY_INTF_SEL_RGMII 1 -+#define PHY_INTF_SEL_SGMII 2 -+#define PHY_INTF_SEL_TBI 3 -+#define PHY_INTF_SEL_RMII 4 -+#define PHY_INTF_SEL_RTBI 5 -+#define PHY_INTF_SEL_SMII 6 -+#define PHY_INTF_SEL_REVMII 7 -+ - /* MSI defines */ - #define STMMAC_MSI_VEC_MAX 32 - --- -2.53.0 - diff --git a/SPECS/linux-lts/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch b/SPECS/linux-lts/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch new file mode 100644 index 0000000000..9563df2a93 --- /dev/null +++ b/SPECS/linux-lts/0152-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch @@ -0,0 +1,70 @@ +From 89d282d18f9a93cdff176ee6469c67a8b11cb528 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:21 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: convert to PHY_INTF_SEL_xxx + +Convert dwmac-imx to use the PHY_INTF_SEL_xxx definitions rather than +constants via: +- ensuring that the prefix for the MASK and value definitions is the + same. +- using FIELD_PREP() to shift the PHY_INTF_SEL_xxx definition to the + appropriate bitfield. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt4n-0000000Choy-0IeG@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit 8233cc439779eac1d2682d334c1aa6bb6d95120c) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 23 ++++++++++++------- + 1 file changed, 15 insertions(+), 8 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index 147fa08d5b6e..4fbee59e7337 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -23,18 +23,25 @@ + #include "stmmac_platform.h" + + #define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16) +-#define GPR_ENET_QOS_INTF_SEL_MII (0x0 << 16) +-#define GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 16) +-#define GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 16) ++#define GPR_ENET_QOS_INTF_SEL_MASK GENMASK(20, 16) ++#define GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ ++ PHY_INTF_SEL_GMII_MII) ++#define GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ ++ PHY_INTF_SEL_RMII) ++#define GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ ++ PHY_INTF_SEL_RGMII) + #define GPR_ENET_QOS_CLK_GEN_EN (0x1 << 19) + #define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20) + #define GPR_ENET_QOS_RGMII_EN (0x1 << 21) + + #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0) +-#define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1) +-#define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1) +-#define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1) +-#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1) ++#define MX93_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(3, 1) ++#define MX93_GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ ++ PHY_INTF_SEL_GMII_MII) ++#define MX93_GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ ++ PHY_INTF_SEL_RMII) ++#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ ++ PHY_INTF_SEL_RGMII) + #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) + #define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0) + #define MX93_GPR_CLK_SEL_OFFSET (4) +@@ -241,7 +248,7 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode) + if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface)) + return; + +- iface &= MX93_GPR_ENET_QOS_INTF_MASK; ++ iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; + if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII) + return; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0153-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch b/SPECS/linux-lts/0153-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch deleted file mode 100644 index 7628db8ba4..0000000000 --- a/SPECS/linux-lts/0153-UPSTREAM-net-stmmac-add-stmmac_get_phy_intf_sel.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 43838e019c5010025e2e2c06687a7e97c3153717 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:10 +0000 -Subject: [PATCH 153/467] UPSTREAM: net: stmmac: add stmmac_get_phy_intf_sel() - -Provide a function to translate the PHY interface mode to the -phy_intf_sel pin configuration for dwmac1000 and dwmac4 cores that -support multiple interfaces. We currently handle MII, GMII, RGMII, -SGMII, RMII and REVMII, but not TBI, RTBI nor SMII as drivers do not -appear to use these three and the driver doesn't currently support -these. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt4c-0000000Choe-3SII@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit b459790d3fd6d7ead31182ae0cd8632fe79deed6) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 + - .../net/ethernet/stmicro/stmmac/stmmac_main.c | 20 +++++++++++++++++++ - 2 files changed, 21 insertions(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h -index 865531d6cd3b..a628b5039448 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h -@@ -395,6 +395,7 @@ void stmmac_ptp_register(struct stmmac_priv *priv); - void stmmac_ptp_unregister(struct stmmac_priv *priv); - int stmmac_xdp_open(struct net_device *dev); - void stmmac_xdp_release(struct net_device *dev); -+int stmmac_get_phy_intf_sel(phy_interface_t interface); - int stmmac_resume(struct device *dev); - int stmmac_suspend(struct device *dev); - void stmmac_dvr_remove(struct device *dev); -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -index 41b270a48630..efe313a59b33 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -3035,6 +3035,26 @@ static void stmmac_check_ether_addr(struct stmmac_priv *priv) - } - } - -+int stmmac_get_phy_intf_sel(phy_interface_t interface) -+{ -+ int phy_intf_sel = -EINVAL; -+ -+ if (interface == PHY_INTERFACE_MODE_MII || -+ interface == PHY_INTERFACE_MODE_GMII) -+ phy_intf_sel = PHY_INTF_SEL_GMII_MII; -+ else if (phy_interface_mode_is_rgmii(interface)) -+ phy_intf_sel = PHY_INTF_SEL_RGMII; -+ else if (interface == PHY_INTERFACE_MODE_SGMII) -+ phy_intf_sel = PHY_INTF_SEL_SGMII; -+ else if (interface == PHY_INTERFACE_MODE_RMII) -+ phy_intf_sel = PHY_INTF_SEL_RMII; -+ else if (interface == PHY_INTERFACE_MODE_REVMII) -+ phy_intf_sel = PHY_INTF_SEL_REVMII; -+ -+ return phy_intf_sel; -+} -+EXPORT_SYMBOL_GPL(stmmac_get_phy_intf_sel); -+ - /** - * stmmac_init_dma_engine - DMA init. - * @priv: driver private structure --- -2.53.0 - diff --git a/SPECS/linux-lts/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch b/SPECS/linux-lts/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch new file mode 100644 index 0000000000..3546e04959 --- /dev/null +++ b/SPECS/linux-lts/0153-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch @@ -0,0 +1,151 @@ +From cc8ade8e3e83180c2b2c2458f61161c29f310f53 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:26 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use FIELD_PREP()/FIELD_GET() + for PHY_INTF_SEL_x + +Use FIELD_PREP()/FIELD_GET() in the functions to construct the PHY +interface selection bitfield or to extract its value. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt4s-0000000Chp4-0kwf@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit d73c1dccfb9909f0e2d517af887fe414ab421cea) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 44 +++++++++---------- + 1 file changed, 20 insertions(+), 24 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index 4fbee59e7337..f1cfccd4269c 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -24,24 +24,12 @@ + + #define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16) + #define GPR_ENET_QOS_INTF_SEL_MASK GENMASK(20, 16) +-#define GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ +- PHY_INTF_SEL_GMII_MII) +-#define GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ +- PHY_INTF_SEL_RMII) +-#define GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ +- PHY_INTF_SEL_RGMII) + #define GPR_ENET_QOS_CLK_GEN_EN (0x1 << 19) + #define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20) + #define GPR_ENET_QOS_RGMII_EN (0x1 << 21) + + #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0) + #define MX93_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(3, 1) +-#define MX93_GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ +- PHY_INTF_SEL_GMII_MII) +-#define MX93_GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ +- PHY_INTF_SEL_RMII) +-#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ +- PHY_INTF_SEL_RGMII) + #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) + #define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0) + #define MX93_GPR_CLK_SEL_OFFSET (4) +@@ -77,22 +65,24 @@ struct imx_priv_data { + static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + { + struct imx_priv_data *dwmac = plat_dat->bsp_priv; ++ u8 phy_intf_sel; + int val; + + switch (plat_dat->phy_interface) { + case PHY_INTERFACE_MODE_MII: +- val = GPR_ENET_QOS_INTF_SEL_MII; ++ phy_intf_sel = PHY_INTF_SEL_GMII_MII; ++ val = 0; + break; + case PHY_INTERFACE_MODE_RMII: +- val = GPR_ENET_QOS_INTF_SEL_RMII; +- val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL); ++ phy_intf_sel = PHY_INTF_SEL_RMII; ++ val = dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: +- val = GPR_ENET_QOS_INTF_SEL_RGMII | +- GPR_ENET_QOS_RGMII_EN; ++ phy_intf_sel = PHY_INTF_SEL_RGMII; ++ val = GPR_ENET_QOS_RGMII_EN; + break; + default: + pr_debug("imx dwmac doesn't support %s interface\n", +@@ -100,7 +90,9 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + return -EINVAL; + } + +- val |= GPR_ENET_QOS_CLK_GEN_EN; ++ val |= FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | ++ GPR_ENET_QOS_CLK_GEN_EN; ++ + return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, + GPR_ENET_QOS_INTF_MODE_MASK, val); + }; +@@ -117,11 +109,12 @@ imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + { + struct imx_priv_data *dwmac = plat_dat->bsp_priv; ++ u8 phy_intf_sel; + int val, ret; + + switch (plat_dat->phy_interface) { + case PHY_INTERFACE_MODE_MII: +- val = MX93_GPR_ENET_QOS_INTF_SEL_MII; ++ phy_intf_sel = PHY_INTF_SEL_GMII_MII; + break; + case PHY_INTERFACE_MODE_RMII: + if (dwmac->rmii_refclk_ext) { +@@ -132,13 +125,13 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + if (ret) + return ret; + } +- val = MX93_GPR_ENET_QOS_INTF_SEL_RMII; ++ phy_intf_sel = PHY_INTF_SEL_RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: +- val = MX93_GPR_ENET_QOS_INTF_SEL_RGMII; ++ phy_intf_sel = PHY_INTF_SEL_RGMII; + break; + default: + dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n", +@@ -146,7 +139,9 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + return -EINVAL; + } + +- val |= MX93_GPR_ENET_QOS_CLK_GEN_EN; ++ val = FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | ++ MX93_GPR_ENET_QOS_CLK_GEN_EN; ++ + return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, + MX93_GPR_ENET_QOS_INTF_MODE_MASK, val); + }; +@@ -248,8 +243,8 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode) + if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface)) + return; + +- iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; +- if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII) ++ if (FIELD_GET(MX93_GPR_ENET_QOS_INTF_SEL_MASK, iface) != ++ PHY_INTF_SEL_RGMII) + return; + + old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG); +@@ -262,6 +257,7 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode) + readl(dwmac->base_addr + MAC_CTRL_REG); + + usleep_range(10, 20); ++ iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; + iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN; + regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, + MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0154-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch b/SPECS/linux-lts/0154-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch deleted file mode 100644 index e57e4171fb..0000000000 --- a/SPECS/linux-lts/0154-UPSTREAM-net-stmmac-add-support-for-configuring-the-.patch +++ /dev/null @@ -1,90 +0,0 @@ -From ea8b437fd179a8f307c0e49128898b0424718763 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:15 +0000 -Subject: [PATCH 154/467] UPSTREAM: net: stmmac: add support for configuring - the phy_intf_sel inputs - -When dwmac is synthesised with support for multiple PHY interfaces, the -core provides phy_intf_sel inputs, sampled on reset, to configure the -PHY facing interface. Use stmmac_get_phy_intf_sel() in core code to -determine the dwmac phy_intf_sel input value, and provide a new -platform method called with this value just before we issue a soft -reset to the dwmac core. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt4h-0000000Chos-3wxX@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit 1b6aa81c85621d6b55099906585ff09a477203b8) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/stmmac_main.c | 34 +++++++++++++++++++ - include/linux/stmmac.h | 1 + - 2 files changed, 35 insertions(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -index efe313a59b33..0f7fda75f7fe 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -3055,6 +3055,36 @@ int stmmac_get_phy_intf_sel(phy_interface_t interface) - } - EXPORT_SYMBOL_GPL(stmmac_get_phy_intf_sel); - -+static int stmmac_prereset_configure(struct stmmac_priv *priv) -+{ -+ struct plat_stmmacenet_data *plat_dat = priv->plat; -+ phy_interface_t interface; -+ int phy_intf_sel, ret; -+ -+ if (!plat_dat->set_phy_intf_sel) -+ return 0; -+ -+ interface = plat_dat->phy_interface; -+ phy_intf_sel = stmmac_get_phy_intf_sel(interface); -+ if (phy_intf_sel < 0) { -+ netdev_err(priv->dev, -+ "failed to get phy_intf_sel for %s: %pe\n", -+ phy_modes(interface), ERR_PTR(phy_intf_sel)); -+ return phy_intf_sel; -+ } -+ -+ ret = plat_dat->set_phy_intf_sel(plat_dat->bsp_priv, phy_intf_sel); -+ if (ret == -EINVAL) -+ netdev_err(priv->dev, "platform does not support %s\n", -+ phy_modes(interface)); -+ else if (ret < 0) -+ netdev_err(priv->dev, -+ "platform failed to set interface %s: %pe\n", -+ phy_modes(interface), ERR_PTR(ret)); -+ -+ return ret; -+} -+ - /** - * stmmac_init_dma_engine - DMA init. - * @priv: driver private structure -@@ -3081,6 +3111,10 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) - if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) - priv->plat->dma_cfg->atds = 1; - -+ ret = stmmac_prereset_configure(priv); -+ if (ret) -+ return ret; -+ - ret = stmmac_reset(priv, priv->ioaddr); - if (ret) { - netdev_err(priv->dev, "Failed to reset the dma\n"); -diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h -index 7e989d0edead..8cbac4559f96 100644 ---- a/include/linux/stmmac.h -+++ b/include/linux/stmmac.h -@@ -250,6 +250,7 @@ struct plat_stmmacenet_data { - struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; - void (*get_interfaces)(struct stmmac_priv *priv, void *bsp_priv, - unsigned long *interfaces); -+ int (*set_phy_intf_sel)(void *priv, u8 phy_intf_sel); - int (*set_clk_tx_rate)(void *priv, struct clk *clk_tx_i, - phy_interface_t interface, int speed); - void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); --- -2.53.0 - diff --git a/SPECS/linux-lts/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch b/SPECS/linux-lts/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch new file mode 100644 index 0000000000..133ab7846d --- /dev/null +++ b/SPECS/linux-lts/0154-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch @@ -0,0 +1,140 @@ +From c242a53cab013ff50b42785236d0b703b63c9e37 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:31 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use + stmmac_get_phy_intf_sel() + +i.MX implementations other than IMX8DXL involve setting the dwmac core +phy_intf_sel input. Use stmmac_get_phy_intf_sel() to decode the PHY +interface mode to the phy_intf_sel value, validating the result, and +passing it into the implementation specific .set_intf_mode() method +rather than each .set_intf_mode() method doing this. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt4x-0000000ChpA-1Edr@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit c012710c14a70dfa21691e2542d18dd4b621c518) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 43 +++++++++++-------- + 1 file changed, 25 insertions(+), 18 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index f1cfccd4269c..dc28486a7af0 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -45,7 +45,8 @@ struct imx_dwmac_ops { + bool mac_rgmii_txclk_auto_adj; + + int (*fix_soc_reset)(struct stmmac_priv *priv, void __iomem *ioaddr); +- int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat); ++ int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat, ++ u8 phy_intf_sel); + void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); + }; + +@@ -62,26 +63,23 @@ struct imx_priv_data { + struct plat_stmmacenet_data *plat_dat; + }; + +-static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) ++static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, ++ u8 phy_intf_sel) + { + struct imx_priv_data *dwmac = plat_dat->bsp_priv; +- u8 phy_intf_sel; + int val; + + switch (plat_dat->phy_interface) { + case PHY_INTERFACE_MODE_MII: +- phy_intf_sel = PHY_INTF_SEL_GMII_MII; + val = 0; + break; + case PHY_INTERFACE_MODE_RMII: +- phy_intf_sel = PHY_INTF_SEL_RMII; + val = dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: +- phy_intf_sel = PHY_INTF_SEL_RGMII; + val = GPR_ENET_QOS_RGMII_EN; + break; + default: +@@ -98,7 +96,8 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + }; + + static int +-imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) ++imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat, ++ u8 phy_intf_sel) + { + int ret = 0; + +@@ -106,16 +105,13 @@ imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + return ret; + } + +-static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) ++static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat, ++ u8 phy_intf_sel) + { + struct imx_priv_data *dwmac = plat_dat->bsp_priv; +- u8 phy_intf_sel; + int val, ret; + + switch (plat_dat->phy_interface) { +- case PHY_INTERFACE_MODE_MII: +- phy_intf_sel = PHY_INTF_SEL_GMII_MII; +- break; + case PHY_INTERFACE_MODE_RMII: + if (dwmac->rmii_refclk_ext) { + ret = regmap_clear_bits(dwmac->intf_regmap, +@@ -125,13 +121,12 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) + if (ret) + return ret; + } +- phy_intf_sel = PHY_INTF_SEL_RMII; + break; ++ case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: +- phy_intf_sel = PHY_INTF_SEL_RGMII; + break; + default: + dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n", +@@ -176,12 +171,24 @@ static int imx_dwmac_init(struct platform_device *pdev, void *priv) + { + struct plat_stmmacenet_data *plat_dat; + struct imx_priv_data *dwmac = priv; +- int ret; +- +- plat_dat = dwmac->plat_dat; ++ phy_interface_t interface; ++ int phy_intf_sel, ret; + + if (dwmac->ops->set_intf_mode) { +- ret = dwmac->ops->set_intf_mode(plat_dat); ++ plat_dat = dwmac->plat_dat; ++ interface = plat_dat->phy_interface; ++ ++ phy_intf_sel = stmmac_get_phy_intf_sel(interface); ++ if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && ++ phy_intf_sel != PHY_INTF_SEL_RGMII && ++ phy_intf_sel != PHY_INTF_SEL_RMII) { ++ dev_dbg(dwmac->dev, ++ "imx dwmac doesn't support %s interface\n", ++ phy_modes(interface)); ++ return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; ++ } ++ ++ ret = dwmac->ops->set_intf_mode(plat_dat, phy_intf_sel); + if (ret) + return ret; + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0155-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch b/SPECS/linux-lts/0155-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch deleted file mode 100644 index 4686086a36..0000000000 --- a/SPECS/linux-lts/0155-UPSTREAM-net-stmmac-imx-convert-to-PHY_INTF_SEL_xxx.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 298cb039696cadbf544bfbe91d55631386fabfa1 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:21 +0000 -Subject: [PATCH 155/467] UPSTREAM: net: stmmac: imx: convert to - PHY_INTF_SEL_xxx - -Convert dwmac-imx to use the PHY_INTF_SEL_xxx definitions rather than -constants via: -- ensuring that the prefix for the MASK and value definitions is the - same. -- using FIELD_PREP() to shift the PHY_INTF_SEL_xxx definition to the - appropriate bitfield. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt4n-0000000Choy-0IeG@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit 8233cc439779eac1d2682d334c1aa6bb6d95120c) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 23 ++++++++++++------- - 1 file changed, 15 insertions(+), 8 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index 147fa08d5b6e..4fbee59e7337 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -23,18 +23,25 @@ - #include "stmmac_platform.h" - - #define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16) --#define GPR_ENET_QOS_INTF_SEL_MII (0x0 << 16) --#define GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 16) --#define GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 16) -+#define GPR_ENET_QOS_INTF_SEL_MASK GENMASK(20, 16) -+#define GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ -+ PHY_INTF_SEL_GMII_MII) -+#define GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ -+ PHY_INTF_SEL_RMII) -+#define GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ -+ PHY_INTF_SEL_RGMII) - #define GPR_ENET_QOS_CLK_GEN_EN (0x1 << 19) - #define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20) - #define GPR_ENET_QOS_RGMII_EN (0x1 << 21) - - #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0) --#define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1) --#define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1) --#define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1) --#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1) -+#define MX93_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(3, 1) -+#define MX93_GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ -+ PHY_INTF_SEL_GMII_MII) -+#define MX93_GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ -+ PHY_INTF_SEL_RMII) -+#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ -+ PHY_INTF_SEL_RGMII) - #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) - #define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0) - #define MX93_GPR_CLK_SEL_OFFSET (4) -@@ -241,7 +248,7 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode) - if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface)) - return; - -- iface &= MX93_GPR_ENET_QOS_INTF_MASK; -+ iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; - if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII) - return; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch b/SPECS/linux-lts/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch new file mode 100644 index 0000000000..cc5171568d --- /dev/null +++ b/SPECS/linux-lts/0155-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch @@ -0,0 +1,114 @@ +From 38044c901de858463843f7c8cfab808a34627f56 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:36 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: simplify set_intf_mode() + implementations + +Simplify the set_intf_mode() implementations, testing the phy_intf_sel +value rather than the PHY interface mode. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt52-0000000ChpG-1bsd@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit 35103babce3036058cd9ed8674c98e9ab397d715) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 67 ++++++------------- + 1 file changed, 19 insertions(+), 48 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index dc28486a7af0..d69be9de4468 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -67,29 +67,15 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, + u8 phy_intf_sel) + { + struct imx_priv_data *dwmac = plat_dat->bsp_priv; +- int val; +- +- switch (plat_dat->phy_interface) { +- case PHY_INTERFACE_MODE_MII: +- val = 0; +- break; +- case PHY_INTERFACE_MODE_RMII: +- val = dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL; +- break; +- case PHY_INTERFACE_MODE_RGMII: +- case PHY_INTERFACE_MODE_RGMII_ID: +- case PHY_INTERFACE_MODE_RGMII_RXID: +- case PHY_INTERFACE_MODE_RGMII_TXID: +- val = GPR_ENET_QOS_RGMII_EN; +- break; +- default: +- pr_debug("imx dwmac doesn't support %s interface\n", +- phy_modes(plat_dat->phy_interface)); +- return -EINVAL; +- } ++ unsigned int val; + +- val |= FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | +- GPR_ENET_QOS_CLK_GEN_EN; ++ val = FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | ++ GPR_ENET_QOS_CLK_GEN_EN; ++ ++ if (phy_intf_sel == PHY_INTF_SEL_RMII && !dwmac->rmii_refclk_ext) ++ val |= GPR_ENET_QOS_CLK_TX_CLK_SEL; ++ else if (phy_intf_sel == PHY_INTF_SEL_RGMII) ++ val |= GPR_ENET_QOS_RGMII_EN; + + return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, + GPR_ENET_QOS_INTF_MODE_MASK, val); +@@ -99,39 +85,24 @@ static int + imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat, + u8 phy_intf_sel) + { +- int ret = 0; +- + /* TBD: depends on imx8dxl scu interfaces to be upstreamed */ +- return ret; ++ return 0; + } + + static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat, + u8 phy_intf_sel) + { + struct imx_priv_data *dwmac = plat_dat->bsp_priv; +- int val, ret; +- +- switch (plat_dat->phy_interface) { +- case PHY_INTERFACE_MODE_RMII: +- if (dwmac->rmii_refclk_ext) { +- ret = regmap_clear_bits(dwmac->intf_regmap, +- dwmac->intf_reg_off + +- MX93_GPR_CLK_SEL_OFFSET, +- MX93_GPR_ENET_QOS_CLK_SEL_MASK); +- if (ret) +- return ret; +- } +- break; +- case PHY_INTERFACE_MODE_MII: +- case PHY_INTERFACE_MODE_RGMII: +- case PHY_INTERFACE_MODE_RGMII_ID: +- case PHY_INTERFACE_MODE_RGMII_RXID: +- case PHY_INTERFACE_MODE_RGMII_TXID: +- break; +- default: +- dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n", +- phy_modes(plat_dat->phy_interface)); +- return -EINVAL; ++ unsigned int val; ++ int ret; ++ ++ if (phy_intf_sel == PHY_INTF_SEL_RMII && dwmac->rmii_refclk_ext) { ++ ret = regmap_clear_bits(dwmac->intf_regmap, ++ dwmac->intf_reg_off + ++ MX93_GPR_CLK_SEL_OFFSET, ++ MX93_GPR_ENET_QOS_CLK_SEL_MASK); ++ if (ret) ++ return ret; + } + + val = FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | +-- +2.53.0 + diff --git a/SPECS/linux-lts/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch b/SPECS/linux-lts/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch new file mode 100644 index 0000000000..7f2c908494 --- /dev/null +++ b/SPECS/linux-lts/0156-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch @@ -0,0 +1,100 @@ +From 3c89184f3302aafeabc618409bf916aa970f4f16 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:41 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: cleanup arguments for + set_intf_mode() method + +Pass the imx_priv_data instead of the plat_stmmacenet_data into the +set_intf_mode() SoC specific methods. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt57-0000000ChpL-25kS@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit 38cd4e84b369c11680966fdea129e11dbb28a6ec) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 22 +++++++------------ + 1 file changed, 8 insertions(+), 14 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index d69be9de4468..ae1b73e1bcb2 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -39,14 +39,15 @@ + #define RMII_RESET_SPEED (0x3 << 14) + #define CTRL_SPEED_MASK GENMASK(15, 14) + ++struct imx_priv_data; ++ + struct imx_dwmac_ops { + u32 addr_width; + u32 flags; + bool mac_rgmii_txclk_auto_adj; + + int (*fix_soc_reset)(struct stmmac_priv *priv, void __iomem *ioaddr); +- int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat, +- u8 phy_intf_sel); ++ int (*set_intf_mode)(struct imx_priv_data *dwmac, u8 phy_intf_sel); + void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); + }; + +@@ -63,10 +64,8 @@ struct imx_priv_data { + struct plat_stmmacenet_data *plat_dat; + }; + +-static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, +- u8 phy_intf_sel) ++static int imx8mp_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) + { +- struct imx_priv_data *dwmac = plat_dat->bsp_priv; + unsigned int val; + + val = FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | +@@ -82,17 +81,14 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, + }; + + static int +-imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat, +- u8 phy_intf_sel) ++imx8dxl_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) + { + /* TBD: depends on imx8dxl scu interfaces to be upstreamed */ + return 0; + } + +-static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat, +- u8 phy_intf_sel) ++static int imx93_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) + { +- struct imx_priv_data *dwmac = plat_dat->bsp_priv; + unsigned int val; + int ret; + +@@ -140,14 +136,12 @@ static int imx_dwmac_clks_config(void *priv, bool enabled) + + static int imx_dwmac_init(struct platform_device *pdev, void *priv) + { +- struct plat_stmmacenet_data *plat_dat; + struct imx_priv_data *dwmac = priv; + phy_interface_t interface; + int phy_intf_sel, ret; + + if (dwmac->ops->set_intf_mode) { +- plat_dat = dwmac->plat_dat; +- interface = plat_dat->phy_interface; ++ interface = dwmac->plat_dat->phy_interface; + + phy_intf_sel = stmmac_get_phy_intf_sel(interface); + if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && +@@ -159,7 +153,7 @@ static int imx_dwmac_init(struct platform_device *pdev, void *priv) + return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; + } + +- ret = dwmac->ops->set_intf_mode(plat_dat, phy_intf_sel); ++ ret = dwmac->ops->set_intf_mode(dwmac, phy_intf_sel); + if (ret) + return ret; + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0156-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch b/SPECS/linux-lts/0156-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch deleted file mode 100644 index ff69081e5a..0000000000 --- a/SPECS/linux-lts/0156-UPSTREAM-net-stmmac-imx-use-FIELD_PREP-FIELD_GET-for.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 96a2fbe70c985e615419f7e5872b429885c2832b Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:26 +0000 -Subject: [PATCH 156/467] UPSTREAM: net: stmmac: imx: use - FIELD_PREP()/FIELD_GET() for PHY_INTF_SEL_x - -Use FIELD_PREP()/FIELD_GET() in the functions to construct the PHY -interface selection bitfield or to extract its value. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt4s-0000000Chp4-0kwf@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit d73c1dccfb9909f0e2d517af887fe414ab421cea) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 44 +++++++++---------- - 1 file changed, 20 insertions(+), 24 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index 4fbee59e7337..f1cfccd4269c 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -24,24 +24,12 @@ - - #define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16) - #define GPR_ENET_QOS_INTF_SEL_MASK GENMASK(20, 16) --#define GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ -- PHY_INTF_SEL_GMII_MII) --#define GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ -- PHY_INTF_SEL_RMII) --#define GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, \ -- PHY_INTF_SEL_RGMII) - #define GPR_ENET_QOS_CLK_GEN_EN (0x1 << 19) - #define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20) - #define GPR_ENET_QOS_RGMII_EN (0x1 << 21) - - #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0) - #define MX93_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(3, 1) --#define MX93_GPR_ENET_QOS_INTF_SEL_MII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ -- PHY_INTF_SEL_GMII_MII) --#define MX93_GPR_ENET_QOS_INTF_SEL_RMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ -- PHY_INTF_SEL_RMII) --#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, \ -- PHY_INTF_SEL_RGMII) - #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) - #define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0) - #define MX93_GPR_CLK_SEL_OFFSET (4) -@@ -77,22 +65,24 @@ struct imx_priv_data { - static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - { - struct imx_priv_data *dwmac = plat_dat->bsp_priv; -+ u8 phy_intf_sel; - int val; - - switch (plat_dat->phy_interface) { - case PHY_INTERFACE_MODE_MII: -- val = GPR_ENET_QOS_INTF_SEL_MII; -+ phy_intf_sel = PHY_INTF_SEL_GMII_MII; -+ val = 0; - break; - case PHY_INTERFACE_MODE_RMII: -- val = GPR_ENET_QOS_INTF_SEL_RMII; -- val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL); -+ phy_intf_sel = PHY_INTF_SEL_RMII; -+ val = dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: -- val = GPR_ENET_QOS_INTF_SEL_RGMII | -- GPR_ENET_QOS_RGMII_EN; -+ phy_intf_sel = PHY_INTF_SEL_RGMII; -+ val = GPR_ENET_QOS_RGMII_EN; - break; - default: - pr_debug("imx dwmac doesn't support %s interface\n", -@@ -100,7 +90,9 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - return -EINVAL; - } - -- val |= GPR_ENET_QOS_CLK_GEN_EN; -+ val |= FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | -+ GPR_ENET_QOS_CLK_GEN_EN; -+ - return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, - GPR_ENET_QOS_INTF_MODE_MASK, val); - }; -@@ -117,11 +109,12 @@ imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - { - struct imx_priv_data *dwmac = plat_dat->bsp_priv; -+ u8 phy_intf_sel; - int val, ret; - - switch (plat_dat->phy_interface) { - case PHY_INTERFACE_MODE_MII: -- val = MX93_GPR_ENET_QOS_INTF_SEL_MII; -+ phy_intf_sel = PHY_INTF_SEL_GMII_MII; - break; - case PHY_INTERFACE_MODE_RMII: - if (dwmac->rmii_refclk_ext) { -@@ -132,13 +125,13 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - if (ret) - return ret; - } -- val = MX93_GPR_ENET_QOS_INTF_SEL_RMII; -+ phy_intf_sel = PHY_INTF_SEL_RMII; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: -- val = MX93_GPR_ENET_QOS_INTF_SEL_RGMII; -+ phy_intf_sel = PHY_INTF_SEL_RGMII; - break; - default: - dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n", -@@ -146,7 +139,9 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - return -EINVAL; - } - -- val |= MX93_GPR_ENET_QOS_CLK_GEN_EN; -+ val = FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | -+ MX93_GPR_ENET_QOS_CLK_GEN_EN; -+ - return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, - MX93_GPR_ENET_QOS_INTF_MODE_MASK, val); - }; -@@ -248,8 +243,8 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode) - if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface)) - return; - -- iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; -- if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII) -+ if (FIELD_GET(MX93_GPR_ENET_QOS_INTF_SEL_MASK, iface) != -+ PHY_INTF_SEL_RGMII) - return; - - old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG); -@@ -262,6 +257,7 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode) - readl(dwmac->base_addr + MAC_CTRL_REG); - - usleep_range(10, 20); -+ iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK; - iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN; - regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, - MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface); --- -2.53.0 - diff --git a/SPECS/linux-lts/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch b/SPECS/linux-lts/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch new file mode 100644 index 0000000000..20bb16df38 --- /dev/null +++ b/SPECS/linux-lts/0157-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch @@ -0,0 +1,80 @@ +From e0a6c2e873b5d2ba2e3a62461407c4523f488812 Mon Sep 17 00:00:00 2001 +From: "Russell King (Oracle)" +Date: Mon, 3 Nov 2025 11:50:46 +0000 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: imx: use ->set_phy_intf_sel() + +Rather than placing the phy_intf_sel() setup in the ->init() method, +move it to the new ->set_phy_intf_sel() method. + +Signed-off-by: Russell King (Oracle) +Link: https://patch.msgid.link/E1vFt5C-0000000ChpR-2kAB@rmk-PC.armlinux.org.uk +Signed-off-by: Jakub Kicinski +(cherry picked from commit eaca1a4dc51e5e4979e45a4ad72a1c2a88a80a72) +Signed-off-by: Han Gao +--- + .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 38 +++++-------------- + 1 file changed, 10 insertions(+), 28 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +index ae1b73e1bcb2..db288fbd5a4d 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +@@ -134,36 +134,19 @@ static int imx_dwmac_clks_config(void *priv, bool enabled) + return ret; + } + +-static int imx_dwmac_init(struct platform_device *pdev, void *priv) ++static int imx_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) + { +- struct imx_priv_data *dwmac = priv; +- phy_interface_t interface; +- int phy_intf_sel, ret; +- +- if (dwmac->ops->set_intf_mode) { +- interface = dwmac->plat_dat->phy_interface; +- +- phy_intf_sel = stmmac_get_phy_intf_sel(interface); +- if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && +- phy_intf_sel != PHY_INTF_SEL_RGMII && +- phy_intf_sel != PHY_INTF_SEL_RMII) { +- dev_dbg(dwmac->dev, +- "imx dwmac doesn't support %s interface\n", +- phy_modes(interface)); +- return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; +- } ++ struct imx_priv_data *dwmac = bsp_priv; + +- ret = dwmac->ops->set_intf_mode(dwmac, phy_intf_sel); +- if (ret) +- return ret; +- } ++ if (!dwmac->ops->set_intf_mode) ++ return 0; + +- return 0; +-} ++ if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && ++ phy_intf_sel != PHY_INTF_SEL_RGMII && ++ phy_intf_sel != PHY_INTF_SEL_RMII) ++ return -EINVAL; + +-static void imx_dwmac_exit(struct platform_device *pdev, void *priv) +-{ +- /* nothing to do now */ ++ return dwmac->ops->set_intf_mode(dwmac, phy_intf_sel); + } + + static int imx_dwmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, +@@ -342,8 +325,7 @@ static int imx_dwmac_probe(struct platform_device *pdev) + plat_dat->tx_queues_cfg[i].tbs_en = 1; + + plat_dat->host_dma_width = dwmac->ops->addr_width; +- plat_dat->init = imx_dwmac_init; +- plat_dat->exit = imx_dwmac_exit; ++ plat_dat->set_phy_intf_sel = imx_set_phy_intf_sel; + plat_dat->clks_config = imx_dwmac_clks_config; + plat_dat->bsp_priv = dwmac; + dwmac->plat_dat = plat_dat; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0157-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch b/SPECS/linux-lts/0157-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch deleted file mode 100644 index 948f2ff114..0000000000 --- a/SPECS/linux-lts/0157-UPSTREAM-net-stmmac-imx-use-stmmac_get_phy_intf_sel.patch +++ /dev/null @@ -1,140 +0,0 @@ -From a7b4a86b0a6221000c68f097653ff86de2485ea0 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:31 +0000 -Subject: [PATCH 157/467] UPSTREAM: net: stmmac: imx: use - stmmac_get_phy_intf_sel() - -i.MX implementations other than IMX8DXL involve setting the dwmac core -phy_intf_sel input. Use stmmac_get_phy_intf_sel() to decode the PHY -interface mode to the phy_intf_sel value, validating the result, and -passing it into the implementation specific .set_intf_mode() method -rather than each .set_intf_mode() method doing this. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt4x-0000000ChpA-1Edr@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit c012710c14a70dfa21691e2542d18dd4b621c518) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 43 +++++++++++-------- - 1 file changed, 25 insertions(+), 18 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index f1cfccd4269c..dc28486a7af0 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -45,7 +45,8 @@ struct imx_dwmac_ops { - bool mac_rgmii_txclk_auto_adj; - - int (*fix_soc_reset)(struct stmmac_priv *priv, void __iomem *ioaddr); -- int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat); -+ int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat, -+ u8 phy_intf_sel); - void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); - }; - -@@ -62,26 +63,23 @@ struct imx_priv_data { - struct plat_stmmacenet_data *plat_dat; - }; - --static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) -+static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, -+ u8 phy_intf_sel) - { - struct imx_priv_data *dwmac = plat_dat->bsp_priv; -- u8 phy_intf_sel; - int val; - - switch (plat_dat->phy_interface) { - case PHY_INTERFACE_MODE_MII: -- phy_intf_sel = PHY_INTF_SEL_GMII_MII; - val = 0; - break; - case PHY_INTERFACE_MODE_RMII: -- phy_intf_sel = PHY_INTF_SEL_RMII; - val = dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL; - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: -- phy_intf_sel = PHY_INTF_SEL_RGMII; - val = GPR_ENET_QOS_RGMII_EN; - break; - default: -@@ -98,7 +96,8 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - }; - - static int --imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) -+imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat, -+ u8 phy_intf_sel) - { - int ret = 0; - -@@ -106,16 +105,13 @@ imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - return ret; - } - --static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) -+static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat, -+ u8 phy_intf_sel) - { - struct imx_priv_data *dwmac = plat_dat->bsp_priv; -- u8 phy_intf_sel; - int val, ret; - - switch (plat_dat->phy_interface) { -- case PHY_INTERFACE_MODE_MII: -- phy_intf_sel = PHY_INTF_SEL_GMII_MII; -- break; - case PHY_INTERFACE_MODE_RMII: - if (dwmac->rmii_refclk_ext) { - ret = regmap_clear_bits(dwmac->intf_regmap, -@@ -125,13 +121,12 @@ static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat) - if (ret) - return ret; - } -- phy_intf_sel = PHY_INTF_SEL_RMII; - break; -+ case PHY_INTERFACE_MODE_MII: - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: -- phy_intf_sel = PHY_INTF_SEL_RGMII; - break; - default: - dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n", -@@ -176,12 +171,24 @@ static int imx_dwmac_init(struct platform_device *pdev, void *priv) - { - struct plat_stmmacenet_data *plat_dat; - struct imx_priv_data *dwmac = priv; -- int ret; -- -- plat_dat = dwmac->plat_dat; -+ phy_interface_t interface; -+ int phy_intf_sel, ret; - - if (dwmac->ops->set_intf_mode) { -- ret = dwmac->ops->set_intf_mode(plat_dat); -+ plat_dat = dwmac->plat_dat; -+ interface = plat_dat->phy_interface; -+ -+ phy_intf_sel = stmmac_get_phy_intf_sel(interface); -+ if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && -+ phy_intf_sel != PHY_INTF_SEL_RGMII && -+ phy_intf_sel != PHY_INTF_SEL_RMII) { -+ dev_dbg(dwmac->dev, -+ "imx dwmac doesn't support %s interface\n", -+ phy_modes(interface)); -+ return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; -+ } -+ -+ ret = dwmac->ops->set_intf_mode(plat_dat, phy_intf_sel); - if (ret) - return ret; - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0158-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch b/SPECS/linux-lts/0158-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch deleted file mode 100644 index 4fca5088f0..0000000000 --- a/SPECS/linux-lts/0158-UPSTREAM-net-stmmac-imx-simplify-set_intf_mode-imple.patch +++ /dev/null @@ -1,114 +0,0 @@ -From a4d4ff59a90369776a587bea80bb089b9b3ff2e4 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:36 +0000 -Subject: [PATCH 158/467] UPSTREAM: net: stmmac: imx: simplify set_intf_mode() - implementations - -Simplify the set_intf_mode() implementations, testing the phy_intf_sel -value rather than the PHY interface mode. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt52-0000000ChpG-1bsd@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit 35103babce3036058cd9ed8674c98e9ab397d715) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 67 ++++++------------- - 1 file changed, 19 insertions(+), 48 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index dc28486a7af0..d69be9de4468 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -67,29 +67,15 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, - u8 phy_intf_sel) - { - struct imx_priv_data *dwmac = plat_dat->bsp_priv; -- int val; -- -- switch (plat_dat->phy_interface) { -- case PHY_INTERFACE_MODE_MII: -- val = 0; -- break; -- case PHY_INTERFACE_MODE_RMII: -- val = dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL; -- break; -- case PHY_INTERFACE_MODE_RGMII: -- case PHY_INTERFACE_MODE_RGMII_ID: -- case PHY_INTERFACE_MODE_RGMII_RXID: -- case PHY_INTERFACE_MODE_RGMII_TXID: -- val = GPR_ENET_QOS_RGMII_EN; -- break; -- default: -- pr_debug("imx dwmac doesn't support %s interface\n", -- phy_modes(plat_dat->phy_interface)); -- return -EINVAL; -- } -+ unsigned int val; - -- val |= FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | -- GPR_ENET_QOS_CLK_GEN_EN; -+ val = FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | -+ GPR_ENET_QOS_CLK_GEN_EN; -+ -+ if (phy_intf_sel == PHY_INTF_SEL_RMII && !dwmac->rmii_refclk_ext) -+ val |= GPR_ENET_QOS_CLK_TX_CLK_SEL; -+ else if (phy_intf_sel == PHY_INTF_SEL_RGMII) -+ val |= GPR_ENET_QOS_RGMII_EN; - - return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, - GPR_ENET_QOS_INTF_MODE_MASK, val); -@@ -99,39 +85,24 @@ static int - imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat, - u8 phy_intf_sel) - { -- int ret = 0; -- - /* TBD: depends on imx8dxl scu interfaces to be upstreamed */ -- return ret; -+ return 0; - } - - static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat, - u8 phy_intf_sel) - { - struct imx_priv_data *dwmac = plat_dat->bsp_priv; -- int val, ret; -- -- switch (plat_dat->phy_interface) { -- case PHY_INTERFACE_MODE_RMII: -- if (dwmac->rmii_refclk_ext) { -- ret = regmap_clear_bits(dwmac->intf_regmap, -- dwmac->intf_reg_off + -- MX93_GPR_CLK_SEL_OFFSET, -- MX93_GPR_ENET_QOS_CLK_SEL_MASK); -- if (ret) -- return ret; -- } -- break; -- case PHY_INTERFACE_MODE_MII: -- case PHY_INTERFACE_MODE_RGMII: -- case PHY_INTERFACE_MODE_RGMII_ID: -- case PHY_INTERFACE_MODE_RGMII_RXID: -- case PHY_INTERFACE_MODE_RGMII_TXID: -- break; -- default: -- dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n", -- phy_modes(plat_dat->phy_interface)); -- return -EINVAL; -+ unsigned int val; -+ int ret; -+ -+ if (phy_intf_sel == PHY_INTF_SEL_RMII && dwmac->rmii_refclk_ext) { -+ ret = regmap_clear_bits(dwmac->intf_regmap, -+ dwmac->intf_reg_off + -+ MX93_GPR_CLK_SEL_OFFSET, -+ MX93_GPR_ENET_QOS_CLK_SEL_MASK); -+ if (ret) -+ return ret; - } - - val = FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | --- -2.53.0 - diff --git a/SPECS/linux-lts/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch b/SPECS/linux-lts/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch new file mode 100644 index 0000000000..f73e1f62b4 --- /dev/null +++ b/SPECS/linux-lts/0158-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch @@ -0,0 +1,59 @@ +From d219e86b2ba446033884ed9b3f3cb9d0edcd98ef Mon Sep 17 00:00:00 2001 +From: Nilay Shroff +Date: Fri, 20 Feb 2026 12:32:27 +0530 +Subject: [RUYI PATCH] UPSTREAM: powerpc/pci: Initialize msi_addr_mask for + OF-created PCI devices + +Recent changes replaced the use of no_64bit_msi with msi_addr_mask. As a +result, msi_addr_mask is now expected to be initialized to DMA_BIT_MASK(64) +when a pci_dev is set up. However, this initialization was missed on +powerpc due to differences in the device initialization path compared to +other (x86) architecture. Due to this, now PCI device probe method fails on +powerpc system. + +On powerpc systems, struct pci_dev instances are created from device tree +nodes via of_create_pci_dev(). Because msi_addr_mask was not initialized +there, it remained zero. Later, during MSI setup, msi_verify_entries() +validates the programmed MSI address against pdev->msi_addr_mask. Since the +mask was not set correctly, the validation fails, causing PCI driver probe +failures for devices on powerpc systems. + +Initialize pdev->msi_addr_mask to DMA_BIT_MASK(64) in of_create_pci_dev() +so that MSI address validation succeeds and device probe works as expected. + +Fixes: 386ced19e9a3 ("PCI/MSI: Convert the boolean no_64bit_msi flag to a DMA address mask") +Signed-off-by: Nilay Shroff +Signed-off-by: Bjorn Helgaas +Tested-by: Venkat Rao Bagalkote +Tested-by: Nam Cao +Reviewed-by: Nam Cao +Reviewed-by: Vivian Wang +Acked-by: Madhavan Srinivasan +Link: https://patch.msgid.link/20260220070239.1693303-2-nilay@linux.ibm.com +(cherry picked from commit 2185904ff8b5da76a4353e5d1236caa78e0d98e3) +Signed-off-by: Han Gao +--- + arch/powerpc/kernel/pci_of_scan.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c +index 756043dd06e9..fb9fbf0d1796 100644 +--- a/arch/powerpc/kernel/pci_of_scan.c ++++ b/arch/powerpc/kernel/pci_of_scan.c +@@ -212,6 +212,13 @@ struct pci_dev *of_create_pci_dev(struct device_node *node, + dev->error_state = pci_channel_io_normal; + dev->dma_mask = 0xffffffff; + ++ /* ++ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit ++ * if MSI (rather than MSI-X) capability does not have ++ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. ++ */ ++ dev->msi_addr_mask = DMA_BIT_MASK(64); ++ + /* Early fixups, before probing the BARs */ + pci_fixup_device(pci_fixup_early, dev); + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0159-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch b/SPECS/linux-lts/0159-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch deleted file mode 100644 index 416094c8bf..0000000000 --- a/SPECS/linux-lts/0159-UPSTREAM-net-stmmac-imx-cleanup-arguments-for-set_in.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 651b057371e02ed78100a1da8b724c5996480add Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:41 +0000 -Subject: [PATCH 159/467] UPSTREAM: net: stmmac: imx: cleanup arguments for - set_intf_mode() method - -Pass the imx_priv_data instead of the plat_stmmacenet_data into the -set_intf_mode() SoC specific methods. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt57-0000000ChpL-25kS@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit 38cd4e84b369c11680966fdea129e11dbb28a6ec) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 22 +++++++------------ - 1 file changed, 8 insertions(+), 14 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index d69be9de4468..ae1b73e1bcb2 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -39,14 +39,15 @@ - #define RMII_RESET_SPEED (0x3 << 14) - #define CTRL_SPEED_MASK GENMASK(15, 14) - -+struct imx_priv_data; -+ - struct imx_dwmac_ops { - u32 addr_width; - u32 flags; - bool mac_rgmii_txclk_auto_adj; - - int (*fix_soc_reset)(struct stmmac_priv *priv, void __iomem *ioaddr); -- int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat, -- u8 phy_intf_sel); -+ int (*set_intf_mode)(struct imx_priv_data *dwmac, u8 phy_intf_sel); - void (*fix_mac_speed)(void *priv, int speed, unsigned int mode); - }; - -@@ -63,10 +64,8 @@ struct imx_priv_data { - struct plat_stmmacenet_data *plat_dat; - }; - --static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, -- u8 phy_intf_sel) -+static int imx8mp_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) - { -- struct imx_priv_data *dwmac = plat_dat->bsp_priv; - unsigned int val; - - val = FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) | -@@ -82,17 +81,14 @@ static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat, - }; - - static int --imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat, -- u8 phy_intf_sel) -+imx8dxl_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) - { - /* TBD: depends on imx8dxl scu interfaces to be upstreamed */ - return 0; - } - --static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat, -- u8 phy_intf_sel) -+static int imx93_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel) - { -- struct imx_priv_data *dwmac = plat_dat->bsp_priv; - unsigned int val; - int ret; - -@@ -140,14 +136,12 @@ static int imx_dwmac_clks_config(void *priv, bool enabled) - - static int imx_dwmac_init(struct platform_device *pdev, void *priv) - { -- struct plat_stmmacenet_data *plat_dat; - struct imx_priv_data *dwmac = priv; - phy_interface_t interface; - int phy_intf_sel, ret; - - if (dwmac->ops->set_intf_mode) { -- plat_dat = dwmac->plat_dat; -- interface = plat_dat->phy_interface; -+ interface = dwmac->plat_dat->phy_interface; - - phy_intf_sel = stmmac_get_phy_intf_sel(interface); - if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && -@@ -159,7 +153,7 @@ static int imx_dwmac_init(struct platform_device *pdev, void *priv) - return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; - } - -- ret = dwmac->ops->set_intf_mode(plat_dat, phy_intf_sel); -+ ret = dwmac->ops->set_intf_mode(dwmac, phy_intf_sel); - if (ret) - return ret; - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch b/SPECS/linux-lts/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch new file mode 100644 index 0000000000..e75eecbde3 --- /dev/null +++ b/SPECS/linux-lts/0159-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch @@ -0,0 +1,51 @@ +From 9e9a5cb4c3cd15b6b321a0ec71d41d8318cfd254 Mon Sep 17 00:00:00 2001 +From: Nilay Shroff +Date: Fri, 20 Feb 2026 12:32:28 +0530 +Subject: [RUYI PATCH] UPSTREAM: sparc/PCI: Initialize msi_addr_mask for + OF-created PCI devices + +Recent changes replaced the use of no_64bit_msi with msi_addr_mask, which +is now expected to be initialized to DMA_BIT_MASK(64) during PCI device +setup. On SPARC systems, this initialization was inadvertently missed for +devices instantiated from device tree nodes, leaving msi_addr_mask unset +for OF-created pci_dev instances. As a result, MSI address validation fails +during probe, causing affected devices to fail initialization. + +Initialize pdev->msi_addr_mask to DMA_BIT_MASK(64) in of_create_pci_dev() +so that MSI address validation succeeds and PCI device probing works as +expected. + +Fixes: 386ced19e9a3 ("PCI/MSI: Convert the boolean no_64bit_msi flag to a DMA address mask") +Signed-off-by: Nilay Shroff +Signed-off-by: Bjorn Helgaas +Tested-by: Han Gao # SPARC Enterprise T5220 +Tested-by: Nathaniel Roach # SPARC T5-2 +Reviewed-by: Vivian Wang +Link: https://patch.msgid.link/20260220070239.1693303-3-nilay@linux.ibm.com +(cherry picked from commit 147dae12985947cdb9e1918142f06482c5077a81) +Signed-off-by: Han Gao +--- + arch/sparc/kernel/pci.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c +index b290107170e9..a4815d544781 100644 +--- a/arch/sparc/kernel/pci.c ++++ b/arch/sparc/kernel/pci.c +@@ -355,6 +355,13 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, + dev->error_state = pci_channel_io_normal; + dev->dma_mask = 0xffffffff; + ++ /* ++ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit ++ * if MSI (rather than MSI-X) capability does not have ++ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. ++ */ ++ dev->msi_addr_mask = DMA_BIT_MASK(64); ++ + if (of_node_name_eq(node, "pci")) { + /* a PCI-PCI bridge */ + dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0160-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch b/SPECS/linux-lts/0160-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch deleted file mode 100644 index cb7b7536b5..0000000000 --- a/SPECS/linux-lts/0160-UPSTREAM-net-stmmac-imx-use-set_phy_intf_sel.patch +++ /dev/null @@ -1,80 +0,0 @@ -From dd51d5c75d4f912be30523c694e72ffe87fa3d99 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 3 Nov 2025 11:50:46 +0000 -Subject: [PATCH 160/467] UPSTREAM: net: stmmac: imx: use ->set_phy_intf_sel() - -Rather than placing the phy_intf_sel() setup in the ->init() method, -move it to the new ->set_phy_intf_sel() method. - -Signed-off-by: Russell King (Oracle) -Link: https://patch.msgid.link/E1vFt5C-0000000ChpR-2kAB@rmk-PC.armlinux.org.uk -Signed-off-by: Jakub Kicinski -(cherry picked from commit eaca1a4dc51e5e4979e45a4ad72a1c2a88a80a72) -Signed-off-by: Han Gao ---- - .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 38 +++++-------------- - 1 file changed, 10 insertions(+), 28 deletions(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -index ae1b73e1bcb2..db288fbd5a4d 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -134,36 +134,19 @@ static int imx_dwmac_clks_config(void *priv, bool enabled) - return ret; - } - --static int imx_dwmac_init(struct platform_device *pdev, void *priv) -+static int imx_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) - { -- struct imx_priv_data *dwmac = priv; -- phy_interface_t interface; -- int phy_intf_sel, ret; -- -- if (dwmac->ops->set_intf_mode) { -- interface = dwmac->plat_dat->phy_interface; -- -- phy_intf_sel = stmmac_get_phy_intf_sel(interface); -- if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && -- phy_intf_sel != PHY_INTF_SEL_RGMII && -- phy_intf_sel != PHY_INTF_SEL_RMII) { -- dev_dbg(dwmac->dev, -- "imx dwmac doesn't support %s interface\n", -- phy_modes(interface)); -- return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL; -- } -+ struct imx_priv_data *dwmac = bsp_priv; - -- ret = dwmac->ops->set_intf_mode(dwmac, phy_intf_sel); -- if (ret) -- return ret; -- } -+ if (!dwmac->ops->set_intf_mode) -+ return 0; - -- return 0; --} -+ if (phy_intf_sel != PHY_INTF_SEL_GMII_MII && -+ phy_intf_sel != PHY_INTF_SEL_RGMII && -+ phy_intf_sel != PHY_INTF_SEL_RMII) -+ return -EINVAL; - --static void imx_dwmac_exit(struct platform_device *pdev, void *priv) --{ -- /* nothing to do now */ -+ return dwmac->ops->set_intf_mode(dwmac, phy_intf_sel); - } - - static int imx_dwmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i, -@@ -342,8 +325,7 @@ static int imx_dwmac_probe(struct platform_device *pdev) - plat_dat->tx_queues_cfg[i].tbs_en = 1; - - plat_dat->host_dma_width = dwmac->ops->addr_width; -- plat_dat->init = imx_dwmac_init; -- plat_dat->exit = imx_dwmac_exit; -+ plat_dat->set_phy_intf_sel = imx_set_phy_intf_sel; - plat_dat->clks_config = imx_dwmac_clks_config; - plat_dat->bsp_priv = dwmac; - dwmac->plat_dat = plat_dat; --- -2.53.0 - diff --git a/SPECS/linux-lts/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch b/SPECS/linux-lts/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch new file mode 100644 index 0000000000..9f8cb3b4b0 --- /dev/null +++ b/SPECS/linux-lts/0160-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch @@ -0,0 +1,4919 @@ +From 94993ae18a9db8b1a6f5939a8bfc465712f0e760 Mon Sep 17 00:00:00 2001 +From: Thierry Reding +Date: Wed, 29 Oct 2025 17:33:30 +0100 +Subject: [RUYI PATCH] UPSTREAM: syscore: Pass context data to callbacks + +Several drivers can benefit from registering per-instance data along +with the syscore operations. To achieve this, move the modifiable fields +out of the syscore_ops structure and into a separate struct syscore that +can be registered with the framework. Add a void * driver data field for +drivers to store contextual data that will be passed to the syscore ops. + +Acked-by: Rafael J. Wysocki (Intel) +Signed-off-by: Thierry Reding +(cherry picked from commit a97fbc3ee3e2a536fafaff04f21f45472db71769) +Signed-off-by: Han Gao +--- + arch/arm/mach-exynos/mcpm-exynos.c | 12 ++-- + arch/arm/mach-exynos/suspend.c | 48 +++++++------ + arch/arm/mach-pxa/generic.h | 6 +- + arch/arm/mach-pxa/irq.c | 10 ++- + arch/arm/mach-pxa/mfp-pxa2xx.c | 10 ++- + arch/arm/mach-pxa/mfp-pxa3xx.c | 10 ++- + arch/arm/mach-pxa/pxa25x.c | 4 +- + arch/arm/mach-pxa/pxa27x.c | 4 +- + arch/arm/mach-pxa/pxa3xx.c | 4 +- + arch/arm/mach-pxa/smemc.c | 12 ++-- + arch/arm/mach-s3c/irq-pm-s3c64xx.c | 12 ++-- + arch/arm/mach-s5pv210/pm.c | 10 ++- + arch/arm/mach-versatile/integrator_ap.c | 12 ++-- + arch/arm/mm/cache-b15-rac.c | 12 ++-- + arch/loongarch/kernel/smp.c | 12 ++-- + arch/mips/alchemy/common/dbdma.c | 12 ++-- + arch/mips/alchemy/common/irq.c | 24 ++++--- + arch/mips/alchemy/common/usb.c | 12 ++-- + arch/mips/pci/pci-alchemy.c | 16 +++-- + arch/powerpc/platforms/cell/spu_base.c | 10 ++- + arch/powerpc/platforms/powermac/pic.c | 12 ++-- + arch/powerpc/sysdev/fsl_lbc.c | 12 ++-- + arch/powerpc/sysdev/fsl_pci.c | 12 ++-- + arch/powerpc/sysdev/ipic.c | 12 ++-- + arch/powerpc/sysdev/mpic.c | 14 ++-- + arch/powerpc/sysdev/mpic_timer.c | 10 ++- + arch/sh/mm/pmb.c | 10 ++- + arch/x86/events/amd/ibs.c | 12 ++-- + arch/x86/hyperv/hv_init.c | 12 ++-- + arch/x86/kernel/amd_gart_64.c | 10 ++- + arch/x86/kernel/apic/apic.c | 12 ++-- + arch/x86/kernel/apic/io_apic.c | 17 +++-- + arch/x86/kernel/cpu/aperfmperf.c | 20 +++--- + arch/x86/kernel/cpu/intel_epb.c | 16 +++-- + arch/x86/kernel/cpu/mce/core.c | 14 ++-- + arch/x86/kernel/cpu/microcode/core.c | 15 ++++- + arch/x86/kernel/cpu/mtrr/legacy.c | 12 ++-- + arch/x86/kernel/cpu/umwait.c | 10 ++- + arch/x86/kernel/i8237.c | 10 ++- + arch/x86/kernel/i8259.c | 14 ++-- + arch/x86/kernel/kvm.c | 12 ++-- + drivers/acpi/pci_link.c | 10 ++- + drivers/acpi/sleep.c | 12 ++-- + drivers/base/firmware_loader/main.c | 12 ++-- + drivers/base/syscore.c | 82 ++++++++++++----------- + drivers/bus/mvebu-mbus.c | 16 +++-- + drivers/clk/at91/pmc.c | 12 ++-- + drivers/clk/imx/clk-vf610.c | 12 ++-- + drivers/clk/ingenic/jz4725b-cgu.c | 2 +- + drivers/clk/ingenic/jz4740-cgu.c | 2 +- + drivers/clk/ingenic/jz4755-cgu.c | 2 +- + drivers/clk/ingenic/jz4760-cgu.c | 2 +- + drivers/clk/ingenic/jz4770-cgu.c | 2 +- + drivers/clk/ingenic/jz4780-cgu.c | 2 +- + drivers/clk/ingenic/pm.c | 14 ++-- + drivers/clk/ingenic/pm.h | 2 +- + drivers/clk/ingenic/tcu.c | 12 ++-- + drivers/clk/ingenic/x1000-cgu.c | 2 +- + drivers/clk/ingenic/x1830-cgu.c | 2 +- + drivers/clk/mvebu/common.c | 12 ++-- + drivers/clk/rockchip/clk-rk3288.c | 12 ++-- + drivers/clk/samsung/clk-s5pv210-audss.c | 12 ++-- + drivers/clk/samsung/clk.c | 12 ++-- + drivers/clk/tegra/clk-tegra210.c | 12 ++-- + drivers/clocksource/timer-armada-370-xp.c | 12 ++-- + drivers/cpuidle/cpuidle-psci.c | 12 ++-- + drivers/gpio/gpio-mxc.c | 12 ++-- + drivers/gpio/gpio-pxa.c | 12 ++-- + drivers/gpio/gpio-sa1100.c | 12 ++-- + drivers/hv/vmbus_drv.c | 14 ++-- + drivers/iommu/amd/init.c | 16 +++-- + drivers/iommu/intel/iommu.c | 12 ++-- + drivers/irqchip/exynos-combiner.c | 14 ++-- + drivers/irqchip/irq-armada-370-xp.c | 12 ++-- + drivers/irqchip/irq-bcm7038-l1.c | 12 ++-- + drivers/irqchip/irq-gic-v3-its.c | 12 ++-- + drivers/irqchip/irq-i8259.c | 12 ++-- + drivers/irqchip/irq-imx-gpcv2.c | 16 +++-- + drivers/irqchip/irq-loongson-eiointc.c | 12 ++-- + drivers/irqchip/irq-loongson-htpic.c | 10 ++- + drivers/irqchip/irq-loongson-htvec.c | 12 ++-- + drivers/irqchip/irq-loongson-pch-lpc.c | 12 ++-- + drivers/irqchip/irq-loongson-pch-pic.c | 12 ++-- + drivers/irqchip/irq-mchp-eic.c | 12 ++-- + drivers/irqchip/irq-mst-intc.c | 12 ++-- + drivers/irqchip/irq-mtk-cirq.c | 12 ++-- + drivers/irqchip/irq-renesas-rzg2l.c | 12 ++-- + drivers/irqchip/irq-sa11x0.c | 12 ++-- + drivers/irqchip/irq-sifive-plic.c | 12 ++-- + drivers/irqchip/irq-sun6i-r.c | 18 +++-- + drivers/irqchip/irq-tegra.c | 12 ++-- + drivers/irqchip/irq-vic.c | 12 ++-- + drivers/leds/trigger/ledtrig-cpu.c | 14 ++-- + drivers/macintosh/via-pmu.c | 12 ++-- + drivers/power/reset/sc27xx-poweroff.c | 10 ++- + drivers/sh/clk/core.c | 10 ++- + drivers/sh/intc/core.c | 12 ++-- + drivers/soc/bcm/brcmstb/biuctrl.c | 12 ++-- + drivers/soc/tegra/pmc.c | 17 +++-- + drivers/thermal/intel/intel_hfi.c | 12 ++-- + drivers/xen/xen-acpi-processor.c | 12 ++-- + include/linux/syscore_ops.h | 15 +++-- + kernel/cpu_pm.c | 12 ++-- + kernel/irq/generic-chip.c | 14 ++-- + kernel/irq/pm.c | 11 ++- + kernel/printk/printk.c | 11 ++- + kernel/time/sched_clock.c | 22 ++++-- + kernel/time/timekeeping.c | 22 ++++-- + virt/kvm/kvm_main.c | 18 +++-- + 109 files changed, 898 insertions(+), 470 deletions(-) + +diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c +index fd0dbeb93357..cb7d8a7b14e0 100644 +--- a/arch/arm/mach-exynos/mcpm-exynos.c ++++ b/arch/arm/mach-exynos/mcpm-exynos.c +@@ -215,7 +215,7 @@ static const struct of_device_id exynos_dt_mcpm_match[] = { + {}, + }; + +-static void exynos_mcpm_setup_entry_point(void) ++static void exynos_mcpm_setup_entry_point(void *data) + { + /* + * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr +@@ -228,10 +228,14 @@ static void exynos_mcpm_setup_entry_point(void) + __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8); + } + +-static struct syscore_ops exynos_mcpm_syscore_ops = { ++static const struct syscore_ops exynos_mcpm_syscore_ops = { + .resume = exynos_mcpm_setup_entry_point, + }; + ++static struct syscore exynos_mcpm_syscore = { ++ .ops = &exynos_mcpm_syscore_ops, ++}; ++ + static int __init exynos_mcpm_init(void) + { + struct device_node *node; +@@ -300,9 +304,9 @@ static int __init exynos_mcpm_init(void) + pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i)); + } + +- exynos_mcpm_setup_entry_point(); ++ exynos_mcpm_setup_entry_point(NULL); + +- register_syscore_ops(&exynos_mcpm_syscore_ops); ++ register_syscore(&exynos_mcpm_syscore); + + return ret; + } +diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c +index 150a1e56dcae..22d723553f62 100644 +--- a/arch/arm/mach-exynos/suspend.c ++++ b/arch/arm/mach-exynos/suspend.c +@@ -53,9 +53,9 @@ struct exynos_pm_data { + + void (*pm_prepare)(void); + void (*pm_resume_prepare)(void); +- void (*pm_resume)(void); +- int (*pm_suspend)(void); + int (*cpu_suspend)(unsigned long); ++ ++ const struct syscore_ops *syscore_ops; + }; + + /* Used only on Exynos542x/5800 */ +@@ -376,7 +376,7 @@ static void exynos5420_pm_prepare(void) + } + + +-static int exynos_pm_suspend(void) ++static int exynos_pm_suspend(void *data) + { + exynos_pm_central_suspend(); + +@@ -390,7 +390,7 @@ static int exynos_pm_suspend(void) + return 0; + } + +-static int exynos5420_pm_suspend(void) ++static int exynos5420_pm_suspend(void *data) + { + u32 this_cluster; + +@@ -408,7 +408,7 @@ static int exynos5420_pm_suspend(void) + return 0; + } + +-static void exynos_pm_resume(void) ++static void exynos_pm_resume(void *data) + { + u32 cpuid = read_cpuid_part(); + +@@ -429,7 +429,7 @@ static void exynos_pm_resume(void) + exynos_set_delayed_reset_assertion(true); + } + +-static void exynos3250_pm_resume(void) ++static void exynos3250_pm_resume(void *data) + { + u32 cpuid = read_cpuid_part(); + +@@ -473,7 +473,7 @@ static void exynos5420_prepare_pm_resume(void) + } + } + +-static void exynos5420_pm_resume(void) ++static void exynos5420_pm_resume(void *data) + { + unsigned long tmp; + +@@ -596,41 +596,52 @@ static const struct platform_suspend_ops exynos_suspend_ops = { + .valid = suspend_valid_only_mem, + }; + ++static const struct syscore_ops exynos3250_syscore_ops = { ++ .suspend = exynos_pm_suspend, ++ .resume = exynos3250_pm_resume, ++}; ++ + static const struct exynos_pm_data exynos3250_pm_data = { + .wkup_irq = exynos3250_wkup_irq, + .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), +- .pm_suspend = exynos_pm_suspend, +- .pm_resume = exynos3250_pm_resume, + .pm_prepare = exynos3250_pm_prepare, + .cpu_suspend = exynos3250_cpu_suspend, ++ .syscore_ops = &exynos3250_syscore_ops, ++}; ++ ++static const struct syscore_ops exynos_syscore_ops = { ++ .suspend = exynos_pm_suspend, ++ .resume = exynos_pm_resume, + }; + + static const struct exynos_pm_data exynos4_pm_data = { + .wkup_irq = exynos4_wkup_irq, + .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), +- .pm_suspend = exynos_pm_suspend, +- .pm_resume = exynos_pm_resume, + .pm_prepare = exynos_pm_prepare, + .cpu_suspend = exynos_cpu_suspend, ++ .syscore_ops = &exynos_syscore_ops, + }; + + static const struct exynos_pm_data exynos5250_pm_data = { + .wkup_irq = exynos5250_wkup_irq, + .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), +- .pm_suspend = exynos_pm_suspend, +- .pm_resume = exynos_pm_resume, + .pm_prepare = exynos_pm_prepare, + .cpu_suspend = exynos_cpu_suspend, ++ .syscore_ops = &exynos_syscore_ops, ++}; ++ ++static const struct syscore_ops exynos5420_syscore_ops = { ++ .resume = exynos5420_pm_resume, ++ .suspend = exynos5420_pm_suspend, + }; + + static const struct exynos_pm_data exynos5420_pm_data = { + .wkup_irq = exynos5250_wkup_irq, + .wake_disable_mask = (0x7F << 7) | (0x1F << 1), + .pm_resume_prepare = exynos5420_prepare_pm_resume, +- .pm_resume = exynos5420_pm_resume, +- .pm_suspend = exynos5420_pm_suspend, + .pm_prepare = exynos5420_pm_prepare, + .cpu_suspend = exynos5420_cpu_suspend, ++ .syscore_ops = &exynos5420_syscore_ops, + }; + + static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { +@@ -656,7 +667,7 @@ static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { + { /*sentinel*/ }, + }; + +-static struct syscore_ops exynos_pm_syscore_ops; ++static struct syscore exynos_pm_syscore; + + void __init exynos_pm_init(void) + { +@@ -684,10 +695,9 @@ void __init exynos_pm_init(void) + tmp |= pm_data->wake_disable_mask; + pmu_raw_writel(tmp, S5P_WAKEUP_MASK); + +- exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; +- exynos_pm_syscore_ops.resume = pm_data->pm_resume; ++ exynos_pm_syscore.ops = pm_data->syscore_ops; + +- register_syscore_ops(&exynos_pm_syscore_ops); ++ register_syscore(&exynos_pm_syscore); + suspend_set_ops(&exynos_suspend_ops); + + /* +diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h +index c9c2c46ecead..caad4fca8de3 100644 +--- a/arch/arm/mach-pxa/generic.h ++++ b/arch/arm/mach-pxa/generic.h +@@ -34,9 +34,9 @@ extern void __init pxa27x_map_io(void); + extern void __init pxa3xx_init_irq(void); + extern void __init pxa3xx_map_io(void); + +-extern struct syscore_ops pxa_irq_syscore_ops; +-extern struct syscore_ops pxa2xx_mfp_syscore_ops; +-extern struct syscore_ops pxa3xx_mfp_syscore_ops; ++extern struct syscore pxa_irq_syscore; ++extern struct syscore pxa2xx_mfp_syscore; ++extern struct syscore pxa3xx_mfp_syscore; + + void __init pxa_set_ffuart_info(void *info); + void __init pxa_set_btuart_info(void *info); +diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c +index 5bfce8aa4102..99acebbbf065 100644 +--- a/arch/arm/mach-pxa/irq.c ++++ b/arch/arm/mach-pxa/irq.c +@@ -178,7 +178,7 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) + static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; + static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; + +-static int pxa_irq_suspend(void) ++static int pxa_irq_suspend(void *data) + { + int i; + +@@ -197,7 +197,7 @@ static int pxa_irq_suspend(void) + return 0; + } + +-static void pxa_irq_resume(void) ++static void pxa_irq_resume(void *data) + { + int i; + +@@ -219,11 +219,15 @@ static void pxa_irq_resume(void) + #define pxa_irq_resume NULL + #endif + +-struct syscore_ops pxa_irq_syscore_ops = { ++static const struct syscore_ops pxa_irq_syscore_ops = { + .suspend = pxa_irq_suspend, + .resume = pxa_irq_resume, + }; + ++struct syscore pxa_irq_syscore = { ++ .ops = &pxa_irq_syscore_ops, ++}; ++ + #ifdef CONFIG_OF + static const struct of_device_id intc_ids[] __initconst = { + { .compatible = "marvell,pxa-intc", }, +diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c +index f5a3d890f682..d1347055fbe4 100644 +--- a/arch/arm/mach-pxa/mfp-pxa2xx.c ++++ b/arch/arm/mach-pxa/mfp-pxa2xx.c +@@ -346,7 +346,7 @@ static unsigned long saved_gpdr[4]; + static unsigned long saved_gplr[4]; + static unsigned long saved_pgsr[4]; + +-static int pxa2xx_mfp_suspend(void) ++static int pxa2xx_mfp_suspend(void *data) + { + int i; + +@@ -385,7 +385,7 @@ static int pxa2xx_mfp_suspend(void) + return 0; + } + +-static void pxa2xx_mfp_resume(void) ++static void pxa2xx_mfp_resume(void *data) + { + int i; + +@@ -404,11 +404,15 @@ static void pxa2xx_mfp_resume(void) + #define pxa2xx_mfp_resume NULL + #endif + +-struct syscore_ops pxa2xx_mfp_syscore_ops = { ++static const struct syscore_ops pxa2xx_mfp_syscore_ops = { + .suspend = pxa2xx_mfp_suspend, + .resume = pxa2xx_mfp_resume, + }; + ++struct syscore pxa2xx_mfp_syscore = { ++ .ops = &pxa2xx_mfp_syscore_ops, ++}; ++ + static int __init pxa2xx_mfp_init(void) + { + int i; +diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c +index d16ab7451efe..fe7498fbb62b 100644 +--- a/arch/arm/mach-pxa/mfp-pxa3xx.c ++++ b/arch/arm/mach-pxa/mfp-pxa3xx.c +@@ -27,13 +27,13 @@ + * a pull-down mode if they're an active low chip select, and we're + * just entering standby. + */ +-static int pxa3xx_mfp_suspend(void) ++static int pxa3xx_mfp_suspend(void *data) + { + mfp_config_lpm(); + return 0; + } + +-static void pxa3xx_mfp_resume(void) ++static void pxa3xx_mfp_resume(void *data) + { + mfp_config_run(); + +@@ -49,7 +49,11 @@ static void pxa3xx_mfp_resume(void) + #define pxa3xx_mfp_resume NULL + #endif + +-struct syscore_ops pxa3xx_mfp_syscore_ops = { ++static const struct syscore_ops pxa3xx_mfp_syscore_ops = { + .suspend = pxa3xx_mfp_suspend, + .resume = pxa3xx_mfp_resume, + }; ++ ++struct syscore pxa3xx_mfp_syscore = { ++ .ops = &pxa3xx_mfp_syscore_ops, ++}; +diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c +index 03e34841fc00..70509a599814 100644 +--- a/arch/arm/mach-pxa/pxa25x.c ++++ b/arch/arm/mach-pxa/pxa25x.c +@@ -235,8 +235,8 @@ static int __init pxa25x_init(void) + + pxa25x_init_pm(); + +- register_syscore_ops(&pxa_irq_syscore_ops); +- register_syscore_ops(&pxa2xx_mfp_syscore_ops); ++ register_syscore(&pxa_irq_syscore); ++ register_syscore(&pxa2xx_mfp_syscore); + + if (!of_have_populated_dt()) { + software_node_register(&pxa2xx_gpiochip_node); +diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c +index f8382477d629..ff6361979038 100644 +--- a/arch/arm/mach-pxa/pxa27x.c ++++ b/arch/arm/mach-pxa/pxa27x.c +@@ -337,8 +337,8 @@ static int __init pxa27x_init(void) + + pxa27x_init_pm(); + +- register_syscore_ops(&pxa_irq_syscore_ops); +- register_syscore_ops(&pxa2xx_mfp_syscore_ops); ++ register_syscore(&pxa_irq_syscore); ++ register_syscore(&pxa2xx_mfp_syscore); + + if (!of_have_populated_dt()) { + software_node_register(&pxa2xx_gpiochip_node); +diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c +index 1d1e5713464d..06c578ea658e 100644 +--- a/arch/arm/mach-pxa/pxa3xx.c ++++ b/arch/arm/mach-pxa/pxa3xx.c +@@ -424,8 +424,8 @@ static int __init pxa3xx_init(void) + if (cpu_is_pxa320()) + enable_irq_wake(IRQ_WAKEUP1); + +- register_syscore_ops(&pxa_irq_syscore_ops); +- register_syscore_ops(&pxa3xx_mfp_syscore_ops); ++ register_syscore(&pxa_irq_syscore); ++ register_syscore(&pxa3xx_mfp_syscore); + } + + return ret; +diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c +index 2d2a321d82f8..fb93a8f28356 100644 +--- a/arch/arm/mach-pxa/smemc.c ++++ b/arch/arm/mach-pxa/smemc.c +@@ -18,7 +18,7 @@ static unsigned long msc[2]; + static unsigned long sxcnfg, memclkcfg; + static unsigned long csadrcfg[4]; + +-static int pxa3xx_smemc_suspend(void) ++static int pxa3xx_smemc_suspend(void *data) + { + msc[0] = __raw_readl(MSC0); + msc[1] = __raw_readl(MSC1); +@@ -32,7 +32,7 @@ static int pxa3xx_smemc_suspend(void) + return 0; + } + +-static void pxa3xx_smemc_resume(void) ++static void pxa3xx_smemc_resume(void *data) + { + __raw_writel(msc[0], MSC0); + __raw_writel(msc[1], MSC1); +@@ -46,11 +46,15 @@ static void pxa3xx_smemc_resume(void) + __raw_writel(0x2, CSMSADRCFG); + } + +-static struct syscore_ops smemc_syscore_ops = { ++static const struct syscore_ops smemc_syscore_ops = { + .suspend = pxa3xx_smemc_suspend, + .resume = pxa3xx_smemc_resume, + }; + ++static struct syscore smemc_syscore = { ++ .ops = &smemc_syscore_ops, ++}; ++ + static int __init smemc_init(void) + { + if (cpu_is_pxa3xx()) { +@@ -64,7 +68,7 @@ static int __init smemc_init(void) + */ + __raw_writel(0x2, CSMSADRCFG); + +- register_syscore_ops(&smemc_syscore_ops); ++ register_syscore(&smemc_syscore); + } + + return 0; +diff --git a/arch/arm/mach-s3c/irq-pm-s3c64xx.c b/arch/arm/mach-s3c/irq-pm-s3c64xx.c +index 4a1e935bada1..ab726c595001 100644 +--- a/arch/arm/mach-s3c/irq-pm-s3c64xx.c ++++ b/arch/arm/mach-s3c/irq-pm-s3c64xx.c +@@ -58,7 +58,7 @@ static struct irq_grp_save { + + static u32 irq_uart_mask[SERIAL_SAMSUNG_UARTS]; + +-static int s3c64xx_irq_pm_suspend(void) ++static int s3c64xx_irq_pm_suspend(void *data) + { + struct irq_grp_save *grp = eint_grp_save; + int i; +@@ -79,7 +79,7 @@ static int s3c64xx_irq_pm_suspend(void) + return 0; + } + +-static void s3c64xx_irq_pm_resume(void) ++static void s3c64xx_irq_pm_resume(void *data) + { + struct irq_grp_save *grp = eint_grp_save; + int i; +@@ -100,18 +100,22 @@ static void s3c64xx_irq_pm_resume(void) + S3C_PMDBG("%s: IRQ configuration restored\n", __func__); + } + +-static struct syscore_ops s3c64xx_irq_syscore_ops = { ++static const struct syscore_ops s3c64xx_irq_syscore_ops = { + .suspend = s3c64xx_irq_pm_suspend, + .resume = s3c64xx_irq_pm_resume, + }; + ++static struct syscore s3c64xx_irq_syscore = { ++ .ops = &s3c64xx_irq_syscore_ops, ++}; ++ + static __init int s3c64xx_syscore_init(void) + { + /* Appropriate drivers (pinctrl, uart) handle this when using DT. */ + if (of_have_populated_dt() || !soc_is_s3c64xx()) + return 0; + +- register_syscore_ops(&s3c64xx_irq_syscore_ops); ++ register_syscore(&s3c64xx_irq_syscore); + + return 0; + } +diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c +index 6fa70f787df4..fa270750364c 100644 +--- a/arch/arm/mach-s5pv210/pm.c ++++ b/arch/arm/mach-s5pv210/pm.c +@@ -195,20 +195,24 @@ static const struct platform_suspend_ops s5pv210_suspend_ops = { + /* + * Syscore operations used to delay restore of certain registers. + */ +-static void s5pv210_pm_resume(void) ++static void s5pv210_pm_resume(void *data) + { + s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); + } + +-static struct syscore_ops s5pv210_pm_syscore_ops = { ++static const struct syscore_ops s5pv210_pm_syscore_ops = { + .resume = s5pv210_pm_resume, + }; + ++static struct syscore s5pv210_pm_syscore = { ++ .ops = &s5pv210_pm_syscore_ops, ++}; ++ + /* + * Initialization entry point. + */ + void __init s5pv210_pm_init(void) + { +- register_syscore_ops(&s5pv210_pm_syscore_ops); ++ register_syscore(&s5pv210_pm_syscore); + suspend_set_ops(&s5pv210_suspend_ops); + } +diff --git a/arch/arm/mach-versatile/integrator_ap.c b/arch/arm/mach-versatile/integrator_ap.c +index 4bd6712e9f52..ee90d6619d0d 100644 +--- a/arch/arm/mach-versatile/integrator_ap.c ++++ b/arch/arm/mach-versatile/integrator_ap.c +@@ -63,13 +63,13 @@ static void __init ap_map_io(void) + #ifdef CONFIG_PM + static unsigned long ic_irq_enable; + +-static int irq_suspend(void) ++static int irq_suspend(void *data) + { + ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); + return 0; + } + +-static void irq_resume(void) ++static void irq_resume(void *data) + { + /* disable all irq sources */ + cm_clear_irqs(); +@@ -83,14 +83,18 @@ static void irq_resume(void) + #define irq_resume NULL + #endif + +-static struct syscore_ops irq_syscore_ops = { ++static const struct syscore_ops irq_syscore_ops = { + .suspend = irq_suspend, + .resume = irq_resume, + }; + ++static struct syscore irq_syscore = { ++ .ops = &irq_syscore_ops, ++}; ++ + static int __init irq_syscore_init(void) + { +- register_syscore_ops(&irq_syscore_ops); ++ register_syscore(&irq_syscore); + + return 0; + } +diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c +index 6f63b90f9e1a..e7807356dfab 100644 +--- a/arch/arm/mm/cache-b15-rac.c ++++ b/arch/arm/mm/cache-b15-rac.c +@@ -256,7 +256,7 @@ static int b15_rac_dead_cpu(unsigned int cpu) + return 0; + } + +-static int b15_rac_suspend(void) ++static int b15_rac_suspend(void *data) + { + /* Suspend the read-ahead cache oeprations, forcing our cache + * implementation to fallback to the regular ARMv7 calls. +@@ -271,7 +271,7 @@ static int b15_rac_suspend(void) + return 0; + } + +-static void b15_rac_resume(void) ++static void b15_rac_resume(void *data) + { + /* Coming out of a S3 suspend/resume cycle, the read-ahead cache + * register RAC_CONFIG0_REG will be restored to its default value, make +@@ -282,11 +282,15 @@ static void b15_rac_resume(void) + clear_bit(RAC_SUSPENDED, &b15_rac_flags); + } + +-static struct syscore_ops b15_rac_syscore_ops = { ++static const struct syscore_ops b15_rac_syscore_ops = { + .suspend = b15_rac_suspend, + .resume = b15_rac_resume, + }; + ++static struct syscore b15_rac_syscore = { ++ .ops = &b15_rac_syscore_ops, ++}; ++ + static int __init b15_rac_init(void) + { + struct device_node *dn, *cpu_dn; +@@ -347,7 +351,7 @@ static int __init b15_rac_init(void) + } + + if (IS_ENABLED(CONFIG_PM_SLEEP)) +- register_syscore_ops(&b15_rac_syscore_ops); ++ register_syscore(&b15_rac_syscore); + + spin_lock(&rac_lock); + reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); +diff --git a/arch/loongarch/kernel/smp.c b/arch/loongarch/kernel/smp.c +index 46036d98da75..8b2fcb3fb874 100644 +--- a/arch/loongarch/kernel/smp.c ++++ b/arch/loongarch/kernel/smp.c +@@ -535,28 +535,32 @@ int hibernate_resume_nonboot_cpu_disable(void) + */ + #ifdef CONFIG_PM + +-static int loongson_ipi_suspend(void) ++static int loongson_ipi_suspend(void *data) + { + return 0; + } + +-static void loongson_ipi_resume(void) ++static void loongson_ipi_resume(void *data) + { + iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN); + } + +-static struct syscore_ops loongson_ipi_syscore_ops = { ++static const struct syscore_ops loongson_ipi_syscore_ops = { + .resume = loongson_ipi_resume, + .suspend = loongson_ipi_suspend, + }; + ++static struct syscore loongson_ipi_syscore = { ++ .ops = &loongson_ipi_syscore_ops, ++}; ++ + /* + * Enable boot cpu ipi before enabling nonboot cpus + * during syscore_resume. + */ + static int __init ipi_pm_init(void) + { +- register_syscore_ops(&loongson_ipi_syscore_ops); ++ register_syscore(&loongson_ipi_syscore); + return 0; + } + +diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c +index 6a3c890f7bbf..6c2c2010bbae 100644 +--- a/arch/mips/alchemy/common/dbdma.c ++++ b/arch/mips/alchemy/common/dbdma.c +@@ -982,7 +982,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) + + static unsigned long alchemy_dbdma_pm_data[NUM_DBDMA_CHANS + 1][6]; + +-static int alchemy_dbdma_suspend(void) ++static int alchemy_dbdma_suspend(void *data) + { + int i; + void __iomem *addr; +@@ -1019,7 +1019,7 @@ static int alchemy_dbdma_suspend(void) + return 0; + } + +-static void alchemy_dbdma_resume(void) ++static void alchemy_dbdma_resume(void *data) + { + int i; + void __iomem *addr; +@@ -1044,11 +1044,15 @@ static void alchemy_dbdma_resume(void) + } + } + +-static struct syscore_ops alchemy_dbdma_syscore_ops = { ++static const struct syscore_ops alchemy_dbdma_syscore_ops = { + .suspend = alchemy_dbdma_suspend, + .resume = alchemy_dbdma_resume, + }; + ++static struct syscore alchemy_dbdma_syscore = { ++ .ops = &alchemy_dbdma_syscore_ops, ++}; ++ + static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable) + { + int ret; +@@ -1071,7 +1075,7 @@ static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable) + printk(KERN_ERR "Cannot grab DBDMA interrupt!\n"); + else { + dbdma_initialized = 1; +- register_syscore_ops(&alchemy_dbdma_syscore_ops); ++ register_syscore(&alchemy_dbdma_syscore); + } + + return ret; +diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c +index da9f9220048f..2403afcd2fb9 100644 +--- a/arch/mips/alchemy/common/irq.c ++++ b/arch/mips/alchemy/common/irq.c +@@ -758,7 +758,7 @@ static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d) + wmb(); + } + +-static int alchemy_ic_suspend(void) ++static int alchemy_ic_suspend(void *data) + { + alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), + alchemy_gpic_pmdata); +@@ -767,7 +767,7 @@ static int alchemy_ic_suspend(void) + return 0; + } + +-static void alchemy_ic_resume(void) ++static void alchemy_ic_resume(void *data) + { + alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), + &alchemy_gpic_pmdata[7]); +@@ -775,7 +775,7 @@ static void alchemy_ic_resume(void) + alchemy_gpic_pmdata); + } + +-static int alchemy_gpic_suspend(void) ++static int alchemy_gpic_suspend(void *data) + { + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + int i; +@@ -806,7 +806,7 @@ static int alchemy_gpic_suspend(void) + return 0; + } + +-static void alchemy_gpic_resume(void) ++static void alchemy_gpic_resume(void *data) + { + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + int i; +@@ -837,16 +837,24 @@ static void alchemy_gpic_resume(void) + wmb(); + } + +-static struct syscore_ops alchemy_ic_pmops = { ++static const struct syscore_ops alchemy_ic_pmops = { + .suspend = alchemy_ic_suspend, + .resume = alchemy_ic_resume, + }; + +-static struct syscore_ops alchemy_gpic_pmops = { ++static struct syscore alchemy_ic_pm = { ++ .ops = &alchemy_ic_pmops, ++}; ++ ++static const struct syscore_ops alchemy_gpic_pmops = { + .suspend = alchemy_gpic_suspend, + .resume = alchemy_gpic_resume, + }; + ++static struct syscore alchemy_gpic_pm = { ++ .ops = &alchemy_gpic_pmops, ++}; ++ + /******************************************************************************/ + + /* create chained handlers for the 4 IC requests to the MIPS IRQ ctrl */ +@@ -880,7 +888,7 @@ static void __init au1000_init_irq(struct alchemy_irqmap *map) + + ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR)); + ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR)); +- register_syscore_ops(&alchemy_ic_pmops); ++ register_syscore(&alchemy_ic_pm); + mips_cpu_irq_init(); + + /* register all 64 possible IC0+IC1 irq sources as type "none". +@@ -925,7 +933,7 @@ static void __init alchemy_gpic_init_irq(const struct alchemy_irqmap *dints) + int i; + void __iomem *bank_base; + +- register_syscore_ops(&alchemy_gpic_pmops); ++ register_syscore(&alchemy_gpic_pm); + mips_cpu_irq_init(); + + /* disable & ack all possible interrupt sources */ +diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c +index 5d618547ebf0..a55f32bf517c 100644 +--- a/arch/mips/alchemy/common/usb.c ++++ b/arch/mips/alchemy/common/usb.c +@@ -580,22 +580,26 @@ static void alchemy_usb_pm(int susp) + } + } + +-static int alchemy_usb_suspend(void) ++static int alchemy_usb_suspend(void *data) + { + alchemy_usb_pm(1); + return 0; + } + +-static void alchemy_usb_resume(void) ++static void alchemy_usb_resume(void *data) + { + alchemy_usb_pm(0); + } + +-static struct syscore_ops alchemy_usb_pm_ops = { ++static const struct syscore_ops alchemy_usb_pm_syscore_ops = { + .suspend = alchemy_usb_suspend, + .resume = alchemy_usb_resume, + }; + ++static struct syscore alchemy_usb_pm_syscore = { ++ .ops = &alchemy_usb_pm_syscore_ops, ++}; ++ + static int __init alchemy_usb_init(void) + { + int ret = 0; +@@ -620,7 +624,7 @@ static int __init alchemy_usb_init(void) + } + + if (!ret) +- register_syscore_ops(&alchemy_usb_pm_ops); ++ register_syscore(&alchemy_usb_pm_syscore); + + return ret; + } +diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c +index 58625d1b6465..6bfee0f71803 100644 +--- a/arch/mips/pci/pci-alchemy.c ++++ b/arch/mips/pci/pci-alchemy.c +@@ -304,7 +304,7 @@ static int alchemy_pci_def_idsel(unsigned int devsel, int assert) + } + + /* save PCI controller register contents. */ +-static int alchemy_pci_suspend(void) ++static int alchemy_pci_suspend(void *data) + { + struct alchemy_pci_context *ctx = __alchemy_pci_ctx; + if (!ctx) +@@ -326,7 +326,7 @@ static int alchemy_pci_suspend(void) + return 0; + } + +-static void alchemy_pci_resume(void) ++static void alchemy_pci_resume(void *data) + { + struct alchemy_pci_context *ctx = __alchemy_pci_ctx; + if (!ctx) +@@ -354,9 +354,13 @@ static void alchemy_pci_resume(void) + alchemy_pci_wired_entry(ctx); /* install it */ + } + +-static struct syscore_ops alchemy_pci_pmops = { +- .suspend = alchemy_pci_suspend, +- .resume = alchemy_pci_resume, ++static const struct syscore_ops alchemy_pci_syscore_ops = { ++ .suspend = alchemy_pci_suspend, ++ .resume = alchemy_pci_resume, ++}; ++ ++static struct syscore alchemy_pci_syscore = { ++ .ops = &alchemy_pci_syscore_ops, + }; + + static int alchemy_pci_probe(struct platform_device *pdev) +@@ -478,7 +482,7 @@ static int alchemy_pci_probe(struct platform_device *pdev) + + __alchemy_pci_ctx = ctx; + platform_set_drvdata(pdev, ctx); +- register_syscore_ops(&alchemy_pci_pmops); ++ register_syscore(&alchemy_pci_syscore); + register_pci_controller(&ctx->alchemy_pci_ctrl); + + dev_info(&pdev->dev, "PCI controller at %ld MHz\n", +diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c +index 2c07387201d0..2ddb93df4817 100644 +--- a/arch/powerpc/platforms/cell/spu_base.c ++++ b/arch/powerpc/platforms/cell/spu_base.c +@@ -726,7 +726,7 @@ static inline void crash_register_spus(struct list_head *list) + } + #endif + +-static void spu_shutdown(void) ++static void spu_shutdown(void *data) + { + struct spu *spu; + +@@ -738,10 +738,14 @@ static void spu_shutdown(void) + mutex_unlock(&spu_full_list_mutex); + } + +-static struct syscore_ops spu_syscore_ops = { ++static const struct syscore_ops spu_syscore_ops = { + .shutdown = spu_shutdown, + }; + ++static struct syscore spu_syscore = { ++ .ops = &spu_syscore_ops, ++}; ++ + static int __init init_spu_base(void) + { + int i, ret = 0; +@@ -774,7 +778,7 @@ static int __init init_spu_base(void) + crash_register_spus(&spu_full_list); + mutex_unlock(&spu_full_list_mutex); + spu_add_dev_attr(&dev_attr_stat); +- register_syscore_ops(&spu_syscore_ops); ++ register_syscore(&spu_syscore); + + spu_init_affinity(); + +diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c +index c37783a03d25..1959cc13438f 100644 +--- a/arch/powerpc/platforms/powermac/pic.c ++++ b/arch/powerpc/platforms/powermac/pic.c +@@ -600,7 +600,7 @@ static int pmacpic_find_viaint(void) + return viaint; + } + +-static int pmacpic_suspend(void) ++static int pmacpic_suspend(void *data) + { + int viaint = pmacpic_find_viaint(); + +@@ -621,7 +621,7 @@ static int pmacpic_suspend(void) + return 0; + } + +-static void pmacpic_resume(void) ++static void pmacpic_resume(void *data) + { + int i; + +@@ -634,15 +634,19 @@ static void pmacpic_resume(void) + pmac_unmask_irq(irq_get_irq_data(i)); + } + +-static struct syscore_ops pmacpic_syscore_ops = { ++static const struct syscore_ops pmacpic_syscore_ops = { + .suspend = pmacpic_suspend, + .resume = pmacpic_resume, + }; + ++static struct syscore pmacpic_syscore = { ++ .ops = &pmacpic_syscore_ops, ++}; ++ + static int __init init_pmacpic_syscore(void) + { + if (pmac_irq_hw[0]) +- register_syscore_ops(&pmacpic_syscore_ops); ++ register_syscore(&pmacpic_syscore); + return 0; + } + +diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c +index 217cea150987..7ed07232a69a 100644 +--- a/arch/powerpc/sysdev/fsl_lbc.c ++++ b/arch/powerpc/sysdev/fsl_lbc.c +@@ -350,7 +350,7 @@ static int fsl_lbc_ctrl_probe(struct platform_device *dev) + #ifdef CONFIG_SUSPEND + + /* save lbc registers */ +-static int fsl_lbc_syscore_suspend(void) ++static int fsl_lbc_syscore_suspend(void *data) + { + struct fsl_lbc_ctrl *ctrl; + struct fsl_lbc_regs __iomem *lbc; +@@ -374,7 +374,7 @@ static int fsl_lbc_syscore_suspend(void) + } + + /* restore lbc registers */ +-static void fsl_lbc_syscore_resume(void) ++static void fsl_lbc_syscore_resume(void *data) + { + struct fsl_lbc_ctrl *ctrl; + struct fsl_lbc_regs __iomem *lbc; +@@ -408,10 +408,14 @@ static const struct of_device_id fsl_lbc_match[] = { + }; + + #ifdef CONFIG_SUSPEND +-static struct syscore_ops lbc_syscore_pm_ops = { ++static const struct syscore_ops lbc_syscore_pm_ops = { + .suspend = fsl_lbc_syscore_suspend, + .resume = fsl_lbc_syscore_resume, + }; ++ ++static struct syscore lbc_syscore_pm = { ++ .ops = &lbc_syscore_pm_ops, ++}; + #endif + + static struct platform_driver fsl_lbc_ctrl_driver = { +@@ -425,7 +429,7 @@ static struct platform_driver fsl_lbc_ctrl_driver = { + static int __init fsl_lbc_init(void) + { + #ifdef CONFIG_SUSPEND +- register_syscore_ops(&lbc_syscore_pm_ops); ++ register_syscore(&lbc_syscore_pm); + #endif + return platform_driver_register(&fsl_lbc_ctrl_driver); + } +diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c +index ef7707ea0db7..4e501654cb41 100644 +--- a/arch/powerpc/sysdev/fsl_pci.c ++++ b/arch/powerpc/sysdev/fsl_pci.c +@@ -1258,7 +1258,7 @@ static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) + send_pme_turnoff_message(hose); + } + +-static int fsl_pci_syscore_suspend(void) ++static int fsl_pci_syscore_suspend(void *data) + { + struct pci_controller *hose, *tmp; + +@@ -1291,7 +1291,7 @@ static void fsl_pci_syscore_do_resume(struct pci_controller *hose) + setup_pci_atmu(hose); + } + +-static void fsl_pci_syscore_resume(void) ++static void fsl_pci_syscore_resume(void *data) + { + struct pci_controller *hose, *tmp; + +@@ -1299,10 +1299,14 @@ static void fsl_pci_syscore_resume(void) + fsl_pci_syscore_do_resume(hose); + } + +-static struct syscore_ops pci_syscore_pm_ops = { ++static const struct syscore_ops pci_syscore_pm_ops = { + .suspend = fsl_pci_syscore_suspend, + .resume = fsl_pci_syscore_resume, + }; ++ ++static struct syscore pci_syscore_pm = { ++ .ops = &pci_syscore_pm_ops, ++}; + #endif + + void fsl_pcibios_fixup_phb(struct pci_controller *phb) +@@ -1359,7 +1363,7 @@ static struct platform_driver fsl_pci_driver = { + static int __init fsl_pci_init(void) + { + #ifdef CONFIG_PM_SLEEP +- register_syscore_ops(&pci_syscore_pm_ops); ++ register_syscore(&pci_syscore_pm); + #endif + return platform_driver_register(&fsl_pci_driver); + } +diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c +index 70be2105865d..290ba8427239 100644 +--- a/arch/powerpc/sysdev/ipic.c ++++ b/arch/powerpc/sysdev/ipic.c +@@ -817,7 +817,7 @@ static struct { + u32 sercr; + } ipic_saved_state; + +-static int ipic_suspend(void) ++static int ipic_suspend(void *data) + { + struct ipic *ipic = primary_ipic; + +@@ -848,7 +848,7 @@ static int ipic_suspend(void) + return 0; + } + +-static void ipic_resume(void) ++static void ipic_resume(void *data) + { + struct ipic *ipic = primary_ipic; + +@@ -870,18 +870,22 @@ static void ipic_resume(void) + #define ipic_resume NULL + #endif + +-static struct syscore_ops ipic_syscore_ops = { ++static const struct syscore_ops ipic_syscore_ops = { + .suspend = ipic_suspend, + .resume = ipic_resume, + }; + ++static struct syscore ipic_syscore = { ++ .ops = &ipic_syscore_ops, ++}; ++ + static int __init init_ipic_syscore(void) + { + if (!primary_ipic || !primary_ipic->regs) + return -ENODEV; + + printk(KERN_DEBUG "Registering ipic system core operations\n"); +- register_syscore_ops(&ipic_syscore_ops); ++ register_syscore(&ipic_syscore); + + return 0; + } +diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c +index ad7310bba00b..67e51998d1ae 100644 +--- a/arch/powerpc/sysdev/mpic.c ++++ b/arch/powerpc/sysdev/mpic.c +@@ -1944,7 +1944,7 @@ static void mpic_suspend_one(struct mpic *mpic) + } + } + +-static int mpic_suspend(void) ++static int mpic_suspend(void *data) + { + struct mpic *mpic = mpics; + +@@ -1986,7 +1986,7 @@ static void mpic_resume_one(struct mpic *mpic) + } /* end for loop */ + } + +-static void mpic_resume(void) ++static void mpic_resume(void *data) + { + struct mpic *mpic = mpics; + +@@ -1996,19 +1996,23 @@ static void mpic_resume(void) + } + } + +-static struct syscore_ops mpic_syscore_ops = { ++static const struct syscore_ops mpic_syscore_ops = { + .resume = mpic_resume, + .suspend = mpic_suspend, + }; + ++static struct syscore mpic_syscore = { ++ .ops = &mpic_syscore_ops, ++}; ++ + static int mpic_init_sys(void) + { + int rc; + +- register_syscore_ops(&mpic_syscore_ops); ++ register_syscore(&mpic_syscore); + rc = subsys_system_register(&mpic_subsys, NULL); + if (rc) { +- unregister_syscore_ops(&mpic_syscore_ops); ++ unregister_syscore(&mpic_syscore); + pr_err("mpic: Failed to register subsystem!\n"); + return rc; + } +diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c +index 7166e2e0baaf..60f5b3934b51 100644 +--- a/arch/powerpc/sysdev/mpic_timer.c ++++ b/arch/powerpc/sysdev/mpic_timer.c +@@ -519,7 +519,7 @@ static void __init timer_group_init(struct device_node *np) + kfree(priv); + } + +-static void mpic_timer_resume(void) ++static void mpic_timer_resume(void *data) + { + struct timer_group_priv *priv; + +@@ -535,10 +535,14 @@ static const struct of_device_id mpic_timer_ids[] = { + {}, + }; + +-static struct syscore_ops mpic_timer_syscore_ops = { ++static const struct syscore_ops mpic_timer_syscore_ops = { + .resume = mpic_timer_resume, + }; + ++static struct syscore mpic_timer_syscore = { ++ .ops = &mpic_timer_syscore_ops, ++}; ++ + static int __init mpic_timer_init(void) + { + struct device_node *np = NULL; +@@ -546,7 +550,7 @@ static int __init mpic_timer_init(void) + for_each_matching_node(np, mpic_timer_ids) + timer_group_init(np); + +- register_syscore_ops(&mpic_timer_syscore_ops); ++ register_syscore(&mpic_timer_syscore); + + if (list_empty(&timer_group_list)) + return -ENODEV; +diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c +index 68eb7cc6e564..482eec50f404 100644 +--- a/arch/sh/mm/pmb.c ++++ b/arch/sh/mm/pmb.c +@@ -857,7 +857,7 @@ static int __init pmb_debugfs_init(void) + subsys_initcall(pmb_debugfs_init); + + #ifdef CONFIG_PM +-static void pmb_syscore_resume(void) ++static void pmb_syscore_resume(void *data) + { + struct pmb_entry *pmbe; + int i; +@@ -874,13 +874,17 @@ static void pmb_syscore_resume(void) + read_unlock(&pmb_rwlock); + } + +-static struct syscore_ops pmb_syscore_ops = { ++static const struct syscore_ops pmb_syscore_ops = { + .resume = pmb_syscore_resume, + }; + ++static struct syscore pmb_syscore = { ++ .ops = &pmb_syscore_ops, ++}; ++ + static int __init pmb_sysdev_init(void) + { +- register_syscore_ops(&pmb_syscore_ops); ++ register_syscore(&pmb_syscore); + return 0; + } + subsys_initcall(pmb_sysdev_init); +diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c +index 56918cd91115..23d834e7b565 100644 +--- a/arch/x86/events/amd/ibs.c ++++ b/arch/x86/events/amd/ibs.c +@@ -1719,26 +1719,30 @@ static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu) + + #ifdef CONFIG_PM + +-static int perf_ibs_suspend(void) ++static int perf_ibs_suspend(void *data) + { + clear_APIC_ibs(); + return 0; + } + +-static void perf_ibs_resume(void) ++static void perf_ibs_resume(void *data) + { + ibs_eilvt_setup(); + setup_APIC_ibs(); + } + +-static struct syscore_ops perf_ibs_syscore_ops = { ++static const struct syscore_ops perf_ibs_syscore_ops = { + .resume = perf_ibs_resume, + .suspend = perf_ibs_suspend, + }; + ++static struct syscore perf_ibs_syscore = { ++ .ops = &perf_ibs_syscore_ops, ++}; ++ + static void perf_ibs_pm_init(void) + { +- register_syscore_ops(&perf_ibs_syscore_ops); ++ register_syscore(&perf_ibs_syscore); + } + + #else +diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c +index e890fd37e9c2..085ef4f2e73a 100644 +--- a/arch/x86/hyperv/hv_init.c ++++ b/arch/x86/hyperv/hv_init.c +@@ -351,7 +351,7 @@ static int __init hv_pci_init(void) + return 1; + } + +-static int hv_suspend(void) ++static int hv_suspend(void *data) + { + union hv_x64_msr_hypercall_contents hypercall_msr; + int ret; +@@ -378,7 +378,7 @@ static int hv_suspend(void) + return ret; + } + +-static void hv_resume(void) ++static void hv_resume(void *data) + { + union hv_x64_msr_hypercall_contents hypercall_msr; + int ret; +@@ -405,11 +405,15 @@ static void hv_resume(void) + } + + /* Note: when the ops are called, only CPU0 is online and IRQs are disabled. */ +-static struct syscore_ops hv_syscore_ops = { ++static const struct syscore_ops hv_syscore_ops = { + .suspend = hv_suspend, + .resume = hv_resume, + }; + ++static struct syscore hv_syscore = { ++ .ops = &hv_syscore_ops, ++}; ++ + static void (* __initdata old_setup_percpu_clockev)(void); + + static void __init hv_stimer_setup_percpu_clockev(void) +@@ -569,7 +573,7 @@ void __init hyperv_init(void) + + x86_init.pci.arch_init = hv_pci_init; + +- register_syscore_ops(&hv_syscore_ops); ++ register_syscore(&hv_syscore); + + if (ms_hyperv.priv_high & HV_ACCESS_PARTITION_ID) + hv_get_partition_id(); +diff --git a/arch/x86/kernel/amd_gart_64.c b/arch/x86/kernel/amd_gart_64.c +index 3485d419c2f5..e6e68a31634c 100644 +--- a/arch/x86/kernel/amd_gart_64.c ++++ b/arch/x86/kernel/amd_gart_64.c +@@ -591,7 +591,7 @@ static void gart_fixup_northbridges(void) + } + } + +-static void gart_resume(void) ++static void gart_resume(void *data) + { + pr_info("PCI-DMA: Resuming GART IOMMU\n"); + +@@ -600,11 +600,15 @@ static void gart_resume(void) + enable_gart_translations(); + } + +-static struct syscore_ops gart_syscore_ops = { ++static const struct syscore_ops gart_syscore_ops = { + .resume = gart_resume, + + }; + ++static struct syscore gart_syscore = { ++ .ops = &gart_syscore_ops, ++}; ++ + /* + * Private Northbridge GATT initialization in case we cannot use the + * AGP driver for some reason. +@@ -650,7 +654,7 @@ static __init int init_amd_gatt(struct agp_kern_info *info) + + agp_gatt_table = gatt; + +- register_syscore_ops(&gart_syscore_ops); ++ register_syscore(&gart_syscore); + + flush_gart(); + +diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c +index aa1b0ef5e931..a4431f0d2580 100644 +--- a/arch/x86/kernel/apic/apic.c ++++ b/arch/x86/kernel/apic/apic.c +@@ -2382,7 +2382,7 @@ static struct { + unsigned int apic_cmci; + } apic_pm_state; + +-static int lapic_suspend(void) ++static int lapic_suspend(void *data) + { + unsigned long flags; + int maxlvt; +@@ -2430,7 +2430,7 @@ static int lapic_suspend(void) + return 0; + } + +-static void lapic_resume(void) ++static void lapic_resume(void *data) + { + unsigned int l, h; + unsigned long flags; +@@ -2510,11 +2510,15 @@ static void lapic_resume(void) + * are needed on every CPU up until machine_halt/restart/poweroff. + */ + +-static struct syscore_ops lapic_syscore_ops = { ++static const struct syscore_ops lapic_syscore_ops = { + .resume = lapic_resume, + .suspend = lapic_suspend, + }; + ++static struct syscore lapic_syscore = { ++ .ops = &lapic_syscore_ops, ++}; ++ + static void apic_pm_activate(void) + { + apic_pm_state.active = 1; +@@ -2524,7 +2528,7 @@ static int __init init_lapic_sysfs(void) + { + /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ + if (boot_cpu_has(X86_FEATURE_APIC)) +- register_syscore_ops(&lapic_syscore_ops); ++ register_syscore(&lapic_syscore); + + return 0; + } +diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c +index 5ba2feb2c04c..84e200662ce6 100644 +--- a/arch/x86/kernel/apic/io_apic.c ++++ b/arch/x86/kernel/apic/io_apic.c +@@ -2308,7 +2308,12 @@ static void resume_ioapic_id(int ioapic_idx) + } + } + +-static void ioapic_resume(void) ++static int ioapic_suspend(void *data) ++{ ++ return save_ioapic_entries(); ++} ++ ++static void ioapic_resume(void *data) + { + int ioapic_idx; + +@@ -2318,14 +2323,18 @@ static void ioapic_resume(void) + restore_ioapic_entries(); + } + +-static struct syscore_ops ioapic_syscore_ops = { +- .suspend = save_ioapic_entries, ++static const struct syscore_ops ioapic_syscore_ops = { ++ .suspend = ioapic_suspend, + .resume = ioapic_resume, + }; + ++static struct syscore ioapic_syscore = { ++ .ops = &ioapic_syscore_ops, ++}; ++ + static int __init ioapic_init_ops(void) + { +- register_syscore_ops(&ioapic_syscore_ops); ++ register_syscore(&ioapic_syscore); + + return 0; + } +diff --git a/arch/x86/kernel/cpu/aperfmperf.c b/arch/x86/kernel/cpu/aperfmperf.c +index a315b0627dfb..7ffc78d5ebf2 100644 +--- a/arch/x86/kernel/cpu/aperfmperf.c ++++ b/arch/x86/kernel/cpu/aperfmperf.c +@@ -37,7 +37,7 @@ static DEFINE_PER_CPU_SHARED_ALIGNED(struct aperfmperf, cpu_samples) = { + .seq = SEQCNT_ZERO(cpu_samples.seq) + }; + +-static void init_counter_refs(void) ++static void init_counter_refs(void *data) + { + u64 aperf, mperf; + +@@ -289,16 +289,20 @@ static bool __init intel_set_max_freq_ratio(void) + } + + #ifdef CONFIG_PM_SLEEP +-static struct syscore_ops freq_invariance_syscore_ops = { ++static const struct syscore_ops freq_invariance_syscore_ops = { + .resume = init_counter_refs, + }; + +-static void register_freq_invariance_syscore_ops(void) ++static struct syscore freq_invariance_syscore = { ++ .ops = &freq_invariance_syscore_ops, ++}; ++ ++static void register_freq_invariance_syscore(void) + { +- register_syscore_ops(&freq_invariance_syscore_ops); ++ register_syscore(&freq_invariance_syscore); + } + #else +-static inline void register_freq_invariance_syscore_ops(void) {} ++static inline void register_freq_invariance_syscore(void) {} + #endif + + static void freq_invariance_enable(void) +@@ -308,7 +312,7 @@ static void freq_invariance_enable(void) + return; + } + static_branch_enable_cpuslocked(&arch_scale_freq_key); +- register_freq_invariance_syscore_ops(); ++ register_freq_invariance_syscore(); + pr_info("Estimated ratio of average max frequency by base frequency (times 1024): %llu\n", arch_max_freq_ratio); + } + +@@ -535,7 +539,7 @@ static int __init bp_init_aperfmperf(void) + if (!cpu_feature_enabled(X86_FEATURE_APERFMPERF)) + return 0; + +- init_counter_refs(); ++ init_counter_refs(NULL); + bp_init_freq_invariance(); + return 0; + } +@@ -544,5 +548,5 @@ early_initcall(bp_init_aperfmperf); + void ap_init_aperfmperf(void) + { + if (cpu_feature_enabled(X86_FEATURE_APERFMPERF)) +- init_counter_refs(); ++ init_counter_refs(NULL); + } +diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c +index bc7671f920a7..2c56f8730f59 100644 +--- a/arch/x86/kernel/cpu/intel_epb.c ++++ b/arch/x86/kernel/cpu/intel_epb.c +@@ -75,7 +75,7 @@ static u8 energ_perf_values[] = { + [EPB_INDEX_POWERSAVE] = ENERGY_PERF_BIAS_POWERSAVE, + }; + +-static int intel_epb_save(void) ++static int intel_epb_save(void *data) + { + u64 epb; + +@@ -89,7 +89,7 @@ static int intel_epb_save(void) + return 0; + } + +-static void intel_epb_restore(void) ++static void intel_epb_restore(void *data) + { + u64 val = this_cpu_read(saved_epb); + u64 epb; +@@ -114,11 +114,15 @@ static void intel_epb_restore(void) + wrmsrq(MSR_IA32_ENERGY_PERF_BIAS, (epb & ~EPB_MASK) | val); + } + +-static struct syscore_ops intel_epb_syscore_ops = { ++static const struct syscore_ops intel_epb_syscore_ops = { + .suspend = intel_epb_save, + .resume = intel_epb_restore, + }; + ++static struct syscore intel_epb_syscore = { ++ .ops = &intel_epb_syscore_ops, ++}; ++ + static const char * const energy_perf_strings[] = { + [EPB_INDEX_PERFORMANCE] = "performance", + [EPB_INDEX_BALANCE_PERFORMANCE] = "balance-performance", +@@ -185,7 +189,7 @@ static int intel_epb_online(unsigned int cpu) + { + struct device *cpu_dev = get_cpu_device(cpu); + +- intel_epb_restore(); ++ intel_epb_restore(NULL); + if (!cpuhp_tasks_frozen) + sysfs_merge_group(&cpu_dev->kobj, &intel_epb_attr_group); + +@@ -199,7 +203,7 @@ static int intel_epb_offline(unsigned int cpu) + if (!cpuhp_tasks_frozen) + sysfs_unmerge_group(&cpu_dev->kobj, &intel_epb_attr_group); + +- intel_epb_save(); ++ intel_epb_save(NULL); + return 0; + } + +@@ -230,7 +234,7 @@ static __init int intel_epb_init(void) + if (ret < 0) + goto err_out_online; + +- register_syscore_ops(&intel_epb_syscore_ops); ++ register_syscore(&intel_epb_syscore); + return 0; + + err_out_online: +diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c +index c8b112c6c549..26c98d9002bc 100644 +--- a/arch/x86/kernel/cpu/mce/core.c ++++ b/arch/x86/kernel/cpu/mce/core.c +@@ -2387,13 +2387,13 @@ static void vendor_disable_error_reporting(void) + mce_disable_error_reporting(); + } + +-static int mce_syscore_suspend(void) ++static int mce_syscore_suspend(void *data) + { + vendor_disable_error_reporting(); + return 0; + } + +-static void mce_syscore_shutdown(void) ++static void mce_syscore_shutdown(void *data) + { + vendor_disable_error_reporting(); + } +@@ -2403,7 +2403,7 @@ static void mce_syscore_shutdown(void) + * Only one CPU is active at this time, the others get re-added later using + * CPU hotplug: + */ +-static void mce_syscore_resume(void) ++static void mce_syscore_resume(void *data) + { + __mcheck_cpu_init_generic(); + __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); +@@ -2411,12 +2411,16 @@ static void mce_syscore_resume(void) + cr4_set_bits(X86_CR4_MCE); + } + +-static struct syscore_ops mce_syscore_ops = { ++static const struct syscore_ops mce_syscore_ops = { + .suspend = mce_syscore_suspend, + .shutdown = mce_syscore_shutdown, + .resume = mce_syscore_resume, + }; + ++static struct syscore mce_syscore = { ++ .ops = &mce_syscore_ops, ++}; ++ + /* + * mce_device: Sysfs support + */ +@@ -2817,7 +2821,7 @@ static __init int mcheck_init_device(void) + if (err < 0) + goto err_out_online; + +- register_syscore_ops(&mce_syscore_ops); ++ register_syscore(&mce_syscore); + + return 0; + +diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c +index 539edd6d6dc8..81aa079fad26 100644 +--- a/arch/x86/kernel/cpu/microcode/core.c ++++ b/arch/x86/kernel/cpu/microcode/core.c +@@ -812,8 +812,17 @@ void microcode_bsp_resume(void) + reload_early_microcode(cpu); + } + +-static struct syscore_ops mc_syscore_ops = { +- .resume = microcode_bsp_resume, ++static void microcode_bsp_syscore_resume(void *data) ++{ ++ microcode_bsp_resume(); ++} ++ ++static const struct syscore_ops mc_syscore_ops = { ++ .resume = microcode_bsp_syscore_resume, ++}; ++ ++static struct syscore mc_syscore = { ++ .ops = &mc_syscore_ops, + }; + + static int mc_cpu_online(unsigned int cpu) +@@ -892,7 +901,7 @@ static int __init microcode_init(void) + } + } + +- register_syscore_ops(&mc_syscore_ops); ++ register_syscore(&mc_syscore); + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", + mc_cpu_online, mc_cpu_down_prep); + +diff --git a/arch/x86/kernel/cpu/mtrr/legacy.c b/arch/x86/kernel/cpu/mtrr/legacy.c +index d25882fcf181..2415ffaaf02c 100644 +--- a/arch/x86/kernel/cpu/mtrr/legacy.c ++++ b/arch/x86/kernel/cpu/mtrr/legacy.c +@@ -41,7 +41,7 @@ struct mtrr_value { + + static struct mtrr_value *mtrr_value; + +-static int mtrr_save(void) ++static int mtrr_save(void *data) + { + int i; + +@@ -56,7 +56,7 @@ static int mtrr_save(void) + return 0; + } + +-static void mtrr_restore(void) ++static void mtrr_restore(void *data) + { + int i; + +@@ -69,11 +69,15 @@ static void mtrr_restore(void) + } + } + +-static struct syscore_ops mtrr_syscore_ops = { ++static const struct syscore_ops mtrr_syscore_ops = { + .suspend = mtrr_save, + .resume = mtrr_restore, + }; + ++static struct syscore mtrr_syscore = { ++ .ops = &mtrr_syscore_ops, ++}; ++ + void mtrr_register_syscore(void) + { + mtrr_value = kcalloc(num_var_ranges, sizeof(*mtrr_value), GFP_KERNEL); +@@ -86,5 +90,5 @@ void mtrr_register_syscore(void) + * TBD: is there any system with such CPU which supports + * suspend/resume? If no, we should remove the code. + */ +- register_syscore_ops(&mtrr_syscore_ops); ++ register_syscore(&mtrr_syscore); + } +diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c +index 933fcd7ff250..e4a31c536642 100644 +--- a/arch/x86/kernel/cpu/umwait.c ++++ b/arch/x86/kernel/cpu/umwait.c +@@ -86,15 +86,19 @@ static int umwait_cpu_offline(unsigned int cpu) + * trust the firmware nor does it matter if the same value is written + * again. + */ +-static void umwait_syscore_resume(void) ++static void umwait_syscore_resume(void *data) + { + umwait_update_control_msr(NULL); + } + +-static struct syscore_ops umwait_syscore_ops = { ++static const struct syscore_ops umwait_syscore_ops = { + .resume = umwait_syscore_resume, + }; + ++static struct syscore umwait_syscore = { ++ .ops = &umwait_syscore_ops, ++}; ++ + /* sysfs interface */ + + /* +@@ -226,7 +230,7 @@ static int __init umwait_init(void) + return ret; + } + +- register_syscore_ops(&umwait_syscore_ops); ++ register_syscore(&umwait_syscore); + + /* + * Add umwait control interface. Ignore failure, so at least the +diff --git a/arch/x86/kernel/i8237.c b/arch/x86/kernel/i8237.c +index 2cd124ad9380..896d46b44284 100644 +--- a/arch/x86/kernel/i8237.c ++++ b/arch/x86/kernel/i8237.c +@@ -19,7 +19,7 @@ + * in asm/dma.h. + */ + +-static void i8237A_resume(void) ++static void i8237A_resume(void *data) + { + unsigned long flags; + int i; +@@ -41,10 +41,14 @@ static void i8237A_resume(void) + release_dma_lock(flags); + } + +-static struct syscore_ops i8237_syscore_ops = { ++static const struct syscore_ops i8237_syscore_ops = { + .resume = i8237A_resume, + }; + ++static struct syscore i8237_syscore = { ++ .ops = &i8237_syscore_ops, ++}; ++ + static int __init i8237A_init_ops(void) + { + /* +@@ -70,7 +74,7 @@ static int __init i8237A_init_ops(void) + if (x86_pnpbios_disabled() && dmi_get_bios_year() >= 2017) + return -ENODEV; + +- register_syscore_ops(&i8237_syscore_ops); ++ register_syscore(&i8237_syscore); + return 0; + } + device_initcall(i8237A_init_ops); +diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c +index 2bade73f49e3..f67063df6723 100644 +--- a/arch/x86/kernel/i8259.c ++++ b/arch/x86/kernel/i8259.c +@@ -247,19 +247,19 @@ static void save_ELCR(char *trigger) + trigger[1] = inb(PIC_ELCR2) & 0xDE; + } + +-static void i8259A_resume(void) ++static void i8259A_resume(void *data) + { + init_8259A(i8259A_auto_eoi); + restore_ELCR(irq_trigger); + } + +-static int i8259A_suspend(void) ++static int i8259A_suspend(void *data) + { + save_ELCR(irq_trigger); + return 0; + } + +-static void i8259A_shutdown(void) ++static void i8259A_shutdown(void *data) + { + /* Put the i8259A into a quiescent state that + * the kernel initialization code can get it +@@ -269,12 +269,16 @@ static void i8259A_shutdown(void) + outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ + } + +-static struct syscore_ops i8259_syscore_ops = { ++static const struct syscore_ops i8259_syscore_ops = { + .suspend = i8259A_suspend, + .resume = i8259A_resume, + .shutdown = i8259A_shutdown, + }; + ++static struct syscore i8259_syscore = { ++ .ops = &i8259_syscore_ops, ++}; ++ + static void mask_8259A(void) + { + unsigned long flags; +@@ -444,7 +448,7 @@ EXPORT_SYMBOL(legacy_pic); + static int __init i8259A_init_ops(void) + { + if (legacy_pic == &default_legacy_pic) +- register_syscore_ops(&i8259_syscore_ops); ++ register_syscore(&i8259_syscore); + + return 0; + } +diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c +index b67d7c59dca0..1500852ba03c 100644 +--- a/arch/x86/kernel/kvm.c ++++ b/arch/x86/kernel/kvm.c +@@ -720,7 +720,7 @@ static int kvm_cpu_down_prepare(unsigned int cpu) + + #endif + +-static int kvm_suspend(void) ++static int kvm_suspend(void *data) + { + u64 val = 0; + +@@ -734,7 +734,7 @@ static int kvm_suspend(void) + return 0; + } + +-static void kvm_resume(void) ++static void kvm_resume(void *data) + { + kvm_cpu_online(raw_smp_processor_id()); + +@@ -744,11 +744,15 @@ static void kvm_resume(void) + #endif + } + +-static struct syscore_ops kvm_syscore_ops = { ++static const struct syscore_ops kvm_syscore_ops = { + .suspend = kvm_suspend, + .resume = kvm_resume, + }; + ++static struct syscore kvm_syscore = { ++ .ops = &kvm_syscore_ops, ++}; ++ + static void kvm_pv_guest_cpu_reboot(void *unused) + { + kvm_guest_cpu_offline(true); +@@ -858,7 +862,7 @@ static void __init kvm_guest_init(void) + machine_ops.crash_shutdown = kvm_crash_shutdown; + #endif + +- register_syscore_ops(&kvm_syscore_ops); ++ register_syscore(&kvm_syscore); + + /* + * Hard lockup detection is enabled by default. Disable it, as guests +diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c +index e4560b33b8ad..bed7dc85612e 100644 +--- a/drivers/acpi/pci_link.c ++++ b/drivers/acpi/pci_link.c +@@ -761,7 +761,7 @@ static int acpi_pci_link_resume(struct acpi_pci_link *link) + return 0; + } + +-static void irqrouter_resume(void) ++static void irqrouter_resume(void *data) + { + struct acpi_pci_link *link; + +@@ -888,10 +888,14 @@ static int __init acpi_irq_balance_set(char *str) + + __setup("acpi_irq_balance", acpi_irq_balance_set); + +-static struct syscore_ops irqrouter_syscore_ops = { ++static const struct syscore_ops irqrouter_syscore_ops = { + .resume = irqrouter_resume, + }; + ++static struct syscore irqrouter_syscore = { ++ .ops = &irqrouter_syscore_ops, ++}; ++ + void __init acpi_pci_link_init(void) + { + if (acpi_noirq) +@@ -904,6 +908,6 @@ void __init acpi_pci_link_init(void) + else + acpi_irq_balance = 0; + } +- register_syscore_ops(&irqrouter_syscore_ops); ++ register_syscore(&irqrouter_syscore); + acpi_scan_add_handler(&pci_link_handler); + } +diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c +index 0b7fa4a8c379..1b9579bb97c2 100644 +--- a/drivers/acpi/sleep.c ++++ b/drivers/acpi/sleep.c +@@ -892,13 +892,13 @@ bool acpi_s2idle_wakeup(void) + #ifdef CONFIG_PM_SLEEP + static u32 saved_bm_rld; + +-static int acpi_save_bm_rld(void) ++static int acpi_save_bm_rld(void *data) + { + acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); + return 0; + } + +-static void acpi_restore_bm_rld(void) ++static void acpi_restore_bm_rld(void *data) + { + u32 resumed_bm_rld = 0; + +@@ -909,14 +909,18 @@ static void acpi_restore_bm_rld(void) + acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); + } + +-static struct syscore_ops acpi_sleep_syscore_ops = { ++static const struct syscore_ops acpi_sleep_syscore_ops = { + .suspend = acpi_save_bm_rld, + .resume = acpi_restore_bm_rld, + }; + ++static struct syscore acpi_sleep_syscore = { ++ .ops = &acpi_sleep_syscore_ops, ++}; ++ + static void acpi_sleep_syscore_init(void) + { +- register_syscore_ops(&acpi_sleep_syscore_ops); ++ register_syscore(&acpi_sleep_syscore); + } + #else + static inline void acpi_sleep_syscore_init(void) {} +diff --git a/drivers/base/firmware_loader/main.c b/drivers/base/firmware_loader/main.c +index 6942c62fa59d..8191dbab92c4 100644 +--- a/drivers/base/firmware_loader/main.c ++++ b/drivers/base/firmware_loader/main.c +@@ -1585,16 +1585,20 @@ static int fw_pm_notify(struct notifier_block *notify_block, + } + + /* stop caching firmware once syscore_suspend is reached */ +-static int fw_suspend(void) ++static int fw_suspend(void *data) + { + fw_cache.state = FW_LOADER_NO_CACHE; + return 0; + } + +-static struct syscore_ops fw_syscore_ops = { ++static const struct syscore_ops fw_syscore_ops = { + .suspend = fw_suspend, + }; + ++static struct syscore fw_syscore = { ++ .ops = &fw_syscore_ops, ++}; ++ + static int __init register_fw_pm_ops(void) + { + int ret; +@@ -1610,14 +1614,14 @@ static int __init register_fw_pm_ops(void) + if (ret) + return ret; + +- register_syscore_ops(&fw_syscore_ops); ++ register_syscore(&fw_syscore); + + return ret; + } + + static inline void unregister_fw_pm_ops(void) + { +- unregister_syscore_ops(&fw_syscore_ops); ++ unregister_syscore(&fw_syscore); + unregister_pm_notifier(&fw_cache.pm_notify); + } + #else +diff --git a/drivers/base/syscore.c b/drivers/base/syscore.c +index 13db1f78d2ce..483adb796654 100644 +--- a/drivers/base/syscore.c ++++ b/drivers/base/syscore.c +@@ -11,32 +11,32 @@ + #include + #include + +-static LIST_HEAD(syscore_ops_list); +-static DEFINE_MUTEX(syscore_ops_lock); ++static LIST_HEAD(syscore_list); ++static DEFINE_MUTEX(syscore_lock); + + /** +- * register_syscore_ops - Register a set of system core operations. +- * @ops: System core operations to register. ++ * register_syscore - Register a set of system core operations. ++ * @syscore: System core operations to register. + */ +-void register_syscore_ops(struct syscore_ops *ops) ++void register_syscore(struct syscore *syscore) + { +- mutex_lock(&syscore_ops_lock); +- list_add_tail(&ops->node, &syscore_ops_list); +- mutex_unlock(&syscore_ops_lock); ++ mutex_lock(&syscore_lock); ++ list_add_tail(&syscore->node, &syscore_list); ++ mutex_unlock(&syscore_lock); + } +-EXPORT_SYMBOL_GPL(register_syscore_ops); ++EXPORT_SYMBOL_GPL(register_syscore); + + /** +- * unregister_syscore_ops - Unregister a set of system core operations. +- * @ops: System core operations to unregister. ++ * unregister_syscore - Unregister a set of system core operations. ++ * @syscore: System core operations to unregister. + */ +-void unregister_syscore_ops(struct syscore_ops *ops) ++void unregister_syscore(struct syscore *syscore) + { +- mutex_lock(&syscore_ops_lock); +- list_del(&ops->node); +- mutex_unlock(&syscore_ops_lock); ++ mutex_lock(&syscore_lock); ++ list_del(&syscore->node); ++ mutex_unlock(&syscore_lock); + } +-EXPORT_SYMBOL_GPL(unregister_syscore_ops); ++EXPORT_SYMBOL_GPL(unregister_syscore); + + #ifdef CONFIG_PM_SLEEP + /** +@@ -46,7 +46,7 @@ EXPORT_SYMBOL_GPL(unregister_syscore_ops); + */ + int syscore_suspend(void) + { +- struct syscore_ops *ops; ++ struct syscore *syscore; + int ret = 0; + + trace_suspend_resume(TPS("syscore_suspend"), 0, true); +@@ -59,25 +59,27 @@ int syscore_suspend(void) + WARN_ONCE(!irqs_disabled(), + "Interrupts enabled before system core suspend.\n"); + +- list_for_each_entry_reverse(ops, &syscore_ops_list, node) +- if (ops->suspend) { +- pm_pr_dbg("Calling %pS\n", ops->suspend); +- ret = ops->suspend(); ++ list_for_each_entry_reverse(syscore, &syscore_list, node) ++ if (syscore->ops->suspend) { ++ pm_pr_dbg("Calling %pS\n", syscore->ops->suspend); ++ ret = syscore->ops->suspend(syscore->data); + if (ret) + goto err_out; + WARN_ONCE(!irqs_disabled(), +- "Interrupts enabled after %pS\n", ops->suspend); ++ "Interrupts enabled after %pS\n", ++ syscore->ops->suspend); + } + + trace_suspend_resume(TPS("syscore_suspend"), 0, false); + return 0; + + err_out: +- pr_err("PM: System core suspend callback %pS failed.\n", ops->suspend); ++ pr_err("PM: System core suspend callback %pS failed.\n", ++ syscore->ops->suspend); + +- list_for_each_entry_continue(ops, &syscore_ops_list, node) +- if (ops->resume) +- ops->resume(); ++ list_for_each_entry_continue(syscore, &syscore_list, node) ++ if (syscore->ops->resume) ++ syscore->ops->resume(syscore->data); + + return ret; + } +@@ -90,18 +92,19 @@ EXPORT_SYMBOL_GPL(syscore_suspend); + */ + void syscore_resume(void) + { +- struct syscore_ops *ops; ++ struct syscore *syscore; + + trace_suspend_resume(TPS("syscore_resume"), 0, true); + WARN_ONCE(!irqs_disabled(), + "Interrupts enabled before system core resume.\n"); + +- list_for_each_entry(ops, &syscore_ops_list, node) +- if (ops->resume) { +- pm_pr_dbg("Calling %pS\n", ops->resume); +- ops->resume(); ++ list_for_each_entry(syscore, &syscore_list, node) ++ if (syscore->ops->resume) { ++ pm_pr_dbg("Calling %pS\n", syscore->ops->resume); ++ syscore->ops->resume(syscore->data); + WARN_ONCE(!irqs_disabled(), +- "Interrupts enabled after %pS\n", ops->resume); ++ "Interrupts enabled after %pS\n", ++ syscore->ops->resume); + } + trace_suspend_resume(TPS("syscore_resume"), 0, false); + } +@@ -113,16 +116,17 @@ EXPORT_SYMBOL_GPL(syscore_resume); + */ + void syscore_shutdown(void) + { +- struct syscore_ops *ops; ++ struct syscore *syscore; + +- mutex_lock(&syscore_ops_lock); ++ mutex_lock(&syscore_lock); + +- list_for_each_entry_reverse(ops, &syscore_ops_list, node) +- if (ops->shutdown) { ++ list_for_each_entry_reverse(syscore, &syscore_list, node) ++ if (syscore->ops->shutdown) { + if (initcall_debug) +- pr_info("PM: Calling %pS\n", ops->shutdown); +- ops->shutdown(); ++ pr_info("PM: Calling %pS\n", ++ syscore->ops->shutdown); ++ syscore->ops->shutdown(syscore->data); + } + +- mutex_unlock(&syscore_ops_lock); ++ mutex_unlock(&syscore_lock); + } +diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c +index 00cb792bda18..dd94145c9b22 100644 +--- a/drivers/bus/mvebu-mbus.c ++++ b/drivers/bus/mvebu-mbus.c +@@ -1006,7 +1006,7 @@ static __init int mvebu_mbus_debugfs_init(void) + } + fs_initcall(mvebu_mbus_debugfs_init); + +-static int mvebu_mbus_suspend(void) ++static int mvebu_mbus_suspend(void *data) + { + struct mvebu_mbus_state *s = &mbus_state; + int win; +@@ -1040,7 +1040,7 @@ static int mvebu_mbus_suspend(void) + return 0; + } + +-static void mvebu_mbus_resume(void) ++static void mvebu_mbus_resume(void *data) + { + struct mvebu_mbus_state *s = &mbus_state; + int win; +@@ -1069,9 +1069,13 @@ static void mvebu_mbus_resume(void) + } + } + +-static struct syscore_ops mvebu_mbus_syscore_ops = { +- .suspend = mvebu_mbus_suspend, +- .resume = mvebu_mbus_resume, ++static const struct syscore_ops mvebu_mbus_syscore_ops = { ++ .suspend = mvebu_mbus_suspend, ++ .resume = mvebu_mbus_resume, ++}; ++ ++static struct syscore mvebu_mbus_syscore = { ++ .ops = &mvebu_mbus_syscore_ops, + }; + + static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, +@@ -1118,7 +1122,7 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, + writel(UNIT_SYNC_BARRIER_ALL, + mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF); + +- register_syscore_ops(&mvebu_mbus_syscore_ops); ++ register_syscore(&mvebu_mbus_syscore); + + return 0; + } +diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c +index acf780a81589..2310f6f73162 100644 +--- a/drivers/clk/at91/pmc.c ++++ b/drivers/clk/at91/pmc.c +@@ -115,7 +115,7 @@ struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, + /* Address in SECURAM that say if we suspend to backup mode. */ + static void __iomem *at91_pmc_backup_suspend; + +-static int at91_pmc_suspend(void) ++static int at91_pmc_suspend(void *data) + { + unsigned int backup; + +@@ -129,7 +129,7 @@ static int at91_pmc_suspend(void) + return clk_save_context(); + } + +-static void at91_pmc_resume(void) ++static void at91_pmc_resume(void *data) + { + unsigned int backup; + +@@ -143,11 +143,15 @@ static void at91_pmc_resume(void) + clk_restore_context(); + } + +-static struct syscore_ops pmc_syscore_ops = { ++static const struct syscore_ops pmc_syscore_ops = { + .suspend = at91_pmc_suspend, + .resume = at91_pmc_resume, + }; + ++static struct syscore pmc_syscore = { ++ .ops = &pmc_syscore_ops, ++}; ++ + static const struct of_device_id pmc_dt_ids[] = { + { .compatible = "atmel,sama5d2-pmc" }, + { .compatible = "microchip,sama7g5-pmc", }, +@@ -185,7 +189,7 @@ static int __init pmc_register_ops(void) + return -ENOMEM; + } + +- register_syscore_ops(&pmc_syscore_ops); ++ register_syscore(&pmc_syscore); + + return 0; + } +diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c +index 9e11f1c7c397..41eb38552a9c 100644 +--- a/drivers/clk/imx/clk-vf610.c ++++ b/drivers/clk/imx/clk-vf610.c +@@ -139,7 +139,7 @@ static struct clk * __init vf610_get_fixed_clock( + return clk; + }; + +-static int vf610_clk_suspend(void) ++static int vf610_clk_suspend(void *data) + { + int i; + +@@ -156,7 +156,7 @@ static int vf610_clk_suspend(void) + return 0; + } + +-static void vf610_clk_resume(void) ++static void vf610_clk_resume(void *data) + { + int i; + +@@ -171,11 +171,15 @@ static void vf610_clk_resume(void) + writel_relaxed(ccgr[i], CCM_CCGRx(i)); + } + +-static struct syscore_ops vf610_clk_syscore_ops = { ++static const struct syscore_ops vf610_clk_syscore_ops = { + .suspend = vf610_clk_suspend, + .resume = vf610_clk_resume, + }; + ++static struct syscore vf610_clk_syscore = { ++ .ops = &vf610_clk_syscore_ops, ++}; ++ + static void __init vf610_clocks_init(struct device_node *ccm_node) + { + struct device_node *np; +@@ -462,7 +466,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) + clk_prepare_enable(clk[clks_init_on[i]]); + +- register_syscore_ops(&vf610_clk_syscore_ops); ++ register_syscore(&vf610_clk_syscore); + + /* Add the clocks to provider list */ + clk_data.clks = clk; +diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c +index 590e9c85cb25..94cee44c854f 100644 +--- a/drivers/clk/ingenic/jz4725b-cgu.c ++++ b/drivers/clk/ingenic/jz4725b-cgu.c +@@ -268,6 +268,6 @@ static void __init jz4725b_cgu_init(struct device_node *np) + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init); +diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c +index 3e0a30574ebb..2def3aedc8dd 100644 +--- a/drivers/clk/ingenic/jz4740-cgu.c ++++ b/drivers/clk/ingenic/jz4740-cgu.c +@@ -266,6 +266,6 @@ static void __init jz4740_cgu_init(struct device_node *np) + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init); +diff --git a/drivers/clk/ingenic/jz4755-cgu.c b/drivers/clk/ingenic/jz4755-cgu.c +index f2c2d848dab7..17cf5dcaece9 100644 +--- a/drivers/clk/ingenic/jz4755-cgu.c ++++ b/drivers/clk/ingenic/jz4755-cgu.c +@@ -337,7 +337,7 @@ static void __init jz4755_cgu_init(struct device_node *np) + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + /* + * CGU has some children devices, this is useful for probing children devices +diff --git a/drivers/clk/ingenic/jz4760-cgu.c b/drivers/clk/ingenic/jz4760-cgu.c +index e407f00bd594..372fe4b07992 100644 +--- a/drivers/clk/ingenic/jz4760-cgu.c ++++ b/drivers/clk/ingenic/jz4760-cgu.c +@@ -436,7 +436,7 @@ static void __init jz4760_cgu_init(struct device_node *np) + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + + /* We only probe via devicetree, no need for a platform driver */ +diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c +index 6ae1740367f9..58f1d3bad677 100644 +--- a/drivers/clk/ingenic/jz4770-cgu.c ++++ b/drivers/clk/ingenic/jz4770-cgu.c +@@ -456,7 +456,7 @@ static void __init jz4770_cgu_init(struct device_node *np) + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + + /* We only probe via devicetree, no need for a platform driver */ +diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c +index 07e2f3c5c454..1e88aef7ac0f 100644 +--- a/drivers/clk/ingenic/jz4780-cgu.c ++++ b/drivers/clk/ingenic/jz4780-cgu.c +@@ -803,6 +803,6 @@ static void __init jz4780_cgu_init(struct device_node *np) + return; + } + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init); +diff --git a/drivers/clk/ingenic/pm.c b/drivers/clk/ingenic/pm.c +index 341752b640d2..206d5cf2872f 100644 +--- a/drivers/clk/ingenic/pm.c ++++ b/drivers/clk/ingenic/pm.c +@@ -15,7 +15,7 @@ + + static void __iomem * __maybe_unused ingenic_cgu_base; + +-static int __maybe_unused ingenic_cgu_pm_suspend(void) ++static int __maybe_unused ingenic_cgu_pm_suspend(void *data) + { + u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); + +@@ -24,22 +24,26 @@ static int __maybe_unused ingenic_cgu_pm_suspend(void) + return 0; + } + +-static void __maybe_unused ingenic_cgu_pm_resume(void) ++static void __maybe_unused ingenic_cgu_pm_resume(void *data) + { + u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); + + writel(val & ~LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR); + } + +-static struct syscore_ops __maybe_unused ingenic_cgu_pm_ops = { ++static const struct syscore_ops __maybe_unused ingenic_cgu_pm_ops = { + .suspend = ingenic_cgu_pm_suspend, + .resume = ingenic_cgu_pm_resume, + }; + +-void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu) ++static struct syscore __maybe_unused ingenic_cgu_pm = { ++ .ops = &ingenic_cgu_pm_ops, ++}; ++ ++void ingenic_cgu_register_syscore(struct ingenic_cgu *cgu) + { + if (IS_ENABLED(CONFIG_PM_SLEEP)) { + ingenic_cgu_base = cgu->base; +- register_syscore_ops(&ingenic_cgu_pm_ops); ++ register_syscore(&ingenic_cgu_pm); + } + } +diff --git a/drivers/clk/ingenic/pm.h b/drivers/clk/ingenic/pm.h +index fa7540407b6b..0dcb57dc64cb 100644 +--- a/drivers/clk/ingenic/pm.h ++++ b/drivers/clk/ingenic/pm.h +@@ -7,6 +7,6 @@ + + struct ingenic_cgu; + +-void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu); ++void ingenic_cgu_register_syscore(struct ingenic_cgu *cgu); + + #endif /* DRIVERS_CLK_INGENIC_PM_H */ +diff --git a/drivers/clk/ingenic/tcu.c b/drivers/clk/ingenic/tcu.c +index 7d04ef40b7cf..bc6a51da2072 100644 +--- a/drivers/clk/ingenic/tcu.c ++++ b/drivers/clk/ingenic/tcu.c +@@ -455,7 +455,7 @@ static int __init ingenic_tcu_probe(struct device_node *np) + return ret; + } + +-static int __maybe_unused tcu_pm_suspend(void) ++static int __maybe_unused tcu_pm_suspend(void *data) + { + struct ingenic_tcu *tcu = ingenic_tcu; + +@@ -465,7 +465,7 @@ static int __maybe_unused tcu_pm_suspend(void) + return 0; + } + +-static void __maybe_unused tcu_pm_resume(void) ++static void __maybe_unused tcu_pm_resume(void *data) + { + struct ingenic_tcu *tcu = ingenic_tcu; + +@@ -473,11 +473,15 @@ static void __maybe_unused tcu_pm_resume(void) + clk_enable(tcu->clk); + } + +-static struct syscore_ops __maybe_unused tcu_pm_ops = { ++static const struct syscore_ops __maybe_unused tcu_pm_ops = { + .suspend = tcu_pm_suspend, + .resume = tcu_pm_resume, + }; + ++static struct syscore __maybe_unused tcu_pm = { ++ .ops = &tcu_pm_ops, ++}; ++ + static void __init ingenic_tcu_init(struct device_node *np) + { + int ret = ingenic_tcu_probe(np); +@@ -486,7 +490,7 @@ static void __init ingenic_tcu_init(struct device_node *np) + pr_crit("Failed to initialize TCU clocks: %d\n", ret); + + if (IS_ENABLED(CONFIG_PM_SLEEP)) +- register_syscore_ops(&tcu_pm_ops); ++ register_syscore(&tcu_pm); + } + + CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init); +diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c +index d80886caf393..d89bdfb7c219 100644 +--- a/drivers/clk/ingenic/x1000-cgu.c ++++ b/drivers/clk/ingenic/x1000-cgu.c +@@ -556,7 +556,7 @@ static void __init x1000_cgu_init(struct device_node *np) + return; + } + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + /* + * CGU has some children devices, this is useful for probing children devices +diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c +index 0fd46e50a513..acf856e5009e 100644 +--- a/drivers/clk/ingenic/x1830-cgu.c ++++ b/drivers/clk/ingenic/x1830-cgu.c +@@ -463,7 +463,7 @@ static void __init x1830_cgu_init(struct device_node *np) + return; + } + +- ingenic_cgu_register_syscore_ops(cgu); ++ ingenic_cgu_register_syscore(cgu); + } + /* + * CGU has some children devices, this is useful for probing children devices +diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c +index 785dbede4835..5adbbd91a6db 100644 +--- a/drivers/clk/mvebu/common.c ++++ b/drivers/clk/mvebu/common.c +@@ -215,22 +215,26 @@ static struct clk *clk_gating_get_src( + return ERR_PTR(-ENODEV); + } + +-static int mvebu_clk_gating_suspend(void) ++static int mvebu_clk_gating_suspend(void *data) + { + ctrl->saved_reg = readl(ctrl->base); + return 0; + } + +-static void mvebu_clk_gating_resume(void) ++static void mvebu_clk_gating_resume(void *data) + { + writel(ctrl->saved_reg, ctrl->base); + } + +-static struct syscore_ops clk_gate_syscore_ops = { ++static const struct syscore_ops clk_gate_syscore_ops = { + .suspend = mvebu_clk_gating_suspend, + .resume = mvebu_clk_gating_resume, + }; + ++static struct syscore clk_gate_syscore = { ++ .ops = &clk_gate_syscore_ops, ++}; ++ + void __init mvebu_clk_gating_setup(struct device_node *np, + const struct clk_gating_soc_desc *desc) + { +@@ -284,7 +288,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, + + of_clk_add_provider(np, clk_gating_get_src, ctrl); + +- register_syscore_ops(&clk_gate_syscore_ops); ++ register_syscore(&clk_gate_syscore); + + return; + gates_out: +diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c +index 0a1e017df7c6..9cf3e1e43b78 100644 +--- a/drivers/clk/rockchip/clk-rk3288.c ++++ b/drivers/clk/rockchip/clk-rk3288.c +@@ -871,7 +871,7 @@ static const int rk3288_saved_cru_reg_ids[] = { + + static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)]; + +-static int rk3288_clk_suspend(void) ++static int rk3288_clk_suspend(void *data) + { + int i, reg_id; + +@@ -906,7 +906,7 @@ static int rk3288_clk_suspend(void) + return 0; + } + +-static void rk3288_clk_resume(void) ++static void rk3288_clk_resume(void *data) + { + int i, reg_id; + +@@ -923,11 +923,15 @@ static void rk3288_clk_shutdown(void) + writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON); + } + +-static struct syscore_ops rk3288_clk_syscore_ops = { ++static const struct syscore_ops rk3288_clk_syscore_ops = { + .suspend = rk3288_clk_suspend, + .resume = rk3288_clk_resume, + }; + ++static struct syscore rk3288_clk_syscore = { ++ .ops = &rk3288_clk_syscore_ops, ++}; ++ + static void __init rk3288_common_init(struct device_node *np, + enum rk3288_variant soc) + { +@@ -976,7 +980,7 @@ static void __init rk3288_common_init(struct device_node *np, + + rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST, + rk3288_clk_shutdown); +- register_syscore_ops(&rk3288_clk_syscore_ops); ++ register_syscore(&rk3288_clk_syscore); + + rockchip_clk_of_add_provider(np, ctx); + } +diff --git a/drivers/clk/samsung/clk-s5pv210-audss.c b/drivers/clk/samsung/clk-s5pv210-audss.c +index b1fd8fac3a4c..c9fcb23de183 100644 +--- a/drivers/clk/samsung/clk-s5pv210-audss.c ++++ b/drivers/clk/samsung/clk-s5pv210-audss.c +@@ -36,7 +36,7 @@ static unsigned long reg_save[][2] = { + {ASS_CLK_GATE, 0}, + }; + +-static int s5pv210_audss_clk_suspend(void) ++static int s5pv210_audss_clk_suspend(void *data) + { + int i; + +@@ -46,7 +46,7 @@ static int s5pv210_audss_clk_suspend(void) + return 0; + } + +-static void s5pv210_audss_clk_resume(void) ++static void s5pv210_audss_clk_resume(void *data) + { + int i; + +@@ -54,10 +54,14 @@ static void s5pv210_audss_clk_resume(void) + writel(reg_save[i][1], reg_base + reg_save[i][0]); + } + +-static struct syscore_ops s5pv210_audss_clk_syscore_ops = { ++static const struct syscore_ops s5pv210_audss_clk_syscore_ops = { + .suspend = s5pv210_audss_clk_suspend, + .resume = s5pv210_audss_clk_resume, + }; ++ ++static struct syscore s5pv210_audss_clk_syscore = { ++ .ops = &s5pv210_audss_clk_syscore_ops, ++}; + #endif /* CONFIG_PM_SLEEP */ + + /* register s5pv210_audss clocks */ +@@ -175,7 +179,7 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev) + } + + #ifdef CONFIG_PM_SLEEP +- register_syscore_ops(&s5pv210_audss_clk_syscore_ops); ++ register_syscore(&s5pv210_audss_clk_syscore); + #endif + + return 0; +diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c +index dbc9925ca8f4..c149ca6c2217 100644 +--- a/drivers/clk/samsung/clk.c ++++ b/drivers/clk/samsung/clk.c +@@ -271,7 +271,7 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, + } + + #ifdef CONFIG_PM_SLEEP +-static int samsung_clk_suspend(void) ++static int samsung_clk_suspend(void *data) + { + struct samsung_clock_reg_cache *reg_cache; + +@@ -284,7 +284,7 @@ static int samsung_clk_suspend(void) + return 0; + } + +-static void samsung_clk_resume(void) ++static void samsung_clk_resume(void *data) + { + struct samsung_clock_reg_cache *reg_cache; + +@@ -293,11 +293,15 @@ static void samsung_clk_resume(void) + reg_cache->rd_num); + } + +-static struct syscore_ops samsung_clk_syscore_ops = { ++static const struct syscore_ops samsung_clk_syscore_ops = { + .suspend = samsung_clk_suspend, + .resume = samsung_clk_resume, + }; + ++static struct syscore samsung_clk_syscore = { ++ .ops = &samsung_clk_syscore_ops, ++}; ++ + void samsung_clk_extended_sleep_init(void __iomem *reg_base, + const unsigned long *rdump, + unsigned long nr_rdump, +@@ -316,7 +320,7 @@ void samsung_clk_extended_sleep_init(void __iomem *reg_base, + panic("could not allocate register dump storage.\n"); + + if (list_empty(&clock_reg_cache_list)) +- register_syscore_ops(&samsung_clk_syscore_ops); ++ register_syscore(&samsung_clk_syscore); + + reg_cache->reg_base = reg_base; + reg_cache->rd_num = nr_rdump; +diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c +index 412902f573b5..504d0ea997a5 100644 +--- a/drivers/clk/tegra/clk-tegra210.c ++++ b/drivers/clk/tegra/clk-tegra210.c +@@ -3444,7 +3444,7 @@ static void tegra210_disable_cpu_clock(u32 cpu) + static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx; + static u32 cpu_softrst_ctx[3]; + +-static int tegra210_clk_suspend(void) ++static int tegra210_clk_suspend(void *data) + { + unsigned int i; + +@@ -3465,7 +3465,7 @@ static int tegra210_clk_suspend(void) + return 0; + } + +-static void tegra210_clk_resume(void) ++static void tegra210_clk_resume(void *data) + { + unsigned int i; + +@@ -3523,13 +3523,17 @@ static void tegra210_cpu_clock_resume(void) + } + #endif + +-static struct syscore_ops tegra_clk_syscore_ops = { ++static const struct syscore_ops tegra_clk_syscore_ops = { + #ifdef CONFIG_PM_SLEEP + .suspend = tegra210_clk_suspend, + .resume = tegra210_clk_resume, + #endif + }; + ++static struct syscore tegra_clk_syscore = { ++ .ops = &tegra_clk_syscore_ops, ++}; ++ + static struct tegra_cpu_car_ops tegra210_cpu_car_ops = { + .wait_for_reset = tegra210_wait_cpu_in_reset, + .disable_clock = tegra210_disable_cpu_clock, +@@ -3813,6 +3817,6 @@ static void __init tegra210_clock_init(struct device_node *np) + + tegra_cpu_car_ops = &tegra210_cpu_car_ops; + +- register_syscore_ops(&tegra_clk_syscore_ops); ++ register_syscore(&tegra_clk_syscore); + } + CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); +diff --git a/drivers/clocksource/timer-armada-370-xp.c b/drivers/clocksource/timer-armada-370-xp.c +index 54284c1c0651..f2b4cc40db93 100644 +--- a/drivers/clocksource/timer-armada-370-xp.c ++++ b/drivers/clocksource/timer-armada-370-xp.c +@@ -207,14 +207,14 @@ static int armada_370_xp_timer_dying_cpu(unsigned int cpu) + + static u32 timer0_ctrl_reg, timer0_local_ctrl_reg; + +-static int armada_370_xp_timer_suspend(void) ++static int armada_370_xp_timer_suspend(void *data) + { + timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF); + timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF); + return 0; + } + +-static void armada_370_xp_timer_resume(void) ++static void armada_370_xp_timer_resume(void *data) + { + writel(0xffffffff, timer_base + TIMER0_VAL_OFF); + writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); +@@ -222,11 +222,15 @@ static void armada_370_xp_timer_resume(void) + writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF); + } + +-static struct syscore_ops armada_370_xp_timer_syscore_ops = { ++static const struct syscore_ops armada_370_xp_timer_syscore_ops = { + .suspend = armada_370_xp_timer_suspend, + .resume = armada_370_xp_timer_resume, + }; + ++static struct syscore armada_370_xp_timer_syscore = { ++ .ops = &armada_370_xp_timer_syscore_ops, ++}; ++ + static unsigned long armada_370_delay_timer_read(void) + { + return ~readl(timer_base + TIMER0_VAL_OFF); +@@ -324,7 +328,7 @@ static int __init armada_370_xp_timer_common_init(struct device_node *np) + return res; + } + +- register_syscore_ops(&armada_370_xp_timer_syscore_ops); ++ register_syscore(&armada_370_xp_timer_syscore); + + return 0; + } +diff --git a/drivers/cpuidle/cpuidle-psci.c b/drivers/cpuidle/cpuidle-psci.c +index b19bc60cc627..3372e1f90561 100644 +--- a/drivers/cpuidle/cpuidle-psci.c ++++ b/drivers/cpuidle/cpuidle-psci.c +@@ -177,26 +177,30 @@ static void psci_idle_syscore_switch(bool suspend) + } + } + +-static int psci_idle_syscore_suspend(void) ++static int psci_idle_syscore_suspend(void *data) + { + psci_idle_syscore_switch(true); + return 0; + } + +-static void psci_idle_syscore_resume(void) ++static void psci_idle_syscore_resume(void *data) + { + psci_idle_syscore_switch(false); + } + +-static struct syscore_ops psci_idle_syscore_ops = { ++static const struct syscore_ops psci_idle_syscore_ops = { + .suspend = psci_idle_syscore_suspend, + .resume = psci_idle_syscore_resume, + }; + ++static struct syscore psci_idle_syscore = { ++ .ops = &psci_idle_syscore_ops, ++}; ++ + static void psci_idle_init_syscore(void) + { + if (psci_cpuidle_use_syscore) +- register_syscore_ops(&psci_idle_syscore_ops); ++ register_syscore(&psci_idle_syscore); + } + + static void psci_idle_init_cpuhp(void) +diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c +index 441ba95b38cf..647b6f4861b7 100644 +--- a/drivers/gpio/gpio-mxc.c ++++ b/drivers/gpio/gpio-mxc.c +@@ -675,7 +675,7 @@ static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { + RUNTIME_PM_OPS(mxc_gpio_runtime_suspend, mxc_gpio_runtime_resume, NULL) + }; + +-static int mxc_gpio_syscore_suspend(void) ++static int mxc_gpio_syscore_suspend(void *data) + { + struct mxc_gpio_port *port; + int ret; +@@ -692,7 +692,7 @@ static int mxc_gpio_syscore_suspend(void) + return 0; + } + +-static void mxc_gpio_syscore_resume(void) ++static void mxc_gpio_syscore_resume(void *data) + { + struct mxc_gpio_port *port; + int ret; +@@ -709,11 +709,15 @@ static void mxc_gpio_syscore_resume(void) + } + } + +-static struct syscore_ops mxc_gpio_syscore_ops = { ++static const struct syscore_ops mxc_gpio_syscore_ops = { + .suspend = mxc_gpio_syscore_suspend, + .resume = mxc_gpio_syscore_resume, + }; + ++static struct syscore mxc_gpio_syscore = { ++ .ops = &mxc_gpio_syscore_ops, ++}; ++ + static struct platform_driver mxc_gpio_driver = { + .driver = { + .name = "gpio-mxc", +@@ -726,7 +730,7 @@ static struct platform_driver mxc_gpio_driver = { + + static int __init gpio_mxc_init(void) + { +- register_syscore_ops(&mxc_gpio_syscore_ops); ++ register_syscore(&mxc_gpio_syscore); + + return platform_driver_register(&mxc_gpio_driver); + } +diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c +index fa22f3faa163..664cf1eef494 100644 +--- a/drivers/gpio/gpio-pxa.c ++++ b/drivers/gpio/gpio-pxa.c +@@ -747,7 +747,7 @@ static int __init pxa_gpio_dt_init(void) + device_initcall(pxa_gpio_dt_init); + + #ifdef CONFIG_PM +-static int pxa_gpio_suspend(void) ++static int pxa_gpio_suspend(void *data) + { + struct pxa_gpio_chip *pchip = pxa_gpio_chip; + struct pxa_gpio_bank *c; +@@ -768,7 +768,7 @@ static int pxa_gpio_suspend(void) + return 0; + } + +-static void pxa_gpio_resume(void) ++static void pxa_gpio_resume(void *data) + { + struct pxa_gpio_chip *pchip = pxa_gpio_chip; + struct pxa_gpio_bank *c; +@@ -792,14 +792,18 @@ static void pxa_gpio_resume(void) + #define pxa_gpio_resume NULL + #endif + +-static struct syscore_ops pxa_gpio_syscore_ops = { ++static const struct syscore_ops pxa_gpio_syscore_ops = { + .suspend = pxa_gpio_suspend, + .resume = pxa_gpio_resume, + }; + ++static struct syscore pxa_gpio_syscore = { ++ .ops = &pxa_gpio_syscore_ops, ++}; ++ + static int __init pxa_gpio_sysinit(void) + { +- register_syscore_ops(&pxa_gpio_syscore_ops); ++ register_syscore(&pxa_gpio_syscore); + return 0; + } + postcore_initcall(pxa_gpio_sysinit); +diff --git a/drivers/gpio/gpio-sa1100.c b/drivers/gpio/gpio-sa1100.c +index 7f6a62f5d1ee..1938ffa2f4f3 100644 +--- a/drivers/gpio/gpio-sa1100.c ++++ b/drivers/gpio/gpio-sa1100.c +@@ -256,7 +256,7 @@ static void sa1100_gpio_handler(struct irq_desc *desc) + } while (mask); + } + +-static int sa1100_gpio_suspend(void) ++static int sa1100_gpio_suspend(void *data) + { + struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip; + +@@ -275,19 +275,23 @@ static int sa1100_gpio_suspend(void) + return 0; + } + +-static void sa1100_gpio_resume(void) ++static void sa1100_gpio_resume(void *data) + { + sa1100_update_edge_regs(&sa1100_gpio_chip); + } + +-static struct syscore_ops sa1100_gpio_syscore_ops = { ++static const struct syscore_ops sa1100_gpio_syscore_ops = { + .suspend = sa1100_gpio_suspend, + .resume = sa1100_gpio_resume, + }; + ++static struct syscore sa1100_gpio_syscore = { ++ .ops = &sa1100_gpio_syscore_ops, ++}; ++ + static int __init sa1100_gpio_init_devicefs(void) + { +- register_syscore_ops(&sa1100_gpio_syscore_ops); ++ register_syscore(&sa1100_gpio_syscore); + return 0; + } + +diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c +index 3ab62277b6be..7000e2a5511f 100644 +--- a/drivers/hv/vmbus_drv.c ++++ b/drivers/hv/vmbus_drv.c +@@ -2861,7 +2861,7 @@ static void hv_crash_handler(struct pt_regs *regs) + hv_synic_disable_regs(cpu); + }; + +-static int hv_synic_suspend(void) ++static int hv_synic_suspend(void *data) + { + /* + * When we reach here, all the non-boot CPUs have been offlined. +@@ -2888,7 +2888,7 @@ static int hv_synic_suspend(void) + return 0; + } + +-static void hv_synic_resume(void) ++static void hv_synic_resume(void *data) + { + hv_synic_enable_regs(0); + +@@ -2900,11 +2900,15 @@ static void hv_synic_resume(void) + } + + /* The callbacks run only on CPU0, with irqs_disabled. */ +-static struct syscore_ops hv_synic_syscore_ops = { ++static const struct syscore_ops hv_synic_syscore_ops = { + .suspend = hv_synic_suspend, + .resume = hv_synic_resume, + }; + ++static struct syscore hv_synic_syscore = { ++ .ops = &hv_synic_syscore_ops, ++}; ++ + static int __init hv_acpi_init(void) + { + int ret; +@@ -2947,7 +2951,7 @@ static int __init hv_acpi_init(void) + hv_setup_kexec_handler(hv_kexec_handler); + hv_setup_crash_handler(hv_crash_handler); + +- register_syscore_ops(&hv_synic_syscore_ops); ++ register_syscore(&hv_synic_syscore); + + return 0; + +@@ -2961,7 +2965,7 @@ static void __exit vmbus_exit(void) + { + int cpu; + +- unregister_syscore_ops(&hv_synic_syscore_ops); ++ unregister_syscore(&hv_synic_syscore); + + hv_remove_kexec_handler(); + hv_remove_crash_handler(); +diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c +index 76efd74124b3..4aa09660804b 100644 +--- a/drivers/iommu/amd/init.c ++++ b/drivers/iommu/amd/init.c +@@ -3050,7 +3050,7 @@ static void disable_iommus(void) + * disable suspend until real resume implemented + */ + +-static void amd_iommu_resume(void) ++static void amd_iommu_resume(void *data) + { + struct amd_iommu *iommu; + +@@ -3064,7 +3064,7 @@ static void amd_iommu_resume(void) + amd_iommu_enable_interrupts(); + } + +-static int amd_iommu_suspend(void) ++static int amd_iommu_suspend(void *data) + { + /* disable IOMMUs to go out of the way for BIOS */ + disable_iommus(); +@@ -3072,11 +3072,15 @@ static int amd_iommu_suspend(void) + return 0; + } + +-static struct syscore_ops amd_iommu_syscore_ops = { ++static const struct syscore_ops amd_iommu_syscore_ops = { + .suspend = amd_iommu_suspend, + .resume = amd_iommu_resume, + }; + ++static struct syscore amd_iommu_syscore = { ++ .ops = &amd_iommu_syscore_ops, ++}; ++ + static void __init free_iommu_resources(void) + { + free_iommu_all(); +@@ -3421,7 +3425,7 @@ static int __init state_next(void) + init_state = IOMMU_ENABLED; + break; + case IOMMU_ENABLED: +- register_syscore_ops(&amd_iommu_syscore_ops); ++ register_syscore(&amd_iommu_syscore); + iommu_snp_enable(); + ret = amd_iommu_init_pci(); + init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; +@@ -3524,12 +3528,12 @@ int __init amd_iommu_enable(void) + + void amd_iommu_disable(void) + { +- amd_iommu_suspend(); ++ amd_iommu_suspend(NULL); + } + + int amd_iommu_reenable(int mode) + { +- amd_iommu_resume(); ++ amd_iommu_resume(NULL); + + return 0; + } +diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c +index 79676188f60f..3d1cacad559b 100644 +--- a/drivers/iommu/intel/iommu.c ++++ b/drivers/iommu/intel/iommu.c +@@ -2305,7 +2305,7 @@ static void iommu_flush_all(void) + } + } + +-static int iommu_suspend(void) ++static int iommu_suspend(void *data) + { + struct dmar_drhd_unit *drhd; + struct intel_iommu *iommu = NULL; +@@ -2332,7 +2332,7 @@ static int iommu_suspend(void) + return 0; + } + +-static void iommu_resume(void) ++static void iommu_resume(void *data) + { + struct dmar_drhd_unit *drhd; + struct intel_iommu *iommu = NULL; +@@ -2363,14 +2363,18 @@ static void iommu_resume(void) + } + } + +-static struct syscore_ops iommu_syscore_ops = { ++static const struct syscore_ops iommu_syscore_ops = { + .resume = iommu_resume, + .suspend = iommu_suspend, + }; + ++static struct syscore iommu_syscore = { ++ .ops = &iommu_syscore_ops, ++}; ++ + static void __init init_iommu_pm_ops(void) + { +- register_syscore_ops(&iommu_syscore_ops); ++ register_syscore(&iommu_syscore); + } + + #else +diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c +index e7dfcf0cda43..495848442b35 100644 +--- a/drivers/irqchip/exynos-combiner.c ++++ b/drivers/irqchip/exynos-combiner.c +@@ -200,12 +200,13 @@ static void __init combiner_init(void __iomem *combiner_base, + + /** + * combiner_suspend - save interrupt combiner state before suspend ++ * @data: syscore context + * + * Save the interrupt enable set register for all combiner groups since + * the state is lost when the system enters into a sleep state. + * + */ +-static int combiner_suspend(void) ++static int combiner_suspend(void *data) + { + int i; + +@@ -218,12 +219,13 @@ static int combiner_suspend(void) + + /** + * combiner_resume - restore interrupt combiner state after resume ++ * @data: syscore context + * + * Restore the interrupt enable set register for all combiner groups since + * the state is lost when the system enters into a sleep state on suspend. + * + */ +-static void combiner_resume(void) ++static void combiner_resume(void *data) + { + int i; + +@@ -240,11 +242,15 @@ static void combiner_resume(void) + #define combiner_resume NULL + #endif + +-static struct syscore_ops combiner_syscore_ops = { ++static const struct syscore_ops combiner_syscore_ops = { + .suspend = combiner_suspend, + .resume = combiner_resume, + }; + ++static struct syscore combiner_syscore = { ++ .ops = &combiner_syscore_ops, ++}; ++ + static int __init combiner_of_init(struct device_node *np, + struct device_node *parent) + { +@@ -264,7 +270,7 @@ static int __init combiner_of_init(struct device_node *np, + + combiner_init(combiner_base, np); + +- register_syscore_ops(&combiner_syscore_ops); ++ register_syscore(&combiner_syscore); + + return 0; + } +diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c +index a44c49e985b7..a4d03a2d1569 100644 +--- a/drivers/irqchip/irq-armada-370-xp.c ++++ b/drivers/irqchip/irq-armada-370-xp.c +@@ -726,7 +726,7 @@ static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs) + } while (1); + } + +-static int mpic_suspend(void) ++static int mpic_suspend(void *data) + { + struct mpic *mpic = mpic_data; + +@@ -735,7 +735,7 @@ static int mpic_suspend(void) + return 0; + } + +-static void mpic_resume(void) ++static void mpic_resume(void *data) + { + struct mpic *mpic = mpic_data; + bool src0, src1; +@@ -788,11 +788,15 @@ static void mpic_resume(void) + mpic_ipi_resume(mpic); + } + +-static struct syscore_ops mpic_syscore_ops = { ++static const struct syscore_ops mpic_syscore_ops = { + .suspend = mpic_suspend, + .resume = mpic_resume, + }; + ++static struct syscore mpic_syscore = { ++ .ops = &mpic_syscore_ops, ++}; ++ + static int __init mpic_map_region(struct device_node *np, int index, + void __iomem **base, phys_addr_t *phys_base) + { +@@ -905,7 +909,7 @@ static int __init mpic_of_init(struct device_node *node, struct device_node *par + mpic_handle_cascade_irq, mpic); + } + +- register_syscore_ops(&mpic_syscore_ops); ++ register_syscore(&mpic_syscore); + + return 0; + } +diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c +index 821b288587ca..674138668f1c 100644 +--- a/drivers/irqchip/irq-bcm7038-l1.c ++++ b/drivers/irqchip/irq-bcm7038-l1.c +@@ -291,7 +291,7 @@ static int bcm7038_l1_init_one(struct device_node *dn, unsigned int idx, + static LIST_HEAD(bcm7038_l1_intcs_list); + static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock); + +-static int bcm7038_l1_suspend(void) ++static int bcm7038_l1_suspend(void *data) + { + struct bcm7038_l1_chip *intc; + int boot_cpu, word; +@@ -317,7 +317,7 @@ static int bcm7038_l1_suspend(void) + return 0; + } + +-static void bcm7038_l1_resume(void) ++static void bcm7038_l1_resume(void *data) + { + struct bcm7038_l1_chip *intc; + int boot_cpu, word; +@@ -338,11 +338,15 @@ static void bcm7038_l1_resume(void) + } + } + +-static struct syscore_ops bcm7038_l1_syscore_ops = { ++static const struct syscore_ops bcm7038_l1_syscore_ops = { + .suspend = bcm7038_l1_suspend, + .resume = bcm7038_l1_resume, + }; + ++static struct syscore bcm7038_l1_syscore = { ++ .ops = &bcm7038_l1_syscore_ops, ++}; ++ + static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on) + { + struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); +@@ -430,7 +434,7 @@ static int bcm7038_l1_probe(struct platform_device *pdev, struct device_node *pa + raw_spin_unlock(&bcm7038_l1_intcs_lock); + + if (list_is_singular(&bcm7038_l1_intcs_list)) +- register_syscore_ops(&bcm7038_l1_syscore_ops); ++ register_syscore(&bcm7038_l1_syscore); + #endif + + pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n", +diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c +index 23158fc8d392..a51e8e6a8181 100644 +--- a/drivers/irqchip/irq-gic-v3-its.c ++++ b/drivers/irqchip/irq-gic-v3-its.c +@@ -4996,7 +4996,7 @@ static void its_enable_quirks(struct its_node *its) + its_quirks, its); + } + +-static int its_save_disable(void) ++static int its_save_disable(void *data) + { + struct its_node *its; + int err = 0; +@@ -5032,7 +5032,7 @@ static int its_save_disable(void) + return err; + } + +-static void its_restore_enable(void) ++static void its_restore_enable(void *data) + { + struct its_node *its; + int ret; +@@ -5092,11 +5092,15 @@ static void its_restore_enable(void) + raw_spin_unlock(&its_lock); + } + +-static struct syscore_ops its_syscore_ops = { ++static const struct syscore_ops its_syscore_ops = { + .suspend = its_save_disable, + .resume = its_restore_enable, + }; + ++static struct syscore its_syscore = { ++ .ops = &its_syscore_ops, ++}; ++ + static void __init __iomem *its_map_one(struct resource *res, int *err) + { + void __iomem *its_base; +@@ -5868,7 +5872,7 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, + } + } + +- register_syscore_ops(&its_syscore_ops); ++ register_syscore(&its_syscore); + + return 0; + } +diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c +index 91b2f587119c..cca77f9948a3 100644 +--- a/drivers/irqchip/irq-i8259.c ++++ b/drivers/irqchip/irq-i8259.c +@@ -202,13 +202,13 @@ static void mask_and_ack_8259A(struct irq_data *d) + } + } + +-static void i8259A_resume(void) ++static void i8259A_resume(void *data) + { + if (i8259A_auto_eoi >= 0) + init_8259A(i8259A_auto_eoi); + } + +-static void i8259A_shutdown(void) ++static void i8259A_shutdown(void *data) + { + /* Put the i8259A into a quiescent state that + * the kernel initialization code can get it +@@ -220,11 +220,15 @@ static void i8259A_shutdown(void) + } + } + +-static struct syscore_ops i8259_syscore_ops = { ++static const struct syscore_ops i8259_syscore_ops = { + .resume = i8259A_resume, + .shutdown = i8259A_shutdown, + }; + ++static struct syscore i8259_syscore = { ++ .ops = &i8259_syscore_ops, ++}; ++ + static void init_8259A(int auto_eoi) + { + unsigned long flags; +@@ -320,7 +324,7 @@ struct irq_domain * __init __init_i8259_irqs(struct device_node *node) + + if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL)) + pr_err("Failed to register cascade interrupt\n"); +- register_syscore_ops(&i8259_syscore_ops); ++ register_syscore(&i8259_syscore); + return domain; + } + +diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c +index b91f5c14b405..04f7ba0657be 100644 +--- a/drivers/irqchip/irq-imx-gpcv2.c ++++ b/drivers/irqchip/irq-imx-gpcv2.c +@@ -33,7 +33,7 @@ static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i) + return cd->gpc_base + cd->cpu2wakeup + i * 4; + } + +-static int gpcv2_wakeup_source_save(void) ++static int gpcv2_wakeup_source_save(void *data) + { + struct gpcv2_irqchip_data *cd; + void __iomem *reg; +@@ -52,7 +52,7 @@ static int gpcv2_wakeup_source_save(void) + return 0; + } + +-static void gpcv2_wakeup_source_restore(void) ++static void gpcv2_wakeup_source_restore(void *data) + { + struct gpcv2_irqchip_data *cd; + int i; +@@ -65,9 +65,13 @@ static void gpcv2_wakeup_source_restore(void) + writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i)); + } + +-static struct syscore_ops imx_gpcv2_syscore_ops = { +- .suspend = gpcv2_wakeup_source_save, +- .resume = gpcv2_wakeup_source_restore, ++static const struct syscore_ops gpcv2_syscore_ops = { ++ .suspend = gpcv2_wakeup_source_save, ++ .resume = gpcv2_wakeup_source_restore, ++}; ++ ++static struct syscore gpcv2_syscore = { ++ .ops = &gpcv2_syscore_ops, + }; + + static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) +@@ -276,7 +280,7 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node, + writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup); + + imx_gpcv2_instance = cd; +- register_syscore_ops(&imx_gpcv2_syscore_ops); ++ register_syscore(&gpcv2_syscore); + + /* + * Clear the OF_POPULATED flag set in of_irq_init so that +diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c +index 39e5a72ccd3c..ad2105685b48 100644 +--- a/drivers/irqchip/irq-loongson-eiointc.c ++++ b/drivers/irqchip/irq-loongson-eiointc.c +@@ -407,21 +407,25 @@ static struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group + return NULL; + } + +-static int eiointc_suspend(void) ++static int eiointc_suspend(void *data) + { + return 0; + } + +-static void eiointc_resume(void) ++static void eiointc_resume(void *data) + { + eiointc_router_init(0); + } + +-static struct syscore_ops eiointc_syscore_ops = { ++static const struct syscore_ops eiointc_syscore_ops = { + .suspend = eiointc_suspend, + .resume = eiointc_resume, + }; + ++static struct syscore eiointc_syscore = { ++ .ops = &eiointc_syscore_ops, ++}; ++ + static int __init pch_pic_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) + { +@@ -540,7 +544,7 @@ static int __init eiointc_init(struct eiointc_priv *priv, int parent_irq, + eiointc_router_init(0); + + if (nr_pics == 1) { +- register_syscore_ops(&eiointc_syscore_ops); ++ register_syscore(&eiointc_syscore); + cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_EIOINTC_STARTING, + "irqchip/loongarch/eiointc:starting", + eiointc_router_init, NULL); +diff --git a/drivers/irqchip/irq-loongson-htpic.c b/drivers/irqchip/irq-loongson-htpic.c +index f4abdf156de7..1c691c4be989 100644 +--- a/drivers/irqchip/irq-loongson-htpic.c ++++ b/drivers/irqchip/irq-loongson-htpic.c +@@ -71,15 +71,19 @@ static void htpic_reg_init(void) + writel(0xffff, htpic->base + HTINT_EN_OFF); + } + +-static void htpic_resume(void) ++static void htpic_resume(void *data) + { + htpic_reg_init(); + } + +-struct syscore_ops htpic_syscore_ops = { ++static const struct syscore_ops htpic_syscore_ops = { + .resume = htpic_resume, + }; + ++static struct syscore htpic_syscore = { ++ .ops = &htpic_syscore_ops, ++}; ++ + static int __init htpic_of_init(struct device_node *node, struct device_node *parent) + { + unsigned int parent_irq[4]; +@@ -130,7 +134,7 @@ static int __init htpic_of_init(struct device_node *node, struct device_node *pa + htpic_irq_dispatch, htpic); + } + +- register_syscore_ops(&htpic_syscore_ops); ++ register_syscore(&htpic_syscore); + + return 0; + +diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c +index d8558eb35044..d2be8e954e92 100644 +--- a/drivers/irqchip/irq-loongson-htvec.c ++++ b/drivers/irqchip/irq-loongson-htvec.c +@@ -159,7 +159,7 @@ static void htvec_reset(struct htvec *priv) + } + } + +-static int htvec_suspend(void) ++static int htvec_suspend(void *data) + { + int i; + +@@ -169,7 +169,7 @@ static int htvec_suspend(void) + return 0; + } + +-static void htvec_resume(void) ++static void htvec_resume(void *data) + { + int i; + +@@ -177,11 +177,15 @@ static void htvec_resume(void) + writel(htvec_priv->saved_vec_en[i], htvec_priv->base + HTVEC_EN_OFF + 4 * i); + } + +-static struct syscore_ops htvec_syscore_ops = { ++static const struct syscore_ops htvec_syscore_ops = { + .suspend = htvec_suspend, + .resume = htvec_resume, + }; + ++static struct syscore htvec_syscore = { ++ .ops = &htvec_syscore_ops, ++}; ++ + static int htvec_init(phys_addr_t addr, unsigned long size, + int num_parents, int parent_irq[], struct fwnode_handle *domain_handle) + { +@@ -214,7 +218,7 @@ static int htvec_init(phys_addr_t addr, unsigned long size, + + htvec_priv = priv; + +- register_syscore_ops(&htvec_syscore_ops); ++ register_syscore(&htvec_syscore); + + return 0; + +diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c +index 912bf50a5c7c..3a125f3e4287 100644 +--- a/drivers/irqchip/irq-loongson-pch-lpc.c ++++ b/drivers/irqchip/irq-loongson-pch-lpc.c +@@ -151,7 +151,7 @@ static int pch_lpc_disabled(struct pch_lpc *priv) + (readl(priv->base + LPC_INT_STS) == 0xffffffff); + } + +-static int pch_lpc_suspend(void) ++static int pch_lpc_suspend(void *data) + { + pch_lpc_priv->saved_reg_ctl = readl(pch_lpc_priv->base + LPC_INT_CTL); + pch_lpc_priv->saved_reg_ena = readl(pch_lpc_priv->base + LPC_INT_ENA); +@@ -159,18 +159,22 @@ static int pch_lpc_suspend(void) + return 0; + } + +-static void pch_lpc_resume(void) ++static void pch_lpc_resume(void *data) + { + writel(pch_lpc_priv->saved_reg_ctl, pch_lpc_priv->base + LPC_INT_CTL); + writel(pch_lpc_priv->saved_reg_ena, pch_lpc_priv->base + LPC_INT_ENA); + writel(pch_lpc_priv->saved_reg_pol, pch_lpc_priv->base + LPC_INT_POL); + } + +-static struct syscore_ops pch_lpc_syscore_ops = { ++static const struct syscore_ops pch_lpc_syscore_ops = { + .suspend = pch_lpc_suspend, + .resume = pch_lpc_resume, + }; + ++static struct syscore pch_lpc_syscore = { ++ .ops = &pch_lpc_syscore_ops, ++}; ++ + int __init pch_lpc_acpi_init(struct irq_domain *parent, + struct acpi_madt_lpc_pic *acpi_pchlpc) + { +@@ -222,7 +226,7 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, + + pch_lpc_priv = priv; + pch_lpc_handle = irq_handle; +- register_syscore_ops(&pch_lpc_syscore_ops); ++ register_syscore(&pch_lpc_syscore); + + return 0; + +diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c +index 62e6bf3a0611..c6b369a974a7 100644 +--- a/drivers/irqchip/irq-loongson-pch-pic.c ++++ b/drivers/irqchip/irq-loongson-pch-pic.c +@@ -278,7 +278,7 @@ static void pch_pic_reset(struct pch_pic *priv) + } + } + +-static int pch_pic_suspend(void) ++static int pch_pic_suspend(void *data) + { + int i, j; + +@@ -296,7 +296,7 @@ static int pch_pic_suspend(void) + return 0; + } + +-static void pch_pic_resume(void) ++static void pch_pic_resume(void *data) + { + int i, j; + +@@ -313,11 +313,15 @@ static void pch_pic_resume(void) + } + } + +-static struct syscore_ops pch_pic_syscore_ops = { ++static const struct syscore_ops pch_pic_syscore_ops = { + .suspend = pch_pic_suspend, + .resume = pch_pic_resume, + }; + ++static struct syscore pch_pic_syscore = { ++ .ops = &pch_pic_syscore_ops, ++}; ++ + static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base, + struct irq_domain *parent_domain, struct fwnode_handle *domain_handle, + u32 gsi_base) +@@ -356,7 +360,7 @@ static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base, + pch_pic_priv[nr_pics++] = priv; + + if (nr_pics == 1) +- register_syscore_ops(&pch_pic_syscore_ops); ++ register_syscore(&pch_pic_syscore); + + return 0; + +diff --git a/drivers/irqchip/irq-mchp-eic.c b/drivers/irqchip/irq-mchp-eic.c +index 979bb86929f8..31093a8ab67c 100644 +--- a/drivers/irqchip/irq-mchp-eic.c ++++ b/drivers/irqchip/irq-mchp-eic.c +@@ -109,7 +109,7 @@ static int mchp_eic_irq_set_wake(struct irq_data *d, unsigned int on) + return 0; + } + +-static int mchp_eic_irq_suspend(void) ++static int mchp_eic_irq_suspend(void *data) + { + unsigned int hwirq; + +@@ -123,7 +123,7 @@ static int mchp_eic_irq_suspend(void) + return 0; + } + +-static void mchp_eic_irq_resume(void) ++static void mchp_eic_irq_resume(void *data) + { + unsigned int hwirq; + +@@ -135,11 +135,15 @@ static void mchp_eic_irq_resume(void) + MCHP_EIC_SCFG(hwirq)); + } + +-static struct syscore_ops mchp_eic_syscore_ops = { ++static const struct syscore_ops mchp_eic_syscore_ops = { + .suspend = mchp_eic_irq_suspend, + .resume = mchp_eic_irq_resume, + }; + ++static struct syscore mchp_eic_syscore = { ++ .ops = &mchp_eic_syscore_ops, ++}; ++ + static struct irq_chip mchp_eic_chip = { + .name = "eic", + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED, +@@ -258,7 +262,7 @@ static int mchp_eic_probe(struct platform_device *pdev, struct device_node *pare + goto clk_unprepare; + } + +- register_syscore_ops(&mchp_eic_syscore_ops); ++ register_syscore(&mchp_eic_syscore); + + pr_info("%pOF: EIC registered, nr_irqs %u\n", node, MCHP_EIC_NIRQ); + +diff --git a/drivers/irqchip/irq-mst-intc.c b/drivers/irqchip/irq-mst-intc.c +index 9643cc3a77d7..7f760f555a76 100644 +--- a/drivers/irqchip/irq-mst-intc.c ++++ b/drivers/irqchip/irq-mst-intc.c +@@ -143,7 +143,7 @@ static void mst_intc_polarity_restore(struct mst_intc_chip_data *cd) + writew_relaxed(cd->saved_polarity_conf[i], addr + i * 4); + } + +-static void mst_irq_resume(void) ++static void mst_irq_resume(void *data) + { + struct mst_intc_chip_data *cd; + +@@ -151,7 +151,7 @@ static void mst_irq_resume(void) + mst_intc_polarity_restore(cd); + } + +-static int mst_irq_suspend(void) ++static int mst_irq_suspend(void *data) + { + struct mst_intc_chip_data *cd; + +@@ -160,14 +160,18 @@ static int mst_irq_suspend(void) + return 0; + } + +-static struct syscore_ops mst_irq_syscore_ops = { ++static const struct syscore_ops mst_irq_syscore_ops = { + .suspend = mst_irq_suspend, + .resume = mst_irq_resume, + }; + ++static struct syscore mst_irq_syscore = { ++ .ops = &mst_irq_syscore_ops, ++}; ++ + static int __init mst_irq_pm_init(void) + { +- register_syscore_ops(&mst_irq_syscore_ops); ++ register_syscore(&mst_irq_syscore); + return 0; + } + late_initcall(mst_irq_pm_init); +diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c +index de481ba340f8..9571f622774e 100644 +--- a/drivers/irqchip/irq-mtk-cirq.c ++++ b/drivers/irqchip/irq-mtk-cirq.c +@@ -199,7 +199,7 @@ static const struct irq_domain_ops cirq_domain_ops = { + }; + + #ifdef CONFIG_PM_SLEEP +-static int mtk_cirq_suspend(void) ++static int mtk_cirq_suspend(void *data) + { + void __iomem *reg; + u32 value, mask; +@@ -257,7 +257,7 @@ static int mtk_cirq_suspend(void) + return 0; + } + +-static void mtk_cirq_resume(void) ++static void mtk_cirq_resume(void *data) + { + void __iomem *reg = mtk_cirq_reg(cirq_data, CIRQ_CONTROL); + u32 value; +@@ -272,14 +272,18 @@ static void mtk_cirq_resume(void) + writel_relaxed(value, reg); + } + +-static struct syscore_ops mtk_cirq_syscore_ops = { ++static const struct syscore_ops mtk_cirq_syscore_ops = { + .suspend = mtk_cirq_suspend, + .resume = mtk_cirq_resume, + }; + ++static struct syscore mtk_cirq_syscore = { ++ .ops = &mtk_cirq_syscore_ops, ++}; ++ + static void mtk_cirq_syscore_init(void) + { +- register_syscore_ops(&mtk_cirq_syscore_ops); ++ register_syscore(&mtk_cirq_syscore); + } + #else + static inline void mtk_cirq_syscore_init(void) {} +diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c +index c938ab159289..eb01d4c5aca7 100644 +--- a/drivers/irqchip/irq-renesas-rzg2l.c ++++ b/drivers/irqchip/irq-renesas-rzg2l.c +@@ -398,7 +398,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); + } + +-static int rzg2l_irqc_irq_suspend(void) ++static int rzg2l_irqc_irq_suspend(void *data) + { + struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; + void __iomem *base = rzg2l_irqc_data->base; +@@ -410,7 +410,7 @@ static int rzg2l_irqc_irq_suspend(void) + return 0; + } + +-static void rzg2l_irqc_irq_resume(void) ++static void rzg2l_irqc_irq_resume(void *data) + { + struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; + void __iomem *base = rzg2l_irqc_data->base; +@@ -425,11 +425,15 @@ static void rzg2l_irqc_irq_resume(void) + writel_relaxed(cache->iitsr, base + IITSR); + } + +-static struct syscore_ops rzg2l_irqc_syscore_ops = { ++static const struct syscore_ops rzg2l_irqc_syscore_ops = { + .suspend = rzg2l_irqc_irq_suspend, + .resume = rzg2l_irqc_irq_resume, + }; + ++static struct syscore rzg2l_irqc_syscore = { ++ .ops = &rzg2l_irqc_syscore_ops, ++}; ++ + static const struct irq_chip rzg2l_irqc_chip = { + .name = "rzg2l-irqc", + .irq_eoi = rzg2l_irqc_eoi, +@@ -577,7 +581,7 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n + return -ENOMEM; + } + +- register_syscore_ops(&rzg2l_irqc_syscore_ops); ++ register_syscore(&rzg2l_irqc_syscore); + + return 0; + } +diff --git a/drivers/irqchip/irq-sa11x0.c b/drivers/irqchip/irq-sa11x0.c +index d8d4dff16276..e5f24c5f3f41 100644 +--- a/drivers/irqchip/irq-sa11x0.c ++++ b/drivers/irqchip/irq-sa11x0.c +@@ -85,7 +85,7 @@ static struct sa1100irq_state { + unsigned int iccr; + } sa1100irq_state; + +-static int sa1100irq_suspend(void) ++static int sa1100irq_suspend(void *data) + { + struct sa1100irq_state *st = &sa1100irq_state; + +@@ -102,7 +102,7 @@ static int sa1100irq_suspend(void) + return 0; + } + +-static void sa1100irq_resume(void) ++static void sa1100irq_resume(void *data) + { + struct sa1100irq_state *st = &sa1100irq_state; + +@@ -114,14 +114,18 @@ static void sa1100irq_resume(void) + } + } + +-static struct syscore_ops sa1100irq_syscore_ops = { ++static const struct syscore_ops sa1100irq_syscore_ops = { + .suspend = sa1100irq_suspend, + .resume = sa1100irq_resume, + }; + ++static struct syscore sa1100irq_syscore = { ++ .ops = &sa1100irq_syscore_ops, ++}; ++ + static int __init sa1100irq_init_devicefs(void) + { +- register_syscore_ops(&sa1100irq_syscore_ops); ++ register_syscore(&sa1100irq_syscore); + return 0; + } + +diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c +index f255fa044764..70058871d2fb 100644 +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -268,7 +268,7 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type) + return IRQ_SET_MASK_OK; + } + +-static int plic_irq_suspend(void) ++static int plic_irq_suspend(void *data) + { + struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; + +@@ -280,7 +280,7 @@ static int plic_irq_suspend(void) + return 0; + } + +-static void plic_irq_resume(void) ++static void plic_irq_resume(void *data) + { + struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; + unsigned int index, cpu; +@@ -308,11 +308,15 @@ static void plic_irq_resume(void) + } + } + +-static struct syscore_ops plic_irq_syscore_ops = { ++static const struct syscore_ops plic_irq_syscore_ops = { + .suspend = plic_irq_suspend, + .resume = plic_irq_resume, + }; + ++static struct syscore plic_irq_syscore = { ++ .ops = &plic_irq_syscore_ops, ++}; ++ + static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) + { +@@ -782,7 +786,7 @@ static int plic_probe(struct fwnode_handle *fwnode) + cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, + "irqchip/sifive/plic:starting", + plic_starting_cpu, plic_dying_cpu); +- register_syscore_ops(&plic_irq_syscore_ops); ++ register_syscore(&plic_irq_syscore); + plic_global_setup_done = true; + } + } +diff --git a/drivers/irqchip/irq-sun6i-r.c b/drivers/irqchip/irq-sun6i-r.c +index 37d4b29763bc..23251831c06e 100644 +--- a/drivers/irqchip/irq-sun6i-r.c ++++ b/drivers/irqchip/irq-sun6i-r.c +@@ -268,7 +268,7 @@ static const struct irq_domain_ops sun6i_r_intc_domain_ops = { + .free = irq_domain_free_irqs_common, + }; + +-static int sun6i_r_intc_suspend(void) ++static int sun6i_r_intc_suspend(void *data) + { + u32 buf[BITS_TO_U32(MAX(SUN6I_NR_TOP_LEVEL_IRQS, SUN6I_NR_MUX_BITS))]; + int i; +@@ -284,7 +284,7 @@ static int sun6i_r_intc_suspend(void) + return 0; + } + +-static void sun6i_r_intc_resume(void) ++static void sun6i_r_intc_resume(void *data) + { + int i; + +@@ -294,17 +294,21 @@ static void sun6i_r_intc_resume(void) + writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i)); + } + +-static void sun6i_r_intc_shutdown(void) ++static void sun6i_r_intc_shutdown(void *data) + { +- sun6i_r_intc_suspend(); ++ sun6i_r_intc_suspend(data); + } + +-static struct syscore_ops sun6i_r_intc_syscore_ops = { ++static const struct syscore_ops sun6i_r_intc_syscore_ops = { + .suspend = sun6i_r_intc_suspend, + .resume = sun6i_r_intc_resume, + .shutdown = sun6i_r_intc_shutdown, + }; + ++static struct syscore sun6i_r_intc_syscore = { ++ .ops = &sun6i_r_intc_syscore_ops, ++}; ++ + static int __init sun6i_r_intc_init(struct device_node *node, + struct device_node *parent, + const struct sun6i_r_intc_variant *v) +@@ -346,10 +350,10 @@ static int __init sun6i_r_intc_init(struct device_node *node, + return -ENOMEM; + } + +- register_syscore_ops(&sun6i_r_intc_syscore_ops); ++ register_syscore(&sun6i_r_intc_syscore); + + sun6i_r_intc_ack_nmi(); +- sun6i_r_intc_resume(); ++ sun6i_r_intc_resume(NULL); + + return 0; + } +diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c +index 66cbb9f77ff3..b6382cf6359a 100644 +--- a/drivers/irqchip/irq-tegra.c ++++ b/drivers/irqchip/irq-tegra.c +@@ -132,7 +132,7 @@ static int tegra_set_wake(struct irq_data *d, unsigned int enable) + return 0; + } + +-static int tegra_ictlr_suspend(void) ++static int tegra_ictlr_suspend(void *data) + { + unsigned long flags; + unsigned int i; +@@ -161,7 +161,7 @@ static int tegra_ictlr_suspend(void) + return 0; + } + +-static void tegra_ictlr_resume(void) ++static void tegra_ictlr_resume(void *data) + { + unsigned long flags; + unsigned int i; +@@ -184,14 +184,18 @@ static void tegra_ictlr_resume(void) + local_irq_restore(flags); + } + +-static struct syscore_ops tegra_ictlr_syscore_ops = { ++static const struct syscore_ops tegra_ictlr_syscore_ops = { + .suspend = tegra_ictlr_suspend, + .resume = tegra_ictlr_resume, + }; + ++static struct syscore tegra_ictlr_syscore = { ++ .ops = &tegra_ictlr_syscore_ops, ++}; ++ + static void tegra_ictlr_syscore_init(void) + { +- register_syscore_ops(&tegra_ictlr_syscore_ops); ++ register_syscore(&tegra_ictlr_syscore); + } + #else + #define tegra_set_wake NULL +diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c +index 2bcdf216a000..e38104c5064e 100644 +--- a/drivers/irqchip/irq-vic.c ++++ b/drivers/irqchip/irq-vic.c +@@ -120,7 +120,7 @@ static void resume_one_vic(struct vic_device *vic) + writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); + } + +-static void vic_resume(void) ++static void vic_resume(void *data) + { + int id; + +@@ -146,7 +146,7 @@ static void suspend_one_vic(struct vic_device *vic) + writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); + } + +-static int vic_suspend(void) ++static int vic_suspend(void *data) + { + int id; + +@@ -156,11 +156,15 @@ static int vic_suspend(void) + return 0; + } + +-static struct syscore_ops vic_syscore_ops = { ++static const struct syscore_ops vic_syscore_ops = { + .suspend = vic_suspend, + .resume = vic_resume, + }; + ++static struct syscore vic_syscore = { ++ .ops = &vic_syscore_ops, ++}; ++ + /** + * vic_pm_init - initcall to register VIC pm + * +@@ -171,7 +175,7 @@ static struct syscore_ops vic_syscore_ops = { + static int __init vic_pm_init(void) + { + if (vic_id > 0) +- register_syscore_ops(&vic_syscore_ops); ++ register_syscore(&vic_syscore); + + return 0; + } +diff --git a/drivers/leds/trigger/ledtrig-cpu.c b/drivers/leds/trigger/ledtrig-cpu.c +index 05848a2fecff..679323c2ccda 100644 +--- a/drivers/leds/trigger/ledtrig-cpu.c ++++ b/drivers/leds/trigger/ledtrig-cpu.c +@@ -94,28 +94,32 @@ void ledtrig_cpu(enum cpu_led_event ledevt) + } + EXPORT_SYMBOL(ledtrig_cpu); + +-static int ledtrig_cpu_syscore_suspend(void) ++static int ledtrig_cpu_syscore_suspend(void *data) + { + ledtrig_cpu(CPU_LED_STOP); + return 0; + } + +-static void ledtrig_cpu_syscore_resume(void) ++static void ledtrig_cpu_syscore_resume(void *data) + { + ledtrig_cpu(CPU_LED_START); + } + +-static void ledtrig_cpu_syscore_shutdown(void) ++static void ledtrig_cpu_syscore_shutdown(void *data) + { + ledtrig_cpu(CPU_LED_HALTED); + } + +-static struct syscore_ops ledtrig_cpu_syscore_ops = { ++static const struct syscore_ops ledtrig_cpu_syscore_ops = { + .shutdown = ledtrig_cpu_syscore_shutdown, + .suspend = ledtrig_cpu_syscore_suspend, + .resume = ledtrig_cpu_syscore_resume, + }; + ++static struct syscore ledtrig_cpu_syscore = { ++ .ops = &ledtrig_cpu_syscore_ops, ++}; ++ + static int ledtrig_online_cpu(unsigned int cpu) + { + ledtrig_cpu(CPU_LED_START); +@@ -157,7 +161,7 @@ static int __init ledtrig_cpu_init(void) + led_trigger_register_simple(trig->name, &trig->_trig); + } + +- register_syscore_ops(&ledtrig_cpu_syscore_ops); ++ register_syscore(&ledtrig_cpu_syscore); + + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "leds/trigger:starting", + ledtrig_online_cpu, ledtrig_prepare_down_cpu); +diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c +index b0f09c70f1ff..5fe47e784d43 100644 +--- a/drivers/macintosh/via-pmu.c ++++ b/drivers/macintosh/via-pmu.c +@@ -2600,7 +2600,7 @@ void pmu_blink(int n) + #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC32) + int pmu_sys_suspended; + +-static int pmu_syscore_suspend(void) ++static int pmu_syscore_suspend(void *data) + { + /* Suspend PMU event interrupts */ + pmu_suspend(); +@@ -2614,7 +2614,7 @@ static int pmu_syscore_suspend(void) + return 0; + } + +-static void pmu_syscore_resume(void) ++static void pmu_syscore_resume(void *data) + { + struct adb_request req; + +@@ -2634,14 +2634,18 @@ static void pmu_syscore_resume(void) + pmu_sys_suspended = 0; + } + +-static struct syscore_ops pmu_syscore_ops = { ++static const struct syscore_ops pmu_syscore_ops = { + .suspend = pmu_syscore_suspend, + .resume = pmu_syscore_resume, + }; + ++static struct syscore pmu_syscore = { ++ .ops = &pmu_syscore_ops, ++}; ++ + static int pmu_syscore_register(void) + { +- register_syscore_ops(&pmu_syscore_ops); ++ register_syscore(&pmu_syscore); + + return 0; + } +diff --git a/drivers/power/reset/sc27xx-poweroff.c b/drivers/power/reset/sc27xx-poweroff.c +index 90287c31992c..393bd1c33b73 100644 +--- a/drivers/power/reset/sc27xx-poweroff.c ++++ b/drivers/power/reset/sc27xx-poweroff.c +@@ -28,7 +28,7 @@ static struct regmap *regmap; + * taking cpus down to avoid racing regmap or spi mutex lock when poweroff + * system through PMIC. + */ +-static void sc27xx_poweroff_shutdown(void) ++static void sc27xx_poweroff_shutdown(void *data) + { + #ifdef CONFIG_HOTPLUG_CPU + int cpu; +@@ -40,10 +40,14 @@ static void sc27xx_poweroff_shutdown(void) + #endif + } + +-static struct syscore_ops poweroff_syscore_ops = { ++static const struct syscore_ops poweroff_syscore_ops = { + .shutdown = sc27xx_poweroff_shutdown, + }; + ++static struct syscore poweroff_syscore = { ++ .ops = &poweroff_syscore_ops, ++}; ++ + static void sc27xx_poweroff_do_poweroff(void) + { + /* Disable the external subsys connection's power firstly */ +@@ -62,7 +66,7 @@ static int sc27xx_poweroff_probe(struct platform_device *pdev) + return -ENODEV; + + pm_power_off = sc27xx_poweroff_do_poweroff; +- register_syscore_ops(&poweroff_syscore_ops); ++ register_syscore(&poweroff_syscore); + return 0; + } + +diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c +index 7a73f5e4a1fc..f02e12dfa5f6 100644 +--- a/drivers/sh/clk/core.c ++++ b/drivers/sh/clk/core.c +@@ -569,7 +569,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) + EXPORT_SYMBOL_GPL(clk_round_rate); + + #ifdef CONFIG_PM +-static void clks_core_resume(void) ++static void clks_core_resume(void *data) + { + struct clk *clkp; + +@@ -588,13 +588,17 @@ static void clks_core_resume(void) + } + } + +-static struct syscore_ops clks_syscore_ops = { ++static const struct syscore_ops clks_syscore_ops = { + .resume = clks_core_resume, + }; + ++static struct syscore clks_syscore = { ++ .ops = &clks_syscore_ops, ++}; ++ + static int __init clk_syscore_init(void) + { +- register_syscore_ops(&clks_syscore_ops); ++ register_syscore(&clks_syscore); + + return 0; + } +diff --git a/drivers/sh/intc/core.c b/drivers/sh/intc/core.c +index ea571eeb3078..3dde703b7766 100644 +--- a/drivers/sh/intc/core.c ++++ b/drivers/sh/intc/core.c +@@ -394,7 +394,7 @@ int __init register_intc_controller(struct intc_desc *desc) + return -ENOMEM; + } + +-static int intc_suspend(void) ++static int intc_suspend(void *data) + { + struct intc_desc_int *d; + +@@ -420,7 +420,7 @@ static int intc_suspend(void) + return 0; + } + +-static void intc_resume(void) ++static void intc_resume(void *data) + { + struct intc_desc_int *d; + +@@ -450,11 +450,15 @@ static void intc_resume(void) + } + } + +-struct syscore_ops intc_syscore_ops = { ++static const struct syscore_ops intc_syscore_ops = { + .suspend = intc_suspend, + .resume = intc_resume, + }; + ++static struct syscore intc_syscore = { ++ .ops = &intc_syscore_ops, ++}; ++ + const struct bus_type intc_subsys = { + .name = "intc", + .dev_name = "intc", +@@ -477,7 +481,7 @@ static int __init register_intc_devs(void) + struct intc_desc_int *d; + int error; + +- register_syscore_ops(&intc_syscore_ops); ++ register_syscore(&intc_syscore); + + error = subsys_system_register(&intc_subsys, NULL); + if (!error) { +diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c +index 364ddbe365c2..bd830649b60d 100644 +--- a/drivers/soc/bcm/brcmstb/biuctrl.c ++++ b/drivers/soc/bcm/brcmstb/biuctrl.c +@@ -298,7 +298,7 @@ static int __init setup_hifcpubiuctrl_regs(struct device_node *np) + #ifdef CONFIG_PM_SLEEP + static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS]; + +-static int brcmstb_cpu_credit_reg_suspend(void) ++static int brcmstb_cpu_credit_reg_suspend(void *data) + { + unsigned int i; + +@@ -311,7 +311,7 @@ static int brcmstb_cpu_credit_reg_suspend(void) + return 0; + } + +-static void brcmstb_cpu_credit_reg_resume(void) ++static void brcmstb_cpu_credit_reg_resume(void *data) + { + unsigned int i; + +@@ -322,10 +322,14 @@ static void brcmstb_cpu_credit_reg_resume(void) + cbc_writel(cpubiuctrl_reg_save[i], i); + } + +-static struct syscore_ops brcmstb_cpu_credit_syscore_ops = { ++static const struct syscore_ops brcmstb_cpu_credit_syscore_ops = { + .suspend = brcmstb_cpu_credit_reg_suspend, + .resume = brcmstb_cpu_credit_reg_resume, + }; ++ ++static struct syscore brcmstb_cpu_credit_syscore = { ++ .ops = &brcmstb_cpu_credit_syscore_ops, ++}; + #endif + + +@@ -354,7 +358,7 @@ static int __init brcmstb_biuctrl_init(void) + a72_b53_rac_enable_all(np); + mcp_a72_b53_set(); + #ifdef CONFIG_PM_SLEEP +- register_syscore_ops(&brcmstb_cpu_credit_syscore_ops); ++ register_syscore(&brcmstb_cpu_credit_syscore); + #endif + ret = 0; + out_put: +diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c +index 034a2a535a1e..93bbebd68001 100644 +--- a/drivers/soc/tegra/pmc.c ++++ b/drivers/soc/tegra/pmc.c +@@ -466,7 +466,7 @@ struct tegra_pmc { + unsigned long *wake_type_dual_edge_map; + unsigned long *wake_sw_status_map; + unsigned long *wake_cntrl_level_map; +- struct syscore_ops syscore; ++ struct syscore syscore; + }; + + static struct tegra_pmc *pmc = &(struct tegra_pmc) { +@@ -3147,7 +3147,7 @@ static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int + } + } + +-static void tegra186_pmc_wake_syscore_resume(void) ++static void tegra186_pmc_wake_syscore_resume(void *data) + { + u32 status, mask; + unsigned int i; +@@ -3160,7 +3160,7 @@ static void tegra186_pmc_wake_syscore_resume(void) + } + } + +-static int tegra186_pmc_wake_syscore_suspend(void) ++static int tegra186_pmc_wake_syscore_suspend(void *data) + { + wke_read_sw_wake_status(pmc); + +@@ -3179,6 +3179,11 @@ static int tegra186_pmc_wake_syscore_suspend(void) + return 0; + } + ++static const struct syscore_ops tegra186_pmc_wake_syscore_ops = { ++ .suspend = tegra186_pmc_wake_syscore_suspend, ++ .resume = tegra186_pmc_wake_syscore_resume, ++}; ++ + #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) + static int tegra_pmc_suspend(struct device *dev) + { +@@ -3829,10 +3834,8 @@ static const struct tegra_pmc_regs tegra186_pmc_regs = { + + static void tegra186_pmc_init(struct tegra_pmc *pmc) + { +- pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; +- pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; +- +- register_syscore_ops(&pmc->syscore); ++ pmc->syscore.ops = &tegra186_pmc_wake_syscore_ops; ++ register_syscore(&pmc->syscore); + } + + static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, +diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c +index bd2fca7dc017..8a2f441cd2ec 100644 +--- a/drivers/thermal/intel/intel_hfi.c ++++ b/drivers/thermal/intel/intel_hfi.c +@@ -592,7 +592,7 @@ static void hfi_disable_instance(void *ptr) + hfi_disable(); + } + +-static void hfi_syscore_resume(void) ++static void hfi_syscore_resume(void *data) + { + /* This code runs only on the boot CPU. */ + struct hfi_cpu_info *info = &per_cpu(hfi_cpu_info, 0); +@@ -603,7 +603,7 @@ static void hfi_syscore_resume(void) + hfi_enable_instance(hfi_instance); + } + +-static int hfi_syscore_suspend(void) ++static int hfi_syscore_suspend(void *data) + { + /* No locking needed. There is no concurrency with CPU offline. */ + hfi_disable(); +@@ -611,11 +611,15 @@ static int hfi_syscore_suspend(void) + return 0; + } + +-static struct syscore_ops hfi_pm_ops = { ++static const struct syscore_ops hfi_pm_ops = { + .resume = hfi_syscore_resume, + .suspend = hfi_syscore_suspend, + }; + ++static struct syscore hfi_pm = { ++ .ops = &hfi_pm_ops, ++}; ++ + static int hfi_thermal_notify(struct notifier_block *nb, unsigned long state, + void *_notify) + { +@@ -710,7 +714,7 @@ void __init intel_hfi_init(void) + if (thermal_genl_register_notifier(&hfi_thermal_nb)) + goto err_nl_notif; + +- register_syscore_ops(&hfi_pm_ops); ++ register_syscore(&hfi_pm); + + return; + +diff --git a/drivers/xen/xen-acpi-processor.c b/drivers/xen/xen-acpi-processor.c +index 520756159d3d..8d1860bd5d57 100644 +--- a/drivers/xen/xen-acpi-processor.c ++++ b/drivers/xen/xen-acpi-processor.c +@@ -492,7 +492,7 @@ static void xen_acpi_processor_resume_worker(struct work_struct *dummy) + pr_info("ACPI data upload failed, error = %d\n", rc); + } + +-static void xen_acpi_processor_resume(void) ++static void xen_acpi_processor_resume(void *data) + { + static DECLARE_WORK(wq, xen_acpi_processor_resume_worker); + +@@ -506,10 +506,14 @@ static void xen_acpi_processor_resume(void) + schedule_work(&wq); + } + +-static struct syscore_ops xap_syscore_ops = { ++static const struct syscore_ops xap_syscore_ops = { + .resume = xen_acpi_processor_resume, + }; + ++static struct syscore xap_syscore = { ++ .ops = &xap_syscore_ops, ++}; ++ + static int __init xen_acpi_processor_init(void) + { + int i; +@@ -560,7 +564,7 @@ static int __init xen_acpi_processor_init(void) + if (rc) + goto err_unregister; + +- register_syscore_ops(&xap_syscore_ops); ++ register_syscore(&xap_syscore); + + return 0; + err_unregister: +@@ -577,7 +581,7 @@ static void __exit xen_acpi_processor_exit(void) + { + int i; + +- unregister_syscore_ops(&xap_syscore_ops); ++ unregister_syscore(&xap_syscore); + bitmap_free(acpi_ids_done); + bitmap_free(acpi_id_present); + bitmap_free(acpi_id_cst_present); +diff --git a/include/linux/syscore_ops.h b/include/linux/syscore_ops.h +index ae4d48e4c970..ac6d71be5c38 100644 +--- a/include/linux/syscore_ops.h ++++ b/include/linux/syscore_ops.h +@@ -11,14 +11,19 @@ + #include + + struct syscore_ops { ++ int (*suspend)(void *data); ++ void (*resume)(void *data); ++ void (*shutdown)(void *data); ++}; ++ ++struct syscore { + struct list_head node; +- int (*suspend)(void); +- void (*resume)(void); +- void (*shutdown)(void); ++ const struct syscore_ops *ops; ++ void *data; + }; + +-extern void register_syscore_ops(struct syscore_ops *ops); +-extern void unregister_syscore_ops(struct syscore_ops *ops); ++extern void register_syscore(struct syscore *syscore); ++extern void unregister_syscore(struct syscore *syscore); + #ifdef CONFIG_PM_SLEEP + extern int syscore_suspend(void); + extern void syscore_resume(void); +diff --git a/kernel/cpu_pm.c b/kernel/cpu_pm.c +index b0f0d15085db..7481fbb947d3 100644 +--- a/kernel/cpu_pm.c ++++ b/kernel/cpu_pm.c +@@ -173,7 +173,7 @@ int cpu_cluster_pm_exit(void) + EXPORT_SYMBOL_GPL(cpu_cluster_pm_exit); + + #ifdef CONFIG_PM +-static int cpu_pm_suspend(void) ++static int cpu_pm_suspend(void *data) + { + int ret; + +@@ -185,20 +185,24 @@ static int cpu_pm_suspend(void) + return ret; + } + +-static void cpu_pm_resume(void) ++static void cpu_pm_resume(void *data) + { + cpu_cluster_pm_exit(); + cpu_pm_exit(); + } + +-static struct syscore_ops cpu_pm_syscore_ops = { ++static const struct syscore_ops cpu_pm_syscore_ops = { + .suspend = cpu_pm_suspend, + .resume = cpu_pm_resume, + }; + ++static struct syscore cpu_pm_syscore = { ++ .ops = &cpu_pm_syscore_ops, ++}; ++ + static int cpu_pm_init(void) + { +- register_syscore_ops(&cpu_pm_syscore_ops); ++ register_syscore(&cpu_pm_syscore); + return 0; + } + core_initcall(cpu_pm_init); +diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c +index bf59e37d650a..3cd0c40282c0 100644 +--- a/kernel/irq/generic-chip.c ++++ b/kernel/irq/generic-chip.c +@@ -650,7 +650,7 @@ static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc) + } + + #ifdef CONFIG_PM +-static int irq_gc_suspend(void) ++static int irq_gc_suspend(void *data) + { + struct irq_chip_generic *gc; + +@@ -670,7 +670,7 @@ static int irq_gc_suspend(void) + return 0; + } + +-static void irq_gc_resume(void) ++static void irq_gc_resume(void *data) + { + struct irq_chip_generic *gc; + +@@ -693,7 +693,7 @@ static void irq_gc_resume(void) + #define irq_gc_resume NULL + #endif + +-static void irq_gc_shutdown(void) ++static void irq_gc_shutdown(void *data) + { + struct irq_chip_generic *gc; + +@@ -709,15 +709,19 @@ static void irq_gc_shutdown(void) + } + } + +-static struct syscore_ops irq_gc_syscore_ops = { ++static const struct syscore_ops irq_gc_syscore_ops = { + .suspend = irq_gc_suspend, + .resume = irq_gc_resume, + .shutdown = irq_gc_shutdown, + }; + ++static struct syscore irq_gc_syscore = { ++ .ops = &irq_gc_syscore_ops, ++}; ++ + static int __init irq_gc_init_ops(void) + { +- register_syscore_ops(&irq_gc_syscore_ops); ++ register_syscore(&irq_gc_syscore); + return 0; + } + device_initcall(irq_gc_init_ops); +diff --git a/kernel/irq/pm.c b/kernel/irq/pm.c +index f7394729cedc..99ff65466d87 100644 +--- a/kernel/irq/pm.c ++++ b/kernel/irq/pm.c +@@ -211,21 +211,26 @@ void rearm_wake_irq(unsigned int irq) + + /** + * irq_pm_syscore_resume - enable interrupt lines early ++ * @data: syscore context + * + * Enable all interrupt lines with %IRQF_EARLY_RESUME set. + */ +-static void irq_pm_syscore_resume(void) ++static void irq_pm_syscore_resume(void *data) + { + resume_irqs(true); + } + +-static struct syscore_ops irq_pm_syscore_ops = { ++static const struct syscore_ops irq_pm_syscore_ops = { + .resume = irq_pm_syscore_resume, + }; + ++static struct syscore irq_pm_syscore = { ++ .ops = &irq_pm_syscore_ops, ++}; ++ + static int __init irq_pm_init_ops(void) + { +- register_syscore_ops(&irq_pm_syscore_ops); ++ register_syscore(&irq_pm_syscore); + return 0; + } + +diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c +index c27fc7fc64eb..70a97290ad90 100644 +--- a/kernel/printk/printk.c ++++ b/kernel/printk/printk.c +@@ -3660,12 +3660,13 @@ static bool legacy_kthread_create(void) + + /** + * printk_kthreads_shutdown - shutdown all threaded printers ++ * @data: syscore context + * + * On system shutdown all threaded printers are stopped. This allows printk + * to transition back to atomic printing, thus providing a robust mechanism + * for the final shutdown/reboot messages to be output. + */ +-static void printk_kthreads_shutdown(void) ++static void printk_kthreads_shutdown(void *data) + { + struct console *con; + +@@ -3687,10 +3688,14 @@ static void printk_kthreads_shutdown(void) + console_list_unlock(); + } + +-static struct syscore_ops printk_syscore_ops = { ++static const struct syscore_ops printk_syscore_ops = { + .shutdown = printk_kthreads_shutdown, + }; + ++static struct syscore printk_syscore = { ++ .ops = &printk_syscore_ops, ++}; ++ + /* + * If appropriate, start nbcon kthreads and set @printk_kthreads_running. + * If any kthreads fail to start, those consoles are unregistered. +@@ -3758,7 +3763,7 @@ static void printk_kthreads_check_locked(void) + + static int __init printk_set_kthreads_ready(void) + { +- register_syscore_ops(&printk_syscore_ops); ++ register_syscore(&printk_syscore); + + console_list_lock(); + printk_kthreads_ready = true; +diff --git a/kernel/time/sched_clock.c b/kernel/time/sched_clock.c +index 425d429906d0..f3aaef695b8c 100644 +--- a/kernel/time/sched_clock.c ++++ b/kernel/time/sched_clock.c +@@ -296,6 +296,11 @@ int sched_clock_suspend(void) + return 0; + } + ++static int sched_clock_syscore_suspend(void *data) ++{ ++ return sched_clock_suspend(); ++} ++ + void sched_clock_resume(void) + { + struct clock_read_data *rd = &cd.read_data[0]; +@@ -305,14 +310,23 @@ void sched_clock_resume(void) + rd->read_sched_clock = cd.actual_read_sched_clock; + } + +-static struct syscore_ops sched_clock_ops = { +- .suspend = sched_clock_suspend, +- .resume = sched_clock_resume, ++static void sched_clock_syscore_resume(void *data) ++{ ++ sched_clock_resume(); ++} ++ ++static const struct syscore_ops sched_clock_syscore_ops = { ++ .suspend = sched_clock_syscore_suspend, ++ .resume = sched_clock_syscore_resume, ++}; ++ ++static struct syscore sched_clock_syscore = { ++ .ops = &sched_clock_syscore_ops, + }; + + static int __init sched_clock_syscore_init(void) + { +- register_syscore_ops(&sched_clock_ops); ++ register_syscore(&sched_clock_syscore); + + return 0; + } +diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c +index c7dcccc5f3d6..c07e562ee4c1 100644 +--- a/kernel/time/timekeeping.c ++++ b/kernel/time/timekeeping.c +@@ -1994,6 +1994,11 @@ void timekeeping_resume(void) + timerfd_resume(); + } + ++static void timekeeping_syscore_resume(void *data) ++{ ++ timekeeping_resume(); ++} ++ + int timekeeping_suspend(void) + { + struct timekeeper *tks = &tk_core.shadow_timekeeper; +@@ -2061,15 +2066,24 @@ int timekeeping_suspend(void) + return 0; + } + ++static int timekeeping_syscore_suspend(void *data) ++{ ++ return timekeeping_suspend(); ++} ++ + /* sysfs resume/suspend bits for timekeeping */ +-static struct syscore_ops timekeeping_syscore_ops = { +- .resume = timekeeping_resume, +- .suspend = timekeeping_suspend, ++static const struct syscore_ops timekeeping_syscore_ops = { ++ .resume = timekeeping_syscore_resume, ++ .suspend = timekeeping_syscore_suspend, ++}; ++ ++static struct syscore timekeeping_syscore = { ++ .ops = &timekeeping_syscore_ops, + }; + + static int __init timekeeping_init_ops(void) + { +- register_syscore_ops(&timekeeping_syscore_ops); ++ register_syscore(&timekeeping_syscore); + return 0; + } + device_initcall(timekeeping_init_ops); +diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c +index 46581554abfb..3ec22d034e73 100644 +--- a/virt/kvm/kvm_main.c ++++ b/virt/kvm/kvm_main.c +@@ -5629,7 +5629,7 @@ static int kvm_offline_cpu(unsigned int cpu) + return 0; + } + +-static void kvm_shutdown(void) ++static void kvm_shutdown(void *data) + { + /* + * Disable hardware virtualization and set kvm_rebooting to indicate +@@ -5647,7 +5647,7 @@ static void kvm_shutdown(void) + on_each_cpu(kvm_disable_virtualization_cpu, NULL, 1); + } + +-static int kvm_suspend(void) ++static int kvm_suspend(void *data) + { + /* + * Secondary CPUs and CPU hotplug are disabled across the suspend/resume +@@ -5664,7 +5664,7 @@ static int kvm_suspend(void) + return 0; + } + +-static void kvm_resume(void) ++static void kvm_resume(void *data) + { + lockdep_assert_not_held(&kvm_usage_lock); + lockdep_assert_irqs_disabled(); +@@ -5672,12 +5672,16 @@ static void kvm_resume(void) + WARN_ON_ONCE(kvm_enable_virtualization_cpu()); + } + +-static struct syscore_ops kvm_syscore_ops = { ++static const struct syscore_ops kvm_syscore_ops = { + .suspend = kvm_suspend, + .resume = kvm_resume, + .shutdown = kvm_shutdown, + }; + ++static struct syscore kvm_syscore = { ++ .ops = &kvm_syscore_ops, ++}; ++ + int kvm_enable_virtualization(void) + { + int r; +@@ -5694,7 +5698,7 @@ int kvm_enable_virtualization(void) + if (r) + goto err_cpuhp; + +- register_syscore_ops(&kvm_syscore_ops); ++ register_syscore(&kvm_syscore); + + /* + * Undo virtualization enabling and bail if the system is going down. +@@ -5716,7 +5720,7 @@ int kvm_enable_virtualization(void) + return 0; + + err_rebooting: +- unregister_syscore_ops(&kvm_syscore_ops); ++ unregister_syscore(&kvm_syscore); + cpuhp_remove_state(CPUHP_AP_KVM_ONLINE); + err_cpuhp: + kvm_arch_disable_virtualization(); +@@ -5732,7 +5736,7 @@ void kvm_disable_virtualization(void) + if (--kvm_usage_count) + return; + +- unregister_syscore_ops(&kvm_syscore_ops); ++ unregister_syscore(&kvm_syscore); + cpuhp_remove_state(CPUHP_AP_KVM_ONLINE); + kvm_arch_disable_virtualization(); + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch b/SPECS/linux-lts/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch new file mode 100644 index 0000000000..778297758c --- /dev/null +++ b/SPECS/linux-lts/0161-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch @@ -0,0 +1,325 @@ +From dc079d2d3ef26e7fc9ba38e7af9c67873ed5fc55 Mon Sep 17 00:00:00 2001 +From: Nick Hu +Date: Tue, 2 Dec 2025 14:07:41 +0800 +Subject: [RUYI PATCH] UPSTREAM: irqchip/riscv-aplic: Preserve APLIC states + across suspend/resume + +The APLIC states might be reset when the platform enters a low power +state, but the register states are not being preserved and restored, +which prevents interrupt delivery after the platform resumes. +Solve this by adding a syscore ops and a power management notifier to +preserve and restore the APLIC states on suspend and resume. + +[ tglx: Folded the build fix provided by Geert ] + +Signed-off-by: Nick Hu +Signed-off-by: Thomas Gleixner +Reviewed-by: Yong-Xuan Wang +Reviewed-by: Cyan Yang +Reviewed-by: Nutty Liu +Reviewed-by: Anup Patel +Link: https://patch.msgid.link/20251202-preserve-aplic-imsic-v3-2-1844fbf1fe92@sifive.com +(cherry picked from commit 95a8ddde36601d0a645475fb080ed118db59c8c3) +Signed-off-by: Han Gao +--- + drivers/irqchip/irq-riscv-aplic-direct.c | 10 ++ + drivers/irqchip/irq-riscv-aplic-main.c | 170 ++++++++++++++++++++++- + drivers/irqchip/irq-riscv-aplic-main.h | 19 +++ + 3 files changed, 198 insertions(+), 1 deletion(-) + +diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c +index c2a75bf3d20c..5a9650225dd8 100644 +--- a/drivers/irqchip/irq-riscv-aplic-direct.c ++++ b/drivers/irqchip/irq-riscv-aplic-direct.c +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -171,6 +172,15 @@ static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en) + writel(de, idc->regs + APLIC_IDC_IDELIVERY); + } + ++void aplic_direct_restore_states(struct aplic_priv *priv) ++{ ++ struct aplic_direct *direct = container_of(priv, struct aplic_direct, priv); ++ int cpu; ++ ++ for_each_cpu(cpu, &direct->lmask) ++ aplic_idc_set_delivery(per_cpu_ptr(&aplic_idcs, cpu), true); ++} ++ + static int aplic_direct_dying_cpu(unsigned int cpu) + { + if (aplic_direct_parent_irq) +diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c +index 93e7c51f944a..4495ca26abf5 100644 +--- a/drivers/irqchip/irq-riscv-aplic-main.c ++++ b/drivers/irqchip/irq-riscv-aplic-main.c +@@ -12,10 +12,169 @@ + #include + #include + #include ++#include ++#include + #include ++#include + + #include "irq-riscv-aplic-main.h" + ++static LIST_HEAD(aplics); ++ ++static void aplic_restore_states(struct aplic_priv *priv) ++{ ++ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs; ++ struct aplic_src_ctrl *srcs; ++ void __iomem *regs; ++ u32 nr_irqs, i; ++ ++ regs = priv->regs; ++ writel(saved_regs->domaincfg, regs + APLIC_DOMAINCFG); ++#ifdef CONFIG_RISCV_M_MODE ++ writel(saved_regs->msiaddr, regs + APLIC_xMSICFGADDR); ++ writel(saved_regs->msiaddrh, regs + APLIC_xMSICFGADDRH); ++#endif ++ /* ++ * The sourcecfg[i] has to be restored prior to the target[i], interrupt-pending and ++ * interrupt-enable bits. The AIA specification states that "Whenever interrupt source i is ++ * inactive in an interrupt domain, the corresponding interrupt-pending and interrupt-enable ++ * bits within the domain are read-only zeros, and register target[i] is also read-only ++ * zero." ++ */ ++ nr_irqs = priv->nr_irqs; ++ for (i = 0; i < nr_irqs; i++) { ++ srcs = &priv->saved_hw_regs.srcs[i]; ++ writel(srcs->sourcecfg, regs + APLIC_SOURCECFG_BASE + i * sizeof(u32)); ++ writel(srcs->target, regs + APLIC_TARGET_BASE + i * sizeof(u32)); ++ } ++ ++ for (i = 0; i <= nr_irqs; i += 32) { ++ srcs = &priv->saved_hw_regs.srcs[i]; ++ writel(-1U, regs + APLIC_CLRIE_BASE + (i / 32) * sizeof(u32)); ++ writel(srcs->ie, regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32)); ++ ++ /* Re-trigger the interrupts if it forwards interrupts to target harts by MSIs */ ++ if (!priv->nr_idcs) ++ writel(readl(regs + APLIC_CLRIP_BASE + (i / 32) * sizeof(u32)), ++ regs + APLIC_SETIP_BASE + (i / 32) * sizeof(u32)); ++ } ++ ++ if (priv->nr_idcs) ++ aplic_direct_restore_states(priv); ++} ++ ++static void aplic_save_states(struct aplic_priv *priv) ++{ ++ struct aplic_src_ctrl *srcs; ++ void __iomem *regs; ++ u32 i, nr_irqs; ++ ++ regs = priv->regs; ++ nr_irqs = priv->nr_irqs; ++ /* The valid interrupt source IDs range from 1 to N, where N is priv->nr_irqs */ ++ for (i = 0; i < nr_irqs; i++) { ++ srcs = &priv->saved_hw_regs.srcs[i]; ++ srcs->target = readl(regs + APLIC_TARGET_BASE + i * sizeof(u32)); ++ ++ if (i % 32) ++ continue; ++ ++ srcs->ie = readl(regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32)); ++ } ++ ++ /* Save the nr_irqs bit if needed */ ++ if (!(nr_irqs % 32)) { ++ srcs = &priv->saved_hw_regs.srcs[nr_irqs]; ++ srcs->ie = readl(regs + APLIC_SETIE_BASE + (nr_irqs / 32) * sizeof(u32)); ++ } ++} ++ ++static int aplic_syscore_suspend(void *data) ++{ ++ struct aplic_priv *priv; ++ ++ list_for_each_entry(priv, &aplics, head) ++ aplic_save_states(priv); ++ ++ return 0; ++} ++ ++static void aplic_syscore_resume(void *data) ++{ ++ struct aplic_priv *priv; ++ ++ list_for_each_entry(priv, &aplics, head) ++ aplic_restore_states(priv); ++} ++ ++static struct syscore_ops aplic_syscore_ops = { ++ .suspend = aplic_syscore_suspend, ++ .resume = aplic_syscore_resume, ++}; ++ ++static struct syscore aplic_syscore = { ++ .ops = &aplic_syscore_ops, ++}; ++ ++static int aplic_pm_notifier(struct notifier_block *nb, unsigned long action, void *data) ++{ ++ struct aplic_priv *priv = container_of(nb, struct aplic_priv, genpd_nb); ++ ++ switch (action) { ++ case GENPD_NOTIFY_PRE_OFF: ++ aplic_save_states(priv); ++ break; ++ case GENPD_NOTIFY_ON: ++ aplic_restore_states(priv); ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static void aplic_pm_remove(void *data) ++{ ++ struct aplic_priv *priv = data; ++ struct device *dev = priv->dev; ++ ++ list_del(&priv->head); ++ if (dev->pm_domain) ++ dev_pm_genpd_remove_notifier(dev); ++} ++ ++static int aplic_pm_add(struct device *dev, struct aplic_priv *priv) ++{ ++ struct aplic_src_ctrl *srcs; ++ int ret; ++ ++ srcs = devm_kzalloc(dev, (priv->nr_irqs + 1) * sizeof(*srcs), GFP_KERNEL); ++ if (!srcs) ++ return -ENOMEM; ++ ++ priv->saved_hw_regs.srcs = srcs; ++ list_add(&priv->head, &aplics); ++ if (dev->pm_domain) { ++ priv->genpd_nb.notifier_call = aplic_pm_notifier; ++ ret = dev_pm_genpd_add_notifier(dev, &priv->genpd_nb); ++ if (ret) ++ goto remove_head; ++ ++ ret = devm_pm_runtime_enable(dev); ++ if (ret) ++ goto remove_notifier; ++ } ++ ++ return devm_add_action_or_reset(dev, aplic_pm_remove, priv); ++ ++remove_notifier: ++ dev_pm_genpd_remove_notifier(dev); ++remove_head: ++ list_del(&priv->head); ++ return ret; ++} ++ + void aplic_irq_unmask(struct irq_data *d) + { + struct aplic_priv *priv = irq_data_get_irq_chip_data(d); +@@ -60,6 +219,8 @@ int aplic_irq_set_type(struct irq_data *d, unsigned int type) + sourcecfg += (d->hwirq - 1) * sizeof(u32); + writel(val, sourcecfg); + ++ priv->saved_hw_regs.srcs[d->hwirq - 1].sourcecfg = val; ++ + return 0; + } + +@@ -82,6 +243,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, + + void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) + { ++ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs; + u32 val; + #ifdef CONFIG_RISCV_M_MODE + u32 valh; +@@ -95,6 +257,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) + valh |= FIELD_PREP(APLIC_xMSICFGADDRH_HHXS, priv->msicfg.hhxs); + writel(val, priv->regs + APLIC_xMSICFGADDR); + writel(valh, priv->regs + APLIC_xMSICFGADDRH); ++ saved_regs->msiaddr = val; ++ saved_regs->msiaddrh = valh; + } + #endif + +@@ -106,6 +270,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) + writel(val, priv->regs + APLIC_DOMAINCFG); + if (readl(priv->regs + APLIC_DOMAINCFG) != val) + dev_warn(priv->dev, "unable to write 0x%x in domaincfg\n", val); ++ ++ saved_regs->domaincfg = val; + } + + static void aplic_init_hw_irqs(struct aplic_priv *priv) +@@ -176,7 +342,7 @@ int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem * + /* Setup initial state APLIC interrupts */ + aplic_init_hw_irqs(priv); + +- return 0; ++ return aplic_pm_add(dev, priv); + } + + static int aplic_probe(struct platform_device *pdev) +@@ -209,6 +375,8 @@ static int aplic_probe(struct platform_device *pdev) + if (rc) + dev_err_probe(dev, rc, "failed to setup APLIC in %s mode\n", + msi_mode ? "MSI" : "direct"); ++ else ++ register_syscore(&aplic_syscore); + + #ifdef CONFIG_ACPI + if (!acpi_disabled) +diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-riscv-aplic-main.h +index b0ad8cde69b1..2d8ad7138541 100644 +--- a/drivers/irqchip/irq-riscv-aplic-main.h ++++ b/drivers/irqchip/irq-riscv-aplic-main.h +@@ -23,7 +23,25 @@ struct aplic_msicfg { + u32 lhxw; + }; + ++struct aplic_src_ctrl { ++ u32 sourcecfg; ++ u32 target; ++ u32 ie; ++}; ++ ++struct aplic_saved_regs { ++ u32 domaincfg; ++#ifdef CONFIG_RISCV_M_MODE ++ u32 msiaddr; ++ u32 msiaddrh; ++#endif ++ struct aplic_src_ctrl *srcs; ++}; ++ + struct aplic_priv { ++ struct list_head head; ++ struct notifier_block genpd_nb; ++ struct aplic_saved_regs saved_hw_regs; + struct device *dev; + u32 gsi_base; + u32 nr_irqs; +@@ -40,6 +58,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, + unsigned long *hwirq, unsigned int *type); + void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode); + int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *regs); ++void aplic_direct_restore_states(struct aplic_priv *priv); + int aplic_direct_setup(struct device *dev, void __iomem *regs); + #ifdef CONFIG_RISCV_APLIC_MSI + int aplic_msi_setup(struct device *dev, void __iomem *regs); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0161-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch b/SPECS/linux-lts/0161-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch deleted file mode 100644 index f7ae99a862..0000000000 --- a/SPECS/linux-lts/0161-UPSTREAM-powerpc-pci-Initialize-msi_addr_mask-for-OF.patch +++ /dev/null @@ -1,59 +0,0 @@ -From d55d880c109f6894dbe383af6cca3b65ebab1537 Mon Sep 17 00:00:00 2001 -From: Nilay Shroff -Date: Fri, 20 Feb 2026 12:32:27 +0530 -Subject: [PATCH 161/467] UPSTREAM: powerpc/pci: Initialize msi_addr_mask for - OF-created PCI devices - -Recent changes replaced the use of no_64bit_msi with msi_addr_mask. As a -result, msi_addr_mask is now expected to be initialized to DMA_BIT_MASK(64) -when a pci_dev is set up. However, this initialization was missed on -powerpc due to differences in the device initialization path compared to -other (x86) architecture. Due to this, now PCI device probe method fails on -powerpc system. - -On powerpc systems, struct pci_dev instances are created from device tree -nodes via of_create_pci_dev(). Because msi_addr_mask was not initialized -there, it remained zero. Later, during MSI setup, msi_verify_entries() -validates the programmed MSI address against pdev->msi_addr_mask. Since the -mask was not set correctly, the validation fails, causing PCI driver probe -failures for devices on powerpc systems. - -Initialize pdev->msi_addr_mask to DMA_BIT_MASK(64) in of_create_pci_dev() -so that MSI address validation succeeds and device probe works as expected. - -Fixes: 386ced19e9a3 ("PCI/MSI: Convert the boolean no_64bit_msi flag to a DMA address mask") -Signed-off-by: Nilay Shroff -Signed-off-by: Bjorn Helgaas -Tested-by: Venkat Rao Bagalkote -Tested-by: Nam Cao -Reviewed-by: Nam Cao -Reviewed-by: Vivian Wang -Acked-by: Madhavan Srinivasan -Link: https://patch.msgid.link/20260220070239.1693303-2-nilay@linux.ibm.com -(cherry picked from commit 2185904ff8b5da76a4353e5d1236caa78e0d98e3) -Signed-off-by: Han Gao ---- - arch/powerpc/kernel/pci_of_scan.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c -index 756043dd06e9..fb9fbf0d1796 100644 ---- a/arch/powerpc/kernel/pci_of_scan.c -+++ b/arch/powerpc/kernel/pci_of_scan.c -@@ -212,6 +212,13 @@ struct pci_dev *of_create_pci_dev(struct device_node *node, - dev->error_state = pci_channel_io_normal; - dev->dma_mask = 0xffffffff; - -+ /* -+ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit -+ * if MSI (rather than MSI-X) capability does not have -+ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. -+ */ -+ dev->msi_addr_mask = DMA_BIT_MASK(64); -+ - /* Early fixups, before probing the BARs */ - pci_fixup_device(pci_fixup_early, dev); - --- -2.53.0 - diff --git a/SPECS/linux-lts/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch b/SPECS/linux-lts/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch new file mode 100644 index 0000000000..9ede52445f --- /dev/null +++ b/SPECS/linux-lts/0162-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch @@ -0,0 +1,59 @@ +From 9030f2dc70b9b4bd8e20de88dcbbd8afa905d20e Mon Sep 17 00:00:00 2001 +From: Jessica Liu +Date: Tue, 10 Mar 2026 14:16:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: irqchip/riscv-aplic: Do not clear ACPI + dependencies on probe failure + +aplic_probe() calls acpi_dev_clear_dependencies() unconditionally at the +end, even when the preceding setup (MSI or direct mode) has failed. This is +incorrect because if the device failed to probe, it should not be +considered as active and should not clear dependencies for other devices +waiting on it. + +Fix this by returning immediately when the setup fails, skipping the ACPI +dependency cleanup. Also, explicitly return 0 on success instead of relying +on the value of 'rc' to make the success path clear. + +Fixes: 5122e380c23b ("irqchip/riscv-aplic: Add ACPI support") +Signed-off-by: Jessica Liu +Signed-off-by: Thomas Gleixner +Link: https://patch.msgid.link/20260310141600411Fu8H8-GXOOgKISU48Tjgx@zte.com.cn +(cherry picked from commit 620b6ded72a7f0f77be6ec44d0462bb85729ab7a) +Signed-off-by: Han Gao +--- + drivers/irqchip/irq-riscv-aplic-main.c | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c +index 4495ca26abf5..8775f188ea4f 100644 +--- a/drivers/irqchip/irq-riscv-aplic-main.c ++++ b/drivers/irqchip/irq-riscv-aplic-main.c +@@ -372,18 +372,21 @@ static int aplic_probe(struct platform_device *pdev) + rc = aplic_msi_setup(dev, regs); + else + rc = aplic_direct_setup(dev, regs); +- if (rc) ++ ++ if (rc) { + dev_err_probe(dev, rc, "failed to setup APLIC in %s mode\n", + msi_mode ? "MSI" : "direct"); +- else +- register_syscore(&aplic_syscore); ++ return rc; ++ } ++ ++ register_syscore(&aplic_syscore); + + #ifdef CONFIG_ACPI + if (!acpi_disabled) + acpi_dev_clear_dependencies(ACPI_COMPANION(dev)); + #endif + +- return rc; ++ return 0; + } + + static const struct of_device_id aplic_match[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0162-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch b/SPECS/linux-lts/0162-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch deleted file mode 100644 index ee5c00b176..0000000000 --- a/SPECS/linux-lts/0162-UPSTREAM-sparc-PCI-Initialize-msi_addr_mask-for-OF-c.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 062318331f0323b6c2cde88974f89889bd3b3983 Mon Sep 17 00:00:00 2001 -From: Nilay Shroff -Date: Fri, 20 Feb 2026 12:32:28 +0530 -Subject: [PATCH 162/467] UPSTREAM: sparc/PCI: Initialize msi_addr_mask for - OF-created PCI devices - -Recent changes replaced the use of no_64bit_msi with msi_addr_mask, which -is now expected to be initialized to DMA_BIT_MASK(64) during PCI device -setup. On SPARC systems, this initialization was inadvertently missed for -devices instantiated from device tree nodes, leaving msi_addr_mask unset -for OF-created pci_dev instances. As a result, MSI address validation fails -during probe, causing affected devices to fail initialization. - -Initialize pdev->msi_addr_mask to DMA_BIT_MASK(64) in of_create_pci_dev() -so that MSI address validation succeeds and PCI device probing works as -expected. - -Fixes: 386ced19e9a3 ("PCI/MSI: Convert the boolean no_64bit_msi flag to a DMA address mask") -Signed-off-by: Nilay Shroff -Signed-off-by: Bjorn Helgaas -Tested-by: Han Gao # SPARC Enterprise T5220 -Tested-by: Nathaniel Roach # SPARC T5-2 -Reviewed-by: Vivian Wang -Link: https://patch.msgid.link/20260220070239.1693303-3-nilay@linux.ibm.com -(cherry picked from commit 147dae12985947cdb9e1918142f06482c5077a81) -Signed-off-by: Han Gao ---- - arch/sparc/kernel/pci.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c -index b290107170e9..a4815d544781 100644 ---- a/arch/sparc/kernel/pci.c -+++ b/arch/sparc/kernel/pci.c -@@ -355,6 +355,13 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, - dev->error_state = pci_channel_io_normal; - dev->dma_mask = 0xffffffff; - -+ /* -+ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit -+ * if MSI (rather than MSI-X) capability does not have -+ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver. -+ */ -+ dev->msi_addr_mask = DMA_BIT_MASK(64); -+ - if (of_node_name_eq(node, "pci")) { - /* a PCI-PCI bridge */ - dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; --- -2.53.0 - diff --git a/SPECS/linux-lts/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch b/SPECS/linux-lts/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch new file mode 100644 index 0000000000..7e5c262b22 --- /dev/null +++ b/SPECS/linux-lts/0163-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch @@ -0,0 +1,65 @@ +From f0f6537007b57483923b71a9da409d7811b4a6a1 Mon Sep 17 00:00:00 2001 +From: Jessica Liu +Date: Tue, 10 Mar 2026 14:17:31 +0800 +Subject: [RUYI PATCH] UPSTREAM: irqchip/riscv-aplic: Register syscore + operations only once + +Since commit 95a8ddde3660 ("irqchip/riscv-aplic: Preserve APLIC +states across suspend/resume"), when multiple NUMA nodes exist +and AIA is not configured as "none", aplic_probe() is called +multiple times. This leads to register_syscore(&aplic_syscore) +being invoked repeatedly, causing the following Oops: + + list_add double add: new=ffffffffb91461f0, prev=ffffffffb91461f0, next=ffffffffb915c408. + [] __list_add_valid_or_report+0x60/0xc0 + [] register_syscore+0x3e/0x70 + [] aplic_probe+0xc6/0x112 + +Fix this by registering syscore operations only once, using a static +variable aplic_syscore_registered to track registration. + +[ tglx: Trim backtrace properly ] + +Fixes: 95a8ddde3660 ("irqchip/riscv-aplic: Preserve APLIC states across suspend/resume") +Signed-off-by: Jessica Liu +Signed-off-by: Thomas Gleixner +Link: https://patch.msgid.link/20260310141731145xMwLsyvXl9Gw-m6A4VRYj@zte.com.cn +(cherry picked from commit b330fbfd34d7624bec62b99ad88dba2614326a19) +Signed-off-by: Han Gao +--- + drivers/irqchip/irq-riscv-aplic-main.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c +index 8775f188ea4f..9f53979b6962 100644 +--- a/drivers/irqchip/irq-riscv-aplic-main.c ++++ b/drivers/irqchip/irq-riscv-aplic-main.c +@@ -116,6 +116,16 @@ static struct syscore aplic_syscore = { + .ops = &aplic_syscore_ops, + }; + ++static bool aplic_syscore_registered __ro_after_init; ++ ++static void aplic_syscore_init(void) ++{ ++ if (!aplic_syscore_registered) { ++ register_syscore(&aplic_syscore); ++ aplic_syscore_registered = true; ++ } ++} ++ + static int aplic_pm_notifier(struct notifier_block *nb, unsigned long action, void *data) + { + struct aplic_priv *priv = container_of(nb, struct aplic_priv, genpd_nb); +@@ -379,7 +389,7 @@ static int aplic_probe(struct platform_device *pdev) + return rc; + } + +- register_syscore(&aplic_syscore); ++ aplic_syscore_init(); + + #ifdef CONFIG_ACPI + if (!acpi_disabled) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0163-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch b/SPECS/linux-lts/0163-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch deleted file mode 100644 index d62c31b7b3..0000000000 --- a/SPECS/linux-lts/0163-UPSTREAM-syscore-Pass-context-data-to-callbacks.patch +++ /dev/null @@ -1,4919 +0,0 @@ -From 3db4461f56317b6d1205c5f1aa79d971772b0d4d Mon Sep 17 00:00:00 2001 -From: Thierry Reding -Date: Wed, 29 Oct 2025 17:33:30 +0100 -Subject: [PATCH 163/467] UPSTREAM: syscore: Pass context data to callbacks - -Several drivers can benefit from registering per-instance data along -with the syscore operations. To achieve this, move the modifiable fields -out of the syscore_ops structure and into a separate struct syscore that -can be registered with the framework. Add a void * driver data field for -drivers to store contextual data that will be passed to the syscore ops. - -Acked-by: Rafael J. Wysocki (Intel) -Signed-off-by: Thierry Reding -(cherry picked from commit a97fbc3ee3e2a536fafaff04f21f45472db71769) -Signed-off-by: Han Gao ---- - arch/arm/mach-exynos/mcpm-exynos.c | 12 ++-- - arch/arm/mach-exynos/suspend.c | 48 +++++++------ - arch/arm/mach-pxa/generic.h | 6 +- - arch/arm/mach-pxa/irq.c | 10 ++- - arch/arm/mach-pxa/mfp-pxa2xx.c | 10 ++- - arch/arm/mach-pxa/mfp-pxa3xx.c | 10 ++- - arch/arm/mach-pxa/pxa25x.c | 4 +- - arch/arm/mach-pxa/pxa27x.c | 4 +- - arch/arm/mach-pxa/pxa3xx.c | 4 +- - arch/arm/mach-pxa/smemc.c | 12 ++-- - arch/arm/mach-s3c/irq-pm-s3c64xx.c | 12 ++-- - arch/arm/mach-s5pv210/pm.c | 10 ++- - arch/arm/mach-versatile/integrator_ap.c | 12 ++-- - arch/arm/mm/cache-b15-rac.c | 12 ++-- - arch/loongarch/kernel/smp.c | 12 ++-- - arch/mips/alchemy/common/dbdma.c | 12 ++-- - arch/mips/alchemy/common/irq.c | 24 ++++--- - arch/mips/alchemy/common/usb.c | 12 ++-- - arch/mips/pci/pci-alchemy.c | 16 +++-- - arch/powerpc/platforms/cell/spu_base.c | 10 ++- - arch/powerpc/platforms/powermac/pic.c | 12 ++-- - arch/powerpc/sysdev/fsl_lbc.c | 12 ++-- - arch/powerpc/sysdev/fsl_pci.c | 12 ++-- - arch/powerpc/sysdev/ipic.c | 12 ++-- - arch/powerpc/sysdev/mpic.c | 14 ++-- - arch/powerpc/sysdev/mpic_timer.c | 10 ++- - arch/sh/mm/pmb.c | 10 ++- - arch/x86/events/amd/ibs.c | 12 ++-- - arch/x86/hyperv/hv_init.c | 12 ++-- - arch/x86/kernel/amd_gart_64.c | 10 ++- - arch/x86/kernel/apic/apic.c | 12 ++-- - arch/x86/kernel/apic/io_apic.c | 17 +++-- - arch/x86/kernel/cpu/aperfmperf.c | 20 +++--- - arch/x86/kernel/cpu/intel_epb.c | 16 +++-- - arch/x86/kernel/cpu/mce/core.c | 14 ++-- - arch/x86/kernel/cpu/microcode/core.c | 15 ++++- - arch/x86/kernel/cpu/mtrr/legacy.c | 12 ++-- - arch/x86/kernel/cpu/umwait.c | 10 ++- - arch/x86/kernel/i8237.c | 10 ++- - arch/x86/kernel/i8259.c | 14 ++-- - arch/x86/kernel/kvm.c | 12 ++-- - drivers/acpi/pci_link.c | 10 ++- - drivers/acpi/sleep.c | 12 ++-- - drivers/base/firmware_loader/main.c | 12 ++-- - drivers/base/syscore.c | 82 ++++++++++++----------- - drivers/bus/mvebu-mbus.c | 16 +++-- - drivers/clk/at91/pmc.c | 12 ++-- - drivers/clk/imx/clk-vf610.c | 12 ++-- - drivers/clk/ingenic/jz4725b-cgu.c | 2 +- - drivers/clk/ingenic/jz4740-cgu.c | 2 +- - drivers/clk/ingenic/jz4755-cgu.c | 2 +- - drivers/clk/ingenic/jz4760-cgu.c | 2 +- - drivers/clk/ingenic/jz4770-cgu.c | 2 +- - drivers/clk/ingenic/jz4780-cgu.c | 2 +- - drivers/clk/ingenic/pm.c | 14 ++-- - drivers/clk/ingenic/pm.h | 2 +- - drivers/clk/ingenic/tcu.c | 12 ++-- - drivers/clk/ingenic/x1000-cgu.c | 2 +- - drivers/clk/ingenic/x1830-cgu.c | 2 +- - drivers/clk/mvebu/common.c | 12 ++-- - drivers/clk/rockchip/clk-rk3288.c | 12 ++-- - drivers/clk/samsung/clk-s5pv210-audss.c | 12 ++-- - drivers/clk/samsung/clk.c | 12 ++-- - drivers/clk/tegra/clk-tegra210.c | 12 ++-- - drivers/clocksource/timer-armada-370-xp.c | 12 ++-- - drivers/cpuidle/cpuidle-psci.c | 12 ++-- - drivers/gpio/gpio-mxc.c | 12 ++-- - drivers/gpio/gpio-pxa.c | 12 ++-- - drivers/gpio/gpio-sa1100.c | 12 ++-- - drivers/hv/vmbus_drv.c | 14 ++-- - drivers/iommu/amd/init.c | 16 +++-- - drivers/iommu/intel/iommu.c | 12 ++-- - drivers/irqchip/exynos-combiner.c | 14 ++-- - drivers/irqchip/irq-armada-370-xp.c | 12 ++-- - drivers/irqchip/irq-bcm7038-l1.c | 12 ++-- - drivers/irqchip/irq-gic-v3-its.c | 12 ++-- - drivers/irqchip/irq-i8259.c | 12 ++-- - drivers/irqchip/irq-imx-gpcv2.c | 16 +++-- - drivers/irqchip/irq-loongson-eiointc.c | 12 ++-- - drivers/irqchip/irq-loongson-htpic.c | 10 ++- - drivers/irqchip/irq-loongson-htvec.c | 12 ++-- - drivers/irqchip/irq-loongson-pch-lpc.c | 12 ++-- - drivers/irqchip/irq-loongson-pch-pic.c | 12 ++-- - drivers/irqchip/irq-mchp-eic.c | 12 ++-- - drivers/irqchip/irq-mst-intc.c | 12 ++-- - drivers/irqchip/irq-mtk-cirq.c | 12 ++-- - drivers/irqchip/irq-renesas-rzg2l.c | 12 ++-- - drivers/irqchip/irq-sa11x0.c | 12 ++-- - drivers/irqchip/irq-sifive-plic.c | 12 ++-- - drivers/irqchip/irq-sun6i-r.c | 18 +++-- - drivers/irqchip/irq-tegra.c | 12 ++-- - drivers/irqchip/irq-vic.c | 12 ++-- - drivers/leds/trigger/ledtrig-cpu.c | 14 ++-- - drivers/macintosh/via-pmu.c | 12 ++-- - drivers/power/reset/sc27xx-poweroff.c | 10 ++- - drivers/sh/clk/core.c | 10 ++- - drivers/sh/intc/core.c | 12 ++-- - drivers/soc/bcm/brcmstb/biuctrl.c | 12 ++-- - drivers/soc/tegra/pmc.c | 17 +++-- - drivers/thermal/intel/intel_hfi.c | 12 ++-- - drivers/xen/xen-acpi-processor.c | 12 ++-- - include/linux/syscore_ops.h | 15 +++-- - kernel/cpu_pm.c | 12 ++-- - kernel/irq/generic-chip.c | 14 ++-- - kernel/irq/pm.c | 11 ++- - kernel/printk/printk.c | 11 ++- - kernel/time/sched_clock.c | 22 ++++-- - kernel/time/timekeeping.c | 22 ++++-- - virt/kvm/kvm_main.c | 18 +++-- - 109 files changed, 898 insertions(+), 470 deletions(-) - -diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c -index fd0dbeb93357..cb7d8a7b14e0 100644 ---- a/arch/arm/mach-exynos/mcpm-exynos.c -+++ b/arch/arm/mach-exynos/mcpm-exynos.c -@@ -215,7 +215,7 @@ static const struct of_device_id exynos_dt_mcpm_match[] = { - {}, - }; - --static void exynos_mcpm_setup_entry_point(void) -+static void exynos_mcpm_setup_entry_point(void *data) - { - /* - * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr -@@ -228,10 +228,14 @@ static void exynos_mcpm_setup_entry_point(void) - __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8); - } - --static struct syscore_ops exynos_mcpm_syscore_ops = { -+static const struct syscore_ops exynos_mcpm_syscore_ops = { - .resume = exynos_mcpm_setup_entry_point, - }; - -+static struct syscore exynos_mcpm_syscore = { -+ .ops = &exynos_mcpm_syscore_ops, -+}; -+ - static int __init exynos_mcpm_init(void) - { - struct device_node *node; -@@ -300,9 +304,9 @@ static int __init exynos_mcpm_init(void) - pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i)); - } - -- exynos_mcpm_setup_entry_point(); -+ exynos_mcpm_setup_entry_point(NULL); - -- register_syscore_ops(&exynos_mcpm_syscore_ops); -+ register_syscore(&exynos_mcpm_syscore); - - return ret; - } -diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c -index 150a1e56dcae..22d723553f62 100644 ---- a/arch/arm/mach-exynos/suspend.c -+++ b/arch/arm/mach-exynos/suspend.c -@@ -53,9 +53,9 @@ struct exynos_pm_data { - - void (*pm_prepare)(void); - void (*pm_resume_prepare)(void); -- void (*pm_resume)(void); -- int (*pm_suspend)(void); - int (*cpu_suspend)(unsigned long); -+ -+ const struct syscore_ops *syscore_ops; - }; - - /* Used only on Exynos542x/5800 */ -@@ -376,7 +376,7 @@ static void exynos5420_pm_prepare(void) - } - - --static int exynos_pm_suspend(void) -+static int exynos_pm_suspend(void *data) - { - exynos_pm_central_suspend(); - -@@ -390,7 +390,7 @@ static int exynos_pm_suspend(void) - return 0; - } - --static int exynos5420_pm_suspend(void) -+static int exynos5420_pm_suspend(void *data) - { - u32 this_cluster; - -@@ -408,7 +408,7 @@ static int exynos5420_pm_suspend(void) - return 0; - } - --static void exynos_pm_resume(void) -+static void exynos_pm_resume(void *data) - { - u32 cpuid = read_cpuid_part(); - -@@ -429,7 +429,7 @@ static void exynos_pm_resume(void) - exynos_set_delayed_reset_assertion(true); - } - --static void exynos3250_pm_resume(void) -+static void exynos3250_pm_resume(void *data) - { - u32 cpuid = read_cpuid_part(); - -@@ -473,7 +473,7 @@ static void exynos5420_prepare_pm_resume(void) - } - } - --static void exynos5420_pm_resume(void) -+static void exynos5420_pm_resume(void *data) - { - unsigned long tmp; - -@@ -596,41 +596,52 @@ static const struct platform_suspend_ops exynos_suspend_ops = { - .valid = suspend_valid_only_mem, - }; - -+static const struct syscore_ops exynos3250_syscore_ops = { -+ .suspend = exynos_pm_suspend, -+ .resume = exynos3250_pm_resume, -+}; -+ - static const struct exynos_pm_data exynos3250_pm_data = { - .wkup_irq = exynos3250_wkup_irq, - .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), -- .pm_suspend = exynos_pm_suspend, -- .pm_resume = exynos3250_pm_resume, - .pm_prepare = exynos3250_pm_prepare, - .cpu_suspend = exynos3250_cpu_suspend, -+ .syscore_ops = &exynos3250_syscore_ops, -+}; -+ -+static const struct syscore_ops exynos_syscore_ops = { -+ .suspend = exynos_pm_suspend, -+ .resume = exynos_pm_resume, - }; - - static const struct exynos_pm_data exynos4_pm_data = { - .wkup_irq = exynos4_wkup_irq, - .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), -- .pm_suspend = exynos_pm_suspend, -- .pm_resume = exynos_pm_resume, - .pm_prepare = exynos_pm_prepare, - .cpu_suspend = exynos_cpu_suspend, -+ .syscore_ops = &exynos_syscore_ops, - }; - - static const struct exynos_pm_data exynos5250_pm_data = { - .wkup_irq = exynos5250_wkup_irq, - .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), -- .pm_suspend = exynos_pm_suspend, -- .pm_resume = exynos_pm_resume, - .pm_prepare = exynos_pm_prepare, - .cpu_suspend = exynos_cpu_suspend, -+ .syscore_ops = &exynos_syscore_ops, -+}; -+ -+static const struct syscore_ops exynos5420_syscore_ops = { -+ .resume = exynos5420_pm_resume, -+ .suspend = exynos5420_pm_suspend, - }; - - static const struct exynos_pm_data exynos5420_pm_data = { - .wkup_irq = exynos5250_wkup_irq, - .wake_disable_mask = (0x7F << 7) | (0x1F << 1), - .pm_resume_prepare = exynos5420_prepare_pm_resume, -- .pm_resume = exynos5420_pm_resume, -- .pm_suspend = exynos5420_pm_suspend, - .pm_prepare = exynos5420_pm_prepare, - .cpu_suspend = exynos5420_cpu_suspend, -+ .syscore_ops = &exynos5420_syscore_ops, - }; - - static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { -@@ -656,7 +667,7 @@ static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { - { /*sentinel*/ }, - }; - --static struct syscore_ops exynos_pm_syscore_ops; -+static struct syscore exynos_pm_syscore; - - void __init exynos_pm_init(void) - { -@@ -684,10 +695,9 @@ void __init exynos_pm_init(void) - tmp |= pm_data->wake_disable_mask; - pmu_raw_writel(tmp, S5P_WAKEUP_MASK); - -- exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; -- exynos_pm_syscore_ops.resume = pm_data->pm_resume; -+ exynos_pm_syscore.ops = pm_data->syscore_ops; - -- register_syscore_ops(&exynos_pm_syscore_ops); -+ register_syscore(&exynos_pm_syscore); - suspend_set_ops(&exynos_suspend_ops); - - /* -diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h -index c9c2c46ecead..caad4fca8de3 100644 ---- a/arch/arm/mach-pxa/generic.h -+++ b/arch/arm/mach-pxa/generic.h -@@ -34,9 +34,9 @@ extern void __init pxa27x_map_io(void); - extern void __init pxa3xx_init_irq(void); - extern void __init pxa3xx_map_io(void); - --extern struct syscore_ops pxa_irq_syscore_ops; --extern struct syscore_ops pxa2xx_mfp_syscore_ops; --extern struct syscore_ops pxa3xx_mfp_syscore_ops; -+extern struct syscore pxa_irq_syscore; -+extern struct syscore pxa2xx_mfp_syscore; -+extern struct syscore pxa3xx_mfp_syscore; - - void __init pxa_set_ffuart_info(void *info); - void __init pxa_set_btuart_info(void *info); -diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c -index 5bfce8aa4102..99acebbbf065 100644 ---- a/arch/arm/mach-pxa/irq.c -+++ b/arch/arm/mach-pxa/irq.c -@@ -178,7 +178,7 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) - static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; - static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; - --static int pxa_irq_suspend(void) -+static int pxa_irq_suspend(void *data) - { - int i; - -@@ -197,7 +197,7 @@ static int pxa_irq_suspend(void) - return 0; - } - --static void pxa_irq_resume(void) -+static void pxa_irq_resume(void *data) - { - int i; - -@@ -219,11 +219,15 @@ static void pxa_irq_resume(void) - #define pxa_irq_resume NULL - #endif - --struct syscore_ops pxa_irq_syscore_ops = { -+static const struct syscore_ops pxa_irq_syscore_ops = { - .suspend = pxa_irq_suspend, - .resume = pxa_irq_resume, - }; - -+struct syscore pxa_irq_syscore = { -+ .ops = &pxa_irq_syscore_ops, -+}; -+ - #ifdef CONFIG_OF - static const struct of_device_id intc_ids[] __initconst = { - { .compatible = "marvell,pxa-intc", }, -diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c -index f5a3d890f682..d1347055fbe4 100644 ---- a/arch/arm/mach-pxa/mfp-pxa2xx.c -+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c -@@ -346,7 +346,7 @@ static unsigned long saved_gpdr[4]; - static unsigned long saved_gplr[4]; - static unsigned long saved_pgsr[4]; - --static int pxa2xx_mfp_suspend(void) -+static int pxa2xx_mfp_suspend(void *data) - { - int i; - -@@ -385,7 +385,7 @@ static int pxa2xx_mfp_suspend(void) - return 0; - } - --static void pxa2xx_mfp_resume(void) -+static void pxa2xx_mfp_resume(void *data) - { - int i; - -@@ -404,11 +404,15 @@ static void pxa2xx_mfp_resume(void) - #define pxa2xx_mfp_resume NULL - #endif - --struct syscore_ops pxa2xx_mfp_syscore_ops = { -+static const struct syscore_ops pxa2xx_mfp_syscore_ops = { - .suspend = pxa2xx_mfp_suspend, - .resume = pxa2xx_mfp_resume, - }; - -+struct syscore pxa2xx_mfp_syscore = { -+ .ops = &pxa2xx_mfp_syscore_ops, -+}; -+ - static int __init pxa2xx_mfp_init(void) - { - int i; -diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c -index d16ab7451efe..fe7498fbb62b 100644 ---- a/arch/arm/mach-pxa/mfp-pxa3xx.c -+++ b/arch/arm/mach-pxa/mfp-pxa3xx.c -@@ -27,13 +27,13 @@ - * a pull-down mode if they're an active low chip select, and we're - * just entering standby. - */ --static int pxa3xx_mfp_suspend(void) -+static int pxa3xx_mfp_suspend(void *data) - { - mfp_config_lpm(); - return 0; - } - --static void pxa3xx_mfp_resume(void) -+static void pxa3xx_mfp_resume(void *data) - { - mfp_config_run(); - -@@ -49,7 +49,11 @@ static void pxa3xx_mfp_resume(void) - #define pxa3xx_mfp_resume NULL - #endif - --struct syscore_ops pxa3xx_mfp_syscore_ops = { -+static const struct syscore_ops pxa3xx_mfp_syscore_ops = { - .suspend = pxa3xx_mfp_suspend, - .resume = pxa3xx_mfp_resume, - }; -+ -+struct syscore pxa3xx_mfp_syscore = { -+ .ops = &pxa3xx_mfp_syscore_ops, -+}; -diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c -index 03e34841fc00..70509a599814 100644 ---- a/arch/arm/mach-pxa/pxa25x.c -+++ b/arch/arm/mach-pxa/pxa25x.c -@@ -235,8 +235,8 @@ static int __init pxa25x_init(void) - - pxa25x_init_pm(); - -- register_syscore_ops(&pxa_irq_syscore_ops); -- register_syscore_ops(&pxa2xx_mfp_syscore_ops); -+ register_syscore(&pxa_irq_syscore); -+ register_syscore(&pxa2xx_mfp_syscore); - - if (!of_have_populated_dt()) { - software_node_register(&pxa2xx_gpiochip_node); -diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c -index f8382477d629..ff6361979038 100644 ---- a/arch/arm/mach-pxa/pxa27x.c -+++ b/arch/arm/mach-pxa/pxa27x.c -@@ -337,8 +337,8 @@ static int __init pxa27x_init(void) - - pxa27x_init_pm(); - -- register_syscore_ops(&pxa_irq_syscore_ops); -- register_syscore_ops(&pxa2xx_mfp_syscore_ops); -+ register_syscore(&pxa_irq_syscore); -+ register_syscore(&pxa2xx_mfp_syscore); - - if (!of_have_populated_dt()) { - software_node_register(&pxa2xx_gpiochip_node); -diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c -index 1d1e5713464d..06c578ea658e 100644 ---- a/arch/arm/mach-pxa/pxa3xx.c -+++ b/arch/arm/mach-pxa/pxa3xx.c -@@ -424,8 +424,8 @@ static int __init pxa3xx_init(void) - if (cpu_is_pxa320()) - enable_irq_wake(IRQ_WAKEUP1); - -- register_syscore_ops(&pxa_irq_syscore_ops); -- register_syscore_ops(&pxa3xx_mfp_syscore_ops); -+ register_syscore(&pxa_irq_syscore); -+ register_syscore(&pxa3xx_mfp_syscore); - } - - return ret; -diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c -index 2d2a321d82f8..fb93a8f28356 100644 ---- a/arch/arm/mach-pxa/smemc.c -+++ b/arch/arm/mach-pxa/smemc.c -@@ -18,7 +18,7 @@ static unsigned long msc[2]; - static unsigned long sxcnfg, memclkcfg; - static unsigned long csadrcfg[4]; - --static int pxa3xx_smemc_suspend(void) -+static int pxa3xx_smemc_suspend(void *data) - { - msc[0] = __raw_readl(MSC0); - msc[1] = __raw_readl(MSC1); -@@ -32,7 +32,7 @@ static int pxa3xx_smemc_suspend(void) - return 0; - } - --static void pxa3xx_smemc_resume(void) -+static void pxa3xx_smemc_resume(void *data) - { - __raw_writel(msc[0], MSC0); - __raw_writel(msc[1], MSC1); -@@ -46,11 +46,15 @@ static void pxa3xx_smemc_resume(void) - __raw_writel(0x2, CSMSADRCFG); - } - --static struct syscore_ops smemc_syscore_ops = { -+static const struct syscore_ops smemc_syscore_ops = { - .suspend = pxa3xx_smemc_suspend, - .resume = pxa3xx_smemc_resume, - }; - -+static struct syscore smemc_syscore = { -+ .ops = &smemc_syscore_ops, -+}; -+ - static int __init smemc_init(void) - { - if (cpu_is_pxa3xx()) { -@@ -64,7 +68,7 @@ static int __init smemc_init(void) - */ - __raw_writel(0x2, CSMSADRCFG); - -- register_syscore_ops(&smemc_syscore_ops); -+ register_syscore(&smemc_syscore); - } - - return 0; -diff --git a/arch/arm/mach-s3c/irq-pm-s3c64xx.c b/arch/arm/mach-s3c/irq-pm-s3c64xx.c -index 4a1e935bada1..ab726c595001 100644 ---- a/arch/arm/mach-s3c/irq-pm-s3c64xx.c -+++ b/arch/arm/mach-s3c/irq-pm-s3c64xx.c -@@ -58,7 +58,7 @@ static struct irq_grp_save { - - static u32 irq_uart_mask[SERIAL_SAMSUNG_UARTS]; - --static int s3c64xx_irq_pm_suspend(void) -+static int s3c64xx_irq_pm_suspend(void *data) - { - struct irq_grp_save *grp = eint_grp_save; - int i; -@@ -79,7 +79,7 @@ static int s3c64xx_irq_pm_suspend(void) - return 0; - } - --static void s3c64xx_irq_pm_resume(void) -+static void s3c64xx_irq_pm_resume(void *data) - { - struct irq_grp_save *grp = eint_grp_save; - int i; -@@ -100,18 +100,22 @@ static void s3c64xx_irq_pm_resume(void) - S3C_PMDBG("%s: IRQ configuration restored\n", __func__); - } - --static struct syscore_ops s3c64xx_irq_syscore_ops = { -+static const struct syscore_ops s3c64xx_irq_syscore_ops = { - .suspend = s3c64xx_irq_pm_suspend, - .resume = s3c64xx_irq_pm_resume, - }; - -+static struct syscore s3c64xx_irq_syscore = { -+ .ops = &s3c64xx_irq_syscore_ops, -+}; -+ - static __init int s3c64xx_syscore_init(void) - { - /* Appropriate drivers (pinctrl, uart) handle this when using DT. */ - if (of_have_populated_dt() || !soc_is_s3c64xx()) - return 0; - -- register_syscore_ops(&s3c64xx_irq_syscore_ops); -+ register_syscore(&s3c64xx_irq_syscore); - - return 0; - } -diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c -index 6fa70f787df4..fa270750364c 100644 ---- a/arch/arm/mach-s5pv210/pm.c -+++ b/arch/arm/mach-s5pv210/pm.c -@@ -195,20 +195,24 @@ static const struct platform_suspend_ops s5pv210_suspend_ops = { - /* - * Syscore operations used to delay restore of certain registers. - */ --static void s5pv210_pm_resume(void) -+static void s5pv210_pm_resume(void *data) - { - s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); - } - --static struct syscore_ops s5pv210_pm_syscore_ops = { -+static const struct syscore_ops s5pv210_pm_syscore_ops = { - .resume = s5pv210_pm_resume, - }; - -+static struct syscore s5pv210_pm_syscore = { -+ .ops = &s5pv210_pm_syscore_ops, -+}; -+ - /* - * Initialization entry point. - */ - void __init s5pv210_pm_init(void) - { -- register_syscore_ops(&s5pv210_pm_syscore_ops); -+ register_syscore(&s5pv210_pm_syscore); - suspend_set_ops(&s5pv210_suspend_ops); - } -diff --git a/arch/arm/mach-versatile/integrator_ap.c b/arch/arm/mach-versatile/integrator_ap.c -index 4bd6712e9f52..ee90d6619d0d 100644 ---- a/arch/arm/mach-versatile/integrator_ap.c -+++ b/arch/arm/mach-versatile/integrator_ap.c -@@ -63,13 +63,13 @@ static void __init ap_map_io(void) - #ifdef CONFIG_PM - static unsigned long ic_irq_enable; - --static int irq_suspend(void) -+static int irq_suspend(void *data) - { - ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); - return 0; - } - --static void irq_resume(void) -+static void irq_resume(void *data) - { - /* disable all irq sources */ - cm_clear_irqs(); -@@ -83,14 +83,18 @@ static void irq_resume(void) - #define irq_resume NULL - #endif - --static struct syscore_ops irq_syscore_ops = { -+static const struct syscore_ops irq_syscore_ops = { - .suspend = irq_suspend, - .resume = irq_resume, - }; - -+static struct syscore irq_syscore = { -+ .ops = &irq_syscore_ops, -+}; -+ - static int __init irq_syscore_init(void) - { -- register_syscore_ops(&irq_syscore_ops); -+ register_syscore(&irq_syscore); - - return 0; - } -diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c -index 6f63b90f9e1a..e7807356dfab 100644 ---- a/arch/arm/mm/cache-b15-rac.c -+++ b/arch/arm/mm/cache-b15-rac.c -@@ -256,7 +256,7 @@ static int b15_rac_dead_cpu(unsigned int cpu) - return 0; - } - --static int b15_rac_suspend(void) -+static int b15_rac_suspend(void *data) - { - /* Suspend the read-ahead cache oeprations, forcing our cache - * implementation to fallback to the regular ARMv7 calls. -@@ -271,7 +271,7 @@ static int b15_rac_suspend(void) - return 0; - } - --static void b15_rac_resume(void) -+static void b15_rac_resume(void *data) - { - /* Coming out of a S3 suspend/resume cycle, the read-ahead cache - * register RAC_CONFIG0_REG will be restored to its default value, make -@@ -282,11 +282,15 @@ static void b15_rac_resume(void) - clear_bit(RAC_SUSPENDED, &b15_rac_flags); - } - --static struct syscore_ops b15_rac_syscore_ops = { -+static const struct syscore_ops b15_rac_syscore_ops = { - .suspend = b15_rac_suspend, - .resume = b15_rac_resume, - }; - -+static struct syscore b15_rac_syscore = { -+ .ops = &b15_rac_syscore_ops, -+}; -+ - static int __init b15_rac_init(void) - { - struct device_node *dn, *cpu_dn; -@@ -347,7 +351,7 @@ static int __init b15_rac_init(void) - } - - if (IS_ENABLED(CONFIG_PM_SLEEP)) -- register_syscore_ops(&b15_rac_syscore_ops); -+ register_syscore(&b15_rac_syscore); - - spin_lock(&rac_lock); - reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); -diff --git a/arch/loongarch/kernel/smp.c b/arch/loongarch/kernel/smp.c -index 46036d98da75..8b2fcb3fb874 100644 ---- a/arch/loongarch/kernel/smp.c -+++ b/arch/loongarch/kernel/smp.c -@@ -535,28 +535,32 @@ int hibernate_resume_nonboot_cpu_disable(void) - */ - #ifdef CONFIG_PM - --static int loongson_ipi_suspend(void) -+static int loongson_ipi_suspend(void *data) - { - return 0; - } - --static void loongson_ipi_resume(void) -+static void loongson_ipi_resume(void *data) - { - iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN); - } - --static struct syscore_ops loongson_ipi_syscore_ops = { -+static const struct syscore_ops loongson_ipi_syscore_ops = { - .resume = loongson_ipi_resume, - .suspend = loongson_ipi_suspend, - }; - -+static struct syscore loongson_ipi_syscore = { -+ .ops = &loongson_ipi_syscore_ops, -+}; -+ - /* - * Enable boot cpu ipi before enabling nonboot cpus - * during syscore_resume. - */ - static int __init ipi_pm_init(void) - { -- register_syscore_ops(&loongson_ipi_syscore_ops); -+ register_syscore(&loongson_ipi_syscore); - return 0; - } - -diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c -index 6a3c890f7bbf..6c2c2010bbae 100644 ---- a/arch/mips/alchemy/common/dbdma.c -+++ b/arch/mips/alchemy/common/dbdma.c -@@ -982,7 +982,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) - - static unsigned long alchemy_dbdma_pm_data[NUM_DBDMA_CHANS + 1][6]; - --static int alchemy_dbdma_suspend(void) -+static int alchemy_dbdma_suspend(void *data) - { - int i; - void __iomem *addr; -@@ -1019,7 +1019,7 @@ static int alchemy_dbdma_suspend(void) - return 0; - } - --static void alchemy_dbdma_resume(void) -+static void alchemy_dbdma_resume(void *data) - { - int i; - void __iomem *addr; -@@ -1044,11 +1044,15 @@ static void alchemy_dbdma_resume(void) - } - } - --static struct syscore_ops alchemy_dbdma_syscore_ops = { -+static const struct syscore_ops alchemy_dbdma_syscore_ops = { - .suspend = alchemy_dbdma_suspend, - .resume = alchemy_dbdma_resume, - }; - -+static struct syscore alchemy_dbdma_syscore = { -+ .ops = &alchemy_dbdma_syscore_ops, -+}; -+ - static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable) - { - int ret; -@@ -1071,7 +1075,7 @@ static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable) - printk(KERN_ERR "Cannot grab DBDMA interrupt!\n"); - else { - dbdma_initialized = 1; -- register_syscore_ops(&alchemy_dbdma_syscore_ops); -+ register_syscore(&alchemy_dbdma_syscore); - } - - return ret; -diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c -index da9f9220048f..2403afcd2fb9 100644 ---- a/arch/mips/alchemy/common/irq.c -+++ b/arch/mips/alchemy/common/irq.c -@@ -758,7 +758,7 @@ static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d) - wmb(); - } - --static int alchemy_ic_suspend(void) -+static int alchemy_ic_suspend(void *data) - { - alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR), - alchemy_gpic_pmdata); -@@ -767,7 +767,7 @@ static int alchemy_ic_suspend(void) - return 0; - } - --static void alchemy_ic_resume(void) -+static void alchemy_ic_resume(void *data) - { - alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR), - &alchemy_gpic_pmdata[7]); -@@ -775,7 +775,7 @@ static void alchemy_ic_resume(void) - alchemy_gpic_pmdata); - } - --static int alchemy_gpic_suspend(void) -+static int alchemy_gpic_suspend(void *data) - { - void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); - int i; -@@ -806,7 +806,7 @@ static int alchemy_gpic_suspend(void) - return 0; - } - --static void alchemy_gpic_resume(void) -+static void alchemy_gpic_resume(void *data) - { - void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); - int i; -@@ -837,16 +837,24 @@ static void alchemy_gpic_resume(void) - wmb(); - } - --static struct syscore_ops alchemy_ic_pmops = { -+static const struct syscore_ops alchemy_ic_pmops = { - .suspend = alchemy_ic_suspend, - .resume = alchemy_ic_resume, - }; - --static struct syscore_ops alchemy_gpic_pmops = { -+static struct syscore alchemy_ic_pm = { -+ .ops = &alchemy_ic_pmops, -+}; -+ -+static const struct syscore_ops alchemy_gpic_pmops = { - .suspend = alchemy_gpic_suspend, - .resume = alchemy_gpic_resume, - }; - -+static struct syscore alchemy_gpic_pm = { -+ .ops = &alchemy_gpic_pmops, -+}; -+ - /******************************************************************************/ - - /* create chained handlers for the 4 IC requests to the MIPS IRQ ctrl */ -@@ -880,7 +888,7 @@ static void __init au1000_init_irq(struct alchemy_irqmap *map) - - ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR)); - ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR)); -- register_syscore_ops(&alchemy_ic_pmops); -+ register_syscore(&alchemy_ic_pm); - mips_cpu_irq_init(); - - /* register all 64 possible IC0+IC1 irq sources as type "none". -@@ -925,7 +933,7 @@ static void __init alchemy_gpic_init_irq(const struct alchemy_irqmap *dints) - int i; - void __iomem *bank_base; - -- register_syscore_ops(&alchemy_gpic_pmops); -+ register_syscore(&alchemy_gpic_pm); - mips_cpu_irq_init(); - - /* disable & ack all possible interrupt sources */ -diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c -index 5d618547ebf0..a55f32bf517c 100644 ---- a/arch/mips/alchemy/common/usb.c -+++ b/arch/mips/alchemy/common/usb.c -@@ -580,22 +580,26 @@ static void alchemy_usb_pm(int susp) - } - } - --static int alchemy_usb_suspend(void) -+static int alchemy_usb_suspend(void *data) - { - alchemy_usb_pm(1); - return 0; - } - --static void alchemy_usb_resume(void) -+static void alchemy_usb_resume(void *data) - { - alchemy_usb_pm(0); - } - --static struct syscore_ops alchemy_usb_pm_ops = { -+static const struct syscore_ops alchemy_usb_pm_syscore_ops = { - .suspend = alchemy_usb_suspend, - .resume = alchemy_usb_resume, - }; - -+static struct syscore alchemy_usb_pm_syscore = { -+ .ops = &alchemy_usb_pm_syscore_ops, -+}; -+ - static int __init alchemy_usb_init(void) - { - int ret = 0; -@@ -620,7 +624,7 @@ static int __init alchemy_usb_init(void) - } - - if (!ret) -- register_syscore_ops(&alchemy_usb_pm_ops); -+ register_syscore(&alchemy_usb_pm_syscore); - - return ret; - } -diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c -index 58625d1b6465..6bfee0f71803 100644 ---- a/arch/mips/pci/pci-alchemy.c -+++ b/arch/mips/pci/pci-alchemy.c -@@ -304,7 +304,7 @@ static int alchemy_pci_def_idsel(unsigned int devsel, int assert) - } - - /* save PCI controller register contents. */ --static int alchemy_pci_suspend(void) -+static int alchemy_pci_suspend(void *data) - { - struct alchemy_pci_context *ctx = __alchemy_pci_ctx; - if (!ctx) -@@ -326,7 +326,7 @@ static int alchemy_pci_suspend(void) - return 0; - } - --static void alchemy_pci_resume(void) -+static void alchemy_pci_resume(void *data) - { - struct alchemy_pci_context *ctx = __alchemy_pci_ctx; - if (!ctx) -@@ -354,9 +354,13 @@ static void alchemy_pci_resume(void) - alchemy_pci_wired_entry(ctx); /* install it */ - } - --static struct syscore_ops alchemy_pci_pmops = { -- .suspend = alchemy_pci_suspend, -- .resume = alchemy_pci_resume, -+static const struct syscore_ops alchemy_pci_syscore_ops = { -+ .suspend = alchemy_pci_suspend, -+ .resume = alchemy_pci_resume, -+}; -+ -+static struct syscore alchemy_pci_syscore = { -+ .ops = &alchemy_pci_syscore_ops, - }; - - static int alchemy_pci_probe(struct platform_device *pdev) -@@ -478,7 +482,7 @@ static int alchemy_pci_probe(struct platform_device *pdev) - - __alchemy_pci_ctx = ctx; - platform_set_drvdata(pdev, ctx); -- register_syscore_ops(&alchemy_pci_pmops); -+ register_syscore(&alchemy_pci_syscore); - register_pci_controller(&ctx->alchemy_pci_ctrl); - - dev_info(&pdev->dev, "PCI controller at %ld MHz\n", -diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c -index 2c07387201d0..2ddb93df4817 100644 ---- a/arch/powerpc/platforms/cell/spu_base.c -+++ b/arch/powerpc/platforms/cell/spu_base.c -@@ -726,7 +726,7 @@ static inline void crash_register_spus(struct list_head *list) - } - #endif - --static void spu_shutdown(void) -+static void spu_shutdown(void *data) - { - struct spu *spu; - -@@ -738,10 +738,14 @@ static void spu_shutdown(void) - mutex_unlock(&spu_full_list_mutex); - } - --static struct syscore_ops spu_syscore_ops = { -+static const struct syscore_ops spu_syscore_ops = { - .shutdown = spu_shutdown, - }; - -+static struct syscore spu_syscore = { -+ .ops = &spu_syscore_ops, -+}; -+ - static int __init init_spu_base(void) - { - int i, ret = 0; -@@ -774,7 +778,7 @@ static int __init init_spu_base(void) - crash_register_spus(&spu_full_list); - mutex_unlock(&spu_full_list_mutex); - spu_add_dev_attr(&dev_attr_stat); -- register_syscore_ops(&spu_syscore_ops); -+ register_syscore(&spu_syscore); - - spu_init_affinity(); - -diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c -index c37783a03d25..1959cc13438f 100644 ---- a/arch/powerpc/platforms/powermac/pic.c -+++ b/arch/powerpc/platforms/powermac/pic.c -@@ -600,7 +600,7 @@ static int pmacpic_find_viaint(void) - return viaint; - } - --static int pmacpic_suspend(void) -+static int pmacpic_suspend(void *data) - { - int viaint = pmacpic_find_viaint(); - -@@ -621,7 +621,7 @@ static int pmacpic_suspend(void) - return 0; - } - --static void pmacpic_resume(void) -+static void pmacpic_resume(void *data) - { - int i; - -@@ -634,15 +634,19 @@ static void pmacpic_resume(void) - pmac_unmask_irq(irq_get_irq_data(i)); - } - --static struct syscore_ops pmacpic_syscore_ops = { -+static const struct syscore_ops pmacpic_syscore_ops = { - .suspend = pmacpic_suspend, - .resume = pmacpic_resume, - }; - -+static struct syscore pmacpic_syscore = { -+ .ops = &pmacpic_syscore_ops, -+}; -+ - static int __init init_pmacpic_syscore(void) - { - if (pmac_irq_hw[0]) -- register_syscore_ops(&pmacpic_syscore_ops); -+ register_syscore(&pmacpic_syscore); - return 0; - } - -diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c -index 217cea150987..7ed07232a69a 100644 ---- a/arch/powerpc/sysdev/fsl_lbc.c -+++ b/arch/powerpc/sysdev/fsl_lbc.c -@@ -350,7 +350,7 @@ static int fsl_lbc_ctrl_probe(struct platform_device *dev) - #ifdef CONFIG_SUSPEND - - /* save lbc registers */ --static int fsl_lbc_syscore_suspend(void) -+static int fsl_lbc_syscore_suspend(void *data) - { - struct fsl_lbc_ctrl *ctrl; - struct fsl_lbc_regs __iomem *lbc; -@@ -374,7 +374,7 @@ static int fsl_lbc_syscore_suspend(void) - } - - /* restore lbc registers */ --static void fsl_lbc_syscore_resume(void) -+static void fsl_lbc_syscore_resume(void *data) - { - struct fsl_lbc_ctrl *ctrl; - struct fsl_lbc_regs __iomem *lbc; -@@ -408,10 +408,14 @@ static const struct of_device_id fsl_lbc_match[] = { - }; - - #ifdef CONFIG_SUSPEND --static struct syscore_ops lbc_syscore_pm_ops = { -+static const struct syscore_ops lbc_syscore_pm_ops = { - .suspend = fsl_lbc_syscore_suspend, - .resume = fsl_lbc_syscore_resume, - }; -+ -+static struct syscore lbc_syscore_pm = { -+ .ops = &lbc_syscore_pm_ops, -+}; - #endif - - static struct platform_driver fsl_lbc_ctrl_driver = { -@@ -425,7 +429,7 @@ static struct platform_driver fsl_lbc_ctrl_driver = { - static int __init fsl_lbc_init(void) - { - #ifdef CONFIG_SUSPEND -- register_syscore_ops(&lbc_syscore_pm_ops); -+ register_syscore(&lbc_syscore_pm); - #endif - return platform_driver_register(&fsl_lbc_ctrl_driver); - } -diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c -index ef7707ea0db7..4e501654cb41 100644 ---- a/arch/powerpc/sysdev/fsl_pci.c -+++ b/arch/powerpc/sysdev/fsl_pci.c -@@ -1258,7 +1258,7 @@ static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) - send_pme_turnoff_message(hose); - } - --static int fsl_pci_syscore_suspend(void) -+static int fsl_pci_syscore_suspend(void *data) - { - struct pci_controller *hose, *tmp; - -@@ -1291,7 +1291,7 @@ static void fsl_pci_syscore_do_resume(struct pci_controller *hose) - setup_pci_atmu(hose); - } - --static void fsl_pci_syscore_resume(void) -+static void fsl_pci_syscore_resume(void *data) - { - struct pci_controller *hose, *tmp; - -@@ -1299,10 +1299,14 @@ static void fsl_pci_syscore_resume(void) - fsl_pci_syscore_do_resume(hose); - } - --static struct syscore_ops pci_syscore_pm_ops = { -+static const struct syscore_ops pci_syscore_pm_ops = { - .suspend = fsl_pci_syscore_suspend, - .resume = fsl_pci_syscore_resume, - }; -+ -+static struct syscore pci_syscore_pm = { -+ .ops = &pci_syscore_pm_ops, -+}; - #endif - - void fsl_pcibios_fixup_phb(struct pci_controller *phb) -@@ -1359,7 +1363,7 @@ static struct platform_driver fsl_pci_driver = { - static int __init fsl_pci_init(void) - { - #ifdef CONFIG_PM_SLEEP -- register_syscore_ops(&pci_syscore_pm_ops); -+ register_syscore(&pci_syscore_pm); - #endif - return platform_driver_register(&fsl_pci_driver); - } -diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c -index 70be2105865d..290ba8427239 100644 ---- a/arch/powerpc/sysdev/ipic.c -+++ b/arch/powerpc/sysdev/ipic.c -@@ -817,7 +817,7 @@ static struct { - u32 sercr; - } ipic_saved_state; - --static int ipic_suspend(void) -+static int ipic_suspend(void *data) - { - struct ipic *ipic = primary_ipic; - -@@ -848,7 +848,7 @@ static int ipic_suspend(void) - return 0; - } - --static void ipic_resume(void) -+static void ipic_resume(void *data) - { - struct ipic *ipic = primary_ipic; - -@@ -870,18 +870,22 @@ static void ipic_resume(void) - #define ipic_resume NULL - #endif - --static struct syscore_ops ipic_syscore_ops = { -+static const struct syscore_ops ipic_syscore_ops = { - .suspend = ipic_suspend, - .resume = ipic_resume, - }; - -+static struct syscore ipic_syscore = { -+ .ops = &ipic_syscore_ops, -+}; -+ - static int __init init_ipic_syscore(void) - { - if (!primary_ipic || !primary_ipic->regs) - return -ENODEV; - - printk(KERN_DEBUG "Registering ipic system core operations\n"); -- register_syscore_ops(&ipic_syscore_ops); -+ register_syscore(&ipic_syscore); - - return 0; - } -diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c -index ad7310bba00b..67e51998d1ae 100644 ---- a/arch/powerpc/sysdev/mpic.c -+++ b/arch/powerpc/sysdev/mpic.c -@@ -1944,7 +1944,7 @@ static void mpic_suspend_one(struct mpic *mpic) - } - } - --static int mpic_suspend(void) -+static int mpic_suspend(void *data) - { - struct mpic *mpic = mpics; - -@@ -1986,7 +1986,7 @@ static void mpic_resume_one(struct mpic *mpic) - } /* end for loop */ - } - --static void mpic_resume(void) -+static void mpic_resume(void *data) - { - struct mpic *mpic = mpics; - -@@ -1996,19 +1996,23 @@ static void mpic_resume(void) - } - } - --static struct syscore_ops mpic_syscore_ops = { -+static const struct syscore_ops mpic_syscore_ops = { - .resume = mpic_resume, - .suspend = mpic_suspend, - }; - -+static struct syscore mpic_syscore = { -+ .ops = &mpic_syscore_ops, -+}; -+ - static int mpic_init_sys(void) - { - int rc; - -- register_syscore_ops(&mpic_syscore_ops); -+ register_syscore(&mpic_syscore); - rc = subsys_system_register(&mpic_subsys, NULL); - if (rc) { -- unregister_syscore_ops(&mpic_syscore_ops); -+ unregister_syscore(&mpic_syscore); - pr_err("mpic: Failed to register subsystem!\n"); - return rc; - } -diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c -index 7166e2e0baaf..60f5b3934b51 100644 ---- a/arch/powerpc/sysdev/mpic_timer.c -+++ b/arch/powerpc/sysdev/mpic_timer.c -@@ -519,7 +519,7 @@ static void __init timer_group_init(struct device_node *np) - kfree(priv); - } - --static void mpic_timer_resume(void) -+static void mpic_timer_resume(void *data) - { - struct timer_group_priv *priv; - -@@ -535,10 +535,14 @@ static const struct of_device_id mpic_timer_ids[] = { - {}, - }; - --static struct syscore_ops mpic_timer_syscore_ops = { -+static const struct syscore_ops mpic_timer_syscore_ops = { - .resume = mpic_timer_resume, - }; - -+static struct syscore mpic_timer_syscore = { -+ .ops = &mpic_timer_syscore_ops, -+}; -+ - static int __init mpic_timer_init(void) - { - struct device_node *np = NULL; -@@ -546,7 +550,7 @@ static int __init mpic_timer_init(void) - for_each_matching_node(np, mpic_timer_ids) - timer_group_init(np); - -- register_syscore_ops(&mpic_timer_syscore_ops); -+ register_syscore(&mpic_timer_syscore); - - if (list_empty(&timer_group_list)) - return -ENODEV; -diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c -index 68eb7cc6e564..482eec50f404 100644 ---- a/arch/sh/mm/pmb.c -+++ b/arch/sh/mm/pmb.c -@@ -857,7 +857,7 @@ static int __init pmb_debugfs_init(void) - subsys_initcall(pmb_debugfs_init); - - #ifdef CONFIG_PM --static void pmb_syscore_resume(void) -+static void pmb_syscore_resume(void *data) - { - struct pmb_entry *pmbe; - int i; -@@ -874,13 +874,17 @@ static void pmb_syscore_resume(void) - read_unlock(&pmb_rwlock); - } - --static struct syscore_ops pmb_syscore_ops = { -+static const struct syscore_ops pmb_syscore_ops = { - .resume = pmb_syscore_resume, - }; - -+static struct syscore pmb_syscore = { -+ .ops = &pmb_syscore_ops, -+}; -+ - static int __init pmb_sysdev_init(void) - { -- register_syscore_ops(&pmb_syscore_ops); -+ register_syscore(&pmb_syscore); - return 0; - } - subsys_initcall(pmb_sysdev_init); -diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c -index 56918cd91115..23d834e7b565 100644 ---- a/arch/x86/events/amd/ibs.c -+++ b/arch/x86/events/amd/ibs.c -@@ -1719,26 +1719,30 @@ static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu) - - #ifdef CONFIG_PM - --static int perf_ibs_suspend(void) -+static int perf_ibs_suspend(void *data) - { - clear_APIC_ibs(); - return 0; - } - --static void perf_ibs_resume(void) -+static void perf_ibs_resume(void *data) - { - ibs_eilvt_setup(); - setup_APIC_ibs(); - } - --static struct syscore_ops perf_ibs_syscore_ops = { -+static const struct syscore_ops perf_ibs_syscore_ops = { - .resume = perf_ibs_resume, - .suspend = perf_ibs_suspend, - }; - -+static struct syscore perf_ibs_syscore = { -+ .ops = &perf_ibs_syscore_ops, -+}; -+ - static void perf_ibs_pm_init(void) - { -- register_syscore_ops(&perf_ibs_syscore_ops); -+ register_syscore(&perf_ibs_syscore); - } - - #else -diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c -index e890fd37e9c2..085ef4f2e73a 100644 ---- a/arch/x86/hyperv/hv_init.c -+++ b/arch/x86/hyperv/hv_init.c -@@ -351,7 +351,7 @@ static int __init hv_pci_init(void) - return 1; - } - --static int hv_suspend(void) -+static int hv_suspend(void *data) - { - union hv_x64_msr_hypercall_contents hypercall_msr; - int ret; -@@ -378,7 +378,7 @@ static int hv_suspend(void) - return ret; - } - --static void hv_resume(void) -+static void hv_resume(void *data) - { - union hv_x64_msr_hypercall_contents hypercall_msr; - int ret; -@@ -405,11 +405,15 @@ static void hv_resume(void) - } - - /* Note: when the ops are called, only CPU0 is online and IRQs are disabled. */ --static struct syscore_ops hv_syscore_ops = { -+static const struct syscore_ops hv_syscore_ops = { - .suspend = hv_suspend, - .resume = hv_resume, - }; - -+static struct syscore hv_syscore = { -+ .ops = &hv_syscore_ops, -+}; -+ - static void (* __initdata old_setup_percpu_clockev)(void); - - static void __init hv_stimer_setup_percpu_clockev(void) -@@ -569,7 +573,7 @@ void __init hyperv_init(void) - - x86_init.pci.arch_init = hv_pci_init; - -- register_syscore_ops(&hv_syscore_ops); -+ register_syscore(&hv_syscore); - - if (ms_hyperv.priv_high & HV_ACCESS_PARTITION_ID) - hv_get_partition_id(); -diff --git a/arch/x86/kernel/amd_gart_64.c b/arch/x86/kernel/amd_gart_64.c -index 3485d419c2f5..e6e68a31634c 100644 ---- a/arch/x86/kernel/amd_gart_64.c -+++ b/arch/x86/kernel/amd_gart_64.c -@@ -591,7 +591,7 @@ static void gart_fixup_northbridges(void) - } - } - --static void gart_resume(void) -+static void gart_resume(void *data) - { - pr_info("PCI-DMA: Resuming GART IOMMU\n"); - -@@ -600,11 +600,15 @@ static void gart_resume(void) - enable_gart_translations(); - } - --static struct syscore_ops gart_syscore_ops = { -+static const struct syscore_ops gart_syscore_ops = { - .resume = gart_resume, - - }; - -+static struct syscore gart_syscore = { -+ .ops = &gart_syscore_ops, -+}; -+ - /* - * Private Northbridge GATT initialization in case we cannot use the - * AGP driver for some reason. -@@ -650,7 +654,7 @@ static __init int init_amd_gatt(struct agp_kern_info *info) - - agp_gatt_table = gatt; - -- register_syscore_ops(&gart_syscore_ops); -+ register_syscore(&gart_syscore); - - flush_gart(); - -diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c -index aa1b0ef5e931..a4431f0d2580 100644 ---- a/arch/x86/kernel/apic/apic.c -+++ b/arch/x86/kernel/apic/apic.c -@@ -2382,7 +2382,7 @@ static struct { - unsigned int apic_cmci; - } apic_pm_state; - --static int lapic_suspend(void) -+static int lapic_suspend(void *data) - { - unsigned long flags; - int maxlvt; -@@ -2430,7 +2430,7 @@ static int lapic_suspend(void) - return 0; - } - --static void lapic_resume(void) -+static void lapic_resume(void *data) - { - unsigned int l, h; - unsigned long flags; -@@ -2510,11 +2510,15 @@ static void lapic_resume(void) - * are needed on every CPU up until machine_halt/restart/poweroff. - */ - --static struct syscore_ops lapic_syscore_ops = { -+static const struct syscore_ops lapic_syscore_ops = { - .resume = lapic_resume, - .suspend = lapic_suspend, - }; - -+static struct syscore lapic_syscore = { -+ .ops = &lapic_syscore_ops, -+}; -+ - static void apic_pm_activate(void) - { - apic_pm_state.active = 1; -@@ -2524,7 +2528,7 @@ static int __init init_lapic_sysfs(void) - { - /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ - if (boot_cpu_has(X86_FEATURE_APIC)) -- register_syscore_ops(&lapic_syscore_ops); -+ register_syscore(&lapic_syscore); - - return 0; - } -diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c -index 5ba2feb2c04c..84e200662ce6 100644 ---- a/arch/x86/kernel/apic/io_apic.c -+++ b/arch/x86/kernel/apic/io_apic.c -@@ -2308,7 +2308,12 @@ static void resume_ioapic_id(int ioapic_idx) - } - } - --static void ioapic_resume(void) -+static int ioapic_suspend(void *data) -+{ -+ return save_ioapic_entries(); -+} -+ -+static void ioapic_resume(void *data) - { - int ioapic_idx; - -@@ -2318,14 +2323,18 @@ static void ioapic_resume(void) - restore_ioapic_entries(); - } - --static struct syscore_ops ioapic_syscore_ops = { -- .suspend = save_ioapic_entries, -+static const struct syscore_ops ioapic_syscore_ops = { -+ .suspend = ioapic_suspend, - .resume = ioapic_resume, - }; - -+static struct syscore ioapic_syscore = { -+ .ops = &ioapic_syscore_ops, -+}; -+ - static int __init ioapic_init_ops(void) - { -- register_syscore_ops(&ioapic_syscore_ops); -+ register_syscore(&ioapic_syscore); - - return 0; - } -diff --git a/arch/x86/kernel/cpu/aperfmperf.c b/arch/x86/kernel/cpu/aperfmperf.c -index a315b0627dfb..7ffc78d5ebf2 100644 ---- a/arch/x86/kernel/cpu/aperfmperf.c -+++ b/arch/x86/kernel/cpu/aperfmperf.c -@@ -37,7 +37,7 @@ static DEFINE_PER_CPU_SHARED_ALIGNED(struct aperfmperf, cpu_samples) = { - .seq = SEQCNT_ZERO(cpu_samples.seq) - }; - --static void init_counter_refs(void) -+static void init_counter_refs(void *data) - { - u64 aperf, mperf; - -@@ -289,16 +289,20 @@ static bool __init intel_set_max_freq_ratio(void) - } - - #ifdef CONFIG_PM_SLEEP --static struct syscore_ops freq_invariance_syscore_ops = { -+static const struct syscore_ops freq_invariance_syscore_ops = { - .resume = init_counter_refs, - }; - --static void register_freq_invariance_syscore_ops(void) -+static struct syscore freq_invariance_syscore = { -+ .ops = &freq_invariance_syscore_ops, -+}; -+ -+static void register_freq_invariance_syscore(void) - { -- register_syscore_ops(&freq_invariance_syscore_ops); -+ register_syscore(&freq_invariance_syscore); - } - #else --static inline void register_freq_invariance_syscore_ops(void) {} -+static inline void register_freq_invariance_syscore(void) {} - #endif - - static void freq_invariance_enable(void) -@@ -308,7 +312,7 @@ static void freq_invariance_enable(void) - return; - } - static_branch_enable_cpuslocked(&arch_scale_freq_key); -- register_freq_invariance_syscore_ops(); -+ register_freq_invariance_syscore(); - pr_info("Estimated ratio of average max frequency by base frequency (times 1024): %llu\n", arch_max_freq_ratio); - } - -@@ -535,7 +539,7 @@ static int __init bp_init_aperfmperf(void) - if (!cpu_feature_enabled(X86_FEATURE_APERFMPERF)) - return 0; - -- init_counter_refs(); -+ init_counter_refs(NULL); - bp_init_freq_invariance(); - return 0; - } -@@ -544,5 +548,5 @@ early_initcall(bp_init_aperfmperf); - void ap_init_aperfmperf(void) - { - if (cpu_feature_enabled(X86_FEATURE_APERFMPERF)) -- init_counter_refs(); -+ init_counter_refs(NULL); - } -diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c -index bc7671f920a7..2c56f8730f59 100644 ---- a/arch/x86/kernel/cpu/intel_epb.c -+++ b/arch/x86/kernel/cpu/intel_epb.c -@@ -75,7 +75,7 @@ static u8 energ_perf_values[] = { - [EPB_INDEX_POWERSAVE] = ENERGY_PERF_BIAS_POWERSAVE, - }; - --static int intel_epb_save(void) -+static int intel_epb_save(void *data) - { - u64 epb; - -@@ -89,7 +89,7 @@ static int intel_epb_save(void) - return 0; - } - --static void intel_epb_restore(void) -+static void intel_epb_restore(void *data) - { - u64 val = this_cpu_read(saved_epb); - u64 epb; -@@ -114,11 +114,15 @@ static void intel_epb_restore(void) - wrmsrq(MSR_IA32_ENERGY_PERF_BIAS, (epb & ~EPB_MASK) | val); - } - --static struct syscore_ops intel_epb_syscore_ops = { -+static const struct syscore_ops intel_epb_syscore_ops = { - .suspend = intel_epb_save, - .resume = intel_epb_restore, - }; - -+static struct syscore intel_epb_syscore = { -+ .ops = &intel_epb_syscore_ops, -+}; -+ - static const char * const energy_perf_strings[] = { - [EPB_INDEX_PERFORMANCE] = "performance", - [EPB_INDEX_BALANCE_PERFORMANCE] = "balance-performance", -@@ -185,7 +189,7 @@ static int intel_epb_online(unsigned int cpu) - { - struct device *cpu_dev = get_cpu_device(cpu); - -- intel_epb_restore(); -+ intel_epb_restore(NULL); - if (!cpuhp_tasks_frozen) - sysfs_merge_group(&cpu_dev->kobj, &intel_epb_attr_group); - -@@ -199,7 +203,7 @@ static int intel_epb_offline(unsigned int cpu) - if (!cpuhp_tasks_frozen) - sysfs_unmerge_group(&cpu_dev->kobj, &intel_epb_attr_group); - -- intel_epb_save(); -+ intel_epb_save(NULL); - return 0; - } - -@@ -230,7 +234,7 @@ static __init int intel_epb_init(void) - if (ret < 0) - goto err_out_online; - -- register_syscore_ops(&intel_epb_syscore_ops); -+ register_syscore(&intel_epb_syscore); - return 0; - - err_out_online: -diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c -index 460e90a1a0b1..23bfbc7dfb8e 100644 ---- a/arch/x86/kernel/cpu/mce/core.c -+++ b/arch/x86/kernel/cpu/mce/core.c -@@ -2410,13 +2410,13 @@ static void vendor_disable_error_reporting(void) - mce_disable_error_reporting(); - } - --static int mce_syscore_suspend(void) -+static int mce_syscore_suspend(void *data) - { - vendor_disable_error_reporting(); - return 0; - } - --static void mce_syscore_shutdown(void) -+static void mce_syscore_shutdown(void *data) - { - vendor_disable_error_reporting(); - } -@@ -2426,7 +2426,7 @@ static void mce_syscore_shutdown(void) - * Only one CPU is active at this time, the others get re-added later using - * CPU hotplug: - */ --static void mce_syscore_resume(void) -+static void mce_syscore_resume(void *data) - { - __mcheck_cpu_init_generic(); - __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); -@@ -2434,12 +2434,16 @@ static void mce_syscore_resume(void) - cr4_set_bits(X86_CR4_MCE); - } - --static struct syscore_ops mce_syscore_ops = { -+static const struct syscore_ops mce_syscore_ops = { - .suspend = mce_syscore_suspend, - .shutdown = mce_syscore_shutdown, - .resume = mce_syscore_resume, - }; - -+static struct syscore mce_syscore = { -+ .ops = &mce_syscore_ops, -+}; -+ - /* - * mce_device: Sysfs support - */ -@@ -2840,7 +2844,7 @@ static __init int mcheck_init_device(void) - if (err < 0) - goto err_out_online; - -- register_syscore_ops(&mce_syscore_ops); -+ register_syscore(&mce_syscore); - - return 0; - -diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c -index 539edd6d6dc8..81aa079fad26 100644 ---- a/arch/x86/kernel/cpu/microcode/core.c -+++ b/arch/x86/kernel/cpu/microcode/core.c -@@ -812,8 +812,17 @@ void microcode_bsp_resume(void) - reload_early_microcode(cpu); - } - --static struct syscore_ops mc_syscore_ops = { -- .resume = microcode_bsp_resume, -+static void microcode_bsp_syscore_resume(void *data) -+{ -+ microcode_bsp_resume(); -+} -+ -+static const struct syscore_ops mc_syscore_ops = { -+ .resume = microcode_bsp_syscore_resume, -+}; -+ -+static struct syscore mc_syscore = { -+ .ops = &mc_syscore_ops, - }; - - static int mc_cpu_online(unsigned int cpu) -@@ -892,7 +901,7 @@ static int __init microcode_init(void) - } - } - -- register_syscore_ops(&mc_syscore_ops); -+ register_syscore(&mc_syscore); - cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", - mc_cpu_online, mc_cpu_down_prep); - -diff --git a/arch/x86/kernel/cpu/mtrr/legacy.c b/arch/x86/kernel/cpu/mtrr/legacy.c -index d25882fcf181..2415ffaaf02c 100644 ---- a/arch/x86/kernel/cpu/mtrr/legacy.c -+++ b/arch/x86/kernel/cpu/mtrr/legacy.c -@@ -41,7 +41,7 @@ struct mtrr_value { - - static struct mtrr_value *mtrr_value; - --static int mtrr_save(void) -+static int mtrr_save(void *data) - { - int i; - -@@ -56,7 +56,7 @@ static int mtrr_save(void) - return 0; - } - --static void mtrr_restore(void) -+static void mtrr_restore(void *data) - { - int i; - -@@ -69,11 +69,15 @@ static void mtrr_restore(void) - } - } - --static struct syscore_ops mtrr_syscore_ops = { -+static const struct syscore_ops mtrr_syscore_ops = { - .suspend = mtrr_save, - .resume = mtrr_restore, - }; - -+static struct syscore mtrr_syscore = { -+ .ops = &mtrr_syscore_ops, -+}; -+ - void mtrr_register_syscore(void) - { - mtrr_value = kcalloc(num_var_ranges, sizeof(*mtrr_value), GFP_KERNEL); -@@ -86,5 +90,5 @@ void mtrr_register_syscore(void) - * TBD: is there any system with such CPU which supports - * suspend/resume? If no, we should remove the code. - */ -- register_syscore_ops(&mtrr_syscore_ops); -+ register_syscore(&mtrr_syscore); - } -diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c -index 933fcd7ff250..e4a31c536642 100644 ---- a/arch/x86/kernel/cpu/umwait.c -+++ b/arch/x86/kernel/cpu/umwait.c -@@ -86,15 +86,19 @@ static int umwait_cpu_offline(unsigned int cpu) - * trust the firmware nor does it matter if the same value is written - * again. - */ --static void umwait_syscore_resume(void) -+static void umwait_syscore_resume(void *data) - { - umwait_update_control_msr(NULL); - } - --static struct syscore_ops umwait_syscore_ops = { -+static const struct syscore_ops umwait_syscore_ops = { - .resume = umwait_syscore_resume, - }; - -+static struct syscore umwait_syscore = { -+ .ops = &umwait_syscore_ops, -+}; -+ - /* sysfs interface */ - - /* -@@ -226,7 +230,7 @@ static int __init umwait_init(void) - return ret; - } - -- register_syscore_ops(&umwait_syscore_ops); -+ register_syscore(&umwait_syscore); - - /* - * Add umwait control interface. Ignore failure, so at least the -diff --git a/arch/x86/kernel/i8237.c b/arch/x86/kernel/i8237.c -index 2cd124ad9380..896d46b44284 100644 ---- a/arch/x86/kernel/i8237.c -+++ b/arch/x86/kernel/i8237.c -@@ -19,7 +19,7 @@ - * in asm/dma.h. - */ - --static void i8237A_resume(void) -+static void i8237A_resume(void *data) - { - unsigned long flags; - int i; -@@ -41,10 +41,14 @@ static void i8237A_resume(void) - release_dma_lock(flags); - } - --static struct syscore_ops i8237_syscore_ops = { -+static const struct syscore_ops i8237_syscore_ops = { - .resume = i8237A_resume, - }; - -+static struct syscore i8237_syscore = { -+ .ops = &i8237_syscore_ops, -+}; -+ - static int __init i8237A_init_ops(void) - { - /* -@@ -70,7 +74,7 @@ static int __init i8237A_init_ops(void) - if (x86_pnpbios_disabled() && dmi_get_bios_year() >= 2017) - return -ENODEV; - -- register_syscore_ops(&i8237_syscore_ops); -+ register_syscore(&i8237_syscore); - return 0; - } - device_initcall(i8237A_init_ops); -diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c -index 2bade73f49e3..f67063df6723 100644 ---- a/arch/x86/kernel/i8259.c -+++ b/arch/x86/kernel/i8259.c -@@ -247,19 +247,19 @@ static void save_ELCR(char *trigger) - trigger[1] = inb(PIC_ELCR2) & 0xDE; - } - --static void i8259A_resume(void) -+static void i8259A_resume(void *data) - { - init_8259A(i8259A_auto_eoi); - restore_ELCR(irq_trigger); - } - --static int i8259A_suspend(void) -+static int i8259A_suspend(void *data) - { - save_ELCR(irq_trigger); - return 0; - } - --static void i8259A_shutdown(void) -+static void i8259A_shutdown(void *data) - { - /* Put the i8259A into a quiescent state that - * the kernel initialization code can get it -@@ -269,12 +269,16 @@ static void i8259A_shutdown(void) - outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ - } - --static struct syscore_ops i8259_syscore_ops = { -+static const struct syscore_ops i8259_syscore_ops = { - .suspend = i8259A_suspend, - .resume = i8259A_resume, - .shutdown = i8259A_shutdown, - }; - -+static struct syscore i8259_syscore = { -+ .ops = &i8259_syscore_ops, -+}; -+ - static void mask_8259A(void) - { - unsigned long flags; -@@ -444,7 +448,7 @@ EXPORT_SYMBOL(legacy_pic); - static int __init i8259A_init_ops(void) - { - if (legacy_pic == &default_legacy_pic) -- register_syscore_ops(&i8259_syscore_ops); -+ register_syscore(&i8259_syscore); - - return 0; - } -diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c -index b67d7c59dca0..1500852ba03c 100644 ---- a/arch/x86/kernel/kvm.c -+++ b/arch/x86/kernel/kvm.c -@@ -720,7 +720,7 @@ static int kvm_cpu_down_prepare(unsigned int cpu) - - #endif - --static int kvm_suspend(void) -+static int kvm_suspend(void *data) - { - u64 val = 0; - -@@ -734,7 +734,7 @@ static int kvm_suspend(void) - return 0; - } - --static void kvm_resume(void) -+static void kvm_resume(void *data) - { - kvm_cpu_online(raw_smp_processor_id()); - -@@ -744,11 +744,15 @@ static void kvm_resume(void) - #endif - } - --static struct syscore_ops kvm_syscore_ops = { -+static const struct syscore_ops kvm_syscore_ops = { - .suspend = kvm_suspend, - .resume = kvm_resume, - }; - -+static struct syscore kvm_syscore = { -+ .ops = &kvm_syscore_ops, -+}; -+ - static void kvm_pv_guest_cpu_reboot(void *unused) - { - kvm_guest_cpu_offline(true); -@@ -858,7 +862,7 @@ static void __init kvm_guest_init(void) - machine_ops.crash_shutdown = kvm_crash_shutdown; - #endif - -- register_syscore_ops(&kvm_syscore_ops); -+ register_syscore(&kvm_syscore); - - /* - * Hard lockup detection is enabled by default. Disable it, as guests -diff --git a/drivers/acpi/pci_link.c b/drivers/acpi/pci_link.c -index e4560b33b8ad..bed7dc85612e 100644 ---- a/drivers/acpi/pci_link.c -+++ b/drivers/acpi/pci_link.c -@@ -761,7 +761,7 @@ static int acpi_pci_link_resume(struct acpi_pci_link *link) - return 0; - } - --static void irqrouter_resume(void) -+static void irqrouter_resume(void *data) - { - struct acpi_pci_link *link; - -@@ -888,10 +888,14 @@ static int __init acpi_irq_balance_set(char *str) - - __setup("acpi_irq_balance", acpi_irq_balance_set); - --static struct syscore_ops irqrouter_syscore_ops = { -+static const struct syscore_ops irqrouter_syscore_ops = { - .resume = irqrouter_resume, - }; - -+static struct syscore irqrouter_syscore = { -+ .ops = &irqrouter_syscore_ops, -+}; -+ - void __init acpi_pci_link_init(void) - { - if (acpi_noirq) -@@ -904,6 +908,6 @@ void __init acpi_pci_link_init(void) - else - acpi_irq_balance = 0; - } -- register_syscore_ops(&irqrouter_syscore_ops); -+ register_syscore(&irqrouter_syscore); - acpi_scan_add_handler(&pci_link_handler); - } -diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c -index 0b7fa4a8c379..1b9579bb97c2 100644 ---- a/drivers/acpi/sleep.c -+++ b/drivers/acpi/sleep.c -@@ -892,13 +892,13 @@ bool acpi_s2idle_wakeup(void) - #ifdef CONFIG_PM_SLEEP - static u32 saved_bm_rld; - --static int acpi_save_bm_rld(void) -+static int acpi_save_bm_rld(void *data) - { - acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); - return 0; - } - --static void acpi_restore_bm_rld(void) -+static void acpi_restore_bm_rld(void *data) - { - u32 resumed_bm_rld = 0; - -@@ -909,14 +909,18 @@ static void acpi_restore_bm_rld(void) - acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); - } - --static struct syscore_ops acpi_sleep_syscore_ops = { -+static const struct syscore_ops acpi_sleep_syscore_ops = { - .suspend = acpi_save_bm_rld, - .resume = acpi_restore_bm_rld, - }; - -+static struct syscore acpi_sleep_syscore = { -+ .ops = &acpi_sleep_syscore_ops, -+}; -+ - static void acpi_sleep_syscore_init(void) - { -- register_syscore_ops(&acpi_sleep_syscore_ops); -+ register_syscore(&acpi_sleep_syscore); - } - #else - static inline void acpi_sleep_syscore_init(void) {} -diff --git a/drivers/base/firmware_loader/main.c b/drivers/base/firmware_loader/main.c -index 6942c62fa59d..8191dbab92c4 100644 ---- a/drivers/base/firmware_loader/main.c -+++ b/drivers/base/firmware_loader/main.c -@@ -1585,16 +1585,20 @@ static int fw_pm_notify(struct notifier_block *notify_block, - } - - /* stop caching firmware once syscore_suspend is reached */ --static int fw_suspend(void) -+static int fw_suspend(void *data) - { - fw_cache.state = FW_LOADER_NO_CACHE; - return 0; - } - --static struct syscore_ops fw_syscore_ops = { -+static const struct syscore_ops fw_syscore_ops = { - .suspend = fw_suspend, - }; - -+static struct syscore fw_syscore = { -+ .ops = &fw_syscore_ops, -+}; -+ - static int __init register_fw_pm_ops(void) - { - int ret; -@@ -1610,14 +1614,14 @@ static int __init register_fw_pm_ops(void) - if (ret) - return ret; - -- register_syscore_ops(&fw_syscore_ops); -+ register_syscore(&fw_syscore); - - return ret; - } - - static inline void unregister_fw_pm_ops(void) - { -- unregister_syscore_ops(&fw_syscore_ops); -+ unregister_syscore(&fw_syscore); - unregister_pm_notifier(&fw_cache.pm_notify); - } - #else -diff --git a/drivers/base/syscore.c b/drivers/base/syscore.c -index 13db1f78d2ce..483adb796654 100644 ---- a/drivers/base/syscore.c -+++ b/drivers/base/syscore.c -@@ -11,32 +11,32 @@ - #include - #include - --static LIST_HEAD(syscore_ops_list); --static DEFINE_MUTEX(syscore_ops_lock); -+static LIST_HEAD(syscore_list); -+static DEFINE_MUTEX(syscore_lock); - - /** -- * register_syscore_ops - Register a set of system core operations. -- * @ops: System core operations to register. -+ * register_syscore - Register a set of system core operations. -+ * @syscore: System core operations to register. - */ --void register_syscore_ops(struct syscore_ops *ops) -+void register_syscore(struct syscore *syscore) - { -- mutex_lock(&syscore_ops_lock); -- list_add_tail(&ops->node, &syscore_ops_list); -- mutex_unlock(&syscore_ops_lock); -+ mutex_lock(&syscore_lock); -+ list_add_tail(&syscore->node, &syscore_list); -+ mutex_unlock(&syscore_lock); - } --EXPORT_SYMBOL_GPL(register_syscore_ops); -+EXPORT_SYMBOL_GPL(register_syscore); - - /** -- * unregister_syscore_ops - Unregister a set of system core operations. -- * @ops: System core operations to unregister. -+ * unregister_syscore - Unregister a set of system core operations. -+ * @syscore: System core operations to unregister. - */ --void unregister_syscore_ops(struct syscore_ops *ops) -+void unregister_syscore(struct syscore *syscore) - { -- mutex_lock(&syscore_ops_lock); -- list_del(&ops->node); -- mutex_unlock(&syscore_ops_lock); -+ mutex_lock(&syscore_lock); -+ list_del(&syscore->node); -+ mutex_unlock(&syscore_lock); - } --EXPORT_SYMBOL_GPL(unregister_syscore_ops); -+EXPORT_SYMBOL_GPL(unregister_syscore); - - #ifdef CONFIG_PM_SLEEP - /** -@@ -46,7 +46,7 @@ EXPORT_SYMBOL_GPL(unregister_syscore_ops); - */ - int syscore_suspend(void) - { -- struct syscore_ops *ops; -+ struct syscore *syscore; - int ret = 0; - - trace_suspend_resume(TPS("syscore_suspend"), 0, true); -@@ -59,25 +59,27 @@ int syscore_suspend(void) - WARN_ONCE(!irqs_disabled(), - "Interrupts enabled before system core suspend.\n"); - -- list_for_each_entry_reverse(ops, &syscore_ops_list, node) -- if (ops->suspend) { -- pm_pr_dbg("Calling %pS\n", ops->suspend); -- ret = ops->suspend(); -+ list_for_each_entry_reverse(syscore, &syscore_list, node) -+ if (syscore->ops->suspend) { -+ pm_pr_dbg("Calling %pS\n", syscore->ops->suspend); -+ ret = syscore->ops->suspend(syscore->data); - if (ret) - goto err_out; - WARN_ONCE(!irqs_disabled(), -- "Interrupts enabled after %pS\n", ops->suspend); -+ "Interrupts enabled after %pS\n", -+ syscore->ops->suspend); - } - - trace_suspend_resume(TPS("syscore_suspend"), 0, false); - return 0; - - err_out: -- pr_err("PM: System core suspend callback %pS failed.\n", ops->suspend); -+ pr_err("PM: System core suspend callback %pS failed.\n", -+ syscore->ops->suspend); - -- list_for_each_entry_continue(ops, &syscore_ops_list, node) -- if (ops->resume) -- ops->resume(); -+ list_for_each_entry_continue(syscore, &syscore_list, node) -+ if (syscore->ops->resume) -+ syscore->ops->resume(syscore->data); - - return ret; - } -@@ -90,18 +92,19 @@ EXPORT_SYMBOL_GPL(syscore_suspend); - */ - void syscore_resume(void) - { -- struct syscore_ops *ops; -+ struct syscore *syscore; - - trace_suspend_resume(TPS("syscore_resume"), 0, true); - WARN_ONCE(!irqs_disabled(), - "Interrupts enabled before system core resume.\n"); - -- list_for_each_entry(ops, &syscore_ops_list, node) -- if (ops->resume) { -- pm_pr_dbg("Calling %pS\n", ops->resume); -- ops->resume(); -+ list_for_each_entry(syscore, &syscore_list, node) -+ if (syscore->ops->resume) { -+ pm_pr_dbg("Calling %pS\n", syscore->ops->resume); -+ syscore->ops->resume(syscore->data); - WARN_ONCE(!irqs_disabled(), -- "Interrupts enabled after %pS\n", ops->resume); -+ "Interrupts enabled after %pS\n", -+ syscore->ops->resume); - } - trace_suspend_resume(TPS("syscore_resume"), 0, false); - } -@@ -113,16 +116,17 @@ EXPORT_SYMBOL_GPL(syscore_resume); - */ - void syscore_shutdown(void) - { -- struct syscore_ops *ops; -+ struct syscore *syscore; - -- mutex_lock(&syscore_ops_lock); -+ mutex_lock(&syscore_lock); - -- list_for_each_entry_reverse(ops, &syscore_ops_list, node) -- if (ops->shutdown) { -+ list_for_each_entry_reverse(syscore, &syscore_list, node) -+ if (syscore->ops->shutdown) { - if (initcall_debug) -- pr_info("PM: Calling %pS\n", ops->shutdown); -- ops->shutdown(); -+ pr_info("PM: Calling %pS\n", -+ syscore->ops->shutdown); -+ syscore->ops->shutdown(syscore->data); - } - -- mutex_unlock(&syscore_ops_lock); -+ mutex_unlock(&syscore_lock); - } -diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c -index 00cb792bda18..dd94145c9b22 100644 ---- a/drivers/bus/mvebu-mbus.c -+++ b/drivers/bus/mvebu-mbus.c -@@ -1006,7 +1006,7 @@ static __init int mvebu_mbus_debugfs_init(void) - } - fs_initcall(mvebu_mbus_debugfs_init); - --static int mvebu_mbus_suspend(void) -+static int mvebu_mbus_suspend(void *data) - { - struct mvebu_mbus_state *s = &mbus_state; - int win; -@@ -1040,7 +1040,7 @@ static int mvebu_mbus_suspend(void) - return 0; - } - --static void mvebu_mbus_resume(void) -+static void mvebu_mbus_resume(void *data) - { - struct mvebu_mbus_state *s = &mbus_state; - int win; -@@ -1069,9 +1069,13 @@ static void mvebu_mbus_resume(void) - } - } - --static struct syscore_ops mvebu_mbus_syscore_ops = { -- .suspend = mvebu_mbus_suspend, -- .resume = mvebu_mbus_resume, -+static const struct syscore_ops mvebu_mbus_syscore_ops = { -+ .suspend = mvebu_mbus_suspend, -+ .resume = mvebu_mbus_resume, -+}; -+ -+static struct syscore mvebu_mbus_syscore = { -+ .ops = &mvebu_mbus_syscore_ops, - }; - - static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, -@@ -1118,7 +1122,7 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, - writel(UNIT_SYNC_BARRIER_ALL, - mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF); - -- register_syscore_ops(&mvebu_mbus_syscore_ops); -+ register_syscore(&mvebu_mbus_syscore); - - return 0; - } -diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c -index acf780a81589..2310f6f73162 100644 ---- a/drivers/clk/at91/pmc.c -+++ b/drivers/clk/at91/pmc.c -@@ -115,7 +115,7 @@ struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, - /* Address in SECURAM that say if we suspend to backup mode. */ - static void __iomem *at91_pmc_backup_suspend; - --static int at91_pmc_suspend(void) -+static int at91_pmc_suspend(void *data) - { - unsigned int backup; - -@@ -129,7 +129,7 @@ static int at91_pmc_suspend(void) - return clk_save_context(); - } - --static void at91_pmc_resume(void) -+static void at91_pmc_resume(void *data) - { - unsigned int backup; - -@@ -143,11 +143,15 @@ static void at91_pmc_resume(void) - clk_restore_context(); - } - --static struct syscore_ops pmc_syscore_ops = { -+static const struct syscore_ops pmc_syscore_ops = { - .suspend = at91_pmc_suspend, - .resume = at91_pmc_resume, - }; - -+static struct syscore pmc_syscore = { -+ .ops = &pmc_syscore_ops, -+}; -+ - static const struct of_device_id pmc_dt_ids[] = { - { .compatible = "atmel,sama5d2-pmc" }, - { .compatible = "microchip,sama7g5-pmc", }, -@@ -185,7 +189,7 @@ static int __init pmc_register_ops(void) - return -ENOMEM; - } - -- register_syscore_ops(&pmc_syscore_ops); -+ register_syscore(&pmc_syscore); - - return 0; - } -diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c -index 9e11f1c7c397..41eb38552a9c 100644 ---- a/drivers/clk/imx/clk-vf610.c -+++ b/drivers/clk/imx/clk-vf610.c -@@ -139,7 +139,7 @@ static struct clk * __init vf610_get_fixed_clock( - return clk; - }; - --static int vf610_clk_suspend(void) -+static int vf610_clk_suspend(void *data) - { - int i; - -@@ -156,7 +156,7 @@ static int vf610_clk_suspend(void) - return 0; - } - --static void vf610_clk_resume(void) -+static void vf610_clk_resume(void *data) - { - int i; - -@@ -171,11 +171,15 @@ static void vf610_clk_resume(void) - writel_relaxed(ccgr[i], CCM_CCGRx(i)); - } - --static struct syscore_ops vf610_clk_syscore_ops = { -+static const struct syscore_ops vf610_clk_syscore_ops = { - .suspend = vf610_clk_suspend, - .resume = vf610_clk_resume, - }; - -+static struct syscore vf610_clk_syscore = { -+ .ops = &vf610_clk_syscore_ops, -+}; -+ - static void __init vf610_clocks_init(struct device_node *ccm_node) - { - struct device_node *np; -@@ -462,7 +466,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clk[clks_init_on[i]]); - -- register_syscore_ops(&vf610_clk_syscore_ops); -+ register_syscore(&vf610_clk_syscore); - - /* Add the clocks to provider list */ - clk_data.clks = clk; -diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c -index 590e9c85cb25..94cee44c854f 100644 ---- a/drivers/clk/ingenic/jz4725b-cgu.c -+++ b/drivers/clk/ingenic/jz4725b-cgu.c -@@ -268,6 +268,6 @@ static void __init jz4725b_cgu_init(struct device_node *np) - if (retval) - pr_err("%s: failed to register CGU Clocks\n", __func__); - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init); -diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c -index 3e0a30574ebb..2def3aedc8dd 100644 ---- a/drivers/clk/ingenic/jz4740-cgu.c -+++ b/drivers/clk/ingenic/jz4740-cgu.c -@@ -266,6 +266,6 @@ static void __init jz4740_cgu_init(struct device_node *np) - if (retval) - pr_err("%s: failed to register CGU Clocks\n", __func__); - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init); -diff --git a/drivers/clk/ingenic/jz4755-cgu.c b/drivers/clk/ingenic/jz4755-cgu.c -index f2c2d848dab7..17cf5dcaece9 100644 ---- a/drivers/clk/ingenic/jz4755-cgu.c -+++ b/drivers/clk/ingenic/jz4755-cgu.c -@@ -337,7 +337,7 @@ static void __init jz4755_cgu_init(struct device_node *np) - if (retval) - pr_err("%s: failed to register CGU Clocks\n", __func__); - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - /* - * CGU has some children devices, this is useful for probing children devices -diff --git a/drivers/clk/ingenic/jz4760-cgu.c b/drivers/clk/ingenic/jz4760-cgu.c -index e407f00bd594..372fe4b07992 100644 ---- a/drivers/clk/ingenic/jz4760-cgu.c -+++ b/drivers/clk/ingenic/jz4760-cgu.c -@@ -436,7 +436,7 @@ static void __init jz4760_cgu_init(struct device_node *np) - if (retval) - pr_err("%s: failed to register CGU Clocks\n", __func__); - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - - /* We only probe via devicetree, no need for a platform driver */ -diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c -index 6ae1740367f9..58f1d3bad677 100644 ---- a/drivers/clk/ingenic/jz4770-cgu.c -+++ b/drivers/clk/ingenic/jz4770-cgu.c -@@ -456,7 +456,7 @@ static void __init jz4770_cgu_init(struct device_node *np) - if (retval) - pr_err("%s: failed to register CGU Clocks\n", __func__); - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - - /* We only probe via devicetree, no need for a platform driver */ -diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c -index 07e2f3c5c454..1e88aef7ac0f 100644 ---- a/drivers/clk/ingenic/jz4780-cgu.c -+++ b/drivers/clk/ingenic/jz4780-cgu.c -@@ -803,6 +803,6 @@ static void __init jz4780_cgu_init(struct device_node *np) - return; - } - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init); -diff --git a/drivers/clk/ingenic/pm.c b/drivers/clk/ingenic/pm.c -index 341752b640d2..206d5cf2872f 100644 ---- a/drivers/clk/ingenic/pm.c -+++ b/drivers/clk/ingenic/pm.c -@@ -15,7 +15,7 @@ - - static void __iomem * __maybe_unused ingenic_cgu_base; - --static int __maybe_unused ingenic_cgu_pm_suspend(void) -+static int __maybe_unused ingenic_cgu_pm_suspend(void *data) - { - u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); - -@@ -24,22 +24,26 @@ static int __maybe_unused ingenic_cgu_pm_suspend(void) - return 0; - } - --static void __maybe_unused ingenic_cgu_pm_resume(void) -+static void __maybe_unused ingenic_cgu_pm_resume(void *data) - { - u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); - - writel(val & ~LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR); - } - --static struct syscore_ops __maybe_unused ingenic_cgu_pm_ops = { -+static const struct syscore_ops __maybe_unused ingenic_cgu_pm_ops = { - .suspend = ingenic_cgu_pm_suspend, - .resume = ingenic_cgu_pm_resume, - }; - --void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu) -+static struct syscore __maybe_unused ingenic_cgu_pm = { -+ .ops = &ingenic_cgu_pm_ops, -+}; -+ -+void ingenic_cgu_register_syscore(struct ingenic_cgu *cgu) - { - if (IS_ENABLED(CONFIG_PM_SLEEP)) { - ingenic_cgu_base = cgu->base; -- register_syscore_ops(&ingenic_cgu_pm_ops); -+ register_syscore(&ingenic_cgu_pm); - } - } -diff --git a/drivers/clk/ingenic/pm.h b/drivers/clk/ingenic/pm.h -index fa7540407b6b..0dcb57dc64cb 100644 ---- a/drivers/clk/ingenic/pm.h -+++ b/drivers/clk/ingenic/pm.h -@@ -7,6 +7,6 @@ - - struct ingenic_cgu; - --void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu); -+void ingenic_cgu_register_syscore(struct ingenic_cgu *cgu); - - #endif /* DRIVERS_CLK_INGENIC_PM_H */ -diff --git a/drivers/clk/ingenic/tcu.c b/drivers/clk/ingenic/tcu.c -index 7d04ef40b7cf..bc6a51da2072 100644 ---- a/drivers/clk/ingenic/tcu.c -+++ b/drivers/clk/ingenic/tcu.c -@@ -455,7 +455,7 @@ static int __init ingenic_tcu_probe(struct device_node *np) - return ret; - } - --static int __maybe_unused tcu_pm_suspend(void) -+static int __maybe_unused tcu_pm_suspend(void *data) - { - struct ingenic_tcu *tcu = ingenic_tcu; - -@@ -465,7 +465,7 @@ static int __maybe_unused tcu_pm_suspend(void) - return 0; - } - --static void __maybe_unused tcu_pm_resume(void) -+static void __maybe_unused tcu_pm_resume(void *data) - { - struct ingenic_tcu *tcu = ingenic_tcu; - -@@ -473,11 +473,15 @@ static void __maybe_unused tcu_pm_resume(void) - clk_enable(tcu->clk); - } - --static struct syscore_ops __maybe_unused tcu_pm_ops = { -+static const struct syscore_ops __maybe_unused tcu_pm_ops = { - .suspend = tcu_pm_suspend, - .resume = tcu_pm_resume, - }; - -+static struct syscore __maybe_unused tcu_pm = { -+ .ops = &tcu_pm_ops, -+}; -+ - static void __init ingenic_tcu_init(struct device_node *np) - { - int ret = ingenic_tcu_probe(np); -@@ -486,7 +490,7 @@ static void __init ingenic_tcu_init(struct device_node *np) - pr_crit("Failed to initialize TCU clocks: %d\n", ret); - - if (IS_ENABLED(CONFIG_PM_SLEEP)) -- register_syscore_ops(&tcu_pm_ops); -+ register_syscore(&tcu_pm); - } - - CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init); -diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c -index d80886caf393..d89bdfb7c219 100644 ---- a/drivers/clk/ingenic/x1000-cgu.c -+++ b/drivers/clk/ingenic/x1000-cgu.c -@@ -556,7 +556,7 @@ static void __init x1000_cgu_init(struct device_node *np) - return; - } - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - /* - * CGU has some children devices, this is useful for probing children devices -diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c -index 0fd46e50a513..acf856e5009e 100644 ---- a/drivers/clk/ingenic/x1830-cgu.c -+++ b/drivers/clk/ingenic/x1830-cgu.c -@@ -463,7 +463,7 @@ static void __init x1830_cgu_init(struct device_node *np) - return; - } - -- ingenic_cgu_register_syscore_ops(cgu); -+ ingenic_cgu_register_syscore(cgu); - } - /* - * CGU has some children devices, this is useful for probing children devices -diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c -index 785dbede4835..5adbbd91a6db 100644 ---- a/drivers/clk/mvebu/common.c -+++ b/drivers/clk/mvebu/common.c -@@ -215,22 +215,26 @@ static struct clk *clk_gating_get_src( - return ERR_PTR(-ENODEV); - } - --static int mvebu_clk_gating_suspend(void) -+static int mvebu_clk_gating_suspend(void *data) - { - ctrl->saved_reg = readl(ctrl->base); - return 0; - } - --static void mvebu_clk_gating_resume(void) -+static void mvebu_clk_gating_resume(void *data) - { - writel(ctrl->saved_reg, ctrl->base); - } - --static struct syscore_ops clk_gate_syscore_ops = { -+static const struct syscore_ops clk_gate_syscore_ops = { - .suspend = mvebu_clk_gating_suspend, - .resume = mvebu_clk_gating_resume, - }; - -+static struct syscore clk_gate_syscore = { -+ .ops = &clk_gate_syscore_ops, -+}; -+ - void __init mvebu_clk_gating_setup(struct device_node *np, - const struct clk_gating_soc_desc *desc) - { -@@ -284,7 +288,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, - - of_clk_add_provider(np, clk_gating_get_src, ctrl); - -- register_syscore_ops(&clk_gate_syscore_ops); -+ register_syscore(&clk_gate_syscore); - - return; - gates_out: -diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 0a1e017df7c6..9cf3e1e43b78 100644 ---- a/drivers/clk/rockchip/clk-rk3288.c -+++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -871,7 +871,7 @@ static const int rk3288_saved_cru_reg_ids[] = { - - static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)]; - --static int rk3288_clk_suspend(void) -+static int rk3288_clk_suspend(void *data) - { - int i, reg_id; - -@@ -906,7 +906,7 @@ static int rk3288_clk_suspend(void) - return 0; - } - --static void rk3288_clk_resume(void) -+static void rk3288_clk_resume(void *data) - { - int i, reg_id; - -@@ -923,11 +923,15 @@ static void rk3288_clk_shutdown(void) - writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON); - } - --static struct syscore_ops rk3288_clk_syscore_ops = { -+static const struct syscore_ops rk3288_clk_syscore_ops = { - .suspend = rk3288_clk_suspend, - .resume = rk3288_clk_resume, - }; - -+static struct syscore rk3288_clk_syscore = { -+ .ops = &rk3288_clk_syscore_ops, -+}; -+ - static void __init rk3288_common_init(struct device_node *np, - enum rk3288_variant soc) - { -@@ -976,7 +980,7 @@ static void __init rk3288_common_init(struct device_node *np, - - rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST, - rk3288_clk_shutdown); -- register_syscore_ops(&rk3288_clk_syscore_ops); -+ register_syscore(&rk3288_clk_syscore); - - rockchip_clk_of_add_provider(np, ctx); - } -diff --git a/drivers/clk/samsung/clk-s5pv210-audss.c b/drivers/clk/samsung/clk-s5pv210-audss.c -index b1fd8fac3a4c..c9fcb23de183 100644 ---- a/drivers/clk/samsung/clk-s5pv210-audss.c -+++ b/drivers/clk/samsung/clk-s5pv210-audss.c -@@ -36,7 +36,7 @@ static unsigned long reg_save[][2] = { - {ASS_CLK_GATE, 0}, - }; - --static int s5pv210_audss_clk_suspend(void) -+static int s5pv210_audss_clk_suspend(void *data) - { - int i; - -@@ -46,7 +46,7 @@ static int s5pv210_audss_clk_suspend(void) - return 0; - } - --static void s5pv210_audss_clk_resume(void) -+static void s5pv210_audss_clk_resume(void *data) - { - int i; - -@@ -54,10 +54,14 @@ static void s5pv210_audss_clk_resume(void) - writel(reg_save[i][1], reg_base + reg_save[i][0]); - } - --static struct syscore_ops s5pv210_audss_clk_syscore_ops = { -+static const struct syscore_ops s5pv210_audss_clk_syscore_ops = { - .suspend = s5pv210_audss_clk_suspend, - .resume = s5pv210_audss_clk_resume, - }; -+ -+static struct syscore s5pv210_audss_clk_syscore = { -+ .ops = &s5pv210_audss_clk_syscore_ops, -+}; - #endif /* CONFIG_PM_SLEEP */ - - /* register s5pv210_audss clocks */ -@@ -175,7 +179,7 @@ static int s5pv210_audss_clk_probe(struct platform_device *pdev) - } - - #ifdef CONFIG_PM_SLEEP -- register_syscore_ops(&s5pv210_audss_clk_syscore_ops); -+ register_syscore(&s5pv210_audss_clk_syscore); - #endif - - return 0; -diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c -index dbc9925ca8f4..c149ca6c2217 100644 ---- a/drivers/clk/samsung/clk.c -+++ b/drivers/clk/samsung/clk.c -@@ -271,7 +271,7 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, - } - - #ifdef CONFIG_PM_SLEEP --static int samsung_clk_suspend(void) -+static int samsung_clk_suspend(void *data) - { - struct samsung_clock_reg_cache *reg_cache; - -@@ -284,7 +284,7 @@ static int samsung_clk_suspend(void) - return 0; - } - --static void samsung_clk_resume(void) -+static void samsung_clk_resume(void *data) - { - struct samsung_clock_reg_cache *reg_cache; - -@@ -293,11 +293,15 @@ static void samsung_clk_resume(void) - reg_cache->rd_num); - } - --static struct syscore_ops samsung_clk_syscore_ops = { -+static const struct syscore_ops samsung_clk_syscore_ops = { - .suspend = samsung_clk_suspend, - .resume = samsung_clk_resume, - }; - -+static struct syscore samsung_clk_syscore = { -+ .ops = &samsung_clk_syscore_ops, -+}; -+ - void samsung_clk_extended_sleep_init(void __iomem *reg_base, - const unsigned long *rdump, - unsigned long nr_rdump, -@@ -316,7 +320,7 @@ void samsung_clk_extended_sleep_init(void __iomem *reg_base, - panic("could not allocate register dump storage.\n"); - - if (list_empty(&clock_reg_cache_list)) -- register_syscore_ops(&samsung_clk_syscore_ops); -+ register_syscore(&samsung_clk_syscore); - - reg_cache->reg_base = reg_base; - reg_cache->rd_num = nr_rdump; -diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c -index 412902f573b5..504d0ea997a5 100644 ---- a/drivers/clk/tegra/clk-tegra210.c -+++ b/drivers/clk/tegra/clk-tegra210.c -@@ -3444,7 +3444,7 @@ static void tegra210_disable_cpu_clock(u32 cpu) - static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx; - static u32 cpu_softrst_ctx[3]; - --static int tegra210_clk_suspend(void) -+static int tegra210_clk_suspend(void *data) - { - unsigned int i; - -@@ -3465,7 +3465,7 @@ static int tegra210_clk_suspend(void) - return 0; - } - --static void tegra210_clk_resume(void) -+static void tegra210_clk_resume(void *data) - { - unsigned int i; - -@@ -3523,13 +3523,17 @@ static void tegra210_cpu_clock_resume(void) - } - #endif - --static struct syscore_ops tegra_clk_syscore_ops = { -+static const struct syscore_ops tegra_clk_syscore_ops = { - #ifdef CONFIG_PM_SLEEP - .suspend = tegra210_clk_suspend, - .resume = tegra210_clk_resume, - #endif - }; - -+static struct syscore tegra_clk_syscore = { -+ .ops = &tegra_clk_syscore_ops, -+}; -+ - static struct tegra_cpu_car_ops tegra210_cpu_car_ops = { - .wait_for_reset = tegra210_wait_cpu_in_reset, - .disable_clock = tegra210_disable_cpu_clock, -@@ -3813,6 +3817,6 @@ static void __init tegra210_clock_init(struct device_node *np) - - tegra_cpu_car_ops = &tegra210_cpu_car_ops; - -- register_syscore_ops(&tegra_clk_syscore_ops); -+ register_syscore(&tegra_clk_syscore); - } - CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); -diff --git a/drivers/clocksource/timer-armada-370-xp.c b/drivers/clocksource/timer-armada-370-xp.c -index 54284c1c0651..f2b4cc40db93 100644 ---- a/drivers/clocksource/timer-armada-370-xp.c -+++ b/drivers/clocksource/timer-armada-370-xp.c -@@ -207,14 +207,14 @@ static int armada_370_xp_timer_dying_cpu(unsigned int cpu) - - static u32 timer0_ctrl_reg, timer0_local_ctrl_reg; - --static int armada_370_xp_timer_suspend(void) -+static int armada_370_xp_timer_suspend(void *data) - { - timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF); - timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF); - return 0; - } - --static void armada_370_xp_timer_resume(void) -+static void armada_370_xp_timer_resume(void *data) - { - writel(0xffffffff, timer_base + TIMER0_VAL_OFF); - writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); -@@ -222,11 +222,15 @@ static void armada_370_xp_timer_resume(void) - writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF); - } - --static struct syscore_ops armada_370_xp_timer_syscore_ops = { -+static const struct syscore_ops armada_370_xp_timer_syscore_ops = { - .suspend = armada_370_xp_timer_suspend, - .resume = armada_370_xp_timer_resume, - }; - -+static struct syscore armada_370_xp_timer_syscore = { -+ .ops = &armada_370_xp_timer_syscore_ops, -+}; -+ - static unsigned long armada_370_delay_timer_read(void) - { - return ~readl(timer_base + TIMER0_VAL_OFF); -@@ -324,7 +328,7 @@ static int __init armada_370_xp_timer_common_init(struct device_node *np) - return res; - } - -- register_syscore_ops(&armada_370_xp_timer_syscore_ops); -+ register_syscore(&armada_370_xp_timer_syscore); - - return 0; - } -diff --git a/drivers/cpuidle/cpuidle-psci.c b/drivers/cpuidle/cpuidle-psci.c -index b19bc60cc627..3372e1f90561 100644 ---- a/drivers/cpuidle/cpuidle-psci.c -+++ b/drivers/cpuidle/cpuidle-psci.c -@@ -177,26 +177,30 @@ static void psci_idle_syscore_switch(bool suspend) - } - } - --static int psci_idle_syscore_suspend(void) -+static int psci_idle_syscore_suspend(void *data) - { - psci_idle_syscore_switch(true); - return 0; - } - --static void psci_idle_syscore_resume(void) -+static void psci_idle_syscore_resume(void *data) - { - psci_idle_syscore_switch(false); - } - --static struct syscore_ops psci_idle_syscore_ops = { -+static const struct syscore_ops psci_idle_syscore_ops = { - .suspend = psci_idle_syscore_suspend, - .resume = psci_idle_syscore_resume, - }; - -+static struct syscore psci_idle_syscore = { -+ .ops = &psci_idle_syscore_ops, -+}; -+ - static void psci_idle_init_syscore(void) - { - if (psci_cpuidle_use_syscore) -- register_syscore_ops(&psci_idle_syscore_ops); -+ register_syscore(&psci_idle_syscore); - } - - static void psci_idle_init_cpuhp(void) -diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c -index 441ba95b38cf..647b6f4861b7 100644 ---- a/drivers/gpio/gpio-mxc.c -+++ b/drivers/gpio/gpio-mxc.c -@@ -675,7 +675,7 @@ static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { - RUNTIME_PM_OPS(mxc_gpio_runtime_suspend, mxc_gpio_runtime_resume, NULL) - }; - --static int mxc_gpio_syscore_suspend(void) -+static int mxc_gpio_syscore_suspend(void *data) - { - struct mxc_gpio_port *port; - int ret; -@@ -692,7 +692,7 @@ static int mxc_gpio_syscore_suspend(void) - return 0; - } - --static void mxc_gpio_syscore_resume(void) -+static void mxc_gpio_syscore_resume(void *data) - { - struct mxc_gpio_port *port; - int ret; -@@ -709,11 +709,15 @@ static void mxc_gpio_syscore_resume(void) - } - } - --static struct syscore_ops mxc_gpio_syscore_ops = { -+static const struct syscore_ops mxc_gpio_syscore_ops = { - .suspend = mxc_gpio_syscore_suspend, - .resume = mxc_gpio_syscore_resume, - }; - -+static struct syscore mxc_gpio_syscore = { -+ .ops = &mxc_gpio_syscore_ops, -+}; -+ - static struct platform_driver mxc_gpio_driver = { - .driver = { - .name = "gpio-mxc", -@@ -726,7 +730,7 @@ static struct platform_driver mxc_gpio_driver = { - - static int __init gpio_mxc_init(void) - { -- register_syscore_ops(&mxc_gpio_syscore_ops); -+ register_syscore(&mxc_gpio_syscore); - - return platform_driver_register(&mxc_gpio_driver); - } -diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c -index fa22f3faa163..664cf1eef494 100644 ---- a/drivers/gpio/gpio-pxa.c -+++ b/drivers/gpio/gpio-pxa.c -@@ -747,7 +747,7 @@ static int __init pxa_gpio_dt_init(void) - device_initcall(pxa_gpio_dt_init); - - #ifdef CONFIG_PM --static int pxa_gpio_suspend(void) -+static int pxa_gpio_suspend(void *data) - { - struct pxa_gpio_chip *pchip = pxa_gpio_chip; - struct pxa_gpio_bank *c; -@@ -768,7 +768,7 @@ static int pxa_gpio_suspend(void) - return 0; - } - --static void pxa_gpio_resume(void) -+static void pxa_gpio_resume(void *data) - { - struct pxa_gpio_chip *pchip = pxa_gpio_chip; - struct pxa_gpio_bank *c; -@@ -792,14 +792,18 @@ static void pxa_gpio_resume(void) - #define pxa_gpio_resume NULL - #endif - --static struct syscore_ops pxa_gpio_syscore_ops = { -+static const struct syscore_ops pxa_gpio_syscore_ops = { - .suspend = pxa_gpio_suspend, - .resume = pxa_gpio_resume, - }; - -+static struct syscore pxa_gpio_syscore = { -+ .ops = &pxa_gpio_syscore_ops, -+}; -+ - static int __init pxa_gpio_sysinit(void) - { -- register_syscore_ops(&pxa_gpio_syscore_ops); -+ register_syscore(&pxa_gpio_syscore); - return 0; - } - postcore_initcall(pxa_gpio_sysinit); -diff --git a/drivers/gpio/gpio-sa1100.c b/drivers/gpio/gpio-sa1100.c -index 7f6a62f5d1ee..1938ffa2f4f3 100644 ---- a/drivers/gpio/gpio-sa1100.c -+++ b/drivers/gpio/gpio-sa1100.c -@@ -256,7 +256,7 @@ static void sa1100_gpio_handler(struct irq_desc *desc) - } while (mask); - } - --static int sa1100_gpio_suspend(void) -+static int sa1100_gpio_suspend(void *data) - { - struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip; - -@@ -275,19 +275,23 @@ static int sa1100_gpio_suspend(void) - return 0; - } - --static void sa1100_gpio_resume(void) -+static void sa1100_gpio_resume(void *data) - { - sa1100_update_edge_regs(&sa1100_gpio_chip); - } - --static struct syscore_ops sa1100_gpio_syscore_ops = { -+static const struct syscore_ops sa1100_gpio_syscore_ops = { - .suspend = sa1100_gpio_suspend, - .resume = sa1100_gpio_resume, - }; - -+static struct syscore sa1100_gpio_syscore = { -+ .ops = &sa1100_gpio_syscore_ops, -+}; -+ - static int __init sa1100_gpio_init_devicefs(void) - { -- register_syscore_ops(&sa1100_gpio_syscore_ops); -+ register_syscore(&sa1100_gpio_syscore); - return 0; - } - -diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c -index 3ab62277b6be..7000e2a5511f 100644 ---- a/drivers/hv/vmbus_drv.c -+++ b/drivers/hv/vmbus_drv.c -@@ -2861,7 +2861,7 @@ static void hv_crash_handler(struct pt_regs *regs) - hv_synic_disable_regs(cpu); - }; - --static int hv_synic_suspend(void) -+static int hv_synic_suspend(void *data) - { - /* - * When we reach here, all the non-boot CPUs have been offlined. -@@ -2888,7 +2888,7 @@ static int hv_synic_suspend(void) - return 0; - } - --static void hv_synic_resume(void) -+static void hv_synic_resume(void *data) - { - hv_synic_enable_regs(0); - -@@ -2900,11 +2900,15 @@ static void hv_synic_resume(void) - } - - /* The callbacks run only on CPU0, with irqs_disabled. */ --static struct syscore_ops hv_synic_syscore_ops = { -+static const struct syscore_ops hv_synic_syscore_ops = { - .suspend = hv_synic_suspend, - .resume = hv_synic_resume, - }; - -+static struct syscore hv_synic_syscore = { -+ .ops = &hv_synic_syscore_ops, -+}; -+ - static int __init hv_acpi_init(void) - { - int ret; -@@ -2947,7 +2951,7 @@ static int __init hv_acpi_init(void) - hv_setup_kexec_handler(hv_kexec_handler); - hv_setup_crash_handler(hv_crash_handler); - -- register_syscore_ops(&hv_synic_syscore_ops); -+ register_syscore(&hv_synic_syscore); - - return 0; - -@@ -2961,7 +2965,7 @@ static void __exit vmbus_exit(void) - { - int cpu; - -- unregister_syscore_ops(&hv_synic_syscore_ops); -+ unregister_syscore(&hv_synic_syscore); - - hv_remove_kexec_handler(); - hv_remove_crash_handler(); -diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c -index 76efd74124b3..4aa09660804b 100644 ---- a/drivers/iommu/amd/init.c -+++ b/drivers/iommu/amd/init.c -@@ -3050,7 +3050,7 @@ static void disable_iommus(void) - * disable suspend until real resume implemented - */ - --static void amd_iommu_resume(void) -+static void amd_iommu_resume(void *data) - { - struct amd_iommu *iommu; - -@@ -3064,7 +3064,7 @@ static void amd_iommu_resume(void) - amd_iommu_enable_interrupts(); - } - --static int amd_iommu_suspend(void) -+static int amd_iommu_suspend(void *data) - { - /* disable IOMMUs to go out of the way for BIOS */ - disable_iommus(); -@@ -3072,11 +3072,15 @@ static int amd_iommu_suspend(void) - return 0; - } - --static struct syscore_ops amd_iommu_syscore_ops = { -+static const struct syscore_ops amd_iommu_syscore_ops = { - .suspend = amd_iommu_suspend, - .resume = amd_iommu_resume, - }; - -+static struct syscore amd_iommu_syscore = { -+ .ops = &amd_iommu_syscore_ops, -+}; -+ - static void __init free_iommu_resources(void) - { - free_iommu_all(); -@@ -3421,7 +3425,7 @@ static int __init state_next(void) - init_state = IOMMU_ENABLED; - break; - case IOMMU_ENABLED: -- register_syscore_ops(&amd_iommu_syscore_ops); -+ register_syscore(&amd_iommu_syscore); - iommu_snp_enable(); - ret = amd_iommu_init_pci(); - init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT; -@@ -3524,12 +3528,12 @@ int __init amd_iommu_enable(void) - - void amd_iommu_disable(void) - { -- amd_iommu_suspend(); -+ amd_iommu_suspend(NULL); - } - - int amd_iommu_reenable(int mode) - { -- amd_iommu_resume(); -+ amd_iommu_resume(NULL); - - return 0; - } -diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c -index 79676188f60f..3d1cacad559b 100644 ---- a/drivers/iommu/intel/iommu.c -+++ b/drivers/iommu/intel/iommu.c -@@ -2305,7 +2305,7 @@ static void iommu_flush_all(void) - } - } - --static int iommu_suspend(void) -+static int iommu_suspend(void *data) - { - struct dmar_drhd_unit *drhd; - struct intel_iommu *iommu = NULL; -@@ -2332,7 +2332,7 @@ static int iommu_suspend(void) - return 0; - } - --static void iommu_resume(void) -+static void iommu_resume(void *data) - { - struct dmar_drhd_unit *drhd; - struct intel_iommu *iommu = NULL; -@@ -2363,14 +2363,18 @@ static void iommu_resume(void) - } - } - --static struct syscore_ops iommu_syscore_ops = { -+static const struct syscore_ops iommu_syscore_ops = { - .resume = iommu_resume, - .suspend = iommu_suspend, - }; - -+static struct syscore iommu_syscore = { -+ .ops = &iommu_syscore_ops, -+}; -+ - static void __init init_iommu_pm_ops(void) - { -- register_syscore_ops(&iommu_syscore_ops); -+ register_syscore(&iommu_syscore); - } - - #else -diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c -index e7dfcf0cda43..495848442b35 100644 ---- a/drivers/irqchip/exynos-combiner.c -+++ b/drivers/irqchip/exynos-combiner.c -@@ -200,12 +200,13 @@ static void __init combiner_init(void __iomem *combiner_base, - - /** - * combiner_suspend - save interrupt combiner state before suspend -+ * @data: syscore context - * - * Save the interrupt enable set register for all combiner groups since - * the state is lost when the system enters into a sleep state. - * - */ --static int combiner_suspend(void) -+static int combiner_suspend(void *data) - { - int i; - -@@ -218,12 +219,13 @@ static int combiner_suspend(void) - - /** - * combiner_resume - restore interrupt combiner state after resume -+ * @data: syscore context - * - * Restore the interrupt enable set register for all combiner groups since - * the state is lost when the system enters into a sleep state on suspend. - * - */ --static void combiner_resume(void) -+static void combiner_resume(void *data) - { - int i; - -@@ -240,11 +242,15 @@ static void combiner_resume(void) - #define combiner_resume NULL - #endif - --static struct syscore_ops combiner_syscore_ops = { -+static const struct syscore_ops combiner_syscore_ops = { - .suspend = combiner_suspend, - .resume = combiner_resume, - }; - -+static struct syscore combiner_syscore = { -+ .ops = &combiner_syscore_ops, -+}; -+ - static int __init combiner_of_init(struct device_node *np, - struct device_node *parent) - { -@@ -264,7 +270,7 @@ static int __init combiner_of_init(struct device_node *np, - - combiner_init(combiner_base, np); - -- register_syscore_ops(&combiner_syscore_ops); -+ register_syscore(&combiner_syscore); - - return 0; - } -diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c -index a44c49e985b7..a4d03a2d1569 100644 ---- a/drivers/irqchip/irq-armada-370-xp.c -+++ b/drivers/irqchip/irq-armada-370-xp.c -@@ -726,7 +726,7 @@ static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs) - } while (1); - } - --static int mpic_suspend(void) -+static int mpic_suspend(void *data) - { - struct mpic *mpic = mpic_data; - -@@ -735,7 +735,7 @@ static int mpic_suspend(void) - return 0; - } - --static void mpic_resume(void) -+static void mpic_resume(void *data) - { - struct mpic *mpic = mpic_data; - bool src0, src1; -@@ -788,11 +788,15 @@ static void mpic_resume(void) - mpic_ipi_resume(mpic); - } - --static struct syscore_ops mpic_syscore_ops = { -+static const struct syscore_ops mpic_syscore_ops = { - .suspend = mpic_suspend, - .resume = mpic_resume, - }; - -+static struct syscore mpic_syscore = { -+ .ops = &mpic_syscore_ops, -+}; -+ - static int __init mpic_map_region(struct device_node *np, int index, - void __iomem **base, phys_addr_t *phys_base) - { -@@ -905,7 +909,7 @@ static int __init mpic_of_init(struct device_node *node, struct device_node *par - mpic_handle_cascade_irq, mpic); - } - -- register_syscore_ops(&mpic_syscore_ops); -+ register_syscore(&mpic_syscore); - - return 0; - } -diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c -index 821b288587ca..674138668f1c 100644 ---- a/drivers/irqchip/irq-bcm7038-l1.c -+++ b/drivers/irqchip/irq-bcm7038-l1.c -@@ -291,7 +291,7 @@ static int bcm7038_l1_init_one(struct device_node *dn, unsigned int idx, - static LIST_HEAD(bcm7038_l1_intcs_list); - static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock); - --static int bcm7038_l1_suspend(void) -+static int bcm7038_l1_suspend(void *data) - { - struct bcm7038_l1_chip *intc; - int boot_cpu, word; -@@ -317,7 +317,7 @@ static int bcm7038_l1_suspend(void) - return 0; - } - --static void bcm7038_l1_resume(void) -+static void bcm7038_l1_resume(void *data) - { - struct bcm7038_l1_chip *intc; - int boot_cpu, word; -@@ -338,11 +338,15 @@ static void bcm7038_l1_resume(void) - } - } - --static struct syscore_ops bcm7038_l1_syscore_ops = { -+static const struct syscore_ops bcm7038_l1_syscore_ops = { - .suspend = bcm7038_l1_suspend, - .resume = bcm7038_l1_resume, - }; - -+static struct syscore bcm7038_l1_syscore = { -+ .ops = &bcm7038_l1_syscore_ops, -+}; -+ - static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on) - { - struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d); -@@ -430,7 +434,7 @@ static int bcm7038_l1_probe(struct platform_device *pdev, struct device_node *pa - raw_spin_unlock(&bcm7038_l1_intcs_lock); - - if (list_is_singular(&bcm7038_l1_intcs_list)) -- register_syscore_ops(&bcm7038_l1_syscore_ops); -+ register_syscore(&bcm7038_l1_syscore); - #endif - - pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n", -diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c -index 23158fc8d392..a51e8e6a8181 100644 ---- a/drivers/irqchip/irq-gic-v3-its.c -+++ b/drivers/irqchip/irq-gic-v3-its.c -@@ -4996,7 +4996,7 @@ static void its_enable_quirks(struct its_node *its) - its_quirks, its); - } - --static int its_save_disable(void) -+static int its_save_disable(void *data) - { - struct its_node *its; - int err = 0; -@@ -5032,7 +5032,7 @@ static int its_save_disable(void) - return err; - } - --static void its_restore_enable(void) -+static void its_restore_enable(void *data) - { - struct its_node *its; - int ret; -@@ -5092,11 +5092,15 @@ static void its_restore_enable(void) - raw_spin_unlock(&its_lock); - } - --static struct syscore_ops its_syscore_ops = { -+static const struct syscore_ops its_syscore_ops = { - .suspend = its_save_disable, - .resume = its_restore_enable, - }; - -+static struct syscore its_syscore = { -+ .ops = &its_syscore_ops, -+}; -+ - static void __init __iomem *its_map_one(struct resource *res, int *err) - { - void __iomem *its_base; -@@ -5868,7 +5872,7 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, - } - } - -- register_syscore_ops(&its_syscore_ops); -+ register_syscore(&its_syscore); - - return 0; - } -diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c -index 91b2f587119c..cca77f9948a3 100644 ---- a/drivers/irqchip/irq-i8259.c -+++ b/drivers/irqchip/irq-i8259.c -@@ -202,13 +202,13 @@ static void mask_and_ack_8259A(struct irq_data *d) - } - } - --static void i8259A_resume(void) -+static void i8259A_resume(void *data) - { - if (i8259A_auto_eoi >= 0) - init_8259A(i8259A_auto_eoi); - } - --static void i8259A_shutdown(void) -+static void i8259A_shutdown(void *data) - { - /* Put the i8259A into a quiescent state that - * the kernel initialization code can get it -@@ -220,11 +220,15 @@ static void i8259A_shutdown(void) - } - } - --static struct syscore_ops i8259_syscore_ops = { -+static const struct syscore_ops i8259_syscore_ops = { - .resume = i8259A_resume, - .shutdown = i8259A_shutdown, - }; - -+static struct syscore i8259_syscore = { -+ .ops = &i8259_syscore_ops, -+}; -+ - static void init_8259A(int auto_eoi) - { - unsigned long flags; -@@ -320,7 +324,7 @@ struct irq_domain * __init __init_i8259_irqs(struct device_node *node) - - if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL)) - pr_err("Failed to register cascade interrupt\n"); -- register_syscore_ops(&i8259_syscore_ops); -+ register_syscore(&i8259_syscore); - return domain; - } - -diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c -index b91f5c14b405..04f7ba0657be 100644 ---- a/drivers/irqchip/irq-imx-gpcv2.c -+++ b/drivers/irqchip/irq-imx-gpcv2.c -@@ -33,7 +33,7 @@ static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i) - return cd->gpc_base + cd->cpu2wakeup + i * 4; - } - --static int gpcv2_wakeup_source_save(void) -+static int gpcv2_wakeup_source_save(void *data) - { - struct gpcv2_irqchip_data *cd; - void __iomem *reg; -@@ -52,7 +52,7 @@ static int gpcv2_wakeup_source_save(void) - return 0; - } - --static void gpcv2_wakeup_source_restore(void) -+static void gpcv2_wakeup_source_restore(void *data) - { - struct gpcv2_irqchip_data *cd; - int i; -@@ -65,9 +65,13 @@ static void gpcv2_wakeup_source_restore(void) - writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i)); - } - --static struct syscore_ops imx_gpcv2_syscore_ops = { -- .suspend = gpcv2_wakeup_source_save, -- .resume = gpcv2_wakeup_source_restore, -+static const struct syscore_ops gpcv2_syscore_ops = { -+ .suspend = gpcv2_wakeup_source_save, -+ .resume = gpcv2_wakeup_source_restore, -+}; -+ -+static struct syscore gpcv2_syscore = { -+ .ops = &gpcv2_syscore_ops, - }; - - static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) -@@ -276,7 +280,7 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node, - writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup); - - imx_gpcv2_instance = cd; -- register_syscore_ops(&imx_gpcv2_syscore_ops); -+ register_syscore(&gpcv2_syscore); - - /* - * Clear the OF_POPULATED flag set in of_irq_init so that -diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c -index 39e5a72ccd3c..ad2105685b48 100644 ---- a/drivers/irqchip/irq-loongson-eiointc.c -+++ b/drivers/irqchip/irq-loongson-eiointc.c -@@ -407,21 +407,25 @@ static struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group - return NULL; - } - --static int eiointc_suspend(void) -+static int eiointc_suspend(void *data) - { - return 0; - } - --static void eiointc_resume(void) -+static void eiointc_resume(void *data) - { - eiointc_router_init(0); - } - --static struct syscore_ops eiointc_syscore_ops = { -+static const struct syscore_ops eiointc_syscore_ops = { - .suspend = eiointc_suspend, - .resume = eiointc_resume, - }; - -+static struct syscore eiointc_syscore = { -+ .ops = &eiointc_syscore_ops, -+}; -+ - static int __init pch_pic_parse_madt(union acpi_subtable_headers *header, - const unsigned long end) - { -@@ -540,7 +544,7 @@ static int __init eiointc_init(struct eiointc_priv *priv, int parent_irq, - eiointc_router_init(0); - - if (nr_pics == 1) { -- register_syscore_ops(&eiointc_syscore_ops); -+ register_syscore(&eiointc_syscore); - cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_EIOINTC_STARTING, - "irqchip/loongarch/eiointc:starting", - eiointc_router_init, NULL); -diff --git a/drivers/irqchip/irq-loongson-htpic.c b/drivers/irqchip/irq-loongson-htpic.c -index f4abdf156de7..1c691c4be989 100644 ---- a/drivers/irqchip/irq-loongson-htpic.c -+++ b/drivers/irqchip/irq-loongson-htpic.c -@@ -71,15 +71,19 @@ static void htpic_reg_init(void) - writel(0xffff, htpic->base + HTINT_EN_OFF); - } - --static void htpic_resume(void) -+static void htpic_resume(void *data) - { - htpic_reg_init(); - } - --struct syscore_ops htpic_syscore_ops = { -+static const struct syscore_ops htpic_syscore_ops = { - .resume = htpic_resume, - }; - -+static struct syscore htpic_syscore = { -+ .ops = &htpic_syscore_ops, -+}; -+ - static int __init htpic_of_init(struct device_node *node, struct device_node *parent) - { - unsigned int parent_irq[4]; -@@ -130,7 +134,7 @@ static int __init htpic_of_init(struct device_node *node, struct device_node *pa - htpic_irq_dispatch, htpic); - } - -- register_syscore_ops(&htpic_syscore_ops); -+ register_syscore(&htpic_syscore); - - return 0; - -diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c -index d8558eb35044..d2be8e954e92 100644 ---- a/drivers/irqchip/irq-loongson-htvec.c -+++ b/drivers/irqchip/irq-loongson-htvec.c -@@ -159,7 +159,7 @@ static void htvec_reset(struct htvec *priv) - } - } - --static int htvec_suspend(void) -+static int htvec_suspend(void *data) - { - int i; - -@@ -169,7 +169,7 @@ static int htvec_suspend(void) - return 0; - } - --static void htvec_resume(void) -+static void htvec_resume(void *data) - { - int i; - -@@ -177,11 +177,15 @@ static void htvec_resume(void) - writel(htvec_priv->saved_vec_en[i], htvec_priv->base + HTVEC_EN_OFF + 4 * i); - } - --static struct syscore_ops htvec_syscore_ops = { -+static const struct syscore_ops htvec_syscore_ops = { - .suspend = htvec_suspend, - .resume = htvec_resume, - }; - -+static struct syscore htvec_syscore = { -+ .ops = &htvec_syscore_ops, -+}; -+ - static int htvec_init(phys_addr_t addr, unsigned long size, - int num_parents, int parent_irq[], struct fwnode_handle *domain_handle) - { -@@ -214,7 +218,7 @@ static int htvec_init(phys_addr_t addr, unsigned long size, - - htvec_priv = priv; - -- register_syscore_ops(&htvec_syscore_ops); -+ register_syscore(&htvec_syscore); - - return 0; - -diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c -index 912bf50a5c7c..3a125f3e4287 100644 ---- a/drivers/irqchip/irq-loongson-pch-lpc.c -+++ b/drivers/irqchip/irq-loongson-pch-lpc.c -@@ -151,7 +151,7 @@ static int pch_lpc_disabled(struct pch_lpc *priv) - (readl(priv->base + LPC_INT_STS) == 0xffffffff); - } - --static int pch_lpc_suspend(void) -+static int pch_lpc_suspend(void *data) - { - pch_lpc_priv->saved_reg_ctl = readl(pch_lpc_priv->base + LPC_INT_CTL); - pch_lpc_priv->saved_reg_ena = readl(pch_lpc_priv->base + LPC_INT_ENA); -@@ -159,18 +159,22 @@ static int pch_lpc_suspend(void) - return 0; - } - --static void pch_lpc_resume(void) -+static void pch_lpc_resume(void *data) - { - writel(pch_lpc_priv->saved_reg_ctl, pch_lpc_priv->base + LPC_INT_CTL); - writel(pch_lpc_priv->saved_reg_ena, pch_lpc_priv->base + LPC_INT_ENA); - writel(pch_lpc_priv->saved_reg_pol, pch_lpc_priv->base + LPC_INT_POL); - } - --static struct syscore_ops pch_lpc_syscore_ops = { -+static const struct syscore_ops pch_lpc_syscore_ops = { - .suspend = pch_lpc_suspend, - .resume = pch_lpc_resume, - }; - -+static struct syscore pch_lpc_syscore = { -+ .ops = &pch_lpc_syscore_ops, -+}; -+ - int __init pch_lpc_acpi_init(struct irq_domain *parent, - struct acpi_madt_lpc_pic *acpi_pchlpc) - { -@@ -222,7 +226,7 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, - - pch_lpc_priv = priv; - pch_lpc_handle = irq_handle; -- register_syscore_ops(&pch_lpc_syscore_ops); -+ register_syscore(&pch_lpc_syscore); - - return 0; - -diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c -index 62e6bf3a0611..c6b369a974a7 100644 ---- a/drivers/irqchip/irq-loongson-pch-pic.c -+++ b/drivers/irqchip/irq-loongson-pch-pic.c -@@ -278,7 +278,7 @@ static void pch_pic_reset(struct pch_pic *priv) - } - } - --static int pch_pic_suspend(void) -+static int pch_pic_suspend(void *data) - { - int i, j; - -@@ -296,7 +296,7 @@ static int pch_pic_suspend(void) - return 0; - } - --static void pch_pic_resume(void) -+static void pch_pic_resume(void *data) - { - int i, j; - -@@ -313,11 +313,15 @@ static void pch_pic_resume(void) - } - } - --static struct syscore_ops pch_pic_syscore_ops = { -+static const struct syscore_ops pch_pic_syscore_ops = { - .suspend = pch_pic_suspend, - .resume = pch_pic_resume, - }; - -+static struct syscore pch_pic_syscore = { -+ .ops = &pch_pic_syscore_ops, -+}; -+ - static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base, - struct irq_domain *parent_domain, struct fwnode_handle *domain_handle, - u32 gsi_base) -@@ -356,7 +360,7 @@ static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base, - pch_pic_priv[nr_pics++] = priv; - - if (nr_pics == 1) -- register_syscore_ops(&pch_pic_syscore_ops); -+ register_syscore(&pch_pic_syscore); - - return 0; - -diff --git a/drivers/irqchip/irq-mchp-eic.c b/drivers/irqchip/irq-mchp-eic.c -index 979bb86929f8..31093a8ab67c 100644 ---- a/drivers/irqchip/irq-mchp-eic.c -+++ b/drivers/irqchip/irq-mchp-eic.c -@@ -109,7 +109,7 @@ static int mchp_eic_irq_set_wake(struct irq_data *d, unsigned int on) - return 0; - } - --static int mchp_eic_irq_suspend(void) -+static int mchp_eic_irq_suspend(void *data) - { - unsigned int hwirq; - -@@ -123,7 +123,7 @@ static int mchp_eic_irq_suspend(void) - return 0; - } - --static void mchp_eic_irq_resume(void) -+static void mchp_eic_irq_resume(void *data) - { - unsigned int hwirq; - -@@ -135,11 +135,15 @@ static void mchp_eic_irq_resume(void) - MCHP_EIC_SCFG(hwirq)); - } - --static struct syscore_ops mchp_eic_syscore_ops = { -+static const struct syscore_ops mchp_eic_syscore_ops = { - .suspend = mchp_eic_irq_suspend, - .resume = mchp_eic_irq_resume, - }; - -+static struct syscore mchp_eic_syscore = { -+ .ops = &mchp_eic_syscore_ops, -+}; -+ - static struct irq_chip mchp_eic_chip = { - .name = "eic", - .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED, -@@ -258,7 +262,7 @@ static int mchp_eic_probe(struct platform_device *pdev, struct device_node *pare - goto clk_unprepare; - } - -- register_syscore_ops(&mchp_eic_syscore_ops); -+ register_syscore(&mchp_eic_syscore); - - pr_info("%pOF: EIC registered, nr_irqs %u\n", node, MCHP_EIC_NIRQ); - -diff --git a/drivers/irqchip/irq-mst-intc.c b/drivers/irqchip/irq-mst-intc.c -index 9643cc3a77d7..7f760f555a76 100644 ---- a/drivers/irqchip/irq-mst-intc.c -+++ b/drivers/irqchip/irq-mst-intc.c -@@ -143,7 +143,7 @@ static void mst_intc_polarity_restore(struct mst_intc_chip_data *cd) - writew_relaxed(cd->saved_polarity_conf[i], addr + i * 4); - } - --static void mst_irq_resume(void) -+static void mst_irq_resume(void *data) - { - struct mst_intc_chip_data *cd; - -@@ -151,7 +151,7 @@ static void mst_irq_resume(void) - mst_intc_polarity_restore(cd); - } - --static int mst_irq_suspend(void) -+static int mst_irq_suspend(void *data) - { - struct mst_intc_chip_data *cd; - -@@ -160,14 +160,18 @@ static int mst_irq_suspend(void) - return 0; - } - --static struct syscore_ops mst_irq_syscore_ops = { -+static const struct syscore_ops mst_irq_syscore_ops = { - .suspend = mst_irq_suspend, - .resume = mst_irq_resume, - }; - -+static struct syscore mst_irq_syscore = { -+ .ops = &mst_irq_syscore_ops, -+}; -+ - static int __init mst_irq_pm_init(void) - { -- register_syscore_ops(&mst_irq_syscore_ops); -+ register_syscore(&mst_irq_syscore); - return 0; - } - late_initcall(mst_irq_pm_init); -diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c -index de481ba340f8..9571f622774e 100644 ---- a/drivers/irqchip/irq-mtk-cirq.c -+++ b/drivers/irqchip/irq-mtk-cirq.c -@@ -199,7 +199,7 @@ static const struct irq_domain_ops cirq_domain_ops = { - }; - - #ifdef CONFIG_PM_SLEEP --static int mtk_cirq_suspend(void) -+static int mtk_cirq_suspend(void *data) - { - void __iomem *reg; - u32 value, mask; -@@ -257,7 +257,7 @@ static int mtk_cirq_suspend(void) - return 0; - } - --static void mtk_cirq_resume(void) -+static void mtk_cirq_resume(void *data) - { - void __iomem *reg = mtk_cirq_reg(cirq_data, CIRQ_CONTROL); - u32 value; -@@ -272,14 +272,18 @@ static void mtk_cirq_resume(void) - writel_relaxed(value, reg); - } - --static struct syscore_ops mtk_cirq_syscore_ops = { -+static const struct syscore_ops mtk_cirq_syscore_ops = { - .suspend = mtk_cirq_suspend, - .resume = mtk_cirq_resume, - }; - -+static struct syscore mtk_cirq_syscore = { -+ .ops = &mtk_cirq_syscore_ops, -+}; -+ - static void mtk_cirq_syscore_init(void) - { -- register_syscore_ops(&mtk_cirq_syscore_ops); -+ register_syscore(&mtk_cirq_syscore); - } - #else - static inline void mtk_cirq_syscore_init(void) {} -diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c -index c938ab159289..eb01d4c5aca7 100644 ---- a/drivers/irqchip/irq-renesas-rzg2l.c -+++ b/drivers/irqchip/irq-renesas-rzg2l.c -@@ -398,7 +398,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) - return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); - } - --static int rzg2l_irqc_irq_suspend(void) -+static int rzg2l_irqc_irq_suspend(void *data) - { - struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; - void __iomem *base = rzg2l_irqc_data->base; -@@ -410,7 +410,7 @@ static int rzg2l_irqc_irq_suspend(void) - return 0; - } - --static void rzg2l_irqc_irq_resume(void) -+static void rzg2l_irqc_irq_resume(void *data) - { - struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; - void __iomem *base = rzg2l_irqc_data->base; -@@ -425,11 +425,15 @@ static void rzg2l_irqc_irq_resume(void) - writel_relaxed(cache->iitsr, base + IITSR); - } - --static struct syscore_ops rzg2l_irqc_syscore_ops = { -+static const struct syscore_ops rzg2l_irqc_syscore_ops = { - .suspend = rzg2l_irqc_irq_suspend, - .resume = rzg2l_irqc_irq_resume, - }; - -+static struct syscore rzg2l_irqc_syscore = { -+ .ops = &rzg2l_irqc_syscore_ops, -+}; -+ - static const struct irq_chip rzg2l_irqc_chip = { - .name = "rzg2l-irqc", - .irq_eoi = rzg2l_irqc_eoi, -@@ -577,7 +581,7 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n - return -ENOMEM; - } - -- register_syscore_ops(&rzg2l_irqc_syscore_ops); -+ register_syscore(&rzg2l_irqc_syscore); - - return 0; - } -diff --git a/drivers/irqchip/irq-sa11x0.c b/drivers/irqchip/irq-sa11x0.c -index d8d4dff16276..e5f24c5f3f41 100644 ---- a/drivers/irqchip/irq-sa11x0.c -+++ b/drivers/irqchip/irq-sa11x0.c -@@ -85,7 +85,7 @@ static struct sa1100irq_state { - unsigned int iccr; - } sa1100irq_state; - --static int sa1100irq_suspend(void) -+static int sa1100irq_suspend(void *data) - { - struct sa1100irq_state *st = &sa1100irq_state; - -@@ -102,7 +102,7 @@ static int sa1100irq_suspend(void) - return 0; - } - --static void sa1100irq_resume(void) -+static void sa1100irq_resume(void *data) - { - struct sa1100irq_state *st = &sa1100irq_state; - -@@ -114,14 +114,18 @@ static void sa1100irq_resume(void) - } - } - --static struct syscore_ops sa1100irq_syscore_ops = { -+static const struct syscore_ops sa1100irq_syscore_ops = { - .suspend = sa1100irq_suspend, - .resume = sa1100irq_resume, - }; - -+static struct syscore sa1100irq_syscore = { -+ .ops = &sa1100irq_syscore_ops, -+}; -+ - static int __init sa1100irq_init_devicefs(void) - { -- register_syscore_ops(&sa1100irq_syscore_ops); -+ register_syscore(&sa1100irq_syscore); - return 0; - } - -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index f255fa044764..70058871d2fb 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -268,7 +268,7 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type) - return IRQ_SET_MASK_OK; - } - --static int plic_irq_suspend(void) -+static int plic_irq_suspend(void *data) - { - struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; - -@@ -280,7 +280,7 @@ static int plic_irq_suspend(void) - return 0; - } - --static void plic_irq_resume(void) -+static void plic_irq_resume(void *data) - { - struct plic_priv *priv = this_cpu_ptr(&plic_handlers)->priv; - unsigned int index, cpu; -@@ -308,11 +308,15 @@ static void plic_irq_resume(void) - } - } - --static struct syscore_ops plic_irq_syscore_ops = { -+static const struct syscore_ops plic_irq_syscore_ops = { - .suspend = plic_irq_suspend, - .resume = plic_irq_resume, - }; - -+static struct syscore plic_irq_syscore = { -+ .ops = &plic_irq_syscore_ops, -+}; -+ - static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq) - { -@@ -782,7 +786,7 @@ static int plic_probe(struct fwnode_handle *fwnode) - cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, - "irqchip/sifive/plic:starting", - plic_starting_cpu, plic_dying_cpu); -- register_syscore_ops(&plic_irq_syscore_ops); -+ register_syscore(&plic_irq_syscore); - plic_global_setup_done = true; - } - } -diff --git a/drivers/irqchip/irq-sun6i-r.c b/drivers/irqchip/irq-sun6i-r.c -index 37d4b29763bc..23251831c06e 100644 ---- a/drivers/irqchip/irq-sun6i-r.c -+++ b/drivers/irqchip/irq-sun6i-r.c -@@ -268,7 +268,7 @@ static const struct irq_domain_ops sun6i_r_intc_domain_ops = { - .free = irq_domain_free_irqs_common, - }; - --static int sun6i_r_intc_suspend(void) -+static int sun6i_r_intc_suspend(void *data) - { - u32 buf[BITS_TO_U32(MAX(SUN6I_NR_TOP_LEVEL_IRQS, SUN6I_NR_MUX_BITS))]; - int i; -@@ -284,7 +284,7 @@ static int sun6i_r_intc_suspend(void) - return 0; - } - --static void sun6i_r_intc_resume(void) -+static void sun6i_r_intc_resume(void *data) - { - int i; - -@@ -294,17 +294,21 @@ static void sun6i_r_intc_resume(void) - writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i)); - } - --static void sun6i_r_intc_shutdown(void) -+static void sun6i_r_intc_shutdown(void *data) - { -- sun6i_r_intc_suspend(); -+ sun6i_r_intc_suspend(data); - } - --static struct syscore_ops sun6i_r_intc_syscore_ops = { -+static const struct syscore_ops sun6i_r_intc_syscore_ops = { - .suspend = sun6i_r_intc_suspend, - .resume = sun6i_r_intc_resume, - .shutdown = sun6i_r_intc_shutdown, - }; - -+static struct syscore sun6i_r_intc_syscore = { -+ .ops = &sun6i_r_intc_syscore_ops, -+}; -+ - static int __init sun6i_r_intc_init(struct device_node *node, - struct device_node *parent, - const struct sun6i_r_intc_variant *v) -@@ -346,10 +350,10 @@ static int __init sun6i_r_intc_init(struct device_node *node, - return -ENOMEM; - } - -- register_syscore_ops(&sun6i_r_intc_syscore_ops); -+ register_syscore(&sun6i_r_intc_syscore); - - sun6i_r_intc_ack_nmi(); -- sun6i_r_intc_resume(); -+ sun6i_r_intc_resume(NULL); - - return 0; - } -diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c -index 66cbb9f77ff3..b6382cf6359a 100644 ---- a/drivers/irqchip/irq-tegra.c -+++ b/drivers/irqchip/irq-tegra.c -@@ -132,7 +132,7 @@ static int tegra_set_wake(struct irq_data *d, unsigned int enable) - return 0; - } - --static int tegra_ictlr_suspend(void) -+static int tegra_ictlr_suspend(void *data) - { - unsigned long flags; - unsigned int i; -@@ -161,7 +161,7 @@ static int tegra_ictlr_suspend(void) - return 0; - } - --static void tegra_ictlr_resume(void) -+static void tegra_ictlr_resume(void *data) - { - unsigned long flags; - unsigned int i; -@@ -184,14 +184,18 @@ static void tegra_ictlr_resume(void) - local_irq_restore(flags); - } - --static struct syscore_ops tegra_ictlr_syscore_ops = { -+static const struct syscore_ops tegra_ictlr_syscore_ops = { - .suspend = tegra_ictlr_suspend, - .resume = tegra_ictlr_resume, - }; - -+static struct syscore tegra_ictlr_syscore = { -+ .ops = &tegra_ictlr_syscore_ops, -+}; -+ - static void tegra_ictlr_syscore_init(void) - { -- register_syscore_ops(&tegra_ictlr_syscore_ops); -+ register_syscore(&tegra_ictlr_syscore); - } - #else - #define tegra_set_wake NULL -diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c -index 2bcdf216a000..e38104c5064e 100644 ---- a/drivers/irqchip/irq-vic.c -+++ b/drivers/irqchip/irq-vic.c -@@ -120,7 +120,7 @@ static void resume_one_vic(struct vic_device *vic) - writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); - } - --static void vic_resume(void) -+static void vic_resume(void *data) - { - int id; - -@@ -146,7 +146,7 @@ static void suspend_one_vic(struct vic_device *vic) - writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); - } - --static int vic_suspend(void) -+static int vic_suspend(void *data) - { - int id; - -@@ -156,11 +156,15 @@ static int vic_suspend(void) - return 0; - } - --static struct syscore_ops vic_syscore_ops = { -+static const struct syscore_ops vic_syscore_ops = { - .suspend = vic_suspend, - .resume = vic_resume, - }; - -+static struct syscore vic_syscore = { -+ .ops = &vic_syscore_ops, -+}; -+ - /** - * vic_pm_init - initcall to register VIC pm - * -@@ -171,7 +175,7 @@ static struct syscore_ops vic_syscore_ops = { - static int __init vic_pm_init(void) - { - if (vic_id > 0) -- register_syscore_ops(&vic_syscore_ops); -+ register_syscore(&vic_syscore); - - return 0; - } -diff --git a/drivers/leds/trigger/ledtrig-cpu.c b/drivers/leds/trigger/ledtrig-cpu.c -index 05848a2fecff..679323c2ccda 100644 ---- a/drivers/leds/trigger/ledtrig-cpu.c -+++ b/drivers/leds/trigger/ledtrig-cpu.c -@@ -94,28 +94,32 @@ void ledtrig_cpu(enum cpu_led_event ledevt) - } - EXPORT_SYMBOL(ledtrig_cpu); - --static int ledtrig_cpu_syscore_suspend(void) -+static int ledtrig_cpu_syscore_suspend(void *data) - { - ledtrig_cpu(CPU_LED_STOP); - return 0; - } - --static void ledtrig_cpu_syscore_resume(void) -+static void ledtrig_cpu_syscore_resume(void *data) - { - ledtrig_cpu(CPU_LED_START); - } - --static void ledtrig_cpu_syscore_shutdown(void) -+static void ledtrig_cpu_syscore_shutdown(void *data) - { - ledtrig_cpu(CPU_LED_HALTED); - } - --static struct syscore_ops ledtrig_cpu_syscore_ops = { -+static const struct syscore_ops ledtrig_cpu_syscore_ops = { - .shutdown = ledtrig_cpu_syscore_shutdown, - .suspend = ledtrig_cpu_syscore_suspend, - .resume = ledtrig_cpu_syscore_resume, - }; - -+static struct syscore ledtrig_cpu_syscore = { -+ .ops = &ledtrig_cpu_syscore_ops, -+}; -+ - static int ledtrig_online_cpu(unsigned int cpu) - { - ledtrig_cpu(CPU_LED_START); -@@ -157,7 +161,7 @@ static int __init ledtrig_cpu_init(void) - led_trigger_register_simple(trig->name, &trig->_trig); - } - -- register_syscore_ops(&ledtrig_cpu_syscore_ops); -+ register_syscore(&ledtrig_cpu_syscore); - - ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "leds/trigger:starting", - ledtrig_online_cpu, ledtrig_prepare_down_cpu); -diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c -index b0f09c70f1ff..5fe47e784d43 100644 ---- a/drivers/macintosh/via-pmu.c -+++ b/drivers/macintosh/via-pmu.c -@@ -2600,7 +2600,7 @@ void pmu_blink(int n) - #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC32) - int pmu_sys_suspended; - --static int pmu_syscore_suspend(void) -+static int pmu_syscore_suspend(void *data) - { - /* Suspend PMU event interrupts */ - pmu_suspend(); -@@ -2614,7 +2614,7 @@ static int pmu_syscore_suspend(void) - return 0; - } - --static void pmu_syscore_resume(void) -+static void pmu_syscore_resume(void *data) - { - struct adb_request req; - -@@ -2634,14 +2634,18 @@ static void pmu_syscore_resume(void) - pmu_sys_suspended = 0; - } - --static struct syscore_ops pmu_syscore_ops = { -+static const struct syscore_ops pmu_syscore_ops = { - .suspend = pmu_syscore_suspend, - .resume = pmu_syscore_resume, - }; - -+static struct syscore pmu_syscore = { -+ .ops = &pmu_syscore_ops, -+}; -+ - static int pmu_syscore_register(void) - { -- register_syscore_ops(&pmu_syscore_ops); -+ register_syscore(&pmu_syscore); - - return 0; - } -diff --git a/drivers/power/reset/sc27xx-poweroff.c b/drivers/power/reset/sc27xx-poweroff.c -index 90287c31992c..393bd1c33b73 100644 ---- a/drivers/power/reset/sc27xx-poweroff.c -+++ b/drivers/power/reset/sc27xx-poweroff.c -@@ -28,7 +28,7 @@ static struct regmap *regmap; - * taking cpus down to avoid racing regmap or spi mutex lock when poweroff - * system through PMIC. - */ --static void sc27xx_poweroff_shutdown(void) -+static void sc27xx_poweroff_shutdown(void *data) - { - #ifdef CONFIG_HOTPLUG_CPU - int cpu; -@@ -40,10 +40,14 @@ static void sc27xx_poweroff_shutdown(void) - #endif - } - --static struct syscore_ops poweroff_syscore_ops = { -+static const struct syscore_ops poweroff_syscore_ops = { - .shutdown = sc27xx_poweroff_shutdown, - }; - -+static struct syscore poweroff_syscore = { -+ .ops = &poweroff_syscore_ops, -+}; -+ - static void sc27xx_poweroff_do_poweroff(void) - { - /* Disable the external subsys connection's power firstly */ -@@ -62,7 +66,7 @@ static int sc27xx_poweroff_probe(struct platform_device *pdev) - return -ENODEV; - - pm_power_off = sc27xx_poweroff_do_poweroff; -- register_syscore_ops(&poweroff_syscore_ops); -+ register_syscore(&poweroff_syscore); - return 0; - } - -diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c -index 7a73f5e4a1fc..f02e12dfa5f6 100644 ---- a/drivers/sh/clk/core.c -+++ b/drivers/sh/clk/core.c -@@ -569,7 +569,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) - EXPORT_SYMBOL_GPL(clk_round_rate); - - #ifdef CONFIG_PM --static void clks_core_resume(void) -+static void clks_core_resume(void *data) - { - struct clk *clkp; - -@@ -588,13 +588,17 @@ static void clks_core_resume(void) - } - } - --static struct syscore_ops clks_syscore_ops = { -+static const struct syscore_ops clks_syscore_ops = { - .resume = clks_core_resume, - }; - -+static struct syscore clks_syscore = { -+ .ops = &clks_syscore_ops, -+}; -+ - static int __init clk_syscore_init(void) - { -- register_syscore_ops(&clks_syscore_ops); -+ register_syscore(&clks_syscore); - - return 0; - } -diff --git a/drivers/sh/intc/core.c b/drivers/sh/intc/core.c -index ea571eeb3078..3dde703b7766 100644 ---- a/drivers/sh/intc/core.c -+++ b/drivers/sh/intc/core.c -@@ -394,7 +394,7 @@ int __init register_intc_controller(struct intc_desc *desc) - return -ENOMEM; - } - --static int intc_suspend(void) -+static int intc_suspend(void *data) - { - struct intc_desc_int *d; - -@@ -420,7 +420,7 @@ static int intc_suspend(void) - return 0; - } - --static void intc_resume(void) -+static void intc_resume(void *data) - { - struct intc_desc_int *d; - -@@ -450,11 +450,15 @@ static void intc_resume(void) - } - } - --struct syscore_ops intc_syscore_ops = { -+static const struct syscore_ops intc_syscore_ops = { - .suspend = intc_suspend, - .resume = intc_resume, - }; - -+static struct syscore intc_syscore = { -+ .ops = &intc_syscore_ops, -+}; -+ - const struct bus_type intc_subsys = { - .name = "intc", - .dev_name = "intc", -@@ -477,7 +481,7 @@ static int __init register_intc_devs(void) - struct intc_desc_int *d; - int error; - -- register_syscore_ops(&intc_syscore_ops); -+ register_syscore(&intc_syscore); - - error = subsys_system_register(&intc_subsys, NULL); - if (!error) { -diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c -index 364ddbe365c2..bd830649b60d 100644 ---- a/drivers/soc/bcm/brcmstb/biuctrl.c -+++ b/drivers/soc/bcm/brcmstb/biuctrl.c -@@ -298,7 +298,7 @@ static int __init setup_hifcpubiuctrl_regs(struct device_node *np) - #ifdef CONFIG_PM_SLEEP - static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS]; - --static int brcmstb_cpu_credit_reg_suspend(void) -+static int brcmstb_cpu_credit_reg_suspend(void *data) - { - unsigned int i; - -@@ -311,7 +311,7 @@ static int brcmstb_cpu_credit_reg_suspend(void) - return 0; - } - --static void brcmstb_cpu_credit_reg_resume(void) -+static void brcmstb_cpu_credit_reg_resume(void *data) - { - unsigned int i; - -@@ -322,10 +322,14 @@ static void brcmstb_cpu_credit_reg_resume(void) - cbc_writel(cpubiuctrl_reg_save[i], i); - } - --static struct syscore_ops brcmstb_cpu_credit_syscore_ops = { -+static const struct syscore_ops brcmstb_cpu_credit_syscore_ops = { - .suspend = brcmstb_cpu_credit_reg_suspend, - .resume = brcmstb_cpu_credit_reg_resume, - }; -+ -+static struct syscore brcmstb_cpu_credit_syscore = { -+ .ops = &brcmstb_cpu_credit_syscore_ops, -+}; - #endif - - -@@ -354,7 +358,7 @@ static int __init brcmstb_biuctrl_init(void) - a72_b53_rac_enable_all(np); - mcp_a72_b53_set(); - #ifdef CONFIG_PM_SLEEP -- register_syscore_ops(&brcmstb_cpu_credit_syscore_ops); -+ register_syscore(&brcmstb_cpu_credit_syscore); - #endif - ret = 0; - out_put: -diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c -index 034a2a535a1e..93bbebd68001 100644 ---- a/drivers/soc/tegra/pmc.c -+++ b/drivers/soc/tegra/pmc.c -@@ -466,7 +466,7 @@ struct tegra_pmc { - unsigned long *wake_type_dual_edge_map; - unsigned long *wake_sw_status_map; - unsigned long *wake_cntrl_level_map; -- struct syscore_ops syscore; -+ struct syscore syscore; - }; - - static struct tegra_pmc *pmc = &(struct tegra_pmc) { -@@ -3147,7 +3147,7 @@ static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int - } - } - --static void tegra186_pmc_wake_syscore_resume(void) -+static void tegra186_pmc_wake_syscore_resume(void *data) - { - u32 status, mask; - unsigned int i; -@@ -3160,7 +3160,7 @@ static void tegra186_pmc_wake_syscore_resume(void) - } - } - --static int tegra186_pmc_wake_syscore_suspend(void) -+static int tegra186_pmc_wake_syscore_suspend(void *data) - { - wke_read_sw_wake_status(pmc); - -@@ -3179,6 +3179,11 @@ static int tegra186_pmc_wake_syscore_suspend(void) - return 0; - } - -+static const struct syscore_ops tegra186_pmc_wake_syscore_ops = { -+ .suspend = tegra186_pmc_wake_syscore_suspend, -+ .resume = tegra186_pmc_wake_syscore_resume, -+}; -+ - #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) - static int tegra_pmc_suspend(struct device *dev) - { -@@ -3829,10 +3834,8 @@ static const struct tegra_pmc_regs tegra186_pmc_regs = { - - static void tegra186_pmc_init(struct tegra_pmc *pmc) - { -- pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; -- pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; -- -- register_syscore_ops(&pmc->syscore); -+ pmc->syscore.ops = &tegra186_pmc_wake_syscore_ops; -+ register_syscore(&pmc->syscore); - } - - static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, -diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c -index bd2fca7dc017..8a2f441cd2ec 100644 ---- a/drivers/thermal/intel/intel_hfi.c -+++ b/drivers/thermal/intel/intel_hfi.c -@@ -592,7 +592,7 @@ static void hfi_disable_instance(void *ptr) - hfi_disable(); - } - --static void hfi_syscore_resume(void) -+static void hfi_syscore_resume(void *data) - { - /* This code runs only on the boot CPU. */ - struct hfi_cpu_info *info = &per_cpu(hfi_cpu_info, 0); -@@ -603,7 +603,7 @@ static void hfi_syscore_resume(void) - hfi_enable_instance(hfi_instance); - } - --static int hfi_syscore_suspend(void) -+static int hfi_syscore_suspend(void *data) - { - /* No locking needed. There is no concurrency with CPU offline. */ - hfi_disable(); -@@ -611,11 +611,15 @@ static int hfi_syscore_suspend(void) - return 0; - } - --static struct syscore_ops hfi_pm_ops = { -+static const struct syscore_ops hfi_pm_ops = { - .resume = hfi_syscore_resume, - .suspend = hfi_syscore_suspend, - }; - -+static struct syscore hfi_pm = { -+ .ops = &hfi_pm_ops, -+}; -+ - static int hfi_thermal_notify(struct notifier_block *nb, unsigned long state, - void *_notify) - { -@@ -710,7 +714,7 @@ void __init intel_hfi_init(void) - if (thermal_genl_register_notifier(&hfi_thermal_nb)) - goto err_nl_notif; - -- register_syscore_ops(&hfi_pm_ops); -+ register_syscore(&hfi_pm); - - return; - -diff --git a/drivers/xen/xen-acpi-processor.c b/drivers/xen/xen-acpi-processor.c -index 520756159d3d..8d1860bd5d57 100644 ---- a/drivers/xen/xen-acpi-processor.c -+++ b/drivers/xen/xen-acpi-processor.c -@@ -492,7 +492,7 @@ static void xen_acpi_processor_resume_worker(struct work_struct *dummy) - pr_info("ACPI data upload failed, error = %d\n", rc); - } - --static void xen_acpi_processor_resume(void) -+static void xen_acpi_processor_resume(void *data) - { - static DECLARE_WORK(wq, xen_acpi_processor_resume_worker); - -@@ -506,10 +506,14 @@ static void xen_acpi_processor_resume(void) - schedule_work(&wq); - } - --static struct syscore_ops xap_syscore_ops = { -+static const struct syscore_ops xap_syscore_ops = { - .resume = xen_acpi_processor_resume, - }; - -+static struct syscore xap_syscore = { -+ .ops = &xap_syscore_ops, -+}; -+ - static int __init xen_acpi_processor_init(void) - { - int i; -@@ -560,7 +564,7 @@ static int __init xen_acpi_processor_init(void) - if (rc) - goto err_unregister; - -- register_syscore_ops(&xap_syscore_ops); -+ register_syscore(&xap_syscore); - - return 0; - err_unregister: -@@ -577,7 +581,7 @@ static void __exit xen_acpi_processor_exit(void) - { - int i; - -- unregister_syscore_ops(&xap_syscore_ops); -+ unregister_syscore(&xap_syscore); - bitmap_free(acpi_ids_done); - bitmap_free(acpi_id_present); - bitmap_free(acpi_id_cst_present); -diff --git a/include/linux/syscore_ops.h b/include/linux/syscore_ops.h -index ae4d48e4c970..ac6d71be5c38 100644 ---- a/include/linux/syscore_ops.h -+++ b/include/linux/syscore_ops.h -@@ -11,14 +11,19 @@ - #include - - struct syscore_ops { -+ int (*suspend)(void *data); -+ void (*resume)(void *data); -+ void (*shutdown)(void *data); -+}; -+ -+struct syscore { - struct list_head node; -- int (*suspend)(void); -- void (*resume)(void); -- void (*shutdown)(void); -+ const struct syscore_ops *ops; -+ void *data; - }; - --extern void register_syscore_ops(struct syscore_ops *ops); --extern void unregister_syscore_ops(struct syscore_ops *ops); -+extern void register_syscore(struct syscore *syscore); -+extern void unregister_syscore(struct syscore *syscore); - #ifdef CONFIG_PM_SLEEP - extern int syscore_suspend(void); - extern void syscore_resume(void); -diff --git a/kernel/cpu_pm.c b/kernel/cpu_pm.c -index b0f0d15085db..7481fbb947d3 100644 ---- a/kernel/cpu_pm.c -+++ b/kernel/cpu_pm.c -@@ -173,7 +173,7 @@ int cpu_cluster_pm_exit(void) - EXPORT_SYMBOL_GPL(cpu_cluster_pm_exit); - - #ifdef CONFIG_PM --static int cpu_pm_suspend(void) -+static int cpu_pm_suspend(void *data) - { - int ret; - -@@ -185,20 +185,24 @@ static int cpu_pm_suspend(void) - return ret; - } - --static void cpu_pm_resume(void) -+static void cpu_pm_resume(void *data) - { - cpu_cluster_pm_exit(); - cpu_pm_exit(); - } - --static struct syscore_ops cpu_pm_syscore_ops = { -+static const struct syscore_ops cpu_pm_syscore_ops = { - .suspend = cpu_pm_suspend, - .resume = cpu_pm_resume, - }; - -+static struct syscore cpu_pm_syscore = { -+ .ops = &cpu_pm_syscore_ops, -+}; -+ - static int cpu_pm_init(void) - { -- register_syscore_ops(&cpu_pm_syscore_ops); -+ register_syscore(&cpu_pm_syscore); - return 0; - } - core_initcall(cpu_pm_init); -diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c -index bf59e37d650a..3cd0c40282c0 100644 ---- a/kernel/irq/generic-chip.c -+++ b/kernel/irq/generic-chip.c -@@ -650,7 +650,7 @@ static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc) - } - - #ifdef CONFIG_PM --static int irq_gc_suspend(void) -+static int irq_gc_suspend(void *data) - { - struct irq_chip_generic *gc; - -@@ -670,7 +670,7 @@ static int irq_gc_suspend(void) - return 0; - } - --static void irq_gc_resume(void) -+static void irq_gc_resume(void *data) - { - struct irq_chip_generic *gc; - -@@ -693,7 +693,7 @@ static void irq_gc_resume(void) - #define irq_gc_resume NULL - #endif - --static void irq_gc_shutdown(void) -+static void irq_gc_shutdown(void *data) - { - struct irq_chip_generic *gc; - -@@ -709,15 +709,19 @@ static void irq_gc_shutdown(void) - } - } - --static struct syscore_ops irq_gc_syscore_ops = { -+static const struct syscore_ops irq_gc_syscore_ops = { - .suspend = irq_gc_suspend, - .resume = irq_gc_resume, - .shutdown = irq_gc_shutdown, - }; - -+static struct syscore irq_gc_syscore = { -+ .ops = &irq_gc_syscore_ops, -+}; -+ - static int __init irq_gc_init_ops(void) - { -- register_syscore_ops(&irq_gc_syscore_ops); -+ register_syscore(&irq_gc_syscore); - return 0; - } - device_initcall(irq_gc_init_ops); -diff --git a/kernel/irq/pm.c b/kernel/irq/pm.c -index f7394729cedc..99ff65466d87 100644 ---- a/kernel/irq/pm.c -+++ b/kernel/irq/pm.c -@@ -211,21 +211,26 @@ void rearm_wake_irq(unsigned int irq) - - /** - * irq_pm_syscore_resume - enable interrupt lines early -+ * @data: syscore context - * - * Enable all interrupt lines with %IRQF_EARLY_RESUME set. - */ --static void irq_pm_syscore_resume(void) -+static void irq_pm_syscore_resume(void *data) - { - resume_irqs(true); - } - --static struct syscore_ops irq_pm_syscore_ops = { -+static const struct syscore_ops irq_pm_syscore_ops = { - .resume = irq_pm_syscore_resume, - }; - -+static struct syscore irq_pm_syscore = { -+ .ops = &irq_pm_syscore_ops, -+}; -+ - static int __init irq_pm_init_ops(void) - { -- register_syscore_ops(&irq_pm_syscore_ops); -+ register_syscore(&irq_pm_syscore); - return 0; - } - -diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c -index c27fc7fc64eb..70a97290ad90 100644 ---- a/kernel/printk/printk.c -+++ b/kernel/printk/printk.c -@@ -3660,12 +3660,13 @@ static bool legacy_kthread_create(void) - - /** - * printk_kthreads_shutdown - shutdown all threaded printers -+ * @data: syscore context - * - * On system shutdown all threaded printers are stopped. This allows printk - * to transition back to atomic printing, thus providing a robust mechanism - * for the final shutdown/reboot messages to be output. - */ --static void printk_kthreads_shutdown(void) -+static void printk_kthreads_shutdown(void *data) - { - struct console *con; - -@@ -3687,10 +3688,14 @@ static void printk_kthreads_shutdown(void) - console_list_unlock(); - } - --static struct syscore_ops printk_syscore_ops = { -+static const struct syscore_ops printk_syscore_ops = { - .shutdown = printk_kthreads_shutdown, - }; - -+static struct syscore printk_syscore = { -+ .ops = &printk_syscore_ops, -+}; -+ - /* - * If appropriate, start nbcon kthreads and set @printk_kthreads_running. - * If any kthreads fail to start, those consoles are unregistered. -@@ -3758,7 +3763,7 @@ static void printk_kthreads_check_locked(void) - - static int __init printk_set_kthreads_ready(void) - { -- register_syscore_ops(&printk_syscore_ops); -+ register_syscore(&printk_syscore); - - console_list_lock(); - printk_kthreads_ready = true; -diff --git a/kernel/time/sched_clock.c b/kernel/time/sched_clock.c -index 425d429906d0..f3aaef695b8c 100644 ---- a/kernel/time/sched_clock.c -+++ b/kernel/time/sched_clock.c -@@ -296,6 +296,11 @@ int sched_clock_suspend(void) - return 0; - } - -+static int sched_clock_syscore_suspend(void *data) -+{ -+ return sched_clock_suspend(); -+} -+ - void sched_clock_resume(void) - { - struct clock_read_data *rd = &cd.read_data[0]; -@@ -305,14 +310,23 @@ void sched_clock_resume(void) - rd->read_sched_clock = cd.actual_read_sched_clock; - } - --static struct syscore_ops sched_clock_ops = { -- .suspend = sched_clock_suspend, -- .resume = sched_clock_resume, -+static void sched_clock_syscore_resume(void *data) -+{ -+ sched_clock_resume(); -+} -+ -+static const struct syscore_ops sched_clock_syscore_ops = { -+ .suspend = sched_clock_syscore_suspend, -+ .resume = sched_clock_syscore_resume, -+}; -+ -+static struct syscore sched_clock_syscore = { -+ .ops = &sched_clock_syscore_ops, - }; - - static int __init sched_clock_syscore_init(void) - { -- register_syscore_ops(&sched_clock_ops); -+ register_syscore(&sched_clock_syscore); - - return 0; - } -diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c -index c7dcccc5f3d6..c07e562ee4c1 100644 ---- a/kernel/time/timekeeping.c -+++ b/kernel/time/timekeeping.c -@@ -1994,6 +1994,11 @@ void timekeeping_resume(void) - timerfd_resume(); - } - -+static void timekeeping_syscore_resume(void *data) -+{ -+ timekeeping_resume(); -+} -+ - int timekeeping_suspend(void) - { - struct timekeeper *tks = &tk_core.shadow_timekeeper; -@@ -2061,15 +2066,24 @@ int timekeeping_suspend(void) - return 0; - } - -+static int timekeeping_syscore_suspend(void *data) -+{ -+ return timekeeping_suspend(); -+} -+ - /* sysfs resume/suspend bits for timekeeping */ --static struct syscore_ops timekeeping_syscore_ops = { -- .resume = timekeeping_resume, -- .suspend = timekeeping_suspend, -+static const struct syscore_ops timekeeping_syscore_ops = { -+ .resume = timekeeping_syscore_resume, -+ .suspend = timekeeping_syscore_suspend, -+}; -+ -+static struct syscore timekeeping_syscore = { -+ .ops = &timekeeping_syscore_ops, - }; - - static int __init timekeeping_init_ops(void) - { -- register_syscore_ops(&timekeeping_syscore_ops); -+ register_syscore(&timekeeping_syscore); - return 0; - } - device_initcall(timekeeping_init_ops); -diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c -index 46581554abfb..3ec22d034e73 100644 ---- a/virt/kvm/kvm_main.c -+++ b/virt/kvm/kvm_main.c -@@ -5629,7 +5629,7 @@ static int kvm_offline_cpu(unsigned int cpu) - return 0; - } - --static void kvm_shutdown(void) -+static void kvm_shutdown(void *data) - { - /* - * Disable hardware virtualization and set kvm_rebooting to indicate -@@ -5647,7 +5647,7 @@ static void kvm_shutdown(void) - on_each_cpu(kvm_disable_virtualization_cpu, NULL, 1); - } - --static int kvm_suspend(void) -+static int kvm_suspend(void *data) - { - /* - * Secondary CPUs and CPU hotplug are disabled across the suspend/resume -@@ -5664,7 +5664,7 @@ static int kvm_suspend(void) - return 0; - } - --static void kvm_resume(void) -+static void kvm_resume(void *data) - { - lockdep_assert_not_held(&kvm_usage_lock); - lockdep_assert_irqs_disabled(); -@@ -5672,12 +5672,16 @@ static void kvm_resume(void) - WARN_ON_ONCE(kvm_enable_virtualization_cpu()); - } - --static struct syscore_ops kvm_syscore_ops = { -+static const struct syscore_ops kvm_syscore_ops = { - .suspend = kvm_suspend, - .resume = kvm_resume, - .shutdown = kvm_shutdown, - }; - -+static struct syscore kvm_syscore = { -+ .ops = &kvm_syscore_ops, -+}; -+ - int kvm_enable_virtualization(void) - { - int r; -@@ -5694,7 +5698,7 @@ int kvm_enable_virtualization(void) - if (r) - goto err_cpuhp; - -- register_syscore_ops(&kvm_syscore_ops); -+ register_syscore(&kvm_syscore); - - /* - * Undo virtualization enabling and bail if the system is going down. -@@ -5716,7 +5720,7 @@ int kvm_enable_virtualization(void) - return 0; - - err_rebooting: -- unregister_syscore_ops(&kvm_syscore_ops); -+ unregister_syscore(&kvm_syscore); - cpuhp_remove_state(CPUHP_AP_KVM_ONLINE); - err_cpuhp: - kvm_arch_disable_virtualization(); -@@ -5732,7 +5736,7 @@ void kvm_disable_virtualization(void) - if (--kvm_usage_count) - return; - -- unregister_syscore_ops(&kvm_syscore_ops); -+ unregister_syscore(&kvm_syscore); - cpuhp_remove_state(CPUHP_AP_KVM_ONLINE); - kvm_arch_disable_virtualization(); - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch b/SPECS/linux-lts/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch new file mode 100644 index 0000000000..edf918ccc1 --- /dev/null +++ b/SPECS/linux-lts/0164-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch @@ -0,0 +1,96 @@ +From 362bcba652bd4b28531fbf93691ef6fba9a852a7 Mon Sep 17 00:00:00 2001 +From: Frank Li +Date: Mon, 29 Sep 2025 10:24:14 -0400 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: add missed compatible string + for arm64 layerscape + +Add missed compatible string for arm64 layerscape platform. Allow these +fallback to fsl,ls1028a-dwc3. + +Remove fallback snps,dwc3 because layerscape dwc3 is not full compatible +with common snps,dwc3 device, a special value gsburstcfg0 need be set when +dma coherence enabled. + +Allow iommus property. + +Change ref to snps,dwc3-common.yaml to use dwc3 flatten library. + +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Frank Li +Link: https://lore.kernel.org/r/20250929-ls_dma_coherence-v5-1-2ebee578eb7e@nxp.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit b9f1c762a4de17d93017fbd12b9941caff6d3078) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/usb/fsl,ls1028a.yaml | 33 ++++++++++--------- + 1 file changed, 18 insertions(+), 15 deletions(-) + +diff --git a/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml b/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml +index a44bdf391887..4784f057264a 100644 +--- a/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml ++++ b/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml +@@ -9,21 +9,19 @@ title: Freescale layerscape SuperSpeed DWC3 USB SoC controller + maintainers: + - Frank Li + +-select: +- properties: +- compatible: +- contains: +- enum: +- - fsl,ls1028a-dwc3 +- required: +- - compatible +- + properties: + compatible: +- items: +- - enum: +- - fsl,ls1028a-dwc3 +- - const: snps,dwc3 ++ oneOf: ++ - items: ++ - enum: ++ - fsl,ls1012a-dwc3 ++ - fsl,ls1043a-dwc3 ++ - fsl,ls1046a-dwc3 ++ - fsl,ls1088a-dwc3 ++ - fsl,ls208xa-dwc3 ++ - fsl,lx2160a-dwc3 ++ - const: fsl,ls1028a-dwc3 ++ - const: fsl,ls1028a-dwc3 + + reg: + maxItems: 1 +@@ -31,6 +29,11 @@ properties: + interrupts: + maxItems: 1 + ++ iommus: ++ maxItems: 1 ++ ++ dma-coherent: true ++ + unevaluatedProperties: false + + required: +@@ -39,14 +42,14 @@ required: + - interrupts + + allOf: +- - $ref: snps,dwc3.yaml# ++ - $ref: snps,dwc3-common.yaml# + + examples: + - | + #include + + usb@fe800000 { +- compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; ++ compatible = "fsl,ls1028a-dwc3"; + reg = <0xfe800000 0x100000>; + interrupts = ; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0164-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch b/SPECS/linux-lts/0164-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch deleted file mode 100644 index 76e29a3422..0000000000 --- a/SPECS/linux-lts/0164-UPSTREAM-irqchip-riscv-aplic-Preserve-APLIC-states-a.patch +++ /dev/null @@ -1,325 +0,0 @@ -From bb03ede744a1b004dd7ecaebdb891a4d0bc0c559 Mon Sep 17 00:00:00 2001 -From: Nick Hu -Date: Tue, 2 Dec 2025 14:07:41 +0800 -Subject: [PATCH 164/467] UPSTREAM: irqchip/riscv-aplic: Preserve APLIC states - across suspend/resume - -The APLIC states might be reset when the platform enters a low power -state, but the register states are not being preserved and restored, -which prevents interrupt delivery after the platform resumes. -Solve this by adding a syscore ops and a power management notifier to -preserve and restore the APLIC states on suspend and resume. - -[ tglx: Folded the build fix provided by Geert ] - -Signed-off-by: Nick Hu -Signed-off-by: Thomas Gleixner -Reviewed-by: Yong-Xuan Wang -Reviewed-by: Cyan Yang -Reviewed-by: Nutty Liu -Reviewed-by: Anup Patel -Link: https://patch.msgid.link/20251202-preserve-aplic-imsic-v3-2-1844fbf1fe92@sifive.com -(cherry picked from commit 95a8ddde36601d0a645475fb080ed118db59c8c3) -Signed-off-by: Han Gao ---- - drivers/irqchip/irq-riscv-aplic-direct.c | 10 ++ - drivers/irqchip/irq-riscv-aplic-main.c | 170 ++++++++++++++++++++++- - drivers/irqchip/irq-riscv-aplic-main.h | 19 +++ - 3 files changed, 198 insertions(+), 1 deletion(-) - -diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c -index c2a75bf3d20c..5a9650225dd8 100644 ---- a/drivers/irqchip/irq-riscv-aplic-direct.c -+++ b/drivers/irqchip/irq-riscv-aplic-direct.c -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -171,6 +172,15 @@ static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en) - writel(de, idc->regs + APLIC_IDC_IDELIVERY); - } - -+void aplic_direct_restore_states(struct aplic_priv *priv) -+{ -+ struct aplic_direct *direct = container_of(priv, struct aplic_direct, priv); -+ int cpu; -+ -+ for_each_cpu(cpu, &direct->lmask) -+ aplic_idc_set_delivery(per_cpu_ptr(&aplic_idcs, cpu), true); -+} -+ - static int aplic_direct_dying_cpu(unsigned int cpu) - { - if (aplic_direct_parent_irq) -diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c -index 93e7c51f944a..4495ca26abf5 100644 ---- a/drivers/irqchip/irq-riscv-aplic-main.c -+++ b/drivers/irqchip/irq-riscv-aplic-main.c -@@ -12,10 +12,169 @@ - #include - #include - #include -+#include -+#include - #include -+#include - - #include "irq-riscv-aplic-main.h" - -+static LIST_HEAD(aplics); -+ -+static void aplic_restore_states(struct aplic_priv *priv) -+{ -+ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs; -+ struct aplic_src_ctrl *srcs; -+ void __iomem *regs; -+ u32 nr_irqs, i; -+ -+ regs = priv->regs; -+ writel(saved_regs->domaincfg, regs + APLIC_DOMAINCFG); -+#ifdef CONFIG_RISCV_M_MODE -+ writel(saved_regs->msiaddr, regs + APLIC_xMSICFGADDR); -+ writel(saved_regs->msiaddrh, regs + APLIC_xMSICFGADDRH); -+#endif -+ /* -+ * The sourcecfg[i] has to be restored prior to the target[i], interrupt-pending and -+ * interrupt-enable bits. The AIA specification states that "Whenever interrupt source i is -+ * inactive in an interrupt domain, the corresponding interrupt-pending and interrupt-enable -+ * bits within the domain are read-only zeros, and register target[i] is also read-only -+ * zero." -+ */ -+ nr_irqs = priv->nr_irqs; -+ for (i = 0; i < nr_irqs; i++) { -+ srcs = &priv->saved_hw_regs.srcs[i]; -+ writel(srcs->sourcecfg, regs + APLIC_SOURCECFG_BASE + i * sizeof(u32)); -+ writel(srcs->target, regs + APLIC_TARGET_BASE + i * sizeof(u32)); -+ } -+ -+ for (i = 0; i <= nr_irqs; i += 32) { -+ srcs = &priv->saved_hw_regs.srcs[i]; -+ writel(-1U, regs + APLIC_CLRIE_BASE + (i / 32) * sizeof(u32)); -+ writel(srcs->ie, regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32)); -+ -+ /* Re-trigger the interrupts if it forwards interrupts to target harts by MSIs */ -+ if (!priv->nr_idcs) -+ writel(readl(regs + APLIC_CLRIP_BASE + (i / 32) * sizeof(u32)), -+ regs + APLIC_SETIP_BASE + (i / 32) * sizeof(u32)); -+ } -+ -+ if (priv->nr_idcs) -+ aplic_direct_restore_states(priv); -+} -+ -+static void aplic_save_states(struct aplic_priv *priv) -+{ -+ struct aplic_src_ctrl *srcs; -+ void __iomem *regs; -+ u32 i, nr_irqs; -+ -+ regs = priv->regs; -+ nr_irqs = priv->nr_irqs; -+ /* The valid interrupt source IDs range from 1 to N, where N is priv->nr_irqs */ -+ for (i = 0; i < nr_irqs; i++) { -+ srcs = &priv->saved_hw_regs.srcs[i]; -+ srcs->target = readl(regs + APLIC_TARGET_BASE + i * sizeof(u32)); -+ -+ if (i % 32) -+ continue; -+ -+ srcs->ie = readl(regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32)); -+ } -+ -+ /* Save the nr_irqs bit if needed */ -+ if (!(nr_irqs % 32)) { -+ srcs = &priv->saved_hw_regs.srcs[nr_irqs]; -+ srcs->ie = readl(regs + APLIC_SETIE_BASE + (nr_irqs / 32) * sizeof(u32)); -+ } -+} -+ -+static int aplic_syscore_suspend(void *data) -+{ -+ struct aplic_priv *priv; -+ -+ list_for_each_entry(priv, &aplics, head) -+ aplic_save_states(priv); -+ -+ return 0; -+} -+ -+static void aplic_syscore_resume(void *data) -+{ -+ struct aplic_priv *priv; -+ -+ list_for_each_entry(priv, &aplics, head) -+ aplic_restore_states(priv); -+} -+ -+static struct syscore_ops aplic_syscore_ops = { -+ .suspend = aplic_syscore_suspend, -+ .resume = aplic_syscore_resume, -+}; -+ -+static struct syscore aplic_syscore = { -+ .ops = &aplic_syscore_ops, -+}; -+ -+static int aplic_pm_notifier(struct notifier_block *nb, unsigned long action, void *data) -+{ -+ struct aplic_priv *priv = container_of(nb, struct aplic_priv, genpd_nb); -+ -+ switch (action) { -+ case GENPD_NOTIFY_PRE_OFF: -+ aplic_save_states(priv); -+ break; -+ case GENPD_NOTIFY_ON: -+ aplic_restore_states(priv); -+ break; -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+static void aplic_pm_remove(void *data) -+{ -+ struct aplic_priv *priv = data; -+ struct device *dev = priv->dev; -+ -+ list_del(&priv->head); -+ if (dev->pm_domain) -+ dev_pm_genpd_remove_notifier(dev); -+} -+ -+static int aplic_pm_add(struct device *dev, struct aplic_priv *priv) -+{ -+ struct aplic_src_ctrl *srcs; -+ int ret; -+ -+ srcs = devm_kzalloc(dev, (priv->nr_irqs + 1) * sizeof(*srcs), GFP_KERNEL); -+ if (!srcs) -+ return -ENOMEM; -+ -+ priv->saved_hw_regs.srcs = srcs; -+ list_add(&priv->head, &aplics); -+ if (dev->pm_domain) { -+ priv->genpd_nb.notifier_call = aplic_pm_notifier; -+ ret = dev_pm_genpd_add_notifier(dev, &priv->genpd_nb); -+ if (ret) -+ goto remove_head; -+ -+ ret = devm_pm_runtime_enable(dev); -+ if (ret) -+ goto remove_notifier; -+ } -+ -+ return devm_add_action_or_reset(dev, aplic_pm_remove, priv); -+ -+remove_notifier: -+ dev_pm_genpd_remove_notifier(dev); -+remove_head: -+ list_del(&priv->head); -+ return ret; -+} -+ - void aplic_irq_unmask(struct irq_data *d) - { - struct aplic_priv *priv = irq_data_get_irq_chip_data(d); -@@ -60,6 +219,8 @@ int aplic_irq_set_type(struct irq_data *d, unsigned int type) - sourcecfg += (d->hwirq - 1) * sizeof(u32); - writel(val, sourcecfg); - -+ priv->saved_hw_regs.srcs[d->hwirq - 1].sourcecfg = val; -+ - return 0; - } - -@@ -82,6 +243,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, - - void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) - { -+ struct aplic_saved_regs *saved_regs = &priv->saved_hw_regs; - u32 val; - #ifdef CONFIG_RISCV_M_MODE - u32 valh; -@@ -95,6 +257,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) - valh |= FIELD_PREP(APLIC_xMSICFGADDRH_HHXS, priv->msicfg.hhxs); - writel(val, priv->regs + APLIC_xMSICFGADDR); - writel(valh, priv->regs + APLIC_xMSICFGADDRH); -+ saved_regs->msiaddr = val; -+ saved_regs->msiaddrh = valh; - } - #endif - -@@ -106,6 +270,8 @@ void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode) - writel(val, priv->regs + APLIC_DOMAINCFG); - if (readl(priv->regs + APLIC_DOMAINCFG) != val) - dev_warn(priv->dev, "unable to write 0x%x in domaincfg\n", val); -+ -+ saved_regs->domaincfg = val; - } - - static void aplic_init_hw_irqs(struct aplic_priv *priv) -@@ -176,7 +342,7 @@ int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem * - /* Setup initial state APLIC interrupts */ - aplic_init_hw_irqs(priv); - -- return 0; -+ return aplic_pm_add(dev, priv); - } - - static int aplic_probe(struct platform_device *pdev) -@@ -209,6 +375,8 @@ static int aplic_probe(struct platform_device *pdev) - if (rc) - dev_err_probe(dev, rc, "failed to setup APLIC in %s mode\n", - msi_mode ? "MSI" : "direct"); -+ else -+ register_syscore(&aplic_syscore); - - #ifdef CONFIG_ACPI - if (!acpi_disabled) -diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-riscv-aplic-main.h -index b0ad8cde69b1..2d8ad7138541 100644 ---- a/drivers/irqchip/irq-riscv-aplic-main.h -+++ b/drivers/irqchip/irq-riscv-aplic-main.h -@@ -23,7 +23,25 @@ struct aplic_msicfg { - u32 lhxw; - }; - -+struct aplic_src_ctrl { -+ u32 sourcecfg; -+ u32 target; -+ u32 ie; -+}; -+ -+struct aplic_saved_regs { -+ u32 domaincfg; -+#ifdef CONFIG_RISCV_M_MODE -+ u32 msiaddr; -+ u32 msiaddrh; -+#endif -+ struct aplic_src_ctrl *srcs; -+}; -+ - struct aplic_priv { -+ struct list_head head; -+ struct notifier_block genpd_nb; -+ struct aplic_saved_regs saved_hw_regs; - struct device *dev; - u32 gsi_base; - u32 nr_irqs; -@@ -40,6 +58,7 @@ int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base, - unsigned long *hwirq, unsigned int *type); - void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode); - int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *regs); -+void aplic_direct_restore_states(struct aplic_priv *priv); - int aplic_direct_setup(struct device *dev, void __iomem *regs); - #ifdef CONFIG_RISCV_APLIC_MSI - int aplic_msi_setup(struct device *dev, void __iomem *regs); --- -2.53.0 - diff --git a/SPECS/linux-lts/0165-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch b/SPECS/linux-lts/0165-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch deleted file mode 100644 index 3b32023095..0000000000 --- a/SPECS/linux-lts/0165-UPSTREAM-irqchip-riscv-aplic-Do-not-clear-ACPI-depen.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 53ca58e7f8870492ce5c75dda934c60d28026396 Mon Sep 17 00:00:00 2001 -From: Jessica Liu -Date: Tue, 10 Mar 2026 14:16:00 +0800 -Subject: [PATCH 165/467] UPSTREAM: irqchip/riscv-aplic: Do not clear ACPI - dependencies on probe failure - -aplic_probe() calls acpi_dev_clear_dependencies() unconditionally at the -end, even when the preceding setup (MSI or direct mode) has failed. This is -incorrect because if the device failed to probe, it should not be -considered as active and should not clear dependencies for other devices -waiting on it. - -Fix this by returning immediately when the setup fails, skipping the ACPI -dependency cleanup. Also, explicitly return 0 on success instead of relying -on the value of 'rc' to make the success path clear. - -Fixes: 5122e380c23b ("irqchip/riscv-aplic: Add ACPI support") -Signed-off-by: Jessica Liu -Signed-off-by: Thomas Gleixner -Link: https://patch.msgid.link/20260310141600411Fu8H8-GXOOgKISU48Tjgx@zte.com.cn -(cherry picked from commit 620b6ded72a7f0f77be6ec44d0462bb85729ab7a) -Signed-off-by: Han Gao ---- - drivers/irqchip/irq-riscv-aplic-main.c | 11 +++++++---- - 1 file changed, 7 insertions(+), 4 deletions(-) - -diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c -index 4495ca26abf5..8775f188ea4f 100644 ---- a/drivers/irqchip/irq-riscv-aplic-main.c -+++ b/drivers/irqchip/irq-riscv-aplic-main.c -@@ -372,18 +372,21 @@ static int aplic_probe(struct platform_device *pdev) - rc = aplic_msi_setup(dev, regs); - else - rc = aplic_direct_setup(dev, regs); -- if (rc) -+ -+ if (rc) { - dev_err_probe(dev, rc, "failed to setup APLIC in %s mode\n", - msi_mode ? "MSI" : "direct"); -- else -- register_syscore(&aplic_syscore); -+ return rc; -+ } -+ -+ register_syscore(&aplic_syscore); - - #ifdef CONFIG_ACPI - if (!acpi_disabled) - acpi_dev_clear_dependencies(ACPI_COMPANION(dev)); - #endif - -- return rc; -+ return 0; - } - - static const struct of_device_id aplic_match[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch b/SPECS/linux-lts/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch new file mode 100644 index 0000000000..3f06b45545 --- /dev/null +++ b/SPECS/linux-lts/0165-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch @@ -0,0 +1,135 @@ +From 95da822dbecb61c821f0748e19304ec198992377 Mon Sep 17 00:00:00 2001 +From: Frank Li +Date: Mon, 29 Sep 2025 10:24:15 -0400 +Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: Add software-managed properties for + flattened model + +Add software-managed properties for the flattened model, which does not +need to use device tree properties to pass down information to the +common DWC3 core. + +Add 'properties' in dwc3_probe_data and set default values for existing +users (dwc3-qcom, dwc3-generic-plat). + +No functional changes. + +Acked-by: Thinh Nguyen +Signed-off-by: Frank Li +Link: https://lore.kernel.org/r/20250929-ls_dma_coherence-v5-2-2ebee578eb7e@nxp.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 7298c06d58e23c1c6e60180ab1ce069087ae38e2) +Signed-off-by: Han Gao +--- + drivers/usb/dwc3/core.c | 12 ++++++++++-- + drivers/usb/dwc3/dwc3-generic-plat.c | 1 + + drivers/usb/dwc3/dwc3-qcom.c | 1 + + drivers/usb/dwc3/glue.h | 14 ++++++++++++++ + 4 files changed, 26 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c +index a1f99c3b5f37..dd08b7f5b9a1 100644 +--- a/drivers/usb/dwc3/core.c ++++ b/drivers/usb/dwc3/core.c +@@ -1669,7 +1669,8 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc) + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true); + } + +-static void dwc3_get_software_properties(struct dwc3 *dwc) ++static void dwc3_get_software_properties(struct dwc3 *dwc, ++ const struct dwc3_properties *properties) + { + struct device *tmpdev; + u16 gsbuscfg0_reqinfo; +@@ -1677,6 +1678,12 @@ static void dwc3_get_software_properties(struct dwc3 *dwc) + + dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED; + ++ if (properties->gsbuscfg0_reqinfo != ++ DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) { ++ dwc->gsbuscfg0_reqinfo = properties->gsbuscfg0_reqinfo; ++ return; ++ } ++ + /* + * Iterate over all parent nodes for finding swnode properties + * and non-DT (non-ABI) properties. +@@ -2224,7 +2231,7 @@ int dwc3_core_probe(const struct dwc3_probe_data *data) + + dwc3_get_properties(dwc); + +- dwc3_get_software_properties(dwc); ++ dwc3_get_software_properties(dwc, &data->properties); + + dwc->usb_psy = dwc3_get_usb_power_supply(dwc); + if (IS_ERR(dwc->usb_psy)) +@@ -2374,6 +2381,7 @@ static int dwc3_probe(struct platform_device *pdev) + + probe_data.dwc = dwc; + probe_data.res = res; ++ probe_data.properties = DWC3_DEFAULT_PROPERTIES; + + return dwc3_core_probe(&probe_data); + } +diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c +index f8ad79c08c4e..ba3aec4cb963 100644 +--- a/drivers/usb/dwc3/dwc3-generic-plat.c ++++ b/drivers/usb/dwc3/dwc3-generic-plat.c +@@ -75,6 +75,7 @@ static int dwc3_generic_probe(struct platform_device *pdev) + probe_data.dwc = &dwc3g->dwc; + probe_data.res = res; + probe_data.ignore_clocks_and_resets = true; ++ probe_data.properties = DWC3_DEFAULT_PROPERTIES; + ret = dwc3_core_probe(&probe_data); + if (ret) + return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); +diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c +index ded2ca86670c..9ac75547820d 100644 +--- a/drivers/usb/dwc3/dwc3-qcom.c ++++ b/drivers/usb/dwc3/dwc3-qcom.c +@@ -704,6 +704,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev) + probe_data.dwc = &qcom->dwc; + probe_data.res = &res; + probe_data.ignore_clocks_and_resets = true; ++ probe_data.properties = DWC3_DEFAULT_PROPERTIES; + ret = dwc3_core_probe(&probe_data); + if (ret) { + ret = dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); +diff --git a/drivers/usb/dwc3/glue.h b/drivers/usb/dwc3/glue.h +index 2efd00e763be..cc6e138bd9ef 100644 +--- a/drivers/usb/dwc3/glue.h ++++ b/drivers/usb/dwc3/glue.h +@@ -9,17 +9,31 @@ + #include + #include "core.h" + ++/** ++ * dwc3_properties: DWC3 core properties ++ * @gsbuscfg0_reqinfo: Value to be programmed in the GSBUSCFG0.REQINFO field ++ */ ++struct dwc3_properties { ++ u32 gsbuscfg0_reqinfo; ++}; ++ ++#define DWC3_DEFAULT_PROPERTIES ((struct dwc3_properties){ \ ++ .gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED, \ ++ }) ++ + /** + * dwc3_probe_data: Initialization parameters passed to dwc3_core_probe() + * @dwc: Reference to dwc3 context structure + * @res: resource for the DWC3 core mmio region + * @ignore_clocks_and_resets: clocks and resets defined for the device should + * be ignored by the DWC3 core, as they are managed by the glue ++ * @properties: dwc3 software manage properties + */ + struct dwc3_probe_data { + struct dwc3 *dwc; + struct resource *res; + bool ignore_clocks_and_resets; ++ struct dwc3_properties properties; + }; + + int dwc3_core_probe(const struct dwc3_probe_data *data); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0166-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch b/SPECS/linux-lts/0166-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch deleted file mode 100644 index e1aff8100a..0000000000 --- a/SPECS/linux-lts/0166-UPSTREAM-irqchip-riscv-aplic-Register-syscore-operat.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 8ae93b636f92b573aec71e026e1959d7342e76f5 Mon Sep 17 00:00:00 2001 -From: Jessica Liu -Date: Tue, 10 Mar 2026 14:17:31 +0800 -Subject: [PATCH 166/467] UPSTREAM: irqchip/riscv-aplic: Register syscore - operations only once - -Since commit 95a8ddde3660 ("irqchip/riscv-aplic: Preserve APLIC -states across suspend/resume"), when multiple NUMA nodes exist -and AIA is not configured as "none", aplic_probe() is called -multiple times. This leads to register_syscore(&aplic_syscore) -being invoked repeatedly, causing the following Oops: - - list_add double add: new=ffffffffb91461f0, prev=ffffffffb91461f0, next=ffffffffb915c408. - [] __list_add_valid_or_report+0x60/0xc0 - [] register_syscore+0x3e/0x70 - [] aplic_probe+0xc6/0x112 - -Fix this by registering syscore operations only once, using a static -variable aplic_syscore_registered to track registration. - -[ tglx: Trim backtrace properly ] - -Fixes: 95a8ddde3660 ("irqchip/riscv-aplic: Preserve APLIC states across suspend/resume") -Signed-off-by: Jessica Liu -Signed-off-by: Thomas Gleixner -Link: https://patch.msgid.link/20260310141731145xMwLsyvXl9Gw-m6A4VRYj@zte.com.cn -(cherry picked from commit b330fbfd34d7624bec62b99ad88dba2614326a19) -Signed-off-by: Han Gao ---- - drivers/irqchip/irq-riscv-aplic-main.c | 12 +++++++++++- - 1 file changed, 11 insertions(+), 1 deletion(-) - -diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c -index 8775f188ea4f..9f53979b6962 100644 ---- a/drivers/irqchip/irq-riscv-aplic-main.c -+++ b/drivers/irqchip/irq-riscv-aplic-main.c -@@ -116,6 +116,16 @@ static struct syscore aplic_syscore = { - .ops = &aplic_syscore_ops, - }; - -+static bool aplic_syscore_registered __ro_after_init; -+ -+static void aplic_syscore_init(void) -+{ -+ if (!aplic_syscore_registered) { -+ register_syscore(&aplic_syscore); -+ aplic_syscore_registered = true; -+ } -+} -+ - static int aplic_pm_notifier(struct notifier_block *nb, unsigned long action, void *data) - { - struct aplic_priv *priv = container_of(nb, struct aplic_priv, genpd_nb); -@@ -379,7 +389,7 @@ static int aplic_probe(struct platform_device *pdev) - return rc; - } - -- register_syscore(&aplic_syscore); -+ aplic_syscore_init(); - - #ifdef CONFIG_ACPI - if (!acpi_disabled) --- -2.53.0 - diff --git a/SPECS/linux-lts/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch b/SPECS/linux-lts/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch new file mode 100644 index 0000000000..0ff5ac0f10 --- /dev/null +++ b/SPECS/linux-lts/0166-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch @@ -0,0 +1,63 @@ +From 336f616b6d4b4f53eb9ffdf8822f067ff0820efa Mon Sep 17 00:00:00 2001 +From: Frank Li +Date: Mon, 29 Sep 2025 10:24:16 -0400 +Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: dwc3-generic-plat: Add layerscape + dwc3 support + +Add layerscape dwc3 support by using flatten dwc3 core library. Layerscape +dwc3 need set gsbuscfg0-reqinfo as 0x2222 when dma-coherence set. + +Signed-off-by: Frank Li +Acked-by: Thinh Nguyen +Link: https://lore.kernel.org/r/20250929-ls_dma_coherence-v5-3-2ebee578eb7e@nxp.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 1c97fc901fb6318aca0160da96736d0bc136ddcd) +Signed-off-by: Han Gao +--- + drivers/usb/dwc3/dwc3-generic-plat.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c +index ba3aec4cb963..e869c7de7bc8 100644 +--- a/drivers/usb/dwc3/dwc3-generic-plat.c ++++ b/drivers/usb/dwc3/dwc3-generic-plat.c +@@ -29,6 +29,7 @@ static void dwc3_generic_reset_control_assert(void *data) + + static int dwc3_generic_probe(struct platform_device *pdev) + { ++ const struct dwc3_properties *properties; + struct dwc3_probe_data probe_data = {}; + struct device *dev = &pdev->dev; + struct dwc3_generic *dwc3g; +@@ -75,7 +76,13 @@ static int dwc3_generic_probe(struct platform_device *pdev) + probe_data.dwc = &dwc3g->dwc; + probe_data.res = res; + probe_data.ignore_clocks_and_resets = true; +- probe_data.properties = DWC3_DEFAULT_PROPERTIES; ++ ++ properties = of_device_get_match_data(dev); ++ if (properties) ++ probe_data.properties = *properties; ++ else ++ probe_data.properties = DWC3_DEFAULT_PROPERTIES; ++ + ret = dwc3_core_probe(&probe_data); + if (ret) + return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); +@@ -143,8 +150,13 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { + dwc3_generic_runtime_idle) + }; + ++static const struct dwc3_properties fsl_ls1028_dwc3 = { ++ .gsbuscfg0_reqinfo = 0x2222, ++}; ++ + static const struct of_device_id dwc3_generic_of_match[] = { + { .compatible = "spacemit,k1-dwc3", }, ++ { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch b/SPECS/linux-lts/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch new file mode 100644 index 0000000000..85f93bef67 --- /dev/null +++ b/SPECS/linux-lts/0167-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch @@ -0,0 +1,124 @@ +From 4b1c4f9c84bda4bcf482c0efe496c3a6648372ca Mon Sep 17 00:00:00 2001 +From: Hang Cao +Date: Wed, 12 Nov 2025 13:53:21 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: Add ESWIN EIC7700 USB + controller + +Add Device Tree binding documentation for the ESWIN EIC7700 +usb controller module. + +Signed-off-by: Senchuan Zhang +Signed-off-by: Hang Cao +Reviewed-by: Rob Herring (Arm) +Link: https://patch.msgid.link/20251112055321.1638-1-caohang@eswincomputing.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit c640a4239db53e077dd5fd20db52fbc8b64f290b) +Signed-off-by: Han Gao +--- + .../bindings/usb/eswin,eic7700-usb.yaml | 94 +++++++++++++++++++ + 1 file changed, 94 insertions(+) + create mode 100644 Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml + +diff --git a/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml +new file mode 100644 +index 000000000000..41c3b1b98991 +--- /dev/null ++++ b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml +@@ -0,0 +1,94 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/usb/eswin,eic7700-usb.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: ESWIN EIC7700 SoC Usb Controller ++ ++maintainers: ++ - Wei Yang ++ - Senchuan Zhang ++ - Hang Cao ++ ++description: ++ The Usb controller on EIC7700 SoC. ++ ++allOf: ++ - $ref: snps,dwc3-common.yaml# ++ ++properties: ++ compatible: ++ const: eswin,eic7700-dwc3 ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ interrupt-names: ++ items: ++ - const: peripheral ++ ++ clocks: ++ maxItems: 3 ++ ++ clock-names: ++ items: ++ - const: aclk ++ - const: cfg ++ - const: usb_en ++ ++ resets: ++ maxItems: 2 ++ ++ reset-names: ++ items: ++ - const: vaux ++ - const: usb_rst ++ ++ eswin,hsp-sp-csr: ++ description: ++ HSP CSR is to control and get status of different high-speed peripherals ++ (such as Ethernet, USB, SATA, etc.) via register, which can tune ++ board-level's parameters of PHY, etc. ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle to HSP Register Controller hsp_sp_csr node. ++ - description: USB bus register offset. ++ - description: AXI low power register offset. ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - interrupts ++ - interrupt-names ++ - resets ++ - reset-names ++ - eswin,hsp-sp-csr ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ usb@50480000 { ++ compatible = "eswin,eic7700-dwc3"; ++ reg = <0x50480000 0x10000>; ++ clocks = <&clock 135>, ++ <&clock 136>, ++ <&hspcrg 18>; ++ clock-names = "aclk", "cfg", "usb_en"; ++ interrupt-parent = <&plic>; ++ interrupts = <85>; ++ interrupt-names = "peripheral"; ++ resets = <&reset 84>, <&hspcrg 2>; ++ reset-names = "vaux", "usb_rst"; ++ dr_mode = "peripheral"; ++ maximum-speed = "high-speed"; ++ phy_type = "utmi"; ++ eswin,hsp-sp-csr = <&hsp_sp_csr 0x800 0x818>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0167-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch b/SPECS/linux-lts/0167-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch deleted file mode 100644 index 9f4bf625b0..0000000000 --- a/SPECS/linux-lts/0167-UPSTREAM-dt-bindings-usb-add-missed-compatible-strin.patch +++ /dev/null @@ -1,96 +0,0 @@ -From c8008d5da7b2415832577084ccba87ecd7a44f39 Mon Sep 17 00:00:00 2001 -From: Frank Li -Date: Mon, 29 Sep 2025 10:24:14 -0400 -Subject: [PATCH 167/467] UPSTREAM: dt-bindings: usb: add missed compatible - string for arm64 layerscape - -Add missed compatible string for arm64 layerscape platform. Allow these -fallback to fsl,ls1028a-dwc3. - -Remove fallback snps,dwc3 because layerscape dwc3 is not full compatible -with common snps,dwc3 device, a special value gsburstcfg0 need be set when -dma coherence enabled. - -Allow iommus property. - -Change ref to snps,dwc3-common.yaml to use dwc3 flatten library. - -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Frank Li -Link: https://lore.kernel.org/r/20250929-ls_dma_coherence-v5-1-2ebee578eb7e@nxp.com -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit b9f1c762a4de17d93017fbd12b9941caff6d3078) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/usb/fsl,ls1028a.yaml | 33 ++++++++++--------- - 1 file changed, 18 insertions(+), 15 deletions(-) - -diff --git a/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml b/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml -index a44bdf391887..4784f057264a 100644 ---- a/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml -+++ b/Documentation/devicetree/bindings/usb/fsl,ls1028a.yaml -@@ -9,21 +9,19 @@ title: Freescale layerscape SuperSpeed DWC3 USB SoC controller - maintainers: - - Frank Li - --select: -- properties: -- compatible: -- contains: -- enum: -- - fsl,ls1028a-dwc3 -- required: -- - compatible -- - properties: - compatible: -- items: -- - enum: -- - fsl,ls1028a-dwc3 -- - const: snps,dwc3 -+ oneOf: -+ - items: -+ - enum: -+ - fsl,ls1012a-dwc3 -+ - fsl,ls1043a-dwc3 -+ - fsl,ls1046a-dwc3 -+ - fsl,ls1088a-dwc3 -+ - fsl,ls208xa-dwc3 -+ - fsl,lx2160a-dwc3 -+ - const: fsl,ls1028a-dwc3 -+ - const: fsl,ls1028a-dwc3 - - reg: - maxItems: 1 -@@ -31,6 +29,11 @@ properties: - interrupts: - maxItems: 1 - -+ iommus: -+ maxItems: 1 -+ -+ dma-coherent: true -+ - unevaluatedProperties: false - - required: -@@ -39,14 +42,14 @@ required: - - interrupts - - allOf: -- - $ref: snps,dwc3.yaml# -+ - $ref: snps,dwc3-common.yaml# - - examples: - - | - #include - - usb@fe800000 { -- compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; -+ compatible = "fsl,ls1028a-dwc3"; - reg = <0xfe800000 0x100000>; - interrupts = ; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0168-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch b/SPECS/linux-lts/0168-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch deleted file mode 100644 index 9c997b8d12..0000000000 --- a/SPECS/linux-lts/0168-UPSTREAM-usb-dwc3-Add-software-managed-properties-fo.patch +++ /dev/null @@ -1,135 +0,0 @@ -From ec754531fae0f05264d641470206d128b8955455 Mon Sep 17 00:00:00 2001 -From: Frank Li -Date: Mon, 29 Sep 2025 10:24:15 -0400 -Subject: [PATCH 168/467] UPSTREAM: usb: dwc3: Add software-managed properties - for flattened model - -Add software-managed properties for the flattened model, which does not -need to use device tree properties to pass down information to the -common DWC3 core. - -Add 'properties' in dwc3_probe_data and set default values for existing -users (dwc3-qcom, dwc3-generic-plat). - -No functional changes. - -Acked-by: Thinh Nguyen -Signed-off-by: Frank Li -Link: https://lore.kernel.org/r/20250929-ls_dma_coherence-v5-2-2ebee578eb7e@nxp.com -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit 7298c06d58e23c1c6e60180ab1ce069087ae38e2) -Signed-off-by: Han Gao ---- - drivers/usb/dwc3/core.c | 12 ++++++++++-- - drivers/usb/dwc3/dwc3-generic-plat.c | 1 + - drivers/usb/dwc3/dwc3-qcom.c | 1 + - drivers/usb/dwc3/glue.h | 14 ++++++++++++++ - 4 files changed, 26 insertions(+), 2 deletions(-) - -diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c -index a1f99c3b5f37..dd08b7f5b9a1 100644 ---- a/drivers/usb/dwc3/core.c -+++ b/drivers/usb/dwc3/core.c -@@ -1669,7 +1669,8 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc) - dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true); - } - --static void dwc3_get_software_properties(struct dwc3 *dwc) -+static void dwc3_get_software_properties(struct dwc3 *dwc, -+ const struct dwc3_properties *properties) - { - struct device *tmpdev; - u16 gsbuscfg0_reqinfo; -@@ -1677,6 +1678,12 @@ static void dwc3_get_software_properties(struct dwc3 *dwc) - - dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED; - -+ if (properties->gsbuscfg0_reqinfo != -+ DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) { -+ dwc->gsbuscfg0_reqinfo = properties->gsbuscfg0_reqinfo; -+ return; -+ } -+ - /* - * Iterate over all parent nodes for finding swnode properties - * and non-DT (non-ABI) properties. -@@ -2224,7 +2231,7 @@ int dwc3_core_probe(const struct dwc3_probe_data *data) - - dwc3_get_properties(dwc); - -- dwc3_get_software_properties(dwc); -+ dwc3_get_software_properties(dwc, &data->properties); - - dwc->usb_psy = dwc3_get_usb_power_supply(dwc); - if (IS_ERR(dwc->usb_psy)) -@@ -2374,6 +2381,7 @@ static int dwc3_probe(struct platform_device *pdev) - - probe_data.dwc = dwc; - probe_data.res = res; -+ probe_data.properties = DWC3_DEFAULT_PROPERTIES; - - return dwc3_core_probe(&probe_data); - } -diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c -index f8ad79c08c4e..ba3aec4cb963 100644 ---- a/drivers/usb/dwc3/dwc3-generic-plat.c -+++ b/drivers/usb/dwc3/dwc3-generic-plat.c -@@ -75,6 +75,7 @@ static int dwc3_generic_probe(struct platform_device *pdev) - probe_data.dwc = &dwc3g->dwc; - probe_data.res = res; - probe_data.ignore_clocks_and_resets = true; -+ probe_data.properties = DWC3_DEFAULT_PROPERTIES; - ret = dwc3_core_probe(&probe_data); - if (ret) - return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); -diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c -index ded2ca86670c..9ac75547820d 100644 ---- a/drivers/usb/dwc3/dwc3-qcom.c -+++ b/drivers/usb/dwc3/dwc3-qcom.c -@@ -704,6 +704,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev) - probe_data.dwc = &qcom->dwc; - probe_data.res = &res; - probe_data.ignore_clocks_and_resets = true; -+ probe_data.properties = DWC3_DEFAULT_PROPERTIES; - ret = dwc3_core_probe(&probe_data); - if (ret) { - ret = dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); -diff --git a/drivers/usb/dwc3/glue.h b/drivers/usb/dwc3/glue.h -index 2efd00e763be..cc6e138bd9ef 100644 ---- a/drivers/usb/dwc3/glue.h -+++ b/drivers/usb/dwc3/glue.h -@@ -9,17 +9,31 @@ - #include - #include "core.h" - -+/** -+ * dwc3_properties: DWC3 core properties -+ * @gsbuscfg0_reqinfo: Value to be programmed in the GSBUSCFG0.REQINFO field -+ */ -+struct dwc3_properties { -+ u32 gsbuscfg0_reqinfo; -+}; -+ -+#define DWC3_DEFAULT_PROPERTIES ((struct dwc3_properties){ \ -+ .gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED, \ -+ }) -+ - /** - * dwc3_probe_data: Initialization parameters passed to dwc3_core_probe() - * @dwc: Reference to dwc3 context structure - * @res: resource for the DWC3 core mmio region - * @ignore_clocks_and_resets: clocks and resets defined for the device should - * be ignored by the DWC3 core, as they are managed by the glue -+ * @properties: dwc3 software manage properties - */ - struct dwc3_probe_data { - struct dwc3 *dwc; - struct resource *res; - bool ignore_clocks_and_resets; -+ struct dwc3_properties properties; - }; - - int dwc3_core_probe(const struct dwc3_probe_data *data); --- -2.53.0 - diff --git a/SPECS/linux-lts/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch b/SPECS/linux-lts/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch new file mode 100644 index 0000000000..c664c16a80 --- /dev/null +++ b/SPECS/linux-lts/0168-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch @@ -0,0 +1,149 @@ +From a2ce6ee9f23da731a7f30c0869f5b48c66d727e1 Mon Sep 17 00:00:00 2001 +From: Hang Cao +Date: Wed, 12 Nov 2025 13:53:45 +0800 +Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: eic7700: Add EIC7700 USB driver + +The EIC7700 instantiates two USB 3.0 DWC3 IPs, each of which is backward +compatible with USB interfaces. It supports Super-speed (5Gb/s), DRD mode, +and compatible with xHCI 1.1, etc. Each of instances supports 16 endpoints +in device's mode and max 64 devices in host's mode. + +This module needs to interact with the NOC via the AXI master bus, thus +requiring some HSP configuration operations to achieve this. Ops include +bus filter, pm signal or status to usb bus and so on. + +Acked-by: Thinh Nguyen +Signed-off-by: Senchuan Zhang +Signed-off-by: Hang Cao +Link: https://patch.msgid.link/20251112055346.1655-1-caohang@eswincomputing.com +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit e05d28b759c28660c28a36bf0add178edcc3466e) +Signed-off-by: Han Gao +--- + drivers/usb/dwc3/dwc3-generic-plat.c | 71 +++++++++++++++++++++++++--- + 1 file changed, 64 insertions(+), 7 deletions(-) + +diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c +index e869c7de7bc8..e846844e0023 100644 +--- a/drivers/usb/dwc3/dwc3-generic-plat.c ++++ b/drivers/usb/dwc3/dwc3-generic-plat.c +@@ -10,8 +10,16 @@ + #include + #include + #include ++#include ++#include + #include "glue.h" + ++#define EIC7700_HSP_BUS_FILTER_EN BIT(0) ++#define EIC7700_HSP_BUS_CLKEN_GM BIT(9) ++#define EIC7700_HSP_BUS_CLKEN_GS BIT(16) ++#define EIC7700_HSP_AXI_LP_XM_CSYSREQ BIT(0) ++#define EIC7700_HSP_AXI_LP_XS_CSYSREQ BIT(16) ++ + struct dwc3_generic { + struct device *dev; + struct dwc3 dwc; +@@ -20,6 +28,11 @@ struct dwc3_generic { + struct reset_control *resets; + }; + ++struct dwc3_generic_config { ++ int (*init)(struct dwc3_generic *dwc3g); ++ struct dwc3_properties properties; ++}; ++ + #define to_dwc3_generic(d) container_of((d), struct dwc3_generic, dwc) + + static void dwc3_generic_reset_control_assert(void *data) +@@ -27,9 +40,38 @@ static void dwc3_generic_reset_control_assert(void *data) + reset_control_assert(data); + } + ++static int dwc3_eic7700_init(struct dwc3_generic *dwc3g) ++{ ++ struct device *dev = dwc3g->dev; ++ struct regmap *regmap; ++ u32 hsp_usb_axi_lp; ++ u32 hsp_usb_bus; ++ u32 args[2]; ++ u32 val; ++ ++ regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, ++ "eswin,hsp-sp-csr", ++ ARRAY_SIZE(args), args); ++ if (IS_ERR(regmap)) { ++ dev_err(dev, "No hsp-sp-csr phandle specified\n"); ++ return PTR_ERR(regmap); ++ } ++ ++ hsp_usb_bus = args[0]; ++ hsp_usb_axi_lp = args[1]; ++ ++ regmap_read(regmap, hsp_usb_bus, &val); ++ regmap_write(regmap, hsp_usb_bus, val | EIC7700_HSP_BUS_FILTER_EN | ++ EIC7700_HSP_BUS_CLKEN_GM | EIC7700_HSP_BUS_CLKEN_GS); ++ ++ regmap_write(regmap, hsp_usb_axi_lp, EIC7700_HSP_AXI_LP_XM_CSYSREQ | ++ EIC7700_HSP_AXI_LP_XS_CSYSREQ); ++ return 0; ++} ++ + static int dwc3_generic_probe(struct platform_device *pdev) + { +- const struct dwc3_properties *properties; ++ const struct dwc3_generic_config *plat_config; + struct dwc3_probe_data probe_data = {}; + struct device *dev = &pdev->dev; + struct dwc3_generic *dwc3g; +@@ -77,12 +119,21 @@ static int dwc3_generic_probe(struct platform_device *pdev) + probe_data.res = res; + probe_data.ignore_clocks_and_resets = true; + +- properties = of_device_get_match_data(dev); +- if (properties) +- probe_data.properties = *properties; +- else ++ plat_config = of_device_get_match_data(dev); ++ if (!plat_config) { + probe_data.properties = DWC3_DEFAULT_PROPERTIES; ++ goto core_probe; ++ } + ++ probe_data.properties = plat_config->properties; ++ if (plat_config->init) { ++ ret = plat_config->init(dwc3g); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "failed to init platform\n"); ++ } ++ ++core_probe: + ret = dwc3_core_probe(&probe_data); + if (ret) + return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); +@@ -150,13 +201,19 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { + dwc3_generic_runtime_idle) + }; + +-static const struct dwc3_properties fsl_ls1028_dwc3 = { +- .gsbuscfg0_reqinfo = 0x2222, ++static const struct dwc3_generic_config fsl_ls1028_dwc3 = { ++ .properties.gsbuscfg0_reqinfo = 0x2222, ++}; ++ ++static const struct dwc3_generic_config eic7700_dwc3 = { ++ .init = dwc3_eic7700_init, ++ .properties = DWC3_DEFAULT_PROPERTIES, + }; + + static const struct of_device_id dwc3_generic_of_match[] = { + { .compatible = "spacemit,k1-dwc3", }, + { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, ++ { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch b/SPECS/linux-lts/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch new file mode 100644 index 0000000000..0830c4cd17 --- /dev/null +++ b/SPECS/linux-lts/0169-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch @@ -0,0 +1,58 @@ +From 9acac5b146b312ddb8525d13c2ba273dff6508a0 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 16 Feb 2026 23:26:53 +0800 +Subject: [RUYI PATCH] UPSTREAM: phy: k1-usb: add disconnect function support + +A disconnect status BIT of USB2 PHY need to be cleared, otherwise +it will fail to work properly during next connection when devices +connect to roothub directly. + +Fixes: fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller") +Signed-off-by: Yixun Lan +Reviewed-by: Vladimir Oltean +Link: https://patch.msgid.link/20260216152653.25244-1-dlan@kernel.org +Signed-off-by: Vinod Koul +(cherry picked from commit f0cf0a882a02dcf28547f32264f6fd37e9a7b147) +Signed-off-by: Han Gao +--- + drivers/phy/spacemit/phy-k1-usb2.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c +index 342061380012..9215d0b223b2 100644 +--- a/drivers/phy/spacemit/phy-k1-usb2.c ++++ b/drivers/phy/spacemit/phy-k1-usb2.c +@@ -48,6 +48,9 @@ + #define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */ + #define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */ + ++#define PHY_K1_HS_HOST_DISC 0x40 ++#define PHY_K1_HS_HOST_DISC_CLR BIT(0) ++ + #define PHY_PLL_DIV_CFG 0x98 + #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) + #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) +@@ -142,9 +145,20 @@ static int spacemit_usb2phy_exit(struct phy *phy) + return 0; + } + ++static int spacemit_usb2phy_disconnect(struct phy *phy, int port) ++{ ++ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); ++ ++ regmap_update_bits(sphy->regmap_base, PHY_K1_HS_HOST_DISC, ++ PHY_K1_HS_HOST_DISC_CLR, PHY_K1_HS_HOST_DISC_CLR); ++ ++ return 0; ++} ++ + static const struct phy_ops spacemit_usb2phy_ops = { + .init = spacemit_usb2phy_init, + .exit = spacemit_usb2phy_exit, ++ .disconnect = spacemit_usb2phy_disconnect, + .owner = THIS_MODULE, + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0169-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch b/SPECS/linux-lts/0169-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch deleted file mode 100644 index 5518a57821..0000000000 --- a/SPECS/linux-lts/0169-UPSTREAM-usb-dwc3-dwc3-generic-plat-Add-layerscape-d.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 2ad4fd487b3a00d0f606fecc70edc0fe56d6b43e Mon Sep 17 00:00:00 2001 -From: Frank Li -Date: Mon, 29 Sep 2025 10:24:16 -0400 -Subject: [PATCH 169/467] UPSTREAM: usb: dwc3: dwc3-generic-plat: Add - layerscape dwc3 support - -Add layerscape dwc3 support by using flatten dwc3 core library. Layerscape -dwc3 need set gsbuscfg0-reqinfo as 0x2222 when dma-coherence set. - -Signed-off-by: Frank Li -Acked-by: Thinh Nguyen -Link: https://lore.kernel.org/r/20250929-ls_dma_coherence-v5-3-2ebee578eb7e@nxp.com -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit 1c97fc901fb6318aca0160da96736d0bc136ddcd) -Signed-off-by: Han Gao ---- - drivers/usb/dwc3/dwc3-generic-plat.c | 14 +++++++++++++- - 1 file changed, 13 insertions(+), 1 deletion(-) - -diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c -index ba3aec4cb963..e869c7de7bc8 100644 ---- a/drivers/usb/dwc3/dwc3-generic-plat.c -+++ b/drivers/usb/dwc3/dwc3-generic-plat.c -@@ -29,6 +29,7 @@ static void dwc3_generic_reset_control_assert(void *data) - - static int dwc3_generic_probe(struct platform_device *pdev) - { -+ const struct dwc3_properties *properties; - struct dwc3_probe_data probe_data = {}; - struct device *dev = &pdev->dev; - struct dwc3_generic *dwc3g; -@@ -75,7 +76,13 @@ static int dwc3_generic_probe(struct platform_device *pdev) - probe_data.dwc = &dwc3g->dwc; - probe_data.res = res; - probe_data.ignore_clocks_and_resets = true; -- probe_data.properties = DWC3_DEFAULT_PROPERTIES; -+ -+ properties = of_device_get_match_data(dev); -+ if (properties) -+ probe_data.properties = *properties; -+ else -+ probe_data.properties = DWC3_DEFAULT_PROPERTIES; -+ - ret = dwc3_core_probe(&probe_data); - if (ret) - return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); -@@ -143,8 +150,13 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { - dwc3_generic_runtime_idle) - }; - -+static const struct dwc3_properties fsl_ls1028_dwc3 = { -+ .gsbuscfg0_reqinfo = 0x2222, -+}; -+ - static const struct of_device_id dwc3_generic_of_match[] = { - { .compatible = "spacemit,k1-dwc3", }, -+ { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); --- -2.53.0 - diff --git a/SPECS/linux-lts/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch b/SPECS/linux-lts/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch new file mode 100644 index 0000000000..f563981345 --- /dev/null +++ b/SPECS/linux-lts/0170-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch @@ -0,0 +1,49 @@ +From 8aba9c8ffd6f7bf33950abcc2bb276254f6749cf Mon Sep 17 00:00:00 2001 +From: Nirmoy Das +Date: Wed, 17 Dec 2025 07:45:28 -0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: Add ASPEED vendor ID to pci_ids.h + +Add PCI_VENDOR_ID_ASPEED to the shared pci_ids.h header and remove the +duplicate local definition from ehci-pci.c. + +This prepares for adding a PCI quirk for ASPEED devices. + +Signed-off-by: Nirmoy Das +Signed-off-by: Bjorn Helgaas +Reviewed-by: Jason Gunthorpe +Link: https://patch.msgid.link/20251217154529.377586-1-nirmoyd@nvidia.com +(cherry picked from commit eeb95c07d5fcaafb1829d5307ce4290cf1dc3190) +Signed-off-by: Han Gao +--- + drivers/usb/host/ehci-pci.c | 1 - + include/linux/pci_ids.h | 2 ++ + 2 files changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c +index 889dc4426271..bd3a63555594 100644 +--- a/drivers/usb/host/ehci-pci.c ++++ b/drivers/usb/host/ehci-pci.c +@@ -21,7 +21,6 @@ static const char hcd_name[] = "ehci-pci"; + /* defined here to avoid adding to pci_ids.h for single instance use */ + #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 + +-#define PCI_VENDOR_ID_ASPEED 0x1a03 + #define PCI_DEVICE_ID_ASPEED_EHCI 0x2603 + + /*-------------------------------------------------------------------------*/ +diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h +index 03b7c0380f71..2b6692a5005f 100644 +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2583,6 +2583,8 @@ + #define PCI_DEVICE_ID_NETRONOME_NFP3800_VF 0x3803 + #define PCI_DEVICE_ID_NETRONOME_NFP6000_VF 0x6003 + ++#define PCI_VENDOR_ID_ASPEED 0x1a03 ++ + #define PCI_VENDOR_ID_QMI 0x1a32 + + #define PCI_VENDOR_ID_AZWAVE 0x1a3b +-- +2.53.0 + diff --git a/SPECS/linux-lts/0170-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch b/SPECS/linux-lts/0170-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch deleted file mode 100644 index 6b5f344dd1..0000000000 --- a/SPECS/linux-lts/0170-UPSTREAM-dt-bindings-usb-Add-ESWIN-EIC7700-USB-contr.patch +++ /dev/null @@ -1,124 +0,0 @@ -From fd6aed5b51bb1817267103bf54285d06b25b5d2f Mon Sep 17 00:00:00 2001 -From: Hang Cao -Date: Wed, 12 Nov 2025 13:53:21 +0800 -Subject: [PATCH 170/467] UPSTREAM: dt-bindings: usb: Add ESWIN EIC7700 USB - controller - -Add Device Tree binding documentation for the ESWIN EIC7700 -usb controller module. - -Signed-off-by: Senchuan Zhang -Signed-off-by: Hang Cao -Reviewed-by: Rob Herring (Arm) -Link: https://patch.msgid.link/20251112055321.1638-1-caohang@eswincomputing.com -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit c640a4239db53e077dd5fd20db52fbc8b64f290b) -Signed-off-by: Han Gao ---- - .../bindings/usb/eswin,eic7700-usb.yaml | 94 +++++++++++++++++++ - 1 file changed, 94 insertions(+) - create mode 100644 Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml - -diff --git a/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml -new file mode 100644 -index 000000000000..41c3b1b98991 ---- /dev/null -+++ b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml -@@ -0,0 +1,94 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/usb/eswin,eic7700-usb.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: ESWIN EIC7700 SoC Usb Controller -+ -+maintainers: -+ - Wei Yang -+ - Senchuan Zhang -+ - Hang Cao -+ -+description: -+ The Usb controller on EIC7700 SoC. -+ -+allOf: -+ - $ref: snps,dwc3-common.yaml# -+ -+properties: -+ compatible: -+ const: eswin,eic7700-dwc3 -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ interrupt-names: -+ items: -+ - const: peripheral -+ -+ clocks: -+ maxItems: 3 -+ -+ clock-names: -+ items: -+ - const: aclk -+ - const: cfg -+ - const: usb_en -+ -+ resets: -+ maxItems: 2 -+ -+ reset-names: -+ items: -+ - const: vaux -+ - const: usb_rst -+ -+ eswin,hsp-sp-csr: -+ description: -+ HSP CSR is to control and get status of different high-speed peripherals -+ (such as Ethernet, USB, SATA, etc.) via register, which can tune -+ board-level's parameters of PHY, etc. -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ items: -+ - items: -+ - description: phandle to HSP Register Controller hsp_sp_csr node. -+ - description: USB bus register offset. -+ - description: AXI low power register offset. -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - interrupt-names -+ - resets -+ - reset-names -+ - eswin,hsp-sp-csr -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ usb@50480000 { -+ compatible = "eswin,eic7700-dwc3"; -+ reg = <0x50480000 0x10000>; -+ clocks = <&clock 135>, -+ <&clock 136>, -+ <&hspcrg 18>; -+ clock-names = "aclk", "cfg", "usb_en"; -+ interrupt-parent = <&plic>; -+ interrupts = <85>; -+ interrupt-names = "peripheral"; -+ resets = <&reset 84>, <&hspcrg 2>; -+ reset-names = "vaux", "usb_rst"; -+ dr_mode = "peripheral"; -+ maximum-speed = "high-speed"; -+ phy_type = "utmi"; -+ eswin,hsp-sp-csr = <&hsp_sp_csr 0x800 0x818>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch b/SPECS/linux-lts/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch new file mode 100644 index 0000000000..dba743541d --- /dev/null +++ b/SPECS/linux-lts/0171-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch @@ -0,0 +1,89 @@ +From ebc23bfadb5fbe0d0f28b65fd9c6837238e6e941 Mon Sep 17 00:00:00 2001 +From: Nirmoy Das +Date: Wed, 17 Dec 2025 07:45:29 -0800 +Subject: [RUYI PATCH] UPSTREAM: PCI: Add PCI_BRIDGE_NO_ALIAS quirk for ASPEED + AST1150 + +ASPEED BMC controllers have VGA and USB functions behind a PCIe-to-PCI +bridge that causes them to share the same StreamID: + + [e0]---00.0-[e1-e2]----00.0-[e2]--+-00.0 ASPEED Graphics Family + \-02.0 ASPEED USB Controller + +Both devices get StreamID 0x5e200 due to bridge aliasing, causing the USB +controller to be rejected with 'Aliasing StreamID unsupported'. + +Per ASPEED, the AST1150 doesn't use a real PCI bus and always forwards +the original Requester ID from downstream devices rather than replacing +it with any alias. + +Add a new PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS flag and apply it to the +AST1150. + +Suggested-by: Jason Gunthorpe +Signed-off-by: Nirmoy Das +Signed-off-by: Bjorn Helgaas +Reviewed-by: Robin Murphy +Reviewed-by: Jason Gunthorpe +Link: https://patch.msgid.link/20251217154529.377586-2-nirmoyd@nvidia.com +(cherry picked from commit 550a190494a0d3e933dd6f3b2e9c430f94a30a8c) +Signed-off-by: Han Gao +--- + drivers/pci/quirks.c | 10 ++++++++++ + drivers/pci/search.c | 2 ++ + include/linux/pci.h | 5 +++++ + 3 files changed, 17 insertions(+) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index d32a47e81fcf..481e4186a5c1 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -4481,6 +4481,16 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, + quirk_bridge_cavm_thrx2_pcie_root); + ++/* ++ * AST1150 doesn't use a real PCI bus and always forwards the requester ID ++ * from downstream devices. ++ */ ++static void quirk_aspeed_pci_bridge_no_alias(struct pci_dev *pdev) ++{ ++ pdev->dev_flags |= PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS; ++} ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASPEED, 0x1150, quirk_aspeed_pci_bridge_no_alias); ++ + /* + * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) + * class code. Fix it. +diff --git a/drivers/pci/search.c b/drivers/pci/search.c +index 53840634fbfc..b3c9e3d82201 100644 +--- a/drivers/pci/search.c ++++ b/drivers/pci/search.c +@@ -86,6 +86,8 @@ int pci_for_each_dma_alias(struct pci_dev *pdev, + case PCI_EXP_TYPE_DOWNSTREAM: + continue; + case PCI_EXP_TYPE_PCI_BRIDGE: ++ if (tmp->dev_flags & PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS) ++ continue; + ret = fn(tmp, + PCI_DEVID(tmp->subordinate->number, + PCI_DEVFN(0, 0)), data); +diff --git a/include/linux/pci.h b/include/linux/pci.h +index 3ea77b9c5901..cdf67f5aa239 100644 +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -248,6 +248,11 @@ enum pci_dev_flags { + PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), + /* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */ + PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13), ++ /* ++ * PCIe to PCI bridge does not create RID aliases because the bridge is ++ * integrated with the downstream devices and doesn't use real PCI. ++ */ ++ PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = (__force pci_dev_flags_t) (1 << 14), + }; + + enum pci_irq_reroute_variant { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0171-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch b/SPECS/linux-lts/0171-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch deleted file mode 100644 index 7144558c46..0000000000 --- a/SPECS/linux-lts/0171-UPSTREAM-usb-dwc3-eic7700-Add-EIC7700-USB-driver.patch +++ /dev/null @@ -1,149 +0,0 @@ -From 76caa8b77c6909d2488024da63eb6de0ae401844 Mon Sep 17 00:00:00 2001 -From: Hang Cao -Date: Wed, 12 Nov 2025 13:53:45 +0800 -Subject: [PATCH 171/467] UPSTREAM: usb: dwc3: eic7700: Add EIC7700 USB driver - -The EIC7700 instantiates two USB 3.0 DWC3 IPs, each of which is backward -compatible with USB interfaces. It supports Super-speed (5Gb/s), DRD mode, -and compatible with xHCI 1.1, etc. Each of instances supports 16 endpoints -in device's mode and max 64 devices in host's mode. - -This module needs to interact with the NOC via the AXI master bus, thus -requiring some HSP configuration operations to achieve this. Ops include -bus filter, pm signal or status to usb bus and so on. - -Acked-by: Thinh Nguyen -Signed-off-by: Senchuan Zhang -Signed-off-by: Hang Cao -Link: https://patch.msgid.link/20251112055346.1655-1-caohang@eswincomputing.com -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit e05d28b759c28660c28a36bf0add178edcc3466e) -Signed-off-by: Han Gao ---- - drivers/usb/dwc3/dwc3-generic-plat.c | 71 +++++++++++++++++++++++++--- - 1 file changed, 64 insertions(+), 7 deletions(-) - -diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c -index e869c7de7bc8..e846844e0023 100644 ---- a/drivers/usb/dwc3/dwc3-generic-plat.c -+++ b/drivers/usb/dwc3/dwc3-generic-plat.c -@@ -10,8 +10,16 @@ - #include - #include - #include -+#include -+#include - #include "glue.h" - -+#define EIC7700_HSP_BUS_FILTER_EN BIT(0) -+#define EIC7700_HSP_BUS_CLKEN_GM BIT(9) -+#define EIC7700_HSP_BUS_CLKEN_GS BIT(16) -+#define EIC7700_HSP_AXI_LP_XM_CSYSREQ BIT(0) -+#define EIC7700_HSP_AXI_LP_XS_CSYSREQ BIT(16) -+ - struct dwc3_generic { - struct device *dev; - struct dwc3 dwc; -@@ -20,6 +28,11 @@ struct dwc3_generic { - struct reset_control *resets; - }; - -+struct dwc3_generic_config { -+ int (*init)(struct dwc3_generic *dwc3g); -+ struct dwc3_properties properties; -+}; -+ - #define to_dwc3_generic(d) container_of((d), struct dwc3_generic, dwc) - - static void dwc3_generic_reset_control_assert(void *data) -@@ -27,9 +40,38 @@ static void dwc3_generic_reset_control_assert(void *data) - reset_control_assert(data); - } - -+static int dwc3_eic7700_init(struct dwc3_generic *dwc3g) -+{ -+ struct device *dev = dwc3g->dev; -+ struct regmap *regmap; -+ u32 hsp_usb_axi_lp; -+ u32 hsp_usb_bus; -+ u32 args[2]; -+ u32 val; -+ -+ regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, -+ "eswin,hsp-sp-csr", -+ ARRAY_SIZE(args), args); -+ if (IS_ERR(regmap)) { -+ dev_err(dev, "No hsp-sp-csr phandle specified\n"); -+ return PTR_ERR(regmap); -+ } -+ -+ hsp_usb_bus = args[0]; -+ hsp_usb_axi_lp = args[1]; -+ -+ regmap_read(regmap, hsp_usb_bus, &val); -+ regmap_write(regmap, hsp_usb_bus, val | EIC7700_HSP_BUS_FILTER_EN | -+ EIC7700_HSP_BUS_CLKEN_GM | EIC7700_HSP_BUS_CLKEN_GS); -+ -+ regmap_write(regmap, hsp_usb_axi_lp, EIC7700_HSP_AXI_LP_XM_CSYSREQ | -+ EIC7700_HSP_AXI_LP_XS_CSYSREQ); -+ return 0; -+} -+ - static int dwc3_generic_probe(struct platform_device *pdev) - { -- const struct dwc3_properties *properties; -+ const struct dwc3_generic_config *plat_config; - struct dwc3_probe_data probe_data = {}; - struct device *dev = &pdev->dev; - struct dwc3_generic *dwc3g; -@@ -77,12 +119,21 @@ static int dwc3_generic_probe(struct platform_device *pdev) - probe_data.res = res; - probe_data.ignore_clocks_and_resets = true; - -- properties = of_device_get_match_data(dev); -- if (properties) -- probe_data.properties = *properties; -- else -+ plat_config = of_device_get_match_data(dev); -+ if (!plat_config) { - probe_data.properties = DWC3_DEFAULT_PROPERTIES; -+ goto core_probe; -+ } - -+ probe_data.properties = plat_config->properties; -+ if (plat_config->init) { -+ ret = plat_config->init(dwc3g); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "failed to init platform\n"); -+ } -+ -+core_probe: - ret = dwc3_core_probe(&probe_data); - if (ret) - return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); -@@ -150,13 +201,19 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { - dwc3_generic_runtime_idle) - }; - --static const struct dwc3_properties fsl_ls1028_dwc3 = { -- .gsbuscfg0_reqinfo = 0x2222, -+static const struct dwc3_generic_config fsl_ls1028_dwc3 = { -+ .properties.gsbuscfg0_reqinfo = 0x2222, -+}; -+ -+static const struct dwc3_generic_config eic7700_dwc3 = { -+ .init = dwc3_eic7700_init, -+ .properties = DWC3_DEFAULT_PROPERTIES, - }; - - static const struct of_device_id dwc3_generic_of_match[] = { - { .compatible = "spacemit,k1-dwc3", }, - { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, -+ { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); --- -2.53.0 - diff --git a/SPECS/linux-lts/0172-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch b/SPECS/linux-lts/0172-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch deleted file mode 100644 index 324034713f..0000000000 --- a/SPECS/linux-lts/0172-UPSTREAM-phy-k1-usb-add-disconnect-function-support.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 7ce945a45771d022307a72be01e01ba8f621f6ae Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 16 Feb 2026 23:26:53 +0800 -Subject: [PATCH 172/467] UPSTREAM: phy: k1-usb: add disconnect function - support - -A disconnect status BIT of USB2 PHY need to be cleared, otherwise -it will fail to work properly during next connection when devices -connect to roothub directly. - -Fixes: fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller") -Signed-off-by: Yixun Lan -Reviewed-by: Vladimir Oltean -Link: https://patch.msgid.link/20260216152653.25244-1-dlan@kernel.org -Signed-off-by: Vinod Koul -(cherry picked from commit f0cf0a882a02dcf28547f32264f6fd37e9a7b147) -Signed-off-by: Han Gao ---- - drivers/phy/spacemit/phy-k1-usb2.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c -index 342061380012..9215d0b223b2 100644 ---- a/drivers/phy/spacemit/phy-k1-usb2.c -+++ b/drivers/phy/spacemit/phy-k1-usb2.c -@@ -48,6 +48,9 @@ - #define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */ - #define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */ - -+#define PHY_K1_HS_HOST_DISC 0x40 -+#define PHY_K1_HS_HOST_DISC_CLR BIT(0) -+ - #define PHY_PLL_DIV_CFG 0x98 - #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) - #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) -@@ -142,9 +145,20 @@ static int spacemit_usb2phy_exit(struct phy *phy) - return 0; - } - -+static int spacemit_usb2phy_disconnect(struct phy *phy, int port) -+{ -+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); -+ -+ regmap_update_bits(sphy->regmap_base, PHY_K1_HS_HOST_DISC, -+ PHY_K1_HS_HOST_DISC_CLR, PHY_K1_HS_HOST_DISC_CLR); -+ -+ return 0; -+} -+ - static const struct phy_ops spacemit_usb2phy_ops = { - .init = spacemit_usb2phy_init, - .exit = spacemit_usb2phy_exit, -+ .disconnect = spacemit_usb2phy_disconnect, - .owner = THIS_MODULE, - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch b/SPECS/linux-lts/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch new file mode 100644 index 0000000000..b717a1f71f --- /dev/null +++ b/SPECS/linux-lts/0172-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch @@ -0,0 +1,72 @@ +From 9b54a8b4866b22ba764ced5eadb4df836758c46b Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Mon, 23 Mar 2026 17:43:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: patch: Avoid early phys_to_page() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Similarly to commit 8d09e2d569f6 ("arm64: patching: avoid early +page_to_phys()"), avoid using phys_to_page() for the kernel address case +in patch_map(). + +Since this is called from apply_boot_alternatives() in setup_arch(), and +commit 4267739cabb8 ("arch, mm: consolidate initialization of SPARSE +memory model") has moved sparse_init() to after setup_arch(), +phys_to_page() is not available there yet, and it panics on boot with +SPARSEMEM on RV32, which does not use SPARSEMEM_VMEMMAP. + +Reported-by: Thomas Weißschuh +Closes: https://lore.kernel.org/r/20260223144108-dcace0b9-02e8-4b67-a7ce-f263bed36f26@linutronix.de/ +Fixes: 4267739cabb8 ("arch, mm: consolidate initialization of SPARSE memory model") +Suggested-by: Mike Rapoport +Signed-off-by: Vivian Wang +Acked-by: Mike Rapoport (Microsoft) +Tested-by: Thomas Weißschuh +Link: https://patch.msgid.link/20260310-riscv-sparsemem-alternatives-fix-v1-1-659d5dd257e2@iscas.ac.cn +[pjw@kernel.org: fix the subject line to align with the patch description] +Signed-off-by: Paul Walmsley +(cherry picked from commit 6b60a128c2f43180664a614830f3c529497e0394) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/patch.c | 21 +++++++++++---------- + 1 file changed, 11 insertions(+), 10 deletions(-) + +diff --git a/arch/riscv/kernel/patch.c b/arch/riscv/kernel/patch.c +index db13c9ddf9e3..16b243376f36 100644 +--- a/arch/riscv/kernel/patch.c ++++ b/arch/riscv/kernel/patch.c +@@ -42,19 +42,20 @@ static inline bool is_kernel_exittext(uintptr_t addr) + static __always_inline void *patch_map(void *addr, const unsigned int fixmap) + { + uintptr_t uintaddr = (uintptr_t) addr; +- struct page *page; ++ phys_addr_t phys; + +- if (core_kernel_text(uintaddr) || is_kernel_exittext(uintaddr)) +- page = phys_to_page(__pa_symbol(addr)); +- else if (IS_ENABLED(CONFIG_STRICT_MODULE_RWX)) +- page = vmalloc_to_page(addr); +- else +- return addr; ++ if (core_kernel_text(uintaddr) || is_kernel_exittext(uintaddr)) { ++ phys = __pa_symbol(addr); ++ } else if (IS_ENABLED(CONFIG_STRICT_MODULE_RWX)) { ++ struct page *page = vmalloc_to_page(addr); + +- BUG_ON(!page); ++ BUG_ON(!page); ++ phys = page_to_phys(page) + offset_in_page(addr); ++ } else { ++ return addr; ++ } + +- return (void *)set_fixmap_offset(fixmap, page_to_phys(page) + +- offset_in_page(addr)); ++ return (void *)set_fixmap_offset(fixmap, phys); + } + + static void patch_unmap(int fixmap) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0173-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch b/SPECS/linux-lts/0173-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch deleted file mode 100644 index 33ff2c2664..0000000000 --- a/SPECS/linux-lts/0173-UPSTREAM-PCI-Add-ASPEED-vendor-ID-to-pci_ids.h.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 6b3c31276fbb62225261d4063f231152756c3c24 Mon Sep 17 00:00:00 2001 -From: Nirmoy Das -Date: Wed, 17 Dec 2025 07:45:28 -0800 -Subject: [PATCH 173/467] UPSTREAM: PCI: Add ASPEED vendor ID to pci_ids.h - -Add PCI_VENDOR_ID_ASPEED to the shared pci_ids.h header and remove the -duplicate local definition from ehci-pci.c. - -This prepares for adding a PCI quirk for ASPEED devices. - -Signed-off-by: Nirmoy Das -Signed-off-by: Bjorn Helgaas -Reviewed-by: Jason Gunthorpe -Link: https://patch.msgid.link/20251217154529.377586-1-nirmoyd@nvidia.com -(cherry picked from commit eeb95c07d5fcaafb1829d5307ce4290cf1dc3190) -Signed-off-by: Han Gao ---- - drivers/usb/host/ehci-pci.c | 1 - - include/linux/pci_ids.h | 2 ++ - 2 files changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c -index 889dc4426271..bd3a63555594 100644 ---- a/drivers/usb/host/ehci-pci.c -+++ b/drivers/usb/host/ehci-pci.c -@@ -21,7 +21,6 @@ static const char hcd_name[] = "ehci-pci"; - /* defined here to avoid adding to pci_ids.h for single instance use */ - #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 - --#define PCI_VENDOR_ID_ASPEED 0x1a03 - #define PCI_DEVICE_ID_ASPEED_EHCI 0x2603 - - /*-------------------------------------------------------------------------*/ -diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h -index 03b7c0380f71..2b6692a5005f 100644 ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -2583,6 +2583,8 @@ - #define PCI_DEVICE_ID_NETRONOME_NFP3800_VF 0x3803 - #define PCI_DEVICE_ID_NETRONOME_NFP6000_VF 0x6003 - -+#define PCI_VENDOR_ID_ASPEED 0x1a03 -+ - #define PCI_VENDOR_ID_QMI 0x1a32 - - #define PCI_VENDOR_ID_AZWAVE 0x1a3b --- -2.53.0 - diff --git a/SPECS/linux-lts/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch b/SPECS/linux-lts/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch new file mode 100644 index 0000000000..7274ae6b1a --- /dev/null +++ b/SPECS/linux-lts/0173-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch @@ -0,0 +1,51 @@ +From 6727a0a8b7add2ff9543cd2e8e0f4e29a5a9b89a Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam +Date: Tue, 20 Jan 2026 23:17:44 +0530 +Subject: [RUYI PATCH] UPSTREAM: PCI: dwc: Fail dw_pcie_host_init() if + dw_pcie_wait_for_link() returns -ETIMEDOUT + +The dw_pcie_wait_for_link() API now distinguishes link failures more +precisely: + +-ENODEV: Device not found on the bus. +-EIO: Device found but inactive. +-ETIMEDOUT: Link failed to come up. + +Out of these three errors, only -ETIMEDOUT represents a definitive link +failure since it signals that something is wrong with the link. For the +other two errors, there is a possibility that the link might come up later. +So fail dw_pcie_host_init() if -ETIMEDOUT is returned and skip the failure +otherwise. + +Signed-off-by: Manivannan Sadhasivam +Reviewed-by: Niklas Cassel +Link: https://patch.msgid.link/20260120-pci-dwc-suspend-rework-v4-5-2f32d5082549@oss.qualcomm.com +(cherry picked from commit 86cbb7a81068434fdc1d5afb96d91ab971fb279e) +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c +index 993858fd0529..dbd4b66934df 100644 +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -664,8 +664,13 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) + goto err_remove_edma; + } + +- /* Ignore errors, the link may come up later */ +- dw_pcie_wait_for_link(pci); ++ /* ++ * Only fail on timeout error. Other errors indicate the device may ++ * become available later, so continue without failing. ++ */ ++ ret = dw_pcie_wait_for_link(pci); ++ if (ret == -ETIMEDOUT) ++ goto err_stop_link; + + ret = pci_host_probe(bridge); + if (ret) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0174-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch b/SPECS/linux-lts/0174-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch deleted file mode 100644 index 5c4614e51e..0000000000 --- a/SPECS/linux-lts/0174-UPSTREAM-PCI-Add-PCI_BRIDGE_NO_ALIAS-quirk-for-ASPEE.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 12f86c495ee4dc708c6b0b172a7518faf4303656 Mon Sep 17 00:00:00 2001 -From: Nirmoy Das -Date: Wed, 17 Dec 2025 07:45:29 -0800 -Subject: [PATCH 174/467] UPSTREAM: PCI: Add PCI_BRIDGE_NO_ALIAS quirk for - ASPEED AST1150 - -ASPEED BMC controllers have VGA and USB functions behind a PCIe-to-PCI -bridge that causes them to share the same StreamID: - - [e0]---00.0-[e1-e2]----00.0-[e2]--+-00.0 ASPEED Graphics Family - \-02.0 ASPEED USB Controller - -Both devices get StreamID 0x5e200 due to bridge aliasing, causing the USB -controller to be rejected with 'Aliasing StreamID unsupported'. - -Per ASPEED, the AST1150 doesn't use a real PCI bus and always forwards -the original Requester ID from downstream devices rather than replacing -it with any alias. - -Add a new PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS flag and apply it to the -AST1150. - -Suggested-by: Jason Gunthorpe -Signed-off-by: Nirmoy Das -Signed-off-by: Bjorn Helgaas -Reviewed-by: Robin Murphy -Reviewed-by: Jason Gunthorpe -Link: https://patch.msgid.link/20251217154529.377586-2-nirmoyd@nvidia.com -(cherry picked from commit 550a190494a0d3e933dd6f3b2e9c430f94a30a8c) -Signed-off-by: Han Gao ---- - drivers/pci/quirks.c | 10 ++++++++++ - drivers/pci/search.c | 2 ++ - include/linux/pci.h | 5 +++++ - 3 files changed, 17 insertions(+) - -diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index d32a47e81fcf..481e4186a5c1 100644 ---- a/drivers/pci/quirks.c -+++ b/drivers/pci/quirks.c -@@ -4481,6 +4481,16 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, - DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, - quirk_bridge_cavm_thrx2_pcie_root); - -+/* -+ * AST1150 doesn't use a real PCI bus and always forwards the requester ID -+ * from downstream devices. -+ */ -+static void quirk_aspeed_pci_bridge_no_alias(struct pci_dev *pdev) -+{ -+ pdev->dev_flags |= PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS; -+} -+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASPEED, 0x1150, quirk_aspeed_pci_bridge_no_alias); -+ - /* - * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) - * class code. Fix it. -diff --git a/drivers/pci/search.c b/drivers/pci/search.c -index 53840634fbfc..b3c9e3d82201 100644 ---- a/drivers/pci/search.c -+++ b/drivers/pci/search.c -@@ -86,6 +86,8 @@ int pci_for_each_dma_alias(struct pci_dev *pdev, - case PCI_EXP_TYPE_DOWNSTREAM: - continue; - case PCI_EXP_TYPE_PCI_BRIDGE: -+ if (tmp->dev_flags & PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS) -+ continue; - ret = fn(tmp, - PCI_DEVID(tmp->subordinate->number, - PCI_DEVFN(0, 0)), data); -diff --git a/include/linux/pci.h b/include/linux/pci.h -index 3ea77b9c5901..cdf67f5aa239 100644 ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -248,6 +248,11 @@ enum pci_dev_flags { - PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), - /* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */ - PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13), -+ /* -+ * PCIe to PCI bridge does not create RID aliases because the bridge is -+ * integrated with the downstream devices and doesn't use real PCI. -+ */ -+ PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = (__force pci_dev_flags_t) (1 << 14), - }; - - enum pci_irq_reroute_variant { --- -2.53.0 - diff --git a/SPECS/linux-lts/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch b/SPECS/linux-lts/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch new file mode 100644 index 0000000000..1cc4f9a6b9 --- /dev/null +++ b/SPECS/linux-lts/0174-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch @@ -0,0 +1,200 @@ +From a21ca9741cdf655d806097dd0285fc759b7550dd Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 20 Mar 2026 11:06:17 +0000 +Subject: [RUYI PATCH] UPSTREAM: reset: spacemit: k3: Decouple composite reset + lines + +Instead of grouping several different reset lines into one composite +reset, decouple them to individual ones which make it more aligned +with underlying hardware. And for DWC USB driver, it will match well +with the number of the reset property in the DT bindings. + +The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, +PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. +Also three reset lines each for UCIE and RCPU block. + +As an agreement with maintainer, the reset IDs has been rearranged as +contiguous number but keep most part unchanged to avoid break patches +which already sent to mailing list. The changes of DT binding header file +and reset driver are merged together as one single commit to avoid +git-bisect breakage. + +Fixes: 938ce3b16582 ("reset: spacemit: Add SpacemiT K3 reset driver") +Fixes: 216e0a5e98e5 ("dt-bindings: soc: spacemit: Add K3 reset support and IDs") +Signed-off-by: Yixun Lan +Reviewed-by: Philipp Zabel +Acked-by: Conor Dooley +Signed-off-by: Philipp Zabel +(cherry picked from commit a0e0c2f8c5f32b675f58e25a9338283cedb5ad2b) +Signed-off-by: Han Gao +--- + drivers/reset/spacemit/reset-spacemit-k3.c | 60 +++++++++++-------- + .../dt-bindings/reset/spacemit,k3-resets.h | 48 +++++++++++---- + 2 files changed, 72 insertions(+), 36 deletions(-) + +diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c +index e9e32e4c1ba5..9841f5e057b2 100644 +--- a/drivers/reset/spacemit/reset-spacemit-k3.c ++++ b/drivers/reset/spacemit/reset-spacemit-k3.c +@@ -112,16 +112,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = { + [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), +- [RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, +- BIT(1)|BIT(2)|BIT(3)), +- [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, +- BIT(5)|BIT(6)|BIT(7)), +- [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, +- BIT(9)|BIT(10)|BIT(11)), +- [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, +- BIT(13)|BIT(14)|BIT(15)), +- [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, +- BIT(17)|BIT(18)|BIT(19)), ++ [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)), ++ [RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)), ++ [RESET_APMU_USB3_A_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(6)), ++ [RESET_APMU_USB3_A_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(7)), ++ [RESET_APMU_USB3_B_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)), ++ [RESET_APMU_USB3_B_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)), ++ [RESET_APMU_USB3_B_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)), ++ [RESET_APMU_USB3_C_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(13)), ++ [RESET_APMU_USB3_C_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(14)), ++ [RESET_APMU_USB3_C_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(15)), ++ [RESET_APMU_USB3_D_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(17)), ++ [RESET_APMU_USB3_D_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(18)), ++ [RESET_APMU_USB3_D_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(19)), + [RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), +@@ -151,10 +156,12 @@ static const struct ccu_reset_data k3_apmu_resets[] = { + [RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), + [RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), + [RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), +- [RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL, +- BIT(1) | BIT(2) | BIT(3), 0), +- [RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, +- BIT(3) | BIT(2) | BIT(0)), ++ [RESET_APMU_UCIE_IP] = RESET_DATA(APMU_UCIE_CTRL, BIT(1), 0), ++ [RESET_APMU_UCIE_HOT] = RESET_DATA(APMU_UCIE_CTRL, BIT(2), 0), ++ [RESET_APMU_UCIE_MON] = RESET_DATA(APMU_UCIE_CTRL, BIT(3), 0), ++ [RESET_APMU_RCPU_AUDIO_SYS] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(0)), ++ [RESET_APMU_RCPU_MCU_CORE] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(2)), ++ [RESET_APMU_RCPU_AUDIO_APMU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(3)), + [RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)), + [RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)), + [RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)), +@@ -164,16 +171,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = { + [RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), + [RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), +- [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, +- BIT(5) | BIT(4) | BIT(3)), +- [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, +- BIT(5) | BIT(4) | BIT(3)), +- [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, +- BIT(5) | BIT(4) | BIT(3)), +- [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, +- BIT(5) | BIT(4) | BIT(3)), +- [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, +- BIT(5) | BIT(4) | BIT(3)), ++ [RESET_APMU_PCIE_A_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(3)), ++ [RESET_APMU_PCIE_A_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(4)), ++ [RESET_APMU_PCIE_A_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(5)), ++ [RESET_APMU_PCIE_B_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(3)), ++ [RESET_APMU_PCIE_B_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(4)), ++ [RESET_APMU_PCIE_B_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(5)), ++ [RESET_APMU_PCIE_C_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(3)), ++ [RESET_APMU_PCIE_C_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(4)), ++ [RESET_APMU_PCIE_C_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(5)), ++ [RESET_APMU_PCIE_D_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(3)), ++ [RESET_APMU_PCIE_D_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(4)), ++ [RESET_APMU_PCIE_D_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(5)), ++ [RESET_APMU_PCIE_E_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(3)), ++ [RESET_APMU_PCIE_E_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(4)), ++ [RESET_APMU_PCIE_E_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(5)), + [RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)), +diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h +index 79ac1c22b7b5..dc1ef009ba79 100644 +--- a/include/dt-bindings/reset/spacemit,k3-resets.h ++++ b/include/dt-bindings/reset/spacemit,k3-resets.h +@@ -97,11 +97,11 @@ + #define RESET_APMU_SDH0 13 + #define RESET_APMU_SDH1 14 + #define RESET_APMU_SDH2 15 +-#define RESET_APMU_USB2 16 +-#define RESET_APMU_USB3_PORTA 17 +-#define RESET_APMU_USB3_PORTB 18 +-#define RESET_APMU_USB3_PORTC 19 +-#define RESET_APMU_USB3_PORTD 20 ++#define RESET_APMU_USB2_AHB 16 ++#define RESET_APMU_USB2_VCC 17 ++#define RESET_APMU_USB2_PHY 18 ++#define RESET_APMU_USB3_A_AHB 19 ++#define RESET_APMU_USB3_A_VCC 20 + #define RESET_APMU_QSPI 21 + #define RESET_APMU_QSPI_BUS 22 + #define RESET_APMU_DMA 23 +@@ -132,8 +132,8 @@ + #define RESET_APMU_CPU7_SW 48 + #define RESET_APMU_C1_MPSUB_SW 49 + #define RESET_APMU_MPSUB_DBG 50 +-#define RESET_APMU_UCIE 51 +-#define RESET_APMU_RCPU 52 ++#define RESET_APMU_USB3_A_PHY 51 /* USB3 A */ ++#define RESET_APMU_USB3_B_AHB 52 + #define RESET_APMU_DSI4LN2_ESCCLK 53 + #define RESET_APMU_DSI4LN2_LCD_SW 54 + #define RESET_APMU_DSI4LN2_LCD_MCLK 55 +@@ -143,16 +143,40 @@ + #define RESET_APMU_UFS_ACLK 59 + #define RESET_APMU_EDP0 60 + #define RESET_APMU_EDP1 61 +-#define RESET_APMU_PCIE_PORTA 62 +-#define RESET_APMU_PCIE_PORTB 63 +-#define RESET_APMU_PCIE_PORTC 64 +-#define RESET_APMU_PCIE_PORTD 65 +-#define RESET_APMU_PCIE_PORTE 66 ++#define RESET_APMU_USB3_B_VCC 62 /* USB3 B */ ++#define RESET_APMU_USB3_B_PHY 63 ++#define RESET_APMU_USB3_C_AHB 64 ++#define RESET_APMU_USB3_C_VCC 65 ++#define RESET_APMU_USB3_C_PHY 66 + #define RESET_APMU_EMAC0 67 + #define RESET_APMU_EMAC1 68 + #define RESET_APMU_EMAC2 69 + #define RESET_APMU_ESPI_MCLK 70 + #define RESET_APMU_ESPI_SCLK 71 ++#define RESET_APMU_USB3_D_AHB 72 /* USB3 D */ ++#define RESET_APMU_USB3_D_VCC 73 ++#define RESET_APMU_USB3_D_PHY 74 ++#define RESET_APMU_UCIE_IP 75 ++#define RESET_APMU_UCIE_HOT 76 ++#define RESET_APMU_UCIE_MON 77 ++#define RESET_APMU_RCPU_AUDIO_SYS 78 ++#define RESET_APMU_RCPU_MCU_CORE 79 ++#define RESET_APMU_RCPU_AUDIO_APMU 80 ++#define RESET_APMU_PCIE_A_DBI 81 ++#define RESET_APMU_PCIE_A_SLAVE 82 ++#define RESET_APMU_PCIE_A_MASTER 83 ++#define RESET_APMU_PCIE_B_DBI 84 ++#define RESET_APMU_PCIE_B_SLAVE 85 ++#define RESET_APMU_PCIE_B_MASTER 86 ++#define RESET_APMU_PCIE_C_DBI 87 ++#define RESET_APMU_PCIE_C_SLAVE 88 ++#define RESET_APMU_PCIE_C_MASTER 89 ++#define RESET_APMU_PCIE_D_DBI 90 ++#define RESET_APMU_PCIE_D_SLAVE 91 ++#define RESET_APMU_PCIE_D_MASTER 92 ++#define RESET_APMU_PCIE_E_DBI 93 ++#define RESET_APMU_PCIE_E_SLAVE 94 ++#define RESET_APMU_PCIE_E_MASTER 95 + + /* DCIU resets*/ + #define RESET_DCIU_HDMA 0 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0175-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch b/SPECS/linux-lts/0175-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch deleted file mode 100644 index df952d8560..0000000000 --- a/SPECS/linux-lts/0175-UPSTREAM-riscv-patch-Avoid-early-phys_to_page.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 8118d162255f24fd2cd5dee126efaea4a5cba952 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Mon, 23 Mar 2026 17:43:47 -0600 -Subject: [PATCH 175/467] UPSTREAM: riscv: patch: Avoid early phys_to_page() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Similarly to commit 8d09e2d569f6 ("arm64: patching: avoid early -page_to_phys()"), avoid using phys_to_page() for the kernel address case -in patch_map(). - -Since this is called from apply_boot_alternatives() in setup_arch(), and -commit 4267739cabb8 ("arch, mm: consolidate initialization of SPARSE -memory model") has moved sparse_init() to after setup_arch(), -phys_to_page() is not available there yet, and it panics on boot with -SPARSEMEM on RV32, which does not use SPARSEMEM_VMEMMAP. - -Reported-by: Thomas Weißschuh -Closes: https://lore.kernel.org/r/20260223144108-dcace0b9-02e8-4b67-a7ce-f263bed36f26@linutronix.de/ -Fixes: 4267739cabb8 ("arch, mm: consolidate initialization of SPARSE memory model") -Suggested-by: Mike Rapoport -Signed-off-by: Vivian Wang -Acked-by: Mike Rapoport (Microsoft) -Tested-by: Thomas Weißschuh -Link: https://patch.msgid.link/20260310-riscv-sparsemem-alternatives-fix-v1-1-659d5dd257e2@iscas.ac.cn -[pjw@kernel.org: fix the subject line to align with the patch description] -Signed-off-by: Paul Walmsley -(cherry picked from commit 6b60a128c2f43180664a614830f3c529497e0394) -Signed-off-by: Han Gao ---- - arch/riscv/kernel/patch.c | 21 +++++++++++---------- - 1 file changed, 11 insertions(+), 10 deletions(-) - -diff --git a/arch/riscv/kernel/patch.c b/arch/riscv/kernel/patch.c -index db13c9ddf9e3..16b243376f36 100644 ---- a/arch/riscv/kernel/patch.c -+++ b/arch/riscv/kernel/patch.c -@@ -42,19 +42,20 @@ static inline bool is_kernel_exittext(uintptr_t addr) - static __always_inline void *patch_map(void *addr, const unsigned int fixmap) - { - uintptr_t uintaddr = (uintptr_t) addr; -- struct page *page; -+ phys_addr_t phys; - -- if (core_kernel_text(uintaddr) || is_kernel_exittext(uintaddr)) -- page = phys_to_page(__pa_symbol(addr)); -- else if (IS_ENABLED(CONFIG_STRICT_MODULE_RWX)) -- page = vmalloc_to_page(addr); -- else -- return addr; -+ if (core_kernel_text(uintaddr) || is_kernel_exittext(uintaddr)) { -+ phys = __pa_symbol(addr); -+ } else if (IS_ENABLED(CONFIG_STRICT_MODULE_RWX)) { -+ struct page *page = vmalloc_to_page(addr); - -- BUG_ON(!page); -+ BUG_ON(!page); -+ phys = page_to_phys(page) + offset_in_page(addr); -+ } else { -+ return addr; -+ } - -- return (void *)set_fixmap_offset(fixmap, page_to_phys(page) + -- offset_in_page(addr)); -+ return (void *)set_fixmap_offset(fixmap, phys); - } - - static void patch_unmap(int fixmap) --- -2.53.0 - diff --git a/SPECS/linux-lts/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch b/SPECS/linux-lts/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch new file mode 100644 index 0000000000..f22e81a3cb --- /dev/null +++ b/SPECS/linux-lts/0175-UPSTREAM-rust-clk-implement-Send-and-Sync.patch @@ -0,0 +1,46 @@ +From 36c2fd3cabf5ec62efb4f91282e7b4afd1034963 Mon Sep 17 00:00:00 2001 +From: Alice Ryhl +Date: Mon, 23 Feb 2026 10:08:25 +0000 +Subject: [RUYI PATCH] UPSTREAM: rust: clk: implement Send and Sync + +These traits are required for drivers to embed the Clk type in their own +data structures because driver data structures are usually required to +be Send. Since the Clk type is thread-safe, implement the relevant +traits. + +Reviewed-by: Daniel Almeida +Reviewed-by: Danilo Krummrich +Acked-by: Viresh Kumar +Reviewed-by: Boqun Feng +Reviewed-by: Gary Guo +Signed-off-by: Alice Ryhl +Acked-by: Brian Masney # Active contributor to clk +Link: https://patch.msgid.link/20260223-clk-send-sync-v5-1-181bf2f35652@google.com +Signed-off-by: Miguel Ojeda +(cherry picked from commit 0c0695a9d8c97f63d71dc890faa6999eef728f57) +Signed-off-by: Han Gao +--- + rust/kernel/clk.rs | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/rust/kernel/clk.rs b/rust/kernel/clk.rs +index 1e6c8c42fb3a..0a290202da69 100644 +--- a/rust/kernel/clk.rs ++++ b/rust/kernel/clk.rs +@@ -129,6 +129,13 @@ mod common_clk { + #[repr(transparent)] + pub struct Clk(*mut bindings::clk); + ++ // SAFETY: It is safe to call `clk_put` on another thread than where `clk_get` was called. ++ unsafe impl Send for Clk {} ++ ++ // SAFETY: It is safe to call any combination of the `&self` methods in parallel, as the ++ // methods are synchronized internally. ++ unsafe impl Sync for Clk {} ++ + impl Clk { + /// Gets [`Clk`] corresponding to a [`Device`] and a connection id. + /// +-- +2.53.0 + diff --git a/SPECS/linux-lts/0176-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch b/SPECS/linux-lts/0176-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch deleted file mode 100644 index 1bd8a9ebb3..0000000000 --- a/SPECS/linux-lts/0176-UPSTREAM-PCI-dwc-Fail-dw_pcie_host_init-if-dw_pcie_w.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 23cc45c1d179af7b48fdde28d5607b138fb0ca43 Mon Sep 17 00:00:00 2001 -From: Manivannan Sadhasivam -Date: Tue, 20 Jan 2026 23:17:44 +0530 -Subject: [PATCH 176/467] UPSTREAM: PCI: dwc: Fail dw_pcie_host_init() if - dw_pcie_wait_for_link() returns -ETIMEDOUT - -The dw_pcie_wait_for_link() API now distinguishes link failures more -precisely: - --ENODEV: Device not found on the bus. --EIO: Device found but inactive. --ETIMEDOUT: Link failed to come up. - -Out of these three errors, only -ETIMEDOUT represents a definitive link -failure since it signals that something is wrong with the link. For the -other two errors, there is a possibility that the link might come up later. -So fail dw_pcie_host_init() if -ETIMEDOUT is returned and skip the failure -otherwise. - -Signed-off-by: Manivannan Sadhasivam -Reviewed-by: Niklas Cassel -Link: https://patch.msgid.link/20260120-pci-dwc-suspend-rework-v4-5-2f32d5082549@oss.qualcomm.com -(cherry picked from commit 86cbb7a81068434fdc1d5afb96d91ab971fb279e) -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - -diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c -index 993858fd0529..dbd4b66934df 100644 ---- a/drivers/pci/controller/dwc/pcie-designware-host.c -+++ b/drivers/pci/controller/dwc/pcie-designware-host.c -@@ -664,8 +664,13 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) - goto err_remove_edma; - } - -- /* Ignore errors, the link may come up later */ -- dw_pcie_wait_for_link(pci); -+ /* -+ * Only fail on timeout error. Other errors indicate the device may -+ * become available later, so continue without failing. -+ */ -+ ret = dw_pcie_wait_for_link(pci); -+ if (ret == -ETIMEDOUT) -+ goto err_stop_link; - - ret = pci_host_probe(bridge); - if (ret) --- -2.53.0 - diff --git a/SPECS/linux-lts/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch b/SPECS/linux-lts/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch new file mode 100644 index 0000000000..de7554e891 --- /dev/null +++ b/SPECS/linux-lts/0176-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch @@ -0,0 +1,51 @@ +From 83865522aaf93ce13b4bf32daff035cc0ffb1875 Mon Sep 17 00:00:00 2001 +From: Alice Ryhl +Date: Mon, 23 Feb 2026 10:08:26 +0000 +Subject: [RUYI PATCH] UPSTREAM: tyr: remove impl Send/Sync for TyrData + +Now that clk implements Send and Sync, we no longer need to manually +implement these traits for TyrData. Thus remove the implementations. + +The comment also mentions the regulator. However, the regulator had the +traits added in commit 9a200cbdb543 ("rust: regulator: implement Send +and Sync for Regulator"), which is already in mainline. + +Reviewed-by: Danilo Krummrich +Reviewed-by: Boqun Feng +Reviewed-by: Gary Guo +Reviewed-by: Daniel Almeida +Signed-off-by: Alice Ryhl +Link: https://patch.msgid.link/20260223-clk-send-sync-v5-2-181bf2f35652@google.com +Signed-off-by: Miguel Ojeda +(cherry picked from commit ef90b103e8f767ffc31b1ddfef012358ea873d85) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/tyr/driver.rs | 12 ------------ + 1 file changed, 12 deletions(-) + +diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver.rs +index 0052ebe95719..0b741450724e 100644 +--- a/drivers/gpu/drm/tyr/driver.rs ++++ b/drivers/gpu/drm/tyr/driver.rs +@@ -53,18 +53,6 @@ pub(crate) struct TyrData { + pub(crate) gpu_info: GpuInfo, + } + +-// Both `Clk` and `Regulator` do not implement `Send` or `Sync`, but they +-// should. There are patches on the mailing list to address this, but they have +-// not landed yet. +-// +-// For now, add this workaround so that this patch compiles with the promise +-// that it will be removed in a future patch. +-// +-// SAFETY: This will be removed in a future patch. +-unsafe impl Send for TyrData {} +-// SAFETY: This will be removed in a future patch. +-unsafe impl Sync for TyrData {} +- + fn issue_soft_reset(dev: &Device, iomem: &Devres) -> Result { + regs::GPU_CMD.write(dev, iomem, regs::GPU_CMD_SOFT_RESET)?; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch b/SPECS/linux-lts/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch new file mode 100644 index 0000000000..96d1a40105 --- /dev/null +++ b/SPECS/linux-lts/0177-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch @@ -0,0 +1,72 @@ +From 196de3c6b4e75a74ef0157f0c59ca867711beb1f Mon Sep 17 00:00:00 2001 +From: Miguel Ojeda +Date: Wed, 21 Jan 2026 19:37:19 +0100 +Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: fix `CLIPPY=1` warning +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The Rust kernel code should be kept `CLIPPY=1`-clean [1]. + +Clippy reports: + + error: this pattern reimplements `Option::unwrap_or` + --> drivers/pwm/pwm_th1520.rs:64:5 + | + 64 | / (match ns.checked_mul(rate_hz) { + 65 | | Some(product) => product, + 66 | | None => u64::MAX, + 67 | | }) / NSEC_PER_SEC_U64 + | |______^ help: replace with: `ns.checked_mul(rate_hz).unwrap_or(u64::MAX)` + | + = help: for further information visit https://rust-lang.github.io/rust-clippy/rust-1.92.0/index.html#manual_unwrap_or + = note: `-D clippy::manual-unwrap-or` implied by `-D warnings` + = help: to override `-D warnings` add `#[allow(clippy::manual_unwrap_or)]` + +Applying the suggestion then triggers: + + error: manual saturating arithmetic + --> drivers/pwm/pwm_th1520.rs:64:5 + | + 64 | ns.checked_mul(rate_hz).unwrap_or(u64::MAX) / NSEC_PER_SEC_U64 + | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `saturating_mul`: `ns.saturating_mul(rate_hz)` + | + = help: for further information visit https://rust-lang.github.io/rust-clippy/rust-1.92.0/index.html#manual_saturating_arithmetic + = note: `-D clippy::manual-saturating-arithmetic` implied by `-D warnings` + = help: to override `-D warnings` add `#[allow(clippy::manual_saturating_arithmetic)]` + +Thus fix it by using saturating arithmetic, which simplifies the code +as well. + +Link: https://rust-for-linux.com/contributing#submit-checklist-addendum [1] +Fixes: e03724aac758 ("pwm: Add Rust driver for T-HEAD TH1520 SoC") +Signed-off-by: Miguel Ojeda +Reviewed-by: Danilo Krummrich +Reviewed-by: Michal Wilczynski +Link: https://patch.msgid.link/20260121183719.71659-1-ojeda@kernel.org +Signed-off-by: Uwe Kleine-König +(cherry picked from commit aa8f35172ab66c57d4355a8c4e28d05b44c938e3) +Signed-off-by: Han Gao +--- + drivers/pwm/pwm_th1520.rs | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs +index 955c359b07fb..571db5928356 100644 +--- a/drivers/pwm/pwm_th1520.rs ++++ b/drivers/pwm/pwm_th1520.rs +@@ -62,10 +62,7 @@ const fn th1520_pwm_fp(n: u32) -> usize { + fn ns_to_cycles(ns: u64, rate_hz: u64) -> u64 { + const NSEC_PER_SEC_U64: u64 = time::NSEC_PER_SEC as u64; + +- (match ns.checked_mul(rate_hz) { +- Some(product) => product, +- None => u64::MAX, +- }) / NSEC_PER_SEC_U64 ++ ns.saturating_mul(rate_hz) / NSEC_PER_SEC_U64 + } + + fn cycles_to_ns(cycles: u64, rate_hz: u64) -> u64 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0177-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch b/SPECS/linux-lts/0177-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch deleted file mode 100644 index 659010a91f..0000000000 --- a/SPECS/linux-lts/0177-UPSTREAM-reset-spacemit-k3-Decouple-composite-reset-.patch +++ /dev/null @@ -1,200 +0,0 @@ -From 760f735fd91860a199a5219ec9e84def5029f0c6 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 20 Mar 2026 11:06:17 +0000 -Subject: [PATCH 177/467] UPSTREAM: reset: spacemit: k3: Decouple composite - reset lines - -Instead of grouping several different reset lines into one composite -reset, decouple them to individual ones which make it more aligned -with underlying hardware. And for DWC USB driver, it will match well -with the number of the reset property in the DT bindings. - -The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC, -PHY. The PCIe controller also has three reset lines - DBI, Slave, Master. -Also three reset lines each for UCIE and RCPU block. - -As an agreement with maintainer, the reset IDs has been rearranged as -contiguous number but keep most part unchanged to avoid break patches -which already sent to mailing list. The changes of DT binding header file -and reset driver are merged together as one single commit to avoid -git-bisect breakage. - -Fixes: 938ce3b16582 ("reset: spacemit: Add SpacemiT K3 reset driver") -Fixes: 216e0a5e98e5 ("dt-bindings: soc: spacemit: Add K3 reset support and IDs") -Signed-off-by: Yixun Lan -Reviewed-by: Philipp Zabel -Acked-by: Conor Dooley -Signed-off-by: Philipp Zabel -(cherry picked from commit a0e0c2f8c5f32b675f58e25a9338283cedb5ad2b) -Signed-off-by: Han Gao ---- - drivers/reset/spacemit/reset-spacemit-k3.c | 60 +++++++++++-------- - .../dt-bindings/reset/spacemit,k3-resets.h | 48 +++++++++++---- - 2 files changed, 72 insertions(+), 36 deletions(-) - -diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c -index e9e32e4c1ba5..9841f5e057b2 100644 ---- a/drivers/reset/spacemit/reset-spacemit-k3.c -+++ b/drivers/reset/spacemit/reset-spacemit-k3.c -@@ -112,16 +112,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = { - [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), -- [RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -- BIT(1)|BIT(2)|BIT(3)), -- [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -- BIT(5)|BIT(6)|BIT(7)), -- [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -- BIT(9)|BIT(10)|BIT(11)), -- [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -- BIT(13)|BIT(14)|BIT(15)), -- [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, -- BIT(17)|BIT(18)|BIT(19)), -+ [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)), -+ [RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)), -+ [RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)), -+ [RESET_APMU_USB3_A_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(6)), -+ [RESET_APMU_USB3_A_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(7)), -+ [RESET_APMU_USB3_B_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)), -+ [RESET_APMU_USB3_B_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)), -+ [RESET_APMU_USB3_B_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)), -+ [RESET_APMU_USB3_C_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(13)), -+ [RESET_APMU_USB3_C_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(14)), -+ [RESET_APMU_USB3_C_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(15)), -+ [RESET_APMU_USB3_D_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(17)), -+ [RESET_APMU_USB3_D_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(18)), -+ [RESET_APMU_USB3_D_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(19)), - [RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), - [RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), -@@ -151,10 +156,12 @@ static const struct ccu_reset_data k3_apmu_resets[] = { - [RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), - [RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), - [RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), -- [RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL, -- BIT(1) | BIT(2) | BIT(3), 0), -- [RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, -- BIT(3) | BIT(2) | BIT(0)), -+ [RESET_APMU_UCIE_IP] = RESET_DATA(APMU_UCIE_CTRL, BIT(1), 0), -+ [RESET_APMU_UCIE_HOT] = RESET_DATA(APMU_UCIE_CTRL, BIT(2), 0), -+ [RESET_APMU_UCIE_MON] = RESET_DATA(APMU_UCIE_CTRL, BIT(3), 0), -+ [RESET_APMU_RCPU_AUDIO_SYS] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(0)), -+ [RESET_APMU_RCPU_MCU_CORE] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(2)), -+ [RESET_APMU_RCPU_AUDIO_APMU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(3)), - [RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)), - [RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)), - [RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)), -@@ -164,16 +171,21 @@ static const struct ccu_reset_data k3_apmu_resets[] = { - [RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), - [RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), - [RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), -- [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, -- BIT(5) | BIT(4) | BIT(3)), -- [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, -- BIT(5) | BIT(4) | BIT(3)), -- [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, -- BIT(5) | BIT(4) | BIT(3)), -- [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, -- BIT(5) | BIT(4) | BIT(3)), -- [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, -- BIT(5) | BIT(4) | BIT(3)), -+ [RESET_APMU_PCIE_A_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(3)), -+ [RESET_APMU_PCIE_A_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(4)), -+ [RESET_APMU_PCIE_A_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(5)), -+ [RESET_APMU_PCIE_B_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(3)), -+ [RESET_APMU_PCIE_B_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(4)), -+ [RESET_APMU_PCIE_B_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(5)), -+ [RESET_APMU_PCIE_C_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(3)), -+ [RESET_APMU_PCIE_C_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(4)), -+ [RESET_APMU_PCIE_C_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(5)), -+ [RESET_APMU_PCIE_D_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(3)), -+ [RESET_APMU_PCIE_D_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(4)), -+ [RESET_APMU_PCIE_D_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(5)), -+ [RESET_APMU_PCIE_E_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(3)), -+ [RESET_APMU_PCIE_E_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(4)), -+ [RESET_APMU_PCIE_E_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(5)), - [RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)), -diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h -index 79ac1c22b7b5..dc1ef009ba79 100644 ---- a/include/dt-bindings/reset/spacemit,k3-resets.h -+++ b/include/dt-bindings/reset/spacemit,k3-resets.h -@@ -97,11 +97,11 @@ - #define RESET_APMU_SDH0 13 - #define RESET_APMU_SDH1 14 - #define RESET_APMU_SDH2 15 --#define RESET_APMU_USB2 16 --#define RESET_APMU_USB3_PORTA 17 --#define RESET_APMU_USB3_PORTB 18 --#define RESET_APMU_USB3_PORTC 19 --#define RESET_APMU_USB3_PORTD 20 -+#define RESET_APMU_USB2_AHB 16 -+#define RESET_APMU_USB2_VCC 17 -+#define RESET_APMU_USB2_PHY 18 -+#define RESET_APMU_USB3_A_AHB 19 -+#define RESET_APMU_USB3_A_VCC 20 - #define RESET_APMU_QSPI 21 - #define RESET_APMU_QSPI_BUS 22 - #define RESET_APMU_DMA 23 -@@ -132,8 +132,8 @@ - #define RESET_APMU_CPU7_SW 48 - #define RESET_APMU_C1_MPSUB_SW 49 - #define RESET_APMU_MPSUB_DBG 50 --#define RESET_APMU_UCIE 51 --#define RESET_APMU_RCPU 52 -+#define RESET_APMU_USB3_A_PHY 51 /* USB3 A */ -+#define RESET_APMU_USB3_B_AHB 52 - #define RESET_APMU_DSI4LN2_ESCCLK 53 - #define RESET_APMU_DSI4LN2_LCD_SW 54 - #define RESET_APMU_DSI4LN2_LCD_MCLK 55 -@@ -143,16 +143,40 @@ - #define RESET_APMU_UFS_ACLK 59 - #define RESET_APMU_EDP0 60 - #define RESET_APMU_EDP1 61 --#define RESET_APMU_PCIE_PORTA 62 --#define RESET_APMU_PCIE_PORTB 63 --#define RESET_APMU_PCIE_PORTC 64 --#define RESET_APMU_PCIE_PORTD 65 --#define RESET_APMU_PCIE_PORTE 66 -+#define RESET_APMU_USB3_B_VCC 62 /* USB3 B */ -+#define RESET_APMU_USB3_B_PHY 63 -+#define RESET_APMU_USB3_C_AHB 64 -+#define RESET_APMU_USB3_C_VCC 65 -+#define RESET_APMU_USB3_C_PHY 66 - #define RESET_APMU_EMAC0 67 - #define RESET_APMU_EMAC1 68 - #define RESET_APMU_EMAC2 69 - #define RESET_APMU_ESPI_MCLK 70 - #define RESET_APMU_ESPI_SCLK 71 -+#define RESET_APMU_USB3_D_AHB 72 /* USB3 D */ -+#define RESET_APMU_USB3_D_VCC 73 -+#define RESET_APMU_USB3_D_PHY 74 -+#define RESET_APMU_UCIE_IP 75 -+#define RESET_APMU_UCIE_HOT 76 -+#define RESET_APMU_UCIE_MON 77 -+#define RESET_APMU_RCPU_AUDIO_SYS 78 -+#define RESET_APMU_RCPU_MCU_CORE 79 -+#define RESET_APMU_RCPU_AUDIO_APMU 80 -+#define RESET_APMU_PCIE_A_DBI 81 -+#define RESET_APMU_PCIE_A_SLAVE 82 -+#define RESET_APMU_PCIE_A_MASTER 83 -+#define RESET_APMU_PCIE_B_DBI 84 -+#define RESET_APMU_PCIE_B_SLAVE 85 -+#define RESET_APMU_PCIE_B_MASTER 86 -+#define RESET_APMU_PCIE_C_DBI 87 -+#define RESET_APMU_PCIE_C_SLAVE 88 -+#define RESET_APMU_PCIE_C_MASTER 89 -+#define RESET_APMU_PCIE_D_DBI 90 -+#define RESET_APMU_PCIE_D_SLAVE 91 -+#define RESET_APMU_PCIE_D_MASTER 92 -+#define RESET_APMU_PCIE_E_DBI 93 -+#define RESET_APMU_PCIE_E_SLAVE 94 -+#define RESET_APMU_PCIE_E_MASTER 95 - - /* DCIU resets*/ - #define RESET_DCIU_HDMA 0 --- -2.53.0 - diff --git a/SPECS/linux-lts/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch b/SPECS/linux-lts/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch new file mode 100644 index 0000000000..bfdd63b39b --- /dev/null +++ b/SPECS/linux-lts/0178-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch @@ -0,0 +1,55 @@ +From b521133241a4f965f50ccf4af99769c36904d779 Mon Sep 17 00:00:00 2001 +From: Alice Ryhl +Date: Mon, 23 Feb 2026 10:08:27 +0000 +Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: remove impl Send/Sync for + Th1520PwmDriverData +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Now that clk implements Send and Sync, we no longer need to manually +implement these traits for Th1520PwmDriverData. Thus remove the +implementations. + +Reviewed-by: Gary Guo +Reviewed-by: Daniel Almeida +Acked-by: Uwe Kleine-König +Reviewed-by: Michal Wilczynski +Signed-off-by: Alice Ryhl +Link: https://patch.msgid.link/20260223-clk-send-sync-v5-3-181bf2f35652@google.com +Signed-off-by: Miguel Ojeda +(cherry picked from commit 96f4e74cab632ea5c7e7fa996a28337283ecca11) +Signed-off-by: Han Gao +--- + drivers/pwm/pwm_th1520.rs | 15 --------------- + 1 file changed, 15 deletions(-) + +diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs +index 571db5928356..5559f4273b3d 100644 +--- a/drivers/pwm/pwm_th1520.rs ++++ b/drivers/pwm/pwm_th1520.rs +@@ -94,21 +94,6 @@ struct Th1520PwmDriverData { + clk: Clk, + } + +-// This `unsafe` implementation is a temporary necessity because the underlying `kernel::clk::Clk` +-// type does not yet expose `Send` and `Sync` implementations. This block should be removed +-// as soon as the clock abstraction provides these guarantees directly. +-// TODO: Remove those unsafe impl's when Clk will support them itself. +- +-// SAFETY: The `devres` framework requires the driver's private data to be `Send` and `Sync`. +-// We can guarantee this because the PWM core synchronizes all callbacks, preventing concurrent +-// access to the contained `iomem` and `clk` resources. +-unsafe impl Send for Th1520PwmDriverData {} +- +-// SAFETY: The same reasoning applies as for `Send`. The PWM core's synchronization +-// guarantees that it is safe for multiple threads to have shared access (`&self`) +-// to the driver data during callbacks. +-unsafe impl Sync for Th1520PwmDriverData {} +- + impl pwm::PwmOps for Th1520PwmDriverData { + type WfHw = Th1520WfHw; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0178-UPSTREAM-rust-clk-implement-Send-and-Sync.patch b/SPECS/linux-lts/0178-UPSTREAM-rust-clk-implement-Send-and-Sync.patch deleted file mode 100644 index 1806623564..0000000000 --- a/SPECS/linux-lts/0178-UPSTREAM-rust-clk-implement-Send-and-Sync.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 1642a007a0a6fae07e706694a837771d62f6a5fd Mon Sep 17 00:00:00 2001 -From: Alice Ryhl -Date: Mon, 23 Feb 2026 10:08:25 +0000 -Subject: [PATCH 178/467] UPSTREAM: rust: clk: implement Send and Sync - -These traits are required for drivers to embed the Clk type in their own -data structures because driver data structures are usually required to -be Send. Since the Clk type is thread-safe, implement the relevant -traits. - -Reviewed-by: Daniel Almeida -Reviewed-by: Danilo Krummrich -Acked-by: Viresh Kumar -Reviewed-by: Boqun Feng -Reviewed-by: Gary Guo -Signed-off-by: Alice Ryhl -Acked-by: Brian Masney # Active contributor to clk -Link: https://patch.msgid.link/20260223-clk-send-sync-v5-1-181bf2f35652@google.com -Signed-off-by: Miguel Ojeda -(cherry picked from commit 0c0695a9d8c97f63d71dc890faa6999eef728f57) -Signed-off-by: Han Gao ---- - rust/kernel/clk.rs | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/rust/kernel/clk.rs b/rust/kernel/clk.rs -index 1e6c8c42fb3a..0a290202da69 100644 ---- a/rust/kernel/clk.rs -+++ b/rust/kernel/clk.rs -@@ -129,6 +129,13 @@ mod common_clk { - #[repr(transparent)] - pub struct Clk(*mut bindings::clk); - -+ // SAFETY: It is safe to call `clk_put` on another thread than where `clk_get` was called. -+ unsafe impl Send for Clk {} -+ -+ // SAFETY: It is safe to call any combination of the `&self` methods in parallel, as the -+ // methods are synchronized internally. -+ unsafe impl Sync for Clk {} -+ - impl Clk { - /// Gets [`Clk`] corresponding to a [`Device`] and a connection id. - /// --- -2.53.0 - diff --git a/SPECS/linux-lts/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch b/SPECS/linux-lts/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch new file mode 100644 index 0000000000..3373671d06 --- /dev/null +++ b/SPECS/linux-lts/0179-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch @@ -0,0 +1,49 @@ +From 32264ffa5210859b00dbce09fa640779874438f7 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 5 Mar 2026 15:00:29 +0800 +Subject: [RUYI PATCH] UPSTREAM: net: spacemit: Remove unused buff_addr fields + +These were never used. Just remove them. + +No functional change intended. + +Signed-off-by: Vivian Wang +Link: https://patch.msgid.link/20260305-k1-ethernet-cleanup-buff_addr-v1-1-e978ef119231@iscas.ac.cn +Signed-off-by: Jakub Kicinski +(cherry picked from commit 70eba59f92076d84264762d63d30532685943017) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/spacemit/k1_emac.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c +index 52c0c00a471f..359b409f8203 100644 +--- a/drivers/net/ethernet/spacemit/k1_emac.c ++++ b/drivers/net/ethernet/spacemit/k1_emac.c +@@ -59,7 +59,6 @@ + + struct desc_buf { + u64 dma_addr; +- void *buff_addr; + u16 dma_len; + u8 map_as_page; + }; +@@ -72,7 +71,6 @@ struct emac_tx_desc_buffer { + struct emac_rx_desc_buffer { + struct sk_buff *skb; + u64 dma_addr; +- void *buff_addr; + u16 dma_len; + u8 map_as_page; + }; +@@ -355,7 +353,6 @@ static void emac_free_tx_buf(struct emac_priv *priv, int i) + + buf->dma_addr = 0; + buf->map_as_page = false; +- buf->buff_addr = NULL; + } + + if (tx_buf->skb) { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0179-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch b/SPECS/linux-lts/0179-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch deleted file mode 100644 index 8176cbc5dd..0000000000 --- a/SPECS/linux-lts/0179-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 98d1f3807843d1600d9c0fed44a0c1cfeee7e373 Mon Sep 17 00:00:00 2001 -From: Alice Ryhl -Date: Mon, 23 Feb 2026 10:08:26 +0000 -Subject: [PATCH 179/467] UPSTREAM: tyr: remove impl Send/Sync for TyrData - -Now that clk implements Send and Sync, we no longer need to manually -implement these traits for TyrData. Thus remove the implementations. - -The comment also mentions the regulator. However, the regulator had the -traits added in commit 9a200cbdb543 ("rust: regulator: implement Send -and Sync for Regulator"), which is already in mainline. - -Reviewed-by: Danilo Krummrich -Reviewed-by: Boqun Feng -Reviewed-by: Gary Guo -Reviewed-by: Daniel Almeida -Signed-off-by: Alice Ryhl -Link: https://patch.msgid.link/20260223-clk-send-sync-v5-2-181bf2f35652@google.com -Signed-off-by: Miguel Ojeda -(cherry picked from commit ef90b103e8f767ffc31b1ddfef012358ea873d85) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/tyr/driver.rs | 12 ------------ - 1 file changed, 12 deletions(-) - -diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver.rs -index 0052ebe95719..0b741450724e 100644 ---- a/drivers/gpu/drm/tyr/driver.rs -+++ b/drivers/gpu/drm/tyr/driver.rs -@@ -53,18 +53,6 @@ pub(crate) struct TyrData { - pub(crate) gpu_info: GpuInfo, - } - --// Both `Clk` and `Regulator` do not implement `Send` or `Sync`, but they --// should. There are patches on the mailing list to address this, but they have --// not landed yet. --// --// For now, add this workaround so that this patch compiles with the promise --// that it will be removed in a future patch. --// --// SAFETY: This will be removed in a future patch. --unsafe impl Send for TyrData {} --// SAFETY: This will be removed in a future patch. --unsafe impl Sync for TyrData {} -- - fn issue_soft_reset(dev: &Device, iomem: &Devres) -> Result { - regs::GPU_CMD.write(dev, iomem, regs::GPU_CMD_SOFT_RESET)?; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch b/SPECS/linux-lts/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch new file mode 100644 index 0000000000..9f38d216be --- /dev/null +++ b/SPECS/linux-lts/0180-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch @@ -0,0 +1,154 @@ +From c446f352ebab05c2cef0a9835bd9224e19c24ccb Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Mon, 16 Mar 2026 09:00:37 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: net: Add support for Spacemit K3 + dwmac + +The GMAC IP on Spacemit K3 is almost a standard Synopsys DesignWare +MAC (version 5.40a) with some extra clock. + +Add necessary compatible string for this device. + +Signed-off-by: Inochi Amaoto +Reviewed-by: Rob Herring (Arm) +Link: https://patch.msgid.link/20260316010041.164360-2-inochiama@gmail.com +Signed-off-by: Jakub Kicinski +(cherry picked from commit bb30400a566c7a6a9355873344ec63e2c6310e2c) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/net/snps,dwmac.yaml | 2 + + .../bindings/net/spacemit,k3-dwmac.yaml | 102 ++++++++++++++++++ + 2 files changed, 104 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml + +diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +index 658c004e6a5c..eb36cb36a57a 100644 +--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml ++++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +@@ -104,6 +104,7 @@ properties: + - snps,dwmac-5.10a + - snps,dwmac-5.20 + - snps,dwmac-5.30a ++ - snps,dwmac-5.40a + - snps,dwxgmac + - snps,dwxgmac-2.10 + - sophgo,sg2042-dwmac +@@ -649,6 +650,7 @@ allOf: + - snps,dwmac-5.10a + - snps,dwmac-5.20 + - snps,dwmac-5.30a ++ - snps,dwmac-5.40a + - snps,dwxgmac + - snps,dwxgmac-2.10 + - st,spear600-gmac +diff --git a/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml b/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml +new file mode 100644 +index 000000000000..678eccf044f9 +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml +@@ -0,0 +1,102 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/spacemit,k3-dwmac.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Spacemit K3 DWMAC glue layer ++ ++maintainers: ++ - Inochi Amaoto ++ ++select: ++ properties: ++ compatible: ++ contains: ++ const: spacemit,k3-dwmac ++ required: ++ - compatible ++ ++properties: ++ compatible: ++ items: ++ - const: spacemit,k3-dwmac ++ - const: snps,dwmac-5.40a ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: GMAC application clock ++ - description: PTP clock ++ - description: TX clock ++ ++ clock-names: ++ items: ++ - const: stmmaceth ++ - const: ptp_ref ++ - const: tx ++ ++ interrupts: ++ minItems: 1 ++ items: ++ - description: MAC interrupt ++ - description: MAC wake interrupt ++ ++ interrupt-names: ++ minItems: 1 ++ items: ++ - const: macirq ++ - const: eth_wake_irq ++ ++ resets: ++ maxItems: 1 ++ ++ reset-names: ++ const: stmmaceth ++ ++ spacemit,apmu: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle to the syscon node which control the glue register ++ - description: offset of the control register ++ - description: offset of the dline register ++ description: ++ A phandle to syscon with offset to control registers for this MAC ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - interrupts ++ - interrupt-names ++ - resets ++ - reset-names ++ - spacemit,apmu ++ ++allOf: ++ - $ref: snps,dwmac.yaml# ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ ++ ethernet@cac80000 { ++ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; ++ reg = <0xcac80000 0x2000>; ++ clocks = <&syscon_apmu 66>, <&syscon_apmu 68>, ++ <&syscon_apmu 69>; ++ clock-names = "stmmaceth", "ptp_ref", "tx"; ++ interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, <276 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&phy0>; ++ resets = <&syscon_apmu 67>; ++ reset-names = "stmmaceth"; ++ spacemit,apmu = <&syscon_apmu 0x384 0x38c>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0180-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch b/SPECS/linux-lts/0180-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch deleted file mode 100644 index bfcbe3e3d7..0000000000 --- a/SPECS/linux-lts/0180-UPSTREAM-pwm-th1520-fix-CLIPPY-1-warning.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 9ca8e005adc28dc70cd2159ee5e1b4357360f8e3 Mon Sep 17 00:00:00 2001 -From: Miguel Ojeda -Date: Wed, 21 Jan 2026 19:37:19 +0100 -Subject: [PATCH 180/467] UPSTREAM: pwm: th1520: fix `CLIPPY=1` warning -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The Rust kernel code should be kept `CLIPPY=1`-clean [1]. - -Clippy reports: - - error: this pattern reimplements `Option::unwrap_or` - --> drivers/pwm/pwm_th1520.rs:64:5 - | - 64 | / (match ns.checked_mul(rate_hz) { - 65 | | Some(product) => product, - 66 | | None => u64::MAX, - 67 | | }) / NSEC_PER_SEC_U64 - | |______^ help: replace with: `ns.checked_mul(rate_hz).unwrap_or(u64::MAX)` - | - = help: for further information visit https://rust-lang.github.io/rust-clippy/rust-1.92.0/index.html#manual_unwrap_or - = note: `-D clippy::manual-unwrap-or` implied by `-D warnings` - = help: to override `-D warnings` add `#[allow(clippy::manual_unwrap_or)]` - -Applying the suggestion then triggers: - - error: manual saturating arithmetic - --> drivers/pwm/pwm_th1520.rs:64:5 - | - 64 | ns.checked_mul(rate_hz).unwrap_or(u64::MAX) / NSEC_PER_SEC_U64 - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `saturating_mul`: `ns.saturating_mul(rate_hz)` - | - = help: for further information visit https://rust-lang.github.io/rust-clippy/rust-1.92.0/index.html#manual_saturating_arithmetic - = note: `-D clippy::manual-saturating-arithmetic` implied by `-D warnings` - = help: to override `-D warnings` add `#[allow(clippy::manual_saturating_arithmetic)]` - -Thus fix it by using saturating arithmetic, which simplifies the code -as well. - -Link: https://rust-for-linux.com/contributing#submit-checklist-addendum [1] -Fixes: e03724aac758 ("pwm: Add Rust driver for T-HEAD TH1520 SoC") -Signed-off-by: Miguel Ojeda -Reviewed-by: Danilo Krummrich -Reviewed-by: Michal Wilczynski -Link: https://patch.msgid.link/20260121183719.71659-1-ojeda@kernel.org -Signed-off-by: Uwe Kleine-König -(cherry picked from commit aa8f35172ab66c57d4355a8c4e28d05b44c938e3) -Signed-off-by: Han Gao ---- - drivers/pwm/pwm_th1520.rs | 5 +---- - 1 file changed, 1 insertion(+), 4 deletions(-) - -diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs -index 955c359b07fb..571db5928356 100644 ---- a/drivers/pwm/pwm_th1520.rs -+++ b/drivers/pwm/pwm_th1520.rs -@@ -62,10 +62,7 @@ const fn th1520_pwm_fp(n: u32) -> usize { - fn ns_to_cycles(ns: u64, rate_hz: u64) -> u64 { - const NSEC_PER_SEC_U64: u64 = time::NSEC_PER_SEC as u64; - -- (match ns.checked_mul(rate_hz) { -- Some(product) => product, -- None => u64::MAX, -- }) / NSEC_PER_SEC_U64 -+ ns.saturating_mul(rate_hz) / NSEC_PER_SEC_U64 - } - - fn cycles_to_ns(cycles: u64, rate_hz: u64) -> u64 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch b/SPECS/linux-lts/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch new file mode 100644 index 0000000000..e0e422ae4b --- /dev/null +++ b/SPECS/linux-lts/0181-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch @@ -0,0 +1,34 @@ +From 415d3b3b2a8fe07f5d9c84225c47c6f3be8fd827 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Mon, 16 Mar 2026 09:00:38 +0800 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: platform: Add snps,dwmac-5.40a IP + compatible string + +Add compatible string for 5.40a version that can avoid to define some +platform data in the glue layer. + +Signed-off-by: Inochi Amaoto +Reviewed-by: Russell King (Oracle) +Link: https://patch.msgid.link/20260316010041.164360-3-inochiama@gmail.com +Signed-off-by: Jakub Kicinski +(cherry picked from commit d35aa97ea908a17809358a981bef6cd752f2e8a0) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +index 0cb51935c405..3416ca24f623 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -414,6 +414,7 @@ static const char * const stmmac_gmac4_compats[] = { + "snps,dwmac-5.10a", + "snps,dwmac-5.20", + "snps,dwmac-5.30a", ++ "snps,dwmac-5.40a", + NULL + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0181-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch b/SPECS/linux-lts/0181-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch deleted file mode 100644 index 90f301730b..0000000000 --- a/SPECS/linux-lts/0181-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 17144d80f2540d040b45eb32a29a9afc0d23845e Mon Sep 17 00:00:00 2001 -From: Alice Ryhl -Date: Mon, 23 Feb 2026 10:08:27 +0000 -Subject: [PATCH 181/467] UPSTREAM: pwm: th1520: remove impl Send/Sync for - Th1520PwmDriverData -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Now that clk implements Send and Sync, we no longer need to manually -implement these traits for Th1520PwmDriverData. Thus remove the -implementations. - -Reviewed-by: Gary Guo -Reviewed-by: Daniel Almeida -Acked-by: Uwe Kleine-König -Reviewed-by: Michal Wilczynski -Signed-off-by: Alice Ryhl -Link: https://patch.msgid.link/20260223-clk-send-sync-v5-3-181bf2f35652@google.com -Signed-off-by: Miguel Ojeda -(cherry picked from commit 96f4e74cab632ea5c7e7fa996a28337283ecca11) -Signed-off-by: Han Gao ---- - drivers/pwm/pwm_th1520.rs | 15 --------------- - 1 file changed, 15 deletions(-) - -diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs -index 571db5928356..5559f4273b3d 100644 ---- a/drivers/pwm/pwm_th1520.rs -+++ b/drivers/pwm/pwm_th1520.rs -@@ -94,21 +94,6 @@ struct Th1520PwmDriverData { - clk: Clk, - } - --// This `unsafe` implementation is a temporary necessity because the underlying `kernel::clk::Clk` --// type does not yet expose `Send` and `Sync` implementations. This block should be removed --// as soon as the clock abstraction provides these guarantees directly. --// TODO: Remove those unsafe impl's when Clk will support them itself. -- --// SAFETY: The `devres` framework requires the driver's private data to be `Send` and `Sync`. --// We can guarantee this because the PWM core synchronizes all callbacks, preventing concurrent --// access to the contained `iomem` and `clk` resources. --unsafe impl Send for Th1520PwmDriverData {} -- --// SAFETY: The same reasoning applies as for `Send`. The PWM core's synchronization --// guarantees that it is safe for multiple threads to have shared access (`&self`) --// to the driver data during callbacks. --unsafe impl Sync for Th1520PwmDriverData {} -- - impl pwm::PwmOps for Th1520PwmDriverData { - type WfHw = Th1520WfHw; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0182-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch b/SPECS/linux-lts/0182-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch deleted file mode 100644 index 5b71138373..0000000000 --- a/SPECS/linux-lts/0182-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 4a69779f56c915bdce7bc724b34f0efd8a77f9fb Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 5 Mar 2026 15:00:29 +0800 -Subject: [PATCH 182/467] UPSTREAM: net: spacemit: Remove unused buff_addr - fields - -These were never used. Just remove them. - -No functional change intended. - -Signed-off-by: Vivian Wang -Link: https://patch.msgid.link/20260305-k1-ethernet-cleanup-buff_addr-v1-1-e978ef119231@iscas.ac.cn -Signed-off-by: Jakub Kicinski -(cherry picked from commit 70eba59f92076d84264762d63d30532685943017) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/spacemit/k1_emac.c | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c -index 52c0c00a471f..359b409f8203 100644 ---- a/drivers/net/ethernet/spacemit/k1_emac.c -+++ b/drivers/net/ethernet/spacemit/k1_emac.c -@@ -59,7 +59,6 @@ - - struct desc_buf { - u64 dma_addr; -- void *buff_addr; - u16 dma_len; - u8 map_as_page; - }; -@@ -72,7 +71,6 @@ struct emac_tx_desc_buffer { - struct emac_rx_desc_buffer { - struct sk_buff *skb; - u64 dma_addr; -- void *buff_addr; - u16 dma_len; - u8 map_as_page; - }; -@@ -355,7 +353,6 @@ static void emac_free_tx_buf(struct emac_priv *priv, int i) - - buf->dma_addr = 0; - buf->map_as_page = false; -- buf->buff_addr = NULL; - } - - if (tx_buf->skb) { --- -2.53.0 - diff --git a/SPECS/linux-lts/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch b/SPECS/linux-lts/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch new file mode 100644 index 0000000000..e3ca4ecc6c --- /dev/null +++ b/SPECS/linux-lts/0182-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch @@ -0,0 +1,300 @@ +From 945ce43958e6a4b22a3bf632d66514c6e279d2e9 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Mon, 16 Mar 2026 09:00:39 +0800 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: Add glue layer for Spacemit K3 + SoC + +The ethernet controller on Spacemit K3 SoC is Synopsys DesignWare +MAC (version 5.40a), with the following special points: +1. The rate of the tx clock line is auto changed when the mac speed + rate is changed, and no need for changing the input tx clock. +2. This controller require a extra syscon device to configure the + interface type, enable wake up interrupt and delay configuration + if needed. + +Add Spacemit dwmac driver support on the Spacemit K3 SoC. + +Signed-off-by: Inochi Amaoto +Reviewed-by: Russell King (Oracle) +Link: https://patch.msgid.link/20260316010041.164360-4-inochiama@gmail.com +Signed-off-by: Jakub Kicinski +(cherry picked from commit 30f0ba420ed3fb9a16d55523ae3c1b43a6f00e22) +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 + + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + + .../ethernet/stmicro/stmmac/dwmac-spacemit.c | 227 ++++++++++++++++++ + 3 files changed, 240 insertions(+) + create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c + +diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig +index 9507131875b2..3209353b7659 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig ++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig +@@ -206,6 +206,18 @@ config DWMAC_SOPHGO + for the stmmac device driver. This driver is used for the + ethernet controllers on various Sophgo SoCs. + ++config DWMAC_SPACEMIT ++ tristate "Spacemit dwmac support" ++ depends on OF && (ARCH_SPACEMIT || COMPILE_TEST) ++ select MFD_SYSCON ++ default m if ARCH_SPACEMIT ++ help ++ Support for ethernet controllers on Spacemit RISC-V SoCs ++ ++ This selects the Spacemit platform specific glue layer support ++ for the stmmac device driver. This driver is used for the ++ Spacemit K3 ethernet controllers. ++ + config DWMAC_STARFIVE + tristate "StarFive dwmac support" + depends on OF && (ARCH_STARFIVE || COMPILE_TEST) +diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile +index 51e068e26ce4..2a24934f5c43 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Makefile ++++ b/drivers/net/ethernet/stmicro/stmmac/Makefile +@@ -26,6 +26,7 @@ obj-$(CONFIG_DWMAC_RZN1) += dwmac-rzn1.o + obj-$(CONFIG_DWMAC_S32) += dwmac-s32.o + obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o + obj-$(CONFIG_DWMAC_SOPHGO) += dwmac-sophgo.o ++obj-$(CONFIG_DWMAC_SPACEMIT) += dwmac-spacemit.o + obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o + obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o + obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c +new file mode 100644 +index 000000000000..223754cc5c79 +--- /dev/null ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c +@@ -0,0 +1,227 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Spacemit DWMAC platform driver ++ * ++ * Copyright (C) 2026 Inochi Amaoto ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "stmmac_platform.h" ++ ++/* ctrl register bits */ ++#define CTRL_PHY_INTF_RGMII BIT(3) ++#define CTRL_PHY_INTF_MII BIT(4) ++#define CTRL_WAKE_IRQ_EN BIT(9) ++#define CTRL_PHY_IRQ_EN BIT(12) ++ ++/* dline register bits */ ++#define RGMII_RX_DLINE_EN BIT(0) ++#define RGMII_RX_DLINE_STEP GENMASK(5, 4) ++#define RGMII_RX_DLINE_CODE GENMASK(15, 8) ++#define RGMII_TX_DLINE_EN BIT(16) ++#define RGMII_TX_DLINE_STEP GENMASK(21, 20) ++#define RGMII_TX_DLINE_CODE GENMASK(31, 24) ++ ++#define MAX_DLINE_DELAY_CODE 0xff ++#define MAX_WORKED_DELAY 2800 ++/* Note: the delay step value is at 0.1ps */ ++#define K3_DELAY_STEP 367 ++ ++struct spacmit_dwmac { ++ struct regmap *apmu; ++ unsigned int ctrl_offset; ++ unsigned int dline_offset; ++}; ++ ++static int spacemit_dwmac_set_delay(struct spacmit_dwmac *dwmac, ++ unsigned int tx_code, unsigned int rx_code) ++{ ++ unsigned int mask, val; ++ ++ mask = RGMII_TX_DLINE_STEP | RGMII_TX_DLINE_CODE | RGMII_TX_DLINE_EN | ++ RGMII_RX_DLINE_STEP | RGMII_RX_DLINE_CODE | RGMII_RX_DLINE_EN; ++ ++ /* ++ * Since the delay step provided by config 0 is small enough, and ++ * it can cover the range of the valid delay, so there is no needed ++ * to use other step config. ++ */ ++ val = FIELD_PREP(RGMII_TX_DLINE_STEP, 0) | ++ FIELD_PREP(RGMII_TX_DLINE_CODE, tx_code) | RGMII_TX_DLINE_EN | ++ FIELD_PREP(RGMII_RX_DLINE_STEP, 0) | ++ FIELD_PREP(RGMII_RX_DLINE_CODE, rx_code) | RGMII_RX_DLINE_EN; ++ ++ return regmap_update_bits(dwmac->apmu, dwmac->dline_offset, ++ mask, val); ++} ++ ++static int spacemit_dwmac_detected_delay_value(unsigned int delay) ++{ ++ if (delay == 0) ++ return 0; ++ ++ if (delay > MAX_WORKED_DELAY) ++ return -EINVAL; ++ ++ /* ++ * Note K3 require a specific factor for calculate ++ * the delay, in this scenario it is 0.9. So the ++ * formula is code * step / 10 * 0.9 ++ */ ++ return DIV_ROUND_CLOSEST(delay * 10 * 10, K3_DELAY_STEP * 9); ++} ++ ++static int spacemit_dwmac_fix_delay(struct spacmit_dwmac *dwmac, ++ unsigned int tx_delay, ++ unsigned int rx_delay) ++{ ++ int rx_code; ++ int tx_code; ++ ++ rx_code = spacemit_dwmac_detected_delay_value(rx_delay); ++ if (rx_code < 0) ++ return rx_code; ++ ++ tx_code = spacemit_dwmac_detected_delay_value(tx_delay); ++ if (tx_code < 0) ++ return tx_code; ++ ++ return spacemit_dwmac_set_delay(dwmac, tx_code, rx_code); ++} ++ ++static int spacemit_dwmac_update_irq_config(struct spacmit_dwmac *dwmac, ++ struct stmmac_resources *stmmac_res) ++{ ++ unsigned int val = stmmac_res->wol_irq >= 0 ? CTRL_WAKE_IRQ_EN : 0; ++ unsigned int mask = CTRL_WAKE_IRQ_EN; ++ ++ return regmap_update_bits(dwmac->apmu, dwmac->ctrl_offset, ++ mask, val); ++} ++ ++static void spacemit_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, ++ unsigned long *interfaces) ++{ ++ __set_bit(PHY_INTERFACE_MODE_MII, interfaces); ++ __set_bit(PHY_INTERFACE_MODE_RMII, interfaces); ++ phy_interface_set_rgmii(interfaces); ++} ++ ++static int spacemit_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) ++{ ++ unsigned int mask = CTRL_PHY_INTF_MII | CTRL_PHY_INTF_RGMII; ++ struct spacmit_dwmac *dwmac = bsp_priv; ++ unsigned int val = 0; ++ ++ switch (phy_intf_sel) { ++ case PHY_INTF_SEL_GMII_MII: ++ val = CTRL_PHY_INTF_MII; ++ break; ++ ++ case PHY_INTF_SEL_RMII: ++ break; ++ ++ case PHY_INTF_SEL_RGMII: ++ val = CTRL_PHY_INTF_RGMII; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ return regmap_update_bits(dwmac->apmu, dwmac->ctrl_offset, ++ mask, val); ++} ++ ++static int spacemit_dwmac_probe(struct platform_device *pdev) ++{ ++ struct plat_stmmacenet_data *plat_dat; ++ struct stmmac_resources stmmac_res; ++ struct device *dev = &pdev->dev; ++ struct spacmit_dwmac *dwmac; ++ unsigned int offset[2]; ++ struct regmap *apmu; ++ struct clk *clk_tx; ++ u32 rx_delay = 0; ++ u32 tx_delay = 0; ++ int ret; ++ ++ ret = stmmac_get_platform_resources(pdev, &stmmac_res); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "failed to get platform resources\n"); ++ ++ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); ++ if (!dwmac) ++ return -ENOMEM; ++ ++ plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); ++ if (IS_ERR(plat_dat)) ++ return dev_err_probe(dev, PTR_ERR(plat_dat), ++ "failed to parse DT parameters\n"); ++ ++ clk_tx = devm_clk_get_enabled(&pdev->dev, "tx"); ++ if (IS_ERR(clk_tx)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(clk_tx), ++ "failed to get tx clock\n"); ++ ++ apmu = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, ++ "spacemit,apmu", 2, ++ offset); ++ if (IS_ERR(apmu)) ++ return dev_err_probe(dev, PTR_ERR(apmu), ++ "Failed to get apmu regmap\n"); ++ ++ dwmac->apmu = apmu; ++ dwmac->ctrl_offset = offset[0]; ++ dwmac->dline_offset = offset[1]; ++ ++ ret = spacemit_dwmac_update_irq_config(dwmac, &stmmac_res); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to configure irq config\n"); ++ ++ of_property_read_u32(pdev->dev.of_node, "tx-internal-delay-ps", ++ &tx_delay); ++ of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps", ++ &rx_delay); ++ ++ plat_dat->get_interfaces = spacemit_get_interfaces; ++ plat_dat->set_phy_intf_sel = spacemit_set_phy_intf_sel; ++ plat_dat->bsp_priv = dwmac; ++ ++ ret = spacemit_dwmac_fix_delay(dwmac, tx_delay, rx_delay); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to configure delay\n"); ++ ++ return stmmac_dvr_probe(dev, plat_dat, &stmmac_res); ++} ++ ++static const struct of_device_id spacemit_dwmac_match[] = { ++ { .compatible = "spacemit,k3-dwmac" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, spacemit_dwmac_match); ++ ++static struct platform_driver spacemit_dwmac_driver = { ++ .probe = spacemit_dwmac_probe, ++ .remove = stmmac_pltfr_remove, ++ .driver = { ++ .name = "spacemit-dwmac", ++ .pm = &stmmac_pltfr_pm_ops, ++ .of_match_table = spacemit_dwmac_match, ++ }, ++}; ++module_platform_driver(spacemit_dwmac_driver); ++ ++MODULE_AUTHOR("Inochi Amaoto "); ++MODULE_DESCRIPTION("Spacemit DWMAC platform driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch b/SPECS/linux-lts/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch new file mode 100644 index 0000000000..be1102a0eb --- /dev/null +++ b/SPECS/linux-lts/0183-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch @@ -0,0 +1,53 @@ +From eaea87333b8ad51ffef8e8e2939c8aedc0c6f5f5 Mon Sep 17 00:00:00 2001 +From: Matt Coster +Date: Fri, 6 Feb 2026 16:02:12 +0000 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Improve handling of unknown + FWCCB commands + +A couple small changes: + - Validate the magic value at the head of FWCCB commands, and + - Mask off the magic value before logging unknown command types to make + them easier to interpret on sight. + +Reviewed-by: Frank Binns +Link: https://patch.msgid.link/20260206-improve-bad-fwccb-cmd-v1-1-831a852ca127@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit c7384288d9266e52cd35aadb1749872caf3c0257) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_ccb.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c +index 2bbdc05a3b97..1ccd3e3dab2b 100644 +--- a/drivers/gpu/drm/imagination/pvr_ccb.c ++++ b/drivers/gpu/drm/imagination/pvr_ccb.c +@@ -135,6 +135,14 @@ pvr_ccb_slot_available_locked(struct pvr_ccb *pvr_ccb, u32 *write_offset) + static void + process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *cmd) + { ++ struct drm_device *drm_dev = from_pvr_device(pvr_dev); ++ ++ if ((cmd->cmd_type & ROGUE_CMD_MAGIC_DWORD_MASK) != ROGUE_CMD_MAGIC_DWORD_SHIFTED) { ++ drm_warn_once(drm_dev, "Received FWCCB command with bad magic value; ignoring (type=0x%08x)\n", ++ cmd->cmd_type); ++ return; ++ } ++ + switch (cmd->cmd_type) { + case ROGUE_FWIF_FWCCB_CMD_REQUEST_GPU_RESTART: + pvr_power_reset(pvr_dev, false); +@@ -150,8 +158,8 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c + break; + + default: +- drm_info(from_pvr_device(pvr_dev), "Received unknown FWCCB command %x\n", +- cmd->cmd_type); ++ drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n", ++ cmd->cmd_type & ~ROGUE_CMD_MAGIC_DWORD_MASK); + break; + } + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0183-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch b/SPECS/linux-lts/0183-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch deleted file mode 100644 index db4eb1efc3..0000000000 --- a/SPECS/linux-lts/0183-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch +++ /dev/null @@ -1,154 +0,0 @@ -From 4a88a11688e5e382e88e35f9cf81a4be6943b420 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Mon, 16 Mar 2026 09:00:37 +0800 -Subject: [PATCH 183/467] UPSTREAM: dt-bindings: net: Add support for Spacemit - K3 dwmac - -The GMAC IP on Spacemit K3 is almost a standard Synopsys DesignWare -MAC (version 5.40a) with some extra clock. - -Add necessary compatible string for this device. - -Signed-off-by: Inochi Amaoto -Reviewed-by: Rob Herring (Arm) -Link: https://patch.msgid.link/20260316010041.164360-2-inochiama@gmail.com -Signed-off-by: Jakub Kicinski -(cherry picked from commit bb30400a566c7a6a9355873344ec63e2c6310e2c) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/net/snps,dwmac.yaml | 2 + - .../bindings/net/spacemit,k3-dwmac.yaml | 102 ++++++++++++++++++ - 2 files changed, 104 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml - -diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -index 658c004e6a5c..eb36cb36a57a 100644 ---- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml -+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -@@ -104,6 +104,7 @@ properties: - - snps,dwmac-5.10a - - snps,dwmac-5.20 - - snps,dwmac-5.30a -+ - snps,dwmac-5.40a - - snps,dwxgmac - - snps,dwxgmac-2.10 - - sophgo,sg2042-dwmac -@@ -649,6 +650,7 @@ allOf: - - snps,dwmac-5.10a - - snps,dwmac-5.20 - - snps,dwmac-5.30a -+ - snps,dwmac-5.40a - - snps,dwxgmac - - snps,dwxgmac-2.10 - - st,spear600-gmac -diff --git a/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml b/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml -new file mode 100644 -index 000000000000..678eccf044f9 ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml -@@ -0,0 +1,102 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/spacemit,k3-dwmac.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Spacemit K3 DWMAC glue layer -+ -+maintainers: -+ - Inochi Amaoto -+ -+select: -+ properties: -+ compatible: -+ contains: -+ const: spacemit,k3-dwmac -+ required: -+ - compatible -+ -+properties: -+ compatible: -+ items: -+ - const: spacemit,k3-dwmac -+ - const: snps,dwmac-5.40a -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: GMAC application clock -+ - description: PTP clock -+ - description: TX clock -+ -+ clock-names: -+ items: -+ - const: stmmaceth -+ - const: ptp_ref -+ - const: tx -+ -+ interrupts: -+ minItems: 1 -+ items: -+ - description: MAC interrupt -+ - description: MAC wake interrupt -+ -+ interrupt-names: -+ minItems: 1 -+ items: -+ - const: macirq -+ - const: eth_wake_irq -+ -+ resets: -+ maxItems: 1 -+ -+ reset-names: -+ const: stmmaceth -+ -+ spacemit,apmu: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ items: -+ - items: -+ - description: phandle to the syscon node which control the glue register -+ - description: offset of the control register -+ - description: offset of the dline register -+ description: -+ A phandle to syscon with offset to control registers for this MAC -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - interrupt-names -+ - resets -+ - reset-names -+ - spacemit,apmu -+ -+allOf: -+ - $ref: snps,dwmac.yaml# -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ -+ ethernet@cac80000 { -+ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; -+ reg = <0xcac80000 0x2000>; -+ clocks = <&syscon_apmu 66>, <&syscon_apmu 68>, -+ <&syscon_apmu 69>; -+ clock-names = "stmmaceth", "ptp_ref", "tx"; -+ interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, <276 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "macirq", "eth_wake_irq"; -+ phy-mode = "rgmii-id"; -+ phy-handle = <&phy0>; -+ resets = <&syscon_apmu 67>; -+ reset-names = "stmmaceth"; -+ spacemit,apmu = <&syscon_apmu 0x384 0x38c>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch b/SPECS/linux-lts/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch new file mode 100644 index 0000000000..d0de8aa1e5 --- /dev/null +++ b/SPECS/linux-lts/0184-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch @@ -0,0 +1,40 @@ +From 74c17747b1c536e207645c2cd6bd1399b9d2ec05 Mon Sep 17 00:00:00 2001 +From: Matt Coster +Date: Fri, 6 Feb 2026 16:02:13 +0000 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Mark FWCCB_CMD_UPDATE_STATS + as known + +Suppress the "unknown type" warning when processing a FWCCB command of +type CMD_UPDATE_STATS which is known but (currently) unused. + +Reviewed-by: Frank Binns +Link: https://patch.msgid.link/20260206-improve-bad-fwccb-cmd-v1-2-831a852ca127@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 4af267ce3441e10198daa52a8cc4b5cb4575d06f) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_ccb.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c +index 1ccd3e3dab2b..da281b5c7055 100644 +--- a/drivers/gpu/drm/imagination/pvr_ccb.c ++++ b/drivers/gpu/drm/imagination/pvr_ccb.c +@@ -157,6 +157,14 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c + pvr_free_list_process_grow_req(pvr_dev, &cmd->cmd_data.cmd_free_list_gs); + break; + ++ case ROGUE_FWIF_FWCCB_CMD_UPDATE_STATS: ++ /* ++ * We currently have no infrastructure for processing these ++ * stats. It may be added in the future, but for now just ++ * suppress the "unknown" warning when receiving this command. ++ */ ++ break; ++ + default: + drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n", + cmd->cmd_type & ~ROGUE_CMD_MAGIC_DWORD_MASK); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0184-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch b/SPECS/linux-lts/0184-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch deleted file mode 100644 index e03a1f861d..0000000000 --- a/SPECS/linux-lts/0184-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch +++ /dev/null @@ -1,34 +0,0 @@ -From c8782bd2669420615c2b9caaadd9a78cd7da0123 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Mon, 16 Mar 2026 09:00:38 +0800 -Subject: [PATCH 184/467] UPSTREAM: net: stmmac: platform: Add snps,dwmac-5.40a - IP compatible string - -Add compatible string for 5.40a version that can avoid to define some -platform data in the glue layer. - -Signed-off-by: Inochi Amaoto -Reviewed-by: Russell King (Oracle) -Link: https://patch.msgid.link/20260316010041.164360-3-inochiama@gmail.com -Signed-off-by: Jakub Kicinski -(cherry picked from commit d35aa97ea908a17809358a981bef6cd752f2e8a0) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -index 0cb51935c405..3416ca24f623 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -@@ -414,6 +414,7 @@ static const char * const stmmac_gmac4_compats[] = { - "snps,dwmac-5.10a", - "snps,dwmac-5.20", - "snps,dwmac-5.30a", -+ "snps,dwmac-5.40a", - NULL - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch b/SPECS/linux-lts/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch new file mode 100644 index 0000000000..50ffd104f5 --- /dev/null +++ b/SPECS/linux-lts/0185-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch @@ -0,0 +1,144 @@ +From 913bf005c8fcc762460c945ae4c4b99a3b30e116 Mon Sep 17 00:00:00 2001 +From: Brajesh Gupta +Date: Fri, 13 Mar 2026 06:38:24 +0000 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Improve firmware power off + for layout_mars config + +In layout_mars HW config, Firmware MCU moved from Sidekick to new Mars +domain so Firmware takes care of powering down Sidekick/Jones and SLC. +Skip checks for those from kernel and check idle bits for Firmware MCU +and system arbiter excluding SOCIF. + +Signed-off-by: Brajesh Gupta +Reviewed-by: Matt Coster +Link: https://patch.msgid.link/20260313-b4-staging-layout_mars_base-v2-1-9e3c251d278e@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 51e39ceeca7e85a3b9ca533502a404eb5f3b0f02) +Signed-off-by: Han Gao +--- + .../gpu/drm/imagination/pvr_fw_startstop.c | 85 +++++++++++++------ + 1 file changed, 57 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c +index dcbb9903e791..6ae0489f7e2e 100644 +--- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c ++++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c +@@ -209,18 +209,32 @@ pvr_fw_stop(struct pvr_device *pvr_dev) + ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN | + ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN); + bool skip_garten_idle = false; ++ u64 layout_mars_value = 0; ++ bool layout_mars = false; ++ bool meta_fw = pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META; + u32 reg_value; + int err; + ++ if (PVR_FEATURE_VALUE(pvr_dev, layout_mars, &layout_mars_value) == 0) ++ layout_mars = layout_mars_value > 0; ++ + /* +- * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. +- * For cores with the LAYOUT_MARS feature, SIDEKICK would have been ++ * For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have been + * powered down by the FW. + */ +- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, +- sidekick_idle_mask, POLL_TIMEOUT_USEC); +- if (err) +- return err; ++ if (!layout_mars) { ++ /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. */ ++ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, ++ sidekick_idle_mask, POLL_TIMEOUT_USEC); ++ if (err) ++ return err; ++ ++ /* Wait for SLC to signal IDLE. */ ++ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, ROGUE_CR_SLC_IDLE_MASKFULL, ++ ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); ++ if (err) ++ return err; ++ } + + /* Unset MTS DM association with threads. */ + pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC, +@@ -270,27 +284,25 @@ pvr_fw_stop(struct pvr_device *pvr_dev) + return err; + + /* +- * Wait for SLC to signal IDLE. +- * For cores with the LAYOUT_MARS feature, SLC would have been powered +- * down by the FW. ++ * For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have been ++ * powered down by the FW. + */ +- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, +- ROGUE_CR_SLC_IDLE_MASKFULL, +- ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); +- if (err) +- return err; ++ if (!layout_mars) { ++ /* Wait for SLC to signal IDLE. */ ++ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, ++ ROGUE_CR_SLC_IDLE_MASKFULL, ++ ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); ++ if (err) ++ return err; + +- /* +- * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. +- * For cores with the LAYOUT_MARS feature, SIDEKICK would have been powered +- * down by the FW. +- */ +- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, +- sidekick_idle_mask, POLL_TIMEOUT_USEC); +- if (err) +- return err; ++ /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. */ ++ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, ++ sidekick_idle_mask, POLL_TIMEOUT_USEC); ++ if (err) ++ return err; ++ } + +- if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META) { ++ if (meta_fw) { + err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, ®_value); + if (err) + return err; +@@ -304,11 +316,28 @@ pvr_fw_stop(struct pvr_device *pvr_dev) + skip_garten_idle = true; + } + +- if (!skip_garten_idle) { +- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, +- ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, +- ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, ++ if (meta_fw || !layout_mars) { ++ if (!skip_garten_idle) { ++ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, ++ ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, ++ ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, ++ POLL_TIMEOUT_USEC); ++ if (err) ++ return err; ++ } ++ } else { ++ /* ++ * As FW core has been moved from SIDEKICK to the new MARS domain, checking ++ * idle bits for CPU & System Arbiter excluding SOCIF which will never be ++ * idle if Host polling on this register ++ */ ++ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_MARS_IDLE, ++ ROGUE_CR_MARS_IDLE_CPU_EN | ++ ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN, ++ ROGUE_CR_MARS_IDLE_CPU_EN | ++ ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN, + POLL_TIMEOUT_USEC); ++ + if (err) + return err; + } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0185-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch b/SPECS/linux-lts/0185-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch deleted file mode 100644 index 2bfbada31b..0000000000 --- a/SPECS/linux-lts/0185-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch +++ /dev/null @@ -1,300 +0,0 @@ -From 837416c6927afd924e7c91dccfb60253d6a9e498 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Mon, 16 Mar 2026 09:00:39 +0800 -Subject: [PATCH 185/467] UPSTREAM: net: stmmac: Add glue layer for Spacemit K3 - SoC - -The ethernet controller on Spacemit K3 SoC is Synopsys DesignWare -MAC (version 5.40a), with the following special points: -1. The rate of the tx clock line is auto changed when the mac speed - rate is changed, and no need for changing the input tx clock. -2. This controller require a extra syscon device to configure the - interface type, enable wake up interrupt and delay configuration - if needed. - -Add Spacemit dwmac driver support on the Spacemit K3 SoC. - -Signed-off-by: Inochi Amaoto -Reviewed-by: Russell King (Oracle) -Link: https://patch.msgid.link/20260316010041.164360-4-inochiama@gmail.com -Signed-off-by: Jakub Kicinski -(cherry picked from commit 30f0ba420ed3fb9a16d55523ae3c1b43a6f00e22) -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 + - drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + - .../ethernet/stmicro/stmmac/dwmac-spacemit.c | 227 ++++++++++++++++++ - 3 files changed, 240 insertions(+) - create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c - -diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig -index 9507131875b2..3209353b7659 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig -+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig -@@ -206,6 +206,18 @@ config DWMAC_SOPHGO - for the stmmac device driver. This driver is used for the - ethernet controllers on various Sophgo SoCs. - -+config DWMAC_SPACEMIT -+ tristate "Spacemit dwmac support" -+ depends on OF && (ARCH_SPACEMIT || COMPILE_TEST) -+ select MFD_SYSCON -+ default m if ARCH_SPACEMIT -+ help -+ Support for ethernet controllers on Spacemit RISC-V SoCs -+ -+ This selects the Spacemit platform specific glue layer support -+ for the stmmac device driver. This driver is used for the -+ Spacemit K3 ethernet controllers. -+ - config DWMAC_STARFIVE - tristate "StarFive dwmac support" - depends on OF && (ARCH_STARFIVE || COMPILE_TEST) -diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile -index 51e068e26ce4..2a24934f5c43 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/Makefile -+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile -@@ -26,6 +26,7 @@ obj-$(CONFIG_DWMAC_RZN1) += dwmac-rzn1.o - obj-$(CONFIG_DWMAC_S32) += dwmac-s32.o - obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o - obj-$(CONFIG_DWMAC_SOPHGO) += dwmac-sophgo.o -+obj-$(CONFIG_DWMAC_SPACEMIT) += dwmac-spacemit.o - obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o - obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o - obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c -new file mode 100644 -index 000000000000..223754cc5c79 ---- /dev/null -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c -@@ -0,0 +1,227 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Spacemit DWMAC platform driver -+ * -+ * Copyright (C) 2026 Inochi Amaoto -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "stmmac_platform.h" -+ -+/* ctrl register bits */ -+#define CTRL_PHY_INTF_RGMII BIT(3) -+#define CTRL_PHY_INTF_MII BIT(4) -+#define CTRL_WAKE_IRQ_EN BIT(9) -+#define CTRL_PHY_IRQ_EN BIT(12) -+ -+/* dline register bits */ -+#define RGMII_RX_DLINE_EN BIT(0) -+#define RGMII_RX_DLINE_STEP GENMASK(5, 4) -+#define RGMII_RX_DLINE_CODE GENMASK(15, 8) -+#define RGMII_TX_DLINE_EN BIT(16) -+#define RGMII_TX_DLINE_STEP GENMASK(21, 20) -+#define RGMII_TX_DLINE_CODE GENMASK(31, 24) -+ -+#define MAX_DLINE_DELAY_CODE 0xff -+#define MAX_WORKED_DELAY 2800 -+/* Note: the delay step value is at 0.1ps */ -+#define K3_DELAY_STEP 367 -+ -+struct spacmit_dwmac { -+ struct regmap *apmu; -+ unsigned int ctrl_offset; -+ unsigned int dline_offset; -+}; -+ -+static int spacemit_dwmac_set_delay(struct spacmit_dwmac *dwmac, -+ unsigned int tx_code, unsigned int rx_code) -+{ -+ unsigned int mask, val; -+ -+ mask = RGMII_TX_DLINE_STEP | RGMII_TX_DLINE_CODE | RGMII_TX_DLINE_EN | -+ RGMII_RX_DLINE_STEP | RGMII_RX_DLINE_CODE | RGMII_RX_DLINE_EN; -+ -+ /* -+ * Since the delay step provided by config 0 is small enough, and -+ * it can cover the range of the valid delay, so there is no needed -+ * to use other step config. -+ */ -+ val = FIELD_PREP(RGMII_TX_DLINE_STEP, 0) | -+ FIELD_PREP(RGMII_TX_DLINE_CODE, tx_code) | RGMII_TX_DLINE_EN | -+ FIELD_PREP(RGMII_RX_DLINE_STEP, 0) | -+ FIELD_PREP(RGMII_RX_DLINE_CODE, rx_code) | RGMII_RX_DLINE_EN; -+ -+ return regmap_update_bits(dwmac->apmu, dwmac->dline_offset, -+ mask, val); -+} -+ -+static int spacemit_dwmac_detected_delay_value(unsigned int delay) -+{ -+ if (delay == 0) -+ return 0; -+ -+ if (delay > MAX_WORKED_DELAY) -+ return -EINVAL; -+ -+ /* -+ * Note K3 require a specific factor for calculate -+ * the delay, in this scenario it is 0.9. So the -+ * formula is code * step / 10 * 0.9 -+ */ -+ return DIV_ROUND_CLOSEST(delay * 10 * 10, K3_DELAY_STEP * 9); -+} -+ -+static int spacemit_dwmac_fix_delay(struct spacmit_dwmac *dwmac, -+ unsigned int tx_delay, -+ unsigned int rx_delay) -+{ -+ int rx_code; -+ int tx_code; -+ -+ rx_code = spacemit_dwmac_detected_delay_value(rx_delay); -+ if (rx_code < 0) -+ return rx_code; -+ -+ tx_code = spacemit_dwmac_detected_delay_value(tx_delay); -+ if (tx_code < 0) -+ return tx_code; -+ -+ return spacemit_dwmac_set_delay(dwmac, tx_code, rx_code); -+} -+ -+static int spacemit_dwmac_update_irq_config(struct spacmit_dwmac *dwmac, -+ struct stmmac_resources *stmmac_res) -+{ -+ unsigned int val = stmmac_res->wol_irq >= 0 ? CTRL_WAKE_IRQ_EN : 0; -+ unsigned int mask = CTRL_WAKE_IRQ_EN; -+ -+ return regmap_update_bits(dwmac->apmu, dwmac->ctrl_offset, -+ mask, val); -+} -+ -+static void spacemit_get_interfaces(struct stmmac_priv *priv, void *bsp_priv, -+ unsigned long *interfaces) -+{ -+ __set_bit(PHY_INTERFACE_MODE_MII, interfaces); -+ __set_bit(PHY_INTERFACE_MODE_RMII, interfaces); -+ phy_interface_set_rgmii(interfaces); -+} -+ -+static int spacemit_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel) -+{ -+ unsigned int mask = CTRL_PHY_INTF_MII | CTRL_PHY_INTF_RGMII; -+ struct spacmit_dwmac *dwmac = bsp_priv; -+ unsigned int val = 0; -+ -+ switch (phy_intf_sel) { -+ case PHY_INTF_SEL_GMII_MII: -+ val = CTRL_PHY_INTF_MII; -+ break; -+ -+ case PHY_INTF_SEL_RMII: -+ break; -+ -+ case PHY_INTF_SEL_RGMII: -+ val = CTRL_PHY_INTF_RGMII; -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ return regmap_update_bits(dwmac->apmu, dwmac->ctrl_offset, -+ mask, val); -+} -+ -+static int spacemit_dwmac_probe(struct platform_device *pdev) -+{ -+ struct plat_stmmacenet_data *plat_dat; -+ struct stmmac_resources stmmac_res; -+ struct device *dev = &pdev->dev; -+ struct spacmit_dwmac *dwmac; -+ unsigned int offset[2]; -+ struct regmap *apmu; -+ struct clk *clk_tx; -+ u32 rx_delay = 0; -+ u32 tx_delay = 0; -+ int ret; -+ -+ ret = stmmac_get_platform_resources(pdev, &stmmac_res); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "failed to get platform resources\n"); -+ -+ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); -+ if (!dwmac) -+ return -ENOMEM; -+ -+ plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); -+ if (IS_ERR(plat_dat)) -+ return dev_err_probe(dev, PTR_ERR(plat_dat), -+ "failed to parse DT parameters\n"); -+ -+ clk_tx = devm_clk_get_enabled(&pdev->dev, "tx"); -+ if (IS_ERR(clk_tx)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(clk_tx), -+ "failed to get tx clock\n"); -+ -+ apmu = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, -+ "spacemit,apmu", 2, -+ offset); -+ if (IS_ERR(apmu)) -+ return dev_err_probe(dev, PTR_ERR(apmu), -+ "Failed to get apmu regmap\n"); -+ -+ dwmac->apmu = apmu; -+ dwmac->ctrl_offset = offset[0]; -+ dwmac->dline_offset = offset[1]; -+ -+ ret = spacemit_dwmac_update_irq_config(dwmac, &stmmac_res); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to configure irq config\n"); -+ -+ of_property_read_u32(pdev->dev.of_node, "tx-internal-delay-ps", -+ &tx_delay); -+ of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps", -+ &rx_delay); -+ -+ plat_dat->get_interfaces = spacemit_get_interfaces; -+ plat_dat->set_phy_intf_sel = spacemit_set_phy_intf_sel; -+ plat_dat->bsp_priv = dwmac; -+ -+ ret = spacemit_dwmac_fix_delay(dwmac, tx_delay, rx_delay); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to configure delay\n"); -+ -+ return stmmac_dvr_probe(dev, plat_dat, &stmmac_res); -+} -+ -+static const struct of_device_id spacemit_dwmac_match[] = { -+ { .compatible = "spacemit,k3-dwmac" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, spacemit_dwmac_match); -+ -+static struct platform_driver spacemit_dwmac_driver = { -+ .probe = spacemit_dwmac_probe, -+ .remove = stmmac_pltfr_remove, -+ .driver = { -+ .name = "spacemit-dwmac", -+ .pm = &stmmac_pltfr_pm_ops, -+ .of_match_table = spacemit_dwmac_match, -+ }, -+}; -+module_platform_driver(spacemit_dwmac_driver); -+ -+MODULE_AUTHOR("Inochi Amaoto "); -+MODULE_DESCRIPTION("Spacemit DWMAC platform driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0186-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch b/SPECS/linux-lts/0186-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch deleted file mode 100644 index 6e6ee0a8cc..0000000000 --- a/SPECS/linux-lts/0186-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 870f5224fe15bfcd81de45da48168616a0d5c1d5 Mon Sep 17 00:00:00 2001 -From: Matt Coster -Date: Fri, 6 Feb 2026 16:02:12 +0000 -Subject: [PATCH 186/467] UPSTREAM: drm/imagination: Improve handling of - unknown FWCCB commands - -A couple small changes: - - Validate the magic value at the head of FWCCB commands, and - - Mask off the magic value before logging unknown command types to make - them easier to interpret on sight. - -Reviewed-by: Frank Binns -Link: https://patch.msgid.link/20260206-improve-bad-fwccb-cmd-v1-1-831a852ca127@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit c7384288d9266e52cd35aadb1749872caf3c0257) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_ccb.c | 12 ++++++++++-- - 1 file changed, 10 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c -index 2bbdc05a3b97..1ccd3e3dab2b 100644 ---- a/drivers/gpu/drm/imagination/pvr_ccb.c -+++ b/drivers/gpu/drm/imagination/pvr_ccb.c -@@ -135,6 +135,14 @@ pvr_ccb_slot_available_locked(struct pvr_ccb *pvr_ccb, u32 *write_offset) - static void - process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *cmd) - { -+ struct drm_device *drm_dev = from_pvr_device(pvr_dev); -+ -+ if ((cmd->cmd_type & ROGUE_CMD_MAGIC_DWORD_MASK) != ROGUE_CMD_MAGIC_DWORD_SHIFTED) { -+ drm_warn_once(drm_dev, "Received FWCCB command with bad magic value; ignoring (type=0x%08x)\n", -+ cmd->cmd_type); -+ return; -+ } -+ - switch (cmd->cmd_type) { - case ROGUE_FWIF_FWCCB_CMD_REQUEST_GPU_RESTART: - pvr_power_reset(pvr_dev, false); -@@ -150,8 +158,8 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c - break; - - default: -- drm_info(from_pvr_device(pvr_dev), "Received unknown FWCCB command %x\n", -- cmd->cmd_type); -+ drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n", -+ cmd->cmd_type & ~ROGUE_CMD_MAGIC_DWORD_MASK); - break; - } - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch b/SPECS/linux-lts/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch new file mode 100644 index 0000000000..30928dca28 --- /dev/null +++ b/SPECS/linux-lts/0186-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch @@ -0,0 +1,47 @@ +From 1c4786d466085bd7d5e793bc432f8d9d77048fb9 Mon Sep 17 00:00:00 2001 +From: Brajesh Gupta +Date: Fri, 13 Mar 2026 06:38:25 +0000 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Skip 2nd thread DM + association for non META Firmware + +Only a META firmware can have two threads. + +Signed-off-by: Brajesh Gupta +Reviewed-by: Matt Coster +Link: https://patch.msgid.link/20260313-b4-staging-layout_mars_base-v2-2-9e3c251d278e@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 62a6f98cda4ec75107e96571346349a649fc63d1) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_fw_startstop.c | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c +index 6ae0489f7e2e..e24ed6fc4362 100644 +--- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c ++++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c +@@ -243,12 +243,15 @@ pvr_fw_stop(struct pvr_device *pvr_dev) + pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC, + ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL & + ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK); +- pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, +- ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & +- ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); +- pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, +- ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & +- ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); ++ ++ if (meta_fw) { ++ pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, ++ ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & ++ ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); ++ pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, ++ ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & ++ ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); ++ } + + /* Extra Idle checks. */ + err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_STATUS_MMU, 0, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch b/SPECS/linux-lts/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch new file mode 100644 index 0000000000..74f768a3dd --- /dev/null +++ b/SPECS/linux-lts/0187-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch @@ -0,0 +1,53 @@ +From 2af0a8e17c8cfcbee59a2a2f6315c394a0342dc5 Mon Sep 17 00:00:00 2001 +From: Alexandru Dadu +Date: Mon, 23 Mar 2026 20:31:28 +0200 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Add missing rogue context + reset reasons + +Update the context reset reason enum with the missing reset reasons in +the 6-11 value gap: + - CDM Mission/safety checksum mismatch; + - TRP checksum mismatch; + - GPU ECC error (corrected, OK); + - GPU ECC error (uncorrected, HWR); + - FW ECC error (corrected, OK); + - FW ECC error (uncorrected, ERR); + +Co-developed-by: Sarah Walker +Signed-off-by: Sarah Walker +Signed-off-by: Alexandru Dadu +Reviewed-by: Matt Coster +Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-1-1a66049a9a65@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit da173557a2b090d7d8c155283ba489a287983ced) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h +index f95acd5a1f8e..869d904e3649 100644 +--- a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h ++++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h +@@ -236,6 +236,18 @@ enum rogue_context_reset_reason { + ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING = 4, + /* Forced reset to ensure scheduling requirements */ + ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH = 5, ++ /* CDM Mission/safety checksum mismatch */ ++ ROGUE_CONTEXT_RESET_REASON_WGP_CHECKSUM = 6, ++ /* TRP checksum mismatch */ ++ ROGUE_CONTEXT_RESET_REASON_TRP_CHECKSUM = 7, ++ /* GPU ECC error (corrected, OK) */ ++ ROGUE_CONTEXT_RESET_REASON_GPU_ECC_OK = 8, ++ /* GPU ECC error (uncorrected, HWR) */ ++ ROGUE_CONTEXT_RESET_REASON_GPU_ECC_HWR = 9, ++ /* FW ECC error (corrected, OK) */ ++ ROGUE_CONTEXT_RESET_REASON_FW_ECC_OK = 10, ++ /* FW ECC error (uncorrected, ERR) */ ++ ROGUE_CONTEXT_RESET_REASON_FW_ECC_ERR = 11, + /* FW Safety watchdog triggered */ + ROGUE_CONTEXT_RESET_REASON_FW_WATCHDOG = 12, + /* FW page fault (no HWR) */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0187-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch b/SPECS/linux-lts/0187-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch deleted file mode 100644 index 46f5bd7d70..0000000000 --- a/SPECS/linux-lts/0187-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 5e86b21fc9e1bab746f921d406840979e1851e0e Mon Sep 17 00:00:00 2001 -From: Matt Coster -Date: Fri, 6 Feb 2026 16:02:13 +0000 -Subject: [PATCH 187/467] UPSTREAM: drm/imagination: Mark - FWCCB_CMD_UPDATE_STATS as known - -Suppress the "unknown type" warning when processing a FWCCB command of -type CMD_UPDATE_STATS which is known but (currently) unused. - -Reviewed-by: Frank Binns -Link: https://patch.msgid.link/20260206-improve-bad-fwccb-cmd-v1-2-831a852ca127@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 4af267ce3441e10198daa52a8cc4b5cb4575d06f) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_ccb.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c -index 1ccd3e3dab2b..da281b5c7055 100644 ---- a/drivers/gpu/drm/imagination/pvr_ccb.c -+++ b/drivers/gpu/drm/imagination/pvr_ccb.c -@@ -157,6 +157,14 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c - pvr_free_list_process_grow_req(pvr_dev, &cmd->cmd_data.cmd_free_list_gs); - break; - -+ case ROGUE_FWIF_FWCCB_CMD_UPDATE_STATS: -+ /* -+ * We currently have no infrastructure for processing these -+ * stats. It may be added in the future, but for now just -+ * suppress the "unknown" warning when receiving this command. -+ */ -+ break; -+ - default: - drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n", - cmd->cmd_type & ~ROGUE_CMD_MAGIC_DWORD_MASK); --- -2.53.0 - diff --git a/SPECS/linux-lts/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch b/SPECS/linux-lts/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch new file mode 100644 index 0000000000..0b560df8fc --- /dev/null +++ b/SPECS/linux-lts/0188-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch @@ -0,0 +1,208 @@ +From 3ea351d649da005c14bb7563aff7c5a258116a18 Mon Sep 17 00:00:00 2001 +From: Alexandru Dadu +Date: Mon, 23 Mar 2026 20:31:30 +0200 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Implement handling of context + reset notification + +The firmware will send the context reset notification message as +part of handling hardware recovery (HWR) events deecoding the message +and printing via drm_info(). This eliminates the "Unknown FWCCB command" +message that was previously printed. + +Co-developed-by: Sarah Walker +Signed-off-by: Sarah Walker +Signed-off-by: Alexandru Dadu +Reviewed-by: Matt Coster +Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-3-1a66049a9a65@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit d994acc526c70d40ec9029cfe03d08ee411083c5) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/Makefile | 1 + + drivers/gpu/drm/imagination/pvr_ccb.c | 5 ++ + drivers/gpu/drm/imagination/pvr_dump.c | 113 +++++++++++++++++++++++++ + drivers/gpu/drm/imagination/pvr_dump.h | 17 ++++ + 4 files changed, 136 insertions(+) + create mode 100644 drivers/gpu/drm/imagination/pvr_dump.c + create mode 100644 drivers/gpu/drm/imagination/pvr_dump.h + +diff --git a/drivers/gpu/drm/imagination/Makefile b/drivers/gpu/drm/imagination/Makefile +index 7cca66f00a38..d94a8f592c74 100644 +--- a/drivers/gpu/drm/imagination/Makefile ++++ b/drivers/gpu/drm/imagination/Makefile +@@ -8,6 +8,7 @@ powervr-y := \ + pvr_device.o \ + pvr_device_info.o \ + pvr_drv.o \ ++ pvr_dump.o \ + pvr_free_list.o \ + pvr_fw.o \ + pvr_fw_meta.o \ +diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c +index da281b5c7055..8e8e7c1e0b03 100644 +--- a/drivers/gpu/drm/imagination/pvr_ccb.c ++++ b/drivers/gpu/drm/imagination/pvr_ccb.c +@@ -4,6 +4,7 @@ + #include "pvr_ccb.h" + #include "pvr_device.h" + #include "pvr_drv.h" ++#include "pvr_dump.h" + #include "pvr_free_list.h" + #include "pvr_fw.h" + #include "pvr_gem.h" +@@ -164,6 +165,10 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c + * suppress the "unknown" warning when receiving this command. + */ + break; ++ case ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_NOTIFICATION: ++ pvr_dump_context_reset_notification(pvr_dev, ++ &cmd->cmd_data.cmd_context_reset_notification); ++ break; + + default: + drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n", +diff --git a/drivers/gpu/drm/imagination/pvr_dump.c b/drivers/gpu/drm/imagination/pvr_dump.c +new file mode 100644 +index 000000000000..52e95fce2817 +--- /dev/null ++++ b/drivers/gpu/drm/imagination/pvr_dump.c +@@ -0,0 +1,113 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* Copyright (c) 2026 Imagination Technologies Ltd. */ ++ ++#include "pvr_device.h" ++#include "pvr_dump.h" ++#include "pvr_rogue_fwif.h" ++ ++#include ++#include ++ ++static const char * ++get_reset_reason_desc(enum rogue_context_reset_reason reason) ++{ ++ switch (reason) { ++ case ROGUE_CONTEXT_RESET_REASON_NONE: ++ return "None"; ++ case ROGUE_CONTEXT_RESET_REASON_GUILTY_LOCKUP: ++ return "Guilty lockup"; ++ case ROGUE_CONTEXT_RESET_REASON_INNOCENT_LOCKUP: ++ return "Innocent lockup"; ++ case ROGUE_CONTEXT_RESET_REASON_GUILTY_OVERRUNING: ++ return "Guilty overrunning"; ++ case ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING: ++ return "Innocent overrunning"; ++ case ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH: ++ return "Hard context switch"; ++ case ROGUE_CONTEXT_RESET_REASON_WGP_CHECKSUM: ++ return "CDM Mission/safety checksum mismatch"; ++ case ROGUE_CONTEXT_RESET_REASON_TRP_CHECKSUM: ++ return "TRP checksum mismatch"; ++ case ROGUE_CONTEXT_RESET_REASON_GPU_ECC_OK: ++ return "GPU ECC error (corrected, OK)"; ++ case ROGUE_CONTEXT_RESET_REASON_GPU_ECC_HWR: ++ return "GPU ECC error (uncorrected, HWR)"; ++ case ROGUE_CONTEXT_RESET_REASON_FW_ECC_OK: ++ return "Firmware ECC error (corrected, OK)"; ++ case ROGUE_CONTEXT_RESET_REASON_FW_ECC_ERR: ++ return "Firmware ECC error (uncorrected, ERR)"; ++ case ROGUE_CONTEXT_RESET_REASON_FW_WATCHDOG: ++ return "Firmware watchdog"; ++ case ROGUE_CONTEXT_RESET_REASON_FW_PAGEFAULT: ++ return "Firmware pagefault"; ++ case ROGUE_CONTEXT_RESET_REASON_FW_EXEC_ERR: ++ return "Firmware execution error"; ++ case ROGUE_CONTEXT_RESET_REASON_HOST_WDG_FW_ERR: ++ return "Host watchdog"; ++ case ROGUE_CONTEXT_GEOM_OOM_DISABLED: ++ return "Geometry OOM disabled"; ++ ++ default: ++ return "Unknown"; ++ } ++} ++ ++static const char * ++get_dm_name(u32 dm) ++{ ++ switch (dm) { ++ case PVR_FWIF_DM_GP: ++ return "General purpose"; ++ /* PVR_FWIF_DM_TDM has the same index, but is discriminated by a device feature */ ++ case PVR_FWIF_DM_2D: ++ return "2D or TDM"; ++ case PVR_FWIF_DM_GEOM: ++ return "Geometry"; ++ case PVR_FWIF_DM_FRAG: ++ return "Fragment"; ++ case PVR_FWIF_DM_CDM: ++ return "Compute"; ++ case PVR_FWIF_DM_RAY: ++ return "Raytracing"; ++ case PVR_FWIF_DM_GEOM2: ++ return "Geometry 2"; ++ case PVR_FWIF_DM_GEOM3: ++ return "Geometry 3"; ++ case PVR_FWIF_DM_GEOM4: ++ return "Geometry 4"; ++ ++ default: ++ return "Unknown"; ++ } ++} ++ ++/** ++ * pvr_dump_context_reset_notification() - Handle context reset notification from FW ++ * @pvr_dev: Device pointer. ++ * @data: Data provided by FW. ++ * ++ * This will decode the data structure provided by FW and print the results via drm_info(). ++ */ ++void ++pvr_dump_context_reset_notification(struct pvr_device *pvr_dev, ++ struct rogue_fwif_fwccb_cmd_context_reset_data *data) ++{ ++ struct drm_device *drm_dev = from_pvr_device(pvr_dev); ++ ++ if (data->flags & ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_FLAG_ALL_CTXS) { ++ drm_info(drm_dev, "Received context reset notification for all contexts\n"); ++ } else { ++ drm_info(drm_dev, "Received context reset notification on context %u\n", ++ data->server_common_context_id); ++ } ++ ++ drm_info(drm_dev, " Reset reason=%u (%s)\n", data->reset_reason, ++ get_reset_reason_desc((enum rogue_context_reset_reason)data->reset_reason)); ++ drm_info(drm_dev, " Data Master=%u (%s)\n", data->dm, get_dm_name(data->dm)); ++ drm_info(drm_dev, " Job ref=%u\n", data->reset_job_ref); ++ ++ if (data->flags & ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_FLAG_PF) { ++ drm_info(drm_dev, " Page fault occurred, fault address=%llx\n", ++ data->fault_address); ++ } ++} +diff --git a/drivers/gpu/drm/imagination/pvr_dump.h b/drivers/gpu/drm/imagination/pvr_dump.h +new file mode 100644 +index 000000000000..3c0728c05596 +--- /dev/null ++++ b/drivers/gpu/drm/imagination/pvr_dump.h +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR MIT */ ++/* Copyright (c) 2026 Imagination Technologies Ltd. */ ++ ++#ifndef PVR_DUMP_H ++#define PVR_DUMP_H ++ ++/* Forward declaration from pvr_device.h. */ ++struct pvr_device; ++ ++/* Forward declaration from pvr_rogue_fwif.h. */ ++struct rogue_fwif_fwccb_cmd_context_reset_data; ++ ++void ++pvr_dump_context_reset_notification(struct pvr_device *pvr_dev, ++ struct rogue_fwif_fwccb_cmd_context_reset_data *data); ++ ++#endif /* PVR_DUMP_H */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0188-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch b/SPECS/linux-lts/0188-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch deleted file mode 100644 index c50be1defc..0000000000 --- a/SPECS/linux-lts/0188-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch +++ /dev/null @@ -1,144 +0,0 @@ -From c27b56fa68e0dc9f68c93f5024501db480e2a75f Mon Sep 17 00:00:00 2001 -From: Brajesh Gupta -Date: Fri, 13 Mar 2026 06:38:24 +0000 -Subject: [PATCH 188/467] UPSTREAM: drm/imagination: Improve firmware power off - for layout_mars config - -In layout_mars HW config, Firmware MCU moved from Sidekick to new Mars -domain so Firmware takes care of powering down Sidekick/Jones and SLC. -Skip checks for those from kernel and check idle bits for Firmware MCU -and system arbiter excluding SOCIF. - -Signed-off-by: Brajesh Gupta -Reviewed-by: Matt Coster -Link: https://patch.msgid.link/20260313-b4-staging-layout_mars_base-v2-1-9e3c251d278e@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 51e39ceeca7e85a3b9ca533502a404eb5f3b0f02) -Signed-off-by: Han Gao ---- - .../gpu/drm/imagination/pvr_fw_startstop.c | 85 +++++++++++++------ - 1 file changed, 57 insertions(+), 28 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c -index dcbb9903e791..6ae0489f7e2e 100644 ---- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c -+++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c -@@ -209,18 +209,32 @@ pvr_fw_stop(struct pvr_device *pvr_dev) - ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN | - ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN); - bool skip_garten_idle = false; -+ u64 layout_mars_value = 0; -+ bool layout_mars = false; -+ bool meta_fw = pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META; - u32 reg_value; - int err; - -+ if (PVR_FEATURE_VALUE(pvr_dev, layout_mars, &layout_mars_value) == 0) -+ layout_mars = layout_mars_value > 0; -+ - /* -- * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. -- * For cores with the LAYOUT_MARS feature, SIDEKICK would have been -+ * For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have been - * powered down by the FW. - */ -- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, -- sidekick_idle_mask, POLL_TIMEOUT_USEC); -- if (err) -- return err; -+ if (!layout_mars) { -+ /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. */ -+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, -+ sidekick_idle_mask, POLL_TIMEOUT_USEC); -+ if (err) -+ return err; -+ -+ /* Wait for SLC to signal IDLE. */ -+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, ROGUE_CR_SLC_IDLE_MASKFULL, -+ ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); -+ if (err) -+ return err; -+ } - - /* Unset MTS DM association with threads. */ - pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC, -@@ -270,27 +284,25 @@ pvr_fw_stop(struct pvr_device *pvr_dev) - return err; - - /* -- * Wait for SLC to signal IDLE. -- * For cores with the LAYOUT_MARS feature, SLC would have been powered -- * down by the FW. -+ * For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have been -+ * powered down by the FW. - */ -- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, -- ROGUE_CR_SLC_IDLE_MASKFULL, -- ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); -- if (err) -- return err; -+ if (!layout_mars) { -+ /* Wait for SLC to signal IDLE. */ -+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, -+ ROGUE_CR_SLC_IDLE_MASKFULL, -+ ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC); -+ if (err) -+ return err; - -- /* -- * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. -- * For cores with the LAYOUT_MARS feature, SIDEKICK would have been powered -- * down by the FW. -- */ -- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, -- sidekick_idle_mask, POLL_TIMEOUT_USEC); -- if (err) -- return err; -+ /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. */ -+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask, -+ sidekick_idle_mask, POLL_TIMEOUT_USEC); -+ if (err) -+ return err; -+ } - -- if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META) { -+ if (meta_fw) { - err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, ®_value); - if (err) - return err; -@@ -304,11 +316,28 @@ pvr_fw_stop(struct pvr_device *pvr_dev) - skip_garten_idle = true; - } - -- if (!skip_garten_idle) { -- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, -- ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, -- ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, -+ if (meta_fw || !layout_mars) { -+ if (!skip_garten_idle) { -+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, -+ ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, -+ ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN, -+ POLL_TIMEOUT_USEC); -+ if (err) -+ return err; -+ } -+ } else { -+ /* -+ * As FW core has been moved from SIDEKICK to the new MARS domain, checking -+ * idle bits for CPU & System Arbiter excluding SOCIF which will never be -+ * idle if Host polling on this register -+ */ -+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_MARS_IDLE, -+ ROGUE_CR_MARS_IDLE_CPU_EN | -+ ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN, -+ ROGUE_CR_MARS_IDLE_CPU_EN | -+ ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN, - POLL_TIMEOUT_USEC); -+ - if (err) - return err; - } --- -2.53.0 - diff --git a/SPECS/linux-lts/0189-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch b/SPECS/linux-lts/0189-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch deleted file mode 100644 index a38db47b95..0000000000 --- a/SPECS/linux-lts/0189-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 5fa9c63710bdd821c67cb83870bd773ad29fb978 Mon Sep 17 00:00:00 2001 -From: Brajesh Gupta -Date: Fri, 13 Mar 2026 06:38:25 +0000 -Subject: [PATCH 189/467] UPSTREAM: drm/imagination: Skip 2nd thread DM - association for non META Firmware - -Only a META firmware can have two threads. - -Signed-off-by: Brajesh Gupta -Reviewed-by: Matt Coster -Link: https://patch.msgid.link/20260313-b4-staging-layout_mars_base-v2-2-9e3c251d278e@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 62a6f98cda4ec75107e96571346349a649fc63d1) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_fw_startstop.c | 15 +++++++++------ - 1 file changed, 9 insertions(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c -index 6ae0489f7e2e..e24ed6fc4362 100644 ---- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c -+++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c -@@ -243,12 +243,15 @@ pvr_fw_stop(struct pvr_device *pvr_dev) - pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC, - ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL & - ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK); -- pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, -- ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & -- ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); -- pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, -- ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & -- ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); -+ -+ if (meta_fw) { -+ pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC, -+ ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL & -+ ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); -+ pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC, -+ ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL & -+ ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK); -+ } - - /* Extra Idle checks. */ - err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_STATUS_MMU, 0, --- -2.53.0 - diff --git a/SPECS/linux-lts/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch b/SPECS/linux-lts/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch new file mode 100644 index 0000000000..f7d478ada1 --- /dev/null +++ b/SPECS/linux-lts/0189-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch @@ -0,0 +1,37 @@ +From e88d780551651b13977fcb9a0fc500f0edc4ec8d Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:15 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: vendor-prefixes: add verisilicon + +VeriSilicon is a Silicon IP vendor, which is the current owner of +Vivante series video-related IPs and Hantro series video codec IPs. + +Add a vendor prefix for this company. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Acked-by: Rob Herring (Arm) +Signed-off-by: Thomas Zimmermann +Link: https://patch.msgid.link/20260129023922.1527729-2-zhengxingda@iscas.ac.cn +(cherry picked from commit c131d78840d7487e41c3afdc52bb74fd3f8861ef) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml +index 647746e6f75f..d03f700d178e 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml ++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml +@@ -1723,6 +1723,8 @@ patternProperties: + description: Variscite Ltd. + "^vdl,.*": + description: Van der Laan b.v. ++ "^verisilicon,.*": ++ description: VeriSilicon Microelectronics (Shanghai) Co., Ltd. + "^vertexcom,.*": + description: Vertexcom Technologies, Inc. + "^via,.*": +-- +2.53.0 + diff --git a/SPECS/linux-lts/0190-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch b/SPECS/linux-lts/0190-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch deleted file mode 100644 index 47548d9611..0000000000 --- a/SPECS/linux-lts/0190-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch +++ /dev/null @@ -1,53 +0,0 @@ -From abb8bc1c87a792d8e9fb2ec18bace8773ff287fa Mon Sep 17 00:00:00 2001 -From: Alexandru Dadu -Date: Mon, 23 Mar 2026 20:31:28 +0200 -Subject: [PATCH 190/467] UPSTREAM: drm/imagination: Add missing rogue context - reset reasons - -Update the context reset reason enum with the missing reset reasons in -the 6-11 value gap: - - CDM Mission/safety checksum mismatch; - - TRP checksum mismatch; - - GPU ECC error (corrected, OK); - - GPU ECC error (uncorrected, HWR); - - FW ECC error (corrected, OK); - - FW ECC error (uncorrected, ERR); - -Co-developed-by: Sarah Walker -Signed-off-by: Sarah Walker -Signed-off-by: Alexandru Dadu -Reviewed-by: Matt Coster -Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-1-1a66049a9a65@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit da173557a2b090d7d8c155283ba489a287983ced) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -index f95acd5a1f8e..869d904e3649 100644 ---- a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -@@ -236,6 +236,18 @@ enum rogue_context_reset_reason { - ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING = 4, - /* Forced reset to ensure scheduling requirements */ - ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH = 5, -+ /* CDM Mission/safety checksum mismatch */ -+ ROGUE_CONTEXT_RESET_REASON_WGP_CHECKSUM = 6, -+ /* TRP checksum mismatch */ -+ ROGUE_CONTEXT_RESET_REASON_TRP_CHECKSUM = 7, -+ /* GPU ECC error (corrected, OK) */ -+ ROGUE_CONTEXT_RESET_REASON_GPU_ECC_OK = 8, -+ /* GPU ECC error (uncorrected, HWR) */ -+ ROGUE_CONTEXT_RESET_REASON_GPU_ECC_HWR = 9, -+ /* FW ECC error (corrected, OK) */ -+ ROGUE_CONTEXT_RESET_REASON_FW_ECC_OK = 10, -+ /* FW ECC error (uncorrected, ERR) */ -+ ROGUE_CONTEXT_RESET_REASON_FW_ECC_ERR = 11, - /* FW Safety watchdog triggered */ - ROGUE_CONTEXT_RESET_REASON_FW_WATCHDOG = 12, - /* FW page fault (no HWR) */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch b/SPECS/linux-lts/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch new file mode 100644 index 0000000000..3ab06308e6 --- /dev/null +++ b/SPECS/linux-lts/0190-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch @@ -0,0 +1,157 @@ +From 0097108abfd8e7e0526f283feef46f9ff85d3019 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:16 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: display: add verisilicon,dc + +Verisilicon has a series of display controllers prefixed with DC and +with self-identification facility like their GC series GPUs. + +Add a device tree binding for it. + +Depends on the specific DC model, it can have either one or two display +outputs, and each display output could be set to DPI signal or "DP" +signal (which seems to be some plain parallel bus to HDMI controllers). + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Thomas Zimmermann +Link: https://patch.msgid.link/20260129023922.1527729-3-zhengxingda@iscas.ac.cn +(cherry picked from commit 5f6965fa1e2ec8ac69e1d448d343a528dc60cdfb) +Signed-off-by: Han Gao +--- + .../bindings/display/verisilicon,dc.yaml | 122 ++++++++++++++++++ + 1 file changed, 122 insertions(+) + create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml + +diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml +new file mode 100644 +index 000000000000..9dc35ab973f2 +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml +@@ -0,0 +1,122 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Verisilicon DC-series display controllers ++ ++maintainers: ++ - Icenowy Zheng ++ ++properties: ++ $nodename: ++ pattern: "^display@[0-9a-f]+$" ++ ++ compatible: ++ items: ++ - enum: ++ - thead,th1520-dc8200 ++ - const: verisilicon,dc # DC IPs have discoverable ID/revision registers ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: DC Core clock ++ - description: DMA AXI bus clock ++ - description: Configuration AHB bus clock ++ - description: Pixel clock of output 0 ++ - description: Pixel clock of output 1 ++ ++ clock-names: ++ items: ++ - const: core ++ - const: axi ++ - const: ahb ++ - const: pix0 ++ - const: pix1 ++ ++ resets: ++ items: ++ - description: DC Core reset ++ - description: DMA AXI bus reset ++ - description: Configuration AHB bus reset ++ ++ reset-names: ++ items: ++ - const: core ++ - const: axi ++ - const: ahb ++ ++ ports: ++ $ref: /schemas/graph.yaml#/properties/ports ++ ++ properties: ++ port@0: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: The first output channel , endpoint 0 should be ++ used for DPI format output and endpoint 1 should be used ++ for DP format output. ++ ++ port@1: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: The second output channel if the DC variant ++ supports. Follow the same endpoint addressing rule with ++ the first port. ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ - ports ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ display@ffef600000 { ++ compatible = "thead,th1520-dc8200", "verisilicon,dc"; ++ reg = <0xff 0xef600000 0x0 0x100000>; ++ interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_vo CLK_DPU_CCLK>, ++ <&clk_vo CLK_DPU_ACLK>, ++ <&clk_vo CLK_DPU_HCLK>, ++ <&clk_vo CLK_DPU_PIXELCLK0>, ++ <&clk_vo CLK_DPU_PIXELCLK1>; ++ clock-names = "core", "axi", "ahb", "pix0", "pix1"; ++ resets = <&rst TH1520_RESET_ID_DPU_CORE>, ++ <&rst TH1520_RESET_ID_DPU_AXI>, ++ <&rst TH1520_RESET_ID_DPU_AHB>; ++ reset-names = "core", "axi", "ahb"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dpu_out_dp1: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&hdmi_in>; ++ }; ++ }; ++ }; ++ }; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0191-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch b/SPECS/linux-lts/0191-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch deleted file mode 100644 index 239f0e4598..0000000000 --- a/SPECS/linux-lts/0191-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch +++ /dev/null @@ -1,208 +0,0 @@ -From 8b9e78b54cb9659d9121ea4bf1e3368763df3af7 Mon Sep 17 00:00:00 2001 -From: Alexandru Dadu -Date: Mon, 23 Mar 2026 20:31:30 +0200 -Subject: [PATCH 191/467] UPSTREAM: drm/imagination: Implement handling of - context reset notification - -The firmware will send the context reset notification message as -part of handling hardware recovery (HWR) events deecoding the message -and printing via drm_info(). This eliminates the "Unknown FWCCB command" -message that was previously printed. - -Co-developed-by: Sarah Walker -Signed-off-by: Sarah Walker -Signed-off-by: Alexandru Dadu -Reviewed-by: Matt Coster -Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-3-1a66049a9a65@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit d994acc526c70d40ec9029cfe03d08ee411083c5) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/Makefile | 1 + - drivers/gpu/drm/imagination/pvr_ccb.c | 5 ++ - drivers/gpu/drm/imagination/pvr_dump.c | 113 +++++++++++++++++++++++++ - drivers/gpu/drm/imagination/pvr_dump.h | 17 ++++ - 4 files changed, 136 insertions(+) - create mode 100644 drivers/gpu/drm/imagination/pvr_dump.c - create mode 100644 drivers/gpu/drm/imagination/pvr_dump.h - -diff --git a/drivers/gpu/drm/imagination/Makefile b/drivers/gpu/drm/imagination/Makefile -index 7cca66f00a38..d94a8f592c74 100644 ---- a/drivers/gpu/drm/imagination/Makefile -+++ b/drivers/gpu/drm/imagination/Makefile -@@ -8,6 +8,7 @@ powervr-y := \ - pvr_device.o \ - pvr_device_info.o \ - pvr_drv.o \ -+ pvr_dump.o \ - pvr_free_list.o \ - pvr_fw.o \ - pvr_fw_meta.o \ -diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c -index da281b5c7055..8e8e7c1e0b03 100644 ---- a/drivers/gpu/drm/imagination/pvr_ccb.c -+++ b/drivers/gpu/drm/imagination/pvr_ccb.c -@@ -4,6 +4,7 @@ - #include "pvr_ccb.h" - #include "pvr_device.h" - #include "pvr_drv.h" -+#include "pvr_dump.h" - #include "pvr_free_list.h" - #include "pvr_fw.h" - #include "pvr_gem.h" -@@ -164,6 +165,10 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c - * suppress the "unknown" warning when receiving this command. - */ - break; -+ case ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_NOTIFICATION: -+ pvr_dump_context_reset_notification(pvr_dev, -+ &cmd->cmd_data.cmd_context_reset_notification); -+ break; - - default: - drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n", -diff --git a/drivers/gpu/drm/imagination/pvr_dump.c b/drivers/gpu/drm/imagination/pvr_dump.c -new file mode 100644 -index 000000000000..52e95fce2817 ---- /dev/null -+++ b/drivers/gpu/drm/imagination/pvr_dump.c -@@ -0,0 +1,113 @@ -+// SPDX-License-Identifier: GPL-2.0 OR MIT -+/* Copyright (c) 2026 Imagination Technologies Ltd. */ -+ -+#include "pvr_device.h" -+#include "pvr_dump.h" -+#include "pvr_rogue_fwif.h" -+ -+#include -+#include -+ -+static const char * -+get_reset_reason_desc(enum rogue_context_reset_reason reason) -+{ -+ switch (reason) { -+ case ROGUE_CONTEXT_RESET_REASON_NONE: -+ return "None"; -+ case ROGUE_CONTEXT_RESET_REASON_GUILTY_LOCKUP: -+ return "Guilty lockup"; -+ case ROGUE_CONTEXT_RESET_REASON_INNOCENT_LOCKUP: -+ return "Innocent lockup"; -+ case ROGUE_CONTEXT_RESET_REASON_GUILTY_OVERRUNING: -+ return "Guilty overrunning"; -+ case ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING: -+ return "Innocent overrunning"; -+ case ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH: -+ return "Hard context switch"; -+ case ROGUE_CONTEXT_RESET_REASON_WGP_CHECKSUM: -+ return "CDM Mission/safety checksum mismatch"; -+ case ROGUE_CONTEXT_RESET_REASON_TRP_CHECKSUM: -+ return "TRP checksum mismatch"; -+ case ROGUE_CONTEXT_RESET_REASON_GPU_ECC_OK: -+ return "GPU ECC error (corrected, OK)"; -+ case ROGUE_CONTEXT_RESET_REASON_GPU_ECC_HWR: -+ return "GPU ECC error (uncorrected, HWR)"; -+ case ROGUE_CONTEXT_RESET_REASON_FW_ECC_OK: -+ return "Firmware ECC error (corrected, OK)"; -+ case ROGUE_CONTEXT_RESET_REASON_FW_ECC_ERR: -+ return "Firmware ECC error (uncorrected, ERR)"; -+ case ROGUE_CONTEXT_RESET_REASON_FW_WATCHDOG: -+ return "Firmware watchdog"; -+ case ROGUE_CONTEXT_RESET_REASON_FW_PAGEFAULT: -+ return "Firmware pagefault"; -+ case ROGUE_CONTEXT_RESET_REASON_FW_EXEC_ERR: -+ return "Firmware execution error"; -+ case ROGUE_CONTEXT_RESET_REASON_HOST_WDG_FW_ERR: -+ return "Host watchdog"; -+ case ROGUE_CONTEXT_GEOM_OOM_DISABLED: -+ return "Geometry OOM disabled"; -+ -+ default: -+ return "Unknown"; -+ } -+} -+ -+static const char * -+get_dm_name(u32 dm) -+{ -+ switch (dm) { -+ case PVR_FWIF_DM_GP: -+ return "General purpose"; -+ /* PVR_FWIF_DM_TDM has the same index, but is discriminated by a device feature */ -+ case PVR_FWIF_DM_2D: -+ return "2D or TDM"; -+ case PVR_FWIF_DM_GEOM: -+ return "Geometry"; -+ case PVR_FWIF_DM_FRAG: -+ return "Fragment"; -+ case PVR_FWIF_DM_CDM: -+ return "Compute"; -+ case PVR_FWIF_DM_RAY: -+ return "Raytracing"; -+ case PVR_FWIF_DM_GEOM2: -+ return "Geometry 2"; -+ case PVR_FWIF_DM_GEOM3: -+ return "Geometry 3"; -+ case PVR_FWIF_DM_GEOM4: -+ return "Geometry 4"; -+ -+ default: -+ return "Unknown"; -+ } -+} -+ -+/** -+ * pvr_dump_context_reset_notification() - Handle context reset notification from FW -+ * @pvr_dev: Device pointer. -+ * @data: Data provided by FW. -+ * -+ * This will decode the data structure provided by FW and print the results via drm_info(). -+ */ -+void -+pvr_dump_context_reset_notification(struct pvr_device *pvr_dev, -+ struct rogue_fwif_fwccb_cmd_context_reset_data *data) -+{ -+ struct drm_device *drm_dev = from_pvr_device(pvr_dev); -+ -+ if (data->flags & ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_FLAG_ALL_CTXS) { -+ drm_info(drm_dev, "Received context reset notification for all contexts\n"); -+ } else { -+ drm_info(drm_dev, "Received context reset notification on context %u\n", -+ data->server_common_context_id); -+ } -+ -+ drm_info(drm_dev, " Reset reason=%u (%s)\n", data->reset_reason, -+ get_reset_reason_desc((enum rogue_context_reset_reason)data->reset_reason)); -+ drm_info(drm_dev, " Data Master=%u (%s)\n", data->dm, get_dm_name(data->dm)); -+ drm_info(drm_dev, " Job ref=%u\n", data->reset_job_ref); -+ -+ if (data->flags & ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_FLAG_PF) { -+ drm_info(drm_dev, " Page fault occurred, fault address=%llx\n", -+ data->fault_address); -+ } -+} -diff --git a/drivers/gpu/drm/imagination/pvr_dump.h b/drivers/gpu/drm/imagination/pvr_dump.h -new file mode 100644 -index 000000000000..3c0728c05596 ---- /dev/null -+++ b/drivers/gpu/drm/imagination/pvr_dump.h -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -+/* Copyright (c) 2026 Imagination Technologies Ltd. */ -+ -+#ifndef PVR_DUMP_H -+#define PVR_DUMP_H -+ -+/* Forward declaration from pvr_device.h. */ -+struct pvr_device; -+ -+/* Forward declaration from pvr_rogue_fwif.h. */ -+struct rogue_fwif_fwccb_cmd_context_reset_data; -+ -+void -+pvr_dump_context_reset_notification(struct pvr_device *pvr_dev, -+ struct rogue_fwif_fwccb_cmd_context_reset_data *data); -+ -+#endif /* PVR_DUMP_H */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch b/SPECS/linux-lts/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch new file mode 100644 index 0000000000..f6b7875e3a --- /dev/null +++ b/SPECS/linux-lts/0191-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch @@ -0,0 +1,2082 @@ +From 6b2f35b64e7c0486c46921e2bae819b08dc83a72 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:17 +0800 +Subject: [RUYI PATCH] UPSTREAM: drm: verisilicon: add a driver for Verisilicon + display controllers + +This is a from-scratch driver targeting Verisilicon DC-series display +controllers, which feature self-identification functionality like their +GC-series GPUs. + +Only DC8200 is being supported now, and only the main framebuffer is set +up (as the DRM primary plane). Support for more DC models and more +features is my further targets. + +As the display controller is delivered to SoC vendors as a whole part, +this driver does not use component framework and extra bridges inside a +SoC is expected to be implemented as dedicated bridges (this driver +properly supports bridge chaining). + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Tested-by: Han Gao +Tested-by: Michal Wilczynski +Reviewed-by: Thomas Zimmermann +Signed-off-by: Thomas Zimmermann +Link: https://patch.msgid.link/20260129023922.1527729-4-zhengxingda@iscas.ac.cn +(cherry picked from commit dbf21777caa8b8c88c12f7f036b01208fec0d55a) +Signed-off-by: Han Gao +--- + MAINTAINERS | 7 + + drivers/gpu/drm/Kconfig | 2 + + drivers/gpu/drm/Makefile | 1 + + drivers/gpu/drm/verisilicon/Kconfig | 16 + + drivers/gpu/drm/verisilicon/Makefile | 5 + + drivers/gpu/drm/verisilicon/vs_bridge.c | 371 ++++++++++++++++++ + drivers/gpu/drm/verisilicon/vs_bridge.h | 39 ++ + drivers/gpu/drm/verisilicon/vs_bridge_regs.h | 54 +++ + drivers/gpu/drm/verisilicon/vs_crtc.c | 191 +++++++++ + drivers/gpu/drm/verisilicon/vs_crtc.h | 31 ++ + drivers/gpu/drm/verisilicon/vs_crtc_regs.h | 60 +++ + drivers/gpu/drm/verisilicon/vs_dc.c | 207 ++++++++++ + drivers/gpu/drm/verisilicon/vs_dc.h | 38 ++ + drivers/gpu/drm/verisilicon/vs_dc_top_regs.h | 27 ++ + drivers/gpu/drm/verisilicon/vs_drm.c | 182 +++++++++ + drivers/gpu/drm/verisilicon/vs_drm.h | 28 ++ + drivers/gpu/drm/verisilicon/vs_hwdb.c | 150 +++++++ + drivers/gpu/drm/verisilicon/vs_hwdb.h | 29 ++ + drivers/gpu/drm/verisilicon/vs_plane.c | 124 ++++++ + drivers/gpu/drm/verisilicon/vs_plane.h | 72 ++++ + .../gpu/drm/verisilicon/vs_primary_plane.c | 173 ++++++++ + .../drm/verisilicon/vs_primary_plane_regs.h | 53 +++ + 22 files changed, 1860 insertions(+) + create mode 100644 drivers/gpu/drm/verisilicon/Kconfig + create mode 100644 drivers/gpu/drm/verisilicon/Makefile + create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge_regs.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc_regs.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_dc.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_dc.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_top_regs.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_drm.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_drm.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_hwdb.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_hwdb.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_primary_plane.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h + +diff --git a/MAINTAINERS b/MAINTAINERS +index a615f46a6e8d..b50b6c7a9b52 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -8546,6 +8546,13 @@ F: Documentation/devicetree/bindings/display/brcm,bcm2835-*.yaml + F: drivers/gpu/drm/vc4/ + F: include/uapi/drm/vc4_drm.h + ++DRM DRIVERS FOR VERISILICON DISPLAY CONTROLLER IP ++M: Icenowy Zheng ++L: dri-devel@lists.freedesktop.org ++S: Maintained ++F: Documentation/devicetree/bindings/display/verisilicon,dc.yaml ++F: drivers/gpu/drm/verisilicon/ ++ + DRM DRIVERS FOR VIVANTE GPU IP + M: Lucas Stach + R: Russell King +diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig +index ed85d0ceee3b..a0917595d11c 100644 +--- a/drivers/gpu/drm/Kconfig ++++ b/drivers/gpu/drm/Kconfig +@@ -398,6 +398,8 @@ source "drivers/gpu/drm/imagination/Kconfig" + + source "drivers/gpu/drm/tyr/Kconfig" + ++source "drivers/gpu/drm/verisilicon/Kconfig" ++ + config DRM_HYPERV + tristate "DRM Support for Hyper-V synthetic video device" + depends on DRM && PCI && HYPERV_VMBUS +diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile +index b248e64587ed..90eb61d3a823 100644 +--- a/drivers/gpu/drm/Makefile ++++ b/drivers/gpu/drm/Makefile +@@ -235,6 +235,7 @@ obj-y += solomon/ + obj-$(CONFIG_DRM_SPRD) += sprd/ + obj-$(CONFIG_DRM_LOONGSON) += loongson/ + obj-$(CONFIG_DRM_POWERVR) += imagination/ ++obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon/ + + # Ensure drm headers are self-contained and pass kernel-doc + hdrtest-files := \ +diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisilicon/Kconfig +new file mode 100644 +index 000000000000..7cce86ec8603 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/Kconfig +@@ -0,0 +1,16 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++config DRM_VERISILICON_DC ++ tristate "DRM Support for Verisilicon DC-series display controllers" ++ depends on DRM && COMMON_CLK ++ depends on RISCV || COMPILE_TEST ++ select DRM_BRIDGE_CONNECTOR ++ select DRM_CLIENT_SELECTION ++ select DRM_DISPLAY_HELPER ++ select DRM_GEM_DMA_HELPER ++ select DRM_KMS_HELPER ++ select REGMAP_MMIO ++ select VIDEOMODE_HELPERS ++ help ++ Choose this option if you have a SoC with Verisilicon DC-series ++ display controllers. If M is selected, the module will be called ++ verisilicon-dc. +diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile +new file mode 100644 +index 000000000000..fd8d805fbcde +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/Makefile +@@ -0,0 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o ++ ++obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o +diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.c b/drivers/gpu/drm/verisilicon/vs_bridge.c +new file mode 100644 +index 000000000000..2a0ad00a94d6 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_bridge.c +@@ -0,0 +1,371 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_bridge.h" ++#include "vs_bridge_regs.h" ++#include "vs_crtc.h" ++#include "vs_dc.h" ++ ++static int vs_bridge_attach(struct drm_bridge *bridge, ++ struct drm_encoder *encoder, ++ enum drm_bridge_attach_flags flags) ++{ ++ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); ++ ++ return drm_bridge_attach(encoder, vbridge->next_bridge, ++ bridge, flags); ++} ++ ++struct vsdc_dp_format { ++ u32 linux_fmt; ++ bool is_yuv; ++ u32 vsdc_fmt; ++}; ++ ++static struct vsdc_dp_format vsdc_dp_supported_fmts[] = { ++ /* default to RGB888 */ ++ { MEDIA_BUS_FMT_FIXED, false, VSDC_DISP_DP_CONFIG_FMT_RGB888 }, ++ { MEDIA_BUS_FMT_RGB888_1X24, false, VSDC_DISP_DP_CONFIG_FMT_RGB888 }, ++ { MEDIA_BUS_FMT_RGB565_1X16, false, VSDC_DISP_DP_CONFIG_FMT_RGB565 }, ++ { MEDIA_BUS_FMT_RGB666_1X18, false, VSDC_DISP_DP_CONFIG_FMT_RGB666 }, ++ { MEDIA_BUS_FMT_RGB101010_1X30, ++ false, VSDC_DISP_DP_CONFIG_FMT_RGB101010 }, ++ { MEDIA_BUS_FMT_UYVY8_1X16, true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY8 }, ++ { MEDIA_BUS_FMT_UYVY10_1X20, true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY10 }, ++ { MEDIA_BUS_FMT_YUV8_1X24, true, VSDC_DISP_DP_CONFIG_YUV_FMT_YUV8 }, ++ { MEDIA_BUS_FMT_YUV10_1X30, true, VSDC_DISP_DP_CONFIG_YUV_FMT_YUV10 }, ++ { MEDIA_BUS_FMT_UYYVYY8_0_5X24, ++ true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY8 }, ++ { MEDIA_BUS_FMT_UYYVYY10_0_5X30, ++ true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY10 }, ++}; ++ ++static u32 *vs_bridge_atomic_get_output_bus_fmts_dpi(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state, ++ unsigned int *num_output_fmts) ++{ ++ u32 *output_fmts; ++ ++ *num_output_fmts = 2; ++ ++ output_fmts = kcalloc(*num_output_fmts, sizeof(*output_fmts), ++ GFP_KERNEL); ++ if (!output_fmts) ++ return NULL; ++ ++ /* TODO: support more DPI output formats */ ++ output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; ++ output_fmts[1] = MEDIA_BUS_FMT_FIXED; ++ ++ return output_fmts; ++} ++ ++static u32 *vs_bridge_atomic_get_output_bus_fmts_dp(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state, ++ unsigned int *num_output_fmts) ++{ ++ u32 *output_fmts; ++ unsigned int i; ++ ++ *num_output_fmts = ARRAY_SIZE(vsdc_dp_supported_fmts); ++ ++ output_fmts = kcalloc(*num_output_fmts, sizeof(*output_fmts), ++ GFP_KERNEL); ++ if (!output_fmts) ++ return NULL; ++ ++ for (i = 0; i < *num_output_fmts; i++) ++ output_fmts[i] = vsdc_dp_supported_fmts[i].linux_fmt; ++ ++ return output_fmts; ++} ++ ++static bool vs_bridge_out_dp_fmt_supported(u32 out_fmt) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(vsdc_dp_supported_fmts); i++) ++ if (vsdc_dp_supported_fmts[i].linux_fmt == out_fmt) ++ return true; ++ ++ return false; ++} ++ ++static u32 *vs_bridge_atomic_get_input_bus_fmts_dp(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state, ++ u32 output_fmt, ++ unsigned int *num_input_fmts) ++{ ++ if (!vs_bridge_out_dp_fmt_supported(output_fmt)) { ++ *num_input_fmts = 0; ++ return NULL; ++ } ++ ++ return drm_atomic_helper_bridge_propagate_bus_fmt(bridge, bridge_state, ++ crtc_state, ++ conn_state, ++ output_fmt, ++ num_input_fmts); ++} ++ ++static int vs_bridge_atomic_check_dp(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state) ++{ ++ if (!vs_bridge_out_dp_fmt_supported(bridge_state->output_bus_cfg.format)) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static void vs_bridge_enable_common(struct vs_crtc *crtc, ++ struct drm_bridge_state *br_state) ++{ ++ struct vs_dc *dc = crtc->dc; ++ unsigned int output = crtc->id; ++ ++ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_DAT_POL); ++ regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_DE_POL, ++ br_state->output_bus_cfg.flags & ++ DRM_BUS_FLAG_DE_LOW); ++ regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_CLK_POL, ++ br_state->output_bus_cfg.flags & ++ DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); ++ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_DE_EN | ++ VSDC_DISP_PANEL_CONFIG_DAT_EN | ++ VSDC_DISP_PANEL_CONFIG_CLK_EN); ++ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_RUNNING); ++ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, ++ VSDC_DISP_PANEL_START_MULTI_DISP_SYNC); ++ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START, ++ VSDC_DISP_PANEL_START_RUNNING(output)); ++ ++ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), ++ VSDC_DISP_PANEL_CONFIG_EX_COMMIT); ++} ++ ++static void vs_bridge_atomic_enable_dpi(struct drm_bridge *bridge, ++ struct drm_atomic_state *state) ++{ ++ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); ++ struct drm_bridge_state *br_state = ++ drm_atomic_get_new_bridge_state(state, bridge); ++ struct vs_crtc *crtc = vbridge->crtc; ++ struct vs_dc *dc = crtc->dc; ++ unsigned int output = crtc->id; ++ ++ regmap_clear_bits(dc->regs, VSDC_DISP_DP_CONFIG(output), ++ VSDC_DISP_DP_CONFIG_DP_EN); ++ regmap_write(dc->regs, VSDC_DISP_DPI_CONFIG(output), ++ VSDC_DISP_DPI_CONFIG_FMT_RGB888); ++ ++ vs_bridge_enable_common(crtc, br_state); ++} ++ ++static void vs_bridge_atomic_enable_dp(struct drm_bridge *bridge, ++ struct drm_atomic_state *state) ++{ ++ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); ++ struct drm_bridge_state *br_state = ++ drm_atomic_get_new_bridge_state(state, bridge); ++ struct vs_crtc *crtc = vbridge->crtc; ++ struct vs_dc *dc = crtc->dc; ++ unsigned int output = crtc->id; ++ u32 dp_fmt; ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(vsdc_dp_supported_fmts); i++) { ++ if (vsdc_dp_supported_fmts[i].linux_fmt == ++ br_state->output_bus_cfg.format) ++ break; ++ } ++ if (WARN_ON_ONCE(i == ARRAY_SIZE(vsdc_dp_supported_fmts))) ++ return; ++ dp_fmt = vsdc_dp_supported_fmts[i].vsdc_fmt; ++ dp_fmt |= VSDC_DISP_DP_CONFIG_DP_EN; ++ regmap_write(dc->regs, VSDC_DISP_DP_CONFIG(output), dp_fmt); ++ regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_YUV, ++ vsdc_dp_supported_fmts[i].is_yuv); ++ ++ vs_bridge_enable_common(crtc, br_state); ++} ++ ++static void vs_bridge_atomic_disable(struct drm_bridge *bridge, ++ struct drm_atomic_state *state) ++{ ++ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); ++ struct vs_crtc *crtc = vbridge->crtc; ++ struct vs_dc *dc = crtc->dc; ++ unsigned int output = crtc->id; ++ ++ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, ++ VSDC_DISP_PANEL_START_MULTI_DISP_SYNC | ++ VSDC_DISP_PANEL_START_RUNNING(output)); ++ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), ++ VSDC_DISP_PANEL_CONFIG_RUNNING); ++ ++ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), ++ VSDC_DISP_PANEL_CONFIG_EX_COMMIT); ++} ++ ++static const struct drm_bridge_funcs vs_dpi_bridge_funcs = { ++ .attach = vs_bridge_attach, ++ .atomic_enable = vs_bridge_atomic_enable_dpi, ++ .atomic_disable = vs_bridge_atomic_disable, ++ .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt, ++ .atomic_get_output_bus_fmts = vs_bridge_atomic_get_output_bus_fmts_dpi, ++ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, ++ .atomic_reset = drm_atomic_helper_bridge_reset, ++}; ++ ++static const struct drm_bridge_funcs vs_dp_bridge_funcs = { ++ .attach = vs_bridge_attach, ++ .atomic_enable = vs_bridge_atomic_enable_dp, ++ .atomic_disable = vs_bridge_atomic_disable, ++ .atomic_check = vs_bridge_atomic_check_dp, ++ .atomic_get_input_bus_fmts = vs_bridge_atomic_get_input_bus_fmts_dp, ++ .atomic_get_output_bus_fmts = vs_bridge_atomic_get_output_bus_fmts_dp, ++ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, ++ .atomic_reset = drm_atomic_helper_bridge_reset, ++}; ++ ++static int vs_bridge_detect_output_interface(struct device_node *of_node, ++ unsigned int output) ++{ ++ int ret; ++ struct device_node *remote; ++ ++ remote = of_graph_get_remote_node(of_node, output, ++ VSDC_OUTPUT_INTERFACE_DPI); ++ if (remote) { ++ ret = VSDC_OUTPUT_INTERFACE_DPI; ++ } else { ++ remote = of_graph_get_remote_node(of_node, output, ++ VSDC_OUTPUT_INTERFACE_DP); ++ if (remote) ++ ret = VSDC_OUTPUT_INTERFACE_DP; ++ else ++ ret = -ENODEV; ++ } ++ ++ if (remote) ++ of_node_put(remote); ++ ++ return ret; ++} ++ ++struct vs_bridge *vs_bridge_init(struct drm_device *drm_dev, ++ struct vs_crtc *crtc) ++{ ++ unsigned int output = crtc->id; ++ struct vs_bridge *bridge; ++ struct drm_bridge *next; ++ enum vs_bridge_output_interface intf; ++ const struct drm_bridge_funcs *bridge_funcs; ++ int ret, enctype; ++ ++ intf = vs_bridge_detect_output_interface(drm_dev->dev->of_node, ++ output); ++ if (intf == -ENODEV) { ++ drm_dbg(drm_dev, "Skipping output %u\n", output); ++ return NULL; ++ } ++ ++ next = devm_drm_of_get_bridge(drm_dev->dev, drm_dev->dev->of_node, ++ output, intf); ++ if (IS_ERR(next)) { ++ ret = PTR_ERR(next); ++ if (ret != -EPROBE_DEFER) ++ drm_err(drm_dev, ++ "Cannot get downstream bridge of output %u\n", ++ output); ++ return ERR_PTR(ret); ++ } ++ ++ if (intf == VSDC_OUTPUT_INTERFACE_DPI) ++ bridge_funcs = &vs_dpi_bridge_funcs; ++ else ++ bridge_funcs = &vs_dp_bridge_funcs; ++ ++ bridge = devm_drm_bridge_alloc(drm_dev->dev, struct vs_bridge, base, ++ bridge_funcs); ++ if (IS_ERR(bridge)) ++ return ERR_PTR(PTR_ERR(bridge)); ++ ++ bridge->crtc = crtc; ++ bridge->intf = intf; ++ bridge->next_bridge = next; ++ ++ if (intf == VSDC_OUTPUT_INTERFACE_DPI) ++ enctype = DRM_MODE_ENCODER_DPI; ++ else ++ enctype = DRM_MODE_ENCODER_NONE; ++ ++ bridge->enc = drmm_plain_encoder_alloc(drm_dev, NULL, enctype, NULL); ++ if (IS_ERR(bridge->enc)) { ++ drm_err(drm_dev, ++ "Cannot initialize encoder for output %u\n", output); ++ ret = PTR_ERR(bridge->enc); ++ return ERR_PTR(ret); ++ } ++ ++ bridge->enc->possible_crtcs = drm_crtc_mask(&crtc->base); ++ ++ ret = devm_drm_bridge_add(drm_dev->dev, &bridge->base); ++ if (ret) { ++ drm_err(drm_dev, ++ "Cannot add bridge for output %u\n", output); ++ return ERR_PTR(ret); ++ } ++ ++ ret = drm_bridge_attach(bridge->enc, &bridge->base, NULL, ++ DRM_BRIDGE_ATTACH_NO_CONNECTOR); ++ if (ret) { ++ drm_err(drm_dev, ++ "Cannot attach bridge for output %u\n", output); ++ return ERR_PTR(ret); ++ } ++ ++ bridge->conn = drm_bridge_connector_init(drm_dev, bridge->enc); ++ if (IS_ERR(bridge->conn)) { ++ drm_err(drm_dev, ++ "Cannot create connector for output %u\n", output); ++ ret = PTR_ERR(bridge->conn); ++ return ERR_PTR(ret); ++ } ++ drm_connector_attach_encoder(bridge->conn, bridge->enc); ++ ++ return bridge; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.h b/drivers/gpu/drm/verisilicon/vs_bridge.h +new file mode 100644 +index 000000000000..70fee1749699 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_bridge.h +@@ -0,0 +1,39 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#ifndef _VS_BRIDGE_H_ ++#define _VS_BRIDGE_H_ ++ ++#include ++ ++#include ++#include ++#include ++ ++struct vs_crtc; ++ ++enum vs_bridge_output_interface { ++ VSDC_OUTPUT_INTERFACE_DPI = 0, ++ VSDC_OUTPUT_INTERFACE_DP = 1 ++}; ++ ++struct vs_bridge { ++ struct drm_bridge base; ++ struct drm_encoder *enc; ++ struct drm_connector *conn; ++ ++ struct vs_crtc *crtc; ++ struct drm_bridge *next_bridge; ++ enum vs_bridge_output_interface intf; ++}; ++ ++static inline struct vs_bridge *drm_bridge_to_vs_bridge(struct drm_bridge *bridge) ++{ ++ return container_of(bridge, struct vs_bridge, base); ++} ++ ++struct vs_bridge *vs_bridge_init(struct drm_device *drm_dev, ++ struct vs_crtc *crtc); ++#endif /* _VS_BRIDGE_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_bridge_regs.h b/drivers/gpu/drm/verisilicon/vs_bridge_regs.h +new file mode 100644 +index 000000000000..9eb30e4564be +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_bridge_regs.h +@@ -0,0 +1,54 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_BRIDGE_REGS_H_ ++#define _VS_BRIDGE_REGS_H_ ++ ++#include ++ ++#define VSDC_DISP_PANEL_CONFIG(n) (0x1418 + 0x4 * (n)) ++#define VSDC_DISP_PANEL_CONFIG_DE_EN BIT(0) ++#define VSDC_DISP_PANEL_CONFIG_DE_POL BIT(1) ++#define VSDC_DISP_PANEL_CONFIG_DAT_EN BIT(4) ++#define VSDC_DISP_PANEL_CONFIG_DAT_POL BIT(5) ++#define VSDC_DISP_PANEL_CONFIG_CLK_EN BIT(8) ++#define VSDC_DISP_PANEL_CONFIG_CLK_POL BIT(9) ++#define VSDC_DISP_PANEL_CONFIG_RUNNING BIT(12) ++#define VSDC_DISP_PANEL_CONFIG_GAMMA BIT(13) ++#define VSDC_DISP_PANEL_CONFIG_YUV BIT(16) ++ ++#define VSDC_DISP_DPI_CONFIG(n) (0x14B8 + 0x4 * (n)) ++#define VSDC_DISP_DPI_CONFIG_FMT_MASK GENMASK(2, 0) ++#define VSDC_DISP_DPI_CONFIG_FMT_RGB565 (0) ++#define VSDC_DISP_DPI_CONFIG_FMT_RGB666 (3) ++#define VSDC_DISP_DPI_CONFIG_FMT_RGB888 (5) ++#define VSDC_DISP_DPI_CONFIG_FMT_RGB101010 (6) ++ ++#define VSDC_DISP_PANEL_START 0x1CCC ++#define VSDC_DISP_PANEL_START_RUNNING(n) BIT(n) ++#define VSDC_DISP_PANEL_START_MULTI_DISP_SYNC BIT(3) ++ ++#define VSDC_DISP_DP_CONFIG(n) (0x1CD0 + 0x4 * (n)) ++#define VSDC_DISP_DP_CONFIG_DP_EN BIT(3) ++#define VSDC_DISP_DP_CONFIG_FMT_MASK GENMASK(2, 0) ++#define VSDC_DISP_DP_CONFIG_FMT_RGB565 (0) ++#define VSDC_DISP_DP_CONFIG_FMT_RGB666 (1) ++#define VSDC_DISP_DP_CONFIG_FMT_RGB888 (2) ++#define VSDC_DISP_DP_CONFIG_FMT_RGB101010 (3) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_MASK GENMASK(7, 4) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY8 (2 << 4) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_YUV8 (4 << 4) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY10 (8 << 4) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_YUV10 (10 << 4) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY8 (12 << 4) ++#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY10 (13 << 4) ++ ++#define VSDC_DISP_PANEL_CONFIG_EX(n) (0x2518 + 0x4 * (n)) ++#define VSDC_DISP_PANEL_CONFIG_EX_COMMIT BIT(0) ++ ++#endif /* _VS_BRIDGE_REGS_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisilicon/vs_crtc.c +new file mode 100644 +index 000000000000..f49401713000 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_crtc.c +@@ -0,0 +1,191 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_crtc_regs.h" ++#include "vs_crtc.h" ++#include "vs_dc.h" ++#include "vs_dc_top_regs.h" ++#include "vs_drm.h" ++#include "vs_plane.h" ++ ++static void vs_crtc_atomic_disable(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ unsigned int output = vcrtc->id; ++ ++ drm_crtc_vblank_off(crtc); ++ ++ clk_disable_unprepare(dc->pix_clk[output]); ++} ++ ++static void vs_crtc_atomic_enable(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ unsigned int output = vcrtc->id; ++ ++ drm_WARN_ON(&dc->drm_dev->base, ++ clk_prepare_enable(dc->pix_clk[output])); ++ ++ drm_crtc_vblank_on(crtc); ++} ++ ++static void vs_crtc_mode_set_nofb(struct drm_crtc *crtc) ++{ ++ struct drm_display_mode *mode = &crtc->state->adjusted_mode; ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ unsigned int output = vcrtc->id; ++ ++ regmap_write(dc->regs, VSDC_DISP_HSIZE(output), ++ VSDC_DISP_HSIZE_DISP(mode->hdisplay) | ++ VSDC_DISP_HSIZE_TOTAL(mode->htotal)); ++ regmap_write(dc->regs, VSDC_DISP_VSIZE(output), ++ VSDC_DISP_VSIZE_DISP(mode->vdisplay) | ++ VSDC_DISP_VSIZE_TOTAL(mode->vtotal)); ++ regmap_write(dc->regs, VSDC_DISP_HSYNC(output), ++ VSDC_DISP_HSYNC_START(mode->hsync_start) | ++ VSDC_DISP_HSYNC_END(mode->hsync_end) | ++ VSDC_DISP_HSYNC_EN); ++ if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) ++ regmap_set_bits(dc->regs, VSDC_DISP_HSYNC(output), ++ VSDC_DISP_HSYNC_POL); ++ regmap_write(dc->regs, VSDC_DISP_VSYNC(output), ++ VSDC_DISP_VSYNC_START(mode->vsync_start) | ++ VSDC_DISP_VSYNC_END(mode->vsync_end) | ++ VSDC_DISP_VSYNC_EN); ++ if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) ++ regmap_set_bits(dc->regs, VSDC_DISP_VSYNC(output), ++ VSDC_DISP_VSYNC_POL); ++ ++ WARN_ON(clk_set_rate(dc->pix_clk[output], mode->crtc_clock * 1000)); ++} ++ ++static enum drm_mode_status ++vs_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) ++{ ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ unsigned int output = vcrtc->id; ++ long rate; ++ ++ if (mode->htotal > VSDC_DISP_TIMING_VALUE_MAX) ++ return MODE_BAD_HVALUE; ++ if (mode->vtotal > VSDC_DISP_TIMING_VALUE_MAX) ++ return MODE_BAD_VVALUE; ++ ++ rate = clk_round_rate(dc->pix_clk[output], mode->clock * HZ_PER_KHZ); ++ if (rate <= 0) ++ return MODE_CLOCK_RANGE; ++ ++ return MODE_OK; ++} ++ ++static bool vs_crtc_mode_fixup(struct drm_crtc *crtc, ++ const struct drm_display_mode *m, ++ struct drm_display_mode *adjusted_mode) ++{ ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ unsigned int output = vcrtc->id; ++ long clk_rate; ++ ++ drm_mode_set_crtcinfo(adjusted_mode, 0); ++ ++ /* Feedback the pixel clock to crtc_clock */ ++ clk_rate = adjusted_mode->crtc_clock * HZ_PER_KHZ; ++ clk_rate = clk_round_rate(dc->pix_clk[output], clk_rate); ++ if (clk_rate <= 0) ++ return false; ++ ++ adjusted_mode->crtc_clock = clk_rate / HZ_PER_KHZ; ++ ++ return true; ++} ++ ++static const struct drm_crtc_helper_funcs vs_crtc_helper_funcs = { ++ .atomic_flush = drm_crtc_vblank_atomic_flush, ++ .atomic_enable = vs_crtc_atomic_enable, ++ .atomic_disable = vs_crtc_atomic_disable, ++ .mode_set_nofb = vs_crtc_mode_set_nofb, ++ .mode_valid = vs_crtc_mode_valid, ++ .mode_fixup = vs_crtc_mode_fixup, ++}; ++ ++static int vs_crtc_enable_vblank(struct drm_crtc *crtc) ++{ ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id)); ++ ++ return 0; ++} ++ ++static void vs_crtc_disable_vblank(struct drm_crtc *crtc) ++{ ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_clear_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id)); ++} ++ ++static const struct drm_crtc_funcs vs_crtc_funcs = { ++ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, ++ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, ++ .page_flip = drm_atomic_helper_page_flip, ++ .reset = drm_atomic_helper_crtc_reset, ++ .set_config = drm_atomic_helper_set_config, ++ .enable_vblank = vs_crtc_enable_vblank, ++ .disable_vblank = vs_crtc_disable_vblank, ++}; ++ ++struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, ++ unsigned int output) ++{ ++ struct vs_crtc *vcrtc; ++ struct drm_plane *primary; ++ int ret; ++ ++ vcrtc = drmm_kzalloc(drm_dev, sizeof(*vcrtc), GFP_KERNEL); ++ if (!vcrtc) ++ return ERR_PTR(-ENOMEM); ++ vcrtc->dc = dc; ++ vcrtc->id = output; ++ ++ /* Create our primary plane */ ++ primary = vs_primary_plane_init(drm_dev, dc); ++ if (IS_ERR(primary)) { ++ drm_err(drm_dev, "Couldn't create the primary plane\n"); ++ return ERR_PTR(PTR_ERR(primary)); ++ } ++ ++ ret = drmm_crtc_init_with_planes(drm_dev, &vcrtc->base, ++ primary, ++ NULL, ++ &vs_crtc_funcs, ++ NULL); ++ if (ret) { ++ drm_err(drm_dev, "Couldn't initialize CRTC\n"); ++ return ERR_PTR(ret); ++ } ++ ++ drm_crtc_helper_add(&vcrtc->base, &vs_crtc_helper_funcs); ++ ++ return vcrtc; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.h b/drivers/gpu/drm/verisilicon/vs_crtc.h +new file mode 100644 +index 000000000000..b45580bd99b3 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_crtc.h +@@ -0,0 +1,31 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#ifndef _VS_CRTC_H_ ++#define _VS_CRTC_H_ ++ ++#include ++#include ++ ++#define VSDC_DISP_TIMING_VALUE_MAX BIT_MASK(15) ++ ++struct vs_dc; ++ ++struct vs_crtc { ++ struct drm_crtc base; ++ ++ struct vs_dc *dc; ++ unsigned int id; ++}; ++ ++static inline struct vs_crtc *drm_crtc_to_vs_crtc(struct drm_crtc *crtc) ++{ ++ return container_of(crtc, struct vs_crtc, base); ++} ++ ++struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, ++ unsigned int output); ++ ++#endif /* _VS_CRTC_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h +new file mode 100644 +index 000000000000..c7930e817635 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h +@@ -0,0 +1,60 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_CRTC_REGS_H_ ++#define _VS_CRTC_REGS_H_ ++ ++#include ++ ++#define VSDC_DISP_DITHER_CONFIG(n) (0x1410 + 0x4 * (n)) ++ ++#define VSDC_DISP_DITHER_TABLE_LOW(n) (0x1420 + 0x4 * (n)) ++#define VSDC_DISP_DITHER_TABLE_LOW_DEFAULT 0x7B48F3C0 ++ ++#define VSDC_DISP_DITHER_TABLE_HIGH(n) (0x1428 + 0x4 * (n)) ++#define VSDC_DISP_DITHER_TABLE_HIGH_DEFAULT 0x596AD1E2 ++ ++#define VSDC_DISP_HSIZE(n) (0x1430 + 0x4 * (n)) ++#define VSDC_DISP_HSIZE_DISP_MASK GENMASK(14, 0) ++#define VSDC_DISP_HSIZE_DISP(v) ((v) << 0) ++#define VSDC_DISP_HSIZE_TOTAL_MASK GENMASK(30, 16) ++#define VSDC_DISP_HSIZE_TOTAL(v) ((v) << 16) ++ ++#define VSDC_DISP_HSYNC(n) (0x1438 + 0x4 * (n)) ++#define VSDC_DISP_HSYNC_START_MASK GENMASK(14, 0) ++#define VSDC_DISP_HSYNC_START(v) ((v) << 0) ++#define VSDC_DISP_HSYNC_END_MASK GENMASK(29, 15) ++#define VSDC_DISP_HSYNC_END(v) ((v) << 15) ++#define VSDC_DISP_HSYNC_EN BIT(30) ++#define VSDC_DISP_HSYNC_POL BIT(31) ++ ++#define VSDC_DISP_VSIZE(n) (0x1440 + 0x4 * (n)) ++#define VSDC_DISP_VSIZE_DISP_MASK GENMASK(14, 0) ++#define VSDC_DISP_VSIZE_DISP(v) ((v) << 0) ++#define VSDC_DISP_VSIZE_TOTAL_MASK GENMASK(30, 16) ++#define VSDC_DISP_VSIZE_TOTAL(v) ((v) << 16) ++ ++#define VSDC_DISP_VSYNC(n) (0x1448 + 0x4 * (n)) ++#define VSDC_DISP_VSYNC_START_MASK GENMASK(14, 0) ++#define VSDC_DISP_VSYNC_START(v) ((v) << 0) ++#define VSDC_DISP_VSYNC_END_MASK GENMASK(29, 15) ++#define VSDC_DISP_VSYNC_END(v) ((v) << 15) ++#define VSDC_DISP_VSYNC_EN BIT(30) ++#define VSDC_DISP_VSYNC_POL BIT(31) ++ ++#define VSDC_DISP_CURRENT_LOCATION(n) (0x1450 + 0x4 * (n)) ++ ++#define VSDC_DISP_GAMMA_INDEX(n) (0x1458 + 0x4 * (n)) ++ ++#define VSDC_DISP_GAMMA_DATA(n) (0x1460 + 0x4 * (n)) ++ ++#define VSDC_DISP_IRQ_STA 0x147C ++ ++#define VSDC_DISP_IRQ_EN 0x1480 ++ ++#endif /* _VS_CRTC_REGS_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c +new file mode 100644 +index 000000000000..ba1b3f261a3a +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_dc.c +@@ -0,0 +1,207 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "vs_crtc.h" ++#include "vs_dc.h" ++#include "vs_dc_top_regs.h" ++#include "vs_drm.h" ++#include "vs_hwdb.h" ++ ++static const struct regmap_config vs_dc_regmap_cfg = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = sizeof(u32), ++ /* VSDC_OVL_CONFIG_EX(1) */ ++ .max_register = 0x2544, ++}; ++ ++static const struct of_device_id vs_dc_driver_dt_match[] = { ++ { .compatible = "verisilicon,dc" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, vs_dc_driver_dt_match); ++ ++static irqreturn_t vs_dc_irq_handler(int irq, void *private) ++{ ++ struct vs_dc *dc = private; ++ u32 irqs; ++ ++ regmap_read(dc->regs, VSDC_TOP_IRQ_ACK, &irqs); ++ ++ vs_drm_handle_irq(dc, irqs); ++ ++ return IRQ_HANDLED; ++} ++ ++static int vs_dc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct vs_dc *dc; ++ void __iomem *regs; ++ unsigned int port_count, i; ++ /* pix0/pix1 */ ++ char pixclk_name[5]; ++ int irq, ret; ++ ++ if (!dev->of_node) { ++ dev_err(dev, "can't find DC devices\n"); ++ return -ENODEV; ++ } ++ ++ port_count = of_graph_get_port_count(dev->of_node); ++ if (!port_count) { ++ dev_err(dev, "can't find DC downstream ports\n"); ++ return -ENODEV; ++ } ++ if (port_count > VSDC_MAX_OUTPUTS) { ++ dev_err(dev, "too many DC downstream ports than possible\n"); ++ return -EINVAL; ++ } ++ ++ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(dev, "No suitable DMA available\n"); ++ return ret; ++ } ++ ++ dc = devm_kzalloc(dev, sizeof(*dc), GFP_KERNEL); ++ if (!dc) ++ return -ENOMEM; ++ ++ dc->rsts[0].id = "core"; ++ dc->rsts[1].id = "axi"; ++ dc->rsts[2].id = "ahb"; ++ ++ ret = devm_reset_control_bulk_get_optional_shared(dev, VSDC_RESET_COUNT, ++ dc->rsts); ++ if (ret) { ++ dev_err(dev, "can't get reset lines\n"); ++ return ret; ++ } ++ ++ dc->core_clk = devm_clk_get_enabled(dev, "core"); ++ if (IS_ERR(dc->core_clk)) { ++ dev_err(dev, "can't get core clock\n"); ++ return PTR_ERR(dc->core_clk); ++ } ++ ++ dc->axi_clk = devm_clk_get_enabled(dev, "axi"); ++ if (IS_ERR(dc->axi_clk)) { ++ dev_err(dev, "can't get axi clock\n"); ++ return PTR_ERR(dc->axi_clk); ++ } ++ ++ dc->ahb_clk = devm_clk_get_enabled(dev, "ahb"); ++ if (IS_ERR(dc->ahb_clk)) { ++ dev_err(dev, "can't get ahb clock\n"); ++ return PTR_ERR(dc->ahb_clk); ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(dev, "can't get irq\n"); ++ return irq; ++ } ++ ++ ret = reset_control_bulk_deassert(VSDC_RESET_COUNT, dc->rsts); ++ if (ret) { ++ dev_err(dev, "can't deassert reset lines\n"); ++ return ret; ++ } ++ ++ regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(regs)) { ++ dev_err(dev, "can't map registers"); ++ ret = PTR_ERR(regs); ++ goto err_rst_assert; ++ } ++ ++ dc->regs = devm_regmap_init_mmio(dev, regs, &vs_dc_regmap_cfg); ++ if (IS_ERR(dc->regs)) { ++ ret = PTR_ERR(dc->regs); ++ goto err_rst_assert; ++ } ++ ++ ret = vs_fill_chip_identity(dc->regs, &dc->identity); ++ if (ret) ++ goto err_rst_assert; ++ ++ dev_info(dev, "Found DC%x rev %x customer %x\n", dc->identity.model, ++ dc->identity.revision, dc->identity.customer_id); ++ ++ if (port_count > dc->identity.display_count) { ++ dev_err(dev, "too many downstream ports than HW capability\n"); ++ ret = -EINVAL; ++ goto err_rst_assert; ++ } ++ ++ for (i = 0; i < dc->identity.display_count; i++) { ++ snprintf(pixclk_name, sizeof(pixclk_name), "pix%u", i); ++ dc->pix_clk[i] = devm_clk_get(dev, pixclk_name); ++ if (IS_ERR(dc->pix_clk[i])) { ++ dev_err(dev, "can't get pixel clk %u\n", i); ++ ret = PTR_ERR(dc->pix_clk[i]); ++ goto err_rst_assert; ++ } ++ } ++ ++ ret = devm_request_irq(dev, irq, vs_dc_irq_handler, 0, ++ dev_name(dev), dc); ++ if (ret) { ++ dev_err(dev, "can't request irq\n"); ++ goto err_rst_assert; ++ } ++ ++ dev_set_drvdata(dev, dc); ++ ++ ret = vs_drm_initialize(dc, pdev); ++ if (ret) ++ goto err_rst_assert; ++ ++ return 0; ++ ++err_rst_assert: ++ reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); ++ return ret; ++} ++ ++static void vs_dc_remove(struct platform_device *pdev) ++{ ++ struct vs_dc *dc = dev_get_drvdata(&pdev->dev); ++ ++ vs_drm_finalize(dc); ++ ++ dev_set_drvdata(&pdev->dev, NULL); ++ ++ reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); ++} ++ ++static void vs_dc_shutdown(struct platform_device *pdev) ++{ ++ struct vs_dc *dc = dev_get_drvdata(&pdev->dev); ++ ++ vs_drm_shutdown_handler(dc); ++} ++ ++struct platform_driver vs_dc_platform_driver = { ++ .probe = vs_dc_probe, ++ .remove = vs_dc_remove, ++ .shutdown = vs_dc_shutdown, ++ .driver = { ++ .name = "verisilicon-dc", ++ .of_match_table = vs_dc_driver_dt_match, ++ }, ++}; ++ ++module_platform_driver(vs_dc_platform_driver); ++ ++MODULE_AUTHOR("Icenowy Zheng "); ++MODULE_DESCRIPTION("Verisilicon display controller driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h b/drivers/gpu/drm/verisilicon/vs_dc.h +new file mode 100644 +index 000000000000..ed1016f18758 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_dc.h +@@ -0,0 +1,38 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_DC_H_ ++#define _VS_DC_H_ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include "vs_hwdb.h" ++ ++#define VSDC_MAX_OUTPUTS 2 ++#define VSDC_RESET_COUNT 3 ++ ++struct vs_drm_dev; ++struct vs_crtc; ++ ++struct vs_dc { ++ struct regmap *regs; ++ struct clk *core_clk; ++ struct clk *axi_clk; ++ struct clk *ahb_clk; ++ struct clk *pix_clk[VSDC_MAX_OUTPUTS]; ++ struct reset_control_bulk_data rsts[VSDC_RESET_COUNT]; ++ ++ struct vs_drm_dev *drm_dev; ++ struct vs_chip_identity identity; ++}; ++ ++#endif /* _VS_DC_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h b/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h +new file mode 100644 +index 000000000000..50509bbbff08 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_DC_TOP_H_ ++#define _VS_DC_TOP_H_ ++ ++#include ++ ++#define VSDC_TOP_RST 0x0000 ++ ++#define VSDC_TOP_IRQ_ACK 0x0010 ++#define VSDC_TOP_IRQ_VSYNC(n) BIT(n) ++ ++#define VSDC_TOP_IRQ_EN 0x0014 ++ ++#define VSDC_TOP_CHIP_MODEL 0x0020 ++ ++#define VSDC_TOP_CHIP_REV 0x0024 ++ ++#define VSDC_TOP_CHIP_CUSTOMER_ID 0x0030 ++ ++#endif /* _VS_DC_TOP_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_drm.c b/drivers/gpu/drm/verisilicon/vs_drm.c +new file mode 100644 +index 000000000000..fd259d53f49f +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_drm.c +@@ -0,0 +1,182 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_bridge.h" ++#include "vs_crtc.h" ++#include "vs_dc.h" ++#include "vs_dc_top_regs.h" ++#include "vs_drm.h" ++ ++#define DRIVER_NAME "verisilicon" ++#define DRIVER_DESC "Verisilicon DC-series display controller driver" ++#define DRIVER_MAJOR 1 ++#define DRIVER_MINOR 0 ++ ++static int vs_gem_dumb_create(struct drm_file *file_priv, ++ struct drm_device *drm, ++ struct drm_mode_create_dumb *args) ++{ ++ int ret; ++ ++ /* The hardware wants 128B-aligned pitches for linear buffers. */ ++ ret = drm_mode_size_dumb(drm, args, 128, 0); ++ if (ret) ++ return ret; ++ ++ return drm_gem_dma_dumb_create_internal(file_priv, drm, args); ++} ++ ++DEFINE_DRM_GEM_FOPS(vs_drm_driver_fops); ++ ++static const struct drm_driver vs_drm_driver = { ++ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, ++ .fops = &vs_drm_driver_fops, ++ .name = DRIVER_NAME, ++ .desc = DRIVER_DESC, ++ .major = DRIVER_MAJOR, ++ .minor = DRIVER_MINOR, ++ ++ /* GEM Operations */ ++ DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(vs_gem_dumb_create), ++ DRM_FBDEV_DMA_DRIVER_OPS, ++}; ++ ++static const struct drm_mode_config_funcs vs_mode_config_funcs = { ++ .fb_create = drm_gem_fb_create, ++ .atomic_check = drm_atomic_helper_check, ++ .atomic_commit = drm_atomic_helper_commit, ++}; ++ ++static struct drm_mode_config_helper_funcs vs_mode_config_helper_funcs = { ++ .atomic_commit_tail = drm_atomic_helper_commit_tail, ++}; ++ ++static void vs_mode_config_init(struct drm_device *drm) ++{ ++ drm->mode_config.min_width = 0; ++ drm->mode_config.min_height = 0; ++ drm->mode_config.max_width = 8192; ++ drm->mode_config.max_height = 8192; ++ drm->mode_config.funcs = &vs_mode_config_funcs; ++ drm->mode_config.helper_private = &vs_mode_config_helper_funcs; ++} ++ ++int vs_drm_initialize(struct vs_dc *dc, struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct vs_drm_dev *vdrm; ++ struct drm_device *drm; ++ struct vs_crtc *crtc; ++ struct vs_bridge *bridge; ++ unsigned int i; ++ int ret; ++ ++ vdrm = devm_drm_dev_alloc(dev, &vs_drm_driver, struct vs_drm_dev, base); ++ if (IS_ERR(vdrm)) ++ return PTR_ERR(vdrm); ++ ++ drm = &vdrm->base; ++ vdrm->dc = dc; ++ dc->drm_dev = vdrm; ++ ++ ret = drmm_mode_config_init(drm); ++ if (ret) ++ return ret; ++ ++ /* Remove early framebuffers (ie. simple-framebuffer) */ ++ ret = aperture_remove_all_conflicting_devices(DRIVER_NAME); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < dc->identity.display_count; i++) { ++ crtc = vs_crtc_init(drm, dc, i); ++ if (IS_ERR(crtc)) ++ return PTR_ERR(crtc); ++ ++ bridge = vs_bridge_init(drm, crtc); ++ if (IS_ERR(bridge)) ++ return PTR_ERR(bridge); ++ ++ vdrm->crtcs[i] = crtc; ++ } ++ ++ ret = drm_vblank_init(drm, dc->identity.display_count); ++ if (ret) ++ return ret; ++ ++ vs_mode_config_init(drm); ++ ++ /* Enable connectors polling */ ++ drm_kms_helper_poll_init(drm); ++ ++ drm_mode_config_reset(drm); ++ ++ ret = drm_dev_register(drm, 0); ++ if (ret) ++ goto err_fini_poll; ++ ++ drm_client_setup(drm, NULL); ++ ++ return 0; ++ ++err_fini_poll: ++ drm_kms_helper_poll_fini(drm); ++ return ret; ++} ++ ++void vs_drm_finalize(struct vs_dc *dc) ++{ ++ struct vs_drm_dev *vdrm = dc->drm_dev; ++ struct drm_device *drm = &vdrm->base; ++ ++ drm_dev_unregister(drm); ++ drm_kms_helper_poll_fini(drm); ++ drm_atomic_helper_shutdown(drm); ++ dc->drm_dev = NULL; ++} ++ ++void vs_drm_shutdown_handler(struct vs_dc *dc) ++{ ++ struct vs_drm_dev *vdrm = dc->drm_dev; ++ ++ drm_atomic_helper_shutdown(&vdrm->base); ++} ++ ++void vs_drm_handle_irq(struct vs_dc *dc, u32 irqs) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < dc->identity.display_count; i++) { ++ if (irqs & VSDC_TOP_IRQ_VSYNC(i)) { ++ irqs &= ~VSDC_TOP_IRQ_VSYNC(i); ++ if (dc->drm_dev->crtcs[i]) ++ drm_crtc_handle_vblank(&dc->drm_dev->crtcs[i]->base); ++ } ++ } ++ ++ if (irqs) ++ drm_warn_once(&dc->drm_dev->base, ++ "Unknown Verisilicon DC interrupt 0x%x fired!\n", ++ irqs); ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_drm.h b/drivers/gpu/drm/verisilicon/vs_drm.h +new file mode 100644 +index 000000000000..606338206a42 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_drm.h +@@ -0,0 +1,28 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#ifndef _VS_DRM_H_ ++#define _VS_DRM_H_ ++ ++#include ++#include ++ ++#include ++ ++struct vs_dc; ++ ++struct vs_drm_dev { ++ struct drm_device base; ++ ++ struct vs_dc *dc; ++ struct vs_crtc *crtcs[VSDC_MAX_OUTPUTS]; ++}; ++ ++int vs_drm_initialize(struct vs_dc *dc, struct platform_device *pdev); ++void vs_drm_finalize(struct vs_dc *dc); ++void vs_drm_shutdown_handler(struct vs_dc *dc); ++void vs_drm_handle_irq(struct vs_dc *dc, u32 irqs); ++ ++#endif /* _VS_DRM_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisilicon/vs_hwdb.c +new file mode 100644 +index 000000000000..09336af0900a +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c +@@ -0,0 +1,150 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++ ++#include ++ ++#include "vs_dc_top_regs.h" ++#include "vs_hwdb.h" ++ ++static const u32 vs_formats_array_no_yuv444[] = { ++ DRM_FORMAT_XRGB4444, ++ DRM_FORMAT_XBGR4444, ++ DRM_FORMAT_RGBX4444, ++ DRM_FORMAT_BGRX4444, ++ DRM_FORMAT_ARGB4444, ++ DRM_FORMAT_ABGR4444, ++ DRM_FORMAT_RGBA4444, ++ DRM_FORMAT_BGRA4444, ++ DRM_FORMAT_XRGB1555, ++ DRM_FORMAT_XBGR1555, ++ DRM_FORMAT_RGBX5551, ++ DRM_FORMAT_BGRX5551, ++ DRM_FORMAT_ARGB1555, ++ DRM_FORMAT_ABGR1555, ++ DRM_FORMAT_RGBA5551, ++ DRM_FORMAT_BGRA5551, ++ DRM_FORMAT_RGB565, ++ DRM_FORMAT_BGR565, ++ DRM_FORMAT_XRGB8888, ++ DRM_FORMAT_XBGR8888, ++ DRM_FORMAT_RGBX8888, ++ DRM_FORMAT_BGRX8888, ++ DRM_FORMAT_ARGB8888, ++ DRM_FORMAT_ABGR8888, ++ DRM_FORMAT_RGBA8888, ++ DRM_FORMAT_BGRA8888, ++ DRM_FORMAT_ARGB2101010, ++ DRM_FORMAT_ABGR2101010, ++ DRM_FORMAT_RGBA1010102, ++ DRM_FORMAT_BGRA1010102, ++ /* TODO: non-RGB formats */ ++}; ++ ++static const u32 vs_formats_array_with_yuv444[] = { ++ DRM_FORMAT_XRGB4444, ++ DRM_FORMAT_XBGR4444, ++ DRM_FORMAT_RGBX4444, ++ DRM_FORMAT_BGRX4444, ++ DRM_FORMAT_ARGB4444, ++ DRM_FORMAT_ABGR4444, ++ DRM_FORMAT_RGBA4444, ++ DRM_FORMAT_BGRA4444, ++ DRM_FORMAT_XRGB1555, ++ DRM_FORMAT_XBGR1555, ++ DRM_FORMAT_RGBX5551, ++ DRM_FORMAT_BGRX5551, ++ DRM_FORMAT_ARGB1555, ++ DRM_FORMAT_ABGR1555, ++ DRM_FORMAT_RGBA5551, ++ DRM_FORMAT_BGRA5551, ++ DRM_FORMAT_RGB565, ++ DRM_FORMAT_BGR565, ++ DRM_FORMAT_XRGB8888, ++ DRM_FORMAT_XBGR8888, ++ DRM_FORMAT_RGBX8888, ++ DRM_FORMAT_BGRX8888, ++ DRM_FORMAT_ARGB8888, ++ DRM_FORMAT_ABGR8888, ++ DRM_FORMAT_RGBA8888, ++ DRM_FORMAT_BGRA8888, ++ DRM_FORMAT_ARGB2101010, ++ DRM_FORMAT_ABGR2101010, ++ DRM_FORMAT_RGBA1010102, ++ DRM_FORMAT_BGRA1010102, ++ /* TODO: non-RGB formats */ ++}; ++ ++static const struct vs_formats vs_formats_no_yuv444 = { ++ .array = vs_formats_array_no_yuv444, ++ .num = ARRAY_SIZE(vs_formats_array_no_yuv444) ++}; ++ ++static const struct vs_formats vs_formats_with_yuv444 = { ++ .array = vs_formats_array_with_yuv444, ++ .num = ARRAY_SIZE(vs_formats_array_with_yuv444) ++}; ++ ++static struct vs_chip_identity vs_chip_identities[] = { ++ { ++ .model = 0x8200, ++ .revision = 0x5720, ++ .customer_id = ~0U, ++ ++ .display_count = 2, ++ .formats = &vs_formats_no_yuv444, ++ }, ++ { ++ .model = 0x8200, ++ .revision = 0x5721, ++ .customer_id = 0x30B, ++ ++ .display_count = 2, ++ .formats = &vs_formats_no_yuv444, ++ }, ++ { ++ .model = 0x8200, ++ .revision = 0x5720, ++ .customer_id = 0x310, ++ ++ .display_count = 2, ++ .formats = &vs_formats_with_yuv444, ++ }, ++ { ++ .model = 0x8200, ++ .revision = 0x5720, ++ .customer_id = 0x311, ++ ++ .display_count = 2, ++ .formats = &vs_formats_no_yuv444, ++ }, ++}; ++ ++int vs_fill_chip_identity(struct regmap *regs, ++ struct vs_chip_identity *ident) ++{ ++ u32 model; ++ u32 revision; ++ u32 customer_id; ++ int i; ++ ++ regmap_read(regs, VSDC_TOP_CHIP_MODEL, &model); ++ regmap_read(regs, VSDC_TOP_CHIP_REV, &revision); ++ regmap_read(regs, VSDC_TOP_CHIP_CUSTOMER_ID, &customer_id); ++ ++ for (i = 0; i < ARRAY_SIZE(vs_chip_identities); i++) { ++ if (vs_chip_identities[i].model == model && ++ vs_chip_identities[i].revision == revision && ++ (vs_chip_identities[i].customer_id == customer_id || ++ vs_chip_identities[i].customer_id == ~0U)) { ++ memcpy(ident, &vs_chip_identities[i], sizeof(*ident)); ++ ident->customer_id = customer_id; ++ return 0; ++ } ++ } ++ ++ return -EINVAL; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisilicon/vs_hwdb.h +new file mode 100644 +index 000000000000..92192e4fa086 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h +@@ -0,0 +1,29 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#ifndef _VS_HWDB_H_ ++#define _VS_HWDB_H_ ++ ++#include ++#include ++ ++struct vs_formats { ++ const u32 *array; ++ unsigned int num; ++}; ++ ++struct vs_chip_identity { ++ u32 model; ++ u32 revision; ++ u32 customer_id; ++ ++ u32 display_count; ++ const struct vs_formats *formats; ++}; ++ ++int vs_fill_chip_identity(struct regmap *regs, ++ struct vs_chip_identity *ident); ++ ++#endif /* _VS_HWDB_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_plane.c b/drivers/gpu/drm/verisilicon/vs_plane.c +new file mode 100644 +index 000000000000..2f3953e588a3 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_plane.c +@@ -0,0 +1,124 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "vs_plane.h" ++ ++void drm_format_to_vs_format(u32 drm_format, struct vs_format *vs_format) ++{ ++ switch (drm_format) { ++ case DRM_FORMAT_XRGB4444: ++ case DRM_FORMAT_RGBX4444: ++ case DRM_FORMAT_XBGR4444: ++ case DRM_FORMAT_BGRX4444: ++ vs_format->color = VSDC_COLOR_FORMAT_X4R4G4B4; ++ break; ++ case DRM_FORMAT_ARGB4444: ++ case DRM_FORMAT_RGBA4444: ++ case DRM_FORMAT_ABGR4444: ++ case DRM_FORMAT_BGRA4444: ++ vs_format->color = VSDC_COLOR_FORMAT_A4R4G4B4; ++ break; ++ case DRM_FORMAT_XRGB1555: ++ case DRM_FORMAT_RGBX5551: ++ case DRM_FORMAT_XBGR1555: ++ case DRM_FORMAT_BGRX5551: ++ vs_format->color = VSDC_COLOR_FORMAT_X1R5G5B5; ++ break; ++ case DRM_FORMAT_ARGB1555: ++ case DRM_FORMAT_RGBA5551: ++ case DRM_FORMAT_ABGR1555: ++ case DRM_FORMAT_BGRA5551: ++ vs_format->color = VSDC_COLOR_FORMAT_A1R5G5B5; ++ break; ++ case DRM_FORMAT_RGB565: ++ case DRM_FORMAT_BGR565: ++ vs_format->color = VSDC_COLOR_FORMAT_R5G6B5; ++ break; ++ case DRM_FORMAT_XRGB8888: ++ case DRM_FORMAT_RGBX8888: ++ case DRM_FORMAT_XBGR8888: ++ case DRM_FORMAT_BGRX8888: ++ vs_format->color = VSDC_COLOR_FORMAT_X8R8G8B8; ++ break; ++ case DRM_FORMAT_ARGB8888: ++ case DRM_FORMAT_RGBA8888: ++ case DRM_FORMAT_ABGR8888: ++ case DRM_FORMAT_BGRA8888: ++ vs_format->color = VSDC_COLOR_FORMAT_A8R8G8B8; ++ break; ++ case DRM_FORMAT_ARGB2101010: ++ case DRM_FORMAT_RGBA1010102: ++ case DRM_FORMAT_ABGR2101010: ++ case DRM_FORMAT_BGRA1010102: ++ vs_format->color = VSDC_COLOR_FORMAT_A2R10G10B10; ++ break; ++ default: ++ pr_warn("Unexpected drm format!\n"); ++ } ++ ++ switch (drm_format) { ++ case DRM_FORMAT_RGBX4444: ++ case DRM_FORMAT_RGBA4444: ++ case DRM_FORMAT_RGBX5551: ++ case DRM_FORMAT_RGBA5551: ++ case DRM_FORMAT_RGBX8888: ++ case DRM_FORMAT_RGBA8888: ++ case DRM_FORMAT_RGBA1010102: ++ vs_format->swizzle = VSDC_SWIZZLE_RGBA; ++ break; ++ case DRM_FORMAT_XBGR4444: ++ case DRM_FORMAT_ABGR4444: ++ case DRM_FORMAT_XBGR1555: ++ case DRM_FORMAT_ABGR1555: ++ case DRM_FORMAT_BGR565: ++ case DRM_FORMAT_XBGR8888: ++ case DRM_FORMAT_ABGR8888: ++ case DRM_FORMAT_ABGR2101010: ++ vs_format->swizzle = VSDC_SWIZZLE_ABGR; ++ break; ++ case DRM_FORMAT_BGRX4444: ++ case DRM_FORMAT_BGRA4444: ++ case DRM_FORMAT_BGRX5551: ++ case DRM_FORMAT_BGRA5551: ++ case DRM_FORMAT_BGRX8888: ++ case DRM_FORMAT_BGRA8888: ++ case DRM_FORMAT_BGRA1010102: ++ vs_format->swizzle = VSDC_SWIZZLE_BGRA; ++ break; ++ default: ++ /* N/A for YUV formats */ ++ vs_format->swizzle = VSDC_SWIZZLE_ARGB; ++ } ++ ++ /* N/A for non-YUV formats */ ++ vs_format->uv_swizzle = false; ++} ++ ++dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, ++ const struct drm_rect *src_rect) ++{ ++ struct drm_gem_dma_object *gem; ++ dma_addr_t dma_addr; ++ ++ /* Get the physical address of the buffer in memory */ ++ gem = drm_fb_dma_get_gem_obj(fb, 0); ++ ++ /* Compute the start of the displayed memory */ ++ dma_addr = gem->dma_addr + fb->offsets[0]; ++ ++ /* Fixup framebuffer address for src coordinates */ ++ dma_addr += drm_format_info_min_pitch(fb->format, 0, ++ src_rect->x1 >> 16); ++ dma_addr += (src_rect->y1 >> 16) * fb->pitches[0]; ++ ++ return dma_addr; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_plane.h b/drivers/gpu/drm/verisilicon/vs_plane.h +new file mode 100644 +index 000000000000..41875ea3d66a +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_plane.h +@@ -0,0 +1,72 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_PLANE_H_ ++#define _VS_PLANE_H_ ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#define VSDC_MAKE_PLANE_SIZE(w, h) (((w) & 0x7fff) | (((h) & 0x7fff) << 15)) ++#define VSDC_MAKE_PLANE_POS(x, y) (((x) & 0x7fff) | (((y) & 0x7fff) << 15)) ++ ++struct vs_dc; ++ ++enum vs_color_format { ++ VSDC_COLOR_FORMAT_X4R4G4B4, ++ VSDC_COLOR_FORMAT_A4R4G4B4, ++ VSDC_COLOR_FORMAT_X1R5G5B5, ++ VSDC_COLOR_FORMAT_A1R5G5B5, ++ VSDC_COLOR_FORMAT_R5G6B5, ++ VSDC_COLOR_FORMAT_X8R8G8B8, ++ VSDC_COLOR_FORMAT_A8R8G8B8, ++ VSDC_COLOR_FORMAT_YUY2, ++ VSDC_COLOR_FORMAT_UYVY, ++ VSDC_COLOR_FORMAT_INDEX8, ++ VSDC_COLOR_FORMAT_MONOCHROME, ++ VSDC_COLOR_FORMAT_YV12 = 0xf, ++ VSDC_COLOR_FORMAT_A8, ++ VSDC_COLOR_FORMAT_NV12, ++ VSDC_COLOR_FORMAT_NV16, ++ VSDC_COLOR_FORMAT_RG16, ++ VSDC_COLOR_FORMAT_R8, ++ VSDC_COLOR_FORMAT_NV12_10BIT, ++ VSDC_COLOR_FORMAT_A2R10G10B10, ++ VSDC_COLOR_FORMAT_NV16_10BIT, ++ VSDC_COLOR_FORMAT_INDEX1, ++ VSDC_COLOR_FORMAT_INDEX2, ++ VSDC_COLOR_FORMAT_INDEX4, ++ VSDC_COLOR_FORMAT_P010, ++ VSDC_COLOR_FORMAT_YUV444, ++ VSDC_COLOR_FORMAT_YUV444_10BIT ++}; ++ ++enum vs_swizzle { ++ VSDC_SWIZZLE_ARGB, ++ VSDC_SWIZZLE_RGBA, ++ VSDC_SWIZZLE_ABGR, ++ VSDC_SWIZZLE_BGRA, ++}; ++ ++struct vs_format { ++ enum vs_color_format color; ++ enum vs_swizzle swizzle; ++ bool uv_swizzle; ++}; ++ ++void drm_format_to_vs_format(u32 drm_format, struct vs_format *vs_format); ++dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, ++ const struct drm_rect *src_rect); ++ ++struct drm_plane *vs_primary_plane_init(struct drm_device *dev, struct vs_dc *dc); ++ ++#endif /* _VS_PLANE_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane.c b/drivers/gpu/drm/verisilicon/vs_primary_plane.c +new file mode 100644 +index 000000000000..e8fcb5958615 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_primary_plane.c +@@ -0,0 +1,173 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ */ ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_crtc.h" ++#include "vs_plane.h" ++#include "vs_dc.h" ++#include "vs_primary_plane_regs.h" ++ ++static int vs_primary_plane_atomic_check(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, ++ plane); ++ struct drm_crtc *crtc = new_plane_state->crtc; ++ struct drm_crtc_state *crtc_state; ++ ++ if (!crtc) ++ return 0; ++ ++ crtc_state = drm_atomic_get_new_crtc_state(state, crtc); ++ if (WARN_ON(!crtc_state)) ++ return -EINVAL; ++ ++ return drm_atomic_helper_check_plane_state(new_plane_state, ++ crtc_state, ++ DRM_PLANE_NO_SCALING, ++ DRM_PLANE_NO_SCALING, ++ false, true); ++} ++ ++static void vs_primary_plane_commit(struct vs_dc *dc, unsigned int output) ++{ ++ regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), ++ VSDC_FB_CONFIG_EX_COMMIT); ++} ++ ++static void vs_primary_plane_atomic_enable(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, ++ plane); ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ unsigned int output = vcrtc->id; ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), ++ VSDC_FB_CONFIG_EX_FB_EN); ++ regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output), ++ VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK, ++ VSDC_FB_CONFIG_EX_DISPLAY_ID(output)); ++ ++ vs_primary_plane_commit(dc, output); ++} ++ ++static void vs_primary_plane_atomic_disable(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_old_plane_state(atomic_state, ++ plane); ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ unsigned int output = vcrtc->id; ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), ++ VSDC_FB_CONFIG_EX_FB_EN); ++ ++ vs_primary_plane_commit(dc, output); ++} ++ ++static void vs_primary_plane_atomic_update(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, ++ plane); ++ struct drm_framebuffer *fb = state->fb; ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_dc *dc; ++ struct vs_crtc *vcrtc; ++ struct vs_format fmt; ++ unsigned int output; ++ dma_addr_t dma_addr; ++ ++ if (!state->visible) { ++ vs_primary_plane_atomic_disable(plane, atomic_state); ++ return; ++ } ++ ++ vcrtc = drm_crtc_to_vs_crtc(crtc); ++ output = vcrtc->id; ++ dc = vcrtc->dc; ++ ++ drm_format_to_vs_format(state->fb->format->format, &fmt); ++ ++ regmap_update_bits(dc->regs, VSDC_FB_CONFIG(output), ++ VSDC_FB_CONFIG_FMT_MASK, ++ VSDC_FB_CONFIG_FMT(fmt.color)); ++ regmap_update_bits(dc->regs, VSDC_FB_CONFIG(output), ++ VSDC_FB_CONFIG_SWIZZLE_MASK, ++ VSDC_FB_CONFIG_SWIZZLE(fmt.swizzle)); ++ regmap_assign_bits(dc->regs, VSDC_FB_CONFIG(output), ++ VSDC_FB_CONFIG_UV_SWIZZLE_EN, fmt.uv_swizzle); ++ ++ dma_addr = vs_fb_get_dma_addr(fb, &state->src); ++ ++ regmap_write(dc->regs, VSDC_FB_ADDRESS(output), ++ lower_32_bits(dma_addr)); ++ regmap_write(dc->regs, VSDC_FB_STRIDE(output), ++ fb->pitches[0]); ++ ++ regmap_write(dc->regs, VSDC_FB_TOP_LEFT(output), ++ VSDC_MAKE_PLANE_POS(state->crtc_x, state->crtc_y)); ++ regmap_write(dc->regs, VSDC_FB_BOTTOM_RIGHT(output), ++ VSDC_MAKE_PLANE_POS(state->crtc_x + state->crtc_w, ++ state->crtc_y + state->crtc_h)); ++ regmap_write(dc->regs, VSDC_FB_SIZE(output), ++ VSDC_MAKE_PLANE_SIZE(state->crtc_w, state->crtc_h)); ++ ++ regmap_write(dc->regs, VSDC_FB_BLEND_CONFIG(output), ++ VSDC_FB_BLEND_CONFIG_BLEND_DISABLE); ++ ++ vs_primary_plane_commit(dc, output); ++} ++ ++static const struct drm_plane_helper_funcs vs_primary_plane_helper_funcs = { ++ .atomic_check = vs_primary_plane_atomic_check, ++ .atomic_update = vs_primary_plane_atomic_update, ++ .atomic_enable = vs_primary_plane_atomic_enable, ++ .atomic_disable = vs_primary_plane_atomic_disable, ++}; ++ ++static const struct drm_plane_funcs vs_primary_plane_funcs = { ++ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, ++ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, ++ .disable_plane = drm_atomic_helper_disable_plane, ++ .reset = drm_atomic_helper_plane_reset, ++ .update_plane = drm_atomic_helper_update_plane, ++}; ++ ++struct drm_plane *vs_primary_plane_init(struct drm_device *drm_dev, struct vs_dc *dc) ++{ ++ struct drm_plane *plane; ++ ++ plane = drmm_universal_plane_alloc(drm_dev, struct drm_plane, dev, 0, ++ &vs_primary_plane_funcs, ++ dc->identity.formats->array, ++ dc->identity.formats->num, ++ NULL, ++ DRM_PLANE_TYPE_PRIMARY, ++ NULL); ++ ++ if (IS_ERR(plane)) ++ return plane; ++ ++ drm_plane_helper_add(plane, &vs_primary_plane_helper_funcs); ++ ++ return plane; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h +new file mode 100644 +index 000000000000..cbb125c46b39 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h +@@ -0,0 +1,53 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_PRIMARY_PLANE_REGS_H_ ++#define _VS_PRIMARY_PLANE_REGS_H_ ++ ++#include ++ ++#define VSDC_FB_ADDRESS(n) (0x1400 + 0x4 * (n)) ++ ++#define VSDC_FB_STRIDE(n) (0x1408 + 0x4 * (n)) ++ ++#define VSDC_FB_CONFIG(n) (0x1518 + 0x4 * (n)) ++#define VSDC_FB_CONFIG_CLEAR_EN BIT(8) ++#define VSDC_FB_CONFIG_ROT_MASK GENMASK(13, 11) ++#define VSDC_FB_CONFIG_ROT(v) ((v) << 11) ++#define VSDC_FB_CONFIG_YUV_SPACE_MASK GENMASK(16, 14) ++#define VSDC_FB_CONFIG_YUV_SPACE(v) ((v) << 14) ++#define VSDC_FB_CONFIG_TILE_MODE_MASK GENMASK(21, 17) ++#define VSDC_FB_CONFIG_TILE_MODE(v) ((v) << 14) ++#define VSDC_FB_CONFIG_SCALE_EN BIT(22) ++#define VSDC_FB_CONFIG_SWIZZLE_MASK GENMASK(24, 23) ++#define VSDC_FB_CONFIG_SWIZZLE(v) ((v) << 23) ++#define VSDC_FB_CONFIG_UV_SWIZZLE_EN BIT(25) ++#define VSDC_FB_CONFIG_FMT_MASK GENMASK(31, 26) ++#define VSDC_FB_CONFIG_FMT(v) ((v) << 26) ++ ++#define VSDC_FB_SIZE(n) (0x1810 + 0x4 * (n)) ++/* Fill with value generated with VSDC_MAKE_PLANE_SIZE(w, h) */ ++ ++#define VSDC_FB_CONFIG_EX(n) (0x1CC0 + 0x4 * (n)) ++#define VSDC_FB_CONFIG_EX_COMMIT BIT(12) ++#define VSDC_FB_CONFIG_EX_FB_EN BIT(13) ++#define VSDC_FB_CONFIG_EX_ZPOS_MASK GENMASK(18, 16) ++#define VSDC_FB_CONFIG_EX_ZPOS(v) ((v) << 16) ++#define VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK GENMASK(19, 19) ++#define VSDC_FB_CONFIG_EX_DISPLAY_ID(v) ((v) << 19) ++ ++#define VSDC_FB_TOP_LEFT(n) (0x24D8 + 0x4 * (n)) ++/* Fill with value generated with VSDC_MAKE_PLANE_POS(x, y) */ ++ ++#define VSDC_FB_BOTTOM_RIGHT(n) (0x24E0 + 0x4 * (n)) ++/* Fill with value generated with VSDC_MAKE_PLANE_POS(x, y) */ ++ ++#define VSDC_FB_BLEND_CONFIG(n) (0x2510 + 0x4 * (n)) ++#define VSDC_FB_BLEND_CONFIG_BLEND_DISABLE BIT(1) ++ ++#endif /* _VS_PRIMARY_PLANE_REGS_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch b/SPECS/linux-lts/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch new file mode 100644 index 0000000000..641e31a30d --- /dev/null +++ b/SPECS/linux-lts/0192-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch @@ -0,0 +1,153 @@ +From f3c9d099748a9f334530dc8d3b829667282a09e2 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:18 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: display/bridge: add binding for + TH1520 HDMI controller + +T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired +with DesignWare HDMI PHY, with an extra clock gate for HDMI pixel clock +and two reset controls. + +Add a device tree binding to it. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Thomas Zimmermann +Link: https://patch.msgid.link/20260129023922.1527729-5-zhengxingda@iscas.ac.cn +(cherry picked from commit 3d60ff99a78ccd3b72765542dd083b134d6ae4bb) +Signed-off-by: Han Gao +--- + .../display/bridge/thead,th1520-dw-hdmi.yaml | 120 ++++++++++++++++++ + 1 file changed, 120 insertions(+) + create mode 100644 Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml + +diff --git a/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml +new file mode 100644 +index 000000000000..68fff885ce15 +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml +@@ -0,0 +1,120 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/display/bridge/thead,th1520-dw-hdmi.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: T-Head TH1520 DesignWare HDMI TX Encoder ++ ++maintainers: ++ - Icenowy Zheng ++ ++description: ++ The HDMI transmitter is a Synopsys DesignWare HDMI TX controller ++ paired with a DesignWare HDMI Gen2 TX PHY. ++ ++allOf: ++ - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - thead,th1520-dw-hdmi ++ ++ reg-io-width: ++ const: 4 ++ ++ clocks: ++ maxItems: 4 ++ ++ clock-names: ++ items: ++ - const: iahb ++ - const: isfr ++ - const: cec ++ - const: pix ++ ++ resets: ++ items: ++ - description: Main reset ++ - description: Configuration APB reset ++ ++ reset-names: ++ items: ++ - const: main ++ - const: apb ++ ++ ports: ++ $ref: /schemas/graph.yaml#/properties/ports ++ ++ properties: ++ port@0: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: Input port connected to DC8200 DPU "DP" output ++ ++ port@1: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: HDMI output port ++ ++ required: ++ - port@0 ++ - port@1 ++ ++required: ++ - compatible ++ - reg ++ - reg-io-width ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - interrupts ++ - ports ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ hdmi@ffef540000 { ++ compatible = "thead,th1520-dw-hdmi"; ++ reg = <0xff 0xef540000 0x0 0x40000>; ++ reg-io-width = <4>; ++ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_vo CLK_HDMI_PCLK>, ++ <&clk_vo CLK_HDMI_SFR>, ++ <&clk_vo CLK_HDMI_CEC>, ++ <&clk_vo CLK_HDMI_PIXCLK>; ++ clock-names = "iahb", "isfr", "cec", "pix"; ++ resets = <&rst_vo TH1520_RESET_ID_HDMI>, ++ <&rst_vo TH1520_RESET_ID_HDMI_APB>; ++ reset-names = "main", "apb"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ ++ hdmi_in: endpoint { ++ remote-endpoint = <&dpu_out_dp1>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ hdmi_out_conn: endpoint { ++ remote-endpoint = <&hdmi_conn_in>; ++ }; ++ }; ++ }; ++ }; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0192-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch b/SPECS/linux-lts/0192-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch deleted file mode 100644 index feb6510c1b..0000000000 --- a/SPECS/linux-lts/0192-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 34a1f2a285caa0d97a9ec22b7fdad41bc44c6a59 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:15 +0800 -Subject: [PATCH 192/467] UPSTREAM: dt-bindings: vendor-prefixes: add - verisilicon - -VeriSilicon is a Silicon IP vendor, which is the current owner of -Vivante series video-related IPs and Hantro series video codec IPs. - -Add a vendor prefix for this company. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Acked-by: Rob Herring (Arm) -Signed-off-by: Thomas Zimmermann -Link: https://patch.msgid.link/20260129023922.1527729-2-zhengxingda@iscas.ac.cn -(cherry picked from commit c131d78840d7487e41c3afdc52bb74fd3f8861ef) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml -index 647746e6f75f..d03f700d178e 100644 ---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml -+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -1723,6 +1723,8 @@ patternProperties: - description: Variscite Ltd. - "^vdl,.*": - description: Van der Laan b.v. -+ "^verisilicon,.*": -+ description: VeriSilicon Microelectronics (Shanghai) Co., Ltd. - "^vertexcom,.*": - description: Vertexcom Technologies, Inc. - "^via,.*": --- -2.53.0 - diff --git a/SPECS/linux-lts/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch b/SPECS/linux-lts/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch new file mode 100644 index 0000000000..cf9d00a163 --- /dev/null +++ b/SPECS/linux-lts/0193-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch @@ -0,0 +1,257 @@ +From 58ad5626c4911a37f2e711c60ae825d55251511b Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:19 +0800 +Subject: [RUYI PATCH] UPSTREAM: drm/bridge: add a driver for T-Head TH1520 + HDMI controller + +T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller (paired +with DesignWare HDMI TX PHY Gen2) that takes the "DP" output from the +display controller. + +Add a driver for this controller utilizing the common DesignWare HDMI +code in the kernel. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Tested-by: Han Gao +Tested-by: Michal Wilczynski +Acked-by: Thomas Zimmermann +Signed-off-by: Thomas Zimmermann +Link: https://patch.msgid.link/20260129023922.1527729-6-zhengxingda@iscas.ac.cn +(cherry picked from commit 96f30ee0fb9db1663eb8fd55c12e4c67da8c4a90) +Signed-off-by: Han Gao +--- + MAINTAINERS | 1 + + drivers/gpu/drm/bridge/Kconfig | 10 ++ + drivers/gpu/drm/bridge/Makefile | 1 + + drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 173 ++++++++++++++++++++++++ + 4 files changed, 185 insertions(+) + create mode 100644 drivers/gpu/drm/bridge/th1520-dw-hdmi.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index b50b6c7a9b52..1509fa6ab229 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -22227,6 +22227,7 @@ F: Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml + F: arch/riscv/boot/dts/thead/ + F: drivers/clk/thead/clk-th1520-ap.c + F: drivers/firmware/thead,th1520-aon.c ++F: drivers/gpu/drm/bridge/th1520-dw-hdmi.c + F: drivers/mailbox/mailbox-th1520.c + F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c + F: drivers/pinctrl/pinctrl-th1520.c +diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig +index a250afd8d662..8e19f5fb9ad7 100644 +--- a/drivers/gpu/drm/bridge/Kconfig ++++ b/drivers/gpu/drm/bridge/Kconfig +@@ -335,6 +335,16 @@ config DRM_THINE_THC63LVD1024 + help + Thine THC63LVD1024 LVDS/parallel converter driver. + ++config DRM_THEAD_TH1520_DW_HDMI ++ tristate "T-Head TH1520 DesignWare HDMI bridge" ++ depends on OF ++ depends on COMMON_CLK ++ depends on ARCH_THEAD || COMPILE_TEST ++ select DRM_DW_HDMI ++ help ++ Choose this to enable support for the internal HDMI bridge found ++ on the T-Head TH1520 SoC. ++ + config DRM_TOSHIBA_TC358762 + tristate "TC358762 DSI/DPI bridge" + depends on OF +diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile +index c7dc03182e59..085b5db45d6f 100644 +--- a/drivers/gpu/drm/bridge/Makefile ++++ b/drivers/gpu/drm/bridge/Makefile +@@ -28,6 +28,7 @@ obj-$(CONFIG_DRM_SII902X) += sii902x.o + obj-$(CONFIG_DRM_SII9234) += sii9234.o + obj-$(CONFIG_DRM_SIMPLE_BRIDGE) += simple-bridge.o + obj-$(CONFIG_DRM_SOLOMON_SSD2825) += ssd2825.o ++obj-$(CONFIG_DRM_THEAD_TH1520_DW_HDMI) += th1520-dw-hdmi.o + obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o + obj-$(CONFIG_DRM_TOSHIBA_TC358762) += tc358762.o + obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o +diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +new file mode 100644 +index 000000000000..389eead5f1c4 +--- /dev/null ++++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +@@ -0,0 +1,173 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on rcar_dw_hdmi.c, which is: ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * Based on imx8mp-hdmi-tx.c, which is: ++ * Copyright (C) 2022 Pengutronix, Lucas Stach ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define TH1520_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */ ++#define TH1520_HDMI_PHY_CKSYMTXCTRL 0x09 /* Clock Symbol and Transmitter Control Register */ ++#define TH1520_HDMI_PHY_VLEVCTRL 0x0e /* Voltage Level Control Register */ ++#define TH1520_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */ ++#define TH1520_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */ ++#define TH1520_HDMI_PHY_TXTERM 0x19 /* Transmission Termination Register */ ++ ++struct th1520_hdmi_phy_params { ++ unsigned long mpixelclock; ++ u16 opmode_pllcfg; ++ u16 pllcurrgmpctrl; ++ u16 plldivctrl; ++ u16 cksymtxctrl; ++ u16 vlevctrl; ++ u16 txterm; ++}; ++ ++static const struct th1520_hdmi_phy_params th1520_hdmi_phy_params[] = { ++ { 35500000, 0x0003, 0x0283, 0x0628, 0x8088, 0x01a0, 0x0007 }, ++ { 44900000, 0x0003, 0x0285, 0x0228, 0x8088, 0x01a0, 0x0007 }, ++ { 71000000, 0x0002, 0x1183, 0x0614, 0x8088, 0x01a0, 0x0007 }, ++ { 90000000, 0x0002, 0x1142, 0x0214, 0x8088, 0x01a0, 0x0007 }, ++ { 121750000, 0x0001, 0x20c0, 0x060a, 0x8088, 0x01a0, 0x0007 }, ++ { 165000000, 0x0001, 0x2080, 0x020a, 0x8088, 0x01a0, 0x0007 }, ++ { 198000000, 0x0000, 0x3040, 0x0605, 0x83c8, 0x0120, 0x0004 }, ++ { 297000000, 0x0000, 0x3041, 0x0205, 0x81dc, 0x0200, 0x0005 }, ++ { 371250000, 0x0640, 0x3041, 0x0205, 0x80f6, 0x0140, 0x0000 }, ++ { 495000000, 0x0640, 0x3080, 0x0005, 0x80f6, 0x0140, 0x0000 }, ++ { 594000000, 0x0640, 0x3080, 0x0005, 0x80fa, 0x01e0, 0x0004 }, ++}; ++ ++struct th1520_hdmi { ++ struct dw_hdmi_plat_data plat_data; ++ struct dw_hdmi *dw_hdmi; ++ struct clk *pixclk; ++ struct reset_control *mainrst, *prst; ++}; ++ ++static enum drm_mode_status ++th1520_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, ++ const struct drm_display_info *info, ++ const struct drm_display_mode *mode) ++{ ++ /* ++ * The maximum supported clock frequency is 594 MHz, as shown in the PHY ++ * parameters table. ++ */ ++ if (mode->clock > 594000) ++ return MODE_CLOCK_HIGH; ++ ++ return MODE_OK; ++} ++ ++static void th1520_hdmi_phy_set_params(struct dw_hdmi *hdmi, ++ const struct th1520_hdmi_phy_params *params) ++{ ++ dw_hdmi_phy_i2c_write(hdmi, params->opmode_pllcfg, ++ TH1520_HDMI_PHY_OPMODE_PLLCFG); ++ dw_hdmi_phy_i2c_write(hdmi, params->pllcurrgmpctrl, ++ TH1520_HDMI_PHY_PLLCURRGMPCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, params->plldivctrl, ++ TH1520_HDMI_PHY_PLLDIVCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, params->vlevctrl, ++ TH1520_HDMI_PHY_VLEVCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, params->cksymtxctrl, ++ TH1520_HDMI_PHY_CKSYMTXCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, params->txterm, ++ TH1520_HDMI_PHY_TXTERM); ++} ++ ++static int th1520_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data, ++ unsigned long mpixelclock) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(th1520_hdmi_phy_params); i++) { ++ if (mpixelclock <= th1520_hdmi_phy_params[i].mpixelclock) { ++ th1520_hdmi_phy_set_params(hdmi, ++ &th1520_hdmi_phy_params[i]); ++ return 0; ++ } ++ } ++ ++ return -EINVAL; ++} ++ ++static int th1520_dw_hdmi_probe(struct platform_device *pdev) ++{ ++ struct th1520_hdmi *hdmi; ++ struct dw_hdmi_plat_data *plat_data; ++ struct device *dev = &pdev->dev; ++ ++ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); ++ if (!hdmi) ++ return -ENOMEM; ++ ++ plat_data = &hdmi->plat_data; ++ ++ hdmi->pixclk = devm_clk_get_enabled(dev, "pix"); ++ if (IS_ERR(hdmi->pixclk)) ++ return dev_err_probe(dev, PTR_ERR(hdmi->pixclk), ++ "Unable to get pixel clock\n"); ++ ++ hdmi->mainrst = devm_reset_control_get_exclusive_deasserted(dev, "main"); ++ if (IS_ERR(hdmi->mainrst)) ++ return dev_err_probe(dev, PTR_ERR(hdmi->mainrst), ++ "Unable to get main reset\n"); ++ ++ hdmi->prst = devm_reset_control_get_exclusive_deasserted(dev, "apb"); ++ if (IS_ERR(hdmi->prst)) ++ return dev_err_probe(dev, PTR_ERR(hdmi->prst), ++ "Unable to get apb reset\n"); ++ ++ plat_data->output_port = 1; ++ plat_data->mode_valid = th1520_hdmi_mode_valid; ++ plat_data->configure_phy = th1520_hdmi_phy_configure; ++ plat_data->priv_data = hdmi; ++ ++ hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); ++ if (IS_ERR(hdmi)) ++ return PTR_ERR(hdmi); ++ ++ platform_set_drvdata(pdev, hdmi); ++ ++ return 0; ++} ++ ++static void th1520_dw_hdmi_remove(struct platform_device *pdev) ++{ ++ struct dw_hdmi *hdmi = platform_get_drvdata(pdev); ++ ++ dw_hdmi_remove(hdmi); ++} ++ ++static const struct of_device_id th1520_dw_hdmi_of_table[] = { ++ { .compatible = "thead,th1520-dw-hdmi" }, ++ { /* Sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, th1520_dw_hdmi_of_table); ++ ++static struct platform_driver th1520_dw_hdmi_platform_driver = { ++ .probe = th1520_dw_hdmi_probe, ++ .remove = th1520_dw_hdmi_remove, ++ .driver = { ++ .name = "th1520-dw-hdmi", ++ .of_match_table = th1520_dw_hdmi_of_table, ++ }, ++}; ++ ++module_platform_driver(th1520_dw_hdmi_platform_driver); ++ ++MODULE_AUTHOR("Icenowy Zheng "); ++MODULE_DESCRIPTION("T-Head TH1520 HDMI Encoder Driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0193-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch b/SPECS/linux-lts/0193-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch deleted file mode 100644 index aa338ea8fe..0000000000 --- a/SPECS/linux-lts/0193-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch +++ /dev/null @@ -1,157 +0,0 @@ -From 0ed3496b3f01c4dd2f8e63571a0b1aaddeb71419 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:16 +0800 -Subject: [PATCH 193/467] UPSTREAM: dt-bindings: display: add verisilicon,dc - -Verisilicon has a series of display controllers prefixed with DC and -with self-identification facility like their GC series GPUs. - -Add a device tree binding for it. - -Depends on the specific DC model, it can have either one or two display -outputs, and each display output could be set to DPI signal or "DP" -signal (which seems to be some plain parallel bus to HDMI controllers). - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Thomas Zimmermann -Link: https://patch.msgid.link/20260129023922.1527729-3-zhengxingda@iscas.ac.cn -(cherry picked from commit 5f6965fa1e2ec8ac69e1d448d343a528dc60cdfb) -Signed-off-by: Han Gao ---- - .../bindings/display/verisilicon,dc.yaml | 122 ++++++++++++++++++ - 1 file changed, 122 insertions(+) - create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml - -diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml -new file mode 100644 -index 000000000000..9dc35ab973f2 ---- /dev/null -+++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml -@@ -0,0 +1,122 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Verisilicon DC-series display controllers -+ -+maintainers: -+ - Icenowy Zheng -+ -+properties: -+ $nodename: -+ pattern: "^display@[0-9a-f]+$" -+ -+ compatible: -+ items: -+ - enum: -+ - thead,th1520-dc8200 -+ - const: verisilicon,dc # DC IPs have discoverable ID/revision registers -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: DC Core clock -+ - description: DMA AXI bus clock -+ - description: Configuration AHB bus clock -+ - description: Pixel clock of output 0 -+ - description: Pixel clock of output 1 -+ -+ clock-names: -+ items: -+ - const: core -+ - const: axi -+ - const: ahb -+ - const: pix0 -+ - const: pix1 -+ -+ resets: -+ items: -+ - description: DC Core reset -+ - description: DMA AXI bus reset -+ - description: Configuration AHB bus reset -+ -+ reset-names: -+ items: -+ - const: core -+ - const: axi -+ - const: ahb -+ -+ ports: -+ $ref: /schemas/graph.yaml#/properties/ports -+ -+ properties: -+ port@0: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: The first output channel , endpoint 0 should be -+ used for DPI format output and endpoint 1 should be used -+ for DP format output. -+ -+ port@1: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: The second output channel if the DC variant -+ supports. Follow the same endpoint addressing rule with -+ the first port. -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - clocks -+ - clock-names -+ - ports -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ display@ffef600000 { -+ compatible = "thead,th1520-dc8200", "verisilicon,dc"; -+ reg = <0xff 0xef600000 0x0 0x100000>; -+ interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_vo CLK_DPU_CCLK>, -+ <&clk_vo CLK_DPU_ACLK>, -+ <&clk_vo CLK_DPU_HCLK>, -+ <&clk_vo CLK_DPU_PIXELCLK0>, -+ <&clk_vo CLK_DPU_PIXELCLK1>; -+ clock-names = "core", "axi", "ahb", "pix0", "pix1"; -+ resets = <&rst TH1520_RESET_ID_DPU_CORE>, -+ <&rst TH1520_RESET_ID_DPU_AXI>, -+ <&rst TH1520_RESET_ID_DPU_AHB>; -+ reset-names = "core", "axi", "ahb"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dpu_out_dp1: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&hdmi_in>; -+ }; -+ }; -+ }; -+ }; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0194-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch b/SPECS/linux-lts/0194-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch deleted file mode 100644 index 8afe0ebfca..0000000000 --- a/SPECS/linux-lts/0194-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch +++ /dev/null @@ -1,2082 +0,0 @@ -From 8c4bdd8a532c94e0c03dff0c3191f51e6d57c008 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:17 +0800 -Subject: [PATCH 194/467] UPSTREAM: drm: verisilicon: add a driver for - Verisilicon display controllers - -This is a from-scratch driver targeting Verisilicon DC-series display -controllers, which feature self-identification functionality like their -GC-series GPUs. - -Only DC8200 is being supported now, and only the main framebuffer is set -up (as the DRM primary plane). Support for more DC models and more -features is my further targets. - -As the display controller is delivered to SoC vendors as a whole part, -this driver does not use component framework and extra bridges inside a -SoC is expected to be implemented as dedicated bridges (this driver -properly supports bridge chaining). - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Tested-by: Han Gao -Tested-by: Michal Wilczynski -Reviewed-by: Thomas Zimmermann -Signed-off-by: Thomas Zimmermann -Link: https://patch.msgid.link/20260129023922.1527729-4-zhengxingda@iscas.ac.cn -(cherry picked from commit dbf21777caa8b8c88c12f7f036b01208fec0d55a) -Signed-off-by: Han Gao ---- - MAINTAINERS | 7 + - drivers/gpu/drm/Kconfig | 2 + - drivers/gpu/drm/Makefile | 1 + - drivers/gpu/drm/verisilicon/Kconfig | 16 + - drivers/gpu/drm/verisilicon/Makefile | 5 + - drivers/gpu/drm/verisilicon/vs_bridge.c | 371 ++++++++++++++++++ - drivers/gpu/drm/verisilicon/vs_bridge.h | 39 ++ - drivers/gpu/drm/verisilicon/vs_bridge_regs.h | 54 +++ - drivers/gpu/drm/verisilicon/vs_crtc.c | 191 +++++++++ - drivers/gpu/drm/verisilicon/vs_crtc.h | 31 ++ - drivers/gpu/drm/verisilicon/vs_crtc_regs.h | 60 +++ - drivers/gpu/drm/verisilicon/vs_dc.c | 207 ++++++++++ - drivers/gpu/drm/verisilicon/vs_dc.h | 38 ++ - drivers/gpu/drm/verisilicon/vs_dc_top_regs.h | 27 ++ - drivers/gpu/drm/verisilicon/vs_drm.c | 182 +++++++++ - drivers/gpu/drm/verisilicon/vs_drm.h | 28 ++ - drivers/gpu/drm/verisilicon/vs_hwdb.c | 150 +++++++ - drivers/gpu/drm/verisilicon/vs_hwdb.h | 29 ++ - drivers/gpu/drm/verisilicon/vs_plane.c | 124 ++++++ - drivers/gpu/drm/verisilicon/vs_plane.h | 72 ++++ - .../gpu/drm/verisilicon/vs_primary_plane.c | 173 ++++++++ - .../drm/verisilicon/vs_primary_plane_regs.h | 53 +++ - 22 files changed, 1860 insertions(+) - create mode 100644 drivers/gpu/drm/verisilicon/Kconfig - create mode 100644 drivers/gpu/drm/verisilicon/Makefile - create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge_regs.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc_regs.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_dc.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_dc.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_top_regs.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_drm.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_drm.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_hwdb.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_hwdb.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.h - create mode 100644 drivers/gpu/drm/verisilicon/vs_primary_plane.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h - -diff --git a/MAINTAINERS b/MAINTAINERS -index a615f46a6e8d..b50b6c7a9b52 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -8546,6 +8546,13 @@ F: Documentation/devicetree/bindings/display/brcm,bcm2835-*.yaml - F: drivers/gpu/drm/vc4/ - F: include/uapi/drm/vc4_drm.h - -+DRM DRIVERS FOR VERISILICON DISPLAY CONTROLLER IP -+M: Icenowy Zheng -+L: dri-devel@lists.freedesktop.org -+S: Maintained -+F: Documentation/devicetree/bindings/display/verisilicon,dc.yaml -+F: drivers/gpu/drm/verisilicon/ -+ - DRM DRIVERS FOR VIVANTE GPU IP - M: Lucas Stach - R: Russell King -diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig -index ed85d0ceee3b..a0917595d11c 100644 ---- a/drivers/gpu/drm/Kconfig -+++ b/drivers/gpu/drm/Kconfig -@@ -398,6 +398,8 @@ source "drivers/gpu/drm/imagination/Kconfig" - - source "drivers/gpu/drm/tyr/Kconfig" - -+source "drivers/gpu/drm/verisilicon/Kconfig" -+ - config DRM_HYPERV - tristate "DRM Support for Hyper-V synthetic video device" - depends on DRM && PCI && HYPERV_VMBUS -diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile -index b248e64587ed..90eb61d3a823 100644 ---- a/drivers/gpu/drm/Makefile -+++ b/drivers/gpu/drm/Makefile -@@ -235,6 +235,7 @@ obj-y += solomon/ - obj-$(CONFIG_DRM_SPRD) += sprd/ - obj-$(CONFIG_DRM_LOONGSON) += loongson/ - obj-$(CONFIG_DRM_POWERVR) += imagination/ -+obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon/ - - # Ensure drm headers are self-contained and pass kernel-doc - hdrtest-files := \ -diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisilicon/Kconfig -new file mode 100644 -index 000000000000..7cce86ec8603 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/Kconfig -@@ -0,0 +1,16 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+config DRM_VERISILICON_DC -+ tristate "DRM Support for Verisilicon DC-series display controllers" -+ depends on DRM && COMMON_CLK -+ depends on RISCV || COMPILE_TEST -+ select DRM_BRIDGE_CONNECTOR -+ select DRM_CLIENT_SELECTION -+ select DRM_DISPLAY_HELPER -+ select DRM_GEM_DMA_HELPER -+ select DRM_KMS_HELPER -+ select REGMAP_MMIO -+ select VIDEOMODE_HELPERS -+ help -+ Choose this option if you have a SoC with Verisilicon DC-series -+ display controllers. If M is selected, the module will be called -+ verisilicon-dc. -diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile -new file mode 100644 -index 000000000000..fd8d805fbcde ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/Makefile -@@ -0,0 +1,5 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o -+ -+obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o -diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.c b/drivers/gpu/drm/verisilicon/vs_bridge.c -new file mode 100644 -index 000000000000..2a0ad00a94d6 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_bridge.c -@@ -0,0 +1,371 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vs_bridge.h" -+#include "vs_bridge_regs.h" -+#include "vs_crtc.h" -+#include "vs_dc.h" -+ -+static int vs_bridge_attach(struct drm_bridge *bridge, -+ struct drm_encoder *encoder, -+ enum drm_bridge_attach_flags flags) -+{ -+ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); -+ -+ return drm_bridge_attach(encoder, vbridge->next_bridge, -+ bridge, flags); -+} -+ -+struct vsdc_dp_format { -+ u32 linux_fmt; -+ bool is_yuv; -+ u32 vsdc_fmt; -+}; -+ -+static struct vsdc_dp_format vsdc_dp_supported_fmts[] = { -+ /* default to RGB888 */ -+ { MEDIA_BUS_FMT_FIXED, false, VSDC_DISP_DP_CONFIG_FMT_RGB888 }, -+ { MEDIA_BUS_FMT_RGB888_1X24, false, VSDC_DISP_DP_CONFIG_FMT_RGB888 }, -+ { MEDIA_BUS_FMT_RGB565_1X16, false, VSDC_DISP_DP_CONFIG_FMT_RGB565 }, -+ { MEDIA_BUS_FMT_RGB666_1X18, false, VSDC_DISP_DP_CONFIG_FMT_RGB666 }, -+ { MEDIA_BUS_FMT_RGB101010_1X30, -+ false, VSDC_DISP_DP_CONFIG_FMT_RGB101010 }, -+ { MEDIA_BUS_FMT_UYVY8_1X16, true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY8 }, -+ { MEDIA_BUS_FMT_UYVY10_1X20, true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY10 }, -+ { MEDIA_BUS_FMT_YUV8_1X24, true, VSDC_DISP_DP_CONFIG_YUV_FMT_YUV8 }, -+ { MEDIA_BUS_FMT_YUV10_1X30, true, VSDC_DISP_DP_CONFIG_YUV_FMT_YUV10 }, -+ { MEDIA_BUS_FMT_UYYVYY8_0_5X24, -+ true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY8 }, -+ { MEDIA_BUS_FMT_UYYVYY10_0_5X30, -+ true, VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY10 }, -+}; -+ -+static u32 *vs_bridge_atomic_get_output_bus_fmts_dpi(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ unsigned int *num_output_fmts) -+{ -+ u32 *output_fmts; -+ -+ *num_output_fmts = 2; -+ -+ output_fmts = kcalloc(*num_output_fmts, sizeof(*output_fmts), -+ GFP_KERNEL); -+ if (!output_fmts) -+ return NULL; -+ -+ /* TODO: support more DPI output formats */ -+ output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; -+ output_fmts[1] = MEDIA_BUS_FMT_FIXED; -+ -+ return output_fmts; -+} -+ -+static u32 *vs_bridge_atomic_get_output_bus_fmts_dp(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ unsigned int *num_output_fmts) -+{ -+ u32 *output_fmts; -+ unsigned int i; -+ -+ *num_output_fmts = ARRAY_SIZE(vsdc_dp_supported_fmts); -+ -+ output_fmts = kcalloc(*num_output_fmts, sizeof(*output_fmts), -+ GFP_KERNEL); -+ if (!output_fmts) -+ return NULL; -+ -+ for (i = 0; i < *num_output_fmts; i++) -+ output_fmts[i] = vsdc_dp_supported_fmts[i].linux_fmt; -+ -+ return output_fmts; -+} -+ -+static bool vs_bridge_out_dp_fmt_supported(u32 out_fmt) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(vsdc_dp_supported_fmts); i++) -+ if (vsdc_dp_supported_fmts[i].linux_fmt == out_fmt) -+ return true; -+ -+ return false; -+} -+ -+static u32 *vs_bridge_atomic_get_input_bus_fmts_dp(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ u32 output_fmt, -+ unsigned int *num_input_fmts) -+{ -+ if (!vs_bridge_out_dp_fmt_supported(output_fmt)) { -+ *num_input_fmts = 0; -+ return NULL; -+ } -+ -+ return drm_atomic_helper_bridge_propagate_bus_fmt(bridge, bridge_state, -+ crtc_state, -+ conn_state, -+ output_fmt, -+ num_input_fmts); -+} -+ -+static int vs_bridge_atomic_check_dp(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state) -+{ -+ if (!vs_bridge_out_dp_fmt_supported(bridge_state->output_bus_cfg.format)) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static void vs_bridge_enable_common(struct vs_crtc *crtc, -+ struct drm_bridge_state *br_state) -+{ -+ struct vs_dc *dc = crtc->dc; -+ unsigned int output = crtc->id; -+ -+ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_DAT_POL); -+ regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_DE_POL, -+ br_state->output_bus_cfg.flags & -+ DRM_BUS_FLAG_DE_LOW); -+ regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_CLK_POL, -+ br_state->output_bus_cfg.flags & -+ DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); -+ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_DE_EN | -+ VSDC_DISP_PANEL_CONFIG_DAT_EN | -+ VSDC_DISP_PANEL_CONFIG_CLK_EN); -+ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_RUNNING); -+ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, -+ VSDC_DISP_PANEL_START_MULTI_DISP_SYNC); -+ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_START, -+ VSDC_DISP_PANEL_START_RUNNING(output)); -+ -+ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), -+ VSDC_DISP_PANEL_CONFIG_EX_COMMIT); -+} -+ -+static void vs_bridge_atomic_enable_dpi(struct drm_bridge *bridge, -+ struct drm_atomic_state *state) -+{ -+ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); -+ struct drm_bridge_state *br_state = -+ drm_atomic_get_new_bridge_state(state, bridge); -+ struct vs_crtc *crtc = vbridge->crtc; -+ struct vs_dc *dc = crtc->dc; -+ unsigned int output = crtc->id; -+ -+ regmap_clear_bits(dc->regs, VSDC_DISP_DP_CONFIG(output), -+ VSDC_DISP_DP_CONFIG_DP_EN); -+ regmap_write(dc->regs, VSDC_DISP_DPI_CONFIG(output), -+ VSDC_DISP_DPI_CONFIG_FMT_RGB888); -+ -+ vs_bridge_enable_common(crtc, br_state); -+} -+ -+static void vs_bridge_atomic_enable_dp(struct drm_bridge *bridge, -+ struct drm_atomic_state *state) -+{ -+ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); -+ struct drm_bridge_state *br_state = -+ drm_atomic_get_new_bridge_state(state, bridge); -+ struct vs_crtc *crtc = vbridge->crtc; -+ struct vs_dc *dc = crtc->dc; -+ unsigned int output = crtc->id; -+ u32 dp_fmt; -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(vsdc_dp_supported_fmts); i++) { -+ if (vsdc_dp_supported_fmts[i].linux_fmt == -+ br_state->output_bus_cfg.format) -+ break; -+ } -+ if (WARN_ON_ONCE(i == ARRAY_SIZE(vsdc_dp_supported_fmts))) -+ return; -+ dp_fmt = vsdc_dp_supported_fmts[i].vsdc_fmt; -+ dp_fmt |= VSDC_DISP_DP_CONFIG_DP_EN; -+ regmap_write(dc->regs, VSDC_DISP_DP_CONFIG(output), dp_fmt); -+ regmap_assign_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_YUV, -+ vsdc_dp_supported_fmts[i].is_yuv); -+ -+ vs_bridge_enable_common(crtc, br_state); -+} -+ -+static void vs_bridge_atomic_disable(struct drm_bridge *bridge, -+ struct drm_atomic_state *state) -+{ -+ struct vs_bridge *vbridge = drm_bridge_to_vs_bridge(bridge); -+ struct vs_crtc *crtc = vbridge->crtc; -+ struct vs_dc *dc = crtc->dc; -+ unsigned int output = crtc->id; -+ -+ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_START, -+ VSDC_DISP_PANEL_START_MULTI_DISP_SYNC | -+ VSDC_DISP_PANEL_START_RUNNING(output)); -+ regmap_clear_bits(dc->regs, VSDC_DISP_PANEL_CONFIG(output), -+ VSDC_DISP_PANEL_CONFIG_RUNNING); -+ -+ regmap_set_bits(dc->regs, VSDC_DISP_PANEL_CONFIG_EX(crtc->id), -+ VSDC_DISP_PANEL_CONFIG_EX_COMMIT); -+} -+ -+static const struct drm_bridge_funcs vs_dpi_bridge_funcs = { -+ .attach = vs_bridge_attach, -+ .atomic_enable = vs_bridge_atomic_enable_dpi, -+ .atomic_disable = vs_bridge_atomic_disable, -+ .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt, -+ .atomic_get_output_bus_fmts = vs_bridge_atomic_get_output_bus_fmts_dpi, -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_reset = drm_atomic_helper_bridge_reset, -+}; -+ -+static const struct drm_bridge_funcs vs_dp_bridge_funcs = { -+ .attach = vs_bridge_attach, -+ .atomic_enable = vs_bridge_atomic_enable_dp, -+ .atomic_disable = vs_bridge_atomic_disable, -+ .atomic_check = vs_bridge_atomic_check_dp, -+ .atomic_get_input_bus_fmts = vs_bridge_atomic_get_input_bus_fmts_dp, -+ .atomic_get_output_bus_fmts = vs_bridge_atomic_get_output_bus_fmts_dp, -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_reset = drm_atomic_helper_bridge_reset, -+}; -+ -+static int vs_bridge_detect_output_interface(struct device_node *of_node, -+ unsigned int output) -+{ -+ int ret; -+ struct device_node *remote; -+ -+ remote = of_graph_get_remote_node(of_node, output, -+ VSDC_OUTPUT_INTERFACE_DPI); -+ if (remote) { -+ ret = VSDC_OUTPUT_INTERFACE_DPI; -+ } else { -+ remote = of_graph_get_remote_node(of_node, output, -+ VSDC_OUTPUT_INTERFACE_DP); -+ if (remote) -+ ret = VSDC_OUTPUT_INTERFACE_DP; -+ else -+ ret = -ENODEV; -+ } -+ -+ if (remote) -+ of_node_put(remote); -+ -+ return ret; -+} -+ -+struct vs_bridge *vs_bridge_init(struct drm_device *drm_dev, -+ struct vs_crtc *crtc) -+{ -+ unsigned int output = crtc->id; -+ struct vs_bridge *bridge; -+ struct drm_bridge *next; -+ enum vs_bridge_output_interface intf; -+ const struct drm_bridge_funcs *bridge_funcs; -+ int ret, enctype; -+ -+ intf = vs_bridge_detect_output_interface(drm_dev->dev->of_node, -+ output); -+ if (intf == -ENODEV) { -+ drm_dbg(drm_dev, "Skipping output %u\n", output); -+ return NULL; -+ } -+ -+ next = devm_drm_of_get_bridge(drm_dev->dev, drm_dev->dev->of_node, -+ output, intf); -+ if (IS_ERR(next)) { -+ ret = PTR_ERR(next); -+ if (ret != -EPROBE_DEFER) -+ drm_err(drm_dev, -+ "Cannot get downstream bridge of output %u\n", -+ output); -+ return ERR_PTR(ret); -+ } -+ -+ if (intf == VSDC_OUTPUT_INTERFACE_DPI) -+ bridge_funcs = &vs_dpi_bridge_funcs; -+ else -+ bridge_funcs = &vs_dp_bridge_funcs; -+ -+ bridge = devm_drm_bridge_alloc(drm_dev->dev, struct vs_bridge, base, -+ bridge_funcs); -+ if (IS_ERR(bridge)) -+ return ERR_PTR(PTR_ERR(bridge)); -+ -+ bridge->crtc = crtc; -+ bridge->intf = intf; -+ bridge->next_bridge = next; -+ -+ if (intf == VSDC_OUTPUT_INTERFACE_DPI) -+ enctype = DRM_MODE_ENCODER_DPI; -+ else -+ enctype = DRM_MODE_ENCODER_NONE; -+ -+ bridge->enc = drmm_plain_encoder_alloc(drm_dev, NULL, enctype, NULL); -+ if (IS_ERR(bridge->enc)) { -+ drm_err(drm_dev, -+ "Cannot initialize encoder for output %u\n", output); -+ ret = PTR_ERR(bridge->enc); -+ return ERR_PTR(ret); -+ } -+ -+ bridge->enc->possible_crtcs = drm_crtc_mask(&crtc->base); -+ -+ ret = devm_drm_bridge_add(drm_dev->dev, &bridge->base); -+ if (ret) { -+ drm_err(drm_dev, -+ "Cannot add bridge for output %u\n", output); -+ return ERR_PTR(ret); -+ } -+ -+ ret = drm_bridge_attach(bridge->enc, &bridge->base, NULL, -+ DRM_BRIDGE_ATTACH_NO_CONNECTOR); -+ if (ret) { -+ drm_err(drm_dev, -+ "Cannot attach bridge for output %u\n", output); -+ return ERR_PTR(ret); -+ } -+ -+ bridge->conn = drm_bridge_connector_init(drm_dev, bridge->enc); -+ if (IS_ERR(bridge->conn)) { -+ drm_err(drm_dev, -+ "Cannot create connector for output %u\n", output); -+ ret = PTR_ERR(bridge->conn); -+ return ERR_PTR(ret); -+ } -+ drm_connector_attach_encoder(bridge->conn, bridge->enc); -+ -+ return bridge; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_bridge.h b/drivers/gpu/drm/verisilicon/vs_bridge.h -new file mode 100644 -index 000000000000..70fee1749699 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_bridge.h -@@ -0,0 +1,39 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#ifndef _VS_BRIDGE_H_ -+#define _VS_BRIDGE_H_ -+ -+#include -+ -+#include -+#include -+#include -+ -+struct vs_crtc; -+ -+enum vs_bridge_output_interface { -+ VSDC_OUTPUT_INTERFACE_DPI = 0, -+ VSDC_OUTPUT_INTERFACE_DP = 1 -+}; -+ -+struct vs_bridge { -+ struct drm_bridge base; -+ struct drm_encoder *enc; -+ struct drm_connector *conn; -+ -+ struct vs_crtc *crtc; -+ struct drm_bridge *next_bridge; -+ enum vs_bridge_output_interface intf; -+}; -+ -+static inline struct vs_bridge *drm_bridge_to_vs_bridge(struct drm_bridge *bridge) -+{ -+ return container_of(bridge, struct vs_bridge, base); -+} -+ -+struct vs_bridge *vs_bridge_init(struct drm_device *drm_dev, -+ struct vs_crtc *crtc); -+#endif /* _VS_BRIDGE_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_bridge_regs.h b/drivers/gpu/drm/verisilicon/vs_bridge_regs.h -new file mode 100644 -index 000000000000..9eb30e4564be ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_bridge_regs.h -@@ -0,0 +1,54 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_BRIDGE_REGS_H_ -+#define _VS_BRIDGE_REGS_H_ -+ -+#include -+ -+#define VSDC_DISP_PANEL_CONFIG(n) (0x1418 + 0x4 * (n)) -+#define VSDC_DISP_PANEL_CONFIG_DE_EN BIT(0) -+#define VSDC_DISP_PANEL_CONFIG_DE_POL BIT(1) -+#define VSDC_DISP_PANEL_CONFIG_DAT_EN BIT(4) -+#define VSDC_DISP_PANEL_CONFIG_DAT_POL BIT(5) -+#define VSDC_DISP_PANEL_CONFIG_CLK_EN BIT(8) -+#define VSDC_DISP_PANEL_CONFIG_CLK_POL BIT(9) -+#define VSDC_DISP_PANEL_CONFIG_RUNNING BIT(12) -+#define VSDC_DISP_PANEL_CONFIG_GAMMA BIT(13) -+#define VSDC_DISP_PANEL_CONFIG_YUV BIT(16) -+ -+#define VSDC_DISP_DPI_CONFIG(n) (0x14B8 + 0x4 * (n)) -+#define VSDC_DISP_DPI_CONFIG_FMT_MASK GENMASK(2, 0) -+#define VSDC_DISP_DPI_CONFIG_FMT_RGB565 (0) -+#define VSDC_DISP_DPI_CONFIG_FMT_RGB666 (3) -+#define VSDC_DISP_DPI_CONFIG_FMT_RGB888 (5) -+#define VSDC_DISP_DPI_CONFIG_FMT_RGB101010 (6) -+ -+#define VSDC_DISP_PANEL_START 0x1CCC -+#define VSDC_DISP_PANEL_START_RUNNING(n) BIT(n) -+#define VSDC_DISP_PANEL_START_MULTI_DISP_SYNC BIT(3) -+ -+#define VSDC_DISP_DP_CONFIG(n) (0x1CD0 + 0x4 * (n)) -+#define VSDC_DISP_DP_CONFIG_DP_EN BIT(3) -+#define VSDC_DISP_DP_CONFIG_FMT_MASK GENMASK(2, 0) -+#define VSDC_DISP_DP_CONFIG_FMT_RGB565 (0) -+#define VSDC_DISP_DP_CONFIG_FMT_RGB666 (1) -+#define VSDC_DISP_DP_CONFIG_FMT_RGB888 (2) -+#define VSDC_DISP_DP_CONFIG_FMT_RGB101010 (3) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_MASK GENMASK(7, 4) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY8 (2 << 4) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_YUV8 (4 << 4) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYVY10 (8 << 4) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_YUV10 (10 << 4) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY8 (12 << 4) -+#define VSDC_DISP_DP_CONFIG_YUV_FMT_UYYVYY10 (13 << 4) -+ -+#define VSDC_DISP_PANEL_CONFIG_EX(n) (0x2518 + 0x4 * (n)) -+#define VSDC_DISP_PANEL_CONFIG_EX_COMMIT BIT(0) -+ -+#endif /* _VS_BRIDGE_REGS_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisilicon/vs_crtc.c -new file mode 100644 -index 000000000000..f49401713000 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_crtc.c -@@ -0,0 +1,191 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "vs_crtc_regs.h" -+#include "vs_crtc.h" -+#include "vs_dc.h" -+#include "vs_dc_top_regs.h" -+#include "vs_drm.h" -+#include "vs_plane.h" -+ -+static void vs_crtc_atomic_disable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ unsigned int output = vcrtc->id; -+ -+ drm_crtc_vblank_off(crtc); -+ -+ clk_disable_unprepare(dc->pix_clk[output]); -+} -+ -+static void vs_crtc_atomic_enable(struct drm_crtc *crtc, -+ struct drm_atomic_state *state) -+{ -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ unsigned int output = vcrtc->id; -+ -+ drm_WARN_ON(&dc->drm_dev->base, -+ clk_prepare_enable(dc->pix_clk[output])); -+ -+ drm_crtc_vblank_on(crtc); -+} -+ -+static void vs_crtc_mode_set_nofb(struct drm_crtc *crtc) -+{ -+ struct drm_display_mode *mode = &crtc->state->adjusted_mode; -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ unsigned int output = vcrtc->id; -+ -+ regmap_write(dc->regs, VSDC_DISP_HSIZE(output), -+ VSDC_DISP_HSIZE_DISP(mode->hdisplay) | -+ VSDC_DISP_HSIZE_TOTAL(mode->htotal)); -+ regmap_write(dc->regs, VSDC_DISP_VSIZE(output), -+ VSDC_DISP_VSIZE_DISP(mode->vdisplay) | -+ VSDC_DISP_VSIZE_TOTAL(mode->vtotal)); -+ regmap_write(dc->regs, VSDC_DISP_HSYNC(output), -+ VSDC_DISP_HSYNC_START(mode->hsync_start) | -+ VSDC_DISP_HSYNC_END(mode->hsync_end) | -+ VSDC_DISP_HSYNC_EN); -+ if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) -+ regmap_set_bits(dc->regs, VSDC_DISP_HSYNC(output), -+ VSDC_DISP_HSYNC_POL); -+ regmap_write(dc->regs, VSDC_DISP_VSYNC(output), -+ VSDC_DISP_VSYNC_START(mode->vsync_start) | -+ VSDC_DISP_VSYNC_END(mode->vsync_end) | -+ VSDC_DISP_VSYNC_EN); -+ if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) -+ regmap_set_bits(dc->regs, VSDC_DISP_VSYNC(output), -+ VSDC_DISP_VSYNC_POL); -+ -+ WARN_ON(clk_set_rate(dc->pix_clk[output], mode->crtc_clock * 1000)); -+} -+ -+static enum drm_mode_status -+vs_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) -+{ -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ unsigned int output = vcrtc->id; -+ long rate; -+ -+ if (mode->htotal > VSDC_DISP_TIMING_VALUE_MAX) -+ return MODE_BAD_HVALUE; -+ if (mode->vtotal > VSDC_DISP_TIMING_VALUE_MAX) -+ return MODE_BAD_VVALUE; -+ -+ rate = clk_round_rate(dc->pix_clk[output], mode->clock * HZ_PER_KHZ); -+ if (rate <= 0) -+ return MODE_CLOCK_RANGE; -+ -+ return MODE_OK; -+} -+ -+static bool vs_crtc_mode_fixup(struct drm_crtc *crtc, -+ const struct drm_display_mode *m, -+ struct drm_display_mode *adjusted_mode) -+{ -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ unsigned int output = vcrtc->id; -+ long clk_rate; -+ -+ drm_mode_set_crtcinfo(adjusted_mode, 0); -+ -+ /* Feedback the pixel clock to crtc_clock */ -+ clk_rate = adjusted_mode->crtc_clock * HZ_PER_KHZ; -+ clk_rate = clk_round_rate(dc->pix_clk[output], clk_rate); -+ if (clk_rate <= 0) -+ return false; -+ -+ adjusted_mode->crtc_clock = clk_rate / HZ_PER_KHZ; -+ -+ return true; -+} -+ -+static const struct drm_crtc_helper_funcs vs_crtc_helper_funcs = { -+ .atomic_flush = drm_crtc_vblank_atomic_flush, -+ .atomic_enable = vs_crtc_atomic_enable, -+ .atomic_disable = vs_crtc_atomic_disable, -+ .mode_set_nofb = vs_crtc_mode_set_nofb, -+ .mode_valid = vs_crtc_mode_valid, -+ .mode_fixup = vs_crtc_mode_fixup, -+}; -+ -+static int vs_crtc_enable_vblank(struct drm_crtc *crtc) -+{ -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_set_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id)); -+ -+ return 0; -+} -+ -+static void vs_crtc_disable_vblank(struct drm_crtc *crtc) -+{ -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_clear_bits(dc->regs, VSDC_TOP_IRQ_EN, VSDC_TOP_IRQ_VSYNC(vcrtc->id)); -+} -+ -+static const struct drm_crtc_funcs vs_crtc_funcs = { -+ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, -+ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, -+ .page_flip = drm_atomic_helper_page_flip, -+ .reset = drm_atomic_helper_crtc_reset, -+ .set_config = drm_atomic_helper_set_config, -+ .enable_vblank = vs_crtc_enable_vblank, -+ .disable_vblank = vs_crtc_disable_vblank, -+}; -+ -+struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, -+ unsigned int output) -+{ -+ struct vs_crtc *vcrtc; -+ struct drm_plane *primary; -+ int ret; -+ -+ vcrtc = drmm_kzalloc(drm_dev, sizeof(*vcrtc), GFP_KERNEL); -+ if (!vcrtc) -+ return ERR_PTR(-ENOMEM); -+ vcrtc->dc = dc; -+ vcrtc->id = output; -+ -+ /* Create our primary plane */ -+ primary = vs_primary_plane_init(drm_dev, dc); -+ if (IS_ERR(primary)) { -+ drm_err(drm_dev, "Couldn't create the primary plane\n"); -+ return ERR_PTR(PTR_ERR(primary)); -+ } -+ -+ ret = drmm_crtc_init_with_planes(drm_dev, &vcrtc->base, -+ primary, -+ NULL, -+ &vs_crtc_funcs, -+ NULL); -+ if (ret) { -+ drm_err(drm_dev, "Couldn't initialize CRTC\n"); -+ return ERR_PTR(ret); -+ } -+ -+ drm_crtc_helper_add(&vcrtc->base, &vs_crtc_helper_funcs); -+ -+ return vcrtc; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.h b/drivers/gpu/drm/verisilicon/vs_crtc.h -new file mode 100644 -index 000000000000..b45580bd99b3 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_crtc.h -@@ -0,0 +1,31 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#ifndef _VS_CRTC_H_ -+#define _VS_CRTC_H_ -+ -+#include -+#include -+ -+#define VSDC_DISP_TIMING_VALUE_MAX BIT_MASK(15) -+ -+struct vs_dc; -+ -+struct vs_crtc { -+ struct drm_crtc base; -+ -+ struct vs_dc *dc; -+ unsigned int id; -+}; -+ -+static inline struct vs_crtc *drm_crtc_to_vs_crtc(struct drm_crtc *crtc) -+{ -+ return container_of(crtc, struct vs_crtc, base); -+} -+ -+struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, -+ unsigned int output); -+ -+#endif /* _VS_CRTC_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h -new file mode 100644 -index 000000000000..c7930e817635 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h -@@ -0,0 +1,60 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_CRTC_REGS_H_ -+#define _VS_CRTC_REGS_H_ -+ -+#include -+ -+#define VSDC_DISP_DITHER_CONFIG(n) (0x1410 + 0x4 * (n)) -+ -+#define VSDC_DISP_DITHER_TABLE_LOW(n) (0x1420 + 0x4 * (n)) -+#define VSDC_DISP_DITHER_TABLE_LOW_DEFAULT 0x7B48F3C0 -+ -+#define VSDC_DISP_DITHER_TABLE_HIGH(n) (0x1428 + 0x4 * (n)) -+#define VSDC_DISP_DITHER_TABLE_HIGH_DEFAULT 0x596AD1E2 -+ -+#define VSDC_DISP_HSIZE(n) (0x1430 + 0x4 * (n)) -+#define VSDC_DISP_HSIZE_DISP_MASK GENMASK(14, 0) -+#define VSDC_DISP_HSIZE_DISP(v) ((v) << 0) -+#define VSDC_DISP_HSIZE_TOTAL_MASK GENMASK(30, 16) -+#define VSDC_DISP_HSIZE_TOTAL(v) ((v) << 16) -+ -+#define VSDC_DISP_HSYNC(n) (0x1438 + 0x4 * (n)) -+#define VSDC_DISP_HSYNC_START_MASK GENMASK(14, 0) -+#define VSDC_DISP_HSYNC_START(v) ((v) << 0) -+#define VSDC_DISP_HSYNC_END_MASK GENMASK(29, 15) -+#define VSDC_DISP_HSYNC_END(v) ((v) << 15) -+#define VSDC_DISP_HSYNC_EN BIT(30) -+#define VSDC_DISP_HSYNC_POL BIT(31) -+ -+#define VSDC_DISP_VSIZE(n) (0x1440 + 0x4 * (n)) -+#define VSDC_DISP_VSIZE_DISP_MASK GENMASK(14, 0) -+#define VSDC_DISP_VSIZE_DISP(v) ((v) << 0) -+#define VSDC_DISP_VSIZE_TOTAL_MASK GENMASK(30, 16) -+#define VSDC_DISP_VSIZE_TOTAL(v) ((v) << 16) -+ -+#define VSDC_DISP_VSYNC(n) (0x1448 + 0x4 * (n)) -+#define VSDC_DISP_VSYNC_START_MASK GENMASK(14, 0) -+#define VSDC_DISP_VSYNC_START(v) ((v) << 0) -+#define VSDC_DISP_VSYNC_END_MASK GENMASK(29, 15) -+#define VSDC_DISP_VSYNC_END(v) ((v) << 15) -+#define VSDC_DISP_VSYNC_EN BIT(30) -+#define VSDC_DISP_VSYNC_POL BIT(31) -+ -+#define VSDC_DISP_CURRENT_LOCATION(n) (0x1450 + 0x4 * (n)) -+ -+#define VSDC_DISP_GAMMA_INDEX(n) (0x1458 + 0x4 * (n)) -+ -+#define VSDC_DISP_GAMMA_DATA(n) (0x1460 + 0x4 * (n)) -+ -+#define VSDC_DISP_IRQ_STA 0x147C -+ -+#define VSDC_DISP_IRQ_EN 0x1480 -+ -+#endif /* _VS_CRTC_REGS_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c -new file mode 100644 -index 000000000000..ba1b3f261a3a ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_dc.c -@@ -0,0 +1,207 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "vs_crtc.h" -+#include "vs_dc.h" -+#include "vs_dc_top_regs.h" -+#include "vs_drm.h" -+#include "vs_hwdb.h" -+ -+static const struct regmap_config vs_dc_regmap_cfg = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = sizeof(u32), -+ /* VSDC_OVL_CONFIG_EX(1) */ -+ .max_register = 0x2544, -+}; -+ -+static const struct of_device_id vs_dc_driver_dt_match[] = { -+ { .compatible = "verisilicon,dc" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, vs_dc_driver_dt_match); -+ -+static irqreturn_t vs_dc_irq_handler(int irq, void *private) -+{ -+ struct vs_dc *dc = private; -+ u32 irqs; -+ -+ regmap_read(dc->regs, VSDC_TOP_IRQ_ACK, &irqs); -+ -+ vs_drm_handle_irq(dc, irqs); -+ -+ return IRQ_HANDLED; -+} -+ -+static int vs_dc_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct vs_dc *dc; -+ void __iomem *regs; -+ unsigned int port_count, i; -+ /* pix0/pix1 */ -+ char pixclk_name[5]; -+ int irq, ret; -+ -+ if (!dev->of_node) { -+ dev_err(dev, "can't find DC devices\n"); -+ return -ENODEV; -+ } -+ -+ port_count = of_graph_get_port_count(dev->of_node); -+ if (!port_count) { -+ dev_err(dev, "can't find DC downstream ports\n"); -+ return -ENODEV; -+ } -+ if (port_count > VSDC_MAX_OUTPUTS) { -+ dev_err(dev, "too many DC downstream ports than possible\n"); -+ return -EINVAL; -+ } -+ -+ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); -+ if (ret) { -+ dev_err(dev, "No suitable DMA available\n"); -+ return ret; -+ } -+ -+ dc = devm_kzalloc(dev, sizeof(*dc), GFP_KERNEL); -+ if (!dc) -+ return -ENOMEM; -+ -+ dc->rsts[0].id = "core"; -+ dc->rsts[1].id = "axi"; -+ dc->rsts[2].id = "ahb"; -+ -+ ret = devm_reset_control_bulk_get_optional_shared(dev, VSDC_RESET_COUNT, -+ dc->rsts); -+ if (ret) { -+ dev_err(dev, "can't get reset lines\n"); -+ return ret; -+ } -+ -+ dc->core_clk = devm_clk_get_enabled(dev, "core"); -+ if (IS_ERR(dc->core_clk)) { -+ dev_err(dev, "can't get core clock\n"); -+ return PTR_ERR(dc->core_clk); -+ } -+ -+ dc->axi_clk = devm_clk_get_enabled(dev, "axi"); -+ if (IS_ERR(dc->axi_clk)) { -+ dev_err(dev, "can't get axi clock\n"); -+ return PTR_ERR(dc->axi_clk); -+ } -+ -+ dc->ahb_clk = devm_clk_get_enabled(dev, "ahb"); -+ if (IS_ERR(dc->ahb_clk)) { -+ dev_err(dev, "can't get ahb clock\n"); -+ return PTR_ERR(dc->ahb_clk); -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) { -+ dev_err(dev, "can't get irq\n"); -+ return irq; -+ } -+ -+ ret = reset_control_bulk_deassert(VSDC_RESET_COUNT, dc->rsts); -+ if (ret) { -+ dev_err(dev, "can't deassert reset lines\n"); -+ return ret; -+ } -+ -+ regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(regs)) { -+ dev_err(dev, "can't map registers"); -+ ret = PTR_ERR(regs); -+ goto err_rst_assert; -+ } -+ -+ dc->regs = devm_regmap_init_mmio(dev, regs, &vs_dc_regmap_cfg); -+ if (IS_ERR(dc->regs)) { -+ ret = PTR_ERR(dc->regs); -+ goto err_rst_assert; -+ } -+ -+ ret = vs_fill_chip_identity(dc->regs, &dc->identity); -+ if (ret) -+ goto err_rst_assert; -+ -+ dev_info(dev, "Found DC%x rev %x customer %x\n", dc->identity.model, -+ dc->identity.revision, dc->identity.customer_id); -+ -+ if (port_count > dc->identity.display_count) { -+ dev_err(dev, "too many downstream ports than HW capability\n"); -+ ret = -EINVAL; -+ goto err_rst_assert; -+ } -+ -+ for (i = 0; i < dc->identity.display_count; i++) { -+ snprintf(pixclk_name, sizeof(pixclk_name), "pix%u", i); -+ dc->pix_clk[i] = devm_clk_get(dev, pixclk_name); -+ if (IS_ERR(dc->pix_clk[i])) { -+ dev_err(dev, "can't get pixel clk %u\n", i); -+ ret = PTR_ERR(dc->pix_clk[i]); -+ goto err_rst_assert; -+ } -+ } -+ -+ ret = devm_request_irq(dev, irq, vs_dc_irq_handler, 0, -+ dev_name(dev), dc); -+ if (ret) { -+ dev_err(dev, "can't request irq\n"); -+ goto err_rst_assert; -+ } -+ -+ dev_set_drvdata(dev, dc); -+ -+ ret = vs_drm_initialize(dc, pdev); -+ if (ret) -+ goto err_rst_assert; -+ -+ return 0; -+ -+err_rst_assert: -+ reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); -+ return ret; -+} -+ -+static void vs_dc_remove(struct platform_device *pdev) -+{ -+ struct vs_dc *dc = dev_get_drvdata(&pdev->dev); -+ -+ vs_drm_finalize(dc); -+ -+ dev_set_drvdata(&pdev->dev, NULL); -+ -+ reset_control_bulk_assert(VSDC_RESET_COUNT, dc->rsts); -+} -+ -+static void vs_dc_shutdown(struct platform_device *pdev) -+{ -+ struct vs_dc *dc = dev_get_drvdata(&pdev->dev); -+ -+ vs_drm_shutdown_handler(dc); -+} -+ -+struct platform_driver vs_dc_platform_driver = { -+ .probe = vs_dc_probe, -+ .remove = vs_dc_remove, -+ .shutdown = vs_dc_shutdown, -+ .driver = { -+ .name = "verisilicon-dc", -+ .of_match_table = vs_dc_driver_dt_match, -+ }, -+}; -+ -+module_platform_driver(vs_dc_platform_driver); -+ -+MODULE_AUTHOR("Icenowy Zheng "); -+MODULE_DESCRIPTION("Verisilicon display controller driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h b/drivers/gpu/drm/verisilicon/vs_dc.h -new file mode 100644 -index 000000000000..ed1016f18758 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_dc.h -@@ -0,0 +1,38 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_DC_H_ -+#define _VS_DC_H_ -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "vs_hwdb.h" -+ -+#define VSDC_MAX_OUTPUTS 2 -+#define VSDC_RESET_COUNT 3 -+ -+struct vs_drm_dev; -+struct vs_crtc; -+ -+struct vs_dc { -+ struct regmap *regs; -+ struct clk *core_clk; -+ struct clk *axi_clk; -+ struct clk *ahb_clk; -+ struct clk *pix_clk[VSDC_MAX_OUTPUTS]; -+ struct reset_control_bulk_data rsts[VSDC_RESET_COUNT]; -+ -+ struct vs_drm_dev *drm_dev; -+ struct vs_chip_identity identity; -+}; -+ -+#endif /* _VS_DC_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h b/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h -new file mode 100644 -index 000000000000..50509bbbff08 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_dc_top_regs.h -@@ -0,0 +1,27 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_DC_TOP_H_ -+#define _VS_DC_TOP_H_ -+ -+#include -+ -+#define VSDC_TOP_RST 0x0000 -+ -+#define VSDC_TOP_IRQ_ACK 0x0010 -+#define VSDC_TOP_IRQ_VSYNC(n) BIT(n) -+ -+#define VSDC_TOP_IRQ_EN 0x0014 -+ -+#define VSDC_TOP_CHIP_MODEL 0x0020 -+ -+#define VSDC_TOP_CHIP_REV 0x0024 -+ -+#define VSDC_TOP_CHIP_CUSTOMER_ID 0x0030 -+ -+#endif /* _VS_DC_TOP_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_drm.c b/drivers/gpu/drm/verisilicon/vs_drm.c -new file mode 100644 -index 000000000000..fd259d53f49f ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_drm.c -@@ -0,0 +1,182 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vs_bridge.h" -+#include "vs_crtc.h" -+#include "vs_dc.h" -+#include "vs_dc_top_regs.h" -+#include "vs_drm.h" -+ -+#define DRIVER_NAME "verisilicon" -+#define DRIVER_DESC "Verisilicon DC-series display controller driver" -+#define DRIVER_MAJOR 1 -+#define DRIVER_MINOR 0 -+ -+static int vs_gem_dumb_create(struct drm_file *file_priv, -+ struct drm_device *drm, -+ struct drm_mode_create_dumb *args) -+{ -+ int ret; -+ -+ /* The hardware wants 128B-aligned pitches for linear buffers. */ -+ ret = drm_mode_size_dumb(drm, args, 128, 0); -+ if (ret) -+ return ret; -+ -+ return drm_gem_dma_dumb_create_internal(file_priv, drm, args); -+} -+ -+DEFINE_DRM_GEM_FOPS(vs_drm_driver_fops); -+ -+static const struct drm_driver vs_drm_driver = { -+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, -+ .fops = &vs_drm_driver_fops, -+ .name = DRIVER_NAME, -+ .desc = DRIVER_DESC, -+ .major = DRIVER_MAJOR, -+ .minor = DRIVER_MINOR, -+ -+ /* GEM Operations */ -+ DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(vs_gem_dumb_create), -+ DRM_FBDEV_DMA_DRIVER_OPS, -+}; -+ -+static const struct drm_mode_config_funcs vs_mode_config_funcs = { -+ .fb_create = drm_gem_fb_create, -+ .atomic_check = drm_atomic_helper_check, -+ .atomic_commit = drm_atomic_helper_commit, -+}; -+ -+static struct drm_mode_config_helper_funcs vs_mode_config_helper_funcs = { -+ .atomic_commit_tail = drm_atomic_helper_commit_tail, -+}; -+ -+static void vs_mode_config_init(struct drm_device *drm) -+{ -+ drm->mode_config.min_width = 0; -+ drm->mode_config.min_height = 0; -+ drm->mode_config.max_width = 8192; -+ drm->mode_config.max_height = 8192; -+ drm->mode_config.funcs = &vs_mode_config_funcs; -+ drm->mode_config.helper_private = &vs_mode_config_helper_funcs; -+} -+ -+int vs_drm_initialize(struct vs_dc *dc, struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct vs_drm_dev *vdrm; -+ struct drm_device *drm; -+ struct vs_crtc *crtc; -+ struct vs_bridge *bridge; -+ unsigned int i; -+ int ret; -+ -+ vdrm = devm_drm_dev_alloc(dev, &vs_drm_driver, struct vs_drm_dev, base); -+ if (IS_ERR(vdrm)) -+ return PTR_ERR(vdrm); -+ -+ drm = &vdrm->base; -+ vdrm->dc = dc; -+ dc->drm_dev = vdrm; -+ -+ ret = drmm_mode_config_init(drm); -+ if (ret) -+ return ret; -+ -+ /* Remove early framebuffers (ie. simple-framebuffer) */ -+ ret = aperture_remove_all_conflicting_devices(DRIVER_NAME); -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < dc->identity.display_count; i++) { -+ crtc = vs_crtc_init(drm, dc, i); -+ if (IS_ERR(crtc)) -+ return PTR_ERR(crtc); -+ -+ bridge = vs_bridge_init(drm, crtc); -+ if (IS_ERR(bridge)) -+ return PTR_ERR(bridge); -+ -+ vdrm->crtcs[i] = crtc; -+ } -+ -+ ret = drm_vblank_init(drm, dc->identity.display_count); -+ if (ret) -+ return ret; -+ -+ vs_mode_config_init(drm); -+ -+ /* Enable connectors polling */ -+ drm_kms_helper_poll_init(drm); -+ -+ drm_mode_config_reset(drm); -+ -+ ret = drm_dev_register(drm, 0); -+ if (ret) -+ goto err_fini_poll; -+ -+ drm_client_setup(drm, NULL); -+ -+ return 0; -+ -+err_fini_poll: -+ drm_kms_helper_poll_fini(drm); -+ return ret; -+} -+ -+void vs_drm_finalize(struct vs_dc *dc) -+{ -+ struct vs_drm_dev *vdrm = dc->drm_dev; -+ struct drm_device *drm = &vdrm->base; -+ -+ drm_dev_unregister(drm); -+ drm_kms_helper_poll_fini(drm); -+ drm_atomic_helper_shutdown(drm); -+ dc->drm_dev = NULL; -+} -+ -+void vs_drm_shutdown_handler(struct vs_dc *dc) -+{ -+ struct vs_drm_dev *vdrm = dc->drm_dev; -+ -+ drm_atomic_helper_shutdown(&vdrm->base); -+} -+ -+void vs_drm_handle_irq(struct vs_dc *dc, u32 irqs) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < dc->identity.display_count; i++) { -+ if (irqs & VSDC_TOP_IRQ_VSYNC(i)) { -+ irqs &= ~VSDC_TOP_IRQ_VSYNC(i); -+ if (dc->drm_dev->crtcs[i]) -+ drm_crtc_handle_vblank(&dc->drm_dev->crtcs[i]->base); -+ } -+ } -+ -+ if (irqs) -+ drm_warn_once(&dc->drm_dev->base, -+ "Unknown Verisilicon DC interrupt 0x%x fired!\n", -+ irqs); -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_drm.h b/drivers/gpu/drm/verisilicon/vs_drm.h -new file mode 100644 -index 000000000000..606338206a42 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_drm.h -@@ -0,0 +1,28 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#ifndef _VS_DRM_H_ -+#define _VS_DRM_H_ -+ -+#include -+#include -+ -+#include -+ -+struct vs_dc; -+ -+struct vs_drm_dev { -+ struct drm_device base; -+ -+ struct vs_dc *dc; -+ struct vs_crtc *crtcs[VSDC_MAX_OUTPUTS]; -+}; -+ -+int vs_drm_initialize(struct vs_dc *dc, struct platform_device *pdev); -+void vs_drm_finalize(struct vs_dc *dc); -+void vs_drm_shutdown_handler(struct vs_dc *dc); -+void vs_drm_handle_irq(struct vs_dc *dc, u32 irqs); -+ -+#endif /* _VS_DRM_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisilicon/vs_hwdb.c -new file mode 100644 -index 000000000000..09336af0900a ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c -@@ -0,0 +1,150 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+ -+#include -+ -+#include "vs_dc_top_regs.h" -+#include "vs_hwdb.h" -+ -+static const u32 vs_formats_array_no_yuv444[] = { -+ DRM_FORMAT_XRGB4444, -+ DRM_FORMAT_XBGR4444, -+ DRM_FORMAT_RGBX4444, -+ DRM_FORMAT_BGRX4444, -+ DRM_FORMAT_ARGB4444, -+ DRM_FORMAT_ABGR4444, -+ DRM_FORMAT_RGBA4444, -+ DRM_FORMAT_BGRA4444, -+ DRM_FORMAT_XRGB1555, -+ DRM_FORMAT_XBGR1555, -+ DRM_FORMAT_RGBX5551, -+ DRM_FORMAT_BGRX5551, -+ DRM_FORMAT_ARGB1555, -+ DRM_FORMAT_ABGR1555, -+ DRM_FORMAT_RGBA5551, -+ DRM_FORMAT_BGRA5551, -+ DRM_FORMAT_RGB565, -+ DRM_FORMAT_BGR565, -+ DRM_FORMAT_XRGB8888, -+ DRM_FORMAT_XBGR8888, -+ DRM_FORMAT_RGBX8888, -+ DRM_FORMAT_BGRX8888, -+ DRM_FORMAT_ARGB8888, -+ DRM_FORMAT_ABGR8888, -+ DRM_FORMAT_RGBA8888, -+ DRM_FORMAT_BGRA8888, -+ DRM_FORMAT_ARGB2101010, -+ DRM_FORMAT_ABGR2101010, -+ DRM_FORMAT_RGBA1010102, -+ DRM_FORMAT_BGRA1010102, -+ /* TODO: non-RGB formats */ -+}; -+ -+static const u32 vs_formats_array_with_yuv444[] = { -+ DRM_FORMAT_XRGB4444, -+ DRM_FORMAT_XBGR4444, -+ DRM_FORMAT_RGBX4444, -+ DRM_FORMAT_BGRX4444, -+ DRM_FORMAT_ARGB4444, -+ DRM_FORMAT_ABGR4444, -+ DRM_FORMAT_RGBA4444, -+ DRM_FORMAT_BGRA4444, -+ DRM_FORMAT_XRGB1555, -+ DRM_FORMAT_XBGR1555, -+ DRM_FORMAT_RGBX5551, -+ DRM_FORMAT_BGRX5551, -+ DRM_FORMAT_ARGB1555, -+ DRM_FORMAT_ABGR1555, -+ DRM_FORMAT_RGBA5551, -+ DRM_FORMAT_BGRA5551, -+ DRM_FORMAT_RGB565, -+ DRM_FORMAT_BGR565, -+ DRM_FORMAT_XRGB8888, -+ DRM_FORMAT_XBGR8888, -+ DRM_FORMAT_RGBX8888, -+ DRM_FORMAT_BGRX8888, -+ DRM_FORMAT_ARGB8888, -+ DRM_FORMAT_ABGR8888, -+ DRM_FORMAT_RGBA8888, -+ DRM_FORMAT_BGRA8888, -+ DRM_FORMAT_ARGB2101010, -+ DRM_FORMAT_ABGR2101010, -+ DRM_FORMAT_RGBA1010102, -+ DRM_FORMAT_BGRA1010102, -+ /* TODO: non-RGB formats */ -+}; -+ -+static const struct vs_formats vs_formats_no_yuv444 = { -+ .array = vs_formats_array_no_yuv444, -+ .num = ARRAY_SIZE(vs_formats_array_no_yuv444) -+}; -+ -+static const struct vs_formats vs_formats_with_yuv444 = { -+ .array = vs_formats_array_with_yuv444, -+ .num = ARRAY_SIZE(vs_formats_array_with_yuv444) -+}; -+ -+static struct vs_chip_identity vs_chip_identities[] = { -+ { -+ .model = 0x8200, -+ .revision = 0x5720, -+ .customer_id = ~0U, -+ -+ .display_count = 2, -+ .formats = &vs_formats_no_yuv444, -+ }, -+ { -+ .model = 0x8200, -+ .revision = 0x5721, -+ .customer_id = 0x30B, -+ -+ .display_count = 2, -+ .formats = &vs_formats_no_yuv444, -+ }, -+ { -+ .model = 0x8200, -+ .revision = 0x5720, -+ .customer_id = 0x310, -+ -+ .display_count = 2, -+ .formats = &vs_formats_with_yuv444, -+ }, -+ { -+ .model = 0x8200, -+ .revision = 0x5720, -+ .customer_id = 0x311, -+ -+ .display_count = 2, -+ .formats = &vs_formats_no_yuv444, -+ }, -+}; -+ -+int vs_fill_chip_identity(struct regmap *regs, -+ struct vs_chip_identity *ident) -+{ -+ u32 model; -+ u32 revision; -+ u32 customer_id; -+ int i; -+ -+ regmap_read(regs, VSDC_TOP_CHIP_MODEL, &model); -+ regmap_read(regs, VSDC_TOP_CHIP_REV, &revision); -+ regmap_read(regs, VSDC_TOP_CHIP_CUSTOMER_ID, &customer_id); -+ -+ for (i = 0; i < ARRAY_SIZE(vs_chip_identities); i++) { -+ if (vs_chip_identities[i].model == model && -+ vs_chip_identities[i].revision == revision && -+ (vs_chip_identities[i].customer_id == customer_id || -+ vs_chip_identities[i].customer_id == ~0U)) { -+ memcpy(ident, &vs_chip_identities[i], sizeof(*ident)); -+ ident->customer_id = customer_id; -+ return 0; -+ } -+ } -+ -+ return -EINVAL; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisilicon/vs_hwdb.h -new file mode 100644 -index 000000000000..92192e4fa086 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h -@@ -0,0 +1,29 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#ifndef _VS_HWDB_H_ -+#define _VS_HWDB_H_ -+ -+#include -+#include -+ -+struct vs_formats { -+ const u32 *array; -+ unsigned int num; -+}; -+ -+struct vs_chip_identity { -+ u32 model; -+ u32 revision; -+ u32 customer_id; -+ -+ u32 display_count; -+ const struct vs_formats *formats; -+}; -+ -+int vs_fill_chip_identity(struct regmap *regs, -+ struct vs_chip_identity *ident); -+ -+#endif /* _VS_HWDB_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_plane.c b/drivers/gpu/drm/verisilicon/vs_plane.c -new file mode 100644 -index 000000000000..2f3953e588a3 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_plane.c -@@ -0,0 +1,124 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "vs_plane.h" -+ -+void drm_format_to_vs_format(u32 drm_format, struct vs_format *vs_format) -+{ -+ switch (drm_format) { -+ case DRM_FORMAT_XRGB4444: -+ case DRM_FORMAT_RGBX4444: -+ case DRM_FORMAT_XBGR4444: -+ case DRM_FORMAT_BGRX4444: -+ vs_format->color = VSDC_COLOR_FORMAT_X4R4G4B4; -+ break; -+ case DRM_FORMAT_ARGB4444: -+ case DRM_FORMAT_RGBA4444: -+ case DRM_FORMAT_ABGR4444: -+ case DRM_FORMAT_BGRA4444: -+ vs_format->color = VSDC_COLOR_FORMAT_A4R4G4B4; -+ break; -+ case DRM_FORMAT_XRGB1555: -+ case DRM_FORMAT_RGBX5551: -+ case DRM_FORMAT_XBGR1555: -+ case DRM_FORMAT_BGRX5551: -+ vs_format->color = VSDC_COLOR_FORMAT_X1R5G5B5; -+ break; -+ case DRM_FORMAT_ARGB1555: -+ case DRM_FORMAT_RGBA5551: -+ case DRM_FORMAT_ABGR1555: -+ case DRM_FORMAT_BGRA5551: -+ vs_format->color = VSDC_COLOR_FORMAT_A1R5G5B5; -+ break; -+ case DRM_FORMAT_RGB565: -+ case DRM_FORMAT_BGR565: -+ vs_format->color = VSDC_COLOR_FORMAT_R5G6B5; -+ break; -+ case DRM_FORMAT_XRGB8888: -+ case DRM_FORMAT_RGBX8888: -+ case DRM_FORMAT_XBGR8888: -+ case DRM_FORMAT_BGRX8888: -+ vs_format->color = VSDC_COLOR_FORMAT_X8R8G8B8; -+ break; -+ case DRM_FORMAT_ARGB8888: -+ case DRM_FORMAT_RGBA8888: -+ case DRM_FORMAT_ABGR8888: -+ case DRM_FORMAT_BGRA8888: -+ vs_format->color = VSDC_COLOR_FORMAT_A8R8G8B8; -+ break; -+ case DRM_FORMAT_ARGB2101010: -+ case DRM_FORMAT_RGBA1010102: -+ case DRM_FORMAT_ABGR2101010: -+ case DRM_FORMAT_BGRA1010102: -+ vs_format->color = VSDC_COLOR_FORMAT_A2R10G10B10; -+ break; -+ default: -+ pr_warn("Unexpected drm format!\n"); -+ } -+ -+ switch (drm_format) { -+ case DRM_FORMAT_RGBX4444: -+ case DRM_FORMAT_RGBA4444: -+ case DRM_FORMAT_RGBX5551: -+ case DRM_FORMAT_RGBA5551: -+ case DRM_FORMAT_RGBX8888: -+ case DRM_FORMAT_RGBA8888: -+ case DRM_FORMAT_RGBA1010102: -+ vs_format->swizzle = VSDC_SWIZZLE_RGBA; -+ break; -+ case DRM_FORMAT_XBGR4444: -+ case DRM_FORMAT_ABGR4444: -+ case DRM_FORMAT_XBGR1555: -+ case DRM_FORMAT_ABGR1555: -+ case DRM_FORMAT_BGR565: -+ case DRM_FORMAT_XBGR8888: -+ case DRM_FORMAT_ABGR8888: -+ case DRM_FORMAT_ABGR2101010: -+ vs_format->swizzle = VSDC_SWIZZLE_ABGR; -+ break; -+ case DRM_FORMAT_BGRX4444: -+ case DRM_FORMAT_BGRA4444: -+ case DRM_FORMAT_BGRX5551: -+ case DRM_FORMAT_BGRA5551: -+ case DRM_FORMAT_BGRX8888: -+ case DRM_FORMAT_BGRA8888: -+ case DRM_FORMAT_BGRA1010102: -+ vs_format->swizzle = VSDC_SWIZZLE_BGRA; -+ break; -+ default: -+ /* N/A for YUV formats */ -+ vs_format->swizzle = VSDC_SWIZZLE_ARGB; -+ } -+ -+ /* N/A for non-YUV formats */ -+ vs_format->uv_swizzle = false; -+} -+ -+dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, -+ const struct drm_rect *src_rect) -+{ -+ struct drm_gem_dma_object *gem; -+ dma_addr_t dma_addr; -+ -+ /* Get the physical address of the buffer in memory */ -+ gem = drm_fb_dma_get_gem_obj(fb, 0); -+ -+ /* Compute the start of the displayed memory */ -+ dma_addr = gem->dma_addr + fb->offsets[0]; -+ -+ /* Fixup framebuffer address for src coordinates */ -+ dma_addr += drm_format_info_min_pitch(fb->format, 0, -+ src_rect->x1 >> 16); -+ dma_addr += (src_rect->y1 >> 16) * fb->pitches[0]; -+ -+ return dma_addr; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_plane.h b/drivers/gpu/drm/verisilicon/vs_plane.h -new file mode 100644 -index 000000000000..41875ea3d66a ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_plane.h -@@ -0,0 +1,72 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_PLANE_H_ -+#define _VS_PLANE_H_ -+ -+#include -+ -+#include -+#include -+#include -+#include -+ -+#define VSDC_MAKE_PLANE_SIZE(w, h) (((w) & 0x7fff) | (((h) & 0x7fff) << 15)) -+#define VSDC_MAKE_PLANE_POS(x, y) (((x) & 0x7fff) | (((y) & 0x7fff) << 15)) -+ -+struct vs_dc; -+ -+enum vs_color_format { -+ VSDC_COLOR_FORMAT_X4R4G4B4, -+ VSDC_COLOR_FORMAT_A4R4G4B4, -+ VSDC_COLOR_FORMAT_X1R5G5B5, -+ VSDC_COLOR_FORMAT_A1R5G5B5, -+ VSDC_COLOR_FORMAT_R5G6B5, -+ VSDC_COLOR_FORMAT_X8R8G8B8, -+ VSDC_COLOR_FORMAT_A8R8G8B8, -+ VSDC_COLOR_FORMAT_YUY2, -+ VSDC_COLOR_FORMAT_UYVY, -+ VSDC_COLOR_FORMAT_INDEX8, -+ VSDC_COLOR_FORMAT_MONOCHROME, -+ VSDC_COLOR_FORMAT_YV12 = 0xf, -+ VSDC_COLOR_FORMAT_A8, -+ VSDC_COLOR_FORMAT_NV12, -+ VSDC_COLOR_FORMAT_NV16, -+ VSDC_COLOR_FORMAT_RG16, -+ VSDC_COLOR_FORMAT_R8, -+ VSDC_COLOR_FORMAT_NV12_10BIT, -+ VSDC_COLOR_FORMAT_A2R10G10B10, -+ VSDC_COLOR_FORMAT_NV16_10BIT, -+ VSDC_COLOR_FORMAT_INDEX1, -+ VSDC_COLOR_FORMAT_INDEX2, -+ VSDC_COLOR_FORMAT_INDEX4, -+ VSDC_COLOR_FORMAT_P010, -+ VSDC_COLOR_FORMAT_YUV444, -+ VSDC_COLOR_FORMAT_YUV444_10BIT -+}; -+ -+enum vs_swizzle { -+ VSDC_SWIZZLE_ARGB, -+ VSDC_SWIZZLE_RGBA, -+ VSDC_SWIZZLE_ABGR, -+ VSDC_SWIZZLE_BGRA, -+}; -+ -+struct vs_format { -+ enum vs_color_format color; -+ enum vs_swizzle swizzle; -+ bool uv_swizzle; -+}; -+ -+void drm_format_to_vs_format(u32 drm_format, struct vs_format *vs_format); -+dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, -+ const struct drm_rect *src_rect); -+ -+struct drm_plane *vs_primary_plane_init(struct drm_device *dev, struct vs_dc *dc); -+ -+#endif /* _VS_PLANE_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane.c b/drivers/gpu/drm/verisilicon/vs_primary_plane.c -new file mode 100644 -index 000000000000..e8fcb5958615 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_primary_plane.c -@@ -0,0 +1,173 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ */ -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vs_crtc.h" -+#include "vs_plane.h" -+#include "vs_dc.h" -+#include "vs_primary_plane_regs.h" -+ -+static int vs_primary_plane_atomic_check(struct drm_plane *plane, -+ struct drm_atomic_state *state) -+{ -+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, -+ plane); -+ struct drm_crtc *crtc = new_plane_state->crtc; -+ struct drm_crtc_state *crtc_state; -+ -+ if (!crtc) -+ return 0; -+ -+ crtc_state = drm_atomic_get_new_crtc_state(state, crtc); -+ if (WARN_ON(!crtc_state)) -+ return -EINVAL; -+ -+ return drm_atomic_helper_check_plane_state(new_plane_state, -+ crtc_state, -+ DRM_PLANE_NO_SCALING, -+ DRM_PLANE_NO_SCALING, -+ false, true); -+} -+ -+static void vs_primary_plane_commit(struct vs_dc *dc, unsigned int output) -+{ -+ regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), -+ VSDC_FB_CONFIG_EX_COMMIT); -+} -+ -+static void vs_primary_plane_atomic_enable(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, -+ plane); -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ unsigned int output = vcrtc->id; -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), -+ VSDC_FB_CONFIG_EX_FB_EN); -+ regmap_update_bits(dc->regs, VSDC_FB_CONFIG_EX(output), -+ VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK, -+ VSDC_FB_CONFIG_EX_DISPLAY_ID(output)); -+ -+ vs_primary_plane_commit(dc, output); -+} -+ -+static void vs_primary_plane_atomic_disable(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_old_plane_state(atomic_state, -+ plane); -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ unsigned int output = vcrtc->id; -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_set_bits(dc->regs, VSDC_FB_CONFIG_EX(output), -+ VSDC_FB_CONFIG_EX_FB_EN); -+ -+ vs_primary_plane_commit(dc, output); -+} -+ -+static void vs_primary_plane_atomic_update(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, -+ plane); -+ struct drm_framebuffer *fb = state->fb; -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_dc *dc; -+ struct vs_crtc *vcrtc; -+ struct vs_format fmt; -+ unsigned int output; -+ dma_addr_t dma_addr; -+ -+ if (!state->visible) { -+ vs_primary_plane_atomic_disable(plane, atomic_state); -+ return; -+ } -+ -+ vcrtc = drm_crtc_to_vs_crtc(crtc); -+ output = vcrtc->id; -+ dc = vcrtc->dc; -+ -+ drm_format_to_vs_format(state->fb->format->format, &fmt); -+ -+ regmap_update_bits(dc->regs, VSDC_FB_CONFIG(output), -+ VSDC_FB_CONFIG_FMT_MASK, -+ VSDC_FB_CONFIG_FMT(fmt.color)); -+ regmap_update_bits(dc->regs, VSDC_FB_CONFIG(output), -+ VSDC_FB_CONFIG_SWIZZLE_MASK, -+ VSDC_FB_CONFIG_SWIZZLE(fmt.swizzle)); -+ regmap_assign_bits(dc->regs, VSDC_FB_CONFIG(output), -+ VSDC_FB_CONFIG_UV_SWIZZLE_EN, fmt.uv_swizzle); -+ -+ dma_addr = vs_fb_get_dma_addr(fb, &state->src); -+ -+ regmap_write(dc->regs, VSDC_FB_ADDRESS(output), -+ lower_32_bits(dma_addr)); -+ regmap_write(dc->regs, VSDC_FB_STRIDE(output), -+ fb->pitches[0]); -+ -+ regmap_write(dc->regs, VSDC_FB_TOP_LEFT(output), -+ VSDC_MAKE_PLANE_POS(state->crtc_x, state->crtc_y)); -+ regmap_write(dc->regs, VSDC_FB_BOTTOM_RIGHT(output), -+ VSDC_MAKE_PLANE_POS(state->crtc_x + state->crtc_w, -+ state->crtc_y + state->crtc_h)); -+ regmap_write(dc->regs, VSDC_FB_SIZE(output), -+ VSDC_MAKE_PLANE_SIZE(state->crtc_w, state->crtc_h)); -+ -+ regmap_write(dc->regs, VSDC_FB_BLEND_CONFIG(output), -+ VSDC_FB_BLEND_CONFIG_BLEND_DISABLE); -+ -+ vs_primary_plane_commit(dc, output); -+} -+ -+static const struct drm_plane_helper_funcs vs_primary_plane_helper_funcs = { -+ .atomic_check = vs_primary_plane_atomic_check, -+ .atomic_update = vs_primary_plane_atomic_update, -+ .atomic_enable = vs_primary_plane_atomic_enable, -+ .atomic_disable = vs_primary_plane_atomic_disable, -+}; -+ -+static const struct drm_plane_funcs vs_primary_plane_funcs = { -+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, -+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, -+ .disable_plane = drm_atomic_helper_disable_plane, -+ .reset = drm_atomic_helper_plane_reset, -+ .update_plane = drm_atomic_helper_update_plane, -+}; -+ -+struct drm_plane *vs_primary_plane_init(struct drm_device *drm_dev, struct vs_dc *dc) -+{ -+ struct drm_plane *plane; -+ -+ plane = drmm_universal_plane_alloc(drm_dev, struct drm_plane, dev, 0, -+ &vs_primary_plane_funcs, -+ dc->identity.formats->array, -+ dc->identity.formats->num, -+ NULL, -+ DRM_PLANE_TYPE_PRIMARY, -+ NULL); -+ -+ if (IS_ERR(plane)) -+ return plane; -+ -+ drm_plane_helper_add(plane, &vs_primary_plane_helper_funcs); -+ -+ return plane; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h -new file mode 100644 -index 000000000000..cbb125c46b39 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h -@@ -0,0 +1,53 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_PRIMARY_PLANE_REGS_H_ -+#define _VS_PRIMARY_PLANE_REGS_H_ -+ -+#include -+ -+#define VSDC_FB_ADDRESS(n) (0x1400 + 0x4 * (n)) -+ -+#define VSDC_FB_STRIDE(n) (0x1408 + 0x4 * (n)) -+ -+#define VSDC_FB_CONFIG(n) (0x1518 + 0x4 * (n)) -+#define VSDC_FB_CONFIG_CLEAR_EN BIT(8) -+#define VSDC_FB_CONFIG_ROT_MASK GENMASK(13, 11) -+#define VSDC_FB_CONFIG_ROT(v) ((v) << 11) -+#define VSDC_FB_CONFIG_YUV_SPACE_MASK GENMASK(16, 14) -+#define VSDC_FB_CONFIG_YUV_SPACE(v) ((v) << 14) -+#define VSDC_FB_CONFIG_TILE_MODE_MASK GENMASK(21, 17) -+#define VSDC_FB_CONFIG_TILE_MODE(v) ((v) << 14) -+#define VSDC_FB_CONFIG_SCALE_EN BIT(22) -+#define VSDC_FB_CONFIG_SWIZZLE_MASK GENMASK(24, 23) -+#define VSDC_FB_CONFIG_SWIZZLE(v) ((v) << 23) -+#define VSDC_FB_CONFIG_UV_SWIZZLE_EN BIT(25) -+#define VSDC_FB_CONFIG_FMT_MASK GENMASK(31, 26) -+#define VSDC_FB_CONFIG_FMT(v) ((v) << 26) -+ -+#define VSDC_FB_SIZE(n) (0x1810 + 0x4 * (n)) -+/* Fill with value generated with VSDC_MAKE_PLANE_SIZE(w, h) */ -+ -+#define VSDC_FB_CONFIG_EX(n) (0x1CC0 + 0x4 * (n)) -+#define VSDC_FB_CONFIG_EX_COMMIT BIT(12) -+#define VSDC_FB_CONFIG_EX_FB_EN BIT(13) -+#define VSDC_FB_CONFIG_EX_ZPOS_MASK GENMASK(18, 16) -+#define VSDC_FB_CONFIG_EX_ZPOS(v) ((v) << 16) -+#define VSDC_FB_CONFIG_EX_DISPLAY_ID_MASK GENMASK(19, 19) -+#define VSDC_FB_CONFIG_EX_DISPLAY_ID(v) ((v) << 19) -+ -+#define VSDC_FB_TOP_LEFT(n) (0x24D8 + 0x4 * (n)) -+/* Fill with value generated with VSDC_MAKE_PLANE_POS(x, y) */ -+ -+#define VSDC_FB_BOTTOM_RIGHT(n) (0x24E0 + 0x4 * (n)) -+/* Fill with value generated with VSDC_MAKE_PLANE_POS(x, y) */ -+ -+#define VSDC_FB_BLEND_CONFIG(n) (0x2510 + 0x4 * (n)) -+#define VSDC_FB_BLEND_CONFIG_BLEND_DISABLE BIT(1) -+ -+#endif /* _VS_PRIMARY_PLANE_REGS_H_ */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch b/SPECS/linux-lts/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch new file mode 100644 index 0000000000..6f796d9cbc --- /dev/null +++ b/SPECS/linux-lts/0194-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch @@ -0,0 +1,103 @@ +From ea4a0e0935587b36a14380693c67c8cd0a9b30f1 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Fri, 6 Feb 2026 10:32:02 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mfd: spacemit,p1: Add individual + regulator supply properties + +Add supply properties that match the P1 PMIC's actual hardware topology +where each buck converter has its own VIN pin and LDO groups share +common input pins. Supply names are defined according to the pinout +names in the P1 datasheet. + +The existing "vin-supply" is dropped from the binding document as the +updated spacemit P1 driver no longer parses it. Only the per-rail names +("vin1-supply", "vin2-supply", ...) are supported. + +Signed-off-by: Guodong Xu +Acked-by: Conor Dooley +Reviewed-by: Alex Elder +Link: https://patch.msgid.link/20260206-spacemit-p1-v4-1-8f695d93811e@riscstar.com +Signed-off-by: Mark Brown +(cherry picked from commit 82ffa9610ba39d3628a9bec968ddc68fe2fe6612) +Signed-off-by: Han Gao +--- + .../devicetree/bindings/mfd/spacemit,p1.yaml | 49 ++++++++++++++++++- + 1 file changed, 47 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml b/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml +index c6593ac6ef6a..c67b1c6e4e4f 100644 +--- a/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml ++++ b/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml +@@ -27,8 +27,41 @@ properties: + interrupts: + maxItems: 1 + +- vin-supply: +- description: Input supply phandle. ++ vin1-supply: ++ description: ++ Power supply for BUCK1. Required if BUCK1 is defined. ++ ++ vin2-supply: ++ description: ++ Power supply for BUCK2. Required if BUCK2 is defined. ++ ++ vin3-supply: ++ description: ++ Power supply for BUCK3. Required if BUCK3 is defined. ++ ++ vin4-supply: ++ description: ++ Power supply for BUCK4. Required if BUCK4 is defined. ++ ++ vin5-supply: ++ description: ++ Power supply for BUCK5. Required if BUCK5 is defined. ++ ++ vin6-supply: ++ description: ++ Power supply for BUCK6. Required if BUCK6 is defined. ++ ++ aldoin-supply: ++ description: ++ Power supply for ALDO1-4. Required if any are defined. ++ ++ dldoin1-supply: ++ description: ++ Power supply for DLDO1-4. Required if any are defined. ++ ++ dldoin2-supply: ++ description: ++ Power supply for DLDO5-7. Required if any are defined. + + regulators: + type: object +@@ -58,6 +91,10 @@ examples: + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; ++ vin1-supply = <®_vcc_5v>; ++ vin5-supply = <®_vcc_5v>; ++ aldoin-supply = <®_vcc_5v>; ++ dldoin1-supply = <&buck5>; + + regulators { + buck1 { +@@ -68,6 +105,14 @@ examples: + regulator-always-on; + }; + ++ buck5: buck5 { ++ regulator-name = "buck5"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ + aldo1 { + regulator-name = "aldo1"; + regulator-min-microvolt = <500000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0195-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch b/SPECS/linux-lts/0195-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch deleted file mode 100644 index 31987352cf..0000000000 --- a/SPECS/linux-lts/0195-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch +++ /dev/null @@ -1,153 +0,0 @@ -From ee91943024b041838f8d48b5875cd8083a8d0945 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:18 +0800 -Subject: [PATCH 195/467] UPSTREAM: dt-bindings: display/bridge: add binding - for TH1520 HDMI controller - -T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired -with DesignWare HDMI PHY, with an extra clock gate for HDMI pixel clock -and two reset controls. - -Add a device tree binding to it. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Thomas Zimmermann -Link: https://patch.msgid.link/20260129023922.1527729-5-zhengxingda@iscas.ac.cn -(cherry picked from commit 3d60ff99a78ccd3b72765542dd083b134d6ae4bb) -Signed-off-by: Han Gao ---- - .../display/bridge/thead,th1520-dw-hdmi.yaml | 120 ++++++++++++++++++ - 1 file changed, 120 insertions(+) - create mode 100644 Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml - -diff --git a/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml -new file mode 100644 -index 000000000000..68fff885ce15 ---- /dev/null -+++ b/Documentation/devicetree/bindings/display/bridge/thead,th1520-dw-hdmi.yaml -@@ -0,0 +1,120 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/display/bridge/thead,th1520-dw-hdmi.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: T-Head TH1520 DesignWare HDMI TX Encoder -+ -+maintainers: -+ - Icenowy Zheng -+ -+description: -+ The HDMI transmitter is a Synopsys DesignWare HDMI TX controller -+ paired with a DesignWare HDMI Gen2 TX PHY. -+ -+allOf: -+ - $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - thead,th1520-dw-hdmi -+ -+ reg-io-width: -+ const: 4 -+ -+ clocks: -+ maxItems: 4 -+ -+ clock-names: -+ items: -+ - const: iahb -+ - const: isfr -+ - const: cec -+ - const: pix -+ -+ resets: -+ items: -+ - description: Main reset -+ - description: Configuration APB reset -+ -+ reset-names: -+ items: -+ - const: main -+ - const: apb -+ -+ ports: -+ $ref: /schemas/graph.yaml#/properties/ports -+ -+ properties: -+ port@0: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: Input port connected to DC8200 DPU "DP" output -+ -+ port@1: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: HDMI output port -+ -+ required: -+ - port@0 -+ - port@1 -+ -+required: -+ - compatible -+ - reg -+ - reg-io-width -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ - interrupts -+ - ports -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ hdmi@ffef540000 { -+ compatible = "thead,th1520-dw-hdmi"; -+ reg = <0xff 0xef540000 0x0 0x40000>; -+ reg-io-width = <4>; -+ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_vo CLK_HDMI_PCLK>, -+ <&clk_vo CLK_HDMI_SFR>, -+ <&clk_vo CLK_HDMI_CEC>, -+ <&clk_vo CLK_HDMI_PIXCLK>; -+ clock-names = "iahb", "isfr", "cec", "pix"; -+ resets = <&rst_vo TH1520_RESET_ID_HDMI>, -+ <&rst_vo TH1520_RESET_ID_HDMI_APB>; -+ reset-names = "main", "apb"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ port@0 { -+ reg = <0>; -+ -+ hdmi_in: endpoint { -+ remote-endpoint = <&dpu_out_dp1>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ hdmi_out_conn: endpoint { -+ remote-endpoint = <&hdmi_conn_in>; -+ }; -+ }; -+ }; -+ }; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch b/SPECS/linux-lts/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch new file mode 100644 index 0000000000..c1c7ac83ec --- /dev/null +++ b/SPECS/linux-lts/0195-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch @@ -0,0 +1,75 @@ +From 42b7ba3e5273fbdc3ca27c1fb551be6f0eccab97 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Fri, 6 Feb 2026 10:32:03 +0800 +Subject: [RUYI PATCH] UPSTREAM: regulator: spacemit-p1: Update supply names + +Update supply names to match the P1 PMIC's actual hardware pinout where +each buck has an individual VIN pin (vin1-vin6) and LDO groups have +dedicated input pins (aldoin, dldoin1, dldoin2). + +This is an ABI change from the original "vin" and "buck5" supplies. +The P1/PMIC regulator has no consumers in the DTS tree yet. For the two +K1 boards in-tree (BPI-F3 and Jupiter), power settings come from +boot firmware, so a probe failure has minimal impact. + +Signed-off-by: Guodong Xu +Link: https://developer.spacemit.com/documentation?token=T1Btw2BdiiSlSXkAdibcoMetnag +[1] +Reviewed-by: Alex Elder +Link: https://patch.msgid.link/20260206-spacemit-p1-v4-2-8f695d93811e@riscstar.com +Signed-off-by: Mark Brown +(cherry picked from commit fbb4c52ccdcb4a612d2b7f800aa57090eeee16d7) +Signed-off-by: Han Gao +--- + drivers/regulator/spacemit-p1.c | 25 ++++++++++++++----------- + 1 file changed, 14 insertions(+), 11 deletions(-) + +diff --git a/drivers/regulator/spacemit-p1.c b/drivers/regulator/spacemit-p1.c +index 2b585ba01a93..57e6e00a73fa 100644 +--- a/drivers/regulator/spacemit-p1.c ++++ b/drivers/regulator/spacemit-p1.c +@@ -87,13 +87,16 @@ static const struct linear_range p1_ldo_ranges[] = { + } + + #define P1_BUCK_DESC(_n) \ +- P1_REG_DESC(BUCK, buck, _n, "vin", 0x47, BUCK_MASK, 255, p1_buck_ranges) ++ P1_REG_DESC(BUCK, buck, _n, "vin" #_n, 0x47, BUCK_MASK, 255, p1_buck_ranges) + + #define P1_ALDO_DESC(_n) \ +- P1_REG_DESC(ALDO, aldo, _n, "vin", 0x5b, LDO_MASK, 128, p1_ldo_ranges) ++ P1_REG_DESC(ALDO, aldo, _n, "aldoin", 0x5b, LDO_MASK, 128, p1_ldo_ranges) + +-#define P1_DLDO_DESC(_n) \ +- P1_REG_DESC(DLDO, dldo, _n, "buck5", 0x67, LDO_MASK, 128, p1_ldo_ranges) ++#define P1_DLDO1_DESC(_n) \ ++ P1_REG_DESC(DLDO, dldo, _n, "dldoin1", 0x67, LDO_MASK, 128, p1_ldo_ranges) ++ ++#define P1_DLDO2_DESC(_n) \ ++ P1_REG_DESC(DLDO, dldo, _n, "dldoin2", 0x67, LDO_MASK, 128, p1_ldo_ranges) + + static const struct regulator_desc p1_regulator_desc[] = { + P1_BUCK_DESC(1), +@@ -108,13 +111,13 @@ static const struct regulator_desc p1_regulator_desc[] = { + P1_ALDO_DESC(3), + P1_ALDO_DESC(4), + +- P1_DLDO_DESC(1), +- P1_DLDO_DESC(2), +- P1_DLDO_DESC(3), +- P1_DLDO_DESC(4), +- P1_DLDO_DESC(5), +- P1_DLDO_DESC(6), +- P1_DLDO_DESC(7), ++ P1_DLDO1_DESC(1), ++ P1_DLDO1_DESC(2), ++ P1_DLDO1_DESC(3), ++ P1_DLDO1_DESC(4), ++ P1_DLDO2_DESC(5), ++ P1_DLDO2_DESC(6), ++ P1_DLDO2_DESC(7), + }; + + static int p1_regulator_probe(struct platform_device *pdev) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0196-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch b/SPECS/linux-lts/0196-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch deleted file mode 100644 index d96c026cbf..0000000000 --- a/SPECS/linux-lts/0196-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch +++ /dev/null @@ -1,257 +0,0 @@ -From 93ee7e5ff8c14262f2edbaebf59e12ec50ebeac0 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:19 +0800 -Subject: [PATCH 196/467] UPSTREAM: drm/bridge: add a driver for T-Head TH1520 - HDMI controller - -T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller (paired -with DesignWare HDMI TX PHY Gen2) that takes the "DP" output from the -display controller. - -Add a driver for this controller utilizing the common DesignWare HDMI -code in the kernel. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Tested-by: Han Gao -Tested-by: Michal Wilczynski -Acked-by: Thomas Zimmermann -Signed-off-by: Thomas Zimmermann -Link: https://patch.msgid.link/20260129023922.1527729-6-zhengxingda@iscas.ac.cn -(cherry picked from commit 96f30ee0fb9db1663eb8fd55c12e4c67da8c4a90) -Signed-off-by: Han Gao ---- - MAINTAINERS | 1 + - drivers/gpu/drm/bridge/Kconfig | 10 ++ - drivers/gpu/drm/bridge/Makefile | 1 + - drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 173 ++++++++++++++++++++++++ - 4 files changed, 185 insertions(+) - create mode 100644 drivers/gpu/drm/bridge/th1520-dw-hdmi.c - -diff --git a/MAINTAINERS b/MAINTAINERS -index b50b6c7a9b52..1509fa6ab229 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -22227,6 +22227,7 @@ F: Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml - F: arch/riscv/boot/dts/thead/ - F: drivers/clk/thead/clk-th1520-ap.c - F: drivers/firmware/thead,th1520-aon.c -+F: drivers/gpu/drm/bridge/th1520-dw-hdmi.c - F: drivers/mailbox/mailbox-th1520.c - F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c - F: drivers/pinctrl/pinctrl-th1520.c -diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig -index a250afd8d662..8e19f5fb9ad7 100644 ---- a/drivers/gpu/drm/bridge/Kconfig -+++ b/drivers/gpu/drm/bridge/Kconfig -@@ -335,6 +335,16 @@ config DRM_THINE_THC63LVD1024 - help - Thine THC63LVD1024 LVDS/parallel converter driver. - -+config DRM_THEAD_TH1520_DW_HDMI -+ tristate "T-Head TH1520 DesignWare HDMI bridge" -+ depends on OF -+ depends on COMMON_CLK -+ depends on ARCH_THEAD || COMPILE_TEST -+ select DRM_DW_HDMI -+ help -+ Choose this to enable support for the internal HDMI bridge found -+ on the T-Head TH1520 SoC. -+ - config DRM_TOSHIBA_TC358762 - tristate "TC358762 DSI/DPI bridge" - depends on OF -diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile -index c7dc03182e59..085b5db45d6f 100644 ---- a/drivers/gpu/drm/bridge/Makefile -+++ b/drivers/gpu/drm/bridge/Makefile -@@ -28,6 +28,7 @@ obj-$(CONFIG_DRM_SII902X) += sii902x.o - obj-$(CONFIG_DRM_SII9234) += sii9234.o - obj-$(CONFIG_DRM_SIMPLE_BRIDGE) += simple-bridge.o - obj-$(CONFIG_DRM_SOLOMON_SSD2825) += ssd2825.o -+obj-$(CONFIG_DRM_THEAD_TH1520_DW_HDMI) += th1520-dw-hdmi.o - obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o - obj-$(CONFIG_DRM_TOSHIBA_TC358762) += tc358762.o - obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o -diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -new file mode 100644 -index 000000000000..389eead5f1c4 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -@@ -0,0 +1,173 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on rcar_dw_hdmi.c, which is: -+ * Copyright (C) 2016 Renesas Electronics Corporation -+ * Based on imx8mp-hdmi-tx.c, which is: -+ * Copyright (C) 2022 Pengutronix, Lucas Stach -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define TH1520_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */ -+#define TH1520_HDMI_PHY_CKSYMTXCTRL 0x09 /* Clock Symbol and Transmitter Control Register */ -+#define TH1520_HDMI_PHY_VLEVCTRL 0x0e /* Voltage Level Control Register */ -+#define TH1520_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */ -+#define TH1520_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */ -+#define TH1520_HDMI_PHY_TXTERM 0x19 /* Transmission Termination Register */ -+ -+struct th1520_hdmi_phy_params { -+ unsigned long mpixelclock; -+ u16 opmode_pllcfg; -+ u16 pllcurrgmpctrl; -+ u16 plldivctrl; -+ u16 cksymtxctrl; -+ u16 vlevctrl; -+ u16 txterm; -+}; -+ -+static const struct th1520_hdmi_phy_params th1520_hdmi_phy_params[] = { -+ { 35500000, 0x0003, 0x0283, 0x0628, 0x8088, 0x01a0, 0x0007 }, -+ { 44900000, 0x0003, 0x0285, 0x0228, 0x8088, 0x01a0, 0x0007 }, -+ { 71000000, 0x0002, 0x1183, 0x0614, 0x8088, 0x01a0, 0x0007 }, -+ { 90000000, 0x0002, 0x1142, 0x0214, 0x8088, 0x01a0, 0x0007 }, -+ { 121750000, 0x0001, 0x20c0, 0x060a, 0x8088, 0x01a0, 0x0007 }, -+ { 165000000, 0x0001, 0x2080, 0x020a, 0x8088, 0x01a0, 0x0007 }, -+ { 198000000, 0x0000, 0x3040, 0x0605, 0x83c8, 0x0120, 0x0004 }, -+ { 297000000, 0x0000, 0x3041, 0x0205, 0x81dc, 0x0200, 0x0005 }, -+ { 371250000, 0x0640, 0x3041, 0x0205, 0x80f6, 0x0140, 0x0000 }, -+ { 495000000, 0x0640, 0x3080, 0x0005, 0x80f6, 0x0140, 0x0000 }, -+ { 594000000, 0x0640, 0x3080, 0x0005, 0x80fa, 0x01e0, 0x0004 }, -+}; -+ -+struct th1520_hdmi { -+ struct dw_hdmi_plat_data plat_data; -+ struct dw_hdmi *dw_hdmi; -+ struct clk *pixclk; -+ struct reset_control *mainrst, *prst; -+}; -+ -+static enum drm_mode_status -+th1520_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, -+ const struct drm_display_info *info, -+ const struct drm_display_mode *mode) -+{ -+ /* -+ * The maximum supported clock frequency is 594 MHz, as shown in the PHY -+ * parameters table. -+ */ -+ if (mode->clock > 594000) -+ return MODE_CLOCK_HIGH; -+ -+ return MODE_OK; -+} -+ -+static void th1520_hdmi_phy_set_params(struct dw_hdmi *hdmi, -+ const struct th1520_hdmi_phy_params *params) -+{ -+ dw_hdmi_phy_i2c_write(hdmi, params->opmode_pllcfg, -+ TH1520_HDMI_PHY_OPMODE_PLLCFG); -+ dw_hdmi_phy_i2c_write(hdmi, params->pllcurrgmpctrl, -+ TH1520_HDMI_PHY_PLLCURRGMPCTRL); -+ dw_hdmi_phy_i2c_write(hdmi, params->plldivctrl, -+ TH1520_HDMI_PHY_PLLDIVCTRL); -+ dw_hdmi_phy_i2c_write(hdmi, params->vlevctrl, -+ TH1520_HDMI_PHY_VLEVCTRL); -+ dw_hdmi_phy_i2c_write(hdmi, params->cksymtxctrl, -+ TH1520_HDMI_PHY_CKSYMTXCTRL); -+ dw_hdmi_phy_i2c_write(hdmi, params->txterm, -+ TH1520_HDMI_PHY_TXTERM); -+} -+ -+static int th1520_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data, -+ unsigned long mpixelclock) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(th1520_hdmi_phy_params); i++) { -+ if (mpixelclock <= th1520_hdmi_phy_params[i].mpixelclock) { -+ th1520_hdmi_phy_set_params(hdmi, -+ &th1520_hdmi_phy_params[i]); -+ return 0; -+ } -+ } -+ -+ return -EINVAL; -+} -+ -+static int th1520_dw_hdmi_probe(struct platform_device *pdev) -+{ -+ struct th1520_hdmi *hdmi; -+ struct dw_hdmi_plat_data *plat_data; -+ struct device *dev = &pdev->dev; -+ -+ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); -+ if (!hdmi) -+ return -ENOMEM; -+ -+ plat_data = &hdmi->plat_data; -+ -+ hdmi->pixclk = devm_clk_get_enabled(dev, "pix"); -+ if (IS_ERR(hdmi->pixclk)) -+ return dev_err_probe(dev, PTR_ERR(hdmi->pixclk), -+ "Unable to get pixel clock\n"); -+ -+ hdmi->mainrst = devm_reset_control_get_exclusive_deasserted(dev, "main"); -+ if (IS_ERR(hdmi->mainrst)) -+ return dev_err_probe(dev, PTR_ERR(hdmi->mainrst), -+ "Unable to get main reset\n"); -+ -+ hdmi->prst = devm_reset_control_get_exclusive_deasserted(dev, "apb"); -+ if (IS_ERR(hdmi->prst)) -+ return dev_err_probe(dev, PTR_ERR(hdmi->prst), -+ "Unable to get apb reset\n"); -+ -+ plat_data->output_port = 1; -+ plat_data->mode_valid = th1520_hdmi_mode_valid; -+ plat_data->configure_phy = th1520_hdmi_phy_configure; -+ plat_data->priv_data = hdmi; -+ -+ hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); -+ if (IS_ERR(hdmi)) -+ return PTR_ERR(hdmi); -+ -+ platform_set_drvdata(pdev, hdmi); -+ -+ return 0; -+} -+ -+static void th1520_dw_hdmi_remove(struct platform_device *pdev) -+{ -+ struct dw_hdmi *hdmi = platform_get_drvdata(pdev); -+ -+ dw_hdmi_remove(hdmi); -+} -+ -+static const struct of_device_id th1520_dw_hdmi_of_table[] = { -+ { .compatible = "thead,th1520-dw-hdmi" }, -+ { /* Sentinel */ }, -+}; -+MODULE_DEVICE_TABLE(of, th1520_dw_hdmi_of_table); -+ -+static struct platform_driver th1520_dw_hdmi_platform_driver = { -+ .probe = th1520_dw_hdmi_probe, -+ .remove = th1520_dw_hdmi_remove, -+ .driver = { -+ .name = "th1520-dw-hdmi", -+ .of_match_table = th1520_dw_hdmi_of_table, -+ }, -+}; -+ -+module_platform_driver(th1520_dw_hdmi_platform_driver); -+ -+MODULE_AUTHOR("Icenowy Zheng "); -+MODULE_DESCRIPTION("T-Head TH1520 HDMI Encoder Driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch b/SPECS/linux-lts/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch new file mode 100644 index 0000000000..7a0dd9d20a --- /dev/null +++ b/SPECS/linux-lts/0196-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch @@ -0,0 +1,67 @@ +From a16a762a96646468762203524a13847057523875 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 23 Dec 2025 10:24:50 +0800 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: add reset support + +The SDHCI controller of SpacemiT K1 SoC requires two resets, add +support to explicitly request the reset line and deassert during +initialization phase. Still using devm_xx_get_optional() API to +make the request optional. + +Signed-off-by: Yixun Lan +Reviewed-by: Javier Martinez Canillas +Signed-off-by: Ulf Hansson +(cherry picked from commit 658b716c048684ad13d78280d69b883f181251da) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index 0cc97e23a2f9..a160e1d5d9bd 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + + #include "sdhci.h" +@@ -223,6 +224,21 @@ static inline int spacemit_sdhci_get_clocks(struct device *dev, + return 0; + } + ++static inline int spacemit_sdhci_get_resets(struct device *dev) ++{ ++ struct reset_control *rst; ++ ++ rst = devm_reset_control_get_optional_shared_deasserted(dev, "axi"); ++ if (IS_ERR(rst)) ++ return PTR_ERR(rst); ++ ++ rst = devm_reset_control_get_optional_exclusive_deasserted(dev, "sdh"); ++ if (IS_ERR(rst)) ++ return PTR_ERR(rst); ++ ++ return 0; ++} ++ + static const struct sdhci_ops spacemit_sdhci_ops = { + .get_max_clock = spacemit_sdhci_clk_get_max_clock, + .reset = spacemit_sdhci_reset, +@@ -284,6 +300,10 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) + if (ret) + goto err_pltfm; + ++ ret = spacemit_sdhci_get_resets(dev); ++ if (ret) ++ goto err_pltfm; ++ + ret = sdhci_add_host(host); + if (ret) + goto err_pltfm; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0197-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch b/SPECS/linux-lts/0197-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch deleted file mode 100644 index fd657fca32..0000000000 --- a/SPECS/linux-lts/0197-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch +++ /dev/null @@ -1,103 +0,0 @@ -From d3f0701d0caf105e3dca7e90f7611eb6111ae3e5 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Fri, 6 Feb 2026 10:32:02 +0800 -Subject: [PATCH 197/467] UPSTREAM: dt-bindings: mfd: spacemit,p1: Add - individual regulator supply properties - -Add supply properties that match the P1 PMIC's actual hardware topology -where each buck converter has its own VIN pin and LDO groups share -common input pins. Supply names are defined according to the pinout -names in the P1 datasheet. - -The existing "vin-supply" is dropped from the binding document as the -updated spacemit P1 driver no longer parses it. Only the per-rail names -("vin1-supply", "vin2-supply", ...) are supported. - -Signed-off-by: Guodong Xu -Acked-by: Conor Dooley -Reviewed-by: Alex Elder -Link: https://patch.msgid.link/20260206-spacemit-p1-v4-1-8f695d93811e@riscstar.com -Signed-off-by: Mark Brown -(cherry picked from commit 82ffa9610ba39d3628a9bec968ddc68fe2fe6612) -Signed-off-by: Han Gao ---- - .../devicetree/bindings/mfd/spacemit,p1.yaml | 49 ++++++++++++++++++- - 1 file changed, 47 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml b/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml -index c6593ac6ef6a..c67b1c6e4e4f 100644 ---- a/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml -+++ b/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml -@@ -27,8 +27,41 @@ properties: - interrupts: - maxItems: 1 - -- vin-supply: -- description: Input supply phandle. -+ vin1-supply: -+ description: -+ Power supply for BUCK1. Required if BUCK1 is defined. -+ -+ vin2-supply: -+ description: -+ Power supply for BUCK2. Required if BUCK2 is defined. -+ -+ vin3-supply: -+ description: -+ Power supply for BUCK3. Required if BUCK3 is defined. -+ -+ vin4-supply: -+ description: -+ Power supply for BUCK4. Required if BUCK4 is defined. -+ -+ vin5-supply: -+ description: -+ Power supply for BUCK5. Required if BUCK5 is defined. -+ -+ vin6-supply: -+ description: -+ Power supply for BUCK6. Required if BUCK6 is defined. -+ -+ aldoin-supply: -+ description: -+ Power supply for ALDO1-4. Required if any are defined. -+ -+ dldoin1-supply: -+ description: -+ Power supply for DLDO1-4. Required if any are defined. -+ -+ dldoin2-supply: -+ description: -+ Power supply for DLDO5-7. Required if any are defined. - - regulators: - type: object -@@ -58,6 +91,10 @@ examples: - compatible = "spacemit,p1"; - reg = <0x41>; - interrupts = <64>; -+ vin1-supply = <®_vcc_5v>; -+ vin5-supply = <®_vcc_5v>; -+ aldoin-supply = <®_vcc_5v>; -+ dldoin1-supply = <&buck5>; - - regulators { - buck1 { -@@ -68,6 +105,14 @@ examples: - regulator-always-on; - }; - -+ buck5: buck5 { -+ regulator-name = "buck5"; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ - aldo1 { - regulator-name = "aldo1"; - regulator-min-microvolt = <500000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch b/SPECS/linux-lts/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch new file mode 100644 index 0000000000..271bd70fc5 --- /dev/null +++ b/SPECS/linux-lts/0197-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch @@ -0,0 +1,37 @@ +From 3661bb1bda184323b7f27ca11c4f6aa2453a891b Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 22 Jan 2026 17:37:30 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add support + for K3 SoC + +The SDHCI controller found on SpacemiT K3 SoC share the same IP with +K1 generation, while fixed the broken 64BIT DMA issue. Introduce a +compatible string to enable support for it. + +Acked-by: Rob Herring (Arm) +Signed-off-by: Yixun Lan +Signed-off-by: Ulf Hansson +(cherry picked from commit b4206966e2d48883f04d5a2b2ae6c46b528245d3) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +index 13d9382058fb..383841369fb2 100644 +--- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml ++++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +@@ -14,7 +14,9 @@ allOf: + + properties: + compatible: +- const: spacemit,k1-sdhci ++ enum: ++ - spacemit,k1-sdhci ++ - spacemit,k3-sdhci + + reg: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch b/SPECS/linux-lts/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch new file mode 100644 index 0000000000..067922ab83 --- /dev/null +++ b/SPECS/linux-lts/0198-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch @@ -0,0 +1,62 @@ +From aef7fb87d55efc5bff2a628b6196c36b7eaf3e12 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 22 Jan 2026 17:37:31 +0800 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: spacemit: Add support for K3 + SoC + +The SDHCI controller found on SpacemiT K3 SoC share the same IP with K1 +generation and introduce a compatible data to denote the change that broken +64BIT DMA issue has been fixed. + +Signed-off-by: Yixun Lan +Signed-off-by: Ulf Hansson +(cherry picked from commit 1e9f43a1dbefd3de45b97545e5773d2b52dc7f02) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 19 +++++++++++++++++-- + 1 file changed, 17 insertions(+), 2 deletions(-) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index a160e1d5d9bd..455656f9842d 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -259,8 +259,20 @@ static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata = { + SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }; + ++static const struct sdhci_pltfm_data spacemit_sdhci_k3_pdata = { ++ .ops = &spacemit_sdhci_ops, ++ .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | ++ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | ++ SDHCI_QUIRK_32BIT_ADMA_SIZE | ++ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | ++ SDHCI_QUIRK_BROKEN_CARD_DETECTION | ++ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, ++}; ++ + static const struct of_device_id spacemit_sdhci_of_match[] = { +- { .compatible = "spacemit,k1-sdhci" }, ++ { .compatible = "spacemit,k1-sdhci", .data = &spacemit_sdhci_k1_pdata }, ++ { .compatible = "spacemit,k3-sdhci", .data = &spacemit_sdhci_k3_pdata }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, spacemit_sdhci_of_match); +@@ -271,10 +283,13 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) + struct spacemit_sdhci_host *sdhst; + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_host *host; ++ const struct sdhci_pltfm_data *data; + struct mmc_host_ops *mops; + int ret; + +- host = sdhci_pltfm_init(pdev, &spacemit_sdhci_k1_pdata, sizeof(*sdhst)); ++ data = of_device_get_match_data(&pdev->dev); ++ ++ host = sdhci_pltfm_init(pdev, data, sizeof(*sdhst)); + if (IS_ERR(host)) + return PTR_ERR(host); + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0198-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch b/SPECS/linux-lts/0198-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch deleted file mode 100644 index 369110a4e9..0000000000 --- a/SPECS/linux-lts/0198-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 9bd75aaa59fb6ab1d9e1b11f9f2ad77f1658b9a4 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Fri, 6 Feb 2026 10:32:03 +0800 -Subject: [PATCH 198/467] UPSTREAM: regulator: spacemit-p1: Update supply names - -Update supply names to match the P1 PMIC's actual hardware pinout where -each buck has an individual VIN pin (vin1-vin6) and LDO groups have -dedicated input pins (aldoin, dldoin1, dldoin2). - -This is an ABI change from the original "vin" and "buck5" supplies. -The P1/PMIC regulator has no consumers in the DTS tree yet. For the two -K1 boards in-tree (BPI-F3 and Jupiter), power settings come from -boot firmware, so a probe failure has minimal impact. - -Signed-off-by: Guodong Xu -Link: https://developer.spacemit.com/documentation?token=T1Btw2BdiiSlSXkAdibcoMetnag -[1] -Reviewed-by: Alex Elder -Link: https://patch.msgid.link/20260206-spacemit-p1-v4-2-8f695d93811e@riscstar.com -Signed-off-by: Mark Brown -(cherry picked from commit fbb4c52ccdcb4a612d2b7f800aa57090eeee16d7) -Signed-off-by: Han Gao ---- - drivers/regulator/spacemit-p1.c | 25 ++++++++++++++----------- - 1 file changed, 14 insertions(+), 11 deletions(-) - -diff --git a/drivers/regulator/spacemit-p1.c b/drivers/regulator/spacemit-p1.c -index 2b585ba01a93..57e6e00a73fa 100644 ---- a/drivers/regulator/spacemit-p1.c -+++ b/drivers/regulator/spacemit-p1.c -@@ -87,13 +87,16 @@ static const struct linear_range p1_ldo_ranges[] = { - } - - #define P1_BUCK_DESC(_n) \ -- P1_REG_DESC(BUCK, buck, _n, "vin", 0x47, BUCK_MASK, 255, p1_buck_ranges) -+ P1_REG_DESC(BUCK, buck, _n, "vin" #_n, 0x47, BUCK_MASK, 255, p1_buck_ranges) - - #define P1_ALDO_DESC(_n) \ -- P1_REG_DESC(ALDO, aldo, _n, "vin", 0x5b, LDO_MASK, 128, p1_ldo_ranges) -+ P1_REG_DESC(ALDO, aldo, _n, "aldoin", 0x5b, LDO_MASK, 128, p1_ldo_ranges) - --#define P1_DLDO_DESC(_n) \ -- P1_REG_DESC(DLDO, dldo, _n, "buck5", 0x67, LDO_MASK, 128, p1_ldo_ranges) -+#define P1_DLDO1_DESC(_n) \ -+ P1_REG_DESC(DLDO, dldo, _n, "dldoin1", 0x67, LDO_MASK, 128, p1_ldo_ranges) -+ -+#define P1_DLDO2_DESC(_n) \ -+ P1_REG_DESC(DLDO, dldo, _n, "dldoin2", 0x67, LDO_MASK, 128, p1_ldo_ranges) - - static const struct regulator_desc p1_regulator_desc[] = { - P1_BUCK_DESC(1), -@@ -108,13 +111,13 @@ static const struct regulator_desc p1_regulator_desc[] = { - P1_ALDO_DESC(3), - P1_ALDO_DESC(4), - -- P1_DLDO_DESC(1), -- P1_DLDO_DESC(2), -- P1_DLDO_DESC(3), -- P1_DLDO_DESC(4), -- P1_DLDO_DESC(5), -- P1_DLDO_DESC(6), -- P1_DLDO_DESC(7), -+ P1_DLDO1_DESC(1), -+ P1_DLDO1_DESC(2), -+ P1_DLDO1_DESC(3), -+ P1_DLDO1_DESC(4), -+ P1_DLDO2_DESC(5), -+ P1_DLDO2_DESC(6), -+ P1_DLDO2_DESC(7), - }; - - static int p1_regulator_probe(struct platform_device *pdev) --- -2.53.0 - diff --git a/SPECS/linux-lts/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch b/SPECS/linux-lts/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch new file mode 100644 index 0000000000..bd29a279bd --- /dev/null +++ b/SPECS/linux-lts/0199-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch @@ -0,0 +1,90 @@ +From 71fc35504a003f43684f36757050f5c7e1ca7c23 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Sun, 5 Apr 2026 15:41:53 +0000 +Subject: [RUYI PATCH] UPSTREAM: PCI: cadence: Add flags for disabling ASPM + capability for broken Root Ports + +Add flags for disabling the ASPM L0s/L1 capability for broken Root Ports +by clearing the corresponding bits in Link Capabilities Register through +the local management bus. This allows ASPM to be disabled on platforms +which don't support it. + +Signed-off-by: Yao Zi +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Helgaas +Tested-by: Han Gao +Tested-by: Chen Wang # Pioneerbox +Reviewed-by: Chen Wang +Link: https://patch.msgid.link/20260405154154.46829-2-me@ziyao.cc +(cherry picked from commit 5ccc76a87f1ec2422811e61be44165bfc9e7cf54) +Signed-off-by: Han Gao +--- + .../controller/cadence/pcie-cadence-host.c | 7 +++++++ + drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++ + 2 files changed, 26 insertions(+) + +diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c +index db3154c1eccb..0bc9e6e90e0e 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence-host.c ++++ b/drivers/pci/controller/cadence/pcie-cadence-host.c +@@ -147,6 +147,13 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) + cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0); + cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); + ++ value = cdns_pcie_rp_readl(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP); ++ if (rc->quirk_broken_aspm_l0s) ++ value &= ~PCI_EXP_LNKCAP_ASPM_L0S; ++ if (rc->quirk_broken_aspm_l1) ++ value &= ~PCI_EXP_LNKCAP_ASPM_L1; ++ cdns_pcie_rp_writel(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP, value); ++ + return 0; + } + +diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h +index 277f3706a4f4..574e9cf4d003 100644 +--- a/drivers/pci/controller/cadence/pcie-cadence.h ++++ b/drivers/pci/controller/cadence/pcie-cadence.h +@@ -115,6 +115,8 @@ struct cdns_pcie { + * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk + * @ecam_supported: Whether the ECAM is supported + * @no_inbound_map: Whether inbound mapping is supported ++ * @quirk_broken_aspm_l0s: Disable ASPM L0s support as quirk ++ * @quirk_broken_aspm_l1: Disable ASPM L1 support as quirk + */ + struct cdns_pcie_rc { + struct cdns_pcie pcie; +@@ -127,6 +129,8 @@ struct cdns_pcie_rc { + unsigned int quirk_detect_quiet_flag:1; + unsigned int ecam_supported:1; + unsigned int no_inbound_map:1; ++ unsigned int quirk_broken_aspm_l0s:1; ++ unsigned int quirk_broken_aspm_l1:1; + }; + + /** +@@ -338,6 +342,21 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) + return cdns_pcie_read_sz(addr, 0x2); + } + ++static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie, ++ u32 reg, u32 value) ++{ ++ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; ++ ++ cdns_pcie_write_sz(addr, 0x4, value); ++} ++ ++static inline u32 cdns_pcie_rp_readl(struct cdns_pcie *pcie, u32 reg) ++{ ++ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; ++ ++ return cdns_pcie_read_sz(addr, 0x4); ++} ++ + static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie, + u32 reg, u8 value) + { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0199-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch b/SPECS/linux-lts/0199-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch deleted file mode 100644 index ac158c2c11..0000000000 --- a/SPECS/linux-lts/0199-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 2d76e75bca7e55bd00d4506359572a867aa1b303 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 23 Dec 2025 10:24:50 +0800 -Subject: [PATCH 199/467] UPSTREAM: mmc: sdhci-of-k1: add reset support - -The SDHCI controller of SpacemiT K1 SoC requires two resets, add -support to explicitly request the reset line and deassert during -initialization phase. Still using devm_xx_get_optional() API to -make the request optional. - -Signed-off-by: Yixun Lan -Reviewed-by: Javier Martinez Canillas -Signed-off-by: Ulf Hansson -(cherry picked from commit 658b716c048684ad13d78280d69b883f181251da) -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index 0cc97e23a2f9..a160e1d5d9bd 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - - #include "sdhci.h" -@@ -223,6 +224,21 @@ static inline int spacemit_sdhci_get_clocks(struct device *dev, - return 0; - } - -+static inline int spacemit_sdhci_get_resets(struct device *dev) -+{ -+ struct reset_control *rst; -+ -+ rst = devm_reset_control_get_optional_shared_deasserted(dev, "axi"); -+ if (IS_ERR(rst)) -+ return PTR_ERR(rst); -+ -+ rst = devm_reset_control_get_optional_exclusive_deasserted(dev, "sdh"); -+ if (IS_ERR(rst)) -+ return PTR_ERR(rst); -+ -+ return 0; -+} -+ - static const struct sdhci_ops spacemit_sdhci_ops = { - .get_max_clock = spacemit_sdhci_clk_get_max_clock, - .reset = spacemit_sdhci_reset, -@@ -284,6 +300,10 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) - if (ret) - goto err_pltfm; - -+ ret = spacemit_sdhci_get_resets(dev); -+ if (ret) -+ goto err_pltfm; -+ - ret = sdhci_add_host(host); - if (ret) - goto err_pltfm; --- -2.53.0 - diff --git a/SPECS/linux-lts/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch b/SPECS/linux-lts/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch new file mode 100644 index 0000000000..863472668a --- /dev/null +++ b/SPECS/linux-lts/0200-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch @@ -0,0 +1,47 @@ +From b79c6a8e8737f691e21ed1f9492ed9784de03550 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Sun, 5 Apr 2026 15:41:54 +0000 +Subject: [RUYI PATCH] UPSTREAM: PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 + PCIe Root Ports + +Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states +for devicetree platforms") force enables ASPM on all device tree platforms, +the SG2042 Root Ports are breaking as they advertise L0s and L1 +capabilities without supporting them. + +Set ASPM quirks to disable the L0s and L1 capabilities for the Root Ports +so that these broken link states won't be enabled. + +Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042") +Co-developed-by: Inochi Amaoto +Signed-off-by: Inochi Amaoto +Signed-off-by: Yao Zi +[mani: commit log] +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Helgaas +Tested-by: Han Gao +Tested-by: Chen Wang # Pioneerbox +Reviewed-by: Chen Wang +Link: https://patch.msgid.link/20260405154154.46829-3-me@ziyao.cc +(cherry picked from commit 988ef706cdd8a72e61dd90c0d0554eec4df7594a) +Signed-off-by: Han Gao +--- + drivers/pci/controller/cadence/pcie-sg2042.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c +index 0c50c74d03ee..4a2af4d0713e 100644 +--- a/drivers/pci/controller/cadence/pcie-sg2042.c ++++ b/drivers/pci/controller/cadence/pcie-sg2042.c +@@ -48,6 +48,8 @@ static int sg2042_pcie_probe(struct platform_device *pdev) + bridge->child_ops = &sg2042_pcie_child_ops; + + rc = pci_host_bridge_priv(bridge); ++ rc->quirk_broken_aspm_l0s = 1; ++ rc->quirk_broken_aspm_l1 = 1; + pcie = &rc->pcie; + pcie->dev = dev; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0200-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch b/SPECS/linux-lts/0200-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch deleted file mode 100644 index ab4886f545..0000000000 --- a/SPECS/linux-lts/0200-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch +++ /dev/null @@ -1,37 +0,0 @@ -From c062f31f265429d1f2fce4dfb8396648bb008bee Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 22 Jan 2026 17:37:30 +0800 -Subject: [PATCH 200/467] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add - support for K3 SoC - -The SDHCI controller found on SpacemiT K3 SoC share the same IP with -K1 generation, while fixed the broken 64BIT DMA issue. Introduce a -compatible string to enable support for it. - -Acked-by: Rob Herring (Arm) -Signed-off-by: Yixun Lan -Signed-off-by: Ulf Hansson -(cherry picked from commit b4206966e2d48883f04d5a2b2ae6c46b528245d3) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -index 13d9382058fb..383841369fb2 100644 ---- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -+++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -@@ -14,7 +14,9 @@ allOf: - - properties: - compatible: -- const: spacemit,k1-sdhci -+ enum: -+ - spacemit,k1-sdhci -+ - spacemit,k3-sdhci - - reg: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch b/SPECS/linux-lts/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch new file mode 100644 index 0000000000..45d9a8f9de --- /dev/null +++ b/SPECS/linux-lts/0201-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch @@ -0,0 +1,51 @@ +From e8797e3dcfc25acbd3f8c8b268ec9d8bd1c28295 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Tue, 10 Mar 2026 00:24:56 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: hwmon: moortec,mr75203: adapt + multipleOf for T-Head TH1520 + +The G and J coefficients provided by T-Head TH1520 manual (which calls +them A and C coefficients and calls H coefficient in the binding as B) +have 1/100 degree Celsius precision (the values are 42.74 and -0.16 +respectively), however the binding currently only allows coefficients as +precise as 100 milli-Celsius (1/10 degree Celsius). + +Change the multipleOf value of these two coefficients to 10 (in the unit +of milli-Celsius) to satisfy the need of TH1520. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Drew Fustini +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20260309162457.4128205-2-zhengxingda@iscas.ac.cn +Signed-off-by: Guenter Roeck +(cherry picked from commit 967ee29c103a44c6e584a5e37401968a69e54a0c) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml +index 56db2292f062..7d57c2934a8a 100644 +--- a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml ++++ b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml +@@ -105,7 +105,7 @@ properties: + G coefficient for temperature equation. + Default for series 5 = 60000 + Default for series 6 = 57400 +- multipleOf: 100 ++ multipleOf: 10 + minimum: 1000 + $ref: /schemas/types.yaml#/definitions/uint32 + +@@ -131,7 +131,7 @@ properties: + J coefficient for temperature equation. + Default for series 5 = -100 + Default for series 6 = 0 +- multipleOf: 100 ++ multipleOf: 10 + maximum: 0 + $ref: /schemas/types.yaml#/definitions/int32 + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0201-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch b/SPECS/linux-lts/0201-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch deleted file mode 100644 index 8b39d10761..0000000000 --- a/SPECS/linux-lts/0201-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch +++ /dev/null @@ -1,62 +0,0 @@ -From bf01dbbc2a84e73472ec8407e03ad78c12a261d7 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 22 Jan 2026 17:37:31 +0800 -Subject: [PATCH 201/467] UPSTREAM: mmc: sdhci-of-k1: spacemit: Add support for - K3 SoC - -The SDHCI controller found on SpacemiT K3 SoC share the same IP with K1 -generation and introduce a compatible data to denote the change that broken -64BIT DMA issue has been fixed. - -Signed-off-by: Yixun Lan -Signed-off-by: Ulf Hansson -(cherry picked from commit 1e9f43a1dbefd3de45b97545e5773d2b52dc7f02) -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 19 +++++++++++++++++-- - 1 file changed, 17 insertions(+), 2 deletions(-) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index a160e1d5d9bd..455656f9842d 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -259,8 +259,20 @@ static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata = { - SDHCI_QUIRK2_PRESET_VALUE_BROKEN, - }; - -+static const struct sdhci_pltfm_data spacemit_sdhci_k3_pdata = { -+ .ops = &spacemit_sdhci_ops, -+ .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | -+ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | -+ SDHCI_QUIRK_32BIT_ADMA_SIZE | -+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | -+ SDHCI_QUIRK_BROKEN_CARD_DETECTION | -+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, -+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, -+}; -+ - static const struct of_device_id spacemit_sdhci_of_match[] = { -- { .compatible = "spacemit,k1-sdhci" }, -+ { .compatible = "spacemit,k1-sdhci", .data = &spacemit_sdhci_k1_pdata }, -+ { .compatible = "spacemit,k3-sdhci", .data = &spacemit_sdhci_k3_pdata }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, spacemit_sdhci_of_match); -@@ -271,10 +283,13 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) - struct spacemit_sdhci_host *sdhst; - struct sdhci_pltfm_host *pltfm_host; - struct sdhci_host *host; -+ const struct sdhci_pltfm_data *data; - struct mmc_host_ops *mops; - int ret; - -- host = sdhci_pltfm_init(pdev, &spacemit_sdhci_k1_pdata, sizeof(*sdhst)); -+ data = of_device_get_match_data(&pdev->dev); -+ -+ host = sdhci_pltfm_init(pdev, data, sizeof(*sdhst)); - if (IS_ERR(host)) - return PTR_ERR(host); - --- -2.53.0 - diff --git a/SPECS/linux-lts/0202-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch b/SPECS/linux-lts/0202-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch deleted file mode 100644 index f4079da8cb..0000000000 --- a/SPECS/linux-lts/0202-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 666104d46e408b7abf14799de82ab3cefcdf0964 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Sun, 5 Apr 2026 15:41:53 +0000 -Subject: [PATCH 202/467] UPSTREAM: PCI: cadence: Add flags for disabling ASPM - capability for broken Root Ports - -Add flags for disabling the ASPM L0s/L1 capability for broken Root Ports -by clearing the corresponding bits in Link Capabilities Register through -the local management bus. This allows ASPM to be disabled on platforms -which don't support it. - -Signed-off-by: Yao Zi -Signed-off-by: Manivannan Sadhasivam -Signed-off-by: Bjorn Helgaas -Tested-by: Han Gao -Tested-by: Chen Wang # Pioneerbox -Reviewed-by: Chen Wang -Link: https://patch.msgid.link/20260405154154.46829-2-me@ziyao.cc -(cherry picked from commit 5ccc76a87f1ec2422811e61be44165bfc9e7cf54) -Signed-off-by: Han Gao ---- - .../controller/cadence/pcie-cadence-host.c | 7 +++++++ - drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++ - 2 files changed, 26 insertions(+) - -diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c -index db3154c1eccb..0bc9e6e90e0e 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence-host.c -+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c -@@ -147,6 +147,13 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) - cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0); - cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); - -+ value = cdns_pcie_rp_readl(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP); -+ if (rc->quirk_broken_aspm_l0s) -+ value &= ~PCI_EXP_LNKCAP_ASPM_L0S; -+ if (rc->quirk_broken_aspm_l1) -+ value &= ~PCI_EXP_LNKCAP_ASPM_L1; -+ cdns_pcie_rp_writel(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP, value); -+ - return 0; - } - -diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h -index 277f3706a4f4..574e9cf4d003 100644 ---- a/drivers/pci/controller/cadence/pcie-cadence.h -+++ b/drivers/pci/controller/cadence/pcie-cadence.h -@@ -115,6 +115,8 @@ struct cdns_pcie { - * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk - * @ecam_supported: Whether the ECAM is supported - * @no_inbound_map: Whether inbound mapping is supported -+ * @quirk_broken_aspm_l0s: Disable ASPM L0s support as quirk -+ * @quirk_broken_aspm_l1: Disable ASPM L1 support as quirk - */ - struct cdns_pcie_rc { - struct cdns_pcie pcie; -@@ -127,6 +129,8 @@ struct cdns_pcie_rc { - unsigned int quirk_detect_quiet_flag:1; - unsigned int ecam_supported:1; - unsigned int no_inbound_map:1; -+ unsigned int quirk_broken_aspm_l0s:1; -+ unsigned int quirk_broken_aspm_l1:1; - }; - - /** -@@ -338,6 +342,21 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) - return cdns_pcie_read_sz(addr, 0x2); - } - -+static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie, -+ u32 reg, u32 value) -+{ -+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; -+ -+ cdns_pcie_write_sz(addr, 0x4, value); -+} -+ -+static inline u32 cdns_pcie_rp_readl(struct cdns_pcie *pcie, u32 reg) -+{ -+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; -+ -+ return cdns_pcie_read_sz(addr, 0x4); -+} -+ - static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie, - u32 reg, u8 value) - { --- -2.53.0 - diff --git a/SPECS/linux-lts/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch b/SPECS/linux-lts/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch new file mode 100644 index 0000000000..3011e77bd5 --- /dev/null +++ b/SPECS/linux-lts/0202-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch @@ -0,0 +1,116 @@ +From 42218f60a7def59ca6f9513365c5aed9fb77a124 Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Tue, 10 Mar 2026 11:41:12 +0000 +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Disable interrupts before + suspending the GPU + +This is an additional safety layer to ensure no accesses to the GPU +registers can be made while it is powered off. + +While we can disable IRQ generation from GPU, META firmware, MIPS +firmware and for safety events, we cannot do the same for the RISC-V +firmware. +To keep a unified approach, once the firmware has completed its power +off sequence, disable IRQs for the while GPU at the kernel level +instead. + +Signed-off-by: Alessio Belle +Reviewed-by: Matt Coster +Link: https://patch.msgid.link/20260310-drain-irqs-before-suspend-v1-2-bf4f9ed68e75@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 74ef7844dd8c27d6b94ebc102bb4677edd3e7696) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_power.c | 33 +++++++++++++++++-------- + 1 file changed, 23 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imagination/pvr_power.c +index a7994457900d..c03bbf139562 100644 +--- a/drivers/gpu/drm/imagination/pvr_power.c ++++ b/drivers/gpu/drm/imagination/pvr_power.c +@@ -91,9 +91,9 @@ pvr_power_request_pwr_off(struct pvr_device *pvr_dev) + static int + pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm_suspend) + { +- if (!hard_reset) { +- int err; ++ int err; + ++ if (!hard_reset) { + cancel_delayed_work_sync(&pvr_dev->watchdog.work); + + err = pvr_power_request_idle(pvr_dev); +@@ -106,33 +106,46 @@ pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm_suspe + } + + if (rpm_suspend) { +- /* Wait for late processing of GPU or firmware IRQs in other cores */ +- synchronize_irq(pvr_dev->irq); ++ /* This also waits for late processing of GPU or firmware IRQs in other cores */ ++ disable_irq(pvr_dev->irq); + } + +- return pvr_fw_stop(pvr_dev); ++ err = pvr_fw_stop(pvr_dev); ++ if (err && rpm_suspend) ++ enable_irq(pvr_dev->irq); ++ ++ return err; + } + + static int +-pvr_power_fw_enable(struct pvr_device *pvr_dev) ++pvr_power_fw_enable(struct pvr_device *pvr_dev, bool rpm_resume) + { + int err; + ++ if (rpm_resume) ++ enable_irq(pvr_dev->irq); ++ + err = pvr_fw_start(pvr_dev); + if (err) +- return err; ++ goto out; + + err = pvr_wait_for_fw_boot(pvr_dev); + if (err) { + drm_err(from_pvr_device(pvr_dev), "Firmware failed to boot\n"); + pvr_fw_stop(pvr_dev); +- return err; ++ goto out; + } + + queue_delayed_work(pvr_dev->sched_wq, &pvr_dev->watchdog.work, + msecs_to_jiffies(WATCHDOG_TIME_MS)); + + return 0; ++ ++out: ++ if (rpm_resume) ++ disable_irq(pvr_dev->irq); ++ ++ return err; + } + + bool +@@ -395,7 +408,7 @@ pvr_power_device_resume(struct device *dev) + goto err_drm_dev_exit; + + if (pvr_dev->fw_dev.booted) { +- err = pvr_power_fw_enable(pvr_dev); ++ err = pvr_power_fw_enable(pvr_dev, true); + if (err) + goto err_power_off; + } +@@ -554,7 +567,7 @@ pvr_power_reset(struct pvr_device *pvr_dev, bool hard_reset) + + pvr_fw_irq_clear(pvr_dev); + +- err = pvr_power_fw_enable(pvr_dev); ++ err = pvr_power_fw_enable(pvr_dev, false); + } + + if (err && hard_reset) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0203-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch b/SPECS/linux-lts/0203-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch deleted file mode 100644 index 9fcf206ede..0000000000 --- a/SPECS/linux-lts/0203-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 97c5f5dec6275526d950871d6697610efd8bbfc9 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Sun, 5 Apr 2026 15:41:54 +0000 -Subject: [PATCH 203/467] UPSTREAM: PCI: sg2042: Avoid L0s and L1 on Sophgo - 2042 PCIe Root Ports - -Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states -for devicetree platforms") force enables ASPM on all device tree platforms, -the SG2042 Root Ports are breaking as they advertise L0s and L1 -capabilities without supporting them. - -Set ASPM quirks to disable the L0s and L1 capabilities for the Root Ports -so that these broken link states won't be enabled. - -Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042") -Co-developed-by: Inochi Amaoto -Signed-off-by: Inochi Amaoto -Signed-off-by: Yao Zi -[mani: commit log] -Signed-off-by: Manivannan Sadhasivam -Signed-off-by: Bjorn Helgaas -Tested-by: Han Gao -Tested-by: Chen Wang # Pioneerbox -Reviewed-by: Chen Wang -Link: https://patch.msgid.link/20260405154154.46829-3-me@ziyao.cc -(cherry picked from commit 988ef706cdd8a72e61dd90c0d0554eec4df7594a) -Signed-off-by: Han Gao ---- - drivers/pci/controller/cadence/pcie-sg2042.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c -index 0c50c74d03ee..4a2af4d0713e 100644 ---- a/drivers/pci/controller/cadence/pcie-sg2042.c -+++ b/drivers/pci/controller/cadence/pcie-sg2042.c -@@ -48,6 +48,8 @@ static int sg2042_pcie_probe(struct platform_device *pdev) - bridge->child_ops = &sg2042_pcie_child_ops; - - rc = pci_host_bridge_priv(bridge); -+ rc->quirk_broken_aspm_l0s = 1; -+ rc->quirk_broken_aspm_l1 = 1; - pcie = &rc->pcie; - pcie->dev = dev; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch b/SPECS/linux-lts/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch new file mode 100644 index 0000000000..97daa0a8b0 --- /dev/null +++ b/SPECS/linux-lts/0203-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch @@ -0,0 +1,104 @@ +From 9714f16b48717549d0332bbcd37661290bf0a765 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:20 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add DPU and HDMI device + tree nodes + +T-Head TH1520 SoC contains a Verisilicon DC8200 display controller +(called DPU in manual) and a Synopsys DesignWare HDMI TX controller. + +Add device tree nodes to them. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Tested-by: Han Gao +Tested-by: Michal Wilczynski +Reviewed-by: Drew Fustini +Reviewed-by: Luca Ceresoli +Signed-off-by: Drew Fustini +(cherry picked from commit 5634f777a6a94db316f9b26c00525320c3b582c2) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 66 +++++++++++++++++++++++++++ + 1 file changed, 66 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index c24d6b779fa4..aa6c9afa1a20 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -555,6 +555,72 @@ clk_vo: clock-controller@ffef528050 { + #clock-cells = <1>; + }; + ++ hdmi: hdmi@ffef540000 { ++ compatible = "thead,th1520-dw-hdmi"; ++ reg = <0xff 0xef540000 0x0 0x40000>; ++ reg-io-width = <4>; ++ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_vo CLK_HDMI_PCLK>, ++ <&clk_vo CLK_HDMI_SFR>, ++ <&clk_vo CLK_HDMI_CEC>, ++ <&clk_vo CLK_HDMI_PIXCLK>; ++ clock-names = "iahb", "isfr", "cec", "pix"; ++ resets = <&rst TH1520_RESET_ID_HDMI>, ++ <&rst TH1520_RESET_ID_HDMI_APB>; ++ reset-names = "main", "apb"; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ hdmi_in: endpoint { ++ remote-endpoint = <&dpu_out_dp1>; ++ }; ++ }; ++ ++ hdmi_out_port: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ ++ dpu: display@ffef600000 { ++ compatible = "thead,th1520-dc8200", "verisilicon,dc"; ++ reg = <0xff 0xef600000 0x0 0x100000>; ++ interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_vo CLK_DPU_CCLK>, ++ <&clk_vo CLK_DPU_ACLK>, ++ <&clk_vo CLK_DPU_HCLK>, ++ <&clk_vo CLK_DPU_PIXELCLK0>, ++ <&clk_vo CLK_DPU_PIXELCLK1>; ++ clock-names = "core", "axi", "ahb", "pix0", "pix1"; ++ resets = <&rst TH1520_RESET_ID_DPU_CORE>, ++ <&rst TH1520_RESET_ID_DPU_AXI>, ++ <&rst TH1520_RESET_ID_DPU_AHB>; ++ reset-names = "core", "axi", "ahb"; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dpu_port1: port@1 { ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dpu_out_dp1: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&hdmi_in>; ++ }; ++ }; ++ }; ++ }; ++ + dmac0: dma-controller@ffefc00000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0xff 0xefc00000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0204-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch b/SPECS/linux-lts/0204-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch deleted file mode 100644 index 2ddec8736f..0000000000 --- a/SPECS/linux-lts/0204-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 9fa99cb8701fa1bb6152da334dca564f23e9f456 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Tue, 10 Mar 2026 00:24:56 +0800 -Subject: [PATCH 204/467] UPSTREAM: dt-bindings: hwmon: moortec,mr75203: adapt - multipleOf for T-Head TH1520 - -The G and J coefficients provided by T-Head TH1520 manual (which calls -them A and C coefficients and calls H coefficient in the binding as B) -have 1/100 degree Celsius precision (the values are 42.74 and -0.16 -respectively), however the binding currently only allows coefficients as -precise as 100 milli-Celsius (1/10 degree Celsius). - -Change the multipleOf value of these two coefficients to 10 (in the unit -of milli-Celsius) to satisfy the need of TH1520. - -Signed-off-by: Icenowy Zheng -Reviewed-by: Drew Fustini -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20260309162457.4128205-2-zhengxingda@iscas.ac.cn -Signed-off-by: Guenter Roeck -(cherry picked from commit 967ee29c103a44c6e584a5e37401968a69e54a0c) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml -index 56db2292f062..7d57c2934a8a 100644 ---- a/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml -+++ b/Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml -@@ -105,7 +105,7 @@ properties: - G coefficient for temperature equation. - Default for series 5 = 60000 - Default for series 6 = 57400 -- multipleOf: 100 -+ multipleOf: 10 - minimum: 1000 - $ref: /schemas/types.yaml#/definitions/uint32 - -@@ -131,7 +131,7 @@ properties: - J coefficient for temperature equation. - Default for series 5 = -100 - Default for series 6 = 0 -- multipleOf: 100 -+ multipleOf: 10 - maximum: 0 - $ref: /schemas/types.yaml#/definitions/int32 - --- -2.53.0 - diff --git a/SPECS/linux-lts/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch b/SPECS/linux-lts/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch new file mode 100644 index 0000000000..df92d3aeea --- /dev/null +++ b/SPECS/linux-lts/0204-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch @@ -0,0 +1,70 @@ +From 4633a7a2c68426c3f3fc28382fd6cba7df6134d8 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 29 Jan 2026 10:39:21 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: lichee-pi-4a: enable HDMI + +Lichee Pi 4A board features a HDMI Type-A connector connected to the +HDMI TX controller of TH1520 SoC. + +Add a device tree node describing the connector, connect it to the HDMI +controller, and enable everything on this display pipeline. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Tested-by: Han Gao +Tested-by: Michal Wilczynski +Reviewed-by: Luca Ceresoli +Reviewed-by: Drew Fustini +Signed-off-by: Drew Fustini +(cherry picked from commit 9c99a784d9117a192ebf779d4f72ebec435ada97) +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 25 +++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index c58c2085ca92..7cb7d28683bc 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -29,6 +29,17 @@ chosen { + stdout-path = "serial0:115200n8"; + }; + ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + thermal-zones { + cpu-thermal { + polling-delay = <1000>; +@@ -121,6 +132,20 @@ rx-pins { + }; + }; + ++&dpu { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out_port { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0205-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch b/SPECS/linux-lts/0205-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch deleted file mode 100644 index eb78cafb3a..0000000000 --- a/SPECS/linux-lts/0205-UPSTREAM-drm-imagination-Disable-interrupts-before-s.patch +++ /dev/null @@ -1,116 +0,0 @@ -From 2575af4e9ef38dd97f241b4be5afd8a68de35365 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Tue, 10 Mar 2026 11:41:12 +0000 -Subject: [PATCH 205/467] UPSTREAM: drm/imagination: Disable interrupts before - suspending the GPU - -This is an additional safety layer to ensure no accesses to the GPU -registers can be made while it is powered off. - -While we can disable IRQ generation from GPU, META firmware, MIPS -firmware and for safety events, we cannot do the same for the RISC-V -firmware. -To keep a unified approach, once the firmware has completed its power -off sequence, disable IRQs for the while GPU at the kernel level -instead. - -Signed-off-by: Alessio Belle -Reviewed-by: Matt Coster -Link: https://patch.msgid.link/20260310-drain-irqs-before-suspend-v1-2-bf4f9ed68e75@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 74ef7844dd8c27d6b94ebc102bb4677edd3e7696) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_power.c | 33 +++++++++++++++++-------- - 1 file changed, 23 insertions(+), 10 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imagination/pvr_power.c -index a7994457900d..c03bbf139562 100644 ---- a/drivers/gpu/drm/imagination/pvr_power.c -+++ b/drivers/gpu/drm/imagination/pvr_power.c -@@ -91,9 +91,9 @@ pvr_power_request_pwr_off(struct pvr_device *pvr_dev) - static int - pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm_suspend) - { -- if (!hard_reset) { -- int err; -+ int err; - -+ if (!hard_reset) { - cancel_delayed_work_sync(&pvr_dev->watchdog.work); - - err = pvr_power_request_idle(pvr_dev); -@@ -106,33 +106,46 @@ pvr_power_fw_disable(struct pvr_device *pvr_dev, bool hard_reset, bool rpm_suspe - } - - if (rpm_suspend) { -- /* Wait for late processing of GPU or firmware IRQs in other cores */ -- synchronize_irq(pvr_dev->irq); -+ /* This also waits for late processing of GPU or firmware IRQs in other cores */ -+ disable_irq(pvr_dev->irq); - } - -- return pvr_fw_stop(pvr_dev); -+ err = pvr_fw_stop(pvr_dev); -+ if (err && rpm_suspend) -+ enable_irq(pvr_dev->irq); -+ -+ return err; - } - - static int --pvr_power_fw_enable(struct pvr_device *pvr_dev) -+pvr_power_fw_enable(struct pvr_device *pvr_dev, bool rpm_resume) - { - int err; - -+ if (rpm_resume) -+ enable_irq(pvr_dev->irq); -+ - err = pvr_fw_start(pvr_dev); - if (err) -- return err; -+ goto out; - - err = pvr_wait_for_fw_boot(pvr_dev); - if (err) { - drm_err(from_pvr_device(pvr_dev), "Firmware failed to boot\n"); - pvr_fw_stop(pvr_dev); -- return err; -+ goto out; - } - - queue_delayed_work(pvr_dev->sched_wq, &pvr_dev->watchdog.work, - msecs_to_jiffies(WATCHDOG_TIME_MS)); - - return 0; -+ -+out: -+ if (rpm_resume) -+ disable_irq(pvr_dev->irq); -+ -+ return err; - } - - bool -@@ -395,7 +408,7 @@ pvr_power_device_resume(struct device *dev) - goto err_drm_dev_exit; - - if (pvr_dev->fw_dev.booted) { -- err = pvr_power_fw_enable(pvr_dev); -+ err = pvr_power_fw_enable(pvr_dev, true); - if (err) - goto err_power_off; - } -@@ -554,7 +567,7 @@ pvr_power_reset(struct pvr_device *pvr_dev, bool hard_reset) - - pvr_fw_irq_clear(pvr_dev); - -- err = pvr_power_fw_enable(pvr_dev); -+ err = pvr_power_fw_enable(pvr_dev, false); - } - - if (err && hard_reset) --- -2.53.0 - diff --git a/SPECS/linux-lts/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch b/SPECS/linux-lts/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch new file mode 100644 index 0000000000..dfee292fb6 --- /dev/null +++ b/SPECS/linux-lts/0205-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch @@ -0,0 +1,39 @@ +From 00020f3b46c3943b6ce714ac17de5fd1573b399b Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Tue, 10 Mar 2026 00:24:57 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: th1520: add coefficients to + the PVT node + +The manual of TH1520 contains a set of coefficients a little different +to the driver default ones. + +Add them to the device tree node of PVT. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Icenowy Zheng +Reviewed-by: Drew Fustini +Signed-off-by: Drew Fustini +(cherry picked from commit a7aa874b69460896349985833059a764e688f1d0) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index aa6c9afa1a20..c65b71d9a1b8 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -782,6 +782,10 @@ pvt: pvt@fffff4e000 { + reg-names = "common", "ts", "pd", "vm"; + clocks = <&aonsys_clk>; + #thermal-sensor-cells = <1>; ++ moortec,ts-coeff-g = <42740>; ++ moortec,ts-coeff-h = <220500>; ++ moortec,ts-coeff-j = <(-160)>; ++ moortec,ts-coeff-cal5 = <4094>; + }; + + gpio@fffff52000 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0206-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch b/SPECS/linux-lts/0206-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch deleted file mode 100644 index 279438ed87..0000000000 --- a/SPECS/linux-lts/0206-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 889a08c4fbd66cd2cccce2fe6c281d18a78edf6f Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:20 +0800 -Subject: [PATCH 206/467] UPSTREAM: riscv: dts: thead: add DPU and HDMI device - tree nodes - -T-Head TH1520 SoC contains a Verisilicon DC8200 display controller -(called DPU in manual) and a Synopsys DesignWare HDMI TX controller. - -Add device tree nodes to them. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Tested-by: Han Gao -Tested-by: Michal Wilczynski -Reviewed-by: Drew Fustini -Reviewed-by: Luca Ceresoli -Signed-off-by: Drew Fustini -(cherry picked from commit 5634f777a6a94db316f9b26c00525320c3b582c2) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 66 +++++++++++++++++++++++++++ - 1 file changed, 66 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index c24d6b779fa4..aa6c9afa1a20 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -555,6 +555,72 @@ clk_vo: clock-controller@ffef528050 { - #clock-cells = <1>; - }; - -+ hdmi: hdmi@ffef540000 { -+ compatible = "thead,th1520-dw-hdmi"; -+ reg = <0xff 0xef540000 0x0 0x40000>; -+ reg-io-width = <4>; -+ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_vo CLK_HDMI_PCLK>, -+ <&clk_vo CLK_HDMI_SFR>, -+ <&clk_vo CLK_HDMI_CEC>, -+ <&clk_vo CLK_HDMI_PIXCLK>; -+ clock-names = "iahb", "isfr", "cec", "pix"; -+ resets = <&rst TH1520_RESET_ID_HDMI>, -+ <&rst TH1520_RESET_ID_HDMI_APB>; -+ reset-names = "main", "apb"; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ hdmi_in: endpoint { -+ remote-endpoint = <&dpu_out_dp1>; -+ }; -+ }; -+ -+ hdmi_out_port: port@1 { -+ reg = <1>; -+ }; -+ }; -+ }; -+ -+ dpu: display@ffef600000 { -+ compatible = "thead,th1520-dc8200", "verisilicon,dc"; -+ reg = <0xff 0xef600000 0x0 0x100000>; -+ interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_vo CLK_DPU_CCLK>, -+ <&clk_vo CLK_DPU_ACLK>, -+ <&clk_vo CLK_DPU_HCLK>, -+ <&clk_vo CLK_DPU_PIXELCLK0>, -+ <&clk_vo CLK_DPU_PIXELCLK1>; -+ clock-names = "core", "axi", "ahb", "pix0", "pix1"; -+ resets = <&rst TH1520_RESET_ID_DPU_CORE>, -+ <&rst TH1520_RESET_ID_DPU_AXI>, -+ <&rst TH1520_RESET_ID_DPU_AHB>; -+ reset-names = "core", "axi", "ahb"; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dpu_port1: port@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dpu_out_dp1: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&hdmi_in>; -+ }; -+ }; -+ }; -+ }; -+ - dmac0: dma-controller@ffefc00000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0xff 0xefc00000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch b/SPECS/linux-lts/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch new file mode 100644 index 0000000000..03da857375 --- /dev/null +++ b/SPECS/linux-lts/0206-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch @@ -0,0 +1,67 @@ +From 1cce6a25c0cf7aab271eb21e6d8b9ed58ed13b84 Mon Sep 17 00:00:00 2001 +From: Robert Mazur +Date: Wed, 25 Mar 2026 09:18:59 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: beaglev-ahead: enable HDMI + output + +The BeagleV Ahead board includes a micro HDMI connector (Type-D) +wired to the TH1520 SoC's HDMI transmitter. + +Enable the display pipeline by adding the HDMI connector node, +connecting it to the HDMI controller, and activating the DPU +and HDMI nodes. + +Signed-off-by: Robert Mazur +Signed-off-by: Drew Fustini +(cherry picked from commit 74ec3d52c0035b662ec295bef2bbffad68446391) +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-beaglev-ahead.dts | 25 +++++++++++++++++++ + 1 file changed, 25 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +index 21c33f165ba9..91f3f9b987bc 100644 +--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts ++++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +@@ -75,6 +75,17 @@ led-5 { + label = "led5"; + }; + }; ++ ++ hdmi-connector { ++ compatible = "hdmi-connector"; ++ type = "d"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; + }; + + &osc { +@@ -236,6 +247,20 @@ &sdio0 { + status = "okay"; + }; + ++&dpu { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out_port { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch b/SPECS/linux-lts/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch new file mode 100644 index 0000000000..0128ba9bc1 --- /dev/null +++ b/SPECS/linux-lts/0207-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch @@ -0,0 +1,107 @@ +From d2ce0203a4d1455b03013278280f7ac698fce115 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Sat, 7 Feb 2026 23:08:21 +0800 +Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: move i2c_xfer_msg() + +The upcoming PIO support requires a wait_pio_xfer() helper, which is +invoked from xfer_msg(). + +Since wait_pio_xfer() depends on err_check(), move the definition of +xfer_msg() after err_check() to avoid a forward declaration of +err_check(). + +Reviewed-by: Aurelien Jarno +Reviewed-by: Alex Elder +Signed-off-by: Troy Mitchell +Tested-by: Aurelien Jarno +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20260207-b4-k3-i2c-pio-v7-1-626942d94d91@linux.spacemit.com +(cherry picked from commit 5b74da8e6cf7e2b5aed0836c733238c0fd7235af) +Signed-off-by: Han Gao +--- + drivers/i2c/busses/i2c-k1.c | 62 ++++++++++++++++++------------------- + 1 file changed, 31 insertions(+), 31 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index d0948a16de3e..6787a51e7391 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -305,37 +305,6 @@ static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) + writel(val, i2c->base + SPACEMIT_ICR); + } + +-static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) +-{ +- unsigned long time_left; +- struct i2c_msg *msg; +- +- for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { +- msg = &i2c->msgs[i2c->msg_idx]; +- i2c->msg_buf = msg->buf; +- i2c->unprocessed = msg->len; +- i2c->status = 0; +- +- reinit_completion(&i2c->complete); +- +- spacemit_i2c_start(i2c); +- +- time_left = wait_for_completion_timeout(&i2c->complete, +- i2c->adapt.timeout); +- if (!time_left) { +- dev_err(i2c->dev, "msg completion timeout\n"); +- spacemit_i2c_conditionally_reset_bus(i2c); +- spacemit_i2c_reset(i2c); +- return -ETIMEDOUT; +- } +- +- if (i2c->status & SPACEMIT_SR_ERR) +- return spacemit_i2c_handle_err(i2c); +- } +- +- return 0; +-} +- + static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c) + { + if (i2c->msg_idx != i2c->msg_num - 1) +@@ -419,6 +388,37 @@ static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c) + complete(&i2c->complete); + } + ++static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) ++{ ++ unsigned long time_left; ++ struct i2c_msg *msg; ++ ++ for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { ++ msg = &i2c->msgs[i2c->msg_idx]; ++ i2c->msg_buf = msg->buf; ++ i2c->unprocessed = msg->len; ++ i2c->status = 0; ++ ++ reinit_completion(&i2c->complete); ++ ++ spacemit_i2c_start(i2c); ++ ++ time_left = wait_for_completion_timeout(&i2c->complete, ++ i2c->adapt.timeout); ++ if (!time_left) { ++ dev_err(i2c->dev, "msg completion timeout\n"); ++ spacemit_i2c_conditionally_reset_bus(i2c); ++ spacemit_i2c_reset(i2c); ++ return -ETIMEDOUT; ++ } ++ ++ if (i2c->status & SPACEMIT_SR_ERR) ++ return spacemit_i2c_handle_err(i2c); ++ } ++ ++ return 0; ++} ++ + static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) + { + struct spacemit_i2c_dev *i2c = devid; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0207-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch b/SPECS/linux-lts/0207-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch deleted file mode 100644 index e9c9006b5c..0000000000 --- a/SPECS/linux-lts/0207-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch +++ /dev/null @@ -1,71 +0,0 @@ -From efdb5c77db11f97a43075c7a399a52fb4beeadf1 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 29 Jan 2026 10:39:21 +0800 -Subject: [PATCH 207/467] UPSTREAM: riscv: dts: thead: lichee-pi-4a: enable - HDMI - -Lichee Pi 4A board features a HDMI Type-A connector connected to the -HDMI TX controller of TH1520 SoC. - -Add a device tree node describing the connector, connect it to the HDMI -controller, and enable everything on this display pipeline. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Tested-by: Han Gao -Tested-by: Michal Wilczynski -Reviewed-by: Luca Ceresoli -Reviewed-by: Drew Fustini -Signed-off-by: Drew Fustini -(cherry picked from commit 9c99a784d9117a192ebf779d4f72ebec435ada97) -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-lichee-pi-4a.dts | 25 +++++++++++++++++++ - 1 file changed, 25 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -index c58c2085ca92..7cb7d28683bc 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -@@ -29,6 +29,17 @@ chosen { - stdout-path = "serial0:115200n8"; - }; - -+ hdmi-connector { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - thermal-zones { - cpu-thermal { - polling-delay = <1000>; -@@ -121,6 +132,20 @@ rx-pins { - }; - }; - -+&dpu { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out_port { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch b/SPECS/linux-lts/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch new file mode 100644 index 0000000000..34101370a3 --- /dev/null +++ b/SPECS/linux-lts/0208-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch @@ -0,0 +1,487 @@ +From 4fa4815280ddada7e960eb90a9ccccd015916c00 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Sat, 7 Feb 2026 23:08:22 +0800 +Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: introduce pio for k1 + +This patch introduces I2C PIO functionality for the Spacemit K1 SoC, +enabling the use of I2C in atomic context. + +When i2c xfer_atomic is invoked, use_pio is set accordingly. + +Since an atomic context is required, all interrupts are disabled when +operating in PIO mode. Even with interrupts disabled, the bits in the +ISR (Interrupt Status Register) will still be set, so error handling can +be performed by polling the relevant status bits in the ISR. + +Signed-off-by: Troy Mitchell +Tested-by: Aurelien Jarno +Reviewed-by: Aurelien Jarno +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20260207-b4-k3-i2c-pio-v7-2-626942d94d91@linux.spacemit.com +(cherry picked from commit 5dd75dac1b35e5b24f5051d01fc85105adcc2e15) +Signed-off-by: Han Gao +--- + drivers/i2c/busses/i2c-k1.c | 300 +++++++++++++++++++++++++++--------- + 1 file changed, 228 insertions(+), 72 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index 6787a51e7391..afc6bdd68bd4 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -98,6 +98,10 @@ + + #define SPACEMIT_BUS_RESET_CLK_CNT_MAX 9 + ++#define SPACEMIT_WAIT_TIMEOUT 1000 /* ms */ ++#define SPACEMIT_POLL_TIMEOUT 1000 /* us */ ++#define SPACEMIT_POLL_INTERVAL 30 /* us */ ++ + enum spacemit_i2c_state { + SPACEMIT_STATE_IDLE, + SPACEMIT_STATE_START, +@@ -126,6 +130,7 @@ struct spacemit_i2c_dev { + + enum spacemit_i2c_state state; + bool read; ++ bool use_pio; + struct completion complete; + u32 status; + }; +@@ -172,6 +177,14 @@ static int spacemit_i2c_handle_err(struct spacemit_i2c_dev *i2c) + return i2c->status & SPACEMIT_SR_ACKNAK ? -ENXIO : -EIO; + } + ++static inline void spacemit_i2c_delay(struct spacemit_i2c_dev *i2c, unsigned int us) ++{ ++ if (i2c->use_pio) ++ udelay(us); ++ else ++ fsleep(us); ++} ++ + static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c) + { + u32 status; +@@ -183,7 +196,8 @@ static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c) + return; + + spacemit_i2c_reset(i2c); +- usleep_range(10, 20); ++ ++ spacemit_i2c_delay(i2c, 10); + + for (clk_cnt = 0; clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX; clk_cnt++) { + status = readl(i2c->base + SPACEMIT_IBMR); +@@ -212,9 +226,15 @@ static int spacemit_i2c_wait_bus_idle(struct spacemit_i2c_dev *i2c) + if (!(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB))) + return 0; + +- ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, +- val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), +- 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); ++ if (i2c->use_pio) ++ ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, ++ val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), ++ 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); ++ else ++ ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, ++ val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), ++ 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); ++ + if (ret) + spacemit_i2c_reset(i2c); + +@@ -226,7 +246,7 @@ static void spacemit_i2c_check_bus_release(struct spacemit_i2c_dev *i2c) + /* in case bus is not released after transfer completes */ + if (readl(i2c->base + SPACEMIT_ISR) & SPACEMIT_SR_EBB) { + spacemit_i2c_conditionally_reset_bus(i2c); +- usleep_range(90, 150); ++ spacemit_i2c_delay(i2c, 90); + } + } + +@@ -238,25 +258,33 @@ spacemit_i2c_clear_int_status(struct spacemit_i2c_dev *i2c, u32 mask) + + static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) + { +- u32 val; +- +- /* +- * Unmask interrupt bits for all xfer mode: +- * bus error, arbitration loss detected. +- * For transaction complete signal, we use master stop +- * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. +- */ +- val = SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; +- +- /* +- * Unmask interrupt bits for interrupt xfer mode: +- * When IDBR receives a byte, an interrupt is triggered. +- * +- * For the tx empty interrupt, it will be enabled in the +- * i2c_start function. +- * Otherwise, it will cause an erroneous empty interrupt before i2c_start. +- */ +- val |= SPACEMIT_CR_DRFIE; ++ u32 val = 0; ++ ++ if (!i2c->use_pio) { ++ /* ++ * Enable interrupt bits for all xfer mode: ++ * bus error, arbitration loss detected. ++ */ ++ val |= SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; ++ ++ /* ++ * Unmask interrupt bits for interrupt xfer mode: ++ * When IDBR receives a byte, an interrupt is triggered. ++ * ++ * For the tx empty interrupt, it will be enabled in the ++ * i2c_start(). ++ * We don't want a TX empty interrupt until we start ++ * a transfer in i2c_start(). ++ */ ++ val |= SPACEMIT_CR_DRFIE; ++ ++ /* ++ * Enable master stop interrupt bit. ++ * For transaction complete signal, we use master stop ++ * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. ++ */ ++ val |= SPACEMIT_CR_MSDIE; ++ } + + if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) + val |= SPACEMIT_CR_MODE_FAST; +@@ -268,7 +296,7 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) + val |= SPACEMIT_CR_SCLE; + + /* enable master stop detected */ +- val |= SPACEMIT_CR_MSDE | SPACEMIT_CR_MSDIE; ++ val |= SPACEMIT_CR_MSDE; + + writel(val, i2c->base + SPACEMIT_ICR); + +@@ -301,7 +329,12 @@ static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) + /* send start pulse */ + val = readl(i2c->base + SPACEMIT_ICR); + val &= ~SPACEMIT_CR_STOP; +- val |= SPACEMIT_CR_START | SPACEMIT_CR_TB | SPACEMIT_CR_DTEIE; ++ val |= SPACEMIT_CR_START | SPACEMIT_CR_TB; ++ ++ /* Enable the TX empty interrupt */ ++ if (!i2c->use_pio) ++ val |= SPACEMIT_CR_DTEIE; ++ + writel(val, i2c->base + SPACEMIT_ICR); + } + +@@ -316,8 +349,23 @@ static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c) + return !i2c->unprocessed; + } + ++static inline void spacemit_i2c_complete(struct spacemit_i2c_dev *i2c) ++{ ++ /* SPACEMIT_STATE_IDLE avoids triggering the next byte */ ++ i2c->state = SPACEMIT_STATE_IDLE; ++ ++ if (i2c->use_pio) ++ return; ++ ++ complete(&i2c->complete); ++} ++ + static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c) + { ++ /* If there's no space in the IDBR, we're done */ ++ if (!(i2c->status & SPACEMIT_SR_ITE)) ++ return; ++ + /* if transfer completes, SPACEMIT_ISR will handle it */ + if (i2c->status & SPACEMIT_SR_MSD) + return; +@@ -328,16 +376,19 @@ static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c) + return; + } + +- /* SPACEMIT_STATE_IDLE avoids trigger next byte */ +- i2c->state = SPACEMIT_STATE_IDLE; +- complete(&i2c->complete); ++ spacemit_i2c_complete(i2c); + } + + static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c) + { ++ /* If there's nothing in the IDBR, we're done */ ++ if (!(i2c->status & SPACEMIT_SR_IRF)) ++ return; ++ + if (i2c->unprocessed) { + *i2c->msg_buf++ = readl(i2c->base + SPACEMIT_IDBR); + i2c->unprocessed--; ++ return; + } + + /* if transfer completes, SPACEMIT_ISR will handle it */ +@@ -348,9 +399,7 @@ static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c) + if (i2c->unprocessed) + return; + +- /* SPACEMIT_STATE_IDLE avoids trigger next byte */ +- i2c->state = SPACEMIT_STATE_IDLE; +- complete(&i2c->complete); ++ spacemit_i2c_complete(i2c); + } + + static void spacemit_i2c_handle_start(struct spacemit_i2c_dev *i2c) +@@ -384,8 +433,129 @@ static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c) + + spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); + +- i2c->state = SPACEMIT_STATE_IDLE; +- complete(&i2c->complete); ++ spacemit_i2c_complete(i2c); ++} ++ ++static void spacemit_i2c_handle_state(struct spacemit_i2c_dev *i2c) ++{ ++ u32 val; ++ ++ if (i2c->status & SPACEMIT_SR_ERR) ++ goto err_out; ++ ++ switch (i2c->state) { ++ case SPACEMIT_STATE_START: ++ spacemit_i2c_handle_start(i2c); ++ break; ++ case SPACEMIT_STATE_READ: ++ spacemit_i2c_handle_read(i2c); ++ break; ++ case SPACEMIT_STATE_WRITE: ++ spacemit_i2c_handle_write(i2c); ++ break; ++ default: ++ break; ++ } ++ ++ if (i2c->state != SPACEMIT_STATE_IDLE) { ++ val = readl(i2c->base + SPACEMIT_ICR); ++ val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | ++ SPACEMIT_CR_STOP | SPACEMIT_CR_START); ++ val |= SPACEMIT_CR_TB; ++ if (!i2c->use_pio) ++ val |= SPACEMIT_CR_ALDIE; ++ ++ if (spacemit_i2c_is_last_msg(i2c)) { ++ /* trigger next byte with stop */ ++ val |= SPACEMIT_CR_STOP; ++ ++ if (i2c->read) ++ val |= SPACEMIT_CR_ACKNAK; ++ } ++ writel(val, i2c->base + SPACEMIT_ICR); ++ } ++ ++err_out: ++ spacemit_i2c_err_check(i2c); ++} ++ ++/* ++ * In PIO mode, this function is used as a replacement for ++ * wait_for_completion_timeout(), whose return value indicates ++ * the remaining time. ++ * ++ * We do not have a meaningful remaining-time value here, so ++ * return a non-zero value on success to indicate "not timed out". ++ * Returning 1 ensures callers treating the return value as ++ * time_left will not incorrectly report a timeout. ++ */ ++static int spacemit_i2c_wait_pio_xfer(struct spacemit_i2c_dev *i2c) ++{ ++ u32 mask, msec = jiffies_to_msecs(i2c->adapt.timeout); ++ ktime_t timeout = ktime_add_ms(ktime_get(), msec); ++ int ret; ++ ++ mask = SPACEMIT_SR_IRF | SPACEMIT_SR_ITE; ++ ++ do { ++ i2c->status = readl(i2c->base + SPACEMIT_ISR); ++ ++ spacemit_i2c_clear_int_status(i2c, i2c->status); ++ ++ if (i2c->status & mask) ++ spacemit_i2c_handle_state(i2c); ++ else ++ udelay(SPACEMIT_POLL_INTERVAL); ++ } while (i2c->unprocessed && ktime_compare(ktime_get(), timeout) < 0); ++ ++ if (i2c->unprocessed) ++ return 0; ++ ++ if (i2c->read) ++ return 1; ++ ++ /* ++ * If this is the last byte to write of the current message, ++ * we have to wait here. Otherwise, control will proceed directly ++ * to start(), which would overwrite the current data. ++ */ ++ ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, ++ i2c->status, i2c->status & SPACEMIT_SR_ITE, ++ SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT); ++ if (ret) ++ return 0; ++ ++ /* ++ * For writes: in interrupt mode, an ITE (write-empty) interrupt is triggered ++ * after the last byte, and the MSD-related handling takes place there. ++ * In PIO mode, however, we need to explicitly call err_check() to emulate this ++ * step, otherwise the next transfer will fail. ++ */ ++ if (i2c->msg_idx == i2c->msg_num - 1) { ++ mask = SPACEMIT_SR_MSD | SPACEMIT_SR_ERR; ++ /* ++ * In some cases, MSD may not arrive immediately; ++ * wait here to handle that. ++ */ ++ ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, ++ i2c->status, i2c->status & mask, ++ SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT); ++ if (ret) ++ return 0; ++ ++ spacemit_i2c_err_check(i2c); ++ } ++ ++ return 1; ++} ++ ++static int spacemit_i2c_wait_xfer_complete(struct spacemit_i2c_dev *i2c) ++{ ++ if (i2c->use_pio) ++ return spacemit_i2c_wait_pio_xfer(i2c); ++ ++ return wait_for_completion_timeout(&i2c->complete, ++ i2c->adapt.timeout); + } + + static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) +@@ -403,8 +573,8 @@ static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) + + spacemit_i2c_start(i2c); + +- time_left = wait_for_completion_timeout(&i2c->complete, +- i2c->adapt.timeout); ++ time_left = spacemit_i2c_wait_xfer_complete(i2c); ++ + if (!time_left) { + dev_err(i2c->dev, "msg completion timeout\n"); + spacemit_i2c_conditionally_reset_bus(i2c); +@@ -422,7 +592,7 @@ static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) + static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) + { + struct spacemit_i2c_dev *i2c = devid; +- u32 status, val; ++ u32 status; + + status = readl(i2c->base + SPACEMIT_ISR); + if (!status) +@@ -432,41 +602,8 @@ static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) + + spacemit_i2c_clear_int_status(i2c, status); + +- if (i2c->status & SPACEMIT_SR_ERR) +- goto err_out; +- +- val = readl(i2c->base + SPACEMIT_ICR); +- val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | SPACEMIT_CR_STOP | SPACEMIT_CR_START); ++ spacemit_i2c_handle_state(i2c); + +- switch (i2c->state) { +- case SPACEMIT_STATE_START: +- spacemit_i2c_handle_start(i2c); +- break; +- case SPACEMIT_STATE_READ: +- spacemit_i2c_handle_read(i2c); +- break; +- case SPACEMIT_STATE_WRITE: +- spacemit_i2c_handle_write(i2c); +- break; +- default: +- break; +- } +- +- if (i2c->state != SPACEMIT_STATE_IDLE) { +- val |= SPACEMIT_CR_TB | SPACEMIT_CR_ALDIE; +- +- if (spacemit_i2c_is_last_msg(i2c)) { +- /* trigger next byte with stop */ +- val |= SPACEMIT_CR_STOP; +- +- if (i2c->read) +- val |= SPACEMIT_CR_ACKNAK; +- } +- writel(val, i2c->base + SPACEMIT_ICR); +- } +- +-err_out: +- spacemit_i2c_err_check(i2c); + return IRQ_HANDLED; + } + +@@ -475,6 +612,11 @@ static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c) + unsigned long timeout; + int idx = 0, cnt = 0; + ++ if (i2c->use_pio) { ++ i2c->adapt.timeout = msecs_to_jiffies(SPACEMIT_WAIT_TIMEOUT); ++ return; ++ } ++ + for (; idx < i2c->msg_num; idx++) + cnt += (i2c->msgs + idx)->len + 1; + +@@ -487,11 +629,14 @@ static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c) + i2c->adapt.timeout = usecs_to_jiffies(timeout + USEC_PER_SEC / 10) / i2c->msg_num; + } + +-static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) ++static inline int ++spacemit_i2c_xfer_common(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num, bool use_pio) + { + struct spacemit_i2c_dev *i2c = i2c_get_adapdata(adapt); + int ret; + ++ i2c->use_pio = use_pio; ++ + i2c->msgs = msgs; + i2c->msg_num = num; + +@@ -519,6 +664,16 @@ static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, in + return ret < 0 ? ret : num; + } + ++static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) ++{ ++ return spacemit_i2c_xfer_common(adapt, msgs, num, false); ++} ++ ++static int spacemit_i2c_pio_xfer_atomic(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) ++{ ++ return spacemit_i2c_xfer_common(adapt, msgs, num, true); ++} ++ + static u32 spacemit_i2c_func(struct i2c_adapter *adap) + { + return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); +@@ -526,6 +681,7 @@ static u32 spacemit_i2c_func(struct i2c_adapter *adap) + + static const struct i2c_algorithm spacemit_i2c_algo = { + .xfer = spacemit_i2c_xfer, ++ .xfer_atomic = spacemit_i2c_pio_xfer_atomic, + .functionality = spacemit_i2c_func, + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0208-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch b/SPECS/linux-lts/0208-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch deleted file mode 100644 index 4ccee80d92..0000000000 --- a/SPECS/linux-lts/0208-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 9e80c22940c9b510b2ee11be7109bdff5e262886 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Tue, 10 Mar 2026 00:24:57 +0800 -Subject: [PATCH 208/467] UPSTREAM: riscv: dts: thead: th1520: add coefficients - to the PVT node - -The manual of TH1520 contains a set of coefficients a little different -to the driver default ones. - -Add them to the device tree node of PVT. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Icenowy Zheng -Reviewed-by: Drew Fustini -Signed-off-by: Drew Fustini -(cherry picked from commit a7aa874b69460896349985833059a764e688f1d0) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index aa6c9afa1a20..c65b71d9a1b8 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -782,6 +782,10 @@ pvt: pvt@fffff4e000 { - reg-names = "common", "ts", "pd", "vm"; - clocks = <&aonsys_clk>; - #thermal-sensor-cells = <1>; -+ moortec,ts-coeff-g = <42740>; -+ moortec,ts-coeff-h = <220500>; -+ moortec,ts-coeff-j = <(-160)>; -+ moortec,ts-coeff-cal5 = <4094>; - }; - - gpio@fffff52000 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch b/SPECS/linux-lts/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch new file mode 100644 index 0000000000..d01da0caa4 --- /dev/null +++ b/SPECS/linux-lts/0209-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch @@ -0,0 +1,86 @@ +From 55a3d0c1bf77d828f3581b3c07e12d8a25775e1c Mon Sep 17 00:00:00 2001 +From: Junhui Liu +Date: Thu, 12 Mar 2026 16:42:42 +0800 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: return -ENOTSUPP for + unsupported pin configurations + +Return -ENOTSUPP instead of -EINVAL when encountering unsupported pin +configuration parameters. This is more logical and allows the GPIO +subsystem to gracefully handle unsupported parameters via functions like +gpio_set_config_with_argument_optional(), which specifically ignores +-ENOTSUPP but treats others as failure. + +Signed-off-by: Junhui Liu +Reviewed-by: Anand Moon +Reviewed-by: Bartosz Golaszewski +Reviewed-by: Yixun Lan +Signed-off-by: Linus Walleij +(cherry picked from commit c3b0c06b73974d75c640a4ebc8678f8538654e5a) +Signed-off-by: Han Gao +--- + drivers/pinctrl/spacemit/pinctrl-k1.c | 21 ++++++++++++--------- + 1 file changed, 12 insertions(+), 9 deletions(-) + +diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c +index 71390402aaa6..f3c754f78074 100644 +--- a/drivers/pinctrl/spacemit/pinctrl-k1.c ++++ b/drivers/pinctrl/spacemit/pinctrl-k1.c +@@ -674,7 +674,7 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, + arg = 0; + break; + default: +- return -EINVAL; ++ return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); +@@ -740,7 +740,7 @@ static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, + } + break; + default: +- return -EINVAL; ++ return -ENOTSUPP; + } + } + +@@ -814,10 +814,12 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, + struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + u32 value; ++ int ret; + +- if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, +- configs, num_configs, &value)) +- return -EINVAL; ++ ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, ++ configs, num_configs, &value); ++ if (ret) ++ return ret; + + return spacemit_pin_set_config(pctrl, pin, value); + } +@@ -831,16 +833,17 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, + const struct spacemit_pin *spin; + const struct group_desc *group; + u32 value; +- int i; ++ int i, ret; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + spin = spacemit_get_pin(pctrl, group->grp.pins[0]); +- if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, +- configs, num_configs, &value)) +- return -EINVAL; ++ ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, ++ configs, num_configs, &value); ++ if (ret) ++ return ret; + + for (i = 0; i < group->grp.npins; i++) + spacemit_pin_set_config(pctrl, group->grp.pins[i], value); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0209-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch b/SPECS/linux-lts/0209-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch deleted file mode 100644 index 58b7193f04..0000000000 --- a/SPECS/linux-lts/0209-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 2c28be0f3ea2c24030f397d840f378703b680aed Mon Sep 17 00:00:00 2001 -From: Robert Mazur -Date: Wed, 25 Mar 2026 09:18:59 +0100 -Subject: [PATCH 209/467] UPSTREAM: riscv: dts: thead: beaglev-ahead: enable - HDMI output - -The BeagleV Ahead board includes a micro HDMI connector (Type-D) -wired to the TH1520 SoC's HDMI transmitter. - -Enable the display pipeline by adding the HDMI connector node, -connecting it to the HDMI controller, and activating the DPU -and HDMI nodes. - -Signed-off-by: Robert Mazur -Signed-off-by: Drew Fustini -(cherry picked from commit 74ec3d52c0035b662ec295bef2bbffad68446391) -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-beaglev-ahead.dts | 25 +++++++++++++++++++ - 1 file changed, 25 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -index 21c33f165ba9..91f3f9b987bc 100644 ---- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -@@ -75,6 +75,17 @@ led-5 { - label = "led5"; - }; - }; -+ -+ hdmi-connector { -+ compatible = "hdmi-connector"; -+ type = "d"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; - }; - - &osc { -@@ -236,6 +247,20 @@ &sdio0 { - status = "okay"; - }; - -+&dpu { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out_port { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch b/SPECS/linux-lts/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch new file mode 100644 index 0000000000..5b07efea54 --- /dev/null +++ b/SPECS/linux-lts/0210-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch @@ -0,0 +1,37 @@ +From 698e2cf6a0e40c6a445aeefa403bb4ac1b28919a Mon Sep 17 00:00:00 2001 +From: Junhui Liu +Date: Thu, 12 Mar 2026 16:42:43 +0800 +Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit-k1: Add set_config callback + support + +Assign gpiochip_generic_config() to the set_config() callback to support +pin configuration through the GPIO subsystem. This allows users to +configure GPIO pin attributes like pull-up/down when specifying a GPIO +line in the Device Tree. + +Signed-off-by: Junhui Liu +Reviewed-by: Anand Moon +Acked-by: Bartosz Golaszewski +Reviewed-by: Yixun Lan +Signed-off-by: Linus Walleij +(cherry picked from commit 47a9050e678c7929ada33c3f1f28ac4403423181) +Signed-off-by: Han Gao +--- + drivers/gpio/gpio-spacemit-k1.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c +index dbd2e81094b9..5fe813b7f9bb 100644 +--- a/drivers/gpio/gpio-spacemit-k1.c ++++ b/drivers/gpio/gpio-spacemit-k1.c +@@ -228,6 +228,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, + gc->label = dev_name(dev); + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; ++ gc->set_config = gpiochip_generic_config; + gc->ngpio = SPACEMIT_NR_GPIOS_PER_BANK; + gc->base = -1; + gc->of_gpio_n_cells = 3; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0210-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch b/SPECS/linux-lts/0210-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch deleted file mode 100644 index b96de6f772..0000000000 --- a/SPECS/linux-lts/0210-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 3ceed31e1551882d64e7fd0770c15f8c1a4c15e9 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Sat, 7 Feb 2026 23:08:21 +0800 -Subject: [PATCH 210/467] UPSTREAM: i2c: spacemit: move i2c_xfer_msg() - -The upcoming PIO support requires a wait_pio_xfer() helper, which is -invoked from xfer_msg(). - -Since wait_pio_xfer() depends on err_check(), move the definition of -xfer_msg() after err_check() to avoid a forward declaration of -err_check(). - -Reviewed-by: Aurelien Jarno -Reviewed-by: Alex Elder -Signed-off-by: Troy Mitchell -Tested-by: Aurelien Jarno -Signed-off-by: Andi Shyti -Link: https://lore.kernel.org/r/20260207-b4-k3-i2c-pio-v7-1-626942d94d91@linux.spacemit.com -(cherry picked from commit 5b74da8e6cf7e2b5aed0836c733238c0fd7235af) -Signed-off-by: Han Gao ---- - drivers/i2c/busses/i2c-k1.c | 62 ++++++++++++++++++------------------- - 1 file changed, 31 insertions(+), 31 deletions(-) - -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index d0948a16de3e..6787a51e7391 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -305,37 +305,6 @@ static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) - writel(val, i2c->base + SPACEMIT_ICR); - } - --static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) --{ -- unsigned long time_left; -- struct i2c_msg *msg; -- -- for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { -- msg = &i2c->msgs[i2c->msg_idx]; -- i2c->msg_buf = msg->buf; -- i2c->unprocessed = msg->len; -- i2c->status = 0; -- -- reinit_completion(&i2c->complete); -- -- spacemit_i2c_start(i2c); -- -- time_left = wait_for_completion_timeout(&i2c->complete, -- i2c->adapt.timeout); -- if (!time_left) { -- dev_err(i2c->dev, "msg completion timeout\n"); -- spacemit_i2c_conditionally_reset_bus(i2c); -- spacemit_i2c_reset(i2c); -- return -ETIMEDOUT; -- } -- -- if (i2c->status & SPACEMIT_SR_ERR) -- return spacemit_i2c_handle_err(i2c); -- } -- -- return 0; --} -- - static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c) - { - if (i2c->msg_idx != i2c->msg_num - 1) -@@ -419,6 +388,37 @@ static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c) - complete(&i2c->complete); - } - -+static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) -+{ -+ unsigned long time_left; -+ struct i2c_msg *msg; -+ -+ for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) { -+ msg = &i2c->msgs[i2c->msg_idx]; -+ i2c->msg_buf = msg->buf; -+ i2c->unprocessed = msg->len; -+ i2c->status = 0; -+ -+ reinit_completion(&i2c->complete); -+ -+ spacemit_i2c_start(i2c); -+ -+ time_left = wait_for_completion_timeout(&i2c->complete, -+ i2c->adapt.timeout); -+ if (!time_left) { -+ dev_err(i2c->dev, "msg completion timeout\n"); -+ spacemit_i2c_conditionally_reset_bus(i2c); -+ spacemit_i2c_reset(i2c); -+ return -ETIMEDOUT; -+ } -+ -+ if (i2c->status & SPACEMIT_SR_ERR) -+ return spacemit_i2c_handle_err(i2c); -+ } -+ -+ return 0; -+} -+ - static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) - { - struct spacemit_i2c_dev *i2c = devid; --- -2.53.0 - diff --git a/SPECS/linux-lts/0211-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch b/SPECS/linux-lts/0211-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch deleted file mode 100644 index 46854f2eb4..0000000000 --- a/SPECS/linux-lts/0211-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch +++ /dev/null @@ -1,487 +0,0 @@ -From 4c5b92d265c0ff7e581b5979bc668b3a0358edba Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Sat, 7 Feb 2026 23:08:22 +0800 -Subject: [PATCH 211/467] UPSTREAM: i2c: spacemit: introduce pio for k1 - -This patch introduces I2C PIO functionality for the Spacemit K1 SoC, -enabling the use of I2C in atomic context. - -When i2c xfer_atomic is invoked, use_pio is set accordingly. - -Since an atomic context is required, all interrupts are disabled when -operating in PIO mode. Even with interrupts disabled, the bits in the -ISR (Interrupt Status Register) will still be set, so error handling can -be performed by polling the relevant status bits in the ISR. - -Signed-off-by: Troy Mitchell -Tested-by: Aurelien Jarno -Reviewed-by: Aurelien Jarno -Signed-off-by: Andi Shyti -Link: https://lore.kernel.org/r/20260207-b4-k3-i2c-pio-v7-2-626942d94d91@linux.spacemit.com -(cherry picked from commit 5dd75dac1b35e5b24f5051d01fc85105adcc2e15) -Signed-off-by: Han Gao ---- - drivers/i2c/busses/i2c-k1.c | 300 +++++++++++++++++++++++++++--------- - 1 file changed, 228 insertions(+), 72 deletions(-) - -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index 6787a51e7391..afc6bdd68bd4 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -98,6 +98,10 @@ - - #define SPACEMIT_BUS_RESET_CLK_CNT_MAX 9 - -+#define SPACEMIT_WAIT_TIMEOUT 1000 /* ms */ -+#define SPACEMIT_POLL_TIMEOUT 1000 /* us */ -+#define SPACEMIT_POLL_INTERVAL 30 /* us */ -+ - enum spacemit_i2c_state { - SPACEMIT_STATE_IDLE, - SPACEMIT_STATE_START, -@@ -126,6 +130,7 @@ struct spacemit_i2c_dev { - - enum spacemit_i2c_state state; - bool read; -+ bool use_pio; - struct completion complete; - u32 status; - }; -@@ -172,6 +177,14 @@ static int spacemit_i2c_handle_err(struct spacemit_i2c_dev *i2c) - return i2c->status & SPACEMIT_SR_ACKNAK ? -ENXIO : -EIO; - } - -+static inline void spacemit_i2c_delay(struct spacemit_i2c_dev *i2c, unsigned int us) -+{ -+ if (i2c->use_pio) -+ udelay(us); -+ else -+ fsleep(us); -+} -+ - static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c) - { - u32 status; -@@ -183,7 +196,8 @@ static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c) - return; - - spacemit_i2c_reset(i2c); -- usleep_range(10, 20); -+ -+ spacemit_i2c_delay(i2c, 10); - - for (clk_cnt = 0; clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX; clk_cnt++) { - status = readl(i2c->base + SPACEMIT_IBMR); -@@ -212,9 +226,15 @@ static int spacemit_i2c_wait_bus_idle(struct spacemit_i2c_dev *i2c) - if (!(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB))) - return 0; - -- ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, -- val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), -- 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); -+ if (i2c->use_pio) -+ ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, -+ val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), -+ 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); -+ else -+ ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR, -+ val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)), -+ 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT); -+ - if (ret) - spacemit_i2c_reset(i2c); - -@@ -226,7 +246,7 @@ static void spacemit_i2c_check_bus_release(struct spacemit_i2c_dev *i2c) - /* in case bus is not released after transfer completes */ - if (readl(i2c->base + SPACEMIT_ISR) & SPACEMIT_SR_EBB) { - spacemit_i2c_conditionally_reset_bus(i2c); -- usleep_range(90, 150); -+ spacemit_i2c_delay(i2c, 90); - } - } - -@@ -238,25 +258,33 @@ spacemit_i2c_clear_int_status(struct spacemit_i2c_dev *i2c, u32 mask) - - static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) - { -- u32 val; -- -- /* -- * Unmask interrupt bits for all xfer mode: -- * bus error, arbitration loss detected. -- * For transaction complete signal, we use master stop -- * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. -- */ -- val = SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; -- -- /* -- * Unmask interrupt bits for interrupt xfer mode: -- * When IDBR receives a byte, an interrupt is triggered. -- * -- * For the tx empty interrupt, it will be enabled in the -- * i2c_start function. -- * Otherwise, it will cause an erroneous empty interrupt before i2c_start. -- */ -- val |= SPACEMIT_CR_DRFIE; -+ u32 val = 0; -+ -+ if (!i2c->use_pio) { -+ /* -+ * Enable interrupt bits for all xfer mode: -+ * bus error, arbitration loss detected. -+ */ -+ val |= SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE; -+ -+ /* -+ * Unmask interrupt bits for interrupt xfer mode: -+ * When IDBR receives a byte, an interrupt is triggered. -+ * -+ * For the tx empty interrupt, it will be enabled in the -+ * i2c_start(). -+ * We don't want a TX empty interrupt until we start -+ * a transfer in i2c_start(). -+ */ -+ val |= SPACEMIT_CR_DRFIE; -+ -+ /* -+ * Enable master stop interrupt bit. -+ * For transaction complete signal, we use master stop -+ * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE. -+ */ -+ val |= SPACEMIT_CR_MSDIE; -+ } - - if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) - val |= SPACEMIT_CR_MODE_FAST; -@@ -268,7 +296,7 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) - val |= SPACEMIT_CR_SCLE; - - /* enable master stop detected */ -- val |= SPACEMIT_CR_MSDE | SPACEMIT_CR_MSDIE; -+ val |= SPACEMIT_CR_MSDE; - - writel(val, i2c->base + SPACEMIT_ICR); - -@@ -301,7 +329,12 @@ static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) - /* send start pulse */ - val = readl(i2c->base + SPACEMIT_ICR); - val &= ~SPACEMIT_CR_STOP; -- val |= SPACEMIT_CR_START | SPACEMIT_CR_TB | SPACEMIT_CR_DTEIE; -+ val |= SPACEMIT_CR_START | SPACEMIT_CR_TB; -+ -+ /* Enable the TX empty interrupt */ -+ if (!i2c->use_pio) -+ val |= SPACEMIT_CR_DTEIE; -+ - writel(val, i2c->base + SPACEMIT_ICR); - } - -@@ -316,8 +349,23 @@ static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c) - return !i2c->unprocessed; - } - -+static inline void spacemit_i2c_complete(struct spacemit_i2c_dev *i2c) -+{ -+ /* SPACEMIT_STATE_IDLE avoids triggering the next byte */ -+ i2c->state = SPACEMIT_STATE_IDLE; -+ -+ if (i2c->use_pio) -+ return; -+ -+ complete(&i2c->complete); -+} -+ - static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c) - { -+ /* If there's no space in the IDBR, we're done */ -+ if (!(i2c->status & SPACEMIT_SR_ITE)) -+ return; -+ - /* if transfer completes, SPACEMIT_ISR will handle it */ - if (i2c->status & SPACEMIT_SR_MSD) - return; -@@ -328,16 +376,19 @@ static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c) - return; - } - -- /* SPACEMIT_STATE_IDLE avoids trigger next byte */ -- i2c->state = SPACEMIT_STATE_IDLE; -- complete(&i2c->complete); -+ spacemit_i2c_complete(i2c); - } - - static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c) - { -+ /* If there's nothing in the IDBR, we're done */ -+ if (!(i2c->status & SPACEMIT_SR_IRF)) -+ return; -+ - if (i2c->unprocessed) { - *i2c->msg_buf++ = readl(i2c->base + SPACEMIT_IDBR); - i2c->unprocessed--; -+ return; - } - - /* if transfer completes, SPACEMIT_ISR will handle it */ -@@ -348,9 +399,7 @@ static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c) - if (i2c->unprocessed) - return; - -- /* SPACEMIT_STATE_IDLE avoids trigger next byte */ -- i2c->state = SPACEMIT_STATE_IDLE; -- complete(&i2c->complete); -+ spacemit_i2c_complete(i2c); - } - - static void spacemit_i2c_handle_start(struct spacemit_i2c_dev *i2c) -@@ -384,8 +433,129 @@ static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c) - - spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); - -- i2c->state = SPACEMIT_STATE_IDLE; -- complete(&i2c->complete); -+ spacemit_i2c_complete(i2c); -+} -+ -+static void spacemit_i2c_handle_state(struct spacemit_i2c_dev *i2c) -+{ -+ u32 val; -+ -+ if (i2c->status & SPACEMIT_SR_ERR) -+ goto err_out; -+ -+ switch (i2c->state) { -+ case SPACEMIT_STATE_START: -+ spacemit_i2c_handle_start(i2c); -+ break; -+ case SPACEMIT_STATE_READ: -+ spacemit_i2c_handle_read(i2c); -+ break; -+ case SPACEMIT_STATE_WRITE: -+ spacemit_i2c_handle_write(i2c); -+ break; -+ default: -+ break; -+ } -+ -+ if (i2c->state != SPACEMIT_STATE_IDLE) { -+ val = readl(i2c->base + SPACEMIT_ICR); -+ val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | -+ SPACEMIT_CR_STOP | SPACEMIT_CR_START); -+ val |= SPACEMIT_CR_TB; -+ if (!i2c->use_pio) -+ val |= SPACEMIT_CR_ALDIE; -+ -+ if (spacemit_i2c_is_last_msg(i2c)) { -+ /* trigger next byte with stop */ -+ val |= SPACEMIT_CR_STOP; -+ -+ if (i2c->read) -+ val |= SPACEMIT_CR_ACKNAK; -+ } -+ writel(val, i2c->base + SPACEMIT_ICR); -+ } -+ -+err_out: -+ spacemit_i2c_err_check(i2c); -+} -+ -+/* -+ * In PIO mode, this function is used as a replacement for -+ * wait_for_completion_timeout(), whose return value indicates -+ * the remaining time. -+ * -+ * We do not have a meaningful remaining-time value here, so -+ * return a non-zero value on success to indicate "not timed out". -+ * Returning 1 ensures callers treating the return value as -+ * time_left will not incorrectly report a timeout. -+ */ -+static int spacemit_i2c_wait_pio_xfer(struct spacemit_i2c_dev *i2c) -+{ -+ u32 mask, msec = jiffies_to_msecs(i2c->adapt.timeout); -+ ktime_t timeout = ktime_add_ms(ktime_get(), msec); -+ int ret; -+ -+ mask = SPACEMIT_SR_IRF | SPACEMIT_SR_ITE; -+ -+ do { -+ i2c->status = readl(i2c->base + SPACEMIT_ISR); -+ -+ spacemit_i2c_clear_int_status(i2c, i2c->status); -+ -+ if (i2c->status & mask) -+ spacemit_i2c_handle_state(i2c); -+ else -+ udelay(SPACEMIT_POLL_INTERVAL); -+ } while (i2c->unprocessed && ktime_compare(ktime_get(), timeout) < 0); -+ -+ if (i2c->unprocessed) -+ return 0; -+ -+ if (i2c->read) -+ return 1; -+ -+ /* -+ * If this is the last byte to write of the current message, -+ * we have to wait here. Otherwise, control will proceed directly -+ * to start(), which would overwrite the current data. -+ */ -+ ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, -+ i2c->status, i2c->status & SPACEMIT_SR_ITE, -+ SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT); -+ if (ret) -+ return 0; -+ -+ /* -+ * For writes: in interrupt mode, an ITE (write-empty) interrupt is triggered -+ * after the last byte, and the MSD-related handling takes place there. -+ * In PIO mode, however, we need to explicitly call err_check() to emulate this -+ * step, otherwise the next transfer will fail. -+ */ -+ if (i2c->msg_idx == i2c->msg_num - 1) { -+ mask = SPACEMIT_SR_MSD | SPACEMIT_SR_ERR; -+ /* -+ * In some cases, MSD may not arrive immediately; -+ * wait here to handle that. -+ */ -+ ret = readl_poll_timeout_atomic(i2c->base + SPACEMIT_ISR, -+ i2c->status, i2c->status & mask, -+ SPACEMIT_POLL_INTERVAL, SPACEMIT_POLL_TIMEOUT); -+ if (ret) -+ return 0; -+ -+ spacemit_i2c_err_check(i2c); -+ } -+ -+ return 1; -+} -+ -+static int spacemit_i2c_wait_xfer_complete(struct spacemit_i2c_dev *i2c) -+{ -+ if (i2c->use_pio) -+ return spacemit_i2c_wait_pio_xfer(i2c); -+ -+ return wait_for_completion_timeout(&i2c->complete, -+ i2c->adapt.timeout); - } - - static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) -@@ -403,8 +573,8 @@ static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) - - spacemit_i2c_start(i2c); - -- time_left = wait_for_completion_timeout(&i2c->complete, -- i2c->adapt.timeout); -+ time_left = spacemit_i2c_wait_xfer_complete(i2c); -+ - if (!time_left) { - dev_err(i2c->dev, "msg completion timeout\n"); - spacemit_i2c_conditionally_reset_bus(i2c); -@@ -422,7 +592,7 @@ static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c) - static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) - { - struct spacemit_i2c_dev *i2c = devid; -- u32 status, val; -+ u32 status; - - status = readl(i2c->base + SPACEMIT_ISR); - if (!status) -@@ -432,41 +602,8 @@ static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid) - - spacemit_i2c_clear_int_status(i2c, status); - -- if (i2c->status & SPACEMIT_SR_ERR) -- goto err_out; -- -- val = readl(i2c->base + SPACEMIT_ICR); -- val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | SPACEMIT_CR_STOP | SPACEMIT_CR_START); -+ spacemit_i2c_handle_state(i2c); - -- switch (i2c->state) { -- case SPACEMIT_STATE_START: -- spacemit_i2c_handle_start(i2c); -- break; -- case SPACEMIT_STATE_READ: -- spacemit_i2c_handle_read(i2c); -- break; -- case SPACEMIT_STATE_WRITE: -- spacemit_i2c_handle_write(i2c); -- break; -- default: -- break; -- } -- -- if (i2c->state != SPACEMIT_STATE_IDLE) { -- val |= SPACEMIT_CR_TB | SPACEMIT_CR_ALDIE; -- -- if (spacemit_i2c_is_last_msg(i2c)) { -- /* trigger next byte with stop */ -- val |= SPACEMIT_CR_STOP; -- -- if (i2c->read) -- val |= SPACEMIT_CR_ACKNAK; -- } -- writel(val, i2c->base + SPACEMIT_ICR); -- } -- --err_out: -- spacemit_i2c_err_check(i2c); - return IRQ_HANDLED; - } - -@@ -475,6 +612,11 @@ static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c) - unsigned long timeout; - int idx = 0, cnt = 0; - -+ if (i2c->use_pio) { -+ i2c->adapt.timeout = msecs_to_jiffies(SPACEMIT_WAIT_TIMEOUT); -+ return; -+ } -+ - for (; idx < i2c->msg_num; idx++) - cnt += (i2c->msgs + idx)->len + 1; - -@@ -487,11 +629,14 @@ static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c) - i2c->adapt.timeout = usecs_to_jiffies(timeout + USEC_PER_SEC / 10) / i2c->msg_num; - } - --static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) -+static inline int -+spacemit_i2c_xfer_common(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num, bool use_pio) - { - struct spacemit_i2c_dev *i2c = i2c_get_adapdata(adapt); - int ret; - -+ i2c->use_pio = use_pio; -+ - i2c->msgs = msgs; - i2c->msg_num = num; - -@@ -519,6 +664,16 @@ static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, in - return ret < 0 ? ret : num; - } - -+static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) -+{ -+ return spacemit_i2c_xfer_common(adapt, msgs, num, false); -+} -+ -+static int spacemit_i2c_pio_xfer_atomic(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num) -+{ -+ return spacemit_i2c_xfer_common(adapt, msgs, num, true); -+} -+ - static u32 spacemit_i2c_func(struct i2c_adapter *adap) - { - return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); -@@ -526,6 +681,7 @@ static u32 spacemit_i2c_func(struct i2c_adapter *adap) - - static const struct i2c_algorithm spacemit_i2c_algo = { - .xfer = spacemit_i2c_xfer, -+ .xfer_atomic = spacemit_i2c_pio_xfer_atomic, - .functionality = spacemit_i2c_func, - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch b/SPECS/linux-lts/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch new file mode 100644 index 0000000000..e3ff5c7bb8 --- /dev/null +++ b/SPECS/linux-lts/0211-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch @@ -0,0 +1,45 @@ +From 8572451bc96b2e6e3f43ce554e3806a5b1c7778c Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 26 Feb 2026 08:17:55 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: pcie: fix missing power + regulator + +The PCIe port require 3.3v power regulator for device to work properly, So +explicitly add it to fix the DT warning: + +arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dtb: pcie@ca400000 (spacemit,k1-pcie): pcie@0: 'vpcie3v3-supply' is a required property + from schema $id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml + +Fixes: 0be016a4b5d1 ("riscv: dts: spacemit: PCIe and PHY-related updates") +Reported-by: Conor Dooley +Link: https://lore.kernel.org/r/20260226-k1-pcie-fix-pwr-v1-1-94b493cd27e5@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 8a9071299dec817a544c0fb48f7302396fafdc4b) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 5971605754b3..51f6c6a774b0 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -305,6 +305,7 @@ &pcie1_phy { + + &pcie1_port { + phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc_3v3>; + }; + + &pcie1 { +@@ -320,6 +321,7 @@ &pcie2_phy { + + &pcie2_port { + phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&pcie_vcc_3v3>; + }; + + &pcie2 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0212-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch b/SPECS/linux-lts/0212-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch deleted file mode 100644 index 829d6bbcd0..0000000000 --- a/SPECS/linux-lts/0212-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch +++ /dev/null @@ -1,86 +0,0 @@ -From b353a7aa6259753c7025aedf18b101189b01e902 Mon Sep 17 00:00:00 2001 -From: Junhui Liu -Date: Thu, 12 Mar 2026 16:42:42 +0800 -Subject: [PATCH 212/467] UPSTREAM: pinctrl: spacemit: return -ENOTSUPP for - unsupported pin configurations - -Return -ENOTSUPP instead of -EINVAL when encountering unsupported pin -configuration parameters. This is more logical and allows the GPIO -subsystem to gracefully handle unsupported parameters via functions like -gpio_set_config_with_argument_optional(), which specifically ignores --ENOTSUPP but treats others as failure. - -Signed-off-by: Junhui Liu -Reviewed-by: Anand Moon -Reviewed-by: Bartosz Golaszewski -Reviewed-by: Yixun Lan -Signed-off-by: Linus Walleij -(cherry picked from commit c3b0c06b73974d75c640a4ebc8678f8538654e5a) -Signed-off-by: Han Gao ---- - drivers/pinctrl/spacemit/pinctrl-k1.c | 21 ++++++++++++--------- - 1 file changed, 12 insertions(+), 9 deletions(-) - -diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c -index 71390402aaa6..f3c754f78074 100644 ---- a/drivers/pinctrl/spacemit/pinctrl-k1.c -+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c -@@ -674,7 +674,7 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, - arg = 0; - break; - default: -- return -EINVAL; -+ return -ENOTSUPP; - } - - *config = pinconf_to_config_packed(param, arg); -@@ -740,7 +740,7 @@ static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl, - } - break; - default: -- return -EINVAL; -+ return -ENOTSUPP; - } - } - -@@ -814,10 +814,12 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, - struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); - u32 value; -+ int ret; - -- if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, -- configs, num_configs, &value)) -- return -EINVAL; -+ ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, -+ configs, num_configs, &value); -+ if (ret) -+ return ret; - - return spacemit_pin_set_config(pctrl, pin, value); - } -@@ -831,16 +833,17 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, - const struct spacemit_pin *spin; - const struct group_desc *group; - u32 value; -- int i; -+ int i, ret; - - group = pinctrl_generic_get_group(pctldev, gsel); - if (!group) - return -EINVAL; - - spin = spacemit_get_pin(pctrl, group->grp.pins[0]); -- if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, -- configs, num_configs, &value)) -- return -EINVAL; -+ ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf, -+ configs, num_configs, &value); -+ if (ret) -+ return ret; - - for (i = 0; i < group->grp.npins; i++) - spacemit_pin_set_config(pctrl, group->grp.pins[i], value); --- -2.53.0 - diff --git a/SPECS/linux-lts/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch b/SPECS/linux-lts/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch new file mode 100644 index 0000000000..c1a03ad44a --- /dev/null +++ b/SPECS/linux-lts/0212-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch @@ -0,0 +1,83 @@ +From d591170d2ed25e8716eb3db09e686e859c5c318b Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Fri, 6 Feb 2026 10:32:04 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Update PMIC supply + properties for BPI-F3 and Jupiter + +Use per-regulator supply names in pmic "spacemit,p1" node to specify +each board's power tree topology and match the updated dt-binding. + +Signed-off-by: Guodong Xu +Reviewed-by: Alex Elder +Link: https://lore.kernel.org/r/20260206-spacemit-p1-v4-3-8f695d93811e@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 108c77b34b929e6bdb7ac9613ed65c90da8bcb9f) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++-- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 12 ++++++++++-- + 2 files changed, 20 insertions(+), 4 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 51f6c6a774b0..ed88507b84e9 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -190,7 +190,15 @@ pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; +- vin-supply = <®_vcc_4v>; ++ vin1-supply = <®_vcc_4v>; ++ vin2-supply = <®_vcc_4v>; ++ vin3-supply = <®_vcc_4v>; ++ vin4-supply = <®_vcc_4v>; ++ vin5-supply = <®_vcc_4v>; ++ vin6-supply = <®_vcc_4v>; ++ aldoin-supply = <®_vcc_4v>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; + + regulators { + buck1 { +@@ -221,7 +229,7 @@ buck4 { + regulator-always-on; + }; + +- buck5 { ++ buck5: buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 800a112d5d70..e2702a781734 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -100,7 +100,15 @@ pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; +- vin-supply = <®_vcc_4v>; ++ vin1-supply = <®_vcc_4v>; ++ vin2-supply = <®_vcc_4v>; ++ vin3-supply = <®_vcc_4v>; ++ vin4-supply = <®_vcc_4v>; ++ vin5-supply = <®_vcc_4v>; ++ vin6-supply = <®_vcc_4v>; ++ aldoin-supply = <®_vcc_4v>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; + + regulators { + buck1 { +@@ -131,7 +139,7 @@ buck4 { + regulator-always-on; + }; + +- buck5 { ++ buck5: buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0213-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch b/SPECS/linux-lts/0213-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch deleted file mode 100644 index 94351bf0cb..0000000000 --- a/SPECS/linux-lts/0213-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch +++ /dev/null @@ -1,37 +0,0 @@ -From d5b0b0437eee5d56c49e36bb6f428b5171ddb716 Mon Sep 17 00:00:00 2001 -From: Junhui Liu -Date: Thu, 12 Mar 2026 16:42:43 +0800 -Subject: [PATCH 213/467] UPSTREAM: gpio: spacemit-k1: Add set_config callback - support - -Assign gpiochip_generic_config() to the set_config() callback to support -pin configuration through the GPIO subsystem. This allows users to -configure GPIO pin attributes like pull-up/down when specifying a GPIO -line in the Device Tree. - -Signed-off-by: Junhui Liu -Reviewed-by: Anand Moon -Acked-by: Bartosz Golaszewski -Reviewed-by: Yixun Lan -Signed-off-by: Linus Walleij -(cherry picked from commit 47a9050e678c7929ada33c3f1f28ac4403423181) -Signed-off-by: Han Gao ---- - drivers/gpio/gpio-spacemit-k1.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c -index dbd2e81094b9..5fe813b7f9bb 100644 ---- a/drivers/gpio/gpio-spacemit-k1.c -+++ b/drivers/gpio/gpio-spacemit-k1.c -@@ -228,6 +228,7 @@ static int spacemit_gpio_add_bank(struct spacemit_gpio *sg, - gc->label = dev_name(dev); - gc->request = gpiochip_generic_request; - gc->free = gpiochip_generic_free; -+ gc->set_config = gpiochip_generic_config; - gc->ngpio = SPACEMIT_NR_GPIOS_PER_BANK; - gc->base = -1; - gc->of_gpio_n_cells = 3; --- -2.53.0 - diff --git a/SPECS/linux-lts/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch b/SPECS/linux-lts/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch new file mode 100644 index 0000000000..2dce8101f3 --- /dev/null +++ b/SPECS/linux-lts/0213-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch @@ -0,0 +1,96 @@ +From d068a8147daedba4965fc79a896ad7dcaa91b9e4 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 26 Feb 2026 09:35:00 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: adapt regulator node + name to preferred form + +The preferred node name for fixed-regulators has changed to pattern [1]: + '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$' + +Adjust all SpacemiT DT regulator node names to fix this. + +Reviewed-by: Javier Martinez Canillas +Link: https://lore.kernel.org/r/20240426215147.3138211-1-robh@kernel.org [1] +Link: https://lore.kernel.org/r/20260226-02-k1-regulator-names-v1-1-e87695d50159@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit ec1fb4e55df47ed043ab2ccc6787e39b9d67e49b) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 10 +++++----- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++-- + 2 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index ed88507b84e9..404b69c47b91 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -33,7 +33,7 @@ led1 { + }; + }; + +- pcie_vcc_3v3: pcie-vcc3v3 { ++ pcie_vcc_3v3: regulator-pcie-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "PCIE_VCC3V3"; + regulator-min-microvolt = <3300000>; +@@ -41,7 +41,7 @@ pcie_vcc_3v3: pcie-vcc3v3 { + regulator-always-on; + }; + +- reg_dc_in: dc-in-12v { ++ reg_dc_in: regulator-dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; + regulator-min-microvolt = <12000000>; +@@ -50,7 +50,7 @@ reg_dc_in: dc-in-12v { + regulator-always-on; + }; + +- reg_vcc_4v: vcc-4v { ++ reg_vcc_4v: regulator-vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "vcc_4v"; + regulator-min-microvolt = <4000000>; +@@ -60,7 +60,7 @@ reg_vcc_4v: vcc-4v { + vin-supply = <®_dc_in>; + }; + +- usb3-vbus-5v { ++ regulator-usb3-vbus-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_VBUS"; + regulator-min-microvolt = <5000000>; +@@ -70,7 +70,7 @@ usb3-vbus-5v { + enable-active-high; + }; + +- usb3_hub_5v: usb3-hub-5v { ++ usb3_hub_5v: regulator-usb3-hub-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_HUB"; + regulator-min-microvolt = <5000000>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index e2702a781734..9959c8023ece 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -21,7 +21,7 @@ chosen { + stdout-path = "serial0"; + }; + +- reg_dc_in: dc-in-12v { ++ reg_dc_in: regulator-dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; + regulator-min-microvolt = <12000000>; +@@ -30,7 +30,7 @@ reg_dc_in: dc-in-12v { + regulator-always-on; + }; + +- reg_vcc_4v: vcc-4v { ++ reg_vcc_4v: regulator-vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "vcc_4v"; + regulator-min-microvolt = <4000000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch b/SPECS/linux-lts/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch new file mode 100644 index 0000000000..dd31af6364 --- /dev/null +++ b/SPECS/linux-lts/0214-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch @@ -0,0 +1,62 @@ +From 3c942f15e5112f8554b39f1c889cb52184bd3e90 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Mon, 9 Mar 2026 11:00:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add 'linux,pci-domain' + to PCIe nodes for K1 + +The SpacemiT K1 SoC has 3 PCIe EP controller nodes. Add the +'linux,pci-domain' property to assign a PCI domain number to +each of the controllers instead of assigning it randomly. + +This creates a stable sysfs path, allowing userspace scripts +to reliably target specific PCIe devices (such as PCIe NICs). + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260309030000.1157040-1-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit 86314111f654310a69c9775e35e263c036031675) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 529ec68e9c23..d2015201f8e5 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -1033,6 +1033,7 @@ pcie-bus { + #size-cells = <2>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, + <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; ++ + pcie0: pcie@ca000000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; +@@ -1044,6 +1045,7 @@ pcie0: pcie@ca000000 { + "atu", + "config", + "link"; ++ linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, +@@ -1087,6 +1089,7 @@ pcie1: pcie@ca400000 { + "atu", + "config", + "link"; ++ linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, +@@ -1130,6 +1133,7 @@ pcie2: pcie@ca800000 { + "atu", + "config", + "link"; ++ linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0214-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch b/SPECS/linux-lts/0214-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch deleted file mode 100644 index af101ace4b..0000000000 --- a/SPECS/linux-lts/0214-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 0b209a13a933458317f10fc48bd50c2986ab96fc Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 26 Feb 2026 08:17:55 +0000 -Subject: [PATCH 214/467] UPSTREAM: riscv: dts: spacemit: pcie: fix missing - power regulator - -The PCIe port require 3.3v power regulator for device to work properly, So -explicitly add it to fix the DT warning: - -arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dtb: pcie@ca400000 (spacemit,k1-pcie): pcie@0: 'vpcie3v3-supply' is a required property - from schema $id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml - -Fixes: 0be016a4b5d1 ("riscv: dts: spacemit: PCIe and PHY-related updates") -Reported-by: Conor Dooley -Link: https://lore.kernel.org/r/20260226-k1-pcie-fix-pwr-v1-1-94b493cd27e5@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit 8a9071299dec817a544c0fb48f7302396fafdc4b) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 5971605754b3..51f6c6a774b0 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -305,6 +305,7 @@ &pcie1_phy { - - &pcie1_port { - phys = <&pcie1_phy>; -+ vpcie3v3-supply = <&pcie_vcc_3v3>; - }; - - &pcie1 { -@@ -320,6 +321,7 @@ &pcie2_phy { - - &pcie2_port { - phys = <&pcie2_phy>; -+ vpcie3v3-supply = <&pcie_vcc_3v3>; - }; - - &pcie2 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch b/SPECS/linux-lts/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch new file mode 100644 index 0000000000..1a6351971a --- /dev/null +++ b/SPECS/linux-lts/0215-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch @@ -0,0 +1,46 @@ +From e6fddcb8065f3568285549e732cda7618b1e5065 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 4 Mar 2026 07:19:39 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: serial: 8250: spacemit: fix clock + property for K3 SoC + +The UART of SpacemiT K3 SoC has same clock property as K1 generation which +request two clock sources, fix the binding otherwise will get DT check +warnings. + +Acked-by: Greg Kroah-Hartman +Acked-by: Rob Herring (Arm) +Link: https://lore.kernel.org/r/20260304-01-uart-clock-names-v1-1-338483f04a8b@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 606a6b8bca570aa4f838ddd410345a2937bd98eb) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/serial/8250.yaml | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml +index b243afa69a1a..0d4ae9a62f4c 100644 +--- a/Documentation/devicetree/bindings/serial/8250.yaml ++++ b/Documentation/devicetree/bindings/serial/8250.yaml +@@ -63,7 +63,9 @@ allOf: + properties: + compatible: + contains: +- const: spacemit,k1-uart ++ enum: ++ - spacemit,k1-uart ++ - spacemit,k3-uart + then: + properties: + clock-names: +@@ -76,6 +78,7 @@ allOf: + contains: + enum: + - spacemit,k1-uart ++ - spacemit,k3-uart + - nxp,lpc1850-uart + then: + required: +-- +2.53.0 + diff --git a/SPECS/linux-lts/0215-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch b/SPECS/linux-lts/0215-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch deleted file mode 100644 index 812b0f1ef8..0000000000 --- a/SPECS/linux-lts/0215-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 867d1c8308a1f4fcaa14a9efca280d8e5ca431a1 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Fri, 6 Feb 2026 10:32:04 +0800 -Subject: [PATCH 215/467] UPSTREAM: riscv: dts: spacemit: Update PMIC supply - properties for BPI-F3 and Jupiter - -Use per-regulator supply names in pmic "spacemit,p1" node to specify -each board's power tree topology and match the updated dt-binding. - -Signed-off-by: Guodong Xu -Reviewed-by: Alex Elder -Link: https://lore.kernel.org/r/20260206-spacemit-p1-v4-3-8f695d93811e@riscstar.com -Signed-off-by: Yixun Lan -(cherry picked from commit 108c77b34b929e6bdb7ac9613ed65c90da8bcb9f) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++-- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 12 ++++++++++-- - 2 files changed, 20 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 51f6c6a774b0..ed88507b84e9 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -190,7 +190,15 @@ pmic@41 { - compatible = "spacemit,p1"; - reg = <0x41>; - interrupts = <64>; -- vin-supply = <®_vcc_4v>; -+ vin1-supply = <®_vcc_4v>; -+ vin2-supply = <®_vcc_4v>; -+ vin3-supply = <®_vcc_4v>; -+ vin4-supply = <®_vcc_4v>; -+ vin5-supply = <®_vcc_4v>; -+ vin6-supply = <®_vcc_4v>; -+ aldoin-supply = <®_vcc_4v>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; - - regulators { - buck1 { -@@ -221,7 +229,7 @@ buck4 { - regulator-always-on; - }; - -- buck5 { -+ buck5: buck5 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; - regulator-ramp-delay = <5000>; -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 800a112d5d70..e2702a781734 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -100,7 +100,15 @@ pmic@41 { - compatible = "spacemit,p1"; - reg = <0x41>; - interrupts = <64>; -- vin-supply = <®_vcc_4v>; -+ vin1-supply = <®_vcc_4v>; -+ vin2-supply = <®_vcc_4v>; -+ vin3-supply = <®_vcc_4v>; -+ vin4-supply = <®_vcc_4v>; -+ vin5-supply = <®_vcc_4v>; -+ vin6-supply = <®_vcc_4v>; -+ aldoin-supply = <®_vcc_4v>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; - - regulators { - buck1 { -@@ -131,7 +139,7 @@ buck4 { - regulator-always-on; - }; - -- buck5 { -+ buck5: buck5 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; - regulator-ramp-delay = <5000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0216-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch b/SPECS/linux-lts/0216-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch deleted file mode 100644 index 0baf5e0509..0000000000 --- a/SPECS/linux-lts/0216-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 8e847600364cd4fb332c1e6d69b370eab667157b Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 26 Feb 2026 09:35:00 +0000 -Subject: [PATCH 216/467] UPSTREAM: riscv: dts: spacemit: adapt regulator node - name to preferred form - -The preferred node name for fixed-regulators has changed to pattern [1]: - '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$' - -Adjust all SpacemiT DT regulator node names to fix this. - -Reviewed-by: Javier Martinez Canillas -Link: https://lore.kernel.org/r/20240426215147.3138211-1-robh@kernel.org [1] -Link: https://lore.kernel.org/r/20260226-02-k1-regulator-names-v1-1-e87695d50159@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit ec1fb4e55df47ed043ab2ccc6787e39b9d67e49b) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 10 +++++----- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++-- - 2 files changed, 7 insertions(+), 7 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index ed88507b84e9..404b69c47b91 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -33,7 +33,7 @@ led1 { - }; - }; - -- pcie_vcc_3v3: pcie-vcc3v3 { -+ pcie_vcc_3v3: regulator-pcie-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "PCIE_VCC3V3"; - regulator-min-microvolt = <3300000>; -@@ -41,7 +41,7 @@ pcie_vcc_3v3: pcie-vcc3v3 { - regulator-always-on; - }; - -- reg_dc_in: dc-in-12v { -+ reg_dc_in: regulator-dc-in-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_in_12v"; - regulator-min-microvolt = <12000000>; -@@ -50,7 +50,7 @@ reg_dc_in: dc-in-12v { - regulator-always-on; - }; - -- reg_vcc_4v: vcc-4v { -+ reg_vcc_4v: regulator-vcc-4v { - compatible = "regulator-fixed"; - regulator-name = "vcc_4v"; - regulator-min-microvolt = <4000000>; -@@ -60,7 +60,7 @@ reg_vcc_4v: vcc-4v { - vin-supply = <®_dc_in>; - }; - -- usb3-vbus-5v { -+ regulator-usb3-vbus-5v { - compatible = "regulator-fixed"; - regulator-name = "USB30_VBUS"; - regulator-min-microvolt = <5000000>; -@@ -70,7 +70,7 @@ usb3-vbus-5v { - enable-active-high; - }; - -- usb3_hub_5v: usb3-hub-5v { -+ usb3_hub_5v: regulator-usb3-hub-5v { - compatible = "regulator-fixed"; - regulator-name = "USB30_HUB"; - regulator-min-microvolt = <5000000>; -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index e2702a781734..9959c8023ece 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -21,7 +21,7 @@ chosen { - stdout-path = "serial0"; - }; - -- reg_dc_in: dc-in-12v { -+ reg_dc_in: regulator-dc-in-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_in_12v"; - regulator-min-microvolt = <12000000>; -@@ -30,7 +30,7 @@ reg_dc_in: dc-in-12v { - regulator-always-on; - }; - -- reg_vcc_4v: vcc-4v { -+ reg_vcc_4v: regulator-vcc-4v { - compatible = "regulator-fixed"; - regulator-name = "vcc_4v"; - regulator-min-microvolt = <4000000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch b/SPECS/linux-lts/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch new file mode 100644 index 0000000000..d84cac3c6d --- /dev/null +++ b/SPECS/linux-lts/0216-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch @@ -0,0 +1,126 @@ +From d685ab6d599ba502610b5f425c35683c2c838c0a Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 4 Mar 2026 07:36:42 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add clock tree + +Add clock support to SpacemiT K3 SoC, the clock tree consist of several +blocks which are APBC, APMU, DCIU, MPUM. + +Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-1-50a0aa53a245@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 67072c8cd48c1fbb95cea39239eba5526395fcf5) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++ + 1 file changed, 75 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index b69cf81b5d55..e3d7f3102fd5 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -4,6 +4,7 @@ + * Copyright (c) 2026 Guodong Xu + */ + ++#include + #include + + /dts-v1/; +@@ -398,6 +399,36 @@ core3 { + }; + }; + ++ clocks { ++ vctcxo_1m: clock-1m { ++ compatible = "fixed-clock"; ++ clock-frequency = <1000000>; ++ clock-output-names = "vctcxo_1m"; ++ #clock-cells = <0>; ++ }; ++ ++ vctcxo_24m: clock-24m { ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ clock-output-names = "vctcxo_24m"; ++ #clock-cells = <0>; ++ }; ++ ++ vctcxo_3m: clock-3m { ++ compatible = "fixed-clock"; ++ clock-frequency = <3000000>; ++ clock-output-names = "vctcxo_3m"; ++ #clock-cells = <0>; ++ }; ++ ++ osc_32k: clock-32k { ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++ clock-output-names = "osc_32k"; ++ #clock-cells = <0>; ++ }; ++ }; ++ + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&saplic>; +@@ -406,6 +437,15 @@ soc: soc { + dma-noncoherent; + ranges; + ++ syscon_apbc: system-controller@d4015000 { ++ compatible = "spacemit,k3-syscon-apbc"; ++ reg = <0x0 0xd4015000 0x0 0x1000>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; ++ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ + uart0: serial@d4017000 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017000 0x0 0x100>; +@@ -506,6 +546,41 @@ uart10: serial@d401f000 { + status = "disabled"; + }; + ++ syscon_mpmu: system-controller@d4050000 { ++ compatible = "spacemit,k3-syscon-mpmu"; ++ reg = <0x0 0xd4050000 0x0 0x10000>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; ++ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; ++ #clock-cells = <1>; ++ #power-domain-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ pll: clock-controller@d4090000 { ++ compatible = "spacemit,k3-pll"; ++ reg = <0x0 0xd4090000 0x0 0x10000>; ++ clocks = <&vctcxo_24m>; ++ spacemit,mpmu = <&syscon_mpmu>; ++ #clock-cells = <1>; ++ }; ++ ++ syscon_apmu: system-controller@d4282800 { ++ compatible = "spacemit,k3-syscon-apmu"; ++ reg = <0x0 0xd4282800 0x0 0x400>; ++ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; ++ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; ++ #clock-cells = <1>; ++ #power-domain-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ syscon_dciu: system-controller@d8440000 { ++ compatible = "spacemit,k3-syscon-dciu"; ++ reg = <0x0 0xd8440000 0x0 0xc000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ + simsic: interrupt-controller@e0400000 { + compatible = "spacemit,k3-imsics", "riscv,imsics"; + reg = <0x0 0xe0400000 0x0 0x200000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0217-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch b/SPECS/linux-lts/0217-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch deleted file mode 100644 index 29c5e0b70c..0000000000 --- a/SPECS/linux-lts/0217-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 6763f6325a6f023a8781d9eda31e4313f90861b7 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 9 Mar 2026 11:00:00 +0800 -Subject: [PATCH 217/467] UPSTREAM: riscv: dts: spacemit: Add - 'linux,pci-domain' to PCIe nodes for K1 - -The SpacemiT K1 SoC has 3 PCIe EP controller nodes. Add the -'linux,pci-domain' property to assign a PCI domain number to -each of the controllers instead of assigning it randomly. - -This creates a stable sysfs path, allowing userspace scripts -to reliably target specific PCIe devices (such as PCIe NICs). - -Signed-off-by: Chukun Pan -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260309030000.1157040-1-amadeus@jmu.edu.cn -Signed-off-by: Yixun Lan -(cherry picked from commit 86314111f654310a69c9775e35e263c036031675) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 529ec68e9c23..d2015201f8e5 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -1033,6 +1033,7 @@ pcie-bus { - #size-cells = <2>; - dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, - <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; -+ - pcie0: pcie@ca000000 { - device_type = "pci"; - compatible = "spacemit,k1-pcie"; -@@ -1044,6 +1045,7 @@ pcie0: pcie@ca000000 { - "atu", - "config", - "link"; -+ linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, -@@ -1087,6 +1089,7 @@ pcie1: pcie@ca400000 { - "atu", - "config", - "link"; -+ linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, -@@ -1130,6 +1133,7 @@ pcie2: pcie@ca800000 { - "atu", - "config", - "link"; -+ linux,pci-domain = <2>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, --- -2.53.0 - diff --git a/SPECS/linux-lts/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch b/SPECS/linux-lts/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch new file mode 100644 index 0000000000..43081756d0 --- /dev/null +++ b/SPECS/linux-lts/0217-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch @@ -0,0 +1,38 @@ +From 26584036220607376da285b0c0cf42306e1dc824 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 4 Mar 2026 07:36:43 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add pinctrl support + +Populate pinctrl node in Device Tree for SpacemiT K3 SoC, So devices +can request pinctrl resource properly. + +Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-2-50a0aa53a245@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit d8944577496b5b99061d3b2020704fc86ab1f9e6) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index e3d7f3102fd5..6449ab056293 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -536,6 +536,14 @@ uart9: serial@d4017800 { + status = "disabled"; + }; + ++ pinctrl: pinctrl@d401e000 { ++ compatible = "spacemit,k3-pinctrl"; ++ reg = <0x0 0xd401e000 0x0 0x1000>; ++ clocks = <&syscon_apbc CLK_APBC_AIB>, ++ <&syscon_apbc CLK_APBC_AIB_BUS>; ++ clock-names = "func", "bus"; ++ }; ++ + uart10: serial@d401f000 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd401f000 0x0 0x100>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0218-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch b/SPECS/linux-lts/0218-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch deleted file mode 100644 index cbfd5a28a6..0000000000 --- a/SPECS/linux-lts/0218-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 8a9141deb50f0c4e00218a10123b0b9653a96872 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 4 Mar 2026 07:19:39 +0000 -Subject: [PATCH 218/467] UPSTREAM: dt-bindings: serial: 8250: spacemit: fix - clock property for K3 SoC - -The UART of SpacemiT K3 SoC has same clock property as K1 generation which -request two clock sources, fix the binding otherwise will get DT check -warnings. - -Acked-by: Greg Kroah-Hartman -Acked-by: Rob Herring (Arm) -Link: https://lore.kernel.org/r/20260304-01-uart-clock-names-v1-1-338483f04a8b@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit 606a6b8bca570aa4f838ddd410345a2937bd98eb) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/serial/8250.yaml | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml -index b243afa69a1a..0d4ae9a62f4c 100644 ---- a/Documentation/devicetree/bindings/serial/8250.yaml -+++ b/Documentation/devicetree/bindings/serial/8250.yaml -@@ -63,7 +63,9 @@ allOf: - properties: - compatible: - contains: -- const: spacemit,k1-uart -+ enum: -+ - spacemit,k1-uart -+ - spacemit,k3-uart - then: - properties: - clock-names: -@@ -76,6 +78,7 @@ allOf: - contains: - enum: - - spacemit,k1-uart -+ - spacemit,k3-uart - - nxp,lpc1850-uart - then: - required: --- -2.53.0 - diff --git a/SPECS/linux-lts/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch b/SPECS/linux-lts/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch new file mode 100644 index 0000000000..dae1e8f109 --- /dev/null +++ b/SPECS/linux-lts/0218-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch @@ -0,0 +1,48 @@ +From d0197dc9c7ce0b6d04f508db631f06668553d958 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 4 Mar 2026 07:36:44 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add GPIO support + +Add GPIO node in the Device Tree, so devices are able to request GPIO +resource properly. + +Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-3-50a0aa53a245@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 20b77926864203e10b85af5276b17c2812d92ec1) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 6449ab056293..3683a1a65362 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -536,6 +536,24 @@ uart9: serial@d4017800 { + status = "disabled"; + }; + ++ gpio: gpio@d4019000 { ++ compatible = "spacemit,k3-gpio"; ++ reg = <0x0 0xd4019000 0x0 0x100>; ++ clocks = <&syscon_apbc CLK_APBC_GPIO>, ++ <&syscon_apbc CLK_APBC_GPIO_BUS>; ++ clock-names = "core", "bus"; ++ gpio-controller; ++ #gpio-cells = <3>; ++ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ gpio-ranges = <&pinctrl 0 0 0 32>, ++ <&pinctrl 1 0 32 32>, ++ <&pinctrl 2 0 64 32>, ++ <&pinctrl 3 0 96 32>; ++ }; ++ + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k3-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0219-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch b/SPECS/linux-lts/0219-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch deleted file mode 100644 index 08aa7a8885..0000000000 --- a/SPECS/linux-lts/0219-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch +++ /dev/null @@ -1,126 +0,0 @@ -From d6d720c6f2938cc35fbb2411f4bcfffe2d3210cc Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 4 Mar 2026 07:36:42 +0000 -Subject: [PATCH 219/467] UPSTREAM: riscv: dts: spacemit: k3: add clock tree - -Add clock support to SpacemiT K3 SoC, the clock tree consist of several -blocks which are APBC, APMU, DCIU, MPUM. - -Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-1-50a0aa53a245@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit 67072c8cd48c1fbb95cea39239eba5526395fcf5) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++ - 1 file changed, 75 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index b69cf81b5d55..e3d7f3102fd5 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -4,6 +4,7 @@ - * Copyright (c) 2026 Guodong Xu - */ - -+#include - #include - - /dts-v1/; -@@ -398,6 +399,36 @@ core3 { - }; - }; - -+ clocks { -+ vctcxo_1m: clock-1m { -+ compatible = "fixed-clock"; -+ clock-frequency = <1000000>; -+ clock-output-names = "vctcxo_1m"; -+ #clock-cells = <0>; -+ }; -+ -+ vctcxo_24m: clock-24m { -+ compatible = "fixed-clock"; -+ clock-frequency = <24000000>; -+ clock-output-names = "vctcxo_24m"; -+ #clock-cells = <0>; -+ }; -+ -+ vctcxo_3m: clock-3m { -+ compatible = "fixed-clock"; -+ clock-frequency = <3000000>; -+ clock-output-names = "vctcxo_3m"; -+ #clock-cells = <0>; -+ }; -+ -+ osc_32k: clock-32k { -+ compatible = "fixed-clock"; -+ clock-frequency = <32000>; -+ clock-output-names = "osc_32k"; -+ #clock-cells = <0>; -+ }; -+ }; -+ - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&saplic>; -@@ -406,6 +437,15 @@ soc: soc { - dma-noncoherent; - ranges; - -+ syscon_apbc: system-controller@d4015000 { -+ compatible = "spacemit,k3-syscon-apbc"; -+ reg = <0x0 0xd4015000 0x0 0x1000>; -+ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; -+ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ - uart0: serial@d4017000 { - compatible = "spacemit,k3-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017000 0x0 0x100>; -@@ -506,6 +546,41 @@ uart10: serial@d401f000 { - status = "disabled"; - }; - -+ syscon_mpmu: system-controller@d4050000 { -+ compatible = "spacemit,k3-syscon-mpmu"; -+ reg = <0x0 0xd4050000 0x0 0x10000>; -+ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; -+ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; -+ #clock-cells = <1>; -+ #power-domain-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ pll: clock-controller@d4090000 { -+ compatible = "spacemit,k3-pll"; -+ reg = <0x0 0xd4090000 0x0 0x10000>; -+ clocks = <&vctcxo_24m>; -+ spacemit,mpmu = <&syscon_mpmu>; -+ #clock-cells = <1>; -+ }; -+ -+ syscon_apmu: system-controller@d4282800 { -+ compatible = "spacemit,k3-syscon-apmu"; -+ reg = <0x0 0xd4282800 0x0 0x400>; -+ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; -+ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; -+ #clock-cells = <1>; -+ #power-domain-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ syscon_dciu: system-controller@d8440000 { -+ compatible = "spacemit,k3-syscon-dciu"; -+ reg = <0x0 0xd8440000 0x0 0xc000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ - simsic: interrupt-controller@e0400000 { - compatible = "spacemit,k3-imsics", "riscv,imsics"; - reg = <0x0 0xe0400000 0x0 0x200000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch b/SPECS/linux-lts/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch new file mode 100644 index 0000000000..581044da67 --- /dev/null +++ b/SPECS/linux-lts/0219-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch @@ -0,0 +1,206 @@ +From 186d384a785aeb3b664585647bd06ee2009145dd Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 4 Mar 2026 07:36:45 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add full resource to + UART + +Previously the UART rely on external bootloader to initialize clock, +pinctrl and reset, to solve this, explicitly adding those resource in +Device Tree, so UART driver will handle them properly. + +Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-4-50a0aa53a245@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit 28a7f755d7c9a4b9c41c12620fb4885f39b554ad) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 ++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 24 +++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 51 ++++++++++++++++---- + 3 files changed, 68 insertions(+), 10 deletions(-) + create mode 100644 arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index b691304d4b74..b098dbd0e7a1 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -5,6 +5,7 @@ + */ + + #include "k3.dtsi" ++#include "k3-pinctrl.dtsi" + + / { + model = "SpacemiT K3 Pico-ITX"; +@@ -25,5 +26,7 @@ memory@100000000 { + }; + + &uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_0_cfg>; + status = "okay"; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +new file mode 100644 +index 000000000000..efb0f1572188 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -0,0 +1,24 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (c) 2026 Yixun Lan ++ */ ++ ++#include ++ ++#define K3_PADCONF(pin, func) (((pin) << 16) | (func)) ++ ++/* Map GPIO pin to each bank's */ ++#define K3_GPIO(x) (x / 32) (x % 32) ++ ++&pinctrl { ++ /omit-if-no-ref/ ++ uart0_0_cfg: uart0-0-cfg { ++ uart0-0-pins { ++ pinmux = , /* uart0 tx */ ++ ; /* uart0 rx */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 3683a1a65362..a3a8ceddabec 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -5,6 +5,7 @@ + */ + + #include ++#include + #include + + /dts-v1/; +@@ -451,7 +452,10 @@ uart0: serial@d4017000 { + reg = <0x0 0xd4017000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART0>, ++ <&syscon_apbc CLK_APBC_UART0_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART0>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -461,7 +465,10 @@ uart2: serial@d4017100 { + reg = <0x0 0xd4017100 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART2>, ++ <&syscon_apbc CLK_APBC_UART2_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART2>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -471,7 +478,10 @@ uart3: serial@d4017200 { + reg = <0x0 0xd4017200 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART3>, ++ <&syscon_apbc CLK_APBC_UART3_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART3>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -481,7 +491,10 @@ uart4: serial@d4017300 { + reg = <0x0 0xd4017300 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART4>, ++ <&syscon_apbc CLK_APBC_UART4_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART4>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -491,7 +504,10 @@ uart5: serial@d4017400 { + reg = <0x0 0xd4017400 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART5>, ++ <&syscon_apbc CLK_APBC_UART5_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART5>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -501,7 +517,10 @@ uart6: serial@d4017500 { + reg = <0x0 0xd4017500 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART6>, ++ <&syscon_apbc CLK_APBC_UART6_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART6>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -511,7 +530,10 @@ uart7: serial@d4017600 { + reg = <0x0 0xd4017600 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART7>, ++ <&syscon_apbc CLK_APBC_UART7_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART7>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -521,7 +543,10 @@ uart8: serial@d4017700 { + reg = <0x0 0xd4017700 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART8>, ++ <&syscon_apbc CLK_APBC_UART8_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART8>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -531,7 +556,10 @@ uart9: serial@d4017800 { + reg = <0x0 0xd4017800 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART9>, ++ <&syscon_apbc CLK_APBC_UART9_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART9>; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +@@ -567,7 +595,10 @@ uart10: serial@d401f000 { + reg = <0x0 0xd401f000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; +- clock-frequency = <14700000>; ++ clocks = <&syscon_apbc CLK_APBC_UART10>, ++ <&syscon_apbc CLK_APBC_UART10_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_APBC_UART10>; + interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch b/SPECS/linux-lts/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch new file mode 100644 index 0000000000..a15e56ca61 --- /dev/null +++ b/SPECS/linux-lts/0220-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch @@ -0,0 +1,59 @@ +From 8ded8df1d9dccc63760629834a87ae2c8615e042 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 20 Mar 2026 07:15:37 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: dwc3: spacemit: add support + for K3 SoC + +Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC. + +The USB2.0 host controller in K3 SoC actually use DWC3 IP but only support +USB2.0 functionality, thus in the hardware layer, it has only one USB2 PHY. +While in K1 SoC, the USB controller has both USB2 and USB3 Combo PHY +connected, but able to work in a reduced USB2.0 mode which requres only +one USB2 PHY, leaves the USB3 Combo PHY to PCIe controller. So both K1 +and K3 SoC are able to work in the USB2.0 mode which requires one PHY. + +Explicitly reduce number of phy property to minimal one. + +Signed-off-by: Yixun Lan +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260320-02-k3-usb20-support-v2-1-308ea0e44038@kernel.org +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit e7e86965a69d0f6797116e54dda01b56deca71c0) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml +index 0f0b5e061ca1..cc27b363ca79 100644 +--- a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml ++++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml +@@ -27,7 +27,9 @@ allOf: + + properties: + compatible: +- const: spacemit,k1-dwc3 ++ enum: ++ - spacemit,k1-dwc3 ++ - spacemit,k3-dwc3 + + reg: + maxItems: 1 +@@ -42,11 +44,13 @@ properties: + maxItems: 1 + + phys: ++ minItems: 1 + items: + - description: phandle to USB2/HS PHY + - description: phandle to USB3/SS PHY + + phy-names: ++ minItems: 1 + items: + - const: usb2-phy + - const: usb3-phy +-- +2.53.0 + diff --git a/SPECS/linux-lts/0220-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch b/SPECS/linux-lts/0220-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch deleted file mode 100644 index 7467adfc98..0000000000 --- a/SPECS/linux-lts/0220-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch +++ /dev/null @@ -1,39 +0,0 @@ -From b712bbdcd69a0cf77827e15a2b8d0c593a348c55 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 4 Mar 2026 07:36:43 +0000 -Subject: [PATCH 220/467] UPSTREAM: riscv: dts: spacemit: k3: add pinctrl - support - -Populate pinctrl node in Device Tree for SpacemiT K3 SoC, So devices -can request pinctrl resource properly. - -Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-2-50a0aa53a245@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit d8944577496b5b99061d3b2020704fc86ab1f9e6) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index e3d7f3102fd5..6449ab056293 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -536,6 +536,14 @@ uart9: serial@d4017800 { - status = "disabled"; - }; - -+ pinctrl: pinctrl@d401e000 { -+ compatible = "spacemit,k3-pinctrl"; -+ reg = <0x0 0xd401e000 0x0 0x1000>; -+ clocks = <&syscon_apbc CLK_APBC_AIB>, -+ <&syscon_apbc CLK_APBC_AIB_BUS>; -+ clock-names = "func", "bus"; -+ }; -+ - uart10: serial@d401f000 { - compatible = "spacemit,k3-uart", "intel,xscale-uart"; - reg = <0x0 0xd401f000 0x0 0x100>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0221-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch b/SPECS/linux-lts/0221-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch deleted file mode 100644 index 267f0b7a53..0000000000 --- a/SPECS/linux-lts/0221-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 42bb1ee59c5be1344c00b635eb294286c0516236 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 4 Mar 2026 07:36:44 +0000 -Subject: [PATCH 221/467] UPSTREAM: riscv: dts: spacemit: k3: add GPIO support - -Add GPIO node in the Device Tree, so devices are able to request GPIO -resource properly. - -Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-3-50a0aa53a245@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit 20b77926864203e10b85af5276b17c2812d92ec1) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 6449ab056293..3683a1a65362 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -536,6 +536,24 @@ uart9: serial@d4017800 { - status = "disabled"; - }; - -+ gpio: gpio@d4019000 { -+ compatible = "spacemit,k3-gpio"; -+ reg = <0x0 0xd4019000 0x0 0x100>; -+ clocks = <&syscon_apbc CLK_APBC_GPIO>, -+ <&syscon_apbc CLK_APBC_GPIO_BUS>; -+ clock-names = "core", "bus"; -+ gpio-controller; -+ #gpio-cells = <3>; -+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&saplic>; -+ interrupt-controller; -+ #interrupt-cells = <3>; -+ gpio-ranges = <&pinctrl 0 0 0 32>, -+ <&pinctrl 1 0 32 32>, -+ <&pinctrl 2 0 64 32>, -+ <&pinctrl 3 0 96 32>; -+ }; -+ - pinctrl: pinctrl@d401e000 { - compatible = "spacemit,k3-pinctrl"; - reg = <0x0 0xd401e000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch b/SPECS/linux-lts/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch new file mode 100644 index 0000000000..45a1cbb328 --- /dev/null +++ b/SPECS/linux-lts/0221-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch @@ -0,0 +1,33 @@ +From 27133a501e88e5b271c1a5c98f2013d1f8dc931a Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 20 Mar 2026 07:15:38 +0000 +Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: dwc3-generic-plat: spacemit: add + support for K3 SoC + +Add support for the DWC3 USB controller which found in SpacemiT K3 SoC. + +Acked-by: Thinh Nguyen +Signed-off-by: Yixun Lan +Link: https://patch.msgid.link/20260320-02-k3-usb20-support-v2-2-308ea0e44038@kernel.org +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit c05cf9d274daf72dc7e433480cf2e0e888f6bd89) +Signed-off-by: Han Gao +--- + drivers/usb/dwc3/dwc3-generic-plat.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c +index e846844e0023..28219968b8b0 100644 +--- a/drivers/usb/dwc3/dwc3-generic-plat.c ++++ b/drivers/usb/dwc3/dwc3-generic-plat.c +@@ -212,6 +212,7 @@ static const struct dwc3_generic_config eic7700_dwc3 = { + + static const struct of_device_id dwc3_generic_of_match[] = { + { .compatible = "spacemit,k1-dwc3", }, ++ { .compatible = "spacemit,k3-dwc3", }, + { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, + { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, + { /* sentinel */ } +-- +2.53.0 + diff --git a/SPECS/linux-lts/0222-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch b/SPECS/linux-lts/0222-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch deleted file mode 100644 index 5ed83a3077..0000000000 --- a/SPECS/linux-lts/0222-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch +++ /dev/null @@ -1,206 +0,0 @@ -From e189d040b406ed393e4e7d5bf768de16b63cdf18 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 4 Mar 2026 07:36:45 +0000 -Subject: [PATCH 222/467] UPSTREAM: riscv: dts: spacemit: k3: add full resource - to UART - -Previously the UART rely on external bootloader to initialize clock, -pinctrl and reset, to solve this, explicitly adding those resource in -Device Tree, so UART driver will handle them properly. - -Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-4-50a0aa53a245@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit 28a7f755d7c9a4b9c41c12620fb4885f39b554ad) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 ++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 24 +++++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 51 ++++++++++++++++---- - 3 files changed, 68 insertions(+), 10 deletions(-) - create mode 100644 arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index b691304d4b74..b098dbd0e7a1 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -5,6 +5,7 @@ - */ - - #include "k3.dtsi" -+#include "k3-pinctrl.dtsi" - - / { - model = "SpacemiT K3 Pico-ITX"; -@@ -25,5 +26,7 @@ memory@100000000 { - }; - - &uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_0_cfg>; - status = "okay"; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -new file mode 100644 -index 000000000000..efb0f1572188 ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: GPL-2.0 OR MIT -+/* -+ * Copyright (c) 2026 Yixun Lan -+ */ -+ -+#include -+ -+#define K3_PADCONF(pin, func) (((pin) << 16) | (func)) -+ -+/* Map GPIO pin to each bank's */ -+#define K3_GPIO(x) (x / 32) (x % 32) -+ -+&pinctrl { -+ /omit-if-no-ref/ -+ uart0_0_cfg: uart0-0-cfg { -+ uart0-0-pins { -+ pinmux = , /* uart0 tx */ -+ ; /* uart0 rx */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 3683a1a65362..a3a8ceddabec 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -5,6 +5,7 @@ - */ - - #include -+#include - #include - - /dts-v1/; -@@ -451,7 +452,10 @@ uart0: serial@d4017000 { - reg = <0x0 0xd4017000 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART0>, -+ <&syscon_apbc CLK_APBC_UART0_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART0>; - interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -461,7 +465,10 @@ uart2: serial@d4017100 { - reg = <0x0 0xd4017100 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART2>, -+ <&syscon_apbc CLK_APBC_UART2_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART2>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -471,7 +478,10 @@ uart3: serial@d4017200 { - reg = <0x0 0xd4017200 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART3>, -+ <&syscon_apbc CLK_APBC_UART3_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART3>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -481,7 +491,10 @@ uart4: serial@d4017300 { - reg = <0x0 0xd4017300 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART4>, -+ <&syscon_apbc CLK_APBC_UART4_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART4>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -491,7 +504,10 @@ uart5: serial@d4017400 { - reg = <0x0 0xd4017400 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART5>, -+ <&syscon_apbc CLK_APBC_UART5_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART5>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -501,7 +517,10 @@ uart6: serial@d4017500 { - reg = <0x0 0xd4017500 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART6>, -+ <&syscon_apbc CLK_APBC_UART6_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART6>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -511,7 +530,10 @@ uart7: serial@d4017600 { - reg = <0x0 0xd4017600 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART7>, -+ <&syscon_apbc CLK_APBC_UART7_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART7>; - interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -521,7 +543,10 @@ uart8: serial@d4017700 { - reg = <0x0 0xd4017700 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART8>, -+ <&syscon_apbc CLK_APBC_UART8_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART8>; - interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -531,7 +556,10 @@ uart9: serial@d4017800 { - reg = <0x0 0xd4017800 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART9>, -+ <&syscon_apbc CLK_APBC_UART9_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART9>; - interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; -@@ -567,7 +595,10 @@ uart10: serial@d401f000 { - reg = <0x0 0xd401f000 0x0 0x100>; - reg-shift = <2>; - reg-io-width = <4>; -- clock-frequency = <14700000>; -+ clocks = <&syscon_apbc CLK_APBC_UART10>, -+ <&syscon_apbc CLK_APBC_UART10_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_APBC_UART10>; - interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch b/SPECS/linux-lts/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch new file mode 100644 index 0000000000..e9139f8f74 --- /dev/null +++ b/SPECS/linux-lts/0222-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch @@ -0,0 +1,84 @@ +From ec33bc462214da036d45ea0a3822c34e9f3d422b Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Thu, 26 Mar 2026 18:00:10 +0800 +Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: Add optional VBUS regulator support + to SpacemiT K1 + +Some SpacemiT K1 boards (like OrangePi R2S) provide USB VBUS +through a controllable regulator. Add support for the optional +vbus-supply property so the regulator can be properly managed +in host mode instead of left always-on. Note that this doesn't +apply to USB Hub downstream ports with different VBUS supplies. + +The enabled and disabled actions of the regulator are handled +automatically by devm_regulator_get_enable_optional(). + +Signed-off-by: Chukun Pan +Acked-by: Thinh Nguyen +Reviewed-by: Anand Moon +Link: https://patch.msgid.link/20260326100010.3588454-2-amadeus@jmu.edu.cn +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 764c2e6e60bf17910d84e7179fee14129e053b96) +Signed-off-by: Han Gao +--- + drivers/usb/dwc3/dwc3-generic-plat.c | 23 ++++++++++++++++++++++- + 1 file changed, 22 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c +index 28219968b8b0..69b7e6227b3b 100644 +--- a/drivers/usb/dwc3/dwc3-generic-plat.c ++++ b/drivers/usb/dwc3/dwc3-generic-plat.c +@@ -12,6 +12,8 @@ + #include + #include + #include ++#include ++#include + #include "glue.h" + + #define EIC7700_HSP_BUS_FILTER_EN BIT(0) +@@ -69,6 +71,20 @@ static int dwc3_eic7700_init(struct dwc3_generic *dwc3g) + return 0; + } + ++static int dwc3_spacemit_k1_init(struct dwc3_generic *dwc3g) ++{ ++ struct device *dev = dwc3g->dev; ++ ++ if (usb_get_dr_mode(dev) == USB_DR_MODE_HOST) { ++ int ret = devm_regulator_get_enable_optional(dev, "vbus"); ++ ++ if (ret && ret != -ENODEV) ++ return dev_err_probe(dev, ret, "failed to enable VBUS\n"); ++ } ++ ++ return 0; ++} ++ + static int dwc3_generic_probe(struct platform_device *pdev) + { + const struct dwc3_generic_config *plat_config; +@@ -201,6 +217,11 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { + dwc3_generic_runtime_idle) + }; + ++static const struct dwc3_generic_config spacemit_k1_dwc3 = { ++ .init = dwc3_spacemit_k1_init, ++ .properties = DWC3_DEFAULT_PROPERTIES, ++}; ++ + static const struct dwc3_generic_config fsl_ls1028_dwc3 = { + .properties.gsbuscfg0_reqinfo = 0x2222, + }; +@@ -211,7 +232,7 @@ static const struct dwc3_generic_config eic7700_dwc3 = { + }; + + static const struct of_device_id dwc3_generic_of_match[] = { +- { .compatible = "spacemit,k1-dwc3", }, ++ { .compatible = "spacemit,k1-dwc3", &spacemit_k1_dwc3}, + { .compatible = "spacemit,k3-dwc3", }, + { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, + { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0223-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch b/SPECS/linux-lts/0223-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch deleted file mode 100644 index 11ec0b2493..0000000000 --- a/SPECS/linux-lts/0223-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 65d15c8340d9e4aa40a623ff2449950059808d92 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 20 Mar 2026 07:15:37 +0000 -Subject: [PATCH 223/467] UPSTREAM: dt-bindings: usb: dwc3: spacemit: add - support for K3 SoC - -Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC. - -The USB2.0 host controller in K3 SoC actually use DWC3 IP but only support -USB2.0 functionality, thus in the hardware layer, it has only one USB2 PHY. -While in K1 SoC, the USB controller has both USB2 and USB3 Combo PHY -connected, but able to work in a reduced USB2.0 mode which requres only -one USB2 PHY, leaves the USB3 Combo PHY to PCIe controller. So both K1 -and K3 SoC are able to work in the USB2.0 mode which requires one PHY. - -Explicitly reduce number of phy property to minimal one. - -Signed-off-by: Yixun Lan -Acked-by: Conor Dooley -Link: https://patch.msgid.link/20260320-02-k3-usb20-support-v2-1-308ea0e44038@kernel.org -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit e7e86965a69d0f6797116e54dda01b56deca71c0) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml -index 0f0b5e061ca1..cc27b363ca79 100644 ---- a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml -+++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml -@@ -27,7 +27,9 @@ allOf: - - properties: - compatible: -- const: spacemit,k1-dwc3 -+ enum: -+ - spacemit,k1-dwc3 -+ - spacemit,k3-dwc3 - - reg: - maxItems: 1 -@@ -42,11 +44,13 @@ properties: - maxItems: 1 - - phys: -+ minItems: 1 - items: - - description: phandle to USB2/HS PHY - - description: phandle to USB3/SS PHY - - phy-names: -+ minItems: 1 - items: - - const: usb2-phy - - const: usb3-phy --- -2.53.0 - diff --git a/SPECS/linux-lts/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch b/SPECS/linux-lts/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch new file mode 100644 index 0000000000..4c498e66d6 --- /dev/null +++ b/SPECS/linux-lts/0223-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch @@ -0,0 +1,148 @@ +From feb6ae05030bda7ec7a43a8384cfdffc80d33e30 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Wed, 18 Mar 2026 18:00:00 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: reorder phy nodes for K1 + +Reorder the PHY nodes of USB and PCIe to the correct positions based on +the register address. This improves the readability and maintainability +of the DT. No functional change is introduced by this reordering. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260318100000.3934516-1-amadeus@jmu.edu.cn +Signed-off-by: Yixun Lan +(cherry picked from commit eac600d5cc42b04e799fb65169b8f4060773381b) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 108 +++++++++++++-------------- + 1 file changed, 54 insertions(+), 54 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index d2015201f8e5..f0bad6855c97 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -359,6 +359,60 @@ syscon_rcpu2: system-controller@c0888000 { + #reset-cells = <1>; + }; + ++ usbphy2: phy@c0a30000 { ++ compatible = "spacemit,k1-usb2-phy"; ++ reg = <0x0 0xc0a30000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_USB30>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ combo_phy: phy@c0b10000 { ++ compatible = "spacemit,k1-combo-phy"; ++ reg = <0x0 0xc0b10000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>, ++ <&syscon_apmu CLK_PCIE0_DBI>, ++ <&syscon_apmu CLK_PCIE0_MASTER>, ++ <&syscon_apmu CLK_PCIE0_SLAVE>; ++ clock-names = "refclk", ++ "dbi", ++ "mstr", ++ "slv"; ++ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, ++ <&syscon_apmu RESET_PCIE0_DBI>, ++ <&syscon_apmu RESET_PCIE0_MASTER>, ++ <&syscon_apmu RESET_PCIE0_SLAVE>; ++ reset-names = "phy", ++ "dbi", ++ "mstr", ++ "slv"; ++ #phy-cells = <1>; ++ spacemit,apmu = <&syscon_apmu>; ++ status = "disabled"; ++ }; ++ ++ pcie1_phy: phy@c0c10000 { ++ compatible = "spacemit,k1-pcie-phy"; ++ reg = <0x0 0xc0c10000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>; ++ clock-names = "refclk"; ++ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; ++ reset-names = "phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pcie2_phy: phy@c0d10000 { ++ compatible = "spacemit,k1-pcie-phy"; ++ reg = <0x0 0xc0d10000 0x0 0x1000>; ++ clocks = <&vctcxo_24m>; ++ clock-names = "refclk"; ++ resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; ++ reset-names = "phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@d4010800 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd4010800 0x0 0x38>; +@@ -429,60 +483,6 @@ i2c5: i2c@d4013800 { + status = "disabled"; + }; + +- usbphy2: phy@c0a30000 { +- compatible = "spacemit,k1-usb2-phy"; +- reg = <0x0 0xc0a30000 0x0 0x200>; +- clocks = <&syscon_apmu CLK_USB30>; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- combo_phy: phy@c0b10000 { +- compatible = "spacemit,k1-combo-phy"; +- reg = <0x0 0xc0b10000 0x0 0x1000>; +- clocks = <&vctcxo_24m>, +- <&syscon_apmu CLK_PCIE0_DBI>, +- <&syscon_apmu CLK_PCIE0_MASTER>, +- <&syscon_apmu CLK_PCIE0_SLAVE>; +- clock-names = "refclk", +- "dbi", +- "mstr", +- "slv"; +- resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, +- <&syscon_apmu RESET_PCIE0_DBI>, +- <&syscon_apmu RESET_PCIE0_MASTER>, +- <&syscon_apmu RESET_PCIE0_SLAVE>; +- reset-names = "phy", +- "dbi", +- "mstr", +- "slv"; +- #phy-cells = <1>; +- spacemit,apmu = <&syscon_apmu>; +- status = "disabled"; +- }; +- +- pcie1_phy: phy@c0c10000 { +- compatible = "spacemit,k1-pcie-phy"; +- reg = <0x0 0xc0c10000 0x0 0x1000>; +- clocks = <&vctcxo_24m>; +- clock-names = "refclk"; +- resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; +- reset-names = "phy"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- +- pcie2_phy: phy@c0d10000 { +- compatible = "spacemit,k1-pcie-phy"; +- reg = <0x0 0xc0d10000 0x0 0x1000>; +- clocks = <&vctcxo_24m>; +- clock-names = "refclk"; +- resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; +- reset-names = "phy"; +- #phy-cells = <0>; +- status = "disabled"; +- }; +- + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k1-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch b/SPECS/linux-lts/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch new file mode 100644 index 0000000000..7d60f42287 --- /dev/null +++ b/SPECS/linux-lts/0224-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch @@ -0,0 +1,42 @@ +From 9c90526d6c53498c2b0fce296ea54822274f4e03 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Sun, 22 Mar 2026 21:25:01 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: drop incorrect pinctrl + for combo PHY + +The combo PHY on the Banana Pi F3 is used for the USB 3.0 port. The high +speed differential lanes are always configured as such, and do not +require a pinctrl entry. + +The existing pinctrl entry only configures PCIe secondary pins, which +are unused for USB and instead routed to the MIPI CSI1 connector. + +Remove this incorrect pinctrl entry. + +Fixes: 0be016a4b5d1b9 ("riscv: dts: spacemit: PCIe and PHY-related updates") +Signed-off-by: Aurelien Jarno +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260322202502.2205755-1-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit c68360c0d636dae71f766b7b296ddfcf2827ccc7) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 404b69c47b91..5790d927b93d 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -81,8 +81,6 @@ usb3_hub_5v: regulator-usb3-hub-5v { + }; + + &combo_phy { +- pinctrl-names = "default"; +- pinctrl-0 = <&pcie0_3_cfg>; + status = "okay"; + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0224-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch b/SPECS/linux-lts/0224-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch deleted file mode 100644 index dc96a39982..0000000000 --- a/SPECS/linux-lts/0224-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch +++ /dev/null @@ -1,33 +0,0 @@ -From d139bb98d6afd681a1d2b0a68a1986ce01b0e4b7 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 20 Mar 2026 07:15:38 +0000 -Subject: [PATCH 224/467] UPSTREAM: usb: dwc3: dwc3-generic-plat: spacemit: add - support for K3 SoC - -Add support for the DWC3 USB controller which found in SpacemiT K3 SoC. - -Acked-by: Thinh Nguyen -Signed-off-by: Yixun Lan -Link: https://patch.msgid.link/20260320-02-k3-usb20-support-v2-2-308ea0e44038@kernel.org -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit c05cf9d274daf72dc7e433480cf2e0e888f6bd89) -Signed-off-by: Han Gao ---- - drivers/usb/dwc3/dwc3-generic-plat.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c -index e846844e0023..28219968b8b0 100644 ---- a/drivers/usb/dwc3/dwc3-generic-plat.c -+++ b/drivers/usb/dwc3/dwc3-generic-plat.c -@@ -212,6 +212,7 @@ static const struct dwc3_generic_config eic7700_dwc3 = { - - static const struct of_device_id dwc3_generic_of_match[] = { - { .compatible = "spacemit,k1-dwc3", }, -+ { .compatible = "spacemit,k3-dwc3", }, - { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, - { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, - { /* sentinel */ } --- -2.53.0 - diff --git a/SPECS/linux-lts/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch b/SPECS/linux-lts/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch new file mode 100644 index 0000000000..daa6d30ac8 --- /dev/null +++ b/SPECS/linux-lts/0225-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch @@ -0,0 +1,241 @@ +From f1fd9849a3a86e6e7567394bcfbd7e80314e1925 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 26 Mar 2026 09:46:17 +0800 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add ethernet device for + K3 + +Add all ethernet device nodes for K3 SoC. + +Signed-off-by: Inochi Amaoto +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326014617.1011732-1-inochiama@gmail.com +Signed-off-by: Yixun Lan +(cherry picked from commit 74657a376960252e248089e518cfaaf813906989) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 20 ++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 34 ++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 117 +++++++++++++++++++ + 3 files changed, 171 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index b098dbd0e7a1..504fe6bd46b2 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -3,6 +3,7 @@ + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Guodong Xu + */ ++#include + + #include "k3.dtsi" + #include "k3-pinctrl.dtsi" +@@ -12,6 +13,7 @@ / { + compatible = "spacemit,k3-pico-itx", "spacemit,k3"; + + aliases { ++ ethernet0 = ð0; + serial0 = &uart0; + }; + +@@ -25,6 +27,24 @@ memory@100000000 { + }; + }; + ++ð0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&phy0>; ++ status = "okay"; ++ ++ mdio { ++ phy0: phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <10000>; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index efb0f1572188..a7b5d10c332e 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -11,6 +11,40 @@ + #define K3_GPIO(x) (x / 32) (x % 32) + + &pinctrl { ++ gmac0_rgmii_0_cfg: gmac0-rgmii-0-cfg { ++ gmac0-rgmii-0-pins { ++ pinmux = , /* gmac0_rxdv */ ++ , /* gmac0_rx_d0 */ ++ , /* gmac0_rx_d1 */ ++ , /* gmac0_rx_clk */ ++ , /* gmac0_rx_d2 */ ++ , /* gmac0_rx_d3 */ ++ , /* gmac0_tx_d0 */ ++ , /* gmac0_tx_d1 */ ++ , /* gmac0_tx_clk */ ++ , /* gmac0_tx_d2 */ ++ , /* gmac0_tx_d3 */ ++ , /* gmac0_tx_en */ ++ , /* gmac0_mdc */ ++ ; /* gmac0_mdio */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ power-source = <1800>; ++ }; ++ ++ }; ++ ++ gmac0_phy_0_cfg: gmac0-phy-0-cfg { ++ gmac0-phy-0-pins { ++ pinmux = ; /* gmac0_int */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ power-source = <1800>; ++ }; ++ }; ++ + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index a3a8ceddabec..5f4818cd5d6d 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -438,6 +438,123 @@ soc: soc { + dma-noncoherent; + ranges; + ++ eth0: ethernet@cac80000 { ++ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; ++ reg = <0x0 0xcac80000 0x0 0x2000>; ++ clocks = <&syscon_apmu CLK_APMU_EMAC0_BUS>, ++ <&syscon_apmu CLK_APMU_EMAC0_1588>, ++ <&syscon_apmu CLK_APMU_EMAC0_RGMII_TX>; ++ clock-names = "stmmaceth", "ptp_ref", "tx"; ++ interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, ++ <276 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ resets = <&syscon_apmu RESET_APMU_EMAC0>; ++ reset-names = "stmmaceth"; ++ rx-fifo-depth = <8192>; ++ tx-fifo-depth = <8192>; ++ snps,multicast-filter-bins = <64>; ++ snps,perfect-filter-entries = <32>; ++ snps,aal; ++ snps,tso; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ snps,force_sf_dma_mode; ++ snps,axi-config = <&gmac0_axi_setup>; ++ spacemit,apmu = <&syscon_apmu 0x3e4 0x3e8>; ++ status = "disabled"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ gmac0_axi_setup: stmmac-axi-config { ++ snps,wr_osr_lmt = <0xf>; ++ snps,rd_osr_lmt = <0xf>; ++ /* max axi burst len is 256 */ ++ snps,blen = <256 128 64 32 16 0 0>; ++ }; ++ }; ++ ++ eth1: ethernet@cac82000 { ++ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; ++ reg = <0x0 0xcac82000 0x0 0x2000>; ++ clocks = <&syscon_apmu CLK_APMU_EMAC1_BUS>, ++ <&syscon_apmu CLK_APMU_EMAC1_1588>, ++ <&syscon_apmu CLK_APMU_EMAC1_RGMII_TX>; ++ clock-names = "stmmaceth", "ptp_ref", "tx"; ++ interrupts = <133 IRQ_TYPE_LEVEL_HIGH>, ++ <277 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ resets = <&syscon_apmu RESET_APMU_EMAC1>; ++ reset-names = "stmmaceth"; ++ rx-fifo-depth = <8192>; ++ tx-fifo-depth = <8192>; ++ snps,multicast-filter-bins = <64>; ++ snps,perfect-filter-entries = <32>; ++ snps,aal; ++ snps,tso; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ snps,force_sf_dma_mode; ++ snps,axi-config = <&gmac1_axi_setup>; ++ spacemit,apmu = <&syscon_apmu 0x3ec 0x3f0>; ++ status = "disabled"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ gmac1_axi_setup: stmmac-axi-config { ++ snps,wr_osr_lmt = <0xf>; ++ snps,rd_osr_lmt = <0xf>; ++ /* max axi burst len is 256 */ ++ snps,blen = <256 128 64 32 16 0 0>; ++ }; ++ }; ++ ++ eth2: ethernet@cac8e000 { ++ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; ++ reg = <0x0 0xcac8e000 0x0 0x2000>; ++ clocks = <&syscon_apmu CLK_APMU_EMAC2_BUS>, ++ <&syscon_apmu CLK_APMU_EMAC2_1588>, ++ <&syscon_apmu CLK_APMU_EMAC2_RGMII_TX>; ++ clock-names = "stmmaceth", "ptp_ref", "tx"; ++ interrupts = <130 IRQ_TYPE_LEVEL_HIGH>, ++ <278 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ resets = <&syscon_apmu RESET_APMU_EMAC2>; ++ reset-names = "stmmaceth"; ++ rx-fifo-depth = <4096>; ++ tx-fifo-depth = <4096>; ++ snps,multicast-filter-bins = <64>; ++ snps,perfect-filter-entries = <32>; ++ snps,aal; ++ snps,tso; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ snps,force_sf_dma_mode; ++ snps,axi-config = <&gmac2_axi_setup>; ++ spacemit,apmu = <&syscon_apmu 0x248 0x24c>; ++ status = "disabled"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ gmac2_axi_setup: stmmac-axi-config { ++ snps,wr_osr_lmt = <0xf>; ++ snps,rd_osr_lmt = <0xf>; ++ /* max axi burst len is 256 */ ++ snps,blen = <256 128 64 32 16 0 0>; ++ }; ++ }; ++ + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0225-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch b/SPECS/linux-lts/0225-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch deleted file mode 100644 index 2b7267977c..0000000000 --- a/SPECS/linux-lts/0225-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 9990dc7ec3ce2387190d0ea86d2050589b85cd73 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Thu, 26 Mar 2026 18:00:10 +0800 -Subject: [PATCH 225/467] UPSTREAM: usb: dwc3: Add optional VBUS regulator - support to SpacemiT K1 - -Some SpacemiT K1 boards (like OrangePi R2S) provide USB VBUS -through a controllable regulator. Add support for the optional -vbus-supply property so the regulator can be properly managed -in host mode instead of left always-on. Note that this doesn't -apply to USB Hub downstream ports with different VBUS supplies. - -The enabled and disabled actions of the regulator are handled -automatically by devm_regulator_get_enable_optional(). - -Signed-off-by: Chukun Pan -Acked-by: Thinh Nguyen -Reviewed-by: Anand Moon -Link: https://patch.msgid.link/20260326100010.3588454-2-amadeus@jmu.edu.cn -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit 764c2e6e60bf17910d84e7179fee14129e053b96) -Signed-off-by: Han Gao ---- - drivers/usb/dwc3/dwc3-generic-plat.c | 23 ++++++++++++++++++++++- - 1 file changed, 22 insertions(+), 1 deletion(-) - -diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c -index 28219968b8b0..69b7e6227b3b 100644 ---- a/drivers/usb/dwc3/dwc3-generic-plat.c -+++ b/drivers/usb/dwc3/dwc3-generic-plat.c -@@ -12,6 +12,8 @@ - #include - #include - #include -+#include -+#include - #include "glue.h" - - #define EIC7700_HSP_BUS_FILTER_EN BIT(0) -@@ -69,6 +71,20 @@ static int dwc3_eic7700_init(struct dwc3_generic *dwc3g) - return 0; - } - -+static int dwc3_spacemit_k1_init(struct dwc3_generic *dwc3g) -+{ -+ struct device *dev = dwc3g->dev; -+ -+ if (usb_get_dr_mode(dev) == USB_DR_MODE_HOST) { -+ int ret = devm_regulator_get_enable_optional(dev, "vbus"); -+ -+ if (ret && ret != -ENODEV) -+ return dev_err_probe(dev, ret, "failed to enable VBUS\n"); -+ } -+ -+ return 0; -+} -+ - static int dwc3_generic_probe(struct platform_device *pdev) - { - const struct dwc3_generic_config *plat_config; -@@ -201,6 +217,11 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = { - dwc3_generic_runtime_idle) - }; - -+static const struct dwc3_generic_config spacemit_k1_dwc3 = { -+ .init = dwc3_spacemit_k1_init, -+ .properties = DWC3_DEFAULT_PROPERTIES, -+}; -+ - static const struct dwc3_generic_config fsl_ls1028_dwc3 = { - .properties.gsbuscfg0_reqinfo = 0x2222, - }; -@@ -211,7 +232,7 @@ static const struct dwc3_generic_config eic7700_dwc3 = { - }; - - static const struct of_device_id dwc3_generic_of_match[] = { -- { .compatible = "spacemit,k1-dwc3", }, -+ { .compatible = "spacemit,k1-dwc3", &spacemit_k1_dwc3}, - { .compatible = "spacemit,k3-dwc3", }, - { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, - { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, --- -2.53.0 - diff --git a/SPECS/linux-lts/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch b/SPECS/linux-lts/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch new file mode 100644 index 0000000000..0ef10a2c37 --- /dev/null +++ b/SPECS/linux-lts/0226-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch @@ -0,0 +1,60 @@ +From 22e068c1b0db347abe57240b5f4e6aea284b400a Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 26 Mar 2026 19:35:29 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add LEDs for Milk-V + Jupiter board + +The Milk-V Jupiter board provides support for two LEDs through the front +panel header. The "Power LED" indicates the system is running, and the +"HDD LED" shows disk activity. Configure the corresponding LED triggers +accordingly. + +Caveats: +- The LEDs are driven through a 4.7k series resistor, making them + quite faint. +- The disk activity trigger requires a storage controller on the M.2 or + PCIe interface. That said, it matches the purpose and the vendor + kernel. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326183745.1370642-2-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 334e64abacd3df4005de80b082d0dbf02b453c76) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 9959c8023ece..3cd83c5924e4 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -21,6 +21,23 @@ chosen { + stdout-path = "serial0"; + }; + ++ leds { ++ compatible = "gpio-leds"; ++ ++ led1 { ++ label = "pwr-led"; ++ gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-on"; ++ default-state = "on"; ++ }; ++ ++ led2 { ++ label = "hdd-led"; ++ gpios = <&gpio K1_GPIO(92) GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "disk-activity"; ++ }; ++ }; ++ + reg_dc_in: regulator-dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0226-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch b/SPECS/linux-lts/0226-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch deleted file mode 100644 index a511212ed8..0000000000 --- a/SPECS/linux-lts/0226-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch +++ /dev/null @@ -1,149 +0,0 @@ -From eed2d8946ef831dead32e3b9c4d588b283ae1195 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Wed, 18 Mar 2026 18:00:00 +0800 -Subject: [PATCH 226/467] UPSTREAM: riscv: dts: spacemit: reorder phy nodes for - K1 - -Reorder the PHY nodes of USB and PCIe to the correct positions based on -the register address. This improves the readability and maintainability -of the DT. No functional change is introduced by this reordering. - -Signed-off-by: Chukun Pan -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260318100000.3934516-1-amadeus@jmu.edu.cn -Signed-off-by: Yixun Lan -(cherry picked from commit eac600d5cc42b04e799fb65169b8f4060773381b) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 108 +++++++++++++-------------- - 1 file changed, 54 insertions(+), 54 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index d2015201f8e5..f0bad6855c97 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -359,6 +359,60 @@ syscon_rcpu2: system-controller@c0888000 { - #reset-cells = <1>; - }; - -+ usbphy2: phy@c0a30000 { -+ compatible = "spacemit,k1-usb2-phy"; -+ reg = <0x0 0xc0a30000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_USB30>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ combo_phy: phy@c0b10000 { -+ compatible = "spacemit,k1-combo-phy"; -+ reg = <0x0 0xc0b10000 0x0 0x1000>; -+ clocks = <&vctcxo_24m>, -+ <&syscon_apmu CLK_PCIE0_DBI>, -+ <&syscon_apmu CLK_PCIE0_MASTER>, -+ <&syscon_apmu CLK_PCIE0_SLAVE>; -+ clock-names = "refclk", -+ "dbi", -+ "mstr", -+ "slv"; -+ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, -+ <&syscon_apmu RESET_PCIE0_DBI>, -+ <&syscon_apmu RESET_PCIE0_MASTER>, -+ <&syscon_apmu RESET_PCIE0_SLAVE>; -+ reset-names = "phy", -+ "dbi", -+ "mstr", -+ "slv"; -+ #phy-cells = <1>; -+ spacemit,apmu = <&syscon_apmu>; -+ status = "disabled"; -+ }; -+ -+ pcie1_phy: phy@c0c10000 { -+ compatible = "spacemit,k1-pcie-phy"; -+ reg = <0x0 0xc0c10000 0x0 0x1000>; -+ clocks = <&vctcxo_24m>; -+ clock-names = "refclk"; -+ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; -+ reset-names = "phy"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ pcie2_phy: phy@c0d10000 { -+ compatible = "spacemit,k1-pcie-phy"; -+ reg = <0x0 0xc0d10000 0x0 0x1000>; -+ clocks = <&vctcxo_24m>; -+ clock-names = "refclk"; -+ resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; -+ reset-names = "phy"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - i2c0: i2c@d4010800 { - compatible = "spacemit,k1-i2c"; - reg = <0x0 0xd4010800 0x0 0x38>; -@@ -429,60 +483,6 @@ i2c5: i2c@d4013800 { - status = "disabled"; - }; - -- usbphy2: phy@c0a30000 { -- compatible = "spacemit,k1-usb2-phy"; -- reg = <0x0 0xc0a30000 0x0 0x200>; -- clocks = <&syscon_apmu CLK_USB30>; -- #phy-cells = <0>; -- status = "disabled"; -- }; -- -- combo_phy: phy@c0b10000 { -- compatible = "spacemit,k1-combo-phy"; -- reg = <0x0 0xc0b10000 0x0 0x1000>; -- clocks = <&vctcxo_24m>, -- <&syscon_apmu CLK_PCIE0_DBI>, -- <&syscon_apmu CLK_PCIE0_MASTER>, -- <&syscon_apmu CLK_PCIE0_SLAVE>; -- clock-names = "refclk", -- "dbi", -- "mstr", -- "slv"; -- resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, -- <&syscon_apmu RESET_PCIE0_DBI>, -- <&syscon_apmu RESET_PCIE0_MASTER>, -- <&syscon_apmu RESET_PCIE0_SLAVE>; -- reset-names = "phy", -- "dbi", -- "mstr", -- "slv"; -- #phy-cells = <1>; -- spacemit,apmu = <&syscon_apmu>; -- status = "disabled"; -- }; -- -- pcie1_phy: phy@c0c10000 { -- compatible = "spacemit,k1-pcie-phy"; -- reg = <0x0 0xc0c10000 0x0 0x1000>; -- clocks = <&vctcxo_24m>; -- clock-names = "refclk"; -- resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; -- reset-names = "phy"; -- #phy-cells = <0>; -- status = "disabled"; -- }; -- -- pcie2_phy: phy@c0d10000 { -- compatible = "spacemit,k1-pcie-phy"; -- reg = <0x0 0xc0d10000 0x0 0x1000>; -- clocks = <&vctcxo_24m>; -- clock-names = "refclk"; -- resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; -- reset-names = "phy"; -- #phy-cells = <0>; -- status = "disabled"; -- }; -- - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k1-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch b/SPECS/linux-lts/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch new file mode 100644 index 0000000000..d1757910da --- /dev/null +++ b/SPECS/linux-lts/0227-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch @@ -0,0 +1,61 @@ +From fd0cc30ddc8df5ecd44ae759b0d7ba0d8b5140c5 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 26 Mar 2026 19:35:30 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add 24c04 eeprom on + Milk-V Jupiter + +The Milk-V Jupiter board includes a 24c04 eeprom on the i2c2 bus. The +eeprom contains an ONIE TLV table, which on the board I tested only +provides a product-name entry. Expose it via an onie,tlv-layout nvmem +layout. + +The eeprom is marked as read-only since its contents are not supposed to +be modified. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326183745.1370642-3-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 77156216f1d0f57e1cfce3452410db20468edca4) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 3cd83c5924e4..bd48208a370c 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -108,6 +108,28 @@ &pdma { + status = "okay"; + }; + ++&i2c2 { ++ pinctrl-0 = <&i2c2_0_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ eeprom@50 { ++ compatible = "atmel,24c04"; ++ reg = <0x50>; ++ vcc-supply = <&buck3_1v8>; /* EEPROM_VCC18 */ ++ pagesize = <16>; ++ read-only; ++ size = <512>; ++ ++ nvmem-layout { ++ compatible = "onie,tlv-layout"; ++ ++ product-name { ++ }; ++ }; ++ }; ++}; ++ + &i2c8 { + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0227-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch b/SPECS/linux-lts/0227-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch deleted file mode 100644 index d629f7d904..0000000000 --- a/SPECS/linux-lts/0227-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 16fa682f25aa8efc5b297d6efcaaf5d684c6fd7b Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Sun, 22 Mar 2026 21:25:01 +0100 -Subject: [PATCH 227/467] UPSTREAM: riscv: dts: spacemit: drop incorrect - pinctrl for combo PHY - -The combo PHY on the Banana Pi F3 is used for the USB 3.0 port. The high -speed differential lanes are always configured as such, and do not -require a pinctrl entry. - -The existing pinctrl entry only configures PCIe secondary pins, which -are unused for USB and instead routed to the MIPI CSI1 connector. - -Remove this incorrect pinctrl entry. - -Fixes: 0be016a4b5d1b9 ("riscv: dts: spacemit: PCIe and PHY-related updates") -Signed-off-by: Aurelien Jarno -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260322202502.2205755-1-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit c68360c0d636dae71f766b7b296ddfcf2827ccc7) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 404b69c47b91..5790d927b93d 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -81,8 +81,6 @@ usb3_hub_5v: regulator-usb3-hub-5v { - }; - - &combo_phy { -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_3_cfg>; - status = "okay"; - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0228-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch b/SPECS/linux-lts/0228-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch deleted file mode 100644 index aca0bf2ca8..0000000000 --- a/SPECS/linux-lts/0228-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 03c170ac39ef66094f9171ed83e48fcf67edc777 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Thu, 26 Mar 2026 09:46:17 +0800 -Subject: [PATCH 228/467] UPSTREAM: riscv: dts: spacemit: Add ethernet device - for K3 - -Add all ethernet device nodes for K3 SoC. - -Signed-off-by: Inochi Amaoto -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326014617.1011732-1-inochiama@gmail.com -Signed-off-by: Yixun Lan -(cherry picked from commit 74657a376960252e248089e518cfaaf813906989) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 20 ++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 34 ++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 117 +++++++++++++++++++ - 3 files changed, 171 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index b098dbd0e7a1..504fe6bd46b2 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -3,6 +3,7 @@ - * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd - * Copyright (c) 2026 Guodong Xu - */ -+#include - - #include "k3.dtsi" - #include "k3-pinctrl.dtsi" -@@ -12,6 +13,7 @@ / { - compatible = "spacemit,k3-pico-itx", "spacemit,k3"; - - aliases { -+ ethernet0 = ð0; - serial0 = &uart0; - }; - -@@ -25,6 +27,24 @@ memory@100000000 { - }; - }; - -+ð0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <&phy0>; -+ status = "okay"; -+ -+ mdio { -+ phy0: phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <10000>; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_0_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index efb0f1572188..a7b5d10c332e 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -11,6 +11,40 @@ - #define K3_GPIO(x) (x / 32) (x % 32) - - &pinctrl { -+ gmac0_rgmii_0_cfg: gmac0-rgmii-0-cfg { -+ gmac0-rgmii-0-pins { -+ pinmux = , /* gmac0_rxdv */ -+ , /* gmac0_rx_d0 */ -+ , /* gmac0_rx_d1 */ -+ , /* gmac0_rx_clk */ -+ , /* gmac0_rx_d2 */ -+ , /* gmac0_rx_d3 */ -+ , /* gmac0_tx_d0 */ -+ , /* gmac0_tx_d1 */ -+ , /* gmac0_tx_clk */ -+ , /* gmac0_tx_d2 */ -+ , /* gmac0_tx_d3 */ -+ , /* gmac0_tx_en */ -+ , /* gmac0_mdc */ -+ ; /* gmac0_mdio */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ power-source = <1800>; -+ }; -+ -+ }; -+ -+ gmac0_phy_0_cfg: gmac0-phy-0-cfg { -+ gmac0-phy-0-pins { -+ pinmux = ; /* gmac0_int */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ power-source = <1800>; -+ }; -+ }; -+ - /omit-if-no-ref/ - uart0_0_cfg: uart0-0-cfg { - uart0-0-pins { -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index a3a8ceddabec..5f4818cd5d6d 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -438,6 +438,123 @@ soc: soc { - dma-noncoherent; - ranges; - -+ eth0: ethernet@cac80000 { -+ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; -+ reg = <0x0 0xcac80000 0x0 0x2000>; -+ clocks = <&syscon_apmu CLK_APMU_EMAC0_BUS>, -+ <&syscon_apmu CLK_APMU_EMAC0_1588>, -+ <&syscon_apmu CLK_APMU_EMAC0_RGMII_TX>; -+ clock-names = "stmmaceth", "ptp_ref", "tx"; -+ interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, -+ <276 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "macirq", "eth_wake_irq"; -+ resets = <&syscon_apmu RESET_APMU_EMAC0>; -+ reset-names = "stmmaceth"; -+ rx-fifo-depth = <8192>; -+ tx-fifo-depth = <8192>; -+ snps,multicast-filter-bins = <64>; -+ snps,perfect-filter-entries = <32>; -+ snps,aal; -+ snps,tso; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ snps,force_sf_dma_mode; -+ snps,axi-config = <&gmac0_axi_setup>; -+ spacemit,apmu = <&syscon_apmu 0x3e4 0x3e8>; -+ status = "disabled"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ gmac0_axi_setup: stmmac-axi-config { -+ snps,wr_osr_lmt = <0xf>; -+ snps,rd_osr_lmt = <0xf>; -+ /* max axi burst len is 256 */ -+ snps,blen = <256 128 64 32 16 0 0>; -+ }; -+ }; -+ -+ eth1: ethernet@cac82000 { -+ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; -+ reg = <0x0 0xcac82000 0x0 0x2000>; -+ clocks = <&syscon_apmu CLK_APMU_EMAC1_BUS>, -+ <&syscon_apmu CLK_APMU_EMAC1_1588>, -+ <&syscon_apmu CLK_APMU_EMAC1_RGMII_TX>; -+ clock-names = "stmmaceth", "ptp_ref", "tx"; -+ interrupts = <133 IRQ_TYPE_LEVEL_HIGH>, -+ <277 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "macirq", "eth_wake_irq"; -+ resets = <&syscon_apmu RESET_APMU_EMAC1>; -+ reset-names = "stmmaceth"; -+ rx-fifo-depth = <8192>; -+ tx-fifo-depth = <8192>; -+ snps,multicast-filter-bins = <64>; -+ snps,perfect-filter-entries = <32>; -+ snps,aal; -+ snps,tso; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ snps,force_sf_dma_mode; -+ snps,axi-config = <&gmac1_axi_setup>; -+ spacemit,apmu = <&syscon_apmu 0x3ec 0x3f0>; -+ status = "disabled"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ gmac1_axi_setup: stmmac-axi-config { -+ snps,wr_osr_lmt = <0xf>; -+ snps,rd_osr_lmt = <0xf>; -+ /* max axi burst len is 256 */ -+ snps,blen = <256 128 64 32 16 0 0>; -+ }; -+ }; -+ -+ eth2: ethernet@cac8e000 { -+ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; -+ reg = <0x0 0xcac8e000 0x0 0x2000>; -+ clocks = <&syscon_apmu CLK_APMU_EMAC2_BUS>, -+ <&syscon_apmu CLK_APMU_EMAC2_1588>, -+ <&syscon_apmu CLK_APMU_EMAC2_RGMII_TX>; -+ clock-names = "stmmaceth", "ptp_ref", "tx"; -+ interrupts = <130 IRQ_TYPE_LEVEL_HIGH>, -+ <278 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "macirq", "eth_wake_irq"; -+ resets = <&syscon_apmu RESET_APMU_EMAC2>; -+ reset-names = "stmmaceth"; -+ rx-fifo-depth = <4096>; -+ tx-fifo-depth = <4096>; -+ snps,multicast-filter-bins = <64>; -+ snps,perfect-filter-entries = <32>; -+ snps,aal; -+ snps,tso; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ snps,force_sf_dma_mode; -+ snps,axi-config = <&gmac2_axi_setup>; -+ spacemit,apmu = <&syscon_apmu 0x248 0x24c>; -+ status = "disabled"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ gmac2_axi_setup: stmmac-axi-config { -+ snps,wr_osr_lmt = <0xf>; -+ snps,rd_osr_lmt = <0xf>; -+ /* max axi burst len is 256 */ -+ snps,blen = <256 128 64 32 16 0 0>; -+ }; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k3-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch b/SPECS/linux-lts/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch new file mode 100644 index 0000000000..d6371cd157 --- /dev/null +++ b/SPECS/linux-lts/0228-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch @@ -0,0 +1,37 @@ +From 82fab0710b5af85d582db37f1628e0efe0783003 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 26 Mar 2026 19:35:31 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add i2c aliases on + Milk-V Jupiter + +Add i2c aliases for i2c2 and i2c8 on Milk-V Jupiter. This is useful to +keep a stable number for the /dev entries after loading the i2c-dev +module. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326183745.1370642-4-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 7af5edec73d5d69618541f91600adeb6f35b7d17) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index bd48208a370c..836311c3f035 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -15,6 +15,8 @@ aliases { + ethernet0 = ð0; + ethernet1 = ð1; + serial0 = &uart0; ++ i2c2 = &i2c2; ++ i2c8 = &i2c8; + }; + + chosen { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0229-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch b/SPECS/linux-lts/0229-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch deleted file mode 100644 index 7a250b9fd2..0000000000 --- a/SPECS/linux-lts/0229-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch +++ /dev/null @@ -1,60 +0,0 @@ -From f028688afe776c5820cff9effa08a9558b3e27e7 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Thu, 26 Mar 2026 19:35:29 +0100 -Subject: [PATCH 229/467] UPSTREAM: riscv: dts: spacemit: add LEDs for Milk-V - Jupiter board - -The Milk-V Jupiter board provides support for two LEDs through the front -panel header. The "Power LED" indicates the system is running, and the -"HDD LED" shows disk activity. Configure the corresponding LED triggers -accordingly. - -Caveats: -- The LEDs are driven through a 4.7k series resistor, making them - quite faint. -- The disk activity trigger requires a storage controller on the M.2 or - PCIe interface. That said, it matches the purpose and the vendor - kernel. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326183745.1370642-2-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit 334e64abacd3df4005de80b082d0dbf02b453c76) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 9959c8023ece..3cd83c5924e4 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -21,6 +21,23 @@ chosen { - stdout-path = "serial0"; - }; - -+ leds { -+ compatible = "gpio-leds"; -+ -+ led1 { -+ label = "pwr-led"; -+ gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "default-on"; -+ default-state = "on"; -+ }; -+ -+ led2 { -+ label = "hdd-led"; -+ gpios = <&gpio K1_GPIO(92) GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "disk-activity"; -+ }; -+ }; -+ - reg_dc_in: regulator-dc-in-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_in_12v"; --- -2.53.0 - diff --git a/SPECS/linux-lts/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch b/SPECS/linux-lts/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch new file mode 100644 index 0000000000..7da7a14692 --- /dev/null +++ b/SPECS/linux-lts/0229-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch @@ -0,0 +1,95 @@ +From 8cd168c0e1c6761c9dc36dba489883961c115b69 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 26 Mar 2026 19:35:32 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable QSPI and add SPI + NOR on Milk-V Jupiter + +Add the QSPI controller node for the Milk-V Jupiter board and describe +the attached SPI NOR flash (GD25Q64E). + +The flash supports a frequency up to 133MHz (80 MHz for reads), and the +SoC supports a frequency up to 104 MHz. However tests have shown that +the flash is not reliably detected above 26.5 MHz, consistent with +frequency used in the vendor kernel. Therefore, use this frequency. + +The m25p,fast-read properties is taken from the vendor kernel, and the +GD25Q64E datasheet confirms tha the fast read opcodes are supported. + +Add a corresponding flash partition layout, matching the layout and the +names used in the vendor U-Boot. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326183745.1370642-5-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 2829823956f0f590f5c6b4eafed2dab7a96f69b3) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 43 ++++++++++++++++++- + 1 file changed, 42 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 836311c3f035..bac6438c6753 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -173,7 +173,7 @@ buck3_1v8: buck3 { + regulator-always-on; + }; + +- buck4 { ++ buck4_3v3: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; +@@ -256,6 +256,47 @@ dldo7 { + }; + }; + ++&qspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi_cfg>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <26500000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; ++ vcc-supply = <&buck4_3v3>; /* QSPI_VCC1833 */ ++ m25p,fast-read; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bootinfo@0 { ++ reg = <0x0 0x10000>; ++ }; ++ private@10000 { ++ reg = <0x10000 0x10000>; ++ }; ++ fsbl@20000 { ++ reg = <0x20000 0x40000>; ++ }; ++ env@60000 { ++ reg = <0x60000 0x10000>; ++ }; ++ opensbi@70000 { ++ reg = <0x70000 0x30000>; ++ }; ++ uboot@a00000 { ++ reg = <0xa0000 0x760000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0230-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch b/SPECS/linux-lts/0230-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch deleted file mode 100644 index 526c0f8b8d..0000000000 --- a/SPECS/linux-lts/0230-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 33c5fad73ed5d84207033735a7ebe3c7f3a3401b Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Thu, 26 Mar 2026 19:35:30 +0100 -Subject: [PATCH 230/467] UPSTREAM: riscv: dts: spacemit: add 24c04 eeprom on - Milk-V Jupiter - -The Milk-V Jupiter board includes a 24c04 eeprom on the i2c2 bus. The -eeprom contains an ONIE TLV table, which on the board I tested only -provides a product-name entry. Expose it via an onie,tlv-layout nvmem -layout. - -The eeprom is marked as read-only since its contents are not supposed to -be modified. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326183745.1370642-3-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit 77156216f1d0f57e1cfce3452410db20468edca4) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 22 +++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 3cd83c5924e4..bd48208a370c 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -108,6 +108,28 @@ &pdma { - status = "okay"; - }; - -+&i2c2 { -+ pinctrl-0 = <&i2c2_0_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ eeprom@50 { -+ compatible = "atmel,24c04"; -+ reg = <0x50>; -+ vcc-supply = <&buck3_1v8>; /* EEPROM_VCC18 */ -+ pagesize = <16>; -+ read-only; -+ size = <512>; -+ -+ nvmem-layout { -+ compatible = "onie,tlv-layout"; -+ -+ product-name { -+ }; -+ }; -+ }; -+}; -+ - &i2c8 { - pinctrl-0 = <&i2c8_cfg>; - pinctrl-names = "default"; --- -2.53.0 - diff --git a/SPECS/linux-lts/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch b/SPECS/linux-lts/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch new file mode 100644 index 0000000000..ab6defa852 --- /dev/null +++ b/SPECS/linux-lts/0230-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch @@ -0,0 +1,112 @@ +From 7c97859e0dc8e3a13976fbd8fa3512d2a6469e32 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 26 Mar 2026 19:35:33 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable USB 3 ports on + Milk-V Jupiter + +Enable the DWC3 USB 3.0 controller (USB#2 port in the K1 datasheet) and +its associated combo_phy (USB 3 PHY) and usbphy2 (USB 2 PHY) on the +Milk-V Jupiter board. + +The board uses a VLI VL817 hub, providing four ports. Two are routed to +the 3.0 type-A connectors, and two to the F_USB3 front USB header. The +hub requires two separate 5V power supplies: one for the hub itself and +one for the USB connectors. Add an always-on regulator sourcing 5V from +the DC-IN input, along with two GPIO-controlled fixed regulators to +manage the hub and connectors power supplies. + +Note that the board also provides four USB 2.0 ports (two via type-A +connectors and two via the F_USB2 front USB header), but these are +handled by a different controller (USB#1 port in the K1 datasheet). + +Signed-off-by: Aurelien Jarno +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326183745.1370642-6-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit dce01d8585a22f708b5f1eb621cacd9878258ac8) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 62 +++++++++++++++++++ + 1 file changed, 62 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index bac6438c6753..8eeaf2631b71 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -58,6 +58,41 @@ reg_vcc_4v: regulator-vcc-4v { + regulator-always-on; + vin-supply = <®_dc_in>; + }; ++ ++ reg_vcc_5v: regulator-vcc-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <®_dc_in>; ++ }; ++ ++ regulator-usb3-vbus-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB30_VBUS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ vin-supply = <®_vcc_5v>; ++ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ usb3_hub_5v: regulator-usb3-hub-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "USB30_HUB"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <®_vcc_5v>; ++ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++}; ++ ++&combo_phy { ++ status = "okay"; + }; + + ð0 { +@@ -302,3 +337,30 @@ &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub_2_0: hub@1 { ++ compatible = "usb2109,2817"; ++ reg = <0x1>; ++ vdd-supply = <&usb3_hub_5v>; ++ peer-hub = <&hub_3_0>; ++ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; ++ }; ++ ++ hub_3_0: hub@2 { ++ compatible = "usb2109,817"; ++ reg = <0x2>; ++ vdd-supply = <&usb3_hub_5v>; ++ peer-hub = <&hub_2_0>; ++ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0231-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch b/SPECS/linux-lts/0231-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch deleted file mode 100644 index bf9e8fcaf8..0000000000 --- a/SPECS/linux-lts/0231-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 91f109859aa003662be934a38045864d35c9ba4b Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Thu, 26 Mar 2026 19:35:31 +0100 -Subject: [PATCH 231/467] UPSTREAM: riscv: dts: spacemit: add i2c aliases on - Milk-V Jupiter - -Add i2c aliases for i2c2 and i2c8 on Milk-V Jupiter. This is useful to -keep a stable number for the /dev entries after loading the i2c-dev -module. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326183745.1370642-4-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit 7af5edec73d5d69618541f91600adeb6f35b7d17) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index bd48208a370c..836311c3f035 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -15,6 +15,8 @@ aliases { - ethernet0 = ð0; - ethernet1 = ð1; - serial0 = &uart0; -+ i2c2 = &i2c2; -+ i2c8 = &i2c8; - }; - - chosen { --- -2.53.0 - diff --git a/SPECS/linux-lts/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch b/SPECS/linux-lts/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch new file mode 100644 index 0000000000..37c7e74275 --- /dev/null +++ b/SPECS/linux-lts/0231-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch @@ -0,0 +1,86 @@ +From a6af60e5b4b61218cbfe45507b2a9c0740b13741 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Thu, 26 Mar 2026 19:35:34 +0100 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable PCIe ports on + Milk-V Jupiter + +Enable the two PCIe controller along with and their associated PHY. They +are routed to the M.2 M-key connector and to the PCIe x8 slot. + +Add an always-on regulator sourcing 3.3V from the DC-IN input, to power +the PCIe ports. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Javier Martinez Canillas +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260326183745.1370642-7-aurelien@aurel32.net +Signed-off-by: Yixun Lan +(cherry picked from commit 2b8bd26bbfcdeb1a06127dcd8f9101080133f2a1) +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 42 +++++++++++++++++++ + 1 file changed, 42 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 8eeaf2631b71..afaad59e6bce 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -40,6 +40,16 @@ led2 { + }; + }; + ++ pcie_vcc_3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie_vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <®_dc_in>; ++ }; ++ + reg_dc_in: regulator-dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; +@@ -291,6 +301,38 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++}; ++ ++&pcie1 { ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++}; ++ ++&pcie2 { ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++ status = "okay"; ++}; ++ + &qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch b/SPECS/linux-lts/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch new file mode 100644 index 0000000000..636cc98729 --- /dev/null +++ b/SPECS/linux-lts/0232-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch @@ -0,0 +1,39 @@ +From ffb258a6f70ad79ca6c7b0a4c04cd38fbdd33471 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 25 Mar 2026 09:49:24 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: i2c: spacemit: k3: Add compatible + +Add a compatible string for the I2C controller found in SpacemiT K3 SoC +which use same I2C IP as K1, so make it fallback to K1 compatible. + +Signed-off-by: Yixun Lan +Acked-by: Conor Dooley +Reviewed-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260325-02-k3-i2c-v1-1-78f29c83d9ac@kernel.org +Signed-off-by: Andi Shyti +(cherry picked from commit 4f1e5c967231fefcd04290396724d519961ecffb) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml +index 5896fb120501..8c04c675b25e 100644 +--- a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml ++++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml +@@ -14,7 +14,11 @@ allOf: + + properties: + compatible: +- const: spacemit,k1-i2c ++ oneOf: ++ - items: ++ - const: spacemit,k3-i2c ++ - const: spacemit,k1-i2c ++ - const: spacemit,k1-i2c + + reg: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0232-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch b/SPECS/linux-lts/0232-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch deleted file mode 100644 index f3c36b8033..0000000000 --- a/SPECS/linux-lts/0232-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch +++ /dev/null @@ -1,95 +0,0 @@ -From da2e8b5f724f182ad77cb1d9607a06367e832eb8 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Thu, 26 Mar 2026 19:35:32 +0100 -Subject: [PATCH 232/467] UPSTREAM: riscv: dts: spacemit: enable QSPI and add - SPI NOR on Milk-V Jupiter - -Add the QSPI controller node for the Milk-V Jupiter board and describe -the attached SPI NOR flash (GD25Q64E). - -The flash supports a frequency up to 133MHz (80 MHz for reads), and the -SoC supports a frequency up to 104 MHz. However tests have shown that -the flash is not reliably detected above 26.5 MHz, consistent with -frequency used in the vendor kernel. Therefore, use this frequency. - -The m25p,fast-read properties is taken from the vendor kernel, and the -GD25Q64E datasheet confirms tha the fast read opcodes are supported. - -Add a corresponding flash partition layout, matching the layout and the -names used in the vendor U-Boot. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326183745.1370642-5-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit 2829823956f0f590f5c6b4eafed2dab7a96f69b3) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 43 ++++++++++++++++++- - 1 file changed, 42 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 836311c3f035..bac6438c6753 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -173,7 +173,7 @@ buck3_1v8: buck3 { - regulator-always-on; - }; - -- buck4 { -+ buck4_3v3: buck4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <5000>; -@@ -256,6 +256,47 @@ dldo7 { - }; - }; - -+&qspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qspi_cfg>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <26500000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ vcc-supply = <&buck4_3v3>; /* QSPI_VCC1833 */ -+ m25p,fast-read; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ bootinfo@0 { -+ reg = <0x0 0x10000>; -+ }; -+ private@10000 { -+ reg = <0x10000 0x10000>; -+ }; -+ fsbl@20000 { -+ reg = <0x20000 0x40000>; -+ }; -+ env@60000 { -+ reg = <0x60000 0x10000>; -+ }; -+ opensbi@70000 { -+ reg = <0x70000 0x30000>; -+ }; -+ uboot@a00000 { -+ reg = <0xa0000 0x760000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch b/SPECS/linux-lts/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch new file mode 100644 index 0000000000..4fa6b0eb20 --- /dev/null +++ b/SPECS/linux-lts/0233-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch @@ -0,0 +1,154 @@ +From 2e5ff84331e9d469cf732e06694632b4d7f0a64e Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 27 Mar 2026 11:40:40 +0000 +Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: k3: Add i2c nodes + +Populate all I2C devicetree nodes for SpacemiT K3 SoC. The controller of +i2c3 is reserved for secure domain, and not available from Linux. The +controller of i2c7 simply doesn't exist from hardware perspective, as +vendor directly name the i2c controller used for PMIC as i2c8. + +Reviewed-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260327-02-k3-i2c-v2-1-2119c0918868@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit cb322cbffb1e70b4ca1be7955ed19fe486de8295) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 100 +++++++++++++++++++++++++++ + 1 file changed, 100 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 5f4818cd5d6d..815debd16409 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -555,6 +555,76 @@ gmac2_axi_setup: stmmac-axi-config { + }; + }; + ++ i2c0: i2c@d4010800 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd4010800 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI0>, ++ <&syscon_apbc CLK_APBC_TWSI0_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI0>; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@d4011000 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd4011000 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI1>, ++ <&syscon_apbc CLK_APBC_TWSI1_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI1>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@d4012000 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd4012000 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI2>, ++ <&syscon_apbc CLK_APBC_TWSI2_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI2>; ++ status = "disabled"; ++ }; ++ ++ i2c4: i2c@d4012800 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd4012800 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI4>, ++ <&syscon_apbc CLK_APBC_TWSI4_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI4>; ++ status = "disabled"; ++ }; ++ ++ i2c5: i2c@d4013800 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd4013800 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI5>, ++ <&syscon_apbc CLK_APBC_TWSI5_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI5>; ++ status = "disabled"; ++ }; ++ + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; +@@ -681,6 +751,20 @@ uart9: serial@d4017800 { + status = "disabled"; + }; + ++ i2c6: i2c@d4018800 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd4018800 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI6>, ++ <&syscon_apbc CLK_APBC_TWSI6_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI6>; ++ status = "disabled"; ++ }; ++ + gpio: gpio@d4019000 { + compatible = "spacemit,k3-gpio"; + reg = <0x0 0xd4019000 0x0 0x100>; +@@ -699,6 +783,20 @@ gpio: gpio@d4019000 { + <&pinctrl 3 0 96 32>; + }; + ++ i2c8: i2c@d401d800 { ++ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; ++ reg = <0x0 0xd401d800 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&syscon_apbc CLK_APBC_TWSI8>, ++ <&syscon_apbc CLK_APBC_TWSI8_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ resets = <&syscon_apbc RESET_APBC_TWSI8>; ++ status = "disabled"; ++ }; ++ + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k3-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x1000>; +@@ -794,6 +892,8 @@ clint: timer@e081c000 { + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + ++ /* sec_i2c3: 0xf0614000, not available from Linux */ ++ + mimsic: interrupt-controller@f1000000 { + compatible = "spacemit,k3-imsics", "riscv,imsics"; + reg = <0x0 0xf1000000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0233-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch b/SPECS/linux-lts/0233-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch deleted file mode 100644 index e1e2fcd5ce..0000000000 --- a/SPECS/linux-lts/0233-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 8618f21bd007f6291498d88d9392d4f15cd10805 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Thu, 26 Mar 2026 19:35:33 +0100 -Subject: [PATCH 233/467] UPSTREAM: riscv: dts: spacemit: enable USB 3 ports on - Milk-V Jupiter - -Enable the DWC3 USB 3.0 controller (USB#2 port in the K1 datasheet) and -its associated combo_phy (USB 3 PHY) and usbphy2 (USB 2 PHY) on the -Milk-V Jupiter board. - -The board uses a VLI VL817 hub, providing four ports. Two are routed to -the 3.0 type-A connectors, and two to the F_USB3 front USB header. The -hub requires two separate 5V power supplies: one for the hub itself and -one for the USB connectors. Add an always-on regulator sourcing 5V from -the DC-IN input, along with two GPIO-controlled fixed regulators to -manage the hub and connectors power supplies. - -Note that the board also provides four USB 2.0 ports (two via type-A -connectors and two via the F_USB2 front USB header), but these are -handled by a different controller (USB#1 port in the K1 datasheet). - -Signed-off-by: Aurelien Jarno -Reviewed-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326183745.1370642-6-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit dce01d8585a22f708b5f1eb621cacd9878258ac8) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 62 +++++++++++++++++++ - 1 file changed, 62 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index bac6438c6753..8eeaf2631b71 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -58,6 +58,41 @@ reg_vcc_4v: regulator-vcc-4v { - regulator-always-on; - vin-supply = <®_dc_in>; - }; -+ -+ reg_vcc_5v: regulator-vcc-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_5v"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <®_dc_in>; -+ }; -+ -+ regulator-usb3-vbus-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "USB30_VBUS"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ vin-supply = <®_vcc_5v>; -+ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ usb3_hub_5v: regulator-usb3-hub-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "USB30_HUB"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <®_vcc_5v>; -+ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+}; -+ -+&combo_phy { -+ status = "okay"; - }; - - ð0 { -@@ -302,3 +337,30 @@ &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ hub_2_0: hub@1 { -+ compatible = "usb2109,2817"; -+ reg = <0x1>; -+ vdd-supply = <&usb3_hub_5v>; -+ peer-hub = <&hub_3_0>; -+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; -+ }; -+ -+ hub_3_0: hub@2 { -+ compatible = "usb2109,817"; -+ reg = <0x2>; -+ vdd-supply = <&usb3_hub_5v>; -+ peer-hub = <&hub_2_0>; -+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch b/SPECS/linux-lts/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch new file mode 100644 index 0000000000..fec47cecd6 --- /dev/null +++ b/SPECS/linux-lts/0234-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch @@ -0,0 +1,200 @@ +From 7602638398631706b3b851eeb82562691d9fbf20 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Fri, 27 Mar 2026 11:51:18 +0000 +Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: k3: add P1 PMIC + regulator tree + +Add the P1 PMIC's regulator topology tree for pico-itx board. + +Link: https://lore.kernel.org/r/20260327-02-k3-i2c-v2-1-9c6b374470c6@kernel.org +Signed-off-by: Yixun Lan +(cherry picked from commit af62a095eb0c3359d477b55ef72d2afd94c83c8f) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 147 +++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 11 ++ + 2 files changed, 158 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 504fe6bd46b2..4486dc1fe114 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -25,6 +25,153 @@ memory@100000000 { + device_type = "memory"; + reg = <0x1 0x00000000 0x4 0x00000000>; + }; ++ ++ reg_aux_vcc5v: regulator-aux-vcc5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "AUX_VCC5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++}; ++ ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8_cfg>; ++ status = "okay"; ++ ++ p1@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; ++ vin1-supply = <®_aux_vcc5v>; ++ vin2-supply = <®_aux_vcc5v>; ++ vin3-supply = <®_aux_vcc5v>; ++ vin4-supply = <®_aux_vcc5v>; ++ vin5-supply = <®_aux_vcc5v>; ++ vin6-supply = <®_aux_vcc5v>; ++ aldoin-supply = <®_aux_vcc5v>; ++ dldoin1-supply = <&buck4>; ++ dldoin2-supply = <&buck4>; ++ ++ regulators { ++ buck1: buck1 { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2: buck2 { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3: buck3 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4: buck4 { ++ regulator-min-microvolt = <2100000>; ++ regulator-max-microvolt = <2100000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6: buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <500000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1: aldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ aldo2: aldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ aldo3: aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4: aldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo1: dldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo2: dldo2 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo3: dldo3 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo4: dldo4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ }; ++ ++ dldo5: dldo5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo6: dldo6 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo7: dldo7 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ }; ++ }; + }; + + ð0 { +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index a7b5d10c332e..23899d3f308a 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -45,6 +45,17 @@ gmac0-phy-0-pins { + }; + }; + ++ /omit-if-no-ref/ ++ i2c8_cfg: i2c8-cfg { ++ i2c8-pins { ++ pinmux = , /* i2c8 scl */ ++ ; /* i2c8 sda */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0234-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch b/SPECS/linux-lts/0234-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch deleted file mode 100644 index 7bf6a68c5f..0000000000 --- a/SPECS/linux-lts/0234-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 29c798bc348079c4005d8f1237132733e5fefd2a Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Thu, 26 Mar 2026 19:35:34 +0100 -Subject: [PATCH 234/467] UPSTREAM: riscv: dts: spacemit: enable PCIe ports on - Milk-V Jupiter - -Enable the two PCIe controller along with and their associated PHY. They -are routed to the M.2 M-key connector and to the PCIe x8 slot. - -Add an always-on regulator sourcing 3.3V from the DC-IN input, to power -the PCIe ports. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Javier Martinez Canillas -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260326183745.1370642-7-aurelien@aurel32.net -Signed-off-by: Yixun Lan -(cherry picked from commit 2b8bd26bbfcdeb1a06127dcd8f9101080133f2a1) -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 42 +++++++++++++++++++ - 1 file changed, 42 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 8eeaf2631b71..afaad59e6bce 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -40,6 +40,16 @@ led2 { - }; - }; - -+ pcie_vcc_3v3: regulator-pcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "pcie_vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <®_dc_in>; -+ }; -+ - reg_dc_in: regulator-dc-in-12v { - compatible = "regulator-fixed"; - regulator-name = "dc_in_12v"; -@@ -291,6 +301,38 @@ dldo7 { - }; - }; - -+&pcie1_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_3_cfg>; -+ status = "okay"; -+}; -+ -+&pcie1_port { -+ phys = <&pcie1_phy>; -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+}; -+ -+&pcie1 { -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+ status = "okay"; -+}; -+ -+&pcie2_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_4_cfg>; -+ status = "okay"; -+}; -+ -+&pcie2_port { -+ phys = <&pcie2_phy>; -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+}; -+ -+&pcie2 { -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+ status = "okay"; -+}; -+ - &qspi { - pinctrl-names = "default"; - pinctrl-0 = <&qspi_cfg>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0235-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch b/SPECS/linux-lts/0235-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch deleted file mode 100644 index e9b0909fb8..0000000000 --- a/SPECS/linux-lts/0235-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 06a529a2e71c9d5cfdfe39c8829383f4535447af Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 25 Mar 2026 09:49:24 +0000 -Subject: [PATCH 235/467] UPSTREAM: dt-bindings: i2c: spacemit: k3: Add - compatible - -Add a compatible string for the I2C controller found in SpacemiT K3 SoC -which use same I2C IP as K1, so make it fallback to K1 compatible. - -Signed-off-by: Yixun Lan -Acked-by: Conor Dooley -Reviewed-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260325-02-k3-i2c-v1-1-78f29c83d9ac@kernel.org -Signed-off-by: Andi Shyti -(cherry picked from commit 4f1e5c967231fefcd04290396724d519961ecffb) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml -index 5896fb120501..8c04c675b25e 100644 ---- a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml -+++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml -@@ -14,7 +14,11 @@ allOf: - - properties: - compatible: -- const: spacemit,k1-i2c -+ oneOf: -+ - items: -+ - const: spacemit,k3-i2c -+ - const: spacemit,k1-i2c -+ - const: spacemit,k1-i2c - - reg: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux-lts/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch b/SPECS/linux-lts/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch new file mode 100644 index 0000000000..dc246bac07 --- /dev/null +++ b/SPECS/linux-lts/0235-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch @@ -0,0 +1,50 @@ +From e2f15b90c20c9acc8b6524640ad61e8dd279261b Mon Sep 17 00:00:00 2001 +From: Chen Pei +Date: Tue, 17 Mar 2026 11:48:47 +0800 +Subject: [RUYI PATCH] UPSTREAM: perf symbol: Add RISCV case in get_plt_sizes + +According to RISC-V psABI specification, the PLT (Program Linkage Table) +has the following layout: +- The first PLT entry occupies two 16-byte entries (32 bytes total) +- Subsequent PLT entries take up 16 bytes each + +This aligns with the binutils-gdb implementation which defines the same +PLT sizes for RISC-V architecture. + +Update get_plt_sizes() to set plt_header_size=32 and plt_entry_size=16 +for EM_RISCV, matching the architecture's standard ABI. + +Since AARCH64, LOONGARCH, and RISCV have the same PLT size definition, +they are merged together. + +Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc +Link: https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=bfd/elfnn-riscv.c + +Signed-off-by: Chen Pei +Reviewed-by: Guo Ren +Signed-off-by: Namhyung Kim +(cherry picked from commit 616cd6047cbf736d93808f652086dd10a836005f) +Signed-off-by: Han Gao +--- + tools/perf/util/symbol-elf.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c +index 9602cc51dcc6..dedeb0a25b80 100644 +--- a/tools/perf/util/symbol-elf.c ++++ b/tools/perf/util/symbol-elf.c +@@ -372,10 +372,8 @@ static bool get_plt_sizes(struct dso *dso, GElf_Ehdr *ehdr, GElf_Shdr *shdr_plt, + *plt_entry_size = 12; + return true; + case EM_AARCH64: +- *plt_header_size = 32; +- *plt_entry_size = 16; +- return true; + case EM_LOONGARCH: ++ case EM_RISCV: + *plt_header_size = 32; + *plt_entry_size = 16; + return true; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0236-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch b/SPECS/linux-lts/0236-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch deleted file mode 100644 index bcae7bdbb6..0000000000 --- a/SPECS/linux-lts/0236-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch +++ /dev/null @@ -1,154 +0,0 @@ -From 51e77bd033c67ea1bad41c8dc364dc87af69176a Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 27 Mar 2026 11:40:40 +0000 -Subject: [PATCH 236/467] UPSTREAM: dts: riscv: spacemit: k3: Add i2c nodes - -Populate all I2C devicetree nodes for SpacemiT K3 SoC. The controller of -i2c3 is reserved for secure domain, and not available from Linux. The -controller of i2c7 simply doesn't exist from hardware perspective, as -vendor directly name the i2c controller used for PMIC as i2c8. - -Reviewed-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260327-02-k3-i2c-v2-1-2119c0918868@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit cb322cbffb1e70b4ca1be7955ed19fe486de8295) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 100 +++++++++++++++++++++++++++ - 1 file changed, 100 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 5f4818cd5d6d..815debd16409 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -555,6 +555,76 @@ gmac2_axi_setup: stmmac-axi-config { - }; - }; - -+ i2c0: i2c@d4010800 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd4010800 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI0>, -+ <&syscon_apbc CLK_APBC_TWSI0_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI0>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@d4011000 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd4011000 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI1>, -+ <&syscon_apbc CLK_APBC_TWSI1_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI1>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@d4012000 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd4012000 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI2>, -+ <&syscon_apbc CLK_APBC_TWSI2_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI2>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@d4012800 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd4012800 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI4>, -+ <&syscon_apbc CLK_APBC_TWSI4_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI4>; -+ status = "disabled"; -+ }; -+ -+ i2c5: i2c@d4013800 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd4013800 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI5>, -+ <&syscon_apbc CLK_APBC_TWSI5_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI5>; -+ status = "disabled"; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k3-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; -@@ -681,6 +751,20 @@ uart9: serial@d4017800 { - status = "disabled"; - }; - -+ i2c6: i2c@d4018800 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd4018800 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI6>, -+ <&syscon_apbc CLK_APBC_TWSI6_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI6>; -+ status = "disabled"; -+ }; -+ - gpio: gpio@d4019000 { - compatible = "spacemit,k3-gpio"; - reg = <0x0 0xd4019000 0x0 0x100>; -@@ -699,6 +783,20 @@ gpio: gpio@d4019000 { - <&pinctrl 3 0 96 32>; - }; - -+ i2c8: i2c@d401d800 { -+ compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; -+ reg = <0x0 0xd401d800 0x0 0x38>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&syscon_apbc CLK_APBC_TWSI8>, -+ <&syscon_apbc CLK_APBC_TWSI8_BUS>; -+ clock-names = "func", "bus"; -+ clock-frequency = <400000>; -+ resets = <&syscon_apbc RESET_APBC_TWSI8>; -+ status = "disabled"; -+ }; -+ - pinctrl: pinctrl@d401e000 { - compatible = "spacemit,k3-pinctrl"; - reg = <0x0 0xd401e000 0x0 0x1000>; -@@ -794,6 +892,8 @@ clint: timer@e081c000 { - <&cpu7_intc 3>, <&cpu7_intc 7>; - }; - -+ /* sec_i2c3: 0xf0614000, not available from Linux */ -+ - mimsic: interrupt-controller@f1000000 { - compatible = "spacemit,k3-imsics", "riscv,imsics"; - reg = <0x0 0xf1000000 0x0 0x10000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch b/SPECS/linux-lts/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch new file mode 100644 index 0000000000..4135dc8422 --- /dev/null +++ b/SPECS/linux-lts/0236-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch @@ -0,0 +1,51 @@ +From 88b461165ff138a8bc16b7a3d1540a19c8a3710e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= +Date: Sat, 4 Apr 2026 18:42:40 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: Simplify assignment for UTS_MACHINE +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The BITS variable conveniently allows to simplify the assignment for +UTS_MACHINE. + +Signed-off-by: Uwe Kleine-König (The Capable Hub) +Link: https://patch.msgid.link/20260313164012.1153936-2-u.kleine-koenig@baylibre.com +Signed-off-by: Paul Walmsley +(cherry picked from commit c8d0c36d852ccd7caf9d5a44f3090f80a060c28d) +Signed-off-by: Han Gao +--- + arch/riscv/Makefile | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 4c6de57f65ef..775b5faa4b2e 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -28,7 +28,6 @@ endif + export BITS + ifeq ($(CONFIG_ARCH_RV64I),y) + BITS := 64 +- UTS_MACHINE := riscv64 + + KBUILD_CFLAGS += -mabi=lp64 + KBUILD_AFLAGS += -mabi=lp64 +@@ -39,13 +38,14 @@ ifeq ($(CONFIG_ARCH_RV64I),y) + -Cno-redzone + else + BITS := 32 +- UTS_MACHINE := riscv32 + + KBUILD_CFLAGS += -mabi=ilp32 + KBUILD_AFLAGS += -mabi=ilp32 + KBUILD_LDFLAGS += -melf32lriscv + endif + ++UTS_MACHINE := riscv$(BITS) ++ + # LLVM has an issue with target-features and LTO: https://github.com/llvm/llvm-project/issues/59350 + # Ensure it is aware of linker relaxation with LTO, otherwise relocations may + # be incorrect: https://github.com/llvm/llvm-project/issues/65090 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0237-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch b/SPECS/linux-lts/0237-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch deleted file mode 100644 index 2dbc249507..0000000000 --- a/SPECS/linux-lts/0237-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch +++ /dev/null @@ -1,200 +0,0 @@ -From 3d90cd2fe817a9d87061b1aaf12ab04d512bb830 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Fri, 27 Mar 2026 11:51:18 +0000 -Subject: [PATCH 237/467] UPSTREAM: dts: riscv: spacemit: k3: add P1 PMIC - regulator tree - -Add the P1 PMIC's regulator topology tree for pico-itx board. - -Link: https://lore.kernel.org/r/20260327-02-k3-i2c-v2-1-9c6b374470c6@kernel.org -Signed-off-by: Yixun Lan -(cherry picked from commit af62a095eb0c3359d477b55ef72d2afd94c83c8f) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 147 +++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 11 ++ - 2 files changed, 158 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index 504fe6bd46b2..4486dc1fe114 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -25,6 +25,153 @@ memory@100000000 { - device_type = "memory"; - reg = <0x1 0x00000000 0x4 0x00000000>; - }; -+ -+ reg_aux_vcc5v: regulator-aux-vcc5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "AUX_VCC5V"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+}; -+ -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+ -+ p1@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; -+ vin1-supply = <®_aux_vcc5v>; -+ vin2-supply = <®_aux_vcc5v>; -+ vin3-supply = <®_aux_vcc5v>; -+ vin4-supply = <®_aux_vcc5v>; -+ vin5-supply = <®_aux_vcc5v>; -+ vin6-supply = <®_aux_vcc5v>; -+ aldoin-supply = <®_aux_vcc5v>; -+ dldoin1-supply = <&buck4>; -+ dldoin2-supply = <&buck4>; -+ -+ regulators { -+ buck1: buck1 { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2: buck2 { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3: buck3 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4: buck4 { -+ regulator-min-microvolt = <2100000>; -+ regulator-max-microvolt = <2100000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6: buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <500000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1: aldo1 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ aldo2: aldo2 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ aldo3: aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4: aldo4 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo1: dldo1 { -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo2: dldo2 { -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo3: dldo3 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo4: dldo4 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ }; -+ -+ dldo5: dldo5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo6: dldo6 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo7: dldo7 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ }; -+ }; - }; - - ð0 { -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index a7b5d10c332e..23899d3f308a 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -45,6 +45,17 @@ gmac0-phy-0-pins { - }; - }; - -+ /omit-if-no-ref/ -+ i2c8_cfg: i2c8-cfg { -+ i2c8-pins { -+ pinmux = , /* i2c8 scl */ -+ ; /* i2c8 sda */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ - /omit-if-no-ref/ - uart0_0_cfg: uart0-0-cfg { - uart0-0-pins { --- -2.53.0 - diff --git a/SPECS/linux-lts/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch b/SPECS/linux-lts/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch new file mode 100644 index 0000000000..c12445faca --- /dev/null +++ b/SPECS/linux-lts/0237-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch @@ -0,0 +1,36 @@ +From f64acae7865de9be5e3490b46bc253b9e0d8464e Mon Sep 17 00:00:00 2001 +From: Austin Kim +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: increase COMMAND_LINE_SIZE value to + 2048 + +SoC people may send many parameters to configure the drivers via kernel +command line. If COMMAND_LINE_SIZE is not enough, they may go through +unexpected error. + +To avoid the potential pain, we had better increase COMMAND_LINE_SIZE. + +Signed-off-by: Austin Kim +Link: https://patch.msgid.link/aW3gFmOlA/Z4kmfJ@adminpc-PowerEdge-R7525 +Signed-off-by: Paul Walmsley +(cherry picked from commit 580e626dd0304b4cafb2a5d21c6f0401b44f0ffb) +Signed-off-by: Han Gao +--- + arch/riscv/include/uapi/asm/setup.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/include/uapi/asm/setup.h b/arch/riscv/include/uapi/asm/setup.h +index 66b13a522880..eb4f0209c696 100644 +--- a/arch/riscv/include/uapi/asm/setup.h ++++ b/arch/riscv/include/uapi/asm/setup.h +@@ -3,6 +3,6 @@ + #ifndef _UAPI_ASM_RISCV_SETUP_H + #define _UAPI_ASM_RISCV_SETUP_H + +-#define COMMAND_LINE_SIZE 1024 ++#define COMMAND_LINE_SIZE 2048 + + #endif /* _UAPI_ASM_RISCV_SETUP_H */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0238-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch b/SPECS/linux-lts/0238-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch deleted file mode 100644 index 050b3605d2..0000000000 --- a/SPECS/linux-lts/0238-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 648a8870dbad32008ba12e159e37944eb9d7180e Mon Sep 17 00:00:00 2001 -From: Chen Pei -Date: Tue, 17 Mar 2026 11:48:47 +0800 -Subject: [PATCH 238/467] UPSTREAM: perf symbol: Add RISCV case in - get_plt_sizes - -According to RISC-V psABI specification, the PLT (Program Linkage Table) -has the following layout: -- The first PLT entry occupies two 16-byte entries (32 bytes total) -- Subsequent PLT entries take up 16 bytes each - -This aligns with the binutils-gdb implementation which defines the same -PLT sizes for RISC-V architecture. - -Update get_plt_sizes() to set plt_header_size=32 and plt_entry_size=16 -for EM_RISCV, matching the architecture's standard ABI. - -Since AARCH64, LOONGARCH, and RISCV have the same PLT size definition, -they are merged together. - -Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc -Link: https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=bfd/elfnn-riscv.c - -Signed-off-by: Chen Pei -Reviewed-by: Guo Ren -Signed-off-by: Namhyung Kim -(cherry picked from commit 616cd6047cbf736d93808f652086dd10a836005f) -Signed-off-by: Han Gao ---- - tools/perf/util/symbol-elf.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - -diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c -index 9602cc51dcc6..dedeb0a25b80 100644 ---- a/tools/perf/util/symbol-elf.c -+++ b/tools/perf/util/symbol-elf.c -@@ -372,10 +372,8 @@ static bool get_plt_sizes(struct dso *dso, GElf_Ehdr *ehdr, GElf_Shdr *shdr_plt, - *plt_entry_size = 12; - return true; - case EM_AARCH64: -- *plt_header_size = 32; -- *plt_entry_size = 16; -- return true; - case EM_LOONGARCH: -+ case EM_RISCV: - *plt_header_size = 32; - *plt_entry_size = 16; - return true; --- -2.53.0 - diff --git a/SPECS/linux-lts/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch b/SPECS/linux-lts/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch new file mode 100644 index 0000000000..53eb710553 --- /dev/null +++ b/SPECS/linux-lts/0238-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch @@ -0,0 +1,49 @@ +From 50da2d0c20ed5daeac5e56fc3b173a315118dc29 Mon Sep 17 00:00:00 2001 +From: Yufeng Wang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: acpi: update FADT revision check to 6.6 + +ACPI 6.6 is required for RISC-V as it introduces RISC-V specific +tables such as RHCT (RISC-V Hart Capabilities Table) and +RIMT (RISC-V I/O Mapping Table). + +Update the FADT revision check from 6.5 to 6.6 and remove +the TODO comment since ACPI 6.6 has been officially released. + +Signed-off-by: Yufeng Wang +Reviewed-by: Sunil V L +Acked-by: Heinrich Schuchardt +Reviewed-by: Yao Zi +Link: https://patch.msgid.link/20260305091433.83983-1-r4o5m6e8o@163.com +Signed-off-by: Paul Walmsley +(cherry picked from commit dd598449338212f9262424fa67e40b5643ab6c06) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/acpi.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c +index 71698ee11621..ff681db9f4f1 100644 +--- a/arch/riscv/kernel/acpi.c ++++ b/arch/riscv/kernel/acpi.c +@@ -85,12 +85,12 @@ static int __init acpi_fadt_sanity_check(void) + * The revision in the table header is the FADT's Major revision. The + * FADT also has a minor revision, which is stored in the FADT itself. + * +- * TODO: Currently, we check for 6.5 as the minimum version to check +- * for HW_REDUCED flag. However, once RISC-V updates are released in +- * the ACPI spec, we need to update this check for exact minor revision ++ * ACPI 6.6 is required for RISC-V as it introduces RISC-V specific ++ * tables such as RHCT (RISC-V Hart Capabilities Table) and RIMT ++ * (RISC-V I/O Mapping Table). + */ +- if (table->revision < 6 || (table->revision == 6 && fadt->minor_revision < 5)) +- pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 6.5+\n", ++ if (table->revision < 6 || (table->revision == 6 && fadt->minor_revision < 6)) ++ pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 6.6+\n", + table->revision, fadt->minor_revision); + + if (!(fadt->flags & ACPI_FADT_HW_REDUCED)) { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0239-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch b/SPECS/linux-lts/0239-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch deleted file mode 100644 index 9fe6fe1315..0000000000 --- a/SPECS/linux-lts/0239-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch +++ /dev/null @@ -1,51 +0,0 @@ -From f61f4c49f48046edb4ce0352be894de34dfcd5a3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= -Date: Sat, 4 Apr 2026 18:42:40 -0600 -Subject: [PATCH 239/467] UPSTREAM: riscv: Simplify assignment for UTS_MACHINE -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The BITS variable conveniently allows to simplify the assignment for -UTS_MACHINE. - -Signed-off-by: Uwe Kleine-König (The Capable Hub) -Link: https://patch.msgid.link/20260313164012.1153936-2-u.kleine-koenig@baylibre.com -Signed-off-by: Paul Walmsley -(cherry picked from commit c8d0c36d852ccd7caf9d5a44f3090f80a060c28d) -Signed-off-by: Han Gao ---- - arch/riscv/Makefile | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile -index 4c6de57f65ef..775b5faa4b2e 100644 ---- a/arch/riscv/Makefile -+++ b/arch/riscv/Makefile -@@ -28,7 +28,6 @@ endif - export BITS - ifeq ($(CONFIG_ARCH_RV64I),y) - BITS := 64 -- UTS_MACHINE := riscv64 - - KBUILD_CFLAGS += -mabi=lp64 - KBUILD_AFLAGS += -mabi=lp64 -@@ -39,13 +38,14 @@ ifeq ($(CONFIG_ARCH_RV64I),y) - -Cno-redzone - else - BITS := 32 -- UTS_MACHINE := riscv32 - - KBUILD_CFLAGS += -mabi=ilp32 - KBUILD_AFLAGS += -mabi=ilp32 - KBUILD_LDFLAGS += -melf32lriscv - endif - -+UTS_MACHINE := riscv$(BITS) -+ - # LLVM has an issue with target-features and LTO: https://github.com/llvm/llvm-project/issues/59350 - # Ensure it is aware of linker relaxation with LTO, otherwise relocations may - # be incorrect: https://github.com/llvm/llvm-project/issues/65090 --- -2.53.0 - diff --git a/SPECS/linux-lts/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch b/SPECS/linux-lts/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch new file mode 100644 index 0000000000..03b0b8232a --- /dev/null +++ b/SPECS/linux-lts/0239-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch @@ -0,0 +1,35 @@ +From 527bf47071201cafeeb74ad89ac94e5d61eb3691 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: mm: WARN_ON() for bad addresses in + vmemmap_populate() + +Similarly to the same check in arch/arm64/mm/mmu.c, in +vmemmap_populate(), add a warning for start and end being outside of the +range of vmemmap. + +Signed-off-by: Vivian Wang +Link: https://patch.msgid.link/20260309-riscv-sparsemem-vmemmap-limits-v1-1-f40efe18e3cd@iscas.ac.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit b0217d97eeeaca199eff23102b3fa72ea8c4ddea) +Signed-off-by: Han Gao +--- + arch/riscv/mm/init.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index ee40ca01ac66..8f4e7e505906 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -1486,6 +1486,8 @@ int __meminit vmemmap_check_pmd(pmd_t *pmdp, int node, + int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, + struct vmem_altmap *altmap) + { ++ WARN_ON((start < VMEMMAP_START) || (end > VMEMMAP_END)); ++ + /* + * Note that SPARSEMEM_VMEMMAP is only selected for rv64 and that we + * can't use hugepage mappings for 2-level page table because in case of +-- +2.53.0 + diff --git a/SPECS/linux-lts/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch b/SPECS/linux-lts/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch new file mode 100644 index 0000000000..d8e8ef3623 --- /dev/null +++ b/SPECS/linux-lts/0240-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch @@ -0,0 +1,50 @@ +From 21223e48716232b52be9719f8d4361bc9f82af59 Mon Sep 17 00:00:00 2001 +From: Yufeng Wang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: enable HAVE_IOREMAP_PROT + +RISC-V has implemented pte_pgprot() and selects GENERIC_IOREMAP, +which provides a generic ioremap_prot() implementation. Enable +HAVE_IOREMAP_PROT to activate generic_access_phys() support, which +is useful for debugging (e.g., accessing /dev/mem via gdb). + +Also update the architecture support documentation accordingly. + +Signed-off-by: Yufeng Wang +Link: https://patch.msgid.link/20260306112734.108186-1-r4o5m6e8o@163.com +Signed-off-by: Paul Walmsley +(cherry picked from commit d1f014012571323f3857873d94c2abf9343ef62d) +Signed-off-by: Han Gao +--- + Documentation/features/vm/ioremap_prot/arch-support.txt | 2 +- + arch/riscv/Kconfig | 1 + + 2 files changed, 2 insertions(+), 1 deletion(-) + +diff --git a/Documentation/features/vm/ioremap_prot/arch-support.txt b/Documentation/features/vm/ioremap_prot/arch-support.txt +index 1638c2cb17f1..c0a2d8f56046 100644 +--- a/Documentation/features/vm/ioremap_prot/arch-support.txt ++++ b/Documentation/features/vm/ioremap_prot/arch-support.txt +@@ -20,7 +20,7 @@ + | openrisc: | TODO | + | parisc: | TODO | + | powerpc: | ok | +- | riscv: | TODO | ++ | riscv: | ok | + | s390: | ok | + | sh: | ok | + | sparc: | TODO | +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index fadec20b87a8..9c43346fabcd 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -113,6 +113,7 @@ config RISCV + select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO && 64BIT + select GENERIC_IDLE_POLL_SETUP + select GENERIC_IOREMAP if MMU ++ select HAVE_IOREMAP_PROT if MMU + select GENERIC_IRQ_IPI if SMP + select GENERIC_IRQ_IPI_MUX if SMP + select GENERIC_IRQ_MULTI_HANDLER +-- +2.53.0 + diff --git a/SPECS/linux-lts/0240-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch b/SPECS/linux-lts/0240-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch deleted file mode 100644 index 35ec7040c2..0000000000 --- a/SPECS/linux-lts/0240-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 3d0d22f6281de4b039180e5e5096041117526be7 Mon Sep 17 00:00:00 2001 -From: Austin Kim -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 240/467] UPSTREAM: riscv: increase COMMAND_LINE_SIZE value to - 2048 - -SoC people may send many parameters to configure the drivers via kernel -command line. If COMMAND_LINE_SIZE is not enough, they may go through -unexpected error. - -To avoid the potential pain, we had better increase COMMAND_LINE_SIZE. - -Signed-off-by: Austin Kim -Link: https://patch.msgid.link/aW3gFmOlA/Z4kmfJ@adminpc-PowerEdge-R7525 -Signed-off-by: Paul Walmsley -(cherry picked from commit 580e626dd0304b4cafb2a5d21c6f0401b44f0ffb) -Signed-off-by: Han Gao ---- - arch/riscv/include/uapi/asm/setup.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/include/uapi/asm/setup.h b/arch/riscv/include/uapi/asm/setup.h -index 66b13a522880..eb4f0209c696 100644 ---- a/arch/riscv/include/uapi/asm/setup.h -+++ b/arch/riscv/include/uapi/asm/setup.h -@@ -3,6 +3,6 @@ - #ifndef _UAPI_ASM_RISCV_SETUP_H - #define _UAPI_ASM_RISCV_SETUP_H - --#define COMMAND_LINE_SIZE 1024 -+#define COMMAND_LINE_SIZE 2048 - - #endif /* _UAPI_ASM_RISCV_SETUP_H */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0241-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch b/SPECS/linux-lts/0241-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch deleted file mode 100644 index 0a4ec4eaf8..0000000000 --- a/SPECS/linux-lts/0241-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch +++ /dev/null @@ -1,50 +0,0 @@ -From 40f9fb3f9445f0a2bab1227aad457b443ce8c21f Mon Sep 17 00:00:00 2001 -From: Yufeng Wang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 241/467] UPSTREAM: riscv: acpi: update FADT revision check to - 6.6 - -ACPI 6.6 is required for RISC-V as it introduces RISC-V specific -tables such as RHCT (RISC-V Hart Capabilities Table) and -RIMT (RISC-V I/O Mapping Table). - -Update the FADT revision check from 6.5 to 6.6 and remove -the TODO comment since ACPI 6.6 has been officially released. - -Signed-off-by: Yufeng Wang -Reviewed-by: Sunil V L -Acked-by: Heinrich Schuchardt -Reviewed-by: Yao Zi -Link: https://patch.msgid.link/20260305091433.83983-1-r4o5m6e8o@163.com -Signed-off-by: Paul Walmsley -(cherry picked from commit dd598449338212f9262424fa67e40b5643ab6c06) -Signed-off-by: Han Gao ---- - arch/riscv/kernel/acpi.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c -index 71698ee11621..ff681db9f4f1 100644 ---- a/arch/riscv/kernel/acpi.c -+++ b/arch/riscv/kernel/acpi.c -@@ -85,12 +85,12 @@ static int __init acpi_fadt_sanity_check(void) - * The revision in the table header is the FADT's Major revision. The - * FADT also has a minor revision, which is stored in the FADT itself. - * -- * TODO: Currently, we check for 6.5 as the minimum version to check -- * for HW_REDUCED flag. However, once RISC-V updates are released in -- * the ACPI spec, we need to update this check for exact minor revision -+ * ACPI 6.6 is required for RISC-V as it introduces RISC-V specific -+ * tables such as RHCT (RISC-V Hart Capabilities Table) and RIMT -+ * (RISC-V I/O Mapping Table). - */ -- if (table->revision < 6 || (table->revision == 6 && fadt->minor_revision < 5)) -- pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 6.5+\n", -+ if (table->revision < 6 || (table->revision == 6 && fadt->minor_revision < 6)) -+ pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 6.6+\n", - table->revision, fadt->minor_revision); - - if (!(fadt->flags & ACPI_FADT_HW_REDUCED)) { --- -2.53.0 - diff --git a/SPECS/linux-lts/0241-UPSTREAM-string-provide-strends.patch b/SPECS/linux-lts/0241-UPSTREAM-string-provide-strends.patch new file mode 100644 index 0000000000..1647db78f8 --- /dev/null +++ b/SPECS/linux-lts/0241-UPSTREAM-string-provide-strends.patch @@ -0,0 +1,79 @@ +From 94b2dc80662df98e75c5893573a98c832aa7b104 Mon Sep 17 00:00:00 2001 +From: Bartosz Golaszewski +Date: Wed, 12 Nov 2025 14:55:30 +0100 +Subject: [RUYI PATCH] UPSTREAM: string: provide strends() + +Implement a function for checking if a string ends with a different +string and add its kunit test cases. + +Acked-by: Linus Walleij +Link: https://lore.kernel.org/r/20251112-gpio-shared-v4-1-b51f97b1abd8@linaro.org +Signed-off-by: Bartosz Golaszewski +(cherry picked from commit 197b3f3c70d61ff1c7ca24f66d567e06fe8ed3d9) +Signed-off-by: Han Gao +--- + include/linux/string.h | 18 ++++++++++++++++++ + lib/tests/string_kunit.c | 13 +++++++++++++ + 2 files changed, 31 insertions(+) + +diff --git a/include/linux/string.h b/include/linux/string.h +index fdd3442c6bcb..929d05d1247c 100644 +--- a/include/linux/string.h ++++ b/include/linux/string.h +@@ -562,4 +562,22 @@ static inline bool strstarts(const char *str, const char *prefix) + return strncmp(str, prefix, strlen(prefix)) == 0; + } + ++/** ++ * strends - Check if a string ends with another string. ++ * @str - NULL-terminated string to check against @suffix ++ * @suffix - NULL-terminated string defining the suffix to look for in @str ++ * ++ * Returns: ++ * True if @str ends with @suffix. False in all other cases. ++ */ ++static inline bool strends(const char *str, const char *suffix) ++{ ++ unsigned int str_len = strlen(str), suffix_len = strlen(suffix); ++ ++ if (str_len < suffix_len) ++ return false; ++ ++ return !(strcmp(str + str_len - suffix_len, suffix)); ++} ++ + #endif /* _LINUX_STRING_H_ */ +diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c +index 0ed7448a26d3..f9a8e557ba77 100644 +--- a/lib/tests/string_kunit.c ++++ b/lib/tests/string_kunit.c +@@ -602,6 +602,18 @@ static void string_test_memtostr(struct kunit *test) + KUNIT_EXPECT_EQ(test, dest[7], '\0'); + } + ++static void string_test_strends(struct kunit *test) ++{ ++ KUNIT_EXPECT_TRUE(test, strends("foo-bar", "bar")); ++ KUNIT_EXPECT_TRUE(test, strends("foo-bar", "-bar")); ++ KUNIT_EXPECT_TRUE(test, strends("foobar", "foobar")); ++ KUNIT_EXPECT_TRUE(test, strends("foobar", "")); ++ KUNIT_EXPECT_FALSE(test, strends("bar", "foobar")); ++ KUNIT_EXPECT_FALSE(test, strends("", "foo")); ++ KUNIT_EXPECT_FALSE(test, strends("foobar", "ba")); ++ KUNIT_EXPECT_TRUE(test, strends("", "")); ++} ++ + static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_memset16), + KUNIT_CASE(string_test_memset32), +@@ -623,6 +635,7 @@ static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_strlcat), + KUNIT_CASE(string_test_strtomem), + KUNIT_CASE(string_test_memtostr), ++ KUNIT_CASE(string_test_strends), + {} + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch new file mode 100644 index 0000000000..98ac349bfa --- /dev/null +++ b/SPECS/linux-lts/0242-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -0,0 +1,91 @@ +From 79e2cd89898e36fdb3d1714bbd7988fb286c84c7 Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for + strlen() + +Add a KUnit test for strlen() to verify correctness across +different string lengths and memory alignments. Use vmalloc() +to place the NUL character at the page boundary to ensure +over-reads are detected. + +Suggested-by: Kees Cook +Signed-off-by: Feng Jiang +Reviewed-by: Kees Cook +Link: https://patch.msgid.link/20260130025018.172925-2-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit ae45f896a40a07449d9b45d0395fb7245fdd75fc) +Signed-off-by: Han Gao +--- + lib/tests/string_kunit.c | 30 ++++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c +index f9a8e557ba77..26962118768e 100644 +--- a/lib/tests/string_kunit.c ++++ b/lib/tests/string_kunit.c +@@ -6,10 +6,12 @@ + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + + #include ++#include + #include + #include + #include + #include ++#include + + #define STRCMP_LARGE_BUF_LEN 2048 + #define STRCMP_CHANGE_POINT 1337 +@@ -17,6 +19,9 @@ + #define STRCMP_TEST_EXPECT_LOWER(test, fn, ...) KUNIT_EXPECT_LT(test, fn(__VA_ARGS__), 0) + #define STRCMP_TEST_EXPECT_GREATER(test, fn, ...) KUNIT_EXPECT_GT(test, fn(__VA_ARGS__), 0) + ++#define STRING_TEST_MAX_LEN 128 ++#define STRING_TEST_MAX_OFFSET 16 ++ + static void string_test_memset16(struct kunit *test) + { + unsigned i, j, k; +@@ -104,6 +109,30 @@ static void string_test_memset64(struct kunit *test) + } + } + ++static void string_test_strlen(struct kunit *test) ++{ ++ size_t buf_size; ++ char *buf, *s; ++ ++ buf_size = PAGE_ALIGN(STRING_TEST_MAX_LEN + STRING_TEST_MAX_OFFSET + 1); ++ buf = vmalloc(buf_size); ++ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); ++ ++ memset(buf, 'A', buf_size); ++ ++ for (size_t offset = 0; offset < STRING_TEST_MAX_OFFSET; offset++) { ++ for (size_t len = 0; len <= STRING_TEST_MAX_LEN; len++) { ++ s = buf + buf_size - 1 - offset - len; ++ s[len] = '\0'; ++ KUNIT_EXPECT_EQ_MSG(test, strlen(s), len, ++ "offset:%zu len:%zu", offset, len); ++ s[len] = 'A'; ++ } ++ } ++ ++ vfree(buf); ++} ++ + static void string_test_strchr(struct kunit *test) + { + const char *test_string = "abcdefghijkl"; +@@ -618,6 +647,7 @@ static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_memset16), + KUNIT_CASE(string_test_memset32), + KUNIT_CASE(string_test_memset64), ++ KUNIT_CASE(string_test_strlen), + KUNIT_CASE(string_test_strchr), + KUNIT_CASE(string_test_strnchr), + KUNIT_CASE(string_test_strspn), +-- +2.53.0 + diff --git a/SPECS/linux-lts/0242-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch b/SPECS/linux-lts/0242-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch deleted file mode 100644 index f514478c34..0000000000 --- a/SPECS/linux-lts/0242-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch +++ /dev/null @@ -1,35 +0,0 @@ -From a0fb9210411d1e9cf24e0002bf7eab0d439012ce Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 242/467] UPSTREAM: riscv: mm: WARN_ON() for bad addresses in - vmemmap_populate() - -Similarly to the same check in arch/arm64/mm/mmu.c, in -vmemmap_populate(), add a warning for start and end being outside of the -range of vmemmap. - -Signed-off-by: Vivian Wang -Link: https://patch.msgid.link/20260309-riscv-sparsemem-vmemmap-limits-v1-1-f40efe18e3cd@iscas.ac.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit b0217d97eeeaca199eff23102b3fa72ea8c4ddea) -Signed-off-by: Han Gao ---- - arch/riscv/mm/init.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index d85efe74a4b6..a7d0cde6536b 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -1461,6 +1461,8 @@ int __meminit vmemmap_check_pmd(pmd_t *pmdp, int node, - int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, - struct vmem_altmap *altmap) - { -+ WARN_ON((start < VMEMMAP_START) || (end > VMEMMAP_END)); -+ - /* - * Note that SPARSEMEM_VMEMMAP is only selected for rv64 and that we - * can't use hugepage mappings for 2-level page table because in case of --- -2.53.0 - diff --git a/SPECS/linux-lts/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch new file mode 100644 index 0000000000..cf2e77deb8 --- /dev/null +++ b/SPECS/linux-lts/0243-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -0,0 +1,79 @@ +From 902bdb8bb0a0f55816f458cf513b52da08e503fb Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for + strnlen() + +Add a KUnit test for strnlen() to verify correctness across +different string lengths and memory alignments. Use vmalloc() +to place the NUL character at the page boundary to ensure +over-reads are detected. + +Suggested-by: Andy Shevchenko +Suggested-by: Kees Cook +Signed-off-by: Feng Jiang +Reviewed-by: Kees Cook +Link: https://patch.msgid.link/20260130025018.172925-3-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit 263dca234e5cc12aa8b434592ceb655538bf4ea4) +Signed-off-by: Han Gao +--- + lib/tests/string_kunit.c | 35 +++++++++++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c +index 26962118768e..1c2d57e05624 100644 +--- a/lib/tests/string_kunit.c ++++ b/lib/tests/string_kunit.c +@@ -133,6 +133,40 @@ static void string_test_strlen(struct kunit *test) + vfree(buf); + } + ++static void string_test_strnlen(struct kunit *test) ++{ ++ size_t buf_size; ++ char *buf, *s; ++ ++ buf_size = PAGE_ALIGN(STRING_TEST_MAX_LEN + STRING_TEST_MAX_OFFSET + 1); ++ buf = vmalloc(buf_size); ++ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); ++ ++ memset(buf, 'A', buf_size); ++ ++ for (size_t offset = 0; offset < STRING_TEST_MAX_OFFSET; offset++) { ++ for (size_t len = 0; len <= STRING_TEST_MAX_LEN; len++) { ++ s = buf + buf_size - 1 - offset - len; ++ s[len] = '\0'; ++ ++ if (len > 0) ++ KUNIT_EXPECT_EQ(test, strnlen(s, len - 1), len - 1); ++ if (len > 1) ++ KUNIT_EXPECT_EQ(test, strnlen(s, len - 2), len - 2); ++ ++ KUNIT_EXPECT_EQ(test, strnlen(s, len), len); ++ ++ KUNIT_EXPECT_EQ(test, strnlen(s, len + 1), len); ++ KUNIT_EXPECT_EQ(test, strnlen(s, len + 2), len); ++ KUNIT_EXPECT_EQ(test, strnlen(s, len + 10), len); ++ ++ s[len] = 'A'; ++ } ++ } ++ ++ vfree(buf); ++} ++ + static void string_test_strchr(struct kunit *test) + { + const char *test_string = "abcdefghijkl"; +@@ -648,6 +682,7 @@ static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_memset32), + KUNIT_CASE(string_test_memset64), + KUNIT_CASE(string_test_strlen), ++ KUNIT_CASE(string_test_strnlen), + KUNIT_CASE(string_test_strchr), + KUNIT_CASE(string_test_strnchr), + KUNIT_CASE(string_test_strspn), +-- +2.53.0 + diff --git a/SPECS/linux-lts/0243-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch b/SPECS/linux-lts/0243-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch deleted file mode 100644 index f3074ab38b..0000000000 --- a/SPECS/linux-lts/0243-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 91dae5c9d0216f41e065a75837f17dc7e99d545e Mon Sep 17 00:00:00 2001 -From: Yufeng Wang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 243/467] UPSTREAM: riscv: enable HAVE_IOREMAP_PROT - -RISC-V has implemented pte_pgprot() and selects GENERIC_IOREMAP, -which provides a generic ioremap_prot() implementation. Enable -HAVE_IOREMAP_PROT to activate generic_access_phys() support, which -is useful for debugging (e.g., accessing /dev/mem via gdb). - -Also update the architecture support documentation accordingly. - -Signed-off-by: Yufeng Wang -Link: https://patch.msgid.link/20260306112734.108186-1-r4o5m6e8o@163.com -Signed-off-by: Paul Walmsley -(cherry picked from commit d1f014012571323f3857873d94c2abf9343ef62d) -Signed-off-by: Han Gao ---- - Documentation/features/vm/ioremap_prot/arch-support.txt | 2 +- - arch/riscv/Kconfig | 1 + - 2 files changed, 2 insertions(+), 1 deletion(-) - -diff --git a/Documentation/features/vm/ioremap_prot/arch-support.txt b/Documentation/features/vm/ioremap_prot/arch-support.txt -index 1638c2cb17f1..c0a2d8f56046 100644 ---- a/Documentation/features/vm/ioremap_prot/arch-support.txt -+++ b/Documentation/features/vm/ioremap_prot/arch-support.txt -@@ -20,7 +20,7 @@ - | openrisc: | TODO | - | parisc: | TODO | - | powerpc: | ok | -- | riscv: | TODO | -+ | riscv: | ok | - | s390: | ok | - | sh: | ok | - | sparc: | TODO | -diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index fadec20b87a8..9c43346fabcd 100644 ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -113,6 +113,7 @@ config RISCV - select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO && 64BIT - select GENERIC_IDLE_POLL_SETUP - select GENERIC_IOREMAP if MMU -+ select HAVE_IOREMAP_PROT if MMU - select GENERIC_IRQ_IPI if SMP - select GENERIC_IRQ_IPI_MUX if SMP - select GENERIC_IRQ_MULTI_HANDLER --- -2.53.0 - diff --git a/SPECS/linux-lts/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch new file mode 100644 index 0000000000..b303a23ddc --- /dev/null +++ b/SPECS/linux-lts/0244-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -0,0 +1,74 @@ +From a35e09fa31b7cc0d163e681b2acef99edf7f626b Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for + strrchr() + +Add a KUnit test for strrchr() to verify correctness across +different string lengths and memory alignments. Use vmalloc() +to place the NUL character at the page boundary to ensure +over-reads are detected. + +Suggested-by: Kees Cook +Signed-off-by: Feng Jiang +Reviewed-by: Kees Cook +Link: https://patch.msgid.link/20260130025018.172925-4-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit 27b2810a4a3dcd1545ec8bafc82f967eda591c47) +Signed-off-by: Han Gao +--- + lib/tests/string_kunit.c | 31 +++++++++++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c +index 1c2d57e05624..2bed641e1eae 100644 +--- a/lib/tests/string_kunit.c ++++ b/lib/tests/string_kunit.c +@@ -190,6 +190,36 @@ static void string_test_strchr(struct kunit *test) + KUNIT_ASSERT_NULL(test, result); + } + ++static void string_test_strrchr(struct kunit *test) ++{ ++ size_t buf_size; ++ char *buf, *s; ++ ++ buf_size = PAGE_ALIGN(STRING_TEST_MAX_LEN + STRING_TEST_MAX_OFFSET + 1); ++ buf = vmalloc(buf_size); ++ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); ++ ++ memset(buf, 'A', buf_size); ++ ++ for (size_t offset = 0; offset < STRING_TEST_MAX_OFFSET; offset++) { ++ for (size_t len = 0; len <= STRING_TEST_MAX_LEN; len++) { ++ s = buf + buf_size - 1 - offset - len; ++ s[len] = '\0'; ++ ++ KUNIT_EXPECT_PTR_EQ(test, strrchr(s, 'Z'), NULL); ++ ++ if (len > 0) ++ KUNIT_EXPECT_PTR_EQ(test, strrchr(s, 'A'), s + len - 1); ++ else ++ KUNIT_EXPECT_PTR_EQ(test, strrchr(s, 'A'), NULL); ++ ++ s[len] = 'A'; ++ } ++ } ++ ++ vfree(buf); ++} ++ + static void string_test_strnchr(struct kunit *test) + { + const char *test_string = "abcdefghijkl"; +@@ -685,6 +715,7 @@ static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_strnlen), + KUNIT_CASE(string_test_strchr), + KUNIT_CASE(string_test_strnchr), ++ KUNIT_CASE(string_test_strrchr), + KUNIT_CASE(string_test_strspn), + KUNIT_CASE(string_test_strcmp), + KUNIT_CASE(string_test_strcmp_long_strings), +-- +2.53.0 + diff --git a/SPECS/linux-lts/0244-UPSTREAM-string-provide-strends.patch b/SPECS/linux-lts/0244-UPSTREAM-string-provide-strends.patch deleted file mode 100644 index a94ffb8092..0000000000 --- a/SPECS/linux-lts/0244-UPSTREAM-string-provide-strends.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 51707af489a55246eec9dc64f9b85831e0fd4706 Mon Sep 17 00:00:00 2001 -From: Bartosz Golaszewski -Date: Wed, 12 Nov 2025 14:55:30 +0100 -Subject: [PATCH 244/467] UPSTREAM: string: provide strends() - -Implement a function for checking if a string ends with a different -string and add its kunit test cases. - -Acked-by: Linus Walleij -Link: https://lore.kernel.org/r/20251112-gpio-shared-v4-1-b51f97b1abd8@linaro.org -Signed-off-by: Bartosz Golaszewski -(cherry picked from commit 197b3f3c70d61ff1c7ca24f66d567e06fe8ed3d9) -Signed-off-by: Han Gao ---- - include/linux/string.h | 18 ++++++++++++++++++ - lib/tests/string_kunit.c | 13 +++++++++++++ - 2 files changed, 31 insertions(+) - -diff --git a/include/linux/string.h b/include/linux/string.h -index fdd3442c6bcb..929d05d1247c 100644 ---- a/include/linux/string.h -+++ b/include/linux/string.h -@@ -562,4 +562,22 @@ static inline bool strstarts(const char *str, const char *prefix) - return strncmp(str, prefix, strlen(prefix)) == 0; - } - -+/** -+ * strends - Check if a string ends with another string. -+ * @str - NULL-terminated string to check against @suffix -+ * @suffix - NULL-terminated string defining the suffix to look for in @str -+ * -+ * Returns: -+ * True if @str ends with @suffix. False in all other cases. -+ */ -+static inline bool strends(const char *str, const char *suffix) -+{ -+ unsigned int str_len = strlen(str), suffix_len = strlen(suffix); -+ -+ if (str_len < suffix_len) -+ return false; -+ -+ return !(strcmp(str + str_len - suffix_len, suffix)); -+} -+ - #endif /* _LINUX_STRING_H_ */ -diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c -index 0ed7448a26d3..f9a8e557ba77 100644 ---- a/lib/tests/string_kunit.c -+++ b/lib/tests/string_kunit.c -@@ -602,6 +602,18 @@ static void string_test_memtostr(struct kunit *test) - KUNIT_EXPECT_EQ(test, dest[7], '\0'); - } - -+static void string_test_strends(struct kunit *test) -+{ -+ KUNIT_EXPECT_TRUE(test, strends("foo-bar", "bar")); -+ KUNIT_EXPECT_TRUE(test, strends("foo-bar", "-bar")); -+ KUNIT_EXPECT_TRUE(test, strends("foobar", "foobar")); -+ KUNIT_EXPECT_TRUE(test, strends("foobar", "")); -+ KUNIT_EXPECT_FALSE(test, strends("bar", "foobar")); -+ KUNIT_EXPECT_FALSE(test, strends("", "foo")); -+ KUNIT_EXPECT_FALSE(test, strends("foobar", "ba")); -+ KUNIT_EXPECT_TRUE(test, strends("", "")); -+} -+ - static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_memset16), - KUNIT_CASE(string_test_memset32), -@@ -623,6 +635,7 @@ static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_strlcat), - KUNIT_CASE(string_test_strtomem), - KUNIT_CASE(string_test_memtostr), -+ KUNIT_CASE(string_test_strends), - {} - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0245-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts/0245-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch deleted file mode 100644 index 97e4def775..0000000000 --- a/SPECS/linux-lts/0245-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ /dev/null @@ -1,91 +0,0 @@ -From a0ea3d9866b712d229e263440d46912dd67c4437 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 245/467] UPSTREAM: lib/string_kunit: add correctness test for - strlen() - -Add a KUnit test for strlen() to verify correctness across -different string lengths and memory alignments. Use vmalloc() -to place the NUL character at the page boundary to ensure -over-reads are detected. - -Suggested-by: Kees Cook -Signed-off-by: Feng Jiang -Reviewed-by: Kees Cook -Link: https://patch.msgid.link/20260130025018.172925-2-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit ae45f896a40a07449d9b45d0395fb7245fdd75fc) -Signed-off-by: Han Gao ---- - lib/tests/string_kunit.c | 30 ++++++++++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - -diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c -index f9a8e557ba77..26962118768e 100644 ---- a/lib/tests/string_kunit.c -+++ b/lib/tests/string_kunit.c -@@ -6,10 +6,12 @@ - #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - - #include -+#include - #include - #include - #include - #include -+#include - - #define STRCMP_LARGE_BUF_LEN 2048 - #define STRCMP_CHANGE_POINT 1337 -@@ -17,6 +19,9 @@ - #define STRCMP_TEST_EXPECT_LOWER(test, fn, ...) KUNIT_EXPECT_LT(test, fn(__VA_ARGS__), 0) - #define STRCMP_TEST_EXPECT_GREATER(test, fn, ...) KUNIT_EXPECT_GT(test, fn(__VA_ARGS__), 0) - -+#define STRING_TEST_MAX_LEN 128 -+#define STRING_TEST_MAX_OFFSET 16 -+ - static void string_test_memset16(struct kunit *test) - { - unsigned i, j, k; -@@ -104,6 +109,30 @@ static void string_test_memset64(struct kunit *test) - } - } - -+static void string_test_strlen(struct kunit *test) -+{ -+ size_t buf_size; -+ char *buf, *s; -+ -+ buf_size = PAGE_ALIGN(STRING_TEST_MAX_LEN + STRING_TEST_MAX_OFFSET + 1); -+ buf = vmalloc(buf_size); -+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); -+ -+ memset(buf, 'A', buf_size); -+ -+ for (size_t offset = 0; offset < STRING_TEST_MAX_OFFSET; offset++) { -+ for (size_t len = 0; len <= STRING_TEST_MAX_LEN; len++) { -+ s = buf + buf_size - 1 - offset - len; -+ s[len] = '\0'; -+ KUNIT_EXPECT_EQ_MSG(test, strlen(s), len, -+ "offset:%zu len:%zu", offset, len); -+ s[len] = 'A'; -+ } -+ } -+ -+ vfree(buf); -+} -+ - static void string_test_strchr(struct kunit *test) - { - const char *test_string = "abcdefghijkl"; -@@ -618,6 +647,7 @@ static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_memset16), - KUNIT_CASE(string_test_memset32), - KUNIT_CASE(string_test_memset64), -+ KUNIT_CASE(string_test_strlen), - KUNIT_CASE(string_test_strchr), - KUNIT_CASE(string_test_strnchr), - KUNIT_CASE(string_test_strspn), --- -2.53.0 - diff --git a/SPECS/linux-lts/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch b/SPECS/linux-lts/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch new file mode 100644 index 0000000000..8ed6b57c83 --- /dev/null +++ b/SPECS/linux-lts/0245-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch @@ -0,0 +1,256 @@ +From 3157c725cd7a5774a6e772aee7c537b7bc65a90e Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add performance benchmark + for strlen() + +Introduce a benchmarking framework to the string_kunit test suite to +measure the execution efficiency of string functions. + +The implementation is inspired by crc_benchmark(), measuring throughput +(MB/s) and latency (ns/call) across a range of string lengths. It +includes a warm-up phase, disables preemption during measurement, and +uses a fixed seed for reproducible results. + +This framework allows for comparing different implementations (e.g., +generic C vs. architecture-optimized assembly) within the KUnit +environment. + +Initially, provide a benchmark for strlen(). + +Suggested-by: Andy Shevchenko +Suggested-by: Eric Biggers +Signed-off-by: Feng Jiang +Reviewed-by: Kees Cook +Link: https://patch.msgid.link/20260130025018.172925-5-jiangfeng@kylinos.cn +[pjw@kernel.org: fixed a checkpatch issue] +Signed-off-by: Paul Walmsley +(cherry picked from commit 0020240a431187628e2636284023e63b9b7a2aa1) +Signed-off-by: Han Gao +--- + lib/Kconfig.debug | 11 +++ + lib/tests/string_kunit.c | 160 +++++++++++++++++++++++++++++++++++++++ + 2 files changed, 171 insertions(+) + +diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug +index 21cd68084e46..a4d1ce2f4600 100644 +--- a/lib/Kconfig.debug ++++ b/lib/Kconfig.debug +@@ -2446,6 +2446,17 @@ config STRING_HELPERS_KUNIT_TEST + depends on KUNIT + default KUNIT_ALL_TESTS + ++config STRING_KUNIT_BENCH ++ bool "Benchmark string functions at runtime" ++ depends on STRING_KUNIT_TEST ++ help ++ Enable performance measurement for string functions. ++ ++ This measures the execution efficiency of string functions ++ during the KUnit test run. ++ ++ If unsure, say N. ++ + config FFS_KUNIT_TEST + tristate "KUnit test ffs-family functions at runtime" if !KUNIT_ALL_TESTS + depends on KUNIT +diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c +index 2bed641e1eae..cd5837373427 100644 +--- a/lib/tests/string_kunit.c ++++ b/lib/tests/string_kunit.c +@@ -6,11 +6,17 @@ + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + + #include ++#include ++#include ++#include + #include + #include ++#include + #include + #include + #include ++#include ++#include + #include + + #define STRCMP_LARGE_BUF_LEN 2048 +@@ -22,6 +28,9 @@ + #define STRING_TEST_MAX_LEN 128 + #define STRING_TEST_MAX_OFFSET 16 + ++#define STRING_BENCH_SEED 888 ++#define STRING_BENCH_WORKLOAD (1 * MEGA) ++ + static void string_test_memset16(struct kunit *test) + { + unsigned i, j, k; +@@ -707,6 +716,156 @@ static void string_test_strends(struct kunit *test) + KUNIT_EXPECT_TRUE(test, strends("", "")); + } + ++#if IS_ENABLED(CONFIG_STRING_KUNIT_BENCH) ++/* Target string lengths for benchmarking */ ++static const size_t bench_lens[] = { ++ 0, 1, 7, 8, 16, 31, 64, 127, 512, 1024, 3173, 4096, ++}; ++ ++/** ++ * alloc_max_bench_buffer() - Allocate buffer for the max test case. ++ * @test: KUnit context for managed allocation. ++ * @lens: Array of lengths used in the benchmark cases. ++ * @count: Number of elements in the @lens array. ++ * @buf_len: [out] Pointer to store the actually allocated buffer ++ * size (including NUL character). ++ * ++ * Return: Pointer to the allocated memory, or NULL on failure. ++ */ ++static void *alloc_max_bench_buffer(struct kunit *test, const size_t *lens, ++ size_t count, size_t *buf_len) ++{ ++ size_t max_len = 0; ++ void *buf; ++ ++ for (size_t i = 0; i < count; i++) ++ max_len = max(lens[i], max_len); ++ ++ /* Add space for NUL character */ ++ max_len += 1; ++ ++ buf = kunit_kzalloc(test, max_len, GFP_KERNEL); ++ if (!buf) ++ return NULL; ++ ++ if (buf_len) ++ *buf_len = max_len; ++ ++ return buf; ++} ++ ++/** ++ * fill_random_string() - Populate a buffer with a random NUL-terminated string. ++ * @buf: Buffer to fill. ++ * @len: Length of the buffer in bytes. ++ * ++ * Fills the buffer with random non-NUL bytes and ensures the string is ++ * properly NUL-terminated. ++ */ ++static void fill_random_string(char *buf, size_t len) ++{ ++ struct rnd_state state; ++ ++ if (!buf || !len) ++ return; ++ ++ /* Use a fixed seed to ensure deterministic benchmark results */ ++ prandom_seed_state(&state, STRING_BENCH_SEED); ++ prandom_bytes_state(&state, buf, len); ++ ++ /* Replace NUL characters to avoid early string termination */ ++ for (size_t i = 0; i < len; i++) { ++ if (buf[i] == '\0') ++ buf[i] = 0x01; ++ } ++ ++ buf[len - 1] = '\0'; ++} ++ ++/** ++ * STRING_BENCH() - Benchmark string functions. ++ * @iters: Number of iterations to run. ++ * @func: Function to benchmark. ++ * @...: Variable arguments passed to @func. ++ * ++ * Disables preemption and measures the total time in nanoseconds to execute ++ * @func(@__VA_ARGS__) for @iters times, including a small warm-up phase. ++ * ++ * Context: Disables preemption during measurement. ++ * Return: Total execution time in nanoseconds (u64). ++ */ ++#define STRING_BENCH(iters, func, ...) \ ++({ \ ++ /* Volatile function pointer prevents dead code elimination */ \ ++ typeof(func) (* volatile __func) = (func); \ ++ size_t __bn_iters = (iters); \ ++ size_t __bn_warm_iters; \ ++ u64 __bn_t; \ ++ \ ++ /* Use 10% of the given iterations (maximum 50) to warm up */ \ ++ __bn_warm_iters = max(__bn_iters / 10, 50U); \ ++ \ ++ for (size_t __bn_i = 0; __bn_i < __bn_warm_iters; __bn_i++) \ ++ (void)__func(__VA_ARGS__); \ ++ \ ++ preempt_disable(); \ ++ __bn_t = ktime_get_ns(); \ ++ for (size_t __bn_i = 0; __bn_i < __bn_iters; __bn_i++) \ ++ (void)__func(__VA_ARGS__); \ ++ __bn_t = ktime_get_ns() - __bn_t; \ ++ preempt_enable(); \ ++ __bn_t; \ ++}) ++ ++/** ++ * STRING_BENCH_BUF() - Benchmark harness for single-buffer functions. ++ * @test: KUnit context. ++ * @buf_name: Local char * variable name to be defined. ++ * @buf_size: Local size_t variable name to be defined. ++ * @func: Function to benchmark. ++ * @...: Extra arguments for @func. ++ * ++ * Prepares a randomized, NUL-terminated buffer and iterates through lengths ++ * in bench_lens, defining @buf_name and @buf_size in each loop. ++ */ ++#define STRING_BENCH_BUF(test, buf_name, buf_size, func, ...) \ ++do { \ ++ size_t _bn_i, _bn_iters, _bn_size = 0; \ ++ u64 _bn_t, _bn_mbps = 0, _bn_lat = 0; \ ++ char *_bn_buf; \ ++ \ ++ _bn_buf = alloc_max_bench_buffer(test, bench_lens, \ ++ ARRAY_SIZE(bench_lens), &_bn_size); \ ++ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, _bn_buf); \ ++ \ ++ fill_random_string(_bn_buf, _bn_size); \ ++ \ ++ for (_bn_i = 0; _bn_i < ARRAY_SIZE(bench_lens); _bn_i++) { \ ++ size_t buf_size = bench_lens[_bn_i]; \ ++ char *buf_name = _bn_buf + _bn_size - buf_size - 1; \ ++ _bn_iters = STRING_BENCH_WORKLOAD / max(buf_size, 1U); \ ++ \ ++ _bn_t = STRING_BENCH(_bn_iters, func, ##__VA_ARGS__); \ ++ if (_bn_t > 0) { \ ++ _bn_mbps = (u64)(buf_size) * _bn_iters * \ ++ (NSEC_PER_SEC / MEGA); \ ++ _bn_mbps = div64_u64(_bn_mbps, _bn_t); \ ++ _bn_lat = div64_u64(_bn_t, _bn_iters); \ ++ } \ ++ kunit_info(test, "len=%zu: %llu MB/s (%llu ns/call)\n", \ ++ buf_size, _bn_mbps, _bn_lat); \ ++ } \ ++} while (0) ++#else ++#define STRING_BENCH_BUF(test, buf_name, buf_size, func, ...) \ ++ kunit_skip(test, "not enabled") ++#endif /* IS_ENABLED(CONFIG_STRING_KUNIT_BENCH) */ ++ ++static void string_bench_strlen(struct kunit *test) ++{ ++ STRING_BENCH_BUF(test, buf, len, strlen, buf); ++} ++ + static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_memset16), + KUNIT_CASE(string_test_memset32), +@@ -732,6 +891,7 @@ static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_strtomem), + KUNIT_CASE(string_test_memtostr), + KUNIT_CASE(string_test_strends), ++ KUNIT_CASE(string_bench_strlen), + {} + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0246-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts/0246-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch deleted file mode 100644 index b070b96048..0000000000 --- a/SPECS/linux-lts/0246-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 7d205ff17788553db4370fc8017670aeff19fe77 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 246/467] UPSTREAM: lib/string_kunit: add correctness test for - strnlen() - -Add a KUnit test for strnlen() to verify correctness across -different string lengths and memory alignments. Use vmalloc() -to place the NUL character at the page boundary to ensure -over-reads are detected. - -Suggested-by: Andy Shevchenko -Suggested-by: Kees Cook -Signed-off-by: Feng Jiang -Reviewed-by: Kees Cook -Link: https://patch.msgid.link/20260130025018.172925-3-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit 263dca234e5cc12aa8b434592ceb655538bf4ea4) -Signed-off-by: Han Gao ---- - lib/tests/string_kunit.c | 35 +++++++++++++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - -diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c -index 26962118768e..1c2d57e05624 100644 ---- a/lib/tests/string_kunit.c -+++ b/lib/tests/string_kunit.c -@@ -133,6 +133,40 @@ static void string_test_strlen(struct kunit *test) - vfree(buf); - } - -+static void string_test_strnlen(struct kunit *test) -+{ -+ size_t buf_size; -+ char *buf, *s; -+ -+ buf_size = PAGE_ALIGN(STRING_TEST_MAX_LEN + STRING_TEST_MAX_OFFSET + 1); -+ buf = vmalloc(buf_size); -+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); -+ -+ memset(buf, 'A', buf_size); -+ -+ for (size_t offset = 0; offset < STRING_TEST_MAX_OFFSET; offset++) { -+ for (size_t len = 0; len <= STRING_TEST_MAX_LEN; len++) { -+ s = buf + buf_size - 1 - offset - len; -+ s[len] = '\0'; -+ -+ if (len > 0) -+ KUNIT_EXPECT_EQ(test, strnlen(s, len - 1), len - 1); -+ if (len > 1) -+ KUNIT_EXPECT_EQ(test, strnlen(s, len - 2), len - 2); -+ -+ KUNIT_EXPECT_EQ(test, strnlen(s, len), len); -+ -+ KUNIT_EXPECT_EQ(test, strnlen(s, len + 1), len); -+ KUNIT_EXPECT_EQ(test, strnlen(s, len + 2), len); -+ KUNIT_EXPECT_EQ(test, strnlen(s, len + 10), len); -+ -+ s[len] = 'A'; -+ } -+ } -+ -+ vfree(buf); -+} -+ - static void string_test_strchr(struct kunit *test) - { - const char *test_string = "abcdefghijkl"; -@@ -648,6 +682,7 @@ static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_memset32), - KUNIT_CASE(string_test_memset64), - KUNIT_CASE(string_test_strlen), -+ KUNIT_CASE(string_test_strnlen), - KUNIT_CASE(string_test_strchr), - KUNIT_CASE(string_test_strnchr), - KUNIT_CASE(string_test_strspn), --- -2.53.0 - diff --git a/SPECS/linux-lts/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch b/SPECS/linux-lts/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch new file mode 100644 index 0000000000..8a4b47a942 --- /dev/null +++ b/SPECS/linux-lts/0246-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch @@ -0,0 +1,66 @@ +From d4f3b19d0ba9850b6052f6adfda81bdd61650371 Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: extend benchmarks to + strnlen() and chr searches + +Extend the string benchmarking suite to include strnlen(), strchr(), +and strrchr(). + +For character search functions strchr() and strrchr(), the benchmark +targets the NUL character. This ensures the entire string is scanned, +providing a consistent measure of full-length processing efficiency +comparable to strlen(). + +Suggested-by: Andy Shevchenko +Suggested-by: Eric Biggers +Signed-off-by: Feng Jiang +Acked-by: Andy Shevchenko +Reviewed-by: Kees Cook +Link: https://patch.msgid.link/20260130025018.172925-6-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit e73bcb3708a69369d506e5bc6a63d4fc13d8e28a) +Signed-off-by: Han Gao +--- + lib/tests/string_kunit.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c +index cd5837373427..0819ace5b027 100644 +--- a/lib/tests/string_kunit.c ++++ b/lib/tests/string_kunit.c +@@ -866,6 +866,21 @@ static void string_bench_strlen(struct kunit *test) + STRING_BENCH_BUF(test, buf, len, strlen, buf); + } + ++static void string_bench_strnlen(struct kunit *test) ++{ ++ STRING_BENCH_BUF(test, buf, len, strnlen, buf, len); ++} ++ ++static void string_bench_strchr(struct kunit *test) ++{ ++ STRING_BENCH_BUF(test, buf, len, strchr, buf, '\0'); ++} ++ ++static void string_bench_strrchr(struct kunit *test) ++{ ++ STRING_BENCH_BUF(test, buf, len, strrchr, buf, '\0'); ++} ++ + static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_memset16), + KUNIT_CASE(string_test_memset32), +@@ -892,6 +907,9 @@ static struct kunit_case string_test_cases[] = { + KUNIT_CASE(string_test_memtostr), + KUNIT_CASE(string_test_strends), + KUNIT_CASE(string_bench_strlen), ++ KUNIT_CASE(string_bench_strnlen), ++ KUNIT_CASE(string_bench_strchr), ++ KUNIT_CASE(string_bench_strrchr), + {} + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0247-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux-lts/0247-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch deleted file mode 100644 index ce8b0f8a5b..0000000000 --- a/SPECS/linux-lts/0247-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 0a17629f949ff3604a42f6cbe6c0609a51050633 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 247/467] UPSTREAM: lib/string_kunit: add correctness test for - strrchr() - -Add a KUnit test for strrchr() to verify correctness across -different string lengths and memory alignments. Use vmalloc() -to place the NUL character at the page boundary to ensure -over-reads are detected. - -Suggested-by: Kees Cook -Signed-off-by: Feng Jiang -Reviewed-by: Kees Cook -Link: https://patch.msgid.link/20260130025018.172925-4-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit 27b2810a4a3dcd1545ec8bafc82f967eda591c47) -Signed-off-by: Han Gao ---- - lib/tests/string_kunit.c | 31 +++++++++++++++++++++++++++++++ - 1 file changed, 31 insertions(+) - -diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c -index 1c2d57e05624..2bed641e1eae 100644 ---- a/lib/tests/string_kunit.c -+++ b/lib/tests/string_kunit.c -@@ -190,6 +190,36 @@ static void string_test_strchr(struct kunit *test) - KUNIT_ASSERT_NULL(test, result); - } - -+static void string_test_strrchr(struct kunit *test) -+{ -+ size_t buf_size; -+ char *buf, *s; -+ -+ buf_size = PAGE_ALIGN(STRING_TEST_MAX_LEN + STRING_TEST_MAX_OFFSET + 1); -+ buf = vmalloc(buf_size); -+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); -+ -+ memset(buf, 'A', buf_size); -+ -+ for (size_t offset = 0; offset < STRING_TEST_MAX_OFFSET; offset++) { -+ for (size_t len = 0; len <= STRING_TEST_MAX_LEN; len++) { -+ s = buf + buf_size - 1 - offset - len; -+ s[len] = '\0'; -+ -+ KUNIT_EXPECT_PTR_EQ(test, strrchr(s, 'Z'), NULL); -+ -+ if (len > 0) -+ KUNIT_EXPECT_PTR_EQ(test, strrchr(s, 'A'), s + len - 1); -+ else -+ KUNIT_EXPECT_PTR_EQ(test, strrchr(s, 'A'), NULL); -+ -+ s[len] = 'A'; -+ } -+ } -+ -+ vfree(buf); -+} -+ - static void string_test_strnchr(struct kunit *test) - { - const char *test_string = "abcdefghijkl"; -@@ -685,6 +715,7 @@ static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_strnlen), - KUNIT_CASE(string_test_strchr), - KUNIT_CASE(string_test_strnchr), -+ KUNIT_CASE(string_test_strrchr), - KUNIT_CASE(string_test_strspn), - KUNIT_CASE(string_test_strcmp), - KUNIT_CASE(string_test_strcmp_long_strings), --- -2.53.0 - diff --git a/SPECS/linux-lts/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch b/SPECS/linux-lts/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch new file mode 100644 index 0000000000..da2b0c30de --- /dev/null +++ b/SPECS/linux-lts/0247-UPSTREAM-riscv-lib-add-strnlen-implementation.patch @@ -0,0 +1,252 @@ +From d7fce76a1ce208fab598335c38ae8071bb4d893d Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strnlen() implementation + +Add an optimized strnlen() implementation for RISC-V. This version +includes a generic optimization and a Zbb-powered optimization using +the 'orc.b' instruction, derived from the strlen() implementation. + +Benchmark results (QEMU TCG, rv64): + Length | Original (MB/s) | Optimized (MB/s) | Improvement + -------|-----------------|------------------|------------ + 16 B | 179 | 309 | +72.6% + 512 B | 347 | 1562 | +350.1% + 4096 B | 356 | 1878 | +427.5% + +Suggested-by: Qingfang Deng +Signed-off-by: Feng Jiang +Link: https://patch.msgid.link/20260130025018.172925-7-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit 5ba15d419fab848a3813eb56bbcad00e291fbc49) +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/string.h | 3 + + arch/riscv/lib/Makefile | 1 + + arch/riscv/lib/strnlen.S | 164 ++++++++++++++++++++++++++++++++ + arch/riscv/purgatory/Makefile | 5 +- + 4 files changed, 172 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/lib/strnlen.S + +diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h +index 5ba77f60bf0b..16634d67c217 100644 +--- a/arch/riscv/include/asm/string.h ++++ b/arch/riscv/include/asm/string.h +@@ -28,6 +28,9 @@ extern asmlinkage __kernel_size_t strlen(const char *); + + #define __HAVE_ARCH_STRNCMP + extern asmlinkage int strncmp(const char *cs, const char *ct, size_t count); ++ ++#define __HAVE_ARCH_STRNLEN ++extern asmlinkage __kernel_size_t strnlen(const char *, size_t); + #endif + + /* For those files which don't want to check by kasan. */ +diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile +index bbc031124974..0969d8136df0 100644 +--- a/arch/riscv/lib/Makefile ++++ b/arch/riscv/lib/Makefile +@@ -7,6 +7,7 @@ ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) + lib-y += strcmp.o + lib-y += strlen.o + lib-y += strncmp.o ++lib-y += strnlen.o + endif + lib-y += csum.o + ifeq ($(CONFIG_MMU), y) +diff --git a/arch/riscv/lib/strnlen.S b/arch/riscv/lib/strnlen.S +new file mode 100644 +index 000000000000..53afa7b5b314 +--- /dev/null ++++ b/arch/riscv/lib/strnlen.S +@@ -0,0 +1,164 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* ++ * Base on arch/riscv/lib/strlen.S ++ * ++ * Copyright (C) Feng Jiang ++ */ ++ ++#include ++#include ++#include ++#include ++ ++/* size_t strnlen(const char *s, size_t count) */ ++SYM_FUNC_START(strnlen) ++ ++ __ALTERNATIVE_CFG("nop", "j strnlen_zbb", 0, RISCV_ISA_EXT_ZBB, ++ IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) ++ ++ ++ /* ++ * Returns ++ * a0 - String length ++ * ++ * Parameters ++ * a0 - String to measure ++ * a1 - Max length of string ++ * ++ * Clobbers ++ * t0, t1, t2 ++ */ ++ addi t1, a0, -1 ++ add t2, a0, a1 ++1: ++ addi t1, t1, 1 ++ beq t1, t2, 2f ++ lbu t0, 0(t1) ++ bnez t0, 1b ++2: ++ sub a0, t1, a0 ++ ret ++ ++ ++/* ++ * Variant of strnlen using the ZBB extension if available ++ */ ++#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) ++strnlen_zbb: ++ ++#ifdef CONFIG_CPU_BIG_ENDIAN ++# define CZ clz ++# define SHIFT sll ++#else ++# define CZ ctz ++# define SHIFT srl ++#endif ++ ++.option push ++.option arch,+zbb ++ ++ /* ++ * Returns ++ * a0 - String length ++ * ++ * Parameters ++ * a0 - String to measure ++ * a1 - Max length of string ++ * ++ * Clobbers ++ * t0, t1, t2, t3, t4 ++ */ ++ ++ /* If maxlen is 0, return 0. */ ++ beqz a1, 3f ++ ++ /* Number of irrelevant bytes in the first word. */ ++ andi t2, a0, SZREG-1 ++ ++ /* Align pointer. */ ++ andi t0, a0, -SZREG ++ ++ li t3, SZREG ++ sub t3, t3, t2 ++ slli t2, t2, 3 ++ ++ /* Aligned boundary. */ ++ add t4, a0, a1 ++ andi t4, t4, -SZREG ++ ++ /* Get the first word. */ ++ REG_L t1, 0(t0) ++ ++ /* ++ * Shift away the partial data we loaded to remove the irrelevant bytes ++ * preceding the string with the effect of adding NUL bytes at the ++ * end of the string's first word. ++ */ ++ SHIFT t1, t1, t2 ++ ++ /* Convert non-NUL into 0xff and NUL into 0x00. */ ++ orc.b t1, t1 ++ ++ /* Convert non-NUL into 0x00 and NUL into 0xff. */ ++ not t1, t1 ++ ++ /* ++ * Search for the first set bit (corresponding to a NUL byte in the ++ * original chunk). ++ */ ++ CZ t1, t1 ++ ++ /* ++ * The first chunk is special: compare against the number ++ * of valid bytes in this chunk. ++ */ ++ srli a0, t1, 3 ++ ++ /* Limit the result by maxlen. */ ++ minu a0, a0, a1 ++ ++ bgtu t3, a0, 2f ++ ++ /* Prepare for the word comparison loop. */ ++ addi t2, t0, SZREG ++ li t3, -1 ++ ++ /* ++ * Our critical loop is 4 instructions and processes data in ++ * 4 byte or 8 byte chunks. ++ */ ++ .p2align 3 ++1: ++ REG_L t1, SZREG(t0) ++ addi t0, t0, SZREG ++ orc.b t1, t1 ++ bgeu t0, t4, 4f ++ beq t1, t3, 1b ++4: ++ not t1, t1 ++ CZ t1, t1 ++ srli t1, t1, 3 ++ ++ /* Get number of processed bytes. */ ++ sub t2, t0, t2 ++ ++ /* Add number of characters in the first word. */ ++ add a0, a0, t2 ++ ++ /* Add number of characters in the last word. */ ++ add a0, a0, t1 ++ ++ /* Ensure the final result does not exceed maxlen. */ ++ minu a0, a0, a1 ++2: ++ ret ++3: ++ mv a0, a1 ++ ret ++ ++.option pop ++#endif ++SYM_FUNC_END(strnlen) ++SYM_FUNC_ALIAS(__pi_strnlen, strnlen) ++EXPORT_SYMBOL(strnlen) +diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile +index 530e497ca2f9..d7c0533108be 100644 +--- a/arch/riscv/purgatory/Makefile ++++ b/arch/riscv/purgatory/Makefile +@@ -2,7 +2,7 @@ + + purgatory-y := purgatory.o sha256.o entry.o string.o ctype.o memcpy.o memset.o + ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) +-purgatory-y += strcmp.o strlen.o strncmp.o ++purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o + endif + + targets += $(purgatory-y) +@@ -32,6 +32,9 @@ $(obj)/strncmp.o: $(srctree)/arch/riscv/lib/strncmp.S FORCE + $(obj)/sha256.o: $(srctree)/lib/crypto/sha256.c FORCE + $(call if_changed_rule,cc_o_c) + ++$(obj)/strnlen.o: $(srctree)/arch/riscv/lib/strnlen.S FORCE ++ $(call if_changed_rule,as_o_S) ++ + CFLAGS_sha256.o := -D__DISABLE_EXPORTS -D__NO_FORTIFY + CFLAGS_string.o := -D__DISABLE_EXPORTS + CFLAGS_ctype.o := -D__DISABLE_EXPORTS +-- +2.53.0 + diff --git a/SPECS/linux-lts/0248-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch b/SPECS/linux-lts/0248-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch deleted file mode 100644 index 52ac6d1a18..0000000000 --- a/SPECS/linux-lts/0248-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch +++ /dev/null @@ -1,256 +0,0 @@ -From 1b38e17c75d77d3173ec154a74233c0c19c8f8f1 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 248/467] UPSTREAM: lib/string_kunit: add performance benchmark - for strlen() - -Introduce a benchmarking framework to the string_kunit test suite to -measure the execution efficiency of string functions. - -The implementation is inspired by crc_benchmark(), measuring throughput -(MB/s) and latency (ns/call) across a range of string lengths. It -includes a warm-up phase, disables preemption during measurement, and -uses a fixed seed for reproducible results. - -This framework allows for comparing different implementations (e.g., -generic C vs. architecture-optimized assembly) within the KUnit -environment. - -Initially, provide a benchmark for strlen(). - -Suggested-by: Andy Shevchenko -Suggested-by: Eric Biggers -Signed-off-by: Feng Jiang -Reviewed-by: Kees Cook -Link: https://patch.msgid.link/20260130025018.172925-5-jiangfeng@kylinos.cn -[pjw@kernel.org: fixed a checkpatch issue] -Signed-off-by: Paul Walmsley -(cherry picked from commit 0020240a431187628e2636284023e63b9b7a2aa1) -Signed-off-by: Han Gao ---- - lib/Kconfig.debug | 11 +++ - lib/tests/string_kunit.c | 160 +++++++++++++++++++++++++++++++++++++++ - 2 files changed, 171 insertions(+) - -diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug -index 21cd68084e46..a4d1ce2f4600 100644 ---- a/lib/Kconfig.debug -+++ b/lib/Kconfig.debug -@@ -2446,6 +2446,17 @@ config STRING_HELPERS_KUNIT_TEST - depends on KUNIT - default KUNIT_ALL_TESTS - -+config STRING_KUNIT_BENCH -+ bool "Benchmark string functions at runtime" -+ depends on STRING_KUNIT_TEST -+ help -+ Enable performance measurement for string functions. -+ -+ This measures the execution efficiency of string functions -+ during the KUnit test run. -+ -+ If unsure, say N. -+ - config FFS_KUNIT_TEST - tristate "KUnit test ffs-family functions at runtime" if !KUNIT_ALL_TESTS - depends on KUNIT -diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c -index 2bed641e1eae..cd5837373427 100644 ---- a/lib/tests/string_kunit.c -+++ b/lib/tests/string_kunit.c -@@ -6,11 +6,17 @@ - #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - - #include -+#include -+#include -+#include - #include - #include -+#include - #include - #include - #include -+#include -+#include - #include - - #define STRCMP_LARGE_BUF_LEN 2048 -@@ -22,6 +28,9 @@ - #define STRING_TEST_MAX_LEN 128 - #define STRING_TEST_MAX_OFFSET 16 - -+#define STRING_BENCH_SEED 888 -+#define STRING_BENCH_WORKLOAD (1 * MEGA) -+ - static void string_test_memset16(struct kunit *test) - { - unsigned i, j, k; -@@ -707,6 +716,156 @@ static void string_test_strends(struct kunit *test) - KUNIT_EXPECT_TRUE(test, strends("", "")); - } - -+#if IS_ENABLED(CONFIG_STRING_KUNIT_BENCH) -+/* Target string lengths for benchmarking */ -+static const size_t bench_lens[] = { -+ 0, 1, 7, 8, 16, 31, 64, 127, 512, 1024, 3173, 4096, -+}; -+ -+/** -+ * alloc_max_bench_buffer() - Allocate buffer for the max test case. -+ * @test: KUnit context for managed allocation. -+ * @lens: Array of lengths used in the benchmark cases. -+ * @count: Number of elements in the @lens array. -+ * @buf_len: [out] Pointer to store the actually allocated buffer -+ * size (including NUL character). -+ * -+ * Return: Pointer to the allocated memory, or NULL on failure. -+ */ -+static void *alloc_max_bench_buffer(struct kunit *test, const size_t *lens, -+ size_t count, size_t *buf_len) -+{ -+ size_t max_len = 0; -+ void *buf; -+ -+ for (size_t i = 0; i < count; i++) -+ max_len = max(lens[i], max_len); -+ -+ /* Add space for NUL character */ -+ max_len += 1; -+ -+ buf = kunit_kzalloc(test, max_len, GFP_KERNEL); -+ if (!buf) -+ return NULL; -+ -+ if (buf_len) -+ *buf_len = max_len; -+ -+ return buf; -+} -+ -+/** -+ * fill_random_string() - Populate a buffer with a random NUL-terminated string. -+ * @buf: Buffer to fill. -+ * @len: Length of the buffer in bytes. -+ * -+ * Fills the buffer with random non-NUL bytes and ensures the string is -+ * properly NUL-terminated. -+ */ -+static void fill_random_string(char *buf, size_t len) -+{ -+ struct rnd_state state; -+ -+ if (!buf || !len) -+ return; -+ -+ /* Use a fixed seed to ensure deterministic benchmark results */ -+ prandom_seed_state(&state, STRING_BENCH_SEED); -+ prandom_bytes_state(&state, buf, len); -+ -+ /* Replace NUL characters to avoid early string termination */ -+ for (size_t i = 0; i < len; i++) { -+ if (buf[i] == '\0') -+ buf[i] = 0x01; -+ } -+ -+ buf[len - 1] = '\0'; -+} -+ -+/** -+ * STRING_BENCH() - Benchmark string functions. -+ * @iters: Number of iterations to run. -+ * @func: Function to benchmark. -+ * @...: Variable arguments passed to @func. -+ * -+ * Disables preemption and measures the total time in nanoseconds to execute -+ * @func(@__VA_ARGS__) for @iters times, including a small warm-up phase. -+ * -+ * Context: Disables preemption during measurement. -+ * Return: Total execution time in nanoseconds (u64). -+ */ -+#define STRING_BENCH(iters, func, ...) \ -+({ \ -+ /* Volatile function pointer prevents dead code elimination */ \ -+ typeof(func) (* volatile __func) = (func); \ -+ size_t __bn_iters = (iters); \ -+ size_t __bn_warm_iters; \ -+ u64 __bn_t; \ -+ \ -+ /* Use 10% of the given iterations (maximum 50) to warm up */ \ -+ __bn_warm_iters = max(__bn_iters / 10, 50U); \ -+ \ -+ for (size_t __bn_i = 0; __bn_i < __bn_warm_iters; __bn_i++) \ -+ (void)__func(__VA_ARGS__); \ -+ \ -+ preempt_disable(); \ -+ __bn_t = ktime_get_ns(); \ -+ for (size_t __bn_i = 0; __bn_i < __bn_iters; __bn_i++) \ -+ (void)__func(__VA_ARGS__); \ -+ __bn_t = ktime_get_ns() - __bn_t; \ -+ preempt_enable(); \ -+ __bn_t; \ -+}) -+ -+/** -+ * STRING_BENCH_BUF() - Benchmark harness for single-buffer functions. -+ * @test: KUnit context. -+ * @buf_name: Local char * variable name to be defined. -+ * @buf_size: Local size_t variable name to be defined. -+ * @func: Function to benchmark. -+ * @...: Extra arguments for @func. -+ * -+ * Prepares a randomized, NUL-terminated buffer and iterates through lengths -+ * in bench_lens, defining @buf_name and @buf_size in each loop. -+ */ -+#define STRING_BENCH_BUF(test, buf_name, buf_size, func, ...) \ -+do { \ -+ size_t _bn_i, _bn_iters, _bn_size = 0; \ -+ u64 _bn_t, _bn_mbps = 0, _bn_lat = 0; \ -+ char *_bn_buf; \ -+ \ -+ _bn_buf = alloc_max_bench_buffer(test, bench_lens, \ -+ ARRAY_SIZE(bench_lens), &_bn_size); \ -+ KUNIT_ASSERT_NOT_ERR_OR_NULL(test, _bn_buf); \ -+ \ -+ fill_random_string(_bn_buf, _bn_size); \ -+ \ -+ for (_bn_i = 0; _bn_i < ARRAY_SIZE(bench_lens); _bn_i++) { \ -+ size_t buf_size = bench_lens[_bn_i]; \ -+ char *buf_name = _bn_buf + _bn_size - buf_size - 1; \ -+ _bn_iters = STRING_BENCH_WORKLOAD / max(buf_size, 1U); \ -+ \ -+ _bn_t = STRING_BENCH(_bn_iters, func, ##__VA_ARGS__); \ -+ if (_bn_t > 0) { \ -+ _bn_mbps = (u64)(buf_size) * _bn_iters * \ -+ (NSEC_PER_SEC / MEGA); \ -+ _bn_mbps = div64_u64(_bn_mbps, _bn_t); \ -+ _bn_lat = div64_u64(_bn_t, _bn_iters); \ -+ } \ -+ kunit_info(test, "len=%zu: %llu MB/s (%llu ns/call)\n", \ -+ buf_size, _bn_mbps, _bn_lat); \ -+ } \ -+} while (0) -+#else -+#define STRING_BENCH_BUF(test, buf_name, buf_size, func, ...) \ -+ kunit_skip(test, "not enabled") -+#endif /* IS_ENABLED(CONFIG_STRING_KUNIT_BENCH) */ -+ -+static void string_bench_strlen(struct kunit *test) -+{ -+ STRING_BENCH_BUF(test, buf, len, strlen, buf); -+} -+ - static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_memset16), - KUNIT_CASE(string_test_memset32), -@@ -732,6 +891,7 @@ static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_strtomem), - KUNIT_CASE(string_test_memtostr), - KUNIT_CASE(string_test_strends), -+ KUNIT_CASE(string_bench_strlen), - {} - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch b/SPECS/linux-lts/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch new file mode 100644 index 0000000000..82e732ebcb --- /dev/null +++ b/SPECS/linux-lts/0248-UPSTREAM-riscv-lib-add-strchr-implementation.patch @@ -0,0 +1,129 @@ +From 2f4c1bb28db6a3485cd348d5484cabeee5afb672 Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strchr() implementation + +Add an assembly implementation of strchr() for RISC-V. + +By eliminating stack frame management (prologue/epilogue) and optimizing +the function entries, the assembly version provides significant relative +gains for short strings where the fixed overhead of the C function is +most prominent. As string length increases, performance converges with +the generic C implementation. + +Benchmark results (QEMU TCG, rv64): + Length | Original (MB/s) | Optimized (MB/s) | Improvement + -------|-----------------|------------------|------------ + 1 B | 21 | 22 | +4.8% + 7 B | 113 | 121 | +7.1% + 16 B | 195 | 202 | +3.6% + 512 B | 376 | 389 | +3.5% + 4096 B | 394 | 393 | -0.3% + +Signed-off-by: Feng Jiang +Tested-by: Joel Stanley +Link: https://patch.msgid.link/20260130025018.172925-8-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit adf542133960d402f63c976b00e46be4d986d4c3) +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/string.h | 3 +++ + arch/riscv/lib/Makefile | 1 + + arch/riscv/lib/strchr.S | 35 +++++++++++++++++++++++++++++++++ + arch/riscv/purgatory/Makefile | 5 ++++- + 4 files changed, 43 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/lib/strchr.S + +diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h +index 16634d67c217..ca3ade82b124 100644 +--- a/arch/riscv/include/asm/string.h ++++ b/arch/riscv/include/asm/string.h +@@ -31,6 +31,9 @@ extern asmlinkage int strncmp(const char *cs, const char *ct, size_t count); + + #define __HAVE_ARCH_STRNLEN + extern asmlinkage __kernel_size_t strnlen(const char *, size_t); ++ ++#define __HAVE_ARCH_STRCHR ++extern asmlinkage char *strchr(const char *, int); + #endif + + /* For those files which don't want to check by kasan. */ +diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile +index 0969d8136df0..b7f804dce1c3 100644 +--- a/arch/riscv/lib/Makefile ++++ b/arch/riscv/lib/Makefile +@@ -8,6 +8,7 @@ lib-y += strcmp.o + lib-y += strlen.o + lib-y += strncmp.o + lib-y += strnlen.o ++lib-y += strchr.o + endif + lib-y += csum.o + ifeq ($(CONFIG_MMU), y) +diff --git a/arch/riscv/lib/strchr.S b/arch/riscv/lib/strchr.S +new file mode 100644 +index 000000000000..48c3a9da53e3 +--- /dev/null ++++ b/arch/riscv/lib/strchr.S +@@ -0,0 +1,35 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* ++ * Copyright (C) 2025 Feng Jiang ++ */ ++ ++#include ++#include ++ ++/* char *strchr(const char *s, int c) */ ++SYM_FUNC_START(strchr) ++ /* ++ * Parameters ++ * a0 - The string to be searched ++ * a1 - The character to search for ++ * ++ * Returns ++ * a0 - Address of first occurrence of 'c' or 0 ++ * ++ * Clobbers ++ * t0 ++ */ ++ andi a1, a1, 0xff ++1: ++ lbu t0, 0(a0) ++ beq t0, a1, 2f ++ addi a0, a0, 1 ++ bnez t0, 1b ++ li a0, 0 ++2: ++ ret ++SYM_FUNC_END(strchr) ++ ++SYM_FUNC_ALIAS_WEAK(__pi_strchr, strchr) ++EXPORT_SYMBOL(strchr) +diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile +index d7c0533108be..e7b3d748c913 100644 +--- a/arch/riscv/purgatory/Makefile ++++ b/arch/riscv/purgatory/Makefile +@@ -2,7 +2,7 @@ + + purgatory-y := purgatory.o sha256.o entry.o string.o ctype.o memcpy.o memset.o + ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) +-purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o ++purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o strchr.o + endif + + targets += $(purgatory-y) +@@ -35,6 +35,9 @@ $(obj)/sha256.o: $(srctree)/lib/crypto/sha256.c FORCE + $(obj)/strnlen.o: $(srctree)/arch/riscv/lib/strnlen.S FORCE + $(call if_changed_rule,as_o_S) + ++$(obj)/strchr.o: $(srctree)/arch/riscv/lib/strchr.S FORCE ++ $(call if_changed_rule,as_o_S) ++ + CFLAGS_sha256.o := -D__DISABLE_EXPORTS -D__NO_FORTIFY + CFLAGS_string.o := -D__DISABLE_EXPORTS + CFLAGS_ctype.o := -D__DISABLE_EXPORTS +-- +2.53.0 + diff --git a/SPECS/linux-lts/0249-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch b/SPECS/linux-lts/0249-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch deleted file mode 100644 index dfda66cc5e..0000000000 --- a/SPECS/linux-lts/0249-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch +++ /dev/null @@ -1,66 +0,0 @@ -From d0124b59c28b2a764db245d8be9fc383ac7e7933 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 249/467] UPSTREAM: lib/string_kunit: extend benchmarks to - strnlen() and chr searches - -Extend the string benchmarking suite to include strnlen(), strchr(), -and strrchr(). - -For character search functions strchr() and strrchr(), the benchmark -targets the NUL character. This ensures the entire string is scanned, -providing a consistent measure of full-length processing efficiency -comparable to strlen(). - -Suggested-by: Andy Shevchenko -Suggested-by: Eric Biggers -Signed-off-by: Feng Jiang -Acked-by: Andy Shevchenko -Reviewed-by: Kees Cook -Link: https://patch.msgid.link/20260130025018.172925-6-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit e73bcb3708a69369d506e5bc6a63d4fc13d8e28a) -Signed-off-by: Han Gao ---- - lib/tests/string_kunit.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/lib/tests/string_kunit.c b/lib/tests/string_kunit.c -index cd5837373427..0819ace5b027 100644 ---- a/lib/tests/string_kunit.c -+++ b/lib/tests/string_kunit.c -@@ -866,6 +866,21 @@ static void string_bench_strlen(struct kunit *test) - STRING_BENCH_BUF(test, buf, len, strlen, buf); - } - -+static void string_bench_strnlen(struct kunit *test) -+{ -+ STRING_BENCH_BUF(test, buf, len, strnlen, buf, len); -+} -+ -+static void string_bench_strchr(struct kunit *test) -+{ -+ STRING_BENCH_BUF(test, buf, len, strchr, buf, '\0'); -+} -+ -+static void string_bench_strrchr(struct kunit *test) -+{ -+ STRING_BENCH_BUF(test, buf, len, strrchr, buf, '\0'); -+} -+ - static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_memset16), - KUNIT_CASE(string_test_memset32), -@@ -892,6 +907,9 @@ static struct kunit_case string_test_cases[] = { - KUNIT_CASE(string_test_memtostr), - KUNIT_CASE(string_test_strends), - KUNIT_CASE(string_bench_strlen), -+ KUNIT_CASE(string_bench_strnlen), -+ KUNIT_CASE(string_bench_strchr), -+ KUNIT_CASE(string_bench_strrchr), - {} - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch b/SPECS/linux-lts/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch new file mode 100644 index 0000000000..4a1a619b26 --- /dev/null +++ b/SPECS/linux-lts/0249-UPSTREAM-riscv-lib-add-strrchr-implementation.patch @@ -0,0 +1,130 @@ +From 7a1bef3a9306a7c4cd45d233b4965356c86f23d4 Mon Sep 17 00:00:00 2001 +From: Feng Jiang +Date: Fri, 3 Apr 2026 19:28:47 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strrchr() implementation + +Add an assembly implementation of strrchr() for RISC-V. + +This implementation minimizes instruction count and avoids unnecessary +memory access to the stack. The performance benefits are most visible +on small workloads (1-16 bytes) where the architectural savings in +function overhead outweigh the execution time of the scan loop. + +Benchmark results (QEMU TCG, rv64): + Length | Original (MB/s) | Optimized (MB/s) | Improvement + -------|-----------------|------------------|------------ + 1 B | 20 | 21 | +5.0% + 7 B | 111 | 120 | +8.1% + 16 B | 189 | 199 | +5.3% + 512 B | 361 | 382 | +5.8% + 4096 B | 388 | 391 | +0.8% + +Signed-off-by: Feng Jiang +Tested-by: Joel Stanley +Link: https://patch.msgid.link/20260130025018.172925-9-jiangfeng@kylinos.cn +Signed-off-by: Paul Walmsley +(cherry picked from commit bef64bcb940269a503d12eb1bc180d1aa9adf74d) +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/string.h | 3 +++ + arch/riscv/lib/Makefile | 1 + + arch/riscv/lib/strrchr.S | 37 +++++++++++++++++++++++++++++++++ + arch/riscv/purgatory/Makefile | 5 ++++- + 4 files changed, 45 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/lib/strrchr.S + +diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h +index ca3ade82b124..764ffe8f6479 100644 +--- a/arch/riscv/include/asm/string.h ++++ b/arch/riscv/include/asm/string.h +@@ -34,6 +34,9 @@ extern asmlinkage __kernel_size_t strnlen(const char *, size_t); + + #define __HAVE_ARCH_STRCHR + extern asmlinkage char *strchr(const char *, int); ++ ++#define __HAVE_ARCH_STRRCHR ++extern asmlinkage char *strrchr(const char *, int); + #endif + + /* For those files which don't want to check by kasan. */ +diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile +index b7f804dce1c3..735d0b665536 100644 +--- a/arch/riscv/lib/Makefile ++++ b/arch/riscv/lib/Makefile +@@ -9,6 +9,7 @@ lib-y += strlen.o + lib-y += strncmp.o + lib-y += strnlen.o + lib-y += strchr.o ++lib-y += strrchr.o + endif + lib-y += csum.o + ifeq ($(CONFIG_MMU), y) +diff --git a/arch/riscv/lib/strrchr.S b/arch/riscv/lib/strrchr.S +new file mode 100644 +index 000000000000..ac58b20ca21d +--- /dev/null ++++ b/arch/riscv/lib/strrchr.S +@@ -0,0 +1,37 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++/* ++ * Copyright (C) 2025 Feng Jiang ++ */ ++ ++#include ++#include ++ ++/* char *strrchr(const char *s, int c) */ ++SYM_FUNC_START(strrchr) ++ /* ++ * Parameters ++ * a0 - The string to be searched ++ * a1 - The character to seaerch for ++ * ++ * Returns ++ * a0 - Address of last occurrence of 'c' or 0 ++ * ++ * Clobbers ++ * t0, t1 ++ */ ++ andi a1, a1, 0xff ++ mv t1, a0 ++ li a0, 0 ++1: ++ lbu t0, 0(t1) ++ bne t0, a1, 2f ++ mv a0, t1 ++2: ++ addi t1, t1, 1 ++ bnez t0, 1b ++ ret ++SYM_FUNC_END(strrchr) ++ ++SYM_FUNC_ALIAS_WEAK(__pi_strrchr, strrchr) ++EXPORT_SYMBOL(strrchr) +diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile +index e7b3d748c913..b0358a78f11a 100644 +--- a/arch/riscv/purgatory/Makefile ++++ b/arch/riscv/purgatory/Makefile +@@ -2,7 +2,7 @@ + + purgatory-y := purgatory.o sha256.o entry.o string.o ctype.o memcpy.o memset.o + ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) +-purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o strchr.o ++purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o strchr.o strrchr.o + endif + + targets += $(purgatory-y) +@@ -38,6 +38,9 @@ $(obj)/strnlen.o: $(srctree)/arch/riscv/lib/strnlen.S FORCE + $(obj)/strchr.o: $(srctree)/arch/riscv/lib/strchr.S FORCE + $(call if_changed_rule,as_o_S) + ++$(obj)/strrchr.o: $(srctree)/arch/riscv/lib/strrchr.S FORCE ++ $(call if_changed_rule,as_o_S) ++ + CFLAGS_sha256.o := -D__DISABLE_EXPORTS -D__NO_FORTIFY + CFLAGS_string.o := -D__DISABLE_EXPORTS + CFLAGS_ctype.o := -D__DISABLE_EXPORTS +-- +2.53.0 + diff --git a/SPECS/linux-lts/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch b/SPECS/linux-lts/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch new file mode 100644 index 0000000000..a11233ee84 --- /dev/null +++ b/SPECS/linux-lts/0250-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch @@ -0,0 +1,52 @@ +From 0bd7f056d6569dc61e0cc65e7eaab3c9d9d1e879 Mon Sep 17 00:00:00 2001 +From: Vincent Guittot +Date: Fri, 21 Nov 2025 17:49:18 +0100 +Subject: [RUYI PATCH] UPSTREAM: PCI: dwc: Add register and bitfield + definitions + +Add register and bitfield definitions: + + - GEN3_RELATED_OFF_EQ_PHASE_2_3 field of GEN3_RELATED_OFF + + - Coherency control registers + +Signed-off-by: Vincent Guittot +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Helgaas +Reviewed-by: Frank Li +Link: https://patch.msgid.link/20251121164920.2008569-3-vincent.guittot@linaro.org +(cherry picked from commit 045ad2c623d607f2c7720e2b8fcda675d96f7381) +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-designware.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h +index aa27211b68dd..295e113189b7 100644 +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -123,6 +123,7 @@ + + #define GEN3_RELATED_OFF 0x890 + #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) ++#define GEN3_RELATED_OFF_EQ_PHASE_2_3 BIT(9) + #define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13) + #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) + #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 +@@ -140,6 +141,13 @@ + #define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA GENMASK(13, 10) + #define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA GENMASK(17, 14) + ++#define COHERENCY_CONTROL_1_OFF 0x8E0 ++#define CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK GENMASK(31, 2) ++#define CFG_MEMTYPE_VALUE BIT(0) ++ ++#define COHERENCY_CONTROL_2_OFF 0x8E4 ++#define COHERENCY_CONTROL_3_OFF 0x8E8 ++ + #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 + #define PORT_MLTI_UPCFG_SUPPORT BIT(7) + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0250-UPSTREAM-riscv-lib-add-strnlen-implementation.patch b/SPECS/linux-lts/0250-UPSTREAM-riscv-lib-add-strnlen-implementation.patch deleted file mode 100644 index c5b7f485ce..0000000000 --- a/SPECS/linux-lts/0250-UPSTREAM-riscv-lib-add-strnlen-implementation.patch +++ /dev/null @@ -1,252 +0,0 @@ -From c90c1b627d1a7bfa2d85045606e6db6a1224dbe2 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 250/467] UPSTREAM: riscv: lib: add strnlen() implementation - -Add an optimized strnlen() implementation for RISC-V. This version -includes a generic optimization and a Zbb-powered optimization using -the 'orc.b' instruction, derived from the strlen() implementation. - -Benchmark results (QEMU TCG, rv64): - Length | Original (MB/s) | Optimized (MB/s) | Improvement - -------|-----------------|------------------|------------ - 16 B | 179 | 309 | +72.6% - 512 B | 347 | 1562 | +350.1% - 4096 B | 356 | 1878 | +427.5% - -Suggested-by: Qingfang Deng -Signed-off-by: Feng Jiang -Link: https://patch.msgid.link/20260130025018.172925-7-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit 5ba15d419fab848a3813eb56bbcad00e291fbc49) -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/string.h | 3 + - arch/riscv/lib/Makefile | 1 + - arch/riscv/lib/strnlen.S | 164 ++++++++++++++++++++++++++++++++ - arch/riscv/purgatory/Makefile | 5 +- - 4 files changed, 172 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/lib/strnlen.S - -diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h -index 5ba77f60bf0b..16634d67c217 100644 ---- a/arch/riscv/include/asm/string.h -+++ b/arch/riscv/include/asm/string.h -@@ -28,6 +28,9 @@ extern asmlinkage __kernel_size_t strlen(const char *); - - #define __HAVE_ARCH_STRNCMP - extern asmlinkage int strncmp(const char *cs, const char *ct, size_t count); -+ -+#define __HAVE_ARCH_STRNLEN -+extern asmlinkage __kernel_size_t strnlen(const char *, size_t); - #endif - - /* For those files which don't want to check by kasan. */ -diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile -index bbc031124974..0969d8136df0 100644 ---- a/arch/riscv/lib/Makefile -+++ b/arch/riscv/lib/Makefile -@@ -7,6 +7,7 @@ ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) - lib-y += strcmp.o - lib-y += strlen.o - lib-y += strncmp.o -+lib-y += strnlen.o - endif - lib-y += csum.o - ifeq ($(CONFIG_MMU), y) -diff --git a/arch/riscv/lib/strnlen.S b/arch/riscv/lib/strnlen.S -new file mode 100644 -index 000000000000..53afa7b5b314 ---- /dev/null -+++ b/arch/riscv/lib/strnlen.S -@@ -0,0 +1,164 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* -+ * Base on arch/riscv/lib/strlen.S -+ * -+ * Copyright (C) Feng Jiang -+ */ -+ -+#include -+#include -+#include -+#include -+ -+/* size_t strnlen(const char *s, size_t count) */ -+SYM_FUNC_START(strnlen) -+ -+ __ALTERNATIVE_CFG("nop", "j strnlen_zbb", 0, RISCV_ISA_EXT_ZBB, -+ IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) -+ -+ -+ /* -+ * Returns -+ * a0 - String length -+ * -+ * Parameters -+ * a0 - String to measure -+ * a1 - Max length of string -+ * -+ * Clobbers -+ * t0, t1, t2 -+ */ -+ addi t1, a0, -1 -+ add t2, a0, a1 -+1: -+ addi t1, t1, 1 -+ beq t1, t2, 2f -+ lbu t0, 0(t1) -+ bnez t0, 1b -+2: -+ sub a0, t1, a0 -+ ret -+ -+ -+/* -+ * Variant of strnlen using the ZBB extension if available -+ */ -+#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) -+strnlen_zbb: -+ -+#ifdef CONFIG_CPU_BIG_ENDIAN -+# define CZ clz -+# define SHIFT sll -+#else -+# define CZ ctz -+# define SHIFT srl -+#endif -+ -+.option push -+.option arch,+zbb -+ -+ /* -+ * Returns -+ * a0 - String length -+ * -+ * Parameters -+ * a0 - String to measure -+ * a1 - Max length of string -+ * -+ * Clobbers -+ * t0, t1, t2, t3, t4 -+ */ -+ -+ /* If maxlen is 0, return 0. */ -+ beqz a1, 3f -+ -+ /* Number of irrelevant bytes in the first word. */ -+ andi t2, a0, SZREG-1 -+ -+ /* Align pointer. */ -+ andi t0, a0, -SZREG -+ -+ li t3, SZREG -+ sub t3, t3, t2 -+ slli t2, t2, 3 -+ -+ /* Aligned boundary. */ -+ add t4, a0, a1 -+ andi t4, t4, -SZREG -+ -+ /* Get the first word. */ -+ REG_L t1, 0(t0) -+ -+ /* -+ * Shift away the partial data we loaded to remove the irrelevant bytes -+ * preceding the string with the effect of adding NUL bytes at the -+ * end of the string's first word. -+ */ -+ SHIFT t1, t1, t2 -+ -+ /* Convert non-NUL into 0xff and NUL into 0x00. */ -+ orc.b t1, t1 -+ -+ /* Convert non-NUL into 0x00 and NUL into 0xff. */ -+ not t1, t1 -+ -+ /* -+ * Search for the first set bit (corresponding to a NUL byte in the -+ * original chunk). -+ */ -+ CZ t1, t1 -+ -+ /* -+ * The first chunk is special: compare against the number -+ * of valid bytes in this chunk. -+ */ -+ srli a0, t1, 3 -+ -+ /* Limit the result by maxlen. */ -+ minu a0, a0, a1 -+ -+ bgtu t3, a0, 2f -+ -+ /* Prepare for the word comparison loop. */ -+ addi t2, t0, SZREG -+ li t3, -1 -+ -+ /* -+ * Our critical loop is 4 instructions and processes data in -+ * 4 byte or 8 byte chunks. -+ */ -+ .p2align 3 -+1: -+ REG_L t1, SZREG(t0) -+ addi t0, t0, SZREG -+ orc.b t1, t1 -+ bgeu t0, t4, 4f -+ beq t1, t3, 1b -+4: -+ not t1, t1 -+ CZ t1, t1 -+ srli t1, t1, 3 -+ -+ /* Get number of processed bytes. */ -+ sub t2, t0, t2 -+ -+ /* Add number of characters in the first word. */ -+ add a0, a0, t2 -+ -+ /* Add number of characters in the last word. */ -+ add a0, a0, t1 -+ -+ /* Ensure the final result does not exceed maxlen. */ -+ minu a0, a0, a1 -+2: -+ ret -+3: -+ mv a0, a1 -+ ret -+ -+.option pop -+#endif -+SYM_FUNC_END(strnlen) -+SYM_FUNC_ALIAS(__pi_strnlen, strnlen) -+EXPORT_SYMBOL(strnlen) -diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile -index 530e497ca2f9..d7c0533108be 100644 ---- a/arch/riscv/purgatory/Makefile -+++ b/arch/riscv/purgatory/Makefile -@@ -2,7 +2,7 @@ - - purgatory-y := purgatory.o sha256.o entry.o string.o ctype.o memcpy.o memset.o - ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) --purgatory-y += strcmp.o strlen.o strncmp.o -+purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o - endif - - targets += $(purgatory-y) -@@ -32,6 +32,9 @@ $(obj)/strncmp.o: $(srctree)/arch/riscv/lib/strncmp.S FORCE - $(obj)/sha256.o: $(srctree)/lib/crypto/sha256.c FORCE - $(call if_changed_rule,cc_o_c) - -+$(obj)/strnlen.o: $(srctree)/arch/riscv/lib/strnlen.S FORCE -+ $(call if_changed_rule,as_o_S) -+ - CFLAGS_sha256.o := -D__DISABLE_EXPORTS -D__NO_FORTIFY - CFLAGS_string.o := -D__DISABLE_EXPORTS - CFLAGS_ctype.o := -D__DISABLE_EXPORTS --- -2.53.0 - diff --git a/SPECS/linux-lts/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch b/SPECS/linux-lts/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch new file mode 100644 index 0000000000..9b9454daa8 --- /dev/null +++ b/SPECS/linux-lts/0251-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch @@ -0,0 +1,100 @@ +From 22c3a93bf61eb47e3b47fd1cbfb9bed064b5de81 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Wed, 29 Apr 2026 09:38:47 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: move hw constraints from + hw_params to startup + +Hardware constraints should be applied in the startup callback rather +than hw_params, as hw_params may be called too late for the constraints +to take effect properly. + +Move the channel count and format constraints for I2S and DSP_A/DSP_B +modes into a new startup callback. This also tightens the I2S mode +channel constraint from 1-2 to exactly 2, matching the actual hardware +behavior. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260429-k3-i2s-v1-2-2fe99db11ecb@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit 6b4afbaaa342eaa52172e0be5ef8d1fcbf9ff460) +Signed-off-by: Han Gao +--- + sound/soc/spacemit/k1_i2s.c | 45 ++++++++++++++++++++++++++----------- + 1 file changed, 32 insertions(+), 13 deletions(-) + +diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c +index abc439b53e3d..331668b979fd 100644 +--- a/sound/soc/spacemit/k1_i2s.c ++++ b/sound/soc/spacemit/k1_i2s.c +@@ -106,6 +106,37 @@ static void spacemit_i2s_init(struct spacemit_i2s_dev *i2s) + writel(0, i2s->base + SSINTEN); + } + ++static int spacemit_i2s_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct spacemit_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); ++ ++ switch (i2s->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ snd_pcm_hw_constraint_minmax(substream->runtime, ++ SNDRV_PCM_HW_PARAM_CHANNELS, ++ 2, 2); ++ snd_pcm_hw_constraint_mask64(substream->runtime, ++ SNDRV_PCM_HW_PARAM_FORMAT, ++ SNDRV_PCM_FMTBIT_S16_LE); ++ break; ++ case SND_SOC_DAIFMT_DSP_A: ++ case SND_SOC_DAIFMT_DSP_B: ++ snd_pcm_hw_constraint_minmax(substream->runtime, ++ SNDRV_PCM_HW_PARAM_CHANNELS, ++ 1, 1); ++ snd_pcm_hw_constraint_mask64(substream->runtime, ++ SNDRV_PCM_HW_PARAM_FORMAT, ++ SNDRV_PCM_FMTBIT_S32_LE); ++ break; ++ default: ++ dev_dbg(i2s->dev, "unexpected format type"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ + static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +@@ -157,22 +188,9 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, + dma_data->maxburst = 32; + dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + } +- +- snd_pcm_hw_constraint_minmax(substream->runtime, +- SNDRV_PCM_HW_PARAM_CHANNELS, +- 1, 2); +- snd_pcm_hw_constraint_mask64(substream->runtime, +- SNDRV_PCM_HW_PARAM_FORMAT, +- SNDRV_PCM_FMTBIT_S16_LE); + break; + case SND_SOC_DAIFMT_DSP_A: + case SND_SOC_DAIFMT_DSP_B: +- snd_pcm_hw_constraint_minmax(substream->runtime, +- SNDRV_PCM_HW_PARAM_CHANNELS, +- 1, 1); +- snd_pcm_hw_constraint_mask64(substream->runtime, +- SNDRV_PCM_HW_PARAM_FORMAT, +- SNDRV_PCM_FMTBIT_S32_LE); + break; + default: + dev_dbg(i2s->dev, "unexpected format type"); +@@ -303,6 +321,7 @@ static int spacemit_i2s_dai_remove(struct snd_soc_dai *dai) + static const struct snd_soc_dai_ops spacemit_i2s_dai_ops = { + .probe = spacemit_i2s_dai_probe, + .remove = spacemit_i2s_dai_remove, ++ .startup = spacemit_i2s_startup, + .hw_params = spacemit_i2s_hw_params, + .set_sysclk = spacemit_i2s_set_sysclk, + .set_fmt = spacemit_i2s_set_fmt, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0251-UPSTREAM-riscv-lib-add-strchr-implementation.patch b/SPECS/linux-lts/0251-UPSTREAM-riscv-lib-add-strchr-implementation.patch deleted file mode 100644 index 11242e7cf1..0000000000 --- a/SPECS/linux-lts/0251-UPSTREAM-riscv-lib-add-strchr-implementation.patch +++ /dev/null @@ -1,129 +0,0 @@ -From d70c03b9f8f7b1f45dfa6d3b248cd26e173574bf Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 251/467] UPSTREAM: riscv: lib: add strchr() implementation - -Add an assembly implementation of strchr() for RISC-V. - -By eliminating stack frame management (prologue/epilogue) and optimizing -the function entries, the assembly version provides significant relative -gains for short strings where the fixed overhead of the C function is -most prominent. As string length increases, performance converges with -the generic C implementation. - -Benchmark results (QEMU TCG, rv64): - Length | Original (MB/s) | Optimized (MB/s) | Improvement - -------|-----------------|------------------|------------ - 1 B | 21 | 22 | +4.8% - 7 B | 113 | 121 | +7.1% - 16 B | 195 | 202 | +3.6% - 512 B | 376 | 389 | +3.5% - 4096 B | 394 | 393 | -0.3% - -Signed-off-by: Feng Jiang -Tested-by: Joel Stanley -Link: https://patch.msgid.link/20260130025018.172925-8-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit adf542133960d402f63c976b00e46be4d986d4c3) -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/string.h | 3 +++ - arch/riscv/lib/Makefile | 1 + - arch/riscv/lib/strchr.S | 35 +++++++++++++++++++++++++++++++++ - arch/riscv/purgatory/Makefile | 5 ++++- - 4 files changed, 43 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/lib/strchr.S - -diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h -index 16634d67c217..ca3ade82b124 100644 ---- a/arch/riscv/include/asm/string.h -+++ b/arch/riscv/include/asm/string.h -@@ -31,6 +31,9 @@ extern asmlinkage int strncmp(const char *cs, const char *ct, size_t count); - - #define __HAVE_ARCH_STRNLEN - extern asmlinkage __kernel_size_t strnlen(const char *, size_t); -+ -+#define __HAVE_ARCH_STRCHR -+extern asmlinkage char *strchr(const char *, int); - #endif - - /* For those files which don't want to check by kasan. */ -diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile -index 0969d8136df0..b7f804dce1c3 100644 ---- a/arch/riscv/lib/Makefile -+++ b/arch/riscv/lib/Makefile -@@ -8,6 +8,7 @@ lib-y += strcmp.o - lib-y += strlen.o - lib-y += strncmp.o - lib-y += strnlen.o -+lib-y += strchr.o - endif - lib-y += csum.o - ifeq ($(CONFIG_MMU), y) -diff --git a/arch/riscv/lib/strchr.S b/arch/riscv/lib/strchr.S -new file mode 100644 -index 000000000000..48c3a9da53e3 ---- /dev/null -+++ b/arch/riscv/lib/strchr.S -@@ -0,0 +1,35 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* -+ * Copyright (C) 2025 Feng Jiang -+ */ -+ -+#include -+#include -+ -+/* char *strchr(const char *s, int c) */ -+SYM_FUNC_START(strchr) -+ /* -+ * Parameters -+ * a0 - The string to be searched -+ * a1 - The character to search for -+ * -+ * Returns -+ * a0 - Address of first occurrence of 'c' or 0 -+ * -+ * Clobbers -+ * t0 -+ */ -+ andi a1, a1, 0xff -+1: -+ lbu t0, 0(a0) -+ beq t0, a1, 2f -+ addi a0, a0, 1 -+ bnez t0, 1b -+ li a0, 0 -+2: -+ ret -+SYM_FUNC_END(strchr) -+ -+SYM_FUNC_ALIAS_WEAK(__pi_strchr, strchr) -+EXPORT_SYMBOL(strchr) -diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile -index d7c0533108be..e7b3d748c913 100644 ---- a/arch/riscv/purgatory/Makefile -+++ b/arch/riscv/purgatory/Makefile -@@ -2,7 +2,7 @@ - - purgatory-y := purgatory.o sha256.o entry.o string.o ctype.o memcpy.o memset.o - ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) --purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o -+purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o strchr.o - endif - - targets += $(purgatory-y) -@@ -35,6 +35,9 @@ $(obj)/sha256.o: $(srctree)/lib/crypto/sha256.c FORCE - $(obj)/strnlen.o: $(srctree)/arch/riscv/lib/strnlen.S FORCE - $(call if_changed_rule,as_o_S) - -+$(obj)/strchr.o: $(srctree)/arch/riscv/lib/strchr.S FORCE -+ $(call if_changed_rule,as_o_S) -+ - CFLAGS_sha256.o := -D__DISABLE_EXPORTS -D__NO_FORTIFY - CFLAGS_string.o := -D__DISABLE_EXPORTS - CFLAGS_ctype.o := -D__DISABLE_EXPORTS --- -2.53.0 - diff --git a/SPECS/linux-lts/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch b/SPECS/linux-lts/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch new file mode 100644 index 0000000000..a235db3255 --- /dev/null +++ b/SPECS/linux-lts/0252-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch @@ -0,0 +1,38 @@ +From b81d7e8285e49c07fa31cdb599fdeedddec0fb3c Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Wed, 29 Apr 2026 09:38:48 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: adjust FIFO trigger threshold + to half FIFO size + +Set both TX and RX FIFO trigger thresholds (TFT/RFT) to 0xF (half of +the 32-entry FIFO) instead of 5. This provides better DMA efficiency +by allowing more data to accumulate before triggering a DMA request, +reducing the number of DMA transactions needed. + +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260429-k3-i2s-v1-3-2fe99db11ecb@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit 03dcb5b68a96b51157ec2d17042fa2f0106828ae) +Signed-off-by: Han Gao +--- + sound/soc/spacemit/k1_i2s.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c +index 331668b979fd..b48c57bede37 100644 +--- a/sound/soc/spacemit/k1_i2s.c ++++ b/sound/soc/spacemit/k1_i2s.c +@@ -93,8 +93,8 @@ static void spacemit_i2s_init(struct spacemit_i2s_dev *i2s) + u32 sscr_val, sspsp_val, ssfcr_val, ssrwt_val; + + sscr_val = SSCR_TRAIL | SSCR_FRF_PSP; +- ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 5) | +- FIELD_PREP(SSFCR_FIELD_RFT, 5) | ++ ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 0xF) | ++ FIELD_PREP(SSFCR_FIELD_RFT, 0xF) | + SSFCR_RSRE | SSFCR_TSRE; + ssrwt_val = SSRWT_RWOT; + sspsp_val = SSPSP_SFRMP; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0252-UPSTREAM-riscv-lib-add-strrchr-implementation.patch b/SPECS/linux-lts/0252-UPSTREAM-riscv-lib-add-strrchr-implementation.patch deleted file mode 100644 index bbb8905d30..0000000000 --- a/SPECS/linux-lts/0252-UPSTREAM-riscv-lib-add-strrchr-implementation.patch +++ /dev/null @@ -1,130 +0,0 @@ -From d06ce21328bc140c9a983924c52277ee37808254 Mon Sep 17 00:00:00 2001 -From: Feng Jiang -Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 252/467] UPSTREAM: riscv: lib: add strrchr() implementation - -Add an assembly implementation of strrchr() for RISC-V. - -This implementation minimizes instruction count and avoids unnecessary -memory access to the stack. The performance benefits are most visible -on small workloads (1-16 bytes) where the architectural savings in -function overhead outweigh the execution time of the scan loop. - -Benchmark results (QEMU TCG, rv64): - Length | Original (MB/s) | Optimized (MB/s) | Improvement - -------|-----------------|------------------|------------ - 1 B | 20 | 21 | +5.0% - 7 B | 111 | 120 | +8.1% - 16 B | 189 | 199 | +5.3% - 512 B | 361 | 382 | +5.8% - 4096 B | 388 | 391 | +0.8% - -Signed-off-by: Feng Jiang -Tested-by: Joel Stanley -Link: https://patch.msgid.link/20260130025018.172925-9-jiangfeng@kylinos.cn -Signed-off-by: Paul Walmsley -(cherry picked from commit bef64bcb940269a503d12eb1bc180d1aa9adf74d) -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/string.h | 3 +++ - arch/riscv/lib/Makefile | 1 + - arch/riscv/lib/strrchr.S | 37 +++++++++++++++++++++++++++++++++ - arch/riscv/purgatory/Makefile | 5 ++++- - 4 files changed, 45 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/lib/strrchr.S - -diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h -index ca3ade82b124..764ffe8f6479 100644 ---- a/arch/riscv/include/asm/string.h -+++ b/arch/riscv/include/asm/string.h -@@ -34,6 +34,9 @@ extern asmlinkage __kernel_size_t strnlen(const char *, size_t); - - #define __HAVE_ARCH_STRCHR - extern asmlinkage char *strchr(const char *, int); -+ -+#define __HAVE_ARCH_STRRCHR -+extern asmlinkage char *strrchr(const char *, int); - #endif - - /* For those files which don't want to check by kasan. */ -diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile -index b7f804dce1c3..735d0b665536 100644 ---- a/arch/riscv/lib/Makefile -+++ b/arch/riscv/lib/Makefile -@@ -9,6 +9,7 @@ lib-y += strlen.o - lib-y += strncmp.o - lib-y += strnlen.o - lib-y += strchr.o -+lib-y += strrchr.o - endif - lib-y += csum.o - ifeq ($(CONFIG_MMU), y) -diff --git a/arch/riscv/lib/strrchr.S b/arch/riscv/lib/strrchr.S -new file mode 100644 -index 000000000000..ac58b20ca21d ---- /dev/null -+++ b/arch/riscv/lib/strrchr.S -@@ -0,0 +1,37 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+/* -+ * Copyright (C) 2025 Feng Jiang -+ */ -+ -+#include -+#include -+ -+/* char *strrchr(const char *s, int c) */ -+SYM_FUNC_START(strrchr) -+ /* -+ * Parameters -+ * a0 - The string to be searched -+ * a1 - The character to seaerch for -+ * -+ * Returns -+ * a0 - Address of last occurrence of 'c' or 0 -+ * -+ * Clobbers -+ * t0, t1 -+ */ -+ andi a1, a1, 0xff -+ mv t1, a0 -+ li a0, 0 -+1: -+ lbu t0, 0(t1) -+ bne t0, a1, 2f -+ mv a0, t1 -+2: -+ addi t1, t1, 1 -+ bnez t0, 1b -+ ret -+SYM_FUNC_END(strrchr) -+ -+SYM_FUNC_ALIAS_WEAK(__pi_strrchr, strrchr) -+EXPORT_SYMBOL(strrchr) -diff --git a/arch/riscv/purgatory/Makefile b/arch/riscv/purgatory/Makefile -index e7b3d748c913..b0358a78f11a 100644 ---- a/arch/riscv/purgatory/Makefile -+++ b/arch/riscv/purgatory/Makefile -@@ -2,7 +2,7 @@ - - purgatory-y := purgatory.o sha256.o entry.o string.o ctype.o memcpy.o memset.o - ifeq ($(CONFIG_KASAN_GENERIC)$(CONFIG_KASAN_SW_TAGS),) --purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o strchr.o -+purgatory-y += strcmp.o strlen.o strncmp.o strnlen.o strchr.o strrchr.o - endif - - targets += $(purgatory-y) -@@ -38,6 +38,9 @@ $(obj)/strnlen.o: $(srctree)/arch/riscv/lib/strnlen.S FORCE - $(obj)/strchr.o: $(srctree)/arch/riscv/lib/strchr.S FORCE - $(call if_changed_rule,as_o_S) - -+$(obj)/strrchr.o: $(srctree)/arch/riscv/lib/strrchr.S FORCE -+ $(call if_changed_rule,as_o_S) -+ - CFLAGS_sha256.o := -D__DISABLE_EXPORTS -D__NO_FORTIFY - CFLAGS_string.o := -D__DISABLE_EXPORTS - CFLAGS_ctype.o := -D__DISABLE_EXPORTS --- -2.53.0 - diff --git a/SPECS/linux-lts/0253-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch b/SPECS/linux-lts/0253-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch deleted file mode 100644 index 139a305f3e..0000000000 --- a/SPECS/linux-lts/0253-UPSTREAM-PCI-dwc-Add-register-and-bitfield-definitio.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 8d6883e557feae1df51a14f0a3008c5104978a75 Mon Sep 17 00:00:00 2001 -From: Vincent Guittot -Date: Fri, 21 Nov 2025 17:49:18 +0100 -Subject: [PATCH 253/467] UPSTREAM: PCI: dwc: Add register and bitfield - definitions - -Add register and bitfield definitions: - - - GEN3_RELATED_OFF_EQ_PHASE_2_3 field of GEN3_RELATED_OFF - - - Coherency control registers - -Signed-off-by: Vincent Guittot -Signed-off-by: Manivannan Sadhasivam -Signed-off-by: Bjorn Helgaas -Reviewed-by: Frank Li -Link: https://patch.msgid.link/20251121164920.2008569-3-vincent.guittot@linaro.org -(cherry picked from commit 045ad2c623d607f2c7720e2b8fcda675d96f7381) -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/pcie-designware.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h -index aa27211b68dd..295e113189b7 100644 ---- a/drivers/pci/controller/dwc/pcie-designware.h -+++ b/drivers/pci/controller/dwc/pcie-designware.h -@@ -123,6 +123,7 @@ - - #define GEN3_RELATED_OFF 0x890 - #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) -+#define GEN3_RELATED_OFF_EQ_PHASE_2_3 BIT(9) - #define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13) - #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) - #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 -@@ -140,6 +141,13 @@ - #define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA GENMASK(13, 10) - #define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA GENMASK(17, 14) - -+#define COHERENCY_CONTROL_1_OFF 0x8E0 -+#define CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK GENMASK(31, 2) -+#define CFG_MEMTYPE_VALUE BIT(0) -+ -+#define COHERENCY_CONTROL_2_OFF 0x8E4 -+#define COHERENCY_CONTROL_3_OFF 0x8E8 -+ - #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0 - #define PORT_MLTI_UPCFG_SUPPORT BIT(7) - --- -2.53.0 - diff --git a/SPECS/linux-lts/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch b/SPECS/linux-lts/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch new file mode 100644 index 0000000000..dbc1d4ed46 --- /dev/null +++ b/SPECS/linux-lts/0253-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch @@ -0,0 +1,43 @@ +From 42cd6879691919aaf3200276ed71a8c7f081bf8f Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 14 Oct 2025 13:10:28 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: reset: thead,th1520-reset: Remove + non-VO-subsystem resets + +Registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} belong to AP +reset controller, not the VO one which is documented as +"thead,th1520-reset" and is the only reset controller supported for +TH1520 for now. + +Let's remove the IDs, leaving them to be implemented by AP-subsystem +reset controller in the future. + +Fixes: 30e7573babdc ("dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller") +Signed-off-by: Yao Zi +Acked-by: Rob Herring (Arm) +Reviewed-by: Drew Fustini +Acked-by: Guo Ren +Signed-off-by: Philipp Zabel +(cherry picked from commit 5334eb9de76c74e24821aae89e111e27398b5add) +Signed-off-by: Han Gao +--- + include/dt-bindings/reset/thead,th1520-reset.h | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h +index ee799286c175..e51d6314d131 100644 +--- a/include/dt-bindings/reset/thead,th1520-reset.h ++++ b/include/dt-bindings/reset/thead,th1520-reset.h +@@ -9,9 +9,6 @@ + + #define TH1520_RESET_ID_GPU 0 + #define TH1520_RESET_ID_GPU_CLKGEN 1 +-#define TH1520_RESET_ID_NPU 2 +-#define TH1520_RESET_ID_WDT0 3 +-#define TH1520_RESET_ID_WDT1 4 + #define TH1520_RESET_ID_DPU_AHB 5 + #define TH1520_RESET_ID_DPU_AXI 6 + #define TH1520_RESET_ID_DPU_CORE 7 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0254-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch b/SPECS/linux-lts/0254-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch deleted file mode 100644 index 802aad400b..0000000000 --- a/SPECS/linux-lts/0254-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 0b98034970a41ebd870d94873762f355265308b5 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Wed, 29 Apr 2026 09:38:47 +0800 -Subject: [PATCH 254/467] UPSTREAM: ASoC: spacemit: move hw constraints from - hw_params to startup - -Hardware constraints should be applied in the startup callback rather -than hw_params, as hw_params may be called too late for the constraints -to take effect properly. - -Move the channel count and format constraints for I2S and DSP_A/DSP_B -modes into a new startup callback. This also tightens the I2S mode -channel constraint from 1-2 to exactly 2, matching the actual hardware -behavior. - -Signed-off-by: Troy Mitchell -Link: https://patch.msgid.link/20260429-k3-i2s-v1-2-2fe99db11ecb@linux.spacemit.com -Signed-off-by: Mark Brown -(cherry picked from commit 6b4afbaaa342eaa52172e0be5ef8d1fcbf9ff460) -Signed-off-by: Han Gao ---- - sound/soc/spacemit/k1_i2s.c | 45 ++++++++++++++++++++++++++----------- - 1 file changed, 32 insertions(+), 13 deletions(-) - -diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c -index abc439b53e3d..331668b979fd 100644 ---- a/sound/soc/spacemit/k1_i2s.c -+++ b/sound/soc/spacemit/k1_i2s.c -@@ -106,6 +106,37 @@ static void spacemit_i2s_init(struct spacemit_i2s_dev *i2s) - writel(0, i2s->base + SSINTEN); - } - -+static int spacemit_i2s_startup(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct spacemit_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); -+ -+ switch (i2s->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_I2S: -+ snd_pcm_hw_constraint_minmax(substream->runtime, -+ SNDRV_PCM_HW_PARAM_CHANNELS, -+ 2, 2); -+ snd_pcm_hw_constraint_mask64(substream->runtime, -+ SNDRV_PCM_HW_PARAM_FORMAT, -+ SNDRV_PCM_FMTBIT_S16_LE); -+ break; -+ case SND_SOC_DAIFMT_DSP_A: -+ case SND_SOC_DAIFMT_DSP_B: -+ snd_pcm_hw_constraint_minmax(substream->runtime, -+ SNDRV_PCM_HW_PARAM_CHANNELS, -+ 1, 1); -+ snd_pcm_hw_constraint_mask64(substream->runtime, -+ SNDRV_PCM_HW_PARAM_FORMAT, -+ SNDRV_PCM_FMTBIT_S32_LE); -+ break; -+ default: -+ dev_dbg(i2s->dev, "unexpected format type"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ - static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, - struct snd_soc_dai *dai) -@@ -157,22 +188,9 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, - dma_data->maxburst = 32; - dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - } -- -- snd_pcm_hw_constraint_minmax(substream->runtime, -- SNDRV_PCM_HW_PARAM_CHANNELS, -- 1, 2); -- snd_pcm_hw_constraint_mask64(substream->runtime, -- SNDRV_PCM_HW_PARAM_FORMAT, -- SNDRV_PCM_FMTBIT_S16_LE); - break; - case SND_SOC_DAIFMT_DSP_A: - case SND_SOC_DAIFMT_DSP_B: -- snd_pcm_hw_constraint_minmax(substream->runtime, -- SNDRV_PCM_HW_PARAM_CHANNELS, -- 1, 1); -- snd_pcm_hw_constraint_mask64(substream->runtime, -- SNDRV_PCM_HW_PARAM_FORMAT, -- SNDRV_PCM_FMTBIT_S32_LE); - break; - default: - dev_dbg(i2s->dev, "unexpected format type"); -@@ -303,6 +321,7 @@ static int spacemit_i2s_dai_remove(struct snd_soc_dai *dai) - static const struct snd_soc_dai_ops spacemit_i2s_dai_ops = { - .probe = spacemit_i2s_dai_probe, - .remove = spacemit_i2s_dai_remove, -+ .startup = spacemit_i2s_startup, - .hw_params = spacemit_i2s_hw_params, - .set_sysclk = spacemit_i2s_set_sysclk, - .set_fmt = spacemit_i2s_set_fmt, --- -2.53.0 - diff --git a/SPECS/linux-lts/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch b/SPECS/linux-lts/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch new file mode 100644 index 0000000000..20d4cb4ce7 --- /dev/null +++ b/SPECS/linux-lts/0254-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch @@ -0,0 +1,277 @@ +From 729fb80f40c116319af3f00f273cb56718995e42 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 14 Oct 2025 13:10:29 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: reset: thead,th1520-reset: Add + controllers for more subsys + +TH1520 SoC is divided into several subsystems, most of them have +distinct reset controllers. Let's document reset controllers other than +the one for VO subsystem and IDs for their reset signals. + +Signed-off-by: Yao Zi +Acked-by: Rob Herring (Arm) +Reviewed-by: Drew Fustini +Acked-by: Guo Ren +Signed-off-by: Philipp Zabel +(cherry picked from commit a35ac6f3bdb135debc8e1ff599d0009bc64dc329) +Signed-off-by: Han Gao +--- + .../bindings/reset/thead,th1520-reset.yaml | 8 +- + .../dt-bindings/reset/thead,th1520-reset.h | 216 ++++++++++++++++++ + 2 files changed, 223 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml +index f2e91d0add7a..7b5053c177fe 100644 +--- a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml ++++ b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml +@@ -16,7 +16,13 @@ maintainers: + properties: + compatible: + enum: +- - thead,th1520-reset ++ - thead,th1520-reset # Reset controller for VO subsystem ++ - thead,th1520-reset-ao ++ - thead,th1520-reset-ap ++ - thead,th1520-reset-dsp ++ - thead,th1520-reset-misc ++ - thead,th1520-reset-vi ++ - thead,th1520-reset-vp + + reg: + maxItems: 1 +diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h +index e51d6314d131..ba6805b6b12a 100644 +--- a/include/dt-bindings/reset/thead,th1520-reset.h ++++ b/include/dt-bindings/reset/thead,th1520-reset.h +@@ -7,6 +7,200 @@ + #ifndef _DT_BINDINGS_TH1520_RESET_H + #define _DT_BINDINGS_TH1520_RESET_H + ++/* AO Subsystem */ ++#define TH1520_RESET_ID_SYSTEM 0 ++#define TH1520_RESET_ID_RTC_APB 1 ++#define TH1520_RESET_ID_RTC_REF 2 ++#define TH1520_RESET_ID_AOGPIO_DB 3 ++#define TH1520_RESET_ID_AOGPIO_APB 4 ++#define TH1520_RESET_ID_AOI2C_APB 5 ++#define TH1520_RESET_ID_PVT_APB 6 ++#define TH1520_RESET_ID_E902_CORE 7 ++#define TH1520_RESET_ID_E902_HAD 8 ++#define TH1520_RESET_ID_AOTIMER_APB 9 ++#define TH1520_RESET_ID_AOTIMER_CORE 10 ++#define TH1520_RESET_ID_AOWDT_APB 11 ++#define TH1520_RESET_ID_APSYS 12 ++#define TH1520_RESET_ID_NPUSYS 13 ++#define TH1520_RESET_ID_DDRSYS 14 ++#define TH1520_RESET_ID_AXI_AP2CP 15 ++#define TH1520_RESET_ID_AXI_CP2AP 16 ++#define TH1520_RESET_ID_AXI_CP2SRAM 17 ++#define TH1520_RESET_ID_AUDSYS_CORE 18 ++#define TH1520_RESET_ID_AUDSYS_IOPMP 19 ++#define TH1520_RESET_ID_AUDSYS 20 ++#define TH1520_RESET_ID_DSP0 21 ++#define TH1520_RESET_ID_DSP1 22 ++#define TH1520_RESET_ID_GPU_MODULE 23 ++#define TH1520_RESET_ID_VDEC 24 ++#define TH1520_RESET_ID_VENC 25 ++#define TH1520_RESET_ID_ADC_APB 26 ++#define TH1520_RESET_ID_AUDGPIO_DB 27 ++#define TH1520_RESET_ID_AUDGPIO_APB 28 ++#define TH1520_RESET_ID_AOUART_IF 29 ++#define TH1520_RESET_ID_AOUART_APB 30 ++#define TH1520_RESET_ID_SRAM_AXI_P0 31 ++#define TH1520_RESET_ID_SRAM_AXI_P1 32 ++#define TH1520_RESET_ID_SRAM_AXI_P2 33 ++#define TH1520_RESET_ID_SRAM_AXI_P3 34 ++#define TH1520_RESET_ID_SRAM_AXI_P4 35 ++#define TH1520_RESET_ID_SRAM_AXI_CORE 36 ++#define TH1520_RESET_ID_SE 37 ++ ++/* AP Subsystem */ ++#define TH1520_RESET_ID_BROM 0 ++#define TH1520_RESET_ID_C910_TOP 1 ++#define TH1520_RESET_ID_NPU 2 ++#define TH1520_RESET_ID_WDT0 3 ++#define TH1520_RESET_ID_WDT1 4 ++#define TH1520_RESET_ID_C910_C0 5 ++#define TH1520_RESET_ID_C910_C1 6 ++#define TH1520_RESET_ID_C910_C2 7 ++#define TH1520_RESET_ID_C910_C3 8 ++#define TH1520_RESET_ID_CHIP_DBG_CORE 9 ++#define TH1520_RESET_ID_CHIP_DBG_AXI 10 ++#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI 11 ++#define TH1520_RESET_ID_AXI4_CPUSYS2_APB 12 ++#define TH1520_RESET_ID_X2H_CPUSYS 13 ++#define TH1520_RESET_ID_AHB2_CPUSYS 14 ++#define TH1520_RESET_ID_APB3_CPUSYS 15 ++#define TH1520_RESET_ID_MBOX0_APB 16 ++#define TH1520_RESET_ID_MBOX1_APB 17 ++#define TH1520_RESET_ID_MBOX2_APB 18 ++#define TH1520_RESET_ID_MBOX3_APB 19 ++#define TH1520_RESET_ID_TIMER0_APB 20 ++#define TH1520_RESET_ID_TIMER0_CORE 21 ++#define TH1520_RESET_ID_TIMER1_APB 22 ++#define TH1520_RESET_ID_TIMER1_CORE 23 ++#define TH1520_RESET_ID_PERISYS_AHB 24 ++#define TH1520_RESET_ID_PERISYS_APB1 25 ++#define TH1520_RESET_ID_PERISYS_APB2 26 ++#define TH1520_RESET_ID_GMAC0_APB 27 ++#define TH1520_RESET_ID_GMAC0_AHB 28 ++#define TH1520_RESET_ID_GMAC0_CLKGEN 29 ++#define TH1520_RESET_ID_GMAC0_AXI 30 ++#define TH1520_RESET_ID_UART0_APB 31 ++#define TH1520_RESET_ID_UART0_IF 32 ++#define TH1520_RESET_ID_UART1_APB 33 ++#define TH1520_RESET_ID_UART1_IF 34 ++#define TH1520_RESET_ID_UART2_APB 35 ++#define TH1520_RESET_ID_UART2_IF 36 ++#define TH1520_RESET_ID_UART3_APB 37 ++#define TH1520_RESET_ID_UART3_IF 38 ++#define TH1520_RESET_ID_UART4_APB 39 ++#define TH1520_RESET_ID_UART4_IF 40 ++#define TH1520_RESET_ID_UART5_APB 41 ++#define TH1520_RESET_ID_UART5_IF 42 ++#define TH1520_RESET_ID_QSPI0_IF 43 ++#define TH1520_RESET_ID_QSPI0_APB 44 ++#define TH1520_RESET_ID_QSPI1_IF 45 ++#define TH1520_RESET_ID_QSPI1_APB 46 ++#define TH1520_RESET_ID_SPI_IF 47 ++#define TH1520_RESET_ID_SPI_APB 48 ++#define TH1520_RESET_ID_I2C0_APB 49 ++#define TH1520_RESET_ID_I2C0_CORE 50 ++#define TH1520_RESET_ID_I2C1_APB 51 ++#define TH1520_RESET_ID_I2C1_CORE 52 ++#define TH1520_RESET_ID_I2C2_APB 53 ++#define TH1520_RESET_ID_I2C2_CORE 54 ++#define TH1520_RESET_ID_I2C3_APB 55 ++#define TH1520_RESET_ID_I2C3_CORE 56 ++#define TH1520_RESET_ID_I2C4_APB 57 ++#define TH1520_RESET_ID_I2C4_CORE 58 ++#define TH1520_RESET_ID_I2C5_APB 59 ++#define TH1520_RESET_ID_I2C5_CORE 60 ++#define TH1520_RESET_ID_GPIO0_DB 61 ++#define TH1520_RESET_ID_GPIO0_APB 62 ++#define TH1520_RESET_ID_GPIO1_DB 63 ++#define TH1520_RESET_ID_GPIO1_APB 64 ++#define TH1520_RESET_ID_GPIO2_DB 65 ++#define TH1520_RESET_ID_GPIO2_APB 66 ++#define TH1520_RESET_ID_PWM_COUNTER 67 ++#define TH1520_RESET_ID_PWM_APB 68 ++#define TH1520_RESET_ID_PADCTRL0_APB 69 ++#define TH1520_RESET_ID_CPU2PERI_X2H 70 ++#define TH1520_RESET_ID_CPU2AON_X2H 71 ++#define TH1520_RESET_ID_AON2CPU_A2X 72 ++#define TH1520_RESET_ID_NPUSYS_AXI 73 ++#define TH1520_RESET_ID_NPUSYS_AXI_APB 74 ++#define TH1520_RESET_ID_CPU2VP_X2P 75 ++#define TH1520_RESET_ID_CPU2VI_X2H 76 ++#define TH1520_RESET_ID_BMU_AXI 77 ++#define TH1520_RESET_ID_BMU_APB 78 ++#define TH1520_RESET_ID_DMAC_CPUSYS_AXI 79 ++#define TH1520_RESET_ID_DMAC_CPUSYS_AHB 80 ++#define TH1520_RESET_ID_SPINLOCK 81 ++#define TH1520_RESET_ID_CFG2TEE 82 ++#define TH1520_RESET_ID_DSMART 83 ++#define TH1520_RESET_ID_GPIO3_DB 84 ++#define TH1520_RESET_ID_GPIO3_APB 85 ++#define TH1520_RESET_ID_PERI_I2S 86 ++#define TH1520_RESET_ID_PERI_APB3 87 ++#define TH1520_RESET_ID_PERI2PERI1_APB 88 ++#define TH1520_RESET_ID_VPSYS_APB 89 ++#define TH1520_RESET_ID_PERISYS_APB4 90 ++#define TH1520_RESET_ID_GMAC1_APB 91 ++#define TH1520_RESET_ID_GMAC1_AHB 92 ++#define TH1520_RESET_ID_GMAC1_CLKGEN 93 ++#define TH1520_RESET_ID_GMAC1_AXI 94 ++#define TH1520_RESET_ID_GMAC_AXI 95 ++#define TH1520_RESET_ID_GMAC_AXI_APB 96 ++#define TH1520_RESET_ID_PADCTRL1_APB 97 ++#define TH1520_RESET_ID_VOSYS_AXI 98 ++#define TH1520_RESET_ID_VOSYS_AXI_APB 99 ++#define TH1520_RESET_ID_VOSYS_AXI_X2X 100 ++#define TH1520_RESET_ID_MISC2VP_X2X 101 ++#define TH1520_RESET_ID_DSPSYS 102 ++#define TH1520_RESET_ID_VISYS 103 ++#define TH1520_RESET_ID_VOSYS 104 ++#define TH1520_RESET_ID_VPSYS 105 ++ ++/* DSP Subsystem */ ++#define TH1520_RESET_ID_X2X_DSP1 0 ++#define TH1520_RESET_ID_X2X_DSP0 1 ++#define TH1520_RESET_ID_X2X_SLAVE_DSP1 2 ++#define TH1520_RESET_ID_X2X_SLAVE_DSP0 3 ++#define TH1520_RESET_ID_DSP0_CORE 4 ++#define TH1520_RESET_ID_DSP0_DEBUG 5 ++#define TH1520_RESET_ID_DSP0_APB 6 ++#define TH1520_RESET_ID_DSP1_CORE 7 ++#define TH1520_RESET_ID_DSP1_DEBUG 8 ++#define TH1520_RESET_ID_DSP1_APB 9 ++#define TH1520_RESET_ID_DSPSYS_APB 10 ++#define TH1520_RESET_ID_AXI4_DSPSYS_SLV 11 ++#define TH1520_RESET_ID_AXI4_DSPSYS 12 ++#define TH1520_RESET_ID_AXI4_DSP_RS 13 ++ ++/* MISC Subsystem */ ++#define TH1520_RESET_ID_EMMC_SDIO_CLKGEN 0 ++#define TH1520_RESET_ID_EMMC 1 ++#define TH1520_RESET_ID_MISCSYS_AXI 2 ++#define TH1520_RESET_ID_MISCSYS_AXI_APB 3 ++#define TH1520_RESET_ID_SDIO0 4 ++#define TH1520_RESET_ID_SDIO1 5 ++#define TH1520_RESET_ID_USB3_APB 6 ++#define TH1520_RESET_ID_USB3_PHY 7 ++#define TH1520_RESET_ID_USB3_VCC 8 ++ ++/* VI Subsystem */ ++#define TH1520_RESET_ID_ISP0 0 ++#define TH1520_RESET_ID_ISP1 1 ++#define TH1520_RESET_ID_CSI0_APB 2 ++#define TH1520_RESET_ID_CSI1_APB 3 ++#define TH1520_RESET_ID_CSI2_APB 4 ++#define TH1520_RESET_ID_MIPI_FIFO 5 ++#define TH1520_RESET_ID_ISP_VENC_APB 6 ++#define TH1520_RESET_ID_VIPRE_APB 7 ++#define TH1520_RESET_ID_VIPRE_AXI 8 ++#define TH1520_RESET_ID_DW200_APB 9 ++#define TH1520_RESET_ID_VISYS3_AXI 10 ++#define TH1520_RESET_ID_VISYS2_AXI 11 ++#define TH1520_RESET_ID_VISYS1_AXI 12 ++#define TH1520_RESET_ID_VISYS_AXI 13 ++#define TH1520_RESET_ID_VISYS_APB 14 ++#define TH1520_RESET_ID_ISP_VENC_AXI 15 ++ ++/* VO Subsystem */ + #define TH1520_RESET_ID_GPU 0 + #define TH1520_RESET_ID_GPU_CLKGEN 1 + #define TH1520_RESET_ID_DPU_AHB 5 +@@ -16,5 +210,27 @@ + #define TH1520_RESET_ID_DSI1_APB 9 + #define TH1520_RESET_ID_HDMI 10 + #define TH1520_RESET_ID_HDMI_APB 11 ++#define TH1520_RESET_ID_VOAXI 12 ++#define TH1520_RESET_ID_VOAXI_APB 13 ++#define TH1520_RESET_ID_X2H_DPU_AXI 14 ++#define TH1520_RESET_ID_X2H_DPU_AHB 15 ++#define TH1520_RESET_ID_X2H_DPU1_AXI 16 ++#define TH1520_RESET_ID_X2H_DPU1_AHB 17 ++ ++/* VP Subsystem */ ++#define TH1520_RESET_ID_VPSYS_AXI_APB 0 ++#define TH1520_RESET_ID_VPSYS_AXI 1 ++#define TH1520_RESET_ID_FCE_APB 2 ++#define TH1520_RESET_ID_FCE_CORE 3 ++#define TH1520_RESET_ID_FCE_X2X_MASTER 4 ++#define TH1520_RESET_ID_FCE_X2X_SLAVE 5 ++#define TH1520_RESET_ID_G2D_APB 6 ++#define TH1520_RESET_ID_G2D_ACLK 7 ++#define TH1520_RESET_ID_G2D_CORE 8 ++#define TH1520_RESET_ID_VDEC_APB 9 ++#define TH1520_RESET_ID_VDEC_ACLK 10 ++#define TH1520_RESET_ID_VDEC_CORE 11 ++#define TH1520_RESET_ID_VENC_APB 12 ++#define TH1520_RESET_ID_VENC_CORE 13 + + #endif /* _DT_BINDINGS_TH1520_RESET_H */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0255-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch b/SPECS/linux-lts/0255-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch deleted file mode 100644 index 1e9bf3e407..0000000000 --- a/SPECS/linux-lts/0255-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch +++ /dev/null @@ -1,38 +0,0 @@ -From ef5e4c0292bbb0c8ac2209001b6adcdb0ee1fc37 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Wed, 29 Apr 2026 09:38:48 +0800 -Subject: [PATCH 255/467] UPSTREAM: ASoC: spacemit: adjust FIFO trigger - threshold to half FIFO size - -Set both TX and RX FIFO trigger thresholds (TFT/RFT) to 0xF (half of -the 32-entry FIFO) instead of 5. This provides better DMA efficiency -by allowing more data to accumulate before triggering a DMA request, -reducing the number of DMA transactions needed. - -Signed-off-by: Troy Mitchell -Link: https://patch.msgid.link/20260429-k3-i2s-v1-3-2fe99db11ecb@linux.spacemit.com -Signed-off-by: Mark Brown -(cherry picked from commit 03dcb5b68a96b51157ec2d17042fa2f0106828ae) -Signed-off-by: Han Gao ---- - sound/soc/spacemit/k1_i2s.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c -index 331668b979fd..b48c57bede37 100644 ---- a/sound/soc/spacemit/k1_i2s.c -+++ b/sound/soc/spacemit/k1_i2s.c -@@ -93,8 +93,8 @@ static void spacemit_i2s_init(struct spacemit_i2s_dev *i2s) - u32 sscr_val, sspsp_val, ssfcr_val, ssrwt_val; - - sscr_val = SSCR_TRAIL | SSCR_FRF_PSP; -- ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 5) | -- FIELD_PREP(SSFCR_FIELD_RFT, 5) | -+ ssfcr_val = FIELD_PREP(SSFCR_FIELD_TFT, 0xF) | -+ FIELD_PREP(SSFCR_FIELD_RFT, 0xF) | - SSFCR_RSRE | SSFCR_TSRE; - ssrwt_val = SSRWT_RWOT; - sspsp_val = SSPSP_SFRMP; --- -2.53.0 - diff --git a/SPECS/linux-lts/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch b/SPECS/linux-lts/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch new file mode 100644 index 0000000000..46e0cf3948 --- /dev/null +++ b/SPECS/linux-lts/0255-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch @@ -0,0 +1,124 @@ +From 822ec8590fdd9c6e8152814eca6d64a56660f962 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 14 Oct 2025 13:10:30 +0000 +Subject: [RUYI PATCH] UPSTREAM: reset: th1520: Prepare for supporting multiple + controllers + +TH1520 SoC is divided into several subsystems, shipping distinct reset +controllers with similar control logic. Let's make reset signal mapping +a data structure specific to one compatible to prepare for introduction +of more reset controllers in the future. + +Signed-off-by: Yao Zi +Acked-by: Guo Ren +Reviewed-by: Drew Fustini +Signed-off-by: Philipp Zabel +(cherry picked from commit 0040d9eac391bacefcb0c748cf32c8fe5900b13b) +Signed-off-by: Han Gao +--- + drivers/reset/reset-th1520.c | 42 +++++++++++++++++++++++++----------- + 1 file changed, 30 insertions(+), 12 deletions(-) + +diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c +index 14d964a9c6b6..2b65a95ed021 100644 +--- a/drivers/reset/reset-th1520.c ++++ b/drivers/reset/reset-th1520.c +@@ -29,14 +29,20 @@ + #define TH1520_HDMI_SW_MAIN_RST BIT(0) + #define TH1520_HDMI_SW_PRST BIT(1) + ++struct th1520_reset_map { ++ u32 bit; ++ u32 reg; ++}; ++ + struct th1520_reset_priv { + struct reset_controller_dev rcdev; + struct regmap *map; ++ const struct th1520_reset_map *resets; + }; + +-struct th1520_reset_map { +- u32 bit; +- u32 reg; ++struct th1520_reset_data { ++ const struct th1520_reset_map *resets; ++ size_t num; + }; + + static const struct th1520_reset_map th1520_resets[] = { +@@ -90,7 +96,7 @@ static int th1520_reset_assert(struct reset_controller_dev *rcdev, + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); + const struct th1520_reset_map *reset; + +- reset = &th1520_resets[id]; ++ reset = &priv->resets[id]; + + return regmap_update_bits(priv->map, reset->reg, reset->bit, 0); + } +@@ -101,7 +107,7 @@ static int th1520_reset_deassert(struct reset_controller_dev *rcdev, + struct th1520_reset_priv *priv = to_th1520_reset(rcdev); + const struct th1520_reset_map *reset; + +- reset = &th1520_resets[id]; ++ reset = &priv->resets[id]; + + return regmap_update_bits(priv->map, reset->reg, reset->bit, + reset->bit); +@@ -120,11 +126,14 @@ static const struct regmap_config th1520_reset_regmap_config = { + + static int th1520_reset_probe(struct platform_device *pdev) + { ++ const struct th1520_reset_data *data; + struct device *dev = &pdev->dev; + struct th1520_reset_priv *priv; + void __iomem *base; + int ret; + ++ data = device_get_match_data(dev); ++ + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; +@@ -138,22 +147,31 @@ static int th1520_reset_probe(struct platform_device *pdev) + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + +- /* Initialize GPU resets to asserted state */ +- ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, +- TH1520_GPU_RST_CFG_MASK, 0); +- if (ret) +- return ret; ++ if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) { ++ /* Initialize GPU resets to asserted state */ ++ ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, ++ TH1520_GPU_RST_CFG_MASK, 0); ++ if (ret) ++ return ret; ++ } + + priv->rcdev.owner = THIS_MODULE; +- priv->rcdev.nr_resets = ARRAY_SIZE(th1520_resets); ++ priv->rcdev.nr_resets = data->num; + priv->rcdev.ops = &th1520_reset_ops; + priv->rcdev.of_node = dev->of_node; + ++ priv->resets = data->resets; ++ + return devm_reset_controller_register(dev, &priv->rcdev); + } + ++static const struct th1520_reset_data th1520_reset_data = { ++ .resets = th1520_resets, ++ .num = ARRAY_SIZE(th1520_resets), ++}; ++ + static const struct of_device_id th1520_reset_match[] = { +- { .compatible = "thead,th1520-reset" }, ++ { .compatible = "thead,th1520-reset", .data = &th1520_reset_data }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, th1520_reset_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0256-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch b/SPECS/linux-lts/0256-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch deleted file mode 100644 index 069e0e55c6..0000000000 --- a/SPECS/linux-lts/0256-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Remove.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 70c964d224ef054526b245c614230ab634b0bde7 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Tue, 14 Oct 2025 13:10:28 +0000 -Subject: [PATCH 256/467] UPSTREAM: dt-bindings: reset: thead,th1520-reset: - Remove non-VO-subsystem resets - -Registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} belong to AP -reset controller, not the VO one which is documented as -"thead,th1520-reset" and is the only reset controller supported for -TH1520 for now. - -Let's remove the IDs, leaving them to be implemented by AP-subsystem -reset controller in the future. - -Fixes: 30e7573babdc ("dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller") -Signed-off-by: Yao Zi -Acked-by: Rob Herring (Arm) -Reviewed-by: Drew Fustini -Acked-by: Guo Ren -Signed-off-by: Philipp Zabel -(cherry picked from commit 5334eb9de76c74e24821aae89e111e27398b5add) -Signed-off-by: Han Gao ---- - include/dt-bindings/reset/thead,th1520-reset.h | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h -index ee799286c175..e51d6314d131 100644 ---- a/include/dt-bindings/reset/thead,th1520-reset.h -+++ b/include/dt-bindings/reset/thead,th1520-reset.h -@@ -9,9 +9,6 @@ - - #define TH1520_RESET_ID_GPU 0 - #define TH1520_RESET_ID_GPU_CLKGEN 1 --#define TH1520_RESET_ID_NPU 2 --#define TH1520_RESET_ID_WDT0 3 --#define TH1520_RESET_ID_WDT1 4 - #define TH1520_RESET_ID_DPU_AHB 5 - #define TH1520_RESET_ID_DPU_AXI 6 - #define TH1520_RESET_ID_DPU_CORE 7 --- -2.53.0 - diff --git a/SPECS/linux-lts/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch b/SPECS/linux-lts/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch new file mode 100644 index 0000000000..7a6c0e9f96 --- /dev/null +++ b/SPECS/linux-lts/0256-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch @@ -0,0 +1,856 @@ +From 34aaa4adc6171c1a972e81edbb9861406d7dfa83 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 14 Oct 2025 13:10:31 +0000 +Subject: [RUYI PATCH] UPSTREAM: reset: th1520: Support reset controllers in + more subsystems + +Introduce reset controllers for AP, MISC, VI, VP and DSP subsystems and +add their reset signal mappings. + +Signed-off-by: Yao Zi +Reviewed-by: Drew Fustini +Acked-by: Guo Ren +Signed-off-by: Philipp Zabel +(cherry picked from commit da91533c2b7a569b272b8271f0b2c407f86407ed) +Signed-off-by: Han Gao +--- + drivers/reset/reset-th1520.c | 793 +++++++++++++++++++++++++++++++++++ + 1 file changed, 793 insertions(+) + +diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c +index 2b65a95ed021..fd32e991c4cb 100644 +--- a/drivers/reset/reset-th1520.c ++++ b/drivers/reset/reset-th1520.c +@@ -11,6 +11,85 @@ + + #include + ++ /* register offset in RSTGEN_R */ ++#define TH1520_BROM_RST_CFG 0x0 ++#define TH1520_C910_RST_CFG 0x4 ++#define TH1520_CHIP_DBG_RST_CFG 0xc ++#define TH1520_AXI4_CPUSYS2_RST_CFG 0x10 ++#define TH1520_X2H_CPUSYS_RST_CFG 0x18 ++#define TH1520_AHB2_CPUSYS_RST_CFG 0x1c ++#define TH1520_APB3_CPUSYS_RST_CFG 0x20 ++#define TH1520_MBOX0_RST_CFG 0x24 ++#define TH1520_MBOX1_RST_CFG 0x28 ++#define TH1520_MBOX2_RST_CFG 0x2c ++#define TH1520_MBOX3_RST_CFG 0x30 ++#define TH1520_WDT0_RST_CFG 0x34 ++#define TH1520_WDT1_RST_CFG 0x38 ++#define TH1520_TIMER0_RST_CFG 0x3c ++#define TH1520_TIMER1_RST_CFG 0x40 ++#define TH1520_PERISYS_AHB_RST_CFG 0x44 ++#define TH1520_PERISYS_APB1_RST_CFG 0x48 ++#define TH1520_PERISYS_APB2_RST_CFG 0x4c ++#define TH1520_GMAC0_RST_CFG 0x68 ++#define TH1520_UART0_RST_CFG 0x70 ++#define TH1520_UART1_RST_CFG 0x74 ++#define TH1520_UART2_RST_CFG 0x78 ++#define TH1520_UART3_RST_CFG 0x7c ++#define TH1520_UART4_RST_CFG 0x80 ++#define TH1520_UART5_RST_CFG 0x84 ++#define TH1520_QSPI0_RST_CFG 0x8c ++#define TH1520_QSPI1_RST_CFG 0x90 ++#define TH1520_SPI_RST_CFG 0x94 ++#define TH1520_I2C0_RST_CFG 0x98 ++#define TH1520_I2C1_RST_CFG 0x9c ++#define TH1520_I2C2_RST_CFG 0xa0 ++#define TH1520_I2C3_RST_CFG 0xa4 ++#define TH1520_I2C4_RST_CFG 0xa8 ++#define TH1520_I2C5_RST_CFG 0xac ++#define TH1520_GPIO0_RST_CFG 0xb0 ++#define TH1520_GPIO1_RST_CFG 0xb4 ++#define TH1520_GPIO2_RST_CFG 0xb8 ++#define TH1520_PWM_RST_CFG 0xc0 ++#define TH1520_PADCTRL0_APSYS_RST_CFG 0xc4 ++#define TH1520_CPU2PERI_X2H_RST_CFG 0xcc ++#define TH1520_CPU2AON_X2H_RST_CFG 0xe4 ++#define TH1520_AON2CPU_A2X_RST_CFG 0xfc ++#define TH1520_NPUSYS_AXI_RST_CFG 0x128 ++#define TH1520_CPU2VP_X2P_RST_CFG 0x12c ++#define TH1520_CPU2VI_X2H_RST_CFG 0x138 ++#define TH1520_BMU_C910_RST_CFG 0x148 ++#define TH1520_DMAC_CPUSYS_RST_CFG 0x14c ++#define TH1520_SPINLOCK_RST_CFG 0x178 ++#define TH1520_CFG2TEE_X2H_RST_CFG 0x188 ++#define TH1520_DSMART_RST_CFG 0x18c ++#define TH1520_GPIO3_RST_CFG 0x1a8 ++#define TH1520_I2S_RST_CFG 0x1ac ++#define TH1520_IMG_NNA_RST_CFG 0x1b0 ++#define TH1520_PERI_APB3_RST_CFG 0x1dc ++#define TH1520_VP_SUBSYS_RST_CFG 0x1ec ++#define TH1520_PERISYS_APB4_RST_CFG 0x1f8 ++#define TH1520_GMAC1_RST_CFG 0x204 ++#define TH1520_GMAC_AXI_RST_CFG 0x208 ++#define TH1520_PADCTRL1_APSYS_RST_CFG 0x20c ++#define TH1520_VOSYS_AXI_RST_CFG 0x210 ++#define TH1520_VOSYS_X2X_RST_CFG 0x214 ++#define TH1520_MISC2VP_X2X_RST_CFG 0x218 ++#define TH1520_SUBSYS_RST_CFG 0x220 ++ ++ /* register offset in DSP_REGMAP */ ++#define TH1520_DSPSYS_RST_CFG 0x0 ++ ++ /* register offset in MISCSYS_REGMAP */ ++#define TH1520_EMMC_RST_CFG 0x0 ++#define TH1520_MISCSYS_AXI_RST_CFG 0x8 ++#define TH1520_SDIO0_RST_CFG 0xc ++#define TH1520_SDIO1_RST_CFG 0x10 ++#define TH1520_USB3_DRD_RST_CFG 0x14 ++ ++ /* register offset in VISYS_REGMAP */ ++#define TH1520_VISYS_RST_CFG 0x0 ++#define TH1520_VISYS_2_RST_CFG 0x4 ++ + /* register offset in VOSYS_REGMAP */ + #define TH1520_GPU_RST_CFG 0x0 + #define TH1520_GPU_RST_CFG_MASK GENMASK(1, 0) +@@ -18,6 +97,8 @@ + #define TH1520_DSI0_RST_CFG 0x8 + #define TH1520_DSI1_RST_CFG 0xc + #define TH1520_HDMI_RST_CFG 0x14 ++#define TH1520_AXI4_VO_DW_AXI_RST_CFG 0x18 ++#define TH1520_X2H_X4_VOSYS_DW_RST_CFG 0x20 + + /* register values */ + #define TH1520_GPU_SW_GPU_RST BIT(0) +@@ -29,6 +110,13 @@ + #define TH1520_HDMI_SW_MAIN_RST BIT(0) + #define TH1520_HDMI_SW_PRST BIT(1) + ++ /* register offset in VPSYS_REGMAP */ ++#define TH1520_AXIBUS_RST_CFG 0x0 ++#define TH1520_FCE_RST_CFG 0x4 ++#define TH1520_G2D_RST_CFG 0x8 ++#define TH1520_VDEC_RST_CFG 0xc ++#define TH1520_VENC_RST_CFG 0x10 ++ + struct th1520_reset_map { + u32 bit; + u32 reg; +@@ -82,6 +170,681 @@ static const struct th1520_reset_map th1520_resets[] = { + .bit = TH1520_HDMI_SW_PRST, + .reg = TH1520_HDMI_RST_CFG, + }, ++ [TH1520_RESET_ID_VOAXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VOAXI_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2H_DPU_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2H_DPU_AHB] = { ++ .bit = BIT(1), ++ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2H_DPU1_AXI] = { ++ .bit = BIT(2), ++ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2H_DPU1_AHB] = { ++ .bit = BIT(3), ++ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, ++ }, ++}; ++ ++static const struct th1520_reset_map th1520_ap_resets[] = { ++ [TH1520_RESET_ID_BROM] = { ++ .bit = BIT(0), ++ .reg = TH1520_BROM_RST_CFG, ++ }, ++ [TH1520_RESET_ID_C910_TOP] = { ++ .bit = BIT(0), ++ .reg = TH1520_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_NPU] = { ++ .bit = BIT(0), ++ .reg = TH1520_IMG_NNA_RST_CFG, ++ }, ++ [TH1520_RESET_ID_WDT0] = { ++ .bit = BIT(0), ++ .reg = TH1520_WDT0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_WDT1] = { ++ .bit = BIT(0), ++ .reg = TH1520_WDT1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_C910_C0] = { ++ .bit = BIT(1), ++ .reg = TH1520_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_C910_C1] = { ++ .bit = BIT(2), ++ .reg = TH1520_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_C910_C2] = { ++ .bit = BIT(3), ++ .reg = TH1520_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_C910_C3] = { ++ .bit = BIT(4), ++ .reg = TH1520_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CHIP_DBG_CORE] = { ++ .bit = BIT(0), ++ .reg = TH1520_CHIP_DBG_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CHIP_DBG_AXI] = { ++ .bit = BIT(1), ++ .reg = TH1520_CHIP_DBG_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AXI4_CPUSYS2_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_AXI4_CPUSYS2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AXI4_CPUSYS2_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_AXI4_CPUSYS2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2H_CPUSYS] = { ++ .bit = BIT(0), ++ .reg = TH1520_X2H_CPUSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AHB2_CPUSYS] = { ++ .bit = BIT(0), ++ .reg = TH1520_AHB2_CPUSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_APB3_CPUSYS] = { ++ .bit = BIT(0), ++ .reg = TH1520_APB3_CPUSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MBOX0_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_MBOX0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MBOX1_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_MBOX1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MBOX2_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_MBOX2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MBOX3_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_MBOX3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_TIMER0_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_TIMER0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_TIMER0_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_TIMER0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_TIMER1_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_TIMER1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_TIMER1_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_TIMER1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERISYS_AHB] = { ++ .bit = BIT(0), ++ .reg = TH1520_PERISYS_AHB_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERISYS_APB1] = { ++ .bit = BIT(0), ++ .reg = TH1520_PERISYS_APB1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERISYS_APB2] = { ++ .bit = BIT(0), ++ .reg = TH1520_PERISYS_APB2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC0_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_GMAC0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC0_AHB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GMAC0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC0_CLKGEN] = { ++ .bit = BIT(2), ++ .reg = TH1520_GMAC0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC0_AXI] = { ++ .bit = BIT(3), ++ .reg = TH1520_GMAC0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART0_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_UART0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART0_IF] = { ++ .bit = BIT(1), ++ .reg = TH1520_UART0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART1_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_UART1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART1_IF] = { ++ .bit = BIT(1), ++ .reg = TH1520_UART1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART2_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_UART2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART2_IF] = { ++ .bit = BIT(1), ++ .reg = TH1520_UART2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART3_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_UART3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART3_IF] = { ++ .bit = BIT(1), ++ .reg = TH1520_UART3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART4_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_UART4_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART4_IF] = { ++ .bit = BIT(1), ++ .reg = TH1520_UART4_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART5_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_UART5_RST_CFG, ++ }, ++ [TH1520_RESET_ID_UART5_IF] = { ++ .bit = BIT(1), ++ .reg = TH1520_UART5_RST_CFG, ++ }, ++ [TH1520_RESET_ID_QSPI0_IF] = { ++ .bit = BIT(0), ++ .reg = TH1520_QSPI0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_QSPI0_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_QSPI0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_QSPI1_IF] = { ++ .bit = BIT(0), ++ .reg = TH1520_QSPI1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_QSPI1_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_QSPI1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_SPI_IF] = { ++ .bit = BIT(0), ++ .reg = TH1520_SPI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_SPI_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_SPI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C0_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2C0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C0_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_I2C0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C1_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2C1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C1_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_I2C1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C2_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2C2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C2_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_I2C2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C3_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2C3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C3_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_I2C3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C4_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2C4_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C4_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_I2C4_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C5_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2C5_RST_CFG, ++ }, ++ [TH1520_RESET_ID_I2C5_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_I2C5_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO0_DB] = { ++ .bit = BIT(0), ++ .reg = TH1520_GPIO0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO0_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GPIO0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO1_DB] = { ++ .bit = BIT(0), ++ .reg = TH1520_GPIO1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO1_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GPIO1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO2_DB] = { ++ .bit = BIT(0), ++ .reg = TH1520_GPIO2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO2_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GPIO2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PWM_COUNTER] = { ++ .bit = BIT(0), ++ .reg = TH1520_PWM_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PWM_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_PWM_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PADCTRL0_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_PADCTRL0_APSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CPU2PERI_X2H] = { ++ .bit = BIT(1), ++ .reg = TH1520_CPU2PERI_X2H_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CPU2AON_X2H] = { ++ .bit = BIT(0), ++ .reg = TH1520_CPU2AON_X2H_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AON2CPU_A2X] = { ++ .bit = BIT(0), ++ .reg = TH1520_AON2CPU_A2X_RST_CFG, ++ }, ++ [TH1520_RESET_ID_NPUSYS_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_NPUSYS_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_NPUSYS_AXI_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_NPUSYS_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CPU2VP_X2P] = { ++ .bit = BIT(0), ++ .reg = TH1520_CPU2VP_X2P_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CPU2VI_X2H] = { ++ .bit = BIT(0), ++ .reg = TH1520_CPU2VI_X2H_RST_CFG, ++ }, ++ [TH1520_RESET_ID_BMU_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_BMU_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_BMU_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_BMU_C910_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DMAC_CPUSYS_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_DMAC_CPUSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DMAC_CPUSYS_AHB] = { ++ .bit = BIT(1), ++ .reg = TH1520_DMAC_CPUSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_SPINLOCK] = { ++ .bit = BIT(0), ++ .reg = TH1520_SPINLOCK_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CFG2TEE] = { ++ .bit = BIT(0), ++ .reg = TH1520_CFG2TEE_X2H_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSMART] = { ++ .bit = BIT(0), ++ .reg = TH1520_DSMART_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO3_DB] = { ++ .bit = BIT(0), ++ .reg = TH1520_GPIO3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GPIO3_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GPIO3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERI_I2S] = { ++ .bit = BIT(0), ++ .reg = TH1520_I2S_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERI_APB3] = { ++ .bit = BIT(0), ++ .reg = TH1520_PERI_APB3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERI2PERI1_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_PERI_APB3_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VPSYS_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_VP_SUBSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PERISYS_APB4] = { ++ .bit = BIT(0), ++ .reg = TH1520_PERISYS_APB4_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC1_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_GMAC1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC1_AHB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GMAC1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC1_CLKGEN] = { ++ .bit = BIT(2), ++ .reg = TH1520_GMAC1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC1_AXI] = { ++ .bit = BIT(3), ++ .reg = TH1520_GMAC1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_GMAC_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_GMAC_AXI_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_GMAC_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_PADCTRL1_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_PADCTRL1_APSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VOSYS_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_VOSYS_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VOSYS_AXI_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_VOSYS_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VOSYS_AXI_X2X] = { ++ .bit = BIT(0), ++ .reg = TH1520_VOSYS_X2X_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MISC2VP_X2X] = { ++ .bit = BIT(0), ++ .reg = TH1520_MISC2VP_X2X_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSPSYS] = { ++ .bit = BIT(0), ++ .reg = TH1520_SUBSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VISYS] = { ++ .bit = BIT(1), ++ .reg = TH1520_SUBSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VOSYS] = { ++ .bit = BIT(2), ++ .reg = TH1520_SUBSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VPSYS] = { ++ .bit = BIT(3), ++ .reg = TH1520_SUBSYS_RST_CFG, ++ }, ++}; ++ ++static const struct th1520_reset_map th1520_dsp_resets[] = { ++ [TH1520_RESET_ID_X2X_DSP1] = { ++ .bit = BIT(0), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2X_DSP0] = { ++ .bit = BIT(1), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2X_SLAVE_DSP1] = { ++ .bit = BIT(2), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_X2X_SLAVE_DSP0] = { ++ .bit = BIT(3), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSP0_CORE] = { ++ .bit = BIT(8), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSP0_DEBUG] = { ++ .bit = BIT(9), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSP0_APB] = { ++ .bit = BIT(10), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSP1_CORE] = { ++ .bit = BIT(12), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSP1_DEBUG] = { ++ .bit = BIT(13), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSP1_APB] = { ++ .bit = BIT(14), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DSPSYS_APB] = { ++ .bit = BIT(16), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AXI4_DSPSYS_SLV] = { ++ .bit = BIT(20), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AXI4_DSPSYS] = { ++ .bit = BIT(24), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_AXI4_DSP_RS] = { ++ .bit = BIT(26), ++ .reg = TH1520_DSPSYS_RST_CFG, ++ }, ++}; ++ ++static const struct th1520_reset_map th1520_misc_resets[] = { ++ [TH1520_RESET_ID_EMMC_SDIO_CLKGEN] = { ++ .bit = BIT(0), ++ .reg = TH1520_EMMC_RST_CFG, ++ }, ++ [TH1520_RESET_ID_EMMC] = { ++ .bit = BIT(1), ++ .reg = TH1520_EMMC_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MISCSYS_AXI] = { ++ .bit = BIT(0), ++ .reg = TH1520_MISCSYS_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MISCSYS_AXI_APB] = { ++ .bit = BIT(1), ++ .reg = TH1520_MISCSYS_AXI_RST_CFG, ++ }, ++ [TH1520_RESET_ID_SDIO0] = { ++ .bit = BIT(0), ++ .reg = TH1520_SDIO0_RST_CFG, ++ }, ++ [TH1520_RESET_ID_SDIO1] = { ++ .bit = BIT(1), ++ .reg = TH1520_SDIO1_RST_CFG, ++ }, ++ [TH1520_RESET_ID_USB3_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_USB3_DRD_RST_CFG, ++ }, ++ [TH1520_RESET_ID_USB3_PHY] = { ++ .bit = BIT(1), ++ .reg = TH1520_USB3_DRD_RST_CFG, ++ }, ++ [TH1520_RESET_ID_USB3_VCC] = { ++ .bit = BIT(2), ++ .reg = TH1520_USB3_DRD_RST_CFG, ++ }, ++}; ++ ++static const struct th1520_reset_map th1520_vi_resets[] = { ++ [TH1520_RESET_ID_ISP0] = { ++ .bit = BIT(0), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_ISP1] = { ++ .bit = BIT(4), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CSI0_APB] = { ++ .bit = BIT(16), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CSI1_APB] = { ++ .bit = BIT(17), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_CSI2_APB] = { ++ .bit = BIT(18), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_MIPI_FIFO] = { ++ .bit = BIT(20), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_ISP_VENC_APB] = { ++ .bit = BIT(24), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VIPRE_APB] = { ++ .bit = BIT(28), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VIPRE_AXI] = { ++ .bit = BIT(29), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_DW200_APB] = { ++ .bit = BIT(31), ++ .reg = TH1520_VISYS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VISYS3_AXI] = { ++ .bit = BIT(8), ++ .reg = TH1520_VISYS_2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VISYS2_AXI] = { ++ .bit = BIT(9), ++ .reg = TH1520_VISYS_2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VISYS1_AXI] = { ++ .bit = BIT(10), ++ .reg = TH1520_VISYS_2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VISYS_AXI] = { ++ .bit = BIT(12), ++ .reg = TH1520_VISYS_2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VISYS_APB] = { ++ .bit = BIT(16), ++ .reg = TH1520_VISYS_2_RST_CFG, ++ }, ++ [TH1520_RESET_ID_ISP_VENC_AXI] = { ++ .bit = BIT(20), ++ .reg = TH1520_VISYS_2_RST_CFG, ++ }, ++}; ++ ++static const struct th1520_reset_map th1520_vp_resets[] = { ++ [TH1520_RESET_ID_VPSYS_AXI_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_AXIBUS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VPSYS_AXI] = { ++ .bit = BIT(1), ++ .reg = TH1520_AXIBUS_RST_CFG, ++ }, ++ [TH1520_RESET_ID_FCE_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_FCE_RST_CFG, ++ }, ++ [TH1520_RESET_ID_FCE_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_FCE_RST_CFG, ++ }, ++ [TH1520_RESET_ID_FCE_X2X_MASTER] = { ++ .bit = BIT(4), ++ .reg = TH1520_FCE_RST_CFG, ++ }, ++ [TH1520_RESET_ID_FCE_X2X_SLAVE] = { ++ .bit = BIT(5), ++ .reg = TH1520_FCE_RST_CFG, ++ }, ++ [TH1520_RESET_ID_G2D_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_G2D_RST_CFG, ++ }, ++ [TH1520_RESET_ID_G2D_ACLK] = { ++ .bit = BIT(1), ++ .reg = TH1520_G2D_RST_CFG, ++ }, ++ [TH1520_RESET_ID_G2D_CORE] = { ++ .bit = BIT(2), ++ .reg = TH1520_G2D_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VDEC_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_VDEC_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VDEC_ACLK] = { ++ .bit = BIT(1), ++ .reg = TH1520_VDEC_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VDEC_CORE] = { ++ .bit = BIT(2), ++ .reg = TH1520_VDEC_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VENC_APB] = { ++ .bit = BIT(0), ++ .reg = TH1520_VENC_RST_CFG, ++ }, ++ [TH1520_RESET_ID_VENC_CORE] = { ++ .bit = BIT(1), ++ .reg = TH1520_VENC_RST_CFG, ++ }, + }; + + static inline struct th1520_reset_priv * +@@ -170,8 +933,38 @@ static const struct th1520_reset_data th1520_reset_data = { + .num = ARRAY_SIZE(th1520_resets), + }; + ++static const struct th1520_reset_data th1520_ap_reset_data = { ++ .resets = th1520_ap_resets, ++ .num = ARRAY_SIZE(th1520_ap_resets), ++}; ++ ++static const struct th1520_reset_data th1520_dsp_reset_data = { ++ .resets = th1520_dsp_resets, ++ .num = ARRAY_SIZE(th1520_dsp_resets), ++}; ++ ++static const struct th1520_reset_data th1520_misc_reset_data = { ++ .resets = th1520_misc_resets, ++ .num = ARRAY_SIZE(th1520_misc_resets), ++}; ++ ++static const struct th1520_reset_data th1520_vi_reset_data = { ++ .resets = th1520_vi_resets, ++ .num = ARRAY_SIZE(th1520_vi_resets), ++}; ++ ++static const struct th1520_reset_data th1520_vp_reset_data = { ++ .resets = th1520_vp_resets, ++ .num = ARRAY_SIZE(th1520_vp_resets), ++}; ++ + static const struct of_device_id th1520_reset_match[] = { + { .compatible = "thead,th1520-reset", .data = &th1520_reset_data }, ++ { .compatible = "thead,th1520-reset-ap", .data = &th1520_ap_reset_data }, ++ { .compatible = "thead,th1520-reset-dsp", .data = &th1520_dsp_reset_data }, ++ { .compatible = "thead,th1520-reset-misc", .data = &th1520_misc_reset_data }, ++ { .compatible = "thead,th1520-reset-vi", .data = &th1520_vi_reset_data }, ++ { .compatible = "thead,th1520-reset-vp", .data = &th1520_vp_reset_data }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, th1520_reset_match); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0257-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch b/SPECS/linux-lts/0257-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch deleted file mode 100644 index 1cbde5c75c..0000000000 --- a/SPECS/linux-lts/0257-UPSTREAM-dt-bindings-reset-thead-th1520-reset-Add-co.patch +++ /dev/null @@ -1,277 +0,0 @@ -From 184187292f9161178cb3c60ba9bc5998781517ec Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Tue, 14 Oct 2025 13:10:29 +0000 -Subject: [PATCH 257/467] UPSTREAM: dt-bindings: reset: thead,th1520-reset: Add - controllers for more subsys - -TH1520 SoC is divided into several subsystems, most of them have -distinct reset controllers. Let's document reset controllers other than -the one for VO subsystem and IDs for their reset signals. - -Signed-off-by: Yao Zi -Acked-by: Rob Herring (Arm) -Reviewed-by: Drew Fustini -Acked-by: Guo Ren -Signed-off-by: Philipp Zabel -(cherry picked from commit a35ac6f3bdb135debc8e1ff599d0009bc64dc329) -Signed-off-by: Han Gao ---- - .../bindings/reset/thead,th1520-reset.yaml | 8 +- - .../dt-bindings/reset/thead,th1520-reset.h | 216 ++++++++++++++++++ - 2 files changed, 223 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml -index f2e91d0add7a..7b5053c177fe 100644 ---- a/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml -+++ b/Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml -@@ -16,7 +16,13 @@ maintainers: - properties: - compatible: - enum: -- - thead,th1520-reset -+ - thead,th1520-reset # Reset controller for VO subsystem -+ - thead,th1520-reset-ao -+ - thead,th1520-reset-ap -+ - thead,th1520-reset-dsp -+ - thead,th1520-reset-misc -+ - thead,th1520-reset-vi -+ - thead,th1520-reset-vp - - reg: - maxItems: 1 -diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h -index e51d6314d131..ba6805b6b12a 100644 ---- a/include/dt-bindings/reset/thead,th1520-reset.h -+++ b/include/dt-bindings/reset/thead,th1520-reset.h -@@ -7,6 +7,200 @@ - #ifndef _DT_BINDINGS_TH1520_RESET_H - #define _DT_BINDINGS_TH1520_RESET_H - -+/* AO Subsystem */ -+#define TH1520_RESET_ID_SYSTEM 0 -+#define TH1520_RESET_ID_RTC_APB 1 -+#define TH1520_RESET_ID_RTC_REF 2 -+#define TH1520_RESET_ID_AOGPIO_DB 3 -+#define TH1520_RESET_ID_AOGPIO_APB 4 -+#define TH1520_RESET_ID_AOI2C_APB 5 -+#define TH1520_RESET_ID_PVT_APB 6 -+#define TH1520_RESET_ID_E902_CORE 7 -+#define TH1520_RESET_ID_E902_HAD 8 -+#define TH1520_RESET_ID_AOTIMER_APB 9 -+#define TH1520_RESET_ID_AOTIMER_CORE 10 -+#define TH1520_RESET_ID_AOWDT_APB 11 -+#define TH1520_RESET_ID_APSYS 12 -+#define TH1520_RESET_ID_NPUSYS 13 -+#define TH1520_RESET_ID_DDRSYS 14 -+#define TH1520_RESET_ID_AXI_AP2CP 15 -+#define TH1520_RESET_ID_AXI_CP2AP 16 -+#define TH1520_RESET_ID_AXI_CP2SRAM 17 -+#define TH1520_RESET_ID_AUDSYS_CORE 18 -+#define TH1520_RESET_ID_AUDSYS_IOPMP 19 -+#define TH1520_RESET_ID_AUDSYS 20 -+#define TH1520_RESET_ID_DSP0 21 -+#define TH1520_RESET_ID_DSP1 22 -+#define TH1520_RESET_ID_GPU_MODULE 23 -+#define TH1520_RESET_ID_VDEC 24 -+#define TH1520_RESET_ID_VENC 25 -+#define TH1520_RESET_ID_ADC_APB 26 -+#define TH1520_RESET_ID_AUDGPIO_DB 27 -+#define TH1520_RESET_ID_AUDGPIO_APB 28 -+#define TH1520_RESET_ID_AOUART_IF 29 -+#define TH1520_RESET_ID_AOUART_APB 30 -+#define TH1520_RESET_ID_SRAM_AXI_P0 31 -+#define TH1520_RESET_ID_SRAM_AXI_P1 32 -+#define TH1520_RESET_ID_SRAM_AXI_P2 33 -+#define TH1520_RESET_ID_SRAM_AXI_P3 34 -+#define TH1520_RESET_ID_SRAM_AXI_P4 35 -+#define TH1520_RESET_ID_SRAM_AXI_CORE 36 -+#define TH1520_RESET_ID_SE 37 -+ -+/* AP Subsystem */ -+#define TH1520_RESET_ID_BROM 0 -+#define TH1520_RESET_ID_C910_TOP 1 -+#define TH1520_RESET_ID_NPU 2 -+#define TH1520_RESET_ID_WDT0 3 -+#define TH1520_RESET_ID_WDT1 4 -+#define TH1520_RESET_ID_C910_C0 5 -+#define TH1520_RESET_ID_C910_C1 6 -+#define TH1520_RESET_ID_C910_C2 7 -+#define TH1520_RESET_ID_C910_C3 8 -+#define TH1520_RESET_ID_CHIP_DBG_CORE 9 -+#define TH1520_RESET_ID_CHIP_DBG_AXI 10 -+#define TH1520_RESET_ID_AXI4_CPUSYS2_AXI 11 -+#define TH1520_RESET_ID_AXI4_CPUSYS2_APB 12 -+#define TH1520_RESET_ID_X2H_CPUSYS 13 -+#define TH1520_RESET_ID_AHB2_CPUSYS 14 -+#define TH1520_RESET_ID_APB3_CPUSYS 15 -+#define TH1520_RESET_ID_MBOX0_APB 16 -+#define TH1520_RESET_ID_MBOX1_APB 17 -+#define TH1520_RESET_ID_MBOX2_APB 18 -+#define TH1520_RESET_ID_MBOX3_APB 19 -+#define TH1520_RESET_ID_TIMER0_APB 20 -+#define TH1520_RESET_ID_TIMER0_CORE 21 -+#define TH1520_RESET_ID_TIMER1_APB 22 -+#define TH1520_RESET_ID_TIMER1_CORE 23 -+#define TH1520_RESET_ID_PERISYS_AHB 24 -+#define TH1520_RESET_ID_PERISYS_APB1 25 -+#define TH1520_RESET_ID_PERISYS_APB2 26 -+#define TH1520_RESET_ID_GMAC0_APB 27 -+#define TH1520_RESET_ID_GMAC0_AHB 28 -+#define TH1520_RESET_ID_GMAC0_CLKGEN 29 -+#define TH1520_RESET_ID_GMAC0_AXI 30 -+#define TH1520_RESET_ID_UART0_APB 31 -+#define TH1520_RESET_ID_UART0_IF 32 -+#define TH1520_RESET_ID_UART1_APB 33 -+#define TH1520_RESET_ID_UART1_IF 34 -+#define TH1520_RESET_ID_UART2_APB 35 -+#define TH1520_RESET_ID_UART2_IF 36 -+#define TH1520_RESET_ID_UART3_APB 37 -+#define TH1520_RESET_ID_UART3_IF 38 -+#define TH1520_RESET_ID_UART4_APB 39 -+#define TH1520_RESET_ID_UART4_IF 40 -+#define TH1520_RESET_ID_UART5_APB 41 -+#define TH1520_RESET_ID_UART5_IF 42 -+#define TH1520_RESET_ID_QSPI0_IF 43 -+#define TH1520_RESET_ID_QSPI0_APB 44 -+#define TH1520_RESET_ID_QSPI1_IF 45 -+#define TH1520_RESET_ID_QSPI1_APB 46 -+#define TH1520_RESET_ID_SPI_IF 47 -+#define TH1520_RESET_ID_SPI_APB 48 -+#define TH1520_RESET_ID_I2C0_APB 49 -+#define TH1520_RESET_ID_I2C0_CORE 50 -+#define TH1520_RESET_ID_I2C1_APB 51 -+#define TH1520_RESET_ID_I2C1_CORE 52 -+#define TH1520_RESET_ID_I2C2_APB 53 -+#define TH1520_RESET_ID_I2C2_CORE 54 -+#define TH1520_RESET_ID_I2C3_APB 55 -+#define TH1520_RESET_ID_I2C3_CORE 56 -+#define TH1520_RESET_ID_I2C4_APB 57 -+#define TH1520_RESET_ID_I2C4_CORE 58 -+#define TH1520_RESET_ID_I2C5_APB 59 -+#define TH1520_RESET_ID_I2C5_CORE 60 -+#define TH1520_RESET_ID_GPIO0_DB 61 -+#define TH1520_RESET_ID_GPIO0_APB 62 -+#define TH1520_RESET_ID_GPIO1_DB 63 -+#define TH1520_RESET_ID_GPIO1_APB 64 -+#define TH1520_RESET_ID_GPIO2_DB 65 -+#define TH1520_RESET_ID_GPIO2_APB 66 -+#define TH1520_RESET_ID_PWM_COUNTER 67 -+#define TH1520_RESET_ID_PWM_APB 68 -+#define TH1520_RESET_ID_PADCTRL0_APB 69 -+#define TH1520_RESET_ID_CPU2PERI_X2H 70 -+#define TH1520_RESET_ID_CPU2AON_X2H 71 -+#define TH1520_RESET_ID_AON2CPU_A2X 72 -+#define TH1520_RESET_ID_NPUSYS_AXI 73 -+#define TH1520_RESET_ID_NPUSYS_AXI_APB 74 -+#define TH1520_RESET_ID_CPU2VP_X2P 75 -+#define TH1520_RESET_ID_CPU2VI_X2H 76 -+#define TH1520_RESET_ID_BMU_AXI 77 -+#define TH1520_RESET_ID_BMU_APB 78 -+#define TH1520_RESET_ID_DMAC_CPUSYS_AXI 79 -+#define TH1520_RESET_ID_DMAC_CPUSYS_AHB 80 -+#define TH1520_RESET_ID_SPINLOCK 81 -+#define TH1520_RESET_ID_CFG2TEE 82 -+#define TH1520_RESET_ID_DSMART 83 -+#define TH1520_RESET_ID_GPIO3_DB 84 -+#define TH1520_RESET_ID_GPIO3_APB 85 -+#define TH1520_RESET_ID_PERI_I2S 86 -+#define TH1520_RESET_ID_PERI_APB3 87 -+#define TH1520_RESET_ID_PERI2PERI1_APB 88 -+#define TH1520_RESET_ID_VPSYS_APB 89 -+#define TH1520_RESET_ID_PERISYS_APB4 90 -+#define TH1520_RESET_ID_GMAC1_APB 91 -+#define TH1520_RESET_ID_GMAC1_AHB 92 -+#define TH1520_RESET_ID_GMAC1_CLKGEN 93 -+#define TH1520_RESET_ID_GMAC1_AXI 94 -+#define TH1520_RESET_ID_GMAC_AXI 95 -+#define TH1520_RESET_ID_GMAC_AXI_APB 96 -+#define TH1520_RESET_ID_PADCTRL1_APB 97 -+#define TH1520_RESET_ID_VOSYS_AXI 98 -+#define TH1520_RESET_ID_VOSYS_AXI_APB 99 -+#define TH1520_RESET_ID_VOSYS_AXI_X2X 100 -+#define TH1520_RESET_ID_MISC2VP_X2X 101 -+#define TH1520_RESET_ID_DSPSYS 102 -+#define TH1520_RESET_ID_VISYS 103 -+#define TH1520_RESET_ID_VOSYS 104 -+#define TH1520_RESET_ID_VPSYS 105 -+ -+/* DSP Subsystem */ -+#define TH1520_RESET_ID_X2X_DSP1 0 -+#define TH1520_RESET_ID_X2X_DSP0 1 -+#define TH1520_RESET_ID_X2X_SLAVE_DSP1 2 -+#define TH1520_RESET_ID_X2X_SLAVE_DSP0 3 -+#define TH1520_RESET_ID_DSP0_CORE 4 -+#define TH1520_RESET_ID_DSP0_DEBUG 5 -+#define TH1520_RESET_ID_DSP0_APB 6 -+#define TH1520_RESET_ID_DSP1_CORE 7 -+#define TH1520_RESET_ID_DSP1_DEBUG 8 -+#define TH1520_RESET_ID_DSP1_APB 9 -+#define TH1520_RESET_ID_DSPSYS_APB 10 -+#define TH1520_RESET_ID_AXI4_DSPSYS_SLV 11 -+#define TH1520_RESET_ID_AXI4_DSPSYS 12 -+#define TH1520_RESET_ID_AXI4_DSP_RS 13 -+ -+/* MISC Subsystem */ -+#define TH1520_RESET_ID_EMMC_SDIO_CLKGEN 0 -+#define TH1520_RESET_ID_EMMC 1 -+#define TH1520_RESET_ID_MISCSYS_AXI 2 -+#define TH1520_RESET_ID_MISCSYS_AXI_APB 3 -+#define TH1520_RESET_ID_SDIO0 4 -+#define TH1520_RESET_ID_SDIO1 5 -+#define TH1520_RESET_ID_USB3_APB 6 -+#define TH1520_RESET_ID_USB3_PHY 7 -+#define TH1520_RESET_ID_USB3_VCC 8 -+ -+/* VI Subsystem */ -+#define TH1520_RESET_ID_ISP0 0 -+#define TH1520_RESET_ID_ISP1 1 -+#define TH1520_RESET_ID_CSI0_APB 2 -+#define TH1520_RESET_ID_CSI1_APB 3 -+#define TH1520_RESET_ID_CSI2_APB 4 -+#define TH1520_RESET_ID_MIPI_FIFO 5 -+#define TH1520_RESET_ID_ISP_VENC_APB 6 -+#define TH1520_RESET_ID_VIPRE_APB 7 -+#define TH1520_RESET_ID_VIPRE_AXI 8 -+#define TH1520_RESET_ID_DW200_APB 9 -+#define TH1520_RESET_ID_VISYS3_AXI 10 -+#define TH1520_RESET_ID_VISYS2_AXI 11 -+#define TH1520_RESET_ID_VISYS1_AXI 12 -+#define TH1520_RESET_ID_VISYS_AXI 13 -+#define TH1520_RESET_ID_VISYS_APB 14 -+#define TH1520_RESET_ID_ISP_VENC_AXI 15 -+ -+/* VO Subsystem */ - #define TH1520_RESET_ID_GPU 0 - #define TH1520_RESET_ID_GPU_CLKGEN 1 - #define TH1520_RESET_ID_DPU_AHB 5 -@@ -16,5 +210,27 @@ - #define TH1520_RESET_ID_DSI1_APB 9 - #define TH1520_RESET_ID_HDMI 10 - #define TH1520_RESET_ID_HDMI_APB 11 -+#define TH1520_RESET_ID_VOAXI 12 -+#define TH1520_RESET_ID_VOAXI_APB 13 -+#define TH1520_RESET_ID_X2H_DPU_AXI 14 -+#define TH1520_RESET_ID_X2H_DPU_AHB 15 -+#define TH1520_RESET_ID_X2H_DPU1_AXI 16 -+#define TH1520_RESET_ID_X2H_DPU1_AHB 17 -+ -+/* VP Subsystem */ -+#define TH1520_RESET_ID_VPSYS_AXI_APB 0 -+#define TH1520_RESET_ID_VPSYS_AXI 1 -+#define TH1520_RESET_ID_FCE_APB 2 -+#define TH1520_RESET_ID_FCE_CORE 3 -+#define TH1520_RESET_ID_FCE_X2X_MASTER 4 -+#define TH1520_RESET_ID_FCE_X2X_SLAVE 5 -+#define TH1520_RESET_ID_G2D_APB 6 -+#define TH1520_RESET_ID_G2D_ACLK 7 -+#define TH1520_RESET_ID_G2D_CORE 8 -+#define TH1520_RESET_ID_VDEC_APB 9 -+#define TH1520_RESET_ID_VDEC_ACLK 10 -+#define TH1520_RESET_ID_VDEC_CORE 11 -+#define TH1520_RESET_ID_VENC_APB 12 -+#define TH1520_RESET_ID_VENC_CORE 13 - - #endif /* _DT_BINDINGS_TH1520_RESET_H */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch b/SPECS/linux-lts/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch new file mode 100644 index 0000000000..0509d7a26d --- /dev/null +++ b/SPECS/linux-lts/0257-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch @@ -0,0 +1,91 @@ +From 9edafc5f3980e8fcb1a7a18a54466898f1279c14 Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Tue, 14 Oct 2025 13:10:32 +0000 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: Add reset controllers of + more subsystems for TH1520 + +Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The +one for AO subsystem is marked as reserved, since it may be used by AON +firmware. + +Reviewed-by: Drew Fustini +Signed-off-by: Yao Zi +Signed-off-by: Drew Fustini +(cherry picked from commit d8a174babf649346b6dad6784ae1e9bc8417af71) +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++ + 1 file changed, 37 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index c65b71d9a1b8..5e91dc1d2b9b 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -289,6 +289,12 @@ clint: timer@ffdc000000 { + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + ++ rst_vi: reset-controller@ffe4040100 { ++ compatible = "thead,th1520-reset-vi"; ++ reg = <0xff 0xe4040100 0x0 0x8>; ++ #reset-cells = <1>; ++ }; ++ + spi0: spi@ffe700c000 { + compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; + reg = <0xff 0xe700c000 0x0 0x1000>; +@@ -521,6 +527,18 @@ pwm: pwm@ffec01c000 { + #pwm-cells = <3>; + }; + ++ rst_misc: reset-controller@ffec02c000 { ++ compatible = "thead,th1520-reset-misc"; ++ reg = <0xff 0xec02c000 0x0 0x18>; ++ #reset-cells = <1>; ++ }; ++ ++ rst_vp: reset-controller@ffecc30000 { ++ compatible = "thead,th1520-reset-vp"; ++ reg = <0xff 0xecc30000 0x0 0x14>; ++ #reset-cells = <1>; ++ }; ++ + clk: clock-controller@ffef010000 { + compatible = "thead,th1520-clk-ap"; + reg = <0xff 0xef010000 0x0 0x1000>; +@@ -528,6 +546,18 @@ clk: clock-controller@ffef010000 { + #clock-cells = <1>; + }; + ++ rst_ap: reset-controller@ffef014000 { ++ compatible = "thead,th1520-reset-ap"; ++ reg = <0xff 0xef014000 0x0 0x1000>; ++ #reset-cells = <1>; ++ }; ++ ++ rst_dsp: reset-controller@ffef040028 { ++ compatible = "thead,th1520-reset-dsp"; ++ reg = <0xff 0xef040028 0x0 0x4>; ++ #reset-cells = <1>; ++ }; ++ + gpu: gpu@ffef400000 { + compatible = "thead,th1520-gpu", "img,img-bxm-4-64", + "img,img-rogue"; +@@ -766,6 +796,13 @@ aogpio: gpio-controller@0 { + }; + }; + ++ rst_ao: reset-controller@fffff44000 { ++ compatible = "thead,th1520-reset-ao"; ++ reg = <0xff 0xfff44000 0x0 0x2000>; ++ #reset-cells = <1>; ++ status = "reserved"; ++ }; ++ + padctrl_aosys: pinctrl@fffff4a000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xfff4a000 0x0 0x2000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch b/SPECS/linux-lts/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch new file mode 100644 index 0000000000..983dd64913 --- /dev/null +++ b/SPECS/linux-lts/0258-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch @@ -0,0 +1,39 @@ +From 5f50d2a328f7b2daa106bafdb1d4a794f52fbdb4 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 24 Apr 2026 16:20:32 +0800 +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: mark top_dclk as + CLK_IS_CRITICAL + +top_dclk is the DDR bus clock. If it is gated by clk_disable_unused, +all memory-mapped bus transactions cease to function, causing DMA +engines to hang and general system instability. + +Mark it CLK_IS_CRITICAL so the CCF never gates it during the +unused clock sweep. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Reviewed-by: Brian Masney +Signed-off-by: Troy Mitchell +Signed-off-by: Stephen Boyd +(cherry picked from commit 3e75021f615ceee8562e6455c335936b39929ffb) +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index e98afd59f05c..bb8b75bdbdb3 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -846,7 +846,7 @@ static const struct clk_parent_data top_parents[] = { + CCU_PARENT_HW(pll6_d3), + }; + CCU_MUX_DIV_GATE_FC_DEFINE(top_dclk, top_parents, APMU_TOP_DCLK_CTRL, 5, 3, +- BIT(8), 2, 3, BIT(1), 0); ++ BIT(8), 2, 3, BIT(1), CLK_IS_CRITICAL); + + static const struct clk_parent_data ucie_parents[] = { + CCU_PARENT_HW(pll1_d8_307p2), +-- +2.53.0 + diff --git a/SPECS/linux-lts/0258-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch b/SPECS/linux-lts/0258-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch deleted file mode 100644 index 350dce55d4..0000000000 --- a/SPECS/linux-lts/0258-UPSTREAM-reset-th1520-Prepare-for-supporting-multipl.patch +++ /dev/null @@ -1,124 +0,0 @@ -From db3838d594378909391879da3362ce86ec33cc81 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Tue, 14 Oct 2025 13:10:30 +0000 -Subject: [PATCH 258/467] UPSTREAM: reset: th1520: Prepare for supporting - multiple controllers - -TH1520 SoC is divided into several subsystems, shipping distinct reset -controllers with similar control logic. Let's make reset signal mapping -a data structure specific to one compatible to prepare for introduction -of more reset controllers in the future. - -Signed-off-by: Yao Zi -Acked-by: Guo Ren -Reviewed-by: Drew Fustini -Signed-off-by: Philipp Zabel -(cherry picked from commit 0040d9eac391bacefcb0c748cf32c8fe5900b13b) -Signed-off-by: Han Gao ---- - drivers/reset/reset-th1520.c | 42 +++++++++++++++++++++++++----------- - 1 file changed, 30 insertions(+), 12 deletions(-) - -diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c -index 14d964a9c6b6..2b65a95ed021 100644 ---- a/drivers/reset/reset-th1520.c -+++ b/drivers/reset/reset-th1520.c -@@ -29,14 +29,20 @@ - #define TH1520_HDMI_SW_MAIN_RST BIT(0) - #define TH1520_HDMI_SW_PRST BIT(1) - -+struct th1520_reset_map { -+ u32 bit; -+ u32 reg; -+}; -+ - struct th1520_reset_priv { - struct reset_controller_dev rcdev; - struct regmap *map; -+ const struct th1520_reset_map *resets; - }; - --struct th1520_reset_map { -- u32 bit; -- u32 reg; -+struct th1520_reset_data { -+ const struct th1520_reset_map *resets; -+ size_t num; - }; - - static const struct th1520_reset_map th1520_resets[] = { -@@ -90,7 +96,7 @@ static int th1520_reset_assert(struct reset_controller_dev *rcdev, - struct th1520_reset_priv *priv = to_th1520_reset(rcdev); - const struct th1520_reset_map *reset; - -- reset = &th1520_resets[id]; -+ reset = &priv->resets[id]; - - return regmap_update_bits(priv->map, reset->reg, reset->bit, 0); - } -@@ -101,7 +107,7 @@ static int th1520_reset_deassert(struct reset_controller_dev *rcdev, - struct th1520_reset_priv *priv = to_th1520_reset(rcdev); - const struct th1520_reset_map *reset; - -- reset = &th1520_resets[id]; -+ reset = &priv->resets[id]; - - return regmap_update_bits(priv->map, reset->reg, reset->bit, - reset->bit); -@@ -120,11 +126,14 @@ static const struct regmap_config th1520_reset_regmap_config = { - - static int th1520_reset_probe(struct platform_device *pdev) - { -+ const struct th1520_reset_data *data; - struct device *dev = &pdev->dev; - struct th1520_reset_priv *priv; - void __iomem *base; - int ret; - -+ data = device_get_match_data(dev); -+ - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; -@@ -138,22 +147,31 @@ static int th1520_reset_probe(struct platform_device *pdev) - if (IS_ERR(priv->map)) - return PTR_ERR(priv->map); - -- /* Initialize GPU resets to asserted state */ -- ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, -- TH1520_GPU_RST_CFG_MASK, 0); -- if (ret) -- return ret; -+ if (of_device_is_compatible(dev->of_node, "thead,th1520-reset")) { -+ /* Initialize GPU resets to asserted state */ -+ ret = regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, -+ TH1520_GPU_RST_CFG_MASK, 0); -+ if (ret) -+ return ret; -+ } - - priv->rcdev.owner = THIS_MODULE; -- priv->rcdev.nr_resets = ARRAY_SIZE(th1520_resets); -+ priv->rcdev.nr_resets = data->num; - priv->rcdev.ops = &th1520_reset_ops; - priv->rcdev.of_node = dev->of_node; - -+ priv->resets = data->resets; -+ - return devm_reset_controller_register(dev, &priv->rcdev); - } - -+static const struct th1520_reset_data th1520_reset_data = { -+ .resets = th1520_resets, -+ .num = ARRAY_SIZE(th1520_resets), -+}; -+ - static const struct of_device_id th1520_reset_match[] = { -- { .compatible = "thead,th1520-reset" }, -+ { .compatible = "thead,th1520-reset", .data = &th1520_reset_data }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, th1520_reset_match); --- -2.53.0 - diff --git a/SPECS/linux-lts/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch b/SPECS/linux-lts/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch new file mode 100644 index 0000000000..b11d06885a --- /dev/null +++ b/SPECS/linux-lts/0259-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch @@ -0,0 +1,53 @@ +From a7739f1ea5fb20b796b4b1d3758fd44635a40ea9 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Wed, 29 Apr 2026 17:00:50 +0800 +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: fix RX DMA params not set when + TX is running + +When TX is already running (SSCR_SSE is set), the hw_params callback +returns early before setting up DMA parameters for the RX stream. This +prevents the capture path from configuring its DMA data properly. + +Move the SSCR_SSE check after DMA parameter setup and format +constraints, so both TX and RX streams get their DMA configuration +regardless of whether the hardware is already enabled. The early return +now only skips the register writes that would disrupt an active stream. + +Fixes: fce217449075 ("ASoC: spacemit: add i2s support for K1 SoC") +Signed-off-by: Troy Mitchell +Link: https://patch.msgid.link/20260429-k1-i2s-fix-v2-1-8d67835aaddc@linux.spacemit.com +Signed-off-by: Mark Brown +(cherry picked from commit ec0611868f2fcf29e4c2bebdc6702d3e1f272fec) +Signed-off-by: Han Gao +--- + sound/soc/spacemit/k1_i2s.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c +index b48c57bede37..03cca5d84503 100644 +--- a/sound/soc/spacemit/k1_i2s.c ++++ b/sound/soc/spacemit/k1_i2s.c +@@ -148,10 +148,6 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, + u32 val; + int ret; + +- val = readl(i2s->base + SSCR); +- if (val & SSCR_SSE) +- return 0; +- + dma_data = &i2s->playback_dma_data; + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) +@@ -199,6 +195,9 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, + } + + val = readl(i2s->base + SSCR); ++ if (val & SSCR_SSE) ++ return 0; ++ + val &= ~SSCR_DW_32BYTE; + val |= data_width; + writel(val, i2s->base + SSCR); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0259-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch b/SPECS/linux-lts/0259-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch deleted file mode 100644 index 6e02a295c5..0000000000 --- a/SPECS/linux-lts/0259-UPSTREAM-reset-th1520-Support-reset-controllers-in-m.patch +++ /dev/null @@ -1,856 +0,0 @@ -From 8109a7f9d10f1d9ce7e0ee5a3f63993d591d8673 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Tue, 14 Oct 2025 13:10:31 +0000 -Subject: [PATCH 259/467] UPSTREAM: reset: th1520: Support reset controllers in - more subsystems - -Introduce reset controllers for AP, MISC, VI, VP and DSP subsystems and -add their reset signal mappings. - -Signed-off-by: Yao Zi -Reviewed-by: Drew Fustini -Acked-by: Guo Ren -Signed-off-by: Philipp Zabel -(cherry picked from commit da91533c2b7a569b272b8271f0b2c407f86407ed) -Signed-off-by: Han Gao ---- - drivers/reset/reset-th1520.c | 793 +++++++++++++++++++++++++++++++++++ - 1 file changed, 793 insertions(+) - -diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c -index 2b65a95ed021..fd32e991c4cb 100644 ---- a/drivers/reset/reset-th1520.c -+++ b/drivers/reset/reset-th1520.c -@@ -11,6 +11,85 @@ - - #include - -+ /* register offset in RSTGEN_R */ -+#define TH1520_BROM_RST_CFG 0x0 -+#define TH1520_C910_RST_CFG 0x4 -+#define TH1520_CHIP_DBG_RST_CFG 0xc -+#define TH1520_AXI4_CPUSYS2_RST_CFG 0x10 -+#define TH1520_X2H_CPUSYS_RST_CFG 0x18 -+#define TH1520_AHB2_CPUSYS_RST_CFG 0x1c -+#define TH1520_APB3_CPUSYS_RST_CFG 0x20 -+#define TH1520_MBOX0_RST_CFG 0x24 -+#define TH1520_MBOX1_RST_CFG 0x28 -+#define TH1520_MBOX2_RST_CFG 0x2c -+#define TH1520_MBOX3_RST_CFG 0x30 -+#define TH1520_WDT0_RST_CFG 0x34 -+#define TH1520_WDT1_RST_CFG 0x38 -+#define TH1520_TIMER0_RST_CFG 0x3c -+#define TH1520_TIMER1_RST_CFG 0x40 -+#define TH1520_PERISYS_AHB_RST_CFG 0x44 -+#define TH1520_PERISYS_APB1_RST_CFG 0x48 -+#define TH1520_PERISYS_APB2_RST_CFG 0x4c -+#define TH1520_GMAC0_RST_CFG 0x68 -+#define TH1520_UART0_RST_CFG 0x70 -+#define TH1520_UART1_RST_CFG 0x74 -+#define TH1520_UART2_RST_CFG 0x78 -+#define TH1520_UART3_RST_CFG 0x7c -+#define TH1520_UART4_RST_CFG 0x80 -+#define TH1520_UART5_RST_CFG 0x84 -+#define TH1520_QSPI0_RST_CFG 0x8c -+#define TH1520_QSPI1_RST_CFG 0x90 -+#define TH1520_SPI_RST_CFG 0x94 -+#define TH1520_I2C0_RST_CFG 0x98 -+#define TH1520_I2C1_RST_CFG 0x9c -+#define TH1520_I2C2_RST_CFG 0xa0 -+#define TH1520_I2C3_RST_CFG 0xa4 -+#define TH1520_I2C4_RST_CFG 0xa8 -+#define TH1520_I2C5_RST_CFG 0xac -+#define TH1520_GPIO0_RST_CFG 0xb0 -+#define TH1520_GPIO1_RST_CFG 0xb4 -+#define TH1520_GPIO2_RST_CFG 0xb8 -+#define TH1520_PWM_RST_CFG 0xc0 -+#define TH1520_PADCTRL0_APSYS_RST_CFG 0xc4 -+#define TH1520_CPU2PERI_X2H_RST_CFG 0xcc -+#define TH1520_CPU2AON_X2H_RST_CFG 0xe4 -+#define TH1520_AON2CPU_A2X_RST_CFG 0xfc -+#define TH1520_NPUSYS_AXI_RST_CFG 0x128 -+#define TH1520_CPU2VP_X2P_RST_CFG 0x12c -+#define TH1520_CPU2VI_X2H_RST_CFG 0x138 -+#define TH1520_BMU_C910_RST_CFG 0x148 -+#define TH1520_DMAC_CPUSYS_RST_CFG 0x14c -+#define TH1520_SPINLOCK_RST_CFG 0x178 -+#define TH1520_CFG2TEE_X2H_RST_CFG 0x188 -+#define TH1520_DSMART_RST_CFG 0x18c -+#define TH1520_GPIO3_RST_CFG 0x1a8 -+#define TH1520_I2S_RST_CFG 0x1ac -+#define TH1520_IMG_NNA_RST_CFG 0x1b0 -+#define TH1520_PERI_APB3_RST_CFG 0x1dc -+#define TH1520_VP_SUBSYS_RST_CFG 0x1ec -+#define TH1520_PERISYS_APB4_RST_CFG 0x1f8 -+#define TH1520_GMAC1_RST_CFG 0x204 -+#define TH1520_GMAC_AXI_RST_CFG 0x208 -+#define TH1520_PADCTRL1_APSYS_RST_CFG 0x20c -+#define TH1520_VOSYS_AXI_RST_CFG 0x210 -+#define TH1520_VOSYS_X2X_RST_CFG 0x214 -+#define TH1520_MISC2VP_X2X_RST_CFG 0x218 -+#define TH1520_SUBSYS_RST_CFG 0x220 -+ -+ /* register offset in DSP_REGMAP */ -+#define TH1520_DSPSYS_RST_CFG 0x0 -+ -+ /* register offset in MISCSYS_REGMAP */ -+#define TH1520_EMMC_RST_CFG 0x0 -+#define TH1520_MISCSYS_AXI_RST_CFG 0x8 -+#define TH1520_SDIO0_RST_CFG 0xc -+#define TH1520_SDIO1_RST_CFG 0x10 -+#define TH1520_USB3_DRD_RST_CFG 0x14 -+ -+ /* register offset in VISYS_REGMAP */ -+#define TH1520_VISYS_RST_CFG 0x0 -+#define TH1520_VISYS_2_RST_CFG 0x4 -+ - /* register offset in VOSYS_REGMAP */ - #define TH1520_GPU_RST_CFG 0x0 - #define TH1520_GPU_RST_CFG_MASK GENMASK(1, 0) -@@ -18,6 +97,8 @@ - #define TH1520_DSI0_RST_CFG 0x8 - #define TH1520_DSI1_RST_CFG 0xc - #define TH1520_HDMI_RST_CFG 0x14 -+#define TH1520_AXI4_VO_DW_AXI_RST_CFG 0x18 -+#define TH1520_X2H_X4_VOSYS_DW_RST_CFG 0x20 - - /* register values */ - #define TH1520_GPU_SW_GPU_RST BIT(0) -@@ -29,6 +110,13 @@ - #define TH1520_HDMI_SW_MAIN_RST BIT(0) - #define TH1520_HDMI_SW_PRST BIT(1) - -+ /* register offset in VPSYS_REGMAP */ -+#define TH1520_AXIBUS_RST_CFG 0x0 -+#define TH1520_FCE_RST_CFG 0x4 -+#define TH1520_G2D_RST_CFG 0x8 -+#define TH1520_VDEC_RST_CFG 0xc -+#define TH1520_VENC_RST_CFG 0x10 -+ - struct th1520_reset_map { - u32 bit; - u32 reg; -@@ -82,6 +170,681 @@ static const struct th1520_reset_map th1520_resets[] = { - .bit = TH1520_HDMI_SW_PRST, - .reg = TH1520_HDMI_RST_CFG, - }, -+ [TH1520_RESET_ID_VOAXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VOAXI_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_AXI4_VO_DW_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2H_DPU_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2H_DPU_AHB] = { -+ .bit = BIT(1), -+ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2H_DPU1_AXI] = { -+ .bit = BIT(2), -+ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2H_DPU1_AHB] = { -+ .bit = BIT(3), -+ .reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG, -+ }, -+}; -+ -+static const struct th1520_reset_map th1520_ap_resets[] = { -+ [TH1520_RESET_ID_BROM] = { -+ .bit = BIT(0), -+ .reg = TH1520_BROM_RST_CFG, -+ }, -+ [TH1520_RESET_ID_C910_TOP] = { -+ .bit = BIT(0), -+ .reg = TH1520_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_NPU] = { -+ .bit = BIT(0), -+ .reg = TH1520_IMG_NNA_RST_CFG, -+ }, -+ [TH1520_RESET_ID_WDT0] = { -+ .bit = BIT(0), -+ .reg = TH1520_WDT0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_WDT1] = { -+ .bit = BIT(0), -+ .reg = TH1520_WDT1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_C910_C0] = { -+ .bit = BIT(1), -+ .reg = TH1520_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_C910_C1] = { -+ .bit = BIT(2), -+ .reg = TH1520_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_C910_C2] = { -+ .bit = BIT(3), -+ .reg = TH1520_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_C910_C3] = { -+ .bit = BIT(4), -+ .reg = TH1520_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CHIP_DBG_CORE] = { -+ .bit = BIT(0), -+ .reg = TH1520_CHIP_DBG_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CHIP_DBG_AXI] = { -+ .bit = BIT(1), -+ .reg = TH1520_CHIP_DBG_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AXI4_CPUSYS2_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_AXI4_CPUSYS2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AXI4_CPUSYS2_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_AXI4_CPUSYS2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2H_CPUSYS] = { -+ .bit = BIT(0), -+ .reg = TH1520_X2H_CPUSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AHB2_CPUSYS] = { -+ .bit = BIT(0), -+ .reg = TH1520_AHB2_CPUSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_APB3_CPUSYS] = { -+ .bit = BIT(0), -+ .reg = TH1520_APB3_CPUSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MBOX0_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_MBOX0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MBOX1_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_MBOX1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MBOX2_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_MBOX2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MBOX3_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_MBOX3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_TIMER0_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_TIMER0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_TIMER0_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_TIMER0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_TIMER1_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_TIMER1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_TIMER1_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_TIMER1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERISYS_AHB] = { -+ .bit = BIT(0), -+ .reg = TH1520_PERISYS_AHB_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERISYS_APB1] = { -+ .bit = BIT(0), -+ .reg = TH1520_PERISYS_APB1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERISYS_APB2] = { -+ .bit = BIT(0), -+ .reg = TH1520_PERISYS_APB2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC0_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_GMAC0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC0_AHB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GMAC0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC0_CLKGEN] = { -+ .bit = BIT(2), -+ .reg = TH1520_GMAC0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC0_AXI] = { -+ .bit = BIT(3), -+ .reg = TH1520_GMAC0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART0_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_UART0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART0_IF] = { -+ .bit = BIT(1), -+ .reg = TH1520_UART0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART1_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_UART1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART1_IF] = { -+ .bit = BIT(1), -+ .reg = TH1520_UART1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART2_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_UART2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART2_IF] = { -+ .bit = BIT(1), -+ .reg = TH1520_UART2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART3_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_UART3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART3_IF] = { -+ .bit = BIT(1), -+ .reg = TH1520_UART3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART4_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_UART4_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART4_IF] = { -+ .bit = BIT(1), -+ .reg = TH1520_UART4_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART5_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_UART5_RST_CFG, -+ }, -+ [TH1520_RESET_ID_UART5_IF] = { -+ .bit = BIT(1), -+ .reg = TH1520_UART5_RST_CFG, -+ }, -+ [TH1520_RESET_ID_QSPI0_IF] = { -+ .bit = BIT(0), -+ .reg = TH1520_QSPI0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_QSPI0_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_QSPI0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_QSPI1_IF] = { -+ .bit = BIT(0), -+ .reg = TH1520_QSPI1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_QSPI1_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_QSPI1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_SPI_IF] = { -+ .bit = BIT(0), -+ .reg = TH1520_SPI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_SPI_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_SPI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C0_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2C0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C0_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_I2C0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C1_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2C1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C1_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_I2C1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C2_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2C2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C2_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_I2C2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C3_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2C3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C3_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_I2C3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C4_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2C4_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C4_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_I2C4_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C5_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2C5_RST_CFG, -+ }, -+ [TH1520_RESET_ID_I2C5_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_I2C5_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO0_DB] = { -+ .bit = BIT(0), -+ .reg = TH1520_GPIO0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO0_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GPIO0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO1_DB] = { -+ .bit = BIT(0), -+ .reg = TH1520_GPIO1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO1_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GPIO1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO2_DB] = { -+ .bit = BIT(0), -+ .reg = TH1520_GPIO2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO2_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GPIO2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PWM_COUNTER] = { -+ .bit = BIT(0), -+ .reg = TH1520_PWM_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PWM_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_PWM_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PADCTRL0_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_PADCTRL0_APSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CPU2PERI_X2H] = { -+ .bit = BIT(1), -+ .reg = TH1520_CPU2PERI_X2H_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CPU2AON_X2H] = { -+ .bit = BIT(0), -+ .reg = TH1520_CPU2AON_X2H_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AON2CPU_A2X] = { -+ .bit = BIT(0), -+ .reg = TH1520_AON2CPU_A2X_RST_CFG, -+ }, -+ [TH1520_RESET_ID_NPUSYS_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_NPUSYS_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_NPUSYS_AXI_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_NPUSYS_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CPU2VP_X2P] = { -+ .bit = BIT(0), -+ .reg = TH1520_CPU2VP_X2P_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CPU2VI_X2H] = { -+ .bit = BIT(0), -+ .reg = TH1520_CPU2VI_X2H_RST_CFG, -+ }, -+ [TH1520_RESET_ID_BMU_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_BMU_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_BMU_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_BMU_C910_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DMAC_CPUSYS_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_DMAC_CPUSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DMAC_CPUSYS_AHB] = { -+ .bit = BIT(1), -+ .reg = TH1520_DMAC_CPUSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_SPINLOCK] = { -+ .bit = BIT(0), -+ .reg = TH1520_SPINLOCK_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CFG2TEE] = { -+ .bit = BIT(0), -+ .reg = TH1520_CFG2TEE_X2H_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSMART] = { -+ .bit = BIT(0), -+ .reg = TH1520_DSMART_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO3_DB] = { -+ .bit = BIT(0), -+ .reg = TH1520_GPIO3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GPIO3_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GPIO3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERI_I2S] = { -+ .bit = BIT(0), -+ .reg = TH1520_I2S_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERI_APB3] = { -+ .bit = BIT(0), -+ .reg = TH1520_PERI_APB3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERI2PERI1_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_PERI_APB3_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VPSYS_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_VP_SUBSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PERISYS_APB4] = { -+ .bit = BIT(0), -+ .reg = TH1520_PERISYS_APB4_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC1_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_GMAC1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC1_AHB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GMAC1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC1_CLKGEN] = { -+ .bit = BIT(2), -+ .reg = TH1520_GMAC1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC1_AXI] = { -+ .bit = BIT(3), -+ .reg = TH1520_GMAC1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_GMAC_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_GMAC_AXI_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_GMAC_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_PADCTRL1_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_PADCTRL1_APSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VOSYS_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_VOSYS_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VOSYS_AXI_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_VOSYS_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VOSYS_AXI_X2X] = { -+ .bit = BIT(0), -+ .reg = TH1520_VOSYS_X2X_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MISC2VP_X2X] = { -+ .bit = BIT(0), -+ .reg = TH1520_MISC2VP_X2X_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSPSYS] = { -+ .bit = BIT(0), -+ .reg = TH1520_SUBSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VISYS] = { -+ .bit = BIT(1), -+ .reg = TH1520_SUBSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VOSYS] = { -+ .bit = BIT(2), -+ .reg = TH1520_SUBSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VPSYS] = { -+ .bit = BIT(3), -+ .reg = TH1520_SUBSYS_RST_CFG, -+ }, -+}; -+ -+static const struct th1520_reset_map th1520_dsp_resets[] = { -+ [TH1520_RESET_ID_X2X_DSP1] = { -+ .bit = BIT(0), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2X_DSP0] = { -+ .bit = BIT(1), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2X_SLAVE_DSP1] = { -+ .bit = BIT(2), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_X2X_SLAVE_DSP0] = { -+ .bit = BIT(3), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSP0_CORE] = { -+ .bit = BIT(8), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSP0_DEBUG] = { -+ .bit = BIT(9), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSP0_APB] = { -+ .bit = BIT(10), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSP1_CORE] = { -+ .bit = BIT(12), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSP1_DEBUG] = { -+ .bit = BIT(13), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSP1_APB] = { -+ .bit = BIT(14), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DSPSYS_APB] = { -+ .bit = BIT(16), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AXI4_DSPSYS_SLV] = { -+ .bit = BIT(20), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AXI4_DSPSYS] = { -+ .bit = BIT(24), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_AXI4_DSP_RS] = { -+ .bit = BIT(26), -+ .reg = TH1520_DSPSYS_RST_CFG, -+ }, -+}; -+ -+static const struct th1520_reset_map th1520_misc_resets[] = { -+ [TH1520_RESET_ID_EMMC_SDIO_CLKGEN] = { -+ .bit = BIT(0), -+ .reg = TH1520_EMMC_RST_CFG, -+ }, -+ [TH1520_RESET_ID_EMMC] = { -+ .bit = BIT(1), -+ .reg = TH1520_EMMC_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MISCSYS_AXI] = { -+ .bit = BIT(0), -+ .reg = TH1520_MISCSYS_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MISCSYS_AXI_APB] = { -+ .bit = BIT(1), -+ .reg = TH1520_MISCSYS_AXI_RST_CFG, -+ }, -+ [TH1520_RESET_ID_SDIO0] = { -+ .bit = BIT(0), -+ .reg = TH1520_SDIO0_RST_CFG, -+ }, -+ [TH1520_RESET_ID_SDIO1] = { -+ .bit = BIT(1), -+ .reg = TH1520_SDIO1_RST_CFG, -+ }, -+ [TH1520_RESET_ID_USB3_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_USB3_DRD_RST_CFG, -+ }, -+ [TH1520_RESET_ID_USB3_PHY] = { -+ .bit = BIT(1), -+ .reg = TH1520_USB3_DRD_RST_CFG, -+ }, -+ [TH1520_RESET_ID_USB3_VCC] = { -+ .bit = BIT(2), -+ .reg = TH1520_USB3_DRD_RST_CFG, -+ }, -+}; -+ -+static const struct th1520_reset_map th1520_vi_resets[] = { -+ [TH1520_RESET_ID_ISP0] = { -+ .bit = BIT(0), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_ISP1] = { -+ .bit = BIT(4), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CSI0_APB] = { -+ .bit = BIT(16), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CSI1_APB] = { -+ .bit = BIT(17), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_CSI2_APB] = { -+ .bit = BIT(18), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_MIPI_FIFO] = { -+ .bit = BIT(20), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_ISP_VENC_APB] = { -+ .bit = BIT(24), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VIPRE_APB] = { -+ .bit = BIT(28), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VIPRE_AXI] = { -+ .bit = BIT(29), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_DW200_APB] = { -+ .bit = BIT(31), -+ .reg = TH1520_VISYS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VISYS3_AXI] = { -+ .bit = BIT(8), -+ .reg = TH1520_VISYS_2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VISYS2_AXI] = { -+ .bit = BIT(9), -+ .reg = TH1520_VISYS_2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VISYS1_AXI] = { -+ .bit = BIT(10), -+ .reg = TH1520_VISYS_2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VISYS_AXI] = { -+ .bit = BIT(12), -+ .reg = TH1520_VISYS_2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VISYS_APB] = { -+ .bit = BIT(16), -+ .reg = TH1520_VISYS_2_RST_CFG, -+ }, -+ [TH1520_RESET_ID_ISP_VENC_AXI] = { -+ .bit = BIT(20), -+ .reg = TH1520_VISYS_2_RST_CFG, -+ }, -+}; -+ -+static const struct th1520_reset_map th1520_vp_resets[] = { -+ [TH1520_RESET_ID_VPSYS_AXI_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_AXIBUS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VPSYS_AXI] = { -+ .bit = BIT(1), -+ .reg = TH1520_AXIBUS_RST_CFG, -+ }, -+ [TH1520_RESET_ID_FCE_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_FCE_RST_CFG, -+ }, -+ [TH1520_RESET_ID_FCE_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_FCE_RST_CFG, -+ }, -+ [TH1520_RESET_ID_FCE_X2X_MASTER] = { -+ .bit = BIT(4), -+ .reg = TH1520_FCE_RST_CFG, -+ }, -+ [TH1520_RESET_ID_FCE_X2X_SLAVE] = { -+ .bit = BIT(5), -+ .reg = TH1520_FCE_RST_CFG, -+ }, -+ [TH1520_RESET_ID_G2D_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_G2D_RST_CFG, -+ }, -+ [TH1520_RESET_ID_G2D_ACLK] = { -+ .bit = BIT(1), -+ .reg = TH1520_G2D_RST_CFG, -+ }, -+ [TH1520_RESET_ID_G2D_CORE] = { -+ .bit = BIT(2), -+ .reg = TH1520_G2D_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VDEC_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_VDEC_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VDEC_ACLK] = { -+ .bit = BIT(1), -+ .reg = TH1520_VDEC_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VDEC_CORE] = { -+ .bit = BIT(2), -+ .reg = TH1520_VDEC_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VENC_APB] = { -+ .bit = BIT(0), -+ .reg = TH1520_VENC_RST_CFG, -+ }, -+ [TH1520_RESET_ID_VENC_CORE] = { -+ .bit = BIT(1), -+ .reg = TH1520_VENC_RST_CFG, -+ }, - }; - - static inline struct th1520_reset_priv * -@@ -170,8 +933,38 @@ static const struct th1520_reset_data th1520_reset_data = { - .num = ARRAY_SIZE(th1520_resets), - }; - -+static const struct th1520_reset_data th1520_ap_reset_data = { -+ .resets = th1520_ap_resets, -+ .num = ARRAY_SIZE(th1520_ap_resets), -+}; -+ -+static const struct th1520_reset_data th1520_dsp_reset_data = { -+ .resets = th1520_dsp_resets, -+ .num = ARRAY_SIZE(th1520_dsp_resets), -+}; -+ -+static const struct th1520_reset_data th1520_misc_reset_data = { -+ .resets = th1520_misc_resets, -+ .num = ARRAY_SIZE(th1520_misc_resets), -+}; -+ -+static const struct th1520_reset_data th1520_vi_reset_data = { -+ .resets = th1520_vi_resets, -+ .num = ARRAY_SIZE(th1520_vi_resets), -+}; -+ -+static const struct th1520_reset_data th1520_vp_reset_data = { -+ .resets = th1520_vp_resets, -+ .num = ARRAY_SIZE(th1520_vp_resets), -+}; -+ - static const struct of_device_id th1520_reset_match[] = { - { .compatible = "thead,th1520-reset", .data = &th1520_reset_data }, -+ { .compatible = "thead,th1520-reset-ap", .data = &th1520_ap_reset_data }, -+ { .compatible = "thead,th1520-reset-dsp", .data = &th1520_dsp_reset_data }, -+ { .compatible = "thead,th1520-reset-misc", .data = &th1520_misc_reset_data }, -+ { .compatible = "thead,th1520-reset-vi", .data = &th1520_vi_reset_data }, -+ { .compatible = "thead,th1520-reset-vp", .data = &th1520_vp_reset_data }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, th1520_reset_match); --- -2.53.0 - diff --git a/SPECS/linux-lts/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch b/SPECS/linux-lts/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch new file mode 100644 index 0000000000..23a5e1bf51 --- /dev/null +++ b/SPECS/linux-lts/0260-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch @@ -0,0 +1,46 @@ +From 2c946683705fc6706119c588fd5499c0c91b2369 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 26 Dec 2025 16:31:59 +0800 +Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: drop useless spaces + +Previously, the I2C driver had an extra leading space in column 0 of +included header lines. This commit removes the redundant whitespace. + +Signed-off-by: Troy Mitchell +Reviewed-by: Alex Elder +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/20251226-k1-i2c-ilcr-v5-1-b5807b7dd0e6@linux.spacemit.com +(cherry picked from commit 7b5073f9897f67af58b5bf17232bf60fc42e7ecd) +Signed-off-by: Han Gao +--- + drivers/i2c/busses/i2c-k1.c | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index afc6bdd68bd4..9152cf436bea 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -4,13 +4,13 @@ + */ + + #include +- #include +- #include +- #include +- #include +- #include +- #include +- #include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + + /* spacemit i2c registers */ + #define SPACEMIT_ICR 0x0 /* Control register */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0260-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch b/SPECS/linux-lts/0260-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch deleted file mode 100644 index ebe12f51cf..0000000000 --- a/SPECS/linux-lts/0260-UPSTREAM-riscv-dts-thead-Add-reset-controllers-of-mo.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 58993e46afb677069983e73a6be1ea0562b65730 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Tue, 14 Oct 2025 13:10:32 +0000 -Subject: [PATCH 260/467] UPSTREAM: riscv: dts: thead: Add reset controllers of - more subsystems for TH1520 - -Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The -one for AO subsystem is marked as reserved, since it may be used by AON -firmware. - -Reviewed-by: Drew Fustini -Signed-off-by: Yao Zi -Signed-off-by: Drew Fustini -(cherry picked from commit d8a174babf649346b6dad6784ae1e9bc8417af71) -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++ - 1 file changed, 37 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index c65b71d9a1b8..5e91dc1d2b9b 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -289,6 +289,12 @@ clint: timer@ffdc000000 { - <&cpu3_intc 3>, <&cpu3_intc 7>; - }; - -+ rst_vi: reset-controller@ffe4040100 { -+ compatible = "thead,th1520-reset-vi"; -+ reg = <0xff 0xe4040100 0x0 0x8>; -+ #reset-cells = <1>; -+ }; -+ - spi0: spi@ffe700c000 { - compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; - reg = <0xff 0xe700c000 0x0 0x1000>; -@@ -521,6 +527,18 @@ pwm: pwm@ffec01c000 { - #pwm-cells = <3>; - }; - -+ rst_misc: reset-controller@ffec02c000 { -+ compatible = "thead,th1520-reset-misc"; -+ reg = <0xff 0xec02c000 0x0 0x18>; -+ #reset-cells = <1>; -+ }; -+ -+ rst_vp: reset-controller@ffecc30000 { -+ compatible = "thead,th1520-reset-vp"; -+ reg = <0xff 0xecc30000 0x0 0x14>; -+ #reset-cells = <1>; -+ }; -+ - clk: clock-controller@ffef010000 { - compatible = "thead,th1520-clk-ap"; - reg = <0xff 0xef010000 0x0 0x1000>; -@@ -528,6 +546,18 @@ clk: clock-controller@ffef010000 { - #clock-cells = <1>; - }; - -+ rst_ap: reset-controller@ffef014000 { -+ compatible = "thead,th1520-reset-ap"; -+ reg = <0xff 0xef014000 0x0 0x1000>; -+ #reset-cells = <1>; -+ }; -+ -+ rst_dsp: reset-controller@ffef040028 { -+ compatible = "thead,th1520-reset-dsp"; -+ reg = <0xff 0xef040028 0x0 0x4>; -+ #reset-cells = <1>; -+ }; -+ - gpu: gpu@ffef400000 { - compatible = "thead,th1520-gpu", "img,img-bxm-4-64", - "img,img-rogue"; -@@ -766,6 +796,13 @@ aogpio: gpio-controller@0 { - }; - }; - -+ rst_ao: reset-controller@fffff44000 { -+ compatible = "thead,th1520-reset-ao"; -+ reg = <0xff 0xfff44000 0x0 0x2000>; -+ #reset-cells = <1>; -+ status = "reserved"; -+ }; -+ - padctrl_aosys: pinctrl@fffff4a000 { - compatible = "thead,th1520-pinctrl"; - reg = <0xff 0xfff4a000 0x0 0x2000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch b/SPECS/linux-lts/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch new file mode 100644 index 0000000000..dbb5d3dfe0 --- /dev/null +++ b/SPECS/linux-lts/0261-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch @@ -0,0 +1,40 @@ +From fa80698856016bcd983f8ac31a38e4f108170879 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:49 +0100 +Subject: [RUYI PATCH] UPSTREAM: clk: at91: pmc: #undef field_{get,prep}() + before definition + +Prepare for the advent of globally available common field_get() and +field_prep() macros by undefining the symbols before defining local +variants. This prevents redefinition warnings from the C preprocessor +when introducing the common macros later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Alexandre Belloni +Acked-by: Stephen Boyd +Acked-by: Claudiu Beznea +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit dbfe51513aae6bace00cc390e11cb486a64a63d2) +Signed-off-by: Han Gao +--- + drivers/clk/at91/pmc.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h +index 5daa32c4cf25..78a87d31463e 100644 +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -117,7 +117,9 @@ struct at91_clk_pms { + unsigned int parent; + }; + ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) ++#undef field_prep + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + + #define ndck(a, s) (a[s - 1].id + 1) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0261-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch b/SPECS/linux-lts/0261-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch deleted file mode 100644 index 7b49003d10..0000000000 --- a/SPECS/linux-lts/0261-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 15b0da3632a0e43073d2d2875332dc913c17ce30 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Fri, 24 Apr 2026 16:20:32 +0800 -Subject: [PATCH 261/467] UPSTREAM: clk: spacemit: k3: mark top_dclk as - CLK_IS_CRITICAL - -top_dclk is the DDR bus clock. If it is gated by clk_disable_unused, -all memory-mapped bus transactions cease to function, causing DMA -engines to hang and general system instability. - -Mark it CLK_IS_CRITICAL so the CCF never gates it during the -unused clock sweep. - -Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") -Reviewed-by: Brian Masney -Signed-off-by: Troy Mitchell -Signed-off-by: Stephen Boyd -(cherry picked from commit 3e75021f615ceee8562e6455c335936b39929ffb) -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index e98afd59f05c..bb8b75bdbdb3 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -846,7 +846,7 @@ static const struct clk_parent_data top_parents[] = { - CCU_PARENT_HW(pll6_d3), - }; - CCU_MUX_DIV_GATE_FC_DEFINE(top_dclk, top_parents, APMU_TOP_DCLK_CTRL, 5, 3, -- BIT(8), 2, 3, BIT(1), 0); -+ BIT(8), 2, 3, BIT(1), CLK_IS_CRITICAL); - - static const struct clk_parent_data ucie_parents[] = { - CCU_PARENT_HW(pll1_d8_307p2), --- -2.53.0 - diff --git a/SPECS/linux-lts/0262-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch b/SPECS/linux-lts/0262-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch deleted file mode 100644 index 3d3549d028..0000000000 --- a/SPECS/linux-lts/0262-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch +++ /dev/null @@ -1,53 +0,0 @@ -From d025cd979cf997c3b4e7096ac8dddcdd81e4c90c Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Wed, 29 Apr 2026 17:00:50 +0800 -Subject: [PATCH 262/467] UPSTREAM: ASoC: spacemit: fix RX DMA params not set - when TX is running - -When TX is already running (SSCR_SSE is set), the hw_params callback -returns early before setting up DMA parameters for the RX stream. This -prevents the capture path from configuring its DMA data properly. - -Move the SSCR_SSE check after DMA parameter setup and format -constraints, so both TX and RX streams get their DMA configuration -regardless of whether the hardware is already enabled. The early return -now only skips the register writes that would disrupt an active stream. - -Fixes: fce217449075 ("ASoC: spacemit: add i2s support for K1 SoC") -Signed-off-by: Troy Mitchell -Link: https://patch.msgid.link/20260429-k1-i2s-fix-v2-1-8d67835aaddc@linux.spacemit.com -Signed-off-by: Mark Brown -(cherry picked from commit ec0611868f2fcf29e4c2bebdc6702d3e1f272fec) -Signed-off-by: Han Gao ---- - sound/soc/spacemit/k1_i2s.c | 7 +++---- - 1 file changed, 3 insertions(+), 4 deletions(-) - -diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c -index b48c57bede37..03cca5d84503 100644 ---- a/sound/soc/spacemit/k1_i2s.c -+++ b/sound/soc/spacemit/k1_i2s.c -@@ -148,10 +148,6 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, - u32 val; - int ret; - -- val = readl(i2s->base + SSCR); -- if (val & SSCR_SSE) -- return 0; -- - dma_data = &i2s->playback_dma_data; - - if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) -@@ -199,6 +195,9 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, - } - - val = readl(i2s->base + SSCR); -+ if (val & SSCR_SSE) -+ return 0; -+ - val &= ~SSCR_DW_32BYTE; - val |= data_width; - writel(val, i2s->base + SSCR); --- -2.53.0 - diff --git a/SPECS/linux-lts/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch b/SPECS/linux-lts/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch new file mode 100644 index 0000000000..28c2c8a5db --- /dev/null +++ b/SPECS/linux-lts/0262-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch @@ -0,0 +1,36 @@ +From 0443b117c46d5530b02f66cefa36882031ef8c7f Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:50 +0100 +Subject: [RUYI PATCH] UPSTREAM: crypto: qat - #undef field_get() before local + definition + +Prepare for the advent of a globally available common field_get() macro +by undefining the symbol before defining a local variant. This prevents +redefinition warnings from the C preprocessor when introducing the common +macro later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Giovanni Cabiddu +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 7996cbdb3f8472bc4286c776d3fa39cf0c20237a) +Signed-off-by: Han Gao +--- + drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c +index 69295a9ddf0a..6186fafb4a7b 100644 +--- a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c ++++ b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c +@@ -11,6 +11,7 @@ + * pm_scnprint_table(), making it not compile time constant, so the compile + * asserts from FIELD_GET() or u32_get_bits() won't be fulfilled. + */ ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + + #define PM_INFO_MAX_KEY_LEN 21 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch b/SPECS/linux-lts/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch new file mode 100644 index 0000000000..5bd7f8e544 --- /dev/null +++ b/SPECS/linux-lts/0263-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch @@ -0,0 +1,36 @@ +From 8d1903d76c78fd4c3f54ccb47a84b23de8c65c5a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:51 +0100 +Subject: [RUYI PATCH] UPSTREAM: EDAC/ie31200: #undef field_get() before local + definition + +Prepare for the advent of a globally available common field_get() macro +by undefining the symbol before defining a local variant. This prevents +redefinition warnings from the C preprocessor when introducing the common +macro later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Qiuxu Zhuo +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit d51b09a0feb63029be64226502cbcf53adc434b0) +Signed-off-by: Han Gao +--- + drivers/edac/ie31200_edac.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c +index 5a080ab65476..72290f430126 100644 +--- a/drivers/edac/ie31200_edac.c ++++ b/drivers/edac/ie31200_edac.c +@@ -140,6 +140,7 @@ + #define IE31200_CAPID0_ECC BIT(1) + + /* Non-constant mask variant of FIELD_GET() */ ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + + static int nr_channels; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0263-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch b/SPECS/linux-lts/0263-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch deleted file mode 100644 index 8c37a3b093..0000000000 --- a/SPECS/linux-lts/0263-UPSTREAM-i2c-spacemit-drop-useless-spaces.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 695a3cc0b23ff691c0498a95c87551886e34dd5e Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Fri, 26 Dec 2025 16:31:59 +0800 -Subject: [PATCH 263/467] UPSTREAM: i2c: spacemit: drop useless spaces - -Previously, the I2C driver had an extra leading space in column 0 of -included header lines. This commit removes the redundant whitespace. - -Signed-off-by: Troy Mitchell -Reviewed-by: Alex Elder -Signed-off-by: Andi Shyti -Link: https://lore.kernel.org/r/20251226-k1-i2c-ilcr-v5-1-b5807b7dd0e6@linux.spacemit.com -(cherry picked from commit 7b5073f9897f67af58b5bf17232bf60fc42e7ecd) -Signed-off-by: Han Gao ---- - drivers/i2c/busses/i2c-k1.c | 14 +++++++------- - 1 file changed, 7 insertions(+), 7 deletions(-) - -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index afc6bdd68bd4..9152cf436bea 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -4,13 +4,13 @@ - */ - - #include -- #include -- #include -- #include -- #include -- #include -- #include -- #include -+#include -+#include -+#include -+#include -+#include -+#include -+#include - - /* spacemit i2c registers */ - #define SPACEMIT_ICR 0x0 /* Control register */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0264-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch b/SPECS/linux-lts/0264-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch deleted file mode 100644 index 0936955312..0000000000 --- a/SPECS/linux-lts/0264-UPSTREAM-clk-at91-pmc-undef-field_-get-prep-before-d.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 03331389d49d55c643b7b13c9dcfefff41959a64 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:49 +0100 -Subject: [PATCH 264/467] UPSTREAM: clk: at91: pmc: #undef field_{get,prep}() - before definition - -Prepare for the advent of globally available common field_get() and -field_prep() macros by undefining the symbols before defining local -variants. This prevents redefinition warnings from the C preprocessor -when introducing the common macros later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Alexandre Belloni -Acked-by: Stephen Boyd -Acked-by: Claudiu Beznea -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit dbfe51513aae6bace00cc390e11cb486a64a63d2) -Signed-off-by: Han Gao ---- - drivers/clk/at91/pmc.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h -index 5daa32c4cf25..78a87d31463e 100644 ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -117,7 +117,9 @@ struct at91_clk_pms { - unsigned int parent; - }; - -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -+#undef field_prep - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - - #define ndck(a, s) (a[s - 1].id + 1) --- -2.53.0 - diff --git a/SPECS/linux-lts/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch b/SPECS/linux-lts/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch new file mode 100644 index 0000000000..8d05fa846c --- /dev/null +++ b/SPECS/linux-lts/0264-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch @@ -0,0 +1,38 @@ +From 8490549e86aef53fa8416d6accaa31283186c10b Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:52 +0100 +Subject: [RUYI PATCH] UPSTREAM: gpio: aspeed: #undef field_{get,prep}() before + local definition + +Prepare for the advent of globally available common field_get() and +field_prep() macros by undefining the symbols before defining local +variants. This prevents redefinition warnings from the C preprocessor +when introducing the common macros later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Bartosz Golaszewski +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit d1e1a7271e97bf679d355777a10fa8c0dc259b86) +Signed-off-by: Han Gao +--- + drivers/gpio/gpio-aspeed.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c +index 3da37a0fda3f..6255b2080a41 100644 +--- a/drivers/gpio/gpio-aspeed.c ++++ b/drivers/gpio/gpio-aspeed.c +@@ -32,7 +32,9 @@ + #include "gpiolib.h" + + /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) ++#undef field_prep + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + + #define GPIO_G7_IRQ_STS_BASE 0x100 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0265-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch b/SPECS/linux-lts/0265-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch deleted file mode 100644 index 1b6177367f..0000000000 --- a/SPECS/linux-lts/0265-UPSTREAM-crypto-qat-undef-field_get-before-local-def.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 392241b97a7350e89982e3083de87d916d7823fe Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:50 +0100 -Subject: [PATCH 265/467] UPSTREAM: crypto: qat - #undef field_get() before - local definition - -Prepare for the advent of a globally available common field_get() macro -by undefining the symbol before defining a local variant. This prevents -redefinition warnings from the C preprocessor when introducing the common -macro later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Giovanni Cabiddu -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 7996cbdb3f8472bc4286c776d3fa39cf0c20237a) -Signed-off-by: Han Gao ---- - drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c -index 69295a9ddf0a..6186fafb4a7b 100644 ---- a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c -+++ b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c -@@ -11,6 +11,7 @@ - * pm_scnprint_table(), making it not compile time constant, so the compile - * asserts from FIELD_GET() or u32_get_bits() won't be fulfilled. - */ -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) - - #define PM_INFO_MAX_KEY_LEN 21 --- -2.53.0 - diff --git a/SPECS/linux-lts/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch b/SPECS/linux-lts/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch new file mode 100644 index 0000000000..7595552488 --- /dev/null +++ b/SPECS/linux-lts/0265-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch @@ -0,0 +1,36 @@ +From 2fda7cbf1f4289cbb26b12faf98ad22cbbf1c6b6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:53 +0100 +Subject: [RUYI PATCH] UPSTREAM: iio: dac: ad3530r: #undef field_prep() before + local definition + +Prepare for the advent of a globally available common field_prep() macro +by undefining the symbol before defining a local variant. This prevents +redefinition warnings from the C preprocessor when introducing the common +macro later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Jonathan Cameron +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 27856d2b2b0f259ba261a3e3e028cc75a70ae817) +Signed-off-by: Han Gao +--- + drivers/iio/dac/ad3530r.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c +index 6134613777b8..5684d11137f2 100644 +--- a/drivers/iio/dac/ad3530r.c ++++ b/drivers/iio/dac/ad3530r.c +@@ -54,6 +54,7 @@ + #define AD3531R_MAX_CHANNELS 4 + + /* Non-constant mask variant of FIELD_PREP() */ ++#undef field_prep + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + + enum ad3530r_mode { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0266-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch b/SPECS/linux-lts/0266-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch deleted file mode 100644 index d0db5deaca..0000000000 --- a/SPECS/linux-lts/0266-UPSTREAM-EDAC-ie31200-undef-field_get-before-local-d.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 6bfc62473ec56ec0afab933ca32873fe718bc7f2 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:51 +0100 -Subject: [PATCH 266/467] UPSTREAM: EDAC/ie31200: #undef field_get() before - local definition - -Prepare for the advent of a globally available common field_get() macro -by undefining the symbol before defining a local variant. This prevents -redefinition warnings from the C preprocessor when introducing the common -macro later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Qiuxu Zhuo -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit d51b09a0feb63029be64226502cbcf53adc434b0) -Signed-off-by: Han Gao ---- - drivers/edac/ie31200_edac.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c -index 5a080ab65476..72290f430126 100644 ---- a/drivers/edac/ie31200_edac.c -+++ b/drivers/edac/ie31200_edac.c -@@ -140,6 +140,7 @@ - #define IE31200_CAPID0_ECC BIT(1) - - /* Non-constant mask variant of FIELD_GET() */ -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) - - static int nr_channels; --- -2.53.0 - diff --git a/SPECS/linux-lts/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch b/SPECS/linux-lts/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch new file mode 100644 index 0000000000..9deec2c78e --- /dev/null +++ b/SPECS/linux-lts/0266-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch @@ -0,0 +1,38 @@ +From a31ca7ca552212b34bea5cb3fcf52759dc2a28a0 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:54 +0100 +Subject: [RUYI PATCH] UPSTREAM: iio: mlx90614: #undef field_{get,prep}() + before local definition + +Prepare for the advent of globally available common field_get() and +field_prep() macros by undefining the symbols before defining local +variants. This prevents redefinition warnings from the C preprocessor +when introducing the common macros later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Jonathan Cameron +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 8a838dabf145818e67b304997c21a055dd5943dc) +Signed-off-by: Han Gao +--- + drivers/iio/temperature/mlx90614.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/iio/temperature/mlx90614.c b/drivers/iio/temperature/mlx90614.c +index 8a44a00bfd5e..de5615fdb396 100644 +--- a/drivers/iio/temperature/mlx90614.c ++++ b/drivers/iio/temperature/mlx90614.c +@@ -69,7 +69,9 @@ + #define MLX90614_CONST_FIR 0x7 /* Fixed value for FIR part of low pass filter */ + + /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) ++#undef field_prep + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + + struct mlx_chip_info { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0267-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch b/SPECS/linux-lts/0267-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch deleted file mode 100644 index 61221b73a7..0000000000 --- a/SPECS/linux-lts/0267-UPSTREAM-gpio-aspeed-undef-field_-get-prep-before-lo.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 137405298c4f5336043e5c49266ff25e7485e66c Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:52 +0100 -Subject: [PATCH 267/467] UPSTREAM: gpio: aspeed: #undef field_{get,prep}() - before local definition - -Prepare for the advent of globally available common field_get() and -field_prep() macros by undefining the symbols before defining local -variants. This prevents redefinition warnings from the C preprocessor -when introducing the common macros later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Bartosz Golaszewski -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit d1e1a7271e97bf679d355777a10fa8c0dc259b86) -Signed-off-by: Han Gao ---- - drivers/gpio/gpio-aspeed.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c -index 3da37a0fda3f..6255b2080a41 100644 ---- a/drivers/gpio/gpio-aspeed.c -+++ b/drivers/gpio/gpio-aspeed.c -@@ -32,7 +32,9 @@ - #include "gpiolib.h" - - /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -+#undef field_prep - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - - #define GPIO_G7_IRQ_STS_BASE 0x100 --- -2.53.0 - diff --git a/SPECS/linux-lts/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch b/SPECS/linux-lts/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch new file mode 100644 index 0000000000..747d0f1115 --- /dev/null +++ b/SPECS/linux-lts/0267-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch @@ -0,0 +1,38 @@ +From 92ba8033d4f60d619ebeb8f1f465e68d66004e81 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:55 +0100 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: ma35: #undef field_{get,prep}() + before local definition + +Prepare for the advent of globally available common field_get() and +field_prep() macros by undefining the symbols before defining local +variants. This prevents redefinition warnings from the C preprocessor +when introducing the common macros later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Linus Walleij +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 2fc00c008e9043ca66b711cc0df78a4d94da2e34) +Signed-off-by: Han Gao +--- + drivers/pinctrl/nuvoton/pinctrl-ma35.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c +index cdad01d68a37..925dd717c9de 100644 +--- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c ++++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c +@@ -82,7 +82,9 @@ + #define MVOLT_3300 1 + + /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) ++#undef field_prep + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + + static const char * const gpio_group_name[] = { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0268-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch b/SPECS/linux-lts/0268-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch deleted file mode 100644 index 85b6350ba6..0000000000 --- a/SPECS/linux-lts/0268-UPSTREAM-iio-dac-ad3530r-undef-field_prep-before-loc.patch +++ /dev/null @@ -1,36 +0,0 @@ -From fa6237d944a588964130114d731d4b7480bb020d Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:53 +0100 -Subject: [PATCH 268/467] UPSTREAM: iio: dac: ad3530r: #undef field_prep() - before local definition - -Prepare for the advent of a globally available common field_prep() macro -by undefining the symbol before defining a local variant. This prevents -redefinition warnings from the C preprocessor when introducing the common -macro later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Jonathan Cameron -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 27856d2b2b0f259ba261a3e3e028cc75a70ae817) -Signed-off-by: Han Gao ---- - drivers/iio/dac/ad3530r.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c -index 6134613777b8..5684d11137f2 100644 ---- a/drivers/iio/dac/ad3530r.c -+++ b/drivers/iio/dac/ad3530r.c -@@ -54,6 +54,7 @@ - #define AD3531R_MAX_CHANNELS 4 - - /* Non-constant mask variant of FIELD_PREP() */ -+#undef field_prep - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - - enum ad3530r_mode { --- -2.53.0 - diff --git a/SPECS/linux-lts/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch b/SPECS/linux-lts/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch new file mode 100644 index 0000000000..a8085f2c11 --- /dev/null +++ b/SPECS/linux-lts/0268-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch @@ -0,0 +1,36 @@ +From f43d3afeb48fc78d1fa9aec7aaaefdf6964e4b6c Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:56 +0100 +Subject: [RUYI PATCH] UPSTREAM: soc: renesas: rz-sysc: #undef field_get() + before local definition + +Prepare for the advent of a globally available common field_get() macro +by undefining the symbol before defining a local variant. This prevents +redefinition warnings from the C preprocessor when introducing the common +macro later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Claudiu Beznea +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 138ab44108fad96c22b381ebfb6936ab9787aedc) +Signed-off-by: Han Gao +--- + drivers/soc/renesas/rz-sysc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c +index 19c1e666279b..a1487195dc87 100644 +--- a/drivers/soc/renesas/rz-sysc.c ++++ b/drivers/soc/renesas/rz-sysc.c +@@ -16,6 +16,7 @@ + + #include "rz-sysc.h" + ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + + /** +-- +2.53.0 + diff --git a/SPECS/linux-lts/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch b/SPECS/linux-lts/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch new file mode 100644 index 0000000000..ae69b76f2a --- /dev/null +++ b/SPECS/linux-lts/0269-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch @@ -0,0 +1,38 @@ +From a743678cdf95c66206f1cefd74ad8f2e3157f680 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:33:57 +0100 +Subject: [RUYI PATCH] UPSTREAM: ALSA: usb-audio: #undef field_{get,prep}() + before local definition + +Prepare for the advent of globally available common field_get() and +field_prep() macros by undefining the symbols before defining local +variants. This prevents redefinition warnings from the C preprocessor +when introducing the common macros later. + +Suggested-by: Yury Norov +Signed-off-by: Geert Uytterhoeven +Acked-by: Takashi Iwai +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 85a8ff11853110e59396f97b3239db40cc89e08c) +Signed-off-by: Han Gao +--- + sound/usb/mixer_quirks.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c +index 7126a2cf9e79..bf8f97d43299 100644 +--- a/sound/usb/mixer_quirks.c ++++ b/sound/usb/mixer_quirks.c +@@ -3309,7 +3309,9 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) + #define RME_DIGIFACE_INVERT BIT(31) + + /* Nonconst helpers */ ++#undef field_get + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) ++#undef field_prep + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + + static int snd_rme_digiface_write_reg(struct snd_kcontrol *kcontrol, int item, u16 mask, u16 val) +-- +2.53.0 + diff --git a/SPECS/linux-lts/0269-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch b/SPECS/linux-lts/0269-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch deleted file mode 100644 index 98a708ccec..0000000000 --- a/SPECS/linux-lts/0269-UPSTREAM-iio-mlx90614-undef-field_-get-prep-before-l.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 37980b18b9c919ed290f5d9d31476b4b92d67a1d Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:54 +0100 -Subject: [PATCH 269/467] UPSTREAM: iio: mlx90614: #undef field_{get,prep}() - before local definition - -Prepare for the advent of globally available common field_get() and -field_prep() macros by undefining the symbols before defining local -variants. This prevents redefinition warnings from the C preprocessor -when introducing the common macros later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Jonathan Cameron -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 8a838dabf145818e67b304997c21a055dd5943dc) -Signed-off-by: Han Gao ---- - drivers/iio/temperature/mlx90614.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/iio/temperature/mlx90614.c b/drivers/iio/temperature/mlx90614.c -index 8a44a00bfd5e..de5615fdb396 100644 ---- a/drivers/iio/temperature/mlx90614.c -+++ b/drivers/iio/temperature/mlx90614.c -@@ -69,7 +69,9 @@ - #define MLX90614_CONST_FIR 0x7 /* Fixed value for FIR part of low pass filter */ - - /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -+#undef field_prep - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - - struct mlx_chip_info { --- -2.53.0 - diff --git a/SPECS/linux-lts/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch b/SPECS/linux-lts/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch new file mode 100644 index 0000000000..9a78322adf --- /dev/null +++ b/SPECS/linux-lts/0270-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch @@ -0,0 +1,111 @@ +From c59127e75e8cf8ce74f12bd0fe0bb2574674fbe4 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:00 +0100 +Subject: [RUYI PATCH] UPSTREAM: bitfield: Add less-checking + __FIELD_{GET,PREP}() + +The BUILD_BUG_ON_MSG() check against "~0ull" works only with "unsigned +(long) long" _mask types. For constant masks, that condition is usually +met, as GENMASK() yields an UL value. The few places where the +constant mask is stored in an intermediate variable were fixed by +changing the variable type to u64 (see e.g. [1] and [2]). + +However, for non-constant masks, smaller unsigned types should be valid, +too, but currently lead to "result of comparison of constant +18446744073709551615 with expression of type ... is always +false"-warnings with clang and W=1. + +Hence refactor the __BF_FIELD_CHECK() helper, and factor out +__FIELD_{GET,PREP}(). The later lack the single problematic check, but +are otherwise identical to FIELD_{GET,PREP}(), and are intended to be +used in the fully non-const variants later. + +[1] commit 5c667d5a5a3ec166 ("clk: sp7021: Adjust width of _m in + HWM_FIELD_PREP()") +[2] commit cfd6fb45cfaf46fa ("crypto: ccree - avoid out-of-range + warnings from clang") + +Signed-off-by: Geert Uytterhoeven +Link: https://git.kernel.org/torvalds/c/5c667d5a5a3ec166 [1] +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 2a6c045640c38a407a39cd40c3c4d8dd2fd89aa8) +Signed-off-by: Han Gao +--- + include/linux/bitfield.h | 36 ++++++++++++++++++++++++++++-------- + 1 file changed, 28 insertions(+), 8 deletions(-) + +diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h +index 5355f8f806a9..bf8e0ae4b5b4 100644 +--- a/include/linux/bitfield.h ++++ b/include/linux/bitfield.h +@@ -60,7 +60,7 @@ + + #define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x)) + +-#define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \ ++#define __BF_FIELD_CHECK_MASK(_mask, _val, _pfx) \ + ({ \ + BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ + _pfx "mask is not constant"); \ +@@ -69,13 +69,33 @@ + ~((_mask) >> __bf_shf(_mask)) & \ + (0 + (_val)) : 0, \ + _pfx "value too large for the field"); \ +- BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \ +- __bf_cast_unsigned(_reg, ~0ull), \ +- _pfx "type of reg too small for mask"); \ + __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \ + (1ULL << __bf_shf(_mask))); \ + }) + ++#define __BF_FIELD_CHECK_REG(mask, reg, pfx) \ ++ BUILD_BUG_ON_MSG(__bf_cast_unsigned(mask, mask) > \ ++ __bf_cast_unsigned(reg, ~0ull), \ ++ pfx "type of reg too small for mask") ++ ++#define __BF_FIELD_CHECK(mask, reg, val, pfx) \ ++ ({ \ ++ __BF_FIELD_CHECK_MASK(mask, val, pfx); \ ++ __BF_FIELD_CHECK_REG(mask, reg, pfx); \ ++ }) ++ ++#define __FIELD_PREP(mask, val, pfx) \ ++ ({ \ ++ __BF_FIELD_CHECK_MASK(mask, val, pfx); \ ++ ((typeof(mask))(val) << __bf_shf(mask)) & (mask); \ ++ }) ++ ++#define __FIELD_GET(mask, reg, pfx) \ ++ ({ \ ++ __BF_FIELD_CHECK_MASK(mask, 0U, pfx); \ ++ (typeof(mask))(((reg) & (mask)) >> __bf_shf(mask)); \ ++ }) ++ + /** + * FIELD_MAX() - produce the maximum value representable by a field + * @_mask: shifted mask defining the field's length and position +@@ -112,8 +132,8 @@ + */ + #define FIELD_PREP(_mask, _val) \ + ({ \ +- __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ +- ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ ++ __BF_FIELD_CHECK_REG(_mask, 0ULL, "FIELD_PREP: "); \ ++ __FIELD_PREP(_mask, _val, "FIELD_PREP: "); \ + }) + + #define __BF_CHECK_POW2(n) BUILD_BUG_ON_ZERO(((n) & ((n) - 1)) != 0) +@@ -152,8 +172,8 @@ + */ + #define FIELD_GET(_mask, _reg) \ + ({ \ +- __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \ +- (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ ++ __BF_FIELD_CHECK_REG(_mask, _reg, "FIELD_GET: "); \ ++ __FIELD_GET(_mask, _reg, "FIELD_GET: "); \ + }) + + /** +-- +2.53.0 + diff --git a/SPECS/linux-lts/0270-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch b/SPECS/linux-lts/0270-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch deleted file mode 100644 index ead3cb8e47..0000000000 --- a/SPECS/linux-lts/0270-UPSTREAM-pinctrl-ma35-undef-field_-get-prep-before-l.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 5ec1150af9a71fda593306905af42d92479e2e05 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:55 +0100 -Subject: [PATCH 270/467] UPSTREAM: pinctrl: ma35: #undef field_{get,prep}() - before local definition - -Prepare for the advent of globally available common field_get() and -field_prep() macros by undefining the symbols before defining local -variants. This prevents redefinition warnings from the C preprocessor -when introducing the common macros later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Linus Walleij -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 2fc00c008e9043ca66b711cc0df78a4d94da2e34) -Signed-off-by: Han Gao ---- - drivers/pinctrl/nuvoton/pinctrl-ma35.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c -index cdad01d68a37..925dd717c9de 100644 ---- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c -+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c -@@ -82,7 +82,9 @@ - #define MVOLT_3300 1 - - /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -+#undef field_prep - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - - static const char * const gpio_group_name[] = { --- -2.53.0 - diff --git a/SPECS/linux-lts/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch b/SPECS/linux-lts/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch new file mode 100644 index 0000000000..68212a5dda --- /dev/null +++ b/SPECS/linux-lts/0271-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch @@ -0,0 +1,122 @@ +From 9508a0e99753a0d15b30509ead3b2314fe5d2572 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:01 +0100 +Subject: [RUYI PATCH] UPSTREAM: bitfield: Add non-constant field_{prep,get}() + helpers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The existing FIELD_{GET,PREP}() macros are limited to compile-time +constants. However, it is very common to prepare or extract bitfield +elements where the bitfield mask is not a compile-time constant. + +To avoid this limitation, the AT91 clock driver and several other +drivers already have their own non-const field_{prep,get}() macros. +Make them available for general use by adding them to +, and improve them slightly: + 1. Avoid evaluating macro parameters more than once, + 2. Replace "ffs() - 1" by "__ffs()", + 3. Support 64-bit use on 32-bit architectures, + 4. Wire field_{get,prep}() to FIELD_{GET,PREP}() when mask is + actually constant. + +This is deliberately not merged into the existing FIELD_{GET,PREP}() +macros, as people expressed the desire to keep stricter variants for +increased safety, or for performance critical paths. + +Yury: use __mask withing new macros. + +Signed-off-by: Geert Uytterhoeven +Acked-by: Alexandre Belloni +Acked-by: Jonathan Cameron +Acked-by: Crt Mori +Acked-by: Nuno Sá +Acked-by: Richard Genoud +Reviewed-by: Andy Shevchenko +Reviewed-by: Yury Norov (NVIDIA) +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit c1c6ab80b25c8db1e2ef5ae3ac8075d2c242ae13) +Signed-off-by: Han Gao +--- + include/linux/bitfield.h | 59 ++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 59 insertions(+) + +diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h +index bf8e0ae4b5b4..126dc5b380af 100644 +--- a/include/linux/bitfield.h ++++ b/include/linux/bitfield.h +@@ -17,6 +17,7 @@ + * FIELD_{GET,PREP} macros take as first parameter shifted mask + * from which they extract the base mask and shift amount. + * Mask must be a compilation time constant. ++ * field_{get,prep} are variants that take a non-const mask. + * + * Example: + * +@@ -240,4 +241,62 @@ __MAKE_OP(64) + #undef __MAKE_OP + #undef ____MAKE_OP + ++#define __field_prep(mask, val) \ ++ ({ \ ++ __auto_type __mask = (mask); \ ++ typeof(__mask) __val = (val); \ ++ unsigned int __shift = BITS_PER_TYPE(__mask) <= 32 ? \ ++ __ffs(__mask) : __ffs64(__mask); \ ++ (__val << __shift) & __mask; \ ++ }) ++ ++#define __field_get(mask, reg) \ ++ ({ \ ++ __auto_type __mask = (mask); \ ++ typeof(__mask) __reg = (reg); \ ++ unsigned int __shift = BITS_PER_TYPE(__mask) <= 32 ? \ ++ __ffs(__mask) : __ffs64(__mask); \ ++ (__reg & __mask) >> __shift; \ ++ }) ++ ++/** ++ * field_prep() - prepare a bitfield element ++ * @mask: shifted mask defining the field's length and position, must be ++ * non-zero ++ * @val: value to put in the field ++ * ++ * Return: field value masked and shifted to its final destination ++ * ++ * field_prep() masks and shifts up the value. The result should be ++ * combined with other fields of the bitfield using logical OR. ++ * Unlike FIELD_PREP(), @mask is not limited to a compile-time constant. ++ * Typical usage patterns are a value stored in a table, or calculated by ++ * shifting a constant by a variable number of bits. ++ * If you want to ensure that @mask is a compile-time constant, please use ++ * FIELD_PREP() directly instead. ++ */ ++#define field_prep(mask, val) \ ++ (__builtin_constant_p(mask) ? __FIELD_PREP(mask, val, "field_prep: ") \ ++ : __field_prep(mask, val)) ++ ++/** ++ * field_get() - extract a bitfield element ++ * @mask: shifted mask defining the field's length and position, must be ++ * non-zero ++ * @reg: value of entire bitfield ++ * ++ * Return: extracted field value ++ * ++ * field_get() extracts the field specified by @mask from the ++ * bitfield passed in as @reg by masking and shifting it down. ++ * Unlike FIELD_GET(), @mask is not limited to a compile-time constant. ++ * Typical usage patterns are a value stored in a table, or calculated by ++ * shifting a constant by a variable number of bits. ++ * If you want to ensure that @mask is a compile-time constant, please use ++ * FIELD_GET() directly instead. ++ */ ++#define field_get(mask, reg) \ ++ (__builtin_constant_p(mask) ? __FIELD_GET(mask, reg, "field_get: ") \ ++ : __field_get(mask, reg)) ++ + #endif +-- +2.53.0 + diff --git a/SPECS/linux-lts/0271-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch b/SPECS/linux-lts/0271-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch deleted file mode 100644 index a86fd11345..0000000000 --- a/SPECS/linux-lts/0271-UPSTREAM-soc-renesas-rz-sysc-undef-field_get-before-.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 189ddb8df1658f8de6447a903b626df7170869eb Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:56 +0100 -Subject: [PATCH 271/467] UPSTREAM: soc: renesas: rz-sysc: #undef field_get() - before local definition - -Prepare for the advent of a globally available common field_get() macro -by undefining the symbol before defining a local variant. This prevents -redefinition warnings from the C preprocessor when introducing the common -macro later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Claudiu Beznea -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 138ab44108fad96c22b381ebfb6936ab9787aedc) -Signed-off-by: Han Gao ---- - drivers/soc/renesas/rz-sysc.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c -index 19c1e666279b..a1487195dc87 100644 ---- a/drivers/soc/renesas/rz-sysc.c -+++ b/drivers/soc/renesas/rz-sysc.c -@@ -16,6 +16,7 @@ - - #include "rz-sysc.h" - -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) - - /** --- -2.53.0 - diff --git a/SPECS/linux-lts/0272-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch b/SPECS/linux-lts/0272-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch deleted file mode 100644 index 42d41b0ad2..0000000000 --- a/SPECS/linux-lts/0272-UPSTREAM-ALSA-usb-audio-undef-field_-get-prep-before.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 6293531e707d6e8a2b3ad5606ee2ed0e96173a30 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:33:57 +0100 -Subject: [PATCH 272/467] UPSTREAM: ALSA: usb-audio: #undef field_{get,prep}() - before local definition - -Prepare for the advent of globally available common field_get() and -field_prep() macros by undefining the symbols before defining local -variants. This prevents redefinition warnings from the C preprocessor -when introducing the common macros later. - -Suggested-by: Yury Norov -Signed-off-by: Geert Uytterhoeven -Acked-by: Takashi Iwai -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 85a8ff11853110e59396f97b3239db40cc89e08c) -Signed-off-by: Han Gao ---- - sound/usb/mixer_quirks.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c -index 7126a2cf9e79..bf8f97d43299 100644 ---- a/sound/usb/mixer_quirks.c -+++ b/sound/usb/mixer_quirks.c -@@ -3309,7 +3309,9 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) - #define RME_DIGIFACE_INVERT BIT(31) - - /* Nonconst helpers */ -+#undef field_get - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -+#undef field_prep - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - - static int snd_rme_digiface_write_reg(struct snd_kcontrol *kcontrol, int item, u16 mask, u16 val) --- -2.53.0 - diff --git a/SPECS/linux-lts/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch b/SPECS/linux-lts/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch new file mode 100644 index 0000000000..5f249092c8 --- /dev/null +++ b/SPECS/linux-lts/0272-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch @@ -0,0 +1,52 @@ +From 7ab27d3da88e00fd0367baf7b18fb5484ac4fd65 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:02 +0100 +Subject: [RUYI PATCH] UPSTREAM: clk: at91: Convert to common + field_{get,prep}() helpers + +Drop the driver-specific field_get() and field_prep() macros, in favor +of the globally available variants from . + +Signed-off-by: Geert Uytterhoeven +Acked-by: Alexandre Belloni +Acked-by: Stephen Boyd +Acked-by: Claudiu Beznea +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 0f8407a1f1c795c417e4c7750654a6024a3ec68b) +Signed-off-by: Han Gao +--- + drivers/clk/at91/clk-peripheral.c | 1 + + drivers/clk/at91/pmc.h | 5 ----- + 2 files changed, 1 insertion(+), 5 deletions(-) + +diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c +index e700f40fd87f..e7208c47268b 100644 +--- a/drivers/clk/at91/clk-peripheral.c ++++ b/drivers/clk/at91/clk-peripheral.c +@@ -3,6 +3,7 @@ + * Copyright (C) 2013 Boris BREZILLON + */ + ++#include + #include + #include + #include +diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h +index 78a87d31463e..543d7aee8d24 100644 +--- a/drivers/clk/at91/pmc.h ++++ b/drivers/clk/at91/pmc.h +@@ -117,11 +117,6 @@ struct at91_clk_pms { + unsigned int parent; + }; + +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +-#undef field_prep +-#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +- + #define ndck(a, s) (a[s - 1].id + 1) + #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0273-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch b/SPECS/linux-lts/0273-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch deleted file mode 100644 index 616035b685..0000000000 --- a/SPECS/linux-lts/0273-UPSTREAM-bitfield-Add-less-checking-__FIELD_-GET-PRE.patch +++ /dev/null @@ -1,111 +0,0 @@ -From 61e3d11ff249dabbd495ec0164ee8a1425826bb9 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:00 +0100 -Subject: [PATCH 273/467] UPSTREAM: bitfield: Add less-checking - __FIELD_{GET,PREP}() - -The BUILD_BUG_ON_MSG() check against "~0ull" works only with "unsigned -(long) long" _mask types. For constant masks, that condition is usually -met, as GENMASK() yields an UL value. The few places where the -constant mask is stored in an intermediate variable were fixed by -changing the variable type to u64 (see e.g. [1] and [2]). - -However, for non-constant masks, smaller unsigned types should be valid, -too, but currently lead to "result of comparison of constant -18446744073709551615 with expression of type ... is always -false"-warnings with clang and W=1. - -Hence refactor the __BF_FIELD_CHECK() helper, and factor out -__FIELD_{GET,PREP}(). The later lack the single problematic check, but -are otherwise identical to FIELD_{GET,PREP}(), and are intended to be -used in the fully non-const variants later. - -[1] commit 5c667d5a5a3ec166 ("clk: sp7021: Adjust width of _m in - HWM_FIELD_PREP()") -[2] commit cfd6fb45cfaf46fa ("crypto: ccree - avoid out-of-range - warnings from clang") - -Signed-off-by: Geert Uytterhoeven -Link: https://git.kernel.org/torvalds/c/5c667d5a5a3ec166 [1] -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 2a6c045640c38a407a39cd40c3c4d8dd2fd89aa8) -Signed-off-by: Han Gao ---- - include/linux/bitfield.h | 36 ++++++++++++++++++++++++++++-------- - 1 file changed, 28 insertions(+), 8 deletions(-) - -diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h -index 5355f8f806a9..bf8e0ae4b5b4 100644 ---- a/include/linux/bitfield.h -+++ b/include/linux/bitfield.h -@@ -60,7 +60,7 @@ - - #define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x)) - --#define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \ -+#define __BF_FIELD_CHECK_MASK(_mask, _val, _pfx) \ - ({ \ - BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ - _pfx "mask is not constant"); \ -@@ -69,13 +69,33 @@ - ~((_mask) >> __bf_shf(_mask)) & \ - (0 + (_val)) : 0, \ - _pfx "value too large for the field"); \ -- BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \ -- __bf_cast_unsigned(_reg, ~0ull), \ -- _pfx "type of reg too small for mask"); \ - __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \ - (1ULL << __bf_shf(_mask))); \ - }) - -+#define __BF_FIELD_CHECK_REG(mask, reg, pfx) \ -+ BUILD_BUG_ON_MSG(__bf_cast_unsigned(mask, mask) > \ -+ __bf_cast_unsigned(reg, ~0ull), \ -+ pfx "type of reg too small for mask") -+ -+#define __BF_FIELD_CHECK(mask, reg, val, pfx) \ -+ ({ \ -+ __BF_FIELD_CHECK_MASK(mask, val, pfx); \ -+ __BF_FIELD_CHECK_REG(mask, reg, pfx); \ -+ }) -+ -+#define __FIELD_PREP(mask, val, pfx) \ -+ ({ \ -+ __BF_FIELD_CHECK_MASK(mask, val, pfx); \ -+ ((typeof(mask))(val) << __bf_shf(mask)) & (mask); \ -+ }) -+ -+#define __FIELD_GET(mask, reg, pfx) \ -+ ({ \ -+ __BF_FIELD_CHECK_MASK(mask, 0U, pfx); \ -+ (typeof(mask))(((reg) & (mask)) >> __bf_shf(mask)); \ -+ }) -+ - /** - * FIELD_MAX() - produce the maximum value representable by a field - * @_mask: shifted mask defining the field's length and position -@@ -112,8 +132,8 @@ - */ - #define FIELD_PREP(_mask, _val) \ - ({ \ -- __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ -- ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ -+ __BF_FIELD_CHECK_REG(_mask, 0ULL, "FIELD_PREP: "); \ -+ __FIELD_PREP(_mask, _val, "FIELD_PREP: "); \ - }) - - #define __BF_CHECK_POW2(n) BUILD_BUG_ON_ZERO(((n) & ((n) - 1)) != 0) -@@ -152,8 +172,8 @@ - */ - #define FIELD_GET(_mask, _reg) \ - ({ \ -- __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \ -- (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ -+ __BF_FIELD_CHECK_REG(_mask, _reg, "FIELD_GET: "); \ -+ __FIELD_GET(_mask, _reg, "FIELD_GET: "); \ - }) - - /** --- -2.53.0 - diff --git a/SPECS/linux-lts/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch b/SPECS/linux-lts/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch new file mode 100644 index 0000000000..ad7e2a30bc --- /dev/null +++ b/SPECS/linux-lts/0273-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch @@ -0,0 +1,46 @@ +From e7cc1307805b330990170342cd2e17a4790cae37 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:03 +0100 +Subject: [RUYI PATCH] UPSTREAM: crypto: qat - convert to common field_get() + helper + +Drop the driver-specific field_get() macro, in favor of the globally +available variant from . + +Signed-off-by: Geert Uytterhoeven +Acked-by: Giovanni Cabiddu +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 350f06c9e2c97aca009fa10e8636ecf297ccd330) +Signed-off-by: Han Gao +--- + drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c | 9 +-------- + 1 file changed, 1 insertion(+), 8 deletions(-) + +diff --git a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c +index 6186fafb4a7b..4ccc94ed9493 100644 +--- a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c ++++ b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c +@@ -1,19 +1,12 @@ + // SPDX-License-Identifier: GPL-2.0-only + /* Copyright(c) 2025 Intel Corporation */ ++#include + #include + #include + #include + + #include "adf_pm_dbgfs_utils.h" + +-/* +- * This is needed because a variable is used to index the mask at +- * pm_scnprint_table(), making it not compile time constant, so the compile +- * asserts from FIELD_GET() or u32_get_bits() won't be fulfilled. +- */ +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +- + #define PM_INFO_MAX_KEY_LEN 21 + + static int pm_scnprint_table(char *buff, const struct pm_status_row *table, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch b/SPECS/linux-lts/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch new file mode 100644 index 0000000000..15800bac47 --- /dev/null +++ b/SPECS/linux-lts/0274-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch @@ -0,0 +1,44 @@ +From 435c6fcc72eff501ecd29fabd2fedec939c67aa6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:04 +0100 +Subject: [RUYI PATCH] UPSTREAM: EDAC/ie31200: Convert to common field_get() + helper + +Drop the driver-specific field_get() macro, in favor of the globally +available variant from . + +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Qiuxu Zhuo +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 331a1457d8d5d233435633fcea116abeb775c4b4) +Signed-off-by: Han Gao +--- + drivers/edac/ie31200_edac.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c +index 72290f430126..dfc9a9cecd74 100644 +--- a/drivers/edac/ie31200_edac.c ++++ b/drivers/edac/ie31200_edac.c +@@ -44,6 +44,7 @@ + * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. + */ + ++#include + #include + #include + #include +@@ -139,10 +140,6 @@ + #define IE31200_CAPID0_DDPCD BIT(6) + #define IE31200_CAPID0_ECC BIT(1) + +-/* Non-constant mask variant of FIELD_GET() */ +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +- + static int nr_channels; + static struct pci_dev *mci_pdev; + static int ie31200_registered = 1; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0274-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch b/SPECS/linux-lts/0274-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch deleted file mode 100644 index 7c6fbc972f..0000000000 --- a/SPECS/linux-lts/0274-UPSTREAM-bitfield-Add-non-constant-field_-prep-get-h.patch +++ /dev/null @@ -1,122 +0,0 @@ -From e7e8f944057ad724dd477ac753b3c5b9c451fdcb Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:01 +0100 -Subject: [PATCH 274/467] UPSTREAM: bitfield: Add non-constant - field_{prep,get}() helpers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The existing FIELD_{GET,PREP}() macros are limited to compile-time -constants. However, it is very common to prepare or extract bitfield -elements where the bitfield mask is not a compile-time constant. - -To avoid this limitation, the AT91 clock driver and several other -drivers already have their own non-const field_{prep,get}() macros. -Make them available for general use by adding them to -, and improve them slightly: - 1. Avoid evaluating macro parameters more than once, - 2. Replace "ffs() - 1" by "__ffs()", - 3. Support 64-bit use on 32-bit architectures, - 4. Wire field_{get,prep}() to FIELD_{GET,PREP}() when mask is - actually constant. - -This is deliberately not merged into the existing FIELD_{GET,PREP}() -macros, as people expressed the desire to keep stricter variants for -increased safety, or for performance critical paths. - -Yury: use __mask withing new macros. - -Signed-off-by: Geert Uytterhoeven -Acked-by: Alexandre Belloni -Acked-by: Jonathan Cameron -Acked-by: Crt Mori -Acked-by: Nuno Sá -Acked-by: Richard Genoud -Reviewed-by: Andy Shevchenko -Reviewed-by: Yury Norov (NVIDIA) -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit c1c6ab80b25c8db1e2ef5ae3ac8075d2c242ae13) -Signed-off-by: Han Gao ---- - include/linux/bitfield.h | 59 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 59 insertions(+) - -diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h -index bf8e0ae4b5b4..126dc5b380af 100644 ---- a/include/linux/bitfield.h -+++ b/include/linux/bitfield.h -@@ -17,6 +17,7 @@ - * FIELD_{GET,PREP} macros take as first parameter shifted mask - * from which they extract the base mask and shift amount. - * Mask must be a compilation time constant. -+ * field_{get,prep} are variants that take a non-const mask. - * - * Example: - * -@@ -240,4 +241,62 @@ __MAKE_OP(64) - #undef __MAKE_OP - #undef ____MAKE_OP - -+#define __field_prep(mask, val) \ -+ ({ \ -+ __auto_type __mask = (mask); \ -+ typeof(__mask) __val = (val); \ -+ unsigned int __shift = BITS_PER_TYPE(__mask) <= 32 ? \ -+ __ffs(__mask) : __ffs64(__mask); \ -+ (__val << __shift) & __mask; \ -+ }) -+ -+#define __field_get(mask, reg) \ -+ ({ \ -+ __auto_type __mask = (mask); \ -+ typeof(__mask) __reg = (reg); \ -+ unsigned int __shift = BITS_PER_TYPE(__mask) <= 32 ? \ -+ __ffs(__mask) : __ffs64(__mask); \ -+ (__reg & __mask) >> __shift; \ -+ }) -+ -+/** -+ * field_prep() - prepare a bitfield element -+ * @mask: shifted mask defining the field's length and position, must be -+ * non-zero -+ * @val: value to put in the field -+ * -+ * Return: field value masked and shifted to its final destination -+ * -+ * field_prep() masks and shifts up the value. The result should be -+ * combined with other fields of the bitfield using logical OR. -+ * Unlike FIELD_PREP(), @mask is not limited to a compile-time constant. -+ * Typical usage patterns are a value stored in a table, or calculated by -+ * shifting a constant by a variable number of bits. -+ * If you want to ensure that @mask is a compile-time constant, please use -+ * FIELD_PREP() directly instead. -+ */ -+#define field_prep(mask, val) \ -+ (__builtin_constant_p(mask) ? __FIELD_PREP(mask, val, "field_prep: ") \ -+ : __field_prep(mask, val)) -+ -+/** -+ * field_get() - extract a bitfield element -+ * @mask: shifted mask defining the field's length and position, must be -+ * non-zero -+ * @reg: value of entire bitfield -+ * -+ * Return: extracted field value -+ * -+ * field_get() extracts the field specified by @mask from the -+ * bitfield passed in as @reg by masking and shifting it down. -+ * Unlike FIELD_GET(), @mask is not limited to a compile-time constant. -+ * Typical usage patterns are a value stored in a table, or calculated by -+ * shifting a constant by a variable number of bits. -+ * If you want to ensure that @mask is a compile-time constant, please use -+ * FIELD_GET() directly instead. -+ */ -+#define field_get(mask, reg) \ -+ (__builtin_constant_p(mask) ? __FIELD_GET(mask, reg, "field_get: ") \ -+ : __field_get(mask, reg)) -+ - #endif --- -2.53.0 - diff --git a/SPECS/linux-lts/0275-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch b/SPECS/linux-lts/0275-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch deleted file mode 100644 index 5b6ce03e18..0000000000 --- a/SPECS/linux-lts/0275-UPSTREAM-clk-at91-Convert-to-common-field_-get-prep-.patch +++ /dev/null @@ -1,52 +0,0 @@ -From ee4a40739254d7da1f8363a89f53765733b99b28 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:02 +0100 -Subject: [PATCH 275/467] UPSTREAM: clk: at91: Convert to common - field_{get,prep}() helpers - -Drop the driver-specific field_get() and field_prep() macros, in favor -of the globally available variants from . - -Signed-off-by: Geert Uytterhoeven -Acked-by: Alexandre Belloni -Acked-by: Stephen Boyd -Acked-by: Claudiu Beznea -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 0f8407a1f1c795c417e4c7750654a6024a3ec68b) -Signed-off-by: Han Gao ---- - drivers/clk/at91/clk-peripheral.c | 1 + - drivers/clk/at91/pmc.h | 5 ----- - 2 files changed, 1 insertion(+), 5 deletions(-) - -diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c -index e700f40fd87f..e7208c47268b 100644 ---- a/drivers/clk/at91/clk-peripheral.c -+++ b/drivers/clk/at91/clk-peripheral.c -@@ -3,6 +3,7 @@ - * Copyright (C) 2013 Boris BREZILLON - */ - -+#include - #include - #include - #include -diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h -index 78a87d31463e..543d7aee8d24 100644 ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -117,11 +117,6 @@ struct at91_clk_pms { - unsigned int parent; - }; - --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) --#undef field_prep --#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -- - #define ndck(a, s) (a[s - 1].id + 1) - #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) - --- -2.53.0 - diff --git a/SPECS/linux-lts/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch b/SPECS/linux-lts/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch new file mode 100644 index 0000000000..8bbf1a93ec --- /dev/null +++ b/SPECS/linux-lts/0275-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch @@ -0,0 +1,45 @@ +From d812b182981498ab3054a3c64531710d096f4e8a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:05 +0100 +Subject: [RUYI PATCH] UPSTREAM: gpio: aspeed: Convert to common + field_{get,prep}() helpers + +Drop the driver-specific field_get() and field_prep() macros, in favor +of the globally available variants from . + +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 2ef26ba8192c6ef49dd9ed1a95f990c438085517) +Signed-off-by: Han Gao +--- + drivers/gpio/gpio-aspeed.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c +index 6255b2080a41..37f2543e3909 100644 +--- a/drivers/gpio/gpio-aspeed.c ++++ b/drivers/gpio/gpio-aspeed.c +@@ -5,6 +5,7 @@ + * Joel Stanley + */ + ++#include + #include + #include + #include +@@ -31,12 +32,6 @@ + #include + #include "gpiolib.h" + +-/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +-#undef field_prep +-#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +- + #define GPIO_G7_IRQ_STS_BASE 0x100 + #define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4) + #define GPIO_G7_CTRL_REG_BASE 0x180 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0276-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch b/SPECS/linux-lts/0276-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch deleted file mode 100644 index 98b12e48bb..0000000000 --- a/SPECS/linux-lts/0276-UPSTREAM-crypto-qat-convert-to-common-field_get-help.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 7a384b9f65e72b723c2c45d4d331ac597edb9b2a Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:03 +0100 -Subject: [PATCH 276/467] UPSTREAM: crypto: qat - convert to common field_get() - helper - -Drop the driver-specific field_get() macro, in favor of the globally -available variant from . - -Signed-off-by: Geert Uytterhoeven -Acked-by: Giovanni Cabiddu -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 350f06c9e2c97aca009fa10e8636ecf297ccd330) -Signed-off-by: Han Gao ---- - drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c | 9 +-------- - 1 file changed, 1 insertion(+), 8 deletions(-) - -diff --git a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c -index 6186fafb4a7b..4ccc94ed9493 100644 ---- a/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c -+++ b/drivers/crypto/intel/qat/qat_common/adf_pm_dbgfs_utils.c -@@ -1,19 +1,12 @@ - // SPDX-License-Identifier: GPL-2.0-only - /* Copyright(c) 2025 Intel Corporation */ -+#include - #include - #include - #include - - #include "adf_pm_dbgfs_utils.h" - --/* -- * This is needed because a variable is used to index the mask at -- * pm_scnprint_table(), making it not compile time constant, so the compile -- * asserts from FIELD_GET() or u32_get_bits() won't be fulfilled. -- */ --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -- - #define PM_INFO_MAX_KEY_LEN 21 - - static int pm_scnprint_table(char *buff, const struct pm_status_row *table, --- -2.53.0 - diff --git a/SPECS/linux-lts/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch b/SPECS/linux-lts/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch new file mode 100644 index 0000000000..0c7f9de5cc --- /dev/null +++ b/SPECS/linux-lts/0276-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch @@ -0,0 +1,36 @@ +From 8c762e56b97e2dfa47081feffdf43f03d3f977e5 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:06 +0100 +Subject: [RUYI PATCH] UPSTREAM: iio: dac: Convert to common field_prep() + helper + +Drop the driver-specific field_prep() macro, in favor of the globally +available variant from . + +Signed-off-by: Geert Uytterhoeven +Acked-by: Jonathan Cameron +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 54bfd90ca3b41567cbfdac2f633ae329eb3a665a) +Signed-off-by: Han Gao +--- + drivers/iio/dac/ad3530r.c | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c +index 5684d11137f2..b97b46090d80 100644 +--- a/drivers/iio/dac/ad3530r.c ++++ b/drivers/iio/dac/ad3530r.c +@@ -53,10 +53,6 @@ + #define AD3530R_MAX_CHANNELS 8 + #define AD3531R_MAX_CHANNELS 4 + +-/* Non-constant mask variant of FIELD_PREP() */ +-#undef field_prep +-#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +- + enum ad3530r_mode { + AD3530R_NORMAL_OP, + AD3530R_POWERDOWN_1K, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0277-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch b/SPECS/linux-lts/0277-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch deleted file mode 100644 index 137572c73d..0000000000 --- a/SPECS/linux-lts/0277-UPSTREAM-EDAC-ie31200-Convert-to-common-field_get-he.patch +++ /dev/null @@ -1,44 +0,0 @@ -From ce4af8fd49443cd868f89dbe502bbcca49cd05dd Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:04 +0100 -Subject: [PATCH 277/467] UPSTREAM: EDAC/ie31200: Convert to common field_get() - helper - -Drop the driver-specific field_get() macro, in favor of the globally -available variant from . - -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Qiuxu Zhuo -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 331a1457d8d5d233435633fcea116abeb775c4b4) -Signed-off-by: Han Gao ---- - drivers/edac/ie31200_edac.c | 5 +---- - 1 file changed, 1 insertion(+), 4 deletions(-) - -diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c -index 72290f430126..dfc9a9cecd74 100644 ---- a/drivers/edac/ie31200_edac.c -+++ b/drivers/edac/ie31200_edac.c -@@ -44,6 +44,7 @@ - * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. - */ - -+#include - #include - #include - #include -@@ -139,10 +140,6 @@ - #define IE31200_CAPID0_DDPCD BIT(6) - #define IE31200_CAPID0_ECC BIT(1) - --/* Non-constant mask variant of FIELD_GET() */ --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -- - static int nr_channels; - static struct pci_dev *mci_pdev; - static int ie31200_registered = 1; --- -2.53.0 - diff --git a/SPECS/linux-lts/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch b/SPECS/linux-lts/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch new file mode 100644 index 0000000000..5dec21e9bb --- /dev/null +++ b/SPECS/linux-lts/0277-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch @@ -0,0 +1,47 @@ +From c7ea1c7ee160166a1ed64ca27681872c97335904 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:07 +0100 +Subject: [RUYI PATCH] UPSTREAM: iio: mlx90614: Convert to common + field_{get,prep}() helpers + +Drop the driver-specific field_get() and field_prep() macros, in favor +of the globally available variants from . + +Signed-off-by: Geert Uytterhoeven +Acked-by: Jonathan Cameron +Acked-by: Crt Mori +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 1fe1c28a108e4953f083c0106575ee0eccc296ae) +Signed-off-by: Han Gao +--- + drivers/iio/temperature/mlx90614.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +diff --git a/drivers/iio/temperature/mlx90614.c b/drivers/iio/temperature/mlx90614.c +index de5615fdb396..1ad21b73e1b4 100644 +--- a/drivers/iio/temperature/mlx90614.c ++++ b/drivers/iio/temperature/mlx90614.c +@@ -22,6 +22,7 @@ + * the "wakeup" GPIO is not given, power management will be disabled. + */ + ++#include + #include + #include + #include +@@ -68,12 +69,6 @@ + #define MLX90614_CONST_SCALE 20 /* Scale in milliKelvin (0.02 * 1000) */ + #define MLX90614_CONST_FIR 0x7 /* Fixed value for FIR part of low pass filter */ + +-/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +-#undef field_prep +-#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +- + struct mlx_chip_info { + /* EEPROM offsets with 16-bit data, MSB first */ + /* emissivity correction coefficient */ +-- +2.53.0 + diff --git a/SPECS/linux-lts/0278-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch b/SPECS/linux-lts/0278-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch deleted file mode 100644 index 071ded89ee..0000000000 --- a/SPECS/linux-lts/0278-UPSTREAM-gpio-aspeed-Convert-to-common-field_-get-pr.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 60aa83cc5e5af809b2fd0c7b94edda8ab4da2eb1 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:05 +0100 -Subject: [PATCH 278/467] UPSTREAM: gpio: aspeed: Convert to common - field_{get,prep}() helpers - -Drop the driver-specific field_get() and field_prep() macros, in favor -of the globally available variants from . - -Signed-off-by: Geert Uytterhoeven -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 2ef26ba8192c6ef49dd9ed1a95f990c438085517) -Signed-off-by: Han Gao ---- - drivers/gpio/gpio-aspeed.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - -diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c -index 6255b2080a41..37f2543e3909 100644 ---- a/drivers/gpio/gpio-aspeed.c -+++ b/drivers/gpio/gpio-aspeed.c -@@ -5,6 +5,7 @@ - * Joel Stanley - */ - -+#include - #include - #include - #include -@@ -31,12 +32,6 @@ - #include - #include "gpiolib.h" - --/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) --#undef field_prep --#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -- - #define GPIO_G7_IRQ_STS_BASE 0x100 - #define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4) - #define GPIO_G7_CTRL_REG_BASE 0x180 --- -2.53.0 - diff --git a/SPECS/linux-lts/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch b/SPECS/linux-lts/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch new file mode 100644 index 0000000000..d757b43507 --- /dev/null +++ b/SPECS/linux-lts/0278-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch @@ -0,0 +1,38 @@ +From 2cbda24297eace09de563cb06455c5936a00088e Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:08 +0100 +Subject: [RUYI PATCH] UPSTREAM: pinctrl: ma35: Convert to common + field_{get,prep}() helpers + +Drop the driver-specific field_get() and field_prep() macros, in favor +of the globally available variants from . + +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Linus Walleij +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit bb0e7fda87753a973cb4a86c22905b1177f00d4e) +Signed-off-by: Han Gao +--- + drivers/pinctrl/nuvoton/pinctrl-ma35.c | 6 ------ + 1 file changed, 6 deletions(-) + +diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c +index 925dd717c9de..8d71dc53cc1d 100644 +--- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c ++++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c +@@ -81,12 +81,6 @@ + #define MVOLT_1800 0 + #define MVOLT_3300 1 + +-/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +-#undef field_prep +-#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +- + static const char * const gpio_group_name[] = { + "gpioa", "gpiob", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", + "gpioh", "gpioi", "gpioj", "gpiok", "gpiol", "gpiom", "gpion", +-- +2.53.0 + diff --git a/SPECS/linux-lts/0279-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch b/SPECS/linux-lts/0279-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch deleted file mode 100644 index 36b95a7cc1..0000000000 --- a/SPECS/linux-lts/0279-UPSTREAM-iio-dac-Convert-to-common-field_prep-helper.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 762f69a712f2a14242aa86c29e0cefe82355d45e Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:06 +0100 -Subject: [PATCH 279/467] UPSTREAM: iio: dac: Convert to common field_prep() - helper - -Drop the driver-specific field_prep() macro, in favor of the globally -available variant from . - -Signed-off-by: Geert Uytterhoeven -Acked-by: Jonathan Cameron -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 54bfd90ca3b41567cbfdac2f633ae329eb3a665a) -Signed-off-by: Han Gao ---- - drivers/iio/dac/ad3530r.c | 4 ---- - 1 file changed, 4 deletions(-) - -diff --git a/drivers/iio/dac/ad3530r.c b/drivers/iio/dac/ad3530r.c -index 5684d11137f2..b97b46090d80 100644 ---- a/drivers/iio/dac/ad3530r.c -+++ b/drivers/iio/dac/ad3530r.c -@@ -53,10 +53,6 @@ - #define AD3530R_MAX_CHANNELS 8 - #define AD3531R_MAX_CHANNELS 4 - --/* Non-constant mask variant of FIELD_PREP() */ --#undef field_prep --#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -- - enum ad3530r_mode { - AD3530R_NORMAL_OP, - AD3530R_POWERDOWN_1K, --- -2.53.0 - diff --git a/SPECS/linux-lts/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch b/SPECS/linux-lts/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch new file mode 100644 index 0000000000..f9d9f0c492 --- /dev/null +++ b/SPECS/linux-lts/0279-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch @@ -0,0 +1,43 @@ +From 8833c4b417190dce1a91dbf31da82221a266f133 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:09 +0100 +Subject: [RUYI PATCH] UPSTREAM: soc: renesas: rz-sysc: Convert to common + field_get() helper + +Drop the driver-specific field_get() macro, in favor of the globally +available variant from . + +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Claudiu Beznea +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 610c4408a2f7a09a00f656459e762ee1e21bbd7b) +Signed-off-by: Han Gao +--- + drivers/soc/renesas/rz-sysc.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c +index a1487195dc87..ae727d9c8cc5 100644 +--- a/drivers/soc/renesas/rz-sysc.c ++++ b/drivers/soc/renesas/rz-sysc.c +@@ -5,6 +5,7 @@ + * Copyright (C) 2024 Renesas Electronics Corp. + */ + ++#include + #include + #include + #include +@@ -16,9 +17,6 @@ + + #include "rz-sysc.h" + +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +- + /** + * struct rz_sysc - RZ SYSC private data structure + * @base: SYSC base address +-- +2.53.0 + diff --git a/SPECS/linux-lts/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch b/SPECS/linux-lts/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch new file mode 100644 index 0000000000..9e36e61789 --- /dev/null +++ b/SPECS/linux-lts/0280-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch @@ -0,0 +1,38 @@ +From d565f3b6ace21a51f62812c86add16af8553952d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:10 +0100 +Subject: [RUYI PATCH] UPSTREAM: ALSA: usb-audio: Convert to common + field_{get,prep}() helpers + +Drop the driver-specific field_get() and field_prep() macros, in favor +of the globally available variants from . + +Signed-off-by: Geert Uytterhoeven +Acked-by: Takashi Iwai +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit b1cff2f4b2391a13bd3e9263502072df1ee5d035) +Signed-off-by: Han Gao +--- + sound/usb/mixer_quirks.c | 6 ------ + 1 file changed, 6 deletions(-) + +diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c +index bf8f97d43299..6069d9267c6c 100644 +--- a/sound/usb/mixer_quirks.c ++++ b/sound/usb/mixer_quirks.c +@@ -3308,12 +3308,6 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) + #define RME_DIGIFACE_REGISTER(reg, mask) (((reg) << 16) | (mask)) + #define RME_DIGIFACE_INVERT BIT(31) + +-/* Nonconst helpers */ +-#undef field_get +-#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +-#undef field_prep +-#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +- + static int snd_rme_digiface_write_reg(struct snd_kcontrol *kcontrol, int item, u16 mask, u16 val) + { + struct usb_mixer_elem_list *list = snd_kcontrol_chip(kcontrol); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0280-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch b/SPECS/linux-lts/0280-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch deleted file mode 100644 index 88ee4da2de..0000000000 --- a/SPECS/linux-lts/0280-UPSTREAM-iio-mlx90614-Convert-to-common-field_-get-p.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 2ddc0140e0d67f1413257af9982a7bc533c450f1 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:07 +0100 -Subject: [PATCH 280/467] UPSTREAM: iio: mlx90614: Convert to common - field_{get,prep}() helpers - -Drop the driver-specific field_get() and field_prep() macros, in favor -of the globally available variants from . - -Signed-off-by: Geert Uytterhoeven -Acked-by: Jonathan Cameron -Acked-by: Crt Mori -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 1fe1c28a108e4953f083c0106575ee0eccc296ae) -Signed-off-by: Han Gao ---- - drivers/iio/temperature/mlx90614.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - -diff --git a/drivers/iio/temperature/mlx90614.c b/drivers/iio/temperature/mlx90614.c -index de5615fdb396..1ad21b73e1b4 100644 ---- a/drivers/iio/temperature/mlx90614.c -+++ b/drivers/iio/temperature/mlx90614.c -@@ -22,6 +22,7 @@ - * the "wakeup" GPIO is not given, power management will be disabled. - */ - -+#include - #include - #include - #include -@@ -68,12 +69,6 @@ - #define MLX90614_CONST_SCALE 20 /* Scale in milliKelvin (0.02 * 1000) */ - #define MLX90614_CONST_FIR 0x7 /* Fixed value for FIR part of low pass filter */ - --/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) --#undef field_prep --#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -- - struct mlx_chip_info { - /* EEPROM offsets with 16-bit data, MSB first */ - /* emissivity correction coefficient */ --- -2.53.0 - diff --git a/SPECS/linux-lts/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch b/SPECS/linux-lts/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch new file mode 100644 index 0000000000..383627c806 --- /dev/null +++ b/SPECS/linux-lts/0281-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch @@ -0,0 +1,129 @@ +From 019a7bd0c854f0ec67ae6e379c46f05ccf4be4dd Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:13 +0100 +Subject: [RUYI PATCH] UPSTREAM: clk: renesas: Use bitfield helpers + +Use the FIELD_{GET,PREP}() and field_{get,prep}() helpers for const +respective non-const bitfields, instead of open-coding the same +operations. + +Signed-off-by: Geert Uytterhoeven +Reviewed-by: Stephen Boyd +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit 3937b05bb78f3ad1e8887b91b9a97ea05ac0a4a8) +Signed-off-by: Han Gao +--- + drivers/clk/renesas/clk-div6.c | 6 +++--- + drivers/clk/renesas/rcar-gen3-cpg.c | 15 +++++---------- + drivers/clk/renesas/rcar-gen4-cpg.c | 9 +++------ + 3 files changed, 11 insertions(+), 19 deletions(-) + +diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c +index 3abd6e5400ad..f7b827b5e9b2 100644 +--- a/drivers/clk/renesas/clk-div6.c ++++ b/drivers/clk/renesas/clk-div6.c +@@ -7,6 +7,7 @@ + * Contact: Laurent Pinchart + */ + ++#include + #include + #include + #include +@@ -171,8 +172,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) + if (clock->src_mask == 0) + return 0; + +- hw_index = (readl(clock->reg) & clock->src_mask) >> +- __ffs(clock->src_mask); ++ hw_index = field_get(clock->src_mask, readl(clock->reg)); + for (i = 0; i < clk_hw_get_num_parents(hw); i++) { + if (clock->parents[i] == hw_index) + return i; +@@ -191,7 +191,7 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) + if (index >= clk_hw_get_num_parents(hw)) + return -EINVAL; + +- src = clock->parents[index] << __ffs(clock->src_mask); ++ src = field_prep(clock->src_mask, clock->parents[index]); + writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg); + return 0; + } +diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c +index 10ae20489df9..b954278ddd9d 100644 +--- a/drivers/clk/renesas/rcar-gen3-cpg.c ++++ b/drivers/clk/renesas/rcar-gen3-cpg.c +@@ -54,10 +54,8 @@ static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, + { + struct cpg_pll_clk *pll_clk = to_pll_clk(hw); + unsigned int mult; +- u32 val; + +- val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; +- mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; ++ mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1; + + return parent_rate * mult * pll_clk->fixed_mult; + } +@@ -94,7 +92,7 @@ static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, + + val = readl(pll_clk->pllcr_reg); + val &= ~CPG_PLLnCR_STC_MASK; +- val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK); ++ val |= FIELD_PREP(CPG_PLLnCR_STC_MASK, mult - 1); + writel(val, pll_clk->pllcr_reg); + + for (i = 1000; i; i--) { +@@ -176,11 +174,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) + { + struct cpg_z_clk *zclk = to_z_clk(hw); +- unsigned int mult; +- u32 val; +- +- val = readl(zclk->reg) & zclk->mask; +- mult = 32 - (val >> __ffs(zclk->mask)); ++ unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, + 32 * zclk->fixed_div); +@@ -231,7 +225,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, + if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) + return -EBUSY; + +- cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); ++ cpg_reg_modify(zclk->reg, zclk->mask, ++ field_prep(zclk->mask, 32 - mult)); + + /* + * Set KICK bit in FRQCRB to update hardware setting and wait for +diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c +index fb9a876aaba5..db3a0b8ef2b9 100644 +--- a/drivers/clk/renesas/rcar-gen4-cpg.c ++++ b/drivers/clk/renesas/rcar-gen4-cpg.c +@@ -279,11 +279,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) + { + struct cpg_z_clk *zclk = to_z_clk(hw); +- unsigned int mult; +- u32 val; +- +- val = readl(zclk->reg) & zclk->mask; +- mult = 32 - (val >> __ffs(zclk->mask)); ++ unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, + 32 * zclk->fixed_div); +@@ -334,7 +330,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, + if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) + return -EBUSY; + +- cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); ++ cpg_reg_modify(zclk->reg, zclk->mask, ++ field_prep(zclk->mask, 32 - mult)); + + /* + * Set KICK bit in FRQCRB to update hardware setting and wait for +-- +2.53.0 + diff --git a/SPECS/linux-lts/0281-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch b/SPECS/linux-lts/0281-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch deleted file mode 100644 index f9a128bab3..0000000000 --- a/SPECS/linux-lts/0281-UPSTREAM-pinctrl-ma35-Convert-to-common-field_-get-p.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 0eb5bae05723a59adbe4e3bbbab9ba880ecd2177 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:08 +0100 -Subject: [PATCH 281/467] UPSTREAM: pinctrl: ma35: Convert to common - field_{get,prep}() helpers - -Drop the driver-specific field_get() and field_prep() macros, in favor -of the globally available variants from . - -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Linus Walleij -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit bb0e7fda87753a973cb4a86c22905b1177f00d4e) -Signed-off-by: Han Gao ---- - drivers/pinctrl/nuvoton/pinctrl-ma35.c | 6 ------ - 1 file changed, 6 deletions(-) - -diff --git a/drivers/pinctrl/nuvoton/pinctrl-ma35.c b/drivers/pinctrl/nuvoton/pinctrl-ma35.c -index 925dd717c9de..8d71dc53cc1d 100644 ---- a/drivers/pinctrl/nuvoton/pinctrl-ma35.c -+++ b/drivers/pinctrl/nuvoton/pinctrl-ma35.c -@@ -81,12 +81,6 @@ - #define MVOLT_1800 0 - #define MVOLT_3300 1 - --/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) --#undef field_prep --#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -- - static const char * const gpio_group_name[] = { - "gpioa", "gpiob", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog", - "gpioh", "gpioi", "gpioj", "gpiok", "gpiol", "gpiom", "gpion", --- -2.53.0 - diff --git a/SPECS/linux-lts/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch b/SPECS/linux-lts/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch new file mode 100644 index 0000000000..4685894400 --- /dev/null +++ b/SPECS/linux-lts/0282-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch @@ -0,0 +1,40 @@ +From 23fef80ff6550ef4d1ece307b5c601d37a1fe71c Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 6 Nov 2025 14:34:14 +0100 +Subject: [RUYI PATCH] UPSTREAM: soc: renesas: Use bitfield helpers + +Use the field_get() helper, instead of open-coding the same operation. + +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Yury Norov (NVIDIA) +(cherry picked from commit c604cb5fdf0f569a9ce344a37a79958c3841396e) +Signed-off-by: Han Gao +--- + drivers/soc/renesas/renesas-soc.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c +index 1eb52356b996..ee4f17bb4db4 100644 +--- a/drivers/soc/renesas/renesas-soc.c ++++ b/drivers/soc/renesas/renesas-soc.c +@@ -5,6 +5,7 @@ + * Copyright (C) 2014-2016 Glider bvba + */ + ++#include + #include + #include + #include +@@ -524,8 +525,7 @@ static int __init renesas_soc_init(void) + eshi, eslo); + } + +- if (soc->id && +- ((product & id->mask) >> __ffs(id->mask)) != soc->id) { ++ if (soc->id && field_get(id->mask, product) != soc->id) { + pr_warn("SoC mismatch (product = 0x%x)\n", product); + ret = -ENODEV; + goto free_soc_dev_attr; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0282-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch b/SPECS/linux-lts/0282-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch deleted file mode 100644 index 53220f5a78..0000000000 --- a/SPECS/linux-lts/0282-UPSTREAM-soc-renesas-rz-sysc-Convert-to-common-field.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 8f99a7fa8c497ef1e8a0fc31678125daf8f04aef Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:09 +0100 -Subject: [PATCH 282/467] UPSTREAM: soc: renesas: rz-sysc: Convert to common - field_get() helper - -Drop the driver-specific field_get() macro, in favor of the globally -available variant from . - -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Claudiu Beznea -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 610c4408a2f7a09a00f656459e762ee1e21bbd7b) -Signed-off-by: Han Gao ---- - drivers/soc/renesas/rz-sysc.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - -diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c -index a1487195dc87..ae727d9c8cc5 100644 ---- a/drivers/soc/renesas/rz-sysc.c -+++ b/drivers/soc/renesas/rz-sysc.c -@@ -5,6 +5,7 @@ - * Copyright (C) 2024 Renesas Electronics Corp. - */ - -+#include - #include - #include - #include -@@ -16,9 +17,6 @@ - - #include "rz-sysc.h" - --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -- - /** - * struct rz_sysc - RZ SYSC private data structure - * @base: SYSC base address --- -2.53.0 - diff --git a/SPECS/linux-lts/0283-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch b/SPECS/linux-lts/0283-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch deleted file mode 100644 index 2ff6a0b412..0000000000 --- a/SPECS/linux-lts/0283-UPSTREAM-ALSA-usb-audio-Convert-to-common-field_-get.patch +++ /dev/null @@ -1,38 +0,0 @@ -From a254a77e47af456314d9166e8c477362f99da854 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:10 +0100 -Subject: [PATCH 283/467] UPSTREAM: ALSA: usb-audio: Convert to common - field_{get,prep}() helpers - -Drop the driver-specific field_get() and field_prep() macros, in favor -of the globally available variants from . - -Signed-off-by: Geert Uytterhoeven -Acked-by: Takashi Iwai -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit b1cff2f4b2391a13bd3e9263502072df1ee5d035) -Signed-off-by: Han Gao ---- - sound/usb/mixer_quirks.c | 6 ------ - 1 file changed, 6 deletions(-) - -diff --git a/sound/usb/mixer_quirks.c b/sound/usb/mixer_quirks.c -index bf8f97d43299..6069d9267c6c 100644 ---- a/sound/usb/mixer_quirks.c -+++ b/sound/usb/mixer_quirks.c -@@ -3308,12 +3308,6 @@ static int snd_bbfpro_controls_create(struct usb_mixer_interface *mixer) - #define RME_DIGIFACE_REGISTER(reg, mask) (((reg) << 16) | (mask)) - #define RME_DIGIFACE_INVERT BIT(31) - --/* Nonconst helpers */ --#undef field_get --#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) --#undef field_prep --#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) -- - static int snd_rme_digiface_write_reg(struct snd_kcontrol *kcontrol, int item, u16 mask, u16 val) - { - struct usb_mixer_elem_list *list = snd_kcontrol_chip(kcontrol); --- -2.53.0 - diff --git a/SPECS/linux-lts/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch b/SPECS/linux-lts/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch new file mode 100644 index 0000000000..45f824af71 --- /dev/null +++ b/SPECS/linux-lts/0283-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch @@ -0,0 +1,96 @@ +From 56a298b59d7189961a4e6a04e449718ff2944c21 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 19 Mar 2026 07:51:03 +0000 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: Add support for Terminus + FE1.1s USB2.0 Hub controller + +Terminus FE1.1s is USB2.0 protocol compliant 4-port USB HUB, It support +MTT (Multiple Transaction Translator) mode, the upstream port supports +high-speed 480MHz and full-speed 12MHz modes, also has integrated 5V to +3.3V, 1.8V regulator and Power-On-Reset circuit. + +Introduce the DT binding for it. + +Link: https://terminus-usa.com/wp-content/uploads/2024/06/FE1.1s-Product-Brief-Rev.-2.0-2023.pdf [1] +Signed-off-by: Yixun Lan +Reviewed-by: Rob Herring (Arm) +Link: https://patch.msgid.link/20260319-03-usb-hub-fe1-v2-1-e4e26809dd7d@kernel.org +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit e972256f256c5ae908e15e2c6880f9144fbcae93) +Signed-off-by: Han Gao +--- + .../bindings/usb/terminus,fe11.yaml | 62 +++++++++++++++++++ + 1 file changed, 62 insertions(+) + create mode 100644 Documentation/devicetree/bindings/usb/terminus,fe11.yaml + +diff --git a/Documentation/devicetree/bindings/usb/terminus,fe11.yaml b/Documentation/devicetree/bindings/usb/terminus,fe11.yaml +new file mode 100644 +index 000000000000..645f97d73807 +--- /dev/null ++++ b/Documentation/devicetree/bindings/usb/terminus,fe11.yaml +@@ -0,0 +1,62 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/usb/terminus,fe11.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Terminus FE1.1/1.1S USB 2.0 Hub Controller ++ ++maintainers: ++ - Yixun Lan ++ ++allOf: ++ - $ref: usb-hub.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - usb1a40,0101 ++ ++ reg: true ++ ++ reset-gpios: ++ description: ++ GPIO controlling the RESET#. ++ ++ vdd-supply: ++ description: ++ Regulator supply to the hub, one of 3.3V or 5V can be chosen. ++ ++ ports: ++ $ref: /schemas/graph.yaml#/properties/ports ++ ++ patternProperties: ++ '^port@': ++ $ref: /schemas/graph.yaml#/properties/port ++ ++ properties: ++ reg: ++ minimum: 1 ++ maximum: 4 ++ ++required: ++ - compatible ++ - reg ++ - vdd-supply ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ usb { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hub@1 { ++ compatible = "usb1a40,0101"; ++ reg = <1>; ++ reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; ++ vdd-supply = <&vcc_5v>; ++ }; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0284-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch b/SPECS/linux-lts/0284-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch deleted file mode 100644 index c4a78ea5e6..0000000000 --- a/SPECS/linux-lts/0284-UPSTREAM-clk-renesas-Use-bitfield-helpers.patch +++ /dev/null @@ -1,129 +0,0 @@ -From 40419cc775df729cfc32aee2a6b02c853ad42dd1 Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:13 +0100 -Subject: [PATCH 284/467] UPSTREAM: clk: renesas: Use bitfield helpers - -Use the FIELD_{GET,PREP}() and field_{get,prep}() helpers for const -respective non-const bitfields, instead of open-coding the same -operations. - -Signed-off-by: Geert Uytterhoeven -Reviewed-by: Stephen Boyd -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit 3937b05bb78f3ad1e8887b91b9a97ea05ac0a4a8) -Signed-off-by: Han Gao ---- - drivers/clk/renesas/clk-div6.c | 6 +++--- - drivers/clk/renesas/rcar-gen3-cpg.c | 15 +++++---------- - drivers/clk/renesas/rcar-gen4-cpg.c | 9 +++------ - 3 files changed, 11 insertions(+), 19 deletions(-) - -diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c -index 3abd6e5400ad..f7b827b5e9b2 100644 ---- a/drivers/clk/renesas/clk-div6.c -+++ b/drivers/clk/renesas/clk-div6.c -@@ -7,6 +7,7 @@ - * Contact: Laurent Pinchart - */ - -+#include - #include - #include - #include -@@ -171,8 +172,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw) - if (clock->src_mask == 0) - return 0; - -- hw_index = (readl(clock->reg) & clock->src_mask) >> -- __ffs(clock->src_mask); -+ hw_index = field_get(clock->src_mask, readl(clock->reg)); - for (i = 0; i < clk_hw_get_num_parents(hw); i++) { - if (clock->parents[i] == hw_index) - return i; -@@ -191,7 +191,7 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index) - if (index >= clk_hw_get_num_parents(hw)) - return -EINVAL; - -- src = clock->parents[index] << __ffs(clock->src_mask); -+ src = field_prep(clock->src_mask, clock->parents[index]); - writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg); - return 0; - } -diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c -index 10ae20489df9..b954278ddd9d 100644 ---- a/drivers/clk/renesas/rcar-gen3-cpg.c -+++ b/drivers/clk/renesas/rcar-gen3-cpg.c -@@ -54,10 +54,8 @@ static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw, - { - struct cpg_pll_clk *pll_clk = to_pll_clk(hw); - unsigned int mult; -- u32 val; - -- val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; -- mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1; -+ mult = FIELD_GET(CPG_PLLnCR_STC_MASK, readl(pll_clk->pllcr_reg)) + 1; - - return parent_rate * mult * pll_clk->fixed_mult; - } -@@ -94,7 +92,7 @@ static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, - - val = readl(pll_clk->pllcr_reg); - val &= ~CPG_PLLnCR_STC_MASK; -- val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK); -+ val |= FIELD_PREP(CPG_PLLnCR_STC_MASK, mult - 1); - writel(val, pll_clk->pllcr_reg); - - for (i = 1000; i; i--) { -@@ -176,11 +174,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) - { - struct cpg_z_clk *zclk = to_z_clk(hw); -- unsigned int mult; -- u32 val; -- -- val = readl(zclk->reg) & zclk->mask; -- mult = 32 - (val >> __ffs(zclk->mask)); -+ unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); - - return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, - 32 * zclk->fixed_div); -@@ -231,7 +225,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, - if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) - return -EBUSY; - -- cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); -+ cpg_reg_modify(zclk->reg, zclk->mask, -+ field_prep(zclk->mask, 32 - mult)); - - /* - * Set KICK bit in FRQCRB to update hardware setting and wait for -diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c -index fb9a876aaba5..db3a0b8ef2b9 100644 ---- a/drivers/clk/renesas/rcar-gen4-cpg.c -+++ b/drivers/clk/renesas/rcar-gen4-cpg.c -@@ -279,11 +279,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) - { - struct cpg_z_clk *zclk = to_z_clk(hw); -- unsigned int mult; -- u32 val; -- -- val = readl(zclk->reg) & zclk->mask; -- mult = 32 - (val >> __ffs(zclk->mask)); -+ unsigned int mult = 32 - field_get(zclk->mask, readl(zclk->reg)); - - return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, - 32 * zclk->fixed_div); -@@ -334,7 +330,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, - if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) - return -EBUSY; - -- cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); -+ cpg_reg_modify(zclk->reg, zclk->mask, -+ field_prep(zclk->mask, 32 - mult)); - - /* - * Set KICK bit in FRQCRB to update hardware setting and wait for --- -2.53.0 - diff --git a/SPECS/linux-lts/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch b/SPECS/linux-lts/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch new file mode 100644 index 0000000000..d9fcc7fdbd --- /dev/null +++ b/SPECS/linux-lts/0284-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch @@ -0,0 +1,57 @@ +From 7cc16fe69696bb942fb6f1b9a227fd74082707ae Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 19 Mar 2026 07:51:04 +0000 +Subject: [RUYI PATCH] UPSTREAM: usb: misc: onboard_usb_dev: Add Terminus + FE1.1s USB2.0 Hub (1a40:0101) + +Terminus FE1.1s is USB2.0 protocol compliant 4-port USB HUB, It support +MTT (Multiple Transaction Translator) mode, the upstream port supports +high-speed 480MHz and full-speed 12MHz modes, also it has integrated 5V +to 3.3V/1.8V regulator and Power-On-Reset circuit. + +Link: https://terminus-usa.com/wp-content/uploads/2024/06/FE1.1s-Product-Brief-Rev.-2.0-2023.pdf [1] +Signed-off-by: Yixun Lan +Link: https://patch.msgid.link/20260319-03-usb-hub-fe1-v2-2-e4e26809dd7d@kernel.org +Signed-off-by: Greg Kroah-Hartman +(cherry picked from commit 00b4fe5be06aecd6426930de86b7cffc2330f4b8) +Signed-off-by: Han Gao +--- + drivers/usb/misc/onboard_usb_dev.c | 2 ++ + drivers/usb/misc/onboard_usb_dev.h | 1 + + 2 files changed, 3 insertions(+) + +diff --git a/drivers/usb/misc/onboard_usb_dev.c b/drivers/usb/misc/onboard_usb_dev.c +index 41360a7591e5..40b2ebf45a9a 100644 +--- a/drivers/usb/misc/onboard_usb_dev.c ++++ b/drivers/usb/misc/onboard_usb_dev.c +@@ -570,6 +570,7 @@ static struct platform_driver onboard_dev_driver = { + #define VENDOR_ID_MICROCHIP 0x0424 + #define VENDOR_ID_PARADE 0x1da0 + #define VENDOR_ID_REALTEK 0x0bda ++#define VENDOR_ID_TERMINUS 0x1a40 + #define VENDOR_ID_TI 0x0451 + #define VENDOR_ID_VIA 0x2109 + #define VENDOR_ID_XMOS 0x20B1 +@@ -673,6 +674,7 @@ static const struct usb_device_id onboard_dev_id_table[] = { + { USB_DEVICE(VENDOR_ID_REALTEK, 0x0414) }, /* RTS5414 USB 3.2 HUB */ + { USB_DEVICE(VENDOR_ID_REALTEK, 0x5414) }, /* RTS5414 USB 2.1 HUB */ + { USB_DEVICE(VENDOR_ID_REALTEK, 0x0179) }, /* RTL8188ETV 2.4GHz WiFi */ ++ { USB_DEVICE(VENDOR_ID_TERMINUS, 0x0101) }, /* Terminus FE1.1s 2.0 HUB */ + { USB_DEVICE(VENDOR_ID_TI, 0x8025) }, /* TI USB8020B 3.0 HUB */ + { USB_DEVICE(VENDOR_ID_TI, 0x8027) }, /* TI USB8020B 2.0 HUB */ + { USB_DEVICE(VENDOR_ID_TI, 0x8140) }, /* TI USB8041 3.0 HUB */ +diff --git a/drivers/usb/misc/onboard_usb_dev.h b/drivers/usb/misc/onboard_usb_dev.h +index c1462be5526d..be234b5a97bb 100644 +--- a/drivers/usb/misc/onboard_usb_dev.h ++++ b/drivers/usb/misc/onboard_usb_dev.h +@@ -146,6 +146,7 @@ static const struct of_device_id onboard_dev_match[] = { + { .compatible = "usbbda,5411", .data = &realtek_rts5411_data, }, + { .compatible = "usbbda,414", .data = &realtek_rts5411_data, }, + { .compatible = "usbbda,5414", .data = &realtek_rts5411_data, }, ++ { .compatible = "usb1a40,0101", .data = &vialab_vl817_data, }, + { .compatible = "usb1da0,5511", .data = ¶de_ps5511_data, }, + { .compatible = "usb1da0,55a1", .data = ¶de_ps5511_data, }, + { .compatible = "usb2109,817", .data = &vialab_vl817_data, }, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch b/SPECS/linux-lts/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch new file mode 100644 index 0000000000..366e334f76 --- /dev/null +++ b/SPECS/linux-lts/0285-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch @@ -0,0 +1,96 @@ +From 3df7916fd6c198c8e58d6d4914ab06ebca3918bc Mon Sep 17 00:00:00 2001 +From: Nathan Chancellor +Date: Wed, 29 Apr 2026 20:38:17 -0600 +Subject: [RUYI PATCH] UPSTREAM: riscv: Define + __riscv_copy_{,vec_}{words,bytes}_unaligned() using SYM_TYPED_FUNC_START + +After commit 67bdd7b01387 ("riscv: Split out measure_cycles() for +reuse") and commit c03ad15f7cf6 ("riscv: Reuse measure_cycles() in +check_vector_unaligned_access()"), there are CFI failure when booting +kernels with CONFIG_CFI=y: + + CFI failure at measure_cycles+0x38/0xe0 (target: __riscv_copy_words_unaligned+0x0/0x50; expected type: ...) + CFI failure at measure_cycles+0x38/0xe0 (target: __riscv_copy_vec_words_unaligned+0x0/0x24; expected type: ...) + +The __riscv_copy_*_unaligned() functions are now called indirectly but +they are not defined with SYM_TYPED_FUNC_START, which is required for +assembly functions called indirectly from C to pass CFI checking. Switch +to SYM_TYPED_FUNC_START to clear up the CFI failures. + +Fixes: 67bdd7b01387 ("riscv: Split out measure_cycles() for reuse") +Fixes: c03ad15f7cf6 ("riscv: Reuse measure_cycles() in check_vector_unaligned_access()") +Signed-off-by: Nathan Chancellor +Reviewed-by: Sami Tolvanen +Reviewed-by: Nam Cao +Link: https://patch.msgid.link/20260406-measure_cycles-cfi-failure-v1-1-03e0234ae02f@kernel.org +Signed-off-by: Paul Walmsley +(cherry picked from commit f2abc305aa93f5b12d5c929d7a9c1cf7d7fee8af) +Signed-off-by: Han Gao +--- + arch/riscv/kernel/copy-unaligned.S | 5 +++-- + arch/riscv/kernel/vec-copy-unaligned.S | 5 +++-- + 2 files changed, 6 insertions(+), 4 deletions(-) + +diff --git a/arch/riscv/kernel/copy-unaligned.S b/arch/riscv/kernel/copy-unaligned.S +index 2b3d9398c113..90f3549621f7 100644 +--- a/arch/riscv/kernel/copy-unaligned.S ++++ b/arch/riscv/kernel/copy-unaligned.S +@@ -1,6 +1,7 @@ + /* SPDX-License-Identifier: GPL-2.0 */ + /* Copyright (C) 2023 Rivos Inc. */ + ++#include + #include + #include + +@@ -9,7 +10,7 @@ + /* void __riscv_copy_words_unaligned(void *, const void *, size_t) */ + /* Performs a memcpy without aligning buffers, using word loads and stores. */ + /* Note: The size is truncated to a multiple of 8 * SZREG */ +-SYM_FUNC_START(__riscv_copy_words_unaligned) ++SYM_TYPED_FUNC_START(__riscv_copy_words_unaligned) + andi a4, a2, ~((8*SZREG)-1) + beqz a4, 2f + add a3, a1, a4 +@@ -41,7 +42,7 @@ SYM_FUNC_END(__riscv_copy_words_unaligned) + /* void __riscv_copy_bytes_unaligned(void *, const void *, size_t) */ + /* Performs a memcpy without aligning buffers, using only byte accesses. */ + /* Note: The size is truncated to a multiple of 8 */ +-SYM_FUNC_START(__riscv_copy_bytes_unaligned) ++SYM_TYPED_FUNC_START(__riscv_copy_bytes_unaligned) + andi a4, a2, ~(8-1) + beqz a4, 2f + add a3, a1, a4 +diff --git a/arch/riscv/kernel/vec-copy-unaligned.S b/arch/riscv/kernel/vec-copy-unaligned.S +index 7ce4de6f6e69..361039f7b944 100644 +--- a/arch/riscv/kernel/vec-copy-unaligned.S ++++ b/arch/riscv/kernel/vec-copy-unaligned.S +@@ -2,6 +2,7 @@ + /* Copyright (C) 2024 Rivos Inc. */ + + #include ++#include + #include + #include + +@@ -16,7 +17,7 @@ + /* void __riscv_copy_vec_words_unaligned(void *, const void *, size_t) */ + /* Performs a memcpy without aligning buffers, using word loads and stores. */ + /* Note: The size is truncated to a multiple of WORD_EEW */ +-SYM_FUNC_START(__riscv_copy_vec_words_unaligned) ++SYM_TYPED_FUNC_START(__riscv_copy_vec_words_unaligned) + andi a4, a2, ~(WORD_EEW-1) + beqz a4, 2f + add a3, a1, a4 +@@ -38,7 +39,7 @@ SYM_FUNC_END(__riscv_copy_vec_words_unaligned) + /* void __riscv_copy_vec_bytes_unaligned(void *, const void *, size_t) */ + /* Performs a memcpy without aligning buffers, using only byte accesses. */ + /* Note: The size is truncated to a multiple of 8 */ +-SYM_FUNC_START(__riscv_copy_vec_bytes_unaligned) ++SYM_TYPED_FUNC_START(__riscv_copy_vec_bytes_unaligned) + andi a4, a2, ~(8-1) + beqz a4, 2f + add a3, a1, a4 +-- +2.53.0 + diff --git a/SPECS/linux-lts/0285-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch b/SPECS/linux-lts/0285-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch deleted file mode 100644 index d10c6a26d4..0000000000 --- a/SPECS/linux-lts/0285-UPSTREAM-soc-renesas-Use-bitfield-helpers.patch +++ /dev/null @@ -1,40 +0,0 @@ -From fbb168fdc7492006a9f7780a6ec49834031eea6e Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Thu, 6 Nov 2025 14:34:14 +0100 -Subject: [PATCH 285/467] UPSTREAM: soc: renesas: Use bitfield helpers - -Use the field_get() helper, instead of open-coding the same operation. - -Signed-off-by: Geert Uytterhoeven -Signed-off-by: Yury Norov (NVIDIA) -(cherry picked from commit c604cb5fdf0f569a9ce344a37a79958c3841396e) -Signed-off-by: Han Gao ---- - drivers/soc/renesas/renesas-soc.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c -index 1eb52356b996..ee4f17bb4db4 100644 ---- a/drivers/soc/renesas/renesas-soc.c -+++ b/drivers/soc/renesas/renesas-soc.c -@@ -5,6 +5,7 @@ - * Copyright (C) 2014-2016 Glider bvba - */ - -+#include - #include - #include - #include -@@ -524,8 +525,7 @@ static int __init renesas_soc_init(void) - eshi, eslo); - } - -- if (soc->id && -- ((product & id->mask) >> __ffs(id->mask)) != soc->id) { -+ if (soc->id && field_get(id->mask, product) != soc->id) { - pr_warn("SoC mismatch (product = 0x%x)\n", product); - ret = -ENODEV; - goto free_soc_dev_attr; --- -2.53.0 - diff --git a/SPECS/linux-lts/0286-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch b/SPECS/linux-lts/0286-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch deleted file mode 100644 index 0a3a2a1e7d..0000000000 --- a/SPECS/linux-lts/0286-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 42fe4e15f9f853b366dfddb9cd5fdda93c07db7b Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 19 Mar 2026 07:51:03 +0000 -Subject: [PATCH 286/467] UPSTREAM: dt-bindings: usb: Add support for Terminus - FE1.1s USB2.0 Hub controller - -Terminus FE1.1s is USB2.0 protocol compliant 4-port USB HUB, It support -MTT (Multiple Transaction Translator) mode, the upstream port supports -high-speed 480MHz and full-speed 12MHz modes, also has integrated 5V to -3.3V, 1.8V regulator and Power-On-Reset circuit. - -Introduce the DT binding for it. - -Link: https://terminus-usa.com/wp-content/uploads/2024/06/FE1.1s-Product-Brief-Rev.-2.0-2023.pdf [1] -Signed-off-by: Yixun Lan -Reviewed-by: Rob Herring (Arm) -Link: https://patch.msgid.link/20260319-03-usb-hub-fe1-v2-1-e4e26809dd7d@kernel.org -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit e972256f256c5ae908e15e2c6880f9144fbcae93) -Signed-off-by: Han Gao ---- - .../bindings/usb/terminus,fe11.yaml | 62 +++++++++++++++++++ - 1 file changed, 62 insertions(+) - create mode 100644 Documentation/devicetree/bindings/usb/terminus,fe11.yaml - -diff --git a/Documentation/devicetree/bindings/usb/terminus,fe11.yaml b/Documentation/devicetree/bindings/usb/terminus,fe11.yaml -new file mode 100644 -index 000000000000..645f97d73807 ---- /dev/null -+++ b/Documentation/devicetree/bindings/usb/terminus,fe11.yaml -@@ -0,0 +1,62 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/usb/terminus,fe11.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Terminus FE1.1/1.1S USB 2.0 Hub Controller -+ -+maintainers: -+ - Yixun Lan -+ -+allOf: -+ - $ref: usb-hub.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - usb1a40,0101 -+ -+ reg: true -+ -+ reset-gpios: -+ description: -+ GPIO controlling the RESET#. -+ -+ vdd-supply: -+ description: -+ Regulator supply to the hub, one of 3.3V or 5V can be chosen. -+ -+ ports: -+ $ref: /schemas/graph.yaml#/properties/ports -+ -+ patternProperties: -+ '^port@': -+ $ref: /schemas/graph.yaml#/properties/port -+ -+ properties: -+ reg: -+ minimum: 1 -+ maximum: 4 -+ -+required: -+ - compatible -+ - reg -+ - vdd-supply -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ usb { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hub@1 { -+ compatible = "usb1a40,0101"; -+ reg = <1>; -+ reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; -+ vdd-supply = <&vcc_5v>; -+ }; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch b/SPECS/linux-lts/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch new file mode 100644 index 0000000000..74474ab04e --- /dev/null +++ b/SPECS/linux-lts/0286-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch @@ -0,0 +1,39 @@ +From 2eae98ea7476677c8119a80ff9bf50c8a3600315 Mon Sep 17 00:00:00 2001 +From: Zhengyu He +Date: Thu, 21 May 2026 22:44:45 +0800 +Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: support SpacemiT + K3 + +Add the SpacemiT K3 QSPI compatible to the fsl-qspi binding. + +K3 and K1 use the same QSPI controller, so document the K3 compatible +with "spacemit,k1-qspi" as fallback. + +Signed-off-by: Cody Kang +Signed-off-by: Zhengyu He +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-1-52bce26e5fd8@gmail.com +Signed-off-by: Mark Brown +(cherry picked from commit 27cd2dde35b2c3b8659fa18f6a935c61fedee5c1) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml +index 1d10cfbad86c..504df31a4f90 100644 +--- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml ++++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml +@@ -20,6 +20,9 @@ properties: + - fsl,ls1021a-qspi + - fsl,ls2080a-qspi + - spacemit,k1-qspi ++ - items: ++ - const: spacemit,k3-qspi ++ - const: spacemit,k1-qspi + - items: + - enum: + - fsl,ls1043a-qspi +-- +2.53.0 + diff --git a/SPECS/linux-lts/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch b/SPECS/linux-lts/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch new file mode 100644 index 0000000000..cee092d499 --- /dev/null +++ b/SPECS/linux-lts/0287-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch @@ -0,0 +1,45 @@ +From 4f4bff270953588decae0547de96ac02939beaad Mon Sep 17 00:00:00 2001 +From: Jiakai Xu +Date: Sun, 17 May 2026 12:44:14 +0000 +Subject: [RUYI PATCH] UPSTREAM: RISC-V: KVM: Fix NULL pointer dereference in + SBI v0.1 SEND_IPI handler + +The SBI v0.1 SEND_IPI handler iterates over the hart mask and calls +kvm_get_vcpu_by_id() to find the target vcpu for each set bit. When a +guest provides a hart mask containing bits for non-existent vcpu_ids, +kvm_get_vcpu_by_id() returns NULL, which is then unconditionally +dereferenced by kvm_riscv_vcpu_set_interrupt(), causing a kernel crash. + +Fix this by adding a NULL check before dereferencing the return value. +If the target vcpu is not found, skip it and continue processing the +remaining valid harts. + +Fixes: a046c2d8578c ("RISC-V: KVM: Reorganize SBI code by moving SBI v0.1 to its own file") +Signed-off-by: Jiakai Xu +Signed-off-by: Jiakai Xu +Assisted-by: OpenClaw:DeepSeek-V3.2 +Reviewed-by: Anup Patel +Link: https://lore.kernel.org/r/20260517124414.420919-1-xujiakai2025@iscas.ac.cn +Signed-off-by: Anup Patel +(cherry picked from commit fdb69d401967fd88d27982a7e4984b2a3a4f0314) +Signed-off-by: Han Gao +--- + arch/riscv/kvm/vcpu_sbi_v01.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c +index 368dfddd23d9..b6aef0e5ea57 100644 +--- a/arch/riscv/kvm/vcpu_sbi_v01.c ++++ b/arch/riscv/kvm/vcpu_sbi_v01.c +@@ -56,6 +56,8 @@ static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, + + for_each_set_bit(i, &hmask, BITS_PER_LONG) { + rvcpu = kvm_get_vcpu_by_id(vcpu->kvm, i); ++ if (!rvcpu) ++ continue; + ret = kvm_riscv_vcpu_set_interrupt(rvcpu, IRQ_VS_SOFT); + if (ret < 0) + break; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0287-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch b/SPECS/linux-lts/0287-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch deleted file mode 100644 index c3ed343dd6..0000000000 --- a/SPECS/linux-lts/0287-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 6004bf7f9a93b484f6869e38172fbf3543cd888a Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 19 Mar 2026 07:51:04 +0000 -Subject: [PATCH 287/467] UPSTREAM: usb: misc: onboard_usb_dev: Add Terminus - FE1.1s USB2.0 Hub (1a40:0101) - -Terminus FE1.1s is USB2.0 protocol compliant 4-port USB HUB, It support -MTT (Multiple Transaction Translator) mode, the upstream port supports -high-speed 480MHz and full-speed 12MHz modes, also it has integrated 5V -to 3.3V/1.8V regulator and Power-On-Reset circuit. - -Link: https://terminus-usa.com/wp-content/uploads/2024/06/FE1.1s-Product-Brief-Rev.-2.0-2023.pdf [1] -Signed-off-by: Yixun Lan -Link: https://patch.msgid.link/20260319-03-usb-hub-fe1-v2-2-e4e26809dd7d@kernel.org -Signed-off-by: Greg Kroah-Hartman -(cherry picked from commit 00b4fe5be06aecd6426930de86b7cffc2330f4b8) -Signed-off-by: Han Gao ---- - drivers/usb/misc/onboard_usb_dev.c | 2 ++ - drivers/usb/misc/onboard_usb_dev.h | 1 + - 2 files changed, 3 insertions(+) - -diff --git a/drivers/usb/misc/onboard_usb_dev.c b/drivers/usb/misc/onboard_usb_dev.c -index 41360a7591e5..40b2ebf45a9a 100644 ---- a/drivers/usb/misc/onboard_usb_dev.c -+++ b/drivers/usb/misc/onboard_usb_dev.c -@@ -570,6 +570,7 @@ static struct platform_driver onboard_dev_driver = { - #define VENDOR_ID_MICROCHIP 0x0424 - #define VENDOR_ID_PARADE 0x1da0 - #define VENDOR_ID_REALTEK 0x0bda -+#define VENDOR_ID_TERMINUS 0x1a40 - #define VENDOR_ID_TI 0x0451 - #define VENDOR_ID_VIA 0x2109 - #define VENDOR_ID_XMOS 0x20B1 -@@ -673,6 +674,7 @@ static const struct usb_device_id onboard_dev_id_table[] = { - { USB_DEVICE(VENDOR_ID_REALTEK, 0x0414) }, /* RTS5414 USB 3.2 HUB */ - { USB_DEVICE(VENDOR_ID_REALTEK, 0x5414) }, /* RTS5414 USB 2.1 HUB */ - { USB_DEVICE(VENDOR_ID_REALTEK, 0x0179) }, /* RTL8188ETV 2.4GHz WiFi */ -+ { USB_DEVICE(VENDOR_ID_TERMINUS, 0x0101) }, /* Terminus FE1.1s 2.0 HUB */ - { USB_DEVICE(VENDOR_ID_TI, 0x8025) }, /* TI USB8020B 3.0 HUB */ - { USB_DEVICE(VENDOR_ID_TI, 0x8027) }, /* TI USB8020B 2.0 HUB */ - { USB_DEVICE(VENDOR_ID_TI, 0x8140) }, /* TI USB8041 3.0 HUB */ -diff --git a/drivers/usb/misc/onboard_usb_dev.h b/drivers/usb/misc/onboard_usb_dev.h -index c1462be5526d..be234b5a97bb 100644 ---- a/drivers/usb/misc/onboard_usb_dev.h -+++ b/drivers/usb/misc/onboard_usb_dev.h -@@ -146,6 +146,7 @@ static const struct of_device_id onboard_dev_match[] = { - { .compatible = "usbbda,5411", .data = &realtek_rts5411_data, }, - { .compatible = "usbbda,414", .data = &realtek_rts5411_data, }, - { .compatible = "usbbda,5414", .data = &realtek_rts5411_data, }, -+ { .compatible = "usb1a40,0101", .data = &vialab_vl817_data, }, - { .compatible = "usb1da0,5511", .data = ¶de_ps5511_data, }, - { .compatible = "usb1da0,55a1", .data = ¶de_ps5511_data, }, - { .compatible = "usb2109,817", .data = &vialab_vl817_data, }, --- -2.53.0 - diff --git a/SPECS/linux-lts/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch b/SPECS/linux-lts/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch new file mode 100644 index 0000000000..e7deac9aea --- /dev/null +++ b/SPECS/linux-lts/0288-UPSTREAM-dt-bindings-mmc-sdhci-of-dwcmshc-Add-Eswin-.patch @@ -0,0 +1,108 @@ +From bb40d8362ee33eb3d7341201cc0193113631e03c Mon Sep 17 00:00:00 2001 +From: Huan He +Date: Sun, 19 Oct 2025 19:52:38 +0800 +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: sdhci-of-dwcmshc: Add Eswin + EIC7700 + +EIC7700 use Synopsys dwcmshc IP for SD/eMMC controllers. +Add Eswin EIC7700 support in sdhci-of-dwcmshc.yaml. + +Signed-off-by: Huan He +Reviewed-by: Conor Dooley +Signed-off-by: Ulf Hansson +(cherry picked from commit 30009a21f257a02feea7a7708ef3d0118e7f824a) +Signed-off-by: Han Gao +--- + .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 57 +++++++++++++++++-- + 1 file changed, 51 insertions(+), 6 deletions(-) + +diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +index f882219a0a26..7e7c55dc2440 100644 +--- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml ++++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +@@ -30,6 +30,7 @@ properties: + - sophgo,sg2002-dwcmshc + - sophgo,sg2042-dwcmshc + - thead,th1520-dwcmshc ++ - eswin,eic7700-dwcmshc + + reg: + maxItems: 1 +@@ -52,17 +53,30 @@ properties: + maxItems: 5 + + reset-names: +- items: +- - const: core +- - const: bus +- - const: axi +- - const: block +- - const: timer ++ maxItems: 5 + + rockchip,txclk-tapnum: + description: Specify the number of delay for tx sampling. + $ref: /schemas/types.yaml#/definitions/uint8 + ++ eswin,hsp-sp-csr: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: Phandle to HSP(High-Speed Peripheral) device ++ - description: Offset of the stability status register for internal ++ clock. ++ - description: Offset of the stability register for host regulator ++ voltage. ++ description: ++ HSP CSR is to control and get status of different high-speed peripherals ++ (such as Ethernet, USB, SATA, etc.) via register, which can tune ++ board-level's parameters of PHY, etc. ++ ++ eswin,drive-impedance-ohms: ++ description: Specifies the drive impedance in Ohm. ++ enum: [33, 40, 50, 66, 100] ++ + required: + - compatible + - reg +@@ -110,6 +124,37 @@ allOf: + - const: block + - const: timer + ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: eswin,eic7700-dwcmshc ++ then: ++ properties: ++ resets: ++ minItems: 4 ++ maxItems: 4 ++ reset-names: ++ items: ++ - const: axi ++ - const: phy ++ - const: prstn ++ - const: txrx ++ required: ++ - eswin,hsp-sp-csr ++ - eswin,drive-impedance-ohms ++ else: ++ properties: ++ resets: ++ maxItems: 5 ++ reset-names: ++ items: ++ - const: core ++ - const: bus ++ - const: axi ++ - const: block ++ - const: timer ++ + - if: + properties: + compatible: +-- +2.53.0 + diff --git a/SPECS/linux-lts/0288-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch b/SPECS/linux-lts/0288-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch deleted file mode 100644 index 1d01c9a2ed..0000000000 --- a/SPECS/linux-lts/0288-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch +++ /dev/null @@ -1,96 +0,0 @@ -From ed5a7f0bdca54d386d2e845f3ebadc8b204c271c Mon Sep 17 00:00:00 2001 -From: Nathan Chancellor -Date: Wed, 29 Apr 2026 20:38:17 -0600 -Subject: [PATCH 288/467] UPSTREAM: riscv: Define - __riscv_copy_{,vec_}{words,bytes}_unaligned() using SYM_TYPED_FUNC_START - -After commit 67bdd7b01387 ("riscv: Split out measure_cycles() for -reuse") and commit c03ad15f7cf6 ("riscv: Reuse measure_cycles() in -check_vector_unaligned_access()"), there are CFI failure when booting -kernels with CONFIG_CFI=y: - - CFI failure at measure_cycles+0x38/0xe0 (target: __riscv_copy_words_unaligned+0x0/0x50; expected type: ...) - CFI failure at measure_cycles+0x38/0xe0 (target: __riscv_copy_vec_words_unaligned+0x0/0x24; expected type: ...) - -The __riscv_copy_*_unaligned() functions are now called indirectly but -they are not defined with SYM_TYPED_FUNC_START, which is required for -assembly functions called indirectly from C to pass CFI checking. Switch -to SYM_TYPED_FUNC_START to clear up the CFI failures. - -Fixes: 67bdd7b01387 ("riscv: Split out measure_cycles() for reuse") -Fixes: c03ad15f7cf6 ("riscv: Reuse measure_cycles() in check_vector_unaligned_access()") -Signed-off-by: Nathan Chancellor -Reviewed-by: Sami Tolvanen -Reviewed-by: Nam Cao -Link: https://patch.msgid.link/20260406-measure_cycles-cfi-failure-v1-1-03e0234ae02f@kernel.org -Signed-off-by: Paul Walmsley -(cherry picked from commit f2abc305aa93f5b12d5c929d7a9c1cf7d7fee8af) -Signed-off-by: Han Gao ---- - arch/riscv/kernel/copy-unaligned.S | 5 +++-- - arch/riscv/kernel/vec-copy-unaligned.S | 5 +++-- - 2 files changed, 6 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/kernel/copy-unaligned.S b/arch/riscv/kernel/copy-unaligned.S -index 2b3d9398c113..90f3549621f7 100644 ---- a/arch/riscv/kernel/copy-unaligned.S -+++ b/arch/riscv/kernel/copy-unaligned.S -@@ -1,6 +1,7 @@ - /* SPDX-License-Identifier: GPL-2.0 */ - /* Copyright (C) 2023 Rivos Inc. */ - -+#include - #include - #include - -@@ -9,7 +10,7 @@ - /* void __riscv_copy_words_unaligned(void *, const void *, size_t) */ - /* Performs a memcpy without aligning buffers, using word loads and stores. */ - /* Note: The size is truncated to a multiple of 8 * SZREG */ --SYM_FUNC_START(__riscv_copy_words_unaligned) -+SYM_TYPED_FUNC_START(__riscv_copy_words_unaligned) - andi a4, a2, ~((8*SZREG)-1) - beqz a4, 2f - add a3, a1, a4 -@@ -41,7 +42,7 @@ SYM_FUNC_END(__riscv_copy_words_unaligned) - /* void __riscv_copy_bytes_unaligned(void *, const void *, size_t) */ - /* Performs a memcpy without aligning buffers, using only byte accesses. */ - /* Note: The size is truncated to a multiple of 8 */ --SYM_FUNC_START(__riscv_copy_bytes_unaligned) -+SYM_TYPED_FUNC_START(__riscv_copy_bytes_unaligned) - andi a4, a2, ~(8-1) - beqz a4, 2f - add a3, a1, a4 -diff --git a/arch/riscv/kernel/vec-copy-unaligned.S b/arch/riscv/kernel/vec-copy-unaligned.S -index 7ce4de6f6e69..361039f7b944 100644 ---- a/arch/riscv/kernel/vec-copy-unaligned.S -+++ b/arch/riscv/kernel/vec-copy-unaligned.S -@@ -2,6 +2,7 @@ - /* Copyright (C) 2024 Rivos Inc. */ - - #include -+#include - #include - #include - -@@ -16,7 +17,7 @@ - /* void __riscv_copy_vec_words_unaligned(void *, const void *, size_t) */ - /* Performs a memcpy without aligning buffers, using word loads and stores. */ - /* Note: The size is truncated to a multiple of WORD_EEW */ --SYM_FUNC_START(__riscv_copy_vec_words_unaligned) -+SYM_TYPED_FUNC_START(__riscv_copy_vec_words_unaligned) - andi a4, a2, ~(WORD_EEW-1) - beqz a4, 2f - add a3, a1, a4 -@@ -38,7 +39,7 @@ SYM_FUNC_END(__riscv_copy_vec_words_unaligned) - /* void __riscv_copy_vec_bytes_unaligned(void *, const void *, size_t) */ - /* Performs a memcpy without aligning buffers, using only byte accesses. */ - /* Note: The size is truncated to a multiple of 8 */ --SYM_FUNC_START(__riscv_copy_vec_bytes_unaligned) -+SYM_TYPED_FUNC_START(__riscv_copy_vec_bytes_unaligned) - andi a4, a2, ~(8-1) - beqz a4, 2f - add a3, a1, a4 --- -2.53.0 - diff --git a/SPECS/linux-lts/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch b/SPECS/linux-lts/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch new file mode 100644 index 0000000000..ca470143dd --- /dev/null +++ b/SPECS/linux-lts/0289-UPSTREAM-mmc-sdhci-of-dwcmshc-Add-support-for-Eswin-.patch @@ -0,0 +1,614 @@ +From 09f0d19162ff660efb7b93fd764ae93f6d004129 Mon Sep 17 00:00:00 2001 +From: Huan He +Date: Sun, 19 Oct 2025 19:53:16 +0800 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-dwcmshc: Add support for Eswin + EIC7700 + +Add support for the mmc controller in the Eswin EIC7700 with the new +compatible "eswin,eic7700-dwcmshc". Implement custom sdhci_ops for +set_clock, reset, set_uhs_signaling, platform_execute_tuning. + +Signed-off-by: Huan He +Acked-by: Adrian Hunter +Signed-off-by: Ulf Hansson +(cherry picked from commit 32b2633219d3509d8174737bb0a8afa060e55655) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 502 +++++++++++++++++++++++++++- + 1 file changed, 491 insertions(+), 11 deletions(-) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index 5b7ffc359414..dfad61f332c4 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -19,8 +20,11 @@ + #include + #include + #include ++#include + #include + #include ++#include ++#include + + #include "sdhci-pltfm.h" + #include "cqhci.h" +@@ -39,6 +43,7 @@ + #define DWCMSHC_CARD_IS_EMMC BIT(0) + #define DWCMSHC_ENHANCED_STROBE BIT(8) + #define DWCMSHC_EMMC_ATCTRL 0x40 ++#define DWCMSHC_AT_STAT 0x44 + /* Tuning and auto-tuning fields in AT_CTRL_R control register */ + #define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */ + #define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */ +@@ -194,6 +199,19 @@ + #define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */ + #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */ + ++/* PHY DLL offset setting register */ ++#define PHY_DLL_OFFST_R (DWC_MSHC_PTR_PHY_R + 0x29) ++/* DLL LBT setting register */ ++#define PHY_DLLBT_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x2c) ++/* DLL Status register */ ++#define PHY_DLL_STATUS_R (DWC_MSHC_PTR_PHY_R + 0x2e) ++#define DLL_LOCK_STS BIT(0)/* DLL is locked and ready */ ++/* ++ * Captures the value of DLL's lock error status information. Value is valid ++ * only when LOCK_STS is set. ++ */ ++#define DLL_ERROR_STS BIT(1) ++ + #define FLAG_IO_FIXED_1V8 BIT(0) + + #define BOUNDARY_OK(addr, len) \ +@@ -206,6 +224,31 @@ + /* SMC call for BlueField-3 eMMC RST_N */ + #define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007 + ++/* Eswin specific Registers */ ++#define EIC7700_CARD_CLK_STABLE BIT(28) ++#define EIC7700_INT_BCLK_STABLE BIT(16) ++#define EIC7700_INT_ACLK_STABLE BIT(8) ++#define EIC7700_INT_TMCLK_STABLE BIT(0) ++#define EIC7700_INT_CLK_STABLE (EIC7700_CARD_CLK_STABLE | \ ++ EIC7700_INT_ACLK_STABLE | \ ++ EIC7700_INT_BCLK_STABLE | \ ++ EIC7700_INT_TMCLK_STABLE) ++#define EIC7700_HOST_VAL_STABLE BIT(0) ++ ++/* strength definition */ ++#define PHYCTRL_DR_33OHM 0xee ++#define PHYCTRL_DR_40OHM 0xcc ++#define PHYCTRL_DR_50OHM 0x88 ++#define PHYCTRL_DR_66OHM 0x44 ++#define PHYCTRL_DR_100OHM 0x00 ++ ++#define MAX_PHASE_CODE 0xff ++#define TUNING_RANGE_THRESHOLD 40 ++#define PHY_CLK_MAX_DELAY_MASK 0x7f ++#define PHY_DELAY_CODE_MAX 0x7f ++#define PHY_DELAY_CODE_EMMC 0x17 ++#define PHY_DELAY_CODE_SD 0x55 ++ + enum dwcmshc_rk_type { + DWCMSHC_RK3568, + DWCMSHC_RK3588, +@@ -217,6 +260,11 @@ struct rk35xx_priv { + u8 txclk_tapnum; + }; + ++struct eic7700_priv { ++ struct reset_control *reset; ++ unsigned int drive_impedance; ++}; ++ + #define DWCMSHC_MAX_OTHER_CLKS 3 + + struct dwcmshc_priv { +@@ -238,6 +286,17 @@ struct dwcmshc_pltfm_data { + void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); + }; + ++static void dwcmshc_enable_card_clk(struct sdhci_host *host) ++{ ++ u16 ctrl; ++ ++ ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) { ++ ctrl |= SDHCI_CLOCK_CARD_EN; ++ sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); ++ } ++} ++ + static int dwcmshc_get_enable_other_clks(struct device *dev, + struct dwcmshc_priv *priv, + int num_clks, +@@ -1120,6 +1179,411 @@ static int sg2042_init(struct device *dev, struct sdhci_host *host, + ARRAY_SIZE(clk_ids), clk_ids); + } + ++static void sdhci_eic7700_set_clock(struct sdhci_host *host, unsigned int clock) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ u16 clk; ++ ++ host->mmc->actual_clock = clock; ++ ++ if (clock == 0) { ++ sdhci_set_clock(host, clock); ++ return; ++ } ++ ++ clk_set_rate(pltfm_host->clk, clock); ++ ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ clk |= SDHCI_CLOCK_INT_EN; ++ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); ++ ++ dwcmshc_enable_card_clk(host); ++} ++ ++static void sdhci_eic7700_config_phy_delay(struct sdhci_host *host, int delay) ++{ ++ delay &= PHY_CLK_MAX_DELAY_MASK; ++ ++ /* phy clk delay line config */ ++ sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); ++ sdhci_writeb(host, delay, PHY_SDCLKDL_DC_R); ++ sdhci_writeb(host, 0x0, PHY_SDCLKDL_CNFG_R); ++} ++ ++static void sdhci_eic7700_config_phy(struct sdhci_host *host) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); ++ u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; ++ struct eic7700_priv *priv = dwc_priv->priv; ++ unsigned int val, drv; ++ ++ drv = FIELD_PREP(PHY_CNFG_PAD_SP_MASK, priv->drive_impedance & 0xF); ++ drv |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, (priv->drive_impedance >> 4) & 0xF); ++ ++ if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { ++ val = sdhci_readw(host, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); ++ val |= DWCMSHC_CARD_IS_EMMC; ++ sdhci_writew(host, val, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); ++ } ++ ++ /* reset phy, config phy's pad */ ++ sdhci_writel(host, drv | ~PHY_CNFG_RSTN_DEASSERT, PHY_CNFG_R); ++ ++ /* configure phy pads */ ++ val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); ++ val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); ++ val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); ++ val |= PHY_PAD_RXSEL_1V8; ++ sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); ++ sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); ++ sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); ++ ++ /* Clock PAD Setting */ ++ val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); ++ val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); ++ sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); ++ ++ /* PHY strobe PAD setting (EMMC only) */ ++ if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { ++ val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); ++ val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); ++ val |= PHY_PAD_RXSEL_1V8; ++ sdhci_writew(host, val, PHY_STBPAD_CNFG_R); ++ } ++ usleep_range(2000, 3000); ++ sdhci_writel(host, drv | PHY_CNFG_RSTN_DEASSERT, PHY_CNFG_R); ++ sdhci_eic7700_config_phy_delay(host, dwc_priv->delay_line); ++} ++ ++static void sdhci_eic7700_reset(struct sdhci_host *host, u8 mask) ++{ ++ sdhci_reset(host, mask); ++ ++ /* after reset all, the phy's config will be clear */ ++ if (mask == SDHCI_RESET_ALL) ++ sdhci_eic7700_config_phy(host); ++} ++ ++static int sdhci_eic7700_reset_init(struct device *dev, struct eic7700_priv *priv) ++{ ++ int ret; ++ ++ priv->reset = devm_reset_control_array_get_optional_exclusive(dev); ++ if (IS_ERR(priv->reset)) { ++ ret = PTR_ERR(priv->reset); ++ dev_err(dev, "failed to get reset control %d\n", ret); ++ return ret; ++ } ++ ++ ret = reset_control_assert(priv->reset); ++ if (ret) { ++ dev_err(dev, "Failed to assert reset signals: %d\n", ret); ++ return ret; ++ } ++ usleep_range(2000, 2100); ++ ret = reset_control_deassert(priv->reset); ++ if (ret) { ++ dev_err(dev, "Failed to deassert reset signals: %d\n", ret); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++static unsigned int eic7700_convert_drive_impedance_ohm(struct device *dev, unsigned int dr_ohm) ++{ ++ switch (dr_ohm) { ++ case 100: ++ return PHYCTRL_DR_100OHM; ++ case 66: ++ return PHYCTRL_DR_66OHM; ++ case 50: ++ return PHYCTRL_DR_50OHM; ++ case 40: ++ return PHYCTRL_DR_40OHM; ++ case 33: ++ return PHYCTRL_DR_33OHM; ++ } ++ ++ dev_warn(dev, "Invalid value %u for drive-impedance-ohms.\n", dr_ohm); ++ return PHYCTRL_DR_50OHM; ++} ++ ++static int sdhci_eic7700_delay_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); ++ int delay_min = -1; ++ int delay_max = -1; ++ int cmd_error = 0; ++ int delay = 0; ++ int i = 0; ++ int ret; ++ ++ for (i = 0; i <= PHY_DELAY_CODE_MAX; i++) { ++ sdhci_eic7700_config_phy_delay(host, i); ++ ret = mmc_send_tuning(host->mmc, opcode, &cmd_error); ++ if (ret) { ++ host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); ++ usleep_range(200, 210); ++ if (delay_min != -1 && delay_max != -1) ++ break; ++ } else { ++ if (delay_min == -1) { ++ delay_min = i; ++ continue; ++ } else { ++ delay_max = i; ++ continue; ++ } ++ } ++ } ++ if (delay_min == -1 && delay_max == -1) { ++ pr_err("%s: delay code tuning failed!\n", mmc_hostname(host->mmc)); ++ sdhci_eic7700_config_phy_delay(host, dwc_priv->delay_line); ++ return ret; ++ } ++ ++ delay = (delay_min + delay_max) / 2; ++ sdhci_eic7700_config_phy_delay(host, delay); ++ ++ return 0; ++} ++ ++static int sdhci_eic7700_phase_code_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); ++ u32 sd_caps = MMC_CAP2_NO_MMC | MMC_CAP2_NO_SDIO; ++ int phase_code = -1; ++ int code_range = -1; ++ bool is_sd = false; ++ int code_min = -1; ++ int code_max = -1; ++ int cmd_error = 0; ++ int ret = 0; ++ int i = 0; ++ ++ if ((host->mmc->caps2 & sd_caps) == sd_caps) ++ is_sd = true; ++ ++ for (i = 0; i <= MAX_PHASE_CODE; i++) { ++ /* Centered Phase code */ ++ sdhci_writew(host, i, priv->vendor_specific_area1 + DWCMSHC_AT_STAT); ++ ret = mmc_send_tuning(host->mmc, opcode, &cmd_error); ++ host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); ++ ++ if (ret) { ++ /* SD specific range tracking */ ++ if (is_sd && code_min != -1 && code_max != -1) { ++ if (code_max - code_min > code_range) { ++ code_range = code_max - code_min; ++ phase_code = (code_min + code_max) / 2; ++ if (code_range > TUNING_RANGE_THRESHOLD) ++ break; ++ } ++ code_min = -1; ++ code_max = -1; ++ } ++ /* EMMC breaks after first valid range */ ++ if (!is_sd && code_min != -1 && code_max != -1) ++ break; ++ } else { ++ /* Track valid phase code range */ ++ if (code_min == -1) { ++ code_min = i; ++ if (!is_sd) ++ continue; ++ } ++ code_max = i; ++ if (is_sd && i == MAX_PHASE_CODE) { ++ if (code_max - code_min > code_range) { ++ code_range = code_max - code_min; ++ phase_code = (code_min + code_max) / 2; ++ } ++ } ++ } ++ } ++ ++ /* Handle tuning failure case */ ++ if ((is_sd && phase_code == -1) || ++ (!is_sd && code_min == -1 && code_max == -1)) { ++ pr_err("%s: phase code tuning failed!\n", mmc_hostname(host->mmc)); ++ sdhci_writew(host, 0, priv->vendor_specific_area1 + DWCMSHC_AT_STAT); ++ return -EIO; ++ } ++ if (!is_sd) ++ phase_code = (code_min + code_max) / 2; ++ ++ sdhci_writew(host, phase_code, priv->vendor_specific_area1 + DWCMSHC_AT_STAT); ++ ++ /* SD specific final verification */ ++ if (is_sd) { ++ ret = mmc_send_tuning(host->mmc, opcode, &cmd_error); ++ host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); ++ if (ret) { ++ pr_err("%s: Final phase code 0x%x verification failed!\n", ++ mmc_hostname(host->mmc), phase_code); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int sdhci_eic7700_executing_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); ++ u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; ++ int ret = 0; ++ u16 ctrl; ++ u32 val; ++ ++ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); ++ ctrl &= ~SDHCI_CTRL_TUNED_CLK; ++ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); ++ ++ val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); ++ val |= AT_CTRL_SW_TUNE_EN; ++ sdhci_writew(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); ++ ++ sdhci_writew(host, 0, priv->vendor_specific_area1 + DWCMSHC_AT_STAT); ++ sdhci_writew(host, 0x0, SDHCI_CMD_DATA); ++ ++ if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { ++ ret = sdhci_eic7700_delay_tuning(host, opcode); ++ if (ret) ++ return ret; ++ } ++ ++ ret = sdhci_eic7700_phase_code_tuning(host, opcode); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void sdhci_eic7700_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); ++ u8 status; ++ u32 val; ++ int ret; ++ ++ dwcmshc_set_uhs_signaling(host, timing); ++ ++ /* here need make dll locked when in hs400 at 200MHz */ ++ if (timing == MMC_TIMING_MMC_HS400 && host->clock == 200000000) { ++ val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); ++ val &= ~(FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY)); ++ /* 2-cycle latency */ ++ val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, 0x2); ++ sdhci_writew(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); ++ ++ sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) | ++ 0x3, PHY_DLL_CNFG1_R);/* DLL wait cycle input */ ++ /* DLL jump step input */ ++ sdhci_writeb(host, 0x02, PHY_DLL_CNFG2_R); ++ sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, ++ PHY_DLLDL_CNFG_SLV_INPSEL), PHY_DLLDL_CNFG_R); ++ /* Sets the value of DLL's offset input */ ++ sdhci_writeb(host, 0x00, PHY_DLL_OFFST_R); ++ /* ++ * Sets the value of DLL's olbt loadval input. Controls the Ibt ++ * timer's timeout value at which DLL runs a revalidation cycle. ++ */ ++ sdhci_writew(host, 0xffff, PHY_DLLBT_CNFG_R); ++ sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); ++ usleep_range(100, 110); ++ ++ ret = read_poll_timeout(sdhci_readb, status, status & DLL_LOCK_STS, 100, 1000000, ++ false, host, PHY_DLL_STATUS_R); ++ if (ret) { ++ pr_err("%s: DLL lock timeout! status: 0x%x\n", ++ mmc_hostname(host->mmc), status); ++ return; ++ } ++ ++ status = sdhci_readb(host, PHY_DLL_STATUS_R); ++ if (status & DLL_ERROR_STS) { ++ pr_err("%s: DLL lock failed!err_status:0x%x\n", ++ mmc_hostname(host->mmc), status); ++ } ++ } ++} ++ ++static void sdhci_eic7700_set_uhs_wrapper(struct sdhci_host *host, unsigned int timing) ++{ ++ u32 sd_caps = MMC_CAP2_NO_MMC | MMC_CAP2_NO_SDIO; ++ ++ if ((host->mmc->caps2 & sd_caps) == sd_caps) ++ sdhci_set_uhs_signaling(host, timing); ++ else ++ sdhci_eic7700_set_uhs_signaling(host, timing); ++} ++ ++static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) ++{ ++ u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; ++ unsigned int val, hsp_int_status, hsp_pwr_ctrl; ++ struct of_phandle_args args; ++ struct eic7700_priv *priv; ++ struct regmap *hsp_regmap; ++ int ret; ++ ++ priv = devm_kzalloc(dev, sizeof(struct eic7700_priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ dwc_priv->priv = priv; ++ ++ ret = sdhci_eic7700_reset_init(dev, dwc_priv->priv); ++ if (ret) { ++ dev_err(dev, "failed to reset\n"); ++ return ret; ++ } ++ ++ ret = of_parse_phandle_with_fixed_args(dev->of_node, "eswin,hsp-sp-csr", 2, 0, &args); ++ if (ret) { ++ dev_err(dev, "Fail to parse 'eswin,hsp-sp-csr' phandle (%d)\n", ret); ++ return ret; ++ } ++ ++ hsp_regmap = syscon_node_to_regmap(args.np); ++ if (IS_ERR(hsp_regmap)) { ++ dev_err(dev, "Failed to get regmap for 'eswin,hsp-sp-csr'\n"); ++ of_node_put(args.np); ++ return PTR_ERR(hsp_regmap); ++ } ++ hsp_int_status = args.args[0]; ++ hsp_pwr_ctrl = args.args[1]; ++ of_node_put(args.np); ++ /* ++ * Assert clock stability: write EIC7700_INT_CLK_STABLE to hsp_int_status. ++ * This signals to the eMMC controller that platform clocks (card, ACLK, ++ * BCLK, TMCLK) are enabled and stable. ++ */ ++ regmap_write(hsp_regmap, hsp_int_status, EIC7700_INT_CLK_STABLE); ++ /* ++ * Assert voltage stability: write EIC7700_HOST_VAL_STABLE to hsp_pwr_ctrl. ++ * This signals that VDD is stable and permits transition to high-speed ++ * modes (e.g., UHS-I). ++ */ ++ regmap_write(hsp_regmap, hsp_pwr_ctrl, EIC7700_HOST_VAL_STABLE); ++ ++ if ((host->mmc->caps2 & emmc_caps) == emmc_caps) ++ dwc_priv->delay_line = PHY_DELAY_CODE_EMMC; ++ else ++ dwc_priv->delay_line = PHY_DELAY_CODE_SD; ++ ++ if (!of_property_read_u32(dev->of_node, "eswin,drive-impedance-ohms", &val)) ++ priv->drive_impedance = eic7700_convert_drive_impedance_ohm(dev, val); ++ return 0; ++} ++ + static const struct sdhci_ops sdhci_dwcmshc_ops = { + .set_clock = sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, +@@ -1194,6 +1658,18 @@ static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { + .platform_execute_tuning = th1520_execute_tuning, + }; + ++static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { ++ .set_clock = sdhci_eic7700_set_clock, ++ .get_max_clock = sdhci_pltfm_clk_get_max_clock, ++ .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, ++ .set_bus_width = sdhci_set_bus_width, ++ .reset = sdhci_eic7700_reset, ++ .set_uhs_signaling = sdhci_eic7700_set_uhs_wrapper, ++ .set_power = sdhci_set_power_and_bus_voltage, ++ .irq = dwcmshc_cqe_irq_handler, ++ .platform_execute_tuning = sdhci_eic7700_executing_tuning, ++}; ++ + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_ops, +@@ -1263,6 +1739,17 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { + .init = sg2042_init, + }; + ++static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = { ++ .pdata = { ++ .ops = &sdhci_dwcmshc_eic7700_ops, ++ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | ++ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | ++ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, ++ }, ++ .init = eic7700_init, ++}; ++ + static const struct cqhci_host_ops dwcmshc_cqhci_ops = { + .enable = dwcmshc_sdhci_cqe_enable, + .disable = sdhci_cqe_disable, +@@ -1363,6 +1850,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { + .compatible = "sophgo,sg2042-dwcmshc", + .data = &sdhci_dwcmshc_sg2042_pdata, + }, ++ { ++ .compatible = "eswin,eic7700-dwcmshc", ++ .data = &sdhci_dwcmshc_eic7700_pdata, ++ }, + {}, + }; + MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); +@@ -1595,17 +2086,6 @@ static int dwcmshc_resume(struct device *dev) + return ret; + } + +-static void dwcmshc_enable_card_clk(struct sdhci_host *host) +-{ +- u16 ctrl; +- +- ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); +- if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) { +- ctrl |= SDHCI_CLOCK_CARD_EN; +- sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); +- } +-} +- + static int dwcmshc_runtime_suspend(struct device *dev) + { + struct sdhci_host *host = dev_get_drvdata(dev); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0289-UPSTREAM-riscv-mm-Fixup-no5lvl-failure-when-vaddr-is.patch b/SPECS/linux-lts/0289-UPSTREAM-riscv-mm-Fixup-no5lvl-failure-when-vaddr-is.patch deleted file mode 100644 index 66787c96fb..0000000000 --- a/SPECS/linux-lts/0289-UPSTREAM-riscv-mm-Fixup-no5lvl-failure-when-vaddr-is.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 3de0647d68580730c9dea18c73c0c4298eeaea58 Mon Sep 17 00:00:00 2001 -From: "Guo Ren (Alibaba DAMO Academy)" -Date: Sun, 25 Jan 2026 00:52:12 -0500 -Subject: [PATCH 289/467] UPSTREAM: riscv: mm: Fixup no5lvl failure when vaddr - is invalid -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Unlike no4lvl, no5lvl still continues to detect satp, which -requires va=pa mapping. When pa=0x800000000000, no5lvl -would fail in Sv48 mode due to an illegal VA value of -0x800000000000. - -So, prevent detecting the satp flow for no5lvl, when -vaddr is invalid. Add the is_vaddr_valid() function for -checking. - -Fixes: 26e7aacb83df ("riscv: Allow to downgrade paging mode from the command line") -Cc: Alexandre Ghiti -Cc: Björn Töpel -Signed-off-by: Guo Ren (Alibaba DAMO Academy) -Tested-by: Fangyu Yu -Link: https://patch.msgid.link/20260125055212.433163-1-guoren@kernel.org -[pjw@kernel.org: cleaned up commit message] -Signed-off-by: Paul Walmsley -(cherry picked from commit db909bd7986c10da074917af3dae83a60fa65093) -Signed-off-by: Han Gao ---- - arch/riscv/mm/init.c | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index a7d0cde6536b..8f4e7e505906 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -852,6 +852,27 @@ static void __init set_mmap_rnd_bits_max(void) - mmap_rnd_bits_max = MMAP_VA_BITS - PAGE_SHIFT - 3; - } - -+static bool __init is_vaddr_valid(unsigned long va) -+{ -+ unsigned long up = 0; -+ -+ switch (satp_mode) { -+ case SATP_MODE_39: -+ up = 1UL << 38; -+ break; -+ case SATP_MODE_48: -+ up = 1UL << 47; -+ break; -+ case SATP_MODE_57: -+ up = 1UL << 56; -+ break; -+ default: -+ return false; -+ } -+ -+ return (va < up) || (va >= (ULONG_MAX - up + 1)); -+} -+ - /* - * There is a simple way to determine if 4-level is supported by the - * underlying hardware: establish 1:1 mapping in 4-level page table mode -@@ -893,6 +914,9 @@ static __init void set_satp_mode(uintptr_t dtb_pa) - set_satp_mode_pmd + PMD_SIZE, - PMD_SIZE, PAGE_KERNEL_EXEC); - retry: -+ if (!is_vaddr_valid(set_satp_mode_pmd)) -+ goto out; -+ - create_pgd_mapping(early_pg_dir, - set_satp_mode_pmd, - pgtable_l5_enabled ? -@@ -915,6 +939,7 @@ static __init void set_satp_mode(uintptr_t dtb_pa) - disable_pgtable_l4(); - } - -+out: - memset(early_pg_dir, 0, PAGE_SIZE); - memset(early_p4d, 0, PAGE_SIZE); - memset(early_pud, 0, PAGE_SIZE); --- -2.53.0 - diff --git a/SPECS/linux-lts/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch b/SPECS/linux-lts/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch new file mode 100644 index 0000000000..8991fa572e --- /dev/null +++ b/SPECS/linux-lts/0290-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-init-for-AXI-clock.patch @@ -0,0 +1,45 @@ +From eec5a961f5c9f3a5b4a99624544700e30ae02323 Mon Sep 17 00:00:00 2001 +From: Huan He +Date: Wed, 14 Jan 2026 20:21:41 +0800 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-dwcmshc: Fix init for AXI clock + for Eswin EIC7700 + +Accessing the High-Speed registers requires the AXI clock to be enabled. + +Signed-off-by: Huan He +Acked-by: Adrian Hunter +Fixes: 32b2633219d3 ("mmc: sdhci-of-dwcmshc: Add support for Eswin EIC7700") +Signed-off-by: Ulf Hansson +(cherry picked from commit fd9809ec6704db0c162b4510b11f877ec7b72065) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index dfad61f332c4..2ce2626a7993 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -1529,6 +1529,7 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm + { + u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; + unsigned int val, hsp_int_status, hsp_pwr_ctrl; ++ static const char * const clk_ids[] = {"axi"}; + struct of_phandle_args args; + struct eic7700_priv *priv; + struct regmap *hsp_regmap; +@@ -1546,6 +1547,11 @@ static int eic7700_init(struct device *dev, struct sdhci_host *host, struct dwcm + return ret; + } + ++ ret = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, ++ ARRAY_SIZE(clk_ids), clk_ids); ++ if (ret) ++ return ret; ++ + ret = of_parse_phandle_with_fixed_args(dev->of_node, "eswin,hsp-sp-csr", 2, 0, &args); + if (ret) { + dev_err(dev, "Fail to parse 'eswin,hsp-sp-csr' phandle (%d)\n", ret); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0290-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch b/SPECS/linux-lts/0290-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch deleted file mode 100644 index 9e5685bd91..0000000000 --- a/SPECS/linux-lts/0290-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch +++ /dev/null @@ -1,39 +0,0 @@ -From b163c53eda4a5dd98999c324051fbec43d33e6d9 Mon Sep 17 00:00:00 2001 -From: Zhengyu He -Date: Thu, 21 May 2026 22:44:45 +0800 -Subject: [PATCH 290/467] UPSTREAM: spi: dt-bindings: fsl-qspi: support - SpacemiT K3 - -Add the SpacemiT K3 QSPI compatible to the fsl-qspi binding. - -K3 and K1 use the same QSPI controller, so document the K3 compatible -with "spacemit,k1-qspi" as fallback. - -Signed-off-by: Cody Kang -Signed-off-by: Zhengyu He -Acked-by: Conor Dooley -Link: https://patch.msgid.link/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-1-52bce26e5fd8@gmail.com -Signed-off-by: Mark Brown -(cherry picked from commit 27cd2dde35b2c3b8659fa18f6a935c61fedee5c1) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml -index 1d10cfbad86c..504df31a4f90 100644 ---- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml -+++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml -@@ -20,6 +20,9 @@ properties: - - fsl,ls1021a-qspi - - fsl,ls2080a-qspi - - spacemit,k1-qspi -+ - items: -+ - const: spacemit,k3-qspi -+ - const: spacemit,k1-qspi - - items: - - enum: - - fsl,ls1043a-qspi --- -2.53.0 - diff --git a/SPECS/linux-lts/0291-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch b/SPECS/linux-lts/0291-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch deleted file mode 100644 index 1e760e063a..0000000000 --- a/SPECS/linux-lts/0291-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch +++ /dev/null @@ -1,45 +0,0 @@ -From ffdb403e8aa1eacebe47a4796578523b663508ee Mon Sep 17 00:00:00 2001 -From: Jiakai Xu -Date: Sun, 17 May 2026 12:44:14 +0000 -Subject: [PATCH 291/467] UPSTREAM: RISC-V: KVM: Fix NULL pointer dereference - in SBI v0.1 SEND_IPI handler - -The SBI v0.1 SEND_IPI handler iterates over the hart mask and calls -kvm_get_vcpu_by_id() to find the target vcpu for each set bit. When a -guest provides a hart mask containing bits for non-existent vcpu_ids, -kvm_get_vcpu_by_id() returns NULL, which is then unconditionally -dereferenced by kvm_riscv_vcpu_set_interrupt(), causing a kernel crash. - -Fix this by adding a NULL check before dereferencing the return value. -If the target vcpu is not found, skip it and continue processing the -remaining valid harts. - -Fixes: a046c2d8578c ("RISC-V: KVM: Reorganize SBI code by moving SBI v0.1 to its own file") -Signed-off-by: Jiakai Xu -Signed-off-by: Jiakai Xu -Assisted-by: OpenClaw:DeepSeek-V3.2 -Reviewed-by: Anup Patel -Link: https://lore.kernel.org/r/20260517124414.420919-1-xujiakai2025@iscas.ac.cn -Signed-off-by: Anup Patel -(cherry picked from commit fdb69d401967fd88d27982a7e4984b2a3a4f0314) -Signed-off-by: Han Gao ---- - arch/riscv/kvm/vcpu_sbi_v01.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c -index 368dfddd23d9..b6aef0e5ea57 100644 ---- a/arch/riscv/kvm/vcpu_sbi_v01.c -+++ b/arch/riscv/kvm/vcpu_sbi_v01.c -@@ -56,6 +56,8 @@ static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, - - for_each_set_bit(i, &hmask, BITS_PER_LONG) { - rvcpu = kvm_get_vcpu_by_id(vcpu->kvm, i); -+ if (!rvcpu) -+ continue; - ret = kvm_riscv_vcpu_set_interrupt(rvcpu, IRQ_VS_SOFT); - if (ret < 0) - break; --- -2.53.0 - diff --git a/SPECS/linux-lts/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch b/SPECS/linux-lts/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch new file mode 100644 index 0000000000..25b1fd7b47 --- /dev/null +++ b/SPECS/linux-lts/0291-UPSTREAM-mmc-sdhci-of-dwcmshc-Fix-DMA-128MB-boundary.patch @@ -0,0 +1,35 @@ +From 3cd03e009502a385f88e1102cb0517e2f25f455c Mon Sep 17 00:00:00 2001 +From: Huan He +Date: Wed, 14 Jan 2026 20:22:56 +0800 +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-dwcmshc: Fix DMA 128MB boundary + for Eswin EIC7700 + +This DWC MSHC has a 128MB limitation where the data buffer size and start +address must not exceed the 128MB boundary. Registering the missing +'adma_write_desc' callback function. + +Signed-off-by: Huan He +Acked-by: Adrian Hunter +Fixes: 32b2633219d3 ("mmc: sdhci-of-dwcmshc: Add support for Eswin EIC7700") +Signed-off-by: Ulf Hansson +(cherry picked from commit 5cfc828502cbd0c827113bdb5694c2658af2c37c) +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index 2ce2626a7993..90aa146a1be3 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -1673,6 +1673,7 @@ static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { + .set_uhs_signaling = sdhci_eic7700_set_uhs_wrapper, + .set_power = sdhci_set_power_and_bus_voltage, + .irq = dwcmshc_cqe_irq_handler, ++ .adma_write_desc = dwcmshc_adma_write_desc, + .platform_execute_tuning = sdhci_eic7700_executing_tuning, + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch b/SPECS/linux-lts/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch index 6ce60cb539..c72f779250 100644 --- a/SPECS/linux-lts/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch +++ b/SPECS/linux-lts/0292-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch @@ -1,7 +1,7 @@ -From a609d4433c7a1614a618e8aa8e2eab96362fefac Mon Sep 17 00:00:00 2001 +From 07935065ada83928cfb96ceab6a5ec204787eed5 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:36 +0100 -Subject: [PATCH 292/467] FROMGIT: drm/imagination: Count paired job fence as +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Count paired job fence as dependency in prepare_job() The DRM scheduler's prepare_job() callback counts the remaining diff --git a/SPECS/linux-lts/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch b/SPECS/linux-lts/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch index 02e01dee82..26a9e98208 100644 --- a/SPECS/linux-lts/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch +++ b/SPECS/linux-lts/0293-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch @@ -1,8 +1,8 @@ -From 9290d92ea555570942074fc606d13eb4d3bbf981 Mon Sep 17 00:00:00 2001 +From cc7e1eff70086b94e4cc0442c78e493d14ea2a91 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:37 +0100 -Subject: [PATCH 293/467] FROMGIT: drm/imagination: Fit paired fragment job in - the correct CCCB +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Fit paired fragment job in the + correct CCCB For geometry jobs with a paired fragment job, at the moment, the DRM scheduler's prepare_job() callback: diff --git a/SPECS/linux-lts/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch b/SPECS/linux-lts/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch index 585fa629fa..ef8b49eec6 100644 --- a/SPECS/linux-lts/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch +++ b/SPECS/linux-lts/0294-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch @@ -1,8 +1,8 @@ -From 9a88a3b7b00b1c31c53573cb70a52e28c6a93a00 Mon Sep 17 00:00:00 2001 +From a64a810c6fa9b9f608d345c1c8fddcb487bf750a Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:38 +0100 -Subject: [PATCH 294/467] FROMGIT: drm/imagination: Skip check on paired job - fence during job submission +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Skip check on paired job fence + during job submission While submitting a paired fragment job, there is no need to manually look for, and skip, the paired job fence, as the existing logic to diff --git a/SPECS/linux-lts/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch b/SPECS/linux-lts/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch index eee3351fd4..9cc27fddc4 100644 --- a/SPECS/linux-lts/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch +++ b/SPECS/linux-lts/0295-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch @@ -1,7 +1,7 @@ -From f20230f3dc06eafd26b5cd6d132c0cca76331d33 Mon Sep 17 00:00:00 2001 +From 37bce3dfda3d6bfd8120dd4ca4ce59da566ffd8c Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:39 +0100 -Subject: [PATCH 295/467] FROMGIT: drm/imagination: Rename +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Rename pvr_queue_fence_is_ufo_backed() to reflect usage This function is only used by the synchronization code to figure out if diff --git a/SPECS/linux-lts/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch b/SPECS/linux-lts/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch index d4492c8980..726a6e00f1 100644 --- a/SPECS/linux-lts/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch +++ b/SPECS/linux-lts/0296-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch @@ -1,7 +1,7 @@ -From d480bfc6a4ff28539bca859b78544e8a3762c85e Mon Sep 17 00:00:00 2001 +From 1b5c97a61b1f397f31c97959e50a7bafe4997757 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:40 +0100 -Subject: [PATCH 296/467] FROMGIT: drm/imagination: Rename fence returned by +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Rename fence returned by pvr_queue_job_arm() Rename from done_fence to finished_fence, both because the function diff --git a/SPECS/linux-lts/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch b/SPECS/linux-lts/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch index 4e1d0d7c5d..aaa07dc5cb 100644 --- a/SPECS/linux-lts/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch +++ b/SPECS/linux-lts/0297-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch @@ -1,8 +1,8 @@ -From 24d18b49f8c07b709700ed96d89d8612d2fb5668 Mon Sep 17 00:00:00 2001 +From 03aa10e9329f54737669ec56c2b2ab66eac2f987 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:41 +0100 -Subject: [PATCH 297/467] FROMGIT: drm/imagination: Move repeated job fence - check to its own function +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Move repeated job fence check + to its own function This should make the code slightly clearer. diff --git a/SPECS/linux-lts/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch b/SPECS/linux-lts/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch index 6b4300cbe2..c27054fa2d 100644 --- a/SPECS/linux-lts/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch +++ b/SPECS/linux-lts/0298-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch @@ -1,7 +1,7 @@ -From 9f3709e29e576a8943a5c7b99d82d4a0293cc32f Mon Sep 17 00:00:00 2001 +From de6096b77f0bf0bf39ff10bd616f13c5e0945d58 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:42 +0100 -Subject: [PATCH 298/467] FROMGIT: drm/imagination: Update check to skip +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Update check to skip prepare_job() for fragment jobs By the time prepare_job() is called on a paired fragment job, the paired diff --git a/SPECS/linux-lts/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch b/SPECS/linux-lts/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch index fcc409d926..e093399458 100644 --- a/SPECS/linux-lts/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch +++ b/SPECS/linux-lts/0299-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch @@ -1,7 +1,7 @@ -From b1bc1325baa32b8ced34662415894d905572c0e3 Mon Sep 17 00:00:00 2001 +From fea5671abc67fb18ac13ed5ac838464e6ac1d034 Mon Sep 17 00:00:00 2001 From: Alessio Belle Date: Mon, 30 Mar 2026 08:56:43 +0100 -Subject: [PATCH 299/467] FROMGIT: drm/imagination: Minor improvements to job +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Minor improvements to job submission code documentation Mixed list of clarifications and typo fixes. diff --git a/SPECS/linux-lts/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch b/SPECS/linux-lts/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch index 3e227cd8fa..ed087c87c3 100644 --- a/SPECS/linux-lts/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch +++ b/SPECS/linux-lts/0300-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch @@ -1,7 +1,7 @@ -From 347d0feb0828177c85358f21ba7942d4d10abb3f Mon Sep 17 00:00:00 2001 +From d6e9674d63435e685b8f714dd05c6d76d0cd3383 Mon Sep 17 00:00:00 2001 From: Li Guan Date: Thu, 14 May 2026 02:07:21 +0800 -Subject: [PATCH 300/467] FROMGIT: perf riscv: Fix discarded const qualifier in +Subject: [RUYI PATCH] FROMGIT: perf riscv: Fix discarded const qualifier in _get_field() The assignment of strrchr() return values to non-const char * variables diff --git a/SPECS/linux-lts/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch b/SPECS/linux-lts/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch index d4d9cf39fa..df45fcf2dc 100644 --- a/SPECS/linux-lts/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch +++ b/SPECS/linux-lts/0301-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch @@ -1,7 +1,7 @@ -From c04270e93a53b96a6f98611da3684d1fb609b347 Mon Sep 17 00:00:00 2001 +From 9312f5952083473da163ade5c4b5f0cd1170caf2 Mon Sep 17 00:00:00 2001 From: "Guo Ren (Alibaba DAMO Academy)" Date: Tue, 21 Apr 2026 10:31:40 -0400 -Subject: [PATCH 301/467] FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE +Subject: [RUYI PATCH] FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup The early version of XuanTie C910 core has a store merge buffer diff --git a/SPECS/linux-lts/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch b/SPECS/linux-lts/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch index eb1ea9ea73..747ee38919 100644 --- a/SPECS/linux-lts/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch +++ b/SPECS/linux-lts/0302-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch @@ -1,7 +1,7 @@ -From f8ed95adec720bc723ed825f8d90a76e3b3b0a12 Mon Sep 17 00:00:00 2001 +From 4c835b4cf54a8879850b5743cbe7d75d2b218c9c Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 1 Apr 2026 01:56:57 +0800 -Subject: [PATCH 302/467] FROMLIST: PCI: Add per-device flag to disable native +Subject: [RUYI PATCH] FROMLIST: PCI: Add per-device flag to disable native PCIe port services Add PCI_DEV_FLAGS_NO_PORT_SERVICES to allow quirks to prevent the PCIe diff --git a/SPECS/linux-lts/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch b/SPECS/linux-lts/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch index 4f0837e1d9..58cd59ae0c 100644 --- a/SPECS/linux-lts/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch +++ b/SPECS/linux-lts/0303-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch @@ -1,8 +1,8 @@ -From 283d1e50a78cf88b9bc5a76ae2e1ce0163dc502a Mon Sep 17 00:00:00 2001 +From cfb56bdda1f734ba778e001d5436e62217a69a3c Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 1 Apr 2026 01:56:58 +0800 -Subject: [PATCH 303/467] FROMLIST: PCI: Add quirk to disable PCIe port - services on Sophgo SG2042 +Subject: [RUYI PATCH] FROMLIST: PCI: Add quirk to disable PCIe port services + on Sophgo SG2042 SG2042's PCIe root ports [1f1c:2042] fail to deliver MSI interrupts to downstream devices when native port services are enabled. Devices under diff --git a/SPECS/linux-lts/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch b/SPECS/linux-lts/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch index 3533acb885..92052a71a6 100644 --- a/SPECS/linux-lts/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch +++ b/SPECS/linux-lts/0304-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch @@ -1,8 +1,8 @@ -From 5061c065b398815d41839dbd6c2d13c2213c2d99 Mon Sep 17 00:00:00 2001 +From ef760574ea2b96b482691e4b76ea4544d2b04231 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Thu, 18 Sep 2025 13:58:56 -0700 -Subject: [PATCH 304/467] FROMLIST: PCI: Release BAR0 of an integrated bridge - to allow GPU BAR resize +Subject: [RUYI PATCH] FROMLIST: PCI: Release BAR0 of an integrated bridge to + allow GPU BAR resize MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch b/SPECS/linux-lts/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch index 41052b1644..826058c0bf 100644 --- a/SPECS/linux-lts/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch +++ b/SPECS/linux-lts/0305-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch @@ -1,7 +1,7 @@ -From 930af6ff12384f1fc15fbeaba533c8791537aafb Mon Sep 17 00:00:00 2001 +From 1f52ff4a8952f2dcd39f984b094e0d3ba4227bcd Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 29 Jun 2024 13:22:46 +0800 -Subject: [PATCH 305/467] BACKPORT: FROMLIST: drm/ttm: save the device's DMA +Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: save the device's DMA coherency status in ttm_device Currently TTM utilizes cached memory regardless of whether the device diff --git a/SPECS/linux-lts/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch b/SPECS/linux-lts/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch index 7dbe06800d..bb46fa248c 100644 --- a/SPECS/linux-lts/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch +++ b/SPECS/linux-lts/0306-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch @@ -1,7 +1,7 @@ -From 6b19f0c2ff8d4334e8350b2aba256942682560f0 Mon Sep 17 00:00:00 2001 +From 555ac6aeaf274981371546928300e152ff7ac153 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 29 Jun 2024 13:22:47 +0800 -Subject: [PATCH 306/467] BACKPORT: FROMLIST: drm/ttm: downgrade cached to +Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: downgrade cached to write_combined when snooping not available As we can now acquire the presence of the full DMA coherency (snooping diff --git a/SPECS/linux-lts/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch b/SPECS/linux-lts/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch index a7e829871e..58e516d738 100644 --- a/SPECS/linux-lts/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch +++ b/SPECS/linux-lts/0307-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch @@ -1,8 +1,8 @@ -From 09dc9193b8a9859bdfcf7826fcef126692322cfa Mon Sep 17 00:00:00 2001 +From 5911aa5fe93310aba068d9a4361bc5827ce35b62 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Thu, 20 Nov 2025 13:14:16 +0000 -Subject: [PATCH 307/467] FROMLIST: NFU: riscv: dts: thead: Add CPU clock and - OPP table for TH1520 +Subject: [RUYI PATCH] FROMLIST: NFU: riscv: dts: thead: Add CPU clock and OPP + table for TH1520 Add operating point table for CPU cores, and wire up clocks for CPU nodes. diff --git a/SPECS/linux-lts/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch b/SPECS/linux-lts/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch index 1556101b34..207ec24976 100644 --- a/SPECS/linux-lts/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch +++ b/SPECS/linux-lts/0308-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch @@ -1,7 +1,7 @@ -From fb63a586880480ca4a13569a25a63f4aecf4dc1c Mon Sep 17 00:00:00 2001 +From 1331a7f7caf771503583f18f7576c01b13e887ec Mon Sep 17 00:00:00 2001 From: Asuna Yang Date: Tue, 30 Dec 2025 17:47:54 +0100 -Subject: [PATCH 308/467] FROMLIST: rust: export BINDGEN_TARGET from a separate +Subject: [RUYI PATCH] FROMLIST: rust: export BINDGEN_TARGET from a separate Makefile A subsequent commit will add a new function `bindgen-option` to @@ -29,7 +29,7 @@ Signed-off-by: Han Gao create mode 100644 scripts/Makefile.rust diff --git a/Makefile b/Makefile -index dc63a98489a5..895fd1827580 100644 +index 5087bd6183dd..e5901ed88254 100644 --- a/Makefile +++ b/Makefile @@ -724,9 +724,10 @@ ifneq ($(findstring clang,$(CC_VERSION_TEXT)),) diff --git a/SPECS/linux-lts/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch b/SPECS/linux-lts/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch index 1346386899..99ff4e9cc0 100644 --- a/SPECS/linux-lts/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch +++ b/SPECS/linux-lts/0309-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch @@ -1,8 +1,8 @@ -From 68a1f8f93b448edbae9513aa35f8fdfd2d0c9d10 Mon Sep 17 00:00:00 2001 +From 22c8be25d1ed7a76f36d5f1d30f0c61faa68b951 Mon Sep 17 00:00:00 2001 From: Asuna Yang Date: Tue, 30 Dec 2025 17:47:55 +0100 -Subject: [PATCH 309/467] FROMLIST: rust: generate a fatal error if - BINDGEN_TARGET is undefined +Subject: [RUYI PATCH] FROMLIST: rust: generate a fatal error if BINDGEN_TARGET + is undefined Generate a friendly fatal error if the target triplet is undefined for bindgen, rather than having the compiler generate obscure error messages diff --git a/SPECS/linux-lts/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch b/SPECS/linux-lts/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch index 73dc849cc5..f14c7c2ccd 100644 --- a/SPECS/linux-lts/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch +++ b/SPECS/linux-lts/0310-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch @@ -1,7 +1,7 @@ -From e4594d4716d61ca97443e9a44af78e400c9462f9 Mon Sep 17 00:00:00 2001 +From 0bae0d06c2aca802becde0cd7d5cb153390dcd4d Mon Sep 17 00:00:00 2001 From: Asuna Yang Date: Tue, 30 Dec 2025 17:47:56 +0100 -Subject: [PATCH 310/467] FROMLIST: rust: add a Kconfig function to test for +Subject: [RUYI PATCH] FROMLIST: rust: add a Kconfig function to test for support of bindgen options Add a new `bindgen-backend-option` Kconfig function to test whether the diff --git a/SPECS/linux-lts/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch b/SPECS/linux-lts/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch index 89093b0689..22dad26c59 100644 --- a/SPECS/linux-lts/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch +++ b/SPECS/linux-lts/0311-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch @@ -1,8 +1,8 @@ -From 4a0cd79c6b96ef6fc06137c6845d2d4f679efee9 Mon Sep 17 00:00:00 2001 +From bdb364df3673e4e729a0e33788d91c7ace67e22e Mon Sep 17 00:00:00 2001 From: Asuna Yang Date: Tue, 30 Dec 2025 17:47:57 +0100 -Subject: [PATCH 311/467] FROMLIST: RISC-V: handle extension configs for - bindgen, re-enable gcc + rust builds +Subject: [RUYI PATCH] FROMLIST: RISC-V: handle extension configs for bindgen, + re-enable gcc + rust builds Commit 33549fcf37ec ("RISC-V: disallow gcc + rust builds") disabled GCC + Rust builds for RISC-V due to differences in extension handling diff --git a/SPECS/linux-lts/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch b/SPECS/linux-lts/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch index 26ee47ecbd..cde256c3dd 100644 --- a/SPECS/linux-lts/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch +++ b/SPECS/linux-lts/0312-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch @@ -1,7 +1,7 @@ -From 159388b0a2e5ca3f2f88124a933d969ed86fbeba Mon Sep 17 00:00:00 2001 +From 6b99e40ab4ea69deb0bef324e4a5160a020862f2 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Sun, 21 Dec 2025 16:20:26 +0800 -Subject: [PATCH 312/467] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add reset +Subject: [RUYI PATCH] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add reset support The SpacemiT SDHCI controller has two reset lines, one connect to AXI bus diff --git a/SPECS/linux-lts/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch b/SPECS/linux-lts/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch index d14424b2c5..27e125777e 100644 --- a/SPECS/linux-lts/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch +++ b/SPECS/linux-lts/0313-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch @@ -1,8 +1,8 @@ -From 8d7a4704394936b4c6294288c8ef99b5d613a2b5 Mon Sep 17 00:00:00 2001 +From e4c3413f71ca577a9344235a8e76978b9df6b41d Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 3 Nov 2025 00:02:00 +0100 -Subject: [PATCH 313/467] FROMLIST: mfd: simple-mfd-i2c: add a reboot cell for - the SpacemiT P1 chip +Subject: [RUYI PATCH] FROMLIST: mfd: simple-mfd-i2c: add a reboot cell for the + SpacemiT P1 chip Add a "spacemit-p1-reboot" cell for the SpacemiT P1 chip. diff --git a/SPECS/linux-lts/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch b/SPECS/linux-lts/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch index 6dfcd96600..2e6395db50 100644 --- a/SPECS/linux-lts/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch +++ b/SPECS/linux-lts/0314-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch @@ -1,7 +1,7 @@ -From 454712fedf570ad8e52defdca4d86a789ae66c49 Mon Sep 17 00:00:00 2001 +From 976f3a509c35b7b5a88d9f5f44f15301bbfef945 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 8 Jan 2026 16:38:54 +0800 -Subject: [PATCH 314/467] FROMLIST: regulator: spacemit: MFD_SPACEMIT_P1 as +Subject: [RUYI PATCH] FROMLIST: regulator: spacemit: MFD_SPACEMIT_P1 as dependencies REGULATOR_SPACEMIT_P1 is a subdevice of P1 and should depend on diff --git a/SPECS/linux-lts/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch b/SPECS/linux-lts/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch index e05b43ffa7..a28f57c29e 100644 --- a/SPECS/linux-lts/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch +++ b/SPECS/linux-lts/0315-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch @@ -1,7 +1,7 @@ -From 2364564dbaafd4e805bbea77f317865dd5622725 Mon Sep 17 00:00:00 2001 +From f7a63859a84191dd8619e6a34c9bf4d6664dcf23 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 8 Jan 2026 16:38:56 +0800 -Subject: [PATCH 315/467] FROMLIST: rtc: spacemit: default module when +Subject: [RUYI PATCH] FROMLIST: rtc: spacemit: default module when MFD_SPACEMIT_P1 is enabled The RTC driver defaulted to the same value as MFD_SPACEMIT_P1, which diff --git a/SPECS/linux-lts/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch b/SPECS/linux-lts/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch index 1418affeb4..6981bb7c1e 100644 --- a/SPECS/linux-lts/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch +++ b/SPECS/linux-lts/0316-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch @@ -1,8 +1,7 @@ -From a1ffb3d0ac5dd81cbe0345aa8213f747b7560145 Mon Sep 17 00:00:00 2001 +From 2a9661946f61c576e2b7534403eae881deb90a82 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Sat, 2 May 2026 21:30:51 -0400 -Subject: [PATCH 316/467] FROMLIST: spi: dt-bindings: add SpacemiT K1 SPI - support +Subject: [RUYI PATCH] FROMLIST: spi: dt-bindings: add SpacemiT K1 SPI support Add support for the SPI controller implemented by the SpacemiT K1 SoC. diff --git a/SPECS/linux-lts/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch b/SPECS/linux-lts/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch index 4359fe4be8..0ee0c336df 100644 --- a/SPECS/linux-lts/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch +++ b/SPECS/linux-lts/0317-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch @@ -1,7 +1,7 @@ -From 63948c550b2a578e8e796c78af7e572c4b02c041 Mon Sep 17 00:00:00 2001 +From 36ae899198d9231685aaf77e1dbcd6d51b0c9a76 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Sat, 2 May 2026 21:30:52 -0400 -Subject: [PATCH 317/467] FROMLIST: spi: spacemit: introduce SpacemiT K1 SPI +Subject: [RUYI PATCH] FROMLIST: spi: spacemit: introduce SpacemiT K1 SPI controller driver This patch introduces the driver for the SPI controller found in the diff --git a/SPECS/linux-lts/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch b/SPECS/linux-lts/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch index 0b7dc30a96..e4a7aa5c83 100644 --- a/SPECS/linux-lts/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch +++ b/SPECS/linux-lts/0318-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch @@ -1,8 +1,8 @@ -From 6d39268afdf29820170db1c0b7f7b3d785ed0795 Mon Sep 17 00:00:00 2001 +From e61e5b8803d80c43b4959f8e4b6e863d1730fe51 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Sat, 2 May 2026 21:30:53 -0400 -Subject: [PATCH 318/467] FROMLIST: riscv: dts: spacemit: define a SPI - controller node +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: define a SPI controller + node Define a node for the fourth SoC SPI controller (number 3) on the SpacemiT K1 SoC. diff --git a/SPECS/linux-lts/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch b/SPECS/linux-lts/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch index ff0f94f63b..7bd9ac4c2d 100644 --- a/SPECS/linux-lts/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch +++ b/SPECS/linux-lts/0319-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch @@ -1,8 +1,8 @@ -From 28a0a1dcd7e90cf89bf17b18faf7da6856e72983 Mon Sep 17 00:00:00 2001 +From 7769d31e702d0f09a02488efb2a7b55c42255417 Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Mon, 27 Apr 2026 15:15:15 +0800 -Subject: [PATCH 319/467] FROMLIST: dt-bindings: thermal: Add SpacemiT K1 - thermal sensor +Subject: [RUYI PATCH] FROMLIST: dt-bindings: thermal: Add SpacemiT K1 thermal + sensor Document the SpacemiT K1 Thermal Sensor, which supports monitoring temperatures for five zones: soc, package, gpu, cluster0, diff --git a/SPECS/linux-lts/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch b/SPECS/linux-lts/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch index 7b249b4f9e..0a1aad818b 100644 --- a/SPECS/linux-lts/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch +++ b/SPECS/linux-lts/0320-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch @@ -1,7 +1,7 @@ -From 28919e9eba67c4c3ff61ca30861fad9fbcf74dca Mon Sep 17 00:00:00 2001 +From e87ee0243fcb7c4480eb9766f9800d4905e11b24 Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Mon, 27 Apr 2026 15:15:16 +0800 -Subject: [PATCH 320/467] FROMLIST: thermal: spacemit: k1: Add thermal sensor +Subject: [RUYI PATCH] FROMLIST: thermal: spacemit: k1: Add thermal sensor support The thermal sensor on K1 supports monitoring five temperature zones. diff --git a/SPECS/linux-lts/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch b/SPECS/linux-lts/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch index e7612aa962..6ad93704d4 100644 --- a/SPECS/linux-lts/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch +++ b/SPECS/linux-lts/0321-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch @@ -1,8 +1,8 @@ -From 620eb1089f29269e2b8d8cb733ae93bd8bf2b73a Mon Sep 17 00:00:00 2001 +From 99bf7248cb67723d749134575afb9fcb3425bccd Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Mon, 27 Apr 2026 15:15:17 +0800 -Subject: [PATCH 321/467] FROMLIST: riscv: dts: spacemit: Add thermal sensor - for K1 SoC +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add thermal sensor for + K1 SoC Include the Thermal Sensor node in the SpacemiT K1 dtsi with definitions for registers, clocks, and interrupts. diff --git a/SPECS/linux-lts/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch b/SPECS/linux-lts/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch index 59ab5c280e..560b162481 100644 --- a/SPECS/linux-lts/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch +++ b/SPECS/linux-lts/0322-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch @@ -1,7 +1,7 @@ -From 9b48aded2603c80a65f27877a0ac7d5d6c21f77b Mon Sep 17 00:00:00 2001 +From 83a04d13a39350e2059289ae74da6a837187c63e Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 3 Mar 2026 17:24:21 +0800 -Subject: [PATCH 322/467] FROMLIST: net: spacemit: Free rings of memory after +Subject: [RUYI PATCH] FROMLIST: net: spacemit: Free rings of memory after unmapping DMA In emac_free_{tx,rx}_resources, call dma_free_coherent() to unmap DMA diff --git a/SPECS/linux-lts/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch b/SPECS/linux-lts/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch index 3dea49628f..5a383caca0 100644 --- a/SPECS/linux-lts/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch +++ b/SPECS/linux-lts/0323-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch @@ -1,8 +1,7 @@ -From 52f87bf6d6ba5fb8c57374827a76e0cfdaa332f4 Mon Sep 17 00:00:00 2001 +From 0615284b82b82ee1dc7ccbc7146e31afa8bbbc9f Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 3 Mar 2026 13:29:45 +0800 -Subject: [PATCH 323/467] FROMLIST: riscv: mm: Extract helper - mark_new_valid_map() +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Extract helper mark_new_valid_map() In preparation of a future patch using the same mechanism for non-vmalloc addresses, extract the mark_new_valid_map() helper from diff --git a/SPECS/linux-lts/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch b/SPECS/linux-lts/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch index e67a8f5e7c..24cfe28e1b 100644 --- a/SPECS/linux-lts/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch +++ b/SPECS/linux-lts/0324-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch @@ -1,8 +1,8 @@ -From 8417f8da2a6a1f07550805e452db0d0ebe5c568a Mon Sep 17 00:00:00 2001 +From a6ee02e2ad7a759a5906206b87b7525c1ac580e4 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 3 Mar 2026 13:29:46 +0800 -Subject: [PATCH 324/467] FROMLIST: riscv: kfence: Call mark_new_valid_map() - for kfence_unprotect() +Subject: [RUYI PATCH] FROMLIST: riscv: kfence: Call mark_new_valid_map() for + kfence_unprotect() In kfence_protect_page(), which kfence_unprotect() calls, we cannot send IPIs to other CPUs to ask them to flush TLB. This may lead to those CPUs diff --git a/SPECS/linux-lts/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch b/SPECS/linux-lts/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch index de6f2fb9c4..a75c6a24b4 100644 --- a/SPECS/linux-lts/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch +++ b/SPECS/linux-lts/0325-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch @@ -1,7 +1,7 @@ -From 99970ee4696d11a17cec30bcbaae18f61ca484e0 Mon Sep 17 00:00:00 2001 +From 0ff2687ed24d31a6e1dcee2c1fd287112688dabe Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 3 Mar 2026 13:29:47 +0800 -Subject: [PATCH 325/467] FROMLIST: riscv: mm: Rename new_vmalloc into +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Rename new_vmalloc into new_valid_map_cpus Since this mechanism is now used for the kfence pool, which comes from diff --git a/SPECS/linux-lts/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch b/SPECS/linux-lts/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch index 4e1aa9308b..6e8c075234 100644 --- a/SPECS/linux-lts/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch +++ b/SPECS/linux-lts/0326-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch @@ -1,7 +1,7 @@ -From de070642f61aec41c533f778ceb930d16a10c18b Mon Sep 17 00:00:00 2001 +From e7c9b52a88814781a9b973a8bc5d43cb3655f869 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 3 Mar 2026 13:29:48 +0800 -Subject: [PATCH 326/467] FROMLIST: riscv: mm: Use the bitmap API for +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Use the bitmap API for new_valid_map_cpus The bitmap was defined with incorrect size. Fix it by using the proper diff --git a/SPECS/linux-lts/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch b/SPECS/linux-lts/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch index 5c74f6500e..9d00d9a51f 100644 --- a/SPECS/linux-lts/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch +++ b/SPECS/linux-lts/0327-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch @@ -1,7 +1,7 @@ -From 4ffd4c28732d478d17dffb2e85279d7eca746271 Mon Sep 17 00:00:00 2001 +From 0236a57f077395bd67012bf4e9d33ba23ecdedd5 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Tue, 3 Mar 2026 13:29:49 +0800 -Subject: [PATCH 327/467] FROMLIST: riscv: mm: Unconditionally sfence.vma for +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Unconditionally sfence.vma for spurious fault Svvptc does not guarantee that it's safe to just return here. Since we diff --git a/SPECS/linux-lts/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch b/SPECS/linux-lts/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch index 43c7534f17..113e960802 100644 --- a/SPECS/linux-lts/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch +++ b/SPECS/linux-lts/0328-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch @@ -1,8 +1,8 @@ -From bba7975767efba6ca778e4283bcfd050aa140145 Mon Sep 17 00:00:00 2001 +From 1bee6d3eac2cd34b39a8ce2c3e590aaf2f4f38f1 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 5 Mar 2026 01:00:51 +0000 -Subject: [PATCH 328/467] FROMLIST: dt-bindings: phy: spacemit: k3: add USB2 - PHY support +Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: spacemit: k3: add USB2 PHY + support Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP of USB2 PHY mostly shares the same functionalities with K1 SoC, while has diff --git a/SPECS/linux-lts/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch b/SPECS/linux-lts/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch index 1d3d66b5ab..309f8ea1b2 100644 --- a/SPECS/linux-lts/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch +++ b/SPECS/linux-lts/0329-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch @@ -1,7 +1,7 @@ -From 0ad076c041bad32acd43346053a2e901e8f92fe6 Mon Sep 17 00:00:00 2001 +From e42b13b733fe6bf35801da4dd939e98421377976 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 5 Mar 2026 01:00:52 +0000 -Subject: [PATCH 329/467] FROMLIST: phy: k1-usb: k3: add USB2 PHY support +Subject: [RUYI PATCH] FROMLIST: phy: k1-usb: k3: add USB2 PHY support Add USB2 PHY support for SpacemiT K3 SoC. diff --git a/SPECS/linux-lts/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch b/SPECS/linux-lts/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch index 3e745bddcc..f84dd26276 100644 --- a/SPECS/linux-lts/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch +++ b/SPECS/linux-lts/0330-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch @@ -1,7 +1,7 @@ -From 23c19485341345cc9ae14d6943205d5dec3eb56e Mon Sep 17 00:00:00 2001 +From 313a26d3fa86f65c2c9bcfdaa1d325594d4d3960 Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Fri, 10 Apr 2026 15:58:22 +0800 -Subject: [PATCH 330/467] FROMLIST: cpufreq: dt-platdev: Add SpacemiT K1 SoC to +Subject: [RUYI PATCH] FROMLIST: cpufreq: dt-platdev: Add SpacemiT K1 SoC to the allowlist The SpacemiT K1 SoC uses standard device tree based CPU frequency diff --git a/SPECS/linux-lts/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch b/SPECS/linux-lts/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch index 4dea3b010e..ab37eecf22 100644 --- a/SPECS/linux-lts/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch +++ b/SPECS/linux-lts/0331-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch @@ -1,8 +1,8 @@ -From 2dd9746124535df6e29c3f1b6ac66084412c1e34 Mon Sep 17 00:00:00 2001 +From 76023519e9da3b79768d23f7ffe1a08e230674bd Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Fri, 10 Apr 2026 15:58:23 +0800 -Subject: [PATCH 331/467] FROMLIST: riscv: dts: spacemit: Add cpu scaling for - K1 SoC +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add cpu scaling for K1 + SoC Add Operating Performance Points (OPP) tables and CPU clock properties for the two clusters in the SpacemiT K1 SoC. diff --git a/SPECS/linux-lts/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch b/SPECS/linux-lts/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch index 6f2c86a077..a5d6058fa5 100644 --- a/SPECS/linux-lts/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch +++ b/SPECS/linux-lts/0332-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch @@ -1,7 +1,7 @@ -From 84df59a45f81e8ef941f44d41c695a0186bc324d Mon Sep 17 00:00:00 2001 +From b71c8252ef37bceafb077b1ac8b79eb81f094356 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Mon, 9 Mar 2026 19:09:38 +0800 -Subject: [PATCH 332/467] FROMLIST: riscv: mm: Define DIRECT_MAP_PHYSMEM_END +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Define DIRECT_MAP_PHYSMEM_END On RISC-V, the actual mappable range of physical address space is dependent on the current MMU mode i.e. satp_mode (See diff --git a/SPECS/linux-lts/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch b/SPECS/linux-lts/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch index ffdaa4ceaf..3cac36fd67 100644 --- a/SPECS/linux-lts/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch +++ b/SPECS/linux-lts/0333-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch @@ -1,8 +1,7 @@ -From e9080d8837f54bf02fccf98d737de780bbba0ca0 Mon Sep 17 00:00:00 2001 +From 3d54bf791cf5017cc96bc5222094dc98fb50e585 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 01:56:09 +0800 -Subject: [PATCH 333/467] FROMLIST: drm: verisilicon: add max cursor size to - HWDB +Subject: [RUYI PATCH] FROMLIST: drm: verisilicon: add max cursor size to HWDB Different display controller variants support different maximum cursor size. All known DC8200 variants support both 32x32 and 64x64, but some diff --git a/SPECS/linux-lts/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch b/SPECS/linux-lts/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch index efa9ea2a66..0430f73844 100644 --- a/SPECS/linux-lts/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch +++ b/SPECS/linux-lts/0334-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch @@ -1,7 +1,7 @@ -From 2bd08175bb99fd7bbb5cb6b7fdd965ec4ba85dc8 Mon Sep 17 00:00:00 2001 +From 5b2cb452135b05fe65a5440fa7f2e39d9b28d5f3 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 01:56:10 +0800 -Subject: [PATCH 334/467] FROMLIST: drm: verisilicon: add support for cursor +Subject: [RUYI PATCH] FROMLIST: drm: verisilicon: add support for cursor planes Verisilicon display controllers support hardware cursors per output diff --git a/SPECS/linux-lts/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch b/SPECS/linux-lts/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch index a0682cc71a..6d1f390fdf 100644 --- a/SPECS/linux-lts/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch +++ b/SPECS/linux-lts/0335-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch @@ -1,7 +1,7 @@ -From cfebf812bf3cf178789e8e4b6e59b083c727c04a Mon Sep 17 00:00:00 2001 +From 7670121cc9020d50b0705929db01a06e18578be0 Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Mon, 27 Apr 2026 09:32:10 +0800 -Subject: [PATCH 335/467] FROMLIST: riscv: add UltraRISC SoC family Kconfig +Subject: [RUYI PATCH] FROMLIST: riscv: add UltraRISC SoC family Kconfig support The first SoC in the UltraRISC series is UR-DP1000, containing octa diff --git a/SPECS/linux-lts/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch b/SPECS/linux-lts/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch index 3b43f26e44..e2d8d4c7b2 100644 --- a/SPECS/linux-lts/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch +++ b/SPECS/linux-lts/0336-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch @@ -1,7 +1,7 @@ -From e5f3fecea63d9f7a27e40543136978db11aaa96e Mon Sep 17 00:00:00 2001 +From 7bdcfb039d0ab0b746a0ee44a449149463a7b94e Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Mon, 27 Apr 2026 09:32:11 +0800 -Subject: [PATCH 336/467] FROMLIST: dt-bindings: PCI: Add UltraRISC DP1000 PCIe +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. diff --git a/SPECS/linux-lts/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch b/SPECS/linux-lts/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch index 7be27531fb..520f243b8f 100644 --- a/SPECS/linux-lts/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch +++ b/SPECS/linux-lts/0337-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch @@ -1,8 +1,8 @@ -From 5bcc18d72b72bff66068705f1f27ce4557a42f48 Mon Sep 17 00:00:00 2001 +From 4263860bea4eb50e8c9cce4769c096e144fd0400 Mon Sep 17 00:00:00 2001 From: Xincheng Zhang Date: Mon, 27 Apr 2026 09:32:12 +0800 -Subject: [PATCH 337/467] FROMLIST: PCI: ultrarisc: Add UltraRISC DP1000 PCIe - Root Complex driver +Subject: [RUYI PATCH] FROMLIST: PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root + Complex driver Add DP1000 SoC PCIe Root Complex driver. diff --git a/SPECS/linux-lts/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch b/SPECS/linux-lts/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch index ec329324ac..43fcf3979b 100644 --- a/SPECS/linux-lts/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch +++ b/SPECS/linux-lts/0338-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch @@ -1,8 +1,8 @@ -From 886ed98a1e1397b695753fffcc8263183552c408 Mon Sep 17 00:00:00 2001 +From 7215c59bd1680f8f694982585919d6ec01c2e009 Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Tue, 28 Apr 2026 13:26:26 +0800 -Subject: [PATCH 338/467] FROMLIST: serial: 8250_dwlib: move DesignWare - register definitions to header +Subject: [RUYI PATCH] FROMLIST: serial: 8250_dwlib: move DesignWare register + definitions to header Move the DW_UART_* register offsets and CPR bit/field definitions from 8250_dwlib.c into 8250_dwlib.h so they can be shared by 8250_dw and diff --git a/SPECS/linux-lts/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch b/SPECS/linux-lts/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch index 130d9f9ba9..361bfc6547 100644 --- a/SPECS/linux-lts/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch +++ b/SPECS/linux-lts/0339-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch @@ -1,8 +1,8 @@ -From 42a71ab9826c831f05fc6ceba6e355108b57394e Mon Sep 17 00:00:00 2001 +From 6180d1c44da7f8a61ffe42b1aa5f7fed0db947c5 Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Tue, 28 Apr 2026 13:26:27 +0800 -Subject: [PATCH 339/467] FROMLIST: serial: 8250_dw: build Renesas RZN1 CPR - value from DW_UART_CPR_* definitions +Subject: [RUYI PATCH] FROMLIST: serial: 8250_dw: build Renesas RZN1 CPR value + from DW_UART_CPR_* definitions Replace the magic CPR value for Renesas RZ/N1 with a composition using DW_UART_CPR_* bit/field definitions and FIELD_PREP_CONST(). diff --git a/SPECS/linux-lts/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch b/SPECS/linux-lts/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch index 7595c4aa93..2d2f322fc8 100644 --- a/SPECS/linux-lts/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch +++ b/SPECS/linux-lts/0340-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch @@ -1,7 +1,7 @@ -From 236f493127f843659bf2a955a31f416c1f8239bf Mon Sep 17 00:00:00 2001 +From 0b0183bf49240d8f6c2d66b6eaff2fe17c541d19 Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Tue, 28 Apr 2026 13:26:28 +0800 -Subject: [PATCH 340/467] FROMLIST: dt-bindings: serial: snps-dw-apb-uart: Add +Subject: [RUYI PATCH] FROMLIST: dt-bindings: serial: snps-dw-apb-uart: Add UltraRISC DP1000 UART UltraRISC DP1000 integrates a Synopsys DesignWare APB UART, but it does diff --git a/SPECS/linux-lts/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch b/SPECS/linux-lts/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch index 35aee10ecf..710885bf79 100644 --- a/SPECS/linux-lts/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch +++ b/SPECS/linux-lts/0341-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch @@ -1,7 +1,7 @@ -From 406c8fb8927861192219fce3ae1613ad4a1e0f0e Mon Sep 17 00:00:00 2001 +From 07e647f6d38a2395768391b1126d6af257685679 Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Tue, 28 Apr 2026 13:26:29 +0800 -Subject: [PATCH 341/467] FROMLIST: serial: 8250_dw: Use a fixed CPR value for +Subject: [RUYI PATCH] FROMLIST: serial: 8250_dw: Use a fixed CPR value for UltraRISC DP1000 UART The UltraRISC DP1000 UART does not provide the standard CPR register used diff --git a/SPECS/linux-lts/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch b/SPECS/linux-lts/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch index 0f7ba1cddb..e964c8cfd5 100644 --- a/SPECS/linux-lts/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch +++ b/SPECS/linux-lts/0342-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch @@ -1,8 +1,8 @@ -From 1c12aaa685ca33a5f2a5de71d4290b7374d1266c Mon Sep 17 00:00:00 2001 +From 53a9a6f9561ecf77c64e14e718b3c6677e450356 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Tue, 17 Mar 2026 16:48:06 +0800 -Subject: [PATCH 342/467] FROMLIST: riscv: disable local interrupts and stop - other CPUs before reboot/shutdown +Subject: [RUYI PATCH] FROMLIST: riscv: disable local interrupts and stop other + CPUs before reboot/shutdown Currently, the RISC-V implementation of machine_restart(), machine_halt(), and machine_power_off() invokes the kernel teardown chains (e.g., diff --git a/SPECS/linux-lts/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch b/SPECS/linux-lts/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch index 4858ae86ef..baf487668c 100644 --- a/SPECS/linux-lts/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch +++ b/SPECS/linux-lts/0343-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch @@ -1,8 +1,8 @@ -From ccbeae62330c25b6ad110b82754b6ef592620f48 Mon Sep 17 00:00:00 2001 +From c3dbfd57b9930def2f6e386d4a107127d798a89e Mon Sep 17 00:00:00 2001 From: Felix Gu Date: Sat, 21 Mar 2026 03:12:10 +0800 -Subject: [PATCH 343/467] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix error check - on dw_hdmi_probe() return value +Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix error check on + dw_hdmi_probe() return value The error check after calling dw_hdmi_probe() was incorrectly checking the struct pointer hdmi instead of the probe result hdmi->dw_hdmi. diff --git a/SPECS/linux-lts/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch b/SPECS/linux-lts/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch index 98f6f2d216..107fa9a940 100644 --- a/SPECS/linux-lts/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch +++ b/SPECS/linux-lts/0344-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch @@ -1,7 +1,7 @@ -From a97ea68639336a5b8e0fdb9e4c6983351f80d0a9 Mon Sep 17 00:00:00 2001 +From e4498bef7d35202c1d4fff03e1f738c01c63141b Mon Sep 17 00:00:00 2001 From: Felix Gu Date: Sat, 21 Mar 2026 03:12:11 +0800 -Subject: [PATCH 344/467] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix remove() +Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix remove() callback This driver stores struct th1520_hdmi * in platform drvdata, but diff --git a/SPECS/linux-lts/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux-lts/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch index f3db0b293e..f320d51fd9 100644 --- a/SPECS/linux-lts/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch +++ b/SPECS/linux-lts/0345-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch @@ -1,8 +1,8 @@ -From 166375a08d14e14a8b6eb3f9258fcba57cb866dc Mon Sep 17 00:00:00 2001 +From b6fedd583f0486d6ff23a73e611445adac11b2b7 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Tue, 7 Apr 2026 23:28:14 +0800 -Subject: [PATCH 345/467] FROMLIST: riscv: dts: spacemit: Enable i2c8 adapter - for OrangePi RV2 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Enable i2c8 adapter for + OrangePi RV2 The adapter is used to access the SpacemiT P1 PMIC present in this board. diff --git a/SPECS/linux-lts/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux-lts/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch index 917a05e075..d8cc2b7e7f 100644 --- a/SPECS/linux-lts/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch +++ b/SPECS/linux-lts/0346-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch @@ -1,7 +1,7 @@ -From 604976f3e404c825a56845e3b4bd0137fc436656 Mon Sep 17 00:00:00 2001 +From 8a8b83695e5206dc768419823d357d36066dcc1a Mon Sep 17 00:00:00 2001 From: Han Gao Date: Tue, 7 Apr 2026 23:28:15 +0800 -Subject: [PATCH 346/467] FROMLIST: riscv: dts: spacemit: Define the P1 PMIC +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2 Define the DC power input and the 4v power as fixed regulator supplies. diff --git a/SPECS/linux-lts/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch b/SPECS/linux-lts/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch index cb5590d8b9..2eece049ed 100644 --- a/SPECS/linux-lts/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch +++ b/SPECS/linux-lts/0347-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch @@ -1,7 +1,7 @@ -From f555e0c21e1df43b0df0074068872e999f825c2b Mon Sep 17 00:00:00 2001 +From be6360dcda59815d23e91c2273c7af8ee688b197 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Tue, 7 Apr 2026 23:28:16 +0800 -Subject: [PATCH 347/467] FROMLIST: riscv: dts: spacemit: Enable USB3.0/PCIe on +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2 Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the diff --git a/SPECS/linux-lts/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch b/SPECS/linux-lts/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch index b8175caff4..ec194d2c76 100644 --- a/SPECS/linux-lts/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch +++ b/SPECS/linux-lts/0348-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch @@ -1,7 +1,7 @@ -From 737838a83cfda4cb3b3cf4a600489972c9b23a6d Mon Sep 17 00:00:00 2001 +From 35352343154bd3b77a7ce708b33610ead4fa645b Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 18 May 2026 11:32:41 +0800 -Subject: [PATCH 348/467] FROMLIST: dt-bindings: dmaengine: Add SpacemiT K3 DMA +Subject: [RUYI PATCH] FROMLIST: dt-bindings: dmaengine: Add SpacemiT K3 DMA compatible string Add the "spacemit,k3-pdma" compatible string for the SpacemiT K3 SoC. diff --git a/SPECS/linux-lts/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch b/SPECS/linux-lts/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch index 71e53cff3d..2671371cc9 100644 --- a/SPECS/linux-lts/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch +++ b/SPECS/linux-lts/0349-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch @@ -1,7 +1,7 @@ -From 5f2df0c7e8305b8b19caa95ac987d272196435e5 Mon Sep 17 00:00:00 2001 +From 086a8550aad82551854f105777656e655e68512f Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 18 May 2026 11:32:42 +0800 -Subject: [PATCH 349/467] FROMLIST: dmaengine: mmp_pdma: refactor DRCMR access +Subject: [RUYI PATCH] FROMLIST: dmaengine: mmp_pdma: refactor DRCMR access with helper function Refactor the DRCMR macro into a helper function mmp_pdma_get_drcmr() diff --git a/SPECS/linux-lts/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch b/SPECS/linux-lts/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch index 8c3206e558..db3d534951 100644 --- a/SPECS/linux-lts/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch +++ b/SPECS/linux-lts/0350-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch @@ -1,8 +1,7 @@ -From 84f3de67f834507b179cd81bf093f799203f394a Mon Sep 17 00:00:00 2001 +From e077c02ed73be7f8782ceacc9a2f7dd9396857b0 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Mon, 18 May 2026 11:32:43 +0800 -Subject: [PATCH 350/467] FROMLIST: dmaengine: mmp_pdma: add SpacemiT K3 - support +Subject: [RUYI PATCH] FROMLIST: dmaengine: mmp_pdma: add SpacemiT K3 support SpacemiT K3 reuses most of the PDMA IP design found on K1, with one difference being the extended DRCMR base address. Add "spacemit,k3-pdma" diff --git a/SPECS/linux-lts/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch b/SPECS/linux-lts/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch index 22e28c9866..3b955dda90 100644 --- a/SPECS/linux-lts/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch +++ b/SPECS/linux-lts/0351-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch @@ -1,8 +1,8 @@ -From 35c22cf7e41f72e6b806aa58d4e48f88725f6c79 Mon Sep 17 00:00:00 2001 +From 21b7895de7539f827659bef3d905b99563ac4277 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Mon, 18 May 2026 11:32:44 +0800 -Subject: [PATCH 351/467] FROMLIST: riscv: dts: spacemit: Add PDMA controller - node for K3 SoC +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add PDMA controller node + for K3 SoC Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC. The PDMA controller provides general-purpose DMA capabilities for various diff --git a/SPECS/linux-lts/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch b/SPECS/linux-lts/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch index dbfadcecc7..505c1fcf8b 100644 --- a/SPECS/linux-lts/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch +++ b/SPECS/linux-lts/0352-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch @@ -1,7 +1,7 @@ -From de29158aef7f0ff1a48fb23a0fed37c1d80cd812 Mon Sep 17 00:00:00 2001 +From e45053fa3fb846fee16140a46bfca3810a696d3a Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 1 Apr 2026 01:12:47 +0800 -Subject: [PATCH 352/467] FROMLIST: dt-bindings: pci: sophgo: Add dma-coherent +Subject: [RUYI PATCH] FROMLIST: dt-bindings: pci: sophgo: Add dma-coherent property for SG2042 Add dma-coherent as an allowed property in the SG2042 PCIe host diff --git a/SPECS/linux-lts/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch b/SPECS/linux-lts/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch index 9b7fdd2999..59e22401d2 100644 --- a/SPECS/linux-lts/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch +++ b/SPECS/linux-lts/0353-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch @@ -1,8 +1,8 @@ -From 14a4dab155f695a1b19f164b9eeee33c118daf70 Mon Sep 17 00:00:00 2001 +From 4edb2b9deb6868de278295f9df339eb66e2dc5e6 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 1 Apr 2026 01:12:48 +0800 -Subject: [PATCH 353/467] FROMLIST: riscv: dts: sophgo: Add dma-coherent to - SG2042 PCIe controllers +Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: Add dma-coherent to SG2042 + PCIe controllers SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent diff --git a/SPECS/linux-lts/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch b/SPECS/linux-lts/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch index 618303a1e3..54ce584981 100644 --- a/SPECS/linux-lts/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch +++ b/SPECS/linux-lts/0354-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch @@ -1,7 +1,7 @@ -From 4d9c7d6292f64242b0740b0768cab12a1a481731 Mon Sep 17 00:00:00 2001 +From 4d5cd4b1f6fe26dc668fffd055e5d01af826c026 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Tue, 31 Mar 2026 15:37:22 +0800 -Subject: [PATCH 354/467] FROMLIST: riscv: mm: fix SWIOTLB initialization for +Subject: [RUYI PATCH] FROMLIST: riscv: mm: fix SWIOTLB initialization for systems with DRAM above 4GB On RISC-V platforms where the entire physical memory (DRAM) resides diff --git a/SPECS/linux-lts/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch b/SPECS/linux-lts/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch index 4200dc10cc..223d5a699f 100644 --- a/SPECS/linux-lts/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch +++ b/SPECS/linux-lts/0355-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch @@ -1,7 +1,7 @@ -From 2dc1b2a77fff1059529b2bbe0401aebebcef36b6 Mon Sep 17 00:00:00 2001 +From 1e089bd4441c081e557a84db781ccfe5f79b5601 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Wed, 25 Mar 2026 13:46:08 +0530 -Subject: [PATCH 355/467] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Add +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Add vcc5v0_sys regulator for Banana Pi F3 Define the system 5V fixed regulator (vcc5v0_sys) supplied by the diff --git a/SPECS/linux-lts/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch b/SPECS/linux-lts/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch index 8ff016743a..5fda255af1 100644 --- a/SPECS/linux-lts/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch +++ b/SPECS/linux-lts/0356-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch @@ -1,8 +1,8 @@ -From 9d3523b5cb45cb30a771f227a10b7c0231a04cca Mon Sep 17 00:00:00 2001 +From 9927a583ce5c19e8befcb7ed40a6238c53f79b35 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Wed, 25 Mar 2026 13:46:09 +0530 -Subject: [PATCH 356/467] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: - Update USB regulator on onboard usb and lable +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Update + USB regulator on onboard usb and lable Update the USB regulator labels to align with the board schematics and power hierarchy. This change renames the regulator to reg_5v_vbus and diff --git a/SPECS/linux-lts/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch b/SPECS/linux-lts/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch index ea69bfa145..a3dbb529e4 100644 --- a/SPECS/linux-lts/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch +++ b/SPECS/linux-lts/0357-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch @@ -1,8 +1,8 @@ -From c7a2f9b4d3c4915e78cf4248387543db008498e7 Mon Sep 17 00:00:00 2001 +From c3e497dbbb78a87638bd90cab0bd7540fd683d89 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Wed, 25 Mar 2026 13:46:10 +0530 -Subject: [PATCH 357/467] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: - Correct USB hub power hierarchy +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Correct + USB hub power hierarchy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch b/SPECS/linux-lts/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch index eb490256c2..39245052d3 100644 --- a/SPECS/linux-lts/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch +++ b/SPECS/linux-lts/0358-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch @@ -1,7 +1,7 @@ -From 630ef2347457f4560466095f5ad84c7b3acb944a Mon Sep 17 00:00:00 2001 +From a19f30eaeebdca312c928a1bd82a354ba9ce2e8e Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 26 Apr 2026 09:34:48 +0800 -Subject: [PATCH 358/467] FROMLIST: riscv: dts: sophgo: sg2044: use hex for CPU +Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: sg2044: use hex for CPU unit address Previous the CPU unit address cpu of sg2044 use decimal, it is diff --git a/SPECS/linux-lts/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch b/SPECS/linux-lts/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch index ae30ede27c..56f743e220 100644 --- a/SPECS/linux-lts/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch +++ b/SPECS/linux-lts/0359-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch @@ -1,7 +1,7 @@ -From 067a2a1c8ce433461ac63ad6029f55a9ec8e23e5 Mon Sep 17 00:00:00 2001 +From 1e554a628178f25ce798d80c22f6e32c9013f918 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 26 Apr 2026 09:34:49 +0800 -Subject: [PATCH 359/467] FROMLIST: riscv: dts: sophgo: sg2042: use hex for CPU +Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: sg2042: use hex for CPU unit address Previous the CPU unit address cpu of sg2042 use decimal, it is diff --git a/SPECS/linux-lts/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch b/SPECS/linux-lts/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch index 671d17f19a..3978b9eca3 100644 --- a/SPECS/linux-lts/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch +++ b/SPECS/linux-lts/0360-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch @@ -1,8 +1,8 @@ -From 7874ddbe01ccbe13b5a4828243511becf3108c87 Mon Sep 17 00:00:00 2001 +From 344151a10b042115f283ccb3ceb2241243f4f16a Mon Sep 17 00:00:00 2001 From: Nam Cao Date: Tue, 7 Apr 2026 14:06:39 +0200 -Subject: [PATCH 360/467] FROMLIST: riscv: Fix fast_unaligned_access_speed_key - not getting initialized +Subject: [RUYI PATCH] FROMLIST: riscv: Fix fast_unaligned_access_speed_key not + getting initialized The static key fast_unaligned_access_speed_key is supposed to be initialized after check_unaligned_access_all_cpus() has been completed. diff --git a/SPECS/linux-lts/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch b/SPECS/linux-lts/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch index 032ecea051..4ca22126b9 100644 --- a/SPECS/linux-lts/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch +++ b/SPECS/linux-lts/0361-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch @@ -1,8 +1,8 @@ -From 32a650e4403e9cc5000554982cacf78cf1e8d147 Mon Sep 17 00:00:00 2001 +From 6f609eb72f740d3d3be5b596fca48b7d76f3a181 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 8 Apr 2026 00:01:43 +0800 -Subject: [PATCH 361/467] FROMLIST: riscv: dts: sophgo: reduce SG2042 MSI count - to 16 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: reduce SG2042 MSI count to + 16 The SG2042 MSI controller has one 32-bit doorbell register, and each bit corresponds to an interrupt. At a glance, it seems that the MSI diff --git a/SPECS/linux-lts/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch b/SPECS/linux-lts/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch index 81da872e3d..fe8f74bcb4 100644 --- a/SPECS/linux-lts/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch +++ b/SPECS/linux-lts/0362-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch @@ -1,7 +1,7 @@ -From 4d5d4944086158dd4169828c2d3596f2ec8291f4 Mon Sep 17 00:00:00 2001 +From a42a4931c6355f9aec78b37eacf4e7f01afaa772 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 28 Apr 2026 10:46:50 +0000 -Subject: [PATCH 362/467] FROMLIST: dt-bindings: pwm: marvell,pxa-pwm: Add +Subject: [RUYI PATCH] FROMLIST: dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K3 PWM support The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1 diff --git a/SPECS/linux-lts/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch b/SPECS/linux-lts/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch index 0516614297..8346eff059 100644 --- a/SPECS/linux-lts/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch +++ b/SPECS/linux-lts/0363-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch @@ -1,7 +1,7 @@ -From 9f3707cb456d37931f9025ad6d4c4f1e44e27460 Mon Sep 17 00:00:00 2001 +From 2173dcb3b9c7cd083216f7561ca2c80cc779e6c3 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 28 Apr 2026 10:46:51 +0000 -Subject: [PATCH 363/467] FROMLIST: pwm: pxa: Add optional bus clock +Subject: [RUYI PATCH] FROMLIST: pwm: pxa: Add optional bus clock Add one secondary optional bus clock for the PWM PXA driver, also keep it compatible with old single clock. diff --git a/SPECS/linux-lts/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch b/SPECS/linux-lts/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch index d409c0ae6f..169b4e07b6 100644 --- a/SPECS/linux-lts/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch +++ b/SPECS/linux-lts/0364-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch @@ -1,7 +1,7 @@ -From 6240fb17598cbb164c6964e57937b0e241213797 Mon Sep 17 00:00:00 2001 +From a9afe33a20c57d9588e3a723da69fe92572f5726 Mon Sep 17 00:00:00 2001 From: Chen Pei Date: Thu, 9 Apr 2026 19:47:36 +0800 -Subject: [PATCH 364/467] FROMLIST: riscv: ftrace: select +Subject: [RUYI PATCH] FROMLIST: riscv: ftrace: select HAVE_BUILDTIME_MCOUNT_SORT RISC-V already satisfies all prerequisites for build-time mcount sorting: diff --git a/SPECS/linux-lts/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch b/SPECS/linux-lts/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch index 0c063dad19..63660577e2 100644 --- a/SPECS/linux-lts/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch +++ b/SPECS/linux-lts/0365-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch @@ -1,8 +1,8 @@ -From 198b6af6a42ee5ace108899f8074347faeed4504 Mon Sep 17 00:00:00 2001 +From 62c0719d1e7faf6136869e6f6da6b1f069f63523 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 18 May 2026 18:00:30 +0800 -Subject: [PATCH 365/467] FROMLIST: riscv: dts: spacemit: enable USB3 on - OrangePi R2S +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable USB3 on OrangePi + R2S Enable the DWC3 USB3.0 controller and its associated PHY on the OrangePi R2S. The USB regulator provides VBUS for USB2 and USB3 diff --git a/SPECS/linux-lts/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch b/SPECS/linux-lts/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch index 2398e5b545..84486826fc 100644 --- a/SPECS/linux-lts/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch +++ b/SPECS/linux-lts/0366-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch @@ -1,7 +1,7 @@ -From 1810a45e1f7eb932747edb129c2cc22f50a85617 Mon Sep 17 00:00:00 2001 +From 5d9676891cd5d6a9735391e8b346e75d7f6559c9 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 28 Apr 2026 10:57:29 +0000 -Subject: [PATCH 366/467] FROMLIST: dts: riscv: spacemit: correct 32k clock +Subject: [RUYI PATCH] FROMLIST: dts: riscv: spacemit: correct 32k clock frequency The 32k oscillator's clock frequency is actually 32768Hz, so correct it. diff --git a/SPECS/linux-lts/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch b/SPECS/linux-lts/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch index e142c9f76a..ae80025a53 100644 --- a/SPECS/linux-lts/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch +++ b/SPECS/linux-lts/0367-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch @@ -1,7 +1,7 @@ -From d0fad1ec15d004a802d36b225277a28831021f52 Mon Sep 17 00:00:00 2001 +From 50c5274eb867073ad2b53bef51e6d9d19aa9ac2a Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 7 May 2026 15:33:09 +0800 -Subject: [PATCH 367/467] FROMLIST: ASoC: dt-bindings: add SpacemiT K3 SoC +Subject: [RUYI PATCH] FROMLIST: ASoC: dt-bindings: add SpacemiT K3 SoC compatible Add the spacemit,k3-i2s compatible string for the K3 SoC I2S diff --git a/SPECS/linux-lts/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch b/SPECS/linux-lts/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch index 872f1859cf..f0c06195d2 100644 --- a/SPECS/linux-lts/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch +++ b/SPECS/linux-lts/0368-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch @@ -1,7 +1,7 @@ -From fdabd394ccbcb3a01600534aae7a6a5b2c4adf5d Mon Sep 17 00:00:00 2001 +From ff69086b4bd33d60ba9c418d37ac92992aae8876 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 7 May 2026 15:33:10 +0800 -Subject: [PATCH 368/467] FROMLIST: ASoC: spacemit: add K3 SoC support with +Subject: [RUYI PATCH] FROMLIST: ASoC: spacemit: add K3 SoC support with additional clocks Add support for the SpacemiT K3 SoC I2S controller, which shares the diff --git a/SPECS/linux-lts/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch b/SPECS/linux-lts/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch index 0fc85b0aa1..7eaa0d4690 100644 --- a/SPECS/linux-lts/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch +++ b/SPECS/linux-lts/0369-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch @@ -1,7 +1,7 @@ -From 71e5ec3830b135ac33f67234ab3560e96b244d65 Mon Sep 17 00:00:00 2001 +From 0151c24b6a7cffec1479bc57a27443328f1d2fef Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 7 May 2026 18:31:42 +0800 -Subject: [PATCH 369/467] FROMLIST: ASoC: soc-dai: add shared BCLK clock for +Subject: [RUYI PATCH] FROMLIST: ASoC: soc-dai: add shared BCLK clock for cross-DAI rate constraints Add a bclk field to struct snd_soc_dai and a helper function diff --git a/SPECS/linux-lts/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch b/SPECS/linux-lts/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch index 8633e3a2c1..b2112c73cc 100644 --- a/SPECS/linux-lts/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch +++ b/SPECS/linux-lts/0370-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch @@ -1,8 +1,8 @@ -From eafa7c60eb86e4ce51877b8dedcc634a13188bcf Mon Sep 17 00:00:00 2001 +From 811d7e0186f2cec4b5ebbd7506439ef84e15a0ff Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 7 May 2026 18:31:43 +0800 -Subject: [PATCH 370/467] FROMLIST: ASoC: soc-pcm: constrain hw_params when - DAIs share the same BCLK +Subject: [RUYI PATCH] FROMLIST: ASoC: soc-pcm: constrain hw_params when DAIs + share the same BCLK When multiple CPU DAIs on the same sound card share the same physical BCLK, add a hw_rule during PCM open that constrains the sample rate so diff --git a/SPECS/linux-lts/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch b/SPECS/linux-lts/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch index df88e6dc93..ff936b2c7c 100644 --- a/SPECS/linux-lts/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch +++ b/SPECS/linux-lts/0371-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch @@ -1,7 +1,7 @@ -From 87485a6e8c2da82863181097d7d37ba1ebc90eb9 Mon Sep 17 00:00:00 2001 +From ab006e609e125b2253d6016108a7ac52e642a192 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 7 May 2026 18:31:44 +0800 -Subject: [PATCH 371/467] FROMLIST: ASoC: spacemit: declare shared BCLK for +Subject: [RUYI PATCH] FROMLIST: ASoC: spacemit: declare shared BCLK for cross-DAI rate constraint On SpacemiT K3, multiple I2S controllers share the same physical BCLK diff --git a/SPECS/linux-lts/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch b/SPECS/linux-lts/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch index 54669c5f23..26e3e584c6 100644 --- a/SPECS/linux-lts/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch +++ b/SPECS/linux-lts/0372-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch @@ -1,8 +1,8 @@ -From ff1bd9de50fd99b0b63391ed7079a66e92f5fb02 Mon Sep 17 00:00:00 2001 +From fd1098639a4174a54cfc40a6fe40bbcb9569aee6 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Tue, 5 May 2026 09:53:34 -0400 -Subject: [PATCH 372/467] FROMLIST: spi: spacemit: add u64 cast to NSEC_PER_SEC - to avoid 32-bit overflow +Subject: [RUYI PATCH] FROMLIST: spi: spacemit: add u64 cast to NSEC_PER_SEC to + avoid 32-bit overflow NSEC_PER_SEC expands to the long constant 1000000000L, so NSEC_PER_SEC * BITS_PER_BYTE (8 * 10^9) overflows on 32-bit-long architectures diff --git a/SPECS/linux-lts/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch b/SPECS/linux-lts/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch index 06e80d2111..1ec5840379 100644 --- a/SPECS/linux-lts/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch +++ b/SPECS/linux-lts/0373-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch @@ -1,7 +1,7 @@ -From eb891952a841254f3564aa2b534dd235469daaa5 Mon Sep 17 00:00:00 2001 +From 70157c501907a5cde732fdf89f3f458d3aba2959 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:16:59 +0800 -Subject: [PATCH 373/467] FROMLIST: dt-bindings: clock: thead: add TH1520 MISC +Subject: [RUYI PATCH] FROMLIST: dt-bindings: clock: thead: add TH1520 MISC subsys clock controller TH1520 has a subsystem clock controller called MISC_SUBSYS in its diff --git a/SPECS/linux-lts/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch b/SPECS/linux-lts/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch index 381e497d96..4e7272cafb 100644 --- a/SPECS/linux-lts/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch +++ b/SPECS/linux-lts/0374-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch @@ -1,7 +1,7 @@ -From beef94a59a428c2ee10412cd8414e2f4022aa76c Mon Sep 17 00:00:00 2001 +From ff7baa8d99b3acfa161a96f9d572688e8fbfb14f Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:00 +0800 -Subject: [PATCH 374/467] FROMLIST: clk: thead: th1520-ap: add support for MISC +Subject: [RUYI PATCH] FROMLIST: clk: thead: th1520-ap: add support for MISC subsys clocks The TH1520 SoC contains a MISC_SUBSYS clock controller, which allows diff --git a/SPECS/linux-lts/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch b/SPECS/linux-lts/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch index dc3399e4cb..5712f59936 100644 --- a/SPECS/linux-lts/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch +++ b/SPECS/linux-lts/0375-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch @@ -1,7 +1,7 @@ -From 225dd81ab8f245421e354bac14e6182025c41df1 Mon Sep 17 00:00:00 2001 +From 25858e77df3fb64d1db8a210aa513630aa172761 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:01 +0800 -Subject: [PATCH 375/467] FROMLIST: riscv: dts: thead: add device tree node for +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device tree node for MISC clock controller The MISC_SUBSYS clock controller on TH1520 SoC is a clock controller diff --git a/SPECS/linux-lts/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch b/SPECS/linux-lts/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch index b7ae4ae866..d6fc48cce2 100644 --- a/SPECS/linux-lts/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch +++ b/SPECS/linux-lts/0376-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch @@ -1,7 +1,7 @@ -From 1f883f8b2aaf90f81e9cc3e07c5d07d624331025 Mon Sep 17 00:00:00 2001 +From bf1bce6b58599f811e5d960528b05a56606c6198 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:02 +0800 -Subject: [PATCH 376/467] FROMLIST: dt-bindings: phy: add binding for T-Head +Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: add binding for T-Head TH1520 USB PHY The TH1520 SoC features a Synopsys USB 3.0 FemtoPHY with some custom diff --git a/SPECS/linux-lts/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch b/SPECS/linux-lts/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch index 08e62a086f..f37bec7b80 100644 --- a/SPECS/linux-lts/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch +++ b/SPECS/linux-lts/0377-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch @@ -1,7 +1,7 @@ -From dcb5013bc09740ec69367c77d4a4947ec96f20ed Mon Sep 17 00:00:00 2001 +From 6836defb3d09054866bd4165ee60f3bcd6135b07 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:03 +0800 -Subject: [PATCH 377/467] FROMLIST: phy: add a driver for T-Head TH1520 USB PHY +Subject: [RUYI PATCH] FROMLIST: phy: add a driver for T-Head TH1520 USB PHY The USB PHY on T-Head TH1520 SoC is a Synopsys USB 3.0 FemtoPHY, with some PHY parameters exported as another system controller along with it. diff --git a/SPECS/linux-lts/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch b/SPECS/linux-lts/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch index ce28cb8915..01b5e27c73 100644 --- a/SPECS/linux-lts/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch +++ b/SPECS/linux-lts/0378-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch @@ -1,7 +1,7 @@ -From 762073e75c3906c685bc8388091a72f59d6e33f5 Mon Sep 17 00:00:00 2001 +From 2be6de531146e3cb05e762c17c5d087a15b3ad2d Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:04 +0800 -Subject: [PATCH 378/467] FROMLIST: riscv: dts: thead: add device nodes for USB +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device nodes for USB The TH1520 SoC contains a Synopsys DesignWare Cores SuperSpeed USB3.0 Dual Role Device controller in addition to a USB2+USB3 combo PHY based diff --git a/SPECS/linux-lts/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch b/SPECS/linux-lts/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch index 42750a360c..bd9aea764d 100644 --- a/SPECS/linux-lts/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch +++ b/SPECS/linux-lts/0379-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch @@ -1,7 +1,7 @@ -From 1ecd168027599967fe95397ece7faa754e5f5e39 Mon Sep 17 00:00:00 2001 +From b2708e5bb25843313bbb63f5c6417d756f0ce5e0 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:05 +0800 -Subject: [PATCH 379/467] FROMLIST: dt-bindings: gpio: dwapb: allow GPIO hogs +Subject: [RUYI PATCH] FROMLIST: dt-bindings: gpio: dwapb: allow GPIO hogs GPIO hogs are described in the gpio.txt binding as automatic default GPIO configuration items. diff --git a/SPECS/linux-lts/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch b/SPECS/linux-lts/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch index a57fbf8f5b..00f4949ecd 100644 --- a/SPECS/linux-lts/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch +++ b/SPECS/linux-lts/0380-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch @@ -1,7 +1,7 @@ -From 49426bc2f4eec81986cedeb4485276ce9681a724 Mon Sep 17 00:00:00 2001 +From d114c66e2f27fb7d5c538f14399ab98ce4960f83 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:06 +0800 -Subject: [PATCH 380/467] FROMLIST: dt-bindings: usb: vialab,vl817: allow ports +Subject: [RUYI PATCH] FROMLIST: dt-bindings: usb: vialab,vl817: allow ports property As a USB hub device, VL817 can surely be connected to external USB diff --git a/SPECS/linux-lts/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch b/SPECS/linux-lts/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch index d00e626d15..16cdfd9cbf 100644 --- a/SPECS/linux-lts/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch +++ b/SPECS/linux-lts/0381-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch @@ -1,7 +1,7 @@ -From 6dcc9b3c4294c90622f68260717fcf8f07891f3b Mon Sep 17 00:00:00 2001 +From f92fde63364be52d61f1457466f5b1697b0e9b09 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:07 +0800 -Subject: [PATCH 381/467] FROMLIST: riscv: dts: thead: lpi4a: sort nodes +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: lpi4a: sort nodes Although "D" and "H" are earlier in the alphabet than "P", the DPU and HDMI nodes were added after PADCTRL node in the Lichee Pi 4A device tree. diff --git a/SPECS/linux-lts/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch b/SPECS/linux-lts/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch index e9b32dab3d..e70fcfd352 100644 --- a/SPECS/linux-lts/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch +++ b/SPECS/linux-lts/0382-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch @@ -1,7 +1,7 @@ -From 9ce853f956a1bebf43c4053c02a67914c6fd8b50 Mon Sep 17 00:00:00 2001 +From 235225ebc673fe3cf62d79eb1936fb0ef9b3aa52 Mon Sep 17 00:00:00 2001 From: Thomas Bonnefille Date: Thu, 7 May 2026 16:17:08 +0800 -Subject: [PATCH 382/467] FROMLIST: riscv: dts: thead: Add TH1520 I2C nodes +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Add TH1520 I2C nodes Add nodes for the six I2C on the T-Head TH1520 RISCV SoC. diff --git a/SPECS/linux-lts/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch b/SPECS/linux-lts/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch index 5c45f4179f..6905dfac60 100644 --- a/SPECS/linux-lts/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch +++ b/SPECS/linux-lts/0383-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch @@ -1,7 +1,7 @@ -From b4e786b2f0c59be9a66614adc05dff50460e5292 Mon Sep 17 00:00:00 2001 +From e7621614a1d93b84b3994cc4e147e2f5f24e8b8c Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Thu, 7 May 2026 16:17:09 +0800 -Subject: [PATCH 383/467] FROMLIST: riscv: dts: thead: Add Lichee Pi 4A IO +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Add Lichee Pi 4A IO expansions Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the diff --git a/SPECS/linux-lts/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch b/SPECS/linux-lts/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch index 5fc96a0c1d..f1e49e1290 100644 --- a/SPECS/linux-lts/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch +++ b/SPECS/linux-lts/0384-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch @@ -1,8 +1,8 @@ -From e65c217e4f180a09599dcf963d7917ca8f2dce56 Mon Sep 17 00:00:00 2001 +From 0b1e399727d5ebc0f998864161be37205403f479 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 7 May 2026 16:17:10 +0800 -Subject: [PATCH 384/467] FROMLIST: riscv: dts: thead: enable USB3 ports on - Lichee Pi 4A +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: enable USB3 ports on Lichee + Pi 4A The Lichee Pi 4A board features an onboard VIA VL817 hub connected to the SoC's USB3 as upstream and 4 USB-3.0-capable Type-A ports as diff --git a/SPECS/linux-lts/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch b/SPECS/linux-lts/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch index c128317cc7..9a32cb3ce3 100644 --- a/SPECS/linux-lts/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch +++ b/SPECS/linux-lts/0385-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch @@ -1,8 +1,8 @@ -From 74fce4ca0259a2fb6f07e9a9db0da7a4b6d187ad Mon Sep 17 00:00:00 2001 +From 52e6648f05a98b5daa57d14ffbc7a8f17e0a2e70 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 11 May 2026 13:11:08 +0200 -Subject: [PATCH 385/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add - PMIC and power infrastructure +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add PMIC + and power infrastructure Enable i2c8 and add the connected SpacemiT P1 PMIC with its related regulators for the board's power infrastructure and voltage regulation support. diff --git a/SPECS/linux-lts/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch b/SPECS/linux-lts/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch index 7c213bac42..27c61ac393 100644 --- a/SPECS/linux-lts/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch +++ b/SPECS/linux-lts/0386-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch @@ -1,8 +1,8 @@ -From 46e98f453443e84d2c39d1a192493f63035cb983 Mon Sep 17 00:00:00 2001 +From 766c66afb264021498a9385a2332b05c2ab32653 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 11 May 2026 13:11:09 +0200 -Subject: [PATCH 386/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add - 24c04 eeprom +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add 24c04 + eeprom Enable i2c2 and add the connected 24c04 EEPROM. diff --git a/SPECS/linux-lts/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch b/SPECS/linux-lts/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch index 93c6f40848..bb1a850bdd 100644 --- a/SPECS/linux-lts/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch +++ b/SPECS/linux-lts/0387-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch @@ -1,7 +1,7 @@ -From 75a37f9d516eb90b20c532be235d4a9752fba6be Mon Sep 17 00:00:00 2001 +From c117a7fcd7c10d4f8235ca033fe3b09674838cc2 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 11 May 2026 13:11:10 +0200 -Subject: [PATCH 387/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable QSPI and add SPI NOR Add the QSPI controller node and describe the attached SPI NOR flash diff --git a/SPECS/linux-lts/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch b/SPECS/linux-lts/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch index aa1fefae14..e2dbb68dfc 100644 --- a/SPECS/linux-lts/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch +++ b/SPECS/linux-lts/0388-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch @@ -1,7 +1,7 @@ -From 74f565b6e699c8ec0bd9138b54c7af5f73b625e3 Mon Sep 17 00:00:00 2001 +From a94156daa45213f4dfc1d6f6cc6a3f25b4e635c1 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 11 May 2026 13:11:11 +0200 -Subject: [PATCH 388/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable USB 3 ports Enable the DWC3 USB 3.0 controller, its associated combo_phy (USB 3 PHY) diff --git a/SPECS/linux-lts/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch b/SPECS/linux-lts/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch index 4d368a61b1..23832d06b8 100644 --- a/SPECS/linux-lts/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch +++ b/SPECS/linux-lts/0389-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch @@ -1,7 +1,7 @@ -From b2f775e8f1fe4ec525455361eadc7df47250a44b Mon Sep 17 00:00:00 2001 +From 349e55f2df85d45315a64261930482121af299e5 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 11 May 2026 13:11:12 +0200 -Subject: [PATCH 389/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable PCIe ports Enable the two PCIe controller along with and their associated PHYs. They diff --git a/SPECS/linux-lts/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch b/SPECS/linux-lts/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch index ee53b03556..2a721e03c5 100644 --- a/SPECS/linux-lts/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch +++ b/SPECS/linux-lts/0390-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch @@ -1,7 +1,7 @@ -From d3e09b27f344f7b9353cf66a5884e1eaa20cc2d9 Mon Sep 17 00:00:00 2001 +From 9a43c78660975e06c30cbaf943e981dd50feee99 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Mon, 11 May 2026 13:11:13 +0200 -Subject: [PATCH 390/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: set +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: set default console baud rate Allow serial output with the same uboot/opensbi settings so the diff --git a/SPECS/linux-lts/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch b/SPECS/linux-lts/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch index 5e1bb550cd..e480697ecf 100644 --- a/SPECS/linux-lts/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch +++ b/SPECS/linux-lts/0391-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch @@ -1,7 +1,7 @@ -From 17640c2f952d4636e28f6c91c28cad7c0cbcfeb5 Mon Sep 17 00:00:00 2001 +From 19e0459a70fb9e1c62f2eb097e72e73136997ccd Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 21 May 2026 00:24:41 +0000 -Subject: [PATCH 391/467] FROMLIST: riscv: dts: spacemit: k3: Add pwm support +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add pwm support Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents the pinctrl info which would easily help to enable them in future. diff --git a/SPECS/linux-lts/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch b/SPECS/linux-lts/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch index ded1d721e2..dfea8b63a1 100644 --- a/SPECS/linux-lts/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch +++ b/SPECS/linux-lts/0392-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch @@ -1,8 +1,7 @@ -From 8a3c697d67f26e7001badacbe651347af98734fc Mon Sep 17 00:00:00 2001 +From 990e07e7b25d9ad6863585a17875fd32e9b194ed Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Sun, 10 May 2026 18:54:21 +0200 -Subject: [PATCH 392/467] FROMLIST: riscv: use sysfs_emit in - cpu_show_ghostwrite +Subject: [RUYI PATCH] FROMLIST: riscv: use sysfs_emit in cpu_show_ghostwrite Replace sprintf() with sysfs_emit() in cpu_show_ghostwrite(), which is preferred for formatting sysfs output because it provides safer bounds diff --git a/SPECS/linux-lts/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch b/SPECS/linux-lts/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch index 0f04216c5b..61c699fb6b 100644 --- a/SPECS/linux-lts/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch +++ b/SPECS/linux-lts/0393-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch @@ -1,8 +1,8 @@ -From 5a543b79cba1602b35c7bf4c272f6c1082403ec9 Mon Sep 17 00:00:00 2001 +From 5feeaceeac1d83b0bc4b52a476972edb0633b9b1 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 11 May 2026 02:59:09 +0000 -Subject: [PATCH 393/467] FROMLIST: clk: spacemit: k3: Switch to pll2_d6 as - parent for PCIe clock +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Switch to pll2_d6 as parent + for PCIe clock According to SpacemiT updated docs, the PCIe master and slave clock's parent is the pll2_d6 clock, so fix it. diff --git a/SPECS/linux-lts/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch b/SPECS/linux-lts/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch index 1709d97c4d..cec142274b 100644 --- a/SPECS/linux-lts/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch +++ b/SPECS/linux-lts/0394-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch @@ -1,7 +1,7 @@ -From e8eb8752ce8b21f83609892d2702ada2791d6878 Mon Sep 17 00:00:00 2001 +From e7889702a01dfeefc13f75527701150067033d27 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 11 May 2026 02:59:10 +0000 -Subject: [PATCH 394/467] FROMLIST: clk: spacemit: k3: Fix PCIe clock register +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Fix PCIe clock register offset The offset of PCIe Clock CTRL register for port B and C controller was diff --git a/SPECS/linux-lts/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch b/SPECS/linux-lts/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch index 40b18595f7..8c7de819c6 100644 --- a/SPECS/linux-lts/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch +++ b/SPECS/linux-lts/0395-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch @@ -1,8 +1,8 @@ -From 71cbe41aa3e3af9d8f5d8e6ecd78f702cebb6de4 Mon Sep 17 00:00:00 2001 +From 81e7dee63c57fbbbf525e3b3e475ac4463f4be56 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 11 May 2026 02:59:11 +0000 -Subject: [PATCH 395/467] FROMLIST: dt-bindings: soc: spacemit: k3: Add PCIe - DBI clock IDs +Subject: [RUYI PATCH] FROMLIST: dt-bindings: soc: spacemit: k3: Add PCIe DBI + clock IDs Add clock IDs of PCIe DBI (Data Bus Interface) clock. diff --git a/SPECS/linux-lts/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch b/SPECS/linux-lts/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch index 77b2c6bba2..b1757a1b9e 100644 --- a/SPECS/linux-lts/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch +++ b/SPECS/linux-lts/0396-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch @@ -1,7 +1,7 @@ -From f93186e43511bbaed54be71b65d9a4479244fd07 Mon Sep 17 00:00:00 2001 +From 2e07351b454e444fdff46836d26d0ca8f0f1d241 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 11 May 2026 02:59:12 +0000 -Subject: [PATCH 396/467] FROMLIST: clk: spacemit: k3: Add PCIe DBI clock +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Add PCIe DBI clock Add PCIe DBI (Data Bus Interface) clock which was missing, This will support PCIe driver to explicitly request and enable all clocks that diff --git a/SPECS/linux-lts/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch b/SPECS/linux-lts/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch index 498e072354..3c8f831c46 100644 --- a/SPECS/linux-lts/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch +++ b/SPECS/linux-lts/0397-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch @@ -1,8 +1,8 @@ -From 6ff2a06cb85f689598ffa5ccd38fc8fe6b494f5f Mon Sep 17 00:00:00 2001 +From 1e42639469619e69ed0fe533281513ebbf8fb45f Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 9 May 2026 18:00:00 +0800 -Subject: [PATCH 397/467] FROMLIST: riscv: dts: spacemit: enable eMMC for - OrangePi RV2 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable eMMC for OrangePi + RV2 The OrangePi RV2 board has one eMMC slot, so enable eMMC. Tested using a 16 GiB AJTD4R eMMC module. diff --git a/SPECS/linux-lts/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch b/SPECS/linux-lts/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch index e24ba9833d..f786ba93a4 100644 --- a/SPECS/linux-lts/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch +++ b/SPECS/linux-lts/0398-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch @@ -1,7 +1,7 @@ -From 1dffaef4daca33ae971decf2ae555fde6d43ccd1 Mon Sep 17 00:00:00 2001 +From 952ad4c278b4a099d4fbcabc3b23304339f3277a Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 8 May 2026 15:25:24 +0800 -Subject: [PATCH 398/467] FROMLIST: i2c: spacemit: configure ILCR/IWCR for +Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: configure ILCR/IWCR for accurate SCL frequency The SpacemiT I2C controller's SCL (Serial Clock Line) frequency for diff --git a/SPECS/linux-lts/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch b/SPECS/linux-lts/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch index ca4e9fec31..7e3a638bb7 100644 --- a/SPECS/linux-lts/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch +++ b/SPECS/linux-lts/0399-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch @@ -1,7 +1,7 @@ -From dbd9d83cae62b43735c4ed79553380f3d33cf666 Mon Sep 17 00:00:00 2001 +From 362a9bc03d8080d38e5ea64ba2c39884e945e945 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 8 May 2026 15:25:25 +0800 -Subject: [PATCH 399/467] FROMLIST: i2c: spacemit: drop warning when +Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: drop warning when clock-frequency property is absent The clock-frequency property is optional according to the DT binding. diff --git a/SPECS/linux-lts/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch b/SPECS/linux-lts/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch index 62f24cc91b..837fc9207b 100644 --- a/SPECS/linux-lts/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch +++ b/SPECS/linux-lts/0400-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch @@ -1,8 +1,8 @@ -From d7f231111494d8c2ec36cad45aabe28d70c55167 Mon Sep 17 00:00:00 2001 +From 56ba1d8c335d661163b9d3b1d870a9e07dd575cc Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Mon, 11 May 2026 10:53:56 +0200 -Subject: [PATCH 400/467] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add - pinctrl support for voltage switching +Subject: [RUYI PATCH] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add pinctrl + support for voltage switching Document pinctrl properties to support voltage-dependent pin configuration switching for UHS-I SD card modes. diff --git a/SPECS/linux-lts/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch b/SPECS/linux-lts/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch index f52dc6e418..5583dc6077 100644 --- a/SPECS/linux-lts/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch +++ b/SPECS/linux-lts/0401-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch @@ -1,7 +1,7 @@ -From 59062924d61974dd50fb52db1a6267bdd0e9caa5 Mon Sep 17 00:00:00 2001 +From a164c67f524d96eea999938772b0e7664cf8432d Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Mon, 11 May 2026 10:53:57 +0200 -Subject: [PATCH 401/467] FROMLIST: mmc: sdhci-of-k1: enable essential clock +Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: enable essential clock infrastructure for SD operation Ensure SD card pins receive clock signals by enabling pad clock diff --git a/SPECS/linux-lts/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch b/SPECS/linux-lts/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch index 98058cb5ec..d77d4b7d8e 100644 --- a/SPECS/linux-lts/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch +++ b/SPECS/linux-lts/0402-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch @@ -1,7 +1,7 @@ -From 6bff1487d38af8eca2467da0d9f7b7e22ef8941d Mon Sep 17 00:00:00 2001 +From 7104b26621a3b8b7a0f213f846d4e94f40cbd6ef Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Mon, 11 May 2026 10:53:58 +0200 -Subject: [PATCH 402/467] FROMLIST: mmc: sdhci-of-k1: add regulator and pinctrl +Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: add regulator and pinctrl voltage switching support Add voltage switching infrastructure for UHS-I modes by integrating both diff --git a/SPECS/linux-lts/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch b/SPECS/linux-lts/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch index 763c405e53..a431dd69fd 100644 --- a/SPECS/linux-lts/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch +++ b/SPECS/linux-lts/0403-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch @@ -1,8 +1,8 @@ -From 7a0c2f9d8bc3d427aff7d62359f74e8a21ecb98f Mon Sep 17 00:00:00 2001 +From 88c16045a194f9da4ac3d1e41104c2bc67bef52f Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Mon, 11 May 2026 10:53:59 +0200 -Subject: [PATCH 403/467] FROMLIST: mmc: sdhci-of-k1: add comprehensive SDR - tuning support +Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: add comprehensive SDR tuning + support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux-lts/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch b/SPECS/linux-lts/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch index 0efaca8eaf..acee11c137 100644 --- a/SPECS/linux-lts/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch +++ b/SPECS/linux-lts/0404-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch @@ -1,7 +1,7 @@ -From 81aae30b2ea47630a098bc16822c4b8ce486f96b Mon Sep 17 00:00:00 2001 +From c7ea3695cea289291e871b1d5ee24585b4b969ad Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Fri, 15 May 2026 12:48:59 +0200 -Subject: [PATCH 404/467] FROMLIST: riscv: dts: spacemit: k1: add SD card +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1: add SD card controller and pinctrl support Add SD card controller infrastructure for SpacemiT K1 SoC with complete diff --git a/SPECS/linux-lts/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch b/SPECS/linux-lts/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch index fb0555d636..ba6141397e 100644 --- a/SPECS/linux-lts/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch +++ b/SPECS/linux-lts/0405-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch @@ -1,8 +1,8 @@ -From 0d69badbae2aa8cfd8dceca3cf87987d79f9a61e Mon Sep 17 00:00:00 2001 +From 43968e62edda768281d634a038212b96befc49e5 Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Fri, 15 May 2026 12:49:00 +0200 -Subject: [PATCH 405/467] FROMLIST: riscv: dts: spacemit: k1-orangepi-rv2: add - SD card support with UHS modes +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-orangepi-rv2: add SD + card support with UHS modes Add complete SD card controller support with UHS high-speed modes. diff --git a/SPECS/linux-lts/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch b/SPECS/linux-lts/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch index 76ff2fbb1d..5173364a60 100644 --- a/SPECS/linux-lts/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch +++ b/SPECS/linux-lts/0406-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch @@ -1,8 +1,8 @@ -From f2d8d59f6d99fa77ef4d8ba4fd987daeff28eab5 Mon Sep 17 00:00:00 2001 +From 139e0716fdfe2ce733d52f88221f1b6727235cf7 Mon Sep 17 00:00:00 2001 From: Iker Pedrosa Date: Fri, 15 May 2026 12:49:01 +0200 -Subject: [PATCH 406/467] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: add - SD card support with UHS modes +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: add SD + card support with UHS modes Add complete SD card controller support with UHS high-speed modes. diff --git a/SPECS/linux-lts/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch b/SPECS/linux-lts/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch index 998c64454d..fc44499a76 100644 --- a/SPECS/linux-lts/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch +++ b/SPECS/linux-lts/0407-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch @@ -1,7 +1,7 @@ -From f96189263aef32389c97389eb3235827e96b5a5d Mon Sep 17 00:00:00 2001 +From 25997e10bcbb4842cd8f7f69db1754a807b4515b Mon Sep 17 00:00:00 2001 From: Trevor Gamblin Date: Fri, 15 May 2026 12:49:02 +0200 -Subject: [PATCH 407/467] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add SD +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add SD card support with UHS modes Update the Muse Pi Pro devicetree with SD card support to match what diff --git a/SPECS/linux-lts/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch b/SPECS/linux-lts/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch index 4a176d39a7..5f154ddf37 100644 --- a/SPECS/linux-lts/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch +++ b/SPECS/linux-lts/0408-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch @@ -1,7 +1,7 @@ -From a366a6ddd2d146abfc8ac12c6d57701a94a7c725 Mon Sep 17 00:00:00 2001 +From 30f59c0f689a00390e4183a7b58ec3108d1d55a8 Mon Sep 17 00:00:00 2001 From: Thomas Gerner Date: Thu, 14 May 2026 20:32:01 +0200 -Subject: [PATCH 408/467] FROMLIST: riscv: dts: thead: Enable wifi on the +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Enable wifi on the BeagleV-Ahead The BeagleV-Ahead board uses an AP6203BM WiFi chip from AMPAK Technology diff --git a/SPECS/linux-lts/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch b/SPECS/linux-lts/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch index 52300d9fdd..d8e8c34faf 100644 --- a/SPECS/linux-lts/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch +++ b/SPECS/linux-lts/0409-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch @@ -1,8 +1,8 @@ -From 5eb58bc515879ba41b74f3e37a8bdc20196e4ed0 Mon Sep 17 00:00:00 2001 +From d02e702da21996ccb557b91e5cb594f6c76e0025 Mon Sep 17 00:00:00 2001 From: Florian Schmaus Date: Tue, 12 May 2026 08:32:31 +0200 -Subject: [PATCH 409/467] FROMLIST: riscv: module: Use generic cmp_int() - instead of custom cmp_3way() +Subject: [RUYI PATCH] FROMLIST: riscv: module: Use generic cmp_int() instead + of custom cmp_3way() The module-sections.c file defines a custom cmp_3way() macro to perform 3-way comparisons during relocation sorting. diff --git a/SPECS/linux-lts/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch b/SPECS/linux-lts/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch index 78445b0fd9..616724be18 100644 --- a/SPECS/linux-lts/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch +++ b/SPECS/linux-lts/0410-FROMLIST-riscv-propagate-insert_resource-result-from.patch @@ -1,8 +1,8 @@ -From 2cba62c648b6d8eaad866c02dec48f863e787414 Mon Sep 17 00:00:00 2001 +From 41705cbe35101c7de961fb93f3c0d01b4f424bd3 Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Tue, 12 May 2026 19:20:35 +0200 -Subject: [PATCH 410/467] FROMLIST: riscv: propagate insert_resource result - from add_resource +Subject: [RUYI PATCH] FROMLIST: riscv: propagate insert_resource result from + add_resource Currently, add_resource() returns 1 on success, even though its callers only check for negative values. Instead, propagate the insert_resource() diff --git a/SPECS/linux-lts/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch b/SPECS/linux-lts/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch index 43182331d6..d8ae0df53d 100644 --- a/SPECS/linux-lts/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch +++ b/SPECS/linux-lts/0411-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch @@ -1,7 +1,7 @@ -From 42583ca7d256f65f3ea896a2719f5e5a76a3ab57 Mon Sep 17 00:00:00 2001 +From a380dc5ba876575445cbffdd6abae226725a9fce Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 17 May 2026 09:48:36 +0800 -Subject: [PATCH 411/467] FROMLIST: PCI: spacemit-k1: Add device data support +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add device data support To reuse the K1 PCIe driver logic for K3 PCIe controller, add device data to handle the K1 specific logic and make room for the incoming diff --git a/SPECS/linux-lts/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch b/SPECS/linux-lts/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch index c7cc73fe1f..b4cf2fd137 100644 --- a/SPECS/linux-lts/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch +++ b/SPECS/linux-lts/0412-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch @@ -1,7 +1,7 @@ -From 641cdd56986dd7dd9d5ffec8b4a316e528313390 Mon Sep 17 00:00:00 2001 +From 291d83131cb1a80661bf10272be1b0aab99fb39d Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 17 May 2026 09:48:37 +0800 -Subject: [PATCH 412/467] FROMLIST: PCI: spacemit-k1: Add multiple PHY handles +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add multiple PHY handles support The PCIe controller on Spacemit K3 may use multiple PHYs at the diff --git a/SPECS/linux-lts/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch b/SPECS/linux-lts/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch index e8c8226d5d..d0085e05ec 100644 --- a/SPECS/linux-lts/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch +++ b/SPECS/linux-lts/0413-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch @@ -1,8 +1,8 @@ -From ff7b3a40f58430d7040609bb6beb23f080eb3bec Mon Sep 17 00:00:00 2001 +From e1caa735029246df2abdcf416ccc274ca3ff53d5 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 17 May 2026 09:48:38 +0800 -Subject: [PATCH 413/467] FROMLIST: dt-bindings: PCI: snps,dw-pcie: Add - msi-parent for MSI handle check +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: snps,dw-pcie: Add msi-parent + for MSI handle check The IMSIC device on RISC-V based system does not require ID remapping for MSI. So this device only needs "msi-parent" diff --git a/SPECS/linux-lts/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch b/SPECS/linux-lts/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch index a9f880b0b2..ce7568b3bb 100644 --- a/SPECS/linux-lts/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch +++ b/SPECS/linux-lts/0414-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch @@ -1,8 +1,8 @@ -From b71db7acd338b565ebfa25fdafffccc306c3f667 Mon Sep 17 00:00:00 2001 +From f9aab33c4cd724380b176901c11e9b2d5dbe7b6f Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 17 May 2026 09:48:39 +0800 -Subject: [PATCH 414/467] FROMLIST: dt-bindings: PCI: spacemit: Introduce - Spacemit K3 PCIe host controller +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: spacemit: Introduce Spacemit + K3 PCIe host controller Add binding support for the PCIe controller on the SpacemiT K3 SoC. This controller is almost a standard Synopsys DesignWare PCIe IP, diff --git a/SPECS/linux-lts/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch b/SPECS/linux-lts/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch index 94610a7b9a..66e63181b2 100644 --- a/SPECS/linux-lts/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch +++ b/SPECS/linux-lts/0415-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch @@ -1,7 +1,7 @@ -From 099bfd3e55205ace595ca828ce5afae419eefaf7 Mon Sep 17 00:00:00 2001 +From 28a3c6b229dbe4b76f568ab83a3d0405809c7f1b Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 17 May 2026 09:48:40 +0800 -Subject: [PATCH 415/467] FROMLIST: PCI: spacemit-k1: Add Spacemit K3 PCIe host +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add Spacemit K3 PCIe host controller support The PCIe controller on Spacemit K3 is almost a standard Synopsys diff --git a/SPECS/linux-lts/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch b/SPECS/linux-lts/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch index 416a37403f..80bd621ef2 100644 --- a/SPECS/linux-lts/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch +++ b/SPECS/linux-lts/0416-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch @@ -1,8 +1,8 @@ -From 2d3f6de67eb533903d80677a6a462979c87143b9 Mon Sep 17 00:00:00 2001 +From e933fb1426b50978196a70b05655d5cb7a3bcb76 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 16 May 2026 16:00:30 +0800 -Subject: [PATCH 416/467] FROMLIST: riscv: dts: spacemit: enable QSPI for - OrangePi RV2 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable QSPI for OrangePi + RV2 Enable the QSPI controller and the XM25QU128C SPI NOR flash on the OrangePi RV2 board. Add a flash partition layout from vendor UBoot. diff --git a/SPECS/linux-lts/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch b/SPECS/linux-lts/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch index c6980ac2dd..7ce6604711 100644 --- a/SPECS/linux-lts/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch +++ b/SPECS/linux-lts/0417-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch @@ -1,7 +1,7 @@ -From c77834df77a830ed52e78558f67b5e02fa4379f9 Mon Sep 17 00:00:00 2001 +From 9ffbd34c853c426d82f3daf0bb7512fc1b08d611 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 18 May 2026 02:58:36 +0000 -Subject: [PATCH 417/467] FROMLIST: clk: spacemit: k3: fix USB2 bus clock +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix USB2 bus clock According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus clock enable bit was wrongly swapped, the correct one should be: diff --git a/SPECS/linux-lts/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch b/SPECS/linux-lts/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch index 350548f91c..ef6c5cfcb2 100644 --- a/SPECS/linux-lts/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch +++ b/SPECS/linux-lts/0418-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch @@ -1,7 +1,7 @@ -From a9788cf9dae7cfe18b553bd1ae42afe7ef003b45 Mon Sep 17 00:00:00 2001 +From d420aa127fcbe63635453a4103d4d013e9027703 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 18 May 2026 02:58:37 +0000 -Subject: [PATCH 418/467] FROMLIST: reset: spacemit: k3: fix USB2 ahb reset +Subject: [RUYI PATCH] FROMLIST: reset: spacemit: k3: fix USB2 ahb reset According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus clock enable bit was wrongly swapped, the correct one should be: diff --git a/SPECS/linux-lts/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch b/SPECS/linux-lts/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch index 48fdd3cc67..05b9ee6eb7 100644 --- a/SPECS/linux-lts/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch +++ b/SPECS/linux-lts/0419-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch @@ -1,7 +1,7 @@ -From 4224b1f1d490ae209fbb371252179c523d1733f9 Mon Sep 17 00:00:00 2001 +From cf3c64c0e469dac06db3606b299ff2b6be12345c Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 18 May 2026 20:58:16 +0000 -Subject: [PATCH 419/467] FROMLIST: dts: riscv: spacemit: k3: Fix I/O power +Subject: [RUYI PATCH] FROMLIST: dts: riscv: spacemit: k3: Fix I/O power settings SpacemiT K3 SoC support dual-voltage I/O power domain, while initially diff --git a/SPECS/linux-lts/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch index 65aa7a68b9..5640477b61 100644 --- a/SPECS/linux-lts/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch +++ b/SPECS/linux-lts/0420-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch @@ -1,8 +1,8 @@ -From ad3f20a31772c6ad7ebc8fa7c75029764a774a46 Mon Sep 17 00:00:00 2001 +From 24e92b2f714ec09b1217533e18d18a7a1416d52f Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:35 +0200 -Subject: [PATCH 420/467] FROMLIST: riscv: dts: spacemit: set console baud rate - on Milk-V Jupiter +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on + Milk-V Jupiter Because the default console's baud rate is not set, defconfig kernels do not have any serial output on this platform. Set the baud rate to diff --git a/SPECS/linux-lts/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch b/SPECS/linux-lts/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch index 6e6cedf534..f35dbf7a0b 100644 --- a/SPECS/linux-lts/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch +++ b/SPECS/linux-lts/0421-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch @@ -1,8 +1,8 @@ -From 430637bb4afb74146c8c8829d0da513b6bd4c91e Mon Sep 17 00:00:00 2001 +From 8422624a96d6035950f1902cc537f1e7d2a4c281 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:36 +0200 -Subject: [PATCH 421/467] FROMLIST: riscv: dts: spacemit: sort aliases on - Milk-V Jupiter +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: sort aliases on Milk-V + Jupiter Before adding more aliases, just sort them. diff --git a/SPECS/linux-lts/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch b/SPECS/linux-lts/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch index 2dba11e059..ebf0663617 100644 --- a/SPECS/linux-lts/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch +++ b/SPECS/linux-lts/0422-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch @@ -1,7 +1,7 @@ -From 5128b77b7248e5ff6e789388a31e1d4980db9625 Mon Sep 17 00:00:00 2001 +From 72311926929a84047a95c07cdcaf0f7211764d88 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:37 +0200 -Subject: [PATCH 422/467] FROMLIST: riscv: dts: spacemit: enable eMMC on Milk-V +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable eMMC on Milk-V Jupiter The Milk-V Jupiter board has a connector for an eMMC module. Add an diff --git a/SPECS/linux-lts/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch b/SPECS/linux-lts/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch index 8563b02bad..7b0fee89d3 100644 --- a/SPECS/linux-lts/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch +++ b/SPECS/linux-lts/0423-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch @@ -1,8 +1,8 @@ -From e4c393d2cacfe99846fc5b646d0e38cbe35f4d0b Mon Sep 17 00:00:00 2001 +From 629f9f3c4e0f9cca344b52a02ceedd2e91ab9756 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:38 +0200 -Subject: [PATCH 423/467] FROMLIST: riscv: dts: spacemit: enable SD card - support on Milk-V Jupiter +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable SD card support + on Milk-V Jupiter Add complete SD card controller support with UHS high-speed modes. diff --git a/SPECS/linux-lts/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch b/SPECS/linux-lts/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch index b8e8229208..c52a677920 100644 --- a/SPECS/linux-lts/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch +++ b/SPECS/linux-lts/0424-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch @@ -1,7 +1,7 @@ -From 9b3916fc9b9300620706c675eef564914105dc63 Mon Sep 17 00:00:00 2001 +From 396d9a81ca85057f4a8bc7ad711b684dcffafb06 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 19 May 2026 06:12:39 +0200 -Subject: [PATCH 424/467] FROMLIST: riscv: dts: spacemit: fix uboot partition +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: fix uboot partition offset on Milk-V Jupiter Correct the uboot partition node name to match its actual offset. diff --git a/SPECS/linux-lts/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch b/SPECS/linux-lts/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch index 67c3e016f4..3cee4760cd 100644 --- a/SPECS/linux-lts/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch +++ b/SPECS/linux-lts/0425-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch @@ -1,8 +1,8 @@ -From 79d41f5abc296c99b6a3b3418eb3600e2082a9e3 Mon Sep 17 00:00:00 2001 +From 98c6ddea13512cec403705f0e1898daa262466b1 Mon Sep 17 00:00:00 2001 From: Zhengyu He Date: Thu, 21 May 2026 22:44:46 +0800 -Subject: [PATCH 425/467] FROMLIST: riscv: dts: spacemit: add QSPI support for - K3 Pico-ITX +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: add QSPI support for K3 + Pico-ITX Add K3 QSPI controller node into k3.dtsi, and add related pinmux configuration. diff --git a/SPECS/linux-lts/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch b/SPECS/linux-lts/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch index e4ca4afdfc..2df47fbbeb 100644 --- a/SPECS/linux-lts/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch +++ b/SPECS/linux-lts/0426-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch @@ -1,7 +1,7 @@ -From f8132c56be19ef8420d61eee66dc7352ecdd3ded Mon Sep 17 00:00:00 2001 +From 4188a3bf42259d212c5d61101e694a2dc05e3dd4 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 20 May 2026 00:40:07 +0800 -Subject: [PATCH 426/467] FROMLIST: pinctrl: spacemit: fix NULL check in +Subject: [RUYI PATCH] FROMLIST: pinctrl: spacemit: fix NULL check in spacemit_pin_set_config spacemit_pin_set_config() looks up the per-pin descriptor with diff --git a/SPECS/linux-lts/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch b/SPECS/linux-lts/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch index 02c7c4c58f..950680a506 100644 --- a/SPECS/linux-lts/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch +++ b/SPECS/linux-lts/0427-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch @@ -1,7 +1,7 @@ -From 9255f275eddde413b57b043618f6838db76a010c Mon Sep 17 00:00:00 2001 +From 2e0cced73e82d39a2fd99776f4972c20778cd27b Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 20 May 2026 00:55:46 +0800 -Subject: [PATCH 427/467] FROMLIST: riscv: unconditionally select +Subject: [RUYI PATCH] FROMLIST: riscv: unconditionally select ARCH_KEEP_MEMBLOCK Select ARCH_KEEP_MEMBLOCK unconditionally. kexec requires memblock diff --git a/SPECS/linux-lts/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch b/SPECS/linux-lts/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch index 309e71bdd7..c4ff341f5d 100644 --- a/SPECS/linux-lts/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch +++ b/SPECS/linux-lts/0428-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch @@ -1,8 +1,8 @@ -From 20deb98d0307212f2ae260f532f5c40944d5cfd4 Mon Sep 17 00:00:00 2001 +From 3c28d26c50aa548e866a1681ca068993386a91c3 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 20 May 2026 01:06:41 +0800 -Subject: [PATCH 428/467] FROMLIST: riscv: kexec_file: Constrain segment - placement to direct map +Subject: [RUYI PATCH] FROMLIST: riscv: kexec_file: Constrain segment placement + to direct map When kexec_file_load places segments with buf_max=ULONG_MAX and top_down=true, they land at the highest available physical addresses. diff --git a/SPECS/linux-lts/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch b/SPECS/linux-lts/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch index 970ceb6e88..35f6ab7227 100644 --- a/SPECS/linux-lts/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch +++ b/SPECS/linux-lts/0429-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch @@ -1,7 +1,7 @@ -From f0bf64c6e64658862d7fd2f298df04c873197db3 Mon Sep 17 00:00:00 2001 +From 66203a4e0eefa5812e80d8953dd2e958bbeaa89b Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 20 May 2026 23:45:27 +0000 -Subject: [PATCH 429/467] FROMLIST: dt-bindings: riscv: spacemit: Add K3 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: riscv: spacemit: Add K3 CoM260-IFX board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 diff --git a/SPECS/linux-lts/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch b/SPECS/linux-lts/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch index 2679db01b7..30fcfb32cb 100644 --- a/SPECS/linux-lts/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch +++ b/SPECS/linux-lts/0430-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch @@ -1,8 +1,8 @@ -From c7390a2a3f64b04ffd7c0a83d5e8e49be1607158 Mon Sep 17 00:00:00 2001 +From 204ddf86a80e19378811ebf324fd4e8474fa0834 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 20 May 2026 23:45:28 +0000 -Subject: [PATCH 430/467] FROMLIST: riscv: dts: spacemit: k3: Initial support - for CoM260-IFX board +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Initial support for + CoM260-IFX board The K3 CoM260-IFX board combine with one 260 pins "Gold Finger" computer module with a carrier board. The module integrates the K3 SoC, LPDDR5, diff --git a/SPECS/linux-lts/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch b/SPECS/linux-lts/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch index e7f194e629..70f7cc89e9 100644 --- a/SPECS/linux-lts/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch +++ b/SPECS/linux-lts/0431-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch @@ -1,8 +1,8 @@ -From d2737c5027f8388399e5428feeb50be212faf26b Mon Sep 17 00:00:00 2001 +From 78d249e0f67dafbf778883d6990fcb4c34638969 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 20 May 2026 18:00:00 +0800 -Subject: [PATCH 431/467] FROMLIST: riscv: dts: spacemit: enable PMIC on - OrangePi R2S +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable PMIC on OrangePi + R2S Enable the i2c8 interface and add the connected SpacemiT P1 PMIC and its associated regulators to support voltage regulation on the board. diff --git a/SPECS/linux-lts/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux-lts/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch index 1717fb80dd..5e9e4db788 100644 --- a/SPECS/linux-lts/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch +++ b/SPECS/linux-lts/0432-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch @@ -1,8 +1,8 @@ -From db15fe493d454f8d6639f751b051418ca4ffa796 Mon Sep 17 00:00:00 2001 +From 6aa02cc299f6c36d323e193ab8c1f6118e33d3f9 Mon Sep 17 00:00:00 2001 From: Jennifer Berringer Date: Wed, 20 May 2026 07:11:50 -0400 -Subject: [PATCH 432/467] FROMLIST: riscv: dts: spacemit: set console baud rate - on OrangePi RV2 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on + OrangePi RV2 Set the baud rate to 115200, matching what is used by U-Boot on this platform so that the console is usable even when console options are not diff --git a/SPECS/linux-lts/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch b/SPECS/linux-lts/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch index 19747d8e29..cd9e99e6c3 100644 --- a/SPECS/linux-lts/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch +++ b/SPECS/linux-lts/0433-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch @@ -1,7 +1,7 @@ -From e61fb83553f88a67832eb605add845486af0407c Mon Sep 17 00:00:00 2001 +From 82b7ff76828e1cb4e0a7b4cf12583f33f99e37bc Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Mon, 25 May 2026 12:23:29 +0800 -Subject: [PATCH 433/467] FROMLIST: riscv: mm: Call mark_new_valid_map() after +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Call mark_new_valid_map() after hotplugging vmemmap section_activate() creates new mappings in the vmemmap range without diff --git a/SPECS/linux-lts/0434-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch b/SPECS/linux-lts/0434-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch new file mode 100644 index 0000000000..de078902a8 --- /dev/null +++ b/SPECS/linux-lts/0434-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch @@ -0,0 +1,99 @@ +From 39f4f9ff2f7384331b347a162c95587733dbc042 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 26 May 2026 15:22:58 -0400 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add Ziccrse + extension for X100 cores + +Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse +provides a forward progress guarantee on LR/SC sequences in main +memory regions with cacheability and coherence PMAs. + +The SpacemiT X100 core supports it per the SpacemiT K3 hardware +specification. + +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260526-k3-ziccrse-v1-1-c759792ca3a3@riscstar.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 5b17612fe58e..ed046714a7ac 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -36,7 +36,7 @@ cpu_0: cpu@0 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -77,7 +77,7 @@ cpu_1: cpu@1 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -118,7 +118,7 @@ cpu_2: cpu@2 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -159,7 +159,7 @@ cpu_3: cpu@3 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -200,7 +200,7 @@ cpu_4: cpu@4 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -241,7 +241,7 @@ cpu_5: cpu@5 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -282,7 +282,7 @@ cpu_6: cpu@6 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -323,7 +323,7 @@ cpu_7: cpu@7 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +-- +2.53.0 + diff --git a/SPECS/linux-lts/0434-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch b/SPECS/linux-lts/0434-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch deleted file mode 100644 index 5d85c8b043..0000000000 --- a/SPECS/linux-lts/0434-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch +++ /dev/null @@ -1,50 +0,0 @@ -From f1a862c276fa513a0c9ccc9835a65f55feeb22d6 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Mon, 24 Nov 2025 20:38:44 +0800 -Subject: [PATCH 434/467] XUANTIE: riscv: dts: th1520: add licheepi4a 16g - support - -From: https://github.com/revyos/th1520-linux-kernel/commit/01a510898e41e704bee1fe58a2c0c0a29cb96548 - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/Makefile | 1 + - .../boot/dts/thead/th1520-lichee-pi-4a-16g.dts | 18 ++++++++++++++++++ - 2 files changed, 19 insertions(+) - create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts - -diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile -index b55a17127c2b..281849e71ccb 100644 ---- a/arch/riscv/boot/dts/thead/Makefile -+++ b/arch/riscv/boot/dts/thead/Makefile -@@ -1,2 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb -+dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a-16g.dtb -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts -new file mode 100644 -index 000000000000..a3a991baf716 ---- /dev/null -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts -@@ -0,0 +1,18 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2023 Han Gao -+ */ -+ -+/dts-v1/; -+ -+#include "th1520-lichee-pi-4a.dts" -+ -+/ { -+ model = "Sipeed Lichee Pi 4A 16G"; -+ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x00000000 0x4 0x00000000>; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0435-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch b/SPECS/linux-lts/0435-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch new file mode 100644 index 0000000000..3c0a31840b --- /dev/null +++ b/SPECS/linux-lts/0435-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch @@ -0,0 +1,52 @@ +From 5bf0a7bd6d1da26628096529743d98bfd1be37e1 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 28 May 2026 19:38:39 +0800 +Subject: [RUYI PATCH] FROMLIST: RISC-V: KVM: Enhance the logging check for mmu + mapping + +When enabling dirty ring, the dirty bitmap is disable, and the logging +check is always false as the RISC-V architecture does not select +"NEED_KVM_DIRTY_RING_WITH_BITMAP". Although the dirty log is recorded +since the write path already trying to add the dirty log, the logic for +logging check is broken and some side effect will occurs. + +Enhance the logging check for mmu mapping so it can check both the dirty +ring and the dirty bitmap. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260528113840.2629186-1-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/kvm/mmu.c | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c +index 58f5f3536ffd..a0d9c113258e 100644 +--- a/arch/riscv/kvm/mmu.c ++++ b/arch/riscv/kvm/mmu.c +@@ -157,9 +157,8 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, + enum kvm_mr_change change) + { + /* +- * At this point memslot has been committed and there is an +- * allocated dirty_bitmap[], dirty pages will be tracked while +- * the memory slot is write protected. ++ * At this point memslot has been committed and dirty pages will be ++ * tracked while the memory slot is write protected. + */ + if (change != KVM_MR_DELETE && new->flags & KVM_MEM_LOG_DIRTY_PAGES) + mmu_wp_memory_region(kvm, new->id); +@@ -314,8 +313,8 @@ int kvm_riscv_mmu_map(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot, + struct vm_area_struct *vma; + struct kvm *kvm = vcpu->kvm; + struct kvm_mmu_memory_cache *pcache = &vcpu->arch.mmu_page_cache; +- bool logging = (memslot->dirty_bitmap && +- !(memslot->flags & KVM_MEM_READONLY)) ? true : false; ++ bool logging = kvm_slot_dirty_track_enabled(memslot) && ++ !(memslot->flags & KVM_MEM_READONLY); + unsigned long vma_pagesize, mmu_seq; + struct kvm_gstage gstage; + struct page *page; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0435-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch b/SPECS/linux-lts/0435-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch deleted file mode 100644 index 4ffd3a5571..0000000000 --- a/SPECS/linux-lts/0435-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 48c328f5e19a84fb0c038a92a3aecb8167523082 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 14 May 2025 08:16:15 +0800 -Subject: [PATCH 435/467] REVYOS: riscv: dts: th1520: rename thead to xuantie - -Signed-off-by: Han Gao -[Icenowy: preserve the original compatible to allow Linux to match] -Signed-off-by: Icenowy Zheng ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index e44010810c07..f85d93227170 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -286,7 +286,7 @@ stmmac_axi_config: stmmac-axi-config { - }; - - aon: aon { -- compatible = "thead,th1520-aon"; -+ compatible = "xuantie,th1520-aon", "thead,th1520-aon"; - mboxes = <&mbox_910t 1>; - mbox-names = "aon"; - resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0436-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch b/SPECS/linux-lts/0436-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch new file mode 100644 index 0000000000..3af359443c --- /dev/null +++ b/SPECS/linux-lts/0436-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch @@ -0,0 +1,75 @@ +From 1089052df50a4781f12e65e68f2cfeb75dca9d84 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Tue, 2 Jun 2026 18:00:00 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable PCIe on OrangePi + R2S + +Enable the two RTL8125 network controllers and corresponding +PHYs connected via the PCIe controllers on the OrangePi R2S. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20260602100000.2402784-1-amadeus@jmu.edu.cn +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-r2s.dts | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index b13a8d6a2670..919e5b451109 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -23,6 +23,14 @@ chosen { + stdout-path = "serial0"; + }; + ++ pcie_vcc3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie_vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + vcc4v0: regulator-vcc4v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0"; +@@ -228,6 +236,36 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie2 { ++ status = "okay"; ++}; ++ + &pdma { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0436-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch b/SPECS/linux-lts/0436-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch deleted file mode 100644 index ba1a3a3e56..0000000000 --- a/SPECS/linux-lts/0436-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch +++ /dev/null @@ -1,44 +0,0 @@ -From e973bd6b6cca07542eeec6f28391bf5e9bf49ef3 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 14 May 2025 08:27:18 +0800 -Subject: [PATCH 436/467] REVYOS: riscv: dts: th1520: add xuantie,th1520-mbox-r - -Signed-off-by: Han Gao -[Icenowy: remove the interrupt-controller property] -Signed-off-by: Icenowy Zheng ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index f85d93227170..ab681cf850d1 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -292,6 +292,24 @@ aon: aon { - resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; - reset-names = "gpu-clkgen"; - #power-domain-cells = <1>; -+ opensbi-mboxes = <&mbox_910r>; -+ status = "okay"; -+ }; -+ -+ mbox_910r: mbox@ffefc53000 { -+ compatible = "xuantie,th1520-mbox-r"; -+ reg = <0xff 0xefc53000 0x0 0x4000>, -+ <0xff 0xefc3f000 0x0 0x1000>, -+ <0xff 0xefc47000 0x0 0x1000>, -+ <0xff 0xefc4f000 0x0 0x1000>; -+ reg-names = "local_base", -+ "remote_icu0", -+ "remote_icu1", -+ "remote_icu2"; -+ clocks = <&clk CLK_PERI_APB_PCLK>; -+ clock-names = "ipg"; -+ icu_cpu_id = <3>; -+ #mbox-cells = <2>; - }; - - soc { --- -2.53.0 - diff --git a/SPECS/linux-lts/0437-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch b/SPECS/linux-lts/0437-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch new file mode 100644 index 0000000000..0150c1e446 --- /dev/null +++ b/SPECS/linux-lts/0437-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch @@ -0,0 +1,105 @@ +From 63031abd1c4c52dfc3b406612721eff99c69ed49 Mon Sep 17 00:00:00 2001 +From: Wang Yechao +Date: Thu, 4 Jun 2026 14:55:10 +0800 +Subject: [RUYI PATCH] FROMLIST: iommu/riscv: Add dependency between iommu and + devices + +Commit 9156585280f1 ("ACPI: RIMT: Add dependency between iommu and +devices") adds the dependency between iommu and devices on ACPI +systems. On devicetree systems, the incorrect removal order also +occurs. + +It can be reproduced on the QEMU RISC-V machine if the kernel enables +IOMMU_DMA: + +[ 635.081530] e1000e: EEE TX LPI TIMER: 00000000 +[ 656.100306] rcu: INFO: rcu_sched self-detected stall on CPU +[ 656.101374] rcu: 5-....: (5250 ticks this GP) idle=d774/1/0x4000000000000000 softirq=5173/5185 fqs=2625 +[ 656.102237] rcu: (t=5251 jiffies g=36825 q=101 ncpus=16) +[ 656.103801] CPU: 5 UID: 0 PID: 1958 Comm: reboot Tainted: G W 7.1.0-rc5 #31 PREEMPTLAZY +[ 656.104127] Tainted: [W]=WARN +[ 656.104182] Hardware name: QEMU QEMU Virtual Machine, BIOS 2.7 02/02/2022 +[ 656.104339] epc : riscv_iommu_cmd_sync.constprop.0+0xb8/0x148 +[ 656.105352] ra : riscv_iommu_cmd_sync.constprop.0+0xa8/0x148 +[ 656.105433] epc : ffffffff807ca980 ra : ffffffff807ca970 sp : ff60000085dbf960 +[ 656.105475] gp : ffffffff81e0d798 tp : ff60000084b58e00 t0 : ffffffff80021048 +[ 656.105514] t1 : ff60000081b18400 t2 : 45203a6530303031 s0 : ff60000085dbf9c0 +[ 656.105554] s1 : 00000098c92a567c a0 : 00000098c03986f0 a1 : ff60000085dbf970 +[ 656.105594] a2 : 000024bb5cac6aee a3 : ff200000004f1000 a4 : ff6000008140a040 +[ 656.105632] a5 : 0000000000000669 a6 : 0000000000000000 a7 : 00000000ffffa000 +[ 656.105669] s2 : 0000000000000000 s3 : 00000098c0398308 s4 : 000000000000066a +[ 656.105706] s5 : 0000000008f0d180 s6 : 000000a8d08b8de9 s7 : 0000000000001fff +[ 656.105743] s8 : ff6000008140a040 s9 : ff6000008484cb00 s10: ff200000005cc000 +[ 656.105781] s11: ff600000814652a0 t3 : 000000f000000000 t4 : 0000000000000000 +[ 656.105845] t5 : 0000000000000003 t6 : ff600000841666b0 ssp : 0000000000000000 +[ 656.105883] status: 0000000200000120 badaddr: 0000000000000000 cause: 8000000000000005 +[ 656.106072] riscv_iommu_cmd_sync.constprop.0+0xb8/0x148 +[ 656.106321] riscv_iommu_iotlb_inval+0x120/0x160 +[ 656.106373] riscv_iommu_iotlb_sync+0x48/0x60 +[ 656.106422] __iommu_dma_unmap+0xca/0xf8 +[ 656.106470] iommu_dma_unmap_phys+0x58/0xc8 +[ 656.106517] dma_unmap_phys+0x15c/0x248 +[ 656.106564] dma_unmap_page_attrs+0x1e/0x30 +[ 656.106915] e1000_clean_rx_ring+0x1d2/0x200 [e1000e] +[ 656.107668] e1000e_down+0x168/0x1c8 [e1000e] +[ 656.107995] e1000e_pm_freeze+0x94/0x128 [e1000e] +[ 656.108328] e1000_shutdown+0x28/0x48 [e1000e] +[ 656.108652] pci_device_shutdown+0x34/0x48 +[ 656.108706] device_shutdown+0x104/0x1e8 +[ 656.108752] kernel_restart+0x46/0xb8 +[ 656.108797] __do_sys_reboot+0xc0/0x1c8 +[ 656.108840] __riscv_sys_reboot+0x22/0x38 +[ 656.108882] do_trap_ecall_u+0x236/0x3f8 +[ 656.108947] handle_exception+0x15a/0x166 + +So move the device link into the iommu driver to fix both ACPI and +devicetree systems. + +Fixes: 488ffbf18171 ("iommu/riscv: Paging domain support") +Signed-off-by: Wang Yechao +Link: https://lore.kernel.org/r/20260604145510898G2kTwM2Pr25QE5H8T4Wh6@zte.com.cn +Signed-off-by: Han Gao +--- + drivers/acpi/riscv/rimt.c | 7 ------- + drivers/iommu/riscv/iommu.c | 7 +++++++ + 2 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/acpi/riscv/rimt.c b/drivers/acpi/riscv/rimt.c +index 8eaa8731bddd..7f423405e5ef 100644 +--- a/drivers/acpi/riscv/rimt.c ++++ b/drivers/acpi/riscv/rimt.c +@@ -263,13 +263,6 @@ static int rimt_iommu_xlate(struct device *dev, struct acpi_rimt_node *node, u32 + if (!rimt_fwnode) + return -EPROBE_DEFER; + +- /* +- * EPROBE_DEFER ensures IOMMU is probed before the devices that +- * depend on them. During shutdown, however, the IOMMU may be removed +- * first, leading to issues. To avoid this, a device link is added +- * which enforces the correct removal order. +- */ +- device_link_add(dev, rimt_fwnode->dev, DL_FLAG_AUTOREMOVE_CONSUMER); + return acpi_iommu_fwspec_init(dev, deviceid, rimt_fwnode); + } + +diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c +index de286563bd44..07ae3c4ec38e 100644 +--- a/drivers/iommu/riscv/iommu.c ++++ b/drivers/iommu/riscv/iommu.c +@@ -1598,6 +1598,13 @@ static struct iommu_device *riscv_iommu_probe_device(struct device *dev) + + dev_iommu_priv_set(dev, info); + ++ /* ++ * During shutdown, however, the IOMMU may be removed first, leading ++ * to issues. To avoid this, a device link is added which enforces ++ * the correct removal order. ++ */ ++ device_link_add(dev, fwspec->iommu_fwnode->dev, DL_FLAG_AUTOREMOVE_CONSUMER); ++ + return &iommu->iommu; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0437-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch b/SPECS/linux-lts/0437-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch deleted file mode 100644 index 3913520ac4..0000000000 --- a/SPECS/linux-lts/0437-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 58b84bc14138597b9031f9e8d047b52130e77045 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 19 Nov 2023 21:13:31 +0800 -Subject: [PATCH 437/467] SOPHGO: dt-bindings: nvmem: Add SG2044 eFuse - controller - -Sophgo SG2044 uses eFuses used to store factory-programmed data -such as ROM patch, public keys and other factory information. - -Signed-off-by: Inochi Amaoto ---- - .../bindings/nvmem/sophgo,efuse.yaml | 61 +++++++++++++++++++ - 1 file changed, 61 insertions(+) - create mode 100644 Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml - -diff --git a/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml -new file mode 100644 -index 000000000000..d4bffe2724ac ---- /dev/null -+++ b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml -@@ -0,0 +1,61 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/nvmem/sophgo,efuse.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Sophgo SoC eFuse-based NVMEM -+ -+description: -+ Sophgo SoCs contain factory-programmed eFuses used to store ROM patch, -+ public key and other factory information. -+ -+maintainers: -+ - Inochi Amaoto -+ -+allOf: -+ - $ref: nvmem.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - sophgo,sg2044-efuse -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 1 -+ items: -+ - description: Core clock -+ - description: APB clock -+ -+ clock-names: -+ minItems: 1 -+ items: -+ - const: core -+ - const: apb -+ -+ resets: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ efuse@40000000 { -+ compatible = "sophgo,sg2044-efuse"; -+ reg = <0x40000000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&clk 0>, -+ <&clk 1>; -+ clock-names = "core", "apb"; -+ }; -+ -+... --- -2.53.0 - diff --git a/SPECS/linux-lts/0438-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch b/SPECS/linux-lts/0438-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch deleted file mode 100644 index 7a5c632111..0000000000 --- a/SPECS/linux-lts/0438-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 6ac29107a01f6a190188cc8c4ed3d8f9ac21c834 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 19 Nov 2023 21:13:32 +0800 -Subject: [PATCH 438/467] SOPHGO: nvmem: Add Sophgo SG2044 eFuse driver - -Sophgo SoCs such as SG2044 contain eFuses used to store -factory-programmed data. - -As for SG2044, HW automatically loads the eFuse content -into shadow registers which are organized as 32bit values -exposed as MMIO. - -Signed-off-by: Inochi Amaoto ---- - drivers/nvmem/Kconfig | 12 +++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/sophgo-efuse.c | 176 +++++++++++++++++++++++++++++++++++ - 3 files changed, 190 insertions(+) - create mode 100644 drivers/nvmem/sophgo-efuse.c - -diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig -index 11b098705ec6..42f46eb0462a 100644 ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -356,6 +356,18 @@ config NVMEM_SNVS_LPGPR - This driver can also be built as a module. If so, the module - will be called nvmem-snvs-lpgpr. - -+config NVMEM_SOPHGO_EFUSE -+ tristate "Sophgo eFuse support" -+ depends on ARCH_SOPHGO || COMPILE_TEST -+ default ARCH_SOPHGO -+ help -+ Say y here to enable support for reading eFuses on Sophgo SoCs -+ such as the CV1800B. These are e.g. used to store factory programmed -+ calibration data required for the builtin ethernet PHY. -+ -+ This driver can also be built as a module. If so, the module will -+ be called nvmem-sophgo-efuse. -+ - config NVMEM_SPMI_SDAM - tristate "SPMI SDAM Support" - depends on SPMI -diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile -index 70a4464dcb1e..6cc324aaa757 100644 ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -70,6 +70,8 @@ obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o - nvmem-sc27xx-efuse-y := sc27xx-efuse.o - obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o - nvmem_snvs_lpgpr-y := snvs_lpgpr.o -+obj-$(CONFIG_NVMEM_SOPHGO_EFUSE) += nvmem-sophgo-efuse.o -+nvmem-sophgo-efuse-y := sophgo-efuse.o - obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o - nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o - obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o -diff --git a/drivers/nvmem/sophgo-efuse.c b/drivers/nvmem/sophgo-efuse.c -new file mode 100644 -index 000000000000..5f90adaf8e4f ---- /dev/null -+++ b/drivers/nvmem/sophgo-efuse.c -@@ -0,0 +1,176 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Sophgo SoC eFuse driver -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define SG2044_EFUSE_CONTENT_SIZE 0x400 -+ -+#define SG2044_EFUSE_MD 0x000 -+#define SG2044_EFUSE_ADR 0x004 -+#define SG2044_EFUSE_RD_DATA 0x00c -+ -+#define SG2044_EFUSE_MODE GENMASK(1, 0) -+#define SG2044_EFUSE_MODE_READ 2 -+ -+#define SG2044_EFUSE_BOOT_DONE BIT(7) -+#define SG2044_BOOT_TIMEOUT 10000 -+ -+#define SG2044_EFUSE_ADR_ADDR GENMASK(7, 0) -+ -+#define SG2044_EFUSE_ALIGN 4 -+ -+struct sophgo_efuses { -+ void __iomem *base; -+ struct clk_bulk_data *clks; -+ int num_clks; -+ struct mutex mutex; -+}; -+ -+static int sg2044_efuse_wait_mode(struct sophgo_efuses *efuse) -+{ -+ u32 value; -+ -+ return readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, -+ FIELD_GET(SG2044_EFUSE_MODE, value) == 0, -+ 1, SG2044_BOOT_TIMEOUT); -+} -+ -+static int sg2044_efuse_set_mode(struct sophgo_efuses *efuse, int mode) -+{ -+ u32 val = readl(efuse->base + SG2044_EFUSE_MD); -+ -+ val &= ~SG2044_EFUSE_MODE; -+ val |= FIELD_PREP(SG2044_EFUSE_MODE, mode); -+ -+ writel(val, efuse->base + SG2044_EFUSE_MD); -+ -+ return sg2044_efuse_wait_mode(efuse); -+} -+ -+static u32 sg2044_efuses_read_strip(struct sophgo_efuses *efuse, -+ unsigned int offset, u32 *strip) -+{ -+ u32 val = FIELD_PREP(SG2044_EFUSE_ADR_ADDR, offset); -+ int ret; -+ -+ guard(mutex)(&efuse->mutex); -+ -+ writel(val, efuse->base + SG2044_EFUSE_ADR); -+ -+ ret = sg2044_efuse_set_mode(efuse, SG2044_EFUSE_MODE_READ); -+ if (ret < 0) -+ return ret; -+ -+ *strip = readl(efuse->base + SG2044_EFUSE_RD_DATA); -+ -+ return 0; -+} -+ -+static int sg2044_efuses_read(void *context, unsigned int offset, void *val, -+ size_t bytes) -+{ -+ struct sophgo_efuses *efuse = context; -+ unsigned int start, start_offset, end, i; -+ u32 value; -+ u8 *buf; -+ int ret; -+ -+ start = rounddown(offset, SG2044_EFUSE_ALIGN); -+ end = roundup(offset + bytes, SG2044_EFUSE_ALIGN); -+ start_offset = offset - start; -+ -+ start /= SG2044_EFUSE_ALIGN; -+ end /= SG2044_EFUSE_ALIGN; -+ -+ ret = readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, -+ (value & SG2044_EFUSE_BOOT_DONE), -+ 1, SG2044_BOOT_TIMEOUT); -+ if (ret < 0) -+ return ret; -+ -+ buf = kzalloc(end - start, GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ for (i = start; i < end; i++) { -+ ret = sg2044_efuses_read_strip(efuse, i, &value); -+ if (ret) -+ goto failed; -+ -+ memcpy(&buf[(i - start) * 4], &value, SG2044_EFUSE_ALIGN); -+ } -+ -+ memcpy(val, buf + start_offset, bytes); -+ -+failed: -+ kfree(buf); -+ -+ return ret; -+} -+ -+static int sophgo_efuses_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct sophgo_efuses *efuse; -+ struct nvmem_config config = { -+ .dev = &pdev->dev, -+ .add_legacy_fixed_of_cells = true, -+ .read_only = true, -+ .reg_read = sg2044_efuses_read, -+ .stride = 1, -+ .word_size = 1, -+ .name = "sophgo-efuse", -+ .id = NVMEM_DEVID_AUTO, -+ .root_only = true, -+ }; -+ -+ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); -+ if (!efuse) -+ return -ENOMEM; -+ -+ efuse->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(efuse->base)) -+ return PTR_ERR(efuse->base); -+ -+ efuse->num_clks = devm_clk_bulk_get_all_enabled(&pdev->dev, &efuse->clks); -+ if (efuse->num_clks < 0) -+ return dev_err_probe(dev, efuse->num_clks, "failed to get clocks\n"); -+ -+ config.priv = efuse; -+ config.size = SG2044_EFUSE_CONTENT_SIZE; -+ -+ return PTR_ERR_OR_ZERO(devm_nvmem_register(config.dev, &config)); -+} -+ -+static const struct of_device_id sophgo_efuses_of_match[] = { -+ { .compatible = "sophgo,sg2044-efuse", }, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(of, sophgo_efuses_of_match); -+ -+static struct platform_driver sophgo_efuses_driver = { -+ .driver = { -+ .name = "sophgo_efuse", -+ .of_match_table = sophgo_efuses_of_match, -+ }, -+ .probe = sophgo_efuses_probe, -+}; -+ -+module_platform_driver(sophgo_efuses_driver); -+ -+MODULE_AUTHOR("Inochi Amaoto "); -+MODULE_DESCRIPTION("Sophgo efuse driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0438-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch b/SPECS/linux-lts/0438-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch new file mode 100644 index 0000000000..19a9ca6539 --- /dev/null +++ b/SPECS/linux-lts/0438-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch @@ -0,0 +1,49 @@ +From 202c07f948325a5c584ae346de90b289bd86b125 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Mon, 24 Nov 2025 20:38:44 +0800 +Subject: [RUYI PATCH] XUANTIE: riscv: dts: th1520: add licheepi4a 16g support + +From: https://github.com/revyos/th1520-linux-kernel/commit/01a510898e41e704bee1fe58a2c0c0a29cb96548 + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/Makefile | 1 + + .../boot/dts/thead/th1520-lichee-pi-4a-16g.dts | 18 ++++++++++++++++++ + 2 files changed, 19 insertions(+) + create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts + +diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile +index b55a17127c2b..281849e71ccb 100644 +--- a/arch/riscv/boot/dts/thead/Makefile ++++ b/arch/riscv/boot/dts/thead/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb ++dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a-16g.dtb +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts +new file mode 100644 +index 000000000000..a3a991baf716 +--- /dev/null ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts +@@ -0,0 +1,18 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 Han Gao ++ */ ++ ++/dts-v1/; ++ ++#include "th1520-lichee-pi-4a.dts" ++ ++/ { ++ model = "Sipeed Lichee Pi 4A 16G"; ++ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x00000000 0x4 0x00000000>; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0439-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch b/SPECS/linux-lts/0439-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch new file mode 100644 index 0000000000..1c294c8a28 --- /dev/null +++ b/SPECS/linux-lts/0439-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch @@ -0,0 +1,28 @@ +From 7b0831ac6fa2e8db34c9c89d4e02bf2aa105fab3 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 14 May 2025 08:16:15 +0800 +Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: rename thead to xuantie + +Signed-off-by: Han Gao +[Icenowy: preserve the original compatible to allow Linux to match] +Signed-off-by: Icenowy Zheng +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index e44010810c07..f85d93227170 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -286,7 +286,7 @@ stmmac_axi_config: stmmac-axi-config { + }; + + aon: aon { +- compatible = "thead,th1520-aon"; ++ compatible = "xuantie,th1520-aon", "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0439-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch b/SPECS/linux-lts/0439-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch deleted file mode 100644 index 13be292227..0000000000 --- a/SPECS/linux-lts/0439-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 067900c6efeb7cfec72358b2de3190c383988fb7 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Thu, 5 Dec 2024 13:24:13 +0800 -Subject: [PATCH 439/467] SOPHGO: riscv: dts: sophgo: sg2044: Add eFUSE device - -Add eFUSE controller node for SG2044. - -Signed-off-by: Inochi Amaoto ---- - arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ - arch/riscv/boot/dts/sophgo/sg2044.dtsi | 12 ++++++++++++ - 2 files changed, 16 insertions(+) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -index fed3d9a384a0..1b506972d465 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -@@ -36,6 +36,10 @@ &emmc { - status = "okay"; - }; - -+&efuse0 { -+ status = "okay"; -+}; -+ - &gmac0 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; -diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -index 320c4d1d08e6..9577aae08f7f 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -@@ -408,6 +408,18 @@ sd: mmc@703000b000 { - status = "disabled"; - }; - -+ efuse0: efuse@7040000000 { -+ compatible = "sophgo,sg2044-efuse"; -+ reg = <0x70 0x40000000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&clk CLK_GATE_EFUSE>, -+ <&clk CLK_GATE_APB_EFUSE>; -+ clock-names = "core", "apb"; -+ resets = <&rst RST_EFUSE0>; -+ status = "disabled"; -+ }; -+ - i2c0: i2c@7040005000 { - compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; - reg = <0x70 0x40005000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0440-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch b/SPECS/linux-lts/0440-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch new file mode 100644 index 0000000000..757ee92472 --- /dev/null +++ b/SPECS/linux-lts/0440-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch @@ -0,0 +1,44 @@ +From 1fa033781168266e279c276df269822336f8d946 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 14 May 2025 08:27:18 +0800 +Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: add xuantie,th1520-mbox-r + +Signed-off-by: Han Gao +[Icenowy: remove the interrupt-controller property] +Signed-off-by: Icenowy Zheng +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index f85d93227170..ab681cf850d1 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -292,6 +292,24 @@ aon: aon { + resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; + reset-names = "gpu-clkgen"; + #power-domain-cells = <1>; ++ opensbi-mboxes = <&mbox_910r>; ++ status = "okay"; ++ }; ++ ++ mbox_910r: mbox@ffefc53000 { ++ compatible = "xuantie,th1520-mbox-r"; ++ reg = <0xff 0xefc53000 0x0 0x4000>, ++ <0xff 0xefc3f000 0x0 0x1000>, ++ <0xff 0xefc47000 0x0 0x1000>, ++ <0xff 0xefc4f000 0x0 0x1000>; ++ reg-names = "local_base", ++ "remote_icu0", ++ "remote_icu1", ++ "remote_icu2"; ++ clocks = <&clk CLK_PERI_APB_PCLK>; ++ clock-names = "ipg"; ++ icu_cpu_id = <3>; ++ #mbox-cells = <2>; + }; + + soc { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0440-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch b/SPECS/linux-lts/0440-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch deleted file mode 100644 index 4dd1171275..0000000000 --- a/SPECS/linux-lts/0440-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 819aa39c2d1a6d2c6cbde41fb83516b927d08626 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Sun, 28 Dec 2025 23:02:15 +0800 -Subject: [PATCH 440/467] SOPHGO: dts: sg2044: Modify pcie bar address - -FROM: https://github.com/sophgo/linux-riscv/commit/efddc3e2d3d57b27054415afb522100e6dce8692 - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2044.dtsi | 28 +++++++++++++------------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -index 9577aae08f7f..f1377ee8e149 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -@@ -36,7 +36,7 @@ pcie0: pcie@6c00000000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x00000000 0x0 0x00001000>, - <0x6c 0x00300000 0x0 0x00004000>, -- <0x48 0x00000000 0x0 0x00001000>, -+ <0x50 0x00000000 0x0 0x00001000>, - <0x6c 0x000c0000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -51,11 +51,11 @@ pcie0: pcie@6c00000000 { - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, - <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, -- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, -- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x54 0x00000000 0x54 0x00000000 0x4 0x00000000>, -+ <0x03000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>; - status = "disabled"; - - pcie_intc0: interrupt-controller { -@@ -89,8 +89,8 @@ pcie1: pcie@6c00400000 { - ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>, - <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>, -- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, -- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x44 0x00000000 0x44 0x00000000 0x4 0x00000000>, -+ <0x03000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>; - status = "disabled"; - - pcie_intc1: interrupt-controller { -@@ -106,7 +106,7 @@ pcie2: pcie@6c04000000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x04000000 0x0 0x00001000>, - <0x6c 0x04300000 0x0 0x00004000>, -- <0x58 0x00000000 0x0 0x00001000>, -+ <0x7c 0x00000000 0x0 0x00001000>, - <0x6c 0x040c0000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -121,11 +121,11 @@ pcie2: pcie@6c04000000 { - <0 0 0 3 &pcie_intc2 2>, - <0 0 0 4 &pcie_intc2 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x7c 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>, - <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>, -- <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>, -- <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x7d 0x00000000 0x7d 0x00000000 0x1 0x00000000>, -+ <0x03000000 0x7c 0x80000000 0x7c 0x80000000 0x0 0x80000000>; - status = "disabled"; - - pcie_intc2: interrupt-controller { -@@ -141,7 +141,7 @@ pcie3: pcie@6c04400000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x04400000 0x0 0x00001000>, - <0x6c 0x04700000 0x0 0x00004000>, -- <0x50 0x00000000 0x0 0x00001000>, -+ <0x78 0x00000000 0x0 0x00001000>, - <0x6c 0x04780000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -156,11 +156,11 @@ pcie3: pcie@6c04400000 { - <0 0 0 3 &pcie_intc3 2>, - <0 0 0 4 &pcie_intc3 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x78 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>, - <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>, -- <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>, -- <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x79 0x00000000 0x79 0x00000000 0x1 0x00000000>, -+ <0x03000000 0x78 0x80000000 0x78 0x80000000 0x0 0x80000000>; - status = "disabled"; - - pcie_intc3: interrupt-controller { --- -2.53.0 - diff --git a/SPECS/linux-lts/0441-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch b/SPECS/linux-lts/0441-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch new file mode 100644 index 0000000000..79f21e68df --- /dev/null +++ b/SPECS/linux-lts/0441-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch @@ -0,0 +1,84 @@ +From 40d9d7d4261e84ef42987558481248dd8a8a89b0 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 19 Nov 2023 21:13:31 +0800 +Subject: [RUYI PATCH] SOPHGO: dt-bindings: nvmem: Add SG2044 eFuse controller + +Sophgo SG2044 uses eFuses used to store factory-programmed data +such as ROM patch, public keys and other factory information. + +Signed-off-by: Inochi Amaoto +--- + .../bindings/nvmem/sophgo,efuse.yaml | 61 +++++++++++++++++++ + 1 file changed, 61 insertions(+) + create mode 100644 Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml + +diff --git a/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml +new file mode 100644 +index 000000000000..d4bffe2724ac +--- /dev/null ++++ b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml +@@ -0,0 +1,61 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/nvmem/sophgo,efuse.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Sophgo SoC eFuse-based NVMEM ++ ++description: ++ Sophgo SoCs contain factory-programmed eFuses used to store ROM patch, ++ public key and other factory information. ++ ++maintainers: ++ - Inochi Amaoto ++ ++allOf: ++ - $ref: nvmem.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - sophgo,sg2044-efuse ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 1 ++ items: ++ - description: Core clock ++ - description: APB clock ++ ++ clock-names: ++ minItems: 1 ++ items: ++ - const: core ++ - const: apb ++ ++ resets: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ efuse@40000000 { ++ compatible = "sophgo,sg2044-efuse"; ++ reg = <0x40000000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&clk 0>, ++ <&clk 1>; ++ clock-names = "core", "apb"; ++ }; ++ ++... +-- +2.53.0 + diff --git a/SPECS/linux-lts/0441-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch b/SPECS/linux-lts/0441-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch deleted file mode 100644 index 23c3d7b4f9..0000000000 --- a/SPECS/linux-lts/0441-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch +++ /dev/null @@ -1,30 +0,0 @@ -From c9a6181747df1dd9980ccca9e4e34a51afc1f1db Mon Sep 17 00:00:00 2001 -From: Xiaoguang Xing -Date: Mon, 22 Jan 2024 10:31:30 +0800 -Subject: [PATCH 441/467] SOPHGO: riscv: sg2042: errata: Replace thead cache - clean with flush - -FROM: https://github.com/sophgo/linux-riscv/commit/9f8fdd99aae6ae8f037ad9c80b968de7c4252a65 - -Signed-off-by: Xiaoguang Xing -Signed-off-by: Han Gao ---- - arch/riscv/errata/thead/errata.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c -index fbe46f2fa8fb..9be8c45f4531 100644 ---- a/arch/riscv/errata/thead/errata.c -+++ b/arch/riscv/errata/thead/errata.c -@@ -67,7 +67,7 @@ static bool errata_probe_mae(unsigned int stage, - * 0000000 11001 00000 000 00000 0001011 - */ - #define THEAD_INVAL_A0 ".long 0x02a5000b" --#define THEAD_CLEAN_A0 ".long 0x0295000b" -+#define THEAD_CLEAN_A0 ".long 0x02b5000b" - #define THEAD_FLUSH_A0 ".long 0x02b5000b" - #define THEAD_SYNC_S ".long 0x0190000b" - --- -2.53.0 - diff --git a/SPECS/linux-lts/0442-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch b/SPECS/linux-lts/0442-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch deleted file mode 100644 index ff15f677fa..0000000000 --- a/SPECS/linux-lts/0442-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 5d179609e5c15e909b3700913113fa6b03c0cb53 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Fri, 24 Oct 2025 15:59:17 +0800 -Subject: [PATCH 442/467] REVYSR: dt-bindings: net: ultrarisc,dp1000-gmac: Add - support for Ultrarisc DP1000 GMAC - -The GMAC IP on DP1000 is a standard Synopsys DesignWare MAC -(version 5.10a). - -Add necessary compatible string for this device. - -Signed-off-by: Han Gao -Signed-off-by: Han Gao -FROM: https://github.com/RevySR/linux/commit/5eda7fb5c988909f44edab38678cd124a9a5b98f -Signed-off-by: Han Gao ---- - .../devicetree/bindings/net/snps,dwmac.yaml | 1 + - .../bindings/net/ultrarisc,dp1000-gmac.yaml | 89 +++++++++++++++++++ - 2 files changed, 90 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml - -diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -index eb36cb36a57a..a8a45b844335 100644 ---- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml -+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -@@ -113,6 +113,7 @@ properties: - - starfive,jh7110-dwmac - - tesla,fsd-ethqos - - thead,th1520-gmac -+ - ultrarisc,dp1000-gmac - - reg: - minItems: 1 -diff --git a/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml -new file mode 100644 -index 000000000000..ace5c4058cc9 ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml -@@ -0,0 +1,89 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/ultrarisc,dp1000-gmac.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Ultrarisc dp1000 glue layer -+ -+maintainers: -+ - Han Gao -+ -+select: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - ultrarisc,dp1000-gmac -+ required: -+ - compatible -+ -+properties: -+ compatible: -+ oneOf: -+ - items: -+ - const: ultrarisc,dp1000-gmac -+ - const: snps,dwmac-5.10a -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: GMAC main clock -+ - description: PTP clock -+ - description: TX clock -+ -+ clock-names: -+ items: -+ - const: stmmaceth -+ -+ dma-noncoherent: true -+ -+ interrupts: -+ maxItems: 1 -+ -+ interrupt-names: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - interrupt-names -+ -+allOf: -+ - $ref: snps,dwmac.yaml# -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ -+ ethernet1@38000000 { -+ clocks = <&csr_clk>; -+ clock-names = "stmmaceth"; -+ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; -+ interrupt-parent = <0x01>; -+ interrupts = <84>; -+ interrupt-names = "macirq"; -+ reg = <0x00 0x38000000 0x00 0x1000000>; -+ local-mac-address = [ff ff ff ff ff ff]; -+ phy-mode = "rgmii"; -+ max-speed = <1000>; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ phy-handle = <&phy0>; -+ mdio { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ compatible = "snps,dwmac-mdio"; -+ phy0: phy@0{ -+ reg = <0x00>; -+ status = "okay"; -+ }; -+ }; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch b/SPECS/linux-lts/0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch new file mode 100644 index 0000000000..2ebd4453f3 --- /dev/null +++ b/SPECS/linux-lts/0442-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch @@ -0,0 +1,241 @@ +From e96eabf82535fd6f2fc338f3f5af2fb50721a459 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 19 Nov 2023 21:13:32 +0800 +Subject: [RUYI PATCH] SOPHGO: nvmem: Add Sophgo SG2044 eFuse driver + +Sophgo SoCs such as SG2044 contain eFuses used to store +factory-programmed data. + +As for SG2044, HW automatically loads the eFuse content +into shadow registers which are organized as 32bit values +exposed as MMIO. + +Signed-off-by: Inochi Amaoto +--- + drivers/nvmem/Kconfig | 12 +++ + drivers/nvmem/Makefile | 2 + + drivers/nvmem/sophgo-efuse.c | 176 +++++++++++++++++++++++++++++++++++ + 3 files changed, 190 insertions(+) + create mode 100644 drivers/nvmem/sophgo-efuse.c + +diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig +index 11b098705ec6..42f46eb0462a 100644 +--- a/drivers/nvmem/Kconfig ++++ b/drivers/nvmem/Kconfig +@@ -356,6 +356,18 @@ config NVMEM_SNVS_LPGPR + This driver can also be built as a module. If so, the module + will be called nvmem-snvs-lpgpr. + ++config NVMEM_SOPHGO_EFUSE ++ tristate "Sophgo eFuse support" ++ depends on ARCH_SOPHGO || COMPILE_TEST ++ default ARCH_SOPHGO ++ help ++ Say y here to enable support for reading eFuses on Sophgo SoCs ++ such as the CV1800B. These are e.g. used to store factory programmed ++ calibration data required for the builtin ethernet PHY. ++ ++ This driver can also be built as a module. If so, the module will ++ be called nvmem-sophgo-efuse. ++ + config NVMEM_SPMI_SDAM + tristate "SPMI SDAM Support" + depends on SPMI +diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile +index 70a4464dcb1e..6cc324aaa757 100644 +--- a/drivers/nvmem/Makefile ++++ b/drivers/nvmem/Makefile +@@ -70,6 +70,8 @@ obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o + nvmem-sc27xx-efuse-y := sc27xx-efuse.o + obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o + nvmem_snvs_lpgpr-y := snvs_lpgpr.o ++obj-$(CONFIG_NVMEM_SOPHGO_EFUSE) += nvmem-sophgo-efuse.o ++nvmem-sophgo-efuse-y := sophgo-efuse.o + obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o + nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o + obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o +diff --git a/drivers/nvmem/sophgo-efuse.c b/drivers/nvmem/sophgo-efuse.c +new file mode 100644 +index 000000000000..5f90adaf8e4f +--- /dev/null ++++ b/drivers/nvmem/sophgo-efuse.c +@@ -0,0 +1,176 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Sophgo SoC eFuse driver ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SG2044_EFUSE_CONTENT_SIZE 0x400 ++ ++#define SG2044_EFUSE_MD 0x000 ++#define SG2044_EFUSE_ADR 0x004 ++#define SG2044_EFUSE_RD_DATA 0x00c ++ ++#define SG2044_EFUSE_MODE GENMASK(1, 0) ++#define SG2044_EFUSE_MODE_READ 2 ++ ++#define SG2044_EFUSE_BOOT_DONE BIT(7) ++#define SG2044_BOOT_TIMEOUT 10000 ++ ++#define SG2044_EFUSE_ADR_ADDR GENMASK(7, 0) ++ ++#define SG2044_EFUSE_ALIGN 4 ++ ++struct sophgo_efuses { ++ void __iomem *base; ++ struct clk_bulk_data *clks; ++ int num_clks; ++ struct mutex mutex; ++}; ++ ++static int sg2044_efuse_wait_mode(struct sophgo_efuses *efuse) ++{ ++ u32 value; ++ ++ return readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, ++ FIELD_GET(SG2044_EFUSE_MODE, value) == 0, ++ 1, SG2044_BOOT_TIMEOUT); ++} ++ ++static int sg2044_efuse_set_mode(struct sophgo_efuses *efuse, int mode) ++{ ++ u32 val = readl(efuse->base + SG2044_EFUSE_MD); ++ ++ val &= ~SG2044_EFUSE_MODE; ++ val |= FIELD_PREP(SG2044_EFUSE_MODE, mode); ++ ++ writel(val, efuse->base + SG2044_EFUSE_MD); ++ ++ return sg2044_efuse_wait_mode(efuse); ++} ++ ++static u32 sg2044_efuses_read_strip(struct sophgo_efuses *efuse, ++ unsigned int offset, u32 *strip) ++{ ++ u32 val = FIELD_PREP(SG2044_EFUSE_ADR_ADDR, offset); ++ int ret; ++ ++ guard(mutex)(&efuse->mutex); ++ ++ writel(val, efuse->base + SG2044_EFUSE_ADR); ++ ++ ret = sg2044_efuse_set_mode(efuse, SG2044_EFUSE_MODE_READ); ++ if (ret < 0) ++ return ret; ++ ++ *strip = readl(efuse->base + SG2044_EFUSE_RD_DATA); ++ ++ return 0; ++} ++ ++static int sg2044_efuses_read(void *context, unsigned int offset, void *val, ++ size_t bytes) ++{ ++ struct sophgo_efuses *efuse = context; ++ unsigned int start, start_offset, end, i; ++ u32 value; ++ u8 *buf; ++ int ret; ++ ++ start = rounddown(offset, SG2044_EFUSE_ALIGN); ++ end = roundup(offset + bytes, SG2044_EFUSE_ALIGN); ++ start_offset = offset - start; ++ ++ start /= SG2044_EFUSE_ALIGN; ++ end /= SG2044_EFUSE_ALIGN; ++ ++ ret = readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, ++ (value & SG2044_EFUSE_BOOT_DONE), ++ 1, SG2044_BOOT_TIMEOUT); ++ if (ret < 0) ++ return ret; ++ ++ buf = kzalloc(end - start, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ for (i = start; i < end; i++) { ++ ret = sg2044_efuses_read_strip(efuse, i, &value); ++ if (ret) ++ goto failed; ++ ++ memcpy(&buf[(i - start) * 4], &value, SG2044_EFUSE_ALIGN); ++ } ++ ++ memcpy(val, buf + start_offset, bytes); ++ ++failed: ++ kfree(buf); ++ ++ return ret; ++} ++ ++static int sophgo_efuses_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct sophgo_efuses *efuse; ++ struct nvmem_config config = { ++ .dev = &pdev->dev, ++ .add_legacy_fixed_of_cells = true, ++ .read_only = true, ++ .reg_read = sg2044_efuses_read, ++ .stride = 1, ++ .word_size = 1, ++ .name = "sophgo-efuse", ++ .id = NVMEM_DEVID_AUTO, ++ .root_only = true, ++ }; ++ ++ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); ++ if (!efuse) ++ return -ENOMEM; ++ ++ efuse->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(efuse->base)) ++ return PTR_ERR(efuse->base); ++ ++ efuse->num_clks = devm_clk_bulk_get_all_enabled(&pdev->dev, &efuse->clks); ++ if (efuse->num_clks < 0) ++ return dev_err_probe(dev, efuse->num_clks, "failed to get clocks\n"); ++ ++ config.priv = efuse; ++ config.size = SG2044_EFUSE_CONTENT_SIZE; ++ ++ return PTR_ERR_OR_ZERO(devm_nvmem_register(config.dev, &config)); ++} ++ ++static const struct of_device_id sophgo_efuses_of_match[] = { ++ { .compatible = "sophgo,sg2044-efuse", }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, sophgo_efuses_of_match); ++ ++static struct platform_driver sophgo_efuses_driver = { ++ .driver = { ++ .name = "sophgo_efuse", ++ .of_match_table = sophgo_efuses_of_match, ++ }, ++ .probe = sophgo_efuses_probe, ++}; ++ ++module_platform_driver(sophgo_efuses_driver); ++ ++MODULE_AUTHOR("Inochi Amaoto "); ++MODULE_DESCRIPTION("Sophgo efuse driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0443-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch b/SPECS/linux-lts/0443-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch deleted file mode 100644 index 86078006ad..0000000000 --- a/SPECS/linux-lts/0443-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch +++ /dev/null @@ -1,27 +0,0 @@ -From f541fa0b3dbdffb41fa000bff4a473af0b9f662b Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Fri, 24 Oct 2025 17:00:37 +0800 -Subject: [PATCH 443/467] REVYSR: net: stmmac: add support for dwmac 5.10a - -Signed-off-by: Han Gao -FROM: https://github.com/RevySR/linux/commit/5bc2d2af06ccd13675b8d4751226fb56bc8ee6df -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -index b9218c07eb6b..a27b2bc177af 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -@@ -59,6 +59,7 @@ static const struct of_device_id dwmac_generic_match[] = { - { .compatible = "snps,dwmac-3.72a"}, - { .compatible = "snps,dwmac-4.00"}, - { .compatible = "snps,dwmac-4.10a"}, -+ { .compatible = "snps,dwmac-5.10a"}, - { .compatible = "snps,dwmac"}, - { .compatible = "snps,dwxgmac-2.10"}, - { .compatible = "snps,dwxgmac"}, --- -2.53.0 - diff --git a/SPECS/linux-lts/0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch b/SPECS/linux-lts/0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch new file mode 100644 index 0000000000..ca1a921e5d --- /dev/null +++ b/SPECS/linux-lts/0443-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch @@ -0,0 +1,54 @@ +From 973bb367e07f78196b1e441326cbdef6c366955f Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 5 Dec 2024 13:24:13 +0800 +Subject: [RUYI PATCH] SOPHGO: riscv: dts: sophgo: sg2044: Add eFUSE device + +Add eFUSE controller node for SG2044. + +Signed-off-by: Inochi Amaoto +--- + arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ + arch/riscv/boot/dts/sophgo/sg2044.dtsi | 12 ++++++++++++ + 2 files changed, 16 insertions(+) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +index fed3d9a384a0..1b506972d465 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts ++++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +@@ -36,6 +36,10 @@ &emmc { + status = "okay"; + }; + ++&efuse0 { ++ status = "okay"; ++}; ++ + &gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; +diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +index 320c4d1d08e6..9577aae08f7f 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +@@ -408,6 +408,18 @@ sd: mmc@703000b000 { + status = "disabled"; + }; + ++ efuse0: efuse@7040000000 { ++ compatible = "sophgo,sg2044-efuse"; ++ reg = <0x70 0x40000000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&clk CLK_GATE_EFUSE>, ++ <&clk CLK_GATE_APB_EFUSE>; ++ clock-names = "core", "apb"; ++ resets = <&rst RST_EFUSE0>; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@7040005000 { + compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; + reg = <0x70 0x40005000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0444-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch b/SPECS/linux-lts/0444-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch deleted file mode 100644 index e1c1a55eec..0000000000 --- a/SPECS/linux-lts/0444-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch +++ /dev/null @@ -1,579 +0,0 @@ -From b77880a0dbc2004c552fb776369d9ee9c2e82477 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Fri, 16 May 2025 11:12:26 +0800 -Subject: [PATCH 444/467] RVCK: riscv:dts: add dp1000.dts for UltraRIsc DP1000 - SoC - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/8fa6586e8607e8f2b9bbf701a6cf282b29dac1f7 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/Makefile | 1 + - arch/riscv/boot/dts/ultrarisc/Makefile | 2 + - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 536 +++++++++++++++++++++++ - 3 files changed, 539 insertions(+) - create mode 100644 arch/riscv/boot/dts/ultrarisc/Makefile - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000.dts - -diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile -index 3763d199c70a..297b30243037 100644 ---- a/arch/riscv/boot/dts/Makefile -+++ b/arch/riscv/boot/dts/Makefile -@@ -10,3 +10,4 @@ subdir-y += sophgo - subdir-y += spacemit - subdir-y += starfive - subdir-y += thead -+subdir-y += ultrarisc -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -new file mode 100644 -index 000000000000..c27f490e2b99 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+dtb-y += dp1000.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -new file mode 100644 -index 000000000000..3eb811f73aa8 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -0,0 +1,536 @@ -+/* -+* SPDX-License-Identifier: GPL-2.0+ -+* -+* Copyright (c) 2019-2022 UltraRisc,Inc -+* -+*/ -+ -+/dts-v1/; -+ -+/ { -+ #address-cells = <0x02>; -+ #size-cells = <0x02>; -+ compatible = "ultrarisc,dp1000"; -+ model = "ultrarisc,dp1000"; -+ -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS1,115200"; -+ stdout-path = &uart1; -+ }; -+ -+ cpus { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ timebase-frequency = <10000000>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ reg = <0x00>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu0_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ reg = <0x1>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu1_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ reg = <0x2>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu2_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ reg = <0x3>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu3_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu4: cpu@4 { -+ device_type = "cpu"; -+ reg = <0x10>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu4_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu5: cpu@5 { -+ device_type = "cpu"; -+ reg = <0x11>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu5_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu6: cpu@6 { -+ device_type = "cpu"; -+ reg = <0x12>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ -+ clock-frequency = <2000000000>; -+ -+ cpu6_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu7: cpu@7 { -+ device_type = "cpu"; -+ reg = <0x13>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu7_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00 0x80000000 0x4 0x00000000>; -+ }; -+ -+ soc { -+ #address-cells = <0x02>; -+ #size-cells = <0x02>; -+ compatible = "simple-bus"; -+ ranges; -+ -+ clocks { -+ compatible = "simple-bus"; -+ u-boot,dm-pre-reloc; -+ device_clk: device_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <62500000>; -+ #clock-cells = <0>; -+ }; -+ csr_clk: csr_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <250000000>; -+ #clock-cells = <0>; -+ }; -+ }; -+ -+ clint: clint@8000000 { -+ compatible = "riscv,clint0"; -+ interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, -+ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -+ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -+ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -+ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -+ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -+ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -+ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; -+ reg = <0x00 0x8000000 0x00 0x100000>; -+ }; -+ -+ plic: plic@9000000 { -+ #interrupt-cells = <1>; -+ #address-cells = <0>; -+ phandle = <0x01>; -+ compatible = "ultrarisc,dp1000-plic"; -+ interrupt-controller; -+ interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, -+ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -+ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -+ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -+ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -+ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -+ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -+ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; -+ reg = <0x00 0x9000000 0x00 0x4000000>; -+ riscv,max-priority = <0x07>; -+ riscv,ndev = <160>; -+ }; -+ -+ uart0: serial@20300000 { -+ interrupt-parent = <0x01>; -+ interrupts = <17>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20300000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart1: serial@20310000 { -+ interrupt-parent = <0x01>; -+ interrupts = <18>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20310000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart2: serial@20400000 { -+ interrupt-parent = <0x01>; -+ interrupts = <25>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20400000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart3: serial@20410000 { -+ interrupt-parent = <0x01>; -+ interrupts = <26>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20410000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ spi0: spi@20320000 { -+ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ status = "okay"; -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ reg = <0x0 0x20320000 0x0 0x1000>; -+ interrupt-parent = <0x01>; -+ interrupts = <19>; -+ clocks = <&device_clk>; -+ clock-names = "device_clk"; -+ num-cs = <3>; -+ spi-max-frequency = <62500000>; -+ mmc0: mmc@0 { -+ compatible = "mmc-spi-slot"; -+ spi-max-frequency = <15625000>; -+ reg = <0x00>; -+ voltage-ranges = <3300 3300>; -+ disable-wp; -+ }; -+ }; -+ -+ spi1: spi@20420000 { -+ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ status = "okay"; -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ reg = <0x0 0x20420000 0x0 0x1000>; -+ interrupt-parent = <0x01>; -+ interrupts = <27>; -+ clocks = <&device_clk>; -+ clock-names = "device_clk"; -+ num-cs = <3>; -+ spi-max-frequency = <62500000>; -+ }; -+ -+ i2c0: i2c@20330000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20330000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <20>; -+ }; -+ -+ i2c1: i2c@20340000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20340000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <21>; -+ }; -+ -+ i2c2: i2c@20430000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20430000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <28>; -+ }; -+ -+ i2c3: i2c@20440000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20440000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <29>; -+ }; -+ -+ wdt0: watchdog@20210000 { -+ compatible = "snps,dw-wdt"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20210000 0x0 0x100>; -+ interrupt-parent = <0x01>; -+ interrupts = <33>; -+ clocks = <&device_clk>; -+ }; -+ -+ timer0: timer@20220000 { -+ compatible = "snps,dw-apb-timer"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20220000 0x0 0x100>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <35>; -+ status = "okay"; -+ }; -+ -+ timer1: timer@20230000 { -+ compatible = "snps,dw-apb-timer"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20230000 0x0 0x100>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <36>; -+ status = "okay"; -+ }; -+ -+ gpio: gpio@20200000 { -+ compatible = "snps,dw-apb-gpio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20200000 0x0 0x1000>; -+ clocks = <&csr_clk>, <&device_clk>; -+ clock-names = "bus", "db"; -+ status = "okay"; -+ -+ porta: gpio-port@0 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <0>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <16>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ interrupt-parent = <0x01>; -+ interrupts = <34>; -+ }; -+ -+ portb: gpio-port@1 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <1>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ -+ portc: gpio-port@2 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <2>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ -+ portd: gpio-port@3 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <3>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ }; -+ -+ ethernet1@38000000 { -+ clocks = <&csr_clk>; -+ clock-names = "stmmaceth"; -+ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; -+ interrupt-parent = <0x01>; -+ interrupts = <84>; -+ interrupt-names = "macirq"; -+ reg = <0x00 0x38000000 0x00 0x1000000>; -+ local-mac-address = [ff ff ff ff ff ff]; -+ phy-mode = "rgmii"; -+ max-speed = <1000>; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ phy-handle = <&phy0>; -+ mdio { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ compatible = "snps,dwmac-mdio"; -+ phy0: phy@0{ -+ phandle = <0x04>; -+ reg = <0x00>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ dmac: dma-controller@39000000 { -+ compatible = "snps,axi-dma-1.01a"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x39000000 0x0 0x400>; -+ clocks = <&device_clk>, <&device_clk>; -+ clock-names = "core-clk", "cfgr-clk"; -+ interrupt-parent = <0x01>; -+ interrupts = <152>; -+ #dma-cells = <1>; -+ dma-channels = <8>; -+ snps,dma-masters = <1>; -+ snps,data-width = <4>; -+ snps,block-size = <512 512 512 512 512 512 512 512>; -+ snps,priority = <0 1 2 3 4 5 6 7>; -+ snps,axi-max-burst-len = <256>; -+ }; -+ -+ pcie_x16: pcie@21000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x21000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x4fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <16>; -+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <43>, <44>, <45>, <46>, <47>, <48>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, -+ <0x0 0x0 0x0 0x2 &plic 45>, -+ <0x0 0x0 0x0 0x3 &plic 46>, -+ <0x0 0x0 0x0 0x4 &plic 47>; -+ }; -+ -+ pcie_x4a: pcie@23000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x23000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x6fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <4>; -+ ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <63>, <64>, <65>, <66>, <67>, <68>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, -+ <0x0 0x0 0x0 0x2 &plic 65>, -+ <0x0 0x0 0x0 0x3 &plic 66>, -+ <0x0 0x0 0x0 0x4 &plic 67>; -+ }; -+ -+ pcie_x4b: pcie@24000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x24000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x7fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <4>; -+ ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <73>, <74>, <75>, <76>, <77>, <78>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, -+ <0x0 0x0 0x0 0x2 &plic 75>, -+ <0x0 0x0 0x0 0x3 &plic 76>, -+ <0x0 0x0 0x0 0x4 &plic 77>; -+ }; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch b/SPECS/linux-lts/0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch new file mode 100644 index 0000000000..7551151403 --- /dev/null +++ b/SPECS/linux-lts/0444-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch @@ -0,0 +1,102 @@ +From e2ed9e487c648247b91a25cef6515dc2a54aba85 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Sun, 28 Dec 2025 23:02:15 +0800 +Subject: [RUYI PATCH] SOPHGO: dts: sg2044: Modify pcie bar address + +FROM: https://github.com/sophgo/linux-riscv/commit/efddc3e2d3d57b27054415afb522100e6dce8692 + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2044.dtsi | 28 +++++++++++++------------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +index 9577aae08f7f..f1377ee8e149 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +@@ -36,7 +36,7 @@ pcie0: pcie@6c00000000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x00000000 0x0 0x00001000>, + <0x6c 0x00300000 0x0 0x00004000>, +- <0x48 0x00000000 0x0 0x00001000>, ++ <0x50 0x00000000 0x0 0x00001000>, + <0x6c 0x000c0000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -51,11 +51,11 @@ pcie0: pcie@6c00000000 { + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, + <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, +- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, +- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x54 0x00000000 0x54 0x00000000 0x4 0x00000000>, ++ <0x03000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>; + status = "disabled"; + + pcie_intc0: interrupt-controller { +@@ -89,8 +89,8 @@ pcie1: pcie@6c00400000 { + ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>, + <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>, +- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, +- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x44 0x00000000 0x44 0x00000000 0x4 0x00000000>, ++ <0x03000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>; + status = "disabled"; + + pcie_intc1: interrupt-controller { +@@ -106,7 +106,7 @@ pcie2: pcie@6c04000000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x04000000 0x0 0x00001000>, + <0x6c 0x04300000 0x0 0x00004000>, +- <0x58 0x00000000 0x0 0x00001000>, ++ <0x7c 0x00000000 0x0 0x00001000>, + <0x6c 0x040c0000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -121,11 +121,11 @@ pcie2: pcie@6c04000000 { + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x7c 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>, + <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>, +- <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>, +- <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x7d 0x00000000 0x7d 0x00000000 0x1 0x00000000>, ++ <0x03000000 0x7c 0x80000000 0x7c 0x80000000 0x0 0x80000000>; + status = "disabled"; + + pcie_intc2: interrupt-controller { +@@ -141,7 +141,7 @@ pcie3: pcie@6c04400000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x04400000 0x0 0x00001000>, + <0x6c 0x04700000 0x0 0x00004000>, +- <0x50 0x00000000 0x0 0x00001000>, ++ <0x78 0x00000000 0x0 0x00001000>, + <0x6c 0x04780000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -156,11 +156,11 @@ pcie3: pcie@6c04400000 { + <0 0 0 3 &pcie_intc3 2>, + <0 0 0 4 &pcie_intc3 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x78 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>, + <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>, +- <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>, +- <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x79 0x00000000 0x79 0x00000000 0x1 0x00000000>, ++ <0x03000000 0x78 0x80000000 0x78 0x80000000 0x0 0x80000000>; + status = "disabled"; + + pcie_intc3: interrupt-controller { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0445-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch b/SPECS/linux-lts/0445-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch deleted file mode 100644 index 2a78270fd1..0000000000 --- a/SPECS/linux-lts/0445-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch +++ /dev/null @@ -1,881 +0,0 @@ -From 29f4764a9f5c2daf1ba382864a626abb65b50d8f Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Fri, 17 Jan 2025 19:34:48 +0800 -Subject: [PATCH 445/467] RVCK: pinctrl: add pinctrl dirver for UltraRisc - DP1000 - -support pinmux and pinconf for UltraRisc DP1000 SoC - -Signed-off-by: Jia Wang -Signed-off-by: Yanteng Si -FROM: https://github.com/RVCK-Project/rvck/commit/2fdd7d95fb0408b67353ea82e378773ebfe39ade -Signed-off-by: Han Gao ---- - drivers/pinctrl/Kconfig | 1 + - drivers/pinctrl/Makefile | 1 + - drivers/pinctrl/ultrarisc/Kconfig | 20 + - drivers/pinctrl/ultrarisc/Makefile | 4 + - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 122 +++++ - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 503 ++++++++++++++++++ - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 78 +++ - .../dt-bindings/pinctrl/ur-dp1000-pinctrl.h | 65 +++ - 8 files changed, 794 insertions(+) - create mode 100644 drivers/pinctrl/ultrarisc/Kconfig - create mode 100644 drivers/pinctrl/ultrarisc/Makefile - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h - create mode 100644 include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h - -diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig -index 4f8507ebbdac..b4ba4fb72f10 100644 ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -712,5 +712,6 @@ source "drivers/pinctrl/ti/Kconfig" - source "drivers/pinctrl/uniphier/Kconfig" - source "drivers/pinctrl/visconti/Kconfig" - source "drivers/pinctrl/vt8500/Kconfig" -+source "drivers/pinctrl/ultrarisc/Kconfig" - - endif -diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile -index e0cfb9b7c99b..32f0d988e505 100644 ---- a/drivers/pinctrl/Makefile -+++ b/drivers/pinctrl/Makefile -@@ -95,3 +95,4 @@ obj-y += ti/ - obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ - obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ - obj-$(CONFIG_ARCH_VT8500) += vt8500/ -+obj-$(CONFIG_ARCH_ULTRARISC) += ultrarisc/ -diff --git a/drivers/pinctrl/ultrarisc/Kconfig b/drivers/pinctrl/ultrarisc/Kconfig -new file mode 100644 -index 000000000000..e4db80843bea ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/Kconfig -@@ -0,0 +1,20 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config PINCTRL_ULTRARISC -+ bool -+ depends on OF -+ select PINMUX -+ select GENERIC_PINCTRL_GROUPS -+ select GENERIC_PINCONF -+ select GENERIC_PINMUX_FUNCTIONS -+ select GPIOLIB -+ select IRQ_DOMAIN_HIERARCHY -+ select MFD_SYSCON -+ -+config PINCTRL_ULTRARISC_DP1000 -+ tristate "Pinctrl driver of UltraRisc DP1000" -+ select PINCTRL_ULTRARISC -+ depends on OF && HAS_IOMEM -+ help -+ This driver configures the UltraRisc DP1000 SoC's pinctrl -+ subsystem. -diff --git a/drivers/pinctrl/ultrarisc/Makefile b/drivers/pinctrl/ultrarisc/Makefile -new file mode 100644 -index 000000000000..5bf3f449d59b ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+obj-$(CONFIG_PINCTRL_ULTRARISC) += pinctrl-ultrarisc.o -+obj-$(CONFIG_PINCTRL_ULTRARISC_DP1000) += pinctrl-ultrarisc-dp1000.o -\ No newline at end of file -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -new file mode 100644 -index 000000000000..217f671fe63a ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -0,0 +1,122 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc DP1000 pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../pinctrl-utils.h" -+#include "../pinmux.h" -+#include "../core.h" -+#include "../devicetree.h" -+ -+#include "pinctrl-ultrarisc.h" -+ -+static const struct pinctrl_pin_desc ur_dp1000_pins[] = { -+ // PA -+ PINCTRL_PIN(0, "PA0"), -+ PINCTRL_PIN(1, "PA1"), -+ PINCTRL_PIN(2, "PA2"), -+ PINCTRL_PIN(3, "PA3"), -+ PINCTRL_PIN(4, "PA4"), -+ PINCTRL_PIN(5, "PA5"), -+ PINCTRL_PIN(6, "PA6"), -+ PINCTRL_PIN(7, "PA7"), -+ PINCTRL_PIN(8, "PA8"), -+ PINCTRL_PIN(9, "PA9"), -+ PINCTRL_PIN(10, "PA10"), -+ PINCTRL_PIN(11, "PA11"), -+ PINCTRL_PIN(12, "PA12"), -+ PINCTRL_PIN(13, "PA13"), -+ PINCTRL_PIN(14, "PA14"), -+ PINCTRL_PIN(15, "PA15"), -+ // PB -+ PINCTRL_PIN(16, "PB0"), -+ PINCTRL_PIN(17, "PB1"), -+ PINCTRL_PIN(18, "PB2"), -+ PINCTRL_PIN(19, "PB3"), -+ PINCTRL_PIN(20, "PB4"), -+ PINCTRL_PIN(21, "PB5"), -+ PINCTRL_PIN(22, "PB6"), -+ PINCTRL_PIN(23, "PB7"), -+ // PC -+ PINCTRL_PIN(24, "PC0"), -+ PINCTRL_PIN(25, "PC1"), -+ PINCTRL_PIN(26, "PC2"), -+ PINCTRL_PIN(27, "PC3"), -+ PINCTRL_PIN(28, "PC4"), -+ PINCTRL_PIN(29, "PC5"), -+ PINCTRL_PIN(30, "PC6"), -+ PINCTRL_PIN(31, "PC7"), -+ // PD -+ PINCTRL_PIN(32, "PD0"), -+ PINCTRL_PIN(33, "PD1"), -+ PINCTRL_PIN(34, "PD2"), -+ PINCTRL_PIN(35, "PD3"), -+ PINCTRL_PIN(36, "PD4"), -+ PINCTRL_PIN(37, "PD5"), -+ PINCTRL_PIN(38, "PD6"), -+ PINCTRL_PIN(39, "PD7"), -+ // LPC -+ PINCTRL_PIN(40, "LPC0"), -+ PINCTRL_PIN(41, "LPC1"), -+ PINCTRL_PIN(42, "LPC2"), -+ PINCTRL_PIN(43, "LPC3"), -+ PINCTRL_PIN(44, "LPC4"), -+ PINCTRL_PIN(45, "LPC5"), -+ PINCTRL_PIN(46, "LPC6"), -+ PINCTRL_PIN(47, "LPC7"), -+ PINCTRL_PIN(48, "LPC8"), -+ PINCTRL_PIN(49, "LPC9"), -+ PINCTRL_PIN(50, "LPC10"), -+ PINCTRL_PIN(51, "LPC11"), -+ PINCTRL_PIN(52, "LPC12"), -+}; -+ -+static struct ur_pinctrl_match_data ur_dp1000_match_data = { -+ .pins = ur_dp1000_pins, -+ .npins = ARRAY_SIZE(ur_dp1000_pins), -+ .offset = 0x2c0, -+ .ports = { -+ {"A", 16, 0x2c0, 0x310}, -+ {"B", 8, 0x2c4, 0x318}, -+ {"C", 8, 0x2c8, 0x31c}, -+ {"D", 8, 0x2cc, 0x320}, -+ {"LPC", 13, 0x2d0, 0x324}, -+ }, -+}; -+ -+enum ur_dp1000_port_list { -+ PORT_A = 0, -+ PORT_B, -+ PORT_C, -+ PORT_D, -+ PORT_LPC -+}; -+ -+ -+static const struct of_device_id ur_pinctrl_of_match[] = { -+ { .compatible = "ultrarisc,dp1000-pinctrl", .data = &ur_dp1000_match_data, }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, ur_pinctrl_of_match); -+ -+static struct platform_driver ur_pinctrl_driver = { -+ .driver = { -+ .name = "ultrarisc-pinctrl-dp1000", -+ .of_match_table = ur_pinctrl_of_match, -+ }, -+ .probe = ur_pinctrl_probe, -+ .remove = ur_pinctrl_remove, -+}; -+ -+module_platform_driver(ur_pinctrl_driver); -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -new file mode 100644 -index 000000000000..667d59e0ac6e ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -0,0 +1,503 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../pinctrl-utils.h" -+#include "../pinmux.h" -+#include "../core.h" -+#include "../devicetree.h" -+ -+#include "pinctrl-ultrarisc.h" -+ -+static int ur_pin_to_desc(struct pinctrl_dev *pctldev, struct ur_pin_val *pin_val) -+{ -+ int index = 0; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ const struct ur_pinctrl_match_data *ur_match_data = ur_pinctrl->match_data; -+ -+ for (int i = 0; i < pin_val->port; i++) -+ index += ur_match_data->ports[i].npins; -+ index += pin_val->pin; -+ dev_dbg(pctldev->dev, "port %d pin %d index %d\n", pin_val->port, pin_val->pin, index); -+ return index; -+} -+ -+static int ur_subnode_to_pin(struct pinctrl_dev *pctldev, -+ const char *name, -+ enum pinctrl_map_type type, -+ struct device_node *np, -+ int **pins, -+ struct ur_pin_val **pin_val, -+ int *pin_num) -+{ -+ struct ur_pin_val *pin_vals; -+ int rows; -+ int ret = -EINVAL; -+ int *group_pins; -+ const char **pgnames; -+ -+ dev_dbg(pctldev->dev, "pinctrl node %s\n", np->name); -+ rows = pinctrl_count_index_with_args(np, name); -+ if (rows < 0) { -+ dev_err(pctldev->dev, "%s count is invalid %d\n", name, rows); -+ return rows; -+ } -+ -+ pin_vals = devm_kcalloc(pctldev->dev, rows, sizeof(*pin_vals), GFP_KERNEL); -+ if (!pin_vals) { -+ return -ENOMEM; -+ } -+ -+ group_pins = devm_kcalloc(pctldev->dev, rows, sizeof(*group_pins), GFP_KERNEL); -+ if (!group_pins) { -+ ret = -ENOMEM; -+ goto free_pin_vals; -+ } -+ -+ pgnames = devm_kzalloc(pctldev->dev, sizeof(*pgnames), GFP_KERNEL); -+ if (!pgnames) { -+ ret = -ENOMEM; -+ goto free_pins; -+ } -+ -+ for (int i = 0; i < rows; i++) { -+ struct of_phandle_args pin_args; -+ -+ ret = pinctrl_parse_index_with_args(np, name, i, &pin_args); -+ if (ret) { -+ dev_err(pctldev->dev, "parse args of %s index %d failed\n", name, i); -+ goto free_pgnames; -+ } -+ -+ if (pin_args.args_count < 3) { -+ dev_err(pctldev->dev, "invalid args_count(%d) of %s index %d/%d\n", -+ pin_args.args_count, name, i, rows); -+ ret = -EINVAL; -+ goto free_pgnames; -+ } -+ pin_vals[i].port = pin_args.args[0]; -+ pin_vals[i].pin = pin_args.args[1]; -+ pin_vals[i].mode = pin_args.args[2]; -+ -+ dev_dbg(pctldev->dev, "found a pinctrl: port=%d pin=%d val=0x%x\n", -+ pin_vals[i].port, pin_vals[i].pin, pin_vals[i].mode); -+ -+ group_pins[i] = ur_pin_to_desc(pctldev, &pin_vals[i]); -+ } -+ -+ dev_dbg(pctldev->dev, "get an pinmux of %s\n", np->name); -+ -+ ret = pinctrl_generic_add_group(pctldev, np->name, group_pins, rows, pin_vals); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "add group %s failed\n", np->name); -+ goto free_pgnames; -+ } -+ -+ *pgnames = np->name; -+ ret = pinmux_generic_add_function(pctldev, np->name, pgnames, 1, NULL); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "add function %s failed\n", np->name); -+ goto free_group; -+ } -+ -+ dev_dbg(pctldev->dev, "add group and function of %s\n", np->name); -+ -+ *pins = group_pins; -+ *pin_val = pin_vals; -+ *pin_num = rows; -+ -+ return 0; -+ -+free_group: -+ pinctrl_generic_remove_group(pctldev, ret); -+free_pgnames: -+ devm_kfree(pctldev->dev, pgnames); -+free_pins: -+ devm_kfree(pctldev->dev, group_pins); -+free_pin_vals: -+ devm_kfree(pctldev->dev, pin_vals); -+ return ret; -+} -+ -+static int ur_pinmux_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map *map) -+{ -+ int ret; -+ int *pins; -+ struct ur_pin_val *pin_vals; -+ int pin_num; -+ -+ ret = ur_subnode_to_pin(pctldev, PINMUX_PROP_NAME, PIN_MAP_TYPE_MUX_GROUP, -+ np, &pins, &pin_vals, &pin_num); -+ if (ret) { -+ dev_err(pctldev->dev, "get pinmux data %s failed\n", np->name); -+ return ret; -+ } -+ -+ map->type = PIN_MAP_TYPE_MUX_GROUP; -+ map->data.mux.group = np->name; -+ map->data.mux.function = np->name; -+ -+ dev_dbg(pctldev->dev, "type=%d, mux.group=%s, mux.function=%s\n", -+ map->type, map->data.mux.group, map->data.mux.function); -+ -+ return 0; -+} -+ -+static int ur_pinconf_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map *map) -+{ -+ int ret; -+ int *pins; -+ struct ur_pin_val *pin; -+ int pin_num; -+ -+ ret = ur_subnode_to_pin(pctldev, PINCONF_PROP_NAME, PIN_MAP_TYPE_CONFIGS_GROUP, -+ np, &pins, &pin, &pin_num); -+ if (ret) { -+ dev_err(pctldev->dev, "get pinconf data %s failed\n", np->name); -+ return ret; -+ } -+ -+ dev_dbg(pctldev->dev, "get an pinconf of %s\n", np->name); -+ map->type = PIN_MAP_TYPE_CONFIGS_GROUP; -+ map->data.configs.group_or_pin = np->name; -+ map->data.configs.configs = (unsigned long *)pin; -+ map->data.configs.num_configs = pin_num; -+ -+ dev_dbg(pctldev->dev, "type=%d, config.group_or_pin=%s, configs.num_config=%d\n", -+ map->type, map->data.configs.group_or_pin, map->data.configs.num_configs); -+ -+ return 0; -+} -+ -+static int ur_dt_node_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map **map, -+ unsigned int *num_maps) -+{ -+ int ret; -+ bool mux_present = false, conf_present = false; -+ struct pinctrl_map *new_map; -+ unsigned int map_num = 0, prop_count = 0; -+ -+ //device_get_named_child_node(pctldev->dev, np->name); -+ if (of_property_present(np, PINMUX_PROP_NAME)) { -+ mux_present = true; -+ prop_count++; -+ } -+ if (of_property_present(np, PINCONF_PROP_NAME)) { -+ conf_present = true; -+ prop_count++; -+ } -+ -+ if (!prop_count) { -+ dev_err(pctldev->dev, "no pinctrl node(%d) in %s\n", prop_count, np->name); -+ return -EINVAL; -+ } -+ -+ new_map = devm_kmalloc_array(pctldev->dev, prop_count, sizeof(**map), GFP_KERNEL); -+ if (!new_map) -+ return -ENOMEM; -+ -+ *map = new_map; -+ if (mux_present) { -+ ret = ur_pinmux_to_map(pctldev, np, new_map); -+ if (!ret) { -+ new_map++; -+ map_num++; -+ } -+ } -+ if (conf_present) { -+ ret = ur_pinconf_to_map(pctldev, np, new_map); -+ if (!ret) -+ map_num++; -+ } -+ -+ if (!map_num) { -+ dev_err(pctldev->dev, "no pinctrl info of %s failed\n", np->name); -+ goto free_map; -+ } -+ *num_maps = map_num; -+ -+ return 0; -+ -+free_map: -+ devm_kfree(pctldev->dev, new_map); -+ return ret; -+} -+ -+static void ur_dt_free_map(struct pinctrl_dev *pctldev, -+ struct pinctrl_map *map, unsigned int num_maps) -+{ -+ if (map) -+ devm_kfree(pctldev->dev, map); -+} -+ -+static void ur_pin_dbg_show(struct pinctrl_dev *pctldev, -+ struct seq_file *s, unsigned int offset) -+{ -+ seq_printf(s, "%s", dev_name(pctldev->dev)); -+} -+ -+static const struct pinctrl_ops ur_pinctrl_ops = { -+ .get_groups_count = pinctrl_generic_get_group_count, -+ .get_group_name = pinctrl_generic_get_group_name, -+ .get_group_pins = pinctrl_generic_get_group_pins, -+ .dt_node_to_map = ur_dt_node_to_map, -+ .dt_free_map = ur_dt_free_map, -+ .pin_dbg_show = ur_pin_dbg_show, -+}; -+ -+static int ur_set_pin_mux(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) -+{ -+ unsigned long flag; -+ //bool clear_mode = false; -+ void __iomem *reg; -+ u32 val; -+ const struct ur_port_desc *port; -+ -+ port = &pin_ctrl->match_data->ports[pin_vals->port]; -+ -+ reg = pin_ctrl->base + port->func_offset; -+ -+ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); -+ val = readl_relaxed(reg); -+ val &= ~((UR_FUNC0 | UR_FUNC1)<pin); -+ val |= (pin_vals->mode << pin_vals->pin); -+ writel_relaxed(val, reg); -+ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); -+ -+ return 0; -+} -+ -+static int ur_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, -+ unsigned int group_selector) -+{ -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ struct group_desc *ur_group; -+ struct ur_pin_val *pin_vals; -+ -+ dev_dbg(pctldev->dev, "set mux: func_selector=%d, group_selector=%d\n", -+ func_selector, group_selector); -+ ur_group = pinctrl_generic_get_group(pctldev, group_selector); -+ if (!ur_group) { -+ dev_err(pctldev->dev, "get group %d failed\n", group_selector); -+ return -EINVAL; -+ } -+ -+ dev_dbg(pctldev->dev, "get group %s, num_pins=%zu\n", ur_group->grp.name, ur_group->grp.npins); -+ pin_vals = ur_group->data; -+ if (!pin_vals) { -+ dev_err(pctldev->dev, "data of %s is invalid\n", ur_group->grp.name); -+ return -EINVAL; -+ } -+ -+ for (int i = 0; i < ur_group->grp.npins; i++) -+ ur_set_pin_mux(ur_pinctrl, &pin_vals[i]); -+ -+ return 0; -+} -+ -+static const struct pinmux_ops ur_pinmux_ops = { -+ .get_functions_count = pinmux_generic_get_function_count, -+ .get_function_name = pinmux_generic_get_function_name, -+ .get_function_groups = pinmux_generic_get_function_groups, -+ .set_mux = ur_set_mux, -+ .strict = true, -+}; -+ -+#define UR_CONF_BIT_PER_PIN (4) -+#define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) -+static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) -+{ -+ const struct ur_port_desc *port_desc; -+ unsigned long flag; -+ void __iomem *reg; -+ u32 val, conf; -+ -+ port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; -+ reg = pin_ctrl->base + port_desc->conf_offset; -+ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); -+ reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; -+ dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); -+ -+ conf = pin_vals->conf << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN); -+ dev_dbg(pin_ctrl->dev, "pinconf conf=0x%x\n", conf); -+ -+ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); -+ val = readl_relaxed(reg); -+ val &= ~(UR_BIAS_MASK << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN)); -+ val |= conf; -+ writel_relaxed(val, reg); -+ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); -+ dev_dbg(pin_ctrl->dev, "pinconf val=0x%x\n", val); -+ -+ return 0; -+} -+ -+static int ur_pin_config_get(struct pinctrl_dev *pctldev, -+ unsigned int pin, -+ unsigned long *config) -+{ -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d\n", __func__, __LINE__, pin); -+ // TODO: this is call by pinconf-generic -+ return -EOPNOTSUPP; -+} -+ -+static int ur_pin_config_set(struct pinctrl_dev *pctldev, -+ unsigned int pin, -+ unsigned long *configs, -+ unsigned int num_configs) -+{ -+ struct ur_pin_val *pin_conf; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", -+ __func__, __LINE__, pin, num_configs); -+ pin_conf = (struct ur_pin_val *)configs; -+ for (int i = 0; i < num_configs; i++) { -+ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -+ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ } -+ return 0; -+} -+ -+static int ur_pin_config_group_get(struct pinctrl_dev *pctldev, -+ unsigned selector, -+ unsigned long *config) -+{ -+ dev_dbg(pctldev->dev, "%s(%d): selector=%d, config=0x%lx\n", -+ __func__, __LINE__, selector, *config); -+ return -EOPNOTSUPP; -+} -+ -+static int ur_pin_config_group_set(struct pinctrl_dev *pctldev, -+ unsigned int selector, -+ unsigned long *configs, -+ unsigned int num_configs) -+{ -+ struct group_desc *ur_group; -+ struct ur_pin_val *pin_conf; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ -+ dev_dbg(pctldev->dev, "%s(%d): selector=%d, num_configs=%d\n", -+ __func__, __LINE__, selector, num_configs); -+ ur_group = pinctrl_generic_get_group(pctldev, selector); -+ if (!ur_group) { -+ dev_err(pctldev->dev, "Cannot get group by selector %d\n", selector); -+ return -EINVAL; -+ } -+ -+ dev_dbg(pctldev->dev, "get pinconf group %s\n", ur_group->grp.name); -+ pin_conf = (struct ur_pin_val *)configs; -+ for (int i = 0; i < num_configs; i++) { -+ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -+ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ } -+ return 0; -+} -+ -+static const struct pinconf_ops ur_pinconf_ops = { -+ .pin_config_get = ur_pin_config_get, -+ .pin_config_set = ur_pin_config_set, -+ .pin_config_group_get = ur_pin_config_group_get, -+ .pin_config_group_set = ur_pin_config_group_set, -+#ifdef CONFIG_GENERIC_PINCONF -+ .is_generic = true, -+#endif -+}; -+ -+int ur_pinctrl_probe(struct platform_device *pdev) -+{ -+ struct pinctrl_desc *ur_pinctrl_desc; -+ const struct ur_pinctrl_match_data *pins_data; -+ struct ur_pinctrl *ur_pinctrl; -+ int ret; -+ -+ pins_data = of_device_get_match_data(&pdev->dev); -+ if (!pins_data) -+ return -ENODEV; -+ -+ ur_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl_desc), GFP_KERNEL); -+ if (!ur_pinctrl_desc) { -+ dev_err(&pdev->dev, "pinctrl desc alloc failed\n"); -+ return -ENOMEM; -+ } -+ -+ ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); -+ if (!ur_pinctrl) { -+ dev_err(&pdev->dev, "pinctrl alloc failed\n"); -+ ret = -ENOMEM; -+ goto free_pinctrl_desc; -+ } -+ struct resource *res; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ dev_dbg(&pdev->dev, "iomem start=0x%llx\n", res->start); -+ ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(ur_pinctrl->base)) { -+ dev_err(&pdev->dev, "get ioremap resource failed\n"); -+ ret = -EINVAL; -+ goto free_pinctrl_desc; -+ } -+ dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); -+ ur_pinctrl_desc->name = dev_name(&pdev->dev); -+ ur_pinctrl_desc->owner = THIS_MODULE; -+ ur_pinctrl_desc->pins = pins_data->pins; -+ ur_pinctrl_desc->npins = pins_data->npins; -+ ur_pinctrl_desc->pctlops = &ur_pinctrl_ops; -+ ur_pinctrl_desc->pmxops = &ur_pinmux_ops; -+ ur_pinctrl_desc->confops = &ur_pinconf_ops; -+ -+ ur_pinctrl->dev = &pdev->dev; -+ ur_pinctrl->match_data = pins_data; -+ ur_pinctrl->pctl_desc = ur_pinctrl_desc; -+ raw_spin_lock_init(&ur_pinctrl->lock); -+ mutex_init(&ur_pinctrl->mutex); -+ -+ ret = devm_pinctrl_register_and_init(&pdev->dev, ur_pinctrl_desc, -+ ur_pinctrl, &ur_pinctrl->pctl_dev); -+ if (ret) { -+ dev_err(&pdev->dev, "pinctrl register failed\n"); -+ goto free_pinctrl; -+ } -+ -+ platform_set_drvdata(pdev, ur_pinctrl); -+ -+ return pinctrl_enable(ur_pinctrl->pctl_dev); -+ -+free_pinctrl: -+ devm_kfree(&pdev->dev, ur_pinctrl); -+free_pinctrl_desc: -+ devm_kfree(&pdev->dev, ur_pinctrl_desc); -+ return ret; -+} -+ -+ -+void ur_pinctrl_remove(struct platform_device *pdev) -+{ -+ struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); -+ -+ if (ur_pinctrl->pctl_dev) -+ devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); -+} -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -new file mode 100644 -index 000000000000..eec621bf8b05 ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -@@ -0,0 +1,78 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#ifndef __PINCTRL_ULTRARISC_H__ -+#define __PINCTRL_ULTRARISC_H__ -+ -+#include -+#include -+ -+#define PINMUX_PROP_NAME "pinctrl-pins" -+#define PINCONF_PROP_NAME "pinconf-pins" -+ -+struct ur_pin_conf { -+ u16 pull; -+ u16 drive; -+}; -+ -+struct ur_pin_val { -+ u32 port; -+ u32 pin; -+ union { -+ u32 mode; -+ u32 conf; -+ }; -+#define UR_FUNC_DEF 0 -+#define UR_FUNC0 1 -+#define UR_FUNC1 0x10000 -+ -+#define UR_BIAS_MASK 0x0000000F -+#define UR_PULL_MASK 0x0C -+#define UR_PULL_DIS 0 -+#define UR_PULL_UP 1 -+#define UR_PULL_DOWN 2 -+#define UR_DRIVE_MASK 0x03 -+}; -+ -+struct ur_port_desc { -+ char *name; -+ u32 npins; -+ u32 func_offset; -+ u32 conf_offset; -+}; -+ -+struct ur_pinctrl_match_data { -+ const struct pinctrl_pin_desc *pins; -+ u32 npins; -+ u32 offset; -+ //u32 conf_offset[]; -+ struct ur_port_desc ports[]; -+}; -+ -+ -+struct ur_pinctrl { -+ struct device *dev; -+ struct pinctrl_dev *pctl_dev; -+ struct pinctrl_desc *pctl_desc; -+ void __iomem *base; -+ unsigned int ngroups; -+ const char **grp_names; -+ unsigned int nbanks; -+ const struct ur_pinctrl_match_data *match_data; -+ struct regmap *regmap; -+ raw_spinlock_t lock; -+ struct mutex mutex; -+ struct pinctrl_pin_desc *pins; -+ u32 npins; -+ u32 pkg; -+}; -+ -+int ur_pinctrl_probe(struct platform_device *pdev); -+void ur_pinctrl_remove(struct platform_device *pdev); -+ -+#endif -diff --git a/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h -new file mode 100644 -index 000000000000..5bec446e2411 ---- /dev/null -+++ b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc DP1000 pinctrl header -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#ifndef __UR_DP1000_PINCTRL_H__ -+#define __UR_DP1000_PINCTRL_H__ -+ -+#define UR_DP1000_IOMUX_A 0x0 -+#define UR_DP1000_IOMUX_B 0x1 -+#define UR_DP1000_IOMUX_C 0x2 -+#define UR_DP1000_IOMUX_D 0x3 -+#define UR_DP1000_IOMUX_LPC 0x4 -+ -+#define UR_FUNC_DEF 0 -+#define UR_FUNC0 1 -+#define UR_FUNC1 0x10000 -+ -+/** -+ * port: 'A' 'B' 'C' -+ * Pin in the port -+ * pin: -+ * PA: 0 - 15 -+ * PB-PD: 0 - 7 -+ * func: -+ * UR_FUNC_DEF: default -+ * UR_FUNC0: func0 -+ * UR_FUNC1: func1 -+ */ -+#define UR_DP1000_IOPAD(port, pin, func) (port) (pin) (func) -+ -+/** -+ * Configure pull up/down resistor of the IO pin -+ * UR_PULL_DIS: disable pull-up and pull-down -+ * UR_PULL_UP: enable pull-up -+ * UR_PULL_DOWN: enable pull-down -+ */ -+#define UR_PULL_DIS 0 -+#define UR_PULL_UP 1 -+#define UR_PULL_DOWN 2 -+/** -+ * Configure drive strength of the IO pin -+ * UR_DRIVE_DEF: default value, reset value is 2 -+ * UR_DRIVE_0: 20mA -+ * UR_DRIVE_1: 27mA -+ * UR_DIRVE_2: 33mA -+ * UR_DRIVE_3: 40mA -+ */ -+#define UR_DRIVE_DEF 2 -+#define UR_DRIVE_0 0 -+#define UR_DRIVE_1 1 -+#define UR_DRIVE_2 2 -+#define UR_DRIVE_3 3 -+ -+/** -+ * Combine the pull-up/down resistor and drive strength -+ * pull: UR_PULL_DIS, UR_PULL_UP, UR_PULL_DOWN -+ * drive: UR_DRIVE_DEF, UR_DRIVE_0, UR_DRIVE_1, UR_DRIVE_2, UR_DRIVE_3 -+ */ -+#define UR_DP1000_BIAS(pull, drive) (((pull)<<2) + (drive)) -+ -+#endif --- -2.53.0 - diff --git a/SPECS/linux-lts/0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch b/SPECS/linux-lts/0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch new file mode 100644 index 0000000000..8f80489e78 --- /dev/null +++ b/SPECS/linux-lts/0445-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch @@ -0,0 +1,30 @@ +From 90bc96384294bf251a26f5f518765309821b8cd2 Mon Sep 17 00:00:00 2001 +From: Xiaoguang Xing +Date: Mon, 22 Jan 2024 10:31:30 +0800 +Subject: [RUYI PATCH] SOPHGO: riscv: sg2042: errata: Replace thead cache clean + with flush + +FROM: https://github.com/sophgo/linux-riscv/commit/9f8fdd99aae6ae8f037ad9c80b968de7c4252a65 + +Signed-off-by: Xiaoguang Xing +Signed-off-by: Han Gao +--- + arch/riscv/errata/thead/errata.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c +index fbe46f2fa8fb..9be8c45f4531 100644 +--- a/arch/riscv/errata/thead/errata.c ++++ b/arch/riscv/errata/thead/errata.c +@@ -67,7 +67,7 @@ static bool errata_probe_mae(unsigned int stage, + * 0000000 11001 00000 000 00000 0001011 + */ + #define THEAD_INVAL_A0 ".long 0x02a5000b" +-#define THEAD_CLEAN_A0 ".long 0x0295000b" ++#define THEAD_CLEAN_A0 ".long 0x02b5000b" + #define THEAD_FLUSH_A0 ".long 0x02b5000b" + #define THEAD_SYNC_S ".long 0x0190000b" + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch b/SPECS/linux-lts/0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch new file mode 100644 index 0000000000..5ca806b352 --- /dev/null +++ b/SPECS/linux-lts/0446-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch @@ -0,0 +1,131 @@ +From 283120c06a7de7f2b98715726a766cbef2459707 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Fri, 24 Oct 2025 15:59:17 +0800 +Subject: [RUYI PATCH] REVYSR: dt-bindings: net: ultrarisc,dp1000-gmac: Add + support for Ultrarisc DP1000 GMAC + +The GMAC IP on DP1000 is a standard Synopsys DesignWare MAC +(version 5.10a). + +Add necessary compatible string for this device. + +Signed-off-by: Han Gao +Signed-off-by: Han Gao +FROM: https://github.com/RevySR/linux/commit/5eda7fb5c988909f44edab38678cd124a9a5b98f +Signed-off-by: Han Gao +--- + .../devicetree/bindings/net/snps,dwmac.yaml | 1 + + .../bindings/net/ultrarisc,dp1000-gmac.yaml | 89 +++++++++++++++++++ + 2 files changed, 90 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml + +diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +index eb36cb36a57a..a8a45b844335 100644 +--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml ++++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +@@ -113,6 +113,7 @@ properties: + - starfive,jh7110-dwmac + - tesla,fsd-ethqos + - thead,th1520-gmac ++ - ultrarisc,dp1000-gmac + + reg: + minItems: 1 +diff --git a/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml +new file mode 100644 +index 000000000000..ace5c4058cc9 +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml +@@ -0,0 +1,89 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/ultrarisc,dp1000-gmac.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Ultrarisc dp1000 glue layer ++ ++maintainers: ++ - Han Gao ++ ++select: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - ultrarisc,dp1000-gmac ++ required: ++ - compatible ++ ++properties: ++ compatible: ++ oneOf: ++ - items: ++ - const: ultrarisc,dp1000-gmac ++ - const: snps,dwmac-5.10a ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: GMAC main clock ++ - description: PTP clock ++ - description: TX clock ++ ++ clock-names: ++ items: ++ - const: stmmaceth ++ ++ dma-noncoherent: true ++ ++ interrupts: ++ maxItems: 1 ++ ++ interrupt-names: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - interrupts ++ - interrupt-names ++ ++allOf: ++ - $ref: snps,dwmac.yaml# ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ ++ ethernet1@38000000 { ++ clocks = <&csr_clk>; ++ clock-names = "stmmaceth"; ++ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; ++ interrupt-parent = <0x01>; ++ interrupts = <84>; ++ interrupt-names = "macirq"; ++ reg = <0x00 0x38000000 0x00 0x1000000>; ++ local-mac-address = [ff ff ff ff ff ff]; ++ phy-mode = "rgmii"; ++ max-speed = <1000>; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ phy-handle = <&phy0>; ++ mdio { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ compatible = "snps,dwmac-mdio"; ++ phy0: phy@0{ ++ reg = <0x00>; ++ status = "okay"; ++ }; ++ }; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0446-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch b/SPECS/linux-lts/0446-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch deleted file mode 100644 index 4e043bafce..0000000000 --- a/SPECS/linux-lts/0446-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch +++ /dev/null @@ -1,237 +0,0 @@ -From 182a5e8e69bcf91baec912e83b948dfda780e9e5 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 16 Jun 2025 10:25:31 +0800 -Subject: [PATCH 446/467] RVCK: dts: add pinctrl dtsi/dts for UltraRisc DP1000 - -The newly added dtsi/dts is used to describe the pinctrl -configuration of the UltraRisc DP1000-EVB mainboard. - -Do not involve functional changes. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/e00864f9706198f8b278551217c048a140cbe39f -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 2 +- - .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 141 ++++++++++++++++++ - .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 52 +++++++ - 3 files changed, 194 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index c27f490e2b99..ef70e28e0b65 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,2 +1,2 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-y += dp1000.dtb -+dtb-y += dp1000.dtb dp1000-evb-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -new file mode 100644 -index 000000000000..be898b6df6fb ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -0,0 +1,141 @@ -+#include -+ -+/ { -+ -+ soc { -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -new file mode 100644 -index 000000000000..5ec9a39e8c34 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -0,0 +1,52 @@ -+/* -+* SPDX-License-Identifier: GPL-2.0+ -+* -+* Copyright (c) 2019-2022 UltraRisc,Inc -+* -+*/ -+ -+#include "dp1000.dts" -+#include "dp1000-evb-pinctrl.dtsi" -+#include -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch b/SPECS/linux-lts/0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch new file mode 100644 index 0000000000..271d5db9ac --- /dev/null +++ b/SPECS/linux-lts/0447-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch @@ -0,0 +1,27 @@ +From 10d617cd5ad42153be1aa390de90e0cdd8376340 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Fri, 24 Oct 2025 17:00:37 +0800 +Subject: [RUYI PATCH] REVYSR: net: stmmac: add support for dwmac 5.10a + +Signed-off-by: Han Gao +FROM: https://github.com/RevySR/linux/commit/5bc2d2af06ccd13675b8d4751226fb56bc8ee6df +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c +index b9218c07eb6b..a27b2bc177af 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c +@@ -59,6 +59,7 @@ static const struct of_device_id dwmac_generic_match[] = { + { .compatible = "snps,dwmac-3.72a"}, + { .compatible = "snps,dwmac-4.00"}, + { .compatible = "snps,dwmac-4.10a"}, ++ { .compatible = "snps,dwmac-5.10a"}, + { .compatible = "snps,dwmac"}, + { .compatible = "snps,dwxgmac-2.10"}, + { .compatible = "snps,dwxgmac"}, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0447-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch b/SPECS/linux-lts/0447-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch deleted file mode 100644 index c8897fb4ae..0000000000 --- a/SPECS/linux-lts/0447-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch +++ /dev/null @@ -1,251 +0,0 @@ -From 2faa790be1496587400ee51ba2cb7b112892e54d Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 4 Sep 2025 16:31:30 +0800 -Subject: [PATCH 447/467] RVCK: riscv: dp1000: dts: add the dts of UltraRISC - dp1000-mo-v1 board - -adds the necessary device tree files for the UltraRISC -dp1000-mo-v1 board. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/1186c972f5908717ab186cea67403c74ea03cde1 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 4 +- - .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 146 ++++++++++++++++++ - .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 60 +++++++ - 3 files changed, 209 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index ef70e28e0b65..9eac56549340 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,2 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-y += dp1000.dtb dp1000-evb-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -new file mode 100644 -index 000000000000..e82fcf2901ab ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -@@ -0,0 +1,146 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+ -+/ { -+ -+ soc { -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -new file mode 100644 -index 000000000000..a74714629566 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include "dp1000.dts" -+#include "dp1000-mo-pinctrl.dtsi" -+#include -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ -+ rtc@32 { -+ compatible = "whwave,sd3078"; -+ reg = <0x32>; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0448-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch b/SPECS/linux-lts/0448-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch deleted file mode 100644 index e3ebcd1989..0000000000 --- a/SPECS/linux-lts/0448-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch +++ /dev/null @@ -1,111 +0,0 @@ -From c88f25eebc30016da836312d9bdf40c93746a6ae Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 9 Sep 2025 15:45:52 +0800 -Subject: [PATCH 448/467] RVCK: riscv: dp1000: dts: Move mmc0 node from SoC to - board DTS - -The mmc0 node (mmc-spi-slot) is a board-level peripheral -specific to the UltraRISC DP1000 EVB V1.0, not part of the -base SoC. Move it from the SoC-level dp1000.dts to the -board-specific dp1000-evb-v1.dts to maintain proper device -tree hierarchy between SoC core and board-specific components. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/c719099661103786c877036840568c38f3d083a9 -Signed-off-by: Han Gao ---- - .../boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 9 +++++++-- - arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 16 +++++++++++----- - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 15 +++------------ - 3 files changed, 21 insertions(+), 19 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -index be898b6df6fb..e82fcf2901ab 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -1,3 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ - #include - - / { -@@ -63,8 +68,8 @@ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) - - uart0_pins: uart0_pins { - pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) - >; - - pinconf-pins = < -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 5ec9a39e8c34..34622a33e63b 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -1,9 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0 - /* --* SPDX-License-Identifier: GPL-2.0+ --* --* Copyright (c) 2019-2022 UltraRisc,Inc --* --*/ -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ - - #include "dp1000.dts" - #include "dp1000-evb-pinctrl.dtsi" -@@ -27,6 +25,14 @@ &i2c3 { - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; -+ -+ mmc0: mmc@0 { -+ compatible = "mmc-spi-slot"; -+ spi-max-frequency = <15625000>; -+ reg = <0x00>; -+ voltage-ranges = <3300 3300>; -+ disable-wp; -+ }; - }; - - &spi1 { -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 3eb811f73aa8..23a983d6a4c8 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -1,9 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0 - /* --* SPDX-License-Identifier: GPL-2.0+ --* --* Copyright (c) 2019-2022 UltraRisc,Inc --* --*/ -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ - - /dts-v1/; - -@@ -261,13 +259,6 @@ spi0: spi@20320000 { - clock-names = "device_clk"; - num-cs = <3>; - spi-max-frequency = <62500000>; -- mmc0: mmc@0 { -- compatible = "mmc-spi-slot"; -- spi-max-frequency = <15625000>; -- reg = <0x00>; -- voltage-ranges = <3300 3300>; -- disable-wp; -- }; - }; - - spi1: spi@20420000 { --- -2.53.0 - diff --git a/SPECS/linux-lts/0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch b/SPECS/linux-lts/0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch new file mode 100644 index 0000000000..9de39c75e0 --- /dev/null +++ b/SPECS/linux-lts/0448-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch @@ -0,0 +1,578 @@ +From 99ea7fd4bd1ccf2910170d8c84c997b33c948537 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 16 May 2025 11:12:26 +0800 +Subject: [RUYI PATCH] RVCK: riscv:dts: add dp1000.dts for UltraRIsc DP1000 SoC + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/8fa6586e8607e8f2b9bbf701a6cf282b29dac1f7 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/Makefile | 1 + + arch/riscv/boot/dts/ultrarisc/Makefile | 2 + + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 536 +++++++++++++++++++++++ + 3 files changed, 539 insertions(+) + create mode 100644 arch/riscv/boot/dts/ultrarisc/Makefile + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000.dts + +diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile +index 3763d199c70a..297b30243037 100644 +--- a/arch/riscv/boot/dts/Makefile ++++ b/arch/riscv/boot/dts/Makefile +@@ -10,3 +10,4 @@ subdir-y += sophgo + subdir-y += spacemit + subdir-y += starfive + subdir-y += thead ++subdir-y += ultrarisc +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +new file mode 100644 +index 000000000000..c27f490e2b99 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtb-y += dp1000.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +new file mode 100644 +index 000000000000..3eb811f73aa8 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +@@ -0,0 +1,536 @@ ++/* ++* SPDX-License-Identifier: GPL-2.0+ ++* ++* Copyright (c) 2019-2022 UltraRisc,Inc ++* ++*/ ++ ++/dts-v1/; ++ ++/ { ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ compatible = "ultrarisc,dp1000"; ++ model = "ultrarisc,dp1000"; ++ ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS1,115200"; ++ stdout-path = &uart1; ++ }; ++ ++ cpus { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ timebase-frequency = <10000000>; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ reg = <0x00>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu0_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ reg = <0x1>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu1_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu2: cpu@2 { ++ device_type = "cpu"; ++ reg = <0x2>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu2_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu3: cpu@3 { ++ device_type = "cpu"; ++ reg = <0x3>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu3_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu4: cpu@4 { ++ device_type = "cpu"; ++ reg = <0x10>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu4_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu5: cpu@5 { ++ device_type = "cpu"; ++ reg = <0x11>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu5_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu6: cpu@6 { ++ device_type = "cpu"; ++ reg = <0x12>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ ++ clock-frequency = <2000000000>; ++ ++ cpu6_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu7: cpu@7 { ++ device_type = "cpu"; ++ reg = <0x13>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu7_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ }; ++ ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x00 0x80000000 0x4 0x00000000>; ++ }; ++ ++ soc { ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ compatible = "simple-bus"; ++ ranges; ++ ++ clocks { ++ compatible = "simple-bus"; ++ u-boot,dm-pre-reloc; ++ device_clk: device_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <62500000>; ++ #clock-cells = <0>; ++ }; ++ csr_clk: csr_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <250000000>; ++ #clock-cells = <0>; ++ }; ++ }; ++ ++ clint: clint@8000000 { ++ compatible = "riscv,clint0"; ++ interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, ++ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, ++ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, ++ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, ++ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, ++ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, ++ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, ++ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; ++ reg = <0x00 0x8000000 0x00 0x100000>; ++ }; ++ ++ plic: plic@9000000 { ++ #interrupt-cells = <1>; ++ #address-cells = <0>; ++ phandle = <0x01>; ++ compatible = "ultrarisc,dp1000-plic"; ++ interrupt-controller; ++ interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, ++ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, ++ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, ++ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, ++ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, ++ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, ++ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, ++ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; ++ reg = <0x00 0x9000000 0x00 0x4000000>; ++ riscv,max-priority = <0x07>; ++ riscv,ndev = <160>; ++ }; ++ ++ uart0: serial@20300000 { ++ interrupt-parent = <0x01>; ++ interrupts = <17>; ++ clock-frequency = <62500000>; ++ current-speed = <115200>; ++ reg = <0x00 0x20300000 0x00 0x10000>; ++ compatible = "ultrarisc,dp1000-uart","ns16550"; ++ reg-offset = <0x0>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart1: serial@20310000 { ++ interrupt-parent = <0x01>; ++ interrupts = <18>; ++ clock-frequency = <62500000>; ++ current-speed = <115200>; ++ reg = <0x00 0x20310000 0x00 0x10000>; ++ compatible = "ultrarisc,dp1000-uart","ns16550"; ++ reg-offset = <0x0>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart2: serial@20400000 { ++ interrupt-parent = <0x01>; ++ interrupts = <25>; ++ clock-frequency = <62500000>; ++ current-speed = <115200>; ++ reg = <0x00 0x20400000 0x00 0x10000>; ++ compatible = "ultrarisc,dp1000-uart","ns16550"; ++ reg-offset = <0x0>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart3: serial@20410000 { ++ interrupt-parent = <0x01>; ++ interrupts = <26>; ++ clock-frequency = <62500000>; ++ current-speed = <115200>; ++ reg = <0x00 0x20410000 0x00 0x10000>; ++ compatible = "ultrarisc,dp1000-uart","ns16550"; ++ reg-offset = <0x0>; ++ reg-shift = <0x02>; ++ }; ++ ++ spi0: spi@20320000 { ++ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; ++ status = "okay"; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ reg = <0x0 0x20320000 0x0 0x1000>; ++ interrupt-parent = <0x01>; ++ interrupts = <19>; ++ clocks = <&device_clk>; ++ clock-names = "device_clk"; ++ num-cs = <3>; ++ spi-max-frequency = <62500000>; ++ mmc0: mmc@0 { ++ compatible = "mmc-spi-slot"; ++ spi-max-frequency = <15625000>; ++ reg = <0x00>; ++ voltage-ranges = <3300 3300>; ++ disable-wp; ++ }; ++ }; ++ ++ spi1: spi@20420000 { ++ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; ++ status = "okay"; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ reg = <0x0 0x20420000 0x0 0x1000>; ++ interrupt-parent = <0x01>; ++ interrupts = <27>; ++ clocks = <&device_clk>; ++ clock-names = "device_clk"; ++ num-cs = <3>; ++ spi-max-frequency = <62500000>; ++ }; ++ ++ i2c0: i2c@20330000{ ++ compatible = "snps,designware-i2c"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20330000 0x0 0x100>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <20>; ++ }; ++ ++ i2c1: i2c@20340000{ ++ compatible = "snps,designware-i2c"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20340000 0x0 0x100>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <21>; ++ }; ++ ++ i2c2: i2c@20430000{ ++ compatible = "snps,designware-i2c"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20430000 0x0 0x100>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <28>; ++ }; ++ ++ i2c3: i2c@20440000{ ++ compatible = "snps,designware-i2c"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20440000 0x0 0x100>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <29>; ++ }; ++ ++ wdt0: watchdog@20210000 { ++ compatible = "snps,dw-wdt"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20210000 0x0 0x100>; ++ interrupt-parent = <0x01>; ++ interrupts = <33>; ++ clocks = <&device_clk>; ++ }; ++ ++ timer0: timer@20220000 { ++ compatible = "snps,dw-apb-timer"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20220000 0x0 0x100>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <35>; ++ status = "okay"; ++ }; ++ ++ timer1: timer@20230000 { ++ compatible = "snps,dw-apb-timer"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20230000 0x0 0x100>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <36>; ++ status = "okay"; ++ }; ++ ++ gpio: gpio@20200000 { ++ compatible = "snps,dw-apb-gpio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20200000 0x0 0x1000>; ++ clocks = <&csr_clk>, <&device_clk>; ++ clock-names = "bus", "db"; ++ status = "okay"; ++ ++ porta: gpio-port@0 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <16>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupt-parent = <0x01>; ++ interrupts = <34>; ++ }; ++ ++ portb: gpio-port@1 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <1>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ }; ++ ++ portc: gpio-port@2 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <2>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ }; ++ ++ portd: gpio-port@3 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <3>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ }; ++ }; ++ ++ ethernet1@38000000 { ++ clocks = <&csr_clk>; ++ clock-names = "stmmaceth"; ++ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; ++ interrupt-parent = <0x01>; ++ interrupts = <84>; ++ interrupt-names = "macirq"; ++ reg = <0x00 0x38000000 0x00 0x1000000>; ++ local-mac-address = [ff ff ff ff ff ff]; ++ phy-mode = "rgmii"; ++ max-speed = <1000>; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ phy-handle = <&phy0>; ++ mdio { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ compatible = "snps,dwmac-mdio"; ++ phy0: phy@0{ ++ phandle = <0x04>; ++ reg = <0x00>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ dmac: dma-controller@39000000 { ++ compatible = "snps,axi-dma-1.01a"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x39000000 0x0 0x400>; ++ clocks = <&device_clk>, <&device_clk>; ++ clock-names = "core-clk", "cfgr-clk"; ++ interrupt-parent = <0x01>; ++ interrupts = <152>; ++ #dma-cells = <1>; ++ dma-channels = <8>; ++ snps,dma-masters = <1>; ++ snps,data-width = <4>; ++ snps,block-size = <512 512 512 512 512 512 512 512>; ++ snps,priority = <0 1 2 3 4 5 6 7>; ++ snps,axi-max-burst-len = <256>; ++ }; ++ ++ pcie_x16: pcie@21000000 { ++ compatible = "ultrarisc,dw-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x21000000 0x0 0x01000000>, /* IP registers */ ++ <0x0 0x4fff0000 0x0 0x00010000>; /* Configuration space */ ++ reg-names = "dbi", "config"; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <16>; ++ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ ++ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ ++ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ max-link-speed = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <43>, <44>, <45>, <46>, <47>, <48>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, ++ <0x0 0x0 0x0 0x2 &plic 45>, ++ <0x0 0x0 0x0 0x3 &plic 46>, ++ <0x0 0x0 0x0 0x4 &plic 47>; ++ }; ++ ++ pcie_x4a: pcie@23000000 { ++ compatible = "ultrarisc,dw-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x23000000 0x0 0x01000000>, /* IP registers */ ++ <0x0 0x6fff0000 0x0 0x00010000>; /* Configuration space */ ++ reg-names = "dbi", "config"; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <4>; ++ ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ ++ <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ ++ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ max-link-speed = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <63>, <64>, <65>, <66>, <67>, <68>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, ++ <0x0 0x0 0x0 0x2 &plic 65>, ++ <0x0 0x0 0x0 0x3 &plic 66>, ++ <0x0 0x0 0x0 0x4 &plic 67>; ++ }; ++ ++ pcie_x4b: pcie@24000000 { ++ compatible = "ultrarisc,dw-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x24000000 0x0 0x01000000>, /* IP registers */ ++ <0x0 0x7fff0000 0x0 0x00010000>; /* Configuration space */ ++ reg-names = "dbi", "config"; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <4>; ++ ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ ++ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ ++ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ max-link-speed = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <73>, <74>, <75>, <76>, <77>, <78>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, ++ <0x0 0x0 0x0 0x2 &plic 75>, ++ <0x0 0x0 0x0 0x3 &plic 76>, ++ <0x0 0x0 0x0 0x4 &plic 77>; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch b/SPECS/linux-lts/0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch new file mode 100644 index 0000000000..fad0cc8ffd --- /dev/null +++ b/SPECS/linux-lts/0449-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch @@ -0,0 +1,880 @@ +From 709a5329d0c5e869292d0fb40e080d1e280adb51 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 17 Jan 2025 19:34:48 +0800 +Subject: [RUYI PATCH] RVCK: pinctrl: add pinctrl dirver for UltraRisc DP1000 + +support pinmux and pinconf for UltraRisc DP1000 SoC + +Signed-off-by: Jia Wang +Signed-off-by: Yanteng Si +FROM: https://github.com/RVCK-Project/rvck/commit/2fdd7d95fb0408b67353ea82e378773ebfe39ade +Signed-off-by: Han Gao +--- + drivers/pinctrl/Kconfig | 1 + + drivers/pinctrl/Makefile | 1 + + drivers/pinctrl/ultrarisc/Kconfig | 20 + + drivers/pinctrl/ultrarisc/Makefile | 4 + + .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 122 +++++ + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 503 ++++++++++++++++++ + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 78 +++ + .../dt-bindings/pinctrl/ur-dp1000-pinctrl.h | 65 +++ + 8 files changed, 794 insertions(+) + create mode 100644 drivers/pinctrl/ultrarisc/Kconfig + create mode 100644 drivers/pinctrl/ultrarisc/Makefile + create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c + create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c + create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h + create mode 100644 include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h + +diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig +index 4f8507ebbdac..b4ba4fb72f10 100644 +--- a/drivers/pinctrl/Kconfig ++++ b/drivers/pinctrl/Kconfig +@@ -712,5 +712,6 @@ source "drivers/pinctrl/ti/Kconfig" + source "drivers/pinctrl/uniphier/Kconfig" + source "drivers/pinctrl/visconti/Kconfig" + source "drivers/pinctrl/vt8500/Kconfig" ++source "drivers/pinctrl/ultrarisc/Kconfig" + + endif +diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile +index e0cfb9b7c99b..32f0d988e505 100644 +--- a/drivers/pinctrl/Makefile ++++ b/drivers/pinctrl/Makefile +@@ -95,3 +95,4 @@ obj-y += ti/ + obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ + obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ + obj-$(CONFIG_ARCH_VT8500) += vt8500/ ++obj-$(CONFIG_ARCH_ULTRARISC) += ultrarisc/ +diff --git a/drivers/pinctrl/ultrarisc/Kconfig b/drivers/pinctrl/ultrarisc/Kconfig +new file mode 100644 +index 000000000000..e4db80843bea +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/Kconfig +@@ -0,0 +1,20 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config PINCTRL_ULTRARISC ++ bool ++ depends on OF ++ select PINMUX ++ select GENERIC_PINCTRL_GROUPS ++ select GENERIC_PINCONF ++ select GENERIC_PINMUX_FUNCTIONS ++ select GPIOLIB ++ select IRQ_DOMAIN_HIERARCHY ++ select MFD_SYSCON ++ ++config PINCTRL_ULTRARISC_DP1000 ++ tristate "Pinctrl driver of UltraRisc DP1000" ++ select PINCTRL_ULTRARISC ++ depends on OF && HAS_IOMEM ++ help ++ This driver configures the UltraRisc DP1000 SoC's pinctrl ++ subsystem. +diff --git a/drivers/pinctrl/ultrarisc/Makefile b/drivers/pinctrl/ultrarisc/Makefile +new file mode 100644 +index 000000000000..5bf3f449d59b +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/Makefile +@@ -0,0 +1,4 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++obj-$(CONFIG_PINCTRL_ULTRARISC) += pinctrl-ultrarisc.o ++obj-$(CONFIG_PINCTRL_ULTRARISC_DP1000) += pinctrl-ultrarisc-dp1000.o +\ No newline at end of file +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +new file mode 100644 +index 000000000000..217f671fe63a +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +@@ -0,0 +1,122 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* UltraRisc DP1000 pinctrl driver ++ * ++ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../pinctrl-utils.h" ++#include "../pinmux.h" ++#include "../core.h" ++#include "../devicetree.h" ++ ++#include "pinctrl-ultrarisc.h" ++ ++static const struct pinctrl_pin_desc ur_dp1000_pins[] = { ++ // PA ++ PINCTRL_PIN(0, "PA0"), ++ PINCTRL_PIN(1, "PA1"), ++ PINCTRL_PIN(2, "PA2"), ++ PINCTRL_PIN(3, "PA3"), ++ PINCTRL_PIN(4, "PA4"), ++ PINCTRL_PIN(5, "PA5"), ++ PINCTRL_PIN(6, "PA6"), ++ PINCTRL_PIN(7, "PA7"), ++ PINCTRL_PIN(8, "PA8"), ++ PINCTRL_PIN(9, "PA9"), ++ PINCTRL_PIN(10, "PA10"), ++ PINCTRL_PIN(11, "PA11"), ++ PINCTRL_PIN(12, "PA12"), ++ PINCTRL_PIN(13, "PA13"), ++ PINCTRL_PIN(14, "PA14"), ++ PINCTRL_PIN(15, "PA15"), ++ // PB ++ PINCTRL_PIN(16, "PB0"), ++ PINCTRL_PIN(17, "PB1"), ++ PINCTRL_PIN(18, "PB2"), ++ PINCTRL_PIN(19, "PB3"), ++ PINCTRL_PIN(20, "PB4"), ++ PINCTRL_PIN(21, "PB5"), ++ PINCTRL_PIN(22, "PB6"), ++ PINCTRL_PIN(23, "PB7"), ++ // PC ++ PINCTRL_PIN(24, "PC0"), ++ PINCTRL_PIN(25, "PC1"), ++ PINCTRL_PIN(26, "PC2"), ++ PINCTRL_PIN(27, "PC3"), ++ PINCTRL_PIN(28, "PC4"), ++ PINCTRL_PIN(29, "PC5"), ++ PINCTRL_PIN(30, "PC6"), ++ PINCTRL_PIN(31, "PC7"), ++ // PD ++ PINCTRL_PIN(32, "PD0"), ++ PINCTRL_PIN(33, "PD1"), ++ PINCTRL_PIN(34, "PD2"), ++ PINCTRL_PIN(35, "PD3"), ++ PINCTRL_PIN(36, "PD4"), ++ PINCTRL_PIN(37, "PD5"), ++ PINCTRL_PIN(38, "PD6"), ++ PINCTRL_PIN(39, "PD7"), ++ // LPC ++ PINCTRL_PIN(40, "LPC0"), ++ PINCTRL_PIN(41, "LPC1"), ++ PINCTRL_PIN(42, "LPC2"), ++ PINCTRL_PIN(43, "LPC3"), ++ PINCTRL_PIN(44, "LPC4"), ++ PINCTRL_PIN(45, "LPC5"), ++ PINCTRL_PIN(46, "LPC6"), ++ PINCTRL_PIN(47, "LPC7"), ++ PINCTRL_PIN(48, "LPC8"), ++ PINCTRL_PIN(49, "LPC9"), ++ PINCTRL_PIN(50, "LPC10"), ++ PINCTRL_PIN(51, "LPC11"), ++ PINCTRL_PIN(52, "LPC12"), ++}; ++ ++static struct ur_pinctrl_match_data ur_dp1000_match_data = { ++ .pins = ur_dp1000_pins, ++ .npins = ARRAY_SIZE(ur_dp1000_pins), ++ .offset = 0x2c0, ++ .ports = { ++ {"A", 16, 0x2c0, 0x310}, ++ {"B", 8, 0x2c4, 0x318}, ++ {"C", 8, 0x2c8, 0x31c}, ++ {"D", 8, 0x2cc, 0x320}, ++ {"LPC", 13, 0x2d0, 0x324}, ++ }, ++}; ++ ++enum ur_dp1000_port_list { ++ PORT_A = 0, ++ PORT_B, ++ PORT_C, ++ PORT_D, ++ PORT_LPC ++}; ++ ++ ++static const struct of_device_id ur_pinctrl_of_match[] = { ++ { .compatible = "ultrarisc,dp1000-pinctrl", .data = &ur_dp1000_match_data, }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ur_pinctrl_of_match); ++ ++static struct platform_driver ur_pinctrl_driver = { ++ .driver = { ++ .name = "ultrarisc-pinctrl-dp1000", ++ .of_match_table = ur_pinctrl_of_match, ++ }, ++ .probe = ur_pinctrl_probe, ++ .remove = ur_pinctrl_remove, ++}; ++ ++module_platform_driver(ur_pinctrl_driver); +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +new file mode 100644 +index 000000000000..667d59e0ac6e +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +@@ -0,0 +1,503 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* UltraRisc pinctrl driver ++ * ++ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../pinctrl-utils.h" ++#include "../pinmux.h" ++#include "../core.h" ++#include "../devicetree.h" ++ ++#include "pinctrl-ultrarisc.h" ++ ++static int ur_pin_to_desc(struct pinctrl_dev *pctldev, struct ur_pin_val *pin_val) ++{ ++ int index = 0; ++ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ const struct ur_pinctrl_match_data *ur_match_data = ur_pinctrl->match_data; ++ ++ for (int i = 0; i < pin_val->port; i++) ++ index += ur_match_data->ports[i].npins; ++ index += pin_val->pin; ++ dev_dbg(pctldev->dev, "port %d pin %d index %d\n", pin_val->port, pin_val->pin, index); ++ return index; ++} ++ ++static int ur_subnode_to_pin(struct pinctrl_dev *pctldev, ++ const char *name, ++ enum pinctrl_map_type type, ++ struct device_node *np, ++ int **pins, ++ struct ur_pin_val **pin_val, ++ int *pin_num) ++{ ++ struct ur_pin_val *pin_vals; ++ int rows; ++ int ret = -EINVAL; ++ int *group_pins; ++ const char **pgnames; ++ ++ dev_dbg(pctldev->dev, "pinctrl node %s\n", np->name); ++ rows = pinctrl_count_index_with_args(np, name); ++ if (rows < 0) { ++ dev_err(pctldev->dev, "%s count is invalid %d\n", name, rows); ++ return rows; ++ } ++ ++ pin_vals = devm_kcalloc(pctldev->dev, rows, sizeof(*pin_vals), GFP_KERNEL); ++ if (!pin_vals) { ++ return -ENOMEM; ++ } ++ ++ group_pins = devm_kcalloc(pctldev->dev, rows, sizeof(*group_pins), GFP_KERNEL); ++ if (!group_pins) { ++ ret = -ENOMEM; ++ goto free_pin_vals; ++ } ++ ++ pgnames = devm_kzalloc(pctldev->dev, sizeof(*pgnames), GFP_KERNEL); ++ if (!pgnames) { ++ ret = -ENOMEM; ++ goto free_pins; ++ } ++ ++ for (int i = 0; i < rows; i++) { ++ struct of_phandle_args pin_args; ++ ++ ret = pinctrl_parse_index_with_args(np, name, i, &pin_args); ++ if (ret) { ++ dev_err(pctldev->dev, "parse args of %s index %d failed\n", name, i); ++ goto free_pgnames; ++ } ++ ++ if (pin_args.args_count < 3) { ++ dev_err(pctldev->dev, "invalid args_count(%d) of %s index %d/%d\n", ++ pin_args.args_count, name, i, rows); ++ ret = -EINVAL; ++ goto free_pgnames; ++ } ++ pin_vals[i].port = pin_args.args[0]; ++ pin_vals[i].pin = pin_args.args[1]; ++ pin_vals[i].mode = pin_args.args[2]; ++ ++ dev_dbg(pctldev->dev, "found a pinctrl: port=%d pin=%d val=0x%x\n", ++ pin_vals[i].port, pin_vals[i].pin, pin_vals[i].mode); ++ ++ group_pins[i] = ur_pin_to_desc(pctldev, &pin_vals[i]); ++ } ++ ++ dev_dbg(pctldev->dev, "get an pinmux of %s\n", np->name); ++ ++ ret = pinctrl_generic_add_group(pctldev, np->name, group_pins, rows, pin_vals); ++ if (ret < 0) { ++ dev_err(pctldev->dev, "add group %s failed\n", np->name); ++ goto free_pgnames; ++ } ++ ++ *pgnames = np->name; ++ ret = pinmux_generic_add_function(pctldev, np->name, pgnames, 1, NULL); ++ if (ret < 0) { ++ dev_err(pctldev->dev, "add function %s failed\n", np->name); ++ goto free_group; ++ } ++ ++ dev_dbg(pctldev->dev, "add group and function of %s\n", np->name); ++ ++ *pins = group_pins; ++ *pin_val = pin_vals; ++ *pin_num = rows; ++ ++ return 0; ++ ++free_group: ++ pinctrl_generic_remove_group(pctldev, ret); ++free_pgnames: ++ devm_kfree(pctldev->dev, pgnames); ++free_pins: ++ devm_kfree(pctldev->dev, group_pins); ++free_pin_vals: ++ devm_kfree(pctldev->dev, pin_vals); ++ return ret; ++} ++ ++static int ur_pinmux_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *np, ++ struct pinctrl_map *map) ++{ ++ int ret; ++ int *pins; ++ struct ur_pin_val *pin_vals; ++ int pin_num; ++ ++ ret = ur_subnode_to_pin(pctldev, PINMUX_PROP_NAME, PIN_MAP_TYPE_MUX_GROUP, ++ np, &pins, &pin_vals, &pin_num); ++ if (ret) { ++ dev_err(pctldev->dev, "get pinmux data %s failed\n", np->name); ++ return ret; ++ } ++ ++ map->type = PIN_MAP_TYPE_MUX_GROUP; ++ map->data.mux.group = np->name; ++ map->data.mux.function = np->name; ++ ++ dev_dbg(pctldev->dev, "type=%d, mux.group=%s, mux.function=%s\n", ++ map->type, map->data.mux.group, map->data.mux.function); ++ ++ return 0; ++} ++ ++static int ur_pinconf_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *np, ++ struct pinctrl_map *map) ++{ ++ int ret; ++ int *pins; ++ struct ur_pin_val *pin; ++ int pin_num; ++ ++ ret = ur_subnode_to_pin(pctldev, PINCONF_PROP_NAME, PIN_MAP_TYPE_CONFIGS_GROUP, ++ np, &pins, &pin, &pin_num); ++ if (ret) { ++ dev_err(pctldev->dev, "get pinconf data %s failed\n", np->name); ++ return ret; ++ } ++ ++ dev_dbg(pctldev->dev, "get an pinconf of %s\n", np->name); ++ map->type = PIN_MAP_TYPE_CONFIGS_GROUP; ++ map->data.configs.group_or_pin = np->name; ++ map->data.configs.configs = (unsigned long *)pin; ++ map->data.configs.num_configs = pin_num; ++ ++ dev_dbg(pctldev->dev, "type=%d, config.group_or_pin=%s, configs.num_config=%d\n", ++ map->type, map->data.configs.group_or_pin, map->data.configs.num_configs); ++ ++ return 0; ++} ++ ++static int ur_dt_node_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *np, ++ struct pinctrl_map **map, ++ unsigned int *num_maps) ++{ ++ int ret; ++ bool mux_present = false, conf_present = false; ++ struct pinctrl_map *new_map; ++ unsigned int map_num = 0, prop_count = 0; ++ ++ //device_get_named_child_node(pctldev->dev, np->name); ++ if (of_property_present(np, PINMUX_PROP_NAME)) { ++ mux_present = true; ++ prop_count++; ++ } ++ if (of_property_present(np, PINCONF_PROP_NAME)) { ++ conf_present = true; ++ prop_count++; ++ } ++ ++ if (!prop_count) { ++ dev_err(pctldev->dev, "no pinctrl node(%d) in %s\n", prop_count, np->name); ++ return -EINVAL; ++ } ++ ++ new_map = devm_kmalloc_array(pctldev->dev, prop_count, sizeof(**map), GFP_KERNEL); ++ if (!new_map) ++ return -ENOMEM; ++ ++ *map = new_map; ++ if (mux_present) { ++ ret = ur_pinmux_to_map(pctldev, np, new_map); ++ if (!ret) { ++ new_map++; ++ map_num++; ++ } ++ } ++ if (conf_present) { ++ ret = ur_pinconf_to_map(pctldev, np, new_map); ++ if (!ret) ++ map_num++; ++ } ++ ++ if (!map_num) { ++ dev_err(pctldev->dev, "no pinctrl info of %s failed\n", np->name); ++ goto free_map; ++ } ++ *num_maps = map_num; ++ ++ return 0; ++ ++free_map: ++ devm_kfree(pctldev->dev, new_map); ++ return ret; ++} ++ ++static void ur_dt_free_map(struct pinctrl_dev *pctldev, ++ struct pinctrl_map *map, unsigned int num_maps) ++{ ++ if (map) ++ devm_kfree(pctldev->dev, map); ++} ++ ++static void ur_pin_dbg_show(struct pinctrl_dev *pctldev, ++ struct seq_file *s, unsigned int offset) ++{ ++ seq_printf(s, "%s", dev_name(pctldev->dev)); ++} ++ ++static const struct pinctrl_ops ur_pinctrl_ops = { ++ .get_groups_count = pinctrl_generic_get_group_count, ++ .get_group_name = pinctrl_generic_get_group_name, ++ .get_group_pins = pinctrl_generic_get_group_pins, ++ .dt_node_to_map = ur_dt_node_to_map, ++ .dt_free_map = ur_dt_free_map, ++ .pin_dbg_show = ur_pin_dbg_show, ++}; ++ ++static int ur_set_pin_mux(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) ++{ ++ unsigned long flag; ++ //bool clear_mode = false; ++ void __iomem *reg; ++ u32 val; ++ const struct ur_port_desc *port; ++ ++ port = &pin_ctrl->match_data->ports[pin_vals->port]; ++ ++ reg = pin_ctrl->base + port->func_offset; ++ ++ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); ++ val = readl_relaxed(reg); ++ val &= ~((UR_FUNC0 | UR_FUNC1)<pin); ++ val |= (pin_vals->mode << pin_vals->pin); ++ writel_relaxed(val, reg); ++ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); ++ ++ return 0; ++} ++ ++static int ur_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, ++ unsigned int group_selector) ++{ ++ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ struct group_desc *ur_group; ++ struct ur_pin_val *pin_vals; ++ ++ dev_dbg(pctldev->dev, "set mux: func_selector=%d, group_selector=%d\n", ++ func_selector, group_selector); ++ ur_group = pinctrl_generic_get_group(pctldev, group_selector); ++ if (!ur_group) { ++ dev_err(pctldev->dev, "get group %d failed\n", group_selector); ++ return -EINVAL; ++ } ++ ++ dev_dbg(pctldev->dev, "get group %s, num_pins=%zu\n", ur_group->grp.name, ur_group->grp.npins); ++ pin_vals = ur_group->data; ++ if (!pin_vals) { ++ dev_err(pctldev->dev, "data of %s is invalid\n", ur_group->grp.name); ++ return -EINVAL; ++ } ++ ++ for (int i = 0; i < ur_group->grp.npins; i++) ++ ur_set_pin_mux(ur_pinctrl, &pin_vals[i]); ++ ++ return 0; ++} ++ ++static const struct pinmux_ops ur_pinmux_ops = { ++ .get_functions_count = pinmux_generic_get_function_count, ++ .get_function_name = pinmux_generic_get_function_name, ++ .get_function_groups = pinmux_generic_get_function_groups, ++ .set_mux = ur_set_mux, ++ .strict = true, ++}; ++ ++#define UR_CONF_BIT_PER_PIN (4) ++#define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) ++static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) ++{ ++ const struct ur_port_desc *port_desc; ++ unsigned long flag; ++ void __iomem *reg; ++ u32 val, conf; ++ ++ port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; ++ reg = pin_ctrl->base + port_desc->conf_offset; ++ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); ++ reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; ++ dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); ++ ++ conf = pin_vals->conf << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN); ++ dev_dbg(pin_ctrl->dev, "pinconf conf=0x%x\n", conf); ++ ++ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); ++ val = readl_relaxed(reg); ++ val &= ~(UR_BIAS_MASK << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN)); ++ val |= conf; ++ writel_relaxed(val, reg); ++ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); ++ dev_dbg(pin_ctrl->dev, "pinconf val=0x%x\n", val); ++ ++ return 0; ++} ++ ++static int ur_pin_config_get(struct pinctrl_dev *pctldev, ++ unsigned int pin, ++ unsigned long *config) ++{ ++ dev_dbg(pctldev->dev, "%s(%d): pin=%d\n", __func__, __LINE__, pin); ++ // TODO: this is call by pinconf-generic ++ return -EOPNOTSUPP; ++} ++ ++static int ur_pin_config_set(struct pinctrl_dev *pctldev, ++ unsigned int pin, ++ unsigned long *configs, ++ unsigned int num_configs) ++{ ++ struct ur_pin_val *pin_conf; ++ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ ++ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", ++ __func__, __LINE__, pin, num_configs); ++ pin_conf = (struct ur_pin_val *)configs; ++ for (int i = 0; i < num_configs; i++) { ++ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", ++ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); ++ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); ++ } ++ return 0; ++} ++ ++static int ur_pin_config_group_get(struct pinctrl_dev *pctldev, ++ unsigned selector, ++ unsigned long *config) ++{ ++ dev_dbg(pctldev->dev, "%s(%d): selector=%d, config=0x%lx\n", ++ __func__, __LINE__, selector, *config); ++ return -EOPNOTSUPP; ++} ++ ++static int ur_pin_config_group_set(struct pinctrl_dev *pctldev, ++ unsigned int selector, ++ unsigned long *configs, ++ unsigned int num_configs) ++{ ++ struct group_desc *ur_group; ++ struct ur_pin_val *pin_conf; ++ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ ++ dev_dbg(pctldev->dev, "%s(%d): selector=%d, num_configs=%d\n", ++ __func__, __LINE__, selector, num_configs); ++ ur_group = pinctrl_generic_get_group(pctldev, selector); ++ if (!ur_group) { ++ dev_err(pctldev->dev, "Cannot get group by selector %d\n", selector); ++ return -EINVAL; ++ } ++ ++ dev_dbg(pctldev->dev, "get pinconf group %s\n", ur_group->grp.name); ++ pin_conf = (struct ur_pin_val *)configs; ++ for (int i = 0; i < num_configs; i++) { ++ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", ++ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); ++ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); ++ } ++ return 0; ++} ++ ++static const struct pinconf_ops ur_pinconf_ops = { ++ .pin_config_get = ur_pin_config_get, ++ .pin_config_set = ur_pin_config_set, ++ .pin_config_group_get = ur_pin_config_group_get, ++ .pin_config_group_set = ur_pin_config_group_set, ++#ifdef CONFIG_GENERIC_PINCONF ++ .is_generic = true, ++#endif ++}; ++ ++int ur_pinctrl_probe(struct platform_device *pdev) ++{ ++ struct pinctrl_desc *ur_pinctrl_desc; ++ const struct ur_pinctrl_match_data *pins_data; ++ struct ur_pinctrl *ur_pinctrl; ++ int ret; ++ ++ pins_data = of_device_get_match_data(&pdev->dev); ++ if (!pins_data) ++ return -ENODEV; ++ ++ ur_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl_desc), GFP_KERNEL); ++ if (!ur_pinctrl_desc) { ++ dev_err(&pdev->dev, "pinctrl desc alloc failed\n"); ++ return -ENOMEM; ++ } ++ ++ ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); ++ if (!ur_pinctrl) { ++ dev_err(&pdev->dev, "pinctrl alloc failed\n"); ++ ret = -ENOMEM; ++ goto free_pinctrl_desc; ++ } ++ struct resource *res; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dev_dbg(&pdev->dev, "iomem start=0x%llx\n", res->start); ++ ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(ur_pinctrl->base)) { ++ dev_err(&pdev->dev, "get ioremap resource failed\n"); ++ ret = -EINVAL; ++ goto free_pinctrl_desc; ++ } ++ dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); ++ ur_pinctrl_desc->name = dev_name(&pdev->dev); ++ ur_pinctrl_desc->owner = THIS_MODULE; ++ ur_pinctrl_desc->pins = pins_data->pins; ++ ur_pinctrl_desc->npins = pins_data->npins; ++ ur_pinctrl_desc->pctlops = &ur_pinctrl_ops; ++ ur_pinctrl_desc->pmxops = &ur_pinmux_ops; ++ ur_pinctrl_desc->confops = &ur_pinconf_ops; ++ ++ ur_pinctrl->dev = &pdev->dev; ++ ur_pinctrl->match_data = pins_data; ++ ur_pinctrl->pctl_desc = ur_pinctrl_desc; ++ raw_spin_lock_init(&ur_pinctrl->lock); ++ mutex_init(&ur_pinctrl->mutex); ++ ++ ret = devm_pinctrl_register_and_init(&pdev->dev, ur_pinctrl_desc, ++ ur_pinctrl, &ur_pinctrl->pctl_dev); ++ if (ret) { ++ dev_err(&pdev->dev, "pinctrl register failed\n"); ++ goto free_pinctrl; ++ } ++ ++ platform_set_drvdata(pdev, ur_pinctrl); ++ ++ return pinctrl_enable(ur_pinctrl->pctl_dev); ++ ++free_pinctrl: ++ devm_kfree(&pdev->dev, ur_pinctrl); ++free_pinctrl_desc: ++ devm_kfree(&pdev->dev, ur_pinctrl_desc); ++ return ret; ++} ++ ++ ++void ur_pinctrl_remove(struct platform_device *pdev) ++{ ++ struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); ++ ++ if (ur_pinctrl->pctl_dev) ++ devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); ++} +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +new file mode 100644 +index 000000000000..eec621bf8b05 +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +@@ -0,0 +1,78 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* UltraRisc pinctrl driver ++ * ++ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#ifndef __PINCTRL_ULTRARISC_H__ ++#define __PINCTRL_ULTRARISC_H__ ++ ++#include ++#include ++ ++#define PINMUX_PROP_NAME "pinctrl-pins" ++#define PINCONF_PROP_NAME "pinconf-pins" ++ ++struct ur_pin_conf { ++ u16 pull; ++ u16 drive; ++}; ++ ++struct ur_pin_val { ++ u32 port; ++ u32 pin; ++ union { ++ u32 mode; ++ u32 conf; ++ }; ++#define UR_FUNC_DEF 0 ++#define UR_FUNC0 1 ++#define UR_FUNC1 0x10000 ++ ++#define UR_BIAS_MASK 0x0000000F ++#define UR_PULL_MASK 0x0C ++#define UR_PULL_DIS 0 ++#define UR_PULL_UP 1 ++#define UR_PULL_DOWN 2 ++#define UR_DRIVE_MASK 0x03 ++}; ++ ++struct ur_port_desc { ++ char *name; ++ u32 npins; ++ u32 func_offset; ++ u32 conf_offset; ++}; ++ ++struct ur_pinctrl_match_data { ++ const struct pinctrl_pin_desc *pins; ++ u32 npins; ++ u32 offset; ++ //u32 conf_offset[]; ++ struct ur_port_desc ports[]; ++}; ++ ++ ++struct ur_pinctrl { ++ struct device *dev; ++ struct pinctrl_dev *pctl_dev; ++ struct pinctrl_desc *pctl_desc; ++ void __iomem *base; ++ unsigned int ngroups; ++ const char **grp_names; ++ unsigned int nbanks; ++ const struct ur_pinctrl_match_data *match_data; ++ struct regmap *regmap; ++ raw_spinlock_t lock; ++ struct mutex mutex; ++ struct pinctrl_pin_desc *pins; ++ u32 npins; ++ u32 pkg; ++}; ++ ++int ur_pinctrl_probe(struct platform_device *pdev); ++void ur_pinctrl_remove(struct platform_device *pdev); ++ ++#endif +diff --git a/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h +new file mode 100644 +index 000000000000..5bec446e2411 +--- /dev/null ++++ b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h +@@ -0,0 +1,65 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* UltraRisc DP1000 pinctrl header ++ * ++ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#ifndef __UR_DP1000_PINCTRL_H__ ++#define __UR_DP1000_PINCTRL_H__ ++ ++#define UR_DP1000_IOMUX_A 0x0 ++#define UR_DP1000_IOMUX_B 0x1 ++#define UR_DP1000_IOMUX_C 0x2 ++#define UR_DP1000_IOMUX_D 0x3 ++#define UR_DP1000_IOMUX_LPC 0x4 ++ ++#define UR_FUNC_DEF 0 ++#define UR_FUNC0 1 ++#define UR_FUNC1 0x10000 ++ ++/** ++ * port: 'A' 'B' 'C' ++ * Pin in the port ++ * pin: ++ * PA: 0 - 15 ++ * PB-PD: 0 - 7 ++ * func: ++ * UR_FUNC_DEF: default ++ * UR_FUNC0: func0 ++ * UR_FUNC1: func1 ++ */ ++#define UR_DP1000_IOPAD(port, pin, func) (port) (pin) (func) ++ ++/** ++ * Configure pull up/down resistor of the IO pin ++ * UR_PULL_DIS: disable pull-up and pull-down ++ * UR_PULL_UP: enable pull-up ++ * UR_PULL_DOWN: enable pull-down ++ */ ++#define UR_PULL_DIS 0 ++#define UR_PULL_UP 1 ++#define UR_PULL_DOWN 2 ++/** ++ * Configure drive strength of the IO pin ++ * UR_DRIVE_DEF: default value, reset value is 2 ++ * UR_DRIVE_0: 20mA ++ * UR_DRIVE_1: 27mA ++ * UR_DIRVE_2: 33mA ++ * UR_DRIVE_3: 40mA ++ */ ++#define UR_DRIVE_DEF 2 ++#define UR_DRIVE_0 0 ++#define UR_DRIVE_1 1 ++#define UR_DRIVE_2 2 ++#define UR_DRIVE_3 3 ++ ++/** ++ * Combine the pull-up/down resistor and drive strength ++ * pull: UR_PULL_DIS, UR_PULL_UP, UR_PULL_DOWN ++ * drive: UR_DRIVE_DEF, UR_DRIVE_0, UR_DRIVE_1, UR_DRIVE_2, UR_DRIVE_3 ++ */ ++#define UR_DP1000_BIAS(pull, drive) (((pull)<<2) + (drive)) ++ ++#endif +-- +2.53.0 + diff --git a/SPECS/linux-lts/0449-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch b/SPECS/linux-lts/0449-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch deleted file mode 100644 index 67053738ec..0000000000 --- a/SPECS/linux-lts/0449-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch +++ /dev/null @@ -1,78 +0,0 @@ -From b8a01535a0fbc907f912f8d76412850ef78416a8 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 18 Sep 2025 10:44:01 +0800 -Subject: [PATCH 449/467] RVCK: riscv: dp1000: plic: add plic early init - supports - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - -------------------------------------------------- - -Add PLIC early init supports and remove invalid -timer nodes in dp1000.dts. - -Signed-off-by: Jia Wang -From: https://github.com/RVCK-Project/rvck/commit/9e4cfbdf46fad772cc002c53b9e295cda600e9c5 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 25 ++---------------------- - drivers/irqchip/irq-sifive-plic.c | 1 + - 2 files changed, 3 insertions(+), 23 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 23a983d6a4c8..4a2dae602693 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -164,6 +164,7 @@ device_clk: device_clk { - clock-frequency = <62500000>; - #clock-cells = <0>; - }; -+ - csr_clk: csr_clk { - compatible = "fixed-clock"; - clock-frequency = <250000000>; -@@ -333,29 +334,7 @@ wdt0: watchdog@20210000 { - interrupts = <33>; - clocks = <&device_clk>; - }; -- -- timer0: timer@20220000 { -- compatible = "snps,dw-apb-timer"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x20220000 0x0 0x100>; -- clocks = <&device_clk>; -- interrupt-parent = <0x01>; -- interrupts = <35>; -- status = "okay"; -- }; -- -- timer1: timer@20230000 { -- compatible = "snps,dw-apb-timer"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x20230000 0x0 0x100>; -- clocks = <&device_clk>; -- interrupt-parent = <0x01>; -- interrupts = <36>; -- status = "okay"; -- }; -- -+ - gpio: gpio@20200000 { - compatible = "snps,dw-apb-gpio"; - #address-cells = <1>; -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index 70058871d2fb..007a4668f9e5 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -846,3 +846,4 @@ static int __init plic_early_probe(struct device_node *node, - } - - IRQCHIP_DECLARE(riscv, "allwinner,sun20i-d1-plic", plic_early_probe); -+IRQCHIP_DECLARE(ultrarisc_dp1000_plic, "ultrarisc,dp1000-plic", plic_early_probe); --- -2.53.0 - diff --git a/SPECS/linux-lts/0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch b/SPECS/linux-lts/0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch new file mode 100644 index 0000000000..935589d38c --- /dev/null +++ b/SPECS/linux-lts/0450-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch @@ -0,0 +1,237 @@ +From c3b99eaa70d3c031fe29c503b85abb31e02d50a4 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Mon, 16 Jun 2025 10:25:31 +0800 +Subject: [RUYI PATCH] RVCK: dts: add pinctrl dtsi/dts for UltraRisc DP1000 + +The newly added dtsi/dts is used to describe the pinctrl +configuration of the UltraRisc DP1000-EVB mainboard. + +Do not involve functional changes. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/e00864f9706198f8b278551217c048a140cbe39f +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 2 +- + .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 141 ++++++++++++++++++ + .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 52 +++++++ + 3 files changed, 194 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index c27f490e2b99..ef70e28e0b65 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,2 +1,2 @@ + # SPDX-License-Identifier: GPL-2.0 +-dtb-y += dp1000.dtb ++dtb-y += dp1000.dtb dp1000-evb-v1.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +new file mode 100644 +index 000000000000..be898b6df6fb +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +@@ -0,0 +1,141 @@ ++#include ++ ++/ { ++ ++ soc { ++ pmx0: pinmux@11081000 { ++ compatible = "ultrarisc,dp1000-pinctrl"; ++ reg = <0x0 0x11081000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #pinctrl-cells = <2>; ++ pinctrl-single,register-width = <32>; ++ pinctrl-single,function-mask = <0x3ff>; ++ pinctrl-use-default; ++ ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +new file mode 100644 +index 000000000000..5ec9a39e8c34 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +@@ -0,0 +1,52 @@ ++/* ++* SPDX-License-Identifier: GPL-2.0+ ++* ++* Copyright (c) 2019-2022 UltraRisc,Inc ++* ++*/ ++ ++#include "dp1000.dts" ++#include "dp1000-evb-pinctrl.dtsi" ++#include ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0450-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch b/SPECS/linux-lts/0450-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch deleted file mode 100644 index fbb0fe8e41..0000000000 --- a/SPECS/linux-lts/0450-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch +++ /dev/null @@ -1,85 +0,0 @@ -From c2b729c99b333e2485660b66669d1415bfd256bb Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 10 Nov 2025 16:11:12 +0800 -Subject: [PATCH 450/467] RVCK: riscv: dp1000: dts: Move chosen node from - common to board-specific DTS - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -This commit moves the chosen node configuration from the -common dp1000.dts file to the respective board-specific -DTS files. - -This change allows each board to specify its own console -configuration while keeping the common SoC definitions clean. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/db5745be89ee881ff18a7ded0bcff1c2f495becf -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 7 +++++++ - arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 7 +++++++ - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 7 +------ - 3 files changed, 15 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 34622a33e63b..34d024a083fc 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -7,6 +7,13 @@ - #include "dp1000-evb-pinctrl.dtsi" - #include - -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS1,115200"; -+ stdout-path = &uart1; -+ }; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -index a74714629566..8c532e5b71a3 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -7,6 +7,13 @@ - #include "dp1000-mo-pinctrl.dtsi" - #include - -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS0,115200"; -+ stdout-path = &uart0; -+ }; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 4a2dae602693..128293c0af1f 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -10,12 +10,7 @@ / { - #size-cells = <0x02>; - compatible = "ultrarisc,dp1000"; - model = "ultrarisc,dp1000"; -- -- chosen { -- bootargs = "earlycon=sbi console=ttyS1,115200"; -- stdout-path = &uart1; -- }; -- -+ - cpus { - #address-cells = <0x01>; - #size-cells = <0x00>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0451-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch b/SPECS/linux-lts/0451-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch deleted file mode 100644 index bd085b039a..0000000000 --- a/SPECS/linux-lts/0451-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch +++ /dev/null @@ -1,677 +0,0 @@ -From 03de28a6f7321aa6b3f914c0547661e9c15e62cc Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 11 Nov 2025 17:03:37 +0800 -Subject: [PATCH 451/467] RVCK: dts: riscv: ultrarisc: Refactor DP1000 device - tree files - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Add gpio-ranges property to all gpio/portX nodes. -This property maps GPIO lines to pin controller pins, -ensuring proper GPIO pin allocation and management. - -Convert dp1000.dts to a common include file (dp1000.dtsi) and update -the board-specific DTS files to include it. This refactoring allows -for better code reuse across different DP1000-based boards (EVB, MO, -and Titan variants) while maintaining board-specific configurations. - -The changes include: -- Renaming dp1000.dts to dp1000.dtsi -- Updating board-specific DTS files to include the common .dtsi -- Adjusting Makefile to reflect these changes -- Updating pinctrl files for all board variants - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/f9d4926fccee70f72d11e11dfa11b99f59caa947 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 1 - - .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 261 +++++++++--------- - .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 1 - - .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 261 +++++++++--------- - .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 1 - - .../dts/ultrarisc/{dp1000.dts => dp1000.dtsi} | 15 + - 6 files changed, 263 insertions(+), 277 deletions(-) - rename arch/riscv/boot/dts/ultrarisc/{dp1000.dts => dp1000.dtsi} (96%) - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index 9eac56549340..22c03b44b2f8 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,4 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -index e82fcf2901ab..e2c09d5bdb20 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -4,143 +4,130 @@ - */ - - #include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ UR_DP1000_IOMUX_D 6 UR_FUNC1 -+ UR_DP1000_IOMUX_D 7 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; - --/ { -- -- soc { -- pmx0: pinmux@11081000 { -- compatible = "ultrarisc,dp1000-pinctrl"; -- reg = <0x0 0x11081000 0x0 0x1000>; -- #address-cells = <1>; -- #size-cells = <0>; -- #pinctrl-cells = <2>; -- pinctrl-single,register-width = <32>; -- pinctrl-single,function-mask = <0x3ff>; -- pinctrl-use-default; -- -- i2c0_pins: i2c0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c1_pins: i2c1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c2_pins: i2c2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c3_pins: i2c3_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart0_pins: uart0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart1_pins: uart1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart2_pins: uart2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi0_pins: spi0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi1_pins: spi1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- }; -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; - }; - }; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 34d024a083fc..46fe457b5f52 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -3,7 +3,6 @@ - * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. - */ - --#include "dp1000.dts" - #include "dp1000-evb-pinctrl.dtsi" - #include - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -index e82fcf2901ab..85b013f66bbd 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -@@ -4,143 +4,130 @@ - */ - - #include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ UR_DP1000_IOMUX_D 6 UR_FUNC1 -+ UR_DP1000_IOMUX_D 7 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; - --/ { -- -- soc { -- pmx0: pinmux@11081000 { -- compatible = "ultrarisc,dp1000-pinctrl"; -- reg = <0x0 0x11081000 0x0 0x1000>; -- #address-cells = <1>; -- #size-cells = <0>; -- #pinctrl-cells = <2>; -- pinctrl-single,register-width = <32>; -- pinctrl-single,function-mask = <0x3ff>; -- pinctrl-use-default; -- -- i2c0_pins: i2c0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c1_pins: i2c1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c2_pins: i2c2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c3_pins: i2c3_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart0_pins: uart0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart1_pins: uart1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart2_pins: uart2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi0_pins: spi0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi1_pins: spi1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- }; -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; - }; - }; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -index 8c532e5b71a3..dc057cbaf59b 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -3,7 +3,6 @@ - * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. - */ - --#include "dp1000.dts" - #include "dp1000-mo-pinctrl.dtsi" - #include - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -similarity index 96% -rename from arch/riscv/boot/dts/ultrarisc/dp1000.dts -rename to arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index 128293c0af1f..a25e87e15553 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -330,6 +330,17 @@ wdt0: watchdog@20210000 { - clocks = <&device_clk>; - }; - -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ }; -+ - gpio: gpio@20200000 { - compatible = "snps,dw-apb-gpio"; - #address-cells = <1>; -@@ -349,6 +360,7 @@ porta: gpio-port@0 { - #interrupt-cells = <2>; - interrupt-parent = <0x01>; - interrupts = <34>; -+ gpio-ranges = <&pmx0 0 0 16>; - }; - - portb: gpio-port@1 { -@@ -357,6 +369,7 @@ portb: gpio-port@1 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 16 0 8>; - }; - - portc: gpio-port@2 { -@@ -365,6 +378,7 @@ portc: gpio-port@2 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 24 0 8>; - }; - - portd: gpio-port@3 { -@@ -373,6 +387,7 @@ portd: gpio-port@3 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 32 0 8>; - }; - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch b/SPECS/linux-lts/0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch new file mode 100644 index 0000000000..dfeb639386 --- /dev/null +++ b/SPECS/linux-lts/0451-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch @@ -0,0 +1,251 @@ +From 6e08f5227680fcb9eef599c73c6a48dbba8d8f66 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Thu, 4 Sep 2025 16:31:30 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: add the dts of UltraRISC + dp1000-mo-v1 board + +adds the necessary device tree files for the UltraRISC +dp1000-mo-v1 board. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/1186c972f5908717ab186cea67403c74ea03cde1 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 4 +- + .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 146 ++++++++++++++++++ + .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 60 +++++++ + 3 files changed, 209 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index ef70e28e0b65..9eac56549340 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,2 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 +-dtb-y += dp1000.dtb dp1000-evb-v1.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +new file mode 100644 +index 000000000000..e82fcf2901ab +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +@@ -0,0 +1,146 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include ++ ++/ { ++ ++ soc { ++ pmx0: pinmux@11081000 { ++ compatible = "ultrarisc,dp1000-pinctrl"; ++ reg = <0x0 0x11081000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #pinctrl-cells = <2>; ++ pinctrl-single,register-width = <32>; ++ pinctrl-single,function-mask = <0x3ff>; ++ pinctrl-use-default; ++ ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +new file mode 100644 +index 000000000000..a74714629566 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +@@ -0,0 +1,60 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000.dts" ++#include "dp1000-mo-pinctrl.dtsi" ++#include ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ ++ rtc@32 { ++ compatible = "whwave,sd3078"; ++ reg = <0x32>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch b/SPECS/linux-lts/0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch new file mode 100644 index 0000000000..ee76518537 --- /dev/null +++ b/SPECS/linux-lts/0452-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch @@ -0,0 +1,111 @@ +From b9ce7c71ab1aae741d95ad74bd380256a79a7de3 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 9 Sep 2025 15:45:52 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: Move mmc0 node from SoC to + board DTS + +The mmc0 node (mmc-spi-slot) is a board-level peripheral +specific to the UltraRISC DP1000 EVB V1.0, not part of the +base SoC. Move it from the SoC-level dp1000.dts to the +board-specific dp1000-evb-v1.dts to maintain proper device +tree hierarchy between SoC core and board-specific components. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/c719099661103786c877036840568c38f3d083a9 +Signed-off-by: Han Gao +--- + .../boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 9 +++++++-- + arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 16 +++++++++++----- + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 15 +++------------ + 3 files changed, 21 insertions(+), 19 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +index be898b6df6fb..e82fcf2901ab 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +@@ -1,3 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ + #include + + / { +@@ -63,8 +68,8 @@ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) + + uart0_pins: uart0_pins { + pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) + >; + + pinconf-pins = < +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +index 5ec9a39e8c34..34622a33e63b 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +@@ -1,9 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0 + /* +-* SPDX-License-Identifier: GPL-2.0+ +-* +-* Copyright (c) 2019-2022 UltraRisc,Inc +-* +-*/ ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ + + #include "dp1000.dts" + #include "dp1000-evb-pinctrl.dtsi" +@@ -27,6 +25,14 @@ &i2c3 { + &spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; ++ ++ mmc0: mmc@0 { ++ compatible = "mmc-spi-slot"; ++ spi-max-frequency = <15625000>; ++ reg = <0x00>; ++ voltage-ranges = <3300 3300>; ++ disable-wp; ++ }; + }; + + &spi1 { +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +index 3eb811f73aa8..23a983d6a4c8 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +@@ -1,9 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0 + /* +-* SPDX-License-Identifier: GPL-2.0+ +-* +-* Copyright (c) 2019-2022 UltraRisc,Inc +-* +-*/ ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ + + /dts-v1/; + +@@ -261,13 +259,6 @@ spi0: spi@20320000 { + clock-names = "device_clk"; + num-cs = <3>; + spi-max-frequency = <62500000>; +- mmc0: mmc@0 { +- compatible = "mmc-spi-slot"; +- spi-max-frequency = <15625000>; +- reg = <0x00>; +- voltage-ranges = <3300 3300>; +- disable-wp; +- }; + }; + + spi1: spi@20420000 { +-- +2.53.0 + diff --git a/SPECS/linux-lts/0452-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch b/SPECS/linux-lts/0452-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch deleted file mode 100644 index 0bc0730651..0000000000 --- a/SPECS/linux-lts/0452-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 9990048297fff986d79fe3f64e82e5f0856461e4 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Wed, 12 Nov 2025 15:43:27 +0800 -Subject: [PATCH 452/467] RVCK: riscv: pinctrl: ultrarisc: Implement pin - configuration support - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Update ur_pin_config_set() to use the new configuration handling logic. -This allows the driver to properly handle standard Linux kernel pin -configuration parameters such as PIN_CONFIG_BIAS_PULL_UP, -PIN_CONFIG_BIAS_PULL_DOWN, etc. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/d094389a972a4b03d04b77a47c19f5c9c9fb0627 -Signed-off-by: Han Gao ---- - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 + - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 83 +++++++++++++++++-- - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 2 +- - 3 files changed, 77 insertions(+), 9 deletions(-) - -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -index 217f671fe63a..6a7496a465d8 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -86,6 +86,7 @@ static struct ur_pinctrl_match_data ur_dp1000_match_data = { - .pins = ur_dp1000_pins, - .npins = ARRAY_SIZE(ur_dp1000_pins), - .offset = 0x2c0, -+ .num_ports = 5, - .ports = { - {"A", 16, 0x2c0, 0x310}, - {"B", 8, 0x2c4, 0x318}, -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -index 667d59e0ac6e..edaeca881af7 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -326,6 +326,58 @@ static const struct pinmux_ops ur_pinmux_ops = { - - #define UR_CONF_BIT_PER_PIN (4) - #define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) -+ -+static int ur_pin_num_to_port_pin(const struct ur_pinctrl_match_data *match_data, -+ struct ur_pin_val *pin_val, u32 pin_num) -+{ -+ const struct ur_port_desc *port_desc; -+ -+ for (int i = 0; i < match_data->num_ports; i++) { -+ port_desc = &match_data->ports[i]; -+ if (pin_num < port_desc->npins) { -+ pin_val->port = i; -+ pin_val->pin = pin_num; -+ pin_val->conf = 0; -+ return 0; -+ } -+ pin_num -= port_desc->npins; -+ } -+ return -EINVAL; -+} -+ -+static int ur_config_to_pin_val(struct ur_pinctrl *pin_ctrl, -+ struct ur_pin_val *pin_vals, -+ unsigned long *config) -+{ -+ enum pin_config_param param = pinconf_to_config_param(*config); -+ u32 arg = pinconf_to_config_argument(*config); -+ -+ dev_dbg(pin_ctrl->dev, "%s(%d): config_to_pin_val: param=%d, arg=0x%x\n", -+ __func__, __LINE__, param, arg); -+ -+ switch (param) { -+ case PIN_CONFIG_BIAS_DISABLE: -+ pin_vals->conf &= ~UR_BIAS_MASK; -+ break; -+ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: -+ pin_vals->conf &= ~(UR_PULL_DOWN | UR_PULL_UP); -+ break; -+ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: -+ case PIN_CONFIG_BIAS_PULL_DOWN: -+ pin_vals->conf |= UR_PULL_DOWN; -+ break; -+ case PIN_CONFIG_BIAS_PULL_UP: -+ pin_vals->conf |= UR_PULL_UP; -+ break; -+ case PIN_CONFIG_DRIVE_PUSH_PULL: -+ case PIN_CONFIG_PERSIST_STATE: -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ return 0; -+} -+ - static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) - { - const struct ur_port_desc *port_desc; -@@ -334,8 +386,11 @@ static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_v - u32 val, conf; - - port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; -+ dev_dbg(pin_ctrl->dev, "set pinconf port=%d pin=%d conf=0x%x\n", -+ pin_vals->port, pin_vals->pin, pin_vals->conf); - reg = pin_ctrl->base + port_desc->conf_offset; -- dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); -+ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, conf_offset=0x%x, reg=0x%llx\n", -+ (u64)pin_ctrl->base, port_desc->conf_offset, (u64)reg); - reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; - dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); - -@@ -367,16 +422,28 @@ static int ur_pin_config_set(struct pinctrl_dev *pctldev, - unsigned long *configs, - unsigned int num_configs) - { -- struct ur_pin_val *pin_conf; -+ struct ur_pin_val pin_val; - struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ int ret; -+ -+ ret = ur_pin_num_to_port_pin(ur_pinctrl->match_data, &pin_val, pin); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "invalid pin number %d\n", pin); -+ return ret; -+ } -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d, port=%d, pin=%d\n", -+ __func__, __LINE__, pin, num_configs, pin_val.port, pin_val.pin); - -- dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", -- __func__, __LINE__, pin, num_configs); -- pin_conf = (struct ur_pin_val *)configs; - for (int i = 0; i < num_configs; i++) { -- dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -- i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -- ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ ret = ur_config_to_pin_val(ur_pinctrl, &pin_val, &configs[i]); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "invalid config 0x%lx\n", configs[i]); -+ return ret; -+ } -+ -+ dev_dbg(pctldev->dev, "%s(%d): port=%d, pin=%d, conf=0x%x\n", -+ __func__, __LINE__, pin_val.port, pin_val.pin, pin_val.conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_val); - } - return 0; - } -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -index eec621bf8b05..728b2111def0 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -@@ -50,7 +50,7 @@ struct ur_pinctrl_match_data { - const struct pinctrl_pin_desc *pins; - u32 npins; - u32 offset; -- //u32 conf_offset[]; -+ u32 num_ports; - struct ur_port_desc ports[]; - }; - --- -2.53.0 - diff --git a/SPECS/linux-lts/0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch b/SPECS/linux-lts/0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch new file mode 100644 index 0000000000..2e0d7ad5ce --- /dev/null +++ b/SPECS/linux-lts/0453-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch @@ -0,0 +1,77 @@ +From 2e69e921113ca412333654bea99e8cde384f3780 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Thu, 18 Sep 2025 10:44:01 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dp1000: plic: add plic early init supports + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +------------------------------------------------- + +Add PLIC early init supports and remove invalid +timer nodes in dp1000.dts. + +Signed-off-by: Jia Wang +From: https://github.com/RVCK-Project/rvck/commit/9e4cfbdf46fad772cc002c53b9e295cda600e9c5 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 25 ++---------------------- + drivers/irqchip/irq-sifive-plic.c | 1 + + 2 files changed, 3 insertions(+), 23 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +index 23a983d6a4c8..4a2dae602693 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +@@ -164,6 +164,7 @@ device_clk: device_clk { + clock-frequency = <62500000>; + #clock-cells = <0>; + }; ++ + csr_clk: csr_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; +@@ -333,29 +334,7 @@ wdt0: watchdog@20210000 { + interrupts = <33>; + clocks = <&device_clk>; + }; +- +- timer0: timer@20220000 { +- compatible = "snps,dw-apb-timer"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x20220000 0x0 0x100>; +- clocks = <&device_clk>; +- interrupt-parent = <0x01>; +- interrupts = <35>; +- status = "okay"; +- }; +- +- timer1: timer@20230000 { +- compatible = "snps,dw-apb-timer"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x20230000 0x0 0x100>; +- clocks = <&device_clk>; +- interrupt-parent = <0x01>; +- interrupts = <36>; +- status = "okay"; +- }; +- ++ + gpio: gpio@20200000 { + compatible = "snps,dw-apb-gpio"; + #address-cells = <1>; +diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c +index 70058871d2fb..007a4668f9e5 100644 +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -846,3 +846,4 @@ static int __init plic_early_probe(struct device_node *node, + } + + IRQCHIP_DECLARE(riscv, "allwinner,sun20i-d1-plic", plic_early_probe); ++IRQCHIP_DECLARE(ultrarisc_dp1000_plic, "ultrarisc,dp1000-plic", plic_early_probe); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0453-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch b/SPECS/linux-lts/0453-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch deleted file mode 100644 index 1eed92849d..0000000000 --- a/SPECS/linux-lts/0453-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch +++ /dev/null @@ -1,364 +0,0 @@ -From fbad2c8916d16de5ce5963b7dcc776529371ad4c Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 18 Nov 2025 13:48:49 +0800 -Subject: [PATCH 453/467] RVCK: riscv: dts: dp1000: add dts/dtsi for Milk-V - Titan board based on UltraRISC DP1000 SoC - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Add dp1000-titan-v1.dts and dp1000-titan-pinctrl.dtsi for the Milk-V Titan -board. The Titan board is designed by Milk-V and is based on the UltraRISC -DP1000 SoC. These device tree files provide the initial support for the -board, including pinctrl and basic peripheral configuration. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/edab885e252d0442ccf52b2b554934138b82b2ec -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 1 + - .../dts/ultrarisc/dp1000-titan-pinctrl.dtsi | 173 ++++++++++++++++++ - .../boot/dts/ultrarisc/dp1000-titan-v1.dts | 139 ++++++++++++++ - 3 files changed, 313 insertions(+) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index 22c03b44b2f8..df8efe1a3ed7 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-titan-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi -new file mode 100644 -index 000000000000..35429e539832 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi -@@ -0,0 +1,173 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart3_pins: uart3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 6 UR_FUNC0 -+ UR_DP1000_IOMUX_C 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ UR_DP1000_IOMUX_A 4 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ gpios_pin: gpios_pin { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 10 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 11 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 14 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 15 UR_FUNC_DEF -+ -+ UR_DP1000_IOMUX_B 0 UR_FUNC_DEF -+ UR_DP1000_IOMUX_B 1 UR_FUNC_DEF -+ UR_DP1000_IOMUX_B 2 UR_FUNC_DEF -+ -+ UR_DP1000_IOMUX_D 6 UR_FUNC_DEF -+ UR_DP1000_IOMUX_D 7 UR_FUNC_DEF -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 10 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 11 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 14 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 15 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ -+ UR_DP1000_IOMUX_B 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts -new file mode 100644 -index 000000000000..2cbdfa2ad813 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts -@@ -0,0 +1,139 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include "dp1000-titan-pinctrl.dtsi" -+#include -+#include -+#include -+#include -+ -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS0,115200"; -+ stdout-path = &uart0; -+ }; -+ -+ gpio-poweroff { -+ compatible = "gpio-poweroff"; -+ gpios = <&portb 0 GPIO_ACTIVE_LOW>; -+ active-delay-ms = <100>; -+ line-name = "power-off"; -+ status = "okay"; -+ }; -+ -+ gpio-restart { -+ compatible = "gpio-restart"; -+ gpios = <&portb 1 GPIO_ACTIVE_LOW>; -+ active-delay-ms = <100>; -+ line-name = "reset-system"; -+ status = "okay"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ -+ key-wakeup { -+ label = "Wake-Up"; -+ gpios = <&porta 14 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ linux,input-type = ; -+ debounce-interval = <10>; -+ wakeup-source; -+ wakeup-event-action = ; -+ }; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ -+ rtc@68 { -+ compatible = "st,m41t11"; -+ reg = <0x68>; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart3_pins>; -+}; -+ -+&porta { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpios_pin>; -+ -+ i2c1-mux-hog { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ /* LOW: DCDC(U6) connect MCU(EC) -+ * HIGH: DCDC(U6) connect CPU -+ */ -+ output-low; -+ line-name = "gpio-mux-dcdc"; -+ }; -+ -+ i2c3-mux-hog { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_LOW>; -+ /* LOW: CPU i2c3 connect nvme -+ * HIGH: CPU i2c3 connect pciex16 -+ */ -+ output-low; -+ line-name = "gpio-mux-i2c3"; -+ }; -+ -+ uart0-mux-hog { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ /* LOW: uart_debug connect BMC -+ * HIGH: uart_debug connect CPU -+ */ -+ output-high; -+ line-name = "gpio-mux-debug"; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux-lts/0454-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch b/SPECS/linux-lts/0454-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch deleted file mode 100644 index 600e84fb7f..0000000000 --- a/SPECS/linux-lts/0454-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch +++ /dev/null @@ -1,77 +0,0 @@ -From a5bc9efc302578399318b126b9ad08dc8f2925c9 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Mon, 23 Feb 2026 14:35:29 +0800 -Subject: [PATCH 454/467] REVYSR: pinctrl: ultrarisc: cleanup probe&remove - -Signed-off-by: Han Gao ---- - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 - - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 22 +++---------------- - 2 files changed, 3 insertions(+), 20 deletions(-) - -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -index 6a7496a465d8..0ead138c9d1f 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -117,7 +117,6 @@ static struct platform_driver ur_pinctrl_driver = { - .of_match_table = ur_pinctrl_of_match, - }, - .probe = ur_pinctrl_probe, -- .remove = ur_pinctrl_remove, - }; - - module_platform_driver(ur_pinctrl_driver); -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -index edaeca881af7..cdd7160f3183 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -514,8 +514,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); - if (!ur_pinctrl) { - dev_err(&pdev->dev, "pinctrl alloc failed\n"); -- ret = -ENOMEM; -- goto free_pinctrl_desc; -+ return -ENOMEM; - } - struct resource *res; - -@@ -524,8 +523,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(ur_pinctrl->base)) { - dev_err(&pdev->dev, "get ioremap resource failed\n"); -- ret = -EINVAL; -- goto free_pinctrl_desc; -+ return -EINVAL; - } - dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); - ur_pinctrl_desc->name = dev_name(&pdev->dev); -@@ -546,25 +544,11 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl, &ur_pinctrl->pctl_dev); - if (ret) { - dev_err(&pdev->dev, "pinctrl register failed\n"); -- goto free_pinctrl; -+ return ret; - } - - platform_set_drvdata(pdev, ur_pinctrl); - - return pinctrl_enable(ur_pinctrl->pctl_dev); -- --free_pinctrl: -- devm_kfree(&pdev->dev, ur_pinctrl); --free_pinctrl_desc: -- devm_kfree(&pdev->dev, ur_pinctrl_desc); -- return ret; - } - -- --void ur_pinctrl_remove(struct platform_device *pdev) --{ -- struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); -- -- if (ur_pinctrl->pctl_dev) -- devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); --} --- -2.53.0 - diff --git a/SPECS/linux-lts/0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch b/SPECS/linux-lts/0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch new file mode 100644 index 0000000000..87e90bc15e --- /dev/null +++ b/SPECS/linux-lts/0454-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch @@ -0,0 +1,85 @@ +From c95a87c3fe519649f8470396461cd19be68bb138 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Mon, 10 Nov 2025 16:11:12 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: Move chosen node from common + to board-specific DTS + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +-------------------------------- + +This commit moves the chosen node configuration from the +common dp1000.dts file to the respective board-specific +DTS files. + +This change allows each board to specify its own console +configuration while keeping the common SoC definitions clean. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/db5745be89ee881ff18a7ded0bcff1c2f495becf +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 7 +++++++ + arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 7 +++++++ + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 7 +------ + 3 files changed, 15 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +index 34622a33e63b..34d024a083fc 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +@@ -7,6 +7,13 @@ + #include "dp1000-evb-pinctrl.dtsi" + #include + ++/ { ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS1,115200"; ++ stdout-path = &uart1; ++ }; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +index a74714629566..8c532e5b71a3 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +@@ -7,6 +7,13 @@ + #include "dp1000-mo-pinctrl.dtsi" + #include + ++/ { ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS0,115200"; ++ stdout-path = &uart0; ++ }; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +index 4a2dae602693..128293c0af1f 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +@@ -10,12 +10,7 @@ / { + #size-cells = <0x02>; + compatible = "ultrarisc,dp1000"; + model = "ultrarisc,dp1000"; +- +- chosen { +- bootargs = "earlycon=sbi console=ttyS1,115200"; +- stdout-path = &uart1; +- }; +- ++ + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0455-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch b/SPECS/linux-lts/0455-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch deleted file mode 100644 index 02ee603e78..0000000000 --- a/SPECS/linux-lts/0455-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch +++ /dev/null @@ -1,46 +0,0 @@ -From e8065f872b91db0f8430308a5dd01266928a98d9 Mon Sep 17 00:00:00 2001 -From: U2FsdGVkX1 -Date: Sun, 29 Mar 2026 15:31:14 +0000 -Subject: [PATCH 455/467] REVYSR: riscv: dp1000: dts: use ultrarisc,dp1000-pcie - for PCIe nodes - -Signed-off-by: U2FsdGVkX1 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index a25e87e15553..78e0cda1fcb9 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -436,7 +436,7 @@ dmac: dma-controller@39000000 { - }; - - pcie_x16: pcie@21000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; -@@ -462,7 +462,7 @@ pcie_x16: pcie@21000000 { - }; - - pcie_x4a: pcie@23000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; -@@ -488,7 +488,7 @@ pcie_x4a: pcie@23000000 { - }; - - pcie_x4b: pcie@24000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch b/SPECS/linux-lts/0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch new file mode 100644 index 0000000000..47458b4dd9 --- /dev/null +++ b/SPECS/linux-lts/0455-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch @@ -0,0 +1,677 @@ +From efed87f8a357dd6937ae5011627de96daf2e7029 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 11 Nov 2025 17:03:37 +0800 +Subject: [RUYI PATCH] RVCK: dts: riscv: ultrarisc: Refactor DP1000 device tree + files + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +-------------------------------- + +Add gpio-ranges property to all gpio/portX nodes. +This property maps GPIO lines to pin controller pins, +ensuring proper GPIO pin allocation and management. + +Convert dp1000.dts to a common include file (dp1000.dtsi) and update +the board-specific DTS files to include it. This refactoring allows +for better code reuse across different DP1000-based boards (EVB, MO, +and Titan variants) while maintaining board-specific configurations. + +The changes include: +- Renaming dp1000.dts to dp1000.dtsi +- Updating board-specific DTS files to include the common .dtsi +- Adjusting Makefile to reflect these changes +- Updating pinctrl files for all board variants + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/f9d4926fccee70f72d11e11dfa11b99f59caa947 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 1 - + .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 261 +++++++++--------- + .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 1 - + .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 261 +++++++++--------- + .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 1 - + .../dts/ultrarisc/{dp1000.dts => dp1000.dtsi} | 15 + + 6 files changed, 263 insertions(+), 277 deletions(-) + rename arch/riscv/boot/dts/ultrarisc/{dp1000.dts => dp1000.dtsi} (96%) + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index 9eac56549340..22c03b44b2f8 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,4 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +index e82fcf2901ab..e2c09d5bdb20 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +@@ -4,143 +4,130 @@ + */ + + #include ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 12 UR_FUNC0 ++ UR_DP1000_IOMUX_A 13 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 6 UR_FUNC0 ++ UR_DP1000_IOMUX_B 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 0 UR_FUNC0 ++ UR_DP1000_IOMUX_C 1 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 2 UR_FUNC0 ++ UR_DP1000_IOMUX_C 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 8 UR_FUNC1 ++ UR_DP1000_IOMUX_A 9 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 4 UR_FUNC0 ++ UR_DP1000_IOMUX_B 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 4 UR_FUNC0 ++ UR_DP1000_IOMUX_C 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_D 0 UR_FUNC1 ++ UR_DP1000_IOMUX_D 1 UR_FUNC1 ++ UR_DP1000_IOMUX_D 2 UR_FUNC1 ++ UR_DP1000_IOMUX_D 3 UR_FUNC1 ++ UR_DP1000_IOMUX_D 4 UR_FUNC1 ++ UR_DP1000_IOMUX_D 5 UR_FUNC1 ++ UR_DP1000_IOMUX_D 6 UR_FUNC1 ++ UR_DP1000_IOMUX_D 7 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; + +-/ { +- +- soc { +- pmx0: pinmux@11081000 { +- compatible = "ultrarisc,dp1000-pinctrl"; +- reg = <0x0 0x11081000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <2>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x3ff>; +- pinctrl-use-default; +- +- i2c0_pins: i2c0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c1_pins: i2c1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c2_pins: i2c2_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c3_pins: i2c3_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart0_pins: uart0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart1_pins: uart1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart2_pins: uart2_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- spi0_pins: spi0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- spi1_pins: spi1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- }; ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 0 UR_FUNC0 ++ UR_DP1000_IOMUX_A 1 UR_FUNC0 ++ UR_DP1000_IOMUX_A 2 UR_FUNC0 ++ UR_DP1000_IOMUX_A 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; + }; + }; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +index 34d024a083fc..46fe457b5f52 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +@@ -3,7 +3,6 @@ + * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +-#include "dp1000.dts" + #include "dp1000-evb-pinctrl.dtsi" + #include + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +index e82fcf2901ab..85b013f66bbd 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +@@ -4,143 +4,130 @@ + */ + + #include ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 12 UR_FUNC0 ++ UR_DP1000_IOMUX_A 13 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 6 UR_FUNC0 ++ UR_DP1000_IOMUX_B 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 0 UR_FUNC0 ++ UR_DP1000_IOMUX_C 1 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 2 UR_FUNC0 ++ UR_DP1000_IOMUX_C 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 8 UR_FUNC1 ++ UR_DP1000_IOMUX_A 9 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 4 UR_FUNC0 ++ UR_DP1000_IOMUX_B 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 4 UR_FUNC0 ++ UR_DP1000_IOMUX_C 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_D 0 UR_FUNC1 ++ UR_DP1000_IOMUX_D 1 UR_FUNC1 ++ UR_DP1000_IOMUX_D 2 UR_FUNC1 ++ UR_DP1000_IOMUX_D 3 UR_FUNC1 ++ UR_DP1000_IOMUX_D 4 UR_FUNC1 ++ UR_DP1000_IOMUX_D 5 UR_FUNC1 ++ UR_DP1000_IOMUX_D 6 UR_FUNC1 ++ UR_DP1000_IOMUX_D 7 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; + +-/ { +- +- soc { +- pmx0: pinmux@11081000 { +- compatible = "ultrarisc,dp1000-pinctrl"; +- reg = <0x0 0x11081000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <2>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x3ff>; +- pinctrl-use-default; +- +- i2c0_pins: i2c0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c1_pins: i2c1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c2_pins: i2c2_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c3_pins: i2c3_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart0_pins: uart0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart1_pins: uart1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart2_pins: uart2_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- spi0_pins: spi0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- spi1_pins: spi1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- }; ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 0 UR_FUNC0 ++ UR_DP1000_IOMUX_A 1 UR_FUNC0 ++ UR_DP1000_IOMUX_A 2 UR_FUNC0 ++ UR_DP1000_IOMUX_A 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; + }; + }; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +index 8c532e5b71a3..dc057cbaf59b 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +@@ -3,7 +3,6 @@ + * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +-#include "dp1000.dts" + #include "dp1000-mo-pinctrl.dtsi" + #include + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +similarity index 96% +rename from arch/riscv/boot/dts/ultrarisc/dp1000.dts +rename to arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +index 128293c0af1f..a25e87e15553 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +@@ -330,6 +330,17 @@ wdt0: watchdog@20210000 { + clocks = <&device_clk>; + }; + ++ pmx0: pinmux@11081000 { ++ compatible = "ultrarisc,dp1000-pinctrl"; ++ reg = <0x0 0x11081000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #pinctrl-cells = <2>; ++ pinctrl-single,register-width = <32>; ++ pinctrl-single,function-mask = <0x3ff>; ++ pinctrl-use-default; ++ }; ++ + gpio: gpio@20200000 { + compatible = "snps,dw-apb-gpio"; + #address-cells = <1>; +@@ -349,6 +360,7 @@ porta: gpio-port@0 { + #interrupt-cells = <2>; + interrupt-parent = <0x01>; + interrupts = <34>; ++ gpio-ranges = <&pmx0 0 0 16>; + }; + + portb: gpio-port@1 { +@@ -357,6 +369,7 @@ portb: gpio-port@1 { + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 16 0 8>; + }; + + portc: gpio-port@2 { +@@ -365,6 +378,7 @@ portc: gpio-port@2 { + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 24 0 8>; + }; + + portd: gpio-port@3 { +@@ -373,6 +387,7 @@ portd: gpio-port@3 { + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 32 0 8>; + }; + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch b/SPECS/linux-lts/0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch new file mode 100644 index 0000000000..ebf2263e4c --- /dev/null +++ b/SPECS/linux-lts/0456-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch @@ -0,0 +1,166 @@ +From bae8242b84b2c9409608fced96e355aa782dfcd8 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Wed, 12 Nov 2025 15:43:27 +0800 +Subject: [RUYI PATCH] RVCK: riscv: pinctrl: ultrarisc: Implement pin + configuration support + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +-------------------------------- + +Update ur_pin_config_set() to use the new configuration handling logic. +This allows the driver to properly handle standard Linux kernel pin +configuration parameters such as PIN_CONFIG_BIAS_PULL_UP, +PIN_CONFIG_BIAS_PULL_DOWN, etc. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/d094389a972a4b03d04b77a47c19f5c9c9fb0627 +Signed-off-by: Han Gao +--- + .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 + + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 83 +++++++++++++++++-- + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 2 +- + 3 files changed, 77 insertions(+), 9 deletions(-) + +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +index 217f671fe63a..6a7496a465d8 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +@@ -86,6 +86,7 @@ static struct ur_pinctrl_match_data ur_dp1000_match_data = { + .pins = ur_dp1000_pins, + .npins = ARRAY_SIZE(ur_dp1000_pins), + .offset = 0x2c0, ++ .num_ports = 5, + .ports = { + {"A", 16, 0x2c0, 0x310}, + {"B", 8, 0x2c4, 0x318}, +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +index 667d59e0ac6e..edaeca881af7 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +@@ -326,6 +326,58 @@ static const struct pinmux_ops ur_pinmux_ops = { + + #define UR_CONF_BIT_PER_PIN (4) + #define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) ++ ++static int ur_pin_num_to_port_pin(const struct ur_pinctrl_match_data *match_data, ++ struct ur_pin_val *pin_val, u32 pin_num) ++{ ++ const struct ur_port_desc *port_desc; ++ ++ for (int i = 0; i < match_data->num_ports; i++) { ++ port_desc = &match_data->ports[i]; ++ if (pin_num < port_desc->npins) { ++ pin_val->port = i; ++ pin_val->pin = pin_num; ++ pin_val->conf = 0; ++ return 0; ++ } ++ pin_num -= port_desc->npins; ++ } ++ return -EINVAL; ++} ++ ++static int ur_config_to_pin_val(struct ur_pinctrl *pin_ctrl, ++ struct ur_pin_val *pin_vals, ++ unsigned long *config) ++{ ++ enum pin_config_param param = pinconf_to_config_param(*config); ++ u32 arg = pinconf_to_config_argument(*config); ++ ++ dev_dbg(pin_ctrl->dev, "%s(%d): config_to_pin_val: param=%d, arg=0x%x\n", ++ __func__, __LINE__, param, arg); ++ ++ switch (param) { ++ case PIN_CONFIG_BIAS_DISABLE: ++ pin_vals->conf &= ~UR_BIAS_MASK; ++ break; ++ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: ++ pin_vals->conf &= ~(UR_PULL_DOWN | UR_PULL_UP); ++ break; ++ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: ++ case PIN_CONFIG_BIAS_PULL_DOWN: ++ pin_vals->conf |= UR_PULL_DOWN; ++ break; ++ case PIN_CONFIG_BIAS_PULL_UP: ++ pin_vals->conf |= UR_PULL_UP; ++ break; ++ case PIN_CONFIG_DRIVE_PUSH_PULL: ++ case PIN_CONFIG_PERSIST_STATE: ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ return 0; ++} ++ + static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) + { + const struct ur_port_desc *port_desc; +@@ -334,8 +386,11 @@ static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_v + u32 val, conf; + + port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; ++ dev_dbg(pin_ctrl->dev, "set pinconf port=%d pin=%d conf=0x%x\n", ++ pin_vals->port, pin_vals->pin, pin_vals->conf); + reg = pin_ctrl->base + port_desc->conf_offset; +- dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); ++ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, conf_offset=0x%x, reg=0x%llx\n", ++ (u64)pin_ctrl->base, port_desc->conf_offset, (u64)reg); + reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; + dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); + +@@ -367,16 +422,28 @@ static int ur_pin_config_set(struct pinctrl_dev *pctldev, + unsigned long *configs, + unsigned int num_configs) + { +- struct ur_pin_val *pin_conf; ++ struct ur_pin_val pin_val; + struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ int ret; ++ ++ ret = ur_pin_num_to_port_pin(ur_pinctrl->match_data, &pin_val, pin); ++ if (ret < 0) { ++ dev_err(pctldev->dev, "invalid pin number %d\n", pin); ++ return ret; ++ } ++ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d, port=%d, pin=%d\n", ++ __func__, __LINE__, pin, num_configs, pin_val.port, pin_val.pin); + +- dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", +- __func__, __LINE__, pin, num_configs); +- pin_conf = (struct ur_pin_val *)configs; + for (int i = 0; i < num_configs; i++) { +- dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", +- i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); +- ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); ++ ret = ur_config_to_pin_val(ur_pinctrl, &pin_val, &configs[i]); ++ if (ret < 0) { ++ dev_err(pctldev->dev, "invalid config 0x%lx\n", configs[i]); ++ return ret; ++ } ++ ++ dev_dbg(pctldev->dev, "%s(%d): port=%d, pin=%d, conf=0x%x\n", ++ __func__, __LINE__, pin_val.port, pin_val.pin, pin_val.conf); ++ ur_set_pin_conf(ur_pinctrl, &pin_val); + } + return 0; + } +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +index eec621bf8b05..728b2111def0 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +@@ -50,7 +50,7 @@ struct ur_pinctrl_match_data { + const struct pinctrl_pin_desc *pins; + u32 npins; + u32 offset; +- //u32 conf_offset[]; ++ u32 num_ports; + struct ur_port_desc ports[]; + }; + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0456-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch b/SPECS/linux-lts/0456-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch deleted file mode 100644 index cff95295c4..0000000000 --- a/SPECS/linux-lts/0456-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch +++ /dev/null @@ -1,451 +0,0 @@ -From 02e4c1a0f94cd44c90eee6410e5cf4484bb234a2 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 13 Feb 2025 15:50:12 +0800 -Subject: [PATCH 456/467] ULTRARISC: hwmon: add corepvt driver of UltraRISC - DP1000 - -From: https://github.com/ultrarisc/linux-6.8.0/commit/2cb818e1179844847d3be752b978a4ee7e633bc3 - -UltraRISC Corepvt driver supports cluster voltage -and core temperature detection - -Signed-off-by: Jia Wang -Signed-off-by: Han Gao ---- - drivers/hwmon/Kconfig | 9 + - drivers/hwmon/Makefile | 1 + - drivers/hwmon/corepvt-ultrarisc.c | 390 ++++++++++++++++++++++++++++++ - 3 files changed, 400 insertions(+) - create mode 100644 drivers/hwmon/corepvt-ultrarisc.c - -diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig -index 2a71b6e834b0..2a44030c7796 100644 ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -503,6 +503,15 @@ config SENSORS_CHIPCAP2 - To compile this driver as a module, choose M here: the module - will be called chipcap2. - -+config SENSORS_COREPVT_ULTRARISC -+ tristate "UltraRISC Core Voltage, Temperature sensor driver" -+ help -+ If you say yes here you get support for UltraRISC Core PVT sensor -+ embedded into the SoC. -+ -+ This driver can also be built as a module. If so, the module will be -+ called corepvt-ultrarisc. -+ - config SENSORS_CORSAIR_CPRO - tristate "Corsair Commander Pro controller" - depends on HID -diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile -index 73b2abdcc6dd..6cf5fac80b7b 100644 ---- a/drivers/hwmon/Makefile -+++ b/drivers/hwmon/Makefile -@@ -61,6 +61,7 @@ obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o - obj-$(CONFIG_SENSORS_BT1_PVT) += bt1-pvt.o - obj-$(CONFIG_SENSORS_CGBC) += cgbc-hwmon.o - obj-$(CONFIG_SENSORS_CHIPCAP2) += chipcap2.o -+obj-$(CONFIG_SENSORS_COREPVT_ULTRARISC) += corepvt-ultrarisc.o - obj-$(CONFIG_SENSORS_CORETEMP) += coretemp.o - obj-$(CONFIG_SENSORS_CORSAIR_CPRO) += corsair-cpro.o - obj-$(CONFIG_SENSORS_CORSAIR_PSU) += corsair-psu.o -diff --git a/drivers/hwmon/corepvt-ultrarisc.c b/drivers/hwmon/corepvt-ultrarisc.c -new file mode 100644 -index 000000000000..3674eedefbda ---- /dev/null -+++ b/drivers/hwmon/corepvt-ultrarisc.c -@@ -0,0 +1,390 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Driver for UltraRISC Core PVT -+ * -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define COREPVT_CHL_OFFSET 0x1000 -+#define COREPVT_REG_CIR 0x0 -+#define COREPVT_REG_PSCR 0x04 -+#define COREPVT_REG_CFDR 0x08 -+#define COREPVT_REG_DOR 0x0C -+#define COREPVT_REG_ICR 0x10 -+#define COREPVT_REG_IER 0x14 -+#define COREPVT_REG_IMSR 0x18 -+#define COREPVT_REG_IRSR 0x1C -+ -+#define PVT_MAX_CHANNEL 64 -+#define PVT_TRIM_DEFAULT 0x7 -+ -+struct corepvt_channel_config { -+ const char *label; -+ u32 trim; -+}; -+ -+struct corepvt_cal_data { -+ u32 val_offset; -+ u32 val_lsb; -+}; -+ -+struct corepvt_data { -+ const struct hwmon_chip_info *chip_info; -+ u64 temp_chl_mask; -+ u64 vol_chl_mask; -+}; -+ -+struct corepvt_hwmon { -+ struct device *dev; -+ struct device *hwmon; -+ -+ void __iomem *regs; -+ int irq; -+ int clk_freq; -+ int channels; -+ const struct hwmon_chip_info *chip_info; -+ struct corepvt_channel_config config[PVT_MAX_CHANNEL]; -+ const struct corepvt_data *pvt_data; -+ raw_spinlock_t lock; -+}; -+ -+#define COREPVT_VOLTAGE_DATA_BASE 2065100 /* 2065.1 */ -+#define COREPVT_VOLTAGE_LSB 1682 /* 1.682 mV */ -+#define COREPVT_TEMP_DATA_BASE 27049000 /* 2704.9 */ -+#define COREPVT_TEMP_LSB 22632 /* 2.2632 Celsius */ -+ -+static int corepvt_read_vol(struct corepvt_hwmon *pvt, -+ int channel, long *val) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ u32 dout; -+ u32 chl_offset = 0; -+ -+ // Assume that the voltage channel is continuous -+ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ *val = ((long)dout * 1000 - COREPVT_VOLTAGE_DATA_BASE) / COREPVT_VOLTAGE_LSB; -+ -+ return 0; -+} -+ -+static int corepvt_read_temp(struct corepvt_hwmon *pvt, -+ int channel, long *val) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ u32 dout; -+ u32 chl_offset = 0; -+ -+ // Assume that the temperature channel is continuous -+ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ *val = ((long)dout * 10000 - COREPVT_TEMP_DATA_BASE) * 1000 / COREPVT_TEMP_LSB; -+ -+ return 0; -+} -+ -+static umode_t corepvt_is_visible(const void *drvdata, enum hwmon_sensor_types type, -+ u32 attr, int channel) -+{ -+ const struct corepvt_hwmon *pvt = drvdata; -+ -+ if (channel >= pvt->channels) -+ return 0; -+ -+ switch (type) { -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_input: -+ case hwmon_in_label: -+ return 0444; -+ } -+ break; -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_input: -+ case hwmon_temp_type: -+ case hwmon_temp_label: -+ return 0444; -+ } -+ break; -+ default: -+ return 0; -+ } -+ -+ return 0; -+} -+ -+static int corepvt_read(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long *val) -+{ -+ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); -+ -+ switch (type) { -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_input: -+ return corepvt_read_vol(pvt, channel, val); -+ } -+ break; -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_type: -+ *val = 1; -+ return 0; -+ case hwmon_temp_input: -+ return corepvt_read_temp(pvt, channel, val); -+ } -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ return -ENODATA; -+} -+ -+static int corepvt_read_string(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, const char **str) -+{ -+ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); -+ u32 chl_offset = 0; -+ -+ switch (type) { -+ case hwmon_in: -+ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); -+ break; -+ case hwmon_temp: -+ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); -+ break; -+ default: -+ return -ENODATA; -+ break; -+ } -+ -+ *str = pvt->config[channel + chl_offset].label; -+ -+ return 0; -+} -+ -+/* -+ * corepvt init process: -+ * 1. config SETUP time, should be 10us, set PSCR register -+ * 2. config CLKIN, should be 4MHz, set CFDR register -+ * 3. (TODO)config interrupt, set ICR/IER/IMSR/IRSR -+ * 4. config TRIM and enable PVT, set CIR -+ */ -+static int corepvt_init(struct corepvt_hwmon *pvt) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ /* -+ * SETUP time 10us = 100KHz -+ * PSCR = CLK_FREQ / 100KHz -+ */ -+ u32 pscr_val = pvt->clk_freq / 100000; -+ /* -+ * CFDR = CLK_FREQ / 4MHz / 2 -+ */ -+ u32 cfdr_val = pvt->clk_freq / 8000000; -+ /* -+ * CIR: -+ * bit[0]: PU_VTDC, set 1 to enable pvt -+ * bit[5:2]: TRIM -+ */ -+ u32 cir_val; -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ for (int i = 0; i < pvt->channels; i++) { -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * i; -+ cir_val = (pvt->config[i].trim << 2) | 0x01; -+ writel_relaxed(pscr_val, chl_base + COREPVT_REG_PSCR); -+ writel_relaxed(cfdr_val, chl_base + COREPVT_REG_CFDR); -+ writel_relaxed(cir_val, chl_base + COREPVT_REG_CIR); -+ } -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ return 0; -+} -+ -+static const struct hwmon_ops corepvt_hwmon_ops = { -+ .is_visible = corepvt_is_visible, -+ .read = corepvt_read, -+ .read_string = corepvt_read_string, -+}; -+ -+static int corepvt_probe_channel_from_dt(struct platform_device *pdev, struct corepvt_hwmon *pvt) -+{ -+ struct device_node *child; -+ int ret; -+ u32 channel; -+ const char *label; -+ u32 trim; -+ -+ for_each_child_of_node(pdev->dev.of_node, child) { -+ if (!of_node_name_eq(child, "channel")) -+ continue; -+ -+ ret = of_property_read_u32(child, "reg", &channel); -+ if (ret) -+ goto node_put; -+ -+ ret = of_property_read_string(child, "label", &label); -+ if (ret) -+ goto node_put; -+ -+ if (of_property_present(child, "trim")) -+ of_property_read_u32(child, "trim", &trim); -+ else -+ trim = PVT_TRIM_DEFAULT; -+ -+ pvt->config[channel].label = label; -+ pvt->config[channel].trim = trim; -+ } -+ -+ return 0; -+ -+node_put: -+ of_node_put(child); -+ return ret; -+} -+ -+static int corepvt_probe(struct platform_device *pdev) -+{ -+ struct corepvt_hwmon *pvt; -+ const struct corepvt_data *pvt_data; -+ int ret; -+ -+ pvt = devm_kzalloc(&pdev->dev, sizeof(*pvt), GFP_KERNEL); -+ if (!pvt) -+ return -ENOMEM; -+ -+ pvt->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(pvt->regs)) { -+ dev_err(&pdev->dev, "get ioremap resource failed\n"); -+ ret = -EINVAL; -+ goto free_pvt; -+ } -+ -+ if (device_property_present(&pdev->dev, "interrupts")) -+ pvt->irq = platform_get_irq(pdev, 0); -+ -+ ret = device_property_read_u32(&pdev->dev, "clock-frequency", &pvt->clk_freq); -+ if (ret) { -+ dev_err(&pdev->dev, "get clock-frequency failed\n"); -+ goto free_pvt; -+ } -+ -+ ret = device_property_read_u32(&pdev->dev, "channels", &pvt->channels); -+ if (ret) { -+ dev_err(&pdev->dev, "get channels failed\n"); -+ goto free_pvt; -+ } -+ -+ pvt_data = device_get_match_data(&pdev->dev); -+ if (!pvt_data) { -+ dev_err(&pdev->dev, "No chip info found\n"); -+ ret = -ENODATA; -+ goto free_pvt; -+ } -+ -+ pvt->dev = &pdev->dev; -+ pvt->chip_info = pvt_data->chip_info; -+ pvt->pvt_data = pvt_data; -+ -+ if (pdev->dev.of_node) { -+ ret = corepvt_probe_channel_from_dt(pdev, pvt); -+ if (ret) -+ dev_warn(&pdev->dev, "WARN: probe channel failed\n"); -+ } -+ -+ pvt->hwmon = devm_hwmon_device_register_with_info(&pdev->dev, "corepvt_ultrarisc", -+ pvt, pvt->chip_info, -+ NULL); -+ if (IS_ERR(pvt->hwmon)) { -+ dev_err(&pdev->dev, "register hwmon failed(%ld)\n", PTR_ERR(pvt->hwmon)); -+ ret = -EINVAL; -+ goto free_pvt; -+ } -+ -+ pvt->dev = &pdev->dev; -+ raw_spin_lock_init(&pvt->lock); -+ -+ // Config and enable corepvt -+ corepvt_init(pvt); -+ -+ return 0; -+ -+free_pvt: -+ devm_kfree(&pdev->dev, pvt); -+ return ret; -+} -+ -+static const struct hwmon_channel_info * const ur_dp1000_channel_info[] = { -+ HWMON_CHANNEL_INFO(temp, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL), -+ HWMON_CHANNEL_INFO(in, -+ HWMON_I_INPUT | HWMON_I_LABEL, -+ HWMON_I_INPUT | HWMON_I_LABEL), -+ NULL -+}; -+ -+static const struct hwmon_chip_info ur_dp1000_chip_info = { -+ .ops = &corepvt_hwmon_ops, -+ .info = ur_dp1000_channel_info, -+}; -+ -+static struct corepvt_data ur_dp1000_pvt_data = { -+ .chip_info = &ur_dp1000_chip_info, -+ .temp_chl_mask = GENMASK_ULL(10, 0), -+ .vol_chl_mask = GENMASK_ULL(12, 11) -+}; -+ -+static const struct of_device_id corepvt_of_match[] = { -+ { .compatible = "ultrarisc,dp1000-pvt", .data = &ur_dp1000_pvt_data }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, corepvt_of_match); -+ -+static struct platform_driver corepvt_driver = { -+ .probe = corepvt_probe, -+ .driver = { -+ .name = "corepvt-ultrarisc", -+ .of_match_table = corepvt_of_match -+ } -+}; -+module_platform_driver(corepvt_driver); -+ -+MODULE_AUTHOR("Jia Wang "); -+MODULE_DESCRIPTION("corepvt-ultrarisc driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux-lts/0457-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch b/SPECS/linux-lts/0457-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch deleted file mode 100644 index 6ef6c25e68..0000000000 --- a/SPECS/linux-lts/0457-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch +++ /dev/null @@ -1,732 +0,0 @@ -From f1121d3ef4c87b156c91316132e05476fc6b3bf4 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Sun, 12 Apr 2026 02:50:03 +0800 -Subject: [PATCH 457/467] RUYI: SYNC: riscv: dts: dp1000: Update dp1000.dtsi - -FROM: https://github.com/ultrarisc/linux-6.8.0/commit/b4a00f2f96a9c7d8d550259292fd19568fe9beec - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 521 ++++++++++++++++++++-- - 1 file changed, 489 insertions(+), 32 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index 78e0cda1fcb9..7b7016618dcd 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -22,121 +22,491 @@ cpu0: cpu@0 { - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache0>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu0_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache0: l2-cache0 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu1: cpu@1 { - device_type = "cpu"; - reg = <0x1>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache1>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu1_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache1: l2-cache1 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu2: cpu@2 { - device_type = "cpu"; - reg = <0x2>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache2>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu2_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache2: l2-cache2 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu3: cpu@3 { - device_type = "cpu"; - reg = <0x3>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache3>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu3_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache3: l2-cache3 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu4: cpu@4 { - device_type = "cpu"; - reg = <0x10>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache4>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu4_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache4: l2-cache4 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu5: cpu@5 { - device_type = "cpu"; - reg = <0x11>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache5>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu5_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache5: l2-cache5 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu6: cpu@6 { - device_type = "cpu"; - reg = <0x12>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; -- - clock-frequency = <2000000000>; -- -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache6>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu6_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache6: l2-cache6 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu7: cpu@7 { - device_type = "cpu"; - reg = <0x13>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache7>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu7_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache7: l2-cache7 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; -+ }; -+ -+ cpu-map { -+ cluster0: cluster0 { -+ core0 { -+ cpu = <&cpu0>; -+ }; -+ core1 { -+ cpu = <&cpu1>; -+ }; -+ core2 { -+ cpu = <&cpu2>; -+ }; -+ core3 { -+ cpu = <&cpu3>; -+ }; -+ -+ cluster0_l3: l3-cache0 { -+ /* L3 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 4MB -+ * per-cluster. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <3>; -+ cache-size = <0x400000>; -+ cache-sets = <0x1000>; -+ cache-unified; -+ next-level-cache = <&l4_cache>; -+ }; -+ }; -+ -+ cluster1: cluster1 { -+ core0 { -+ cpu = <&cpu4>; -+ }; -+ core1 { -+ cpu = <&cpu5>; -+ }; -+ core2 { -+ cpu = <&cpu6>; -+ }; -+ core3 { -+ cpu = <&cpu7>; -+ }; -+ cluster1_l3: l3-cache1 { -+ /* L3 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 4MB -+ * per-cluster. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <3>; -+ cache-size = <0x400000>; -+ cache-sets = <0x1000>; -+ cache-unified; -+ next-level-cache = <&l4_cache>; -+ }; -+ }; - }; - }; - -@@ -150,6 +520,20 @@ soc { - #size-cells = <0x02>; - compatible = "simple-bus"; - ranges; -+ -+ l4_cache: l4-cache { -+ /* L4 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 16MB -+ * shared by the SoC. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <4>; -+ cache-size = <0x1000000>; -+ cache-sets = <0x4000>; -+ cache-unified; -+ }; - - clocks { - compatible = "simple-bus"; -@@ -160,6 +544,12 @@ device_clk: device_clk { - #clock-cells = <0>; - }; - -+ timer_clk: timer_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <50000000>; -+ #clock-cells = <0>; -+ }; -+ - csr_clk: csr_clk { - compatible = "fixed-clock"; - clock-frequency = <250000000>; -@@ -170,35 +560,102 @@ csr_clk: csr_clk { - clint: clint@8000000 { - compatible = "riscv,clint0"; - interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, -- <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -- <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -- <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -- <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -- <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -- <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -- <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; -+ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -+ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -+ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -+ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -+ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -+ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -+ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; - reg = <0x00 0x8000000 0x00 0x100000>; - }; -- -+ - plic: plic@9000000 { - #interrupt-cells = <1>; - #address-cells = <0>; -- phandle = <0x01>; -- compatible = "ultrarisc,dp1000-plic"; -+ compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; - interrupt-controller; - interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, -- <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -- <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -- <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -- <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -- <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -- <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -- <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; -+ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -+ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -+ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -+ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -+ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -+ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -+ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; - reg = <0x00 0x9000000 0x00 0x4000000>; - riscv,max-priority = <0x07>; - riscv,ndev = <160>; - }; -- -+ -+ core_pvt: pvt@110D0000 { -+ compatible = "ultrarisc,dp1000-pvt"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x00 0x110D0000 0x00 0x0000D000>; -+ clock-frequency = <250000000>; -+ channels = <13>; -+ -+ #thermal-sensor-cells = <1>; -+ channel@0 { -+ label = "Core temp0"; -+ reg = <0>; -+ }; -+ -+ channel@1 { -+ label = "Core temp1"; -+ reg = <1>; -+ }; -+ -+ channel@2 { -+ label = "Core temp2"; -+ reg = <2>; -+ }; -+ -+ channel@3 { -+ label = "Core temp3"; -+ reg = <3>; -+ }; -+ -+ channel@4 { -+ label = "Core temp4"; -+ reg = <4>; -+ }; -+ -+ channel@5 { -+ label = "Core temp5"; -+ reg = <5>; -+ }; -+ channel@6 { -+ label = "Core temp6"; -+ reg = <6>; -+ }; -+ channel@7 { -+ label = "Core temp7"; -+ reg = <7>; -+ }; -+ channel@8 { -+ label = "Core temp8"; -+ reg = <8>; -+ }; -+ channel@9 { -+ label = "Core temp9"; -+ reg = <9>; -+ }; -+ channel@10 { -+ label = "Core temp10"; -+ reg = <10>; -+ }; -+ channel@11 { -+ label = "Cluster0 voltage"; -+ reg = <11>; -+ }; -+ channel@12 { -+ label = "Cluster1 voltage"; -+ reg = <12>; -+ }; -+ }; -+ - uart0: serial@20300000 { - interrupt-parent = <0x01>; - interrupts = <17>; -@@ -244,7 +701,7 @@ uart3: serial@20410000 { - }; - - spi0: spi@20320000 { -- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ compatible = "snps,dw-apb-ssi"; - status = "okay"; - #address-cells = <0x01>; - #size-cells = <0x00>; -@@ -258,7 +715,7 @@ spi0: spi@20320000 { - }; - - spi1: spi@20420000 { -- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ compatible = "snps,dw-apb-ssi"; - status = "okay"; - #address-cells = <0x01>; - #size-cells = <0x00>; -@@ -449,11 +906,11 @@ pcie_x16: pcie@21000000 { - num-lanes = <16>; - ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -- max-link-speed = <4>; -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <16>; - interrupt-parent = <&plic>; -- interrupts = <43>, <44>, <45>, <46>, <47>, <48>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <43>, <44>, <45>, <46>, <47>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, - <0x0 0x0 0x0 0x2 &plic 45>, -@@ -475,11 +932,11 @@ pcie_x4a: pcie@23000000 { - num-lanes = <4>; - ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ - max-link-speed = <4>; - interrupt-parent = <&plic>; -- interrupts = <63>, <64>, <65>, <66>, <67>, <68>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <63>, <64>, <65>, <66>, <67>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, - <0x0 0x0 0x0 0x2 &plic 65>, -@@ -501,11 +958,11 @@ pcie_x4b: pcie@24000000 { - num-lanes = <4>; - ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ - max-link-speed = <4>; - interrupt-parent = <&plic>; -- interrupts = <73>, <74>, <75>, <76>, <77>, <78>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <73>, <74>, <75>, <76>, <77>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, - <0x0 0x0 0x0 0x2 &plic 75>, --- -2.53.0 - diff --git a/SPECS/linux-lts/0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch b/SPECS/linux-lts/0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch new file mode 100644 index 0000000000..ca0081cabf --- /dev/null +++ b/SPECS/linux-lts/0457-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch @@ -0,0 +1,364 @@ +From 90a72c61206582a7f4df5b88119e6602cbafc201 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 18 Nov 2025 13:48:49 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dts: dp1000: add dts/dtsi for Milk-V Titan + board based on UltraRISC DP1000 SoC + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +-------------------------------- + +Add dp1000-titan-v1.dts and dp1000-titan-pinctrl.dtsi for the Milk-V Titan +board. The Titan board is designed by Milk-V and is based on the UltraRISC +DP1000 SoC. These device tree files provide the initial support for the +board, including pinctrl and basic peripheral configuration. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/edab885e252d0442ccf52b2b554934138b82b2ec +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 1 + + .../dts/ultrarisc/dp1000-titan-pinctrl.dtsi | 173 ++++++++++++++++++ + .../boot/dts/ultrarisc/dp1000-titan-v1.dts | 139 ++++++++++++++ + 3 files changed, 313 insertions(+) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index 22c03b44b2f8..df8efe1a3ed7 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-titan-v1.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi +new file mode 100644 +index 000000000000..35429e539832 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi +@@ -0,0 +1,173 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 12 UR_FUNC0 ++ UR_DP1000_IOMUX_A 13 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 6 UR_FUNC0 ++ UR_DP1000_IOMUX_B 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 0 UR_FUNC0 ++ UR_DP1000_IOMUX_C 1 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 2 UR_FUNC0 ++ UR_DP1000_IOMUX_C 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 8 UR_FUNC1 ++ UR_DP1000_IOMUX_A 9 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 4 UR_FUNC0 ++ UR_DP1000_IOMUX_B 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 4 UR_FUNC0 ++ UR_DP1000_IOMUX_C 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart3_pins: uart3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 6 UR_FUNC0 ++ UR_DP1000_IOMUX_C 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_D 0 UR_FUNC1 ++ UR_DP1000_IOMUX_D 1 UR_FUNC1 ++ UR_DP1000_IOMUX_D 2 UR_FUNC1 ++ UR_DP1000_IOMUX_D 3 UR_FUNC1 ++ UR_DP1000_IOMUX_D 4 UR_FUNC1 ++ UR_DP1000_IOMUX_D 5 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 0 UR_FUNC0 ++ UR_DP1000_IOMUX_A 1 UR_FUNC0 ++ UR_DP1000_IOMUX_A 2 UR_FUNC0 ++ UR_DP1000_IOMUX_A 3 UR_FUNC0 ++ UR_DP1000_IOMUX_A 4 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ gpios_pin: gpios_pin { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 10 UR_FUNC_DEF ++ UR_DP1000_IOMUX_A 11 UR_FUNC_DEF ++ UR_DP1000_IOMUX_A 14 UR_FUNC_DEF ++ UR_DP1000_IOMUX_A 15 UR_FUNC_DEF ++ ++ UR_DP1000_IOMUX_B 0 UR_FUNC_DEF ++ UR_DP1000_IOMUX_B 1 UR_FUNC_DEF ++ UR_DP1000_IOMUX_B 2 UR_FUNC_DEF ++ ++ UR_DP1000_IOMUX_D 6 UR_FUNC_DEF ++ UR_DP1000_IOMUX_D 7 UR_FUNC_DEF ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 10 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 11 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 14 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 15 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ ++ UR_DP1000_IOMUX_B 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ ++ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts +new file mode 100644 +index 000000000000..2cbdfa2ad813 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts +@@ -0,0 +1,139 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000-titan-pinctrl.dtsi" ++#include ++#include ++#include ++#include ++ ++/ { ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS0,115200"; ++ stdout-path = &uart0; ++ }; ++ ++ gpio-poweroff { ++ compatible = "gpio-poweroff"; ++ gpios = <&portb 0 GPIO_ACTIVE_LOW>; ++ active-delay-ms = <100>; ++ line-name = "power-off"; ++ status = "okay"; ++ }; ++ ++ gpio-restart { ++ compatible = "gpio-restart"; ++ gpios = <&portb 1 GPIO_ACTIVE_LOW>; ++ active-delay-ms = <100>; ++ line-name = "reset-system"; ++ status = "okay"; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ key-wakeup { ++ label = "Wake-Up"; ++ gpios = <&porta 14 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ linux,input-type = ; ++ debounce-interval = <10>; ++ wakeup-source; ++ wakeup-event-action = ; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ ++ rtc@68 { ++ compatible = "st,m41t11"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++}; ++ ++&porta { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpios_pin>; ++ ++ i2c1-mux-hog { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ /* LOW: DCDC(U6) connect MCU(EC) ++ * HIGH: DCDC(U6) connect CPU ++ */ ++ output-low; ++ line-name = "gpio-mux-dcdc"; ++ }; ++ ++ i2c3-mux-hog { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_LOW>; ++ /* LOW: CPU i2c3 connect nvme ++ * HIGH: CPU i2c3 connect pciex16 ++ */ ++ output-low; ++ line-name = "gpio-mux-i2c3"; ++ }; ++ ++ uart0-mux-hog { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ /* LOW: uart_debug connect BMC ++ * HIGH: uart_debug connect CPU ++ */ ++ output-high; ++ line-name = "gpio-mux-debug"; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch b/SPECS/linux-lts/0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch new file mode 100644 index 0000000000..7b6568d84b --- /dev/null +++ b/SPECS/linux-lts/0458-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch @@ -0,0 +1,77 @@ +From ad2ca89827235515c3cfea8822ac22544a6f79f1 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Mon, 23 Feb 2026 14:35:29 +0800 +Subject: [RUYI PATCH] REVYSR: pinctrl: ultrarisc: cleanup probe&remove + +Signed-off-by: Han Gao +--- + .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 - + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 22 +++---------------- + 2 files changed, 3 insertions(+), 20 deletions(-) + +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +index 6a7496a465d8..0ead138c9d1f 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +@@ -117,7 +117,6 @@ static struct platform_driver ur_pinctrl_driver = { + .of_match_table = ur_pinctrl_of_match, + }, + .probe = ur_pinctrl_probe, +- .remove = ur_pinctrl_remove, + }; + + module_platform_driver(ur_pinctrl_driver); +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +index edaeca881af7..cdd7160f3183 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +@@ -514,8 +514,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) + ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); + if (!ur_pinctrl) { + dev_err(&pdev->dev, "pinctrl alloc failed\n"); +- ret = -ENOMEM; +- goto free_pinctrl_desc; ++ return -ENOMEM; + } + struct resource *res; + +@@ -524,8 +523,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) + ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ur_pinctrl->base)) { + dev_err(&pdev->dev, "get ioremap resource failed\n"); +- ret = -EINVAL; +- goto free_pinctrl_desc; ++ return -EINVAL; + } + dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); + ur_pinctrl_desc->name = dev_name(&pdev->dev); +@@ -546,25 +544,11 @@ int ur_pinctrl_probe(struct platform_device *pdev) + ur_pinctrl, &ur_pinctrl->pctl_dev); + if (ret) { + dev_err(&pdev->dev, "pinctrl register failed\n"); +- goto free_pinctrl; ++ return ret; + } + + platform_set_drvdata(pdev, ur_pinctrl); + + return pinctrl_enable(ur_pinctrl->pctl_dev); +- +-free_pinctrl: +- devm_kfree(&pdev->dev, ur_pinctrl); +-free_pinctrl_desc: +- devm_kfree(&pdev->dev, ur_pinctrl_desc); +- return ret; + } + +- +-void ur_pinctrl_remove(struct platform_device *pdev) +-{ +- struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); +- +- if (ur_pinctrl->pctl_dev) +- devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); +-} +-- +2.53.0 + diff --git a/SPECS/linux-lts/0458-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch b/SPECS/linux-lts/0458-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch deleted file mode 100644 index 7a4dc86808..0000000000 --- a/SPECS/linux-lts/0458-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch +++ /dev/null @@ -1,102 +0,0 @@ -From da670b3d82267098c5ec850e11e6810ba6c0141b Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sat, 24 Jan 2026 08:48:53 +0800 -Subject: [PATCH 458/467] RUYI: riscv: dts: spacemit: k3: Add USB2.0 support - -FROM: https://github.com/spacemit-com/linux/commit/6f1578894e4484f8a6724aceff099d2e90450e10 - -The USB2.0 controller on Pico-ITX board connnect to a Terminus FE1.1 Hub -which fully USB2.0 protocol compliant and provides 4 ports. - -Signed-off-by: Yixun Lan -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 25 ++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++ - 2 files changed, 56 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index 61cbf924830b..ac965ec83f2c 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -33,6 +33,15 @@ reg_aux_vcc5v: regulator-aux-vcc5v { - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -+ -+ aux_vcc3v3: regulator-aux-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "AUX_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ - }; - - &i2c8 { -@@ -255,3 +264,19 @@ &uart0 { - pinctrl-0 = <&uart0_0_cfg>; - status = "okay"; - }; -+ -+&usb2_host { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ hub@1 { -+ compatible = "usb1a40,0101"; -+ reg = <1>; -+ vdd-supply = <&aux_vcc3v3>; -+ }; -+}; -+ -+&usb2_phy { -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 5b17612fe58e..66dcabd0a815 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -637,6 +637,37 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ usb2_host: usb@c0a00000 { -+ compatible = "spacemit,k3-dwc3"; -+ reg = <0x0 0xc0a00000 0x0 0x10000>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ clock-names = "usbdrd30"; -+ resets = <&syscon_apmu RESET_APMU_USB2_AHB>, -+ <&syscon_apmu RESET_APMU_USB2_VCC>, -+ <&syscon_apmu RESET_APMU_USB2_PHY>; -+ reset-names = "ahb", "vcc", "phy"; -+ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&saplic>; -+ phys = <&usb2_phy>; -+ phy-names = "usb2-phy"; -+ phy_type = "utmi"; -+ snps,dis_enblslpm_quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ dr_mode = "host"; -+ maximum-speed = "high-speed"; -+ status = "disabled"; -+ }; -+ -+ usb2_phy: phy@c0a20000 { -+ compatible = "spacemit,k3-usb2-phy"; -+ reg = <0x0 0xc0a20000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k3-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch b/SPECS/linux-lts/0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch new file mode 100644 index 0000000000..3ab0a8fab6 --- /dev/null +++ b/SPECS/linux-lts/0459-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch @@ -0,0 +1,46 @@ +From 3a0ec292f418c3f0ec2630531aeab29eea263f22 Mon Sep 17 00:00:00 2001 +From: U2FsdGVkX1 +Date: Sun, 29 Mar 2026 15:31:14 +0000 +Subject: [RUYI PATCH] REVYSR: riscv: dp1000: dts: use ultrarisc,dp1000-pcie + for PCIe nodes + +Signed-off-by: U2FsdGVkX1 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +index a25e87e15553..78e0cda1fcb9 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +@@ -436,7 +436,7 @@ dmac: dma-controller@39000000 { + }; + + pcie_x16: pcie@21000000 { +- compatible = "ultrarisc,dw-pcie"; ++ compatible = "ultrarisc,dp1000-pcie"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; +@@ -462,7 +462,7 @@ pcie_x16: pcie@21000000 { + }; + + pcie_x4a: pcie@23000000 { +- compatible = "ultrarisc,dw-pcie"; ++ compatible = "ultrarisc,dp1000-pcie"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; +@@ -488,7 +488,7 @@ pcie_x4a: pcie@23000000 { + }; + + pcie_x4b: pcie@24000000 { +- compatible = "ultrarisc,dw-pcie"; ++ compatible = "ultrarisc,dp1000-pcie"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0459-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch b/SPECS/linux-lts/0459-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch deleted file mode 100644 index fb68ebb141..0000000000 --- a/SPECS/linux-lts/0459-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch +++ /dev/null @@ -1,145 +0,0 @@ -From a778bb9a14663755014caabaaa245eba24561659 Mon Sep 17 00:00:00 2001 -From: Zhang Meng -Date: Mon, 5 Jan 2026 20:05:04 +0800 -Subject: [PATCH 459/467] SPACEMIT: riscv: uaccess: don't use vector if buffer - is not cacheable - -FROM: https://github.com/spacemit-com/linux-6.18/commit/9168f7e0c6bfdcfa3b6a64a4d45e3cd68a81618f - -Change-Id: I040d597ee246777767f7be747fa9202154524538 -[ Vivian: Rebase and move check into enter_vector_usercopy ] -Signed-off-by: Vivian Wang -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/uaccess.h | 5 +++ - arch/riscv/lib/Makefile | 1 + - arch/riscv/lib/riscv_v_helpers.c | 5 +++ - arch/riscv/lib/uaccess_cache_check.c | 65 ++++++++++++++++++++++++++++ - 4 files changed, 76 insertions(+) - create mode 100644 arch/riscv/lib/uaccess_cache_check.c - -diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h -index 6aef591a6bfc..b028208b05ec 100644 ---- a/arch/riscv/include/asm/uaccess.h -+++ b/arch/riscv/include/asm/uaccess.h -@@ -487,6 +487,11 @@ static inline void user_access_restore(unsigned long enabled) { } - if (__asm_copy_from_user_sum_enabled(_dst, _src, _len)) \ - goto label; - -+/* Memory cacheability check for vector uaccess optimization */ -+#ifdef CONFIG_RISCV_ISA_V -+int is_cacheable_safe(const void *addr); -+#endif -+ - #else /* CONFIG_MMU */ - #include - #endif /* CONFIG_MMU */ -diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile -index 735d0b665536..43fe69db9803 100644 ---- a/arch/riscv/lib/Makefile -+++ b/arch/riscv/lib/Makefile -@@ -14,6 +14,7 @@ endif - lib-y += csum.o - ifeq ($(CONFIG_MMU), y) - lib-$(CONFIG_RISCV_ISA_V) += uaccess_vector.o -+lib-$(CONFIG_RISCV_ISA_V) += uaccess_cache_check.o - endif - lib-$(CONFIG_MMU) += uaccess.o - lib-$(CONFIG_64BIT) += tishift.o -diff --git a/arch/riscv/lib/riscv_v_helpers.c b/arch/riscv/lib/riscv_v_helpers.c -index 7bbdfc6d4552..7ab2cea280f8 100644 ---- a/arch/riscv/lib/riscv_v_helpers.c -+++ b/arch/riscv/lib/riscv_v_helpers.c -@@ -8,6 +8,7 @@ - - #include - #include -+#include - - #ifdef CONFIG_MMU - #include -@@ -28,6 +29,10 @@ asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n, - if (!may_use_simd()) - goto fallback; - -+ /* HACK */ -+ if (!is_cacheable_safe(dst) || !is_cacheable_safe(src)) -+ goto fallback; -+ - kernel_vector_begin(); - remain = enable_sum ? __asm_vector_usercopy(dst, src, n) : - __asm_vector_usercopy_sum_enabled(dst, src, n); -diff --git a/arch/riscv/lib/uaccess_cache_check.c b/arch/riscv/lib/uaccess_cache_check.c -new file mode 100644 -index 000000000000..0b0996fa2d37 ---- /dev/null -+++ b/arch/riscv/lib/uaccess_cache_check.c -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Memory cacheability check for RISC-V uaccess optimization -+ * -+ * This file provides a C function that can be called from assembly -+ * to determine if a buffer is cacheable before using vector instructions. -+ */ -+ -+#include -+#include -+#include -+ -+/** -+ * is_cacheable_safe - Check if memory buffer is cacheable -+ * @addr: Virtual address to check (kernel or user space) -+ * -+ * Returns: 1 if cacheable, 0 if non-cacheable -+ * -+ * This function is designed to be called from assembly code in uaccess.S -+ * to determine if vector instructions are safe to use for memory copy. -+ * -+ * Non-cacheable memory (device IO, DMA coherent buffers) should not use -+ * vector instructions as they may cause cache coherency issues. -+ * -+ * Handles both kernel and user space addresses safely: -+ * - Kernel direct mapping: Always cacheable -+ * - Kernel vmalloc: Check VM flags -+ * - User space: Check page table (most are cacheable) -+ * - ioremap/DMA: Non-cacheable -+ */ -+int is_cacheable_safe(const void *addr) -+{ -+ unsigned long vaddr = (unsigned long)addr; -+ -+ /* Kernel direct mapped memory - always cacheable */ -+ if (virt_addr_valid(addr)) -+ return 1; -+ -+ if (vaddr < TASK_SIZE) { -+ /* -+ * User space address, Determine it as a cacheable buffer, -+ * maybe not safe!! -+ */ -+ return 1; -+ } -+ -+ /* Check if it's a vmalloc region (kernel virtual address) */ -+ if (is_vmalloc_addr(addr)) { -+ struct vm_struct *vm; -+ -+ vm = find_vm_area(addr); -+ if (!vm) -+ return 0; -+ -+ /* Exclude ioremap and DMA coherent buffers */ -+ if (vm->flags & (VM_IOREMAP | VM_DMA_COHERENT)) -+ return 0; -+ -+ /* Normal vmalloc - cacheable */ -+ return 1; -+ } -+ -+ /* Unknown kernel region - assume non-cacheable for safety */ -+ return 0; -+} --- -2.53.0 - diff --git a/SPECS/linux-lts/0460-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch b/SPECS/linux-lts/0460-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch deleted file mode 100644 index 7e8d2c8137..0000000000 --- a/SPECS/linux-lts/0460-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch +++ /dev/null @@ -1,90 +0,0 @@ -From b29e3da058bfbb22e49d731df4e66c5998bd6324 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 13 Feb 2026 09:01:58 +0800 -Subject: [PATCH 460/467] RUYI: dt-bindings: phy: Add Spacemit K3 USB3/PCIe - comb phy support - -The USB3/PCIe comb PHY on the K3 is a complex PHY group that -can provide multiple phy for both PCIe and USB controller. -Its mux configuration is controlled by the APMU syscon device. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - .../bindings/phy/spacemit,k3-combo-phy.yaml | 64 +++++++++++++++++++ - 1 file changed, 64 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml -new file mode 100644 -index 000000000000..eafc753b7e9b ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml -@@ -0,0 +1,64 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Spacemit K3 PCIE/USB3 Comb PHY -+ -+maintainers: -+ - Inochi Amaoto -+ -+properties: -+ compatible: -+ const: spacemit,k3-combo-phy -+ -+ reg: -+ maxItems: 1 -+ -+ "#phy-cells": -+ const: 2 -+ description: -+ The first one is phy id, the second one is phy type. -+ -+ spacemit,apb-spare: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: -+ Phandle to APB SPARE system controller interface, used for -+ PHY calibration. -+ -+ spacemit,apmu: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ items: -+ - items: -+ - description: phandle of APMU syscon -+ - description: configuration of the PHY lanes -+ description: | -+ Phandle to control PHY mux configuration. The configuration -+ is described as follows: -+ bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode -+ bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode -+ bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode -+ bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode -+ bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode -+ -+ The bit[3:0] is only valid when bit 4 is 1. -+ -+required: -+ - compatible -+ - reg -+ - "#phy-cells" -+ - spacemit,apb-spare -+ - spacemit,apmu -+ -+additionalProperties: false -+ -+examples: -+ - | -+ phy@81d00000 { -+ compatible = "spacemit,k3-combo-phy"; -+ reg = <0x81d00000 0x600000>; -+ #phy-cells = <2>; -+ spacemit,apb-spare = <&apb_spare>; -+ spacemit,apmu = <&apmu 0x00>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux-lts/0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch b/SPECS/linux-lts/0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch new file mode 100644 index 0000000000..732de29759 --- /dev/null +++ b/SPECS/linux-lts/0460-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch @@ -0,0 +1,450 @@ +From 3091a1fa3451d492041d5cc22aeb46f67edaf469 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Thu, 13 Feb 2025 15:50:12 +0800 +Subject: [RUYI PATCH] ULTRARISC: hwmon: add corepvt driver of UltraRISC DP1000 + +From: https://github.com/ultrarisc/linux-6.8.0/commit/2cb818e1179844847d3be752b978a4ee7e633bc3 + +UltraRISC Corepvt driver supports cluster voltage +and core temperature detection + +Signed-off-by: Jia Wang +Signed-off-by: Han Gao +--- + drivers/hwmon/Kconfig | 9 + + drivers/hwmon/Makefile | 1 + + drivers/hwmon/corepvt-ultrarisc.c | 390 ++++++++++++++++++++++++++++++ + 3 files changed, 400 insertions(+) + create mode 100644 drivers/hwmon/corepvt-ultrarisc.c + +diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig +index 2a71b6e834b0..2a44030c7796 100644 +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -503,6 +503,15 @@ config SENSORS_CHIPCAP2 + To compile this driver as a module, choose M here: the module + will be called chipcap2. + ++config SENSORS_COREPVT_ULTRARISC ++ tristate "UltraRISC Core Voltage, Temperature sensor driver" ++ help ++ If you say yes here you get support for UltraRISC Core PVT sensor ++ embedded into the SoC. ++ ++ This driver can also be built as a module. If so, the module will be ++ called corepvt-ultrarisc. ++ + config SENSORS_CORSAIR_CPRO + tristate "Corsair Commander Pro controller" + depends on HID +diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile +index 73b2abdcc6dd..6cf5fac80b7b 100644 +--- a/drivers/hwmon/Makefile ++++ b/drivers/hwmon/Makefile +@@ -61,6 +61,7 @@ obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o + obj-$(CONFIG_SENSORS_BT1_PVT) += bt1-pvt.o + obj-$(CONFIG_SENSORS_CGBC) += cgbc-hwmon.o + obj-$(CONFIG_SENSORS_CHIPCAP2) += chipcap2.o ++obj-$(CONFIG_SENSORS_COREPVT_ULTRARISC) += corepvt-ultrarisc.o + obj-$(CONFIG_SENSORS_CORETEMP) += coretemp.o + obj-$(CONFIG_SENSORS_CORSAIR_CPRO) += corsair-cpro.o + obj-$(CONFIG_SENSORS_CORSAIR_PSU) += corsair-psu.o +diff --git a/drivers/hwmon/corepvt-ultrarisc.c b/drivers/hwmon/corepvt-ultrarisc.c +new file mode 100644 +index 000000000000..3674eedefbda +--- /dev/null ++++ b/drivers/hwmon/corepvt-ultrarisc.c +@@ -0,0 +1,390 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Driver for UltraRISC Core PVT ++ * ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define COREPVT_CHL_OFFSET 0x1000 ++#define COREPVT_REG_CIR 0x0 ++#define COREPVT_REG_PSCR 0x04 ++#define COREPVT_REG_CFDR 0x08 ++#define COREPVT_REG_DOR 0x0C ++#define COREPVT_REG_ICR 0x10 ++#define COREPVT_REG_IER 0x14 ++#define COREPVT_REG_IMSR 0x18 ++#define COREPVT_REG_IRSR 0x1C ++ ++#define PVT_MAX_CHANNEL 64 ++#define PVT_TRIM_DEFAULT 0x7 ++ ++struct corepvt_channel_config { ++ const char *label; ++ u32 trim; ++}; ++ ++struct corepvt_cal_data { ++ u32 val_offset; ++ u32 val_lsb; ++}; ++ ++struct corepvt_data { ++ const struct hwmon_chip_info *chip_info; ++ u64 temp_chl_mask; ++ u64 vol_chl_mask; ++}; ++ ++struct corepvt_hwmon { ++ struct device *dev; ++ struct device *hwmon; ++ ++ void __iomem *regs; ++ int irq; ++ int clk_freq; ++ int channels; ++ const struct hwmon_chip_info *chip_info; ++ struct corepvt_channel_config config[PVT_MAX_CHANNEL]; ++ const struct corepvt_data *pvt_data; ++ raw_spinlock_t lock; ++}; ++ ++#define COREPVT_VOLTAGE_DATA_BASE 2065100 /* 2065.1 */ ++#define COREPVT_VOLTAGE_LSB 1682 /* 1.682 mV */ ++#define COREPVT_TEMP_DATA_BASE 27049000 /* 2704.9 */ ++#define COREPVT_TEMP_LSB 22632 /* 2.2632 Celsius */ ++ ++static int corepvt_read_vol(struct corepvt_hwmon *pvt, ++ int channel, long *val) ++{ ++ void __iomem *chl_base; ++ unsigned long flag; ++ u32 dout; ++ u32 chl_offset = 0; ++ ++ // Assume that the voltage channel is continuous ++ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); ++ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); ++ ++ raw_spin_lock_irqsave(&pvt->lock, flag); ++ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); ++ raw_spin_unlock_irqrestore(&pvt->lock, flag); ++ ++ *val = ((long)dout * 1000 - COREPVT_VOLTAGE_DATA_BASE) / COREPVT_VOLTAGE_LSB; ++ ++ return 0; ++} ++ ++static int corepvt_read_temp(struct corepvt_hwmon *pvt, ++ int channel, long *val) ++{ ++ void __iomem *chl_base; ++ unsigned long flag; ++ u32 dout; ++ u32 chl_offset = 0; ++ ++ // Assume that the temperature channel is continuous ++ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); ++ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); ++ ++ raw_spin_lock_irqsave(&pvt->lock, flag); ++ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); ++ raw_spin_unlock_irqrestore(&pvt->lock, flag); ++ ++ *val = ((long)dout * 10000 - COREPVT_TEMP_DATA_BASE) * 1000 / COREPVT_TEMP_LSB; ++ ++ return 0; ++} ++ ++static umode_t corepvt_is_visible(const void *drvdata, enum hwmon_sensor_types type, ++ u32 attr, int channel) ++{ ++ const struct corepvt_hwmon *pvt = drvdata; ++ ++ if (channel >= pvt->channels) ++ return 0; ++ ++ switch (type) { ++ case hwmon_in: ++ switch (attr) { ++ case hwmon_in_input: ++ case hwmon_in_label: ++ return 0444; ++ } ++ break; ++ case hwmon_temp: ++ switch (attr) { ++ case hwmon_temp_input: ++ case hwmon_temp_type: ++ case hwmon_temp_label: ++ return 0444; ++ } ++ break; ++ default: ++ return 0; ++ } ++ ++ return 0; ++} ++ ++static int corepvt_read(struct device *dev, enum hwmon_sensor_types type, ++ u32 attr, int channel, long *val) ++{ ++ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); ++ ++ switch (type) { ++ case hwmon_in: ++ switch (attr) { ++ case hwmon_in_input: ++ return corepvt_read_vol(pvt, channel, val); ++ } ++ break; ++ case hwmon_temp: ++ switch (attr) { ++ case hwmon_temp_type: ++ *val = 1; ++ return 0; ++ case hwmon_temp_input: ++ return corepvt_read_temp(pvt, channel, val); ++ } ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return -ENODATA; ++} ++ ++static int corepvt_read_string(struct device *dev, enum hwmon_sensor_types type, ++ u32 attr, int channel, const char **str) ++{ ++ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); ++ u32 chl_offset = 0; ++ ++ switch (type) { ++ case hwmon_in: ++ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); ++ break; ++ case hwmon_temp: ++ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); ++ break; ++ default: ++ return -ENODATA; ++ break; ++ } ++ ++ *str = pvt->config[channel + chl_offset].label; ++ ++ return 0; ++} ++ ++/* ++ * corepvt init process: ++ * 1. config SETUP time, should be 10us, set PSCR register ++ * 2. config CLKIN, should be 4MHz, set CFDR register ++ * 3. (TODO)config interrupt, set ICR/IER/IMSR/IRSR ++ * 4. config TRIM and enable PVT, set CIR ++ */ ++static int corepvt_init(struct corepvt_hwmon *pvt) ++{ ++ void __iomem *chl_base; ++ unsigned long flag; ++ /* ++ * SETUP time 10us = 100KHz ++ * PSCR = CLK_FREQ / 100KHz ++ */ ++ u32 pscr_val = pvt->clk_freq / 100000; ++ /* ++ * CFDR = CLK_FREQ / 4MHz / 2 ++ */ ++ u32 cfdr_val = pvt->clk_freq / 8000000; ++ /* ++ * CIR: ++ * bit[0]: PU_VTDC, set 1 to enable pvt ++ * bit[5:2]: TRIM ++ */ ++ u32 cir_val; ++ ++ raw_spin_lock_irqsave(&pvt->lock, flag); ++ for (int i = 0; i < pvt->channels; i++) { ++ chl_base = pvt->regs + COREPVT_CHL_OFFSET * i; ++ cir_val = (pvt->config[i].trim << 2) | 0x01; ++ writel_relaxed(pscr_val, chl_base + COREPVT_REG_PSCR); ++ writel_relaxed(cfdr_val, chl_base + COREPVT_REG_CFDR); ++ writel_relaxed(cir_val, chl_base + COREPVT_REG_CIR); ++ } ++ raw_spin_unlock_irqrestore(&pvt->lock, flag); ++ ++ return 0; ++} ++ ++static const struct hwmon_ops corepvt_hwmon_ops = { ++ .is_visible = corepvt_is_visible, ++ .read = corepvt_read, ++ .read_string = corepvt_read_string, ++}; ++ ++static int corepvt_probe_channel_from_dt(struct platform_device *pdev, struct corepvt_hwmon *pvt) ++{ ++ struct device_node *child; ++ int ret; ++ u32 channel; ++ const char *label; ++ u32 trim; ++ ++ for_each_child_of_node(pdev->dev.of_node, child) { ++ if (!of_node_name_eq(child, "channel")) ++ continue; ++ ++ ret = of_property_read_u32(child, "reg", &channel); ++ if (ret) ++ goto node_put; ++ ++ ret = of_property_read_string(child, "label", &label); ++ if (ret) ++ goto node_put; ++ ++ if (of_property_present(child, "trim")) ++ of_property_read_u32(child, "trim", &trim); ++ else ++ trim = PVT_TRIM_DEFAULT; ++ ++ pvt->config[channel].label = label; ++ pvt->config[channel].trim = trim; ++ } ++ ++ return 0; ++ ++node_put: ++ of_node_put(child); ++ return ret; ++} ++ ++static int corepvt_probe(struct platform_device *pdev) ++{ ++ struct corepvt_hwmon *pvt; ++ const struct corepvt_data *pvt_data; ++ int ret; ++ ++ pvt = devm_kzalloc(&pdev->dev, sizeof(*pvt), GFP_KERNEL); ++ if (!pvt) ++ return -ENOMEM; ++ ++ pvt->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(pvt->regs)) { ++ dev_err(&pdev->dev, "get ioremap resource failed\n"); ++ ret = -EINVAL; ++ goto free_pvt; ++ } ++ ++ if (device_property_present(&pdev->dev, "interrupts")) ++ pvt->irq = platform_get_irq(pdev, 0); ++ ++ ret = device_property_read_u32(&pdev->dev, "clock-frequency", &pvt->clk_freq); ++ if (ret) { ++ dev_err(&pdev->dev, "get clock-frequency failed\n"); ++ goto free_pvt; ++ } ++ ++ ret = device_property_read_u32(&pdev->dev, "channels", &pvt->channels); ++ if (ret) { ++ dev_err(&pdev->dev, "get channels failed\n"); ++ goto free_pvt; ++ } ++ ++ pvt_data = device_get_match_data(&pdev->dev); ++ if (!pvt_data) { ++ dev_err(&pdev->dev, "No chip info found\n"); ++ ret = -ENODATA; ++ goto free_pvt; ++ } ++ ++ pvt->dev = &pdev->dev; ++ pvt->chip_info = pvt_data->chip_info; ++ pvt->pvt_data = pvt_data; ++ ++ if (pdev->dev.of_node) { ++ ret = corepvt_probe_channel_from_dt(pdev, pvt); ++ if (ret) ++ dev_warn(&pdev->dev, "WARN: probe channel failed\n"); ++ } ++ ++ pvt->hwmon = devm_hwmon_device_register_with_info(&pdev->dev, "corepvt_ultrarisc", ++ pvt, pvt->chip_info, ++ NULL); ++ if (IS_ERR(pvt->hwmon)) { ++ dev_err(&pdev->dev, "register hwmon failed(%ld)\n", PTR_ERR(pvt->hwmon)); ++ ret = -EINVAL; ++ goto free_pvt; ++ } ++ ++ pvt->dev = &pdev->dev; ++ raw_spin_lock_init(&pvt->lock); ++ ++ // Config and enable corepvt ++ corepvt_init(pvt); ++ ++ return 0; ++ ++free_pvt: ++ devm_kfree(&pdev->dev, pvt); ++ return ret; ++} ++ ++static const struct hwmon_channel_info * const ur_dp1000_channel_info[] = { ++ HWMON_CHANNEL_INFO(temp, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL), ++ HWMON_CHANNEL_INFO(in, ++ HWMON_I_INPUT | HWMON_I_LABEL, ++ HWMON_I_INPUT | HWMON_I_LABEL), ++ NULL ++}; ++ ++static const struct hwmon_chip_info ur_dp1000_chip_info = { ++ .ops = &corepvt_hwmon_ops, ++ .info = ur_dp1000_channel_info, ++}; ++ ++static struct corepvt_data ur_dp1000_pvt_data = { ++ .chip_info = &ur_dp1000_chip_info, ++ .temp_chl_mask = GENMASK_ULL(10, 0), ++ .vol_chl_mask = GENMASK_ULL(12, 11) ++}; ++ ++static const struct of_device_id corepvt_of_match[] = { ++ { .compatible = "ultrarisc,dp1000-pvt", .data = &ur_dp1000_pvt_data }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, corepvt_of_match); ++ ++static struct platform_driver corepvt_driver = { ++ .probe = corepvt_probe, ++ .driver = { ++ .name = "corepvt-ultrarisc", ++ .of_match_table = corepvt_of_match ++ } ++}; ++module_platform_driver(corepvt_driver); ++ ++MODULE_AUTHOR("Jia Wang "); ++MODULE_DESCRIPTION("corepvt-ultrarisc driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch b/SPECS/linux-lts/0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch new file mode 100644 index 0000000000..0582b1d016 --- /dev/null +++ b/SPECS/linux-lts/0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch @@ -0,0 +1,732 @@ +From 817a4331068207be97f31dbe87e3512e92b549de Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Sun, 12 Apr 2026 02:50:03 +0800 +Subject: [RUYI PATCH] RUYI: SYNC: riscv: dts: dp1000: Update dp1000.dtsi + +FROM: https://github.com/ultrarisc/linux-6.8.0/commit/b4a00f2f96a9c7d8d550259292fd19568fe9beec + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 521 ++++++++++++++++++++-- + 1 file changed, 489 insertions(+), 32 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +index 78e0cda1fcb9..7b7016618dcd 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +@@ -22,121 +22,491 @@ cpu0: cpu@0 { + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache0>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu0_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache0: l2-cache0 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; + }; ++ + cpu1: cpu@1 { + device_type = "cpu"; + reg = <0x1>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache1>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu1_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache1: l2-cache1 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; + }; ++ + cpu2: cpu@2 { + device_type = "cpu"; + reg = <0x2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache2>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu2_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache2: l2-cache2 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; + }; ++ + cpu3: cpu@3 { + device_type = "cpu"; + reg = <0x3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache3>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu3_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache3: l2-cache3 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; + }; ++ + cpu4: cpu@4 { + device_type = "cpu"; + reg = <0x10>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache4>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu4_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache4: l2-cache4 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; + }; ++ + cpu5: cpu@5 { + device_type = "cpu"; + reg = <0x11>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache5>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu5_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache5: l2-cache5 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; + }; ++ + cpu6: cpu@6 { + device_type = "cpu"; + reg = <0x12>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; +- + clock-frequency = <2000000000>; +- ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache6>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu6_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache6: l2-cache6 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; + }; ++ + cpu7: cpu@7 { + device_type = "cpu"; + reg = <0x13>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache7>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu7_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache7: l2-cache7 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; ++ }; ++ ++ cpu-map { ++ cluster0: cluster0 { ++ core0 { ++ cpu = <&cpu0>; ++ }; ++ core1 { ++ cpu = <&cpu1>; ++ }; ++ core2 { ++ cpu = <&cpu2>; ++ }; ++ core3 { ++ cpu = <&cpu3>; ++ }; ++ ++ cluster0_l3: l3-cache0 { ++ /* L3 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 4MB ++ * per-cluster. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <3>; ++ cache-size = <0x400000>; ++ cache-sets = <0x1000>; ++ cache-unified; ++ next-level-cache = <&l4_cache>; ++ }; ++ }; ++ ++ cluster1: cluster1 { ++ core0 { ++ cpu = <&cpu4>; ++ }; ++ core1 { ++ cpu = <&cpu5>; ++ }; ++ core2 { ++ cpu = <&cpu6>; ++ }; ++ core3 { ++ cpu = <&cpu7>; ++ }; ++ cluster1_l3: l3-cache1 { ++ /* L3 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 4MB ++ * per-cluster. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <3>; ++ cache-size = <0x400000>; ++ cache-sets = <0x1000>; ++ cache-unified; ++ next-level-cache = <&l4_cache>; ++ }; ++ }; + }; + }; + +@@ -150,6 +520,20 @@ soc { + #size-cells = <0x02>; + compatible = "simple-bus"; + ranges; ++ ++ l4_cache: l4-cache { ++ /* L4 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 16MB ++ * shared by the SoC. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <4>; ++ cache-size = <0x1000000>; ++ cache-sets = <0x4000>; ++ cache-unified; ++ }; + + clocks { + compatible = "simple-bus"; +@@ -160,6 +544,12 @@ device_clk: device_clk { + #clock-cells = <0>; + }; + ++ timer_clk: timer_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <50000000>; ++ #clock-cells = <0>; ++ }; ++ + csr_clk: csr_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; +@@ -170,35 +560,102 @@ csr_clk: csr_clk { + clint: clint@8000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, +- <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, +- <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, +- <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, +- <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, +- <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, +- <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, +- <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; ++ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, ++ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, ++ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, ++ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, ++ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, ++ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, ++ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; + reg = <0x00 0x8000000 0x00 0x100000>; + }; +- ++ + plic: plic@9000000 { + #interrupt-cells = <1>; + #address-cells = <0>; +- phandle = <0x01>; +- compatible = "ultrarisc,dp1000-plic"; ++ compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; + interrupt-controller; + interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, +- <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, +- <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, +- <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, +- <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, +- <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, +- <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, +- <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; ++ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, ++ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, ++ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, ++ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, ++ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, ++ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, ++ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; + reg = <0x00 0x9000000 0x00 0x4000000>; + riscv,max-priority = <0x07>; + riscv,ndev = <160>; + }; +- ++ ++ core_pvt: pvt@110D0000 { ++ compatible = "ultrarisc,dp1000-pvt"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x00 0x110D0000 0x00 0x0000D000>; ++ clock-frequency = <250000000>; ++ channels = <13>; ++ ++ #thermal-sensor-cells = <1>; ++ channel@0 { ++ label = "Core temp0"; ++ reg = <0>; ++ }; ++ ++ channel@1 { ++ label = "Core temp1"; ++ reg = <1>; ++ }; ++ ++ channel@2 { ++ label = "Core temp2"; ++ reg = <2>; ++ }; ++ ++ channel@3 { ++ label = "Core temp3"; ++ reg = <3>; ++ }; ++ ++ channel@4 { ++ label = "Core temp4"; ++ reg = <4>; ++ }; ++ ++ channel@5 { ++ label = "Core temp5"; ++ reg = <5>; ++ }; ++ channel@6 { ++ label = "Core temp6"; ++ reg = <6>; ++ }; ++ channel@7 { ++ label = "Core temp7"; ++ reg = <7>; ++ }; ++ channel@8 { ++ label = "Core temp8"; ++ reg = <8>; ++ }; ++ channel@9 { ++ label = "Core temp9"; ++ reg = <9>; ++ }; ++ channel@10 { ++ label = "Core temp10"; ++ reg = <10>; ++ }; ++ channel@11 { ++ label = "Cluster0 voltage"; ++ reg = <11>; ++ }; ++ channel@12 { ++ label = "Cluster1 voltage"; ++ reg = <12>; ++ }; ++ }; ++ + uart0: serial@20300000 { + interrupt-parent = <0x01>; + interrupts = <17>; +@@ -244,7 +701,7 @@ uart3: serial@20410000 { + }; + + spi0: spi@20320000 { +- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; ++ compatible = "snps,dw-apb-ssi"; + status = "okay"; + #address-cells = <0x01>; + #size-cells = <0x00>; +@@ -258,7 +715,7 @@ spi0: spi@20320000 { + }; + + spi1: spi@20420000 { +- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; ++ compatible = "snps,dw-apb-ssi"; + status = "okay"; + #address-cells = <0x01>; + #size-cells = <0x00>; +@@ -449,11 +906,11 @@ pcie_x16: pcie@21000000 { + num-lanes = <16>; + ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ +- <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ +- max-link-speed = <4>; ++ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ ++ max-link-speed = <16>; + interrupt-parent = <&plic>; +- interrupts = <43>, <44>, <45>, <46>, <47>, <48>; +- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupts = <43>, <44>, <45>, <46>, <47>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, +@@ -475,11 +932,11 @@ pcie_x4a: pcie@23000000 { + num-lanes = <4>; + ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ + <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ +- <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ + max-link-speed = <4>; + interrupt-parent = <&plic>; +- interrupts = <63>, <64>, <65>, <66>, <67>, <68>; +- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupts = <63>, <64>, <65>, <66>, <67>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, + <0x0 0x0 0x0 0x2 &plic 65>, +@@ -501,11 +958,11 @@ pcie_x4b: pcie@24000000 { + num-lanes = <4>; + ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ +- <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ + max-link-speed = <4>; + interrupt-parent = <&plic>; +- interrupts = <73>, <74>, <75>, <76>, <77>, <78>; +- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupts = <73>, <74>, <75>, <76>, <77>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, + <0x0 0x0 0x0 0x2 &plic 75>, +-- +2.53.0 + diff --git a/SPECS/linux-lts/0461-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch b/SPECS/linux-lts/0461-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch deleted file mode 100644 index 5fcf731d24..0000000000 --- a/SPECS/linux-lts/0461-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch +++ /dev/null @@ -1,730 +0,0 @@ -From d562b4d41d3ea85b9696fdce97dcf47fc485046b Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 13 Feb 2026 09:09:58 +0800 -Subject: [PATCH 461/467] RUYI: phy: spacemit: Add USB3/PCIe comb PHY driver - for Spacemit K3 - -The comb PHY on K3 requires to configure a syscon device for the -right mux configuration. And it requires calibration before any -usage. - -Add USB3/PCIe comb PHY driver for Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - drivers/phy/spacemit/Kconfig | 16 ++ - drivers/phy/spacemit/Makefile | 2 + - drivers/phy/spacemit/phy-k3-combo.c | 252 ++++++++++++++++++ - drivers/phy/spacemit/phy-k3-common.c | 372 +++++++++++++++++++++++++++ - drivers/phy/spacemit/phy-k3-common.h | 27 ++ - 5 files changed, 669 insertions(+) - create mode 100644 drivers/phy/spacemit/phy-k3-combo.c - create mode 100644 drivers/phy/spacemit/phy-k3-common.c - create mode 100644 drivers/phy/spacemit/phy-k3-common.h - -diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig -index 0136aee2e8a2..9a1e25592f25 100644 ---- a/drivers/phy/spacemit/Kconfig -+++ b/drivers/phy/spacemit/Kconfig -@@ -11,3 +11,19 @@ config PHY_SPACEMIT_K1_USB2 - help - Enable this to support K1 USB 2.0 PHY driver. This driver takes care of - enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. -+ -+config PHY_SPACEMIT_K3_COMMON_OPS -+ tristate -+ select MFD_SYSCON -+ select GENERIC_PHY -+ -+config PHY_SPACEMIT_K3_COMBO_PHY -+ tristate "SpacemiT K3 USB3/PCIe PHY support" -+ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF -+ depends on COMMON_CLK -+ select PHY_SPACEMIT_K3_COMMON_OPS -+ help -+ Enable this to support K3 USB3/PCIe combo PHY driver. This -+ driver takes care of enabling and clock setup and will be used -+ by K3 dwc3 driver. -+ If unsure, say N. -diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile -index fec0b425a948..df9b609d066f 100644 ---- a/drivers/phy/spacemit/Makefile -+++ b/drivers/phy/spacemit/Makefile -@@ -1,2 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0-only - obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o -+obj-$(CONFIG_PHY_SPACEMIT_K3_COMBO_PHY) += phy-k3-combo.o -+obj-$(CONFIG_PHY_SPACEMIT_K3_COMMON_OPS) += phy-k3-common.o -diff --git a/drivers/phy/spacemit/phy-k3-combo.c b/drivers/phy/spacemit/phy-k3-combo.c -new file mode 100644 -index 000000000000..abd0aad18893 ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-combo.c -@@ -0,0 +1,252 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * phy-k3-usb3.c - SpacemiT K3 Type-C Orientation Switch Driver -+ * -+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "phy-k3-common.h" -+ -+/* -+ * The PCIE/USB Subsystem on SpacemiT K3 have 3 single lane PIPE3 PHYs -+ * (PHY2/3/4) shared by PCIE PortC/D and USB3 PortB/C/D. -+ * -+ * PMUA_PCIE_SUBSYS_MGMT[4:0] -+ * -+ * bit4 = 0 : PCIe A X8 mode, all 8 lanes dedicated to PCIe Port A -+ * 1 : PHY lanes shared between PCIe or USB according to [3:0] -+ * -+ * All PHY matrix combinations according to [4:0]: -+ * -+ * 0x0X : PCIe-A X8 -+ * 0x10 : PCIe-C x2 (PHY2+PHY3) + PCIe-D x1 (PHY4) -+ * 0x11 : PCIe-C x2 (PHY2+PHY3) + USB-D (PHY4) -+ * 0x12 : PCIe-C x1 (PHY2) + USB-C (PHY3) -+ * 0x13 : PCIe-C x1 (PHY2) + USB-C (PHY3) + USB-D (PHY4) -+ * 0x14 : PCIe-C x1 (PHY3) + USB-B (PHY2) -+ * 0x15 : PCIe-C x1 (PHY3) + USB-B (PHY2) + USB-D (PHY4) -+ * 0x16 : USB-B (PHY2) + USB-C (PHY3) + PCIe D x1 (PHY4) -+ * 0x17 : USB-B (PHY2) + USB-C (PHY3) + USB-D (PHY4) -+ * -+ * So any USB Port B/C/D operation requires PCIe A X8 mode to be disabled. -+ */ -+#define PMUA_PCIE_SUBSYS_MGMT 0x1d8 -+#define PU_MATRIX_CONF_MASK GENMASK(4, 0) -+ -+#define COMBPHY_MAX_SUBPHYS 6 -+ -+struct k3_combo_phy { -+ struct device *dev; -+ struct k3_lane_group groups[COMBPHY_MAX_SUBPHYS]; -+ void __iomem *base; -+ struct regmap *apb_spare; -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group0 = { -+ .lanes = 2, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x0, 0x400 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group1 = { -+ .lanes = 2, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x100000, 0x100400 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group2 = { -+ .lanes = 1, -+ .config = 0x14, -+ .mask = 0x14, -+ .offsets = { -+ 0x200000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group3 = { -+ .lanes = 1, -+ .config = 0x12, -+ .mask = 0x12, -+ .offsets = { -+ 0x300000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group4 = { -+ .lanes = 1, -+ .config = 0x11, -+ .mask = 0x11, -+ .offsets = { -+ 0x400000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group5 = { -+ .lanes = 1, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x500000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data *k3_combphy_lane_datas[] = { -+ &k3_combphy_lane_group0, -+ &k3_combphy_lane_group1, -+ &k3_combphy_lane_group2, -+ &k3_combphy_lane_group3, -+ &k3_combphy_lane_group4, -+ &k3_combphy_lane_group5, -+}; -+ -+static int k3_combo_phy_init_lanes(struct k3_combo_phy *phy, unsigned int config) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(k3_combphy_lane_datas); i++) { -+ const struct k3_phy_lane_group_data *data = k3_combphy_lane_datas[i]; -+ struct k3_lane_group *lg = &phy->groups[i]; -+ const struct phy_ops *ops; -+ bool is_usb; -+ -+ is_usb = (data->mask & config) == data->config; -+ if (is_usb) -+ ops = &k3_usb3_phy_ops; -+ else -+ ops = &k3_pcie_phy_ops; -+ -+ dev_dbg(phy->dev, "phy %d is %s\n", i, is_usb ? "usb" : "pcie"); -+ -+ lg->phy = devm_phy_create(phy->dev, NULL, ops); -+ if (IS_ERR(lg->phy)) -+ return PTR_ERR(lg->phy); -+ -+ lg->is_pcie = !is_usb; -+ lg->data = data; -+ lg->base = phy->base; -+ phy_set_drvdata(lg->phy, lg); -+ } -+ -+ return 0; -+} -+ -+static int k3_combo_phy_update_config(struct regmap *apmu, unsigned int config) -+{ -+ if (config & ~PU_MATRIX_CONF_MASK) -+ return -EINVAL; -+ -+ return regmap_update_bits(apmu, PMUA_PCIE_SUBSYS_MGMT, PU_MATRIX_CONF_MASK, config); -+} -+ -+static struct phy *k3_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) -+{ -+ struct k3_combo_phy *phy = dev_get_drvdata(dev); -+ struct k3_lane_group *lg; -+ -+ if (args->args_count != 2) { -+ dev_err(dev, "Invalid number of arguments\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ if (args->args[0] >= ARRAY_SIZE(k3_combphy_lane_datas)) { -+ dev_err(dev, "Invalid PHY id\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ lg = &phy->groups[args->args[0]]; -+ -+ if ((lg->is_pcie && args->args[1] != PHY_TYPE_PCIE) || -+ (!lg->is_pcie && args->args[1] != PHY_TYPE_USB3)) { -+ dev_err(dev, "Invalid PHY mode\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ return lg->phy; -+} -+ -+static int k3_combo_phy_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct device_node *node = dev->of_node; -+ struct phy_provider *provider; -+ struct k3_combo_phy *phy; -+ struct regmap *apmu; -+ u32 config = 0; -+ int ret; -+ -+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); -+ if (!phy) -+ return -ENOMEM; -+ -+ phy->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(phy->base)) -+ return PTR_ERR(phy->base); -+ -+ phy->apb_spare = syscon_regmap_lookup_by_phandle(node, "spacemit,apb-spare"); -+ if (IS_ERR(phy->apb_spare)) -+ return dev_err_probe(dev, PTR_ERR(phy->apb_spare), -+ "Failed to fine APB SPARE syscon"); -+ -+ apmu = syscon_regmap_lookup_by_phandle_args(node, "spacemit,apmu", 1, &config); -+ if (IS_ERR(apmu)) -+ return dev_err_probe(dev, PTR_ERR(apmu), -+ "Failed to find APMU syscon"); -+ -+ ret = k3_combo_phy_update_config(apmu, config); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to set lane configuration"); -+ -+ phy->dev = dev; -+ platform_set_drvdata(pdev, phy); -+ -+ ret = k3_phy_calibrate(phy->apb_spare); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to calibrate phy"); -+ -+ ret = k3_combo_phy_init_lanes(phy, config); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to init lanes"); -+ -+ provider = devm_of_phy_provider_register(dev, k3_combo_phy_xlate); -+ if (IS_ERR(provider)) -+ return dev_err_probe(dev, PTR_ERR(provider), -+ "Failed to register provider\n"); -+ -+ return 0; -+} -+ -+static const struct of_device_id k3_combo_phy_of_match[] = { -+ { .compatible = "spacemit,k3-combo-phy" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, k3_combo_phy_of_match); -+ -+static struct platform_driver k3_combo_phy_driver = { -+ .probe = k3_combo_phy_probe, -+ .driver = { -+ .name = "spacemit,k3-combo-phy", -+ .of_match_table = k3_combo_phy_of_match, -+ }, -+}; -+module_platform_driver(k3_combo_phy_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K3 USB3/PCIe combo PHY driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/phy/spacemit/phy-k3-common.c b/drivers/phy/spacemit/phy-k3-common.c -new file mode 100644 -index 000000000000..840524cbe533 ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-common.c -@@ -0,0 +1,372 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "phy-k3-common.h" -+ -+/* PHY Registers */ -+#define PHY_VERSION 0x0 -+ -+#define PHY_RESET_CFG 0x04 -+ -+#define PHY_RESET_RXBUF_RST BIT(0) -+#define PHY_RESET_SOFT_RST_PCS BIT(1) -+#define PHY_RESET_SOFT_RST_AHB BIT(2) -+#define PHY_RESET_EN_SD_AFTER_LOCK BIT(6) -+ -+#define PHY_CLK_CFG 0x08 -+ -+#define PHY_CLK_PLL_READY BIT(0) -+#define PHY_CLK_TXCLK_INV BIT(2) -+#define PHY_CLK_RXCLK_EN BIT(3) -+#define PHY_CLK_TXCLK_EN BIT(4) -+#define PHY_CLK_PCLK_EN BIT(5) -+#define PHY_CLK_PIPE_PCLK_EN BIT(6) -+#define PHY_CLK_REFCLK_FREQ GENMASK(10, 7) -+#define PHY_CLK_REFCLK_24M 2 -+#define PHY_CLK_SW_INIT_DONE BIT(11) -+#define PHY_CLK_PU_SSC_OUT BIT(23) -+ -+#define PHY_MODE_CFG 0x0C -+ -+#define PHY_MODE_PCIE_INT_EN BIT(0) -+#define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8) -+#define PHY_MODE_LFPS_TPERIOD_USB 3 -+ -+#define PHY_PU_SEL 0x40 -+ -+#define PHY_PU_CFG_STATUS BIT(9) -+#define PHY_PU_OVRD_STATUS BIT(10) -+ -+#define PHY_PU_CK_REG 0x54 -+ -+#define PHY_PU_REFCLK_100 BIT(25) -+ -+#define PHY_PLL_REG1 0x58 -+ -+#define PHY_PLL_FREF_SEL GENMASK(15, 13) -+#define PHY_PLL_FREF_24M 0x1 -+#define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24) -+#define PHY_PLL_SSC_5000PPM 0xa -+#define PHY_PLL_SSC_MODE GENMASK(29, 28) -+#define PHY_PLL_SSC_MODE_CENTER_SPREAD 0 -+#define PHY_PLL_SSC_MODE_UP_SPREAD 1 -+#define PHY_PLL_SSC_MODE_DOWN_SPREAD 2 -+#define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3 -+ -+#define PHY_PLL_REG2 0x5c -+ -+#define PHY_PLL_SEL_REF100 BIT(21) -+ -+/* PHY RX Register Definitions */ -+#define PHY_RX_REG_A 0x60 -+ -+#define PHY_RX_REG0_RLOAD BIT(4) -+#define PHY_RX_REG1_RTERM GENMASK(11, 8) -+#define PHY_RX_REG1_RC_CALI GENMASK(15, 12) -+#define PHY_RX_REG2_CSEL GENMASK(19, 16) -+#define PHY_RX_REG2_FORCE_CSEL BIT(20) -+#define PHY_RX_REG2_PSEL GENMASK(23, 21) -+#define PHY_RX_REG3_I_LOAD GENMASK(26, 24) -+#define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27) -+#define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28) -+#define PHY_RX_REG3_RDEG1 GENMASK(31, 30) -+ -+#define PHY_RX_REG_B 0x64 -+ -+#define PHY_RX_REGB_MASK GENMASK(23, 0) -+ -+#define PHY_RX_REG4_RDEG2 GENMASK(2, 1) -+#define PHY_RX_REG4_ENVOS BIT(4) -+#define PHY_RX_REG4_RTERM_SEL BIT(5) -+#define PHY_RX_REG4_MANUAL_CFG BIT(7) -+#define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8) -+#define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12) -+#define PHY_RX_REG6_H1_REG GENMASK(19, 16) -+#define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20) -+#define PHY_RX_REG6_BYPASS_ADPT BIT(22) -+ -+#define PHY_ADPT_CFG0 0x140 -+#define PHY_ADPT_AFE_RST_OVRD_EN BIT(1) -+#define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4) -+ -+#define PHY_RXEQ_TIME 0xb4 -+#define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21) -+#define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22) -+#define PHY_RXEQ_TIME_AMP_SOC_650M 0 -+#define PHY_RXEQ_TIME_AMP_SOC_800M 1 -+#define PHY_RXEQ_TIME_AMP_SOC_870M 2 -+#define PHY_RXEQ_TIME_AMP_SOC_900M 3 -+#define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24) -+ -+#define PCIE_PU_ADDR_CLK_CFG 0x0008 -+#define PHY_CLK_PLL_READY BIT(0) -+#define PCIE_INITAL_TIMER GENMASK(6, 3) -+#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) -+#define CFG_SW_PHY_INIT_DONE BIT(11) -+ -+/* Lane RX/TX configuration (per‑lane, at lane_base) */ -+#define PCIE_RX_REG1 0x050 -+#define PCIE_TX_REG1 0x064 -+ -+#define PCIE_PLL_TIMEOUT 500000 -+#define PCIE_POLL_DELAY 500 -+ -+static int k3_usb3phy_init_single(struct k3_lane_group *lg, void __iomem *base) -+{ -+ struct phy *phy = lg->phy; -+ u32 val, tmp; -+ int ret; -+ -+ /* Do not wait CDR lock before sampling data */ -+ val = readl(base + PHY_RESET_CFG); -+ val = u32_replace_bits(val, 0, PHY_RESET_EN_SD_AFTER_LOCK); -+ writel(val, base + PHY_RESET_CFG); -+ -+ /* Power down 100MHz refclk buffer */ -+ val = readl(base + PHY_PU_CK_REG); -+ val = u32_replace_bits(val, 0, PHY_PU_REFCLK_100); -+ writel(val, base + PHY_PU_CK_REG); -+ -+ /* Program PLL REG1 configure the SSC */ -+ val = FIELD_PREP(PHY_PLL_SSC_MODE, PHY_PLL_SSC_MODE_DOWN_SPREAD1) | -+ FIELD_PREP(PHY_PLL_SSC_DEP_SEL, PHY_PLL_SSC_5000PPM) | -+ FIELD_PREP(PHY_PLL_FREF_SEL, PHY_PLL_FREF_24M); -+ writel(val, base + PHY_PLL_REG1); -+ -+ /* Un-select 100MHz PLL reference */ -+ val = readl(base + PHY_PLL_REG2); -+ val = u32_replace_bits(val, 0, PHY_PLL_SEL_REF100); -+ writel(val, base + PHY_PLL_REG2); -+ -+ /* USB LFPS period configuration */ -+ val = readl(base + PHY_MODE_CFG); -+ val = u32_replace_bits(val, PHY_MODE_LFPS_TPERIOD_USB, PHY_MODE_LFPS_TPERIOD); -+ writel(val, base + PHY_MODE_CFG); -+ -+ /* Force AFE adaptation reset */ -+ val = readl(base + PHY_ADPT_CFG0); -+ val |= PHY_ADPT_AFE_RST_OVRD_EN | PHY_ADPT_AFE_RST_OVRD_VAL; -+ writel(val, base + PHY_ADPT_CFG0); -+ -+ /* Override driver amplitude value to 900m */ -+ val = readl(base + PHY_RXEQ_TIME); -+ val |= PHY_RXEQ_TIME_OVRD_AMP_SOC; -+ val = u32_replace_bits(val, PHY_RXEQ_TIME_AMP_SOC_900M, PHY_RXEQ_TIME_CFG_AMP_SOC); -+ writel(val, base + PHY_RXEQ_TIME); -+ -+ /* Configure RX parameters */ -+ val = PHY_RX_REG0_RLOAD | -+ FIELD_PREP(PHY_RX_REG1_RTERM, 0x8) | -+ FIELD_PREP(PHY_RX_REG1_RC_CALI, 0x7) | -+ FIELD_PREP(PHY_RX_REG2_CSEL, 0x8) | -+ PHY_RX_REG2_FORCE_CSEL | -+ FIELD_PREP(PHY_RX_REG2_PSEL, 0x4) | -+ FIELD_PREP(PHY_RX_REG3_I_LOAD, 0x7) | -+ PHY_RX_REG3_SEL_CBOOST_CODE | -+ FIELD_PREP(PHY_RX_REG3_ADJ_BIAS, 0x1) | -+ FIELD_PREP(PHY_RX_REG3_RDEG1, 0x3); -+ writel(val, base + PHY_RX_REG_A); -+ -+ val = readl(base + PHY_RX_REG_B); -+ tmp = FIELD_PREP(PHY_RX_REG4_RDEG2, 0x2) | -+ PHY_RX_REG4_ENVOS | PHY_RX_REG4_RTERM_SEL | PHY_RX_REG4_MANUAL_CFG | -+ FIELD_PREP(PHY_RX_REG5_RCELL_VCM, 0x8) | -+ FIELD_PREP(PHY_RX_REG5_RCELL_BIAS, 0x8) | -+ FIELD_PREP(PHY_RX_REG6_H1_REG, 0x8) | -+ FIELD_PREP(PHY_RX_REG6_ADAPT_GAIN, 0x2); -+ val = u32_replace_bits(val, tmp, PHY_RX_REGB_MASK); -+ writel(val, base + PHY_RX_REG_B); -+ -+ /* -+ * Inform PHY that all PLL-related configuration is done. -+ * PLL will not start locking until PHY_CLK_SW_INIT_DONE is set. -+ */ -+ val = PHY_CLK_SW_INIT_DONE | PHY_CLK_PU_SSC_OUT | -+ FIELD_PREP(PHY_CLK_REFCLK_FREQ, PHY_CLK_REFCLK_24M) | -+ PHY_CLK_RXCLK_EN | PHY_CLK_TXCLK_EN | -+ PHY_CLK_PCLK_EN | PHY_CLK_PIPE_PCLK_EN; -+ writel(val, base + PHY_CLK_CFG); -+ -+ ret = readl_poll_timeout(base + PHY_CLK_CFG, val, -+ (val & PHY_CLK_PLL_READY), -+ PCIE_POLL_DELAY, PCIE_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(&phy->dev, "PHY PLL polling timeout\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int k3_usb3phy_init(struct phy *phy) -+{ -+ struct k3_lane_group *lg = phy_get_drvdata(phy); -+ int ret, i; -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ ret = k3_usb3phy_init_single(lg, lg->base + lg->data->offsets[i]); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+const struct phy_ops k3_usb3_phy_ops = { -+ .init = k3_usb3phy_init, -+ .owner = THIS_MODULE, -+}; -+EXPORT_SYMBOL_GPL(k3_usb3_phy_ops); -+ -+static int k3_pcie_phy_init(struct phy *phy) -+{ -+ struct k3_lane_group *lg = phy_get_drvdata(phy); -+ void __iomem *phy_base = lg->base + lg->data->offsets[0]; -+ u32 val; -+ int ret; -+ int i; -+ -+ val = readl(phy_base + PHY_PLL_REG1); -+ val = u32_replace_bits(val, 0x2, GENMASK(15, 12)); -+ writel(val, phy_base + PHY_PLL_REG1); -+ -+ val = readl(phy_base + PHY_PLL_REG2); -+ val = u32_replace_bits(val, 0, BIT(21)); -+ writel(val, phy_base + PHY_PLL_REG2); -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ void __iomem *lane_base = lg->base + lg->data->offsets[i]; -+ -+ val = readl(lane_base + PCIE_RX_REG1); -+ val = u32_replace_bits(val, 0, 0x3); -+ writel(val, lane_base + PCIE_RX_REG1); -+ } -+ -+ val = readl(phy_base + PHY_PLL_REG2); -+ val |= BIT(20); -+ writel(val, phy_base + PHY_PLL_REG2); -+ -+ writel(0x00006505, phy_base + PCIE_RX_REG1); -+ -+ /* pll_reg1 of lane0, disable SSC: pll[27:24] = 0 */ -+ val = readl(phy_base + PHY_PLL_REG1); -+ val = u32_replace_bits(val, 0, GENMASK(27, 24)); -+ writel(val, phy_base + PHY_PLL_REG1); -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ void __iomem *lane_base = lg->base + lg->data->offsets[i]; -+ -+ /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */ -+ val = readl(lane_base + PHY_PU_SEL); -+ val = u32_replace_bits(val, 1, BIT(13)); -+ writel(val, lane_base + PHY_PU_SEL); -+ -+ /* disable en_sample_data_after_cdr_locked */ -+ val = readl(lane_base + PHY_RESET_CFG); -+ val = u32_replace_bits(val, 0, BIT(6)); -+ writel(val, lane_base + PHY_RESET_CFG); -+ -+ /* Dynamic Lock */ -+ val = readl(lane_base + PHY_MODE_CFG); -+ val = u32_replace_bits(val, 1, BIT(2)); -+ writel(val, lane_base + PHY_MODE_CFG); -+ -+ val = FIELD_PREP(GENMASK(7, 0), 0x10) | -+ FIELD_PREP(GENMASK(15, 8), 0x78) | -+ FIELD_PREP(GENMASK(23, 16), 0x98) | -+ FIELD_PREP(GENMASK(31, 24), 0xdf); -+ writel(val, lane_base + PHY_RX_REG_A); -+ -+ val = readl(lane_base + PHY_RX_REG_B); -+ val &= ~PHY_RX_REGB_MASK; -+ val |= FIELD_PREP(GENMASK(7, 0), 0xb4) | -+ FIELD_PREP(GENMASK(15, 8), 0x88) | -+ FIELD_PREP(GENMASK(23, 16), 0x28); -+ writel(val, lane_base + PHY_RX_REG_B); -+ -+ /* Set init done */ -+ val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG); -+ val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE); -+ writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG); -+ } -+ -+ ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val, -+ (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY, -+ PCIE_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(&lg->phy->dev, "PHY PLL lock timeout\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+const struct phy_ops k3_pcie_phy_ops = { -+ .init = k3_pcie_phy_init, -+ .owner = THIS_MODULE, -+}; -+EXPORT_SYMBOL_GPL(k3_pcie_phy_ops); -+ -+/* PHY rcal init requires APB_SPARE regmap access */ -+ -+#define APB_SPARE_PU_CAL 0x178 -+#define PU_CAL BIT(17) -+ -+#define APB_SPARE_RCAL_HSIO 0x17c -+#define APB_SPARE_PU_CAL_DONE BIT(8) -+#define RCAL_OVRD_PTRIM GENMASK(23, 20) -+#define RCAL_OVRD_NTRIM GENMASK(27, 24) -+#define RCAL_OVRD_PTRIM_EN BIT(28) -+#define RCAL_OVRD_NTRIM_EN BIT(29) -+#define RCAL_OVRD_STABLE_VAL BIT(30) -+#define RCAL_OVRD_STABLE_EN BIT(31) -+ -+#define RCAL_OVRD_TRIM_EN (RCAL_OVRD_NTRIM_EN | RCAL_OVRD_PTRIM_EN) -+#define RCAL_OVRD_TRIM_MASK (RCAL_OVRD_NTRIM | RCAL_OVRD_PTRIM) -+ -+#define PU_CAL_TIMEOUT 2000000 -+ -+static DEFINE_MUTEX(calibrate_lock); -+ -+int k3_phy_calibrate(struct regmap *apb_spare) -+{ -+ unsigned int val = 0; -+ int ret; -+ -+ guard(mutex)(&calibrate_lock); -+ -+ regmap_read(apb_spare, APB_SPARE_RCAL_HSIO, &val); -+ if (val & APB_SPARE_PU_CAL_DONE) -+ return 0; -+ -+ regmap_update_bits(apb_spare, APB_SPARE_PU_CAL, PU_CAL, -+ PU_CAL); -+ -+ ret = regmap_read_poll_timeout(apb_spare, APB_SPARE_RCAL_HSIO, -+ val, (val & APB_SPARE_PU_CAL_DONE), PCIE_POLL_DELAY, -+ PU_CAL_TIMEOUT); -+ -+ if (ret) -+ regmap_update_bits(apb_spare, APB_SPARE_RCAL_HSIO, -+ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | -+ RCAL_OVRD_TRIM_MASK | RCAL_OVRD_STABLE_EN, -+ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | -+ FIELD_PREP(RCAL_OVRD_NTRIM, 0x6) | -+ FIELD_PREP(RCAL_OVRD_PTRIM, 0xa) | -+ RCAL_OVRD_STABLE_EN); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(k3_phy_calibrate); -+ -+MODULE_DESCRIPTION("SpacemiT K3 PHY common ops"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/phy/spacemit/phy-k3-common.h b/drivers/phy/spacemit/phy-k3-common.h -new file mode 100644 -index 000000000000..49009c3c313a ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-common.h -@@ -0,0 +1,27 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef _PHY_K3_COMMON_H -+#define _PHY_K3_COMMON_H -+ -+#include -+ -+struct k3_phy_lane_group_data { -+ u32 lanes; -+ u8 config; -+ u8 mask; -+ u32 offsets[] __counted_by(lanes); -+}; -+ -+struct k3_lane_group { -+ const struct k3_phy_lane_group_data *data; -+ void __iomem *base; -+ struct phy *phy; -+ bool is_pcie; -+}; -+ -+extern const struct phy_ops k3_pcie_phy_ops; -+extern const struct phy_ops k3_usb3_phy_ops; -+ -+int k3_phy_calibrate(struct regmap *apb_spare); -+ -+#endif --- -2.53.0 - diff --git a/SPECS/linux-lts/0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch b/SPECS/linux-lts/0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch new file mode 100644 index 0000000000..f7231a5dd3 --- /dev/null +++ b/SPECS/linux-lts/0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch @@ -0,0 +1,102 @@ +From 360a4acac1e14c683370c4ffa8f3e85733ca0207 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Sat, 24 Jan 2026 08:48:53 +0800 +Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: Add USB2.0 support + +FROM: https://github.com/spacemit-com/linux/commit/6f1578894e4484f8a6724aceff099d2e90450e10 + +The USB2.0 controller on Pico-ITX board connnect to a Terminus FE1.1 Hub +which fully USB2.0 protocol compliant and provides 4 ports. + +Signed-off-by: Yixun Lan +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 25 ++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++ + 2 files changed, 56 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 61cbf924830b..ac965ec83f2c 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -33,6 +33,15 @@ reg_aux_vcc5v: regulator-aux-vcc5v { + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; ++ ++ aux_vcc3v3: regulator-aux-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "AUX_VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + }; + + &i2c8 { +@@ -255,3 +264,19 @@ &uart0 { + pinctrl-0 = <&uart0_0_cfg>; + status = "okay"; + }; ++ ++&usb2_host { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub@1 { ++ compatible = "usb1a40,0101"; ++ reg = <1>; ++ vdd-supply = <&aux_vcc3v3>; ++ }; ++}; ++ ++&usb2_phy { ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index ed046714a7ac..1b86c872accb 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -637,6 +637,37 @@ pdma: dma-controller@d4000000 { + status = "disabled"; + }; + ++ usb2_host: usb@c0a00000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0xc0a00000 0x0 0x10000>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB2_AHB>, ++ <&syscon_apmu RESET_APMU_USB2_VCC>, ++ <&syscon_apmu RESET_APMU_USB2_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ phys = <&usb2_phy>; ++ phy-names = "usb2-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ dr_mode = "host"; ++ maximum-speed = "high-speed"; ++ status = "disabled"; ++ }; ++ ++ usb2_phy: phy@c0a20000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0xc0a20000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0462-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch b/SPECS/linux-lts/0462-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch deleted file mode 100644 index bf914252d4..0000000000 --- a/SPECS/linux-lts/0462-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 115adac703e8d0d67045f2ed4fe1a495ab4b5448 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 27 Feb 2026 09:46:06 +0800 -Subject: [PATCH 462/467] RUYI: riscv: dts: spacemit: k3: add USB controller - and USB phy support - -Add all USB device node to the Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++ - 2 files changed, 55 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index ac965ec83f2c..acfbb5029c15 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -183,6 +183,11 @@ dldo7: dldo7 { - }; - }; - -+&combophy { -+ spacemit,apmu = <&syscon_apmu 0x11>; -+ status = "okay"; -+}; -+ - ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; -@@ -280,3 +285,11 @@ hub@1 { - &usb2_phy { - status = "okay"; - }; -+ -+&usb3d_u2phy { -+ status = "okay"; -+}; -+ -+&usb3d { -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 66dcabd0a815..130828ca3b43 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -7,6 +7,7 @@ - #include - #include - #include -+#include - - /dts-v1/; - -@@ -637,6 +638,47 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ usb3d: usb@81a00000 { -+ compatible = "spacemit,k3-dwc3"; -+ reg = <0x0 0x81a00000 0x0 0x10000>; -+ interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&saplic>; -+ clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; -+ clock-names = "usbdrd30"; -+ resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, -+ <&syscon_apmu RESET_APMU_USB3_D_VCC>, -+ <&syscon_apmu RESET_APMU_USB3_D_PHY>; -+ reset-names = "ahb", "vcc", "phy"; -+ phys = <&usb3d_u2phy>, -+ <&combophy 4 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi"; -+ snps,dis_enblslpm_quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ snps,parkmode-disable-ss-quirk; -+ dr_mode = "host"; -+ status = "disabled"; -+ }; -+ -+ usb3d_u2phy: phy@81b00000 { -+ compatible = "spacemit,k3-usb2-phy"; -+ reg = <0x0 0x81b00000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ combophy: phy@81d00000 { -+ compatible = "spacemit,k3-combo-phy"; -+ reg = <0x0 0x81d00000 0x0 0x600000>; -+ #phy-cells = <2>; -+ spacemit,apb-spare = <&pll>; -+ status = "disabled"; -+ }; -+ - usb2_host: usb@c0a00000 { - compatible = "spacemit,k3-dwc3"; - reg = <0x0 0xc0a00000 0x0 0x10000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0463-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch b/SPECS/linux-lts/0463-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch deleted file mode 100644 index e319ecab6f..0000000000 --- a/SPECS/linux-lts/0463-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch +++ /dev/null @@ -1,261 +0,0 @@ -From 14ecb0eaa2ab52030c7f36a293df59f07bdc1bb0 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Tue, 24 Mar 2026 11:06:24 +0800 -Subject: [PATCH 463/467] RUYI: riscv: dts: spacemit: k3: Add PCIe device node - -Add all PCIe device node for Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 ++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 150 +++++++++++++++++++ - 3 files changed, 212 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index acfbb5029c15..f24ada15f182 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -264,6 +264,35 @@ uboot@210000 { - }; - }; - -+&pcie0_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie0_0_cfg>; -+ phys = <&combophy 0 PHY_TYPE_PCIE>, -+ <&combophy 1 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0", "pcie-phy1"; -+ num-lanes = <4>; -+ status = "okay"; -+}; -+ -+&pcie2_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_cfg>; -+ phys = <&combophy 2 PHY_TYPE_PCIE>, -+ <&combophy 3 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0", "pcie-phy1"; -+ num-lanes = <2>; -+ status = "okay"; -+}; -+ -+&pcie4_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie4_0_cfg>; -+ phys = <&combophy 5 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0"; -+ num-lanes = <1>; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_0_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index 846d5e8cc783..5a817610101b 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -710,4 +710,37 @@ uart0-0-pins { - drive-strength = <25>; - }; - }; -+ -+ pcie0_0_cfg: pcie0-0-cfg { -+ pcie0-0-pins { -+ pinmux = , /* pcie0 perst */ -+ ; /* pcie0 clkreq */ -+ -+ bias-pull-up = <1>; -+ drive-strength = <33>; -+ power-source = <1800>; -+ }; -+ }; -+ -+ pcie2_0_cfg: pcie2-0-cfg { -+ pcie2-0-pins { -+ pinmux = , /* pcie2 perst */ -+ ; /* pcie2 clkreq */ -+ -+ drive-strength = <38>; -+ power-source = <3300>; -+ }; -+ }; -+ -+ pcie4_0_cfg: pcie4-0-cfg { -+ pcie4-0-pins { -+ pinmux = , /* pcie4 perst */ -+ , /* pcie4 wake */ -+ ; /* pcie4 clkreq */ -+ -+ bias-pull-up = <1>; -+ drive-strength = <33>; -+ power-source = <1800>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 130828ca3b43..6adfbd505e9e 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -638,6 +638,156 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ pcie0_rc: pcie@80000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80000000 0x0 0x00001000>, -+ <0x0 0x80100000 0x0 0x00001000>, -+ <0x0 0x80300000 0x0 0x00003f20>, -+ <0x11 0x00000000 0x0 0x00010000>, -+ <0x0 0x82900000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTA_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTA_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTA_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_A_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_A_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_A_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ linux,pci-domain = <0>; -+ spacemit,apmu = <&syscon_apmu 0x1f0>; -+ status = "disabled"; -+ }; -+ -+ pcie1_rc: pcie@80400000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80400000 0x0 0x00001000>, -+ <0x0 0x80500000 0x0 0x00001000>, -+ <0x0 0x80700000 0x0 0x00003f20>, -+ <0x11 0x80000000 0x0 0x00010000>, -+ <0x0 0x82c00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTB_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTB_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTB_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00010000 0x11 0x80010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x80110000 0x11 0x80110000 0x0 0x7fef0000>, -+ <0x43000000 0x16 0x00000000 0x16 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_B_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_B_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_B_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ linux,pci-domain = <1>; -+ spacemit,apmu = <&syscon_apmu 0x1d0>; -+ status = "disabled"; -+ }; -+ -+ pcie2_rc: pcie@80800000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80800000 0x0 0x00001000>, -+ <0x0 0x80900000 0x0 0x00001000>, -+ <0x0 0x80b00000 0x0 0x00003f20>, -+ <0x12 0x00000000 0x0 0x00010000>, -+ <0x0 0x82d00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTC_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTC_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTC_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00000000 0x12 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x12 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x15 0x00000000 0x15 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_C_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_C_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_C_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <2>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1c8>; -+ status = "disabled"; -+ }; -+ -+ pcie3_rc: pcie@80c00000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80c00000 0x0 0x00001000>, -+ <0x0 0x80d00000 0x0 0x00001000>, -+ <0x0 0x80f00000 0x0 0x00003f20>, -+ <0x12 0x80000000 0x0 0x00010000>, -+ <0x0 0x82a00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTD_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTD_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTD_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00010000 0x12 0x80010000 0x0 0x100000>, -+ <0x02000000 0x0 0x80110000 0x12 0x80110000 0x0 0x3fef0000>, -+ <0x43000000 0x14 0x00000000 0x14 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_D_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_D_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_D_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <3>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1e0>; -+ status = "disabled"; -+ }; -+ -+ pcie4_rc: pcie@81000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x81000000 0x0 0x00001000>, -+ <0x0 0x81100000 0x0 0x00001000>, -+ <0x0 0x81300000 0x0 0x00003f20>, -+ <0x12 0xc0000000 0x0 0x00010000>, -+ <0x0 0x82b00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTE_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTE_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTE_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00000000 0x12 0xc0010000 0x0 0x100000>, -+ <0x02000000 0x0 0xc0110000 0x12 0xc0110000 0x0 0x3fef0000>, -+ <0x43000000 0x13 0x00000000 0x13 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_E_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_E_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_E_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <4>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1e8>; -+ status = "disabled"; -+ }; -+ - usb3d: usb@81a00000 { - compatible = "spacemit,k3-dwc3"; - reg = <0x0 0x81a00000 0x0 0x10000>; --- -2.53.0 - diff --git a/SPECS/linux-lts/0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch b/SPECS/linux-lts/0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch new file mode 100644 index 0000000000..7871de10b3 --- /dev/null +++ b/SPECS/linux-lts/0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch @@ -0,0 +1,145 @@ +From 8b65d5e0ae467754eccf77dddcd58ae11ea35cdd Mon Sep 17 00:00:00 2001 +From: Zhang Meng +Date: Mon, 5 Jan 2026 20:05:04 +0800 +Subject: [RUYI PATCH] SPACEMIT: riscv: uaccess: don't use vector if buffer is + not cacheable + +FROM: https://github.com/spacemit-com/linux-6.18/commit/9168f7e0c6bfdcfa3b6a64a4d45e3cd68a81618f + +Change-Id: I040d597ee246777767f7be747fa9202154524538 +[ Vivian: Rebase and move check into enter_vector_usercopy ] +Signed-off-by: Vivian Wang +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/uaccess.h | 5 +++ + arch/riscv/lib/Makefile | 1 + + arch/riscv/lib/riscv_v_helpers.c | 5 +++ + arch/riscv/lib/uaccess_cache_check.c | 65 ++++++++++++++++++++++++++++ + 4 files changed, 76 insertions(+) + create mode 100644 arch/riscv/lib/uaccess_cache_check.c + +diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h +index 6aef591a6bfc..b028208b05ec 100644 +--- a/arch/riscv/include/asm/uaccess.h ++++ b/arch/riscv/include/asm/uaccess.h +@@ -487,6 +487,11 @@ static inline void user_access_restore(unsigned long enabled) { } + if (__asm_copy_from_user_sum_enabled(_dst, _src, _len)) \ + goto label; + ++/* Memory cacheability check for vector uaccess optimization */ ++#ifdef CONFIG_RISCV_ISA_V ++int is_cacheable_safe(const void *addr); ++#endif ++ + #else /* CONFIG_MMU */ + #include + #endif /* CONFIG_MMU */ +diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile +index 735d0b665536..43fe69db9803 100644 +--- a/arch/riscv/lib/Makefile ++++ b/arch/riscv/lib/Makefile +@@ -14,6 +14,7 @@ endif + lib-y += csum.o + ifeq ($(CONFIG_MMU), y) + lib-$(CONFIG_RISCV_ISA_V) += uaccess_vector.o ++lib-$(CONFIG_RISCV_ISA_V) += uaccess_cache_check.o + endif + lib-$(CONFIG_MMU) += uaccess.o + lib-$(CONFIG_64BIT) += tishift.o +diff --git a/arch/riscv/lib/riscv_v_helpers.c b/arch/riscv/lib/riscv_v_helpers.c +index 7bbdfc6d4552..7ab2cea280f8 100644 +--- a/arch/riscv/lib/riscv_v_helpers.c ++++ b/arch/riscv/lib/riscv_v_helpers.c +@@ -8,6 +8,7 @@ + + #include + #include ++#include + + #ifdef CONFIG_MMU + #include +@@ -28,6 +29,10 @@ asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n, + if (!may_use_simd()) + goto fallback; + ++ /* HACK */ ++ if (!is_cacheable_safe(dst) || !is_cacheable_safe(src)) ++ goto fallback; ++ + kernel_vector_begin(); + remain = enable_sum ? __asm_vector_usercopy(dst, src, n) : + __asm_vector_usercopy_sum_enabled(dst, src, n); +diff --git a/arch/riscv/lib/uaccess_cache_check.c b/arch/riscv/lib/uaccess_cache_check.c +new file mode 100644 +index 000000000000..0b0996fa2d37 +--- /dev/null ++++ b/arch/riscv/lib/uaccess_cache_check.c +@@ -0,0 +1,65 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Memory cacheability check for RISC-V uaccess optimization ++ * ++ * This file provides a C function that can be called from assembly ++ * to determine if a buffer is cacheable before using vector instructions. ++ */ ++ ++#include ++#include ++#include ++ ++/** ++ * is_cacheable_safe - Check if memory buffer is cacheable ++ * @addr: Virtual address to check (kernel or user space) ++ * ++ * Returns: 1 if cacheable, 0 if non-cacheable ++ * ++ * This function is designed to be called from assembly code in uaccess.S ++ * to determine if vector instructions are safe to use for memory copy. ++ * ++ * Non-cacheable memory (device IO, DMA coherent buffers) should not use ++ * vector instructions as they may cause cache coherency issues. ++ * ++ * Handles both kernel and user space addresses safely: ++ * - Kernel direct mapping: Always cacheable ++ * - Kernel vmalloc: Check VM flags ++ * - User space: Check page table (most are cacheable) ++ * - ioremap/DMA: Non-cacheable ++ */ ++int is_cacheable_safe(const void *addr) ++{ ++ unsigned long vaddr = (unsigned long)addr; ++ ++ /* Kernel direct mapped memory - always cacheable */ ++ if (virt_addr_valid(addr)) ++ return 1; ++ ++ if (vaddr < TASK_SIZE) { ++ /* ++ * User space address, Determine it as a cacheable buffer, ++ * maybe not safe!! ++ */ ++ return 1; ++ } ++ ++ /* Check if it's a vmalloc region (kernel virtual address) */ ++ if (is_vmalloc_addr(addr)) { ++ struct vm_struct *vm; ++ ++ vm = find_vm_area(addr); ++ if (!vm) ++ return 0; ++ ++ /* Exclude ioremap and DMA coherent buffers */ ++ if (vm->flags & (VM_IOREMAP | VM_DMA_COHERENT)) ++ return 0; ++ ++ /* Normal vmalloc - cacheable */ ++ return 1; ++ } ++ ++ /* Unknown kernel region - assume non-cacheable for safety */ ++ return 0; ++} +-- +2.53.0 + diff --git a/SPECS/linux-lts/0464-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch b/SPECS/linux-lts/0464-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch deleted file mode 100644 index cd7020b4ac..0000000000 --- a/SPECS/linux-lts/0464-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch +++ /dev/null @@ -1,34 +0,0 @@ -From a36a6a20bb6a9f93f79425be30e4469453576929 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 20 May 2026 23:28:15 +0800 -Subject: [PATCH 464/467] RUYI: PCI: add SpacemiT vendor id and its K3 device - id to pci_ids - -The SpacemiT K3 chip's root complex needs to be listed in the allowlist -of rtw89 driver to allow 36-bit DMA. - -Add the vendor and device IDs to pci_ids.h header file. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - include/linux/pci_ids.h | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h -index 7c01548a6ddb..e5a5700f7c8c 100644 ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -2643,6 +2643,9 @@ - #define PCI_VENDOR_ID_SUNIX 0x1fd4 - #define PCI_DEVICE_ID_SUNIX_1999 0x1999 - -+#define PCI_VENDOR_ID_SPACEMIT 0x201f -+#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 -+ - #define PCI_VENDOR_ID_HINT 0x3388 - #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 - --- -2.53.0 - diff --git a/SPECS/linux-lts/0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch b/SPECS/linux-lts/0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch new file mode 100644 index 0000000000..2a03ed4e12 --- /dev/null +++ b/SPECS/linux-lts/0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch @@ -0,0 +1,90 @@ +From 675808049c603e6935816557a160a1d7f6eb5495 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 13 Feb 2026 09:01:58 +0800 +Subject: [RUYI PATCH] RUYI: dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb + phy support + +The USB3/PCIe comb PHY on the K3 is a complex PHY group that +can provide multiple phy for both PCIe and USB controller. +Its mux configuration is controlled by the APMU syscon device. + +Signed-off-by: Inochi Amaoto +Signed-off-by: Han Gao +--- + .../bindings/phy/spacemit,k3-combo-phy.yaml | 64 +++++++++++++++++++ + 1 file changed, 64 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml +new file mode 100644 +index 000000000000..eafc753b7e9b +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml +@@ -0,0 +1,64 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Spacemit K3 PCIE/USB3 Comb PHY ++ ++maintainers: ++ - Inochi Amaoto ++ ++properties: ++ compatible: ++ const: spacemit,k3-combo-phy ++ ++ reg: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 2 ++ description: ++ The first one is phy id, the second one is phy type. ++ ++ spacemit,apb-spare: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: ++ Phandle to APB SPARE system controller interface, used for ++ PHY calibration. ++ ++ spacemit,apmu: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle of APMU syscon ++ - description: configuration of the PHY lanes ++ description: | ++ Phandle to control PHY mux configuration. The configuration ++ is described as follows: ++ bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode ++ bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode ++ bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode ++ bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode ++ bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode ++ ++ The bit[3:0] is only valid when bit 4 is 1. ++ ++required: ++ - compatible ++ - reg ++ - "#phy-cells" ++ - spacemit,apb-spare ++ - spacemit,apmu ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@81d00000 { ++ compatible = "spacemit,k3-combo-phy"; ++ reg = <0x81d00000 0x600000>; ++ #phy-cells = <2>; ++ spacemit,apb-spare = <&apb_spare>; ++ spacemit,apmu = <&apmu 0x00>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch b/SPECS/linux-lts/0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch new file mode 100644 index 0000000000..4c1686add5 --- /dev/null +++ b/SPECS/linux-lts/0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch @@ -0,0 +1,730 @@ +From 4ee622c1f03b3a5e9d6df7f54f612202f9462d8c Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 13 Feb 2026 09:09:58 +0800 +Subject: [RUYI PATCH] RUYI: phy: spacemit: Add USB3/PCIe comb PHY driver for + Spacemit K3 + +The comb PHY on K3 requires to configure a syscon device for the +right mux configuration. And it requires calibration before any +usage. + +Add USB3/PCIe comb PHY driver for Spacemit K3. + +Signed-off-by: Inochi Amaoto +Signed-off-by: Han Gao +--- + drivers/phy/spacemit/Kconfig | 16 ++ + drivers/phy/spacemit/Makefile | 2 + + drivers/phy/spacemit/phy-k3-combo.c | 252 ++++++++++++++++++ + drivers/phy/spacemit/phy-k3-common.c | 372 +++++++++++++++++++++++++++ + drivers/phy/spacemit/phy-k3-common.h | 27 ++ + 5 files changed, 669 insertions(+) + create mode 100644 drivers/phy/spacemit/phy-k3-combo.c + create mode 100644 drivers/phy/spacemit/phy-k3-common.c + create mode 100644 drivers/phy/spacemit/phy-k3-common.h + +diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig +index 0136aee2e8a2..9a1e25592f25 100644 +--- a/drivers/phy/spacemit/Kconfig ++++ b/drivers/phy/spacemit/Kconfig +@@ -11,3 +11,19 @@ config PHY_SPACEMIT_K1_USB2 + help + Enable this to support K1 USB 2.0 PHY driver. This driver takes care of + enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. ++ ++config PHY_SPACEMIT_K3_COMMON_OPS ++ tristate ++ select MFD_SYSCON ++ select GENERIC_PHY ++ ++config PHY_SPACEMIT_K3_COMBO_PHY ++ tristate "SpacemiT K3 USB3/PCIe PHY support" ++ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF ++ depends on COMMON_CLK ++ select PHY_SPACEMIT_K3_COMMON_OPS ++ help ++ Enable this to support K3 USB3/PCIe combo PHY driver. This ++ driver takes care of enabling and clock setup and will be used ++ by K3 dwc3 driver. ++ If unsure, say N. +diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile +index fec0b425a948..df9b609d066f 100644 +--- a/drivers/phy/spacemit/Makefile ++++ b/drivers/phy/spacemit/Makefile +@@ -1,2 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o ++obj-$(CONFIG_PHY_SPACEMIT_K3_COMBO_PHY) += phy-k3-combo.o ++obj-$(CONFIG_PHY_SPACEMIT_K3_COMMON_OPS) += phy-k3-common.o +diff --git a/drivers/phy/spacemit/phy-k3-combo.c b/drivers/phy/spacemit/phy-k3-combo.c +new file mode 100644 +index 000000000000..abd0aad18893 +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-combo.c +@@ -0,0 +1,252 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * phy-k3-usb3.c - SpacemiT K3 Type-C Orientation Switch Driver ++ * ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-k3-common.h" ++ ++/* ++ * The PCIE/USB Subsystem on SpacemiT K3 have 3 single lane PIPE3 PHYs ++ * (PHY2/3/4) shared by PCIE PortC/D and USB3 PortB/C/D. ++ * ++ * PMUA_PCIE_SUBSYS_MGMT[4:0] ++ * ++ * bit4 = 0 : PCIe A X8 mode, all 8 lanes dedicated to PCIe Port A ++ * 1 : PHY lanes shared between PCIe or USB according to [3:0] ++ * ++ * All PHY matrix combinations according to [4:0]: ++ * ++ * 0x0X : PCIe-A X8 ++ * 0x10 : PCIe-C x2 (PHY2+PHY3) + PCIe-D x1 (PHY4) ++ * 0x11 : PCIe-C x2 (PHY2+PHY3) + USB-D (PHY4) ++ * 0x12 : PCIe-C x1 (PHY2) + USB-C (PHY3) ++ * 0x13 : PCIe-C x1 (PHY2) + USB-C (PHY3) + USB-D (PHY4) ++ * 0x14 : PCIe-C x1 (PHY3) + USB-B (PHY2) ++ * 0x15 : PCIe-C x1 (PHY3) + USB-B (PHY2) + USB-D (PHY4) ++ * 0x16 : USB-B (PHY2) + USB-C (PHY3) + PCIe D x1 (PHY4) ++ * 0x17 : USB-B (PHY2) + USB-C (PHY3) + USB-D (PHY4) ++ * ++ * So any USB Port B/C/D operation requires PCIe A X8 mode to be disabled. ++ */ ++#define PMUA_PCIE_SUBSYS_MGMT 0x1d8 ++#define PU_MATRIX_CONF_MASK GENMASK(4, 0) ++ ++#define COMBPHY_MAX_SUBPHYS 6 ++ ++struct k3_combo_phy { ++ struct device *dev; ++ struct k3_lane_group groups[COMBPHY_MAX_SUBPHYS]; ++ void __iomem *base; ++ struct regmap *apb_spare; ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group0 = { ++ .lanes = 2, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x0, 0x400 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group1 = { ++ .lanes = 2, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x100000, 0x100400 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group2 = { ++ .lanes = 1, ++ .config = 0x14, ++ .mask = 0x14, ++ .offsets = { ++ 0x200000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group3 = { ++ .lanes = 1, ++ .config = 0x12, ++ .mask = 0x12, ++ .offsets = { ++ 0x300000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group4 = { ++ .lanes = 1, ++ .config = 0x11, ++ .mask = 0x11, ++ .offsets = { ++ 0x400000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group5 = { ++ .lanes = 1, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x500000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data *k3_combphy_lane_datas[] = { ++ &k3_combphy_lane_group0, ++ &k3_combphy_lane_group1, ++ &k3_combphy_lane_group2, ++ &k3_combphy_lane_group3, ++ &k3_combphy_lane_group4, ++ &k3_combphy_lane_group5, ++}; ++ ++static int k3_combo_phy_init_lanes(struct k3_combo_phy *phy, unsigned int config) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(k3_combphy_lane_datas); i++) { ++ const struct k3_phy_lane_group_data *data = k3_combphy_lane_datas[i]; ++ struct k3_lane_group *lg = &phy->groups[i]; ++ const struct phy_ops *ops; ++ bool is_usb; ++ ++ is_usb = (data->mask & config) == data->config; ++ if (is_usb) ++ ops = &k3_usb3_phy_ops; ++ else ++ ops = &k3_pcie_phy_ops; ++ ++ dev_dbg(phy->dev, "phy %d is %s\n", i, is_usb ? "usb" : "pcie"); ++ ++ lg->phy = devm_phy_create(phy->dev, NULL, ops); ++ if (IS_ERR(lg->phy)) ++ return PTR_ERR(lg->phy); ++ ++ lg->is_pcie = !is_usb; ++ lg->data = data; ++ lg->base = phy->base; ++ phy_set_drvdata(lg->phy, lg); ++ } ++ ++ return 0; ++} ++ ++static int k3_combo_phy_update_config(struct regmap *apmu, unsigned int config) ++{ ++ if (config & ~PU_MATRIX_CONF_MASK) ++ return -EINVAL; ++ ++ return regmap_update_bits(apmu, PMUA_PCIE_SUBSYS_MGMT, PU_MATRIX_CONF_MASK, config); ++} ++ ++static struct phy *k3_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) ++{ ++ struct k3_combo_phy *phy = dev_get_drvdata(dev); ++ struct k3_lane_group *lg; ++ ++ if (args->args_count != 2) { ++ dev_err(dev, "Invalid number of arguments\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (args->args[0] >= ARRAY_SIZE(k3_combphy_lane_datas)) { ++ dev_err(dev, "Invalid PHY id\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ lg = &phy->groups[args->args[0]]; ++ ++ if ((lg->is_pcie && args->args[1] != PHY_TYPE_PCIE) || ++ (!lg->is_pcie && args->args[1] != PHY_TYPE_USB3)) { ++ dev_err(dev, "Invalid PHY mode\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ return lg->phy; ++} ++ ++static int k3_combo_phy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct phy_provider *provider; ++ struct k3_combo_phy *phy; ++ struct regmap *apmu; ++ u32 config = 0; ++ int ret; ++ ++ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); ++ if (!phy) ++ return -ENOMEM; ++ ++ phy->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(phy->base)) ++ return PTR_ERR(phy->base); ++ ++ phy->apb_spare = syscon_regmap_lookup_by_phandle(node, "spacemit,apb-spare"); ++ if (IS_ERR(phy->apb_spare)) ++ return dev_err_probe(dev, PTR_ERR(phy->apb_spare), ++ "Failed to fine APB SPARE syscon"); ++ ++ apmu = syscon_regmap_lookup_by_phandle_args(node, "spacemit,apmu", 1, &config); ++ if (IS_ERR(apmu)) ++ return dev_err_probe(dev, PTR_ERR(apmu), ++ "Failed to find APMU syscon"); ++ ++ ret = k3_combo_phy_update_config(apmu, config); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to set lane configuration"); ++ ++ phy->dev = dev; ++ platform_set_drvdata(pdev, phy); ++ ++ ret = k3_phy_calibrate(phy->apb_spare); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to calibrate phy"); ++ ++ ret = k3_combo_phy_init_lanes(phy, config); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to init lanes"); ++ ++ provider = devm_of_phy_provider_register(dev, k3_combo_phy_xlate); ++ if (IS_ERR(provider)) ++ return dev_err_probe(dev, PTR_ERR(provider), ++ "Failed to register provider\n"); ++ ++ return 0; ++} ++ ++static const struct of_device_id k3_combo_phy_of_match[] = { ++ { .compatible = "spacemit,k3-combo-phy" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, k3_combo_phy_of_match); ++ ++static struct platform_driver k3_combo_phy_driver = { ++ .probe = k3_combo_phy_probe, ++ .driver = { ++ .name = "spacemit,k3-combo-phy", ++ .of_match_table = k3_combo_phy_of_match, ++ }, ++}; ++module_platform_driver(k3_combo_phy_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K3 USB3/PCIe combo PHY driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/phy/spacemit/phy-k3-common.c b/drivers/phy/spacemit/phy-k3-common.c +new file mode 100644 +index 000000000000..840524cbe533 +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-common.c +@@ -0,0 +1,372 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-k3-common.h" ++ ++/* PHY Registers */ ++#define PHY_VERSION 0x0 ++ ++#define PHY_RESET_CFG 0x04 ++ ++#define PHY_RESET_RXBUF_RST BIT(0) ++#define PHY_RESET_SOFT_RST_PCS BIT(1) ++#define PHY_RESET_SOFT_RST_AHB BIT(2) ++#define PHY_RESET_EN_SD_AFTER_LOCK BIT(6) ++ ++#define PHY_CLK_CFG 0x08 ++ ++#define PHY_CLK_PLL_READY BIT(0) ++#define PHY_CLK_TXCLK_INV BIT(2) ++#define PHY_CLK_RXCLK_EN BIT(3) ++#define PHY_CLK_TXCLK_EN BIT(4) ++#define PHY_CLK_PCLK_EN BIT(5) ++#define PHY_CLK_PIPE_PCLK_EN BIT(6) ++#define PHY_CLK_REFCLK_FREQ GENMASK(10, 7) ++#define PHY_CLK_REFCLK_24M 2 ++#define PHY_CLK_SW_INIT_DONE BIT(11) ++#define PHY_CLK_PU_SSC_OUT BIT(23) ++ ++#define PHY_MODE_CFG 0x0C ++ ++#define PHY_MODE_PCIE_INT_EN BIT(0) ++#define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8) ++#define PHY_MODE_LFPS_TPERIOD_USB 3 ++ ++#define PHY_PU_SEL 0x40 ++ ++#define PHY_PU_CFG_STATUS BIT(9) ++#define PHY_PU_OVRD_STATUS BIT(10) ++ ++#define PHY_PU_CK_REG 0x54 ++ ++#define PHY_PU_REFCLK_100 BIT(25) ++ ++#define PHY_PLL_REG1 0x58 ++ ++#define PHY_PLL_FREF_SEL GENMASK(15, 13) ++#define PHY_PLL_FREF_24M 0x1 ++#define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24) ++#define PHY_PLL_SSC_5000PPM 0xa ++#define PHY_PLL_SSC_MODE GENMASK(29, 28) ++#define PHY_PLL_SSC_MODE_CENTER_SPREAD 0 ++#define PHY_PLL_SSC_MODE_UP_SPREAD 1 ++#define PHY_PLL_SSC_MODE_DOWN_SPREAD 2 ++#define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3 ++ ++#define PHY_PLL_REG2 0x5c ++ ++#define PHY_PLL_SEL_REF100 BIT(21) ++ ++/* PHY RX Register Definitions */ ++#define PHY_RX_REG_A 0x60 ++ ++#define PHY_RX_REG0_RLOAD BIT(4) ++#define PHY_RX_REG1_RTERM GENMASK(11, 8) ++#define PHY_RX_REG1_RC_CALI GENMASK(15, 12) ++#define PHY_RX_REG2_CSEL GENMASK(19, 16) ++#define PHY_RX_REG2_FORCE_CSEL BIT(20) ++#define PHY_RX_REG2_PSEL GENMASK(23, 21) ++#define PHY_RX_REG3_I_LOAD GENMASK(26, 24) ++#define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27) ++#define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28) ++#define PHY_RX_REG3_RDEG1 GENMASK(31, 30) ++ ++#define PHY_RX_REG_B 0x64 ++ ++#define PHY_RX_REGB_MASK GENMASK(23, 0) ++ ++#define PHY_RX_REG4_RDEG2 GENMASK(2, 1) ++#define PHY_RX_REG4_ENVOS BIT(4) ++#define PHY_RX_REG4_RTERM_SEL BIT(5) ++#define PHY_RX_REG4_MANUAL_CFG BIT(7) ++#define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8) ++#define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12) ++#define PHY_RX_REG6_H1_REG GENMASK(19, 16) ++#define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20) ++#define PHY_RX_REG6_BYPASS_ADPT BIT(22) ++ ++#define PHY_ADPT_CFG0 0x140 ++#define PHY_ADPT_AFE_RST_OVRD_EN BIT(1) ++#define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4) ++ ++#define PHY_RXEQ_TIME 0xb4 ++#define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21) ++#define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22) ++#define PHY_RXEQ_TIME_AMP_SOC_650M 0 ++#define PHY_RXEQ_TIME_AMP_SOC_800M 1 ++#define PHY_RXEQ_TIME_AMP_SOC_870M 2 ++#define PHY_RXEQ_TIME_AMP_SOC_900M 3 ++#define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24) ++ ++#define PCIE_PU_ADDR_CLK_CFG 0x0008 ++#define PHY_CLK_PLL_READY BIT(0) ++#define PCIE_INITAL_TIMER GENMASK(6, 3) ++#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) ++#define CFG_SW_PHY_INIT_DONE BIT(11) ++ ++/* Lane RX/TX configuration (per‑lane, at lane_base) */ ++#define PCIE_RX_REG1 0x050 ++#define PCIE_TX_REG1 0x064 ++ ++#define PCIE_PLL_TIMEOUT 500000 ++#define PCIE_POLL_DELAY 500 ++ ++static int k3_usb3phy_init_single(struct k3_lane_group *lg, void __iomem *base) ++{ ++ struct phy *phy = lg->phy; ++ u32 val, tmp; ++ int ret; ++ ++ /* Do not wait CDR lock before sampling data */ ++ val = readl(base + PHY_RESET_CFG); ++ val = u32_replace_bits(val, 0, PHY_RESET_EN_SD_AFTER_LOCK); ++ writel(val, base + PHY_RESET_CFG); ++ ++ /* Power down 100MHz refclk buffer */ ++ val = readl(base + PHY_PU_CK_REG); ++ val = u32_replace_bits(val, 0, PHY_PU_REFCLK_100); ++ writel(val, base + PHY_PU_CK_REG); ++ ++ /* Program PLL REG1 configure the SSC */ ++ val = FIELD_PREP(PHY_PLL_SSC_MODE, PHY_PLL_SSC_MODE_DOWN_SPREAD1) | ++ FIELD_PREP(PHY_PLL_SSC_DEP_SEL, PHY_PLL_SSC_5000PPM) | ++ FIELD_PREP(PHY_PLL_FREF_SEL, PHY_PLL_FREF_24M); ++ writel(val, base + PHY_PLL_REG1); ++ ++ /* Un-select 100MHz PLL reference */ ++ val = readl(base + PHY_PLL_REG2); ++ val = u32_replace_bits(val, 0, PHY_PLL_SEL_REF100); ++ writel(val, base + PHY_PLL_REG2); ++ ++ /* USB LFPS period configuration */ ++ val = readl(base + PHY_MODE_CFG); ++ val = u32_replace_bits(val, PHY_MODE_LFPS_TPERIOD_USB, PHY_MODE_LFPS_TPERIOD); ++ writel(val, base + PHY_MODE_CFG); ++ ++ /* Force AFE adaptation reset */ ++ val = readl(base + PHY_ADPT_CFG0); ++ val |= PHY_ADPT_AFE_RST_OVRD_EN | PHY_ADPT_AFE_RST_OVRD_VAL; ++ writel(val, base + PHY_ADPT_CFG0); ++ ++ /* Override driver amplitude value to 900m */ ++ val = readl(base + PHY_RXEQ_TIME); ++ val |= PHY_RXEQ_TIME_OVRD_AMP_SOC; ++ val = u32_replace_bits(val, PHY_RXEQ_TIME_AMP_SOC_900M, PHY_RXEQ_TIME_CFG_AMP_SOC); ++ writel(val, base + PHY_RXEQ_TIME); ++ ++ /* Configure RX parameters */ ++ val = PHY_RX_REG0_RLOAD | ++ FIELD_PREP(PHY_RX_REG1_RTERM, 0x8) | ++ FIELD_PREP(PHY_RX_REG1_RC_CALI, 0x7) | ++ FIELD_PREP(PHY_RX_REG2_CSEL, 0x8) | ++ PHY_RX_REG2_FORCE_CSEL | ++ FIELD_PREP(PHY_RX_REG2_PSEL, 0x4) | ++ FIELD_PREP(PHY_RX_REG3_I_LOAD, 0x7) | ++ PHY_RX_REG3_SEL_CBOOST_CODE | ++ FIELD_PREP(PHY_RX_REG3_ADJ_BIAS, 0x1) | ++ FIELD_PREP(PHY_RX_REG3_RDEG1, 0x3); ++ writel(val, base + PHY_RX_REG_A); ++ ++ val = readl(base + PHY_RX_REG_B); ++ tmp = FIELD_PREP(PHY_RX_REG4_RDEG2, 0x2) | ++ PHY_RX_REG4_ENVOS | PHY_RX_REG4_RTERM_SEL | PHY_RX_REG4_MANUAL_CFG | ++ FIELD_PREP(PHY_RX_REG5_RCELL_VCM, 0x8) | ++ FIELD_PREP(PHY_RX_REG5_RCELL_BIAS, 0x8) | ++ FIELD_PREP(PHY_RX_REG6_H1_REG, 0x8) | ++ FIELD_PREP(PHY_RX_REG6_ADAPT_GAIN, 0x2); ++ val = u32_replace_bits(val, tmp, PHY_RX_REGB_MASK); ++ writel(val, base + PHY_RX_REG_B); ++ ++ /* ++ * Inform PHY that all PLL-related configuration is done. ++ * PLL will not start locking until PHY_CLK_SW_INIT_DONE is set. ++ */ ++ val = PHY_CLK_SW_INIT_DONE | PHY_CLK_PU_SSC_OUT | ++ FIELD_PREP(PHY_CLK_REFCLK_FREQ, PHY_CLK_REFCLK_24M) | ++ PHY_CLK_RXCLK_EN | PHY_CLK_TXCLK_EN | ++ PHY_CLK_PCLK_EN | PHY_CLK_PIPE_PCLK_EN; ++ writel(val, base + PHY_CLK_CFG); ++ ++ ret = readl_poll_timeout(base + PHY_CLK_CFG, val, ++ (val & PHY_CLK_PLL_READY), ++ PCIE_POLL_DELAY, PCIE_PLL_TIMEOUT); ++ if (ret) { ++ dev_err(&phy->dev, "PHY PLL polling timeout\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int k3_usb3phy_init(struct phy *phy) ++{ ++ struct k3_lane_group *lg = phy_get_drvdata(phy); ++ int ret, i; ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ ret = k3_usb3phy_init_single(lg, lg->base + lg->data->offsets[i]); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++const struct phy_ops k3_usb3_phy_ops = { ++ .init = k3_usb3phy_init, ++ .owner = THIS_MODULE, ++}; ++EXPORT_SYMBOL_GPL(k3_usb3_phy_ops); ++ ++static int k3_pcie_phy_init(struct phy *phy) ++{ ++ struct k3_lane_group *lg = phy_get_drvdata(phy); ++ void __iomem *phy_base = lg->base + lg->data->offsets[0]; ++ u32 val; ++ int ret; ++ int i; ++ ++ val = readl(phy_base + PHY_PLL_REG1); ++ val = u32_replace_bits(val, 0x2, GENMASK(15, 12)); ++ writel(val, phy_base + PHY_PLL_REG1); ++ ++ val = readl(phy_base + PHY_PLL_REG2); ++ val = u32_replace_bits(val, 0, BIT(21)); ++ writel(val, phy_base + PHY_PLL_REG2); ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ void __iomem *lane_base = lg->base + lg->data->offsets[i]; ++ ++ val = readl(lane_base + PCIE_RX_REG1); ++ val = u32_replace_bits(val, 0, 0x3); ++ writel(val, lane_base + PCIE_RX_REG1); ++ } ++ ++ val = readl(phy_base + PHY_PLL_REG2); ++ val |= BIT(20); ++ writel(val, phy_base + PHY_PLL_REG2); ++ ++ writel(0x00006505, phy_base + PCIE_RX_REG1); ++ ++ /* pll_reg1 of lane0, disable SSC: pll[27:24] = 0 */ ++ val = readl(phy_base + PHY_PLL_REG1); ++ val = u32_replace_bits(val, 0, GENMASK(27, 24)); ++ writel(val, phy_base + PHY_PLL_REG1); ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ void __iomem *lane_base = lg->base + lg->data->offsets[i]; ++ ++ /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */ ++ val = readl(lane_base + PHY_PU_SEL); ++ val = u32_replace_bits(val, 1, BIT(13)); ++ writel(val, lane_base + PHY_PU_SEL); ++ ++ /* disable en_sample_data_after_cdr_locked */ ++ val = readl(lane_base + PHY_RESET_CFG); ++ val = u32_replace_bits(val, 0, BIT(6)); ++ writel(val, lane_base + PHY_RESET_CFG); ++ ++ /* Dynamic Lock */ ++ val = readl(lane_base + PHY_MODE_CFG); ++ val = u32_replace_bits(val, 1, BIT(2)); ++ writel(val, lane_base + PHY_MODE_CFG); ++ ++ val = FIELD_PREP(GENMASK(7, 0), 0x10) | ++ FIELD_PREP(GENMASK(15, 8), 0x78) | ++ FIELD_PREP(GENMASK(23, 16), 0x98) | ++ FIELD_PREP(GENMASK(31, 24), 0xdf); ++ writel(val, lane_base + PHY_RX_REG_A); ++ ++ val = readl(lane_base + PHY_RX_REG_B); ++ val &= ~PHY_RX_REGB_MASK; ++ val |= FIELD_PREP(GENMASK(7, 0), 0xb4) | ++ FIELD_PREP(GENMASK(15, 8), 0x88) | ++ FIELD_PREP(GENMASK(23, 16), 0x28); ++ writel(val, lane_base + PHY_RX_REG_B); ++ ++ /* Set init done */ ++ val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG); ++ val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE); ++ writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG); ++ } ++ ++ ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val, ++ (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY, ++ PCIE_PLL_TIMEOUT); ++ if (ret) { ++ dev_err(&lg->phy->dev, "PHY PLL lock timeout\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++const struct phy_ops k3_pcie_phy_ops = { ++ .init = k3_pcie_phy_init, ++ .owner = THIS_MODULE, ++}; ++EXPORT_SYMBOL_GPL(k3_pcie_phy_ops); ++ ++/* PHY rcal init requires APB_SPARE regmap access */ ++ ++#define APB_SPARE_PU_CAL 0x178 ++#define PU_CAL BIT(17) ++ ++#define APB_SPARE_RCAL_HSIO 0x17c ++#define APB_SPARE_PU_CAL_DONE BIT(8) ++#define RCAL_OVRD_PTRIM GENMASK(23, 20) ++#define RCAL_OVRD_NTRIM GENMASK(27, 24) ++#define RCAL_OVRD_PTRIM_EN BIT(28) ++#define RCAL_OVRD_NTRIM_EN BIT(29) ++#define RCAL_OVRD_STABLE_VAL BIT(30) ++#define RCAL_OVRD_STABLE_EN BIT(31) ++ ++#define RCAL_OVRD_TRIM_EN (RCAL_OVRD_NTRIM_EN | RCAL_OVRD_PTRIM_EN) ++#define RCAL_OVRD_TRIM_MASK (RCAL_OVRD_NTRIM | RCAL_OVRD_PTRIM) ++ ++#define PU_CAL_TIMEOUT 2000000 ++ ++static DEFINE_MUTEX(calibrate_lock); ++ ++int k3_phy_calibrate(struct regmap *apb_spare) ++{ ++ unsigned int val = 0; ++ int ret; ++ ++ guard(mutex)(&calibrate_lock); ++ ++ regmap_read(apb_spare, APB_SPARE_RCAL_HSIO, &val); ++ if (val & APB_SPARE_PU_CAL_DONE) ++ return 0; ++ ++ regmap_update_bits(apb_spare, APB_SPARE_PU_CAL, PU_CAL, ++ PU_CAL); ++ ++ ret = regmap_read_poll_timeout(apb_spare, APB_SPARE_RCAL_HSIO, ++ val, (val & APB_SPARE_PU_CAL_DONE), PCIE_POLL_DELAY, ++ PU_CAL_TIMEOUT); ++ ++ if (ret) ++ regmap_update_bits(apb_spare, APB_SPARE_RCAL_HSIO, ++ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | ++ RCAL_OVRD_TRIM_MASK | RCAL_OVRD_STABLE_EN, ++ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | ++ FIELD_PREP(RCAL_OVRD_NTRIM, 0x6) | ++ FIELD_PREP(RCAL_OVRD_PTRIM, 0xa) | ++ RCAL_OVRD_STABLE_EN); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(k3_phy_calibrate); ++ ++MODULE_DESCRIPTION("SpacemiT K3 PHY common ops"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/phy/spacemit/phy-k3-common.h b/drivers/phy/spacemit/phy-k3-common.h +new file mode 100644 +index 000000000000..49009c3c313a +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-common.h +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef _PHY_K3_COMMON_H ++#define _PHY_K3_COMMON_H ++ ++#include ++ ++struct k3_phy_lane_group_data { ++ u32 lanes; ++ u8 config; ++ u8 mask; ++ u32 offsets[] __counted_by(lanes); ++}; ++ ++struct k3_lane_group { ++ const struct k3_phy_lane_group_data *data; ++ void __iomem *base; ++ struct phy *phy; ++ bool is_pcie; ++}; ++ ++extern const struct phy_ops k3_pcie_phy_ops; ++extern const struct phy_ops k3_usb3_phy_ops; ++ ++int k3_phy_calibrate(struct regmap *apb_spare); ++ ++#endif +-- +2.53.0 + diff --git a/SPECS/linux-lts/0465-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch b/SPECS/linux-lts/0465-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch deleted file mode 100644 index 00f7e5801c..0000000000 --- a/SPECS/linux-lts/0465-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch +++ /dev/null @@ -1,36 +0,0 @@ -From df6fd4d5556ae9ac72a7fe88d7ac07abeaaaa7d5 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 20 May 2026 23:29:46 +0800 -Subject: [PATCH 465/467] RUYI: wifi: rtw89: pci: add SpacemiT K3 to 36-bit DMA - allowlist - -The SpacemiT K3 platform has no system memory in the 32-bit address -space, and it's verified that the chip works well with 36-bit DMA of -RTL8852BE. - -Add it to the 36-bit DMA allowlist of rtw89_pci. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - drivers/net/wireless/realtek/rtw89/pci.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c -index 6be1849b0c4d..5058ebadb604 100644 ---- a/drivers/net/wireless/realtek/rtw89/pci.c -+++ b/drivers/net/wireless/realtek/rtw89/pci.c -@@ -3295,6 +3295,10 @@ static bool rtw89_pci_is_dac_compatible_bridge(struct rtw89_dev *rtwdev) - if (bridge->device == 0x2806) - return true; - break; -+ case PCI_VENDOR_ID_SPACEMIT: -+ if (bridge->device == PCI_DEVICE_ID_SPACEMIT_K3) -+ return true; -+ break; - } - - return false; --- -2.53.0 - diff --git a/SPECS/linux-lts/0466-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch b/SPECS/linux-lts/0466-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch deleted file mode 100644 index e3e07666c1..0000000000 --- a/SPECS/linux-lts/0466-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 1cae45d935c7ce67a69b1440b362c73b5ce1446c Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Tue, 19 May 2026 19:57:52 +0800 -Subject: [PATCH 466/467] RUYI: drm/amdgpu: disable dynamic PCIe speed switch - on SpacemiT K3 - -The dynamic speed switch functionality seems to be broken on SpacemiT -K3, and leads to frequent GPU crashes at least with Polaris GPUs. - -Disable dynamic speed switch on this platform. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -index c22aea46efcd..c69fd0b66dd4 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -@@ -1867,6 +1867,14 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev) - */ - static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev) - { -+ struct pci_dev *parent = adev->pdev; -+ static const struct pci_device_id broken_devids[] = { -+ /* SpacemiT K3 */ -+ { PCI_DEVICE(PCI_VENDOR_ID_SPACEMIT, -+ PCI_DEVICE_ID_SPACEMIT_K3) }, -+ {} -+ }; -+ - #if IS_ENABLED(CONFIG_X86) - struct cpuinfo_x86 *c = &cpu_data(0); - -@@ -1877,6 +1885,17 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device - if (c->x86_vendor == X86_VENDOR_INTEL) - return false; - #endif -+ /* skip upstream/downstream switches internal to dGPU */ -+ while (parent->vendor == PCI_VENDOR_ID_ATI) { -+ parent = pci_upstream_bridge(parent); -+ } -+ -+ if (!parent) -+ return true; -+ -+ if (pci_match_id(broken_devids, parent)) -+ return false; -+ - return true; - } - --- -2.53.0 - diff --git a/SPECS/linux-lts/0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch b/SPECS/linux-lts/0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch new file mode 100644 index 0000000000..ce8ce857a9 --- /dev/null +++ b/SPECS/linux-lts/0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch @@ -0,0 +1,106 @@ +From 448b7e9c38ae27c10f2aa343886ce7c2b8243f8d Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 27 Feb 2026 09:46:06 +0800 +Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: add USB controller and + USB phy support + +Add all USB device node to the Spacemit K3. + +Signed-off-by: Inochi Amaoto +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++ + 2 files changed, 55 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index ac965ec83f2c..acfbb5029c15 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -183,6 +183,11 @@ dldo7: dldo7 { + }; + }; + ++&combophy { ++ spacemit,apmu = <&syscon_apmu 0x11>; ++ status = "okay"; ++}; ++ + ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; +@@ -280,3 +285,11 @@ hub@1 { + &usb2_phy { + status = "okay"; + }; ++ ++&usb3d_u2phy { ++ status = "okay"; ++}; ++ ++&usb3d { ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 1b86c872accb..e73e6838f6b0 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + + /dts-v1/; + +@@ -637,6 +638,47 @@ pdma: dma-controller@d4000000 { + status = "disabled"; + }; + ++ usb3d: usb@81a00000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0x81a00000 0x0 0x10000>; ++ interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, ++ <&syscon_apmu RESET_APMU_USB3_D_VCC>, ++ <&syscon_apmu RESET_APMU_USB3_D_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ phys = <&usb3d_u2phy>, ++ <&combophy 4 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,parkmode-disable-ss-quirk; ++ dr_mode = "host"; ++ status = "disabled"; ++ }; ++ ++ usb3d_u2phy: phy@81b00000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0x81b00000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ combophy: phy@81d00000 { ++ compatible = "spacemit,k3-combo-phy"; ++ reg = <0x0 0x81d00000 0x0 0x600000>; ++ #phy-cells = <2>; ++ spacemit,apb-spare = <&pll>; ++ status = "disabled"; ++ }; ++ + usb2_host: usb@c0a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0xc0a00000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch b/SPECS/linux-lts/0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch new file mode 100644 index 0000000000..76aa9565cc --- /dev/null +++ b/SPECS/linux-lts/0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch @@ -0,0 +1,261 @@ +From 3e1379ca2b2ca099c8a0a6900f9be381e48213c6 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Tue, 24 Mar 2026 11:06:24 +0800 +Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: Add PCIe device node + +Add all PCIe device node for Spacemit K3. + +Signed-off-by: Inochi Amaoto +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 ++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 150 +++++++++++++++++++ + 3 files changed, 212 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index acfbb5029c15..f24ada15f182 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -264,6 +264,35 @@ uboot@210000 { + }; + }; + ++&pcie0_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_0_cfg>; ++ phys = <&combophy 0 PHY_TYPE_PCIE>, ++ <&combophy 1 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0", "pcie-phy1"; ++ num-lanes = <4>; ++ status = "okay"; ++}; ++ ++&pcie2_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_cfg>; ++ phys = <&combophy 2 PHY_TYPE_PCIE>, ++ <&combophy 3 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0", "pcie-phy1"; ++ num-lanes = <2>; ++ status = "okay"; ++}; ++ ++&pcie4_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie4_0_cfg>; ++ phys = <&combophy 5 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0"; ++ num-lanes = <1>; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 846d5e8cc783..5a817610101b 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -710,4 +710,37 @@ uart0-0-pins { + drive-strength = <25>; + }; + }; ++ ++ pcie0_0_cfg: pcie0-0-cfg { ++ pcie0-0-pins { ++ pinmux = , /* pcie0 perst */ ++ ; /* pcie0 clkreq */ ++ ++ bias-pull-up = <1>; ++ drive-strength = <33>; ++ power-source = <1800>; ++ }; ++ }; ++ ++ pcie2_0_cfg: pcie2-0-cfg { ++ pcie2-0-pins { ++ pinmux = , /* pcie2 perst */ ++ ; /* pcie2 clkreq */ ++ ++ drive-strength = <38>; ++ power-source = <3300>; ++ }; ++ }; ++ ++ pcie4_0_cfg: pcie4-0-cfg { ++ pcie4-0-pins { ++ pinmux = , /* pcie4 perst */ ++ , /* pcie4 wake */ ++ ; /* pcie4 clkreq */ ++ ++ bias-pull-up = <1>; ++ drive-strength = <33>; ++ power-source = <1800>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index e73e6838f6b0..9552089c7c73 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -638,6 +638,156 @@ pdma: dma-controller@d4000000 { + status = "disabled"; + }; + ++ pcie0_rc: pcie@80000000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80000000 0x0 0x00001000>, ++ <0x0 0x80100000 0x0 0x00001000>, ++ <0x0 0x80300000 0x0 0x00003f20>, ++ <0x11 0x00000000 0x0 0x00010000>, ++ <0x0 0x82900000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTA_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTA_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTA_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, ++ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_A_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_A_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_A_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ linux,pci-domain = <0>; ++ spacemit,apmu = <&syscon_apmu 0x1f0>; ++ status = "disabled"; ++ }; ++ ++ pcie1_rc: pcie@80400000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80400000 0x0 0x00001000>, ++ <0x0 0x80500000 0x0 0x00001000>, ++ <0x0 0x80700000 0x0 0x00003f20>, ++ <0x11 0x80000000 0x0 0x00010000>, ++ <0x0 0x82c00000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTB_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTB_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTB_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00010000 0x11 0x80010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x80110000 0x11 0x80110000 0x0 0x7fef0000>, ++ <0x43000000 0x16 0x00000000 0x16 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_B_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_B_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_B_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ linux,pci-domain = <1>; ++ spacemit,apmu = <&syscon_apmu 0x1d0>; ++ status = "disabled"; ++ }; ++ ++ pcie2_rc: pcie@80800000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80800000 0x0 0x00001000>, ++ <0x0 0x80900000 0x0 0x00001000>, ++ <0x0 0x80b00000 0x0 0x00003f20>, ++ <0x12 0x00000000 0x0 0x00010000>, ++ <0x0 0x82d00000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTC_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTC_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTC_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x00 0x00000000 0x12 0x00010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00110000 0x12 0x00110000 0x0 0x7fef0000>, ++ <0x43000000 0x15 0x00000000 0x15 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_C_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_C_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_C_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <2>; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1c8>; ++ status = "disabled"; ++ }; ++ ++ pcie3_rc: pcie@80c00000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80c00000 0x0 0x00001000>, ++ <0x0 0x80d00000 0x0 0x00001000>, ++ <0x0 0x80f00000 0x0 0x00003f20>, ++ <0x12 0x80000000 0x0 0x00010000>, ++ <0x0 0x82a00000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTD_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTD_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTD_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00010000 0x12 0x80010000 0x0 0x100000>, ++ <0x02000000 0x0 0x80110000 0x12 0x80110000 0x0 0x3fef0000>, ++ <0x43000000 0x14 0x00000000 0x14 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_D_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_D_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_D_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <3>; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1e0>; ++ status = "disabled"; ++ }; ++ ++ pcie4_rc: pcie@81000000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x81000000 0x0 0x00001000>, ++ <0x0 0x81100000 0x0 0x00001000>, ++ <0x0 0x81300000 0x0 0x00003f20>, ++ <0x12 0xc0000000 0x0 0x00010000>, ++ <0x0 0x82b00000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTE_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTE_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTE_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00000000 0x12 0xc0010000 0x0 0x100000>, ++ <0x02000000 0x0 0xc0110000 0x12 0xc0110000 0x0 0x3fef0000>, ++ <0x43000000 0x13 0x00000000 0x13 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_E_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_E_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_E_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <4>; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1e8>; ++ status = "disabled"; ++ }; ++ + usb3d: usb@81a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0x81a00000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0467-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch b/SPECS/linux-lts/0467-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch deleted file mode 100644 index 654f9a8c87..0000000000 --- a/SPECS/linux-lts/0467-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch +++ /dev/null @@ -1,50 +0,0 @@ -From d56459ef2dadb714f51cfba37b08e7cec2640ea1 Mon Sep 17 00:00:00 2001 -From: Zhang Meng -Date: Wed, 4 Feb 2026 08:54:40 +0800 -Subject: [PATCH 467/467] RVCK: driver: clk: k3: keep some system based clock - always on - -FROM: https://github.com/RVCK-Project/rvck/pull/213 - -community inclusion -category: bugfix -bugzilla: https://github.com/RVCK-Project/rvck/issues/212 - --------------------------------- - -The hdma clk is used by some component of CCI bus, it should -be keep always on, regardless of whether hdma enabled. - -The rcpu clk should be always on because it is running backround. - -Signed-off-by: Zhang Meng -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index 03de04144963..6acde3b76b7b 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -866,7 +866,7 @@ static const struct clk_parent_data rcpu_clk_parents[] = { - CCU_PARENT_HW(pll1_d6_409p6), - }; - CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, -- 4, 3, BIT(15), 7, 3, BIT(12), 0); -+ 4, 3, BIT(15), 7, 3, BIT(12), CLK_IS_CRITICAL); - - static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { - CCU_PARENT_HW(pll1_d48_51p2_ap), -@@ -1026,7 +1026,7 @@ CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CT - /* APMU clocks end */ - - /* DCIU clocks start */ --CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); -+CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), CLK_IS_CRITICAL); - CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); - CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); - CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); --- -2.53.0 - diff --git a/SPECS/linux-lts/0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch b/SPECS/linux-lts/0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch new file mode 100644 index 0000000000..9a9326a3e9 --- /dev/null +++ b/SPECS/linux-lts/0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch @@ -0,0 +1,34 @@ +From 88fa19733f8dc09f9c51bf41ded9c4d68c722b88 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Wed, 20 May 2026 23:28:15 +0800 +Subject: [RUYI PATCH] RUYI: PCI: add SpacemiT vendor id and its K3 device id + to pci_ids + +The SpacemiT K3 chip's root complex needs to be listed in the allowlist +of rtw89 driver to allow 36-bit DMA. + +Add the vendor and device IDs to pci_ids.h header file. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Han Gao +--- + include/linux/pci_ids.h | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h +index 7c01548a6ddb..e5a5700f7c8c 100644 +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2643,6 +2643,9 @@ + #define PCI_VENDOR_ID_SUNIX 0x1fd4 + #define PCI_DEVICE_ID_SUNIX_1999 0x1999 + ++#define PCI_VENDOR_ID_SPACEMIT 0x201f ++#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 ++ + #define PCI_VENDOR_ID_HINT 0x3388 + #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch b/SPECS/linux-lts/0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch new file mode 100644 index 0000000000..e0b9eb8766 --- /dev/null +++ b/SPECS/linux-lts/0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch @@ -0,0 +1,36 @@ +From e57bb71611315a5153d479c9e82b806ab76de1fb Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Wed, 20 May 2026 23:29:46 +0800 +Subject: [RUYI PATCH] RUYI: wifi: rtw89: pci: add SpacemiT K3 to 36-bit DMA + allowlist + +The SpacemiT K3 platform has no system memory in the 32-bit address +space, and it's verified that the chip works well with 36-bit DMA of +RTL8852BE. + +Add it to the 36-bit DMA allowlist of rtw89_pci. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Han Gao +--- + drivers/net/wireless/realtek/rtw89/pci.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c +index 6be1849b0c4d..5058ebadb604 100644 +--- a/drivers/net/wireless/realtek/rtw89/pci.c ++++ b/drivers/net/wireless/realtek/rtw89/pci.c +@@ -3295,6 +3295,10 @@ static bool rtw89_pci_is_dac_compatible_bridge(struct rtw89_dev *rtwdev) + if (bridge->device == 0x2806) + return true; + break; ++ case PCI_VENDOR_ID_SPACEMIT: ++ if (bridge->device == PCI_DEVICE_ID_SPACEMIT_K3) ++ return true; ++ break; + } + + return false; +-- +2.53.0 + diff --git a/SPECS/linux-lts/0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch b/SPECS/linux-lts/0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch new file mode 100644 index 0000000000..00daab299c --- /dev/null +++ b/SPECS/linux-lts/0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch @@ -0,0 +1,57 @@ +From 50eb8f06ed16e79d0840e5c58220ae05cac7dbb1 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Tue, 19 May 2026 19:57:52 +0800 +Subject: [RUYI PATCH] RUYI: drm/amdgpu: disable dynamic PCIe speed switch on + SpacemiT K3 + +The dynamic speed switch functionality seems to be broken on SpacemiT +K3, and leads to frequent GPU crashes at least with Polaris GPUs. + +Disable dynamic speed switch on this platform. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Han Gao +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index c22aea46efcd..b54f7cdd0ce8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1867,6 +1867,14 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev) + */ + static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev) + { ++ struct pci_dev *parent = adev->pdev; ++ static const struct pci_device_id broken_devids[] = { ++ /* SpacemiT K3 */ ++ { PCI_DEVICE(PCI_VENDOR_ID_SPACEMIT, ++ PCI_DEVICE_ID_SPACEMIT_K3) }, ++ {} ++ }; ++ + #if IS_ENABLED(CONFIG_X86) + struct cpuinfo_x86 *c = &cpu_data(0); + +@@ -1877,6 +1885,17 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device + if (c->x86_vendor == X86_VENDOR_INTEL) + return false; + #endif ++ /* skip upstream/downstream switches internal to dGPU */ ++ while (parent && parent->vendor == PCI_VENDOR_ID_ATI) { ++ parent = pci_upstream_bridge(parent); ++ } ++ ++ if (!parent) ++ return true; ++ ++ if (pci_match_id(broken_devids, parent)) ++ return false; ++ + return true; + } + +-- +2.53.0 + diff --git a/SPECS/linux-lts/0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch b/SPECS/linux-lts/0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch new file mode 100644 index 0000000000..daa05c9c8d --- /dev/null +++ b/SPECS/linux-lts/0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch @@ -0,0 +1,50 @@ +From c0f35dd9ad2ce894ee2fef94f5ac86216d03ef46 Mon Sep 17 00:00:00 2001 +From: Zhang Meng +Date: Wed, 4 Feb 2026 08:54:40 +0800 +Subject: [RUYI PATCH] RVCK: driver: clk: k3: keep some system based clock + always on + +FROM: https://github.com/RVCK-Project/rvck/pull/213 + +community inclusion +category: bugfix +bugzilla: https://github.com/RVCK-Project/rvck/issues/212 + +-------------------------------- + +The hdma clk is used by some component of CCI bus, it should +be keep always on, regardless of whether hdma enabled. + +The rcpu clk should be always on because it is running backround. + +Signed-off-by: Zhang Meng +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 03de04144963..6acde3b76b7b 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -866,7 +866,7 @@ static const struct clk_parent_data rcpu_clk_parents[] = { + CCU_PARENT_HW(pll1_d6_409p6), + }; + CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, +- 4, 3, BIT(15), 7, 3, BIT(12), 0); ++ 4, 3, BIT(15), 7, 3, BIT(12), CLK_IS_CRITICAL); + + static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { + CCU_PARENT_HW(pll1_d48_51p2_ap), +@@ -1026,7 +1026,7 @@ CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CT + /* APMU clocks end */ + + /* DCIU clocks start */ +-CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); ++CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), CLK_IS_CRITICAL); + CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); + CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); + CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); +-- +2.53.0 + diff --git a/SPECS/linux-lts/0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch b/SPECS/linux-lts/0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch new file mode 100644 index 0000000000..5c6f644043 --- /dev/null +++ b/SPECS/linux-lts/0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch @@ -0,0 +1,65 @@ +From af2e3f98ce75fe961163f67f323465d95ce082d9 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 28 May 2026 14:18:23 +0800 +Subject: [RUYI PATCH] RUYI: mmc: sdhci-of-dwcmshc: Add support for SG2042 FPGA + variant + +Add support for a testing variant of the SG2042 SDHCI controller without +PHY reset and without the "timer" clock. + +Signed-off-by: Vivian Wang +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index 90aa146a1be3..292940d9c45b 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -1664,6 +1664,16 @@ static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { + .platform_execute_tuning = th1520_execute_tuning, + }; + ++static const struct sdhci_ops sdhci_dwcmshc_sg2042_fpga_ops = { ++ .set_clock = sdhci_set_clock, ++ .set_bus_width = sdhci_set_bus_width, ++ .set_uhs_signaling = dwcmshc_set_uhs_signaling, ++ .get_max_clock = dwcmshc_get_max_clock, ++ .reset = sdhci_reset, ++ .adma_write_desc = dwcmshc_adma_write_desc, ++ .platform_execute_tuning = th1520_execute_tuning, ++}; ++ + static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { + .set_clock = sdhci_eic7700_set_clock, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, +@@ -1746,6 +1756,14 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { + .init = sg2042_init, + }; + ++static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_fpga_pdata = { ++ .pdata = { ++ .ops = &sdhci_dwcmshc_sg2042_fpga_ops, ++ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, ++ }, ++}; ++ + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_eic7700_ops, +@@ -1857,6 +1875,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { + .compatible = "sophgo,sg2042-dwcmshc", + .data = &sdhci_dwcmshc_sg2042_pdata, + }, ++ { ++ .compatible = "sophgo,sg2042-fpga-dwcmshc", ++ .data = &sdhci_dwcmshc_sg2042_fpga_pdata, ++ }, + { + .compatible = "eswin,eic7700-dwcmshc", + .data = &sdhci_dwcmshc_eic7700_pdata, +-- +2.53.0 + diff --git a/SPECS/linux-lts/linux-lts.spec b/SPECS/linux-lts/linux-lts.spec index 2342f9c6b9..0f4104316e 100644 --- a/SPECS/linux-lts/linux-lts.spec +++ b/SPECS/linux-lts/linux-lts.spec @@ -23,14 +23,15 @@ %global kernel_make_flags LD=ld.bfd KBUILD_BUILD_VERSION=%{release} Name: linux-lts -Version: 6.18.33 +Version: 6.18.34 Release: %autorelease Summary: The Linux lts Kernel License: GPL-2.0-only URL: https://www.kernel.org/ -#!RemoteAsset: sha256:6f16ff302599f6fe34742890322cf0775703105fbd8767449682fca6af0fb782 +#!RemoteAsset: sha256:640c4732fb42842166db97e032c1fe7e5ff72c85a8982c75b40f74be3555d760 Source0: https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-%{version}.tar.xz Source1: config.%{_arch} +Source2: series BuildRequires: gcc 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+0461-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch +0462-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch +0463-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch +0464-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch +0465-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch +0466-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch +0467-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch +0468-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch +0469-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch +0470-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch +0471-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch +0472-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch diff --git a/SPECS/linux/0001-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch b/SPECS/linux/0001-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch deleted file mode 100644 index c61d8c49ba..0000000000 --- a/SPECS/linux/0001-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 30511272dcaccf22b5c421d030ecc5605477fcf9 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Thu, 28 May 2026 14:18:23 +0800 -Subject: [PATCH] RUYI: mmc: sdhci-of-dwcmshc: Add support for SG2042 FPGA - variant - -Add support for a testing variant of the SG2042 SDHCI controller without -PHY reset and without the "timer" clock. - -Signed-off-by: Vivian Wang ---- - drivers/mmc/host/sdhci-of-dwcmshc.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c -index bf2cb49ddd8196..b16d34c4c4c915 100644 ---- a/drivers/mmc/host/sdhci-of-dwcmshc.c -+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c -@@ -1743,6 +1743,16 @@ static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { - .platform_execute_tuning = th1520_execute_tuning, - }; - -+static const struct sdhci_ops sdhci_dwcmshc_sg2042_fpga_ops = { -+ .set_clock = sdhci_set_clock, -+ .set_bus_width = sdhci_set_bus_width, -+ .set_uhs_signaling = dwcmshc_set_uhs_signaling, -+ .get_max_clock = dwcmshc_get_max_clock, -+ .reset = sdhci_reset, -+ .adma_write_desc = dwcmshc_adma_write_desc, -+ .platform_execute_tuning = th1520_execute_tuning, -+}; -+ - static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { - .set_clock = sdhci_eic7700_set_clock, - .get_max_clock = sdhci_pltfm_clk_get_max_clock, -@@ -1836,6 +1846,14 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { - .init = sg2042_init, - }; - -+static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_fpga_pdata = { -+ .pdata = { -+ .ops = &sdhci_dwcmshc_sg2042_fpga_ops, -+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, -+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, -+ }, -+}; -+ - static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = { - .pdata = { - .ops = &sdhci_dwcmshc_eic7700_ops, -@@ -1951,6 +1969,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { - .compatible = "sophgo,sg2042-dwcmshc", - .data = &sdhci_dwcmshc_sg2042_pdata, - }, -+ { -+ .compatible = "sophgo,sg2042-fpga-dwcmshc", -+ .data = &sdhci_dwcmshc_sg2042_fpga_pdata, -+ }, - { - .compatible = "eswin,eic7700-dwcmshc", - .data = &sdhci_dwcmshc_eic7700_pdata, diff --git a/SPECS/linux/0001-UPSTREAM-rust-clk-implement-Send-and-Sync.patch b/SPECS/linux/0001-UPSTREAM-rust-clk-implement-Send-and-Sync.patch index 51d4577f5a..f727581bf4 100644 --- a/SPECS/linux/0001-UPSTREAM-rust-clk-implement-Send-and-Sync.patch +++ b/SPECS/linux/0001-UPSTREAM-rust-clk-implement-Send-and-Sync.patch @@ -1,7 +1,7 @@ -From 32e626aa8faf34a07c872f1361c1a54bee79cfa6 Mon Sep 17 00:00:00 2001 +From 3f54eb610b37726f67899513801c0738e778671f Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Mon, 23 Feb 2026 10:08:25 +0000 -Subject: [PATCH 001/269] UPSTREAM: rust: clk: implement Send and Sync +Subject: [RUYI PATCH] UPSTREAM: rust: clk: implement Send and Sync These traits are required for drivers to embed the Clk type in their own data structures because driver data structures are usually required to diff --git a/SPECS/linux/0002-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch b/SPECS/linux/0002-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch index f4c21cefe0..4cea692a3f 100644 --- a/SPECS/linux/0002-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch +++ b/SPECS/linux/0002-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch @@ -1,7 +1,7 @@ -From dac00a8ef6875cd9259bd95898cbef71645284fa Mon Sep 17 00:00:00 2001 +From a77b1e7035c35ef20cecc8246daaa652c0e37fb5 Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Mon, 23 Feb 2026 10:08:26 +0000 -Subject: [PATCH 002/269] UPSTREAM: tyr: remove impl Send/Sync for TyrData +Subject: [RUYI PATCH] UPSTREAM: tyr: remove impl Send/Sync for TyrData Now that clk implements Send and Sync, we no longer need to manually implement these traits for TyrData. Thus remove the implementations. diff --git a/SPECS/linux/0003-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch b/SPECS/linux/0003-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch index 85b6b10347..d2f2157d0c 100644 --- a/SPECS/linux/0003-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch +++ b/SPECS/linux/0003-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch @@ -1,7 +1,7 @@ -From cbac7fc52208de24384218e7f99e0a7ae6902d6a Mon Sep 17 00:00:00 2001 +From 98675c53ff87036feeaa5057ff52b999a55679ed Mon Sep 17 00:00:00 2001 From: Alice Ryhl Date: Mon, 23 Feb 2026 10:08:27 +0000 -Subject: [PATCH 003/269] UPSTREAM: pwm: th1520: remove impl Send/Sync for +Subject: [RUYI PATCH] UPSTREAM: pwm: th1520: remove impl Send/Sync for Th1520PwmDriverData MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 diff --git a/SPECS/linux/0004-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch b/SPECS/linux/0004-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch index 8379c24191..6aa2d56750 100644 --- a/SPECS/linux/0004-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch +++ b/SPECS/linux/0004-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch @@ -1,8 +1,7 @@ -From 13bee0d695478f82109006c9eba8e86c5a827181 Mon Sep 17 00:00:00 2001 +From 5766fc48be56acab88f1a50368573393fa0305a1 Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Thu, 5 Mar 2026 15:00:29 +0800 -Subject: [PATCH 004/269] UPSTREAM: net: spacemit: Remove unused buff_addr - fields +Subject: [RUYI PATCH] UPSTREAM: net: spacemit: Remove unused buff_addr fields These were never used. Just remove them. diff --git a/SPECS/linux/0005-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch b/SPECS/linux/0005-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch index 2e08961b35..badbc9faca 100644 --- a/SPECS/linux/0005-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch +++ b/SPECS/linux/0005-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch @@ -1,8 +1,8 @@ -From 1e7406222abdb03a7abe502c45cac01ef23ee2fc Mon Sep 17 00:00:00 2001 +From 1aed9c9b5c8fc861ea231a94eb16317d1a189327 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 16 Mar 2026 09:00:37 +0800 -Subject: [PATCH 005/269] UPSTREAM: dt-bindings: net: Add support for Spacemit - K3 dwmac +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: net: Add support for Spacemit K3 + dwmac The GMAC IP on Spacemit K3 is almost a standard Synopsys DesignWare MAC (version 5.40a) with some extra clock. diff --git a/SPECS/linux/0006-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch b/SPECS/linux/0006-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch index 43af2bb8ab..b386f36cf0 100644 --- a/SPECS/linux/0006-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch +++ b/SPECS/linux/0006-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch @@ -1,8 +1,8 @@ -From 35042675e0055981bd4339b42933d010e151a97f Mon Sep 17 00:00:00 2001 +From b87eb6266c630ca14fc62950df92636440bbd3ac Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 16 Mar 2026 09:00:38 +0800 -Subject: [PATCH 006/269] UPSTREAM: net: stmmac: platform: Add snps,dwmac-5.40a - IP compatible string +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: platform: Add snps,dwmac-5.40a IP + compatible string Add compatible string for 5.40a version that can avoid to define some platform data in the glue layer. diff --git a/SPECS/linux/0007-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch b/SPECS/linux/0007-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch index 496cd6a6a2..72cb4be85b 100644 --- a/SPECS/linux/0007-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch +++ b/SPECS/linux/0007-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch @@ -1,7 +1,7 @@ -From 844ab29e418ac63ed5c3d3f9fe3336cca312ca83 Mon Sep 17 00:00:00 2001 +From 1111d25f0f3b5f222aa200de96d68b736167267f Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 16 Mar 2026 09:00:39 +0800 -Subject: [PATCH 007/269] UPSTREAM: net: stmmac: Add glue layer for Spacemit K3 +Subject: [RUYI PATCH] UPSTREAM: net: stmmac: Add glue layer for Spacemit K3 SoC The ethernet controller on Spacemit K3 SoC is Synopsys DesignWare diff --git a/SPECS/linux/0008-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch b/SPECS/linux/0008-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch index d15c0beee5..d857e5156a 100644 --- a/SPECS/linux/0008-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch +++ b/SPECS/linux/0008-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch @@ -1,8 +1,8 @@ -From 1e781e2ba620529c68644f4788a346b991b47dba Mon Sep 17 00:00:00 2001 +From 3fa38dee57c6dfdc25c2cb94b508edb6917fcdc4 Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Fri, 6 Feb 2026 16:02:12 +0000 -Subject: [PATCH 008/269] UPSTREAM: drm/imagination: Improve handling of - unknown FWCCB commands +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Improve handling of unknown + FWCCB commands A couple small changes: - Validate the magic value at the head of FWCCB commands, and diff --git a/SPECS/linux/0009-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch b/SPECS/linux/0009-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch index 7aff3cd3a0..a53c57f617 100644 --- a/SPECS/linux/0009-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch +++ b/SPECS/linux/0009-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch @@ -1,8 +1,8 @@ -From 82d9f60a95285445282c42b28590778d2fd7437e Mon Sep 17 00:00:00 2001 +From 95b245031f0856b75f157d12a7b6d8e41544204a Mon Sep 17 00:00:00 2001 From: Matt Coster Date: Fri, 6 Feb 2026 16:02:13 +0000 -Subject: [PATCH 009/269] UPSTREAM: drm/imagination: Mark - FWCCB_CMD_UPDATE_STATS as known +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Mark FWCCB_CMD_UPDATE_STATS + as known Suppress the "unknown type" warning when processing a FWCCB command of type CMD_UPDATE_STATS which is known but (currently) unused. diff --git a/SPECS/linux/0010-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch b/SPECS/linux/0010-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch index 98d6d2a8b0..eeb059e7b0 100644 --- a/SPECS/linux/0010-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch +++ b/SPECS/linux/0010-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch @@ -1,7 +1,7 @@ -From 522b99e4644148a2c6ad8676e6bddf1908da1406 Mon Sep 17 00:00:00 2001 +From 6cc5cddda02fd86187b713bcf88f9cf8fd2630c3 Mon Sep 17 00:00:00 2001 From: Brajesh Gupta Date: Fri, 13 Mar 2026 06:38:24 +0000 -Subject: [PATCH 010/269] UPSTREAM: drm/imagination: Improve firmware power off +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Improve firmware power off for layout_mars config In layout_mars HW config, Firmware MCU moved from Sidekick to new Mars diff --git a/SPECS/linux/0011-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch b/SPECS/linux/0011-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch index 429bd33818..9e9a8ec4d2 100644 --- a/SPECS/linux/0011-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch +++ b/SPECS/linux/0011-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch @@ -1,7 +1,7 @@ -From 33316f50c56ad0f90cbead2c681ff5006a565205 Mon Sep 17 00:00:00 2001 +From 7a98a5855cdcefc0e58a77bd95f3f198732f8979 Mon Sep 17 00:00:00 2001 From: Brajesh Gupta Date: Fri, 13 Mar 2026 06:38:25 +0000 -Subject: [PATCH 011/269] UPSTREAM: drm/imagination: Skip 2nd thread DM +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Skip 2nd thread DM association for non META Firmware Only a META firmware can have two threads. diff --git a/SPECS/linux/0012-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch b/SPECS/linux/0012-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch index 6ae8413920..299ca155e3 100644 --- a/SPECS/linux/0012-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch +++ b/SPECS/linux/0012-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch @@ -1,7 +1,7 @@ -From 74e36a3e32847bbe65aa3a9a29a841e9a1a287ad Mon Sep 17 00:00:00 2001 +From 4bb20fb967b9fde691b582965e6481ad3422bd78 Mon Sep 17 00:00:00 2001 From: Alexandru Dadu Date: Mon, 23 Mar 2026 20:31:28 +0200 -Subject: [PATCH 012/269] UPSTREAM: drm/imagination: Add missing rogue context +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Add missing rogue context reset reasons Update the context reset reason enum with the missing reset reasons in diff --git a/SPECS/linux/0013-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch b/SPECS/linux/0013-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch index 9805d9c009..35a50d2060 100644 --- a/SPECS/linux/0013-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch +++ b/SPECS/linux/0013-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch @@ -1,8 +1,8 @@ -From 38d25068d294339e76dd47a93aa9d99e760faf95 Mon Sep 17 00:00:00 2001 +From 992d53125289da2ed35b94d39033965633eeb01a Mon Sep 17 00:00:00 2001 From: Alexandru Dadu Date: Mon, 23 Mar 2026 20:31:30 +0200 -Subject: [PATCH 013/269] UPSTREAM: drm/imagination: Implement handling of - context reset notification +Subject: [RUYI PATCH] UPSTREAM: drm/imagination: Implement handling of context + reset notification The firmware will send the context reset notification message as part of handling hardware recovery (HWR) events deecoding the message diff --git a/SPECS/linux/0014-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch b/SPECS/linux/0014-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch index 9941e00704..670c827cfc 100644 --- a/SPECS/linux/0014-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch +++ b/SPECS/linux/0014-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch @@ -1,8 +1,7 @@ -From 86fa00014bbc21edb0a54d8889ec0dd041d97294 Mon Sep 17 00:00:00 2001 +From 7d3364edcd6a443dea3c653117830d499c23f554 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:15 +0800 -Subject: [PATCH 014/269] UPSTREAM: dt-bindings: vendor-prefixes: add - verisilicon +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: vendor-prefixes: add verisilicon VeriSilicon is a Silicon IP vendor, which is the current owner of Vivante series video-related IPs and Hantro series video codec IPs. diff --git a/SPECS/linux/0015-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch b/SPECS/linux/0015-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch index 4d2a99ee15..39f5c4f017 100644 --- a/SPECS/linux/0015-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch +++ b/SPECS/linux/0015-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch @@ -1,7 +1,7 @@ -From da348c6ec0ee62a6ce3e8b4ef60eea6befa0eeab Mon Sep 17 00:00:00 2001 +From 2bee5931b9eb68b84da4bc4686476ead9489059c Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:16 +0800 -Subject: [PATCH 015/269] UPSTREAM: dt-bindings: display: add verisilicon,dc +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: display: add verisilicon,dc Verisilicon has a series of display controllers prefixed with DC and with self-identification facility like their GC series GPUs. diff --git a/SPECS/linux/0016-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch b/SPECS/linux/0016-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch index d6750eb3fc..3ac8f40440 100644 --- a/SPECS/linux/0016-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch +++ b/SPECS/linux/0016-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch @@ -1,8 +1,8 @@ -From 2ca89890f1a13910f9a3e9dcebbb0043a3909f54 Mon Sep 17 00:00:00 2001 +From 992a45de879887311976295d6b73b3dc0f719ebc Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:17 +0800 -Subject: [PATCH 016/269] UPSTREAM: drm: verisilicon: add a driver for - Verisilicon display controllers +Subject: [RUYI PATCH] UPSTREAM: drm: verisilicon: add a driver for Verisilicon + display controllers This is a from-scratch driver targeting Verisilicon DC-series display controllers, which feature self-identification functionality like their diff --git a/SPECS/linux/0017-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch b/SPECS/linux/0017-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch index c5abc73bf4..5bc999ca35 100644 --- a/SPECS/linux/0017-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch +++ b/SPECS/linux/0017-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch @@ -1,8 +1,8 @@ -From e8de64d708a84beef39575a6b434ff0890c2169b Mon Sep 17 00:00:00 2001 +From ed1be580f527074f99d1b00510bfe2d2d40709df Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:18 +0800 -Subject: [PATCH 017/269] UPSTREAM: dt-bindings: display/bridge: add binding - for TH1520 HDMI controller +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: display/bridge: add binding for + TH1520 HDMI controller T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired with DesignWare HDMI PHY, with an extra clock gate for HDMI pixel clock diff --git a/SPECS/linux/0018-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch b/SPECS/linux/0018-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch index 9a2cb514eb..9040245b2c 100644 --- a/SPECS/linux/0018-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch +++ b/SPECS/linux/0018-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch @@ -1,7 +1,7 @@ -From 5c7ee13986715018eed1b0d6ed85af9469933e2b Mon Sep 17 00:00:00 2001 +From 8f4c23fbbe5b4f710b06bdb1e40b52c84340ce3f Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:19 +0800 -Subject: [PATCH 018/269] UPSTREAM: drm/bridge: add a driver for T-Head TH1520 +Subject: [RUYI PATCH] UPSTREAM: drm/bridge: add a driver for T-Head TH1520 HDMI controller T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller (paired diff --git a/SPECS/linux/0019-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch b/SPECS/linux/0019-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch index 47ac48fd8c..7e7a3d474d 100644 --- a/SPECS/linux/0019-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch +++ b/SPECS/linux/0019-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch @@ -1,8 +1,8 @@ -From c27659adb8ff66b7d690aba80400f8996f00a247 Mon Sep 17 00:00:00 2001 +From cea0787ce8056c7b05f8654c6a768d950eea234f Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 6 Feb 2026 10:32:02 +0800 -Subject: [PATCH 019/269] UPSTREAM: dt-bindings: mfd: spacemit,p1: Add - individual regulator supply properties +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mfd: spacemit,p1: Add individual + regulator supply properties Add supply properties that match the P1 PMIC's actual hardware topology where each buck converter has its own VIN pin and LDO groups share diff --git a/SPECS/linux/0020-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch b/SPECS/linux/0020-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch index b4f6ebf06c..5093cd5f34 100644 --- a/SPECS/linux/0020-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch +++ b/SPECS/linux/0020-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch @@ -1,7 +1,7 @@ -From 8428e9f6c9dacf79dc0905aed3db711b7bff5a59 Mon Sep 17 00:00:00 2001 +From 85343501c8c4a3b7c88ff45b945213064b197975 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 6 Feb 2026 10:32:03 +0800 -Subject: [PATCH 020/269] UPSTREAM: regulator: spacemit-p1: Update supply names +Subject: [RUYI PATCH] UPSTREAM: regulator: spacemit-p1: Update supply names Update supply names to match the P1 PMIC's actual hardware pinout where each buck has an individual VIN pin (vin1-vin6) and LDO groups have diff --git a/SPECS/linux/0021-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch b/SPECS/linux/0021-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch index ba4b02510c..3978e98199 100644 --- a/SPECS/linux/0021-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch +++ b/SPECS/linux/0021-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch @@ -1,7 +1,7 @@ -From 49446b9b5652ede3c857da8ace5bf329df41b2cb Mon Sep 17 00:00:00 2001 +From 90b207c5e43b4e0d9fba86ef988b9b08026078de Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 23 Dec 2025 10:24:50 +0800 -Subject: [PATCH 021/269] UPSTREAM: mmc: sdhci-of-k1: add reset support +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: add reset support The SDHCI controller of SpacemiT K1 SoC requires two resets, add support to explicitly request the reset line and deassert during diff --git a/SPECS/linux/0022-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch b/SPECS/linux/0022-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch index 9ae5fac256..2e851166b9 100644 --- a/SPECS/linux/0022-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch +++ b/SPECS/linux/0022-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch @@ -1,8 +1,8 @@ -From 89351aec08d522ddfbba5fb204ff212cf00ee26e Mon Sep 17 00:00:00 2001 +From f07e982850d3ae363adbd141b80108da63da642b Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 22 Jan 2026 17:37:30 +0800 -Subject: [PATCH 022/269] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add - support for K3 SoC +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add support + for K3 SoC The SDHCI controller found on SpacemiT K3 SoC share the same IP with K1 generation, while fixed the broken 64BIT DMA issue. Introduce a diff --git a/SPECS/linux/0023-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch b/SPECS/linux/0023-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch index e7db76e054..69070fb5a2 100644 --- a/SPECS/linux/0023-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch +++ b/SPECS/linux/0023-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch @@ -1,8 +1,8 @@ -From 57ff3302c7e1a5be2572cc607e6243267ef5f37b Mon Sep 17 00:00:00 2001 +From 9daeb4a536f71bfe6a633cd2699921998bbb6418 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 22 Jan 2026 17:37:31 +0800 -Subject: [PATCH 023/269] UPSTREAM: mmc: sdhci-of-k1: spacemit: Add support for - K3 SoC +Subject: [RUYI PATCH] UPSTREAM: mmc: sdhci-of-k1: spacemit: Add support for K3 + SoC The SDHCI controller found on SpacemiT K3 SoC share the same IP with K1 generation and introduce a compatible data to denote the change that broken diff --git a/SPECS/linux/0024-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch b/SPECS/linux/0024-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch index 462862ed3b..e5e57ede2f 100644 --- a/SPECS/linux/0024-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch +++ b/SPECS/linux/0024-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch @@ -1,7 +1,7 @@ -From dfabed26dc6ae1b5469ed7d5e6bf03ff5870fe96 Mon Sep 17 00:00:00 2001 +From 57d5e402524d9ff1f3736ea17f619ed4e28921d9 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 10 Mar 2026 00:24:56 +0800 -Subject: [PATCH 024/269] UPSTREAM: dt-bindings: hwmon: moortec,mr75203: adapt +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: hwmon: moortec,mr75203: adapt multipleOf for T-Head TH1520 The G and J coefficients provided by T-Head TH1520 manual (which calls diff --git a/SPECS/linux/0025-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch b/SPECS/linux/0025-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch index a9010769c1..f383f11b2e 100644 --- a/SPECS/linux/0025-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch +++ b/SPECS/linux/0025-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch @@ -1,7 +1,7 @@ -From ea2c1e85b699fc3c114e255f51d7630dd2d57654 Mon Sep 17 00:00:00 2001 +From cada81866815ff90f7d108bf24e4248f30638644 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:20 +0800 -Subject: [PATCH 025/269] UPSTREAM: riscv: dts: thead: add DPU and HDMI device +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: add DPU and HDMI device tree nodes T-Head TH1520 SoC contains a Verisilicon DC8200 display controller diff --git a/SPECS/linux/0026-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch b/SPECS/linux/0026-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch index 91730f296f..f22f4acd8e 100644 --- a/SPECS/linux/0026-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch +++ b/SPECS/linux/0026-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch @@ -1,8 +1,7 @@ -From 51696f7b0480c9f64849dc1c3f893da4dda2fc76 Mon Sep 17 00:00:00 2001 +From 5a28dc8e0e5728a367d1e79fe2703ce452c017f6 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Thu, 29 Jan 2026 10:39:21 +0800 -Subject: [PATCH 026/269] UPSTREAM: riscv: dts: thead: lichee-pi-4a: enable - HDMI +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: lichee-pi-4a: enable HDMI Lichee Pi 4A board features a HDMI Type-A connector connected to the HDMI TX controller of TH1520 SoC. diff --git a/SPECS/linux/0027-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch b/SPECS/linux/0027-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch index 835fef3e37..ef4ba859b4 100644 --- a/SPECS/linux/0027-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch +++ b/SPECS/linux/0027-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch @@ -1,8 +1,8 @@ -From 7753a7edfccf1f16df111bbb87464d07c82ba49a Mon Sep 17 00:00:00 2001 +From eb079b0d7eaaf150988b0daa889f6334018c7848 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 10 Mar 2026 00:24:57 +0800 -Subject: [PATCH 027/269] UPSTREAM: riscv: dts: thead: th1520: add coefficients - to the PVT node +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: th1520: add coefficients to + the PVT node The manual of TH1520 contains a set of coefficients a little different to the driver default ones. diff --git a/SPECS/linux/0028-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch b/SPECS/linux/0028-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch index cea0b884ee..792f5dc903 100644 --- a/SPECS/linux/0028-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch +++ b/SPECS/linux/0028-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch @@ -1,8 +1,8 @@ -From 3751524813fc46f2b9cb044ed110fc489d5765a7 Mon Sep 17 00:00:00 2001 +From b77cd9567fbc0337667a601979b262a815c1e7c2 Mon Sep 17 00:00:00 2001 From: Robert Mazur Date: Wed, 25 Mar 2026 09:18:59 +0100 -Subject: [PATCH 028/269] UPSTREAM: riscv: dts: thead: beaglev-ahead: enable - HDMI output +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: thead: beaglev-ahead: enable HDMI + output The BeagleV Ahead board includes a micro HDMI connector (Type-D) wired to the TH1520 SoC's HDMI transmitter. diff --git a/SPECS/linux/0029-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch b/SPECS/linux/0029-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch index aef4b67538..d9cd408015 100644 --- a/SPECS/linux/0029-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch +++ b/SPECS/linux/0029-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch @@ -1,7 +1,7 @@ -From ca8f0147958660e97976db95f3e8944992cb2b00 Mon Sep 17 00:00:00 2001 +From 5b234af9b55bdbb9547c37df8d28cdb8abfae6ae Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Sat, 7 Feb 2026 23:08:21 +0800 -Subject: [PATCH 029/269] UPSTREAM: i2c: spacemit: move i2c_xfer_msg() +Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: move i2c_xfer_msg() The upcoming PIO support requires a wait_pio_xfer() helper, which is invoked from xfer_msg(). diff --git a/SPECS/linux/0030-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch b/SPECS/linux/0030-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch index a5bc66e970..c486135fe9 100644 --- a/SPECS/linux/0030-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch +++ b/SPECS/linux/0030-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch @@ -1,7 +1,7 @@ -From 99d654e69ac2fce074257e7df304c05145c96d7f Mon Sep 17 00:00:00 2001 +From 6f59c024e794c022c26891390ee88fa3281b75e2 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Sat, 7 Feb 2026 23:08:22 +0800 -Subject: [PATCH 030/269] UPSTREAM: i2c: spacemit: introduce pio for k1 +Subject: [RUYI PATCH] UPSTREAM: i2c: spacemit: introduce pio for k1 This patch introduces I2C PIO functionality for the Spacemit K1 SoC, enabling the use of I2C in atomic context. diff --git a/SPECS/linux/0031-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch b/SPECS/linux/0031-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch index 884c34a81c..fd72379a0c 100644 --- a/SPECS/linux/0031-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch +++ b/SPECS/linux/0031-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch @@ -1,7 +1,7 @@ -From 37bfdd9267f3e05a571f741d27e2be7d95ac0c39 Mon Sep 17 00:00:00 2001 +From 6d60005d031747f97a95aeb53ada85deaad0485f Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Thu, 12 Mar 2026 16:42:42 +0800 -Subject: [PATCH 031/269] UPSTREAM: pinctrl: spacemit: return -ENOTSUPP for +Subject: [RUYI PATCH] UPSTREAM: pinctrl: spacemit: return -ENOTSUPP for unsupported pin configurations Return -ENOTSUPP instead of -EINVAL when encountering unsupported pin diff --git a/SPECS/linux/0032-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch b/SPECS/linux/0032-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch index 38d84d98b1..d543dda0d3 100644 --- a/SPECS/linux/0032-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch +++ b/SPECS/linux/0032-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch @@ -1,7 +1,7 @@ -From 7e8738b353b5990d25948e7c3537149c311beb52 Mon Sep 17 00:00:00 2001 +From eb0bfa60765ecbd42d2473d893ad3e767b94a7b3 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Thu, 12 Mar 2026 16:42:43 +0800 -Subject: [PATCH 032/269] UPSTREAM: gpio: spacemit-k1: Add set_config callback +Subject: [RUYI PATCH] UPSTREAM: gpio: spacemit-k1: Add set_config callback support Assign gpiochip_generic_config() to the set_config() callback to support diff --git a/SPECS/linux/0033-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch b/SPECS/linux/0033-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch index b1736c4c3a..0652512036 100644 --- a/SPECS/linux/0033-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch +++ b/SPECS/linux/0033-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch @@ -1,7 +1,7 @@ -From f836055f93cdd62be774990e5acc58644439ac72 Mon Sep 17 00:00:00 2001 +From a24a5a9a5c99bae245862e7b456a4b3a713e48d8 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 6 Feb 2026 10:32:04 +0800 -Subject: [PATCH 033/269] UPSTREAM: riscv: dts: spacemit: Update PMIC supply +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Update PMIC supply properties for BPI-F3 and Jupiter Use per-regulator supply names in pmic "spacemit,p1" node to specify diff --git a/SPECS/linux/0034-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch b/SPECS/linux/0034-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch index 1eda916afe..8134bdeaef 100644 --- a/SPECS/linux/0034-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch +++ b/SPECS/linux/0034-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch @@ -1,7 +1,7 @@ -From 9b4d81f61deba40c33135d9f87e3a1438f2b1ba4 Mon Sep 17 00:00:00 2001 +From 3dfde5da94b932865e0d30178d63853ab3782636 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 26 Feb 2026 09:35:00 +0000 -Subject: [PATCH 034/269] UPSTREAM: riscv: dts: spacemit: adapt regulator node +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: adapt regulator node name to preferred form The preferred node name for fixed-regulators has changed to pattern [1]: diff --git a/SPECS/linux/0035-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch b/SPECS/linux/0035-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch index a243f6745b..7022e905d4 100644 --- a/SPECS/linux/0035-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch +++ b/SPECS/linux/0035-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch @@ -1,8 +1,8 @@ -From 1dc3a2458237396ae40fc204ed4a33f22fbaafa6 Mon Sep 17 00:00:00 2001 +From 2bced42ebf32379078a1e7d4448a9ecb52e3b184 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 9 Mar 2026 11:00:00 +0800 -Subject: [PATCH 035/269] UPSTREAM: riscv: dts: spacemit: Add - 'linux,pci-domain' to PCIe nodes for K1 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add 'linux,pci-domain' + to PCIe nodes for K1 The SpacemiT K1 SoC has 3 PCIe EP controller nodes. Add the 'linux,pci-domain' property to assign a PCI domain number to diff --git a/SPECS/linux/0036-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch b/SPECS/linux/0036-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch index 0bab6f7caa..4d8508cfa0 100644 --- a/SPECS/linux/0036-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch +++ b/SPECS/linux/0036-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch @@ -1,8 +1,8 @@ -From 25bb35a0f7a04d31cc53e31949bf5099a8a18a86 Mon Sep 17 00:00:00 2001 +From 8b4a39964f7a8d22973263c7046c64333b3ef7df Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:19:39 +0000 -Subject: [PATCH 036/269] UPSTREAM: dt-bindings: serial: 8250: spacemit: fix - clock property for K3 SoC +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: serial: 8250: spacemit: fix clock + property for K3 SoC The UART of SpacemiT K3 SoC has same clock property as K1 generation which request two clock sources, fix the binding otherwise will get DT check diff --git a/SPECS/linux/0037-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch b/SPECS/linux/0037-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch index 4a2776aa5d..448348461a 100644 --- a/SPECS/linux/0037-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch +++ b/SPECS/linux/0037-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch @@ -1,7 +1,7 @@ -From 0e4f6236a5b2381a2d6dfc9dbda71d77be9dd33f Mon Sep 17 00:00:00 2001 +From 596a2b899f247fbd19b7b573057be9d25628b728 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:42 +0000 -Subject: [PATCH 037/269] UPSTREAM: riscv: dts: spacemit: k3: add clock tree +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add clock tree Add clock support to SpacemiT K3 SoC, the clock tree consist of several blocks which are APBC, APMU, DCIU, MPUM. diff --git a/SPECS/linux/0038-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch b/SPECS/linux/0038-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch index f4031fef2b..4626ad1703 100644 --- a/SPECS/linux/0038-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch +++ b/SPECS/linux/0038-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch @@ -1,8 +1,7 @@ -From e25c40f1fbc03b6e608a4ccf8117faa35d8b90a3 Mon Sep 17 00:00:00 2001 +From 5edf743bb22da241fe3135105a0ec1162a3767a2 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:43 +0000 -Subject: [PATCH 038/269] UPSTREAM: riscv: dts: spacemit: k3: add pinctrl - support +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add pinctrl support Populate pinctrl node in Device Tree for SpacemiT K3 SoC, So devices can request pinctrl resource properly. diff --git a/SPECS/linux/0039-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch b/SPECS/linux/0039-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch index 5acb6b4410..8c0d6af2ad 100644 --- a/SPECS/linux/0039-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch +++ b/SPECS/linux/0039-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch @@ -1,7 +1,7 @@ -From 992854035ed63e3393e9176932efe97d6ce16d17 Mon Sep 17 00:00:00 2001 +From bbffe92b161825051ec7b5d36863f1df8c865108 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:44 +0000 -Subject: [PATCH 039/269] UPSTREAM: riscv: dts: spacemit: k3: add GPIO support +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add GPIO support Add GPIO node in the Device Tree, so devices are able to request GPIO resource properly. diff --git a/SPECS/linux/0040-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch b/SPECS/linux/0040-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch index e945999f9c..10bb6cd027 100644 --- a/SPECS/linux/0040-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch +++ b/SPECS/linux/0040-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch @@ -1,8 +1,8 @@ -From ae51e3d6b1d2f029bd7d6144af175d833dbba69c Mon Sep 17 00:00:00 2001 +From d33095ec24c1fe93dcea23dcfea83ab07cbca1ae Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 4 Mar 2026 07:36:45 +0000 -Subject: [PATCH 040/269] UPSTREAM: riscv: dts: spacemit: k3: add full resource - to UART +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: k3: add full resource to + UART Previously the UART rely on external bootloader to initialize clock, pinctrl and reset, to solve this, explicitly adding those resource in diff --git a/SPECS/linux/0041-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch b/SPECS/linux/0041-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch index 6cf4e150cd..88815fe933 100644 --- a/SPECS/linux/0041-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch +++ b/SPECS/linux/0041-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch @@ -1,8 +1,8 @@ -From eecefa404c1eb578a61d409769ed3963200e7eb3 Mon Sep 17 00:00:00 2001 +From 9f06c3f9b9dfd33262923be2f74fdaacce7b9480 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 20 Mar 2026 07:15:37 +0000 -Subject: [PATCH 041/269] UPSTREAM: dt-bindings: usb: dwc3: spacemit: add - support for K3 SoC +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: dwc3: spacemit: add support + for K3 SoC Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC. diff --git a/SPECS/linux/0042-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch b/SPECS/linux/0042-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch index 44a36b14b3..2b0848eaf7 100644 --- a/SPECS/linux/0042-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch +++ b/SPECS/linux/0042-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch @@ -1,7 +1,7 @@ -From 73d26018437e56ff543a9ea2ba45b8e6aa83b4c1 Mon Sep 17 00:00:00 2001 +From caa5dc9da8f5f5ebdd4992b644a245ff29b456b4 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 20 Mar 2026 07:15:38 +0000 -Subject: [PATCH 042/269] UPSTREAM: usb: dwc3: dwc3-generic-plat: spacemit: add +Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: dwc3-generic-plat: spacemit: add support for K3 SoC Add support for the DWC3 USB controller which found in SpacemiT K3 SoC. diff --git a/SPECS/linux/0043-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch b/SPECS/linux/0043-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch index 3b4f228a78..1a1bd3d8c8 100644 --- a/SPECS/linux/0043-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch +++ b/SPECS/linux/0043-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch @@ -1,8 +1,8 @@ -From ce5ab7f33a42ca6bc5aa4b3e848c771896729f2f Mon Sep 17 00:00:00 2001 +From 75dc9853f472ebfe220d2ed5e6392a3e9662d664 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Thu, 26 Mar 2026 18:00:10 +0800 -Subject: [PATCH 043/269] UPSTREAM: usb: dwc3: Add optional VBUS regulator - support to SpacemiT K1 +Subject: [RUYI PATCH] UPSTREAM: usb: dwc3: Add optional VBUS regulator support + to SpacemiT K1 Some SpacemiT K1 boards (like OrangePi R2S) provide USB VBUS through a controllable regulator. Add support for the optional diff --git a/SPECS/linux/0044-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch b/SPECS/linux/0044-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch index 64a53311fe..588ddfa1eb 100644 --- a/SPECS/linux/0044-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch +++ b/SPECS/linux/0044-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch @@ -1,8 +1,7 @@ -From b42be3aff8da85420e9ab0f6af7413aeaab5d0d7 Mon Sep 17 00:00:00 2001 +From dff58898a5a601b29fa554f766e8325afaf9bbe6 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 18 Mar 2026 18:00:00 +0800 -Subject: [PATCH 044/269] UPSTREAM: riscv: dts: spacemit: reorder phy nodes for - K1 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: reorder phy nodes for K1 Reorder the PHY nodes of USB and PCIe to the correct positions based on the register address. This improves the readability and maintainability diff --git a/SPECS/linux/0045-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch b/SPECS/linux/0045-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch index 1ee9c3a956..4c926ad28c 100644 --- a/SPECS/linux/0045-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch +++ b/SPECS/linux/0045-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch @@ -1,8 +1,8 @@ -From 59310ed3e36d6426ef719fc33d471760916abb5c Mon Sep 17 00:00:00 2001 +From faacc650f6105f56273160e96d47227c84967fb4 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 26 Mar 2026 09:46:17 +0800 -Subject: [PATCH 045/269] UPSTREAM: riscv: dts: spacemit: Add ethernet device - for K3 +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: Add ethernet device for + K3 Add all ethernet device nodes for K3 SoC. diff --git a/SPECS/linux/0046-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch b/SPECS/linux/0046-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch index 1bf4b3d27d..b7eefeebba 100644 --- a/SPECS/linux/0046-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch +++ b/SPECS/linux/0046-UPSTREAM-riscv-dts-spacemit-add-LEDs-for-Milk-V-Jupi.patch @@ -1,7 +1,7 @@ -From e6186278f475a79d90231662a47067e6f8a4bb4c Mon Sep 17 00:00:00 2001 +From 890d8a85d76089df416ad13de2ac512eba485ca2 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:29 +0100 -Subject: [PATCH 046/269] UPSTREAM: riscv: dts: spacemit: add LEDs for Milk-V +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add LEDs for Milk-V Jupiter board The Milk-V Jupiter board provides support for two LEDs through the front diff --git a/SPECS/linux/0047-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch b/SPECS/linux/0047-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch index 6bfb4643aa..677d2cc180 100644 --- a/SPECS/linux/0047-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch +++ b/SPECS/linux/0047-UPSTREAM-riscv-dts-spacemit-add-24c04-eeprom-on-Milk.patch @@ -1,7 +1,7 @@ -From a40ad7fe714b297e95dcc53f1942fe61021d2603 Mon Sep 17 00:00:00 2001 +From 6cda85b74dcd76a96128ce64db0d23148a55a76a Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:30 +0100 -Subject: [PATCH 047/269] UPSTREAM: riscv: dts: spacemit: add 24c04 eeprom on +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add 24c04 eeprom on Milk-V Jupiter The Milk-V Jupiter board includes a 24c04 eeprom on the i2c2 bus. The diff --git a/SPECS/linux/0048-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch b/SPECS/linux/0048-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch index eeabf645b8..45ab648574 100644 --- a/SPECS/linux/0048-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch +++ b/SPECS/linux/0048-UPSTREAM-riscv-dts-spacemit-add-i2c-aliases-on-Milk-.patch @@ -1,7 +1,7 @@ -From 0529389e911bc07f3419c66a0f53a3b8a7b4ca01 Mon Sep 17 00:00:00 2001 +From ac84eec1a95c286939a124cc599fd1ee24a44c80 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:31 +0100 -Subject: [PATCH 048/269] UPSTREAM: riscv: dts: spacemit: add i2c aliases on +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: add i2c aliases on Milk-V Jupiter Add i2c aliases for i2c2 and i2c8 on Milk-V Jupiter. This is useful to diff --git a/SPECS/linux/0049-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch b/SPECS/linux/0049-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch index 8a1186c84d..e0148df441 100644 --- a/SPECS/linux/0049-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch +++ b/SPECS/linux/0049-UPSTREAM-riscv-dts-spacemit-enable-QSPI-and-add-SPI-.patch @@ -1,8 +1,8 @@ -From 509dec7e7670b6a2b7ad97b0e65a954ed524f149 Mon Sep 17 00:00:00 2001 +From 2247c72d83bcb1a74ae4beb888b88dcb6970194c Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:32 +0100 -Subject: [PATCH 049/269] UPSTREAM: riscv: dts: spacemit: enable QSPI and add - SPI NOR on Milk-V Jupiter +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable QSPI and add SPI + NOR on Milk-V Jupiter Add the QSPI controller node for the Milk-V Jupiter board and describe the attached SPI NOR flash (GD25Q64E). diff --git a/SPECS/linux/0050-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch b/SPECS/linux/0050-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch index ec96f5bb38..bab47c3a64 100644 --- a/SPECS/linux/0050-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch +++ b/SPECS/linux/0050-UPSTREAM-riscv-dts-spacemit-enable-USB-3-ports-on-Mi.patch @@ -1,7 +1,7 @@ -From ce6dafb8880e4df7bafeb93591d67ad8d5a62e1a Mon Sep 17 00:00:00 2001 +From 6cdd3d4630e9e7ddd493231b4dd4d1204061c752 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:33 +0100 -Subject: [PATCH 050/269] UPSTREAM: riscv: dts: spacemit: enable USB 3 ports on +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable USB 3 ports on Milk-V Jupiter Enable the DWC3 USB 3.0 controller (USB#2 port in the K1 datasheet) and diff --git a/SPECS/linux/0051-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch b/SPECS/linux/0051-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch index 418a45b9ec..1c3934af38 100644 --- a/SPECS/linux/0051-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch +++ b/SPECS/linux/0051-UPSTREAM-riscv-dts-spacemit-enable-PCIe-ports-on-Mil.patch @@ -1,7 +1,7 @@ -From 6c69d39fdd805b24d6e022e57923a5f7ab0431eb Mon Sep 17 00:00:00 2001 +From 6774929b5a289c286924ed1fbccbc23ce4f6ac8f Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Thu, 26 Mar 2026 19:35:34 +0100 -Subject: [PATCH 051/269] UPSTREAM: riscv: dts: spacemit: enable PCIe ports on +Subject: [RUYI PATCH] UPSTREAM: riscv: dts: spacemit: enable PCIe ports on Milk-V Jupiter Enable the two PCIe controller along with and their associated PHY. They diff --git a/SPECS/linux/0052-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch b/SPECS/linux/0052-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch index 61c6f55c28..522fbc5ab2 100644 --- a/SPECS/linux/0052-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch +++ b/SPECS/linux/0052-UPSTREAM-dt-bindings-i2c-spacemit-k3-Add-compatible.patch @@ -1,8 +1,7 @@ -From 855990996aab9c1d81b8177a453308574d856865 Mon Sep 17 00:00:00 2001 +From d44c703213fa190bb7cd9048479aee6529f56b60 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 25 Mar 2026 09:49:24 +0000 -Subject: [PATCH 052/269] UPSTREAM: dt-bindings: i2c: spacemit: k3: Add - compatible +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: i2c: spacemit: k3: Add compatible Add a compatible string for the I2C controller found in SpacemiT K3 SoC which use same I2C IP as K1, so make it fallback to K1 compatible. diff --git a/SPECS/linux/0053-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch b/SPECS/linux/0053-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch index de08066251..c09b0e5bf8 100644 --- a/SPECS/linux/0053-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch +++ b/SPECS/linux/0053-UPSTREAM-dts-riscv-spacemit-k3-Add-i2c-nodes.patch @@ -1,7 +1,7 @@ -From 710086905721646f4e792849cd56b0a30f5c236b Mon Sep 17 00:00:00 2001 +From d777fc59865dcb85f6c2ee360127c52a74f6df7d Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 27 Mar 2026 11:40:40 +0000 -Subject: [PATCH 053/269] UPSTREAM: dts: riscv: spacemit: k3: Add i2c nodes +Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: k3: Add i2c nodes Populate all I2C devicetree nodes for SpacemiT K3 SoC. The controller of i2c3 is reserved for secure domain, and not available from Linux. The diff --git a/SPECS/linux/0054-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch b/SPECS/linux/0054-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch index 5c09b67f29..0823d9e55f 100644 --- a/SPECS/linux/0054-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch +++ b/SPECS/linux/0054-UPSTREAM-dts-riscv-spacemit-k3-add-P1-PMIC-regulator.patch @@ -1,7 +1,7 @@ -From f63fb7efe62ee0dc3da55c70cdc7c3e1846e261b Mon Sep 17 00:00:00 2001 +From fe739b7c392e7a882052c2179abf27223c04b38a Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 27 Mar 2026 11:51:18 +0000 -Subject: [PATCH 054/269] UPSTREAM: dts: riscv: spacemit: k3: add P1 PMIC +Subject: [RUYI PATCH] UPSTREAM: dts: riscv: spacemit: k3: add P1 PMIC regulator tree Add the P1 PMIC's regulator topology tree for pico-itx board. diff --git a/SPECS/linux/0055-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch b/SPECS/linux/0055-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch index 4ee2cdf8a6..e3b3825c15 100644 --- a/SPECS/linux/0055-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch +++ b/SPECS/linux/0055-UPSTREAM-perf-symbol-Add-RISCV-case-in-get_plt_sizes.patch @@ -1,8 +1,7 @@ -From 1d2c4fd214e8c4fd57ed9e93d8240e30b3ad674d Mon Sep 17 00:00:00 2001 +From cfba0efefdea75250c07d3c2766d2e25a5f5cc94 Mon Sep 17 00:00:00 2001 From: Chen Pei Date: Tue, 17 Mar 2026 11:48:47 +0800 -Subject: [PATCH 055/269] UPSTREAM: perf symbol: Add RISCV case in - get_plt_sizes +Subject: [RUYI PATCH] UPSTREAM: perf symbol: Add RISCV case in get_plt_sizes According to RISC-V psABI specification, the PLT (Program Linkage Table) has the following layout: diff --git a/SPECS/linux/0056-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch b/SPECS/linux/0056-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch index 7a69760a9f..2b5547943a 100644 --- a/SPECS/linux/0056-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch +++ b/SPECS/linux/0056-UPSTREAM-riscv-Simplify-assignment-for-UTS_MACHINE.patch @@ -1,7 +1,7 @@ -From 2a1d84bced9b3fa60b29773f122dfdae3c5c72ec Mon Sep 17 00:00:00 2001 +From 3548663d9ec9cb78ff9e36047f3e9463a2c219e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 4 Apr 2026 18:42:40 -0600 -Subject: [PATCH 056/269] UPSTREAM: riscv: Simplify assignment for UTS_MACHINE +Subject: [RUYI PATCH] UPSTREAM: riscv: Simplify assignment for UTS_MACHINE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit diff --git a/SPECS/linux/0057-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch b/SPECS/linux/0057-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch index c19f707a47..d446b1a200 100644 --- a/SPECS/linux/0057-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch +++ b/SPECS/linux/0057-UPSTREAM-riscv-increase-COMMAND_LINE_SIZE-value-to-2.patch @@ -1,7 +1,7 @@ -From d74ae16ee8e39915cb8547a18f11abfab7621f82 Mon Sep 17 00:00:00 2001 +From 55f34890b7174492ac193e2942401366cade0b5b Mon Sep 17 00:00:00 2001 From: Austin Kim Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 057/269] UPSTREAM: riscv: increase COMMAND_LINE_SIZE value to +Subject: [RUYI PATCH] UPSTREAM: riscv: increase COMMAND_LINE_SIZE value to 2048 SoC people may send many parameters to configure the drivers via kernel diff --git a/SPECS/linux/0058-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch b/SPECS/linux/0058-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch index ecf21a90ef..b672153e6f 100644 --- a/SPECS/linux/0058-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch +++ b/SPECS/linux/0058-UPSTREAM-riscv-acpi-update-FADT-revision-check-to-6..patch @@ -1,8 +1,7 @@ -From 8841400b98d1855c6b7147cfcffd9adb0072b8d0 Mon Sep 17 00:00:00 2001 +From 9f65d8563b908295c1b15c136d55bbdfc8404d41 Mon Sep 17 00:00:00 2001 From: Yufeng Wang Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 058/269] UPSTREAM: riscv: acpi: update FADT revision check to - 6.6 +Subject: [RUYI PATCH] UPSTREAM: riscv: acpi: update FADT revision check to 6.6 ACPI 6.6 is required for RISC-V as it introduces RISC-V specific tables such as RHCT (RISC-V Hart Capabilities Table) and diff --git a/SPECS/linux/0059-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch b/SPECS/linux/0059-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch index 9e083b7659..19d69e90fa 100644 --- a/SPECS/linux/0059-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch +++ b/SPECS/linux/0059-UPSTREAM-riscv-mm-WARN_ON-for-bad-addresses-in-vmemm.patch @@ -1,7 +1,7 @@ -From 6fcf52df0f09e8702771043b2309d24a592c6738 Mon Sep 17 00:00:00 2001 +From 2882b8c5d55e211d5a055174329abbbf006e052f Mon Sep 17 00:00:00 2001 From: Vivian Wang Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 059/269] UPSTREAM: riscv: mm: WARN_ON() for bad addresses in +Subject: [RUYI PATCH] UPSTREAM: riscv: mm: WARN_ON() for bad addresses in vmemmap_populate() Similarly to the same check in arch/arm64/mm/mmu.c, in @@ -18,10 +18,10 @@ Signed-off-by: Han Gao 1 file changed, 2 insertions(+) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index 811e03786c56..c12590ab3d0e 100644 +index 1b221c3fe275..31007b426d54 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c -@@ -1453,6 +1453,8 @@ int __meminit vmemmap_check_pmd(pmd_t *pmdp, int node, +@@ -1478,6 +1478,8 @@ int __meminit vmemmap_check_pmd(pmd_t *pmdp, int node, int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, struct vmem_altmap *altmap) { diff --git a/SPECS/linux/0060-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch b/SPECS/linux/0060-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch index 21c0a0f336..e1926ed57f 100644 --- a/SPECS/linux/0060-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch +++ b/SPECS/linux/0060-UPSTREAM-riscv-enable-HAVE_IOREMAP_PROT.patch @@ -1,7 +1,7 @@ -From 949e84cef2a3abd4c191ad5c3327a7d44d5a8548 Mon Sep 17 00:00:00 2001 +From 3ac9785b5e20daa4133d6b6758fa55af7ca5dd52 Mon Sep 17 00:00:00 2001 From: Yufeng Wang Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 060/269] UPSTREAM: riscv: enable HAVE_IOREMAP_PROT +Subject: [RUYI PATCH] UPSTREAM: riscv: enable HAVE_IOREMAP_PROT RISC-V has implemented pte_pgprot() and selects GENERIC_IOREMAP, which provides a generic ioremap_prot() implementation. Enable diff --git a/SPECS/linux/0061-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux/0061-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch index a311a0599c..82c7b05f25 100644 --- a/SPECS/linux/0061-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ b/SPECS/linux/0061-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -1,7 +1,7 @@ -From a93839d7a5a7ce3fba6e6564ad126f5689b1ec64 Mon Sep 17 00:00:00 2001 +From afa22c63ff3a8e9a83984ead4323d920b10b0615 Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 061/269] UPSTREAM: lib/string_kunit: add correctness test for +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for strlen() Add a KUnit test for strlen() to verify correctness across diff --git a/SPECS/linux/0062-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux/0062-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch index 2a8a41431d..c8caceb04c 100644 --- a/SPECS/linux/0062-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ b/SPECS/linux/0062-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -1,7 +1,7 @@ -From 2ed066d6e95ff3d4b13353e229f07ba72fa1ccbd Mon Sep 17 00:00:00 2001 +From f3f10c18fe356aaa640a91657a43ce861a75b1a3 Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 062/269] UPSTREAM: lib/string_kunit: add correctness test for +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for strnlen() Add a KUnit test for strnlen() to verify correctness across diff --git a/SPECS/linux/0063-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch b/SPECS/linux/0063-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch index 9002396c98..a3056b9c83 100644 --- a/SPECS/linux/0063-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch +++ b/SPECS/linux/0063-UPSTREAM-lib-string_kunit-add-correctness-test-for-s.patch @@ -1,7 +1,7 @@ -From 35bc12c89250a27187edba752adca38c1658acd1 Mon Sep 17 00:00:00 2001 +From 45e5a04263c7675d5f42be7a9449c3a3126a1de5 Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 063/269] UPSTREAM: lib/string_kunit: add correctness test for +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add correctness test for strrchr() Add a KUnit test for strrchr() to verify correctness across diff --git a/SPECS/linux/0064-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch b/SPECS/linux/0064-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch index 657756c664..5f33a9116a 100644 --- a/SPECS/linux/0064-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch +++ b/SPECS/linux/0064-UPSTREAM-lib-string_kunit-add-performance-benchmark-.patch @@ -1,7 +1,7 @@ -From e2ac3841583ad6b836c92211c5480be0a0a8567a Mon Sep 17 00:00:00 2001 +From e5ce3031ffa70c704a411387fe2093c26694de67 Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 064/269] UPSTREAM: lib/string_kunit: add performance benchmark +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: add performance benchmark for strlen() Introduce a benchmarking framework to the string_kunit test suite to diff --git a/SPECS/linux/0065-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch b/SPECS/linux/0065-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch index 9894bcb319..63bd6642ea 100644 --- a/SPECS/linux/0065-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch +++ b/SPECS/linux/0065-UPSTREAM-lib-string_kunit-extend-benchmarks-to-strnl.patch @@ -1,7 +1,7 @@ -From 78f21c231152c5a7d7bea2fd2c558671ddb0cca7 Mon Sep 17 00:00:00 2001 +From 3ab46395f4240316d920f2d1412da3cf84a78dc9 Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 065/269] UPSTREAM: lib/string_kunit: extend benchmarks to +Subject: [RUYI PATCH] UPSTREAM: lib/string_kunit: extend benchmarks to strnlen() and chr searches Extend the string benchmarking suite to include strnlen(), strchr(), diff --git a/SPECS/linux/0066-UPSTREAM-riscv-lib-add-strnlen-implementation.patch b/SPECS/linux/0066-UPSTREAM-riscv-lib-add-strnlen-implementation.patch index 53e488bfc6..98993ef9b3 100644 --- a/SPECS/linux/0066-UPSTREAM-riscv-lib-add-strnlen-implementation.patch +++ b/SPECS/linux/0066-UPSTREAM-riscv-lib-add-strnlen-implementation.patch @@ -1,7 +1,7 @@ -From 105db5672657eef3c6dedce14524f8d3d3123f4a Mon Sep 17 00:00:00 2001 +From eb1f1b88db85183b4e0d29b7d676929a87af9d3f Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 066/269] UPSTREAM: riscv: lib: add strnlen() implementation +Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strnlen() implementation Add an optimized strnlen() implementation for RISC-V. This version includes a generic optimization and a Zbb-powered optimization using diff --git a/SPECS/linux/0067-UPSTREAM-riscv-lib-add-strchr-implementation.patch b/SPECS/linux/0067-UPSTREAM-riscv-lib-add-strchr-implementation.patch index 359a2a5dda..9791752ab5 100644 --- a/SPECS/linux/0067-UPSTREAM-riscv-lib-add-strchr-implementation.patch +++ b/SPECS/linux/0067-UPSTREAM-riscv-lib-add-strchr-implementation.patch @@ -1,7 +1,7 @@ -From 706a4890803c70dc8cedd84261f851bf99a6c86b Mon Sep 17 00:00:00 2001 +From 47ea0b035ac1607487388024968a520f56f0bd9b Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 067/269] UPSTREAM: riscv: lib: add strchr() implementation +Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strchr() implementation Add an assembly implementation of strchr() for RISC-V. diff --git a/SPECS/linux/0068-UPSTREAM-riscv-lib-add-strrchr-implementation.patch b/SPECS/linux/0068-UPSTREAM-riscv-lib-add-strrchr-implementation.patch index 0c0d319c32..d224deca7c 100644 --- a/SPECS/linux/0068-UPSTREAM-riscv-lib-add-strrchr-implementation.patch +++ b/SPECS/linux/0068-UPSTREAM-riscv-lib-add-strrchr-implementation.patch @@ -1,7 +1,7 @@ -From 9185bd24b1ae1baf984b706eb85d57f47217e26b Mon Sep 17 00:00:00 2001 +From c4246da8b2d60d3bedc9b83613a16f8d56d620cd Mon Sep 17 00:00:00 2001 From: Feng Jiang Date: Fri, 3 Apr 2026 19:28:47 -0600 -Subject: [PATCH 068/269] UPSTREAM: riscv: lib: add strrchr() implementation +Subject: [RUYI PATCH] UPSTREAM: riscv: lib: add strrchr() implementation Add an assembly implementation of strrchr() for RISC-V. diff --git a/SPECS/linux/0069-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch b/SPECS/linux/0069-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch index b75d894d7b..9ab2f88bd0 100644 --- a/SPECS/linux/0069-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch +++ b/SPECS/linux/0069-UPSTREAM-ASoC-spacemit-move-hw-constraints-from-hw_p.patch @@ -1,7 +1,7 @@ -From 694399354a2dca37e145726e522142fd92d5f3c7 Mon Sep 17 00:00:00 2001 +From df7dd57a3fddcaf65e709e99b459e1c78d2c91a8 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 29 Apr 2026 09:38:47 +0800 -Subject: [PATCH 069/269] UPSTREAM: ASoC: spacemit: move hw constraints from +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: move hw constraints from hw_params to startup Hardware constraints should be applied in the startup callback rather diff --git a/SPECS/linux/0070-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch b/SPECS/linux/0070-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch index 361d8b6205..7793515f68 100644 --- a/SPECS/linux/0070-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch +++ b/SPECS/linux/0070-UPSTREAM-ASoC-spacemit-adjust-FIFO-trigger-threshold.patch @@ -1,8 +1,8 @@ -From d7f2529fa33a1b03694b1d36f7d1cd60ba258910 Mon Sep 17 00:00:00 2001 +From 3bc40b5fe7a89b0fefce7c8ef383f7ee85f075d1 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 29 Apr 2026 09:38:48 +0800 -Subject: [PATCH 070/269] UPSTREAM: ASoC: spacemit: adjust FIFO trigger - threshold to half FIFO size +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: adjust FIFO trigger threshold + to half FIFO size Set both TX and RX FIFO trigger thresholds (TFT/RFT) to 0xF (half of the 32-entry FIFO) instead of 5. This provides better DMA efficiency diff --git a/SPECS/linux/0071-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch b/SPECS/linux/0071-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch index 80bd255b66..eeb45e2b2d 100644 --- a/SPECS/linux/0071-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch +++ b/SPECS/linux/0071-UPSTREAM-clk-spacemit-k3-mark-top_dclk-as-CLK_IS_CRI.patch @@ -1,7 +1,7 @@ -From 4b49c6fe6de7cf7ee9fefc9a9c9fe76db69ecde6 Mon Sep 17 00:00:00 2001 +From d7f7e2d348dbab7a1ba91d441165e6b7adfa1110 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Fri, 24 Apr 2026 16:20:32 +0800 -Subject: [PATCH 071/269] UPSTREAM: clk: spacemit: k3: mark top_dclk as +Subject: [RUYI PATCH] UPSTREAM: clk: spacemit: k3: mark top_dclk as CLK_IS_CRITICAL top_dclk is the DDR bus clock. If it is gated by clk_disable_unused, diff --git a/SPECS/linux/0072-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch b/SPECS/linux/0072-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch index df9be863a7..5443aa4c05 100644 --- a/SPECS/linux/0072-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch +++ b/SPECS/linux/0072-UPSTREAM-ASoC-spacemit-fix-RX-DMA-params-not-set-whe.patch @@ -1,8 +1,8 @@ -From 63c515a59ebf4202f9383bcfe70604c7fd45d9a0 Mon Sep 17 00:00:00 2001 +From 3a012f1ebf343fe4ebc8990aaf7404eebf395ac6 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Wed, 29 Apr 2026 17:00:50 +0800 -Subject: [PATCH 072/269] UPSTREAM: ASoC: spacemit: fix RX DMA params not set - when TX is running +Subject: [RUYI PATCH] UPSTREAM: ASoC: spacemit: fix RX DMA params not set when + TX is running When TX is already running (SSCR_SSE is set), the hw_params callback returns early before setting up DMA parameters for the RX stream. This diff --git a/SPECS/linux/0073-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch b/SPECS/linux/0073-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch index dfad33f44a..630043867a 100644 --- a/SPECS/linux/0073-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch +++ b/SPECS/linux/0073-UPSTREAM-dt-bindings-usb-Add-support-for-Terminus-FE.patch @@ -1,7 +1,7 @@ -From 547eed1c1fdf7efb31324f4c91f23f79921e4d85 Mon Sep 17 00:00:00 2001 +From 38c76b211a4eaf5b8c41d743248432b57c6b6d9b Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 19 Mar 2026 07:51:03 +0000 -Subject: [PATCH 073/269] UPSTREAM: dt-bindings: usb: Add support for Terminus +Subject: [RUYI PATCH] UPSTREAM: dt-bindings: usb: Add support for Terminus FE1.1s USB2.0 Hub controller Terminus FE1.1s is USB2.0 protocol compliant 4-port USB HUB, It support diff --git a/SPECS/linux/0074-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch b/SPECS/linux/0074-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch index c338380b70..bba3e23eb3 100644 --- a/SPECS/linux/0074-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch +++ b/SPECS/linux/0074-UPSTREAM-usb-misc-onboard_usb_dev-Add-Terminus-FE1.1.patch @@ -1,7 +1,7 @@ -From 393a81ec066f3f0be02d736b35215e61fc39ed08 Mon Sep 17 00:00:00 2001 +From df5d3328d768f9db710c64dc3145300fbfe9a795 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Thu, 19 Mar 2026 07:51:04 +0000 -Subject: [PATCH 074/269] UPSTREAM: usb: misc: onboard_usb_dev: Add Terminus +Subject: [RUYI PATCH] UPSTREAM: usb: misc: onboard_usb_dev: Add Terminus FE1.1s USB2.0 Hub (1a40:0101) Terminus FE1.1s is USB2.0 protocol compliant 4-port USB HUB, It support diff --git a/SPECS/linux/0075-UPSTREAM-iommupt-Add-the-RISC-V-page-table-format.patch b/SPECS/linux/0075-UPSTREAM-iommupt-Add-the-RISC-V-page-table-format.patch index fa704aad1b..5cc22d8e81 100644 --- a/SPECS/linux/0075-UPSTREAM-iommupt-Add-the-RISC-V-page-table-format.patch +++ b/SPECS/linux/0075-UPSTREAM-iommupt-Add-the-RISC-V-page-table-format.patch @@ -1,7 +1,7 @@ -From 85bf2b20fd6fe1b4fee29c3f6a12f52206cdae78 Mon Sep 17 00:00:00 2001 +From c72a35372b822351a8ba9b1b87fd0eb71ee24e6d Mon Sep 17 00:00:00 2001 From: Jason Gunthorpe Date: Fri, 27 Feb 2026 11:25:36 -0400 -Subject: [PATCH 075/269] UPSTREAM: iommupt: Add the RISC-V page table format +Subject: [RUYI PATCH] UPSTREAM: iommupt: Add the RISC-V page table format The RISC-V format is a fairly simple 5 level page table not unlike the x86 one. It has optional support for a single contiguous page size of 64k (16 @@ -486,10 +486,10 @@ index 6a9a1acb5aad..fc5d0b5edadc 100644 struct pt_common common; }; diff --git a/include/linux/generic_pt/iommu.h b/include/linux/generic_pt/iommu.h -index 9eefbb74efd0..49d9addb98c5 100644 +index 43cc98c9c55f..dd0edd02a48a 100644 --- a/include/linux/generic_pt/iommu.h +++ b/include/linux/generic_pt/iommu.h -@@ -275,6 +275,17 @@ struct pt_iommu_vtdss_hw_info { +@@ -322,6 +322,17 @@ struct pt_iommu_vtdss_hw_info { IOMMU_FORMAT(vtdss, vtdss_pt); diff --git a/SPECS/linux/0076-UPSTREAM-iommu-riscv-Disable-SADE.patch b/SPECS/linux/0076-UPSTREAM-iommu-riscv-Disable-SADE.patch index 4119634580..8ba3beae44 100644 --- a/SPECS/linux/0076-UPSTREAM-iommu-riscv-Disable-SADE.patch +++ b/SPECS/linux/0076-UPSTREAM-iommu-riscv-Disable-SADE.patch @@ -1,7 +1,7 @@ -From 67145eb27fcf9d63cb376698b725d3152c12a344 Mon Sep 17 00:00:00 2001 +From 0d4f3d6072aa64dcf8264c20f390c5b3804e54b6 Mon Sep 17 00:00:00 2001 From: Jason Gunthorpe Date: Fri, 27 Feb 2026 11:25:37 -0400 -Subject: [PATCH 076/269] UPSTREAM: iommu/riscv: Disable SADE +Subject: [RUYI PATCH] UPSTREAM: iommu/riscv: Disable SADE In terms of the iommu subystem the SADE/GADE feature "3.4. IOMMU updating of PTE accessed (A) and dirty (D) updates" is called dirty tracking. diff --git a/SPECS/linux/0077-UPSTREAM-iommu-riscv-Use-the-generic-iommu-page-tabl.patch b/SPECS/linux/0077-UPSTREAM-iommu-riscv-Use-the-generic-iommu-page-tabl.patch index 0bec3d03b4..7fcca04320 100644 --- a/SPECS/linux/0077-UPSTREAM-iommu-riscv-Use-the-generic-iommu-page-tabl.patch +++ b/SPECS/linux/0077-UPSTREAM-iommu-riscv-Use-the-generic-iommu-page-tabl.patch @@ -1,8 +1,7 @@ -From ed50d3475f69d828a05b881a731b1852d092a1e8 Mon Sep 17 00:00:00 2001 +From 1715db28fd8764e226c22f04ef0788b8eeead1c3 Mon Sep 17 00:00:00 2001 From: Jason Gunthorpe Date: Fri, 27 Feb 2026 11:25:38 -0400 -Subject: [PATCH 077/269] UPSTREAM: iommu/riscv: Use the generic iommu page - table +Subject: [RUYI PATCH] UPSTREAM: iommu/riscv: Use the generic iommu page table This is a fairly straightforward conversion of the RISC-V iommu driver to use the generic iommu page table code. diff --git a/SPECS/linux/0078-UPSTREAM-iommu-riscv-Enable-SVNAPOT-support-for-cont.patch b/SPECS/linux/0078-UPSTREAM-iommu-riscv-Enable-SVNAPOT-support-for-cont.patch index 84318876e1..82c80b2cf0 100644 --- a/SPECS/linux/0078-UPSTREAM-iommu-riscv-Enable-SVNAPOT-support-for-cont.patch +++ b/SPECS/linux/0078-UPSTREAM-iommu-riscv-Enable-SVNAPOT-support-for-cont.patch @@ -1,7 +1,7 @@ -From 4eccbb21ec7749e9a380a211cd492d8201790b3c Mon Sep 17 00:00:00 2001 +From da61e60d428f734608bb453fc37d49b1ce449afd Mon Sep 17 00:00:00 2001 From: Jason Gunthorpe Date: Fri, 27 Feb 2026 11:25:39 -0400 -Subject: [PATCH 078/269] UPSTREAM: iommu/riscv: Enable SVNAPOT support for +Subject: [RUYI PATCH] UPSTREAM: iommu/riscv: Enable SVNAPOT support for contiguous ptes This turns on a 64k page size. The "RISC-V IOMMU Architecture diff --git a/SPECS/linux/0079-UPSTREAM-iommu-riscv-Allow-RISC_VIOMMU-to-COMPILE_TE.patch b/SPECS/linux/0079-UPSTREAM-iommu-riscv-Allow-RISC_VIOMMU-to-COMPILE_TE.patch index 24407c4974..12d0cc5214 100644 --- a/SPECS/linux/0079-UPSTREAM-iommu-riscv-Allow-RISC_VIOMMU-to-COMPILE_TE.patch +++ b/SPECS/linux/0079-UPSTREAM-iommu-riscv-Allow-RISC_VIOMMU-to-COMPILE_TE.patch @@ -1,8 +1,7 @@ -From 648ac33a730ff526540f0eccb16de8566029f9da Mon Sep 17 00:00:00 2001 +From 469c466637a1ccb4ffed886b2d6667267a70c218 Mon Sep 17 00:00:00 2001 From: Jason Gunthorpe Date: Fri, 27 Feb 2026 11:25:41 -0400 -Subject: [PATCH 079/269] UPSTREAM: iommu/riscv: Allow RISC_VIOMMU to - COMPILE_TEST +Subject: [RUYI PATCH] UPSTREAM: iommu/riscv: Allow RISC_VIOMMU to COMPILE_TEST This driver used to use a lot of page table constants from the architecture code which prevented COMPILE_TEST on other architectures. Now that iommupt diff --git a/SPECS/linux/0080-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch b/SPECS/linux/0080-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch index 533bd3939a..7456eb80f0 100644 --- a/SPECS/linux/0080-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch +++ b/SPECS/linux/0080-UPSTREAM-riscv-Define-__riscv_copy_-vec_-words-bytes.patch @@ -1,7 +1,7 @@ -From 7a7f7da197b8a725ccd0708c0899416e7d73dda2 Mon Sep 17 00:00:00 2001 +From 34543ba7fb1ecd51a87c4f643b632200b8d6c448 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 29 Apr 2026 20:38:17 -0600 -Subject: [PATCH 080/269] UPSTREAM: riscv: Define +Subject: [RUYI PATCH] UPSTREAM: riscv: Define __riscv_copy_{,vec_}{words,bytes}_unaligned() using SYM_TYPED_FUNC_START After commit 67bdd7b01387 ("riscv: Split out measure_cycles() for diff --git a/SPECS/linux/0081-UPSTREAM-drm-amd-display-Add-min-clock-init-for-DML2.patch b/SPECS/linux/0081-UPSTREAM-drm-amd-display-Add-min-clock-init-for-DML2.patch new file mode 100644 index 0000000000..42a6de024d --- /dev/null +++ b/SPECS/linux/0081-UPSTREAM-drm-amd-display-Add-min-clock-init-for-DML2.patch @@ -0,0 +1,86 @@ +From 16c408532e6dbd202fa49f477cd44fb0c7c8207c Mon Sep 17 00:00:00 2001 +From: Ovidiu Bunea +Date: Tue, 10 Feb 2026 15:26:18 -0500 +Subject: [RUYI PATCH] UPSTREAM: drm/amd/display: Add min clock init for DML21 + mode programming + +[WHY & HOW] +0 stream cases do not go through any DML validation which leaves DCN +clocks in unoptimized states. + +If requesting DML validation or programming with 0 streams, program +DCN clocks to lowest DPM state. + +Reviewed-by: Dillon Varone +Signed-off-by: Ovidiu Bunea +Signed-off-by: Alex Hung +Tested-by: Dan Wheeler +Signed-off-by: Alex Deucher + +(cherry picked from commit 23dee18f6503d67b195f1513e404c78653ed0d40) +Signed-off-by: Xi Ruoyao +Signed-off-by: Han Gao +--- + .../dml2_0/dml21/dml21_translation_helper.c | 25 +++++++++++++++++++ + .../dml2_0/dml21/dml21_translation_helper.h | 1 + + .../display/dc/dml2_0/dml21/dml21_wrapper.c | 1 + + 3 files changed, 27 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +index bf5e7f4e0416..5bf3008a71c9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +@@ -927,3 +927,28 @@ void dml21_set_dc_p_state_type( + } + } + ++void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_state *context) ++{ ++ unsigned int lowest_dpm_state_index = 0; ++ struct dc_clocks *min_clocks = &context->bw_ctx.bw.dcn.clk; ++ ++ min_clocks->dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[lowest_dpm_state_index]; ++ min_clocks->dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[lowest_dpm_state_index]; ++ min_clocks->dcfclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dcfclk.clk_values_khz[lowest_dpm_state_index]; ++ min_clocks->dramclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.uclk.clk_values_khz[lowest_dpm_state_index]; ++ min_clocks->fclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.fclk.clk_values_khz[lowest_dpm_state_index]; ++ min_clocks->idle_dramclk_khz = 0; ++ min_clocks->idle_fclk_khz = 0; ++ min_clocks->dcfclk_deep_sleep_khz = 0; ++ min_clocks->fclk_p_state_change_support = true; ++ min_clocks->p_state_change_support = true; ++ min_clocks->dtbclk_en = false; ++ min_clocks->ref_dtbclk_khz = 0; ++ min_clocks->socclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.socclk.clk_values_khz[lowest_dpm_state_index]; ++ min_clocks->subvp_prefetch_dramclk_khz = 0; ++ min_clocks->subvp_prefetch_fclk_khz = 0; ++ min_clocks->phyclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.phyclk.clk_values_khz[lowest_dpm_state_index]; ++ min_clocks->stutter_efficiency.base_efficiency = 1; ++ min_clocks->stutter_efficiency.low_power_efficiency = 1; ++} ++ +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h +index 9880d3e0398e..f51d3d8a52c3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h +@@ -25,4 +25,5 @@ void dml21_map_hw_resources(struct dml2_context *dml_ctx); + void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config); + void dml21_set_dc_p_state_type(struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming, bool sub_vp_enabled); + unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id, const struct dc_plane_state *plane, const struct dc_state *context); ++void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_state *context); + #endif +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c +index 798abb2b2e67..96c62bd6a37b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c +@@ -215,6 +215,7 @@ static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_s + return true; + + if (context->stream_count == 0) { ++ dml21_init_min_clocks_for_dc_state(dml_ctx, context); + dml21_build_fams2_programming(in_dc, context, dml_ctx); + return true; + } +-- +2.53.0 + diff --git a/SPECS/linux/0081-UPSTREAM-riscv-mm-Fixup-no5lvl-failure-when-vaddr-is.patch b/SPECS/linux/0081-UPSTREAM-riscv-mm-Fixup-no5lvl-failure-when-vaddr-is.patch deleted file mode 100644 index c619aafd04..0000000000 --- a/SPECS/linux/0081-UPSTREAM-riscv-mm-Fixup-no5lvl-failure-when-vaddr-is.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 2317b5fc8310beaff7198764bb2602cb64e84df9 Mon Sep 17 00:00:00 2001 -From: "Guo Ren (Alibaba DAMO Academy)" -Date: Sun, 25 Jan 2026 00:52:12 -0500 -Subject: [PATCH 081/269] UPSTREAM: riscv: mm: Fixup no5lvl failure when vaddr - is invalid -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Unlike no4lvl, no5lvl still continues to detect satp, which -requires va=pa mapping. When pa=0x800000000000, no5lvl -would fail in Sv48 mode due to an illegal VA value of -0x800000000000. - -So, prevent detecting the satp flow for no5lvl, when -vaddr is invalid. Add the is_vaddr_valid() function for -checking. - -Fixes: 26e7aacb83df ("riscv: Allow to downgrade paging mode from the command line") -Cc: Alexandre Ghiti -Cc: Björn Töpel -Signed-off-by: Guo Ren (Alibaba DAMO Academy) -Tested-by: Fangyu Yu -Link: https://patch.msgid.link/20260125055212.433163-1-guoren@kernel.org -[pjw@kernel.org: cleaned up commit message] -Signed-off-by: Paul Walmsley -(cherry picked from commit db909bd7986c10da074917af3dae83a60fa65093) -Signed-off-by: Han Gao ---- - arch/riscv/mm/init.c | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index c12590ab3d0e..31007b426d54 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -846,6 +846,27 @@ static void __init set_mmap_rnd_bits_max(void) - mmap_rnd_bits_max = MMAP_VA_BITS - PAGE_SHIFT - 3; - } - -+static bool __init is_vaddr_valid(unsigned long va) -+{ -+ unsigned long up = 0; -+ -+ switch (satp_mode) { -+ case SATP_MODE_39: -+ up = 1UL << 38; -+ break; -+ case SATP_MODE_48: -+ up = 1UL << 47; -+ break; -+ case SATP_MODE_57: -+ up = 1UL << 56; -+ break; -+ default: -+ return false; -+ } -+ -+ return (va < up) || (va >= (ULONG_MAX - up + 1)); -+} -+ - /* - * There is a simple way to determine if 4-level is supported by the - * underlying hardware: establish 1:1 mapping in 4-level page table mode -@@ -887,6 +908,9 @@ static __init void set_satp_mode(uintptr_t dtb_pa) - set_satp_mode_pmd + PMD_SIZE, - PMD_SIZE, PAGE_KERNEL_EXEC); - retry: -+ if (!is_vaddr_valid(set_satp_mode_pmd)) -+ goto out; -+ - create_pgd_mapping(early_pg_dir, - set_satp_mode_pmd, - pgtable_l5_enabled ? -@@ -909,6 +933,7 @@ static __init void set_satp_mode(uintptr_t dtb_pa) - disable_pgtable_l4(); - } - -+out: - memset(early_pg_dir, 0, PAGE_SIZE); - memset(early_p4d, 0, PAGE_SIZE); - memset(early_pud, 0, PAGE_SIZE); --- -2.53.0 - diff --git a/SPECS/linux/0082-UPSTREAM-drm-amd-display-Add-min-clock-init-for-DML2.patch b/SPECS/linux/0082-UPSTREAM-drm-amd-display-Add-min-clock-init-for-DML2.patch deleted file mode 100644 index c8bd563685..0000000000 --- a/SPECS/linux/0082-UPSTREAM-drm-amd-display-Add-min-clock-init-for-DML2.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 8c600c53e43b0fede5a5ed881f04f1b846a2ee98 Mon Sep 17 00:00:00 2001 -From: Ovidiu Bunea -Date: Tue, 10 Feb 2026 15:26:18 -0500 -Subject: [PATCH 082/269] UPSTREAM: drm/amd/display: Add min clock init for - DML21 mode programming - -[WHY & HOW] -0 stream cases do not go through any DML validation which leaves DCN -clocks in unoptimized states. - -If requesting DML validation or programming with 0 streams, program -DCN clocks to lowest DPM state. - -Reviewed-by: Dillon Varone -Signed-off-by: Ovidiu Bunea -Signed-off-by: Alex Hung -Tested-by: Dan Wheeler -Signed-off-by: Alex Deucher - -(cherry picked from commit 23dee18f6503d67b195f1513e404c78653ed0d40) -Signed-off-by: Xi Ruoyao -Signed-off-by: Han Gao ---- - .../dml2_0/dml21/dml21_translation_helper.c | 25 +++++++++++++++++++ - .../dml2_0/dml21/dml21_translation_helper.h | 1 + - .../display/dc/dml2_0/dml21/dml21_wrapper.c | 1 + - 3 files changed, 27 insertions(+) - -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c -index bf5e7f4e0416..5bf3008a71c9 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c -@@ -927,3 +927,28 @@ void dml21_set_dc_p_state_type( - } - } - -+void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_state *context) -+{ -+ unsigned int lowest_dpm_state_index = 0; -+ struct dc_clocks *min_clocks = &context->bw_ctx.bw.dcn.clk; -+ -+ min_clocks->dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[lowest_dpm_state_index]; -+ min_clocks->dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[lowest_dpm_state_index]; -+ min_clocks->dcfclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dcfclk.clk_values_khz[lowest_dpm_state_index]; -+ min_clocks->dramclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.uclk.clk_values_khz[lowest_dpm_state_index]; -+ min_clocks->fclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.fclk.clk_values_khz[lowest_dpm_state_index]; -+ min_clocks->idle_dramclk_khz = 0; -+ min_clocks->idle_fclk_khz = 0; -+ min_clocks->dcfclk_deep_sleep_khz = 0; -+ min_clocks->fclk_p_state_change_support = true; -+ min_clocks->p_state_change_support = true; -+ min_clocks->dtbclk_en = false; -+ min_clocks->ref_dtbclk_khz = 0; -+ min_clocks->socclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.socclk.clk_values_khz[lowest_dpm_state_index]; -+ min_clocks->subvp_prefetch_dramclk_khz = 0; -+ min_clocks->subvp_prefetch_fclk_khz = 0; -+ min_clocks->phyclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.phyclk.clk_values_khz[lowest_dpm_state_index]; -+ min_clocks->stutter_efficiency.base_efficiency = 1; -+ min_clocks->stutter_efficiency.low_power_efficiency = 1; -+} -+ -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h -index 9880d3e0398e..f51d3d8a52c3 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h -@@ -25,4 +25,5 @@ void dml21_map_hw_resources(struct dml2_context *dml_ctx); - void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config); - void dml21_set_dc_p_state_type(struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming, bool sub_vp_enabled); - unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id, const struct dc_plane_state *plane, const struct dc_state *context); -+void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_state *context); - #endif -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -index 798abb2b2e67..96c62bd6a37b 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -@@ -215,6 +215,7 @@ static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_s - return true; - - if (context->stream_count == 0) { -+ dml21_init_min_clocks_for_dc_state(dml_ctx, context); - dml21_build_fams2_programming(in_dc, context, dml_ctx); - return true; - } --- -2.53.0 - diff --git a/SPECS/linux/0082-UPSTREAM-drm-amd-display-Backport-dml21-DC_RUN_WITH_.patch b/SPECS/linux/0082-UPSTREAM-drm-amd-display-Backport-dml21-DC_RUN_WITH_.patch new file mode 100644 index 0000000000..e3ca2dc6b7 --- /dev/null +++ b/SPECS/linux/0082-UPSTREAM-drm-amd-display-Backport-dml21-DC_RUN_WITH_.patch @@ -0,0 +1,67 @@ +From fab74884e826254f5ab9b2b1c57c94225c37096b Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao +Date: Mon, 11 May 2026 16:42:19 +0800 +Subject: [RUYI PATCH] UPSTREAM: drm/amd/display: Backport dml21 + DC_RUN_WITH_PREEMPTION_ENABLED addition from DC 3.2.373 + +It's a part of the upstream commit e56e3cff2a1b ("drm/amd/display: Sync +dcn42 with DC 3.2.373") needed for the following backports moving FPU +guards from DML to DC. + +Signed-off-by: Xi Ruoyao +Signed-off-by: Han Gao +--- + .../amd/display/dc/dml2_0/dml21/dml21_wrapper.c | 14 ++++++++++---- + 1 file changed, 10 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c +index 96c62bd6a37b..2623e917ec28 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c +@@ -9,16 +9,21 @@ + #include "dml21_utils.h" + #include "dml21_translation_helper.h" + #include "dml2_dc_resource_mgmt.h" ++#include "dc_fpu.h" ++ ++#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) ++#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code ++#endif // !DC_RUN_WITH_PREEMPTION_ENABLED + + #define INVALID -1 + + static bool dml21_allocate_memory(struct dml2_context **dml_ctx) + { +- *dml_ctx = vzalloc(sizeof(struct dml2_context)); ++ DC_RUN_WITH_PREEMPTION_ENABLED(*dml_ctx = vzalloc(sizeof(struct dml2_context))); + if (!(*dml_ctx)) + return false; + +- (*dml_ctx)->v21.dml_init.dml2_instance = vzalloc(sizeof(struct dml2_instance)); ++ DC_RUN_WITH_PREEMPTION_ENABLED((*dml_ctx)->v21.dml_init.dml2_instance = vzalloc(sizeof(struct dml2_instance))); + if (!((*dml_ctx)->v21.dml_init.dml2_instance)) + return false; + +@@ -28,7 +33,7 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx) + (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; + (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; + +- (*dml_ctx)->v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming)); ++ DC_RUN_WITH_PREEMPTION_ENABLED((*dml_ctx)->v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming))); + if (!((*dml_ctx)->v21.mode_programming.programming)) + return false; + +@@ -70,8 +75,9 @@ static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, con + bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) + { + /* Allocate memory for initializing DML21 instance */ +- if (!dml21_allocate_memory(dml_ctx)) ++ if (!dml21_allocate_memory(dml_ctx)) { + return false; ++ } + + dml21_init(in_dc, *dml_ctx, config); + +-- +2.53.0 + diff --git a/SPECS/linux/0083-UPSTREAM-drm-amd-display-Backport-dml21-DC_RUN_WITH_.patch b/SPECS/linux/0083-UPSTREAM-drm-amd-display-Backport-dml21-DC_RUN_WITH_.patch deleted file mode 100644 index 33e64ffaf5..0000000000 --- a/SPECS/linux/0083-UPSTREAM-drm-amd-display-Backport-dml21-DC_RUN_WITH_.patch +++ /dev/null @@ -1,67 +0,0 @@ -From a0b2a89dfeef479667ec1148740053b59f60ec23 Mon Sep 17 00:00:00 2001 -From: Xi Ruoyao -Date: Mon, 11 May 2026 16:42:19 +0800 -Subject: [PATCH 083/269] UPSTREAM: drm/amd/display: Backport dml21 - DC_RUN_WITH_PREEMPTION_ENABLED addition from DC 3.2.373 - -It's a part of the upstream commit e56e3cff2a1b ("drm/amd/display: Sync -dcn42 with DC 3.2.373") needed for the following backports moving FPU -guards from DML to DC. - -Signed-off-by: Xi Ruoyao -Signed-off-by: Han Gao ---- - .../amd/display/dc/dml2_0/dml21/dml21_wrapper.c | 14 ++++++++++---- - 1 file changed, 10 insertions(+), 4 deletions(-) - -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -index 96c62bd6a37b..2623e917ec28 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -@@ -9,16 +9,21 @@ - #include "dml21_utils.h" - #include "dml21_translation_helper.h" - #include "dml2_dc_resource_mgmt.h" -+#include "dc_fpu.h" -+ -+#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) -+#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code -+#endif // !DC_RUN_WITH_PREEMPTION_ENABLED - - #define INVALID -1 - - static bool dml21_allocate_memory(struct dml2_context **dml_ctx) - { -- *dml_ctx = vzalloc(sizeof(struct dml2_context)); -+ DC_RUN_WITH_PREEMPTION_ENABLED(*dml_ctx = vzalloc(sizeof(struct dml2_context))); - if (!(*dml_ctx)) - return false; - -- (*dml_ctx)->v21.dml_init.dml2_instance = vzalloc(sizeof(struct dml2_instance)); -+ DC_RUN_WITH_PREEMPTION_ENABLED((*dml_ctx)->v21.dml_init.dml2_instance = vzalloc(sizeof(struct dml2_instance))); - if (!((*dml_ctx)->v21.dml_init.dml2_instance)) - return false; - -@@ -28,7 +33,7 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx) - (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; - (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; - -- (*dml_ctx)->v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming)); -+ DC_RUN_WITH_PREEMPTION_ENABLED((*dml_ctx)->v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming))); - if (!((*dml_ctx)->v21.mode_programming.programming)) - return false; - -@@ -70,8 +75,9 @@ static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, con - bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) - { - /* Allocate memory for initializing DML21 instance */ -- if (!dml21_allocate_memory(dml_ctx)) -+ if (!dml21_allocate_memory(dml_ctx)) { - return false; -+ } - - dml21_init(in_dc, *dml_ctx, config); - --- -2.53.0 - diff --git a/SPECS/linux/0083-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch b/SPECS/linux/0083-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch new file mode 100644 index 0000000000..160df5c013 --- /dev/null +++ b/SPECS/linux/0083-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch @@ -0,0 +1,2921 @@ +From 06d3a3080e44798d7b786bfd80432f4db9281cd0 Mon Sep 17 00:00:00 2001 +From: Rafal Ostrowski +Date: Tue, 24 Feb 2026 15:36:09 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/amd/display: Move FPU Guards From DML To + DC - Part 1 + +[Why] +FPU guards (DC_FP_START/DC_FP_END) are required to wrap around code that +can manipulates floats. To do this properly, the FPU guards must be used +in a file that is not compiled as a FPU unit. If the guards are used in +a file that is a FPU unit, other sections in the file that aren't guarded +may be end up being compiled to use FPU operations. + +[How] +Added DC_FP_START and DC_FP_END to DC functions that call DML functions +using FPU. + +Reviewed-by: Dillon Varone +Signed-off-by: Rafal Ostrowski +Signed-off-by: Alex Hung +Signed-off-by: Alex Deucher + +(cherry picked from commit 3539437f354bd24c98928a80d4db3a23fa2a7b19) +Signed-off-by: Xi Ruoyao +Signed-off-by: Han Gao +--- + .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 25 +- + .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.h | 17 +- + .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 2 - + .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 - + drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +- + .../gpu/drm/amd/display/dc/core/dc_state.c | 75 +- + .../gpu/drm/amd/display/dc/core/dc_stream.c | 15 +- + .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 4 +- + .../dc/resource/dcn35/dcn35_resource.c | 10 +- + .../dc/resource/dcn35/dcn35_resource.h | 1 + + .../dc/resource/dcn351/dcn351_resource.c | 10 +- + .../dc/resource/dcn36/dcn36_resource.c | 4 +- + .../dc/resource/dcn401/dcn401_resource.c | 30 +- + .../dc/resource/dcn42/dcn42_resource.c | 2355 +++++++++++++++++ + 14 files changed, 2508 insertions(+), 47 deletions(-) + create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +index e46f8ce41d87..8ba9b4f56f87 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +@@ -53,11 +53,30 @@ inline void dc_assert_fp_enabled(void) + { + int depth; + +- depth = __this_cpu_read(fpu_recursion_depth); ++ depth = this_cpu_read(fpu_recursion_depth); + + ASSERT(depth >= 1); + } + ++/** ++ * dc_assert_fp_enabled - Check if FPU protection is enabled ++ * ++ * This function tells if the code is already under FPU protection or not. A ++ * function that works as an API for a set of FPU operations can use this ++ * function for checking if the caller invoked it after DC_FP_START(). For ++ * example, take a look at dcn20_fpu.c file. ++ * ++ * Similar to dc_assert_fp_enabled, but does not assert, returns status instead. ++ */ ++inline bool dc_is_fp_enabled(void) ++{ ++ int depth; ++ ++ depth = this_cpu_read(fpu_recursion_depth); ++ ++ return (depth >= 1); ++} ++ + /** + * dc_fpu_begin - Enables FPU protection + * @function_name: A string containing the function name for debug purposes +@@ -77,7 +96,7 @@ void dc_fpu_begin(const char *function_name, const int line) + + WARN_ON_ONCE(!in_task()); + preempt_disable(); +- depth = __this_cpu_inc_return(fpu_recursion_depth); ++ depth = this_cpu_inc_return(fpu_recursion_depth); + if (depth == 1) { + BUG_ON(!kernel_fpu_available()); + kernel_fpu_begin(); +@@ -100,7 +119,7 @@ void dc_fpu_end(const char *function_name, const int line) + { + int depth; + +- depth = __this_cpu_dec_return(fpu_recursion_depth); ++ depth = this_cpu_dec_return(fpu_recursion_depth); + if (depth == 0) { + kernel_fpu_end(); + } else { +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h +index 4e921632bc4e..5e95419d3798 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h +@@ -28,15 +28,30 @@ + #define __DC_FPU_H__ + + void dc_assert_fp_enabled(void); ++bool dc_is_fp_enabled(void); + void dc_fpu_begin(const char *function_name, const int line); + void dc_fpu_end(const char *function_name, const int line); + + #ifndef _LINUX_FPU_COMPILATION_UNIT + #define DC_FP_START() dc_fpu_begin(__func__, __LINE__) + #define DC_FP_END() dc_fpu_end(__func__, __LINE__) ++#ifdef CONFIG_DRM_AMD_DC_FP ++#define DC_RUN_WITH_PREEMPTION_ENABLED(code) \ ++ do { \ ++ bool dc_fp_enabled = dc_is_fp_enabled(); \ ++ if (dc_fp_enabled) \ ++ DC_FP_END(); \ ++ code; \ ++ if (dc_fp_enabled) \ ++ DC_FP_START(); \ ++ } while (0) ++#else ++#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code ++#endif // !CONFIG_DRM_AMD_DC_FP + #else + #define DC_FP_START() BUILD_BUG() + #define DC_FP_END() BUILD_BUG() +-#endif ++#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code ++#endif // !_LINUX_FPU_COMPILATION_UNIT + + #endif /* __DC_FPU_H__ */ +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c +index b0aba3a6f13c..e06f06158ac8 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c +@@ -421,10 +421,8 @@ static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) + clk_mgr_base->bw_params->dc_mode_softmax_memclk = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK); + + /* Refresh bounding box */ +- DC_FP_START(); + clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( + clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); +- DC_FP_END(); + } + + static bool dcn3_is_smu_present(struct clk_mgr *clk_mgr_base) +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +index 2856b0337e87..4007ab353ffd 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +@@ -1059,11 +1059,9 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) + if (!clk_mgr->dpm_present) + dcn32_patch_dpm_table(clk_mgr_base->bw_params); + +- DC_FP_START(); + /* Refresh bounding box */ + clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( + clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); +- DC_FP_END(); + } + + static bool dcn32_are_clock_states_equal(struct dc_clocks *a, +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 73fde9df22d1..c406cc963b5a 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1165,11 +1165,8 @@ static bool dc_construct(struct dc *dc, + #ifdef CONFIG_DRM_AMD_DC_FP + dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present; + +- if (dc->res_pool->funcs->update_bw_bounding_box) { +- DC_FP_START(); ++ if (dc->res_pool->funcs->update_bw_bounding_box) + dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); +- DC_FP_END(); +- } + dc->soc_and_ip_translator = dc_create_soc_and_ip_translator(dc_ctx->dce_version); + if (!dc->soc_and_ip_translator) + goto fail; +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c +index a40e5c44143f..13d334c2cb6b 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c +@@ -205,19 +205,33 @@ struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *p + state->power_source = params ? params->power_source : DC_POWER_SOURCE_AC; + + #ifdef CONFIG_DRM_AMD_DC_FP ++ bool status; ++ + if (dc->debug.using_dml2) { +- if (!dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2)) { ++ DC_FP_START(); ++ status = dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2); ++ DC_FP_END(); ++ ++ if (!status) { + dc_state_release(state); + return NULL; + } + +- if (dc->caps.dcmode_power_limits_present && !dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source)) { +- dc_state_release(state); +- return NULL; ++ if (dc->caps.dcmode_power_limits_present) { ++ bool status; ++ ++ DC_FP_START(); ++ status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source); ++ DC_FP_END(); ++ ++ if (!status) { ++ dc_state_release(state); ++ return NULL; ++ } + } +- } +-#endif + ++ } ++#endif // CONFIG_DRM_AMD_DC_FP + kref_init(&state->refcount); + + return state; +@@ -235,14 +249,20 @@ void dc_state_copy(struct dc_state *dst_state, struct dc_state *src_state) + + #ifdef CONFIG_DRM_AMD_DC_FP + dst_state->bw_ctx.dml2 = dst_dml2; +- if (src_state->bw_ctx.dml2) ++ if (src_state->bw_ctx.dml2) { ++ DC_FP_START(); + dml2_copy(dst_state->bw_ctx.dml2, src_state->bw_ctx.dml2); ++ DC_FP_END(); ++ } + + dst_state->bw_ctx.dml2_dc_power_source = dst_dml2_dc_power_source; +- if (src_state->bw_ctx.dml2_dc_power_source) +- dml2_copy(dst_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source); +-#endif + ++ if (src_state->bw_ctx.dml2_dc_power_source) { ++ DC_FP_START(); ++ dml2_copy(dst_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source); ++ DC_FP_END(); ++ } ++#endif // CONFIG_DRM_AMD_DC_FP + /* context refcount should not be overridden */ + dst_state->refcount = refcount; + } +@@ -258,22 +278,35 @@ struct dc_state *dc_state_create_copy(struct dc_state *src_state) + dc_state_copy_internal(new_state, src_state); + + #ifdef CONFIG_DRM_AMD_DC_FP ++ bool status; ++ + new_state->bw_ctx.dml2 = NULL; + new_state->bw_ctx.dml2_dc_power_source = NULL; + +- if (src_state->bw_ctx.dml2 && +- !dml2_create_copy(&new_state->bw_ctx.dml2, src_state->bw_ctx.dml2)) { +- dc_state_release(new_state); +- return NULL; +- } ++ if (src_state->bw_ctx.dml2) { ++ DC_FP_START(); ++ status = dml2_create_copy(&new_state->bw_ctx.dml2, src_state->bw_ctx.dml2); ++ DC_FP_END(); + +- if (src_state->bw_ctx.dml2_dc_power_source && +- !dml2_create_copy(&new_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source)) { +- dc_state_release(new_state); +- return NULL; ++ if (!status) { ++ dc_state_release(new_state); ++ return NULL; ++ } + } +-#endif + ++ ++ if (src_state->bw_ctx.dml2_dc_power_source) { ++ DC_FP_START(); ++ status = dml2_create_copy(&new_state->bw_ctx.dml2_dc_power_source, ++ src_state->bw_ctx.dml2_dc_power_source); ++ DC_FP_END(); ++ ++ if (!status) { ++ dc_state_release(new_state); ++ return NULL; ++ } ++ } ++#endif // CONFIG_DRM_AMD_DC_FP + kref_init(&new_state->refcount); + + return new_state; +@@ -351,11 +384,13 @@ static void dc_state_free(struct kref *kref) + dc_state_destruct(state); + + #ifdef CONFIG_DRM_AMD_DC_FP ++ DC_FP_START(); + dml2_destroy(state->bw_ctx.dml2); + state->bw_ctx.dml2 = 0; + + dml2_destroy(state->bw_ctx.dml2_dc_power_source); + state->bw_ctx.dml2_dc_power_source = 0; ++ DC_FP_END(); + #endif + + kvfree(state); +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +index baf820e6eae8..dca64e1671f6 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +@@ -42,6 +42,13 @@ + #define MAX(x, y) ((x > y) ? x : y) + #endif + ++#include "dc_fpu.h" ++ ++#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) ++#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code ++#endif // !DC_RUN_WITH_PREEMPTION_ENABLED ++ ++ + /******************************************************************************* + * Private functions + ******************************************************************************/ +@@ -170,11 +177,15 @@ struct dc_stream_state *dc_create_stream_for_sink( + if (sink == NULL) + goto fail; + +- stream = kzalloc_obj(struct dc_stream_state, GFP_ATOMIC); ++ DC_RUN_WITH_PREEMPTION_ENABLED(stream = kzalloc_obj(struct dc_stream_state, GFP_ATOMIC)); ++ + if (stream == NULL) + goto fail; + +- stream->update_scratch = kzalloc((int32_t) dc_update_scratch_space_size(), GFP_ATOMIC); ++ DC_RUN_WITH_PREEMPTION_ENABLED(stream->update_scratch = ++ kzalloc((int32_t) dc_update_scratch_space_size(), ++ GFP_ATOMIC)); ++ + if (stream->update_scratch == NULL) + goto fail; + +diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +index 4dfb6c865831..a6c3a1f5fbfa 100644 +--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +@@ -371,8 +371,8 @@ void dcn401_init_hw(struct dc *dc) + dc->res_pool->funcs->update_bw_bounding_box && + dc->clk_mgr && dc->clk_mgr->bw_params) { + /* update bounding box if FAMS2 disabled, or if dchub clk has changed */ +- dc->res_pool->funcs->update_bw_bounding_box(dc, +- dc->clk_mgr->bw_params); ++ if (dc->clk_mgr) ++ dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); + } + } + } +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +index 598b2f25881d..adbd23fcc9b7 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +@@ -1773,9 +1773,11 @@ static enum dc_status dcn35_validate_bandwidth(struct dc *dc, + { + bool out = false; + ++ DC_FP_START(); + out = dml2_validate(dc, context, + context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, + validate_mode); ++ DC_FP_END(); + + if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) + return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; +@@ -1809,6 +1811,12 @@ static int populate_dml_pipes_from_context_fpu(struct dc *dc, + return ret; + } + ++void dcn35_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++{ ++ DC_FP_START(); ++ dcn35_update_bw_bounding_box_fpu(dc, bw_params); ++ DC_FP_END(); ++} + static struct resource_funcs dcn35_res_pool_funcs = { + .destroy = dcn35_destroy_resource_pool, + .link_enc_create = dcn35_link_encoder_create, +@@ -1830,7 +1838,7 @@ static struct resource_funcs dcn35_res_pool_funcs = { + .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, + .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, + .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, +- .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu, ++ .update_bw_bounding_box = dcn35_update_bw_bounding_box, + .patch_unknown_plane_state = dcn35_patch_unknown_plane_state, + .get_panel_config_defaults = dcn35_get_panel_config_defaults, + .get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia, +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h +index 9c56ae76e0c7..6c2c61c711b9 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h +@@ -312,4 +312,5 @@ struct resource_pool *dcn35_create_resource_pool( + #define DPP_REG_LIST_DCN35_RI(id)\ + DPP_REG_LIST_DCN30_COMMON_RI(id) + ++void dcn35_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); + #endif /* _DCN35_RESOURCE_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +index 7e15d07df7a3..dc70b771633f 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +@@ -1753,9 +1753,11 @@ static enum dc_status dcn351_validate_bandwidth(struct dc *dc, + { + bool out = false; + ++ DC_FP_START(); + out = dml2_validate(dc, context, + context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, + validate_mode); ++ DC_FP_END(); + + if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) + return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; +@@ -1782,6 +1784,12 @@ static int populate_dml_pipes_from_context_fpu(struct dc *dc, + + } + ++static void dcn351_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++{ ++ DC_FP_START(); ++ dcn351_update_bw_bounding_box_fpu(dc, bw_params); ++ DC_FP_END(); ++} + static struct resource_funcs dcn351_res_pool_funcs = { + .destroy = dcn351_destroy_resource_pool, + .link_enc_create = dcn35_link_encoder_create, +@@ -1803,7 +1811,7 @@ static struct resource_funcs dcn351_res_pool_funcs = { + .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, + .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, + .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, +- .update_bw_bounding_box = dcn351_update_bw_bounding_box_fpu, ++ .update_bw_bounding_box = dcn351_update_bw_bounding_box, + .patch_unknown_plane_state = dcn35_patch_unknown_plane_state, + .get_panel_config_defaults = dcn35_get_panel_config_defaults, + .get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia, +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +index 83fee2ca61bf..2667a2e8b04f 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +@@ -1760,9 +1760,11 @@ static enum dc_status dcn35_validate_bandwidth(struct dc *dc, + { + bool out = false; + ++ DC_FP_START(); + out = dml2_validate(dc, context, + context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, + validate_mode); ++ DC_FP_END(); + + if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) + return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; +@@ -1810,7 +1812,7 @@ static struct resource_funcs dcn36_res_pool_funcs = { + .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, + .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, + .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, +- .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu, ++ .update_bw_bounding_box = dcn35_update_bw_bounding_box, + .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, + .get_panel_config_defaults = dcn35_get_panel_config_defaults, + .get_preferred_eng_id_dpia = dcn36_get_preferred_eng_id_dpia, +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +index e37aab939a41..237d1a561da7 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +@@ -1643,8 +1643,10 @@ static struct dc_cap_funcs cap_funcs = { + .get_subvp_en = dcn32_subvp_in_use, + }; + +-static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++static void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) + { ++ dc_assert_fp_enabled(); ++ + /* re-calculate the available MALL size if required */ + if (bw_params->num_channels > 0) { + dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall( +@@ -1653,17 +1655,19 @@ static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b + dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; + } + +- DC_FP_START(); +- + if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2) + dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); + + if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source) + dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source); ++} + ++static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++{ ++ DC_FP_START(); ++ dcn401_update_bw_bounding_box_fpu(dc, bw_params); + DC_FP_END(); + } +- + enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state) + { + plane_state->tiling_info.gfxversion = DcGfxAddr3; +@@ -1688,10 +1692,13 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, + } + } + +- if (dc->debug.using_dml2) ++ if (dc->debug.using_dml2) { ++ DC_FP_START(); + status = dml2_validate(dc, context, + context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, + validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; ++ DC_FP_END(); ++ } + + if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) { + /* check new stream configuration still supports cursor if subvp used */ +@@ -1710,10 +1717,13 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, + + if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) { + /* attempt to validate again with subvp disabled due to cursor */ +- if (dc->debug.using_dml2) ++ if (dc->debug.using_dml2) { ++ DC_FP_START(); + status = dml2_validate(dc, context, + context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, + validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; ++ DC_FP_END(); ++ } + } + + return status; +@@ -1722,9 +1732,13 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, + void dcn401_prepare_mcache_programming(struct dc *dc, + struct dc_state *context) + { +- if (dc->debug.using_dml21) ++ if (dc->debug.using_dml21) { ++ DC_FP_START(); + dml2_prepare_mcache_programming(dc, context, +- context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); ++ context->power_source == DC_POWER_SOURCE_DC ? ++ context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); ++ DC_FP_END(); ++ } + } + + static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +new file mode 100644 +index 000000000000..b9532ebcced4 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +@@ -0,0 +1,2355 @@ ++// SPDX-License-Identifier: MIT ++// ++// Copyright 2026 Advanced Micro Devices, Inc. ++ ++#include "dm_services.h" ++#include "dc.h" ++ ++#include "dcn32/dcn32_init.h" ++#include "dcn42/dcn42_init.h" ++ ++#include "resource.h" ++#include "include/irq_service_interface.h" ++ ++#include "dcn42_resource.h" ++#include "dcn42_resource_fpu.h" ++#include "dcn20/dcn20_resource.h" ++#include "dcn30/dcn30_resource.h" ++#include "dcn31/dcn31_resource.h" ++#include "dcn32/dcn32_resource.h" ++#include "dcn35/dcn35_resource.h" ++#include "dcn321/dcn321_resource.h" ++#include "dcn401/dcn401_resource.h" ++ ++#include "dcn10/dcn10_ipp.h" ++#include "dcn35/dcn35_hubbub.h" ++#include "dcn42/dcn42_hubbub.h" ++#include "dcn401/dcn401_mpc.h" ++#include "dcn42/dcn42_mpc.h" ++#include "dcn35/dcn35_hubp.h" ++#include "dcn42/dcn42_hubp.h" ++#include "irq/dcn42/irq_service_dcn42.h" ++#include "dcn42/dcn42_dpp.h" ++#include "dcn401/dcn401_dsc.h" ++#include "dcn42/dcn42_optc.h" ++#include "dcn20/dcn20_hwseq.h" ++#include "dcn30/dcn30_hwseq.h" ++#include "dce110/dce110_hwseq.h" ++#include "dcn35/dcn35_opp.h" ++#include "dcn30/dcn30_vpg.h" ++#include "dcn31/dcn31_vpg.h" ++#include "dcn42/dcn42_dio_stream_encoder.h" ++#include "dcn42/dcn42_pg_cntl.h" ++#include "dcn31/dcn31_hpo_dp_stream_encoder.h" ++#include "dcn31/dcn31_hpo_dp_link_encoder.h" ++#include "dcn32/dcn32_hpo_dp_link_encoder.h" ++#include "dcn42/dcn42_hpo_dp_link_encoder.h" ++#include "dcn31/dcn31_apg.h" ++#include "dcn31/dcn31_dio_link_encoder.h" ++#include "dcn401/dcn401_dio_link_encoder.h" ++#include "dcn10/dcn10_link_encoder.h" ++#include "dcn321/dcn321_dio_link_encoder.h" ++#include "dce/dce_clock_source.h" ++#include "dce/dce_audio.h" ++#include "dce/dce_hwseq.h" ++#include "clk_mgr.h" ++#include "dio/virtual/virtual_stream_encoder.h" ++#include "dml/display_mode_vba.h" ++#include "dcn42/dcn42_dccg.h" ++#include "dcn10/dcn10_resource.h" ++#include "link_service.h" ++#include "dcn31/dcn31_panel_cntl.h" ++ ++#include "dcn30/dcn30_dwb.h" ++#include "dcn42/dcn42_mmhubbub.h" ++#include "dcn42/dcn42_dio_link_encoder.h" ++ ++#include "dcn/dcn_4_2_0_offset.h" ++#include "dcn/dcn_4_2_0_sh_mask.h" ++#include "dpcs/dpcs_4_0_0_offset.h" ++#include "dpcs/dpcs_4_0_0_sh_mask.h" ++ ++#include "reg_helper.h" ++#include "dce/dmub_abm.h" ++#include "dce/dmub_psr.h" ++#include "dce/dmub_replay.h" ++#include "dce/dce_aux.h" ++#include "dce/dce_i2c.h" ++ ++#include "dml/dcn30/display_mode_vba_30.h" ++#include "vm_helper.h" ++#include "dcn20/dcn20_vmid.h" ++ ++#include "dc_state_priv.h" ++#include "link_enc_cfg.h" ++ ++#include "dml2_0/dml2_wrapper.h" ++ ++#define regBIF_BX0_BIOS_SCRATCH_3 0x003b ++#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 ++#define regBIF_BX0_BIOS_SCRATCH_6 0x003e ++#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 ++ ++#define DC_LOGGER_INIT(logger) ++ ++enum dcn401_clk_src_array_id { ++ DCN401_CLK_SRC_PLL0, ++ DCN401_CLK_SRC_PLL1, ++ DCN401_CLK_SRC_PLL2, ++ DCN401_CLK_SRC_PLL3, ++ DCN401_CLK_SRC_PLL4, ++ DCN401_CLK_SRC_TOTAL ++}; ++ ++/* begin ++ * macros to expend register list macro defined in HW object header file ++ */ ++ ++/* DCN */ ++#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] ++ ++#define BASE(seg) BASE_INNER(seg) ++ ++#define SR(reg_name) \ ++ REG_STRUCT.reg_name = BASE(reg##reg_name##_BASE_IDX) + \ ++ reg##reg_name ++#define SR_ARR(reg_name, id) \ ++ REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \ ++ reg##reg_name ++#define SR_ARR_INIT(reg_name, id, value) \ ++ REG_STRUCT[id].reg_name = value ++ ++#define SRI(reg_name, block, id) \ ++ REG_STRUCT.reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ ++ reg##block##id##_##reg_name ++ ++#define SRI_ARR(reg_name, block, id) \ ++ REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ ++ reg##block##id##_##reg_name ++ ++/* ++ * Used when a reg_name would otherwise begin with an integer ++ */ ++#define SRI_ARR_US(reg_name, block, id) \ ++ REG_STRUCT[id].reg_name = BASE(reg##block##id##reg_name##_BASE_IDX) + \ ++ reg##block##id##reg_name ++#define SR_ARR_I2C(reg_name, id) \ ++ REG_STRUCT[id - 1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name ++ ++#define SRI_ARR_I2C(reg_name, block, id) \ ++ REG_STRUCT[id - 1].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ ++ reg##block##id##_##reg_name ++ ++ ++#define SRI_ARR_ALPHABET(reg_name, block, index, id) \ ++ REG_STRUCT[index].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ ++ reg##block##id##_##reg_name ++ ++#define SRI2(reg_name, block, id) \ ++ .reg_name = BASE(reg##reg_name##_BASE_IDX) + \ ++ reg##reg_name ++#define SRI2_ARR(reg_name, block, id) \ ++ REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \ ++ reg##reg_name ++ ++#define SRIR(var_name, reg_name, block, id) \ ++ .var_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ ++ reg##block##id##_##reg_name ++ ++#define SRII(reg_name, block, id) \ ++ REG_STRUCT.reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ ++ reg##block##id##_##reg_name ++ ++#define SRII_ARR_2(reg_name, block, id, inst) \ ++ REG_STRUCT[inst].reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ ++ reg##block##id##_##reg_name ++ ++#define SRII_MPC_RMU(reg_name, block, id) \ ++ .RMU##_##reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ ++ reg##block##id##_##reg_name ++ ++#define SRII_DWB(reg_name, temp_name, block, id) \ ++ REG_STRUCT.reg_name[id] = \ ++ BASE(reg##block##id##_##temp_name##_BASE_IDX) + \ ++ reg##block##id##_##temp_name ++ ++#define DCCG_SRII(reg_name, block, id) \ ++ REG_STRUCT.block##_##reg_name[id] = \ ++ BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ ++ reg##block##id##_##reg_name ++ ++#define SF_DWB2(reg_name, block, id, field_name, post_fix) \ ++ .field_name = reg_name##__##field_name##post_fix ++ ++#define VUPDATE_SRII(reg_name, block, id) \ ++ REG_STRUCT.reg_name[id] = BASE(reg##reg_name##_##block##id##_BASE_IDX) + \ ++ reg##reg_name##_##block##id ++ ++/* NBIO */ ++#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] ++ ++#define NBIO_BASE(seg) \ ++ NBIO_BASE_INNER(seg) ++ ++#define NBIO_SR(reg_name) \ ++ REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_##reg_name##_BASE_IDX) + \ ++ regBIF_BX0_##reg_name ++#define NBIO_SR_ARR(reg_name, id) \ ++ REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_##reg_name##_BASE_IDX) + \ ++ regBIF_BX0_##reg_name ++ ++#define CTX ctx ++#define REG(reg_name) \ ++ (ctx->dcn_reg_offsets[reg##reg_name##_BASE_IDX] + reg##reg_name) ++ ++static struct bios_registers bios_regs; ++ ++#define bios_regs_init() \ ++ NBIO_SR(BIOS_SCRATCH_3), \ ++ NBIO_SR(BIOS_SCRATCH_6) ++ ++#define clk_src_regs_init(index, pllid) \ ++ CS_COMMON_REG_LIST_DCN42_RI(index, pllid) ++ ++static struct dce110_clk_src_regs clk_src_regs[5]; ++ ++static const struct dce110_clk_src_shift cs_shift = { ++ CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) ++}; ++static const struct dce110_clk_src_mask cs_mask = { ++ CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) ++}; ++#define abm_regs_init(id) \ ++ ABM_DCN42_REG_LIST_RI(id) ++ ++static struct dce_abm_registers abm_regs[4]; ++ ++static const struct dce_abm_shift abm_shift = { ++ ABM_MASK_SH_LIST_DCN42(__SHIFT)}; ++ ++static const struct dce_abm_mask abm_mask = { ++ ABM_MASK_SH_LIST_DCN42(_MASK)}; ++ ++#define audio_regs_init(id) \ ++ AUD_COMMON_REG_LIST_RI(id) ++ ++static struct dce_audio_registers audio_regs[5]; ++ ++static const struct dce_audio_shift audio_shift = { ++ DCN42_AUD_COMMON_MASK_SH_LIST(__SHIFT) ++}; ++ ++static const struct dce_audio_mask audio_mask = { ++ DCN42_AUD_COMMON_MASK_SH_LIST(_MASK) ++}; ++ ++#define vpg_regs_init(id) \ ++ VPG_DCN401_REG_LIST_RI(id) ++ ++static struct dcn31_vpg_registers vpg_regs[10]; ++ ++static const struct dcn31_vpg_shift vpg_shift = { ++ DCN31_VPG_MASK_SH_LIST(__SHIFT)}; ++ ++static const struct dcn31_vpg_mask vpg_mask = { ++ DCN31_VPG_MASK_SH_LIST(_MASK)}; ++ ++#define apg_regs_init(id) \ ++ APG_DCN31_REG_LIST_RI(id) ++ ++static struct dcn31_apg_registers apg_regs[10]; ++ ++static const struct dcn31_apg_shift apg_shift = { ++ DCN31_APG_MASK_SH_LIST(__SHIFT)}; ++ ++static const struct dcn31_apg_mask apg_mask = { ++ DCN31_APG_MASK_SH_LIST(_MASK)}; ++ ++#define stream_enc_regs_init(id) \ ++ SE_DCN42_REG_LIST_RI(id) ++ ++static struct dcn10_stream_enc_registers stream_enc_regs[5]; ++ ++static const struct dcn10_stream_encoder_shift se_shift = { ++ SE_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; ++ ++static const struct dcn10_stream_encoder_mask se_mask = { ++ SE_COMMON_MASK_SH_LIST_DCN42(_MASK)}; ++ ++#define aux_regs_init(id) \ ++ DCN2_AUX_REG_LIST_RI(id) ++ ++static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; ++ ++#define hpd_regs_init(id) \ ++ HPD_REG_LIST_RI(id) ++ ++static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; ++ ++#define link_regs_init(id, phyid) \ ++ LE_DCN401_REG_LIST_RI(id) ++ ++static struct dcn10_link_enc_registers link_enc_regs[5]; ++ ++static const struct dcn10_link_enc_shift le_shift = { ++ LINK_ENCODER_MASK_SH_LIST_DCN42(__SHIFT)}; ++ ++static const struct dcn10_link_enc_mask le_mask = { ++ LINK_ENCODER_MASK_SH_LIST_DCN42(_MASK)}; ++ ++#define hpo_dp_stream_encoder_reg_init(id) \ ++ DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id) ++ ++static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; ++ ++static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { ++ DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)}; ++ ++static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { ++ DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)}; ++ ++#define hpo_dp_link_encoder_reg_init(id) \ ++ DCN42_HPO_DP_LINK_ENC_REG_LIST_RI(id) ++ ++static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4]; ++ ++static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { ++ DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)}; ++ ++static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { ++ DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)}; ++ ++#define dpp_regs_init(id) \ ++ DPP_REG_LIST_DCN42_COMMON_RI(id) ++ ++static struct dcn42_dpp_registers dpp_regs[4]; ++ ++static const struct dcn42_dpp_shift tf_shift = { ++ DPP_REG_LIST_SH_MASK_DCN42_COMMON(__SHIFT)}; ++ ++static const struct dcn42_dpp_mask tf_mask = { ++ DPP_REG_LIST_SH_MASK_DCN42_COMMON(_MASK)}; ++ ++#define opp_regs_init(id) \ ++ OPP_REG_LIST_DCN401_RI(id) ++ ++static struct dcn20_opp_registers opp_regs[4]; ++ ++static const struct dcn20_opp_shift opp_shift = { ++ OPP_MASK_SH_LIST_DCN20(__SHIFT)}; ++ ++static const struct dcn20_opp_mask opp_mask = { ++ OPP_MASK_SH_LIST_DCN20(_MASK)}; ++ ++#define aux_engine_regs_init(id) \ ++ AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ ++ SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ ++ SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ ++ SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) ++ ++static struct dce110_aux_registers aux_engine_regs[5]; ++ ++static const struct dce110_aux_registers_shift aux_shift = { ++ DCN_AUX_MASK_SH_LIST(__SHIFT)}; ++ ++static const struct dce110_aux_registers_mask aux_mask = { ++ DCN_AUX_MASK_SH_LIST(_MASK)}; ++ ++#define dwbc_regs_dcn401_init(id) \ ++ DWBC_COMMON_REG_LIST_DCN30_RI(id) ++ ++static struct dcn30_dwbc_registers dwbc401_regs[1]; ++ ++static const struct dcn30_dwbc_shift dwbc401_shift = { ++ DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)}; ++ ++static const struct dcn30_dwbc_mask dwbc401_mask = { ++ DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)}; ++ ++#define mcif_wb_regs_dcn3_init(id) \ ++ MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id) ++ ++static struct dcn35_mmhubbub_registers mcif_wb35_regs[1]; ++ ++static const struct dcn35_mmhubbub_shift mcif_wb35_shift = { ++ MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)}; ++ ++static const struct dcn35_mmhubbub_mask mcif_wb35_mask = { ++ MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)}; ++ ++#define dsc_regs_init(id) \ ++ DSC_REG_LIST_DCN401_RI(id) ++ ++static struct dcn401_dsc_registers dsc_regs[4]; ++ ++static const struct dcn401_dsc_shift dsc_shift = { ++ DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)}; ++ ++static const struct dcn401_dsc_mask dsc_mask = { ++ DSC_REG_LIST_SH_MASK_DCN401(_MASK)}; ++ ++static struct dcn42_mpc_registers mpc_regs; ++ ++#define dcn_mpc_regs_init() \ ++ MPC_REG_LIST_DCN42(0), \ ++ MPC_REG_LIST_DCN42(1), \ ++ MPC_REG_LIST_DCN42(2), \ ++ MPC_REG_LIST_DCN42(3), \ ++ MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0), \ ++ MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1), \ ++ MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2), \ ++ MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3), \ ++ MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0), \ ++ MPC_RMCM_REG_LIST_DCN42(0), \ ++ MPC_RMCM_REG_LIST_DCN42(1) ++ ++static const struct dcn42_mpc_shift mpc_shift = { ++ MPC_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; ++ ++static const struct dcn42_mpc_mask mpc_mask = { ++ MPC_COMMON_MASK_SH_LIST_DCN42(_MASK)}; ++ ++#define optc_regs_init(id) \ ++ OPTC_COMMON_REG_LIST_DCN42_RI(id) ++ ++static struct dcn_optc_registers optc_regs[4]; ++ ++static const struct dcn_optc_shift optc_shift = { ++ OPTC_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; ++ ++static const struct dcn_optc_mask optc_mask = { ++ OPTC_COMMON_MASK_SH_LIST_DCN42(_MASK)}; ++ ++#define hubp_regs_init(id) \ ++ HUBP_REG_LIST_DCN42_RI(id) ++ ++static struct dcn_hubp2_registers hubp_regs[4]; ++ ++static const struct dcn_hubp2_shift hubp_shift = { ++ HUBP_MASK_SH_LIST_DCN42(__SHIFT)}; ++ ++static const struct dcn_hubp2_mask hubp_mask = { ++ HUBP_MASK_SH_LIST_DCN42(_MASK)}; ++ ++static struct dcn_hubbub_registers hubbub_reg; ++ ++#define hubbub_reg_init() \ ++ HUBBUB_REG_LIST_DCN42(0) ++ ++static const struct dcn_hubbub_shift hubbub_shift = { ++ HUBBUB_MASK_SH_LIST_DCN4_2(__SHIFT)}; ++ ++static const struct dcn_hubbub_mask hubbub_mask = { ++ HUBBUB_MASK_SH_LIST_DCN4_2(_MASK)}; ++ ++static struct dccg_registers dccg_regs; ++ ++#define dccg_regs_init() \ ++ DCCG_REG_LIST_DCN42_RI() ++ ++static const struct dccg_shift dccg_shift = { ++ DCCG_MASK_SH_LIST_DCN42(__SHIFT)}; ++ ++static const struct dccg_mask dccg_mask = { ++ DCCG_MASK_SH_LIST_DCN42(_MASK)}; ++ ++static struct pg_cntl_registers pg_cntl_regs; ++ ++#define pg_cntl_dcn42_regs_init() \ ++ PG_CNTL_REG_LIST_DCN42() ++ ++static const struct pg_cntl_shift pg_cntl_shift = { ++ PG_CNTL_MASK_SH_LIST_DCN42(__SHIFT) ++}; ++ ++static const struct pg_cntl_mask pg_cntl_mask = { ++ PG_CNTL_MASK_SH_LIST_DCN42(_MASK) ++}; ++#define SRII2(reg_name_pre, reg_name_post, id) \ ++ .reg_name_pre##_##reg_name_post[id] = \ ++ BASE(reg##reg_name_pre##id##_##reg_name_post##_BASE_IDX) + \ ++ reg##reg_name_pre##id##_##reg_name_post ++ ++#define HWSEQ_DCN42_REG_LIST() \ ++ SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ ++ SR(DIO_MEM_PWR_CTRL), \ ++ SR(ODM_MEM_PWR_CTRL3), \ ++ SR(MMHUBBUB_MEM_PWR_CNTL), \ ++ SR(DCCG_GATE_DISABLE_CNTL), \ ++ SR(DCCG_GATE_DISABLE_CNTL2), \ ++ SR(DCFCLK_CNTL), \ ++ SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ ++ SRII(PIXEL_RATE_CNTL, OTG, 0), \ ++ SRII(PIXEL_RATE_CNTL, OTG, 1), \ ++ SRII(PIXEL_RATE_CNTL, OTG, 2), \ ++ SRII(PIXEL_RATE_CNTL, OTG, 3),\ ++ SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0), \ ++ SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1), \ ++ SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2), \ ++ SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ ++ SR(MICROSECOND_TIME_BASE_DIV), \ ++ SR(MILLISECOND_TIME_BASE_DIV), \ ++ SR(DISPCLK_FREQ_CHANGE_CNTL), \ ++ SR(RBBMIF_TIMEOUT_DIS), \ ++ SR(RBBMIF_TIMEOUT_DIS_2), \ ++ SR(DCHUBBUB_CRC_CTRL), \ ++ SR(DPP_TOP0_DPP_CRC_CTRL), \ ++ SR(DPP_TOP0_DPP_CRC_VAL_R), \ ++ SR(DPP_TOP0_DPP_CRC_VAL_G), \ ++ SR(DPP_TOP0_DPP_CRC_VAL_B), \ ++ SR(MPC_CRC_CTRL), \ ++ SR(MPC_CRC_RESULT_R), \ ++ SR(MPC_CRC_RESULT_G), \ ++ SR(MPC_CRC_RESULT_B), \ ++ SR(MPC_CRC_RESULT_A), \ ++ SR(DOMAIN0_PG_CONFIG), \ ++ SR(DOMAIN1_PG_CONFIG), \ ++ SR(DOMAIN2_PG_CONFIG), \ ++ SR(DOMAIN3_PG_CONFIG), \ ++ SR(DOMAIN16_PG_CONFIG), \ ++ SR(DOMAIN17_PG_CONFIG), \ ++ SR(DOMAIN18_PG_CONFIG), \ ++ SR(DOMAIN19_PG_CONFIG), \ ++ SR(DOMAIN22_PG_CONFIG), \ ++ SR(DOMAIN23_PG_CONFIG), \ ++ SR(DOMAIN24_PG_CONFIG), \ ++ SR(DOMAIN25_PG_CONFIG), \ ++ SR(DOMAIN26_PG_CONFIG), \ ++ SR(DOMAIN0_PG_STATUS), \ ++ SR(DOMAIN1_PG_STATUS), \ ++ SR(DOMAIN2_PG_STATUS), \ ++ SR(DOMAIN3_PG_STATUS), \ ++ SR(DOMAIN16_PG_STATUS), \ ++ SR(DOMAIN17_PG_STATUS), \ ++ SR(DOMAIN18_PG_STATUS), \ ++ SR(DOMAIN19_PG_STATUS), \ ++ SR(DOMAIN22_PG_STATUS), \ ++ SR(DOMAIN23_PG_STATUS), \ ++ SR(DOMAIN24_PG_STATUS), \ ++ SR(DOMAIN25_PG_STATUS), \ ++ SR(DOMAIN26_PG_STATUS), \ ++ SR(DC_IP_REQUEST_CNTL), \ ++ SR(AZALIA_AUDIO_DTO), \ ++ SR(HPO_TOP_HW_CONTROL), \ ++ SR(AZALIA_CONTROLLER_CLOCK_GATING) ++ ++static struct dce_hwseq_registers hwseq_reg; ++ ++#define hwseq_reg_init() \ ++ HWSEQ_DCN42_REG_LIST() ++ ++#define HWSEQ_DCN42_MASK_SH_LIST(mask_sh) \ ++ HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ ++ HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ ++ HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ ++ HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ ++ HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ ++ HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DOMAIN26_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ ++ HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ ++ HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ ++ HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ ++ HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \ ++ HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ ++ HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ ++ HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ ++ HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\ ++ HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\ ++ HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\ ++ HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ ++ HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ ++ HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ ++ HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\ ++ HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ ++ HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\ ++ HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\ ++ HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK4_GATE_DISABLE, mask_sh),\ ++ HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK5_GATE_DISABLE, mask_sh) ++ ++static const struct dce_hwseq_shift hwseq_shift = { ++ HWSEQ_DCN42_MASK_SH_LIST(__SHIFT)}; ++ ++static const struct dce_hwseq_mask hwseq_mask = { ++ HWSEQ_DCN42_MASK_SH_LIST(_MASK)}; ++ ++#define vmid_regs_init(id) \ ++ DCN20_VMID_REG_LIST_RI(id) ++ ++static struct dcn_vmid_registers vmid_regs[16]; ++ ++static const struct dcn20_vmid_shift vmid_shifts = { ++ DCN20_VMID_MASK_SH_LIST(__SHIFT)}; ++ ++static const struct dcn20_vmid_mask vmid_masks = { ++ DCN20_VMID_MASK_SH_LIST(_MASK)}; ++ ++static const struct resource_caps res_cap_dcn42 = { ++ .num_timing_generator = 4, ++ .num_opp = 4, ++ .num_dpp = 4, ++ .num_video_plane = 4, ++ .num_audio = 5, ++ .num_stream_encoder = 5, ++ .num_dig_link_enc = 5, ++ .num_usb4_dpia = 6, ++ .num_hpo_dp_stream_encoder = 4, ++ .num_hpo_dp_link_encoder = 4, ++ .num_pll = 5, ++ .num_dwb = 1, ++ .num_ddc = 5, ++ .num_vmid = 16, ++ .num_mpc_3dlut = 2, ++ .num_dsc = 4, ++ .num_rmcm = 2, ++}; ++ ++static const struct dc_plane_cap plane_cap = { ++ .type = DC_PLANE_TYPE_DCN_UNIVERSAL, ++ .per_pixel_alpha = true, ++ ++ .pixel_format_support = { ++ .argb8888 = true, ++ .nv12 = true, ++ .fp16 = true, ++ .p010 = true, ++ .ayuv = false, ++ }, ++ ++ .max_upscale_factor = {.argb8888 = 16000, .nv12 = 16000, .fp16 = 16000}, ++ ++ // 6:1 downscaling ratio: 1000/6 = 166.666 ++ .max_downscale_factor = {.argb8888 = 167, .nv12 = 167, .fp16 = 167}, ++ ++ .min_width = 64, ++ .min_height = 64}; ++ ++static const struct dc_debug_options debug_defaults_drv = { ++ .disable_dmcu = true, ++ .force_abm_enable = false, ++ .clock_trace = true, ++ .disable_pplib_clock_request = false, ++ .disable_dpp_power_gate = true, ++ .disable_hubp_power_gate = true, ++ .disable_optc_power_gate = true, ++ .pipe_split_policy = MPC_SPLIT_AVOID, ++ .force_single_disp_pipe_split = false, ++ .disable_dcc = DCC_ENABLE, ++ .vsr_support = true, ++ .performance_trace = false, ++ .max_downscale_src_width = 4096, /*up to 4K for APU*/ ++ .disable_pplib_wm_range = false, ++ .scl_reset_length10 = true, ++ .sanity_checks = false, ++ .underflow_assert_delay_us = 0xFFFFFFFF, ++ .dwb_fi_phase = -1, // -1 = disable, ++ .dmub_command_table = true, ++ .pstate_enabled = true, ++ .enable_mem_low_power = { ++ .bits = { ++ .vga = false, ++ .i2c = true, ++ .dscl = true, ++ .cm = true, ++ .mpc = true, ++ .optc = true, ++ .vpg = true, ++ }}, ++ .root_clock_optimization = { ++ .bits = { ++ .dpp = true, ++ .dsc = true,/*dscclk and dsc pg*/ ++ .hdmistream = false, ++ .hdmichar = true, ++ .dpstream = true, ++ .symclk32_se = true, ++ .symclk32_le = true, ++ .symclk_fe = true, ++ .physymclk = false, ++ .dpiasymclk = true, ++ } ++ }, ++ .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT, ++ .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ ++ .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */ ++ .support_eDP1_5 = true, ++ .use_max_lb = true, ++ .force_disable_subvp = false, ++ .exit_idle_opt_for_cursor_updates = true, ++ .using_dml2 = true, ++ .using_dml21 = true, ++ .enable_single_display_2to1_odm_policy = true, ++ ++ // must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions ++ .enable_double_buffered_dsc_pg_support = true, ++ .enable_dp_dig_pixel_rate_div_policy = 1, ++ .allow_sw_cursor_fallback = false, ++ .psp_disabled_wa = true, ++ .alloc_extra_way_for_cursor = true, ++ .min_prefetch_in_strobe_ns = 60000, // 60us ++ .disable_unbounded_requesting = false, ++ .dcc_meta_propagation_delay_us = 10, ++ .disable_timeout = true, ++ .min_disp_clk_khz = 50000, ++ .static_screen_wait_frames = 2, ++ .disable_z10 = false, ++ .ignore_pg = true, ++ .disable_stutter_for_wm_program = true, ++ .min_deep_sleep_dcfclk_khz = 8000, ++ .replay_skip_crtc_disabled = true, ++ .psr_skip_crtc_disable = true, ++}; ++ ++static const struct dc_check_config config_defaults = { ++ .enable_legacy_fast_update = false, ++}; ++ ++static struct dce_aux *dcn42_aux_engine_create( ++ struct dc_context *ctx, ++ uint32_t inst) ++{ ++ struct aux_engine_dce110 *aux_engine = ++ kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); ++ ++ if (!aux_engine) ++ return NULL; ++ ++#undef REG_STRUCT ++#define REG_STRUCT aux_engine_regs ++ aux_engine_regs_init(0), ++ aux_engine_regs_init(1), ++ aux_engine_regs_init(2), ++ aux_engine_regs_init(3), ++ aux_engine_regs_init(4); ++ ++ dce110_aux_engine_construct(aux_engine, ctx, inst, ++ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, ++ &aux_engine_regs[inst], ++ &aux_mask, ++ &aux_shift, ++ ctx->dc->caps.extended_aux_timeout_support); ++ ++ return &aux_engine->base; ++} ++ ++#define i2c_inst_regs_init(id) \ ++ I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) ++ ++static struct dce_i2c_registers i2c_hw_regs[5]; ++ ++static const struct dce_i2c_shift i2c_shifts = { ++ I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT) ++}; ++static const struct dce_i2c_mask i2c_masks = { ++ I2C_COMMON_MASK_SH_LIST_DCN35(_MASK) ++}; ++ ++/* ========================================================== */ ++ ++/* ++ * DPIA index | Preferred Encoder | Host Router ++ * 0 | C | 0 ++ * 1 | First Available | 0 ++ * 2 | D | 1 ++ * 3 | First Available | 1 ++ * 4 | E | 2 ++ * 5 | First Available | 2 ++ */ ++/* ========================================================== */ ++static const enum engine_id dpia_to_preferred_enc_id_table[] = { ++ ENGINE_ID_DIGC, ++ ENGINE_ID_DIGC, ++ ENGINE_ID_DIGD, ++ ENGINE_ID_DIGD, ++ ENGINE_ID_DIGE, ++ ENGINE_ID_DIGE ++}; ++ ++static enum engine_id dcn42_get_preferred_eng_id_dpia(unsigned int dpia_index) ++{ ++ return dpia_to_preferred_enc_id_table[dpia_index]; ++} ++ ++static struct dce_i2c_hw *dcn42_i2c_hw_create( ++ struct dc_context *ctx, ++ uint32_t inst) ++{ ++ struct dce_i2c_hw *dce_i2c_hw = ++ kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); ++ ++ if (!dce_i2c_hw) ++ return NULL; ++ ++#undef REG_STRUCT ++#define REG_STRUCT i2c_hw_regs ++ i2c_inst_regs_init(1), ++ i2c_inst_regs_init(2), ++ i2c_inst_regs_init(3), ++ i2c_inst_regs_init(4), ++ i2c_inst_regs_init(5); ++ dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, ++ &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); ++ ++ return dce_i2c_hw; ++} ++ ++static struct clock_source *dcn42_clock_source_create( ++ struct dc_context *ctx, ++ struct dc_bios *bios, ++ enum clock_source_id id, ++ const struct dce110_clk_src_regs *regs, ++ bool dp_clk_src) ++{ ++ struct dce110_clk_src *clk_src = ++ kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); ++ ++ if (!clk_src) ++ return NULL; ++ ++ if (dcn401_clk_src_construct(clk_src, ctx, bios, id, ++ regs, &cs_shift, &cs_mask)) { ++ clk_src->base.dp_clk_src = dp_clk_src; ++ return &clk_src->base; ++ } ++ ++ kfree(clk_src); ++ BREAK_TO_DEBUGGER(); ++ return NULL; ++} ++ ++static struct hubbub *dcn42_hubbub_create(struct dc_context *ctx) ++{ ++ int i; ++ ++ struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), ++ GFP_KERNEL); ++ ++ if (!hubbub3) ++ return NULL; ++ ++#undef REG_STRUCT ++#define REG_STRUCT hubbub_reg ++ hubbub_reg_init(); ++ ++#undef REG_STRUCT ++#define REG_STRUCT vmid_regs ++ vmid_regs_init(0), ++ vmid_regs_init(1), ++ vmid_regs_init(2), ++ vmid_regs_init(3), ++ vmid_regs_init(4), ++ vmid_regs_init(5), ++ vmid_regs_init(6), ++ vmid_regs_init(7), ++ vmid_regs_init(8), ++ vmid_regs_init(9), ++ vmid_regs_init(10), ++ vmid_regs_init(11), ++ vmid_regs_init(12), ++ vmid_regs_init(13), ++ vmid_regs_init(14), ++ vmid_regs_init(15); ++ ++ hubbub42_construct(hubbub3, ctx, ++ &hubbub_reg, ++ &hubbub_shift, ++ &hubbub_mask, ++ DCN42_DEFAULT_DET_SIZE, ++ 8, ++ DCN42_CRB_SIZE_KB); ++ for (i = 0; i < res_cap_dcn42.num_vmid; i++) { ++ struct dcn20_vmid *vmid = &hubbub3->vmid[i]; ++ ++ vmid->ctx = ctx; ++ ++ vmid->regs = &vmid_regs[i]; ++ vmid->shifts = &vmid_shifts; ++ vmid->masks = &vmid_masks; ++ } ++ ++ return &hubbub3->base; ++} ++ ++static struct hubp *dcn42_hubp_create( ++ struct dc_context *ctx, ++ uint32_t inst) ++{ ++ struct dcn20_hubp *hubp2 = ++ kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); ++ ++ if (!hubp2) ++ return NULL; ++ ++#undef REG_STRUCT ++#define REG_STRUCT hubp_regs ++ hubp_regs_init(0), ++ hubp_regs_init(1), ++ hubp_regs_init(2), ++ hubp_regs_init(3); ++ ++ if (hubp42_construct(hubp2, ctx, inst, ++ &hubp_regs[inst], &hubp_shift, &hubp_mask)) ++ return &hubp2->base; ++ ++ BREAK_TO_DEBUGGER(); ++ kfree(hubp2); ++ return NULL; ++} ++static const struct dc_panel_config dcn42_panel_config_defaults = { ++ .psr = { ++ .disable_psr = false, ++ .disallow_psrsu = false, ++ .disallow_replay = false, ++ }, ++ .ilr = { ++ .optimize_edp_link_rate = true, ++ }, ++}; ++ ++static void dcn42_dpp_destroy(struct dpp **dpp) ++{ ++ kfree(TO_DCN42_DPP(*dpp)); ++ *dpp = NULL; ++} ++ ++static struct dpp *dcn42_dpp_create( ++ struct dc_context *ctx, ++ uint32_t inst) ++{ ++ struct dcn42_dpp *dpp42 = ++ kzalloc(sizeof(struct dcn42_dpp), GFP_KERNEL); ++ ++ if (!dpp42) ++ return NULL; ++ ++#undef REG_STRUCT ++#define REG_STRUCT dpp_regs ++ dpp_regs_init(0), ++ dpp_regs_init(1), ++ dpp_regs_init(2), ++ dpp_regs_init(3); ++ ++ if (dpp42_construct(dpp42, ctx, inst, ++ &dpp_regs[inst], &tf_shift, &tf_mask)) ++ return &dpp42->base; ++ ++ BREAK_TO_DEBUGGER(); ++ kfree(dpp42); ++ return NULL; ++} ++ ++static struct mpc *dcn42_mpc_create( ++ struct dc_context *ctx, ++ int num_mpcc, ++ int num_rmu) ++{ ++ struct dcn42_mpc *mpc401 = kzalloc(sizeof(struct dcn42_mpc), ++ GFP_KERNEL); ++ ++ if (!mpc401) ++ return NULL; ++ ++#undef REG_STRUCT ++#define REG_STRUCT mpc_regs ++ dcn_mpc_regs_init(); ++ ++ dcn42_mpc_construct(mpc401, ctx, ++ &mpc_regs, ++ &mpc_shift, ++ &mpc_mask, ++ num_mpcc, ++ num_rmu); ++ ++ return &mpc401->base; ++} ++ ++static struct output_pixel_processor *dcn42_opp_create( ++ struct dc_context *ctx, uint32_t inst) ++{ ++ struct dcn20_opp *opp4 = ++ kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); ++ ++ if (!opp4) { ++ BREAK_TO_DEBUGGER(); ++ return NULL; ++ } ++ ++#undef REG_STRUCT ++#define REG_STRUCT opp_regs ++ opp_regs_init(0), ++ opp_regs_init(1), ++ opp_regs_init(2), ++ opp_regs_init(3); ++ dcn20_opp_construct(opp4, ctx, inst, ++ &opp_regs[inst], &opp_shift, &opp_mask); ++ return &opp4->base; ++} ++ ++static struct timing_generator *dcn42_timing_generator_create( ++ struct dc_context *ctx, ++ uint32_t instance) ++{ ++ struct optc *tgn10 = ++ kzalloc(sizeof(struct optc), GFP_KERNEL); ++ ++ if (!tgn10) ++ return NULL; ++#undef REG_STRUCT ++#define REG_STRUCT optc_regs ++ optc_regs_init(0), ++ optc_regs_init(1), ++ optc_regs_init(2), ++ optc_regs_init(3); ++ tgn10->base.inst = instance; ++ tgn10->base.ctx = ctx; ++ ++ tgn10->tg_regs = &optc_regs[instance]; ++ tgn10->tg_shift = &optc_shift; ++ tgn10->tg_mask = &optc_mask; ++ ++ dcn42_timing_generator_init(tgn10); ++ ++ return &tgn10->base; ++} ++ ++static const struct encoder_feature_support link_enc_feature = { ++ .max_hdmi_deep_color = COLOR_DEPTH_121212, ++ .max_hdmi_pixel_clock = 600000, ++ .hdmi_ycbcr420_supported = true, ++ .dp_ycbcr420_supported = true, ++ .fec_supported = true, ++ .flags.bits.IS_HBR2_CAPABLE = true, ++ .flags.bits.IS_HBR3_CAPABLE = true, ++ .flags.bits.IS_TPS3_CAPABLE = true, ++ .flags.bits.IS_TPS4_CAPABLE = true}; ++ ++static struct link_encoder *dcn42_link_encoder_create( ++ struct dc_context *ctx, ++ const struct encoder_init_data *enc_init_data) ++{ ++ struct dcn20_link_encoder *enc20 = ++ kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); ++ ++ if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) ++ return NULL; ++ ++#undef REG_STRUCT ++#define REG_STRUCT link_enc_aux_regs ++ aux_regs_init(0), ++ aux_regs_init(1), ++ aux_regs_init(2), ++ aux_regs_init(3), ++ aux_regs_init(4); ++#undef REG_STRUCT ++#define REG_STRUCT link_enc_hpd_regs ++ hpd_regs_init(0), ++ hpd_regs_init(1), ++ hpd_regs_init(2), ++ hpd_regs_init(3), ++ hpd_regs_init(4); ++#undef REG_STRUCT ++#define REG_STRUCT link_enc_regs ++ link_regs_init(0, A), ++ link_regs_init(1, B), ++ link_regs_init(2, C), ++ link_regs_init(3, D), ++ link_regs_init(4, E); ++ ++ dcn42_link_encoder_construct(enc20, ++ enc_init_data, ++ &link_enc_feature, ++ &link_enc_regs[enc_init_data->transmitter], ++ &link_enc_aux_regs[enc_init_data->channel - 1], ++ &link_enc_hpd_regs[enc_init_data->hpd_source], ++ &le_shift, ++ &le_mask); ++ return &enc20->enc10.base; ++} ++ ++static void read_dce_straps( ++ struct dc_context *ctx, ++ struct resource_straps *straps) ++{ ++ generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), ++ FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); ++} ++ ++static struct audio *dcn42_create_audio( ++ struct dc_context *ctx, unsigned int inst) ++{ ++ ++#undef REG_STRUCT ++#define REG_STRUCT audio_regs ++ audio_regs_init(0), ++ audio_regs_init(1), ++ audio_regs_init(2), ++ audio_regs_init(3), ++ audio_regs_init(4); ++ ++ return dce_audio_create(ctx, inst, ++ &audio_regs[inst], &audio_shift, &audio_mask); ++} ++ ++static struct vpg *dcn42_vpg_create( ++ struct dc_context *ctx, ++ uint32_t inst) ++{ ++ struct dcn31_vpg *vpg4 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); ++ ++ if (!vpg4) ++ return NULL; ++ ++#undef REG_STRUCT ++#define REG_STRUCT vpg_regs ++ vpg_regs_init(0), ++ vpg_regs_init(1), ++ vpg_regs_init(2), ++ vpg_regs_init(3), ++ vpg_regs_init(4), ++ vpg_regs_init(5), ++ vpg_regs_init(6), ++ vpg_regs_init(7), ++ vpg_regs_init(8), ++ vpg_regs_init(9); ++ vpg31_construct(vpg4, ctx, inst, ++ &vpg_regs[inst], ++ &vpg_shift, ++ &vpg_mask); ++ ++ return &vpg4->base; ++} ++ ++static struct apg *dcn42_apg_create( ++ struct dc_context *ctx, ++ uint32_t inst) ++{ ++ struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); ++ ++ if (!apg31) ++ return NULL; ++ ++#undef REG_STRUCT ++#define REG_STRUCT apg_regs ++ apg_regs_init(0), ++ apg_regs_init(1), ++ apg_regs_init(2), ++ apg_regs_init(3), ++ apg_regs_init(4), ++ apg_regs_init(5), ++ apg_regs_init(6), ++ apg_regs_init(7), ++ apg_regs_init(8), ++ apg_regs_init(9); ++ ++ apg31_construct(apg31, ctx, inst, ++ &apg_regs[inst], ++ &apg_shift, ++ &apg_mask); ++ ++ return &apg31->base; ++} ++ ++static struct stream_encoder *dcn42_stream_encoder_create( ++ enum engine_id eng_id, ++ struct dc_context *ctx) ++{ ++ struct dcn10_stream_encoder *enc1; ++ struct vpg *vpg; ++ struct apg *apg; ++ ++ uint32_t vpg_inst; ++ uint32_t apg_inst; ++ ++ /* Mapping of VPG, DME register blocks to DIO block instance */ ++ if (eng_id <= ENGINE_ID_DIGE) { ++ vpg_inst = eng_id; ++ apg_inst = eng_id; ++ } else ++ return NULL; ++ ++ enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); ++ vpg = dcn42_vpg_create(ctx, vpg_inst); ++ apg = dcn42_apg_create(ctx, apg_inst); ++ ++ if (!enc1 || !vpg || !apg) { ++ kfree(enc1); ++ kfree(vpg); ++ kfree(apg); ++ return NULL; ++ } ++#undef REG_STRUCT ++#define REG_STRUCT stream_enc_regs ++ stream_enc_regs_init(0), ++ stream_enc_regs_init(1), ++ stream_enc_regs_init(2), ++ stream_enc_regs_init(3), ++ stream_enc_regs_init(4); ++ ++ dcn42_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, ++ eng_id, vpg, apg, ++ &stream_enc_regs[eng_id], ++ &se_shift, &se_mask); ++ return &enc1->base; ++} ++ ++static struct hpo_dp_stream_encoder *dcn42_hpo_dp_stream_encoder_create( ++ enum engine_id eng_id, ++ struct dc_context *ctx) ++{ ++ struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; ++ struct vpg *vpg; ++ struct apg *apg; ++ uint32_t hpo_dp_inst; ++ uint32_t vpg_inst; ++ uint32_t apg_inst; ++ ++ ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); ++ hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; ++ ++ /* Mapping of VPG register blocks to HPO DP block instance: ++ * VPG[5] -> HPO_DP[0] ++ * VPG[6] -> HPO_DP[1] ++ * VPG[7] -> HPO_DP[2] ++ * VPG[8] -> HPO_DP[3] ++ */ ++ vpg_inst = hpo_dp_inst + 5; ++ ++ /* Mapping of APG register blocks to HPO DP block instance: ++ * APG[6] -> HPO_DP[0] ++ * APG[7] -> HPO_DP[1] ++ * APG[8] -> HPO_DP[2] ++ * APG[9] -> HPO_DP[3] ++ */ ++ apg_inst = hpo_dp_inst + 5; ++ ++ /* allocate HPO stream encoder and create VPG sub-block */ ++ hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); ++ vpg = dcn42_vpg_create(ctx, vpg_inst); ++ apg = dcn42_apg_create(ctx, apg_inst); ++ ++ if (!hpo_dp_enc31 || !vpg || !apg) { ++ kfree(hpo_dp_enc31); ++ kfree(vpg); ++ kfree(apg); ++ return NULL; ++ } ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_dp_stream_enc_regs ++ hpo_dp_stream_encoder_reg_init(0), ++ hpo_dp_stream_encoder_reg_init(1), ++ hpo_dp_stream_encoder_reg_init(2), ++ hpo_dp_stream_encoder_reg_init(3); ++ ++ dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, ++ hpo_dp_inst, eng_id, vpg, apg, ++ &hpo_dp_stream_enc_regs[hpo_dp_inst], ++ &hpo_dp_se_shift, &hpo_dp_se_mask); ++ ++ return &hpo_dp_enc31->base; ++} ++ ++static struct hpo_dp_link_encoder *dcn42_hpo_dp_link_encoder_create( ++ uint8_t inst, ++ struct dc_context *ctx) ++{ ++ struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; ++ ++ /* allocate HPO link encoder */ ++ hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); ++ if (!hpo_dp_enc31) ++ return NULL; /* out of memory */ ++ ++#undef REG_STRUCT ++#define REG_STRUCT hpo_dp_link_enc_regs ++ hpo_dp_link_encoder_reg_init(0), ++ hpo_dp_link_encoder_reg_init(1), ++ hpo_dp_link_encoder_reg_init(2), ++ hpo_dp_link_encoder_reg_init(3); ++ ++ hpo_dp_link_encoder42_construct(hpo_dp_enc31, ctx, inst, ++ &hpo_dp_link_enc_regs[inst], ++ &hpo_dp_le_shift, &hpo_dp_le_mask); ++ ++ return &hpo_dp_enc31->base; ++} ++ ++static struct dce_hwseq *dcn42_hwseq_create( ++ struct dc_context *ctx) ++{ ++ struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); ++ ++#undef REG_STRUCT ++#define REG_STRUCT hwseq_reg ++ hwseq_reg_init(); ++ ++ if (hws) { ++ hws->ctx = ctx; ++ hws->regs = &hwseq_reg; ++ hws->shifts = &hwseq_shift; ++ hws->masks = &hwseq_mask; ++ } ++ ++ return hws; ++} ++ ++static const struct resource_create_funcs res_create_funcs = { ++ .read_dce_straps = read_dce_straps, ++ .create_audio = dcn42_create_audio, ++ .create_stream_encoder = dcn42_stream_encoder_create, ++ .create_hpo_dp_stream_encoder = dcn42_hpo_dp_stream_encoder_create, ++ .create_hpo_dp_link_encoder = dcn42_hpo_dp_link_encoder_create, ++ .create_hwseq = dcn42_hwseq_create, ++}; ++ ++static void dcn42_dsc_destroy(struct display_stream_compressor **dsc) ++{ ++ kfree(container_of(*dsc, struct dcn401_dsc, base)); ++ *dsc = NULL; ++} ++ ++static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < pool->base.stream_enc_count; i++) { ++ if (pool->base.stream_enc[i] != NULL) { ++ if (pool->base.stream_enc[i]->vpg != NULL) { ++ kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); ++ pool->base.stream_enc[i]->vpg = NULL; ++ } ++ if (pool->base.stream_enc[i]->apg != NULL) { ++ kfree(DCN31_APG_FROM_APG(pool->base.stream_enc[i]->apg)); ++ pool->base.stream_enc[i]->apg = NULL; ++ } ++ kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); ++ pool->base.stream_enc[i] = NULL; ++ } ++ } ++ ++ for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { ++ if (pool->base.hpo_dp_stream_enc[i] != NULL) { ++ if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { ++ kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); ++ pool->base.hpo_dp_stream_enc[i]->vpg = NULL; ++ } ++ if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { ++ kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); ++ pool->base.hpo_dp_stream_enc[i]->apg = NULL; ++ } ++ kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); ++ pool->base.hpo_dp_stream_enc[i] = NULL; ++ } ++ } ++ ++ for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { ++ if (pool->base.hpo_dp_link_enc[i] != NULL) { ++ kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); ++ pool->base.hpo_dp_link_enc[i] = NULL; ++ } ++ } ++ ++ for (i = 0; i < pool->base.res_cap->num_dsc; i++) { ++ if (pool->base.dscs[i] != NULL) ++ dcn42_dsc_destroy(&pool->base.dscs[i]); ++ } ++ ++ if (pool->base.mpc != NULL) { ++ kfree(TO_DCN20_MPC(pool->base.mpc)); ++ pool->base.mpc = NULL; ++ } ++ if (pool->base.hubbub != NULL) { ++ kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); ++ pool->base.hubbub = NULL; ++ } ++ for (i = 0; i < pool->base.pipe_count; i++) { ++ if (pool->base.dpps[i] != NULL) ++ dcn42_dpp_destroy(&pool->base.dpps[i]); ++ ++ if (pool->base.ipps[i] != NULL) ++ pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); ++ ++ if (pool->base.hubps[i] != NULL) { ++ kfree(TO_DCN20_HUBP(pool->base.hubps[i])); ++ pool->base.hubps[i] = NULL; ++ } ++ ++ if (pool->base.irqs != NULL) ++ dal_irq_service_destroy(&pool->base.irqs); ++ } ++ ++ for (i = 0; i < pool->base.res_cap->num_ddc; i++) { ++ if (pool->base.engines[i] != NULL) ++ dce110_engine_destroy(&pool->base.engines[i]); ++ if (pool->base.hw_i2cs[i] != NULL) { ++ kfree(pool->base.hw_i2cs[i]); ++ pool->base.hw_i2cs[i] = NULL; ++ } ++ if (pool->base.sw_i2cs[i] != NULL) { ++ kfree(pool->base.sw_i2cs[i]); ++ pool->base.sw_i2cs[i] = NULL; ++ } ++ } ++ ++ for (i = 0; i < pool->base.res_cap->num_opp; i++) { ++ if (pool->base.opps[i] != NULL) ++ pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); ++ } ++ ++ for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { ++ if (pool->base.timing_generators[i] != NULL) { ++ kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); ++ pool->base.timing_generators[i] = NULL; ++ } ++ } ++ ++ for (i = 0; i < pool->base.res_cap->num_dwb; i++) { ++ if (pool->base.dwbc[i] != NULL) { ++ kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); ++ pool->base.dwbc[i] = NULL; ++ } ++ if (pool->base.mcif_wb[i] != NULL) { ++ kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); ++ pool->base.mcif_wb[i] = NULL; ++ } ++ } ++ ++ for (i = 0; i < pool->base.audio_count; i++) { ++ if (pool->base.audios[i]) ++ dce_aud_destroy(&pool->base.audios[i]); ++ } ++ ++ for (i = 0; i < pool->base.clk_src_count; i++) { ++ if (pool->base.clock_sources[i] != NULL) { ++ dcn20_clock_source_destroy(&pool->base.clock_sources[i]); ++ pool->base.clock_sources[i] = NULL; ++ } ++ } ++ ++ for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { ++ if (pool->base.mpc_lut[i] != NULL) { ++ dc_3dlut_func_release(pool->base.mpc_lut[i]); ++ pool->base.mpc_lut[i] = NULL; ++ } ++ if (pool->base.mpc_shaper[i] != NULL) { ++ dc_transfer_func_release(pool->base.mpc_shaper[i]); ++ pool->base.mpc_shaper[i] = NULL; ++ } ++ } ++ ++ if (pool->base.dp_clock_source != NULL) { ++ dcn20_clock_source_destroy(&pool->base.dp_clock_source); ++ pool->base.dp_clock_source = NULL; ++ } ++ ++ for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { ++ if (pool->base.multiple_abms[i] != NULL) ++ dce_abm_destroy(&pool->base.multiple_abms[i]); ++ } ++ ++ if (pool->base.psr != NULL) ++ dmub_psr_destroy(&pool->base.psr); ++ ++ if (pool->base.pg_cntl != NULL) ++ dcn_pg_cntl_destroy(&pool->base.pg_cntl); ++ if (pool->base.dccg != NULL) ++ dcn_dccg_destroy(&pool->base.dccg); ++ ++ if (pool->base.oem_device != NULL) { ++ struct dc *dc = pool->base.oem_device->ctx->dc; ++ ++ dc->link_srv->destroy_ddc_service(&pool->base.oem_device); ++ } ++} ++ ++static void dcn42_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) ++{ ++ const struct dc_stream_state *stream = pipe_ctx->stream; ++ struct dc_link *link = stream->link; ++ struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; ++ struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params; ++ ++ pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; ++ ++ if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) ++ pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz; ++ ++ if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) ++ link_enc = link_enc_cfg_get_link_enc(link); ++ if (link_enc) ++ pixel_clk_params->encoder_object_id = link_enc->id; ++ ++ pixel_clk_params->signal_type = pipe_ctx->stream->signal; ++ pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; ++ /* TODO: un-hardcode*/ ++ ++ /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */ ++ ++ pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * ++ LINK_RATE_REF_FREQ_IN_KHZ; ++ pixel_clk_params->flags.ENABLE_SS = 0; ++ pixel_clk_params->color_depth = ++ stream->timing.display_color_depth; ++ pixel_clk_params->flags.DISPLAY_BLANKED = 1; ++ pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; ++ ++ if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) ++ pixel_clk_params->color_depth = COLOR_DEPTH_888; ++ ++ if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) ++ pixel_clk_params->requested_pix_clk_100hz *= 2; ++ if (dc_is_tmds_signal(stream->signal) && ++ stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) ++ pixel_clk_params->requested_pix_clk_100hz /= 2; ++ ++ pipe_ctx->clock_source->funcs->get_pix_clk_dividers( ++ pipe_ctx->clock_source, ++ &pipe_ctx->stream_res.pix_clk_params, ++ &pipe_ctx->pll_settings); ++ ++ pixel_clk_params->dio_se_pix_per_cycle = 1; ++ if (dc_is_tmds_signal(stream->signal) && ++ stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { ++ pixel_clk_params->dio_se_pix_per_cycle = 2; ++ } else if (dc_is_dp_signal(stream->signal)) { ++ /* round up to nearest power of 2, or max at 8 pixels per cycle */ ++ if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { ++ pixel_clk_params->dio_se_pix_per_cycle = 8; ++ } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { ++ pixel_clk_params->dio_se_pix_per_cycle = 4; ++ } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { ++ pixel_clk_params->dio_se_pix_per_cycle = 2; ++ } else { ++ pixel_clk_params->dio_se_pix_per_cycle = 1; ++ } ++ } ++} ++ ++static bool dcn42_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) ++{ ++ int i; ++ uint32_t dwb_count = pool->res_cap->num_dwb; ++ ++ for (i = 0; i < dwb_count; i++) { ++ struct dcn30_dwbc *dwbc42 = kzalloc(sizeof(struct dcn30_dwbc), ++ GFP_KERNEL); ++ ++ if (!dwbc42) { ++ dm_error("DC: failed to create dwbc42!\n"); ++ return false; ++ } ++ ++#undef REG_STRUCT ++#define REG_STRUCT dwbc401_regs ++ dwbc_regs_dcn401_init(0); ++ ++ dcn30_dwbc_construct(dwbc42, ctx, ++ &dwbc401_regs[i], ++ &dwbc401_shift, ++ &dwbc401_mask, ++ i); ++ ++ pool->dwbc[i] = &dwbc42->base; ++ } ++ return true; ++} ++ ++static void dcn42_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, ++ struct dc_context *ctx) ++{ ++ dcn42_mmhubbub_set_fgcg( ++ mcif_wb30, ++ ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub); ++} ++ ++static bool dcn42_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) ++{ ++ int i; ++ uint32_t pipe_count = pool->res_cap->num_dwb; ++ ++ for (i = 0; i < pipe_count; i++) { ++ struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), ++ GFP_KERNEL); ++ ++ if (!mcif_wb30) { ++ dm_error("DC: failed to create mcif_wb30!\n"); ++ return false; ++ } ++ ++#undef REG_STRUCT ++#define REG_STRUCT mcif_wb35_regs ++ mcif_wb_regs_dcn3_init(0); ++ ++ dcn35_mmhubbub_construct(mcif_wb30, ctx, ++ &mcif_wb35_regs[i], ++ &mcif_wb35_shift, ++ &mcif_wb35_mask, ++ i); ++ ++ dcn42_mmhubbub_init(mcif_wb30, ctx); ++ ++ pool->mcif_wb[i] = &mcif_wb30->base; ++ } ++ return true; ++} ++ ++static struct display_stream_compressor *dcn42_dsc_create( ++ struct dc_context *ctx, uint32_t inst) ++{ ++ struct dcn401_dsc *dsc = ++ kzalloc(sizeof(struct dcn401_dsc), GFP_KERNEL); ++ ++ if (!dsc) { ++ BREAK_TO_DEBUGGER(); ++ return NULL; ++ } ++ ++#undef REG_STRUCT ++#define REG_STRUCT dsc_regs ++ dsc_regs_init(0), ++ dsc_regs_init(1), ++ dsc_regs_init(2), ++ dsc_regs_init(3); ++ ++ dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); ++ dsc401_set_fgcg(dsc, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc); ++ ++ dsc->max_image_width = 5760; ++ ++ return &dsc->base; ++} ++ ++static void dcn42_destroy_resource_pool(struct resource_pool **pool) ++{ ++ struct dcn42_resource_pool *dcn42_pool = TO_DCN42_RES_POOL(*pool); ++ ++ dcn42_resource_destruct(dcn42_pool); ++ kfree(dcn42_pool); ++ *pool = NULL; ++} ++ ++static struct dc_cap_funcs cap_funcs = { ++ .get_dcc_compression_cap = dcn20_get_dcc_compression_cap}; ++ ++static void dcn42_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) ++{ ++ dc_assert_fp_enabled(); ++ ++ if (dc->current_state && dc->current_state->bw_ctx.dml2) ++ dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); ++} ++ ++static void dcn42_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++{ ++ DC_FP_START(); ++ dcn42_update_bw_bounding_box_fpu(dc, bw_params); ++ DC_FP_END(); ++} ++enum dc_status dcn42_validate_bandwidth(struct dc *dc, ++ struct dc_state *context, ++ enum dc_validate_mode validate_mode) ++{ ++ bool out = false; ++ ++ DC_FP_START(); ++ ++ out = dml2_validate(dc, context, context->bw_ctx.dml2, ++ validate_mode); ++ ++ if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) { ++ /*not required for mode enumeration*/ ++ dcn42_decide_zstate_support(dc, context); ++ } ++ ++ DC_FP_END(); ++ ++ return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; ++} ++void dcn42_prepare_mcache_programming(struct dc *dc, ++ struct dc_state *context) ++{ ++ if (dc->debug.using_dml21) { ++ DC_FP_START(); ++ dml2_prepare_mcache_programming(dc, context, ++ context->power_source == DC_POWER_SOURCE_DC ? ++ context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); ++ DC_FP_END(); ++ } ++} ++/* Create a minimal link encoder object not associated with a particular ++ * physical connector. ++ * resource_funcs.link_enc_create_minimal ++ */ ++static struct link_encoder *dcn42_link_enc_create_minimal( ++ struct dc_context *ctx, enum engine_id eng_id) ++{ ++ struct dcn20_link_encoder *enc20; ++ ++ if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) ++ return NULL; ++ ++ enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); ++ if (!enc20) ++ return NULL; ++ ++ dcn31_link_encoder_construct_minimal( ++ enc20, ++ ctx, ++ &link_enc_feature, ++ &link_enc_regs[eng_id - ENGINE_ID_DIGA], ++ eng_id); ++ ++ return &enc20->enc10.base; ++} ++static void dcn42_get_panel_config_defaults(struct dc_panel_config *panel_config) ++{ ++ *panel_config = dcn42_panel_config_defaults; ++} ++static unsigned int dcn42_get_max_hw_cursor_size(const struct dc *dc, ++ struct dc_state *state, ++ const struct dc_stream_state *stream) ++{ ++ return dc->caps.max_cursor_size; ++} ++static struct resource_funcs dcn42_res_pool_funcs = { ++ .destroy = dcn42_destroy_resource_pool, ++ .link_enc_create = dcn42_link_encoder_create, ++ .link_enc_create_minimal = dcn42_link_enc_create_minimal, ++ .link_encs_assign = link_enc_cfg_link_encs_assign, ++ .link_enc_unassign = link_enc_cfg_link_enc_unassign, ++ .panel_cntl_create = dcn32_panel_cntl_create, ++ .validate_bandwidth = dcn42_validate_bandwidth, ++ .calculate_wm_and_dlg = NULL, ++ .populate_dml_pipes = NULL, ++ .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe, ++ .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, ++ .release_pipe = dcn20_release_pipe, ++ .add_stream_to_ctx = dcn30_add_stream_to_ctx, ++ .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, ++ .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, ++ .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, ++ .set_mcif_arb_params = dcn30_set_mcif_arb_params, ++ .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, ++ .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, ++ .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, ++ .update_bw_bounding_box = dcn42_update_bw_bounding_box, ++ .patch_unknown_plane_state = dcn35_patch_unknown_plane_state, ++ .get_panel_config_defaults = dcn42_get_panel_config_defaults, ++ .get_preferred_eng_id_dpia = dcn42_get_preferred_eng_id_dpia, ++ .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, ++ .add_phantom_pipes = dcn32_add_phantom_pipes, ++ .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, ++ .prepare_mcache_programming = dcn42_prepare_mcache_programming, ++ .build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params, ++ .get_power_profile = dcn401_get_power_profile, ++ .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe, ++ .get_max_hw_cursor_size = dcn42_get_max_hw_cursor_size, ++ .get_default_tiling_info = dcn10_get_default_tiling_info ++}; ++ ++static uint32_t read_pipe_fuses(struct dc_context *ctx) ++{ ++ uint32_t value = REG_READ(CC_DC_PIPE_DIS); ++ ++ if (value == 0 && ctx->dce_environment == DCE_ENV_DIAG) ++ value = 0xF; ++ /* DCN401 support max 4 pipes */ ++ value = value & 0xf; ++ return value; ++} ++ ++static bool dcn42_resource_construct( ++ uint8_t num_virtual_links, ++ struct dc *dc, ++ struct dcn42_resource_pool *pool) ++{ ++ int i, j; ++ struct dc_context *ctx = dc->ctx; ++ struct irq_service_init_data init_data; ++ uint32_t pipe_fuses; ++ uint32_t num_pipes; ++ ++#undef REG_STRUCT ++#define REG_STRUCT bios_regs ++ bios_regs_init(); ++ ++#undef REG_STRUCT ++#define REG_STRUCT clk_src_regs ++ clk_src_regs_init(0, A), ++ clk_src_regs_init(1, B), ++ clk_src_regs_init(2, C), ++ clk_src_regs_init(3, D), ++ clk_src_regs_init(4, E); ++ ++#undef REG_STRUCT ++#define REG_STRUCT abm_regs ++ abm_regs_init(0), ++ abm_regs_init(1), ++ abm_regs_init(2), ++ abm_regs_init(3); ++#undef REG_STRUCT ++#define REG_STRUCT dccg_regs ++ dccg_regs_init(); ++ ++ ctx->dc_bios->regs = &bios_regs; ++ ++ pool->base.res_cap = &res_cap_dcn42; ++ ++ /* max number of pipes for ASIC before checking for pipe fuses */ ++ num_pipes = pool->base.res_cap->num_dpp; ++ pipe_fuses = read_pipe_fuses(ctx); ++ ++ for (i = 0; i < pool->base.res_cap->num_dpp; i++) ++ if (pipe_fuses & 1 << i) ++ num_pipes--; ++ ++ if (pipe_fuses & 1) ++ ASSERT(0); // Unexpected - Pipe 0 should always be fully functional! ++ ++ if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) ++ ASSERT(0); // Entire DCN is harvested! ++ ++ pool->base.funcs = &dcn42_res_pool_funcs; ++ ++ /************************************************* ++ * Resource + asic cap harcoding * ++ *************************************************/ ++ pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE; ++ pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; ++ pool->base.pipe_count = num_pipes; ++ pool->base.mpcc_count = num_pipes; ++ dc->caps.ips_v2_support = true; ++ dc->caps.max_downscale_ratio = 600; ++ dc->caps.i2c_speed_in_khz = 100; ++ dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ ++ /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ ++ dc->caps.max_cursor_size = 64; ++ dc->caps.max_buffered_cursor_size = 64; ++ dc->caps.cursor_not_scaled = true; ++ dc->caps.min_horizontal_blanking_period = 80; ++ dc->caps.dmdata_alloc_size = 2048; ++ dc->caps.mall_size_per_mem_channel = 4; ++ /* total size = mall per channel * num channels * 1024 * 1024 */ ++ dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * ++ dc->ctx->dc_bios->vram_info.num_chans * 1048576; ++ dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; ++ dc->caps.cache_line_size = 64; ++ dc->caps.cache_num_ways = 16; ++ ++ /* Calculate the available MALL space */ ++ dc->caps.max_cab_allocation_bytes = ++ dcn32_calc_num_avail_chans_for_mall(dc, dc->ctx->dc_bios->vram_info.num_chans) * ++ dc->caps.mall_size_per_mem_channel * 1024 * 1024; ++ dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; ++ ++ dc->caps.subvp_fw_processing_delay_us = 15; ++ dc->caps.subvp_drr_max_vblank_margin_us = 40; ++ dc->caps.subvp_prefetch_end_to_mall_start_us = 15; ++ dc->caps.subvp_swath_height_margin_lines = 16; ++ dc->caps.subvp_pstate_allow_width_us = 20; ++ dc->caps.subvp_vertical_int_margin_us = 30; ++ dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin ++ ++ dc->caps.max_slave_planes = 2; ++ dc->caps.max_slave_yuv_planes = 2; ++ dc->caps.max_slave_rgb_planes = 2; ++ dc->caps.post_blend_color_processing = true; ++ dc->caps.force_dp_tps4_for_cp2520 = true; ++ if (dc->config.forceHBR2CP2520) ++ dc->caps.force_dp_tps4_for_cp2520 = false; ++ dc->caps.dp_hdmi21_pcon_support = true; ++ dc->caps.dp_hpo = true; ++ dc->caps.edp_dsc_support = true; ++ dc->caps.extended_aux_timeout_support = true; ++ dc->caps.dmcub_support = true; ++ dc->caps.is_apu = true; ++ dc->caps.seamless_odm = true; ++ dc->caps.zstate_support = true; ++ dc->caps.ips_support = true; ++ dc->caps.max_v_total = (1 << 15) - 1; ++ dc->caps.vtotal_limited_by_fp2 = true; ++ ++ dc->caps.seamless_odm = true; ++ dc->caps.zstate_support = true; ++ dc->caps.ips_support = true; ++ dc->caps.max_v_total = (1 << 15) - 1; ++ dc->caps.vtotal_limited_by_fp2 = true; ++ ++ /* Color pipeline capabilities */ ++ dc->caps.color.dpp.dcn_arch = 1; ++ dc->caps.color.dpp.input_lut_shared = 0; ++ dc->caps.color.dpp.icsc = 1; ++ dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr ++ dc->caps.color.dpp.dgam_rom_caps.srgb = 1; ++ dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; ++ dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; ++ dc->caps.color.dpp.dgam_rom_caps.pq = 1; ++ dc->caps.color.dpp.dgam_rom_caps.hlg = 1; ++ dc->caps.color.dpp.post_csc = 1; ++ dc->caps.color.dpp.gamma_corr = 1; ++ dc->caps.color.dpp.dgam_rom_for_yuv = 0; ++ ++ dc->caps.color.dpp.hw_3d_lut = 0; ++ dc->caps.color.dpp.ogam_ram = 0; ++ // no OGAM ROM on DCN2 and later ASICs ++ dc->caps.color.dpp.ogam_rom_caps.srgb = 0; ++ dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; ++ dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; ++ dc->caps.color.dpp.ogam_rom_caps.pq = 0; ++ dc->caps.color.dpp.ogam_rom_caps.hlg = 0; ++ dc->caps.color.dpp.ocsc = 0; ++ ++ dc->caps.color.mpc.gamut_remap = 1; ++ //configurable to be before or after BLND in MPCC ++ dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; ++ dc->caps.color.mpc.num_rmcm_3dluts = 2; ++ dc->caps.color.mpc.ogam_ram = 1; ++ dc->caps.color.mpc.ogam_rom_caps.srgb = 0; ++ dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; ++ dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; ++ dc->caps.color.mpc.ogam_rom_caps.pq = 0; ++ dc->caps.color.mpc.ogam_rom_caps.hlg = 0; ++ dc->caps.color.mpc.ocsc = 1; ++ dc->caps.color.mpc.preblend = true; ++ dc->caps.color.mpc.mcm_3d_lut_caps.dma_3d_lut = 1; ++ dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_9 = 1; ++ dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_17 = 1; ++ dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.linear_1d = 1; ++ dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1; ++ dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1; ++ dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12msb = 1; ++ dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1; ++ dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1; ++ dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1; ++ dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1; ++ dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut = 1; ++ dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 = 1; ++ dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 = 1; ++ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.linear_1d = 1; ++ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1; ++ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1; ++ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12msb = 1; ++ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1; ++ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1; ++ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1; ++ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1; ++ ++ dc->caps.num_of_host_routers = 3; ++ dc->caps.num_of_dpias_per_host_router = 2; ++ ++ /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order ++ * to provide some margin. ++ * It's expected for furture ASIC to have equal or higher value, in order to ++ * have determinstic power improvement from generate to genration. ++ * (i.e., we should not expect new ASIC generation with lower vmin rate) ++ */ ++ dc->caps.max_disp_clock_khz_at_vmin = 650000; ++ dc->config.use_spl = true; ++ dc->config.prefer_easf = true; ++ ++ dc->config.dcn_sharpness_range.sdr_rgb_min = 0; ++ dc->config.dcn_sharpness_range.sdr_rgb_max = 1750; ++ dc->config.dcn_sharpness_range.sdr_rgb_mid = 750; ++ dc->config.dcn_sharpness_range.sdr_yuv_min = 0; ++ dc->config.dcn_sharpness_range.sdr_yuv_max = 3500; ++ dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500; ++ dc->config.dcn_sharpness_range.hdr_rgb_min = 0; ++ dc->config.dcn_sharpness_range.hdr_rgb_max = 2750; ++ dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500; ++ ++ dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0; ++ dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250; ++ dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250; ++ dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0; ++ dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500; ++ dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500; ++ dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0; ++ dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750; ++ dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500; ++ ++ dc->config.use_pipe_ctx_sync_logic = true; ++ dc->config.dc_mode_clk_limit_support = false; ++ dc->config.enable_windowed_mpo_odm = true; ++ /* Use psp mailbox to enable assr */ ++ dc->config.use_assr_psp_message = true; ++ /* dcn42 and afterward always support external panel replay */ ++ dc->config.frame_update_cmd_version2 = true; ++ ++ /* read VBIOS LTTPR caps */ ++ { ++ if (ctx->dc_bios->funcs->get_lttpr_caps) { ++ enum bp_result bp_query_result; ++ uint8_t is_vbios_lttpr_enable = 0; ++ ++ bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); ++ dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; ++ } ++ ++ dc->caps.vbios_lttpr_aware = true; ++ } ++ dc->check_config = config_defaults; ++ ++ if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) ++ dc->debug = debug_defaults_drv; ++ ++ /*HW default is to have all the FGCG enabled, SW no need to program them*/ ++ dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF; ++ // Init the vm_helper ++ if (dc->vm_helper) ++ vm_helper_init(dc->vm_helper, 16); ++ ++ /************************************************* ++ * Create resources * ++ *************************************************/ ++ ++ /* Clock Sources for Pixel Clock*/ ++ pool->base.clock_sources[DCN401_CLK_SRC_PLL0] = ++ dcn42_clock_source_create(ctx, ctx->dc_bios, ++ CLOCK_SOURCE_COMBO_PHY_PLL0, ++ &clk_src_regs[0], false); ++ pool->base.clock_sources[DCN401_CLK_SRC_PLL1] = ++ dcn42_clock_source_create(ctx, ctx->dc_bios, ++ CLOCK_SOURCE_COMBO_PHY_PLL1, ++ &clk_src_regs[1], false); ++ pool->base.clock_sources[DCN401_CLK_SRC_PLL2] = ++ dcn42_clock_source_create(ctx, ctx->dc_bios, ++ CLOCK_SOURCE_COMBO_PHY_PLL2, ++ &clk_src_regs[2], false); ++ pool->base.clock_sources[DCN401_CLK_SRC_PLL3] = ++ dcn42_clock_source_create(ctx, ctx->dc_bios, ++ CLOCK_SOURCE_COMBO_PHY_PLL3, ++ &clk_src_regs[3], false); ++ pool->base.clock_sources[DCN401_CLK_SRC_PLL4] = ++ dcn42_clock_source_create(ctx, ctx->dc_bios, ++ CLOCK_SOURCE_COMBO_PHY_PLL4, ++ &clk_src_regs[4], false); ++ ++ pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL; ++ ++ /* todo: not reuse phy_pll registers */ ++ pool->base.dp_clock_source = ++ dcn42_clock_source_create(ctx, ctx->dc_bios, ++ CLOCK_SOURCE_ID_DP_DTO, ++ &clk_src_regs[0], true); ++ ++ for (i = 0; i < pool->base.clk_src_count; i++) { ++ if (pool->base.clock_sources[i] == NULL) { ++ dm_error("DC: failed to create clock sources!\n"); ++ BREAK_TO_DEBUGGER(); ++ goto create_fail; ++ } ++ } ++ ++ /* DCCG */ ++ pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); ++ if (pool->base.dccg == NULL) { ++ dm_error("DC: failed to create dccg!\n"); ++ BREAK_TO_DEBUGGER(); ++ goto create_fail; ++ } ++ ++#undef REG_STRUCT ++#define REG_STRUCT pg_cntl_regs ++ pg_cntl_dcn42_regs_init(); ++ ++ pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); ++ if (pool->base.pg_cntl == NULL) { ++ dm_error("DC: failed to create power gate control!\n"); ++ BREAK_TO_DEBUGGER(); ++ goto create_fail; ++ } ++ /* IRQ Service */ ++ init_data.ctx = dc->ctx; ++ pool->base.irqs = dal_irq_service_dcn42_create(&init_data); ++ if (!pool->base.irqs) ++ goto create_fail; ++ ++ /* HUBBUB */ ++ pool->base.hubbub = dcn42_hubbub_create(ctx); ++ if (pool->base.hubbub == NULL) { ++ BREAK_TO_DEBUGGER(); ++ dm_error("DC: failed to create hubbub!\n"); ++ goto create_fail; ++ } ++ ++ /* HUBPs, DPPs, OPPs, TGs, ABMs */ ++ for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { ++ /* if pipe is disabled, skip instance of HW pipe, ++ * i.e, skip ASIC register instance ++ */ ++ if (pipe_fuses & 1 << i) ++ continue; ++ ++ pool->base.hubps[j] = dcn42_hubp_create(ctx, i); ++ if (pool->base.hubps[j] == NULL) { ++ BREAK_TO_DEBUGGER(); ++ dm_error( ++ "DC: failed to create hubps!\n"); ++ goto create_fail; ++ } ++ ++ pool->base.dpps[j] = dcn42_dpp_create(ctx, i); ++ if (pool->base.dpps[j] == NULL) { ++ BREAK_TO_DEBUGGER(); ++ dm_error( ++ "DC: failed to create dpps!\n"); ++ goto create_fail; ++ } ++ ++ pool->base.opps[j] = dcn42_opp_create(ctx, i); ++ if (pool->base.opps[j] == NULL) { ++ BREAK_TO_DEBUGGER(); ++ dm_error( ++ "DC: failed to create output pixel processor!\n"); ++ goto create_fail; ++ } ++ ++ pool->base.timing_generators[j] = dcn42_timing_generator_create( ++ ctx, i); ++ if (pool->base.timing_generators[j] == NULL) { ++ BREAK_TO_DEBUGGER(); ++ dm_error("DC: failed to create tg!\n"); ++ goto create_fail; ++ } ++ ++ pool->base.multiple_abms[j] = dmub_abm_create(ctx, ++ &abm_regs[i], ++ &abm_shift, ++ &abm_mask); ++ if (pool->base.multiple_abms[j] == NULL) { ++ dm_error("DC: failed to create abm for pipe %d!\n", i); ++ BREAK_TO_DEBUGGER(); ++ goto create_fail; ++ } ++ ++ /* index for resource pool arrays for next valid pipe */ ++ j++; ++ } ++ ++ /* PSR */ ++ pool->base.psr = dmub_psr_create(ctx); ++ if (pool->base.psr == NULL) { ++ dm_error("DC: failed to create psr obj!\n"); ++ BREAK_TO_DEBUGGER(); ++ goto create_fail; ++ } ++ ++ /* Replay */ ++ pool->base.replay = dmub_replay_create(ctx); ++ if (pool->base.replay == NULL) { ++ dm_error("DC: failed to create replay obj!\n"); ++ BREAK_TO_DEBUGGER(); ++ goto create_fail; ++ } ++ ++ /* MPCCs */ ++ pool->base.mpc = dcn42_mpc_create(ctx, pool->base.res_cap->num_timing_generator, ++ pool->base.res_cap->num_mpc_3dlut); ++ if (pool->base.mpc == NULL) { ++ BREAK_TO_DEBUGGER(); ++ dm_error("DC: failed to create mpc!\n"); ++ goto create_fail; ++ } ++ ++ /* DSCs */ ++ for (i = 0; i < pool->base.res_cap->num_dsc; i++) { ++ pool->base.dscs[i] = dcn42_dsc_create(ctx, i); ++ if (pool->base.dscs[i] == NULL) { ++ BREAK_TO_DEBUGGER(); ++ dm_error("DC: failed to create display stream compressor %d!\n", i); ++ goto create_fail; ++ } ++ } ++ ++ /* DWB */ ++ if (!dcn42_dwbc_create(ctx, &pool->base)) { ++ BREAK_TO_DEBUGGER(); ++ dm_error("DC: failed to create dwbc!\n"); ++ goto create_fail; ++ } ++ ++ /* MMHUBBUB */ ++ if (!dcn42_mmhubbub_create(ctx, &pool->base)) { ++ BREAK_TO_DEBUGGER(); ++ dm_error("DC: failed to create mcif_wb!\n"); ++ goto create_fail; ++ } ++ ++ /* AUX and I2C */ ++ for (i = 0; i < pool->base.res_cap->num_ddc; i++) { ++ pool->base.engines[i] = dcn42_aux_engine_create(ctx, i); ++ ++ if (pool->base.engines[i] == NULL) { ++ BREAK_TO_DEBUGGER(); ++ dm_error( ++ "DC:failed to create aux engine!!\n"); ++ goto create_fail; ++ } ++ pool->base.hw_i2cs[i] = dcn42_i2c_hw_create(ctx, i); ++ if (pool->base.hw_i2cs[i] == NULL) { ++ BREAK_TO_DEBUGGER(); ++ dm_error( ++ "DC:failed to create hw i2c!!\n"); ++ goto create_fail; ++ } ++ pool->base.sw_i2cs[i] = NULL; ++ } ++ /* DCN4.2 has 6 DPIA */ ++ pool->base.usb4_dpia_count = dc->caps.num_of_host_routers * dc->caps.num_of_dpias_per_host_router; ++ if (dc->debug.dpia_debug.bits.disable_dpia) ++ pool->base.usb4_dpia_count = 0; ++ ++ /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ ++ if (!resource_construct(num_virtual_links, dc, &pool->base, ++ &res_create_funcs)) ++ goto create_fail; ++ ++ /* HW Sequencer init functions and Plane caps */ ++ dcn42_hw_sequencer_init_functions(dc); ++ ++ dc->caps.max_planes = pool->base.pipe_count; ++ ++ for (i = 0; i < dc->caps.max_planes; ++i) ++ dc->caps.planes[i] = plane_cap; ++ ++ dc->caps.max_odm_combine_factor = 4; ++ ++ dc->cap_funcs = cap_funcs; ++ dc->dcn_ip->max_num_dpp = pool->base.pipe_count; ++ ++ // For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided ++ if (dc->config.sdpif_request_limit_words_per_umc == 0) ++ dc->config.sdpif_request_limit_words_per_umc = 16; ++ ++ dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; ++ /*this will use real soc clock table*/ ++ dc->dml2_options.use_native_soc_bb_construction = true; ++ dc->dml2_options.minimize_dispclk_using_odm = false; ++ if (dc->config.EnableMinDispClkODM) ++ dc->dml2_options.minimize_dispclk_using_odm = true; ++ dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; ++ dc->dml2_options.map_dc_pipes_with_callbacks = true; ++ dc->dml2_options.force_tdlut_enable = true; ++ ++ resource_init_common_dml2_callbacks(dc, &dc->dml2_options); ++ dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = ++ &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; ++ dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; ++ dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = ++ pool->base.funcs->calculate_mall_ways_from_bytes; ++ ++ dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us; ++ dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us; ++ dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; ++ dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines; ++ ++ dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp; ++ dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch; ++ ++ dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size; ++ dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; ++ dc->dml2_options.mall_cfg.max_cab_allocation_bytes = ++ dc->caps.max_cab_allocation_bytes; ++ dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE; ++ dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE; ++ dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES; ++ dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; ++ ++ dc->dml2_options.max_segments_per_hubp = 24; ++ dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB; ++ dc->dml2_options.gpuvm_enable = true; ++ dc->dml2_options.hostvm_enable = true; ++ ++ /* SPL */ ++ dc->caps.scl_caps.sharpener_support = true; ++ ++ return true; ++ ++create_fail: ++ ++ dcn42_resource_destruct(pool); ++ ++ return false; ++} ++struct resource_pool *dcn42_create_resource_pool( ++ const struct dc_init_data *init_data, ++ struct dc *dc) ++{ ++ struct dcn42_resource_pool *pool = ++ kzalloc(sizeof(struct dcn401_resource_pool), GFP_KERNEL); ++ ++ if (!pool) ++ return NULL; ++ ++ if (dcn42_resource_construct(init_data->num_virtual_links, dc, pool)) ++ return &pool->base; ++ ++ BREAK_TO_DEBUGGER(); ++ kfree(pool); ++ return NULL; ++} +-- +2.53.0 + diff --git a/SPECS/linux/0084-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch b/SPECS/linux/0084-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch index eefb74761d..503e0c9301 100644 --- a/SPECS/linux/0084-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch +++ b/SPECS/linux/0084-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch @@ -1,8 +1,8 @@ -From 029ac5da40e6ae95acc9fde9e66c8338d1fa3b87 Mon Sep 17 00:00:00 2001 +From 99a084f5cd5c82834c436119b161e4c598ec7b06 Mon Sep 17 00:00:00 2001 From: Rafal Ostrowski -Date: Tue, 24 Feb 2026 15:36:09 +0100 -Subject: [PATCH 084/269] UPSTREAM: drm/amd/display: Move FPU Guards From DML - To DC - Part 1 +Date: Wed, 18 Feb 2026 16:19:47 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/amd/display: Move FPU Guards From DML To + DC - Part 2 [Why] FPU guards (DC_FP_START/DC_FP_END) are required to wrap around code that @@ -12,2910 +12,1130 @@ a file that is a FPU unit, other sections in the file that aren't guarded may be end up being compiled to use FPU operations. [How] -Added DC_FP_START and DC_FP_END to DC functions that call DML functions -using FPU. +Removed DC_FP_START and DC_FP_END. Reviewed-by: Dillon Varone Signed-off-by: Rafal Ostrowski Signed-off-by: Alex Hung +Signed-off-by: Chuanyu Tseng Signed-off-by: Alex Deucher -(cherry picked from commit 3539437f354bd24c98928a80d4db3a23fa2a7b19) +(cherry picked from commit 4bb2f0721ed8a2a70f864b9358bd6cd4d92199b3) Signed-off-by: Xi Ruoyao Signed-off-by: Han Gao --- - .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 25 +- - .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.h | 17 +- - .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 2 - - .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 - - drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +- - .../gpu/drm/amd/display/dc/core/dc_state.c | 75 +- - .../gpu/drm/amd/display/dc/core/dc_stream.c | 15 +- - .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 4 +- - .../dc/resource/dcn35/dcn35_resource.c | 10 +- - .../dc/resource/dcn35/dcn35_resource.h | 1 + - .../dc/resource/dcn351/dcn351_resource.c | 10 +- - .../dc/resource/dcn36/dcn36_resource.c | 4 +- - .../dc/resource/dcn401/dcn401_resource.c | 30 +- - .../dc/resource/dcn42/dcn42_resource.c | 2355 +++++++++++++++++ - 14 files changed, 2508 insertions(+), 47 deletions(-) - create mode 100644 drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c + .../gpu/drm/amd/display/dc/dml2_0/Makefile | 73 +--- + .../display/dc/dml2_0/dml21/dml21_wrapper.c | 379 +---------------- + .../display/dc/dml2_0/dml21/dml21_wrapper.h | 30 -- + .../dc/dml2_0/dml21/dml21_wrapper_fpu.c | 381 ++++++++++++++++++ + .../dc/dml2_0/dml21/dml21_wrapper_fpu.h | 60 +++ + .../drm/amd/display/dc/dml2_0/dml2_wrapper.c | 21 +- + .../amd/display/dc/dml2_0/dml2_wrapper_fpu.c | 9 +- + 7 files changed, 484 insertions(+), 469 deletions(-) + create mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c + create mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c -index e46f8ce41d87..8ba9b4f56f87 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c -@@ -53,11 +53,30 @@ inline void dc_assert_fp_enabled(void) - { - int depth; +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile +index 30cfc0848792..a094cfa78260 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile +@@ -53,25 +53,29 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/inc + subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/inc + subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/ -- depth = __this_cpu_read(fpu_recursion_depth); -+ depth = this_cpu_read(fpu_recursion_depth); +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper_fpu.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_ccflags) ++# Add FPU flags to all dml2 files by default, remove NO_FPU flags. ++# FPU flags step 1: Find all .c files in dal/dc/dml2_0 and it's subfolders ++DML2_ABS_PATH := $(FULL_AMD_DISPLAY_PATH)/dc/dml2_0 ++DML2_C_FILES := $(shell find $(DML2_ABS_PATH) -name '*.c' -type f) ++ ++# FPU flags step 2: Convert to .o and make paths relative to $(AMDDALPATH)/dc/dml2_0/ ++DML2_RELATIVE_O_FILES := $(patsubst $(DML2_ABS_PATH)/%,dc/dml2_0/%,$(patsubst %.c,%.o,$(DML2_C_FILES))) - ASSERT(depth >= 1); - } ++# FPU flags step 3: Apply FPU flags to all .o files from dal/dc/dml2_0 and it's subfolders ++$(foreach obj,$(DML2_RELATIVE_O_FILES),$(eval CFLAGS_$(AMDDALPATH)/$(obj) := $(dml2_ccflags))) ++$(foreach obj,$(DML2_RELATIVE_O_FILES),$(eval CFLAGS_REMOVE_$(AMDDALPATH)/$(obj) := $(dml2_rcflags))) ++ ++# FPU flags step 4: Replace CFLAGS per file for files with additional flags beyond dml2_ccflags and dml2_rcflags ++CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag) ++CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag) ++CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_ccflags) $(frame_warn_flag) ++CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_rcflags) ++CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_wrapper.o := $(dml2_rcflags) + CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper_fpu.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_ccflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_wrapper.o := $(dml2_ccflags) -+/** -+ * dc_assert_fp_enabled - Check if FPU protection is enabled -+ * -+ * This function tells if the code is already under FPU protection or not. A -+ * function that works as an API for a set of FPU operations can use this -+ * function for checking if the caller invoked it after DC_FP_START(). For -+ * example, take a look at dcn20_fpu.c file. -+ * -+ * Similar to dc_assert_fp_enabled, but does not assert, returns status instead. -+ */ -+inline bool dc_is_fp_enabled(void) -+{ -+ int depth; -+ -+ depth = this_cpu_read(fpu_recursion_depth); -+ -+ return (depth >= 1); -+} -+ - /** - * dc_fpu_begin - Enables FPU protection - * @function_name: A string containing the function name for debug purposes -@@ -77,7 +96,7 @@ void dc_fpu_begin(const char *function_name, const int line) - - WARN_ON_ONCE(!in_task()); - preempt_disable(); -- depth = __this_cpu_inc_return(fpu_recursion_depth); -+ depth = this_cpu_inc_return(fpu_recursion_depth); - if (depth == 1) { - BUG_ON(!kernel_fpu_available()); - kernel_fpu_begin(); -@@ -100,7 +119,7 @@ void dc_fpu_end(const char *function_name, const int line) - { - int depth; - -- depth = __this_cpu_dec_return(fpu_recursion_depth); -+ depth = this_cpu_dec_return(fpu_recursion_depth); - if (depth == 0) { - kernel_fpu_end(); - } else { -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h -index 4e921632bc4e..5e95419d3798 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h -@@ -28,15 +28,30 @@ - #define __DC_FPU_H__ - - void dc_assert_fp_enabled(void); -+bool dc_is_fp_enabled(void); - void dc_fpu_begin(const char *function_name, const int line); - void dc_fpu_end(const char *function_name, const int line); + DML2 = display_mode_core.o display_mode_util.o dml2_wrapper_fpu.o dml2_wrapper.o \ + dml2_utils.o dml2_policy.o dml2_translation_helper.o dml2_dc_resource_mgmt.o dml2_mall_phantom.o \ +@@ -81,40 +85,6 @@ AMD_DAL_DML2 = $(addprefix $(AMDDALPATH)/dc/dml2_0/,$(DML2)) - #ifndef _LINUX_FPU_COMPILATION_UNIT - #define DC_FP_START() dc_fpu_begin(__func__, __LINE__) - #define DC_FP_END() dc_fpu_end(__func__, __LINE__) -+#ifdef CONFIG_DRM_AMD_DC_FP -+#define DC_RUN_WITH_PREEMPTION_ENABLED(code) \ -+ do { \ -+ bool dc_fp_enabled = dc_is_fp_enabled(); \ -+ if (dc_fp_enabled) \ -+ DC_FP_END(); \ -+ code; \ -+ if (dc_fp_enabled) \ -+ DC_FP_START(); \ -+ } while (0) -+#else -+#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code -+#endif // !CONFIG_DRM_AMD_DC_FP - #else - #define DC_FP_START() BUILD_BUG() - #define DC_FP_END() BUILD_BUG() --#endif -+#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code -+#endif // !_LINUX_FPU_COMPILATION_UNIT + AMD_DISPLAY_FILES += $(AMD_DAL_DML2) - #endif /* __DC_FPU_H__ */ -diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c -index b0aba3a6f13c..e06f06158ac8 100644 ---- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c -+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c -@@ -421,10 +421,8 @@ static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) - clk_mgr_base->bw_params->dc_mode_softmax_memclk = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK); - - /* Refresh bounding box */ -- DC_FP_START(); - clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( - clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); -- DC_FP_END(); - } - - static bool dcn3_is_smu_present(struct clk_mgr *clk_mgr_base) -diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c -index 2856b0337e87..4007ab353ffd 100644 ---- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c -+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c -@@ -1059,11 +1059,9 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) - if (!clk_mgr->dpm_present) - dcn32_patch_dpm_table(clk_mgr_base->bw_params); - -- DC_FP_START(); - /* Refresh bounding box */ - clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( - clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); -- DC_FP_END(); - } - - static bool dcn32_are_clock_states_equal(struct dc_clocks *a, -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c -index 3e87b6a553be..0686141af3eb 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c -@@ -1165,11 +1165,8 @@ static bool dc_construct(struct dc *dc, - #ifdef CONFIG_DRM_AMD_DC_FP - dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present; - -- if (dc->res_pool->funcs->update_bw_bounding_box) { -- DC_FP_START(); -+ if (dc->res_pool->funcs->update_bw_bounding_box) - dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); -- DC_FP_END(); -- } - dc->soc_and_ip_translator = dc_create_soc_and_ip_translator(dc_ctx->dce_version); - if (!dc->soc_and_ip_translator) - goto fail; -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c -index a40e5c44143f..13d334c2cb6b 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c -@@ -205,19 +205,33 @@ struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *p - state->power_source = params ? params->power_source : DC_POWER_SOURCE_AC; - - #ifdef CONFIG_DRM_AMD_DC_FP -+ bool status; -+ - if (dc->debug.using_dml2) { -- if (!dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2)) { -+ DC_FP_START(); -+ status = dml2_create(dc, &dc->dml2_options, &state->bw_ctx.dml2); -+ DC_FP_END(); -+ -+ if (!status) { - dc_state_release(state); - return NULL; - } - -- if (dc->caps.dcmode_power_limits_present && !dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source)) { -- dc_state_release(state); -- return NULL; -+ if (dc->caps.dcmode_power_limits_present) { -+ bool status; -+ -+ DC_FP_START(); -+ status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source); -+ DC_FP_END(); -+ -+ if (!status) { -+ dc_state_release(state); -+ return NULL; -+ } - } -- } --#endif - -+ } -+#endif // CONFIG_DRM_AMD_DC_FP - kref_init(&state->refcount); - - return state; -@@ -235,14 +249,20 @@ void dc_state_copy(struct dc_state *dst_state, struct dc_state *src_state) - - #ifdef CONFIG_DRM_AMD_DC_FP - dst_state->bw_ctx.dml2 = dst_dml2; -- if (src_state->bw_ctx.dml2) -+ if (src_state->bw_ctx.dml2) { -+ DC_FP_START(); - dml2_copy(dst_state->bw_ctx.dml2, src_state->bw_ctx.dml2); -+ DC_FP_END(); -+ } +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_ccflags) $(frame_warn_flag) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_ccflags) +-CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_ccflags) +- +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_rcflags) +-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_rcflags) +- + DML21 := src/dml2_top/dml2_top_interfaces.o + DML21 += src/dml2_top/dml2_top_soc15.o + DML21 += src/dml2_core/dml2_core_dcn4.o +@@ -131,6 +101,7 @@ DML21 += src/dml2_pmo/dml2_pmo_dcn4_fams2.o + DML21 += src/dml2_standalone_libraries/lib_float_math.o + DML21 += dml21_translation_helper.o + DML21 += dml21_wrapper.o ++DML21 += dml21_wrapper_fpu.o + DML21 += dml21_utils.o - dst_state->bw_ctx.dml2_dc_power_source = dst_dml2_dc_power_source; -- if (src_state->bw_ctx.dml2_dc_power_source) -- dml2_copy(dst_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source); --#endif + AMD_DAL_DML21 = $(addprefix $(AMDDALPATH)/dc/dml2_0/dml21/,$(DML21)) +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c +index 2623e917ec28..1a98578f223c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c +@@ -9,6 +9,10 @@ + #include "dml21_utils.h" + #include "dml21_translation_helper.h" + #include "dml2_dc_resource_mgmt.h" ++#include "dml2_wrapper.h" ++#include "dml2_wrapper_fpu.h" ++#include "dml21_wrapper.h" ++#include "dml21_wrapper_fpu.h" + #include "dc_fpu.h" -+ if (src_state->bw_ctx.dml2_dc_power_source) { -+ DC_FP_START(); -+ dml2_copy(dst_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source); -+ DC_FP_END(); -+ } -+#endif // CONFIG_DRM_AMD_DC_FP - /* context refcount should not be overridden */ - dst_state->refcount = refcount; + #if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) +@@ -40,44 +44,11 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx) + return true; } -@@ -258,22 +278,35 @@ struct dc_state *dc_state_create_copy(struct dc_state *src_state) - dc_state_copy_internal(new_state, src_state); - #ifdef CONFIG_DRM_AMD_DC_FP -+ bool status; -+ - new_state->bw_ctx.dml2 = NULL; - new_state->bw_ctx.dml2_dc_power_source = NULL; - -- if (src_state->bw_ctx.dml2 && -- !dml2_create_copy(&new_state->bw_ctx.dml2, src_state->bw_ctx.dml2)) { -- dc_state_release(new_state); -- return NULL; +-static void dml21_populate_configuration_options(const struct dc *in_dc, +- struct dml2_context *dml_ctx, +- const struct dml2_configuration_options *config) +-{ +- dml_ctx->config = *config; +- +- /* UCLK P-State options */ +- if (in_dc->debug.dml21_force_pstate_method) { +- dml_ctx->config.pmo.force_pstate_method_enable = true; +- for (int i = 0; i < MAX_PIPES; i++) +- dml_ctx->config.pmo.force_pstate_method_values[i] = in_dc->debug.dml21_force_pstate_method_values[i]; +- } else { +- dml_ctx->config.pmo.force_pstate_method_enable = false; - } -+ if (src_state->bw_ctx.dml2) { -+ DC_FP_START(); -+ status = dml2_create_copy(&new_state->bw_ctx.dml2, src_state->bw_ctx.dml2); -+ DC_FP_END(); - -- if (src_state->bw_ctx.dml2_dc_power_source && -- !dml2_create_copy(&new_state->bw_ctx.dml2_dc_power_source, src_state->bw_ctx.dml2_dc_power_source)) { -- dc_state_release(new_state); -- return NULL; -+ if (!status) { -+ dc_state_release(new_state); -+ return NULL; -+ } - } --#endif - -+ -+ if (src_state->bw_ctx.dml2_dc_power_source) { -+ DC_FP_START(); -+ status = dml2_create_copy(&new_state->bw_ctx.dml2_dc_power_source, -+ src_state->bw_ctx.dml2_dc_power_source); -+ DC_FP_END(); -+ -+ if (!status) { -+ dc_state_release(new_state); -+ return NULL; -+ } -+ } -+#endif // CONFIG_DRM_AMD_DC_FP - kref_init(&new_state->refcount); - - return new_state; -@@ -351,11 +384,13 @@ static void dc_state_free(struct kref *kref) - dc_state_destruct(state); - - #ifdef CONFIG_DRM_AMD_DC_FP -+ DC_FP_START(); - dml2_destroy(state->bw_ctx.dml2); - state->bw_ctx.dml2 = 0; - - dml2_destroy(state->bw_ctx.dml2_dc_power_source); - state->bw_ctx.dml2_dc_power_source = 0; -+ DC_FP_END(); - #endif - - kvfree(state); -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c -index baf820e6eae8..dca64e1671f6 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c -@@ -42,6 +42,13 @@ - #define MAX(x, y) ((x > y) ? x : y) - #endif - -+#include "dc_fpu.h" -+ -+#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) -+#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code -+#endif // !DC_RUN_WITH_PREEMPTION_ENABLED -+ -+ - /******************************************************************************* - * Private functions - ******************************************************************************/ -@@ -170,11 +177,15 @@ struct dc_stream_state *dc_create_stream_for_sink( - if (sink == NULL) - goto fail; - -- stream = kzalloc_obj(struct dc_stream_state, GFP_ATOMIC); -+ DC_RUN_WITH_PREEMPTION_ENABLED(stream = kzalloc_obj(struct dc_stream_state, GFP_ATOMIC)); -+ - if (stream == NULL) - goto fail; - -- stream->update_scratch = kzalloc((int32_t) dc_update_scratch_space_size(), GFP_ATOMIC); -+ DC_RUN_WITH_PREEMPTION_ENABLED(stream->update_scratch = -+ kzalloc((int32_t) dc_update_scratch_space_size(), -+ GFP_ATOMIC)); -+ - if (stream->update_scratch == NULL) - goto fail; - -diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c -index 4dfb6c865831..a6c3a1f5fbfa 100644 ---- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c -+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c -@@ -371,8 +371,8 @@ void dcn401_init_hw(struct dc *dc) - dc->res_pool->funcs->update_bw_bounding_box && - dc->clk_mgr && dc->clk_mgr->bw_params) { - /* update bounding box if FAMS2 disabled, or if dchub clk has changed */ -- dc->res_pool->funcs->update_bw_bounding_box(dc, -- dc->clk_mgr->bw_params); -+ if (dc->clk_mgr) -+ dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); - } - } - } -diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c -index 598b2f25881d..adbd23fcc9b7 100644 ---- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c -@@ -1773,9 +1773,11 @@ static enum dc_status dcn35_validate_bandwidth(struct dc *dc, - { - bool out = false; - -+ DC_FP_START(); - out = dml2_validate(dc, context, - context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, - validate_mode); -+ DC_FP_END(); - - if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) - return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; -@@ -1809,6 +1811,12 @@ static int populate_dml_pipes_from_context_fpu(struct dc *dc, - return ret; - } - -+void dcn35_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+{ -+ DC_FP_START(); -+ dcn35_update_bw_bounding_box_fpu(dc, bw_params); -+ DC_FP_END(); -+} - static struct resource_funcs dcn35_res_pool_funcs = { - .destroy = dcn35_destroy_resource_pool, - .link_enc_create = dcn35_link_encoder_create, -@@ -1830,7 +1838,7 @@ static struct resource_funcs dcn35_res_pool_funcs = { - .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, - .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, - .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, -- .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu, -+ .update_bw_bounding_box = dcn35_update_bw_bounding_box, - .patch_unknown_plane_state = dcn35_patch_unknown_plane_state, - .get_panel_config_defaults = dcn35_get_panel_config_defaults, - .get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia, -diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h -index 9c56ae76e0c7..6c2c61c711b9 100644 ---- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h -+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h -@@ -312,4 +312,5 @@ struct resource_pool *dcn35_create_resource_pool( - #define DPP_REG_LIST_DCN35_RI(id)\ - DPP_REG_LIST_DCN30_COMMON_RI(id) - -+void dcn35_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); - #endif /* _DCN35_RESOURCE_H_ */ -diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c -index 7e15d07df7a3..dc70b771633f 100644 ---- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c -@@ -1753,9 +1753,11 @@ static enum dc_status dcn351_validate_bandwidth(struct dc *dc, - { - bool out = false; - -+ DC_FP_START(); - out = dml2_validate(dc, context, - context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, - validate_mode); -+ DC_FP_END(); - - if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) - return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; -@@ -1782,6 +1784,12 @@ static int populate_dml_pipes_from_context_fpu(struct dc *dc, - - } - -+static void dcn351_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+{ -+ DC_FP_START(); -+ dcn351_update_bw_bounding_box_fpu(dc, bw_params); -+ DC_FP_END(); -+} - static struct resource_funcs dcn351_res_pool_funcs = { - .destroy = dcn351_destroy_resource_pool, - .link_enc_create = dcn35_link_encoder_create, -@@ -1803,7 +1811,7 @@ static struct resource_funcs dcn351_res_pool_funcs = { - .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, - .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, - .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, -- .update_bw_bounding_box = dcn351_update_bw_bounding_box_fpu, -+ .update_bw_bounding_box = dcn351_update_bw_bounding_box, - .patch_unknown_plane_state = dcn35_patch_unknown_plane_state, - .get_panel_config_defaults = dcn35_get_panel_config_defaults, - .get_preferred_eng_id_dpia = dcn351_get_preferred_eng_id_dpia, -diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c -index 83fee2ca61bf..2667a2e8b04f 100644 ---- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c -@@ -1760,9 +1760,11 @@ static enum dc_status dcn35_validate_bandwidth(struct dc *dc, - { - bool out = false; - -+ DC_FP_START(); - out = dml2_validate(dc, context, - context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, - validate_mode); -+ DC_FP_END(); - - if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) - return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; -@@ -1810,7 +1812,7 @@ static struct resource_funcs dcn36_res_pool_funcs = { - .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, - .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, - .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, -- .update_bw_bounding_box = dcn35_update_bw_bounding_box_fpu, -+ .update_bw_bounding_box = dcn35_update_bw_bounding_box, - .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, - .get_panel_config_defaults = dcn35_get_panel_config_defaults, - .get_preferred_eng_id_dpia = dcn36_get_preferred_eng_id_dpia, -diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c -index e37aab939a41..237d1a561da7 100644 ---- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c -@@ -1643,8 +1643,10 @@ static struct dc_cap_funcs cap_funcs = { - .get_subvp_en = dcn32_subvp_in_use, - }; - --static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+static void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) - { -+ dc_assert_fp_enabled(); -+ - /* re-calculate the available MALL size if required */ - if (bw_params->num_channels > 0) { - dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall( -@@ -1653,17 +1655,19 @@ static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b - dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; - } - +-} +- +-static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config) +-{ +- +- dml_ctx->architecture = dml2_architecture_21; +- +- dml21_populate_configuration_options(in_dc, dml_ctx, config); +- - DC_FP_START(); - - if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2) - dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); - - if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source) - dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source); -+} - -+static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+{ -+ DC_FP_START(); -+ dcn401_update_bw_bounding_box_fpu(dc, bw_params); - DC_FP_END(); - } +- dml21_populate_dml_init_params(&dml_ctx->v21.dml_init, &dml_ctx->config, in_dc); +- +- dml2_initialize_instance(&dml_ctx->v21.dml_init); +- +- DC_FP_END(); +-} - - enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state) + bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) { - plane_state->tiling_info.gfxversion = DcGfxAddr3; -@@ -1688,10 +1692,13 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, - } - } - -- if (dc->debug.using_dml2) -+ if (dc->debug.using_dml2) { -+ DC_FP_START(); - status = dml2_validate(dc, context, - context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, - validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; -+ DC_FP_END(); -+ } - - if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) { - /* check new stream configuration still supports cursor if subvp used */ -@@ -1710,10 +1717,13 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, + /* Allocate memory for initializing DML21 instance */ +- if (!dml21_allocate_memory(dml_ctx)) { ++ if (!dml21_allocate_memory(dml_ctx)) + return false; +- } - if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) { - /* attempt to validate again with subvp disabled due to cursor */ -- if (dc->debug.using_dml2) -+ if (dc->debug.using_dml2) { -+ DC_FP_START(); - status = dml2_validate(dc, context, - context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2, - validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; -+ DC_FP_END(); -+ } - } + dml21_init(in_dc, *dml_ctx, config); - return status; -@@ -1722,9 +1732,13 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, - void dcn401_prepare_mcache_programming(struct dc *dc, - struct dc_state *context) - { -- if (dc->debug.using_dml21) -+ if (dc->debug.using_dml21) { -+ DC_FP_START(); - dml2_prepare_mcache_programming(dc, context, -- context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); -+ context->power_source == DC_POWER_SOURCE_DC ? -+ context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); -+ DC_FP_END(); -+ } +@@ -90,337 +61,6 @@ void dml21_destroy(struct dml2_context *dml2) + vfree(dml2->v21.mode_programming.programming); } - static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) -diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c -new file mode 100644 -index 000000000000..b9532ebcced4 ---- /dev/null -+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c -@@ -0,0 +1,2355 @@ -+// SPDX-License-Identifier: MIT -+// -+// Copyright 2026 Advanced Micro Devices, Inc. -+ -+#include "dm_services.h" -+#include "dc.h" -+ -+#include "dcn32/dcn32_init.h" -+#include "dcn42/dcn42_init.h" -+ -+#include "resource.h" -+#include "include/irq_service_interface.h" -+ -+#include "dcn42_resource.h" -+#include "dcn42_resource_fpu.h" -+#include "dcn20/dcn20_resource.h" -+#include "dcn30/dcn30_resource.h" -+#include "dcn31/dcn31_resource.h" -+#include "dcn32/dcn32_resource.h" -+#include "dcn35/dcn35_resource.h" -+#include "dcn321/dcn321_resource.h" -+#include "dcn401/dcn401_resource.h" -+ -+#include "dcn10/dcn10_ipp.h" -+#include "dcn35/dcn35_hubbub.h" -+#include "dcn42/dcn42_hubbub.h" -+#include "dcn401/dcn401_mpc.h" -+#include "dcn42/dcn42_mpc.h" -+#include "dcn35/dcn35_hubp.h" -+#include "dcn42/dcn42_hubp.h" -+#include "irq/dcn42/irq_service_dcn42.h" -+#include "dcn42/dcn42_dpp.h" -+#include "dcn401/dcn401_dsc.h" -+#include "dcn42/dcn42_optc.h" -+#include "dcn20/dcn20_hwseq.h" -+#include "dcn30/dcn30_hwseq.h" -+#include "dce110/dce110_hwseq.h" -+#include "dcn35/dcn35_opp.h" -+#include "dcn30/dcn30_vpg.h" -+#include "dcn31/dcn31_vpg.h" -+#include "dcn42/dcn42_dio_stream_encoder.h" -+#include "dcn42/dcn42_pg_cntl.h" -+#include "dcn31/dcn31_hpo_dp_stream_encoder.h" -+#include "dcn31/dcn31_hpo_dp_link_encoder.h" -+#include "dcn32/dcn32_hpo_dp_link_encoder.h" -+#include "dcn42/dcn42_hpo_dp_link_encoder.h" -+#include "dcn31/dcn31_apg.h" -+#include "dcn31/dcn31_dio_link_encoder.h" -+#include "dcn401/dcn401_dio_link_encoder.h" -+#include "dcn10/dcn10_link_encoder.h" -+#include "dcn321/dcn321_dio_link_encoder.h" -+#include "dce/dce_clock_source.h" -+#include "dce/dce_audio.h" -+#include "dce/dce_hwseq.h" -+#include "clk_mgr.h" -+#include "dio/virtual/virtual_stream_encoder.h" -+#include "dml/display_mode_vba.h" -+#include "dcn42/dcn42_dccg.h" -+#include "dcn10/dcn10_resource.h" -+#include "link_service.h" -+#include "dcn31/dcn31_panel_cntl.h" -+ -+#include "dcn30/dcn30_dwb.h" -+#include "dcn42/dcn42_mmhubbub.h" -+#include "dcn42/dcn42_dio_link_encoder.h" -+ -+#include "dcn/dcn_4_2_0_offset.h" -+#include "dcn/dcn_4_2_0_sh_mask.h" -+#include "dpcs/dpcs_4_0_0_offset.h" -+#include "dpcs/dpcs_4_0_0_sh_mask.h" -+ -+#include "reg_helper.h" -+#include "dce/dmub_abm.h" -+#include "dce/dmub_psr.h" -+#include "dce/dmub_replay.h" -+#include "dce/dce_aux.h" -+#include "dce/dce_i2c.h" -+ -+#include "dml/dcn30/display_mode_vba_30.h" -+#include "vm_helper.h" -+#include "dcn20/dcn20_vmid.h" -+ -+#include "dc_state_priv.h" -+#include "link_enc_cfg.h" -+ -+#include "dml2_0/dml2_wrapper.h" -+ -+#define regBIF_BX0_BIOS_SCRATCH_3 0x003b -+#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 -+#define regBIF_BX0_BIOS_SCRATCH_6 0x003e -+#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 -+ -+#define DC_LOGGER_INIT(logger) -+ -+enum dcn401_clk_src_array_id { -+ DCN401_CLK_SRC_PLL0, -+ DCN401_CLK_SRC_PLL1, -+ DCN401_CLK_SRC_PLL2, -+ DCN401_CLK_SRC_PLL3, -+ DCN401_CLK_SRC_PLL4, -+ DCN401_CLK_SRC_TOTAL -+}; -+ -+/* begin -+ * macros to expend register list macro defined in HW object header file -+ */ -+ -+/* DCN */ -+#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] -+ -+#define BASE(seg) BASE_INNER(seg) -+ -+#define SR(reg_name) \ -+ REG_STRUCT.reg_name = BASE(reg##reg_name##_BASE_IDX) + \ -+ reg##reg_name -+#define SR_ARR(reg_name, id) \ -+ REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \ -+ reg##reg_name -+#define SR_ARR_INIT(reg_name, id, value) \ -+ REG_STRUCT[id].reg_name = value -+ -+#define SRI(reg_name, block, id) \ -+ REG_STRUCT.reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ -+ reg##block##id##_##reg_name -+ -+#define SRI_ARR(reg_name, block, id) \ -+ REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ -+ reg##block##id##_##reg_name -+ -+/* -+ * Used when a reg_name would otherwise begin with an integer -+ */ -+#define SRI_ARR_US(reg_name, block, id) \ -+ REG_STRUCT[id].reg_name = BASE(reg##block##id##reg_name##_BASE_IDX) + \ -+ reg##block##id##reg_name -+#define SR_ARR_I2C(reg_name, id) \ -+ REG_STRUCT[id - 1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name -+ -+#define SRI_ARR_I2C(reg_name, block, id) \ -+ REG_STRUCT[id - 1].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ -+ reg##block##id##_##reg_name -+ -+ -+#define SRI_ARR_ALPHABET(reg_name, block, index, id) \ -+ REG_STRUCT[index].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ -+ reg##block##id##_##reg_name -+ -+#define SRI2(reg_name, block, id) \ -+ .reg_name = BASE(reg##reg_name##_BASE_IDX) + \ -+ reg##reg_name -+#define SRI2_ARR(reg_name, block, id) \ -+ REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \ -+ reg##reg_name -+ -+#define SRIR(var_name, reg_name, block, id) \ -+ .var_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ -+ reg##block##id##_##reg_name -+ -+#define SRII(reg_name, block, id) \ -+ REG_STRUCT.reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ -+ reg##block##id##_##reg_name -+ -+#define SRII_ARR_2(reg_name, block, id, inst) \ -+ REG_STRUCT[inst].reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ -+ reg##block##id##_##reg_name -+ -+#define SRII_MPC_RMU(reg_name, block, id) \ -+ .RMU##_##reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ -+ reg##block##id##_##reg_name -+ -+#define SRII_DWB(reg_name, temp_name, block, id) \ -+ REG_STRUCT.reg_name[id] = \ -+ BASE(reg##block##id##_##temp_name##_BASE_IDX) + \ -+ reg##block##id##_##temp_name -+ -+#define DCCG_SRII(reg_name, block, id) \ -+ REG_STRUCT.block##_##reg_name[id] = \ -+ BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ -+ reg##block##id##_##reg_name -+ -+#define SF_DWB2(reg_name, block, id, field_name, post_fix) \ -+ .field_name = reg_name##__##field_name##post_fix -+ -+#define VUPDATE_SRII(reg_name, block, id) \ -+ REG_STRUCT.reg_name[id] = BASE(reg##reg_name##_##block##id##_BASE_IDX) + \ -+ reg##reg_name##_##block##id -+ -+/* NBIO */ -+#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] -+ -+#define NBIO_BASE(seg) \ -+ NBIO_BASE_INNER(seg) -+ -+#define NBIO_SR(reg_name) \ -+ REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_##reg_name##_BASE_IDX) + \ -+ regBIF_BX0_##reg_name -+#define NBIO_SR_ARR(reg_name, id) \ -+ REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_##reg_name##_BASE_IDX) + \ -+ regBIF_BX0_##reg_name -+ -+#define CTX ctx -+#define REG(reg_name) \ -+ (ctx->dcn_reg_offsets[reg##reg_name##_BASE_IDX] + reg##reg_name) -+ -+static struct bios_registers bios_regs; -+ -+#define bios_regs_init() \ -+ NBIO_SR(BIOS_SCRATCH_3), \ -+ NBIO_SR(BIOS_SCRATCH_6) -+ -+#define clk_src_regs_init(index, pllid) \ -+ CS_COMMON_REG_LIST_DCN42_RI(index, pllid) -+ -+static struct dce110_clk_src_regs clk_src_regs[5]; -+ -+static const struct dce110_clk_src_shift cs_shift = { -+ CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) -+}; -+static const struct dce110_clk_src_mask cs_mask = { -+ CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) -+}; -+#define abm_regs_init(id) \ -+ ABM_DCN42_REG_LIST_RI(id) -+ -+static struct dce_abm_registers abm_regs[4]; -+ -+static const struct dce_abm_shift abm_shift = { -+ ABM_MASK_SH_LIST_DCN42(__SHIFT)}; -+ -+static const struct dce_abm_mask abm_mask = { -+ ABM_MASK_SH_LIST_DCN42(_MASK)}; -+ -+#define audio_regs_init(id) \ -+ AUD_COMMON_REG_LIST_RI(id) -+ -+static struct dce_audio_registers audio_regs[5]; -+ -+static const struct dce_audio_shift audio_shift = { -+ DCN42_AUD_COMMON_MASK_SH_LIST(__SHIFT) -+}; -+ -+static const struct dce_audio_mask audio_mask = { -+ DCN42_AUD_COMMON_MASK_SH_LIST(_MASK) -+}; -+ -+#define vpg_regs_init(id) \ -+ VPG_DCN401_REG_LIST_RI(id) -+ -+static struct dcn31_vpg_registers vpg_regs[10]; -+ -+static const struct dcn31_vpg_shift vpg_shift = { -+ DCN31_VPG_MASK_SH_LIST(__SHIFT)}; -+ -+static const struct dcn31_vpg_mask vpg_mask = { -+ DCN31_VPG_MASK_SH_LIST(_MASK)}; -+ -+#define apg_regs_init(id) \ -+ APG_DCN31_REG_LIST_RI(id) -+ -+static struct dcn31_apg_registers apg_regs[10]; -+ -+static const struct dcn31_apg_shift apg_shift = { -+ DCN31_APG_MASK_SH_LIST(__SHIFT)}; -+ -+static const struct dcn31_apg_mask apg_mask = { -+ DCN31_APG_MASK_SH_LIST(_MASK)}; -+ -+#define stream_enc_regs_init(id) \ -+ SE_DCN42_REG_LIST_RI(id) -+ -+static struct dcn10_stream_enc_registers stream_enc_regs[5]; -+ -+static const struct dcn10_stream_encoder_shift se_shift = { -+ SE_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; -+ -+static const struct dcn10_stream_encoder_mask se_mask = { -+ SE_COMMON_MASK_SH_LIST_DCN42(_MASK)}; -+ -+#define aux_regs_init(id) \ -+ DCN2_AUX_REG_LIST_RI(id) -+ -+static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; -+ -+#define hpd_regs_init(id) \ -+ HPD_REG_LIST_RI(id) -+ -+static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; -+ -+#define link_regs_init(id, phyid) \ -+ LE_DCN401_REG_LIST_RI(id) -+ -+static struct dcn10_link_enc_registers link_enc_regs[5]; -+ -+static const struct dcn10_link_enc_shift le_shift = { -+ LINK_ENCODER_MASK_SH_LIST_DCN42(__SHIFT)}; -+ -+static const struct dcn10_link_enc_mask le_mask = { -+ LINK_ENCODER_MASK_SH_LIST_DCN42(_MASK)}; -+ -+#define hpo_dp_stream_encoder_reg_init(id) \ -+ DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id) -+ -+static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; -+ -+static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { -+ DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)}; -+ -+static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { -+ DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)}; -+ -+#define hpo_dp_link_encoder_reg_init(id) \ -+ DCN42_HPO_DP_LINK_ENC_REG_LIST_RI(id) -+ -+static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4]; -+ -+static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { -+ DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)}; -+ -+static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { -+ DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)}; -+ -+#define dpp_regs_init(id) \ -+ DPP_REG_LIST_DCN42_COMMON_RI(id) -+ -+static struct dcn42_dpp_registers dpp_regs[4]; -+ -+static const struct dcn42_dpp_shift tf_shift = { -+ DPP_REG_LIST_SH_MASK_DCN42_COMMON(__SHIFT)}; -+ -+static const struct dcn42_dpp_mask tf_mask = { -+ DPP_REG_LIST_SH_MASK_DCN42_COMMON(_MASK)}; -+ -+#define opp_regs_init(id) \ -+ OPP_REG_LIST_DCN401_RI(id) -+ -+static struct dcn20_opp_registers opp_regs[4]; -+ -+static const struct dcn20_opp_shift opp_shift = { -+ OPP_MASK_SH_LIST_DCN20(__SHIFT)}; -+ -+static const struct dcn20_opp_mask opp_mask = { -+ OPP_MASK_SH_LIST_DCN20(_MASK)}; -+ -+#define aux_engine_regs_init(id) \ -+ AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ -+ SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ -+ SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ -+ SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) -+ -+static struct dce110_aux_registers aux_engine_regs[5]; -+ -+static const struct dce110_aux_registers_shift aux_shift = { -+ DCN_AUX_MASK_SH_LIST(__SHIFT)}; -+ -+static const struct dce110_aux_registers_mask aux_mask = { -+ DCN_AUX_MASK_SH_LIST(_MASK)}; -+ -+#define dwbc_regs_dcn401_init(id) \ -+ DWBC_COMMON_REG_LIST_DCN30_RI(id) -+ -+static struct dcn30_dwbc_registers dwbc401_regs[1]; -+ -+static const struct dcn30_dwbc_shift dwbc401_shift = { -+ DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)}; -+ -+static const struct dcn30_dwbc_mask dwbc401_mask = { -+ DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)}; -+ -+#define mcif_wb_regs_dcn3_init(id) \ -+ MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id) -+ -+static struct dcn35_mmhubbub_registers mcif_wb35_regs[1]; -+ -+static const struct dcn35_mmhubbub_shift mcif_wb35_shift = { -+ MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)}; -+ -+static const struct dcn35_mmhubbub_mask mcif_wb35_mask = { -+ MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)}; -+ -+#define dsc_regs_init(id) \ -+ DSC_REG_LIST_DCN401_RI(id) -+ -+static struct dcn401_dsc_registers dsc_regs[4]; -+ -+static const struct dcn401_dsc_shift dsc_shift = { -+ DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)}; -+ -+static const struct dcn401_dsc_mask dsc_mask = { -+ DSC_REG_LIST_SH_MASK_DCN401(_MASK)}; -+ -+static struct dcn42_mpc_registers mpc_regs; -+ -+#define dcn_mpc_regs_init() \ -+ MPC_REG_LIST_DCN42(0), \ -+ MPC_REG_LIST_DCN42(1), \ -+ MPC_REG_LIST_DCN42(2), \ -+ MPC_REG_LIST_DCN42(3), \ -+ MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0), \ -+ MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1), \ -+ MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2), \ -+ MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3), \ -+ MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0), \ -+ MPC_RMCM_REG_LIST_DCN42(0), \ -+ MPC_RMCM_REG_LIST_DCN42(1) -+ -+static const struct dcn42_mpc_shift mpc_shift = { -+ MPC_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; -+ -+static const struct dcn42_mpc_mask mpc_mask = { -+ MPC_COMMON_MASK_SH_LIST_DCN42(_MASK)}; -+ -+#define optc_regs_init(id) \ -+ OPTC_COMMON_REG_LIST_DCN42_RI(id) -+ -+static struct dcn_optc_registers optc_regs[4]; -+ -+static const struct dcn_optc_shift optc_shift = { -+ OPTC_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; -+ -+static const struct dcn_optc_mask optc_mask = { -+ OPTC_COMMON_MASK_SH_LIST_DCN42(_MASK)}; -+ -+#define hubp_regs_init(id) \ -+ HUBP_REG_LIST_DCN42_RI(id) -+ -+static struct dcn_hubp2_registers hubp_regs[4]; -+ -+static const struct dcn_hubp2_shift hubp_shift = { -+ HUBP_MASK_SH_LIST_DCN42(__SHIFT)}; -+ -+static const struct dcn_hubp2_mask hubp_mask = { -+ HUBP_MASK_SH_LIST_DCN42(_MASK)}; -+ -+static struct dcn_hubbub_registers hubbub_reg; -+ -+#define hubbub_reg_init() \ -+ HUBBUB_REG_LIST_DCN42(0) -+ -+static const struct dcn_hubbub_shift hubbub_shift = { -+ HUBBUB_MASK_SH_LIST_DCN4_2(__SHIFT)}; -+ -+static const struct dcn_hubbub_mask hubbub_mask = { -+ HUBBUB_MASK_SH_LIST_DCN4_2(_MASK)}; -+ -+static struct dccg_registers dccg_regs; -+ -+#define dccg_regs_init() \ -+ DCCG_REG_LIST_DCN42_RI() -+ -+static const struct dccg_shift dccg_shift = { -+ DCCG_MASK_SH_LIST_DCN42(__SHIFT)}; -+ -+static const struct dccg_mask dccg_mask = { -+ DCCG_MASK_SH_LIST_DCN42(_MASK)}; -+ -+static struct pg_cntl_registers pg_cntl_regs; -+ -+#define pg_cntl_dcn42_regs_init() \ -+ PG_CNTL_REG_LIST_DCN42() -+ -+static const struct pg_cntl_shift pg_cntl_shift = { -+ PG_CNTL_MASK_SH_LIST_DCN42(__SHIFT) -+}; -+ -+static const struct pg_cntl_mask pg_cntl_mask = { -+ PG_CNTL_MASK_SH_LIST_DCN42(_MASK) -+}; -+#define SRII2(reg_name_pre, reg_name_post, id) \ -+ .reg_name_pre##_##reg_name_post[id] = \ -+ BASE(reg##reg_name_pre##id##_##reg_name_post##_BASE_IDX) + \ -+ reg##reg_name_pre##id##_##reg_name_post -+ -+#define HWSEQ_DCN42_REG_LIST() \ -+ SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ -+ SR(DIO_MEM_PWR_CTRL), \ -+ SR(ODM_MEM_PWR_CTRL3), \ -+ SR(MMHUBBUB_MEM_PWR_CNTL), \ -+ SR(DCCG_GATE_DISABLE_CNTL), \ -+ SR(DCCG_GATE_DISABLE_CNTL2), \ -+ SR(DCFCLK_CNTL), \ -+ SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ -+ SRII(PIXEL_RATE_CNTL, OTG, 0), \ -+ SRII(PIXEL_RATE_CNTL, OTG, 1), \ -+ SRII(PIXEL_RATE_CNTL, OTG, 2), \ -+ SRII(PIXEL_RATE_CNTL, OTG, 3),\ -+ SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0), \ -+ SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1), \ -+ SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2), \ -+ SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ -+ SR(MICROSECOND_TIME_BASE_DIV), \ -+ SR(MILLISECOND_TIME_BASE_DIV), \ -+ SR(DISPCLK_FREQ_CHANGE_CNTL), \ -+ SR(RBBMIF_TIMEOUT_DIS), \ -+ SR(RBBMIF_TIMEOUT_DIS_2), \ -+ SR(DCHUBBUB_CRC_CTRL), \ -+ SR(DPP_TOP0_DPP_CRC_CTRL), \ -+ SR(DPP_TOP0_DPP_CRC_VAL_R), \ -+ SR(DPP_TOP0_DPP_CRC_VAL_G), \ -+ SR(DPP_TOP0_DPP_CRC_VAL_B), \ -+ SR(MPC_CRC_CTRL), \ -+ SR(MPC_CRC_RESULT_R), \ -+ SR(MPC_CRC_RESULT_G), \ -+ SR(MPC_CRC_RESULT_B), \ -+ SR(MPC_CRC_RESULT_A), \ -+ SR(DOMAIN0_PG_CONFIG), \ -+ SR(DOMAIN1_PG_CONFIG), \ -+ SR(DOMAIN2_PG_CONFIG), \ -+ SR(DOMAIN3_PG_CONFIG), \ -+ SR(DOMAIN16_PG_CONFIG), \ -+ SR(DOMAIN17_PG_CONFIG), \ -+ SR(DOMAIN18_PG_CONFIG), \ -+ SR(DOMAIN19_PG_CONFIG), \ -+ SR(DOMAIN22_PG_CONFIG), \ -+ SR(DOMAIN23_PG_CONFIG), \ -+ SR(DOMAIN24_PG_CONFIG), \ -+ SR(DOMAIN25_PG_CONFIG), \ -+ SR(DOMAIN26_PG_CONFIG), \ -+ SR(DOMAIN0_PG_STATUS), \ -+ SR(DOMAIN1_PG_STATUS), \ -+ SR(DOMAIN2_PG_STATUS), \ -+ SR(DOMAIN3_PG_STATUS), \ -+ SR(DOMAIN16_PG_STATUS), \ -+ SR(DOMAIN17_PG_STATUS), \ -+ SR(DOMAIN18_PG_STATUS), \ -+ SR(DOMAIN19_PG_STATUS), \ -+ SR(DOMAIN22_PG_STATUS), \ -+ SR(DOMAIN23_PG_STATUS), \ -+ SR(DOMAIN24_PG_STATUS), \ -+ SR(DOMAIN25_PG_STATUS), \ -+ SR(DOMAIN26_PG_STATUS), \ -+ SR(DC_IP_REQUEST_CNTL), \ -+ SR(AZALIA_AUDIO_DTO), \ -+ SR(HPO_TOP_HW_CONTROL), \ -+ SR(AZALIA_CONTROLLER_CLOCK_GATING) -+ -+static struct dce_hwseq_registers hwseq_reg; -+ -+#define hwseq_reg_init() \ -+ HWSEQ_DCN42_REG_LIST() -+ -+#define HWSEQ_DCN42_MASK_SH_LIST(mask_sh) \ -+ HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ -+ HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ -+ HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ -+ HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ -+ HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ -+ HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DOMAIN26_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ -+ HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ -+ HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ -+ HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ -+ HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \ -+ HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ -+ HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ -+ HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ -+ HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\ -+ HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\ -+ HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\ -+ HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ -+ HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ -+ HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ -+ HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\ -+ HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ -+ HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\ -+ HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\ -+ HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK4_GATE_DISABLE, mask_sh),\ -+ HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK5_GATE_DISABLE, mask_sh) -+ -+static const struct dce_hwseq_shift hwseq_shift = { -+ HWSEQ_DCN42_MASK_SH_LIST(__SHIFT)}; -+ -+static const struct dce_hwseq_mask hwseq_mask = { -+ HWSEQ_DCN42_MASK_SH_LIST(_MASK)}; -+ -+#define vmid_regs_init(id) \ -+ DCN20_VMID_REG_LIST_RI(id) -+ -+static struct dcn_vmid_registers vmid_regs[16]; -+ -+static const struct dcn20_vmid_shift vmid_shifts = { -+ DCN20_VMID_MASK_SH_LIST(__SHIFT)}; -+ -+static const struct dcn20_vmid_mask vmid_masks = { -+ DCN20_VMID_MASK_SH_LIST(_MASK)}; -+ -+static const struct resource_caps res_cap_dcn42 = { -+ .num_timing_generator = 4, -+ .num_opp = 4, -+ .num_dpp = 4, -+ .num_video_plane = 4, -+ .num_audio = 5, -+ .num_stream_encoder = 5, -+ .num_dig_link_enc = 5, -+ .num_usb4_dpia = 6, -+ .num_hpo_dp_stream_encoder = 4, -+ .num_hpo_dp_link_encoder = 4, -+ .num_pll = 5, -+ .num_dwb = 1, -+ .num_ddc = 5, -+ .num_vmid = 16, -+ .num_mpc_3dlut = 2, -+ .num_dsc = 4, -+ .num_rmcm = 2, -+}; -+ -+static const struct dc_plane_cap plane_cap = { -+ .type = DC_PLANE_TYPE_DCN_UNIVERSAL, -+ .per_pixel_alpha = true, -+ -+ .pixel_format_support = { -+ .argb8888 = true, -+ .nv12 = true, -+ .fp16 = true, -+ .p010 = true, -+ .ayuv = false, -+ }, -+ -+ .max_upscale_factor = {.argb8888 = 16000, .nv12 = 16000, .fp16 = 16000}, -+ -+ // 6:1 downscaling ratio: 1000/6 = 166.666 -+ .max_downscale_factor = {.argb8888 = 167, .nv12 = 167, .fp16 = 167}, -+ -+ .min_width = 64, -+ .min_height = 64}; -+ -+static const struct dc_debug_options debug_defaults_drv = { -+ .disable_dmcu = true, -+ .force_abm_enable = false, -+ .clock_trace = true, -+ .disable_pplib_clock_request = false, -+ .disable_dpp_power_gate = true, -+ .disable_hubp_power_gate = true, -+ .disable_optc_power_gate = true, -+ .pipe_split_policy = MPC_SPLIT_AVOID, -+ .force_single_disp_pipe_split = false, -+ .disable_dcc = DCC_ENABLE, -+ .vsr_support = true, -+ .performance_trace = false, -+ .max_downscale_src_width = 4096, /*up to 4K for APU*/ -+ .disable_pplib_wm_range = false, -+ .scl_reset_length10 = true, -+ .sanity_checks = false, -+ .underflow_assert_delay_us = 0xFFFFFFFF, -+ .dwb_fi_phase = -1, // -1 = disable, -+ .dmub_command_table = true, -+ .pstate_enabled = true, -+ .enable_mem_low_power = { -+ .bits = { -+ .vga = false, -+ .i2c = true, -+ .dscl = true, -+ .cm = true, -+ .mpc = true, -+ .optc = true, -+ .vpg = true, -+ }}, -+ .root_clock_optimization = { -+ .bits = { -+ .dpp = true, -+ .dsc = true,/*dscclk and dsc pg*/ -+ .hdmistream = false, -+ .hdmichar = true, -+ .dpstream = true, -+ .symclk32_se = true, -+ .symclk32_le = true, -+ .symclk_fe = true, -+ .physymclk = false, -+ .dpiasymclk = true, -+ } -+ }, -+ .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT, -+ .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ -+ .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */ -+ .support_eDP1_5 = true, -+ .use_max_lb = true, -+ .force_disable_subvp = false, -+ .exit_idle_opt_for_cursor_updates = true, -+ .using_dml2 = true, -+ .using_dml21 = true, -+ .enable_single_display_2to1_odm_policy = true, -+ -+ // must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions -+ .enable_double_buffered_dsc_pg_support = true, -+ .enable_dp_dig_pixel_rate_div_policy = 1, -+ .allow_sw_cursor_fallback = false, -+ .psp_disabled_wa = true, -+ .alloc_extra_way_for_cursor = true, -+ .min_prefetch_in_strobe_ns = 60000, // 60us -+ .disable_unbounded_requesting = false, -+ .dcc_meta_propagation_delay_us = 10, -+ .disable_timeout = true, -+ .min_disp_clk_khz = 50000, -+ .static_screen_wait_frames = 2, -+ .disable_z10 = false, -+ .ignore_pg = true, -+ .disable_stutter_for_wm_program = true, -+ .min_deep_sleep_dcfclk_khz = 8000, -+ .replay_skip_crtc_disabled = true, -+ .psr_skip_crtc_disable = true, -+}; -+ -+static const struct dc_check_config config_defaults = { -+ .enable_legacy_fast_update = false, -+}; -+ -+static struct dce_aux *dcn42_aux_engine_create( -+ struct dc_context *ctx, -+ uint32_t inst) -+{ -+ struct aux_engine_dce110 *aux_engine = -+ kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); -+ -+ if (!aux_engine) -+ return NULL; -+ -+#undef REG_STRUCT -+#define REG_STRUCT aux_engine_regs -+ aux_engine_regs_init(0), -+ aux_engine_regs_init(1), -+ aux_engine_regs_init(2), -+ aux_engine_regs_init(3), -+ aux_engine_regs_init(4); -+ -+ dce110_aux_engine_construct(aux_engine, ctx, inst, -+ SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, -+ &aux_engine_regs[inst], -+ &aux_mask, -+ &aux_shift, -+ ctx->dc->caps.extended_aux_timeout_support); -+ -+ return &aux_engine->base; -+} -+ -+#define i2c_inst_regs_init(id) \ -+ I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) -+ -+static struct dce_i2c_registers i2c_hw_regs[5]; -+ -+static const struct dce_i2c_shift i2c_shifts = { -+ I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT) -+}; -+static const struct dce_i2c_mask i2c_masks = { -+ I2C_COMMON_MASK_SH_LIST_DCN35(_MASK) -+}; -+ -+/* ========================================================== */ -+ -+/* -+ * DPIA index | Preferred Encoder | Host Router -+ * 0 | C | 0 -+ * 1 | First Available | 0 -+ * 2 | D | 1 -+ * 3 | First Available | 1 -+ * 4 | E | 2 -+ * 5 | First Available | 2 -+ */ -+/* ========================================================== */ -+static const enum engine_id dpia_to_preferred_enc_id_table[] = { -+ ENGINE_ID_DIGC, -+ ENGINE_ID_DIGC, -+ ENGINE_ID_DIGD, -+ ENGINE_ID_DIGD, -+ ENGINE_ID_DIGE, -+ ENGINE_ID_DIGE -+}; -+ -+static enum engine_id dcn42_get_preferred_eng_id_dpia(unsigned int dpia_index) -+{ -+ return dpia_to_preferred_enc_id_table[dpia_index]; -+} -+ -+static struct dce_i2c_hw *dcn42_i2c_hw_create( -+ struct dc_context *ctx, -+ uint32_t inst) -+{ -+ struct dce_i2c_hw *dce_i2c_hw = -+ kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); -+ -+ if (!dce_i2c_hw) -+ return NULL; -+ -+#undef REG_STRUCT -+#define REG_STRUCT i2c_hw_regs -+ i2c_inst_regs_init(1), -+ i2c_inst_regs_init(2), -+ i2c_inst_regs_init(3), -+ i2c_inst_regs_init(4), -+ i2c_inst_regs_init(5); -+ dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, -+ &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); -+ -+ return dce_i2c_hw; -+} -+ -+static struct clock_source *dcn42_clock_source_create( -+ struct dc_context *ctx, -+ struct dc_bios *bios, -+ enum clock_source_id id, -+ const struct dce110_clk_src_regs *regs, -+ bool dp_clk_src) -+{ -+ struct dce110_clk_src *clk_src = -+ kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); -+ -+ if (!clk_src) -+ return NULL; -+ -+ if (dcn401_clk_src_construct(clk_src, ctx, bios, id, -+ regs, &cs_shift, &cs_mask)) { -+ clk_src->base.dp_clk_src = dp_clk_src; -+ return &clk_src->base; -+ } -+ -+ kfree(clk_src); -+ BREAK_TO_DEBUGGER(); -+ return NULL; -+} -+ -+static struct hubbub *dcn42_hubbub_create(struct dc_context *ctx) -+{ -+ int i; -+ -+ struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), -+ GFP_KERNEL); -+ -+ if (!hubbub3) -+ return NULL; -+ -+#undef REG_STRUCT -+#define REG_STRUCT hubbub_reg -+ hubbub_reg_init(); -+ -+#undef REG_STRUCT -+#define REG_STRUCT vmid_regs -+ vmid_regs_init(0), -+ vmid_regs_init(1), -+ vmid_regs_init(2), -+ vmid_regs_init(3), -+ vmid_regs_init(4), -+ vmid_regs_init(5), -+ vmid_regs_init(6), -+ vmid_regs_init(7), -+ vmid_regs_init(8), -+ vmid_regs_init(9), -+ vmid_regs_init(10), -+ vmid_regs_init(11), -+ vmid_regs_init(12), -+ vmid_regs_init(13), -+ vmid_regs_init(14), -+ vmid_regs_init(15); -+ -+ hubbub42_construct(hubbub3, ctx, -+ &hubbub_reg, -+ &hubbub_shift, -+ &hubbub_mask, -+ DCN42_DEFAULT_DET_SIZE, -+ 8, -+ DCN42_CRB_SIZE_KB); -+ for (i = 0; i < res_cap_dcn42.num_vmid; i++) { -+ struct dcn20_vmid *vmid = &hubbub3->vmid[i]; -+ -+ vmid->ctx = ctx; -+ -+ vmid->regs = &vmid_regs[i]; -+ vmid->shifts = &vmid_shifts; -+ vmid->masks = &vmid_masks; -+ } -+ -+ return &hubbub3->base; -+} -+ -+static struct hubp *dcn42_hubp_create( -+ struct dc_context *ctx, -+ uint32_t inst) -+{ -+ struct dcn20_hubp *hubp2 = -+ kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); -+ -+ if (!hubp2) -+ return NULL; -+ -+#undef REG_STRUCT -+#define REG_STRUCT hubp_regs -+ hubp_regs_init(0), -+ hubp_regs_init(1), -+ hubp_regs_init(2), -+ hubp_regs_init(3); -+ -+ if (hubp42_construct(hubp2, ctx, inst, -+ &hubp_regs[inst], &hubp_shift, &hubp_mask)) -+ return &hubp2->base; -+ -+ BREAK_TO_DEBUGGER(); -+ kfree(hubp2); -+ return NULL; -+} -+static const struct dc_panel_config dcn42_panel_config_defaults = { -+ .psr = { -+ .disable_psr = false, -+ .disallow_psrsu = false, -+ .disallow_replay = false, -+ }, -+ .ilr = { -+ .optimize_edp_link_rate = true, -+ }, -+}; -+ -+static void dcn42_dpp_destroy(struct dpp **dpp) -+{ -+ kfree(TO_DCN42_DPP(*dpp)); -+ *dpp = NULL; -+} -+ -+static struct dpp *dcn42_dpp_create( -+ struct dc_context *ctx, -+ uint32_t inst) -+{ -+ struct dcn42_dpp *dpp42 = -+ kzalloc(sizeof(struct dcn42_dpp), GFP_KERNEL); -+ -+ if (!dpp42) -+ return NULL; -+ -+#undef REG_STRUCT -+#define REG_STRUCT dpp_regs -+ dpp_regs_init(0), -+ dpp_regs_init(1), -+ dpp_regs_init(2), -+ dpp_regs_init(3); -+ -+ if (dpp42_construct(dpp42, ctx, inst, -+ &dpp_regs[inst], &tf_shift, &tf_mask)) -+ return &dpp42->base; -+ -+ BREAK_TO_DEBUGGER(); -+ kfree(dpp42); -+ return NULL; -+} -+ -+static struct mpc *dcn42_mpc_create( -+ struct dc_context *ctx, -+ int num_mpcc, -+ int num_rmu) -+{ -+ struct dcn42_mpc *mpc401 = kzalloc(sizeof(struct dcn42_mpc), -+ GFP_KERNEL); -+ -+ if (!mpc401) -+ return NULL; -+ -+#undef REG_STRUCT -+#define REG_STRUCT mpc_regs -+ dcn_mpc_regs_init(); -+ -+ dcn42_mpc_construct(mpc401, ctx, -+ &mpc_regs, -+ &mpc_shift, -+ &mpc_mask, -+ num_mpcc, -+ num_rmu); -+ -+ return &mpc401->base; -+} -+ -+static struct output_pixel_processor *dcn42_opp_create( -+ struct dc_context *ctx, uint32_t inst) -+{ -+ struct dcn20_opp *opp4 = -+ kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); -+ -+ if (!opp4) { -+ BREAK_TO_DEBUGGER(); -+ return NULL; -+ } -+ -+#undef REG_STRUCT -+#define REG_STRUCT opp_regs -+ opp_regs_init(0), -+ opp_regs_init(1), -+ opp_regs_init(2), -+ opp_regs_init(3); -+ dcn20_opp_construct(opp4, ctx, inst, -+ &opp_regs[inst], &opp_shift, &opp_mask); -+ return &opp4->base; -+} -+ -+static struct timing_generator *dcn42_timing_generator_create( -+ struct dc_context *ctx, -+ uint32_t instance) -+{ -+ struct optc *tgn10 = -+ kzalloc(sizeof(struct optc), GFP_KERNEL); -+ -+ if (!tgn10) -+ return NULL; -+#undef REG_STRUCT -+#define REG_STRUCT optc_regs -+ optc_regs_init(0), -+ optc_regs_init(1), -+ optc_regs_init(2), -+ optc_regs_init(3); -+ tgn10->base.inst = instance; -+ tgn10->base.ctx = ctx; -+ -+ tgn10->tg_regs = &optc_regs[instance]; -+ tgn10->tg_shift = &optc_shift; -+ tgn10->tg_mask = &optc_mask; -+ -+ dcn42_timing_generator_init(tgn10); -+ -+ return &tgn10->base; -+} -+ -+static const struct encoder_feature_support link_enc_feature = { -+ .max_hdmi_deep_color = COLOR_DEPTH_121212, -+ .max_hdmi_pixel_clock = 600000, -+ .hdmi_ycbcr420_supported = true, -+ .dp_ycbcr420_supported = true, -+ .fec_supported = true, -+ .flags.bits.IS_HBR2_CAPABLE = true, -+ .flags.bits.IS_HBR3_CAPABLE = true, -+ .flags.bits.IS_TPS3_CAPABLE = true, -+ .flags.bits.IS_TPS4_CAPABLE = true}; -+ -+static struct link_encoder *dcn42_link_encoder_create( -+ struct dc_context *ctx, -+ const struct encoder_init_data *enc_init_data) -+{ -+ struct dcn20_link_encoder *enc20 = -+ kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); -+ -+ if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) -+ return NULL; -+ -+#undef REG_STRUCT -+#define REG_STRUCT link_enc_aux_regs -+ aux_regs_init(0), -+ aux_regs_init(1), -+ aux_regs_init(2), -+ aux_regs_init(3), -+ aux_regs_init(4); -+#undef REG_STRUCT -+#define REG_STRUCT link_enc_hpd_regs -+ hpd_regs_init(0), -+ hpd_regs_init(1), -+ hpd_regs_init(2), -+ hpd_regs_init(3), -+ hpd_regs_init(4); -+#undef REG_STRUCT -+#define REG_STRUCT link_enc_regs -+ link_regs_init(0, A), -+ link_regs_init(1, B), -+ link_regs_init(2, C), -+ link_regs_init(3, D), -+ link_regs_init(4, E); -+ -+ dcn42_link_encoder_construct(enc20, -+ enc_init_data, -+ &link_enc_feature, -+ &link_enc_regs[enc_init_data->transmitter], -+ &link_enc_aux_regs[enc_init_data->channel - 1], -+ &link_enc_hpd_regs[enc_init_data->hpd_source], -+ &le_shift, -+ &le_mask); -+ return &enc20->enc10.base; -+} -+ -+static void read_dce_straps( -+ struct dc_context *ctx, -+ struct resource_straps *straps) -+{ -+ generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), -+ FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); -+} -+ -+static struct audio *dcn42_create_audio( -+ struct dc_context *ctx, unsigned int inst) -+{ -+ -+#undef REG_STRUCT -+#define REG_STRUCT audio_regs -+ audio_regs_init(0), -+ audio_regs_init(1), -+ audio_regs_init(2), -+ audio_regs_init(3), -+ audio_regs_init(4); -+ -+ return dce_audio_create(ctx, inst, -+ &audio_regs[inst], &audio_shift, &audio_mask); -+} -+ -+static struct vpg *dcn42_vpg_create( -+ struct dc_context *ctx, -+ uint32_t inst) -+{ -+ struct dcn31_vpg *vpg4 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); -+ -+ if (!vpg4) -+ return NULL; -+ -+#undef REG_STRUCT -+#define REG_STRUCT vpg_regs -+ vpg_regs_init(0), -+ vpg_regs_init(1), -+ vpg_regs_init(2), -+ vpg_regs_init(3), -+ vpg_regs_init(4), -+ vpg_regs_init(5), -+ vpg_regs_init(6), -+ vpg_regs_init(7), -+ vpg_regs_init(8), -+ vpg_regs_init(9); -+ vpg31_construct(vpg4, ctx, inst, -+ &vpg_regs[inst], -+ &vpg_shift, -+ &vpg_mask); -+ -+ return &vpg4->base; -+} -+ -+static struct apg *dcn42_apg_create( -+ struct dc_context *ctx, -+ uint32_t inst) -+{ -+ struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); -+ -+ if (!apg31) -+ return NULL; -+ -+#undef REG_STRUCT -+#define REG_STRUCT apg_regs -+ apg_regs_init(0), -+ apg_regs_init(1), -+ apg_regs_init(2), -+ apg_regs_init(3), -+ apg_regs_init(4), -+ apg_regs_init(5), -+ apg_regs_init(6), -+ apg_regs_init(7), -+ apg_regs_init(8), -+ apg_regs_init(9); -+ -+ apg31_construct(apg31, ctx, inst, -+ &apg_regs[inst], -+ &apg_shift, -+ &apg_mask); -+ -+ return &apg31->base; -+} -+ -+static struct stream_encoder *dcn42_stream_encoder_create( -+ enum engine_id eng_id, -+ struct dc_context *ctx) -+{ -+ struct dcn10_stream_encoder *enc1; -+ struct vpg *vpg; -+ struct apg *apg; -+ -+ uint32_t vpg_inst; -+ uint32_t apg_inst; -+ -+ /* Mapping of VPG, DME register blocks to DIO block instance */ -+ if (eng_id <= ENGINE_ID_DIGE) { -+ vpg_inst = eng_id; -+ apg_inst = eng_id; -+ } else -+ return NULL; -+ -+ enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); -+ vpg = dcn42_vpg_create(ctx, vpg_inst); -+ apg = dcn42_apg_create(ctx, apg_inst); -+ -+ if (!enc1 || !vpg || !apg) { -+ kfree(enc1); -+ kfree(vpg); -+ kfree(apg); -+ return NULL; -+ } -+#undef REG_STRUCT -+#define REG_STRUCT stream_enc_regs -+ stream_enc_regs_init(0), -+ stream_enc_regs_init(1), -+ stream_enc_regs_init(2), -+ stream_enc_regs_init(3), -+ stream_enc_regs_init(4); -+ -+ dcn42_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, -+ eng_id, vpg, apg, -+ &stream_enc_regs[eng_id], -+ &se_shift, &se_mask); -+ return &enc1->base; -+} -+ -+static struct hpo_dp_stream_encoder *dcn42_hpo_dp_stream_encoder_create( -+ enum engine_id eng_id, -+ struct dc_context *ctx) +-static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, +- struct dml2_context *in_ctx, unsigned int pipe_cnt) +-{ +- unsigned int dml_prog_idx = 0, dc_pipe_index = 0, num_dpps_required = 0; +- struct dml2_per_plane_programming *pln_prog = NULL; +- struct dml2_per_stream_programming *stream_prog = NULL; +- struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; +- struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; +- int num_pipes; +- unsigned int dml_phantom_prog_idx; +- +- context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; +- +- /* copy global DCHUBBUB arbiter registers */ +- memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.arb_regs, sizeof(struct dml2_display_arb_regs)); +- +- /* legacy only */ +- context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_regs.arb_regs.compbuf_size * 64; +- +- context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; +- context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; +- context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; +- +- /* phantom's start after main planes */ +- dml_phantom_prog_idx = in_ctx->v21.mode_programming.programming->display_config.num_planes; +- +- for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) { +- pln_prog = &in_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; +- +- if (!pln_prog->plane_descriptor) +- continue; +- +- stream_prog = &in_ctx->v21.mode_programming.programming->stream_programming[pln_prog->plane_descriptor->stream_index]; +- num_dpps_required = pln_prog->num_dpps_required; +- +- if (num_dpps_required == 0) { +- continue; +- } +- num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); +- +- if (num_pipes <= 0) +- continue; +- +- /* program each pipe */ +- for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { +- dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog); +- +- if (pln_prog->phantom_plane.valid && dc_phantom_pipes[dc_pipe_index]) { +- dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog); +- } +- } +- +- /* copy per plane mcache allocation */ +- memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx], &pln_prog->mcache_allocation, sizeof(struct dml2_mcache_surface_allocation)); +- if (pln_prog->phantom_plane.valid) { +- memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx], +- &pln_prog->phantom_plane.mcache_allocation, +- sizeof(struct dml2_mcache_surface_allocation)); +- +- dml_phantom_prog_idx++; +- } +- } +- +- /* assign global clocks */ +- context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; +- context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; +- if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { +- context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = +- in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000; +- } else { +- context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000; +- } +- +- if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { +- context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = +- in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000; +- } else { +- context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000; +- } +- +- /* get global mall allocation */ +- if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { +- context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes); +- } else { +- context->bw_ctx.bw.dcn.clk.num_ways = 0; +- } +-} +- +-static void dml21_prepare_mcache_params(struct dml2_context *dml_ctx, struct dc_state *context, struct dc_mcache_params *mcache_params) +-{ +- int dc_plane_idx = 0; +- int dml_prog_idx, stream_idx, plane_idx; +- struct dml2_per_plane_programming *pln_prog = NULL; +- +- for (stream_idx = 0; stream_idx < context->stream_count; stream_idx++) { +- for (plane_idx = 0; plane_idx < context->stream_status[stream_idx].plane_count; plane_idx++) { +- dml_prog_idx = map_plane_to_dml21_display_cfg(dml_ctx, context->streams[stream_idx]->stream_id, context->stream_status[stream_idx].plane_states[plane_idx], context); +- if (dml_prog_idx == INVALID) { +- continue; +- } +- pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; +- mcache_params[dc_plane_idx].valid = pln_prog->mcache_allocation.valid; +- mcache_params[dc_plane_idx].num_mcaches_plane0 = pln_prog->mcache_allocation.num_mcaches_plane0; +- mcache_params[dc_plane_idx].num_mcaches_plane1 = pln_prog->mcache_allocation.num_mcaches_plane1; +- mcache_params[dc_plane_idx].requires_dedicated_mall_mcache = pln_prog->mcache_allocation.requires_dedicated_mall_mcache; +- mcache_params[dc_plane_idx].last_slice_sharing.plane0_plane1 = pln_prog->mcache_allocation.last_slice_sharing.plane0_plane1; +- memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane0, +- pln_prog->mcache_allocation.mcache_x_offsets_plane0, +- sizeof(int) * (DML2_MAX_MCACHES + 1)); +- memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane1, +- pln_prog->mcache_allocation.mcache_x_offsets_plane1, +- sizeof(int) * (DML2_MAX_MCACHES + 1)); +- dc_plane_idx++; +- } +- } +-} +- +-static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) +-{ +- bool result = false; +- struct dml2_build_mode_programming_in_out *mode_programming = &dml_ctx->v21.mode_programming; +- struct dc_mcache_params mcache_params[MAX_PLANES] = {0}; +- +- memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); +- memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); +- memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out)); +- +- if (!context) +- return true; +- +- if (context->stream_count == 0) { +- dml21_init_min_clocks_for_dc_state(dml_ctx, context); +- dml21_build_fams2_programming(in_dc, context, dml_ctx); +- return true; +- } +- +- /* scrub phantom's from current dc_state */ +- dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); +- dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); +- +- /* Populate stream, plane mappings and other fields in display config. */ +- result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); +- if (!result) +- return false; +- +- DC_FP_START(); +- result = dml2_build_mode_programming(mode_programming); +- DC_FP_END(); +- if (!result) +- return false; +- +- /* Check and map HW resources */ +- if (result && !dml_ctx->config.skip_hw_state_mapping) { +- dml21_map_hw_resources(dml_ctx); +- dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, in_dc->current_state); +- /* if subvp phantoms are present, expand them into dc context */ +- dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx); +- +- if (in_dc->res_pool->funcs->program_mcache_pipe_config) { +- //Prepare mcache params for each plane based on mcache output from DML +- dml21_prepare_mcache_params(dml_ctx, context, mcache_params); +- +- //populate mcache regs to each pipe +- dml_ctx->config.callbacks.allocate_mcache(context, mcache_params); +- } +- } +- +- /* Copy DML CLK, WM and REG outputs to bandwidth context */ +- if (result && !dml_ctx->config.skip_hw_state_mapping) { +- dml21_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml_ctx, in_dc->res_pool->pipe_count); +- dml21_copy_clocks_to_dc_state(dml_ctx, context); +- dml21_extract_watermark_sets(in_dc, &context->bw_ctx.bw.dcn.watermarks, dml_ctx); +- dml21_build_fams2_programming(in_dc, context, dml_ctx); +- } +- +- return true; +-} +- +-static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) +-{ +- bool is_supported = false; +- struct dml2_initialize_instance_in_out *dml_init = &dml_ctx->v21.dml_init; +- struct dml2_check_mode_supported_in_out *mode_support = &dml_ctx->v21.mode_support; +- +- memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); +- memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); +- memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out)); +- +- if (!context || context->stream_count == 0) +- return true; +- +- /* Scrub phantom's from current dc_state */ +- dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); +- dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); +- +- mode_support->dml2_instance = dml_init->dml2_instance; +- dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); +- dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; +- DC_FP_START(); +- is_supported = dml2_check_mode_supported(mode_support); +- DC_FP_END(); +- if (!is_supported) +- return false; +- +- return true; +-} +- +-bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, +- enum dc_validate_mode validate_mode) +-{ +- bool out = false; +- +- /* Use dml21_check_mode_support for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */ +- if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) +- out = dml21_check_mode_support(in_dc, context, dml_ctx); +- else +- out = dml21_mode_check_and_programming(in_dc, context, dml_ctx); +- +- return out; +-} +- +-void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) +-{ +- unsigned int dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index; +- int num_pipes; +- struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; +- struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; +- +- struct dml2_per_plane_programming *pln_prog = NULL; +- struct dml2_plane_mcache_configuration_descriptor *mcache_config = NULL; +- struct prepare_mcache_programming_locals *l = &dml_ctx->v21.scratch.prepare_mcache_locals; +- +- if (context->stream_count == 0) { +- return; +- } +- +- memset(&l->build_mcache_programming_params, 0, sizeof(struct dml2_build_mcache_programming_in_out)); +- l->build_mcache_programming_params.dml2_instance = dml_ctx->v21.dml_init.dml2_instance; +- +- /* phantom's start after main planes */ +- dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes; +- +- /* Build mcache programming parameters per plane per pipe */ +- for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { +- pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; +- +- mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_prog_idx]; +- memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); +- mcache_config->plane_descriptor = pln_prog->plane_descriptor; +- mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx]; +- mcache_config->num_pipes = pln_prog->num_dpps_required; +- l->build_mcache_programming_params.num_configurations++; +- +- if (pln_prog->num_dpps_required == 0) { +- continue; +- } +- +- num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); +- if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || +- dc_main_pipes[0]->plane_state == NULL) +- continue; +- +- /* get config for each pipe */ +- for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { +- ASSERT(dc_main_pipes[dc_pipe_index]); +- dml21_get_pipe_mcache_config(context, dc_main_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); +- } +- +- /* get config for each phantom pipe */ +- if (pln_prog->phantom_plane.valid && +- dc_phantom_pipes[0] && +- dc_main_pipes[0]->stream && +- dc_phantom_pipes[0]->plane_state) { +- mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx]; +- memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); +- mcache_config->plane_descriptor = pln_prog->plane_descriptor; +- mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx]; +- mcache_config->num_pipes = pln_prog->num_dpps_required; +- l->build_mcache_programming_params.num_configurations++; +- +- for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { +- ASSERT(dc_phantom_pipes[dc_pipe_index]); +- dml21_get_pipe_mcache_config(context, dc_phantom_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); +- } +- +- /* increment phantom index */ +- dml_phantom_prog_idx++; +- } +- } +- +- /* Call to generate mcache programming per plane per pipe for the given display configuration */ +- dml2_build_mcache_programming(&l->build_mcache_programming_params); +- +- /* get per plane per pipe mcache programming */ +- for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { +- pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; +- +- num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); +- if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || +- dc_main_pipes[0]->plane_state == NULL) +- continue; +- +- /* get config for each pipe */ +- for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { +- ASSERT(dc_main_pipes[dc_pipe_index]); +- if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index]) { +- memcpy(&dc_main_pipes[dc_pipe_index]->mcache_regs, +- l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index], +- sizeof(struct dml2_hubp_pipe_mcache_regs)); +- } +- } +- +- /* get config for each phantom pipe */ +- if (pln_prog->phantom_plane.valid && +- dc_phantom_pipes[0] && +- dc_main_pipes[0]->stream && +- dc_phantom_pipes[0]->plane_state) { +- for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { +- ASSERT(dc_phantom_pipes[dc_pipe_index]); +- if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) { +- memcpy(&dc_phantom_pipes[dc_pipe_index]->mcache_regs, +- l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index], +- sizeof(struct dml2_hubp_pipe_mcache_regs)); +- } +- } +- /* increment phantom index */ +- dml_phantom_prog_idx++; +- } +- } +-} +- + void dml21_copy(struct dml2_context *dst_dml_ctx, + struct dml2_context *src_dml_ctx) + { +@@ -446,12 +86,8 @@ void dml21_copy(struct dml2_context *dst_dml_ctx, + + dst_dml_ctx->v21.mode_programming.programming = dst_dml2_programming; + +- DC_FP_START(); +- + /* need to initialize copied instance for internal references to be correct */ + dml2_initialize_instance(&dst_dml_ctx->v21.dml_init); +- +- DC_FP_END(); + } + + bool dml21_create_copy(struct dml2_context **dst_dml_ctx, +@@ -466,8 +102,3 @@ bool dml21_create_copy(struct dml2_context **dst_dml_ctx, + return true; + } + +-void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config) +-{ +- dml21_init(in_dc, dml_ctx, config); +-} +- +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h +index b508bbcc0e16..c4813c51251b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h +@@ -34,36 +34,6 @@ void dml21_copy(struct dml2_context *dst_dml_ctx, + struct dml2_context *src_dml_ctx); + bool dml21_create_copy(struct dml2_context **dst_dml_ctx, + struct dml2_context *src_dml_ctx); +-void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config); +- +-/** +- * dml21_validate - Determines if a display configuration is supported or not. +- * @in_dc: dc. +- * @context: dc_state to be validated. +- * @dml_ctx: dml21 context. +- * @validate_mode: DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX +- * will not populate context.res_ctx. +- * +- * Based on fast_validate option internally would call: +- * +- * -dml21_mode_check_and_programming - for DC_VALIDATE_MODE_AND_PROGRAMMING option +- * Calculates if dc_state can be supported on the input display +- * configuration. If supported, generates the necessary HW +- * programming for the new dc_state. +- * +- * -dml21_check_mode_support - for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX option +- * Calculates if dc_state can be supported for the input display +- * config. +- * +- * Context: Two threads may not invoke this function concurrently unless they reference +- * separate dc_states for validation. +- * Return: True if mode is supported, false otherwise. +- */ +-bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, +- enum dc_validate_mode validate_mode); +- +-/* Prepare hubp mcache_regs for hubp mcache ID and split coordinate programming */ +-void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx); + + /* Structure for inputting external SOCBB and DCNIP values for tool based debugging. */ + struct socbb_ip_params_external { +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c +new file mode 100644 +index 000000000000..d5885bbd14c4 +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c +@@ -0,0 +1,381 @@ ++// SPDX-License-Identifier: MIT ++// ++// Copyright 2024 Advanced Micro Devices, Inc. ++ ++#include "dml2_internal_types.h" ++#include "dml_top.h" ++#include "dml2_core_dcn4_calcs.h" ++#include "dml2_internal_shared_types.h" ++#include "dml21_utils.h" ++#include "dml21_translation_helper.h" ++#include "dml2_dc_resource_mgmt.h" ++#include "dml2_wrapper.h" ++#include "dml2_wrapper_fpu.h" ++#include "dml21_wrapper.h" ++#include "dml21_wrapper_fpu.h" ++ ++#define INVALID -1 ++ ++static void dml21_populate_configuration_options(const struct dc *in_dc, ++ struct dml2_context *dml_ctx, ++ const struct dml2_configuration_options *config) +{ -+ struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; -+ struct vpg *vpg; -+ struct apg *apg; -+ uint32_t hpo_dp_inst; -+ uint32_t vpg_inst; -+ uint32_t apg_inst; -+ -+ ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); -+ hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; -+ -+ /* Mapping of VPG register blocks to HPO DP block instance: -+ * VPG[5] -> HPO_DP[0] -+ * VPG[6] -> HPO_DP[1] -+ * VPG[7] -> HPO_DP[2] -+ * VPG[8] -> HPO_DP[3] -+ */ -+ vpg_inst = hpo_dp_inst + 5; -+ -+ /* Mapping of APG register blocks to HPO DP block instance: -+ * APG[6] -> HPO_DP[0] -+ * APG[7] -> HPO_DP[1] -+ * APG[8] -> HPO_DP[2] -+ * APG[9] -> HPO_DP[3] -+ */ -+ apg_inst = hpo_dp_inst + 5; -+ -+ /* allocate HPO stream encoder and create VPG sub-block */ -+ hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); -+ vpg = dcn42_vpg_create(ctx, vpg_inst); -+ apg = dcn42_apg_create(ctx, apg_inst); -+ -+ if (!hpo_dp_enc31 || !vpg || !apg) { -+ kfree(hpo_dp_enc31); -+ kfree(vpg); -+ kfree(apg); -+ return NULL; ++ dml_ctx->config = *config; ++ ++ /* UCLK P-State options */ ++ if (in_dc->debug.dml21_force_pstate_method) { ++ dml_ctx->config.pmo.force_pstate_method_enable = true; ++ for (int i = 0; i < MAX_PIPES; i++) ++ dml_ctx->config.pmo.force_pstate_method_values[i] = in_dc->debug.dml21_force_pstate_method_values[i]; ++ } else { ++ dml_ctx->config.pmo.force_pstate_method_enable = false; + } -+ -+#undef REG_STRUCT -+#define REG_STRUCT hpo_dp_stream_enc_regs -+ hpo_dp_stream_encoder_reg_init(0), -+ hpo_dp_stream_encoder_reg_init(1), -+ hpo_dp_stream_encoder_reg_init(2), -+ hpo_dp_stream_encoder_reg_init(3); -+ -+ dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, -+ hpo_dp_inst, eng_id, vpg, apg, -+ &hpo_dp_stream_enc_regs[hpo_dp_inst], -+ &hpo_dp_se_shift, &hpo_dp_se_mask); -+ -+ return &hpo_dp_enc31->base; -+} -+ -+static struct hpo_dp_link_encoder *dcn42_hpo_dp_link_encoder_create( -+ uint8_t inst, -+ struct dc_context *ctx) -+{ -+ struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; -+ -+ /* allocate HPO link encoder */ -+ hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); -+ if (!hpo_dp_enc31) -+ return NULL; /* out of memory */ -+ -+#undef REG_STRUCT -+#define REG_STRUCT hpo_dp_link_enc_regs -+ hpo_dp_link_encoder_reg_init(0), -+ hpo_dp_link_encoder_reg_init(1), -+ hpo_dp_link_encoder_reg_init(2), -+ hpo_dp_link_encoder_reg_init(3); -+ -+ hpo_dp_link_encoder42_construct(hpo_dp_enc31, ctx, inst, -+ &hpo_dp_link_enc_regs[inst], -+ &hpo_dp_le_shift, &hpo_dp_le_mask); -+ -+ return &hpo_dp_enc31->base; +} + -+static struct dce_hwseq *dcn42_hwseq_create( -+ struct dc_context *ctx) ++void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config) +{ -+ struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); ++ dml_ctx->architecture = dml2_architecture_21; + -+#undef REG_STRUCT -+#define REG_STRUCT hwseq_reg -+ hwseq_reg_init(); ++ dml21_populate_configuration_options(in_dc, dml_ctx, config); + -+ if (hws) { -+ hws->ctx = ctx; -+ hws->regs = &hwseq_reg; -+ hws->shifts = &hwseq_shift; -+ hws->masks = &hwseq_mask; -+ } ++ dml21_populate_dml_init_params(&dml_ctx->v21.dml_init, &dml_ctx->config, in_dc); + -+ return hws; ++ dml2_initialize_instance(&dml_ctx->v21.dml_init); +} + -+static const struct resource_create_funcs res_create_funcs = { -+ .read_dce_straps = read_dce_straps, -+ .create_audio = dcn42_create_audio, -+ .create_stream_encoder = dcn42_stream_encoder_create, -+ .create_hpo_dp_stream_encoder = dcn42_hpo_dp_stream_encoder_create, -+ .create_hpo_dp_link_encoder = dcn42_hpo_dp_link_encoder_create, -+ .create_hwseq = dcn42_hwseq_create, -+}; -+ -+static void dcn42_dsc_destroy(struct display_stream_compressor **dsc) ++void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config) +{ -+ kfree(container_of(*dsc, struct dcn401_dsc, base)); -+ *dsc = NULL; ++ dml21_init(in_dc, dml_ctx, config); +} + -+static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) ++static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, ++ struct dml2_context *in_ctx, unsigned int pipe_cnt) +{ -+ unsigned int i; ++ unsigned int dml_prog_idx = 0, dc_pipe_index = 0, num_dpps_required = 0; ++ struct dml2_per_plane_programming *pln_prog = NULL; ++ struct dml2_per_stream_programming *stream_prog = NULL; ++ struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; ++ struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; ++ int num_pipes; ++ unsigned int dml_phantom_prog_idx; + -+ for (i = 0; i < pool->base.stream_enc_count; i++) { -+ if (pool->base.stream_enc[i] != NULL) { -+ if (pool->base.stream_enc[i]->vpg != NULL) { -+ kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); -+ pool->base.stream_enc[i]->vpg = NULL; -+ } -+ if (pool->base.stream_enc[i]->apg != NULL) { -+ kfree(DCN31_APG_FROM_APG(pool->base.stream_enc[i]->apg)); -+ pool->base.stream_enc[i]->apg = NULL; -+ } -+ kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); -+ pool->base.stream_enc[i] = NULL; -+ } -+ } ++ context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; + -+ for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { -+ if (pool->base.hpo_dp_stream_enc[i] != NULL) { -+ if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { -+ kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); -+ pool->base.hpo_dp_stream_enc[i]->vpg = NULL; -+ } -+ if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { -+ kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); -+ pool->base.hpo_dp_stream_enc[i]->apg = NULL; -+ } -+ kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); -+ pool->base.hpo_dp_stream_enc[i] = NULL; -+ } -+ } ++ /* copy global DCHUBBUB arbiter registers */ ++ memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.arb_regs, sizeof(struct dml2_display_arb_regs)); + -+ for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { -+ if (pool->base.hpo_dp_link_enc[i] != NULL) { -+ kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); -+ pool->base.hpo_dp_link_enc[i] = NULL; -+ } -+ } ++ /* legacy only */ ++ context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_regs.arb_regs.compbuf_size * 64; + -+ for (i = 0; i < pool->base.res_cap->num_dsc; i++) { -+ if (pool->base.dscs[i] != NULL) -+ dcn42_dsc_destroy(&pool->base.dscs[i]); -+ } ++ context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; ++ context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; ++ context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; + -+ if (pool->base.mpc != NULL) { -+ kfree(TO_DCN20_MPC(pool->base.mpc)); -+ pool->base.mpc = NULL; -+ } -+ if (pool->base.hubbub != NULL) { -+ kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); -+ pool->base.hubbub = NULL; -+ } -+ for (i = 0; i < pool->base.pipe_count; i++) { -+ if (pool->base.dpps[i] != NULL) -+ dcn42_dpp_destroy(&pool->base.dpps[i]); ++ /* phantom's start after main planes */ ++ dml_phantom_prog_idx = in_ctx->v21.mode_programming.programming->display_config.num_planes; + -+ if (pool->base.ipps[i] != NULL) -+ pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); ++ for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) { ++ pln_prog = &in_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; + -+ if (pool->base.hubps[i] != NULL) { -+ kfree(TO_DCN20_HUBP(pool->base.hubps[i])); -+ pool->base.hubps[i] = NULL; -+ } ++ if (!pln_prog->plane_descriptor) ++ continue; + -+ if (pool->base.irqs != NULL) -+ dal_irq_service_destroy(&pool->base.irqs); -+ } ++ stream_prog = &in_ctx->v21.mode_programming.programming->stream_programming[pln_prog->plane_descriptor->stream_index]; ++ num_dpps_required = pln_prog->num_dpps_required; + -+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) { -+ if (pool->base.engines[i] != NULL) -+ dce110_engine_destroy(&pool->base.engines[i]); -+ if (pool->base.hw_i2cs[i] != NULL) { -+ kfree(pool->base.hw_i2cs[i]); -+ pool->base.hw_i2cs[i] = NULL; -+ } -+ if (pool->base.sw_i2cs[i] != NULL) { -+ kfree(pool->base.sw_i2cs[i]); -+ pool->base.sw_i2cs[i] = NULL; ++ if (num_dpps_required == 0) { ++ continue; + } -+ } ++ num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); + -+ for (i = 0; i < pool->base.res_cap->num_opp; i++) { -+ if (pool->base.opps[i] != NULL) -+ pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); -+ } ++ if (num_pipes <= 0) ++ continue; + -+ for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { -+ if (pool->base.timing_generators[i] != NULL) { -+ kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); -+ pool->base.timing_generators[i] = NULL; -+ } -+ } ++ /* program each pipe */ ++ for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { ++ dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog); + -+ for (i = 0; i < pool->base.res_cap->num_dwb; i++) { -+ if (pool->base.dwbc[i] != NULL) { -+ kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); -+ pool->base.dwbc[i] = NULL; -+ } -+ if (pool->base.mcif_wb[i] != NULL) { -+ kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); -+ pool->base.mcif_wb[i] = NULL; ++ if (pln_prog->phantom_plane.valid && dc_phantom_pipes[dc_pipe_index]) { ++ dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog); ++ } + } -+ } -+ -+ for (i = 0; i < pool->base.audio_count; i++) { -+ if (pool->base.audios[i]) -+ dce_aud_destroy(&pool->base.audios[i]); -+ } + -+ for (i = 0; i < pool->base.clk_src_count; i++) { -+ if (pool->base.clock_sources[i] != NULL) { -+ dcn20_clock_source_destroy(&pool->base.clock_sources[i]); -+ pool->base.clock_sources[i] = NULL; -+ } -+ } ++ /* copy per plane mcache allocation */ ++ memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx], &pln_prog->mcache_allocation, sizeof(struct dml2_mcache_surface_allocation)); ++ if (pln_prog->phantom_plane.valid) { ++ memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx], ++ &pln_prog->phantom_plane.mcache_allocation, ++ sizeof(struct dml2_mcache_surface_allocation)); + -+ for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { -+ if (pool->base.mpc_lut[i] != NULL) { -+ dc_3dlut_func_release(pool->base.mpc_lut[i]); -+ pool->base.mpc_lut[i] = NULL; ++ dml_phantom_prog_idx++; + } -+ if (pool->base.mpc_shaper[i] != NULL) { -+ dc_transfer_func_release(pool->base.mpc_shaper[i]); -+ pool->base.mpc_shaper[i] = NULL; -+ } -+ } -+ -+ if (pool->base.dp_clock_source != NULL) { -+ dcn20_clock_source_destroy(&pool->base.dp_clock_source); -+ pool->base.dp_clock_source = NULL; + } + -+ for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { -+ if (pool->base.multiple_abms[i] != NULL) -+ dce_abm_destroy(&pool->base.multiple_abms[i]); ++ /* assign global clocks */ ++ context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; ++ context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; ++ if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { ++ context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = ++ in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000; ++ } else { ++ context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000; + } + -+ if (pool->base.psr != NULL) -+ dmub_psr_destroy(&pool->base.psr); -+ -+ if (pool->base.pg_cntl != NULL) -+ dcn_pg_cntl_destroy(&pool->base.pg_cntl); -+ if (pool->base.dccg != NULL) -+ dcn_dccg_destroy(&pool->base.dccg); -+ -+ if (pool->base.oem_device != NULL) { -+ struct dc *dc = pool->base.oem_device->ctx->dc; -+ -+ dc->link_srv->destroy_ddc_service(&pool->base.oem_device); ++ if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { ++ context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = ++ in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000; ++ } else { ++ context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000; + } -+} + -+static void dcn42_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) -+{ -+ const struct dc_stream_state *stream = pipe_ctx->stream; -+ struct dc_link *link = stream->link; -+ struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; -+ struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params; -+ -+ pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; -+ -+ if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) -+ pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz; -+ -+ if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) -+ link_enc = link_enc_cfg_get_link_enc(link); -+ if (link_enc) -+ pixel_clk_params->encoder_object_id = link_enc->id; -+ -+ pixel_clk_params->signal_type = pipe_ctx->stream->signal; -+ pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; -+ /* TODO: un-hardcode*/ -+ -+ /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */ -+ -+ pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * -+ LINK_RATE_REF_FREQ_IN_KHZ; -+ pixel_clk_params->flags.ENABLE_SS = 0; -+ pixel_clk_params->color_depth = -+ stream->timing.display_color_depth; -+ pixel_clk_params->flags.DISPLAY_BLANKED = 1; -+ pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; -+ -+ if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) -+ pixel_clk_params->color_depth = COLOR_DEPTH_888; -+ -+ if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) -+ pixel_clk_params->requested_pix_clk_100hz *= 2; -+ if (dc_is_tmds_signal(stream->signal) && -+ stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) -+ pixel_clk_params->requested_pix_clk_100hz /= 2; -+ -+ pipe_ctx->clock_source->funcs->get_pix_clk_dividers( -+ pipe_ctx->clock_source, -+ &pipe_ctx->stream_res.pix_clk_params, -+ &pipe_ctx->pll_settings); -+ -+ pixel_clk_params->dio_se_pix_per_cycle = 1; -+ if (dc_is_tmds_signal(stream->signal) && -+ stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { -+ pixel_clk_params->dio_se_pix_per_cycle = 2; -+ } else if (dc_is_dp_signal(stream->signal)) { -+ /* round up to nearest power of 2, or max at 8 pixels per cycle */ -+ if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { -+ pixel_clk_params->dio_se_pix_per_cycle = 8; -+ } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { -+ pixel_clk_params->dio_se_pix_per_cycle = 4; -+ } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { -+ pixel_clk_params->dio_se_pix_per_cycle = 2; -+ } else { -+ pixel_clk_params->dio_se_pix_per_cycle = 1; -+ } ++ /* get global mall allocation */ ++ if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { ++ context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes); ++ } else { ++ context->bw_ctx.bw.dcn.clk.num_ways = 0; + } +} + -+static bool dcn42_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) ++static void dml21_prepare_mcache_params(struct dml2_context *dml_ctx, struct dc_state *context, struct dc_mcache_params *mcache_params) +{ -+ int i; -+ uint32_t dwb_count = pool->res_cap->num_dwb; -+ -+ for (i = 0; i < dwb_count; i++) { -+ struct dcn30_dwbc *dwbc42 = kzalloc(sizeof(struct dcn30_dwbc), -+ GFP_KERNEL); -+ -+ if (!dwbc42) { -+ dm_error("DC: failed to create dwbc42!\n"); -+ return false; ++ int dc_plane_idx = 0; ++ int dml_prog_idx, stream_idx, plane_idx; ++ struct dml2_per_plane_programming *pln_prog = NULL; ++ ++ for (stream_idx = 0; stream_idx < context->stream_count; stream_idx++) { ++ for (plane_idx = 0; plane_idx < context->stream_status[stream_idx].plane_count; plane_idx++) { ++ dml_prog_idx = map_plane_to_dml21_display_cfg(dml_ctx, context->streams[stream_idx]->stream_id, context->stream_status[stream_idx].plane_states[plane_idx], context); ++ if (dml_prog_idx == INVALID) { ++ continue; ++ } ++ pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; ++ mcache_params[dc_plane_idx].valid = pln_prog->mcache_allocation.valid; ++ mcache_params[dc_plane_idx].num_mcaches_plane0 = pln_prog->mcache_allocation.num_mcaches_plane0; ++ mcache_params[dc_plane_idx].num_mcaches_plane1 = pln_prog->mcache_allocation.num_mcaches_plane1; ++ mcache_params[dc_plane_idx].requires_dedicated_mall_mcache = pln_prog->mcache_allocation.requires_dedicated_mall_mcache; ++ mcache_params[dc_plane_idx].last_slice_sharing.plane0_plane1 = pln_prog->mcache_allocation.last_slice_sharing.plane0_plane1; ++ memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane0, ++ pln_prog->mcache_allocation.mcache_x_offsets_plane0, ++ sizeof(int) * (DML2_MAX_MCACHES + 1)); ++ memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane1, ++ pln_prog->mcache_allocation.mcache_x_offsets_plane1, ++ sizeof(int) * (DML2_MAX_MCACHES + 1)); ++ dc_plane_idx++; + } -+ -+#undef REG_STRUCT -+#define REG_STRUCT dwbc401_regs -+ dwbc_regs_dcn401_init(0); -+ -+ dcn30_dwbc_construct(dwbc42, ctx, -+ &dwbc401_regs[i], -+ &dwbc401_shift, -+ &dwbc401_mask, -+ i); -+ -+ pool->dwbc[i] = &dwbc42->base; + } -+ return true; +} + -+static void dcn42_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, -+ struct dc_context *ctx) ++static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) +{ -+ dcn42_mmhubbub_set_fgcg( -+ mcif_wb30, -+ ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub); -+} ++ bool is_supported = false; ++ struct dml2_initialize_instance_in_out *dml_init = &dml_ctx->v21.dml_init; ++ struct dml2_check_mode_supported_in_out *mode_support = &dml_ctx->v21.mode_support; + -+static bool dcn42_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) -+{ -+ int i; -+ uint32_t pipe_count = pool->res_cap->num_dwb; ++ memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); ++ memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); ++ memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out)); + -+ for (i = 0; i < pipe_count; i++) { -+ struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), -+ GFP_KERNEL); ++ if (!context || context->stream_count == 0) ++ return true; + -+ if (!mcif_wb30) { -+ dm_error("DC: failed to create mcif_wb30!\n"); -+ return false; -+ } ++ /* Scrub phantom's from current dc_state */ ++ dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); ++ dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); + -+#undef REG_STRUCT -+#define REG_STRUCT mcif_wb35_regs -+ mcif_wb_regs_dcn3_init(0); ++ mode_support->dml2_instance = dml_init->dml2_instance; ++ dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); ++ dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; + -+ dcn35_mmhubbub_construct(mcif_wb30, ctx, -+ &mcif_wb35_regs[i], -+ &mcif_wb35_shift, -+ &mcif_wb35_mask, -+ i); ++ is_supported = dml2_check_mode_supported(mode_support); + -+ dcn42_mmhubbub_init(mcif_wb30, ctx); ++ if (!is_supported) ++ return false; + -+ pool->mcif_wb[i] = &mcif_wb30->base; -+ } + return true; +} + -+static struct display_stream_compressor *dcn42_dsc_create( -+ struct dc_context *ctx, uint32_t inst) ++static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) +{ -+ struct dcn401_dsc *dsc = -+ kzalloc(sizeof(struct dcn401_dsc), GFP_KERNEL); ++ bool result = false; ++ struct dml2_build_mode_programming_in_out *mode_programming = &dml_ctx->v21.mode_programming; ++ struct dc_mcache_params mcache_params[MAX_PLANES] = {0}; ++ ++ memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); ++ memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); ++ memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out)); ++ ++ if (!context) ++ return true; + -+ if (!dsc) { -+ BREAK_TO_DEBUGGER(); -+ return NULL; ++ if (context->stream_count == 0) { ++ dml21_init_min_clocks_for_dc_state(dml_ctx, context); ++ dml21_build_fams2_programming(in_dc, context, dml_ctx); ++ return true; + } + -+#undef REG_STRUCT -+#define REG_STRUCT dsc_regs -+ dsc_regs_init(0), -+ dsc_regs_init(1), -+ dsc_regs_init(2), -+ dsc_regs_init(3); ++ /* scrub phantom's from current dc_state */ ++ dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); ++ dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); + -+ dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); -+ dsc401_set_fgcg(dsc, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc); ++ /* Populate stream, plane mappings and other fields in display config. */ ++ result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); ++ if (!result) ++ return false; + -+ dsc->max_image_width = 5760; ++ result = dml2_build_mode_programming(mode_programming); + -+ return &dsc->base; -+} ++ if (!result) ++ return false; + -+static void dcn42_destroy_resource_pool(struct resource_pool **pool) -+{ -+ struct dcn42_resource_pool *dcn42_pool = TO_DCN42_RES_POOL(*pool); ++ /* Check and map HW resources */ ++ if (result && !dml_ctx->config.skip_hw_state_mapping) { ++ dml21_map_hw_resources(dml_ctx); ++ dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, in_dc->current_state); ++ /* if subvp phantoms are present, expand them into dc context */ ++ dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx); + -+ dcn42_resource_destruct(dcn42_pool); -+ kfree(dcn42_pool); -+ *pool = NULL; -+} ++ if (in_dc->res_pool->funcs->program_mcache_pipe_config) { ++ //Prepare mcache params for each plane based on mcache output from DML ++ dml21_prepare_mcache_params(dml_ctx, context, mcache_params); + -+static struct dc_cap_funcs cap_funcs = { -+ .get_dcc_compression_cap = dcn20_get_dcc_compression_cap}; ++ //populate mcache regs to each pipe ++ dml_ctx->config.callbacks.allocate_mcache(context, mcache_params); ++ } ++ } + -+static void dcn42_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) -+{ -+ dc_assert_fp_enabled(); ++ /* Copy DML CLK, WM and REG outputs to bandwidth context */ ++ if (result && !dml_ctx->config.skip_hw_state_mapping) { ++ dml21_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml_ctx, in_dc->res_pool->pipe_count); ++ dml21_copy_clocks_to_dc_state(dml_ctx, context); ++ dml21_extract_watermark_sets(in_dc, &context->bw_ctx.bw.dcn.watermarks, dml_ctx); ++ dml21_build_fams2_programming(in_dc, context, dml_ctx); ++ } + -+ if (dc->current_state && dc->current_state->bw_ctx.dml2) -+ dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); ++ return true; +} + -+static void dcn42_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+{ -+ DC_FP_START(); -+ dcn42_update_bw_bounding_box_fpu(dc, bw_params); -+ DC_FP_END(); -+} -+enum dc_status dcn42_validate_bandwidth(struct dc *dc, -+ struct dc_state *context, -+ enum dc_validate_mode validate_mode) ++bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, ++ enum dc_validate_mode validate_mode) +{ + bool out = false; + -+ DC_FP_START(); -+ -+ out = dml2_validate(dc, context, context->bw_ctx.dml2, -+ validate_mode); -+ -+ if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) { -+ /*not required for mode enumeration*/ -+ dcn42_decide_zstate_support(dc, context); -+ } -+ -+ DC_FP_END(); ++ /* Use dml21_check_mode_support for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */ ++ if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) ++ out = dml21_check_mode_support(in_dc, context, dml_ctx); ++ else ++ out = dml21_mode_check_and_programming(in_dc, context, dml_ctx); + -+ return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; -+} -+void dcn42_prepare_mcache_programming(struct dc *dc, -+ struct dc_state *context) -+{ -+ if (dc->debug.using_dml21) { -+ DC_FP_START(); -+ dml2_prepare_mcache_programming(dc, context, -+ context->power_source == DC_POWER_SOURCE_DC ? -+ context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); -+ DC_FP_END(); -+ } ++ return out; +} -+/* Create a minimal link encoder object not associated with a particular -+ * physical connector. -+ * resource_funcs.link_enc_create_minimal -+ */ -+static struct link_encoder *dcn42_link_enc_create_minimal( -+ struct dc_context *ctx, enum engine_id eng_id) -+{ -+ struct dcn20_link_encoder *enc20; -+ -+ if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) -+ return NULL; + -+ enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); -+ if (!enc20) -+ return NULL; -+ -+ dcn31_link_encoder_construct_minimal( -+ enc20, -+ ctx, -+ &link_enc_feature, -+ &link_enc_regs[eng_id - ENGINE_ID_DIGA], -+ eng_id); -+ -+ return &enc20->enc10.base; -+} -+static void dcn42_get_panel_config_defaults(struct dc_panel_config *panel_config) -+{ -+ *panel_config = dcn42_panel_config_defaults; -+} -+static unsigned int dcn42_get_max_hw_cursor_size(const struct dc *dc, -+ struct dc_state *state, -+ const struct dc_stream_state *stream) -+{ -+ return dc->caps.max_cursor_size; -+} -+static struct resource_funcs dcn42_res_pool_funcs = { -+ .destroy = dcn42_destroy_resource_pool, -+ .link_enc_create = dcn42_link_encoder_create, -+ .link_enc_create_minimal = dcn42_link_enc_create_minimal, -+ .link_encs_assign = link_enc_cfg_link_encs_assign, -+ .link_enc_unassign = link_enc_cfg_link_enc_unassign, -+ .panel_cntl_create = dcn32_panel_cntl_create, -+ .validate_bandwidth = dcn42_validate_bandwidth, -+ .calculate_wm_and_dlg = NULL, -+ .populate_dml_pipes = NULL, -+ .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe, -+ .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, -+ .release_pipe = dcn20_release_pipe, -+ .add_stream_to_ctx = dcn30_add_stream_to_ctx, -+ .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -+ .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, -+ .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, -+ .set_mcif_arb_params = dcn30_set_mcif_arb_params, -+ .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, -+ .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, -+ .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, -+ .update_bw_bounding_box = dcn42_update_bw_bounding_box, -+ .patch_unknown_plane_state = dcn35_patch_unknown_plane_state, -+ .get_panel_config_defaults = dcn42_get_panel_config_defaults, -+ .get_preferred_eng_id_dpia = dcn42_get_preferred_eng_id_dpia, -+ .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, -+ .add_phantom_pipes = dcn32_add_phantom_pipes, -+ .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, -+ .prepare_mcache_programming = dcn42_prepare_mcache_programming, -+ .build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params, -+ .get_power_profile = dcn401_get_power_profile, -+ .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe, -+ .get_max_hw_cursor_size = dcn42_get_max_hw_cursor_size, -+ .get_default_tiling_info = dcn10_get_default_tiling_info -+}; -+ -+static uint32_t read_pipe_fuses(struct dc_context *ctx) ++void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) +{ -+ uint32_t value = REG_READ(CC_DC_PIPE_DIS); -+ -+ if (value == 0 && ctx->dce_environment == DCE_ENV_DIAG) -+ value = 0xF; -+ /* DCN401 support max 4 pipes */ -+ value = value & 0xf; -+ return value; -+} ++ unsigned int dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index; ++ int num_pipes; ++ struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; ++ struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; + -+static bool dcn42_resource_construct( -+ uint8_t num_virtual_links, -+ struct dc *dc, -+ struct dcn42_resource_pool *pool) -+{ -+ int i, j; -+ struct dc_context *ctx = dc->ctx; -+ struct irq_service_init_data init_data; -+ uint32_t pipe_fuses; -+ uint32_t num_pipes; -+ -+#undef REG_STRUCT -+#define REG_STRUCT bios_regs -+ bios_regs_init(); -+ -+#undef REG_STRUCT -+#define REG_STRUCT clk_src_regs -+ clk_src_regs_init(0, A), -+ clk_src_regs_init(1, B), -+ clk_src_regs_init(2, C), -+ clk_src_regs_init(3, D), -+ clk_src_regs_init(4, E); -+ -+#undef REG_STRUCT -+#define REG_STRUCT abm_regs -+ abm_regs_init(0), -+ abm_regs_init(1), -+ abm_regs_init(2), -+ abm_regs_init(3); -+#undef REG_STRUCT -+#define REG_STRUCT dccg_regs -+ dccg_regs_init(); -+ -+ ctx->dc_bios->regs = &bios_regs; -+ -+ pool->base.res_cap = &res_cap_dcn42; -+ -+ /* max number of pipes for ASIC before checking for pipe fuses */ -+ num_pipes = pool->base.res_cap->num_dpp; -+ pipe_fuses = read_pipe_fuses(ctx); -+ -+ for (i = 0; i < pool->base.res_cap->num_dpp; i++) -+ if (pipe_fuses & 1 << i) -+ num_pipes--; -+ -+ if (pipe_fuses & 1) -+ ASSERT(0); // Unexpected - Pipe 0 should always be fully functional! -+ -+ if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) -+ ASSERT(0); // Entire DCN is harvested! -+ -+ pool->base.funcs = &dcn42_res_pool_funcs; -+ -+ /************************************************* -+ * Resource + asic cap harcoding * -+ *************************************************/ -+ pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE; -+ pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; -+ pool->base.pipe_count = num_pipes; -+ pool->base.mpcc_count = num_pipes; -+ dc->caps.ips_v2_support = true; -+ dc->caps.max_downscale_ratio = 600; -+ dc->caps.i2c_speed_in_khz = 100; -+ dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ -+ /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ -+ dc->caps.max_cursor_size = 64; -+ dc->caps.max_buffered_cursor_size = 64; -+ dc->caps.cursor_not_scaled = true; -+ dc->caps.min_horizontal_blanking_period = 80; -+ dc->caps.dmdata_alloc_size = 2048; -+ dc->caps.mall_size_per_mem_channel = 4; -+ /* total size = mall per channel * num channels * 1024 * 1024 */ -+ dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * -+ dc->ctx->dc_bios->vram_info.num_chans * 1048576; -+ dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; -+ dc->caps.cache_line_size = 64; -+ dc->caps.cache_num_ways = 16; -+ -+ /* Calculate the available MALL space */ -+ dc->caps.max_cab_allocation_bytes = -+ dcn32_calc_num_avail_chans_for_mall(dc, dc->ctx->dc_bios->vram_info.num_chans) * -+ dc->caps.mall_size_per_mem_channel * 1024 * 1024; -+ dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; -+ -+ dc->caps.subvp_fw_processing_delay_us = 15; -+ dc->caps.subvp_drr_max_vblank_margin_us = 40; -+ dc->caps.subvp_prefetch_end_to_mall_start_us = 15; -+ dc->caps.subvp_swath_height_margin_lines = 16; -+ dc->caps.subvp_pstate_allow_width_us = 20; -+ dc->caps.subvp_vertical_int_margin_us = 30; -+ dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin -+ -+ dc->caps.max_slave_planes = 2; -+ dc->caps.max_slave_yuv_planes = 2; -+ dc->caps.max_slave_rgb_planes = 2; -+ dc->caps.post_blend_color_processing = true; -+ dc->caps.force_dp_tps4_for_cp2520 = true; -+ if (dc->config.forceHBR2CP2520) -+ dc->caps.force_dp_tps4_for_cp2520 = false; -+ dc->caps.dp_hdmi21_pcon_support = true; -+ dc->caps.dp_hpo = true; -+ dc->caps.edp_dsc_support = true; -+ dc->caps.extended_aux_timeout_support = true; -+ dc->caps.dmcub_support = true; -+ dc->caps.is_apu = true; -+ dc->caps.seamless_odm = true; -+ dc->caps.zstate_support = true; -+ dc->caps.ips_support = true; -+ dc->caps.max_v_total = (1 << 15) - 1; -+ dc->caps.vtotal_limited_by_fp2 = true; -+ -+ dc->caps.seamless_odm = true; -+ dc->caps.zstate_support = true; -+ dc->caps.ips_support = true; -+ dc->caps.max_v_total = (1 << 15) - 1; -+ dc->caps.vtotal_limited_by_fp2 = true; -+ -+ /* Color pipeline capabilities */ -+ dc->caps.color.dpp.dcn_arch = 1; -+ dc->caps.color.dpp.input_lut_shared = 0; -+ dc->caps.color.dpp.icsc = 1; -+ dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr -+ dc->caps.color.dpp.dgam_rom_caps.srgb = 1; -+ dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; -+ dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; -+ dc->caps.color.dpp.dgam_rom_caps.pq = 1; -+ dc->caps.color.dpp.dgam_rom_caps.hlg = 1; -+ dc->caps.color.dpp.post_csc = 1; -+ dc->caps.color.dpp.gamma_corr = 1; -+ dc->caps.color.dpp.dgam_rom_for_yuv = 0; -+ -+ dc->caps.color.dpp.hw_3d_lut = 0; -+ dc->caps.color.dpp.ogam_ram = 0; -+ // no OGAM ROM on DCN2 and later ASICs -+ dc->caps.color.dpp.ogam_rom_caps.srgb = 0; -+ dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; -+ dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; -+ dc->caps.color.dpp.ogam_rom_caps.pq = 0; -+ dc->caps.color.dpp.ogam_rom_caps.hlg = 0; -+ dc->caps.color.dpp.ocsc = 0; -+ -+ dc->caps.color.mpc.gamut_remap = 1; -+ //configurable to be before or after BLND in MPCC -+ dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; -+ dc->caps.color.mpc.num_rmcm_3dluts = 2; -+ dc->caps.color.mpc.ogam_ram = 1; -+ dc->caps.color.mpc.ogam_rom_caps.srgb = 0; -+ dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; -+ dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; -+ dc->caps.color.mpc.ogam_rom_caps.pq = 0; -+ dc->caps.color.mpc.ogam_rom_caps.hlg = 0; -+ dc->caps.color.mpc.ocsc = 1; -+ dc->caps.color.mpc.preblend = true; -+ dc->caps.color.mpc.mcm_3d_lut_caps.dma_3d_lut = 1; -+ dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_9 = 1; -+ dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_17 = 1; -+ dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.linear_1d = 1; -+ dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1; -+ dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1; -+ dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12msb = 1; -+ dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1; -+ dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1; -+ dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1; -+ dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1; -+ dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut = 1; -+ dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 = 1; -+ dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 = 1; -+ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.linear_1d = 1; -+ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1; -+ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1; -+ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12msb = 1; -+ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1; -+ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1; -+ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1; -+ dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1; -+ -+ dc->caps.num_of_host_routers = 3; -+ dc->caps.num_of_dpias_per_host_router = 2; -+ -+ /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order -+ * to provide some margin. -+ * It's expected for furture ASIC to have equal or higher value, in order to -+ * have determinstic power improvement from generate to genration. -+ * (i.e., we should not expect new ASIC generation with lower vmin rate) -+ */ -+ dc->caps.max_disp_clock_khz_at_vmin = 650000; -+ dc->config.use_spl = true; -+ dc->config.prefer_easf = true; -+ -+ dc->config.dcn_sharpness_range.sdr_rgb_min = 0; -+ dc->config.dcn_sharpness_range.sdr_rgb_max = 1750; -+ dc->config.dcn_sharpness_range.sdr_rgb_mid = 750; -+ dc->config.dcn_sharpness_range.sdr_yuv_min = 0; -+ dc->config.dcn_sharpness_range.sdr_yuv_max = 3500; -+ dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500; -+ dc->config.dcn_sharpness_range.hdr_rgb_min = 0; -+ dc->config.dcn_sharpness_range.hdr_rgb_max = 2750; -+ dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500; -+ -+ dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0; -+ dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250; -+ dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250; -+ dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0; -+ dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500; -+ dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500; -+ dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0; -+ dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750; -+ dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500; -+ -+ dc->config.use_pipe_ctx_sync_logic = true; -+ dc->config.dc_mode_clk_limit_support = false; -+ dc->config.enable_windowed_mpo_odm = true; -+ /* Use psp mailbox to enable assr */ -+ dc->config.use_assr_psp_message = true; -+ /* dcn42 and afterward always support external panel replay */ -+ dc->config.frame_update_cmd_version2 = true; -+ -+ /* read VBIOS LTTPR caps */ -+ { -+ if (ctx->dc_bios->funcs->get_lttpr_caps) { -+ enum bp_result bp_query_result; -+ uint8_t is_vbios_lttpr_enable = 0; -+ -+ bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); -+ dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; -+ } ++ struct dml2_per_plane_programming *pln_prog = NULL; ++ struct dml2_plane_mcache_configuration_descriptor *mcache_config = NULL; ++ struct prepare_mcache_programming_locals *l = &dml_ctx->v21.scratch.prepare_mcache_locals; + -+ dc->caps.vbios_lttpr_aware = true; -+ } -+ dc->check_config = config_defaults; -+ -+ if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) -+ dc->debug = debug_defaults_drv; -+ -+ /*HW default is to have all the FGCG enabled, SW no need to program them*/ -+ dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF; -+ // Init the vm_helper -+ if (dc->vm_helper) -+ vm_helper_init(dc->vm_helper, 16); -+ -+ /************************************************* -+ * Create resources * -+ *************************************************/ -+ -+ /* Clock Sources for Pixel Clock*/ -+ pool->base.clock_sources[DCN401_CLK_SRC_PLL0] = -+ dcn42_clock_source_create(ctx, ctx->dc_bios, -+ CLOCK_SOURCE_COMBO_PHY_PLL0, -+ &clk_src_regs[0], false); -+ pool->base.clock_sources[DCN401_CLK_SRC_PLL1] = -+ dcn42_clock_source_create(ctx, ctx->dc_bios, -+ CLOCK_SOURCE_COMBO_PHY_PLL1, -+ &clk_src_regs[1], false); -+ pool->base.clock_sources[DCN401_CLK_SRC_PLL2] = -+ dcn42_clock_source_create(ctx, ctx->dc_bios, -+ CLOCK_SOURCE_COMBO_PHY_PLL2, -+ &clk_src_regs[2], false); -+ pool->base.clock_sources[DCN401_CLK_SRC_PLL3] = -+ dcn42_clock_source_create(ctx, ctx->dc_bios, -+ CLOCK_SOURCE_COMBO_PHY_PLL3, -+ &clk_src_regs[3], false); -+ pool->base.clock_sources[DCN401_CLK_SRC_PLL4] = -+ dcn42_clock_source_create(ctx, ctx->dc_bios, -+ CLOCK_SOURCE_COMBO_PHY_PLL4, -+ &clk_src_regs[4], false); -+ -+ pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL; -+ -+ /* todo: not reuse phy_pll registers */ -+ pool->base.dp_clock_source = -+ dcn42_clock_source_create(ctx, ctx->dc_bios, -+ CLOCK_SOURCE_ID_DP_DTO, -+ &clk_src_regs[0], true); -+ -+ for (i = 0; i < pool->base.clk_src_count; i++) { -+ if (pool->base.clock_sources[i] == NULL) { -+ dm_error("DC: failed to create clock sources!\n"); -+ BREAK_TO_DEBUGGER(); -+ goto create_fail; -+ } ++ if (context->stream_count == 0) { ++ return; + } + -+ /* DCCG */ -+ pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); -+ if (pool->base.dccg == NULL) { -+ dm_error("DC: failed to create dccg!\n"); -+ BREAK_TO_DEBUGGER(); -+ goto create_fail; -+ } ++ memset(&l->build_mcache_programming_params, 0, sizeof(struct dml2_build_mcache_programming_in_out)); ++ l->build_mcache_programming_params.dml2_instance = dml_ctx->v21.dml_init.dml2_instance; + -+#undef REG_STRUCT -+#define REG_STRUCT pg_cntl_regs -+ pg_cntl_dcn42_regs_init(); ++ /* phantom's start after main planes */ ++ dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes; + -+ pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); -+ if (pool->base.pg_cntl == NULL) { -+ dm_error("DC: failed to create power gate control!\n"); -+ BREAK_TO_DEBUGGER(); -+ goto create_fail; -+ } -+ /* IRQ Service */ -+ init_data.ctx = dc->ctx; -+ pool->base.irqs = dal_irq_service_dcn42_create(&init_data); -+ if (!pool->base.irqs) -+ goto create_fail; -+ -+ /* HUBBUB */ -+ pool->base.hubbub = dcn42_hubbub_create(ctx); -+ if (pool->base.hubbub == NULL) { -+ BREAK_TO_DEBUGGER(); -+ dm_error("DC: failed to create hubbub!\n"); -+ goto create_fail; -+ } ++ /* Build mcache programming parameters per plane per pipe */ ++ for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { ++ pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; + -+ /* HUBPs, DPPs, OPPs, TGs, ABMs */ -+ for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { -+ /* if pipe is disabled, skip instance of HW pipe, -+ * i.e, skip ASIC register instance -+ */ -+ if (pipe_fuses & 1 << i) -+ continue; ++ mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_prog_idx]; ++ memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); ++ mcache_config->plane_descriptor = pln_prog->plane_descriptor; ++ mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx]; ++ mcache_config->num_pipes = pln_prog->num_dpps_required; ++ l->build_mcache_programming_params.num_configurations++; + -+ pool->base.hubps[j] = dcn42_hubp_create(ctx, i); -+ if (pool->base.hubps[j] == NULL) { -+ BREAK_TO_DEBUGGER(); -+ dm_error( -+ "DC: failed to create hubps!\n"); -+ goto create_fail; ++ if (pln_prog->num_dpps_required == 0) { ++ continue; + } + -+ pool->base.dpps[j] = dcn42_dpp_create(ctx, i); -+ if (pool->base.dpps[j] == NULL) { -+ BREAK_TO_DEBUGGER(); -+ dm_error( -+ "DC: failed to create dpps!\n"); -+ goto create_fail; -+ } ++ num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); ++ if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || ++ dc_main_pipes[0]->plane_state == NULL) ++ continue; + -+ pool->base.opps[j] = dcn42_opp_create(ctx, i); -+ if (pool->base.opps[j] == NULL) { -+ BREAK_TO_DEBUGGER(); -+ dm_error( -+ "DC: failed to create output pixel processor!\n"); -+ goto create_fail; ++ /* get config for each pipe */ ++ for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { ++ ASSERT(dc_main_pipes[dc_pipe_index]); ++ dml21_get_pipe_mcache_config(context, dc_main_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); + } + -+ pool->base.timing_generators[j] = dcn42_timing_generator_create( -+ ctx, i); -+ if (pool->base.timing_generators[j] == NULL) { -+ BREAK_TO_DEBUGGER(); -+ dm_error("DC: failed to create tg!\n"); -+ goto create_fail; -+ } ++ /* get config for each phantom pipe */ ++ if (pln_prog->phantom_plane.valid && ++ dc_phantom_pipes[0] && ++ dc_main_pipes[0]->stream && ++ dc_phantom_pipes[0]->plane_state) { ++ mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx]; ++ memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); ++ mcache_config->plane_descriptor = pln_prog->plane_descriptor; ++ mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx]; ++ mcache_config->num_pipes = pln_prog->num_dpps_required; ++ l->build_mcache_programming_params.num_configurations++; ++ ++ for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { ++ ASSERT(dc_phantom_pipes[dc_pipe_index]); ++ dml21_get_pipe_mcache_config(context, dc_phantom_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); ++ } + -+ pool->base.multiple_abms[j] = dmub_abm_create(ctx, -+ &abm_regs[i], -+ &abm_shift, -+ &abm_mask); -+ if (pool->base.multiple_abms[j] == NULL) { -+ dm_error("DC: failed to create abm for pipe %d!\n", i); -+ BREAK_TO_DEBUGGER(); -+ goto create_fail; ++ /* increment phantom index */ ++ dml_phantom_prog_idx++; + } -+ -+ /* index for resource pool arrays for next valid pipe */ -+ j++; + } + -+ /* PSR */ -+ pool->base.psr = dmub_psr_create(ctx); -+ if (pool->base.psr == NULL) { -+ dm_error("DC: failed to create psr obj!\n"); -+ BREAK_TO_DEBUGGER(); -+ goto create_fail; -+ } ++ /* Call to generate mcache programming per plane per pipe for the given display configuration */ ++ dml2_build_mcache_programming(&l->build_mcache_programming_params); + -+ /* Replay */ -+ pool->base.replay = dmub_replay_create(ctx); -+ if (pool->base.replay == NULL) { -+ dm_error("DC: failed to create replay obj!\n"); -+ BREAK_TO_DEBUGGER(); -+ goto create_fail; -+ } ++ /* get per plane per pipe mcache programming */ ++ for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { ++ pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; + -+ /* MPCCs */ -+ pool->base.mpc = dcn42_mpc_create(ctx, pool->base.res_cap->num_timing_generator, -+ pool->base.res_cap->num_mpc_3dlut); -+ if (pool->base.mpc == NULL) { -+ BREAK_TO_DEBUGGER(); -+ dm_error("DC: failed to create mpc!\n"); -+ goto create_fail; -+ } ++ num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); ++ if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || ++ dc_main_pipes[0]->plane_state == NULL) ++ continue; + -+ /* DSCs */ -+ for (i = 0; i < pool->base.res_cap->num_dsc; i++) { -+ pool->base.dscs[i] = dcn42_dsc_create(ctx, i); -+ if (pool->base.dscs[i] == NULL) { -+ BREAK_TO_DEBUGGER(); -+ dm_error("DC: failed to create display stream compressor %d!\n", i); -+ goto create_fail; ++ /* get config for each pipe */ ++ for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { ++ ASSERT(dc_main_pipes[dc_pipe_index]); ++ if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index]) { ++ memcpy(&dc_main_pipes[dc_pipe_index]->mcache_regs, ++ l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index], ++ sizeof(struct dml2_hubp_pipe_mcache_regs)); ++ } + } -+ } + -+ /* DWB */ -+ if (!dcn42_dwbc_create(ctx, &pool->base)) { -+ BREAK_TO_DEBUGGER(); -+ dm_error("DC: failed to create dwbc!\n"); -+ goto create_fail; ++ /* get config for each phantom pipe */ ++ if (pln_prog->phantom_plane.valid && ++ dc_phantom_pipes[0] && ++ dc_main_pipes[0]->stream && ++ dc_phantom_pipes[0]->plane_state) { ++ for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { ++ ASSERT(dc_phantom_pipes[dc_pipe_index]); ++ if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) { ++ memcpy(&dc_phantom_pipes[dc_pipe_index]->mcache_regs, ++ l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index], ++ sizeof(struct dml2_hubp_pipe_mcache_regs)); ++ } ++ } ++ /* increment phantom index */ ++ dml_phantom_prog_idx++; ++ } + } ++} + -+ /* MMHUBBUB */ -+ if (!dcn42_mmhubbub_create(ctx, &pool->base)) { -+ BREAK_TO_DEBUGGER(); -+ dm_error("DC: failed to create mcif_wb!\n"); -+ goto create_fail; -+ } + -+ /* AUX and I2C */ -+ for (i = 0; i < pool->base.res_cap->num_ddc; i++) { -+ pool->base.engines[i] = dcn42_aux_engine_create(ctx, i); +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h +new file mode 100644 +index 000000000000..2972c6eed21a +--- /dev/null ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h +@@ -0,0 +1,60 @@ ++// SPDX-License-Identifier: MIT ++// ++// Copyright 2024 Advanced Micro Devices, Inc. + -+ if (pool->base.engines[i] == NULL) { -+ BREAK_TO_DEBUGGER(); -+ dm_error( -+ "DC:failed to create aux engine!!\n"); -+ goto create_fail; -+ } -+ pool->base.hw_i2cs[i] = dcn42_i2c_hw_create(ctx, i); -+ if (pool->base.hw_i2cs[i] == NULL) { -+ BREAK_TO_DEBUGGER(); -+ dm_error( -+ "DC:failed to create hw i2c!!\n"); -+ goto create_fail; -+ } -+ pool->base.sw_i2cs[i] = NULL; -+ } -+ /* DCN4.2 has 6 DPIA */ -+ pool->base.usb4_dpia_count = dc->caps.num_of_host_routers * dc->caps.num_of_dpias_per_host_router; -+ if (dc->debug.dpia_debug.bits.disable_dpia) -+ pool->base.usb4_dpia_count = 0; -+ -+ /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ -+ if (!resource_construct(num_virtual_links, dc, &pool->base, -+ &res_create_funcs)) -+ goto create_fail; -+ -+ /* HW Sequencer init functions and Plane caps */ -+ dcn42_hw_sequencer_init_functions(dc); -+ -+ dc->caps.max_planes = pool->base.pipe_count; -+ -+ for (i = 0; i < dc->caps.max_planes; ++i) -+ dc->caps.planes[i] = plane_cap; -+ -+ dc->caps.max_odm_combine_factor = 4; -+ -+ dc->cap_funcs = cap_funcs; -+ dc->dcn_ip->max_num_dpp = pool->base.pipe_count; -+ -+ // For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided -+ if (dc->config.sdpif_request_limit_words_per_umc == 0) -+ dc->config.sdpif_request_limit_words_per_umc = 16; -+ -+ dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; -+ /*this will use real soc clock table*/ -+ dc->dml2_options.use_native_soc_bb_construction = true; -+ dc->dml2_options.minimize_dispclk_using_odm = false; -+ if (dc->config.EnableMinDispClkODM) -+ dc->dml2_options.minimize_dispclk_using_odm = true; -+ dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; -+ dc->dml2_options.map_dc_pipes_with_callbacks = true; -+ dc->dml2_options.force_tdlut_enable = true; -+ -+ resource_init_common_dml2_callbacks(dc, &dc->dml2_options); -+ dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = -+ &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; -+ dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; -+ dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = -+ pool->base.funcs->calculate_mall_ways_from_bytes; -+ -+ dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us; -+ dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us; -+ dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; -+ dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines; -+ -+ dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp; -+ dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch; -+ -+ dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size; -+ dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; -+ dc->dml2_options.mall_cfg.max_cab_allocation_bytes = -+ dc->caps.max_cab_allocation_bytes; -+ dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE; -+ dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE; -+ dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES; -+ dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; -+ -+ dc->dml2_options.max_segments_per_hubp = 24; -+ dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB; -+ dc->dml2_options.gpuvm_enable = true; -+ dc->dml2_options.hostvm_enable = true; -+ -+ /* SPL */ -+ dc->caps.scl_caps.sharpener_support = true; ++#ifndef _DML21_WRAPPER_FPU_H_ ++#define _DML21_WRAPPER_FPU_H_ + -+ return true; ++#include "os_types.h" ++#include "dml_top_soc_parameter_types.h" ++#include "dml_top_display_cfg_types.h" + -+create_fail: ++struct dc; ++struct dc_state; ++struct dml2_configuration_options; ++struct dml2_context; ++enum dc_validate_mode; + -+ dcn42_resource_destruct(pool); ++/** ++ * dml21_init - Initialize DML21 context ++ * @in_dc: dc. ++ * @dml_ctx: DML21 context to initialize. ++ * @config: dml21 configuration options. ++ * ++ * Performs FPU-requiring initialization. Must be called with FPU protection. ++ */ ++void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config); + -+ return false; -+} -+struct resource_pool *dcn42_create_resource_pool( -+ const struct dc_init_data *init_data, -+ struct dc *dc) -+{ -+ struct dcn42_resource_pool *pool = -+ kzalloc(sizeof(struct dcn401_resource_pool), GFP_KERNEL); ++/** ++ * dml21_validate - Determines if a display configuration is supported or not. ++ * @in_dc: dc. ++ * @context: dc_state to be validated. ++ * @dml_ctx: dml21 context. ++ * @validate_mode: DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX ++ * will not populate context.res_ctx. ++ * ++ * Based on fast_validate option internally would call: ++ * ++ * -dml21_mode_check_and_programming - for DC_VALIDATE_MODE_AND_PROGRAMMING option ++ * Calculates if dc_state can be supported on the input display ++ * configuration. If supported, generates the necessary HW ++ * programming for the new dc_state. ++ * ++ * -dml21_check_mode_support - for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX option ++ * Calculates if dc_state can be supported for the input display ++ * config. ++ * ++ * Context: Two threads may not invoke this function concurrently unless they reference ++ * separate dc_states for validation. ++ * Return: True if mode is supported, false otherwise. ++ */ + -+ if (!pool) -+ return NULL; ++void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, ++ const struct dml2_configuration_options *config); ++bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, ++ enum dc_validate_mode validate_mode); ++ ++/* Prepare hubp mcache_regs for hubp mcache ID and split coordinate programming */ ++void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx); ++ ++#endif /* _DML21_WRAPPER_FPU_H_ */ +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c +index 307186eb6af0..9215e38343ba 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c +@@ -6,7 +6,20 @@ + */ + + #include "dml2_internal_types.h" ++#include "dml2_wrapper.h" + #include "dml2_wrapper_fpu.h" ++#include "dml21_wrapper.h" ++#include "dml21_wrapper_fpu.h" ++ ++#include "dc_fpu.h" + -+ if (dcn42_resource_construct(init_data->num_virtual_links, dc, pool)) -+ return &pool->base; ++struct dml2_context *dml2_allocate_memory(void) ++{ ++ struct dml2_context *dml2; + -+ BREAK_TO_DEBUGGER(); -+ kfree(pool); -+ return NULL; ++ DC_RUN_WITH_PREEMPTION_ENABLED(dml2 = vzalloc(sizeof(struct dml2_context))); ++ return dml2; +} + + bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2, + enum dc_validate_mode validate_mode) +@@ -23,16 +36,12 @@ bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2 + return out; + } + +- DC_FP_START(); +- + /* Use dml_validate_only for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */ + if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) + out = dml2_validate_only(context, validate_mode); + else + out = dml2_validate_and_build_resource(in_dc, context, validate_mode); + +- DC_FP_END(); +- + return out; + } + +@@ -70,15 +79,11 @@ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_op + break; + } + +- DC_FP_START(); +- + initialize_dml2_ip_params(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.ip); + + initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc); + + initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx.states); +- +- DC_FP_END(); + } + + bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2) +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c +index 203eef747262..66624cfc27b1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c +@@ -31,8 +31,10 @@ + #include "dml2_translation_helper.h" + #include "dml2_mall_phantom.h" + #include "dml2_dc_resource_mgmt.h" +-#include "dml21_wrapper.h" ++#include "dml2_wrapper.h" + #include "dml2_wrapper_fpu.h" ++#include "dml21_wrapper.h" ++#include "dml21_wrapper_fpu.h" + + void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out) + { +@@ -546,11 +548,6 @@ void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2) + } + } + +-inline struct dml2_context *dml2_allocate_memory(void) +-{ +- return (struct dml2_context *) vzalloc(sizeof(struct dml2_context)); +-} +- + void dml2_destroy(struct dml2_context *dml2) + { + if (!dml2) -- 2.53.0 diff --git a/SPECS/linux/0085-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch b/SPECS/linux/0085-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch index 380bf545d3..40867c1019 100644 --- a/SPECS/linux/0085-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch +++ b/SPECS/linux/0085-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch @@ -1,8 +1,8 @@ -From eea09df44b0a77d8a7e7b34fc22b8a10148a2f73 Mon Sep 17 00:00:00 2001 +From 053fbb2bf5b5e7db5b0adb9ce4933e320a3b3bd6 Mon Sep 17 00:00:00 2001 From: Rafal Ostrowski -Date: Wed, 18 Feb 2026 16:19:47 +0100 -Subject: [PATCH 085/269] UPSTREAM: drm/amd/display: Move FPU Guards From DML - To DC - Part 2 +Date: Mon, 23 Feb 2026 06:13:32 +0100 +Subject: [RUYI PATCH] UPSTREAM: drm/amd/display: Move FPU Guards From DML To + DC - Part 3 [Why] FPU guards (DC_FP_START/DC_FP_END) are required to wrap around code that @@ -12,1130 +12,110 @@ a file that is a FPU unit, other sections in the file that aren't guarded may be end up being compiled to use FPU operations. [How] -Removed DC_FP_START and DC_FP_END. +Added DC_FP_START and DC_FP_END to DC functions that call DML functions +using FPU. Reviewed-by: Dillon Varone Signed-off-by: Rafal Ostrowski Signed-off-by: Alex Hung -Signed-off-by: Chuanyu Tseng Signed-off-by: Alex Deucher -(cherry picked from commit 4bb2f0721ed8a2a70f864b9358bd6cd4d92199b3) +(cherry picked from commit 32c1c35b6d8bd8b7ea9ab3d1454b56b605f17dd1) Signed-off-by: Xi Ruoyao Signed-off-by: Han Gao --- - .../gpu/drm/amd/display/dc/dml2_0/Makefile | 73 +--- - .../display/dc/dml2_0/dml21/dml21_wrapper.c | 379 +---------------- - .../display/dc/dml2_0/dml21/dml21_wrapper.h | 30 -- - .../dc/dml2_0/dml21/dml21_wrapper_fpu.c | 381 ++++++++++++++++++ - .../dc/dml2_0/dml21/dml21_wrapper_fpu.h | 60 +++ - .../drm/amd/display/dc/dml2_0/dml2_wrapper.c | 21 +- - .../amd/display/dc/dml2_0/dml2_wrapper_fpu.c | 9 +- - 7 files changed, 484 insertions(+), 469 deletions(-) - create mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c - create mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h + drivers/gpu/drm/amd/display/dc/dml2_0/Makefile | 1 + + drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c | 1 + + .../gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c | 4 +--- + .../gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h | 2 +- + drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c | 6 +++++- + 5 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile -index 30cfc0848792..a094cfa78260 100644 +index a094cfa78260..145ff97ed560 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile -@@ -53,25 +53,29 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/inc - subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/inc - subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/ - --CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper_fpu.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_ccflags) -+# Add FPU flags to all dml2 files by default, remove NO_FPU flags. -+# FPU flags step 1: Find all .c files in dal/dc/dml2_0 and it's subfolders -+DML2_ABS_PATH := $(FULL_AMD_DISPLAY_PATH)/dc/dml2_0 -+DML2_C_FILES := $(shell find $(DML2_ABS_PATH) -name '*.c' -type f) -+ -+# FPU flags step 2: Convert to .o and make paths relative to $(AMDDALPATH)/dc/dml2_0/ -+DML2_RELATIVE_O_FILES := $(patsubst $(DML2_ABS_PATH)/%,dc/dml2_0/%,$(patsubst %.c,%.o,$(DML2_C_FILES))) - -+# FPU flags step 3: Apply FPU flags to all .o files from dal/dc/dml2_0 and it's subfolders -+$(foreach obj,$(DML2_RELATIVE_O_FILES),$(eval CFLAGS_$(AMDDALPATH)/$(obj) := $(dml2_ccflags))) -+$(foreach obj,$(DML2_RELATIVE_O_FILES),$(eval CFLAGS_REMOVE_$(AMDDALPATH)/$(obj) := $(dml2_rcflags))) -+ -+# FPU flags step 4: Replace CFLAGS per file for files with additional flags beyond dml2_ccflags and dml2_rcflags -+CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag) -+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag) -+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_ccflags) $(frame_warn_flag) -+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_rcflags) -+CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_wrapper.o := $(dml2_rcflags) - CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper_fpu.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_rcflags) -+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags) -+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_rcflags) -+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_ccflags) -+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_wrapper.o := $(dml2_ccflags) - - DML2 = display_mode_core.o display_mode_util.o dml2_wrapper_fpu.o dml2_wrapper.o \ - dml2_utils.o dml2_policy.o dml2_translation_helper.o dml2_dc_resource_mgmt.o dml2_mall_phantom.o \ -@@ -81,40 +85,6 @@ AMD_DAL_DML2 = $(addprefix $(AMDDALPATH)/dc/dml2_0/,$(DML2)) +@@ -85,6 +85,7 @@ AMD_DAL_DML2 = $(addprefix $(AMDDALPATH)/dc/dml2_0/,$(DML2)) AMD_DISPLAY_FILES += $(AMD_DAL_DML2) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_ccflags) $(frame_warn_flag) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_ccflags) --CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_ccflags) -- --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_rcflags) --CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_rcflags) -- ++ DML21 := src/dml2_top/dml2_top_interfaces.o DML21 += src/dml2_top/dml2_top_soc15.o DML21 += src/dml2_core/dml2_core_dcn4.o -@@ -131,6 +101,7 @@ DML21 += src/dml2_pmo/dml2_pmo_dcn4_fams2.o - DML21 += src/dml2_standalone_libraries/lib_float_math.o - DML21 += dml21_translation_helper.o - DML21 += dml21_wrapper.o -+DML21 += dml21_wrapper_fpu.o - DML21 += dml21_utils.o - - AMD_DAL_DML21 = $(addprefix $(AMDDALPATH)/dc/dml2_0/dml21/,$(DML21)) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -index 2623e917ec28..1a98578f223c 100644 +index 1a98578f223c..7398f8b69adb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -@@ -9,6 +9,10 @@ - #include "dml21_utils.h" - #include "dml21_translation_helper.h" - #include "dml2_dc_resource_mgmt.h" -+#include "dml2_wrapper.h" -+#include "dml2_wrapper_fpu.h" -+#include "dml21_wrapper.h" -+#include "dml21_wrapper_fpu.h" - #include "dc_fpu.h" +@@ -38,6 +38,7 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx) + (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; - #if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) -@@ -40,44 +44,11 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx) - return true; - } - --static void dml21_populate_configuration_options(const struct dc *in_dc, -- struct dml2_context *dml_ctx, -- const struct dml2_configuration_options *config) --{ -- dml_ctx->config = *config; -- -- /* UCLK P-State options */ -- if (in_dc->debug.dml21_force_pstate_method) { -- dml_ctx->config.pmo.force_pstate_method_enable = true; -- for (int i = 0; i < MAX_PIPES; i++) -- dml_ctx->config.pmo.force_pstate_method_values[i] = in_dc->debug.dml21_force_pstate_method_values[i]; -- } else { -- dml_ctx->config.pmo.force_pstate_method_enable = false; -- } --} -- --static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config) --{ -- -- dml_ctx->architecture = dml2_architecture_21; -- -- dml21_populate_configuration_options(in_dc, dml_ctx, config); -- -- DC_FP_START(); -- -- dml21_populate_dml_init_params(&dml_ctx->v21.dml_init, &dml_ctx->config, in_dc); -- -- dml2_initialize_instance(&dml_ctx->v21.dml_init); -- -- DC_FP_END(); --} -- - bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) - { - /* Allocate memory for initializing DML21 instance */ -- if (!dml21_allocate_memory(dml_ctx)) { -+ if (!dml21_allocate_memory(dml_ctx)) + DC_RUN_WITH_PREEMPTION_ENABLED((*dml_ctx)->v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming))); ++ + if (!((*dml_ctx)->v21.mode_programming.programming)) return false; -- } - - dml21_init(in_dc, *dml_ctx, config); - -@@ -90,337 +61,6 @@ void dml21_destroy(struct dml2_context *dml2) - vfree(dml2->v21.mode_programming.programming); - } - --static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, -- struct dml2_context *in_ctx, unsigned int pipe_cnt) --{ -- unsigned int dml_prog_idx = 0, dc_pipe_index = 0, num_dpps_required = 0; -- struct dml2_per_plane_programming *pln_prog = NULL; -- struct dml2_per_stream_programming *stream_prog = NULL; -- struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; -- struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; -- int num_pipes; -- unsigned int dml_phantom_prog_idx; -- -- context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; -- -- /* copy global DCHUBBUB arbiter registers */ -- memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.arb_regs, sizeof(struct dml2_display_arb_regs)); -- -- /* legacy only */ -- context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_regs.arb_regs.compbuf_size * 64; -- -- context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; -- context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; -- context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; -- -- /* phantom's start after main planes */ -- dml_phantom_prog_idx = in_ctx->v21.mode_programming.programming->display_config.num_planes; -- -- for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) { -- pln_prog = &in_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; -- -- if (!pln_prog->plane_descriptor) -- continue; -- -- stream_prog = &in_ctx->v21.mode_programming.programming->stream_programming[pln_prog->plane_descriptor->stream_index]; -- num_dpps_required = pln_prog->num_dpps_required; -- -- if (num_dpps_required == 0) { -- continue; -- } -- num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); -- -- if (num_pipes <= 0) -- continue; -- -- /* program each pipe */ -- for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { -- dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog); -- -- if (pln_prog->phantom_plane.valid && dc_phantom_pipes[dc_pipe_index]) { -- dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog); -- } -- } -- -- /* copy per plane mcache allocation */ -- memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx], &pln_prog->mcache_allocation, sizeof(struct dml2_mcache_surface_allocation)); -- if (pln_prog->phantom_plane.valid) { -- memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx], -- &pln_prog->phantom_plane.mcache_allocation, -- sizeof(struct dml2_mcache_surface_allocation)); -- -- dml_phantom_prog_idx++; -- } -- } -- -- /* assign global clocks */ -- context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; -- context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; -- if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { -- context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = -- in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000; -- } else { -- context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000; -- } -- -- if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { -- context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = -- in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000; -- } else { -- context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000; -- } -- -- /* get global mall allocation */ -- if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { -- context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes); -- } else { -- context->bw_ctx.bw.dcn.clk.num_ways = 0; -- } --} -- --static void dml21_prepare_mcache_params(struct dml2_context *dml_ctx, struct dc_state *context, struct dc_mcache_params *mcache_params) --{ -- int dc_plane_idx = 0; -- int dml_prog_idx, stream_idx, plane_idx; -- struct dml2_per_plane_programming *pln_prog = NULL; -- -- for (stream_idx = 0; stream_idx < context->stream_count; stream_idx++) { -- for (plane_idx = 0; plane_idx < context->stream_status[stream_idx].plane_count; plane_idx++) { -- dml_prog_idx = map_plane_to_dml21_display_cfg(dml_ctx, context->streams[stream_idx]->stream_id, context->stream_status[stream_idx].plane_states[plane_idx], context); -- if (dml_prog_idx == INVALID) { -- continue; -- } -- pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; -- mcache_params[dc_plane_idx].valid = pln_prog->mcache_allocation.valid; -- mcache_params[dc_plane_idx].num_mcaches_plane0 = pln_prog->mcache_allocation.num_mcaches_plane0; -- mcache_params[dc_plane_idx].num_mcaches_plane1 = pln_prog->mcache_allocation.num_mcaches_plane1; -- mcache_params[dc_plane_idx].requires_dedicated_mall_mcache = pln_prog->mcache_allocation.requires_dedicated_mall_mcache; -- mcache_params[dc_plane_idx].last_slice_sharing.plane0_plane1 = pln_prog->mcache_allocation.last_slice_sharing.plane0_plane1; -- memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane0, -- pln_prog->mcache_allocation.mcache_x_offsets_plane0, -- sizeof(int) * (DML2_MAX_MCACHES + 1)); -- memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane1, -- pln_prog->mcache_allocation.mcache_x_offsets_plane1, -- sizeof(int) * (DML2_MAX_MCACHES + 1)); -- dc_plane_idx++; -- } -- } --} -- --static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) --{ -- bool result = false; -- struct dml2_build_mode_programming_in_out *mode_programming = &dml_ctx->v21.mode_programming; -- struct dc_mcache_params mcache_params[MAX_PLANES] = {0}; -- -- memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); -- memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); -- memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out)); -- -- if (!context) -- return true; -- -- if (context->stream_count == 0) { -- dml21_init_min_clocks_for_dc_state(dml_ctx, context); -- dml21_build_fams2_programming(in_dc, context, dml_ctx); -- return true; -- } -- -- /* scrub phantom's from current dc_state */ -- dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); -- dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); -- -- /* Populate stream, plane mappings and other fields in display config. */ -- result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); -- if (!result) -- return false; -- -- DC_FP_START(); -- result = dml2_build_mode_programming(mode_programming); -- DC_FP_END(); -- if (!result) -- return false; -- -- /* Check and map HW resources */ -- if (result && !dml_ctx->config.skip_hw_state_mapping) { -- dml21_map_hw_resources(dml_ctx); -- dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, in_dc->current_state); -- /* if subvp phantoms are present, expand them into dc context */ -- dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx); -- -- if (in_dc->res_pool->funcs->program_mcache_pipe_config) { -- //Prepare mcache params for each plane based on mcache output from DML -- dml21_prepare_mcache_params(dml_ctx, context, mcache_params); -- -- //populate mcache regs to each pipe -- dml_ctx->config.callbacks.allocate_mcache(context, mcache_params); -- } -- } -- -- /* Copy DML CLK, WM and REG outputs to bandwidth context */ -- if (result && !dml_ctx->config.skip_hw_state_mapping) { -- dml21_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml_ctx, in_dc->res_pool->pipe_count); -- dml21_copy_clocks_to_dc_state(dml_ctx, context); -- dml21_extract_watermark_sets(in_dc, &context->bw_ctx.bw.dcn.watermarks, dml_ctx); -- dml21_build_fams2_programming(in_dc, context, dml_ctx); -- } -- -- return true; --} -- --static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) --{ -- bool is_supported = false; -- struct dml2_initialize_instance_in_out *dml_init = &dml_ctx->v21.dml_init; -- struct dml2_check_mode_supported_in_out *mode_support = &dml_ctx->v21.mode_support; -- -- memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); -- memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); -- memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out)); -- -- if (!context || context->stream_count == 0) -- return true; -- -- /* Scrub phantom's from current dc_state */ -- dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); -- dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); -- -- mode_support->dml2_instance = dml_init->dml2_instance; -- dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); -- dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; -- DC_FP_START(); -- is_supported = dml2_check_mode_supported(mode_support); -- DC_FP_END(); -- if (!is_supported) -- return false; -- -- return true; --} -- --bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, -- enum dc_validate_mode validate_mode) --{ -- bool out = false; -- -- /* Use dml21_check_mode_support for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */ -- if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) -- out = dml21_check_mode_support(in_dc, context, dml_ctx); -- else -- out = dml21_mode_check_and_programming(in_dc, context, dml_ctx); -- -- return out; --} -- --void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) --{ -- unsigned int dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index; -- int num_pipes; -- struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; -- struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; -- -- struct dml2_per_plane_programming *pln_prog = NULL; -- struct dml2_plane_mcache_configuration_descriptor *mcache_config = NULL; -- struct prepare_mcache_programming_locals *l = &dml_ctx->v21.scratch.prepare_mcache_locals; -- -- if (context->stream_count == 0) { -- return; -- } -- -- memset(&l->build_mcache_programming_params, 0, sizeof(struct dml2_build_mcache_programming_in_out)); -- l->build_mcache_programming_params.dml2_instance = dml_ctx->v21.dml_init.dml2_instance; -- -- /* phantom's start after main planes */ -- dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes; -- -- /* Build mcache programming parameters per plane per pipe */ -- for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { -- pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; -- -- mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_prog_idx]; -- memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); -- mcache_config->plane_descriptor = pln_prog->plane_descriptor; -- mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx]; -- mcache_config->num_pipes = pln_prog->num_dpps_required; -- l->build_mcache_programming_params.num_configurations++; -- -- if (pln_prog->num_dpps_required == 0) { -- continue; -- } -- -- num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); -- if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || -- dc_main_pipes[0]->plane_state == NULL) -- continue; -- -- /* get config for each pipe */ -- for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { -- ASSERT(dc_main_pipes[dc_pipe_index]); -- dml21_get_pipe_mcache_config(context, dc_main_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); -- } -- -- /* get config for each phantom pipe */ -- if (pln_prog->phantom_plane.valid && -- dc_phantom_pipes[0] && -- dc_main_pipes[0]->stream && -- dc_phantom_pipes[0]->plane_state) { -- mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx]; -- memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); -- mcache_config->plane_descriptor = pln_prog->plane_descriptor; -- mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx]; -- mcache_config->num_pipes = pln_prog->num_dpps_required; -- l->build_mcache_programming_params.num_configurations++; -- -- for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { -- ASSERT(dc_phantom_pipes[dc_pipe_index]); -- dml21_get_pipe_mcache_config(context, dc_phantom_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); -- } -- -- /* increment phantom index */ -- dml_phantom_prog_idx++; -- } -- } -- -- /* Call to generate mcache programming per plane per pipe for the given display configuration */ -- dml2_build_mcache_programming(&l->build_mcache_programming_params); -- -- /* get per plane per pipe mcache programming */ -- for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { -- pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; -- -- num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); -- if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || -- dc_main_pipes[0]->plane_state == NULL) -- continue; -- -- /* get config for each pipe */ -- for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { -- ASSERT(dc_main_pipes[dc_pipe_index]); -- if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index]) { -- memcpy(&dc_main_pipes[dc_pipe_index]->mcache_regs, -- l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index], -- sizeof(struct dml2_hubp_pipe_mcache_regs)); -- } -- } -- -- /* get config for each phantom pipe */ -- if (pln_prog->phantom_plane.valid && -- dc_phantom_pipes[0] && -- dc_main_pipes[0]->stream && -- dc_phantom_pipes[0]->plane_state) { -- for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { -- ASSERT(dc_phantom_pipes[dc_pipe_index]); -- if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) { -- memcpy(&dc_phantom_pipes[dc_pipe_index]->mcache_regs, -- l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index], -- sizeof(struct dml2_hubp_pipe_mcache_regs)); -- } -- } -- /* increment phantom index */ -- dml_phantom_prog_idx++; -- } -- } --} -- - void dml21_copy(struct dml2_context *dst_dml_ctx, - struct dml2_context *src_dml_ctx) - { -@@ -446,12 +86,8 @@ void dml21_copy(struct dml2_context *dst_dml_ctx, - dst_dml_ctx->v21.mode_programming.programming = dst_dml2_programming; - -- DC_FP_START(); -- - /* need to initialize copied instance for internal references to be correct */ - dml2_initialize_instance(&dst_dml_ctx->v21.dml_init); -- -- DC_FP_END(); - } +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c +index d5885bbd14c4..f3abfdbe6805 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: MIT + // +-// Copyright 2024 Advanced Micro Devices, Inc. ++// Copyright 2026 Advanced Micro Devices, Inc. - bool dml21_create_copy(struct dml2_context **dst_dml_ctx, -@@ -466,8 +102,3 @@ bool dml21_create_copy(struct dml2_context **dst_dml_ctx, - return true; + #include "dml2_internal_types.h" + #include "dml_top.h" +@@ -377,5 +377,3 @@ void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context + } + } } - --void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config) --{ -- dml21_init(in_dc, dml_ctx, config); --} -- -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h -index b508bbcc0e16..c4813c51251b 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h -@@ -34,36 +34,6 @@ void dml21_copy(struct dml2_context *dst_dml_ctx, - struct dml2_context *src_dml_ctx); - bool dml21_create_copy(struct dml2_context **dst_dml_ctx, - struct dml2_context *src_dml_ctx); --void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config); - --/** -- * dml21_validate - Determines if a display configuration is supported or not. -- * @in_dc: dc. -- * @context: dc_state to be validated. -- * @dml_ctx: dml21 context. -- * @validate_mode: DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX -- * will not populate context.res_ctx. -- * -- * Based on fast_validate option internally would call: -- * -- * -dml21_mode_check_and_programming - for DC_VALIDATE_MODE_AND_PROGRAMMING option -- * Calculates if dc_state can be supported on the input display -- * configuration. If supported, generates the necessary HW -- * programming for the new dc_state. -- * -- * -dml21_check_mode_support - for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX option -- * Calculates if dc_state can be supported for the input display -- * config. -- * -- * Context: Two threads may not invoke this function concurrently unless they reference -- * separate dc_states for validation. -- * Return: True if mode is supported, false otherwise. -- */ --bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, -- enum dc_validate_mode validate_mode); - --/* Prepare hubp mcache_regs for hubp mcache ID and split coordinate programming */ --void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx); - - /* Structure for inputting external SOCBB and DCNIP values for tool based debugging. */ - struct socbb_ip_params_external { -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c -new file mode 100644 -index 000000000000..d5885bbd14c4 ---- /dev/null -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c -@@ -0,0 +1,381 @@ -+// SPDX-License-Identifier: MIT -+// -+// Copyright 2024 Advanced Micro Devices, Inc. -+ -+#include "dml2_internal_types.h" -+#include "dml_top.h" -+#include "dml2_core_dcn4_calcs.h" -+#include "dml2_internal_shared_types.h" -+#include "dml21_utils.h" -+#include "dml21_translation_helper.h" -+#include "dml2_dc_resource_mgmt.h" -+#include "dml2_wrapper.h" -+#include "dml2_wrapper_fpu.h" -+#include "dml21_wrapper.h" -+#include "dml21_wrapper_fpu.h" -+ -+#define INVALID -1 -+ -+static void dml21_populate_configuration_options(const struct dc *in_dc, -+ struct dml2_context *dml_ctx, -+ const struct dml2_configuration_options *config) -+{ -+ dml_ctx->config = *config; -+ -+ /* UCLK P-State options */ -+ if (in_dc->debug.dml21_force_pstate_method) { -+ dml_ctx->config.pmo.force_pstate_method_enable = true; -+ for (int i = 0; i < MAX_PIPES; i++) -+ dml_ctx->config.pmo.force_pstate_method_values[i] = in_dc->debug.dml21_force_pstate_method_values[i]; -+ } else { -+ dml_ctx->config.pmo.force_pstate_method_enable = false; -+ } -+} -+ -+void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config) -+{ -+ dml_ctx->architecture = dml2_architecture_21; -+ -+ dml21_populate_configuration_options(in_dc, dml_ctx, config); -+ -+ dml21_populate_dml_init_params(&dml_ctx->v21.dml_init, &dml_ctx->config, in_dc); -+ -+ dml2_initialize_instance(&dml_ctx->v21.dml_init); -+} -+ -+void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config) -+{ -+ dml21_init(in_dc, dml_ctx, config); -+} -+ -+static void dml21_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, -+ struct dml2_context *in_ctx, unsigned int pipe_cnt) -+{ -+ unsigned int dml_prog_idx = 0, dc_pipe_index = 0, num_dpps_required = 0; -+ struct dml2_per_plane_programming *pln_prog = NULL; -+ struct dml2_per_stream_programming *stream_prog = NULL; -+ struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; -+ struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; -+ int num_pipes; -+ unsigned int dml_phantom_prog_idx; -+ -+ context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; -+ -+ /* copy global DCHUBBUB arbiter registers */ -+ memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.arb_regs, sizeof(struct dml2_display_arb_regs)); -+ -+ /* legacy only */ -+ context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_regs.arb_regs.compbuf_size * 64; -+ -+ context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; -+ context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; -+ context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; -+ -+ /* phantom's start after main planes */ -+ dml_phantom_prog_idx = in_ctx->v21.mode_programming.programming->display_config.num_planes; -+ -+ for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) { -+ pln_prog = &in_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; -+ -+ if (!pln_prog->plane_descriptor) -+ continue; -+ -+ stream_prog = &in_ctx->v21.mode_programming.programming->stream_programming[pln_prog->plane_descriptor->stream_index]; -+ num_dpps_required = pln_prog->num_dpps_required; -+ -+ if (num_dpps_required == 0) { -+ continue; -+ } -+ num_pipes = dml21_find_dc_pipes_for_plane(dc, context, in_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); -+ -+ if (num_pipes <= 0) -+ continue; -+ -+ /* program each pipe */ -+ for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { -+ dml21_program_dc_pipe(in_ctx, context, dc_main_pipes[dc_pipe_index], pln_prog, stream_prog); -+ -+ if (pln_prog->phantom_plane.valid && dc_phantom_pipes[dc_pipe_index]) { -+ dml21_program_dc_pipe(in_ctx, context, dc_phantom_pipes[dc_pipe_index], pln_prog, stream_prog); -+ } -+ } -+ -+ /* copy per plane mcache allocation */ -+ memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx], &pln_prog->mcache_allocation, sizeof(struct dml2_mcache_surface_allocation)); -+ if (pln_prog->phantom_plane.valid) { -+ memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx], -+ &pln_prog->phantom_plane.mcache_allocation, -+ sizeof(struct dml2_mcache_surface_allocation)); -+ -+ dml_phantom_prog_idx++; -+ } -+ } -+ -+ /* assign global clocks */ -+ context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; -+ context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; -+ if (in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values > 1) { -+ context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = -+ in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.num_clk_values] * 1000; -+ } else { -+ context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[0] * 1000; -+ } -+ -+ if (in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values > 1) { -+ context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = -+ in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.num_clk_values] * 1000; -+ } else { -+ context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[0] * 1000; -+ } -+ -+ /* get global mall allocation */ -+ if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { -+ context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes); -+ } else { -+ context->bw_ctx.bw.dcn.clk.num_ways = 0; -+ } -+} -+ -+static void dml21_prepare_mcache_params(struct dml2_context *dml_ctx, struct dc_state *context, struct dc_mcache_params *mcache_params) -+{ -+ int dc_plane_idx = 0; -+ int dml_prog_idx, stream_idx, plane_idx; -+ struct dml2_per_plane_programming *pln_prog = NULL; -+ -+ for (stream_idx = 0; stream_idx < context->stream_count; stream_idx++) { -+ for (plane_idx = 0; plane_idx < context->stream_status[stream_idx].plane_count; plane_idx++) { -+ dml_prog_idx = map_plane_to_dml21_display_cfg(dml_ctx, context->streams[stream_idx]->stream_id, context->stream_status[stream_idx].plane_states[plane_idx], context); -+ if (dml_prog_idx == INVALID) { -+ continue; -+ } -+ pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; -+ mcache_params[dc_plane_idx].valid = pln_prog->mcache_allocation.valid; -+ mcache_params[dc_plane_idx].num_mcaches_plane0 = pln_prog->mcache_allocation.num_mcaches_plane0; -+ mcache_params[dc_plane_idx].num_mcaches_plane1 = pln_prog->mcache_allocation.num_mcaches_plane1; -+ mcache_params[dc_plane_idx].requires_dedicated_mall_mcache = pln_prog->mcache_allocation.requires_dedicated_mall_mcache; -+ mcache_params[dc_plane_idx].last_slice_sharing.plane0_plane1 = pln_prog->mcache_allocation.last_slice_sharing.plane0_plane1; -+ memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane0, -+ pln_prog->mcache_allocation.mcache_x_offsets_plane0, -+ sizeof(int) * (DML2_MAX_MCACHES + 1)); -+ memcpy(mcache_params[dc_plane_idx].mcache_x_offsets_plane1, -+ pln_prog->mcache_allocation.mcache_x_offsets_plane1, -+ sizeof(int) * (DML2_MAX_MCACHES + 1)); -+ dc_plane_idx++; -+ } -+ } -+} -+ -+static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) -+{ -+ bool is_supported = false; -+ struct dml2_initialize_instance_in_out *dml_init = &dml_ctx->v21.dml_init; -+ struct dml2_check_mode_supported_in_out *mode_support = &dml_ctx->v21.mode_support; -+ -+ memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); -+ memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); -+ memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.check_mode_supported_locals.mode_support_params, 0, sizeof(struct dml2_core_mode_support_in_out)); -+ -+ if (!context || context->stream_count == 0) -+ return true; -+ -+ /* Scrub phantom's from current dc_state */ -+ dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); -+ dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); -+ -+ mode_support->dml2_instance = dml_init->dml2_instance; -+ dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); -+ dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; -+ -+ is_supported = dml2_check_mode_supported(mode_support); -+ -+ if (!is_supported) -+ return false; -+ -+ return true; -+} -+ -+static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) -+{ -+ bool result = false; -+ struct dml2_build_mode_programming_in_out *mode_programming = &dml_ctx->v21.mode_programming; -+ struct dc_mcache_params mcache_params[MAX_PLANES] = {0}; -+ -+ memset(&dml_ctx->v21.display_config, 0, sizeof(struct dml2_display_cfg)); -+ memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); -+ memset(&dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params, 0, sizeof(struct dml2_core_mode_programming_in_out)); -+ -+ if (!context) -+ return true; -+ -+ if (context->stream_count == 0) { -+ dml21_init_min_clocks_for_dc_state(dml_ctx, context); -+ dml21_build_fams2_programming(in_dc, context, dml_ctx); -+ return true; -+ } -+ -+ /* scrub phantom's from current dc_state */ -+ dml_ctx->config.svp_pstate.callbacks.remove_phantom_streams_and_planes(in_dc, context); -+ dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); -+ -+ /* Populate stream, plane mappings and other fields in display config. */ -+ result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); -+ if (!result) -+ return false; -+ -+ result = dml2_build_mode_programming(mode_programming); -+ -+ if (!result) -+ return false; -+ -+ /* Check and map HW resources */ -+ if (result && !dml_ctx->config.skip_hw_state_mapping) { -+ dml21_map_hw_resources(dml_ctx); -+ dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, in_dc->current_state); -+ /* if subvp phantoms are present, expand them into dc context */ -+ dml21_handle_phantom_streams_planes(in_dc, context, dml_ctx); -+ -+ if (in_dc->res_pool->funcs->program_mcache_pipe_config) { -+ //Prepare mcache params for each plane based on mcache output from DML -+ dml21_prepare_mcache_params(dml_ctx, context, mcache_params); -+ -+ //populate mcache regs to each pipe -+ dml_ctx->config.callbacks.allocate_mcache(context, mcache_params); -+ } -+ } -+ -+ /* Copy DML CLK, WM and REG outputs to bandwidth context */ -+ if (result && !dml_ctx->config.skip_hw_state_mapping) { -+ dml21_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml_ctx, in_dc->res_pool->pipe_count); -+ dml21_copy_clocks_to_dc_state(dml_ctx, context); -+ dml21_extract_watermark_sets(in_dc, &context->bw_ctx.bw.dcn.watermarks, dml_ctx); -+ dml21_build_fams2_programming(in_dc, context, dml_ctx); -+ } -+ -+ return true; -+} -+ -+bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, -+ enum dc_validate_mode validate_mode) -+{ -+ bool out = false; -+ -+ /* Use dml21_check_mode_support for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */ -+ if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) -+ out = dml21_check_mode_support(in_dc, context, dml_ctx); -+ else -+ out = dml21_mode_check_and_programming(in_dc, context, dml_ctx); -+ -+ return out; -+} -+ -+void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx) -+{ -+ unsigned int dml_prog_idx, dml_phantom_prog_idx, dc_pipe_index; -+ int num_pipes; -+ struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; -+ struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; -+ -+ struct dml2_per_plane_programming *pln_prog = NULL; -+ struct dml2_plane_mcache_configuration_descriptor *mcache_config = NULL; -+ struct prepare_mcache_programming_locals *l = &dml_ctx->v21.scratch.prepare_mcache_locals; -+ -+ if (context->stream_count == 0) { -+ return; -+ } -+ -+ memset(&l->build_mcache_programming_params, 0, sizeof(struct dml2_build_mcache_programming_in_out)); -+ l->build_mcache_programming_params.dml2_instance = dml_ctx->v21.dml_init.dml2_instance; -+ -+ /* phantom's start after main planes */ -+ dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes; -+ -+ /* Build mcache programming parameters per plane per pipe */ -+ for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { -+ pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; -+ -+ mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_prog_idx]; -+ memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); -+ mcache_config->plane_descriptor = pln_prog->plane_descriptor; -+ mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx]; -+ mcache_config->num_pipes = pln_prog->num_dpps_required; -+ l->build_mcache_programming_params.num_configurations++; -+ -+ if (pln_prog->num_dpps_required == 0) { -+ continue; -+ } -+ -+ num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); -+ if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || -+ dc_main_pipes[0]->plane_state == NULL) -+ continue; -+ -+ /* get config for each pipe */ -+ for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { -+ ASSERT(dc_main_pipes[dc_pipe_index]); -+ dml21_get_pipe_mcache_config(context, dc_main_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); -+ } -+ -+ /* get config for each phantom pipe */ -+ if (pln_prog->phantom_plane.valid && -+ dc_phantom_pipes[0] && -+ dc_main_pipes[0]->stream && -+ dc_phantom_pipes[0]->plane_state) { -+ mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx]; -+ memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); -+ mcache_config->plane_descriptor = pln_prog->plane_descriptor; -+ mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx]; -+ mcache_config->num_pipes = pln_prog->num_dpps_required; -+ l->build_mcache_programming_params.num_configurations++; -+ -+ for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { -+ ASSERT(dc_phantom_pipes[dc_pipe_index]); -+ dml21_get_pipe_mcache_config(context, dc_phantom_pipes[dc_pipe_index], pln_prog, &mcache_config->pipe_configurations[dc_pipe_index]); -+ } -+ -+ /* increment phantom index */ -+ dml_phantom_prog_idx++; -+ } -+ } -+ -+ /* Call to generate mcache programming per plane per pipe for the given display configuration */ -+ dml2_build_mcache_programming(&l->build_mcache_programming_params); -+ -+ /* get per plane per pipe mcache programming */ -+ for (dml_prog_idx = 0; dml_prog_idx < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_prog_idx++) { -+ pln_prog = &dml_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; -+ -+ num_pipes = dml21_find_dc_pipes_for_plane(in_dc, context, dml_ctx, dc_main_pipes, dc_phantom_pipes, dml_prog_idx); -+ if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || -+ dc_main_pipes[0]->plane_state == NULL) -+ continue; -+ -+ /* get config for each pipe */ -+ for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { -+ ASSERT(dc_main_pipes[dc_pipe_index]); -+ if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index]) { -+ memcpy(&dc_main_pipes[dc_pipe_index]->mcache_regs, -+ l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_prog_idx][dc_pipe_index], -+ sizeof(struct dml2_hubp_pipe_mcache_regs)); -+ } -+ } -+ -+ /* get config for each phantom pipe */ -+ if (pln_prog->phantom_plane.valid && -+ dc_phantom_pipes[0] && -+ dc_main_pipes[0]->stream && -+ dc_phantom_pipes[0]->plane_state) { -+ for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { -+ ASSERT(dc_phantom_pipes[dc_pipe_index]); -+ if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) { -+ memcpy(&dc_phantom_pipes[dc_pipe_index]->mcache_regs, -+ l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index], -+ sizeof(struct dml2_hubp_pipe_mcache_regs)); -+ } -+ } -+ /* increment phantom index */ -+ dml_phantom_prog_idx++; -+ } -+ } -+} -+ -+ diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h -new file mode 100644 -index 000000000000..2972c6eed21a ---- /dev/null +index 2972c6eed21a..e5d9a456645f 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: MIT -+// -+// Copyright 2024 Advanced Micro Devices, Inc. -+ -+#ifndef _DML21_WRAPPER_FPU_H_ -+#define _DML21_WRAPPER_FPU_H_ -+ -+#include "os_types.h" -+#include "dml_top_soc_parameter_types.h" -+#include "dml_top_display_cfg_types.h" -+ -+struct dc; -+struct dc_state; -+struct dml2_configuration_options; -+struct dml2_context; -+enum dc_validate_mode; -+ -+/** -+ * dml21_init - Initialize DML21 context -+ * @in_dc: dc. -+ * @dml_ctx: DML21 context to initialize. -+ * @config: dml21 configuration options. -+ * -+ * Performs FPU-requiring initialization. Must be called with FPU protection. -+ */ -+void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config); -+ -+/** -+ * dml21_validate - Determines if a display configuration is supported or not. -+ * @in_dc: dc. -+ * @context: dc_state to be validated. -+ * @dml_ctx: dml21 context. -+ * @validate_mode: DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX -+ * will not populate context.res_ctx. -+ * -+ * Based on fast_validate option internally would call: -+ * -+ * -dml21_mode_check_and_programming - for DC_VALIDATE_MODE_AND_PROGRAMMING option -+ * Calculates if dc_state can be supported on the input display -+ * configuration. If supported, generates the necessary HW -+ * programming for the new dc_state. -+ * -+ * -dml21_check_mode_support - for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX option -+ * Calculates if dc_state can be supported for the input display -+ * config. -+ * -+ * Context: Two threads may not invoke this function concurrently unless they reference -+ * separate dc_states for validation. -+ * Return: True if mode is supported, false otherwise. -+ */ -+ -+void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, -+ const struct dml2_configuration_options *config); -+bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, -+ enum dc_validate_mode validate_mode); -+ -+/* Prepare hubp mcache_regs for hubp mcache ID and split coordinate programming */ -+void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx); -+ -+#endif /* _DML21_WRAPPER_FPU_H_ */ +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: MIT + // +-// Copyright 2024 Advanced Micro Devices, Inc. ++// Copyright 2026 Advanced Micro Devices, Inc. + + #ifndef _DML21_WRAPPER_FPU_H_ + #define _DML21_WRAPPER_FPU_H_ diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c -index 307186eb6af0..9215e38343ba 100644 +index 9215e38343ba..f4d45875d0be 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c -@@ -6,7 +6,20 @@ - */ - - #include "dml2_internal_types.h" -+#include "dml2_wrapper.h" - #include "dml2_wrapper_fpu.h" -+#include "dml21_wrapper.h" -+#include "dml21_wrapper_fpu.h" -+ -+#include "dc_fpu.h" -+ -+struct dml2_context *dml2_allocate_memory(void) -+{ -+ struct dml2_context *dml2; -+ -+ DC_RUN_WITH_PREEMPTION_ENABLED(dml2 = vzalloc(sizeof(struct dml2_context))); -+ return dml2; -+} +@@ -13,6 +13,10 @@ - bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2, - enum dc_validate_mode validate_mode) -@@ -23,16 +36,12 @@ bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2 - return out; - } - -- DC_FP_START(); -- - /* Use dml_validate_only for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */ - if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) - out = dml2_validate_only(context, validate_mode); - else - out = dml2_validate_and_build_resource(in_dc, context, validate_mode); + #include "dc_fpu.h" -- DC_FP_END(); -- - return out; ++#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) ++#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code ++#endif // !DC_RUN_WITH_PREEMPTION_ENABLED ++ + struct dml2_context *dml2_allocate_memory(void) + { + struct dml2_context *dml2; +@@ -20,7 +24,6 @@ struct dml2_context *dml2_allocate_memory(void) + DC_RUN_WITH_PREEMPTION_ENABLED(dml2 = vzalloc(sizeof(struct dml2_context))); + return dml2; } - -@@ -70,15 +79,11 @@ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_op - break; - } - -- DC_FP_START(); - - initialize_dml2_ip_params(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.ip); - + bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2, + enum dc_validate_mode validate_mode) + { +@@ -84,6 +87,7 @@ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_op initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc); initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx.states); -- -- DC_FP_END(); ++ } bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2) -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c -index 203eef747262..66624cfc27b1 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c -@@ -31,8 +31,10 @@ - #include "dml2_translation_helper.h" - #include "dml2_mall_phantom.h" - #include "dml2_dc_resource_mgmt.h" --#include "dml21_wrapper.h" -+#include "dml2_wrapper.h" - #include "dml2_wrapper_fpu.h" -+#include "dml21_wrapper.h" -+#include "dml21_wrapper_fpu.h" - - void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out) - { -@@ -546,11 +548,6 @@ void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2) - } - } - --inline struct dml2_context *dml2_allocate_memory(void) --{ -- return (struct dml2_context *) vzalloc(sizeof(struct dml2_context)); --} -- - void dml2_destroy(struct dml2_context *dml2) - { - if (!dml2) -- 2.53.0 diff --git a/SPECS/linux/0086-UPSTREAM-drm-amd-display-Fix-dc_is_fp_enabled-name-m.patch b/SPECS/linux/0086-UPSTREAM-drm-amd-display-Fix-dc_is_fp_enabled-name-m.patch new file mode 100644 index 0000000000..e032411d0b --- /dev/null +++ b/SPECS/linux/0086-UPSTREAM-drm-amd-display-Fix-dc_is_fp_enabled-name-m.patch @@ -0,0 +1,46 @@ +From 134378a7c59f0d83e59a534520ce4f89315994a6 Mon Sep 17 00:00:00 2001 +From: Srinivasan Shanmugam +Date: Mon, 30 Mar 2026 08:26:03 +0530 +Subject: [RUYI PATCH] UPSTREAM: drm/amd/display: Fix dc_is_fp_enabled name + mismatch + +Fix incorrect function name in comment to match dc_is_fp_enabled. + +This function checks if FPU is currently active by reading a counter. +The FPU helpers manage safe usage of FPU in the kernel by tracking when +it starts and stops, avoiding misuse or crashes. + +Fixes: 3539437f354b ("drm/amd/display: Move FPU Guards From DML To DC - Part 1") +Cc: Roman Li +Cc: Alex Hung +Cc: Tom Chung +Cc: Dillon Varone +Cc: Rafal Ostrowski +Cc: Aurabindo Pillai +Signed-off-by: Srinivasan Shanmugam +Reviewed-by: Alex Hung +Signed-off-by: Alex Deucher + +(cherry picked from commit 57ce498faa1e4d358bf44b5df575874c22922786) +Signed-off-by: Xi Ruoyao +Signed-off-by: Han Gao +--- + drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +index 8ba9b4f56f87..172999cc84e5 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +@@ -59,7 +59,7 @@ inline void dc_assert_fp_enabled(void) + } + + /** +- * dc_assert_fp_enabled - Check if FPU protection is enabled ++ * dc_is_fp_enabled - Check if FPU protection is enabled + * + * This function tells if the code is already under FPU protection or not. A + * function that works as an API for a set of FPU operations can use this +-- +2.53.0 + diff --git a/SPECS/linux/0086-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch b/SPECS/linux/0086-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch deleted file mode 100644 index 994eedb336..0000000000 --- a/SPECS/linux/0086-UPSTREAM-drm-amd-display-Move-FPU-Guards-From-DML-To.patch +++ /dev/null @@ -1,121 +0,0 @@ -From d1c805734f00c654953f0c7f1b1db76674d6d762 Mon Sep 17 00:00:00 2001 -From: Rafal Ostrowski -Date: Mon, 23 Feb 2026 06:13:32 +0100 -Subject: [PATCH 086/269] UPSTREAM: drm/amd/display: Move FPU Guards From DML - To DC - Part 3 - -[Why] -FPU guards (DC_FP_START/DC_FP_END) are required to wrap around code that -can manipulates floats. To do this properly, the FPU guards must be used -in a file that is not compiled as a FPU unit. If the guards are used in -a file that is a FPU unit, other sections in the file that aren't guarded -may be end up being compiled to use FPU operations. - -[How] -Added DC_FP_START and DC_FP_END to DC functions that call DML functions -using FPU. - -Reviewed-by: Dillon Varone -Signed-off-by: Rafal Ostrowski -Signed-off-by: Alex Hung -Signed-off-by: Alex Deucher - -(cherry picked from commit 32c1c35b6d8bd8b7ea9ab3d1454b56b605f17dd1) -Signed-off-by: Xi Ruoyao -Signed-off-by: Han Gao ---- - drivers/gpu/drm/amd/display/dc/dml2_0/Makefile | 1 + - drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c | 1 + - .../gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c | 4 +--- - .../gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h | 2 +- - drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c | 6 +++++- - 5 files changed, 9 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile -index a094cfa78260..145ff97ed560 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile -@@ -85,6 +85,7 @@ AMD_DAL_DML2 = $(addprefix $(AMDDALPATH)/dc/dml2_0/,$(DML2)) - - AMD_DISPLAY_FILES += $(AMD_DAL_DML2) - -+ - DML21 := src/dml2_top/dml2_top_interfaces.o - DML21 += src/dml2_top/dml2_top_soc15.o - DML21 += src/dml2_core/dml2_core_dcn4.o -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -index 1a98578f223c..7398f8b69adb 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -@@ -38,6 +38,7 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx) - (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; - - DC_RUN_WITH_PREEMPTION_ENABLED((*dml_ctx)->v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming))); -+ - if (!((*dml_ctx)->v21.mode_programming.programming)) - return false; - -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c -index d5885bbd14c4..f3abfdbe6805 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: MIT - // --// Copyright 2024 Advanced Micro Devices, Inc. -+// Copyright 2026 Advanced Micro Devices, Inc. - - #include "dml2_internal_types.h" - #include "dml_top.h" -@@ -377,5 +377,3 @@ void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context - } - } - } -- -- -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h -index 2972c6eed21a..e5d9a456645f 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.h -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: MIT - // --// Copyright 2024 Advanced Micro Devices, Inc. -+// Copyright 2026 Advanced Micro Devices, Inc. - - #ifndef _DML21_WRAPPER_FPU_H_ - #define _DML21_WRAPPER_FPU_H_ -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c -index 9215e38343ba..f4d45875d0be 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c -@@ -13,6 +13,10 @@ - - #include "dc_fpu.h" - -+#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) -+#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code -+#endif // !DC_RUN_WITH_PREEMPTION_ENABLED -+ - struct dml2_context *dml2_allocate_memory(void) - { - struct dml2_context *dml2; -@@ -20,7 +24,6 @@ struct dml2_context *dml2_allocate_memory(void) - DC_RUN_WITH_PREEMPTION_ENABLED(dml2 = vzalloc(sizeof(struct dml2_context))); - return dml2; - } -- - bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2, - enum dc_validate_mode validate_mode) - { -@@ -84,6 +87,7 @@ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_op - initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc); - - initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx.states); -+ - } - - bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2) --- -2.53.0 - diff --git a/SPECS/linux/0087-UPSTREAM-drm-amd-display-Fix-dc_is_fp_enabled-name-m.patch b/SPECS/linux/0087-UPSTREAM-drm-amd-display-Fix-dc_is_fp_enabled-name-m.patch deleted file mode 100644 index 60900d1ea5..0000000000 --- a/SPECS/linux/0087-UPSTREAM-drm-amd-display-Fix-dc_is_fp_enabled-name-m.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 1504c2ef8d5f42fa4f97aeb696e9258f9a5ba7fb Mon Sep 17 00:00:00 2001 -From: Srinivasan Shanmugam -Date: Mon, 30 Mar 2026 08:26:03 +0530 -Subject: [PATCH 087/269] UPSTREAM: drm/amd/display: Fix dc_is_fp_enabled name - mismatch - -Fix incorrect function name in comment to match dc_is_fp_enabled. - -This function checks if FPU is currently active by reading a counter. -The FPU helpers manage safe usage of FPU in the kernel by tracking when -it starts and stops, avoiding misuse or crashes. - -Fixes: 3539437f354b ("drm/amd/display: Move FPU Guards From DML To DC - Part 1") -Cc: Roman Li -Cc: Alex Hung -Cc: Tom Chung -Cc: Dillon Varone -Cc: Rafal Ostrowski -Cc: Aurabindo Pillai -Signed-off-by: Srinivasan Shanmugam -Reviewed-by: Alex Hung -Signed-off-by: Alex Deucher - -(cherry picked from commit 57ce498faa1e4d358bf44b5df575874c22922786) -Signed-off-by: Xi Ruoyao -Signed-off-by: Han Gao ---- - drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c -index 8ba9b4f56f87..172999cc84e5 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c -@@ -59,7 +59,7 @@ inline void dc_assert_fp_enabled(void) - } - - /** -- * dc_assert_fp_enabled - Check if FPU protection is enabled -+ * dc_is_fp_enabled - Check if FPU protection is enabled - * - * This function tells if the code is already under FPU protection or not. A - * function that works as an API for a set of FPU operations can use this --- -2.53.0 - diff --git a/SPECS/linux/0087-UPSTREAM-drm-amd-display-Fix-fpu-guard-warning.patch b/SPECS/linux/0087-UPSTREAM-drm-amd-display-Fix-fpu-guard-warning.patch new file mode 100644 index 0000000000..93545d02e2 --- /dev/null +++ b/SPECS/linux/0087-UPSTREAM-drm-amd-display-Fix-fpu-guard-warning.patch @@ -0,0 +1,272 @@ +From f65592b337dff36ed7f9e68f9925ad168fc51eea Mon Sep 17 00:00:00 2001 +From: Wayne Lin +Date: Wed, 8 Apr 2026 15:01:27 +0800 +Subject: [RUYI PATCH] UPSTREAM: drm/amd/display: Fix fpu guard warning + +[Why] +Due to improper fpu guarding, we encounter this warning during boot up: + +[ 10.027021] WARNING: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.c:58 at dc_assert_fp_enabled+0x12/0x20 [amdgpu], CPU#8: (udev-worker)/469 +[ 10.027644] Modules linked in: binfmt_misc snd_ctl_led nls_iso8859_1 intel_rapl_msr amd_atl intel_rapl_common amdgpu(+) snd_acp_legacy_mach snd_acp_mach snd_soc_nau8821 snd_acp3x_pdm_dma snd_acp3x_rn snd_soc_dmic snd_sof_amd_acp63 snd_sof_amd_vangogh snd_sof_amd_rembrandt snd_sof_amd_renoir snd_sof_amd_acp snd_sof_pci snd_hda_codec_alc269 snd_sof_xtensa_dsp snd_hda_scodec_component snd_hda_codec_realtek_lib snd_sof snd_hda_codec_generic snd_sof_utils snd_pci_ps snd_soc_acpi_amd_match snd_amd_sdw_acpi soundwire_amd snd_hda_codec_atihdmi soundwire_generic_allocation snd_hda_codec_hdmi soundwire_bus snd_soc_sdca edac_mce_amd snd_hda_intel snd_soc_core snd_hda_codec kvm_amd snd_compress snd_hda_core ac97_bus ee1004 amdxcp snd_pcm_dmaengine snd_intel_dspcfg snd_intel_sdw_acpi kvm drm_panel_backlight_quirks snd_rpl_pci_acp6x gpu_sched snd_hwdep snd_acp_pci irqbypass snd_amd_acpi_mach drm_buddy snd_acp_legacy_common snd_seq_midi ghash_clmulni_intel drm_ttm_helper aesni_intel snd_seq_midi_event snd_pci_acp6x joydev rapl +[ 10.027750] snd_pcm snd_rawmidi ttm snd_seq snd_pci_acp5x drm_exec drm_suballoc_helper snd_seq_device wmi_bmof snd_rn_pci_acp3x drm_display_helper snd_timer snd_acp_config cec snd_soc_acpi snd rc_core i2c_piix4 ccp snd_pci_acp3x i2c_smbus soundcore k10temp i2c_algo_bit spi_amd cdc_mbim input_leds cdc_wdm mac_hid sch_fq_codel msr parport_pc ppdev lp parport efi_pstore nfnetlink dmi_sysfs autofs4 cdc_ncm cdc_ether usbnet mii hid_logitech_hidpp hid_logitech_dj hid_generic nvme nvme_core ahci serio_raw nvme_keyring usbhid ucsi_acpi amd_xgbe nvme_auth libahci hkdf typec_ucsi video typec wmi i2c_hid_acpi i2c_hid hid +[ 10.027853] CPU: 8 UID: 0 PID: 469 Comm: (udev-worker) Not tainted 6.19.0asdn-260408-asdn #1 PREEMPT(voluntary) +[ 10.027858] Hardware name: AMD Crater-RN/Crater-RN, BIOS TCR1004A 03/12/2024 +[ 10.027861] RIP: 0010:dc_assert_fp_enabled+0x12/0x20 [amdgpu] +[ 10.028416] Code: 00 00 00 00 00 0f 1f 00 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 65 8b 05 39 79 cc c4 85 c0 7e 07 31 c0 e9 9e 75 2a c3 <0f> 0b 31 c0 e9 95 75 2a c3 0f 1f 44 00 00 90 90 90 90 90 90 90 90 +[ 10.028420] RSP: 0018:ffffcca10188b348 EFLAGS: 00010246 +[ 10.028425] RAX: 0000000000000000 RBX: ffff88c6077f8000 RCX: 0000000000000000 +[ 10.028428] RDX: ffff88c607d0e400 RSI: ffffffffc204d860 RDI: ffff88c624c00000 +[ 10.028430] RBP: ffffcca10188b3e8 R08: ffff88c624c35c88 R09: 0000000000000000 +[ 10.028433] R10: 0000000000000000 R11: 0000000000000000 R12: ffffcca10188b548 +[ 10.028435] R13: ffff88c60be5bd00 R14: ffffffffc204d860 R15: ffff88c624c00000 +[ 10.028438] FS: 00007c80c2432980(0000) GS:ffff88cdc7464000(0000) knlGS:0000000000000000 +[ 10.028441] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 +[ 10.028443] CR2: 00007866ae013da8 CR3: 000000010a511000 CR4: 0000000000350ef0 +[ 10.028446] Call Trace: +[ 10.028449] +[ 10.028452] ? dcn21_update_bw_bounding_box+0x38/0xb30 [amdgpu] +[ 10.028991] ? srso_return_thunk+0x5/0x5f +[ 10.029001] dc_create+0x37c/0x730 [amdgpu] +[ 10.029505] ? srso_return_thunk+0x5/0x5f +[ 10.029512] amdgpu_dm_init+0x374/0x2ff0 [amdgpu] +[ 10.030053] ? srso_return_thunk+0x5/0x5f +[ 10.030057] ? __irq_work_queue_local+0x61/0xe0 +[ 10.030063] ? srso_return_thunk+0x5/0x5f +[ 10.030067] ? irq_work_queue+0x2f/0x70 +[ 10.030071] ? srso_return_thunk+0x5/0x5f +[ 10.030075] ? __wake_up_klogd+0x75/0xa0 +[ 10.030081] ? srso_return_thunk+0x5/0x5f +[ 10.030085] ? vprintk_emit+0x35b/0x3f0 +[ 10.030102] dm_hw_init+0x1c/0x110 [amdgpu] +[ 10.030625] amdgpu_device_init+0x23e8/0x3210 [amdgpu] +[ 10.031041] ? pci_read+0x55/0x90 +[ 10.031047] ? srso_return_thunk+0x5/0x5f +[ 10.031051] ? pci_read_config_word+0x27/0x50 +[ 10.031057] ? srso_return_thunk+0x5/0x5f +[ 10.031061] ? do_pci_enable_device+0x155/0x180 +[ 10.031068] amdgpu_driver_load_kms+0x1a/0xd0 [amdgpu] +[ 10.031486] amdgpu_pci_probe+0x28c/0x6f0 [amdgpu] +[ 10.031902] local_pci_probe+0x47/0xb0 +[ 10.031908] pci_device_probe+0xf3/0x270 +[ 10.031914] really_probe+0xf1/0x410 +[ 10.031920] __driver_probe_device+0x8c/0x190 +[ 10.031924] driver_probe_device+0x24/0xd0 +[ 10.031928] __driver_attach+0x10b/0x240 +[ 10.031932] ? __pfx___driver_attach+0x10/0x10 +[ 10.031936] bus_for_each_dev+0x8c/0xf0 +[ 10.031942] driver_attach+0x1e/0x30 +[ 10.031947] bus_add_driver+0x160/0x2a0 +[ 10.031952] driver_register+0x5e/0x130 +[ 10.031957] ? __pfx_amdgpu_init+0x10/0x10 [amdgpu] +[ 10.032361] __pci_register_driver+0x5e/0x70 +[ 10.032366] amdgpu_init+0x5d/0xff0 [amdgpu] +[ 10.032768] ? srso_return_thunk+0x5/0x5f +[ 10.032773] do_one_initcall+0x5d/0x340 +[ 10.032783] do_init_module+0x97/0x2c0 +[ 10.032788] load_module+0x2b49/0x2c30 +[ 10.032800] init_module_from_file+0xf4/0x120 +[ 10.032804] ? init_module_from_file+0xf4/0x120 +[ 10.032813] idempotent_init_module+0x10f/0x300 +[ 10.032820] __x64_sys_finit_module+0x73/0xf0 +[ 10.032824] ? srso_return_thunk+0x5/0x5f +[ 10.032829] x64_sys_call+0x1d68/0x26b0 +[ 10.032834] do_syscall_64+0x81/0x500 +[ 10.032839] ? srso_return_thunk+0x5/0x5f +[ 10.032843] ? do_syscall_64+0x2e5/0x500 +[ 10.032848] ? srso_return_thunk+0x5/0x5f +[ 10.032852] ? native_flush_tlb_global+0x95/0xb0 +[ 10.032860] ? srso_return_thunk+0x5/0x5f +[ 10.032864] ? __flush_tlb_all+0x13/0x60 +[ 10.032870] ? srso_return_thunk+0x5/0x5f +[ 10.032874] ? do_flush_tlb_all+0xe/0x20 +[ 10.032879] ? srso_return_thunk+0x5/0x5f +[ 10.032882] ? __flush_smp_call_function_queue+0x9c/0x430 +[ 10.032888] ? srso_return_thunk+0x5/0x5f +[ 10.032897] ? irqentry_exit+0xb2/0x740 +[ 10.032901] ? srso_return_thunk+0x5/0x5f +[ 10.032906] ? srso_return_thunk+0x5/0x5f +[ 10.032911] entry_SYSCALL_64_after_hwframe+0x76/0x7e +[ 10.032915] RIP: 0033:0x7c80c1d3490d +[ 10.032920] Code: ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d d3 f4 0f 00 f7 d8 64 89 01 48 +[ 10.032923] RSP: 002b:00007fff3a12fe28 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 +[ 10.032928] RAX: ffffffffffffffda RBX: 00005c44096804f0 RCX: 00007c80c1d3490d +[ 10.032930] RDX: 0000000000000000 RSI: 00005c4409681690 RDI: 000000000000002b +[ 10.032933] RBP: 00007fff3a12fec0 R08: 0000000000000000 R09: 00005c4409681790 +[ 10.032935] R10: 0000000000000000 R11: 0000000000000246 R12: 00005c4409681690 +[ 10.032937] R13: 0000000000020000 R14: 00005c44094ff7f0 R15: 00005c4409681690 +[ 10.032945] +[ 10.032948] ---[ end trace 0000000000000000 ]--- + +[How] +Add wrapper function to guard fpu properly for dcn21/dcn31/dcn315/dcn316. + +Fixes: 3539437f354b ("drm/amd/display: Move FPU Guards From DML To DC - Part 1") +Reviewed-by: Dillon Varone +Reviewed-by: Rafal Ostrowski +Signed-off-by: Wayne Lin +Signed-off-by: Chenyu Chen +Signed-off-by: Alex Deucher + +(cherry picked from commit 07598c76964a2c73702fa652bcd07ec21088c5ef) +Signed-off-by: Xi Ruoyao +Signed-off-by: Han Gao +--- + drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 +- + drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h | 2 +- + drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 6 +++--- + drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h | 6 +++--- + .../gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c | 7 +++++++ + .../gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c | 7 +++++++ + .../drm/amd/display/dc/resource/dcn315/dcn315_resource.c | 7 +++++++ + .../drm/amd/display/dc/resource/dcn316/dcn316_resource.c | 7 +++++++ + 8 files changed, 36 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +index 7aaf13bbd4e4..eb4a76fc60d6 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +@@ -2398,7 +2398,7 @@ static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_li + return low_pstate_lvl; + } + +-void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++void dcn21_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) + { + struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; + struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h +index aed00039ca62..8b2226c5bbbf 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h +@@ -78,7 +78,7 @@ int dcn21_populate_dml_pipes_from_context(struct dc *dc, + enum dc_validate_mode validate_mode); + bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum + dc_validate_mode, display_e2e_pipe_params_st *pipes); +-void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); ++void dcn21_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params); + + void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params); + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +index 1a28061bb9ff..ad23215da9f8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +@@ -587,7 +587,7 @@ void dcn31_calculate_wm_and_dlg_fp( + context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - total_det; + } + +-void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) + { + struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; + struct clk_limit_table *clk_table = &bw_params->clk_table; +@@ -665,7 +665,7 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params + dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31); + } + +-void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) + { + struct clk_limit_table *clk_table = &bw_params->clk_table; + int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0; +@@ -726,7 +726,7 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param + dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN315); + } + +-void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++void dcn316_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) + { + struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; + struct clk_limit_table *clk_table = &bw_params->clk_table; +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h +index dfcc5d50071e..0b7fcbbfd17b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h +@@ -44,9 +44,9 @@ void dcn31_calculate_wm_and_dlg_fp( + int pipe_cnt, + int vlevel); + +-void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); +-void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); +-void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); ++void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params); ++void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params); ++void dcn316_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params); + int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc); + int dcn_get_approx_det_segs_required_for_pstate( + struct _vcs_dpi_soc_bounding_box_st *soc, +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +index 4333baac96ad..ec88630ae806 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +@@ -1387,6 +1387,13 @@ static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *pla + return dcn20_patch_unknown_plane_state(plane_state); + } + ++static void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++{ ++ DC_FP_START(); ++ dcn21_update_bw_bounding_box_fpu(dc, bw_params); ++ DC_FP_END(); ++} ++ + static const struct resource_funcs dcn21_res_pool_funcs = { + .destroy = dcn21_destroy_resource_pool, + .link_enc_create = dcn21_link_encoder_create, +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +index 4e9c041c707a..96b1ff262d15 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +@@ -1856,6 +1856,13 @@ static struct dc_cap_funcs cap_funcs = { + .get_dcc_compression_cap = dcn20_get_dcc_compression_cap + }; + ++static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++{ ++ DC_FP_START(); ++ dcn31_update_bw_bounding_box_fpu(dc, bw_params); ++ DC_FP_END(); ++} ++ + static struct resource_funcs dcn31_res_pool_funcs = { + .destroy = dcn31_destroy_resource_pool, + .link_enc_create = dcn31_link_encoder_create, +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +index 131a6cd4c735..e1d703ce81d6 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +@@ -1850,6 +1850,13 @@ static struct dc_cap_funcs cap_funcs = { + .get_dcc_compression_cap = dcn20_get_dcc_compression_cap + }; + ++static void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++{ ++ DC_FP_START(); ++ dcn315_update_bw_bounding_box_fpu(dc, bw_params); ++ DC_FP_END(); ++} ++ + static struct resource_funcs dcn315_res_pool_funcs = { + .destroy = dcn315_destroy_resource_pool, + .link_enc_create = dcn31_link_encoder_create, +diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +index c8c0ce6efcfd..682606563e5d 100644 +--- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +@@ -1726,6 +1726,13 @@ static struct dc_cap_funcs cap_funcs = { + .get_dcc_compression_cap = dcn20_get_dcc_compression_cap + }; + ++static void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) ++{ ++ DC_FP_START(); ++ dcn316_update_bw_bounding_box_fpu(dc, bw_params); ++ DC_FP_END(); ++} ++ + static struct resource_funcs dcn316_res_pool_funcs = { + .destroy = dcn316_destroy_resource_pool, + .link_enc_create = dcn31_link_encoder_create, +-- +2.53.0 + diff --git a/SPECS/linux/0088-UPSTREAM-drm-amd-display-Fix-fpu-guard-warning.patch b/SPECS/linux/0088-UPSTREAM-drm-amd-display-Fix-fpu-guard-warning.patch deleted file mode 100644 index 9abd0fd825..0000000000 --- a/SPECS/linux/0088-UPSTREAM-drm-amd-display-Fix-fpu-guard-warning.patch +++ /dev/null @@ -1,272 +0,0 @@ -From f3347cd6f975caa2e4d778d8149f1d0840e93fab Mon Sep 17 00:00:00 2001 -From: Wayne Lin -Date: Wed, 8 Apr 2026 15:01:27 +0800 -Subject: [PATCH 088/269] UPSTREAM: drm/amd/display: Fix fpu guard warning - -[Why] -Due to improper fpu guarding, we encounter this warning during boot up: - -[ 10.027021] WARNING: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.c:58 at dc_assert_fp_enabled+0x12/0x20 [amdgpu], CPU#8: (udev-worker)/469 -[ 10.027644] Modules linked in: binfmt_misc snd_ctl_led nls_iso8859_1 intel_rapl_msr amd_atl intel_rapl_common amdgpu(+) snd_acp_legacy_mach snd_acp_mach snd_soc_nau8821 snd_acp3x_pdm_dma snd_acp3x_rn snd_soc_dmic snd_sof_amd_acp63 snd_sof_amd_vangogh snd_sof_amd_rembrandt snd_sof_amd_renoir snd_sof_amd_acp snd_sof_pci snd_hda_codec_alc269 snd_sof_xtensa_dsp snd_hda_scodec_component snd_hda_codec_realtek_lib snd_sof snd_hda_codec_generic snd_sof_utils snd_pci_ps snd_soc_acpi_amd_match snd_amd_sdw_acpi soundwire_amd snd_hda_codec_atihdmi soundwire_generic_allocation snd_hda_codec_hdmi soundwire_bus snd_soc_sdca edac_mce_amd snd_hda_intel snd_soc_core snd_hda_codec kvm_amd snd_compress snd_hda_core ac97_bus ee1004 amdxcp snd_pcm_dmaengine snd_intel_dspcfg snd_intel_sdw_acpi kvm drm_panel_backlight_quirks snd_rpl_pci_acp6x gpu_sched snd_hwdep snd_acp_pci irqbypass snd_amd_acpi_mach drm_buddy snd_acp_legacy_common snd_seq_midi ghash_clmulni_intel drm_ttm_helper aesni_intel snd_seq_midi_event snd_pci_acp6x joydev rapl -[ 10.027750] snd_pcm snd_rawmidi ttm snd_seq snd_pci_acp5x drm_exec drm_suballoc_helper snd_seq_device wmi_bmof snd_rn_pci_acp3x drm_display_helper snd_timer snd_acp_config cec snd_soc_acpi snd rc_core i2c_piix4 ccp snd_pci_acp3x i2c_smbus soundcore k10temp i2c_algo_bit spi_amd cdc_mbim input_leds cdc_wdm mac_hid sch_fq_codel msr parport_pc ppdev lp parport efi_pstore nfnetlink dmi_sysfs autofs4 cdc_ncm cdc_ether usbnet mii hid_logitech_hidpp hid_logitech_dj hid_generic nvme nvme_core ahci serio_raw nvme_keyring usbhid ucsi_acpi amd_xgbe nvme_auth libahci hkdf typec_ucsi video typec wmi i2c_hid_acpi i2c_hid hid -[ 10.027853] CPU: 8 UID: 0 PID: 469 Comm: (udev-worker) Not tainted 6.19.0asdn-260408-asdn #1 PREEMPT(voluntary) -[ 10.027858] Hardware name: AMD Crater-RN/Crater-RN, BIOS TCR1004A 03/12/2024 -[ 10.027861] RIP: 0010:dc_assert_fp_enabled+0x12/0x20 [amdgpu] -[ 10.028416] Code: 00 00 00 00 00 0f 1f 00 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 65 8b 05 39 79 cc c4 85 c0 7e 07 31 c0 e9 9e 75 2a c3 <0f> 0b 31 c0 e9 95 75 2a c3 0f 1f 44 00 00 90 90 90 90 90 90 90 90 -[ 10.028420] RSP: 0018:ffffcca10188b348 EFLAGS: 00010246 -[ 10.028425] RAX: 0000000000000000 RBX: ffff88c6077f8000 RCX: 0000000000000000 -[ 10.028428] RDX: ffff88c607d0e400 RSI: ffffffffc204d860 RDI: ffff88c624c00000 -[ 10.028430] RBP: ffffcca10188b3e8 R08: ffff88c624c35c88 R09: 0000000000000000 -[ 10.028433] R10: 0000000000000000 R11: 0000000000000000 R12: ffffcca10188b548 -[ 10.028435] R13: ffff88c60be5bd00 R14: ffffffffc204d860 R15: ffff88c624c00000 -[ 10.028438] FS: 00007c80c2432980(0000) GS:ffff88cdc7464000(0000) knlGS:0000000000000000 -[ 10.028441] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 -[ 10.028443] CR2: 00007866ae013da8 CR3: 000000010a511000 CR4: 0000000000350ef0 -[ 10.028446] Call Trace: -[ 10.028449] -[ 10.028452] ? dcn21_update_bw_bounding_box+0x38/0xb30 [amdgpu] -[ 10.028991] ? srso_return_thunk+0x5/0x5f -[ 10.029001] dc_create+0x37c/0x730 [amdgpu] -[ 10.029505] ? srso_return_thunk+0x5/0x5f -[ 10.029512] amdgpu_dm_init+0x374/0x2ff0 [amdgpu] -[ 10.030053] ? srso_return_thunk+0x5/0x5f -[ 10.030057] ? __irq_work_queue_local+0x61/0xe0 -[ 10.030063] ? srso_return_thunk+0x5/0x5f -[ 10.030067] ? irq_work_queue+0x2f/0x70 -[ 10.030071] ? srso_return_thunk+0x5/0x5f -[ 10.030075] ? __wake_up_klogd+0x75/0xa0 -[ 10.030081] ? srso_return_thunk+0x5/0x5f -[ 10.030085] ? vprintk_emit+0x35b/0x3f0 -[ 10.030102] dm_hw_init+0x1c/0x110 [amdgpu] -[ 10.030625] amdgpu_device_init+0x23e8/0x3210 [amdgpu] -[ 10.031041] ? pci_read+0x55/0x90 -[ 10.031047] ? srso_return_thunk+0x5/0x5f -[ 10.031051] ? pci_read_config_word+0x27/0x50 -[ 10.031057] ? srso_return_thunk+0x5/0x5f -[ 10.031061] ? do_pci_enable_device+0x155/0x180 -[ 10.031068] amdgpu_driver_load_kms+0x1a/0xd0 [amdgpu] -[ 10.031486] amdgpu_pci_probe+0x28c/0x6f0 [amdgpu] -[ 10.031902] local_pci_probe+0x47/0xb0 -[ 10.031908] pci_device_probe+0xf3/0x270 -[ 10.031914] really_probe+0xf1/0x410 -[ 10.031920] __driver_probe_device+0x8c/0x190 -[ 10.031924] driver_probe_device+0x24/0xd0 -[ 10.031928] __driver_attach+0x10b/0x240 -[ 10.031932] ? __pfx___driver_attach+0x10/0x10 -[ 10.031936] bus_for_each_dev+0x8c/0xf0 -[ 10.031942] driver_attach+0x1e/0x30 -[ 10.031947] bus_add_driver+0x160/0x2a0 -[ 10.031952] driver_register+0x5e/0x130 -[ 10.031957] ? __pfx_amdgpu_init+0x10/0x10 [amdgpu] -[ 10.032361] __pci_register_driver+0x5e/0x70 -[ 10.032366] amdgpu_init+0x5d/0xff0 [amdgpu] -[ 10.032768] ? srso_return_thunk+0x5/0x5f -[ 10.032773] do_one_initcall+0x5d/0x340 -[ 10.032783] do_init_module+0x97/0x2c0 -[ 10.032788] load_module+0x2b49/0x2c30 -[ 10.032800] init_module_from_file+0xf4/0x120 -[ 10.032804] ? init_module_from_file+0xf4/0x120 -[ 10.032813] idempotent_init_module+0x10f/0x300 -[ 10.032820] __x64_sys_finit_module+0x73/0xf0 -[ 10.032824] ? srso_return_thunk+0x5/0x5f -[ 10.032829] x64_sys_call+0x1d68/0x26b0 -[ 10.032834] do_syscall_64+0x81/0x500 -[ 10.032839] ? srso_return_thunk+0x5/0x5f -[ 10.032843] ? do_syscall_64+0x2e5/0x500 -[ 10.032848] ? srso_return_thunk+0x5/0x5f -[ 10.032852] ? native_flush_tlb_global+0x95/0xb0 -[ 10.032860] ? srso_return_thunk+0x5/0x5f -[ 10.032864] ? __flush_tlb_all+0x13/0x60 -[ 10.032870] ? srso_return_thunk+0x5/0x5f -[ 10.032874] ? do_flush_tlb_all+0xe/0x20 -[ 10.032879] ? srso_return_thunk+0x5/0x5f -[ 10.032882] ? __flush_smp_call_function_queue+0x9c/0x430 -[ 10.032888] ? srso_return_thunk+0x5/0x5f -[ 10.032897] ? irqentry_exit+0xb2/0x740 -[ 10.032901] ? srso_return_thunk+0x5/0x5f -[ 10.032906] ? srso_return_thunk+0x5/0x5f -[ 10.032911] entry_SYSCALL_64_after_hwframe+0x76/0x7e -[ 10.032915] RIP: 0033:0x7c80c1d3490d -[ 10.032920] Code: ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d d3 f4 0f 00 f7 d8 64 89 01 48 -[ 10.032923] RSP: 002b:00007fff3a12fe28 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 -[ 10.032928] RAX: ffffffffffffffda RBX: 00005c44096804f0 RCX: 00007c80c1d3490d -[ 10.032930] RDX: 0000000000000000 RSI: 00005c4409681690 RDI: 000000000000002b -[ 10.032933] RBP: 00007fff3a12fec0 R08: 0000000000000000 R09: 00005c4409681790 -[ 10.032935] R10: 0000000000000000 R11: 0000000000000246 R12: 00005c4409681690 -[ 10.032937] R13: 0000000000020000 R14: 00005c44094ff7f0 R15: 00005c4409681690 -[ 10.032945] -[ 10.032948] ---[ end trace 0000000000000000 ]--- - -[How] -Add wrapper function to guard fpu properly for dcn21/dcn31/dcn315/dcn316. - -Fixes: 3539437f354b ("drm/amd/display: Move FPU Guards From DML To DC - Part 1") -Reviewed-by: Dillon Varone -Reviewed-by: Rafal Ostrowski -Signed-off-by: Wayne Lin -Signed-off-by: Chenyu Chen -Signed-off-by: Alex Deucher - -(cherry picked from commit 07598c76964a2c73702fa652bcd07ec21088c5ef) -Signed-off-by: Xi Ruoyao -Signed-off-by: Han Gao ---- - drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 +- - drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h | 2 +- - drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 6 +++--- - drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h | 6 +++--- - .../gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c | 7 +++++++ - .../gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c | 7 +++++++ - .../drm/amd/display/dc/resource/dcn315/dcn315_resource.c | 7 +++++++ - .../drm/amd/display/dc/resource/dcn316/dcn316_resource.c | 7 +++++++ - 8 files changed, 36 insertions(+), 8 deletions(-) - -diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c -index 7aaf13bbd4e4..eb4a76fc60d6 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c -+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c -@@ -2398,7 +2398,7 @@ static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_li - return low_pstate_lvl; - } - --void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+void dcn21_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) - { - struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; - struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); -diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h -index aed00039ca62..8b2226c5bbbf 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h -+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h -@@ -78,7 +78,7 @@ int dcn21_populate_dml_pipes_from_context(struct dc *dc, - enum dc_validate_mode validate_mode); - bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum - dc_validate_mode, display_e2e_pipe_params_st *pipes); --void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); -+void dcn21_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params); - - void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params); - -diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c -index 1a28061bb9ff..ad23215da9f8 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c -+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c -@@ -587,7 +587,7 @@ void dcn31_calculate_wm_and_dlg_fp( - context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - total_det; - } - --void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) - { - struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; - struct clk_limit_table *clk_table = &bw_params->clk_table; -@@ -665,7 +665,7 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params - dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31); - } - --void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) - { - struct clk_limit_table *clk_table = &bw_params->clk_table; - int i, max_dispclk_mhz = 0, max_dppclk_mhz = 0; -@@ -726,7 +726,7 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param - dml_init_instance(&dc->dml, &dcn3_15_soc, &dcn3_15_ip, DML_PROJECT_DCN315); - } - --void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+void dcn316_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) - { - struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; - struct clk_limit_table *clk_table = &bw_params->clk_table; -diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h -index dfcc5d50071e..0b7fcbbfd17b 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h -+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h -@@ -44,9 +44,9 @@ void dcn31_calculate_wm_and_dlg_fp( - int pipe_cnt, - int vlevel); - --void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); --void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); --void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); -+void dcn31_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params); -+void dcn315_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params); -+void dcn316_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params); - int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc); - int dcn_get_approx_det_segs_required_for_pstate( - struct _vcs_dpi_soc_bounding_box_st *soc, -diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c -index 4333baac96ad..ec88630ae806 100644 ---- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c -@@ -1387,6 +1387,13 @@ static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *pla - return dcn20_patch_unknown_plane_state(plane_state); - } - -+static void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+{ -+ DC_FP_START(); -+ dcn21_update_bw_bounding_box_fpu(dc, bw_params); -+ DC_FP_END(); -+} -+ - static const struct resource_funcs dcn21_res_pool_funcs = { - .destroy = dcn21_destroy_resource_pool, - .link_enc_create = dcn21_link_encoder_create, -diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c -index 4e9c041c707a..96b1ff262d15 100644 ---- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c -@@ -1856,6 +1856,13 @@ static struct dc_cap_funcs cap_funcs = { - .get_dcc_compression_cap = dcn20_get_dcc_compression_cap - }; - -+static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+{ -+ DC_FP_START(); -+ dcn31_update_bw_bounding_box_fpu(dc, bw_params); -+ DC_FP_END(); -+} -+ - static struct resource_funcs dcn31_res_pool_funcs = { - .destroy = dcn31_destroy_resource_pool, - .link_enc_create = dcn31_link_encoder_create, -diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c -index 131a6cd4c735..e1d703ce81d6 100644 ---- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c -@@ -1850,6 +1850,13 @@ static struct dc_cap_funcs cap_funcs = { - .get_dcc_compression_cap = dcn20_get_dcc_compression_cap - }; - -+static void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+{ -+ DC_FP_START(); -+ dcn315_update_bw_bounding_box_fpu(dc, bw_params); -+ DC_FP_END(); -+} -+ - static struct resource_funcs dcn315_res_pool_funcs = { - .destroy = dcn315_destroy_resource_pool, - .link_enc_create = dcn31_link_encoder_create, -diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c -index c8c0ce6efcfd..682606563e5d 100644 ---- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c -@@ -1726,6 +1726,13 @@ static struct dc_cap_funcs cap_funcs = { - .get_dcc_compression_cap = dcn20_get_dcc_compression_cap - }; - -+static void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) -+{ -+ DC_FP_START(); -+ dcn316_update_bw_bounding_box_fpu(dc, bw_params); -+ DC_FP_END(); -+} -+ - static struct resource_funcs dcn316_res_pool_funcs = { - .destroy = dcn316_destroy_resource_pool, - .link_enc_create = dcn31_link_encoder_create, --- -2.53.0 - diff --git a/SPECS/linux/0088-UPSTREAM-drm-amd-display-Move-dml2_destroy-to-non-FP.patch b/SPECS/linux/0088-UPSTREAM-drm-amd-display-Move-dml2_destroy-to-non-FP.patch new file mode 100644 index 0000000000..4f901104b0 --- /dev/null +++ b/SPECS/linux/0088-UPSTREAM-drm-amd-display-Move-dml2_destroy-to-non-FP.patch @@ -0,0 +1,95 @@ +From 5aba73ab30772b737710fcf864858f19e775db94 Mon Sep 17 00:00:00 2001 +From: Rafal Ostrowski +Date: Fri, 10 Apr 2026 09:09:57 +0200 +Subject: [RUYI PATCH] UPSTREAM: drm/amd/display: Move dml2_destroy to non-FPU + compilation unit + +On PREEMPT_RT kernels, vfree() can sleep because spin_lock is +converted to rt_mutex. dml2_destroy() calls vfree() while inside +an FPU-guarded region (preempt_count=2), which is illegal. + +dml2_wrapper_fpu.c is compiled with CC_FLAGS_FPU which defines +_LINUX_FPU_COMPILATION_UNIT, making DC_RUN_WITH_PREEMPTION_ENABLED() +resolve to a no-op. This prevents the macro from cycling FPU +context off/on around vfree(). + +Move dml2_destroy() to dml2_wrapper.c (non-FPU compilation unit) +where DC_RUN_WITH_PREEMPTION_ENABLED() properly cycles DC_FP_END/ +DC_FP_START around vfree(). This pairs it with dml2_allocate_memory() +which already lives there. + +Reviewed-by: Dillon Varone +Signed-off-by: Rafal Ostrowski +Signed-off-by: Chenyu Chen +Signed-off-by: Alex Deucher + +(cherry picked from commit 8bf0cb97edb697dba2515e6452c17c5245111448) +Signed-off-by: Xi Ruoyao +Signed-off-by: Han Gao +--- + .../drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c | 4 ++-- + drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c | 11 +++++++++++ + .../gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c | 10 ---------- + 3 files changed, 13 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c +index 7398f8b69adb..8bed59e976d1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c +@@ -58,8 +58,8 @@ bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const s + + void dml21_destroy(struct dml2_context *dml2) + { +- vfree(dml2->v21.dml_init.dml2_instance); +- vfree(dml2->v21.mode_programming.programming); ++ DC_RUN_WITH_PREEMPTION_ENABLED(vfree(dml2->v21.dml_init.dml2_instance)); ++ DC_RUN_WITH_PREEMPTION_ENABLED(vfree(dml2->v21.mode_programming.programming)); + } + + void dml21_copy(struct dml2_context *dst_dml_ctx, +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c +index f4d45875d0be..6e3611a05c83 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c +@@ -107,6 +107,17 @@ bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options + return true; + } + ++void dml2_destroy(struct dml2_context *dml2) ++{ ++ if (!dml2) ++ return; ++ ++ if (dml2->architecture == dml2_architecture_21) ++ dml21_destroy(dml2); ++ ++ DC_RUN_WITH_PREEMPTION_ENABLED(vfree(dml2)); ++} ++ + void dml2_reinit(const struct dc *in_dc, + const struct dml2_configuration_options *config, + struct dml2_context **dml2) +diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c +index 66624cfc27b1..a14e3004a7b7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c ++++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c +@@ -548,16 +548,6 @@ void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2) + } + } + +-void dml2_destroy(struct dml2_context *dml2) +-{ +- if (!dml2) +- return; +- +- if (dml2->architecture == dml2_architecture_21) +- dml21_destroy(dml2); +- vfree(dml2); +-} +- + void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2, + unsigned int *fclk_change_support, unsigned int *dram_clk_change_support) + { +-- +2.53.0 + diff --git a/SPECS/linux/0089-UPSTREAM-drm-amd-display-Move-dml2_destroy-to-non-FP.patch b/SPECS/linux/0089-UPSTREAM-drm-amd-display-Move-dml2_destroy-to-non-FP.patch deleted file mode 100644 index 6abe63a384..0000000000 --- a/SPECS/linux/0089-UPSTREAM-drm-amd-display-Move-dml2_destroy-to-non-FP.patch +++ /dev/null @@ -1,95 +0,0 @@ -From dca9f035818a772eb7c352d4d7af9a93f52b1a85 Mon Sep 17 00:00:00 2001 -From: Rafal Ostrowski -Date: Fri, 10 Apr 2026 09:09:57 +0200 -Subject: [PATCH 089/269] UPSTREAM: drm/amd/display: Move dml2_destroy to - non-FPU compilation unit - -On PREEMPT_RT kernels, vfree() can sleep because spin_lock is -converted to rt_mutex. dml2_destroy() calls vfree() while inside -an FPU-guarded region (preempt_count=2), which is illegal. - -dml2_wrapper_fpu.c is compiled with CC_FLAGS_FPU which defines -_LINUX_FPU_COMPILATION_UNIT, making DC_RUN_WITH_PREEMPTION_ENABLED() -resolve to a no-op. This prevents the macro from cycling FPU -context off/on around vfree(). - -Move dml2_destroy() to dml2_wrapper.c (non-FPU compilation unit) -where DC_RUN_WITH_PREEMPTION_ENABLED() properly cycles DC_FP_END/ -DC_FP_START around vfree(). This pairs it with dml2_allocate_memory() -which already lives there. - -Reviewed-by: Dillon Varone -Signed-off-by: Rafal Ostrowski -Signed-off-by: Chenyu Chen -Signed-off-by: Alex Deucher - -(cherry picked from commit 8bf0cb97edb697dba2515e6452c17c5245111448) -Signed-off-by: Xi Ruoyao -Signed-off-by: Han Gao ---- - .../drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c | 4 ++-- - drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c | 11 +++++++++++ - .../gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c | 10 ---------- - 3 files changed, 13 insertions(+), 12 deletions(-) - -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -index 7398f8b69adb..8bed59e976d1 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c -@@ -58,8 +58,8 @@ bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const s - - void dml21_destroy(struct dml2_context *dml2) - { -- vfree(dml2->v21.dml_init.dml2_instance); -- vfree(dml2->v21.mode_programming.programming); -+ DC_RUN_WITH_PREEMPTION_ENABLED(vfree(dml2->v21.dml_init.dml2_instance)); -+ DC_RUN_WITH_PREEMPTION_ENABLED(vfree(dml2->v21.mode_programming.programming)); - } - - void dml21_copy(struct dml2_context *dst_dml_ctx, -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c -index f4d45875d0be..6e3611a05c83 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c -@@ -107,6 +107,17 @@ bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options - return true; - } - -+void dml2_destroy(struct dml2_context *dml2) -+{ -+ if (!dml2) -+ return; -+ -+ if (dml2->architecture == dml2_architecture_21) -+ dml21_destroy(dml2); -+ -+ DC_RUN_WITH_PREEMPTION_ENABLED(vfree(dml2)); -+} -+ - void dml2_reinit(const struct dc *in_dc, - const struct dml2_configuration_options *config, - struct dml2_context **dml2) -diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c -index 66624cfc27b1..a14e3004a7b7 100644 ---- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c -+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c -@@ -548,16 +548,6 @@ void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2) - } - } - --void dml2_destroy(struct dml2_context *dml2) --{ -- if (!dml2) -- return; -- -- if (dml2->architecture == dml2_architecture_21) -- dml21_destroy(dml2); -- vfree(dml2); --} -- - void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2, - unsigned int *fclk_change_support, unsigned int *dram_clk_change_support) - { --- -2.53.0 - diff --git a/SPECS/linux/0089-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch b/SPECS/linux/0089-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch new file mode 100644 index 0000000000..e44e3b451e --- /dev/null +++ b/SPECS/linux/0089-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch @@ -0,0 +1,39 @@ +From b13057276442efd583b5a358c5ed98d7da47fe0b Mon Sep 17 00:00:00 2001 +From: Zhengyu He +Date: Thu, 21 May 2026 22:44:45 +0800 +Subject: [RUYI PATCH] UPSTREAM: spi: dt-bindings: fsl-qspi: support SpacemiT + K3 + +Add the SpacemiT K3 QSPI compatible to the fsl-qspi binding. + +K3 and K1 use the same QSPI controller, so document the K3 compatible +with "spacemit,k1-qspi" as fallback. + +Signed-off-by: Cody Kang +Signed-off-by: Zhengyu He +Acked-by: Conor Dooley +Link: https://patch.msgid.link/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-1-52bce26e5fd8@gmail.com +Signed-off-by: Mark Brown +(cherry picked from commit 27cd2dde35b2c3b8659fa18f6a935c61fedee5c1) +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml +index 1d10cfbad86c..504df31a4f90 100644 +--- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml ++++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml +@@ -20,6 +20,9 @@ properties: + - fsl,ls1021a-qspi + - fsl,ls2080a-qspi + - spacemit,k1-qspi ++ - items: ++ - const: spacemit,k3-qspi ++ - const: spacemit,k1-qspi + - items: + - enum: + - fsl,ls1043a-qspi +-- +2.53.0 + diff --git a/SPECS/linux/0090-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch b/SPECS/linux/0090-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch new file mode 100644 index 0000000000..e6a1442424 --- /dev/null +++ b/SPECS/linux/0090-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch @@ -0,0 +1,45 @@ +From 5c8035de1f4ce6da6803b94fd7191b019d32c10c Mon Sep 17 00:00:00 2001 +From: Jiakai Xu +Date: Sun, 17 May 2026 12:44:14 +0000 +Subject: [RUYI PATCH] UPSTREAM: RISC-V: KVM: Fix NULL pointer dereference in + SBI v0.1 SEND_IPI handler + +The SBI v0.1 SEND_IPI handler iterates over the hart mask and calls +kvm_get_vcpu_by_id() to find the target vcpu for each set bit. When a +guest provides a hart mask containing bits for non-existent vcpu_ids, +kvm_get_vcpu_by_id() returns NULL, which is then unconditionally +dereferenced by kvm_riscv_vcpu_set_interrupt(), causing a kernel crash. + +Fix this by adding a NULL check before dereferencing the return value. +If the target vcpu is not found, skip it and continue processing the +remaining valid harts. + +Fixes: a046c2d8578c ("RISC-V: KVM: Reorganize SBI code by moving SBI v0.1 to its own file") +Signed-off-by: Jiakai Xu +Signed-off-by: Jiakai Xu +Assisted-by: OpenClaw:DeepSeek-V3.2 +Reviewed-by: Anup Patel +Link: https://lore.kernel.org/r/20260517124414.420919-1-xujiakai2025@iscas.ac.cn +Signed-off-by: Anup Patel +(cherry picked from commit fdb69d401967fd88d27982a7e4984b2a3a4f0314) +Signed-off-by: Han Gao +--- + arch/riscv/kvm/vcpu_sbi_v01.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c +index 188d5ea5b3b8..c9c323d4577a 100644 +--- a/arch/riscv/kvm/vcpu_sbi_v01.c ++++ b/arch/riscv/kvm/vcpu_sbi_v01.c +@@ -55,6 +55,8 @@ static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, + + for_each_set_bit(i, &hmask, BITS_PER_LONG) { + rvcpu = kvm_get_vcpu_by_id(vcpu->kvm, i); ++ if (!rvcpu) ++ continue; + ret = kvm_riscv_vcpu_set_interrupt(rvcpu, IRQ_VS_SOFT); + if (ret < 0) + break; +-- +2.53.0 + diff --git a/SPECS/linux/0090-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch b/SPECS/linux/0090-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch deleted file mode 100644 index 8ac08f1cc1..0000000000 --- a/SPECS/linux/0090-UPSTREAM-spi-dt-bindings-fsl-qspi-support-SpacemiT-K.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 5ec915293feef5fd6d1716c6691d15f640ea8394 Mon Sep 17 00:00:00 2001 -From: Zhengyu He -Date: Thu, 21 May 2026 22:44:45 +0800 -Subject: [PATCH 090/269] UPSTREAM: spi: dt-bindings: fsl-qspi: support - SpacemiT K3 - -Add the SpacemiT K3 QSPI compatible to the fsl-qspi binding. - -K3 and K1 use the same QSPI controller, so document the K3 compatible -with "spacemit,k1-qspi" as fallback. - -Signed-off-by: Cody Kang -Signed-off-by: Zhengyu He -Acked-by: Conor Dooley -Link: https://patch.msgid.link/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-1-52bce26e5fd8@gmail.com -Signed-off-by: Mark Brown -(cherry picked from commit 27cd2dde35b2c3b8659fa18f6a935c61fedee5c1) -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml -index 1d10cfbad86c..504df31a4f90 100644 ---- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml -+++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml -@@ -20,6 +20,9 @@ properties: - - fsl,ls1021a-qspi - - fsl,ls2080a-qspi - - spacemit,k1-qspi -+ - items: -+ - const: spacemit,k3-qspi -+ - const: spacemit,k1-qspi - - items: - - enum: - - fsl,ls1043a-qspi --- -2.53.0 - diff --git a/SPECS/linux/0091-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch b/SPECS/linux/0091-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch new file mode 100644 index 0000000000..fbac681a57 --- /dev/null +++ b/SPECS/linux/0091-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch @@ -0,0 +1,138 @@ +From 3cd6bd0e3abdbe08f4ac52fbf67489af438a18ac Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:36 +0100 +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Count paired job fence as + dependency in prepare_job() + +The DRM scheduler's prepare_job() callback counts the remaining +non-signaled native dependencies for a job, preventing job submission +until those (plus job data and fence update) can fit in the job queue's +CCCB. + +This means checking which dependencies can be waited upon in the +firmware, i.e. whether they are backed by a UFO object, i.e. whether +their drm_sched_fence::parent has been assigned to a +pvr_queue_fence::base fence. That happens when the job owning the fence +is submitted to the firmware. + +Paired geometry and fragment jobs are submitted at the same time, which +means the dependency between them can't be checked this way before +submission. + +Update job_count_remaining_native_deps() to take into account the +dependency between paired jobs. + +This fixes cases where prepare_job() underestimated the space left in +an almost full fragment CCCB, wrongly unblocking run_job(), which then +returned early without writing the full sequence of commands to the +CCCB. + +The above lead to kernel warnings such as the following and potentially +job timeouts (depending on waiters on the missing commands): + + [ 375.702979] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#1: kworker/u16:3/47 + [ 375.703160] Modules linked in: + [ 375.703571] CPU: 1 UID: 0 PID: 47 Comm: kworker/u16:3 Tainted: G W 7.0.0-rc2-g817eb6b11ad5 #40 PREEMPT + [ 375.703613] Tainted: [W]=WARN + [ 375.703627] Hardware name: Texas Instruments AM625 SK (DT) + [ 375.703645] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] + [ 375.703741] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) + [ 375.703764] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] + [ 375.703847] lr : pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] + [ 375.703921] sp : ffff800084a97650 + [ 375.703934] x29: ffff800084a97740 x28: 0000000000000958 x27: ffff80008565d000 + [ 375.703979] x26: 0000000000000030 x25: ffff800084a97680 x24: 0000000000001000 + [ 375.704017] x23: ffff800084a97820 x22: 1ffff00010952ecc x21: 0000000000000008 + [ 375.704056] x20: 00000000000006a8 x19: ffff00002ff7da88 x18: 0000000000000000 + [ 375.704093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 + [ 375.704132] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 + [ 375.704168] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 + [ 375.704206] x8 : 00000000f2f2f200 x7 : ffff700010952ecc x6 : 0000000000000008 + [ 375.704243] x5 : 0000000000000000 x4 : 1ffff00010acba00 x3 : 0000000000000000 + [ 375.704279] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f + [ 375.704317] Call trace: + [ 375.704331] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) + [ 375.704411] pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] + [ 375.704487] pvr_queue_run_job+0x3a4/0x990 [powervr] + [ 375.704562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] + [ 375.704623] process_one_work+0x520/0x1288 + [ 375.704658] worker_thread+0x3f0/0xb3c + [ 375.704680] kthread+0x334/0x3d8 + [ 375.704706] ret_from_fork+0x10/0x20 + [ 375.704736] ---[ end trace 0000000000000000 ]--- + +Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") +Cc: stable@vger.kernel.org +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-1-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 9cd74f935306cd857f46686975c43383e1d95f94 + https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 27 +++++++++++++++++++++---- + 1 file changed, 23 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index dd88949f6194..836feaa0b295 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -179,7 +179,7 @@ static const struct dma_fence_ops pvr_queue_job_fence_ops = { + + /** + * to_pvr_queue_job_fence() - Return a pvr_queue_fence object if the fence is +- * backed by a UFO. ++ * already backed by a UFO. + * @f: The dma_fence to turn into a pvr_queue_fence. + * + * Return: +@@ -356,6 +356,15 @@ static u32 job_cmds_size(struct pvr_job *job, u32 ufo_wait_count) + pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len); + } + ++static bool ++is_paired_job_fence(struct dma_fence *fence, struct pvr_job *job) ++{ ++ /* This assumes "fence" is one of "job"'s drm_sched_job::dependencies */ ++ return job->type == DRM_PVR_JOB_TYPE_FRAGMENT && ++ job->paired_job && ++ &job->paired_job->base.s_fence->scheduled == fence; ++} ++ + /** + * job_count_remaining_native_deps() - Count the number of non-signaled native dependencies. + * @job: Job to operate on. +@@ -371,6 +380,17 @@ static unsigned long job_count_remaining_native_deps(struct pvr_job *job) + xa_for_each(&job->base.dependencies, index, fence) { + struct pvr_queue_fence *jfence; + ++ if (is_paired_job_fence(fence, job)) { ++ /* ++ * A fence between paired jobs won't resolve to a pvr_queue_fence (i.e. ++ * be backed by a UFO) until the jobs have been submitted, together. ++ * The submitting code will insert a partial render fence command for this. ++ */ ++ WARN_ON(dma_fence_is_signaled(fence)); ++ remaining_count++; ++ continue; ++ } ++ + jfence = to_pvr_queue_job_fence(fence); + if (!jfence) + continue; +@@ -630,9 +650,8 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + if (!jfence) + continue; + +- /* Skip the partial render fence, we will place it at the end. */ +- if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job && +- &job->paired_job->base.s_fence->scheduled == fence) ++ /* This fence will be placed last, as partial render fence. */ ++ if (is_paired_job_fence(fence, job)) + continue; + + if (dma_fence_is_signaled(&jfence->base)) +-- +2.53.0 + diff --git a/SPECS/linux/0091-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch b/SPECS/linux/0091-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch deleted file mode 100644 index b941ac8653..0000000000 --- a/SPECS/linux/0091-UPSTREAM-RISC-V-KVM-Fix-NULL-pointer-dereference-in-.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 43ea280e7d9cbb6f77bcb9e7c8cc486a16f778d7 Mon Sep 17 00:00:00 2001 -From: Jiakai Xu -Date: Sun, 17 May 2026 12:44:14 +0000 -Subject: [PATCH 091/269] UPSTREAM: RISC-V: KVM: Fix NULL pointer dereference - in SBI v0.1 SEND_IPI handler - -The SBI v0.1 SEND_IPI handler iterates over the hart mask and calls -kvm_get_vcpu_by_id() to find the target vcpu for each set bit. When a -guest provides a hart mask containing bits for non-existent vcpu_ids, -kvm_get_vcpu_by_id() returns NULL, which is then unconditionally -dereferenced by kvm_riscv_vcpu_set_interrupt(), causing a kernel crash. - -Fix this by adding a NULL check before dereferencing the return value. -If the target vcpu is not found, skip it and continue processing the -remaining valid harts. - -Fixes: a046c2d8578c ("RISC-V: KVM: Reorganize SBI code by moving SBI v0.1 to its own file") -Signed-off-by: Jiakai Xu -Signed-off-by: Jiakai Xu -Assisted-by: OpenClaw:DeepSeek-V3.2 -Reviewed-by: Anup Patel -Link: https://lore.kernel.org/r/20260517124414.420919-1-xujiakai2025@iscas.ac.cn -Signed-off-by: Anup Patel -(cherry picked from commit fdb69d401967fd88d27982a7e4984b2a3a4f0314) -Signed-off-by: Han Gao ---- - arch/riscv/kvm/vcpu_sbi_v01.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/riscv/kvm/vcpu_sbi_v01.c b/arch/riscv/kvm/vcpu_sbi_v01.c -index 188d5ea5b3b8..c9c323d4577a 100644 ---- a/arch/riscv/kvm/vcpu_sbi_v01.c -+++ b/arch/riscv/kvm/vcpu_sbi_v01.c -@@ -55,6 +55,8 @@ static int kvm_sbi_ext_v01_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, - - for_each_set_bit(i, &hmask, BITS_PER_LONG) { - rvcpu = kvm_get_vcpu_by_id(vcpu->kvm, i); -+ if (!rvcpu) -+ continue; - ret = kvm_riscv_vcpu_set_interrupt(rvcpu, IRQ_VS_SOFT); - if (ret < 0) - break; --- -2.53.0 - diff --git a/SPECS/linux/0092-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch b/SPECS/linux/0092-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch deleted file mode 100644 index 6d53177813..0000000000 --- a/SPECS/linux/0092-FROMGIT-drm-imagination-Count-paired-job-fence-as-de.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 69e51f88e3011f83d1134588f24cd8cbea380400 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:36 +0100 -Subject: [PATCH 092/269] FROMGIT: drm/imagination: Count paired job fence as - dependency in prepare_job() - -The DRM scheduler's prepare_job() callback counts the remaining -non-signaled native dependencies for a job, preventing job submission -until those (plus job data and fence update) can fit in the job queue's -CCCB. - -This means checking which dependencies can be waited upon in the -firmware, i.e. whether they are backed by a UFO object, i.e. whether -their drm_sched_fence::parent has been assigned to a -pvr_queue_fence::base fence. That happens when the job owning the fence -is submitted to the firmware. - -Paired geometry and fragment jobs are submitted at the same time, which -means the dependency between them can't be checked this way before -submission. - -Update job_count_remaining_native_deps() to take into account the -dependency between paired jobs. - -This fixes cases where prepare_job() underestimated the space left in -an almost full fragment CCCB, wrongly unblocking run_job(), which then -returned early without writing the full sequence of commands to the -CCCB. - -The above lead to kernel warnings such as the following and potentially -job timeouts (depending on waiters on the missing commands): - - [ 375.702979] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#1: kworker/u16:3/47 - [ 375.703160] Modules linked in: - [ 375.703571] CPU: 1 UID: 0 PID: 47 Comm: kworker/u16:3 Tainted: G W 7.0.0-rc2-g817eb6b11ad5 #40 PREEMPT - [ 375.703613] Tainted: [W]=WARN - [ 375.703627] Hardware name: Texas Instruments AM625 SK (DT) - [ 375.703645] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] - [ 375.703741] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) - [ 375.703764] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] - [ 375.703847] lr : pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] - [ 375.703921] sp : ffff800084a97650 - [ 375.703934] x29: ffff800084a97740 x28: 0000000000000958 x27: ffff80008565d000 - [ 375.703979] x26: 0000000000000030 x25: ffff800084a97680 x24: 0000000000001000 - [ 375.704017] x23: ffff800084a97820 x22: 1ffff00010952ecc x21: 0000000000000008 - [ 375.704056] x20: 00000000000006a8 x19: ffff00002ff7da88 x18: 0000000000000000 - [ 375.704093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 - [ 375.704132] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 - [ 375.704168] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 - [ 375.704206] x8 : 00000000f2f2f200 x7 : ffff700010952ecc x6 : 0000000000000008 - [ 375.704243] x5 : 0000000000000000 x4 : 1ffff00010acba00 x3 : 0000000000000000 - [ 375.704279] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f - [ 375.704317] Call trace: - [ 375.704331] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) - [ 375.704411] pvr_queue_submit_job_to_cccb+0x578/0xa70 [powervr] - [ 375.704487] pvr_queue_run_job+0x3a4/0x990 [powervr] - [ 375.704562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] - [ 375.704623] process_one_work+0x520/0x1288 - [ 375.704658] worker_thread+0x3f0/0xb3c - [ 375.704680] kthread+0x334/0x3d8 - [ 375.704706] ret_from_fork+0x10/0x20 - [ 375.704736] ---[ end trace 0000000000000000 ]--- - -Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") -Cc: stable@vger.kernel.org -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-1-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 9cd74f935306cd857f46686975c43383e1d95f94 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 27 +++++++++++++++++++++---- - 1 file changed, 23 insertions(+), 4 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index dd88949f6194..836feaa0b295 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -179,7 +179,7 @@ static const struct dma_fence_ops pvr_queue_job_fence_ops = { - - /** - * to_pvr_queue_job_fence() - Return a pvr_queue_fence object if the fence is -- * backed by a UFO. -+ * already backed by a UFO. - * @f: The dma_fence to turn into a pvr_queue_fence. - * - * Return: -@@ -356,6 +356,15 @@ static u32 job_cmds_size(struct pvr_job *job, u32 ufo_wait_count) - pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len); - } - -+static bool -+is_paired_job_fence(struct dma_fence *fence, struct pvr_job *job) -+{ -+ /* This assumes "fence" is one of "job"'s drm_sched_job::dependencies */ -+ return job->type == DRM_PVR_JOB_TYPE_FRAGMENT && -+ job->paired_job && -+ &job->paired_job->base.s_fence->scheduled == fence; -+} -+ - /** - * job_count_remaining_native_deps() - Count the number of non-signaled native dependencies. - * @job: Job to operate on. -@@ -371,6 +380,17 @@ static unsigned long job_count_remaining_native_deps(struct pvr_job *job) - xa_for_each(&job->base.dependencies, index, fence) { - struct pvr_queue_fence *jfence; - -+ if (is_paired_job_fence(fence, job)) { -+ /* -+ * A fence between paired jobs won't resolve to a pvr_queue_fence (i.e. -+ * be backed by a UFO) until the jobs have been submitted, together. -+ * The submitting code will insert a partial render fence command for this. -+ */ -+ WARN_ON(dma_fence_is_signaled(fence)); -+ remaining_count++; -+ continue; -+ } -+ - jfence = to_pvr_queue_job_fence(fence); - if (!jfence) - continue; -@@ -630,9 +650,8 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - if (!jfence) - continue; - -- /* Skip the partial render fence, we will place it at the end. */ -- if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job && -- &job->paired_job->base.s_fence->scheduled == fence) -+ /* This fence will be placed last, as partial render fence. */ -+ if (is_paired_job_fence(fence, job)) - continue; - - if (dma_fence_is_signaled(&jfence->base)) --- -2.53.0 - diff --git a/SPECS/linux/0092-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch b/SPECS/linux/0092-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch new file mode 100644 index 0000000000..6e773fbb07 --- /dev/null +++ b/SPECS/linux/0092-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch @@ -0,0 +1,161 @@ +From 6dd7524e32972a6684d9ea52b45a39acb09abd6e Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:37 +0100 +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Fit paired fragment job in the + correct CCCB + +For geometry jobs with a paired fragment job, at the moment, the +DRM scheduler's prepare_job() callback: + +- checks for internal (driver) dependencies for the geometry job; +- calls into pvr_queue_get_paired_frag_job_dep() to check for external + dependencies for the fragment job (the two jobs are submitted together + but the common scheduler code doesn't know about it, so this needs to + be done at this point in time); +- calls into the prepare_job() callback again, but for the fragment job, + to check its internal dependencies as well, passing the fragment job's + drm_sched_job and the geometry job's drm_sched_entity / pvr_queue. + +The problem with the last step is that pvr_queue_prepare_job() doesn't +always take the mismatched fragment job and geometry queue into account, +in particular when checking whether there is space for the fragment +command to be submitted, so the code ends up checking for space in the +geometry (i.e. wrong) CCCB. +The rest of the nested prepare_job() callback happens to work fine at +the moment as the other internal dependencies are not relevant for a +paired fragment job. + +Move the initialisation of a paired fragment job's done fence and CCCB +fence to pvr_queue_get_paired_frag_job_dep(), inferring the correct +queue from the fragment job itself. + +This fixes cases where prepare_job() wrongly assumed that there was +enough space for a paired fragment job in its own CCCB, unblocking +run_job(), which then returned early without writing the full sequence +of commands to the CCCB. + +The above lead to kernel warnings such as the following and potentially +job timeouts (depending on waiters on the missing commands): + + [ 552.421075] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#2: kworker/u16:5/63 + [ 552.421230] Modules linked in: + [ 552.421592] CPU: 2 UID: 0 PID: 63 Comm: kworker/u16:5 Tainted: G W 7.0.0-rc2-gc5d053e4dccb #39 PREEMPT + [ 552.421625] Tainted: [W]=WARN + [ 552.421637] Hardware name: Texas Instruments AM625 SK (DT) + [ 552.421655] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] + [ 552.421744] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) + [ 552.421766] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] + [ 552.421850] lr : pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] + [ 552.421923] sp : ffff800084c47650 + [ 552.421936] x29: ffff800084c47740 x28: 0000000000000df8 x27: ffff800088a77000 + [ 552.421979] x26: 0000000000000030 x25: ffff800084c47680 x24: 0000000000001000 + [ 552.422017] x23: ffff800084c47820 x22: 1ffff00010988ecc x21: 0000000000000008 + [ 552.422055] x20: 0000000000000208 x19: ffff000006ad5a88 x18: 0000000000000000 + [ 552.422093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 + [ 552.422130] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 + [ 552.422167] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 + [ 552.422204] x8 : 00000000f2f2f200 x7 : ffff700010988ecc x6 : 0000000000000008 + [ 552.422241] x5 : 0000000000000000 x4 : 1ffff0001114ee00 x3 : 0000000000000000 + [ 552.422278] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f + [ 552.422316] Call trace: + [ 552.422330] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) + [ 552.422411] pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] + [ 552.422486] pvr_queue_run_job+0x3a4/0x990 [powervr] + [ 552.422562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] + [ 552.422623] process_one_work+0x520/0x1288 + [ 552.422657] worker_thread+0x3f0/0xb3c + [ 552.422679] kthread+0x334/0x3d8 + [ 552.422706] ret_from_fork+0x10/0x20 + +Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") +Cc: stable@vger.kernel.org +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-2-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 4baf9e70cb756d78dd56419f8baee2978a72d0c3 + https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 32 +++++++++++-------------- + 1 file changed, 14 insertions(+), 18 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 836feaa0b295..f1e54e6d940d 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -488,10 +488,11 @@ pvr_queue_get_job_kccb_fence(struct pvr_queue *queue, struct pvr_job *job) + } + + static struct dma_fence * +-pvr_queue_get_paired_frag_job_dep(struct pvr_queue *queue, struct pvr_job *job) ++pvr_queue_get_paired_frag_job_dep(struct pvr_job *job) + { + struct pvr_job *frag_job = job->type == DRM_PVR_JOB_TYPE_GEOMETRY ? + job->paired_job : NULL; ++ struct pvr_queue *frag_queue = frag_job ? frag_job->ctx->queues.fragment : NULL; + struct dma_fence *f; + unsigned long index; + +@@ -510,7 +511,10 @@ pvr_queue_get_paired_frag_job_dep(struct pvr_queue *queue, struct pvr_job *job) + return dma_fence_get(f); + } + +- return frag_job->base.sched->ops->prepare_job(&frag_job->base, &queue->entity); ++ /* Initialize the paired fragment job's done_fence, so we can signal it. */ ++ pvr_queue_job_fence_init(frag_job->done_fence, frag_queue); ++ ++ return pvr_queue_get_job_cccb_fence(frag_queue, frag_job); + } + + /** +@@ -529,11 +533,6 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, + struct pvr_queue *queue = container_of(s_entity, struct pvr_queue, entity); + struct dma_fence *internal_dep = NULL; + +- /* +- * Initialize the done_fence, so we can signal it. This must be done +- * here because otherwise by the time of run_job() the job will end up +- * in the pending list without a valid fence. +- */ + if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { + /* + * This will be called on a paired fragment job after being +@@ -543,18 +542,15 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, + */ + if (job->paired_job->has_pm_ref) + return NULL; +- +- /* +- * In this case we need to use the job's own ctx to initialise +- * the done_fence. The other steps are done in the ctx of the +- * paired geometry job. +- */ +- pvr_queue_job_fence_init(job->done_fence, +- job->ctx->queues.fragment); +- } else { +- pvr_queue_job_fence_init(job->done_fence, queue); + } + ++ /* ++ * Initialize the done_fence, so we can signal it. This must be done ++ * here because otherwise by the time of run_job() the job will end up ++ * in the pending list without a valid fence. ++ */ ++ pvr_queue_job_fence_init(job->done_fence, queue); ++ + /* CCCB fence is used to make sure we have enough space in the CCCB to + * submit our commands. + */ +@@ -575,7 +571,7 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, + + /* The paired job fence should come last, when everything else is ready. */ + if (!internal_dep) +- internal_dep = pvr_queue_get_paired_frag_job_dep(queue, job); ++ internal_dep = pvr_queue_get_paired_frag_job_dep(job); + + return internal_dep; + } +-- +2.53.0 + diff --git a/SPECS/linux/0093-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch b/SPECS/linux/0093-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch deleted file mode 100644 index d57af6d2ca..0000000000 --- a/SPECS/linux/0093-FROMGIT-drm-imagination-Fit-paired-fragment-job-in-t.patch +++ /dev/null @@ -1,161 +0,0 @@ -From 9ee437d02899afa205572331c93a75c1e8cde99d Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:37 +0100 -Subject: [PATCH 093/269] FROMGIT: drm/imagination: Fit paired fragment job in - the correct CCCB - -For geometry jobs with a paired fragment job, at the moment, the -DRM scheduler's prepare_job() callback: - -- checks for internal (driver) dependencies for the geometry job; -- calls into pvr_queue_get_paired_frag_job_dep() to check for external - dependencies for the fragment job (the two jobs are submitted together - but the common scheduler code doesn't know about it, so this needs to - be done at this point in time); -- calls into the prepare_job() callback again, but for the fragment job, - to check its internal dependencies as well, passing the fragment job's - drm_sched_job and the geometry job's drm_sched_entity / pvr_queue. - -The problem with the last step is that pvr_queue_prepare_job() doesn't -always take the mismatched fragment job and geometry queue into account, -in particular when checking whether there is space for the fragment -command to be submitted, so the code ends up checking for space in the -geometry (i.e. wrong) CCCB. -The rest of the nested prepare_job() callback happens to work fine at -the moment as the other internal dependencies are not relevant for a -paired fragment job. - -Move the initialisation of a paired fragment job's done fence and CCCB -fence to pvr_queue_get_paired_frag_job_dep(), inferring the correct -queue from the fragment job itself. - -This fixes cases where prepare_job() wrongly assumed that there was -enough space for a paired fragment job in its own CCCB, unblocking -run_job(), which then returned early without writing the full sequence -of commands to the CCCB. - -The above lead to kernel warnings such as the following and potentially -job timeouts (depending on waiters on the missing commands): - - [ 552.421075] WARNING: drivers/gpu/drm/imagination/pvr_cccb.c:178 at pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr], CPU#2: kworker/u16:5/63 - [ 552.421230] Modules linked in: - [ 552.421592] CPU: 2 UID: 0 PID: 63 Comm: kworker/u16:5 Tainted: G W 7.0.0-rc2-gc5d053e4dccb #39 PREEMPT - [ 552.421625] Tainted: [W]=WARN - [ 552.421637] Hardware name: Texas Instruments AM625 SK (DT) - [ 552.421655] Workqueue: powervr-sched drm_sched_run_job_work [gpu_sched] - [ 552.421744] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) - [ 552.421766] pc : pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] - [ 552.421850] lr : pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] - [ 552.421923] sp : ffff800084c47650 - [ 552.421936] x29: ffff800084c47740 x28: 0000000000000df8 x27: ffff800088a77000 - [ 552.421979] x26: 0000000000000030 x25: ffff800084c47680 x24: 0000000000001000 - [ 552.422017] x23: ffff800084c47820 x22: 1ffff00010988ecc x21: 0000000000000008 - [ 552.422055] x20: 0000000000000208 x19: ffff000006ad5a88 x18: 0000000000000000 - [ 552.422093] x17: 0000000020020000 x16: 0000000000020000 x15: 0000000000000000 - [ 552.422130] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 - [ 552.422167] x11: 000000000000f2f2 x10: 00000000f3000000 x9 : 00000000f3f3f3f3 - [ 552.422204] x8 : 00000000f2f2f200 x7 : ffff700010988ecc x6 : 0000000000000008 - [ 552.422241] x5 : 0000000000000000 x4 : 1ffff0001114ee00 x3 : 0000000000000000 - [ 552.422278] x2 : 0000000000000007 x1 : 0000000000000fff x0 : 000000000000002f - [ 552.422316] Call trace: - [ 552.422330] pvr_cccb_write_command_with_header+0x2c4/0x330 [powervr] (P) - [ 552.422411] pvr_queue_submit_job_to_cccb+0x57c/0xa74 [powervr] - [ 552.422486] pvr_queue_run_job+0x3a4/0x990 [powervr] - [ 552.422562] drm_sched_run_job_work+0x580/0xd48 [gpu_sched] - [ 552.422623] process_one_work+0x520/0x1288 - [ 552.422657] worker_thread+0x3f0/0xb3c - [ 552.422679] kthread+0x334/0x3d8 - [ 552.422706] ret_from_fork+0x10/0x20 - -Fixes: eaf01ee5ba28 ("drm/imagination: Implement job submission and scheduling") -Cc: stable@vger.kernel.org -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-2-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 4baf9e70cb756d78dd56419f8baee2978a72d0c3 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 32 +++++++++++-------------- - 1 file changed, 14 insertions(+), 18 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 836feaa0b295..f1e54e6d940d 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -488,10 +488,11 @@ pvr_queue_get_job_kccb_fence(struct pvr_queue *queue, struct pvr_job *job) - } - - static struct dma_fence * --pvr_queue_get_paired_frag_job_dep(struct pvr_queue *queue, struct pvr_job *job) -+pvr_queue_get_paired_frag_job_dep(struct pvr_job *job) - { - struct pvr_job *frag_job = job->type == DRM_PVR_JOB_TYPE_GEOMETRY ? - job->paired_job : NULL; -+ struct pvr_queue *frag_queue = frag_job ? frag_job->ctx->queues.fragment : NULL; - struct dma_fence *f; - unsigned long index; - -@@ -510,7 +511,10 @@ pvr_queue_get_paired_frag_job_dep(struct pvr_queue *queue, struct pvr_job *job) - return dma_fence_get(f); - } - -- return frag_job->base.sched->ops->prepare_job(&frag_job->base, &queue->entity); -+ /* Initialize the paired fragment job's done_fence, so we can signal it. */ -+ pvr_queue_job_fence_init(frag_job->done_fence, frag_queue); -+ -+ return pvr_queue_get_job_cccb_fence(frag_queue, frag_job); - } - - /** -@@ -529,11 +533,6 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, - struct pvr_queue *queue = container_of(s_entity, struct pvr_queue, entity); - struct dma_fence *internal_dep = NULL; - -- /* -- * Initialize the done_fence, so we can signal it. This must be done -- * here because otherwise by the time of run_job() the job will end up -- * in the pending list without a valid fence. -- */ - if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { - /* - * This will be called on a paired fragment job after being -@@ -543,18 +542,15 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, - */ - if (job->paired_job->has_pm_ref) - return NULL; -- -- /* -- * In this case we need to use the job's own ctx to initialise -- * the done_fence. The other steps are done in the ctx of the -- * paired geometry job. -- */ -- pvr_queue_job_fence_init(job->done_fence, -- job->ctx->queues.fragment); -- } else { -- pvr_queue_job_fence_init(job->done_fence, queue); - } - -+ /* -+ * Initialize the done_fence, so we can signal it. This must be done -+ * here because otherwise by the time of run_job() the job will end up -+ * in the pending list without a valid fence. -+ */ -+ pvr_queue_job_fence_init(job->done_fence, queue); -+ - /* CCCB fence is used to make sure we have enough space in the CCCB to - * submit our commands. - */ -@@ -575,7 +571,7 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, - - /* The paired job fence should come last, when everything else is ready. */ - if (!internal_dep) -- internal_dep = pvr_queue_get_paired_frag_job_dep(queue, job); -+ internal_dep = pvr_queue_get_paired_frag_job_dep(job); - - return internal_dep; - } --- -2.53.0 - diff --git a/SPECS/linux/0093-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch b/SPECS/linux/0093-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch new file mode 100644 index 0000000000..74594178b2 --- /dev/null +++ b/SPECS/linux/0093-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch @@ -0,0 +1,58 @@ +From dd23ef7bdc2ac11bf359ac4e35134cf7437f7aaa Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:38 +0100 +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Skip check on paired job fence + during job submission + +While submitting a paired fragment job, there is no need to manually +look for, and skip, the paired job fence, as the existing logic to +resolve dependencies to pvr_queue_fence objects will have failed to +resolve it already and continued with the next one. + +Point this out where the fence is actually accessed and drop the related +check. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-3-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 18998b3cb7595850b8b2da55adb3fdc7aef8bc22 + https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index f1e54e6d940d..527eae1309d8 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -646,10 +646,6 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + if (!jfence) + continue; + +- /* This fence will be placed last, as partial render fence. */ +- if (is_paired_job_fence(fence, job)) +- continue; +- + if (dma_fence_is_signaled(&jfence->base)) + continue; + +@@ -664,8 +660,13 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + } + } + +- /* Partial render fence goes last. */ + if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { ++ /* ++ * The loop above will only process dependencies backed by a UFO i.e. with ++ * a valid parent fence assigned, but the paired job dependency won't have ++ * one until both jobs have been submitted. Access the parent fence directly ++ * here instead, submitting it last as partial render fence. ++ */ + jfence = to_pvr_queue_job_fence(job->paired_job->done_fence); + if (!WARN_ON(!jfence)) { + pvr_fw_object_get_fw_addr(jfence->queue->timeline_ufo.fw_obj, +-- +2.53.0 + diff --git a/SPECS/linux/0094-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch b/SPECS/linux/0094-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch new file mode 100644 index 0000000000..d34168ca7c --- /dev/null +++ b/SPECS/linux/0094-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch @@ -0,0 +1,90 @@ +From 43271ba3eaad7deddb1dde4c8fd30db70bb45060 Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:39 +0100 +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Rename + pvr_queue_fence_is_ufo_backed() to reflect usage + +This function is only used by the synchronization code to figure out if +a fence belongs to this driver. +Rename it to pvr_queue_fence_is_native() and update its documentation to +reflect its current purpose. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-4-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit c162e655092de8de2e0f7776d72919dd5e3b84f2 + https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 14 +++++++------- + drivers/gpu/drm/imagination/pvr_queue.h | 2 +- + drivers/gpu/drm/imagination/pvr_sync.c | 4 ++-- + 3 files changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 527eae1309d8..df0a110ed96f 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -898,16 +898,16 @@ static const struct drm_sched_backend_ops pvr_queue_sched_ops = { + }; + + /** +- * pvr_queue_fence_is_ufo_backed() - Check if a dma_fence is backed by a UFO object ++ * pvr_queue_fence_is_native() - Check if a dma_fence is native to this driver. + * @f: Fence to test. + * +- * A UFO-backed fence is a fence that can be signaled or waited upon FW-side. +- * pvr_job::done_fence objects are backed by the timeline UFO attached to the queue +- * they are pushed to, but those fences are not directly exposed to the outside +- * world, so we also need to check if the fence we're being passed is a +- * drm_sched_fence that was coming from our driver. ++ * Check if the fence we're being passed is a drm_sched_fence that is coming from this driver. ++ * ++ * It may be a UFO-backed fence i.e. a fence that can be signaled or waited upon FW-side, ++ * such as pvr_job::done_fence objects that are backed by the timeline UFO attached to the queue ++ * they are pushed to. + */ +-bool pvr_queue_fence_is_ufo_backed(struct dma_fence *f) ++bool pvr_queue_fence_is_native(struct dma_fence *f) + { + struct drm_sched_fence *sched_fence = f ? to_drm_sched_fence(f) : NULL; + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.h b/drivers/gpu/drm/imagination/pvr_queue.h +index fc1986d73fc8..4aa72665ce25 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.h ++++ b/drivers/gpu/drm/imagination/pvr_queue.h +@@ -141,7 +141,7 @@ struct pvr_queue { + u64 callstack_addr; + }; + +-bool pvr_queue_fence_is_ufo_backed(struct dma_fence *f); ++bool pvr_queue_fence_is_native(struct dma_fence *f); + + int pvr_queue_job_init(struct pvr_job *job, u64 drm_client_id); + +diff --git a/drivers/gpu/drm/imagination/pvr_sync.c b/drivers/gpu/drm/imagination/pvr_sync.c +index 3582616ff722..757a18b1ab8f 100644 +--- a/drivers/gpu/drm/imagination/pvr_sync.c ++++ b/drivers/gpu/drm/imagination/pvr_sync.c +@@ -211,7 +211,7 @@ pvr_sync_add_dep_to_job(struct drm_sched_job *job, struct dma_fence *f) + int err = 0; + + dma_fence_unwrap_for_each(uf, &iter, f) { +- if (pvr_queue_fence_is_ufo_backed(uf)) ++ if (pvr_queue_fence_is_native(uf)) + native_fence_count++; + } + +@@ -227,7 +227,7 @@ pvr_sync_add_dep_to_job(struct drm_sched_job *job, struct dma_fence *f) + if (err) + continue; + +- if (pvr_queue_fence_is_ufo_backed(uf)) { ++ if (pvr_queue_fence_is_native(uf)) { + struct drm_sched_fence *s_fence = to_drm_sched_fence(uf); + + /* If this is a native dependency, we wait for the scheduled fence, +-- +2.53.0 + diff --git a/SPECS/linux/0094-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch b/SPECS/linux/0094-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch deleted file mode 100644 index 64143f2001..0000000000 --- a/SPECS/linux/0094-FROMGIT-drm-imagination-Skip-check-on-paired-job-fen.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 0dbd21bbbae5d3f96c2f2305e1a2c8f78ff80f4b Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:38 +0100 -Subject: [PATCH 094/269] FROMGIT: drm/imagination: Skip check on paired job - fence during job submission - -While submitting a paired fragment job, there is no need to manually -look for, and skip, the paired job fence, as the existing logic to -resolve dependencies to pvr_queue_fence objects will have failed to -resolve it already and continued with the next one. - -Point this out where the fence is actually accessed and drop the related -check. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-3-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 18998b3cb7595850b8b2da55adb3fdc7aef8bc22 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index f1e54e6d940d..527eae1309d8 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -646,10 +646,6 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - if (!jfence) - continue; - -- /* This fence will be placed last, as partial render fence. */ -- if (is_paired_job_fence(fence, job)) -- continue; -- - if (dma_fence_is_signaled(&jfence->base)) - continue; - -@@ -664,8 +660,13 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - } - } - -- /* Partial render fence goes last. */ - if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { -+ /* -+ * The loop above will only process dependencies backed by a UFO i.e. with -+ * a valid parent fence assigned, but the paired job dependency won't have -+ * one until both jobs have been submitted. Access the parent fence directly -+ * here instead, submitting it last as partial render fence. -+ */ - jfence = to_pvr_queue_job_fence(job->paired_job->done_fence); - if (!WARN_ON(!jfence)) { - pvr_fw_object_get_fw_addr(jfence->queue->timeline_ufo.fw_obj, --- -2.53.0 - diff --git a/SPECS/linux/0095-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch b/SPECS/linux/0095-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch new file mode 100644 index 0000000000..c43b23068b --- /dev/null +++ b/SPECS/linux/0095-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch @@ -0,0 +1,91 @@ +From 8f014ec8d9921b4eb82fdf46c0f5f143823f1ffa Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:40 +0100 +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Rename fence returned by + pvr_queue_job_arm() + +Rename from done_fence to finished_fence, both because the function +returns a drm_sched_fence's finished fence, and to avoid confusion with +the job fence, which is called the same but has a different purpose. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-5-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 5dae1a21f1e7128a19c68212422383f700699d01 + https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_job.c | 8 ++++---- + drivers/gpu/drm/imagination/pvr_sync.c | 4 ++-- + drivers/gpu/drm/imagination/pvr_sync.h | 2 +- + 3 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_job.c b/drivers/gpu/drm/imagination/pvr_job.c +index 0c2f511a6178..dd9f5df01e08 100644 +--- a/drivers/gpu/drm/imagination/pvr_job.c ++++ b/drivers/gpu/drm/imagination/pvr_job.c +@@ -326,7 +326,7 @@ prepare_job_syncs(struct pvr_file *pvr_file, + struct pvr_job_data *job_data, + struct xarray *signal_array) + { +- struct dma_fence *done_fence; ++ struct dma_fence *finished_fence; + int err = pvr_sync_signal_array_collect_ops(signal_array, + from_pvr_file(pvr_file), + job_data->sync_op_count, +@@ -359,13 +359,13 @@ prepare_job_syncs(struct pvr_file *pvr_file, + return err; + } + +- /* We need to arm the job to get the job done fence. */ +- done_fence = pvr_queue_job_arm(job_data->job); ++ /* We need to arm the job to get the job finished fence. */ ++ finished_fence = pvr_queue_job_arm(job_data->job); + + err = pvr_sync_signal_array_update_fences(signal_array, + job_data->sync_op_count, + job_data->sync_ops, +- done_fence); ++ finished_fence); + return err; + } + +diff --git a/drivers/gpu/drm/imagination/pvr_sync.c b/drivers/gpu/drm/imagination/pvr_sync.c +index 757a18b1ab8f..936f840a5221 100644 +--- a/drivers/gpu/drm/imagination/pvr_sync.c ++++ b/drivers/gpu/drm/imagination/pvr_sync.c +@@ -160,7 +160,7 @@ int + pvr_sync_signal_array_update_fences(struct xarray *array, + u32 sync_op_count, + const struct drm_pvr_sync_op *sync_ops, +- struct dma_fence *done_fence) ++ struct dma_fence *finished_fence) + { + for (u32 i = 0; i < sync_op_count; i++) { + struct dma_fence *old_fence; +@@ -175,7 +175,7 @@ pvr_sync_signal_array_update_fences(struct xarray *array, + return -EINVAL; + + old_fence = sig_sync->fence; +- sig_sync->fence = dma_fence_get(done_fence); ++ sig_sync->fence = dma_fence_get(finished_fence); + dma_fence_put(old_fence); + + if (WARN_ON(!sig_sync->fence)) +diff --git a/drivers/gpu/drm/imagination/pvr_sync.h b/drivers/gpu/drm/imagination/pvr_sync.h +index db6ccfda104a..48501ad27794 100644 +--- a/drivers/gpu/drm/imagination/pvr_sync.h ++++ b/drivers/gpu/drm/imagination/pvr_sync.h +@@ -70,7 +70,7 @@ int + pvr_sync_signal_array_update_fences(struct xarray *array, + u32 sync_op_count, + const struct drm_pvr_sync_op *sync_ops, +- struct dma_fence *done_fence); ++ struct dma_fence *finished_fence); + + void + pvr_sync_signal_array_push_fences(struct xarray *array); +-- +2.53.0 + diff --git a/SPECS/linux/0095-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch b/SPECS/linux/0095-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch deleted file mode 100644 index da66ae494e..0000000000 --- a/SPECS/linux/0095-FROMGIT-drm-imagination-Rename-pvr_queue_fence_is_uf.patch +++ /dev/null @@ -1,90 +0,0 @@ -From e8f3bc206ee85d21bb4eae5e98ecef8dd447b761 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:39 +0100 -Subject: [PATCH 095/269] FROMGIT: drm/imagination: Rename - pvr_queue_fence_is_ufo_backed() to reflect usage - -This function is only used by the synchronization code to figure out if -a fence belongs to this driver. -Rename it to pvr_queue_fence_is_native() and update its documentation to -reflect its current purpose. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-4-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit c162e655092de8de2e0f7776d72919dd5e3b84f2 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 14 +++++++------- - drivers/gpu/drm/imagination/pvr_queue.h | 2 +- - drivers/gpu/drm/imagination/pvr_sync.c | 4 ++-- - 3 files changed, 10 insertions(+), 10 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 527eae1309d8..df0a110ed96f 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -898,16 +898,16 @@ static const struct drm_sched_backend_ops pvr_queue_sched_ops = { - }; - - /** -- * pvr_queue_fence_is_ufo_backed() - Check if a dma_fence is backed by a UFO object -+ * pvr_queue_fence_is_native() - Check if a dma_fence is native to this driver. - * @f: Fence to test. - * -- * A UFO-backed fence is a fence that can be signaled or waited upon FW-side. -- * pvr_job::done_fence objects are backed by the timeline UFO attached to the queue -- * they are pushed to, but those fences are not directly exposed to the outside -- * world, so we also need to check if the fence we're being passed is a -- * drm_sched_fence that was coming from our driver. -+ * Check if the fence we're being passed is a drm_sched_fence that is coming from this driver. -+ * -+ * It may be a UFO-backed fence i.e. a fence that can be signaled or waited upon FW-side, -+ * such as pvr_job::done_fence objects that are backed by the timeline UFO attached to the queue -+ * they are pushed to. - */ --bool pvr_queue_fence_is_ufo_backed(struct dma_fence *f) -+bool pvr_queue_fence_is_native(struct dma_fence *f) - { - struct drm_sched_fence *sched_fence = f ? to_drm_sched_fence(f) : NULL; - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.h b/drivers/gpu/drm/imagination/pvr_queue.h -index fc1986d73fc8..4aa72665ce25 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.h -+++ b/drivers/gpu/drm/imagination/pvr_queue.h -@@ -141,7 +141,7 @@ struct pvr_queue { - u64 callstack_addr; - }; - --bool pvr_queue_fence_is_ufo_backed(struct dma_fence *f); -+bool pvr_queue_fence_is_native(struct dma_fence *f); - - int pvr_queue_job_init(struct pvr_job *job, u64 drm_client_id); - -diff --git a/drivers/gpu/drm/imagination/pvr_sync.c b/drivers/gpu/drm/imagination/pvr_sync.c -index 3582616ff722..757a18b1ab8f 100644 ---- a/drivers/gpu/drm/imagination/pvr_sync.c -+++ b/drivers/gpu/drm/imagination/pvr_sync.c -@@ -211,7 +211,7 @@ pvr_sync_add_dep_to_job(struct drm_sched_job *job, struct dma_fence *f) - int err = 0; - - dma_fence_unwrap_for_each(uf, &iter, f) { -- if (pvr_queue_fence_is_ufo_backed(uf)) -+ if (pvr_queue_fence_is_native(uf)) - native_fence_count++; - } - -@@ -227,7 +227,7 @@ pvr_sync_add_dep_to_job(struct drm_sched_job *job, struct dma_fence *f) - if (err) - continue; - -- if (pvr_queue_fence_is_ufo_backed(uf)) { -+ if (pvr_queue_fence_is_native(uf)) { - struct drm_sched_fence *s_fence = to_drm_sched_fence(uf); - - /* If this is a native dependency, we wait for the scheduled fence, --- -2.53.0 - diff --git a/SPECS/linux/0096-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch b/SPECS/linux/0096-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch new file mode 100644 index 0000000000..0e971bf591 --- /dev/null +++ b/SPECS/linux/0096-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch @@ -0,0 +1,72 @@ +From 52422ac4da13b730145d8e78ce1721d6270be75c Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:41 +0100 +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Move repeated job fence check + to its own function + +This should make the code slightly clearer. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-6-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 402562e60c6c1b15ee359ba7ffed907baa886a99 + https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 25 ++++++++++++++++++++----- + 1 file changed, 20 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index df0a110ed96f..4a49d954562e 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -177,6 +177,24 @@ static const struct dma_fence_ops pvr_queue_job_fence_ops = { + .release = pvr_queue_fence_release, + }; + ++/** ++ * pvr_queue_fence_is_ufo_backed() - Check if a dma_fence is backed by a UFO. ++ * @f: The dma_fence to check. ++ * ++ * Return: ++ * * true if the dma_fence is backed by a UFO, or ++ * * false otherwise. ++ */ ++static inline bool ++pvr_queue_fence_is_ufo_backed(struct dma_fence *f) ++{ ++ /* ++ * Currently the only dma_fence backed by a UFO object is the job fence, ++ * e.g. pvr_job::done_fence, wrapped by a pvr_queue_fence object. ++ */ ++ return f && f->ops == &pvr_queue_job_fence_ops; ++} ++ + /** + * to_pvr_queue_job_fence() - Return a pvr_queue_fence object if the fence is + * already backed by a UFO. +@@ -194,7 +212,7 @@ to_pvr_queue_job_fence(struct dma_fence *f) + if (sched_fence) + f = sched_fence->parent; + +- if (f && f->ops == &pvr_queue_job_fence_ops) ++ if (pvr_queue_fence_is_ufo_backed(f)) + return container_of(f, struct pvr_queue_fence, base); + + return NULL; +@@ -915,10 +933,7 @@ bool pvr_queue_fence_is_native(struct dma_fence *f) + sched_fence->sched->ops == &pvr_queue_sched_ops) + return true; + +- if (f && f->ops == &pvr_queue_job_fence_ops) +- return true; +- +- return false; ++ return pvr_queue_fence_is_ufo_backed(f); + } + + /** +-- +2.53.0 + diff --git a/SPECS/linux/0096-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch b/SPECS/linux/0096-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch deleted file mode 100644 index 47d08f0b63..0000000000 --- a/SPECS/linux/0096-FROMGIT-drm-imagination-Rename-fence-returned-by-pvr.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 72b191a84d353cc97af41ead4f4695317b88ecd0 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:40 +0100 -Subject: [PATCH 096/269] FROMGIT: drm/imagination: Rename fence returned by - pvr_queue_job_arm() - -Rename from done_fence to finished_fence, both because the function -returns a drm_sched_fence's finished fence, and to avoid confusion with -the job fence, which is called the same but has a different purpose. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-5-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 5dae1a21f1e7128a19c68212422383f700699d01 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_job.c | 8 ++++---- - drivers/gpu/drm/imagination/pvr_sync.c | 4 ++-- - drivers/gpu/drm/imagination/pvr_sync.h | 2 +- - 3 files changed, 7 insertions(+), 7 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_job.c b/drivers/gpu/drm/imagination/pvr_job.c -index 0c2f511a6178..dd9f5df01e08 100644 ---- a/drivers/gpu/drm/imagination/pvr_job.c -+++ b/drivers/gpu/drm/imagination/pvr_job.c -@@ -326,7 +326,7 @@ prepare_job_syncs(struct pvr_file *pvr_file, - struct pvr_job_data *job_data, - struct xarray *signal_array) - { -- struct dma_fence *done_fence; -+ struct dma_fence *finished_fence; - int err = pvr_sync_signal_array_collect_ops(signal_array, - from_pvr_file(pvr_file), - job_data->sync_op_count, -@@ -359,13 +359,13 @@ prepare_job_syncs(struct pvr_file *pvr_file, - return err; - } - -- /* We need to arm the job to get the job done fence. */ -- done_fence = pvr_queue_job_arm(job_data->job); -+ /* We need to arm the job to get the job finished fence. */ -+ finished_fence = pvr_queue_job_arm(job_data->job); - - err = pvr_sync_signal_array_update_fences(signal_array, - job_data->sync_op_count, - job_data->sync_ops, -- done_fence); -+ finished_fence); - return err; - } - -diff --git a/drivers/gpu/drm/imagination/pvr_sync.c b/drivers/gpu/drm/imagination/pvr_sync.c -index 757a18b1ab8f..936f840a5221 100644 ---- a/drivers/gpu/drm/imagination/pvr_sync.c -+++ b/drivers/gpu/drm/imagination/pvr_sync.c -@@ -160,7 +160,7 @@ int - pvr_sync_signal_array_update_fences(struct xarray *array, - u32 sync_op_count, - const struct drm_pvr_sync_op *sync_ops, -- struct dma_fence *done_fence) -+ struct dma_fence *finished_fence) - { - for (u32 i = 0; i < sync_op_count; i++) { - struct dma_fence *old_fence; -@@ -175,7 +175,7 @@ pvr_sync_signal_array_update_fences(struct xarray *array, - return -EINVAL; - - old_fence = sig_sync->fence; -- sig_sync->fence = dma_fence_get(done_fence); -+ sig_sync->fence = dma_fence_get(finished_fence); - dma_fence_put(old_fence); - - if (WARN_ON(!sig_sync->fence)) -diff --git a/drivers/gpu/drm/imagination/pvr_sync.h b/drivers/gpu/drm/imagination/pvr_sync.h -index db6ccfda104a..48501ad27794 100644 ---- a/drivers/gpu/drm/imagination/pvr_sync.h -+++ b/drivers/gpu/drm/imagination/pvr_sync.h -@@ -70,7 +70,7 @@ int - pvr_sync_signal_array_update_fences(struct xarray *array, - u32 sync_op_count, - const struct drm_pvr_sync_op *sync_ops, -- struct dma_fence *done_fence); -+ struct dma_fence *finished_fence); - - void - pvr_sync_signal_array_push_fences(struct xarray *array); --- -2.53.0 - diff --git a/SPECS/linux/0097-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch b/SPECS/linux/0097-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch deleted file mode 100644 index 0093bcf9ed..0000000000 --- a/SPECS/linux/0097-FROMGIT-drm-imagination-Move-repeated-job-fence-chec.patch +++ /dev/null @@ -1,72 +0,0 @@ -From d8558c3607f492513e6ee7fa6701c6fd0e573362 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:41 +0100 -Subject: [PATCH 097/269] FROMGIT: drm/imagination: Move repeated job fence - check to its own function - -This should make the code slightly clearer. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-6-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 402562e60c6c1b15ee359ba7ffed907baa886a99 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 25 ++++++++++++++++++++----- - 1 file changed, 20 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index df0a110ed96f..4a49d954562e 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -177,6 +177,24 @@ static const struct dma_fence_ops pvr_queue_job_fence_ops = { - .release = pvr_queue_fence_release, - }; - -+/** -+ * pvr_queue_fence_is_ufo_backed() - Check if a dma_fence is backed by a UFO. -+ * @f: The dma_fence to check. -+ * -+ * Return: -+ * * true if the dma_fence is backed by a UFO, or -+ * * false otherwise. -+ */ -+static inline bool -+pvr_queue_fence_is_ufo_backed(struct dma_fence *f) -+{ -+ /* -+ * Currently the only dma_fence backed by a UFO object is the job fence, -+ * e.g. pvr_job::done_fence, wrapped by a pvr_queue_fence object. -+ */ -+ return f && f->ops == &pvr_queue_job_fence_ops; -+} -+ - /** - * to_pvr_queue_job_fence() - Return a pvr_queue_fence object if the fence is - * already backed by a UFO. -@@ -194,7 +212,7 @@ to_pvr_queue_job_fence(struct dma_fence *f) - if (sched_fence) - f = sched_fence->parent; - -- if (f && f->ops == &pvr_queue_job_fence_ops) -+ if (pvr_queue_fence_is_ufo_backed(f)) - return container_of(f, struct pvr_queue_fence, base); - - return NULL; -@@ -915,10 +933,7 @@ bool pvr_queue_fence_is_native(struct dma_fence *f) - sched_fence->sched->ops == &pvr_queue_sched_ops) - return true; - -- if (f && f->ops == &pvr_queue_job_fence_ops) -- return true; -- -- return false; -+ return pvr_queue_fence_is_ufo_backed(f); - } - - /** --- -2.53.0 - diff --git a/SPECS/linux/0097-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch b/SPECS/linux/0097-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch new file mode 100644 index 0000000000..6acf36f266 --- /dev/null +++ b/SPECS/linux/0097-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch @@ -0,0 +1,49 @@ +From 14fed2db734ad9b5ea26b14dd292952c5874d2cb Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:42 +0100 +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Update check to skip + prepare_job() for fragment jobs + +By the time prepare_job() is called on a paired fragment job, the paired +geometry job might already be finished and its PM reference dropped. + +Check the fragment job's PM reference instead which is a bit more likely +to be still set. This is a very minor optimization. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-7-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 5c81eb2970133ad073214eb1e5b0c34a1ae793eb + https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 4a49d954562e..303f4d6cc09e 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -553,12 +553,13 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, + + if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { + /* +- * This will be called on a paired fragment job after being +- * submitted to firmware. We can tell if this is the case and +- * bail early from whether run_job() has been called on the +- * geometry job, which would issue a pm ref. ++ * This will be called on a paired fragment job after being submitted ++ * to the firmware as part of the paired geometry job's submission. ++ * We can tell if this is the case and bail early from whether run_job() ++ * has been called on the geometry job, which would issue a pm ref on ++ * this job as well. + */ +- if (job->paired_job->has_pm_ref) ++ if (job->has_pm_ref) + return NULL; + } + +-- +2.53.0 + diff --git a/SPECS/linux/0098-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch b/SPECS/linux/0098-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch new file mode 100644 index 0000000000..19cf1860d6 --- /dev/null +++ b/SPECS/linux/0098-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch @@ -0,0 +1,141 @@ +From 9000ca766038755f68ac40535f91a63a56a24a7d Mon Sep 17 00:00:00 2001 +From: Alessio Belle +Date: Mon, 30 Mar 2026 08:56:43 +0100 +Subject: [RUYI PATCH] FROMGIT: drm/imagination: Minor improvements to job + submission code documentation + +Mixed list of clarifications and typo fixes. + +Signed-off-by: Alessio Belle +Reviewed-by: Brajesh Gupta +Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-8-7de8c09cef8c@imgtec.com +Signed-off-by: Matt Coster +(cherry picked from commit 62a36c2da774800bef893bc4bf8922fb9c07c1d0 + https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) +Signed-off-by: Han Gao +--- + drivers/gpu/drm/imagination/pvr_queue.c | 38 ++++++++++++------- + .../drm/imagination/pvr_rogue_fwif_shared.h | 10 +---- + 2 files changed, 26 insertions(+), 22 deletions(-) + +diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c +index 303f4d6cc09e..b5bec656d13c 100644 +--- a/drivers/gpu/drm/imagination/pvr_queue.c ++++ b/drivers/gpu/drm/imagination/pvr_queue.c +@@ -200,6 +200,13 @@ pvr_queue_fence_is_ufo_backed(struct dma_fence *f) + * already backed by a UFO. + * @f: The dma_fence to turn into a pvr_queue_fence. + * ++ * This could be called on: ++ * - a job fence directly, in which case it simply returns the containing pvr_queue_fence; ++ * - a drm_sched_fence's scheduled or finished fence, in which case it will first try to follow ++ * the parent pointer to find the job fence (note that the parent pointer is initialized ++ * only after the run_job() callback is called on the drm_sched_fence's owning job); ++ * - any other dma_fence, in which case it will return NULL. ++ * + * Return: + * * A non-NULL pvr_queue_fence object if the dma_fence is backed by a UFO, or + * * NULL otherwise. +@@ -367,11 +374,14 @@ static u32 ufo_cmds_size(u32 elem_count) + + static u32 job_cmds_size(struct pvr_job *job, u32 ufo_wait_count) + { +- /* One UFO cmd for the fence signaling, one UFO cmd per native fence native, +- * and a command for the job itself. ++ /* ++ * One UFO command per native fence this job will be waiting on (unless any are ++ * signaled by the time the job is submitted), plus a command for the job itself, ++ * plus one UFO command for the fence signaling. + */ +- return ufo_cmds_size(1) + ufo_cmds_size(ufo_wait_count) + +- pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len); ++ return ufo_cmds_size(ufo_wait_count) + ++ pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len) + ++ ufo_cmds_size(1); + } + + static bool +@@ -517,12 +527,16 @@ pvr_queue_get_paired_frag_job_dep(struct pvr_job *job) + if (!frag_job) + return NULL; + ++ /* Have the geometry job wait on the paired fragment job's dependencies as well. */ + xa_for_each(&frag_job->base.dependencies, index, f) { + /* Skip already signaled fences. */ + if (dma_fence_is_signaled(f)) + continue; + +- /* Skip our own fence. */ ++ /* ++ * The paired job fence won't be signaled until both jobs have ++ * been submitted, so we can't wait on it to schedule them. ++ */ + if (f == &job->base.s_fence->scheduled) + continue; + +@@ -665,6 +679,7 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + if (!jfence) + continue; + ++ /* Some dependencies might have been signaled since prepare_job() */ + if (dma_fence_is_signaled(&jfence->base)) + continue; + +@@ -714,7 +729,7 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) + pvr_cccb_write_command_with_header(cccb, job->fw_ccb_cmd_type, job->cmd_len, job->cmd, + job->id, job->id); + +- /* Signal the job fence. */ ++ /* Update command to signal the job fence. */ + pvr_fw_object_get_fw_addr(queue->timeline_ufo.fw_obj, &ufos[0].addr); + ufos[0].value = job->done_fence->seqno; + pvr_cccb_write_command_with_header(cccb, ROGUE_FWIF_CCB_CMD_TYPE_UPDATE, +@@ -744,10 +759,8 @@ static struct dma_fence *pvr_queue_run_job(struct drm_sched_job *sched_job) + } + + /* The only kind of jobs that can be paired are geometry and fragment, and +- * we bail out early if we see a fragment job that's paired with a geomtry +- * job. +- * Paired jobs must also target the same context and point to the same +- * HWRT. ++ * we bail out early if we see a fragment job that's paired with a geometry job. ++ * Paired jobs must also target the same context and point to the same HWRT. + */ + if (WARN_ON(job->paired_job && + (job->type != DRM_PVR_JOB_TYPE_GEOMETRY || +@@ -966,9 +979,8 @@ pvr_queue_signal_done_fences(struct pvr_queue *queue) + } + + /** +- * pvr_queue_check_job_waiting_for_cccb_space() - Check if the job waiting for CCCB space +- * can be unblocked +- * pushed to the CCCB ++ * pvr_queue_check_job_waiting_for_cccb_space() - Check if a job waiting for CCCB space ++ * can be unblocked and pushed to the CCCB. + * @queue: Queue to check + * + * If we have a job waiting for CCCB, and this job now fits in the CCCB, we signal +diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h +index 869d904e3649..fe54c1cad7a9 100644 +--- a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h ++++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h +@@ -14,15 +14,7 @@ + + #define ROGUE_NUM_GEOM_CORES_SIZE 2U + +-/* +- * Maximum number of UFOs in a CCB command. +- * The number is based on having 32 sync prims (as originally), plus 32 sync +- * checkpoints. +- * Once the use of sync prims is no longer supported, we will retain +- * the same total (64) as the number of sync checkpoints which may be +- * supporting a fence is not visible to the client driver and has to +- * allow for the number of different timelines involved in fence merges. +- */ ++/* Maximum number of UFOs in a CCB command. */ + #define ROGUE_FWIF_CCB_CMD_MAX_UFOS (32U + 32U) + + /* +-- +2.53.0 + diff --git a/SPECS/linux/0098-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch b/SPECS/linux/0098-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch deleted file mode 100644 index 9e309106b7..0000000000 --- a/SPECS/linux/0098-FROMGIT-drm-imagination-Update-check-to-skip-prepare.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 809e55c67e3046c1ccc3b263331905f522e66803 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:42 +0100 -Subject: [PATCH 098/269] FROMGIT: drm/imagination: Update check to skip - prepare_job() for fragment jobs - -By the time prepare_job() is called on a paired fragment job, the paired -geometry job might already be finished and its PM reference dropped. - -Check the fragment job's PM reference instead which is a bit more likely -to be still set. This is a very minor optimization. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-7-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 5c81eb2970133ad073214eb1e5b0c34a1ae793eb - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 11 ++++++----- - 1 file changed, 6 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 4a49d954562e..303f4d6cc09e 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -553,12 +553,13 @@ pvr_queue_prepare_job(struct drm_sched_job *sched_job, - - if (job->type == DRM_PVR_JOB_TYPE_FRAGMENT && job->paired_job) { - /* -- * This will be called on a paired fragment job after being -- * submitted to firmware. We can tell if this is the case and -- * bail early from whether run_job() has been called on the -- * geometry job, which would issue a pm ref. -+ * This will be called on a paired fragment job after being submitted -+ * to the firmware as part of the paired geometry job's submission. -+ * We can tell if this is the case and bail early from whether run_job() -+ * has been called on the geometry job, which would issue a pm ref on -+ * this job as well. - */ -- if (job->paired_job->has_pm_ref) -+ if (job->has_pm_ref) - return NULL; - } - --- -2.53.0 - diff --git a/SPECS/linux/0099-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch b/SPECS/linux/0099-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch deleted file mode 100644 index e56a639e80..0000000000 --- a/SPECS/linux/0099-FROMGIT-drm-imagination-Minor-improvements-to-job-su.patch +++ /dev/null @@ -1,141 +0,0 @@ -From 6f4479babf597988b85595b1a29b711f80187e51 Mon Sep 17 00:00:00 2001 -From: Alessio Belle -Date: Mon, 30 Mar 2026 08:56:43 +0100 -Subject: [PATCH 099/269] FROMGIT: drm/imagination: Minor improvements to job - submission code documentation - -Mixed list of clarifications and typo fixes. - -Signed-off-by: Alessio Belle -Reviewed-by: Brajesh Gupta -Link: https://patch.msgid.link/20260330-job-submission-fixes-cleanup-v1-8-7de8c09cef8c@imgtec.com -Signed-off-by: Matt Coster -(cherry picked from commit 62a36c2da774800bef893bc4bf8922fb9c07c1d0 - https://anongit.freedesktop.org/git/drm/drm-misc.git drm-misc-next) -Signed-off-by: Han Gao ---- - drivers/gpu/drm/imagination/pvr_queue.c | 38 ++++++++++++------- - .../drm/imagination/pvr_rogue_fwif_shared.h | 10 +---- - 2 files changed, 26 insertions(+), 22 deletions(-) - -diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imagination/pvr_queue.c -index 303f4d6cc09e..b5bec656d13c 100644 ---- a/drivers/gpu/drm/imagination/pvr_queue.c -+++ b/drivers/gpu/drm/imagination/pvr_queue.c -@@ -200,6 +200,13 @@ pvr_queue_fence_is_ufo_backed(struct dma_fence *f) - * already backed by a UFO. - * @f: The dma_fence to turn into a pvr_queue_fence. - * -+ * This could be called on: -+ * - a job fence directly, in which case it simply returns the containing pvr_queue_fence; -+ * - a drm_sched_fence's scheduled or finished fence, in which case it will first try to follow -+ * the parent pointer to find the job fence (note that the parent pointer is initialized -+ * only after the run_job() callback is called on the drm_sched_fence's owning job); -+ * - any other dma_fence, in which case it will return NULL. -+ * - * Return: - * * A non-NULL pvr_queue_fence object if the dma_fence is backed by a UFO, or - * * NULL otherwise. -@@ -367,11 +374,14 @@ static u32 ufo_cmds_size(u32 elem_count) - - static u32 job_cmds_size(struct pvr_job *job, u32 ufo_wait_count) - { -- /* One UFO cmd for the fence signaling, one UFO cmd per native fence native, -- * and a command for the job itself. -+ /* -+ * One UFO command per native fence this job will be waiting on (unless any are -+ * signaled by the time the job is submitted), plus a command for the job itself, -+ * plus one UFO command for the fence signaling. - */ -- return ufo_cmds_size(1) + ufo_cmds_size(ufo_wait_count) + -- pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len); -+ return ufo_cmds_size(ufo_wait_count) + -+ pvr_cccb_get_size_of_cmd_with_hdr(job->cmd_len) + -+ ufo_cmds_size(1); - } - - static bool -@@ -517,12 +527,16 @@ pvr_queue_get_paired_frag_job_dep(struct pvr_job *job) - if (!frag_job) - return NULL; - -+ /* Have the geometry job wait on the paired fragment job's dependencies as well. */ - xa_for_each(&frag_job->base.dependencies, index, f) { - /* Skip already signaled fences. */ - if (dma_fence_is_signaled(f)) - continue; - -- /* Skip our own fence. */ -+ /* -+ * The paired job fence won't be signaled until both jobs have -+ * been submitted, so we can't wait on it to schedule them. -+ */ - if (f == &job->base.s_fence->scheduled) - continue; - -@@ -665,6 +679,7 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - if (!jfence) - continue; - -+ /* Some dependencies might have been signaled since prepare_job() */ - if (dma_fence_is_signaled(&jfence->base)) - continue; - -@@ -714,7 +729,7 @@ static void pvr_queue_submit_job_to_cccb(struct pvr_job *job) - pvr_cccb_write_command_with_header(cccb, job->fw_ccb_cmd_type, job->cmd_len, job->cmd, - job->id, job->id); - -- /* Signal the job fence. */ -+ /* Update command to signal the job fence. */ - pvr_fw_object_get_fw_addr(queue->timeline_ufo.fw_obj, &ufos[0].addr); - ufos[0].value = job->done_fence->seqno; - pvr_cccb_write_command_with_header(cccb, ROGUE_FWIF_CCB_CMD_TYPE_UPDATE, -@@ -744,10 +759,8 @@ static struct dma_fence *pvr_queue_run_job(struct drm_sched_job *sched_job) - } - - /* The only kind of jobs that can be paired are geometry and fragment, and -- * we bail out early if we see a fragment job that's paired with a geomtry -- * job. -- * Paired jobs must also target the same context and point to the same -- * HWRT. -+ * we bail out early if we see a fragment job that's paired with a geometry job. -+ * Paired jobs must also target the same context and point to the same HWRT. - */ - if (WARN_ON(job->paired_job && - (job->type != DRM_PVR_JOB_TYPE_GEOMETRY || -@@ -966,9 +979,8 @@ pvr_queue_signal_done_fences(struct pvr_queue *queue) - } - - /** -- * pvr_queue_check_job_waiting_for_cccb_space() - Check if the job waiting for CCCB space -- * can be unblocked -- * pushed to the CCCB -+ * pvr_queue_check_job_waiting_for_cccb_space() - Check if a job waiting for CCCB space -+ * can be unblocked and pushed to the CCCB. - * @queue: Queue to check - * - * If we have a job waiting for CCCB, and this job now fits in the CCCB, we signal -diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -index 869d904e3649..fe54c1cad7a9 100644 ---- a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h -@@ -14,15 +14,7 @@ - - #define ROGUE_NUM_GEOM_CORES_SIZE 2U - --/* -- * Maximum number of UFOs in a CCB command. -- * The number is based on having 32 sync prims (as originally), plus 32 sync -- * checkpoints. -- * Once the use of sync prims is no longer supported, we will retain -- * the same total (64) as the number of sync checkpoints which may be -- * supporting a fence is not visible to the client driver and has to -- * allow for the number of different timelines involved in fence merges. -- */ -+/* Maximum number of UFOs in a CCB command. */ - #define ROGUE_FWIF_CCB_CMD_MAX_UFOS (32U + 32U) - - /* --- -2.53.0 - diff --git a/SPECS/linux/0099-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch b/SPECS/linux/0099-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch new file mode 100644 index 0000000000..8e1a11be69 --- /dev/null +++ b/SPECS/linux/0099-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch @@ -0,0 +1,48 @@ +From 4bc187a7ae04fd6f14affbe24207e65104ef2873 Mon Sep 17 00:00:00 2001 +From: Li Guan +Date: Thu, 14 May 2026 02:07:21 +0800 +Subject: [RUYI PATCH] FROMGIT: perf riscv: Fix discarded const qualifier in + _get_field() + +The assignment of strrchr() return values to non-const char * variables +triggers a -Werror=discarded-qualifiers warning when building with GCC +14. + +This happens because in newer glibc versions, strrchr() returns a 'const +char *' if the input string is const. + +Properly declare 'line2' and 'nl' as const char * to match the glibc +function signature and ensure type safety. This avoids the need for +explicit type casting and aligns with the design pattern of not +modifying read-only memory in the perf tool. + +Reviewed-by: Ian Rogers +Signed-off-by: Li Guan +Cc: Adrian Hunter +Cc: Namhyung Kim +Cc: Palmer Dabbelt +Cc: Paul Walmsley +Signed-off-by: Arnaldo Carvalho de Melo +(cherry picked from commit 7378b6656aa46fda56f2743d5a7c1f619c2f6f9b + https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git perf-tools-next) +Signed-off-by: Han Gao +--- + tools/perf/arch/riscv/util/header.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c +index 4b839203d4a5..891984e909bd 100644 +--- a/tools/perf/arch/riscv/util/header.c ++++ b/tools/perf/arch/riscv/util/header.c +@@ -19,7 +19,7 @@ + + static char *_get_field(const char *line) + { +- char *line2, *nl; ++ const char *line2, *nl; + + line2 = strrchr(line, ' '); + if (!line2) +-- +2.53.0 + diff --git a/SPECS/linux/0100-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch b/SPECS/linux/0100-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch deleted file mode 100644 index 7fe1e258dc..0000000000 --- a/SPECS/linux/0100-FROMGIT-perf-riscv-Fix-discarded-const-qualifier-in-.patch +++ /dev/null @@ -1,48 +0,0 @@ -From fff3f054f2721439f30dcf585d98548549e45d10 Mon Sep 17 00:00:00 2001 -From: Li Guan -Date: Thu, 14 May 2026 02:07:21 +0800 -Subject: [PATCH 100/269] FROMGIT: perf riscv: Fix discarded const qualifier in - _get_field() - -The assignment of strrchr() return values to non-const char * variables -triggers a -Werror=discarded-qualifiers warning when building with GCC -14. - -This happens because in newer glibc versions, strrchr() returns a 'const -char *' if the input string is const. - -Properly declare 'line2' and 'nl' as const char * to match the glibc -function signature and ensure type safety. This avoids the need for -explicit type casting and aligns with the design pattern of not -modifying read-only memory in the perf tool. - -Reviewed-by: Ian Rogers -Signed-off-by: Li Guan -Cc: Adrian Hunter -Cc: Namhyung Kim -Cc: Palmer Dabbelt -Cc: Paul Walmsley -Signed-off-by: Arnaldo Carvalho de Melo -(cherry picked from commit 7378b6656aa46fda56f2743d5a7c1f619c2f6f9b - https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git perf-tools-next) -Signed-off-by: Han Gao ---- - tools/perf/arch/riscv/util/header.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c -index 4b839203d4a5..891984e909bd 100644 ---- a/tools/perf/arch/riscv/util/header.c -+++ b/tools/perf/arch/riscv/util/header.c -@@ -19,7 +19,7 @@ - - static char *_get_field(const char *line) - { -- char *line2, *nl; -+ const char *line2, *nl; - - line2 = strrchr(line, ' '); - if (!line2) --- -2.53.0 - diff --git a/SPECS/linux/0100-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch b/SPECS/linux/0100-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch new file mode 100644 index 0000000000..52a21aa1f2 --- /dev/null +++ b/SPECS/linux/0100-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch @@ -0,0 +1,185 @@ +From 824b4cc1c11d0573893e0bd4ab0ef33d102dc70d Mon Sep 17 00:00:00 2001 +From: "Guo Ren (Alibaba DAMO Academy)" +Date: Tue, 21 Apr 2026 10:31:40 -0400 +Subject: [RUYI PATCH] FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE + fixup + +The early version of XuanTie C910 core has a store merge buffer +delay problem. The store merge buffer could improve the store queue +performance by merging multi-store requests, but when there are not +continued store requests, the prior single store request would be +waiting in the store queue for a long time. That would cause +significant problems for communication between multi-cores. This +problem was found on sg2042 & th1520 platforms with the qspinlock +lock torture test. + +So appending a fence w.o could immediately flush the store merge +buffer and let other cores see the write result. + +This will apply the WRITE_ONCE errata to handle the non-standard +behavior via appending a fence w.o instruction for WRITE_ONCE(). + +This problem is only observed on the sg2042 hardware platform by +running the lock_torture test program for half an hour. The problem +was not found in the user space application, because interrupt can +break the livelock. + +Acked-by: Arnd Bergmann +Reviewed-by: Alexandre Ghiti +Reviewed-by: Leonardo Bras +Reviewed-by: Inochi Amaoto +Tested-by: Han Gao +Tested-by: Yao Zi +Cc: Chen Wang +Cc: Xiaoguang Xing +Cc: Paul Walmsley +Signed-off-by: Guo Ren (Alibaba DAMO Academy) +Link: https://lore.kernel.org/r/20260421143154.1590156-1-guoren@kernel.org +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig.errata | 17 ++++++++++ + arch/riscv/errata/thead/errata.c | 20 ++++++++++++ + arch/riscv/include/asm/errata_list_vendors.h | 3 +- + arch/riscv/include/asm/rwonce.h | 34 ++++++++++++++++++++ + include/asm-generic/rwonce.h | 2 ++ + 5 files changed, 75 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/include/asm/rwonce.h + +diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata +index 3c945d086c7d..4d3f13522da6 100644 +--- a/arch/riscv/Kconfig.errata ++++ b/arch/riscv/Kconfig.errata +@@ -154,4 +154,21 @@ config ERRATA_THEAD_GHOSTWRITE + + If you don't know what to do here, say "Y". + ++config ERRATA_THEAD_WRITE_ONCE ++ bool "Apply T-Head WRITE_ONCE errata" ++ depends on ERRATA_THEAD ++ default y ++ help ++ The early version of T-Head C9xx cores of sg2042 & th1520 have a store ++ merge buffer delay problem. The store merge buffer could improve the ++ store queue performance by merging multi-store requests, but when there ++ are no continued store requests, the prior single store request would be ++ waiting in the store queue for a long time. That would cause signifi- ++ cant problems for communication between multi-cores. Appending a ++ fence w.o could immediately flush the store merge buffer and let other ++ cores see the write result. ++ ++ This will apply the WRITE_ONCE errata to handle the non-standard beh- ++ avior via appending a fence w.o instruction for WRITE_ONCE(). ++ + endmenu # "CPU errata selection" +diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c +index 0b942183f708..fbe46f2fa8fb 100644 +--- a/arch/riscv/errata/thead/errata.c ++++ b/arch/riscv/errata/thead/errata.c +@@ -168,6 +168,23 @@ static bool errata_probe_ghostwrite(unsigned int stage, + return true; + } + ++static bool errata_probe_write_once(unsigned int stage, ++ unsigned long arch_id, unsigned long impid) ++{ ++ if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE)) ++ return false; ++ ++ /* target-c9xx cores report arch_id and impid as 0 */ ++ if (arch_id != 0 || impid != 0) ++ return false; ++ ++ if (stage == RISCV_ALTERNATIVES_BOOT || ++ stage == RISCV_ALTERNATIVES_MODULE) ++ return true; ++ ++ return false; ++} ++ + static u32 thead_errata_probe(unsigned int stage, + unsigned long archid, unsigned long impid) + { +@@ -183,6 +200,9 @@ static u32 thead_errata_probe(unsigned int stage, + + errata_probe_ghostwrite(stage, archid, impid); + ++ if (errata_probe_write_once(stage, archid, impid)) ++ cpu_req_errata |= BIT(ERRATA_THEAD_WRITE_ONCE); ++ + return cpu_req_errata; + } + +diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h +index ec7eba373437..8fd7c36307e2 100644 +--- a/arch/riscv/include/asm/errata_list_vendors.h ++++ b/arch/riscv/include/asm/errata_list_vendors.h +@@ -18,7 +18,8 @@ + #define ERRATA_THEAD_MAE 0 + #define ERRATA_THEAD_PMU 1 + #define ERRATA_THEAD_GHOSTWRITE 2 +-#define ERRATA_THEAD_NUMBER 3 ++#define ERRATA_THEAD_WRITE_ONCE 3 ++#define ERRATA_THEAD_NUMBER 4 + #endif + + #ifdef CONFIG_ERRATA_MIPS +diff --git a/arch/riscv/include/asm/rwonce.h b/arch/riscv/include/asm/rwonce.h +new file mode 100644 +index 000000000000..081793d4d772 +--- /dev/null ++++ b/arch/riscv/include/asm/rwonce.h +@@ -0,0 +1,34 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifndef __ASM_RWONCE_H ++#define __ASM_RWONCE_H ++ ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) ++ ++#define write_once_fence() \ ++do { \ ++ asm volatile(ALTERNATIVE( \ ++ "nop", \ ++ "fence w, o", \ ++ THEAD_VENDOR_ID, \ ++ ERRATA_THEAD_WRITE_ONCE, \ ++ CONFIG_ERRATA_THEAD_WRITE_ONCE) \ ++ : : : "memory"); \ ++} while (0) ++ ++#define __WRITE_ONCE(x, val) \ ++do { \ ++ *(volatile typeof(x) *)&(x) = (val); \ ++ write_once_fence(); \ ++} while (0) ++ ++#endif /* defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) */ ++ ++#include ++ ++#endif /* __ASM_RWONCE_H */ +diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h +index 52b969c7cef9..4e2d941f15a1 100644 +--- a/include/asm-generic/rwonce.h ++++ b/include/asm-generic/rwonce.h +@@ -50,10 +50,12 @@ + __READ_ONCE(x); \ + }) + ++#ifndef __WRITE_ONCE + #define __WRITE_ONCE(x, val) \ + do { \ + *(volatile typeof(x) *)&(x) = (val); \ + } while (0) ++#endif + + #define WRITE_ONCE(x, val) \ + do { \ +-- +2.53.0 + diff --git a/SPECS/linux/0101-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch b/SPECS/linux/0101-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch new file mode 100644 index 0000000000..8ec35826a2 --- /dev/null +++ b/SPECS/linux/0101-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch @@ -0,0 +1,54 @@ +From 81bcad1f694cf955ef27ce08af5269e0948aa9b9 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 1 Apr 2026 01:56:57 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: Add per-device flag to disable native + PCIe port services + +Add PCI_DEV_FLAGS_NO_PORT_SERVICES to allow quirks to prevent the PCIe +port service driver from probing specific devices. This provides a +per-device equivalent of the global pcie_ports=compat kernel parameter. + +Some platforms have PCIe root ports that break MSI delivery to downstream +devices when native port services (AER, PME, bwctrl, etc.) are active. +The existing pci_host_bridge native_* flags do not cover all services +(notably bwctrl), so a mechanism to skip port driver probing entirely +on a per-device basis is needed. + +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20260331175658.1015829-2-gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/pci/pcie/portdrv.c | 3 +++ + include/linux/pci.h | 2 ++ + 2 files changed, 5 insertions(+) + +diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c +index 2d6aa488fe7b..3386818d200d 100644 +--- a/drivers/pci/pcie/portdrv.c ++++ b/drivers/pci/pcie/portdrv.c +@@ -685,6 +685,9 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = { + static int pcie_portdrv_probe(struct pci_dev *dev, + const struct pci_device_id *id) + { ++ if (dev->dev_flags & PCI_DEV_FLAGS_NO_PORT_SERVICES) ++ return -ENODEV; ++ + int type = pci_pcie_type(dev); + int status; + +diff --git a/include/linux/pci.h b/include/linux/pci.h +index 57e9463e4347..89254d53ff1b 100644 +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -253,6 +253,8 @@ enum pci_dev_flags { + * integrated with the downstream devices and doesn't use real PCI. + */ + PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = (__force pci_dev_flags_t) (1 << 14), ++ /* Do not use native PCIe port services (equivalent to pcie_ports=compat) */ ++ PCI_DEV_FLAGS_NO_PORT_SERVICES = (__force pci_dev_flags_t) (1 << 15), + }; + + enum pci_irq_reroute_variant { +-- +2.53.0 + diff --git a/SPECS/linux/0101-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch b/SPECS/linux/0101-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch deleted file mode 100644 index 810eb880f6..0000000000 --- a/SPECS/linux/0101-FROMLIST-riscv-errata-Add-ERRATA_THEAD_WRITE_ONCE-fi.patch +++ /dev/null @@ -1,185 +0,0 @@ -From 7a3d95daa11682847c590b162fda46eecc325a79 Mon Sep 17 00:00:00 2001 -From: "Guo Ren (Alibaba DAMO Academy)" -Date: Tue, 21 Apr 2026 10:31:40 -0400 -Subject: [PATCH 101/269] FROMLIST: riscv: errata: Add ERRATA_THEAD_WRITE_ONCE - fixup - -The early version of XuanTie C910 core has a store merge buffer -delay problem. The store merge buffer could improve the store queue -performance by merging multi-store requests, but when there are not -continued store requests, the prior single store request would be -waiting in the store queue for a long time. That would cause -significant problems for communication between multi-cores. This -problem was found on sg2042 & th1520 platforms with the qspinlock -lock torture test. - -So appending a fence w.o could immediately flush the store merge -buffer and let other cores see the write result. - -This will apply the WRITE_ONCE errata to handle the non-standard -behavior via appending a fence w.o instruction for WRITE_ONCE(). - -This problem is only observed on the sg2042 hardware platform by -running the lock_torture test program for half an hour. The problem -was not found in the user space application, because interrupt can -break the livelock. - -Acked-by: Arnd Bergmann -Reviewed-by: Alexandre Ghiti -Reviewed-by: Leonardo Bras -Reviewed-by: Inochi Amaoto -Tested-by: Han Gao -Tested-by: Yao Zi -Cc: Chen Wang -Cc: Xiaoguang Xing -Cc: Paul Walmsley -Signed-off-by: Guo Ren (Alibaba DAMO Academy) -Link: https://lore.kernel.org/r/20260421143154.1590156-1-guoren@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/Kconfig.errata | 17 ++++++++++ - arch/riscv/errata/thead/errata.c | 20 ++++++++++++ - arch/riscv/include/asm/errata_list_vendors.h | 3 +- - arch/riscv/include/asm/rwonce.h | 34 ++++++++++++++++++++ - include/asm-generic/rwonce.h | 2 ++ - 5 files changed, 75 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/include/asm/rwonce.h - -diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata -index 3c945d086c7d..4d3f13522da6 100644 ---- a/arch/riscv/Kconfig.errata -+++ b/arch/riscv/Kconfig.errata -@@ -154,4 +154,21 @@ config ERRATA_THEAD_GHOSTWRITE - - If you don't know what to do here, say "Y". - -+config ERRATA_THEAD_WRITE_ONCE -+ bool "Apply T-Head WRITE_ONCE errata" -+ depends on ERRATA_THEAD -+ default y -+ help -+ The early version of T-Head C9xx cores of sg2042 & th1520 have a store -+ merge buffer delay problem. The store merge buffer could improve the -+ store queue performance by merging multi-store requests, but when there -+ are no continued store requests, the prior single store request would be -+ waiting in the store queue for a long time. That would cause signifi- -+ cant problems for communication between multi-cores. Appending a -+ fence w.o could immediately flush the store merge buffer and let other -+ cores see the write result. -+ -+ This will apply the WRITE_ONCE errata to handle the non-standard beh- -+ avior via appending a fence w.o instruction for WRITE_ONCE(). -+ - endmenu # "CPU errata selection" -diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c -index 0b942183f708..fbe46f2fa8fb 100644 ---- a/arch/riscv/errata/thead/errata.c -+++ b/arch/riscv/errata/thead/errata.c -@@ -168,6 +168,23 @@ static bool errata_probe_ghostwrite(unsigned int stage, - return true; - } - -+static bool errata_probe_write_once(unsigned int stage, -+ unsigned long arch_id, unsigned long impid) -+{ -+ if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE)) -+ return false; -+ -+ /* target-c9xx cores report arch_id and impid as 0 */ -+ if (arch_id != 0 || impid != 0) -+ return false; -+ -+ if (stage == RISCV_ALTERNATIVES_BOOT || -+ stage == RISCV_ALTERNATIVES_MODULE) -+ return true; -+ -+ return false; -+} -+ - static u32 thead_errata_probe(unsigned int stage, - unsigned long archid, unsigned long impid) - { -@@ -183,6 +200,9 @@ static u32 thead_errata_probe(unsigned int stage, - - errata_probe_ghostwrite(stage, archid, impid); - -+ if (errata_probe_write_once(stage, archid, impid)) -+ cpu_req_errata |= BIT(ERRATA_THEAD_WRITE_ONCE); -+ - return cpu_req_errata; - } - -diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/include/asm/errata_list_vendors.h -index ec7eba373437..8fd7c36307e2 100644 ---- a/arch/riscv/include/asm/errata_list_vendors.h -+++ b/arch/riscv/include/asm/errata_list_vendors.h -@@ -18,7 +18,8 @@ - #define ERRATA_THEAD_MAE 0 - #define ERRATA_THEAD_PMU 1 - #define ERRATA_THEAD_GHOSTWRITE 2 --#define ERRATA_THEAD_NUMBER 3 -+#define ERRATA_THEAD_WRITE_ONCE 3 -+#define ERRATA_THEAD_NUMBER 4 - #endif - - #ifdef CONFIG_ERRATA_MIPS -diff --git a/arch/riscv/include/asm/rwonce.h b/arch/riscv/include/asm/rwonce.h -new file mode 100644 -index 000000000000..081793d4d772 ---- /dev/null -+++ b/arch/riscv/include/asm/rwonce.h -@@ -0,0 +1,34 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+ -+#ifndef __ASM_RWONCE_H -+#define __ASM_RWONCE_H -+ -+#include -+#include -+#include -+#include -+ -+#if defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) -+ -+#define write_once_fence() \ -+do { \ -+ asm volatile(ALTERNATIVE( \ -+ "nop", \ -+ "fence w, o", \ -+ THEAD_VENDOR_ID, \ -+ ERRATA_THEAD_WRITE_ONCE, \ -+ CONFIG_ERRATA_THEAD_WRITE_ONCE) \ -+ : : : "memory"); \ -+} while (0) -+ -+#define __WRITE_ONCE(x, val) \ -+do { \ -+ *(volatile typeof(x) *)&(x) = (val); \ -+ write_once_fence(); \ -+} while (0) -+ -+#endif /* defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) */ -+ -+#include -+ -+#endif /* __ASM_RWONCE_H */ -diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h -index 52b969c7cef9..4e2d941f15a1 100644 ---- a/include/asm-generic/rwonce.h -+++ b/include/asm-generic/rwonce.h -@@ -50,10 +50,12 @@ - __READ_ONCE(x); \ - }) - -+#ifndef __WRITE_ONCE - #define __WRITE_ONCE(x, val) \ - do { \ - *(volatile typeof(x) *)&(x) = (val); \ - } while (0) -+#endif - - #define WRITE_ONCE(x, val) \ - do { \ --- -2.53.0 - diff --git a/SPECS/linux/0102-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch b/SPECS/linux/0102-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch deleted file mode 100644 index 7922b4f42c..0000000000 --- a/SPECS/linux/0102-FROMLIST-PCI-Add-per-device-flag-to-disable-native-P.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 42c5c51b8056c7e2ef089845396c3b5d49a40c3e Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 1 Apr 2026 01:56:57 +0800 -Subject: [PATCH 102/269] FROMLIST: PCI: Add per-device flag to disable native - PCIe port services - -Add PCI_DEV_FLAGS_NO_PORT_SERVICES to allow quirks to prevent the PCIe -port service driver from probing specific devices. This provides a -per-device equivalent of the global pcie_ports=compat kernel parameter. - -Some platforms have PCIe root ports that break MSI delivery to downstream -devices when native port services (AER, PME, bwctrl, etc.) are active. -The existing pci_host_bridge native_* flags do not cover all services -(notably bwctrl), so a mechanism to skip port driver probing entirely -on a per-device basis is needed. - -Cc: stable@vger.kernel.org -Link: https://lore.kernel.org/r/20260331175658.1015829-2-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/pci/pcie/portdrv.c | 3 +++ - include/linux/pci.h | 2 ++ - 2 files changed, 5 insertions(+) - -diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c -index 2d6aa488fe7b..3386818d200d 100644 ---- a/drivers/pci/pcie/portdrv.c -+++ b/drivers/pci/pcie/portdrv.c -@@ -685,6 +685,9 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = { - static int pcie_portdrv_probe(struct pci_dev *dev, - const struct pci_device_id *id) - { -+ if (dev->dev_flags & PCI_DEV_FLAGS_NO_PORT_SERVICES) -+ return -ENODEV; -+ - int type = pci_pcie_type(dev); - int status; - -diff --git a/include/linux/pci.h b/include/linux/pci.h -index 57e9463e4347..89254d53ff1b 100644 ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -253,6 +253,8 @@ enum pci_dev_flags { - * integrated with the downstream devices and doesn't use real PCI. - */ - PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = (__force pci_dev_flags_t) (1 << 14), -+ /* Do not use native PCIe port services (equivalent to pcie_ports=compat) */ -+ PCI_DEV_FLAGS_NO_PORT_SERVICES = (__force pci_dev_flags_t) (1 << 15), - }; - - enum pci_irq_reroute_variant { --- -2.53.0 - diff --git a/SPECS/linux/0102-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch b/SPECS/linux/0102-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch new file mode 100644 index 0000000000..5f6b4ab250 --- /dev/null +++ b/SPECS/linux/0102-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch @@ -0,0 +1,60 @@ +From 6afc65d86d351f958dc63d13cf5c0131f9d0a18c Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 1 Apr 2026 01:56:58 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: Add quirk to disable PCIe port services + on Sophgo SG2042 + +SG2042's PCIe root ports [1f1c:2042] fail to deliver MSI interrupts to +downstream devices when native port services are enabled. Devices under +an affected root port receive zero interrupts despite successful vector +allocation, causing driver timeouts (e.g. amdgpu fence fallback timer +expired on all rings). + +Set PCI_DEV_FLAGS_NO_PORT_SERVICES on SG2042 root ports to prevent the +port service driver from probing, restoring correct MSI delivery. + +Fixes: 1c72774df028 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver") +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20260331175658.1015829-3-gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/pci/quirks.c | 12 ++++++++++++ + include/linux/pci_ids.h | 2 ++ + 2 files changed, 14 insertions(+) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 48946cca4be7..bbde482ff7cb 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -6380,3 +6380,15 @@ static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); + #endif ++ ++/* ++ * SG2042's PCIe root ports do not correctly deliver MSI interrupts to ++ * downstream devices when native PCIe port services are enabled. All ++ * services including bwctrl must be disabled, equivalent to pcie_ports=compat. ++ */ ++static void quirk_sg2042_no_port_services(struct pci_dev *dev) ++{ ++ pci_info(dev, "SG2042: disabling native PCIe port services\n"); ++ dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES; ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services); +diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h +index 406abf629be2..9663be526dd0 100644 +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2630,6 +2630,8 @@ + + #define PCI_VENDOR_ID_CXL 0x1e98 + ++#define PCI_VENDOR_ID_SOPHGO 0x1f1c ++ + #define PCI_VENDOR_ID_TEHUTI 0x1fc9 + #define PCI_DEVICE_ID_TEHUTI_3009 0x3009 + #define PCI_DEVICE_ID_TEHUTI_3010 0x3010 +-- +2.53.0 + diff --git a/SPECS/linux/0103-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch b/SPECS/linux/0103-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch deleted file mode 100644 index a6db8479cc..0000000000 --- a/SPECS/linux/0103-FROMLIST-PCI-Add-quirk-to-disable-PCIe-port-services.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 4380130b07aadfb32a3c593a6c54e095a41680cc Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 1 Apr 2026 01:56:58 +0800 -Subject: [PATCH 103/269] FROMLIST: PCI: Add quirk to disable PCIe port - services on Sophgo SG2042 - -SG2042's PCIe root ports [1f1c:2042] fail to deliver MSI interrupts to -downstream devices when native port services are enabled. Devices under -an affected root port receive zero interrupts despite successful vector -allocation, causing driver timeouts (e.g. amdgpu fence fallback timer -expired on all rings). - -Set PCI_DEV_FLAGS_NO_PORT_SERVICES on SG2042 root ports to prevent the -port service driver from probing, restoring correct MSI delivery. - -Fixes: 1c72774df028 ("PCI: sg2042: Add Sophgo SG2042 PCIe driver") -Cc: stable@vger.kernel.org -Link: https://lore.kernel.org/r/20260331175658.1015829-3-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/pci/quirks.c | 12 ++++++++++++ - include/linux/pci_ids.h | 2 ++ - 2 files changed, 14 insertions(+) - -diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index 48946cca4be7..bbde482ff7cb 100644 ---- a/drivers/pci/quirks.c -+++ b/drivers/pci/quirks.c -@@ -6380,3 +6380,15 @@ static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); - #endif -+ -+/* -+ * SG2042's PCIe root ports do not correctly deliver MSI interrupts to -+ * downstream devices when native PCIe port services are enabled. All -+ * services including bwctrl must be disabled, equivalent to pcie_ports=compat. -+ */ -+static void quirk_sg2042_no_port_services(struct pci_dev *dev) -+{ -+ pci_info(dev, "SG2042: disabling native PCIe port services\n"); -+ dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES; -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services); -diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h -index 406abf629be2..9663be526dd0 100644 ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -2630,6 +2630,8 @@ - - #define PCI_VENDOR_ID_CXL 0x1e98 - -+#define PCI_VENDOR_ID_SOPHGO 0x1f1c -+ - #define PCI_VENDOR_ID_TEHUTI 0x1fc9 - #define PCI_DEVICE_ID_TEHUTI_3009 0x3009 - #define PCI_DEVICE_ID_TEHUTI_3010 0x3010 --- -2.53.0 - diff --git a/SPECS/linux/0103-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch b/SPECS/linux/0103-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch new file mode 100644 index 0000000000..c5542d1485 --- /dev/null +++ b/SPECS/linux/0103-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch @@ -0,0 +1,83 @@ +From 7f371b937b7456a98377ea1782d3c5be557575ae Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= +Date: Thu, 18 Sep 2025 13:58:56 -0700 +Subject: [RUYI PATCH] FROMLIST: PCI: Release BAR0 of an integrated bridge to + allow GPU BAR resize +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Resizing BAR to a larger size has to release upstream bridge windows in +order make the bridge windows larger as well (and to potential relocate +them into a larger free block within iomem space). Some GPUs have an +integrated PCI switch that has BAR0. The resource allocation assigns +space for that BAR0 as it does for any resource. + +An extra resource on a bridge will pin its upstream bridge window in +place which prevents BAR resize for anything beneath that bridge. + +Nothing in the pcieport driver provided by PCI core, which typically is +the driver bound to these bridges, requires that BAR0. Because of that, +releasing the extra BAR does not seem to have notable downsides but +comes with a clear upside. + +Therefore, release BAR0 of such switches using a quirk and clear its +flags to prevent any new invocation of the resource assignment +algorithm from assigning the resource again. + +Due to other siblings within the PCI hierarchy of all the devices +integrated into the GPU, some other devices may still have to be +manually removed before the resize is free of any bridge window pins. +Such siblings can be released through sysfs to unpin windows while +leaving access to GPU's sysfs entries required for initiating the +resize operation, whereas removing the topmost bridge this quirk +targets would result in removing the GPU device as well so no manual +workaround for this problem exists. + +Reported-by: Lucas De Marchi +Link: https://lore.kernel.org/linux-pci/fl6tx5ztvttg7txmz2ps7oyd745wg3lwcp3h7esmvnyg26n44y@owo2ojiu2mov/ +Link: https://lore.kernel.org/intel-xe/20250721173057.867829-1-uwu@icenowy.me/ +Signed-off-by: Ilpo Järvinen +Cc: stable@vger.kernel.org # v6.12+ +Signed-off-by: Lucas De Marchi +Link: https://lore.kernel.org/intel-xe/fafda2a3-fc63-ce97-d22b-803f771a4d19@linux.intel.com +Link: https://lore.kernel.org/r/20250918-xe-pci-rebar-2-v1-1-6c094702a074@intel.com +Signed-off-by: Han Gao +--- + drivers/pci/quirks.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index bbde482ff7cb..9a50c2823c0c 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -6392,3 +6392,26 @@ static void quirk_sg2042_no_port_services(struct pci_dev *dev) + dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES; + } + DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services); ++ ++/* ++ * PCI switches integrated into Intel Arc GPUs have BAR0 that prevents ++ * resizing the BARs of the GPU device due to that bridge BAR0 pinning the ++ * bridge window it's under in place. Nothing in pcieport requires that ++ * BAR0. ++ * ++ * Release and disable BAR0 permanently by clearing its flags to prevent ++ * anything from assigning it again. ++ */ ++static void pci_release_bar0(struct pci_dev *pdev) ++{ ++ struct resource *res = pci_resource_n(pdev, 0); ++ ++ if (!res->parent) ++ return; ++ ++ pci_release_resource(pdev, 0); ++ res->flags = 0; ++} ++DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0x4fa0, pci_release_bar0); ++DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0x4fa1, pci_release_bar0); ++DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0xe2ff, pci_release_bar0); +-- +2.53.0 + diff --git a/SPECS/linux/0104-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch b/SPECS/linux/0104-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch new file mode 100644 index 0000000000..23bde87695 --- /dev/null +++ b/SPECS/linux/0104-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch @@ -0,0 +1,63 @@ +From 4811bb3593988f7d2664075e64d33362e979cc78 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Sat, 29 Jun 2024 13:22:46 +0800 +Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: save the device's DMA + coherency status in ttm_device + +Currently TTM utilizes cached memory regardless of whether the device +have full DMA coherency (can snoop CPU cache). + +Save the device's DMA coherency status in struct ttm_device, to allow +further support of devices w/o snooping capability (the capability +missing on at least one part of the transmission between the CPU and the +device). + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20240629052247.2653363-2-uwu@icenowy.me +[ Han Gao: add conditional compilation for dma_coherent ] +Signed-off-by: Han Gao +--- + drivers/gpu/drm/ttm/ttm_device.c | 6 ++++++ + include/drm/ttm/ttm_device.h | 9 +++++++++ + 2 files changed, 15 insertions(+) + +diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c +index d3bfb9a696a7..7fad8dcd1ecf 100644 +--- a/drivers/gpu/drm/ttm/ttm_device.c ++++ b/drivers/gpu/drm/ttm/ttm_device.c +@@ -244,6 +244,12 @@ int ttm_device_init(struct ttm_device *bdev, const struct ttm_device_funcs *func + list_add_tail(&bdev->device_list, &glob->device_list); + mutex_unlock(&ttm_global_mutex); + ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ bdev->dma_coherent = dev->dma_coherent; ++#endif ++ + return 0; + } + EXPORT_SYMBOL(ttm_device_init); +diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h +index 5618aef462f2..5b7c6a7a0e3b 100644 +--- a/include/drm/ttm/ttm_device.h ++++ b/include/drm/ttm/ttm_device.h +@@ -231,6 +231,15 @@ struct ttm_device { + */ + const struct ttm_device_funcs *funcs; + ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ /** ++ * @dma_coherent: if the device backed is dma-coherent. ++ */ ++ bool dma_coherent; ++#endif ++ + /** + * @sysman: Resource manager for the system domain. + * Access via ttm_manager_type. +-- +2.53.0 + diff --git a/SPECS/linux/0104-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch b/SPECS/linux/0104-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch deleted file mode 100644 index c0dc9f9334..0000000000 --- a/SPECS/linux/0104-FROMLIST-PCI-Release-BAR0-of-an-integrated-bridge-to.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 5c68926836e8bffeb8797d0dbbae85e57e5361b3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= -Date: Thu, 18 Sep 2025 13:58:56 -0700 -Subject: [PATCH 104/269] FROMLIST: PCI: Release BAR0 of an integrated bridge - to allow GPU BAR resize -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Resizing BAR to a larger size has to release upstream bridge windows in -order make the bridge windows larger as well (and to potential relocate -them into a larger free block within iomem space). Some GPUs have an -integrated PCI switch that has BAR0. The resource allocation assigns -space for that BAR0 as it does for any resource. - -An extra resource on a bridge will pin its upstream bridge window in -place which prevents BAR resize for anything beneath that bridge. - -Nothing in the pcieport driver provided by PCI core, which typically is -the driver bound to these bridges, requires that BAR0. Because of that, -releasing the extra BAR does not seem to have notable downsides but -comes with a clear upside. - -Therefore, release BAR0 of such switches using a quirk and clear its -flags to prevent any new invocation of the resource assignment -algorithm from assigning the resource again. - -Due to other siblings within the PCI hierarchy of all the devices -integrated into the GPU, some other devices may still have to be -manually removed before the resize is free of any bridge window pins. -Such siblings can be released through sysfs to unpin windows while -leaving access to GPU's sysfs entries required for initiating the -resize operation, whereas removing the topmost bridge this quirk -targets would result in removing the GPU device as well so no manual -workaround for this problem exists. - -Reported-by: Lucas De Marchi -Link: https://lore.kernel.org/linux-pci/fl6tx5ztvttg7txmz2ps7oyd745wg3lwcp3h7esmvnyg26n44y@owo2ojiu2mov/ -Link: https://lore.kernel.org/intel-xe/20250721173057.867829-1-uwu@icenowy.me/ -Signed-off-by: Ilpo Järvinen -Cc: stable@vger.kernel.org # v6.12+ -Signed-off-by: Lucas De Marchi -Link: https://lore.kernel.org/intel-xe/fafda2a3-fc63-ce97-d22b-803f771a4d19@linux.intel.com -Link: https://lore.kernel.org/r/20250918-xe-pci-rebar-2-v1-1-6c094702a074@intel.com -Signed-off-by: Han Gao ---- - drivers/pci/quirks.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index bbde482ff7cb..9a50c2823c0c 100644 ---- a/drivers/pci/quirks.c -+++ b/drivers/pci/quirks.c -@@ -6392,3 +6392,26 @@ static void quirk_sg2042_no_port_services(struct pci_dev *dev) - dev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES; - } - DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services); -+ -+/* -+ * PCI switches integrated into Intel Arc GPUs have BAR0 that prevents -+ * resizing the BARs of the GPU device due to that bridge BAR0 pinning the -+ * bridge window it's under in place. Nothing in pcieport requires that -+ * BAR0. -+ * -+ * Release and disable BAR0 permanently by clearing its flags to prevent -+ * anything from assigning it again. -+ */ -+static void pci_release_bar0(struct pci_dev *pdev) -+{ -+ struct resource *res = pci_resource_n(pdev, 0); -+ -+ if (!res->parent) -+ return; -+ -+ pci_release_resource(pdev, 0); -+ res->flags = 0; -+} -+DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0x4fa0, pci_release_bar0); -+DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0x4fa1, pci_release_bar0); -+DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, 0xe2ff, pci_release_bar0); --- -2.53.0 - diff --git a/SPECS/linux/0105-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch b/SPECS/linux/0105-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch new file mode 100644 index 0000000000..18a2d98d9c --- /dev/null +++ b/SPECS/linux/0105-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch @@ -0,0 +1,125 @@ +From b56a98bdc8376d49764e9ad76282c11b50865470 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Sat, 29 Jun 2024 13:22:47 +0800 +Subject: [RUYI PATCH] BACKPORT: FROMLIST: drm/ttm: downgrade cached to + write_combined when snooping not available + +As we can now acquire the presence of the full DMA coherency (snooping +capability) from ttm_device, we can now map the CPU side memory as +write-combined when cached is requested and snooping is not avilable. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20240629052247.2653363-3-uwu@icenowy.me +[ Han Gao: add conditional compilation for dma coherent operations ] +[ Icenowy: omit single page ttm_cached optimization when non-coherent and handle linear io iter ] +Signed-off-by: Han Gao +--- + drivers/gpu/drm/ttm/ttm_bo_util.c | 13 +++++++++++++ + drivers/gpu/drm/ttm/ttm_resource.c | 13 +++++++++++-- + drivers/gpu/drm/ttm/ttm_tt.c | 8 ++++++++ + include/drm/ttm/ttm_caching.h | 3 ++- + 4 files changed, 34 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c +index 3e3c201a0222..6f33c77d4715 100644 +--- a/drivers/gpu/drm/ttm/ttm_bo_util.c ++++ b/drivers/gpu/drm/ttm/ttm_bo_util.c +@@ -307,6 +307,14 @@ pgprot_t ttm_io_prot(struct ttm_buffer_object *bo, struct ttm_resource *res, + caching = res->bus.caching; + } + ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ /* Downgrade cached mapping for non-snooping devices */ ++ if (!bo->bdev->dma_coherent && caching == ttm_cached) ++ caching = ttm_write_combined; ++#endif ++ + return ttm_prot_from_caching(caching, tmp); + } + EXPORT_SYMBOL(ttm_io_prot); +@@ -357,6 +365,11 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, + return ret; + + if (num_pages == 1 && ttm->caching == ttm_cached && ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ bo->bdev->dma_coherent && ++#endif + !(man->use_tt && (ttm->page_flags & TTM_TT_FLAG_DECRYPTED))) { + /* + * We're mapping a single page, and the desired +diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c +index bfd9c68fcd9c..3e3489453654 100644 +--- a/drivers/gpu/drm/ttm/ttm_resource.c ++++ b/drivers/gpu/drm/ttm/ttm_resource.c +@@ -848,8 +848,17 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, + struct ttm_device *bdev, + struct ttm_resource *mem) + { ++ enum ttm_caching caching = mem->bus.caching; + int ret; + ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ /* Downgrade cached mapping for non-snooping devices */ ++ if (!bdev->dma_coherent && caching == ttm_cached) ++ caching = ttm_write_combined; ++#endif ++ + ret = ttm_mem_io_reserve(bdev, mem); + if (ret) + goto out_err; +@@ -864,11 +873,11 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, + } else { + iter_io->needs_unmap = true; + memset(&iter_io->dmap, 0, sizeof(iter_io->dmap)); +- if (mem->bus.caching == ttm_write_combined) ++ if (caching == ttm_write_combined) + iosys_map_set_vaddr_iomem(&iter_io->dmap, + ioremap_wc(mem->bus.offset, + mem->size)); +- else if (mem->bus.caching == ttm_cached) ++ else if (caching == ttm_cached) + iosys_map_set_vaddr(&iter_io->dmap, + memremap(mem->bus.offset, mem->size, + MEMREMAP_WB | +diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c +index b645a1818184..47244d1c1b7a 100644 +--- a/drivers/gpu/drm/ttm/ttm_tt.c ++++ b/drivers/gpu/drm/ttm/ttm_tt.c +@@ -156,6 +156,14 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm, + enum ttm_caching caching, + unsigned long extra_pages) + { ++#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ ++ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) ++ /* Downgrade cached mapping for non-snooping devices */ ++ if (!bo->bdev->dma_coherent && caching == ttm_cached) ++ caching = ttm_write_combined; ++#endif ++ + ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) + extra_pages; + ttm->page_flags = page_flags; + ttm->dma_address = NULL; +diff --git a/include/drm/ttm/ttm_caching.h b/include/drm/ttm/ttm_caching.h +index a18f43e93aba..f92d7911f50e 100644 +--- a/include/drm/ttm/ttm_caching.h ++++ b/include/drm/ttm/ttm_caching.h +@@ -47,7 +47,8 @@ enum ttm_caching { + + /** + * @ttm_cached: Fully cached like normal system memory, requires that +- * devices snoop the CPU cache on accesses. ++ * devices snoop the CPU cache on accesses. Downgraded to ++ * ttm_write_combined when the snooping capaiblity is missing. + */ + ttm_cached + }; +-- +2.53.0 + diff --git a/SPECS/linux/0105-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch b/SPECS/linux/0105-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch deleted file mode 100644 index 87009b73a3..0000000000 --- a/SPECS/linux/0105-BACKPORT-FROMLIST-drm-ttm-save-the-device-s-DMA-cohe.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 1b29f8468abaa1b00f904c1f5bef01d1363004e2 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Sat, 29 Jun 2024 13:22:46 +0800 -Subject: [PATCH 105/269] BACKPORT: FROMLIST: drm/ttm: save the device's DMA - coherency status in ttm_device - -Currently TTM utilizes cached memory regardless of whether the device -have full DMA coherency (can snoop CPU cache). - -Save the device's DMA coherency status in struct ttm_device, to allow -further support of devices w/o snooping capability (the capability -missing on at least one part of the transmission between the CPU and the -device). - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20240629052247.2653363-2-uwu@icenowy.me -[ Han Gao: add conditional compilation for dma_coherent ] -Signed-off-by: Han Gao ---- - drivers/gpu/drm/ttm/ttm_device.c | 6 ++++++ - include/drm/ttm/ttm_device.h | 9 +++++++++ - 2 files changed, 15 insertions(+) - -diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c -index d3bfb9a696a7..7fad8dcd1ecf 100644 ---- a/drivers/gpu/drm/ttm/ttm_device.c -+++ b/drivers/gpu/drm/ttm/ttm_device.c -@@ -244,6 +244,12 @@ int ttm_device_init(struct ttm_device *bdev, const struct ttm_device_funcs *func - list_add_tail(&bdev->device_list, &glob->device_list); - mutex_unlock(&ttm_global_mutex); - -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ bdev->dma_coherent = dev->dma_coherent; -+#endif -+ - return 0; - } - EXPORT_SYMBOL(ttm_device_init); -diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h -index 5618aef462f2..5b7c6a7a0e3b 100644 ---- a/include/drm/ttm/ttm_device.h -+++ b/include/drm/ttm/ttm_device.h -@@ -231,6 +231,15 @@ struct ttm_device { - */ - const struct ttm_device_funcs *funcs; - -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ /** -+ * @dma_coherent: if the device backed is dma-coherent. -+ */ -+ bool dma_coherent; -+#endif -+ - /** - * @sysman: Resource manager for the system domain. - * Access via ttm_manager_type. --- -2.53.0 - diff --git a/SPECS/linux/0106-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch b/SPECS/linux/0106-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch deleted file mode 100644 index fa6bd7d82e..0000000000 --- a/SPECS/linux/0106-BACKPORT-FROMLIST-drm-ttm-downgrade-cached-to-write_.patch +++ /dev/null @@ -1,125 +0,0 @@ -From 039ca5547669325bda4c70f6de5a941b49e79b34 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Sat, 29 Jun 2024 13:22:47 +0800 -Subject: [PATCH 106/269] BACKPORT: FROMLIST: drm/ttm: downgrade cached to - write_combined when snooping not available - -As we can now acquire the presence of the full DMA coherency (snooping -capability) from ttm_device, we can now map the CPU side memory as -write-combined when cached is requested and snooping is not avilable. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20240629052247.2653363-3-uwu@icenowy.me -[ Han Gao: add conditional compilation for dma coherent operations ] -[ Icenowy: omit single page ttm_cached optimization when non-coherent and handle linear io iter ] -Signed-off-by: Han Gao ---- - drivers/gpu/drm/ttm/ttm_bo_util.c | 13 +++++++++++++ - drivers/gpu/drm/ttm/ttm_resource.c | 13 +++++++++++-- - drivers/gpu/drm/ttm/ttm_tt.c | 8 ++++++++ - include/drm/ttm/ttm_caching.h | 3 ++- - 4 files changed, 34 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c -index 3e3c201a0222..6f33c77d4715 100644 ---- a/drivers/gpu/drm/ttm/ttm_bo_util.c -+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c -@@ -307,6 +307,14 @@ pgprot_t ttm_io_prot(struct ttm_buffer_object *bo, struct ttm_resource *res, - caching = res->bus.caching; - } - -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ /* Downgrade cached mapping for non-snooping devices */ -+ if (!bo->bdev->dma_coherent && caching == ttm_cached) -+ caching = ttm_write_combined; -+#endif -+ - return ttm_prot_from_caching(caching, tmp); - } - EXPORT_SYMBOL(ttm_io_prot); -@@ -357,6 +365,11 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, - return ret; - - if (num_pages == 1 && ttm->caching == ttm_cached && -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ bo->bdev->dma_coherent && -+#endif - !(man->use_tt && (ttm->page_flags & TTM_TT_FLAG_DECRYPTED))) { - /* - * We're mapping a single page, and the desired -diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c -index bfd9c68fcd9c..3e3489453654 100644 ---- a/drivers/gpu/drm/ttm/ttm_resource.c -+++ b/drivers/gpu/drm/ttm/ttm_resource.c -@@ -848,8 +848,17 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, - struct ttm_device *bdev, - struct ttm_resource *mem) - { -+ enum ttm_caching caching = mem->bus.caching; - int ret; - -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ /* Downgrade cached mapping for non-snooping devices */ -+ if (!bdev->dma_coherent && caching == ttm_cached) -+ caching = ttm_write_combined; -+#endif -+ - ret = ttm_mem_io_reserve(bdev, mem); - if (ret) - goto out_err; -@@ -864,11 +873,11 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, - } else { - iter_io->needs_unmap = true; - memset(&iter_io->dmap, 0, sizeof(iter_io->dmap)); -- if (mem->bus.caching == ttm_write_combined) -+ if (caching == ttm_write_combined) - iosys_map_set_vaddr_iomem(&iter_io->dmap, - ioremap_wc(mem->bus.offset, - mem->size)); -- else if (mem->bus.caching == ttm_cached) -+ else if (caching == ttm_cached) - iosys_map_set_vaddr(&iter_io->dmap, - memremap(mem->bus.offset, mem->size, - MEMREMAP_WB | -diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c -index b645a1818184..47244d1c1b7a 100644 ---- a/drivers/gpu/drm/ttm/ttm_tt.c -+++ b/drivers/gpu/drm/ttm/ttm_tt.c -@@ -156,6 +156,14 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm, - enum ttm_caching caching, - unsigned long extra_pages) - { -+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ -+ defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) -+ /* Downgrade cached mapping for non-snooping devices */ -+ if (!bo->bdev->dma_coherent && caching == ttm_cached) -+ caching = ttm_write_combined; -+#endif -+ - ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) + extra_pages; - ttm->page_flags = page_flags; - ttm->dma_address = NULL; -diff --git a/include/drm/ttm/ttm_caching.h b/include/drm/ttm/ttm_caching.h -index a18f43e93aba..f92d7911f50e 100644 ---- a/include/drm/ttm/ttm_caching.h -+++ b/include/drm/ttm/ttm_caching.h -@@ -47,7 +47,8 @@ enum ttm_caching { - - /** - * @ttm_cached: Fully cached like normal system memory, requires that -- * devices snoop the CPU cache on accesses. -+ * devices snoop the CPU cache on accesses. Downgraded to -+ * ttm_write_combined when the snooping capaiblity is missing. - */ - ttm_cached - }; --- -2.53.0 - diff --git a/SPECS/linux/0106-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch b/SPECS/linux/0106-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch new file mode 100644 index 0000000000..e7d5b702db --- /dev/null +++ b/SPECS/linux/0106-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch @@ -0,0 +1,98 @@ +From e943f5af6d04d50b23df629eaefa1671e406a4bd Mon Sep 17 00:00:00 2001 +From: Yao Zi +Date: Thu, 20 Nov 2025 13:14:16 +0000 +Subject: [RUYI PATCH] FROMLIST: NFU: riscv: dts: thead: Add CPU clock and OPP + table for TH1520 + +Add operating point table for CPU cores, and wire up clocks for CPU +nodes. + +This patch isn't intended for upstreaming but only for testing purpose, +since the PMIC driver for scaling CPU voltage isn't ready yet. Only +operating points whose voltage is satisified by Lichee Module 4A's PMIC +default, i.e. <= 1.5GHz, are enabled. + +Signed-off-by: Yao Zi +Link: https://lore.kernel.org/r/20251120131416.26236-8-ziyao@disroot.org +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 35 +++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index 5e91dc1d2b9b..2910249e1f0c 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -38,6 +38,8 @@ c910_0: cpu@0 { + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&clk CLK_C910>; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -65,6 +67,8 @@ c910_1: cpu@1 { + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&clk CLK_C910>; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -92,6 +96,8 @@ c910_2: cpu@2 { + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&clk CLK_C910>; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -119,6 +125,8 @@ c910_3: cpu@3 { + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&clk CLK_C910>; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -137,6 +145,33 @@ l2_cache: l2-cache { + }; + }; + ++ cpu_opp: opp-table-cpu { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <600000>; ++ }; ++ ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <700000>; ++ }; ++ ++ opp-1500000000 { ++ opp-hz = /bits/ 64 <1500000000>; ++ opp-microvolt = <800000>; ++ }; ++ ++/* ++ opp-1848000000 { ++ opp-hz = /bits/ 64 <1848000000>; ++ opp-microvolt = <1000000>; ++ }; ++ */ ++ }; ++ + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmcounters = +-- +2.53.0 + diff --git a/SPECS/linux/0107-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch b/SPECS/linux/0107-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch deleted file mode 100644 index b375df8b9b..0000000000 --- a/SPECS/linux/0107-FROMLIST-NFU-riscv-dts-thead-Add-CPU-clock-and-OPP-t.patch +++ /dev/null @@ -1,98 +0,0 @@ -From f7b9e23e1bb52ebf95c370b784964d3dc9d8aff0 Mon Sep 17 00:00:00 2001 -From: Yao Zi -Date: Thu, 20 Nov 2025 13:14:16 +0000 -Subject: [PATCH 107/269] FROMLIST: NFU: riscv: dts: thead: Add CPU clock and - OPP table for TH1520 - -Add operating point table for CPU cores, and wire up clocks for CPU -nodes. - -This patch isn't intended for upstreaming but only for testing purpose, -since the PMIC driver for scaling CPU voltage isn't ready yet. Only -operating points whose voltage is satisified by Lichee Module 4A's PMIC -default, i.e. <= 1.5GHz, are enabled. - -Signed-off-by: Yao Zi -Link: https://lore.kernel.org/r/20251120131416.26236-8-ziyao@disroot.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 35 +++++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index 5e91dc1d2b9b..2910249e1f0c 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -38,6 +38,8 @@ c910_0: cpu@0 { - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; -+ operating-points-v2 = <&cpu_opp>; -+ clocks = <&clk CLK_C910>; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; -@@ -65,6 +67,8 @@ c910_1: cpu@1 { - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; -+ operating-points-v2 = <&cpu_opp>; -+ clocks = <&clk CLK_C910>; - - cpu1_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; -@@ -92,6 +96,8 @@ c910_2: cpu@2 { - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; -+ operating-points-v2 = <&cpu_opp>; -+ clocks = <&clk CLK_C910>; - - cpu2_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; -@@ -119,6 +125,8 @@ c910_3: cpu@3 { - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; -+ operating-points-v2 = <&cpu_opp>; -+ clocks = <&clk CLK_C910>; - - cpu3_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; -@@ -137,6 +145,33 @@ l2_cache: l2-cache { - }; - }; - -+ cpu_opp: opp-table-cpu { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <600000>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <700000>; -+ }; -+ -+ opp-1500000000 { -+ opp-hz = /bits/ 64 <1500000000>; -+ opp-microvolt = <800000>; -+ }; -+ -+/* -+ opp-1848000000 { -+ opp-hz = /bits/ 64 <1848000000>; -+ opp-microvolt = <1000000>; -+ }; -+ */ -+ }; -+ - pmu { - compatible = "riscv,pmu"; - riscv,event-to-mhpmcounters = --- -2.53.0 - diff --git a/SPECS/linux/0107-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch b/SPECS/linux/0107-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch new file mode 100644 index 0000000000..6fbab11aa9 --- /dev/null +++ b/SPECS/linux/0107-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch @@ -0,0 +1,83 @@ +From 6acf0575cf5ef17a313cb81bc0c4e4e5743dac56 Mon Sep 17 00:00:00 2001 +From: Asuna Yang +Date: Tue, 30 Dec 2025 17:47:54 +0100 +Subject: [RUYI PATCH] FROMLIST: rust: export BINDGEN_TARGET from a separate + Makefile + +A subsequent commit will add a new function `bindgen-option` to +`scripts/Kconfig.include`. The bindgen backend requires the `--target` +option for cross compiling, but variable `BINDGEN_TARGET` in +`rust/Makefile` cannot be exported to `scripts/Kconfig.include`. + +Therefore, move this variable to a separate new `Makefile.rust` file and +include it from `scripts/Makefile` to make the exported variable +available for use in Kconfig. Place the include in the `need-compiler` +branch to avoid including it in irrelevant make targets. + +Since the new file name is `Makefile.rust`, it matches an existing +MAINTAINERS rule `scripts/*rust*`, so no modification to the MAINTAINERS +file is needed. + +Signed-off-by: Asuna Yang +Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-1-2ac86ba728c8@isrc.iscas.ac.cn +Signed-off-by: Han Gao +--- + Makefile | 3 ++- + rust/Makefile | 8 -------- + scripts/Makefile.rust | 9 +++++++++ + 3 files changed, 11 insertions(+), 9 deletions(-) + create mode 100644 scripts/Makefile.rust + +diff --git a/Makefile b/Makefile +index d2a1c3a1ab44..ee78bc154ee9 100644 +--- a/Makefile ++++ b/Makefile +@@ -728,9 +728,10 @@ ifneq ($(findstring clang,$(CC_VERSION_TEXT)),) + include $(srctree)/scripts/Makefile.clang + endif + ++ifdef need-compiler ++include $(srctree)/scripts/Makefile.rust + # Include this also for config targets because some architectures need + # cc-cross-prefix to determine CROSS_COMPILE. +-ifdef need-compiler + include $(srctree)/scripts/Makefile.compiler + endif + +diff --git a/rust/Makefile b/rust/Makefile +index 9801af2e1e02..b8813ec123e8 100644 +--- a/rust/Makefile ++++ b/rust/Makefile +@@ -404,14 +404,6 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ + -fdiagnostics-show-context -fdiagnostics-show-context=% \ + --param=% --param asan-% -fno-isolate-erroneous-paths-dereference + +-# Derived from `scripts/Makefile.clang`. +-BINDGEN_TARGET_x86 := x86_64-linux-gnu +-BINDGEN_TARGET_arm64 := aarch64-linux-gnu +-BINDGEN_TARGET_arm := arm-linux-gnueabi +-BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf +-BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) +-BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) +- + # All warnings are inhibited since GCC builds are very experimental, + # many GCC warnings are not supported by Clang, they may only appear in + # some configurations, with new GCC versions, etc. +diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust +new file mode 100644 +index 000000000000..5c12b4b8c8b6 +--- /dev/null ++++ b/scripts/Makefile.rust +@@ -0,0 +1,9 @@ ++# Derived from `scripts/Makefile.clang`. ++BINDGEN_TARGET_x86 := x86_64-linux-gnu ++BINDGEN_TARGET_arm64 := aarch64-linux-gnu ++BINDGEN_TARGET_arm := arm-linux-gnueabi ++BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf ++BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) ++BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) ++ ++export BINDGEN_TARGET +-- +2.53.0 + diff --git a/SPECS/linux/0108-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch b/SPECS/linux/0108-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch deleted file mode 100644 index 89ed12acba..0000000000 --- a/SPECS/linux/0108-FROMLIST-rust-export-BINDGEN_TARGET-from-a-separate-.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 50895f69b2de1cb8e4d7882744aeb703c68de8c0 Mon Sep 17 00:00:00 2001 -From: Asuna Yang -Date: Tue, 30 Dec 2025 17:47:54 +0100 -Subject: [PATCH 108/269] FROMLIST: rust: export BINDGEN_TARGET from a separate - Makefile - -A subsequent commit will add a new function `bindgen-option` to -`scripts/Kconfig.include`. The bindgen backend requires the `--target` -option for cross compiling, but variable `BINDGEN_TARGET` in -`rust/Makefile` cannot be exported to `scripts/Kconfig.include`. - -Therefore, move this variable to a separate new `Makefile.rust` file and -include it from `scripts/Makefile` to make the exported variable -available for use in Kconfig. Place the include in the `need-compiler` -branch to avoid including it in irrelevant make targets. - -Since the new file name is `Makefile.rust`, it matches an existing -MAINTAINERS rule `scripts/*rust*`, so no modification to the MAINTAINERS -file is needed. - -Signed-off-by: Asuna Yang -Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-1-2ac86ba728c8@isrc.iscas.ac.cn -Signed-off-by: Han Gao ---- - Makefile | 3 ++- - rust/Makefile | 8 -------- - scripts/Makefile.rust | 9 +++++++++ - 3 files changed, 11 insertions(+), 9 deletions(-) - create mode 100644 scripts/Makefile.rust - -diff --git a/Makefile b/Makefile -index a95f0b3d26bf..12a202e10fe1 100644 ---- a/Makefile -+++ b/Makefile -@@ -728,9 +728,10 @@ ifneq ($(findstring clang,$(CC_VERSION_TEXT)),) - include $(srctree)/scripts/Makefile.clang - endif - -+ifdef need-compiler -+include $(srctree)/scripts/Makefile.rust - # Include this also for config targets because some architectures need - # cc-cross-prefix to determine CROSS_COMPILE. --ifdef need-compiler - include $(srctree)/scripts/Makefile.compiler - endif - -diff --git a/rust/Makefile b/rust/Makefile -index 9801af2e1e02..b8813ec123e8 100644 ---- a/rust/Makefile -+++ b/rust/Makefile -@@ -404,14 +404,6 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ - -fdiagnostics-show-context -fdiagnostics-show-context=% \ - --param=% --param asan-% -fno-isolate-erroneous-paths-dereference - --# Derived from `scripts/Makefile.clang`. --BINDGEN_TARGET_x86 := x86_64-linux-gnu --BINDGEN_TARGET_arm64 := aarch64-linux-gnu --BINDGEN_TARGET_arm := arm-linux-gnueabi --BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf --BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) --BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) -- - # All warnings are inhibited since GCC builds are very experimental, - # many GCC warnings are not supported by Clang, they may only appear in - # some configurations, with new GCC versions, etc. -diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust -new file mode 100644 -index 000000000000..5c12b4b8c8b6 ---- /dev/null -+++ b/scripts/Makefile.rust -@@ -0,0 +1,9 @@ -+# Derived from `scripts/Makefile.clang`. -+BINDGEN_TARGET_x86 := x86_64-linux-gnu -+BINDGEN_TARGET_arm64 := aarch64-linux-gnu -+BINDGEN_TARGET_arm := arm-linux-gnueabi -+BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf -+BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) -+BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) -+ -+export BINDGEN_TARGET --- -2.53.0 - diff --git a/SPECS/linux/0108-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch b/SPECS/linux/0108-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch new file mode 100644 index 0000000000..56ec421586 --- /dev/null +++ b/SPECS/linux/0108-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch @@ -0,0 +1,61 @@ +From 99e56bc7e6cb217e32c1cd9acf36b38ddf739aaa Mon Sep 17 00:00:00 2001 +From: Asuna Yang +Date: Tue, 30 Dec 2025 17:47:55 +0100 +Subject: [RUYI PATCH] FROMLIST: rust: generate a fatal error if BINDGEN_TARGET + is undefined + +Generate a friendly fatal error if the target triplet is undefined for +bindgen, rather than having the compiler generate obscure error messages +during the build stage. + +`BINDGEN_TARGET` is actually defined in `scripts/Makefile.rust`, but the +file is included regardless of whether Rust is enabled, so perform this +check in `rust/Makefile` to avoid breaking targets that do not yet +support Rust builds. + +This piece of code is copied from `scripts/Makefile.clang`. + +Before this commit, error messages might look like: + +error: unknown argument: '-mno-riscv-attribute' +error: unsupported argument 'medany' to option '-mcmodel=' for target +'unknown' +error: unsupported option '-march=' for target '' +error: unsupported option '-mno-save-restore' for target '' +error: unknown target triple 'unknown' +panicked at bindgen/ir/context.rs:562:15: +libclang error; possible causes include: +- Invalid flag syntax +- Unrecognized flags +- Invalid flag arguments +- File I/O errors +- Host vs. target architecture mismatch + +Acked-by: Miguel Ojeda +Signed-off-by: Asuna Yang +Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-2-2ac86ba728c8@isrc.iscas.ac.cn +Signed-off-by: Han Gao +--- + rust/Makefile | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/rust/Makefile b/rust/Makefile +index b8813ec123e8..314329e6bc46 100644 +--- a/rust/Makefile ++++ b/rust/Makefile +@@ -404,6 +404,12 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ + -fdiagnostics-show-context -fdiagnostics-show-context=% \ + --param=% --param asan-% -fno-isolate-erroneous-paths-dereference + ++# Because scripts/Makefile.rust is included regardless of whether Rust is enabled, ++# we perform this check here to avoid breaking targets that do not yet support Rust builds. ++ifeq ($(BINDGEN_TARGET),) ++$(error add '--target=' option to scripts/Makefile.rust) ++endif ++ + # All warnings are inhibited since GCC builds are very experimental, + # many GCC warnings are not supported by Clang, they may only appear in + # some configurations, with new GCC versions, etc. +-- +2.53.0 + diff --git a/SPECS/linux/0109-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch b/SPECS/linux/0109-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch new file mode 100644 index 0000000000..4d90fa621b --- /dev/null +++ b/SPECS/linux/0109-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch @@ -0,0 +1,35 @@ +From 695941c48f54eaf2d9571a60e931545aa0646d38 Mon Sep 17 00:00:00 2001 +From: Asuna Yang +Date: Tue, 30 Dec 2025 17:47:56 +0100 +Subject: [RUYI PATCH] FROMLIST: rust: add a Kconfig function to test for + support of bindgen options + +Add a new `bindgen-backend-option` Kconfig function to test whether the +bindgen backend supports a given flag. + +A subsequent commit will use this function to test for RISC-V extension +flags. + +Signed-off-by: Asuna Yang +Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-3-2ac86ba728c8@isrc.iscas.ac.cn +Signed-off-by: Han Gao +--- + scripts/Kconfig.include | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include +index fc10671c297c..ea5be3c622a8 100644 +--- a/scripts/Kconfig.include ++++ b/scripts/Kconfig.include +@@ -76,3 +76,8 @@ rustc-llvm-version := $(shell,$(srctree)/scripts/rustc-llvm-version.sh $(RUSTC)) + # If you are testing for unstable features, consider testing RUSTC_VERSION + # instead, as features may have different completeness while available. + rustc-option = $(success,trap "rm -rf .tmp_$$" EXIT; mkdir .tmp_$$; $(RUSTC) $(1) --crate-type=rlib /dev/null --out-dir=.tmp_$$ -o .tmp_$$/tmp.rlib) ++ ++# $(bindgen-backend-option,) ++# Return y if bindgen backend supports , n otherwise ++# For now, the backend refers only to libclang, so more specifically, this function tests whether the given flag is recognized by the libclang used by bindgen. ++bindgen-backend-option = $(success,$(BINDGEN) /dev/null -- -x c --target=$(BINDGEN_TARGET) $(1)) +-- +2.53.0 + diff --git a/SPECS/linux/0109-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch b/SPECS/linux/0109-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch deleted file mode 100644 index ee02f4253f..0000000000 --- a/SPECS/linux/0109-FROMLIST-rust-generate-a-fatal-error-if-BINDGEN_TARG.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 43aeaabfcdc3ef135294f3ff9ad674214c66ea15 Mon Sep 17 00:00:00 2001 -From: Asuna Yang -Date: Tue, 30 Dec 2025 17:47:55 +0100 -Subject: [PATCH 109/269] FROMLIST: rust: generate a fatal error if - BINDGEN_TARGET is undefined - -Generate a friendly fatal error if the target triplet is undefined for -bindgen, rather than having the compiler generate obscure error messages -during the build stage. - -`BINDGEN_TARGET` is actually defined in `scripts/Makefile.rust`, but the -file is included regardless of whether Rust is enabled, so perform this -check in `rust/Makefile` to avoid breaking targets that do not yet -support Rust builds. - -This piece of code is copied from `scripts/Makefile.clang`. - -Before this commit, error messages might look like: - -error: unknown argument: '-mno-riscv-attribute' -error: unsupported argument 'medany' to option '-mcmodel=' for target -'unknown' -error: unsupported option '-march=' for target '' -error: unsupported option '-mno-save-restore' for target '' -error: unknown target triple 'unknown' -panicked at bindgen/ir/context.rs:562:15: -libclang error; possible causes include: -- Invalid flag syntax -- Unrecognized flags -- Invalid flag arguments -- File I/O errors -- Host vs. target architecture mismatch - -Acked-by: Miguel Ojeda -Signed-off-by: Asuna Yang -Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-2-2ac86ba728c8@isrc.iscas.ac.cn -Signed-off-by: Han Gao ---- - rust/Makefile | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/rust/Makefile b/rust/Makefile -index b8813ec123e8..314329e6bc46 100644 ---- a/rust/Makefile -+++ b/rust/Makefile -@@ -404,6 +404,12 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ - -fdiagnostics-show-context -fdiagnostics-show-context=% \ - --param=% --param asan-% -fno-isolate-erroneous-paths-dereference - -+# Because scripts/Makefile.rust is included regardless of whether Rust is enabled, -+# we perform this check here to avoid breaking targets that do not yet support Rust builds. -+ifeq ($(BINDGEN_TARGET),) -+$(error add '--target=' option to scripts/Makefile.rust) -+endif -+ - # All warnings are inhibited since GCC builds are very experimental, - # many GCC warnings are not supported by Clang, they may only appear in - # some configurations, with new GCC versions, etc. --- -2.53.0 - diff --git a/SPECS/linux/0110-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch b/SPECS/linux/0110-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch new file mode 100644 index 0000000000..8a84f0cb1a --- /dev/null +++ b/SPECS/linux/0110-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch @@ -0,0 +1,183 @@ +From bb5b174c339f21b29b70aa4066deff3d12c67d57 Mon Sep 17 00:00:00 2001 +From: Asuna Yang +Date: Tue, 30 Dec 2025 17:47:57 +0100 +Subject: [RUYI PATCH] FROMLIST: RISC-V: handle extension configs for bindgen, + re-enable gcc + rust builds + +Commit 33549fcf37ec ("RISC-V: disallow gcc + rust builds") disabled GCC ++ Rust builds for RISC-V due to differences in extension handling +compared to LLVM. This commit enables GCC + Rust builds again. + +Add `bindgen-option` conditions for the availability of libclang to the +RISC-V extension Kconfig symbols that depend on the `cc-option` +function. + +For Zicsr/Zifencei special handling, since LLVM/Clang always enables +these two extensions, either don't pass them to `-march`, or pass them +explicitly and Rust bindgen libclang must recognize them. + +Clang does not support `-mno-riscv-attribute` flag, filter it out to +resolve error: unknown argument: '-mno-riscv-attribute'. + +Define `BINDGEN_TARGET_riscv` to pass the target triplet to Rust bindgen +libclang for RISC-V to resolve error: unsupported argument 'medany' to +option '-mcmodel=' for target 'unknown'. + +Update the documentation, GCC + Rust builds for RISC-V are now +maintained. + +Acked-by: Miguel Ojeda +Signed-off-by: Asuna Yang +Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-4-2ac86ba728c8@isrc.iscas.ac.cn +Signed-off-by: Han Gao +--- + Documentation/rust/arch-support.rst | 2 +- + arch/riscv/Kconfig | 35 ++++++++++++++++++++++++++++- + rust/Makefile | 3 ++- + scripts/Makefile.rust | 1 + + 4 files changed, 38 insertions(+), 3 deletions(-) + +diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst +index 6e6a515d0899..5282e0e174e8 100644 +--- a/Documentation/rust/arch-support.rst ++++ b/Documentation/rust/arch-support.rst +@@ -18,7 +18,7 @@ Architecture Level of support Constraints + ``arm`` Maintained ARMv7 Little Endian only. + ``arm64`` Maintained Little Endian only. + ``loongarch`` Maintained \- +-``riscv`` Maintained ``riscv64`` and LLVM/Clang only. ++``riscv`` Maintained ``riscv64`` only. + ``um`` Maintained \- + ``x86`` Maintained ``x86_64`` only. + ============= ================ ============================================== +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 32b6aa8dece7..602b84e2b05b 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -196,7 +196,7 @@ config RISCV + select HAVE_REGS_AND_STACK_ACCESS_API + select HAVE_RETHOOK if !XIP_KERNEL + select HAVE_RSEQ +- select HAVE_RUST if RUSTC_SUPPORTS_RISCV && CC_IS_CLANG ++ select HAVE_RUST if RUSTC_SUPPORTS_RISCV && TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI + select HAVE_SAMPLE_FTRACE_DIRECT + select HAVE_SAMPLE_FTRACE_DIRECT_MULTI + select HAVE_STACKPROTECTOR +@@ -620,6 +620,8 @@ config TOOLCHAIN_HAS_V + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32imv) + depends on LD_IS_LLD || LD_VERSION >= 23800 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64imv) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32imv) + + config RISCV_ISA_V + bool "Vector extension support" +@@ -684,6 +686,8 @@ config TOOLCHAIN_HAS_ZABHA + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zabha) + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zabha) + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zabha) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zabha) + + config RISCV_ISA_ZABHA + bool "Zabha extension support for atomic byte/halfword operations" +@@ -702,6 +706,8 @@ config TOOLCHAIN_HAS_ZACAS + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zacas) + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zacas) + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zacas) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zacas) + + config RISCV_ISA_ZACAS + bool "Zacas extension support for atomic CAS" +@@ -720,6 +726,8 @@ config TOOLCHAIN_HAS_ZBB + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb) + depends on LD_IS_LLD || LD_VERSION >= 23900 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbb) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbb) + + # This symbol indicates that the toolchain supports all v1.0 vector crypto + # extensions, including Zvk*, Zvbb, and Zvbc. LLVM added all of these at once. +@@ -735,6 +743,8 @@ config TOOLCHAIN_HAS_ZBA + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba) + depends on LD_IS_LLD || LD_VERSION >= 23900 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zba) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zba) + + config RISCV_ISA_ZBA + bool "Zba extension support for bit manipulation instructions" +@@ -770,6 +780,8 @@ config TOOLCHAIN_HAS_ZBC + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc) + depends on LD_IS_LLD || LD_VERSION >= 23900 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbc) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbc) + + config RISCV_ISA_ZBC + bool "Zbc extension support for carry-less multiplication instructions" +@@ -793,6 +805,8 @@ config TOOLCHAIN_HAS_ZBKB + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbkb) + depends on LD_IS_LLD || LD_VERSION >= 23900 + depends on AS_HAS_OPTION_ARCH ++ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbkb) ++ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbkb) + + config RISCV_ISA_ZBKB + bool "Zbkb extension support for bit manipulation instructions" +@@ -894,6 +908,25 @@ config TOOLCHAIN_NEEDS_OLD_ISA_SPEC + versions of clang and GCC to be passed to GAS, which has the same result + as passing zicsr and zifencei to -march. + ++config RUST_BINDGEN_HAS_ZICSR_ZIFENCEI ++ def_bool y ++ depends on !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zicsr_zifencei) ++ depends on !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zicsr_zifencei) ++ ++config TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI ++ def_bool y ++ # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16 ++ depends on TOOLCHAIN_NEEDS_OLD_ISA_SPEC || !TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI || RUST_BINDGEN_HAS_ZICSR_ZIFENCEI ++ help ++ LLVM/Clang >= 17.0.0 starts recognizing Zicsr/Zifencei in -march, passing ++ them to -march doesn't generate an error anymore, and passing them or not ++ doesn't have any real difference, it still follows ISA before version ++ 20190608 - Zicsr/Zifencei are included in base ISA. ++ ++ The current latest version of LLVM/Clang still does not require explicit ++ Zicsr/Zifencei to enable these two extensions, Clang just accepts them in ++ -march and then silently ignores them. ++ + config FPU + bool "FPU support" + default y +diff --git a/rust/Makefile b/rust/Makefile +index 314329e6bc46..a64cdd92ef03 100644 +--- a/rust/Makefile ++++ b/rust/Makefile +@@ -402,7 +402,8 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ + -fstrict-flex-arrays=% -fmin-function-alignment=% \ + -fzero-init-padding-bits=% -mno-fdpic \ + -fdiagnostics-show-context -fdiagnostics-show-context=% \ +- --param=% --param asan-% -fno-isolate-erroneous-paths-dereference ++ --param=% --param asan-% -fno-isolate-erroneous-paths-dereference \ ++ -mno-riscv-attribute + + # Because scripts/Makefile.rust is included regardless of whether Rust is enabled, + # we perform this check here to avoid breaking targets that do not yet support Rust builds. +diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust +index 5c12b4b8c8b6..bfdad4a0a3ce 100644 +--- a/scripts/Makefile.rust ++++ b/scripts/Makefile.rust +@@ -3,6 +3,7 @@ BINDGEN_TARGET_x86 := x86_64-linux-gnu + BINDGEN_TARGET_arm64 := aarch64-linux-gnu + BINDGEN_TARGET_arm := arm-linux-gnueabi + BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf ++BINDGEN_TARGET_riscv := riscv64-linux-gnu + BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) + BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) + +-- +2.53.0 + diff --git a/SPECS/linux/0110-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch b/SPECS/linux/0110-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch deleted file mode 100644 index 0fbf3f1532..0000000000 --- a/SPECS/linux/0110-FROMLIST-rust-add-a-Kconfig-function-to-test-for-sup.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 183abdb6e9049001ddc924585b6fdd557260b1f1 Mon Sep 17 00:00:00 2001 -From: Asuna Yang -Date: Tue, 30 Dec 2025 17:47:56 +0100 -Subject: [PATCH 110/269] FROMLIST: rust: add a Kconfig function to test for - support of bindgen options - -Add a new `bindgen-backend-option` Kconfig function to test whether the -bindgen backend supports a given flag. - -A subsequent commit will use this function to test for RISC-V extension -flags. - -Signed-off-by: Asuna Yang -Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-3-2ac86ba728c8@isrc.iscas.ac.cn -Signed-off-by: Han Gao ---- - scripts/Kconfig.include | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include -index fc10671c297c..ea5be3c622a8 100644 ---- a/scripts/Kconfig.include -+++ b/scripts/Kconfig.include -@@ -76,3 +76,8 @@ rustc-llvm-version := $(shell,$(srctree)/scripts/rustc-llvm-version.sh $(RUSTC)) - # If you are testing for unstable features, consider testing RUSTC_VERSION - # instead, as features may have different completeness while available. - rustc-option = $(success,trap "rm -rf .tmp_$$" EXIT; mkdir .tmp_$$; $(RUSTC) $(1) --crate-type=rlib /dev/null --out-dir=.tmp_$$ -o .tmp_$$/tmp.rlib) -+ -+# $(bindgen-backend-option,) -+# Return y if bindgen backend supports , n otherwise -+# For now, the backend refers only to libclang, so more specifically, this function tests whether the given flag is recognized by the libclang used by bindgen. -+bindgen-backend-option = $(success,$(BINDGEN) /dev/null -- -x c --target=$(BINDGEN_TARGET) $(1)) --- -2.53.0 - diff --git a/SPECS/linux/0111-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch b/SPECS/linux/0111-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch deleted file mode 100644 index b21e87d9c9..0000000000 --- a/SPECS/linux/0111-FROMLIST-RISC-V-handle-extension-configs-for-bindgen.patch +++ /dev/null @@ -1,183 +0,0 @@ -From 95ae77c238fd1d3bf911e2bc963f3e0ee0c2a626 Mon Sep 17 00:00:00 2001 -From: Asuna Yang -Date: Tue, 30 Dec 2025 17:47:57 +0100 -Subject: [PATCH 111/269] FROMLIST: RISC-V: handle extension configs for - bindgen, re-enable gcc + rust builds - -Commit 33549fcf37ec ("RISC-V: disallow gcc + rust builds") disabled GCC -+ Rust builds for RISC-V due to differences in extension handling -compared to LLVM. This commit enables GCC + Rust builds again. - -Add `bindgen-option` conditions for the availability of libclang to the -RISC-V extension Kconfig symbols that depend on the `cc-option` -function. - -For Zicsr/Zifencei special handling, since LLVM/Clang always enables -these two extensions, either don't pass them to `-march`, or pass them -explicitly and Rust bindgen libclang must recognize them. - -Clang does not support `-mno-riscv-attribute` flag, filter it out to -resolve error: unknown argument: '-mno-riscv-attribute'. - -Define `BINDGEN_TARGET_riscv` to pass the target triplet to Rust bindgen -libclang for RISC-V to resolve error: unsupported argument 'medany' to -option '-mcmodel=' for target 'unknown'. - -Update the documentation, GCC + Rust builds for RISC-V are now -maintained. - -Acked-by: Miguel Ojeda -Signed-off-by: Asuna Yang -Link: https://lore.kernel.org/r/20251230-gcc-rust-v5-v6-4-2ac86ba728c8@isrc.iscas.ac.cn -Signed-off-by: Han Gao ---- - Documentation/rust/arch-support.rst | 2 +- - arch/riscv/Kconfig | 35 ++++++++++++++++++++++++++++- - rust/Makefile | 3 ++- - scripts/Makefile.rust | 1 + - 4 files changed, 38 insertions(+), 3 deletions(-) - -diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst -index 6e6a515d0899..5282e0e174e8 100644 ---- a/Documentation/rust/arch-support.rst -+++ b/Documentation/rust/arch-support.rst -@@ -18,7 +18,7 @@ Architecture Level of support Constraints - ``arm`` Maintained ARMv7 Little Endian only. - ``arm64`` Maintained Little Endian only. - ``loongarch`` Maintained \- --``riscv`` Maintained ``riscv64`` and LLVM/Clang only. -+``riscv`` Maintained ``riscv64`` only. - ``um`` Maintained \- - ``x86`` Maintained ``x86_64`` only. - ============= ================ ============================================== -diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index 32b6aa8dece7..602b84e2b05b 100644 ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -196,7 +196,7 @@ config RISCV - select HAVE_REGS_AND_STACK_ACCESS_API - select HAVE_RETHOOK if !XIP_KERNEL - select HAVE_RSEQ -- select HAVE_RUST if RUSTC_SUPPORTS_RISCV && CC_IS_CLANG -+ select HAVE_RUST if RUSTC_SUPPORTS_RISCV && TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI - select HAVE_SAMPLE_FTRACE_DIRECT - select HAVE_SAMPLE_FTRACE_DIRECT_MULTI - select HAVE_STACKPROTECTOR -@@ -620,6 +620,8 @@ config TOOLCHAIN_HAS_V - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32imv) - depends on LD_IS_LLD || LD_VERSION >= 23800 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64imv) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32imv) - - config RISCV_ISA_V - bool "Vector extension support" -@@ -684,6 +686,8 @@ config TOOLCHAIN_HAS_ZABHA - depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zabha) - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zabha) - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zabha) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zabha) - - config RISCV_ISA_ZABHA - bool "Zabha extension support for atomic byte/halfword operations" -@@ -702,6 +706,8 @@ config TOOLCHAIN_HAS_ZACAS - depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zacas) - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zacas) - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zacas) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zacas) - - config RISCV_ISA_ZACAS - bool "Zacas extension support for atomic CAS" -@@ -720,6 +726,8 @@ config TOOLCHAIN_HAS_ZBB - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb) - depends on LD_IS_LLD || LD_VERSION >= 23900 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbb) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbb) - - # This symbol indicates that the toolchain supports all v1.0 vector crypto - # extensions, including Zvk*, Zvbb, and Zvbc. LLVM added all of these at once. -@@ -735,6 +743,8 @@ config TOOLCHAIN_HAS_ZBA - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba) - depends on LD_IS_LLD || LD_VERSION >= 23900 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zba) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zba) - - config RISCV_ISA_ZBA - bool "Zba extension support for bit manipulation instructions" -@@ -770,6 +780,8 @@ config TOOLCHAIN_HAS_ZBC - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbc) - depends on LD_IS_LLD || LD_VERSION >= 23900 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbc) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbc) - - config RISCV_ISA_ZBC - bool "Zbc extension support for carry-less multiplication instructions" -@@ -793,6 +805,8 @@ config TOOLCHAIN_HAS_ZBKB - depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbkb) - depends on LD_IS_LLD || LD_VERSION >= 23900 - depends on AS_HAS_OPTION_ARCH -+ depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zbkb) -+ depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zbkb) - - config RISCV_ISA_ZBKB - bool "Zbkb extension support for bit manipulation instructions" -@@ -894,6 +908,25 @@ config TOOLCHAIN_NEEDS_OLD_ISA_SPEC - versions of clang and GCC to be passed to GAS, which has the same result - as passing zicsr and zifencei to -march. - -+config RUST_BINDGEN_HAS_ZICSR_ZIFENCEI -+ def_bool y -+ depends on !64BIT || $(bindgen-backend-option,-mabi=lp64 -march=rv64ima_zicsr_zifencei) -+ depends on !32BIT || $(bindgen-backend-option,-mabi=ilp32 -march=rv32ima_zicsr_zifencei) -+ -+config TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI -+ def_bool y -+ # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16 -+ depends on TOOLCHAIN_NEEDS_OLD_ISA_SPEC || !TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI || RUST_BINDGEN_HAS_ZICSR_ZIFENCEI -+ help -+ LLVM/Clang >= 17.0.0 starts recognizing Zicsr/Zifencei in -march, passing -+ them to -march doesn't generate an error anymore, and passing them or not -+ doesn't have any real difference, it still follows ISA before version -+ 20190608 - Zicsr/Zifencei are included in base ISA. -+ -+ The current latest version of LLVM/Clang still does not require explicit -+ Zicsr/Zifencei to enable these two extensions, Clang just accepts them in -+ -march and then silently ignores them. -+ - config FPU - bool "FPU support" - default y -diff --git a/rust/Makefile b/rust/Makefile -index 314329e6bc46..a64cdd92ef03 100644 ---- a/rust/Makefile -+++ b/rust/Makefile -@@ -402,7 +402,8 @@ bindgen_skip_c_flags := -mno-fp-ret-in-387 -mpreferred-stack-boundary=% \ - -fstrict-flex-arrays=% -fmin-function-alignment=% \ - -fzero-init-padding-bits=% -mno-fdpic \ - -fdiagnostics-show-context -fdiagnostics-show-context=% \ -- --param=% --param asan-% -fno-isolate-erroneous-paths-dereference -+ --param=% --param asan-% -fno-isolate-erroneous-paths-dereference \ -+ -mno-riscv-attribute - - # Because scripts/Makefile.rust is included regardless of whether Rust is enabled, - # we perform this check here to avoid breaking targets that do not yet support Rust builds. -diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust -index 5c12b4b8c8b6..bfdad4a0a3ce 100644 ---- a/scripts/Makefile.rust -+++ b/scripts/Makefile.rust -@@ -3,6 +3,7 @@ BINDGEN_TARGET_x86 := x86_64-linux-gnu - BINDGEN_TARGET_arm64 := aarch64-linux-gnu - BINDGEN_TARGET_arm := arm-linux-gnueabi - BINDGEN_TARGET_loongarch := loongarch64-linux-gnusf -+BINDGEN_TARGET_riscv := riscv64-linux-gnu - BINDGEN_TARGET_um := $(BINDGEN_TARGET_$(SUBARCH)) - BINDGEN_TARGET := $(BINDGEN_TARGET_$(SRCARCH)) - --- -2.53.0 - diff --git a/SPECS/linux/0111-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch b/SPECS/linux/0111-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch new file mode 100644 index 0000000000..81053adce1 --- /dev/null +++ b/SPECS/linux/0111-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch @@ -0,0 +1,56 @@ +From 6e620bf424d37f6c38f9673b3fe7c9b2d43663d7 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Sun, 21 Dec 2025 16:20:26 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add reset + support + +The SpacemiT SDHCI controller has two reset lines, one connect to AXI bus +which shared by all controllers, while another one connect to individual +controller separately. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20251221-07-k1-sdhci-reset-v1-1-6780af7fa6e7@gentoo.org +Signed-off-by: Han Gao +--- + .../devicetree/bindings/mmc/spacemit,sdhci.yaml | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +index 383841369fb2..1081ea687702 100644 +--- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml ++++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +@@ -34,12 +34,24 @@ properties: + - const: core + - const: io + ++ resets: ++ items: ++ - description: axi reset, connect to AXI bus, shared by all controllers ++ - description: sdh reset, connect to individual controller separately ++ ++ reset-names: ++ items: ++ - const: axi ++ - const: sdh ++ + required: + - compatible + - reg + - interrupts + - clocks + - clock-names ++ - resets ++ - reset-names + + unevaluatedProperties: false + +@@ -52,4 +64,6 @@ examples: + interrupt-parent = <&plic>; + clocks = <&clk_apmu 10>, <&clk_apmu 13>; + clock-names = "core", "io"; ++ resets = <&syscon_apmu 2>, <&syscon_apmu 5>; ++ reset-names = "axi", "sdh"; + }; +-- +2.53.0 + diff --git a/SPECS/linux/0112-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch b/SPECS/linux/0112-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch deleted file mode 100644 index 11019b7de3..0000000000 --- a/SPECS/linux/0112-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-reset-su.patch +++ /dev/null @@ -1,56 +0,0 @@ -From aeb31419784677a87248ff06272de73ff9786ec4 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sun, 21 Dec 2025 16:20:26 +0800 -Subject: [PATCH 112/269] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add reset - support - -The SpacemiT SDHCI controller has two reset lines, one connect to AXI bus -which shared by all controllers, while another one connect to individual -controller separately. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20251221-07-k1-sdhci-reset-v1-1-6780af7fa6e7@gentoo.org -Signed-off-by: Han Gao ---- - .../devicetree/bindings/mmc/spacemit,sdhci.yaml | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -index 383841369fb2..1081ea687702 100644 ---- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -+++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -@@ -34,12 +34,24 @@ properties: - - const: core - - const: io - -+ resets: -+ items: -+ - description: axi reset, connect to AXI bus, shared by all controllers -+ - description: sdh reset, connect to individual controller separately -+ -+ reset-names: -+ items: -+ - const: axi -+ - const: sdh -+ - required: - - compatible - - reg - - interrupts - - clocks - - clock-names -+ - resets -+ - reset-names - - unevaluatedProperties: false - -@@ -52,4 +64,6 @@ examples: - interrupt-parent = <&plic>; - clocks = <&clk_apmu 10>, <&clk_apmu 13>; - clock-names = "core", "io"; -+ resets = <&syscon_apmu 2>, <&syscon_apmu 5>; -+ reset-names = "axi", "sdh"; - }; --- -2.53.0 - diff --git a/SPECS/linux/0112-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch b/SPECS/linux/0112-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch new file mode 100644 index 0000000000..e5ecaae954 --- /dev/null +++ b/SPECS/linux/0112-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch @@ -0,0 +1,31 @@ +From 6eabd498399cf0d21a39ed6c1c658d478009c8a3 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Mon, 3 Nov 2025 00:02:00 +0100 +Subject: [RUYI PATCH] FROMLIST: mfd: simple-mfd-i2c: add a reboot cell for the + SpacemiT P1 chip + +Add a "spacemit-p1-reboot" cell for the SpacemiT P1 chip. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Troy Mitchell +Link: https://lore.kernel.org/r/20251102230352.914421-3-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + drivers/mfd/simple-mfd-i2c.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c +index 7315fad618e4..52c81b18750e 100644 +--- a/drivers/mfd/simple-mfd-i2c.c ++++ b/drivers/mfd/simple-mfd-i2c.c +@@ -105,6 +105,7 @@ static const struct regmap_config spacemit_p1_regmap_config = { + }; + + static const struct mfd_cell spacemit_p1_cells[] = { ++ { .name = "spacemit-p1-reboot", }, + { .name = "spacemit-p1-regulator", }, + { .name = "spacemit-p1-rtc", }, + }; +-- +2.53.0 + diff --git a/SPECS/linux/0113-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch b/SPECS/linux/0113-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch deleted file mode 100644 index f0ca20bc70..0000000000 --- a/SPECS/linux/0113-FROMLIST-mfd-simple-mfd-i2c-add-a-reboot-cell-for-th.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 5d374798992af7036555dc0a8fc3e295b90dabf2 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Mon, 3 Nov 2025 00:02:00 +0100 -Subject: [PATCH 113/269] FROMLIST: mfd: simple-mfd-i2c: add a reboot cell for - the SpacemiT P1 chip - -Add a "spacemit-p1-reboot" cell for the SpacemiT P1 chip. - -Signed-off-by: Aurelien Jarno -Reviewed-by: Troy Mitchell -Link: https://lore.kernel.org/r/20251102230352.914421-3-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - drivers/mfd/simple-mfd-i2c.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c -index 7315fad618e4..52c81b18750e 100644 ---- a/drivers/mfd/simple-mfd-i2c.c -+++ b/drivers/mfd/simple-mfd-i2c.c -@@ -105,6 +105,7 @@ static const struct regmap_config spacemit_p1_regmap_config = { - }; - - static const struct mfd_cell spacemit_p1_cells[] = { -+ { .name = "spacemit-p1-reboot", }, - { .name = "spacemit-p1-regulator", }, - { .name = "spacemit-p1-rtc", }, - }; --- -2.53.0 - diff --git a/SPECS/linux/0113-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch b/SPECS/linux/0113-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch new file mode 100644 index 0000000000..acd1ec7be3 --- /dev/null +++ b/SPECS/linux/0113-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch @@ -0,0 +1,45 @@ +From 976165527481e44220f9bc835db53aa0c66bd96c Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 16:38:54 +0800 +Subject: [RUYI PATCH] FROMLIST: regulator: spacemit: MFD_SPACEMIT_P1 as + dependencies + +REGULATOR_SPACEMIT_P1 is a subdevice of P1 and should depend on +MFD_SPACEMIT_P1 rather than selecting it directly. Using 'select' +does not always respect the parent's dependencies, so 'depends on' +is the safer and more correct choice. + +Since MFD_SPACEMIT_P1 already depends on I2C_K1, the dependency +in REGULATOR_SPACEMIT_P1 is now redundant. + +Additionally, the default value depends on MFD_SPACEMIT_P1 rather +than ARCH_SPACEMIT. + +Acked-by: Mark Brown +Acked-by: Alex Elder +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260108-p1-kconfig-fix-v5-1-6fe19f460269@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/regulator/Kconfig | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig +index d10b6f9243d5..9563b33b6bf2 100644 +--- a/drivers/regulator/Kconfig ++++ b/drivers/regulator/Kconfig +@@ -1514,9 +1514,8 @@ config REGULATOR_SLG51000 + config REGULATOR_SPACEMIT_P1 + tristate "SpacemiT P1 regulators" + depends on ARCH_SPACEMIT || COMPILE_TEST +- depends on I2C +- select MFD_SPACEMIT_P1 +- default ARCH_SPACEMIT ++ depends on MFD_SPACEMIT_P1 ++ default m if MFD_SPACEMIT_P1 + help + Enable support for regulators implemented by the SpacemiT P1 + power controller. The P1 implements 6 high-efficiency buck +-- +2.53.0 + diff --git a/SPECS/linux/0114-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch b/SPECS/linux/0114-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch deleted file mode 100644 index 69fb72ab3a..0000000000 --- a/SPECS/linux/0114-FROMLIST-regulator-spacemit-MFD_SPACEMIT_P1-as-depen.patch +++ /dev/null @@ -1,45 +0,0 @@ -From a41d659ee4ecfe909099727cd1a3215d78bff00c Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 8 Jan 2026 16:38:54 +0800 -Subject: [PATCH 114/269] FROMLIST: regulator: spacemit: MFD_SPACEMIT_P1 as - dependencies - -REGULATOR_SPACEMIT_P1 is a subdevice of P1 and should depend on -MFD_SPACEMIT_P1 rather than selecting it directly. Using 'select' -does not always respect the parent's dependencies, so 'depends on' -is the safer and more correct choice. - -Since MFD_SPACEMIT_P1 already depends on I2C_K1, the dependency -in REGULATOR_SPACEMIT_P1 is now redundant. - -Additionally, the default value depends on MFD_SPACEMIT_P1 rather -than ARCH_SPACEMIT. - -Acked-by: Mark Brown -Acked-by: Alex Elder -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260108-p1-kconfig-fix-v5-1-6fe19f460269@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/regulator/Kconfig | 5 ++--- - 1 file changed, 2 insertions(+), 3 deletions(-) - -diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig -index d10b6f9243d5..9563b33b6bf2 100644 ---- a/drivers/regulator/Kconfig -+++ b/drivers/regulator/Kconfig -@@ -1514,9 +1514,8 @@ config REGULATOR_SLG51000 - config REGULATOR_SPACEMIT_P1 - tristate "SpacemiT P1 regulators" - depends on ARCH_SPACEMIT || COMPILE_TEST -- depends on I2C -- select MFD_SPACEMIT_P1 -- default ARCH_SPACEMIT -+ depends on MFD_SPACEMIT_P1 -+ default m if MFD_SPACEMIT_P1 - help - Enable support for regulators implemented by the SpacemiT P1 - power controller. The P1 implements 6 high-efficiency buck --- -2.53.0 - diff --git a/SPECS/linux/0114-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch b/SPECS/linux/0114-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch new file mode 100644 index 0000000000..4fa974501c --- /dev/null +++ b/SPECS/linux/0114-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch @@ -0,0 +1,37 @@ +From 3bc961796efe1b697fbf81f5cd6f48fe21f71d43 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 16:38:56 +0800 +Subject: [RUYI PATCH] FROMLIST: rtc: spacemit: default module when + MFD_SPACEMIT_P1 is enabled + +The RTC driver defaulted to the same value as MFD_SPACEMIT_P1, which +caused it to be built-in automatically whenever the PMIC support was +set to y. + +This is not always desirable, as the RTC function is not required on +all platforms using the SpacemiT P1 PMIC. + +Acked-by: Alex Elder +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260108-p1-kconfig-fix-v5-3-6fe19f460269@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/rtc/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig +index b46ac73a2124..67f39eae0234 100644 +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -410,7 +410,7 @@ config RTC_DRV_SPACEMIT_P1 + tristate "SpacemiT P1 RTC" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on MFD_SPACEMIT_P1 +- default MFD_SPACEMIT_P1 ++ default m if MFD_SPACEMIT_P1 + help + Enable support for the RTC function in the SpacemiT P1 PMIC. + This driver can also be built as a module, which will be called +-- +2.53.0 + diff --git a/SPECS/linux/0115-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch b/SPECS/linux/0115-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch deleted file mode 100644 index 2db92d4f7d..0000000000 --- a/SPECS/linux/0115-FROMLIST-rtc-spacemit-default-module-when-MFD_SPACEM.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 088a477295ecdf9de9b20588affe5345edc597af Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 8 Jan 2026 16:38:56 +0800 -Subject: [PATCH 115/269] FROMLIST: rtc: spacemit: default module when - MFD_SPACEMIT_P1 is enabled - -The RTC driver defaulted to the same value as MFD_SPACEMIT_P1, which -caused it to be built-in automatically whenever the PMIC support was -set to y. - -This is not always desirable, as the RTC function is not required on -all platforms using the SpacemiT P1 PMIC. - -Acked-by: Alex Elder -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260108-p1-kconfig-fix-v5-3-6fe19f460269@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/rtc/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig -index b46ac73a2124..67f39eae0234 100644 ---- a/drivers/rtc/Kconfig -+++ b/drivers/rtc/Kconfig -@@ -410,7 +410,7 @@ config RTC_DRV_SPACEMIT_P1 - tristate "SpacemiT P1 RTC" - depends on ARCH_SPACEMIT || COMPILE_TEST - depends on MFD_SPACEMIT_P1 -- default MFD_SPACEMIT_P1 -+ default m if MFD_SPACEMIT_P1 - help - Enable support for the RTC function in the SpacemiT P1 PMIC. - This driver can also be built as a module, which will be called --- -2.53.0 - diff --git a/SPECS/linux/0115-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch b/SPECS/linux/0115-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch new file mode 100644 index 0000000000..6668a8d3da --- /dev/null +++ b/SPECS/linux/0115-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch @@ -0,0 +1,112 @@ +From d8fc3735923c949b5513f0ef5bd06d3d34b9b6a8 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Sat, 2 May 2026 21:30:51 -0400 +Subject: [RUYI PATCH] FROMLIST: spi: dt-bindings: add SpacemiT K1 SPI support + +Add support for the SPI controller implemented by the SpacemiT K1 SoC. + +Acked-by: Conor Dooley +Acked-by: Troy Mitchell +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Alex Elder +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-1-f412e1ae8a34@riscstar.com +Signed-off-by: Han Gao +--- + .../bindings/spi/spacemit,k1-spi.yaml | 84 +++++++++++++++++++ + 1 file changed, 84 insertions(+) + create mode 100644 Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml + +diff --git a/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml +new file mode 100644 +index 000000000000..e82c7f8d0b98 +--- /dev/null ++++ b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml +@@ -0,0 +1,84 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/spi/spacemit,k1-spi.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 SoC Serial Peripheral Interface (SPI) ++ ++maintainers: ++ - Alex Elder ++ ++description: ++ The SpacemiT K1 SoC implements a SPI controller that has two 32-entry ++ FIFOs, for transmit and receive. Details are currently available in ++ section 18.2.1 of the K1 User Manual, found in the SpacemiT Keystone ++ K1 Documentation[1]. The controller transfers words using PIO. DMA ++ transfers are supported as well, if both TX and RX DMA channels are ++ specified, ++ ++ [1] https://developer.spacemit.com/documentation ++ ++allOf: ++ - $ref: /schemas/spi/spi-controller.yaml# ++ ++properties: ++ compatible: ++ const: spacemit,k1-spi ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Core clock ++ - description: Bus clock ++ ++ clock-names: ++ items: ++ - const: core ++ - const: bus ++ ++ resets: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ dmas: ++ items: ++ - description: RX DMA channel ++ - description: TX DMA channel ++ ++ dma-names: ++ items: ++ - const: rx ++ - const: tx ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - interrupts ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ ++ #include ++ spi@d401c000 { ++ compatible = "spacemit,k1-spi"; ++ reg = <0xd401c000 0x30>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&syscon_apbc CLK_SSP3>, ++ <&syscon_apbc CLK_SSP3_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_SSP3>; ++ interrupts = <55>; ++ dmas = <&pdma 20>, <&pdma 19>; ++ dma-names = "rx", "tx"; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux/0116-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch b/SPECS/linux/0116-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch deleted file mode 100644 index 59799fea39..0000000000 --- a/SPECS/linux/0116-FROMLIST-spi-dt-bindings-add-SpacemiT-K1-SPI-support.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 3dcb56851d49cf4c3bfe780bcc4ba987abcfeb0b Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Sat, 2 May 2026 21:30:51 -0400 -Subject: [PATCH 116/269] FROMLIST: spi: dt-bindings: add SpacemiT K1 SPI - support - -Add support for the SPI controller implemented by the SpacemiT K1 SoC. - -Acked-by: Conor Dooley -Acked-by: Troy Mitchell -Reviewed-by: Rob Herring (Arm) -Signed-off-by: Alex Elder -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-1-f412e1ae8a34@riscstar.com -Signed-off-by: Han Gao ---- - .../bindings/spi/spacemit,k1-spi.yaml | 84 +++++++++++++++++++ - 1 file changed, 84 insertions(+) - create mode 100644 Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml - -diff --git a/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml -new file mode 100644 -index 000000000000..e82c7f8d0b98 ---- /dev/null -+++ b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml -@@ -0,0 +1,84 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/spi/spacemit,k1-spi.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K1 SoC Serial Peripheral Interface (SPI) -+ -+maintainers: -+ - Alex Elder -+ -+description: -+ The SpacemiT K1 SoC implements a SPI controller that has two 32-entry -+ FIFOs, for transmit and receive. Details are currently available in -+ section 18.2.1 of the K1 User Manual, found in the SpacemiT Keystone -+ K1 Documentation[1]. The controller transfers words using PIO. DMA -+ transfers are supported as well, if both TX and RX DMA channels are -+ specified, -+ -+ [1] https://developer.spacemit.com/documentation -+ -+allOf: -+ - $ref: /schemas/spi/spi-controller.yaml# -+ -+properties: -+ compatible: -+ const: spacemit,k1-spi -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: Core clock -+ - description: Bus clock -+ -+ clock-names: -+ items: -+ - const: core -+ - const: bus -+ -+ resets: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ dmas: -+ items: -+ - description: RX DMA channel -+ - description: TX DMA channel -+ -+ dma-names: -+ items: -+ - const: rx -+ - const: tx -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - resets -+ - interrupts -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ -+ #include -+ spi@d401c000 { -+ compatible = "spacemit,k1-spi"; -+ reg = <0xd401c000 0x30>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&syscon_apbc CLK_SSP3>, -+ <&syscon_apbc CLK_SSP3_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_SSP3>; -+ interrupts = <55>; -+ dmas = <&pdma 20>, <&pdma 19>; -+ dma-names = "rx", "tx"; -+ }; --- -2.53.0 - diff --git a/SPECS/linux/0116-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch b/SPECS/linux/0116-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch new file mode 100644 index 0000000000..df413fe625 --- /dev/null +++ b/SPECS/linux/0116-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch @@ -0,0 +1,852 @@ +From 733d647fce838e188c739aa90fdc75c68e51b0d1 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Sat, 2 May 2026 21:30:52 -0400 +Subject: [RUYI PATCH] FROMLIST: spi: spacemit: introduce SpacemiT K1 SPI + controller driver + +This patch introduces the driver for the SPI controller found in the +SpacemiT K1 SoC. Currently the driver supports master mode only. +The SPI hardware implements RX and TX FIFOs, 32 entries each, and +supports both PIO and DMA mode transfers. + +Signed-off-by: Alex Elder +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-2-f412e1ae8a34@riscstar.com +Signed-off-by: Han Gao +--- + drivers/spi/Kconfig | 9 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-spacemit-k1.c | 789 ++++++++++++++++++++++++++++++++++ + 3 files changed, 799 insertions(+) + create mode 100644 drivers/spi/spi-spacemit-k1.c + +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index c3b2f02f5912..b50d9ae1a498 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -1085,6 +1085,15 @@ config SPI_SG2044_NOR + also supporting 3Byte address devices and 4Byte address + devices. + ++config SPI_SPACEMIT_K1 ++ tristate "K1 SPI Controller" ++ depends on ARCH_SPACEMIT || COMPILE_TEST ++ depends on OF ++ imply MMP_PDMA if ARCH_SPACEMIT ++ default m if ARCH_SPACEMIT ++ help ++ Enable support for the SpacemiT K1 SPI controller. ++ + config SPI_SPRD + tristate "Spreadtrum SPI controller" + depends on ARCH_SPRD || COMPILE_TEST +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 9d36190a9884..9fa12498ce8c 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -143,6 +143,7 @@ obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o + obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o + obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o + obj-$(CONFIG_SPI_SG2044_NOR) += spi-sg2044-nor.o ++obj-$(CONFIG_SPI_SPACEMIT_K1) += spi-spacemit-k1.o + obj-$(CONFIG_SPI_SPRD) += spi-sprd.o + obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o + obj-$(CONFIG_SPI_STM32) += spi-stm32.o +diff --git a/drivers/spi/spi-spacemit-k1.c b/drivers/spi/spi-spacemit-k1.c +new file mode 100644 +index 000000000000..99db429db0b2 +--- /dev/null ++++ b/drivers/spi/spi-spacemit-k1.c +@@ -0,0 +1,789 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// ++// SpacemiT K1 SPI controller driver ++// ++// Copyright (C) 2026, RISCstar Solutions Corporation ++// Copyright (C) 2023, SpacemiT Corporation ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "internals.h" ++ ++/* This is the range of transfer rates supported by the K1 SoC */ ++#define K1_SPI_MIN_SPEED_HZ 6250 ++#define K1_SPI_MAX_SPEED_HZ 51200000 ++ ++/* DMA constraints */ ++#define K1_SPI_DMA_ALIGNMENT 64 ++#define K1_SPI_MAX_DMA_LEN SZ_512K ++ ++/* SSP Top Control Register */ ++#define SSP_TOP_CTRL 0x00 ++#define TOP_SSE BIT(0) /* Enable port */ ++#define TOP_FRF_MASK GENMASK(2, 1) /* Frame format */ ++#define TOP_FRF_MOTOROLA 0 /* Motorola SPI */ ++#define TOP_DSS_MASK GENMASK(9, 5) /* Data size (1-32) */ ++#define TOP_SPO BIT(10) /* Polarity: 0=low */ ++#define TOP_SPH BIT(11) /* Half-cycle phase */ ++#define TOP_LBM BIT(12) /* Loopback mode */ ++#define TOP_TRAIL BIT(13) /* Trailing bytes */ ++#define TOP_HOLD_FRAME_LOW BIT(14) /* Chip select */ ++ ++/* SSP FIFO Control Register */ ++#define SSP_FIFO_CTRL 0x04 ++#define FIFO_TFT_MASK GENMASK(4, 0) /* TX FIFO threshold */ ++#define FIFO_RFT_MASK GENMASK(9, 5) /* RX FIFO threshold */ ++#define FIFO_TSRE BIT(10) /* TX service request */ ++#define FIFO_RSRE BIT(11) /* RX service request */ ++ ++/* SSP Interrupt Enable Register */ ++#define SSP_INT_EN 0x08 ++#define SSP_INT_EN_TINTE BIT(1) /* RX timeout */ ++#define SSP_INT_EN_RIE BIT(2) /* RX FIFO */ ++#define SSP_INT_EN_TIE BIT(3) /* TX FIFO */ ++#define SSP_INT_EN_RIM BIT(4) /* RX FIFO overrun */ ++#define SSP_INT_EN_TIM BIT(5) /* TX FIFO underrun */ ++#define SSP_INT_EN_EBCEI BIT(6) /* Bit count error */ ++ ++/* TX interrupts, RX interrupts, and error interrupts */ ++#define SSP_INT_EN_TX SSP_INT_EN_TIE ++#define SSP_INT_EN_RX \ ++ (SSP_INT_EN_TINTE | SSP_INT_EN_RIE) ++#define SSP_INT_EN_ERROR \ ++ (SSP_INT_EN_RIM | SSP_INT_EN_TIM | SSP_INT_EN_EBCEI) ++ ++/* SSP Time Out Register */ ++#define SSP_TIMEOUT 0x0c ++#define SSP_TIMEOUT_MASK GENMASK(23, 0) ++ ++/* SSP Data Register */ ++#define SSP_DATAR 0x10 ++ ++/* SSP Status Register */ ++#define SSP_STATUS 0x14 ++#define SSP_STATUS_BSY BIT(0) /* SPI/I2S busy */ ++#define SSP_STATUS_TNF BIT(6) /* TX FIFO not full */ ++#define SSP_STATUS_TFL GENMASK(11, 7) /* TX FIFO level */ ++#define SSP_STATUS_TUR BIT(12) /* TX FIFO underrun */ ++#define SSP_STATUS_RNE BIT(14) /* RX FIFO not empty */ ++#define SSP_STATUS_RFL GENMASK(19, 15) /* RX FIFO level */ ++#define SSP_STATUS_ROR BIT(20) /* RX FIFO overrun */ ++#define SSP_STATUS_BCE BIT(21) /* Bit count error */ ++ ++/* Error status mask */ ++#define SSP_STATUS_ERROR \ ++ (SSP_STATUS_TUR | SSP_STATUS_ROR | SSP_STATUS_BCE) ++ ++/* The FIFO sizes and thresholds are the same for RX and TX */ ++#define K1_SPI_FIFO_SIZE 32 ++#define K1_SPI_THRESH (K1_SPI_FIFO_SIZE / 2) ++ ++struct k1_spi_driver_data { ++ struct spi_controller *host; ++ void __iomem *base; ++ phys_addr_t base_addr; ++ unsigned long bus_rate; ++ struct clk *clk; ++ unsigned long rate; ++ int irq; ++ ++ /* Current transfer information; not valid if message is null */ ++ u32 bytes; /* Bytes used for bits_per_word */ ++ unsigned int rx_resid; /* RX bytes left in transfer */ ++ unsigned int tx_resid; /* TX bytes left in transfer */ ++ struct spi_transfer *transfer; /* Current transfer */ ++ ++ bool dma_enabled; ++}; ++ ++/* Set our registers to a known initial state */ ++static void ++k1_spi_register_reset(struct k1_spi_driver_data *drv_data, bool initial) ++{ ++ u32 val = 0; ++ ++ writel(0, drv_data->base + SSP_TOP_CTRL); ++ ++ if (initial) { ++ /* ++ * The TX and RX FIFO thresholds are the same no matter ++ * what the speed or bits per word, so we can just set ++ * them once. The thresholds are one more than the values ++ * in the register. ++ */ ++ val = FIELD_PREP(FIFO_RFT_MASK, K1_SPI_THRESH - 1); ++ val |= FIELD_PREP(FIFO_TFT_MASK, K1_SPI_THRESH - 1); ++ } ++ writel(val, drv_data->base + SSP_FIFO_CTRL); ++ ++ writel(0, drv_data->base + SSP_INT_EN); ++ writel(0, drv_data->base + SSP_TIMEOUT); ++ ++ /* Clear any pending interrupt conditions */ ++ writel(~0, drv_data->base + SSP_STATUS); ++} ++ ++/* ++ * The client can call the setup function multiple times, and each call ++ * can specify a different SPI mode (and transfer speed). Each transfer ++ * can specify its own speed though, and the core code ensures each ++ * transfer's speed is set to something nonzero and supported by both ++ * the controller and the device. We just set the speed for each transfer. ++ */ ++static int k1_spi_setup(struct spi_device *spi) ++{ ++ struct k1_spi_driver_data *drv_data; ++ u32 val; ++ ++ drv_data = spi_controller_get_devdata(spi->controller); ++ ++ /* ++ * Configure the message format for this device. We only ++ * support Motorola SPI format in master mode. ++ */ ++ val = FIELD_PREP(TOP_FRF_MASK, TOP_FRF_MOTOROLA); ++ ++ /* Translate the mode into the value used to program the hardware. */ ++ if (spi->mode & SPI_CPHA) ++ val |= TOP_SPH; /* 1/2 cycle */ ++ if (spi->mode & SPI_CPOL) ++ val |= TOP_SPO; /* active low */ ++ if (spi->mode & SPI_LOOP) ++ val |= TOP_LBM; /* enable loopback */ ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++ ++ return 0; ++} ++ ++static void k1_spi_cleanup(struct spi_device *spi) ++{ ++ struct k1_spi_driver_data *drv_data; ++ ++ drv_data = spi_controller_get_devdata(spi->controller); ++ k1_spi_register_reset(drv_data, false); ++} ++ ++static bool k1_spi_can_dma(struct spi_controller *host, struct spi_device *spi, ++ struct spi_transfer *transfer) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ u32 burst_size; ++ ++ if (!drv_data->dma_enabled) ++ return false; ++ ++ if (transfer->len > SZ_2K) ++ return false; ++ ++ /* Don't bother with DMA if we can't do even a single burst */ ++ burst_size = K1_SPI_THRESH * spi_bpw_to_bytes(transfer->bits_per_word); ++ ++ return transfer->len >= burst_size; ++} ++ ++static void k1_spi_dma_callback(void *param) ++{ ++ struct k1_spi_driver_data *drv_data = param; ++ u32 val; ++ ++ val = readl(drv_data->base + SSP_FIFO_CTRL); ++ val &= ~(FIFO_TSRE | FIFO_RSRE); ++ writel(val, drv_data->base + SSP_FIFO_CTRL); ++ ++ val = readl(drv_data->base + SSP_TOP_CTRL); ++ val &= ~TOP_TRAIL; ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++ ++ /* Check for any error conditions */ ++ val = readl(drv_data->base + SSP_STATUS); ++ if (val & SSP_STATUS_ERROR) ++ drv_data->transfer->error |= SPI_TRANS_FAIL_IO; ++ ++ /* Disable the port */ ++ val = readl(drv_data->base + SSP_TOP_CTRL); ++ val &= ~TOP_SSE; ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++ ++ drv_data->transfer = NULL; ++ ++ spi_finalize_current_transfer(drv_data->host); ++} ++ ++/* Prepare a descriptor for TX or RX DMA */ ++static struct dma_async_tx_descriptor * ++k1_spi_dma_prep(struct k1_spi_driver_data *drv_data, ++ struct spi_transfer *transfer, bool tx) ++{ ++ phys_addr_t addr = drv_data->base_addr + SSP_DATAR; ++ u32 burst_size = K1_SPI_THRESH * drv_data->bytes; ++ struct dma_slave_config cfg = { }; ++ enum dma_transfer_direction dir; ++ enum dma_slave_buswidth width; ++ struct dma_chan *chan; ++ struct sg_table *sgt; ++ ++ switch (drv_data->bytes) { ++ case 1: ++ width = DMA_SLAVE_BUSWIDTH_1_BYTE; ++ break; ++ case 2: ++ width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ break; ++ default: /* bytes == 4 */ ++ width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ break; ++ } ++ ++ if (tx) { ++ chan = drv_data->host->dma_tx; ++ sgt = &transfer->tx_sg; ++ dir = DMA_MEM_TO_DEV; ++ ++ cfg.dst_addr = addr; ++ cfg.dst_addr_width = width; ++ cfg.dst_maxburst = burst_size; ++ } else { ++ chan = drv_data->host->dma_rx; ++ sgt = &transfer->rx_sg; ++ dir = DMA_DEV_TO_MEM; ++ ++ cfg.src_addr = addr; ++ cfg.src_addr_width = width; ++ cfg.src_maxburst = burst_size; ++ } ++ cfg.direction = dir; ++ ++ if (dmaengine_slave_config(chan, &cfg)) ++ return NULL; ++ ++ return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); ++ ++} ++ ++static int k1_spi_dma_one(struct spi_controller *host, struct spi_device *spi, ++ struct spi_transfer *transfer) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ struct dma_async_tx_descriptor *desc; ++ u32 val; ++ ++ /* Prepare the TX descriptor and submit it */ ++ desc = k1_spi_dma_prep(drv_data, transfer, true); ++ if (!desc) ++ goto fallback; ++ dmaengine_submit(desc); ++ ++ /* Prepare the RX descriptor and submit it */ ++ desc = k1_spi_dma_prep(drv_data, transfer, false); ++ if (!desc) ++ goto fallback; ++ ++ /* When RX is complete we also know TX has completed */ ++ desc->callback = k1_spi_dma_callback; ++ desc->callback_param = drv_data; ++ ++ dmaengine_submit(desc); ++ ++ val = readl(drv_data->base + SSP_TOP_CTRL); ++ val |= TOP_TRAIL; /* Trailing bytes handled by DMA */ ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++ ++ val = readl(drv_data->base + SSP_FIFO_CTRL); ++ val |= FIFO_TSRE | FIFO_RSRE; ++ writel(val, drv_data->base + SSP_FIFO_CTRL); ++ ++ /* Start RX first so we're ready the instant we start transmitting */ ++ dma_async_issue_pending(host->dma_rx); ++ dma_async_issue_pending(host->dma_tx); ++ ++ return 1; ++fallback: ++ transfer->error |= SPI_TRANS_FAIL_NO_START; ++ ++ return -EAGAIN; ++} ++ ++/* Flush the RX FIFO of any leftover data before processing a message */ ++static int k1_spi_prepare_message(struct spi_controller *host, ++ struct spi_message *message) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ u32 val = readl(drv_data->base + SSP_STATUS); ++ u32 count; ++ ++ /* If there's nothing in the FIFO, we're done */ ++ if (!(val & SSP_STATUS_RNE)) ++ return 0; ++ ++ /* Read and discard what's there (one more than what the field says) */ ++ count = FIELD_GET(SSP_STATUS_RFL, val) + 1; ++ do ++ (void)readl(drv_data->base + SSP_DATAR); ++ while (--count); ++ ++ return 0; ++} ++ ++/* Set logic level of chip select line (high=true means CS deasserted) */ ++static void k1_spi_set_cs(struct spi_device *spi, bool high) ++{ ++ struct k1_spi_driver_data *drv_data; ++ u32 val; ++ ++ drv_data = spi_controller_get_devdata(spi->controller); ++ ++ val = readl(drv_data->base + SSP_TOP_CTRL); ++ if (high) ++ val &= ~TOP_HOLD_FRAME_LOW; ++ else ++ val |= TOP_HOLD_FRAME_LOW; ++ writel(val, drv_data->base + SSP_TOP_CTRL); ++} ++ ++/* Set the transfer speed; the SPI core code ensures it is supported */ ++static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, ++ struct spi_transfer *transfer) ++{ ++ struct clk *clk = drv_data->clk; ++ u64 nsec_per_word; ++ u64 bus_ticks; ++ u32 timeout; ++ u32 val; ++ int ret; ++ ++ ret = clk_set_rate(clk, transfer->speed_hz); ++ if (ret) ++ return ret; ++ ++ drv_data->rate = clk_get_rate(clk); ++ ++ /* No need for RX FIFO timeout if we're not receiving anything */ ++ if (!transfer->rx_buf) ++ return 0; ++ ++ /* ++ * Compute the RX FIFO inactivity timeout value that should be used. ++ * The inactivity timer restarts with each word that lands in the ++ * FIFO. If several "word transfer times" pass without any new data ++ * in the RX FIFO, we might as well read what's there. ++ * ++ * The rate at which words land in the FIFO is determined by the ++ * word size and the transfer rate. One bit is transferred per ++ * clock tick, and 8 (or 16 or 32) bits are transferred per word. ++ * ++ * So we can get word transfer time (in nanoseconds) from: ++ * nsec_per_tick = NSEC_PER_SEC / drv_data->rate; ++ * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; ++ * We do the divide last for better accuracy. ++ */ ++ nsec_per_word = NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; ++ nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); ++ ++ /* ++ * The timeout (which we'll set to three word transfer times) is ++ * expressed as a number of APB clock ticks. ++ * bus_ticks = 3 * nsec * (drv_data->bus_rate / NSEC_PER_SEC) ++ */ ++ bus_ticks = 3 * nsec_per_word * drv_data->bus_rate; ++ timeout = DIV_ROUND_UP_ULL(bus_ticks, NSEC_PER_SEC); ++ ++ /* Set the RX timeout period (required for both DMA and PIO) */ ++ val = FIELD_PREP(SSP_TIMEOUT_MASK, timeout); ++ writel(val, drv_data->base + SSP_TIMEOUT); ++ ++ return 0; ++} ++ ++static int k1_spi_transfer_one(struct spi_controller *host, ++ struct spi_device *spi, ++ struct spi_transfer *transfer) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ u32 ctrl; ++ u32 val; ++ int ret; ++ ++ /* Bits per word can change on a per-transfer basis */ ++ drv_data->bytes = spi_bpw_to_bytes(transfer->bits_per_word); ++ ++ /* Each transfer can also specify a different rate */ ++ ret = k1_spi_set_speed(drv_data, transfer); ++ if (ret) { ++ dev_err(&host->dev, ++ "failed to set transfer speed: %d\n", ret); ++ return ret; ++ } ++ ++ drv_data->rx_resid = transfer->len; ++ drv_data->tx_resid = transfer->len; ++ ++ drv_data->transfer = transfer; ++ ++ /* Clear any existing interrupt conditions */ ++ writel(~0, drv_data->base + SSP_STATUS); ++ ++ /* Set the data (word) size, and enable the port */ ++ ctrl = readl(drv_data->base + SSP_TOP_CTRL); ++ ctrl &= ~TOP_DSS_MASK; ++ ctrl |= FIELD_PREP(TOP_DSS_MASK, transfer->bits_per_word - 1); ++ ctrl |= TOP_SSE; ++ writel(ctrl, drv_data->base + SSP_TOP_CTRL); ++ ++ if (spi_xfer_is_dma_mapped(host, spi, transfer)) ++ return k1_spi_dma_one(host, spi, transfer); ++ ++ /* An interrupt will initiate the transfer */ ++ val = SSP_INT_EN_TX | SSP_INT_EN_RX | SSP_INT_EN_ERROR; ++ writel(val, drv_data->base + SSP_INT_EN); ++ ++ return 1; /* We will call spi_finalize_current_transfer() */ ++} ++ ++static void ++k1_spi_handle_err(struct spi_controller *host, struct spi_message *message) ++{ ++ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); ++ ++ if (drv_data->dma_enabled) { ++ dmaengine_terminate_sync(host->dma_rx); ++ dmaengine_terminate_sync(host->dma_tx); ++ } ++} ++ ++static void k1_spi_write_word(struct k1_spi_driver_data *drv_data) ++{ ++ struct spi_transfer *transfer = drv_data->transfer; ++ u32 bytes = drv_data->bytes; ++ u32 val; ++ ++ if (transfer->tx_buf) { ++ const void *buf; ++ ++ buf = transfer->tx_buf + (transfer->len - drv_data->tx_resid); ++ if (bytes == 1) ++ val = *(u8 *)buf; ++ else if (bytes == 2) ++ val = *(u16 *)buf; ++ else /* bytes == 4 */ ++ val = *(u32 *)buf; ++ } else { ++ val = 0; /* Null writer; write 1, 2, or 4 zero bytes */ ++ } ++ /* Fill the next TX FIFO entry */ ++ writel(val, drv_data->base + SSP_DATAR); ++ ++ drv_data->tx_resid -= bytes; ++} ++ ++/* The last-read status value is provided; we know SSP_STATUS_TNF is set */ ++static bool k1_spi_write(struct k1_spi_driver_data *drv_data, u32 val) ++{ ++ unsigned int count; ++ ++ /* Get the number of open slots in the FIFO; zero means all */ ++ count = FIELD_GET(SSP_STATUS_TFL, val) ? : K1_SPI_FIFO_SIZE; ++ ++ /* ++ * Limit how much we try to send at a time, to reduce the ++ * chance the other side can overrun our RX FIFO. ++ */ ++ count = min3(count, K1_SPI_THRESH, drv_data->tx_resid / drv_data->bytes); ++ do ++ k1_spi_write_word(drv_data); ++ while (--count); ++ ++ return !drv_data->tx_resid; ++} ++ ++static void k1_spi_read_word(struct k1_spi_driver_data *drv_data) ++{ ++ struct spi_transfer *transfer = drv_data->transfer; ++ u32 bytes = drv_data->bytes; ++ u32 val; ++ ++ /* Consume the next RX FIFO entry */ ++ val = readl(drv_data->base + SSP_DATAR); ++ if (transfer->rx_buf) { ++ void *buf; ++ ++ buf = transfer->rx_buf + (transfer->len - drv_data->rx_resid); ++ ++ if (bytes == 1) ++ *(u8 *)buf = val; ++ else if (bytes == 2) ++ *(u16 *)buf = val; ++ else /* bytes == 4 */ ++ *(u32 *)buf = val; ++ } /* Otherwise null reader: discard the data */ ++ ++ drv_data->rx_resid -= bytes; ++} ++ ++/* The last-read status value is provided; we know SSP_STATUS_RNE is set */ ++static bool k1_spi_read(struct k1_spi_driver_data *drv_data, u32 val) ++{ ++ do { ++ unsigned int count = FIELD_GET(SSP_STATUS_RFL, val) + 1; ++ ++ /* Only read what we need */ ++ count = min(count, drv_data->rx_resid / drv_data->bytes); ++ do ++ k1_spi_read_word(drv_data); ++ while (--count); ++ ++ /* If there's no more to read, we're done */ ++ if (!drv_data->rx_resid) ++ return true; ++ ++ /* Check again in case more became available to read */ ++ val = readl(drv_data->base + SSP_STATUS); ++ if (val & SSP_STATUS_RNE) ++ writel(SSP_STATUS_RNE, drv_data->base + SSP_STATUS); ++ else ++ return false; ++ } while (true); ++} ++ ++static irqreturn_t k1_spi_ssp_isr(int irq, void *dev_id) ++{ ++ struct k1_spi_driver_data *drv_data = dev_id; ++ u32 status; ++ u32 top_ctrl; ++ ++ /* Get status and clear pending interrupts */ ++ status = readl(drv_data->base + SSP_STATUS); ++ writel(status, drv_data->base + SSP_STATUS); ++ ++ /* If no actionable status bits are set, this is not our interrupt */ ++ if (!(status & (SSP_STATUS_ERROR | SSP_STATUS_TNF | SSP_STATUS_RNE))) ++ return IRQ_NONE; ++ ++ /* Check for any error conditions first */ ++ if (status & SSP_STATUS_ERROR) { ++ if (drv_data->transfer) ++ drv_data->transfer->error |= SPI_TRANS_FAIL_IO; ++ goto done; ++ } ++ ++ /* ++ * For SPI, bytes are transferred in both directions equally, and ++ * RX always follows TX. Start by writing if there is anything to ++ * write, then read. Once there's no more to read, we're done. ++ */ ++ if (drv_data->tx_resid && (status & SSP_STATUS_TNF)) { ++ /* If we finish writing, disable TX interrupts */ ++ if (k1_spi_write(drv_data, status)) ++ writel(SSP_INT_EN_RX | SSP_INT_EN_ERROR, ++ drv_data->base + SSP_INT_EN); ++ } ++ ++ /* We're not done unless we've read all that was requested */ ++ if (drv_data->rx_resid) { ++ /* Read more if the FIFO is not empty */ ++ if (status & SSP_STATUS_RNE) ++ if (k1_spi_read(drv_data, status)) ++ goto done; ++ ++ return IRQ_HANDLED; ++ } ++done: ++ /* Disable the port */ ++ top_ctrl = readl(drv_data->base + SSP_TOP_CTRL); ++ top_ctrl &= ~TOP_SSE; ++ writel(top_ctrl, drv_data->base + SSP_TOP_CTRL); ++ ++ /* Disable all interrupts */ ++ writel(0, drv_data->base + SSP_INT_EN); ++ ++ if (drv_data->transfer) { ++ drv_data->transfer = NULL; ++ spi_finalize_current_transfer(drv_data->host); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int ++k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) ++{ ++ struct spi_controller *host = drv_data->host; ++ struct dma_chan *chan; ++ ++ chan = dma_request_chan(dev, "tx"); ++ if (IS_ERR(chan)) ++ return PTR_ERR(chan); ++ host->dma_tx = chan; ++ ++ chan = dma_request_chan(dev, "rx"); ++ if (IS_ERR(chan)) { ++ dma_release_channel(host->dma_tx); ++ host->dma_tx = NULL; ++ return PTR_ERR(chan); ++ } ++ host->dma_rx = chan; ++ ++ drv_data->dma_enabled = true; ++ ++ return 0; ++} ++ ++static void k1_spi_dma_cleanup(struct device *dev, void *res) ++{ ++ struct k1_spi_driver_data **ptr = res; ++ struct k1_spi_driver_data *drv_data = *ptr; ++ struct spi_controller *host = drv_data->host; ++ ++ if (!drv_data->dma_enabled) ++ return; ++ ++ drv_data->dma_enabled = false; ++ ++ dma_release_channel(host->dma_rx); ++ host->dma_rx = NULL; ++ dma_release_channel(host->dma_tx); ++ host->dma_tx = NULL; ++} ++ ++static int ++devm_k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) ++{ ++ struct k1_spi_driver_data **ptr; ++ int ret; ++ ++ if (!IS_ENABLED(CONFIG_MMP_PDMA)) { ++ dev_info(dev, "DMA not available; using PIO\n"); ++ return 0; ++ } ++ ++ ptr = devres_alloc(k1_spi_dma_cleanup, sizeof(*ptr), GFP_KERNEL); ++ if (!ptr) ++ return -ENOMEM; ++ ++ ret = k1_spi_dma_setup(drv_data, dev); ++ if (ret) { ++ devres_free(ptr); ++ return ret; ++ } ++ ++ *ptr = drv_data; ++ devres_add(dev, ptr); ++ ++ return 0; ++} ++ ++static int k1_spi_probe(struct platform_device *pdev) ++{ ++ struct k1_spi_driver_data *drv_data; ++ struct device *dev = &pdev->dev; ++ struct reset_control *reset; ++ struct spi_controller *host; ++ struct resource *iores; ++ struct clk *clk_bus; ++ int ret; ++ ++ host = devm_spi_alloc_host(dev, sizeof(*drv_data)); ++ if (!host) ++ return -ENOMEM; ++ drv_data = spi_controller_get_devdata(host); ++ drv_data->host = host; ++ platform_set_drvdata(pdev, drv_data); ++ ++ ret = devm_k1_spi_dma_setup(drv_data, dev); ++ if (ret == -EPROBE_DEFER) ++ return ret; ++ if (ret) ++ dev_warn(dev, "DMA setup failed (%d), falling back to PIO\n", ret); ++ ++ drv_data->base = devm_platform_get_and_ioremap_resource(pdev, 0, ++ &iores); ++ if (IS_ERR(drv_data->base)) ++ return dev_err_probe(dev, PTR_ERR(drv_data->base), ++ "error mapping memory\n"); ++ drv_data->base_addr = iores->start; ++ ++ clk_bus = devm_clk_get_enabled(dev, "bus"); ++ if (IS_ERR(clk_bus)) ++ return dev_err_probe(dev, PTR_ERR(clk_bus), ++ "error getting/enabling bus clock\n"); ++ drv_data->bus_rate = clk_get_rate(clk_bus); ++ ++ drv_data->clk = devm_clk_get_enabled(dev, "core"); ++ if (IS_ERR(drv_data->clk)) ++ return dev_err_probe(dev, PTR_ERR(drv_data->clk), ++ "error getting/enabling core clock\n"); ++ ++ reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); ++ if (IS_ERR(reset)) ++ return dev_err_probe(dev, PTR_ERR(reset), ++ "error getting/deasserting reset\n"); ++ ++ k1_spi_register_reset(drv_data, true); ++ ++ drv_data->irq = platform_get_irq(pdev, 0); ++ if (drv_data->irq < 0) ++ return dev_err_probe(dev, drv_data->irq, "error getting IRQ\n"); ++ ++ ret = devm_request_irq(dev, drv_data->irq, k1_spi_ssp_isr, ++ IRQF_SHARED, dev_name(dev), drv_data); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "error requesting IRQ\n"); ++ ++ /* Initialize the host structure, then register it */ ++ host->dev.of_node = dev_of_node(dev); ++ host->dev.parent = dev; ++ host->num_chipselect = 1; ++ if (drv_data->dma_enabled) ++ host->dma_alignment = K1_SPI_DMA_ALIGNMENT; ++ host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; ++ host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); ++ host->min_speed_hz = K1_SPI_MIN_SPEED_HZ; ++ host->max_speed_hz = K1_SPI_MAX_SPEED_HZ; ++ host->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; ++ host->max_dma_len = K1_SPI_MAX_DMA_LEN; ++ ++ host->setup = k1_spi_setup; ++ host->cleanup = k1_spi_cleanup; ++ host->can_dma = k1_spi_can_dma; ++ host->prepare_message = k1_spi_prepare_message; ++ host->set_cs = k1_spi_set_cs; ++ host->transfer_one = k1_spi_transfer_one; ++ host->handle_err = k1_spi_handle_err; ++ ++ ret = devm_spi_register_controller(dev, host); ++ if (ret) ++ dev_err(dev, "error registering controller\n"); ++ ++ return ret; ++} ++ ++static const struct of_device_id k1_spi_dt_ids[] = { ++ { .compatible = "spacemit,k1-spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, k1_spi_dt_ids); ++ ++static struct platform_driver k1_spi_driver = { ++ .probe = k1_spi_probe, ++ .driver = { ++ .name = "k1-spi", ++ .of_match_table = k1_spi_dt_ids, ++ }, ++}; ++module_platform_driver(k1_spi_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K1 SPI controller driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux/0117-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch b/SPECS/linux/0117-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch new file mode 100644 index 0000000000..0ceba63b3b --- /dev/null +++ b/SPECS/linux/0117-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch @@ -0,0 +1,114 @@ +From 433bacac564903a66f585a95f0d7d049c4eb5331 Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Sat, 2 May 2026 21:30:53 -0400 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: define a SPI controller + node + +Define a node for the fourth SoC SPI controller (number 3) on the +SpacemiT K1 SoC. + +Enable it on the Banana Pi BPI-F3 board, which exposes this feature +via its GPIO block: + GPIO PIN 19: MOSI + GPIO PIN 21: MISO + GPIO PIN 23: SCLK + GPIO PIN 24: SS (inverted) + +Define pincontrol configurations for the pins as used on that board. + +(This was tested using a GigaDevice GD25Q64E SPI NOR chip.) + +Reviewed-by: Yixun Lan +Signed-off-by: Alex Elder +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-3-f412e1ae8a34@riscstar.com +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 7 +++++++ + arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 +++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 15 ++++++++++++++ + 3 files changed, 42 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 5790d927b93d..9429189354d6 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -14,6 +14,7 @@ aliases { + ethernet0 = ð0; + ethernet1 = ð1; + serial0 = &uart0; ++ spi3 = &spi3; + i2c2 = &i2c2; + i2c8 = &i2c8; + }; +@@ -335,6 +336,12 @@ &pcie2 { + status = "okay"; + }; + ++&spi3 { ++ pinctrl-0 = <&ssp3_0_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +index b13dcb10f4d6..34d88334e95e 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +@@ -570,4 +570,24 @@ pwm14-1-pins { + drive-strength = <32>; + }; + }; ++ ++ ssp3_0_cfg: ssp3-0-cfg { ++ ssp3-0-pins { ++ pinmux = , /* SCLK */ ++ , /* MOSI */ ++ ; /* MISO */ ++ ++ bias-disable; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ ++ ssp3-0-frm-pins { ++ pinmux = ; /* FRM (frame) */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index f0bad6855c97..f8747190d2e1 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -983,6 +983,21 @@ qspi: spi@d420c000 { + status = "disabled"; + }; + ++ spi3: spi@d401c000 { ++ compatible = "spacemit,k1-spi"; ++ reg = <0x0 0xd401c000 0x0 0x30>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&syscon_apbc CLK_SSP3>, ++ <&syscon_apbc CLK_SSP3_BUS>; ++ clock-names = "core", "bus"; ++ resets = <&syscon_apbc RESET_SSP3>; ++ interrupts = <55>; ++ dmas = <&pdma 20>, <&pdma 19>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ + /* sec_uart1: 0xf0612000, not available from Linux */ + }; + +-- +2.53.0 + diff --git a/SPECS/linux/0117-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch b/SPECS/linux/0117-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch deleted file mode 100644 index 2ff18ca4cc..0000000000 --- a/SPECS/linux/0117-FROMLIST-spi-spacemit-introduce-SpacemiT-K1-SPI-cont.patch +++ /dev/null @@ -1,852 +0,0 @@ -From d5fd2de289d1bf633ef2fbabb3f87eba7354c647 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Sat, 2 May 2026 21:30:52 -0400 -Subject: [PATCH 117/269] FROMLIST: spi: spacemit: introduce SpacemiT K1 SPI - controller driver - -This patch introduces the driver for the SPI controller found in the -SpacemiT K1 SoC. Currently the driver supports master mode only. -The SPI hardware implements RX and TX FIFOs, 32 entries each, and -supports both PIO and DMA mode transfers. - -Signed-off-by: Alex Elder -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-2-f412e1ae8a34@riscstar.com -Signed-off-by: Han Gao ---- - drivers/spi/Kconfig | 9 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-spacemit-k1.c | 789 ++++++++++++++++++++++++++++++++++ - 3 files changed, 799 insertions(+) - create mode 100644 drivers/spi/spi-spacemit-k1.c - -diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig -index c3b2f02f5912..b50d9ae1a498 100644 ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -1085,6 +1085,15 @@ config SPI_SG2044_NOR - also supporting 3Byte address devices and 4Byte address - devices. - -+config SPI_SPACEMIT_K1 -+ tristate "K1 SPI Controller" -+ depends on ARCH_SPACEMIT || COMPILE_TEST -+ depends on OF -+ imply MMP_PDMA if ARCH_SPACEMIT -+ default m if ARCH_SPACEMIT -+ help -+ Enable support for the SpacemiT K1 SPI controller. -+ - config SPI_SPRD - tristate "Spreadtrum SPI controller" - depends on ARCH_SPRD || COMPILE_TEST -diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile -index 9d36190a9884..9fa12498ce8c 100644 ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -143,6 +143,7 @@ obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o - obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o - obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o - obj-$(CONFIG_SPI_SG2044_NOR) += spi-sg2044-nor.o -+obj-$(CONFIG_SPI_SPACEMIT_K1) += spi-spacemit-k1.o - obj-$(CONFIG_SPI_SPRD) += spi-sprd.o - obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o - obj-$(CONFIG_SPI_STM32) += spi-stm32.o -diff --git a/drivers/spi/spi-spacemit-k1.c b/drivers/spi/spi-spacemit-k1.c -new file mode 100644 -index 000000000000..99db429db0b2 ---- /dev/null -+++ b/drivers/spi/spi-spacemit-k1.c -@@ -0,0 +1,789 @@ -+// SPDX-License-Identifier: GPL-2.0 -+// -+// SpacemiT K1 SPI controller driver -+// -+// Copyright (C) 2026, RISCstar Solutions Corporation -+// Copyright (C) 2023, SpacemiT Corporation -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "internals.h" -+ -+/* This is the range of transfer rates supported by the K1 SoC */ -+#define K1_SPI_MIN_SPEED_HZ 6250 -+#define K1_SPI_MAX_SPEED_HZ 51200000 -+ -+/* DMA constraints */ -+#define K1_SPI_DMA_ALIGNMENT 64 -+#define K1_SPI_MAX_DMA_LEN SZ_512K -+ -+/* SSP Top Control Register */ -+#define SSP_TOP_CTRL 0x00 -+#define TOP_SSE BIT(0) /* Enable port */ -+#define TOP_FRF_MASK GENMASK(2, 1) /* Frame format */ -+#define TOP_FRF_MOTOROLA 0 /* Motorola SPI */ -+#define TOP_DSS_MASK GENMASK(9, 5) /* Data size (1-32) */ -+#define TOP_SPO BIT(10) /* Polarity: 0=low */ -+#define TOP_SPH BIT(11) /* Half-cycle phase */ -+#define TOP_LBM BIT(12) /* Loopback mode */ -+#define TOP_TRAIL BIT(13) /* Trailing bytes */ -+#define TOP_HOLD_FRAME_LOW BIT(14) /* Chip select */ -+ -+/* SSP FIFO Control Register */ -+#define SSP_FIFO_CTRL 0x04 -+#define FIFO_TFT_MASK GENMASK(4, 0) /* TX FIFO threshold */ -+#define FIFO_RFT_MASK GENMASK(9, 5) /* RX FIFO threshold */ -+#define FIFO_TSRE BIT(10) /* TX service request */ -+#define FIFO_RSRE BIT(11) /* RX service request */ -+ -+/* SSP Interrupt Enable Register */ -+#define SSP_INT_EN 0x08 -+#define SSP_INT_EN_TINTE BIT(1) /* RX timeout */ -+#define SSP_INT_EN_RIE BIT(2) /* RX FIFO */ -+#define SSP_INT_EN_TIE BIT(3) /* TX FIFO */ -+#define SSP_INT_EN_RIM BIT(4) /* RX FIFO overrun */ -+#define SSP_INT_EN_TIM BIT(5) /* TX FIFO underrun */ -+#define SSP_INT_EN_EBCEI BIT(6) /* Bit count error */ -+ -+/* TX interrupts, RX interrupts, and error interrupts */ -+#define SSP_INT_EN_TX SSP_INT_EN_TIE -+#define SSP_INT_EN_RX \ -+ (SSP_INT_EN_TINTE | SSP_INT_EN_RIE) -+#define SSP_INT_EN_ERROR \ -+ (SSP_INT_EN_RIM | SSP_INT_EN_TIM | SSP_INT_EN_EBCEI) -+ -+/* SSP Time Out Register */ -+#define SSP_TIMEOUT 0x0c -+#define SSP_TIMEOUT_MASK GENMASK(23, 0) -+ -+/* SSP Data Register */ -+#define SSP_DATAR 0x10 -+ -+/* SSP Status Register */ -+#define SSP_STATUS 0x14 -+#define SSP_STATUS_BSY BIT(0) /* SPI/I2S busy */ -+#define SSP_STATUS_TNF BIT(6) /* TX FIFO not full */ -+#define SSP_STATUS_TFL GENMASK(11, 7) /* TX FIFO level */ -+#define SSP_STATUS_TUR BIT(12) /* TX FIFO underrun */ -+#define SSP_STATUS_RNE BIT(14) /* RX FIFO not empty */ -+#define SSP_STATUS_RFL GENMASK(19, 15) /* RX FIFO level */ -+#define SSP_STATUS_ROR BIT(20) /* RX FIFO overrun */ -+#define SSP_STATUS_BCE BIT(21) /* Bit count error */ -+ -+/* Error status mask */ -+#define SSP_STATUS_ERROR \ -+ (SSP_STATUS_TUR | SSP_STATUS_ROR | SSP_STATUS_BCE) -+ -+/* The FIFO sizes and thresholds are the same for RX and TX */ -+#define K1_SPI_FIFO_SIZE 32 -+#define K1_SPI_THRESH (K1_SPI_FIFO_SIZE / 2) -+ -+struct k1_spi_driver_data { -+ struct spi_controller *host; -+ void __iomem *base; -+ phys_addr_t base_addr; -+ unsigned long bus_rate; -+ struct clk *clk; -+ unsigned long rate; -+ int irq; -+ -+ /* Current transfer information; not valid if message is null */ -+ u32 bytes; /* Bytes used for bits_per_word */ -+ unsigned int rx_resid; /* RX bytes left in transfer */ -+ unsigned int tx_resid; /* TX bytes left in transfer */ -+ struct spi_transfer *transfer; /* Current transfer */ -+ -+ bool dma_enabled; -+}; -+ -+/* Set our registers to a known initial state */ -+static void -+k1_spi_register_reset(struct k1_spi_driver_data *drv_data, bool initial) -+{ -+ u32 val = 0; -+ -+ writel(0, drv_data->base + SSP_TOP_CTRL); -+ -+ if (initial) { -+ /* -+ * The TX and RX FIFO thresholds are the same no matter -+ * what the speed or bits per word, so we can just set -+ * them once. The thresholds are one more than the values -+ * in the register. -+ */ -+ val = FIELD_PREP(FIFO_RFT_MASK, K1_SPI_THRESH - 1); -+ val |= FIELD_PREP(FIFO_TFT_MASK, K1_SPI_THRESH - 1); -+ } -+ writel(val, drv_data->base + SSP_FIFO_CTRL); -+ -+ writel(0, drv_data->base + SSP_INT_EN); -+ writel(0, drv_data->base + SSP_TIMEOUT); -+ -+ /* Clear any pending interrupt conditions */ -+ writel(~0, drv_data->base + SSP_STATUS); -+} -+ -+/* -+ * The client can call the setup function multiple times, and each call -+ * can specify a different SPI mode (and transfer speed). Each transfer -+ * can specify its own speed though, and the core code ensures each -+ * transfer's speed is set to something nonzero and supported by both -+ * the controller and the device. We just set the speed for each transfer. -+ */ -+static int k1_spi_setup(struct spi_device *spi) -+{ -+ struct k1_spi_driver_data *drv_data; -+ u32 val; -+ -+ drv_data = spi_controller_get_devdata(spi->controller); -+ -+ /* -+ * Configure the message format for this device. We only -+ * support Motorola SPI format in master mode. -+ */ -+ val = FIELD_PREP(TOP_FRF_MASK, TOP_FRF_MOTOROLA); -+ -+ /* Translate the mode into the value used to program the hardware. */ -+ if (spi->mode & SPI_CPHA) -+ val |= TOP_SPH; /* 1/2 cycle */ -+ if (spi->mode & SPI_CPOL) -+ val |= TOP_SPO; /* active low */ -+ if (spi->mode & SPI_LOOP) -+ val |= TOP_LBM; /* enable loopback */ -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+ -+ return 0; -+} -+ -+static void k1_spi_cleanup(struct spi_device *spi) -+{ -+ struct k1_spi_driver_data *drv_data; -+ -+ drv_data = spi_controller_get_devdata(spi->controller); -+ k1_spi_register_reset(drv_data, false); -+} -+ -+static bool k1_spi_can_dma(struct spi_controller *host, struct spi_device *spi, -+ struct spi_transfer *transfer) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ u32 burst_size; -+ -+ if (!drv_data->dma_enabled) -+ return false; -+ -+ if (transfer->len > SZ_2K) -+ return false; -+ -+ /* Don't bother with DMA if we can't do even a single burst */ -+ burst_size = K1_SPI_THRESH * spi_bpw_to_bytes(transfer->bits_per_word); -+ -+ return transfer->len >= burst_size; -+} -+ -+static void k1_spi_dma_callback(void *param) -+{ -+ struct k1_spi_driver_data *drv_data = param; -+ u32 val; -+ -+ val = readl(drv_data->base + SSP_FIFO_CTRL); -+ val &= ~(FIFO_TSRE | FIFO_RSRE); -+ writel(val, drv_data->base + SSP_FIFO_CTRL); -+ -+ val = readl(drv_data->base + SSP_TOP_CTRL); -+ val &= ~TOP_TRAIL; -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+ -+ /* Check for any error conditions */ -+ val = readl(drv_data->base + SSP_STATUS); -+ if (val & SSP_STATUS_ERROR) -+ drv_data->transfer->error |= SPI_TRANS_FAIL_IO; -+ -+ /* Disable the port */ -+ val = readl(drv_data->base + SSP_TOP_CTRL); -+ val &= ~TOP_SSE; -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+ -+ drv_data->transfer = NULL; -+ -+ spi_finalize_current_transfer(drv_data->host); -+} -+ -+/* Prepare a descriptor for TX or RX DMA */ -+static struct dma_async_tx_descriptor * -+k1_spi_dma_prep(struct k1_spi_driver_data *drv_data, -+ struct spi_transfer *transfer, bool tx) -+{ -+ phys_addr_t addr = drv_data->base_addr + SSP_DATAR; -+ u32 burst_size = K1_SPI_THRESH * drv_data->bytes; -+ struct dma_slave_config cfg = { }; -+ enum dma_transfer_direction dir; -+ enum dma_slave_buswidth width; -+ struct dma_chan *chan; -+ struct sg_table *sgt; -+ -+ switch (drv_data->bytes) { -+ case 1: -+ width = DMA_SLAVE_BUSWIDTH_1_BYTE; -+ break; -+ case 2: -+ width = DMA_SLAVE_BUSWIDTH_2_BYTES; -+ break; -+ default: /* bytes == 4 */ -+ width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ break; -+ } -+ -+ if (tx) { -+ chan = drv_data->host->dma_tx; -+ sgt = &transfer->tx_sg; -+ dir = DMA_MEM_TO_DEV; -+ -+ cfg.dst_addr = addr; -+ cfg.dst_addr_width = width; -+ cfg.dst_maxburst = burst_size; -+ } else { -+ chan = drv_data->host->dma_rx; -+ sgt = &transfer->rx_sg; -+ dir = DMA_DEV_TO_MEM; -+ -+ cfg.src_addr = addr; -+ cfg.src_addr_width = width; -+ cfg.src_maxburst = burst_size; -+ } -+ cfg.direction = dir; -+ -+ if (dmaengine_slave_config(chan, &cfg)) -+ return NULL; -+ -+ return dmaengine_prep_slave_sg(chan, sgt->sgl, sgt->nents, dir, -+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); -+ -+} -+ -+static int k1_spi_dma_one(struct spi_controller *host, struct spi_device *spi, -+ struct spi_transfer *transfer) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ struct dma_async_tx_descriptor *desc; -+ u32 val; -+ -+ /* Prepare the TX descriptor and submit it */ -+ desc = k1_spi_dma_prep(drv_data, transfer, true); -+ if (!desc) -+ goto fallback; -+ dmaengine_submit(desc); -+ -+ /* Prepare the RX descriptor and submit it */ -+ desc = k1_spi_dma_prep(drv_data, transfer, false); -+ if (!desc) -+ goto fallback; -+ -+ /* When RX is complete we also know TX has completed */ -+ desc->callback = k1_spi_dma_callback; -+ desc->callback_param = drv_data; -+ -+ dmaengine_submit(desc); -+ -+ val = readl(drv_data->base + SSP_TOP_CTRL); -+ val |= TOP_TRAIL; /* Trailing bytes handled by DMA */ -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+ -+ val = readl(drv_data->base + SSP_FIFO_CTRL); -+ val |= FIFO_TSRE | FIFO_RSRE; -+ writel(val, drv_data->base + SSP_FIFO_CTRL); -+ -+ /* Start RX first so we're ready the instant we start transmitting */ -+ dma_async_issue_pending(host->dma_rx); -+ dma_async_issue_pending(host->dma_tx); -+ -+ return 1; -+fallback: -+ transfer->error |= SPI_TRANS_FAIL_NO_START; -+ -+ return -EAGAIN; -+} -+ -+/* Flush the RX FIFO of any leftover data before processing a message */ -+static int k1_spi_prepare_message(struct spi_controller *host, -+ struct spi_message *message) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ u32 val = readl(drv_data->base + SSP_STATUS); -+ u32 count; -+ -+ /* If there's nothing in the FIFO, we're done */ -+ if (!(val & SSP_STATUS_RNE)) -+ return 0; -+ -+ /* Read and discard what's there (one more than what the field says) */ -+ count = FIELD_GET(SSP_STATUS_RFL, val) + 1; -+ do -+ (void)readl(drv_data->base + SSP_DATAR); -+ while (--count); -+ -+ return 0; -+} -+ -+/* Set logic level of chip select line (high=true means CS deasserted) */ -+static void k1_spi_set_cs(struct spi_device *spi, bool high) -+{ -+ struct k1_spi_driver_data *drv_data; -+ u32 val; -+ -+ drv_data = spi_controller_get_devdata(spi->controller); -+ -+ val = readl(drv_data->base + SSP_TOP_CTRL); -+ if (high) -+ val &= ~TOP_HOLD_FRAME_LOW; -+ else -+ val |= TOP_HOLD_FRAME_LOW; -+ writel(val, drv_data->base + SSP_TOP_CTRL); -+} -+ -+/* Set the transfer speed; the SPI core code ensures it is supported */ -+static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, -+ struct spi_transfer *transfer) -+{ -+ struct clk *clk = drv_data->clk; -+ u64 nsec_per_word; -+ u64 bus_ticks; -+ u32 timeout; -+ u32 val; -+ int ret; -+ -+ ret = clk_set_rate(clk, transfer->speed_hz); -+ if (ret) -+ return ret; -+ -+ drv_data->rate = clk_get_rate(clk); -+ -+ /* No need for RX FIFO timeout if we're not receiving anything */ -+ if (!transfer->rx_buf) -+ return 0; -+ -+ /* -+ * Compute the RX FIFO inactivity timeout value that should be used. -+ * The inactivity timer restarts with each word that lands in the -+ * FIFO. If several "word transfer times" pass without any new data -+ * in the RX FIFO, we might as well read what's there. -+ * -+ * The rate at which words land in the FIFO is determined by the -+ * word size and the transfer rate. One bit is transferred per -+ * clock tick, and 8 (or 16 or 32) bits are transferred per word. -+ * -+ * So we can get word transfer time (in nanoseconds) from: -+ * nsec_per_tick = NSEC_PER_SEC / drv_data->rate; -+ * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; -+ * We do the divide last for better accuracy. -+ */ -+ nsec_per_word = NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; -+ nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); -+ -+ /* -+ * The timeout (which we'll set to three word transfer times) is -+ * expressed as a number of APB clock ticks. -+ * bus_ticks = 3 * nsec * (drv_data->bus_rate / NSEC_PER_SEC) -+ */ -+ bus_ticks = 3 * nsec_per_word * drv_data->bus_rate; -+ timeout = DIV_ROUND_UP_ULL(bus_ticks, NSEC_PER_SEC); -+ -+ /* Set the RX timeout period (required for both DMA and PIO) */ -+ val = FIELD_PREP(SSP_TIMEOUT_MASK, timeout); -+ writel(val, drv_data->base + SSP_TIMEOUT); -+ -+ return 0; -+} -+ -+static int k1_spi_transfer_one(struct spi_controller *host, -+ struct spi_device *spi, -+ struct spi_transfer *transfer) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ u32 ctrl; -+ u32 val; -+ int ret; -+ -+ /* Bits per word can change on a per-transfer basis */ -+ drv_data->bytes = spi_bpw_to_bytes(transfer->bits_per_word); -+ -+ /* Each transfer can also specify a different rate */ -+ ret = k1_spi_set_speed(drv_data, transfer); -+ if (ret) { -+ dev_err(&host->dev, -+ "failed to set transfer speed: %d\n", ret); -+ return ret; -+ } -+ -+ drv_data->rx_resid = transfer->len; -+ drv_data->tx_resid = transfer->len; -+ -+ drv_data->transfer = transfer; -+ -+ /* Clear any existing interrupt conditions */ -+ writel(~0, drv_data->base + SSP_STATUS); -+ -+ /* Set the data (word) size, and enable the port */ -+ ctrl = readl(drv_data->base + SSP_TOP_CTRL); -+ ctrl &= ~TOP_DSS_MASK; -+ ctrl |= FIELD_PREP(TOP_DSS_MASK, transfer->bits_per_word - 1); -+ ctrl |= TOP_SSE; -+ writel(ctrl, drv_data->base + SSP_TOP_CTRL); -+ -+ if (spi_xfer_is_dma_mapped(host, spi, transfer)) -+ return k1_spi_dma_one(host, spi, transfer); -+ -+ /* An interrupt will initiate the transfer */ -+ val = SSP_INT_EN_TX | SSP_INT_EN_RX | SSP_INT_EN_ERROR; -+ writel(val, drv_data->base + SSP_INT_EN); -+ -+ return 1; /* We will call spi_finalize_current_transfer() */ -+} -+ -+static void -+k1_spi_handle_err(struct spi_controller *host, struct spi_message *message) -+{ -+ struct k1_spi_driver_data *drv_data = spi_controller_get_devdata(host); -+ -+ if (drv_data->dma_enabled) { -+ dmaengine_terminate_sync(host->dma_rx); -+ dmaengine_terminate_sync(host->dma_tx); -+ } -+} -+ -+static void k1_spi_write_word(struct k1_spi_driver_data *drv_data) -+{ -+ struct spi_transfer *transfer = drv_data->transfer; -+ u32 bytes = drv_data->bytes; -+ u32 val; -+ -+ if (transfer->tx_buf) { -+ const void *buf; -+ -+ buf = transfer->tx_buf + (transfer->len - drv_data->tx_resid); -+ if (bytes == 1) -+ val = *(u8 *)buf; -+ else if (bytes == 2) -+ val = *(u16 *)buf; -+ else /* bytes == 4 */ -+ val = *(u32 *)buf; -+ } else { -+ val = 0; /* Null writer; write 1, 2, or 4 zero bytes */ -+ } -+ /* Fill the next TX FIFO entry */ -+ writel(val, drv_data->base + SSP_DATAR); -+ -+ drv_data->tx_resid -= bytes; -+} -+ -+/* The last-read status value is provided; we know SSP_STATUS_TNF is set */ -+static bool k1_spi_write(struct k1_spi_driver_data *drv_data, u32 val) -+{ -+ unsigned int count; -+ -+ /* Get the number of open slots in the FIFO; zero means all */ -+ count = FIELD_GET(SSP_STATUS_TFL, val) ? : K1_SPI_FIFO_SIZE; -+ -+ /* -+ * Limit how much we try to send at a time, to reduce the -+ * chance the other side can overrun our RX FIFO. -+ */ -+ count = min3(count, K1_SPI_THRESH, drv_data->tx_resid / drv_data->bytes); -+ do -+ k1_spi_write_word(drv_data); -+ while (--count); -+ -+ return !drv_data->tx_resid; -+} -+ -+static void k1_spi_read_word(struct k1_spi_driver_data *drv_data) -+{ -+ struct spi_transfer *transfer = drv_data->transfer; -+ u32 bytes = drv_data->bytes; -+ u32 val; -+ -+ /* Consume the next RX FIFO entry */ -+ val = readl(drv_data->base + SSP_DATAR); -+ if (transfer->rx_buf) { -+ void *buf; -+ -+ buf = transfer->rx_buf + (transfer->len - drv_data->rx_resid); -+ -+ if (bytes == 1) -+ *(u8 *)buf = val; -+ else if (bytes == 2) -+ *(u16 *)buf = val; -+ else /* bytes == 4 */ -+ *(u32 *)buf = val; -+ } /* Otherwise null reader: discard the data */ -+ -+ drv_data->rx_resid -= bytes; -+} -+ -+/* The last-read status value is provided; we know SSP_STATUS_RNE is set */ -+static bool k1_spi_read(struct k1_spi_driver_data *drv_data, u32 val) -+{ -+ do { -+ unsigned int count = FIELD_GET(SSP_STATUS_RFL, val) + 1; -+ -+ /* Only read what we need */ -+ count = min(count, drv_data->rx_resid / drv_data->bytes); -+ do -+ k1_spi_read_word(drv_data); -+ while (--count); -+ -+ /* If there's no more to read, we're done */ -+ if (!drv_data->rx_resid) -+ return true; -+ -+ /* Check again in case more became available to read */ -+ val = readl(drv_data->base + SSP_STATUS); -+ if (val & SSP_STATUS_RNE) -+ writel(SSP_STATUS_RNE, drv_data->base + SSP_STATUS); -+ else -+ return false; -+ } while (true); -+} -+ -+static irqreturn_t k1_spi_ssp_isr(int irq, void *dev_id) -+{ -+ struct k1_spi_driver_data *drv_data = dev_id; -+ u32 status; -+ u32 top_ctrl; -+ -+ /* Get status and clear pending interrupts */ -+ status = readl(drv_data->base + SSP_STATUS); -+ writel(status, drv_data->base + SSP_STATUS); -+ -+ /* If no actionable status bits are set, this is not our interrupt */ -+ if (!(status & (SSP_STATUS_ERROR | SSP_STATUS_TNF | SSP_STATUS_RNE))) -+ return IRQ_NONE; -+ -+ /* Check for any error conditions first */ -+ if (status & SSP_STATUS_ERROR) { -+ if (drv_data->transfer) -+ drv_data->transfer->error |= SPI_TRANS_FAIL_IO; -+ goto done; -+ } -+ -+ /* -+ * For SPI, bytes are transferred in both directions equally, and -+ * RX always follows TX. Start by writing if there is anything to -+ * write, then read. Once there's no more to read, we're done. -+ */ -+ if (drv_data->tx_resid && (status & SSP_STATUS_TNF)) { -+ /* If we finish writing, disable TX interrupts */ -+ if (k1_spi_write(drv_data, status)) -+ writel(SSP_INT_EN_RX | SSP_INT_EN_ERROR, -+ drv_data->base + SSP_INT_EN); -+ } -+ -+ /* We're not done unless we've read all that was requested */ -+ if (drv_data->rx_resid) { -+ /* Read more if the FIFO is not empty */ -+ if (status & SSP_STATUS_RNE) -+ if (k1_spi_read(drv_data, status)) -+ goto done; -+ -+ return IRQ_HANDLED; -+ } -+done: -+ /* Disable the port */ -+ top_ctrl = readl(drv_data->base + SSP_TOP_CTRL); -+ top_ctrl &= ~TOP_SSE; -+ writel(top_ctrl, drv_data->base + SSP_TOP_CTRL); -+ -+ /* Disable all interrupts */ -+ writel(0, drv_data->base + SSP_INT_EN); -+ -+ if (drv_data->transfer) { -+ drv_data->transfer = NULL; -+ spi_finalize_current_transfer(drv_data->host); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int -+k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) -+{ -+ struct spi_controller *host = drv_data->host; -+ struct dma_chan *chan; -+ -+ chan = dma_request_chan(dev, "tx"); -+ if (IS_ERR(chan)) -+ return PTR_ERR(chan); -+ host->dma_tx = chan; -+ -+ chan = dma_request_chan(dev, "rx"); -+ if (IS_ERR(chan)) { -+ dma_release_channel(host->dma_tx); -+ host->dma_tx = NULL; -+ return PTR_ERR(chan); -+ } -+ host->dma_rx = chan; -+ -+ drv_data->dma_enabled = true; -+ -+ return 0; -+} -+ -+static void k1_spi_dma_cleanup(struct device *dev, void *res) -+{ -+ struct k1_spi_driver_data **ptr = res; -+ struct k1_spi_driver_data *drv_data = *ptr; -+ struct spi_controller *host = drv_data->host; -+ -+ if (!drv_data->dma_enabled) -+ return; -+ -+ drv_data->dma_enabled = false; -+ -+ dma_release_channel(host->dma_rx); -+ host->dma_rx = NULL; -+ dma_release_channel(host->dma_tx); -+ host->dma_tx = NULL; -+} -+ -+static int -+devm_k1_spi_dma_setup(struct k1_spi_driver_data *drv_data, struct device *dev) -+{ -+ struct k1_spi_driver_data **ptr; -+ int ret; -+ -+ if (!IS_ENABLED(CONFIG_MMP_PDMA)) { -+ dev_info(dev, "DMA not available; using PIO\n"); -+ return 0; -+ } -+ -+ ptr = devres_alloc(k1_spi_dma_cleanup, sizeof(*ptr), GFP_KERNEL); -+ if (!ptr) -+ return -ENOMEM; -+ -+ ret = k1_spi_dma_setup(drv_data, dev); -+ if (ret) { -+ devres_free(ptr); -+ return ret; -+ } -+ -+ *ptr = drv_data; -+ devres_add(dev, ptr); -+ -+ return 0; -+} -+ -+static int k1_spi_probe(struct platform_device *pdev) -+{ -+ struct k1_spi_driver_data *drv_data; -+ struct device *dev = &pdev->dev; -+ struct reset_control *reset; -+ struct spi_controller *host; -+ struct resource *iores; -+ struct clk *clk_bus; -+ int ret; -+ -+ host = devm_spi_alloc_host(dev, sizeof(*drv_data)); -+ if (!host) -+ return -ENOMEM; -+ drv_data = spi_controller_get_devdata(host); -+ drv_data->host = host; -+ platform_set_drvdata(pdev, drv_data); -+ -+ ret = devm_k1_spi_dma_setup(drv_data, dev); -+ if (ret == -EPROBE_DEFER) -+ return ret; -+ if (ret) -+ dev_warn(dev, "DMA setup failed (%d), falling back to PIO\n", ret); -+ -+ drv_data->base = devm_platform_get_and_ioremap_resource(pdev, 0, -+ &iores); -+ if (IS_ERR(drv_data->base)) -+ return dev_err_probe(dev, PTR_ERR(drv_data->base), -+ "error mapping memory\n"); -+ drv_data->base_addr = iores->start; -+ -+ clk_bus = devm_clk_get_enabled(dev, "bus"); -+ if (IS_ERR(clk_bus)) -+ return dev_err_probe(dev, PTR_ERR(clk_bus), -+ "error getting/enabling bus clock\n"); -+ drv_data->bus_rate = clk_get_rate(clk_bus); -+ -+ drv_data->clk = devm_clk_get_enabled(dev, "core"); -+ if (IS_ERR(drv_data->clk)) -+ return dev_err_probe(dev, PTR_ERR(drv_data->clk), -+ "error getting/enabling core clock\n"); -+ -+ reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); -+ if (IS_ERR(reset)) -+ return dev_err_probe(dev, PTR_ERR(reset), -+ "error getting/deasserting reset\n"); -+ -+ k1_spi_register_reset(drv_data, true); -+ -+ drv_data->irq = platform_get_irq(pdev, 0); -+ if (drv_data->irq < 0) -+ return dev_err_probe(dev, drv_data->irq, "error getting IRQ\n"); -+ -+ ret = devm_request_irq(dev, drv_data->irq, k1_spi_ssp_isr, -+ IRQF_SHARED, dev_name(dev), drv_data); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "error requesting IRQ\n"); -+ -+ /* Initialize the host structure, then register it */ -+ host->dev.of_node = dev_of_node(dev); -+ host->dev.parent = dev; -+ host->num_chipselect = 1; -+ if (drv_data->dma_enabled) -+ host->dma_alignment = K1_SPI_DMA_ALIGNMENT; -+ host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; -+ host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); -+ host->min_speed_hz = K1_SPI_MIN_SPEED_HZ; -+ host->max_speed_hz = K1_SPI_MAX_SPEED_HZ; -+ host->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; -+ host->max_dma_len = K1_SPI_MAX_DMA_LEN; -+ -+ host->setup = k1_spi_setup; -+ host->cleanup = k1_spi_cleanup; -+ host->can_dma = k1_spi_can_dma; -+ host->prepare_message = k1_spi_prepare_message; -+ host->set_cs = k1_spi_set_cs; -+ host->transfer_one = k1_spi_transfer_one; -+ host->handle_err = k1_spi_handle_err; -+ -+ ret = devm_spi_register_controller(dev, host); -+ if (ret) -+ dev_err(dev, "error registering controller\n"); -+ -+ return ret; -+} -+ -+static const struct of_device_id k1_spi_dt_ids[] = { -+ { .compatible = "spacemit,k1-spi", }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, k1_spi_dt_ids); -+ -+static struct platform_driver k1_spi_driver = { -+ .probe = k1_spi_probe, -+ .driver = { -+ .name = "k1-spi", -+ .of_match_table = k1_spi_dt_ids, -+ }, -+}; -+module_platform_driver(k1_spi_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K1 SPI controller driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux/0118-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch b/SPECS/linux/0118-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch new file mode 100644 index 0000000000..660d7d81de --- /dev/null +++ b/SPECS/linux/0118-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch @@ -0,0 +1,104 @@ +From cade37fccf4287ccd5b5b76d84fa6f23e88e32b2 Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Mon, 27 Apr 2026 15:15:15 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: thermal: Add SpacemiT K1 thermal + sensor + +Document the SpacemiT K1 Thermal Sensor, which supports +monitoring temperatures for five zones: soc, package, gpu, cluster0, +and cluster1. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Shuwei Wu +Link: https://lore.kernel.org/r/20260427-k1-thermal-v5-1-df39187480ed@mailbox.org +Signed-off-by: Han Gao +--- + .../bindings/thermal/spacemit,k1-tsensor.yaml | 76 +++++++++++++++++++ + 1 file changed, 76 insertions(+) + create mode 100644 Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml + +diff --git a/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml +new file mode 100644 +index 000000000000..6dad76a7dd36 +--- /dev/null ++++ b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml +@@ -0,0 +1,76 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/thermal/spacemit,k1-tsensor.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K1 Thermal Sensor ++ ++description: ++ The SpacemiT K1 Thermal Sensor monitors the temperature of the SoC ++ using multiple internal sensors (e.g., soc, package, gpu, clusters). ++ ++maintainers: ++ - Shuwei Wu ++ ++$ref: thermal-sensor.yaml# ++ ++properties: ++ compatible: ++ const: spacemit,k1-tsensor ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Core clock for thermal sensor ++ - description: Bus clock for thermal sensor ++ ++ clock-names: ++ items: ++ - const: core ++ - const: bus ++ ++ interrupts: ++ maxItems: 1 ++ ++ resets: ++ items: ++ - description: Reset for the thermal sensor ++ ++ "#thermal-sensor-cells": ++ const: 1 ++ description: ++ The first cell indicates the sensor ID. ++ 0 = soc ++ 1 = package ++ 2 = gpu ++ 3 = cluster0 ++ 4 = cluster1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - interrupts ++ - resets ++ - "#thermal-sensor-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ ++ thermal@d4018000 { ++ compatible = "spacemit,k1-tsensor"; ++ reg = <0xd4018000 0x100>; ++ clocks = <&syscon_apbc CLK_TSEN>, ++ <&syscon_apbc CLK_TSEN_BUS>; ++ clock-names = "core", "bus"; ++ interrupts = <61>; ++ resets = <&syscon_apbc RESET_TSEN>; ++ #thermal-sensor-cells = <1>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux/0118-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch b/SPECS/linux/0118-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch deleted file mode 100644 index e8d49f2ca8..0000000000 --- a/SPECS/linux/0118-FROMLIST-riscv-dts-spacemit-define-a-SPI-controller-.patch +++ /dev/null @@ -1,114 +0,0 @@ -From 3802a494e2d8776f95e83f6e5c837a0874c253b2 Mon Sep 17 00:00:00 2001 -From: Alex Elder -Date: Sat, 2 May 2026 21:30:53 -0400 -Subject: [PATCH 118/269] FROMLIST: riscv: dts: spacemit: define a SPI - controller node - -Define a node for the fourth SoC SPI controller (number 3) on the -SpacemiT K1 SoC. - -Enable it on the Banana Pi BPI-F3 board, which exposes this feature -via its GPIO block: - GPIO PIN 19: MOSI - GPIO PIN 21: MISO - GPIO PIN 23: SCLK - GPIO PIN 24: SS (inverted) - -Define pincontrol configurations for the pins as used on that board. - -(This was tested using a GigaDevice GD25Q64E SPI NOR chip.) - -Reviewed-by: Yixun Lan -Signed-off-by: Alex Elder -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260502-spi-spacemit-k1-v10-3-f412e1ae8a34@riscstar.com -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 7 +++++++ - arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 20 +++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k1.dtsi | 15 ++++++++++++++ - 3 files changed, 42 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 5790d927b93d..9429189354d6 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -14,6 +14,7 @@ aliases { - ethernet0 = ð0; - ethernet1 = ð1; - serial0 = &uart0; -+ spi3 = &spi3; - i2c2 = &i2c2; - i2c8 = &i2c8; - }; -@@ -335,6 +336,12 @@ &pcie2 { - status = "okay"; - }; - -+&spi3 { -+ pinctrl-0 = <&ssp3_0_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -index b13dcb10f4d6..34d88334e95e 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -@@ -570,4 +570,24 @@ pwm14-1-pins { - drive-strength = <32>; - }; - }; -+ -+ ssp3_0_cfg: ssp3-0-cfg { -+ ssp3-0-pins { -+ pinmux = , /* SCLK */ -+ , /* MOSI */ -+ ; /* MISO */ -+ -+ bias-disable; -+ drive-strength = <19>; -+ power-source = <3300>; -+ }; -+ -+ ssp3-0-frm-pins { -+ pinmux = ; /* FRM (frame) */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <19>; -+ power-source = <3300>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index f0bad6855c97..f8747190d2e1 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -983,6 +983,21 @@ qspi: spi@d420c000 { - status = "disabled"; - }; - -+ spi3: spi@d401c000 { -+ compatible = "spacemit,k1-spi"; -+ reg = <0x0 0xd401c000 0x0 0x30>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&syscon_apbc CLK_SSP3>, -+ <&syscon_apbc CLK_SSP3_BUS>; -+ clock-names = "core", "bus"; -+ resets = <&syscon_apbc RESET_SSP3>; -+ interrupts = <55>; -+ dmas = <&pdma 20>, <&pdma 19>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ - /* sec_uart1: 0xf0612000, not available from Linux */ - }; - --- -2.53.0 - diff --git a/SPECS/linux/0119-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch b/SPECS/linux/0119-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch deleted file mode 100644 index 4255953faf..0000000000 --- a/SPECS/linux/0119-FROMLIST-dt-bindings-thermal-Add-SpacemiT-K1-thermal.patch +++ /dev/null @@ -1,104 +0,0 @@ -From ec3e1c1aa94069e48e58c4ea4273dbd998d90803 Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Mon, 27 Apr 2026 15:15:15 +0800 -Subject: [PATCH 119/269] FROMLIST: dt-bindings: thermal: Add SpacemiT K1 - thermal sensor - -Document the SpacemiT K1 Thermal Sensor, which supports -monitoring temperatures for five zones: soc, package, gpu, cluster0, -and cluster1. - -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260427-k1-thermal-v5-1-df39187480ed@mailbox.org -Signed-off-by: Han Gao ---- - .../bindings/thermal/spacemit,k1-tsensor.yaml | 76 +++++++++++++++++++ - 1 file changed, 76 insertions(+) - create mode 100644 Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml - -diff --git a/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml -new file mode 100644 -index 000000000000..6dad76a7dd36 ---- /dev/null -+++ b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml -@@ -0,0 +1,76 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/thermal/spacemit,k1-tsensor.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K1 Thermal Sensor -+ -+description: -+ The SpacemiT K1 Thermal Sensor monitors the temperature of the SoC -+ using multiple internal sensors (e.g., soc, package, gpu, clusters). -+ -+maintainers: -+ - Shuwei Wu -+ -+$ref: thermal-sensor.yaml# -+ -+properties: -+ compatible: -+ const: spacemit,k1-tsensor -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: Core clock for thermal sensor -+ - description: Bus clock for thermal sensor -+ -+ clock-names: -+ items: -+ - const: core -+ - const: bus -+ -+ interrupts: -+ maxItems: 1 -+ -+ resets: -+ items: -+ - description: Reset for the thermal sensor -+ -+ "#thermal-sensor-cells": -+ const: 1 -+ description: -+ The first cell indicates the sensor ID. -+ 0 = soc -+ 1 = package -+ 2 = gpu -+ 3 = cluster0 -+ 4 = cluster1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - resets -+ - "#thermal-sensor-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ -+ thermal@d4018000 { -+ compatible = "spacemit,k1-tsensor"; -+ reg = <0xd4018000 0x100>; -+ clocks = <&syscon_apbc CLK_TSEN>, -+ <&syscon_apbc CLK_TSEN_BUS>; -+ clock-names = "core", "bus"; -+ interrupts = <61>; -+ resets = <&syscon_apbc RESET_TSEN>; -+ #thermal-sensor-cells = <1>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux/0119-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch b/SPECS/linux/0119-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch new file mode 100644 index 0000000000..76e0a2491a --- /dev/null +++ b/SPECS/linux/0119-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch @@ -0,0 +1,380 @@ +From e1e51fe8098039cfa37eef351f66125d38079ac5 Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Mon, 27 Apr 2026 15:15:16 +0800 +Subject: [RUYI PATCH] FROMLIST: thermal: spacemit: k1: Add thermal sensor + support + +The thermal sensor on K1 supports monitoring five temperature zones. +The driver registers these sensors with the thermal framework +and supports standard operations: +- Reading temperature (millidegree Celsius) +- Setting high/low thresholds for interrupts + +Reviewed-by: Anand Moon +Tested-by: Anand Moon +Reviewed-by: Troy Mitchell +Reviewed-by: Yao Zi +Tested-by: Vincent Legoll # OrangePi-RV2 +Tested-by: Gong Shuai +Signed-off-by: Shuwei Wu +Link: https://lore.kernel.org/r/20260427-k1-thermal-v5-2-df39187480ed@mailbox.org +Signed-off-by: Han Gao +--- + drivers/thermal/Kconfig | 2 + + drivers/thermal/Makefile | 1 + + drivers/thermal/spacemit/Kconfig | 19 ++ + drivers/thermal/spacemit/Makefile | 3 + + drivers/thermal/spacemit/k1_tsensor.c | 280 ++++++++++++++++++++++++++ + 5 files changed, 305 insertions(+) + create mode 100644 drivers/thermal/spacemit/Kconfig + create mode 100644 drivers/thermal/spacemit/Makefile + create mode 100644 drivers/thermal/spacemit/k1_tsensor.c + +diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig +index b10080d61860..1c4a5cd5a23e 100644 +--- a/drivers/thermal/Kconfig ++++ b/drivers/thermal/Kconfig +@@ -472,6 +472,8 @@ endmenu + + source "drivers/thermal/renesas/Kconfig" + ++source "drivers/thermal/spacemit/Kconfig" ++ + source "drivers/thermal/tegra/Kconfig" + + config GENERIC_ADC_THERMAL +diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile +index bb21e7ea7fc6..3b249195c088 100644 +--- a/drivers/thermal/Makefile ++++ b/drivers/thermal/Makefile +@@ -65,6 +65,7 @@ obj-y += mediatek/ + obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o + obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o + obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o ++obj-y += spacemit/ + obj-$(CONFIG_SPRD_THERMAL) += sprd_thermal.o + obj-$(CONFIG_KHADAS_MCU_FAN_THERMAL) += khadas_mcu_fan.o + obj-$(CONFIG_LOONGSON2_THERMAL) += loongson2_thermal.o +diff --git a/drivers/thermal/spacemit/Kconfig b/drivers/thermal/spacemit/Kconfig +new file mode 100644 +index 000000000000..de7b5ece5af2 +--- /dev/null ++++ b/drivers/thermal/spacemit/Kconfig +@@ -0,0 +1,19 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++menu "SpacemiT thermal drivers" ++depends on ARCH_SPACEMIT || COMPILE_TEST ++ ++config SPACEMIT_K1_TSENSOR ++ tristate "SpacemiT K1 thermal sensor driver" ++ depends on THERMAL_OF ++ help ++ This driver provides support for the thermal sensor ++ integrated in the SpacemiT K1 SoC. ++ ++ The thermal sensor monitors temperatures for five thermal zones: ++ soc, package, gpu, cluster0, and cluster1. It supports reporting ++ temperature values and handling high/low threshold interrupts. ++ ++ Say Y here if you want to enable thermal monitoring on SpacemiT K1. ++ If compiled as a module, it will be called k1_tsensor. ++ ++endmenu +diff --git a/drivers/thermal/spacemit/Makefile b/drivers/thermal/spacemit/Makefile +new file mode 100644 +index 000000000000..82b30741e4ec +--- /dev/null ++++ b/drivers/thermal/spacemit/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++obj-$(CONFIG_SPACEMIT_K1_TSENSOR) += k1_tsensor.o +diff --git a/drivers/thermal/spacemit/k1_tsensor.c b/drivers/thermal/spacemit/k1_tsensor.c +new file mode 100644 +index 000000000000..79222d233129 +--- /dev/null ++++ b/drivers/thermal/spacemit/k1_tsensor.c +@@ -0,0 +1,280 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Thermal sensor driver for SpacemiT K1 SoC ++ * ++ * Copyright (C) 2026 Shuwei Wu ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../thermal_hwmon.h" ++ ++#define K1_TSENSOR_PCTRL_REG 0x00 ++#define K1_TSENSOR_PCTRL_ENABLE BIT(0) ++#define K1_TSENSOR_PCTRL_TEMP_MODE BIT(3) ++#define K1_TSENSOR_PCTRL_RAW_SEL BIT(7) ++ ++#define K1_TSENSOR_PCTRL_CTUNE GENMASK(11, 8) ++#define K1_TSENSOR_PCTRL_SW_CTRL GENMASK(21, 18) ++#define K1_TSENSOR_PCTRL_HW_AUTO_MODE BIT(23) ++ ++#define K1_TSENSOR_EN_REG 0x08 ++#define K1_TSENSOR_EN_ALL GENMASK(MAX_SENSOR_NUMBER - 1, 0) ++ ++#define K1_TSENSOR_TIME_REG 0x0C ++#define K1_TSENSOR_TIME_WAIT_REF_CNT GENMASK(3, 0) ++#define K1_TSENSOR_TIME_ADC_CNT_RST GENMASK(7, 4) ++#define K1_TSENSOR_TIME_FILTER_PERIOD GENMASK(21, 20) ++#define K1_TSENSOR_TIME_MASK GENMASK(23, 0) ++ ++#define K1_TSENSOR_INT_CLR_REG 0x10 ++#define K1_TSENSOR_INT_EN_REG 0x14 ++#define K1_TSENSOR_INT_STA_REG 0x18 ++ ++#define K1_TSENSOR_INT_EN_MASK BIT(0) ++#define K1_TSENSOR_INT_MASK(x) (GENMASK(2, 1) << ((x) * 2)) ++ ++#define K1_TSENSOR_DATA_BASE_REG 0x20 ++#define K1_TSENSOR_DATA_REG(x) (K1_TSENSOR_DATA_BASE_REG + ((x) / 2) * 4) ++#define K1_TSENSOR_DATA_LOW_MASK GENMASK(15, 0) ++#define K1_TSENSOR_DATA_HIGH_MASK GENMASK(31, 16) ++ ++#define K1_TSENSOR_THRSH_BASE_REG 0x40 ++#define K1_TSENSOR_THRSH_REG(x) (K1_TSENSOR_THRSH_BASE_REG + ((x) * 4)) ++#define K1_TSENSOR_THRSH_LOW_MASK GENMASK(15, 0) ++#define K1_TSENSOR_THRSH_HIGH_MASK GENMASK(31, 16) ++ ++#define MAX_SENSOR_NUMBER 5 ++ ++/* Hardware offset value required for temperature calculation */ ++#define TEMPERATURE_OFFSET 278 ++ ++struct k1_tsensor_channel { ++ struct k1_tsensor *ts; ++ struct thermal_zone_device *tzd; ++ int id; ++}; ++ ++struct k1_tsensor { ++ void __iomem *base; ++ struct k1_tsensor_channel ch[MAX_SENSOR_NUMBER]; ++}; ++ ++static void k1_tsensor_init(struct k1_tsensor *ts) ++{ ++ u32 val; ++ ++ /* Disable all the interrupts */ ++ writel(0xffffffff, ts->base + K1_TSENSOR_INT_EN_REG); ++ ++ /* Configure ADC sampling time and filter period */ ++ val = readl(ts->base + K1_TSENSOR_TIME_REG); ++ val &= ~K1_TSENSOR_TIME_MASK; ++ val |= K1_TSENSOR_TIME_FILTER_PERIOD | ++ K1_TSENSOR_TIME_ADC_CNT_RST | ++ K1_TSENSOR_TIME_WAIT_REF_CNT; ++ writel(val, ts->base + K1_TSENSOR_TIME_REG); ++ ++ /* ++ * Enable all sensors' auto mode, enable dither control, ++ * consecutive mode, and power up sensor. ++ */ ++ val = readl(ts->base + K1_TSENSOR_PCTRL_REG); ++ val &= ~K1_TSENSOR_PCTRL_SW_CTRL; ++ val &= ~K1_TSENSOR_PCTRL_CTUNE; ++ val |= K1_TSENSOR_PCTRL_RAW_SEL | ++ K1_TSENSOR_PCTRL_TEMP_MODE | ++ K1_TSENSOR_PCTRL_HW_AUTO_MODE | ++ K1_TSENSOR_PCTRL_ENABLE; ++ writel(val, ts->base + K1_TSENSOR_PCTRL_REG); ++ ++ /* Enable each sensor */ ++ val = readl(ts->base + K1_TSENSOR_EN_REG); ++ val |= K1_TSENSOR_EN_ALL; ++ writel(val, ts->base + K1_TSENSOR_EN_REG); ++} ++ ++static void k1_tsensor_enable_irq(struct k1_tsensor_channel *ch) ++{ ++ struct k1_tsensor *ts = ch->ts; ++ u32 val; ++ ++ val = readl(ts->base + K1_TSENSOR_INT_CLR_REG); ++ val |= K1_TSENSOR_INT_MASK(ch->id); ++ writel(val, ts->base + K1_TSENSOR_INT_CLR_REG); ++ ++ val = readl(ts->base + K1_TSENSOR_INT_EN_REG); ++ val &= ~K1_TSENSOR_INT_MASK(ch->id); ++ writel(val, ts->base + K1_TSENSOR_INT_EN_REG); ++ ++ /* Enable thermal interrupt */ ++ val = readl(ts->base + K1_TSENSOR_INT_EN_REG); ++ val |= K1_TSENSOR_INT_EN_MASK; ++ writel(val, ts->base + K1_TSENSOR_INT_EN_REG); ++} ++ ++/* ++ * The conversion formula used is: ++ * T(m°C) = (((raw_value & mask) >> shift) - TEMPERATURE_OFFSET) * 1000 ++ */ ++static int k1_tsensor_get_temp(struct thermal_zone_device *tz, int *temp) ++{ ++ struct k1_tsensor_channel *ch = thermal_zone_device_priv(tz); ++ struct k1_tsensor *ts = ch->ts; ++ u32 val; ++ ++ val = readl(ts->base + K1_TSENSOR_DATA_REG(ch->id)); ++ if (ch->id % 2) ++ *temp = FIELD_GET(K1_TSENSOR_DATA_HIGH_MASK, val); ++ else ++ *temp = FIELD_GET(K1_TSENSOR_DATA_LOW_MASK, val); ++ ++ *temp -= TEMPERATURE_OFFSET; ++ *temp *= 1000; ++ ++ return 0; ++} ++ ++/* ++ * For each sensor, the hardware threshold register is 32 bits: ++ * - Lower 16 bits [15:0] configure the low threshold temperature. ++ * - Upper 16 bits [31:16] configure the high threshold temperature. ++ */ ++static int k1_tsensor_set_trips(struct thermal_zone_device *tz, int low, int high) ++{ ++ struct k1_tsensor_channel *ch = thermal_zone_device_priv(tz); ++ struct k1_tsensor *ts = ch->ts; ++ u32 val; ++ ++ if (low >= high) ++ return -EINVAL; ++ ++ low = clamp_val(low / 1000 + TEMPERATURE_OFFSET, TEMPERATURE_OFFSET, ++ FIELD_MAX(K1_TSENSOR_THRSH_LOW_MASK)); ++ high = clamp_val(high / 1000 + TEMPERATURE_OFFSET, TEMPERATURE_OFFSET, ++ FIELD_MAX(K1_TSENSOR_THRSH_HIGH_MASK)); ++ ++ val = readl(ts->base + K1_TSENSOR_THRSH_REG(ch->id)); ++ ++ val &= ~(K1_TSENSOR_THRSH_LOW_MASK | K1_TSENSOR_THRSH_HIGH_MASK); ++ val |= FIELD_PREP(K1_TSENSOR_THRSH_LOW_MASK, low); ++ val |= FIELD_PREP(K1_TSENSOR_THRSH_HIGH_MASK, high); ++ ++ writel(val, ts->base + K1_TSENSOR_THRSH_REG(ch->id)); ++ ++ return 0; ++} ++ ++static const struct thermal_zone_device_ops k1_tsensor_ops = { ++ .get_temp = k1_tsensor_get_temp, ++ .set_trips = k1_tsensor_set_trips, ++}; ++ ++static irqreturn_t k1_tsensor_irq_thread(int irq, void *data) ++{ ++ struct k1_tsensor *ts = (struct k1_tsensor *)data; ++ int mask, status, i; ++ ++ status = readl(ts->base + K1_TSENSOR_INT_STA_REG); ++ ++ for (i = 0; i < MAX_SENSOR_NUMBER; i++) { ++ if (status & K1_TSENSOR_INT_MASK(i)) { ++ mask = readl(ts->base + K1_TSENSOR_INT_CLR_REG); ++ mask |= K1_TSENSOR_INT_MASK(i); ++ writel(mask, ts->base + K1_TSENSOR_INT_CLR_REG); ++ thermal_zone_device_update(ts->ch[i].tzd, THERMAL_EVENT_UNSPECIFIED); ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int k1_tsensor_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct k1_tsensor *ts; ++ struct reset_control *reset; ++ struct clk *clk; ++ int i, irq, ret; ++ ++ ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL); ++ if (!ts) ++ return -ENOMEM; ++ ++ ts->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(ts->base)) ++ return dev_err_probe(dev, PTR_ERR(ts->base), "Failed to get reg\n"); ++ ++ reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); ++ if (IS_ERR(reset)) ++ return dev_err_probe(dev, PTR_ERR(reset), "Failed to get/deassert reset control\n"); ++ ++ clk = devm_clk_get_enabled(dev, "core"); ++ if (IS_ERR(clk)) ++ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get core clock\n"); ++ ++ clk = devm_clk_get_enabled(dev, "bus"); ++ if (IS_ERR(clk)) ++ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get bus clock\n"); ++ ++ k1_tsensor_init(ts); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return irq; ++ ++ ret = devm_request_threaded_irq(dev, irq, NULL, ++ k1_tsensor_irq_thread, ++ IRQF_ONESHOT, "k1_tsensor", ts); ++ if (ret < 0) ++ return ret; ++ ++ for (i = 0; i < MAX_SENSOR_NUMBER; ++i) { ++ ts->ch[i].id = i; ++ ts->ch[i].ts = ts; ++ ts->ch[i].tzd = devm_thermal_of_zone_register(dev, i, ts->ch + i, &k1_tsensor_ops); ++ if (IS_ERR(ts->ch[i].tzd)) ++ return PTR_ERR(ts->ch[i].tzd); ++ ++ /* Attach sysfs hwmon attributes for userspace monitoring */ ++ ret = devm_thermal_add_hwmon_sysfs(dev, ts->ch[i].tzd); ++ if (ret) ++ dev_warn(dev, "Failed to add hwmon sysfs attributes\n"); ++ ++ k1_tsensor_enable_irq(ts->ch + i); ++ } ++ ++ platform_set_drvdata(pdev, ts); ++ ++ return 0; ++} ++ ++static const struct of_device_id k1_tsensor_dt_ids[] = { ++ { .compatible = "spacemit,k1-tsensor" }, ++ { /* sentinel */ } ++}; ++ ++MODULE_DEVICE_TABLE(of, k1_tsensor_dt_ids); ++ ++static struct platform_driver k1_tsensor_driver = { ++ .driver = { ++ .name = "k1_tsensor", ++ .of_match_table = k1_tsensor_dt_ids, ++ }, ++ .probe = k1_tsensor_probe, ++}; ++module_platform_driver(k1_tsensor_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K1 Thermal Sensor Driver"); ++MODULE_AUTHOR("Shuwei Wu "); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux/0120-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch b/SPECS/linux/0120-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch new file mode 100644 index 0000000000..a0407f4b91 --- /dev/null +++ b/SPECS/linux/0120-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch @@ -0,0 +1,142 @@ +From 9c37fe5edcd25afac729c2dbcf48b40ef2de06a5 Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Mon, 27 Apr 2026 15:15:17 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add thermal sensor for + K1 SoC + +Include the Thermal Sensor node in the SpacemiT K1 dtsi +with definitions for registers, clocks, and interrupts. +Additionally, configure thermal zones for the soc, package, gpu, and +clusters to enable temperature monitoring via the thermal framework. + +Tested-by: Vincent Legoll # OrangePi-RV2 +Tested-by: Gong Shuai +Signed-off-by: Shuwei Wu +Link: https://lore.kernel.org/r/20260427-k1-thermal-v5-3-df39187480ed@mailbox.org +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 101 +++++++++++++++++++++++++++ + 1 file changed, 101 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index f8747190d2e1..2ed5cc24e505 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -339,6 +339,96 @@ osc_32k: clock-32k { + }; + }; + ++ thermal-zones { ++ soc-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 0>; ++ ++ trips { ++ soc-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ package-thermal { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 1>; ++ ++ trips { ++ package-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ gpu-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 2>; ++ ++ trips { ++ gpu-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ gpu-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ cluster0-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 3>; ++ ++ trips { ++ cluster0-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cluster0-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ cluster1-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <0>; ++ thermal-sensors = <&thermal 4>; ++ ++ trips { ++ cluster1-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cluster1-crit { ++ temperature = <115000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++ + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; +@@ -494,6 +584,17 @@ syscon_apbc: system-controller@d4015000 { + #reset-cells = <1>; + }; + ++ thermal: thermal@d4018000 { ++ compatible = "spacemit,k1-tsensor"; ++ reg = <0x0 0xd4018000 0x0 0x100>; ++ clocks = <&syscon_apbc CLK_TSEN>, ++ <&syscon_apbc CLK_TSEN_BUS>; ++ clock-names = "core", "bus"; ++ interrupts = <61>; ++ resets = <&syscon_apbc RESET_TSEN>; ++ #thermal-sensor-cells = <1>; ++ }; ++ + i2c6: i2c@d4018800 { + compatible = "spacemit,k1-i2c"; + reg = <0x0 0xd4018800 0x0 0x38>; +-- +2.53.0 + diff --git a/SPECS/linux/0120-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch b/SPECS/linux/0120-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch deleted file mode 100644 index fd38eca8b1..0000000000 --- a/SPECS/linux/0120-FROMLIST-thermal-spacemit-k1-Add-thermal-sensor-supp.patch +++ /dev/null @@ -1,380 +0,0 @@ -From 895c9bf4639434336ee6d5f9d8f6750f4718c072 Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Mon, 27 Apr 2026 15:15:16 +0800 -Subject: [PATCH 120/269] FROMLIST: thermal: spacemit: k1: Add thermal sensor - support - -The thermal sensor on K1 supports monitoring five temperature zones. -The driver registers these sensors with the thermal framework -and supports standard operations: -- Reading temperature (millidegree Celsius) -- Setting high/low thresholds for interrupts - -Reviewed-by: Anand Moon -Tested-by: Anand Moon -Reviewed-by: Troy Mitchell -Reviewed-by: Yao Zi -Tested-by: Vincent Legoll # OrangePi-RV2 -Tested-by: Gong Shuai -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260427-k1-thermal-v5-2-df39187480ed@mailbox.org -Signed-off-by: Han Gao ---- - drivers/thermal/Kconfig | 2 + - drivers/thermal/Makefile | 1 + - drivers/thermal/spacemit/Kconfig | 19 ++ - drivers/thermal/spacemit/Makefile | 3 + - drivers/thermal/spacemit/k1_tsensor.c | 280 ++++++++++++++++++++++++++ - 5 files changed, 305 insertions(+) - create mode 100644 drivers/thermal/spacemit/Kconfig - create mode 100644 drivers/thermal/spacemit/Makefile - create mode 100644 drivers/thermal/spacemit/k1_tsensor.c - -diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig -index b10080d61860..1c4a5cd5a23e 100644 ---- a/drivers/thermal/Kconfig -+++ b/drivers/thermal/Kconfig -@@ -472,6 +472,8 @@ endmenu - - source "drivers/thermal/renesas/Kconfig" - -+source "drivers/thermal/spacemit/Kconfig" -+ - source "drivers/thermal/tegra/Kconfig" - - config GENERIC_ADC_THERMAL -diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile -index bb21e7ea7fc6..3b249195c088 100644 ---- a/drivers/thermal/Makefile -+++ b/drivers/thermal/Makefile -@@ -65,6 +65,7 @@ obj-y += mediatek/ - obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o - obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o - obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o -+obj-y += spacemit/ - obj-$(CONFIG_SPRD_THERMAL) += sprd_thermal.o - obj-$(CONFIG_KHADAS_MCU_FAN_THERMAL) += khadas_mcu_fan.o - obj-$(CONFIG_LOONGSON2_THERMAL) += loongson2_thermal.o -diff --git a/drivers/thermal/spacemit/Kconfig b/drivers/thermal/spacemit/Kconfig -new file mode 100644 -index 000000000000..de7b5ece5af2 ---- /dev/null -+++ b/drivers/thermal/spacemit/Kconfig -@@ -0,0 +1,19 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+menu "SpacemiT thermal drivers" -+depends on ARCH_SPACEMIT || COMPILE_TEST -+ -+config SPACEMIT_K1_TSENSOR -+ tristate "SpacemiT K1 thermal sensor driver" -+ depends on THERMAL_OF -+ help -+ This driver provides support for the thermal sensor -+ integrated in the SpacemiT K1 SoC. -+ -+ The thermal sensor monitors temperatures for five thermal zones: -+ soc, package, gpu, cluster0, and cluster1. It supports reporting -+ temperature values and handling high/low threshold interrupts. -+ -+ Say Y here if you want to enable thermal monitoring on SpacemiT K1. -+ If compiled as a module, it will be called k1_tsensor. -+ -+endmenu -diff --git a/drivers/thermal/spacemit/Makefile b/drivers/thermal/spacemit/Makefile -new file mode 100644 -index 000000000000..82b30741e4ec ---- /dev/null -+++ b/drivers/thermal/spacemit/Makefile -@@ -0,0 +1,3 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+obj-$(CONFIG_SPACEMIT_K1_TSENSOR) += k1_tsensor.o -diff --git a/drivers/thermal/spacemit/k1_tsensor.c b/drivers/thermal/spacemit/k1_tsensor.c -new file mode 100644 -index 000000000000..79222d233129 ---- /dev/null -+++ b/drivers/thermal/spacemit/k1_tsensor.c -@@ -0,0 +1,280 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Thermal sensor driver for SpacemiT K1 SoC -+ * -+ * Copyright (C) 2026 Shuwei Wu -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../thermal_hwmon.h" -+ -+#define K1_TSENSOR_PCTRL_REG 0x00 -+#define K1_TSENSOR_PCTRL_ENABLE BIT(0) -+#define K1_TSENSOR_PCTRL_TEMP_MODE BIT(3) -+#define K1_TSENSOR_PCTRL_RAW_SEL BIT(7) -+ -+#define K1_TSENSOR_PCTRL_CTUNE GENMASK(11, 8) -+#define K1_TSENSOR_PCTRL_SW_CTRL GENMASK(21, 18) -+#define K1_TSENSOR_PCTRL_HW_AUTO_MODE BIT(23) -+ -+#define K1_TSENSOR_EN_REG 0x08 -+#define K1_TSENSOR_EN_ALL GENMASK(MAX_SENSOR_NUMBER - 1, 0) -+ -+#define K1_TSENSOR_TIME_REG 0x0C -+#define K1_TSENSOR_TIME_WAIT_REF_CNT GENMASK(3, 0) -+#define K1_TSENSOR_TIME_ADC_CNT_RST GENMASK(7, 4) -+#define K1_TSENSOR_TIME_FILTER_PERIOD GENMASK(21, 20) -+#define K1_TSENSOR_TIME_MASK GENMASK(23, 0) -+ -+#define K1_TSENSOR_INT_CLR_REG 0x10 -+#define K1_TSENSOR_INT_EN_REG 0x14 -+#define K1_TSENSOR_INT_STA_REG 0x18 -+ -+#define K1_TSENSOR_INT_EN_MASK BIT(0) -+#define K1_TSENSOR_INT_MASK(x) (GENMASK(2, 1) << ((x) * 2)) -+ -+#define K1_TSENSOR_DATA_BASE_REG 0x20 -+#define K1_TSENSOR_DATA_REG(x) (K1_TSENSOR_DATA_BASE_REG + ((x) / 2) * 4) -+#define K1_TSENSOR_DATA_LOW_MASK GENMASK(15, 0) -+#define K1_TSENSOR_DATA_HIGH_MASK GENMASK(31, 16) -+ -+#define K1_TSENSOR_THRSH_BASE_REG 0x40 -+#define K1_TSENSOR_THRSH_REG(x) (K1_TSENSOR_THRSH_BASE_REG + ((x) * 4)) -+#define K1_TSENSOR_THRSH_LOW_MASK GENMASK(15, 0) -+#define K1_TSENSOR_THRSH_HIGH_MASK GENMASK(31, 16) -+ -+#define MAX_SENSOR_NUMBER 5 -+ -+/* Hardware offset value required for temperature calculation */ -+#define TEMPERATURE_OFFSET 278 -+ -+struct k1_tsensor_channel { -+ struct k1_tsensor *ts; -+ struct thermal_zone_device *tzd; -+ int id; -+}; -+ -+struct k1_tsensor { -+ void __iomem *base; -+ struct k1_tsensor_channel ch[MAX_SENSOR_NUMBER]; -+}; -+ -+static void k1_tsensor_init(struct k1_tsensor *ts) -+{ -+ u32 val; -+ -+ /* Disable all the interrupts */ -+ writel(0xffffffff, ts->base + K1_TSENSOR_INT_EN_REG); -+ -+ /* Configure ADC sampling time and filter period */ -+ val = readl(ts->base + K1_TSENSOR_TIME_REG); -+ val &= ~K1_TSENSOR_TIME_MASK; -+ val |= K1_TSENSOR_TIME_FILTER_PERIOD | -+ K1_TSENSOR_TIME_ADC_CNT_RST | -+ K1_TSENSOR_TIME_WAIT_REF_CNT; -+ writel(val, ts->base + K1_TSENSOR_TIME_REG); -+ -+ /* -+ * Enable all sensors' auto mode, enable dither control, -+ * consecutive mode, and power up sensor. -+ */ -+ val = readl(ts->base + K1_TSENSOR_PCTRL_REG); -+ val &= ~K1_TSENSOR_PCTRL_SW_CTRL; -+ val &= ~K1_TSENSOR_PCTRL_CTUNE; -+ val |= K1_TSENSOR_PCTRL_RAW_SEL | -+ K1_TSENSOR_PCTRL_TEMP_MODE | -+ K1_TSENSOR_PCTRL_HW_AUTO_MODE | -+ K1_TSENSOR_PCTRL_ENABLE; -+ writel(val, ts->base + K1_TSENSOR_PCTRL_REG); -+ -+ /* Enable each sensor */ -+ val = readl(ts->base + K1_TSENSOR_EN_REG); -+ val |= K1_TSENSOR_EN_ALL; -+ writel(val, ts->base + K1_TSENSOR_EN_REG); -+} -+ -+static void k1_tsensor_enable_irq(struct k1_tsensor_channel *ch) -+{ -+ struct k1_tsensor *ts = ch->ts; -+ u32 val; -+ -+ val = readl(ts->base + K1_TSENSOR_INT_CLR_REG); -+ val |= K1_TSENSOR_INT_MASK(ch->id); -+ writel(val, ts->base + K1_TSENSOR_INT_CLR_REG); -+ -+ val = readl(ts->base + K1_TSENSOR_INT_EN_REG); -+ val &= ~K1_TSENSOR_INT_MASK(ch->id); -+ writel(val, ts->base + K1_TSENSOR_INT_EN_REG); -+ -+ /* Enable thermal interrupt */ -+ val = readl(ts->base + K1_TSENSOR_INT_EN_REG); -+ val |= K1_TSENSOR_INT_EN_MASK; -+ writel(val, ts->base + K1_TSENSOR_INT_EN_REG); -+} -+ -+/* -+ * The conversion formula used is: -+ * T(m°C) = (((raw_value & mask) >> shift) - TEMPERATURE_OFFSET) * 1000 -+ */ -+static int k1_tsensor_get_temp(struct thermal_zone_device *tz, int *temp) -+{ -+ struct k1_tsensor_channel *ch = thermal_zone_device_priv(tz); -+ struct k1_tsensor *ts = ch->ts; -+ u32 val; -+ -+ val = readl(ts->base + K1_TSENSOR_DATA_REG(ch->id)); -+ if (ch->id % 2) -+ *temp = FIELD_GET(K1_TSENSOR_DATA_HIGH_MASK, val); -+ else -+ *temp = FIELD_GET(K1_TSENSOR_DATA_LOW_MASK, val); -+ -+ *temp -= TEMPERATURE_OFFSET; -+ *temp *= 1000; -+ -+ return 0; -+} -+ -+/* -+ * For each sensor, the hardware threshold register is 32 bits: -+ * - Lower 16 bits [15:0] configure the low threshold temperature. -+ * - Upper 16 bits [31:16] configure the high threshold temperature. -+ */ -+static int k1_tsensor_set_trips(struct thermal_zone_device *tz, int low, int high) -+{ -+ struct k1_tsensor_channel *ch = thermal_zone_device_priv(tz); -+ struct k1_tsensor *ts = ch->ts; -+ u32 val; -+ -+ if (low >= high) -+ return -EINVAL; -+ -+ low = clamp_val(low / 1000 + TEMPERATURE_OFFSET, TEMPERATURE_OFFSET, -+ FIELD_MAX(K1_TSENSOR_THRSH_LOW_MASK)); -+ high = clamp_val(high / 1000 + TEMPERATURE_OFFSET, TEMPERATURE_OFFSET, -+ FIELD_MAX(K1_TSENSOR_THRSH_HIGH_MASK)); -+ -+ val = readl(ts->base + K1_TSENSOR_THRSH_REG(ch->id)); -+ -+ val &= ~(K1_TSENSOR_THRSH_LOW_MASK | K1_TSENSOR_THRSH_HIGH_MASK); -+ val |= FIELD_PREP(K1_TSENSOR_THRSH_LOW_MASK, low); -+ val |= FIELD_PREP(K1_TSENSOR_THRSH_HIGH_MASK, high); -+ -+ writel(val, ts->base + K1_TSENSOR_THRSH_REG(ch->id)); -+ -+ return 0; -+} -+ -+static const struct thermal_zone_device_ops k1_tsensor_ops = { -+ .get_temp = k1_tsensor_get_temp, -+ .set_trips = k1_tsensor_set_trips, -+}; -+ -+static irqreturn_t k1_tsensor_irq_thread(int irq, void *data) -+{ -+ struct k1_tsensor *ts = (struct k1_tsensor *)data; -+ int mask, status, i; -+ -+ status = readl(ts->base + K1_TSENSOR_INT_STA_REG); -+ -+ for (i = 0; i < MAX_SENSOR_NUMBER; i++) { -+ if (status & K1_TSENSOR_INT_MASK(i)) { -+ mask = readl(ts->base + K1_TSENSOR_INT_CLR_REG); -+ mask |= K1_TSENSOR_INT_MASK(i); -+ writel(mask, ts->base + K1_TSENSOR_INT_CLR_REG); -+ thermal_zone_device_update(ts->ch[i].tzd, THERMAL_EVENT_UNSPECIFIED); -+ } -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int k1_tsensor_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct k1_tsensor *ts; -+ struct reset_control *reset; -+ struct clk *clk; -+ int i, irq, ret; -+ -+ ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL); -+ if (!ts) -+ return -ENOMEM; -+ -+ ts->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(ts->base)) -+ return dev_err_probe(dev, PTR_ERR(ts->base), "Failed to get reg\n"); -+ -+ reset = devm_reset_control_get_exclusive_deasserted(dev, NULL); -+ if (IS_ERR(reset)) -+ return dev_err_probe(dev, PTR_ERR(reset), "Failed to get/deassert reset control\n"); -+ -+ clk = devm_clk_get_enabled(dev, "core"); -+ if (IS_ERR(clk)) -+ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get core clock\n"); -+ -+ clk = devm_clk_get_enabled(dev, "bus"); -+ if (IS_ERR(clk)) -+ return dev_err_probe(dev, PTR_ERR(clk), "Failed to get bus clock\n"); -+ -+ k1_tsensor_init(ts); -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) -+ return irq; -+ -+ ret = devm_request_threaded_irq(dev, irq, NULL, -+ k1_tsensor_irq_thread, -+ IRQF_ONESHOT, "k1_tsensor", ts); -+ if (ret < 0) -+ return ret; -+ -+ for (i = 0; i < MAX_SENSOR_NUMBER; ++i) { -+ ts->ch[i].id = i; -+ ts->ch[i].ts = ts; -+ ts->ch[i].tzd = devm_thermal_of_zone_register(dev, i, ts->ch + i, &k1_tsensor_ops); -+ if (IS_ERR(ts->ch[i].tzd)) -+ return PTR_ERR(ts->ch[i].tzd); -+ -+ /* Attach sysfs hwmon attributes for userspace monitoring */ -+ ret = devm_thermal_add_hwmon_sysfs(dev, ts->ch[i].tzd); -+ if (ret) -+ dev_warn(dev, "Failed to add hwmon sysfs attributes\n"); -+ -+ k1_tsensor_enable_irq(ts->ch + i); -+ } -+ -+ platform_set_drvdata(pdev, ts); -+ -+ return 0; -+} -+ -+static const struct of_device_id k1_tsensor_dt_ids[] = { -+ { .compatible = "spacemit,k1-tsensor" }, -+ { /* sentinel */ } -+}; -+ -+MODULE_DEVICE_TABLE(of, k1_tsensor_dt_ids); -+ -+static struct platform_driver k1_tsensor_driver = { -+ .driver = { -+ .name = "k1_tsensor", -+ .of_match_table = k1_tsensor_dt_ids, -+ }, -+ .probe = k1_tsensor_probe, -+}; -+module_platform_driver(k1_tsensor_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K1 Thermal Sensor Driver"); -+MODULE_AUTHOR("Shuwei Wu "); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux/0121-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch b/SPECS/linux/0121-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch new file mode 100644 index 0000000000..49a230187c --- /dev/null +++ b/SPECS/linux/0121-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch @@ -0,0 +1,57 @@ +From cc245f283a04934061e450ad020c5ef035bfd744 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 17:24:21 +0800 +Subject: [RUYI PATCH] FROMLIST: net: spacemit: Free rings of memory after + unmapping DMA + +In emac_free_{tx,rx}_resources, call dma_free_coherent() to unmap DMA +before calling kfree() to deallocate the memory, instead of the other +way around. + +Fixes: bfec6d7f2001 ("net: spacemit: Add K1 Ethernet MAC") +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260303-k1-ethernet-more-fixes-v1-4-0ab0122fdd14@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/net/ethernet/spacemit/k1_emac.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c +index f7f16397a2c2..02a009afc921 100644 +--- a/drivers/net/ethernet/spacemit/k1_emac.c ++++ b/drivers/net/ethernet/spacemit/k1_emac.c +@@ -446,12 +446,12 @@ static void emac_free_tx_resources(struct emac_priv *priv) + + emac_clean_tx_desc_ring(priv); + +- kfree(tr->tx_desc_buf); +- tr->tx_desc_buf = NULL; +- + dma_free_coherent(dev, tr->total_size, tr->desc_addr, + tr->desc_dma_addr); + tr->desc_addr = NULL; ++ ++ kfree(tr->tx_desc_buf); ++ tr->tx_desc_buf = NULL; + } + + static void emac_free_rx_resources(struct emac_priv *priv) +@@ -461,12 +461,12 @@ static void emac_free_rx_resources(struct emac_priv *priv) + + emac_clean_rx_desc_ring(priv); + +- kfree(rr->rx_desc_buf); +- rr->rx_desc_buf = NULL; +- + dma_free_coherent(dev, rr->total_size, rr->desc_addr, + rr->desc_dma_addr); + rr->desc_addr = NULL; ++ ++ kfree(rr->rx_desc_buf); ++ rr->rx_desc_buf = NULL; + } + + static int emac_tx_clean_desc(struct emac_priv *priv) +-- +2.53.0 + diff --git a/SPECS/linux/0121-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch b/SPECS/linux/0121-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch deleted file mode 100644 index 1a3a0bf8d8..0000000000 --- a/SPECS/linux/0121-FROMLIST-riscv-dts-spacemit-Add-thermal-sensor-for-K.patch +++ /dev/null @@ -1,142 +0,0 @@ -From 36561b9bc6e0b2704f4d2fa97ed3d6d146842d0e Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Mon, 27 Apr 2026 15:15:17 +0800 -Subject: [PATCH 121/269] FROMLIST: riscv: dts: spacemit: Add thermal sensor - for K1 SoC - -Include the Thermal Sensor node in the SpacemiT K1 dtsi -with definitions for registers, clocks, and interrupts. -Additionally, configure thermal zones for the soc, package, gpu, and -clusters to enable temperature monitoring via the thermal framework. - -Tested-by: Vincent Legoll # OrangePi-RV2 -Tested-by: Gong Shuai -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260427-k1-thermal-v5-3-df39187480ed@mailbox.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 101 +++++++++++++++++++++++++++ - 1 file changed, 101 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index f8747190d2e1..2ed5cc24e505 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -339,6 +339,96 @@ osc_32k: clock-32k { - }; - }; - -+ thermal-zones { -+ soc-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 0>; -+ -+ trips { -+ soc-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ package-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 1>; -+ -+ trips { -+ package-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ gpu-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 2>; -+ -+ trips { -+ gpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ gpu-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ cluster0-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 3>; -+ -+ trips { -+ cluster0-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cluster0-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ cluster1-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&thermal 4>; -+ -+ trips { -+ cluster1-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cluster1-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; -@@ -494,6 +584,17 @@ syscon_apbc: system-controller@d4015000 { - #reset-cells = <1>; - }; - -+ thermal: thermal@d4018000 { -+ compatible = "spacemit,k1-tsensor"; -+ reg = <0x0 0xd4018000 0x0 0x100>; -+ clocks = <&syscon_apbc CLK_TSEN>, -+ <&syscon_apbc CLK_TSEN_BUS>; -+ clock-names = "core", "bus"; -+ interrupts = <61>; -+ resets = <&syscon_apbc RESET_TSEN>; -+ #thermal-sensor-cells = <1>; -+ }; -+ - i2c6: i2c@d4018800 { - compatible = "spacemit,k1-i2c"; - reg = <0x0 0xd4018800 0x0 0x38>; --- -2.53.0 - diff --git a/SPECS/linux/0122-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch b/SPECS/linux/0122-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch deleted file mode 100644 index 5a0f474570..0000000000 --- a/SPECS/linux/0122-FROMLIST-net-spacemit-Free-rings-of-memory-after-unm.patch +++ /dev/null @@ -1,57 +0,0 @@ -From ebf8d5dd8aadfb8248b1a8efac678486f96d0b37 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 17:24:21 +0800 -Subject: [PATCH 122/269] FROMLIST: net: spacemit: Free rings of memory after - unmapping DMA - -In emac_free_{tx,rx}_resources, call dma_free_coherent() to unmap DMA -before calling kfree() to deallocate the memory, instead of the other -way around. - -Fixes: bfec6d7f2001 ("net: spacemit: Add K1 Ethernet MAC") -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-k1-ethernet-more-fixes-v1-4-0ab0122fdd14@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/net/ethernet/spacemit/k1_emac.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c -index f7f16397a2c2..02a009afc921 100644 ---- a/drivers/net/ethernet/spacemit/k1_emac.c -+++ b/drivers/net/ethernet/spacemit/k1_emac.c -@@ -446,12 +446,12 @@ static void emac_free_tx_resources(struct emac_priv *priv) - - emac_clean_tx_desc_ring(priv); - -- kfree(tr->tx_desc_buf); -- tr->tx_desc_buf = NULL; -- - dma_free_coherent(dev, tr->total_size, tr->desc_addr, - tr->desc_dma_addr); - tr->desc_addr = NULL; -+ -+ kfree(tr->tx_desc_buf); -+ tr->tx_desc_buf = NULL; - } - - static void emac_free_rx_resources(struct emac_priv *priv) -@@ -461,12 +461,12 @@ static void emac_free_rx_resources(struct emac_priv *priv) - - emac_clean_rx_desc_ring(priv); - -- kfree(rr->rx_desc_buf); -- rr->rx_desc_buf = NULL; -- - dma_free_coherent(dev, rr->total_size, rr->desc_addr, - rr->desc_dma_addr); - rr->desc_addr = NULL; -+ -+ kfree(rr->rx_desc_buf); -+ rr->rx_desc_buf = NULL; - } - - static int emac_tx_clean_desc(struct emac_priv *priv) --- -2.53.0 - diff --git a/SPECS/linux/0122-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch b/SPECS/linux/0122-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch new file mode 100644 index 0000000000..b44ff51416 --- /dev/null +++ b/SPECS/linux/0122-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch @@ -0,0 +1,61 @@ +From 0b454a34dd5bc855e817eaf43baf0ee8f831ba7a Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 13:29:45 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Extract helper mark_new_valid_map() + +In preparation of a future patch using the same mechanism for +non-vmalloc addresses, extract the mark_new_valid_map() helper from +flush_cache_vmap(). + +No functional change intended. + +Cc: stable@vger.kernel.org +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-1-f80d8354d79d@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 25 ++++++++++++++----------- + 1 file changed, 14 insertions(+), 11 deletions(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index 0092513c3376..b1a2ac665792 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -43,20 +43,23 @@ do { \ + #ifdef CONFIG_64BIT + extern u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; + extern char _end[]; ++static inline void mark_new_valid_map(void) ++{ ++ int i; ++ ++ /* ++ * We don't care if concurrently a cpu resets this value since ++ * the only place this can happen is in handle_exception() where ++ * an sfence.vma is emitted. ++ */ ++ for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) ++ new_vmalloc[i] = -1ULL; ++} + #define flush_cache_vmap flush_cache_vmap + static inline void flush_cache_vmap(unsigned long start, unsigned long end) + { +- if (is_vmalloc_or_module_addr((void *)start)) { +- int i; +- +- /* +- * We don't care if concurrently a cpu resets this value since +- * the only place this can happen is in handle_exception() where +- * an sfence.vma is emitted. +- */ +- for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) +- new_vmalloc[i] = -1ULL; +- } ++ if (is_vmalloc_or_module_addr((void *)start)) ++ mark_new_valid_map(); + } + #define flush_cache_vmap_early(start, end) local_flush_tlb_kernel_range(start, end) + #endif +-- +2.53.0 + diff --git a/SPECS/linux/0123-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch b/SPECS/linux/0123-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch new file mode 100644 index 0000000000..5f7959bf8e --- /dev/null +++ b/SPECS/linux/0123-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch @@ -0,0 +1,80 @@ +From ba5b054467f0ae1657d12706b2a39f2bf80f9276 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 13:29:46 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: kfence: Call mark_new_valid_map() for + kfence_unprotect() + +In kfence_protect_page(), which kfence_unprotect() calls, we cannot send +IPIs to other CPUs to ask them to flush TLB. This may lead to those CPUs +spuriously faulting on a recently allocated kfence object despite it +being valid, leading to false positive use-after-free reports. + +Fix this by calling mark_new_valid_map() so that the page fault handling +code path notices the spurious fault and flushes TLB then retries the +access. + +Update the comment in handle_exception to indicate that +new_valid_map_cpus_check also handles kfence_unprotect() spurious +faults. + +Note that kfence_protect() has the same stale TLB entries problem, but +that leads to false negatives, which is fine with kfence. + +Cc: stable@vger.kernel.org +Reported-by: Yanko Kaneti +Fixes: b3431a8bb336 ("riscv: Fix IPIs usage in kfence_protect_page()") +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-2-f80d8354d79d@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/kfence.h | 7 +++++-- + arch/riscv/kernel/entry.S | 6 ++++-- + 2 files changed, 9 insertions(+), 4 deletions(-) + +diff --git a/arch/riscv/include/asm/kfence.h b/arch/riscv/include/asm/kfence.h +index d08bf7fb3aee..29cb3a6ee113 100644 +--- a/arch/riscv/include/asm/kfence.h ++++ b/arch/riscv/include/asm/kfence.h +@@ -6,6 +6,7 @@ + #include + #include + #include ++#include + #include + + static inline bool arch_kfence_init_pool(void) +@@ -17,10 +18,12 @@ static inline bool kfence_protect_page(unsigned long addr, bool protect) + { + pte_t *pte = virt_to_kpte(addr); + +- if (protect) ++ if (protect) { + set_pte(pte, __pte(pte_val(ptep_get(pte)) & ~_PAGE_PRESENT)); +- else ++ } else { + set_pte(pte, __pte(pte_val(ptep_get(pte)) | _PAGE_PRESENT)); ++ mark_new_valid_map(); ++ } + + preempt_disable(); + local_flush_tlb_kernel_range(addr, addr + PAGE_SIZE); +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index 60eb221296a6..ced7a2b160ce 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -136,8 +136,10 @@ SYM_CODE_START(handle_exception) + + #ifdef CONFIG_64BIT + /* +- * The RISC-V kernel does not eagerly emit a sfence.vma after each +- * new vmalloc mapping, which may result in exceptions: ++ * The RISC-V kernel does not flush TLBs on all CPUS after each new ++ * vmalloc mapping or kfence_unprotect(), which may result in ++ * exceptions: ++ * + * - if the uarch caches invalid entries, the new mapping would not be + * observed by the page table walker and an invalidation is needed. + * - if the uarch does not cache invalid entries, a reordered access +-- +2.53.0 + diff --git a/SPECS/linux/0123-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch b/SPECS/linux/0123-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch deleted file mode 100644 index 1c7be92113..0000000000 --- a/SPECS/linux/0123-FROMLIST-riscv-mm-Extract-helper-mark_new_valid_map.patch +++ /dev/null @@ -1,62 +0,0 @@ -From ff5797e0c0c241485e19663b8acf6325074ec17b Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:45 +0800 -Subject: [PATCH 123/269] FROMLIST: riscv: mm: Extract helper - mark_new_valid_map() - -In preparation of a future patch using the same mechanism for -non-vmalloc addresses, extract the mark_new_valid_map() helper from -flush_cache_vmap(). - -No functional change intended. - -Cc: stable@vger.kernel.org -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-1-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/cacheflush.h | 25 ++++++++++++++----------- - 1 file changed, 14 insertions(+), 11 deletions(-) - -diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h -index 0092513c3376..b1a2ac665792 100644 ---- a/arch/riscv/include/asm/cacheflush.h -+++ b/arch/riscv/include/asm/cacheflush.h -@@ -43,20 +43,23 @@ do { \ - #ifdef CONFIG_64BIT - extern u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; - extern char _end[]; -+static inline void mark_new_valid_map(void) -+{ -+ int i; -+ -+ /* -+ * We don't care if concurrently a cpu resets this value since -+ * the only place this can happen is in handle_exception() where -+ * an sfence.vma is emitted. -+ */ -+ for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) -+ new_vmalloc[i] = -1ULL; -+} - #define flush_cache_vmap flush_cache_vmap - static inline void flush_cache_vmap(unsigned long start, unsigned long end) - { -- if (is_vmalloc_or_module_addr((void *)start)) { -- int i; -- -- /* -- * We don't care if concurrently a cpu resets this value since -- * the only place this can happen is in handle_exception() where -- * an sfence.vma is emitted. -- */ -- for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) -- new_vmalloc[i] = -1ULL; -- } -+ if (is_vmalloc_or_module_addr((void *)start)) -+ mark_new_valid_map(); - } - #define flush_cache_vmap_early(start, end) local_flush_tlb_kernel_range(start, end) - #endif --- -2.53.0 - diff --git a/SPECS/linux/0124-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch b/SPECS/linux/0124-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch deleted file mode 100644 index 6db618e22d..0000000000 --- a/SPECS/linux/0124-FROMLIST-riscv-kfence-Call-mark_new_valid_map-for-kf.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 953e866bd2868d60b84a8b2716d4bd5891982912 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:46 +0800 -Subject: [PATCH 124/269] FROMLIST: riscv: kfence: Call mark_new_valid_map() - for kfence_unprotect() - -In kfence_protect_page(), which kfence_unprotect() calls, we cannot send -IPIs to other CPUs to ask them to flush TLB. This may lead to those CPUs -spuriously faulting on a recently allocated kfence object despite it -being valid, leading to false positive use-after-free reports. - -Fix this by calling mark_new_valid_map() so that the page fault handling -code path notices the spurious fault and flushes TLB then retries the -access. - -Update the comment in handle_exception to indicate that -new_valid_map_cpus_check also handles kfence_unprotect() spurious -faults. - -Note that kfence_protect() has the same stale TLB entries problem, but -that leads to false negatives, which is fine with kfence. - -Cc: stable@vger.kernel.org -Reported-by: Yanko Kaneti -Fixes: b3431a8bb336 ("riscv: Fix IPIs usage in kfence_protect_page()") -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-2-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/kfence.h | 7 +++++-- - arch/riscv/kernel/entry.S | 6 ++++-- - 2 files changed, 9 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/include/asm/kfence.h b/arch/riscv/include/asm/kfence.h -index d08bf7fb3aee..29cb3a6ee113 100644 ---- a/arch/riscv/include/asm/kfence.h -+++ b/arch/riscv/include/asm/kfence.h -@@ -6,6 +6,7 @@ - #include - #include - #include -+#include - #include - - static inline bool arch_kfence_init_pool(void) -@@ -17,10 +18,12 @@ static inline bool kfence_protect_page(unsigned long addr, bool protect) - { - pte_t *pte = virt_to_kpte(addr); - -- if (protect) -+ if (protect) { - set_pte(pte, __pte(pte_val(ptep_get(pte)) & ~_PAGE_PRESENT)); -- else -+ } else { - set_pte(pte, __pte(pte_val(ptep_get(pte)) | _PAGE_PRESENT)); -+ mark_new_valid_map(); -+ } - - preempt_disable(); - local_flush_tlb_kernel_range(addr, addr + PAGE_SIZE); -diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S -index 60eb221296a6..ced7a2b160ce 100644 ---- a/arch/riscv/kernel/entry.S -+++ b/arch/riscv/kernel/entry.S -@@ -136,8 +136,10 @@ SYM_CODE_START(handle_exception) - - #ifdef CONFIG_64BIT - /* -- * The RISC-V kernel does not eagerly emit a sfence.vma after each -- * new vmalloc mapping, which may result in exceptions: -+ * The RISC-V kernel does not flush TLBs on all CPUS after each new -+ * vmalloc mapping or kfence_unprotect(), which may result in -+ * exceptions: -+ * - * - if the uarch caches invalid entries, the new mapping would not be - * observed by the page table walker and an invalidation is needed. - * - if the uarch does not cache invalid entries, a reordered access --- -2.53.0 - diff --git a/SPECS/linux/0124-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch b/SPECS/linux/0124-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch new file mode 100644 index 0000000000..8af6383ea3 --- /dev/null +++ b/SPECS/linux/0124-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch @@ -0,0 +1,162 @@ +From 6553a8ba35d78ec2ded4d52da12072e84db3ce22 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 13:29:47 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Rename new_vmalloc into + new_valid_map_cpus + +Since this mechanism is now used for the kfence pool, which comes from +the linear mapping and not vmalloc, rename new_vmalloc into +new_valid_map_cpus to avoid misleading readers. + +No functional change intended. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-3-f80d8354d79d@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 6 ++--- + arch/riscv/kernel/entry.S | 38 ++++++++++++++--------------- + arch/riscv/mm/init.c | 2 +- + 3 files changed, 23 insertions(+), 23 deletions(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index b1a2ac665792..8c7a0ef2635a 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -41,7 +41,7 @@ do { \ + } while (0) + + #ifdef CONFIG_64BIT +-extern u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; ++extern u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; + extern char _end[]; + static inline void mark_new_valid_map(void) + { +@@ -52,8 +52,8 @@ static inline void mark_new_valid_map(void) + * the only place this can happen is in handle_exception() where + * an sfence.vma is emitted. + */ +- for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) +- new_vmalloc[i] = -1ULL; ++ for (i = 0; i < ARRAY_SIZE(new_valid_map_cpus); ++i) ++ new_valid_map_cpus[i] = -1ULL; + } + #define flush_cache_vmap flush_cache_vmap + static inline void flush_cache_vmap(unsigned long start, unsigned long end) +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index ced7a2b160ce..9c6acfd09141 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -20,44 +20,44 @@ + + .section .irqentry.text, "ax" + +-.macro new_vmalloc_check ++.macro new_valid_map_cpus_check + REG_S a0, TASK_TI_A0(tp) + csrr a0, CSR_CAUSE + /* Exclude IRQs */ +- blt a0, zero, .Lnew_vmalloc_restore_context_a0 ++ blt a0, zero, .Lnew_valid_map_cpus_restore_context_a0 + + REG_S a1, TASK_TI_A1(tp) +- /* Only check new_vmalloc if we are in page/protection fault */ ++ /* Only check new_valid_map_cpus if we are in page/protection fault */ + li a1, EXC_LOAD_PAGE_FAULT +- beq a0, a1, .Lnew_vmalloc_kernel_address ++ beq a0, a1, .Lnew_valid_map_cpus_kernel_address + li a1, EXC_STORE_PAGE_FAULT +- beq a0, a1, .Lnew_vmalloc_kernel_address ++ beq a0, a1, .Lnew_valid_map_cpus_kernel_address + li a1, EXC_INST_PAGE_FAULT +- bne a0, a1, .Lnew_vmalloc_restore_context_a1 ++ bne a0, a1, .Lnew_valid_map_cpus_restore_context_a1 + +-.Lnew_vmalloc_kernel_address: ++.Lnew_valid_map_cpus_kernel_address: + /* Is it a kernel address? */ + csrr a0, CSR_TVAL +- bge a0, zero, .Lnew_vmalloc_restore_context_a1 ++ bge a0, zero, .Lnew_valid_map_cpus_restore_context_a1 + + /* Check if a new vmalloc mapping appeared that could explain the trap */ + REG_S a2, TASK_TI_A2(tp) + /* + * Computes: +- * a0 = &new_vmalloc[BIT_WORD(cpu)] ++ * a0 = &new_valid_map_cpus[BIT_WORD(cpu)] + * a1 = BIT_MASK(cpu) + */ + lw a2, TASK_TI_CPU(tp) + /* +- * Compute the new_vmalloc element position: ++ * Compute the new_valid_map_cpus element position: + * (cpu / 64) * 8 = (cpu >> 6) << 3 + */ + srli a1, a2, 6 + slli a1, a1, 3 +- la a0, new_vmalloc ++ la a0, new_valid_map_cpus + add a0, a0, a1 + /* +- * Compute the bit position in the new_vmalloc element: ++ * Compute the bit position in the new_valid_map_cpus element: + * bit_pos = cpu % 64 = cpu - (cpu / 64) * 64 = cpu - (cpu >> 6) << 6 + * = cpu - ((cpu >> 6) << 3) << 3 + */ +@@ -67,12 +67,12 @@ + li a2, 1 + sll a1, a2, a1 + +- /* Check the value of new_vmalloc for this cpu */ ++ /* Check the value of new_valid_map_cpus for this cpu */ + REG_L a2, 0(a0) + and a2, a2, a1 +- beq a2, zero, .Lnew_vmalloc_restore_context ++ beq a2, zero, .Lnew_valid_map_cpus_restore_context + +- /* Atomically reset the current cpu bit in new_vmalloc */ ++ /* Atomically reset the current cpu bit in new_valid_map_cpus */ + amoxor.d a0, a1, (a0) + + /* Only emit a sfence.vma if the uarch caches invalid entries */ +@@ -84,11 +84,11 @@ + csrw CSR_SCRATCH, x0 + sret + +-.Lnew_vmalloc_restore_context: ++.Lnew_valid_map_cpus_restore_context: + REG_L a2, TASK_TI_A2(tp) +-.Lnew_vmalloc_restore_context_a1: ++.Lnew_valid_map_cpus_restore_context_a1: + REG_L a1, TASK_TI_A1(tp) +-.Lnew_vmalloc_restore_context_a0: ++.Lnew_valid_map_cpus_restore_context_a0: + REG_L a0, TASK_TI_A0(tp) + .endm + +@@ -146,7 +146,7 @@ SYM_CODE_START(handle_exception) + * could "miss" the new mapping and traps: in that case, we only need + * to retry the access, no sfence.vma is required. + */ +- new_vmalloc_check ++ new_valid_map_cpus_check + #endif + + REG_S sp, TASK_TI_KERNEL_SP(tp) +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index 31007b426d54..dca35a331c0f 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -37,7 +37,7 @@ + + #include "../kernel/head.h" + +-u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; ++u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; + + struct kernel_mapping kernel_map __ro_after_init; + EXPORT_SYMBOL(kernel_map); +-- +2.53.0 + diff --git a/SPECS/linux/0125-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch b/SPECS/linux/0125-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch deleted file mode 100644 index 893a4ae540..0000000000 --- a/SPECS/linux/0125-FROMLIST-riscv-mm-Rename-new_vmalloc-into-new_valid_.patch +++ /dev/null @@ -1,162 +0,0 @@ -From 7d70e3532028f70ac125619d349c917ab7ff7923 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:47 +0800 -Subject: [PATCH 125/269] FROMLIST: riscv: mm: Rename new_vmalloc into - new_valid_map_cpus - -Since this mechanism is now used for the kfence pool, which comes from -the linear mapping and not vmalloc, rename new_vmalloc into -new_valid_map_cpus to avoid misleading readers. - -No functional change intended. - -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-3-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/cacheflush.h | 6 ++--- - arch/riscv/kernel/entry.S | 38 ++++++++++++++--------------- - arch/riscv/mm/init.c | 2 +- - 3 files changed, 23 insertions(+), 23 deletions(-) - -diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h -index b1a2ac665792..8c7a0ef2635a 100644 ---- a/arch/riscv/include/asm/cacheflush.h -+++ b/arch/riscv/include/asm/cacheflush.h -@@ -41,7 +41,7 @@ do { \ - } while (0) - - #ifdef CONFIG_64BIT --extern u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; -+extern u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; - extern char _end[]; - static inline void mark_new_valid_map(void) - { -@@ -52,8 +52,8 @@ static inline void mark_new_valid_map(void) - * the only place this can happen is in handle_exception() where - * an sfence.vma is emitted. - */ -- for (i = 0; i < ARRAY_SIZE(new_vmalloc); ++i) -- new_vmalloc[i] = -1ULL; -+ for (i = 0; i < ARRAY_SIZE(new_valid_map_cpus); ++i) -+ new_valid_map_cpus[i] = -1ULL; - } - #define flush_cache_vmap flush_cache_vmap - static inline void flush_cache_vmap(unsigned long start, unsigned long end) -diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S -index ced7a2b160ce..9c6acfd09141 100644 ---- a/arch/riscv/kernel/entry.S -+++ b/arch/riscv/kernel/entry.S -@@ -20,44 +20,44 @@ - - .section .irqentry.text, "ax" - --.macro new_vmalloc_check -+.macro new_valid_map_cpus_check - REG_S a0, TASK_TI_A0(tp) - csrr a0, CSR_CAUSE - /* Exclude IRQs */ -- blt a0, zero, .Lnew_vmalloc_restore_context_a0 -+ blt a0, zero, .Lnew_valid_map_cpus_restore_context_a0 - - REG_S a1, TASK_TI_A1(tp) -- /* Only check new_vmalloc if we are in page/protection fault */ -+ /* Only check new_valid_map_cpus if we are in page/protection fault */ - li a1, EXC_LOAD_PAGE_FAULT -- beq a0, a1, .Lnew_vmalloc_kernel_address -+ beq a0, a1, .Lnew_valid_map_cpus_kernel_address - li a1, EXC_STORE_PAGE_FAULT -- beq a0, a1, .Lnew_vmalloc_kernel_address -+ beq a0, a1, .Lnew_valid_map_cpus_kernel_address - li a1, EXC_INST_PAGE_FAULT -- bne a0, a1, .Lnew_vmalloc_restore_context_a1 -+ bne a0, a1, .Lnew_valid_map_cpus_restore_context_a1 - --.Lnew_vmalloc_kernel_address: -+.Lnew_valid_map_cpus_kernel_address: - /* Is it a kernel address? */ - csrr a0, CSR_TVAL -- bge a0, zero, .Lnew_vmalloc_restore_context_a1 -+ bge a0, zero, .Lnew_valid_map_cpus_restore_context_a1 - - /* Check if a new vmalloc mapping appeared that could explain the trap */ - REG_S a2, TASK_TI_A2(tp) - /* - * Computes: -- * a0 = &new_vmalloc[BIT_WORD(cpu)] -+ * a0 = &new_valid_map_cpus[BIT_WORD(cpu)] - * a1 = BIT_MASK(cpu) - */ - lw a2, TASK_TI_CPU(tp) - /* -- * Compute the new_vmalloc element position: -+ * Compute the new_valid_map_cpus element position: - * (cpu / 64) * 8 = (cpu >> 6) << 3 - */ - srli a1, a2, 6 - slli a1, a1, 3 -- la a0, new_vmalloc -+ la a0, new_valid_map_cpus - add a0, a0, a1 - /* -- * Compute the bit position in the new_vmalloc element: -+ * Compute the bit position in the new_valid_map_cpus element: - * bit_pos = cpu % 64 = cpu - (cpu / 64) * 64 = cpu - (cpu >> 6) << 6 - * = cpu - ((cpu >> 6) << 3) << 3 - */ -@@ -67,12 +67,12 @@ - li a2, 1 - sll a1, a2, a1 - -- /* Check the value of new_vmalloc for this cpu */ -+ /* Check the value of new_valid_map_cpus for this cpu */ - REG_L a2, 0(a0) - and a2, a2, a1 -- beq a2, zero, .Lnew_vmalloc_restore_context -+ beq a2, zero, .Lnew_valid_map_cpus_restore_context - -- /* Atomically reset the current cpu bit in new_vmalloc */ -+ /* Atomically reset the current cpu bit in new_valid_map_cpus */ - amoxor.d a0, a1, (a0) - - /* Only emit a sfence.vma if the uarch caches invalid entries */ -@@ -84,11 +84,11 @@ - csrw CSR_SCRATCH, x0 - sret - --.Lnew_vmalloc_restore_context: -+.Lnew_valid_map_cpus_restore_context: - REG_L a2, TASK_TI_A2(tp) --.Lnew_vmalloc_restore_context_a1: -+.Lnew_valid_map_cpus_restore_context_a1: - REG_L a1, TASK_TI_A1(tp) --.Lnew_vmalloc_restore_context_a0: -+.Lnew_valid_map_cpus_restore_context_a0: - REG_L a0, TASK_TI_A0(tp) - .endm - -@@ -146,7 +146,7 @@ SYM_CODE_START(handle_exception) - * could "miss" the new mapping and traps: in that case, we only need - * to retry the access, no sfence.vma is required. - */ -- new_vmalloc_check -+ new_valid_map_cpus_check - #endif - - REG_S sp, TASK_TI_KERNEL_SP(tp) -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index 31007b426d54..dca35a331c0f 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -37,7 +37,7 @@ - - #include "../kernel/head.h" - --u64 new_vmalloc[NR_CPUS / sizeof(u64) + 1]; -+u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; - - struct kernel_mapping kernel_map __ro_after_init; - EXPORT_SYMBOL(kernel_map); --- -2.53.0 - diff --git a/SPECS/linux/0125-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch b/SPECS/linux/0125-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch new file mode 100644 index 0000000000..95bccdf8bd --- /dev/null +++ b/SPECS/linux/0125-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch @@ -0,0 +1,61 @@ +From 9eb13102c442bf93088b8ac5680c9032b0848510 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 13:29:48 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Use the bitmap API for + new_valid_map_cpus + +The bitmap was defined with incorrect size. Fix it by using the proper +bitmap API in C code. The corresponding assembly code is still okay and +remains unchanged. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-4-f80d8354d79d@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/cacheflush.h | 8 +++----- + arch/riscv/mm/init.c | 2 +- + 2 files changed, 4 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h +index 8c7a0ef2635a..8cfe59483a8f 100644 +--- a/arch/riscv/include/asm/cacheflush.h ++++ b/arch/riscv/include/asm/cacheflush.h +@@ -41,19 +41,17 @@ do { \ + } while (0) + + #ifdef CONFIG_64BIT +-extern u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; ++/* This is accessed in assembly code. cpumask_var_t would be too complex. */ ++extern DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); + extern char _end[]; + static inline void mark_new_valid_map(void) + { +- int i; +- + /* + * We don't care if concurrently a cpu resets this value since + * the only place this can happen is in handle_exception() where + * an sfence.vma is emitted. + */ +- for (i = 0; i < ARRAY_SIZE(new_valid_map_cpus); ++i) +- new_valid_map_cpus[i] = -1ULL; ++ bitmap_fill(new_valid_map_cpus, NR_CPUS); + } + #define flush_cache_vmap flush_cache_vmap + static inline void flush_cache_vmap(unsigned long start, unsigned long end) +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index dca35a331c0f..985e496313c8 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -37,7 +37,7 @@ + + #include "../kernel/head.h" + +-u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; ++DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); + + struct kernel_mapping kernel_map __ro_after_init; + EXPORT_SYMBOL(kernel_map); +-- +2.53.0 + diff --git a/SPECS/linux/0126-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch b/SPECS/linux/0126-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch new file mode 100644 index 0000000000..590f90547d --- /dev/null +++ b/SPECS/linux/0126-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch @@ -0,0 +1,44 @@ +From 713703016771c386212d26118b4866a02b2514aa Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Tue, 3 Mar 2026 13:29:49 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Unconditionally sfence.vma for + spurious fault + +Svvptc does not guarantee that it's safe to just return here. Since we +have already cleared our bit, if, theoretically, the bounded timeframe +for the accessed page to become valid still hasn't happened after sret, +we could fault again and actually crash. + +Hopefully, these spurious faults should be rare enough that this is an +acceptable slowdown. + +Cc: stable@vger.kernel.org +Fixes: 503638e0babf ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings") +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-5-f80d8354d79d@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/kernel/entry.S | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S +index 9c6acfd09141..34717bd1fa91 100644 +--- a/arch/riscv/kernel/entry.S ++++ b/arch/riscv/kernel/entry.S +@@ -75,8 +75,11 @@ + /* Atomically reset the current cpu bit in new_valid_map_cpus */ + amoxor.d a0, a1, (a0) + +- /* Only emit a sfence.vma if the uarch caches invalid entries */ +- ALTERNATIVE("sfence.vma", "nop", 0, RISCV_ISA_EXT_SVVPTC, 1) ++ /* ++ * A sfence.vma is required here. Even if we had Svvptc, there's no ++ * guarantee that after returning we wouldn't just fault again. ++ */ ++ sfence.vma + + REG_L a0, TASK_TI_A0(tp) + REG_L a1, TASK_TI_A1(tp) +-- +2.53.0 + diff --git a/SPECS/linux/0126-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch b/SPECS/linux/0126-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch deleted file mode 100644 index f1c4af4d8a..0000000000 --- a/SPECS/linux/0126-FROMLIST-riscv-mm-Use-the-bitmap-API-for-new_valid_m.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 07319b14298d9f2641ea664cab0933b8c7fca581 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:48 +0800 -Subject: [PATCH 126/269] FROMLIST: riscv: mm: Use the bitmap API for - new_valid_map_cpus - -The bitmap was defined with incorrect size. Fix it by using the proper -bitmap API in C code. The corresponding assembly code is still okay and -remains unchanged. - -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-4-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/cacheflush.h | 8 +++----- - arch/riscv/mm/init.c | 2 +- - 2 files changed, 4 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h -index 8c7a0ef2635a..8cfe59483a8f 100644 ---- a/arch/riscv/include/asm/cacheflush.h -+++ b/arch/riscv/include/asm/cacheflush.h -@@ -41,19 +41,17 @@ do { \ - } while (0) - - #ifdef CONFIG_64BIT --extern u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; -+/* This is accessed in assembly code. cpumask_var_t would be too complex. */ -+extern DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); - extern char _end[]; - static inline void mark_new_valid_map(void) - { -- int i; -- - /* - * We don't care if concurrently a cpu resets this value since - * the only place this can happen is in handle_exception() where - * an sfence.vma is emitted. - */ -- for (i = 0; i < ARRAY_SIZE(new_valid_map_cpus); ++i) -- new_valid_map_cpus[i] = -1ULL; -+ bitmap_fill(new_valid_map_cpus, NR_CPUS); - } - #define flush_cache_vmap flush_cache_vmap - static inline void flush_cache_vmap(unsigned long start, unsigned long end) -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index dca35a331c0f..985e496313c8 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -37,7 +37,7 @@ - - #include "../kernel/head.h" - --u64 new_valid_map_cpus[NR_CPUS / sizeof(u64) + 1]; -+DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS); - - struct kernel_mapping kernel_map __ro_after_init; - EXPORT_SYMBOL(kernel_map); --- -2.53.0 - diff --git a/SPECS/linux/0127-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch b/SPECS/linux/0127-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch new file mode 100644 index 0000000000..ec049f6b61 --- /dev/null +++ b/SPECS/linux/0127-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch @@ -0,0 +1,44 @@ +From 0a4410e39c44fa731ee3b176d1d428524ae04483 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 5 Mar 2026 01:00:51 +0000 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: spacemit: k3: add USB2 PHY + support + +Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP +of USB2 PHY mostly shares the same functionalities with K1 SoC, while has +some register layout changes. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260305-11-k3-usb2-phy-v4-1-15554fb933bc@kernel.org +Signed-off-by: Han Gao +--- + .../devicetree/bindings/phy/spacemit,usb2-phy.yaml | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml +index 43eaca90d88c..18025e5f60d6 100644 +--- a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml ++++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml +@@ -4,14 +4,16 @@ + $id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# + +-title: SpacemiT K1 SoC USB 2.0 PHY ++title: SpacemiT K1/K3 SoC USB 2.0 PHY + + maintainers: + - Ze Huang + + properties: + compatible: +- const: spacemit,k1-usb2-phy ++ enum: ++ - spacemit,k1-usb2-phy ++ - spacemit,k3-usb2-phy + + reg: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux/0127-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch b/SPECS/linux/0127-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch deleted file mode 100644 index 430b0c3907..0000000000 --- a/SPECS/linux/0127-FROMLIST-riscv-mm-Unconditionally-sfence.vma-for-spu.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 3c479e3b1dd3b20319a72b8ae77846c27af6c57c Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Tue, 3 Mar 2026 13:29:49 +0800 -Subject: [PATCH 127/269] FROMLIST: riscv: mm: Unconditionally sfence.vma for - spurious fault - -Svvptc does not guarantee that it's safe to just return here. Since we -have already cleared our bit, if, theoretically, the bounded timeframe -for the accessed page to become valid still hasn't happened after sret, -we could fault again and actually crash. - -Hopefully, these spurious faults should be rare enough that this is an -acceptable slowdown. - -Cc: stable@vger.kernel.org -Fixes: 503638e0babf ("riscv: Stop emitting preventive sfence.vma for new vmalloc mappings") -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260303-handle-kfence-protect-spurious-fault-v2-5-f80d8354d79d@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/kernel/entry.S | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S -index 9c6acfd09141..34717bd1fa91 100644 ---- a/arch/riscv/kernel/entry.S -+++ b/arch/riscv/kernel/entry.S -@@ -75,8 +75,11 @@ - /* Atomically reset the current cpu bit in new_valid_map_cpus */ - amoxor.d a0, a1, (a0) - -- /* Only emit a sfence.vma if the uarch caches invalid entries */ -- ALTERNATIVE("sfence.vma", "nop", 0, RISCV_ISA_EXT_SVVPTC, 1) -+ /* -+ * A sfence.vma is required here. Even if we had Svvptc, there's no -+ * guarantee that after returning we wouldn't just fault again. -+ */ -+ sfence.vma - - REG_L a0, TASK_TI_A0(tp) - REG_L a1, TASK_TI_A1(tp) --- -2.53.0 - diff --git a/SPECS/linux/0128-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch b/SPECS/linux/0128-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch deleted file mode 100644 index a87ce87af7..0000000000 --- a/SPECS/linux/0128-FROMLIST-dt-bindings-phy-spacemit-k3-add-USB2-PHY-su.patch +++ /dev/null @@ -1,44 +0,0 @@ -From ee591c3164cc4cd6e943c01fed1b7516d3115c01 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 5 Mar 2026 01:00:51 +0000 -Subject: [PATCH 128/269] FROMLIST: dt-bindings: phy: spacemit: k3: add USB2 - PHY support - -Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP -of USB2 PHY mostly shares the same functionalities with K1 SoC, while has -some register layout changes. - -Acked-by: Krzysztof Kozlowski -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260305-11-k3-usb2-phy-v4-1-15554fb933bc@kernel.org -Signed-off-by: Han Gao ---- - .../devicetree/bindings/phy/spacemit,usb2-phy.yaml | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -index 43eaca90d88c..18025e5f60d6 100644 ---- a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -+++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml -@@ -4,14 +4,16 @@ - $id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# - $schema: http://devicetree.org/meta-schemas/core.yaml# - --title: SpacemiT K1 SoC USB 2.0 PHY -+title: SpacemiT K1/K3 SoC USB 2.0 PHY - - maintainers: - - Ze Huang - - properties: - compatible: -- const: spacemit,k1-usb2-phy -+ enum: -+ - spacemit,k1-usb2-phy -+ - spacemit,k3-usb2-phy - - reg: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux/0128-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch b/SPECS/linux/0128-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch new file mode 100644 index 0000000000..92a0f38e70 --- /dev/null +++ b/SPECS/linux/0128-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch @@ -0,0 +1,109 @@ +From 5dca9dff6d2cb4e3926899a0fc5f2b33df7bee2d Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 5 Mar 2026 01:00:52 +0000 +Subject: [RUYI PATCH] FROMLIST: phy: k1-usb: k3: add USB2 PHY support + +Add USB2 PHY support for SpacemiT K3 SoC. + +Register layout of handling USB disconnect operation has been changed, +So introducing a platform data to distinguish the different SoCs. + +Reviewed-by: Yao Zi +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260305-11-k3-usb2-phy-v4-2-15554fb933bc@kernel.org +Signed-off-by: Han Gao +--- + drivers/phy/spacemit/phy-k1-usb2.c | 34 +++++++++++++++++++++++++----- + 1 file changed, 29 insertions(+), 5 deletions(-) + +diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c +index e8c1e26428a9..8df12eeb20b1 100644 +--- a/drivers/phy/spacemit/phy-k1-usb2.c ++++ b/drivers/phy/spacemit/phy-k1-usb2.c +@@ -51,6 +51,9 @@ + #define PHY_K1_HS_HOST_DISC 0x40 + #define PHY_K1_HS_HOST_DISC_CLR BIT(0) + ++#define PHY_K3_HS_HOST_DISC 0x20 ++#define PHY_K3_HS_HOST_DISC_CLR BIT(8) ++ + #define PHY_PLL_DIV_CFG 0x98 + #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) + #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) +@@ -144,7 +147,7 @@ static int spacemit_usb2phy_exit(struct phy *phy) + return 0; + } + +-static int spacemit_usb2phy_disconnect(struct phy *phy, int port) ++static int spacemit_k1_usb2phy_disconnect(struct phy *phy, int port) + { + struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); + +@@ -154,10 +157,27 @@ static int spacemit_usb2phy_disconnect(struct phy *phy, int port) + return 0; + } + +-static const struct phy_ops spacemit_usb2phy_ops = { ++static int spacemit_k3_usb2phy_disconnect(struct phy *phy, int port) ++{ ++ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); ++ ++ regmap_update_bits(sphy->regmap_base, PHY_K3_HS_HOST_DISC, ++ PHY_K3_HS_HOST_DISC_CLR, PHY_K3_HS_HOST_DISC_CLR); ++ ++ return 0; ++} ++ ++static const struct phy_ops spacemit_k1_usb2phy_ops = { + .init = spacemit_usb2phy_init, + .exit = spacemit_usb2phy_exit, +- .disconnect = spacemit_usb2phy_disconnect, ++ .disconnect = spacemit_k1_usb2phy_disconnect, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct phy_ops spacemit_k3_usb2phy_ops = { ++ .init = spacemit_usb2phy_init, ++ .exit = spacemit_usb2phy_exit, ++ .disconnect = spacemit_k3_usb2phy_disconnect, + .owner = THIS_MODULE, + }; + +@@ -166,12 +186,15 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct spacemit_usb2phy *sphy; ++ const struct phy_ops *ops; + void __iomem *base; + + sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); + if (!sphy) + return -ENOMEM; + ++ ops = device_get_match_data(dev); ++ + sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL); + if (IS_ERR(sphy->clk)) + return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); +@@ -184,7 +207,7 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) + if (IS_ERR(sphy->regmap_base)) + return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n"); + +- sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops); ++ sphy->phy = devm_phy_create(dev, NULL, ops); + if (IS_ERR(sphy->phy)) + return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); + +@@ -195,7 +218,8 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) + } + + static const struct of_device_id spacemit_usb2phy_dt_match[] = { +- { .compatible = "spacemit,k1-usb2-phy", }, ++ { .compatible = "spacemit,k1-usb2-phy", .data = &spacemit_k1_usb2phy_ops }, ++ { .compatible = "spacemit,k3-usb2-phy", .data = &spacemit_k3_usb2phy_ops }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); +-- +2.53.0 + diff --git a/SPECS/linux/0129-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch b/SPECS/linux/0129-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch new file mode 100644 index 0000000000..34edf00e47 --- /dev/null +++ b/SPECS/linux/0129-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch @@ -0,0 +1,31 @@ +From e204510910d0cbedbec37ecd9f005f0ea7e8a48c Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Fri, 10 Apr 2026 15:58:22 +0800 +Subject: [RUYI PATCH] FROMLIST: cpufreq: dt-platdev: Add SpacemiT K1 SoC to + the allowlist + +The SpacemiT K1 SoC uses standard device tree based CPU frequency +scaling. Add it to the allowlist to instantiate the cpufreq-dt driver. + +Signed-off-by: Shuwei Wu +Link: https://lore.kernel.org/r/20260410-shadow-deps-v2-1-4e16b8c0f60e@mailbox.org +Signed-off-by: Han Gao +--- + drivers/cpufreq/cpufreq-dt-platdev.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c +index 25fd3b191b7e..31a64739df25 100644 +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -81,6 +81,7 @@ static const struct of_device_id allowlist[] __initconst = { + { .have_governor_per_policy = true, }, + }, + ++ { .compatible = "spacemit,k1", }, + { .compatible = "st-ericsson,u8500", }, + { .compatible = "st-ericsson,u8540", }, + { .compatible = "st-ericsson,u9500", }, +-- +2.53.0 + diff --git a/SPECS/linux/0129-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch b/SPECS/linux/0129-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch deleted file mode 100644 index 30dfa51538..0000000000 --- a/SPECS/linux/0129-FROMLIST-phy-k1-usb-k3-add-USB2-PHY-support.patch +++ /dev/null @@ -1,109 +0,0 @@ -From d5d54543f300e7133c1defa99cb41ba372e43044 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 5 Mar 2026 01:00:52 +0000 -Subject: [PATCH 129/269] FROMLIST: phy: k1-usb: k3: add USB2 PHY support - -Add USB2 PHY support for SpacemiT K3 SoC. - -Register layout of handling USB disconnect operation has been changed, -So introducing a platform data to distinguish the different SoCs. - -Reviewed-by: Yao Zi -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260305-11-k3-usb2-phy-v4-2-15554fb933bc@kernel.org -Signed-off-by: Han Gao ---- - drivers/phy/spacemit/phy-k1-usb2.c | 34 +++++++++++++++++++++++++----- - 1 file changed, 29 insertions(+), 5 deletions(-) - -diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c -index 9215d0b223b2..87b943d9111f 100644 ---- a/drivers/phy/spacemit/phy-k1-usb2.c -+++ b/drivers/phy/spacemit/phy-k1-usb2.c -@@ -51,6 +51,9 @@ - #define PHY_K1_HS_HOST_DISC 0x40 - #define PHY_K1_HS_HOST_DISC_CLR BIT(0) - -+#define PHY_K3_HS_HOST_DISC 0x20 -+#define PHY_K3_HS_HOST_DISC_CLR BIT(8) -+ - #define PHY_PLL_DIV_CFG 0x98 - #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0) - #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8) -@@ -145,7 +148,7 @@ static int spacemit_usb2phy_exit(struct phy *phy) - return 0; - } - --static int spacemit_usb2phy_disconnect(struct phy *phy, int port) -+static int spacemit_k1_usb2phy_disconnect(struct phy *phy, int port) - { - struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); - -@@ -155,10 +158,27 @@ static int spacemit_usb2phy_disconnect(struct phy *phy, int port) - return 0; - } - --static const struct phy_ops spacemit_usb2phy_ops = { -+static int spacemit_k3_usb2phy_disconnect(struct phy *phy, int port) -+{ -+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy); -+ -+ regmap_update_bits(sphy->regmap_base, PHY_K3_HS_HOST_DISC, -+ PHY_K3_HS_HOST_DISC_CLR, PHY_K3_HS_HOST_DISC_CLR); -+ -+ return 0; -+} -+ -+static const struct phy_ops spacemit_k1_usb2phy_ops = { - .init = spacemit_usb2phy_init, - .exit = spacemit_usb2phy_exit, -- .disconnect = spacemit_usb2phy_disconnect, -+ .disconnect = spacemit_k1_usb2phy_disconnect, -+ .owner = THIS_MODULE, -+}; -+ -+static const struct phy_ops spacemit_k3_usb2phy_ops = { -+ .init = spacemit_usb2phy_init, -+ .exit = spacemit_usb2phy_exit, -+ .disconnect = spacemit_k3_usb2phy_disconnect, - .owner = THIS_MODULE, - }; - -@@ -167,12 +187,15 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) - struct phy_provider *phy_provider; - struct device *dev = &pdev->dev; - struct spacemit_usb2phy *sphy; -+ const struct phy_ops *ops; - void __iomem *base; - - sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); - if (!sphy) - return -ENOMEM; - -+ ops = device_get_match_data(dev); -+ - sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL); - if (IS_ERR(sphy->clk)) - return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n"); -@@ -185,7 +208,7 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) - if (IS_ERR(sphy->regmap_base)) - return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n"); - -- sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops); -+ sphy->phy = devm_phy_create(dev, NULL, ops); - if (IS_ERR(sphy->phy)) - return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n"); - -@@ -196,7 +219,8 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev) - } - - static const struct of_device_id spacemit_usb2phy_dt_match[] = { -- { .compatible = "spacemit,k1-usb2-phy", }, -+ { .compatible = "spacemit,k1-usb2-phy", .data = &spacemit_k1_usb2phy_ops }, -+ { .compatible = "spacemit,k3-usb2-phy", .data = &spacemit_k3_usb2phy_ops }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match); --- -2.53.0 - diff --git a/SPECS/linux/0130-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch b/SPECS/linux/0130-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch deleted file mode 100644 index 20096dcf1a..0000000000 --- a/SPECS/linux/0130-FROMLIST-cpufreq-dt-platdev-Add-SpacemiT-K1-SoC-to-t.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 93260e630e5f737d66d521e03ffe4164195b9c19 Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Fri, 10 Apr 2026 15:58:22 +0800 -Subject: [PATCH 130/269] FROMLIST: cpufreq: dt-platdev: Add SpacemiT K1 SoC to - the allowlist - -The SpacemiT K1 SoC uses standard device tree based CPU frequency -scaling. Add it to the allowlist to instantiate the cpufreq-dt driver. - -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260410-shadow-deps-v2-1-4e16b8c0f60e@mailbox.org -Signed-off-by: Han Gao ---- - drivers/cpufreq/cpufreq-dt-platdev.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c -index 25fd3b191b7e..31a64739df25 100644 ---- a/drivers/cpufreq/cpufreq-dt-platdev.c -+++ b/drivers/cpufreq/cpufreq-dt-platdev.c -@@ -81,6 +81,7 @@ static const struct of_device_id allowlist[] __initconst = { - { .have_governor_per_policy = true, }, - }, - -+ { .compatible = "spacemit,k1", }, - { .compatible = "st-ericsson,u8500", }, - { .compatible = "st-ericsson,u8540", }, - { .compatible = "st-ericsson,u9500", }, --- -2.53.0 - diff --git a/SPECS/linux/0130-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch b/SPECS/linux/0130-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch new file mode 100644 index 0000000000..c5dd599ec4 --- /dev/null +++ b/SPECS/linux/0130-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch @@ -0,0 +1,264 @@ +From 6ff0bd0a75092fcbda5aa2dea35243a387189529 Mon Sep 17 00:00:00 2001 +From: Shuwei Wu +Date: Fri, 10 Apr 2026 15:58:23 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add cpu scaling for K1 + SoC + +Add Operating Performance Points (OPP) tables and CPU clock properties +for the two clusters in the SpacemiT K1 SoC. + +Also assign the CPU power supply (cpu-supply) for the Banana Pi BPI-F3 +board to fully enable CPU DVFS. + +Signed-off-by: Shuwei Wu +Link: https://lore.kernel.org/r/20260410-shadow-deps-v2-2-4e16b8c0f60e@mailbox.org +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 35 +++++- + arch/riscv/boot/dts/spacemit/k1-opp.dtsi | 105 ++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++ + 3 files changed, 147 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/spacemit/k1-opp.dtsi + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 9429189354d6..2a0caecd9a41 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -5,6 +5,7 @@ + + #include "k1.dtsi" + #include "k1-pinctrl.dtsi" ++#include "k1-opp.dtsi" + + / { + model = "Banana Pi BPI-F3"; +@@ -85,6 +86,38 @@ &combo_phy { + status = "okay"; + }; + ++&cpu_0 { ++ cpu-supply = <&buck1_3v45>; ++}; ++ ++&cpu_1 { ++ cpu-supply = <&buck1_3v45>; ++}; ++ ++&cpu_2 { ++ cpu-supply = <&buck1_3v45>; ++}; ++ ++&cpu_3 { ++ cpu-supply = <&buck1_3v45>; ++}; ++ ++&cpu_4 { ++ cpu-supply = <&buck1_3v45>; ++}; ++ ++&cpu_5 { ++ cpu-supply = <&buck1_3v45>; ++}; ++ ++&cpu_6 { ++ cpu-supply = <&buck1_3v45>; ++}; ++ ++&cpu_7 { ++ cpu-supply = <&buck1_3v45>; ++}; ++ + &emmc { + bus-width = <8>; + mmc-hs400-1_8v; +@@ -200,7 +233,7 @@ pmic@41 { + dldoin2-supply = <&buck5>; + + regulators { +- buck1 { ++ buck1_3v45: buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-opp.dtsi b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi +new file mode 100644 +index 000000000000..768ae390686d +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi +@@ -0,0 +1,105 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/ { ++ cluster0_opp_table: opp-table-cluster0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-614400000 { ++ opp-hz = /bits/ 64 <614400000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-819000000 { ++ opp-hz = /bits/ 64 <819000000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1228800000 { ++ opp-hz = /bits/ 64 <1228800000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1600000000 { ++ opp-hz = /bits/ 64 <1600000000>; ++ opp-microvolt = <1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ }; ++ ++ cluster1_opp_table: opp-table-cluster1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-614400000 { ++ opp-hz = /bits/ 64 <614400000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-819000000 { ++ opp-hz = /bits/ 64 <819000000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1228800000 { ++ opp-hz = /bits/ 64 <1228800000>; ++ opp-microvolt = <950000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1600000000 { ++ opp-hz = /bits/ 64 <1600000000>; ++ opp-microvolt = <1050000>; ++ clock-latency-ns = <200000>; ++ }; ++ }; ++}; ++ ++&cpu_0 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_1 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_2 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_3 { ++ operating-points-v2 = <&cluster0_opp_table>; ++}; ++ ++&cpu_4 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_5 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_6 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; ++ ++&cpu_7 { ++ operating-points-v2 = <&cluster1_opp_table>; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 2ed5cc24e505..aefdbbadc9ef 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -54,6 +54,7 @@ cpu_0: cpu@0 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <0>; ++ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -84,6 +85,7 @@ cpu_1: cpu@1 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <1>; ++ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -114,6 +116,7 @@ cpu_2: cpu@2 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <2>; ++ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -144,6 +147,7 @@ cpu_3: cpu@3 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <3>; ++ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -174,6 +178,7 @@ cpu_4: cpu@4 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <4>; ++ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -204,6 +209,7 @@ cpu_5: cpu@5 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <5>; ++ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -234,6 +240,7 @@ cpu_6: cpu@6 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <6>; ++ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +@@ -264,6 +271,7 @@ cpu_7: cpu@7 { + compatible = "spacemit,x60", "riscv"; + device_type = "cpu"; + reg = <7>; ++ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", +-- +2.53.0 + diff --git a/SPECS/linux/0131-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch b/SPECS/linux/0131-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch deleted file mode 100644 index c21481600e..0000000000 --- a/SPECS/linux/0131-FROMLIST-riscv-dts-spacemit-Add-cpu-scaling-for-K1-S.patch +++ /dev/null @@ -1,264 +0,0 @@ -From 1c542475e77927275f0b16032bcff2f190fdf824 Mon Sep 17 00:00:00 2001 -From: Shuwei Wu -Date: Fri, 10 Apr 2026 15:58:23 +0800 -Subject: [PATCH 131/269] FROMLIST: riscv: dts: spacemit: Add cpu scaling for - K1 SoC - -Add Operating Performance Points (OPP) tables and CPU clock properties -for the two clusters in the SpacemiT K1 SoC. - -Also assign the CPU power supply (cpu-supply) for the Banana Pi BPI-F3 -board to fully enable CPU DVFS. - -Signed-off-by: Shuwei Wu -Link: https://lore.kernel.org/r/20260410-shadow-deps-v2-2-4e16b8c0f60e@mailbox.org -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 35 +++++- - arch/riscv/boot/dts/spacemit/k1-opp.dtsi | 105 ++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++ - 3 files changed, 147 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/spacemit/k1-opp.dtsi - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 9429189354d6..2a0caecd9a41 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -5,6 +5,7 @@ - - #include "k1.dtsi" - #include "k1-pinctrl.dtsi" -+#include "k1-opp.dtsi" - - / { - model = "Banana Pi BPI-F3"; -@@ -85,6 +86,38 @@ &combo_phy { - status = "okay"; - }; - -+&cpu_0 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_1 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_2 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_3 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_4 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_5 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_6 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ -+&cpu_7 { -+ cpu-supply = <&buck1_3v45>; -+}; -+ - &emmc { - bus-width = <8>; - mmc-hs400-1_8v; -@@ -200,7 +233,7 @@ pmic@41 { - dldoin2-supply = <&buck5>; - - regulators { -- buck1 { -+ buck1_3v45: buck1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; - regulator-ramp-delay = <5000>; -diff --git a/arch/riscv/boot/dts/spacemit/k1-opp.dtsi b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi -new file mode 100644 -index 000000000000..768ae390686d ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi -@@ -0,0 +1,105 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/ { -+ cluster0_opp_table: opp-table-cluster0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-614400000 { -+ opp-hz = /bits/ 64 <614400000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-819000000 { -+ opp-hz = /bits/ 64 <819000000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1228800000 { -+ opp-hz = /bits/ 64 <1228800000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1600000000 { -+ opp-hz = /bits/ 64 <1600000000>; -+ opp-microvolt = <1050000>; -+ clock-latency-ns = <200000>; -+ }; -+ }; -+ -+ cluster1_opp_table: opp-table-cluster1 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-614400000 { -+ opp-hz = /bits/ 64 <614400000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-819000000 { -+ opp-hz = /bits/ 64 <819000000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1228800000 { -+ opp-hz = /bits/ 64 <1228800000>; -+ opp-microvolt = <950000>; -+ clock-latency-ns = <200000>; -+ }; -+ -+ opp-1600000000 { -+ opp-hz = /bits/ 64 <1600000000>; -+ opp-microvolt = <1050000>; -+ clock-latency-ns = <200000>; -+ }; -+ }; -+}; -+ -+&cpu_0 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_1 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_2 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_3 { -+ operating-points-v2 = <&cluster0_opp_table>; -+}; -+ -+&cpu_4 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_5 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_6 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -+ -+&cpu_7 { -+ operating-points-v2 = <&cluster1_opp_table>; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 2ed5cc24e505..aefdbbadc9ef 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -54,6 +54,7 @@ cpu_0: cpu@0 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <0>; -+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -84,6 +85,7 @@ cpu_1: cpu@1 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <1>; -+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -114,6 +116,7 @@ cpu_2: cpu@2 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <2>; -+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -144,6 +147,7 @@ cpu_3: cpu@3 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <3>; -+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -174,6 +178,7 @@ cpu_4: cpu@4 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <4>; -+ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -204,6 +209,7 @@ cpu_5: cpu@5 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <5>; -+ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -234,6 +240,7 @@ cpu_6: cpu@6 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <6>; -+ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", -@@ -264,6 +271,7 @@ cpu_7: cpu@7 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <7>; -+ clocks = <&syscon_apmu CLK_CPU_C1_CORE>; - riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", --- -2.53.0 - diff --git a/SPECS/linux/0131-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch b/SPECS/linux/0131-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch new file mode 100644 index 0000000000..d1474576e1 --- /dev/null +++ b/SPECS/linux/0131-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch @@ -0,0 +1,47 @@ +From a95c08468425de1ec00fa17e195760c6107b1ef8 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Mon, 9 Mar 2026 19:09:38 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Define DIRECT_MAP_PHYSMEM_END + +On RISC-V, the actual mappable range of physical address space is +dependent on the current MMU mode i.e. satp_mode (See +Documentation/arch/riscv/vm-layout.rst). + +Define the DIRECT_MAP_PHYSMEM_END macro based on the existing virtual +address space layout macros to expose this information to +get_free_mem_region(). Otherwise, it returns a region that couldn't be +mapped, which breaks ZONE_DEVICE. + +Cc: stable@vger.kernel.org # v6.13+ +Tested-by: Han Gao # SG2044 +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260309-riscv-sparsemem-vmemmap-limits-v1-2-f40efe18e3cd@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/pgtable.h | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h +index 08d1ca047104..9c92a84e9755 100644 +--- a/arch/riscv/include/asm/pgtable.h ++++ b/arch/riscv/include/asm/pgtable.h +@@ -93,6 +93,16 @@ + */ + #define vmemmap ((struct page *)VMEMMAP_START - vmemmap_start_pfn) + ++/* Needed to limit get_free_mem_region() */ ++#if defined(CONFIG_FLATMEM) ++#define DIRECT_MAP_PHYSMEM_END (phys_ram_base + KERN_VIRT_SIZE - 1) ++#elif defined(CONFIG_SPARSEMEM_VMEMMAP) ++#define DIRECT_MAP_PHYSMEM_END \ ++ ((vmemmap_start_pfn + VMEMMAP_SIZE / sizeof(struct page)) * PAGE_SIZE - 1) ++#elif defined(CONFIG_SPARSEMEM) ++/* DIRECT_MAP_PHYSMEM_END is not limited by VA space assignment in this case */ ++#endif ++ + #define PCI_IO_SIZE SZ_16M + #define PCI_IO_END VMEMMAP_START + #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) +-- +2.53.0 + diff --git a/SPECS/linux/0132-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch b/SPECS/linux/0132-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch new file mode 100644 index 0000000000..902f724ce2 --- /dev/null +++ b/SPECS/linux/0132-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch @@ -0,0 +1,78 @@ +From 53c96bbf1a32cded7eaa89f038265bcac7fb85bc Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 01:56:09 +0800 +Subject: [RUYI PATCH] FROMLIST: drm: verisilicon: add max cursor size to HWDB + +Different display controller variants support different maximum cursor +size. All known DC8200 variants support both 32x32 and 64x64, but some +DC8000 variants support either only 32x32 or up to 256x256. + +The minimum size is fixed at 32 and only PoT square sizes are supported. + +Add the max cursor size field to HWDB and fill all entries with 64. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Thomas Zimmermann +Reviewed-by: Dmitry Baryshkov +Link: https://lore.kernel.org/r/20260506175610.2542888-2-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/gpu/drm/verisilicon/vs_hwdb.c | 4 ++++ + drivers/gpu/drm/verisilicon/vs_hwdb.h | 5 +++++ + 2 files changed, 9 insertions(+) + +diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisilicon/vs_hwdb.c +index 09336af0900a..2a0f7c59afa3 100644 +--- a/drivers/gpu/drm/verisilicon/vs_hwdb.c ++++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c +@@ -95,6 +95,7 @@ static struct vs_chip_identity vs_chip_identities[] = { + .customer_id = ~0U, + + .display_count = 2, ++ .max_cursor_size = 64, + .formats = &vs_formats_no_yuv444, + }, + { +@@ -103,6 +104,7 @@ static struct vs_chip_identity vs_chip_identities[] = { + .customer_id = 0x30B, + + .display_count = 2, ++ .max_cursor_size = 64, + .formats = &vs_formats_no_yuv444, + }, + { +@@ -111,6 +113,7 @@ static struct vs_chip_identity vs_chip_identities[] = { + .customer_id = 0x310, + + .display_count = 2, ++ .max_cursor_size = 64, + .formats = &vs_formats_with_yuv444, + }, + { +@@ -119,6 +122,7 @@ static struct vs_chip_identity vs_chip_identities[] = { + .customer_id = 0x311, + + .display_count = 2, ++ .max_cursor_size = 64, + .formats = &vs_formats_no_yuv444, + }, + }; +diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisilicon/vs_hwdb.h +index 92192e4fa086..2065ecb73043 100644 +--- a/drivers/gpu/drm/verisilicon/vs_hwdb.h ++++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h +@@ -20,6 +20,11 @@ struct vs_chip_identity { + u32 customer_id; + + u32 display_count; ++ /* ++ * The hardware only supports square cursor planes, so this field ++ * is both the maximum width and height in pixels. ++ */ ++ int32_t max_cursor_size; + const struct vs_formats *formats; + }; + +-- +2.53.0 + diff --git a/SPECS/linux/0132-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch b/SPECS/linux/0132-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch deleted file mode 100644 index 9f59780622..0000000000 --- a/SPECS/linux/0132-FROMLIST-riscv-mm-Define-DIRECT_MAP_PHYSMEM_END.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 053bf74ad61df8d4c2912718c964ad44be477870 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Mon, 9 Mar 2026 19:09:38 +0800 -Subject: [PATCH 132/269] FROMLIST: riscv: mm: Define DIRECT_MAP_PHYSMEM_END - -On RISC-V, the actual mappable range of physical address space is -dependent on the current MMU mode i.e. satp_mode (See -Documentation/arch/riscv/vm-layout.rst). - -Define the DIRECT_MAP_PHYSMEM_END macro based on the existing virtual -address space layout macros to expose this information to -get_free_mem_region(). Otherwise, it returns a region that couldn't be -mapped, which breaks ZONE_DEVICE. - -Cc: stable@vger.kernel.org # v6.13+ -Tested-by: Han Gao # SG2044 -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260309-riscv-sparsemem-vmemmap-limits-v1-2-f40efe18e3cd@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/pgtable.h | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h -index 08d1ca047104..9c92a84e9755 100644 ---- a/arch/riscv/include/asm/pgtable.h -+++ b/arch/riscv/include/asm/pgtable.h -@@ -93,6 +93,16 @@ - */ - #define vmemmap ((struct page *)VMEMMAP_START - vmemmap_start_pfn) - -+/* Needed to limit get_free_mem_region() */ -+#if defined(CONFIG_FLATMEM) -+#define DIRECT_MAP_PHYSMEM_END (phys_ram_base + KERN_VIRT_SIZE - 1) -+#elif defined(CONFIG_SPARSEMEM_VMEMMAP) -+#define DIRECT_MAP_PHYSMEM_END \ -+ ((vmemmap_start_pfn + VMEMMAP_SIZE / sizeof(struct page)) * PAGE_SIZE - 1) -+#elif defined(CONFIG_SPARSEMEM) -+/* DIRECT_MAP_PHYSMEM_END is not limited by VA space assignment in this case */ -+#endif -+ - #define PCI_IO_SIZE SZ_16M - #define PCI_IO_END VMEMMAP_START - #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) --- -2.53.0 - diff --git a/SPECS/linux/0133-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch b/SPECS/linux/0133-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch deleted file mode 100644 index bb7cd8254a..0000000000 --- a/SPECS/linux/0133-FROMLIST-drm-verisilicon-add-max-cursor-size-to-HWDB.patch +++ /dev/null @@ -1,79 +0,0 @@ -From ac07aeb50f9558c4545d9287c3f5da4e674a01f7 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 01:56:09 +0800 -Subject: [PATCH 133/269] FROMLIST: drm: verisilicon: add max cursor size to - HWDB - -Different display controller variants support different maximum cursor -size. All known DC8200 variants support both 32x32 and 64x64, but some -DC8000 variants support either only 32x32 or up to 256x256. - -The minimum size is fixed at 32 and only PoT square sizes are supported. - -Add the max cursor size field to HWDB and fill all entries with 64. - -Signed-off-by: Icenowy Zheng -Reviewed-by: Thomas Zimmermann -Reviewed-by: Dmitry Baryshkov -Link: https://lore.kernel.org/r/20260506175610.2542888-2-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/gpu/drm/verisilicon/vs_hwdb.c | 4 ++++ - drivers/gpu/drm/verisilicon/vs_hwdb.h | 5 +++++ - 2 files changed, 9 insertions(+) - -diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.c b/drivers/gpu/drm/verisilicon/vs_hwdb.c -index 09336af0900a..2a0f7c59afa3 100644 ---- a/drivers/gpu/drm/verisilicon/vs_hwdb.c -+++ b/drivers/gpu/drm/verisilicon/vs_hwdb.c -@@ -95,6 +95,7 @@ static struct vs_chip_identity vs_chip_identities[] = { - .customer_id = ~0U, - - .display_count = 2, -+ .max_cursor_size = 64, - .formats = &vs_formats_no_yuv444, - }, - { -@@ -103,6 +104,7 @@ static struct vs_chip_identity vs_chip_identities[] = { - .customer_id = 0x30B, - - .display_count = 2, -+ .max_cursor_size = 64, - .formats = &vs_formats_no_yuv444, - }, - { -@@ -111,6 +113,7 @@ static struct vs_chip_identity vs_chip_identities[] = { - .customer_id = 0x310, - - .display_count = 2, -+ .max_cursor_size = 64, - .formats = &vs_formats_with_yuv444, - }, - { -@@ -119,6 +122,7 @@ static struct vs_chip_identity vs_chip_identities[] = { - .customer_id = 0x311, - - .display_count = 2, -+ .max_cursor_size = 64, - .formats = &vs_formats_no_yuv444, - }, - }; -diff --git a/drivers/gpu/drm/verisilicon/vs_hwdb.h b/drivers/gpu/drm/verisilicon/vs_hwdb.h -index 92192e4fa086..2065ecb73043 100644 ---- a/drivers/gpu/drm/verisilicon/vs_hwdb.h -+++ b/drivers/gpu/drm/verisilicon/vs_hwdb.h -@@ -20,6 +20,11 @@ struct vs_chip_identity { - u32 customer_id; - - u32 display_count; -+ /* -+ * The hardware only supports square cursor planes, so this field -+ * is both the maximum width and height in pixels. -+ */ -+ int32_t max_cursor_size; - const struct vs_formats *formats; - }; - --- -2.53.0 - diff --git a/SPECS/linux/0133-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch b/SPECS/linux/0133-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch new file mode 100644 index 0000000000..a9043b3c17 --- /dev/null +++ b/SPECS/linux/0133-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch @@ -0,0 +1,411 @@ +From bf5b108a86e16d7f5cd676a3b422db4ae0c45933 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 01:56:10 +0800 +Subject: [RUYI PATCH] FROMLIST: drm: verisilicon: add support for cursor + planes + +Verisilicon display controllers support hardware cursors per output +port. + +Add support for them as cursor planes. + +Signed-off-by: Icenowy Zheng +Reviewed-by: Dmitry Baryshkov +Reviewed-by: Thomas Zimmermann +Link: https://lore.kernel.org/r/20260506175610.2542888-3-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/gpu/drm/verisilicon/Makefile | 3 +- + drivers/gpu/drm/verisilicon/vs_crtc.c | 11 +- + drivers/gpu/drm/verisilicon/vs_cursor_plane.c | 272 ++++++++++++++++++ + .../drm/verisilicon/vs_cursor_plane_regs.h | 44 +++ + drivers/gpu/drm/verisilicon/vs_plane.h | 1 + + 5 files changed, 328 insertions(+), 3 deletions(-) + create mode 100644 drivers/gpu/drm/verisilicon/vs_cursor_plane.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h + +diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile +index fd8d805fbcde..426f4bcaa834 100644 +--- a/drivers/gpu/drm/verisilicon/Makefile ++++ b/drivers/gpu/drm/verisilicon/Makefile +@@ -1,5 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0-only + +-verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o ++verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o \ ++ vs_plane.o vs_primary_plane.o vs_cursor_plane.o + + obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o +diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisilicon/vs_crtc.c +index f49401713000..5c9714a3e69a 100644 +--- a/drivers/gpu/drm/verisilicon/vs_crtc.c ++++ b/drivers/gpu/drm/verisilicon/vs_crtc.c +@@ -159,7 +159,7 @@ struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, + unsigned int output) + { + struct vs_crtc *vcrtc; +- struct drm_plane *primary; ++ struct drm_plane *primary, *cursor; + int ret; + + vcrtc = drmm_kzalloc(drm_dev, sizeof(*vcrtc), GFP_KERNEL); +@@ -175,9 +175,16 @@ struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, + return ERR_PTR(PTR_ERR(primary)); + } + ++ /* Create our cursor plane */ ++ cursor = vs_cursor_plane_init(drm_dev, dc); ++ if (IS_ERR(cursor)) { ++ drm_err(drm_dev, "Couldn't create the cursor plane\n"); ++ return ERR_CAST(cursor); ++ } ++ + ret = drmm_crtc_init_with_planes(drm_dev, &vcrtc->base, + primary, +- NULL, ++ cursor, + &vs_crtc_funcs, + NULL); + if (ret) { +diff --git a/drivers/gpu/drm/verisilicon/vs_cursor_plane.c b/drivers/gpu/drm/verisilicon/vs_cursor_plane.c +new file mode 100644 +index 000000000000..acb9854fa67e +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_cursor_plane.c +@@ -0,0 +1,272 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (ISCAS) ++ * ++ * Authors: ++ * Icenowy Zheng ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_crtc.h" ++#include "vs_plane.h" ++#include "vs_dc.h" ++#include "vs_hwdb.h" ++#include "vs_cursor_plane_regs.h" ++ ++#define VSDC_MIN_CURSOR_SIZE 32 ++#define VSDC_MAX_CURSOR_SIZE 256 ++ ++#define VSDC_CURSOR_LOCATION_MAX_POSITIVE BIT_MASK(15) ++#define VSDC_CURSOR_LOCATION_MAX_NEGATIVE BIT_MASK(5) ++ ++static bool vs_cursor_plane_check_coord(int32_t coord) ++{ ++ if (coord >= 0) ++ return coord <= VSDC_CURSOR_LOCATION_MAX_POSITIVE; ++ else ++ return (-coord) <= VSDC_CURSOR_LOCATION_MAX_NEGATIVE; ++} ++ ++static int vs_cursor_plane_atomic_check(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, ++ plane); ++ struct drm_crtc *crtc = new_plane_state->crtc; ++ struct drm_framebuffer *fb = new_plane_state->fb; ++ struct drm_crtc_state *crtc_state = NULL; ++ struct vs_crtc *vcrtc; ++ struct vs_dc *dc; ++ int ret; ++ ++ if (crtc) ++ crtc_state = drm_atomic_get_new_crtc_state(state, crtc); ++ ++ ret = drm_atomic_helper_check_plane_state(new_plane_state, ++ crtc_state, ++ DRM_PLANE_NO_SCALING, ++ DRM_PLANE_NO_SCALING, ++ true, true); ++ if (ret) ++ return ret; ++ ++ if (!new_plane_state->visible) ++ return 0; /* Skip validity check */ ++ ++ vcrtc = drm_crtc_to_vs_crtc(crtc); ++ dc = vcrtc->dc; ++ ++ /* Only certain PoT square sizes is supported. */ ++ if (!is_power_of_2(new_plane_state->crtc_w) || ++ new_plane_state->crtc_w < VSDC_MIN_CURSOR_SIZE || ++ new_plane_state->crtc_w > dc->identity.max_cursor_size) ++ return -EINVAL; ++ ++ if (new_plane_state->crtc_w != new_plane_state->crtc_h) ++ return -EINVAL; ++ ++ /* Check if the cursor is inside the register fields' range */ ++ if (!vs_cursor_plane_check_coord(new_plane_state->crtc_x) || ++ !vs_cursor_plane_check_coord(new_plane_state->crtc_y)) ++ return -EINVAL; ++ ++ /* Extra line padding isn't supported */ ++ if (fb->pitches[0] != ++ drm_format_info_min_pitch(fb->format, 0, new_plane_state->crtc_w)) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static void vs_cursor_plane_commit(struct vs_dc *dc, unsigned int output) ++{ ++ regmap_set_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_COMMIT | ++ VSDC_CURSOR_CONFIG_IMG_UPDATE); ++} ++ ++static void vs_cursor_plane_atomic_enable(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, ++ plane); ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ unsigned int output = vcrtc->id; ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_FMT_MASK, ++ VSDC_CURSOR_CONFIG_FMT_ARGB8888); ++ ++ vs_cursor_plane_commit(dc, output); ++} ++ ++static void vs_cursor_plane_atomic_disable(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_old_plane_state(atomic_state, ++ plane); ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); ++ unsigned int output = vcrtc->id; ++ struct vs_dc *dc = vcrtc->dc; ++ ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_FMT_MASK, ++ VSDC_CURSOR_CONFIG_FMT_OFF); ++ ++ vs_cursor_plane_commit(dc, output); ++} ++ ++static void vs_cursor_plane_atomic_update(struct drm_plane *plane, ++ struct drm_atomic_state *atomic_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, ++ plane); ++ struct drm_framebuffer *fb = state->fb; ++ struct drm_crtc *crtc = state->crtc; ++ struct vs_dc *dc; ++ struct vs_crtc *vcrtc; ++ unsigned int output; ++ dma_addr_t dma_addr; ++ ++ if (!state->visible) { ++ vs_cursor_plane_atomic_disable(plane, atomic_state); ++ return; ++ } ++ ++ vcrtc = drm_crtc_to_vs_crtc(crtc); ++ output = vcrtc->id; ++ dc = vcrtc->dc; ++ ++ /* Other sizes should be rejected by atomic_check */ ++ switch (state->crtc_w) { ++ case 32: ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_SIZE_MASK, ++ VSDC_CURSOR_CONFIG_SIZE_32); ++ break; ++ case 64: ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_SIZE_MASK, ++ VSDC_CURSOR_CONFIG_SIZE_64); ++ break; ++ case 128: ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_SIZE_MASK, ++ VSDC_CURSOR_CONFIG_SIZE_128); ++ break; ++ case 256: ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_SIZE_MASK, ++ VSDC_CURSOR_CONFIG_SIZE_256); ++ break; ++ } ++ ++ dma_addr = vs_fb_get_dma_addr(fb, &state->src); ++ ++ regmap_write(dc->regs, VSDC_CURSOR_ADDRESS(output), ++ lower_32_bits(dma_addr)); ++ ++ /* ++ * The X_OFF and Y_OFF fields define which point does the LOCATION ++ * register represent in the cursor image, and LOCATION register ++ * values are unsigned. To for positive left-top coordinates the ++ * offset is set to 0 and the location is set to the coordinate, for ++ * negative coordinates the location is set to 0 and the offset ++ * is set to the opposite number of the coordinate to offset the ++ * cursor image partly off-screen. ++ */ ++ if (state->crtc_x >= 0) { ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_X_OFF_MASK, 0); ++ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), ++ VSDC_CURSOR_LOCATION_X_MASK, ++ VSDC_CURSOR_LOCATION_X(state->crtc_x)); ++ } else { ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_X_OFF_MASK, ++ -state->crtc_x); ++ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), ++ VSDC_CURSOR_LOCATION_X_MASK, 0); ++ } ++ ++ if (state->crtc_y >= 0) { ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_Y_OFF_MASK, 0); ++ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), ++ VSDC_CURSOR_LOCATION_Y_MASK, ++ VSDC_CURSOR_LOCATION_Y(state->crtc_y)); ++ } else { ++ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), ++ VSDC_CURSOR_CONFIG_Y_OFF_MASK, ++ -state->crtc_y); ++ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), ++ VSDC_CURSOR_LOCATION_Y_MASK, 0); ++ } ++ ++ vs_cursor_plane_commit(dc, output); ++} ++ ++static const struct drm_plane_helper_funcs vs_cursor_plane_helper_funcs = { ++ .atomic_check = vs_cursor_plane_atomic_check, ++ .atomic_update = vs_cursor_plane_atomic_update, ++ .atomic_enable = vs_cursor_plane_atomic_enable, ++ .atomic_disable = vs_cursor_plane_atomic_disable, ++}; ++ ++static const struct drm_plane_funcs vs_cursor_plane_funcs = { ++ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, ++ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, ++ .disable_plane = drm_atomic_helper_disable_plane, ++ .reset = drm_atomic_helper_plane_reset, ++ .update_plane = drm_atomic_helper_update_plane, ++}; ++ ++static const u32 vs_cursor_plane_formats[] = { ++ DRM_FORMAT_ARGB8888, ++}; ++ ++static const u64 vs_cursor_plane_modifiers[] = { ++ DRM_FORMAT_MOD_LINEAR, ++ DRM_FORMAT_MOD_INVALID, /* sentinel */ ++}; ++ ++struct drm_plane *vs_cursor_plane_init(struct drm_device *drm_dev, ++ struct vs_dc *dc) ++{ ++ int32_t max_cursor_size = dc->identity.max_cursor_size; ++ struct drm_plane *plane; ++ ++ if (drm_WARN_ON_ONCE(drm_dev, max_cursor_size < VSDC_MIN_CURSOR_SIZE || ++ max_cursor_size > VSDC_MAX_CURSOR_SIZE)) ++ return ERR_PTR(-EINVAL); ++ ++ plane = drmm_universal_plane_alloc(drm_dev, struct drm_plane, dev, 0, ++ &vs_cursor_plane_funcs, ++ vs_cursor_plane_formats, ++ ARRAY_SIZE(vs_cursor_plane_formats), ++ vs_cursor_plane_modifiers, ++ DRM_PLANE_TYPE_CURSOR, ++ NULL); ++ ++ if (IS_ERR(plane)) ++ return plane; ++ ++ drm_plane_helper_add(plane, &vs_cursor_plane_helper_funcs); ++ ++ return plane; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h b/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h +new file mode 100644 +index 000000000000..99693f2c95b9 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h +@@ -0,0 +1,44 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++/* ++ * Copyright (C) 2025 Icenowy Zheng ++ * ++ * Based on vs_dc_hw.h, which is: ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef _VS_CURSOR_PLANE_REGS_H_ ++#define _VS_CURSOR_PLANE_REGS_H_ ++ ++#include ++ ++#define VSDC_CURSOR_CONFIG(n) (0x1468 + 0x1080 * (n)) ++#define VSDC_CURSOR_CONFIG_FMT_MASK GENMASK(1, 0) ++#define VSDC_CURSOR_CONFIG_FMT_ARGB8888 (0x2 << 0) ++#define VSDC_CURSOR_CONFIG_FMT_OFF (0x0 << 0) ++#define VSDC_CURSOR_CONFIG_IMG_UPDATE BIT(2) ++#define VSDC_CURSOR_CONFIG_COMMIT BIT(3) ++#define VSDC_CURSOR_CONFIG_SIZE_MASK GENMASK(7, 5) ++#define VSDC_CURSOR_CONFIG_SIZE_32 (0x0 << 5) ++#define VSDC_CURSOR_CONFIG_SIZE_64 (0x1 << 5) ++#define VSDC_CURSOR_CONFIG_SIZE_128 (0x2 << 5) ++#define VSDC_CURSOR_CONFIG_SIZE_256 (0x3 << 5) ++#define VSDC_CURSOR_CONFIG_Y_OFF_MASK GENMASK(12, 8) ++#define VSDC_CURSOR_CONFIG_Y_OFF(v) ((v) << 8) ++#define VSDC_CURSOR_CONFIG_X_OFF_MASK GENMASK(20, 16) ++#define VSDC_CURSOR_CONFIG_X_OFF(v) ((v) << 16) ++ ++#define VSDC_CURSOR_ADDRESS(n) (0x146C + 0x1080 * (n)) ++ ++#define VSDC_CURSOR_LOCATION(n) (0x1470 + 0x1080 * (n)) ++#define VSDC_CURSOR_LOCATION_X_MASK GENMASK(14, 0) ++#define VSDC_CURSOR_LOCATION_X(v) ((v) << 0) ++#define VSDC_CURSOR_LOCATION_Y_MASK GENMASK(30, 16) ++#define VSDC_CURSOR_LOCATION_Y(v) ((v) << 16) ++ ++#define VSDC_CURSOR_BACKGROUND(n) (0x1474 + 0x1080 * (n)) ++#define VSDC_CURSOR_BACKGRUOND_DEFAULT 0x00FFFFFF ++ ++#define VSDC_CURSOR_FOREGROUND(n) (0x1478 + 0x1080 * (n)) ++#define VSDC_CURSOR_FOREGRUOND_DEFAULT 0x00AAAAAA ++ ++#endif /* _VS_CURSOR_PLANE_REGS_H_ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_plane.h b/drivers/gpu/drm/verisilicon/vs_plane.h +index 41875ea3d66a..60b5b3a1bc22 100644 +--- a/drivers/gpu/drm/verisilicon/vs_plane.h ++++ b/drivers/gpu/drm/verisilicon/vs_plane.h +@@ -68,5 +68,6 @@ dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, + const struct drm_rect *src_rect); + + struct drm_plane *vs_primary_plane_init(struct drm_device *dev, struct vs_dc *dc); ++struct drm_plane *vs_cursor_plane_init(struct drm_device *dev, struct vs_dc *dc); + + #endif /* _VS_PLANE_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux/0134-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch b/SPECS/linux/0134-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch deleted file mode 100644 index e688ea09f3..0000000000 --- a/SPECS/linux/0134-FROMLIST-drm-verisilicon-add-support-for-cursor-plan.patch +++ /dev/null @@ -1,411 +0,0 @@ -From fbf6185a7777dd8459eb01b40a7dfeec88373ae1 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 01:56:10 +0800 -Subject: [PATCH 134/269] FROMLIST: drm: verisilicon: add support for cursor - planes - -Verisilicon display controllers support hardware cursors per output -port. - -Add support for them as cursor planes. - -Signed-off-by: Icenowy Zheng -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Thomas Zimmermann -Link: https://lore.kernel.org/r/20260506175610.2542888-3-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/gpu/drm/verisilicon/Makefile | 3 +- - drivers/gpu/drm/verisilicon/vs_crtc.c | 11 +- - drivers/gpu/drm/verisilicon/vs_cursor_plane.c | 272 ++++++++++++++++++ - .../drm/verisilicon/vs_cursor_plane_regs.h | 44 +++ - drivers/gpu/drm/verisilicon/vs_plane.h | 1 + - 5 files changed, 328 insertions(+), 3 deletions(-) - create mode 100644 drivers/gpu/drm/verisilicon/vs_cursor_plane.c - create mode 100644 drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h - -diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile -index fd8d805fbcde..426f4bcaa834 100644 ---- a/drivers/gpu/drm/verisilicon/Makefile -+++ b/drivers/gpu/drm/verisilicon/Makefile -@@ -1,5 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0-only - --verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o vs_plane.o vs_primary_plane.o -+verisilicon-dc-objs := vs_bridge.o vs_crtc.o vs_dc.o vs_drm.o vs_hwdb.o \ -+ vs_plane.o vs_primary_plane.o vs_cursor_plane.o - - obj-$(CONFIG_DRM_VERISILICON_DC) += verisilicon-dc.o -diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisilicon/vs_crtc.c -index f49401713000..5c9714a3e69a 100644 ---- a/drivers/gpu/drm/verisilicon/vs_crtc.c -+++ b/drivers/gpu/drm/verisilicon/vs_crtc.c -@@ -159,7 +159,7 @@ struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, - unsigned int output) - { - struct vs_crtc *vcrtc; -- struct drm_plane *primary; -+ struct drm_plane *primary, *cursor; - int ret; - - vcrtc = drmm_kzalloc(drm_dev, sizeof(*vcrtc), GFP_KERNEL); -@@ -175,9 +175,16 @@ struct vs_crtc *vs_crtc_init(struct drm_device *drm_dev, struct vs_dc *dc, - return ERR_PTR(PTR_ERR(primary)); - } - -+ /* Create our cursor plane */ -+ cursor = vs_cursor_plane_init(drm_dev, dc); -+ if (IS_ERR(cursor)) { -+ drm_err(drm_dev, "Couldn't create the cursor plane\n"); -+ return ERR_CAST(cursor); -+ } -+ - ret = drmm_crtc_init_with_planes(drm_dev, &vcrtc->base, - primary, -- NULL, -+ cursor, - &vs_crtc_funcs, - NULL); - if (ret) { -diff --git a/drivers/gpu/drm/verisilicon/vs_cursor_plane.c b/drivers/gpu/drm/verisilicon/vs_cursor_plane.c -new file mode 100644 -index 000000000000..acb9854fa67e ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_cursor_plane.c -@@ -0,0 +1,272 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (ISCAS) -+ * -+ * Authors: -+ * Icenowy Zheng -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vs_crtc.h" -+#include "vs_plane.h" -+#include "vs_dc.h" -+#include "vs_hwdb.h" -+#include "vs_cursor_plane_regs.h" -+ -+#define VSDC_MIN_CURSOR_SIZE 32 -+#define VSDC_MAX_CURSOR_SIZE 256 -+ -+#define VSDC_CURSOR_LOCATION_MAX_POSITIVE BIT_MASK(15) -+#define VSDC_CURSOR_LOCATION_MAX_NEGATIVE BIT_MASK(5) -+ -+static bool vs_cursor_plane_check_coord(int32_t coord) -+{ -+ if (coord >= 0) -+ return coord <= VSDC_CURSOR_LOCATION_MAX_POSITIVE; -+ else -+ return (-coord) <= VSDC_CURSOR_LOCATION_MAX_NEGATIVE; -+} -+ -+static int vs_cursor_plane_atomic_check(struct drm_plane *plane, -+ struct drm_atomic_state *state) -+{ -+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, -+ plane); -+ struct drm_crtc *crtc = new_plane_state->crtc; -+ struct drm_framebuffer *fb = new_plane_state->fb; -+ struct drm_crtc_state *crtc_state = NULL; -+ struct vs_crtc *vcrtc; -+ struct vs_dc *dc; -+ int ret; -+ -+ if (crtc) -+ crtc_state = drm_atomic_get_new_crtc_state(state, crtc); -+ -+ ret = drm_atomic_helper_check_plane_state(new_plane_state, -+ crtc_state, -+ DRM_PLANE_NO_SCALING, -+ DRM_PLANE_NO_SCALING, -+ true, true); -+ if (ret) -+ return ret; -+ -+ if (!new_plane_state->visible) -+ return 0; /* Skip validity check */ -+ -+ vcrtc = drm_crtc_to_vs_crtc(crtc); -+ dc = vcrtc->dc; -+ -+ /* Only certain PoT square sizes is supported. */ -+ if (!is_power_of_2(new_plane_state->crtc_w) || -+ new_plane_state->crtc_w < VSDC_MIN_CURSOR_SIZE || -+ new_plane_state->crtc_w > dc->identity.max_cursor_size) -+ return -EINVAL; -+ -+ if (new_plane_state->crtc_w != new_plane_state->crtc_h) -+ return -EINVAL; -+ -+ /* Check if the cursor is inside the register fields' range */ -+ if (!vs_cursor_plane_check_coord(new_plane_state->crtc_x) || -+ !vs_cursor_plane_check_coord(new_plane_state->crtc_y)) -+ return -EINVAL; -+ -+ /* Extra line padding isn't supported */ -+ if (fb->pitches[0] != -+ drm_format_info_min_pitch(fb->format, 0, new_plane_state->crtc_w)) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static void vs_cursor_plane_commit(struct vs_dc *dc, unsigned int output) -+{ -+ regmap_set_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_COMMIT | -+ VSDC_CURSOR_CONFIG_IMG_UPDATE); -+} -+ -+static void vs_cursor_plane_atomic_enable(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, -+ plane); -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ unsigned int output = vcrtc->id; -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_FMT_MASK, -+ VSDC_CURSOR_CONFIG_FMT_ARGB8888); -+ -+ vs_cursor_plane_commit(dc, output); -+} -+ -+static void vs_cursor_plane_atomic_disable(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_old_plane_state(atomic_state, -+ plane); -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_crtc *vcrtc = drm_crtc_to_vs_crtc(crtc); -+ unsigned int output = vcrtc->id; -+ struct vs_dc *dc = vcrtc->dc; -+ -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_FMT_MASK, -+ VSDC_CURSOR_CONFIG_FMT_OFF); -+ -+ vs_cursor_plane_commit(dc, output); -+} -+ -+static void vs_cursor_plane_atomic_update(struct drm_plane *plane, -+ struct drm_atomic_state *atomic_state) -+{ -+ struct drm_plane_state *state = drm_atomic_get_new_plane_state(atomic_state, -+ plane); -+ struct drm_framebuffer *fb = state->fb; -+ struct drm_crtc *crtc = state->crtc; -+ struct vs_dc *dc; -+ struct vs_crtc *vcrtc; -+ unsigned int output; -+ dma_addr_t dma_addr; -+ -+ if (!state->visible) { -+ vs_cursor_plane_atomic_disable(plane, atomic_state); -+ return; -+ } -+ -+ vcrtc = drm_crtc_to_vs_crtc(crtc); -+ output = vcrtc->id; -+ dc = vcrtc->dc; -+ -+ /* Other sizes should be rejected by atomic_check */ -+ switch (state->crtc_w) { -+ case 32: -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_SIZE_MASK, -+ VSDC_CURSOR_CONFIG_SIZE_32); -+ break; -+ case 64: -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_SIZE_MASK, -+ VSDC_CURSOR_CONFIG_SIZE_64); -+ break; -+ case 128: -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_SIZE_MASK, -+ VSDC_CURSOR_CONFIG_SIZE_128); -+ break; -+ case 256: -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_SIZE_MASK, -+ VSDC_CURSOR_CONFIG_SIZE_256); -+ break; -+ } -+ -+ dma_addr = vs_fb_get_dma_addr(fb, &state->src); -+ -+ regmap_write(dc->regs, VSDC_CURSOR_ADDRESS(output), -+ lower_32_bits(dma_addr)); -+ -+ /* -+ * The X_OFF and Y_OFF fields define which point does the LOCATION -+ * register represent in the cursor image, and LOCATION register -+ * values are unsigned. To for positive left-top coordinates the -+ * offset is set to 0 and the location is set to the coordinate, for -+ * negative coordinates the location is set to 0 and the offset -+ * is set to the opposite number of the coordinate to offset the -+ * cursor image partly off-screen. -+ */ -+ if (state->crtc_x >= 0) { -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_X_OFF_MASK, 0); -+ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), -+ VSDC_CURSOR_LOCATION_X_MASK, -+ VSDC_CURSOR_LOCATION_X(state->crtc_x)); -+ } else { -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_X_OFF_MASK, -+ -state->crtc_x); -+ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), -+ VSDC_CURSOR_LOCATION_X_MASK, 0); -+ } -+ -+ if (state->crtc_y >= 0) { -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_Y_OFF_MASK, 0); -+ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), -+ VSDC_CURSOR_LOCATION_Y_MASK, -+ VSDC_CURSOR_LOCATION_Y(state->crtc_y)); -+ } else { -+ regmap_update_bits(dc->regs, VSDC_CURSOR_CONFIG(output), -+ VSDC_CURSOR_CONFIG_Y_OFF_MASK, -+ -state->crtc_y); -+ regmap_update_bits(dc->regs, VSDC_CURSOR_LOCATION(output), -+ VSDC_CURSOR_LOCATION_Y_MASK, 0); -+ } -+ -+ vs_cursor_plane_commit(dc, output); -+} -+ -+static const struct drm_plane_helper_funcs vs_cursor_plane_helper_funcs = { -+ .atomic_check = vs_cursor_plane_atomic_check, -+ .atomic_update = vs_cursor_plane_atomic_update, -+ .atomic_enable = vs_cursor_plane_atomic_enable, -+ .atomic_disable = vs_cursor_plane_atomic_disable, -+}; -+ -+static const struct drm_plane_funcs vs_cursor_plane_funcs = { -+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, -+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, -+ .disable_plane = drm_atomic_helper_disable_plane, -+ .reset = drm_atomic_helper_plane_reset, -+ .update_plane = drm_atomic_helper_update_plane, -+}; -+ -+static const u32 vs_cursor_plane_formats[] = { -+ DRM_FORMAT_ARGB8888, -+}; -+ -+static const u64 vs_cursor_plane_modifiers[] = { -+ DRM_FORMAT_MOD_LINEAR, -+ DRM_FORMAT_MOD_INVALID, /* sentinel */ -+}; -+ -+struct drm_plane *vs_cursor_plane_init(struct drm_device *drm_dev, -+ struct vs_dc *dc) -+{ -+ int32_t max_cursor_size = dc->identity.max_cursor_size; -+ struct drm_plane *plane; -+ -+ if (drm_WARN_ON_ONCE(drm_dev, max_cursor_size < VSDC_MIN_CURSOR_SIZE || -+ max_cursor_size > VSDC_MAX_CURSOR_SIZE)) -+ return ERR_PTR(-EINVAL); -+ -+ plane = drmm_universal_plane_alloc(drm_dev, struct drm_plane, dev, 0, -+ &vs_cursor_plane_funcs, -+ vs_cursor_plane_formats, -+ ARRAY_SIZE(vs_cursor_plane_formats), -+ vs_cursor_plane_modifiers, -+ DRM_PLANE_TYPE_CURSOR, -+ NULL); -+ -+ if (IS_ERR(plane)) -+ return plane; -+ -+ drm_plane_helper_add(plane, &vs_cursor_plane_helper_funcs); -+ -+ return plane; -+} -diff --git a/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h b/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h -new file mode 100644 -index 000000000000..99693f2c95b9 ---- /dev/null -+++ b/drivers/gpu/drm/verisilicon/vs_cursor_plane_regs.h -@@ -0,0 +1,44 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Copyright (C) 2025 Icenowy Zheng -+ * -+ * Based on vs_dc_hw.h, which is: -+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. -+ */ -+ -+#ifndef _VS_CURSOR_PLANE_REGS_H_ -+#define _VS_CURSOR_PLANE_REGS_H_ -+ -+#include -+ -+#define VSDC_CURSOR_CONFIG(n) (0x1468 + 0x1080 * (n)) -+#define VSDC_CURSOR_CONFIG_FMT_MASK GENMASK(1, 0) -+#define VSDC_CURSOR_CONFIG_FMT_ARGB8888 (0x2 << 0) -+#define VSDC_CURSOR_CONFIG_FMT_OFF (0x0 << 0) -+#define VSDC_CURSOR_CONFIG_IMG_UPDATE BIT(2) -+#define VSDC_CURSOR_CONFIG_COMMIT BIT(3) -+#define VSDC_CURSOR_CONFIG_SIZE_MASK GENMASK(7, 5) -+#define VSDC_CURSOR_CONFIG_SIZE_32 (0x0 << 5) -+#define VSDC_CURSOR_CONFIG_SIZE_64 (0x1 << 5) -+#define VSDC_CURSOR_CONFIG_SIZE_128 (0x2 << 5) -+#define VSDC_CURSOR_CONFIG_SIZE_256 (0x3 << 5) -+#define VSDC_CURSOR_CONFIG_Y_OFF_MASK GENMASK(12, 8) -+#define VSDC_CURSOR_CONFIG_Y_OFF(v) ((v) << 8) -+#define VSDC_CURSOR_CONFIG_X_OFF_MASK GENMASK(20, 16) -+#define VSDC_CURSOR_CONFIG_X_OFF(v) ((v) << 16) -+ -+#define VSDC_CURSOR_ADDRESS(n) (0x146C + 0x1080 * (n)) -+ -+#define VSDC_CURSOR_LOCATION(n) (0x1470 + 0x1080 * (n)) -+#define VSDC_CURSOR_LOCATION_X_MASK GENMASK(14, 0) -+#define VSDC_CURSOR_LOCATION_X(v) ((v) << 0) -+#define VSDC_CURSOR_LOCATION_Y_MASK GENMASK(30, 16) -+#define VSDC_CURSOR_LOCATION_Y(v) ((v) << 16) -+ -+#define VSDC_CURSOR_BACKGROUND(n) (0x1474 + 0x1080 * (n)) -+#define VSDC_CURSOR_BACKGRUOND_DEFAULT 0x00FFFFFF -+ -+#define VSDC_CURSOR_FOREGROUND(n) (0x1478 + 0x1080 * (n)) -+#define VSDC_CURSOR_FOREGRUOND_DEFAULT 0x00AAAAAA -+ -+#endif /* _VS_CURSOR_PLANE_REGS_H_ */ -diff --git a/drivers/gpu/drm/verisilicon/vs_plane.h b/drivers/gpu/drm/verisilicon/vs_plane.h -index 41875ea3d66a..60b5b3a1bc22 100644 ---- a/drivers/gpu/drm/verisilicon/vs_plane.h -+++ b/drivers/gpu/drm/verisilicon/vs_plane.h -@@ -68,5 +68,6 @@ dma_addr_t vs_fb_get_dma_addr(struct drm_framebuffer *fb, - const struct drm_rect *src_rect); - - struct drm_plane *vs_primary_plane_init(struct drm_device *dev, struct vs_dc *dc); -+struct drm_plane *vs_cursor_plane_init(struct drm_device *dev, struct vs_dc *dc); - - #endif /* _VS_PLANE_H_ */ --- -2.53.0 - diff --git a/SPECS/linux/0134-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch b/SPECS/linux/0134-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch new file mode 100644 index 0000000000..3e5c4be24b --- /dev/null +++ b/SPECS/linux/0134-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch @@ -0,0 +1,37 @@ +From 4ceb8038ae51d5afad023646a49af3b603cbd853 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Mon, 27 Apr 2026 09:32:10 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: add UltraRISC SoC family Kconfig + support + +The first SoC in the UltraRISC series is UR-DP1000, containing octa +UltraRISC CP100 cores. + +Signed-off-by: Jia Wang +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20260427-ultrarisc-pcie-v4-1-98935f6cdfb5@ultrarisc.com +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig.socs | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs +index d621b85dd63b..0b4d06a7b4bf 100644 +--- a/arch/riscv/Kconfig.socs ++++ b/arch/riscv/Kconfig.socs +@@ -84,6 +84,12 @@ config ARCH_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + ++config ARCH_ULTRARISC ++ bool "UltraRISC RISC-V SoCs" ++ help ++ This enables support for UltraRISC SoC platform hardware, ++ including boards based on the UR-DP1000. ++ + config ARCH_VIRT + bool "QEMU Virt Machine" + select POWER_RESET +-- +2.53.0 + diff --git a/SPECS/linux/0135-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch b/SPECS/linux/0135-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch new file mode 100644 index 0000000000..e33e2d422f --- /dev/null +++ b/SPECS/linux/0135-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch @@ -0,0 +1,138 @@ +From 4c1c3438ee690500d08ee4adfe2e7f660fd1a535 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Mon, 27 Apr 2026 09:32:11 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: Add UltraRISC DP1000 PCIe + controller + +Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. + +Signed-off-by: Jia Wang +Reviewed-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com +Signed-off-by: Han Gao +--- + .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 93 +++++++++++++++++++ + MAINTAINERS | 7 ++ + 2 files changed, 100 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml + +diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml +new file mode 100644 +index 000000000000..512b935bf5d1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml +@@ -0,0 +1,93 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: UltraRISC DP1000 PCIe Host Controller ++ ++description: ++ UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. ++ ++maintainers: ++ - Xincheng Zhang ++ - Jia Wang ++ ++allOf: ++ - $ref: /schemas/pci/snps,dw-pcie.yaml# ++ ++properties: ++ compatible: ++ const: ultrarisc,dp1000-pcie ++ ++ reg: ++ items: ++ - description: Data Bus Interface (DBI) registers. ++ - description: PCIe configuration space region. ++ ++ reg-names: ++ items: ++ - const: dbi ++ - const: config ++ ++ num-lanes: ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ enum: [4, 16] ++ description: Number of lanes to use. ++ ++ interrupts: ++ items: ++ - description: MSI interrupt ++ - description: Legacy INTA interrupt ++ - description: Legacy INTB interrupt ++ - description: Legacy INTC interrupt ++ - description: Legacy INTD interrupt ++ ++ interrupt-names: ++ items: ++ - const: msi ++ - const: inta ++ - const: intb ++ - const: intc ++ - const: intd ++ ++required: ++ - compatible ++ - reg ++ - reg-names ++ - interrupts ++ - interrupt-names ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ pcie@21000000 { ++ compatible = "ultrarisc,dp1000-pcie"; ++ reg = <0x0 0x21000000 0x0 0x01000000>, ++ <0x0 0x4fff0000 0x0 0x00010000>; ++ reg-names = "dbi", "config"; ++ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, ++ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, ++ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <16>; ++ interrupt-parent = <&plic>; ++ interrupts = <43>, <44>, <45>, <46>, <47>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, ++ <0x0 0x0 0x0 0x2 &plic 45>, ++ <0x0 0x0 0x0 0x3 &plic 46>, ++ <0x0 0x0 0x0 0x4 &plic 47>; ++ }; ++ }; +diff --git a/MAINTAINERS b/MAINTAINERS +index 08394b6c2f87..791e6d801ca1 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -20591,6 +20591,13 @@ S: Maintained + F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml + F: drivers/pci/controller/plda/pcie-starfive.c + ++PCIE DRIVER FOR ULTRARISC DP1000 ++M: Xincheng Zhang ++M: Jia Wang ++L: linux-pci@vger.kernel.org ++S: Maintained ++F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml ++ + PCIE ENDPOINT DRIVER FOR QUALCOMM + M: Manivannan Sadhasivam + L: linux-pci@vger.kernel.org +-- +2.53.0 + diff --git a/SPECS/linux/0135-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch b/SPECS/linux/0135-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch deleted file mode 100644 index 64028e9e3b..0000000000 --- a/SPECS/linux/0135-FROMLIST-riscv-add-UltraRISC-SoC-family-Kconfig-supp.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 19ea9f3c21f0f43352ac64c89ac71a5af8b3abc1 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 27 Apr 2026 09:32:10 +0800 -Subject: [PATCH 135/269] FROMLIST: riscv: add UltraRISC SoC family Kconfig - support - -The first SoC in the UltraRISC series is UR-DP1000, containing octa -UltraRISC CP100 cores. - -Signed-off-by: Jia Wang -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20260427-ultrarisc-pcie-v4-1-98935f6cdfb5@ultrarisc.com -Signed-off-by: Han Gao ---- - arch/riscv/Kconfig.socs | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs -index d621b85dd63b..0b4d06a7b4bf 100644 ---- a/arch/riscv/Kconfig.socs -+++ b/arch/riscv/Kconfig.socs -@@ -84,6 +84,12 @@ config ARCH_THEAD - help - This enables support for the RISC-V based T-HEAD SoCs. - -+config ARCH_ULTRARISC -+ bool "UltraRISC RISC-V SoCs" -+ help -+ This enables support for UltraRISC SoC platform hardware, -+ including boards based on the UR-DP1000. -+ - config ARCH_VIRT - bool "QEMU Virt Machine" - select POWER_RESET --- -2.53.0 - diff --git a/SPECS/linux/0136-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch b/SPECS/linux/0136-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch new file mode 100644 index 0000000000..74684f14ad --- /dev/null +++ b/SPECS/linux/0136-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch @@ -0,0 +1,292 @@ +From b90ec0b785a09a3a90b5d837f2983c0b5b267b66 Mon Sep 17 00:00:00 2001 +From: Xincheng Zhang +Date: Mon, 27 Apr 2026 09:32:12 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root + Complex driver + +Add DP1000 SoC PCIe Root Complex driver. + +The controller only supports 32-bit aligned configuration space accesses. + +Signed-off-by: Xincheng Zhang +Signed-off-by: Jia Wang +Link: https://lore.kernel.org/r/20260427-ultrarisc-pcie-v4-3-98935f6cdfb5@ultrarisc.com +Signed-off-by: Han Gao +--- + MAINTAINERS | 1 + + drivers/pci/controller/dwc/Kconfig | 12 ++ + drivers/pci/controller/dwc/Makefile | 1 + + drivers/pci/controller/dwc/pcie-designware.h | 22 +++ + drivers/pci/controller/dwc/pcie-ultrarisc.c | 175 +++++++++++++++++++ + 5 files changed, 211 insertions(+) + create mode 100644 drivers/pci/controller/dwc/pcie-ultrarisc.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index 791e6d801ca1..9e4ce740727f 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -20597,6 +20597,7 @@ M: Jia Wang + L: linux-pci@vger.kernel.org + S: Maintained + F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml ++F: drivers/pci/controller/dwc/pcie-ultrarisc.c + + PCIE ENDPOINT DRIVER FOR QUALCOMM + M: Manivannan Sadhasivam +diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig +index d0aa031397fa..06f7d98259cd 100644 +--- a/drivers/pci/controller/dwc/Kconfig ++++ b/drivers/pci/controller/dwc/Kconfig +@@ -548,4 +548,16 @@ config PCIE_VISCONTI_HOST + Say Y here if you want PCIe controller support on Toshiba Visconti SoC. + This driver supports TMPV7708 SoC. + ++config PCIE_ULTRARISC ++ tristate "UltraRISC PCIe host controller" ++ depends on ARCH_ULTRARISC || COMPILE_TEST ++ select PCIE_DW_HOST ++ select PCI_MSI ++ default y if ARCH_ULTRARISC ++ help ++ Enables support for the PCIe controller in the UltraRISC SoC. ++ This driver supports UR-DP1000 SoC. ++ By default, this symbol is enabled when ARCH_ULTRARISC is active, ++ requiring no further configuration on that platform. ++ + endmenu +diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile +index 67ba59c02038..884c46b78e01 100644 +--- a/drivers/pci/controller/dwc/Makefile ++++ b/drivers/pci/controller/dwc/Makefile +@@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o + obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o + obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o + obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o ++obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o + + # The following drivers are for devices that use the generic ACPI + # pci_root.c driver but don't support standard ECAM config access. +diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h +index 3e69ef60165b..4c484c38d790 100644 +--- a/drivers/pci/controller/dwc/pcie-designware.h ++++ b/drivers/pci/controller/dwc/pcie-designware.h +@@ -71,6 +71,8 @@ + + /* Synopsys-specific PCIe configuration registers */ + #define PCIE_PORT_FORCE 0x708 ++/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */ ++#define PORT_LINK_NUM_MASK GENMASK(7, 0) + #define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) + + #define PCIE_PORT_AFR 0x70C +@@ -98,6 +100,26 @@ + #define PCIE_PORT_LANE_SKEW 0x714 + #define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) + ++/* ++ * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number ++ * Register. ++ * This register holds the ack frequency, latency, replay, fast link ++ * scaling timers, and max function number values. ++ * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor. ++ * 0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us). ++ * When the LTSSM is in Config or L12 Entry State, 1ms ++ * timer is 2us, 2ms timer is 4us and 3ms timer is 6us. ++ * 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us) ++ * 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us) ++ * 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us) ++ */ ++#define PCIE_TIMER_CTRL_MAX_FUNC_NUM 0x718 ++#define PORT_FLT_SF_MASK GENMASK(30, 29) ++#define PORT_FLT_SF_VAL_1024 0x0 ++#define PORT_FLT_SF_VAL_256 0x1 ++#define PORT_FLT_SF_VAL_64 0x2 ++#define PORT_FLT_SF_VAL_16 0x3 ++ + #define PCIE_PORT_DEBUG0 0x728 + #define PORT_LOGIC_LTSSM_STATE_MASK 0x3f + #define PORT_LOGIC_LTSSM_STATE_L0 0x11 +diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c +new file mode 100644 +index 000000000000..7326bd446590 +--- /dev/null ++++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c +@@ -0,0 +1,175 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * DWC PCIe RC driver for UltraRISC SoCs ++ * ++ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-designware.h" ++ ++#define PCIE_CUS_CORE 0x400000 ++ ++#define LTSSM_ENABLE BIT(7) ++#define FAST_LINK_MODE BIT(12) ++#define HOLD_PHY_RST BIT(14) ++#define L1SUB_DISABLE BIT(15) ++ ++#define ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS 0x6 ++ ++static struct pci_ops ultrarisc_pci_ops = { ++ .map_bus = dw_pcie_own_conf_map_bus, ++ .read = pci_generic_config_read32, ++ .write = pci_generic_config_write32, ++}; ++ ++static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) ++{ ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ struct pci_host_bridge *bridge = pp->bridge; ++ u8 cap_exp; ++ u32 val; ++ ++ bridge->ops = &ultrarisc_pci_ops; ++ ++ if (dw_pcie_link_up(pci)) ++ return 0; ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); ++ val &= ~FAST_LINK_MODE; ++ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM); ++ FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64); ++ dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val); ++ ++ cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); ++ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2); ++ FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT); ++ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val); ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE); ++ FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0); ++ dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val); ++ ++ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2); ++ FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val, ++ ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS); ++ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val); ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); ++ val &= ~(HOLD_PHY_RST | L1SUB_DISABLE); ++ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); ++ ++ return 0; ++} ++ ++static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp) ++{ ++ /* ++ * DP1000 does not support sending PME_Turn_Off from the RC. ++ * Keep this callback empty to skip the generic MSG TLP path. ++ */ ++} ++ ++static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = { ++ .init = ultrarisc_pcie_host_init, ++ .pme_turn_off = ultrarisc_pcie_pme_turn_off, ++}; ++ ++static int ultrarisc_pcie_start_link(struct dw_pcie *pci) ++{ ++ u32 val; ++ ++ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); ++ val |= LTSSM_ENABLE; ++ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); ++ ++ return 0; ++} ++ ++static const struct dw_pcie_ops dw_pcie_ops = { ++ .start_link = ultrarisc_pcie_start_link, ++}; ++ ++static int ultrarisc_pcie_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct dw_pcie_rp *pp; ++ struct dw_pcie *pci; ++ int ret; ++ ++ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); ++ if (!pci) ++ return -ENOMEM; ++ ++ pci->dev = dev; ++ pci->ops = &dw_pcie_ops; ++ ++ /* Set a default value suitable for at most 16 in and 16 out windows */ ++ pci->atu_size = SZ_8K; ++ ++ pp = &pci->pp; ++ ++ platform_set_drvdata(pdev, pci); ++ ++ pp->num_vectors = MAX_MSI_IRQS; ++ /* No L2/L3 Ready indication is available on this platform. */ ++ pp->skip_l23_ready = true; ++ pp->ops = &ultrarisc_pcie_host_ops; ++ ++ ret = dw_pcie_host_init(pp); ++ if (ret) { ++ dev_err(dev, "Failed to initialize host\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int ultrarisc_pcie_suspend_noirq(struct device *dev) ++{ ++ struct dw_pcie *pci = dev_get_drvdata(dev); ++ ++ return dw_pcie_suspend_noirq(pci); ++} ++ ++static int ultrarisc_pcie_resume_noirq(struct device *dev) ++{ ++ struct dw_pcie *pci = dev_get_drvdata(dev); ++ ++ return dw_pcie_resume_noirq(pci); ++} ++ ++static const struct dev_pm_ops ultrarisc_pcie_pm_ops = { ++ NOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq, ++ ultrarisc_pcie_resume_noirq) ++}; ++ ++static const struct of_device_id ultrarisc_pcie_of_match[] = { ++ { ++ .compatible = "ultrarisc,dp1000-pcie", ++ }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match); ++ ++static struct platform_driver ultrarisc_pcie_driver = { ++ .driver = { ++ .name = "ultrarisc-pcie", ++ .of_match_table = ultrarisc_pcie_of_match, ++ .suppress_bind_attrs = true, ++ .pm = &ultrarisc_pcie_pm_ops, ++ }, ++ .probe = ultrarisc_pcie_probe, ++}; ++module_platform_driver(ultrarisc_pcie_driver); ++ ++MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux/0136-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch b/SPECS/linux/0136-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch deleted file mode 100644 index 980b4cc8b0..0000000000 --- a/SPECS/linux/0136-FROMLIST-dt-bindings-PCI-Add-UltraRISC-DP1000-PCIe-c.patch +++ /dev/null @@ -1,138 +0,0 @@ -From b4ad3f8c3b2e8519370ec127039db7e5b8ce80b8 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 27 Apr 2026 09:32:11 +0800 -Subject: [PATCH 136/269] FROMLIST: dt-bindings: PCI: Add UltraRISC DP1000 PCIe - controller - -Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. - -Signed-off-by: Jia Wang -Reviewed-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com -Signed-off-by: Han Gao ---- - .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 93 +++++++++++++++++++ - MAINTAINERS | 7 ++ - 2 files changed, 100 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml - -diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml -new file mode 100644 -index 000000000000..512b935bf5d1 ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml -@@ -0,0 +1,93 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: UltraRISC DP1000 PCIe Host Controller -+ -+description: -+ UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. -+ -+maintainers: -+ - Xincheng Zhang -+ - Jia Wang -+ -+allOf: -+ - $ref: /schemas/pci/snps,dw-pcie.yaml# -+ -+properties: -+ compatible: -+ const: ultrarisc,dp1000-pcie -+ -+ reg: -+ items: -+ - description: Data Bus Interface (DBI) registers. -+ - description: PCIe configuration space region. -+ -+ reg-names: -+ items: -+ - const: dbi -+ - const: config -+ -+ num-lanes: -+ $ref: /schemas/types.yaml#/definitions/uint32 -+ enum: [4, 16] -+ description: Number of lanes to use. -+ -+ interrupts: -+ items: -+ - description: MSI interrupt -+ - description: Legacy INTA interrupt -+ - description: Legacy INTB interrupt -+ - description: Legacy INTC interrupt -+ - description: Legacy INTD interrupt -+ -+ interrupt-names: -+ items: -+ - const: msi -+ - const: inta -+ - const: intb -+ - const: intc -+ - const: intd -+ -+required: -+ - compatible -+ - reg -+ - reg-names -+ - interrupts -+ - interrupt-names -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ pcie@21000000 { -+ compatible = "ultrarisc,dp1000-pcie"; -+ reg = <0x0 0x21000000 0x0 0x01000000>, -+ <0x0 0x4fff0000 0x0 0x00010000>; -+ reg-names = "dbi", "config"; -+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, -+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <16>; -+ interrupt-parent = <&plic>; -+ interrupts = <43>, <44>, <45>, <46>, <47>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, -+ <0x0 0x0 0x0 0x2 &plic 45>, -+ <0x0 0x0 0x0 0x3 &plic 46>, -+ <0x0 0x0 0x0 0x4 &plic 47>; -+ }; -+ }; -diff --git a/MAINTAINERS b/MAINTAINERS -index 08394b6c2f87..791e6d801ca1 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -20591,6 +20591,13 @@ S: Maintained - F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml - F: drivers/pci/controller/plda/pcie-starfive.c - -+PCIE DRIVER FOR ULTRARISC DP1000 -+M: Xincheng Zhang -+M: Jia Wang -+L: linux-pci@vger.kernel.org -+S: Maintained -+F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml -+ - PCIE ENDPOINT DRIVER FOR QUALCOMM - M: Manivannan Sadhasivam - L: linux-pci@vger.kernel.org --- -2.53.0 - diff --git a/SPECS/linux/0137-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch b/SPECS/linux/0137-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch deleted file mode 100644 index 5f54b8d51b..0000000000 --- a/SPECS/linux/0137-FROMLIST-PCI-ultrarisc-Add-UltraRISC-DP1000-PCIe-Roo.patch +++ /dev/null @@ -1,292 +0,0 @@ -From 2c16bc472ac3f12ba2ca57fd8bffaf404720328a Mon Sep 17 00:00:00 2001 -From: Xincheng Zhang -Date: Mon, 27 Apr 2026 09:32:12 +0800 -Subject: [PATCH 137/269] FROMLIST: PCI: ultrarisc: Add UltraRISC DP1000 PCIe - Root Complex driver - -Add DP1000 SoC PCIe Root Complex driver. - -The controller only supports 32-bit aligned configuration space accesses. - -Signed-off-by: Xincheng Zhang -Signed-off-by: Jia Wang -Link: https://lore.kernel.org/r/20260427-ultrarisc-pcie-v4-3-98935f6cdfb5@ultrarisc.com -Signed-off-by: Han Gao ---- - MAINTAINERS | 1 + - drivers/pci/controller/dwc/Kconfig | 12 ++ - drivers/pci/controller/dwc/Makefile | 1 + - drivers/pci/controller/dwc/pcie-designware.h | 22 +++ - drivers/pci/controller/dwc/pcie-ultrarisc.c | 175 +++++++++++++++++++ - 5 files changed, 211 insertions(+) - create mode 100644 drivers/pci/controller/dwc/pcie-ultrarisc.c - -diff --git a/MAINTAINERS b/MAINTAINERS -index 791e6d801ca1..9e4ce740727f 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -20597,6 +20597,7 @@ M: Jia Wang - L: linux-pci@vger.kernel.org - S: Maintained - F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml -+F: drivers/pci/controller/dwc/pcie-ultrarisc.c - - PCIE ENDPOINT DRIVER FOR QUALCOMM - M: Manivannan Sadhasivam -diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig -index d0aa031397fa..06f7d98259cd 100644 ---- a/drivers/pci/controller/dwc/Kconfig -+++ b/drivers/pci/controller/dwc/Kconfig -@@ -548,4 +548,16 @@ config PCIE_VISCONTI_HOST - Say Y here if you want PCIe controller support on Toshiba Visconti SoC. - This driver supports TMPV7708 SoC. - -+config PCIE_ULTRARISC -+ tristate "UltraRISC PCIe host controller" -+ depends on ARCH_ULTRARISC || COMPILE_TEST -+ select PCIE_DW_HOST -+ select PCI_MSI -+ default y if ARCH_ULTRARISC -+ help -+ Enables support for the PCIe controller in the UltraRISC SoC. -+ This driver supports UR-DP1000 SoC. -+ By default, this symbol is enabled when ARCH_ULTRARISC is active, -+ requiring no further configuration on that platform. -+ - endmenu -diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile -index 67ba59c02038..884c46b78e01 100644 ---- a/drivers/pci/controller/dwc/Makefile -+++ b/drivers/pci/controller/dwc/Makefile -@@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o - obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o - obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o - obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o -+obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o - - # The following drivers are for devices that use the generic ACPI - # pci_root.c driver but don't support standard ECAM config access. -diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h -index 3e69ef60165b..4c484c38d790 100644 ---- a/drivers/pci/controller/dwc/pcie-designware.h -+++ b/drivers/pci/controller/dwc/pcie-designware.h -@@ -71,6 +71,8 @@ - - /* Synopsys-specific PCIe configuration registers */ - #define PCIE_PORT_FORCE 0x708 -+/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */ -+#define PORT_LINK_NUM_MASK GENMASK(7, 0) - #define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) - - #define PCIE_PORT_AFR 0x70C -@@ -98,6 +100,26 @@ - #define PCIE_PORT_LANE_SKEW 0x714 - #define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) - -+/* -+ * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number -+ * Register. -+ * This register holds the ack frequency, latency, replay, fast link -+ * scaling timers, and max function number values. -+ * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor. -+ * 0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us). -+ * When the LTSSM is in Config or L12 Entry State, 1ms -+ * timer is 2us, 2ms timer is 4us and 3ms timer is 6us. -+ * 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us) -+ * 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us) -+ * 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us) -+ */ -+#define PCIE_TIMER_CTRL_MAX_FUNC_NUM 0x718 -+#define PORT_FLT_SF_MASK GENMASK(30, 29) -+#define PORT_FLT_SF_VAL_1024 0x0 -+#define PORT_FLT_SF_VAL_256 0x1 -+#define PORT_FLT_SF_VAL_64 0x2 -+#define PORT_FLT_SF_VAL_16 0x3 -+ - #define PCIE_PORT_DEBUG0 0x728 - #define PORT_LOGIC_LTSSM_STATE_MASK 0x3f - #define PORT_LOGIC_LTSSM_STATE_L0 0x11 -diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c -new file mode 100644 -index 000000000000..7326bd446590 ---- /dev/null -+++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c -@@ -0,0 +1,175 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * DWC PCIe RC driver for UltraRISC SoCs -+ * -+ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pcie-designware.h" -+ -+#define PCIE_CUS_CORE 0x400000 -+ -+#define LTSSM_ENABLE BIT(7) -+#define FAST_LINK_MODE BIT(12) -+#define HOLD_PHY_RST BIT(14) -+#define L1SUB_DISABLE BIT(15) -+ -+#define ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS 0x6 -+ -+static struct pci_ops ultrarisc_pci_ops = { -+ .map_bus = dw_pcie_own_conf_map_bus, -+ .read = pci_generic_config_read32, -+ .write = pci_generic_config_write32, -+}; -+ -+static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) -+{ -+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); -+ struct pci_host_bridge *bridge = pp->bridge; -+ u8 cap_exp; -+ u32 val; -+ -+ bridge->ops = &ultrarisc_pci_ops; -+ -+ if (dw_pcie_link_up(pci)) -+ return 0; -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); -+ val &= ~FAST_LINK_MODE; -+ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM); -+ FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64); -+ dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val); -+ -+ cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); -+ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2); -+ FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT); -+ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val); -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE); -+ FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0); -+ dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val); -+ -+ val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2); -+ FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val, -+ ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS); -+ dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val); -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); -+ val &= ~(HOLD_PHY_RST | L1SUB_DISABLE); -+ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); -+ -+ return 0; -+} -+ -+static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp) -+{ -+ /* -+ * DP1000 does not support sending PME_Turn_Off from the RC. -+ * Keep this callback empty to skip the generic MSG TLP path. -+ */ -+} -+ -+static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = { -+ .init = ultrarisc_pcie_host_init, -+ .pme_turn_off = ultrarisc_pcie_pme_turn_off, -+}; -+ -+static int ultrarisc_pcie_start_link(struct dw_pcie *pci) -+{ -+ u32 val; -+ -+ val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); -+ val |= LTSSM_ENABLE; -+ dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); -+ -+ return 0; -+} -+ -+static const struct dw_pcie_ops dw_pcie_ops = { -+ .start_link = ultrarisc_pcie_start_link, -+}; -+ -+static int ultrarisc_pcie_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct dw_pcie_rp *pp; -+ struct dw_pcie *pci; -+ int ret; -+ -+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); -+ if (!pci) -+ return -ENOMEM; -+ -+ pci->dev = dev; -+ pci->ops = &dw_pcie_ops; -+ -+ /* Set a default value suitable for at most 16 in and 16 out windows */ -+ pci->atu_size = SZ_8K; -+ -+ pp = &pci->pp; -+ -+ platform_set_drvdata(pdev, pci); -+ -+ pp->num_vectors = MAX_MSI_IRQS; -+ /* No L2/L3 Ready indication is available on this platform. */ -+ pp->skip_l23_ready = true; -+ pp->ops = &ultrarisc_pcie_host_ops; -+ -+ ret = dw_pcie_host_init(pp); -+ if (ret) { -+ dev_err(dev, "Failed to initialize host\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int ultrarisc_pcie_suspend_noirq(struct device *dev) -+{ -+ struct dw_pcie *pci = dev_get_drvdata(dev); -+ -+ return dw_pcie_suspend_noirq(pci); -+} -+ -+static int ultrarisc_pcie_resume_noirq(struct device *dev) -+{ -+ struct dw_pcie *pci = dev_get_drvdata(dev); -+ -+ return dw_pcie_resume_noirq(pci); -+} -+ -+static const struct dev_pm_ops ultrarisc_pcie_pm_ops = { -+ NOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq, -+ ultrarisc_pcie_resume_noirq) -+}; -+ -+static const struct of_device_id ultrarisc_pcie_of_match[] = { -+ { -+ .compatible = "ultrarisc,dp1000-pcie", -+ }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match); -+ -+static struct platform_driver ultrarisc_pcie_driver = { -+ .driver = { -+ .name = "ultrarisc-pcie", -+ .of_match_table = ultrarisc_pcie_of_match, -+ .suppress_bind_attrs = true, -+ .pm = &ultrarisc_pcie_pm_ops, -+ }, -+ .probe = ultrarisc_pcie_probe, -+}; -+module_platform_driver(ultrarisc_pcie_driver); -+ -+MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux/0137-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch b/SPECS/linux/0137-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch new file mode 100644 index 0000000000..462ca9d0dd --- /dev/null +++ b/SPECS/linux/0137-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch @@ -0,0 +1,199 @@ +From f5c471276113f304468e2b1da532ee386e484f8e Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 28 Apr 2026 13:26:26 +0800 +Subject: [RUYI PATCH] FROMLIST: serial: 8250_dwlib: move DesignWare register + definitions to header + +Move the DW_UART_* register offsets and CPR bit/field definitions from +8250_dwlib.c into 8250_dwlib.h so they can be shared by 8250_dw and +8250_dwlib users. + +Add an include guard for 8250_dwlib.h. + +Signed-off-by: Jia Wang +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-1-97de63b1e3eb@ultrarisc.com +Signed-off-by: Han Gao +--- + drivers/tty/serial/8250/8250_dw.c | 11 ----- + drivers/tty/serial/8250/8250_dwlib.c | 49 -------------------- + drivers/tty/serial/8250/8250_dwlib.h | 67 ++++++++++++++++++++++++++++ + 3 files changed, 67 insertions(+), 60 deletions(-) + +diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c +index 94beadb4024d..467755bf0092 100644 +--- a/drivers/tty/serial/8250/8250_dw.c ++++ b/drivers/tty/serial/8250/8250_dw.c +@@ -34,22 +34,11 @@ + + #include "8250_dwlib.h" + +-/* Offsets for the DesignWare specific registers */ +-#define DW_UART_USR 0x1f /* UART Status Register */ +-#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ +- + #define OCTEON_UART_USR 0x27 /* UART Status Register */ + + #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */ + #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ + +-/* DesignWare specific register fields */ +-#define DW_UART_IIR_IID GENMASK(3, 0) +- +-#define DW_UART_MCR_SIRE BIT(6) +- +-#define DW_UART_USR_BUSY BIT(0) +- + /* Renesas specific register fields */ + #define RZN1_UART_xDMACR_DMA_EN BIT(0) + #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1) +diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c +index b055d89cfb39..8859e66d2d71 100644 +--- a/drivers/tty/serial/8250/8250_dwlib.c ++++ b/drivers/tty/serial/8250/8250_dwlib.c +@@ -13,55 +13,6 @@ + + #include "8250_dwlib.h" + +-/* Offsets for the DesignWare specific registers */ +-#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ +-#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ +-#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ +-#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ +-#define DW_UART_RAR 0xc4 /* Receive Address Register */ +-#define DW_UART_TAR 0xc8 /* Transmit Address Register */ +-#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ +-#define DW_UART_CPR 0xf4 /* Component Parameter Register */ +-#define DW_UART_UCV 0xf8 /* UART Component Version */ +- +-/* Receive / Transmit Address Register bits */ +-#define DW_UART_ADDR_MASK GENMASK(7, 0) +- +-/* Line Status Register bits */ +-#define DW_UART_LSR_ADDR_RCVD BIT(8) +- +-/* Transceiver Control Register bits */ +-#define DW_UART_TCR_RS485_EN BIT(0) +-#define DW_UART_TCR_RE_POL BIT(1) +-#define DW_UART_TCR_DE_POL BIT(2) +-#define DW_UART_TCR_XFER_MODE GENMASK(4, 3) +-#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) +-#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) +-#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) +- +-/* Line Extended Control Register bits */ +-#define DW_UART_LCR_EXT_DLS_E BIT(0) +-#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) +-#define DW_UART_LCR_EXT_SEND_ADDR BIT(2) +-#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) +- +-/* Component Parameter Register bits */ +-#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) +-#define DW_UART_CPR_AFCE_MODE BIT(4) +-#define DW_UART_CPR_THRE_MODE BIT(5) +-#define DW_UART_CPR_SIR_MODE BIT(6) +-#define DW_UART_CPR_SIR_LP_MODE BIT(7) +-#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) +-#define DW_UART_CPR_FIFO_ACCESS BIT(9) +-#define DW_UART_CPR_FIFO_STAT BIT(10) +-#define DW_UART_CPR_SHADOW BIT(11) +-#define DW_UART_CPR_ENCODED_PARMS BIT(12) +-#define DW_UART_CPR_DMA_EXTRA BIT(13) +-#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) +- +-/* Helper for FIFO size calculation */ +-#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) +- + /* + * divisor = div(I) + div(F) + * "I" means integer, "F" means fractional +diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h +index 7dd2a8e7b780..2f26f9ecacbe 100644 +--- a/drivers/tty/serial/8250/8250_dwlib.h ++++ b/drivers/tty/serial/8250/8250_dwlib.h +@@ -1,11 +1,76 @@ + /* SPDX-License-Identifier: GPL-2.0+ */ + /* Synopsys DesignWare 8250 library header file. */ + ++#ifndef _SERIAL_8250_DWLIB_H_ ++#define _SERIAL_8250_DWLIB_H_ ++ ++#include ++#include + #include + #include + + #include "8250.h" + ++/* Offsets for the DesignWare specific registers */ ++#define DW_UART_USR 0x1f /* UART Status Register */ ++#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ ++#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ ++#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ ++#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ ++#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ ++#define DW_UART_RAR 0xc4 /* Receive Address Register */ ++#define DW_UART_TAR 0xc8 /* Transmit Address Register */ ++#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ ++#define DW_UART_CPR 0xf4 /* Component Parameter Register */ ++#define DW_UART_UCV 0xf8 /* UART Component Version */ ++ ++/* Interrupt ID Register bits */ ++#define DW_UART_IIR_IID GENMASK(3, 0) ++ ++/* Modem Control Register bits */ ++#define DW_UART_MCR_SIRE BIT(6) ++ ++/* Line Status Register bits */ ++#define DW_UART_LSR_ADDR_RCVD BIT(8) ++ ++/* UART Status Register bits */ ++#define DW_UART_USR_BUSY BIT(0) ++ ++/* Transceiver Control Register bits */ ++#define DW_UART_TCR_RS485_EN BIT(0) ++#define DW_UART_TCR_RE_POL BIT(1) ++#define DW_UART_TCR_DE_POL BIT(2) ++#define DW_UART_TCR_XFER_MODE GENMASK(4, 3) ++#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) ++#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) ++#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) ++ ++/* Receive / Transmit Address Register bits */ ++#define DW_UART_ADDR_MASK GENMASK(7, 0) ++ ++/* Line Extended Control Register bits */ ++#define DW_UART_LCR_EXT_DLS_E BIT(0) ++#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) ++#define DW_UART_LCR_EXT_SEND_ADDR BIT(2) ++#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) ++ ++/* Component Parameter Register bits */ ++#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) ++#define DW_UART_CPR_AFCE_MODE BIT(4) ++#define DW_UART_CPR_THRE_MODE BIT(5) ++#define DW_UART_CPR_SIR_MODE BIT(6) ++#define DW_UART_CPR_SIR_LP_MODE BIT(7) ++#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) ++#define DW_UART_CPR_FIFO_ACCESS BIT(9) ++#define DW_UART_CPR_FIFO_STAT BIT(10) ++#define DW_UART_CPR_SHADOW BIT(11) ++#define DW_UART_CPR_ENCODED_PARMS BIT(12) ++#define DW_UART_CPR_DMA_EXTRA BIT(13) ++#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) ++ ++/* Helper for FIFO size calculation */ ++#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) ++ + struct dw8250_port_data { + /* Port properties */ + int line; +@@ -38,3 +103,5 @@ static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg) + else + writel(reg, p->membase + offset); + } ++ ++#endif /* _SERIAL_8250_DWLIB_H_ */ +-- +2.53.0 + diff --git a/SPECS/linux/0138-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch b/SPECS/linux/0138-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch new file mode 100644 index 0000000000..f6e0952475 --- /dev/null +++ b/SPECS/linux/0138-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch @@ -0,0 +1,72 @@ +From 44aacbdd590f85d438612b9d80b533f5337a3319 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 28 Apr 2026 13:26:27 +0800 +Subject: [RUYI PATCH] FROMLIST: serial: 8250_dw: build Renesas RZN1 CPR value + from DW_UART_CPR_* definitions + +Replace the magic CPR value for Renesas RZ/N1 with a composition using +DW_UART_CPR_* bit/field definitions and FIELD_PREP_CONST(). + +Introduce a helper macro to convert a FIFO size (bytes) into the CPR +FIFO_MODE field value, with BUILD_BUG_ON_ZERO() checks for alignment and +bounds. Use it to replace the literal FIFO_MODE values in the RZN1. + +Signed-off-by: Jia Wang +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-2-97de63b1e3eb@ultrarisc.com +Signed-off-by: Han Gao +--- + drivers/tty/serial/8250/8250_dw.c | 11 ++++++++++- + drivers/tty/serial/8250/8250_dwlib.h | 7 +++++++ + 2 files changed, 17 insertions(+), 1 deletion(-) + +diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c +index 467755bf0092..5cf3bb74b285 100644 +--- a/drivers/tty/serial/8250/8250_dw.c ++++ b/drivers/tty/serial/8250/8250_dw.c +@@ -937,7 +937,16 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = { + + static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { + .usr_reg = DW_UART_USR, +- .cpr_value = 0x00012f32, ++ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | ++ DW_UART_CPR_AFCE_MODE | ++ DW_UART_CPR_THRE_MODE | ++ DW_UART_CPR_ADDITIONAL_FEATURES | ++ DW_UART_CPR_FIFO_ACCESS | ++ DW_UART_CPR_FIFO_STAT | ++ DW_UART_CPR_SHADOW | ++ DW_UART_CPR_DMA_EXTRA | ++ FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, ++ DW_UART_CPR_FIFO_MODE_FROM_SIZE(16)), + .quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC, + }; + +diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h +index 2f26f9ecacbe..c1f87cd42ecc 100644 +--- a/drivers/tty/serial/8250/8250_dwlib.h ++++ b/drivers/tty/serial/8250/8250_dwlib.h +@@ -6,6 +6,8 @@ + + #include + #include ++#include ++#include + #include + #include + +@@ -70,6 +72,11 @@ + + /* Helper for FIFO size calculation */ + #define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) ++#define DW_UART_CPR_FIFO_MODE_MAX 0x80 ++#define DW_UART_CPR_FIFO_MODE_FROM_SIZE(size) \ ++ (BUILD_BUG_ON_ZERO(!IS_ALIGNED((size), 16)) + \ ++ BUILD_BUG_ON_ZERO(((size) / 16) > DW_UART_CPR_FIFO_MODE_MAX) + \ ++ ((size) / 16)) + + struct dw8250_port_data { + /* Port properties */ +-- +2.53.0 + diff --git a/SPECS/linux/0138-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch b/SPECS/linux/0138-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch deleted file mode 100644 index e259c9364a..0000000000 --- a/SPECS/linux/0138-FROMLIST-serial-8250_dwlib-move-DesignWare-register-.patch +++ /dev/null @@ -1,199 +0,0 @@ -From a413eaa6f0bf79e6e5da432fa3876b976feb3e76 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 28 Apr 2026 13:26:26 +0800 -Subject: [PATCH 138/269] FROMLIST: serial: 8250_dwlib: move DesignWare - register definitions to header - -Move the DW_UART_* register offsets and CPR bit/field definitions from -8250_dwlib.c into 8250_dwlib.h so they can be shared by 8250_dw and -8250_dwlib users. - -Add an include guard for 8250_dwlib.h. - -Signed-off-by: Jia Wang -Reviewed-by: Andy Shevchenko -Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-1-97de63b1e3eb@ultrarisc.com -Signed-off-by: Han Gao ---- - drivers/tty/serial/8250/8250_dw.c | 11 ----- - drivers/tty/serial/8250/8250_dwlib.c | 49 -------------------- - drivers/tty/serial/8250/8250_dwlib.h | 67 ++++++++++++++++++++++++++++ - 3 files changed, 67 insertions(+), 60 deletions(-) - -diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c -index 94beadb4024d..467755bf0092 100644 ---- a/drivers/tty/serial/8250/8250_dw.c -+++ b/drivers/tty/serial/8250/8250_dw.c -@@ -34,22 +34,11 @@ - - #include "8250_dwlib.h" - --/* Offsets for the DesignWare specific registers */ --#define DW_UART_USR 0x1f /* UART Status Register */ --#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ -- - #define OCTEON_UART_USR 0x27 /* UART Status Register */ - - #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */ - #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ - --/* DesignWare specific register fields */ --#define DW_UART_IIR_IID GENMASK(3, 0) -- --#define DW_UART_MCR_SIRE BIT(6) -- --#define DW_UART_USR_BUSY BIT(0) -- - /* Renesas specific register fields */ - #define RZN1_UART_xDMACR_DMA_EN BIT(0) - #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1) -diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c -index b055d89cfb39..8859e66d2d71 100644 ---- a/drivers/tty/serial/8250/8250_dwlib.c -+++ b/drivers/tty/serial/8250/8250_dwlib.c -@@ -13,55 +13,6 @@ - - #include "8250_dwlib.h" - --/* Offsets for the DesignWare specific registers */ --#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ --#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ --#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ --#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ --#define DW_UART_RAR 0xc4 /* Receive Address Register */ --#define DW_UART_TAR 0xc8 /* Transmit Address Register */ --#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ --#define DW_UART_CPR 0xf4 /* Component Parameter Register */ --#define DW_UART_UCV 0xf8 /* UART Component Version */ -- --/* Receive / Transmit Address Register bits */ --#define DW_UART_ADDR_MASK GENMASK(7, 0) -- --/* Line Status Register bits */ --#define DW_UART_LSR_ADDR_RCVD BIT(8) -- --/* Transceiver Control Register bits */ --#define DW_UART_TCR_RS485_EN BIT(0) --#define DW_UART_TCR_RE_POL BIT(1) --#define DW_UART_TCR_DE_POL BIT(2) --#define DW_UART_TCR_XFER_MODE GENMASK(4, 3) --#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) --#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) --#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) -- --/* Line Extended Control Register bits */ --#define DW_UART_LCR_EXT_DLS_E BIT(0) --#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) --#define DW_UART_LCR_EXT_SEND_ADDR BIT(2) --#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) -- --/* Component Parameter Register bits */ --#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) --#define DW_UART_CPR_AFCE_MODE BIT(4) --#define DW_UART_CPR_THRE_MODE BIT(5) --#define DW_UART_CPR_SIR_MODE BIT(6) --#define DW_UART_CPR_SIR_LP_MODE BIT(7) --#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) --#define DW_UART_CPR_FIFO_ACCESS BIT(9) --#define DW_UART_CPR_FIFO_STAT BIT(10) --#define DW_UART_CPR_SHADOW BIT(11) --#define DW_UART_CPR_ENCODED_PARMS BIT(12) --#define DW_UART_CPR_DMA_EXTRA BIT(13) --#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) -- --/* Helper for FIFO size calculation */ --#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) -- - /* - * divisor = div(I) + div(F) - * "I" means integer, "F" means fractional -diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h -index 7dd2a8e7b780..2f26f9ecacbe 100644 ---- a/drivers/tty/serial/8250/8250_dwlib.h -+++ b/drivers/tty/serial/8250/8250_dwlib.h -@@ -1,11 +1,76 @@ - /* SPDX-License-Identifier: GPL-2.0+ */ - /* Synopsys DesignWare 8250 library header file. */ - -+#ifndef _SERIAL_8250_DWLIB_H_ -+#define _SERIAL_8250_DWLIB_H_ -+ -+#include -+#include - #include - #include - - #include "8250.h" - -+/* Offsets for the DesignWare specific registers */ -+#define DW_UART_USR 0x1f /* UART Status Register */ -+#define DW_UART_DMASA 0xa8 /* DMA Software Ack */ -+#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ -+#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ -+#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ -+#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ -+#define DW_UART_RAR 0xc4 /* Receive Address Register */ -+#define DW_UART_TAR 0xc8 /* Transmit Address Register */ -+#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ -+#define DW_UART_CPR 0xf4 /* Component Parameter Register */ -+#define DW_UART_UCV 0xf8 /* UART Component Version */ -+ -+/* Interrupt ID Register bits */ -+#define DW_UART_IIR_IID GENMASK(3, 0) -+ -+/* Modem Control Register bits */ -+#define DW_UART_MCR_SIRE BIT(6) -+ -+/* Line Status Register bits */ -+#define DW_UART_LSR_ADDR_RCVD BIT(8) -+ -+/* UART Status Register bits */ -+#define DW_UART_USR_BUSY BIT(0) -+ -+/* Transceiver Control Register bits */ -+#define DW_UART_TCR_RS485_EN BIT(0) -+#define DW_UART_TCR_RE_POL BIT(1) -+#define DW_UART_TCR_DE_POL BIT(2) -+#define DW_UART_TCR_XFER_MODE GENMASK(4, 3) -+#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) -+#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) -+#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) -+ -+/* Receive / Transmit Address Register bits */ -+#define DW_UART_ADDR_MASK GENMASK(7, 0) -+ -+/* Line Extended Control Register bits */ -+#define DW_UART_LCR_EXT_DLS_E BIT(0) -+#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) -+#define DW_UART_LCR_EXT_SEND_ADDR BIT(2) -+#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) -+ -+/* Component Parameter Register bits */ -+#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) -+#define DW_UART_CPR_AFCE_MODE BIT(4) -+#define DW_UART_CPR_THRE_MODE BIT(5) -+#define DW_UART_CPR_SIR_MODE BIT(6) -+#define DW_UART_CPR_SIR_LP_MODE BIT(7) -+#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) -+#define DW_UART_CPR_FIFO_ACCESS BIT(9) -+#define DW_UART_CPR_FIFO_STAT BIT(10) -+#define DW_UART_CPR_SHADOW BIT(11) -+#define DW_UART_CPR_ENCODED_PARMS BIT(12) -+#define DW_UART_CPR_DMA_EXTRA BIT(13) -+#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) -+ -+/* Helper for FIFO size calculation */ -+#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) -+ - struct dw8250_port_data { - /* Port properties */ - int line; -@@ -38,3 +103,5 @@ static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg) - else - writel(reg, p->membase + offset); - } -+ -+#endif /* _SERIAL_8250_DWLIB_H_ */ --- -2.53.0 - diff --git a/SPECS/linux/0139-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch b/SPECS/linux/0139-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch new file mode 100644 index 0000000000..08b007d216 --- /dev/null +++ b/SPECS/linux/0139-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch @@ -0,0 +1,32 @@ +From e9f2699713d75d3fbfd2af658ef3ef2e5ee30301 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 28 Apr 2026 13:26:28 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: serial: snps-dw-apb-uart: Add + UltraRISC DP1000 UART + +UltraRISC DP1000 integrates a Synopsys DesignWare APB UART, but it does +not provide the standard CPR and UCV registers. + +Signed-off-by: Jia Wang +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-3-97de63b1e3eb@ultrarisc.com +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +index 6efe43089a74..f84600f66df8 100644 +--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml ++++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +@@ -77,6 +77,7 @@ properties: + - starfive,jh7100-hsuart + - starfive,jh7100-uart + - starfive,jh7110-uart ++ - ultrarisc,dp1000-uart + - const: snps,dw-apb-uart + - const: snps,dw-apb-uart + +-- +2.53.0 + diff --git a/SPECS/linux/0139-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch b/SPECS/linux/0139-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch deleted file mode 100644 index ac282470b2..0000000000 --- a/SPECS/linux/0139-FROMLIST-serial-8250_dw-build-Renesas-RZN1-CPR-value.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 39c2888c6ba610ef47ee68f885afa8a1cd57177e Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 28 Apr 2026 13:26:27 +0800 -Subject: [PATCH 139/269] FROMLIST: serial: 8250_dw: build Renesas RZN1 CPR - value from DW_UART_CPR_* definitions - -Replace the magic CPR value for Renesas RZ/N1 with a composition using -DW_UART_CPR_* bit/field definitions and FIELD_PREP_CONST(). - -Introduce a helper macro to convert a FIFO size (bytes) into the CPR -FIFO_MODE field value, with BUILD_BUG_ON_ZERO() checks for alignment and -bounds. Use it to replace the literal FIFO_MODE values in the RZN1. - -Signed-off-by: Jia Wang -Reviewed-by: Andy Shevchenko -Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-2-97de63b1e3eb@ultrarisc.com -Signed-off-by: Han Gao ---- - drivers/tty/serial/8250/8250_dw.c | 11 ++++++++++- - drivers/tty/serial/8250/8250_dwlib.h | 7 +++++++ - 2 files changed, 17 insertions(+), 1 deletion(-) - -diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c -index 467755bf0092..5cf3bb74b285 100644 ---- a/drivers/tty/serial/8250/8250_dw.c -+++ b/drivers/tty/serial/8250/8250_dw.c -@@ -937,7 +937,16 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = { - - static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { - .usr_reg = DW_UART_USR, -- .cpr_value = 0x00012f32, -+ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | -+ DW_UART_CPR_AFCE_MODE | -+ DW_UART_CPR_THRE_MODE | -+ DW_UART_CPR_ADDITIONAL_FEATURES | -+ DW_UART_CPR_FIFO_ACCESS | -+ DW_UART_CPR_FIFO_STAT | -+ DW_UART_CPR_SHADOW | -+ DW_UART_CPR_DMA_EXTRA | -+ FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, -+ DW_UART_CPR_FIFO_MODE_FROM_SIZE(16)), - .quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC, - }; - -diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h -index 2f26f9ecacbe..c1f87cd42ecc 100644 ---- a/drivers/tty/serial/8250/8250_dwlib.h -+++ b/drivers/tty/serial/8250/8250_dwlib.h -@@ -6,6 +6,8 @@ - - #include - #include -+#include -+#include - #include - #include - -@@ -70,6 +72,11 @@ - - /* Helper for FIFO size calculation */ - #define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) -+#define DW_UART_CPR_FIFO_MODE_MAX 0x80 -+#define DW_UART_CPR_FIFO_MODE_FROM_SIZE(size) \ -+ (BUILD_BUG_ON_ZERO(!IS_ALIGNED((size), 16)) + \ -+ BUILD_BUG_ON_ZERO(((size) / 16) > DW_UART_CPR_FIFO_MODE_MAX) + \ -+ ((size) / 16)) - - struct dw8250_port_data { - /* Port properties */ --- -2.53.0 - diff --git a/SPECS/linux/0140-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch b/SPECS/linux/0140-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch deleted file mode 100644 index ac0dd8d0a1..0000000000 --- a/SPECS/linux/0140-FROMLIST-dt-bindings-serial-snps-dw-apb-uart-Add-Ult.patch +++ /dev/null @@ -1,32 +0,0 @@ -From babb0a7321dac7cb22438c4491e49c4c5dcaf9e8 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 28 Apr 2026 13:26:28 +0800 -Subject: [PATCH 140/269] FROMLIST: dt-bindings: serial: snps-dw-apb-uart: Add - UltraRISC DP1000 UART - -UltraRISC DP1000 integrates a Synopsys DesignWare APB UART, but it does -not provide the standard CPR and UCV registers. - -Signed-off-by: Jia Wang -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-3-97de63b1e3eb@ultrarisc.com -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml -index 6efe43089a74..f84600f66df8 100644 ---- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml -+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml -@@ -77,6 +77,7 @@ properties: - - starfive,jh7100-hsuart - - starfive,jh7100-uart - - starfive,jh7110-uart -+ - ultrarisc,dp1000-uart - - const: snps,dw-apb-uart - - const: snps,dw-apb-uart - --- -2.53.0 - diff --git a/SPECS/linux/0140-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch b/SPECS/linux/0140-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch new file mode 100644 index 0000000000..da0c498a26 --- /dev/null +++ b/SPECS/linux/0140-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch @@ -0,0 +1,52 @@ +From c4e8f76e621f53412ee8a11e088ada66a92bed4d Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 28 Apr 2026 13:26:29 +0800 +Subject: [RUYI PATCH] FROMLIST: serial: 8250_dw: Use a fixed CPR value for + UltraRISC DP1000 UART + +The UltraRISC DP1000 UART does not provide the standard CPR register used +by 8250_dw to discover port capabilities. + +Provide a fixed CPR value for the DP1000-specific compatible so the +driver can configure the port correctly. + +Signed-off-by: Jia Wang +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-4-97de63b1e3eb@ultrarisc.com +Signed-off-by: Han Gao +--- + drivers/tty/serial/8250/8250_dw.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c +index 5cf3bb74b285..6fa7c8440919 100644 +--- a/drivers/tty/serial/8250/8250_dw.c ++++ b/drivers/tty/serial/8250/8250_dw.c +@@ -960,6 +960,16 @@ static const struct dw8250_platform_data dw8250_intc10ee = { + .quirks = DW_UART_QUIRK_IER_KICK, + }; + ++static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = { ++ .usr_reg = DW_UART_USR, ++ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | ++ DW_UART_CPR_THRE_MODE | ++ DW_UART_CPR_DMA_EXTRA | ++ FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, ++ DW_UART_CPR_FIFO_MODE_FROM_SIZE(32)), ++ .quirks = DW_UART_QUIRK_CPR_VALUE, ++}; ++ + static const struct of_device_id dw8250_of_match[] = { + { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, + { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, +@@ -967,6 +977,7 @@ static const struct of_device_id dw8250_of_match[] = { + { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, + { .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data }, + { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, ++ { .compatible = "ultrarisc,dp1000-uart", .data = &dw8250_ultrarisc_dp1000_data }, + { /* Sentinel */ } + }; + MODULE_DEVICE_TABLE(of, dw8250_of_match); +-- +2.53.0 + diff --git a/SPECS/linux/0141-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch b/SPECS/linux/0141-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch new file mode 100644 index 0000000000..7db751bf74 --- /dev/null +++ b/SPECS/linux/0141-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch @@ -0,0 +1,84 @@ +From 131debb680565f50ee2525b83e97b04e46b00545 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Tue, 17 Mar 2026 16:48:06 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: disable local interrupts and stop other + CPUs before reboot/shutdown + +Currently, the RISC-V implementation of machine_restart(), machine_halt(), +and machine_power_off() invokes the kernel teardown chains (e.g., +do_kernel_restart()) with local interrupts enabled and other CPUs still +running. + +This implementation fails to provide a deterministic execution environment +for registered handlers in the restart or power-off notifier chains. These +chains are intended to be executed in a strict atomic and single-threaded +context. + +Specifically, under CONFIG_PREEMPT_RCU, rcu_read_lock() does not increment +the preempt_count. If local interrupts remain enabled, the environment +is not guaranteed to be atomic. This can lead to a context misidentification +within generic kernel teardown code, causing it to incorrectly enter +non-atomic paths (such as attempting to acquire sleeping locks), which +results in fatal "scheduling while atomic" splats or system hangs. + +Additionally, stopping other CPUs ensures the primary CPU has exclusive +access to the hardware state during the final teardown phase, preventing +unpredictable interference from other active cores. + +Align RISC-V with other major architectures by disabling local interrupts +and stopping other CPUs at the beginning of the shutdown sequences. This +guarantees the architectural expectations of the kernel's restart and +power-off handlers are met. + +Signed-off-by: Troy Mitchell +Tested-by: Aurelien Jarno +Link: https://lore.kernel.org/all/abEP80FoCn4S4-WG@aurel32.net/ [1] +Link: https://lore.kernel.org/r/20260317-v7-0-rc1-rv-dis-int-before-restart-v2-1-0ecc85fbb7ff@linux.dev +Signed-off-by: Han Gao +--- + arch/riscv/kernel/reset.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/riscv/kernel/reset.c b/arch/riscv/kernel/reset.c +index 912288572226..8c48466c50e9 100644 +--- a/arch/riscv/kernel/reset.c ++++ b/arch/riscv/kernel/reset.c +@@ -5,6 +5,7 @@ + + #include + #include ++#include + + static void default_power_off(void) + { +@@ -17,18 +18,27 @@ EXPORT_SYMBOL(pm_power_off); + + void machine_restart(char *cmd) + { ++ local_irq_disable(); ++ smp_send_stop(); ++ + do_kernel_restart(cmd); + while (1); + } + + void machine_halt(void) + { ++ local_irq_disable(); ++ smp_send_stop(); ++ + do_kernel_power_off(); + default_power_off(); + } + + void machine_power_off(void) + { ++ local_irq_disable(); ++ smp_send_stop(); ++ + do_kernel_power_off(); + default_power_off(); + } +-- +2.53.0 + diff --git a/SPECS/linux/0141-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch b/SPECS/linux/0141-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch deleted file mode 100644 index b9c3380733..0000000000 --- a/SPECS/linux/0141-FROMLIST-serial-8250_dw-Use-a-fixed-CPR-value-for-Ul.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 10f1d34297dfbadb9eea6a28c96d5c809aa20f91 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 28 Apr 2026 13:26:29 +0800 -Subject: [PATCH 141/269] FROMLIST: serial: 8250_dw: Use a fixed CPR value for - UltraRISC DP1000 UART - -The UltraRISC DP1000 UART does not provide the standard CPR register used -by 8250_dw to discover port capabilities. - -Provide a fixed CPR value for the DP1000-specific compatible so the -driver can configure the port correctly. - -Signed-off-by: Jia Wang -Reviewed-by: Andy Shevchenko -Link: https://lore.kernel.org/r/20260428-ultrarisc-serial-v5-4-97de63b1e3eb@ultrarisc.com -Signed-off-by: Han Gao ---- - drivers/tty/serial/8250/8250_dw.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c -index 5cf3bb74b285..6fa7c8440919 100644 ---- a/drivers/tty/serial/8250/8250_dw.c -+++ b/drivers/tty/serial/8250/8250_dw.c -@@ -960,6 +960,16 @@ static const struct dw8250_platform_data dw8250_intc10ee = { - .quirks = DW_UART_QUIRK_IER_KICK, - }; - -+static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = { -+ .usr_reg = DW_UART_USR, -+ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | -+ DW_UART_CPR_THRE_MODE | -+ DW_UART_CPR_DMA_EXTRA | -+ FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, -+ DW_UART_CPR_FIFO_MODE_FROM_SIZE(32)), -+ .quirks = DW_UART_QUIRK_CPR_VALUE, -+}; -+ - static const struct of_device_id dw8250_of_match[] = { - { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb }, - { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data }, -@@ -967,6 +977,7 @@ static const struct of_device_id dw8250_of_match[] = { - { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data }, - { .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data }, - { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data }, -+ { .compatible = "ultrarisc,dp1000-uart", .data = &dw8250_ultrarisc_dp1000_data }, - { /* Sentinel */ } - }; - MODULE_DEVICE_TABLE(of, dw8250_of_match); --- -2.53.0 - diff --git a/SPECS/linux/0142-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch b/SPECS/linux/0142-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch new file mode 100644 index 0000000000..ad1d2cab5a --- /dev/null +++ b/SPECS/linux/0142-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch @@ -0,0 +1,39 @@ +From 5f2aefa86c8ab39b1e1e3d1022f5e1bd16898f49 Mon Sep 17 00:00:00 2001 +From: Felix Gu +Date: Sat, 21 Mar 2026 03:12:10 +0800 +Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix error check on + dw_hdmi_probe() return value + +The error check after calling dw_hdmi_probe() was incorrectly checking +the struct pointer hdmi instead of the probe result hdmi->dw_hdmi. + +Fix this by checking the correct variable. + +Fixes: 96f30ee0fb9d ("drm/bridge: add a driver for T-Head TH1520 HDMI controller") +Signed-off-by: Felix Gu +Reviewed-by: Dmitry Baryshkov +Reviewed-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260321-th1520-v1-1-ec877197770d@gmail.com +Signed-off-by: Han Gao +--- + drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +index 389eead5f1c4..c9968ec1823c 100644 +--- a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +@@ -136,8 +136,8 @@ static int th1520_dw_hdmi_probe(struct platform_device *pdev) + plat_data->priv_data = hdmi; + + hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); +- if (IS_ERR(hdmi)) +- return PTR_ERR(hdmi); ++ if (IS_ERR(hdmi->dw_hdmi)) ++ return PTR_ERR(hdmi->dw_hdmi); + + platform_set_drvdata(pdev, hdmi); + +-- +2.53.0 + diff --git a/SPECS/linux/0142-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch b/SPECS/linux/0142-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch deleted file mode 100644 index 9caf4ff05b..0000000000 --- a/SPECS/linux/0142-FROMLIST-riscv-disable-local-interrupts-and-stop-oth.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 5dd50075a3c2fe22bfb8fefd766c5c1a389cd284 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Tue, 17 Mar 2026 16:48:06 +0800 -Subject: [PATCH 142/269] FROMLIST: riscv: disable local interrupts and stop - other CPUs before reboot/shutdown - -Currently, the RISC-V implementation of machine_restart(), machine_halt(), -and machine_power_off() invokes the kernel teardown chains (e.g., -do_kernel_restart()) with local interrupts enabled and other CPUs still -running. - -This implementation fails to provide a deterministic execution environment -for registered handlers in the restart or power-off notifier chains. These -chains are intended to be executed in a strict atomic and single-threaded -context. - -Specifically, under CONFIG_PREEMPT_RCU, rcu_read_lock() does not increment -the preempt_count. If local interrupts remain enabled, the environment -is not guaranteed to be atomic. This can lead to a context misidentification -within generic kernel teardown code, causing it to incorrectly enter -non-atomic paths (such as attempting to acquire sleeping locks), which -results in fatal "scheduling while atomic" splats or system hangs. - -Additionally, stopping other CPUs ensures the primary CPU has exclusive -access to the hardware state during the final teardown phase, preventing -unpredictable interference from other active cores. - -Align RISC-V with other major architectures by disabling local interrupts -and stopping other CPUs at the beginning of the shutdown sequences. This -guarantees the architectural expectations of the kernel's restart and -power-off handlers are met. - -Signed-off-by: Troy Mitchell -Tested-by: Aurelien Jarno -Link: https://lore.kernel.org/all/abEP80FoCn4S4-WG@aurel32.net/ [1] -Link: https://lore.kernel.org/r/20260317-v7-0-rc1-rv-dis-int-before-restart-v2-1-0ecc85fbb7ff@linux.dev -Signed-off-by: Han Gao ---- - arch/riscv/kernel/reset.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/riscv/kernel/reset.c b/arch/riscv/kernel/reset.c -index 912288572226..8c48466c50e9 100644 ---- a/arch/riscv/kernel/reset.c -+++ b/arch/riscv/kernel/reset.c -@@ -5,6 +5,7 @@ - - #include - #include -+#include - - static void default_power_off(void) - { -@@ -17,18 +18,27 @@ EXPORT_SYMBOL(pm_power_off); - - void machine_restart(char *cmd) - { -+ local_irq_disable(); -+ smp_send_stop(); -+ - do_kernel_restart(cmd); - while (1); - } - - void machine_halt(void) - { -+ local_irq_disable(); -+ smp_send_stop(); -+ - do_kernel_power_off(); - default_power_off(); - } - - void machine_power_off(void) - { -+ local_irq_disable(); -+ smp_send_stop(); -+ - do_kernel_power_off(); - default_power_off(); - } --- -2.53.0 - diff --git a/SPECS/linux/0143-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch b/SPECS/linux/0143-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch deleted file mode 100644 index 50d8d31ab2..0000000000 --- a/SPECS/linux/0143-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-error-check-o.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 0c3c70a4e3ecac979a30390e88135d285dcfaee2 Mon Sep 17 00:00:00 2001 -From: Felix Gu -Date: Sat, 21 Mar 2026 03:12:10 +0800 -Subject: [PATCH 143/269] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix error check - on dw_hdmi_probe() return value - -The error check after calling dw_hdmi_probe() was incorrectly checking -the struct pointer hdmi instead of the probe result hdmi->dw_hdmi. - -Fix this by checking the correct variable. - -Fixes: 96f30ee0fb9d ("drm/bridge: add a driver for T-Head TH1520 HDMI controller") -Signed-off-by: Felix Gu -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260321-th1520-v1-1-ec877197770d@gmail.com -Signed-off-by: Han Gao ---- - drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -index 389eead5f1c4..c9968ec1823c 100644 ---- a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -@@ -136,8 +136,8 @@ static int th1520_dw_hdmi_probe(struct platform_device *pdev) - plat_data->priv_data = hdmi; - - hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); -- if (IS_ERR(hdmi)) -- return PTR_ERR(hdmi); -+ if (IS_ERR(hdmi->dw_hdmi)) -+ return PTR_ERR(hdmi->dw_hdmi); - - platform_set_drvdata(pdev, hdmi); - --- -2.53.0 - diff --git a/SPECS/linux/0143-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch b/SPECS/linux/0143-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch new file mode 100644 index 0000000000..855db71c4c --- /dev/null +++ b/SPECS/linux/0143-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch @@ -0,0 +1,43 @@ +From b5f3e1b5bd3d82b9b5a0221d6a962b3aa6033743 Mon Sep 17 00:00:00 2001 +From: Felix Gu +Date: Sat, 21 Mar 2026 03:12:11 +0800 +Subject: [RUYI PATCH] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix remove() + callback + +This driver stores struct th1520_hdmi * in platform drvdata, but +th1520_dw_hdmi_remove() was reading it back as struct dw_hdmi * +and passing it to dw_hdmi_remove(), so teardown runs on the wrong +pointer. + +Retrieve struct th1520_hdmi * from platform drvdata and pass +hdmi->dw_hdmi to dw_hdmi_remove(). + +Fixes: 96f30ee0fb9d ("drm/bridge: add a driver for T-Head TH1520 HDMI controller") +Signed-off-by: Felix Gu +Reviewed-by: Dmitry Baryshkov +Reviewed-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260321-th1520-v1-2-ec877197770d@gmail.com +Signed-off-by: Han Gao +--- + drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +index c9968ec1823c..6ec9003a8f3f 100644 +--- a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c +@@ -146,9 +146,9 @@ static int th1520_dw_hdmi_probe(struct platform_device *pdev) + + static void th1520_dw_hdmi_remove(struct platform_device *pdev) + { +- struct dw_hdmi *hdmi = platform_get_drvdata(pdev); ++ struct th1520_hdmi *hdmi = platform_get_drvdata(pdev); + +- dw_hdmi_remove(hdmi); ++ dw_hdmi_remove(hdmi->dw_hdmi); + } + + static const struct of_device_id th1520_dw_hdmi_of_table[] = { +-- +2.53.0 + diff --git a/SPECS/linux/0144-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch b/SPECS/linux/0144-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch deleted file mode 100644 index 0e50864ebf..0000000000 --- a/SPECS/linux/0144-FROMLIST-drm-bridge-th1520-dw-hdmi-Fix-remove-callba.patch +++ /dev/null @@ -1,43 +0,0 @@ -From f4cc5e60f5930e3ede96e55e0e4119dcacb45d59 Mon Sep 17 00:00:00 2001 -From: Felix Gu -Date: Sat, 21 Mar 2026 03:12:11 +0800 -Subject: [PATCH 144/269] FROMLIST: drm/bridge: th1520-dw-hdmi: Fix remove() - callback - -This driver stores struct th1520_hdmi * in platform drvdata, but -th1520_dw_hdmi_remove() was reading it back as struct dw_hdmi * -and passing it to dw_hdmi_remove(), so teardown runs on the wrong -pointer. - -Retrieve struct th1520_hdmi * from platform drvdata and pass -hdmi->dw_hdmi to dw_hdmi_remove(). - -Fixes: 96f30ee0fb9d ("drm/bridge: add a driver for T-Head TH1520 HDMI controller") -Signed-off-by: Felix Gu -Reviewed-by: Dmitry Baryshkov -Reviewed-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260321-th1520-v1-2-ec877197770d@gmail.com -Signed-off-by: Han Gao ---- - drivers/gpu/drm/bridge/th1520-dw-hdmi.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -index c9968ec1823c..6ec9003a8f3f 100644 ---- a/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/th1520-dw-hdmi.c -@@ -146,9 +146,9 @@ static int th1520_dw_hdmi_probe(struct platform_device *pdev) - - static void th1520_dw_hdmi_remove(struct platform_device *pdev) - { -- struct dw_hdmi *hdmi = platform_get_drvdata(pdev); -+ struct th1520_hdmi *hdmi = platform_get_drvdata(pdev); - -- dw_hdmi_remove(hdmi); -+ dw_hdmi_remove(hdmi->dw_hdmi); - } - - static const struct of_device_id th1520_dw_hdmi_of_table[] = { --- -2.53.0 - diff --git a/SPECS/linux/0144-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux/0144-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch new file mode 100644 index 0000000000..ee635c7005 --- /dev/null +++ b/SPECS/linux/0144-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch @@ -0,0 +1,35 @@ +From 700995cb9d605ce5b3366518752a851af8d3326c Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Tue, 7 Apr 2026 23:28:14 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Enable i2c8 adapter for + OrangePi RV2 + +The adapter is used to access the SpacemiT P1 PMIC present in this board. + +Tested-by: Vincent Legoll # OrangePi-RV2 +Link: https://lore.kernel.org/r/d66f897b179271f508ac5352e52b1223f3bca5fb.1775575436.git.gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 7b7331cb3c72..57ec1cc32b03 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -87,6 +87,12 @@ &pdma { + status = "okay"; + }; + ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8_cfg>; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux/0145-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux/0145-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch new file mode 100644 index 0000000000..90ef2c1156 --- /dev/null +++ b/SPECS/linux/0145-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch @@ -0,0 +1,171 @@ +From 56f4ec657e083a7aaffa8767283dd189218c43b2 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Tue, 7 Apr 2026 23:28:15 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Define the P1 PMIC + regulators for OrangePi RV2 + +Define the DC power input and the 4v power as fixed regulator supplies. + +Define the SpacemiT P1 PMIC voltage regulators and their constraints. + +Co-developed-by: Chukun Pan +Signed-off-by: Chukun Pan +Tested-by: Vincent Legoll # OrangePi-RV2 +Link: https://lore.kernel.org/r/193370a69e1cc3e4d8c4eb57bfea208e29ac75d8.1775575436.git.gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 131 ++++++++++++++++++ + 1 file changed, 131 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 57ec1cc32b03..f7a1dadaa95f 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -23,6 +23,25 @@ chosen { + stdout-path = "serial0"; + }; + ++ vcc_5v0: regulator-vcc-5v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_5v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc4v0: regulator-vcc4v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc4v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ vin-supply = <&vcc_5v0>; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -91,6 +110,118 @@ &i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; + status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ vin1-supply = <&vcc4v0>; ++ vin2-supply = <&vcc4v0>; ++ vin3-supply = <&vcc4v0>; ++ vin4-supply = <&vcc4v0>; ++ vin5-supply = <&vcc4v0>; ++ vin6-supply = <&vcc4v0>; ++ aldoin-supply = <&vcc4v0>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; ++ ++ regulators { ++ buck1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3_1v8: buck3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4_3v3: buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ aldo2 { ++ /* not connected */ ++ }; ++ ++ aldo3 { ++ /* not connected */ ++ }; ++ ++ aldo4 { ++ /* not connected */ ++ }; ++ ++ dldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ dldo2 { ++ /* not connected */ ++ }; ++ ++ dldo3 { ++ /* not connected */ ++ }; ++ ++ dldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo7 { ++ /* not connected */ ++ }; ++ }; ++ }; + }; + + &uart0 { +-- +2.53.0 + diff --git a/SPECS/linux/0145-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch b/SPECS/linux/0145-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch deleted file mode 100644 index 0e9c120ca8..0000000000 --- a/SPECS/linux/0145-FROMLIST-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch +++ /dev/null @@ -1,35 +0,0 @@ -From aa0efe15dee89d51832adf1cf57ec4a170d5e8c9 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Tue, 7 Apr 2026 23:28:14 +0800 -Subject: [PATCH 145/269] FROMLIST: riscv: dts: spacemit: Enable i2c8 adapter - for OrangePi RV2 - -The adapter is used to access the SpacemiT P1 PMIC present in this board. - -Tested-by: Vincent Legoll # OrangePi-RV2 -Link: https://lore.kernel.org/r/d66f897b179271f508ac5352e52b1223f3bca5fb.1775575436.git.gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 7b7331cb3c72..57ec1cc32b03 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -87,6 +87,12 @@ &pdma { - status = "okay"; - }; - -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux/0146-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch b/SPECS/linux/0146-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch deleted file mode 100644 index 69771bdcc9..0000000000 --- a/SPECS/linux/0146-FROMLIST-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch +++ /dev/null @@ -1,171 +0,0 @@ -From bd90155ca797fae5beba5173554c2cb0562d7fe3 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Tue, 7 Apr 2026 23:28:15 +0800 -Subject: [PATCH 146/269] FROMLIST: riscv: dts: spacemit: Define the P1 PMIC - regulators for OrangePi RV2 - -Define the DC power input and the 4v power as fixed regulator supplies. - -Define the SpacemiT P1 PMIC voltage regulators and their constraints. - -Co-developed-by: Chukun Pan -Signed-off-by: Chukun Pan -Tested-by: Vincent Legoll # OrangePi-RV2 -Link: https://lore.kernel.org/r/193370a69e1cc3e4d8c4eb57bfea208e29ac75d8.1775575436.git.gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-rv2.dts | 131 ++++++++++++++++++ - 1 file changed, 131 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 57ec1cc32b03..f7a1dadaa95f 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -23,6 +23,25 @@ chosen { - stdout-path = "serial0"; - }; - -+ vcc_5v0: regulator-vcc-5v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_5v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ vcc4v0: regulator-vcc4v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc4v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ vin-supply = <&vcc_5v0>; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -91,6 +110,118 @@ &i2c8 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_cfg>; - status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin1-supply = <&vcc4v0>; -+ vin2-supply = <&vcc4v0>; -+ vin3-supply = <&vcc4v0>; -+ vin4-supply = <&vcc4v0>; -+ vin5-supply = <&vcc4v0>; -+ vin6-supply = <&vcc4v0>; -+ aldoin-supply = <&vcc4v0>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; -+ -+ regulators { -+ buck1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3_1v8: buck3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4_3v3: buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ aldo2 { -+ /* not connected */ -+ }; -+ -+ aldo3 { -+ /* not connected */ -+ }; -+ -+ aldo4 { -+ /* not connected */ -+ }; -+ -+ dldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ dldo2 { -+ /* not connected */ -+ }; -+ -+ dldo3 { -+ /* not connected */ -+ }; -+ -+ dldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo7 { -+ /* not connected */ -+ }; -+ }; -+ }; - }; - - &uart0 { --- -2.53.0 - diff --git a/SPECS/linux/0146-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch b/SPECS/linux/0146-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch new file mode 100644 index 0000000000..b0d14d8271 --- /dev/null +++ b/SPECS/linux/0146-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch @@ -0,0 +1,140 @@ +From 5d0f24dd65b72dbb618134d237e6499604fb1d4d Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Tue, 7 Apr 2026 23:28:16 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Enable USB3.0/PCIe on + OrangePi RV2 + +Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the +OrangePi RV2 board. + +The board utilizes a Genesys Logic GL3523 USB3.0 hub. + +Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and +PHY-related Device Tree nodes for the OrangePi RV2. + +Co-developed-by: Chukun Pan +Signed-off-by: Chukun Pan +Tested-by: Vincent Legoll # OrangePi-RV2 +Link: https://lore.kernel.org/r/8e397efb06efd9b02788df07f435ce153de05cd5.1775575436.git.gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 80 +++++++++++++++++++ + 1 file changed, 80 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index f7a1dadaa95f..3a829e3c9cbc 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -23,6 +23,16 @@ chosen { + stdout-path = "serial0"; + }; + ++ pcie_vcc3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>; ++ regulator-name = "pcie_vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_5v0>; ++ }; ++ + vcc_5v0: regulator-vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; +@@ -42,6 +52,16 @@ vcc4v0: regulator-vcc4v0 { + vin-supply = <&vcc_5v0>; + }; + ++ vcc5v0_usb30: regulator-vcc5v0-usb30 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; ++ regulator-name = "vcc5v0_usb30"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_5v0>; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -54,6 +74,10 @@ led1 { + }; + }; + ++&combo_phy { ++ status = "okay"; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +@@ -224,8 +248,64 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie2 { ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ vbus-supply = <&vcc5v0_usb30>; ++ status = "okay"; ++ ++ hub_2_0: hub@1 { ++ compatible = "usb5e3,610"; ++ reg = <0x1>; ++ peer-hub = <&hub_3_0>; ++ vdd-supply = <&vcc_5v0>; ++ }; ++ ++ hub_3_0: hub@2 { ++ compatible = "usb5e3,620"; ++ reg = <0x2>; ++ peer-hub = <&hub_2_0>; ++ vdd-supply = <&vcc_5v0>; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux/0147-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch b/SPECS/linux/0147-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch new file mode 100644 index 0000000000..b863322935 --- /dev/null +++ b/SPECS/linux/0147-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch @@ -0,0 +1,40 @@ +From d0837aaa4d6a3063a6b97a5535f6679b1933032f Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Mon, 18 May 2026 11:32:41 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: dmaengine: Add SpacemiT K3 DMA + compatible string + +Add the "spacemit,k3-pdma" compatible string for the SpacemiT K3 SoC. + +While the K3 PDMA IP reuses most of the design found on the earlier +K1 SoC, a new compatible string is required because the DRCMR +(DMA Request/Command Register) base address for extended DMA request +numbers (>= 64) differs from the K1 implementation. + +Signed-off-by: Guodong Xu +Acked-by: Conor Dooley +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-1-67fdf319a8f8@linux.spacemit.com +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml +index ec06235baf5c..62ce6d81526b 100644 +--- a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml ++++ b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml +@@ -14,7 +14,9 @@ allOf: + + properties: + compatible: +- const: spacemit,k1-pdma ++ enum: ++ - spacemit,k1-pdma ++ - spacemit,k3-pdma + + reg: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux/0147-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch b/SPECS/linux/0147-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch deleted file mode 100644 index db035fcf76..0000000000 --- a/SPECS/linux/0147-FROMLIST-riscv-dts-spacemit-Enable-USB3.0-PCIe-on-Or.patch +++ /dev/null @@ -1,140 +0,0 @@ -From 038ef50cae35bfa3b89955b6abe063defc86463e Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Tue, 7 Apr 2026 23:28:16 +0800 -Subject: [PATCH 147/269] FROMLIST: riscv: dts: spacemit: Enable USB3.0/PCIe on - OrangePi RV2 - -Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the -OrangePi RV2 board. - -The board utilizes a Genesys Logic GL3523 USB3.0 hub. - -Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and -PHY-related Device Tree nodes for the OrangePi RV2. - -Co-developed-by: Chukun Pan -Signed-off-by: Chukun Pan -Tested-by: Vincent Legoll # OrangePi-RV2 -Link: https://lore.kernel.org/r/8e397efb06efd9b02788df07f435ce153de05cd5.1775575436.git.gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-rv2.dts | 80 +++++++++++++++++++ - 1 file changed, 80 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index f7a1dadaa95f..3a829e3c9cbc 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -23,6 +23,16 @@ chosen { - stdout-path = "serial0"; - }; - -+ pcie_vcc3v3: regulator-pcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>; -+ regulator-name = "pcie_vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_5v0>; -+ }; -+ - vcc_5v0: regulator-vcc-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; -@@ -42,6 +52,16 @@ vcc4v0: regulator-vcc4v0 { - vin-supply = <&vcc_5v0>; - }; - -+ vcc5v0_usb30: regulator-vcc5v0-usb30 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc5v0_usb30"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_5v0>; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -54,6 +74,10 @@ led1 { - }; - }; - -+&combo_phy { -+ status = "okay"; -+}; -+ - ð0 { - phy-handle = <&rgmii0>; - phy-mode = "rgmii-id"; -@@ -224,8 +248,64 @@ dldo7 { - }; - }; - -+&pcie1_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_3_cfg>; -+ status = "okay"; -+}; -+ -+&pcie1_port { -+ phys = <&pcie1_phy>; -+ vpcie3v3-supply = <&pcie_vcc3v3>; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; -+ -+&pcie2_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_4_cfg>; -+ status = "okay"; -+}; -+ -+&pcie2_port { -+ phys = <&pcie2_phy>; -+ vpcie3v3-supply = <&pcie_vcc3v3>; -+}; -+ -+&pcie2 { -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ vbus-supply = <&vcc5v0_usb30>; -+ status = "okay"; -+ -+ hub_2_0: hub@1 { -+ compatible = "usb5e3,610"; -+ reg = <0x1>; -+ peer-hub = <&hub_3_0>; -+ vdd-supply = <&vcc_5v0>; -+ }; -+ -+ hub_3_0: hub@2 { -+ compatible = "usb5e3,620"; -+ reg = <0x2>; -+ peer-hub = <&hub_2_0>; -+ vdd-supply = <&vcc_5v0>; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux/0148-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch b/SPECS/linux/0148-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch new file mode 100644 index 0000000000..b218432893 --- /dev/null +++ b/SPECS/linux/0148-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch @@ -0,0 +1,100 @@ +From 65fb68c807f41ac5e1415fd0a7c5375c481e65e6 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Mon, 18 May 2026 11:32:42 +0800 +Subject: [RUYI PATCH] FROMLIST: dmaengine: mmp_pdma: refactor DRCMR access + with helper function + +Refactor the DRCMR macro into a helper function mmp_pdma_get_drcmr() +to support variable extended DRCMR base addresses across different PDMA +implementations, such as SpacemiT K3. + +Signed-off-by: Guodong Xu +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-2-67fdf319a8f8@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/dma/mmp_pdma.c | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c +index d12e729ee12c..6112369006ee 100644 +--- a/drivers/dma/mmp_pdma.c ++++ b/drivers/dma/mmp_pdma.c +@@ -51,7 +51,9 @@ + #define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ + #define DCSR_EORINTR BIT(9) /* The end of Receive */ + +-#define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + (((n) & 0x3f) << 2)) ++#define DRCMR_BASE 0x0100 ++#define DRCMR_EXT_BASE_DEFAULT 0x1100 ++#define DRCMR_REQ_LIMIT 64 + #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ + #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ + +@@ -154,6 +156,7 @@ struct mmp_pdma_phy { + * @run_bits: Control bits in DCSR register for channel start/stop + * @dma_width: DMA addressing width in bits (32 or 64). Determines the + * DMA mask capability of the controller hardware. ++ * @drcmr_ext_base: Base DRCMR address for extended requests + */ + struct mmp_pdma_ops { + /* Hardware Register Operations */ +@@ -174,6 +177,7 @@ struct mmp_pdma_ops { + /* Controller Configuration */ + u32 run_bits; + u32 dma_width; ++ u32 drcmr_ext_base; + }; + + struct mmp_pdma_device { +@@ -195,6 +199,13 @@ struct mmp_pdma_device { + #define to_mmp_pdma_dev(dmadev) \ + container_of(dmadev, struct mmp_pdma_device, device) + ++static u32 mmp_pdma_get_drcmr(struct mmp_pdma_device *pdev, u32 drcmr) ++{ ++ if (drcmr < DRCMR_REQ_LIMIT) ++ return DRCMR_BASE + (drcmr << 2); ++ return pdev->ops->drcmr_ext_base + ((drcmr - DRCMR_REQ_LIMIT) << 2); ++} ++ + /* For 32-bit PDMA */ + static void write_next_addr_32(struct mmp_pdma_phy *phy, dma_addr_t addr) + { +@@ -301,7 +312,7 @@ static void enable_chan(struct mmp_pdma_phy *phy) + + pdev = to_mmp_pdma_dev(phy->vchan->chan.device); + +- reg = DRCMR(phy->vchan->drcmr); ++ reg = mmp_pdma_get_drcmr(pdev, phy->vchan->drcmr); + writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); + + dalgn = readl(phy->base + DALGN); +@@ -437,7 +448,7 @@ static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan) + return; + + /* clear the channel mapping in DRCMR */ +- reg = DRCMR(pchan->drcmr); ++ reg = mmp_pdma_get_drcmr(pdev, pchan->drcmr); + writel(0, pchan->phy->base + reg); + + spin_lock_irqsave(&pdev->phy_lock, flags); +@@ -1179,6 +1190,7 @@ static const struct mmp_pdma_ops marvell_pdma_v1_ops = { + .get_desc_dst_addr = get_desc_dst_addr_32, + .run_bits = (DCSR_RUN), + .dma_width = 32, ++ .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, + }; + + static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { +@@ -1192,6 +1204,7 @@ static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { + .get_desc_dst_addr = get_desc_dst_addr_64, + .run_bits = (DCSR_RUN | DCSR_LPAEEN), + .dma_width = 64, ++ .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, + }; + + static const struct of_device_id mmp_pdma_dt_ids[] = { +-- +2.53.0 + diff --git a/SPECS/linux/0148-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch b/SPECS/linux/0148-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch deleted file mode 100644 index b3cd4043a4..0000000000 --- a/SPECS/linux/0148-FROMLIST-dt-bindings-dmaengine-Add-SpacemiT-K3-DMA-c.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 160157e79b5b7c5fc765b4fd0935350d8d7e2f48 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Mon, 18 May 2026 11:32:41 +0800 -Subject: [PATCH 148/269] FROMLIST: dt-bindings: dmaengine: Add SpacemiT K3 DMA - compatible string - -Add the "spacemit,k3-pdma" compatible string for the SpacemiT K3 SoC. - -While the K3 PDMA IP reuses most of the design found on the earlier -K1 SoC, a new compatible string is required because the DRCMR -(DMA Request/Command Register) base address for extended DMA request -numbers (>= 64) differs from the K1 implementation. - -Signed-off-by: Guodong Xu -Acked-by: Conor Dooley -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-1-67fdf319a8f8@linux.spacemit.com -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml -index ec06235baf5c..62ce6d81526b 100644 ---- a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml -+++ b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml -@@ -14,7 +14,9 @@ allOf: - - properties: - compatible: -- const: spacemit,k1-pdma -+ enum: -+ - spacemit,k1-pdma -+ - spacemit,k3-pdma - - reg: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux/0149-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch b/SPECS/linux/0149-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch new file mode 100644 index 0000000000..b15e718019 --- /dev/null +++ b/SPECS/linux/0149-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch @@ -0,0 +1,63 @@ +From b8a50cdaa7d0bff7f1b9ec74c15bbe8792f0b5d2 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Mon, 18 May 2026 11:32:43 +0800 +Subject: [RUYI PATCH] FROMLIST: dmaengine: mmp_pdma: add SpacemiT K3 support + +SpacemiT K3 reuses most of the PDMA IP design found on K1, with one +difference being the extended DRCMR base address. Add "spacemit,k3-pdma" +compatible string and define a new mmp_pdma_ops for K3 PDMA. + +Signed-off-by: Guodong Xu +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-3-67fdf319a8f8@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/dma/mmp_pdma.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c +index 6112369006ee..386e85cd4882 100644 +--- a/drivers/dma/mmp_pdma.c ++++ b/drivers/dma/mmp_pdma.c +@@ -52,6 +52,7 @@ + #define DCSR_EORINTR BIT(9) /* The end of Receive */ + + #define DRCMR_BASE 0x0100 ++#define DRCMR_EXT_BASE_K3 0x1000 + #define DRCMR_EXT_BASE_DEFAULT 0x1100 + #define DRCMR_REQ_LIMIT 64 + #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ +@@ -1207,6 +1208,20 @@ static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { + .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, + }; + ++static const struct mmp_pdma_ops spacemit_k3_pdma_ops = { ++ .write_next_addr = write_next_addr_64, ++ .read_src_addr = read_src_addr_64, ++ .read_dst_addr = read_dst_addr_64, ++ .set_desc_next_addr = set_desc_next_addr_64, ++ .set_desc_src_addr = set_desc_src_addr_64, ++ .set_desc_dst_addr = set_desc_dst_addr_64, ++ .get_desc_src_addr = get_desc_src_addr_64, ++ .get_desc_dst_addr = get_desc_dst_addr_64, ++ .run_bits = (DCSR_RUN | DCSR_LPAEEN | DCSR_EORIRQEN | DCSR_EORSTOPEN), ++ .dma_width = 64, ++ .drcmr_ext_base = DRCMR_EXT_BASE_K3, ++}; ++ + static const struct of_device_id mmp_pdma_dt_ids[] = { + { + .compatible = "marvell,pdma-1.0", +@@ -1214,6 +1229,9 @@ static const struct of_device_id mmp_pdma_dt_ids[] = { + }, { + .compatible = "spacemit,k1-pdma", + .data = &spacemit_k1_pdma_ops ++ }, { ++ .compatible = "spacemit,k3-pdma", ++ .data = &spacemit_k3_pdma_ops + }, { + /* sentinel */ + } +-- +2.53.0 + diff --git a/SPECS/linux/0149-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch b/SPECS/linux/0149-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch deleted file mode 100644 index 6ae87c4c57..0000000000 --- a/SPECS/linux/0149-FROMLIST-dmaengine-mmp_pdma-refactor-DRCMR-access-wi.patch +++ /dev/null @@ -1,100 +0,0 @@ -From c77791957eebac9b456023cdd2cf2c43977cb1e5 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Mon, 18 May 2026 11:32:42 +0800 -Subject: [PATCH 149/269] FROMLIST: dmaengine: mmp_pdma: refactor DRCMR access - with helper function - -Refactor the DRCMR macro into a helper function mmp_pdma_get_drcmr() -to support variable extended DRCMR base addresses across different PDMA -implementations, such as SpacemiT K3. - -Signed-off-by: Guodong Xu -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-2-67fdf319a8f8@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/dma/mmp_pdma.c | 19 ++++++++++++++++--- - 1 file changed, 16 insertions(+), 3 deletions(-) - -diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c -index d12e729ee12c..6112369006ee 100644 ---- a/drivers/dma/mmp_pdma.c -+++ b/drivers/dma/mmp_pdma.c -@@ -51,7 +51,9 @@ - #define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ - #define DCSR_EORINTR BIT(9) /* The end of Receive */ - --#define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + (((n) & 0x3f) << 2)) -+#define DRCMR_BASE 0x0100 -+#define DRCMR_EXT_BASE_DEFAULT 0x1100 -+#define DRCMR_REQ_LIMIT 64 - #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ - #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ - -@@ -154,6 +156,7 @@ struct mmp_pdma_phy { - * @run_bits: Control bits in DCSR register for channel start/stop - * @dma_width: DMA addressing width in bits (32 or 64). Determines the - * DMA mask capability of the controller hardware. -+ * @drcmr_ext_base: Base DRCMR address for extended requests - */ - struct mmp_pdma_ops { - /* Hardware Register Operations */ -@@ -174,6 +177,7 @@ struct mmp_pdma_ops { - /* Controller Configuration */ - u32 run_bits; - u32 dma_width; -+ u32 drcmr_ext_base; - }; - - struct mmp_pdma_device { -@@ -195,6 +199,13 @@ struct mmp_pdma_device { - #define to_mmp_pdma_dev(dmadev) \ - container_of(dmadev, struct mmp_pdma_device, device) - -+static u32 mmp_pdma_get_drcmr(struct mmp_pdma_device *pdev, u32 drcmr) -+{ -+ if (drcmr < DRCMR_REQ_LIMIT) -+ return DRCMR_BASE + (drcmr << 2); -+ return pdev->ops->drcmr_ext_base + ((drcmr - DRCMR_REQ_LIMIT) << 2); -+} -+ - /* For 32-bit PDMA */ - static void write_next_addr_32(struct mmp_pdma_phy *phy, dma_addr_t addr) - { -@@ -301,7 +312,7 @@ static void enable_chan(struct mmp_pdma_phy *phy) - - pdev = to_mmp_pdma_dev(phy->vchan->chan.device); - -- reg = DRCMR(phy->vchan->drcmr); -+ reg = mmp_pdma_get_drcmr(pdev, phy->vchan->drcmr); - writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); - - dalgn = readl(phy->base + DALGN); -@@ -437,7 +448,7 @@ static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan) - return; - - /* clear the channel mapping in DRCMR */ -- reg = DRCMR(pchan->drcmr); -+ reg = mmp_pdma_get_drcmr(pdev, pchan->drcmr); - writel(0, pchan->phy->base + reg); - - spin_lock_irqsave(&pdev->phy_lock, flags); -@@ -1179,6 +1190,7 @@ static const struct mmp_pdma_ops marvell_pdma_v1_ops = { - .get_desc_dst_addr = get_desc_dst_addr_32, - .run_bits = (DCSR_RUN), - .dma_width = 32, -+ .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, - }; - - static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { -@@ -1192,6 +1204,7 @@ static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { - .get_desc_dst_addr = get_desc_dst_addr_64, - .run_bits = (DCSR_RUN | DCSR_LPAEEN), - .dma_width = 64, -+ .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, - }; - - static const struct of_device_id mmp_pdma_dt_ids[] = { --- -2.53.0 - diff --git a/SPECS/linux/0150-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch b/SPECS/linux/0150-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch deleted file mode 100644 index f9f97be744..0000000000 --- a/SPECS/linux/0150-FROMLIST-dmaengine-mmp_pdma-add-SpacemiT-K3-support.patch +++ /dev/null @@ -1,64 +0,0 @@ -From feef998462c7a50d6c1a3a570afc8267c0d46b66 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Mon, 18 May 2026 11:32:43 +0800 -Subject: [PATCH 150/269] FROMLIST: dmaengine: mmp_pdma: add SpacemiT K3 - support - -SpacemiT K3 reuses most of the PDMA IP design found on K1, with one -difference being the extended DRCMR base address. Add "spacemit,k3-pdma" -compatible string and define a new mmp_pdma_ops for K3 PDMA. - -Signed-off-by: Guodong Xu -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-3-67fdf319a8f8@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/dma/mmp_pdma.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c -index 6112369006ee..386e85cd4882 100644 ---- a/drivers/dma/mmp_pdma.c -+++ b/drivers/dma/mmp_pdma.c -@@ -52,6 +52,7 @@ - #define DCSR_EORINTR BIT(9) /* The end of Receive */ - - #define DRCMR_BASE 0x0100 -+#define DRCMR_EXT_BASE_K3 0x1000 - #define DRCMR_EXT_BASE_DEFAULT 0x1100 - #define DRCMR_REQ_LIMIT 64 - #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ -@@ -1207,6 +1208,20 @@ static const struct mmp_pdma_ops spacemit_k1_pdma_ops = { - .drcmr_ext_base = DRCMR_EXT_BASE_DEFAULT, - }; - -+static const struct mmp_pdma_ops spacemit_k3_pdma_ops = { -+ .write_next_addr = write_next_addr_64, -+ .read_src_addr = read_src_addr_64, -+ .read_dst_addr = read_dst_addr_64, -+ .set_desc_next_addr = set_desc_next_addr_64, -+ .set_desc_src_addr = set_desc_src_addr_64, -+ .set_desc_dst_addr = set_desc_dst_addr_64, -+ .get_desc_src_addr = get_desc_src_addr_64, -+ .get_desc_dst_addr = get_desc_dst_addr_64, -+ .run_bits = (DCSR_RUN | DCSR_LPAEEN | DCSR_EORIRQEN | DCSR_EORSTOPEN), -+ .dma_width = 64, -+ .drcmr_ext_base = DRCMR_EXT_BASE_K3, -+}; -+ - static const struct of_device_id mmp_pdma_dt_ids[] = { - { - .compatible = "marvell,pdma-1.0", -@@ -1214,6 +1229,9 @@ static const struct of_device_id mmp_pdma_dt_ids[] = { - }, { - .compatible = "spacemit,k1-pdma", - .data = &spacemit_k1_pdma_ops -+ }, { -+ .compatible = "spacemit,k3-pdma", -+ .data = &spacemit_k3_pdma_ops - }, { - /* sentinel */ - } --- -2.53.0 - diff --git a/SPECS/linux/0150-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch b/SPECS/linux/0150-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch new file mode 100644 index 0000000000..637ca762bd --- /dev/null +++ b/SPECS/linux/0150-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch @@ -0,0 +1,49 @@ +From 6d0191c0fcdb94c4ec4bb0d35877e0726b9dab07 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Mon, 18 May 2026 11:32:44 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: Add PDMA controller node + for K3 SoC + +Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC. +The PDMA controller provides general-purpose DMA capabilities for various +peripheral devices across the system to offload CPU data transfers. + +Unlike the previous K1 SoC, where some DMA masters had memory addressing +limitations (e.g. restricted to the 0-4GB space) requiring a dedicated dma-bus +with dma-ranges to restrict memory allocations, the K3 DMA masters have +full memory addressing capabilities. Therefore, the PDMA node is now +instantiated directly under the main soc bus. + +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-4-67fdf319a8f8@linux.spacemit.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 815debd16409..81ad575f16a5 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -625,6 +625,18 @@ i2c5: i2c@d4013800 { + status = "disabled"; + }; + ++ ++ pdma: dma-controller@d4000000 { ++ compatible = "spacemit,k3-pdma"; ++ reg = <0x0 0xd4000000 0x0 0x4000>; ++ clocks = <&syscon_apmu CLK_APMU_DMA>; ++ resets = <&syscon_apmu RESET_APMU_DMA>; ++ interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; ++ dma-channels = <16>; ++ #dma-cells = <1>; ++ status = "disabled"; ++ }; ++ + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux/0151-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch b/SPECS/linux/0151-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch new file mode 100644 index 0000000000..cc4dced099 --- /dev/null +++ b/SPECS/linux/0151-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch @@ -0,0 +1,39 @@ +From ef2259484eb886e83a743eb0fb85396ae726253d Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 1 Apr 2026 01:12:47 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: pci: sophgo: Add dma-coherent + property for SG2042 + +Add dma-coherent as an allowed property in the SG2042 PCIe host +controller binding. SG2042's PCIe root complexes are cache-coherent +with the CPU. + +Link: https://lore.kernel.org/r/20260331171248.973014-2-gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml +index f8b7ca57fff1..ab482488b047 100644 +--- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml ++++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml +@@ -30,6 +30,8 @@ properties: + device-id: + const: 0x2042 + ++ dma-coherent: true ++ + msi-parent: true + + allOf: +@@ -60,5 +62,6 @@ examples: + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + }; +-- +2.53.0 + diff --git a/SPECS/linux/0151-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch b/SPECS/linux/0151-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch deleted file mode 100644 index 5fdc627d16..0000000000 --- a/SPECS/linux/0151-FROMLIST-riscv-dts-spacemit-Add-PDMA-controller-node.patch +++ /dev/null @@ -1,49 +0,0 @@ -From cc845c0f3caec5002618afb0d37d8a21f074669f Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Mon, 18 May 2026 11:32:44 +0800 -Subject: [PATCH 151/269] FROMLIST: riscv: dts: spacemit: Add PDMA controller - node for K3 SoC - -Add the Peripheral DMA (PDMA) controller node for the SpacemiT K3 SoC. -The PDMA controller provides general-purpose DMA capabilities for various -peripheral devices across the system to offload CPU data transfers. - -Unlike the previous K1 SoC, where some DMA masters had memory addressing -limitations (e.g. restricted to the 0-4GB space) requiring a dedicated dma-bus -with dma-ranges to restrict memory allocations, the K3 DMA masters have -full memory addressing capabilities. Therefore, the PDMA node is now -instantiated directly under the main soc bus. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260518-k3-pdma-v6-4-67fdf319a8f8@linux.spacemit.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 815debd16409..81ad575f16a5 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -625,6 +625,18 @@ i2c5: i2c@d4013800 { - status = "disabled"; - }; - -+ -+ pdma: dma-controller@d4000000 { -+ compatible = "spacemit,k3-pdma"; -+ reg = <0x0 0xd4000000 0x0 0x4000>; -+ clocks = <&syscon_apmu CLK_APMU_DMA>; -+ resets = <&syscon_apmu RESET_APMU_DMA>; -+ interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; -+ dma-channels = <16>; -+ #dma-cells = <1>; -+ status = "disabled"; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k3-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux/0152-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch b/SPECS/linux/0152-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch deleted file mode 100644 index 48eb95ca98..0000000000 --- a/SPECS/linux/0152-FROMLIST-dt-bindings-pci-sophgo-Add-dma-coherent-pro.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 98ed5beb5c0df96d799b8b2112e88c75eb9e4411 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 1 Apr 2026 01:12:47 +0800 -Subject: [PATCH 152/269] FROMLIST: dt-bindings: pci: sophgo: Add dma-coherent - property for SG2042 - -Add dma-coherent as an allowed property in the SG2042 PCIe host -controller binding. SG2042's PCIe root complexes are cache-coherent -with the CPU. - -Link: https://lore.kernel.org/r/20260331171248.973014-2-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml -index f8b7ca57fff1..ab482488b047 100644 ---- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml -+++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml -@@ -30,6 +30,8 @@ properties: - device-id: - const: 0x2042 - -+ dma-coherent: true -+ - msi-parent: true - - allOf: -@@ -60,5 +62,6 @@ examples: - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - }; --- -2.53.0 - diff --git a/SPECS/linux/0152-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch b/SPECS/linux/0152-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch new file mode 100644 index 0000000000..ea9d075150 --- /dev/null +++ b/SPECS/linux/0152-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch @@ -0,0 +1,57 @@ +From 6a48070cef58869aa59cd42f8f26b3dd0e5c49f8 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 1 Apr 2026 01:12:48 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: Add dma-coherent to SG2042 + PCIe controllers + +SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all +four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent +so the kernel uses coherent DMA mappings instead of non-coherent bounce +buffering. + +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20260331171248.973014-3-gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +index 9fddf3f0b3b9..3af770549742 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +@@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 { + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + status = "disabled"; + }; +@@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 { + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + status = "disabled"; + }; +@@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 { + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + status = "disabled"; + }; +@@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 { + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; ++ dma-coherent; + msi-parent = <&msi>; + status = "disabled"; + }; +-- +2.53.0 + diff --git a/SPECS/linux/0153-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch b/SPECS/linux/0153-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch deleted file mode 100644 index 917c44c2d1..0000000000 --- a/SPECS/linux/0153-FROMLIST-riscv-dts-sophgo-Add-dma-coherent-to-SG2042.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 5580c0e6f96b1acb5943c89775d0868923971140 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 1 Apr 2026 01:12:48 +0800 -Subject: [PATCH 153/269] FROMLIST: riscv: dts: sophgo: Add dma-coherent to - SG2042 PCIe controllers - -SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all -four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent -so the kernel uses coherent DMA mappings instead of non-coherent bounce -buffering. - -Cc: stable@vger.kernel.org -Link: https://lore.kernel.org/r/20260331171248.973014-3-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -index 9fddf3f0b3b9..3af770549742 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -@@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 { - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - status = "disabled"; - }; -@@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 { - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - status = "disabled"; - }; -@@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 { - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - status = "disabled"; - }; -@@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 { - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; -+ dma-coherent; - msi-parent = <&msi>; - status = "disabled"; - }; --- -2.53.0 - diff --git a/SPECS/linux/0153-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch b/SPECS/linux/0153-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch new file mode 100644 index 0000000000..c83a096754 --- /dev/null +++ b/SPECS/linux/0153-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch @@ -0,0 +1,83 @@ +From e3e108aff62eff53e4f412baa7fabf6d978c40b7 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Tue, 31 Mar 2026 15:37:22 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: fix SWIOTLB initialization for + systems with DRAM above 4GB + +On RISC-V platforms where the entire physical memory (DRAM) resides +above the 32-bit address space (i.e., above dma32_phys_limit), the +current SWIOTLB initialization logic fails. + +This patch addresses two interconnected issues on such platforms: + +1. Incorrect 32-bit DMA bounce assumption: +The existing condition `max_pfn > PFN_DOWN(dma32_phys_limit)` assumes +that a 32-bit DMA bounce buffer is required simply because the maximum +PFN exceeds the 32-bit limit. However, if all DRAM starts above 4GB, +no memory exists below the limit to satisfy this allocation. Fix +this by adding a check to ensure `memblock_start_of_DRAM()` is actually +below the 32-bit limit before enforcing 32-bit SWIOTLB. + +2. kmalloc() bounce buffer allocation failure on non-coherent systems: +For non-coherent hardware, a bounce buffer is still mandatory for +cache-line-aligned kmalloc(), even if 32-bit DMA bouncing is skipped. +Without the `SWIOTLB_ANY` flag, swiotlb_init() defaults to allocating +from low memory, which fails completely when DRAM only exists in high +memory. By appending `SWIOTLB_ANY` to swiotlb_flags, the allocator is +permitted to allocate this alignment buffer from high memory. + +With this patch, systems with non-coherent DMA and DRAM entirely above +4GB can successfully map the software IO TLB in high memory and boot +normally. + +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260331-fix-riscv-swiotlb-v1-1-74dd5e6be0f1@linux.dev +Signed-off-by: Han Gao +--- + arch/riscv/mm/init.c | 16 +++++++++++----- + 1 file changed, 11 insertions(+), 5 deletions(-) + +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index 985e496313c8..cf4f3ec1cca5 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -168,7 +168,9 @@ static void print_vm_layout(void) { } + + void __init arch_mm_preinit(void) + { +- bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit); ++ bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit) && ++ memblock_start_of_DRAM() < dma32_phys_limit; ++ unsigned int swiotlb_flags = SWIOTLB_VERBOSE; + #ifdef CONFIG_FLATMEM + BUG_ON(!mem_map); + #endif /* CONFIG_FLATMEM */ +@@ -176,17 +178,21 @@ void __init arch_mm_preinit(void) + if (IS_ENABLED(CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC) && !swiotlb && + dma_cache_alignment != 1) { + /* +- * If no bouncing needed for ZONE_DMA, allocate 1MB swiotlb +- * buffer per 1GB of RAM for kmalloc() bouncing on +- * non-coherent platforms. ++ * No 32-bit DMA bouncing needed (either all DRAM is within ++ * the 32-bit limit, or it all starts above it), but ++ * non-coherent hardware still requires cache-line-aligned ++ * bounce buffers for kmalloc(). Use SWIOTLB_ANY so that the ++ * buffer can be allocated from high memory when DRAM starts ++ * above dma32_phys_limit. Allocate ~1 MB per 1 GB of RAM. + */ + unsigned long size = + DIV_ROUND_UP(memblock_phys_mem_size(), 1024); + swiotlb_adjust_size(min(swiotlb_size_or_default(), size)); + swiotlb = true; ++ swiotlb_flags |= SWIOTLB_ANY; + } + +- swiotlb_init(swiotlb, SWIOTLB_VERBOSE); ++ swiotlb_init(swiotlb, swiotlb_flags); + + print_vm_layout(); + } +-- +2.53.0 + diff --git a/SPECS/linux/0154-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch b/SPECS/linux/0154-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch new file mode 100644 index 0000000000..84f9a21e79 --- /dev/null +++ b/SPECS/linux/0154-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch @@ -0,0 +1,61 @@ +From 44033f13478c7f3f26e6705b85ae6f83b176f321 Mon Sep 17 00:00:00 2001 +From: Anand Moon +Date: Wed, 25 Mar 2026 13:46:08 +0530 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Add + vcc5v0_sys regulator for Banana Pi F3 + +Define the system 5V fixed regulator (vcc5v0_sys) supplied by the +DC input. As per the schematics, vcc5v0_sys is the input power source +for the VCC5V0_HUB and 5V_VBUS reglators. Update these regulators +to correctly reference vcc5v0_sys as their parent (vin-supply). + +Cc: Han Gao +Cc: Ze Huang +Cc: Chukun Pan +Signed-off-by: Anand Moon +Link: https://lore.kernel.org/r/20260325081700.1502-2-linux.amoon@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 2a0caecd9a41..341d86a8f7ae 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -52,6 +52,16 @@ reg_dc_in: regulator-dc-in-12v { + regulator-always-on; + }; + ++ reg_vcc5v0_sys: regulator-vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <®_dc_in>; ++ }; ++ + reg_vcc_4v: regulator-vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "vcc_4v"; +@@ -68,6 +78,7 @@ regulator-usb3-vbus-5v { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; ++ vin-supply = <®_vcc5v0_sys>; + gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +@@ -77,6 +88,7 @@ usb3_hub_5v: regulator-usb3-hub-5v { + regulator-name = "USB30_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; ++ vin-supply = <®_vcc5v0_sys>; + gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +-- +2.53.0 + diff --git a/SPECS/linux/0154-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch b/SPECS/linux/0154-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch deleted file mode 100644 index 0f777aacfd..0000000000 --- a/SPECS/linux/0154-FROMLIST-riscv-mm-fix-SWIOTLB-initialization-for-sys.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 04603d2f196993532da9e1ef6b3713730436cf02 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Tue, 31 Mar 2026 15:37:22 +0800 -Subject: [PATCH 154/269] FROMLIST: riscv: mm: fix SWIOTLB initialization for - systems with DRAM above 4GB - -On RISC-V platforms where the entire physical memory (DRAM) resides -above the 32-bit address space (i.e., above dma32_phys_limit), the -current SWIOTLB initialization logic fails. - -This patch addresses two interconnected issues on such platforms: - -1. Incorrect 32-bit DMA bounce assumption: -The existing condition `max_pfn > PFN_DOWN(dma32_phys_limit)` assumes -that a 32-bit DMA bounce buffer is required simply because the maximum -PFN exceeds the 32-bit limit. However, if all DRAM starts above 4GB, -no memory exists below the limit to satisfy this allocation. Fix -this by adding a check to ensure `memblock_start_of_DRAM()` is actually -below the 32-bit limit before enforcing 32-bit SWIOTLB. - -2. kmalloc() bounce buffer allocation failure on non-coherent systems: -For non-coherent hardware, a bounce buffer is still mandatory for -cache-line-aligned kmalloc(), even if 32-bit DMA bouncing is skipped. -Without the `SWIOTLB_ANY` flag, swiotlb_init() defaults to allocating -from low memory, which fails completely when DRAM only exists in high -memory. By appending `SWIOTLB_ANY` to swiotlb_flags, the allocator is -permitted to allocate this alignment buffer from high memory. - -With this patch, systems with non-coherent DMA and DRAM entirely above -4GB can successfully map the software IO TLB in high memory and boot -normally. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260331-fix-riscv-swiotlb-v1-1-74dd5e6be0f1@linux.dev -Signed-off-by: Han Gao ---- - arch/riscv/mm/init.c | 16 +++++++++++----- - 1 file changed, 11 insertions(+), 5 deletions(-) - -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index 985e496313c8..cf4f3ec1cca5 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -168,7 +168,9 @@ static void print_vm_layout(void) { } - - void __init arch_mm_preinit(void) - { -- bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit); -+ bool swiotlb = max_pfn > PFN_DOWN(dma32_phys_limit) && -+ memblock_start_of_DRAM() < dma32_phys_limit; -+ unsigned int swiotlb_flags = SWIOTLB_VERBOSE; - #ifdef CONFIG_FLATMEM - BUG_ON(!mem_map); - #endif /* CONFIG_FLATMEM */ -@@ -176,17 +178,21 @@ void __init arch_mm_preinit(void) - if (IS_ENABLED(CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC) && !swiotlb && - dma_cache_alignment != 1) { - /* -- * If no bouncing needed for ZONE_DMA, allocate 1MB swiotlb -- * buffer per 1GB of RAM for kmalloc() bouncing on -- * non-coherent platforms. -+ * No 32-bit DMA bouncing needed (either all DRAM is within -+ * the 32-bit limit, or it all starts above it), but -+ * non-coherent hardware still requires cache-line-aligned -+ * bounce buffers for kmalloc(). Use SWIOTLB_ANY so that the -+ * buffer can be allocated from high memory when DRAM starts -+ * above dma32_phys_limit. Allocate ~1 MB per 1 GB of RAM. - */ - unsigned long size = - DIV_ROUND_UP(memblock_phys_mem_size(), 1024); - swiotlb_adjust_size(min(swiotlb_size_or_default(), size)); - swiotlb = true; -+ swiotlb_flags |= SWIOTLB_ANY; - } - -- swiotlb_init(swiotlb, SWIOTLB_VERBOSE); -+ swiotlb_init(swiotlb, swiotlb_flags); - - print_vm_layout(); - } --- -2.53.0 - diff --git a/SPECS/linux/0155-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch b/SPECS/linux/0155-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch deleted file mode 100644 index 4fc897a8fd..0000000000 --- a/SPECS/linux/0155-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Add-vcc5v.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 3c2245ed9830e05da47d63716c0ac4c9a78af636 Mon Sep 17 00:00:00 2001 -From: Anand Moon -Date: Wed, 25 Mar 2026 13:46:08 +0530 -Subject: [PATCH 155/269] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Add - vcc5v0_sys regulator for Banana Pi F3 - -Define the system 5V fixed regulator (vcc5v0_sys) supplied by the -DC input. As per the schematics, vcc5v0_sys is the input power source -for the VCC5V0_HUB and 5V_VBUS reglators. Update these regulators -to correctly reference vcc5v0_sys as their parent (vin-supply). - -Cc: Han Gao -Cc: Ze Huang -Cc: Chukun Pan -Signed-off-by: Anand Moon -Link: https://lore.kernel.org/r/20260325081700.1502-2-linux.amoon@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 2a0caecd9a41..341d86a8f7ae 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -52,6 +52,16 @@ reg_dc_in: regulator-dc-in-12v { - regulator-always-on; - }; - -+ reg_vcc5v0_sys: regulator-vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <®_dc_in>; -+ }; -+ - reg_vcc_4v: regulator-vcc-4v { - compatible = "regulator-fixed"; - regulator-name = "vcc_4v"; -@@ -68,6 +78,7 @@ regulator-usb3-vbus-5v { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; -+ vin-supply = <®_vcc5v0_sys>; - gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -@@ -77,6 +88,7 @@ usb3_hub_5v: regulator-usb3-hub-5v { - regulator-name = "USB30_HUB"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -+ vin-supply = <®_vcc5v0_sys>; - gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; --- -2.53.0 - diff --git a/SPECS/linux/0155-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch b/SPECS/linux/0155-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch new file mode 100644 index 0000000000..96a20961d6 --- /dev/null +++ b/SPECS/linux/0155-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch @@ -0,0 +1,59 @@ +From 991b7ddc9cbb2fe0b192da9dc3c966798a76fb34 Mon Sep 17 00:00:00 2001 +From: Anand Moon +Date: Wed, 25 Mar 2026 13:46:09 +0530 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Update + USB regulator on onboard usb and lable + +Update the USB regulator labels to align with the board schematics and +power hierarchy. This change renames the regulator to reg_5v_vbus and +its name to 5V_VBUS. Additionally, it fixes the vdd-supply references +for both the USB 2.0 and 3.0 hub nodes to ensure they correctly point +to the 5V_VBUS input source as per the board schematics. + +Cc: Han Gao +Cc: Ze Huang +Cc: Chukun Pan +Signed-off-by: Anand Moon +Link: https://lore.kernel.org/r/20260325081700.1502-3-linux.amoon@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 341d86a8f7ae..6c2a2e713121 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -72,9 +72,9 @@ reg_vcc_4v: regulator-vcc-4v { + vin-supply = <®_dc_in>; + }; + +- regulator-usb3-vbus-5v { ++ reg_5v_vbus: regulator-usb3-vbus-5v { + compatible = "regulator-fixed"; +- regulator-name = "USB30_VBUS"; ++ regulator-name = "5V_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; +@@ -406,7 +406,7 @@ &usb_dwc3 { + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <0x1>; +- vdd-supply = <&usb3_hub_5v>; ++ vdd-supply = <®_5v_vbus>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; +@@ -414,7 +414,7 @@ hub_2_0: hub@1 { + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <0x2>; +- vdd-supply = <&usb3_hub_5v>; ++ vdd-supply = <®_5v_vbus>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; +-- +2.53.0 + diff --git a/SPECS/linux/0156-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch b/SPECS/linux/0156-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch new file mode 100644 index 0000000000..1e7c334a5f --- /dev/null +++ b/SPECS/linux/0156-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch @@ -0,0 +1,52 @@ +From 39032540d6be640b22fd899399a58ce67564fe04 Mon Sep 17 00:00:00 2001 +From: Anand Moon +Date: Wed, 25 Mar 2026 13:46:10 +0530 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: Correct + USB hub power hierarchy +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Link the usb3_hub_5v regulator to the USB controller’s vbus-supply to +ensure the USB 3.0 stack is properly powered as per the schematics. +In addition, align the USB hub regulator with the board schematics +by renaming it to VCC5V0_HUB and marking it as regulator-always-on +to maintain power stability. + +Cc: Han Gao +Cc: Ze Huang +Cc: Chukun Pan +Signed-off-by: Anand Moon +Link: https://lore.kernel.org/r/20260325081700.1502-4-linux.amoon@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 6c2a2e713121..b48a485f954b 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -85,9 +85,10 @@ reg_5v_vbus: regulator-usb3-vbus-5v { + + usb3_hub_5v: regulator-usb3-hub-5v { + compatible = "regulator-fixed"; +- regulator-name = "USB30_HUB"; ++ regulator-name = "VCC5V0_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; ++ regulator-always-on; + vin-supply = <®_vcc5v0_sys>; + gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + enable-active-high; +@@ -401,6 +402,7 @@ &usb_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; ++ vbus-supply = <&usb3_hub_5v>; + status = "okay"; + + hub_2_0: hub@1 { +-- +2.53.0 + diff --git a/SPECS/linux/0156-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch b/SPECS/linux/0156-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch deleted file mode 100644 index aae63697d7..0000000000 --- a/SPECS/linux/0156-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Update-US.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 5a7a9c09553404d805ba2a541a042fc0dab79d5b Mon Sep 17 00:00:00 2001 -From: Anand Moon -Date: Wed, 25 Mar 2026 13:46:09 +0530 -Subject: [PATCH 156/269] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: - Update USB regulator on onboard usb and lable - -Update the USB regulator labels to align with the board schematics and -power hierarchy. This change renames the regulator to reg_5v_vbus and -its name to 5V_VBUS. Additionally, it fixes the vdd-supply references -for both the USB 2.0 and 3.0 hub nodes to ensure they correctly point -to the 5V_VBUS input source as per the board schematics. - -Cc: Han Gao -Cc: Ze Huang -Cc: Chukun Pan -Signed-off-by: Anand Moon -Link: https://lore.kernel.org/r/20260325081700.1502-3-linux.amoon@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 341d86a8f7ae..6c2a2e713121 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -72,9 +72,9 @@ reg_vcc_4v: regulator-vcc-4v { - vin-supply = <®_dc_in>; - }; - -- regulator-usb3-vbus-5v { -+ reg_5v_vbus: regulator-usb3-vbus-5v { - compatible = "regulator-fixed"; -- regulator-name = "USB30_VBUS"; -+ regulator-name = "5V_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; -@@ -406,7 +406,7 @@ &usb_dwc3 { - hub_2_0: hub@1 { - compatible = "usb2109,2817"; - reg = <0x1>; -- vdd-supply = <&usb3_hub_5v>; -+ vdd-supply = <®_5v_vbus>; - peer-hub = <&hub_3_0>; - reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; - }; -@@ -414,7 +414,7 @@ hub_2_0: hub@1 { - hub_3_0: hub@2 { - compatible = "usb2109,817"; - reg = <0x2>; -- vdd-supply = <&usb3_hub_5v>; -+ vdd-supply = <®_5v_vbus>; - peer-hub = <&hub_2_0>; - reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; - }; --- -2.53.0 - diff --git a/SPECS/linux/0157-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch b/SPECS/linux/0157-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch new file mode 100644 index 0000000000..0ee8e7e184 --- /dev/null +++ b/SPECS/linux/0157-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch @@ -0,0 +1,769 @@ +From a0ed813a7bf3b0aa23cacb63d4619915ccbf459d Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 26 Apr 2026 09:34:48 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: sg2044: use hex for CPU + unit address + +Previous the CPU unit address cpu of sg2044 use decimal, it is +not following the general convention for unit addresses of the +OF. Convent the unit address to hex to resolve this problem. + +The introduces a small change for the CPU node name, but it should +nothing since there is no direct full-path reference to these +CPU nodes. + +Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree") +Signed-off-by: Inochi Amaoto +Reviewed-by: Chen Wang +Reviewed-by: Guo Ren +Link: https://lore.kernel.org/r/20260426013449.694435-2-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- + 1 file changed, 118 insertions(+), 118 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +index 3135409c2149..f66a382c95bd 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +@@ -14,7 +14,7 @@ cpus { + + cpu0: cpu@0 { + compatible = "thead,c920", "riscv"; +- reg = <0>; ++ reg = <0x0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller { + + cpu1: cpu@1 { + compatible = "thead,c920", "riscv"; +- reg = <1>; ++ reg = <0x1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller { + + cpu2: cpu@2 { + compatible = "thead,c920", "riscv"; +- reg = <2>; ++ reg = <0x2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller { + + cpu3: cpu@3 { + compatible = "thead,c920", "riscv"; +- reg = <3>; ++ reg = <0x3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller { + + cpu4: cpu@4 { + compatible = "thead,c920", "riscv"; +- reg = <4>; ++ reg = <0x4>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller { + + cpu5: cpu@5 { + compatible = "thead,c920", "riscv"; +- reg = <5>; ++ reg = <0x5>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller { + + cpu6: cpu@6 { + compatible = "thead,c920", "riscv"; +- reg = <6>; ++ reg = <0x6>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller { + + cpu7: cpu@7 { + compatible = "thead,c920", "riscv"; +- reg = <7>; ++ reg = <0x7>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller { + + cpu8: cpu@8 { + compatible = "thead,c920", "riscv"; +- reg = <8>; ++ reg = <0x8>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller { + + cpu9: cpu@9 { + compatible = "thead,c920", "riscv"; +- reg = <9>; ++ reg = <0x9>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller { + }; + }; + +- cpu10: cpu@10 { ++ cpu10: cpu@a { + compatible = "thead,c920", "riscv"; +- reg = <10>; ++ reg = <0xa>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller { + }; + }; + +- cpu11: cpu@11 { ++ cpu11: cpu@b { + compatible = "thead,c920", "riscv"; +- reg = <11>; ++ reg = <0xb>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller { + }; + }; + +- cpu12: cpu@12 { ++ cpu12: cpu@c { + compatible = "thead,c920", "riscv"; +- reg = <12>; ++ reg = <0xc>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller { + }; + }; + +- cpu13: cpu@13 { ++ cpu13: cpu@d { + compatible = "thead,c920", "riscv"; +- reg = <13>; ++ reg = <0xd>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller { + }; + }; + +- cpu14: cpu@14 { ++ cpu14: cpu@e { + compatible = "thead,c920", "riscv"; +- reg = <14>; ++ reg = <0xe>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller { + }; + }; + +- cpu15: cpu@15 { ++ cpu15: cpu@f { + compatible = "thead,c920", "riscv"; +- reg = <15>; ++ reg = <0xf>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller { + }; + }; + +- cpu16: cpu@16 { ++ cpu16: cpu@10 { + compatible = "thead,c920", "riscv"; +- reg = <16>; ++ reg = <0x10>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller { + }; + }; + +- cpu17: cpu@17 { ++ cpu17: cpu@11 { + compatible = "thead,c920", "riscv"; +- reg = <17>; ++ reg = <0x11>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller { + }; + }; + +- cpu18: cpu@18 { ++ cpu18: cpu@12 { + compatible = "thead,c920", "riscv"; +- reg = <18>; ++ reg = <0x12>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller { + }; + }; + +- cpu19: cpu@19 { ++ cpu19: cpu@13 { + compatible = "thead,c920", "riscv"; +- reg = <19>; ++ reg = <0x13>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller { + }; + }; + +- cpu20: cpu@20 { ++ cpu20: cpu@14 { + compatible = "thead,c920", "riscv"; +- reg = <20>; ++ reg = <0x14>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller { + }; + }; + +- cpu21: cpu@21 { ++ cpu21: cpu@15 { + compatible = "thead,c920", "riscv"; +- reg = <21>; ++ reg = <0x15>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller { + }; + }; + +- cpu22: cpu@22 { ++ cpu22: cpu@16 { + compatible = "thead,c920", "riscv"; +- reg = <22>; ++ reg = <0x16>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller { + }; + }; + +- cpu23: cpu@23 { ++ cpu23: cpu@17 { + compatible = "thead,c920", "riscv"; +- reg = <23>; ++ reg = <0x17>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller { + }; + }; + +- cpu24: cpu@24 { ++ cpu24: cpu@18 { + compatible = "thead,c920", "riscv"; +- reg = <24>; ++ reg = <0x18>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller { + }; + }; + +- cpu25: cpu@25 { ++ cpu25: cpu@19 { + compatible = "thead,c920", "riscv"; +- reg = <25>; ++ reg = <0x19>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller { + }; + }; + +- cpu26: cpu@26 { ++ cpu26: cpu@1a { + compatible = "thead,c920", "riscv"; +- reg = <26>; ++ reg = <0x1a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller { + }; + }; + +- cpu27: cpu@27 { ++ cpu27: cpu@1b { + compatible = "thead,c920", "riscv"; +- reg = <27>; ++ reg = <0x1b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller { + }; + }; + +- cpu28: cpu@28 { ++ cpu28: cpu@1c { + compatible = "thead,c920", "riscv"; +- reg = <28>; ++ reg = <0x1c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller { + }; + }; + +- cpu29: cpu@29 { ++ cpu29: cpu@1d { + compatible = "thead,c920", "riscv"; +- reg = <29>; ++ reg = <0x1d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller { + }; + }; + +- cpu30: cpu@30 { ++ cpu30: cpu@1e { + compatible = "thead,c920", "riscv"; +- reg = <30>; ++ reg = <0x1e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller { + }; + }; + +- cpu31: cpu@31 { ++ cpu31: cpu@1f { + compatible = "thead,c920", "riscv"; +- reg = <31>; ++ reg = <0x1f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller { + }; + }; + +- cpu32: cpu@32 { ++ cpu32: cpu@20 { + compatible = "thead,c920", "riscv"; +- reg = <32>; ++ reg = <0x20>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller { + }; + }; + +- cpu33: cpu@33 { ++ cpu33: cpu@21 { + compatible = "thead,c920", "riscv"; +- reg = <33>; ++ reg = <0x21>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller { + }; + }; + +- cpu34: cpu@34 { ++ cpu34: cpu@22 { + compatible = "thead,c920", "riscv"; +- reg = <34>; ++ reg = <0x22>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller { + }; + }; + +- cpu35: cpu@35 { ++ cpu35: cpu@23 { + compatible = "thead,c920", "riscv"; +- reg = <35>; ++ reg = <0x23>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller { + }; + }; + +- cpu36: cpu@36 { ++ cpu36: cpu@24 { + compatible = "thead,c920", "riscv"; +- reg = <36>; ++ reg = <0x24>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller { + }; + }; + +- cpu37: cpu@37 { ++ cpu37: cpu@25 { + compatible = "thead,c920", "riscv"; +- reg = <37>; ++ reg = <0x25>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller { + }; + }; + +- cpu38: cpu@38 { ++ cpu38: cpu@26 { + compatible = "thead,c920", "riscv"; +- reg = <38>; ++ reg = <0x26>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller { + }; + }; + +- cpu39: cpu@39 { ++ cpu39: cpu@27 { + compatible = "thead,c920", "riscv"; +- reg = <39>; ++ reg = <0x27>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller { + }; + }; + +- cpu40: cpu@40 { ++ cpu40: cpu@28 { + compatible = "thead,c920", "riscv"; +- reg = <40>; ++ reg = <0x28>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller { + }; + }; + +- cpu41: cpu@41 { ++ cpu41: cpu@29 { + compatible = "thead,c920", "riscv"; +- reg = <41>; ++ reg = <0x29>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller { + }; + }; + +- cpu42: cpu@42 { ++ cpu42: cpu@2a { + compatible = "thead,c920", "riscv"; +- reg = <42>; ++ reg = <0x2a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller { + }; + }; + +- cpu43: cpu@43 { ++ cpu43: cpu@2b { + compatible = "thead,c920", "riscv"; +- reg = <43>; ++ reg = <0x2b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller { + }; + }; + +- cpu44: cpu@44 { ++ cpu44: cpu@2c { + compatible = "thead,c920", "riscv"; +- reg = <44>; ++ reg = <0x2c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller { + }; + }; + +- cpu45: cpu@45 { ++ cpu45: cpu@2d { + compatible = "thead,c920", "riscv"; +- reg = <45>; ++ reg = <0x2d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller { + }; + }; + +- cpu46: cpu@46 { ++ cpu46: cpu@2e { + compatible = "thead,c920", "riscv"; +- reg = <46>; ++ reg = <0x2e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller { + }; + }; + +- cpu47: cpu@47 { ++ cpu47: cpu@2f { + compatible = "thead,c920", "riscv"; +- reg = <47>; ++ reg = <0x2f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller { + }; + }; + +- cpu48: cpu@48 { ++ cpu48: cpu@30 { + compatible = "thead,c920", "riscv"; +- reg = <48>; ++ reg = <0x30>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller { + }; + }; + +- cpu49: cpu@49 { ++ cpu49: cpu@31 { + compatible = "thead,c920", "riscv"; +- reg = <49>; ++ reg = <0x31>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller { + }; + }; + +- cpu50: cpu@50 { ++ cpu50: cpu@32 { + compatible = "thead,c920", "riscv"; +- reg = <50>; ++ reg = <0x32>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller { + }; + }; + +- cpu51: cpu@51 { ++ cpu51: cpu@33 { + compatible = "thead,c920", "riscv"; +- reg = <51>; ++ reg = <0x33>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller { + }; + }; + +- cpu52: cpu@52 { ++ cpu52: cpu@34 { + compatible = "thead,c920", "riscv"; +- reg = <52>; ++ reg = <0x34>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller { + }; + }; + +- cpu53: cpu@53 { ++ cpu53: cpu@35 { + compatible = "thead,c920", "riscv"; +- reg = <53>; ++ reg = <0x35>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller { + }; + }; + +- cpu54: cpu@54 { ++ cpu54: cpu@36 { + compatible = "thead,c920", "riscv"; +- reg = <54>; ++ reg = <0x36>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller { + }; + }; + +- cpu55: cpu@55 { ++ cpu55: cpu@37 { + compatible = "thead,c920", "riscv"; +- reg = <55>; ++ reg = <0x37>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller { + }; + }; + +- cpu56: cpu@56 { ++ cpu56: cpu@38 { + compatible = "thead,c920", "riscv"; +- reg = <56>; ++ reg = <0x38>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller { + }; + }; + +- cpu57: cpu@57 { ++ cpu57: cpu@39 { + compatible = "thead,c920", "riscv"; +- reg = <57>; ++ reg = <0x39>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller { + }; + }; + +- cpu58: cpu@58 { ++ cpu58: cpu@3a { + compatible = "thead,c920", "riscv"; +- reg = <58>; ++ reg = <0x3a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller { + }; + }; + +- cpu59: cpu@59 { ++ cpu59: cpu@3b { + compatible = "thead,c920", "riscv"; +- reg = <59>; ++ reg = <0x3b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller { + }; + }; + +- cpu60: cpu@60 { ++ cpu60: cpu@3c { + compatible = "thead,c920", "riscv"; +- reg = <60>; ++ reg = <0x3c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller { + }; + }; + +- cpu61: cpu@61 { ++ cpu61: cpu@3d { + compatible = "thead,c920", "riscv"; +- reg = <61>; ++ reg = <0x3d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller { + }; + }; + +- cpu62: cpu@62 { ++ cpu62: cpu@3e { + compatible = "thead,c920", "riscv"; +- reg = <62>; ++ reg = <0x3e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller { + }; + }; + +- cpu63: cpu@63 { ++ cpu63: cpu@3f { + compatible = "thead,c920", "riscv"; +- reg = <63>; ++ reg = <0x3f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +-- +2.53.0 + diff --git a/SPECS/linux/0157-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch b/SPECS/linux/0157-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch deleted file mode 100644 index 5512dc6e71..0000000000 --- a/SPECS/linux/0157-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-Correct-U.patch +++ /dev/null @@ -1,52 +0,0 @@ -From da8f5b2b1d60f5b0b72549b9b7773385fe35add4 Mon Sep 17 00:00:00 2001 -From: Anand Moon -Date: Wed, 25 Mar 2026 13:46:10 +0530 -Subject: [PATCH 157/269] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: - Correct USB hub power hierarchy -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Link the usb3_hub_5v regulator to the USB controller’s vbus-supply to -ensure the USB 3.0 stack is properly powered as per the schematics. -In addition, align the USB hub regulator with the board schematics -by renaming it to VCC5V0_HUB and marking it as regulator-always-on -to maintain power stability. - -Cc: Han Gao -Cc: Ze Huang -Cc: Chukun Pan -Signed-off-by: Anand Moon -Link: https://lore.kernel.org/r/20260325081700.1502-4-linux.amoon@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index 6c2a2e713121..b48a485f954b 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -85,9 +85,10 @@ reg_5v_vbus: regulator-usb3-vbus-5v { - - usb3_hub_5v: regulator-usb3-hub-5v { - compatible = "regulator-fixed"; -- regulator-name = "USB30_HUB"; -+ regulator-name = "VCC5V0_HUB"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -+ regulator-always-on; - vin-supply = <®_vcc5v0_sys>; - gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; - enable-active-high; -@@ -401,6 +402,7 @@ &usb_dwc3 { - dr_mode = "host"; - #address-cells = <1>; - #size-cells = <0>; -+ vbus-supply = <&usb3_hub_5v>; - status = "okay"; - - hub_2_0: hub@1 { --- -2.53.0 - diff --git a/SPECS/linux/0158-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch b/SPECS/linux/0158-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch new file mode 100644 index 0000000000..7792b9d251 --- /dev/null +++ b/SPECS/linux/0158-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch @@ -0,0 +1,1095 @@ +From 37b60b1ba3b2f03748f06d3f8895549fc4344860 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 26 Apr 2026 09:34:49 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: sg2042: use hex for CPU + unit address + +Previous the CPU unit address cpu of sg2042 use decimal, it is +not following the general convention for unit addresses of the +OF. Convent the unit address to hex to resolve this problem. + +The introduces a small change for the CPU node name, but it should +affect nothing since there is no direct full-path reference to +these CPU nodes. + +Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10") +Signed-off-by: Inochi Amaoto +Tested-by: Chen Wang # Pioneerbox. +Reviewed-by: Guo Ren +Reviewed-by: Chen Wang +Acked-by: Conor Dooley +Link: https://lore.kernel.org/r/20260426013449.694435-3-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++---------- + 1 file changed, 118 insertions(+), 118 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +index 509488eee432..fd8906b313d2 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +@@ -263,7 +263,7 @@ cpu0: cpu@0 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <0>; ++ reg = <0x0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -291,7 +291,7 @@ cpu1: cpu@1 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <1>; ++ reg = <0x1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -319,7 +319,7 @@ cpu2: cpu@2 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <2>; ++ reg = <0x2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -347,7 +347,7 @@ cpu3: cpu@3 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <3>; ++ reg = <0x3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -375,7 +375,7 @@ cpu4: cpu@4 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <4>; ++ reg = <0x4>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -403,7 +403,7 @@ cpu5: cpu@5 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <5>; ++ reg = <0x5>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -431,7 +431,7 @@ cpu6: cpu@6 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <6>; ++ reg = <0x6>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -459,7 +459,7 @@ cpu7: cpu@7 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <7>; ++ reg = <0x7>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -487,7 +487,7 @@ cpu8: cpu@8 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <8>; ++ reg = <0x8>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -515,7 +515,7 @@ cpu9: cpu@9 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <9>; ++ reg = <0x9>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -533,7 +533,7 @@ cpu9_intc: interrupt-controller { + }; + }; + +- cpu10: cpu@10 { ++ cpu10: cpu@a { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -543,7 +543,7 @@ cpu10: cpu@10 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <10>; ++ reg = <0xa>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -561,7 +561,7 @@ cpu10_intc: interrupt-controller { + }; + }; + +- cpu11: cpu@11 { ++ cpu11: cpu@b { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -571,7 +571,7 @@ cpu11: cpu@11 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <11>; ++ reg = <0xb>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -589,7 +589,7 @@ cpu11_intc: interrupt-controller { + }; + }; + +- cpu12: cpu@12 { ++ cpu12: cpu@c { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -599,7 +599,7 @@ cpu12: cpu@12 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <12>; ++ reg = <0xc>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -617,7 +617,7 @@ cpu12_intc: interrupt-controller { + }; + }; + +- cpu13: cpu@13 { ++ cpu13: cpu@d { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -627,7 +627,7 @@ cpu13: cpu@13 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <13>; ++ reg = <0xd>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -645,7 +645,7 @@ cpu13_intc: interrupt-controller { + }; + }; + +- cpu14: cpu@14 { ++ cpu14: cpu@e { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -655,7 +655,7 @@ cpu14: cpu@14 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <14>; ++ reg = <0xe>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -673,7 +673,7 @@ cpu14_intc: interrupt-controller { + }; + }; + +- cpu15: cpu@15 { ++ cpu15: cpu@f { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -683,7 +683,7 @@ cpu15: cpu@15 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <15>; ++ reg = <0xf>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -701,7 +701,7 @@ cpu15_intc: interrupt-controller { + }; + }; + +- cpu16: cpu@16 { ++ cpu16: cpu@10 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -711,7 +711,7 @@ cpu16: cpu@16 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <16>; ++ reg = <0x10>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -729,7 +729,7 @@ cpu16_intc: interrupt-controller { + }; + }; + +- cpu17: cpu@17 { ++ cpu17: cpu@11 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -739,7 +739,7 @@ cpu17: cpu@17 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <17>; ++ reg = <0x11>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -757,7 +757,7 @@ cpu17_intc: interrupt-controller { + }; + }; + +- cpu18: cpu@18 { ++ cpu18: cpu@12 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -767,7 +767,7 @@ cpu18: cpu@18 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <18>; ++ reg = <0x12>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -785,7 +785,7 @@ cpu18_intc: interrupt-controller { + }; + }; + +- cpu19: cpu@19 { ++ cpu19: cpu@13 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -795,7 +795,7 @@ cpu19: cpu@19 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <19>; ++ reg = <0x13>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -813,7 +813,7 @@ cpu19_intc: interrupt-controller { + }; + }; + +- cpu20: cpu@20 { ++ cpu20: cpu@14 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -823,7 +823,7 @@ cpu20: cpu@20 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <20>; ++ reg = <0x14>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -841,7 +841,7 @@ cpu20_intc: interrupt-controller { + }; + }; + +- cpu21: cpu@21 { ++ cpu21: cpu@15 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -851,7 +851,7 @@ cpu21: cpu@21 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <21>; ++ reg = <0x15>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -869,7 +869,7 @@ cpu21_intc: interrupt-controller { + }; + }; + +- cpu22: cpu@22 { ++ cpu22: cpu@16 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -879,7 +879,7 @@ cpu22: cpu@22 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <22>; ++ reg = <0x16>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -897,7 +897,7 @@ cpu22_intc: interrupt-controller { + }; + }; + +- cpu23: cpu@23 { ++ cpu23: cpu@17 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -907,7 +907,7 @@ cpu23: cpu@23 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <23>; ++ reg = <0x17>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -925,7 +925,7 @@ cpu23_intc: interrupt-controller { + }; + }; + +- cpu24: cpu@24 { ++ cpu24: cpu@18 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -935,7 +935,7 @@ cpu24: cpu@24 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <24>; ++ reg = <0x18>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -953,7 +953,7 @@ cpu24_intc: interrupt-controller { + }; + }; + +- cpu25: cpu@25 { ++ cpu25: cpu@19 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -963,7 +963,7 @@ cpu25: cpu@25 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <25>; ++ reg = <0x19>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -981,7 +981,7 @@ cpu25_intc: interrupt-controller { + }; + }; + +- cpu26: cpu@26 { ++ cpu26: cpu@1a { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -991,7 +991,7 @@ cpu26: cpu@26 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <26>; ++ reg = <0x1a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1009,7 +1009,7 @@ cpu26_intc: interrupt-controller { + }; + }; + +- cpu27: cpu@27 { ++ cpu27: cpu@1b { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1019,7 +1019,7 @@ cpu27: cpu@27 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <27>; ++ reg = <0x1b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1037,7 +1037,7 @@ cpu27_intc: interrupt-controller { + }; + }; + +- cpu28: cpu@28 { ++ cpu28: cpu@1c { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1047,7 +1047,7 @@ cpu28: cpu@28 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <28>; ++ reg = <0x1c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1065,7 +1065,7 @@ cpu28_intc: interrupt-controller { + }; + }; + +- cpu29: cpu@29 { ++ cpu29: cpu@1d { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1075,7 +1075,7 @@ cpu29: cpu@29 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <29>; ++ reg = <0x1d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1093,7 +1093,7 @@ cpu29_intc: interrupt-controller { + }; + }; + +- cpu30: cpu@30 { ++ cpu30: cpu@1e { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1103,7 +1103,7 @@ cpu30: cpu@30 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <30>; ++ reg = <0x1e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1121,7 +1121,7 @@ cpu30_intc: interrupt-controller { + }; + }; + +- cpu31: cpu@31 { ++ cpu31: cpu@1f { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1131,7 +1131,7 @@ cpu31: cpu@31 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <31>; ++ reg = <0x1f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1149,7 +1149,7 @@ cpu31_intc: interrupt-controller { + }; + }; + +- cpu32: cpu@32 { ++ cpu32: cpu@20 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1159,7 +1159,7 @@ cpu32: cpu@32 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <32>; ++ reg = <0x20>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1177,7 +1177,7 @@ cpu32_intc: interrupt-controller { + }; + }; + +- cpu33: cpu@33 { ++ cpu33: cpu@21 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1187,7 +1187,7 @@ cpu33: cpu@33 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <33>; ++ reg = <0x21>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1205,7 +1205,7 @@ cpu33_intc: interrupt-controller { + }; + }; + +- cpu34: cpu@34 { ++ cpu34: cpu@22 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1215,7 +1215,7 @@ cpu34: cpu@34 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <34>; ++ reg = <0x22>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1233,7 +1233,7 @@ cpu34_intc: interrupt-controller { + }; + }; + +- cpu35: cpu@35 { ++ cpu35: cpu@23 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1243,7 +1243,7 @@ cpu35: cpu@35 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <35>; ++ reg = <0x23>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1261,7 +1261,7 @@ cpu35_intc: interrupt-controller { + }; + }; + +- cpu36: cpu@36 { ++ cpu36: cpu@24 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1271,7 +1271,7 @@ cpu36: cpu@36 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <36>; ++ reg = <0x24>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1289,7 +1289,7 @@ cpu36_intc: interrupt-controller { + }; + }; + +- cpu37: cpu@37 { ++ cpu37: cpu@25 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1299,7 +1299,7 @@ cpu37: cpu@37 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <37>; ++ reg = <0x25>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1317,7 +1317,7 @@ cpu37_intc: interrupt-controller { + }; + }; + +- cpu38: cpu@38 { ++ cpu38: cpu@26 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1327,7 +1327,7 @@ cpu38: cpu@38 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <38>; ++ reg = <0x26>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1345,7 +1345,7 @@ cpu38_intc: interrupt-controller { + }; + }; + +- cpu39: cpu@39 { ++ cpu39: cpu@27 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1355,7 +1355,7 @@ cpu39: cpu@39 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <39>; ++ reg = <0x27>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1373,7 +1373,7 @@ cpu39_intc: interrupt-controller { + }; + }; + +- cpu40: cpu@40 { ++ cpu40: cpu@28 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1383,7 +1383,7 @@ cpu40: cpu@40 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <40>; ++ reg = <0x28>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1401,7 +1401,7 @@ cpu40_intc: interrupt-controller { + }; + }; + +- cpu41: cpu@41 { ++ cpu41: cpu@29 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1411,7 +1411,7 @@ cpu41: cpu@41 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <41>; ++ reg = <0x29>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1429,7 +1429,7 @@ cpu41_intc: interrupt-controller { + }; + }; + +- cpu42: cpu@42 { ++ cpu42: cpu@2a { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1439,7 +1439,7 @@ cpu42: cpu@42 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <42>; ++ reg = <0x2a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1457,7 +1457,7 @@ cpu42_intc: interrupt-controller { + }; + }; + +- cpu43: cpu@43 { ++ cpu43: cpu@2b { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1467,7 +1467,7 @@ cpu43: cpu@43 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <43>; ++ reg = <0x2b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1485,7 +1485,7 @@ cpu43_intc: interrupt-controller { + }; + }; + +- cpu44: cpu@44 { ++ cpu44: cpu@2c { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1495,7 +1495,7 @@ cpu44: cpu@44 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <44>; ++ reg = <0x2c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1513,7 +1513,7 @@ cpu44_intc: interrupt-controller { + }; + }; + +- cpu45: cpu@45 { ++ cpu45: cpu@2d { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1523,7 +1523,7 @@ cpu45: cpu@45 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <45>; ++ reg = <0x2d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1541,7 +1541,7 @@ cpu45_intc: interrupt-controller { + }; + }; + +- cpu46: cpu@46 { ++ cpu46: cpu@2e { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1551,7 +1551,7 @@ cpu46: cpu@46 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <46>; ++ reg = <0x2e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1569,7 +1569,7 @@ cpu46_intc: interrupt-controller { + }; + }; + +- cpu47: cpu@47 { ++ cpu47: cpu@2f { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1579,7 +1579,7 @@ cpu47: cpu@47 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <47>; ++ reg = <0x2f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1597,7 +1597,7 @@ cpu47_intc: interrupt-controller { + }; + }; + +- cpu48: cpu@48 { ++ cpu48: cpu@30 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1607,7 +1607,7 @@ cpu48: cpu@48 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <48>; ++ reg = <0x30>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1625,7 +1625,7 @@ cpu48_intc: interrupt-controller { + }; + }; + +- cpu49: cpu@49 { ++ cpu49: cpu@31 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1635,7 +1635,7 @@ cpu49: cpu@49 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <49>; ++ reg = <0x31>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1653,7 +1653,7 @@ cpu49_intc: interrupt-controller { + }; + }; + +- cpu50: cpu@50 { ++ cpu50: cpu@32 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1663,7 +1663,7 @@ cpu50: cpu@50 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <50>; ++ reg = <0x32>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1681,7 +1681,7 @@ cpu50_intc: interrupt-controller { + }; + }; + +- cpu51: cpu@51 { ++ cpu51: cpu@33 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1691,7 +1691,7 @@ cpu51: cpu@51 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <51>; ++ reg = <0x33>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1709,7 +1709,7 @@ cpu51_intc: interrupt-controller { + }; + }; + +- cpu52: cpu@52 { ++ cpu52: cpu@34 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1719,7 +1719,7 @@ cpu52: cpu@52 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <52>; ++ reg = <0x34>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1737,7 +1737,7 @@ cpu52_intc: interrupt-controller { + }; + }; + +- cpu53: cpu@53 { ++ cpu53: cpu@35 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1747,7 +1747,7 @@ cpu53: cpu@53 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <53>; ++ reg = <0x35>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1765,7 +1765,7 @@ cpu53_intc: interrupt-controller { + }; + }; + +- cpu54: cpu@54 { ++ cpu54: cpu@36 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1775,7 +1775,7 @@ cpu54: cpu@54 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <54>; ++ reg = <0x36>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1793,7 +1793,7 @@ cpu54_intc: interrupt-controller { + }; + }; + +- cpu55: cpu@55 { ++ cpu55: cpu@37 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1803,7 +1803,7 @@ cpu55: cpu@55 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <55>; ++ reg = <0x37>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1821,7 +1821,7 @@ cpu55_intc: interrupt-controller { + }; + }; + +- cpu56: cpu@56 { ++ cpu56: cpu@38 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1831,7 +1831,7 @@ cpu56: cpu@56 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <56>; ++ reg = <0x38>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1849,7 +1849,7 @@ cpu56_intc: interrupt-controller { + }; + }; + +- cpu57: cpu@57 { ++ cpu57: cpu@39 { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1859,7 +1859,7 @@ cpu57: cpu@57 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <57>; ++ reg = <0x39>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1877,7 +1877,7 @@ cpu57_intc: interrupt-controller { + }; + }; + +- cpu58: cpu@58 { ++ cpu58: cpu@3a { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1887,7 +1887,7 @@ cpu58: cpu@58 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <58>; ++ reg = <0x3a>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1905,7 +1905,7 @@ cpu58_intc: interrupt-controller { + }; + }; + +- cpu59: cpu@59 { ++ cpu59: cpu@3b { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1915,7 +1915,7 @@ cpu59: cpu@59 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <59>; ++ reg = <0x3b>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1933,7 +1933,7 @@ cpu59_intc: interrupt-controller { + }; + }; + +- cpu60: cpu@60 { ++ cpu60: cpu@3c { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1943,7 +1943,7 @@ cpu60: cpu@60 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <60>; ++ reg = <0x3c>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1961,7 +1961,7 @@ cpu60_intc: interrupt-controller { + }; + }; + +- cpu61: cpu@61 { ++ cpu61: cpu@3d { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1971,7 +1971,7 @@ cpu61: cpu@61 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <61>; ++ reg = <0x3d>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -1989,7 +1989,7 @@ cpu61_intc: interrupt-controller { + }; + }; + +- cpu62: cpu@62 { ++ cpu62: cpu@3e { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -1999,7 +1999,7 @@ cpu62: cpu@62 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <62>; ++ reg = <0x3e>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +@@ -2017,7 +2017,7 @@ cpu62_intc: interrupt-controller { + }; + }; + +- cpu63: cpu@63 { ++ cpu63: cpu@3f { + compatible = "thead,c920", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; +@@ -2027,7 +2027,7 @@ cpu63: cpu@63 { + "zifencei", "zihpm", "zfh", + "xtheadvector"; + thead,vlenb = <16>; +- reg = <63>; ++ reg = <0x3f>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; +-- +2.53.0 + diff --git a/SPECS/linux/0158-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch b/SPECS/linux/0158-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch deleted file mode 100644 index 7617ba837f..0000000000 --- a/SPECS/linux/0158-FROMLIST-riscv-dts-sophgo-sg2044-use-hex-for-CPU-uni.patch +++ /dev/null @@ -1,769 +0,0 @@ -From dbe5e1f0b07c36921019f4e244b17172c9733368 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 26 Apr 2026 09:34:48 +0800 -Subject: [PATCH 158/269] FROMLIST: riscv: dts: sophgo: sg2044: use hex for CPU - unit address - -Previous the CPU unit address cpu of sg2044 use decimal, it is -not following the general convention for unit addresses of the -OF. Convent the unit address to hex to resolve this problem. - -The introduces a small change for the CPU node name, but it should -nothing since there is no direct full-path reference to these -CPU nodes. - -Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree") -Signed-off-by: Inochi Amaoto -Reviewed-by: Chen Wang -Reviewed-by: Guo Ren -Link: https://lore.kernel.org/r/20260426013449.694435-2-inochiama@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 236 ++++++++++---------- - 1 file changed, 118 insertions(+), 118 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -index 3135409c2149..f66a382c95bd 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi -@@ -14,7 +14,7 @@ cpus { - - cpu0: cpu@0 { - compatible = "thead,c920", "riscv"; -- reg = <0>; -+ reg = <0x0>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -50,7 +50,7 @@ cpu0_intc: interrupt-controller { - - cpu1: cpu@1 { - compatible = "thead,c920", "riscv"; -- reg = <1>; -+ reg = <0x1>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -86,7 +86,7 @@ cpu1_intc: interrupt-controller { - - cpu2: cpu@2 { - compatible = "thead,c920", "riscv"; -- reg = <2>; -+ reg = <0x2>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -122,7 +122,7 @@ cpu2_intc: interrupt-controller { - - cpu3: cpu@3 { - compatible = "thead,c920", "riscv"; -- reg = <3>; -+ reg = <0x3>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -158,7 +158,7 @@ cpu3_intc: interrupt-controller { - - cpu4: cpu@4 { - compatible = "thead,c920", "riscv"; -- reg = <4>; -+ reg = <0x4>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -194,7 +194,7 @@ cpu4_intc: interrupt-controller { - - cpu5: cpu@5 { - compatible = "thead,c920", "riscv"; -- reg = <5>; -+ reg = <0x5>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -230,7 +230,7 @@ cpu5_intc: interrupt-controller { - - cpu6: cpu@6 { - compatible = "thead,c920", "riscv"; -- reg = <6>; -+ reg = <0x6>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -266,7 +266,7 @@ cpu6_intc: interrupt-controller { - - cpu7: cpu@7 { - compatible = "thead,c920", "riscv"; -- reg = <7>; -+ reg = <0x7>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -302,7 +302,7 @@ cpu7_intc: interrupt-controller { - - cpu8: cpu@8 { - compatible = "thead,c920", "riscv"; -- reg = <8>; -+ reg = <0x8>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -338,7 +338,7 @@ cpu8_intc: interrupt-controller { - - cpu9: cpu@9 { - compatible = "thead,c920", "riscv"; -- reg = <9>; -+ reg = <0x9>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -372,9 +372,9 @@ cpu9_intc: interrupt-controller { - }; - }; - -- cpu10: cpu@10 { -+ cpu10: cpu@a { - compatible = "thead,c920", "riscv"; -- reg = <10>; -+ reg = <0xa>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -408,9 +408,9 @@ cpu10_intc: interrupt-controller { - }; - }; - -- cpu11: cpu@11 { -+ cpu11: cpu@b { - compatible = "thead,c920", "riscv"; -- reg = <11>; -+ reg = <0xb>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -444,9 +444,9 @@ cpu11_intc: interrupt-controller { - }; - }; - -- cpu12: cpu@12 { -+ cpu12: cpu@c { - compatible = "thead,c920", "riscv"; -- reg = <12>; -+ reg = <0xc>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -480,9 +480,9 @@ cpu12_intc: interrupt-controller { - }; - }; - -- cpu13: cpu@13 { -+ cpu13: cpu@d { - compatible = "thead,c920", "riscv"; -- reg = <13>; -+ reg = <0xd>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -516,9 +516,9 @@ cpu13_intc: interrupt-controller { - }; - }; - -- cpu14: cpu@14 { -+ cpu14: cpu@e { - compatible = "thead,c920", "riscv"; -- reg = <14>; -+ reg = <0xe>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -552,9 +552,9 @@ cpu14_intc: interrupt-controller { - }; - }; - -- cpu15: cpu@15 { -+ cpu15: cpu@f { - compatible = "thead,c920", "riscv"; -- reg = <15>; -+ reg = <0xf>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -588,9 +588,9 @@ cpu15_intc: interrupt-controller { - }; - }; - -- cpu16: cpu@16 { -+ cpu16: cpu@10 { - compatible = "thead,c920", "riscv"; -- reg = <16>; -+ reg = <0x10>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -624,9 +624,9 @@ cpu16_intc: interrupt-controller { - }; - }; - -- cpu17: cpu@17 { -+ cpu17: cpu@11 { - compatible = "thead,c920", "riscv"; -- reg = <17>; -+ reg = <0x11>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -660,9 +660,9 @@ cpu17_intc: interrupt-controller { - }; - }; - -- cpu18: cpu@18 { -+ cpu18: cpu@12 { - compatible = "thead,c920", "riscv"; -- reg = <18>; -+ reg = <0x12>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -696,9 +696,9 @@ cpu18_intc: interrupt-controller { - }; - }; - -- cpu19: cpu@19 { -+ cpu19: cpu@13 { - compatible = "thead,c920", "riscv"; -- reg = <19>; -+ reg = <0x13>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -732,9 +732,9 @@ cpu19_intc: interrupt-controller { - }; - }; - -- cpu20: cpu@20 { -+ cpu20: cpu@14 { - compatible = "thead,c920", "riscv"; -- reg = <20>; -+ reg = <0x14>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -768,9 +768,9 @@ cpu20_intc: interrupt-controller { - }; - }; - -- cpu21: cpu@21 { -+ cpu21: cpu@15 { - compatible = "thead,c920", "riscv"; -- reg = <21>; -+ reg = <0x15>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -804,9 +804,9 @@ cpu21_intc: interrupt-controller { - }; - }; - -- cpu22: cpu@22 { -+ cpu22: cpu@16 { - compatible = "thead,c920", "riscv"; -- reg = <22>; -+ reg = <0x16>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -840,9 +840,9 @@ cpu22_intc: interrupt-controller { - }; - }; - -- cpu23: cpu@23 { -+ cpu23: cpu@17 { - compatible = "thead,c920", "riscv"; -- reg = <23>; -+ reg = <0x17>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -876,9 +876,9 @@ cpu23_intc: interrupt-controller { - }; - }; - -- cpu24: cpu@24 { -+ cpu24: cpu@18 { - compatible = "thead,c920", "riscv"; -- reg = <24>; -+ reg = <0x18>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -912,9 +912,9 @@ cpu24_intc: interrupt-controller { - }; - }; - -- cpu25: cpu@25 { -+ cpu25: cpu@19 { - compatible = "thead,c920", "riscv"; -- reg = <25>; -+ reg = <0x19>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -948,9 +948,9 @@ cpu25_intc: interrupt-controller { - }; - }; - -- cpu26: cpu@26 { -+ cpu26: cpu@1a { - compatible = "thead,c920", "riscv"; -- reg = <26>; -+ reg = <0x1a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -984,9 +984,9 @@ cpu26_intc: interrupt-controller { - }; - }; - -- cpu27: cpu@27 { -+ cpu27: cpu@1b { - compatible = "thead,c920", "riscv"; -- reg = <27>; -+ reg = <0x1b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1020,9 +1020,9 @@ cpu27_intc: interrupt-controller { - }; - }; - -- cpu28: cpu@28 { -+ cpu28: cpu@1c { - compatible = "thead,c920", "riscv"; -- reg = <28>; -+ reg = <0x1c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1056,9 +1056,9 @@ cpu28_intc: interrupt-controller { - }; - }; - -- cpu29: cpu@29 { -+ cpu29: cpu@1d { - compatible = "thead,c920", "riscv"; -- reg = <29>; -+ reg = <0x1d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1092,9 +1092,9 @@ cpu29_intc: interrupt-controller { - }; - }; - -- cpu30: cpu@30 { -+ cpu30: cpu@1e { - compatible = "thead,c920", "riscv"; -- reg = <30>; -+ reg = <0x1e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1128,9 +1128,9 @@ cpu30_intc: interrupt-controller { - }; - }; - -- cpu31: cpu@31 { -+ cpu31: cpu@1f { - compatible = "thead,c920", "riscv"; -- reg = <31>; -+ reg = <0x1f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1164,9 +1164,9 @@ cpu31_intc: interrupt-controller { - }; - }; - -- cpu32: cpu@32 { -+ cpu32: cpu@20 { - compatible = "thead,c920", "riscv"; -- reg = <32>; -+ reg = <0x20>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1200,9 +1200,9 @@ cpu32_intc: interrupt-controller { - }; - }; - -- cpu33: cpu@33 { -+ cpu33: cpu@21 { - compatible = "thead,c920", "riscv"; -- reg = <33>; -+ reg = <0x21>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1236,9 +1236,9 @@ cpu33_intc: interrupt-controller { - }; - }; - -- cpu34: cpu@34 { -+ cpu34: cpu@22 { - compatible = "thead,c920", "riscv"; -- reg = <34>; -+ reg = <0x22>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1272,9 +1272,9 @@ cpu34_intc: interrupt-controller { - }; - }; - -- cpu35: cpu@35 { -+ cpu35: cpu@23 { - compatible = "thead,c920", "riscv"; -- reg = <35>; -+ reg = <0x23>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1308,9 +1308,9 @@ cpu35_intc: interrupt-controller { - }; - }; - -- cpu36: cpu@36 { -+ cpu36: cpu@24 { - compatible = "thead,c920", "riscv"; -- reg = <36>; -+ reg = <0x24>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1344,9 +1344,9 @@ cpu36_intc: interrupt-controller { - }; - }; - -- cpu37: cpu@37 { -+ cpu37: cpu@25 { - compatible = "thead,c920", "riscv"; -- reg = <37>; -+ reg = <0x25>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1380,9 +1380,9 @@ cpu37_intc: interrupt-controller { - }; - }; - -- cpu38: cpu@38 { -+ cpu38: cpu@26 { - compatible = "thead,c920", "riscv"; -- reg = <38>; -+ reg = <0x26>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1416,9 +1416,9 @@ cpu38_intc: interrupt-controller { - }; - }; - -- cpu39: cpu@39 { -+ cpu39: cpu@27 { - compatible = "thead,c920", "riscv"; -- reg = <39>; -+ reg = <0x27>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1452,9 +1452,9 @@ cpu39_intc: interrupt-controller { - }; - }; - -- cpu40: cpu@40 { -+ cpu40: cpu@28 { - compatible = "thead,c920", "riscv"; -- reg = <40>; -+ reg = <0x28>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1488,9 +1488,9 @@ cpu40_intc: interrupt-controller { - }; - }; - -- cpu41: cpu@41 { -+ cpu41: cpu@29 { - compatible = "thead,c920", "riscv"; -- reg = <41>; -+ reg = <0x29>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1524,9 +1524,9 @@ cpu41_intc: interrupt-controller { - }; - }; - -- cpu42: cpu@42 { -+ cpu42: cpu@2a { - compatible = "thead,c920", "riscv"; -- reg = <42>; -+ reg = <0x2a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1560,9 +1560,9 @@ cpu42_intc: interrupt-controller { - }; - }; - -- cpu43: cpu@43 { -+ cpu43: cpu@2b { - compatible = "thead,c920", "riscv"; -- reg = <43>; -+ reg = <0x2b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1596,9 +1596,9 @@ cpu43_intc: interrupt-controller { - }; - }; - -- cpu44: cpu@44 { -+ cpu44: cpu@2c { - compatible = "thead,c920", "riscv"; -- reg = <44>; -+ reg = <0x2c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1632,9 +1632,9 @@ cpu44_intc: interrupt-controller { - }; - }; - -- cpu45: cpu@45 { -+ cpu45: cpu@2d { - compatible = "thead,c920", "riscv"; -- reg = <45>; -+ reg = <0x2d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1668,9 +1668,9 @@ cpu45_intc: interrupt-controller { - }; - }; - -- cpu46: cpu@46 { -+ cpu46: cpu@2e { - compatible = "thead,c920", "riscv"; -- reg = <46>; -+ reg = <0x2e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1704,9 +1704,9 @@ cpu46_intc: interrupt-controller { - }; - }; - -- cpu47: cpu@47 { -+ cpu47: cpu@2f { - compatible = "thead,c920", "riscv"; -- reg = <47>; -+ reg = <0x2f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1740,9 +1740,9 @@ cpu47_intc: interrupt-controller { - }; - }; - -- cpu48: cpu@48 { -+ cpu48: cpu@30 { - compatible = "thead,c920", "riscv"; -- reg = <48>; -+ reg = <0x30>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1776,9 +1776,9 @@ cpu48_intc: interrupt-controller { - }; - }; - -- cpu49: cpu@49 { -+ cpu49: cpu@31 { - compatible = "thead,c920", "riscv"; -- reg = <49>; -+ reg = <0x31>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1812,9 +1812,9 @@ cpu49_intc: interrupt-controller { - }; - }; - -- cpu50: cpu@50 { -+ cpu50: cpu@32 { - compatible = "thead,c920", "riscv"; -- reg = <50>; -+ reg = <0x32>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1848,9 +1848,9 @@ cpu50_intc: interrupt-controller { - }; - }; - -- cpu51: cpu@51 { -+ cpu51: cpu@33 { - compatible = "thead,c920", "riscv"; -- reg = <51>; -+ reg = <0x33>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1884,9 +1884,9 @@ cpu51_intc: interrupt-controller { - }; - }; - -- cpu52: cpu@52 { -+ cpu52: cpu@34 { - compatible = "thead,c920", "riscv"; -- reg = <52>; -+ reg = <0x34>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1920,9 +1920,9 @@ cpu52_intc: interrupt-controller { - }; - }; - -- cpu53: cpu@53 { -+ cpu53: cpu@35 { - compatible = "thead,c920", "riscv"; -- reg = <53>; -+ reg = <0x35>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1956,9 +1956,9 @@ cpu53_intc: interrupt-controller { - }; - }; - -- cpu54: cpu@54 { -+ cpu54: cpu@36 { - compatible = "thead,c920", "riscv"; -- reg = <54>; -+ reg = <0x36>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1992,9 +1992,9 @@ cpu54_intc: interrupt-controller { - }; - }; - -- cpu55: cpu@55 { -+ cpu55: cpu@37 { - compatible = "thead,c920", "riscv"; -- reg = <55>; -+ reg = <0x37>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2028,9 +2028,9 @@ cpu55_intc: interrupt-controller { - }; - }; - -- cpu56: cpu@56 { -+ cpu56: cpu@38 { - compatible = "thead,c920", "riscv"; -- reg = <56>; -+ reg = <0x38>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2064,9 +2064,9 @@ cpu56_intc: interrupt-controller { - }; - }; - -- cpu57: cpu@57 { -+ cpu57: cpu@39 { - compatible = "thead,c920", "riscv"; -- reg = <57>; -+ reg = <0x39>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2100,9 +2100,9 @@ cpu57_intc: interrupt-controller { - }; - }; - -- cpu58: cpu@58 { -+ cpu58: cpu@3a { - compatible = "thead,c920", "riscv"; -- reg = <58>; -+ reg = <0x3a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2136,9 +2136,9 @@ cpu58_intc: interrupt-controller { - }; - }; - -- cpu59: cpu@59 { -+ cpu59: cpu@3b { - compatible = "thead,c920", "riscv"; -- reg = <59>; -+ reg = <0x3b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2172,9 +2172,9 @@ cpu59_intc: interrupt-controller { - }; - }; - -- cpu60: cpu@60 { -+ cpu60: cpu@3c { - compatible = "thead,c920", "riscv"; -- reg = <60>; -+ reg = <0x3c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2208,9 +2208,9 @@ cpu60_intc: interrupt-controller { - }; - }; - -- cpu61: cpu@61 { -+ cpu61: cpu@3d { - compatible = "thead,c920", "riscv"; -- reg = <61>; -+ reg = <0x3d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2244,9 +2244,9 @@ cpu61_intc: interrupt-controller { - }; - }; - -- cpu62: cpu@62 { -+ cpu62: cpu@3e { - compatible = "thead,c920", "riscv"; -- reg = <62>; -+ reg = <0x3e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2280,9 +2280,9 @@ cpu62_intc: interrupt-controller { - }; - }; - -- cpu63: cpu@63 { -+ cpu63: cpu@3f { - compatible = "thead,c920", "riscv"; -- reg = <63>; -+ reg = <0x3f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; --- -2.53.0 - diff --git a/SPECS/linux/0159-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch b/SPECS/linux/0159-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch new file mode 100644 index 0000000000..30acf3c22e --- /dev/null +++ b/SPECS/linux/0159-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch @@ -0,0 +1,66 @@ +From 71f39070c3ca464a6f2e1961a956feb9cae1ff73 Mon Sep 17 00:00:00 2001 +From: Nam Cao +Date: Tue, 7 Apr 2026 14:06:39 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: Fix fast_unaligned_access_speed_key not + getting initialized + +The static key fast_unaligned_access_speed_key is supposed to be +initialized after check_unaligned_access_all_cpus() has been completed. + +However, check_unaligned_access_all_cpus() has been moved to late_initcall +while setting fast_unaligned_access_speed_key still happens at +arch_initcall_sync, thus the static key does not get properly initialized. + +fast_unaligned_access_speed_key can still be initialized in CPU hotplug +events, but that cannot be relied on. + +Move fast_unaligned_access_speed_key's initialization into +check_unaligned_access_all_cpus() to fix this issue. This also prevent +someone from moving one initcall while forgetting the other in the future. + +Fixes: 6455c6c11827 ("riscv: Clean up & optimize unaligned scalar access probe") +Reported-by: Michael Neuling +Closes: https://lore.kernel.org/linux-riscv/CAEjGV6y0=bSLp_wrS0uHFj1S2TCRtz4GKzaU5O-L1VV-EL7Nnw@mail.gmail.com/ +Signed-off-by: Nam Cao +Link: https://lore.kernel.org/r/20260407120639.4006031-1-namcao@linutronix.de +Signed-off-by: Han Gao +--- + arch/riscv/kernel/unaligned_access_speed.c | 15 ++++----------- + 1 file changed, 4 insertions(+), 11 deletions(-) + +diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c +index b36a6a56f404..45411c3670f3 100644 +--- a/arch/riscv/kernel/unaligned_access_speed.c ++++ b/arch/riscv/kernel/unaligned_access_speed.c +@@ -223,17 +223,6 @@ static void set_unaligned_access_static_branches(void) + modify_unaligned_access_branches(&fast_and_online, num_online_cpus()); + } + +-static int __init lock_and_set_unaligned_access_static_branch(void) +-{ +- cpus_read_lock(); +- set_unaligned_access_static_branches(); +- cpus_read_unlock(); +- +- return 0; +-} +- +-arch_initcall_sync(lock_and_set_unaligned_access_static_branch); +- + static int riscv_online_cpu(unsigned int cpu) + { + int ret = cpu_online_unaligned_access_init(cpu); +@@ -491,6 +480,10 @@ static int __init check_unaligned_access_all_cpus(void) + cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", + riscv_online_cpu_vec, NULL); + ++ cpus_read_lock(); ++ set_unaligned_access_static_branches(); ++ cpus_read_unlock(); ++ + return 0; + } + +-- +2.53.0 + diff --git a/SPECS/linux/0159-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch b/SPECS/linux/0159-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch deleted file mode 100644 index 7255bba9d2..0000000000 --- a/SPECS/linux/0159-FROMLIST-riscv-dts-sophgo-sg2042-use-hex-for-CPU-uni.patch +++ /dev/null @@ -1,1095 +0,0 @@ -From 578b44f1182da116c41440033cf90ba82ff1d047 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 26 Apr 2026 09:34:49 +0800 -Subject: [PATCH 159/269] FROMLIST: riscv: dts: sophgo: sg2042: use hex for CPU - unit address - -Previous the CPU unit address cpu of sg2042 use decimal, it is -not following the general convention for unit addresses of the -OF. Convent the unit address to hex to resolve this problem. - -The introduces a small change for the CPU node name, but it should -affect nothing since there is no direct full-path reference to -these CPU nodes. - -Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10") -Signed-off-by: Inochi Amaoto -Tested-by: Chen Wang # Pioneerbox. -Reviewed-by: Guo Ren -Reviewed-by: Chen Wang -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20260426013449.694435-3-inochiama@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 236 ++++++++++---------- - 1 file changed, 118 insertions(+), 118 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -index 509488eee432..fd8906b313d2 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -@@ -263,7 +263,7 @@ cpu0: cpu@0 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <0>; -+ reg = <0x0>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -291,7 +291,7 @@ cpu1: cpu@1 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <1>; -+ reg = <0x1>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -319,7 +319,7 @@ cpu2: cpu@2 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <2>; -+ reg = <0x2>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -347,7 +347,7 @@ cpu3: cpu@3 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <3>; -+ reg = <0x3>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -375,7 +375,7 @@ cpu4: cpu@4 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <4>; -+ reg = <0x4>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -403,7 +403,7 @@ cpu5: cpu@5 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <5>; -+ reg = <0x5>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -431,7 +431,7 @@ cpu6: cpu@6 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <6>; -+ reg = <0x6>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -459,7 +459,7 @@ cpu7: cpu@7 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <7>; -+ reg = <0x7>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -487,7 +487,7 @@ cpu8: cpu@8 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <8>; -+ reg = <0x8>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -515,7 +515,7 @@ cpu9: cpu@9 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <9>; -+ reg = <0x9>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -533,7 +533,7 @@ cpu9_intc: interrupt-controller { - }; - }; - -- cpu10: cpu@10 { -+ cpu10: cpu@a { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -543,7 +543,7 @@ cpu10: cpu@10 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <10>; -+ reg = <0xa>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -561,7 +561,7 @@ cpu10_intc: interrupt-controller { - }; - }; - -- cpu11: cpu@11 { -+ cpu11: cpu@b { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -571,7 +571,7 @@ cpu11: cpu@11 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <11>; -+ reg = <0xb>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -589,7 +589,7 @@ cpu11_intc: interrupt-controller { - }; - }; - -- cpu12: cpu@12 { -+ cpu12: cpu@c { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -599,7 +599,7 @@ cpu12: cpu@12 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <12>; -+ reg = <0xc>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -617,7 +617,7 @@ cpu12_intc: interrupt-controller { - }; - }; - -- cpu13: cpu@13 { -+ cpu13: cpu@d { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -627,7 +627,7 @@ cpu13: cpu@13 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <13>; -+ reg = <0xd>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -645,7 +645,7 @@ cpu13_intc: interrupt-controller { - }; - }; - -- cpu14: cpu@14 { -+ cpu14: cpu@e { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -655,7 +655,7 @@ cpu14: cpu@14 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <14>; -+ reg = <0xe>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -673,7 +673,7 @@ cpu14_intc: interrupt-controller { - }; - }; - -- cpu15: cpu@15 { -+ cpu15: cpu@f { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -683,7 +683,7 @@ cpu15: cpu@15 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <15>; -+ reg = <0xf>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -701,7 +701,7 @@ cpu15_intc: interrupt-controller { - }; - }; - -- cpu16: cpu@16 { -+ cpu16: cpu@10 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -711,7 +711,7 @@ cpu16: cpu@16 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <16>; -+ reg = <0x10>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -729,7 +729,7 @@ cpu16_intc: interrupt-controller { - }; - }; - -- cpu17: cpu@17 { -+ cpu17: cpu@11 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -739,7 +739,7 @@ cpu17: cpu@17 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <17>; -+ reg = <0x11>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -757,7 +757,7 @@ cpu17_intc: interrupt-controller { - }; - }; - -- cpu18: cpu@18 { -+ cpu18: cpu@12 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -767,7 +767,7 @@ cpu18: cpu@18 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <18>; -+ reg = <0x12>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -785,7 +785,7 @@ cpu18_intc: interrupt-controller { - }; - }; - -- cpu19: cpu@19 { -+ cpu19: cpu@13 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -795,7 +795,7 @@ cpu19: cpu@19 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <19>; -+ reg = <0x13>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -813,7 +813,7 @@ cpu19_intc: interrupt-controller { - }; - }; - -- cpu20: cpu@20 { -+ cpu20: cpu@14 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -823,7 +823,7 @@ cpu20: cpu@20 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <20>; -+ reg = <0x14>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -841,7 +841,7 @@ cpu20_intc: interrupt-controller { - }; - }; - -- cpu21: cpu@21 { -+ cpu21: cpu@15 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -851,7 +851,7 @@ cpu21: cpu@21 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <21>; -+ reg = <0x15>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -869,7 +869,7 @@ cpu21_intc: interrupt-controller { - }; - }; - -- cpu22: cpu@22 { -+ cpu22: cpu@16 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -879,7 +879,7 @@ cpu22: cpu@22 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <22>; -+ reg = <0x16>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -897,7 +897,7 @@ cpu22_intc: interrupt-controller { - }; - }; - -- cpu23: cpu@23 { -+ cpu23: cpu@17 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -907,7 +907,7 @@ cpu23: cpu@23 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <23>; -+ reg = <0x17>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -925,7 +925,7 @@ cpu23_intc: interrupt-controller { - }; - }; - -- cpu24: cpu@24 { -+ cpu24: cpu@18 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -935,7 +935,7 @@ cpu24: cpu@24 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <24>; -+ reg = <0x18>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -953,7 +953,7 @@ cpu24_intc: interrupt-controller { - }; - }; - -- cpu25: cpu@25 { -+ cpu25: cpu@19 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -963,7 +963,7 @@ cpu25: cpu@25 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <25>; -+ reg = <0x19>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -981,7 +981,7 @@ cpu25_intc: interrupt-controller { - }; - }; - -- cpu26: cpu@26 { -+ cpu26: cpu@1a { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -991,7 +991,7 @@ cpu26: cpu@26 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <26>; -+ reg = <0x1a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1009,7 +1009,7 @@ cpu26_intc: interrupt-controller { - }; - }; - -- cpu27: cpu@27 { -+ cpu27: cpu@1b { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1019,7 +1019,7 @@ cpu27: cpu@27 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <27>; -+ reg = <0x1b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1037,7 +1037,7 @@ cpu27_intc: interrupt-controller { - }; - }; - -- cpu28: cpu@28 { -+ cpu28: cpu@1c { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1047,7 +1047,7 @@ cpu28: cpu@28 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <28>; -+ reg = <0x1c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1065,7 +1065,7 @@ cpu28_intc: interrupt-controller { - }; - }; - -- cpu29: cpu@29 { -+ cpu29: cpu@1d { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1075,7 +1075,7 @@ cpu29: cpu@29 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <29>; -+ reg = <0x1d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1093,7 +1093,7 @@ cpu29_intc: interrupt-controller { - }; - }; - -- cpu30: cpu@30 { -+ cpu30: cpu@1e { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1103,7 +1103,7 @@ cpu30: cpu@30 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <30>; -+ reg = <0x1e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1121,7 +1121,7 @@ cpu30_intc: interrupt-controller { - }; - }; - -- cpu31: cpu@31 { -+ cpu31: cpu@1f { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1131,7 +1131,7 @@ cpu31: cpu@31 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <31>; -+ reg = <0x1f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1149,7 +1149,7 @@ cpu31_intc: interrupt-controller { - }; - }; - -- cpu32: cpu@32 { -+ cpu32: cpu@20 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1159,7 +1159,7 @@ cpu32: cpu@32 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <32>; -+ reg = <0x20>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1177,7 +1177,7 @@ cpu32_intc: interrupt-controller { - }; - }; - -- cpu33: cpu@33 { -+ cpu33: cpu@21 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1187,7 +1187,7 @@ cpu33: cpu@33 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <33>; -+ reg = <0x21>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1205,7 +1205,7 @@ cpu33_intc: interrupt-controller { - }; - }; - -- cpu34: cpu@34 { -+ cpu34: cpu@22 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1215,7 +1215,7 @@ cpu34: cpu@34 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <34>; -+ reg = <0x22>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1233,7 +1233,7 @@ cpu34_intc: interrupt-controller { - }; - }; - -- cpu35: cpu@35 { -+ cpu35: cpu@23 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1243,7 +1243,7 @@ cpu35: cpu@35 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <35>; -+ reg = <0x23>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1261,7 +1261,7 @@ cpu35_intc: interrupt-controller { - }; - }; - -- cpu36: cpu@36 { -+ cpu36: cpu@24 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1271,7 +1271,7 @@ cpu36: cpu@36 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <36>; -+ reg = <0x24>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1289,7 +1289,7 @@ cpu36_intc: interrupt-controller { - }; - }; - -- cpu37: cpu@37 { -+ cpu37: cpu@25 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1299,7 +1299,7 @@ cpu37: cpu@37 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <37>; -+ reg = <0x25>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1317,7 +1317,7 @@ cpu37_intc: interrupt-controller { - }; - }; - -- cpu38: cpu@38 { -+ cpu38: cpu@26 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1327,7 +1327,7 @@ cpu38: cpu@38 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <38>; -+ reg = <0x26>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1345,7 +1345,7 @@ cpu38_intc: interrupt-controller { - }; - }; - -- cpu39: cpu@39 { -+ cpu39: cpu@27 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1355,7 +1355,7 @@ cpu39: cpu@39 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <39>; -+ reg = <0x27>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1373,7 +1373,7 @@ cpu39_intc: interrupt-controller { - }; - }; - -- cpu40: cpu@40 { -+ cpu40: cpu@28 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1383,7 +1383,7 @@ cpu40: cpu@40 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <40>; -+ reg = <0x28>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1401,7 +1401,7 @@ cpu40_intc: interrupt-controller { - }; - }; - -- cpu41: cpu@41 { -+ cpu41: cpu@29 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1411,7 +1411,7 @@ cpu41: cpu@41 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <41>; -+ reg = <0x29>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1429,7 +1429,7 @@ cpu41_intc: interrupt-controller { - }; - }; - -- cpu42: cpu@42 { -+ cpu42: cpu@2a { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1439,7 +1439,7 @@ cpu42: cpu@42 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <42>; -+ reg = <0x2a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1457,7 +1457,7 @@ cpu42_intc: interrupt-controller { - }; - }; - -- cpu43: cpu@43 { -+ cpu43: cpu@2b { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1467,7 +1467,7 @@ cpu43: cpu@43 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <43>; -+ reg = <0x2b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1485,7 +1485,7 @@ cpu43_intc: interrupt-controller { - }; - }; - -- cpu44: cpu@44 { -+ cpu44: cpu@2c { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1495,7 +1495,7 @@ cpu44: cpu@44 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <44>; -+ reg = <0x2c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1513,7 +1513,7 @@ cpu44_intc: interrupt-controller { - }; - }; - -- cpu45: cpu@45 { -+ cpu45: cpu@2d { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1523,7 +1523,7 @@ cpu45: cpu@45 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <45>; -+ reg = <0x2d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1541,7 +1541,7 @@ cpu45_intc: interrupt-controller { - }; - }; - -- cpu46: cpu@46 { -+ cpu46: cpu@2e { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1551,7 +1551,7 @@ cpu46: cpu@46 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <46>; -+ reg = <0x2e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1569,7 +1569,7 @@ cpu46_intc: interrupt-controller { - }; - }; - -- cpu47: cpu@47 { -+ cpu47: cpu@2f { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1579,7 +1579,7 @@ cpu47: cpu@47 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <47>; -+ reg = <0x2f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1597,7 +1597,7 @@ cpu47_intc: interrupt-controller { - }; - }; - -- cpu48: cpu@48 { -+ cpu48: cpu@30 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1607,7 +1607,7 @@ cpu48: cpu@48 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <48>; -+ reg = <0x30>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1625,7 +1625,7 @@ cpu48_intc: interrupt-controller { - }; - }; - -- cpu49: cpu@49 { -+ cpu49: cpu@31 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1635,7 +1635,7 @@ cpu49: cpu@49 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <49>; -+ reg = <0x31>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1653,7 +1653,7 @@ cpu49_intc: interrupt-controller { - }; - }; - -- cpu50: cpu@50 { -+ cpu50: cpu@32 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1663,7 +1663,7 @@ cpu50: cpu@50 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <50>; -+ reg = <0x32>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1681,7 +1681,7 @@ cpu50_intc: interrupt-controller { - }; - }; - -- cpu51: cpu@51 { -+ cpu51: cpu@33 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1691,7 +1691,7 @@ cpu51: cpu@51 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <51>; -+ reg = <0x33>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1709,7 +1709,7 @@ cpu51_intc: interrupt-controller { - }; - }; - -- cpu52: cpu@52 { -+ cpu52: cpu@34 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1719,7 +1719,7 @@ cpu52: cpu@52 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <52>; -+ reg = <0x34>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1737,7 +1737,7 @@ cpu52_intc: interrupt-controller { - }; - }; - -- cpu53: cpu@53 { -+ cpu53: cpu@35 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1747,7 +1747,7 @@ cpu53: cpu@53 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <53>; -+ reg = <0x35>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1765,7 +1765,7 @@ cpu53_intc: interrupt-controller { - }; - }; - -- cpu54: cpu@54 { -+ cpu54: cpu@36 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1775,7 +1775,7 @@ cpu54: cpu@54 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <54>; -+ reg = <0x36>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1793,7 +1793,7 @@ cpu54_intc: interrupt-controller { - }; - }; - -- cpu55: cpu@55 { -+ cpu55: cpu@37 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1803,7 +1803,7 @@ cpu55: cpu@55 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <55>; -+ reg = <0x37>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1821,7 +1821,7 @@ cpu55_intc: interrupt-controller { - }; - }; - -- cpu56: cpu@56 { -+ cpu56: cpu@38 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1831,7 +1831,7 @@ cpu56: cpu@56 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <56>; -+ reg = <0x38>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1849,7 +1849,7 @@ cpu56_intc: interrupt-controller { - }; - }; - -- cpu57: cpu@57 { -+ cpu57: cpu@39 { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1859,7 +1859,7 @@ cpu57: cpu@57 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <57>; -+ reg = <0x39>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1877,7 +1877,7 @@ cpu57_intc: interrupt-controller { - }; - }; - -- cpu58: cpu@58 { -+ cpu58: cpu@3a { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1887,7 +1887,7 @@ cpu58: cpu@58 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <58>; -+ reg = <0x3a>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1905,7 +1905,7 @@ cpu58_intc: interrupt-controller { - }; - }; - -- cpu59: cpu@59 { -+ cpu59: cpu@3b { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1915,7 +1915,7 @@ cpu59: cpu@59 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <59>; -+ reg = <0x3b>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1933,7 +1933,7 @@ cpu59_intc: interrupt-controller { - }; - }; - -- cpu60: cpu@60 { -+ cpu60: cpu@3c { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1943,7 +1943,7 @@ cpu60: cpu@60 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <60>; -+ reg = <0x3c>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1961,7 +1961,7 @@ cpu60_intc: interrupt-controller { - }; - }; - -- cpu61: cpu@61 { -+ cpu61: cpu@3d { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1971,7 +1971,7 @@ cpu61: cpu@61 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <61>; -+ reg = <0x3d>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -1989,7 +1989,7 @@ cpu61_intc: interrupt-controller { - }; - }; - -- cpu62: cpu@62 { -+ cpu62: cpu@3e { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -1999,7 +1999,7 @@ cpu62: cpu@62 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <62>; -+ reg = <0x3e>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; -@@ -2017,7 +2017,7 @@ cpu62_intc: interrupt-controller { - }; - }; - -- cpu63: cpu@63 { -+ cpu63: cpu@3f { - compatible = "thead,c920", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; -@@ -2027,7 +2027,7 @@ cpu63: cpu@63 { - "zifencei", "zihpm", "zfh", - "xtheadvector"; - thead,vlenb = <16>; -- reg = <63>; -+ reg = <0x3f>; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; --- -2.53.0 - diff --git a/SPECS/linux/0160-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch b/SPECS/linux/0160-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch deleted file mode 100644 index 64bc647c0d..0000000000 --- a/SPECS/linux/0160-FROMLIST-riscv-Fix-fast_unaligned_access_speed_key-n.patch +++ /dev/null @@ -1,66 +0,0 @@ -From cb761e8c8b38e1f04d0dda5b0ac5c6a75c828a58 Mon Sep 17 00:00:00 2001 -From: Nam Cao -Date: Tue, 7 Apr 2026 14:06:39 +0200 -Subject: [PATCH 160/269] FROMLIST: riscv: Fix fast_unaligned_access_speed_key - not getting initialized - -The static key fast_unaligned_access_speed_key is supposed to be -initialized after check_unaligned_access_all_cpus() has been completed. - -However, check_unaligned_access_all_cpus() has been moved to late_initcall -while setting fast_unaligned_access_speed_key still happens at -arch_initcall_sync, thus the static key does not get properly initialized. - -fast_unaligned_access_speed_key can still be initialized in CPU hotplug -events, but that cannot be relied on. - -Move fast_unaligned_access_speed_key's initialization into -check_unaligned_access_all_cpus() to fix this issue. This also prevent -someone from moving one initcall while forgetting the other in the future. - -Fixes: 6455c6c11827 ("riscv: Clean up & optimize unaligned scalar access probe") -Reported-by: Michael Neuling -Closes: https://lore.kernel.org/linux-riscv/CAEjGV6y0=bSLp_wrS0uHFj1S2TCRtz4GKzaU5O-L1VV-EL7Nnw@mail.gmail.com/ -Signed-off-by: Nam Cao -Link: https://lore.kernel.org/r/20260407120639.4006031-1-namcao@linutronix.de -Signed-off-by: Han Gao ---- - arch/riscv/kernel/unaligned_access_speed.c | 15 ++++----------- - 1 file changed, 4 insertions(+), 11 deletions(-) - -diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c -index b36a6a56f404..45411c3670f3 100644 ---- a/arch/riscv/kernel/unaligned_access_speed.c -+++ b/arch/riscv/kernel/unaligned_access_speed.c -@@ -223,17 +223,6 @@ static void set_unaligned_access_static_branches(void) - modify_unaligned_access_branches(&fast_and_online, num_online_cpus()); - } - --static int __init lock_and_set_unaligned_access_static_branch(void) --{ -- cpus_read_lock(); -- set_unaligned_access_static_branches(); -- cpus_read_unlock(); -- -- return 0; --} -- --arch_initcall_sync(lock_and_set_unaligned_access_static_branch); -- - static int riscv_online_cpu(unsigned int cpu) - { - int ret = cpu_online_unaligned_access_init(cpu); -@@ -491,6 +480,10 @@ static int __init check_unaligned_access_all_cpus(void) - cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", - riscv_online_cpu_vec, NULL); - -+ cpus_read_lock(); -+ set_unaligned_access_static_branches(); -+ cpus_read_unlock(); -+ - return 0; - } - --- -2.53.0 - diff --git a/SPECS/linux/0160-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch b/SPECS/linux/0160-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch new file mode 100644 index 0000000000..a8925bed5b --- /dev/null +++ b/SPECS/linux/0160-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch @@ -0,0 +1,38 @@ +From 3a363472297ffb6712b64b5421abbe5abc73bd3f Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Wed, 8 Apr 2026 00:01:43 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: sophgo: reduce SG2042 MSI count to + 16 + +The SG2042 MSI controller has one 32-bit doorbell register, and each bit +corresponds to an interrupt. At a glance, it seems that the MSI +controller can support 32 interrupts; however the PCI MSI capability +only supports 16-bit messages, which makes the high 16 interrupts +unusable in such way. + +Reduce the MSI count to 16 to prevent producing MSI message values that +cannot fit 16-bit integers. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260407160143.1182430-1-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +index 3af770549742..7eab0655f150 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi +@@ -234,7 +234,7 @@ msi: msi-controller@7030010304 { + reg-names = "clr", "doorbell"; + msi-controller; + #msi-cells = <0>; +- msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>; ++ msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>; + }; + + rpgate: clock-controller@7030010368 { +-- +2.53.0 + diff --git a/SPECS/linux/0161-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch b/SPECS/linux/0161-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch new file mode 100644 index 0000000000..be498ba15e --- /dev/null +++ b/SPECS/linux/0161-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch @@ -0,0 +1,93 @@ +From adc7e690dfd95f19848554f1988a4ddfd4128cee Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 28 Apr 2026 10:46:50 +0000 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: pwm: marvell,pxa-pwm: Add + SpacemiT K3 PWM support + +The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1 +generation, while the difference is that one additional bus clock is +added. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260428-03-k3-pwm-drv-v2-1-a532bbe45556@kernel.org +Signed-off-by: Han Gao +--- + .../bindings/pwm/marvell,pxa-pwm.yaml | 41 +++++++++++++++++-- + 1 file changed, 38 insertions(+), 3 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +index 8df327e52810..f1422a401b6b 100644 +--- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml ++++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +@@ -15,7 +15,9 @@ allOf: + properties: + compatible: + contains: +- const: spacemit,k1-pwm ++ enum: ++ - spacemit,k1-pwm ++ - spacemit,k3-pwm + then: + properties: + "#pwm-cells": +@@ -26,6 +28,26 @@ allOf: + const: 1 + description: | + Used for specifying the period length in nanoseconds. ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - spacemit,k3-pwm ++ then: ++ required: ++ - clock-names ++ properties: ++ clocks: ++ minItems: 2 ++ clock-names: ++ minItems: 2 ++ else: ++ properties: ++ clocks: ++ maxItems: 1 ++ clock-names: ++ maxItems: 1 + + properties: + compatible: +@@ -36,7 +58,9 @@ properties: + - marvell,pxa168-pwm + - marvell,pxa910-pwm + - items: +- - const: spacemit,k1-pwm ++ - enum: ++ - spacemit,k1-pwm ++ - spacemit,k3-pwm + - const: marvell,pxa910-pwm + + reg: +@@ -47,7 +71,18 @@ properties: + description: Number of cells in a pwm specifier. + + clocks: +- maxItems: 1 ++ minItems: 1 ++ items: ++ - description: The function clock ++ - description: An optional bus clock ++ ++ clock-names: ++ minItems: 1 ++ maxItems: 2 ++ oneOf: ++ - items: ++ - const: func ++ - const: bus + + resets: + maxItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux/0161-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch b/SPECS/linux/0161-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch deleted file mode 100644 index 8bfa3108e4..0000000000 --- a/SPECS/linux/0161-FROMLIST-riscv-dts-sophgo-reduce-SG2042-MSI-count-to.patch +++ /dev/null @@ -1,38 +0,0 @@ -From c73cbd2225648501d74ab4898bf20bed55227168 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 8 Apr 2026 00:01:43 +0800 -Subject: [PATCH 161/269] FROMLIST: riscv: dts: sophgo: reduce SG2042 MSI count - to 16 - -The SG2042 MSI controller has one 32-bit doorbell register, and each bit -corresponds to an interrupt. At a glance, it seems that the MSI -controller can support 32 interrupts; however the PCI MSI capability -only supports 16-bit messages, which makes the high 16 interrupts -unusable in such way. - -Reduce the MSI count to 16 to prevent producing MSI message values that -cannot fit 16-bit integers. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260407160143.1182430-1-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -index 3af770549742..7eab0655f150 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -@@ -234,7 +234,7 @@ msi: msi-controller@7030010304 { - reg-names = "clr", "doorbell"; - msi-controller; - #msi-cells = <0>; -- msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>; -+ msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>; - }; - - rpgate: clock-controller@7030010368 { --- -2.53.0 - diff --git a/SPECS/linux/0162-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch b/SPECS/linux/0162-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch deleted file mode 100644 index dd4c766187..0000000000 --- a/SPECS/linux/0162-FROMLIST-dt-bindings-pwm-marvell-pxa-pwm-Add-Spacemi.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 0cb24c01f69fc12abb2a05c7be2c30aecbfb22a1 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 28 Apr 2026 10:46:50 +0000 -Subject: [PATCH 162/269] FROMLIST: dt-bindings: pwm: marvell,pxa-pwm: Add - SpacemiT K3 PWM support - -The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1 -generation, while the difference is that one additional bus clock is -added. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260428-03-k3-pwm-drv-v2-1-a532bbe45556@kernel.org -Signed-off-by: Han Gao ---- - .../bindings/pwm/marvell,pxa-pwm.yaml | 41 +++++++++++++++++-- - 1 file changed, 38 insertions(+), 3 deletions(-) - -diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml -index 8df327e52810..f1422a401b6b 100644 ---- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml -+++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml -@@ -15,7 +15,9 @@ allOf: - properties: - compatible: - contains: -- const: spacemit,k1-pwm -+ enum: -+ - spacemit,k1-pwm -+ - spacemit,k3-pwm - then: - properties: - "#pwm-cells": -@@ -26,6 +28,26 @@ allOf: - const: 1 - description: | - Used for specifying the period length in nanoseconds. -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - spacemit,k3-pwm -+ then: -+ required: -+ - clock-names -+ properties: -+ clocks: -+ minItems: 2 -+ clock-names: -+ minItems: 2 -+ else: -+ properties: -+ clocks: -+ maxItems: 1 -+ clock-names: -+ maxItems: 1 - - properties: - compatible: -@@ -36,7 +58,9 @@ properties: - - marvell,pxa168-pwm - - marvell,pxa910-pwm - - items: -- - const: spacemit,k1-pwm -+ - enum: -+ - spacemit,k1-pwm -+ - spacemit,k3-pwm - - const: marvell,pxa910-pwm - - reg: -@@ -47,7 +71,18 @@ properties: - description: Number of cells in a pwm specifier. - - clocks: -- maxItems: 1 -+ minItems: 1 -+ items: -+ - description: The function clock -+ - description: An optional bus clock -+ -+ clock-names: -+ minItems: 1 -+ maxItems: 2 -+ oneOf: -+ - items: -+ - const: func -+ - const: bus - - resets: - maxItems: 1 --- -2.53.0 - diff --git a/SPECS/linux/0162-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch b/SPECS/linux/0162-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch new file mode 100644 index 0000000000..a7f5dc8119 --- /dev/null +++ b/SPECS/linux/0162-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch @@ -0,0 +1,47 @@ +From 154b97ebf13307c699408106e72e156ea53f3a5e Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 28 Apr 2026 10:46:51 +0000 +Subject: [RUYI PATCH] FROMLIST: pwm: pxa: Add optional bus clock + +Add one secondary optional bus clock for the PWM PXA driver, also keep it +compatible with old single clock. + +The SpacemiT K3 SoC require a bus clock for PWM controller, acquire and +enable it during probe phase. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260428-03-k3-pwm-drv-v2-2-a532bbe45556@kernel.org +Signed-off-by: Han Gao +--- + drivers/pwm/pwm-pxa.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c +index 0f5bdb0e395e..80d2fa10919f 100644 +--- a/drivers/pwm/pwm-pxa.c ++++ b/drivers/pwm/pwm-pxa.c +@@ -161,6 +161,7 @@ static int pwm_probe(struct platform_device *pdev) + const struct platform_device_id *id = platform_get_device_id(pdev); + struct pwm_chip *chip; + struct pxa_pwm_chip *pc; ++ struct clk *bus_clk; + struct device *dev = &pdev->dev; + struct reset_control *rst; + int ret = 0; +@@ -177,7 +178,12 @@ static int pwm_probe(struct platform_device *pdev) + return PTR_ERR(chip); + pc = to_pxa_pwm_chip(chip); + +- pc->clk = devm_clk_get(dev, NULL); ++ bus_clk = devm_clk_get_optional_enabled(dev, "bus"); ++ if (IS_ERR(bus_clk)) ++ return dev_err_probe(dev, PTR_ERR(bus_clk), "Failed to get bus clock\n"); ++ ++ /* Get named func clk if bus clock is valid */ ++ pc->clk = devm_clk_get(dev, bus_clk ? "func" : NULL); + if (IS_ERR(pc->clk)) + return dev_err_probe(dev, PTR_ERR(pc->clk), "Failed to get clock\n"); + +-- +2.53.0 + diff --git a/SPECS/linux/0163-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch b/SPECS/linux/0163-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch deleted file mode 100644 index 6c119665a7..0000000000 --- a/SPECS/linux/0163-FROMLIST-pwm-pxa-Add-optional-bus-clock.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 5856b37386e4f77fb317991ddf6e92158cd1e66a Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 28 Apr 2026 10:46:51 +0000 -Subject: [PATCH 163/269] FROMLIST: pwm: pxa: Add optional bus clock - -Add one secondary optional bus clock for the PWM PXA driver, also keep it -compatible with old single clock. - -The SpacemiT K3 SoC require a bus clock for PWM controller, acquire and -enable it during probe phase. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260428-03-k3-pwm-drv-v2-2-a532bbe45556@kernel.org -Signed-off-by: Han Gao ---- - drivers/pwm/pwm-pxa.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - -diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c -index 0f5bdb0e395e..80d2fa10919f 100644 ---- a/drivers/pwm/pwm-pxa.c -+++ b/drivers/pwm/pwm-pxa.c -@@ -161,6 +161,7 @@ static int pwm_probe(struct platform_device *pdev) - const struct platform_device_id *id = platform_get_device_id(pdev); - struct pwm_chip *chip; - struct pxa_pwm_chip *pc; -+ struct clk *bus_clk; - struct device *dev = &pdev->dev; - struct reset_control *rst; - int ret = 0; -@@ -177,7 +178,12 @@ static int pwm_probe(struct platform_device *pdev) - return PTR_ERR(chip); - pc = to_pxa_pwm_chip(chip); - -- pc->clk = devm_clk_get(dev, NULL); -+ bus_clk = devm_clk_get_optional_enabled(dev, "bus"); -+ if (IS_ERR(bus_clk)) -+ return dev_err_probe(dev, PTR_ERR(bus_clk), "Failed to get bus clock\n"); -+ -+ /* Get named func clk if bus clock is valid */ -+ pc->clk = devm_clk_get(dev, bus_clk ? "func" : NULL); - if (IS_ERR(pc->clk)) - return dev_err_probe(dev, PTR_ERR(pc->clk), "Failed to get clock\n"); - --- -2.53.0 - diff --git a/SPECS/linux/0163-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch b/SPECS/linux/0163-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch new file mode 100644 index 0000000000..9fd9f08770 --- /dev/null +++ b/SPECS/linux/0163-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch @@ -0,0 +1,45 @@ +From 2a9e46f7beb8ddf7a72e2a6fd50d373ea0f72d6b Mon Sep 17 00:00:00 2001 +From: Chen Pei +Date: Thu, 9 Apr 2026 19:47:36 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: ftrace: select + HAVE_BUILDTIME_MCOUNT_SORT + +RISC-V already satisfies all prerequisites for build-time mcount sorting: +the sorttable host tool handles EM_RISCV in its machine-type dispatch, and +the __mcount_loc section entries are stored as direct virtual addresses in +the final vmlinux binary, so no relocation processing is required during +the sort step. + +Select HAVE_BUILDTIME_MCOUNT_SORT so that BUILDTIME_MCOUNT_SORT is +automatically enabled when DYNAMIC_FTRACE is configured. This allows +sorttable to sort the __mcount_loc section at link time, making the +run-time ftrace initialisation path skip the software sort and reducing +kernel startup overhead. + +Verified with CONFIG_FTRACE_SORT_STARTUP_TEST=y, which confirms that +the section produced by the build is already in ascending order: + + [ 0.000000] ftrace section at ffffffff81015a60 sorted properly + +Signed-off-by: Chen Pei +Link: https://lore.kernel.org/r/20260409114736.907-1-cp0613@linux.alibaba.com +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 602b84e2b05b..4ba5392f0dca 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -152,6 +152,7 @@ config RISCV + select HAVE_ARCH_USERFAULTFD_WP if 64BIT && MMU && USERFAULTFD && RISCV_ISA_SVRSW60T59B + select HAVE_ARCH_VMAP_STACK if MMU && 64BIT + select HAVE_ASM_MODVERSIONS ++ select HAVE_BUILDTIME_MCOUNT_SORT + select HAVE_CONTEXT_TRACKING_USER + select HAVE_DEBUG_KMEMLEAK + select HAVE_DMA_CONTIGUOUS if MMU +-- +2.53.0 + diff --git a/SPECS/linux/0164-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch b/SPECS/linux/0164-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch new file mode 100644 index 0000000000..5a21fce0a2 --- /dev/null +++ b/SPECS/linux/0164-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch @@ -0,0 +1,58 @@ +From 01b3027d390d13a17f99b6e1e79066cf1f77b798 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Mon, 18 May 2026 18:00:30 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable USB3 on OrangePi + R2S + +Enable the DWC3 USB3.0 controller and its associated PHY on the +OrangePi R2S. The USB regulator provides VBUS for USB2 and USB3 +ports, but the USB2 ports are handled by a separate controller. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20260518100030.2354606-1-amadeus@jmu.edu.cn +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-r2s.dts | 23 +++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index de75f6aac740..1ecc40749e5a 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -21,6 +21,19 @@ aliases { + chosen { + stdout-path = "serial0"; + }; ++ ++ vcc5v0_usb: regulator-vcc5v0-usb { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio K1_GPIO(126) GPIO_ACTIVE_HIGH>; ++ regulator-name = "vcc5v0_usb"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&combo_phy { ++ status = "okay"; + }; + + &emmc { +@@ -90,3 +103,13 @@ &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ vbus-supply = <&vcc5v0_usb>; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux/0164-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch b/SPECS/linux/0164-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch deleted file mode 100644 index fbdfad92de..0000000000 --- a/SPECS/linux/0164-FROMLIST-riscv-ftrace-select-HAVE_BUILDTIME_MCOUNT_S.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 48ae5ff61edb51994790faefc3b2d90ad30a1d27 Mon Sep 17 00:00:00 2001 -From: Chen Pei -Date: Thu, 9 Apr 2026 19:47:36 +0800 -Subject: [PATCH 164/269] FROMLIST: riscv: ftrace: select - HAVE_BUILDTIME_MCOUNT_SORT - -RISC-V already satisfies all prerequisites for build-time mcount sorting: -the sorttable host tool handles EM_RISCV in its machine-type dispatch, and -the __mcount_loc section entries are stored as direct virtual addresses in -the final vmlinux binary, so no relocation processing is required during -the sort step. - -Select HAVE_BUILDTIME_MCOUNT_SORT so that BUILDTIME_MCOUNT_SORT is -automatically enabled when DYNAMIC_FTRACE is configured. This allows -sorttable to sort the __mcount_loc section at link time, making the -run-time ftrace initialisation path skip the software sort and reducing -kernel startup overhead. - -Verified with CONFIG_FTRACE_SORT_STARTUP_TEST=y, which confirms that -the section produced by the build is already in ascending order: - - [ 0.000000] ftrace section at ffffffff81015a60 sorted properly - -Signed-off-by: Chen Pei -Link: https://lore.kernel.org/r/20260409114736.907-1-cp0613@linux.alibaba.com -Signed-off-by: Han Gao ---- - arch/riscv/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index 602b84e2b05b..4ba5392f0dca 100644 ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -152,6 +152,7 @@ config RISCV - select HAVE_ARCH_USERFAULTFD_WP if 64BIT && MMU && USERFAULTFD && RISCV_ISA_SVRSW60T59B - select HAVE_ARCH_VMAP_STACK if MMU && 64BIT - select HAVE_ASM_MODVERSIONS -+ select HAVE_BUILDTIME_MCOUNT_SORT - select HAVE_CONTEXT_TRACKING_USER - select HAVE_DEBUG_KMEMLEAK - select HAVE_DMA_CONTIGUOUS if MMU --- -2.53.0 - diff --git a/SPECS/linux/0165-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch b/SPECS/linux/0165-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch new file mode 100644 index 0000000000..c00b9bd1c8 --- /dev/null +++ b/SPECS/linux/0165-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch @@ -0,0 +1,47 @@ +From 83a769e5b90e7ead2b105395822b7add9a03f8dd Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 28 Apr 2026 10:57:29 +0000 +Subject: [RUYI PATCH] FROMLIST: dts: riscv: spacemit: correct 32k clock + frequency + +The 32k oscillator's clock frequency is actually 32768Hz, so correct it. + +Fixes: 67072c8cd48c ("riscv: dts: spacemit: k3: add clock tree") +Fixes: a6fafa64b03a ("riscv: dts: spacemit: Add clock tree for SpacemiT K1") +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260428-06-k3-clk-osc32k-v1-1-e2378da7cb9b@kernel.org +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 2 +- + arch/riscv/boot/dts/spacemit/k3.dtsi | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index aefdbbadc9ef..8774a00a854b 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -341,7 +341,7 @@ vctcxo_3m: clock-3m { + + osc_32k: clock-32k { + compatible = "fixed-clock"; +- clock-frequency = <32000>; ++ clock-frequency = <32768>; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 81ad575f16a5..0408929f7949 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -424,7 +424,7 @@ vctcxo_3m: clock-3m { + + osc_32k: clock-32k { + compatible = "fixed-clock"; +- clock-frequency = <32000>; ++ clock-frequency = <32768>; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; +-- +2.53.0 + diff --git a/SPECS/linux/0165-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch b/SPECS/linux/0165-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch deleted file mode 100644 index 983ef875b9..0000000000 --- a/SPECS/linux/0165-FROMLIST-riscv-dts-spacemit-enable-USB3-on-OrangePi-.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 1416a000f1deffb86bfb1570180379385b1fb5a8 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Mon, 18 May 2026 18:00:30 +0800 -Subject: [PATCH 165/269] FROMLIST: riscv: dts: spacemit: enable USB3 on - OrangePi R2S - -Enable the DWC3 USB3.0 controller and its associated PHY on the -OrangePi R2S. The USB regulator provides VBUS for USB2 and USB3 -ports, but the USB2 ports are handled by a separate controller. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20260518100030.2354606-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-r2s.dts | 23 +++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -index de75f6aac740..1ecc40749e5a 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -@@ -21,6 +21,19 @@ aliases { - chosen { - stdout-path = "serial0"; - }; -+ -+ vcc5v0_usb: regulator-vcc5v0-usb { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio K1_GPIO(126) GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc5v0_usb"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&combo_phy { -+ status = "okay"; - }; - - &emmc { -@@ -90,3 +103,13 @@ &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ vbus-supply = <&vcc5v0_usb>; -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux/0166-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch b/SPECS/linux/0166-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch new file mode 100644 index 0000000000..0f9b6528a5 --- /dev/null +++ b/SPECS/linux/0166-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch @@ -0,0 +1,91 @@ +From c4760914af72008c33f318fd488152162f8bdea0 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 7 May 2026 15:33:09 +0800 +Subject: [RUYI PATCH] FROMLIST: ASoC: dt-bindings: add SpacemiT K3 SoC + compatible + +Add the spacemit,k3-i2s compatible string for the K3 SoC I2S +controller. The K3 I2S IP is the same as K1 but requires additional +clocks: a dedicated sysclk_div clock, along with common_sysclk and +common_bclk which are shared across multiple I2S controllers on K3. + +Acked-by: Rob Herring (Arm) +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260507-k3-i2s-v2-1-9cdbf95b7533@linux.spacemit.com +Signed-off-by: Han Gao +--- + .../bindings/sound/spacemit,k1-i2s.yaml | 31 +++++++++++++++++-- + 1 file changed, 29 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml +index 55bd0b307d22..240d90402e4f 100644 +--- a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml ++++ b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml +@@ -4,7 +4,7 @@ + $id: http://devicetree.org/schemas/sound/spacemit,k1-i2s.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# + +-title: K1 I2S controller ++title: SpacemiT K1/K3 I2S controller + + description: + The I2S bus (Inter-IC sound bus) is a serial link for digital +@@ -15,27 +15,54 @@ maintainers: + + allOf: + - $ref: dai-common.yaml# ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: spacemit,k3-i2s ++ then: ++ properties: ++ clocks: ++ minItems: 7 ++ clock-names: ++ minItems: 7 ++ else: ++ properties: ++ clocks: ++ maxItems: 4 ++ clock-names: ++ maxItems: 4 + + properties: + compatible: +- const: spacemit,k1-i2s ++ enum: ++ - spacemit,k1-i2s ++ - spacemit,k3-i2s + + reg: + maxItems: 1 + + clocks: ++ minItems: 4 + items: + - description: clock for I2S sysclk + - description: clock for I2S bclk + - description: clock for I2S bus + - description: clock for I2S controller ++ - description: clock for I2S sysclk divider ++ - description: clock for I2S common sysclk ++ - description: clock for I2S common bclk + + clock-names: ++ minItems: 4 + items: + - const: sysclk + - const: bclk + - const: bus + - const: func ++ - const: sysclk_div ++ - const: c_sysclk ++ - const: c_bclk + + dmas: + minItems: 1 +-- +2.53.0 + diff --git a/SPECS/linux/0166-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch b/SPECS/linux/0166-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch deleted file mode 100644 index c519c182d4..0000000000 --- a/SPECS/linux/0166-FROMLIST-dts-riscv-spacemit-correct-32k-clock-freque.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 5158f04aea351ebe25a91e303f522c482219d8ac Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Tue, 28 Apr 2026 10:57:29 +0000 -Subject: [PATCH 166/269] FROMLIST: dts: riscv: spacemit: correct 32k clock - frequency - -The 32k oscillator's clock frequency is actually 32768Hz, so correct it. - -Fixes: 67072c8cd48c ("riscv: dts: spacemit: k3: add clock tree") -Fixes: a6fafa64b03a ("riscv: dts: spacemit: Add clock tree for SpacemiT K1") -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260428-06-k3-clk-osc32k-v1-1-e2378da7cb9b@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1.dtsi | 2 +- - arch/riscv/boot/dts/spacemit/k3.dtsi | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index aefdbbadc9ef..8774a00a854b 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -341,7 +341,7 @@ vctcxo_3m: clock-3m { - - osc_32k: clock-32k { - compatible = "fixed-clock"; -- clock-frequency = <32000>; -+ clock-frequency = <32768>; - clock-output-names = "osc_32k"; - #clock-cells = <0>; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 81ad575f16a5..0408929f7949 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -424,7 +424,7 @@ vctcxo_3m: clock-3m { - - osc_32k: clock-32k { - compatible = "fixed-clock"; -- clock-frequency = <32000>; -+ clock-frequency = <32768>; - clock-output-names = "osc_32k"; - #clock-cells = <0>; - }; --- -2.53.0 - diff --git a/SPECS/linux/0167-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch b/SPECS/linux/0167-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch deleted file mode 100644 index 25df9a3f24..0000000000 --- a/SPECS/linux/0167-FROMLIST-ASoC-dt-bindings-add-SpacemiT-K3-SoC-compat.patch +++ /dev/null @@ -1,91 +0,0 @@ -From f15066d6184dab3b026b242a47bc0f4a40c709ac Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 15:33:09 +0800 -Subject: [PATCH 167/269] FROMLIST: ASoC: dt-bindings: add SpacemiT K3 SoC - compatible - -Add the spacemit,k3-i2s compatible string for the K3 SoC I2S -controller. The K3 I2S IP is the same as K1 but requires additional -clocks: a dedicated sysclk_div clock, along with common_sysclk and -common_bclk which are shared across multiple I2S controllers on K3. - -Acked-by: Rob Herring (Arm) -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-k3-i2s-v2-1-9cdbf95b7533@linux.spacemit.com -Signed-off-by: Han Gao ---- - .../bindings/sound/spacemit,k1-i2s.yaml | 31 +++++++++++++++++-- - 1 file changed, 29 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml -index 55bd0b307d22..240d90402e4f 100644 ---- a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml -+++ b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml -@@ -4,7 +4,7 @@ - $id: http://devicetree.org/schemas/sound/spacemit,k1-i2s.yaml# - $schema: http://devicetree.org/meta-schemas/core.yaml# - --title: K1 I2S controller -+title: SpacemiT K1/K3 I2S controller - - description: - The I2S bus (Inter-IC sound bus) is a serial link for digital -@@ -15,27 +15,54 @@ maintainers: - - allOf: - - $ref: dai-common.yaml# -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: spacemit,k3-i2s -+ then: -+ properties: -+ clocks: -+ minItems: 7 -+ clock-names: -+ minItems: 7 -+ else: -+ properties: -+ clocks: -+ maxItems: 4 -+ clock-names: -+ maxItems: 4 - - properties: - compatible: -- const: spacemit,k1-i2s -+ enum: -+ - spacemit,k1-i2s -+ - spacemit,k3-i2s - - reg: - maxItems: 1 - - clocks: -+ minItems: 4 - items: - - description: clock for I2S sysclk - - description: clock for I2S bclk - - description: clock for I2S bus - - description: clock for I2S controller -+ - description: clock for I2S sysclk divider -+ - description: clock for I2S common sysclk -+ - description: clock for I2S common bclk - - clock-names: -+ minItems: 4 - items: - - const: sysclk - - const: bclk - - const: bus - - const: func -+ - const: sysclk_div -+ - const: c_sysclk -+ - const: c_bclk - - dmas: - minItems: 1 --- -2.53.0 - diff --git a/SPECS/linux/0167-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch b/SPECS/linux/0167-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch new file mode 100644 index 0000000000..cd37b281e1 --- /dev/null +++ b/SPECS/linux/0167-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch @@ -0,0 +1,112 @@ +From b3edfe872c910ef2cc43efbef8ad09e83eca5a3c Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 7 May 2026 15:33:10 +0800 +Subject: [RUYI PATCH] FROMLIST: ASoC: spacemit: add K3 SoC support with + additional clocks + +Add support for the SpacemiT K3 SoC I2S controller, which shares the +same IP as K1 but requires additional clocks: sysclk_div, c_sysclk, +and c_bclk. These clocks only exist on K3 and are not present on K1. +The sysclk_div clock is present on most K3 I2S controllers except I2S1. +The c_sysclk and c_bclk clocks are shared across multiple I2S +controllers on K3. + +Use devm_clk_get_optional_enabled() to acquire these clocks so that +the driver works on both K1 (where they are absent) and K3 without +needing SoC-specific match data. For K3, the sysclk_div rate is set +before sysclk in set_sysclk, and the common clock rates are configured +in hw_params based on the sample rate. + +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260507-k3-i2s-v2-2-9cdbf95b7533@linux.spacemit.com +Signed-off-by: Han Gao +--- + sound/soc/spacemit/k1_i2s.c | 36 +++++++++++++++++++++++++++++++++++- + 1 file changed, 35 insertions(+), 1 deletion(-) + +diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c +index 5420ca2aefbd..8871fc15b29c 100644 +--- a/sound/soc/spacemit/k1_i2s.c ++++ b/sound/soc/spacemit/k1_i2s.c +@@ -53,6 +53,9 @@ struct spacemit_i2s_dev { + struct clk *sysclk; + struct clk *bclk; + struct clk *sspa_clk; ++ struct clk *sysclk_div; ++ struct clk *c_sysclk; ++ struct clk *c_bclk; + + struct snd_dmaengine_dai_dma_data capture_dma_data; + struct snd_dmaengine_dai_dma_data playback_dma_data; +@@ -206,6 +209,14 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, + params_rate(params) * + data_bits; + ++ ret = clk_set_rate(i2s->c_sysclk, bclk_rate * 2); ++ if (ret) ++ return ret; ++ ++ ret = clk_set_rate(i2s->c_bclk, bclk_rate); ++ if (ret) ++ return ret; ++ + ret = clk_set_rate(i2s->bclk, bclk_rate); + if (ret) + return ret; +@@ -217,10 +228,17 @@ static int spacemit_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, + unsigned int freq, int dir) + { + struct spacemit_i2s_dev *i2s = dev_get_drvdata(cpu_dai->dev); ++ int ret; + + if (freq == 0) + return 0; + ++ if (i2s->sysclk_div) { ++ ret = clk_set_rate(i2s->sysclk_div, freq); ++ if (ret) ++ return ret; ++ } ++ + return clk_set_rate(i2s->sysclk, freq); + } + +@@ -436,6 +454,21 @@ static int spacemit_i2s_probe(struct platform_device *pdev) + return dev_err_probe(i2s->dev, PTR_ERR(i2s->sspa_clk), + "failed to enable sspa clock\n"); + ++ i2s->sysclk_div = devm_clk_get_optional_enabled(i2s->dev, "sysclk_div"); ++ if (IS_ERR(i2s->sysclk_div)) ++ return dev_err_probe(i2s->dev, PTR_ERR(i2s->sysclk_div), ++ "failed to enable sysclk_div clock\n"); ++ ++ i2s->c_sysclk = devm_clk_get_optional_enabled(i2s->dev, "c_sysclk"); ++ if (IS_ERR(i2s->c_sysclk)) ++ return dev_err_probe(i2s->dev, PTR_ERR(i2s->c_sysclk), ++ "failed to enable c_sysclk clock\n"); ++ ++ i2s->c_bclk = devm_clk_get_optional_enabled(i2s->dev, "c_bclk"); ++ if (IS_ERR(i2s->c_bclk)) ++ return dev_err_probe(i2s->dev, PTR_ERR(i2s->c_bclk), ++ "failed to enable c_bclk clock\n"); ++ + i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(i2s->base)) + return dev_err_probe(i2s->dev, PTR_ERR(i2s->base), "failed to map registers\n"); +@@ -462,6 +495,7 @@ static int spacemit_i2s_probe(struct platform_device *pdev) + + static const struct of_device_id spacemit_i2s_of_match[] = { + { .compatible = "spacemit,k1-i2s", }, ++ { .compatible = "spacemit,k3-i2s", }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, spacemit_i2s_of_match); +@@ -476,4 +510,4 @@ static struct platform_driver spacemit_i2s_driver = { + module_platform_driver(spacemit_i2s_driver); + + MODULE_LICENSE("GPL"); +-MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1 SoC"); ++MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1/K3 SoC"); +-- +2.53.0 + diff --git a/SPECS/linux/0168-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch b/SPECS/linux/0168-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch new file mode 100644 index 0000000000..d013b1f727 --- /dev/null +++ b/SPECS/linux/0168-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch @@ -0,0 +1,96 @@ +From 272949e114db6624dac92d1e35c258fb2eebdfd3 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 7 May 2026 18:31:42 +0800 +Subject: [RUYI PATCH] FROMLIST: ASoC: soc-dai: add shared BCLK clock for + cross-DAI rate constraints + +Add a bclk field to struct snd_soc_dai and a helper function +snd_soc_dai_set_bclk_clk() that platform drivers can use to declare +which clock is their BCLK. + +Also cache the bclk_ratio in snd_soc_dai_set_bclk_ratio() so that +the framework can use it later in hw_rule evaluation for TDM +configurations where BCLK = rate * slots * slot_width. + +When multiple DAIs on the same card share the same physical BCLK +(detected via clk_is_match()), the ASoC core can automatically +constrain their hw_params so that the resulting BCLK rates are +compatible. This commit adds the data structure support; the actual +constraint logic follows in the next patch. + +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-1-ede05a22f732@linux.spacemit.com +Signed-off-by: Han Gao +--- + include/sound/soc-dai.h | 7 +++++++ + sound/soc/soc-dai.c | 18 ++++++++++++++++++ + 2 files changed, 25 insertions(+) + +diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h +index 224396927aef..6d3a0ce02fd8 100644 +--- a/include/sound/soc-dai.h ++++ b/include/sound/soc-dai.h +@@ -17,6 +17,7 @@ + struct snd_pcm_substream; + struct snd_soc_dapm_widget; + struct snd_compr_stream; ++struct clk; + + /* + * DAI hardware audio formats. +@@ -173,6 +174,8 @@ int snd_soc_dai_set_pll(struct snd_soc_dai *dai, + + int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio); + ++void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk); ++ + /* Digital Audio interface formatting */ + int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd); + u64 snd_soc_dai_get_fmt(const struct snd_soc_dai *dai, int priority); +@@ -451,6 +454,10 @@ struct snd_soc_dai { + unsigned int symmetric_channels; + unsigned int symmetric_sample_bits; + ++ /* shared BCLK clock for cross-DAI rate constraints */ ++ struct clk *bclk; ++ unsigned int bclk_ratio; /* BCLK = rate * bclk_ratio (0 = use channels * sample_bits) */ ++ + /* parent platform/codec */ + struct snd_soc_component *component; + +diff --git a/sound/soc/soc-dai.c b/sound/soc/soc-dai.c +index a1e05307067d..7c4cdd636d35 100644 +--- a/sound/soc/soc-dai.c ++++ b/sound/soc/soc-dai.c +@@ -116,10 +116,28 @@ int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) + dai->driver->ops->set_bclk_ratio) + ret = dai->driver->ops->set_bclk_ratio(dai, ratio); + ++ if (!ret) ++ dai->bclk_ratio = ratio; ++ + return soc_dai_ret(dai, ret); + } + EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_ratio); + ++/** ++ * snd_soc_dai_set_bclk_clk - set the BCLK clock for shared clock detection ++ * @dai: DAI ++ * @bclk: BCLK clock pointer (or NULL to clear) ++ * ++ * When multiple DAIs share the same physical BCLK (detected via ++ * clk_is_match()), the ASoC core will automatically constrain their ++ * hw_params so that the resulting BCLK rates are compatible. ++ */ ++void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk) ++{ ++ dai->bclk = bclk; ++} ++EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_clk); ++ + int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd) + { + struct snd_soc_dai *dai; +-- +2.53.0 + diff --git a/SPECS/linux/0168-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch b/SPECS/linux/0168-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch deleted file mode 100644 index a248bd3b81..0000000000 --- a/SPECS/linux/0168-FROMLIST-ASoC-spacemit-add-K3-SoC-support-with-addit.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 43c50acbe91b2659301b094a07091c3d00cd990a Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 15:33:10 +0800 -Subject: [PATCH 168/269] FROMLIST: ASoC: spacemit: add K3 SoC support with - additional clocks - -Add support for the SpacemiT K3 SoC I2S controller, which shares the -same IP as K1 but requires additional clocks: sysclk_div, c_sysclk, -and c_bclk. These clocks only exist on K3 and are not present on K1. -The sysclk_div clock is present on most K3 I2S controllers except I2S1. -The c_sysclk and c_bclk clocks are shared across multiple I2S -controllers on K3. - -Use devm_clk_get_optional_enabled() to acquire these clocks so that -the driver works on both K1 (where they are absent) and K3 without -needing SoC-specific match data. For K3, the sysclk_div rate is set -before sysclk in set_sysclk, and the common clock rates are configured -in hw_params based on the sample rate. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-k3-i2s-v2-2-9cdbf95b7533@linux.spacemit.com -Signed-off-by: Han Gao ---- - sound/soc/spacemit/k1_i2s.c | 36 +++++++++++++++++++++++++++++++++++- - 1 file changed, 35 insertions(+), 1 deletion(-) - -diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c -index 5420ca2aefbd..8871fc15b29c 100644 ---- a/sound/soc/spacemit/k1_i2s.c -+++ b/sound/soc/spacemit/k1_i2s.c -@@ -53,6 +53,9 @@ struct spacemit_i2s_dev { - struct clk *sysclk; - struct clk *bclk; - struct clk *sspa_clk; -+ struct clk *sysclk_div; -+ struct clk *c_sysclk; -+ struct clk *c_bclk; - - struct snd_dmaengine_dai_dma_data capture_dma_data; - struct snd_dmaengine_dai_dma_data playback_dma_data; -@@ -206,6 +209,14 @@ static int spacemit_i2s_hw_params(struct snd_pcm_substream *substream, - params_rate(params) * - data_bits; - -+ ret = clk_set_rate(i2s->c_sysclk, bclk_rate * 2); -+ if (ret) -+ return ret; -+ -+ ret = clk_set_rate(i2s->c_bclk, bclk_rate); -+ if (ret) -+ return ret; -+ - ret = clk_set_rate(i2s->bclk, bclk_rate); - if (ret) - return ret; -@@ -217,10 +228,17 @@ static int spacemit_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, - unsigned int freq, int dir) - { - struct spacemit_i2s_dev *i2s = dev_get_drvdata(cpu_dai->dev); -+ int ret; - - if (freq == 0) - return 0; - -+ if (i2s->sysclk_div) { -+ ret = clk_set_rate(i2s->sysclk_div, freq); -+ if (ret) -+ return ret; -+ } -+ - return clk_set_rate(i2s->sysclk, freq); - } - -@@ -436,6 +454,21 @@ static int spacemit_i2s_probe(struct platform_device *pdev) - return dev_err_probe(i2s->dev, PTR_ERR(i2s->sspa_clk), - "failed to enable sspa clock\n"); - -+ i2s->sysclk_div = devm_clk_get_optional_enabled(i2s->dev, "sysclk_div"); -+ if (IS_ERR(i2s->sysclk_div)) -+ return dev_err_probe(i2s->dev, PTR_ERR(i2s->sysclk_div), -+ "failed to enable sysclk_div clock\n"); -+ -+ i2s->c_sysclk = devm_clk_get_optional_enabled(i2s->dev, "c_sysclk"); -+ if (IS_ERR(i2s->c_sysclk)) -+ return dev_err_probe(i2s->dev, PTR_ERR(i2s->c_sysclk), -+ "failed to enable c_sysclk clock\n"); -+ -+ i2s->c_bclk = devm_clk_get_optional_enabled(i2s->dev, "c_bclk"); -+ if (IS_ERR(i2s->c_bclk)) -+ return dev_err_probe(i2s->dev, PTR_ERR(i2s->c_bclk), -+ "failed to enable c_bclk clock\n"); -+ - i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(i2s->base)) - return dev_err_probe(i2s->dev, PTR_ERR(i2s->base), "failed to map registers\n"); -@@ -462,6 +495,7 @@ static int spacemit_i2s_probe(struct platform_device *pdev) - - static const struct of_device_id spacemit_i2s_of_match[] = { - { .compatible = "spacemit,k1-i2s", }, -+ { .compatible = "spacemit,k3-i2s", }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, spacemit_i2s_of_match); -@@ -476,4 +510,4 @@ static struct platform_driver spacemit_i2s_driver = { - module_platform_driver(spacemit_i2s_driver); - - MODULE_LICENSE("GPL"); --MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1 SoC"); -+MODULE_DESCRIPTION("I2S bus driver for SpacemiT K1/K3 SoC"); --- -2.53.0 - diff --git a/SPECS/linux/0169-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch b/SPECS/linux/0169-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch deleted file mode 100644 index d89234c0e1..0000000000 --- a/SPECS/linux/0169-FROMLIST-ASoC-soc-dai-add-shared-BCLK-clock-for-cros.patch +++ /dev/null @@ -1,96 +0,0 @@ -From e82a58667f6827baa3a0747173b70f2aca5ffdcc Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 18:31:42 +0800 -Subject: [PATCH 169/269] FROMLIST: ASoC: soc-dai: add shared BCLK clock for - cross-DAI rate constraints - -Add a bclk field to struct snd_soc_dai and a helper function -snd_soc_dai_set_bclk_clk() that platform drivers can use to declare -which clock is their BCLK. - -Also cache the bclk_ratio in snd_soc_dai_set_bclk_ratio() so that -the framework can use it later in hw_rule evaluation for TDM -configurations where BCLK = rate * slots * slot_width. - -When multiple DAIs on the same card share the same physical BCLK -(detected via clk_is_match()), the ASoC core can automatically -constrain their hw_params so that the resulting BCLK rates are -compatible. This commit adds the data structure support; the actual -constraint logic follows in the next patch. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-1-ede05a22f732@linux.spacemit.com -Signed-off-by: Han Gao ---- - include/sound/soc-dai.h | 7 +++++++ - sound/soc/soc-dai.c | 18 ++++++++++++++++++ - 2 files changed, 25 insertions(+) - -diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h -index 224396927aef..6d3a0ce02fd8 100644 ---- a/include/sound/soc-dai.h -+++ b/include/sound/soc-dai.h -@@ -17,6 +17,7 @@ - struct snd_pcm_substream; - struct snd_soc_dapm_widget; - struct snd_compr_stream; -+struct clk; - - /* - * DAI hardware audio formats. -@@ -173,6 +174,8 @@ int snd_soc_dai_set_pll(struct snd_soc_dai *dai, - - int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio); - -+void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk); -+ - /* Digital Audio interface formatting */ - int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd); - u64 snd_soc_dai_get_fmt(const struct snd_soc_dai *dai, int priority); -@@ -451,6 +454,10 @@ struct snd_soc_dai { - unsigned int symmetric_channels; - unsigned int symmetric_sample_bits; - -+ /* shared BCLK clock for cross-DAI rate constraints */ -+ struct clk *bclk; -+ unsigned int bclk_ratio; /* BCLK = rate * bclk_ratio (0 = use channels * sample_bits) */ -+ - /* parent platform/codec */ - struct snd_soc_component *component; - -diff --git a/sound/soc/soc-dai.c b/sound/soc/soc-dai.c -index a1e05307067d..7c4cdd636d35 100644 ---- a/sound/soc/soc-dai.c -+++ b/sound/soc/soc-dai.c -@@ -116,10 +116,28 @@ int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) - dai->driver->ops->set_bclk_ratio) - ret = dai->driver->ops->set_bclk_ratio(dai, ratio); - -+ if (!ret) -+ dai->bclk_ratio = ratio; -+ - return soc_dai_ret(dai, ret); - } - EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_ratio); - -+/** -+ * snd_soc_dai_set_bclk_clk - set the BCLK clock for shared clock detection -+ * @dai: DAI -+ * @bclk: BCLK clock pointer (or NULL to clear) -+ * -+ * When multiple DAIs share the same physical BCLK (detected via -+ * clk_is_match()), the ASoC core will automatically constrain their -+ * hw_params so that the resulting BCLK rates are compatible. -+ */ -+void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk) -+{ -+ dai->bclk = bclk; -+} -+EXPORT_SYMBOL_GPL(snd_soc_dai_set_bclk_clk); -+ - int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd) - { - struct snd_soc_dai *dai; --- -2.53.0 - diff --git a/SPECS/linux/0169-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch b/SPECS/linux/0169-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch new file mode 100644 index 0000000000..83e8423579 --- /dev/null +++ b/SPECS/linux/0169-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch @@ -0,0 +1,186 @@ +From 66096bfd05e0316c7838c30bba12410413cbdad3 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 7 May 2026 18:31:43 +0800 +Subject: [RUYI PATCH] FROMLIST: ASoC: soc-pcm: constrain hw_params when DAIs + share the same BCLK + +When multiple CPU DAIs on the same sound card share the same physical +BCLK, add a hw_rule during PCM open that constrains the sample rate so +the resulting BCLK rate stays consistent across all sharing DAIs. + +The hw_rule is registered unconditionally for every DAI that has a bclk +clock pointer set. The actual peer scanning happens inside the rule +callback at hw_refine time: it walks all DAIs on the card, looking for +an active peer that shares the same physical BCLK (via clk_is_match()) +and has already completed hw_params (checked via dai->symmetric_rate +!= 0). This ensures the constraint uses the real BCLK rate established +by the peer's clk_set_rate() in hw_params, not a stale boot-time +default. + +The first DAI to complete hw_params is unconstrained (no active peer +yet); subsequent DAIs are constrained to match. + +The rule supports two modes: +- If the DAI has an explicit bclk_ratio set (e.g. for TDM where + BCLK = rate * slots * slot_width), the rate is constrained to + active_bclk_rate / bclk_ratio. +- Otherwise, the default formula BCLK = rate * channels * sample_bits + is used to derive the valid rate range. + +The constraint is purely additive: DAIs that do not set a bclk clock +pointer are completely unaffected. + +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-2-ede05a22f732@linux.spacemit.com +Signed-off-by: Han Gao +--- + sound/soc/soc-pcm.c | 119 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 119 insertions(+) + +diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c +index 9b12eedb77c3..e75c343b8d4e 100644 +--- a/sound/soc/soc-pcm.c ++++ b/sound/soc/soc-pcm.c +@@ -12,6 +12,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -467,6 +468,117 @@ static int soc_pcm_apply_symmetry(struct snd_pcm_substream *substream, + return 0; + } + ++/* ++ * Shared BCLK constraint: when multiple DAIs share the same physical BCLK, ++ * constrain hw_params so that the BCLK rate (rate * channels * sample_bits, ++ * or rate * slots * slot_width for TDM) remains consistent. ++ */ ++ ++static int soc_pcm_shared_bclk_rule_rate(struct snd_pcm_hw_params *params, ++ struct snd_pcm_hw_rule *rule) ++{ ++ struct snd_soc_dai *dai = rule->private; ++ struct snd_soc_card *card = dai->component->card; ++ struct snd_soc_pcm_runtime *rtd; ++ struct snd_soc_dai *other_dai; ++ unsigned long active_bclk_rate = 0; ++ struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); ++ struct snd_interval constraint = { .empty = 1 }; ++ unsigned int target_rate; ++ int i; ++ ++ /* ++ * Protect the rtd list traversal. No nesting: this callback runs ++ * from snd_pcm_hw_refine() which does not hold card->mutex. ++ */ ++ guard(mutex)(&card->mutex); ++ ++ /* Scan all DAIs on the card for an active peer sharing the same BCLK */ ++ for_each_card_rtds(card, rtd) { ++ for_each_rtd_cpu_dais(rtd, i, other_dai) { ++ if (other_dai == dai) ++ continue; ++ if (!other_dai->bclk) ++ continue; ++ if (!snd_soc_dai_active(other_dai)) ++ continue; ++ /* ++ * Skip peers whose hw_params hasn't run yet. ++ * symmetric_rate is set by soc_pcm_set_dai_params() ++ * after snd_soc_dai_hw_params(), so non-zero means ++ * the DAI's clk_set_rate() has already executed. ++ */ ++ if (!other_dai->symmetric_rate) ++ continue; ++ if (!clk_is_match(dai->bclk, other_dai->bclk)) ++ continue; ++ ++ active_bclk_rate = clk_get_rate(other_dai->bclk); ++ if (active_bclk_rate) ++ goto found; ++ } ++ } ++ ++ return 0; ++ ++found: ++ if (dai->bclk_ratio) { ++ /* ++ * Driver has set an explicit BCLK ratio (e.g. for TDM where ++ * BCLK = rate * slots * slot_width). The only valid rate is ++ * active_bclk_rate / bclk_ratio. ++ */ ++ target_rate = active_bclk_rate / dai->bclk_ratio; ++ ++ constraint.min = target_rate; ++ constraint.max = target_rate; ++ } else { ++ struct snd_interval *channels = hw_param_interval(params, ++ SNDRV_PCM_HW_PARAM_CHANNELS); ++ struct snd_interval *sample_bits = hw_param_interval(params, ++ SNDRV_PCM_HW_PARAM_SAMPLE_BITS); ++ ++ /* ++ * Default: BCLK = rate * channels * sample_bits. ++ * Calculate the range of valid rates given the current ++ * channel and sample_bits intervals. ++ */ ++ if (!channels->min || !sample_bits->min) ++ return 0; ++ ++ constraint.max = active_bclk_rate / ++ ((unsigned long)channels->min * sample_bits->min); ++ ++ if (channels->max && sample_bits->max) ++ constraint.min = active_bclk_rate / ++ ((unsigned long)channels->max * sample_bits->max); ++ else ++ constraint.min = constraint.max; ++ } ++ ++ constraint.integer = 1; ++ constraint.empty = 0; ++ ++ return snd_interval_refine(rate, &constraint); ++} ++ ++static int soc_pcm_apply_shared_bclk(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ if (!dai->bclk) ++ return 0; ++ ++ dev_dbg(dai->dev, ++ "ASoC: registering shared BCLK rate constraint\n"); ++ ++ return snd_pcm_hw_rule_add(substream->runtime, 0, ++ SNDRV_PCM_HW_PARAM_RATE, ++ soc_pcm_shared_bclk_rule_rate, dai, ++ SNDRV_PCM_HW_PARAM_CHANNELS, ++ SNDRV_PCM_HW_PARAM_SAMPLE_BITS, ++ -1); ++} ++ + static int soc_pcm_params_symmetry(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) + { +@@ -903,6 +1015,13 @@ static int __soc_pcm_open(struct snd_soc_pcm_runtime *rtd, + if (ret != 0) + goto err; + } ++ ++ /* Shared BCLK constraint across DAIs on the same card */ ++ for_each_rtd_cpu_dais(rtd, i, dai) { ++ ret = soc_pcm_apply_shared_bclk(substream, dai); ++ if (ret != 0) ++ goto err; ++ } + dynamic: + snd_soc_runtime_activate(rtd, substream->stream); + ret = 0; +-- +2.53.0 + diff --git a/SPECS/linux/0170-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch b/SPECS/linux/0170-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch deleted file mode 100644 index 000f3412f4..0000000000 --- a/SPECS/linux/0170-FROMLIST-ASoC-soc-pcm-constrain-hw_params-when-DAIs-.patch +++ /dev/null @@ -1,186 +0,0 @@ -From e6e96efdd436fa1a59572e2721849344b82dabc2 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 18:31:43 +0800 -Subject: [PATCH 170/269] FROMLIST: ASoC: soc-pcm: constrain hw_params when - DAIs share the same BCLK - -When multiple CPU DAIs on the same sound card share the same physical -BCLK, add a hw_rule during PCM open that constrains the sample rate so -the resulting BCLK rate stays consistent across all sharing DAIs. - -The hw_rule is registered unconditionally for every DAI that has a bclk -clock pointer set. The actual peer scanning happens inside the rule -callback at hw_refine time: it walks all DAIs on the card, looking for -an active peer that shares the same physical BCLK (via clk_is_match()) -and has already completed hw_params (checked via dai->symmetric_rate -!= 0). This ensures the constraint uses the real BCLK rate established -by the peer's clk_set_rate() in hw_params, not a stale boot-time -default. - -The first DAI to complete hw_params is unconstrained (no active peer -yet); subsequent DAIs are constrained to match. - -The rule supports two modes: -- If the DAI has an explicit bclk_ratio set (e.g. for TDM where - BCLK = rate * slots * slot_width), the rate is constrained to - active_bclk_rate / bclk_ratio. -- Otherwise, the default formula BCLK = rate * channels * sample_bits - is used to derive the valid rate range. - -The constraint is purely additive: DAIs that do not set a bclk clock -pointer are completely unaffected. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-2-ede05a22f732@linux.spacemit.com -Signed-off-by: Han Gao ---- - sound/soc/soc-pcm.c | 119 ++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 119 insertions(+) - -diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c -index 9b12eedb77c3..e75c343b8d4e 100644 ---- a/sound/soc/soc-pcm.c -+++ b/sound/soc/soc-pcm.c -@@ -12,6 +12,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -467,6 +468,117 @@ static int soc_pcm_apply_symmetry(struct snd_pcm_substream *substream, - return 0; - } - -+/* -+ * Shared BCLK constraint: when multiple DAIs share the same physical BCLK, -+ * constrain hw_params so that the BCLK rate (rate * channels * sample_bits, -+ * or rate * slots * slot_width for TDM) remains consistent. -+ */ -+ -+static int soc_pcm_shared_bclk_rule_rate(struct snd_pcm_hw_params *params, -+ struct snd_pcm_hw_rule *rule) -+{ -+ struct snd_soc_dai *dai = rule->private; -+ struct snd_soc_card *card = dai->component->card; -+ struct snd_soc_pcm_runtime *rtd; -+ struct snd_soc_dai *other_dai; -+ unsigned long active_bclk_rate = 0; -+ struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); -+ struct snd_interval constraint = { .empty = 1 }; -+ unsigned int target_rate; -+ int i; -+ -+ /* -+ * Protect the rtd list traversal. No nesting: this callback runs -+ * from snd_pcm_hw_refine() which does not hold card->mutex. -+ */ -+ guard(mutex)(&card->mutex); -+ -+ /* Scan all DAIs on the card for an active peer sharing the same BCLK */ -+ for_each_card_rtds(card, rtd) { -+ for_each_rtd_cpu_dais(rtd, i, other_dai) { -+ if (other_dai == dai) -+ continue; -+ if (!other_dai->bclk) -+ continue; -+ if (!snd_soc_dai_active(other_dai)) -+ continue; -+ /* -+ * Skip peers whose hw_params hasn't run yet. -+ * symmetric_rate is set by soc_pcm_set_dai_params() -+ * after snd_soc_dai_hw_params(), so non-zero means -+ * the DAI's clk_set_rate() has already executed. -+ */ -+ if (!other_dai->symmetric_rate) -+ continue; -+ if (!clk_is_match(dai->bclk, other_dai->bclk)) -+ continue; -+ -+ active_bclk_rate = clk_get_rate(other_dai->bclk); -+ if (active_bclk_rate) -+ goto found; -+ } -+ } -+ -+ return 0; -+ -+found: -+ if (dai->bclk_ratio) { -+ /* -+ * Driver has set an explicit BCLK ratio (e.g. for TDM where -+ * BCLK = rate * slots * slot_width). The only valid rate is -+ * active_bclk_rate / bclk_ratio. -+ */ -+ target_rate = active_bclk_rate / dai->bclk_ratio; -+ -+ constraint.min = target_rate; -+ constraint.max = target_rate; -+ } else { -+ struct snd_interval *channels = hw_param_interval(params, -+ SNDRV_PCM_HW_PARAM_CHANNELS); -+ struct snd_interval *sample_bits = hw_param_interval(params, -+ SNDRV_PCM_HW_PARAM_SAMPLE_BITS); -+ -+ /* -+ * Default: BCLK = rate * channels * sample_bits. -+ * Calculate the range of valid rates given the current -+ * channel and sample_bits intervals. -+ */ -+ if (!channels->min || !sample_bits->min) -+ return 0; -+ -+ constraint.max = active_bclk_rate / -+ ((unsigned long)channels->min * sample_bits->min); -+ -+ if (channels->max && sample_bits->max) -+ constraint.min = active_bclk_rate / -+ ((unsigned long)channels->max * sample_bits->max); -+ else -+ constraint.min = constraint.max; -+ } -+ -+ constraint.integer = 1; -+ constraint.empty = 0; -+ -+ return snd_interval_refine(rate, &constraint); -+} -+ -+static int soc_pcm_apply_shared_bclk(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ if (!dai->bclk) -+ return 0; -+ -+ dev_dbg(dai->dev, -+ "ASoC: registering shared BCLK rate constraint\n"); -+ -+ return snd_pcm_hw_rule_add(substream->runtime, 0, -+ SNDRV_PCM_HW_PARAM_RATE, -+ soc_pcm_shared_bclk_rule_rate, dai, -+ SNDRV_PCM_HW_PARAM_CHANNELS, -+ SNDRV_PCM_HW_PARAM_SAMPLE_BITS, -+ -1); -+} -+ - static int soc_pcm_params_symmetry(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) - { -@@ -903,6 +1015,13 @@ static int __soc_pcm_open(struct snd_soc_pcm_runtime *rtd, - if (ret != 0) - goto err; - } -+ -+ /* Shared BCLK constraint across DAIs on the same card */ -+ for_each_rtd_cpu_dais(rtd, i, dai) { -+ ret = soc_pcm_apply_shared_bclk(substream, dai); -+ if (ret != 0) -+ goto err; -+ } - dynamic: - snd_soc_runtime_activate(rtd, substream->stream); - ret = 0; --- -2.53.0 - diff --git a/SPECS/linux/0170-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch b/SPECS/linux/0170-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch new file mode 100644 index 0000000000..8d17b9576d --- /dev/null +++ b/SPECS/linux/0170-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch @@ -0,0 +1,37 @@ +From 23652a508a6fbb1f987b179bb7d2426487ef2c05 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 7 May 2026 18:31:44 +0800 +Subject: [RUYI PATCH] FROMLIST: ASoC: spacemit: declare shared BCLK for + cross-DAI rate constraint + +On SpacemiT K3, multiple I2S controllers share the same physical BCLK +(c_bclk). Declare this clock via snd_soc_dai_set_bclk_clk() so the +ASoC core can automatically constrain hw_params when one controller is +already streaming. + +For K1, c_bclk is NULL (obtained via devm_clk_get_optional_enabled), +so this call is a no-op and behavior is unchanged. + +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-3-ede05a22f732@linux.spacemit.com +Signed-off-by: Han Gao +--- + sound/soc/spacemit/k1_i2s.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c +index 8871fc15b29c..d35b57566829 100644 +--- a/sound/soc/spacemit/k1_i2s.c ++++ b/sound/soc/spacemit/k1_i2s.c +@@ -323,6 +323,8 @@ static int spacemit_i2s_dai_probe(struct snd_soc_dai *dai) + + spacemit_i2s_init(i2s); + ++ snd_soc_dai_set_bclk_clk(dai, i2s->c_bclk); ++ + return 0; + } + +-- +2.53.0 + diff --git a/SPECS/linux/0171-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch b/SPECS/linux/0171-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch deleted file mode 100644 index 941b463690..0000000000 --- a/SPECS/linux/0171-FROMLIST-ASoC-spacemit-declare-shared-BCLK-for-cross.patch +++ /dev/null @@ -1,37 +0,0 @@ -From b7ed2c30e3a5e372ad354bd57dbc0b83a25dba54 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Thu, 7 May 2026 18:31:44 +0800 -Subject: [PATCH 171/269] FROMLIST: ASoC: spacemit: declare shared BCLK for - cross-DAI rate constraint - -On SpacemiT K3, multiple I2S controllers share the same physical BCLK -(c_bclk). Declare this clock via snd_soc_dai_set_bclk_clk() so the -ASoC core can automatically constrain hw_params when one controller is -already streaming. - -For K1, c_bclk is NULL (obtained via devm_clk_get_optional_enabled), -so this call is a no-op and behavior is unchanged. - -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260507-i2s-same-blk-v2-3-ede05a22f732@linux.spacemit.com -Signed-off-by: Han Gao ---- - sound/soc/spacemit/k1_i2s.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/sound/soc/spacemit/k1_i2s.c b/sound/soc/spacemit/k1_i2s.c -index 8871fc15b29c..d35b57566829 100644 ---- a/sound/soc/spacemit/k1_i2s.c -+++ b/sound/soc/spacemit/k1_i2s.c -@@ -323,6 +323,8 @@ static int spacemit_i2s_dai_probe(struct snd_soc_dai *dai) - - spacemit_i2s_init(i2s); - -+ snd_soc_dai_set_bclk_clk(dai, i2s->c_bclk); -+ - return 0; - } - --- -2.53.0 - diff --git a/SPECS/linux/0171-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch b/SPECS/linux/0171-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch new file mode 100644 index 0000000000..e4230da117 --- /dev/null +++ b/SPECS/linux/0171-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch @@ -0,0 +1,41 @@ +From d68e168e3794a58f2b7152664616c8a5cdd81dc9 Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 5 May 2026 09:53:34 -0400 +Subject: [RUYI PATCH] FROMLIST: spi: spacemit: add u64 cast to NSEC_PER_SEC to + avoid 32-bit overflow + +NSEC_PER_SEC expands to the long constant 1000000000L, so NSEC_PER_SEC * +BITS_PER_BYTE (8 * 10^9) overflows on 32-bit-long architectures +before the result reaches the u64 nsec_per_word. + +Promote the multiplication to u64 by casting the first operand, which is +NSEC_PER_SEC. + +Fixes: efcd8b9d1111 ("spi: spacemit: introduce SpacemiT K1 SPI controller driver") +Suggested-by: Alex Elder +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202605050437.RS6mmV2b-lkp@intel.com/ +Closes: https://lore.kernel.org/oe-kbuild-all/202605050317.Tf9j487w-lkp@intel.com/ +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260505-spi-spacemit-k1-fix-overflow-v1-1-77564c2e4e86@riscstar.com +Signed-off-by: Han Gao +--- + drivers/spi/spi-spacemit-k1.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/spi/spi-spacemit-k1.c b/drivers/spi/spi-spacemit-k1.c +index 99db429db0b2..215fe66d27b4 100644 +--- a/drivers/spi/spi-spacemit-k1.c ++++ b/drivers/spi/spi-spacemit-k1.c +@@ -390,7 +390,7 @@ static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, + * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; + * We do the divide last for better accuracy. + */ +- nsec_per_word = NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; ++ nsec_per_word = (u64)NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; + nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); + + /* +-- +2.53.0 + diff --git a/SPECS/linux/0172-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch b/SPECS/linux/0172-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch new file mode 100644 index 0000000000..c33a14fce2 --- /dev/null +++ b/SPECS/linux/0172-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch @@ -0,0 +1,65 @@ +From 6e1d2e49773e175bd613d1f1e0440e76432144f0 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:16:59 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: clock: thead: add TH1520 MISC + subsys clock controller + +TH1520 has a subsystem clock controller called MISC_SUBSYS in its +manual, mainly controlling clocks for USB and MMC/SD in non-TEE +environment. + +Add device tree binding for it. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-2-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../devicetree/bindings/clock/thead,th1520-clk-ap.yaml | 5 +++-- + include/dt-bindings/clock/thead,th1520-clk-ap.h | 10 ++++++++++ + 2 files changed, 13 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +index 9d058c00ab3d..d46d13597466 100644 +--- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml ++++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +@@ -23,6 +23,7 @@ properties: + compatible: + enum: + - thead,th1520-clk-ap ++ - thead,th1520-clk-misc + - thead,th1520-clk-vo + + reg: +@@ -32,8 +33,8 @@ properties: + items: + - description: | + One input clock: +- - For "thead,th1520-clk-ap": the clock input must be the 24 MHz +- main oscillator. ++ - For "thead,th1520-clk-ap" and "thead,th1520-clk-misc": the clock ++ input must be the 24 MHz main oscillator. + - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL, + which is configured by the AP clock controller. According to the + TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL +diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h +index 68b35cc61204..642c2a69a579 100644 +--- a/include/dt-bindings/clock/thead,th1520-clk-ap.h ++++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h +@@ -128,4 +128,14 @@ + #define CLK_MIPIDSI1_PIXCLK 29 + #define CLK_HDMI_PIXCLK 30 + ++/* MISC clocks */ ++#define CLK_MISCSYS_ACLK 0 ++#define CLK_USB 1 ++#define CLK_USB_CTL_REF 2 ++#define CLK_USB_PHY_REF 3 ++#define CLK_USB_SUSPEND 4 ++#define CLK_EMMC 5 ++#define CLK_SDIO0 6 ++#define CLK_SDIO1 7 ++ + #endif +-- +2.53.0 + diff --git a/SPECS/linux/0172-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch b/SPECS/linux/0172-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch deleted file mode 100644 index 7a08281e0b..0000000000 --- a/SPECS/linux/0172-FROMLIST-spi-spacemit-add-u64-cast-to-NSEC_PER_SEC-t.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 21ce5b152db764c417d765d7cee20c8c2d1b5361 Mon Sep 17 00:00:00 2001 -From: Guodong Xu -Date: Tue, 5 May 2026 09:53:34 -0400 -Subject: [PATCH 172/269] FROMLIST: spi: spacemit: add u64 cast to NSEC_PER_SEC - to avoid 32-bit overflow - -NSEC_PER_SEC expands to the long constant 1000000000L, so NSEC_PER_SEC * -BITS_PER_BYTE (8 * 10^9) overflows on 32-bit-long architectures -before the result reaches the u64 nsec_per_word. - -Promote the multiplication to u64 by casting the first operand, which is -NSEC_PER_SEC. - -Fixes: efcd8b9d1111 ("spi: spacemit: introduce SpacemiT K1 SPI controller driver") -Suggested-by: Alex Elder -Reported-by: kernel test robot -Closes: https://lore.kernel.org/oe-kbuild-all/202605050437.RS6mmV2b-lkp@intel.com/ -Closes: https://lore.kernel.org/oe-kbuild-all/202605050317.Tf9j487w-lkp@intel.com/ -Signed-off-by: Guodong Xu -Link: https://lore.kernel.org/r/20260505-spi-spacemit-k1-fix-overflow-v1-1-77564c2e4e86@riscstar.com -Signed-off-by: Han Gao ---- - drivers/spi/spi-spacemit-k1.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/spi/spi-spacemit-k1.c b/drivers/spi/spi-spacemit-k1.c -index 99db429db0b2..215fe66d27b4 100644 ---- a/drivers/spi/spi-spacemit-k1.c -+++ b/drivers/spi/spi-spacemit-k1.c -@@ -390,7 +390,7 @@ static int k1_spi_set_speed(struct k1_spi_driver_data *drv_data, - * ticks_per_word = BITS_PER_BYTE * drv_data->bytes; - * We do the divide last for better accuracy. - */ -- nsec_per_word = NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; -+ nsec_per_word = (u64)NSEC_PER_SEC * BITS_PER_BYTE * drv_data->bytes; - nsec_per_word = DIV_ROUND_UP_ULL(nsec_per_word, drv_data->rate); - - /* --- -2.53.0 - diff --git a/SPECS/linux/0173-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch b/SPECS/linux/0173-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch new file mode 100644 index 0000000000..8f3d31999b --- /dev/null +++ b/SPECS/linux/0173-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch @@ -0,0 +1,124 @@ +From 5e228b661c56cbb53366dd07a949a977bbe6c2a2 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:00 +0800 +Subject: [RUYI PATCH] FROMLIST: clk: thead: th1520-ap: add support for MISC + subsys clocks + +The TH1520 SoC contains a MISC_SUBSYS clock controller, which allows +controlling of USB related clocks and MMC/SD controller AHB bus clocks. + +Add support for this clock controller, in order to enable USB support. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-3-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/clk/thead/clk-th1520-ap.c | 64 +++++++++++++++++++++++++++++++ + 1 file changed, 64 insertions(+) + +diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c +index 3a6847f1c950..24f785f0b329 100644 +--- a/drivers/clk/thead/clk-th1520-ap.c ++++ b/drivers/clk/thead/clk-th1520-ap.c +@@ -1266,6 +1266,41 @@ static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk", + static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk_pd, + 0x4, 0, 0); + ++static struct clk_fixed_factor usb_suspend_div_clk = { ++ .div = 24, ++ .mult = 1, ++ .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-suspend-div", ++ osc_24m_clk, ++ &clk_fixed_factor_ops, ++ 0), ++}; ++ ++static const struct clk_parent_data usb_suspend_parents[] = { ++ { .hw = &usb_suspend_div_clk.hw }, ++}; ++ ++static CCU_GATE(CLK_MISCSYS_ACLK, miscsys_aclk, "miscsys-aclk", axi_aclk_pd, ++ 0x0, 0, CLK_IS_CRITICAL); ++ ++static const struct clk_parent_data miscsys_aclk_pd[] = { ++ { .hw = &miscsys_aclk.gate.hw }, ++}; ++ ++static CCU_GATE(CLK_USB, usb_clk, "usb", miscsys_aclk_pd, 0x4, 0, ++ CLK_IS_CRITICAL); ++static CCU_GATE(CLK_USB_CTL_REF, usb_ctl_ref_clk, "usb-ctl-ref", osc_24m_clk, ++ 0x4, 1, 0); ++static CCU_GATE(CLK_USB_PHY_REF, usb_phy_ref_clk, "usb-phy-ref", osc_24m_clk, ++ 0x4, 2, 0); ++static CCU_GATE(CLK_USB_SUSPEND, usb_suspend_clk, "usb-suspend", ++ usb_suspend_parents, 0x4, 3, 0); ++static CCU_GATE(CLK_EMMC, emmc_clk, "emmc", perisys_ahb_hclk_pd, 0x8, 0, ++ 0); ++static CCU_GATE(CLK_SDIO0, sdio0_clk, "sdio0", perisys_ahb_hclk_pd, 0xc, 0, ++ 0); ++static CCU_GATE(CLK_SDIO1, sdio1_clk, "sdio1", perisys_ahb_hclk_pd, 0x10, 0, ++ 0); ++ + static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m", + &gmac_pll_clk.common.hw, 10, 1, 0); + +@@ -1410,6 +1445,17 @@ static struct ccu_gate *th1520_vo_gate_clks[] = { + &hdmi_pixclk + }; + ++static struct ccu_gate *th1520_misc_gate_clks[] = { ++ &miscsys_aclk, ++ &usb_clk, ++ &usb_ctl_ref_clk, ++ &usb_phy_ref_clk, ++ &usb_suspend_clk, ++ &emmc_clk, ++ &sdio0_clk, ++ &sdio1_clk ++}; ++ + static const struct regmap_config th1520_clk_regmap_config = { + .reg_bits = 32, + .val_bits = 32, +@@ -1451,6 +1497,14 @@ static const struct th1520_plat_data th1520_vo_platdata = { + .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks), + }; + ++static const struct th1520_plat_data th1520_misc_platdata = { ++ .th1520_gate_clks = th1520_misc_gate_clks, ++ ++ .nr_clks = CLK_SDIO1 + 1, ++ ++ .nr_gate_clks = ARRAY_SIZE(th1520_misc_gate_clks), ++}; ++ + /* + * Maintain clock rate of c910_bus_clk below TH1520_C910_BUS_MAX_RATE (750MHz) + * when its parent, c910_clk, changes the rate. +@@ -1609,6 +1663,12 @@ static int th1520_clk_probe(struct platform_device *pdev) + return ret; + } + ++ if (plat_data == &th1520_ap_platdata) { ++ ret = devm_clk_hw_register(dev, &usb_suspend_div_clk.hw); ++ if (ret) ++ return ret; ++ } ++ + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); + if (ret) + return ret; +@@ -1625,6 +1685,10 @@ static const struct of_device_id th1520_clk_match[] = { + .compatible = "thead,th1520-clk-vo", + .data = &th1520_vo_platdata, + }, ++ { ++ .compatible = "thead,th1520-clk-misc", ++ .data = &th1520_misc_platdata, ++ }, + { /* sentinel */ }, + }; + MODULE_DEVICE_TABLE(of, th1520_clk_match); +-- +2.53.0 + diff --git a/SPECS/linux/0173-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch b/SPECS/linux/0173-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch deleted file mode 100644 index 297de179be..0000000000 --- a/SPECS/linux/0173-FROMLIST-dt-bindings-clock-thead-add-TH1520-MISC-sub.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 9f5261ef8101423c2511ae1382c0eabd1c404d35 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:16:59 +0800 -Subject: [PATCH 173/269] FROMLIST: dt-bindings: clock: thead: add TH1520 MISC - subsys clock controller - -TH1520 has a subsystem clock controller called MISC_SUBSYS in its -manual, mainly controlling clocks for USB and MMC/SD in non-TEE -environment. - -Add device tree binding for it. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-2-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../devicetree/bindings/clock/thead,th1520-clk-ap.yaml | 5 +++-- - include/dt-bindings/clock/thead,th1520-clk-ap.h | 10 ++++++++++ - 2 files changed, 13 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml -index 9d058c00ab3d..d46d13597466 100644 ---- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml -+++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml -@@ -23,6 +23,7 @@ properties: - compatible: - enum: - - thead,th1520-clk-ap -+ - thead,th1520-clk-misc - - thead,th1520-clk-vo - - reg: -@@ -32,8 +33,8 @@ properties: - items: - - description: | - One input clock: -- - For "thead,th1520-clk-ap": the clock input must be the 24 MHz -- main oscillator. -+ - For "thead,th1520-clk-ap" and "thead,th1520-clk-misc": the clock -+ input must be the 24 MHz main oscillator. - - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL, - which is configured by the AP clock controller. According to the - TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL -diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h -index 68b35cc61204..642c2a69a579 100644 ---- a/include/dt-bindings/clock/thead,th1520-clk-ap.h -+++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h -@@ -128,4 +128,14 @@ - #define CLK_MIPIDSI1_PIXCLK 29 - #define CLK_HDMI_PIXCLK 30 - -+/* MISC clocks */ -+#define CLK_MISCSYS_ACLK 0 -+#define CLK_USB 1 -+#define CLK_USB_CTL_REF 2 -+#define CLK_USB_PHY_REF 3 -+#define CLK_USB_SUSPEND 4 -+#define CLK_EMMC 5 -+#define CLK_SDIO0 6 -+#define CLK_SDIO1 7 -+ - #endif --- -2.53.0 - diff --git a/SPECS/linux/0174-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch b/SPECS/linux/0174-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch deleted file mode 100644 index 0ad2aa214c..0000000000 --- a/SPECS/linux/0174-FROMLIST-clk-thead-th1520-ap-add-support-for-MISC-su.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 42a7744b7b5a08ac30d50468811909e076f5a212 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:00 +0800 -Subject: [PATCH 174/269] FROMLIST: clk: thead: th1520-ap: add support for MISC - subsys clocks - -The TH1520 SoC contains a MISC_SUBSYS clock controller, which allows -controlling of USB related clocks and MMC/SD controller AHB bus clocks. - -Add support for this clock controller, in order to enable USB support. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-3-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/clk/thead/clk-th1520-ap.c | 64 +++++++++++++++++++++++++++++++ - 1 file changed, 64 insertions(+) - -diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c -index 3a6847f1c950..24f785f0b329 100644 ---- a/drivers/clk/thead/clk-th1520-ap.c -+++ b/drivers/clk/thead/clk-th1520-ap.c -@@ -1266,6 +1266,41 @@ static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk", - static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk_pd, - 0x4, 0, 0); - -+static struct clk_fixed_factor usb_suspend_div_clk = { -+ .div = 24, -+ .mult = 1, -+ .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-suspend-div", -+ osc_24m_clk, -+ &clk_fixed_factor_ops, -+ 0), -+}; -+ -+static const struct clk_parent_data usb_suspend_parents[] = { -+ { .hw = &usb_suspend_div_clk.hw }, -+}; -+ -+static CCU_GATE(CLK_MISCSYS_ACLK, miscsys_aclk, "miscsys-aclk", axi_aclk_pd, -+ 0x0, 0, CLK_IS_CRITICAL); -+ -+static const struct clk_parent_data miscsys_aclk_pd[] = { -+ { .hw = &miscsys_aclk.gate.hw }, -+}; -+ -+static CCU_GATE(CLK_USB, usb_clk, "usb", miscsys_aclk_pd, 0x4, 0, -+ CLK_IS_CRITICAL); -+static CCU_GATE(CLK_USB_CTL_REF, usb_ctl_ref_clk, "usb-ctl-ref", osc_24m_clk, -+ 0x4, 1, 0); -+static CCU_GATE(CLK_USB_PHY_REF, usb_phy_ref_clk, "usb-phy-ref", osc_24m_clk, -+ 0x4, 2, 0); -+static CCU_GATE(CLK_USB_SUSPEND, usb_suspend_clk, "usb-suspend", -+ usb_suspend_parents, 0x4, 3, 0); -+static CCU_GATE(CLK_EMMC, emmc_clk, "emmc", perisys_ahb_hclk_pd, 0x8, 0, -+ 0); -+static CCU_GATE(CLK_SDIO0, sdio0_clk, "sdio0", perisys_ahb_hclk_pd, 0xc, 0, -+ 0); -+static CCU_GATE(CLK_SDIO1, sdio1_clk, "sdio1", perisys_ahb_hclk_pd, 0x10, 0, -+ 0); -+ - static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m", - &gmac_pll_clk.common.hw, 10, 1, 0); - -@@ -1410,6 +1445,17 @@ static struct ccu_gate *th1520_vo_gate_clks[] = { - &hdmi_pixclk - }; - -+static struct ccu_gate *th1520_misc_gate_clks[] = { -+ &miscsys_aclk, -+ &usb_clk, -+ &usb_ctl_ref_clk, -+ &usb_phy_ref_clk, -+ &usb_suspend_clk, -+ &emmc_clk, -+ &sdio0_clk, -+ &sdio1_clk -+}; -+ - static const struct regmap_config th1520_clk_regmap_config = { - .reg_bits = 32, - .val_bits = 32, -@@ -1451,6 +1497,14 @@ static const struct th1520_plat_data th1520_vo_platdata = { - .nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks), - }; - -+static const struct th1520_plat_data th1520_misc_platdata = { -+ .th1520_gate_clks = th1520_misc_gate_clks, -+ -+ .nr_clks = CLK_SDIO1 + 1, -+ -+ .nr_gate_clks = ARRAY_SIZE(th1520_misc_gate_clks), -+}; -+ - /* - * Maintain clock rate of c910_bus_clk below TH1520_C910_BUS_MAX_RATE (750MHz) - * when its parent, c910_clk, changes the rate. -@@ -1609,6 +1663,12 @@ static int th1520_clk_probe(struct platform_device *pdev) - return ret; - } - -+ if (plat_data == &th1520_ap_platdata) { -+ ret = devm_clk_hw_register(dev, &usb_suspend_div_clk.hw); -+ if (ret) -+ return ret; -+ } -+ - ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv); - if (ret) - return ret; -@@ -1625,6 +1685,10 @@ static const struct of_device_id th1520_clk_match[] = { - .compatible = "thead,th1520-clk-vo", - .data = &th1520_vo_platdata, - }, -+ { -+ .compatible = "thead,th1520-clk-misc", -+ .data = &th1520_misc_platdata, -+ }, - { /* sentinel */ }, - }; - MODULE_DEVICE_TABLE(of, th1520_clk_match); --- -2.53.0 - diff --git a/SPECS/linux/0174-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch b/SPECS/linux/0174-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch new file mode 100644 index 0000000000..8fdc644c33 --- /dev/null +++ b/SPECS/linux/0174-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch @@ -0,0 +1,74 @@ +From 778f859c641c76dc18d95224b4a57b9bbdbcc08b Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:01 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device tree node for + MISC clock controller + +The MISC_SUBSYS clock controller on TH1520 SoC is a clock controller +mainly controlling USB-related clocks (which isn't utilized yet) and +MMC/SD controllers' AHB bus clocks. + +Add the device tree node for it along with the missing bus clock +references for MMC/SD controllers. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-4-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 19 +++++++++++++------ + 1 file changed, 13 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index 2910249e1f0c..4d1e71227339 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -401,8 +401,8 @@ emmc: mmc@ffe7080000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7080000 0x0 0x10000>; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk CLK_EMMC_SDIO>; +- clock-names = "core"; ++ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_EMMC>; ++ clock-names = "core", "bus"; + status = "disabled"; + }; + +@@ -410,8 +410,8 @@ sdio0: mmc@ffe7090000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7090000 0x0 0x10000>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk CLK_EMMC_SDIO>; +- clock-names = "core"; ++ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO0>; ++ clock-names = "core", "bus"; + status = "disabled"; + }; + +@@ -419,8 +419,8 @@ sdio1: mmc@ffe70a0000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe70a0000 0x0 0x10000>; + interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&clk CLK_EMMC_SDIO>; +- clock-names = "core"; ++ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO1>; ++ clock-names = "core", "bus"; + status = "disabled"; + }; + +@@ -568,6 +568,13 @@ rst_misc: reset-controller@ffec02c000 { + #reset-cells = <1>; + }; + ++ clk_misc: clock-controller@ffec02c100 { ++ compatible = "thead,th1520-clk-misc"; ++ reg = <0xff 0xec02c100 0x0 0x100>; ++ clocks = <&osc>; ++ #clock-cells = <1>; ++ }; ++ + rst_vp: reset-controller@ffecc30000 { + compatible = "thead,th1520-reset-vp"; + reg = <0xff 0xecc30000 0x0 0x14>; +-- +2.53.0 + diff --git a/SPECS/linux/0175-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch b/SPECS/linux/0175-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch new file mode 100644 index 0000000000..b5ec17729f --- /dev/null +++ b/SPECS/linux/0175-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch @@ -0,0 +1,102 @@ +From 8620cc18faf9431ecca7af32d3d19d04aeb36358 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:02 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: phy: add binding for T-Head + TH1520 USB PHY + +The TH1520 SoC features a Synopsys USB 3.0 FemtoPHY with some custom +glue logic configuring PHY parameters. + +Add a binding for it. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-5-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../bindings/phy/thead,th1520-usb-phy.yaml | 74 +++++++++++++++++++ + 1 file changed, 74 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml +new file mode 100644 +index 000000000000..37f5cfb95bad +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml +@@ -0,0 +1,74 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/thead,th1520-usb-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: T-Head TH1520 USB PHY ++ ++description: | ++ The T-HEAD TH1520 USB PHY is a Synopsys USB 3.0 FemtoPHY glued with some ++ custom logic to configure PHY parameters. ++ ++maintainers: ++ - Icenowy Zheng ++ - Wei Fu ++ - Drew Fustini ++ ++properties: ++ compatible: ++ const: thead,th1520-usb-phy ++ ++ reg: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 0 ++ ++ clocks: ++ items: ++ - description: PHY bus clock ++ - description: PHY reference clock ++ ++ clock-names: ++ items: ++ - const: bus ++ - const: ref ++ ++ resets: ++ items: ++ - description: PHY bus reset ++ - description: PHY reset ++ ++ reset-names: ++ items: ++ - const: bus ++ - const: phy ++ ++ avdd33-usb3-supply: ++ description: | ++ 3.3V power supply for the PHY, named AVDD33_USB3 in the SoC pin list. ++ ++required: ++ - compatible ++ - "#phy-cells" ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - avdd33-usb3-supply ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@ec030000 { ++ compatible = "thead,th1520-usb-phy"; ++ reg = <0xec030000 0x10000>; ++ #phy-cells = <0>; ++ clocks = <&clk_misc 1>, <&clk_misc 3>; ++ clock-names = "bus", "ref"; ++ resets = <&rst_misc 6>, <&rst_misc 7>; ++ reset-names = "bus", "phy"; ++ avdd33-usb3-supply = <&avdd33_usb3>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux/0175-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch b/SPECS/linux/0175-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch deleted file mode 100644 index 740d8b2462..0000000000 --- a/SPECS/linux/0175-FROMLIST-riscv-dts-thead-add-device-tree-node-for-MI.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 6d8edd783e0a7d8e0fffc9f59afdf9aca52cef62 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:01 +0800 -Subject: [PATCH 175/269] FROMLIST: riscv: dts: thead: add device tree node for - MISC clock controller - -The MISC_SUBSYS clock controller on TH1520 SoC is a clock controller -mainly controlling USB-related clocks (which isn't utilized yet) and -MMC/SD controllers' AHB bus clocks. - -Add the device tree node for it along with the missing bus clock -references for MMC/SD controllers. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-4-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 19 +++++++++++++------ - 1 file changed, 13 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index 2910249e1f0c..4d1e71227339 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -401,8 +401,8 @@ emmc: mmc@ffe7080000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe7080000 0x0 0x10000>; - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clk CLK_EMMC_SDIO>; -- clock-names = "core"; -+ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_EMMC>; -+ clock-names = "core", "bus"; - status = "disabled"; - }; - -@@ -410,8 +410,8 @@ sdio0: mmc@ffe7090000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe7090000 0x0 0x10000>; - interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clk CLK_EMMC_SDIO>; -- clock-names = "core"; -+ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO0>; -+ clock-names = "core", "bus"; - status = "disabled"; - }; - -@@ -419,8 +419,8 @@ sdio1: mmc@ffe70a0000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe70a0000 0x0 0x10000>; - interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clk CLK_EMMC_SDIO>; -- clock-names = "core"; -+ clocks = <&clk CLK_EMMC_SDIO>, <&clk_misc CLK_SDIO1>; -+ clock-names = "core", "bus"; - status = "disabled"; - }; - -@@ -568,6 +568,13 @@ rst_misc: reset-controller@ffec02c000 { - #reset-cells = <1>; - }; - -+ clk_misc: clock-controller@ffec02c100 { -+ compatible = "thead,th1520-clk-misc"; -+ reg = <0xff 0xec02c100 0x0 0x100>; -+ clocks = <&osc>; -+ #clock-cells = <1>; -+ }; -+ - rst_vp: reset-controller@ffecc30000 { - compatible = "thead,th1520-reset-vp"; - reg = <0xff 0xecc30000 0x0 0x14>; --- -2.53.0 - diff --git a/SPECS/linux/0176-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch b/SPECS/linux/0176-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch deleted file mode 100644 index 8baf862c7f..0000000000 --- a/SPECS/linux/0176-FROMLIST-dt-bindings-phy-add-binding-for-T-Head-TH15.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 6fcf319c3fa563b388bd5ed30e8d105d09ad9fcf Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:02 +0800 -Subject: [PATCH 176/269] FROMLIST: dt-bindings: phy: add binding for T-Head - TH1520 USB PHY - -The TH1520 SoC features a Synopsys USB 3.0 FemtoPHY with some custom -glue logic configuring PHY parameters. - -Add a binding for it. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-5-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../bindings/phy/thead,th1520-usb-phy.yaml | 74 +++++++++++++++++++ - 1 file changed, 74 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml -new file mode 100644 -index 000000000000..37f5cfb95bad ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/thead,th1520-usb-phy.yaml -@@ -0,0 +1,74 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/thead,th1520-usb-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: T-Head TH1520 USB PHY -+ -+description: | -+ The T-HEAD TH1520 USB PHY is a Synopsys USB 3.0 FemtoPHY glued with some -+ custom logic to configure PHY parameters. -+ -+maintainers: -+ - Icenowy Zheng -+ - Wei Fu -+ - Drew Fustini -+ -+properties: -+ compatible: -+ const: thead,th1520-usb-phy -+ -+ reg: -+ maxItems: 1 -+ -+ "#phy-cells": -+ const: 0 -+ -+ clocks: -+ items: -+ - description: PHY bus clock -+ - description: PHY reference clock -+ -+ clock-names: -+ items: -+ - const: bus -+ - const: ref -+ -+ resets: -+ items: -+ - description: PHY bus reset -+ - description: PHY reset -+ -+ reset-names: -+ items: -+ - const: bus -+ - const: phy -+ -+ avdd33-usb3-supply: -+ description: | -+ 3.3V power supply for the PHY, named AVDD33_USB3 in the SoC pin list. -+ -+required: -+ - compatible -+ - "#phy-cells" -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ - avdd33-usb3-supply -+ -+additionalProperties: false -+ -+examples: -+ - | -+ phy@ec030000 { -+ compatible = "thead,th1520-usb-phy"; -+ reg = <0xec030000 0x10000>; -+ #phy-cells = <0>; -+ clocks = <&clk_misc 1>, <&clk_misc 3>; -+ clock-names = "bus", "ref"; -+ resets = <&rst_misc 6>, <&rst_misc 7>; -+ reset-names = "bus", "phy"; -+ avdd33-usb3-supply = <&avdd33_usb3>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux/0176-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch b/SPECS/linux/0176-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch new file mode 100644 index 0000000000..d0c6b0f877 --- /dev/null +++ b/SPECS/linux/0176-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch @@ -0,0 +1,281 @@ +From 2235071fae0b39e9cecef57fcbe3435aaa4fbaa7 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:03 +0800 +Subject: [RUYI PATCH] FROMLIST: phy: add a driver for T-Head TH1520 USB PHY + +The USB PHY on T-Head TH1520 SoC is a Synopsys USB 3.0 FemtoPHY, with +some PHY parameters exported as another system controller along with it. + +As a few PHY parameters' default value isn't ready to work, add a driver +configuring them before letting the PHY run, in addition to +clock/reset/regulator management. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-6-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/phy/Kconfig | 1 + + drivers/phy/Makefile | 1 + + drivers/phy/thead/Kconfig | 12 ++ + drivers/phy/thead/Makefile | 2 + + drivers/phy/thead/phy-th1520-usb.c | 197 +++++++++++++++++++++++++++++ + 5 files changed, 213 insertions(+) + create mode 100644 drivers/phy/thead/Kconfig + create mode 100644 drivers/phy/thead/Makefile + create mode 100644 drivers/phy/thead/phy-th1520-usb.c + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index 1875d5b784f6..6b5d0fda26e1 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -173,6 +173,7 @@ source "drivers/phy/st/Kconfig" + source "drivers/phy/starfive/Kconfig" + source "drivers/phy/sunplus/Kconfig" + source "drivers/phy/tegra/Kconfig" ++source "drivers/phy/thead/Kconfig" + source "drivers/phy/ti/Kconfig" + source "drivers/phy/intel/Kconfig" + source "drivers/phy/xilinx/Kconfig" +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index a648c2e02a83..d4636a375b7c 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -46,5 +46,6 @@ obj-$(CONFIG_GENERIC_PHY) += allwinner/ \ + starfive/ \ + sunplus/ \ + tegra/ \ ++ thead/ \ + ti/ \ + xilinx/ +diff --git a/drivers/phy/thead/Kconfig b/drivers/phy/thead/Kconfig +new file mode 100644 +index 000000000000..14012db5973c +--- /dev/null ++++ b/drivers/phy/thead/Kconfig +@@ -0,0 +1,12 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++config PHY_TH1520_USB ++ tristate "USB PHY driver for T-Head TH1520 SoC" ++ depends on ARCH_THEAD || COMPILE_TEST ++ depends on COMMON_CLK ++ depends on HAS_IOMEM ++ depends on OF ++ depends on RESET_CONTROLLER ++ select GENERIC_PHY ++ default ARCH_THEAD ++ help ++ Enable support for the USB PHY on the T-Head TH1520 SoC. +diff --git a/drivers/phy/thead/Makefile b/drivers/phy/thead/Makefile +new file mode 100644 +index 000000000000..5b459bc7004b +--- /dev/null ++++ b/drivers/phy/thead/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++obj-$(CONFIG_PHY_TH1520_USB) += phy-th1520-usb.o +diff --git a/drivers/phy/thead/phy-th1520-usb.c b/drivers/phy/thead/phy-th1520-usb.c +new file mode 100644 +index 000000000000..c87bd779bbb7 +--- /dev/null ++++ b/drivers/phy/thead/phy-th1520-usb.c +@@ -0,0 +1,197 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (ISCAS) ++ * ++ * Authors: ++ * Icenowy Zheng ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define USB_SYSCON_OFFSET 0xf000 ++ ++/* All the below registers are in the USB syscon region */ ++#define USB_CLK_GATE_STS 0x0 ++#define USB_LOGIC_ANALYZER_TRACE_STS0 0x4 ++#define USB_LOGIC_ANALYZER_TRACE_STS1 0x8 ++#define USB_GPIO 0xc ++#define USB_DEBUG_STS0 0x10 ++#define USB_DEBUG_STS1 0x14 ++#define USB_DEBUG_STS2 0x18 ++#define USBCTL_CLK_CTRL0 0x1c ++#define USBPHY_CLK_CTRL1 0x20 ++#define USBPHY_TEST_CTRL0 0x24 ++#define USBPHY_TEST_CTRL1 0x28 ++#define USBPHY_TEST_CTRL2 0x2c ++#define USBPHY_TEST_CTRL3 0x30 ++#define USB_SSP_EN 0x34 ++#define USB_HADDR_SEL 0x38 ++#define USB_SYS 0x3c ++#define USB_HOST_STATUS 0x40 ++#define USB_HOST_CTRL 0x44 ++#define USBPHY_HOST_CTRL 0x48 ++#define USBPHY_HOST_STATUS 0x4c ++#define USB_TEST_REG0 0x50 ++#define USB_TEST_REG1 0x54 ++#define USB_TEST_REG2 0x58 ++#define USB_TEST_REG3 0x5c ++ ++#define USB_SYS_COMMONONN BIT(0) ++ ++#define USB_SSP_EN_REF_SSP_EN BIT(0) ++ ++struct th1520_usb_phy { ++ struct platform_device *pdev; ++ struct phy *phy; ++ struct regmap *regmap; ++ struct clk *ref_clk; ++ struct reset_control *phy_reset; ++}; ++ ++static int th1520_usb_phy_init(struct phy *phy) ++{ ++ struct th1520_usb_phy *th1520_phy = phy_get_drvdata(phy); ++ int ret; ++ ++ ret = clk_prepare_enable(th1520_phy->ref_clk); ++ if (ret) ++ return ret; ++ ++ ret = reset_control_assert(th1520_phy->phy_reset); ++ if (ret) ++ goto err_disable_clk; ++ ++ /* ++ * Do some initial PHY setup: ++ * - Set COMMONONN to allow the PHY to automatically power down. ++ * - Set REF_SSP_EN to enable feeding reference clock to SuperSpeed ++ * PHY clock PLL. ++ */ ++ regmap_set_bits(th1520_phy->regmap, USB_SYS, USB_SYS_COMMONONN); ++ regmap_set_bits(th1520_phy->regmap, USB_SSP_EN, USB_SSP_EN_REF_SSP_EN); ++ ++ ret = reset_control_deassert(th1520_phy->phy_reset); ++ if (ret) ++ goto err_disable_clk; ++ ++ udelay(10); ++ ++ return 0; ++ ++err_disable_clk: ++ clk_disable_unprepare(th1520_phy->ref_clk); ++ return ret; ++} ++ ++static int th1520_usb_phy_exit(struct phy *phy) ++{ ++ struct th1520_usb_phy *th1520_phy = phy_get_drvdata(phy); ++ int ret; ++ ++ ret = reset_control_assert(th1520_phy->phy_reset); ++ if (ret) ++ return ret; ++ ++ clk_disable_unprepare(th1520_phy->ref_clk); ++ ++ return 0; ++} ++ ++static const struct phy_ops th1520_usb_phy_ops = { ++ .init = th1520_usb_phy_init, ++ .exit = th1520_usb_phy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct regmap_config phy_regmap_config = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ .max_register = USB_TEST_REG3, ++}; ++ ++static int th1520_usb_phy_probe(struct platform_device *pdev) ++{ ++ struct phy_provider *phy_provider; ++ struct device *dev = &pdev->dev; ++ struct th1520_usb_phy *th1520_phy; ++ struct reset_control *bus_reset; ++ void __iomem *base; ++ int ret; ++ ++ th1520_phy = devm_kzalloc(dev, sizeof(*th1520_phy), GFP_KERNEL); ++ if (!th1520_phy) ++ return -ENOMEM; ++ ++ th1520_phy->pdev = pdev; ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ th1520_phy->ref_clk = devm_clk_get(dev, "ref"); ++ if (IS_ERR(th1520_phy->ref_clk)) ++ return PTR_ERR(th1520_phy->ref_clk); ++ ++ /* De-assert the bus reset and leave it that way */ ++ bus_reset = devm_reset_control_get_exclusive_deasserted(dev, "bus"); ++ if (IS_ERR(bus_reset)) ++ return PTR_ERR(bus_reset); ++ ++ th1520_phy->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); ++ if (IS_ERR(th1520_phy->phy_reset)) ++ return PTR_ERR(th1520_phy->phy_reset); ++ ++ /* ++ * Schematics of several boards (Lichee Module 4A/Milk-V Meles) ++ * describe this power rail as always-on. ++ */ ++ ret = devm_regulator_get_enable(dev, "avdd33-usb3"); ++ if (ret) ++ return ret; ++ ++ th1520_phy->regmap = devm_regmap_init_mmio_clk(dev, "bus", ++ base + USB_SYSCON_OFFSET, ++ &phy_regmap_config); ++ if (IS_ERR(th1520_phy->regmap)) ++ return dev_err_probe(dev, PTR_ERR(th1520_phy->regmap), ++ "Failed to init regmap\n"); ++ ++ th1520_phy->phy = devm_phy_create(dev, dev->of_node, &th1520_usb_phy_ops); ++ if (IS_ERR(th1520_phy->phy)) { ++ dev_err(dev, "failed to create PHY\n"); ++ return PTR_ERR(th1520_phy->phy); ++ } ++ ++ phy_set_drvdata(th1520_phy->phy, th1520_phy); ++ ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static const struct of_device_id th1520_usb_phy_of_table[] = { ++ { .compatible = "thead,th1520-usb-phy" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, th1520_usb_phy_of_table); ++ ++static struct platform_driver th1520_usb_phy_driver = { ++ .driver = { ++ .name = "th1520-usb-phy", ++ .of_match_table = th1520_usb_phy_of_table, ++ }, ++ .probe = th1520_usb_phy_probe, ++}; ++ ++module_platform_driver(th1520_usb_phy_driver); ++ ++MODULE_DESCRIPTION("T-Head TH1520 USB PHY driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux/0177-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch b/SPECS/linux/0177-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch deleted file mode 100644 index d1ac0ab273..0000000000 --- a/SPECS/linux/0177-FROMLIST-phy-add-a-driver-for-T-Head-TH1520-USB-PHY.patch +++ /dev/null @@ -1,281 +0,0 @@ -From 8dfb3f35a8fe62724dfade3c5f458c94951ffb21 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:03 +0800 -Subject: [PATCH 177/269] FROMLIST: phy: add a driver for T-Head TH1520 USB PHY - -The USB PHY on T-Head TH1520 SoC is a Synopsys USB 3.0 FemtoPHY, with -some PHY parameters exported as another system controller along with it. - -As a few PHY parameters' default value isn't ready to work, add a driver -configuring them before letting the PHY run, in addition to -clock/reset/regulator management. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-6-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/phy/Kconfig | 1 + - drivers/phy/Makefile | 1 + - drivers/phy/thead/Kconfig | 12 ++ - drivers/phy/thead/Makefile | 2 + - drivers/phy/thead/phy-th1520-usb.c | 197 +++++++++++++++++++++++++++++ - 5 files changed, 213 insertions(+) - create mode 100644 drivers/phy/thead/Kconfig - create mode 100644 drivers/phy/thead/Makefile - create mode 100644 drivers/phy/thead/phy-th1520-usb.c - -diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig -index 1875d5b784f6..6b5d0fda26e1 100644 ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -173,6 +173,7 @@ source "drivers/phy/st/Kconfig" - source "drivers/phy/starfive/Kconfig" - source "drivers/phy/sunplus/Kconfig" - source "drivers/phy/tegra/Kconfig" -+source "drivers/phy/thead/Kconfig" - source "drivers/phy/ti/Kconfig" - source "drivers/phy/intel/Kconfig" - source "drivers/phy/xilinx/Kconfig" -diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile -index a648c2e02a83..d4636a375b7c 100644 ---- a/drivers/phy/Makefile -+++ b/drivers/phy/Makefile -@@ -46,5 +46,6 @@ obj-$(CONFIG_GENERIC_PHY) += allwinner/ \ - starfive/ \ - sunplus/ \ - tegra/ \ -+ thead/ \ - ti/ \ - xilinx/ -diff --git a/drivers/phy/thead/Kconfig b/drivers/phy/thead/Kconfig -new file mode 100644 -index 000000000000..14012db5973c ---- /dev/null -+++ b/drivers/phy/thead/Kconfig -@@ -0,0 +1,12 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+config PHY_TH1520_USB -+ tristate "USB PHY driver for T-Head TH1520 SoC" -+ depends on ARCH_THEAD || COMPILE_TEST -+ depends on COMMON_CLK -+ depends on HAS_IOMEM -+ depends on OF -+ depends on RESET_CONTROLLER -+ select GENERIC_PHY -+ default ARCH_THEAD -+ help -+ Enable support for the USB PHY on the T-Head TH1520 SoC. -diff --git a/drivers/phy/thead/Makefile b/drivers/phy/thead/Makefile -new file mode 100644 -index 000000000000..5b459bc7004b ---- /dev/null -+++ b/drivers/phy/thead/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+obj-$(CONFIG_PHY_TH1520_USB) += phy-th1520-usb.o -diff --git a/drivers/phy/thead/phy-th1520-usb.c b/drivers/phy/thead/phy-th1520-usb.c -new file mode 100644 -index 000000000000..c87bd779bbb7 ---- /dev/null -+++ b/drivers/phy/thead/phy-th1520-usb.c -@@ -0,0 +1,197 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2026 Institute of Software, Chinese Academy of Sciences (ISCAS) -+ * -+ * Authors: -+ * Icenowy Zheng -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define USB_SYSCON_OFFSET 0xf000 -+ -+/* All the below registers are in the USB syscon region */ -+#define USB_CLK_GATE_STS 0x0 -+#define USB_LOGIC_ANALYZER_TRACE_STS0 0x4 -+#define USB_LOGIC_ANALYZER_TRACE_STS1 0x8 -+#define USB_GPIO 0xc -+#define USB_DEBUG_STS0 0x10 -+#define USB_DEBUG_STS1 0x14 -+#define USB_DEBUG_STS2 0x18 -+#define USBCTL_CLK_CTRL0 0x1c -+#define USBPHY_CLK_CTRL1 0x20 -+#define USBPHY_TEST_CTRL0 0x24 -+#define USBPHY_TEST_CTRL1 0x28 -+#define USBPHY_TEST_CTRL2 0x2c -+#define USBPHY_TEST_CTRL3 0x30 -+#define USB_SSP_EN 0x34 -+#define USB_HADDR_SEL 0x38 -+#define USB_SYS 0x3c -+#define USB_HOST_STATUS 0x40 -+#define USB_HOST_CTRL 0x44 -+#define USBPHY_HOST_CTRL 0x48 -+#define USBPHY_HOST_STATUS 0x4c -+#define USB_TEST_REG0 0x50 -+#define USB_TEST_REG1 0x54 -+#define USB_TEST_REG2 0x58 -+#define USB_TEST_REG3 0x5c -+ -+#define USB_SYS_COMMONONN BIT(0) -+ -+#define USB_SSP_EN_REF_SSP_EN BIT(0) -+ -+struct th1520_usb_phy { -+ struct platform_device *pdev; -+ struct phy *phy; -+ struct regmap *regmap; -+ struct clk *ref_clk; -+ struct reset_control *phy_reset; -+}; -+ -+static int th1520_usb_phy_init(struct phy *phy) -+{ -+ struct th1520_usb_phy *th1520_phy = phy_get_drvdata(phy); -+ int ret; -+ -+ ret = clk_prepare_enable(th1520_phy->ref_clk); -+ if (ret) -+ return ret; -+ -+ ret = reset_control_assert(th1520_phy->phy_reset); -+ if (ret) -+ goto err_disable_clk; -+ -+ /* -+ * Do some initial PHY setup: -+ * - Set COMMONONN to allow the PHY to automatically power down. -+ * - Set REF_SSP_EN to enable feeding reference clock to SuperSpeed -+ * PHY clock PLL. -+ */ -+ regmap_set_bits(th1520_phy->regmap, USB_SYS, USB_SYS_COMMONONN); -+ regmap_set_bits(th1520_phy->regmap, USB_SSP_EN, USB_SSP_EN_REF_SSP_EN); -+ -+ ret = reset_control_deassert(th1520_phy->phy_reset); -+ if (ret) -+ goto err_disable_clk; -+ -+ udelay(10); -+ -+ return 0; -+ -+err_disable_clk: -+ clk_disable_unprepare(th1520_phy->ref_clk); -+ return ret; -+} -+ -+static int th1520_usb_phy_exit(struct phy *phy) -+{ -+ struct th1520_usb_phy *th1520_phy = phy_get_drvdata(phy); -+ int ret; -+ -+ ret = reset_control_assert(th1520_phy->phy_reset); -+ if (ret) -+ return ret; -+ -+ clk_disable_unprepare(th1520_phy->ref_clk); -+ -+ return 0; -+} -+ -+static const struct phy_ops th1520_usb_phy_ops = { -+ .init = th1520_usb_phy_init, -+ .exit = th1520_usb_phy_exit, -+ .owner = THIS_MODULE, -+}; -+ -+static const struct regmap_config phy_regmap_config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .max_register = USB_TEST_REG3, -+}; -+ -+static int th1520_usb_phy_probe(struct platform_device *pdev) -+{ -+ struct phy_provider *phy_provider; -+ struct device *dev = &pdev->dev; -+ struct th1520_usb_phy *th1520_phy; -+ struct reset_control *bus_reset; -+ void __iomem *base; -+ int ret; -+ -+ th1520_phy = devm_kzalloc(dev, sizeof(*th1520_phy), GFP_KERNEL); -+ if (!th1520_phy) -+ return -ENOMEM; -+ -+ th1520_phy->pdev = pdev; -+ -+ base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ th1520_phy->ref_clk = devm_clk_get(dev, "ref"); -+ if (IS_ERR(th1520_phy->ref_clk)) -+ return PTR_ERR(th1520_phy->ref_clk); -+ -+ /* De-assert the bus reset and leave it that way */ -+ bus_reset = devm_reset_control_get_exclusive_deasserted(dev, "bus"); -+ if (IS_ERR(bus_reset)) -+ return PTR_ERR(bus_reset); -+ -+ th1520_phy->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); -+ if (IS_ERR(th1520_phy->phy_reset)) -+ return PTR_ERR(th1520_phy->phy_reset); -+ -+ /* -+ * Schematics of several boards (Lichee Module 4A/Milk-V Meles) -+ * describe this power rail as always-on. -+ */ -+ ret = devm_regulator_get_enable(dev, "avdd33-usb3"); -+ if (ret) -+ return ret; -+ -+ th1520_phy->regmap = devm_regmap_init_mmio_clk(dev, "bus", -+ base + USB_SYSCON_OFFSET, -+ &phy_regmap_config); -+ if (IS_ERR(th1520_phy->regmap)) -+ return dev_err_probe(dev, PTR_ERR(th1520_phy->regmap), -+ "Failed to init regmap\n"); -+ -+ th1520_phy->phy = devm_phy_create(dev, dev->of_node, &th1520_usb_phy_ops); -+ if (IS_ERR(th1520_phy->phy)) { -+ dev_err(dev, "failed to create PHY\n"); -+ return PTR_ERR(th1520_phy->phy); -+ } -+ -+ phy_set_drvdata(th1520_phy->phy, th1520_phy); -+ -+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id th1520_usb_phy_of_table[] = { -+ { .compatible = "thead,th1520-usb-phy" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, th1520_usb_phy_of_table); -+ -+static struct platform_driver th1520_usb_phy_driver = { -+ .driver = { -+ .name = "th1520-usb-phy", -+ .of_match_table = th1520_usb_phy_of_table, -+ }, -+ .probe = th1520_usb_phy_probe, -+}; -+ -+module_platform_driver(th1520_usb_phy_driver); -+ -+MODULE_DESCRIPTION("T-Head TH1520 USB PHY driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux/0177-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch b/SPECS/linux/0177-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch new file mode 100644 index 0000000000..c14c946574 --- /dev/null +++ b/SPECS/linux/0177-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch @@ -0,0 +1,68 @@ +From adb387aac2d84509b474f9a538aaf8564db53c48 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:04 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: add device nodes for USB + +The TH1520 SoC contains a Synopsys DesignWare Cores SuperSpeed USB3.0 +Dual Role Device controller in addition to a USB2+USB3 combo PHY based +on Synopsys USB3.0 FemtoPHY. + +Add device tree nodes for them. The USB controller is quite generic, new +and properly configured during silicon design, but the PHY is a little +quirky. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-7-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index 4d1e71227339..f1746b5fcd40 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -351,6 +351,20 @@ uart0: serial@ffe7014000 { + status = "disabled"; + }; + ++ usb: usb@ffe7040000 { ++ compatible = "snps,dwc3"; ++ reg = <0xff 0xe7040000 0x0 0x10000>; ++ interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_misc CLK_USB>, ++ <&clk_misc CLK_USB_CTL_REF>, ++ <&clk_misc CLK_USB_SUSPEND>; ++ clock-names = "bus_early", "ref", "suspend"; ++ resets = <&rst_misc TH1520_RESET_ID_USB3_VCC>; ++ phys = <&usb_phy>; ++ phy-names = "usb3-phy"; ++ status = "disabled"; ++ }; ++ + gmac1: ethernet@ffe7060000 { + compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; + reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; +@@ -575,6 +589,19 @@ clk_misc: clock-controller@ffec02c100 { + #clock-cells = <1>; + }; + ++ usb_phy: phy@ffec030000 { ++ compatible = "thead,th1520-usb-phy"; ++ reg = <0xff 0xec030000 0x0 0x10000>; ++ clocks = <&clk_misc CLK_USB>, ++ <&clk_misc CLK_USB_PHY_REF>; ++ clock-names = "bus", "ref"; ++ resets = <&rst_misc TH1520_RESET_ID_USB3_APB>, ++ <&rst_misc TH1520_RESET_ID_USB3_PHY>; ++ reset-names = "bus", "phy"; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + rst_vp: reset-controller@ffecc30000 { + compatible = "thead,th1520-reset-vp"; + reg = <0xff 0xecc30000 0x0 0x14>; +-- +2.53.0 + diff --git a/SPECS/linux/0178-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch b/SPECS/linux/0178-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch new file mode 100644 index 0000000000..817f70b272 --- /dev/null +++ b/SPECS/linux/0178-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch @@ -0,0 +1,41 @@ +From cef20c021cd1981f24a02368ab1150f185f2350d Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:05 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: gpio: dwapb: allow GPIO hogs + +GPIO hogs are described in the gpio.txt binding as automatic default +GPIO configuration items. + +Allow them for GPIO ports in DesignWare APB GPIO controller nodes. + +Cc: Hoan Tran +Cc: Linus Walleij +Cc: Bartosz Golaszewski +Cc: Serge Semin +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-8-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../devicetree/bindings/gpio/snps,dw-apb-gpio.yaml | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml +index bba6f5b6606f..55069533f6d9 100644 +--- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml ++++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml +@@ -95,6 +95,12 @@ patternProperties: + '#interrupt-cells': + const: 2 + ++ patternProperties: ++ "^.+-hog(-[0-9]+)?$": ++ type: object ++ required: ++ - gpio-hog ++ + required: + - compatible + - reg +-- +2.53.0 + diff --git a/SPECS/linux/0178-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch b/SPECS/linux/0178-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch deleted file mode 100644 index 51cec06625..0000000000 --- a/SPECS/linux/0178-FROMLIST-riscv-dts-thead-add-device-nodes-for-USB.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 2b1c32d8eb39d09e3079eff6a81db2741d53f699 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:04 +0800 -Subject: [PATCH 178/269] FROMLIST: riscv: dts: thead: add device nodes for USB - -The TH1520 SoC contains a Synopsys DesignWare Cores SuperSpeed USB3.0 -Dual Role Device controller in addition to a USB2+USB3 combo PHY based -on Synopsys USB3.0 FemtoPHY. - -Add device tree nodes for them. The USB controller is quite generic, new -and properly configured during silicon design, but the PHY is a little -quirky. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-7-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index 4d1e71227339..f1746b5fcd40 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -351,6 +351,20 @@ uart0: serial@ffe7014000 { - status = "disabled"; - }; - -+ usb: usb@ffe7040000 { -+ compatible = "snps,dwc3"; -+ reg = <0xff 0xe7040000 0x0 0x10000>; -+ interrupts = <68 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk_misc CLK_USB>, -+ <&clk_misc CLK_USB_CTL_REF>, -+ <&clk_misc CLK_USB_SUSPEND>; -+ clock-names = "bus_early", "ref", "suspend"; -+ resets = <&rst_misc TH1520_RESET_ID_USB3_VCC>; -+ phys = <&usb_phy>; -+ phy-names = "usb3-phy"; -+ status = "disabled"; -+ }; -+ - gmac1: ethernet@ffe7060000 { - compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; - reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; -@@ -575,6 +589,19 @@ clk_misc: clock-controller@ffec02c100 { - #clock-cells = <1>; - }; - -+ usb_phy: phy@ffec030000 { -+ compatible = "thead,th1520-usb-phy"; -+ reg = <0xff 0xec030000 0x0 0x10000>; -+ clocks = <&clk_misc CLK_USB>, -+ <&clk_misc CLK_USB_PHY_REF>; -+ clock-names = "bus", "ref"; -+ resets = <&rst_misc TH1520_RESET_ID_USB3_APB>, -+ <&rst_misc TH1520_RESET_ID_USB3_PHY>; -+ reset-names = "bus", "phy"; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - rst_vp: reset-controller@ffecc30000 { - compatible = "thead,th1520-reset-vp"; - reg = <0xff 0xecc30000 0x0 0x14>; --- -2.53.0 - diff --git a/SPECS/linux/0179-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch b/SPECS/linux/0179-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch deleted file mode 100644 index 42cca6cc78..0000000000 --- a/SPECS/linux/0179-FROMLIST-dt-bindings-gpio-dwapb-allow-GPIO-hogs.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 8d5b44b9e1e20e8c11a156cf05f4eebc2353ad11 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:05 +0800 -Subject: [PATCH 179/269] FROMLIST: dt-bindings: gpio: dwapb: allow GPIO hogs - -GPIO hogs are described in the gpio.txt binding as automatic default -GPIO configuration items. - -Allow them for GPIO ports in DesignWare APB GPIO controller nodes. - -Cc: Hoan Tran -Cc: Linus Walleij -Cc: Bartosz Golaszewski -Cc: Serge Semin -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-8-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../devicetree/bindings/gpio/snps,dw-apb-gpio.yaml | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml -index bba6f5b6606f..55069533f6d9 100644 ---- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml -+++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml -@@ -95,6 +95,12 @@ patternProperties: - '#interrupt-cells': - const: 2 - -+ patternProperties: -+ "^.+-hog(-[0-9]+)?$": -+ type: object -+ required: -+ - gpio-hog -+ - required: - - compatible - - reg --- -2.53.0 - diff --git a/SPECS/linux/0179-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch b/SPECS/linux/0179-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch new file mode 100644 index 0000000000..afe5007550 --- /dev/null +++ b/SPECS/linux/0179-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch @@ -0,0 +1,48 @@ +From 0a04aab4ab49a84e24d260494d417c46aa61c5dc Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:06 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: usb: vialab,vl817: allow ports + property + +As a USB hub device, VL817 can surely be connected to external USB +connectors. The binding for such connectors connection is already +described in the generic usb-hub.yaml binding with ports subnode, but +it's not yet allowed in the VL817 binding. + +Switch the reference binding from usb-device.yaml to usb-hub.yaml (which +recursively references usb-device.yaml and contains definition for ports +subnode) and allow ports subnode in VL817 binding. + +Cc: Anand Moon +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-9-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/usb/vialab,vl817.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml +index c815010ba9c2..7387f4fae54d 100644 +--- a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml ++++ b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml +@@ -10,7 +10,7 @@ maintainers: + - Anand Moon + + allOf: +- - $ref: usb-device.yaml# ++ - $ref: usb-hub.yaml# + + properties: + compatible: +@@ -34,6 +34,8 @@ properties: + description: + phandle to the peer hub on the controller. + ++ ports: true ++ + required: + - compatible + - reg +-- +2.53.0 + diff --git a/SPECS/linux/0180-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch b/SPECS/linux/0180-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch deleted file mode 100644 index 22bd8dd71b..0000000000 --- a/SPECS/linux/0180-FROMLIST-dt-bindings-usb-vialab-vl817-allow-ports-pr.patch +++ /dev/null @@ -1,48 +0,0 @@ -From f6873f8ca0bd852d3067add9fd953473f73c2de1 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:06 +0800 -Subject: [PATCH 180/269] FROMLIST: dt-bindings: usb: vialab,vl817: allow ports - property - -As a USB hub device, VL817 can surely be connected to external USB -connectors. The binding for such connectors connection is already -described in the generic usb-hub.yaml binding with ports subnode, but -it's not yet allowed in the VL817 binding. - -Switch the reference binding from usb-device.yaml to usb-hub.yaml (which -recursively references usb-device.yaml and contains definition for ports -subnode) and allow ports subnode in VL817 binding. - -Cc: Anand Moon -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-9-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/usb/vialab,vl817.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml -index c815010ba9c2..7387f4fae54d 100644 ---- a/Documentation/devicetree/bindings/usb/vialab,vl817.yaml -+++ b/Documentation/devicetree/bindings/usb/vialab,vl817.yaml -@@ -10,7 +10,7 @@ maintainers: - - Anand Moon - - allOf: -- - $ref: usb-device.yaml# -+ - $ref: usb-hub.yaml# - - properties: - compatible: -@@ -34,6 +34,8 @@ properties: - description: - phandle to the peer hub on the controller. - -+ ports: true -+ - required: - - compatible - - reg --- -2.53.0 - diff --git a/SPECS/linux/0180-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch b/SPECS/linux/0180-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch new file mode 100644 index 0000000000..1b39142a86 --- /dev/null +++ b/SPECS/linux/0180-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch @@ -0,0 +1,66 @@ +From 4fbacbaa261eb5d38e67abce3e1befcc95b5e2d9 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:07 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: lpi4a: sort nodes + +Although "D" and "H" are earlier in the alphabet than "P", the DPU and +HDMI nodes were added after PADCTRL node in the Lichee Pi 4A device tree. + +Sort the nodes in this device tree. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-10-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 28 +++++++++---------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index 7cb7d28683bc..4198dbf953f0 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -96,6 +96,20 @@ fan: pwm-fan { + + }; + ++&dpu { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out_port { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &padctrl0_apsys { + fan_pins: fan-0 { + pwm1-pins { +@@ -132,20 +146,6 @@ rx-pins { + }; + }; + +-&dpu { +- status = "okay"; +-}; +- +-&hdmi { +- status = "okay"; +-}; +- +-&hdmi_out_port { +- hdmi_out_con: endpoint { +- remote-endpoint = <&hdmi_con_in>; +- }; +-}; +- + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +-- +2.53.0 + diff --git a/SPECS/linux/0181-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch b/SPECS/linux/0181-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch new file mode 100644 index 0000000000..598fdf7c83 --- /dev/null +++ b/SPECS/linux/0181-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch @@ -0,0 +1,112 @@ +From cafa4873834e652c5a0d0c10d04b073018eb693e Mon Sep 17 00:00:00 2001 +From: Thomas Bonnefille +Date: Thu, 7 May 2026 16:17:08 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Add TH1520 I2C nodes + +Add nodes for the six I2C on the T-Head TH1520 RISCV SoC. + +Signed-off-by: Thomas Bonnefille +Reviewed-by: Drew Fustini +[Icenowy: rebase on top of v7.1-rc2] +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-11-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 60 +++++++++++++++++++++++++++ + 1 file changed, 60 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index f1746b5fcd40..e44010810c07 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -460,6 +460,36 @@ uart3: serial@ffe7f04000 { + status = "disabled"; + }; + ++ i2c0: i2c@ffe7f20000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xe7f20000 0x0 0x4000>; ++ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@ffe7f24000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xe7f24000 0x0 0x4000>; ++ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c4: i2c@ffe7f28000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xe7f28000 0x0 0x4000>; ++ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C4>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + gpio@ffe7f34000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f34000 0x0 0x1000>; +@@ -558,6 +588,16 @@ padctrl0_apsys: pinctrl@ffec007000 { + thead,pad-group = <3>; + }; + ++ i2c2: i2c@ffec00c000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xec00c000 0x0 0x4000>; ++ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C2>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + uart2: serial@ffec010000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xec010000 0x0 0x4000>; +@@ -569,6 +609,16 @@ uart2: serial@ffec010000 { + status = "disabled"; + }; + ++ i2c3: i2c@ffec014000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xec014000 0x0 0x4000>; ++ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C3>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + pwm: pwm@ffec01c000 { + compatible = "thead,th1520-pwm"; + reg = <0xff 0xec01c000 0x0 0x4000>; +@@ -794,6 +844,16 @@ uart5: serial@fff7f0c000 { + status = "disabled"; + }; + ++ i2c5: i2c@fff7f2c000 { ++ compatible = "thead,th1520-i2c", "snps,designware-i2c"; ++ reg = <0xff 0xf7f2c000 0x0 0x4000>; ++ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk CLK_I2C5>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + timer4: timer@ffffc33000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33000 0x0 0x14>; +-- +2.53.0 + diff --git a/SPECS/linux/0181-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch b/SPECS/linux/0181-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch deleted file mode 100644 index 7146f8ade4..0000000000 --- a/SPECS/linux/0181-FROMLIST-riscv-dts-thead-lpi4a-sort-nodes.patch +++ /dev/null @@ -1,66 +0,0 @@ -From dc3c3a6909f7928d49cdab3d3bdb993d2479b115 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:07 +0800 -Subject: [PATCH 181/269] FROMLIST: riscv: dts: thead: lpi4a: sort nodes - -Although "D" and "H" are earlier in the alphabet than "P", the DPU and -HDMI nodes were added after PADCTRL node in the Lichee Pi 4A device tree. - -Sort the nodes in this device tree. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-10-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-lichee-pi-4a.dts | 28 +++++++++---------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -index 7cb7d28683bc..4198dbf953f0 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -@@ -96,6 +96,20 @@ fan: pwm-fan { - - }; - -+&dpu { -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out_port { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &padctrl0_apsys { - fan_pins: fan-0 { - pwm1-pins { -@@ -132,20 +146,6 @@ rx-pins { - }; - }; - --&dpu { -- status = "okay"; --}; -- --&hdmi { -- status = "okay"; --}; -- --&hdmi_out_port { -- hdmi_out_con: endpoint { -- remote-endpoint = <&hdmi_con_in>; -- }; --}; -- - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; --- -2.53.0 - diff --git a/SPECS/linux/0182-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch b/SPECS/linux/0182-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch new file mode 100644 index 0000000000..be6a55fdc9 --- /dev/null +++ b/SPECS/linux/0182-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch @@ -0,0 +1,166 @@ +From 832edb826bfc6ad14779e6747d859479b5e59f0d Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Thu, 7 May 2026 16:17:09 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Add Lichee Pi 4A IO + expansions + +Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the +I2C0/1/3 busses. + +Add device tree nodes for them. + +Signed-off-by: Emil Renner Berthing +[Icenowy: added commit description] +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-12-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 111 ++++++++++++++++++ + 1 file changed, 111 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index 4198dbf953f0..354f3893aa8c 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -16,6 +16,9 @@ aliases { + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &aogpio; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c3 = &i2c3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; +@@ -110,6 +113,76 @@ hdmi_out_con: endpoint { + }; + }; + ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ status = "okay"; ++ ++ ioexp1: gpio@18 { ++ compatible = "nxp,pca9557"; ++ reg = <0x18>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = "cam0_dvdd12", ++ "cam0_avdd28", ++ "cam0_dovdd18"; ++ }; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ status = "okay"; ++ ++ ioexp2: gpio@18 { ++ compatible = "nxp,pca9557"; ++ reg = <0x18>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = "", ++ "cam0_reset", ++ "cam1_reset", ++ "cam2_reset", ++ "wl_host_wake", ++ "bt_resetn", ++ "", ++ "bt_host_wake"; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ status = "okay"; ++ ++ ioexp3: gpio@18 { ++ compatible = "nxp,pca9557"; ++ reg = <0x18>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = "tp0_rst", ++ "", ++ "", ++ "vcc5v_usb", ++ "vdd28_tp0", ++ "vdd33_lcd0", ++ "vdd18_lcd0", ++ "lcd0_reset"; ++ }; ++}; ++ + &padctrl0_apsys { + fan_pins: fan-0 { + pwm1-pins { +@@ -123,6 +196,18 @@ pwm1-pins { + }; + }; + ++ i2c3_pins: i2c3-0 { ++ i2c-pins { ++ pins = "I2C3_SCL", "I2C3_SDA"; ++ function = "i2c"; ++ bias-disable; /* external pull-up */ ++ drive-strength = <7>; ++ input-enable; ++ input-schmitt-enable; ++ slew-rate = <0>; ++ }; ++ }; ++ + uart0_pins: uart0-0 { + tx-pins { + pins = "UART0_TXD"; +@@ -146,6 +231,32 @@ rx-pins { + }; + }; + ++&padctrl1_apsys { ++ i2c0_pins: i2c0-0 { ++ i2c-pins { ++ pins = "I2C0_SCL", "I2C0_SDA"; ++ function = "i2c"; ++ bias-disable; /* external pull-up */ ++ drive-strength = <7>; ++ input-enable; ++ input-schmitt-enable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ i2c1_pins: i2c1-0 { ++ i2c-pins { ++ pins = "I2C1_SCL", "I2C1_SDA"; ++ function = "i2c"; ++ bias-disable; /* external pull-up */ ++ drive-strength = <7>; ++ input-enable; ++ input-schmitt-enable; ++ slew-rate = <0>; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +-- +2.53.0 + diff --git a/SPECS/linux/0182-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch b/SPECS/linux/0182-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch deleted file mode 100644 index 0ff8c75983..0000000000 --- a/SPECS/linux/0182-FROMLIST-riscv-dts-thead-Add-TH1520-I2C-nodes.patch +++ /dev/null @@ -1,112 +0,0 @@ -From c7a47dd3521c7febaa5ede78663f085807685032 Mon Sep 17 00:00:00 2001 -From: Thomas Bonnefille -Date: Thu, 7 May 2026 16:17:08 +0800 -Subject: [PATCH 182/269] FROMLIST: riscv: dts: thead: Add TH1520 I2C nodes - -Add nodes for the six I2C on the T-Head TH1520 RISCV SoC. - -Signed-off-by: Thomas Bonnefille -Reviewed-by: Drew Fustini -[Icenowy: rebase on top of v7.1-rc2] -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-11-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 60 +++++++++++++++++++++++++++ - 1 file changed, 60 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index f1746b5fcd40..e44010810c07 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -460,6 +460,36 @@ uart3: serial@ffe7f04000 { - status = "disabled"; - }; - -+ i2c0: i2c@ffe7f20000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xe7f20000 0x0 0x4000>; -+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@ffe7f24000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xe7f24000 0x0 0x4000>; -+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@ffe7f28000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xe7f28000 0x0 0x4000>; -+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C4>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - gpio@ffe7f34000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f34000 0x0 0x1000>; -@@ -558,6 +588,16 @@ padctrl0_apsys: pinctrl@ffec007000 { - thead,pad-group = <3>; - }; - -+ i2c2: i2c@ffec00c000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xec00c000 0x0 0x4000>; -+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - uart2: serial@ffec010000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xec010000 0x0 0x4000>; -@@ -569,6 +609,16 @@ uart2: serial@ffec010000 { - status = "disabled"; - }; - -+ i2c3: i2c@ffec014000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xec014000 0x0 0x4000>; -+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C3>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - pwm: pwm@ffec01c000 { - compatible = "thead,th1520-pwm"; - reg = <0xff 0xec01c000 0x0 0x4000>; -@@ -794,6 +844,16 @@ uart5: serial@fff7f0c000 { - status = "disabled"; - }; - -+ i2c5: i2c@fff7f2c000 { -+ compatible = "thead,th1520-i2c", "snps,designware-i2c"; -+ reg = <0xff 0xf7f2c000 0x0 0x4000>; -+ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clk CLK_I2C5>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - timer4: timer@ffffc33000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33000 0x0 0x14>; --- -2.53.0 - diff --git a/SPECS/linux/0183-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch b/SPECS/linux/0183-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch deleted file mode 100644 index 34135c4498..0000000000 --- a/SPECS/linux/0183-FROMLIST-riscv-dts-thead-Add-Lichee-Pi-4A-IO-expansi.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 0e52d852a2853088113fbb11979bc851ee0f8a6b Mon Sep 17 00:00:00 2001 -From: Emil Renner Berthing -Date: Thu, 7 May 2026 16:17:09 +0800 -Subject: [PATCH 183/269] FROMLIST: riscv: dts: thead: Add Lichee Pi 4A IO - expansions - -Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the -I2C0/1/3 busses. - -Add device tree nodes for them. - -Signed-off-by: Emil Renner Berthing -[Icenowy: added commit description] -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-12-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-lichee-pi-4a.dts | 111 ++++++++++++++++++ - 1 file changed, 111 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -index 4198dbf953f0..354f3893aa8c 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -@@ -16,6 +16,9 @@ aliases { - gpio3 = &gpio3; - gpio4 = &gpio4; - gpio5 = &aogpio; -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2c3 = &i2c3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; -@@ -110,6 +113,76 @@ hdmi_out_con: endpoint { - }; - }; - -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ clock-frequency = <100000>; -+ i2c-sda-hold-time-ns = <300>; -+ i2c-sda-falling-time-ns = <510>; -+ i2c-scl-falling-time-ns = <510>; -+ status = "okay"; -+ -+ ioexp1: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "cam0_dvdd12", -+ "cam0_avdd28", -+ "cam0_dovdd18"; -+ }; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ clock-frequency = <100000>; -+ i2c-sda-hold-time-ns = <300>; -+ i2c-sda-falling-time-ns = <510>; -+ i2c-scl-falling-time-ns = <510>; -+ status = "okay"; -+ -+ ioexp2: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "", -+ "cam0_reset", -+ "cam1_reset", -+ "cam2_reset", -+ "wl_host_wake", -+ "bt_resetn", -+ "", -+ "bt_host_wake"; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+ clock-frequency = <100000>; -+ i2c-sda-hold-time-ns = <300>; -+ i2c-sda-falling-time-ns = <510>; -+ i2c-scl-falling-time-ns = <510>; -+ status = "okay"; -+ -+ ioexp3: gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "tp0_rst", -+ "", -+ "", -+ "vcc5v_usb", -+ "vdd28_tp0", -+ "vdd33_lcd0", -+ "vdd18_lcd0", -+ "lcd0_reset"; -+ }; -+}; -+ - &padctrl0_apsys { - fan_pins: fan-0 { - pwm1-pins { -@@ -123,6 +196,18 @@ pwm1-pins { - }; - }; - -+ i2c3_pins: i2c3-0 { -+ i2c-pins { -+ pins = "I2C3_SCL", "I2C3_SDA"; -+ function = "i2c"; -+ bias-disable; /* external pull-up */ -+ drive-strength = <7>; -+ input-enable; -+ input-schmitt-enable; -+ slew-rate = <0>; -+ }; -+ }; -+ - uart0_pins: uart0-0 { - tx-pins { - pins = "UART0_TXD"; -@@ -146,6 +231,32 @@ rx-pins { - }; - }; - -+&padctrl1_apsys { -+ i2c0_pins: i2c0-0 { -+ i2c-pins { -+ pins = "I2C0_SCL", "I2C0_SDA"; -+ function = "i2c"; -+ bias-disable; /* external pull-up */ -+ drive-strength = <7>; -+ input-enable; -+ input-schmitt-enable; -+ slew-rate = <0>; -+ }; -+ }; -+ -+ i2c1_pins: i2c1-0 { -+ i2c-pins { -+ pins = "I2C1_SCL", "I2C1_SDA"; -+ function = "i2c"; -+ bias-disable; /* external pull-up */ -+ drive-strength = <7>; -+ input-enable; -+ input-schmitt-enable; -+ slew-rate = <0>; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; --- -2.53.0 - diff --git a/SPECS/linux/0183-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch b/SPECS/linux/0183-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch new file mode 100644 index 0000000000..2e34019ffe --- /dev/null +++ b/SPECS/linux/0183-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch @@ -0,0 +1,306 @@ +From d3badbf1b23048af57179cfcec360e6ef0cf7dd6 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Thu, 7 May 2026 16:17:10 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: enable USB3 ports on Lichee + Pi 4A + +The Lichee Pi 4A board features an onboard VIA VL817 hub connected to +the SoC's USB3 as upstream and 4 USB-3.0-capable Type-A ports as +downstream. + +Enable SoC USB3 and the hub on Lichee Pi 4A. + +Signed-off-by: Icenowy Zheng +Link: https://lore.kernel.org/r/20260507081710.4090814-13-zhengxingda@iscas.ac.cn +Signed-off-by: Han Gao +--- + .../dts/thead/th1520-lichee-module-4a.dtsi | 15 ++ + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 231 ++++++++++++++++++ + 2 files changed, 246 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +index 8e76b63e0100..bfda5a6b56b8 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +@@ -20,6 +20,16 @@ memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x2 0x00000000>; + }; ++ ++ /* TODO: Switch to AON regulator when it's available. */ ++ avdd33_usb3: regulator-avdd33-usb3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "AVDD33_USB3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ /* Marked as always on on the schematics */ ++ regulator-always-on; ++ }; + }; + + &osc { +@@ -202,3 +212,8 @@ &sdio0 { + max-frequency = <198000000>; + status = "okay"; + }; ++ ++&usb_phy { ++ avdd33-usb3-supply = <&avdd33_usb3>; ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +index 354f3893aa8c..de38f1f457e6 100644 +--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +@@ -4,6 +4,7 @@ + */ + + #include "th1520-lichee-module-4a.dtsi" ++#include + + / { + model = "Sipeed Lichee Pi 4A"; +@@ -97,6 +98,141 @@ fan: pwm-fan { + cooling-levels = <0 66 196 255>; + }; + ++ hub_5v: regulator-hub-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "HUB_5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&ioexp3 3 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ vcc5v_usb: regulator-vcc5v-usb { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC5V_USB"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ /* ++ * Workaround for Linux currently being not able to power on ++ * Vbus for USB Type-A connectors. ++ */ ++ regulator-always-on; ++ }; ++ ++ connector-usb-a-1 { ++ compatible = "usb-a-connector"; ++ vbus-supply = <&vcc5v_usb>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usb_a_1_hs_ep: endpoint { ++ remote-endpoint = <&hub_hs_port1_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usb_a_1_ss_ep: endpoint { ++ remote-endpoint = <&hub_ss_port1_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ connector-usb-a-2 { ++ compatible = "usb-a-connector"; ++ vbus-supply = <&vcc5v_usb>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usb_a_2_hs_ep: endpoint { ++ remote-endpoint = <&hub_hs_port2_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usb_a_2_ss_ep: endpoint { ++ remote-endpoint = <&hub_ss_port2_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ connector-usb-a-3 { ++ compatible = "usb-a-connector"; ++ vbus-supply = <&vcc5v_usb>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usb_a_3_hs_ep: endpoint { ++ remote-endpoint = <&hub_hs_port3_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usb_a_3_ss_ep: endpoint { ++ remote-endpoint = <&hub_ss_port3_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ connector-usb-a-4 { ++ compatible = "usb-a-connector"; ++ vbus-supply = <&vcc5v_usb>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usb_a_4_hs_ep: endpoint { ++ remote-endpoint = <&hub_hs_port4_ep>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usb_a_4_ss_ep: endpoint { ++ remote-endpoint = <&hub_ss_port4_ep>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&aogpio { ++ /* Route USB2 to the onboard hub for normal operation */ ++ sel-usb-hub-hog { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ }; + }; + + &dpu { +@@ -262,3 +398,98 @@ &uart0 { + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; ++ ++&usb { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub_hs: hub@1 { ++ compatible = "usb2109,2817"; ++ reg = <1>; ++ peer-hub = <&hub_ss>; ++ vdd-supply = <&hub_5v>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ ++ hub_hs_port1_ep: endpoint { ++ remote-endpoint = <&usb_a_1_hs_ep>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ hub_hs_port2_ep: endpoint { ++ remote-endpoint = <&usb_a_2_hs_ep>; ++ }; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ ++ hub_hs_port3_ep: endpoint { ++ remote-endpoint = <&usb_a_3_hs_ep>; ++ }; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ ++ hub_hs_port4_ep: endpoint { ++ remote-endpoint = <&usb_a_4_hs_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ hub_ss: hub@2 { ++ compatible = "usb2109,817"; ++ reg = <2>; ++ peer-hub = <&hub_hs>; ++ vdd-supply = <&hub_5v>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ ++ hub_ss_port1_ep: endpoint { ++ remote-endpoint = <&usb_a_1_ss_ep>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ hub_ss_port2_ep: endpoint { ++ remote-endpoint = <&usb_a_2_ss_ep>; ++ }; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ ++ hub_ss_port3_ep: endpoint { ++ remote-endpoint = <&usb_a_3_ss_ep>; ++ }; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ ++ hub_ss_port4_ep: endpoint { ++ remote-endpoint = <&usb_a_4_ss_ep>; ++ }; ++ }; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux/0184-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch b/SPECS/linux/0184-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch new file mode 100644 index 0000000000..17eee76dbc --- /dev/null +++ b/SPECS/linux/0184-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch @@ -0,0 +1,188 @@ +From f91c86761a676a6def0062c510b6f899f130594d Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Mon, 11 May 2026 13:11:08 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add PMIC + and power infrastructure + +Enable i2c8 and add the connected SpacemiT P1 PMIC with its related regulators +for the board's power infrastructure and voltage regulation support. + +Signed-off-by: Andre Heider +Link: https://lore.kernel.org/r/20260511111116.1109643-2-a.heider@gmail.com +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 144 ++++++++++++++++++ + 1 file changed, 144 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 29e333b670cf..88c35ad1ef2a 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -17,6 +17,7 @@ / { + aliases { + ethernet0 = ð0; + serial0 = &uart0; ++ i2c8 = &i2c8; + }; + + chosen { +@@ -33,6 +34,25 @@ led1 { + default-state = "on"; + }; + }; ++ ++ reg_usb_vbus: regulator-usb-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "USBVBUS"; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_vcc_4v0: regulator-vcc-40v { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC4V0"; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <®_usb_vbus>; ++ }; + }; + + &emmc { +@@ -72,6 +92,130 @@ &pdma { + status = "okay"; + }; + ++&i2c8 { ++ pinctrl-0 = <&i2c8_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ vin1-supply = <®_vcc_4v0>; ++ vin2-supply = <®_vcc_4v0>; ++ vin3-supply = <®_vcc_4v0>; ++ vin4-supply = <®_vcc_4v0>; ++ vin5-supply = <®_vcc_4v0>; ++ vin6-supply = <®_vcc_4v0>; ++ aldoin-supply = <®_vcc_4v0>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; ++ ++ regulators { ++ buck1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ aldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ dldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo7 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + pinctrl-names = "default"; +-- +2.53.0 + diff --git a/SPECS/linux/0184-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch b/SPECS/linux/0184-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch deleted file mode 100644 index 5714a613dd..0000000000 --- a/SPECS/linux/0184-FROMLIST-riscv-dts-thead-enable-USB3-ports-on-Lichee.patch +++ /dev/null @@ -1,306 +0,0 @@ -From 58e325861135f55c3f4ebd4ff1736e24ce4cab23 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Thu, 7 May 2026 16:17:10 +0800 -Subject: [PATCH 184/269] FROMLIST: riscv: dts: thead: enable USB3 ports on - Lichee Pi 4A - -The Lichee Pi 4A board features an onboard VIA VL817 hub connected to -the SoC's USB3 as upstream and 4 USB-3.0-capable Type-A ports as -downstream. - -Enable SoC USB3 and the hub on Lichee Pi 4A. - -Signed-off-by: Icenowy Zheng -Link: https://lore.kernel.org/r/20260507081710.4090814-13-zhengxingda@iscas.ac.cn -Signed-off-by: Han Gao ---- - .../dts/thead/th1520-lichee-module-4a.dtsi | 15 ++ - .../boot/dts/thead/th1520-lichee-pi-4a.dts | 231 ++++++++++++++++++ - 2 files changed, 246 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi -index 8e76b63e0100..bfda5a6b56b8 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi -@@ -20,6 +20,16 @@ memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x2 0x00000000>; - }; -+ -+ /* TODO: Switch to AON regulator when it's available. */ -+ avdd33_usb3: regulator-avdd33-usb3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "AVDD33_USB3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ /* Marked as always on on the schematics */ -+ regulator-always-on; -+ }; - }; - - &osc { -@@ -202,3 +212,8 @@ &sdio0 { - max-frequency = <198000000>; - status = "okay"; - }; -+ -+&usb_phy { -+ avdd33-usb3-supply = <&avdd33_usb3>; -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -index 354f3893aa8c..de38f1f457e6 100644 ---- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts -@@ -4,6 +4,7 @@ - */ - - #include "th1520-lichee-module-4a.dtsi" -+#include - - / { - model = "Sipeed Lichee Pi 4A"; -@@ -97,6 +98,141 @@ fan: pwm-fan { - cooling-levels = <0 66 196 255>; - }; - -+ hub_5v: regulator-hub-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "HUB_5V"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&ioexp3 3 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ }; -+ -+ vcc5v_usb: regulator-vcc5v-usb { -+ compatible = "regulator-fixed"; -+ regulator-name = "VCC5V_USB"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ /* -+ * Workaround for Linux currently being not able to power on -+ * Vbus for USB Type-A connectors. -+ */ -+ regulator-always-on; -+ }; -+ -+ connector-usb-a-1 { -+ compatible = "usb-a-connector"; -+ vbus-supply = <&vcc5v_usb>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usb_a_1_hs_ep: endpoint { -+ remote-endpoint = <&hub_hs_port1_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usb_a_1_ss_ep: endpoint { -+ remote-endpoint = <&hub_ss_port1_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ connector-usb-a-2 { -+ compatible = "usb-a-connector"; -+ vbus-supply = <&vcc5v_usb>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usb_a_2_hs_ep: endpoint { -+ remote-endpoint = <&hub_hs_port2_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usb_a_2_ss_ep: endpoint { -+ remote-endpoint = <&hub_ss_port2_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ connector-usb-a-3 { -+ compatible = "usb-a-connector"; -+ vbus-supply = <&vcc5v_usb>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usb_a_3_hs_ep: endpoint { -+ remote-endpoint = <&hub_hs_port3_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usb_a_3_ss_ep: endpoint { -+ remote-endpoint = <&hub_ss_port3_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ connector-usb-a-4 { -+ compatible = "usb-a-connector"; -+ vbus-supply = <&vcc5v_usb>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ usb_a_4_hs_ep: endpoint { -+ remote-endpoint = <&hub_hs_port4_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ usb_a_4_ss_ep: endpoint { -+ remote-endpoint = <&hub_ss_port4_ep>; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&aogpio { -+ /* Route USB2 to the onboard hub for normal operation */ -+ sel-usb-hub-hog { -+ gpio-hog; -+ gpios = <4 GPIO_ACTIVE_HIGH>; -+ output-high; -+ }; - }; - - &dpu { -@@ -262,3 +398,98 @@ &uart0 { - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; -+ -+&usb { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ hub_hs: hub@1 { -+ compatible = "usb2109,2817"; -+ reg = <1>; -+ peer-hub = <&hub_ss>; -+ vdd-supply = <&hub_5v>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ -+ hub_hs_port1_ep: endpoint { -+ remote-endpoint = <&usb_a_1_hs_ep>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ -+ hub_hs_port2_ep: endpoint { -+ remote-endpoint = <&usb_a_2_hs_ep>; -+ }; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ -+ hub_hs_port3_ep: endpoint { -+ remote-endpoint = <&usb_a_3_hs_ep>; -+ }; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ -+ hub_hs_port4_ep: endpoint { -+ remote-endpoint = <&usb_a_4_hs_ep>; -+ }; -+ }; -+ }; -+ }; -+ -+ hub_ss: hub@2 { -+ compatible = "usb2109,817"; -+ reg = <2>; -+ peer-hub = <&hub_hs>; -+ vdd-supply = <&hub_5v>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@1 { -+ reg = <1>; -+ -+ hub_ss_port1_ep: endpoint { -+ remote-endpoint = <&usb_a_1_ss_ep>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ -+ hub_ss_port2_ep: endpoint { -+ remote-endpoint = <&usb_a_2_ss_ep>; -+ }; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ -+ hub_ss_port3_ep: endpoint { -+ remote-endpoint = <&usb_a_3_ss_ep>; -+ }; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ -+ hub_ss_port4_ep: endpoint { -+ remote-endpoint = <&usb_a_4_ss_ep>; -+ }; -+ }; -+ }; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux/0185-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch b/SPECS/linux/0185-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch new file mode 100644 index 0000000000..d8bfd3b274 --- /dev/null +++ b/SPECS/linux/0185-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch @@ -0,0 +1,97 @@ +From 12a8cc9f5246bcadbedac2fc1996bad23c7d8aad Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Mon, 11 May 2026 13:11:09 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add 24c04 + eeprom + +Enable i2c2 and add the connected 24c04 EEPROM. + +It contains an ONIE TLV table: +=> tlv_eeprom +TLV: 0 +[ 12.162] TlvInfo Header: +[ 12.162] Id String: TlvInfo +[ 12.165] Version: 1 +[ 12.168] Total Length: 58 +[ 12.171] TLV Name Code Len Value +[ 12.175] -------------------- ---- --- ----- +[ 12.179] Product Name 0x21 16 k1-x_MUSE-Pi-Pro +[ 12.184] Serial Number 0x23 17 BPMIMXXXXXXXXXXXX +[ 12.189] Unknown 0x41 1 0x02 +[ 12.194] Base MAC Address 0x24 6 FE:FE:FE:XX:XX:XX +[ 12.199] MAC Addresses 0x2A 2 2 +[ 12.203] CRC-32 0xFE 4 0x395ECD34 +[ 12.207] Checksum is valid. + +(With 0x41 as TLV_CODE_DDR_CSNUM) + +Signed-off-by: Andre Heider +Link: https://lore.kernel.org/r/20260511111116.1109643-3-a.heider@gmail.com +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 35 ++++++++++++++++++- + 1 file changed, 34 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 88c35ad1ef2a..79415d760f16 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -17,6 +17,7 @@ / { + aliases { + ethernet0 = ð0; + serial0 = &uart0; ++ i2c2 = &i2c2; + i2c8 = &i2c8; + }; + +@@ -92,6 +93,38 @@ &pdma { + status = "okay"; + }; + ++&i2c2 { ++ pinctrl-0 = <&i2c2_0_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */ ++ pagesize = <8>; ++ read-only; ++ size = <256>; ++ ++ nvmem-layout { ++ compatible = "onie,tlv-layout"; ++ ++ product-name { ++ }; ++ ++ serial-number { ++ }; ++ ++ mac-address { ++ #nvmem-cell-cells = <1>; ++ }; ++ ++ num-macs { ++ }; ++ }; ++ }; ++}; ++ + &i2c8 { + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; +@@ -126,7 +159,7 @@ buck2 { + regulator-always-on; + }; + +- buck3 { ++ buck3_1v8: buck3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; +-- +2.53.0 + diff --git a/SPECS/linux/0185-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch b/SPECS/linux/0185-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch deleted file mode 100644 index 3453b93aff..0000000000 --- a/SPECS/linux/0185-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-PMIC-a.patch +++ /dev/null @@ -1,188 +0,0 @@ -From d7abfc2f279a779aef9008818f768a37ea7165f8 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:08 +0200 -Subject: [PATCH 185/269] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add - PMIC and power infrastructure - -Enable i2c8 and add the connected SpacemiT P1 PMIC with its related regulators -for the board's power infrastructure and voltage regulation support. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-2-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 144 ++++++++++++++++++ - 1 file changed, 144 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 29e333b670cf..88c35ad1ef2a 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -17,6 +17,7 @@ / { - aliases { - ethernet0 = ð0; - serial0 = &uart0; -+ i2c8 = &i2c8; - }; - - chosen { -@@ -33,6 +34,25 @@ led1 { - default-state = "on"; - }; - }; -+ -+ reg_usb_vbus: regulator-usb-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "USBVBUS"; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_vcc_4v0: regulator-vcc-40v { -+ compatible = "regulator-fixed"; -+ regulator-name = "VCC4V0"; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ }; - }; - - &emmc { -@@ -72,6 +92,130 @@ &pdma { - status = "okay"; - }; - -+&i2c8 { -+ pinctrl-0 = <&i2c8_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin1-supply = <®_vcc_4v0>; -+ vin2-supply = <®_vcc_4v0>; -+ vin3-supply = <®_vcc_4v0>; -+ vin4-supply = <®_vcc_4v0>; -+ vin5-supply = <®_vcc_4v0>; -+ vin6-supply = <®_vcc_4v0>; -+ aldoin-supply = <®_vcc_4v0>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; -+ -+ regulators { -+ buck1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ aldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ dldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo7 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - pinctrl-names = "default"; --- -2.53.0 - diff --git a/SPECS/linux/0186-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch b/SPECS/linux/0186-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch deleted file mode 100644 index a6d86d0898..0000000000 --- a/SPECS/linux/0186-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-24c04-.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 995f8dadb985b9e2b9f46f811c8da53f6417c3dd Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:09 +0200 -Subject: [PATCH 186/269] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add - 24c04 eeprom - -Enable i2c2 and add the connected 24c04 EEPROM. - -It contains an ONIE TLV table: -=> tlv_eeprom -TLV: 0 -[ 12.162] TlvInfo Header: -[ 12.162] Id String: TlvInfo -[ 12.165] Version: 1 -[ 12.168] Total Length: 58 -[ 12.171] TLV Name Code Len Value -[ 12.175] -------------------- ---- --- ----- -[ 12.179] Product Name 0x21 16 k1-x_MUSE-Pi-Pro -[ 12.184] Serial Number 0x23 17 BPMIMXXXXXXXXXXXX -[ 12.189] Unknown 0x41 1 0x02 -[ 12.194] Base MAC Address 0x24 6 FE:FE:FE:XX:XX:XX -[ 12.199] MAC Addresses 0x2A 2 2 -[ 12.203] CRC-32 0xFE 4 0x395ECD34 -[ 12.207] Checksum is valid. - -(With 0x41 as TLV_CODE_DDR_CSNUM) - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-3-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 35 ++++++++++++++++++- - 1 file changed, 34 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 88c35ad1ef2a..79415d760f16 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -17,6 +17,7 @@ / { - aliases { - ethernet0 = ð0; - serial0 = &uart0; -+ i2c2 = &i2c2; - i2c8 = &i2c8; - }; - -@@ -92,6 +93,38 @@ &pdma { - status = "okay"; - }; - -+&i2c2 { -+ pinctrl-0 = <&i2c2_0_cfg>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ -+ eeprom@50 { -+ compatible = "atmel,24c02"; -+ reg = <0x50>; -+ vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */ -+ pagesize = <8>; -+ read-only; -+ size = <256>; -+ -+ nvmem-layout { -+ compatible = "onie,tlv-layout"; -+ -+ product-name { -+ }; -+ -+ serial-number { -+ }; -+ -+ mac-address { -+ #nvmem-cell-cells = <1>; -+ }; -+ -+ num-macs { -+ }; -+ }; -+ }; -+}; -+ - &i2c8 { - pinctrl-0 = <&i2c8_cfg>; - pinctrl-names = "default"; -@@ -126,7 +159,7 @@ buck2 { - regulator-always-on; - }; - -- buck3 { -+ buck3_1v8: buck3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <5000>; --- -2.53.0 - diff --git a/SPECS/linux/0186-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch b/SPECS/linux/0186-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch new file mode 100644 index 0000000000..173fae484b --- /dev/null +++ b/SPECS/linux/0186-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch @@ -0,0 +1,82 @@ +From f0f8b9aeeaae60885412298ddbb582e104d70779 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Mon, 11 May 2026 13:11:10 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable + QSPI and add SPI NOR + +Add the QSPI controller node and describe the attached SPI NOR flash +(Winbond W25Q64FWSSAQ). + +Add a corresponding vendor flash partition layout. + +Signed-off-by: Andre Heider +Link: https://lore.kernel.org/r/20260511111116.1109643-4-a.heider@gmail.com +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 43 ++++++++++++++++++- + 1 file changed, 42 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 79415d760f16..7ebace0e46ed 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -166,7 +166,7 @@ buck3_1v8: buck3 { + regulator-always-on; + }; + +- buck4 { ++ buck4_3v3: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; +@@ -249,6 +249,47 @@ dldo7 { + }; + }; + ++&qspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi_cfg>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <26500000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; ++ vcc-supply = <&buck4_3v3>; /* QSPI_VCC1833 */ ++ m25p,fast-read; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bootinfo@0 { ++ reg = <0x0 0x10000>; ++ }; ++ private@10000 { ++ reg = <0x10000 0x10000>; ++ }; ++ fsbl@20000 { ++ reg = <0x20000 0x40000>; ++ }; ++ env@60000 { ++ reg = <0x60000 0x10000>; ++ }; ++ opensbi@70000 { ++ reg = <0x70000 0x30000>; ++ }; ++ uboot@a00000 { ++ reg = <0xa0000 0x760000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + pinctrl-names = "default"; +-- +2.53.0 + diff --git a/SPECS/linux/0187-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch b/SPECS/linux/0187-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch deleted file mode 100644 index 8f9eb11fd8..0000000000 --- a/SPECS/linux/0187-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-QSP.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 45cce5c72228a0d7f4bd2cbec2e1c727b0a54156 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:10 +0200 -Subject: [PATCH 187/269] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable - QSPI and add SPI NOR - -Add the QSPI controller node and describe the attached SPI NOR flash -(Winbond W25Q64FWSSAQ). - -Add a corresponding vendor flash partition layout. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-4-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 43 ++++++++++++++++++- - 1 file changed, 42 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 79415d760f16..7ebace0e46ed 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -166,7 +166,7 @@ buck3_1v8: buck3 { - regulator-always-on; - }; - -- buck4 { -+ buck4_3v3: buck4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <5000>; -@@ -249,6 +249,47 @@ dldo7 { - }; - }; - -+&qspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qspi_cfg>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <26500000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ vcc-supply = <&buck4_3v3>; /* QSPI_VCC1833 */ -+ m25p,fast-read; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ bootinfo@0 { -+ reg = <0x0 0x10000>; -+ }; -+ private@10000 { -+ reg = <0x10000 0x10000>; -+ }; -+ fsbl@20000 { -+ reg = <0x20000 0x40000>; -+ }; -+ env@60000 { -+ reg = <0x60000 0x10000>; -+ }; -+ opensbi@70000 { -+ reg = <0x70000 0x30000>; -+ }; -+ uboot@a00000 { -+ reg = <0xa0000 0x760000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-0 = <&uart0_2_cfg>; - pinctrl-names = "default"; --- -2.53.0 - diff --git a/SPECS/linux/0187-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch b/SPECS/linux/0187-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch new file mode 100644 index 0000000000..fcb615cf16 --- /dev/null +++ b/SPECS/linux/0187-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch @@ -0,0 +1,97 @@ +From 2358a06c27c3563427c49c2fe6795489a92ac5fe Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Mon, 11 May 2026 13:11:11 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable + USB 3 ports + +Enable the DWC3 USB 3.0 controller, its associated combo_phy (USB 3 PHY) +and usbphy2 (USB 2 PHY) on the MusePi Pro board. + +The board uses a VLI VL817 hub, providing four ports. + +Signed-off-by: Andre Heider +Link: https://lore.kernel.org/r/20260511111116.1109643-5-a.heider@gmail.com +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 54 +++++++++++++++++++ + 1 file changed, 54 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 7ebace0e46ed..9c90c2817ecb 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -54,6 +54,28 @@ reg_vcc_4v0: regulator-vcc-40v { + regulator-always-on; + vin-supply = <®_usb_vbus>; + }; ++ ++ reg_5v_vbus: regulator-5v-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "5V_VBUS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ vin-supply = <®_usb_vbus>; ++ gpio = <&gpio K1_GPIO(79) GPIO_ACTIVE_HIGH>; /* USB3_PWREN */ ++ enable-active-high; ++ }; ++ ++ reg_vcc5v_hub: regulator-vcc5v-hub { ++ compatible = "regulator-fixed"; ++ regulator-name = "VCC5V0_HUB"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ vin-supply = <®_usb_vbus>; ++ gpio = <&gpio K1_GPIO(127) GPIO_ACTIVE_HIGH>; /* HUB_PWREN */ ++ enable-active-high; ++ }; + }; + + &emmc { +@@ -66,6 +88,10 @@ &emmc { + status = "okay"; + }; + ++&combo_phy { ++ status = "okay"; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +@@ -295,3 +321,31 @@ &uart0 { + pinctrl-names = "default"; + status = "okay"; + }; ++ ++&usbphy2 { ++ status = "okay"; ++}; ++ ++&usb_dwc3 { ++ dr_mode = "host"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ vbus-supply = <®_5v_vbus>; ++ status = "okay"; ++ ++ hub_2_0: hub@1 { ++ compatible = "usb2109,2817"; ++ reg = <0x1>; ++ vdd-supply = <®_vcc5v_hub>; ++ peer-hub = <&hub_3_0>; ++ reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ ++ }; ++ ++ hub_3_0: hub@2 { ++ compatible = "usb2109,817"; ++ reg = <0x2>; ++ vdd-supply = <®_vcc5v_hub>; ++ peer-hub = <&hub_2_0>; ++ reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux/0188-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch b/SPECS/linux/0188-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch new file mode 100644 index 0000000000..6d04857fce --- /dev/null +++ b/SPECS/linux/0188-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch @@ -0,0 +1,87 @@ +From abcae120491875c48ac27e34bc7e44032f98aa74 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Mon, 11 May 2026 13:11:12 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable + PCIe ports + +Enable the two PCIe controller along with and their associated PHYs. They +are routed to the M.2 M-key connector and to the PCIe slot. + +Signed-off-by: Andre Heider +Link: https://lore.kernel.org/r/20260511111116.1109643-6-a.heider@gmail.com +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 50 +++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 9c90c2817ecb..2d3e30f0bd80 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -36,6 +36,24 @@ led1 { + }; + }; + ++ pcie_vcc_3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "PCIE_VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <®_usb_vbus>; ++ }; ++ ++ mpcie_vcc_3v3: regulator-mpcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "MPCIE_VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <®_usb_vbus>; ++ }; ++ + reg_usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "USBVBUS"; +@@ -275,6 +293,38 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++}; ++ ++&pcie1 { ++ vpcie3v3-supply = <&pcie_vcc_3v3>; ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&mpcie_vcc_3v3>; ++}; ++ ++&pcie2 { ++ vpcie3v3-supply = <&mpcie_vcc_3v3>; ++ status = "okay"; ++}; ++ + &qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux/0188-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch b/SPECS/linux/0188-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch deleted file mode 100644 index 86e883eaa8..0000000000 --- a/SPECS/linux/0188-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-USB.patch +++ /dev/null @@ -1,97 +0,0 @@ -From d4a6e3d29be27afe5a7e2e108fb4589c09cc706c Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:11 +0200 -Subject: [PATCH 188/269] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable - USB 3 ports - -Enable the DWC3 USB 3.0 controller, its associated combo_phy (USB 3 PHY) -and usbphy2 (USB 2 PHY) on the MusePi Pro board. - -The board uses a VLI VL817 hub, providing four ports. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-5-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 54 +++++++++++++++++++ - 1 file changed, 54 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 7ebace0e46ed..9c90c2817ecb 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -54,6 +54,28 @@ reg_vcc_4v0: regulator-vcc-40v { - regulator-always-on; - vin-supply = <®_usb_vbus>; - }; -+ -+ reg_5v_vbus: regulator-5v-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "5V_VBUS"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ gpio = <&gpio K1_GPIO(79) GPIO_ACTIVE_HIGH>; /* USB3_PWREN */ -+ enable-active-high; -+ }; -+ -+ reg_vcc5v_hub: regulator-vcc5v-hub { -+ compatible = "regulator-fixed"; -+ regulator-name = "VCC5V0_HUB"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ gpio = <&gpio K1_GPIO(127) GPIO_ACTIVE_HIGH>; /* HUB_PWREN */ -+ enable-active-high; -+ }; - }; - - &emmc { -@@ -66,6 +88,10 @@ &emmc { - status = "okay"; - }; - -+&combo_phy { -+ status = "okay"; -+}; -+ - ð0 { - phy-handle = <&rgmii0>; - phy-mode = "rgmii-id"; -@@ -295,3 +321,31 @@ &uart0 { - pinctrl-names = "default"; - status = "okay"; - }; -+ -+&usbphy2 { -+ status = "okay"; -+}; -+ -+&usb_dwc3 { -+ dr_mode = "host"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ vbus-supply = <®_5v_vbus>; -+ status = "okay"; -+ -+ hub_2_0: hub@1 { -+ compatible = "usb2109,2817"; -+ reg = <0x1>; -+ vdd-supply = <®_vcc5v_hub>; -+ peer-hub = <&hub_3_0>; -+ reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ -+ }; -+ -+ hub_3_0: hub@2 { -+ compatible = "usb2109,817"; -+ reg = <0x2>; -+ vdd-supply = <®_vcc5v_hub>; -+ peer-hub = <&hub_2_0>; -+ reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux/0189-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch b/SPECS/linux/0189-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch deleted file mode 100644 index f91edb97ae..0000000000 --- a/SPECS/linux/0189-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-enable-PCI.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 92f38746463cee8bf5ce9e0865395cc42916f4b8 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:12 +0200 -Subject: [PATCH 189/269] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: enable - PCIe ports - -Enable the two PCIe controller along with and their associated PHYs. They -are routed to the M.2 M-key connector and to the PCIe slot. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-6-a.heider@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 50 +++++++++++++++++++ - 1 file changed, 50 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 9c90c2817ecb..2d3e30f0bd80 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -36,6 +36,24 @@ led1 { - }; - }; - -+ pcie_vcc_3v3: regulator-pcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "PCIE_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ }; -+ -+ mpcie_vcc_3v3: regulator-mpcie-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "MPCIE_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ vin-supply = <®_usb_vbus>; -+ }; -+ - reg_usb_vbus: regulator-usb-vbus { - compatible = "regulator-fixed"; - regulator-name = "USBVBUS"; -@@ -275,6 +293,38 @@ dldo7 { - }; - }; - -+&pcie1_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_3_cfg>; -+ status = "okay"; -+}; -+ -+&pcie1_port { -+ phys = <&pcie1_phy>; -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+}; -+ -+&pcie1 { -+ vpcie3v3-supply = <&pcie_vcc_3v3>; -+ status = "okay"; -+}; -+ -+&pcie2_phy { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_4_cfg>; -+ status = "okay"; -+}; -+ -+&pcie2_port { -+ phys = <&pcie2_phy>; -+ vpcie3v3-supply = <&mpcie_vcc_3v3>; -+}; -+ -+&pcie2 { -+ vpcie3v3-supply = <&mpcie_vcc_3v3>; -+ status = "okay"; -+}; -+ - &qspi { - pinctrl-names = "default"; - pinctrl-0 = <&qspi_cfg>; --- -2.53.0 - diff --git a/SPECS/linux/0189-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch b/SPECS/linux/0189-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch new file mode 100644 index 0000000000..4afd6fc002 --- /dev/null +++ b/SPECS/linux/0189-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch @@ -0,0 +1,32 @@ +From 9d245b851f25f33e7aeedcca69e79dcc99eca382 Mon Sep 17 00:00:00 2001 +From: Andre Heider +Date: Mon, 11 May 2026 13:11:13 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: set + default console baud rate + +Allow serial output with the same uboot/opensbi settings so the +console works without providing a cmdline. + +Signed-off-by: Andre Heider +Link: https://lore.kernel.org/r/20260511111116.1109643-7-a.heider@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index 2d3e30f0bd80..c8bf776511c9 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -22,7 +22,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + leds { +-- +2.53.0 + diff --git a/SPECS/linux/0190-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch b/SPECS/linux/0190-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch deleted file mode 100644 index f09e4da77c..0000000000 --- a/SPECS/linux/0190-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-set-defaul.patch +++ /dev/null @@ -1,32 +0,0 @@ -From a6d24b6871f64be6ccd4cf9faadd5ce285d1fe89 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Mon, 11 May 2026 13:11:13 +0200 -Subject: [PATCH 190/269] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: set - default console baud rate - -Allow serial output with the same uboot/opensbi settings so the -console works without providing a cmdline. - -Signed-off-by: Andre Heider -Link: https://lore.kernel.org/r/20260511111116.1109643-7-a.heider@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index 2d3e30f0bd80..c8bf776511c9 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -22,7 +22,7 @@ aliases { - }; - - chosen { -- stdout-path = "serial0"; -+ stdout-path = "serial0:115200n8"; - }; - - leds { --- -2.53.0 - diff --git a/SPECS/linux/0190-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch b/SPECS/linux/0190-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch new file mode 100644 index 0000000000..68f84796b6 --- /dev/null +++ b/SPECS/linux/0190-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch @@ -0,0 +1,851 @@ +From ad5777851494c5ce59eea0ddbebec62813ed07b0 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Thu, 21 May 2026 00:24:41 +0000 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add pwm support + +Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents +the pinctrl info which would easily help to enable them in future. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260521-04-k3-pwm-dts-v4-1-04d4de0f2fc8@kernel.org +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 590 +++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 220 +++++++ + 2 files changed, 810 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 23899d3f308a..252c64af76fe 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -56,6 +56,596 @@ i2c8-pins { + }; + }; + ++ /omit-if-no-ref/ ++ pwm0_0_cfg: pwm0-0-cfg { ++ pwm0-0-pins { ++ pinmux = ; /* pwm0 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm0_1_cfg: pwm0-1-cfg { ++ pwm0-1-pins { ++ pinmux = ; /* pwm0 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_0_cfg: pwm1-0-cfg { ++ pwm1-0-pins { ++ pinmux = ; /* pwm1 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_1_cfg: pwm1-1-cfg { ++ pwm1-1-pins { ++ pinmux = ; /* pwm1 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_2_cfg: pwm1-2-cfg { ++ pwm1-2-pins { ++ pinmux = ; /* pwm1 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_0_cfg: pwm2-0-cfg { ++ pwm2-0-pins { ++ pinmux = ; /* pwm2 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_1_cfg: pwm2-1-cfg { ++ pwm2-1-pins { ++ pinmux = ; /* pwm2 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_2_cfg: pwm2-2-cfg { ++ pwm2-2-pins { ++ pinmux = ; /* pwm2 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_3_cfg: pwm2-3-cfg { ++ pwm2-3-pins { ++ pinmux = ; /* pwm2 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_0_cfg: pwm3-0-cfg { ++ pwm3-0-pins { ++ pinmux = ; /* pwm3 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_1_cfg: pwm3-1-cfg { ++ pwm3-1-pins { ++ pinmux = ; /* pwm3 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_2_cfg: pwm3-2-cfg { ++ pwm3-2-pins { ++ pinmux = ; /* pwm3 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_3_cfg: pwm3-3-cfg { ++ pwm3-3-pins { ++ pinmux = ; /* pwm3 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm4_0_cfg: pwm4-0-cfg { ++ pwm4-0-pins { ++ pinmux = ; /* pwm4 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm4_1_cfg: pwm4-1-cfg { ++ pwm4-1-pins { ++ pinmux = ; /* pwm4 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm4_2_cfg: pwm4-2-cfg { ++ pwm4-2-pins { ++ pinmux = ; /* pwm4 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5_0_cfg: pwm5-0-cfg { ++ pwm5-0-pins { ++ pinmux = ; /* pwm5 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5_1_cfg: pwm5-1-cfg { ++ pwm5-1-pins { ++ pinmux = ; /* pwm5 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5_2_cfg: pwm5-2-cfg { ++ pwm5-2-pins { ++ pinmux = ; /* pwm5 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm6_0_cfg: pwm6-0-cfg { ++ pwm6-0-pins { ++ pinmux = ; /* pwm6 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm6_1_cfg: pwm6-1-cfg { ++ pwm6-1-pins { ++ pinmux = ; /* pwm6 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm6_2_cfg: pwm6-2-cfg { ++ pwm6-2-pins { ++ pinmux = ; /* pwm6 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7_0_cfg: pwm7-0-cfg { ++ pwm7-0-pins { ++ pinmux = ; /* pwm7 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7_1_cfg: pwm7-1-cfg { ++ pwm7-1-pins { ++ pinmux = ; /* pwm7 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm7_2_cfg: pwm7-2-cfg { ++ pwm7-2-pins { ++ pinmux = ; /* pwm7 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8_0_cfg: pwm8-0-cfg { ++ pwm8-0-pins { ++ pinmux = ; /* pwm8 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8_1_cfg: pwm8-1-cfg { ++ pwm8-1-pins { ++ pinmux = ; /* pwm8 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm8_2_cfg: pwm8-2-cfg { ++ pwm8-2-pins { ++ pinmux = ; /* pwm8 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9_0_cfg: pwm9-0-cfg { ++ pwm9-0-pins { ++ pinmux = ; /* pwm9 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9_1_cfg: pwm9-1-cfg { ++ pwm9-1-pins { ++ pinmux = ; /* pwm9 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm9_2_cfg: pwm9-2-cfg { ++ pwm9-2-pins { ++ pinmux = ; /* pwm9 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10_0_cfg: pwm10-0-cfg { ++ pwm10-0-pins { ++ pinmux = ; /* pwm10 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10_1_cfg: pwm10-1-cfg { ++ pwm10-1-pins { ++ pinmux = ; /* pwm10 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm10_2_cfg: pwm10-2-cfg { ++ pwm10-2-pins { ++ pinmux = ; /* pwm10 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm11_0_cfg: pwm11-0-cfg { ++ pwm11-0-pins { ++ pinmux = ; /* pwm11 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm11_1_cfg: pwm11-1-cfg { ++ pwm11-1-pins { ++ pinmux = ; /* pwm11 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm12_0_cfg: pwm12-0-cfg { ++ pwm12-0-pins { ++ pinmux = ; /* pwm12 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm12_1_cfg: pwm12-1-cfg { ++ pwm12-1-pins { ++ pinmux = ; /* pwm12 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13_0_cfg: pwm13-0-cfg { ++ pwm13-0-pins { ++ pinmux = ; /* pwm13 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13_1_cfg: pwm13-1-cfg { ++ pwm13-1-pins { ++ pinmux = ; /* pwm13 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm13_2_cfg: pwm13-2-cfg { ++ pwm13-2-pins { ++ pinmux = ; /* pwm13 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14_0_cfg: pwm14-0-cfg { ++ pwm14-0-pins { ++ pinmux = ; /* pwm14 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14_1_cfg: pwm14-1-cfg { ++ pwm14-1-pins { ++ pinmux = ; /* pwm14 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm14_2_cfg: pwm14-2-cfg { ++ pwm14-2-pins { ++ pinmux = ; /* pwm14 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15_0_cfg: pwm15-0-cfg { ++ pwm15-0-pins { ++ pinmux = ; /* pwm15 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15_1_cfg: pwm15-1-cfg { ++ pwm15-1-pins { ++ pinmux = ; /* pwm15 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm15_2_cfg: pwm15-2-cfg { ++ pwm15-2-pins { ++ pinmux = ; /* pwm15 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm16_0_cfg: pwm16-0-cfg { ++ pwm16-0-pins { ++ pinmux = ; /* pwm16 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm16_1_cfg: pwm16-1-cfg { ++ pwm16-1-pins { ++ pinmux = ; /* pwm16 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm16_2_cfg: pwm16-2-cfg { ++ pwm16-2-pins { ++ pinmux = ; /* pwm16 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm17_0_cfg: pwm17-0-cfg { ++ pwm17-0-pins { ++ pinmux = ; /* pwm17 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm17_1_cfg: pwm17-1-cfg { ++ pwm17-1-pins { ++ pinmux = ; /* pwm17 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm17_2_cfg: pwm17-2-cfg { ++ pwm17-2-pins { ++ pinmux = ; /* pwm17 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm18_0_cfg: pwm18-0-cfg { ++ pwm18-0-pins { ++ pinmux = ; /* pwm18 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm18_1_cfg: pwm18-1-cfg { ++ pwm18-1-pins { ++ pinmux = ; /* pwm18 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm18_2_cfg: pwm18-2-cfg { ++ pwm18-2-pins { ++ pinmux = ; /* pwm18 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm19_0_cfg: pwm19-0-cfg { ++ pwm19-0-pins { ++ pinmux = ; /* pwm19 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm19_1_cfg: pwm19-1-cfg { ++ pwm19-1-pins { ++ pinmux = ; /* pwm19 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm19_2_cfg: pwm19-2-cfg { ++ pwm19-2-pins { ++ pinmux = ; /* pwm19 */ ++ ++ bias-pull-up = <0>; ++ drive-strength = <25>; ++ }; ++ }; ++ + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 0408929f7949..a336de5f3d94 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -809,6 +809,226 @@ i2c8: i2c@d401d800 { + status = "disabled"; + }; + ++ pwm0: pwm@d401a000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401a000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM0>, ++ <&syscon_apbc CLK_APBC_PWM0_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM0>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm1: pwm@d401a400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401a400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM1>, ++ <&syscon_apbc CLK_APBC_PWM1_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM1>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm2: pwm@d401a800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401a800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM2>, ++ <&syscon_apbc CLK_APBC_PWM2_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM2>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm3: pwm@d401ac00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401ac00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM3>, ++ <&syscon_apbc CLK_APBC_PWM3_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM3>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm4: pwm@d401b000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401b000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM4>, ++ <&syscon_apbc CLK_APBC_PWM4_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM4>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm5: pwm@d401b400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401b400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM5>, ++ <&syscon_apbc CLK_APBC_PWM5_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM5>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm6: pwm@d401b800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401b800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM6>, ++ <&syscon_apbc CLK_APBC_PWM6_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM6>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm7: pwm@d401bc00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd401bc00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM7>, ++ <&syscon_apbc CLK_APBC_PWM7_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM7>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm8: pwm@d4020000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4020000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM8>, ++ <&syscon_apbc CLK_APBC_PWM8_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM8>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm9: pwm@d4020400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4020400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM9>, ++ <&syscon_apbc CLK_APBC_PWM9_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM9>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm10: pwm@d4020800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4020800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM10>, ++ <&syscon_apbc CLK_APBC_PWM10_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM10>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm11: pwm@d4020c00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4020c00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM11>, ++ <&syscon_apbc CLK_APBC_PWM11_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM11>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm12: pwm@d4021000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4021000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM12>, ++ <&syscon_apbc CLK_APBC_PWM12_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM12>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm13: pwm@d4021400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4021400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM13>, ++ <&syscon_apbc CLK_APBC_PWM13_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM13>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm14: pwm@d4021800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4021800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM14>, ++ <&syscon_apbc CLK_APBC_PWM14_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM14>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm15: pwm@d4021c00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4021c00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM15>, ++ <&syscon_apbc CLK_APBC_PWM15_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM15>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm16: pwm@d4022000 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4022000 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM16>, ++ <&syscon_apbc CLK_APBC_PWM16_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM16>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm17: pwm@d4022400 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4022400 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM17>, ++ <&syscon_apbc CLK_APBC_PWM17_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM17>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm18: pwm@d4022800 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4022800 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM18>, ++ <&syscon_apbc CLK_APBC_PWM18_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM18>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm19: pwm@d4022c00 { ++ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; ++ reg = <0x0 0xd4022c00 0x0 0x10>; ++ clocks = <&syscon_apbc CLK_APBC_PWM19>, ++ <&syscon_apbc CLK_APBC_PWM19_BUS>; ++ clock-names = "func", "bus"; ++ resets = <&syscon_apbc RESET_APBC_PWM19>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k3-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux/0191-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch b/SPECS/linux/0191-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch deleted file mode 100644 index c675ba835a..0000000000 --- a/SPECS/linux/0191-FROMLIST-riscv-dts-spacemit-k3-Add-pwm-support.patch +++ /dev/null @@ -1,851 +0,0 @@ -From 7b577c9368e036c3b216da7cc99ea8d358d245af Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Thu, 21 May 2026 00:24:41 +0000 -Subject: [PATCH 191/269] FROMLIST: riscv: dts: spacemit: k3: Add pwm support - -Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents -the pinctrl info which would easily help to enable them in future. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260521-04-k3-pwm-dts-v4-1-04d4de0f2fc8@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 590 +++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 220 +++++++ - 2 files changed, 810 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index 23899d3f308a..252c64af76fe 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -56,6 +56,596 @@ i2c8-pins { - }; - }; - -+ /omit-if-no-ref/ -+ pwm0_0_cfg: pwm0-0-cfg { -+ pwm0-0-pins { -+ pinmux = ; /* pwm0 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm0_1_cfg: pwm0-1-cfg { -+ pwm0-1-pins { -+ pinmux = ; /* pwm0 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1_0_cfg: pwm1-0-cfg { -+ pwm1-0-pins { -+ pinmux = ; /* pwm1 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1_1_cfg: pwm1-1-cfg { -+ pwm1-1-pins { -+ pinmux = ; /* pwm1 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm1_2_cfg: pwm1-2-cfg { -+ pwm1-2-pins { -+ pinmux = ; /* pwm1 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_0_cfg: pwm2-0-cfg { -+ pwm2-0-pins { -+ pinmux = ; /* pwm2 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_1_cfg: pwm2-1-cfg { -+ pwm2-1-pins { -+ pinmux = ; /* pwm2 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_2_cfg: pwm2-2-cfg { -+ pwm2-2-pins { -+ pinmux = ; /* pwm2 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm2_3_cfg: pwm2-3-cfg { -+ pwm2-3-pins { -+ pinmux = ; /* pwm2 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_0_cfg: pwm3-0-cfg { -+ pwm3-0-pins { -+ pinmux = ; /* pwm3 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_1_cfg: pwm3-1-cfg { -+ pwm3-1-pins { -+ pinmux = ; /* pwm3 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_2_cfg: pwm3-2-cfg { -+ pwm3-2-pins { -+ pinmux = ; /* pwm3 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm3_3_cfg: pwm3-3-cfg { -+ pwm3-3-pins { -+ pinmux = ; /* pwm3 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm4_0_cfg: pwm4-0-cfg { -+ pwm4-0-pins { -+ pinmux = ; /* pwm4 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm4_1_cfg: pwm4-1-cfg { -+ pwm4-1-pins { -+ pinmux = ; /* pwm4 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm4_2_cfg: pwm4-2-cfg { -+ pwm4-2-pins { -+ pinmux = ; /* pwm4 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm5_0_cfg: pwm5-0-cfg { -+ pwm5-0-pins { -+ pinmux = ; /* pwm5 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm5_1_cfg: pwm5-1-cfg { -+ pwm5-1-pins { -+ pinmux = ; /* pwm5 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm5_2_cfg: pwm5-2-cfg { -+ pwm5-2-pins { -+ pinmux = ; /* pwm5 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm6_0_cfg: pwm6-0-cfg { -+ pwm6-0-pins { -+ pinmux = ; /* pwm6 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm6_1_cfg: pwm6-1-cfg { -+ pwm6-1-pins { -+ pinmux = ; /* pwm6 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm6_2_cfg: pwm6-2-cfg { -+ pwm6-2-pins { -+ pinmux = ; /* pwm6 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm7_0_cfg: pwm7-0-cfg { -+ pwm7-0-pins { -+ pinmux = ; /* pwm7 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm7_1_cfg: pwm7-1-cfg { -+ pwm7-1-pins { -+ pinmux = ; /* pwm7 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm7_2_cfg: pwm7-2-cfg { -+ pwm7-2-pins { -+ pinmux = ; /* pwm7 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm8_0_cfg: pwm8-0-cfg { -+ pwm8-0-pins { -+ pinmux = ; /* pwm8 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm8_1_cfg: pwm8-1-cfg { -+ pwm8-1-pins { -+ pinmux = ; /* pwm8 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm8_2_cfg: pwm8-2-cfg { -+ pwm8-2-pins { -+ pinmux = ; /* pwm8 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm9_0_cfg: pwm9-0-cfg { -+ pwm9-0-pins { -+ pinmux = ; /* pwm9 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm9_1_cfg: pwm9-1-cfg { -+ pwm9-1-pins { -+ pinmux = ; /* pwm9 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm9_2_cfg: pwm9-2-cfg { -+ pwm9-2-pins { -+ pinmux = ; /* pwm9 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm10_0_cfg: pwm10-0-cfg { -+ pwm10-0-pins { -+ pinmux = ; /* pwm10 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm10_1_cfg: pwm10-1-cfg { -+ pwm10-1-pins { -+ pinmux = ; /* pwm10 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm10_2_cfg: pwm10-2-cfg { -+ pwm10-2-pins { -+ pinmux = ; /* pwm10 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm11_0_cfg: pwm11-0-cfg { -+ pwm11-0-pins { -+ pinmux = ; /* pwm11 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm11_1_cfg: pwm11-1-cfg { -+ pwm11-1-pins { -+ pinmux = ; /* pwm11 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm12_0_cfg: pwm12-0-cfg { -+ pwm12-0-pins { -+ pinmux = ; /* pwm12 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm12_1_cfg: pwm12-1-cfg { -+ pwm12-1-pins { -+ pinmux = ; /* pwm12 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm13_0_cfg: pwm13-0-cfg { -+ pwm13-0-pins { -+ pinmux = ; /* pwm13 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm13_1_cfg: pwm13-1-cfg { -+ pwm13-1-pins { -+ pinmux = ; /* pwm13 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm13_2_cfg: pwm13-2-cfg { -+ pwm13-2-pins { -+ pinmux = ; /* pwm13 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm14_0_cfg: pwm14-0-cfg { -+ pwm14-0-pins { -+ pinmux = ; /* pwm14 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm14_1_cfg: pwm14-1-cfg { -+ pwm14-1-pins { -+ pinmux = ; /* pwm14 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm14_2_cfg: pwm14-2-cfg { -+ pwm14-2-pins { -+ pinmux = ; /* pwm14 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm15_0_cfg: pwm15-0-cfg { -+ pwm15-0-pins { -+ pinmux = ; /* pwm15 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm15_1_cfg: pwm15-1-cfg { -+ pwm15-1-pins { -+ pinmux = ; /* pwm15 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm15_2_cfg: pwm15-2-cfg { -+ pwm15-2-pins { -+ pinmux = ; /* pwm15 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm16_0_cfg: pwm16-0-cfg { -+ pwm16-0-pins { -+ pinmux = ; /* pwm16 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm16_1_cfg: pwm16-1-cfg { -+ pwm16-1-pins { -+ pinmux = ; /* pwm16 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm16_2_cfg: pwm16-2-cfg { -+ pwm16-2-pins { -+ pinmux = ; /* pwm16 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm17_0_cfg: pwm17-0-cfg { -+ pwm17-0-pins { -+ pinmux = ; /* pwm17 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm17_1_cfg: pwm17-1-cfg { -+ pwm17-1-pins { -+ pinmux = ; /* pwm17 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm17_2_cfg: pwm17-2-cfg { -+ pwm17-2-pins { -+ pinmux = ; /* pwm17 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm18_0_cfg: pwm18-0-cfg { -+ pwm18-0-pins { -+ pinmux = ; /* pwm18 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm18_1_cfg: pwm18-1-cfg { -+ pwm18-1-pins { -+ pinmux = ; /* pwm18 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm18_2_cfg: pwm18-2-cfg { -+ pwm18-2-pins { -+ pinmux = ; /* pwm18 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm19_0_cfg: pwm19-0-cfg { -+ pwm19-0-pins { -+ pinmux = ; /* pwm19 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm19_1_cfg: pwm19-1-cfg { -+ pwm19-1-pins { -+ pinmux = ; /* pwm19 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ -+ /omit-if-no-ref/ -+ pwm19_2_cfg: pwm19-2-cfg { -+ pwm19-2-pins { -+ pinmux = ; /* pwm19 */ -+ -+ bias-pull-up = <0>; -+ drive-strength = <25>; -+ }; -+ }; -+ - /omit-if-no-ref/ - uart0_0_cfg: uart0-0-cfg { - uart0-0-pins { -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 0408929f7949..a336de5f3d94 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -809,6 +809,226 @@ i2c8: i2c@d401d800 { - status = "disabled"; - }; - -+ pwm0: pwm@d401a000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401a000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM0>, -+ <&syscon_apbc CLK_APBC_PWM0_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM0>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm1: pwm@d401a400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401a400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM1>, -+ <&syscon_apbc CLK_APBC_PWM1_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM1>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm2: pwm@d401a800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401a800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM2>, -+ <&syscon_apbc CLK_APBC_PWM2_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM2>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm3: pwm@d401ac00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401ac00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM3>, -+ <&syscon_apbc CLK_APBC_PWM3_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM3>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm4: pwm@d401b000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401b000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM4>, -+ <&syscon_apbc CLK_APBC_PWM4_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM4>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm5: pwm@d401b400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401b400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM5>, -+ <&syscon_apbc CLK_APBC_PWM5_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM5>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm6: pwm@d401b800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401b800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM6>, -+ <&syscon_apbc CLK_APBC_PWM6_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM6>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm7: pwm@d401bc00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd401bc00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM7>, -+ <&syscon_apbc CLK_APBC_PWM7_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM7>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm8: pwm@d4020000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4020000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM8>, -+ <&syscon_apbc CLK_APBC_PWM8_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM8>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm9: pwm@d4020400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4020400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM9>, -+ <&syscon_apbc CLK_APBC_PWM9_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM9>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm10: pwm@d4020800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4020800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM10>, -+ <&syscon_apbc CLK_APBC_PWM10_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM10>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm11: pwm@d4020c00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4020c00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM11>, -+ <&syscon_apbc CLK_APBC_PWM11_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM11>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm12: pwm@d4021000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4021000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM12>, -+ <&syscon_apbc CLK_APBC_PWM12_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM12>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm13: pwm@d4021400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4021400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM13>, -+ <&syscon_apbc CLK_APBC_PWM13_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM13>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm14: pwm@d4021800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4021800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM14>, -+ <&syscon_apbc CLK_APBC_PWM14_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM14>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm15: pwm@d4021c00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4021c00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM15>, -+ <&syscon_apbc CLK_APBC_PWM15_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM15>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm16: pwm@d4022000 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4022000 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM16>, -+ <&syscon_apbc CLK_APBC_PWM16_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM16>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm17: pwm@d4022400 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4022400 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM17>, -+ <&syscon_apbc CLK_APBC_PWM17_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM17>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm18: pwm@d4022800 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4022800 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM18>, -+ <&syscon_apbc CLK_APBC_PWM18_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM18>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm19: pwm@d4022c00 { -+ compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; -+ reg = <0x0 0xd4022c00 0x0 0x10>; -+ clocks = <&syscon_apbc CLK_APBC_PWM19>, -+ <&syscon_apbc CLK_APBC_PWM19_BUS>; -+ clock-names = "func", "bus"; -+ resets = <&syscon_apbc RESET_APBC_PWM19>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ - pinctrl: pinctrl@d401e000 { - compatible = "spacemit,k3-pinctrl"; - reg = <0x0 0xd401e000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux/0191-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch b/SPECS/linux/0191-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch new file mode 100644 index 0000000000..7ac9015ac8 --- /dev/null +++ b/SPECS/linux/0191-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch @@ -0,0 +1,56 @@ +From a773430e58defdd7194bab2ab807bfb82c0c559f Mon Sep 17 00:00:00 2001 +From: Thorsten Blum +Date: Sun, 10 May 2026 18:54:21 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: use sysfs_emit in cpu_show_ghostwrite + +Replace sprintf() with sysfs_emit() in cpu_show_ghostwrite(), which is +preferred for formatting sysfs output because it provides safer bounds +checking. + +While the current code only emits fixed strings that fit easily within +PAGE_SIZE, use sysfs_emit() to follow secure coding best practices. + +Signed-off-by: Thorsten Blum +Link: https://lore.kernel.org/r/20260510165420.109453-3-thorsten.blum@linux.dev +Signed-off-by: Han Gao +--- + arch/riscv/kernel/bugs.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/kernel/bugs.c b/arch/riscv/kernel/bugs.c +index 3655fe7d678c..e5758e3f1c7e 100644 +--- a/arch/riscv/kernel/bugs.c ++++ b/arch/riscv/kernel/bugs.c +@@ -5,7 +5,7 @@ + + #include + #include +-#include ++#include + + #include + #include +@@ -46,15 +46,15 @@ ssize_t cpu_show_ghostwrite(struct device *dev, struct device_attribute *attr, c + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) { + switch (ghostwrite_state) { + case UNAFFECTED: +- return sprintf(buf, "Not affected\n"); ++ return sysfs_emit(buf, "Not affected\n"); + case MITIGATED: +- return sprintf(buf, "Mitigation: xtheadvector disabled\n"); ++ return sysfs_emit(buf, "Mitigation: xtheadvector disabled\n"); + case VULNERABLE: + fallthrough; + default: +- return sprintf(buf, "Vulnerable\n"); ++ return sysfs_emit(buf, "Vulnerable\n"); + } +- } else { +- return sprintf(buf, "Not affected\n"); + } ++ ++ return sysfs_emit(buf, "Not affected\n"); + } +-- +2.53.0 + diff --git a/SPECS/linux/0192-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch b/SPECS/linux/0192-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch new file mode 100644 index 0000000000..04ed2e0b9c --- /dev/null +++ b/SPECS/linux/0192-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch @@ -0,0 +1,51 @@ +From 44f4371399644fae2ccd90247b656bb6cc6fc81b Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 11 May 2026 02:59:09 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Switch to pll2_d6 as parent + for PCIe clock + +According to SpacemiT updated docs, the PCIe master and slave clock's +parent is the pll2_d6 clock, so fix it. + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-1-c9a5e563bab3@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index bb8b75bdbdb3..1a53b14739fe 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -947,16 +947,16 @@ static const struct clk_parent_data edp1_pclk_parents[] = { + }; + CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); + +-CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); +-CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); +-CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); +-CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); +-CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); +-CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); +-CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); +-CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); +-CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); +-CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); ++CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); ++CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); ++CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); ++CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); ++CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); ++CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); ++CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); ++CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); ++CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); ++CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); + + static const struct clk_parent_data emac_1588_parents[] = { + CCU_PARENT_NAME(vctcxo_24m), +-- +2.53.0 + diff --git a/SPECS/linux/0192-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch b/SPECS/linux/0192-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch deleted file mode 100644 index 481e2735ae..0000000000 --- a/SPECS/linux/0192-FROMLIST-riscv-use-sysfs_emit-in-cpu_show_ghostwrite.patch +++ /dev/null @@ -1,57 +0,0 @@ -From bbc7a70aa1948aca2a192478199bbf79ef230f71 Mon Sep 17 00:00:00 2001 -From: Thorsten Blum -Date: Sun, 10 May 2026 18:54:21 +0200 -Subject: [PATCH 192/269] FROMLIST: riscv: use sysfs_emit in - cpu_show_ghostwrite - -Replace sprintf() with sysfs_emit() in cpu_show_ghostwrite(), which is -preferred for formatting sysfs output because it provides safer bounds -checking. - -While the current code only emits fixed strings that fit easily within -PAGE_SIZE, use sysfs_emit() to follow secure coding best practices. - -Signed-off-by: Thorsten Blum -Link: https://lore.kernel.org/r/20260510165420.109453-3-thorsten.blum@linux.dev -Signed-off-by: Han Gao ---- - arch/riscv/kernel/bugs.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/kernel/bugs.c b/arch/riscv/kernel/bugs.c -index 3655fe7d678c..e5758e3f1c7e 100644 ---- a/arch/riscv/kernel/bugs.c -+++ b/arch/riscv/kernel/bugs.c -@@ -5,7 +5,7 @@ - - #include - #include --#include -+#include - - #include - #include -@@ -46,15 +46,15 @@ ssize_t cpu_show_ghostwrite(struct device *dev, struct device_attribute *attr, c - if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) { - switch (ghostwrite_state) { - case UNAFFECTED: -- return sprintf(buf, "Not affected\n"); -+ return sysfs_emit(buf, "Not affected\n"); - case MITIGATED: -- return sprintf(buf, "Mitigation: xtheadvector disabled\n"); -+ return sysfs_emit(buf, "Mitigation: xtheadvector disabled\n"); - case VULNERABLE: - fallthrough; - default: -- return sprintf(buf, "Vulnerable\n"); -+ return sysfs_emit(buf, "Vulnerable\n"); - } -- } else { -- return sprintf(buf, "Not affected\n"); - } -+ -+ return sysfs_emit(buf, "Not affected\n"); - } --- -2.53.0 - diff --git a/SPECS/linux/0193-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch b/SPECS/linux/0193-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch new file mode 100644 index 0000000000..8179e0b767 --- /dev/null +++ b/SPECS/linux/0193-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch @@ -0,0 +1,35 @@ +From bbe98d4268d3ea7a6409b6f5e7c3d4c623dae6e5 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 11 May 2026 02:59:10 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Fix PCIe clock register + offset + +The offset of PCIe Clock CTRL register for port B and C controller was +wrongly swapped, correct it here. + +Fixes: 091d19cc2401 ("clk: spacemit: k3: extract common header") +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-2-c9a5e563bab3@kernel.org +Signed-off-by: Han Gao +--- + include/soc/spacemit/k3-syscon.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h +index 0299bea065a0..a68255dd641f 100644 +--- a/include/soc/spacemit/k3-syscon.h ++++ b/include/soc/spacemit/k3-syscon.h +@@ -168,8 +168,8 @@ + #define APMU_CPU_C2_CLK_CTRL 0x394 + #define APMU_CPU_C3_CLK_CTRL 0x208 + #define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 +-#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 +-#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 ++#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0 ++#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8 + #define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 + #define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 + #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 +-- +2.53.0 + diff --git a/SPECS/linux/0193-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch b/SPECS/linux/0193-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch deleted file mode 100644 index 4bb975bf93..0000000000 --- a/SPECS/linux/0193-FROMLIST-clk-spacemit-k3-Switch-to-pll2_d6-as-parent.patch +++ /dev/null @@ -1,51 +0,0 @@ -From d6d6ac90557ca0f05b488e7b1611d103d382da16 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 11 May 2026 02:59:09 +0000 -Subject: [PATCH 193/269] FROMLIST: clk: spacemit: k3: Switch to pll2_d6 as - parent for PCIe clock - -According to SpacemiT updated docs, the PCIe master and slave clock's -parent is the pll2_d6 clock, so fix it. - -Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-1-c9a5e563bab3@kernel.org -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 20 ++++++++++---------- - 1 file changed, 10 insertions(+), 10 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index bb8b75bdbdb3..1a53b14739fe 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -947,16 +947,16 @@ static const struct clk_parent_data edp1_pclk_parents[] = { - }; - CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); - --CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); --CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); --CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); --CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); --CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); --CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); --CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); --CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); --CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); --CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); -+CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); -+CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); -+CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); -+CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); -+CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); -+CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); -+CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); -+CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); -+CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); -+CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); - - static const struct clk_parent_data emac_1588_parents[] = { - CCU_PARENT_NAME(vctcxo_24m), --- -2.53.0 - diff --git a/SPECS/linux/0194-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch b/SPECS/linux/0194-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch deleted file mode 100644 index 633f4c4a66..0000000000 --- a/SPECS/linux/0194-FROMLIST-clk-spacemit-k3-Fix-PCIe-clock-register-off.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 70b9b0ec24333ca936dc7801bd41a024638df5f1 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 11 May 2026 02:59:10 +0000 -Subject: [PATCH 194/269] FROMLIST: clk: spacemit: k3: Fix PCIe clock register - offset - -The offset of PCIe Clock CTRL register for port B and C controller was -wrongly swapped, correct it here. - -Fixes: 091d19cc2401 ("clk: spacemit: k3: extract common header") -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-2-c9a5e563bab3@kernel.org -Signed-off-by: Han Gao ---- - include/soc/spacemit/k3-syscon.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h -index 0299bea065a0..a68255dd641f 100644 ---- a/include/soc/spacemit/k3-syscon.h -+++ b/include/soc/spacemit/k3-syscon.h -@@ -168,8 +168,8 @@ - #define APMU_CPU_C2_CLK_CTRL 0x394 - #define APMU_CPU_C3_CLK_CTRL 0x208 - #define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 --#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 --#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 -+#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0 -+#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8 - #define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 - #define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 - #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 --- -2.53.0 - diff --git a/SPECS/linux/0194-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch b/SPECS/linux/0194-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch new file mode 100644 index 0000000000..7a11430d66 --- /dev/null +++ b/SPECS/linux/0194-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch @@ -0,0 +1,34 @@ +From 019132af91999a1420a1c23e25749db9251e9670 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 11 May 2026 02:59:11 +0000 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: soc: spacemit: k3: Add PCIe DBI + clock IDs + +Add clock IDs of PCIe DBI (Data Bus Interface) clock. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-3-c9a5e563bab3@kernel.org +Signed-off-by: Han Gao +--- + include/dt-bindings/clock/spacemit,k3-clocks.h | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h +index b22336f3ae40..dfae52547cda 100644 +--- a/include/dt-bindings/clock/spacemit,k3-clocks.h ++++ b/include/dt-bindings/clock/spacemit,k3-clocks.h +@@ -380,6 +380,11 @@ + #define CLK_APMU_ISIM_VCLK1 86 + #define CLK_APMU_ISIM_VCLK2 87 + #define CLK_APMU_ISIM_VCLK3 88 ++#define CLK_APMU_PCIE_PORTA_DBI 89 ++#define CLK_APMU_PCIE_PORTB_DBI 90 ++#define CLK_APMU_PCIE_PORTC_DBI 91 ++#define CLK_APMU_PCIE_PORTD_DBI 92 ++#define CLK_APMU_PCIE_PORTE_DBI 93 + + /* DCIU clocks */ + #define CLK_DCIU_HDMA 0 +-- +2.53.0 + diff --git a/SPECS/linux/0195-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch b/SPECS/linux/0195-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch new file mode 100644 index 0000000000..8ac95ac323 --- /dev/null +++ b/SPECS/linux/0195-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch @@ -0,0 +1,63 @@ +From 4dede721f5c618685b4d73c90e1777282922b1c5 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 11 May 2026 02:59:12 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: Add PCIe DBI clock + +Add PCIe DBI (Data Bus Interface) clock which was missing, This will +support PCIe driver to explicitly request and enable all clocks that +needed. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-4-c9a5e563bab3@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 1a53b14739fe..cb0c4277f72a 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -949,14 +949,19 @@ CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT + + CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); + CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); ++CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(0), 0); + CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); + CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); ++CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(0), 0); + CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); + CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); ++CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(0), 0); + CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); + CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); ++CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(0), 0); + CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); + CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); ++CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(0), 0); + + static const struct clk_parent_data emac_1588_parents[] = { + CCU_PARENT_NAME(vctcxo_24m), +@@ -1391,14 +1396,19 @@ static struct clk_hw *k3_ccu_apmu_hws[] = { + [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, + [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTA_DBI] = &pciea_dbi_clk.common.hw, + [CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTB_DBI] = &pcieb_dbi_clk.common.hw, + [CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTC_DBI] = &pciec_dbi_clk.common.hw, + [CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTD_DBI] = &pcied_dbi_clk.common.hw, + [CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw, + [CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw, ++ [CLK_APMU_PCIE_PORTE_DBI] = &pciee_dbi_clk.common.hw, + [CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw, + [CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw, + [CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw, +-- +2.53.0 + diff --git a/SPECS/linux/0195-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch b/SPECS/linux/0195-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch deleted file mode 100644 index bac6ba44e2..0000000000 --- a/SPECS/linux/0195-FROMLIST-dt-bindings-soc-spacemit-k3-Add-PCIe-DBI-cl.patch +++ /dev/null @@ -1,34 +0,0 @@ -From a3b545b4e292f534e6d6c9eb903da2ef36a22eb0 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 11 May 2026 02:59:11 +0000 -Subject: [PATCH 195/269] FROMLIST: dt-bindings: soc: spacemit: k3: Add PCIe - DBI clock IDs - -Add clock IDs of PCIe DBI (Data Bus Interface) clock. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-3-c9a5e563bab3@kernel.org -Signed-off-by: Han Gao ---- - include/dt-bindings/clock/spacemit,k3-clocks.h | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h -index b22336f3ae40..dfae52547cda 100644 ---- a/include/dt-bindings/clock/spacemit,k3-clocks.h -+++ b/include/dt-bindings/clock/spacemit,k3-clocks.h -@@ -380,6 +380,11 @@ - #define CLK_APMU_ISIM_VCLK1 86 - #define CLK_APMU_ISIM_VCLK2 87 - #define CLK_APMU_ISIM_VCLK3 88 -+#define CLK_APMU_PCIE_PORTA_DBI 89 -+#define CLK_APMU_PCIE_PORTB_DBI 90 -+#define CLK_APMU_PCIE_PORTC_DBI 91 -+#define CLK_APMU_PCIE_PORTD_DBI 92 -+#define CLK_APMU_PCIE_PORTE_DBI 93 - - /* DCIU clocks */ - #define CLK_DCIU_HDMA 0 --- -2.53.0 - diff --git a/SPECS/linux/0196-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch b/SPECS/linux/0196-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch deleted file mode 100644 index aec843bdcd..0000000000 --- a/SPECS/linux/0196-FROMLIST-clk-spacemit-k3-Add-PCIe-DBI-clock.patch +++ /dev/null @@ -1,63 +0,0 @@ -From f4322934df6fc56a1bea44fb085640ac14707bbf Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 11 May 2026 02:59:12 +0000 -Subject: [PATCH 196/269] FROMLIST: clk: spacemit: k3: Add PCIe DBI clock - -Add PCIe DBI (Data Bus Interface) clock which was missing, This will -support PCIe driver to explicitly request and enable all clocks that -needed. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-4-c9a5e563bab3@kernel.org -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index 1a53b14739fe..cb0c4277f72a 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -949,14 +949,19 @@ CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT - - CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0); - CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0); -+CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(0), 0); - CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0); - CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0); -+CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(0), 0); - CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0); - CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0); -+CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(0), 0); - CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0); - CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0); -+CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(0), 0); - CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0); - CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0); -+CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(0), 0); - - static const struct clk_parent_data emac_1588_parents[] = { - CCU_PARENT_NAME(vctcxo_24m), -@@ -1391,14 +1396,19 @@ static struct clk_hw *k3_ccu_apmu_hws[] = { - [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw, - [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTA_DBI] = &pciea_dbi_clk.common.hw, - [CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTB_DBI] = &pcieb_dbi_clk.common.hw, - [CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTC_DBI] = &pciec_dbi_clk.common.hw, - [CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTD_DBI] = &pcied_dbi_clk.common.hw, - [CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw, - [CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw, -+ [CLK_APMU_PCIE_PORTE_DBI] = &pciee_dbi_clk.common.hw, - [CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw, - [CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw, - [CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw, --- -2.53.0 - diff --git a/SPECS/linux/0196-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch b/SPECS/linux/0196-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch new file mode 100644 index 0000000000..37a358c998 --- /dev/null +++ b/SPECS/linux/0196-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch @@ -0,0 +1,41 @@ +From 085a6662d8b51206c637a4888081191cf0993a6c Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sat, 9 May 2026 18:00:00 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable eMMC for OrangePi + RV2 + +The OrangePi RV2 board has one eMMC slot, so enable eMMC. +Tested using a 16 GiB AJTD4R eMMC module. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260509100000.3315109-1-amadeus@jmu.edu.cn +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 3a829e3c9cbc..c95ca38e3d4a 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -78,6 +78,16 @@ &combo_phy { + status = "okay"; + }; + ++&emmc { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ no-sd; ++ no-sdio; ++ non-removable; ++ status = "okay"; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +-- +2.53.0 + diff --git a/SPECS/linux/0197-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch b/SPECS/linux/0197-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch new file mode 100644 index 0000000000..858f8cfd6b --- /dev/null +++ b/SPECS/linux/0197-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch @@ -0,0 +1,318 @@ +From feb984c8595a2b43ffb1bb60afa09a83f18e83ed Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 8 May 2026 15:25:24 +0800 +Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: configure ILCR/IWCR for + accurate SCL frequency + +The SpacemiT I2C controller's SCL (Serial Clock Line) frequency for +master mode operations is determined by the ILCR (I2C Load Count Register). +Previously, the driver relied on the hardware's reset default +values for this register. + +The hardware's default ILCR values (SLV=0x156, FLV=0x5d) yield SCL +frequencies lower than intended. For example, with the default +31.5 MHz input clock, these default settings result in an SCL +frequency of approximately 93 kHz (standard mode) when targeting 100 kHz, +and approximately 338 kHz (fast mode) when targeting 400 kHz. +These frequencies are below the 100 kHz/400 kHz nominal speeds. + +This patch integrates the SCL frequency management into +the Common Clock Framework (CCF). Specifically, the ILCR register, +which acts as a frequency divider for the SCL clock, is now registered +as a managed clock (scl_clk) within the CCF. + +The actual hardware timing formulas are: +- standard mode: SCL = FCLK / (2 * SLV + 8) +- fast mode: SCL = FCLK / (2 * FLV + 10) + +These formulas are only valid when the IWCR (Wait Count Register) is +programmed to 0x142A, a value specified by the I2C IP designer. The +driver now initializes IWCR to this value during controller init. + +Reviewed-by: Yixun Lan +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-1-8c2dde5c3ed5@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/i2c/busses/Kconfig | 2 +- + drivers/i2c/busses/i2c-k1.c | 174 ++++++++++++++++++++++++++++++++++-- + 2 files changed, 167 insertions(+), 9 deletions(-) + +diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig +index 7cb6b9b864a7..1eb3b5339ba8 100644 +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -793,7 +793,7 @@ config I2C_JZ4780 + config I2C_K1 + tristate "SpacemiT K1 I2C adapter" + depends on ARCH_SPACEMIT || COMPILE_TEST +- depends on OF ++ depends on OF && COMMON_CLK + help + This option enables support for the I2C interface on the SpacemiT K1 + platform. +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index 9152cf436bea..c6fe2052e479 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -4,7 +4,9 @@ + */ + + #include ++#include + #include ++#include + #include + #include + #include +@@ -17,6 +19,8 @@ + #define SPACEMIT_ISR 0x4 /* Status register */ + #define SPACEMIT_IDBR 0xc /* Data buffer register */ + #define SPACEMIT_IRCR 0x18 /* Reset cycle counter */ ++#define SPACEMIT_ILCR 0x10 /* Load Count Register */ ++#define SPACEMIT_IWCR 0x14 /* Wait Count Register */ + #define SPACEMIT_IBMR 0x1c /* Bus monitor register */ + + /* SPACEMIT_ICR register fields */ +@@ -88,6 +92,19 @@ + #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */ + #define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */ + ++#define SPACEMIT_LCR_LV_STANDARD_MASK GENMASK(8, 0) ++#define SPACEMIT_LCR_LV_FAST_MASK GENMASK(17, 9) ++ ++/* SPACEMIT_IWCR register fields */ ++#define SPACEMIT_WCR_COUNT GENMASK(4, 0) ++#define SPACEMIT_WCR_HS_COUNT1 GENMASK(9, 5) ++#define SPACEMIT_WCR_HS_COUNT2 GENMASK(14, 10) ++ ++/* Required by I2C IP for correct SCL timing */ ++#define SPACEMIT_IWCR_INIT_VALUE (FIELD_PREP(SPACEMIT_WCR_COUNT, 10) | \ ++ FIELD_PREP(SPACEMIT_WCR_HS_COUNT1, 1) | \ ++ FIELD_PREP(SPACEMIT_WCR_HS_COUNT2, 5)) ++ + /* i2c bus recover timeout: us */ + #define SPACEMIT_I2C_BUS_BUSY_TIMEOUT 100000 + +@@ -109,11 +126,20 @@ enum spacemit_i2c_state { + SPACEMIT_STATE_WRITE, + }; + ++enum spacemit_i2c_mode { ++ SPACEMIT_MODE_STANDARD, ++ SPACEMIT_MODE_FAST ++}; ++ + /* i2c-spacemit driver's main struct */ + struct spacemit_i2c_dev { + struct device *dev; + struct i2c_adapter adapt; + ++ struct clk_hw scl_clk_hw; ++ struct clk *scl_clk; ++ enum spacemit_i2c_mode mode; ++ + /* hardware resources */ + void __iomem *base; + int irq; +@@ -135,6 +161,85 @@ struct spacemit_i2c_dev { + u32 status; + }; + ++static void spacemit_i2c_scl_clk_disable_unprepare(void *data) ++{ ++ clk_disable_unprepare(data); ++} ++ ++/* ++ * Calculate the ILCR divider value (lv) from the target SCL rate. ++ * ++ * Hardware timing formulas: ++ * - standard mode: SCL = FCLK / (2 * SLV + 8) ++ * - fast mode: SCL = FCLK / (2 * FLV + 10) ++ */ ++static u32 spacemit_i2c_calc_lv(struct spacemit_i2c_dev *i2c, ++ unsigned long parent_rate, ++ unsigned long target_rate) ++{ ++ u32 offset, denom; ++ ++ offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10; ++ denom = DIV_ROUND_CLOSEST(parent_rate, target_rate); ++ ++ return (denom <= offset) ? 0 : DIV_ROUND_CLOSEST(denom - offset, 2); ++} ++ ++static int spacemit_i2c_clk_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); ++ u32 lv, lcr, mask; ++ ++ lv = spacemit_i2c_calc_lv(i2c, parent_rate, rate); ++ ++ mask = (i2c->mode == SPACEMIT_MODE_STANDARD) ? ++ SPACEMIT_LCR_LV_STANDARD_MASK : SPACEMIT_LCR_LV_FAST_MASK; ++ ++ lcr = readl(i2c->base + SPACEMIT_ILCR); ++ lcr &= ~mask; ++ lcr |= field_prep(mask, lv); ++ writel(lcr, i2c->base + SPACEMIT_ILCR); ++ ++ return 0; ++} ++ ++static int spacemit_i2c_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); ++ u32 lv, offset; ++ ++ lv = spacemit_i2c_calc_lv(i2c, req->best_parent_rate, req->rate); ++ offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10; ++ req->rate = DIV_ROUND_CLOSEST(req->best_parent_rate, lv * 2 + offset); ++ ++ return 0; ++} ++ ++static unsigned long spacemit_i2c_clk_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); ++ u32 lcr, lv = 0; ++ ++ lcr = readl(i2c->base + SPACEMIT_ILCR); ++ ++ if (i2c->mode == SPACEMIT_MODE_STANDARD) { ++ lv = FIELD_GET(SPACEMIT_LCR_LV_STANDARD_MASK, lcr); ++ return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 8); ++ } ++ ++ lv = FIELD_GET(SPACEMIT_LCR_LV_FAST_MASK, lcr); ++ return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 10); ++} ++ ++static const struct clk_ops spacemit_i2c_clk_ops = { ++ .set_rate = spacemit_i2c_clk_set_rate, ++ .determine_rate = spacemit_i2c_clk_determine_rate, ++ .recalc_rate = spacemit_i2c_clk_recalc_rate, ++}; ++ + static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c) + { + u32 val; +@@ -153,6 +258,28 @@ static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c) + writel(val, i2c->base + SPACEMIT_ICR); + } + ++static int spacemit_i2c_register_scl_clk(struct spacemit_i2c_dev *i2c) ++{ ++ struct clk_init_data init = {}; ++ char name[64]; ++ int ret; ++ ++ ret = snprintf(name, sizeof(name), "%s_scl_clk", dev_name(i2c->dev)); ++ if (ret >= ARRAY_SIZE(name)) ++ dev_warn(i2c->dev, "scl clock name truncated"); ++ ++ init.name = name; ++ init.ops = &spacemit_i2c_clk_ops; ++ init.parent_data = (struct clk_parent_data[]) { ++ { .fw_name = "func" }, ++ }; ++ init.num_parents = 1; ++ ++ i2c->scl_clk_hw.init = &init; ++ ++ return devm_clk_hw_register(i2c->dev, &i2c->scl_clk_hw); ++} ++ + static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c) + { + writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR); +@@ -286,7 +413,7 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) + val |= SPACEMIT_CR_MSDIE; + } + +- if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) ++ if (i2c->mode == SPACEMIT_MODE_FAST) + val |= SPACEMIT_CR_MODE_FAST; + + /* disable response to general call */ +@@ -309,6 +436,14 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) + writel(val, i2c->base + SPACEMIT_IRCR); + + spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); ++ ++ /* ++ * Initialize IWCR to the value specified by the I2C IP designer. ++ * The SCL frequency formulas (SCL = FCLK / (2*SLV+8) for standard ++ * mode, SCL = FCLK / (2*FLV+10) for fast mode) are only valid when ++ * IWCR contains this specific value. ++ */ ++ writel(SPACEMIT_IWCR_INIT_VALUE, i2c->base + SPACEMIT_IWCR); + } + + static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) +@@ -703,14 +838,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); + + /* For now, this driver doesn't support high-speed. */ +- if (!i2c->clock_freq || i2c->clock_freq > SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { +- dev_warn(dev, "unsupported clock frequency %u; using %u\n", +- i2c->clock_freq, SPACEMIT_I2C_MAX_FAST_MODE_FREQ); ++ if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ && ++ i2c->clock_freq <= SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { ++ i2c->mode = SPACEMIT_MODE_FAST; ++ } else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { ++ i2c->mode = SPACEMIT_MODE_STANDARD; ++ } else { ++ dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode"); ++ i2c->mode = SPACEMIT_MODE_FAST; + i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; +- } else if (i2c->clock_freq < SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { +- dev_warn(dev, "unsupported clock frequency %u; using %u\n", +- i2c->clock_freq, SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ); +- i2c->clock_freq = SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ; + } + + i2c->dev = &pdev->dev; +@@ -732,6 +868,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock"); + ++ ret = spacemit_i2c_register_scl_clk(i2c); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to register scl clock\n"); ++ ++ i2c->scl_clk = devm_clk_hw_get_clk(dev, &i2c->scl_clk_hw, "scl"); ++ if (IS_ERR(i2c->scl_clk)) ++ return dev_err_probe(dev, PTR_ERR(i2c->scl_clk), ++ "failed to get scl clock\n"); ++ + clk = devm_clk_get_enabled(dev, "bus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); +@@ -741,6 +886,19 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + return dev_err_probe(dev, PTR_ERR(rst), + "failed to acquire deasserted reset\n"); + ++ ret = clk_set_rate(i2c->scl_clk, i2c->clock_freq); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to set rate for SCL clock"); ++ ++ ret = clk_prepare_enable(i2c->scl_clk); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to prepare and enable clock"); ++ ++ ret = devm_add_action_or_reset(dev, spacemit_i2c_scl_clk_disable_unprepare, ++ i2c->scl_clk); ++ if (ret) ++ return ret; ++ + spacemit_i2c_reset(i2c); + + i2c_set_adapdata(&i2c->adapt, i2c); +-- +2.53.0 + diff --git a/SPECS/linux/0197-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch b/SPECS/linux/0197-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch deleted file mode 100644 index 865af440be..0000000000 --- a/SPECS/linux/0197-FROMLIST-riscv-dts-spacemit-enable-eMMC-for-OrangePi.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 1220579655cb94a0b94e890b59774a9c0815568d Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sat, 9 May 2026 18:00:00 +0800 -Subject: [PATCH 197/269] FROMLIST: riscv: dts: spacemit: enable eMMC for - OrangePi RV2 - -The OrangePi RV2 board has one eMMC slot, so enable eMMC. -Tested using a 16 GiB AJTD4R eMMC module. - -Signed-off-by: Chukun Pan -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260509100000.3315109-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 3a829e3c9cbc..c95ca38e3d4a 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -78,6 +78,16 @@ &combo_phy { - status = "okay"; - }; - -+&emmc { -+ bus-width = <8>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ no-sd; -+ no-sdio; -+ non-removable; -+ status = "okay"; -+}; -+ - ð0 { - phy-handle = <&rgmii0>; - phy-mode = "rgmii-id"; --- -2.53.0 - diff --git a/SPECS/linux/0198-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch b/SPECS/linux/0198-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch deleted file mode 100644 index 3331f44d1d..0000000000 --- a/SPECS/linux/0198-FROMLIST-i2c-spacemit-configure-ILCR-IWCR-for-accura.patch +++ /dev/null @@ -1,318 +0,0 @@ -From 1b181785b1c0a6e016879d81595128ee131433ea Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Fri, 8 May 2026 15:25:24 +0800 -Subject: [PATCH 198/269] FROMLIST: i2c: spacemit: configure ILCR/IWCR for - accurate SCL frequency - -The SpacemiT I2C controller's SCL (Serial Clock Line) frequency for -master mode operations is determined by the ILCR (I2C Load Count Register). -Previously, the driver relied on the hardware's reset default -values for this register. - -The hardware's default ILCR values (SLV=0x156, FLV=0x5d) yield SCL -frequencies lower than intended. For example, with the default -31.5 MHz input clock, these default settings result in an SCL -frequency of approximately 93 kHz (standard mode) when targeting 100 kHz, -and approximately 338 kHz (fast mode) when targeting 400 kHz. -These frequencies are below the 100 kHz/400 kHz nominal speeds. - -This patch integrates the SCL frequency management into -the Common Clock Framework (CCF). Specifically, the ILCR register, -which acts as a frequency divider for the SCL clock, is now registered -as a managed clock (scl_clk) within the CCF. - -The actual hardware timing formulas are: -- standard mode: SCL = FCLK / (2 * SLV + 8) -- fast mode: SCL = FCLK / (2 * FLV + 10) - -These formulas are only valid when the IWCR (Wait Count Register) is -programmed to 0x142A, a value specified by the I2C IP designer. The -driver now initializes IWCR to this value during controller init. - -Reviewed-by: Yixun Lan -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-1-8c2dde5c3ed5@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/i2c/busses/Kconfig | 2 +- - drivers/i2c/busses/i2c-k1.c | 174 ++++++++++++++++++++++++++++++++++-- - 2 files changed, 167 insertions(+), 9 deletions(-) - -diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig -index 7cb6b9b864a7..1eb3b5339ba8 100644 ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -793,7 +793,7 @@ config I2C_JZ4780 - config I2C_K1 - tristate "SpacemiT K1 I2C adapter" - depends on ARCH_SPACEMIT || COMPILE_TEST -- depends on OF -+ depends on OF && COMMON_CLK - help - This option enables support for the I2C interface on the SpacemiT K1 - platform. -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index 9152cf436bea..c6fe2052e479 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -4,7 +4,9 @@ - */ - - #include -+#include - #include -+#include - #include - #include - #include -@@ -17,6 +19,8 @@ - #define SPACEMIT_ISR 0x4 /* Status register */ - #define SPACEMIT_IDBR 0xc /* Data buffer register */ - #define SPACEMIT_IRCR 0x18 /* Reset cycle counter */ -+#define SPACEMIT_ILCR 0x10 /* Load Count Register */ -+#define SPACEMIT_IWCR 0x14 /* Wait Count Register */ - #define SPACEMIT_IBMR 0x1c /* Bus monitor register */ - - /* SPACEMIT_ICR register fields */ -@@ -88,6 +92,19 @@ - #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */ - #define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */ - -+#define SPACEMIT_LCR_LV_STANDARD_MASK GENMASK(8, 0) -+#define SPACEMIT_LCR_LV_FAST_MASK GENMASK(17, 9) -+ -+/* SPACEMIT_IWCR register fields */ -+#define SPACEMIT_WCR_COUNT GENMASK(4, 0) -+#define SPACEMIT_WCR_HS_COUNT1 GENMASK(9, 5) -+#define SPACEMIT_WCR_HS_COUNT2 GENMASK(14, 10) -+ -+/* Required by I2C IP for correct SCL timing */ -+#define SPACEMIT_IWCR_INIT_VALUE (FIELD_PREP(SPACEMIT_WCR_COUNT, 10) | \ -+ FIELD_PREP(SPACEMIT_WCR_HS_COUNT1, 1) | \ -+ FIELD_PREP(SPACEMIT_WCR_HS_COUNT2, 5)) -+ - /* i2c bus recover timeout: us */ - #define SPACEMIT_I2C_BUS_BUSY_TIMEOUT 100000 - -@@ -109,11 +126,20 @@ enum spacemit_i2c_state { - SPACEMIT_STATE_WRITE, - }; - -+enum spacemit_i2c_mode { -+ SPACEMIT_MODE_STANDARD, -+ SPACEMIT_MODE_FAST -+}; -+ - /* i2c-spacemit driver's main struct */ - struct spacemit_i2c_dev { - struct device *dev; - struct i2c_adapter adapt; - -+ struct clk_hw scl_clk_hw; -+ struct clk *scl_clk; -+ enum spacemit_i2c_mode mode; -+ - /* hardware resources */ - void __iomem *base; - int irq; -@@ -135,6 +161,85 @@ struct spacemit_i2c_dev { - u32 status; - }; - -+static void spacemit_i2c_scl_clk_disable_unprepare(void *data) -+{ -+ clk_disable_unprepare(data); -+} -+ -+/* -+ * Calculate the ILCR divider value (lv) from the target SCL rate. -+ * -+ * Hardware timing formulas: -+ * - standard mode: SCL = FCLK / (2 * SLV + 8) -+ * - fast mode: SCL = FCLK / (2 * FLV + 10) -+ */ -+static u32 spacemit_i2c_calc_lv(struct spacemit_i2c_dev *i2c, -+ unsigned long parent_rate, -+ unsigned long target_rate) -+{ -+ u32 offset, denom; -+ -+ offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10; -+ denom = DIV_ROUND_CLOSEST(parent_rate, target_rate); -+ -+ return (denom <= offset) ? 0 : DIV_ROUND_CLOSEST(denom - offset, 2); -+} -+ -+static int spacemit_i2c_clk_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); -+ u32 lv, lcr, mask; -+ -+ lv = spacemit_i2c_calc_lv(i2c, parent_rate, rate); -+ -+ mask = (i2c->mode == SPACEMIT_MODE_STANDARD) ? -+ SPACEMIT_LCR_LV_STANDARD_MASK : SPACEMIT_LCR_LV_FAST_MASK; -+ -+ lcr = readl(i2c->base + SPACEMIT_ILCR); -+ lcr &= ~mask; -+ lcr |= field_prep(mask, lv); -+ writel(lcr, i2c->base + SPACEMIT_ILCR); -+ -+ return 0; -+} -+ -+static int spacemit_i2c_clk_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); -+ u32 lv, offset; -+ -+ lv = spacemit_i2c_calc_lv(i2c, req->best_parent_rate, req->rate); -+ offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10; -+ req->rate = DIV_ROUND_CLOSEST(req->best_parent_rate, lv * 2 + offset); -+ -+ return 0; -+} -+ -+static unsigned long spacemit_i2c_clk_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw); -+ u32 lcr, lv = 0; -+ -+ lcr = readl(i2c->base + SPACEMIT_ILCR); -+ -+ if (i2c->mode == SPACEMIT_MODE_STANDARD) { -+ lv = FIELD_GET(SPACEMIT_LCR_LV_STANDARD_MASK, lcr); -+ return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 8); -+ } -+ -+ lv = FIELD_GET(SPACEMIT_LCR_LV_FAST_MASK, lcr); -+ return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 10); -+} -+ -+static const struct clk_ops spacemit_i2c_clk_ops = { -+ .set_rate = spacemit_i2c_clk_set_rate, -+ .determine_rate = spacemit_i2c_clk_determine_rate, -+ .recalc_rate = spacemit_i2c_clk_recalc_rate, -+}; -+ - static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c) - { - u32 val; -@@ -153,6 +258,28 @@ static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c) - writel(val, i2c->base + SPACEMIT_ICR); - } - -+static int spacemit_i2c_register_scl_clk(struct spacemit_i2c_dev *i2c) -+{ -+ struct clk_init_data init = {}; -+ char name[64]; -+ int ret; -+ -+ ret = snprintf(name, sizeof(name), "%s_scl_clk", dev_name(i2c->dev)); -+ if (ret >= ARRAY_SIZE(name)) -+ dev_warn(i2c->dev, "scl clock name truncated"); -+ -+ init.name = name; -+ init.ops = &spacemit_i2c_clk_ops; -+ init.parent_data = (struct clk_parent_data[]) { -+ { .fw_name = "func" }, -+ }; -+ init.num_parents = 1; -+ -+ i2c->scl_clk_hw.init = &init; -+ -+ return devm_clk_hw_register(i2c->dev, &i2c->scl_clk_hw); -+} -+ - static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c) - { - writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR); -@@ -286,7 +413,7 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) - val |= SPACEMIT_CR_MSDIE; - } - -- if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ) -+ if (i2c->mode == SPACEMIT_MODE_FAST) - val |= SPACEMIT_CR_MODE_FAST; - - /* disable response to general call */ -@@ -309,6 +436,14 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c) - writel(val, i2c->base + SPACEMIT_IRCR); - - spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK); -+ -+ /* -+ * Initialize IWCR to the value specified by the I2C IP designer. -+ * The SCL frequency formulas (SCL = FCLK / (2*SLV+8) for standard -+ * mode, SCL = FCLK / (2*FLV+10) for fast mode) are only valid when -+ * IWCR contains this specific value. -+ */ -+ writel(SPACEMIT_IWCR_INIT_VALUE, i2c->base + SPACEMIT_IWCR); - } - - static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c) -@@ -703,14 +838,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); - - /* For now, this driver doesn't support high-speed. */ -- if (!i2c->clock_freq || i2c->clock_freq > SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { -- dev_warn(dev, "unsupported clock frequency %u; using %u\n", -- i2c->clock_freq, SPACEMIT_I2C_MAX_FAST_MODE_FREQ); -+ if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ && -+ i2c->clock_freq <= SPACEMIT_I2C_MAX_FAST_MODE_FREQ) { -+ i2c->mode = SPACEMIT_MODE_FAST; -+ } else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { -+ i2c->mode = SPACEMIT_MODE_STANDARD; -+ } else { -+ dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode"); -+ i2c->mode = SPACEMIT_MODE_FAST; - i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; -- } else if (i2c->clock_freq < SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { -- dev_warn(dev, "unsupported clock frequency %u; using %u\n", -- i2c->clock_freq, SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ); -- i2c->clock_freq = SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ; - } - - i2c->dev = &pdev->dev; -@@ -732,6 +868,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock"); - -+ ret = spacemit_i2c_register_scl_clk(i2c); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to register scl clock\n"); -+ -+ i2c->scl_clk = devm_clk_hw_get_clk(dev, &i2c->scl_clk_hw, "scl"); -+ if (IS_ERR(i2c->scl_clk)) -+ return dev_err_probe(dev, PTR_ERR(i2c->scl_clk), -+ "failed to get scl clock\n"); -+ - clk = devm_clk_get_enabled(dev, "bus"); - if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); -@@ -741,6 +886,19 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - return dev_err_probe(dev, PTR_ERR(rst), - "failed to acquire deasserted reset\n"); - -+ ret = clk_set_rate(i2c->scl_clk, i2c->clock_freq); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to set rate for SCL clock"); -+ -+ ret = clk_prepare_enable(i2c->scl_clk); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to prepare and enable clock"); -+ -+ ret = devm_add_action_or_reset(dev, spacemit_i2c_scl_clk_disable_unprepare, -+ i2c->scl_clk); -+ if (ret) -+ return ret; -+ - spacemit_i2c_reset(i2c); - - i2c_set_adapdata(&i2c->adapt, i2c); --- -2.53.0 - diff --git a/SPECS/linux/0198-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch b/SPECS/linux/0198-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch new file mode 100644 index 0000000000..2c2c1857d5 --- /dev/null +++ b/SPECS/linux/0198-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch @@ -0,0 +1,45 @@ +From c69aff2f94c47f9051ff3f2326ea0b61dccfc8e1 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Fri, 8 May 2026 15:25:25 +0800 +Subject: [RUYI PATCH] FROMLIST: i2c: spacemit: drop warning when + clock-frequency property is absent + +The clock-frequency property is optional according to the DT binding. +Do not emit a warning when the property is missing and fall back to the +default frequency instead. + +Reviewed-by: Alex Elder +Signed-off-by: Troy Mitchell +Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-2-8c2dde5c3ed5@linux.spacemit.com +Signed-off-by: Han Gao +--- + drivers/i2c/busses/i2c-k1.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c +index c6fe2052e479..7cf5c05a20d2 100644 +--- a/drivers/i2c/busses/i2c-k1.c ++++ b/drivers/i2c/busses/i2c-k1.c +@@ -833,9 +833,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + if (!i2c) + return -ENOMEM; + +- ret = of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); +- if (ret && ret != -EINVAL) +- dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); ++ of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); + + /* For now, this driver doesn't support high-speed. */ + if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ && +@@ -844,7 +842,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) + } else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { + i2c->mode = SPACEMIT_MODE_STANDARD; + } else { +- dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode"); ++ dev_info(dev, "clock-frequency not set or out of range, using fast mode\n"); + i2c->mode = SPACEMIT_MODE_FAST; + i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; + } +-- +2.53.0 + diff --git a/SPECS/linux/0199-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch b/SPECS/linux/0199-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch new file mode 100644 index 0000000000..a49d35520a --- /dev/null +++ b/SPECS/linux/0199-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch @@ -0,0 +1,59 @@ +From 0bf2f2078011bd701cd96e23b4365a9edf483605 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:56 +0200 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add pinctrl + support for voltage switching + +Document pinctrl properties to support voltage-dependent pin +configuration switching for UHS-I SD card modes. + +Add optional pinctrl-names property with two states: +- "default": For 3.3V operation with standard drive strength +- "state_uhs": For 1.8V operation with optimized drive strength + +These pinctrl states allow the SDHCI driver to coordinate voltage +switching with pin configuration changes, ensuring proper signal +integrity during UHS-I mode transitions. + +Acked-by: Conor Dooley +Signed-off-by: Iker Pedrosa +Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-1-ae48c0b2b2cf@gmail.com +Signed-off-by: Han Gao +--- + .../devicetree/bindings/mmc/spacemit,sdhci.yaml | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +index 1081ea687702..e5534c781c19 100644 +--- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml ++++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +@@ -44,6 +44,18 @@ properties: + - const: axi + - const: sdh + ++ pinctrl-names: ++ minItems: 1 ++ items: ++ - const: default ++ - const: uhs ++ ++ pinctrl-0: ++ description: Default pinctrl state for 3.3V operation ++ ++ pinctrl-1: ++ description: Optional pinctrl state for 1.8V UHS operation with "uhs" name ++ + required: + - compatible + - reg +@@ -66,4 +78,7 @@ examples: + clock-names = "core", "io"; + resets = <&syscon_apmu 2>, <&syscon_apmu 5>; + reset-names = "axi", "sdh"; ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&sdhci_default_cfg>; ++ pinctrl-1 = <&sdhci_uhs_cfg>; + }; +-- +2.53.0 + diff --git a/SPECS/linux/0199-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch b/SPECS/linux/0199-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch deleted file mode 100644 index 60b5463b93..0000000000 --- a/SPECS/linux/0199-FROMLIST-i2c-spacemit-drop-warning-when-clock-freque.patch +++ /dev/null @@ -1,45 +0,0 @@ -From b8c017440462cc188a5442037eaec7c798914775 Mon Sep 17 00:00:00 2001 -From: Troy Mitchell -Date: Fri, 8 May 2026 15:25:25 +0800 -Subject: [PATCH 199/269] FROMLIST: i2c: spacemit: drop warning when - clock-frequency property is absent - -The clock-frequency property is optional according to the DT binding. -Do not emit a warning when the property is missing and fall back to the -default frequency instead. - -Reviewed-by: Alex Elder -Signed-off-by: Troy Mitchell -Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-2-8c2dde5c3ed5@linux.spacemit.com -Signed-off-by: Han Gao ---- - drivers/i2c/busses/i2c-k1.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - -diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c -index c6fe2052e479..7cf5c05a20d2 100644 ---- a/drivers/i2c/busses/i2c-k1.c -+++ b/drivers/i2c/busses/i2c-k1.c -@@ -833,9 +833,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - if (!i2c) - return -ENOMEM; - -- ret = of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); -- if (ret && ret != -EINVAL) -- dev_warn(dev, "failed to read clock-frequency property: %d\n", ret); -+ of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq); - - /* For now, this driver doesn't support high-speed. */ - if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ && -@@ -844,7 +842,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev) - } else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) { - i2c->mode = SPACEMIT_MODE_STANDARD; - } else { -- dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode"); -+ dev_info(dev, "clock-frequency not set or out of range, using fast mode\n"); - i2c->mode = SPACEMIT_MODE_FAST; - i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ; - } --- -2.53.0 - diff --git a/SPECS/linux/0200-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch b/SPECS/linux/0200-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch deleted file mode 100644 index 00f1043680..0000000000 --- a/SPECS/linux/0200-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-pinctrl-.patch +++ /dev/null @@ -1,59 +0,0 @@ -From f78a8061bda3844f94a1eae5bb6521b25e7a0bd0 Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Mon, 11 May 2026 10:53:56 +0200 -Subject: [PATCH 200/269] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add - pinctrl support for voltage switching - -Document pinctrl properties to support voltage-dependent pin -configuration switching for UHS-I SD card modes. - -Add optional pinctrl-names property with two states: -- "default": For 3.3V operation with standard drive strength -- "state_uhs": For 1.8V operation with optimized drive strength - -These pinctrl states allow the SDHCI driver to coordinate voltage -switching with pin configuration changes, ensuring proper signal -integrity during UHS-I mode transitions. - -Acked-by: Conor Dooley -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-1-ae48c0b2b2cf@gmail.com -Signed-off-by: Han Gao ---- - .../devicetree/bindings/mmc/spacemit,sdhci.yaml | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -index 1081ea687702..e5534c781c19 100644 ---- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -+++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml -@@ -44,6 +44,18 @@ properties: - - const: axi - - const: sdh - -+ pinctrl-names: -+ minItems: 1 -+ items: -+ - const: default -+ - const: uhs -+ -+ pinctrl-0: -+ description: Default pinctrl state for 3.3V operation -+ -+ pinctrl-1: -+ description: Optional pinctrl state for 1.8V UHS operation with "uhs" name -+ - required: - - compatible - - reg -@@ -66,4 +78,7 @@ examples: - clock-names = "core", "io"; - resets = <&syscon_apmu 2>, <&syscon_apmu 5>; - reset-names = "axi", "sdh"; -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&sdhci_default_cfg>; -+ pinctrl-1 = <&sdhci_uhs_cfg>; - }; --- -2.53.0 - diff --git a/SPECS/linux/0200-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch b/SPECS/linux/0200-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch new file mode 100644 index 0000000000..3d862cc4bf --- /dev/null +++ b/SPECS/linux/0200-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch @@ -0,0 +1,65 @@ +From 8c4241419ff3d46df6431269b3f523b095a6fa7b Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:57 +0200 +Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: enable essential clock + infrastructure for SD operation + +Ensure SD card pins receive clock signals by enabling pad clock +generation and overriding automatic clock gating. Required for all SD +operation modes. + +The SDHC_GEN_PAD_CLK_ON setting in LEGACY_CTRL_REG is safe for both SD +and eMMC operation as both protocols use the same physical MMC interface +pins and require proper clock signal generation at the hardware level +for signal integrity and timing. + +Additional SD-specific clock overrides (SDHC_OVRRD_CLK_OEN and +SDHC_FORCE_CLK_ON) are conditionally applied only for SD-only +controllers to handle removable card scenarios. + +Tested-by: Anand Moon +Acked-by: Adrian Hunter +Tested-by: Trevor Gamblin +Reviewed-by: Troy Mitchell +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-2-ae48c0b2b2cf@gmail.com +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index 455656f9842d..0dd06fc19b85 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -21,6 +21,13 @@ + #include "sdhci.h" + #include "sdhci-pltfm.h" + ++#define SPACEMIT_SDHC_OP_EXT_REG 0x108 ++#define SDHC_OVRRD_CLK_OEN BIT(11) ++#define SDHC_FORCE_CLK_ON BIT(12) ++ ++#define SPACEMIT_SDHC_LEGACY_CTRL_REG 0x10C ++#define SDHC_GEN_PAD_CLK_ON BIT(6) ++ + #define SPACEMIT_SDHC_MMC_CTRL_REG 0x114 + #define SDHC_MISC_INT_EN BIT(1) + #define SDHC_MISC_INT BIT(2) +@@ -101,6 +108,12 @@ static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) + + if (!(host->mmc->caps2 & MMC_CAP2_NO_MMC)) + spacemit_sdhci_setbits(host, SDHC_MMC_CARD_MODE, SPACEMIT_SDHC_MMC_CTRL_REG); ++ ++ spacemit_sdhci_setbits(host, SDHC_GEN_PAD_CLK_ON, SPACEMIT_SDHC_LEGACY_CTRL_REG); ++ ++ if (host->mmc->caps2 & MMC_CAP2_NO_MMC) ++ spacemit_sdhci_setbits(host, SDHC_OVRRD_CLK_OEN | SDHC_FORCE_CLK_ON, ++ SPACEMIT_SDHC_OP_EXT_REG); + } + + static void spacemit_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) +-- +2.53.0 + diff --git a/SPECS/linux/0201-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch b/SPECS/linux/0201-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch new file mode 100644 index 0000000000..81362419d5 --- /dev/null +++ b/SPECS/linux/0201-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch @@ -0,0 +1,144 @@ +From 39fde1b63254ea21184494734c21d26a70f27b72 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:58 +0200 +Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: add regulator and pinctrl + voltage switching support + +Add voltage switching infrastructure for UHS-I modes by integrating both +regulator framework (for supply voltage control) and pinctrl state +switching (for pin drive strength optimization). + +- Add regulator supply parsing and voltage switching callback +- Add optional pinctrl state switching between "default" (3.3V) and + "state_uhs" (1.8V) configurations +- Enable coordinated voltage and pin configuration changes for UHS modes + +This provides complete voltage switching support while maintaining +backward compatibility when pinctrl states are not defined. + +Tested-by: Anand Moon +Tested-by: Trevor Gamblin +Acked-by: Adrian Hunter +Reviewed-by: Troy Mitchell +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-3-ae48c0b2b2cf@gmail.com +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 72 ++++++++++++++++++++++++++++++++++ + 1 file changed, 72 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index 0dd06fc19b85..d9144537032a 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + + #include "sdhci.h" +@@ -71,6 +72,9 @@ + struct spacemit_sdhci_host { + struct clk *clk_core; + struct clk *clk_io; ++ struct pinctrl *pinctrl; ++ struct pinctrl_state *pinctrl_default; ++ struct pinctrl_state *pinctrl_uhs; + }; + + /* All helper functions will update clr/set while preserve rest bits */ +@@ -219,6 +223,46 @@ static void spacemit_sdhci_pre_hs400_to_hs200(struct mmc_host *mmc) + SPACEMIT_SDHC_PHY_CTRL_REG); + } + ++static int spacemit_sdhci_start_signal_voltage_switch(struct mmc_host *mmc, ++ struct mmc_ios *ios) ++{ ++ struct sdhci_host *host = mmc_priv(mmc); ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); ++ struct pinctrl_state *state; ++ int ret; ++ ++ ret = sdhci_start_signal_voltage_switch(mmc, ios); ++ if (ret) ++ return ret; ++ ++ if (!sdhst->pinctrl) ++ return 0; ++ ++ /* Select appropriate pinctrl state based on signal voltage */ ++ switch (ios->signal_voltage) { ++ case MMC_SIGNAL_VOLTAGE_330: ++ state = sdhst->pinctrl_default; ++ break; ++ case MMC_SIGNAL_VOLTAGE_180: ++ state = sdhst->pinctrl_uhs; ++ break; ++ default: ++ dev_warn(mmc_dev(mmc), "unsupported voltage %d\n", ios->signal_voltage); ++ return 0; ++ } ++ ++ ret = pinctrl_select_state(sdhst->pinctrl, state); ++ if (ret) { ++ dev_warn(mmc_dev(mmc), "failed to select pinctrl state: %d\n", ret); ++ return 0; ++ } ++ dev_dbg(mmc_dev(mmc), "switched to %s pinctrl state\n", ++ ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 ? "UHS" : "default"); ++ ++ return 0; ++} ++ + static inline int spacemit_sdhci_get_clocks(struct device *dev, + struct sdhci_pltfm_host *pltfm_host) + { +@@ -252,6 +296,30 @@ static inline int spacemit_sdhci_get_resets(struct device *dev) + return 0; + } + ++static inline void spacemit_sdhci_get_pins(struct device *dev, ++ struct sdhci_pltfm_host *pltfm_host) ++{ ++ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); ++ ++ sdhst->pinctrl = devm_pinctrl_get(dev); ++ if (IS_ERR(sdhst->pinctrl)) { ++ sdhst->pinctrl = NULL; ++ dev_dbg(dev, "pinctrl not available, voltage switching will work without it\n"); ++ return; ++ } ++ ++ sdhst->pinctrl_default = pinctrl_lookup_state(sdhst->pinctrl, "default"); ++ if (IS_ERR(sdhst->pinctrl_default)) ++ sdhst->pinctrl_default = NULL; ++ ++ sdhst->pinctrl_uhs = pinctrl_lookup_state(sdhst->pinctrl, "uhs"); ++ if (IS_ERR(sdhst->pinctrl_uhs)) ++ sdhst->pinctrl_uhs = NULL; ++ ++ dev_dbg(dev, "pinctrl setup: default=%p, uhs=%p\n", ++ sdhst->pinctrl_default, sdhst->pinctrl_uhs); ++} ++ + static const struct sdhci_ops spacemit_sdhci_ops = { + .get_max_clock = spacemit_sdhci_clk_get_max_clock, + .reset = spacemit_sdhci_reset, +@@ -324,6 +392,10 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) + + host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY; + ++ spacemit_sdhci_get_pins(dev, pltfm_host); ++ ++ host->mmc_host_ops.start_signal_voltage_switch = spacemit_sdhci_start_signal_voltage_switch; ++ + ret = spacemit_sdhci_get_clocks(dev, pltfm_host); + if (ret) + goto err_pltfm; +-- +2.53.0 + diff --git a/SPECS/linux/0201-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch b/SPECS/linux/0201-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch deleted file mode 100644 index befba09c8a..0000000000 --- a/SPECS/linux/0201-FROMLIST-mmc-sdhci-of-k1-enable-essential-clock-infr.patch +++ /dev/null @@ -1,65 +0,0 @@ -From d543dce040ee8f89d24e66d00c34ae476a9ffa8b Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Mon, 11 May 2026 10:53:57 +0200 -Subject: [PATCH 201/269] FROMLIST: mmc: sdhci-of-k1: enable essential clock - infrastructure for SD operation - -Ensure SD card pins receive clock signals by enabling pad clock -generation and overriding automatic clock gating. Required for all SD -operation modes. - -The SDHC_GEN_PAD_CLK_ON setting in LEGACY_CTRL_REG is safe for both SD -and eMMC operation as both protocols use the same physical MMC interface -pins and require proper clock signal generation at the hardware level -for signal integrity and timing. - -Additional SD-specific clock overrides (SDHC_OVRRD_CLK_OEN and -SDHC_FORCE_CLK_ON) are conditionally applied only for SD-only -controllers to handle removable card scenarios. - -Tested-by: Anand Moon -Acked-by: Adrian Hunter -Tested-by: Trevor Gamblin -Reviewed-by: Troy Mitchell -Tested-by: Vincent Legoll -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-2-ae48c0b2b2cf@gmail.com -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index 455656f9842d..0dd06fc19b85 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -21,6 +21,13 @@ - #include "sdhci.h" - #include "sdhci-pltfm.h" - -+#define SPACEMIT_SDHC_OP_EXT_REG 0x108 -+#define SDHC_OVRRD_CLK_OEN BIT(11) -+#define SDHC_FORCE_CLK_ON BIT(12) -+ -+#define SPACEMIT_SDHC_LEGACY_CTRL_REG 0x10C -+#define SDHC_GEN_PAD_CLK_ON BIT(6) -+ - #define SPACEMIT_SDHC_MMC_CTRL_REG 0x114 - #define SDHC_MISC_INT_EN BIT(1) - #define SDHC_MISC_INT BIT(2) -@@ -101,6 +108,12 @@ static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) - - if (!(host->mmc->caps2 & MMC_CAP2_NO_MMC)) - spacemit_sdhci_setbits(host, SDHC_MMC_CARD_MODE, SPACEMIT_SDHC_MMC_CTRL_REG); -+ -+ spacemit_sdhci_setbits(host, SDHC_GEN_PAD_CLK_ON, SPACEMIT_SDHC_LEGACY_CTRL_REG); -+ -+ if (host->mmc->caps2 & MMC_CAP2_NO_MMC) -+ spacemit_sdhci_setbits(host, SDHC_OVRRD_CLK_OEN | SDHC_FORCE_CLK_ON, -+ SPACEMIT_SDHC_OP_EXT_REG); - } - - static void spacemit_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) --- -2.53.0 - diff --git a/SPECS/linux/0202-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch b/SPECS/linux/0202-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch new file mode 100644 index 0000000000..6646ffc1ec --- /dev/null +++ b/SPECS/linux/0202-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch @@ -0,0 +1,241 @@ +From 94dc78e875ba604207c250e239f0a6778fa9d74a Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:59 +0200 +Subject: [RUYI PATCH] FROMLIST: mmc: sdhci-of-k1: add comprehensive SDR tuning + support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Implement software tuning algorithm to enable UHS-I SDR modes for SD +card operation and HS200 mode for eMMC. This adds both TX and RX delay +line tuning based on the SpacemiT K1 controller capabilities. + +Algorithm features: +- Add tuning register definitions (RX_CFG, DLINE_CTRL, DLINE_CFG) +- Conditional tuning: only for high-speed modes (≥100MHz) +- TX tuning: configure transmit delay line with optimal values + (dline_reg=0, delaycode=127) to ensure optimal signal output timing +- RX tuning: single-pass window detection algorithm testing full + delay range (0-255) to find optimal receive timing window +- Retry mechanism: multiple fallback delays within optimal window + for improved reliability + +Tested-by: Anand Moon +Acked-by: Adrian Hunter +Tested-by: Trevor Gamblin +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-4-ae48c0b2b2cf@gmail.com +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-k1.c | 172 +++++++++++++++++++++++++++++++++ + 1 file changed, 172 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index d9144537032a..37b0911e7cf2 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -69,6 +69,28 @@ + #define SDHC_PHY_DRIVE_SEL GENMASK(2, 0) + #define SDHC_RX_BIAS_CTRL BIT(5) + ++#define SPACEMIT_SDHC_RX_CFG_REG 0x118 ++#define SDHC_RX_SDCLK_SEL0_MASK GENMASK(1, 0) ++#define SDHC_RX_SDCLK_SEL1_MASK GENMASK(3, 2) ++#define SDHC_RX_SDCLK_SEL1 FIELD_PREP(SDHC_RX_SDCLK_SEL1_MASK, 1) ++ ++#define SPACEMIT_SDHC_DLINE_CTRL_REG 0x130 ++#define SDHC_DLINE_PU BIT(0) ++#define SDHC_RX_DLINE_CODE_MASK GENMASK(23, 16) ++#define SDHC_TX_DLINE_CODE_MASK GENMASK(31, 24) ++ ++#define SPACEMIT_SDHC_DLINE_CFG_REG 0x134 ++#define SDHC_RX_DLINE_REG_MASK GENMASK(7, 0) ++#define SDHC_RX_DLINE_GAIN BIT(8) ++#define SDHC_TX_DLINE_REG_MASK GENMASK(23, 16) ++ ++#define SPACEMIT_RX_DLINE_REG 9 ++#define SPACEMIT_RX_TUNE_DELAY_MIN 0x0 ++#define SPACEMIT_RX_TUNE_DELAY_MAX 0xFF ++ ++#define SPACEMIT_TX_TUNING_DLINE_REG 0x00 ++#define SPACEMIT_TX_TUNING_DELAYCODE 127 ++ + struct spacemit_sdhci_host { + struct clk *clk_core; + struct clk *clk_io; +@@ -96,6 +118,50 @@ static inline void spacemit_sdhci_clrsetbits(struct sdhci_host *host, u32 clr, u + sdhci_writel(host, val, reg); + } + ++static void spacemit_sdhci_set_rx_delay(struct sdhci_host *host, u8 delay) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_CODE_MASK, ++ FIELD_PREP(SDHC_RX_DLINE_CODE_MASK, delay), ++ SPACEMIT_SDHC_DLINE_CTRL_REG); ++} ++ ++static void spacemit_sdhci_set_tx_delay(struct sdhci_host *host, u8 delay) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_CODE_MASK, ++ FIELD_PREP(SDHC_TX_DLINE_CODE_MASK, delay), ++ SPACEMIT_SDHC_DLINE_CTRL_REG); ++} ++ ++static void spacemit_sdhci_set_tx_dline_reg(struct sdhci_host *host, u8 dline_reg) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_REG_MASK, ++ FIELD_PREP(SDHC_TX_DLINE_REG_MASK, dline_reg), ++ SPACEMIT_SDHC_DLINE_CFG_REG); ++} ++ ++static void spacemit_sdhci_tx_tuning_prepare(struct sdhci_host *host) ++{ ++ spacemit_sdhci_setbits(host, SDHC_TX_MUX_SEL, SPACEMIT_SDHC_TX_CFG_REG); ++ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); ++ udelay(5); ++} ++ ++static void spacemit_sdhci_prepare_tuning(struct sdhci_host *host) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_REG_MASK, ++ FIELD_PREP(SDHC_RX_DLINE_REG_MASK, SPACEMIT_RX_DLINE_REG), ++ SPACEMIT_SDHC_DLINE_CFG_REG); ++ ++ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); ++ udelay(5); ++ ++ spacemit_sdhci_clrsetbits(host, SDHC_RX_SDCLK_SEL1_MASK, SDHC_RX_SDCLK_SEL1, ++ SPACEMIT_SDHC_RX_CFG_REG); ++ ++ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) ++ spacemit_sdhci_setbits(host, SDHC_HS200_USE_RFIFO, SPACEMIT_SDHC_PHY_FUNC_REG); ++} ++ + static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) + { + sdhci_reset(host, mask); +@@ -191,6 +257,111 @@ static unsigned int spacemit_sdhci_clk_get_max_clock(struct sdhci_host *host) + return clk_get_rate(pltfm_host->clk); + } + ++static int spacemit_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ int current_len = 0, current_start = 0; ++ int max_pass_len = 0, max_pass_start = 0; ++ struct mmc_host *mmc = host->mmc; ++ struct mmc_ios ios = mmc->ios; ++ u8 final_delay; ++ int ret = 0; ++ int i; ++ ++ /* ++ * Tuning is required for SDR50/SDR104, HS200/HS400 cards and ++ * if clock frequency is greater than 100MHz in these modes. ++ */ ++ if (host->clock < 100 * 1000 * 1000 || ++ !(ios.timing == MMC_TIMING_MMC_HS200 || ++ ios.timing == MMC_TIMING_UHS_SDR50 || ++ ios.timing == MMC_TIMING_UHS_SDR104)) ++ return 0; ++ ++ if (mmc->caps2 & MMC_CAP2_NO_MMC) { ++ spacemit_sdhci_set_tx_dline_reg(host, SPACEMIT_TX_TUNING_DLINE_REG); ++ spacemit_sdhci_set_tx_delay(host, SPACEMIT_TX_TUNING_DELAYCODE); ++ spacemit_sdhci_tx_tuning_prepare(host); ++ ++ dev_dbg(mmc_dev(host->mmc), "TX tuning: dline_reg=%d, delaycode=%d\n", ++ SPACEMIT_TX_TUNING_DLINE_REG, SPACEMIT_TX_TUNING_DELAYCODE); ++ } ++ ++ spacemit_sdhci_prepare_tuning(host); ++ ++ for (i = SPACEMIT_RX_TUNE_DELAY_MIN; i <= SPACEMIT_RX_TUNE_DELAY_MAX; i++) { ++ spacemit_sdhci_set_rx_delay(host, i); ++ ret = mmc_send_tuning(host->mmc, opcode, NULL); ++ ++ dev_dbg(mmc_dev(host->mmc), "RX delay %d: %s\n", ++ i, ret == 0 ? "pass" : "fail"); ++ ++ if (ret == 0) { ++ /* Test passed - extend current window */ ++ if (current_len == 0) ++ current_start = i; ++ current_len++; ++ } else { ++ /* Test failed - check if current window is best so far */ ++ if (current_len > max_pass_len) { ++ max_pass_len = current_len; ++ max_pass_start = current_start; ++ } ++ current_len = 0; ++ } ++ } ++ ++ if (current_len > max_pass_len) { ++ max_pass_len = current_len; ++ max_pass_start = current_start; ++ } ++ ++ if (max_pass_len < 3) { ++ dev_err(mmc_dev(host->mmc), "Tuning failed: no stable window found\n"); ++ return -EIO; ++ } ++ ++ final_delay = max_pass_start + max_pass_len / 2; ++ spacemit_sdhci_set_rx_delay(host, final_delay); ++ ret = mmc_send_tuning(host->mmc, opcode, NULL); ++ if (ret) { ++ u8 retry_delays[] = { ++ max_pass_start + max_pass_len / 4, ++ max_pass_start + (3 * max_pass_len) / 4, ++ max_pass_start, ++ max_pass_start + max_pass_len - 1 ++ }; ++ int retry_count = ARRAY_SIZE(retry_delays); ++ ++ dev_warn(mmc_dev(mmc), "Primary delay %d failed, trying alternatives\n", ++ final_delay); ++ ++ for (i = 0; i < retry_count; i++) { ++ if (retry_delays[i] >= SPACEMIT_RX_TUNE_DELAY_MIN && ++ retry_delays[i] <= SPACEMIT_RX_TUNE_DELAY_MAX) { ++ spacemit_sdhci_set_rx_delay(host, retry_delays[i]); ++ ret = mmc_send_tuning(host->mmc, opcode, NULL); ++ if (!ret) { ++ final_delay = retry_delays[i]; ++ dev_info(mmc_dev(mmc), "Retry successful with delay %d\n", ++ final_delay); ++ break; ++ } ++ } ++ } ++ ++ if (ret) { ++ dev_err(mmc_dev(mmc), "All retry attempts failed\n"); ++ return -EIO; ++ } ++ } ++ ++ dev_dbg(mmc_dev(host->mmc), ++ "Tuning successful: window %d-%d, using delay %d\n", ++ max_pass_start, max_pass_start + max_pass_len - 1, final_delay); ++ ++ return 0; ++} ++ + static int spacemit_sdhci_pre_select_hs400(struct mmc_host *mmc) + { + struct sdhci_host *host = mmc_priv(mmc); +@@ -326,6 +497,7 @@ static const struct sdhci_ops spacemit_sdhci_ops = { + .set_bus_width = sdhci_set_bus_width, + .set_clock = spacemit_sdhci_set_clock, + .set_uhs_signaling = spacemit_sdhci_set_uhs_signaling, ++ .platform_execute_tuning = spacemit_sdhci_execute_tuning, + }; + + static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata = { +-- +2.53.0 + diff --git a/SPECS/linux/0202-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch b/SPECS/linux/0202-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch deleted file mode 100644 index fb11073de1..0000000000 --- a/SPECS/linux/0202-FROMLIST-mmc-sdhci-of-k1-add-regulator-and-pinctrl-v.patch +++ /dev/null @@ -1,144 +0,0 @@ -From 4e8659e6189f05da42274b2f8aaecb02d4dd4f96 Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Mon, 11 May 2026 10:53:58 +0200 -Subject: [PATCH 202/269] FROMLIST: mmc: sdhci-of-k1: add regulator and pinctrl - voltage switching support - -Add voltage switching infrastructure for UHS-I modes by integrating both -regulator framework (for supply voltage control) and pinctrl state -switching (for pin drive strength optimization). - -- Add regulator supply parsing and voltage switching callback -- Add optional pinctrl state switching between "default" (3.3V) and - "state_uhs" (1.8V) configurations -- Enable coordinated voltage and pin configuration changes for UHS modes - -This provides complete voltage switching support while maintaining -backward compatibility when pinctrl states are not defined. - -Tested-by: Anand Moon -Tested-by: Trevor Gamblin -Acked-by: Adrian Hunter -Reviewed-by: Troy Mitchell -Tested-by: Vincent Legoll -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-3-ae48c0b2b2cf@gmail.com -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 72 ++++++++++++++++++++++++++++++++++ - 1 file changed, 72 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index 0dd06fc19b85..d9144537032a 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include - - #include "sdhci.h" -@@ -71,6 +72,9 @@ - struct spacemit_sdhci_host { - struct clk *clk_core; - struct clk *clk_io; -+ struct pinctrl *pinctrl; -+ struct pinctrl_state *pinctrl_default; -+ struct pinctrl_state *pinctrl_uhs; - }; - - /* All helper functions will update clr/set while preserve rest bits */ -@@ -219,6 +223,46 @@ static void spacemit_sdhci_pre_hs400_to_hs200(struct mmc_host *mmc) - SPACEMIT_SDHC_PHY_CTRL_REG); - } - -+static int spacemit_sdhci_start_signal_voltage_switch(struct mmc_host *mmc, -+ struct mmc_ios *ios) -+{ -+ struct sdhci_host *host = mmc_priv(mmc); -+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); -+ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); -+ struct pinctrl_state *state; -+ int ret; -+ -+ ret = sdhci_start_signal_voltage_switch(mmc, ios); -+ if (ret) -+ return ret; -+ -+ if (!sdhst->pinctrl) -+ return 0; -+ -+ /* Select appropriate pinctrl state based on signal voltage */ -+ switch (ios->signal_voltage) { -+ case MMC_SIGNAL_VOLTAGE_330: -+ state = sdhst->pinctrl_default; -+ break; -+ case MMC_SIGNAL_VOLTAGE_180: -+ state = sdhst->pinctrl_uhs; -+ break; -+ default: -+ dev_warn(mmc_dev(mmc), "unsupported voltage %d\n", ios->signal_voltage); -+ return 0; -+ } -+ -+ ret = pinctrl_select_state(sdhst->pinctrl, state); -+ if (ret) { -+ dev_warn(mmc_dev(mmc), "failed to select pinctrl state: %d\n", ret); -+ return 0; -+ } -+ dev_dbg(mmc_dev(mmc), "switched to %s pinctrl state\n", -+ ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 ? "UHS" : "default"); -+ -+ return 0; -+} -+ - static inline int spacemit_sdhci_get_clocks(struct device *dev, - struct sdhci_pltfm_host *pltfm_host) - { -@@ -252,6 +296,30 @@ static inline int spacemit_sdhci_get_resets(struct device *dev) - return 0; - } - -+static inline void spacemit_sdhci_get_pins(struct device *dev, -+ struct sdhci_pltfm_host *pltfm_host) -+{ -+ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); -+ -+ sdhst->pinctrl = devm_pinctrl_get(dev); -+ if (IS_ERR(sdhst->pinctrl)) { -+ sdhst->pinctrl = NULL; -+ dev_dbg(dev, "pinctrl not available, voltage switching will work without it\n"); -+ return; -+ } -+ -+ sdhst->pinctrl_default = pinctrl_lookup_state(sdhst->pinctrl, "default"); -+ if (IS_ERR(sdhst->pinctrl_default)) -+ sdhst->pinctrl_default = NULL; -+ -+ sdhst->pinctrl_uhs = pinctrl_lookup_state(sdhst->pinctrl, "uhs"); -+ if (IS_ERR(sdhst->pinctrl_uhs)) -+ sdhst->pinctrl_uhs = NULL; -+ -+ dev_dbg(dev, "pinctrl setup: default=%p, uhs=%p\n", -+ sdhst->pinctrl_default, sdhst->pinctrl_uhs); -+} -+ - static const struct sdhci_ops spacemit_sdhci_ops = { - .get_max_clock = spacemit_sdhci_clk_get_max_clock, - .reset = spacemit_sdhci_reset, -@@ -324,6 +392,10 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) - - host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY; - -+ spacemit_sdhci_get_pins(dev, pltfm_host); -+ -+ host->mmc_host_ops.start_signal_voltage_switch = spacemit_sdhci_start_signal_voltage_switch; -+ - ret = spacemit_sdhci_get_clocks(dev, pltfm_host); - if (ret) - goto err_pltfm; --- -2.53.0 - diff --git a/SPECS/linux/0203-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch b/SPECS/linux/0203-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch deleted file mode 100644 index 0c94367660..0000000000 --- a/SPECS/linux/0203-FROMLIST-mmc-sdhci-of-k1-add-comprehensive-SDR-tunin.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 0ae178fac6f2e58e9f5710357bd259631f15fa7e Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Mon, 11 May 2026 10:53:59 +0200 -Subject: [PATCH 203/269] FROMLIST: mmc: sdhci-of-k1: add comprehensive SDR - tuning support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Implement software tuning algorithm to enable UHS-I SDR modes for SD -card operation and HS200 mode for eMMC. This adds both TX and RX delay -line tuning based on the SpacemiT K1 controller capabilities. - -Algorithm features: -- Add tuning register definitions (RX_CFG, DLINE_CTRL, DLINE_CFG) -- Conditional tuning: only for high-speed modes (≥100MHz) -- TX tuning: configure transmit delay line with optimal values - (dline_reg=0, delaycode=127) to ensure optimal signal output timing -- RX tuning: single-pass window detection algorithm testing full - delay range (0-255) to find optimal receive timing window -- Retry mechanism: multiple fallback delays within optimal window - for improved reliability - -Tested-by: Anand Moon -Acked-by: Adrian Hunter -Tested-by: Trevor Gamblin -Tested-by: Vincent Legoll -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260511-orangepi-sd-card-uhs-v9-4-ae48c0b2b2cf@gmail.com -Signed-off-by: Han Gao ---- - drivers/mmc/host/sdhci-of-k1.c | 172 +++++++++++++++++++++++++++++++++ - 1 file changed, 172 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c -index d9144537032a..37b0911e7cf2 100644 ---- a/drivers/mmc/host/sdhci-of-k1.c -+++ b/drivers/mmc/host/sdhci-of-k1.c -@@ -69,6 +69,28 @@ - #define SDHC_PHY_DRIVE_SEL GENMASK(2, 0) - #define SDHC_RX_BIAS_CTRL BIT(5) - -+#define SPACEMIT_SDHC_RX_CFG_REG 0x118 -+#define SDHC_RX_SDCLK_SEL0_MASK GENMASK(1, 0) -+#define SDHC_RX_SDCLK_SEL1_MASK GENMASK(3, 2) -+#define SDHC_RX_SDCLK_SEL1 FIELD_PREP(SDHC_RX_SDCLK_SEL1_MASK, 1) -+ -+#define SPACEMIT_SDHC_DLINE_CTRL_REG 0x130 -+#define SDHC_DLINE_PU BIT(0) -+#define SDHC_RX_DLINE_CODE_MASK GENMASK(23, 16) -+#define SDHC_TX_DLINE_CODE_MASK GENMASK(31, 24) -+ -+#define SPACEMIT_SDHC_DLINE_CFG_REG 0x134 -+#define SDHC_RX_DLINE_REG_MASK GENMASK(7, 0) -+#define SDHC_RX_DLINE_GAIN BIT(8) -+#define SDHC_TX_DLINE_REG_MASK GENMASK(23, 16) -+ -+#define SPACEMIT_RX_DLINE_REG 9 -+#define SPACEMIT_RX_TUNE_DELAY_MIN 0x0 -+#define SPACEMIT_RX_TUNE_DELAY_MAX 0xFF -+ -+#define SPACEMIT_TX_TUNING_DLINE_REG 0x00 -+#define SPACEMIT_TX_TUNING_DELAYCODE 127 -+ - struct spacemit_sdhci_host { - struct clk *clk_core; - struct clk *clk_io; -@@ -96,6 +118,50 @@ static inline void spacemit_sdhci_clrsetbits(struct sdhci_host *host, u32 clr, u - sdhci_writel(host, val, reg); - } - -+static void spacemit_sdhci_set_rx_delay(struct sdhci_host *host, u8 delay) -+{ -+ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_CODE_MASK, -+ FIELD_PREP(SDHC_RX_DLINE_CODE_MASK, delay), -+ SPACEMIT_SDHC_DLINE_CTRL_REG); -+} -+ -+static void spacemit_sdhci_set_tx_delay(struct sdhci_host *host, u8 delay) -+{ -+ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_CODE_MASK, -+ FIELD_PREP(SDHC_TX_DLINE_CODE_MASK, delay), -+ SPACEMIT_SDHC_DLINE_CTRL_REG); -+} -+ -+static void spacemit_sdhci_set_tx_dline_reg(struct sdhci_host *host, u8 dline_reg) -+{ -+ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_REG_MASK, -+ FIELD_PREP(SDHC_TX_DLINE_REG_MASK, dline_reg), -+ SPACEMIT_SDHC_DLINE_CFG_REG); -+} -+ -+static void spacemit_sdhci_tx_tuning_prepare(struct sdhci_host *host) -+{ -+ spacemit_sdhci_setbits(host, SDHC_TX_MUX_SEL, SPACEMIT_SDHC_TX_CFG_REG); -+ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); -+ udelay(5); -+} -+ -+static void spacemit_sdhci_prepare_tuning(struct sdhci_host *host) -+{ -+ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_REG_MASK, -+ FIELD_PREP(SDHC_RX_DLINE_REG_MASK, SPACEMIT_RX_DLINE_REG), -+ SPACEMIT_SDHC_DLINE_CFG_REG); -+ -+ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); -+ udelay(5); -+ -+ spacemit_sdhci_clrsetbits(host, SDHC_RX_SDCLK_SEL1_MASK, SDHC_RX_SDCLK_SEL1, -+ SPACEMIT_SDHC_RX_CFG_REG); -+ -+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) -+ spacemit_sdhci_setbits(host, SDHC_HS200_USE_RFIFO, SPACEMIT_SDHC_PHY_FUNC_REG); -+} -+ - static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) - { - sdhci_reset(host, mask); -@@ -191,6 +257,111 @@ static unsigned int spacemit_sdhci_clk_get_max_clock(struct sdhci_host *host) - return clk_get_rate(pltfm_host->clk); - } - -+static int spacemit_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) -+{ -+ int current_len = 0, current_start = 0; -+ int max_pass_len = 0, max_pass_start = 0; -+ struct mmc_host *mmc = host->mmc; -+ struct mmc_ios ios = mmc->ios; -+ u8 final_delay; -+ int ret = 0; -+ int i; -+ -+ /* -+ * Tuning is required for SDR50/SDR104, HS200/HS400 cards and -+ * if clock frequency is greater than 100MHz in these modes. -+ */ -+ if (host->clock < 100 * 1000 * 1000 || -+ !(ios.timing == MMC_TIMING_MMC_HS200 || -+ ios.timing == MMC_TIMING_UHS_SDR50 || -+ ios.timing == MMC_TIMING_UHS_SDR104)) -+ return 0; -+ -+ if (mmc->caps2 & MMC_CAP2_NO_MMC) { -+ spacemit_sdhci_set_tx_dline_reg(host, SPACEMIT_TX_TUNING_DLINE_REG); -+ spacemit_sdhci_set_tx_delay(host, SPACEMIT_TX_TUNING_DELAYCODE); -+ spacemit_sdhci_tx_tuning_prepare(host); -+ -+ dev_dbg(mmc_dev(host->mmc), "TX tuning: dline_reg=%d, delaycode=%d\n", -+ SPACEMIT_TX_TUNING_DLINE_REG, SPACEMIT_TX_TUNING_DELAYCODE); -+ } -+ -+ spacemit_sdhci_prepare_tuning(host); -+ -+ for (i = SPACEMIT_RX_TUNE_DELAY_MIN; i <= SPACEMIT_RX_TUNE_DELAY_MAX; i++) { -+ spacemit_sdhci_set_rx_delay(host, i); -+ ret = mmc_send_tuning(host->mmc, opcode, NULL); -+ -+ dev_dbg(mmc_dev(host->mmc), "RX delay %d: %s\n", -+ i, ret == 0 ? "pass" : "fail"); -+ -+ if (ret == 0) { -+ /* Test passed - extend current window */ -+ if (current_len == 0) -+ current_start = i; -+ current_len++; -+ } else { -+ /* Test failed - check if current window is best so far */ -+ if (current_len > max_pass_len) { -+ max_pass_len = current_len; -+ max_pass_start = current_start; -+ } -+ current_len = 0; -+ } -+ } -+ -+ if (current_len > max_pass_len) { -+ max_pass_len = current_len; -+ max_pass_start = current_start; -+ } -+ -+ if (max_pass_len < 3) { -+ dev_err(mmc_dev(host->mmc), "Tuning failed: no stable window found\n"); -+ return -EIO; -+ } -+ -+ final_delay = max_pass_start + max_pass_len / 2; -+ spacemit_sdhci_set_rx_delay(host, final_delay); -+ ret = mmc_send_tuning(host->mmc, opcode, NULL); -+ if (ret) { -+ u8 retry_delays[] = { -+ max_pass_start + max_pass_len / 4, -+ max_pass_start + (3 * max_pass_len) / 4, -+ max_pass_start, -+ max_pass_start + max_pass_len - 1 -+ }; -+ int retry_count = ARRAY_SIZE(retry_delays); -+ -+ dev_warn(mmc_dev(mmc), "Primary delay %d failed, trying alternatives\n", -+ final_delay); -+ -+ for (i = 0; i < retry_count; i++) { -+ if (retry_delays[i] >= SPACEMIT_RX_TUNE_DELAY_MIN && -+ retry_delays[i] <= SPACEMIT_RX_TUNE_DELAY_MAX) { -+ spacemit_sdhci_set_rx_delay(host, retry_delays[i]); -+ ret = mmc_send_tuning(host->mmc, opcode, NULL); -+ if (!ret) { -+ final_delay = retry_delays[i]; -+ dev_info(mmc_dev(mmc), "Retry successful with delay %d\n", -+ final_delay); -+ break; -+ } -+ } -+ } -+ -+ if (ret) { -+ dev_err(mmc_dev(mmc), "All retry attempts failed\n"); -+ return -EIO; -+ } -+ } -+ -+ dev_dbg(mmc_dev(host->mmc), -+ "Tuning successful: window %d-%d, using delay %d\n", -+ max_pass_start, max_pass_start + max_pass_len - 1, final_delay); -+ -+ return 0; -+} -+ - static int spacemit_sdhci_pre_select_hs400(struct mmc_host *mmc) - { - struct sdhci_host *host = mmc_priv(mmc); -@@ -326,6 +497,7 @@ static const struct sdhci_ops spacemit_sdhci_ops = { - .set_bus_width = sdhci_set_bus_width, - .set_clock = spacemit_sdhci_set_clock, - .set_uhs_signaling = spacemit_sdhci_set_uhs_signaling, -+ .platform_execute_tuning = spacemit_sdhci_execute_tuning, - }; - - static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata = { --- -2.53.0 - diff --git a/SPECS/linux/0203-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch b/SPECS/linux/0203-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch new file mode 100644 index 0000000000..15598d191f --- /dev/null +++ b/SPECS/linux/0203-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch @@ -0,0 +1,105 @@ +From caad245a3c358af9443ce06c4d8ab79191b28709 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Fri, 15 May 2026 12:48:59 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1: add SD card + controller and pinctrl support + +Add SD card controller infrastructure for SpacemiT K1 SoC with complete +pinctrl support for both standard and UHS modes. + +- Add sdhci0 controller definition with clocks, resets and interrupts +- Add mmc1_cfg pinctrl for 3.3V standard SD operation +- Add mmc1_uhs_cfg pinctrl for 1.8V UHS high-speed operation +- Configure appropriate drive strength and power-source properties + +This provides complete SD card infrastructure that K1-based boards can +enable. + +Tested-by: Anand Moon +Tested-by: Trevor Gamblin +Tested-by: Vincent Legoll +Reviewed-by: Troy Mitchell +Signed-off-by: Iker Pedrosa +Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-1-094af27e310d@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 40 ++++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++ + 2 files changed, 53 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +index 34d88334e95e..4e9a62d0e85b 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +@@ -590,4 +590,44 @@ ssp3-0-frm-pins { + power-source = <3300>; + }; + }; ++ ++ mmc1_cfg: mmc1-cfg { ++ mmc1-data-cmd-pins { ++ pinmux = , /* mmc1_d3 */ ++ , /* mmc1_d2 */ ++ , /* mmc1_d1 */ ++ , /* mmc1_d0 */ ++ ; /* mmc1_cmd */ ++ bias-pull-up = <1>; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ ++ mmc1-clk-pins { ++ pinmux = ; /* mmc1_clk */ ++ bias-pull-down = <1>; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ }; ++ ++ mmc1_uhs_cfg: mmc1-uhs-cfg { ++ mmc1-data-cmd-pins { ++ pinmux = , /* mmc1_d3 */ ++ , /* mmc1_d2 */ ++ , /* mmc1_d1 */ ++ , /* mmc1_d0 */ ++ ; /* mmc1_cmd */ ++ bias-pull-up = <1>; ++ drive-strength = <42>; ++ power-source = <1800>; ++ }; ++ ++ mmc1-clk-pins { ++ pinmux = ; /* mmc1_clk */ ++ bias-pull-down = <1>; ++ drive-strength = <42>; ++ power-source = <1800>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 8774a00a854b..4a359190f633 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -1323,6 +1323,19 @@ usb_dwc3: usb@c0a00000 { + status = "disabled"; + }; + ++ sdhci0: mmc@d4280000 { ++ compatible = "spacemit,k1-sdhci"; ++ reg = <0x0 0xd4280000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_SDH_AXI>, ++ <&syscon_apmu CLK_SDH0>; ++ clock-names = "core", "io"; ++ resets = <&syscon_apmu RESET_SDH_AXI>, ++ <&syscon_apmu RESET_SDH0>; ++ reset-names = "axi", "sdh"; ++ interrupts = <99>; ++ status = "disabled"; ++ }; ++ + emmc: mmc@d4281000 { + compatible = "spacemit,k1-sdhci"; + reg = <0x0 0xd4281000 0x0 0x200>; +-- +2.53.0 + diff --git a/SPECS/linux/0204-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch b/SPECS/linux/0204-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch deleted file mode 100644 index ca51dc676d..0000000000 --- a/SPECS/linux/0204-FROMLIST-riscv-dts-spacemit-k1-add-SD-card-controlle.patch +++ /dev/null @@ -1,105 +0,0 @@ -From cd98b0f82ec00dbc4ce5fcaf71e78f1a53a5fc77 Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Fri, 15 May 2026 12:48:59 +0200 -Subject: [PATCH 204/269] FROMLIST: riscv: dts: spacemit: k1: add SD card - controller and pinctrl support - -Add SD card controller infrastructure for SpacemiT K1 SoC with complete -pinctrl support for both standard and UHS modes. - -- Add sdhci0 controller definition with clocks, resets and interrupts -- Add mmc1_cfg pinctrl for 3.3V standard SD operation -- Add mmc1_uhs_cfg pinctrl for 1.8V UHS high-speed operation -- Configure appropriate drive strength and power-source properties - -This provides complete SD card infrastructure that K1-based boards can -enable. - -Tested-by: Anand Moon -Tested-by: Trevor Gamblin -Tested-by: Vincent Legoll -Reviewed-by: Troy Mitchell -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-1-094af27e310d@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 40 ++++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++ - 2 files changed, 53 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -index 34d88334e95e..4e9a62d0e85b 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi -@@ -590,4 +590,44 @@ ssp3-0-frm-pins { - power-source = <3300>; - }; - }; -+ -+ mmc1_cfg: mmc1-cfg { -+ mmc1-data-cmd-pins { -+ pinmux = , /* mmc1_d3 */ -+ , /* mmc1_d2 */ -+ , /* mmc1_d1 */ -+ , /* mmc1_d0 */ -+ ; /* mmc1_cmd */ -+ bias-pull-up = <1>; -+ drive-strength = <19>; -+ power-source = <3300>; -+ }; -+ -+ mmc1-clk-pins { -+ pinmux = ; /* mmc1_clk */ -+ bias-pull-down = <1>; -+ drive-strength = <19>; -+ power-source = <3300>; -+ }; -+ }; -+ -+ mmc1_uhs_cfg: mmc1-uhs-cfg { -+ mmc1-data-cmd-pins { -+ pinmux = , /* mmc1_d3 */ -+ , /* mmc1_d2 */ -+ , /* mmc1_d1 */ -+ , /* mmc1_d0 */ -+ ; /* mmc1_cmd */ -+ bias-pull-up = <1>; -+ drive-strength = <42>; -+ power-source = <1800>; -+ }; -+ -+ mmc1-clk-pins { -+ pinmux = ; /* mmc1_clk */ -+ bias-pull-down = <1>; -+ drive-strength = <42>; -+ power-source = <1800>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi -index 8774a00a854b..4a359190f633 100644 ---- a/arch/riscv/boot/dts/spacemit/k1.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi -@@ -1323,6 +1323,19 @@ usb_dwc3: usb@c0a00000 { - status = "disabled"; - }; - -+ sdhci0: mmc@d4280000 { -+ compatible = "spacemit,k1-sdhci"; -+ reg = <0x0 0xd4280000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_SDH_AXI>, -+ <&syscon_apmu CLK_SDH0>; -+ clock-names = "core", "io"; -+ resets = <&syscon_apmu RESET_SDH_AXI>, -+ <&syscon_apmu RESET_SDH0>; -+ reset-names = "axi", "sdh"; -+ interrupts = <99>; -+ status = "disabled"; -+ }; -+ - emmc: mmc@d4281000 { - compatible = "spacemit,k1-sdhci"; - reg = <0x0 0xd4281000 0x0 0x200>; --- -2.53.0 - diff --git a/SPECS/linux/0204-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch b/SPECS/linux/0204-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch new file mode 100644 index 0000000000..3535201c26 --- /dev/null +++ b/SPECS/linux/0204-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch @@ -0,0 +1,77 @@ +From f7cc846d57fe7d2e3a40125c103f110237c5c6bb Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Fri, 15 May 2026 12:49:00 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-orangepi-rv2: add SD + card support with UHS modes + +Add complete SD card controller support with UHS high-speed modes. + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with GPIO_ACTIVE_LOW logic +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) + +This enables full SD card functionality including high-speed UHS modes +for improved performance. + +Tested-by: Anand Moon +Tested-by: Trevor Gamblin +Tested-by: Michael Opdenacker +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-2-094af27e310d@gmail.com +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 22 ++++++++++++++++++- + 1 file changed, 21 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index c95ca38e3d4a..bd40bc9011e2 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -17,6 +17,8 @@ aliases { + serial0 = &uart0; + ethernet0 = ð0; + ethernet1 = ð1; ++ mmc0 = &emmc; ++ mmc1 = &sdhci0; + }; + + chosen { +@@ -202,7 +204,7 @@ buck6 { + regulator-always-on; + }; + +- aldo1 { ++ aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; +@@ -319,3 +321,21 @@ hub_3_0: hub@2 { + vdd-supply = <&vcc_5v0>; + }; + }; ++ ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) GPIO_ACTIVE_LOW>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4_3v3>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux/0205-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch b/SPECS/linux/0205-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch new file mode 100644 index 0000000000..64cdab51e8 --- /dev/null +++ b/SPECS/linux/0205-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch @@ -0,0 +1,88 @@ +From 37fe9b7f8a42515c66f664767b4a9c584340ea16 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Fri, 15 May 2026 12:49:01 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: add SD + card support with UHS modes + +Add complete SD card controller support with UHS high-speed modes. + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with GPIO_ACTIVE_LOW and internal pull-up + support +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) + +This enables full SD card functionality including high-speed UHS modes +for improved performance. + +Suggested-by: Anand Moon +Tested-by: Anand Moon +Tested-by: Margherita Milani +Tested-by: Aurelien Jarno +Reviewed-by: Aurelien Jarno +Signed-off-by: Iker Pedrosa +Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-3-094af27e310d@gmail.com +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 24 +++++++++++++++++-- + 1 file changed, 22 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index b48a485f954b..b15f4c36e622 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -18,6 +18,8 @@ aliases { + spi3 = &spi3; + i2c2 = &i2c2; + i2c8 = &i2c8; ++ mmc0 = &emmc; ++ mmc1 = &sdhci0; + }; + + chosen { +@@ -267,7 +269,7 @@ buck3_1v8: buck3 { + regulator-always-on; + }; + +- buck4 { ++ buck4: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; +@@ -288,7 +290,7 @@ buck6 { + regulator-always-on; + }; + +- aldo1 { ++ aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; +@@ -421,3 +423,21 @@ hub_3_0: hub@2 { + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; + }; ++ ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux/0205-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch b/SPECS/linux/0205-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch deleted file mode 100644 index e8b49a8c9c..0000000000 --- a/SPECS/linux/0205-FROMLIST-riscv-dts-spacemit-k1-orangepi-rv2-add-SD-c.patch +++ /dev/null @@ -1,77 +0,0 @@ -From aface59b77b31d881dcc65adfb6e521b5c38604d Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Fri, 15 May 2026 12:49:00 +0200 -Subject: [PATCH 205/269] FROMLIST: riscv: dts: spacemit: k1-orangepi-rv2: add - SD card support with UHS modes - -Add complete SD card controller support with UHS high-speed modes. - -- Enable sdhci0 controller with 4-bit bus width -- Configure card detect GPIO with GPIO_ACTIVE_LOW logic -- Connect vmmc-supply to buck4 for 3.3V card power -- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching -- Add dual pinctrl states for voltage-dependent pin configuration -- Support UHS-I SDR25, SDR50, and SDR104 modes -- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) - -This enables full SD card functionality including high-speed UHS modes -for improved performance. - -Tested-by: Anand Moon -Tested-by: Trevor Gamblin -Tested-by: Michael Opdenacker -Tested-by: Vincent Legoll -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-2-094af27e310d@gmail.com -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-rv2.dts | 22 ++++++++++++++++++- - 1 file changed, 21 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index c95ca38e3d4a..bd40bc9011e2 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -17,6 +17,8 @@ aliases { - serial0 = &uart0; - ethernet0 = ð0; - ethernet1 = ð1; -+ mmc0 = &emmc; -+ mmc1 = &sdhci0; - }; - - chosen { -@@ -202,7 +204,7 @@ buck6 { - regulator-always-on; - }; - -- aldo1 { -+ aldo1: aldo1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; -@@ -319,3 +321,21 @@ hub_3_0: hub@2 { - vdd-supply = <&vcc_5v0>; - }; - }; -+ -+&sdhci0 { -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&mmc1_cfg>; -+ pinctrl-1 = <&mmc1_uhs_cfg>; -+ bus-width = <4>; -+ cd-gpios = <&gpio K1_GPIO(80) GPIO_ACTIVE_LOW>; -+ no-mmc; -+ no-sdio; -+ disable-wp; -+ cap-sd-highspeed; -+ vmmc-supply = <&buck4_3v3>; -+ vqmmc-supply = <&aldo1>; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux/0206-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch b/SPECS/linux/0206-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch deleted file mode 100644 index 373cef797d..0000000000 --- a/SPECS/linux/0206-FROMLIST-riscv-dts-spacemit-k1-bananapi-f3-add-SD-ca.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 0a3b6f9ff4a910ed5cb31bb169d35abbda4f28c8 Mon Sep 17 00:00:00 2001 -From: Iker Pedrosa -Date: Fri, 15 May 2026 12:49:01 +0200 -Subject: [PATCH 206/269] FROMLIST: riscv: dts: spacemit: k1-bananapi-f3: add - SD card support with UHS modes - -Add complete SD card controller support with UHS high-speed modes. - -- Enable sdhci0 controller with 4-bit bus width -- Configure card detect GPIO with GPIO_ACTIVE_LOW and internal pull-up - support -- Connect vmmc-supply to buck4 for 3.3V card power -- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching -- Add dual pinctrl states for voltage-dependent pin configuration -- Support UHS-I SDR25, SDR50, and SDR104 modes -- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) - -This enables full SD card functionality including high-speed UHS modes -for improved performance. - -Suggested-by: Anand Moon -Tested-by: Anand Moon -Tested-by: Margherita Milani -Tested-by: Aurelien Jarno -Reviewed-by: Aurelien Jarno -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-3-094af27e310d@gmail.com -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-bananapi-f3.dts | 24 +++++++++++++++++-- - 1 file changed, 22 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -index b48a485f954b..b15f4c36e622 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts -@@ -18,6 +18,8 @@ aliases { - spi3 = &spi3; - i2c2 = &i2c2; - i2c8 = &i2c8; -+ mmc0 = &emmc; -+ mmc1 = &sdhci0; - }; - - chosen { -@@ -267,7 +269,7 @@ buck3_1v8: buck3 { - regulator-always-on; - }; - -- buck4 { -+ buck4: buck4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <5000>; -@@ -288,7 +290,7 @@ buck6 { - regulator-always-on; - }; - -- aldo1 { -+ aldo1: aldo1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; -@@ -421,3 +423,21 @@ hub_3_0: hub@2 { - reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; - }; - }; -+ -+&sdhci0 { -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&mmc1_cfg>; -+ pinctrl-1 = <&mmc1_uhs_cfg>; -+ bus-width = <4>; -+ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; -+ no-mmc; -+ no-sdio; -+ disable-wp; -+ cap-sd-highspeed; -+ vmmc-supply = <&buck4>; -+ vqmmc-supply = <&aldo1>; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux/0206-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch b/SPECS/linux/0206-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch new file mode 100644 index 0000000000..c719fedcde --- /dev/null +++ b/SPECS/linux/0206-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch @@ -0,0 +1,110 @@ +From eaefeed7d7ce8a2654aab69f1e84d5e767b38d83 Mon Sep 17 00:00:00 2001 +From: Trevor Gamblin +Date: Fri, 15 May 2026 12:49:02 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add SD + card support with UHS modes + +Update the Muse Pi Pro devicetree with SD card support to match what +was done for the OrangePi RV2 in [1]. More precisely: + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with internal pull-up support +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) +- Update PMIC configuration to use per-regulator supply properties + +[1] https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# + +Tested-by: Andre Heider +Signed-off-by: Trevor Gamblin +Signed-off-by: Iker Pedrosa +Link: https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# +Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-4-094af27e310d@gmail.com +Signed-off-by: Han Gao +--- + .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 60 +++++++++++++++++++ + 1 file changed, 60 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +index c8bf776511c9..9952014701f7 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +@@ -19,8 +19,20 @@ aliases { + serial0 = &uart0; + i2c2 = &i2c2; + i2c8 = &i2c8; ++ mmc0 = &emmc; ++ mmc1 = &sdhci0; + }; + ++ reg_vcc_4v: vcc-4v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_4v"; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ + chosen { + stdout-path = "serial0:115200n8"; + }; +@@ -399,3 +411,51 @@ hub_3_0: hub@2 { + reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ + }; + }; ++ ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8_cfg>; ++ status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ vin4-supply = <®_vcc_4v>; ++ aldoin-supply = <®_vcc_4v>; ++ ++ regulators { ++ buck4: buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1: aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; ++ ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; +-- +2.53.0 + diff --git a/SPECS/linux/0207-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch b/SPECS/linux/0207-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch deleted file mode 100644 index 77381028df..0000000000 --- a/SPECS/linux/0207-FROMLIST-riscv-dts-spacemit-k1-musepi-pro-add-SD-car.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 87215d8ac4bdb3c68db95d70e7586e7eff4b304e Mon Sep 17 00:00:00 2001 -From: Trevor Gamblin -Date: Fri, 15 May 2026 12:49:02 +0200 -Subject: [PATCH 207/269] FROMLIST: riscv: dts: spacemit: k1-musepi-pro: add SD - card support with UHS modes - -Update the Muse Pi Pro devicetree with SD card support to match what -was done for the OrangePi RV2 in [1]. More precisely: - -- Enable sdhci0 controller with 4-bit bus width -- Configure card detect GPIO with internal pull-up support -- Connect vmmc-supply to buck4 for 3.3V card power -- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching -- Add dual pinctrl states for voltage-dependent pin configuration -- Support UHS-I SDR25, SDR50, and SDR104 modes -- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) -- Update PMIC configuration to use per-regulator supply properties - -[1] https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# - -Tested-by: Andre Heider -Signed-off-by: Trevor Gamblin -Signed-off-by: Iker Pedrosa -Link: https://lore.kernel.org/linux-riscv/20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com/T/# -Link: https://lore.kernel.org/r/20260515-orangepi-sd-card-uhs-v10-4-094af27e310d@gmail.com -Signed-off-by: Han Gao ---- - .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 60 +++++++++++++++++++ - 1 file changed, 60 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -index c8bf776511c9..9952014701f7 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts -@@ -19,8 +19,20 @@ aliases { - serial0 = &uart0; - i2c2 = &i2c2; - i2c8 = &i2c8; -+ mmc0 = &emmc; -+ mmc1 = &sdhci0; - }; - -+ reg_vcc_4v: vcc-4v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_4v"; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ - chosen { - stdout-path = "serial0:115200n8"; - }; -@@ -399,3 +411,51 @@ hub_3_0: hub@2 { - reset-gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_LOW>; /* HUB_RST */ - }; - }; -+ -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin4-supply = <®_vcc_4v>; -+ aldoin-supply = <®_vcc_4v>; -+ -+ regulators { -+ buck4: buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1: aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -+}; -+ -+&sdhci0 { -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&mmc1_cfg>; -+ pinctrl-1 = <&mmc1_uhs_cfg>; -+ bus-width = <4>; -+ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; -+ no-mmc; -+ no-sdio; -+ disable-wp; -+ cap-sd-highspeed; -+ vmmc-supply = <&buck4>; -+ vqmmc-supply = <&aldo1>; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; --- -2.53.0 - diff --git a/SPECS/linux/0207-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch b/SPECS/linux/0207-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch new file mode 100644 index 0000000000..783acaa1c8 --- /dev/null +++ b/SPECS/linux/0207-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch @@ -0,0 +1,96 @@ +From 678318a03d0cb8348eaa0490f1a93d6fffee90bf Mon Sep 17 00:00:00 2001 +From: Thomas Gerner +Date: Thu, 14 May 2026 20:32:01 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: thead: Enable wifi on the + BeagleV-Ahead + +The BeagleV-Ahead board uses an AP6203BM WiFi chip from AMPAK Technology +Inc. connected to SDIO1. The chip is compatible to the broadcom wireless +driver. + +The AP6203BM is a dual-band 2.4GHz/5GHz Wi-Fi 4 (802.11a/b/g/n) and +Bluetooth 5.4 module. Bluetooth is not enabled by this patch. + +Signed-off-by: Thomas Gerner +Link: https://lore.kernel.org/r/20260514183510.234063-1-thomas.gerner@muenchen-mail.de +Signed-off-by: Han Gao +--- + .../boot/dts/thead/th1520-beaglev-ahead.dts | 48 +++++++++++++++++++ + 1 file changed, 48 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +index 91f3f9b987bc..e16484a47653 100644 +--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts ++++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +@@ -86,6 +86,11 @@ hdmi_con_in: endpoint { + }; + }; + }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ ++ }; + }; + + &osc { +@@ -239,6 +244,28 @@ rx-pins { + slew-rate = <0>; + }; + }; ++ ++ wifi_pins: wifi-0 { ++ host-wake-pins { ++ pins = "GPIO2_25"; ++ function = "gpio"; ++ bias-disable; ++ drive-strength = <1>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ ++ reg-on-pins { ++ pins = "GPIO2_31"; ++ function = "gpio"; ++ bias-disable; ++ drive-strength = <3>; ++ input-disable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; + }; + + &sdio0 { +@@ -247,6 +274,27 @@ &sdio0 { + status = "okay"; + }; + ++&sdio1 { ++ bus-width = <4>; ++ max-frequency = <198000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ non-removable; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ status = "okay"; ++ ++ wifi@1 { ++ compatible = "cypress,cyw43012-fmac", "brcm,bcm4329-fmac"; ++ reg = <1>; ++ interrupt-parent = <&gpio2>; ++ interrupts = <25 IRQ_TYPE_EDGE_RISING>; ++ interrupt-names = "host-wake"; ++ }; ++}; ++ + &dpu { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux/0208-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch b/SPECS/linux/0208-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch deleted file mode 100644 index 181b9c2bb9..0000000000 --- a/SPECS/linux/0208-FROMLIST-riscv-dts-thead-Enable-wifi-on-the-BeagleV-.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 007d756f29c8ccb5746866f75acf9be79a24984a Mon Sep 17 00:00:00 2001 -From: Thomas Gerner -Date: Thu, 14 May 2026 20:32:01 +0200 -Subject: [PATCH 208/269] FROMLIST: riscv: dts: thead: Enable wifi on the - BeagleV-Ahead - -The BeagleV-Ahead board uses an AP6203BM WiFi chip from AMPAK Technology -Inc. connected to SDIO1. The chip is compatible to the broadcom wireless -driver. - -The AP6203BM is a dual-band 2.4GHz/5GHz Wi-Fi 4 (802.11a/b/g/n) and -Bluetooth 5.4 module. Bluetooth is not enabled by this patch. - -Signed-off-by: Thomas Gerner -Link: https://lore.kernel.org/r/20260514183510.234063-1-thomas.gerner@muenchen-mail.de -Signed-off-by: Han Gao ---- - .../boot/dts/thead/th1520-beaglev-ahead.dts | 48 +++++++++++++++++++ - 1 file changed, 48 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -index 91f3f9b987bc..e16484a47653 100644 ---- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts -@@ -86,6 +86,11 @@ hdmi_con_in: endpoint { - }; - }; - }; -+ -+ wifi_pwrseq: wifi-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ -+ }; - }; - - &osc { -@@ -239,6 +244,28 @@ rx-pins { - slew-rate = <0>; - }; - }; -+ -+ wifi_pins: wifi-0 { -+ host-wake-pins { -+ pins = "GPIO2_25"; -+ function = "gpio"; -+ bias-disable; -+ drive-strength = <1>; -+ input-enable; -+ input-schmitt-disable; -+ slew-rate = <0>; -+ }; -+ -+ reg-on-pins { -+ pins = "GPIO2_31"; -+ function = "gpio"; -+ bias-disable; -+ drive-strength = <3>; -+ input-disable; -+ input-schmitt-disable; -+ slew-rate = <0>; -+ }; -+ }; - }; - - &sdio0 { -@@ -247,6 +274,27 @@ &sdio0 { - status = "okay"; - }; - -+&sdio1 { -+ bus-width = <4>; -+ max-frequency = <198000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_pins>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ non-removable; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ status = "okay"; -+ -+ wifi@1 { -+ compatible = "cypress,cyw43012-fmac", "brcm,bcm4329-fmac"; -+ reg = <1>; -+ interrupt-parent = <&gpio2>; -+ interrupts = <25 IRQ_TYPE_EDGE_RISING>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ - &dpu { - status = "okay"; - }; --- -2.53.0 - diff --git a/SPECS/linux/0208-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch b/SPECS/linux/0208-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch new file mode 100644 index 0000000000..1f3cf3e18b --- /dev/null +++ b/SPECS/linux/0208-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch @@ -0,0 +1,47 @@ +From ed9ce6669c079d867ab5bb717a384142dadf4bdc Mon Sep 17 00:00:00 2001 +From: Florian Schmaus +Date: Tue, 12 May 2026 08:32:31 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: module: Use generic cmp_int() instead + of custom cmp_3way() + +The module-sections.c file defines a custom cmp_3way() macro to perform +3-way comparisons during relocation sorting. + +Instead of maintaining our own implementation, use the generic +cmp_int() macro provided by the already included . This +removes redundant code and relies on standard kernel interfaces. + +Signed-off-by: Florian Schmaus +Link: https://lore.kernel.org/r/20260512063231.708256-1-florian.schmaus@codasip.com +Signed-off-by: Han Gao +--- + arch/riscv/kernel/module-sections.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/arch/riscv/kernel/module-sections.c b/arch/riscv/kernel/module-sections.c +index 1675cbad8619..33750a51f157 100644 +--- a/arch/riscv/kernel/module-sections.c ++++ b/arch/riscv/kernel/module-sections.c +@@ -56,17 +56,15 @@ unsigned long module_emit_plt_entry(struct module *mod, unsigned long val) + return (unsigned long)&plt[i]; + } + +-#define cmp_3way(a, b) ((a) < (b) ? -1 : (a) > (b)) +- + static int cmp_rela(const void *a, const void *b) + { + const Elf_Rela *x = a, *y = b; + int i; + + /* sort by type, symbol index and addend */ +- i = cmp_3way(x->r_info, y->r_info); ++ i = cmp_int(x->r_info, y->r_info); + if (i == 0) +- i = cmp_3way(x->r_addend, y->r_addend); ++ i = cmp_int(x->r_addend, y->r_addend); + return i; + } + +-- +2.53.0 + diff --git a/SPECS/linux/0209-FROMLIST-iommu-riscv-Advertise-Svpbmt-support-to-gen.patch b/SPECS/linux/0209-FROMLIST-iommu-riscv-Advertise-Svpbmt-support-to-gen.patch new file mode 100644 index 0000000000..160b86a4f9 --- /dev/null +++ b/SPECS/linux/0209-FROMLIST-iommu-riscv-Advertise-Svpbmt-support-to-gen.patch @@ -0,0 +1,55 @@ +From 0253b4ea6ea21dadd263134ea8198a6911aabc84 Mon Sep 17 00:00:00 2001 +From: Fangyu Yu +Date: Tue, 12 May 2026 15:41:41 +0800 +Subject: [RUYI PATCH] FROMLIST: iommu/riscv: Advertise Svpbmt support to + generic page table + +The RISC-V IOMMU can optionally support Svpbmt page-based memory types +in its page table format. When present,the generic page table code can +use this capability to encode memory attributes (e.g. MMIO vs normal +memory) in PTEs. + +Reviewed-by: Jason Gunthorpe +Reviewed-by: Anup Patel +Reviewed-by: Guo Ren +Reviewed-by: Nutty Liu +Reviewed-by: Kevin Tian +Signed-off-by: Fangyu Yu +Link: https://lore.kernel.org/r/20260512074142.16356-2-fangyu.yu@linux.alibaba.com +Signed-off-by: Han Gao +--- + drivers/iommu/riscv/iommu.c | 2 ++ + include/linux/generic_pt/common.h | 4 ++++ + 2 files changed, 6 insertions(+) + +diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c +index a31f50bbad35..6c324f9fdc53 100644 +--- a/drivers/iommu/riscv/iommu.c ++++ b/drivers/iommu/riscv/iommu.c +@@ -1268,6 +1268,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev) + cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) | + BIT(PT_FEAT_FLUSH_RANGE) | + BIT(PT_FEAT_RISCV_SVNAPOT_64K); ++ if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT) ++ cfg.common.features |= BIT(PT_FEAT_RISCV_SVPBMT); + domain->riscvpt.iommu.nid = dev_to_node(iommu->dev); + domain->domain.ops = &riscv_iommu_paging_domain_ops; + +diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/common.h +index fc5d0b5edadc..2683e5b38998 100644 +--- a/include/linux/generic_pt/common.h ++++ b/include/linux/generic_pt/common.h +@@ -188,6 +188,10 @@ enum { + * Support the 64k contiguous page size following the Svnapot extension. + */ + PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START, ++ /* ++ * Support Svpbmt extension: encode page-based memory type (PBMT) in PTEs. ++ */ ++ PT_FEAT_RISCV_SVPBMT, + + }; + +-- +2.53.0 + diff --git a/SPECS/linux/0209-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch b/SPECS/linux/0209-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch deleted file mode 100644 index 5c86e309ed..0000000000 --- a/SPECS/linux/0209-FROMLIST-riscv-module-Use-generic-cmp_int-instead-of.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 3b0fcc9dcb7af84ad62bc1f7d7e16769c8389416 Mon Sep 17 00:00:00 2001 -From: Florian Schmaus -Date: Tue, 12 May 2026 08:32:31 +0200 -Subject: [PATCH 209/269] FROMLIST: riscv: module: Use generic cmp_int() - instead of custom cmp_3way() - -The module-sections.c file defines a custom cmp_3way() macro to perform -3-way comparisons during relocation sorting. - -Instead of maintaining our own implementation, use the generic -cmp_int() macro provided by the already included . This -removes redundant code and relies on standard kernel interfaces. - -Signed-off-by: Florian Schmaus -Link: https://lore.kernel.org/r/20260512063231.708256-1-florian.schmaus@codasip.com -Signed-off-by: Han Gao ---- - arch/riscv/kernel/module-sections.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - -diff --git a/arch/riscv/kernel/module-sections.c b/arch/riscv/kernel/module-sections.c -index 1675cbad8619..33750a51f157 100644 ---- a/arch/riscv/kernel/module-sections.c -+++ b/arch/riscv/kernel/module-sections.c -@@ -56,17 +56,15 @@ unsigned long module_emit_plt_entry(struct module *mod, unsigned long val) - return (unsigned long)&plt[i]; - } - --#define cmp_3way(a, b) ((a) < (b) ? -1 : (a) > (b)) -- - static int cmp_rela(const void *a, const void *b) - { - const Elf_Rela *x = a, *y = b; - int i; - - /* sort by type, symbol index and addend */ -- i = cmp_3way(x->r_info, y->r_info); -+ i = cmp_int(x->r_info, y->r_info); - if (i == 0) -- i = cmp_3way(x->r_addend, y->r_addend); -+ i = cmp_int(x->r_addend, y->r_addend); - return i; - } - --- -2.53.0 - diff --git a/SPECS/linux/0210-FROMLIST-iommu-riscv-Advertise-Svpbmt-support-to-gen.patch b/SPECS/linux/0210-FROMLIST-iommu-riscv-Advertise-Svpbmt-support-to-gen.patch deleted file mode 100644 index 1f6d5aab49..0000000000 --- a/SPECS/linux/0210-FROMLIST-iommu-riscv-Advertise-Svpbmt-support-to-gen.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 7d26b62732498fd8de555381d67c2a667be46c22 Mon Sep 17 00:00:00 2001 -From: Fangyu Yu -Date: Tue, 12 May 2026 15:41:41 +0800 -Subject: [PATCH 210/269] FROMLIST: iommu/riscv: Advertise Svpbmt support to - generic page table - -The RISC-V IOMMU can optionally support Svpbmt page-based memory types -in its page table format. When present,the generic page table code can -use this capability to encode memory attributes (e.g. MMIO vs normal -memory) in PTEs. - -Reviewed-by: Jason Gunthorpe -Reviewed-by: Anup Patel -Reviewed-by: Guo Ren -Reviewed-by: Nutty Liu -Reviewed-by: Kevin Tian -Signed-off-by: Fangyu Yu -Link: https://lore.kernel.org/r/20260512074142.16356-2-fangyu.yu@linux.alibaba.com -Signed-off-by: Han Gao ---- - drivers/iommu/riscv/iommu.c | 2 ++ - include/linux/generic_pt/common.h | 4 ++++ - 2 files changed, 6 insertions(+) - -diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c -index a31f50bbad35..6c324f9fdc53 100644 ---- a/drivers/iommu/riscv/iommu.c -+++ b/drivers/iommu/riscv/iommu.c -@@ -1268,6 +1268,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev) - cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) | - BIT(PT_FEAT_FLUSH_RANGE) | - BIT(PT_FEAT_RISCV_SVNAPOT_64K); -+ if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT) -+ cfg.common.features |= BIT(PT_FEAT_RISCV_SVPBMT); - domain->riscvpt.iommu.nid = dev_to_node(iommu->dev); - domain->domain.ops = &riscv_iommu_paging_domain_ops; - -diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/common.h -index fc5d0b5edadc..2683e5b38998 100644 ---- a/include/linux/generic_pt/common.h -+++ b/include/linux/generic_pt/common.h -@@ -188,6 +188,10 @@ enum { - * Support the 64k contiguous page size following the Svnapot extension. - */ - PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START, -+ /* -+ * Support Svpbmt extension: encode page-based memory type (PBMT) in PTEs. -+ */ -+ PT_FEAT_RISCV_SVPBMT, - - }; - --- -2.53.0 - diff --git a/SPECS/linux/0210-FROMLIST-iommupt-Encode-IOMMU_MMIO-IOMMU_CACHE-via-R.patch b/SPECS/linux/0210-FROMLIST-iommupt-Encode-IOMMU_MMIO-IOMMU_CACHE-via-R.patch new file mode 100644 index 0000000000..474c4800d9 --- /dev/null +++ b/SPECS/linux/0210-FROMLIST-iommupt-Encode-IOMMU_MMIO-IOMMU_CACHE-via-R.patch @@ -0,0 +1,67 @@ +From 3f4dc1cff28419797eb12a08c6e0a799ba8b2af7 Mon Sep 17 00:00:00 2001 +From: Fangyu Yu +Date: Tue, 12 May 2026 15:41:42 +0800 +Subject: [RUYI PATCH] FROMLIST: iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via + RISC-V Svpbmt bits + +When the RISC-V IOMMU page table format support Svpbmt, PBMT provides +a way to tag mappings with page-based memory types. Encode memory type +via PBMT in RISC-V IOMMU PTEs: + + - IOMMU_MMIO -> PBMT=IO + - !IOMMU_MMIO && !IOMMU_CACHE -> PBMT=NC + - otherwise -> PBMT=Normal (PBMT=0) + +Only touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised. + +Reviewed-by: Jason Gunthorpe +Reviewed-by: Anup Patel +Reviewed-by: Guo Ren +Reviewed-by: Nutty Liu +Reviewed-by: Kevin Tian +Signed-off-by: Fangyu Yu +Link: https://lore.kernel.org/r/20260512074142.16356-3-fangyu.yu@linux.alibaba.com +Signed-off-by: Han Gao +--- + drivers/iommu/generic_pt/fmt/riscv.h | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h +index a7fef6266a36..ae9a76514416 100644 +--- a/drivers/iommu/generic_pt/fmt/riscv.h ++++ b/drivers/iommu/generic_pt/fmt/riscv.h +@@ -64,6 +64,8 @@ enum { + RISCVPT_PPN64 = GENMASK_ULL(53, 10), + RISCVPT_PPN64_64K = GENMASK_ULL(53, 14), + RISCVPT_PBMT = GENMASK_ULL(62, 61), ++ RISCVPT_NC = BIT_ULL(61), ++ RISCVPT_IO = BIT_ULL(62), + RISCVPT_N = BIT_ULL(63), + + /* Svnapot encodings for ppn[0] */ +@@ -201,7 +203,8 @@ static inline void riscvpt_attr_from_entry(const struct pt_state *pts, + { + attrs->descriptor_bits = + pts->entry & (RISCVPT_R | RISCVPT_W | RISCVPT_X | RISCVPT_U | +- RISCVPT_G | RISCVPT_A | RISCVPT_D); ++ RISCVPT_G | RISCVPT_A | RISCVPT_D | RISCVPT_NC | ++ RISCVPT_IO); + } + #define pt_attr_from_entry riscvpt_attr_from_entry + +@@ -237,6 +240,12 @@ static inline int riscvpt_iommu_set_prot(struct pt_common *common, + pte |= RISCVPT_R; + if (!(iommu_prot & IOMMU_NOEXEC)) + pte |= RISCVPT_X; ++ if (common->features & BIT(PT_FEAT_RISCV_SVPBMT)) { ++ if (iommu_prot & IOMMU_MMIO) ++ pte |= RISCVPT_IO; ++ else if (!(iommu_prot & IOMMU_CACHE)) ++ pte |= RISCVPT_NC; ++ } + + /* Caller must specify a supported combination of flags */ + if (unlikely((pte & (RISCVPT_X | RISCVPT_W | RISCVPT_R)) == 0)) +-- +2.53.0 + diff --git a/SPECS/linux/0211-FROMLIST-iommupt-Encode-IOMMU_MMIO-IOMMU_CACHE-via-R.patch b/SPECS/linux/0211-FROMLIST-iommupt-Encode-IOMMU_MMIO-IOMMU_CACHE-via-R.patch deleted file mode 100644 index 4084697a8e..0000000000 --- a/SPECS/linux/0211-FROMLIST-iommupt-Encode-IOMMU_MMIO-IOMMU_CACHE-via-R.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 18958837a677d934210c25cc58e100d5fe0600ca Mon Sep 17 00:00:00 2001 -From: Fangyu Yu -Date: Tue, 12 May 2026 15:41:42 +0800 -Subject: [PATCH 211/269] FROMLIST: iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via - RISC-V Svpbmt bits - -When the RISC-V IOMMU page table format support Svpbmt, PBMT provides -a way to tag mappings with page-based memory types. Encode memory type -via PBMT in RISC-V IOMMU PTEs: - - - IOMMU_MMIO -> PBMT=IO - - !IOMMU_MMIO && !IOMMU_CACHE -> PBMT=NC - - otherwise -> PBMT=Normal (PBMT=0) - -Only touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised. - -Reviewed-by: Jason Gunthorpe -Reviewed-by: Anup Patel -Reviewed-by: Guo Ren -Reviewed-by: Nutty Liu -Reviewed-by: Kevin Tian -Signed-off-by: Fangyu Yu -Link: https://lore.kernel.org/r/20260512074142.16356-3-fangyu.yu@linux.alibaba.com -Signed-off-by: Han Gao ---- - drivers/iommu/generic_pt/fmt/riscv.h | 11 ++++++++++- - 1 file changed, 10 insertions(+), 1 deletion(-) - -diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h -index a7fef6266a36..ae9a76514416 100644 ---- a/drivers/iommu/generic_pt/fmt/riscv.h -+++ b/drivers/iommu/generic_pt/fmt/riscv.h -@@ -64,6 +64,8 @@ enum { - RISCVPT_PPN64 = GENMASK_ULL(53, 10), - RISCVPT_PPN64_64K = GENMASK_ULL(53, 14), - RISCVPT_PBMT = GENMASK_ULL(62, 61), -+ RISCVPT_NC = BIT_ULL(61), -+ RISCVPT_IO = BIT_ULL(62), - RISCVPT_N = BIT_ULL(63), - - /* Svnapot encodings for ppn[0] */ -@@ -201,7 +203,8 @@ static inline void riscvpt_attr_from_entry(const struct pt_state *pts, - { - attrs->descriptor_bits = - pts->entry & (RISCVPT_R | RISCVPT_W | RISCVPT_X | RISCVPT_U | -- RISCVPT_G | RISCVPT_A | RISCVPT_D); -+ RISCVPT_G | RISCVPT_A | RISCVPT_D | RISCVPT_NC | -+ RISCVPT_IO); - } - #define pt_attr_from_entry riscvpt_attr_from_entry - -@@ -237,6 +240,12 @@ static inline int riscvpt_iommu_set_prot(struct pt_common *common, - pte |= RISCVPT_R; - if (!(iommu_prot & IOMMU_NOEXEC)) - pte |= RISCVPT_X; -+ if (common->features & BIT(PT_FEAT_RISCV_SVPBMT)) { -+ if (iommu_prot & IOMMU_MMIO) -+ pte |= RISCVPT_IO; -+ else if (!(iommu_prot & IOMMU_CACHE)) -+ pte |= RISCVPT_NC; -+ } - - /* Caller must specify a supported combination of flags */ - if (unlikely((pte & (RISCVPT_X | RISCVPT_W | RISCVPT_R)) == 0)) --- -2.53.0 - diff --git a/SPECS/linux/0211-FROMLIST-riscv-propagate-insert_resource-result-from.patch b/SPECS/linux/0211-FROMLIST-riscv-propagate-insert_resource-result-from.patch new file mode 100644 index 0000000000..5737d0c50a --- /dev/null +++ b/SPECS/linux/0211-FROMLIST-riscv-propagate-insert_resource-result-from.patch @@ -0,0 +1,48 @@ +From 21e9bbcaa1df24387f7d8f44bf242d87c457e2c1 Mon Sep 17 00:00:00 2001 +From: Thorsten Blum +Date: Tue, 12 May 2026 19:20:35 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: propagate insert_resource result from + add_resource + +Currently, add_resource() returns 1 on success, even though its callers +only check for negative values. Instead, propagate the insert_resource() +result from add_resource() to align with standard kernel return-value +conventions (0 on success, negative errno on failure). + +Use %pR to print the full resource range while at it. + +Signed-off-by: Thorsten Blum +Link: https://lore.kernel.org/r/20260512172034.328405-4-thorsten.blum@linux.dev +Signed-off-by: Han Gao +--- + arch/riscv/kernel/setup.c | 11 ++++------- + 1 file changed, 4 insertions(+), 7 deletions(-) + +diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c +index b5bc5fc65cea..13b27a078912 100644 +--- a/arch/riscv/kernel/setup.c ++++ b/arch/riscv/kernel/setup.c +@@ -75,16 +75,13 @@ static struct resource *standard_resources; + static int __init add_resource(struct resource *parent, + struct resource *res) + { +- int ret = 0; ++ int ret; + + ret = insert_resource(parent, res); +- if (ret < 0) { +- pr_err("Failed to add a %s resource at %llx\n", +- res->name, (unsigned long long) res->start); +- return ret; +- } ++ if (ret < 0) ++ pr_err("Failed to add resource %s %pR\n", res->name, res); + +- return 1; ++ return ret; + } + + static int __init add_kernel_resources(void) +-- +2.53.0 + diff --git a/SPECS/linux/0212-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch b/SPECS/linux/0212-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch new file mode 100644 index 0000000000..8c7e1177f2 --- /dev/null +++ b/SPECS/linux/0212-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch @@ -0,0 +1,91 @@ +From 74d8d264cef04f124939fdbfab858d192638c9fa Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 17 May 2026 09:48:36 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add device data support + +To reuse the K1 PCIe driver logic for K3 PCIe controller, add device +data to handle the K1 specific logic and make room for the incoming +logic for K3. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260517014841.254085-2-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 25 ++++++++++++++++--- + 1 file changed, 21 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index be20a520255b..1b519d49dcc0 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -57,6 +57,12 @@ struct k1_pcie { + u32 pmu_off; + }; + ++struct k1_pcie_device_data { ++ const struct dw_pcie_host_ops *host_ops; ++ const struct dw_pcie_ops *ops; ++ int (*parse_port)(struct k1_pcie *k1); ++}; ++ + #define to_k1_pcie(dw_pcie) \ + platform_get_drvdata(to_platform_device((dw_pcie)->dev)) + +@@ -278,10 +284,15 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) + + static int k1_pcie_probe(struct platform_device *pdev) + { ++ const struct k1_pcie_device_data *data; + struct device *dev = &pdev->dev; + struct k1_pcie *k1; + int ret; + ++ data = device_get_match_data(dev); ++ if (!data) ++ return -ENODEV; ++ + k1 = devm_kzalloc(dev, sizeof(*k1), GFP_KERNEL); + if (!k1) + return -ENOMEM; +@@ -299,11 +310,11 @@ static int k1_pcie_probe(struct platform_device *pdev) + "failed to map \"link\" registers\n"); + + k1->pci.dev = dev; +- k1->pci.ops = &k1_pcie_ops; ++ k1->pci.ops = data->ops; + k1->pci.pp.num_vectors = MAX_MSI_IRQS; + dw_pcie_cap_set(&k1->pci, REQ_RES); + +- k1->pci.pp.ops = &k1_pcie_host_ops; ++ k1->pci.pp.ops = data->host_ops; + + /* Hold the PHY in reset until we start the link */ + regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, +@@ -320,7 +331,7 @@ static int k1_pcie_probe(struct platform_device *pdev) + + platform_set_drvdata(pdev, k1); + +- ret = k1_pcie_parse_port(k1); ++ ret = data->parse_port(k1); + if (ret) + return dev_err_probe(dev, ret, "failed to parse root port\n"); + +@@ -338,8 +349,14 @@ static void k1_pcie_remove(struct platform_device *pdev) + dw_pcie_host_deinit(&k1->pci.pp); + } + ++static const struct k1_pcie_device_data k1_pcie_device_data = { ++ .host_ops = &k1_pcie_host_ops, ++ .ops = &k1_pcie_ops, ++ .parse_port = k1_pcie_parse_port, ++}; ++ + static const struct of_device_id k1_pcie_of_match_table[] = { +- { .compatible = "spacemit,k1-pcie", }, ++ { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, + { } + }; + +-- +2.53.0 + diff --git a/SPECS/linux/0212-FROMLIST-riscv-propagate-insert_resource-result-from.patch b/SPECS/linux/0212-FROMLIST-riscv-propagate-insert_resource-result-from.patch deleted file mode 100644 index 156e3d4264..0000000000 --- a/SPECS/linux/0212-FROMLIST-riscv-propagate-insert_resource-result-from.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 84223fb743681c104a937d6bc4f7b2c6f4c1eabe Mon Sep 17 00:00:00 2001 -From: Thorsten Blum -Date: Tue, 12 May 2026 19:20:35 +0200 -Subject: [PATCH 212/269] FROMLIST: riscv: propagate insert_resource result - from add_resource - -Currently, add_resource() returns 1 on success, even though its callers -only check for negative values. Instead, propagate the insert_resource() -result from add_resource() to align with standard kernel return-value -conventions (0 on success, negative errno on failure). - -Use %pR to print the full resource range while at it. - -Signed-off-by: Thorsten Blum -Link: https://lore.kernel.org/r/20260512172034.328405-4-thorsten.blum@linux.dev -Signed-off-by: Han Gao ---- - arch/riscv/kernel/setup.c | 11 ++++------- - 1 file changed, 4 insertions(+), 7 deletions(-) - -diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c -index b5bc5fc65cea..13b27a078912 100644 ---- a/arch/riscv/kernel/setup.c -+++ b/arch/riscv/kernel/setup.c -@@ -75,16 +75,13 @@ static struct resource *standard_resources; - static int __init add_resource(struct resource *parent, - struct resource *res) - { -- int ret = 0; -+ int ret; - - ret = insert_resource(parent, res); -- if (ret < 0) { -- pr_err("Failed to add a %s resource at %llx\n", -- res->name, (unsigned long long) res->start); -- return ret; -- } -+ if (ret < 0) -+ pr_err("Failed to add resource %s %pR\n", res->name, res); - -- return 1; -+ return ret; - } - - static int __init add_kernel_resources(void) --- -2.53.0 - diff --git a/SPECS/linux/0213-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch b/SPECS/linux/0213-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch deleted file mode 100644 index e16339c3a5..0000000000 --- a/SPECS/linux/0213-FROMLIST-PCI-spacemit-k1-Add-device-data-support.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 5083a26dd498eb6005324b0c93a37963c86bcb04 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:36 +0800 -Subject: [PATCH 213/269] FROMLIST: PCI: spacemit-k1: Add device data support - -To reuse the K1 PCIe driver logic for K3 PCIe controller, add device -data to handle the K1 specific logic and make room for the incoming -logic for K3. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260517014841.254085-2-inochiama@gmail.com -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/pcie-spacemit-k1.c | 25 ++++++++++++++++--- - 1 file changed, 21 insertions(+), 4 deletions(-) - -diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -index be20a520255b..1b519d49dcc0 100644 ---- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c -+++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -@@ -57,6 +57,12 @@ struct k1_pcie { - u32 pmu_off; - }; - -+struct k1_pcie_device_data { -+ const struct dw_pcie_host_ops *host_ops; -+ const struct dw_pcie_ops *ops; -+ int (*parse_port)(struct k1_pcie *k1); -+}; -+ - #define to_k1_pcie(dw_pcie) \ - platform_get_drvdata(to_platform_device((dw_pcie)->dev)) - -@@ -278,10 +284,15 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) - - static int k1_pcie_probe(struct platform_device *pdev) - { -+ const struct k1_pcie_device_data *data; - struct device *dev = &pdev->dev; - struct k1_pcie *k1; - int ret; - -+ data = device_get_match_data(dev); -+ if (!data) -+ return -ENODEV; -+ - k1 = devm_kzalloc(dev, sizeof(*k1), GFP_KERNEL); - if (!k1) - return -ENOMEM; -@@ -299,11 +310,11 @@ static int k1_pcie_probe(struct platform_device *pdev) - "failed to map \"link\" registers\n"); - - k1->pci.dev = dev; -- k1->pci.ops = &k1_pcie_ops; -+ k1->pci.ops = data->ops; - k1->pci.pp.num_vectors = MAX_MSI_IRQS; - dw_pcie_cap_set(&k1->pci, REQ_RES); - -- k1->pci.pp.ops = &k1_pcie_host_ops; -+ k1->pci.pp.ops = data->host_ops; - - /* Hold the PHY in reset until we start the link */ - regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, -@@ -320,7 +331,7 @@ static int k1_pcie_probe(struct platform_device *pdev) - - platform_set_drvdata(pdev, k1); - -- ret = k1_pcie_parse_port(k1); -+ ret = data->parse_port(k1); - if (ret) - return dev_err_probe(dev, ret, "failed to parse root port\n"); - -@@ -338,8 +349,14 @@ static void k1_pcie_remove(struct platform_device *pdev) - dw_pcie_host_deinit(&k1->pci.pp); - } - -+static const struct k1_pcie_device_data k1_pcie_device_data = { -+ .host_ops = &k1_pcie_host_ops, -+ .ops = &k1_pcie_ops, -+ .parse_port = k1_pcie_parse_port, -+}; -+ - static const struct of_device_id k1_pcie_of_match_table[] = { -- { .compatible = "spacemit,k1-pcie", }, -+ { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, - { } - }; - --- -2.53.0 - diff --git a/SPECS/linux/0213-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch b/SPECS/linux/0213-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch new file mode 100644 index 0000000000..5efb51e682 --- /dev/null +++ b/SPECS/linux/0213-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch @@ -0,0 +1,73 @@ +From 7aa0a33b40a08e38337613071fbad3832acf9c99 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 17 May 2026 09:48:37 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add multiple PHY handles + support + +The PCIe controller on Spacemit K3 may use multiple PHYs at the +same time. The feature is not support by the current driver. +So extend the PHY definition to support multiple PHY handles. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260517014841.254085-3-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 16 ++++++++++++---- + 1 file changed, 12 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index 1b519d49dcc0..7f6f1df31cd8 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -51,7 +51,8 @@ + + struct k1_pcie { + struct dw_pcie pci; +- struct phy *phy; ++ struct phy **phy; ++ int phy_count; + void __iomem *link; + struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ + u32 pmu_off; +@@ -171,7 +172,7 @@ static int k1_pcie_init(struct dw_pcie_rp *pp) + */ + regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET); + +- ret = phy_init(k1->phy); ++ ret = phy_init(k1->phy[0]); + if (ret) { + k1_pcie_disable_resources(k1); + +@@ -191,12 +192,14 @@ static void k1_pcie_deinit(struct dw_pcie_rp *pp) + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct k1_pcie *k1 = to_k1_pcie(pci); ++ int i; + + /* Assert fundamental reset (drive PERST# low) */ + regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, + PCIE_RC_PERST); + +- phy_exit(k1->phy); ++ for (i = 0; i < k1->phy_count; i++) ++ phy_exit(k1->phy[i]); + + k1_pcie_disable_resources(k1); + } +@@ -277,7 +280,12 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) + if (IS_ERR(phy)) + return PTR_ERR(phy); + +- k1->phy = phy; ++ k1->phy = devm_kmalloc_array(dev, 1, sizeof(*k1->phy), GFP_KERNEL); ++ if (!k1->phy) ++ return -ENOMEM; ++ ++ k1->phy[0] = phy; ++ k1->phy_count = 1; + + return 0; + } +-- +2.53.0 + diff --git a/SPECS/linux/0214-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch b/SPECS/linux/0214-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch deleted file mode 100644 index 217f05a09f..0000000000 --- a/SPECS/linux/0214-FROMLIST-PCI-spacemit-k1-Add-multiple-PHY-handles-su.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 272e1fdd4e5a07efc1c210921a7d452990eb7ab5 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:37 +0800 -Subject: [PATCH 214/269] FROMLIST: PCI: spacemit-k1: Add multiple PHY handles - support - -The PCIe controller on Spacemit K3 may use multiple PHYs at the -same time. The feature is not support by the current driver. -So extend the PHY definition to support multiple PHY handles. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260517014841.254085-3-inochiama@gmail.com -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/pcie-spacemit-k1.c | 16 ++++++++++++---- - 1 file changed, 12 insertions(+), 4 deletions(-) - -diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -index 1b519d49dcc0..7f6f1df31cd8 100644 ---- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c -+++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -@@ -51,7 +51,8 @@ - - struct k1_pcie { - struct dw_pcie pci; -- struct phy *phy; -+ struct phy **phy; -+ int phy_count; - void __iomem *link; - struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ - u32 pmu_off; -@@ -171,7 +172,7 @@ static int k1_pcie_init(struct dw_pcie_rp *pp) - */ - regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET); - -- ret = phy_init(k1->phy); -+ ret = phy_init(k1->phy[0]); - if (ret) { - k1_pcie_disable_resources(k1); - -@@ -191,12 +192,14 @@ static void k1_pcie_deinit(struct dw_pcie_rp *pp) - { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct k1_pcie *k1 = to_k1_pcie(pci); -+ int i; - - /* Assert fundamental reset (drive PERST# low) */ - regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, - PCIE_RC_PERST); - -- phy_exit(k1->phy); -+ for (i = 0; i < k1->phy_count; i++) -+ phy_exit(k1->phy[i]); - - k1_pcie_disable_resources(k1); - } -@@ -277,7 +280,12 @@ static int k1_pcie_parse_port(struct k1_pcie *k1) - if (IS_ERR(phy)) - return PTR_ERR(phy); - -- k1->phy = phy; -+ k1->phy = devm_kmalloc_array(dev, 1, sizeof(*k1->phy), GFP_KERNEL); -+ if (!k1->phy) -+ return -ENOMEM; -+ -+ k1->phy[0] = phy; -+ k1->phy_count = 1; - - return 0; - } --- -2.53.0 - diff --git a/SPECS/linux/0214-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch b/SPECS/linux/0214-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch new file mode 100644 index 0000000000..23ac18b95c --- /dev/null +++ b/SPECS/linux/0214-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch @@ -0,0 +1,42 @@ +From 71f1e15e0295ded6f0576bee186b3dcbe7418a4b Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 17 May 2026 09:48:38 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: snps,dw-pcie: Add msi-parent + for MSI handle check + +The IMSIC device on RISC-V based system does not require ID +remapping for MSI. So this device only needs "msi-parent" +property for IMSIC-based SoC, and the "msi-map" is not a +necessary property. + +Add new condition for MSI handling on IMSIC based SoC. + +Signed-off-by: Inochi Amaoto +Acked-by: Rob Herring (Arm) +Link: https://lore.kernel.org/r/20260517014841.254085-4-inochiama@gmail.com +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +index b3216141881c..91bbbc8924f6 100644 +--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml ++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +@@ -27,8 +27,11 @@ allOf: + - $ref: /schemas/pci/snps,dw-pcie-common.yaml# + - if: + not: +- required: +- - msi-map ++ anyOf: ++ - required: ++ - msi-map ++ - required: ++ - msi-parent + then: + properties: + interrupt-names: +-- +2.53.0 + diff --git a/SPECS/linux/0215-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch b/SPECS/linux/0215-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch deleted file mode 100644 index 4d37ece85f..0000000000 --- a/SPECS/linux/0215-FROMLIST-dt-bindings-PCI-snps-dw-pcie-Add-msi-parent.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 8e35eff72e16f5c7c57298b80e892d486d9f73ee Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:38 +0800 -Subject: [PATCH 215/269] FROMLIST: dt-bindings: PCI: snps,dw-pcie: Add - msi-parent for MSI handle check - -The IMSIC device on RISC-V based system does not require ID -remapping for MSI. So this device only needs "msi-parent" -property for IMSIC-based SoC, and the "msi-map" is not a -necessary property. - -Add new condition for MSI handling on IMSIC based SoC. - -Signed-off-by: Inochi Amaoto -Acked-by: Rob Herring (Arm) -Link: https://lore.kernel.org/r/20260517014841.254085-4-inochiama@gmail.com -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -index b3216141881c..91bbbc8924f6 100644 ---- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml -@@ -27,8 +27,11 @@ allOf: - - $ref: /schemas/pci/snps,dw-pcie-common.yaml# - - if: - not: -- required: -- - msi-map -+ anyOf: -+ - required: -+ - msi-map -+ - required: -+ - msi-parent - then: - properties: - interrupt-names: --- -2.53.0 - diff --git a/SPECS/linux/0215-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch b/SPECS/linux/0215-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch new file mode 100644 index 0000000000..c422427553 --- /dev/null +++ b/SPECS/linux/0215-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch @@ -0,0 +1,162 @@ +From dd7888dc0e7e490cb363053a7a3addb9ffa7ca7a Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 17 May 2026 09:48:39 +0800 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: PCI: spacemit: Introduce Spacemit + K3 PCIe host controller + +Add binding support for the PCIe controller on the SpacemiT K3 SoC. +This controller is almost a standard Synopsys DesignWare PCIe IP, +with some extra link and reset state control. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260517014841.254085-5-inochiama@gmail.com +Signed-off-by: Han Gao +--- + .../bindings/pci/spacemit,k3-pcie-host.yaml | 135 ++++++++++++++++++ + 1 file changed, 135 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml + +diff --git a/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml +new file mode 100644 +index 000000000000..46147a37a9ce +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml +@@ -0,0 +1,135 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pci/spacemit,k3-pcie-host.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: SpacemiT K3 PCI Express Host Controller ++ ++maintainers: ++ - Inochi Amaoto ++ ++description: ++ The SpacemiT K3 SoC PCIe host controller is based on the Synopsys ++ DesignWare PCIe IP. The controller uses the external MSI interrupt ++ controller. ++ ++allOf: ++ - $ref: /schemas/pci/pci-host-bridge.yaml# ++ - $ref: /schemas/pci/snps,dw-pcie.yaml# ++ ++properties: ++ compatible: ++ const: spacemit,k3-pcie ++ ++ reg: ++ items: ++ - description: DesignWare PCIe registers ++ - description: Data Bus Interface (DBI) shadow registers ++ - description: ATU address space ++ - description: PCIe configuration space ++ - description: Link control registers ++ ++ reg-names: ++ items: ++ - const: dbi ++ - const: dbi2 ++ - const: atu ++ - const: config ++ - const: link ++ ++ clocks: ++ items: ++ - description: DWC PCIe Data Bus Interface (DBI) clock ++ - description: DWC PCIe application AXI-bus master interface clock ++ - description: DWC PCIe application AXI-bus slave interface clock ++ ++ clock-names: ++ items: ++ - const: dbi ++ - const: mstr ++ - const: slv ++ ++ resets: ++ items: ++ - description: DWC PCIe Data Bus Interface (DBI) reset ++ - description: DWC PCIe application AXI-bus master interface reset ++ - description: DWC PCIe application AXI-bus slave interface reset ++ ++ reset-names: ++ items: ++ - const: dbi ++ - const: mstr ++ - const: slv ++ ++ msi-parent: true ++ ++ phys: ++ description: ++ PHY phandle from the Combo PHY, the lane number does not depends ++ on this, since the number of lanes provided by Combo PHY can be ++ 1 or 2. ++ minItems: 1 ++ maxItems: 6 ++ ++ phy-names: ++ minItems: 1 ++ maxItems: 6 ++ ++ spacemit,apmu: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ description: ++ A phandle that refers to the APMU system controller, whose regmap is ++ used in managing resets and link state, along with and offset of its ++ reset control register. ++ items: ++ - items: ++ - description: phandle to APMU system controller ++ - description: register offset ++ ++required: ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - msi-parent ++ - spacemit,apmu ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ pcie@80000000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80000000 0x0 0x00001000>, ++ <0x0 0x80100000 0x0 0x00001000>, ++ <0x0 0x80300000 0x0 0x00003f20>, ++ <0x11 0x00000000 0x0 0x00010000>, ++ <0x0 0x82900000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu 89>, ++ <&syscon_apmu 56>, ++ <&syscon_apmu 57>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, ++ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu 76>, ++ <&syscon_apmu 78>, ++ <&syscon_apmu 77>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <0>; ++ spacemit,apmu = <&syscon_apmu 0x1f0>; ++ }; ++ }; ++ +-- +2.53.0 + diff --git a/SPECS/linux/0216-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch b/SPECS/linux/0216-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch new file mode 100644 index 0000000000..61b5755897 --- /dev/null +++ b/SPECS/linux/0216-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch @@ -0,0 +1,258 @@ +From febdac3aadf3c9ea634d522fd7fe470452b7cf74 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 17 May 2026 09:48:40 +0800 +Subject: [RUYI PATCH] FROMLIST: PCI: spacemit-k1: Add Spacemit K3 PCIe host + controller support + +The PCIe controller on Spacemit K3 is almost a standard Synopsys +DesignWare PCIe IP with extra link and reset control. Unlike +the PCIe controller on K1, this controller supports external MSI +interrupt controller and can use multiple PHYs at the same time. + +Add driver to support PCIe controller on Spacemit K3 PCIe. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260517014841.254085-6-inochiama@gmail.com +Signed-off-by: Han Gao +--- + drivers/pci/controller/dwc/Kconfig | 4 +- + drivers/pci/controller/dwc/pcie-spacemit-k1.c | 169 ++++++++++++++++++ + 2 files changed, 171 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig +index 06f7d98259cd..a6af31f4eb81 100644 +--- a/drivers/pci/controller/dwc/Kconfig ++++ b/drivers/pci/controller/dwc/Kconfig +@@ -427,7 +427,7 @@ config PCIE_SOPHGO_DW + Sophgo SoCs. + + config PCIE_SPACEMIT_K1 +- tristate "SpacemiT K1 PCIe controller (host mode)" ++ tristate "SpacemiT K1/K3 PCIe controller (host mode)" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on HAS_IOMEM + select PCIE_DW_HOST +@@ -435,7 +435,7 @@ config PCIE_SPACEMIT_K1 + default ARCH_SPACEMIT + help + Enables support for the DesignWare based PCIe controller in +- the SpacemiT K1 SoC operating in host mode. Three controllers ++ the SpacemiT K1/K3 SoC operating in host mode. Three controllers + are available on the K1 SoC; the first of these shares a PHY + with a USB 3.0 host controller (one or the other can be used). + +diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +index 7f6f1df31cd8..7854d26220a9 100644 +--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c ++++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c +@@ -23,6 +23,7 @@ + + #define PCI_VENDOR_ID_SPACEMIT 0x201f + #define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 ++#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 + + /* Offsets and field definitions for link management registers */ + #define K1_PHY_AHB_IRQ_EN 0x0000 +@@ -32,8 +33,20 @@ + #define SMLH_LINK_UP BIT(1) + #define RDLH_LINK_UP BIT(12) + ++#define INTR_STATUS 0x0010 ++ + #define INTR_ENABLE 0x0014 + #define MSI_CTRL_INT BIT(11) ++#define RDLH_LINK_UP_INT BIT(20) ++ ++#define K3_PHY_AHB_IRQSTATUS_INTX 0x0008 ++ ++#define K3_ADDR_INTR_STATUS1 0x0018 ++ ++#define K3_CACHE_MSTR_AWCACHE_MODE GENMASK(14, 11) ++#define K3_CACHE_MSTR_AWCACHE_BEHAVIOR 0xf ++ ++#define K3_MAX_PHY_NUMBER 6 + + /* Some controls require APMU regmap access */ + #define SYSCON_APMU "spacemit,apmu" +@@ -48,6 +61,9 @@ + + #define PCIE_CONTROL_LOGIC 0x0004 + #define PCIE_SOFT_RESET BIT(0) ++#define PCIE_PERSTN_OE BIT(24) ++#define PCIE_PERSTN_OUT BIT(25) ++#define PCIE_IGNORE_PERSTN BIT(31) + + struct k1_pcie { + struct dw_pcie pci; +@@ -262,6 +278,152 @@ static const struct dw_pcie_ops k1_pcie_ops = { + .stop_link = k1_pcie_stop_link, + }; + ++static int k3_pcie_enable_phy(struct k1_pcie *pcie) ++{ ++ int i, ret; ++ ++ for (i = 0; i < pcie->phy_count; i++) { ++ ret = phy_init(pcie->phy[i]); ++ if (ret) ++ goto err_phy; ++ } ++ ++ return 0; ++ ++err_phy: ++ while (--i >= 0) ++ phy_exit(pcie->phy[i]); ++ ++ return ret; ++} ++ ++static int k3_pcie_init(struct dw_pcie_rp *pp) ++{ ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ struct k1_pcie *k1 = to_k1_pcie(pci); ++ u32 reset_ctrl = k1->pmu_off + PCIE_CLK_RESET_CONTROL; ++ u32 val; ++ int ret; ++ ++ regmap_clear_bits(k1->pmu, reset_ctrl, LTSSM_EN); ++ ++ k1_pcie_toggle_soft_reset(k1); ++ ++ ret = k1_pcie_enable_resources(k1); ++ if (ret) ++ return ret; ++ ++ regmap_set_bits(k1->pmu, reset_ctrl, PCIE_AUX_PWR_DET); ++ regmap_clear_bits(k1->pmu, reset_ctrl, APP_HOLD_PHY_RST); ++ ++ ret = k3_pcie_enable_phy(k1); ++ if (ret) { ++ k1_pcie_disable_resources(k1); ++ return ret; ++ } ++ ++ /* K3: Set IGNORE_PERSTN and drive PERSTN_OE high (assert reset) */ ++ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, ++ PCIE_IGNORE_PERSTN | PCIE_PERSTN_OE | PCIE_PERSTN_OUT); ++ usleep_range(1000, 2000); ++ regmap_clear_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, PCIE_PERSTN_OUT); ++ ++ msleep(PCIE_T_PVPERL_MS); ++ ++ /* ++ * Put the controller in root complex mode, and indicate that ++ * Vaux (3.3v) is present. ++ */ ++ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, ++ PCIE_PERSTN_OUT | PCIE_PERSTN_OE); ++ ++ val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); ++ val = u32_replace_bits(val, GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE, ++ GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); ++ dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); ++ ++ dw_pcie_dbi_ro_wr_en(pci); ++ dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT); ++ dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_SPACEMIT_K3); ++ dw_pcie_dbi_ro_wr_dis(pci); ++ ++ /* Finally, as a workaround, disable ASPM L1 */ ++ k1_pcie_disable_aspm_l1(k1); ++ ++ return 0; ++} ++ ++static int k3_pcie_msi_host_init(struct dw_pcie_rp *pp) ++{ ++ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); ++ u32 val; ++ ++ dw_pcie_dbi_ro_wr_en(pci); ++ ++ val = dw_pcie_readl_dbi(pci, COHERENCY_CONTROL_3_OFF); ++ val |= u32_replace_bits(val, K3_CACHE_MSTR_AWCACHE_BEHAVIOR, ++ K3_CACHE_MSTR_AWCACHE_MODE); ++ dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_3_OFF, val); ++ ++ dw_pcie_dbi_ro_wr_dis(pci); ++ ++ return 0; ++} ++ ++static const struct dw_pcie_host_ops k3_pcie_host_ops = { ++ .init = k3_pcie_init, ++ .deinit = k1_pcie_deinit, ++ .msi_init = k3_pcie_msi_host_init, ++}; ++ ++static const struct dw_pcie_ops k3_pcie_ops = { ++ .link_up = k1_pcie_link_up, ++ .start_link = k1_pcie_start_link, ++ .stop_link = k1_pcie_stop_link, ++}; ++ ++static void k3_pcie_clear_irq_status(struct k1_pcie *k1, ++ u32 *status0, u32 *status1, u32 *status2) ++{ ++ *status0 = readl_relaxed(k1->link + K3_PHY_AHB_IRQSTATUS_INTX); ++ *status1 = readl_relaxed(k1->link + INTR_STATUS); ++ *status2 = readl_relaxed(k1->link + K3_ADDR_INTR_STATUS1); ++ ++ writel_relaxed(*status0, k1->link + K3_PHY_AHB_IRQSTATUS_INTX); ++ writel_relaxed(*status1, k1->link + INTR_STATUS); ++ writel_relaxed(*status2, k1->link + K3_ADDR_INTR_STATUS1); ++} ++ ++static int k3_pcie_parse_port(struct k1_pcie *k1) ++{ ++ struct device *dev = k1->pci.dev; ++ u32 status0, status1, status2; ++ int i; ++ ++ k1->phy = devm_kmalloc_array(dev, K3_MAX_PHY_NUMBER, sizeof(*k1->phy), ++ GFP_KERNEL); ++ if (!k1->phy) ++ return -ENOMEM; ++ ++ for (i = 0; i < K3_MAX_PHY_NUMBER; i++) { ++ k1->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i); ++ if (IS_ERR(k1->phy[i])) { ++ if (PTR_ERR(k1->phy[i]) == -ENODEV) ++ break; ++ ++ return PTR_ERR(k1->phy[i]); ++ } ++ } ++ ++ k1->phy_count = i; ++ if (k1->phy_count == 0) ++ return -EINVAL; ++ ++ k3_pcie_clear_irq_status(k1, &status0, &status1, &status2); ++ ++ return 0; ++} ++ + static int k1_pcie_parse_port(struct k1_pcie *k1) + { + struct device *dev = k1->pci.dev; +@@ -363,8 +525,15 @@ static const struct k1_pcie_device_data k1_pcie_device_data = { + .parse_port = k1_pcie_parse_port, + }; + ++static const struct k1_pcie_device_data k3_pcie_device_data = { ++ .host_ops = &k3_pcie_host_ops, ++ .ops = &k3_pcie_ops, ++ .parse_port = k3_pcie_parse_port, ++}; ++ + static const struct of_device_id k1_pcie_of_match_table[] = { + { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, ++ { .compatible = "spacemit,k3-pcie", .data = &k3_pcie_device_data}, + { } + }; + +-- +2.53.0 + diff --git a/SPECS/linux/0216-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch b/SPECS/linux/0216-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch deleted file mode 100644 index 50cd8db1b2..0000000000 --- a/SPECS/linux/0216-FROMLIST-dt-bindings-PCI-spacemit-Introduce-Spacemit.patch +++ /dev/null @@ -1,162 +0,0 @@ -From adf247eee6cdc403295d25b65e1c79c9b21a6400 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:39 +0800 -Subject: [PATCH 216/269] FROMLIST: dt-bindings: PCI: spacemit: Introduce - Spacemit K3 PCIe host controller - -Add binding support for the PCIe controller on the SpacemiT K3 SoC. -This controller is almost a standard Synopsys DesignWare PCIe IP, -with some extra link and reset state control. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260517014841.254085-5-inochiama@gmail.com -Signed-off-by: Han Gao ---- - .../bindings/pci/spacemit,k3-pcie-host.yaml | 135 ++++++++++++++++++ - 1 file changed, 135 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml - -diff --git a/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml -new file mode 100644 -index 000000000000..46147a37a9ce ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml -@@ -0,0 +1,135 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pci/spacemit,k3-pcie-host.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: SpacemiT K3 PCI Express Host Controller -+ -+maintainers: -+ - Inochi Amaoto -+ -+description: -+ The SpacemiT K3 SoC PCIe host controller is based on the Synopsys -+ DesignWare PCIe IP. The controller uses the external MSI interrupt -+ controller. -+ -+allOf: -+ - $ref: /schemas/pci/pci-host-bridge.yaml# -+ - $ref: /schemas/pci/snps,dw-pcie.yaml# -+ -+properties: -+ compatible: -+ const: spacemit,k3-pcie -+ -+ reg: -+ items: -+ - description: DesignWare PCIe registers -+ - description: Data Bus Interface (DBI) shadow registers -+ - description: ATU address space -+ - description: PCIe configuration space -+ - description: Link control registers -+ -+ reg-names: -+ items: -+ - const: dbi -+ - const: dbi2 -+ - const: atu -+ - const: config -+ - const: link -+ -+ clocks: -+ items: -+ - description: DWC PCIe Data Bus Interface (DBI) clock -+ - description: DWC PCIe application AXI-bus master interface clock -+ - description: DWC PCIe application AXI-bus slave interface clock -+ -+ clock-names: -+ items: -+ - const: dbi -+ - const: mstr -+ - const: slv -+ -+ resets: -+ items: -+ - description: DWC PCIe Data Bus Interface (DBI) reset -+ - description: DWC PCIe application AXI-bus master interface reset -+ - description: DWC PCIe application AXI-bus slave interface reset -+ -+ reset-names: -+ items: -+ - const: dbi -+ - const: mstr -+ - const: slv -+ -+ msi-parent: true -+ -+ phys: -+ description: -+ PHY phandle from the Combo PHY, the lane number does not depends -+ on this, since the number of lanes provided by Combo PHY can be -+ 1 or 2. -+ minItems: 1 -+ maxItems: 6 -+ -+ phy-names: -+ minItems: 1 -+ maxItems: 6 -+ -+ spacemit,apmu: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ description: -+ A phandle that refers to the APMU system controller, whose regmap is -+ used in managing resets and link state, along with and offset of its -+ reset control register. -+ items: -+ - items: -+ - description: phandle to APMU system controller -+ - description: register offset -+ -+required: -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ - msi-parent -+ - spacemit,apmu -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ pcie@80000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80000000 0x0 0x00001000>, -+ <0x0 0x80100000 0x0 0x00001000>, -+ <0x0 0x80300000 0x0 0x00003f20>, -+ <0x11 0x00000000 0x0 0x00010000>, -+ <0x0 0x82900000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu 89>, -+ <&syscon_apmu 56>, -+ <&syscon_apmu 57>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu 76>, -+ <&syscon_apmu 78>, -+ <&syscon_apmu 77>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <0>; -+ spacemit,apmu = <&syscon_apmu 0x1f0>; -+ }; -+ }; -+ --- -2.53.0 - diff --git a/SPECS/linux/0217-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch b/SPECS/linux/0217-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch deleted file mode 100644 index 5b2edeaced..0000000000 --- a/SPECS/linux/0217-FROMLIST-PCI-spacemit-k1-Add-Spacemit-K3-PCIe-host-c.patch +++ /dev/null @@ -1,258 +0,0 @@ -From e86cf9b33a5b81087cde57897d41d5cd4d7d1d1b Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 17 May 2026 09:48:40 +0800 -Subject: [PATCH 217/269] FROMLIST: PCI: spacemit-k1: Add Spacemit K3 PCIe host - controller support - -The PCIe controller on Spacemit K3 is almost a standard Synopsys -DesignWare PCIe IP with extra link and reset control. Unlike -the PCIe controller on K1, this controller supports external MSI -interrupt controller and can use multiple PHYs at the same time. - -Add driver to support PCIe controller on Spacemit K3 PCIe. - -Signed-off-by: Inochi Amaoto -Link: https://lore.kernel.org/r/20260517014841.254085-6-inochiama@gmail.com -Signed-off-by: Han Gao ---- - drivers/pci/controller/dwc/Kconfig | 4 +- - drivers/pci/controller/dwc/pcie-spacemit-k1.c | 169 ++++++++++++++++++ - 2 files changed, 171 insertions(+), 2 deletions(-) - -diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig -index 06f7d98259cd..a6af31f4eb81 100644 ---- a/drivers/pci/controller/dwc/Kconfig -+++ b/drivers/pci/controller/dwc/Kconfig -@@ -427,7 +427,7 @@ config PCIE_SOPHGO_DW - Sophgo SoCs. - - config PCIE_SPACEMIT_K1 -- tristate "SpacemiT K1 PCIe controller (host mode)" -+ tristate "SpacemiT K1/K3 PCIe controller (host mode)" - depends on ARCH_SPACEMIT || COMPILE_TEST - depends on HAS_IOMEM - select PCIE_DW_HOST -@@ -435,7 +435,7 @@ config PCIE_SPACEMIT_K1 - default ARCH_SPACEMIT - help - Enables support for the DesignWare based PCIe controller in -- the SpacemiT K1 SoC operating in host mode. Three controllers -+ the SpacemiT K1/K3 SoC operating in host mode. Three controllers - are available on the K1 SoC; the first of these shares a PHY - with a USB 3.0 host controller (one or the other can be used). - -diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -index 7f6f1df31cd8..7854d26220a9 100644 ---- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c -+++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c -@@ -23,6 +23,7 @@ - - #define PCI_VENDOR_ID_SPACEMIT 0x201f - #define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 -+#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 - - /* Offsets and field definitions for link management registers */ - #define K1_PHY_AHB_IRQ_EN 0x0000 -@@ -32,8 +33,20 @@ - #define SMLH_LINK_UP BIT(1) - #define RDLH_LINK_UP BIT(12) - -+#define INTR_STATUS 0x0010 -+ - #define INTR_ENABLE 0x0014 - #define MSI_CTRL_INT BIT(11) -+#define RDLH_LINK_UP_INT BIT(20) -+ -+#define K3_PHY_AHB_IRQSTATUS_INTX 0x0008 -+ -+#define K3_ADDR_INTR_STATUS1 0x0018 -+ -+#define K3_CACHE_MSTR_AWCACHE_MODE GENMASK(14, 11) -+#define K3_CACHE_MSTR_AWCACHE_BEHAVIOR 0xf -+ -+#define K3_MAX_PHY_NUMBER 6 - - /* Some controls require APMU regmap access */ - #define SYSCON_APMU "spacemit,apmu" -@@ -48,6 +61,9 @@ - - #define PCIE_CONTROL_LOGIC 0x0004 - #define PCIE_SOFT_RESET BIT(0) -+#define PCIE_PERSTN_OE BIT(24) -+#define PCIE_PERSTN_OUT BIT(25) -+#define PCIE_IGNORE_PERSTN BIT(31) - - struct k1_pcie { - struct dw_pcie pci; -@@ -262,6 +278,152 @@ static const struct dw_pcie_ops k1_pcie_ops = { - .stop_link = k1_pcie_stop_link, - }; - -+static int k3_pcie_enable_phy(struct k1_pcie *pcie) -+{ -+ int i, ret; -+ -+ for (i = 0; i < pcie->phy_count; i++) { -+ ret = phy_init(pcie->phy[i]); -+ if (ret) -+ goto err_phy; -+ } -+ -+ return 0; -+ -+err_phy: -+ while (--i >= 0) -+ phy_exit(pcie->phy[i]); -+ -+ return ret; -+} -+ -+static int k3_pcie_init(struct dw_pcie_rp *pp) -+{ -+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); -+ struct k1_pcie *k1 = to_k1_pcie(pci); -+ u32 reset_ctrl = k1->pmu_off + PCIE_CLK_RESET_CONTROL; -+ u32 val; -+ int ret; -+ -+ regmap_clear_bits(k1->pmu, reset_ctrl, LTSSM_EN); -+ -+ k1_pcie_toggle_soft_reset(k1); -+ -+ ret = k1_pcie_enable_resources(k1); -+ if (ret) -+ return ret; -+ -+ regmap_set_bits(k1->pmu, reset_ctrl, PCIE_AUX_PWR_DET); -+ regmap_clear_bits(k1->pmu, reset_ctrl, APP_HOLD_PHY_RST); -+ -+ ret = k3_pcie_enable_phy(k1); -+ if (ret) { -+ k1_pcie_disable_resources(k1); -+ return ret; -+ } -+ -+ /* K3: Set IGNORE_PERSTN and drive PERSTN_OE high (assert reset) */ -+ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, -+ PCIE_IGNORE_PERSTN | PCIE_PERSTN_OE | PCIE_PERSTN_OUT); -+ usleep_range(1000, 2000); -+ regmap_clear_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, PCIE_PERSTN_OUT); -+ -+ msleep(PCIE_T_PVPERL_MS); -+ -+ /* -+ * Put the controller in root complex mode, and indicate that -+ * Vaux (3.3v) is present. -+ */ -+ regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, -+ PCIE_PERSTN_OUT | PCIE_PERSTN_OE); -+ -+ val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); -+ val = u32_replace_bits(val, GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE, -+ GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); -+ dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val); -+ -+ dw_pcie_dbi_ro_wr_en(pci); -+ dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT); -+ dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_SPACEMIT_K3); -+ dw_pcie_dbi_ro_wr_dis(pci); -+ -+ /* Finally, as a workaround, disable ASPM L1 */ -+ k1_pcie_disable_aspm_l1(k1); -+ -+ return 0; -+} -+ -+static int k3_pcie_msi_host_init(struct dw_pcie_rp *pp) -+{ -+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp); -+ u32 val; -+ -+ dw_pcie_dbi_ro_wr_en(pci); -+ -+ val = dw_pcie_readl_dbi(pci, COHERENCY_CONTROL_3_OFF); -+ val |= u32_replace_bits(val, K3_CACHE_MSTR_AWCACHE_BEHAVIOR, -+ K3_CACHE_MSTR_AWCACHE_MODE); -+ dw_pcie_writel_dbi(pci, COHERENCY_CONTROL_3_OFF, val); -+ -+ dw_pcie_dbi_ro_wr_dis(pci); -+ -+ return 0; -+} -+ -+static const struct dw_pcie_host_ops k3_pcie_host_ops = { -+ .init = k3_pcie_init, -+ .deinit = k1_pcie_deinit, -+ .msi_init = k3_pcie_msi_host_init, -+}; -+ -+static const struct dw_pcie_ops k3_pcie_ops = { -+ .link_up = k1_pcie_link_up, -+ .start_link = k1_pcie_start_link, -+ .stop_link = k1_pcie_stop_link, -+}; -+ -+static void k3_pcie_clear_irq_status(struct k1_pcie *k1, -+ u32 *status0, u32 *status1, u32 *status2) -+{ -+ *status0 = readl_relaxed(k1->link + K3_PHY_AHB_IRQSTATUS_INTX); -+ *status1 = readl_relaxed(k1->link + INTR_STATUS); -+ *status2 = readl_relaxed(k1->link + K3_ADDR_INTR_STATUS1); -+ -+ writel_relaxed(*status0, k1->link + K3_PHY_AHB_IRQSTATUS_INTX); -+ writel_relaxed(*status1, k1->link + INTR_STATUS); -+ writel_relaxed(*status2, k1->link + K3_ADDR_INTR_STATUS1); -+} -+ -+static int k3_pcie_parse_port(struct k1_pcie *k1) -+{ -+ struct device *dev = k1->pci.dev; -+ u32 status0, status1, status2; -+ int i; -+ -+ k1->phy = devm_kmalloc_array(dev, K3_MAX_PHY_NUMBER, sizeof(*k1->phy), -+ GFP_KERNEL); -+ if (!k1->phy) -+ return -ENOMEM; -+ -+ for (i = 0; i < K3_MAX_PHY_NUMBER; i++) { -+ k1->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i); -+ if (IS_ERR(k1->phy[i])) { -+ if (PTR_ERR(k1->phy[i]) == -ENODEV) -+ break; -+ -+ return PTR_ERR(k1->phy[i]); -+ } -+ } -+ -+ k1->phy_count = i; -+ if (k1->phy_count == 0) -+ return -EINVAL; -+ -+ k3_pcie_clear_irq_status(k1, &status0, &status1, &status2); -+ -+ return 0; -+} -+ - static int k1_pcie_parse_port(struct k1_pcie *k1) - { - struct device *dev = k1->pci.dev; -@@ -363,8 +525,15 @@ static const struct k1_pcie_device_data k1_pcie_device_data = { - .parse_port = k1_pcie_parse_port, - }; - -+static const struct k1_pcie_device_data k3_pcie_device_data = { -+ .host_ops = &k3_pcie_host_ops, -+ .ops = &k3_pcie_ops, -+ .parse_port = k3_pcie_parse_port, -+}; -+ - static const struct of_device_id k1_pcie_of_match_table[] = { - { .compatible = "spacemit,k1-pcie", .data = &k1_pcie_device_data}, -+ { .compatible = "spacemit,k3-pcie", .data = &k3_pcie_device_data}, - { } - }; - --- -2.53.0 - diff --git a/SPECS/linux/0217-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch b/SPECS/linux/0217-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch new file mode 100644 index 0000000000..98dcb8492e --- /dev/null +++ b/SPECS/linux/0217-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch @@ -0,0 +1,76 @@ +From 61340a2a8ae64c8740ab040576fb1d9bea07fc58 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Sat, 16 May 2026 16:00:30 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable QSPI for OrangePi + RV2 + +Enable the QSPI controller and the XM25QU128C SPI NOR flash on the +OrangePi RV2 board. Add a flash partition layout from vendor UBoot. + +Signed-off-by: Chukun Pan +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260516080030.1736836-1-amadeus@jmu.edu.cn +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 45 +++++++++++++++++++ + 1 file changed, 45 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index bd40bc9011e2..0b4d4d1418e2 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -290,6 +290,51 @@ &pcie2 { + status = "okay"; + }; + ++&qspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi_cfg>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <26500000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; ++ vcc-supply = <&buck3_1v8>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bootinfo@0 { ++ reg = <0x00000 0x010000>; ++ }; ++ ++ private@10000 { ++ reg = <0x10000 0x010000>; ++ }; ++ ++ fsbl@20000 { ++ reg = <0x20000 0x040000>; ++ }; ++ ++ env@60000 { ++ reg = <0x60000 0x010000>; ++ }; ++ ++ opensbi@70000 { ++ reg = <0x70000 0x030000>; ++ }; ++ ++ uboot@a00000 { ++ reg = <0xa0000 0x760000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux/0218-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch b/SPECS/linux/0218-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch new file mode 100644 index 0000000000..5d3268855e --- /dev/null +++ b/SPECS/linux/0218-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch @@ -0,0 +1,37 @@ +From 8e4787ffe8325bb4111e9e44d0a4886930c0e5a4 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 18 May 2026 02:58:36 +0000 +Subject: [RUYI PATCH] FROMLIST: clk: spacemit: k3: fix USB2 bus clock + +According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus +clock enable bit was wrongly swapped, the correct one should be: + +Register : APMU_USB_CLK_RES_CTRL +bit[1] : usb2_port_bus_clk_en +bit[0] : usb2_port_ahb_rstn + +Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") +Reported-by: Junzhong Pan +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-1-14fc235e692b@kernel.org +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index cb0c4277f72a..03de04144963 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -777,7 +777,7 @@ static const struct clk_parent_data sdh2_parents[] = { + CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, + BIT(11), 5, 3, BIT(4), 0); + +-CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(0), 0); ++CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(1), 0); + CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(4), 0); + CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); + CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(12), 0); +-- +2.53.0 + diff --git a/SPECS/linux/0218-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch b/SPECS/linux/0218-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch deleted file mode 100644 index f4956d8bc5..0000000000 --- a/SPECS/linux/0218-FROMLIST-riscv-dts-spacemit-enable-QSPI-for-OrangePi.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 35088f1c6265377974a29e7aa290aa73eac02a9a Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Sat, 16 May 2026 16:00:30 +0800 -Subject: [PATCH 218/269] FROMLIST: riscv: dts: spacemit: enable QSPI for - OrangePi RV2 - -Enable the QSPI controller and the XM25QU128C SPI NOR flash on the -OrangePi RV2 board. Add a flash partition layout from vendor UBoot. - -Signed-off-by: Chukun Pan -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260516080030.1736836-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-rv2.dts | 45 +++++++++++++++++++ - 1 file changed, 45 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index bd40bc9011e2..0b4d4d1418e2 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -290,6 +290,51 @@ &pcie2 { - status = "okay"; - }; - -+&qspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qspi_cfg>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <26500000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ vcc-supply = <&buck3_1v8>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ bootinfo@0 { -+ reg = <0x00000 0x010000>; -+ }; -+ -+ private@10000 { -+ reg = <0x10000 0x010000>; -+ }; -+ -+ fsbl@20000 { -+ reg = <0x20000 0x040000>; -+ }; -+ -+ env@60000 { -+ reg = <0x60000 0x010000>; -+ }; -+ -+ opensbi@70000 { -+ reg = <0x70000 0x030000>; -+ }; -+ -+ uboot@a00000 { -+ reg = <0xa0000 0x760000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux/0219-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch b/SPECS/linux/0219-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch deleted file mode 100644 index f0f8dd457a..0000000000 --- a/SPECS/linux/0219-FROMLIST-clk-spacemit-k3-fix-USB2-bus-clock.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 08190175da636a932c84b39350e5345ee141177a Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 18 May 2026 02:58:36 +0000 -Subject: [PATCH 219/269] FROMLIST: clk: spacemit: k3: fix USB2 bus clock - -According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus -clock enable bit was wrongly swapped, the correct one should be: - -Register : APMU_USB_CLK_RES_CTRL -bit[1] : usb2_port_bus_clk_en -bit[0] : usb2_port_ahb_rstn - -Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree") -Reported-by: Junzhong Pan -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-1-14fc235e692b@kernel.org -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index cb0c4277f72a..03de04144963 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -777,7 +777,7 @@ static const struct clk_parent_data sdh2_parents[] = { - CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, - BIT(11), 5, 3, BIT(4), 0); - --CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(0), 0); -+CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(1), 0); - CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(4), 0); - CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); - CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(12), 0); --- -2.53.0 - diff --git a/SPECS/linux/0219-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch b/SPECS/linux/0219-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch new file mode 100644 index 0000000000..34d5815700 --- /dev/null +++ b/SPECS/linux/0219-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch @@ -0,0 +1,37 @@ +From 2c8a1059a57e140eb7f436c07c1e0e83a92b875c Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 18 May 2026 02:58:37 +0000 +Subject: [RUYI PATCH] FROMLIST: reset: spacemit: k3: fix USB2 ahb reset + +According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus +clock enable bit was wrongly swapped, the correct one should be: + +Register : APMU_USB_CLK_RES_CTRL +bit[1] : usb2_port_bus_clk_en +bit[0] : usb2_port_ahb_rstn + +Fixes: a0e0c2f8c5f3 ("reset: spacemit: k3: Decouple composite reset lines") +Reported-by: Junzhong Pan +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-2-14fc235e692b@kernel.org +Signed-off-by: Han Gao +--- + drivers/reset/spacemit/reset-spacemit-k3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c +index 9841f5e057b2..2e87f320cf11 100644 +--- a/drivers/reset/spacemit/reset-spacemit-k3.c ++++ b/drivers/reset/spacemit/reset-spacemit-k3.c +@@ -112,7 +112,7 @@ static const struct ccu_reset_data k3_apmu_resets[] = { + [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), +- [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)), ++ [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), + [RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)), + [RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)), + [RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)), +-- +2.53.0 + diff --git a/SPECS/linux/0220-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch b/SPECS/linux/0220-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch new file mode 100644 index 0000000000..5846641bcf --- /dev/null +++ b/SPECS/linux/0220-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch @@ -0,0 +1,37 @@ +From 82547ce6fda10b18258c6ef6f9a0fee803d962f3 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Mon, 18 May 2026 20:58:16 +0000 +Subject: [RUYI PATCH] FROMLIST: dts: riscv: spacemit: k3: Fix I/O power + settings + +SpacemiT K3 SoC support dual-voltage I/O power domain, while initially +configure to 3.3v, and need to access register from APBC space to switch +to 1.8v domain. + +Fix the GMAC0's I/O pins 1.8v switch failure that will result a broken +ethernet driver. + +Fixes: d8944577496b ("riscv: dts: spacemit: k3: add pinctrl support") +Reported-by: Han Gao +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260518-07-dts-pinctrl-io-power-v1-1-abe19c14a726@kernel.org +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index a336de5f3d94..809067d6383c 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -1035,6 +1035,7 @@ pinctrl: pinctrl@d401e000 { + clocks = <&syscon_apbc CLK_APBC_AIB>, + <&syscon_apbc CLK_APBC_AIB_BUS>; + clock-names = "func", "bus"; ++ spacemit,apbc = <&syscon_apbc>; + }; + + uart10: serial@d401f000 { +-- +2.53.0 + diff --git a/SPECS/linux/0220-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch b/SPECS/linux/0220-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch deleted file mode 100644 index 54d56f708f..0000000000 --- a/SPECS/linux/0220-FROMLIST-reset-spacemit-k3-fix-USB2-ahb-reset.patch +++ /dev/null @@ -1,37 +0,0 @@ -From f2d5da0de66720fbd8559833fec9c741b14561aa Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 18 May 2026 02:58:37 +0000 -Subject: [PATCH 220/269] FROMLIST: reset: spacemit: k3: fix USB2 ahb reset - -According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus -clock enable bit was wrongly swapped, the correct one should be: - -Register : APMU_USB_CLK_RES_CTRL -bit[1] : usb2_port_bus_clk_en -bit[0] : usb2_port_ahb_rstn - -Fixes: a0e0c2f8c5f3 ("reset: spacemit: k3: Decouple composite reset lines") -Reported-by: Junzhong Pan -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-2-14fc235e692b@kernel.org -Signed-off-by: Han Gao ---- - drivers/reset/spacemit/reset-spacemit-k3.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/reset/spacemit/reset-spacemit-k3.c b/drivers/reset/spacemit/reset-spacemit-k3.c -index 9841f5e057b2..2e87f320cf11 100644 ---- a/drivers/reset/spacemit/reset-spacemit-k3.c -+++ b/drivers/reset/spacemit/reset-spacemit-k3.c -@@ -112,7 +112,7 @@ static const struct ccu_reset_data k3_apmu_resets[] = { - [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), - [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), -- [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)), -+ [RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), - [RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)), - [RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)), - [RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)), --- -2.53.0 - diff --git a/SPECS/linux/0221-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch b/SPECS/linux/0221-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch deleted file mode 100644 index 3d533964b5..0000000000 --- a/SPECS/linux/0221-FROMLIST-dts-riscv-spacemit-k3-Fix-I-O-power-setting.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 4e41ddc8ca87d9f8af5fc6a06cf8f0ec3d2427b5 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Mon, 18 May 2026 20:58:16 +0000 -Subject: [PATCH 221/269] FROMLIST: dts: riscv: spacemit: k3: Fix I/O power - settings - -SpacemiT K3 SoC support dual-voltage I/O power domain, while initially -configure to 3.3v, and need to access register from APBC space to switch -to 1.8v domain. - -Fix the GMAC0's I/O pins 1.8v switch failure that will result a broken -ethernet driver. - -Fixes: d8944577496b ("riscv: dts: spacemit: k3: add pinctrl support") -Reported-by: Han Gao -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260518-07-dts-pinctrl-io-power-v1-1-abe19c14a726@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index a336de5f3d94..809067d6383c 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -1035,6 +1035,7 @@ pinctrl: pinctrl@d401e000 { - clocks = <&syscon_apbc CLK_APBC_AIB>, - <&syscon_apbc CLK_APBC_AIB_BUS>; - clock-names = "func", "bus"; -+ spacemit,apbc = <&syscon_apbc>; - }; - - uart10: serial@d401f000 { --- -2.53.0 - diff --git a/SPECS/linux/0221-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux/0221-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch new file mode 100644 index 0000000000..67feb59219 --- /dev/null +++ b/SPECS/linux/0221-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch @@ -0,0 +1,35 @@ +From 32d50ad9cd58eb6c4efdd9ae3ac8ebb32a4811d9 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:35 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on + Milk-V Jupiter + +Because the default console's baud rate is not set, defconfig kernels do +not have any serial output on this platform. Set the baud rate to +115200, matching what is used by U-Boot etc on this platform. + +See-also: 24c12ca43b12c ("dts: spacemit: set console baud rate on bpif3") +Fixes: 5b90a3d6092d9 ("riscv: dts: spacemit: Add Milk-V Jupiter board device tree") +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260519041458.3287843-2-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index afaad59e6bce..db98dbfadf00 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -20,7 +20,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + leds { +-- +2.53.0 + diff --git a/SPECS/linux/0222-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux/0222-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch deleted file mode 100644 index 688004b815..0000000000 --- a/SPECS/linux/0222-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch +++ /dev/null @@ -1,35 +0,0 @@ -From f766775d018c48f5d30f3624f61b4f877339fb90 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:35 +0200 -Subject: [PATCH 222/269] FROMLIST: riscv: dts: spacemit: set console baud rate - on Milk-V Jupiter - -Because the default console's baud rate is not set, defconfig kernels do -not have any serial output on this platform. Set the baud rate to -115200, matching what is used by U-Boot etc on this platform. - -See-also: 24c12ca43b12c ("dts: spacemit: set console baud rate on bpif3") -Fixes: 5b90a3d6092d9 ("riscv: dts: spacemit: Add Milk-V Jupiter board device tree") -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-2-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index afaad59e6bce..db98dbfadf00 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -20,7 +20,7 @@ aliases { - }; - - chosen { -- stdout-path = "serial0"; -+ stdout-path = "serial0:115200n8"; - }; - - leds { --- -2.53.0 - diff --git a/SPECS/linux/0222-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch b/SPECS/linux/0222-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch new file mode 100644 index 0000000000..53621ccfff --- /dev/null +++ b/SPECS/linux/0222-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch @@ -0,0 +1,33 @@ +From 8fdf182774d531383f86706f101b38b408aeec32 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:36 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: sort aliases on Milk-V + Jupiter + +Before adding more aliases, just sort them. + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260519041458.3287843-3-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index db98dbfadf00..fbba33992347 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -14,9 +14,9 @@ / { + aliases { + ethernet0 = ð0; + ethernet1 = ð1; +- serial0 = &uart0; + i2c2 = &i2c2; + i2c8 = &i2c8; ++ serial0 = &uart0; + }; + + chosen { +-- +2.53.0 + diff --git a/SPECS/linux/0223-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch b/SPECS/linux/0223-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch new file mode 100644 index 0000000000..f81025f5b1 --- /dev/null +++ b/SPECS/linux/0223-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch @@ -0,0 +1,56 @@ +From 2f5d64a37f4d7c48f2862000bb8c5b565b635cbe Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:37 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable eMMC on Milk-V + Jupiter + +The Milk-V Jupiter board has a connector for an eMMC module. Add an +entry for it in the device tree and alias it mmc0. + +Mark the device as non-removable as eMMC modules have no CD pin and are +not supposed to be inserted or removed while the system is running. On +systems without an eMMC module installed, the kernel emits the following +informational message during boot: + +mmc0: SDHCI controller on d4281000.mmc [d4281000.mmc] using ADMA +mmc0: Failed to initialize a non-removable card + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260519041458.3287843-4-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index fbba33992347..1a833e716cb6 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -16,6 +16,7 @@ aliases { + ethernet1 = ð1; + i2c2 = &i2c2; + i2c8 = &i2c8; ++ mmc0 = &emmc; + serial0 = &uart0; + }; + +@@ -105,6 +106,16 @@ &combo_phy { + status = "okay"; + }; + ++&emmc { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ non-removable; ++ no-sd; ++ no-sdio; ++ status = "okay"; ++}; ++ + ð0 { + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; +-- +2.53.0 + diff --git a/SPECS/linux/0223-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch b/SPECS/linux/0223-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch deleted file mode 100644 index 7327e80ee4..0000000000 --- a/SPECS/linux/0223-FROMLIST-riscv-dts-spacemit-sort-aliases-on-Milk-V-J.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 6128e54f91614fb865cc2a199ad8a0863bda4c0b Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:36 +0200 -Subject: [PATCH 223/269] FROMLIST: riscv: dts: spacemit: sort aliases on - Milk-V Jupiter - -Before adding more aliases, just sort them. - -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-3-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index db98dbfadf00..fbba33992347 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -14,9 +14,9 @@ / { - aliases { - ethernet0 = ð0; - ethernet1 = ð1; -- serial0 = &uart0; - i2c2 = &i2c2; - i2c8 = &i2c8; -+ serial0 = &uart0; - }; - - chosen { --- -2.53.0 - diff --git a/SPECS/linux/0224-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch b/SPECS/linux/0224-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch new file mode 100644 index 0000000000..0167e51037 --- /dev/null +++ b/SPECS/linux/0224-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch @@ -0,0 +1,72 @@ +From 9307972d78fcb63ca4a6ab2649ecc9ea02b3a81d Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:38 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable SD card support + on Milk-V Jupiter + +Add complete SD card controller support with UHS high-speed modes. + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with pull-up +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Alias it as mmc1 + +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260519041458.3287843-5-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-milkv-jupiter.dts | 21 ++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index 1a833e716cb6..beebf804197e 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -17,6 +17,7 @@ aliases { + i2c2 = &i2c2; + i2c8 = &i2c8; + mmc0 = &emmc; ++ mmc1 = &sdhci0; + serial0 = &uart0; + }; + +@@ -250,7 +251,7 @@ buck6 { + regulator-always-on; + }; + +- aldo1 { ++ aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; +@@ -385,6 +386,24 @@ uboot@a00000 { + }; + }; + ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4_3v3>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +-- +2.53.0 + diff --git a/SPECS/linux/0224-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch b/SPECS/linux/0224-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch deleted file mode 100644 index f03bb6861c..0000000000 --- a/SPECS/linux/0224-FROMLIST-riscv-dts-spacemit-enable-eMMC-on-Milk-V-Ju.patch +++ /dev/null @@ -1,56 +0,0 @@ -From dc50a13ede34e19d736820e60bd21c2d91b699f7 Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:37 +0200 -Subject: [PATCH 224/269] FROMLIST: riscv: dts: spacemit: enable eMMC on Milk-V - Jupiter - -The Milk-V Jupiter board has a connector for an eMMC module. Add an -entry for it in the device tree and alias it mmc0. - -Mark the device as non-removable as eMMC modules have no CD pin and are -not supposed to be inserted or removed while the system is running. On -systems without an eMMC module installed, the kernel emits the following -informational message during boot: - -mmc0: SDHCI controller on d4281000.mmc [d4281000.mmc] using ADMA -mmc0: Failed to initialize a non-removable card - -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-4-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index fbba33992347..1a833e716cb6 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -16,6 +16,7 @@ aliases { - ethernet1 = ð1; - i2c2 = &i2c2; - i2c8 = &i2c8; -+ mmc0 = &emmc; - serial0 = &uart0; - }; - -@@ -105,6 +106,16 @@ &combo_phy { - status = "okay"; - }; - -+&emmc { -+ bus-width = <8>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+}; -+ - ð0 { - phy-handle = <&rgmii0>; - phy-mode = "rgmii-id"; --- -2.53.0 - diff --git a/SPECS/linux/0225-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch b/SPECS/linux/0225-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch deleted file mode 100644 index 788954b8e5..0000000000 --- a/SPECS/linux/0225-FROMLIST-riscv-dts-spacemit-enable-SD-card-support-o.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 68410f0eb5da8629511f67c27d0c22ddc6e3620d Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:38 +0200 -Subject: [PATCH 225/269] FROMLIST: riscv: dts: spacemit: enable SD card - support on Milk-V Jupiter - -Add complete SD card controller support with UHS high-speed modes. - -- Enable sdhci0 controller with 4-bit bus width -- Configure card detect GPIO with pull-up -- Connect vmmc-supply to buck4 for 3.3V card power -- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching -- Add dual pinctrl states for voltage-dependent pin configuration -- Support UHS-I SDR25, SDR50, and SDR104 modes -- Alias it as mmc1 - -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-5-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-milkv-jupiter.dts | 21 ++++++++++++++++++- - 1 file changed, 20 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index 1a833e716cb6..beebf804197e 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -17,6 +17,7 @@ aliases { - i2c2 = &i2c2; - i2c8 = &i2c8; - mmc0 = &emmc; -+ mmc1 = &sdhci0; - serial0 = &uart0; - }; - -@@ -250,7 +251,7 @@ buck6 { - regulator-always-on; - }; - -- aldo1 { -+ aldo1: aldo1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; -@@ -385,6 +386,24 @@ uboot@a00000 { - }; - }; - -+&sdhci0 { -+ pinctrl-names = "default", "uhs"; -+ pinctrl-0 = <&mmc1_cfg>; -+ pinctrl-1 = <&mmc1_uhs_cfg>; -+ bus-width = <4>; -+ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; -+ no-mmc; -+ no-sdio; -+ disable-wp; -+ cap-sd-highspeed; -+ vmmc-supply = <&buck4_3v3>; -+ vqmmc-supply = <&aldo1>; -+ sd-uhs-sdr25; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; --- -2.53.0 - diff --git a/SPECS/linux/0225-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch b/SPECS/linux/0225-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch new file mode 100644 index 0000000000..c23d55b77d --- /dev/null +++ b/SPECS/linux/0225-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch @@ -0,0 +1,32 @@ +From 627095821b3f2df8c21de5a90f4a079221c28700 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Tue, 19 May 2026 06:12:39 +0200 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: fix uboot partition + offset on Milk-V Jupiter + +Correct the uboot partition node name to match its actual offset. + +Fixes: 2829823956f0 ("riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter") +Signed-off-by: Aurelien Jarno +Link: https://lore.kernel.org/r/20260519041458.3287843-6-aurelien@aurel32.net +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +index beebf804197e..2fc8d6533786 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +@@ -379,7 +379,7 @@ env@60000 { + opensbi@70000 { + reg = <0x70000 0x30000>; + }; +- uboot@a00000 { ++ uboot@a0000 { + reg = <0xa0000 0x760000>; + }; + }; +-- +2.53.0 + diff --git a/SPECS/linux/0226-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch b/SPECS/linux/0226-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch new file mode 100644 index 0000000000..10790b084f --- /dev/null +++ b/SPECS/linux/0226-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch @@ -0,0 +1,154 @@ +From a9a19c8a5026751d6ef99c2bae387e79f7ba093f Mon Sep 17 00:00:00 2001 +From: Zhengyu He +Date: Thu, 21 May 2026 22:44:46 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: add QSPI support for K3 + Pico-ITX + +Add K3 QSPI controller node into k3.dtsi, and add related pinmux +configuration. + +Enable QSPI on Pico-ITX board, and describe the NOR flash which wires +to it. + +Signed-off-by: Cody Kang +Signed-off-by: Zhengyu He +Link: https://lore.kernel.org/r/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-2-52bce26e5fd8@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 58 ++++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 21 +++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 17 ++++++ + 3 files changed, 96 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 4486dc1fe114..61cbf924830b 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -192,6 +192,64 @@ phy0: phy@1 { + }; + }; + ++&pinctrl { ++ qspi-cfg { ++ qspi-pins { ++ power-source = <1800>; ++ }; ++ ++ qspi-cs0-pins { ++ power-source = <1800>; ++ }; ++ }; ++}; ++ ++&qspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&qspi_cfg>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <26500000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; ++ vcc-supply = <&aldo2>; /* PMIC_VCC1V8_QSPI */ ++ m25p,fast-read; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bootinfo@0 { ++ reg = <0x0 0x20000>; ++ }; ++ ++ fsbl@20000 { ++ reg = <0x20000 0x80000>; ++ }; ++ ++ env@a0000 { ++ reg = <0xa0000 0x10000>; ++ }; ++ ++ esos@b0000 { ++ reg = <0xb0000 0x100000>; ++ }; ++ ++ opensbi@1b0000 { ++ reg = <0x1b0000 0x60000>; ++ }; ++ ++ uboot@210000 { ++ reg = <0x210000 0x5f0000>; ++ }; ++ }; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 252c64af76fe..dffa4d583bb2 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -646,6 +646,27 @@ pwm19-2-pins { + }; + }; + ++ /omit-if-no-ref/ ++ qspi_cfg: qspi-cfg { ++ qspi-pins { ++ pinmux = , /* qspi dat0 */ ++ , /* qspi dat1 */ ++ , /* qspi dat2 */ ++ , /* qspi dat3 */ ++ ; /* qspi clk */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ }; ++ ++ qspi-cs0-pins { ++ pinmux = ; /* qspi cs0 */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ }; ++ }; ++ + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 809067d6383c..5b17612fe58e 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -1069,6 +1069,23 @@ pll: clock-controller@d4090000 { + #clock-cells = <1>; + }; + ++ qspi: spi@d420c000 { ++ compatible = "spacemit,k3-qspi", ++ "spacemit,k1-qspi"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0xd420c000 0x0 0x1000>, ++ <0x0 0xb8000000 0x0 0xc00000>; ++ reg-names = "QuadSPI", "QuadSPI-memory"; ++ clocks = <&syscon_apmu CLK_APMU_QSPI_BUS>, ++ <&syscon_apmu CLK_APMU_QSPI>; ++ clock-names = "qspi_en", "qspi"; ++ resets = <&syscon_apmu RESET_APMU_QSPI>, ++ <&syscon_apmu RESET_APMU_QSPI_BUS>; ++ interrupts = <117 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ }; ++ + syscon_apmu: system-controller@d4282800 { + compatible = "spacemit,k3-syscon-apmu"; + reg = <0x0 0xd4282800 0x0 0x400>; +-- +2.53.0 + diff --git a/SPECS/linux/0226-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch b/SPECS/linux/0226-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch deleted file mode 100644 index 9acec9e924..0000000000 --- a/SPECS/linux/0226-FROMLIST-riscv-dts-spacemit-fix-uboot-partition-offs.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 209e289be72e52635b68fe9aef7e3a9d827a3caa Mon Sep 17 00:00:00 2001 -From: Aurelien Jarno -Date: Tue, 19 May 2026 06:12:39 +0200 -Subject: [PATCH 226/269] FROMLIST: riscv: dts: spacemit: fix uboot partition - offset on Milk-V Jupiter - -Correct the uboot partition node name to match its actual offset. - -Fixes: 2829823956f0 ("riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter") -Signed-off-by: Aurelien Jarno -Link: https://lore.kernel.org/r/20260519041458.3287843-6-aurelien@aurel32.net -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -index beebf804197e..2fc8d6533786 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts -@@ -379,7 +379,7 @@ env@60000 { - opensbi@70000 { - reg = <0x70000 0x30000>; - }; -- uboot@a00000 { -+ uboot@a0000 { - reg = <0xa0000 0x760000>; - }; - }; --- -2.53.0 - diff --git a/SPECS/linux/0227-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch b/SPECS/linux/0227-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch new file mode 100644 index 0000000000..19fd9159dc --- /dev/null +++ b/SPECS/linux/0227-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch @@ -0,0 +1,49 @@ +From 018b260159b4f2877431463dff0b5ad5384a40a0 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 20 May 2026 00:40:07 +0800 +Subject: [RUYI PATCH] FROMLIST: pinctrl: spacemit: fix NULL check in + spacemit_pin_set_config + +spacemit_pin_set_config() looks up the per-pin descriptor with +spacemit_get_pin() then checks the wrong variable for failure: + + const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); + ... + if (!pin) + return -EINVAL; + + reg = spacemit_pin_to_reg(pctrl, spin->pin); + +pin is an unsigned int pin id, where 0 (GPIO_0 / gmac0_rxdv on K3) is a +valid pin, so rejecting it here drops the PAD config write for the first +pin of every group. On K3 Pico-ITX the GMAC RGMII group lists pin 0 as +its first entry, so its drive-strength / bias configuration was silently +ignored. + +The intended guard is against spacemit_get_pin() returning NULL when the +pin id isn't in the SoC's pin table. Check spin instead, which both +restores PAD setup for pin 0 and prevents a NULL deref on spin->pin. + +Fixes: a83c29e1d145 ("pinctrl: spacemit: add support for SpacemiT K1 SoC") +Link: https://lore.kernel.org/r/20260519164007.122574-1-gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + drivers/pinctrl/spacemit/pinctrl-k1.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c +index b0be62b1c816..95024e2bb5a5 100644 +--- a/drivers/pinctrl/spacemit/pinctrl-k1.c ++++ b/drivers/pinctrl/spacemit/pinctrl-k1.c +@@ -795,7 +795,7 @@ static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl, + void __iomem *reg; + unsigned int mux; + +- if (!pin) ++ if (!spin) + return -EINVAL; + + reg = spacemit_pin_to_reg(pctrl, spin->pin); +-- +2.53.0 + diff --git a/SPECS/linux/0227-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch b/SPECS/linux/0227-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch deleted file mode 100644 index 812d5b9c0d..0000000000 --- a/SPECS/linux/0227-FROMLIST-riscv-dts-spacemit-add-QSPI-support-for-K3-.patch +++ /dev/null @@ -1,154 +0,0 @@ -From 00c51e0e7b6a409822a4324c95371a736ce8d836 Mon Sep 17 00:00:00 2001 -From: Zhengyu He -Date: Thu, 21 May 2026 22:44:46 +0800 -Subject: [PATCH 227/269] FROMLIST: riscv: dts: spacemit: add QSPI support for - K3 Pico-ITX - -Add K3 QSPI controller node into k3.dtsi, and add related pinmux -configuration. - -Enable QSPI on Pico-ITX board, and describe the NOR flash which wires -to it. - -Signed-off-by: Cody Kang -Signed-off-by: Zhengyu He -Link: https://lore.kernel.org/r/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-2-52bce26e5fd8@gmail.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 58 ++++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 21 +++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 17 ++++++ - 3 files changed, 96 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index 4486dc1fe114..61cbf924830b 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -192,6 +192,64 @@ phy0: phy@1 { - }; - }; - -+&pinctrl { -+ qspi-cfg { -+ qspi-pins { -+ power-source = <1800>; -+ }; -+ -+ qspi-cs0-pins { -+ power-source = <1800>; -+ }; -+ }; -+}; -+ -+&qspi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qspi_cfg>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <26500000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <4>; -+ vcc-supply = <&aldo2>; /* PMIC_VCC1V8_QSPI */ -+ m25p,fast-read; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ bootinfo@0 { -+ reg = <0x0 0x20000>; -+ }; -+ -+ fsbl@20000 { -+ reg = <0x20000 0x80000>; -+ }; -+ -+ env@a0000 { -+ reg = <0xa0000 0x10000>; -+ }; -+ -+ esos@b0000 { -+ reg = <0xb0000 0x100000>; -+ }; -+ -+ opensbi@1b0000 { -+ reg = <0x1b0000 0x60000>; -+ }; -+ -+ uboot@210000 { -+ reg = <0x210000 0x5f0000>; -+ }; -+ }; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_0_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index 252c64af76fe..dffa4d583bb2 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -646,6 +646,27 @@ pwm19-2-pins { - }; - }; - -+ /omit-if-no-ref/ -+ qspi_cfg: qspi-cfg { -+ qspi-pins { -+ pinmux = , /* qspi dat0 */ -+ , /* qspi dat1 */ -+ , /* qspi dat2 */ -+ , /* qspi dat3 */ -+ ; /* qspi clk */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ }; -+ -+ qspi-cs0-pins { -+ pinmux = ; /* qspi cs0 */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ }; -+ }; -+ - /omit-if-no-ref/ - uart0_0_cfg: uart0-0-cfg { - uart0-0-pins { -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 809067d6383c..5b17612fe58e 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -1069,6 +1069,23 @@ pll: clock-controller@d4090000 { - #clock-cells = <1>; - }; - -+ qspi: spi@d420c000 { -+ compatible = "spacemit,k3-qspi", -+ "spacemit,k1-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0xd420c000 0x0 0x1000>, -+ <0x0 0xb8000000 0x0 0xc00000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ clocks = <&syscon_apmu CLK_APMU_QSPI_BUS>, -+ <&syscon_apmu CLK_APMU_QSPI>; -+ clock-names = "qspi_en", "qspi"; -+ resets = <&syscon_apmu RESET_APMU_QSPI>, -+ <&syscon_apmu RESET_APMU_QSPI_BUS>; -+ interrupts = <117 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ - syscon_apmu: system-controller@d4282800 { - compatible = "spacemit,k3-syscon-apmu"; - reg = <0x0 0xd4282800 0x0 0x400>; --- -2.53.0 - diff --git a/SPECS/linux/0228-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch b/SPECS/linux/0228-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch deleted file mode 100644 index 9cb7203d99..0000000000 --- a/SPECS/linux/0228-FROMLIST-pinctrl-spacemit-fix-NULL-check-in-spacemit.patch +++ /dev/null @@ -1,49 +0,0 @@ -From aa63c1d8256a65d1899cd336a9dc430b3b5b760e Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 20 May 2026 00:40:07 +0800 -Subject: [PATCH 228/269] FROMLIST: pinctrl: spacemit: fix NULL check in - spacemit_pin_set_config - -spacemit_pin_set_config() looks up the per-pin descriptor with -spacemit_get_pin() then checks the wrong variable for failure: - - const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); - ... - if (!pin) - return -EINVAL; - - reg = spacemit_pin_to_reg(pctrl, spin->pin); - -pin is an unsigned int pin id, where 0 (GPIO_0 / gmac0_rxdv on K3) is a -valid pin, so rejecting it here drops the PAD config write for the first -pin of every group. On K3 Pico-ITX the GMAC RGMII group lists pin 0 as -its first entry, so its drive-strength / bias configuration was silently -ignored. - -The intended guard is against spacemit_get_pin() returning NULL when the -pin id isn't in the SoC's pin table. Check spin instead, which both -restores PAD setup for pin 0 and prevents a NULL deref on spin->pin. - -Fixes: a83c29e1d145 ("pinctrl: spacemit: add support for SpacemiT K1 SoC") -Link: https://lore.kernel.org/r/20260519164007.122574-1-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - drivers/pinctrl/spacemit/pinctrl-k1.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c -index b0be62b1c816..95024e2bb5a5 100644 ---- a/drivers/pinctrl/spacemit/pinctrl-k1.c -+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c -@@ -795,7 +795,7 @@ static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl, - void __iomem *reg; - unsigned int mux; - -- if (!pin) -+ if (!spin) - return -EINVAL; - - reg = spacemit_pin_to_reg(pctrl, spin->pin); --- -2.53.0 - diff --git a/SPECS/linux/0228-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch b/SPECS/linux/0228-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch new file mode 100644 index 0000000000..66d62a1182 --- /dev/null +++ b/SPECS/linux/0228-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch @@ -0,0 +1,32 @@ +From 6b750345486592b1da0cd9ad6425db6948e605d4 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 20 May 2026 00:55:46 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: unconditionally select + ARCH_KEEP_MEMBLOCK + +Select ARCH_KEEP_MEMBLOCK unconditionally. kexec requires memblock +to be kept after boot to initialize the secondary kernel. Device +Tree platforms also need this for kexec support. + +Link: https://lore.kernel.org/r/20260519165546.123105-1-gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 4ba5392f0dca..9f6af32889e2 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -56,7 +56,7 @@ config RISCV + select ARCH_HAS_UBSAN + select ARCH_HAS_VDSO_ARCH_DATA if HAVE_GENERIC_VDSO + select ARCH_HAVE_NMI_SAFE_CMPXCHG +- select ARCH_KEEP_MEMBLOCK if ACPI ++ select ARCH_KEEP_MEMBLOCK + select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU + select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX + select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT +-- +2.53.0 + diff --git a/SPECS/linux/0229-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch b/SPECS/linux/0229-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch new file mode 100644 index 0000000000..ad190dc255 --- /dev/null +++ b/SPECS/linux/0229-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch @@ -0,0 +1,51 @@ +From 52284947498fc778578169b72bd26106a8545dd8 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 20 May 2026 01:06:41 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: kexec_file: Constrain segment placement + to direct map + +When kexec_file_load places segments with buf_max=ULONG_MAX and +top_down=true, they land at the highest available physical addresses. +On RISC-V the size of the linear mapping is determined by the active +VM mode: SV39 caps the direct map at roughly 128GB, while SV48/SV57 +extend the range substantially further. When the installed physical +memory exceeds the direct map size of the active mode, top-down +placement puts DTB/initrd at physical addresses outside the linearly +mapped region. The kexec'd kernel cannot reach them during early +boot, triggering a page fault at memcmp in start_kernel. + +Fix by constraining buf_max to PFN_PHYS(max_low_pfn), which reflects +the runtime direct map boundary for the active VM mode (SV39/SV48/ +SV57). This keeps all kexec segments within the linearly mapped +region while preserving the upstream top_down allocation strategy. + +Link: https://lore.kernel.org/r/20260519170641.123517-1-gaohan@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/kernel/machine_kexec_file.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c +index 54e2d9552e93..59d4bbc848a8 100644 +--- a/arch/riscv/kernel/machine_kexec_file.c ++++ b/arch/riscv/kernel/machine_kexec_file.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -266,7 +267,7 @@ int load_extra_segments(struct kimage *image, unsigned long kernel_start, + + kbuf.image = image; + kbuf.buf_min = kernel_start + kernel_len; +- kbuf.buf_max = ULONG_MAX; ++ kbuf.buf_max = PFN_PHYS(max_low_pfn); + + #ifdef CONFIG_CRASH_DUMP + /* Add elfcorehdr */ +-- +2.53.0 + diff --git a/SPECS/linux/0229-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch b/SPECS/linux/0229-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch deleted file mode 100644 index 71b566d342..0000000000 --- a/SPECS/linux/0229-FROMLIST-riscv-unconditionally-select-ARCH_KEEP_MEMB.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 33445409b8c34a18dc9adbc0b571556f8b78dc1d Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 20 May 2026 00:55:46 +0800 -Subject: [PATCH 229/269] FROMLIST: riscv: unconditionally select - ARCH_KEEP_MEMBLOCK - -Select ARCH_KEEP_MEMBLOCK unconditionally. kexec requires memblock -to be kept after boot to initialize the secondary kernel. Device -Tree platforms also need this for kexec support. - -Link: https://lore.kernel.org/r/20260519165546.123105-1-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index 4ba5392f0dca..9f6af32889e2 100644 ---- a/arch/riscv/Kconfig -+++ b/arch/riscv/Kconfig -@@ -56,7 +56,7 @@ config RISCV - select ARCH_HAS_UBSAN - select ARCH_HAS_VDSO_ARCH_DATA if HAVE_GENERIC_VDSO - select ARCH_HAVE_NMI_SAFE_CMPXCHG -- select ARCH_KEEP_MEMBLOCK if ACPI -+ select ARCH_KEEP_MEMBLOCK - select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU - select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX - select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT --- -2.53.0 - diff --git a/SPECS/linux/0230-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch b/SPECS/linux/0230-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch new file mode 100644 index 0000000000..cb4d8de704 --- /dev/null +++ b/SPECS/linux/0230-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch @@ -0,0 +1,48 @@ +From 46a2ee7a1d59c311a3c36f98223855e2b6c8500f Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 20 May 2026 23:45:27 +0000 +Subject: [RUYI PATCH] FROMLIST: dt-bindings: riscv: spacemit: Add K3 + CoM260-IFX board +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The SpacemiT K3 CoM260-IFX board combines a 69.6 × 45 mm compute module +with a reference carrier board. + +The module integrates up to 32GB LPDDR5 memory, UFS storage, Micro SD +card slot and includes interfaces such as dual MIPI CSI-2 connectors, +M.2 expansion, USB 3.0, Gigabit Ethernet, DisplayPort, and a 40-pin +expansion header. + +The carrier board is intended as a general-purpose development platform +for CoM260 module and exposes interfaces for all of storage, display, +networking, and camera connectivity. + +Acked-by: Conor Dooley +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260520-02-k3-com260-ifx-v2-1-d55095457cf0@kernel.org +Signed-off-by: Han Gao +--- + Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml +index b958b94a924d..b753e27b68df 100644 +--- a/Documentation/devicetree/bindings/riscv/spacemit.yaml ++++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml +@@ -31,6 +31,11 @@ properties: + - enum: + - spacemit,k3-pico-itx + - const: spacemit,k3 ++ - items: ++ - enum: ++ - spacemit,k3-com260-ifx ++ - const: spacemit,k3-com260 ++ - const: spacemit,k3 + + additionalProperties: true + +-- +2.53.0 + diff --git a/SPECS/linux/0230-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch b/SPECS/linux/0230-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch deleted file mode 100644 index b8f5f806b7..0000000000 --- a/SPECS/linux/0230-FROMLIST-riscv-kexec_file-Constrain-segment-placemen.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 08ceb81a4fd20f88e3b88dec762e7f55e3a05a72 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 20 May 2026 01:06:41 +0800 -Subject: [PATCH 230/269] FROMLIST: riscv: kexec_file: Constrain segment - placement to direct map - -When kexec_file_load places segments with buf_max=ULONG_MAX and -top_down=true, they land at the highest available physical addresses. -On RISC-V the size of the linear mapping is determined by the active -VM mode: SV39 caps the direct map at roughly 128GB, while SV48/SV57 -extend the range substantially further. When the installed physical -memory exceeds the direct map size of the active mode, top-down -placement puts DTB/initrd at physical addresses outside the linearly -mapped region. The kexec'd kernel cannot reach them during early -boot, triggering a page fault at memcmp in start_kernel. - -Fix by constraining buf_max to PFN_PHYS(max_low_pfn), which reflects -the runtime direct map boundary for the active VM mode (SV39/SV48/ -SV57). This keeps all kexec segments within the linearly mapped -region while preserving the upstream top_down allocation strategy. - -Link: https://lore.kernel.org/r/20260519170641.123517-1-gaohan@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/kernel/machine_kexec_file.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c -index 54e2d9552e93..59d4bbc848a8 100644 ---- a/arch/riscv/kernel/machine_kexec_file.c -+++ b/arch/riscv/kernel/machine_kexec_file.c -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -266,7 +267,7 @@ int load_extra_segments(struct kimage *image, unsigned long kernel_start, - - kbuf.image = image; - kbuf.buf_min = kernel_start + kernel_len; -- kbuf.buf_max = ULONG_MAX; -+ kbuf.buf_max = PFN_PHYS(max_low_pfn); - - #ifdef CONFIG_CRASH_DUMP - /* Add elfcorehdr */ --- -2.53.0 - diff --git a/SPECS/linux/0231-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch b/SPECS/linux/0231-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch deleted file mode 100644 index b4add99c09..0000000000 --- a/SPECS/linux/0231-FROMLIST-dt-bindings-riscv-spacemit-Add-K3-CoM260-IF.patch +++ /dev/null @@ -1,48 +0,0 @@ -From cb09274e58a8ee6106045f3ac535ff6099a0198c Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 20 May 2026 23:45:27 +0000 -Subject: [PATCH 231/269] FROMLIST: dt-bindings: riscv: spacemit: Add K3 - CoM260-IFX board -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The SpacemiT K3 CoM260-IFX board combines a 69.6 × 45 mm compute module -with a reference carrier board. - -The module integrates up to 32GB LPDDR5 memory, UFS storage, Micro SD -card slot and includes interfaces such as dual MIPI CSI-2 connectors, -M.2 expansion, USB 3.0, Gigabit Ethernet, DisplayPort, and a 40-pin -expansion header. - -The carrier board is intended as a general-purpose development platform -for CoM260 module and exposes interfaces for all of storage, display, -networking, and camera connectivity. - -Acked-by: Conor Dooley -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260520-02-k3-com260-ifx-v2-1-d55095457cf0@kernel.org -Signed-off-by: Han Gao ---- - Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml -index b958b94a924d..b753e27b68df 100644 ---- a/Documentation/devicetree/bindings/riscv/spacemit.yaml -+++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml -@@ -31,6 +31,11 @@ properties: - - enum: - - spacemit,k3-pico-itx - - const: spacemit,k3 -+ - items: -+ - enum: -+ - spacemit,k3-com260-ifx -+ - const: spacemit,k3-com260 -+ - const: spacemit,k3 - - additionalProperties: true - --- -2.53.0 - diff --git a/SPECS/linux/0231-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch b/SPECS/linux/0231-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch new file mode 100644 index 0000000000..6a94b89302 --- /dev/null +++ b/SPECS/linux/0231-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch @@ -0,0 +1,306 @@ +From 5435879db98ebd75bc4b44df1ac20e47be865d02 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Wed, 20 May 2026 23:45:28 +0000 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Initial support for + CoM260-IFX board + +The K3 CoM260-IFX board combine with one 260 pins "Gold Finger" computer +module with a carrier board. The module integrates the K3 SoC, LPDDR5, +UFS storage, Gigabit Ethernet, Micro SD card, PMIC Chip. The board offers +a comprehensive array of interfaces, including MIPI-DSI, MIPI-CSI, +DisplayPort, SDIO, SPI, I2S, I2C, CAN-FD, PWM, UART, USB, PCIe, and GMAC. + +Add initial support for enabling Serial UART and ethernet. + +Signed-off-by: Yixun Lan +Link: https://lore.kernel.org/r/20260520-02-k3-com260-ifx-v2-2-d55095457cf0@kernel.org +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/Makefile | 1 + + .../riscv/boot/dts/spacemit/k3-com260-ifx.dts | 21 ++ + arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 190 ++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 +++ + 4 files changed, 245 insertions(+) + create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts + create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260.dtsi + +diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile +index 7e2b87702571..bf233ec0683b 100644 +--- a/arch/riscv/boot/dts/spacemit/Makefile ++++ b/arch/riscv/boot/dts/spacemit/Makefile +@@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb ++dtb-$(CONFIG_ARCH_SPACEMIT) += k3-com260-ifx.dtb + dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb +diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +new file mode 100644 +index 000000000000..238bb03d0e9e +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +@@ -0,0 +1,21 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ * Copyright (c) 2026 Yixun Lan ++ */ ++ ++#include "k3-com260.dtsi" ++ ++/ { ++ model = "SpacemiT K3 CoM260 IFX"; ++ compatible = "spacemit,k3-com260-ifx", "spacemit,k3-com260", "spacemit,k3"; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = ð1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +new file mode 100644 +index 000000000000..a38d7b738258 +--- /dev/null ++++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +@@ -0,0 +1,190 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd ++ * Copyright (c) 2026 Yixun Lan ++ */ ++#include ++ ++#include "k3.dtsi" ++#include "k3-pinctrl.dtsi" ++ ++/ { ++ model = "SpacemiT K3 CoM260 Module"; ++ compatible = "spacemit,k3-com260", "spacemit,k3"; ++ ++ memory@100000000 { ++ device_type = "memory"; ++ reg = <0x1 0x00000000 0x4 0x00000000>; ++ }; ++ ++ reg_5v_sys: regulator-5v-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "P5V0_SYS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++}; ++ ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8_cfg>; ++ status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; ++ vin1-supply = <®_5v_sys>; ++ vin2-supply = <®_5v_sys>; ++ vin3-supply = <®_5v_sys>; ++ vin4-supply = <®_5v_sys>; ++ vin5-supply = <®_5v_sys>; ++ vin6-supply = <®_5v_sys>; ++ aldoin-supply = <®_5v_sys>; ++ dldoin1-supply = <&buck4>; ++ dldoin2-supply = <&buck4>; ++ ++ regulators { ++ buck1: buck1 { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2: buck2 { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3: buck3 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4: buck4 { ++ regulator-min-microvolt = <2100000>; ++ regulator-max-microvolt = <2100000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6: buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <500000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1: aldo1 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ aldo2: aldo2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ aldo3: aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4: aldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo1: dldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo2: dldo2 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo3: dldo3 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo4: dldo4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ }; ++ ++ dldo5: dldo5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo6: dldo6 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ dldo7: dldo7 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ }; ++ }; ++}; ++ ++ð1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1_rgmii_0_cfg>, <&gmac1_phy_0_cfg>; ++ phy-mode = "rgmii-id"; ++ phy-handle = <&phy1>; ++ status = "okay"; ++ ++ mdio { ++ phy1: phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <10000>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_0_cfg>; ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index dffa4d583bb2..846d5e8cc783 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -45,6 +45,39 @@ gmac0-phy-0-pins { + }; + }; + ++ gmac1_rgmii_0_cfg: gmac1-rgmii-0-cfg { ++ gmac1-rgmii-0-pins { ++ pinmux = , /* gmac1_rxdv */ ++ , /* gmac1 rx d0 */ ++ , /* gmac1 rx d1 */ ++ , /* gmac1 rx_clk */ ++ , /* gmac1 rx d2 */ ++ , /* gmac1 rx d3 */ ++ , /* gmac1 tx d0 */ ++ , /* gmac1 tx d1 */ ++ , /* gmac1 tx clk */ ++ , /* gmac1 tx d2 */ ++ , /* gmac1 tx d3 */ ++ , /* gmac1 tx_en */ ++ , /* gmac1 mdc */ ++ ; /* gmac1 mdio */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ power-source = <1800>; ++ }; ++ }; ++ ++ gmac1_phy_0_cfg: gmac1-phy-0-cfg { ++ gmac1-phy-0-pins { ++ pinmux = ; /* gmac1 int */ ++ ++ bias-disable; ++ drive-strength = <25>; ++ power-source = <1800>; ++ }; ++ }; ++ + /omit-if-no-ref/ + i2c8_cfg: i2c8-cfg { + i2c8-pins { +-- +2.53.0 + diff --git a/SPECS/linux/0232-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch b/SPECS/linux/0232-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch new file mode 100644 index 0000000000..04e4c8d0d3 --- /dev/null +++ b/SPECS/linux/0232-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch @@ -0,0 +1,178 @@ +From 3dcca8e2192d07a104e77ae41361bc607e8e422c Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Wed, 20 May 2026 18:00:00 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable PMIC on OrangePi + R2S + +Enable the i2c8 interface and add the connected SpacemiT P1 PMIC and +its associated regulators to support voltage regulation on the board. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20260520100000.575719-1-amadeus@jmu.edu.cn +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-r2s.dts | 134 ++++++++++++++++++ + 1 file changed, 134 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index 1ecc40749e5a..b13a8d6a2670 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -13,6 +13,7 @@ / { + compatible = "xunlong,orangepi-r2s", "spacemit,k1"; + + aliases { ++ i2c8 = &i2c8; + serial0 = &uart0; + ethernet0 = ð0; + ethernet1 = ð1; +@@ -22,6 +23,15 @@ chosen { + stdout-path = "serial0"; + }; + ++ vcc4v0: regulator-vcc4v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc4v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ }; ++ + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + enable-active-high; +@@ -94,6 +104,130 @@ rgmii1: phy@1 { + }; + }; + ++&i2c8 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c8_cfg>; ++ status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ vin1-supply = <&vcc4v0>; ++ vin2-supply = <&vcc4v0>; ++ vin3-supply = <&vcc4v0>; ++ vin4-supply = <&vcc4v0>; ++ vin5-supply = <&vcc4v0>; ++ vin6-supply = <&vcc4v0>; ++ aldoin-supply = <&vcc4v0>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; ++ ++ regulators { ++ buck1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3_1v8: buck3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4_3v3: buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5: buck5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1_3v3: aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ aldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ dldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo7 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ }; ++ }; ++}; ++ + &pdma { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux/0232-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch b/SPECS/linux/0232-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch deleted file mode 100644 index 63e3c3cc97..0000000000 --- a/SPECS/linux/0232-FROMLIST-riscv-dts-spacemit-k3-Initial-support-for-C.patch +++ /dev/null @@ -1,306 +0,0 @@ -From d36d998cfb86010f667695ea1fe0e09400b9b5a7 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Wed, 20 May 2026 23:45:28 +0000 -Subject: [PATCH 232/269] FROMLIST: riscv: dts: spacemit: k3: Initial support - for CoM260-IFX board - -The K3 CoM260-IFX board combine with one 260 pins "Gold Finger" computer -module with a carrier board. The module integrates the K3 SoC, LPDDR5, -UFS storage, Gigabit Ethernet, Micro SD card, PMIC Chip. The board offers -a comprehensive array of interfaces, including MIPI-DSI, MIPI-CSI, -DisplayPort, SDIO, SPI, I2S, I2C, CAN-FD, PWM, UART, USB, PCIe, and GMAC. - -Add initial support for enabling Serial UART and ethernet. - -Signed-off-by: Yixun Lan -Link: https://lore.kernel.org/r/20260520-02-k3-com260-ifx-v2-2-d55095457cf0@kernel.org -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/Makefile | 1 + - .../riscv/boot/dts/spacemit/k3-com260-ifx.dts | 21 ++ - arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 190 ++++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 +++ - 4 files changed, 245 insertions(+) - create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts - create mode 100644 arch/riscv/boot/dts/spacemit/k3-com260.dtsi - -diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile -index 7e2b87702571..bf233ec0683b 100644 ---- a/arch/riscv/boot/dts/spacemit/Makefile -+++ b/arch/riscv/boot/dts/spacemit/Makefile -@@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb -+dtb-$(CONFIG_ARCH_SPACEMIT) += k3-com260-ifx.dtb - dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb -diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts -new file mode 100644 -index 000000000000..238bb03d0e9e ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd -+ * Copyright (c) 2026 Yixun Lan -+ */ -+ -+#include "k3-com260.dtsi" -+ -+/ { -+ model = "SpacemiT K3 CoM260 IFX"; -+ compatible = "spacemit,k3-com260-ifx", "spacemit,k3-com260", "spacemit,k3"; -+ -+ aliases { -+ serial0 = &uart0; -+ ethernet0 = ð1; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi -new file mode 100644 -index 000000000000..a38d7b738258 ---- /dev/null -+++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi -@@ -0,0 +1,190 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd -+ * Copyright (c) 2026 Yixun Lan -+ */ -+#include -+ -+#include "k3.dtsi" -+#include "k3-pinctrl.dtsi" -+ -+/ { -+ model = "SpacemiT K3 CoM260 Module"; -+ compatible = "spacemit,k3-com260", "spacemit,k3"; -+ -+ memory@100000000 { -+ device_type = "memory"; -+ reg = <0x1 0x00000000 0x4 0x00000000>; -+ }; -+ -+ reg_5v_sys: regulator-5v-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "P5V0_SYS"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-always-on; -+ }; -+}; -+ -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; -+ vin1-supply = <®_5v_sys>; -+ vin2-supply = <®_5v_sys>; -+ vin3-supply = <®_5v_sys>; -+ vin4-supply = <®_5v_sys>; -+ vin5-supply = <®_5v_sys>; -+ vin6-supply = <®_5v_sys>; -+ aldoin-supply = <®_5v_sys>; -+ dldoin1-supply = <&buck4>; -+ dldoin2-supply = <&buck4>; -+ -+ regulators { -+ buck1: buck1 { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2: buck2 { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3: buck3 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4: buck4 { -+ regulator-min-microvolt = <2100000>; -+ regulator-max-microvolt = <2100000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6: buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <500000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1: aldo1 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ aldo2: aldo2 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ aldo3: aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4: aldo4 { -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo1: dldo1 { -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo2: dldo2 { -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo3: dldo3 { -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo4: dldo4 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ }; -+ -+ dldo5: dldo5 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo6: dldo6 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ dldo7: dldo7 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ }; -+ }; -+}; -+ -+ð1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1_rgmii_0_cfg>, <&gmac1_phy_0_cfg>; -+ phy-mode = "rgmii-id"; -+ phy-handle = <&phy1>; -+ status = "okay"; -+ -+ mdio { -+ phy1: phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <10000>; -+ }; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_0_cfg>; -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index dffa4d583bb2..846d5e8cc783 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -45,6 +45,39 @@ gmac0-phy-0-pins { - }; - }; - -+ gmac1_rgmii_0_cfg: gmac1-rgmii-0-cfg { -+ gmac1-rgmii-0-pins { -+ pinmux = , /* gmac1_rxdv */ -+ , /* gmac1 rx d0 */ -+ , /* gmac1 rx d1 */ -+ , /* gmac1 rx_clk */ -+ , /* gmac1 rx d2 */ -+ , /* gmac1 rx d3 */ -+ , /* gmac1 tx d0 */ -+ , /* gmac1 tx d1 */ -+ , /* gmac1 tx clk */ -+ , /* gmac1 tx d2 */ -+ , /* gmac1 tx d3 */ -+ , /* gmac1 tx_en */ -+ , /* gmac1 mdc */ -+ ; /* gmac1 mdio */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ power-source = <1800>; -+ }; -+ }; -+ -+ gmac1_phy_0_cfg: gmac1-phy-0-cfg { -+ gmac1-phy-0-pins { -+ pinmux = ; /* gmac1 int */ -+ -+ bias-disable; -+ drive-strength = <25>; -+ power-source = <1800>; -+ }; -+ }; -+ - /omit-if-no-ref/ - i2c8_cfg: i2c8-cfg { - i2c8-pins { --- -2.53.0 - diff --git a/SPECS/linux/0233-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch b/SPECS/linux/0233-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch deleted file mode 100644 index 055ae7c4e6..0000000000 --- a/SPECS/linux/0233-FROMLIST-riscv-dts-spacemit-enable-PMIC-on-OrangePi-.patch +++ /dev/null @@ -1,178 +0,0 @@ -From 1f90376c94530efd9eeb3c0c5b9f76466335b3f0 Mon Sep 17 00:00:00 2001 -From: Chukun Pan -Date: Wed, 20 May 2026 18:00:00 +0800 -Subject: [PATCH 233/269] FROMLIST: riscv: dts: spacemit: enable PMIC on - OrangePi R2S - -Enable the i2c8 interface and add the connected SpacemiT P1 PMIC and -its associated regulators to support voltage regulation on the board. - -Signed-off-by: Chukun Pan -Link: https://lore.kernel.org/r/20260520100000.575719-1-amadeus@jmu.edu.cn -Signed-off-by: Han Gao ---- - .../boot/dts/spacemit/k1-orangepi-r2s.dts | 134 ++++++++++++++++++ - 1 file changed, 134 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -index 1ecc40749e5a..b13a8d6a2670 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts -@@ -13,6 +13,7 @@ / { - compatible = "xunlong,orangepi-r2s", "spacemit,k1"; - - aliases { -+ i2c8 = &i2c8; - serial0 = &uart0; - ethernet0 = ð0; - ethernet1 = ð1; -@@ -22,6 +23,15 @@ chosen { - stdout-path = "serial0"; - }; - -+ vcc4v0: regulator-vcc4v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc4v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ }; -+ - vcc5v0_usb: regulator-vcc5v0-usb { - compatible = "regulator-fixed"; - enable-active-high; -@@ -94,6 +104,130 @@ rgmii1: phy@1 { - }; - }; - -+&i2c8 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c8_cfg>; -+ status = "okay"; -+ -+ pmic@41 { -+ compatible = "spacemit,p1"; -+ reg = <0x41>; -+ interrupts = <64>; -+ vin1-supply = <&vcc4v0>; -+ vin2-supply = <&vcc4v0>; -+ vin3-supply = <&vcc4v0>; -+ vin4-supply = <&vcc4v0>; -+ vin5-supply = <&vcc4v0>; -+ vin6-supply = <&vcc4v0>; -+ aldoin-supply = <&vcc4v0>; -+ dldoin1-supply = <&buck5>; -+ dldoin2-supply = <&buck5>; -+ -+ regulators { -+ buck1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck3_1v8: buck3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck4_3v3: buck4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck5: buck5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ buck6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3450000>; -+ regulator-ramp-delay = <5000>; -+ regulator-always-on; -+ }; -+ -+ aldo1_3v3: aldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ aldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ aldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo1 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-boot-on; -+ }; -+ -+ dldo2 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo3 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo4 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo5 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ -+ dldo6 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ regulator-always-on; -+ }; -+ -+ dldo7 { -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <3400000>; -+ }; -+ }; -+ }; -+}; -+ - &pdma { - status = "okay"; - }; --- -2.53.0 - diff --git a/SPECS/linux/0233-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux/0233-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch new file mode 100644 index 0000000000..5d5c185f40 --- /dev/null +++ b/SPECS/linux/0233-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch @@ -0,0 +1,35 @@ +From 66a9c4fe52bf3e7fd8613e693dbda3e838fabbf7 Mon Sep 17 00:00:00 2001 +From: Jennifer Berringer +Date: Wed, 20 May 2026 07:11:50 -0400 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: set console baud rate on + OrangePi RV2 + +Set the baud rate to 115200, matching what is used by U-Boot on this +platform so that the console is usable even when console options are not +specified in cmdline. + +Fixes: bab8dea259100 ("riscv: dts: spacemit: Add OrangePi RV2 board device tree") +Signed-off-by: Jennifer Berringer +Reviewed-by: Yixun Lan +Link: https://lore.kernel.org/r/20260520111150.3300707-1-jberring@redhat.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +index 0b4d4d1418e2..131062325e08 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +@@ -22,7 +22,7 @@ aliases { + }; + + chosen { +- stdout-path = "serial0"; ++ stdout-path = "serial0:115200n8"; + }; + + pcie_vcc3v3: regulator-pcie-vcc3v3 { +-- +2.53.0 + diff --git a/SPECS/linux/0234-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch b/SPECS/linux/0234-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch new file mode 100644 index 0000000000..2b2db5589c --- /dev/null +++ b/SPECS/linux/0234-FROMLIST-riscv-dts-spacemit-k3-Add-Ziccrse-extension.patch @@ -0,0 +1,99 @@ +From f4f1db3987e59b28388b549e4ecdb8a11068604a Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Tue, 26 May 2026 15:22:58 -0400 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: k3: Add Ziccrse + extension for X100 cores + +Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse +provides a forward progress guarantee on LR/SC sequences in main +memory regions with cacheability and coherence PMAs. + +The SpacemiT X100 core supports it per the SpacemiT K3 hardware +specification. + +Signed-off-by: Guodong Xu +Link: https://lore.kernel.org/r/20260526-k3-ziccrse-v1-1-c759792ca3a3@riscstar.com +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 5b17612fe58e..ed046714a7ac 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -36,7 +36,7 @@ cpu_0: cpu@0 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -77,7 +77,7 @@ cpu_1: cpu@1 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -118,7 +118,7 @@ cpu_2: cpu@2 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -159,7 +159,7 @@ cpu_3: cpu@3 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -200,7 +200,7 @@ cpu_4: cpu@4 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -241,7 +241,7 @@ cpu_5: cpu@5 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -282,7 +282,7 @@ cpu_6: cpu@6 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +@@ -323,7 +323,7 @@ cpu_7: cpu@7 { + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", +- "ziccamoa", "ziccif", "zicclsm", "zicntr", ++ "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", +-- +2.53.0 + diff --git a/SPECS/linux/0234-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch b/SPECS/linux/0234-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch deleted file mode 100644 index dcc7f89108..0000000000 --- a/SPECS/linux/0234-FROMLIST-riscv-dts-spacemit-set-console-baud-rate-on.patch +++ /dev/null @@ -1,35 +0,0 @@ -From a85d760e89e4b0f68b0f8364289fcfd3fba07907 Mon Sep 17 00:00:00 2001 -From: Jennifer Berringer -Date: Wed, 20 May 2026 07:11:50 -0400 -Subject: [PATCH 234/269] FROMLIST: riscv: dts: spacemit: set console baud rate - on OrangePi RV2 - -Set the baud rate to 115200, matching what is used by U-Boot on this -platform so that the console is usable even when console options are not -specified in cmdline. - -Fixes: bab8dea259100 ("riscv: dts: spacemit: Add OrangePi RV2 board device tree") -Signed-off-by: Jennifer Berringer -Reviewed-by: Yixun Lan -Link: https://lore.kernel.org/r/20260520111150.3300707-1-jberring@redhat.com -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -index 0b4d4d1418e2..131062325e08 100644 ---- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts -@@ -22,7 +22,7 @@ aliases { - }; - - chosen { -- stdout-path = "serial0"; -+ stdout-path = "serial0:115200n8"; - }; - - pcie_vcc3v3: regulator-pcie-vcc3v3 { --- -2.53.0 - diff --git a/SPECS/linux/0235-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch b/SPECS/linux/0235-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch new file mode 100644 index 0000000000..5fea2bed54 --- /dev/null +++ b/SPECS/linux/0235-FROMLIST-RISC-V-KVM-Enhance-the-logging-check-for-mm.patch @@ -0,0 +1,52 @@ +From 9accda047320df7f2dd06ca1f0d0bfc94a6b4d7f Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 28 May 2026 19:38:39 +0800 +Subject: [RUYI PATCH] FROMLIST: RISC-V: KVM: Enhance the logging check for mmu + mapping + +When enabling dirty ring, the dirty bitmap is disable, and the logging +check is always false as the RISC-V architecture does not select +"NEED_KVM_DIRTY_RING_WITH_BITMAP". Although the dirty log is recorded +since the write path already trying to add the dirty log, the logic for +logging check is broken and some side effect will occurs. + +Enhance the logging check for mmu mapping so it can check both the dirty +ring and the dirty bitmap. + +Signed-off-by: Inochi Amaoto +Link: https://lore.kernel.org/r/20260528113840.2629186-1-inochiama@gmail.com +Signed-off-by: Han Gao +--- + arch/riscv/kvm/mmu.c | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c +index 088d33ba90ed..2d0d6d8b3dbd 100644 +--- a/arch/riscv/kvm/mmu.c ++++ b/arch/riscv/kvm/mmu.c +@@ -157,9 +157,8 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, + enum kvm_mr_change change) + { + /* +- * At this point memslot has been committed and there is an +- * allocated dirty_bitmap[], dirty pages will be tracked while +- * the memory slot is write protected. ++ * At this point memslot has been committed and dirty pages will be ++ * tracked while the memory slot is write protected. + */ + if (change != KVM_MR_DELETE && new->flags & KVM_MEM_LOG_DIRTY_PAGES) { + if (kvm_dirty_log_manual_protect_and_init_set(kvm)) +@@ -457,8 +456,8 @@ int kvm_riscv_mmu_map(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot, + struct vm_area_struct *vma; + struct kvm *kvm = vcpu->kvm; + struct kvm_mmu_memory_cache *pcache = &vcpu->arch.mmu_page_cache; +- bool logging = (memslot->dirty_bitmap && +- !(memslot->flags & KVM_MEM_READONLY)) ? true : false; ++ bool logging = kvm_slot_dirty_track_enabled(memslot) && ++ !(memslot->flags & KVM_MEM_READONLY); + unsigned long vma_pagesize, mmu_seq; + struct kvm_gstage gstage; + struct page *page; +-- +2.53.0 + diff --git a/SPECS/linux/0235-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch b/SPECS/linux/0235-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch deleted file mode 100644 index 0612b7dd84..0000000000 --- a/SPECS/linux/0235-FROMLIST-riscv-mm-Call-mark_new_valid_map-after-hotp.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 37149bd886755a603be2ffa3db150c8e317e83f4 Mon Sep 17 00:00:00 2001 -From: Vivian Wang -Date: Mon, 25 May 2026 12:23:29 +0800 -Subject: [PATCH 235/269] FROMLIST: riscv: mm: Call mark_new_valid_map() after - hotplugging vmemmap - -section_activate() creates new mappings in the vmemmap range without -flushing TLB, which may cause faults on some RISC-V implementations that -cache non-present PTEs and crashes. - -This seems to be most easily reproduced with DEBUG_VM=y and -PAGE_POISONING=y, which causes these newly mapped struct pages to be -poisoned i.e. written to immediately after mapping. - -Add a hook vmemmap_populate_finalize() in __populate_section_memmap(), -and implement it as calling mark_new_valid_map() on RISC-V, which -arranges for the exception handler to deal with these faults if they -happen. - -Signed-off-by: Vivian Wang -Link: https://lore.kernel.org/r/20260525-mark-after-vmemmap-populate-v1-1-e698d859ba16@iscas.ac.cn -Signed-off-by: Han Gao ---- - arch/riscv/mm/init.c | 6 ++++++ - include/linux/mm.h | 1 + - mm/sparse-vmemmap.c | 6 ++++++ - 3 files changed, 13 insertions(+) - -diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c -index cf4f3ec1cca5..8babe9a8e954 100644 ---- a/arch/riscv/mm/init.c -+++ b/arch/riscv/mm/init.c -@@ -1494,6 +1494,12 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, - */ - return vmemmap_populate_hugepages(start, end, node, altmap); - } -+ -+void __meminit vmemmap_populate_finalize(void) -+{ -+ /* Avoid faults on cached non-present TLB entries. */ -+ mark_new_valid_map(); -+} - #endif - - #if defined(CONFIG_MMU) && defined(CONFIG_64BIT) -diff --git a/include/linux/mm.h b/include/linux/mm.h -index 2d6d268a2798..7ff44f1cc6b5 100644 ---- a/include/linux/mm.h -+++ b/include/linux/mm.h -@@ -4507,6 +4507,7 @@ int vmemmap_populate_hugepages(unsigned long start, unsigned long end, - int node, struct vmem_altmap *altmap); - int vmemmap_populate(unsigned long start, unsigned long end, int node, - struct vmem_altmap *altmap); -+void vmemmap_populate_finalize(void); - int vmemmap_populate_hvo(unsigned long start, unsigned long end, int node, - unsigned long headsize); - int vmemmap_undo_hvo(unsigned long start, unsigned long end, int node, -diff --git a/mm/sparse-vmemmap.c b/mm/sparse-vmemmap.c -index 37522d6cb398..3fa299ce0938 100644 ---- a/mm/sparse-vmemmap.c -+++ b/mm/sparse-vmemmap.c -@@ -558,6 +558,10 @@ static int __meminit vmemmap_populate_compound_pages(unsigned long start_pfn, - - #endif - -+void __weak __meminit vmemmap_populate_finalize(void) -+{ -+} -+ - struct page * __meminit __populate_section_memmap(unsigned long pfn, - unsigned long nr_pages, int nid, struct vmem_altmap *altmap, - struct dev_pagemap *pgmap) -@@ -575,6 +579,8 @@ struct page * __meminit __populate_section_memmap(unsigned long pfn, - else - r = vmemmap_populate(start, end, nid, altmap); - -+ vmemmap_populate_finalize(); -+ - if (r < 0) - return NULL; - --- -2.53.0 - diff --git a/SPECS/linux/0236-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch b/SPECS/linux/0236-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch new file mode 100644 index 0000000000..0cdb22f312 --- /dev/null +++ b/SPECS/linux/0236-FROMLIST-riscv-dts-spacemit-enable-PCIe-on-OrangePi-.patch @@ -0,0 +1,75 @@ +From 0b373ea3428d6d8188b68f0d1ee65c707f29c812 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Tue, 2 Jun 2026 18:00:00 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: dts: spacemit: enable PCIe on OrangePi + R2S + +Enable the two RTL8125 network controllers and corresponding +PHYs connected via the PCIe controllers on the OrangePi R2S. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20260602100000.2402784-1-amadeus@jmu.edu.cn +Signed-off-by: Han Gao +--- + .../boot/dts/spacemit/k1-orangepi-r2s.dts | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +index b13a8d6a2670..919e5b451109 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +@@ -23,6 +23,14 @@ chosen { + stdout-path = "serial0"; + }; + ++ pcie_vcc3v3: regulator-pcie-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie_vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + vcc4v0: regulator-vcc4v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0"; +@@ -228,6 +236,36 @@ dldo7 { + }; + }; + ++&pcie1_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_3_cfg>; ++ status = "okay"; ++}; ++ ++&pcie1_port { ++ phys = <&pcie1_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++&pcie2_phy { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_4_cfg>; ++ status = "okay"; ++}; ++ ++&pcie2_port { ++ phys = <&pcie2_phy>; ++ vpcie3v3-supply = <&pcie_vcc3v3>; ++}; ++ ++&pcie2 { ++ status = "okay"; ++}; ++ + &pdma { + status = "okay"; + }; +-- +2.53.0 + diff --git a/SPECS/linux/0236-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch b/SPECS/linux/0236-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch deleted file mode 100644 index 22eccc6e66..0000000000 --- a/SPECS/linux/0236-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 93f38f49aaab1340f11d04d3f712a4bb47814c26 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Mon, 24 Nov 2025 20:38:44 +0800 -Subject: [PATCH 236/269] XUANTIE: riscv: dts: th1520: add licheepi4a 16g - support - -From: https://github.com/revyos/th1520-linux-kernel/commit/01a510898e41e704bee1fe58a2c0c0a29cb96548 - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/thead/Makefile | 1 + - .../boot/dts/thead/th1520-lichee-pi-4a-16g.dts | 18 ++++++++++++++++++ - 2 files changed, 19 insertions(+) - create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts - -diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile -index b55a17127c2b..281849e71ccb 100644 ---- a/arch/riscv/boot/dts/thead/Makefile -+++ b/arch/riscv/boot/dts/thead/Makefile -@@ -1,2 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb -+dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a-16g.dtb -diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts -new file mode 100644 -index 000000000000..a3a991baf716 ---- /dev/null -+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts -@@ -0,0 +1,18 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2023 Han Gao -+ */ -+ -+/dts-v1/; -+ -+#include "th1520-lichee-pi-4a.dts" -+ -+/ { -+ model = "Sipeed Lichee Pi 4A 16G"; -+ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x00000000 0x4 0x00000000>; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux/0237-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch b/SPECS/linux/0237-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch new file mode 100644 index 0000000000..c0051ae843 --- /dev/null +++ b/SPECS/linux/0237-FROMLIST-iommu-riscv-Add-dependency-between-iommu-an.patch @@ -0,0 +1,105 @@ +From 6c086e87e5aaeb344f1eadf56bd9c79678a3724a Mon Sep 17 00:00:00 2001 +From: Wang Yechao +Date: Thu, 4 Jun 2026 14:55:10 +0800 +Subject: [RUYI PATCH] FROMLIST: iommu/riscv: Add dependency between iommu and + devices + +Commit 9156585280f1 ("ACPI: RIMT: Add dependency between iommu and +devices") adds the dependency between iommu and devices on ACPI +systems. On devicetree systems, the incorrect removal order also +occurs. + +It can be reproduced on the QEMU RISC-V machine if the kernel enables +IOMMU_DMA: + +[ 635.081530] e1000e: EEE TX LPI TIMER: 00000000 +[ 656.100306] rcu: INFO: rcu_sched self-detected stall on CPU +[ 656.101374] rcu: 5-....: (5250 ticks this GP) idle=d774/1/0x4000000000000000 softirq=5173/5185 fqs=2625 +[ 656.102237] rcu: (t=5251 jiffies g=36825 q=101 ncpus=16) +[ 656.103801] CPU: 5 UID: 0 PID: 1958 Comm: reboot Tainted: G W 7.1.0-rc5 #31 PREEMPTLAZY +[ 656.104127] Tainted: [W]=WARN +[ 656.104182] Hardware name: QEMU QEMU Virtual Machine, BIOS 2.7 02/02/2022 +[ 656.104339] epc : riscv_iommu_cmd_sync.constprop.0+0xb8/0x148 +[ 656.105352] ra : riscv_iommu_cmd_sync.constprop.0+0xa8/0x148 +[ 656.105433] epc : ffffffff807ca980 ra : ffffffff807ca970 sp : ff60000085dbf960 +[ 656.105475] gp : ffffffff81e0d798 tp : ff60000084b58e00 t0 : ffffffff80021048 +[ 656.105514] t1 : ff60000081b18400 t2 : 45203a6530303031 s0 : ff60000085dbf9c0 +[ 656.105554] s1 : 00000098c92a567c a0 : 00000098c03986f0 a1 : ff60000085dbf970 +[ 656.105594] a2 : 000024bb5cac6aee a3 : ff200000004f1000 a4 : ff6000008140a040 +[ 656.105632] a5 : 0000000000000669 a6 : 0000000000000000 a7 : 00000000ffffa000 +[ 656.105669] s2 : 0000000000000000 s3 : 00000098c0398308 s4 : 000000000000066a +[ 656.105706] s5 : 0000000008f0d180 s6 : 000000a8d08b8de9 s7 : 0000000000001fff +[ 656.105743] s8 : ff6000008140a040 s9 : ff6000008484cb00 s10: ff200000005cc000 +[ 656.105781] s11: ff600000814652a0 t3 : 000000f000000000 t4 : 0000000000000000 +[ 656.105845] t5 : 0000000000000003 t6 : ff600000841666b0 ssp : 0000000000000000 +[ 656.105883] status: 0000000200000120 badaddr: 0000000000000000 cause: 8000000000000005 +[ 656.106072] riscv_iommu_cmd_sync.constprop.0+0xb8/0x148 +[ 656.106321] riscv_iommu_iotlb_inval+0x120/0x160 +[ 656.106373] riscv_iommu_iotlb_sync+0x48/0x60 +[ 656.106422] __iommu_dma_unmap+0xca/0xf8 +[ 656.106470] iommu_dma_unmap_phys+0x58/0xc8 +[ 656.106517] dma_unmap_phys+0x15c/0x248 +[ 656.106564] dma_unmap_page_attrs+0x1e/0x30 +[ 656.106915] e1000_clean_rx_ring+0x1d2/0x200 [e1000e] +[ 656.107668] e1000e_down+0x168/0x1c8 [e1000e] +[ 656.107995] e1000e_pm_freeze+0x94/0x128 [e1000e] +[ 656.108328] e1000_shutdown+0x28/0x48 [e1000e] +[ 656.108652] pci_device_shutdown+0x34/0x48 +[ 656.108706] device_shutdown+0x104/0x1e8 +[ 656.108752] kernel_restart+0x46/0xb8 +[ 656.108797] __do_sys_reboot+0xc0/0x1c8 +[ 656.108840] __riscv_sys_reboot+0x22/0x38 +[ 656.108882] do_trap_ecall_u+0x236/0x3f8 +[ 656.108947] handle_exception+0x15a/0x166 + +So move the device link into the iommu driver to fix both ACPI and +devicetree systems. + +Fixes: 488ffbf18171 ("iommu/riscv: Paging domain support") +Signed-off-by: Wang Yechao +Link: https://lore.kernel.org/r/20260604145510898G2kTwM2Pr25QE5H8T4Wh6@zte.com.cn +Signed-off-by: Han Gao +--- + drivers/acpi/riscv/rimt.c | 7 ------- + drivers/iommu/riscv/iommu.c | 7 +++++++ + 2 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/acpi/riscv/rimt.c b/drivers/acpi/riscv/rimt.c +index 906282b0e63c..229c4a0d47a3 100644 +--- a/drivers/acpi/riscv/rimt.c ++++ b/drivers/acpi/riscv/rimt.c +@@ -263,13 +263,6 @@ static int rimt_iommu_xlate(struct device *dev, struct acpi_rimt_node *node, u32 + if (!rimt_fwnode) + return -EPROBE_DEFER; + +- /* +- * EPROBE_DEFER ensures IOMMU is probed before the devices that +- * depend on them. During shutdown, however, the IOMMU may be removed +- * first, leading to issues. To avoid this, a device link is added +- * which enforces the correct removal order. +- */ +- device_link_add(dev, rimt_fwnode->dev, DL_FLAG_AUTOREMOVE_CONSUMER); + return acpi_iommu_fwspec_init(dev, deviceid, rimt_fwnode); + } + +diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c +index 6c324f9fdc53..09cc0432114a 100644 +--- a/drivers/iommu/riscv/iommu.c ++++ b/drivers/iommu/riscv/iommu.c +@@ -1387,6 +1387,13 @@ static struct iommu_device *riscv_iommu_probe_device(struct device *dev) + + dev_iommu_priv_set(dev, info); + ++ /* ++ * During shutdown, however, the IOMMU may be removed first, leading ++ * to issues. To avoid this, a device link is added which enforces ++ * the correct removal order. ++ */ ++ device_link_add(dev, fwspec->iommu_fwnode->dev, DL_FLAG_AUTOREMOVE_CONSUMER); ++ + return &iommu->iommu; + } + +-- +2.53.0 + diff --git a/SPECS/linux/0237-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch b/SPECS/linux/0237-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch deleted file mode 100644 index a141d36fdd..0000000000 --- a/SPECS/linux/0237-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 3f9c65918dfcf79c28e3c9592afc59b21e937026 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 14 May 2025 08:16:15 +0800 -Subject: [PATCH 237/269] REVYOS: riscv: dts: th1520: rename thead to xuantie - -Signed-off-by: Han Gao -[Icenowy: preserve the original compatible to allow Linux to match] -Signed-off-by: Icenowy Zheng ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index e44010810c07..f85d93227170 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -286,7 +286,7 @@ stmmac_axi_config: stmmac-axi-config { - }; - - aon: aon { -- compatible = "thead,th1520-aon"; -+ compatible = "xuantie,th1520-aon", "thead,th1520-aon"; - mboxes = <&mbox_910t 1>; - mbox-names = "aon"; - resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; --- -2.53.0 - diff --git a/SPECS/linux/0238-BACKPORT-FROMLIST-riscv-track-effective-hardware-PTE.patch b/SPECS/linux/0238-BACKPORT-FROMLIST-riscv-track-effective-hardware-PTE.patch new file mode 100644 index 0000000000..b712fe6564 --- /dev/null +++ b/SPECS/linux/0238-BACKPORT-FROMLIST-riscv-track-effective-hardware-PTE.patch @@ -0,0 +1,179 @@ +From 9e3fb106ed67ad88ddac6a1ba596a75b965efb34 Mon Sep 17 00:00:00 2001 +From: Yunhui Cui +Date: Fri, 22 May 2026 22:23:57 +0800 +Subject: [RUYI PATCH] BACKPORT: FROMLIST: riscv: track effective hardware PTE + A/D updates + +Track the effective hardware PTE A/D update mode separately from +Svadu capability discovery. When both Svade and Svadu are present, +enable SBI FWFT PTE A/D hardware updating on each online CPU via +CPUHP and use the resulting runtime state for arch_has_hw_pte_young(). +Fall back to software-managed A/D updates if enabling hardware updates +fails. + +When Svadu is present without Svade, assume hardware PTE A/D updating +is enabled from boot, and document that boot-time behavior in the DT +binding. + +Signed-off-by: Yunhui Cui +Reviewed-by: Qingwei Hu +Link: https://lore.kernel.org/r/20260522142358.87589-1-cuiyunhui@bytedance.com +[Han Gao: export riscv_hw_pte_ad_updating, it is referenced by the + arch_has_hw_pte_young() inline pulled into modules such as kvm.ko] +Signed-off-by: Han Gao +--- + .../devicetree/bindings/riscv/extensions.yaml | 6 +- + arch/riscv/include/asm/cpufeature.h | 6 ++ + arch/riscv/include/asm/pgtable.h | 8 +-- + arch/riscv/kernel/cpufeature.c | 59 +++++++++++++++++-- + 4 files changed, 66 insertions(+), 13 deletions(-) + +diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml +index c6ec9290fe07..58a3a67032ed 100644 +--- a/Documentation/devicetree/bindings/riscv/extensions.yaml ++++ b/Documentation/devicetree/bindings/riscv/extensions.yaml +@@ -277,10 +277,10 @@ properties: + of the PTE A/D bits or page faults when they need updated. + 2) Only Svade present in DT => Supervisor must assume Svade to be + always enabled. +- 3) Only Svadu present in DT => Supervisor must assume Svadu to be +- always enabled. ++ 3) Only Svadu present in DT => Supervisor must assume Svadu is ++ enabled at boot. + 4) Both Svade and Svadu present in DT => Supervisor must assume +- Svadu turned-off at boot time. To use Svadu, supervisor must ++ Svadu is disabled at boot time. To use Svadu, supervisor must + explicitly enable it using the SBI FWFT extension. + + - const: svadu +diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h +index 739fcc84bf7b..ad9fad6eee55 100644 +--- a/arch/riscv/include/asm/cpufeature.h ++++ b/arch/riscv/include/asm/cpufeature.h +@@ -128,6 +128,12 @@ struct riscv_isa_ext_data { + extern const struct riscv_isa_ext_data riscv_isa_ext[]; + extern const size_t riscv_isa_ext_count; + extern bool riscv_isa_fallback; ++DECLARE_STATIC_KEY_FALSE(riscv_hw_pte_ad_updating); ++ ++static __always_inline bool riscv_has_hw_pte_ad_updating(void) ++{ ++ return static_branch_unlikely(&riscv_hw_pte_ad_updating); ++} + + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); + static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext) +diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h +index 9c92a84e9755..103e8f92c326 100644 +--- a/arch/riscv/include/asm/pgtable.h ++++ b/arch/riscv/include/asm/pgtable.h +@@ -757,14 +757,14 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot) + #define pgprot_dmacoherent pgprot_writecombine + + /* +- * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By +- * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in +- * DT. ++ * Both Svade and Svadu control the hardware behavior when the PTE A/D bits ++ * need to be set. The core MM code only cares whether hardware updating of ++ * the accessed/dirty state is currently active. + */ + #define arch_has_hw_pte_young arch_has_hw_pte_young + static inline bool arch_has_hw_pte_young(void) + { +- return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); ++ return riscv_has_hw_pte_ad_updating(); + } + + /* +diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c +index 1734f9a4c2fd..7d3aee0e89f7 100644 +--- a/arch/riscv/kernel/cpufeature.c ++++ b/arch/riscv/kernel/cpufeature.c +@@ -35,6 +35,8 @@ + static bool any_cpu_has_zicboz; + static bool any_cpu_has_zicbop; + static bool any_cpu_has_zicbom; ++DEFINE_STATIC_KEY_FALSE(riscv_hw_pte_ad_updating); ++EXPORT_SYMBOL(riscv_hw_pte_ad_updating); + + unsigned long elf_hwcap __read_mostly; + +@@ -287,15 +289,60 @@ static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data, + return -EPROBE_DEFER; + } + +-static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data, +- const unsigned long *isa_bitmap) ++static void riscv_set_hw_pte_ad_updating(void) ++{ ++ static_branch_enable(&riscv_hw_pte_ad_updating); ++} ++ ++static int riscv_hw_pte_ad_updating_starting(unsigned int cpu) ++{ ++ int ret; ++ ++ ret = sbi_fwft_set(SBI_FWFT_PTE_AD_HW_UPDATING, 1, 0); ++ if (ret) { ++ if (ret != -EOPNOTSUPP) ++ pr_err("CPU%u failed to enable hardware PTE A/D updating: %d\n", ++ cpu, ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int __init riscv_hw_pte_ad_updating_init(void) + { +- /* SVADE has already been detected, use SVADE only */ +- if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE)) +- return -EOPNOTSUPP; ++ bool has_svade, has_svadu; ++ int state; + ++ has_svade = riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADE); ++ has_svadu = riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); ++ ++ if (!has_svadu) ++ return 0; ++ ++ if (!has_svade) ++ goto enable; ++ ++ state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, ++ "riscv/pte-ad:starting", ++ riscv_hw_pte_ad_updating_starting, ++ NULL); ++ if (state < 0) { ++ pr_info("riscv: leave PTE A/D updates software-managed (%d)\n", ++ state); ++ return 0; ++ } ++ ++ /* ++ * A successful CPUHP_AP_ONLINE_DYN registration means the startup ++ * callback has already succeeded on all online CPUs. ++ */ ++enable: ++ riscv_set_hw_pte_ad_updating(); ++ pr_debug("riscv: hardware PTE A/D updating enabled\n"); + return 0; + } ++arch_initcall(riscv_hw_pte_ad_updating_init); + + static int riscv_cfilp_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +@@ -584,7 +631,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { + __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts), + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), +- __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate), ++ __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), + __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), + __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), + __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), +-- +2.53.0 + diff --git a/SPECS/linux/0238-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch b/SPECS/linux/0238-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch deleted file mode 100644 index df363b51d3..0000000000 --- a/SPECS/linux/0238-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 6e4c1580c4a705aab8a07e0cd5c470eaee71dfbd Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Wed, 14 May 2025 08:27:18 +0800 -Subject: [PATCH 238/269] REVYOS: riscv: dts: th1520: add xuantie,th1520-mbox-r - -Signed-off-by: Han Gao -[Icenowy: remove the interrupt-controller property] -Signed-off-by: Icenowy Zheng ---- - arch/riscv/boot/dts/thead/th1520.dtsi | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi -index f85d93227170..ab681cf850d1 100644 ---- a/arch/riscv/boot/dts/thead/th1520.dtsi -+++ b/arch/riscv/boot/dts/thead/th1520.dtsi -@@ -292,6 +292,24 @@ aon: aon { - resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; - reset-names = "gpu-clkgen"; - #power-domain-cells = <1>; -+ opensbi-mboxes = <&mbox_910r>; -+ status = "okay"; -+ }; -+ -+ mbox_910r: mbox@ffefc53000 { -+ compatible = "xuantie,th1520-mbox-r"; -+ reg = <0xff 0xefc53000 0x0 0x4000>, -+ <0xff 0xefc3f000 0x0 0x1000>, -+ <0xff 0xefc47000 0x0 0x1000>, -+ <0xff 0xefc4f000 0x0 0x1000>; -+ reg-names = "local_base", -+ "remote_icu0", -+ "remote_icu1", -+ "remote_icu2"; -+ clocks = <&clk CLK_PERI_APB_PCLK>; -+ clock-names = "ipg"; -+ icu_cpu_id = <3>; -+ #mbox-cells = <2>; - }; - - soc { --- -2.53.0 - diff --git a/SPECS/linux/0239-BACKPORT-FROMLIST-riscv-preserve-hardware-updated-A-.patch b/SPECS/linux/0239-BACKPORT-FROMLIST-riscv-preserve-hardware-updated-A-.patch new file mode 100644 index 0000000000..e0e664ce5b --- /dev/null +++ b/SPECS/linux/0239-BACKPORT-FROMLIST-riscv-preserve-hardware-updated-A-.patch @@ -0,0 +1,166 @@ +From 891df3edf83ee7178551554dd9331c5ebb97367e Mon Sep 17 00:00:00 2001 +From: Yunhui Cui +Date: Fri, 22 May 2026 22:23:58 +0800 +Subject: [RUYI PATCH] BACKPORT: FROMLIST: riscv: preserve hardware-updated A/D + bits in PTE accessors + +Use cmpxchg-based merges for live RISC-V PTE permission updates so +software changes do not lose concurrently hardware-updated accessed and +dirty state. Cover ptep_set_access_flags(), +ptep_test_and_clear_young(), and ptep_set_wrprotect(), and extend the +same wrprotect handling to the PUD leaf helper used by huge mappings. + +Keep the existing Svvptc flush behaviour, but only flush when the +merged PTE value actually changed. + +Signed-off-by: Yunhui Cui +Reviewed-by: Qingwei Hu +Link: https://lore.kernel.org/r/20260522142358.87589-2-cuiyunhui@bytedance.com +[ Han Gao: ptep_test_and_clear_young returntype is int. It's adapted and fixed. ] +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/pgtable.h | 19 +++++++-- + arch/riscv/mm/pgtable.c | 68 ++++++++++++++++++++++++++------ + 2 files changed, 73 insertions(+), 14 deletions(-) + +diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h +index 103e8f92c326..8eb1ff060077 100644 +--- a/arch/riscv/include/asm/pgtable.h ++++ b/arch/riscv/include/asm/pgtable.h +@@ -693,15 +693,21 @@ static inline pte_t ptep_get_and_clear(struct mm_struct *mm, + static inline void ptep_set_wrprotect(struct mm_struct *mm, + unsigned long address, pte_t *ptep) + { +- pte_t read_pte = READ_ONCE(*ptep); ++ pte_t old_pte; ++ pte_t pte; + /* + * ptep_set_wrprotect can be called for shadow stack ranges too. + * shadow stack memory is XWR = 010 and thus clearing _PAGE_WRITE will lead to + * encoding 000b which is wrong encoding with V = 1. This should lead to page fault + * but we dont want this wrong configuration to be set in page tables. + */ +- atomic_long_set((atomic_long_t *)ptep, +- ((pte_val(read_pte) & ~(unsigned long)_PAGE_WRITE) | _PAGE_READ)); ++ pte = READ_ONCE(*ptep); ++ do { ++ old_pte = pte; ++ pte = pte_wrprotect(pte); ++ pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), pte_val(old_pte), ++ pte_val(pte)); ++ } while (pte_val(pte) != pte_val(old_pte)); + } + + #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH +@@ -1055,6 +1061,13 @@ static inline void pmdp_set_wrprotect(struct mm_struct *mm, + ptep_set_wrprotect(mm, address, (pte_t *)pmdp); + } + ++#define __HAVE_ARCH_PUDP_SET_WRPROTECT ++static inline void pudp_set_wrprotect(struct mm_struct *mm, ++ unsigned long address, pud_t *pudp) ++{ ++ ptep_set_wrprotect(mm, address, (pte_t *)pudp); ++} ++ + #define pmdp_establish pmdp_establish + static inline pmd_t pmdp_establish(struct vm_area_struct *vma, + unsigned long address, pmd_t *pmdp, pmd_t pmd) +diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c +index b1ed2f14dc3a..bf16581872e6 100644 +--- a/arch/riscv/mm/pgtable.c ++++ b/arch/riscv/mm/pgtable.c +@@ -5,23 +5,55 @@ + #include + #include + ++#define RISCV_PTE_ACCESS_FLAG_MASK (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC | \ ++ _PAGE_ACCESSED | _PAGE_DIRTY | \ ++ _PAGE_SOFT_DIRTY) ++ ++static inline unsigned long riscv_pte_access_flags(unsigned long cur, ++ unsigned long entry) ++{ ++ unsigned long pteval; ++ unsigned long hw_flags; ++ ++ hw_flags = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_SOFT_DIRTY; ++ pteval = cur & ~RISCV_PTE_ACCESS_FLAG_MASK; ++ pteval |= entry & (RISCV_PTE_ACCESS_FLAG_MASK & ~hw_flags); ++ pteval |= (cur | entry) & hw_flags; ++ ++ return pteval; ++} ++ + int ptep_set_access_flags(struct vm_area_struct *vma, + unsigned long address, pte_t *ptep, + pte_t entry, int dirty) + { ++ unsigned long old_pteval; ++ unsigned long new_pteval; ++ unsigned long prev_pteval; ++ bool changed; ++ ++ old_pteval = pte_val(ptep_get(ptep)); ++ do { ++ new_pteval = riscv_pte_access_flags(old_pteval, pte_val(entry)); ++ if (new_pteval == old_pteval) ++ break; ++ ++ prev_pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, ++ new_pteval); ++ if (prev_pteval == old_pteval) ++ break; ++ ++ old_pteval = prev_pteval; ++ } while (1); ++ ++ changed = old_pteval != new_pteval; + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVVPTC)) { +- if (!pte_same(ptep_get(ptep), entry)) { +- __set_pte_at(vma->vm_mm, ptep, entry); +- /* Here only not svadu is impacted */ ++ if (changed) + flush_tlb_page(vma, address); +- return true; +- } + +- return false; ++ return changed; + } + +- if (!pte_same(ptep_get(ptep), entry)) +- __set_pte_at(vma->vm_mm, ptep, entry); + /* + * update_mmu_cache will unconditionally execute, handling both + * the case that the PTE changed and the spurious fault case. +@@ -33,9 +65,23 @@ int ptep_test_and_clear_young(struct vm_area_struct *vma, + unsigned long address, + pte_t *ptep) + { +- if (!pte_young(ptep_get(ptep))) +- return 0; +- return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep)); ++ unsigned long old_pteval; ++ unsigned long new_pteval; ++ unsigned long prev_pteval; ++ ++ old_pteval = pte_val(ptep_get(ptep)); ++ do { ++ if (!(old_pteval & _PAGE_ACCESSED)) ++ return 0; ++ ++ new_pteval = pte_val(pte_mkold(__pte(old_pteval))); ++ prev_pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, ++ new_pteval); ++ if (prev_pteval == old_pteval) ++ return 1; ++ ++ old_pteval = prev_pteval; ++ } while (1); + } + EXPORT_SYMBOL_GPL(ptep_test_and_clear_young); + +-- +2.53.0 + diff --git a/SPECS/linux/0239-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch b/SPECS/linux/0239-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch deleted file mode 100644 index 3748901d56..0000000000 --- a/SPECS/linux/0239-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch +++ /dev/null @@ -1,85 +0,0 @@ -From e93f76cc546e5d62bfec229436d623b936f1308d Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 19 Nov 2023 21:13:31 +0800 -Subject: [PATCH 239/269] SOPHGO: dt-bindings: nvmem: Add SG2044 eFuse - controller - -Sophgo SG2044 uses eFuses used to store factory-programmed data -such as ROM patch, public keys and other factory information. - -Signed-off-by: Inochi Amaoto ---- - .../bindings/nvmem/sophgo,efuse.yaml | 61 +++++++++++++++++++ - 1 file changed, 61 insertions(+) - create mode 100644 Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml - -diff --git a/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml -new file mode 100644 -index 000000000000..d4bffe2724ac ---- /dev/null -+++ b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml -@@ -0,0 +1,61 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/nvmem/sophgo,efuse.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Sophgo SoC eFuse-based NVMEM -+ -+description: -+ Sophgo SoCs contain factory-programmed eFuses used to store ROM patch, -+ public key and other factory information. -+ -+maintainers: -+ - Inochi Amaoto -+ -+allOf: -+ - $ref: nvmem.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - sophgo,sg2044-efuse -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 1 -+ items: -+ - description: Core clock -+ - description: APB clock -+ -+ clock-names: -+ minItems: 1 -+ items: -+ - const: core -+ - const: apb -+ -+ resets: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ efuse@40000000 { -+ compatible = "sophgo,sg2044-efuse"; -+ reg = <0x40000000 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&clk 0>, -+ <&clk 1>; -+ clock-names = "core", "apb"; -+ }; -+ -+... --- -2.53.0 - diff --git a/SPECS/linux/0240-FROMLIST-riscv-mm-Avoid-spurious-fault-after-hotplug.patch b/SPECS/linux/0240-FROMLIST-riscv-mm-Avoid-spurious-fault-after-hotplug.patch new file mode 100644 index 0000000000..d3488fd3de --- /dev/null +++ b/SPECS/linux/0240-FROMLIST-riscv-mm-Avoid-spurious-fault-after-hotplug.patch @@ -0,0 +1,90 @@ +From 785e5d317ad81e175bf70fdeb7630cdf576cc7f3 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Fri, 5 Jun 2026 13:23:22 +0800 +Subject: [RUYI PATCH] FROMLIST: riscv: mm: Avoid spurious fault after + hotplugging vmemmap + +section_activate() does not flush TLB after populating new vmemmap +pages. On most architectures, this is okay. However it is a problem on +RISC-V since there the TLB caching non-present entries is permitted, +which causes spurious faults on some hardwares. + +This seems to be most easily reproduced with DEBUG_VM=y and +PAGE_POISONING=y, which causes these newly mapped struct pages to be +poisoned i.e. written to immediately after mapping. + +Add a hook vmemmap_populate_finalize() in __populate_section_memmap() +after population, to allow architectures to handle such situations as +needed. Then implement it on RISC-V to arrange for the existing +exception handler code to deal with these faults if they happen. + +Signed-off-by: Vivian Wang +Link: https://lore.kernel.org/r/20260605-mark-after-vmemmap-populate-v3-1-a06001ac9264@iscas.ac.cn +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/pgtable.h | 4 ++++ + arch/riscv/mm/init.c | 6 ++++++ + mm/sparse-vmemmap.c | 8 ++++++++ + 3 files changed, 18 insertions(+) + +diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h +index 8eb1ff060077..1291c56eedc7 100644 +--- a/arch/riscv/include/asm/pgtable.h ++++ b/arch/riscv/include/asm/pgtable.h +@@ -1281,6 +1281,10 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte) + #define TASK_SIZE FIXADDR_START + #endif + ++/* Needed on SPARSEMEM_VMEMMAP */ ++#define vmemmap_populate_finalize vmemmap_populate_finalize ++void __meminit vmemmap_populate_finalize(void); ++ + #else /* CONFIG_MMU */ + + #define PAGE_SHARED __pgprot(0) +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index cf4f3ec1cca5..8babe9a8e954 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -1494,6 +1494,12 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node, + */ + return vmemmap_populate_hugepages(start, end, node, altmap); + } ++ ++void __meminit vmemmap_populate_finalize(void) ++{ ++ /* Avoid faults on cached non-present TLB entries. */ ++ mark_new_valid_map(); ++} + #endif + + #if defined(CONFIG_MMU) && defined(CONFIG_64BIT) +diff --git a/mm/sparse-vmemmap.c b/mm/sparse-vmemmap.c +index 37522d6cb398..b0a3decd1eb0 100644 +--- a/mm/sparse-vmemmap.c ++++ b/mm/sparse-vmemmap.c +@@ -558,6 +558,12 @@ static int __meminit vmemmap_populate_compound_pages(unsigned long start_pfn, + + #endif + ++#ifndef vmemmap_populate_finalize ++static void __meminit vmemmap_populate_finalize(void) ++{ ++} ++#endif ++ + struct page * __meminit __populate_section_memmap(unsigned long pfn, + unsigned long nr_pages, int nid, struct vmem_altmap *altmap, + struct dev_pagemap *pgmap) +@@ -578,6 +584,8 @@ struct page * __meminit __populate_section_memmap(unsigned long pfn, + if (r < 0) + return NULL; + ++ vmemmap_populate_finalize(); ++ + return pfn_to_page(pfn); + } + +-- +2.53.0 + diff --git a/SPECS/linux/0240-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch b/SPECS/linux/0240-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch deleted file mode 100644 index 2199d29bc5..0000000000 --- a/SPECS/linux/0240-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 5bd33517c145b1fce4aaff62caafb2afe8388bed Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Sun, 19 Nov 2023 21:13:32 +0800 -Subject: [PATCH 240/269] SOPHGO: nvmem: Add Sophgo SG2044 eFuse driver - -Sophgo SoCs such as SG2044 contain eFuses used to store -factory-programmed data. - -As for SG2044, HW automatically loads the eFuse content -into shadow registers which are organized as 32bit values -exposed as MMIO. - -Signed-off-by: Inochi Amaoto ---- - drivers/nvmem/Kconfig | 12 +++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/sophgo-efuse.c | 176 +++++++++++++++++++++++++++++++++++ - 3 files changed, 190 insertions(+) - create mode 100644 drivers/nvmem/sophgo-efuse.c - -diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig -index 74ddbd0f79b0..13bf77710300 100644 ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -365,6 +365,18 @@ config NVMEM_SNVS_LPGPR - This driver can also be built as a module. If so, the module - will be called nvmem-snvs-lpgpr. - -+config NVMEM_SOPHGO_EFUSE -+ tristate "Sophgo eFuse support" -+ depends on ARCH_SOPHGO || COMPILE_TEST -+ default ARCH_SOPHGO -+ help -+ Say y here to enable support for reading eFuses on Sophgo SoCs -+ such as the CV1800B. These are e.g. used to store factory programmed -+ calibration data required for the builtin ethernet PHY. -+ -+ This driver can also be built as a module. If so, the module will -+ be called nvmem-sophgo-efuse. -+ - config NVMEM_SPMI_SDAM - tristate "SPMI SDAM Support" - depends on SPMI -diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile -index 7252b8ec88d4..eac52240a161 100644 ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -72,6 +72,8 @@ obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o - nvmem-sc27xx-efuse-y := sc27xx-efuse.o - obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o - nvmem_snvs_lpgpr-y := snvs_lpgpr.o -+obj-$(CONFIG_NVMEM_SOPHGO_EFUSE) += nvmem-sophgo-efuse.o -+nvmem-sophgo-efuse-y := sophgo-efuse.o - obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o - nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o - obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o -diff --git a/drivers/nvmem/sophgo-efuse.c b/drivers/nvmem/sophgo-efuse.c -new file mode 100644 -index 000000000000..5f90adaf8e4f ---- /dev/null -+++ b/drivers/nvmem/sophgo-efuse.c -@@ -0,0 +1,176 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Sophgo SoC eFuse driver -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define SG2044_EFUSE_CONTENT_SIZE 0x400 -+ -+#define SG2044_EFUSE_MD 0x000 -+#define SG2044_EFUSE_ADR 0x004 -+#define SG2044_EFUSE_RD_DATA 0x00c -+ -+#define SG2044_EFUSE_MODE GENMASK(1, 0) -+#define SG2044_EFUSE_MODE_READ 2 -+ -+#define SG2044_EFUSE_BOOT_DONE BIT(7) -+#define SG2044_BOOT_TIMEOUT 10000 -+ -+#define SG2044_EFUSE_ADR_ADDR GENMASK(7, 0) -+ -+#define SG2044_EFUSE_ALIGN 4 -+ -+struct sophgo_efuses { -+ void __iomem *base; -+ struct clk_bulk_data *clks; -+ int num_clks; -+ struct mutex mutex; -+}; -+ -+static int sg2044_efuse_wait_mode(struct sophgo_efuses *efuse) -+{ -+ u32 value; -+ -+ return readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, -+ FIELD_GET(SG2044_EFUSE_MODE, value) == 0, -+ 1, SG2044_BOOT_TIMEOUT); -+} -+ -+static int sg2044_efuse_set_mode(struct sophgo_efuses *efuse, int mode) -+{ -+ u32 val = readl(efuse->base + SG2044_EFUSE_MD); -+ -+ val &= ~SG2044_EFUSE_MODE; -+ val |= FIELD_PREP(SG2044_EFUSE_MODE, mode); -+ -+ writel(val, efuse->base + SG2044_EFUSE_MD); -+ -+ return sg2044_efuse_wait_mode(efuse); -+} -+ -+static u32 sg2044_efuses_read_strip(struct sophgo_efuses *efuse, -+ unsigned int offset, u32 *strip) -+{ -+ u32 val = FIELD_PREP(SG2044_EFUSE_ADR_ADDR, offset); -+ int ret; -+ -+ guard(mutex)(&efuse->mutex); -+ -+ writel(val, efuse->base + SG2044_EFUSE_ADR); -+ -+ ret = sg2044_efuse_set_mode(efuse, SG2044_EFUSE_MODE_READ); -+ if (ret < 0) -+ return ret; -+ -+ *strip = readl(efuse->base + SG2044_EFUSE_RD_DATA); -+ -+ return 0; -+} -+ -+static int sg2044_efuses_read(void *context, unsigned int offset, void *val, -+ size_t bytes) -+{ -+ struct sophgo_efuses *efuse = context; -+ unsigned int start, start_offset, end, i; -+ u32 value; -+ u8 *buf; -+ int ret; -+ -+ start = rounddown(offset, SG2044_EFUSE_ALIGN); -+ end = roundup(offset + bytes, SG2044_EFUSE_ALIGN); -+ start_offset = offset - start; -+ -+ start /= SG2044_EFUSE_ALIGN; -+ end /= SG2044_EFUSE_ALIGN; -+ -+ ret = readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, -+ (value & SG2044_EFUSE_BOOT_DONE), -+ 1, SG2044_BOOT_TIMEOUT); -+ if (ret < 0) -+ return ret; -+ -+ buf = kzalloc(end - start, GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ for (i = start; i < end; i++) { -+ ret = sg2044_efuses_read_strip(efuse, i, &value); -+ if (ret) -+ goto failed; -+ -+ memcpy(&buf[(i - start) * 4], &value, SG2044_EFUSE_ALIGN); -+ } -+ -+ memcpy(val, buf + start_offset, bytes); -+ -+failed: -+ kfree(buf); -+ -+ return ret; -+} -+ -+static int sophgo_efuses_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct sophgo_efuses *efuse; -+ struct nvmem_config config = { -+ .dev = &pdev->dev, -+ .add_legacy_fixed_of_cells = true, -+ .read_only = true, -+ .reg_read = sg2044_efuses_read, -+ .stride = 1, -+ .word_size = 1, -+ .name = "sophgo-efuse", -+ .id = NVMEM_DEVID_AUTO, -+ .root_only = true, -+ }; -+ -+ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); -+ if (!efuse) -+ return -ENOMEM; -+ -+ efuse->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(efuse->base)) -+ return PTR_ERR(efuse->base); -+ -+ efuse->num_clks = devm_clk_bulk_get_all_enabled(&pdev->dev, &efuse->clks); -+ if (efuse->num_clks < 0) -+ return dev_err_probe(dev, efuse->num_clks, "failed to get clocks\n"); -+ -+ config.priv = efuse; -+ config.size = SG2044_EFUSE_CONTENT_SIZE; -+ -+ return PTR_ERR_OR_ZERO(devm_nvmem_register(config.dev, &config)); -+} -+ -+static const struct of_device_id sophgo_efuses_of_match[] = { -+ { .compatible = "sophgo,sg2044-efuse", }, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(of, sophgo_efuses_of_match); -+ -+static struct platform_driver sophgo_efuses_driver = { -+ .driver = { -+ .name = "sophgo_efuse", -+ .of_match_table = sophgo_efuses_of_match, -+ }, -+ .probe = sophgo_efuses_probe, -+}; -+ -+module_platform_driver(sophgo_efuses_driver); -+ -+MODULE_AUTHOR("Inochi Amaoto "); -+MODULE_DESCRIPTION("Sophgo efuse driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux/0241-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch b/SPECS/linux/0241-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch deleted file mode 100644 index 6ea010222c..0000000000 --- a/SPECS/linux/0241-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 874f4862e7b9202630c2b204a204128293dab814 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Thu, 5 Dec 2024 13:24:13 +0800 -Subject: [PATCH 241/269] SOPHGO: riscv: dts: sophgo: sg2044: Add eFUSE device - -Add eFUSE controller node for SG2044. - -Signed-off-by: Inochi Amaoto ---- - arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ - arch/riscv/boot/dts/sophgo/sg2044.dtsi | 12 ++++++++++++ - 2 files changed, 16 insertions(+) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -index fed3d9a384a0..1b506972d465 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts -@@ -36,6 +36,10 @@ &emmc { - status = "okay"; - }; - -+&efuse0 { -+ status = "okay"; -+}; -+ - &gmac0 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; -diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -index 320c4d1d08e6..9577aae08f7f 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -@@ -408,6 +408,18 @@ sd: mmc@703000b000 { - status = "disabled"; - }; - -+ efuse0: efuse@7040000000 { -+ compatible = "sophgo,sg2044-efuse"; -+ reg = <0x70 0x40000000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ clocks = <&clk CLK_GATE_EFUSE>, -+ <&clk CLK_GATE_APB_EFUSE>; -+ clock-names = "core", "apb"; -+ resets = <&rst RST_EFUSE0>; -+ status = "disabled"; -+ }; -+ - i2c0: i2c@7040005000 { - compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; - reg = <0x70 0x40005000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux/0241-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch b/SPECS/linux/0241-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch new file mode 100644 index 0000000000..7904205dd4 --- /dev/null +++ b/SPECS/linux/0241-XUANTIE-riscv-dts-th1520-add-licheepi4a-16g-support.patch @@ -0,0 +1,49 @@ +From 6b4d0ea6ea00cef4338cd548642d0b495569ff84 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Mon, 24 Nov 2025 20:38:44 +0800 +Subject: [RUYI PATCH] XUANTIE: riscv: dts: th1520: add licheepi4a 16g support + +From: https://github.com/revyos/th1520-linux-kernel/commit/01a510898e41e704bee1fe58a2c0c0a29cb96548 + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/thead/Makefile | 1 + + .../boot/dts/thead/th1520-lichee-pi-4a-16g.dts | 18 ++++++++++++++++++ + 2 files changed, 19 insertions(+) + create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts + +diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile +index b55a17127c2b..281849e71ccb 100644 +--- a/arch/riscv/boot/dts/thead/Makefile ++++ b/arch/riscv/boot/dts/thead/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb ++dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a-16g.dtb +diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts +new file mode 100644 +index 000000000000..a3a991baf716 +--- /dev/null ++++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts +@@ -0,0 +1,18 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/* ++ * Copyright (C) 2023 Han Gao ++ */ ++ ++/dts-v1/; ++ ++#include "th1520-lichee-pi-4a.dts" ++ ++/ { ++ model = "Sipeed Lichee Pi 4A 16G"; ++ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x00000000 0x4 0x00000000>; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux/0242-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch b/SPECS/linux/0242-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch new file mode 100644 index 0000000000..ae384135d4 --- /dev/null +++ b/SPECS/linux/0242-REVYOS-riscv-dts-th1520-rename-thead-to-xuantie.patch @@ -0,0 +1,28 @@ +From f3f3f3e762444ed79f5851fd1d4439966a7cf378 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 14 May 2025 08:16:15 +0800 +Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: rename thead to xuantie + +Signed-off-by: Han Gao +[Icenowy: preserve the original compatible to allow Linux to match] +Signed-off-by: Icenowy Zheng +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index e44010810c07..f85d93227170 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -286,7 +286,7 @@ stmmac_axi_config: stmmac-axi-config { + }; + + aon: aon { +- compatible = "thead,th1520-aon"; ++ compatible = "xuantie,th1520-aon", "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; +-- +2.53.0 + diff --git a/SPECS/linux/0242-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch b/SPECS/linux/0242-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch deleted file mode 100644 index 510315903f..0000000000 --- a/SPECS/linux/0242-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 82f7e6cd5cc32f57ec9a2aefcb646e7d4d89a881 Mon Sep 17 00:00:00 2001 -From: Xiaoguang Xing -Date: Mon, 22 Jan 2024 10:31:30 +0800 -Subject: [PATCH 242/269] SOPHGO: riscv: sg2042: errata: Replace thead cache - clean with flush - -FROM: https://github.com/sophgo/linux-riscv/commit/9f8fdd99aae6ae8f037ad9c80b968de7c4252a65 - -Signed-off-by: Xiaoguang Xing -Signed-off-by: Han Gao ---- - arch/riscv/errata/thead/errata.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c -index fbe46f2fa8fb..9be8c45f4531 100644 ---- a/arch/riscv/errata/thead/errata.c -+++ b/arch/riscv/errata/thead/errata.c -@@ -67,7 +67,7 @@ static bool errata_probe_mae(unsigned int stage, - * 0000000 11001 00000 000 00000 0001011 - */ - #define THEAD_INVAL_A0 ".long 0x02a5000b" --#define THEAD_CLEAN_A0 ".long 0x0295000b" -+#define THEAD_CLEAN_A0 ".long 0x02b5000b" - #define THEAD_FLUSH_A0 ".long 0x02b5000b" - #define THEAD_SYNC_S ".long 0x0190000b" - --- -2.53.0 - diff --git a/SPECS/linux/0243-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch b/SPECS/linux/0243-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch new file mode 100644 index 0000000000..6e6a06b8e1 --- /dev/null +++ b/SPECS/linux/0243-REVYOS-riscv-dts-th1520-add-xuantie-th1520-mbox-r.patch @@ -0,0 +1,44 @@ +From 88a0182dc6a887d56814a6c0edb154af96622dbe Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Wed, 14 May 2025 08:27:18 +0800 +Subject: [RUYI PATCH] REVYOS: riscv: dts: th1520: add xuantie,th1520-mbox-r + +Signed-off-by: Han Gao +[Icenowy: remove the interrupt-controller property] +Signed-off-by: Icenowy Zheng +--- + arch/riscv/boot/dts/thead/th1520.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi +index f85d93227170..ab681cf850d1 100644 +--- a/arch/riscv/boot/dts/thead/th1520.dtsi ++++ b/arch/riscv/boot/dts/thead/th1520.dtsi +@@ -292,6 +292,24 @@ aon: aon { + resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; + reset-names = "gpu-clkgen"; + #power-domain-cells = <1>; ++ opensbi-mboxes = <&mbox_910r>; ++ status = "okay"; ++ }; ++ ++ mbox_910r: mbox@ffefc53000 { ++ compatible = "xuantie,th1520-mbox-r"; ++ reg = <0xff 0xefc53000 0x0 0x4000>, ++ <0xff 0xefc3f000 0x0 0x1000>, ++ <0xff 0xefc47000 0x0 0x1000>, ++ <0xff 0xefc4f000 0x0 0x1000>; ++ reg-names = "local_base", ++ "remote_icu0", ++ "remote_icu1", ++ "remote_icu2"; ++ clocks = <&clk CLK_PERI_APB_PCLK>; ++ clock-names = "ipg"; ++ icu_cpu_id = <3>; ++ #mbox-cells = <2>; + }; + + soc { +-- +2.53.0 + diff --git a/SPECS/linux/0243-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch b/SPECS/linux/0243-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch deleted file mode 100644 index 72c2bd2012..0000000000 --- a/SPECS/linux/0243-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch +++ /dev/null @@ -1,102 +0,0 @@ -From bdb7ddbbede3c0210447148b44b1dd83137715fa Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Sun, 28 Dec 2025 23:02:15 +0800 -Subject: [PATCH 243/269] SOPHGO: dts: sg2044: Modify pcie bar address - -FROM: https://github.com/sophgo/linux-riscv/commit/efddc3e2d3d57b27054415afb522100e6dce8692 - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/sophgo/sg2044.dtsi | 28 +++++++++++++------------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -index 9577aae08f7f..f1377ee8e149 100644 ---- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi -+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi -@@ -36,7 +36,7 @@ pcie0: pcie@6c00000000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x00000000 0x0 0x00001000>, - <0x6c 0x00300000 0x0 0x00004000>, -- <0x48 0x00000000 0x0 0x00001000>, -+ <0x50 0x00000000 0x0 0x00001000>, - <0x6c 0x000c0000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -51,11 +51,11 @@ pcie0: pcie@6c00000000 { - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, - <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, -- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, -- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x54 0x00000000 0x54 0x00000000 0x4 0x00000000>, -+ <0x03000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>; - status = "disabled"; - - pcie_intc0: interrupt-controller { -@@ -89,8 +89,8 @@ pcie1: pcie@6c00400000 { - ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>, - <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>, -- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, -- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x44 0x00000000 0x44 0x00000000 0x4 0x00000000>, -+ <0x03000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>; - status = "disabled"; - - pcie_intc1: interrupt-controller { -@@ -106,7 +106,7 @@ pcie2: pcie@6c04000000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x04000000 0x0 0x00001000>, - <0x6c 0x04300000 0x0 0x00004000>, -- <0x58 0x00000000 0x0 0x00001000>, -+ <0x7c 0x00000000 0x0 0x00001000>, - <0x6c 0x040c0000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -121,11 +121,11 @@ pcie2: pcie@6c04000000 { - <0 0 0 3 &pcie_intc2 2>, - <0 0 0 4 &pcie_intc2 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x7c 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>, - <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>, -- <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>, -- <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x7d 0x00000000 0x7d 0x00000000 0x1 0x00000000>, -+ <0x03000000 0x7c 0x80000000 0x7c 0x80000000 0x0 0x80000000>; - status = "disabled"; - - pcie_intc2: interrupt-controller { -@@ -141,7 +141,7 @@ pcie3: pcie@6c04400000 { - compatible = "sophgo,sg2044-pcie"; - reg = <0x6c 0x04400000 0x0 0x00001000>, - <0x6c 0x04700000 0x0 0x00004000>, -- <0x50 0x00000000 0x0 0x00001000>, -+ <0x78 0x00000000 0x0 0x00001000>, - <0x6c 0x04780000 0x0 0x00001000>; - reg-names = "dbi", "atu", "config", "app"; - #address-cells = <3>; -@@ -156,11 +156,11 @@ pcie3: pcie@6c04400000 { - <0 0 0 3 &pcie_intc3 2>, - <0 0 0 4 &pcie_intc3 3>; - msi-parent = <&msi>; -- ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, -+ ranges = <0x01000000 0x0 0x00000000 0x78 0x10000000 0x0 0x00200000>, - <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>, - <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>, -- <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>, -- <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>; -+ <0x43000000 0x79 0x00000000 0x79 0x00000000 0x1 0x00000000>, -+ <0x03000000 0x78 0x80000000 0x78 0x80000000 0x0 0x80000000>; - status = "disabled"; - - pcie_intc3: interrupt-controller { --- -2.53.0 - diff --git a/SPECS/linux/0244-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch b/SPECS/linux/0244-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch deleted file mode 100644 index 9026e93aa5..0000000000 --- a/SPECS/linux/0244-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 1cb8355f79c2c3fcc46009a3b36f85dcb74c2298 Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Fri, 24 Oct 2025 15:59:17 +0800 -Subject: [PATCH 244/269] REVYSR: dt-bindings: net: ultrarisc,dp1000-gmac: Add - support for Ultrarisc DP1000 GMAC - -The GMAC IP on DP1000 is a standard Synopsys DesignWare MAC -(version 5.10a). - -Add necessary compatible string for this device. - -Signed-off-by: Han Gao -Signed-off-by: Han Gao -FROM: https://github.com/RevySR/linux/commit/5eda7fb5c988909f44edab38678cd124a9a5b98f -Signed-off-by: Han Gao ---- - .../devicetree/bindings/net/snps,dwmac.yaml | 1 + - .../bindings/net/ultrarisc,dp1000-gmac.yaml | 89 +++++++++++++++++++ - 2 files changed, 90 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml - -diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -index 98ebb6276bc6..44ea20deb863 100644 ---- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml -+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -@@ -118,6 +118,7 @@ properties: - - starfive,jh7110-dwmac - - tesla,fsd-ethqos - - thead,th1520-gmac -+ - ultrarisc,dp1000-gmac - - reg: - minItems: 1 -diff --git a/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml -new file mode 100644 -index 000000000000..ace5c4058cc9 ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml -@@ -0,0 +1,89 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/ultrarisc,dp1000-gmac.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Ultrarisc dp1000 glue layer -+ -+maintainers: -+ - Han Gao -+ -+select: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - ultrarisc,dp1000-gmac -+ required: -+ - compatible -+ -+properties: -+ compatible: -+ oneOf: -+ - items: -+ - const: ultrarisc,dp1000-gmac -+ - const: snps,dwmac-5.10a -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ items: -+ - description: GMAC main clock -+ - description: PTP clock -+ - description: TX clock -+ -+ clock-names: -+ items: -+ - const: stmmaceth -+ -+ dma-noncoherent: true -+ -+ interrupts: -+ maxItems: 1 -+ -+ interrupt-names: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - interrupt-names -+ -+allOf: -+ - $ref: snps,dwmac.yaml# -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ -+ ethernet1@38000000 { -+ clocks = <&csr_clk>; -+ clock-names = "stmmaceth"; -+ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; -+ interrupt-parent = <0x01>; -+ interrupts = <84>; -+ interrupt-names = "macirq"; -+ reg = <0x00 0x38000000 0x00 0x1000000>; -+ local-mac-address = [ff ff ff ff ff ff]; -+ phy-mode = "rgmii"; -+ max-speed = <1000>; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ phy-handle = <&phy0>; -+ mdio { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ compatible = "snps,dwmac-mdio"; -+ phy0: phy@0{ -+ reg = <0x00>; -+ status = "okay"; -+ }; -+ }; -+ }; --- -2.53.0 - diff --git a/SPECS/linux/0244-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch b/SPECS/linux/0244-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch new file mode 100644 index 0000000000..d94ffceb57 --- /dev/null +++ b/SPECS/linux/0244-SOPHGO-dt-bindings-nvmem-Add-SG2044-eFuse-controller.patch @@ -0,0 +1,84 @@ +From 828788cb6576613b13a5eb56a7b0abfba48756a1 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 19 Nov 2023 21:13:31 +0800 +Subject: [RUYI PATCH] SOPHGO: dt-bindings: nvmem: Add SG2044 eFuse controller + +Sophgo SG2044 uses eFuses used to store factory-programmed data +such as ROM patch, public keys and other factory information. + +Signed-off-by: Inochi Amaoto +--- + .../bindings/nvmem/sophgo,efuse.yaml | 61 +++++++++++++++++++ + 1 file changed, 61 insertions(+) + create mode 100644 Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml + +diff --git a/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml +new file mode 100644 +index 000000000000..d4bffe2724ac +--- /dev/null ++++ b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml +@@ -0,0 +1,61 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/nvmem/sophgo,efuse.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Sophgo SoC eFuse-based NVMEM ++ ++description: ++ Sophgo SoCs contain factory-programmed eFuses used to store ROM patch, ++ public key and other factory information. ++ ++maintainers: ++ - Inochi Amaoto ++ ++allOf: ++ - $ref: nvmem.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - sophgo,sg2044-efuse ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 1 ++ items: ++ - description: Core clock ++ - description: APB clock ++ ++ clock-names: ++ minItems: 1 ++ items: ++ - const: core ++ - const: apb ++ ++ resets: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ efuse@40000000 { ++ compatible = "sophgo,sg2044-efuse"; ++ reg = <0x40000000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&clk 0>, ++ <&clk 1>; ++ clock-names = "core", "apb"; ++ }; ++ ++... +-- +2.53.0 + diff --git a/SPECS/linux/0245-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch b/SPECS/linux/0245-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch deleted file mode 100644 index 290dc385e0..0000000000 --- a/SPECS/linux/0245-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch +++ /dev/null @@ -1,27 +0,0 @@ -From a2601d5e354f0a2f491a4b8fbe6b07741ece8aee Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Fri, 24 Oct 2025 17:00:37 +0800 -Subject: [PATCH 245/269] REVYSR: net: stmmac: add support for dwmac 5.10a - -Signed-off-by: Han Gao -FROM: https://github.com/RevySR/linux/commit/5bc2d2af06ccd13675b8d4751226fb56bc8ee6df -Signed-off-by: Han Gao ---- - drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -index b9218c07eb6b..a27b2bc177af 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -@@ -59,6 +59,7 @@ static const struct of_device_id dwmac_generic_match[] = { - { .compatible = "snps,dwmac-3.72a"}, - { .compatible = "snps,dwmac-4.00"}, - { .compatible = "snps,dwmac-4.10a"}, -+ { .compatible = "snps,dwmac-5.10a"}, - { .compatible = "snps,dwmac"}, - { .compatible = "snps,dwxgmac-2.10"}, - { .compatible = "snps,dwxgmac"}, --- -2.53.0 - diff --git a/SPECS/linux/0245-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch b/SPECS/linux/0245-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch new file mode 100644 index 0000000000..c8c983a317 --- /dev/null +++ b/SPECS/linux/0245-SOPHGO-nvmem-Add-Sophgo-SG2044-eFuse-driver.patch @@ -0,0 +1,241 @@ +From 8f115dda9e54d6df037b9bd126a5ce21c977de04 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Sun, 19 Nov 2023 21:13:32 +0800 +Subject: [RUYI PATCH] SOPHGO: nvmem: Add Sophgo SG2044 eFuse driver + +Sophgo SoCs such as SG2044 contain eFuses used to store +factory-programmed data. + +As for SG2044, HW automatically loads the eFuse content +into shadow registers which are organized as 32bit values +exposed as MMIO. + +Signed-off-by: Inochi Amaoto +--- + drivers/nvmem/Kconfig | 12 +++ + drivers/nvmem/Makefile | 2 + + drivers/nvmem/sophgo-efuse.c | 176 +++++++++++++++++++++++++++++++++++ + 3 files changed, 190 insertions(+) + create mode 100644 drivers/nvmem/sophgo-efuse.c + +diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig +index 74ddbd0f79b0..13bf77710300 100644 +--- a/drivers/nvmem/Kconfig ++++ b/drivers/nvmem/Kconfig +@@ -365,6 +365,18 @@ config NVMEM_SNVS_LPGPR + This driver can also be built as a module. If so, the module + will be called nvmem-snvs-lpgpr. + ++config NVMEM_SOPHGO_EFUSE ++ tristate "Sophgo eFuse support" ++ depends on ARCH_SOPHGO || COMPILE_TEST ++ default ARCH_SOPHGO ++ help ++ Say y here to enable support for reading eFuses on Sophgo SoCs ++ such as the CV1800B. These are e.g. used to store factory programmed ++ calibration data required for the builtin ethernet PHY. ++ ++ This driver can also be built as a module. If so, the module will ++ be called nvmem-sophgo-efuse. ++ + config NVMEM_SPMI_SDAM + tristate "SPMI SDAM Support" + depends on SPMI +diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile +index 7252b8ec88d4..eac52240a161 100644 +--- a/drivers/nvmem/Makefile ++++ b/drivers/nvmem/Makefile +@@ -72,6 +72,8 @@ obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o + nvmem-sc27xx-efuse-y := sc27xx-efuse.o + obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o + nvmem_snvs_lpgpr-y := snvs_lpgpr.o ++obj-$(CONFIG_NVMEM_SOPHGO_EFUSE) += nvmem-sophgo-efuse.o ++nvmem-sophgo-efuse-y := sophgo-efuse.o + obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o + nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o + obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o +diff --git a/drivers/nvmem/sophgo-efuse.c b/drivers/nvmem/sophgo-efuse.c +new file mode 100644 +index 000000000000..5f90adaf8e4f +--- /dev/null ++++ b/drivers/nvmem/sophgo-efuse.c +@@ -0,0 +1,176 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Sophgo SoC eFuse driver ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SG2044_EFUSE_CONTENT_SIZE 0x400 ++ ++#define SG2044_EFUSE_MD 0x000 ++#define SG2044_EFUSE_ADR 0x004 ++#define SG2044_EFUSE_RD_DATA 0x00c ++ ++#define SG2044_EFUSE_MODE GENMASK(1, 0) ++#define SG2044_EFUSE_MODE_READ 2 ++ ++#define SG2044_EFUSE_BOOT_DONE BIT(7) ++#define SG2044_BOOT_TIMEOUT 10000 ++ ++#define SG2044_EFUSE_ADR_ADDR GENMASK(7, 0) ++ ++#define SG2044_EFUSE_ALIGN 4 ++ ++struct sophgo_efuses { ++ void __iomem *base; ++ struct clk_bulk_data *clks; ++ int num_clks; ++ struct mutex mutex; ++}; ++ ++static int sg2044_efuse_wait_mode(struct sophgo_efuses *efuse) ++{ ++ u32 value; ++ ++ return readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, ++ FIELD_GET(SG2044_EFUSE_MODE, value) == 0, ++ 1, SG2044_BOOT_TIMEOUT); ++} ++ ++static int sg2044_efuse_set_mode(struct sophgo_efuses *efuse, int mode) ++{ ++ u32 val = readl(efuse->base + SG2044_EFUSE_MD); ++ ++ val &= ~SG2044_EFUSE_MODE; ++ val |= FIELD_PREP(SG2044_EFUSE_MODE, mode); ++ ++ writel(val, efuse->base + SG2044_EFUSE_MD); ++ ++ return sg2044_efuse_wait_mode(efuse); ++} ++ ++static u32 sg2044_efuses_read_strip(struct sophgo_efuses *efuse, ++ unsigned int offset, u32 *strip) ++{ ++ u32 val = FIELD_PREP(SG2044_EFUSE_ADR_ADDR, offset); ++ int ret; ++ ++ guard(mutex)(&efuse->mutex); ++ ++ writel(val, efuse->base + SG2044_EFUSE_ADR); ++ ++ ret = sg2044_efuse_set_mode(efuse, SG2044_EFUSE_MODE_READ); ++ if (ret < 0) ++ return ret; ++ ++ *strip = readl(efuse->base + SG2044_EFUSE_RD_DATA); ++ ++ return 0; ++} ++ ++static int sg2044_efuses_read(void *context, unsigned int offset, void *val, ++ size_t bytes) ++{ ++ struct sophgo_efuses *efuse = context; ++ unsigned int start, start_offset, end, i; ++ u32 value; ++ u8 *buf; ++ int ret; ++ ++ start = rounddown(offset, SG2044_EFUSE_ALIGN); ++ end = roundup(offset + bytes, SG2044_EFUSE_ALIGN); ++ start_offset = offset - start; ++ ++ start /= SG2044_EFUSE_ALIGN; ++ end /= SG2044_EFUSE_ALIGN; ++ ++ ret = readl_poll_timeout(efuse->base + SG2044_EFUSE_MD, value, ++ (value & SG2044_EFUSE_BOOT_DONE), ++ 1, SG2044_BOOT_TIMEOUT); ++ if (ret < 0) ++ return ret; ++ ++ buf = kzalloc(end - start, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ for (i = start; i < end; i++) { ++ ret = sg2044_efuses_read_strip(efuse, i, &value); ++ if (ret) ++ goto failed; ++ ++ memcpy(&buf[(i - start) * 4], &value, SG2044_EFUSE_ALIGN); ++ } ++ ++ memcpy(val, buf + start_offset, bytes); ++ ++failed: ++ kfree(buf); ++ ++ return ret; ++} ++ ++static int sophgo_efuses_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct sophgo_efuses *efuse; ++ struct nvmem_config config = { ++ .dev = &pdev->dev, ++ .add_legacy_fixed_of_cells = true, ++ .read_only = true, ++ .reg_read = sg2044_efuses_read, ++ .stride = 1, ++ .word_size = 1, ++ .name = "sophgo-efuse", ++ .id = NVMEM_DEVID_AUTO, ++ .root_only = true, ++ }; ++ ++ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); ++ if (!efuse) ++ return -ENOMEM; ++ ++ efuse->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(efuse->base)) ++ return PTR_ERR(efuse->base); ++ ++ efuse->num_clks = devm_clk_bulk_get_all_enabled(&pdev->dev, &efuse->clks); ++ if (efuse->num_clks < 0) ++ return dev_err_probe(dev, efuse->num_clks, "failed to get clocks\n"); ++ ++ config.priv = efuse; ++ config.size = SG2044_EFUSE_CONTENT_SIZE; ++ ++ return PTR_ERR_OR_ZERO(devm_nvmem_register(config.dev, &config)); ++} ++ ++static const struct of_device_id sophgo_efuses_of_match[] = { ++ { .compatible = "sophgo,sg2044-efuse", }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, sophgo_efuses_of_match); ++ ++static struct platform_driver sophgo_efuses_driver = { ++ .driver = { ++ .name = "sophgo_efuse", ++ .of_match_table = sophgo_efuses_of_match, ++ }, ++ .probe = sophgo_efuses_probe, ++}; ++ ++module_platform_driver(sophgo_efuses_driver); ++ ++MODULE_AUTHOR("Inochi Amaoto "); ++MODULE_DESCRIPTION("Sophgo efuse driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux/0246-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch b/SPECS/linux/0246-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch deleted file mode 100644 index 63061591a7..0000000000 --- a/SPECS/linux/0246-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch +++ /dev/null @@ -1,579 +0,0 @@ -From 335e17bce811bb12c282e764bcc9742dd83e6ed1 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Fri, 16 May 2025 11:12:26 +0800 -Subject: [PATCH 246/269] RVCK: riscv:dts: add dp1000.dts for UltraRIsc DP1000 - SoC - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/8fa6586e8607e8f2b9bbf701a6cf282b29dac1f7 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/Makefile | 1 + - arch/riscv/boot/dts/ultrarisc/Makefile | 2 + - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 536 +++++++++++++++++++++++ - 3 files changed, 539 insertions(+) - create mode 100644 arch/riscv/boot/dts/ultrarisc/Makefile - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000.dts - -diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile -index 69d8751fb17c..702882974251 100644 ---- a/arch/riscv/boot/dts/Makefile -+++ b/arch/riscv/boot/dts/Makefile -@@ -12,3 +12,4 @@ subdir-y += spacemit - subdir-y += starfive - subdir-y += tenstorrent - subdir-y += thead -+subdir-y += ultrarisc -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -new file mode 100644 -index 000000000000..c27f490e2b99 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+dtb-y += dp1000.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -new file mode 100644 -index 000000000000..3eb811f73aa8 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -0,0 +1,536 @@ -+/* -+* SPDX-License-Identifier: GPL-2.0+ -+* -+* Copyright (c) 2019-2022 UltraRisc,Inc -+* -+*/ -+ -+/dts-v1/; -+ -+/ { -+ #address-cells = <0x02>; -+ #size-cells = <0x02>; -+ compatible = "ultrarisc,dp1000"; -+ model = "ultrarisc,dp1000"; -+ -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS1,115200"; -+ stdout-path = &uart1; -+ }; -+ -+ cpus { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ timebase-frequency = <10000000>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ reg = <0x00>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu0_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ reg = <0x1>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu1_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ reg = <0x2>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu2_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ reg = <0x3>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu3_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu4: cpu@4 { -+ device_type = "cpu"; -+ reg = <0x10>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu4_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu5: cpu@5 { -+ device_type = "cpu"; -+ reg = <0x11>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu5_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu6: cpu@6 { -+ device_type = "cpu"; -+ reg = <0x12>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ -+ clock-frequency = <2000000000>; -+ -+ cpu6_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ cpu7: cpu@7 { -+ device_type = "cpu"; -+ reg = <0x13>; -+ status = "okay"; -+ compatible = "riscv"; -+ riscv,isa = "rv64imafdcbh"; -+ mmu-type = "riscv,sv48"; -+ clock-frequency = <2000000000>; -+ cpu7_intc:interrupt-controller { -+ #address-cells = <0x01>; -+ interrupt-controller; -+ compatible = "riscv,cpu-intc"; -+ #interrupt-cells = <0x01>; -+ }; -+ }; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00 0x80000000 0x4 0x00000000>; -+ }; -+ -+ soc { -+ #address-cells = <0x02>; -+ #size-cells = <0x02>; -+ compatible = "simple-bus"; -+ ranges; -+ -+ clocks { -+ compatible = "simple-bus"; -+ u-boot,dm-pre-reloc; -+ device_clk: device_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <62500000>; -+ #clock-cells = <0>; -+ }; -+ csr_clk: csr_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <250000000>; -+ #clock-cells = <0>; -+ }; -+ }; -+ -+ clint: clint@8000000 { -+ compatible = "riscv,clint0"; -+ interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, -+ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -+ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -+ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -+ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -+ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -+ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -+ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; -+ reg = <0x00 0x8000000 0x00 0x100000>; -+ }; -+ -+ plic: plic@9000000 { -+ #interrupt-cells = <1>; -+ #address-cells = <0>; -+ phandle = <0x01>; -+ compatible = "ultrarisc,dp1000-plic"; -+ interrupt-controller; -+ interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, -+ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -+ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -+ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -+ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -+ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -+ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -+ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; -+ reg = <0x00 0x9000000 0x00 0x4000000>; -+ riscv,max-priority = <0x07>; -+ riscv,ndev = <160>; -+ }; -+ -+ uart0: serial@20300000 { -+ interrupt-parent = <0x01>; -+ interrupts = <17>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20300000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart1: serial@20310000 { -+ interrupt-parent = <0x01>; -+ interrupts = <18>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20310000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart2: serial@20400000 { -+ interrupt-parent = <0x01>; -+ interrupts = <25>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20400000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ uart3: serial@20410000 { -+ interrupt-parent = <0x01>; -+ interrupts = <26>; -+ clock-frequency = <62500000>; -+ current-speed = <115200>; -+ reg = <0x00 0x20410000 0x00 0x10000>; -+ compatible = "ultrarisc,dp1000-uart","ns16550"; -+ reg-offset = <0x0>; -+ reg-shift = <0x02>; -+ }; -+ -+ spi0: spi@20320000 { -+ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ status = "okay"; -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ reg = <0x0 0x20320000 0x0 0x1000>; -+ interrupt-parent = <0x01>; -+ interrupts = <19>; -+ clocks = <&device_clk>; -+ clock-names = "device_clk"; -+ num-cs = <3>; -+ spi-max-frequency = <62500000>; -+ mmc0: mmc@0 { -+ compatible = "mmc-spi-slot"; -+ spi-max-frequency = <15625000>; -+ reg = <0x00>; -+ voltage-ranges = <3300 3300>; -+ disable-wp; -+ }; -+ }; -+ -+ spi1: spi@20420000 { -+ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ status = "okay"; -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ reg = <0x0 0x20420000 0x0 0x1000>; -+ interrupt-parent = <0x01>; -+ interrupts = <27>; -+ clocks = <&device_clk>; -+ clock-names = "device_clk"; -+ num-cs = <3>; -+ spi-max-frequency = <62500000>; -+ }; -+ -+ i2c0: i2c@20330000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20330000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <20>; -+ }; -+ -+ i2c1: i2c@20340000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20340000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <21>; -+ }; -+ -+ i2c2: i2c@20430000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20430000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <28>; -+ }; -+ -+ i2c3: i2c@20440000{ -+ compatible = "snps,designware-i2c"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20440000 0x0 0x100>; -+ clock-frequency = <400000>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <29>; -+ }; -+ -+ wdt0: watchdog@20210000 { -+ compatible = "snps,dw-wdt"; -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20210000 0x0 0x100>; -+ interrupt-parent = <0x01>; -+ interrupts = <33>; -+ clocks = <&device_clk>; -+ }; -+ -+ timer0: timer@20220000 { -+ compatible = "snps,dw-apb-timer"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20220000 0x0 0x100>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <35>; -+ status = "okay"; -+ }; -+ -+ timer1: timer@20230000 { -+ compatible = "snps,dw-apb-timer"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20230000 0x0 0x100>; -+ clocks = <&device_clk>; -+ interrupt-parent = <0x01>; -+ interrupts = <36>; -+ status = "okay"; -+ }; -+ -+ gpio: gpio@20200000 { -+ compatible = "snps,dw-apb-gpio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20200000 0x0 0x1000>; -+ clocks = <&csr_clk>, <&device_clk>; -+ clock-names = "bus", "db"; -+ status = "okay"; -+ -+ porta: gpio-port@0 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <0>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <16>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ interrupt-parent = <0x01>; -+ interrupts = <34>; -+ }; -+ -+ portb: gpio-port@1 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <1>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ -+ portc: gpio-port@2 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <2>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ -+ portd: gpio-port@3 { -+ compatible = "snps,dw-apb-gpio-port"; -+ reg = <3>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ snps,nr-gpios = <8>; -+ }; -+ }; -+ -+ ethernet1@38000000 { -+ clocks = <&csr_clk>; -+ clock-names = "stmmaceth"; -+ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; -+ interrupt-parent = <0x01>; -+ interrupts = <84>; -+ interrupt-names = "macirq"; -+ reg = <0x00 0x38000000 0x00 0x1000000>; -+ local-mac-address = [ff ff ff ff ff ff]; -+ phy-mode = "rgmii"; -+ max-speed = <1000>; -+ snps,txpbl = <8>; -+ snps,rxpbl = <8>; -+ phy-handle = <&phy0>; -+ mdio { -+ #address-cells = <0x01>; -+ #size-cells = <0x00>; -+ compatible = "snps,dwmac-mdio"; -+ phy0: phy@0{ -+ phandle = <0x04>; -+ reg = <0x00>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ dmac: dma-controller@39000000 { -+ compatible = "snps,axi-dma-1.01a"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x39000000 0x0 0x400>; -+ clocks = <&device_clk>, <&device_clk>; -+ clock-names = "core-clk", "cfgr-clk"; -+ interrupt-parent = <0x01>; -+ interrupts = <152>; -+ #dma-cells = <1>; -+ dma-channels = <8>; -+ snps,dma-masters = <1>; -+ snps,data-width = <4>; -+ snps,block-size = <512 512 512 512 512 512 512 512>; -+ snps,priority = <0 1 2 3 4 5 6 7>; -+ snps,axi-max-burst-len = <256>; -+ }; -+ -+ pcie_x16: pcie@21000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x21000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x4fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <16>; -+ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <43>, <44>, <45>, <46>, <47>, <48>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, -+ <0x0 0x0 0x0 0x2 &plic 45>, -+ <0x0 0x0 0x0 0x3 &plic 46>, -+ <0x0 0x0 0x0 0x4 &plic 47>; -+ }; -+ -+ pcie_x4a: pcie@23000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x23000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x6fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <4>; -+ ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <63>, <64>, <65>, <66>, <67>, <68>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, -+ <0x0 0x0 0x0 0x2 &plic 65>, -+ <0x0 0x0 0x0 0x3 &plic 66>, -+ <0x0 0x0 0x0 0x4 &plic 67>; -+ }; -+ -+ pcie_x4b: pcie@24000000 { -+ compatible = "ultrarisc,dw-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ reg = <0x0 0x24000000 0x0 0x01000000>, /* IP registers */ -+ <0x0 0x7fff0000 0x0 0x00010000>; /* Configuration space */ -+ reg-names = "dbi", "config"; -+ device_type = "pci"; -+ dma-coherent; -+ bus-range = <0x0 0xff>; -+ num-lanes = <4>; -+ ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ -+ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ -+ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <4>; -+ interrupt-parent = <&plic>; -+ interrupts = <73>, <74>, <75>, <76>, <77>, <78>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, -+ <0x0 0x0 0x0 0x2 &plic 75>, -+ <0x0 0x0 0x0 0x3 &plic 76>, -+ <0x0 0x0 0x0 0x4 &plic 77>; -+ }; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux/0246-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch b/SPECS/linux/0246-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch new file mode 100644 index 0000000000..e1b5faade9 --- /dev/null +++ b/SPECS/linux/0246-SOPHGO-riscv-dts-sophgo-sg2044-Add-eFUSE-device.patch @@ -0,0 +1,54 @@ +From 79773864273d7e2c3359f2ebeebc658eef9f78fe Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Thu, 5 Dec 2024 13:24:13 +0800 +Subject: [RUYI PATCH] SOPHGO: riscv: dts: sophgo: sg2044: Add eFUSE device + +Add eFUSE controller node for SG2044. + +Signed-off-by: Inochi Amaoto +--- + arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ + arch/riscv/boot/dts/sophgo/sg2044.dtsi | 12 ++++++++++++ + 2 files changed, 16 insertions(+) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +index fed3d9a384a0..1b506972d465 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts ++++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +@@ -36,6 +36,10 @@ &emmc { + status = "okay"; + }; + ++&efuse0 { ++ status = "okay"; ++}; ++ + &gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; +diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +index 320c4d1d08e6..9577aae08f7f 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +@@ -408,6 +408,18 @@ sd: mmc@703000b000 { + status = "disabled"; + }; + ++ efuse0: efuse@7040000000 { ++ compatible = "sophgo,sg2044-efuse"; ++ reg = <0x70 0x40000000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&clk CLK_GATE_EFUSE>, ++ <&clk CLK_GATE_APB_EFUSE>; ++ clock-names = "core", "apb"; ++ resets = <&rst RST_EFUSE0>; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@7040005000 { + compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; + reg = <0x70 0x40005000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux/0247-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch b/SPECS/linux/0247-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch deleted file mode 100644 index caa12006fb..0000000000 --- a/SPECS/linux/0247-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch +++ /dev/null @@ -1,881 +0,0 @@ -From 7e1c7fa705a65bb85bf2d2fdcf0d06e630c1c1df Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Fri, 17 Jan 2025 19:34:48 +0800 -Subject: [PATCH 247/269] RVCK: pinctrl: add pinctrl dirver for UltraRisc - DP1000 - -support pinmux and pinconf for UltraRisc DP1000 SoC - -Signed-off-by: Jia Wang -Signed-off-by: Yanteng Si -FROM: https://github.com/RVCK-Project/rvck/commit/2fdd7d95fb0408b67353ea82e378773ebfe39ade -Signed-off-by: Han Gao ---- - drivers/pinctrl/Kconfig | 1 + - drivers/pinctrl/Makefile | 1 + - drivers/pinctrl/ultrarisc/Kconfig | 20 + - drivers/pinctrl/ultrarisc/Makefile | 4 + - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 122 +++++ - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 503 ++++++++++++++++++ - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 78 +++ - .../dt-bindings/pinctrl/ur-dp1000-pinctrl.h | 65 +++ - 8 files changed, 794 insertions(+) - create mode 100644 drivers/pinctrl/ultrarisc/Kconfig - create mode 100644 drivers/pinctrl/ultrarisc/Makefile - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c - create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h - create mode 100644 include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h - -diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig -index afecd9407f53..bf65ef30394a 100644 ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -720,5 +720,6 @@ source "drivers/pinctrl/ti/Kconfig" - source "drivers/pinctrl/uniphier/Kconfig" - source "drivers/pinctrl/visconti/Kconfig" - source "drivers/pinctrl/vt8500/Kconfig" -+source "drivers/pinctrl/ultrarisc/Kconfig" - - endif -diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile -index f7d5d5f76d0c..4df3e52518ea 100644 ---- a/drivers/pinctrl/Makefile -+++ b/drivers/pinctrl/Makefile -@@ -98,3 +98,4 @@ obj-y += ti/ - obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ - obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ - obj-$(CONFIG_ARCH_VT8500) += vt8500/ -+obj-$(CONFIG_ARCH_ULTRARISC) += ultrarisc/ -diff --git a/drivers/pinctrl/ultrarisc/Kconfig b/drivers/pinctrl/ultrarisc/Kconfig -new file mode 100644 -index 000000000000..e4db80843bea ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/Kconfig -@@ -0,0 +1,20 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+config PINCTRL_ULTRARISC -+ bool -+ depends on OF -+ select PINMUX -+ select GENERIC_PINCTRL_GROUPS -+ select GENERIC_PINCONF -+ select GENERIC_PINMUX_FUNCTIONS -+ select GPIOLIB -+ select IRQ_DOMAIN_HIERARCHY -+ select MFD_SYSCON -+ -+config PINCTRL_ULTRARISC_DP1000 -+ tristate "Pinctrl driver of UltraRisc DP1000" -+ select PINCTRL_ULTRARISC -+ depends on OF && HAS_IOMEM -+ help -+ This driver configures the UltraRisc DP1000 SoC's pinctrl -+ subsystem. -diff --git a/drivers/pinctrl/ultrarisc/Makefile b/drivers/pinctrl/ultrarisc/Makefile -new file mode 100644 -index 000000000000..5bf3f449d59b ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+ -+obj-$(CONFIG_PINCTRL_ULTRARISC) += pinctrl-ultrarisc.o -+obj-$(CONFIG_PINCTRL_ULTRARISC_DP1000) += pinctrl-ultrarisc-dp1000.o -\ No newline at end of file -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -new file mode 100644 -index 000000000000..217f671fe63a ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -0,0 +1,122 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc DP1000 pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../pinctrl-utils.h" -+#include "../pinmux.h" -+#include "../core.h" -+#include "../devicetree.h" -+ -+#include "pinctrl-ultrarisc.h" -+ -+static const struct pinctrl_pin_desc ur_dp1000_pins[] = { -+ // PA -+ PINCTRL_PIN(0, "PA0"), -+ PINCTRL_PIN(1, "PA1"), -+ PINCTRL_PIN(2, "PA2"), -+ PINCTRL_PIN(3, "PA3"), -+ PINCTRL_PIN(4, "PA4"), -+ PINCTRL_PIN(5, "PA5"), -+ PINCTRL_PIN(6, "PA6"), -+ PINCTRL_PIN(7, "PA7"), -+ PINCTRL_PIN(8, "PA8"), -+ PINCTRL_PIN(9, "PA9"), -+ PINCTRL_PIN(10, "PA10"), -+ PINCTRL_PIN(11, "PA11"), -+ PINCTRL_PIN(12, "PA12"), -+ PINCTRL_PIN(13, "PA13"), -+ PINCTRL_PIN(14, "PA14"), -+ PINCTRL_PIN(15, "PA15"), -+ // PB -+ PINCTRL_PIN(16, "PB0"), -+ PINCTRL_PIN(17, "PB1"), -+ PINCTRL_PIN(18, "PB2"), -+ PINCTRL_PIN(19, "PB3"), -+ PINCTRL_PIN(20, "PB4"), -+ PINCTRL_PIN(21, "PB5"), -+ PINCTRL_PIN(22, "PB6"), -+ PINCTRL_PIN(23, "PB7"), -+ // PC -+ PINCTRL_PIN(24, "PC0"), -+ PINCTRL_PIN(25, "PC1"), -+ PINCTRL_PIN(26, "PC2"), -+ PINCTRL_PIN(27, "PC3"), -+ PINCTRL_PIN(28, "PC4"), -+ PINCTRL_PIN(29, "PC5"), -+ PINCTRL_PIN(30, "PC6"), -+ PINCTRL_PIN(31, "PC7"), -+ // PD -+ PINCTRL_PIN(32, "PD0"), -+ PINCTRL_PIN(33, "PD1"), -+ PINCTRL_PIN(34, "PD2"), -+ PINCTRL_PIN(35, "PD3"), -+ PINCTRL_PIN(36, "PD4"), -+ PINCTRL_PIN(37, "PD5"), -+ PINCTRL_PIN(38, "PD6"), -+ PINCTRL_PIN(39, "PD7"), -+ // LPC -+ PINCTRL_PIN(40, "LPC0"), -+ PINCTRL_PIN(41, "LPC1"), -+ PINCTRL_PIN(42, "LPC2"), -+ PINCTRL_PIN(43, "LPC3"), -+ PINCTRL_PIN(44, "LPC4"), -+ PINCTRL_PIN(45, "LPC5"), -+ PINCTRL_PIN(46, "LPC6"), -+ PINCTRL_PIN(47, "LPC7"), -+ PINCTRL_PIN(48, "LPC8"), -+ PINCTRL_PIN(49, "LPC9"), -+ PINCTRL_PIN(50, "LPC10"), -+ PINCTRL_PIN(51, "LPC11"), -+ PINCTRL_PIN(52, "LPC12"), -+}; -+ -+static struct ur_pinctrl_match_data ur_dp1000_match_data = { -+ .pins = ur_dp1000_pins, -+ .npins = ARRAY_SIZE(ur_dp1000_pins), -+ .offset = 0x2c0, -+ .ports = { -+ {"A", 16, 0x2c0, 0x310}, -+ {"B", 8, 0x2c4, 0x318}, -+ {"C", 8, 0x2c8, 0x31c}, -+ {"D", 8, 0x2cc, 0x320}, -+ {"LPC", 13, 0x2d0, 0x324}, -+ }, -+}; -+ -+enum ur_dp1000_port_list { -+ PORT_A = 0, -+ PORT_B, -+ PORT_C, -+ PORT_D, -+ PORT_LPC -+}; -+ -+ -+static const struct of_device_id ur_pinctrl_of_match[] = { -+ { .compatible = "ultrarisc,dp1000-pinctrl", .data = &ur_dp1000_match_data, }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, ur_pinctrl_of_match); -+ -+static struct platform_driver ur_pinctrl_driver = { -+ .driver = { -+ .name = "ultrarisc-pinctrl-dp1000", -+ .of_match_table = ur_pinctrl_of_match, -+ }, -+ .probe = ur_pinctrl_probe, -+ .remove = ur_pinctrl_remove, -+}; -+ -+module_platform_driver(ur_pinctrl_driver); -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -new file mode 100644 -index 000000000000..667d59e0ac6e ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -0,0 +1,503 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../pinctrl-utils.h" -+#include "../pinmux.h" -+#include "../core.h" -+#include "../devicetree.h" -+ -+#include "pinctrl-ultrarisc.h" -+ -+static int ur_pin_to_desc(struct pinctrl_dev *pctldev, struct ur_pin_val *pin_val) -+{ -+ int index = 0; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ const struct ur_pinctrl_match_data *ur_match_data = ur_pinctrl->match_data; -+ -+ for (int i = 0; i < pin_val->port; i++) -+ index += ur_match_data->ports[i].npins; -+ index += pin_val->pin; -+ dev_dbg(pctldev->dev, "port %d pin %d index %d\n", pin_val->port, pin_val->pin, index); -+ return index; -+} -+ -+static int ur_subnode_to_pin(struct pinctrl_dev *pctldev, -+ const char *name, -+ enum pinctrl_map_type type, -+ struct device_node *np, -+ int **pins, -+ struct ur_pin_val **pin_val, -+ int *pin_num) -+{ -+ struct ur_pin_val *pin_vals; -+ int rows; -+ int ret = -EINVAL; -+ int *group_pins; -+ const char **pgnames; -+ -+ dev_dbg(pctldev->dev, "pinctrl node %s\n", np->name); -+ rows = pinctrl_count_index_with_args(np, name); -+ if (rows < 0) { -+ dev_err(pctldev->dev, "%s count is invalid %d\n", name, rows); -+ return rows; -+ } -+ -+ pin_vals = devm_kcalloc(pctldev->dev, rows, sizeof(*pin_vals), GFP_KERNEL); -+ if (!pin_vals) { -+ return -ENOMEM; -+ } -+ -+ group_pins = devm_kcalloc(pctldev->dev, rows, sizeof(*group_pins), GFP_KERNEL); -+ if (!group_pins) { -+ ret = -ENOMEM; -+ goto free_pin_vals; -+ } -+ -+ pgnames = devm_kzalloc(pctldev->dev, sizeof(*pgnames), GFP_KERNEL); -+ if (!pgnames) { -+ ret = -ENOMEM; -+ goto free_pins; -+ } -+ -+ for (int i = 0; i < rows; i++) { -+ struct of_phandle_args pin_args; -+ -+ ret = pinctrl_parse_index_with_args(np, name, i, &pin_args); -+ if (ret) { -+ dev_err(pctldev->dev, "parse args of %s index %d failed\n", name, i); -+ goto free_pgnames; -+ } -+ -+ if (pin_args.args_count < 3) { -+ dev_err(pctldev->dev, "invalid args_count(%d) of %s index %d/%d\n", -+ pin_args.args_count, name, i, rows); -+ ret = -EINVAL; -+ goto free_pgnames; -+ } -+ pin_vals[i].port = pin_args.args[0]; -+ pin_vals[i].pin = pin_args.args[1]; -+ pin_vals[i].mode = pin_args.args[2]; -+ -+ dev_dbg(pctldev->dev, "found a pinctrl: port=%d pin=%d val=0x%x\n", -+ pin_vals[i].port, pin_vals[i].pin, pin_vals[i].mode); -+ -+ group_pins[i] = ur_pin_to_desc(pctldev, &pin_vals[i]); -+ } -+ -+ dev_dbg(pctldev->dev, "get an pinmux of %s\n", np->name); -+ -+ ret = pinctrl_generic_add_group(pctldev, np->name, group_pins, rows, pin_vals); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "add group %s failed\n", np->name); -+ goto free_pgnames; -+ } -+ -+ *pgnames = np->name; -+ ret = pinmux_generic_add_function(pctldev, np->name, pgnames, 1, NULL); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "add function %s failed\n", np->name); -+ goto free_group; -+ } -+ -+ dev_dbg(pctldev->dev, "add group and function of %s\n", np->name); -+ -+ *pins = group_pins; -+ *pin_val = pin_vals; -+ *pin_num = rows; -+ -+ return 0; -+ -+free_group: -+ pinctrl_generic_remove_group(pctldev, ret); -+free_pgnames: -+ devm_kfree(pctldev->dev, pgnames); -+free_pins: -+ devm_kfree(pctldev->dev, group_pins); -+free_pin_vals: -+ devm_kfree(pctldev->dev, pin_vals); -+ return ret; -+} -+ -+static int ur_pinmux_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map *map) -+{ -+ int ret; -+ int *pins; -+ struct ur_pin_val *pin_vals; -+ int pin_num; -+ -+ ret = ur_subnode_to_pin(pctldev, PINMUX_PROP_NAME, PIN_MAP_TYPE_MUX_GROUP, -+ np, &pins, &pin_vals, &pin_num); -+ if (ret) { -+ dev_err(pctldev->dev, "get pinmux data %s failed\n", np->name); -+ return ret; -+ } -+ -+ map->type = PIN_MAP_TYPE_MUX_GROUP; -+ map->data.mux.group = np->name; -+ map->data.mux.function = np->name; -+ -+ dev_dbg(pctldev->dev, "type=%d, mux.group=%s, mux.function=%s\n", -+ map->type, map->data.mux.group, map->data.mux.function); -+ -+ return 0; -+} -+ -+static int ur_pinconf_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map *map) -+{ -+ int ret; -+ int *pins; -+ struct ur_pin_val *pin; -+ int pin_num; -+ -+ ret = ur_subnode_to_pin(pctldev, PINCONF_PROP_NAME, PIN_MAP_TYPE_CONFIGS_GROUP, -+ np, &pins, &pin, &pin_num); -+ if (ret) { -+ dev_err(pctldev->dev, "get pinconf data %s failed\n", np->name); -+ return ret; -+ } -+ -+ dev_dbg(pctldev->dev, "get an pinconf of %s\n", np->name); -+ map->type = PIN_MAP_TYPE_CONFIGS_GROUP; -+ map->data.configs.group_or_pin = np->name; -+ map->data.configs.configs = (unsigned long *)pin; -+ map->data.configs.num_configs = pin_num; -+ -+ dev_dbg(pctldev->dev, "type=%d, config.group_or_pin=%s, configs.num_config=%d\n", -+ map->type, map->data.configs.group_or_pin, map->data.configs.num_configs); -+ -+ return 0; -+} -+ -+static int ur_dt_node_to_map(struct pinctrl_dev *pctldev, -+ struct device_node *np, -+ struct pinctrl_map **map, -+ unsigned int *num_maps) -+{ -+ int ret; -+ bool mux_present = false, conf_present = false; -+ struct pinctrl_map *new_map; -+ unsigned int map_num = 0, prop_count = 0; -+ -+ //device_get_named_child_node(pctldev->dev, np->name); -+ if (of_property_present(np, PINMUX_PROP_NAME)) { -+ mux_present = true; -+ prop_count++; -+ } -+ if (of_property_present(np, PINCONF_PROP_NAME)) { -+ conf_present = true; -+ prop_count++; -+ } -+ -+ if (!prop_count) { -+ dev_err(pctldev->dev, "no pinctrl node(%d) in %s\n", prop_count, np->name); -+ return -EINVAL; -+ } -+ -+ new_map = devm_kmalloc_array(pctldev->dev, prop_count, sizeof(**map), GFP_KERNEL); -+ if (!new_map) -+ return -ENOMEM; -+ -+ *map = new_map; -+ if (mux_present) { -+ ret = ur_pinmux_to_map(pctldev, np, new_map); -+ if (!ret) { -+ new_map++; -+ map_num++; -+ } -+ } -+ if (conf_present) { -+ ret = ur_pinconf_to_map(pctldev, np, new_map); -+ if (!ret) -+ map_num++; -+ } -+ -+ if (!map_num) { -+ dev_err(pctldev->dev, "no pinctrl info of %s failed\n", np->name); -+ goto free_map; -+ } -+ *num_maps = map_num; -+ -+ return 0; -+ -+free_map: -+ devm_kfree(pctldev->dev, new_map); -+ return ret; -+} -+ -+static void ur_dt_free_map(struct pinctrl_dev *pctldev, -+ struct pinctrl_map *map, unsigned int num_maps) -+{ -+ if (map) -+ devm_kfree(pctldev->dev, map); -+} -+ -+static void ur_pin_dbg_show(struct pinctrl_dev *pctldev, -+ struct seq_file *s, unsigned int offset) -+{ -+ seq_printf(s, "%s", dev_name(pctldev->dev)); -+} -+ -+static const struct pinctrl_ops ur_pinctrl_ops = { -+ .get_groups_count = pinctrl_generic_get_group_count, -+ .get_group_name = pinctrl_generic_get_group_name, -+ .get_group_pins = pinctrl_generic_get_group_pins, -+ .dt_node_to_map = ur_dt_node_to_map, -+ .dt_free_map = ur_dt_free_map, -+ .pin_dbg_show = ur_pin_dbg_show, -+}; -+ -+static int ur_set_pin_mux(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) -+{ -+ unsigned long flag; -+ //bool clear_mode = false; -+ void __iomem *reg; -+ u32 val; -+ const struct ur_port_desc *port; -+ -+ port = &pin_ctrl->match_data->ports[pin_vals->port]; -+ -+ reg = pin_ctrl->base + port->func_offset; -+ -+ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); -+ val = readl_relaxed(reg); -+ val &= ~((UR_FUNC0 | UR_FUNC1)<pin); -+ val |= (pin_vals->mode << pin_vals->pin); -+ writel_relaxed(val, reg); -+ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); -+ -+ return 0; -+} -+ -+static int ur_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, -+ unsigned int group_selector) -+{ -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ struct group_desc *ur_group; -+ struct ur_pin_val *pin_vals; -+ -+ dev_dbg(pctldev->dev, "set mux: func_selector=%d, group_selector=%d\n", -+ func_selector, group_selector); -+ ur_group = pinctrl_generic_get_group(pctldev, group_selector); -+ if (!ur_group) { -+ dev_err(pctldev->dev, "get group %d failed\n", group_selector); -+ return -EINVAL; -+ } -+ -+ dev_dbg(pctldev->dev, "get group %s, num_pins=%zu\n", ur_group->grp.name, ur_group->grp.npins); -+ pin_vals = ur_group->data; -+ if (!pin_vals) { -+ dev_err(pctldev->dev, "data of %s is invalid\n", ur_group->grp.name); -+ return -EINVAL; -+ } -+ -+ for (int i = 0; i < ur_group->grp.npins; i++) -+ ur_set_pin_mux(ur_pinctrl, &pin_vals[i]); -+ -+ return 0; -+} -+ -+static const struct pinmux_ops ur_pinmux_ops = { -+ .get_functions_count = pinmux_generic_get_function_count, -+ .get_function_name = pinmux_generic_get_function_name, -+ .get_function_groups = pinmux_generic_get_function_groups, -+ .set_mux = ur_set_mux, -+ .strict = true, -+}; -+ -+#define UR_CONF_BIT_PER_PIN (4) -+#define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) -+static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) -+{ -+ const struct ur_port_desc *port_desc; -+ unsigned long flag; -+ void __iomem *reg; -+ u32 val, conf; -+ -+ port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; -+ reg = pin_ctrl->base + port_desc->conf_offset; -+ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); -+ reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; -+ dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); -+ -+ conf = pin_vals->conf << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN); -+ dev_dbg(pin_ctrl->dev, "pinconf conf=0x%x\n", conf); -+ -+ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); -+ val = readl_relaxed(reg); -+ val &= ~(UR_BIAS_MASK << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN)); -+ val |= conf; -+ writel_relaxed(val, reg); -+ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); -+ dev_dbg(pin_ctrl->dev, "pinconf val=0x%x\n", val); -+ -+ return 0; -+} -+ -+static int ur_pin_config_get(struct pinctrl_dev *pctldev, -+ unsigned int pin, -+ unsigned long *config) -+{ -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d\n", __func__, __LINE__, pin); -+ // TODO: this is call by pinconf-generic -+ return -EOPNOTSUPP; -+} -+ -+static int ur_pin_config_set(struct pinctrl_dev *pctldev, -+ unsigned int pin, -+ unsigned long *configs, -+ unsigned int num_configs) -+{ -+ struct ur_pin_val *pin_conf; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", -+ __func__, __LINE__, pin, num_configs); -+ pin_conf = (struct ur_pin_val *)configs; -+ for (int i = 0; i < num_configs; i++) { -+ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -+ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ } -+ return 0; -+} -+ -+static int ur_pin_config_group_get(struct pinctrl_dev *pctldev, -+ unsigned selector, -+ unsigned long *config) -+{ -+ dev_dbg(pctldev->dev, "%s(%d): selector=%d, config=0x%lx\n", -+ __func__, __LINE__, selector, *config); -+ return -EOPNOTSUPP; -+} -+ -+static int ur_pin_config_group_set(struct pinctrl_dev *pctldev, -+ unsigned int selector, -+ unsigned long *configs, -+ unsigned int num_configs) -+{ -+ struct group_desc *ur_group; -+ struct ur_pin_val *pin_conf; -+ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ -+ dev_dbg(pctldev->dev, "%s(%d): selector=%d, num_configs=%d\n", -+ __func__, __LINE__, selector, num_configs); -+ ur_group = pinctrl_generic_get_group(pctldev, selector); -+ if (!ur_group) { -+ dev_err(pctldev->dev, "Cannot get group by selector %d\n", selector); -+ return -EINVAL; -+ } -+ -+ dev_dbg(pctldev->dev, "get pinconf group %s\n", ur_group->grp.name); -+ pin_conf = (struct ur_pin_val *)configs; -+ for (int i = 0; i < num_configs; i++) { -+ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -+ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ } -+ return 0; -+} -+ -+static const struct pinconf_ops ur_pinconf_ops = { -+ .pin_config_get = ur_pin_config_get, -+ .pin_config_set = ur_pin_config_set, -+ .pin_config_group_get = ur_pin_config_group_get, -+ .pin_config_group_set = ur_pin_config_group_set, -+#ifdef CONFIG_GENERIC_PINCONF -+ .is_generic = true, -+#endif -+}; -+ -+int ur_pinctrl_probe(struct platform_device *pdev) -+{ -+ struct pinctrl_desc *ur_pinctrl_desc; -+ const struct ur_pinctrl_match_data *pins_data; -+ struct ur_pinctrl *ur_pinctrl; -+ int ret; -+ -+ pins_data = of_device_get_match_data(&pdev->dev); -+ if (!pins_data) -+ return -ENODEV; -+ -+ ur_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl_desc), GFP_KERNEL); -+ if (!ur_pinctrl_desc) { -+ dev_err(&pdev->dev, "pinctrl desc alloc failed\n"); -+ return -ENOMEM; -+ } -+ -+ ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); -+ if (!ur_pinctrl) { -+ dev_err(&pdev->dev, "pinctrl alloc failed\n"); -+ ret = -ENOMEM; -+ goto free_pinctrl_desc; -+ } -+ struct resource *res; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ dev_dbg(&pdev->dev, "iomem start=0x%llx\n", res->start); -+ ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(ur_pinctrl->base)) { -+ dev_err(&pdev->dev, "get ioremap resource failed\n"); -+ ret = -EINVAL; -+ goto free_pinctrl_desc; -+ } -+ dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); -+ ur_pinctrl_desc->name = dev_name(&pdev->dev); -+ ur_pinctrl_desc->owner = THIS_MODULE; -+ ur_pinctrl_desc->pins = pins_data->pins; -+ ur_pinctrl_desc->npins = pins_data->npins; -+ ur_pinctrl_desc->pctlops = &ur_pinctrl_ops; -+ ur_pinctrl_desc->pmxops = &ur_pinmux_ops; -+ ur_pinctrl_desc->confops = &ur_pinconf_ops; -+ -+ ur_pinctrl->dev = &pdev->dev; -+ ur_pinctrl->match_data = pins_data; -+ ur_pinctrl->pctl_desc = ur_pinctrl_desc; -+ raw_spin_lock_init(&ur_pinctrl->lock); -+ mutex_init(&ur_pinctrl->mutex); -+ -+ ret = devm_pinctrl_register_and_init(&pdev->dev, ur_pinctrl_desc, -+ ur_pinctrl, &ur_pinctrl->pctl_dev); -+ if (ret) { -+ dev_err(&pdev->dev, "pinctrl register failed\n"); -+ goto free_pinctrl; -+ } -+ -+ platform_set_drvdata(pdev, ur_pinctrl); -+ -+ return pinctrl_enable(ur_pinctrl->pctl_dev); -+ -+free_pinctrl: -+ devm_kfree(&pdev->dev, ur_pinctrl); -+free_pinctrl_desc: -+ devm_kfree(&pdev->dev, ur_pinctrl_desc); -+ return ret; -+} -+ -+ -+void ur_pinctrl_remove(struct platform_device *pdev) -+{ -+ struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); -+ -+ if (ur_pinctrl->pctl_dev) -+ devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); -+} -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -new file mode 100644 -index 000000000000..eec621bf8b05 ---- /dev/null -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -@@ -0,0 +1,78 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc pinctrl driver -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#ifndef __PINCTRL_ULTRARISC_H__ -+#define __PINCTRL_ULTRARISC_H__ -+ -+#include -+#include -+ -+#define PINMUX_PROP_NAME "pinctrl-pins" -+#define PINCONF_PROP_NAME "pinconf-pins" -+ -+struct ur_pin_conf { -+ u16 pull; -+ u16 drive; -+}; -+ -+struct ur_pin_val { -+ u32 port; -+ u32 pin; -+ union { -+ u32 mode; -+ u32 conf; -+ }; -+#define UR_FUNC_DEF 0 -+#define UR_FUNC0 1 -+#define UR_FUNC1 0x10000 -+ -+#define UR_BIAS_MASK 0x0000000F -+#define UR_PULL_MASK 0x0C -+#define UR_PULL_DIS 0 -+#define UR_PULL_UP 1 -+#define UR_PULL_DOWN 2 -+#define UR_DRIVE_MASK 0x03 -+}; -+ -+struct ur_port_desc { -+ char *name; -+ u32 npins; -+ u32 func_offset; -+ u32 conf_offset; -+}; -+ -+struct ur_pinctrl_match_data { -+ const struct pinctrl_pin_desc *pins; -+ u32 npins; -+ u32 offset; -+ //u32 conf_offset[]; -+ struct ur_port_desc ports[]; -+}; -+ -+ -+struct ur_pinctrl { -+ struct device *dev; -+ struct pinctrl_dev *pctl_dev; -+ struct pinctrl_desc *pctl_desc; -+ void __iomem *base; -+ unsigned int ngroups; -+ const char **grp_names; -+ unsigned int nbanks; -+ const struct ur_pinctrl_match_data *match_data; -+ struct regmap *regmap; -+ raw_spinlock_t lock; -+ struct mutex mutex; -+ struct pinctrl_pin_desc *pins; -+ u32 npins; -+ u32 pkg; -+}; -+ -+int ur_pinctrl_probe(struct platform_device *pdev); -+void ur_pinctrl_remove(struct platform_device *pdev); -+ -+#endif -diff --git a/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h -new file mode 100644 -index 000000000000..5bec446e2411 ---- /dev/null -+++ b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* UltraRisc DP1000 pinctrl header -+ * -+ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#ifndef __UR_DP1000_PINCTRL_H__ -+#define __UR_DP1000_PINCTRL_H__ -+ -+#define UR_DP1000_IOMUX_A 0x0 -+#define UR_DP1000_IOMUX_B 0x1 -+#define UR_DP1000_IOMUX_C 0x2 -+#define UR_DP1000_IOMUX_D 0x3 -+#define UR_DP1000_IOMUX_LPC 0x4 -+ -+#define UR_FUNC_DEF 0 -+#define UR_FUNC0 1 -+#define UR_FUNC1 0x10000 -+ -+/** -+ * port: 'A' 'B' 'C' -+ * Pin in the port -+ * pin: -+ * PA: 0 - 15 -+ * PB-PD: 0 - 7 -+ * func: -+ * UR_FUNC_DEF: default -+ * UR_FUNC0: func0 -+ * UR_FUNC1: func1 -+ */ -+#define UR_DP1000_IOPAD(port, pin, func) (port) (pin) (func) -+ -+/** -+ * Configure pull up/down resistor of the IO pin -+ * UR_PULL_DIS: disable pull-up and pull-down -+ * UR_PULL_UP: enable pull-up -+ * UR_PULL_DOWN: enable pull-down -+ */ -+#define UR_PULL_DIS 0 -+#define UR_PULL_UP 1 -+#define UR_PULL_DOWN 2 -+/** -+ * Configure drive strength of the IO pin -+ * UR_DRIVE_DEF: default value, reset value is 2 -+ * UR_DRIVE_0: 20mA -+ * UR_DRIVE_1: 27mA -+ * UR_DIRVE_2: 33mA -+ * UR_DRIVE_3: 40mA -+ */ -+#define UR_DRIVE_DEF 2 -+#define UR_DRIVE_0 0 -+#define UR_DRIVE_1 1 -+#define UR_DRIVE_2 2 -+#define UR_DRIVE_3 3 -+ -+/** -+ * Combine the pull-up/down resistor and drive strength -+ * pull: UR_PULL_DIS, UR_PULL_UP, UR_PULL_DOWN -+ * drive: UR_DRIVE_DEF, UR_DRIVE_0, UR_DRIVE_1, UR_DRIVE_2, UR_DRIVE_3 -+ */ -+#define UR_DP1000_BIAS(pull, drive) (((pull)<<2) + (drive)) -+ -+#endif --- -2.53.0 - diff --git a/SPECS/linux/0247-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch b/SPECS/linux/0247-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch new file mode 100644 index 0000000000..b5f24c4c2f --- /dev/null +++ b/SPECS/linux/0247-SOPHGO-riscv-sg2042-errata-Replace-thead-cache-clean.patch @@ -0,0 +1,30 @@ +From fe58df34262d97f3b0d899fdff6083a4b16f88d8 Mon Sep 17 00:00:00 2001 +From: Xiaoguang Xing +Date: Mon, 22 Jan 2024 10:31:30 +0800 +Subject: [RUYI PATCH] SOPHGO: riscv: sg2042: errata: Replace thead cache clean + with flush + +FROM: https://github.com/sophgo/linux-riscv/commit/9f8fdd99aae6ae8f037ad9c80b968de7c4252a65 + +Signed-off-by: Xiaoguang Xing +Signed-off-by: Han Gao +--- + arch/riscv/errata/thead/errata.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c +index fbe46f2fa8fb..9be8c45f4531 100644 +--- a/arch/riscv/errata/thead/errata.c ++++ b/arch/riscv/errata/thead/errata.c +@@ -67,7 +67,7 @@ static bool errata_probe_mae(unsigned int stage, + * 0000000 11001 00000 000 00000 0001011 + */ + #define THEAD_INVAL_A0 ".long 0x02a5000b" +-#define THEAD_CLEAN_A0 ".long 0x0295000b" ++#define THEAD_CLEAN_A0 ".long 0x02b5000b" + #define THEAD_FLUSH_A0 ".long 0x02b5000b" + #define THEAD_SYNC_S ".long 0x0190000b" + +-- +2.53.0 + diff --git a/SPECS/linux/0248-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch b/SPECS/linux/0248-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch deleted file mode 100644 index 2f77e939b9..0000000000 --- a/SPECS/linux/0248-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch +++ /dev/null @@ -1,237 +0,0 @@ -From 79bc37b5622033ad97d95721a18d3959e32c4881 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 16 Jun 2025 10:25:31 +0800 -Subject: [PATCH 248/269] RVCK: dts: add pinctrl dtsi/dts for UltraRisc DP1000 - -The newly added dtsi/dts is used to describe the pinctrl -configuration of the UltraRisc DP1000-EVB mainboard. - -Do not involve functional changes. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/e00864f9706198f8b278551217c048a140cbe39f -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 2 +- - .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 141 ++++++++++++++++++ - .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 52 +++++++ - 3 files changed, 194 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index c27f490e2b99..ef70e28e0b65 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,2 +1,2 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-y += dp1000.dtb -+dtb-y += dp1000.dtb dp1000-evb-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -new file mode 100644 -index 000000000000..be898b6df6fb ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -0,0 +1,141 @@ -+#include -+ -+/ { -+ -+ soc { -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -new file mode 100644 -index 000000000000..5ec9a39e8c34 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -0,0 +1,52 @@ -+/* -+* SPDX-License-Identifier: GPL-2.0+ -+* -+* Copyright (c) 2019-2022 UltraRisc,Inc -+* -+*/ -+ -+#include "dp1000.dts" -+#include "dp1000-evb-pinctrl.dtsi" -+#include -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; --- -2.53.0 - diff --git a/SPECS/linux/0248-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch b/SPECS/linux/0248-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch new file mode 100644 index 0000000000..7042fed7fe --- /dev/null +++ b/SPECS/linux/0248-SOPHGO-dts-sg2044-Modify-pcie-bar-address.patch @@ -0,0 +1,102 @@ +From fdc16c4665707f0a2612f6691ed2f2b271d6c730 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Sun, 28 Dec 2025 23:02:15 +0800 +Subject: [RUYI PATCH] SOPHGO: dts: sg2044: Modify pcie bar address + +FROM: https://github.com/sophgo/linux-riscv/commit/efddc3e2d3d57b27054415afb522100e6dce8692 + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/sophgo/sg2044.dtsi | 28 +++++++++++++------------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +index 9577aae08f7f..f1377ee8e149 100644 +--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi ++++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi +@@ -36,7 +36,7 @@ pcie0: pcie@6c00000000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x00000000 0x0 0x00001000>, + <0x6c 0x00300000 0x0 0x00004000>, +- <0x48 0x00000000 0x0 0x00001000>, ++ <0x50 0x00000000 0x0 0x00001000>, + <0x6c 0x000c0000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -51,11 +51,11 @@ pcie0: pcie@6c00000000 { + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, + <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, +- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, +- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x54 0x00000000 0x54 0x00000000 0x4 0x00000000>, ++ <0x03000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>; + status = "disabled"; + + pcie_intc0: interrupt-controller { +@@ -89,8 +89,8 @@ pcie1: pcie@6c00400000 { + ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>, + <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>, +- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, +- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x44 0x00000000 0x44 0x00000000 0x4 0x00000000>, ++ <0x03000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>; + status = "disabled"; + + pcie_intc1: interrupt-controller { +@@ -106,7 +106,7 @@ pcie2: pcie@6c04000000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x04000000 0x0 0x00001000>, + <0x6c 0x04300000 0x0 0x00004000>, +- <0x58 0x00000000 0x0 0x00001000>, ++ <0x7c 0x00000000 0x0 0x00001000>, + <0x6c 0x040c0000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -121,11 +121,11 @@ pcie2: pcie@6c04000000 { + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x7c 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>, + <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>, +- <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>, +- <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x7d 0x00000000 0x7d 0x00000000 0x1 0x00000000>, ++ <0x03000000 0x7c 0x80000000 0x7c 0x80000000 0x0 0x80000000>; + status = "disabled"; + + pcie_intc2: interrupt-controller { +@@ -141,7 +141,7 @@ pcie3: pcie@6c04400000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x04400000 0x0 0x00001000>, + <0x6c 0x04700000 0x0 0x00004000>, +- <0x50 0x00000000 0x0 0x00001000>, ++ <0x78 0x00000000 0x0 0x00001000>, + <0x6c 0x04780000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; +@@ -156,11 +156,11 @@ pcie3: pcie@6c04400000 { + <0 0 0 3 &pcie_intc3 2>, + <0 0 0 4 &pcie_intc3 3>; + msi-parent = <&msi>; +- ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, ++ ranges = <0x01000000 0x0 0x00000000 0x78 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>, + <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>, +- <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>, +- <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>; ++ <0x43000000 0x79 0x00000000 0x79 0x00000000 0x1 0x00000000>, ++ <0x03000000 0x78 0x80000000 0x78 0x80000000 0x0 0x80000000>; + status = "disabled"; + + pcie_intc3: interrupt-controller { +-- +2.53.0 + diff --git a/SPECS/linux/0249-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch b/SPECS/linux/0249-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch new file mode 100644 index 0000000000..c584c9090f --- /dev/null +++ b/SPECS/linux/0249-REVYSR-dt-bindings-net-ultrarisc-dp1000-gmac-Add-sup.patch @@ -0,0 +1,131 @@ +From 58749e22f9541ed5cc332114d1e8239e9276fdc0 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Fri, 24 Oct 2025 15:59:17 +0800 +Subject: [RUYI PATCH] REVYSR: dt-bindings: net: ultrarisc,dp1000-gmac: Add + support for Ultrarisc DP1000 GMAC + +The GMAC IP on DP1000 is a standard Synopsys DesignWare MAC +(version 5.10a). + +Add necessary compatible string for this device. + +Signed-off-by: Han Gao +Signed-off-by: Han Gao +FROM: https://github.com/RevySR/linux/commit/5eda7fb5c988909f44edab38678cd124a9a5b98f +Signed-off-by: Han Gao +--- + .../devicetree/bindings/net/snps,dwmac.yaml | 1 + + .../bindings/net/ultrarisc,dp1000-gmac.yaml | 89 +++++++++++++++++++ + 2 files changed, 90 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml + +diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +index 98ebb6276bc6..44ea20deb863 100644 +--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml ++++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +@@ -118,6 +118,7 @@ properties: + - starfive,jh7110-dwmac + - tesla,fsd-ethqos + - thead,th1520-gmac ++ - ultrarisc,dp1000-gmac + + reg: + minItems: 1 +diff --git a/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml +new file mode 100644 +index 000000000000..ace5c4058cc9 +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/ultrarisc,dp1000-gmac.yaml +@@ -0,0 +1,89 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/ultrarisc,dp1000-gmac.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Ultrarisc dp1000 glue layer ++ ++maintainers: ++ - Han Gao ++ ++select: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - ultrarisc,dp1000-gmac ++ required: ++ - compatible ++ ++properties: ++ compatible: ++ oneOf: ++ - items: ++ - const: ultrarisc,dp1000-gmac ++ - const: snps,dwmac-5.10a ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: GMAC main clock ++ - description: PTP clock ++ - description: TX clock ++ ++ clock-names: ++ items: ++ - const: stmmaceth ++ ++ dma-noncoherent: true ++ ++ interrupts: ++ maxItems: 1 ++ ++ interrupt-names: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - interrupts ++ - interrupt-names ++ ++allOf: ++ - $ref: snps,dwmac.yaml# ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ ++ ethernet1@38000000 { ++ clocks = <&csr_clk>; ++ clock-names = "stmmaceth"; ++ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; ++ interrupt-parent = <0x01>; ++ interrupts = <84>; ++ interrupt-names = "macirq"; ++ reg = <0x00 0x38000000 0x00 0x1000000>; ++ local-mac-address = [ff ff ff ff ff ff]; ++ phy-mode = "rgmii"; ++ max-speed = <1000>; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ phy-handle = <&phy0>; ++ mdio { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ compatible = "snps,dwmac-mdio"; ++ phy0: phy@0{ ++ reg = <0x00>; ++ status = "okay"; ++ }; ++ }; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux/0249-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch b/SPECS/linux/0249-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch deleted file mode 100644 index ff26ec489e..0000000000 --- a/SPECS/linux/0249-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch +++ /dev/null @@ -1,251 +0,0 @@ -From 3fc1facd2fff9d8ed420074a8d3815114d5e74ff Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 4 Sep 2025 16:31:30 +0800 -Subject: [PATCH 249/269] RVCK: riscv: dp1000: dts: add the dts of UltraRISC - dp1000-mo-v1 board - -adds the necessary device tree files for the UltraRISC -dp1000-mo-v1 board. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/1186c972f5908717ab186cea67403c74ea03cde1 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 4 +- - .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 146 ++++++++++++++++++ - .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 60 +++++++ - 3 files changed, 209 insertions(+), 1 deletion(-) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index ef70e28e0b65..9eac56549340 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,2 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-y += dp1000.dtb dp1000-evb-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -new file mode 100644 -index 000000000000..e82fcf2901ab ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -@@ -0,0 +1,146 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+ -+/ { -+ -+ soc { -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -new file mode 100644 -index 000000000000..a74714629566 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -0,0 +1,60 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include "dp1000.dts" -+#include "dp1000-mo-pinctrl.dtsi" -+#include -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ -+ rtc@32 { -+ compatible = "whwave,sd3078"; -+ reg = <0x32>; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; --- -2.53.0 - diff --git a/SPECS/linux/0250-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch b/SPECS/linux/0250-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch new file mode 100644 index 0000000000..f9cdec05bc --- /dev/null +++ b/SPECS/linux/0250-REVYSR-net-stmmac-add-support-for-dwmac-5.10a.patch @@ -0,0 +1,27 @@ +From 409d6b10f330918412e65bb62c6b6bff7db7f5ad Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Fri, 24 Oct 2025 17:00:37 +0800 +Subject: [RUYI PATCH] REVYSR: net: stmmac: add support for dwmac 5.10a + +Signed-off-by: Han Gao +FROM: https://github.com/RevySR/linux/commit/5bc2d2af06ccd13675b8d4751226fb56bc8ee6df +Signed-off-by: Han Gao +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c +index b9218c07eb6b..a27b2bc177af 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c +@@ -59,6 +59,7 @@ static const struct of_device_id dwmac_generic_match[] = { + { .compatible = "snps,dwmac-3.72a"}, + { .compatible = "snps,dwmac-4.00"}, + { .compatible = "snps,dwmac-4.10a"}, ++ { .compatible = "snps,dwmac-5.10a"}, + { .compatible = "snps,dwmac"}, + { .compatible = "snps,dwxgmac-2.10"}, + { .compatible = "snps,dwxgmac"}, +-- +2.53.0 + diff --git a/SPECS/linux/0250-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch b/SPECS/linux/0250-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch deleted file mode 100644 index 108c6b470e..0000000000 --- a/SPECS/linux/0250-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch +++ /dev/null @@ -1,111 +0,0 @@ -From fdb3b2a9b77876acca3aa6102e3162c0054b94f5 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 9 Sep 2025 15:45:52 +0800 -Subject: [PATCH 250/269] RVCK: riscv: dp1000: dts: Move mmc0 node from SoC to - board DTS - -The mmc0 node (mmc-spi-slot) is a board-level peripheral -specific to the UltraRISC DP1000 EVB V1.0, not part of the -base SoC. Move it from the SoC-level dp1000.dts to the -board-specific dp1000-evb-v1.dts to maintain proper device -tree hierarchy between SoC core and board-specific components. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/c719099661103786c877036840568c38f3d083a9 -Signed-off-by: Han Gao ---- - .../boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 9 +++++++-- - arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 16 +++++++++++----- - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 15 +++------------ - 3 files changed, 21 insertions(+), 19 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -index be898b6df6fb..e82fcf2901ab 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -1,3 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ - #include - - / { -@@ -63,8 +68,8 @@ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) - - uart0_pins: uart0_pins { - pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -+ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) - >; - - pinconf-pins = < -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 5ec9a39e8c34..34622a33e63b 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -1,9 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0 - /* --* SPDX-License-Identifier: GPL-2.0+ --* --* Copyright (c) 2019-2022 UltraRisc,Inc --* --*/ -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ - - #include "dp1000.dts" - #include "dp1000-evb-pinctrl.dtsi" -@@ -27,6 +25,14 @@ &i2c3 { - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; -+ -+ mmc0: mmc@0 { -+ compatible = "mmc-spi-slot"; -+ spi-max-frequency = <15625000>; -+ reg = <0x00>; -+ voltage-ranges = <3300 3300>; -+ disable-wp; -+ }; - }; - - &spi1 { -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 3eb811f73aa8..23a983d6a4c8 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -1,9 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0 - /* --* SPDX-License-Identifier: GPL-2.0+ --* --* Copyright (c) 2019-2022 UltraRisc,Inc --* --*/ -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ - - /dts-v1/; - -@@ -261,13 +259,6 @@ spi0: spi@20320000 { - clock-names = "device_clk"; - num-cs = <3>; - spi-max-frequency = <62500000>; -- mmc0: mmc@0 { -- compatible = "mmc-spi-slot"; -- spi-max-frequency = <15625000>; -- reg = <0x00>; -- voltage-ranges = <3300 3300>; -- disable-wp; -- }; - }; - - spi1: spi@20420000 { --- -2.53.0 - diff --git a/SPECS/linux/0251-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch b/SPECS/linux/0251-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch deleted file mode 100644 index 27f2c8ef7f..0000000000 --- a/SPECS/linux/0251-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch +++ /dev/null @@ -1,78 +0,0 @@ -From ee4f735ee87fccccab84490e56b104d3e96cabe5 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 18 Sep 2025 10:44:01 +0800 -Subject: [PATCH 251/269] RVCK: riscv: dp1000: plic: add plic early init - supports - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - -------------------------------------------------- - -Add PLIC early init supports and remove invalid -timer nodes in dp1000.dts. - -Signed-off-by: Jia Wang -From: https://github.com/RVCK-Project/rvck/commit/9e4cfbdf46fad772cc002c53b9e295cda600e9c5 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 25 ++---------------------- - drivers/irqchip/irq-sifive-plic.c | 1 + - 2 files changed, 3 insertions(+), 23 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 23a983d6a4c8..4a2dae602693 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -164,6 +164,7 @@ device_clk: device_clk { - clock-frequency = <62500000>; - #clock-cells = <0>; - }; -+ - csr_clk: csr_clk { - compatible = "fixed-clock"; - clock-frequency = <250000000>; -@@ -333,29 +334,7 @@ wdt0: watchdog@20210000 { - interrupts = <33>; - clocks = <&device_clk>; - }; -- -- timer0: timer@20220000 { -- compatible = "snps,dw-apb-timer"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x20220000 0x0 0x100>; -- clocks = <&device_clk>; -- interrupt-parent = <0x01>; -- interrupts = <35>; -- status = "okay"; -- }; -- -- timer1: timer@20230000 { -- compatible = "snps,dw-apb-timer"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x20230000 0x0 0x100>; -- clocks = <&device_clk>; -- interrupt-parent = <0x01>; -- interrupts = <36>; -- status = "okay"; -- }; -- -+ - gpio: gpio@20200000 { - compatible = "snps,dw-apb-gpio"; - #address-cells = <1>; -diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c -index 5b0dac104814..bb64c27d76ca 100644 ---- a/drivers/irqchip/irq-sifive-plic.c -+++ b/drivers/irqchip/irq-sifive-plic.c -@@ -846,3 +846,4 @@ static int __init plic_early_probe(struct device_node *node, - } - - IRQCHIP_DECLARE(riscv, "allwinner,sun20i-d1-plic", plic_early_probe); -+IRQCHIP_DECLARE(ultrarisc_dp1000_plic, "ultrarisc,dp1000-plic", plic_early_probe); --- -2.53.0 - diff --git a/SPECS/linux/0251-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch b/SPECS/linux/0251-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch new file mode 100644 index 0000000000..4fffb16aa4 --- /dev/null +++ b/SPECS/linux/0251-RVCK-riscv-dts-add-dp1000.dts-for-UltraRIsc-DP1000-S.patch @@ -0,0 +1,578 @@ +From 5f377998b2865b1ac0da8c016873120669c1b673 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 16 May 2025 11:12:26 +0800 +Subject: [RUYI PATCH] RVCK: riscv:dts: add dp1000.dts for UltraRIsc DP1000 SoC + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/8fa6586e8607e8f2b9bbf701a6cf282b29dac1f7 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/Makefile | 1 + + arch/riscv/boot/dts/ultrarisc/Makefile | 2 + + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 536 +++++++++++++++++++++++ + 3 files changed, 539 insertions(+) + create mode 100644 arch/riscv/boot/dts/ultrarisc/Makefile + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000.dts + +diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile +index 69d8751fb17c..702882974251 100644 +--- a/arch/riscv/boot/dts/Makefile ++++ b/arch/riscv/boot/dts/Makefile +@@ -12,3 +12,4 @@ subdir-y += spacemit + subdir-y += starfive + subdir-y += tenstorrent + subdir-y += thead ++subdir-y += ultrarisc +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +new file mode 100644 +index 000000000000..c27f490e2b99 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtb-y += dp1000.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +new file mode 100644 +index 000000000000..3eb811f73aa8 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +@@ -0,0 +1,536 @@ ++/* ++* SPDX-License-Identifier: GPL-2.0+ ++* ++* Copyright (c) 2019-2022 UltraRisc,Inc ++* ++*/ ++ ++/dts-v1/; ++ ++/ { ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ compatible = "ultrarisc,dp1000"; ++ model = "ultrarisc,dp1000"; ++ ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS1,115200"; ++ stdout-path = &uart1; ++ }; ++ ++ cpus { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ timebase-frequency = <10000000>; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ reg = <0x00>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu0_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ reg = <0x1>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu1_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu2: cpu@2 { ++ device_type = "cpu"; ++ reg = <0x2>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu2_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu3: cpu@3 { ++ device_type = "cpu"; ++ reg = <0x3>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu3_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu4: cpu@4 { ++ device_type = "cpu"; ++ reg = <0x10>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu4_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu5: cpu@5 { ++ device_type = "cpu"; ++ reg = <0x11>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu5_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu6: cpu@6 { ++ device_type = "cpu"; ++ reg = <0x12>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ ++ clock-frequency = <2000000000>; ++ ++ cpu6_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ cpu7: cpu@7 { ++ device_type = "cpu"; ++ reg = <0x13>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdcbh"; ++ mmu-type = "riscv,sv48"; ++ clock-frequency = <2000000000>; ++ cpu7_intc:interrupt-controller { ++ #address-cells = <0x01>; ++ interrupt-controller; ++ compatible = "riscv,cpu-intc"; ++ #interrupt-cells = <0x01>; ++ }; ++ }; ++ }; ++ ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x00 0x80000000 0x4 0x00000000>; ++ }; ++ ++ soc { ++ #address-cells = <0x02>; ++ #size-cells = <0x02>; ++ compatible = "simple-bus"; ++ ranges; ++ ++ clocks { ++ compatible = "simple-bus"; ++ u-boot,dm-pre-reloc; ++ device_clk: device_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <62500000>; ++ #clock-cells = <0>; ++ }; ++ csr_clk: csr_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <250000000>; ++ #clock-cells = <0>; ++ }; ++ }; ++ ++ clint: clint@8000000 { ++ compatible = "riscv,clint0"; ++ interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, ++ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, ++ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, ++ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, ++ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, ++ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, ++ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, ++ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; ++ reg = <0x00 0x8000000 0x00 0x100000>; ++ }; ++ ++ plic: plic@9000000 { ++ #interrupt-cells = <1>; ++ #address-cells = <0>; ++ phandle = <0x01>; ++ compatible = "ultrarisc,dp1000-plic"; ++ interrupt-controller; ++ interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, ++ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, ++ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, ++ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, ++ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, ++ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, ++ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, ++ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; ++ reg = <0x00 0x9000000 0x00 0x4000000>; ++ riscv,max-priority = <0x07>; ++ riscv,ndev = <160>; ++ }; ++ ++ uart0: serial@20300000 { ++ interrupt-parent = <0x01>; ++ interrupts = <17>; ++ clock-frequency = <62500000>; ++ current-speed = <115200>; ++ reg = <0x00 0x20300000 0x00 0x10000>; ++ compatible = "ultrarisc,dp1000-uart","ns16550"; ++ reg-offset = <0x0>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart1: serial@20310000 { ++ interrupt-parent = <0x01>; ++ interrupts = <18>; ++ clock-frequency = <62500000>; ++ current-speed = <115200>; ++ reg = <0x00 0x20310000 0x00 0x10000>; ++ compatible = "ultrarisc,dp1000-uart","ns16550"; ++ reg-offset = <0x0>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart2: serial@20400000 { ++ interrupt-parent = <0x01>; ++ interrupts = <25>; ++ clock-frequency = <62500000>; ++ current-speed = <115200>; ++ reg = <0x00 0x20400000 0x00 0x10000>; ++ compatible = "ultrarisc,dp1000-uart","ns16550"; ++ reg-offset = <0x0>; ++ reg-shift = <0x02>; ++ }; ++ ++ uart3: serial@20410000 { ++ interrupt-parent = <0x01>; ++ interrupts = <26>; ++ clock-frequency = <62500000>; ++ current-speed = <115200>; ++ reg = <0x00 0x20410000 0x00 0x10000>; ++ compatible = "ultrarisc,dp1000-uart","ns16550"; ++ reg-offset = <0x0>; ++ reg-shift = <0x02>; ++ }; ++ ++ spi0: spi@20320000 { ++ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; ++ status = "okay"; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ reg = <0x0 0x20320000 0x0 0x1000>; ++ interrupt-parent = <0x01>; ++ interrupts = <19>; ++ clocks = <&device_clk>; ++ clock-names = "device_clk"; ++ num-cs = <3>; ++ spi-max-frequency = <62500000>; ++ mmc0: mmc@0 { ++ compatible = "mmc-spi-slot"; ++ spi-max-frequency = <15625000>; ++ reg = <0x00>; ++ voltage-ranges = <3300 3300>; ++ disable-wp; ++ }; ++ }; ++ ++ spi1: spi@20420000 { ++ compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; ++ status = "okay"; ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ reg = <0x0 0x20420000 0x0 0x1000>; ++ interrupt-parent = <0x01>; ++ interrupts = <27>; ++ clocks = <&device_clk>; ++ clock-names = "device_clk"; ++ num-cs = <3>; ++ spi-max-frequency = <62500000>; ++ }; ++ ++ i2c0: i2c@20330000{ ++ compatible = "snps,designware-i2c"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20330000 0x0 0x100>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <20>; ++ }; ++ ++ i2c1: i2c@20340000{ ++ compatible = "snps,designware-i2c"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20340000 0x0 0x100>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <21>; ++ }; ++ ++ i2c2: i2c@20430000{ ++ compatible = "snps,designware-i2c"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20430000 0x0 0x100>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <28>; ++ }; ++ ++ i2c3: i2c@20440000{ ++ compatible = "snps,designware-i2c"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20440000 0x0 0x100>; ++ clock-frequency = <400000>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <29>; ++ }; ++ ++ wdt0: watchdog@20210000 { ++ compatible = "snps,dw-wdt"; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20210000 0x0 0x100>; ++ interrupt-parent = <0x01>; ++ interrupts = <33>; ++ clocks = <&device_clk>; ++ }; ++ ++ timer0: timer@20220000 { ++ compatible = "snps,dw-apb-timer"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20220000 0x0 0x100>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <35>; ++ status = "okay"; ++ }; ++ ++ timer1: timer@20230000 { ++ compatible = "snps,dw-apb-timer"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20230000 0x0 0x100>; ++ clocks = <&device_clk>; ++ interrupt-parent = <0x01>; ++ interrupts = <36>; ++ status = "okay"; ++ }; ++ ++ gpio: gpio@20200000 { ++ compatible = "snps,dw-apb-gpio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20200000 0x0 0x1000>; ++ clocks = <&csr_clk>, <&device_clk>; ++ clock-names = "bus", "db"; ++ status = "okay"; ++ ++ porta: gpio-port@0 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <16>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupt-parent = <0x01>; ++ interrupts = <34>; ++ }; ++ ++ portb: gpio-port@1 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <1>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ }; ++ ++ portc: gpio-port@2 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <2>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ }; ++ ++ portd: gpio-port@3 { ++ compatible = "snps,dw-apb-gpio-port"; ++ reg = <3>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <8>; ++ }; ++ }; ++ ++ ethernet1@38000000 { ++ clocks = <&csr_clk>; ++ clock-names = "stmmaceth"; ++ compatible = "ultrarisc,dp1000-gmac", "snps,dwmac-5.10a"; ++ interrupt-parent = <0x01>; ++ interrupts = <84>; ++ interrupt-names = "macirq"; ++ reg = <0x00 0x38000000 0x00 0x1000000>; ++ local-mac-address = [ff ff ff ff ff ff]; ++ phy-mode = "rgmii"; ++ max-speed = <1000>; ++ snps,txpbl = <8>; ++ snps,rxpbl = <8>; ++ phy-handle = <&phy0>; ++ mdio { ++ #address-cells = <0x01>; ++ #size-cells = <0x00>; ++ compatible = "snps,dwmac-mdio"; ++ phy0: phy@0{ ++ phandle = <0x04>; ++ reg = <0x00>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ dmac: dma-controller@39000000 { ++ compatible = "snps,axi-dma-1.01a"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x39000000 0x0 0x400>; ++ clocks = <&device_clk>, <&device_clk>; ++ clock-names = "core-clk", "cfgr-clk"; ++ interrupt-parent = <0x01>; ++ interrupts = <152>; ++ #dma-cells = <1>; ++ dma-channels = <8>; ++ snps,dma-masters = <1>; ++ snps,data-width = <4>; ++ snps,block-size = <512 512 512 512 512 512 512 512>; ++ snps,priority = <0 1 2 3 4 5 6 7>; ++ snps,axi-max-burst-len = <256>; ++ }; ++ ++ pcie_x16: pcie@21000000 { ++ compatible = "ultrarisc,dw-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x21000000 0x0 0x01000000>, /* IP registers */ ++ <0x0 0x4fff0000 0x0 0x00010000>; /* Configuration space */ ++ reg-names = "dbi", "config"; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <16>; ++ ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ ++ <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ ++ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ max-link-speed = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <43>, <44>, <45>, <46>, <47>, <48>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, ++ <0x0 0x0 0x0 0x2 &plic 45>, ++ <0x0 0x0 0x0 0x3 &plic 46>, ++ <0x0 0x0 0x0 0x4 &plic 47>; ++ }; ++ ++ pcie_x4a: pcie@23000000 { ++ compatible = "ultrarisc,dw-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x23000000 0x0 0x01000000>, /* IP registers */ ++ <0x0 0x6fff0000 0x0 0x00010000>; /* Configuration space */ ++ reg-names = "dbi", "config"; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <4>; ++ ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ ++ <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ ++ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ max-link-speed = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <63>, <64>, <65>, <66>, <67>, <68>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, ++ <0x0 0x0 0x0 0x2 &plic 65>, ++ <0x0 0x0 0x0 0x3 &plic 66>, ++ <0x0 0x0 0x0 0x4 &plic 67>; ++ }; ++ ++ pcie_x4b: pcie@24000000 { ++ compatible = "ultrarisc,dw-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x24000000 0x0 0x01000000>, /* IP registers */ ++ <0x0 0x7fff0000 0x0 0x00010000>; /* Configuration space */ ++ reg-names = "dbi", "config"; ++ device_type = "pci"; ++ dma-coherent; ++ bus-range = <0x0 0xff>; ++ num-lanes = <4>; ++ ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ ++ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ ++ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ max-link-speed = <4>; ++ interrupt-parent = <&plic>; ++ interrupts = <73>, <74>, <75>, <76>, <77>, <78>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, ++ <0x0 0x0 0x0 0x2 &plic 75>, ++ <0x0 0x0 0x0 0x3 &plic 76>, ++ <0x0 0x0 0x0 0x4 &plic 77>; ++ }; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux/0252-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch b/SPECS/linux/0252-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch new file mode 100644 index 0000000000..010a37dd92 --- /dev/null +++ b/SPECS/linux/0252-RVCK-pinctrl-add-pinctrl-dirver-for-UltraRisc-DP1000.patch @@ -0,0 +1,880 @@ +From 00988d4b3f724597782b992ad30fa26b1e1c9a1c Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Fri, 17 Jan 2025 19:34:48 +0800 +Subject: [RUYI PATCH] RVCK: pinctrl: add pinctrl dirver for UltraRisc DP1000 + +support pinmux and pinconf for UltraRisc DP1000 SoC + +Signed-off-by: Jia Wang +Signed-off-by: Yanteng Si +FROM: https://github.com/RVCK-Project/rvck/commit/2fdd7d95fb0408b67353ea82e378773ebfe39ade +Signed-off-by: Han Gao +--- + drivers/pinctrl/Kconfig | 1 + + drivers/pinctrl/Makefile | 1 + + drivers/pinctrl/ultrarisc/Kconfig | 20 + + drivers/pinctrl/ultrarisc/Makefile | 4 + + .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 122 +++++ + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 503 ++++++++++++++++++ + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 78 +++ + .../dt-bindings/pinctrl/ur-dp1000-pinctrl.h | 65 +++ + 8 files changed, 794 insertions(+) + create mode 100644 drivers/pinctrl/ultrarisc/Kconfig + create mode 100644 drivers/pinctrl/ultrarisc/Makefile + create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c + create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c + create mode 100644 drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h + create mode 100644 include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h + +diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig +index afecd9407f53..bf65ef30394a 100644 +--- a/drivers/pinctrl/Kconfig ++++ b/drivers/pinctrl/Kconfig +@@ -720,5 +720,6 @@ source "drivers/pinctrl/ti/Kconfig" + source "drivers/pinctrl/uniphier/Kconfig" + source "drivers/pinctrl/visconti/Kconfig" + source "drivers/pinctrl/vt8500/Kconfig" ++source "drivers/pinctrl/ultrarisc/Kconfig" + + endif +diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile +index f7d5d5f76d0c..4df3e52518ea 100644 +--- a/drivers/pinctrl/Makefile ++++ b/drivers/pinctrl/Makefile +@@ -98,3 +98,4 @@ obj-y += ti/ + obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ + obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ + obj-$(CONFIG_ARCH_VT8500) += vt8500/ ++obj-$(CONFIG_ARCH_ULTRARISC) += ultrarisc/ +diff --git a/drivers/pinctrl/ultrarisc/Kconfig b/drivers/pinctrl/ultrarisc/Kconfig +new file mode 100644 +index 000000000000..e4db80843bea +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/Kconfig +@@ -0,0 +1,20 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config PINCTRL_ULTRARISC ++ bool ++ depends on OF ++ select PINMUX ++ select GENERIC_PINCTRL_GROUPS ++ select GENERIC_PINCONF ++ select GENERIC_PINMUX_FUNCTIONS ++ select GPIOLIB ++ select IRQ_DOMAIN_HIERARCHY ++ select MFD_SYSCON ++ ++config PINCTRL_ULTRARISC_DP1000 ++ tristate "Pinctrl driver of UltraRisc DP1000" ++ select PINCTRL_ULTRARISC ++ depends on OF && HAS_IOMEM ++ help ++ This driver configures the UltraRisc DP1000 SoC's pinctrl ++ subsystem. +diff --git a/drivers/pinctrl/ultrarisc/Makefile b/drivers/pinctrl/ultrarisc/Makefile +new file mode 100644 +index 000000000000..5bf3f449d59b +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/Makefile +@@ -0,0 +1,4 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++obj-$(CONFIG_PINCTRL_ULTRARISC) += pinctrl-ultrarisc.o ++obj-$(CONFIG_PINCTRL_ULTRARISC_DP1000) += pinctrl-ultrarisc-dp1000.o +\ No newline at end of file +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +new file mode 100644 +index 000000000000..217f671fe63a +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +@@ -0,0 +1,122 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* UltraRisc DP1000 pinctrl driver ++ * ++ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../pinctrl-utils.h" ++#include "../pinmux.h" ++#include "../core.h" ++#include "../devicetree.h" ++ ++#include "pinctrl-ultrarisc.h" ++ ++static const struct pinctrl_pin_desc ur_dp1000_pins[] = { ++ // PA ++ PINCTRL_PIN(0, "PA0"), ++ PINCTRL_PIN(1, "PA1"), ++ PINCTRL_PIN(2, "PA2"), ++ PINCTRL_PIN(3, "PA3"), ++ PINCTRL_PIN(4, "PA4"), ++ PINCTRL_PIN(5, "PA5"), ++ PINCTRL_PIN(6, "PA6"), ++ PINCTRL_PIN(7, "PA7"), ++ PINCTRL_PIN(8, "PA8"), ++ PINCTRL_PIN(9, "PA9"), ++ PINCTRL_PIN(10, "PA10"), ++ PINCTRL_PIN(11, "PA11"), ++ PINCTRL_PIN(12, "PA12"), ++ PINCTRL_PIN(13, "PA13"), ++ PINCTRL_PIN(14, "PA14"), ++ PINCTRL_PIN(15, "PA15"), ++ // PB ++ PINCTRL_PIN(16, "PB0"), ++ PINCTRL_PIN(17, "PB1"), ++ PINCTRL_PIN(18, "PB2"), ++ PINCTRL_PIN(19, "PB3"), ++ PINCTRL_PIN(20, "PB4"), ++ PINCTRL_PIN(21, "PB5"), ++ PINCTRL_PIN(22, "PB6"), ++ PINCTRL_PIN(23, "PB7"), ++ // PC ++ PINCTRL_PIN(24, "PC0"), ++ PINCTRL_PIN(25, "PC1"), ++ PINCTRL_PIN(26, "PC2"), ++ PINCTRL_PIN(27, "PC3"), ++ PINCTRL_PIN(28, "PC4"), ++ PINCTRL_PIN(29, "PC5"), ++ PINCTRL_PIN(30, "PC6"), ++ PINCTRL_PIN(31, "PC7"), ++ // PD ++ PINCTRL_PIN(32, "PD0"), ++ PINCTRL_PIN(33, "PD1"), ++ PINCTRL_PIN(34, "PD2"), ++ PINCTRL_PIN(35, "PD3"), ++ PINCTRL_PIN(36, "PD4"), ++ PINCTRL_PIN(37, "PD5"), ++ PINCTRL_PIN(38, "PD6"), ++ PINCTRL_PIN(39, "PD7"), ++ // LPC ++ PINCTRL_PIN(40, "LPC0"), ++ PINCTRL_PIN(41, "LPC1"), ++ PINCTRL_PIN(42, "LPC2"), ++ PINCTRL_PIN(43, "LPC3"), ++ PINCTRL_PIN(44, "LPC4"), ++ PINCTRL_PIN(45, "LPC5"), ++ PINCTRL_PIN(46, "LPC6"), ++ PINCTRL_PIN(47, "LPC7"), ++ PINCTRL_PIN(48, "LPC8"), ++ PINCTRL_PIN(49, "LPC9"), ++ PINCTRL_PIN(50, "LPC10"), ++ PINCTRL_PIN(51, "LPC11"), ++ PINCTRL_PIN(52, "LPC12"), ++}; ++ ++static struct ur_pinctrl_match_data ur_dp1000_match_data = { ++ .pins = ur_dp1000_pins, ++ .npins = ARRAY_SIZE(ur_dp1000_pins), ++ .offset = 0x2c0, ++ .ports = { ++ {"A", 16, 0x2c0, 0x310}, ++ {"B", 8, 0x2c4, 0x318}, ++ {"C", 8, 0x2c8, 0x31c}, ++ {"D", 8, 0x2cc, 0x320}, ++ {"LPC", 13, 0x2d0, 0x324}, ++ }, ++}; ++ ++enum ur_dp1000_port_list { ++ PORT_A = 0, ++ PORT_B, ++ PORT_C, ++ PORT_D, ++ PORT_LPC ++}; ++ ++ ++static const struct of_device_id ur_pinctrl_of_match[] = { ++ { .compatible = "ultrarisc,dp1000-pinctrl", .data = &ur_dp1000_match_data, }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ur_pinctrl_of_match); ++ ++static struct platform_driver ur_pinctrl_driver = { ++ .driver = { ++ .name = "ultrarisc-pinctrl-dp1000", ++ .of_match_table = ur_pinctrl_of_match, ++ }, ++ .probe = ur_pinctrl_probe, ++ .remove = ur_pinctrl_remove, ++}; ++ ++module_platform_driver(ur_pinctrl_driver); +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +new file mode 100644 +index 000000000000..667d59e0ac6e +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +@@ -0,0 +1,503 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* UltraRisc pinctrl driver ++ * ++ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../pinctrl-utils.h" ++#include "../pinmux.h" ++#include "../core.h" ++#include "../devicetree.h" ++ ++#include "pinctrl-ultrarisc.h" ++ ++static int ur_pin_to_desc(struct pinctrl_dev *pctldev, struct ur_pin_val *pin_val) ++{ ++ int index = 0; ++ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ const struct ur_pinctrl_match_data *ur_match_data = ur_pinctrl->match_data; ++ ++ for (int i = 0; i < pin_val->port; i++) ++ index += ur_match_data->ports[i].npins; ++ index += pin_val->pin; ++ dev_dbg(pctldev->dev, "port %d pin %d index %d\n", pin_val->port, pin_val->pin, index); ++ return index; ++} ++ ++static int ur_subnode_to_pin(struct pinctrl_dev *pctldev, ++ const char *name, ++ enum pinctrl_map_type type, ++ struct device_node *np, ++ int **pins, ++ struct ur_pin_val **pin_val, ++ int *pin_num) ++{ ++ struct ur_pin_val *pin_vals; ++ int rows; ++ int ret = -EINVAL; ++ int *group_pins; ++ const char **pgnames; ++ ++ dev_dbg(pctldev->dev, "pinctrl node %s\n", np->name); ++ rows = pinctrl_count_index_with_args(np, name); ++ if (rows < 0) { ++ dev_err(pctldev->dev, "%s count is invalid %d\n", name, rows); ++ return rows; ++ } ++ ++ pin_vals = devm_kcalloc(pctldev->dev, rows, sizeof(*pin_vals), GFP_KERNEL); ++ if (!pin_vals) { ++ return -ENOMEM; ++ } ++ ++ group_pins = devm_kcalloc(pctldev->dev, rows, sizeof(*group_pins), GFP_KERNEL); ++ if (!group_pins) { ++ ret = -ENOMEM; ++ goto free_pin_vals; ++ } ++ ++ pgnames = devm_kzalloc(pctldev->dev, sizeof(*pgnames), GFP_KERNEL); ++ if (!pgnames) { ++ ret = -ENOMEM; ++ goto free_pins; ++ } ++ ++ for (int i = 0; i < rows; i++) { ++ struct of_phandle_args pin_args; ++ ++ ret = pinctrl_parse_index_with_args(np, name, i, &pin_args); ++ if (ret) { ++ dev_err(pctldev->dev, "parse args of %s index %d failed\n", name, i); ++ goto free_pgnames; ++ } ++ ++ if (pin_args.args_count < 3) { ++ dev_err(pctldev->dev, "invalid args_count(%d) of %s index %d/%d\n", ++ pin_args.args_count, name, i, rows); ++ ret = -EINVAL; ++ goto free_pgnames; ++ } ++ pin_vals[i].port = pin_args.args[0]; ++ pin_vals[i].pin = pin_args.args[1]; ++ pin_vals[i].mode = pin_args.args[2]; ++ ++ dev_dbg(pctldev->dev, "found a pinctrl: port=%d pin=%d val=0x%x\n", ++ pin_vals[i].port, pin_vals[i].pin, pin_vals[i].mode); ++ ++ group_pins[i] = ur_pin_to_desc(pctldev, &pin_vals[i]); ++ } ++ ++ dev_dbg(pctldev->dev, "get an pinmux of %s\n", np->name); ++ ++ ret = pinctrl_generic_add_group(pctldev, np->name, group_pins, rows, pin_vals); ++ if (ret < 0) { ++ dev_err(pctldev->dev, "add group %s failed\n", np->name); ++ goto free_pgnames; ++ } ++ ++ *pgnames = np->name; ++ ret = pinmux_generic_add_function(pctldev, np->name, pgnames, 1, NULL); ++ if (ret < 0) { ++ dev_err(pctldev->dev, "add function %s failed\n", np->name); ++ goto free_group; ++ } ++ ++ dev_dbg(pctldev->dev, "add group and function of %s\n", np->name); ++ ++ *pins = group_pins; ++ *pin_val = pin_vals; ++ *pin_num = rows; ++ ++ return 0; ++ ++free_group: ++ pinctrl_generic_remove_group(pctldev, ret); ++free_pgnames: ++ devm_kfree(pctldev->dev, pgnames); ++free_pins: ++ devm_kfree(pctldev->dev, group_pins); ++free_pin_vals: ++ devm_kfree(pctldev->dev, pin_vals); ++ return ret; ++} ++ ++static int ur_pinmux_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *np, ++ struct pinctrl_map *map) ++{ ++ int ret; ++ int *pins; ++ struct ur_pin_val *pin_vals; ++ int pin_num; ++ ++ ret = ur_subnode_to_pin(pctldev, PINMUX_PROP_NAME, PIN_MAP_TYPE_MUX_GROUP, ++ np, &pins, &pin_vals, &pin_num); ++ if (ret) { ++ dev_err(pctldev->dev, "get pinmux data %s failed\n", np->name); ++ return ret; ++ } ++ ++ map->type = PIN_MAP_TYPE_MUX_GROUP; ++ map->data.mux.group = np->name; ++ map->data.mux.function = np->name; ++ ++ dev_dbg(pctldev->dev, "type=%d, mux.group=%s, mux.function=%s\n", ++ map->type, map->data.mux.group, map->data.mux.function); ++ ++ return 0; ++} ++ ++static int ur_pinconf_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *np, ++ struct pinctrl_map *map) ++{ ++ int ret; ++ int *pins; ++ struct ur_pin_val *pin; ++ int pin_num; ++ ++ ret = ur_subnode_to_pin(pctldev, PINCONF_PROP_NAME, PIN_MAP_TYPE_CONFIGS_GROUP, ++ np, &pins, &pin, &pin_num); ++ if (ret) { ++ dev_err(pctldev->dev, "get pinconf data %s failed\n", np->name); ++ return ret; ++ } ++ ++ dev_dbg(pctldev->dev, "get an pinconf of %s\n", np->name); ++ map->type = PIN_MAP_TYPE_CONFIGS_GROUP; ++ map->data.configs.group_or_pin = np->name; ++ map->data.configs.configs = (unsigned long *)pin; ++ map->data.configs.num_configs = pin_num; ++ ++ dev_dbg(pctldev->dev, "type=%d, config.group_or_pin=%s, configs.num_config=%d\n", ++ map->type, map->data.configs.group_or_pin, map->data.configs.num_configs); ++ ++ return 0; ++} ++ ++static int ur_dt_node_to_map(struct pinctrl_dev *pctldev, ++ struct device_node *np, ++ struct pinctrl_map **map, ++ unsigned int *num_maps) ++{ ++ int ret; ++ bool mux_present = false, conf_present = false; ++ struct pinctrl_map *new_map; ++ unsigned int map_num = 0, prop_count = 0; ++ ++ //device_get_named_child_node(pctldev->dev, np->name); ++ if (of_property_present(np, PINMUX_PROP_NAME)) { ++ mux_present = true; ++ prop_count++; ++ } ++ if (of_property_present(np, PINCONF_PROP_NAME)) { ++ conf_present = true; ++ prop_count++; ++ } ++ ++ if (!prop_count) { ++ dev_err(pctldev->dev, "no pinctrl node(%d) in %s\n", prop_count, np->name); ++ return -EINVAL; ++ } ++ ++ new_map = devm_kmalloc_array(pctldev->dev, prop_count, sizeof(**map), GFP_KERNEL); ++ if (!new_map) ++ return -ENOMEM; ++ ++ *map = new_map; ++ if (mux_present) { ++ ret = ur_pinmux_to_map(pctldev, np, new_map); ++ if (!ret) { ++ new_map++; ++ map_num++; ++ } ++ } ++ if (conf_present) { ++ ret = ur_pinconf_to_map(pctldev, np, new_map); ++ if (!ret) ++ map_num++; ++ } ++ ++ if (!map_num) { ++ dev_err(pctldev->dev, "no pinctrl info of %s failed\n", np->name); ++ goto free_map; ++ } ++ *num_maps = map_num; ++ ++ return 0; ++ ++free_map: ++ devm_kfree(pctldev->dev, new_map); ++ return ret; ++} ++ ++static void ur_dt_free_map(struct pinctrl_dev *pctldev, ++ struct pinctrl_map *map, unsigned int num_maps) ++{ ++ if (map) ++ devm_kfree(pctldev->dev, map); ++} ++ ++static void ur_pin_dbg_show(struct pinctrl_dev *pctldev, ++ struct seq_file *s, unsigned int offset) ++{ ++ seq_printf(s, "%s", dev_name(pctldev->dev)); ++} ++ ++static const struct pinctrl_ops ur_pinctrl_ops = { ++ .get_groups_count = pinctrl_generic_get_group_count, ++ .get_group_name = pinctrl_generic_get_group_name, ++ .get_group_pins = pinctrl_generic_get_group_pins, ++ .dt_node_to_map = ur_dt_node_to_map, ++ .dt_free_map = ur_dt_free_map, ++ .pin_dbg_show = ur_pin_dbg_show, ++}; ++ ++static int ur_set_pin_mux(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) ++{ ++ unsigned long flag; ++ //bool clear_mode = false; ++ void __iomem *reg; ++ u32 val; ++ const struct ur_port_desc *port; ++ ++ port = &pin_ctrl->match_data->ports[pin_vals->port]; ++ ++ reg = pin_ctrl->base + port->func_offset; ++ ++ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); ++ val = readl_relaxed(reg); ++ val &= ~((UR_FUNC0 | UR_FUNC1)<pin); ++ val |= (pin_vals->mode << pin_vals->pin); ++ writel_relaxed(val, reg); ++ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); ++ ++ return 0; ++} ++ ++static int ur_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, ++ unsigned int group_selector) ++{ ++ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ struct group_desc *ur_group; ++ struct ur_pin_val *pin_vals; ++ ++ dev_dbg(pctldev->dev, "set mux: func_selector=%d, group_selector=%d\n", ++ func_selector, group_selector); ++ ur_group = pinctrl_generic_get_group(pctldev, group_selector); ++ if (!ur_group) { ++ dev_err(pctldev->dev, "get group %d failed\n", group_selector); ++ return -EINVAL; ++ } ++ ++ dev_dbg(pctldev->dev, "get group %s, num_pins=%zu\n", ur_group->grp.name, ur_group->grp.npins); ++ pin_vals = ur_group->data; ++ if (!pin_vals) { ++ dev_err(pctldev->dev, "data of %s is invalid\n", ur_group->grp.name); ++ return -EINVAL; ++ } ++ ++ for (int i = 0; i < ur_group->grp.npins; i++) ++ ur_set_pin_mux(ur_pinctrl, &pin_vals[i]); ++ ++ return 0; ++} ++ ++static const struct pinmux_ops ur_pinmux_ops = { ++ .get_functions_count = pinmux_generic_get_function_count, ++ .get_function_name = pinmux_generic_get_function_name, ++ .get_function_groups = pinmux_generic_get_function_groups, ++ .set_mux = ur_set_mux, ++ .strict = true, ++}; ++ ++#define UR_CONF_BIT_PER_PIN (4) ++#define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) ++static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) ++{ ++ const struct ur_port_desc *port_desc; ++ unsigned long flag; ++ void __iomem *reg; ++ u32 val, conf; ++ ++ port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; ++ reg = pin_ctrl->base + port_desc->conf_offset; ++ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); ++ reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; ++ dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); ++ ++ conf = pin_vals->conf << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN); ++ dev_dbg(pin_ctrl->dev, "pinconf conf=0x%x\n", conf); ++ ++ raw_spin_lock_irqsave(&pin_ctrl->lock, flag); ++ val = readl_relaxed(reg); ++ val &= ~(UR_BIAS_MASK << ((pin_vals->pin % UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN)); ++ val |= conf; ++ writel_relaxed(val, reg); ++ raw_spin_unlock_irqrestore(&pin_ctrl->lock, flag); ++ dev_dbg(pin_ctrl->dev, "pinconf val=0x%x\n", val); ++ ++ return 0; ++} ++ ++static int ur_pin_config_get(struct pinctrl_dev *pctldev, ++ unsigned int pin, ++ unsigned long *config) ++{ ++ dev_dbg(pctldev->dev, "%s(%d): pin=%d\n", __func__, __LINE__, pin); ++ // TODO: this is call by pinconf-generic ++ return -EOPNOTSUPP; ++} ++ ++static int ur_pin_config_set(struct pinctrl_dev *pctldev, ++ unsigned int pin, ++ unsigned long *configs, ++ unsigned int num_configs) ++{ ++ struct ur_pin_val *pin_conf; ++ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ ++ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", ++ __func__, __LINE__, pin, num_configs); ++ pin_conf = (struct ur_pin_val *)configs; ++ for (int i = 0; i < num_configs; i++) { ++ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", ++ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); ++ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); ++ } ++ return 0; ++} ++ ++static int ur_pin_config_group_get(struct pinctrl_dev *pctldev, ++ unsigned selector, ++ unsigned long *config) ++{ ++ dev_dbg(pctldev->dev, "%s(%d): selector=%d, config=0x%lx\n", ++ __func__, __LINE__, selector, *config); ++ return -EOPNOTSUPP; ++} ++ ++static int ur_pin_config_group_set(struct pinctrl_dev *pctldev, ++ unsigned int selector, ++ unsigned long *configs, ++ unsigned int num_configs) ++{ ++ struct group_desc *ur_group; ++ struct ur_pin_val *pin_conf; ++ struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ ++ dev_dbg(pctldev->dev, "%s(%d): selector=%d, num_configs=%d\n", ++ __func__, __LINE__, selector, num_configs); ++ ur_group = pinctrl_generic_get_group(pctldev, selector); ++ if (!ur_group) { ++ dev_err(pctldev->dev, "Cannot get group by selector %d\n", selector); ++ return -EINVAL; ++ } ++ ++ dev_dbg(pctldev->dev, "get pinconf group %s\n", ur_group->grp.name); ++ pin_conf = (struct ur_pin_val *)configs; ++ for (int i = 0; i < num_configs; i++) { ++ dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", ++ i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); ++ ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); ++ } ++ return 0; ++} ++ ++static const struct pinconf_ops ur_pinconf_ops = { ++ .pin_config_get = ur_pin_config_get, ++ .pin_config_set = ur_pin_config_set, ++ .pin_config_group_get = ur_pin_config_group_get, ++ .pin_config_group_set = ur_pin_config_group_set, ++#ifdef CONFIG_GENERIC_PINCONF ++ .is_generic = true, ++#endif ++}; ++ ++int ur_pinctrl_probe(struct platform_device *pdev) ++{ ++ struct pinctrl_desc *ur_pinctrl_desc; ++ const struct ur_pinctrl_match_data *pins_data; ++ struct ur_pinctrl *ur_pinctrl; ++ int ret; ++ ++ pins_data = of_device_get_match_data(&pdev->dev); ++ if (!pins_data) ++ return -ENODEV; ++ ++ ur_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl_desc), GFP_KERNEL); ++ if (!ur_pinctrl_desc) { ++ dev_err(&pdev->dev, "pinctrl desc alloc failed\n"); ++ return -ENOMEM; ++ } ++ ++ ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); ++ if (!ur_pinctrl) { ++ dev_err(&pdev->dev, "pinctrl alloc failed\n"); ++ ret = -ENOMEM; ++ goto free_pinctrl_desc; ++ } ++ struct resource *res; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dev_dbg(&pdev->dev, "iomem start=0x%llx\n", res->start); ++ ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(ur_pinctrl->base)) { ++ dev_err(&pdev->dev, "get ioremap resource failed\n"); ++ ret = -EINVAL; ++ goto free_pinctrl_desc; ++ } ++ dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); ++ ur_pinctrl_desc->name = dev_name(&pdev->dev); ++ ur_pinctrl_desc->owner = THIS_MODULE; ++ ur_pinctrl_desc->pins = pins_data->pins; ++ ur_pinctrl_desc->npins = pins_data->npins; ++ ur_pinctrl_desc->pctlops = &ur_pinctrl_ops; ++ ur_pinctrl_desc->pmxops = &ur_pinmux_ops; ++ ur_pinctrl_desc->confops = &ur_pinconf_ops; ++ ++ ur_pinctrl->dev = &pdev->dev; ++ ur_pinctrl->match_data = pins_data; ++ ur_pinctrl->pctl_desc = ur_pinctrl_desc; ++ raw_spin_lock_init(&ur_pinctrl->lock); ++ mutex_init(&ur_pinctrl->mutex); ++ ++ ret = devm_pinctrl_register_and_init(&pdev->dev, ur_pinctrl_desc, ++ ur_pinctrl, &ur_pinctrl->pctl_dev); ++ if (ret) { ++ dev_err(&pdev->dev, "pinctrl register failed\n"); ++ goto free_pinctrl; ++ } ++ ++ platform_set_drvdata(pdev, ur_pinctrl); ++ ++ return pinctrl_enable(ur_pinctrl->pctl_dev); ++ ++free_pinctrl: ++ devm_kfree(&pdev->dev, ur_pinctrl); ++free_pinctrl_desc: ++ devm_kfree(&pdev->dev, ur_pinctrl_desc); ++ return ret; ++} ++ ++ ++void ur_pinctrl_remove(struct platform_device *pdev) ++{ ++ struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); ++ ++ if (ur_pinctrl->pctl_dev) ++ devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); ++} +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +new file mode 100644 +index 000000000000..eec621bf8b05 +--- /dev/null ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +@@ -0,0 +1,78 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* UltraRisc pinctrl driver ++ * ++ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#ifndef __PINCTRL_ULTRARISC_H__ ++#define __PINCTRL_ULTRARISC_H__ ++ ++#include ++#include ++ ++#define PINMUX_PROP_NAME "pinctrl-pins" ++#define PINCONF_PROP_NAME "pinconf-pins" ++ ++struct ur_pin_conf { ++ u16 pull; ++ u16 drive; ++}; ++ ++struct ur_pin_val { ++ u32 port; ++ u32 pin; ++ union { ++ u32 mode; ++ u32 conf; ++ }; ++#define UR_FUNC_DEF 0 ++#define UR_FUNC0 1 ++#define UR_FUNC1 0x10000 ++ ++#define UR_BIAS_MASK 0x0000000F ++#define UR_PULL_MASK 0x0C ++#define UR_PULL_DIS 0 ++#define UR_PULL_UP 1 ++#define UR_PULL_DOWN 2 ++#define UR_DRIVE_MASK 0x03 ++}; ++ ++struct ur_port_desc { ++ char *name; ++ u32 npins; ++ u32 func_offset; ++ u32 conf_offset; ++}; ++ ++struct ur_pinctrl_match_data { ++ const struct pinctrl_pin_desc *pins; ++ u32 npins; ++ u32 offset; ++ //u32 conf_offset[]; ++ struct ur_port_desc ports[]; ++}; ++ ++ ++struct ur_pinctrl { ++ struct device *dev; ++ struct pinctrl_dev *pctl_dev; ++ struct pinctrl_desc *pctl_desc; ++ void __iomem *base; ++ unsigned int ngroups; ++ const char **grp_names; ++ unsigned int nbanks; ++ const struct ur_pinctrl_match_data *match_data; ++ struct regmap *regmap; ++ raw_spinlock_t lock; ++ struct mutex mutex; ++ struct pinctrl_pin_desc *pins; ++ u32 npins; ++ u32 pkg; ++}; ++ ++int ur_pinctrl_probe(struct platform_device *pdev); ++void ur_pinctrl_remove(struct platform_device *pdev); ++ ++#endif +diff --git a/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h +new file mode 100644 +index 000000000000..5bec446e2411 +--- /dev/null ++++ b/include/dt-bindings/pinctrl/ur-dp1000-pinctrl.h +@@ -0,0 +1,65 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* UltraRisc DP1000 pinctrl header ++ * ++ * Copyright(C) 2025 UltraRisc Technology Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#ifndef __UR_DP1000_PINCTRL_H__ ++#define __UR_DP1000_PINCTRL_H__ ++ ++#define UR_DP1000_IOMUX_A 0x0 ++#define UR_DP1000_IOMUX_B 0x1 ++#define UR_DP1000_IOMUX_C 0x2 ++#define UR_DP1000_IOMUX_D 0x3 ++#define UR_DP1000_IOMUX_LPC 0x4 ++ ++#define UR_FUNC_DEF 0 ++#define UR_FUNC0 1 ++#define UR_FUNC1 0x10000 ++ ++/** ++ * port: 'A' 'B' 'C' ++ * Pin in the port ++ * pin: ++ * PA: 0 - 15 ++ * PB-PD: 0 - 7 ++ * func: ++ * UR_FUNC_DEF: default ++ * UR_FUNC0: func0 ++ * UR_FUNC1: func1 ++ */ ++#define UR_DP1000_IOPAD(port, pin, func) (port) (pin) (func) ++ ++/** ++ * Configure pull up/down resistor of the IO pin ++ * UR_PULL_DIS: disable pull-up and pull-down ++ * UR_PULL_UP: enable pull-up ++ * UR_PULL_DOWN: enable pull-down ++ */ ++#define UR_PULL_DIS 0 ++#define UR_PULL_UP 1 ++#define UR_PULL_DOWN 2 ++/** ++ * Configure drive strength of the IO pin ++ * UR_DRIVE_DEF: default value, reset value is 2 ++ * UR_DRIVE_0: 20mA ++ * UR_DRIVE_1: 27mA ++ * UR_DIRVE_2: 33mA ++ * UR_DRIVE_3: 40mA ++ */ ++#define UR_DRIVE_DEF 2 ++#define UR_DRIVE_0 0 ++#define UR_DRIVE_1 1 ++#define UR_DRIVE_2 2 ++#define UR_DRIVE_3 3 ++ ++/** ++ * Combine the pull-up/down resistor and drive strength ++ * pull: UR_PULL_DIS, UR_PULL_UP, UR_PULL_DOWN ++ * drive: UR_DRIVE_DEF, UR_DRIVE_0, UR_DRIVE_1, UR_DRIVE_2, UR_DRIVE_3 ++ */ ++#define UR_DP1000_BIAS(pull, drive) (((pull)<<2) + (drive)) ++ ++#endif +-- +2.53.0 + diff --git a/SPECS/linux/0252-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch b/SPECS/linux/0252-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch deleted file mode 100644 index 4c02654e58..0000000000 --- a/SPECS/linux/0252-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 6584710539bdeb262a9cc4526639d166567555b9 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Mon, 10 Nov 2025 16:11:12 +0800 -Subject: [PATCH 252/269] RVCK: riscv: dp1000: dts: Move chosen node from - common to board-specific DTS - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -This commit moves the chosen node configuration from the -common dp1000.dts file to the respective board-specific -DTS files. - -This change allows each board to specify its own console -configuration while keeping the common SoC definitions clean. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/db5745be89ee881ff18a7ded0bcff1c2f495becf -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 7 +++++++ - arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 7 +++++++ - arch/riscv/boot/dts/ultrarisc/dp1000.dts | 7 +------ - 3 files changed, 15 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 34622a33e63b..34d024a083fc 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -7,6 +7,13 @@ - #include "dp1000-evb-pinctrl.dtsi" - #include - -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS1,115200"; -+ stdout-path = &uart1; -+ }; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -index a74714629566..8c532e5b71a3 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -7,6 +7,13 @@ - #include "dp1000-mo-pinctrl.dtsi" - #include - -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS0,115200"; -+ stdout-path = &uart0; -+ }; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -index 4a2dae602693..128293c0af1f 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts -@@ -10,12 +10,7 @@ / { - #size-cells = <0x02>; - compatible = "ultrarisc,dp1000"; - model = "ultrarisc,dp1000"; -- -- chosen { -- bootargs = "earlycon=sbi console=ttyS1,115200"; -- stdout-path = &uart1; -- }; -- -+ - cpus { - #address-cells = <0x01>; - #size-cells = <0x00>; --- -2.53.0 - diff --git a/SPECS/linux/0253-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch b/SPECS/linux/0253-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch new file mode 100644 index 0000000000..ef2f814b7d --- /dev/null +++ b/SPECS/linux/0253-RVCK-dts-add-pinctrl-dtsi-dts-for-UltraRisc-DP1000.patch @@ -0,0 +1,237 @@ +From cdb37bf52175a5e5790361efa064f3c69f1698a8 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Mon, 16 Jun 2025 10:25:31 +0800 +Subject: [RUYI PATCH] RVCK: dts: add pinctrl dtsi/dts for UltraRisc DP1000 + +The newly added dtsi/dts is used to describe the pinctrl +configuration of the UltraRisc DP1000-EVB mainboard. + +Do not involve functional changes. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/e00864f9706198f8b278551217c048a140cbe39f +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 2 +- + .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 141 ++++++++++++++++++ + .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 52 +++++++ + 3 files changed, 194 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index c27f490e2b99..ef70e28e0b65 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,2 +1,2 @@ + # SPDX-License-Identifier: GPL-2.0 +-dtb-y += dp1000.dtb ++dtb-y += dp1000.dtb dp1000-evb-v1.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +new file mode 100644 +index 000000000000..be898b6df6fb +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +@@ -0,0 +1,141 @@ ++#include ++ ++/ { ++ ++ soc { ++ pmx0: pinmux@11081000 { ++ compatible = "ultrarisc,dp1000-pinctrl"; ++ reg = <0x0 0x11081000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #pinctrl-cells = <2>; ++ pinctrl-single,register-width = <32>; ++ pinctrl-single,function-mask = <0x3ff>; ++ pinctrl-use-default; ++ ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +new file mode 100644 +index 000000000000..5ec9a39e8c34 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +@@ -0,0 +1,52 @@ ++/* ++* SPDX-License-Identifier: GPL-2.0+ ++* ++* Copyright (c) 2019-2022 UltraRisc,Inc ++* ++*/ ++ ++#include "dp1000.dts" ++#include "dp1000-evb-pinctrl.dtsi" ++#include ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; +-- +2.53.0 + diff --git a/SPECS/linux/0253-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch b/SPECS/linux/0253-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch deleted file mode 100644 index 32be00c868..0000000000 --- a/SPECS/linux/0253-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch +++ /dev/null @@ -1,677 +0,0 @@ -From 8f6a15ab728bb98f3ddcff83b8d86011f6cd1fd6 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 11 Nov 2025 17:03:37 +0800 -Subject: [PATCH 253/269] RVCK: dts: riscv: ultrarisc: Refactor DP1000 device - tree files - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Add gpio-ranges property to all gpio/portX nodes. -This property maps GPIO lines to pin controller pins, -ensuring proper GPIO pin allocation and management. - -Convert dp1000.dts to a common include file (dp1000.dtsi) and update -the board-specific DTS files to include it. This refactoring allows -for better code reuse across different DP1000-based boards (EVB, MO, -and Titan variants) while maintaining board-specific configurations. - -The changes include: -- Renaming dp1000.dts to dp1000.dtsi -- Updating board-specific DTS files to include the common .dtsi -- Adjusting Makefile to reflect these changes -- Updating pinctrl files for all board variants - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/f9d4926fccee70f72d11e11dfa11b99f59caa947 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 1 - - .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 261 +++++++++--------- - .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 1 - - .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 261 +++++++++--------- - .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 1 - - .../dts/ultrarisc/{dp1000.dts => dp1000.dtsi} | 15 + - 6 files changed, 263 insertions(+), 277 deletions(-) - rename arch/riscv/boot/dts/ultrarisc/{dp1000.dts => dp1000.dtsi} (96%) - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index 9eac56549340..22c03b44b2f8 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,4 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -index e82fcf2901ab..e2c09d5bdb20 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi -@@ -4,143 +4,130 @@ - */ - - #include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ UR_DP1000_IOMUX_D 6 UR_FUNC1 -+ UR_DP1000_IOMUX_D 7 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; - --/ { -- -- soc { -- pmx0: pinmux@11081000 { -- compatible = "ultrarisc,dp1000-pinctrl"; -- reg = <0x0 0x11081000 0x0 0x1000>; -- #address-cells = <1>; -- #size-cells = <0>; -- #pinctrl-cells = <2>; -- pinctrl-single,register-width = <32>; -- pinctrl-single,function-mask = <0x3ff>; -- pinctrl-use-default; -- -- i2c0_pins: i2c0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c1_pins: i2c1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c2_pins: i2c2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c3_pins: i2c3_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart0_pins: uart0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart1_pins: uart1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart2_pins: uart2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi0_pins: spi0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi1_pins: spi1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- }; -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; - }; - }; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -index 34d024a083fc..46fe457b5f52 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts -@@ -3,7 +3,6 @@ - * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. - */ - --#include "dp1000.dts" - #include "dp1000-evb-pinctrl.dtsi" - #include - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -index e82fcf2901ab..85b013f66bbd 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi -@@ -4,143 +4,130 @@ - */ - - #include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ UR_DP1000_IOMUX_D 6 UR_FUNC1 -+ UR_DP1000_IOMUX_D 7 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; - --/ { -- -- soc { -- pmx0: pinmux@11081000 { -- compatible = "ultrarisc,dp1000-pinctrl"; -- reg = <0x0 0x11081000 0x0 0x1000>; -- #address-cells = <1>; -- #size-cells = <0>; -- #pinctrl-cells = <2>; -- pinctrl-single,register-width = <32>; -- pinctrl-single,function-mask = <0x3ff>; -- pinctrl-use-default; -- -- i2c0_pins: i2c0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c1_pins: i2c1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c2_pins: i2c2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- i2c3_pins: i2c3_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart0_pins: uart0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart1_pins: uart1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- uart2_pins: uart2_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi0_pins: spi0_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- -- spi1_pins: spi1_pins { -- pinctrl-pins = < -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) -- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) -- >; -- -- pinconf-pins = < -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) -- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) -- >; -- }; -- }; -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; - }; - }; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -index 8c532e5b71a3..dc057cbaf59b 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts -@@ -3,7 +3,6 @@ - * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. - */ - --#include "dp1000.dts" - #include "dp1000-mo-pinctrl.dtsi" - #include - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -similarity index 96% -rename from arch/riscv/boot/dts/ultrarisc/dp1000.dts -rename to arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index 128293c0af1f..a25e87e15553 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -330,6 +330,17 @@ wdt0: watchdog@20210000 { - clocks = <&device_clk>; - }; - -+ pmx0: pinmux@11081000 { -+ compatible = "ultrarisc,dp1000-pinctrl"; -+ reg = <0x0 0x11081000 0x0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ #pinctrl-cells = <2>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x3ff>; -+ pinctrl-use-default; -+ }; -+ - gpio: gpio@20200000 { - compatible = "snps,dw-apb-gpio"; - #address-cells = <1>; -@@ -349,6 +360,7 @@ porta: gpio-port@0 { - #interrupt-cells = <2>; - interrupt-parent = <0x01>; - interrupts = <34>; -+ gpio-ranges = <&pmx0 0 0 16>; - }; - - portb: gpio-port@1 { -@@ -357,6 +369,7 @@ portb: gpio-port@1 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 16 0 8>; - }; - - portc: gpio-port@2 { -@@ -365,6 +378,7 @@ portc: gpio-port@2 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 24 0 8>; - }; - - portd: gpio-port@3 { -@@ -373,6 +387,7 @@ portd: gpio-port@3 { - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; -+ gpio-ranges = <&pmx0 32 0 8>; - }; - }; - --- -2.53.0 - diff --git a/SPECS/linux/0254-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch b/SPECS/linux/0254-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch new file mode 100644 index 0000000000..06b23336f5 --- /dev/null +++ b/SPECS/linux/0254-RVCK-riscv-dp1000-dts-add-the-dts-of-UltraRISC-dp100.patch @@ -0,0 +1,251 @@ +From 5b02fda142ec866da9b3128d0d0d58270d8a6d48 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Thu, 4 Sep 2025 16:31:30 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: add the dts of UltraRISC + dp1000-mo-v1 board + +adds the necessary device tree files for the UltraRISC +dp1000-mo-v1 board. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/1186c972f5908717ab186cea67403c74ea03cde1 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 4 +- + .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 146 ++++++++++++++++++ + .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 60 +++++++ + 3 files changed, 209 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index ef70e28e0b65..9eac56549340 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,2 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 +-dtb-y += dp1000.dtb dp1000-evb-v1.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +new file mode 100644 +index 000000000000..e82fcf2901ab +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +@@ -0,0 +1,146 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include ++ ++/ { ++ ++ soc { ++ pmx0: pinmux@11081000 { ++ compatible = "ultrarisc,dp1000-pinctrl"; ++ reg = <0x0 0x11081000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #pinctrl-cells = <2>; ++ pinctrl-single,register-width = <32>; ++ pinctrl-single,function-mask = <0x3ff>; ++ pinctrl-use-default; ++ ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +new file mode 100644 +index 000000000000..a74714629566 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +@@ -0,0 +1,60 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000.dts" ++#include "dp1000-mo-pinctrl.dtsi" ++#include ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ ++ rtc@32 { ++ compatible = "whwave,sd3078"; ++ reg = <0x32>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; +-- +2.53.0 + diff --git a/SPECS/linux/0254-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch b/SPECS/linux/0254-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch deleted file mode 100644 index fa5b447f2b..0000000000 --- a/SPECS/linux/0254-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch +++ /dev/null @@ -1,166 +0,0 @@ -From ba532e9a5105d85f8a233aaa29a0bad77ee00371 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Wed, 12 Nov 2025 15:43:27 +0800 -Subject: [PATCH 254/269] RVCK: riscv: pinctrl: ultrarisc: Implement pin - configuration support - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Update ur_pin_config_set() to use the new configuration handling logic. -This allows the driver to properly handle standard Linux kernel pin -configuration parameters such as PIN_CONFIG_BIAS_PULL_UP, -PIN_CONFIG_BIAS_PULL_DOWN, etc. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/d094389a972a4b03d04b77a47c19f5c9c9fb0627 -Signed-off-by: Han Gao ---- - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 + - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 83 +++++++++++++++++-- - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 2 +- - 3 files changed, 77 insertions(+), 9 deletions(-) - -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -index 217f671fe63a..6a7496a465d8 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -86,6 +86,7 @@ static struct ur_pinctrl_match_data ur_dp1000_match_data = { - .pins = ur_dp1000_pins, - .npins = ARRAY_SIZE(ur_dp1000_pins), - .offset = 0x2c0, -+ .num_ports = 5, - .ports = { - {"A", 16, 0x2c0, 0x310}, - {"B", 8, 0x2c4, 0x318}, -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -index 667d59e0ac6e..edaeca881af7 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -326,6 +326,58 @@ static const struct pinmux_ops ur_pinmux_ops = { - - #define UR_CONF_BIT_PER_PIN (4) - #define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) -+ -+static int ur_pin_num_to_port_pin(const struct ur_pinctrl_match_data *match_data, -+ struct ur_pin_val *pin_val, u32 pin_num) -+{ -+ const struct ur_port_desc *port_desc; -+ -+ for (int i = 0; i < match_data->num_ports; i++) { -+ port_desc = &match_data->ports[i]; -+ if (pin_num < port_desc->npins) { -+ pin_val->port = i; -+ pin_val->pin = pin_num; -+ pin_val->conf = 0; -+ return 0; -+ } -+ pin_num -= port_desc->npins; -+ } -+ return -EINVAL; -+} -+ -+static int ur_config_to_pin_val(struct ur_pinctrl *pin_ctrl, -+ struct ur_pin_val *pin_vals, -+ unsigned long *config) -+{ -+ enum pin_config_param param = pinconf_to_config_param(*config); -+ u32 arg = pinconf_to_config_argument(*config); -+ -+ dev_dbg(pin_ctrl->dev, "%s(%d): config_to_pin_val: param=%d, arg=0x%x\n", -+ __func__, __LINE__, param, arg); -+ -+ switch (param) { -+ case PIN_CONFIG_BIAS_DISABLE: -+ pin_vals->conf &= ~UR_BIAS_MASK; -+ break; -+ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: -+ pin_vals->conf &= ~(UR_PULL_DOWN | UR_PULL_UP); -+ break; -+ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: -+ case PIN_CONFIG_BIAS_PULL_DOWN: -+ pin_vals->conf |= UR_PULL_DOWN; -+ break; -+ case PIN_CONFIG_BIAS_PULL_UP: -+ pin_vals->conf |= UR_PULL_UP; -+ break; -+ case PIN_CONFIG_DRIVE_PUSH_PULL: -+ case PIN_CONFIG_PERSIST_STATE: -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ return 0; -+} -+ - static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) - { - const struct ur_port_desc *port_desc; -@@ -334,8 +386,11 @@ static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_v - u32 val, conf; - - port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; -+ dev_dbg(pin_ctrl->dev, "set pinconf port=%d pin=%d conf=0x%x\n", -+ pin_vals->port, pin_vals->pin, pin_vals->conf); - reg = pin_ctrl->base + port_desc->conf_offset; -- dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); -+ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, conf_offset=0x%x, reg=0x%llx\n", -+ (u64)pin_ctrl->base, port_desc->conf_offset, (u64)reg); - reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; - dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); - -@@ -367,16 +422,28 @@ static int ur_pin_config_set(struct pinctrl_dev *pctldev, - unsigned long *configs, - unsigned int num_configs) - { -- struct ur_pin_val *pin_conf; -+ struct ur_pin_val pin_val; - struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); -+ int ret; -+ -+ ret = ur_pin_num_to_port_pin(ur_pinctrl->match_data, &pin_val, pin); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "invalid pin number %d\n", pin); -+ return ret; -+ } -+ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d, port=%d, pin=%d\n", -+ __func__, __LINE__, pin, num_configs, pin_val.port, pin_val.pin); - -- dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", -- __func__, __LINE__, pin, num_configs); -- pin_conf = (struct ur_pin_val *)configs; - for (int i = 0; i < num_configs; i++) { -- dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", -- i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); -- ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); -+ ret = ur_config_to_pin_val(ur_pinctrl, &pin_val, &configs[i]); -+ if (ret < 0) { -+ dev_err(pctldev->dev, "invalid config 0x%lx\n", configs[i]); -+ return ret; -+ } -+ -+ dev_dbg(pctldev->dev, "%s(%d): port=%d, pin=%d, conf=0x%x\n", -+ __func__, __LINE__, pin_val.port, pin_val.pin, pin_val.conf); -+ ur_set_pin_conf(ur_pinctrl, &pin_val); - } - return 0; - } -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -index eec621bf8b05..728b2111def0 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h -@@ -50,7 +50,7 @@ struct ur_pinctrl_match_data { - const struct pinctrl_pin_desc *pins; - u32 npins; - u32 offset; -- //u32 conf_offset[]; -+ u32 num_ports; - struct ur_port_desc ports[]; - }; - --- -2.53.0 - diff --git a/SPECS/linux/0255-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch b/SPECS/linux/0255-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch new file mode 100644 index 0000000000..5104a8fcb6 --- /dev/null +++ b/SPECS/linux/0255-RVCK-riscv-dp1000-dts-Move-mmc0-node-from-SoC-to-boa.patch @@ -0,0 +1,111 @@ +From 6a70dada178f7a2b3b2a1a7f463bad337ddd7074 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 9 Sep 2025 15:45:52 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: Move mmc0 node from SoC to + board DTS + +The mmc0 node (mmc-spi-slot) is a board-level peripheral +specific to the UltraRISC DP1000 EVB V1.0, not part of the +base SoC. Move it from the SoC-level dp1000.dts to the +board-specific dp1000-evb-v1.dts to maintain proper device +tree hierarchy between SoC core and board-specific components. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/c719099661103786c877036840568c38f3d083a9 +Signed-off-by: Han Gao +--- + .../boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 9 +++++++-- + arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 16 +++++++++++----- + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 15 +++------------ + 3 files changed, 21 insertions(+), 19 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +index be898b6df6fb..e82fcf2901ab 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +@@ -1,3 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ + #include + + / { +@@ -63,8 +68,8 @@ UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) + + uart0_pins: uart0_pins { + pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC0) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) ++ UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) + >; + + pinconf-pins = < +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +index 5ec9a39e8c34..34622a33e63b 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +@@ -1,9 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0 + /* +-* SPDX-License-Identifier: GPL-2.0+ +-* +-* Copyright (c) 2019-2022 UltraRisc,Inc +-* +-*/ ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ + + #include "dp1000.dts" + #include "dp1000-evb-pinctrl.dtsi" +@@ -27,6 +25,14 @@ &i2c3 { + &spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; ++ ++ mmc0: mmc@0 { ++ compatible = "mmc-spi-slot"; ++ spi-max-frequency = <15625000>; ++ reg = <0x00>; ++ voltage-ranges = <3300 3300>; ++ disable-wp; ++ }; + }; + + &spi1 { +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +index 3eb811f73aa8..23a983d6a4c8 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +@@ -1,9 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0 + /* +-* SPDX-License-Identifier: GPL-2.0+ +-* +-* Copyright (c) 2019-2022 UltraRisc,Inc +-* +-*/ ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ + + /dts-v1/; + +@@ -261,13 +259,6 @@ spi0: spi@20320000 { + clock-names = "device_clk"; + num-cs = <3>; + spi-max-frequency = <62500000>; +- mmc0: mmc@0 { +- compatible = "mmc-spi-slot"; +- spi-max-frequency = <15625000>; +- reg = <0x00>; +- voltage-ranges = <3300 3300>; +- disable-wp; +- }; + }; + + spi1: spi@20420000 { +-- +2.53.0 + diff --git a/SPECS/linux/0255-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch b/SPECS/linux/0255-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch deleted file mode 100644 index 6c8fdd837e..0000000000 --- a/SPECS/linux/0255-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch +++ /dev/null @@ -1,364 +0,0 @@ -From 54a5d6c95ff0cfcfa26baddda6c8527e957ff553 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Tue, 18 Nov 2025 13:48:49 +0800 -Subject: [PATCH 255/269] RVCK: riscv: dts: dp1000: add dts/dtsi for Milk-V - Titan board based on UltraRISC DP1000 SoC - -community inclusion -category: feature -bugzilla: https://github.com/RVCK-Project/rvck/issues/71 - --------------------------------- - -Add dp1000-titan-v1.dts and dp1000-titan-pinctrl.dtsi for the Milk-V Titan -board. The Titan board is designed by Milk-V and is based on the UltraRISC -DP1000 SoC. These device tree files provide the initial support for the -board, including pinctrl and basic peripheral configuration. - -Signed-off-by: Jia Wang -FROM: https://github.com/RVCK-Project/rvck/commit/edab885e252d0442ccf52b2b554934138b82b2ec -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/Makefile | 1 + - .../dts/ultrarisc/dp1000-titan-pinctrl.dtsi | 173 ++++++++++++++++++ - .../boot/dts/ultrarisc/dp1000-titan-v1.dts | 139 ++++++++++++++ - 3 files changed, 313 insertions(+) - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi - create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts - -diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile -index 22c03b44b2f8..df8efe1a3ed7 100644 ---- a/arch/riscv/boot/dts/ultrarisc/Makefile -+++ b/arch/riscv/boot/dts/ultrarisc/Makefile -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb - dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb -+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-titan-v1.dtb -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi -new file mode 100644 -index 000000000000..35429e539832 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi -@@ -0,0 +1,173 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include -+#include "dp1000.dtsi" -+ -+&pmx0 { -+ i2c0_pins: i2c0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 12 UR_FUNC0 -+ UR_DP1000_IOMUX_A 13 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c1_pins: i2c1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 6 UR_FUNC0 -+ UR_DP1000_IOMUX_B 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c2_pins: i2c2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 0 UR_FUNC0 -+ UR_DP1000_IOMUX_C 1 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ i2c3_pins: i2c3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 2 UR_FUNC0 -+ UR_DP1000_IOMUX_C 3 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart0_pins: uart0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 8 UR_FUNC1 -+ UR_DP1000_IOMUX_A 9 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart1_pins: uart1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_B 4 UR_FUNC0 -+ UR_DP1000_IOMUX_B 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart2_pins: uart2_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 4 UR_FUNC0 -+ UR_DP1000_IOMUX_C 5 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ uart3_pins: uart3_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_C 6 UR_FUNC0 -+ UR_DP1000_IOMUX_C 7 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_C 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_C 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi0_pins: spi0_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_D 0 UR_FUNC1 -+ UR_DP1000_IOMUX_D 1 UR_FUNC1 -+ UR_DP1000_IOMUX_D 2 UR_FUNC1 -+ UR_DP1000_IOMUX_D 3 UR_FUNC1 -+ UR_DP1000_IOMUX_D 4 UR_FUNC1 -+ UR_DP1000_IOMUX_D 5 UR_FUNC1 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ spi1_pins: spi1_pins { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 0 UR_FUNC0 -+ UR_DP1000_IOMUX_A 1 UR_FUNC0 -+ UR_DP1000_IOMUX_A 2 UR_FUNC0 -+ UR_DP1000_IOMUX_A 3 UR_FUNC0 -+ UR_DP1000_IOMUX_A 4 UR_FUNC0 -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+ -+ gpios_pin: gpios_pin { -+ pinctrl-pins = < -+ UR_DP1000_IOMUX_A 10 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 11 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 14 UR_FUNC_DEF -+ UR_DP1000_IOMUX_A 15 UR_FUNC_DEF -+ -+ UR_DP1000_IOMUX_B 0 UR_FUNC_DEF -+ UR_DP1000_IOMUX_B 1 UR_FUNC_DEF -+ UR_DP1000_IOMUX_B 2 UR_FUNC_DEF -+ -+ UR_DP1000_IOMUX_D 6 UR_FUNC_DEF -+ UR_DP1000_IOMUX_D 7 UR_FUNC_DEF -+ >; -+ -+ pinconf-pins = < -+ UR_DP1000_IOMUX_A 10 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 11 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 14 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_A 15 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ -+ UR_DP1000_IOMUX_B 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_B 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ -+ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) -+ >; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts -new file mode 100644 -index 000000000000..2cbdfa2ad813 ---- /dev/null -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts -@@ -0,0 +1,139 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ */ -+ -+#include "dp1000-titan-pinctrl.dtsi" -+#include -+#include -+#include -+#include -+ -+/ { -+ chosen { -+ bootargs = "earlycon=sbi console=ttyS0,115200"; -+ stdout-path = &uart0; -+ }; -+ -+ gpio-poweroff { -+ compatible = "gpio-poweroff"; -+ gpios = <&portb 0 GPIO_ACTIVE_LOW>; -+ active-delay-ms = <100>; -+ line-name = "power-off"; -+ status = "okay"; -+ }; -+ -+ gpio-restart { -+ compatible = "gpio-restart"; -+ gpios = <&portb 1 GPIO_ACTIVE_LOW>; -+ active-delay-ms = <100>; -+ line-name = "reset-system"; -+ status = "okay"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ -+ key-wakeup { -+ label = "Wake-Up"; -+ gpios = <&porta 14 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ linux,input-type = ; -+ debounce-interval = <10>; -+ wakeup-source; -+ wakeup-event-action = ; -+ }; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+}; -+ -+&i2c2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c2_pins>; -+ -+ rtc@68 { -+ compatible = "st,m41t11"; -+ reg = <0x68>; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+}; -+ -+&spi1 { -+ num-cs = <1>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart3_pins>; -+}; -+ -+&porta { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpios_pin>; -+ -+ i2c1-mux-hog { -+ gpio-hog; -+ gpios = <5 GPIO_ACTIVE_HIGH>; -+ /* LOW: DCDC(U6) connect MCU(EC) -+ * HIGH: DCDC(U6) connect CPU -+ */ -+ output-low; -+ line-name = "gpio-mux-dcdc"; -+ }; -+ -+ i2c3-mux-hog { -+ gpio-hog; -+ gpios = <6 GPIO_ACTIVE_LOW>; -+ /* LOW: CPU i2c3 connect nvme -+ * HIGH: CPU i2c3 connect pciex16 -+ */ -+ output-low; -+ line-name = "gpio-mux-i2c3"; -+ }; -+ -+ uart0-mux-hog { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ /* LOW: uart_debug connect BMC -+ * HIGH: uart_debug connect CPU -+ */ -+ output-high; -+ line-name = "gpio-mux-debug"; -+ }; -+}; --- -2.53.0 - diff --git a/SPECS/linux/0256-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch b/SPECS/linux/0256-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch deleted file mode 100644 index df25278d75..0000000000 --- a/SPECS/linux/0256-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 2eb3d7cf7c9f421ab138be87e0fbd6dc6dfa67de Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Mon, 23 Feb 2026 14:35:29 +0800 -Subject: [PATCH 256/269] REVYSR: pinctrl: ultrarisc: cleanup probe&remove - -Signed-off-by: Han Gao ---- - .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 - - drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 22 +++---------------- - 2 files changed, 3 insertions(+), 20 deletions(-) - -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -index 6a7496a465d8..0ead138c9d1f 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c -@@ -117,7 +117,6 @@ static struct platform_driver ur_pinctrl_driver = { - .of_match_table = ur_pinctrl_of_match, - }, - .probe = ur_pinctrl_probe, -- .remove = ur_pinctrl_remove, - }; - - module_platform_driver(ur_pinctrl_driver); -diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -index edaeca881af7..cdd7160f3183 100644 ---- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -+++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c -@@ -514,8 +514,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); - if (!ur_pinctrl) { - dev_err(&pdev->dev, "pinctrl alloc failed\n"); -- ret = -ENOMEM; -- goto free_pinctrl_desc; -+ return -ENOMEM; - } - struct resource *res; - -@@ -524,8 +523,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(ur_pinctrl->base)) { - dev_err(&pdev->dev, "get ioremap resource failed\n"); -- ret = -EINVAL; -- goto free_pinctrl_desc; -+ return -EINVAL; - } - dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); - ur_pinctrl_desc->name = dev_name(&pdev->dev); -@@ -546,25 +544,11 @@ int ur_pinctrl_probe(struct platform_device *pdev) - ur_pinctrl, &ur_pinctrl->pctl_dev); - if (ret) { - dev_err(&pdev->dev, "pinctrl register failed\n"); -- goto free_pinctrl; -+ return ret; - } - - platform_set_drvdata(pdev, ur_pinctrl); - - return pinctrl_enable(ur_pinctrl->pctl_dev); -- --free_pinctrl: -- devm_kfree(&pdev->dev, ur_pinctrl); --free_pinctrl_desc: -- devm_kfree(&pdev->dev, ur_pinctrl_desc); -- return ret; - } - -- --void ur_pinctrl_remove(struct platform_device *pdev) --{ -- struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); -- -- if (ur_pinctrl->pctl_dev) -- devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); --} --- -2.53.0 - diff --git a/SPECS/linux/0256-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch b/SPECS/linux/0256-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch new file mode 100644 index 0000000000..96b16bdf3a --- /dev/null +++ b/SPECS/linux/0256-RVCK-riscv-dp1000-plic-add-plic-early-init-supports.patch @@ -0,0 +1,77 @@ +From b7f462ae6415d55a8f0dccaa06756362f6bd4a16 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Thu, 18 Sep 2025 10:44:01 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dp1000: plic: add plic early init supports + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +------------------------------------------------- + +Add PLIC early init supports and remove invalid +timer nodes in dp1000.dts. + +Signed-off-by: Jia Wang +From: https://github.com/RVCK-Project/rvck/commit/9e4cfbdf46fad772cc002c53b9e295cda600e9c5 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 25 ++---------------------- + drivers/irqchip/irq-sifive-plic.c | 1 + + 2 files changed, 3 insertions(+), 23 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +index 23a983d6a4c8..4a2dae602693 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +@@ -164,6 +164,7 @@ device_clk: device_clk { + clock-frequency = <62500000>; + #clock-cells = <0>; + }; ++ + csr_clk: csr_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; +@@ -333,29 +334,7 @@ wdt0: watchdog@20210000 { + interrupts = <33>; + clocks = <&device_clk>; + }; +- +- timer0: timer@20220000 { +- compatible = "snps,dw-apb-timer"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x20220000 0x0 0x100>; +- clocks = <&device_clk>; +- interrupt-parent = <0x01>; +- interrupts = <35>; +- status = "okay"; +- }; +- +- timer1: timer@20230000 { +- compatible = "snps,dw-apb-timer"; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0 0x20230000 0x0 0x100>; +- clocks = <&device_clk>; +- interrupt-parent = <0x01>; +- interrupts = <36>; +- status = "okay"; +- }; +- ++ + gpio: gpio@20200000 { + compatible = "snps,dw-apb-gpio"; + #address-cells = <1>; +diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c +index 5b0dac104814..bb64c27d76ca 100644 +--- a/drivers/irqchip/irq-sifive-plic.c ++++ b/drivers/irqchip/irq-sifive-plic.c +@@ -846,3 +846,4 @@ static int __init plic_early_probe(struct device_node *node, + } + + IRQCHIP_DECLARE(riscv, "allwinner,sun20i-d1-plic", plic_early_probe); ++IRQCHIP_DECLARE(ultrarisc_dp1000_plic, "ultrarisc,dp1000-plic", plic_early_probe); +-- +2.53.0 + diff --git a/SPECS/linux/0257-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch b/SPECS/linux/0257-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch deleted file mode 100644 index d58caf5a6c..0000000000 --- a/SPECS/linux/0257-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 6bd09fa37639fe6064c95cc808a700f9c0ec5b63 Mon Sep 17 00:00:00 2001 -From: U2FsdGVkX1 -Date: Sun, 29 Mar 2026 15:31:14 +0000 -Subject: [PATCH 257/269] REVYSR: riscv: dp1000: dts: use ultrarisc,dp1000-pcie - for PCIe nodes - -Signed-off-by: U2FsdGVkX1 -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index a25e87e15553..78e0cda1fcb9 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -436,7 +436,7 @@ dmac: dma-controller@39000000 { - }; - - pcie_x16: pcie@21000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; -@@ -462,7 +462,7 @@ pcie_x16: pcie@21000000 { - }; - - pcie_x4a: pcie@23000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; -@@ -488,7 +488,7 @@ pcie_x4a: pcie@23000000 { - }; - - pcie_x4b: pcie@24000000 { -- compatible = "ultrarisc,dw-pcie"; -+ compatible = "ultrarisc,dp1000-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; --- -2.53.0 - diff --git a/SPECS/linux/0257-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch b/SPECS/linux/0257-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch new file mode 100644 index 0000000000..cb34820f7f --- /dev/null +++ b/SPECS/linux/0257-RVCK-riscv-dp1000-dts-Move-chosen-node-from-common-t.patch @@ -0,0 +1,85 @@ +From 84505e39377a72f4d26dc63e3e1af530158a2cb8 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Mon, 10 Nov 2025 16:11:12 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dp1000: dts: Move chosen node from common + to board-specific DTS + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +-------------------------------- + +This commit moves the chosen node configuration from the +common dp1000.dts file to the respective board-specific +DTS files. + +This change allows each board to specify its own console +configuration while keeping the common SoC definitions clean. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/db5745be89ee881ff18a7ded0bcff1c2f495becf +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts | 7 +++++++ + arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 7 +++++++ + arch/riscv/boot/dts/ultrarisc/dp1000.dts | 7 +------ + 3 files changed, 15 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +index 34622a33e63b..34d024a083fc 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +@@ -7,6 +7,13 @@ + #include "dp1000-evb-pinctrl.dtsi" + #include + ++/ { ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS1,115200"; ++ stdout-path = &uart1; ++ }; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +index a74714629566..8c532e5b71a3 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +@@ -7,6 +7,13 @@ + #include "dp1000-mo-pinctrl.dtsi" + #include + ++/ { ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS0,115200"; ++ stdout-path = &uart0; ++ }; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +index 4a2dae602693..128293c0af1f 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dts +@@ -10,12 +10,7 @@ / { + #size-cells = <0x02>; + compatible = "ultrarisc,dp1000"; + model = "ultrarisc,dp1000"; +- +- chosen { +- bootargs = "earlycon=sbi console=ttyS1,115200"; +- stdout-path = &uart1; +- }; +- ++ + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; +-- +2.53.0 + diff --git a/SPECS/linux/0258-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch b/SPECS/linux/0258-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch new file mode 100644 index 0000000000..a0b1cb0475 --- /dev/null +++ b/SPECS/linux/0258-RVCK-dts-riscv-ultrarisc-Refactor-DP1000-device-tree.patch @@ -0,0 +1,677 @@ +From aa4887203bde39969d200fbcaebe436dedf91890 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 11 Nov 2025 17:03:37 +0800 +Subject: [RUYI PATCH] RVCK: dts: riscv: ultrarisc: Refactor DP1000 device tree + files + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +-------------------------------- + +Add gpio-ranges property to all gpio/portX nodes. +This property maps GPIO lines to pin controller pins, +ensuring proper GPIO pin allocation and management. + +Convert dp1000.dts to a common include file (dp1000.dtsi) and update +the board-specific DTS files to include it. This refactoring allows +for better code reuse across different DP1000-based boards (EVB, MO, +and Titan variants) while maintaining board-specific configurations. + +The changes include: +- Renaming dp1000.dts to dp1000.dtsi +- Updating board-specific DTS files to include the common .dtsi +- Adjusting Makefile to reflect these changes +- Updating pinctrl files for all board variants + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/f9d4926fccee70f72d11e11dfa11b99f59caa947 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 1 - + .../dts/ultrarisc/dp1000-evb-pinctrl.dtsi | 261 +++++++++--------- + .../boot/dts/ultrarisc/dp1000-evb-v1.dts | 1 - + .../boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi | 261 +++++++++--------- + .../riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts | 1 - + .../dts/ultrarisc/{dp1000.dts => dp1000.dtsi} | 15 + + 6 files changed, 263 insertions(+), 277 deletions(-) + rename arch/riscv/boot/dts/ultrarisc/{dp1000.dts => dp1000.dtsi} (96%) + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index 9eac56549340..22c03b44b2f8 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,4 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000.dtb + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +index e82fcf2901ab..e2c09d5bdb20 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-pinctrl.dtsi +@@ -4,143 +4,130 @@ + */ + + #include ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 12 UR_FUNC0 ++ UR_DP1000_IOMUX_A 13 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 6 UR_FUNC0 ++ UR_DP1000_IOMUX_B 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 0 UR_FUNC0 ++ UR_DP1000_IOMUX_C 1 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 2 UR_FUNC0 ++ UR_DP1000_IOMUX_C 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 8 UR_FUNC1 ++ UR_DP1000_IOMUX_A 9 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 4 UR_FUNC0 ++ UR_DP1000_IOMUX_B 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 4 UR_FUNC0 ++ UR_DP1000_IOMUX_C 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_D 0 UR_FUNC1 ++ UR_DP1000_IOMUX_D 1 UR_FUNC1 ++ UR_DP1000_IOMUX_D 2 UR_FUNC1 ++ UR_DP1000_IOMUX_D 3 UR_FUNC1 ++ UR_DP1000_IOMUX_D 4 UR_FUNC1 ++ UR_DP1000_IOMUX_D 5 UR_FUNC1 ++ UR_DP1000_IOMUX_D 6 UR_FUNC1 ++ UR_DP1000_IOMUX_D 7 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; + +-/ { +- +- soc { +- pmx0: pinmux@11081000 { +- compatible = "ultrarisc,dp1000-pinctrl"; +- reg = <0x0 0x11081000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <2>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x3ff>; +- pinctrl-use-default; +- +- i2c0_pins: i2c0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c1_pins: i2c1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c2_pins: i2c2_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c3_pins: i2c3_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart0_pins: uart0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart1_pins: uart1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart2_pins: uart2_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- spi0_pins: spi0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- spi1_pins: spi1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- }; ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 0 UR_FUNC0 ++ UR_DP1000_IOMUX_A 1 UR_FUNC0 ++ UR_DP1000_IOMUX_A 2 UR_FUNC0 ++ UR_DP1000_IOMUX_A 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; + }; + }; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +index 34d024a083fc..46fe457b5f52 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-evb-v1.dts +@@ -3,7 +3,6 @@ + * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +-#include "dp1000.dts" + #include "dp1000-evb-pinctrl.dtsi" + #include + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +index e82fcf2901ab..85b013f66bbd 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-pinctrl.dtsi +@@ -4,143 +4,130 @@ + */ + + #include ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 12 UR_FUNC0 ++ UR_DP1000_IOMUX_A 13 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 6 UR_FUNC0 ++ UR_DP1000_IOMUX_B 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 0 UR_FUNC0 ++ UR_DP1000_IOMUX_C 1 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 2 UR_FUNC0 ++ UR_DP1000_IOMUX_C 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 8 UR_FUNC1 ++ UR_DP1000_IOMUX_A 9 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 4 UR_FUNC0 ++ UR_DP1000_IOMUX_B 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 4 UR_FUNC0 ++ UR_DP1000_IOMUX_C 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_D 0 UR_FUNC1 ++ UR_DP1000_IOMUX_D 1 UR_FUNC1 ++ UR_DP1000_IOMUX_D 2 UR_FUNC1 ++ UR_DP1000_IOMUX_D 3 UR_FUNC1 ++ UR_DP1000_IOMUX_D 4 UR_FUNC1 ++ UR_DP1000_IOMUX_D 5 UR_FUNC1 ++ UR_DP1000_IOMUX_D 6 UR_FUNC1 ++ UR_DP1000_IOMUX_D 7 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; + +-/ { +- +- soc { +- pmx0: pinmux@11081000 { +- compatible = "ultrarisc,dp1000-pinctrl"; +- reg = <0x0 0x11081000 0x0 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- #pinctrl-cells = <2>; +- pinctrl-single,register-width = <32>; +- pinctrl-single,function-mask = <0x3ff>; +- pinctrl-use-default; +- +- i2c0_pins: i2c0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 12, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 13, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 12, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 13, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c1_pins: i2c1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 6, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 7, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 6, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 7, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c2_pins: i2c2_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 0, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 1, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 1, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- i2c3_pins: i2c3_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 2, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 3, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 3, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart0_pins: uart0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 8, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 9, UR_FUNC1) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 8, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 9, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart1_pins: uart1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 4, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_B, 5, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_B, 5, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- uart2_pins: uart2_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 4, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_C, 5, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_C, 5, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- spi0_pins: spi0_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 0, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 1, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 2, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 3, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 4, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 5, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 6, UR_FUNC1) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_D, 7, UR_FUNC1) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 1, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 3, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 4, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 5, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 6, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_D, 7, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- +- spi1_pins: spi1_pins { +- pinctrl-pins = < +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 0, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 1, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 2, UR_FUNC0) +- UR_DP1000_IOPAD(UR_DP1000_IOMUX_A, 3, UR_FUNC0) +- >; +- +- pinconf-pins = < +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 0, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 1, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 2, UR_PULL_UP, UR_DRIVE_DEF) +- UR_DP1000_BIAS(UR_DP1000_IOMUX_A, 3, UR_PULL_UP, UR_DRIVE_DEF) +- >; +- }; +- }; ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 0 UR_FUNC0 ++ UR_DP1000_IOMUX_A 1 UR_FUNC0 ++ UR_DP1000_IOMUX_A 2 UR_FUNC0 ++ UR_DP1000_IOMUX_A 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; + }; + }; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +index 8c532e5b71a3..dc057cbaf59b 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-mo-v1.dts +@@ -3,7 +3,6 @@ + * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +-#include "dp1000.dts" + #include "dp1000-mo-pinctrl.dtsi" + #include + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dts b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +similarity index 96% +rename from arch/riscv/boot/dts/ultrarisc/dp1000.dts +rename to arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +index 128293c0af1f..a25e87e15553 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dts ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +@@ -330,6 +330,17 @@ wdt0: watchdog@20210000 { + clocks = <&device_clk>; + }; + ++ pmx0: pinmux@11081000 { ++ compatible = "ultrarisc,dp1000-pinctrl"; ++ reg = <0x0 0x11081000 0x0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #pinctrl-cells = <2>; ++ pinctrl-single,register-width = <32>; ++ pinctrl-single,function-mask = <0x3ff>; ++ pinctrl-use-default; ++ }; ++ + gpio: gpio@20200000 { + compatible = "snps,dw-apb-gpio"; + #address-cells = <1>; +@@ -349,6 +360,7 @@ porta: gpio-port@0 { + #interrupt-cells = <2>; + interrupt-parent = <0x01>; + interrupts = <34>; ++ gpio-ranges = <&pmx0 0 0 16>; + }; + + portb: gpio-port@1 { +@@ -357,6 +369,7 @@ portb: gpio-port@1 { + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 16 0 8>; + }; + + portc: gpio-port@2 { +@@ -365,6 +378,7 @@ portc: gpio-port@2 { + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 24 0 8>; + }; + + portd: gpio-port@3 { +@@ -373,6 +387,7 @@ portd: gpio-port@3 { + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; ++ gpio-ranges = <&pmx0 32 0 8>; + }; + }; + +-- +2.53.0 + diff --git a/SPECS/linux/0258-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch b/SPECS/linux/0258-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch deleted file mode 100644 index 01f833c5b2..0000000000 --- a/SPECS/linux/0258-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch +++ /dev/null @@ -1,451 +0,0 @@ -From 29e0a47635e5c5bb1f29495c9d682c1aa752baa5 Mon Sep 17 00:00:00 2001 -From: Jia Wang -Date: Thu, 13 Feb 2025 15:50:12 +0800 -Subject: [PATCH 258/269] ULTRARISC: hwmon: add corepvt driver of UltraRISC - DP1000 - -From: https://github.com/ultrarisc/linux-6.8.0/commit/2cb818e1179844847d3be752b978a4ee7e633bc3 - -UltraRISC Corepvt driver supports cluster voltage -and core temperature detection - -Signed-off-by: Jia Wang -Signed-off-by: Han Gao ---- - drivers/hwmon/Kconfig | 9 + - drivers/hwmon/Makefile | 1 + - drivers/hwmon/corepvt-ultrarisc.c | 390 ++++++++++++++++++++++++++++++ - 3 files changed, 400 insertions(+) - create mode 100644 drivers/hwmon/corepvt-ultrarisc.c - -diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig -index 328867242cb3..6c3e733b2efe 100644 ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -503,6 +503,15 @@ config SENSORS_CHIPCAP2 - To compile this driver as a module, choose M here: the module - will be called chipcap2. - -+config SENSORS_COREPVT_ULTRARISC -+ tristate "UltraRISC Core Voltage, Temperature sensor driver" -+ help -+ If you say yes here you get support for UltraRISC Core PVT sensor -+ embedded into the SoC. -+ -+ This driver can also be built as a module. If so, the module will be -+ called corepvt-ultrarisc. -+ - config SENSORS_CORSAIR_CPRO - tristate "Corsair Commander Pro controller" - depends on HID -diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile -index 5833c807c688..247cf3d0cda2 100644 ---- a/drivers/hwmon/Makefile -+++ b/drivers/hwmon/Makefile -@@ -61,6 +61,7 @@ obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o - obj-$(CONFIG_SENSORS_BT1_PVT) += bt1-pvt.o - obj-$(CONFIG_SENSORS_CGBC) += cgbc-hwmon.o - obj-$(CONFIG_SENSORS_CHIPCAP2) += chipcap2.o -+obj-$(CONFIG_SENSORS_COREPVT_ULTRARISC) += corepvt-ultrarisc.o - obj-$(CONFIG_SENSORS_CORETEMP) += coretemp.o - obj-$(CONFIG_SENSORS_CORSAIR_CPRO) += corsair-cpro.o - obj-$(CONFIG_SENSORS_CORSAIR_PSU) += corsair-psu.o -diff --git a/drivers/hwmon/corepvt-ultrarisc.c b/drivers/hwmon/corepvt-ultrarisc.c -new file mode 100644 -index 000000000000..3674eedefbda ---- /dev/null -+++ b/drivers/hwmon/corepvt-ultrarisc.c -@@ -0,0 +1,390 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Driver for UltraRISC Core PVT -+ * -+ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. -+ * -+ * Author: wangjia -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define COREPVT_CHL_OFFSET 0x1000 -+#define COREPVT_REG_CIR 0x0 -+#define COREPVT_REG_PSCR 0x04 -+#define COREPVT_REG_CFDR 0x08 -+#define COREPVT_REG_DOR 0x0C -+#define COREPVT_REG_ICR 0x10 -+#define COREPVT_REG_IER 0x14 -+#define COREPVT_REG_IMSR 0x18 -+#define COREPVT_REG_IRSR 0x1C -+ -+#define PVT_MAX_CHANNEL 64 -+#define PVT_TRIM_DEFAULT 0x7 -+ -+struct corepvt_channel_config { -+ const char *label; -+ u32 trim; -+}; -+ -+struct corepvt_cal_data { -+ u32 val_offset; -+ u32 val_lsb; -+}; -+ -+struct corepvt_data { -+ const struct hwmon_chip_info *chip_info; -+ u64 temp_chl_mask; -+ u64 vol_chl_mask; -+}; -+ -+struct corepvt_hwmon { -+ struct device *dev; -+ struct device *hwmon; -+ -+ void __iomem *regs; -+ int irq; -+ int clk_freq; -+ int channels; -+ const struct hwmon_chip_info *chip_info; -+ struct corepvt_channel_config config[PVT_MAX_CHANNEL]; -+ const struct corepvt_data *pvt_data; -+ raw_spinlock_t lock; -+}; -+ -+#define COREPVT_VOLTAGE_DATA_BASE 2065100 /* 2065.1 */ -+#define COREPVT_VOLTAGE_LSB 1682 /* 1.682 mV */ -+#define COREPVT_TEMP_DATA_BASE 27049000 /* 2704.9 */ -+#define COREPVT_TEMP_LSB 22632 /* 2.2632 Celsius */ -+ -+static int corepvt_read_vol(struct corepvt_hwmon *pvt, -+ int channel, long *val) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ u32 dout; -+ u32 chl_offset = 0; -+ -+ // Assume that the voltage channel is continuous -+ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ *val = ((long)dout * 1000 - COREPVT_VOLTAGE_DATA_BASE) / COREPVT_VOLTAGE_LSB; -+ -+ return 0; -+} -+ -+static int corepvt_read_temp(struct corepvt_hwmon *pvt, -+ int channel, long *val) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ u32 dout; -+ u32 chl_offset = 0; -+ -+ // Assume that the temperature channel is continuous -+ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ *val = ((long)dout * 10000 - COREPVT_TEMP_DATA_BASE) * 1000 / COREPVT_TEMP_LSB; -+ -+ return 0; -+} -+ -+static umode_t corepvt_is_visible(const void *drvdata, enum hwmon_sensor_types type, -+ u32 attr, int channel) -+{ -+ const struct corepvt_hwmon *pvt = drvdata; -+ -+ if (channel >= pvt->channels) -+ return 0; -+ -+ switch (type) { -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_input: -+ case hwmon_in_label: -+ return 0444; -+ } -+ break; -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_input: -+ case hwmon_temp_type: -+ case hwmon_temp_label: -+ return 0444; -+ } -+ break; -+ default: -+ return 0; -+ } -+ -+ return 0; -+} -+ -+static int corepvt_read(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long *val) -+{ -+ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); -+ -+ switch (type) { -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_input: -+ return corepvt_read_vol(pvt, channel, val); -+ } -+ break; -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_type: -+ *val = 1; -+ return 0; -+ case hwmon_temp_input: -+ return corepvt_read_temp(pvt, channel, val); -+ } -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ return -ENODATA; -+} -+ -+static int corepvt_read_string(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, const char **str) -+{ -+ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); -+ u32 chl_offset = 0; -+ -+ switch (type) { -+ case hwmon_in: -+ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); -+ break; -+ case hwmon_temp: -+ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); -+ break; -+ default: -+ return -ENODATA; -+ break; -+ } -+ -+ *str = pvt->config[channel + chl_offset].label; -+ -+ return 0; -+} -+ -+/* -+ * corepvt init process: -+ * 1. config SETUP time, should be 10us, set PSCR register -+ * 2. config CLKIN, should be 4MHz, set CFDR register -+ * 3. (TODO)config interrupt, set ICR/IER/IMSR/IRSR -+ * 4. config TRIM and enable PVT, set CIR -+ */ -+static int corepvt_init(struct corepvt_hwmon *pvt) -+{ -+ void __iomem *chl_base; -+ unsigned long flag; -+ /* -+ * SETUP time 10us = 100KHz -+ * PSCR = CLK_FREQ / 100KHz -+ */ -+ u32 pscr_val = pvt->clk_freq / 100000; -+ /* -+ * CFDR = CLK_FREQ / 4MHz / 2 -+ */ -+ u32 cfdr_val = pvt->clk_freq / 8000000; -+ /* -+ * CIR: -+ * bit[0]: PU_VTDC, set 1 to enable pvt -+ * bit[5:2]: TRIM -+ */ -+ u32 cir_val; -+ -+ raw_spin_lock_irqsave(&pvt->lock, flag); -+ for (int i = 0; i < pvt->channels; i++) { -+ chl_base = pvt->regs + COREPVT_CHL_OFFSET * i; -+ cir_val = (pvt->config[i].trim << 2) | 0x01; -+ writel_relaxed(pscr_val, chl_base + COREPVT_REG_PSCR); -+ writel_relaxed(cfdr_val, chl_base + COREPVT_REG_CFDR); -+ writel_relaxed(cir_val, chl_base + COREPVT_REG_CIR); -+ } -+ raw_spin_unlock_irqrestore(&pvt->lock, flag); -+ -+ return 0; -+} -+ -+static const struct hwmon_ops corepvt_hwmon_ops = { -+ .is_visible = corepvt_is_visible, -+ .read = corepvt_read, -+ .read_string = corepvt_read_string, -+}; -+ -+static int corepvt_probe_channel_from_dt(struct platform_device *pdev, struct corepvt_hwmon *pvt) -+{ -+ struct device_node *child; -+ int ret; -+ u32 channel; -+ const char *label; -+ u32 trim; -+ -+ for_each_child_of_node(pdev->dev.of_node, child) { -+ if (!of_node_name_eq(child, "channel")) -+ continue; -+ -+ ret = of_property_read_u32(child, "reg", &channel); -+ if (ret) -+ goto node_put; -+ -+ ret = of_property_read_string(child, "label", &label); -+ if (ret) -+ goto node_put; -+ -+ if (of_property_present(child, "trim")) -+ of_property_read_u32(child, "trim", &trim); -+ else -+ trim = PVT_TRIM_DEFAULT; -+ -+ pvt->config[channel].label = label; -+ pvt->config[channel].trim = trim; -+ } -+ -+ return 0; -+ -+node_put: -+ of_node_put(child); -+ return ret; -+} -+ -+static int corepvt_probe(struct platform_device *pdev) -+{ -+ struct corepvt_hwmon *pvt; -+ const struct corepvt_data *pvt_data; -+ int ret; -+ -+ pvt = devm_kzalloc(&pdev->dev, sizeof(*pvt), GFP_KERNEL); -+ if (!pvt) -+ return -ENOMEM; -+ -+ pvt->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(pvt->regs)) { -+ dev_err(&pdev->dev, "get ioremap resource failed\n"); -+ ret = -EINVAL; -+ goto free_pvt; -+ } -+ -+ if (device_property_present(&pdev->dev, "interrupts")) -+ pvt->irq = platform_get_irq(pdev, 0); -+ -+ ret = device_property_read_u32(&pdev->dev, "clock-frequency", &pvt->clk_freq); -+ if (ret) { -+ dev_err(&pdev->dev, "get clock-frequency failed\n"); -+ goto free_pvt; -+ } -+ -+ ret = device_property_read_u32(&pdev->dev, "channels", &pvt->channels); -+ if (ret) { -+ dev_err(&pdev->dev, "get channels failed\n"); -+ goto free_pvt; -+ } -+ -+ pvt_data = device_get_match_data(&pdev->dev); -+ if (!pvt_data) { -+ dev_err(&pdev->dev, "No chip info found\n"); -+ ret = -ENODATA; -+ goto free_pvt; -+ } -+ -+ pvt->dev = &pdev->dev; -+ pvt->chip_info = pvt_data->chip_info; -+ pvt->pvt_data = pvt_data; -+ -+ if (pdev->dev.of_node) { -+ ret = corepvt_probe_channel_from_dt(pdev, pvt); -+ if (ret) -+ dev_warn(&pdev->dev, "WARN: probe channel failed\n"); -+ } -+ -+ pvt->hwmon = devm_hwmon_device_register_with_info(&pdev->dev, "corepvt_ultrarisc", -+ pvt, pvt->chip_info, -+ NULL); -+ if (IS_ERR(pvt->hwmon)) { -+ dev_err(&pdev->dev, "register hwmon failed(%ld)\n", PTR_ERR(pvt->hwmon)); -+ ret = -EINVAL; -+ goto free_pvt; -+ } -+ -+ pvt->dev = &pdev->dev; -+ raw_spin_lock_init(&pvt->lock); -+ -+ // Config and enable corepvt -+ corepvt_init(pvt); -+ -+ return 0; -+ -+free_pvt: -+ devm_kfree(&pdev->dev, pvt); -+ return ret; -+} -+ -+static const struct hwmon_channel_info * const ur_dp1000_channel_info[] = { -+ HWMON_CHANNEL_INFO(temp, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL, -+ HWMON_T_INPUT | HWMON_T_LABEL), -+ HWMON_CHANNEL_INFO(in, -+ HWMON_I_INPUT | HWMON_I_LABEL, -+ HWMON_I_INPUT | HWMON_I_LABEL), -+ NULL -+}; -+ -+static const struct hwmon_chip_info ur_dp1000_chip_info = { -+ .ops = &corepvt_hwmon_ops, -+ .info = ur_dp1000_channel_info, -+}; -+ -+static struct corepvt_data ur_dp1000_pvt_data = { -+ .chip_info = &ur_dp1000_chip_info, -+ .temp_chl_mask = GENMASK_ULL(10, 0), -+ .vol_chl_mask = GENMASK_ULL(12, 11) -+}; -+ -+static const struct of_device_id corepvt_of_match[] = { -+ { .compatible = "ultrarisc,dp1000-pvt", .data = &ur_dp1000_pvt_data }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, corepvt_of_match); -+ -+static struct platform_driver corepvt_driver = { -+ .probe = corepvt_probe, -+ .driver = { -+ .name = "corepvt-ultrarisc", -+ .of_match_table = corepvt_of_match -+ } -+}; -+module_platform_driver(corepvt_driver); -+ -+MODULE_AUTHOR("Jia Wang "); -+MODULE_DESCRIPTION("corepvt-ultrarisc driver"); -+MODULE_LICENSE("GPL"); --- -2.53.0 - diff --git a/SPECS/linux/0259-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch b/SPECS/linux/0259-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch deleted file mode 100644 index 9d79c9cca4..0000000000 --- a/SPECS/linux/0259-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch +++ /dev/null @@ -1,732 +0,0 @@ -From 6fa416284cb97ce827fdc4da978983b9d903c46f Mon Sep 17 00:00:00 2001 -From: Han Gao -Date: Sun, 12 Apr 2026 02:50:03 +0800 -Subject: [PATCH 259/269] RUYI: SYNC: riscv: dts: dp1000: Update dp1000.dtsi - -FROM: https://github.com/ultrarisc/linux-6.8.0/commit/b4a00f2f96a9c7d8d550259292fd19568fe9beec - -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 521 ++++++++++++++++++++-- - 1 file changed, 489 insertions(+), 32 deletions(-) - -diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -index 78e0cda1fcb9..7b7016618dcd 100644 ---- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -+++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi -@@ -22,121 +22,491 @@ cpu0: cpu@0 { - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache0>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu0_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache0: l2-cache0 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu1: cpu@1 { - device_type = "cpu"; - reg = <0x1>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache1>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu1_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache1: l2-cache1 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu2: cpu@2 { - device_type = "cpu"; - reg = <0x2>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache2>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu2_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache2: l2-cache2 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu3: cpu@3 { - device_type = "cpu"; - reg = <0x3>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache3>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu3_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache3: l2-cache3 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster0_l3>; -+ }; - }; -+ - cpu4: cpu@4 { - device_type = "cpu"; - reg = <0x10>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache4>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu4_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache4: l2-cache4 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu5: cpu@5 { - device_type = "cpu"; - reg = <0x11>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache5>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu5_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache5: l2-cache5 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu6: cpu@6 { - device_type = "cpu"; - reg = <0x12>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; -- - clock-frequency = <2000000000>; -- -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache6>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu6_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache6: l2-cache6 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; - }; -+ - cpu7: cpu@7 { - device_type = "cpu"; - reg = <0x13>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdcbh"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", -+ "zbb","zbc","zbs","zicntr","zicsr", -+ "zifencei","zihpm","ziccif","ziccrse", -+ "ziccamoa","za64rs","zic64b","zicbom", -+ "zicbop","zicboz","zkt","zama16b", -+ "svade","ssccptr","sstvecd","sscounterenw", -+ "shcounterenw","shtvala","shvstvecd", -+ "shvsatpa","ssstrict","svvptc"; - mmu-type = "riscv,sv48"; - clock-frequency = <2000000000>; -+ /* L1 I-cache and D-cache: -+ * block-size 64B -+ * 4-way set associative, size 64KB -+ * per-core. -+ */ -+ d-cache-block-size = <64>; -+ d-cache-sets = <256>; -+ d-cache-size = <0x10000>; -+ i-cache-block-size = <64>; -+ i-cache-sets = <256>; -+ i-cache-size = <0x10000>; -+ next-level-cache = <&l2_cache7>; -+ riscv,cbom-block-size = <64>; -+ riscv,cbop-block-size = <64>; -+ riscv,cboz-block-size = <64>; - cpu7_intc:interrupt-controller { - #address-cells = <0x01>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - #interrupt-cells = <0x01>; - }; -+ l2_cache7: l2-cache7 { -+ /* L2 cache: -+ * cache-unified, block-size 64B -+ * 8-way set associative, size 512KB -+ * per-core. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <0x80000>; -+ cache-sets = <1024>; -+ cache-unified; -+ next-level-cache = <&cluster1_l3>; -+ }; -+ }; -+ -+ cpu-map { -+ cluster0: cluster0 { -+ core0 { -+ cpu = <&cpu0>; -+ }; -+ core1 { -+ cpu = <&cpu1>; -+ }; -+ core2 { -+ cpu = <&cpu2>; -+ }; -+ core3 { -+ cpu = <&cpu3>; -+ }; -+ -+ cluster0_l3: l3-cache0 { -+ /* L3 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 4MB -+ * per-cluster. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <3>; -+ cache-size = <0x400000>; -+ cache-sets = <0x1000>; -+ cache-unified; -+ next-level-cache = <&l4_cache>; -+ }; -+ }; -+ -+ cluster1: cluster1 { -+ core0 { -+ cpu = <&cpu4>; -+ }; -+ core1 { -+ cpu = <&cpu5>; -+ }; -+ core2 { -+ cpu = <&cpu6>; -+ }; -+ core3 { -+ cpu = <&cpu7>; -+ }; -+ cluster1_l3: l3-cache1 { -+ /* L3 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 4MB -+ * per-cluster. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <3>; -+ cache-size = <0x400000>; -+ cache-sets = <0x1000>; -+ cache-unified; -+ next-level-cache = <&l4_cache>; -+ }; -+ }; - }; - }; - -@@ -150,6 +520,20 @@ soc { - #size-cells = <0x02>; - compatible = "simple-bus"; - ranges; -+ -+ l4_cache: l4-cache { -+ /* L4 cache: -+ * cache-unified, block-size 64B -+ * 16-way set associative, size 16MB -+ * shared by the SoC. -+ */ -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <4>; -+ cache-size = <0x1000000>; -+ cache-sets = <0x4000>; -+ cache-unified; -+ }; - - clocks { - compatible = "simple-bus"; -@@ -160,6 +544,12 @@ device_clk: device_clk { - #clock-cells = <0>; - }; - -+ timer_clk: timer_clk { -+ compatible = "fixed-clock"; -+ clock-frequency = <50000000>; -+ #clock-cells = <0>; -+ }; -+ - csr_clk: csr_clk { - compatible = "fixed-clock"; - clock-frequency = <250000000>; -@@ -170,35 +560,102 @@ csr_clk: csr_clk { - clint: clint@8000000 { - compatible = "riscv,clint0"; - interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, -- <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -- <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -- <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -- <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -- <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -- <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -- <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; -+ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, -+ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, -+ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, -+ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, -+ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, -+ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, -+ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; - reg = <0x00 0x8000000 0x00 0x100000>; - }; -- -+ - plic: plic@9000000 { - #interrupt-cells = <1>; - #address-cells = <0>; -- phandle = <0x01>; -- compatible = "ultrarisc,dp1000-plic"; -+ compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; - interrupt-controller; - interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, -- <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -- <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -- <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -- <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -- <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -- <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -- <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; -+ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, -+ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, -+ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, -+ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, -+ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, -+ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, -+ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; - reg = <0x00 0x9000000 0x00 0x4000000>; - riscv,max-priority = <0x07>; - riscv,ndev = <160>; - }; -- -+ -+ core_pvt: pvt@110D0000 { -+ compatible = "ultrarisc,dp1000-pvt"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x00 0x110D0000 0x00 0x0000D000>; -+ clock-frequency = <250000000>; -+ channels = <13>; -+ -+ #thermal-sensor-cells = <1>; -+ channel@0 { -+ label = "Core temp0"; -+ reg = <0>; -+ }; -+ -+ channel@1 { -+ label = "Core temp1"; -+ reg = <1>; -+ }; -+ -+ channel@2 { -+ label = "Core temp2"; -+ reg = <2>; -+ }; -+ -+ channel@3 { -+ label = "Core temp3"; -+ reg = <3>; -+ }; -+ -+ channel@4 { -+ label = "Core temp4"; -+ reg = <4>; -+ }; -+ -+ channel@5 { -+ label = "Core temp5"; -+ reg = <5>; -+ }; -+ channel@6 { -+ label = "Core temp6"; -+ reg = <6>; -+ }; -+ channel@7 { -+ label = "Core temp7"; -+ reg = <7>; -+ }; -+ channel@8 { -+ label = "Core temp8"; -+ reg = <8>; -+ }; -+ channel@9 { -+ label = "Core temp9"; -+ reg = <9>; -+ }; -+ channel@10 { -+ label = "Core temp10"; -+ reg = <10>; -+ }; -+ channel@11 { -+ label = "Cluster0 voltage"; -+ reg = <11>; -+ }; -+ channel@12 { -+ label = "Cluster1 voltage"; -+ reg = <12>; -+ }; -+ }; -+ - uart0: serial@20300000 { - interrupt-parent = <0x01>; - interrupts = <17>; -@@ -244,7 +701,7 @@ uart3: serial@20410000 { - }; - - spi0: spi@20320000 { -- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ compatible = "snps,dw-apb-ssi"; - status = "okay"; - #address-cells = <0x01>; - #size-cells = <0x00>; -@@ -258,7 +715,7 @@ spi0: spi@20320000 { - }; - - spi1: spi@20420000 { -- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; -+ compatible = "snps,dw-apb-ssi"; - status = "okay"; - #address-cells = <0x01>; - #size-cells = <0x00>; -@@ -449,11 +906,11 @@ pcie_x16: pcie@21000000 { - num-lanes = <16>; - ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -- max-link-speed = <4>; -+ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ -+ max-link-speed = <16>; - interrupt-parent = <&plic>; -- interrupts = <43>, <44>, <45>, <46>, <47>, <48>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <43>, <44>, <45>, <46>, <47>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, - <0x0 0x0 0x0 0x2 &plic 45>, -@@ -475,11 +932,11 @@ pcie_x4a: pcie@23000000 { - num-lanes = <4>; - ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ - max-link-speed = <4>; - interrupt-parent = <&plic>; -- interrupts = <63>, <64>, <65>, <66>, <67>, <68>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <63>, <64>, <65>, <66>, <67>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, - <0x0 0x0 0x0 0x2 &plic 65>, -@@ -501,11 +958,11 @@ pcie_x4b: pcie@24000000 { - num-lanes = <4>; - ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ - <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ -- <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ -+ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ - max-link-speed = <4>; - interrupt-parent = <&plic>; -- interrupts = <73>, <74>, <75>, <76>, <77>, <78>; -- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; -+ interrupts = <73>, <74>, <75>, <76>, <77>; -+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, - <0x0 0x0 0x0 0x2 &plic 75>, --- -2.53.0 - diff --git a/SPECS/linux/0259-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch b/SPECS/linux/0259-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch new file mode 100644 index 0000000000..87eddd9b6b --- /dev/null +++ b/SPECS/linux/0259-RVCK-riscv-pinctrl-ultrarisc-Implement-pin-configura.patch @@ -0,0 +1,166 @@ +From 4daa2d6183ff55da8d8c28090a8cc2c128ee4991 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Wed, 12 Nov 2025 15:43:27 +0800 +Subject: [RUYI PATCH] RVCK: riscv: pinctrl: ultrarisc: Implement pin + configuration support + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +-------------------------------- + +Update ur_pin_config_set() to use the new configuration handling logic. +This allows the driver to properly handle standard Linux kernel pin +configuration parameters such as PIN_CONFIG_BIAS_PULL_UP, +PIN_CONFIG_BIAS_PULL_DOWN, etc. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/d094389a972a4b03d04b77a47c19f5c9c9fb0627 +Signed-off-by: Han Gao +--- + .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 + + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 83 +++++++++++++++++-- + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h | 2 +- + 3 files changed, 77 insertions(+), 9 deletions(-) + +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +index 217f671fe63a..6a7496a465d8 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +@@ -86,6 +86,7 @@ static struct ur_pinctrl_match_data ur_dp1000_match_data = { + .pins = ur_dp1000_pins, + .npins = ARRAY_SIZE(ur_dp1000_pins), + .offset = 0x2c0, ++ .num_ports = 5, + .ports = { + {"A", 16, 0x2c0, 0x310}, + {"B", 8, 0x2c4, 0x318}, +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +index 667d59e0ac6e..edaeca881af7 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +@@ -326,6 +326,58 @@ static const struct pinmux_ops ur_pinmux_ops = { + + #define UR_CONF_BIT_PER_PIN (4) + #define UR_CONF_PIN_PER_REG (32/UR_CONF_BIT_PER_PIN) ++ ++static int ur_pin_num_to_port_pin(const struct ur_pinctrl_match_data *match_data, ++ struct ur_pin_val *pin_val, u32 pin_num) ++{ ++ const struct ur_port_desc *port_desc; ++ ++ for (int i = 0; i < match_data->num_ports; i++) { ++ port_desc = &match_data->ports[i]; ++ if (pin_num < port_desc->npins) { ++ pin_val->port = i; ++ pin_val->pin = pin_num; ++ pin_val->conf = 0; ++ return 0; ++ } ++ pin_num -= port_desc->npins; ++ } ++ return -EINVAL; ++} ++ ++static int ur_config_to_pin_val(struct ur_pinctrl *pin_ctrl, ++ struct ur_pin_val *pin_vals, ++ unsigned long *config) ++{ ++ enum pin_config_param param = pinconf_to_config_param(*config); ++ u32 arg = pinconf_to_config_argument(*config); ++ ++ dev_dbg(pin_ctrl->dev, "%s(%d): config_to_pin_val: param=%d, arg=0x%x\n", ++ __func__, __LINE__, param, arg); ++ ++ switch (param) { ++ case PIN_CONFIG_BIAS_DISABLE: ++ pin_vals->conf &= ~UR_BIAS_MASK; ++ break; ++ case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: ++ pin_vals->conf &= ~(UR_PULL_DOWN | UR_PULL_UP); ++ break; ++ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: ++ case PIN_CONFIG_BIAS_PULL_DOWN: ++ pin_vals->conf |= UR_PULL_DOWN; ++ break; ++ case PIN_CONFIG_BIAS_PULL_UP: ++ pin_vals->conf |= UR_PULL_UP; ++ break; ++ case PIN_CONFIG_DRIVE_PUSH_PULL: ++ case PIN_CONFIG_PERSIST_STATE: ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ return 0; ++} ++ + static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_vals) + { + const struct ur_port_desc *port_desc; +@@ -334,8 +386,11 @@ static int ur_set_pin_conf(struct ur_pinctrl *pin_ctrl, struct ur_pin_val *pin_v + u32 val, conf; + + port_desc = &pin_ctrl->match_data->ports[pin_vals->port]; ++ dev_dbg(pin_ctrl->dev, "set pinconf port=%d pin=%d conf=0x%x\n", ++ pin_vals->port, pin_vals->pin, pin_vals->conf); + reg = pin_ctrl->base + port_desc->conf_offset; +- dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, reg=0x%llx\n", (u64)pin_ctrl->base, (u64)reg); ++ dev_dbg(pin_ctrl->dev, "pinconf base=0x%llx, conf_offset=0x%x, reg=0x%llx\n", ++ (u64)pin_ctrl->base, port_desc->conf_offset, (u64)reg); + reg += (pin_vals->pin / UR_CONF_PIN_PER_REG) * UR_CONF_BIT_PER_PIN; + dev_dbg(pin_ctrl->dev, "pinconf pin=0x%llx\n", (u64)reg); + +@@ -367,16 +422,28 @@ static int ur_pin_config_set(struct pinctrl_dev *pctldev, + unsigned long *configs, + unsigned int num_configs) + { +- struct ur_pin_val *pin_conf; ++ struct ur_pin_val pin_val; + struct ur_pinctrl *ur_pinctrl = pinctrl_dev_get_drvdata(pctldev); ++ int ret; ++ ++ ret = ur_pin_num_to_port_pin(ur_pinctrl->match_data, &pin_val, pin); ++ if (ret < 0) { ++ dev_err(pctldev->dev, "invalid pin number %d\n", pin); ++ return ret; ++ } ++ dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d, port=%d, pin=%d\n", ++ __func__, __LINE__, pin, num_configs, pin_val.port, pin_val.pin); + +- dev_dbg(pctldev->dev, "%s(%d): pin=%d, num_configs=%d\n", +- __func__, __LINE__, pin, num_configs); +- pin_conf = (struct ur_pin_val *)configs; + for (int i = 0; i < num_configs; i++) { +- dev_dbg(pctldev->dev, "pinconf[%d], port=%d, pin=%d, conf=0x%x\n", +- i, pin_conf[i].port, pin_conf[i].pin, pin_conf[i].conf); +- ur_set_pin_conf(ur_pinctrl, &pin_conf[i]); ++ ret = ur_config_to_pin_val(ur_pinctrl, &pin_val, &configs[i]); ++ if (ret < 0) { ++ dev_err(pctldev->dev, "invalid config 0x%lx\n", configs[i]); ++ return ret; ++ } ++ ++ dev_dbg(pctldev->dev, "%s(%d): port=%d, pin=%d, conf=0x%x\n", ++ __func__, __LINE__, pin_val.port, pin_val.pin, pin_val.conf); ++ ur_set_pin_conf(ur_pinctrl, &pin_val); + } + return 0; + } +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +index eec621bf8b05..728b2111def0 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.h +@@ -50,7 +50,7 @@ struct ur_pinctrl_match_data { + const struct pinctrl_pin_desc *pins; + u32 npins; + u32 offset; +- //u32 conf_offset[]; ++ u32 num_ports; + struct ur_port_desc ports[]; + }; + +-- +2.53.0 + diff --git a/SPECS/linux/0260-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch b/SPECS/linux/0260-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch deleted file mode 100644 index a1d1817da9..0000000000 --- a/SPECS/linux/0260-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 11210e1596fbaf59ea34ac7512e6b062b4411db8 Mon Sep 17 00:00:00 2001 -From: Yixun Lan -Date: Sat, 24 Jan 2026 08:48:53 +0800 -Subject: [PATCH 260/269] RUYI: riscv: dts: spacemit: k3: Add USB2.0 support - -FROM: https://github.com/spacemit-com/linux/commit/6f1578894e4484f8a6724aceff099d2e90450e10 - -The USB2.0 controller on Pico-ITX board connnect to a Terminus FE1.1 Hub -which fully USB2.0 protocol compliant and provides 4 ports. - -Signed-off-by: Yixun Lan -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 25 ++++++++++++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++ - 2 files changed, 56 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index 61cbf924830b..ac965ec83f2c 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -33,6 +33,15 @@ reg_aux_vcc5v: regulator-aux-vcc5v { - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -+ -+ aux_vcc3v3: regulator-aux-vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "AUX_VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ - }; - - &i2c8 { -@@ -255,3 +264,19 @@ &uart0 { - pinctrl-0 = <&uart0_0_cfg>; - status = "okay"; - }; -+ -+&usb2_host { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ hub@1 { -+ compatible = "usb1a40,0101"; -+ reg = <1>; -+ vdd-supply = <&aux_vcc3v3>; -+ }; -+}; -+ -+&usb2_phy { -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 5b17612fe58e..66dcabd0a815 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -637,6 +637,37 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ usb2_host: usb@c0a00000 { -+ compatible = "spacemit,k3-dwc3"; -+ reg = <0x0 0xc0a00000 0x0 0x10000>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ clock-names = "usbdrd30"; -+ resets = <&syscon_apmu RESET_APMU_USB2_AHB>, -+ <&syscon_apmu RESET_APMU_USB2_VCC>, -+ <&syscon_apmu RESET_APMU_USB2_PHY>; -+ reset-names = "ahb", "vcc", "phy"; -+ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&saplic>; -+ phys = <&usb2_phy>; -+ phy-names = "usb2-phy"; -+ phy_type = "utmi"; -+ snps,dis_enblslpm_quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ dr_mode = "host"; -+ maximum-speed = "high-speed"; -+ status = "disabled"; -+ }; -+ -+ usb2_phy: phy@c0a20000 { -+ compatible = "spacemit,k3-usb2-phy"; -+ reg = <0x0 0xc0a20000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - syscon_apbc: system-controller@d4015000 { - compatible = "spacemit,k3-syscon-apbc"; - reg = <0x0 0xd4015000 0x0 0x1000>; --- -2.53.0 - diff --git a/SPECS/linux/0260-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch b/SPECS/linux/0260-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch new file mode 100644 index 0000000000..8cdb99260c --- /dev/null +++ b/SPECS/linux/0260-RVCK-riscv-dts-dp1000-add-dts-dtsi-for-Milk-V-Titan-.patch @@ -0,0 +1,364 @@ +From e0554496321a0e050cd5b45a85d8722c0e6b4510 Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Tue, 18 Nov 2025 13:48:49 +0800 +Subject: [RUYI PATCH] RVCK: riscv: dts: dp1000: add dts/dtsi for Milk-V Titan + board based on UltraRISC DP1000 SoC + +community inclusion +category: feature +bugzilla: https://github.com/RVCK-Project/rvck/issues/71 + +-------------------------------- + +Add dp1000-titan-v1.dts and dp1000-titan-pinctrl.dtsi for the Milk-V Titan +board. The Titan board is designed by Milk-V and is based on the UltraRISC +DP1000 SoC. These device tree files provide the initial support for the +board, including pinctrl and basic peripheral configuration. + +Signed-off-by: Jia Wang +FROM: https://github.com/RVCK-Project/rvck/commit/edab885e252d0442ccf52b2b554934138b82b2ec +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/Makefile | 1 + + .../dts/ultrarisc/dp1000-titan-pinctrl.dtsi | 173 ++++++++++++++++++ + .../boot/dts/ultrarisc/dp1000-titan-v1.dts | 139 ++++++++++++++ + 3 files changed, 313 insertions(+) + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts + +diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile +index 22c03b44b2f8..df8efe1a3ed7 100644 +--- a/arch/riscv/boot/dts/ultrarisc/Makefile ++++ b/arch/riscv/boot/dts/ultrarisc/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-evb-v1.dtb + dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-mo-v1.dtb ++dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-titan-v1.dtb +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi +new file mode 100644 +index 000000000000..35429e539832 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-pinctrl.dtsi +@@ -0,0 +1,173 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include ++#include "dp1000.dtsi" ++ ++&pmx0 { ++ i2c0_pins: i2c0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 12 UR_FUNC0 ++ UR_DP1000_IOMUX_A 13 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 12 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 13 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c1_pins: i2c1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 6 UR_FUNC0 ++ UR_DP1000_IOMUX_B 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c2_pins: i2c2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 0 UR_FUNC0 ++ UR_DP1000_IOMUX_C 1 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ i2c3_pins: i2c3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 2 UR_FUNC0 ++ UR_DP1000_IOMUX_C 3 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart0_pins: uart0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 8 UR_FUNC1 ++ UR_DP1000_IOMUX_A 9 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 8 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 9 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart1_pins: uart1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_B 4 UR_FUNC0 ++ UR_DP1000_IOMUX_B 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_B 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart2_pins: uart2_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 4 UR_FUNC0 ++ UR_DP1000_IOMUX_C 5 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ uart3_pins: uart3_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_C 6 UR_FUNC0 ++ UR_DP1000_IOMUX_C 7 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_C 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_C 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi0_pins: spi0_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_D 0 UR_FUNC1 ++ UR_DP1000_IOMUX_D 1 UR_FUNC1 ++ UR_DP1000_IOMUX_D 2 UR_FUNC1 ++ UR_DP1000_IOMUX_D 3 UR_FUNC1 ++ UR_DP1000_IOMUX_D 4 UR_FUNC1 ++ UR_DP1000_IOMUX_D 5 UR_FUNC1 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_D 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 5 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ spi1_pins: spi1_pins { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 0 UR_FUNC0 ++ UR_DP1000_IOMUX_A 1 UR_FUNC0 ++ UR_DP1000_IOMUX_A 2 UR_FUNC0 ++ UR_DP1000_IOMUX_A 3 UR_FUNC0 ++ UR_DP1000_IOMUX_A 4 UR_FUNC0 ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 3 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 4 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++ ++ gpios_pin: gpios_pin { ++ pinctrl-pins = < ++ UR_DP1000_IOMUX_A 10 UR_FUNC_DEF ++ UR_DP1000_IOMUX_A 11 UR_FUNC_DEF ++ UR_DP1000_IOMUX_A 14 UR_FUNC_DEF ++ UR_DP1000_IOMUX_A 15 UR_FUNC_DEF ++ ++ UR_DP1000_IOMUX_B 0 UR_FUNC_DEF ++ UR_DP1000_IOMUX_B 1 UR_FUNC_DEF ++ UR_DP1000_IOMUX_B 2 UR_FUNC_DEF ++ ++ UR_DP1000_IOMUX_D 6 UR_FUNC_DEF ++ UR_DP1000_IOMUX_D 7 UR_FUNC_DEF ++ >; ++ ++ pinconf-pins = < ++ UR_DP1000_IOMUX_A 10 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 11 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 14 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_A 15 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ ++ UR_DP1000_IOMUX_B 0 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 1 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_B 2 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ ++ UR_DP1000_IOMUX_D 6 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ UR_DP1000_IOMUX_D 7 UR_DP1000_BIAS(UR_PULL_UP, UR_DRIVE_DEF) ++ >; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts +new file mode 100644 +index 000000000000..2cbdfa2ad813 +--- /dev/null ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000-titan-v1.dts +@@ -0,0 +1,139 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ */ ++ ++#include "dp1000-titan-pinctrl.dtsi" ++#include ++#include ++#include ++#include ++ ++/ { ++ chosen { ++ bootargs = "earlycon=sbi console=ttyS0,115200"; ++ stdout-path = &uart0; ++ }; ++ ++ gpio-poweroff { ++ compatible = "gpio-poweroff"; ++ gpios = <&portb 0 GPIO_ACTIVE_LOW>; ++ active-delay-ms = <100>; ++ line-name = "power-off"; ++ status = "okay"; ++ }; ++ ++ gpio-restart { ++ compatible = "gpio-restart"; ++ gpios = <&portb 1 GPIO_ACTIVE_LOW>; ++ active-delay-ms = <100>; ++ line-name = "reset-system"; ++ status = "okay"; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ key-wakeup { ++ label = "Wake-Up"; ++ gpios = <&porta 14 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ linux,input-type = ; ++ debounce-interval = <10>; ++ wakeup-source; ++ wakeup-event-action = ; ++ }; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ ++ rtc@68 { ++ compatible = "st,m41t11"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++}; ++ ++&spi1 { ++ num-cs = <1>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins>; ++}; ++ ++&porta { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpios_pin>; ++ ++ i2c1-mux-hog { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ /* LOW: DCDC(U6) connect MCU(EC) ++ * HIGH: DCDC(U6) connect CPU ++ */ ++ output-low; ++ line-name = "gpio-mux-dcdc"; ++ }; ++ ++ i2c3-mux-hog { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_LOW>; ++ /* LOW: CPU i2c3 connect nvme ++ * HIGH: CPU i2c3 connect pciex16 ++ */ ++ output-low; ++ line-name = "gpio-mux-i2c3"; ++ }; ++ ++ uart0-mux-hog { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ /* LOW: uart_debug connect BMC ++ * HIGH: uart_debug connect CPU ++ */ ++ output-high; ++ line-name = "gpio-mux-debug"; ++ }; ++}; +-- +2.53.0 + diff --git a/SPECS/linux/0261-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch b/SPECS/linux/0261-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch new file mode 100644 index 0000000000..5bc833ea53 --- /dev/null +++ b/SPECS/linux/0261-REVYSR-pinctrl-ultrarisc-cleanup-probe-remove.patch @@ -0,0 +1,77 @@ +From cdb1be3102f50b00e304a08c398e50a32865f998 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Mon, 23 Feb 2026 14:35:29 +0800 +Subject: [RUYI PATCH] REVYSR: pinctrl: ultrarisc: cleanup probe&remove + +Signed-off-by: Han Gao +--- + .../ultrarisc/pinctrl-ultrarisc-dp1000.c | 1 - + drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c | 22 +++---------------- + 2 files changed, 3 insertions(+), 20 deletions(-) + +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +index 6a7496a465d8..0ead138c9d1f 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc-dp1000.c +@@ -117,7 +117,6 @@ static struct platform_driver ur_pinctrl_driver = { + .of_match_table = ur_pinctrl_of_match, + }, + .probe = ur_pinctrl_probe, +- .remove = ur_pinctrl_remove, + }; + + module_platform_driver(ur_pinctrl_driver); +diff --git a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +index edaeca881af7..cdd7160f3183 100644 +--- a/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c ++++ b/drivers/pinctrl/ultrarisc/pinctrl-ultrarisc.c +@@ -514,8 +514,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) + ur_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*ur_pinctrl), GFP_KERNEL); + if (!ur_pinctrl) { + dev_err(&pdev->dev, "pinctrl alloc failed\n"); +- ret = -ENOMEM; +- goto free_pinctrl_desc; ++ return -ENOMEM; + } + struct resource *res; + +@@ -524,8 +523,7 @@ int ur_pinctrl_probe(struct platform_device *pdev) + ur_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ur_pinctrl->base)) { + dev_err(&pdev->dev, "get ioremap resource failed\n"); +- ret = -EINVAL; +- goto free_pinctrl_desc; ++ return -EINVAL; + } + dev_dbg(&pdev->dev, "pinctrl base=0x%p\n", ur_pinctrl->base); + ur_pinctrl_desc->name = dev_name(&pdev->dev); +@@ -546,25 +544,11 @@ int ur_pinctrl_probe(struct platform_device *pdev) + ur_pinctrl, &ur_pinctrl->pctl_dev); + if (ret) { + dev_err(&pdev->dev, "pinctrl register failed\n"); +- goto free_pinctrl; ++ return ret; + } + + platform_set_drvdata(pdev, ur_pinctrl); + + return pinctrl_enable(ur_pinctrl->pctl_dev); +- +-free_pinctrl: +- devm_kfree(&pdev->dev, ur_pinctrl); +-free_pinctrl_desc: +- devm_kfree(&pdev->dev, ur_pinctrl_desc); +- return ret; + } + +- +-void ur_pinctrl_remove(struct platform_device *pdev) +-{ +- struct ur_pinctrl *ur_pinctrl = platform_get_drvdata(pdev); +- +- if (ur_pinctrl->pctl_dev) +- devm_pinctrl_unregister(&pdev->dev, ur_pinctrl->pctl_dev); +-} +-- +2.53.0 + diff --git a/SPECS/linux/0261-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch b/SPECS/linux/0261-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch deleted file mode 100644 index 93274ec618..0000000000 --- a/SPECS/linux/0261-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch +++ /dev/null @@ -1,145 +0,0 @@ -From 9052e73c75db5b4942063315480e91d0615cf101 Mon Sep 17 00:00:00 2001 -From: Zhang Meng -Date: Mon, 5 Jan 2026 20:05:04 +0800 -Subject: [PATCH 261/269] SPACEMIT: riscv: uaccess: don't use vector if buffer - is not cacheable - -FROM: https://github.com/spacemit-com/linux-6.18/commit/9168f7e0c6bfdcfa3b6a64a4d45e3cd68a81618f - -Change-Id: I040d597ee246777767f7be747fa9202154524538 -[ Vivian: Rebase and move check into enter_vector_usercopy ] -Signed-off-by: Vivian Wang -Signed-off-by: Han Gao ---- - arch/riscv/include/asm/uaccess.h | 5 +++ - arch/riscv/lib/Makefile | 1 + - arch/riscv/lib/riscv_v_helpers.c | 5 +++ - arch/riscv/lib/uaccess_cache_check.c | 65 ++++++++++++++++++++++++++++ - 4 files changed, 76 insertions(+) - create mode 100644 arch/riscv/lib/uaccess_cache_check.c - -diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h -index 11c9886c3b70..69bdc070f420 100644 ---- a/arch/riscv/include/asm/uaccess.h -+++ b/arch/riscv/include/asm/uaccess.h -@@ -487,6 +487,11 @@ static inline void user_access_restore(unsigned long enabled) { } - if (__asm_copy_from_user_sum_enabled(_dst, _src, _len)) \ - goto label; - -+/* Memory cacheability check for vector uaccess optimization */ -+#ifdef CONFIG_RISCV_ISA_V -+int is_cacheable_safe(const void *addr); -+#endif -+ - #else /* CONFIG_MMU */ - #include - #endif /* CONFIG_MMU */ -diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile -index 735d0b665536..43fe69db9803 100644 ---- a/arch/riscv/lib/Makefile -+++ b/arch/riscv/lib/Makefile -@@ -14,6 +14,7 @@ endif - lib-y += csum.o - ifeq ($(CONFIG_MMU), y) - lib-$(CONFIG_RISCV_ISA_V) += uaccess_vector.o -+lib-$(CONFIG_RISCV_ISA_V) += uaccess_cache_check.o - endif - lib-$(CONFIG_MMU) += uaccess.o - lib-$(CONFIG_64BIT) += tishift.o -diff --git a/arch/riscv/lib/riscv_v_helpers.c b/arch/riscv/lib/riscv_v_helpers.c -index 7bbdfc6d4552..7ab2cea280f8 100644 ---- a/arch/riscv/lib/riscv_v_helpers.c -+++ b/arch/riscv/lib/riscv_v_helpers.c -@@ -8,6 +8,7 @@ - - #include - #include -+#include - - #ifdef CONFIG_MMU - #include -@@ -28,6 +29,10 @@ asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n, - if (!may_use_simd()) - goto fallback; - -+ /* HACK */ -+ if (!is_cacheable_safe(dst) || !is_cacheable_safe(src)) -+ goto fallback; -+ - kernel_vector_begin(); - remain = enable_sum ? __asm_vector_usercopy(dst, src, n) : - __asm_vector_usercopy_sum_enabled(dst, src, n); -diff --git a/arch/riscv/lib/uaccess_cache_check.c b/arch/riscv/lib/uaccess_cache_check.c -new file mode 100644 -index 000000000000..0b0996fa2d37 ---- /dev/null -+++ b/arch/riscv/lib/uaccess_cache_check.c -@@ -0,0 +1,65 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Memory cacheability check for RISC-V uaccess optimization -+ * -+ * This file provides a C function that can be called from assembly -+ * to determine if a buffer is cacheable before using vector instructions. -+ */ -+ -+#include -+#include -+#include -+ -+/** -+ * is_cacheable_safe - Check if memory buffer is cacheable -+ * @addr: Virtual address to check (kernel or user space) -+ * -+ * Returns: 1 if cacheable, 0 if non-cacheable -+ * -+ * This function is designed to be called from assembly code in uaccess.S -+ * to determine if vector instructions are safe to use for memory copy. -+ * -+ * Non-cacheable memory (device IO, DMA coherent buffers) should not use -+ * vector instructions as they may cause cache coherency issues. -+ * -+ * Handles both kernel and user space addresses safely: -+ * - Kernel direct mapping: Always cacheable -+ * - Kernel vmalloc: Check VM flags -+ * - User space: Check page table (most are cacheable) -+ * - ioremap/DMA: Non-cacheable -+ */ -+int is_cacheable_safe(const void *addr) -+{ -+ unsigned long vaddr = (unsigned long)addr; -+ -+ /* Kernel direct mapped memory - always cacheable */ -+ if (virt_addr_valid(addr)) -+ return 1; -+ -+ if (vaddr < TASK_SIZE) { -+ /* -+ * User space address, Determine it as a cacheable buffer, -+ * maybe not safe!! -+ */ -+ return 1; -+ } -+ -+ /* Check if it's a vmalloc region (kernel virtual address) */ -+ if (is_vmalloc_addr(addr)) { -+ struct vm_struct *vm; -+ -+ vm = find_vm_area(addr); -+ if (!vm) -+ return 0; -+ -+ /* Exclude ioremap and DMA coherent buffers */ -+ if (vm->flags & (VM_IOREMAP | VM_DMA_COHERENT)) -+ return 0; -+ -+ /* Normal vmalloc - cacheable */ -+ return 1; -+ } -+ -+ /* Unknown kernel region - assume non-cacheable for safety */ -+ return 0; -+} --- -2.53.0 - diff --git a/SPECS/linux/0262-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch b/SPECS/linux/0262-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch new file mode 100644 index 0000000000..a31f03e438 --- /dev/null +++ b/SPECS/linux/0262-REVYSR-riscv-dp1000-dts-use-ultrarisc-dp1000-pcie-fo.patch @@ -0,0 +1,46 @@ +From 0ddae06d8aac7e0959f742ba9141cc4fade954d0 Mon Sep 17 00:00:00 2001 +From: U2FsdGVkX1 +Date: Sun, 29 Mar 2026 15:31:14 +0000 +Subject: [RUYI PATCH] REVYSR: riscv: dp1000: dts: use ultrarisc,dp1000-pcie + for PCIe nodes + +Signed-off-by: U2FsdGVkX1 +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +index a25e87e15553..78e0cda1fcb9 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +@@ -436,7 +436,7 @@ dmac: dma-controller@39000000 { + }; + + pcie_x16: pcie@21000000 { +- compatible = "ultrarisc,dw-pcie"; ++ compatible = "ultrarisc,dp1000-pcie"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; +@@ -462,7 +462,7 @@ pcie_x16: pcie@21000000 { + }; + + pcie_x4a: pcie@23000000 { +- compatible = "ultrarisc,dw-pcie"; ++ compatible = "ultrarisc,dp1000-pcie"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; +@@ -488,7 +488,7 @@ pcie_x4a: pcie@23000000 { + }; + + pcie_x4b: pcie@24000000 { +- compatible = "ultrarisc,dw-pcie"; ++ compatible = "ultrarisc,dp1000-pcie"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; +-- +2.53.0 + diff --git a/SPECS/linux/0262-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch b/SPECS/linux/0262-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch deleted file mode 100644 index 0f14467566..0000000000 --- a/SPECS/linux/0262-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch +++ /dev/null @@ -1,90 +0,0 @@ -From d063e7ddc6ce6c0a4f1729b54ae41212b09237ad Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 13 Feb 2026 09:01:58 +0800 -Subject: [PATCH 262/269] RUYI: dt-bindings: phy: Add Spacemit K3 USB3/PCIe - comb phy support - -The USB3/PCIe comb PHY on the K3 is a complex PHY group that -can provide multiple phy for both PCIe and USB controller. -Its mux configuration is controlled by the APMU syscon device. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - .../bindings/phy/spacemit,k3-combo-phy.yaml | 64 +++++++++++++++++++ - 1 file changed, 64 insertions(+) - create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml - -diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml -new file mode 100644 -index 000000000000..eafc753b7e9b ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml -@@ -0,0 +1,64 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Spacemit K3 PCIE/USB3 Comb PHY -+ -+maintainers: -+ - Inochi Amaoto -+ -+properties: -+ compatible: -+ const: spacemit,k3-combo-phy -+ -+ reg: -+ maxItems: 1 -+ -+ "#phy-cells": -+ const: 2 -+ description: -+ The first one is phy id, the second one is phy type. -+ -+ spacemit,apb-spare: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: -+ Phandle to APB SPARE system controller interface, used for -+ PHY calibration. -+ -+ spacemit,apmu: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ items: -+ - items: -+ - description: phandle of APMU syscon -+ - description: configuration of the PHY lanes -+ description: | -+ Phandle to control PHY mux configuration. The configuration -+ is described as follows: -+ bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode -+ bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode -+ bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode -+ bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode -+ bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode -+ -+ The bit[3:0] is only valid when bit 4 is 1. -+ -+required: -+ - compatible -+ - reg -+ - "#phy-cells" -+ - spacemit,apb-spare -+ - spacemit,apmu -+ -+additionalProperties: false -+ -+examples: -+ - | -+ phy@81d00000 { -+ compatible = "spacemit,k3-combo-phy"; -+ reg = <0x81d00000 0x600000>; -+ #phy-cells = <2>; -+ spacemit,apb-spare = <&apb_spare>; -+ spacemit,apmu = <&apmu 0x00>; -+ }; --- -2.53.0 - diff --git a/SPECS/linux/0263-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch b/SPECS/linux/0263-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch deleted file mode 100644 index db8f4003f9..0000000000 --- a/SPECS/linux/0263-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch +++ /dev/null @@ -1,730 +0,0 @@ -From a6d7eca53960ff1034a30648531b0ca503716c5f Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 13 Feb 2026 09:09:58 +0800 -Subject: [PATCH 263/269] RUYI: phy: spacemit: Add USB3/PCIe comb PHY driver - for Spacemit K3 - -The comb PHY on K3 requires to configure a syscon device for the -right mux configuration. And it requires calibration before any -usage. - -Add USB3/PCIe comb PHY driver for Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - drivers/phy/spacemit/Kconfig | 16 ++ - drivers/phy/spacemit/Makefile | 2 + - drivers/phy/spacemit/phy-k3-combo.c | 252 ++++++++++++++++++ - drivers/phy/spacemit/phy-k3-common.c | 372 +++++++++++++++++++++++++++ - drivers/phy/spacemit/phy-k3-common.h | 27 ++ - 5 files changed, 669 insertions(+) - create mode 100644 drivers/phy/spacemit/phy-k3-combo.c - create mode 100644 drivers/phy/spacemit/phy-k3-common.c - create mode 100644 drivers/phy/spacemit/phy-k3-common.h - -diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig -index 0136aee2e8a2..9a1e25592f25 100644 ---- a/drivers/phy/spacemit/Kconfig -+++ b/drivers/phy/spacemit/Kconfig -@@ -11,3 +11,19 @@ config PHY_SPACEMIT_K1_USB2 - help - Enable this to support K1 USB 2.0 PHY driver. This driver takes care of - enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. -+ -+config PHY_SPACEMIT_K3_COMMON_OPS -+ tristate -+ select MFD_SYSCON -+ select GENERIC_PHY -+ -+config PHY_SPACEMIT_K3_COMBO_PHY -+ tristate "SpacemiT K3 USB3/PCIe PHY support" -+ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF -+ depends on COMMON_CLK -+ select PHY_SPACEMIT_K3_COMMON_OPS -+ help -+ Enable this to support K3 USB3/PCIe combo PHY driver. This -+ driver takes care of enabling and clock setup and will be used -+ by K3 dwc3 driver. -+ If unsure, say N. -diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile -index fec0b425a948..df9b609d066f 100644 ---- a/drivers/phy/spacemit/Makefile -+++ b/drivers/phy/spacemit/Makefile -@@ -1,2 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0-only - obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o -+obj-$(CONFIG_PHY_SPACEMIT_K3_COMBO_PHY) += phy-k3-combo.o -+obj-$(CONFIG_PHY_SPACEMIT_K3_COMMON_OPS) += phy-k3-common.o -diff --git a/drivers/phy/spacemit/phy-k3-combo.c b/drivers/phy/spacemit/phy-k3-combo.c -new file mode 100644 -index 000000000000..abd0aad18893 ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-combo.c -@@ -0,0 +1,252 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * phy-k3-usb3.c - SpacemiT K3 Type-C Orientation Switch Driver -+ * -+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "phy-k3-common.h" -+ -+/* -+ * The PCIE/USB Subsystem on SpacemiT K3 have 3 single lane PIPE3 PHYs -+ * (PHY2/3/4) shared by PCIE PortC/D and USB3 PortB/C/D. -+ * -+ * PMUA_PCIE_SUBSYS_MGMT[4:0] -+ * -+ * bit4 = 0 : PCIe A X8 mode, all 8 lanes dedicated to PCIe Port A -+ * 1 : PHY lanes shared between PCIe or USB according to [3:0] -+ * -+ * All PHY matrix combinations according to [4:0]: -+ * -+ * 0x0X : PCIe-A X8 -+ * 0x10 : PCIe-C x2 (PHY2+PHY3) + PCIe-D x1 (PHY4) -+ * 0x11 : PCIe-C x2 (PHY2+PHY3) + USB-D (PHY4) -+ * 0x12 : PCIe-C x1 (PHY2) + USB-C (PHY3) -+ * 0x13 : PCIe-C x1 (PHY2) + USB-C (PHY3) + USB-D (PHY4) -+ * 0x14 : PCIe-C x1 (PHY3) + USB-B (PHY2) -+ * 0x15 : PCIe-C x1 (PHY3) + USB-B (PHY2) + USB-D (PHY4) -+ * 0x16 : USB-B (PHY2) + USB-C (PHY3) + PCIe D x1 (PHY4) -+ * 0x17 : USB-B (PHY2) + USB-C (PHY3) + USB-D (PHY4) -+ * -+ * So any USB Port B/C/D operation requires PCIe A X8 mode to be disabled. -+ */ -+#define PMUA_PCIE_SUBSYS_MGMT 0x1d8 -+#define PU_MATRIX_CONF_MASK GENMASK(4, 0) -+ -+#define COMBPHY_MAX_SUBPHYS 6 -+ -+struct k3_combo_phy { -+ struct device *dev; -+ struct k3_lane_group groups[COMBPHY_MAX_SUBPHYS]; -+ void __iomem *base; -+ struct regmap *apb_spare; -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group0 = { -+ .lanes = 2, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x0, 0x400 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group1 = { -+ .lanes = 2, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x100000, 0x100400 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group2 = { -+ .lanes = 1, -+ .config = 0x14, -+ .mask = 0x14, -+ .offsets = { -+ 0x200000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group3 = { -+ .lanes = 1, -+ .config = 0x12, -+ .mask = 0x12, -+ .offsets = { -+ 0x300000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group4 = { -+ .lanes = 1, -+ .config = 0x11, -+ .mask = 0x11, -+ .offsets = { -+ 0x400000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data k3_combphy_lane_group5 = { -+ .lanes = 1, -+ .config = 0xff, -+ .mask = 0x00, -+ .offsets = { -+ 0x500000 -+ }, -+}; -+ -+static const struct k3_phy_lane_group_data *k3_combphy_lane_datas[] = { -+ &k3_combphy_lane_group0, -+ &k3_combphy_lane_group1, -+ &k3_combphy_lane_group2, -+ &k3_combphy_lane_group3, -+ &k3_combphy_lane_group4, -+ &k3_combphy_lane_group5, -+}; -+ -+static int k3_combo_phy_init_lanes(struct k3_combo_phy *phy, unsigned int config) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(k3_combphy_lane_datas); i++) { -+ const struct k3_phy_lane_group_data *data = k3_combphy_lane_datas[i]; -+ struct k3_lane_group *lg = &phy->groups[i]; -+ const struct phy_ops *ops; -+ bool is_usb; -+ -+ is_usb = (data->mask & config) == data->config; -+ if (is_usb) -+ ops = &k3_usb3_phy_ops; -+ else -+ ops = &k3_pcie_phy_ops; -+ -+ dev_dbg(phy->dev, "phy %d is %s\n", i, is_usb ? "usb" : "pcie"); -+ -+ lg->phy = devm_phy_create(phy->dev, NULL, ops); -+ if (IS_ERR(lg->phy)) -+ return PTR_ERR(lg->phy); -+ -+ lg->is_pcie = !is_usb; -+ lg->data = data; -+ lg->base = phy->base; -+ phy_set_drvdata(lg->phy, lg); -+ } -+ -+ return 0; -+} -+ -+static int k3_combo_phy_update_config(struct regmap *apmu, unsigned int config) -+{ -+ if (config & ~PU_MATRIX_CONF_MASK) -+ return -EINVAL; -+ -+ return regmap_update_bits(apmu, PMUA_PCIE_SUBSYS_MGMT, PU_MATRIX_CONF_MASK, config); -+} -+ -+static struct phy *k3_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) -+{ -+ struct k3_combo_phy *phy = dev_get_drvdata(dev); -+ struct k3_lane_group *lg; -+ -+ if (args->args_count != 2) { -+ dev_err(dev, "Invalid number of arguments\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ if (args->args[0] >= ARRAY_SIZE(k3_combphy_lane_datas)) { -+ dev_err(dev, "Invalid PHY id\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ lg = &phy->groups[args->args[0]]; -+ -+ if ((lg->is_pcie && args->args[1] != PHY_TYPE_PCIE) || -+ (!lg->is_pcie && args->args[1] != PHY_TYPE_USB3)) { -+ dev_err(dev, "Invalid PHY mode\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ return lg->phy; -+} -+ -+static int k3_combo_phy_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct device_node *node = dev->of_node; -+ struct phy_provider *provider; -+ struct k3_combo_phy *phy; -+ struct regmap *apmu; -+ u32 config = 0; -+ int ret; -+ -+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); -+ if (!phy) -+ return -ENOMEM; -+ -+ phy->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(phy->base)) -+ return PTR_ERR(phy->base); -+ -+ phy->apb_spare = syscon_regmap_lookup_by_phandle(node, "spacemit,apb-spare"); -+ if (IS_ERR(phy->apb_spare)) -+ return dev_err_probe(dev, PTR_ERR(phy->apb_spare), -+ "Failed to fine APB SPARE syscon"); -+ -+ apmu = syscon_regmap_lookup_by_phandle_args(node, "spacemit,apmu", 1, &config); -+ if (IS_ERR(apmu)) -+ return dev_err_probe(dev, PTR_ERR(apmu), -+ "Failed to find APMU syscon"); -+ -+ ret = k3_combo_phy_update_config(apmu, config); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to set lane configuration"); -+ -+ phy->dev = dev; -+ platform_set_drvdata(pdev, phy); -+ -+ ret = k3_phy_calibrate(phy->apb_spare); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to calibrate phy"); -+ -+ ret = k3_combo_phy_init_lanes(phy, config); -+ if (ret < 0) -+ return dev_err_probe(dev, ret, "Failed to init lanes"); -+ -+ provider = devm_of_phy_provider_register(dev, k3_combo_phy_xlate); -+ if (IS_ERR(provider)) -+ return dev_err_probe(dev, PTR_ERR(provider), -+ "Failed to register provider\n"); -+ -+ return 0; -+} -+ -+static const struct of_device_id k3_combo_phy_of_match[] = { -+ { .compatible = "spacemit,k3-combo-phy" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, k3_combo_phy_of_match); -+ -+static struct platform_driver k3_combo_phy_driver = { -+ .probe = k3_combo_phy_probe, -+ .driver = { -+ .name = "spacemit,k3-combo-phy", -+ .of_match_table = k3_combo_phy_of_match, -+ }, -+}; -+module_platform_driver(k3_combo_phy_driver); -+ -+MODULE_DESCRIPTION("SpacemiT K3 USB3/PCIe combo PHY driver"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/phy/spacemit/phy-k3-common.c b/drivers/phy/spacemit/phy-k3-common.c -new file mode 100644 -index 000000000000..840524cbe533 ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-common.c -@@ -0,0 +1,372 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "phy-k3-common.h" -+ -+/* PHY Registers */ -+#define PHY_VERSION 0x0 -+ -+#define PHY_RESET_CFG 0x04 -+ -+#define PHY_RESET_RXBUF_RST BIT(0) -+#define PHY_RESET_SOFT_RST_PCS BIT(1) -+#define PHY_RESET_SOFT_RST_AHB BIT(2) -+#define PHY_RESET_EN_SD_AFTER_LOCK BIT(6) -+ -+#define PHY_CLK_CFG 0x08 -+ -+#define PHY_CLK_PLL_READY BIT(0) -+#define PHY_CLK_TXCLK_INV BIT(2) -+#define PHY_CLK_RXCLK_EN BIT(3) -+#define PHY_CLK_TXCLK_EN BIT(4) -+#define PHY_CLK_PCLK_EN BIT(5) -+#define PHY_CLK_PIPE_PCLK_EN BIT(6) -+#define PHY_CLK_REFCLK_FREQ GENMASK(10, 7) -+#define PHY_CLK_REFCLK_24M 2 -+#define PHY_CLK_SW_INIT_DONE BIT(11) -+#define PHY_CLK_PU_SSC_OUT BIT(23) -+ -+#define PHY_MODE_CFG 0x0C -+ -+#define PHY_MODE_PCIE_INT_EN BIT(0) -+#define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8) -+#define PHY_MODE_LFPS_TPERIOD_USB 3 -+ -+#define PHY_PU_SEL 0x40 -+ -+#define PHY_PU_CFG_STATUS BIT(9) -+#define PHY_PU_OVRD_STATUS BIT(10) -+ -+#define PHY_PU_CK_REG 0x54 -+ -+#define PHY_PU_REFCLK_100 BIT(25) -+ -+#define PHY_PLL_REG1 0x58 -+ -+#define PHY_PLL_FREF_SEL GENMASK(15, 13) -+#define PHY_PLL_FREF_24M 0x1 -+#define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24) -+#define PHY_PLL_SSC_5000PPM 0xa -+#define PHY_PLL_SSC_MODE GENMASK(29, 28) -+#define PHY_PLL_SSC_MODE_CENTER_SPREAD 0 -+#define PHY_PLL_SSC_MODE_UP_SPREAD 1 -+#define PHY_PLL_SSC_MODE_DOWN_SPREAD 2 -+#define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3 -+ -+#define PHY_PLL_REG2 0x5c -+ -+#define PHY_PLL_SEL_REF100 BIT(21) -+ -+/* PHY RX Register Definitions */ -+#define PHY_RX_REG_A 0x60 -+ -+#define PHY_RX_REG0_RLOAD BIT(4) -+#define PHY_RX_REG1_RTERM GENMASK(11, 8) -+#define PHY_RX_REG1_RC_CALI GENMASK(15, 12) -+#define PHY_RX_REG2_CSEL GENMASK(19, 16) -+#define PHY_RX_REG2_FORCE_CSEL BIT(20) -+#define PHY_RX_REG2_PSEL GENMASK(23, 21) -+#define PHY_RX_REG3_I_LOAD GENMASK(26, 24) -+#define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27) -+#define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28) -+#define PHY_RX_REG3_RDEG1 GENMASK(31, 30) -+ -+#define PHY_RX_REG_B 0x64 -+ -+#define PHY_RX_REGB_MASK GENMASK(23, 0) -+ -+#define PHY_RX_REG4_RDEG2 GENMASK(2, 1) -+#define PHY_RX_REG4_ENVOS BIT(4) -+#define PHY_RX_REG4_RTERM_SEL BIT(5) -+#define PHY_RX_REG4_MANUAL_CFG BIT(7) -+#define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8) -+#define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12) -+#define PHY_RX_REG6_H1_REG GENMASK(19, 16) -+#define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20) -+#define PHY_RX_REG6_BYPASS_ADPT BIT(22) -+ -+#define PHY_ADPT_CFG0 0x140 -+#define PHY_ADPT_AFE_RST_OVRD_EN BIT(1) -+#define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4) -+ -+#define PHY_RXEQ_TIME 0xb4 -+#define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21) -+#define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22) -+#define PHY_RXEQ_TIME_AMP_SOC_650M 0 -+#define PHY_RXEQ_TIME_AMP_SOC_800M 1 -+#define PHY_RXEQ_TIME_AMP_SOC_870M 2 -+#define PHY_RXEQ_TIME_AMP_SOC_900M 3 -+#define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24) -+ -+#define PCIE_PU_ADDR_CLK_CFG 0x0008 -+#define PHY_CLK_PLL_READY BIT(0) -+#define PCIE_INITAL_TIMER GENMASK(6, 3) -+#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) -+#define CFG_SW_PHY_INIT_DONE BIT(11) -+ -+/* Lane RX/TX configuration (per‑lane, at lane_base) */ -+#define PCIE_RX_REG1 0x050 -+#define PCIE_TX_REG1 0x064 -+ -+#define PCIE_PLL_TIMEOUT 500000 -+#define PCIE_POLL_DELAY 500 -+ -+static int k3_usb3phy_init_single(struct k3_lane_group *lg, void __iomem *base) -+{ -+ struct phy *phy = lg->phy; -+ u32 val, tmp; -+ int ret; -+ -+ /* Do not wait CDR lock before sampling data */ -+ val = readl(base + PHY_RESET_CFG); -+ val = u32_replace_bits(val, 0, PHY_RESET_EN_SD_AFTER_LOCK); -+ writel(val, base + PHY_RESET_CFG); -+ -+ /* Power down 100MHz refclk buffer */ -+ val = readl(base + PHY_PU_CK_REG); -+ val = u32_replace_bits(val, 0, PHY_PU_REFCLK_100); -+ writel(val, base + PHY_PU_CK_REG); -+ -+ /* Program PLL REG1 configure the SSC */ -+ val = FIELD_PREP(PHY_PLL_SSC_MODE, PHY_PLL_SSC_MODE_DOWN_SPREAD1) | -+ FIELD_PREP(PHY_PLL_SSC_DEP_SEL, PHY_PLL_SSC_5000PPM) | -+ FIELD_PREP(PHY_PLL_FREF_SEL, PHY_PLL_FREF_24M); -+ writel(val, base + PHY_PLL_REG1); -+ -+ /* Un-select 100MHz PLL reference */ -+ val = readl(base + PHY_PLL_REG2); -+ val = u32_replace_bits(val, 0, PHY_PLL_SEL_REF100); -+ writel(val, base + PHY_PLL_REG2); -+ -+ /* USB LFPS period configuration */ -+ val = readl(base + PHY_MODE_CFG); -+ val = u32_replace_bits(val, PHY_MODE_LFPS_TPERIOD_USB, PHY_MODE_LFPS_TPERIOD); -+ writel(val, base + PHY_MODE_CFG); -+ -+ /* Force AFE adaptation reset */ -+ val = readl(base + PHY_ADPT_CFG0); -+ val |= PHY_ADPT_AFE_RST_OVRD_EN | PHY_ADPT_AFE_RST_OVRD_VAL; -+ writel(val, base + PHY_ADPT_CFG0); -+ -+ /* Override driver amplitude value to 900m */ -+ val = readl(base + PHY_RXEQ_TIME); -+ val |= PHY_RXEQ_TIME_OVRD_AMP_SOC; -+ val = u32_replace_bits(val, PHY_RXEQ_TIME_AMP_SOC_900M, PHY_RXEQ_TIME_CFG_AMP_SOC); -+ writel(val, base + PHY_RXEQ_TIME); -+ -+ /* Configure RX parameters */ -+ val = PHY_RX_REG0_RLOAD | -+ FIELD_PREP(PHY_RX_REG1_RTERM, 0x8) | -+ FIELD_PREP(PHY_RX_REG1_RC_CALI, 0x7) | -+ FIELD_PREP(PHY_RX_REG2_CSEL, 0x8) | -+ PHY_RX_REG2_FORCE_CSEL | -+ FIELD_PREP(PHY_RX_REG2_PSEL, 0x4) | -+ FIELD_PREP(PHY_RX_REG3_I_LOAD, 0x7) | -+ PHY_RX_REG3_SEL_CBOOST_CODE | -+ FIELD_PREP(PHY_RX_REG3_ADJ_BIAS, 0x1) | -+ FIELD_PREP(PHY_RX_REG3_RDEG1, 0x3); -+ writel(val, base + PHY_RX_REG_A); -+ -+ val = readl(base + PHY_RX_REG_B); -+ tmp = FIELD_PREP(PHY_RX_REG4_RDEG2, 0x2) | -+ PHY_RX_REG4_ENVOS | PHY_RX_REG4_RTERM_SEL | PHY_RX_REG4_MANUAL_CFG | -+ FIELD_PREP(PHY_RX_REG5_RCELL_VCM, 0x8) | -+ FIELD_PREP(PHY_RX_REG5_RCELL_BIAS, 0x8) | -+ FIELD_PREP(PHY_RX_REG6_H1_REG, 0x8) | -+ FIELD_PREP(PHY_RX_REG6_ADAPT_GAIN, 0x2); -+ val = u32_replace_bits(val, tmp, PHY_RX_REGB_MASK); -+ writel(val, base + PHY_RX_REG_B); -+ -+ /* -+ * Inform PHY that all PLL-related configuration is done. -+ * PLL will not start locking until PHY_CLK_SW_INIT_DONE is set. -+ */ -+ val = PHY_CLK_SW_INIT_DONE | PHY_CLK_PU_SSC_OUT | -+ FIELD_PREP(PHY_CLK_REFCLK_FREQ, PHY_CLK_REFCLK_24M) | -+ PHY_CLK_RXCLK_EN | PHY_CLK_TXCLK_EN | -+ PHY_CLK_PCLK_EN | PHY_CLK_PIPE_PCLK_EN; -+ writel(val, base + PHY_CLK_CFG); -+ -+ ret = readl_poll_timeout(base + PHY_CLK_CFG, val, -+ (val & PHY_CLK_PLL_READY), -+ PCIE_POLL_DELAY, PCIE_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(&phy->dev, "PHY PLL polling timeout\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int k3_usb3phy_init(struct phy *phy) -+{ -+ struct k3_lane_group *lg = phy_get_drvdata(phy); -+ int ret, i; -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ ret = k3_usb3phy_init_single(lg, lg->base + lg->data->offsets[i]); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+const struct phy_ops k3_usb3_phy_ops = { -+ .init = k3_usb3phy_init, -+ .owner = THIS_MODULE, -+}; -+EXPORT_SYMBOL_GPL(k3_usb3_phy_ops); -+ -+static int k3_pcie_phy_init(struct phy *phy) -+{ -+ struct k3_lane_group *lg = phy_get_drvdata(phy); -+ void __iomem *phy_base = lg->base + lg->data->offsets[0]; -+ u32 val; -+ int ret; -+ int i; -+ -+ val = readl(phy_base + PHY_PLL_REG1); -+ val = u32_replace_bits(val, 0x2, GENMASK(15, 12)); -+ writel(val, phy_base + PHY_PLL_REG1); -+ -+ val = readl(phy_base + PHY_PLL_REG2); -+ val = u32_replace_bits(val, 0, BIT(21)); -+ writel(val, phy_base + PHY_PLL_REG2); -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ void __iomem *lane_base = lg->base + lg->data->offsets[i]; -+ -+ val = readl(lane_base + PCIE_RX_REG1); -+ val = u32_replace_bits(val, 0, 0x3); -+ writel(val, lane_base + PCIE_RX_REG1); -+ } -+ -+ val = readl(phy_base + PHY_PLL_REG2); -+ val |= BIT(20); -+ writel(val, phy_base + PHY_PLL_REG2); -+ -+ writel(0x00006505, phy_base + PCIE_RX_REG1); -+ -+ /* pll_reg1 of lane0, disable SSC: pll[27:24] = 0 */ -+ val = readl(phy_base + PHY_PLL_REG1); -+ val = u32_replace_bits(val, 0, GENMASK(27, 24)); -+ writel(val, phy_base + PHY_PLL_REG1); -+ -+ for (i = 0; i < lg->data->lanes; i++) { -+ void __iomem *lane_base = lg->base + lg->data->offsets[i]; -+ -+ /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */ -+ val = readl(lane_base + PHY_PU_SEL); -+ val = u32_replace_bits(val, 1, BIT(13)); -+ writel(val, lane_base + PHY_PU_SEL); -+ -+ /* disable en_sample_data_after_cdr_locked */ -+ val = readl(lane_base + PHY_RESET_CFG); -+ val = u32_replace_bits(val, 0, BIT(6)); -+ writel(val, lane_base + PHY_RESET_CFG); -+ -+ /* Dynamic Lock */ -+ val = readl(lane_base + PHY_MODE_CFG); -+ val = u32_replace_bits(val, 1, BIT(2)); -+ writel(val, lane_base + PHY_MODE_CFG); -+ -+ val = FIELD_PREP(GENMASK(7, 0), 0x10) | -+ FIELD_PREP(GENMASK(15, 8), 0x78) | -+ FIELD_PREP(GENMASK(23, 16), 0x98) | -+ FIELD_PREP(GENMASK(31, 24), 0xdf); -+ writel(val, lane_base + PHY_RX_REG_A); -+ -+ val = readl(lane_base + PHY_RX_REG_B); -+ val &= ~PHY_RX_REGB_MASK; -+ val |= FIELD_PREP(GENMASK(7, 0), 0xb4) | -+ FIELD_PREP(GENMASK(15, 8), 0x88) | -+ FIELD_PREP(GENMASK(23, 16), 0x28); -+ writel(val, lane_base + PHY_RX_REG_B); -+ -+ /* Set init done */ -+ val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG); -+ val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE); -+ writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG); -+ } -+ -+ ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val, -+ (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY, -+ PCIE_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(&lg->phy->dev, "PHY PLL lock timeout\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+const struct phy_ops k3_pcie_phy_ops = { -+ .init = k3_pcie_phy_init, -+ .owner = THIS_MODULE, -+}; -+EXPORT_SYMBOL_GPL(k3_pcie_phy_ops); -+ -+/* PHY rcal init requires APB_SPARE regmap access */ -+ -+#define APB_SPARE_PU_CAL 0x178 -+#define PU_CAL BIT(17) -+ -+#define APB_SPARE_RCAL_HSIO 0x17c -+#define APB_SPARE_PU_CAL_DONE BIT(8) -+#define RCAL_OVRD_PTRIM GENMASK(23, 20) -+#define RCAL_OVRD_NTRIM GENMASK(27, 24) -+#define RCAL_OVRD_PTRIM_EN BIT(28) -+#define RCAL_OVRD_NTRIM_EN BIT(29) -+#define RCAL_OVRD_STABLE_VAL BIT(30) -+#define RCAL_OVRD_STABLE_EN BIT(31) -+ -+#define RCAL_OVRD_TRIM_EN (RCAL_OVRD_NTRIM_EN | RCAL_OVRD_PTRIM_EN) -+#define RCAL_OVRD_TRIM_MASK (RCAL_OVRD_NTRIM | RCAL_OVRD_PTRIM) -+ -+#define PU_CAL_TIMEOUT 2000000 -+ -+static DEFINE_MUTEX(calibrate_lock); -+ -+int k3_phy_calibrate(struct regmap *apb_spare) -+{ -+ unsigned int val = 0; -+ int ret; -+ -+ guard(mutex)(&calibrate_lock); -+ -+ regmap_read(apb_spare, APB_SPARE_RCAL_HSIO, &val); -+ if (val & APB_SPARE_PU_CAL_DONE) -+ return 0; -+ -+ regmap_update_bits(apb_spare, APB_SPARE_PU_CAL, PU_CAL, -+ PU_CAL); -+ -+ ret = regmap_read_poll_timeout(apb_spare, APB_SPARE_RCAL_HSIO, -+ val, (val & APB_SPARE_PU_CAL_DONE), PCIE_POLL_DELAY, -+ PU_CAL_TIMEOUT); -+ -+ if (ret) -+ regmap_update_bits(apb_spare, APB_SPARE_RCAL_HSIO, -+ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | -+ RCAL_OVRD_TRIM_MASK | RCAL_OVRD_STABLE_EN, -+ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | -+ FIELD_PREP(RCAL_OVRD_NTRIM, 0x6) | -+ FIELD_PREP(RCAL_OVRD_PTRIM, 0xa) | -+ RCAL_OVRD_STABLE_EN); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(k3_phy_calibrate); -+ -+MODULE_DESCRIPTION("SpacemiT K3 PHY common ops"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/phy/spacemit/phy-k3-common.h b/drivers/phy/spacemit/phy-k3-common.h -new file mode 100644 -index 000000000000..49009c3c313a ---- /dev/null -+++ b/drivers/phy/spacemit/phy-k3-common.h -@@ -0,0 +1,27 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef _PHY_K3_COMMON_H -+#define _PHY_K3_COMMON_H -+ -+#include -+ -+struct k3_phy_lane_group_data { -+ u32 lanes; -+ u8 config; -+ u8 mask; -+ u32 offsets[] __counted_by(lanes); -+}; -+ -+struct k3_lane_group { -+ const struct k3_phy_lane_group_data *data; -+ void __iomem *base; -+ struct phy *phy; -+ bool is_pcie; -+}; -+ -+extern const struct phy_ops k3_pcie_phy_ops; -+extern const struct phy_ops k3_usb3_phy_ops; -+ -+int k3_phy_calibrate(struct regmap *apb_spare); -+ -+#endif --- -2.53.0 - diff --git a/SPECS/linux/0263-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch b/SPECS/linux/0263-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch new file mode 100644 index 0000000000..326220eece --- /dev/null +++ b/SPECS/linux/0263-ULTRARISC-hwmon-add-corepvt-driver-of-UltraRISC-DP10.patch @@ -0,0 +1,450 @@ +From 785b6a1f0ecf7ea9458ee7f3a925e9aa4acc077c Mon Sep 17 00:00:00 2001 +From: Jia Wang +Date: Thu, 13 Feb 2025 15:50:12 +0800 +Subject: [RUYI PATCH] ULTRARISC: hwmon: add corepvt driver of UltraRISC DP1000 + +From: https://github.com/ultrarisc/linux-6.8.0/commit/2cb818e1179844847d3be752b978a4ee7e633bc3 + +UltraRISC Corepvt driver supports cluster voltage +and core temperature detection + +Signed-off-by: Jia Wang +Signed-off-by: Han Gao +--- + drivers/hwmon/Kconfig | 9 + + drivers/hwmon/Makefile | 1 + + drivers/hwmon/corepvt-ultrarisc.c | 390 ++++++++++++++++++++++++++++++ + 3 files changed, 400 insertions(+) + create mode 100644 drivers/hwmon/corepvt-ultrarisc.c + +diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig +index 328867242cb3..6c3e733b2efe 100644 +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -503,6 +503,15 @@ config SENSORS_CHIPCAP2 + To compile this driver as a module, choose M here: the module + will be called chipcap2. + ++config SENSORS_COREPVT_ULTRARISC ++ tristate "UltraRISC Core Voltage, Temperature sensor driver" ++ help ++ If you say yes here you get support for UltraRISC Core PVT sensor ++ embedded into the SoC. ++ ++ This driver can also be built as a module. If so, the module will be ++ called corepvt-ultrarisc. ++ + config SENSORS_CORSAIR_CPRO + tristate "Corsair Commander Pro controller" + depends on HID +diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile +index 5833c807c688..247cf3d0cda2 100644 +--- a/drivers/hwmon/Makefile ++++ b/drivers/hwmon/Makefile +@@ -61,6 +61,7 @@ obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o + obj-$(CONFIG_SENSORS_BT1_PVT) += bt1-pvt.o + obj-$(CONFIG_SENSORS_CGBC) += cgbc-hwmon.o + obj-$(CONFIG_SENSORS_CHIPCAP2) += chipcap2.o ++obj-$(CONFIG_SENSORS_COREPVT_ULTRARISC) += corepvt-ultrarisc.o + obj-$(CONFIG_SENSORS_CORETEMP) += coretemp.o + obj-$(CONFIG_SENSORS_CORSAIR_CPRO) += corsair-cpro.o + obj-$(CONFIG_SENSORS_CORSAIR_PSU) += corsair-psu.o +diff --git a/drivers/hwmon/corepvt-ultrarisc.c b/drivers/hwmon/corepvt-ultrarisc.c +new file mode 100644 +index 000000000000..3674eedefbda +--- /dev/null ++++ b/drivers/hwmon/corepvt-ultrarisc.c +@@ -0,0 +1,390 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* Driver for UltraRISC Core PVT ++ * ++ * Copyright(C) 2025 UltraRISC Technology (Shanghai) Co., Ltd. ++ * ++ * Author: wangjia ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define COREPVT_CHL_OFFSET 0x1000 ++#define COREPVT_REG_CIR 0x0 ++#define COREPVT_REG_PSCR 0x04 ++#define COREPVT_REG_CFDR 0x08 ++#define COREPVT_REG_DOR 0x0C ++#define COREPVT_REG_ICR 0x10 ++#define COREPVT_REG_IER 0x14 ++#define COREPVT_REG_IMSR 0x18 ++#define COREPVT_REG_IRSR 0x1C ++ ++#define PVT_MAX_CHANNEL 64 ++#define PVT_TRIM_DEFAULT 0x7 ++ ++struct corepvt_channel_config { ++ const char *label; ++ u32 trim; ++}; ++ ++struct corepvt_cal_data { ++ u32 val_offset; ++ u32 val_lsb; ++}; ++ ++struct corepvt_data { ++ const struct hwmon_chip_info *chip_info; ++ u64 temp_chl_mask; ++ u64 vol_chl_mask; ++}; ++ ++struct corepvt_hwmon { ++ struct device *dev; ++ struct device *hwmon; ++ ++ void __iomem *regs; ++ int irq; ++ int clk_freq; ++ int channels; ++ const struct hwmon_chip_info *chip_info; ++ struct corepvt_channel_config config[PVT_MAX_CHANNEL]; ++ const struct corepvt_data *pvt_data; ++ raw_spinlock_t lock; ++}; ++ ++#define COREPVT_VOLTAGE_DATA_BASE 2065100 /* 2065.1 */ ++#define COREPVT_VOLTAGE_LSB 1682 /* 1.682 mV */ ++#define COREPVT_TEMP_DATA_BASE 27049000 /* 2704.9 */ ++#define COREPVT_TEMP_LSB 22632 /* 2.2632 Celsius */ ++ ++static int corepvt_read_vol(struct corepvt_hwmon *pvt, ++ int channel, long *val) ++{ ++ void __iomem *chl_base; ++ unsigned long flag; ++ u32 dout; ++ u32 chl_offset = 0; ++ ++ // Assume that the voltage channel is continuous ++ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); ++ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); ++ ++ raw_spin_lock_irqsave(&pvt->lock, flag); ++ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); ++ raw_spin_unlock_irqrestore(&pvt->lock, flag); ++ ++ *val = ((long)dout * 1000 - COREPVT_VOLTAGE_DATA_BASE) / COREPVT_VOLTAGE_LSB; ++ ++ return 0; ++} ++ ++static int corepvt_read_temp(struct corepvt_hwmon *pvt, ++ int channel, long *val) ++{ ++ void __iomem *chl_base; ++ unsigned long flag; ++ u32 dout; ++ u32 chl_offset = 0; ++ ++ // Assume that the temperature channel is continuous ++ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); ++ chl_base = pvt->regs + COREPVT_CHL_OFFSET * (channel + chl_offset); ++ ++ raw_spin_lock_irqsave(&pvt->lock, flag); ++ dout = readl_relaxed(chl_base + COREPVT_REG_DOR); ++ raw_spin_unlock_irqrestore(&pvt->lock, flag); ++ ++ *val = ((long)dout * 10000 - COREPVT_TEMP_DATA_BASE) * 1000 / COREPVT_TEMP_LSB; ++ ++ return 0; ++} ++ ++static umode_t corepvt_is_visible(const void *drvdata, enum hwmon_sensor_types type, ++ u32 attr, int channel) ++{ ++ const struct corepvt_hwmon *pvt = drvdata; ++ ++ if (channel >= pvt->channels) ++ return 0; ++ ++ switch (type) { ++ case hwmon_in: ++ switch (attr) { ++ case hwmon_in_input: ++ case hwmon_in_label: ++ return 0444; ++ } ++ break; ++ case hwmon_temp: ++ switch (attr) { ++ case hwmon_temp_input: ++ case hwmon_temp_type: ++ case hwmon_temp_label: ++ return 0444; ++ } ++ break; ++ default: ++ return 0; ++ } ++ ++ return 0; ++} ++ ++static int corepvt_read(struct device *dev, enum hwmon_sensor_types type, ++ u32 attr, int channel, long *val) ++{ ++ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); ++ ++ switch (type) { ++ case hwmon_in: ++ switch (attr) { ++ case hwmon_in_input: ++ return corepvt_read_vol(pvt, channel, val); ++ } ++ break; ++ case hwmon_temp: ++ switch (attr) { ++ case hwmon_temp_type: ++ *val = 1; ++ return 0; ++ case hwmon_temp_input: ++ return corepvt_read_temp(pvt, channel, val); ++ } ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return -ENODATA; ++} ++ ++static int corepvt_read_string(struct device *dev, enum hwmon_sensor_types type, ++ u32 attr, int channel, const char **str) ++{ ++ struct corepvt_hwmon *pvt = dev_get_drvdata(dev); ++ u32 chl_offset = 0; ++ ++ switch (type) { ++ case hwmon_in: ++ chl_offset = __ffs64(pvt->pvt_data->vol_chl_mask); ++ break; ++ case hwmon_temp: ++ chl_offset = __ffs64(pvt->pvt_data->temp_chl_mask); ++ break; ++ default: ++ return -ENODATA; ++ break; ++ } ++ ++ *str = pvt->config[channel + chl_offset].label; ++ ++ return 0; ++} ++ ++/* ++ * corepvt init process: ++ * 1. config SETUP time, should be 10us, set PSCR register ++ * 2. config CLKIN, should be 4MHz, set CFDR register ++ * 3. (TODO)config interrupt, set ICR/IER/IMSR/IRSR ++ * 4. config TRIM and enable PVT, set CIR ++ */ ++static int corepvt_init(struct corepvt_hwmon *pvt) ++{ ++ void __iomem *chl_base; ++ unsigned long flag; ++ /* ++ * SETUP time 10us = 100KHz ++ * PSCR = CLK_FREQ / 100KHz ++ */ ++ u32 pscr_val = pvt->clk_freq / 100000; ++ /* ++ * CFDR = CLK_FREQ / 4MHz / 2 ++ */ ++ u32 cfdr_val = pvt->clk_freq / 8000000; ++ /* ++ * CIR: ++ * bit[0]: PU_VTDC, set 1 to enable pvt ++ * bit[5:2]: TRIM ++ */ ++ u32 cir_val; ++ ++ raw_spin_lock_irqsave(&pvt->lock, flag); ++ for (int i = 0; i < pvt->channels; i++) { ++ chl_base = pvt->regs + COREPVT_CHL_OFFSET * i; ++ cir_val = (pvt->config[i].trim << 2) | 0x01; ++ writel_relaxed(pscr_val, chl_base + COREPVT_REG_PSCR); ++ writel_relaxed(cfdr_val, chl_base + COREPVT_REG_CFDR); ++ writel_relaxed(cir_val, chl_base + COREPVT_REG_CIR); ++ } ++ raw_spin_unlock_irqrestore(&pvt->lock, flag); ++ ++ return 0; ++} ++ ++static const struct hwmon_ops corepvt_hwmon_ops = { ++ .is_visible = corepvt_is_visible, ++ .read = corepvt_read, ++ .read_string = corepvt_read_string, ++}; ++ ++static int corepvt_probe_channel_from_dt(struct platform_device *pdev, struct corepvt_hwmon *pvt) ++{ ++ struct device_node *child; ++ int ret; ++ u32 channel; ++ const char *label; ++ u32 trim; ++ ++ for_each_child_of_node(pdev->dev.of_node, child) { ++ if (!of_node_name_eq(child, "channel")) ++ continue; ++ ++ ret = of_property_read_u32(child, "reg", &channel); ++ if (ret) ++ goto node_put; ++ ++ ret = of_property_read_string(child, "label", &label); ++ if (ret) ++ goto node_put; ++ ++ if (of_property_present(child, "trim")) ++ of_property_read_u32(child, "trim", &trim); ++ else ++ trim = PVT_TRIM_DEFAULT; ++ ++ pvt->config[channel].label = label; ++ pvt->config[channel].trim = trim; ++ } ++ ++ return 0; ++ ++node_put: ++ of_node_put(child); ++ return ret; ++} ++ ++static int corepvt_probe(struct platform_device *pdev) ++{ ++ struct corepvt_hwmon *pvt; ++ const struct corepvt_data *pvt_data; ++ int ret; ++ ++ pvt = devm_kzalloc(&pdev->dev, sizeof(*pvt), GFP_KERNEL); ++ if (!pvt) ++ return -ENOMEM; ++ ++ pvt->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(pvt->regs)) { ++ dev_err(&pdev->dev, "get ioremap resource failed\n"); ++ ret = -EINVAL; ++ goto free_pvt; ++ } ++ ++ if (device_property_present(&pdev->dev, "interrupts")) ++ pvt->irq = platform_get_irq(pdev, 0); ++ ++ ret = device_property_read_u32(&pdev->dev, "clock-frequency", &pvt->clk_freq); ++ if (ret) { ++ dev_err(&pdev->dev, "get clock-frequency failed\n"); ++ goto free_pvt; ++ } ++ ++ ret = device_property_read_u32(&pdev->dev, "channels", &pvt->channels); ++ if (ret) { ++ dev_err(&pdev->dev, "get channels failed\n"); ++ goto free_pvt; ++ } ++ ++ pvt_data = device_get_match_data(&pdev->dev); ++ if (!pvt_data) { ++ dev_err(&pdev->dev, "No chip info found\n"); ++ ret = -ENODATA; ++ goto free_pvt; ++ } ++ ++ pvt->dev = &pdev->dev; ++ pvt->chip_info = pvt_data->chip_info; ++ pvt->pvt_data = pvt_data; ++ ++ if (pdev->dev.of_node) { ++ ret = corepvt_probe_channel_from_dt(pdev, pvt); ++ if (ret) ++ dev_warn(&pdev->dev, "WARN: probe channel failed\n"); ++ } ++ ++ pvt->hwmon = devm_hwmon_device_register_with_info(&pdev->dev, "corepvt_ultrarisc", ++ pvt, pvt->chip_info, ++ NULL); ++ if (IS_ERR(pvt->hwmon)) { ++ dev_err(&pdev->dev, "register hwmon failed(%ld)\n", PTR_ERR(pvt->hwmon)); ++ ret = -EINVAL; ++ goto free_pvt; ++ } ++ ++ pvt->dev = &pdev->dev; ++ raw_spin_lock_init(&pvt->lock); ++ ++ // Config and enable corepvt ++ corepvt_init(pvt); ++ ++ return 0; ++ ++free_pvt: ++ devm_kfree(&pdev->dev, pvt); ++ return ret; ++} ++ ++static const struct hwmon_channel_info * const ur_dp1000_channel_info[] = { ++ HWMON_CHANNEL_INFO(temp, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL, ++ HWMON_T_INPUT | HWMON_T_LABEL), ++ HWMON_CHANNEL_INFO(in, ++ HWMON_I_INPUT | HWMON_I_LABEL, ++ HWMON_I_INPUT | HWMON_I_LABEL), ++ NULL ++}; ++ ++static const struct hwmon_chip_info ur_dp1000_chip_info = { ++ .ops = &corepvt_hwmon_ops, ++ .info = ur_dp1000_channel_info, ++}; ++ ++static struct corepvt_data ur_dp1000_pvt_data = { ++ .chip_info = &ur_dp1000_chip_info, ++ .temp_chl_mask = GENMASK_ULL(10, 0), ++ .vol_chl_mask = GENMASK_ULL(12, 11) ++}; ++ ++static const struct of_device_id corepvt_of_match[] = { ++ { .compatible = "ultrarisc,dp1000-pvt", .data = &ur_dp1000_pvt_data }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, corepvt_of_match); ++ ++static struct platform_driver corepvt_driver = { ++ .probe = corepvt_probe, ++ .driver = { ++ .name = "corepvt-ultrarisc", ++ .of_match_table = corepvt_of_match ++ } ++}; ++module_platform_driver(corepvt_driver); ++ ++MODULE_AUTHOR("Jia Wang "); ++MODULE_DESCRIPTION("corepvt-ultrarisc driver"); ++MODULE_LICENSE("GPL"); +-- +2.53.0 + diff --git a/SPECS/linux/0264-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch b/SPECS/linux/0264-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch new file mode 100644 index 0000000000..fbab1d1fa7 --- /dev/null +++ b/SPECS/linux/0264-RUYI-SYNC-riscv-dts-dp1000-Update-dp1000.dtsi.patch @@ -0,0 +1,732 @@ +From 49021cde94070b74978ef72a293539acb7e457a6 Mon Sep 17 00:00:00 2001 +From: Han Gao +Date: Sun, 12 Apr 2026 02:50:03 +0800 +Subject: [RUYI PATCH] RUYI: SYNC: riscv: dts: dp1000: Update dp1000.dtsi + +FROM: https://github.com/ultrarisc/linux-6.8.0/commit/b4a00f2f96a9c7d8d550259292fd19568fe9beec + +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/ultrarisc/dp1000.dtsi | 521 ++++++++++++++++++++-- + 1 file changed, 489 insertions(+), 32 deletions(-) + +diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +index 78e0cda1fcb9..7b7016618dcd 100644 +--- a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi ++++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi +@@ -22,121 +22,491 @@ cpu0: cpu@0 { + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache0>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu0_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache0: l2-cache0 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; + }; ++ + cpu1: cpu@1 { + device_type = "cpu"; + reg = <0x1>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache1>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu1_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache1: l2-cache1 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; + }; ++ + cpu2: cpu@2 { + device_type = "cpu"; + reg = <0x2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache2>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu2_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache2: l2-cache2 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; + }; ++ + cpu3: cpu@3 { + device_type = "cpu"; + reg = <0x3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache3>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu3_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache3: l2-cache3 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster0_l3>; ++ }; + }; ++ + cpu4: cpu@4 { + device_type = "cpu"; + reg = <0x10>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache4>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu4_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache4: l2-cache4 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; + }; ++ + cpu5: cpu@5 { + device_type = "cpu"; + reg = <0x11>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache5>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu5_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache5: l2-cache5 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; + }; ++ + cpu6: cpu@6 { + device_type = "cpu"; + reg = <0x12>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; +- + clock-frequency = <2000000000>; +- ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache6>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu6_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache6: l2-cache6 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; + }; ++ + cpu7: cpu@7 { + device_type = "cpu"; + reg = <0x13>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcbh"; ++ riscv,isa-base = "rv64i"; ++ riscv,isa-extensions = "i","m","a","f","d","c","h","zba", ++ "zbb","zbc","zbs","zicntr","zicsr", ++ "zifencei","zihpm","ziccif","ziccrse", ++ "ziccamoa","za64rs","zic64b","zicbom", ++ "zicbop","zicboz","zkt","zama16b", ++ "svade","ssccptr","sstvecd","sscounterenw", ++ "shcounterenw","shtvala","shvstvecd", ++ "shvsatpa","ssstrict","svvptc"; + mmu-type = "riscv,sv48"; + clock-frequency = <2000000000>; ++ /* L1 I-cache and D-cache: ++ * block-size 64B ++ * 4-way set associative, size 64KB ++ * per-core. ++ */ ++ d-cache-block-size = <64>; ++ d-cache-sets = <256>; ++ d-cache-size = <0x10000>; ++ i-cache-block-size = <64>; ++ i-cache-sets = <256>; ++ i-cache-size = <0x10000>; ++ next-level-cache = <&l2_cache7>; ++ riscv,cbom-block-size = <64>; ++ riscv,cbop-block-size = <64>; ++ riscv,cboz-block-size = <64>; + cpu7_intc:interrupt-controller { + #address-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + #interrupt-cells = <0x01>; + }; ++ l2_cache7: l2-cache7 { ++ /* L2 cache: ++ * cache-unified, block-size 64B ++ * 8-way set associative, size 512KB ++ * per-core. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-size = <0x80000>; ++ cache-sets = <1024>; ++ cache-unified; ++ next-level-cache = <&cluster1_l3>; ++ }; ++ }; ++ ++ cpu-map { ++ cluster0: cluster0 { ++ core0 { ++ cpu = <&cpu0>; ++ }; ++ core1 { ++ cpu = <&cpu1>; ++ }; ++ core2 { ++ cpu = <&cpu2>; ++ }; ++ core3 { ++ cpu = <&cpu3>; ++ }; ++ ++ cluster0_l3: l3-cache0 { ++ /* L3 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 4MB ++ * per-cluster. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <3>; ++ cache-size = <0x400000>; ++ cache-sets = <0x1000>; ++ cache-unified; ++ next-level-cache = <&l4_cache>; ++ }; ++ }; ++ ++ cluster1: cluster1 { ++ core0 { ++ cpu = <&cpu4>; ++ }; ++ core1 { ++ cpu = <&cpu5>; ++ }; ++ core2 { ++ cpu = <&cpu6>; ++ }; ++ core3 { ++ cpu = <&cpu7>; ++ }; ++ cluster1_l3: l3-cache1 { ++ /* L3 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 4MB ++ * per-cluster. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <3>; ++ cache-size = <0x400000>; ++ cache-sets = <0x1000>; ++ cache-unified; ++ next-level-cache = <&l4_cache>; ++ }; ++ }; + }; + }; + +@@ -150,6 +520,20 @@ soc { + #size-cells = <0x02>; + compatible = "simple-bus"; + ranges; ++ ++ l4_cache: l4-cache { ++ /* L4 cache: ++ * cache-unified, block-size 64B ++ * 16-way set associative, size 16MB ++ * shared by the SoC. ++ */ ++ compatible = "cache"; ++ cache-block-size = <64>; ++ cache-level = <4>; ++ cache-size = <0x1000000>; ++ cache-sets = <0x4000>; ++ cache-unified; ++ }; + + clocks { + compatible = "simple-bus"; +@@ -160,6 +544,12 @@ device_clk: device_clk { + #clock-cells = <0>; + }; + ++ timer_clk: timer_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <50000000>; ++ #clock-cells = <0>; ++ }; ++ + csr_clk: csr_clk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; +@@ -170,35 +560,102 @@ csr_clk: csr_clk { + clint: clint@8000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, +- <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, +- <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, +- <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, +- <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, +- <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, +- <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, +- <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; ++ <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, ++ <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, ++ <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, ++ <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, ++ <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, ++ <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, ++ <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; + reg = <0x00 0x8000000 0x00 0x100000>; + }; +- ++ + plic: plic@9000000 { + #interrupt-cells = <1>; + #address-cells = <0>; +- phandle = <0x01>; +- compatible = "ultrarisc,dp1000-plic"; ++ compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; + interrupt-controller; + interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, +- <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, +- <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, +- <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, +- <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, +- <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, +- <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, +- <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; ++ <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, ++ <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, ++ <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, ++ <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, ++ <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, ++ <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, ++ <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; + reg = <0x00 0x9000000 0x00 0x4000000>; + riscv,max-priority = <0x07>; + riscv,ndev = <160>; + }; +- ++ ++ core_pvt: pvt@110D0000 { ++ compatible = "ultrarisc,dp1000-pvt"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x00 0x110D0000 0x00 0x0000D000>; ++ clock-frequency = <250000000>; ++ channels = <13>; ++ ++ #thermal-sensor-cells = <1>; ++ channel@0 { ++ label = "Core temp0"; ++ reg = <0>; ++ }; ++ ++ channel@1 { ++ label = "Core temp1"; ++ reg = <1>; ++ }; ++ ++ channel@2 { ++ label = "Core temp2"; ++ reg = <2>; ++ }; ++ ++ channel@3 { ++ label = "Core temp3"; ++ reg = <3>; ++ }; ++ ++ channel@4 { ++ label = "Core temp4"; ++ reg = <4>; ++ }; ++ ++ channel@5 { ++ label = "Core temp5"; ++ reg = <5>; ++ }; ++ channel@6 { ++ label = "Core temp6"; ++ reg = <6>; ++ }; ++ channel@7 { ++ label = "Core temp7"; ++ reg = <7>; ++ }; ++ channel@8 { ++ label = "Core temp8"; ++ reg = <8>; ++ }; ++ channel@9 { ++ label = "Core temp9"; ++ reg = <9>; ++ }; ++ channel@10 { ++ label = "Core temp10"; ++ reg = <10>; ++ }; ++ channel@11 { ++ label = "Cluster0 voltage"; ++ reg = <11>; ++ }; ++ channel@12 { ++ label = "Cluster1 voltage"; ++ reg = <12>; ++ }; ++ }; ++ + uart0: serial@20300000 { + interrupt-parent = <0x01>; + interrupts = <17>; +@@ -244,7 +701,7 @@ uart3: serial@20410000 { + }; + + spi0: spi@20320000 { +- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; ++ compatible = "snps,dw-apb-ssi"; + status = "okay"; + #address-cells = <0x01>; + #size-cells = <0x00>; +@@ -258,7 +715,7 @@ spi0: spi@20320000 { + }; + + spi1: spi@20420000 { +- compatible = "baikal,bt1-ssi","snps,dw-apb-ssi"; ++ compatible = "snps,dw-apb-ssi"; + status = "okay"; + #address-cells = <0x01>; + #size-cells = <0x00>; +@@ -449,11 +906,11 @@ pcie_x16: pcie@21000000 { + num-lanes = <16>; + ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, /* io */ + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, /* mem32 */ +- <0xc3000000 0x40 0x00000000 0x40 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ +- max-link-speed = <4>; ++ <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ ++ max-link-speed = <16>; + interrupt-parent = <&plic>; +- interrupts = <43>, <44>, <45>, <46>, <47>, <48>; +- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupts = <43>, <44>, <45>, <46>, <47>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, +@@ -475,11 +932,11 @@ pcie_x4a: pcie@23000000 { + num-lanes = <4>; + ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, /* io */ + <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, /* mem32 */ +- <0xc3000000 0x80 0x00000000 0x80 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ + max-link-speed = <4>; + interrupt-parent = <&plic>; +- interrupts = <63>, <64>, <65>, <66>, <67>, <68>; +- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupts = <63>, <64>, <65>, <66>, <67>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, + <0x0 0x0 0x0 0x2 &plic 65>, +@@ -501,11 +958,11 @@ pcie_x4b: pcie@24000000 { + num-lanes = <4>; + ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, /* io */ + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, /* mem32 */ +- <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0x5 0x00000000>; /* mem64 prefetchable */ ++ <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; /* mem64 prefetchable */ + max-link-speed = <4>; + interrupt-parent = <&plic>; +- interrupts = <73>, <74>, <75>, <76>, <77>, <78>; +- interrupt-names = "msi", "inta", "intb", "intc", "intd", "aer"; ++ interrupts = <73>, <74>, <75>, <76>, <77>; ++ interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, + <0x0 0x0 0x0 0x2 &plic 75>, +-- +2.53.0 + diff --git a/SPECS/linux/0264-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch b/SPECS/linux/0264-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch deleted file mode 100644 index 56ca65076c..0000000000 --- a/SPECS/linux/0264-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch +++ /dev/null @@ -1,106 +0,0 @@ -From d998d7cb254181cde5fe683f3e6113406f5f7579 Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Fri, 27 Feb 2026 09:46:06 +0800 -Subject: [PATCH 264/269] RUYI: riscv: dts: spacemit: k3: add USB controller - and USB phy support - -Add all USB device node to the Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++ - 2 files changed, 55 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index ac965ec83f2c..acfbb5029c15 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -183,6 +183,11 @@ dldo7: dldo7 { - }; - }; - -+&combophy { -+ spacemit,apmu = <&syscon_apmu 0x11>; -+ status = "okay"; -+}; -+ - ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; -@@ -280,3 +285,11 @@ hub@1 { - &usb2_phy { - status = "okay"; - }; -+ -+&usb3d_u2phy { -+ status = "okay"; -+}; -+ -+&usb3d { -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 66dcabd0a815..130828ca3b43 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -7,6 +7,7 @@ - #include - #include - #include -+#include - - /dts-v1/; - -@@ -637,6 +638,47 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ usb3d: usb@81a00000 { -+ compatible = "spacemit,k3-dwc3"; -+ reg = <0x0 0x81a00000 0x0 0x10000>; -+ interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-parent = <&saplic>; -+ clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; -+ clock-names = "usbdrd30"; -+ resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, -+ <&syscon_apmu RESET_APMU_USB3_D_VCC>, -+ <&syscon_apmu RESET_APMU_USB3_D_PHY>; -+ reset-names = "ahb", "vcc", "phy"; -+ phys = <&usb3d_u2phy>, -+ <&combophy 4 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi"; -+ snps,dis_enblslpm_quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ snps,parkmode-disable-ss-quirk; -+ dr_mode = "host"; -+ status = "disabled"; -+ }; -+ -+ usb3d_u2phy: phy@81b00000 { -+ compatible = "spacemit,k3-usb2-phy"; -+ reg = <0x0 0x81b00000 0x0 0x200>; -+ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ combophy: phy@81d00000 { -+ compatible = "spacemit,k3-combo-phy"; -+ reg = <0x0 0x81d00000 0x0 0x600000>; -+ #phy-cells = <2>; -+ spacemit,apb-spare = <&pll>; -+ status = "disabled"; -+ }; -+ - usb2_host: usb@c0a00000 { - compatible = "spacemit,k3-dwc3"; - reg = <0x0 0xc0a00000 0x0 0x10000>; --- -2.53.0 - diff --git a/SPECS/linux/0265-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch b/SPECS/linux/0265-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch deleted file mode 100644 index 347f063d0b..0000000000 --- a/SPECS/linux/0265-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch +++ /dev/null @@ -1,261 +0,0 @@ -From 9eb2340edb2989412a100a45539eb6703136e84e Mon Sep 17 00:00:00 2001 -From: Inochi Amaoto -Date: Tue, 24 Mar 2026 11:06:24 +0800 -Subject: [PATCH 265/269] RUYI: riscv: dts: spacemit: k3: Add PCIe device node - -Add all PCIe device node for Spacemit K3. - -Signed-off-by: Inochi Amaoto -Signed-off-by: Han Gao ---- - arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++ - arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 ++++ - arch/riscv/boot/dts/spacemit/k3.dtsi | 150 +++++++++++++++++++ - 3 files changed, 212 insertions(+) - -diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -index acfbb5029c15..f24ada15f182 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts -@@ -264,6 +264,35 @@ uboot@210000 { - }; - }; - -+&pcie0_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie0_0_cfg>; -+ phys = <&combophy 0 PHY_TYPE_PCIE>, -+ <&combophy 1 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0", "pcie-phy1"; -+ num-lanes = <4>; -+ status = "okay"; -+}; -+ -+&pcie2_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_cfg>; -+ phys = <&combophy 2 PHY_TYPE_PCIE>, -+ <&combophy 3 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0", "pcie-phy1"; -+ num-lanes = <2>; -+ status = "okay"; -+}; -+ -+&pcie4_rc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie4_0_cfg>; -+ phys = <&combophy 5 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0"; -+ num-lanes = <1>; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_0_cfg>; -diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -index 846d5e8cc783..5a817610101b 100644 ---- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi -@@ -710,4 +710,37 @@ uart0-0-pins { - drive-strength = <25>; - }; - }; -+ -+ pcie0_0_cfg: pcie0-0-cfg { -+ pcie0-0-pins { -+ pinmux = , /* pcie0 perst */ -+ ; /* pcie0 clkreq */ -+ -+ bias-pull-up = <1>; -+ drive-strength = <33>; -+ power-source = <1800>; -+ }; -+ }; -+ -+ pcie2_0_cfg: pcie2-0-cfg { -+ pcie2-0-pins { -+ pinmux = , /* pcie2 perst */ -+ ; /* pcie2 clkreq */ -+ -+ drive-strength = <38>; -+ power-source = <3300>; -+ }; -+ }; -+ -+ pcie4_0_cfg: pcie4-0-cfg { -+ pcie4-0-pins { -+ pinmux = , /* pcie4 perst */ -+ , /* pcie4 wake */ -+ ; /* pcie4 clkreq */ -+ -+ bias-pull-up = <1>; -+ drive-strength = <33>; -+ power-source = <1800>; -+ }; -+ }; - }; -diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi -index 130828ca3b43..6adfbd505e9e 100644 ---- a/arch/riscv/boot/dts/spacemit/k3.dtsi -+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi -@@ -638,6 +638,156 @@ pdma: dma-controller@d4000000 { - status = "disabled"; - }; - -+ pcie0_rc: pcie@80000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80000000 0x0 0x00001000>, -+ <0x0 0x80100000 0x0 0x00001000>, -+ <0x0 0x80300000 0x0 0x00003f20>, -+ <0x11 0x00000000 0x0 0x00010000>, -+ <0x0 0x82900000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTA_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTA_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTA_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_A_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_A_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_A_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ linux,pci-domain = <0>; -+ spacemit,apmu = <&syscon_apmu 0x1f0>; -+ status = "disabled"; -+ }; -+ -+ pcie1_rc: pcie@80400000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80400000 0x0 0x00001000>, -+ <0x0 0x80500000 0x0 0x00001000>, -+ <0x0 0x80700000 0x0 0x00003f20>, -+ <0x11 0x80000000 0x0 0x00010000>, -+ <0x0 0x82c00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTB_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTB_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTB_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00010000 0x11 0x80010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x80110000 0x11 0x80110000 0x0 0x7fef0000>, -+ <0x43000000 0x16 0x00000000 0x16 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_B_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_B_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_B_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ linux,pci-domain = <1>; -+ spacemit,apmu = <&syscon_apmu 0x1d0>; -+ status = "disabled"; -+ }; -+ -+ pcie2_rc: pcie@80800000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80800000 0x0 0x00001000>, -+ <0x0 0x80900000 0x0 0x00001000>, -+ <0x0 0x80b00000 0x0 0x00003f20>, -+ <0x12 0x00000000 0x0 0x00010000>, -+ <0x0 0x82d00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTC_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTC_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTC_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x00 0x00000000 0x12 0x00010000 0x0 0x00100000>, -+ <0x02000000 0x0 0x00110000 0x12 0x00110000 0x0 0x7fef0000>, -+ <0x43000000 0x15 0x00000000 0x15 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_C_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_C_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_C_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <2>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1c8>; -+ status = "disabled"; -+ }; -+ -+ pcie3_rc: pcie@80c00000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x80c00000 0x0 0x00001000>, -+ <0x0 0x80d00000 0x0 0x00001000>, -+ <0x0 0x80f00000 0x0 0x00003f20>, -+ <0x12 0x80000000 0x0 0x00010000>, -+ <0x0 0x82a00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTD_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTD_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTD_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00010000 0x12 0x80010000 0x0 0x100000>, -+ <0x02000000 0x0 0x80110000 0x12 0x80110000 0x0 0x3fef0000>, -+ <0x43000000 0x14 0x00000000 0x14 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_D_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_D_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_D_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <3>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1e0>; -+ status = "disabled"; -+ }; -+ -+ pcie4_rc: pcie@81000000 { -+ compatible = "spacemit,k3-pcie"; -+ reg = <0x0 0x81000000 0x0 0x00001000>, -+ <0x0 0x81100000 0x0 0x00001000>, -+ <0x0 0x81300000 0x0 0x00003f20>, -+ <0x12 0xc0000000 0x0 0x00010000>, -+ <0x0 0x82b00000 0x0 0x00001000>; -+ reg-names = "dbi", "dbi2", "atu", "config", "link"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTE_DBI>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTE_MSTE>, -+ <&syscon_apmu CLK_APMU_PCIE_PORTE_SLV>; -+ clock-names = "dbi", "mstr", "slv"; -+ msi-parent = <&simsic>; -+ ranges = <0x01000000 0x0 0x00000000 0x12 0xc0010000 0x0 0x100000>, -+ <0x02000000 0x0 0xc0110000 0x12 0xc0110000 0x0 0x3fef0000>, -+ <0x43000000 0x13 0x00000000 0x13 0x00000000 0x1 0x00000000>; -+ resets = <&syscon_apmu RESET_APMU_PCIE_E_DBI>, -+ <&syscon_apmu RESET_APMU_PCIE_E_MASTER>, -+ <&syscon_apmu RESET_APMU_PCIE_E_SLAVE>; -+ reset-names = "dbi", "mstr", "slv"; -+ linux,pci-domain = <4>; -+ bus-range = <0x00 0xff>; -+ max-link-speed = <3>; -+ spacemit,apmu = <&syscon_apmu 0x1e8>; -+ status = "disabled"; -+ }; -+ - usb3d: usb@81a00000 { - compatible = "spacemit,k3-dwc3"; - reg = <0x0 0x81a00000 0x0 0x10000>; --- -2.53.0 - diff --git a/SPECS/linux/0265-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch b/SPECS/linux/0265-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch new file mode 100644 index 0000000000..d67b73e2a0 --- /dev/null +++ b/SPECS/linux/0265-RUYI-riscv-dts-spacemit-k3-Add-USB2.0-support.patch @@ -0,0 +1,102 @@ +From c168a79b974c2ba19245ad2e7f3e1eb295acbb30 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Sat, 24 Jan 2026 08:48:53 +0800 +Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: Add USB2.0 support + +FROM: https://github.com/spacemit-com/linux/commit/6f1578894e4484f8a6724aceff099d2e90450e10 + +The USB2.0 controller on Pico-ITX board connnect to a Terminus FE1.1 Hub +which fully USB2.0 protocol compliant and provides 4 ports. + +Signed-off-by: Yixun Lan +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 25 ++++++++++++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 31 ++++++++++++++++++++ + 2 files changed, 56 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index 61cbf924830b..ac965ec83f2c 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -33,6 +33,15 @@ reg_aux_vcc5v: regulator-aux-vcc5v { + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; ++ ++ aux_vcc3v3: regulator-aux-vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "AUX_VCC3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ + }; + + &i2c8 { +@@ -255,3 +264,19 @@ &uart0 { + pinctrl-0 = <&uart0_0_cfg>; + status = "okay"; + }; ++ ++&usb2_host { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hub@1 { ++ compatible = "usb1a40,0101"; ++ reg = <1>; ++ vdd-supply = <&aux_vcc3v3>; ++ }; ++}; ++ ++&usb2_phy { ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index ed046714a7ac..1b86c872accb 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -637,6 +637,37 @@ pdma: dma-controller@d4000000 { + status = "disabled"; + }; + ++ usb2_host: usb@c0a00000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0xc0a00000 0x0 0x10000>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB2_AHB>, ++ <&syscon_apmu RESET_APMU_USB2_VCC>, ++ <&syscon_apmu RESET_APMU_USB2_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ phys = <&usb2_phy>; ++ phy-names = "usb2-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ dr_mode = "host"; ++ maximum-speed = "high-speed"; ++ status = "disabled"; ++ }; ++ ++ usb2_phy: phy@c0a20000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0xc0a20000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; +-- +2.53.0 + diff --git a/SPECS/linux/0266-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch b/SPECS/linux/0266-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch deleted file mode 100644 index cf6ec503da..0000000000 --- a/SPECS/linux/0266-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch +++ /dev/null @@ -1,34 +0,0 @@ -From c71d38f5e32477d75fc9e9587705ed05cddb3870 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 20 May 2026 23:28:15 +0800 -Subject: [PATCH 266/269] RUYI: PCI: add SpacemiT vendor id and its K3 device - id to pci_ids - -The SpacemiT K3 chip's root complex needs to be listed in the allowlist -of rtw89 driver to allow 36-bit DMA. - -Add the vendor and device IDs to pci_ids.h header file. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - include/linux/pci_ids.h | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h -index 9663be526dd0..6386d4c72103 100644 ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -2640,6 +2640,9 @@ - #define PCI_VENDOR_ID_SUNIX 0x1fd4 - #define PCI_DEVICE_ID_SUNIX_1999 0x1999 - -+#define PCI_VENDOR_ID_SPACEMIT 0x201f -+#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 -+ - #define PCI_VENDOR_ID_HINT 0x3388 - #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 - --- -2.53.0 - diff --git a/SPECS/linux/0266-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch b/SPECS/linux/0266-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch new file mode 100644 index 0000000000..d0818475fc --- /dev/null +++ b/SPECS/linux/0266-SPACEMIT-riscv-uaccess-don-t-use-vector-if-buffer-is.patch @@ -0,0 +1,145 @@ +From 2b84e88568d846ebe8d792c687e2b68a191854f3 Mon Sep 17 00:00:00 2001 +From: Zhang Meng +Date: Mon, 5 Jan 2026 20:05:04 +0800 +Subject: [RUYI PATCH] SPACEMIT: riscv: uaccess: don't use vector if buffer is + not cacheable + +FROM: https://github.com/spacemit-com/linux-6.18/commit/9168f7e0c6bfdcfa3b6a64a4d45e3cd68a81618f + +Change-Id: I040d597ee246777767f7be747fa9202154524538 +[ Vivian: Rebase and move check into enter_vector_usercopy ] +Signed-off-by: Vivian Wang +Signed-off-by: Han Gao +--- + arch/riscv/include/asm/uaccess.h | 5 +++ + arch/riscv/lib/Makefile | 1 + + arch/riscv/lib/riscv_v_helpers.c | 5 +++ + arch/riscv/lib/uaccess_cache_check.c | 65 ++++++++++++++++++++++++++++ + 4 files changed, 76 insertions(+) + create mode 100644 arch/riscv/lib/uaccess_cache_check.c + +diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h +index 11c9886c3b70..69bdc070f420 100644 +--- a/arch/riscv/include/asm/uaccess.h ++++ b/arch/riscv/include/asm/uaccess.h +@@ -487,6 +487,11 @@ static inline void user_access_restore(unsigned long enabled) { } + if (__asm_copy_from_user_sum_enabled(_dst, _src, _len)) \ + goto label; + ++/* Memory cacheability check for vector uaccess optimization */ ++#ifdef CONFIG_RISCV_ISA_V ++int is_cacheable_safe(const void *addr); ++#endif ++ + #else /* CONFIG_MMU */ + #include + #endif /* CONFIG_MMU */ +diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile +index 735d0b665536..43fe69db9803 100644 +--- a/arch/riscv/lib/Makefile ++++ b/arch/riscv/lib/Makefile +@@ -14,6 +14,7 @@ endif + lib-y += csum.o + ifeq ($(CONFIG_MMU), y) + lib-$(CONFIG_RISCV_ISA_V) += uaccess_vector.o ++lib-$(CONFIG_RISCV_ISA_V) += uaccess_cache_check.o + endif + lib-$(CONFIG_MMU) += uaccess.o + lib-$(CONFIG_64BIT) += tishift.o +diff --git a/arch/riscv/lib/riscv_v_helpers.c b/arch/riscv/lib/riscv_v_helpers.c +index 7bbdfc6d4552..7ab2cea280f8 100644 +--- a/arch/riscv/lib/riscv_v_helpers.c ++++ b/arch/riscv/lib/riscv_v_helpers.c +@@ -8,6 +8,7 @@ + + #include + #include ++#include + + #ifdef CONFIG_MMU + #include +@@ -28,6 +29,10 @@ asmlinkage int enter_vector_usercopy(void *dst, void *src, size_t n, + if (!may_use_simd()) + goto fallback; + ++ /* HACK */ ++ if (!is_cacheable_safe(dst) || !is_cacheable_safe(src)) ++ goto fallback; ++ + kernel_vector_begin(); + remain = enable_sum ? __asm_vector_usercopy(dst, src, n) : + __asm_vector_usercopy_sum_enabled(dst, src, n); +diff --git a/arch/riscv/lib/uaccess_cache_check.c b/arch/riscv/lib/uaccess_cache_check.c +new file mode 100644 +index 000000000000..0b0996fa2d37 +--- /dev/null ++++ b/arch/riscv/lib/uaccess_cache_check.c +@@ -0,0 +1,65 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Memory cacheability check for RISC-V uaccess optimization ++ * ++ * This file provides a C function that can be called from assembly ++ * to determine if a buffer is cacheable before using vector instructions. ++ */ ++ ++#include ++#include ++#include ++ ++/** ++ * is_cacheable_safe - Check if memory buffer is cacheable ++ * @addr: Virtual address to check (kernel or user space) ++ * ++ * Returns: 1 if cacheable, 0 if non-cacheable ++ * ++ * This function is designed to be called from assembly code in uaccess.S ++ * to determine if vector instructions are safe to use for memory copy. ++ * ++ * Non-cacheable memory (device IO, DMA coherent buffers) should not use ++ * vector instructions as they may cause cache coherency issues. ++ * ++ * Handles both kernel and user space addresses safely: ++ * - Kernel direct mapping: Always cacheable ++ * - Kernel vmalloc: Check VM flags ++ * - User space: Check page table (most are cacheable) ++ * - ioremap/DMA: Non-cacheable ++ */ ++int is_cacheable_safe(const void *addr) ++{ ++ unsigned long vaddr = (unsigned long)addr; ++ ++ /* Kernel direct mapped memory - always cacheable */ ++ if (virt_addr_valid(addr)) ++ return 1; ++ ++ if (vaddr < TASK_SIZE) { ++ /* ++ * User space address, Determine it as a cacheable buffer, ++ * maybe not safe!! ++ */ ++ return 1; ++ } ++ ++ /* Check if it's a vmalloc region (kernel virtual address) */ ++ if (is_vmalloc_addr(addr)) { ++ struct vm_struct *vm; ++ ++ vm = find_vm_area(addr); ++ if (!vm) ++ return 0; ++ ++ /* Exclude ioremap and DMA coherent buffers */ ++ if (vm->flags & (VM_IOREMAP | VM_DMA_COHERENT)) ++ return 0; ++ ++ /* Normal vmalloc - cacheable */ ++ return 1; ++ } ++ ++ /* Unknown kernel region - assume non-cacheable for safety */ ++ return 0; ++} +-- +2.53.0 + diff --git a/SPECS/linux/0267-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch b/SPECS/linux/0267-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch new file mode 100644 index 0000000000..ec32257c0d --- /dev/null +++ b/SPECS/linux/0267-RUYI-dt-bindings-phy-Add-Spacemit-K3-USB3-PCIe-comb-.patch @@ -0,0 +1,90 @@ +From 66dbf2efb657accb96df8e31216a29f7f41858fa Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 13 Feb 2026 09:01:58 +0800 +Subject: [RUYI PATCH] RUYI: dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb + phy support + +The USB3/PCIe comb PHY on the K3 is a complex PHY group that +can provide multiple phy for both PCIe and USB controller. +Its mux configuration is controlled by the APMU syscon device. + +Signed-off-by: Inochi Amaoto +Signed-off-by: Han Gao +--- + .../bindings/phy/spacemit,k3-combo-phy.yaml | 64 +++++++++++++++++++ + 1 file changed, 64 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml +new file mode 100644 +index 000000000000..eafc753b7e9b +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml +@@ -0,0 +1,64 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Spacemit K3 PCIE/USB3 Comb PHY ++ ++maintainers: ++ - Inochi Amaoto ++ ++properties: ++ compatible: ++ const: spacemit,k3-combo-phy ++ ++ reg: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 2 ++ description: ++ The first one is phy id, the second one is phy type. ++ ++ spacemit,apb-spare: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: ++ Phandle to APB SPARE system controller interface, used for ++ PHY calibration. ++ ++ spacemit,apmu: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle of APMU syscon ++ - description: configuration of the PHY lanes ++ description: | ++ Phandle to control PHY mux configuration. The configuration ++ is described as follows: ++ bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode ++ bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode ++ bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode ++ bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode ++ bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode ++ ++ The bit[3:0] is only valid when bit 4 is 1. ++ ++required: ++ - compatible ++ - reg ++ - "#phy-cells" ++ - spacemit,apb-spare ++ - spacemit,apmu ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@81d00000 { ++ compatible = "spacemit,k3-combo-phy"; ++ reg = <0x81d00000 0x600000>; ++ #phy-cells = <2>; ++ spacemit,apb-spare = <&apb_spare>; ++ spacemit,apmu = <&apmu 0x00>; ++ }; +-- +2.53.0 + diff --git a/SPECS/linux/0267-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch b/SPECS/linux/0267-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch deleted file mode 100644 index 2c73a41d2b..0000000000 --- a/SPECS/linux/0267-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 3264cd3ea80e2a05603fd2471ef8437198fedf7d Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Wed, 20 May 2026 23:29:46 +0800 -Subject: [PATCH 267/269] RUYI: wifi: rtw89: pci: add SpacemiT K3 to 36-bit DMA - allowlist - -The SpacemiT K3 platform has no system memory in the 32-bit address -space, and it's verified that the chip works well with 36-bit DMA of -RTL8852BE. - -Add it to the 36-bit DMA allowlist of rtw89_pci. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - drivers/net/wireless/realtek/rtw89/pci.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c -index 43c61b3dc969..6470d09f17f3 100644 ---- a/drivers/net/wireless/realtek/rtw89/pci.c -+++ b/drivers/net/wireless/realtek/rtw89/pci.c -@@ -3312,6 +3312,10 @@ static bool rtw89_pci_is_dac_compatible_bridge(struct rtw89_dev *rtwdev) - if (bridge->device == 0x2806) - return true; - break; -+ case PCI_VENDOR_ID_SPACEMIT: -+ if (bridge->device == PCI_DEVICE_ID_SPACEMIT_K3) -+ return true; -+ break; - } - - return false; --- -2.53.0 - diff --git a/SPECS/linux/0268-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch b/SPECS/linux/0268-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch deleted file mode 100644 index 3eb5b96030..0000000000 --- a/SPECS/linux/0268-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 6fe9b7fa04a1b9bd9f5a7f13e32508f336728115 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Tue, 19 May 2026 19:57:52 +0800 -Subject: [PATCH 268/269] RUYI: drm/amdgpu: disable dynamic PCIe speed switch - on SpacemiT K3 - -The dynamic speed switch functionality seems to be broken on SpacemiT -K3, and leads to frequent GPU crashes at least with Polaris GPUs. - -Disable dynamic speed switch on this platform. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Han Gao ---- - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -index 2ec69fa05cb1..97664c30ae7b 100644 ---- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c -@@ -2004,6 +2004,14 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev) - */ - static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev) - { -+ struct pci_dev *parent = adev->pdev; -+ static const struct pci_device_id broken_devids[] = { -+ /* SpacemiT K3 */ -+ { PCI_DEVICE(PCI_VENDOR_ID_SPACEMIT, -+ PCI_DEVICE_ID_SPACEMIT_K3) }, -+ {} -+ }; -+ - #if IS_ENABLED(CONFIG_X86) - struct cpuinfo_x86 *c = &cpu_data(0); - -@@ -2014,6 +2022,17 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device - if (c->x86_vendor == X86_VENDOR_INTEL) - return false; - #endif -+ /* skip upstream/downstream switches internal to dGPU */ -+ while (parent->vendor == PCI_VENDOR_ID_ATI) { -+ parent = pci_upstream_bridge(parent); -+ } -+ -+ if (!parent) -+ return true; -+ -+ if (pci_match_id(broken_devids, parent)) -+ return false; -+ - return true; - } - --- -2.53.0 - diff --git a/SPECS/linux/0268-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch b/SPECS/linux/0268-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch new file mode 100644 index 0000000000..49d9337863 --- /dev/null +++ b/SPECS/linux/0268-RUYI-phy-spacemit-Add-USB3-PCIe-comb-PHY-driver-for-.patch @@ -0,0 +1,730 @@ +From 30d345a45af38c2816b2150fc4261b4d500b5a55 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 13 Feb 2026 09:09:58 +0800 +Subject: [RUYI PATCH] RUYI: phy: spacemit: Add USB3/PCIe comb PHY driver for + Spacemit K3 + +The comb PHY on K3 requires to configure a syscon device for the +right mux configuration. And it requires calibration before any +usage. + +Add USB3/PCIe comb PHY driver for Spacemit K3. + +Signed-off-by: Inochi Amaoto +Signed-off-by: Han Gao +--- + drivers/phy/spacemit/Kconfig | 16 ++ + drivers/phy/spacemit/Makefile | 2 + + drivers/phy/spacemit/phy-k3-combo.c | 252 ++++++++++++++++++ + drivers/phy/spacemit/phy-k3-common.c | 372 +++++++++++++++++++++++++++ + drivers/phy/spacemit/phy-k3-common.h | 27 ++ + 5 files changed, 669 insertions(+) + create mode 100644 drivers/phy/spacemit/phy-k3-combo.c + create mode 100644 drivers/phy/spacemit/phy-k3-common.c + create mode 100644 drivers/phy/spacemit/phy-k3-common.h + +diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig +index 0136aee2e8a2..9a1e25592f25 100644 +--- a/drivers/phy/spacemit/Kconfig ++++ b/drivers/phy/spacemit/Kconfig +@@ -11,3 +11,19 @@ config PHY_SPACEMIT_K1_USB2 + help + Enable this to support K1 USB 2.0 PHY driver. This driver takes care of + enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver. ++ ++config PHY_SPACEMIT_K3_COMMON_OPS ++ tristate ++ select MFD_SYSCON ++ select GENERIC_PHY ++ ++config PHY_SPACEMIT_K3_COMBO_PHY ++ tristate "SpacemiT K3 USB3/PCIe PHY support" ++ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF ++ depends on COMMON_CLK ++ select PHY_SPACEMIT_K3_COMMON_OPS ++ help ++ Enable this to support K3 USB3/PCIe combo PHY driver. This ++ driver takes care of enabling and clock setup and will be used ++ by K3 dwc3 driver. ++ If unsure, say N. +diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile +index fec0b425a948..df9b609d066f 100644 +--- a/drivers/phy/spacemit/Makefile ++++ b/drivers/phy/spacemit/Makefile +@@ -1,2 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o ++obj-$(CONFIG_PHY_SPACEMIT_K3_COMBO_PHY) += phy-k3-combo.o ++obj-$(CONFIG_PHY_SPACEMIT_K3_COMMON_OPS) += phy-k3-common.o +diff --git a/drivers/phy/spacemit/phy-k3-combo.c b/drivers/phy/spacemit/phy-k3-combo.c +new file mode 100644 +index 000000000000..abd0aad18893 +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-combo.c +@@ -0,0 +1,252 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * phy-k3-usb3.c - SpacemiT K3 Type-C Orientation Switch Driver ++ * ++ * Copyright (c) 2025 SpacemiT Technology Co. Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-k3-common.h" ++ ++/* ++ * The PCIE/USB Subsystem on SpacemiT K3 have 3 single lane PIPE3 PHYs ++ * (PHY2/3/4) shared by PCIE PortC/D and USB3 PortB/C/D. ++ * ++ * PMUA_PCIE_SUBSYS_MGMT[4:0] ++ * ++ * bit4 = 0 : PCIe A X8 mode, all 8 lanes dedicated to PCIe Port A ++ * 1 : PHY lanes shared between PCIe or USB according to [3:0] ++ * ++ * All PHY matrix combinations according to [4:0]: ++ * ++ * 0x0X : PCIe-A X8 ++ * 0x10 : PCIe-C x2 (PHY2+PHY3) + PCIe-D x1 (PHY4) ++ * 0x11 : PCIe-C x2 (PHY2+PHY3) + USB-D (PHY4) ++ * 0x12 : PCIe-C x1 (PHY2) + USB-C (PHY3) ++ * 0x13 : PCIe-C x1 (PHY2) + USB-C (PHY3) + USB-D (PHY4) ++ * 0x14 : PCIe-C x1 (PHY3) + USB-B (PHY2) ++ * 0x15 : PCIe-C x1 (PHY3) + USB-B (PHY2) + USB-D (PHY4) ++ * 0x16 : USB-B (PHY2) + USB-C (PHY3) + PCIe D x1 (PHY4) ++ * 0x17 : USB-B (PHY2) + USB-C (PHY3) + USB-D (PHY4) ++ * ++ * So any USB Port B/C/D operation requires PCIe A X8 mode to be disabled. ++ */ ++#define PMUA_PCIE_SUBSYS_MGMT 0x1d8 ++#define PU_MATRIX_CONF_MASK GENMASK(4, 0) ++ ++#define COMBPHY_MAX_SUBPHYS 6 ++ ++struct k3_combo_phy { ++ struct device *dev; ++ struct k3_lane_group groups[COMBPHY_MAX_SUBPHYS]; ++ void __iomem *base; ++ struct regmap *apb_spare; ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group0 = { ++ .lanes = 2, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x0, 0x400 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group1 = { ++ .lanes = 2, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x100000, 0x100400 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group2 = { ++ .lanes = 1, ++ .config = 0x14, ++ .mask = 0x14, ++ .offsets = { ++ 0x200000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group3 = { ++ .lanes = 1, ++ .config = 0x12, ++ .mask = 0x12, ++ .offsets = { ++ 0x300000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group4 = { ++ .lanes = 1, ++ .config = 0x11, ++ .mask = 0x11, ++ .offsets = { ++ 0x400000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data k3_combphy_lane_group5 = { ++ .lanes = 1, ++ .config = 0xff, ++ .mask = 0x00, ++ .offsets = { ++ 0x500000 ++ }, ++}; ++ ++static const struct k3_phy_lane_group_data *k3_combphy_lane_datas[] = { ++ &k3_combphy_lane_group0, ++ &k3_combphy_lane_group1, ++ &k3_combphy_lane_group2, ++ &k3_combphy_lane_group3, ++ &k3_combphy_lane_group4, ++ &k3_combphy_lane_group5, ++}; ++ ++static int k3_combo_phy_init_lanes(struct k3_combo_phy *phy, unsigned int config) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(k3_combphy_lane_datas); i++) { ++ const struct k3_phy_lane_group_data *data = k3_combphy_lane_datas[i]; ++ struct k3_lane_group *lg = &phy->groups[i]; ++ const struct phy_ops *ops; ++ bool is_usb; ++ ++ is_usb = (data->mask & config) == data->config; ++ if (is_usb) ++ ops = &k3_usb3_phy_ops; ++ else ++ ops = &k3_pcie_phy_ops; ++ ++ dev_dbg(phy->dev, "phy %d is %s\n", i, is_usb ? "usb" : "pcie"); ++ ++ lg->phy = devm_phy_create(phy->dev, NULL, ops); ++ if (IS_ERR(lg->phy)) ++ return PTR_ERR(lg->phy); ++ ++ lg->is_pcie = !is_usb; ++ lg->data = data; ++ lg->base = phy->base; ++ phy_set_drvdata(lg->phy, lg); ++ } ++ ++ return 0; ++} ++ ++static int k3_combo_phy_update_config(struct regmap *apmu, unsigned int config) ++{ ++ if (config & ~PU_MATRIX_CONF_MASK) ++ return -EINVAL; ++ ++ return regmap_update_bits(apmu, PMUA_PCIE_SUBSYS_MGMT, PU_MATRIX_CONF_MASK, config); ++} ++ ++static struct phy *k3_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) ++{ ++ struct k3_combo_phy *phy = dev_get_drvdata(dev); ++ struct k3_lane_group *lg; ++ ++ if (args->args_count != 2) { ++ dev_err(dev, "Invalid number of arguments\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (args->args[0] >= ARRAY_SIZE(k3_combphy_lane_datas)) { ++ dev_err(dev, "Invalid PHY id\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ lg = &phy->groups[args->args[0]]; ++ ++ if ((lg->is_pcie && args->args[1] != PHY_TYPE_PCIE) || ++ (!lg->is_pcie && args->args[1] != PHY_TYPE_USB3)) { ++ dev_err(dev, "Invalid PHY mode\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ return lg->phy; ++} ++ ++static int k3_combo_phy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct phy_provider *provider; ++ struct k3_combo_phy *phy; ++ struct regmap *apmu; ++ u32 config = 0; ++ int ret; ++ ++ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); ++ if (!phy) ++ return -ENOMEM; ++ ++ phy->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(phy->base)) ++ return PTR_ERR(phy->base); ++ ++ phy->apb_spare = syscon_regmap_lookup_by_phandle(node, "spacemit,apb-spare"); ++ if (IS_ERR(phy->apb_spare)) ++ return dev_err_probe(dev, PTR_ERR(phy->apb_spare), ++ "Failed to fine APB SPARE syscon"); ++ ++ apmu = syscon_regmap_lookup_by_phandle_args(node, "spacemit,apmu", 1, &config); ++ if (IS_ERR(apmu)) ++ return dev_err_probe(dev, PTR_ERR(apmu), ++ "Failed to find APMU syscon"); ++ ++ ret = k3_combo_phy_update_config(apmu, config); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to set lane configuration"); ++ ++ phy->dev = dev; ++ platform_set_drvdata(pdev, phy); ++ ++ ret = k3_phy_calibrate(phy->apb_spare); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to calibrate phy"); ++ ++ ret = k3_combo_phy_init_lanes(phy, config); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Failed to init lanes"); ++ ++ provider = devm_of_phy_provider_register(dev, k3_combo_phy_xlate); ++ if (IS_ERR(provider)) ++ return dev_err_probe(dev, PTR_ERR(provider), ++ "Failed to register provider\n"); ++ ++ return 0; ++} ++ ++static const struct of_device_id k3_combo_phy_of_match[] = { ++ { .compatible = "spacemit,k3-combo-phy" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, k3_combo_phy_of_match); ++ ++static struct platform_driver k3_combo_phy_driver = { ++ .probe = k3_combo_phy_probe, ++ .driver = { ++ .name = "spacemit,k3-combo-phy", ++ .of_match_table = k3_combo_phy_of_match, ++ }, ++}; ++module_platform_driver(k3_combo_phy_driver); ++ ++MODULE_DESCRIPTION("SpacemiT K3 USB3/PCIe combo PHY driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/phy/spacemit/phy-k3-common.c b/drivers/phy/spacemit/phy-k3-common.c +new file mode 100644 +index 000000000000..840524cbe533 +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-common.c +@@ -0,0 +1,372 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "phy-k3-common.h" ++ ++/* PHY Registers */ ++#define PHY_VERSION 0x0 ++ ++#define PHY_RESET_CFG 0x04 ++ ++#define PHY_RESET_RXBUF_RST BIT(0) ++#define PHY_RESET_SOFT_RST_PCS BIT(1) ++#define PHY_RESET_SOFT_RST_AHB BIT(2) ++#define PHY_RESET_EN_SD_AFTER_LOCK BIT(6) ++ ++#define PHY_CLK_CFG 0x08 ++ ++#define PHY_CLK_PLL_READY BIT(0) ++#define PHY_CLK_TXCLK_INV BIT(2) ++#define PHY_CLK_RXCLK_EN BIT(3) ++#define PHY_CLK_TXCLK_EN BIT(4) ++#define PHY_CLK_PCLK_EN BIT(5) ++#define PHY_CLK_PIPE_PCLK_EN BIT(6) ++#define PHY_CLK_REFCLK_FREQ GENMASK(10, 7) ++#define PHY_CLK_REFCLK_24M 2 ++#define PHY_CLK_SW_INIT_DONE BIT(11) ++#define PHY_CLK_PU_SSC_OUT BIT(23) ++ ++#define PHY_MODE_CFG 0x0C ++ ++#define PHY_MODE_PCIE_INT_EN BIT(0) ++#define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8) ++#define PHY_MODE_LFPS_TPERIOD_USB 3 ++ ++#define PHY_PU_SEL 0x40 ++ ++#define PHY_PU_CFG_STATUS BIT(9) ++#define PHY_PU_OVRD_STATUS BIT(10) ++ ++#define PHY_PU_CK_REG 0x54 ++ ++#define PHY_PU_REFCLK_100 BIT(25) ++ ++#define PHY_PLL_REG1 0x58 ++ ++#define PHY_PLL_FREF_SEL GENMASK(15, 13) ++#define PHY_PLL_FREF_24M 0x1 ++#define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24) ++#define PHY_PLL_SSC_5000PPM 0xa ++#define PHY_PLL_SSC_MODE GENMASK(29, 28) ++#define PHY_PLL_SSC_MODE_CENTER_SPREAD 0 ++#define PHY_PLL_SSC_MODE_UP_SPREAD 1 ++#define PHY_PLL_SSC_MODE_DOWN_SPREAD 2 ++#define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3 ++ ++#define PHY_PLL_REG2 0x5c ++ ++#define PHY_PLL_SEL_REF100 BIT(21) ++ ++/* PHY RX Register Definitions */ ++#define PHY_RX_REG_A 0x60 ++ ++#define PHY_RX_REG0_RLOAD BIT(4) ++#define PHY_RX_REG1_RTERM GENMASK(11, 8) ++#define PHY_RX_REG1_RC_CALI GENMASK(15, 12) ++#define PHY_RX_REG2_CSEL GENMASK(19, 16) ++#define PHY_RX_REG2_FORCE_CSEL BIT(20) ++#define PHY_RX_REG2_PSEL GENMASK(23, 21) ++#define PHY_RX_REG3_I_LOAD GENMASK(26, 24) ++#define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27) ++#define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28) ++#define PHY_RX_REG3_RDEG1 GENMASK(31, 30) ++ ++#define PHY_RX_REG_B 0x64 ++ ++#define PHY_RX_REGB_MASK GENMASK(23, 0) ++ ++#define PHY_RX_REG4_RDEG2 GENMASK(2, 1) ++#define PHY_RX_REG4_ENVOS BIT(4) ++#define PHY_RX_REG4_RTERM_SEL BIT(5) ++#define PHY_RX_REG4_MANUAL_CFG BIT(7) ++#define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8) ++#define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12) ++#define PHY_RX_REG6_H1_REG GENMASK(19, 16) ++#define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20) ++#define PHY_RX_REG6_BYPASS_ADPT BIT(22) ++ ++#define PHY_ADPT_CFG0 0x140 ++#define PHY_ADPT_AFE_RST_OVRD_EN BIT(1) ++#define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4) ++ ++#define PHY_RXEQ_TIME 0xb4 ++#define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21) ++#define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22) ++#define PHY_RXEQ_TIME_AMP_SOC_650M 0 ++#define PHY_RXEQ_TIME_AMP_SOC_800M 1 ++#define PHY_RXEQ_TIME_AMP_SOC_870M 2 ++#define PHY_RXEQ_TIME_AMP_SOC_900M 3 ++#define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24) ++ ++#define PCIE_PU_ADDR_CLK_CFG 0x0008 ++#define PHY_CLK_PLL_READY BIT(0) ++#define PCIE_INITAL_TIMER GENMASK(6, 3) ++#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7) ++#define CFG_SW_PHY_INIT_DONE BIT(11) ++ ++/* Lane RX/TX configuration (per‑lane, at lane_base) */ ++#define PCIE_RX_REG1 0x050 ++#define PCIE_TX_REG1 0x064 ++ ++#define PCIE_PLL_TIMEOUT 500000 ++#define PCIE_POLL_DELAY 500 ++ ++static int k3_usb3phy_init_single(struct k3_lane_group *lg, void __iomem *base) ++{ ++ struct phy *phy = lg->phy; ++ u32 val, tmp; ++ int ret; ++ ++ /* Do not wait CDR lock before sampling data */ ++ val = readl(base + PHY_RESET_CFG); ++ val = u32_replace_bits(val, 0, PHY_RESET_EN_SD_AFTER_LOCK); ++ writel(val, base + PHY_RESET_CFG); ++ ++ /* Power down 100MHz refclk buffer */ ++ val = readl(base + PHY_PU_CK_REG); ++ val = u32_replace_bits(val, 0, PHY_PU_REFCLK_100); ++ writel(val, base + PHY_PU_CK_REG); ++ ++ /* Program PLL REG1 configure the SSC */ ++ val = FIELD_PREP(PHY_PLL_SSC_MODE, PHY_PLL_SSC_MODE_DOWN_SPREAD1) | ++ FIELD_PREP(PHY_PLL_SSC_DEP_SEL, PHY_PLL_SSC_5000PPM) | ++ FIELD_PREP(PHY_PLL_FREF_SEL, PHY_PLL_FREF_24M); ++ writel(val, base + PHY_PLL_REG1); ++ ++ /* Un-select 100MHz PLL reference */ ++ val = readl(base + PHY_PLL_REG2); ++ val = u32_replace_bits(val, 0, PHY_PLL_SEL_REF100); ++ writel(val, base + PHY_PLL_REG2); ++ ++ /* USB LFPS period configuration */ ++ val = readl(base + PHY_MODE_CFG); ++ val = u32_replace_bits(val, PHY_MODE_LFPS_TPERIOD_USB, PHY_MODE_LFPS_TPERIOD); ++ writel(val, base + PHY_MODE_CFG); ++ ++ /* Force AFE adaptation reset */ ++ val = readl(base + PHY_ADPT_CFG0); ++ val |= PHY_ADPT_AFE_RST_OVRD_EN | PHY_ADPT_AFE_RST_OVRD_VAL; ++ writel(val, base + PHY_ADPT_CFG0); ++ ++ /* Override driver amplitude value to 900m */ ++ val = readl(base + PHY_RXEQ_TIME); ++ val |= PHY_RXEQ_TIME_OVRD_AMP_SOC; ++ val = u32_replace_bits(val, PHY_RXEQ_TIME_AMP_SOC_900M, PHY_RXEQ_TIME_CFG_AMP_SOC); ++ writel(val, base + PHY_RXEQ_TIME); ++ ++ /* Configure RX parameters */ ++ val = PHY_RX_REG0_RLOAD | ++ FIELD_PREP(PHY_RX_REG1_RTERM, 0x8) | ++ FIELD_PREP(PHY_RX_REG1_RC_CALI, 0x7) | ++ FIELD_PREP(PHY_RX_REG2_CSEL, 0x8) | ++ PHY_RX_REG2_FORCE_CSEL | ++ FIELD_PREP(PHY_RX_REG2_PSEL, 0x4) | ++ FIELD_PREP(PHY_RX_REG3_I_LOAD, 0x7) | ++ PHY_RX_REG3_SEL_CBOOST_CODE | ++ FIELD_PREP(PHY_RX_REG3_ADJ_BIAS, 0x1) | ++ FIELD_PREP(PHY_RX_REG3_RDEG1, 0x3); ++ writel(val, base + PHY_RX_REG_A); ++ ++ val = readl(base + PHY_RX_REG_B); ++ tmp = FIELD_PREP(PHY_RX_REG4_RDEG2, 0x2) | ++ PHY_RX_REG4_ENVOS | PHY_RX_REG4_RTERM_SEL | PHY_RX_REG4_MANUAL_CFG | ++ FIELD_PREP(PHY_RX_REG5_RCELL_VCM, 0x8) | ++ FIELD_PREP(PHY_RX_REG5_RCELL_BIAS, 0x8) | ++ FIELD_PREP(PHY_RX_REG6_H1_REG, 0x8) | ++ FIELD_PREP(PHY_RX_REG6_ADAPT_GAIN, 0x2); ++ val = u32_replace_bits(val, tmp, PHY_RX_REGB_MASK); ++ writel(val, base + PHY_RX_REG_B); ++ ++ /* ++ * Inform PHY that all PLL-related configuration is done. ++ * PLL will not start locking until PHY_CLK_SW_INIT_DONE is set. ++ */ ++ val = PHY_CLK_SW_INIT_DONE | PHY_CLK_PU_SSC_OUT | ++ FIELD_PREP(PHY_CLK_REFCLK_FREQ, PHY_CLK_REFCLK_24M) | ++ PHY_CLK_RXCLK_EN | PHY_CLK_TXCLK_EN | ++ PHY_CLK_PCLK_EN | PHY_CLK_PIPE_PCLK_EN; ++ writel(val, base + PHY_CLK_CFG); ++ ++ ret = readl_poll_timeout(base + PHY_CLK_CFG, val, ++ (val & PHY_CLK_PLL_READY), ++ PCIE_POLL_DELAY, PCIE_PLL_TIMEOUT); ++ if (ret) { ++ dev_err(&phy->dev, "PHY PLL polling timeout\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int k3_usb3phy_init(struct phy *phy) ++{ ++ struct k3_lane_group *lg = phy_get_drvdata(phy); ++ int ret, i; ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ ret = k3_usb3phy_init_single(lg, lg->base + lg->data->offsets[i]); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++const struct phy_ops k3_usb3_phy_ops = { ++ .init = k3_usb3phy_init, ++ .owner = THIS_MODULE, ++}; ++EXPORT_SYMBOL_GPL(k3_usb3_phy_ops); ++ ++static int k3_pcie_phy_init(struct phy *phy) ++{ ++ struct k3_lane_group *lg = phy_get_drvdata(phy); ++ void __iomem *phy_base = lg->base + lg->data->offsets[0]; ++ u32 val; ++ int ret; ++ int i; ++ ++ val = readl(phy_base + PHY_PLL_REG1); ++ val = u32_replace_bits(val, 0x2, GENMASK(15, 12)); ++ writel(val, phy_base + PHY_PLL_REG1); ++ ++ val = readl(phy_base + PHY_PLL_REG2); ++ val = u32_replace_bits(val, 0, BIT(21)); ++ writel(val, phy_base + PHY_PLL_REG2); ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ void __iomem *lane_base = lg->base + lg->data->offsets[i]; ++ ++ val = readl(lane_base + PCIE_RX_REG1); ++ val = u32_replace_bits(val, 0, 0x3); ++ writel(val, lane_base + PCIE_RX_REG1); ++ } ++ ++ val = readl(phy_base + PHY_PLL_REG2); ++ val |= BIT(20); ++ writel(val, phy_base + PHY_PLL_REG2); ++ ++ writel(0x00006505, phy_base + PCIE_RX_REG1); ++ ++ /* pll_reg1 of lane0, disable SSC: pll[27:24] = 0 */ ++ val = readl(phy_base + PHY_PLL_REG1); ++ val = u32_replace_bits(val, 0, GENMASK(27, 24)); ++ writel(val, phy_base + PHY_PLL_REG1); ++ ++ for (i = 0; i < lg->data->lanes; i++) { ++ void __iomem *lane_base = lg->base + lg->data->offsets[i]; ++ ++ /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */ ++ val = readl(lane_base + PHY_PU_SEL); ++ val = u32_replace_bits(val, 1, BIT(13)); ++ writel(val, lane_base + PHY_PU_SEL); ++ ++ /* disable en_sample_data_after_cdr_locked */ ++ val = readl(lane_base + PHY_RESET_CFG); ++ val = u32_replace_bits(val, 0, BIT(6)); ++ writel(val, lane_base + PHY_RESET_CFG); ++ ++ /* Dynamic Lock */ ++ val = readl(lane_base + PHY_MODE_CFG); ++ val = u32_replace_bits(val, 1, BIT(2)); ++ writel(val, lane_base + PHY_MODE_CFG); ++ ++ val = FIELD_PREP(GENMASK(7, 0), 0x10) | ++ FIELD_PREP(GENMASK(15, 8), 0x78) | ++ FIELD_PREP(GENMASK(23, 16), 0x98) | ++ FIELD_PREP(GENMASK(31, 24), 0xdf); ++ writel(val, lane_base + PHY_RX_REG_A); ++ ++ val = readl(lane_base + PHY_RX_REG_B); ++ val &= ~PHY_RX_REGB_MASK; ++ val |= FIELD_PREP(GENMASK(7, 0), 0xb4) | ++ FIELD_PREP(GENMASK(15, 8), 0x88) | ++ FIELD_PREP(GENMASK(23, 16), 0x28); ++ writel(val, lane_base + PHY_RX_REG_B); ++ ++ /* Set init done */ ++ val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG); ++ val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE); ++ writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG); ++ } ++ ++ ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val, ++ (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY, ++ PCIE_PLL_TIMEOUT); ++ if (ret) { ++ dev_err(&lg->phy->dev, "PHY PLL lock timeout\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++const struct phy_ops k3_pcie_phy_ops = { ++ .init = k3_pcie_phy_init, ++ .owner = THIS_MODULE, ++}; ++EXPORT_SYMBOL_GPL(k3_pcie_phy_ops); ++ ++/* PHY rcal init requires APB_SPARE regmap access */ ++ ++#define APB_SPARE_PU_CAL 0x178 ++#define PU_CAL BIT(17) ++ ++#define APB_SPARE_RCAL_HSIO 0x17c ++#define APB_SPARE_PU_CAL_DONE BIT(8) ++#define RCAL_OVRD_PTRIM GENMASK(23, 20) ++#define RCAL_OVRD_NTRIM GENMASK(27, 24) ++#define RCAL_OVRD_PTRIM_EN BIT(28) ++#define RCAL_OVRD_NTRIM_EN BIT(29) ++#define RCAL_OVRD_STABLE_VAL BIT(30) ++#define RCAL_OVRD_STABLE_EN BIT(31) ++ ++#define RCAL_OVRD_TRIM_EN (RCAL_OVRD_NTRIM_EN | RCAL_OVRD_PTRIM_EN) ++#define RCAL_OVRD_TRIM_MASK (RCAL_OVRD_NTRIM | RCAL_OVRD_PTRIM) ++ ++#define PU_CAL_TIMEOUT 2000000 ++ ++static DEFINE_MUTEX(calibrate_lock); ++ ++int k3_phy_calibrate(struct regmap *apb_spare) ++{ ++ unsigned int val = 0; ++ int ret; ++ ++ guard(mutex)(&calibrate_lock); ++ ++ regmap_read(apb_spare, APB_SPARE_RCAL_HSIO, &val); ++ if (val & APB_SPARE_PU_CAL_DONE) ++ return 0; ++ ++ regmap_update_bits(apb_spare, APB_SPARE_PU_CAL, PU_CAL, ++ PU_CAL); ++ ++ ret = regmap_read_poll_timeout(apb_spare, APB_SPARE_RCAL_HSIO, ++ val, (val & APB_SPARE_PU_CAL_DONE), PCIE_POLL_DELAY, ++ PU_CAL_TIMEOUT); ++ ++ if (ret) ++ regmap_update_bits(apb_spare, APB_SPARE_RCAL_HSIO, ++ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | ++ RCAL_OVRD_TRIM_MASK | RCAL_OVRD_STABLE_EN, ++ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL | ++ FIELD_PREP(RCAL_OVRD_NTRIM, 0x6) | ++ FIELD_PREP(RCAL_OVRD_PTRIM, 0xa) | ++ RCAL_OVRD_STABLE_EN); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(k3_phy_calibrate); ++ ++MODULE_DESCRIPTION("SpacemiT K3 PHY common ops"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/phy/spacemit/phy-k3-common.h b/drivers/phy/spacemit/phy-k3-common.h +new file mode 100644 +index 000000000000..49009c3c313a +--- /dev/null ++++ b/drivers/phy/spacemit/phy-k3-common.h +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++ ++#ifndef _PHY_K3_COMMON_H ++#define _PHY_K3_COMMON_H ++ ++#include ++ ++struct k3_phy_lane_group_data { ++ u32 lanes; ++ u8 config; ++ u8 mask; ++ u32 offsets[] __counted_by(lanes); ++}; ++ ++struct k3_lane_group { ++ const struct k3_phy_lane_group_data *data; ++ void __iomem *base; ++ struct phy *phy; ++ bool is_pcie; ++}; ++ ++extern const struct phy_ops k3_pcie_phy_ops; ++extern const struct phy_ops k3_usb3_phy_ops; ++ ++int k3_phy_calibrate(struct regmap *apb_spare); ++ ++#endif +-- +2.53.0 + diff --git a/SPECS/linux/0269-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch b/SPECS/linux/0269-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch new file mode 100644 index 0000000000..ec9432f984 --- /dev/null +++ b/SPECS/linux/0269-RUYI-riscv-dts-spacemit-k3-add-USB-controller-and-US.patch @@ -0,0 +1,106 @@ +From 8dfe6a034348d24ae0381212ae169bb1a511e257 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Fri, 27 Feb 2026 09:46:06 +0800 +Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: add USB controller and + USB phy support + +Add all USB device node to the Spacemit K3. + +Signed-off-by: Inochi Amaoto +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++ + 2 files changed, 55 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index ac965ec83f2c..acfbb5029c15 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -183,6 +183,11 @@ dldo7: dldo7 { + }; + }; + ++&combophy { ++ spacemit,apmu = <&syscon_apmu 0x11>; ++ status = "okay"; ++}; ++ + ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; +@@ -280,3 +285,11 @@ hub@1 { + &usb2_phy { + status = "okay"; + }; ++ ++&usb3d_u2phy { ++ status = "okay"; ++}; ++ ++&usb3d { ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index 1b86c872accb..e73e6838f6b0 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + + /dts-v1/; + +@@ -637,6 +638,47 @@ pdma: dma-controller@d4000000 { + status = "disabled"; + }; + ++ usb3d: usb@81a00000 { ++ compatible = "spacemit,k3-dwc3"; ++ reg = <0x0 0x81a00000 0x0 0x10000>; ++ interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-parent = <&saplic>; ++ clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; ++ clock-names = "usbdrd30"; ++ resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, ++ <&syscon_apmu RESET_APMU_USB3_D_VCC>, ++ <&syscon_apmu RESET_APMU_USB3_D_PHY>; ++ reset-names = "ahb", "vcc", "phy"; ++ phys = <&usb3d_u2phy>, ++ <&combophy 4 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi"; ++ snps,dis_enblslpm_quirk; ++ snps,dis_u2_susphy_quirk; ++ snps,dis_u3_susphy_quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,parkmode-disable-ss-quirk; ++ dr_mode = "host"; ++ status = "disabled"; ++ }; ++ ++ usb3d_u2phy: phy@81b00000 { ++ compatible = "spacemit,k3-usb2-phy"; ++ reg = <0x0 0x81b00000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_APMU_USB2_BUS>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ combophy: phy@81d00000 { ++ compatible = "spacemit,k3-combo-phy"; ++ reg = <0x0 0x81d00000 0x0 0x600000>; ++ #phy-cells = <2>; ++ spacemit,apb-spare = <&pll>; ++ status = "disabled"; ++ }; ++ + usb2_host: usb@c0a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0xc0a00000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux/0269-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch b/SPECS/linux/0269-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch deleted file mode 100644 index fe0aa8e403..0000000000 --- a/SPECS/linux/0269-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 9664b629f655a39a7c67de5e4669718549f87b3e Mon Sep 17 00:00:00 2001 -From: Zhang Meng -Date: Wed, 4 Feb 2026 08:54:40 +0800 -Subject: [PATCH 269/269] RVCK: driver: clk: k3: keep some system based clock - always on - -FROM: https://github.com/RVCK-Project/rvck/pull/213 - -community inclusion -category: bugfix -bugzilla: https://github.com/RVCK-Project/rvck/issues/212 - --------------------------------- - -The hdma clk is used by some component of CCI bus, it should -be keep always on, regardless of whether hdma enabled. - -The rcpu clk should be always on because it is running backround. - -Signed-off-by: Zhang Meng -Signed-off-by: Han Gao ---- - drivers/clk/spacemit/ccu-k3.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c -index 03de04144963..6acde3b76b7b 100644 ---- a/drivers/clk/spacemit/ccu-k3.c -+++ b/drivers/clk/spacemit/ccu-k3.c -@@ -866,7 +866,7 @@ static const struct clk_parent_data rcpu_clk_parents[] = { - CCU_PARENT_HW(pll1_d6_409p6), - }; - CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, -- 4, 3, BIT(15), 7, 3, BIT(12), 0); -+ 4, 3, BIT(15), 7, 3, BIT(12), CLK_IS_CRITICAL); - - static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { - CCU_PARENT_HW(pll1_d48_51p2_ap), -@@ -1026,7 +1026,7 @@ CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CT - /* APMU clocks end */ - - /* DCIU clocks start */ --CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); -+CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), CLK_IS_CRITICAL); - CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); - CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); - CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); --- -2.53.0 - diff --git a/SPECS/linux/0270-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch b/SPECS/linux/0270-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch new file mode 100644 index 0000000000..09ff72ef48 --- /dev/null +++ b/SPECS/linux/0270-RUYI-riscv-dts-spacemit-k3-Add-PCIe-device-node.patch @@ -0,0 +1,261 @@ +From 77881b831ca947a7c8a79aa3518920eb9a3365d0 Mon Sep 17 00:00:00 2001 +From: Inochi Amaoto +Date: Tue, 24 Mar 2026 11:06:24 +0800 +Subject: [RUYI PATCH] RUYI: riscv: dts: spacemit: k3: Add PCIe device node + +Add all PCIe device node for Spacemit K3. + +Signed-off-by: Inochi Amaoto +Signed-off-by: Han Gao +--- + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++ + arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 33 ++++ + arch/riscv/boot/dts/spacemit/k3.dtsi | 150 +++++++++++++++++++ + 3 files changed, 212 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +index acfbb5029c15..f24ada15f182 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts ++++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +@@ -264,6 +264,35 @@ uboot@210000 { + }; + }; + ++&pcie0_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_0_cfg>; ++ phys = <&combophy 0 PHY_TYPE_PCIE>, ++ <&combophy 1 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0", "pcie-phy1"; ++ num-lanes = <4>; ++ status = "okay"; ++}; ++ ++&pcie2_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_cfg>; ++ phys = <&combophy 2 PHY_TYPE_PCIE>, ++ <&combophy 3 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0", "pcie-phy1"; ++ num-lanes = <2>; ++ status = "okay"; ++}; ++ ++&pcie4_rc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie4_0_cfg>; ++ phys = <&combophy 5 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy0"; ++ num-lanes = <1>; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +index 846d5e8cc783..5a817610101b 100644 +--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +@@ -710,4 +710,37 @@ uart0-0-pins { + drive-strength = <25>; + }; + }; ++ ++ pcie0_0_cfg: pcie0-0-cfg { ++ pcie0-0-pins { ++ pinmux = , /* pcie0 perst */ ++ ; /* pcie0 clkreq */ ++ ++ bias-pull-up = <1>; ++ drive-strength = <33>; ++ power-source = <1800>; ++ }; ++ }; ++ ++ pcie2_0_cfg: pcie2-0-cfg { ++ pcie2-0-pins { ++ pinmux = , /* pcie2 perst */ ++ ; /* pcie2 clkreq */ ++ ++ drive-strength = <38>; ++ power-source = <3300>; ++ }; ++ }; ++ ++ pcie4_0_cfg: pcie4-0-cfg { ++ pcie4-0-pins { ++ pinmux = , /* pcie4 perst */ ++ , /* pcie4 wake */ ++ ; /* pcie4 clkreq */ ++ ++ bias-pull-up = <1>; ++ drive-strength = <33>; ++ power-source = <1800>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi +index e73e6838f6b0..9552089c7c73 100644 +--- a/arch/riscv/boot/dts/spacemit/k3.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k3.dtsi +@@ -638,6 +638,156 @@ pdma: dma-controller@d4000000 { + status = "disabled"; + }; + ++ pcie0_rc: pcie@80000000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80000000 0x0 0x00001000>, ++ <0x0 0x80100000 0x0 0x00001000>, ++ <0x0 0x80300000 0x0 0x00003f20>, ++ <0x11 0x00000000 0x0 0x00010000>, ++ <0x0 0x82900000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTA_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTA_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTA_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>, ++ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_A_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_A_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_A_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ linux,pci-domain = <0>; ++ spacemit,apmu = <&syscon_apmu 0x1f0>; ++ status = "disabled"; ++ }; ++ ++ pcie1_rc: pcie@80400000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80400000 0x0 0x00001000>, ++ <0x0 0x80500000 0x0 0x00001000>, ++ <0x0 0x80700000 0x0 0x00003f20>, ++ <0x11 0x80000000 0x0 0x00010000>, ++ <0x0 0x82c00000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTB_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTB_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTB_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00010000 0x11 0x80010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x80110000 0x11 0x80110000 0x0 0x7fef0000>, ++ <0x43000000 0x16 0x00000000 0x16 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_B_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_B_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_B_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ linux,pci-domain = <1>; ++ spacemit,apmu = <&syscon_apmu 0x1d0>; ++ status = "disabled"; ++ }; ++ ++ pcie2_rc: pcie@80800000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80800000 0x0 0x00001000>, ++ <0x0 0x80900000 0x0 0x00001000>, ++ <0x0 0x80b00000 0x0 0x00003f20>, ++ <0x12 0x00000000 0x0 0x00010000>, ++ <0x0 0x82d00000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTC_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTC_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTC_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x00 0x00000000 0x12 0x00010000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00110000 0x12 0x00110000 0x0 0x7fef0000>, ++ <0x43000000 0x15 0x00000000 0x15 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_C_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_C_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_C_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <2>; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1c8>; ++ status = "disabled"; ++ }; ++ ++ pcie3_rc: pcie@80c00000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x80c00000 0x0 0x00001000>, ++ <0x0 0x80d00000 0x0 0x00001000>, ++ <0x0 0x80f00000 0x0 0x00003f20>, ++ <0x12 0x80000000 0x0 0x00010000>, ++ <0x0 0x82a00000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTD_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTD_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTD_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00010000 0x12 0x80010000 0x0 0x100000>, ++ <0x02000000 0x0 0x80110000 0x12 0x80110000 0x0 0x3fef0000>, ++ <0x43000000 0x14 0x00000000 0x14 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_D_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_D_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_D_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <3>; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1e0>; ++ status = "disabled"; ++ }; ++ ++ pcie4_rc: pcie@81000000 { ++ compatible = "spacemit,k3-pcie"; ++ reg = <0x0 0x81000000 0x0 0x00001000>, ++ <0x0 0x81100000 0x0 0x00001000>, ++ <0x0 0x81300000 0x0 0x00003f20>, ++ <0x12 0xc0000000 0x0 0x00010000>, ++ <0x0 0x82b00000 0x0 0x00001000>; ++ reg-names = "dbi", "dbi2", "atu", "config", "link"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ clocks = <&syscon_apmu CLK_APMU_PCIE_PORTE_DBI>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTE_MSTE>, ++ <&syscon_apmu CLK_APMU_PCIE_PORTE_SLV>; ++ clock-names = "dbi", "mstr", "slv"; ++ msi-parent = <&simsic>; ++ ranges = <0x01000000 0x0 0x00000000 0x12 0xc0010000 0x0 0x100000>, ++ <0x02000000 0x0 0xc0110000 0x12 0xc0110000 0x0 0x3fef0000>, ++ <0x43000000 0x13 0x00000000 0x13 0x00000000 0x1 0x00000000>; ++ resets = <&syscon_apmu RESET_APMU_PCIE_E_DBI>, ++ <&syscon_apmu RESET_APMU_PCIE_E_MASTER>, ++ <&syscon_apmu RESET_APMU_PCIE_E_SLAVE>; ++ reset-names = "dbi", "mstr", "slv"; ++ linux,pci-domain = <4>; ++ bus-range = <0x00 0xff>; ++ max-link-speed = <3>; ++ spacemit,apmu = <&syscon_apmu 0x1e8>; ++ status = "disabled"; ++ }; ++ + usb3d: usb@81a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0x81a00000 0x0 0x10000>; +-- +2.53.0 + diff --git a/SPECS/linux/0271-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch b/SPECS/linux/0271-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch new file mode 100644 index 0000000000..c4c9a637dd --- /dev/null +++ b/SPECS/linux/0271-RUYI-PCI-add-SpacemiT-vendor-id-and-its-K3-device-id.patch @@ -0,0 +1,34 @@ +From 7dd093fcb65385a50dfa5f2ceace2e86feae4578 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Wed, 20 May 2026 23:28:15 +0800 +Subject: [RUYI PATCH] RUYI: PCI: add SpacemiT vendor id and its K3 device id + to pci_ids + +The SpacemiT K3 chip's root complex needs to be listed in the allowlist +of rtw89 driver to allow 36-bit DMA. + +Add the vendor and device IDs to pci_ids.h header file. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Han Gao +--- + include/linux/pci_ids.h | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h +index 9663be526dd0..6386d4c72103 100644 +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2640,6 +2640,9 @@ + #define PCI_VENDOR_ID_SUNIX 0x1fd4 + #define PCI_DEVICE_ID_SUNIX_1999 0x1999 + ++#define PCI_VENDOR_ID_SPACEMIT 0x201f ++#define PCI_DEVICE_ID_SPACEMIT_K3 0x0002 ++ + #define PCI_VENDOR_ID_HINT 0x3388 + #define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013 + +-- +2.53.0 + diff --git a/SPECS/linux/0272-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch b/SPECS/linux/0272-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch new file mode 100644 index 0000000000..358dec36a2 --- /dev/null +++ b/SPECS/linux/0272-RUYI-wifi-rtw89-pci-add-SpacemiT-K3-to-36-bit-DMA-al.patch @@ -0,0 +1,36 @@ +From f3b776c5c4a9499f02e7844675bed8907be164e9 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Wed, 20 May 2026 23:29:46 +0800 +Subject: [RUYI PATCH] RUYI: wifi: rtw89: pci: add SpacemiT K3 to 36-bit DMA + allowlist + +The SpacemiT K3 platform has no system memory in the 32-bit address +space, and it's verified that the chip works well with 36-bit DMA of +RTL8852BE. + +Add it to the 36-bit DMA allowlist of rtw89_pci. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Han Gao +--- + drivers/net/wireless/realtek/rtw89/pci.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c +index 43c61b3dc969..6470d09f17f3 100644 +--- a/drivers/net/wireless/realtek/rtw89/pci.c ++++ b/drivers/net/wireless/realtek/rtw89/pci.c +@@ -3312,6 +3312,10 @@ static bool rtw89_pci_is_dac_compatible_bridge(struct rtw89_dev *rtwdev) + if (bridge->device == 0x2806) + return true; + break; ++ case PCI_VENDOR_ID_SPACEMIT: ++ if (bridge->device == PCI_DEVICE_ID_SPACEMIT_K3) ++ return true; ++ break; + } + + return false; +-- +2.53.0 + diff --git a/SPECS/linux/0273-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch b/SPECS/linux/0273-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch new file mode 100644 index 0000000000..248870f723 --- /dev/null +++ b/SPECS/linux/0273-RUYI-drm-amdgpu-disable-dynamic-PCIe-speed-switch-on.patch @@ -0,0 +1,57 @@ +From 875548afc48a498da208bc8f722769e8c9f0a88c Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Tue, 19 May 2026 19:57:52 +0800 +Subject: [RUYI PATCH] RUYI: drm/amdgpu: disable dynamic PCIe speed switch on + SpacemiT K3 + +The dynamic speed switch functionality seems to be broken on SpacemiT +K3, and leads to frequent GPU crashes at least with Polaris GPUs. + +Disable dynamic speed switch on this platform. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Han Gao +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 2ec69fa05cb1..05ebd1b7502f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -2004,6 +2004,14 @@ bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev) + */ + static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev) + { ++ struct pci_dev *parent = adev->pdev; ++ static const struct pci_device_id broken_devids[] = { ++ /* SpacemiT K3 */ ++ { PCI_DEVICE(PCI_VENDOR_ID_SPACEMIT, ++ PCI_DEVICE_ID_SPACEMIT_K3) }, ++ {} ++ }; ++ + #if IS_ENABLED(CONFIG_X86) + struct cpuinfo_x86 *c = &cpu_data(0); + +@@ -2014,6 +2022,17 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device + if (c->x86_vendor == X86_VENDOR_INTEL) + return false; + #endif ++ /* skip upstream/downstream switches internal to dGPU */ ++ while (parent && parent->vendor == PCI_VENDOR_ID_ATI) { ++ parent = pci_upstream_bridge(parent); ++ } ++ ++ if (!parent) ++ return true; ++ ++ if (pci_match_id(broken_devids, parent)) ++ return false; ++ + return true; + } + +-- +2.53.0 + diff --git a/SPECS/linux/0274-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch b/SPECS/linux/0274-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch new file mode 100644 index 0000000000..1e588d8e04 --- /dev/null +++ b/SPECS/linux/0274-RVCK-driver-clk-k3-keep-some-system-based-clock-alwa.patch @@ -0,0 +1,50 @@ +From 5ef99d2db590e72fc08215b1b0ac74ee6386ea77 Mon Sep 17 00:00:00 2001 +From: Zhang Meng +Date: Wed, 4 Feb 2026 08:54:40 +0800 +Subject: [RUYI PATCH] RVCK: driver: clk: k3: keep some system based clock + always on + +FROM: https://github.com/RVCK-Project/rvck/pull/213 + +community inclusion +category: bugfix +bugzilla: https://github.com/RVCK-Project/rvck/issues/212 + +-------------------------------- + +The hdma clk is used by some component of CCI bus, it should +be keep always on, regardless of whether hdma enabled. + +The rcpu clk should be always on because it is running backround. + +Signed-off-by: Zhang Meng +Signed-off-by: Han Gao +--- + drivers/clk/spacemit/ccu-k3.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c +index 03de04144963..6acde3b76b7b 100644 +--- a/drivers/clk/spacemit/ccu-k3.c ++++ b/drivers/clk/spacemit/ccu-k3.c +@@ -866,7 +866,7 @@ static const struct clk_parent_data rcpu_clk_parents[] = { + CCU_PARENT_HW(pll1_d6_409p6), + }; + CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL, +- 4, 3, BIT(15), 7, 3, BIT(12), 0); ++ 4, 3, BIT(15), 7, 3, BIT(12), CLK_IS_CRITICAL); + + static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = { + CCU_PARENT_HW(pll1_d48_51p2_ap), +@@ -1026,7 +1026,7 @@ CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CT + /* APMU clocks end */ + + /* DCIU clocks start */ +-CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), 0); ++CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), CLK_IS_CRITICAL); + CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0); + CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0); + CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0); +-- +2.53.0 + diff --git a/SPECS/linux/0275-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch b/SPECS/linux/0275-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch new file mode 100644 index 0000000000..e6eb17dc3e --- /dev/null +++ b/SPECS/linux/0275-RUYI-mmc-sdhci-of-dwcmshc-Add-support-for-SG2042-FPG.patch @@ -0,0 +1,65 @@ +From b29ac805c857da28d04d2907b7bd6fe2dab7e996 Mon Sep 17 00:00:00 2001 +From: Vivian Wang +Date: Thu, 28 May 2026 14:18:23 +0800 +Subject: [RUYI PATCH] RUYI: mmc: sdhci-of-dwcmshc: Add support for SG2042 FPGA + variant + +Add support for a testing variant of the SG2042 SDHCI controller without +PHY reset and without the "timer" clock. + +Signed-off-by: Vivian Wang +Signed-off-by: Han Gao +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index bf2cb49ddd81..b16d34c4c4c9 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -1743,6 +1743,16 @@ static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { + .platform_execute_tuning = th1520_execute_tuning, + }; + ++static const struct sdhci_ops sdhci_dwcmshc_sg2042_fpga_ops = { ++ .set_clock = sdhci_set_clock, ++ .set_bus_width = sdhci_set_bus_width, ++ .set_uhs_signaling = dwcmshc_set_uhs_signaling, ++ .get_max_clock = dwcmshc_get_max_clock, ++ .reset = sdhci_reset, ++ .adma_write_desc = dwcmshc_adma_write_desc, ++ .platform_execute_tuning = th1520_execute_tuning, ++}; ++ + static const struct sdhci_ops sdhci_dwcmshc_eic7700_ops = { + .set_clock = sdhci_eic7700_set_clock, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, +@@ -1836,6 +1846,14 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { + .init = sg2042_init, + }; + ++static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_fpga_pdata = { ++ .pdata = { ++ .ops = &sdhci_dwcmshc_sg2042_fpga_ops, ++ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, ++ }, ++}; ++ + static const struct dwcmshc_pltfm_data sdhci_dwcmshc_eic7700_pdata = { + .pdata = { + .ops = &sdhci_dwcmshc_eic7700_ops, +@@ -1951,6 +1969,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { + .compatible = "sophgo,sg2042-dwcmshc", + .data = &sdhci_dwcmshc_sg2042_pdata, + }, ++ { ++ .compatible = "sophgo,sg2042-fpga-dwcmshc", ++ .data = &sdhci_dwcmshc_sg2042_fpga_pdata, ++ }, + { + .compatible = "eswin,eic7700-dwcmshc", + .data = &sdhci_dwcmshc_eic7700_pdata, +-- +2.53.0 + diff --git a/SPECS/linux/linux.spec b/SPECS/linux/linux.spec index dec9aa999d..e3ffde4606 100644 --- a/SPECS/linux/linux.spec +++ b/SPECS/linux/linux.spec @@ -34,14 +34,15 @@ %global modpath /lib/modules/%{kernel_full_version} Name: linux -Version: 7.0.10 +Version: 7.0.11 Release: %autorelease Summary: The Linux Kernel License: GPL-2.0-only URL: https://www.kernel.org/ -#!RemoteAsset: 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