From 080972d53cc65eb4451592062a3c9cb4a4271228 Mon Sep 17 00:00:00 2001 From: ZhishengZeng Date: Tue, 15 Sep 2026 10:58:43 +0800 Subject: [PATCH 1/4] refactor(iRT): remove obsolete timing update path --- src/feature/database/feature_irt.h | 5 - src/feature/parser/feature_parser_tools.cpp | 20 -- src/interface/python/py_irt/py_irt_utils.cpp | 4 +- src/interface/tcl/tcl_irt/src/tcl_init_rt.cpp | 2 - src/operation/iRT/interface/RTInterface.cpp | 223 ------------------ src/operation/iRT/interface/RTInterface.hpp | 6 - .../iRT/source/data_manager/DataManager.cpp | 2 - .../source/data_manager/advance/Config.hpp | 1 - .../source/data_manager/advance/Summary.hpp | 5 - .../module/detailed_router/DetailedRouter.cpp | 36 --- .../module/layer_assigner/LayerAssigner.cpp | 45 ---- .../module/planar_router/PlanarRouter.cpp | 44 ---- .../violation_reporter/ViolationReporter.cpp | 36 --- test/fixtures/gcd/config/route_ecc.json | 3 +- 14 files changed, 2 insertions(+), 430 deletions(-) diff --git a/src/feature/database/feature_irt.h b/src/feature/database/feature_irt.h index e60bb3a416..2c6df1b8e8 100644 --- a/src/feature/database/feature_irt.h +++ b/src/feature/database/feature_irt.h @@ -49,7 +49,6 @@ struct PRSummary double total_demand = 0; double total_overflow = 0; double total_wire_length = 0; - std::map> clock_timing_map; std::map type_power_map; }; @@ -63,7 +62,6 @@ struct LASummary double total_wire_length = 0; std::map cut_via_num_map; int32_t total_via_num = 0; - std::map> clock_timing_map; std::map type_power_map; }; @@ -77,7 +75,6 @@ struct SRSummary double total_wire_length = 0; std::map cut_via_num_map; int32_t total_via_num = 0; - std::map> clock_timing_map; std::map type_power_map; }; @@ -99,7 +96,6 @@ struct DRSummary int32_t total_patch_num = 0; std::map routing_violation_num_map; int32_t total_violation_num = 0; - std::map> clock_timing_map; std::map type_power_map; }; @@ -119,7 +115,6 @@ struct VRSummary std::map among_net_violation_type_num_map; std::map among_net_routing_violation_num_map; int32_t among_net_total_violation_num = 0; - std::map> clock_timing_map; std::map type_power_map; }; diff --git a/src/feature/parser/feature_parser_tools.cpp b/src/feature/parser/feature_parser_tools.cpp index b5f1a7ddde..bdd25036da 100644 --- a/src/feature/parser/feature_parser_tools.cpp +++ b/src/feature/parser/feature_parser_tools.cpp @@ -85,10 +85,6 @@ json FeatureParser::buildSummaryRT() pr_json["total_demand"] = summary_irt.pr_summary.total_demand; pr_json["total_overflow"] = summary_irt.pr_summary.total_overflow; pr_json["total_wire_length"] = summary_irt.pr_summary.total_wire_length; - for (auto& [clock_name, timing] : summary_irt.pr_summary.clock_timing_map) { - pr_json["clock_timing_map"]["clock_name"] = clock_name; - pr_json["clock_timing_map"]["timing"] = timing; - } for (auto& [type, power] : summary_irt.pr_summary.type_power_map) { pr_json["type_power_map"]["type"] = type; pr_json["type_power_map"]["power"] = power; @@ -115,10 +111,6 @@ json FeatureParser::buildSummaryRT() la_json["cut_via_num_map"][std::to_string(cut_layer_idx)] = via_num; } la_json["total_via_num"] = summary_irt.la_summary.total_via_num; - for (auto& [clock_name, timing] : summary_irt.la_summary.clock_timing_map) { - la_json["clock_timing_map"]["clock_name"] = clock_name; - la_json["clock_timing_map"]["timing"] = timing; - } for (auto& [type, power] : summary_irt.la_summary.type_power_map) { la_json["type_power_map"]["type"] = type; la_json["type_power_map"]["power"] = power; @@ -148,10 +140,6 @@ json FeatureParser::buildSummaryRT() sr_json["cut_via_num_map"][std::to_string(cut_layer_idx)] = via_num; } sr_json["total_via_num"] = sr_summary.total_via_num; - for (auto& [clock_name, timing] : sr_summary.clock_timing_map) { - sr_json["clock_timing_map"]["clock_name"] = clock_name; - sr_json["clock_timing_map"]["timing"] = timing; - } for (auto& [type, power] : sr_summary.type_power_map) { sr_json["type_power_map"]["type"] = type; sr_json["type_power_map"]["power"] = power; @@ -197,10 +185,6 @@ json FeatureParser::buildSummaryRT() dr_json["routing_violation_num_map"][std::to_string(routing_layer_idx)] = violation_num; } dr_json["total_violation_num"] = dr_summary.total_violation_num; - for (auto& [clock_name, timing] : dr_summary.clock_timing_map) { - dr_json["clock_timing_map"]["clock_name"] = clock_name; - dr_json["clock_timing_map"]["timing"] = timing; - } for (auto& [type, power] : dr_summary.type_power_map) { dr_json["type_power_map"]["type"] = type; dr_json["type_power_map"]["power"] = power; @@ -233,10 +217,6 @@ json FeatureParser::buildSummaryRT() vr_json["among_net_routing_violation_num_map"][std::to_string(routing_layer_idx)] = violation_num; } vr_json["among_net_total_violation_num"] = summary_irt.vr_summary.among_net_total_violation_num; - for (auto& [clock_name, timing] : summary_irt.vr_summary.clock_timing_map) { - vr_json["clock_timing_map"]["clock_name"] = clock_name; - vr_json["clock_timing_map"]["timing"] = timing; - } for (auto& [type, power] : summary_irt.vr_summary.type_power_map) { vr_json["type_power_map"]["type"] = type; vr_json["type_power_map"]["power"] = power; diff --git a/src/interface/python/py_irt/py_irt_utils.cpp b/src/interface/python/py_irt/py_irt_utils.cpp index f9952cb29e..86e52cb659 100644 --- a/src/interface/python/py_irt/py_irt_utils.cpp +++ b/src/interface/python/py_irt/py_irt_utils.cpp @@ -107,8 +107,6 @@ bool initConfigMapByJSON(const std::string& config, std::map& config_map) RTDM.getConfig().bottom_routing_layer = RTUTIL.getConfigValue(config_map, "-bottom_routing_layer", ""); RTDM.getConfig().top_routing_layer = RTUTIL.getConfigValue(config_map, "-top_routing_layer", ""); RTDM.getConfig().output_inter_result = RTUTIL.getConfigValue(config_map, "-output_inter_result", 0); - RTDM.getConfig().enable_timing = RTUTIL.getConfigValue(config_map, "-enable_timing", 0); ///////////////////////////////////////////// } @@ -1451,7 +1450,6 @@ void RTInterface::outputSummary() top_rt_summary.pr_summary.total_demand = rt_summary.pr_summary.total_demand; top_rt_summary.pr_summary.total_overflow = rt_summary.pr_summary.total_overflow; top_rt_summary.pr_summary.total_wire_length = rt_summary.pr_summary.total_wire_length; - top_rt_summary.pr_summary.clock_timing_map = rt_summary.pr_summary.clock_timing_map; } // la_summary { @@ -1463,7 +1461,6 @@ void RTInterface::outputSummary() top_rt_summary.la_summary.total_wire_length = rt_summary.la_summary.total_wire_length; top_rt_summary.la_summary.cut_via_num_map = rt_summary.la_summary.cut_via_num_map; top_rt_summary.la_summary.total_via_num = rt_summary.la_summary.total_via_num; - top_rt_summary.la_summary.clock_timing_map = rt_summary.la_summary.clock_timing_map; } // sr_summary { @@ -1477,7 +1474,6 @@ void RTInterface::outputSummary() top_sr_summary.total_wire_length = sr_summary.total_wire_length; top_sr_summary.cut_via_num_map = sr_summary.cut_via_num_map; top_sr_summary.total_via_num = sr_summary.total_via_num; - top_sr_summary.clock_timing_map = sr_summary.clock_timing_map; } } // ta_summary @@ -1499,7 +1495,6 @@ void RTInterface::outputSummary() top_dr_summary.total_patch_num = dr_summary.total_patch_num; top_dr_summary.routing_violation_num_map = dr_summary.routing_violation_num_map; top_dr_summary.total_violation_num = dr_summary.total_violation_num; - top_dr_summary.clock_timing_map = dr_summary.clock_timing_map; } } // vr_summary @@ -1518,7 +1513,6 @@ void RTInterface::outputSummary() top_rt_summary.vr_summary.among_net_violation_type_num_map = rt_summary.vr_summary.among_net_violation_type_num_map; top_rt_summary.vr_summary.among_net_routing_violation_num_map = rt_summary.vr_summary.among_net_routing_violation_num_map; top_rt_summary.vr_summary.among_net_total_violation_num = rt_summary.vr_summary.among_net_total_violation_num; - top_rt_summary.vr_summary.clock_timing_map = rt_summary.vr_summary.clock_timing_map; } } @@ -1718,223 +1712,6 @@ ids::Shape RTInterface::getIDSShape(int32_t net_idx, LayerRect layer_rect, bool #endif -#if 1 // iSTA - -void RTInterface::updateTiming(std::vector>>& real_pin_coord_map_list, - std::vector>>& routing_segment_list_list, - std::map>& clock_timing) -{ -#if 0 -#if 1 // 数据结构定义 - struct RCPin - { - RCPin() = default; - RCPin(LayerCoord coord, bool is_real_pin, std::string pin_name) - { - _coord = coord; - _is_real_pin = is_real_pin; - _pin_name = pin_name; - } - RCPin(LayerCoord coord, bool is_real_pin, int32_t fake_pin_id) - { - _coord = coord; - _is_real_pin = is_real_pin; - _fake_pin_id = fake_pin_id; - } - ~RCPin() = default; - - LayerCoord _coord; - bool _is_real_pin = false; - std::string _pin_name; - int32_t _fake_pin_id = -1; - }; -#endif - -#if 1 // 函数定义 - auto initTimingEngine = [](std::string workspace) { - ista::TimingEngine* timing_engine = ista::TimingEngine::getOrCreateTimingEngine(); - if (!timing_engine->isBuildGraph()) { - timing_engine->set_design_work_space(workspace.c_str()); - timing_engine->readLiberty(dmInst->get_config().get_lib_paths()); - auto db_adapter = std::make_unique(timing_engine->get_ista()); - db_adapter->set_idb(dmInst->get_idb_builder()); - db_adapter->convertDBToTimingNetlist(); - timing_engine->set_db_adapter(std::move(db_adapter)); - timing_engine->readSdc(dmInst->get_config().get_sdc_path().c_str()); - timing_engine->buildGraph(); - } - timing_engine->initRcTree(); - return timing_engine; - }; - auto getRCSegmentList - = [](std::map, CmpLayerCoordByXASC>& coord_real_pin_map, std::vector>& routing_segment_list) { - // 预处理 对名字去重 - for (auto& [coord, real_pin_list] : coord_real_pin_map) { - std::ranges::sort(real_pin_list); - real_pin_list.erase(std::ranges::unique(real_pin_list).begin(), real_pin_list.end()); - } - // 构建coord_fake_pin_map - std::map coord_fake_pin_map; - { - int32_t fake_id = 0; - for (Segment& routing_segment : routing_segment_list) { - LayerCoord& first_coord = routing_segment.get_first(); - LayerCoord& second_coord = routing_segment.get_second(); - - if (!RTUTIL.exist(coord_real_pin_map, first_coord) && !RTUTIL.exist(coord_fake_pin_map, first_coord)) { - coord_fake_pin_map[first_coord] = fake_id++; - } - if (!RTUTIL.exist(coord_real_pin_map, second_coord) && !RTUTIL.exist(coord_fake_pin_map, second_coord)) { - coord_fake_pin_map[second_coord] = fake_id++; - } - } - } - std::vector> rc_segment_list; - { - // 生成线长为0的线段 - for (auto& [coord, real_pin_list] : coord_real_pin_map) { - for (size_t i = 1; i < real_pin_list.size(); i++) { - RCPin first_rc_pin(coord, true, RTUTIL.escapeBackslash(real_pin_list[i - 1])); - RCPin second_rc_pin(coord, true, RTUTIL.escapeBackslash(real_pin_list[i])); - rc_segment_list.emplace_back(first_rc_pin, second_rc_pin); - } - } - // 生成线长大于0的线段 - for (Segment& routing_segment : routing_segment_list) { - auto getRCPin = [&](LayerCoord& coord) { - RCPin rc_pin; - if (RTUTIL.exist(coord_real_pin_map, coord)) { - rc_pin = RCPin(coord, true, RTUTIL.escapeBackslash(coord_real_pin_map[coord].front())); - } else if (RTUTIL.exist(coord_fake_pin_map, coord)) { - rc_pin = RCPin(coord, false, coord_fake_pin_map[coord]); - } else { - RTLOG.error(Loc::current(), "The coord is not exist!"); - } - return rc_pin; - }; - rc_segment_list.emplace_back(getRCPin(routing_segment.get_first()), getRCPin(routing_segment.get_second())); - } - } - return rc_segment_list; - }; - auto getRctNode = [](ista::TimingEngine* timing_engine, ista::Netlist* sta_net_list, ista::Net* ista_net, RCPin& rc_pin) { - ista::RctNode* rct_node = nullptr; - if (rc_pin._is_real_pin) { - ista::DesignObject* pin_port = nullptr; - auto pin_port_list = sta_net_list->findPin(rc_pin._pin_name.c_str(), false, false); - if (!pin_port_list.empty()) { - pin_port = pin_port_list.front(); - } else { - pin_port = sta_net_list->findPort(rc_pin._pin_name.c_str()); - } - rct_node = timing_engine->makeOrFindRCTreeNode(pin_port); - } else { - rct_node = timing_engine->makeOrFindRCTreeNode(ista_net, rc_pin._fake_pin_id); - } - return rct_node; - }; -#endif - -#if 1 // 预处理流程 - // 每个pin只留一个连通的坐标 - for (size_t i = 0; i < real_pin_coord_map_list.size(); i++) { - std::vector>& routing_segment_list = routing_segment_list_list[i]; - for (auto& [pin_name, coord_list] : real_pin_coord_map_list[i]) { - if (coord_list.size() < 2) { - continue; - } - if (routing_segment_list.empty()) { - coord_list.erase(coord_list.begin() + 1, coord_list.end()); - } else { - for (LayerCoord& coord : coord_list) { - bool is_exist = false; - for (Segment& routing_segment : routing_segment_list) { - if (coord == routing_segment.get_first() || coord == routing_segment.get_second()) { - is_exist = true; - break; - } - } - if (is_exist) { - coord_list[0] = coord; - coord_list.erase(coord_list.begin() + 1, coord_list.end()); - break; - } - } - } - if (coord_list.size() > 2) { - RTLOG.error(Loc::current(), "The pin ", pin_name, " is not in segment_list"); - } - } - } - // coord_real_pin_map_list - std::vector, CmpLayerCoordByXASC>> coord_real_pin_map_list; - coord_real_pin_map_list.resize(real_pin_coord_map_list.size()); - for (size_t i = 0; i < real_pin_coord_map_list.size(); i++) { - for (auto& [real_pin, coord_list] : real_pin_coord_map_list[i]) { - for (LayerCoord& coord : coord_list) { - coord_real_pin_map_list[i][coord].push_back(real_pin); - } - } - } -#endif - -#if 1 // 主流程 - std::vector& net_list = RTDM.getDatabase().get_net_list(); - std::string& temp_directory_path = RTDM.getConfig().temp_directory_path; - - ista::TimingEngine* timing_engine = initTimingEngine(RTUTIL.getString(temp_directory_path, "other_tools/ista/")); - ista::Netlist* sta_net_list = timing_engine->get_netlist(); - - for (size_t net_idx = 0; net_idx < coord_real_pin_map_list.size(); net_idx++) { - ista::Net* ista_net = sta_net_list->findNet(RTUTIL.escapeBackslash(net_list[net_idx].get_net_name()).c_str()); - timing_engine->resetRcTree(ista_net); - for (Segment& segment : getRCSegmentList(coord_real_pin_map_list[net_idx], routing_segment_list_list[net_idx])) { - RCPin& first_rc_pin = segment.get_first(); - RCPin& second_rc_pin = segment.get_second(); - - double cap = 0; - double res = 0; - if (first_rc_pin._coord.get_layer_idx() == second_rc_pin._coord.get_layer_idx()) { - int32_t distance = RTUTIL.getManhattanDistance(first_rc_pin._coord, second_rc_pin._coord); - int32_t unit = dmInst->get_idb_def_service()->get_design()->get_units()->get_micron_dbu(); - std::optional width = std::nullopt; - cap = dynamic_cast(timing_engine->get_db_adapter()) - ->getCapacitance(first_rc_pin._coord.get_layer_idx() + 1, distance / 1.0 / unit, width); - res = dynamic_cast(timing_engine->get_db_adapter()) - ->getResistance(first_rc_pin._coord.get_layer_idx() + 1, distance / 1.0 / unit, width); - } - - ista::RctNode* first_node = getRctNode(timing_engine, sta_net_list, ista_net, first_rc_pin); - ista::RctNode* second_node = getRctNode(timing_engine, sta_net_list, ista_net, second_rc_pin); - timing_engine->makeResistor(ista_net, first_node, second_node, res); - timing_engine->incrCap(first_node, cap / 2, true); - timing_engine->incrCap(second_node, cap / 2, true); - } - timing_engine->updateRCTreeInfo(ista_net); - // auto* rc_tree = timing_engine->get_ista()->getRcNet(ista_net)->rct(); - // rc_tree->printGraphViz(); - // int32_t a = 0; - // dot -Tpdf tree.dot -o tree.pdf - } - timing_engine->updateTiming(); - timing_engine->reportTiming(); - - auto clk_list = timing_engine->getClockList(); - std::ranges::for_each(clk_list, [&](ista::StaClock* clk) { - auto clk_name = clk->get_clock_name(); - auto setup_tns = timing_engine->getTNS(clk_name, AnalysisMode::kMax); - auto setup_wns = timing_engine->getWNS(clk_name, AnalysisMode::kMax); - auto suggest_freq = 1000.0 / (clk->getPeriodNs() - setup_wns); - clock_timing[clk_name]["TNS"] = setup_tns; - clock_timing[clk_name]["WNS"] = setup_wns; - clock_timing[clk_name]["Freq(MHz)"] = suggest_freq; - }); -#endif -#endif -} - -#endif - #endif // private diff --git a/src/operation/iRT/interface/RTInterface.hpp b/src/operation/iRT/interface/RTInterface.hpp index f73f7853e5..84749c2c0f 100644 --- a/src/operation/iRT/interface/RTInterface.hpp +++ b/src/operation/iRT/interface/RTInterface.hpp @@ -146,12 +146,6 @@ class RTInterface ids::Shape getIDSShape(int32_t net_idx, LayerRect layer_rect, bool is_routing); #endif -#if 1 // iSTA - void updateTiming(std::vector>>& real_pin_coord_map_list, - std::vector>>& routing_segment_list_list, - std::map>& clock_timing); -#endif - #endif private: diff --git a/src/operation/iRT/source/data_manager/DataManager.cpp b/src/operation/iRT/source/data_manager/DataManager.cpp index c8bedf425f..40fa463f12 100644 --- a/src/operation/iRT/source/data_manager/DataManager.cpp +++ b/src/operation/iRT/source/data_manager/DataManager.cpp @@ -1309,8 +1309,6 @@ void DataManager::printConfig() RTLOG.info(Loc::current(), RTUTIL.getSpaceByTabNum(2), _config.top_routing_layer); RTLOG.info(Loc::current(), RTUTIL.getSpaceByTabNum(1), "output_inter_result"); RTLOG.info(Loc::current(), RTUTIL.getSpaceByTabNum(2), _config.output_inter_result); - RTLOG.info(Loc::current(), RTUTIL.getSpaceByTabNum(1), "enable_timing"); - RTLOG.info(Loc::current(), RTUTIL.getSpaceByTabNum(2), _config.enable_timing); // ********** RT ********** // RTLOG.info(Loc::current(), RTUTIL.getSpaceByTabNum(0), "RT_CONFIG_BUILD"); RTLOG.info(Loc::current(), RTUTIL.getSpaceByTabNum(1), "log_file_path"); diff --git a/src/operation/iRT/source/data_manager/advance/Config.hpp b/src/operation/iRT/source/data_manager/advance/Config.hpp index e79f245588..8a95abd5a7 100644 --- a/src/operation/iRT/source/data_manager/advance/Config.hpp +++ b/src/operation/iRT/source/data_manager/advance/Config.hpp @@ -32,7 +32,6 @@ class Config std::string bottom_routing_layer; // optional std::string top_routing_layer; // optional int32_t output_inter_result; // optional - int32_t enable_timing; // optional ///////////////////////////////////////////// // ********** RT ********** // std::string log_file_path; // building diff --git a/src/operation/iRT/source/data_manager/advance/Summary.hpp b/src/operation/iRT/source/data_manager/advance/Summary.hpp index 6a5a82126f..53f9d0efc6 100644 --- a/src/operation/iRT/source/data_manager/advance/Summary.hpp +++ b/src/operation/iRT/source/data_manager/advance/Summary.hpp @@ -52,7 +52,6 @@ class PRSummary double total_demand = 0; double total_overflow = 0; double total_wire_length = 0; - std::map> clock_timing_map; }; class LASummary @@ -68,7 +67,6 @@ class LASummary double total_wire_length = 0; std::map cut_via_num_map; int32_t total_via_num = 0; - std::map> clock_timing_map; }; class SRSummary @@ -84,7 +82,6 @@ class SRSummary double total_wire_length = 0; std::map cut_via_num_map; int32_t total_via_num = 0; - std::map> clock_timing_map; }; class TASummary @@ -111,7 +108,6 @@ class DRSummary int32_t total_patch_num = 0; std::map routing_violation_num_map; int32_t total_violation_num = 0; - std::map> clock_timing_map; }; class VRSummary @@ -133,7 +129,6 @@ class VRSummary std::map among_net_violation_type_num_map; std::map among_net_routing_violation_num_map; int32_t among_net_total_violation_num = 0; - std::map> clock_timing_map; }; class Summary diff --git a/src/operation/iRT/source/module/detailed_router/DetailedRouter.cpp b/src/operation/iRT/source/module/detailed_router/DetailedRouter.cpp index bd14342b56..e6cb03d5db 100644 --- a/src/operation/iRT/source/module/detailed_router/DetailedRouter.cpp +++ b/src/operation/iRT/source/module/detailed_router/DetailedRouter.cpp @@ -4253,7 +4253,6 @@ void DetailedRouter::updateSummary(DRModel& dr_model) int32_t micron_dbu = RTDM.getDatabase().get_micron_dbu(); std::vector>& layer_via_master_list = RTDM.getDatabase().get_layer_via_master_list(); Summary& summary = RTDM.getDatabase().get_summary(); - int32_t enable_timing = RTDM.getConfig().enable_timing; std::map& routing_wire_length_map = summary.iter_dr_summary_map[dr_model.get_iter()].routing_wire_length_map; double& total_wire_length = summary.iter_dr_summary_map[dr_model.get_iter()].total_wire_length; @@ -4263,9 +4262,6 @@ void DetailedRouter::updateSummary(DRModel& dr_model) int32_t& total_patch_num = summary.iter_dr_summary_map[dr_model.get_iter()].total_patch_num; std::map& routing_violation_num_map = summary.iter_dr_summary_map[dr_model.get_iter()].routing_violation_num_map; int32_t& total_violation_num = summary.iter_dr_summary_map[dr_model.get_iter()].total_violation_num; - std::map>& clock_timing_map = summary.iter_dr_summary_map[dr_model.get_iter()].clock_timing_map; - - std::vector& dr_net_list = dr_model.get_dr_net_list(); routing_wire_length_map.clear(); total_wire_length = 0; @@ -4275,7 +4271,6 @@ void DetailedRouter::updateSummary(DRModel& dr_model) total_patch_num = 0; routing_violation_num_map.clear(); total_violation_num = 0; - clock_timing_map.clear(); for (auto& [net_idx, segment_list] : dr_model.get_curr_result().get_net_detailed_result_map()) { for (Segment& segment : segment_list) { @@ -4307,23 +4302,6 @@ void DetailedRouter::updateSummary(DRModel& dr_model) routing_violation_num_map[violation.get_violation_shape().get_layer_idx()]++; total_violation_num++; } - if (enable_timing) { - std::vector>> real_pin_coord_map_list; - real_pin_coord_map_list.resize(dr_net_list.size()); - std::vector>> routing_segment_list_list; - routing_segment_list_list.resize(dr_net_list.size()); - for (DRNet& dr_net : dr_net_list) { - for (DRPin& dr_pin : dr_net.get_dr_pin_list()) { - real_pin_coord_map_list[dr_net.get_net_idx()][dr_pin.get_pin_name()].push_back(dr_pin.get_access_point().getRealLayerCoord()); - } - } - for (auto& [net_idx, segment_list] : dr_model.get_curr_result().get_net_detailed_result_map()) { - for (Segment& segment : segment_list) { - routing_segment_list_list[net_idx].emplace_back(segment.get_first(), segment.get_second()); - } - } - RTI.updateTiming(real_pin_coord_map_list, routing_segment_list_list, clock_timing_map); - } } void DetailedRouter::printSummary(DRModel& dr_model) @@ -4331,7 +4309,6 @@ void DetailedRouter::printSummary(DRModel& dr_model) std::vector& routing_layer_list = RTDM.getDatabase().get_routing_layer_list(); std::vector& cut_layer_list = RTDM.getDatabase().get_cut_layer_list(); Summary& summary = RTDM.getDatabase().get_summary(); - int32_t enable_timing = RTDM.getConfig().enable_timing; std::map& routing_wire_length_map = summary.iter_dr_summary_map[dr_model.get_iter()].routing_wire_length_map; double& total_wire_length = summary.iter_dr_summary_map[dr_model.get_iter()].total_wire_length; @@ -4341,7 +4318,6 @@ void DetailedRouter::printSummary(DRModel& dr_model) int32_t& total_patch_num = summary.iter_dr_summary_map[dr_model.get_iter()].total_patch_num; std::map& routing_violation_num_map = summary.iter_dr_summary_map[dr_model.get_iter()].routing_violation_num_map; int32_t& total_violation_num = summary.iter_dr_summary_map[dr_model.get_iter()].total_violation_num; - std::map>& clock_timing_map = summary.iter_dr_summary_map[dr_model.get_iter()].clock_timing_map; fort::char_table routing_wire_length_map_table; { @@ -4392,20 +4368,8 @@ void DetailedRouter::printSummary(DRModel& dr_model) routing_violation_num_map_table << fort::header << "Total" << total_violation_num << RTUTIL.getPercentage(total_violation_num, total_violation_num) << fort::endr; } - fort::char_table timing_table; - timing_table.set_cell_text_align(fort::text_align::right); - if (enable_timing) { - timing_table << fort::header << "clock_name" - << "tns" - << "wns" - << "freq" << fort::endr; - for (auto& [clock_name, timing_map] : clock_timing_map) { - timing_table << clock_name << timing_map["TNS"] << timing_map["WNS"] << timing_map["Freq(MHz)"] << fort::endr; - } - } RTUTIL.printTableList({routing_wire_length_map_table, cut_via_num_map_table, routing_patch_num_map_table}); RTUTIL.printTableList({routing_violation_num_map_table}); - RTUTIL.printTableList({timing_table}); } void DetailedRouter::outputNetCSV(DRModel& dr_model) diff --git a/src/operation/iRT/source/module/layer_assigner/LayerAssigner.cpp b/src/operation/iRT/source/module/layer_assigner/LayerAssigner.cpp index 2bb4f296db..e381ea013b 100644 --- a/src/operation/iRT/source/module/layer_assigner/LayerAssigner.cpp +++ b/src/operation/iRT/source/module/layer_assigner/LayerAssigner.cpp @@ -806,11 +806,9 @@ void LayerAssigner::updateRoutingTreeToGraph(LAModel& la_model, const RoutingSeg void LayerAssigner::updateSummary(LAModel& la_model) { int32_t micron_dbu = RTDM.getDatabase().get_micron_dbu(); - ScaleAxis& gcell_axis = RTDM.getDatabase().get_gcell_axis(); GridMap& gcell_map = RTDM.getDatabase().get_gcell_map(); std::vector>& layer_via_master_list = RTDM.getDatabase().get_layer_via_master_list(); Summary& summary = RTDM.getDatabase().get_summary(); - int32_t enable_timing = RTDM.getConfig().enable_timing; std::map& routing_demand_map = summary.la_summary.routing_demand_map; double& total_demand = summary.la_summary.total_demand; @@ -820,9 +818,6 @@ void LayerAssigner::updateSummary(LAModel& la_model) double& total_wire_length = summary.la_summary.total_wire_length; std::map& cut_via_num_map = summary.la_summary.cut_via_num_map; int32_t& total_via_num = summary.la_summary.total_via_num; - std::map>& clock_timing_map = summary.la_summary.clock_timing_map; - - std::vector& la_net_list = la_model.get_la_net_list(); routing_demand_map.clear(); total_demand = 0; @@ -832,7 +827,6 @@ void LayerAssigner::updateSummary(LAModel& la_model) total_wire_length = 0; cut_via_num_map.clear(); total_via_num = 0; - clock_timing_map.clear(); std::vector>& routing_h_edge_map = RTDM.getDatabase().get_routing_h_edge_map(); std::vector>& routing_v_edge_map = RTDM.getDatabase().get_routing_v_edge_map(); @@ -877,31 +871,6 @@ void LayerAssigner::updateSummary(LAModel& la_model) } } } - if (enable_timing) { - std::vector>> real_pin_coord_map_list; - real_pin_coord_map_list.resize(la_net_list.size()); - std::vector>> routing_segment_list_list; - routing_segment_list_list.resize(la_net_list.size()); - for (LANet& la_net : la_net_list) { - for (LAPin& la_pin : la_net.get_la_pin_list()) { - LayerCoord layer_coord = la_pin.get_access_point().getGridLayerCoord(); - real_pin_coord_map_list[la_net.get_net_idx()][la_pin.get_pin_name()].emplace_back(RTUTIL.getRealRectByGCell(layer_coord, gcell_axis).getMidPoint(), - layer_coord.get_layer_idx()); - } - } - for (auto& [net_idx, segment_set] : la_model.get_net_global_result_map()) { - for (Segment& segment_value : segment_set) { - Segment* segment = &segment_value; - LayerCoord first_layer_coord = segment->get_first(); - LayerCoord first_real_coord(RTUTIL.getRealRectByGCell(first_layer_coord, gcell_axis).getMidPoint(), first_layer_coord.get_layer_idx()); - LayerCoord second_layer_coord = segment->get_second(); - LayerCoord second_real_coord(RTUTIL.getRealRectByGCell(second_layer_coord, gcell_axis).getMidPoint(), second_layer_coord.get_layer_idx()); - - routing_segment_list_list[net_idx].emplace_back(first_real_coord, second_real_coord); - } - } - RTI.updateTiming(real_pin_coord_map_list, routing_segment_list_list, clock_timing_map); - } } void LayerAssigner::printSummary(LAModel& la_model) @@ -909,7 +878,6 @@ void LayerAssigner::printSummary(LAModel& la_model) std::vector& routing_layer_list = RTDM.getDatabase().get_routing_layer_list(); std::vector& cut_layer_list = RTDM.getDatabase().get_cut_layer_list(); Summary& summary = RTDM.getDatabase().get_summary(); - int32_t enable_timing = RTDM.getConfig().enable_timing; std::map& routing_demand_map = summary.la_summary.routing_demand_map; double& total_demand = summary.la_summary.total_demand; @@ -919,7 +887,6 @@ void LayerAssigner::printSummary(LAModel& la_model) double& total_wire_length = summary.la_summary.total_wire_length; std::map& cut_via_num_map = summary.la_summary.cut_via_num_map; int32_t& total_via_num = summary.la_summary.total_via_num; - std::map>& clock_timing_map = summary.la_summary.clock_timing_map; fort::char_table routing_demand_map_table; { @@ -969,19 +936,7 @@ void LayerAssigner::printSummary(LAModel& la_model) } cut_via_num_map_table << fort::header << "Total" << total_via_num << RTUTIL.getPercentage(total_via_num, total_via_num) << fort::endr; } - fort::char_table timing_table; - timing_table.set_cell_text_align(fort::text_align::right); - if (enable_timing) { - timing_table << fort::header << "clock_name" - << "tns" - << "wns" - << "freq" << fort::endr; - for (auto& [clock_name, timing_map] : clock_timing_map) { - timing_table << clock_name << timing_map["TNS"] << timing_map["WNS"] << timing_map["Freq(MHz)"] << fort::endr; - } - } RTUTIL.printTableList({routing_demand_map_table, routing_overflow_map_table, routing_wire_length_map_table, cut_via_num_map_table}); - RTUTIL.printTableList({timing_table}); } void LayerAssigner::outputGuide(LAModel& la_model) diff --git a/src/operation/iRT/source/module/planar_router/PlanarRouter.cpp b/src/operation/iRT/source/module/planar_router/PlanarRouter.cpp index 406ce71faa..7f93f2566c 100644 --- a/src/operation/iRT/source/module/planar_router/PlanarRouter.cpp +++ b/src/operation/iRT/source/module/planar_router/PlanarRouter.cpp @@ -1437,22 +1437,16 @@ void PlanarRouter::uploadNetList(PRModel& pr_model, const std::vector& p void PlanarRouter::updateSummary(PRModel& pr_model) { int32_t micron_dbu = RTDM.getDatabase().get_micron_dbu(); - ScaleAxis& gcell_axis = RTDM.getDatabase().get_gcell_axis(); GridMap& gcell_map = RTDM.getDatabase().get_gcell_map(); Summary& summary = RTDM.getDatabase().get_summary(); - int32_t enable_timing = RTDM.getConfig().enable_timing; double& total_demand = summary.pr_summary.total_demand; double& total_overflow = summary.pr_summary.total_overflow; double& total_wire_length = summary.pr_summary.total_wire_length; - std::map>& clock_timing_map = summary.pr_summary.clock_timing_map; - - std::vector& pr_net_list = pr_model.get_pr_net_list(); total_demand = 0; total_overflow = 0; total_wire_length = 0; - clock_timing_map.clear(); for (GridMap* routing_edge_map : {&RTDM.getDatabase().get_planar_routing_h_edge_map(), &RTDM.getDatabase().get_planar_routing_v_edge_map()}) { for (int32_t x = 0; x < routing_edge_map->get_x_size(); x++) { @@ -1481,41 +1475,15 @@ void PlanarRouter::updateSummary(PRModel& pr_model) } } } - if (enable_timing) { - std::vector>> real_pin_coord_map_list; - real_pin_coord_map_list.resize(pr_net_list.size()); - std::vector>> routing_segment_list_list; - routing_segment_list_list.resize(pr_net_list.size()); - for (PRNet& pr_net : pr_net_list) { - for (PRPin& pr_pin : pr_net.get_pr_pin_list()) { - LayerCoord layer_coord = pr_pin.get_access_point().getGridLayerCoord(); - real_pin_coord_map_list[pr_net.get_net_idx()][pr_pin.get_pin_name()].emplace_back(RTUTIL.getRealRectByGCell(layer_coord, gcell_axis).getMidPoint(), 0); - } - } - for (auto& [net_idx, segment_set] : pr_model.get_net_global_result_map()) { - for (Segment& segment_value : segment_set) { - Segment* segment = &segment_value; - LayerCoord first_layer_coord = segment->get_first(); - LayerCoord first_real_coord(RTUTIL.getRealRectByGCell(first_layer_coord, gcell_axis).getMidPoint(), first_layer_coord.get_layer_idx()); - LayerCoord second_layer_coord = segment->get_second(); - LayerCoord second_real_coord(RTUTIL.getRealRectByGCell(second_layer_coord, gcell_axis).getMidPoint(), second_layer_coord.get_layer_idx()); - - routing_segment_list_list[net_idx].emplace_back(first_real_coord, second_real_coord); - } - } - RTI.updateTiming(real_pin_coord_map_list, routing_segment_list_list, clock_timing_map); - } } void PlanarRouter::printSummary(PRModel& pr_model) { Summary& summary = RTDM.getDatabase().get_summary(); - int32_t enable_timing = RTDM.getConfig().enable_timing; double& total_demand = summary.pr_summary.total_demand; double& total_overflow = summary.pr_summary.total_overflow; double& total_wire_length = summary.pr_summary.total_wire_length; - std::map>& clock_timing_map = summary.pr_summary.clock_timing_map; fort::char_table summary_table; { @@ -1524,19 +1492,7 @@ void PlanarRouter::printSummary(PRModel& pr_model) summary_table << fort::header << "total_overflow" << total_overflow << fort::endr; summary_table << fort::header << "total_wire_length" << total_wire_length << fort::endr; } - fort::char_table timing_table; - timing_table.set_cell_text_align(fort::text_align::right); - if (enable_timing) { - timing_table << fort::header << "clock_name" - << "tns" - << "wns" - << "freq" << fort::endr; - for (auto& [clock_name, timing_map] : clock_timing_map) { - timing_table << clock_name << timing_map["TNS"] << timing_map["WNS"] << timing_map["Freq(MHz)"] << fort::endr; - } - } RTUTIL.printTableList({summary_table}); - RTUTIL.printTableList({timing_table}); } void PlanarRouter::outputGuide(PRModel& pr_model) diff --git a/src/operation/iRT/source/module/violation_reporter/ViolationReporter.cpp b/src/operation/iRT/source/module/violation_reporter/ViolationReporter.cpp index f274a9e58e..0a13322491 100644 --- a/src/operation/iRT/source/module/violation_reporter/ViolationReporter.cpp +++ b/src/operation/iRT/source/module/violation_reporter/ViolationReporter.cpp @@ -175,7 +175,6 @@ void ViolationReporter::updateSummary(VRModel& vr_model) Die& die = RTDM.getDatabase().get_die(); std::vector>& layer_via_master_list = RTDM.getDatabase().get_layer_via_master_list(); Summary& summary = RTDM.getDatabase().get_summary(); - int32_t enable_timing = RTDM.getConfig().enable_timing; std::map& routing_wire_length_map = summary.vr_summary.routing_wire_length_map; double& total_wire_length = summary.vr_summary.total_wire_length; @@ -191,9 +190,6 @@ void ViolationReporter::updateSummary(VRModel& vr_model) std::map& among_net_violation_type_num_map = summary.vr_summary.among_net_violation_type_num_map; std::map& among_net_routing_violation_num_map = summary.vr_summary.among_net_routing_violation_num_map; int32_t& among_net_total_violation_num = summary.vr_summary.among_net_total_violation_num; - std::map>& clock_timing_map = summary.vr_summary.clock_timing_map; - - std::vector& vr_net_list = vr_model.get_vr_net_list(); routing_wire_length_map.clear(); total_wire_length = 0; @@ -209,7 +205,6 @@ void ViolationReporter::updateSummary(VRModel& vr_model) among_net_violation_type_num_map.clear(); among_net_routing_violation_num_map.clear(); among_net_total_violation_num = 0; - clock_timing_map.clear(); for (auto& [net_idx, segment_set] : RTDM.getNetDetailedResultMap(die)) { for (Segment* segment : segment_set) { @@ -255,23 +250,6 @@ void ViolationReporter::updateSummary(VRModel& vr_model) among_net_routing_violation_num_map[violation.get_violation_shape().get_layer_idx()]++; among_net_total_violation_num++; } - if (enable_timing) { - std::vector>> real_pin_coord_map_list; - real_pin_coord_map_list.resize(vr_net_list.size()); - std::vector>> routing_segment_list_list; - routing_segment_list_list.resize(vr_net_list.size()); - for (VRNet& vr_net : vr_net_list) { - for (VRPin& vr_pin : vr_net.get_vr_pin_list()) { - real_pin_coord_map_list[vr_net.get_net_idx()][vr_pin.get_pin_name()].push_back(vr_pin.get_access_point().getRealLayerCoord()); - } - } - for (auto& [net_idx, segment_set] : RTDM.getNetDetailedResultMap(die)) { - for (Segment* segment : segment_set) { - routing_segment_list_list[net_idx].emplace_back(segment->get_first(), segment->get_second()); - } - } - RTI.updateTiming(real_pin_coord_map_list, routing_segment_list_list, clock_timing_map); - } } void ViolationReporter::printSummary(VRModel& vr_model) @@ -279,7 +257,6 @@ void ViolationReporter::printSummary(VRModel& vr_model) std::vector& routing_layer_list = RTDM.getDatabase().get_routing_layer_list(); std::vector& cut_layer_list = RTDM.getDatabase().get_cut_layer_list(); Summary& summary = RTDM.getDatabase().get_summary(); - int32_t enable_timing = RTDM.getConfig().enable_timing; std::map& routing_wire_length_map = summary.vr_summary.routing_wire_length_map; double& total_wire_length = summary.vr_summary.total_wire_length; @@ -295,7 +272,6 @@ void ViolationReporter::printSummary(VRModel& vr_model) std::map& among_net_violation_type_num_map = summary.vr_summary.among_net_violation_type_num_map; std::map& among_net_routing_violation_num_map = summary.vr_summary.among_net_routing_violation_num_map; int32_t& among_net_total_violation_num = summary.vr_summary.among_net_total_violation_num; - std::map>& clock_timing_map = summary.vr_summary.clock_timing_map; fort::char_table routing_wire_length_map_table; { @@ -385,21 +361,9 @@ void ViolationReporter::printSummary(VRModel& vr_model) } among_net_routing_violation_map_table << fort::header << among_net_total_violation_num << fort::endr; } - fort::char_table timing_table; - timing_table.set_cell_text_align(fort::text_align::right); - if (enable_timing) { - timing_table << fort::header << "clock_name" - << "tns" - << "wns" - << "freq" << fort::endr; - for (auto& [clock_name, timing_map] : clock_timing_map) { - timing_table << clock_name << timing_map["TNS"] << timing_map["WNS"] << timing_map["Freq(MHz)"] << fort::endr; - } - } RTUTIL.printTableList({routing_wire_length_map_table, cut_via_num_map_table, routing_patch_num_map_table}); RTUTIL.printTableList({within_net_routing_violation_map_table}); RTUTIL.printTableList({among_net_routing_violation_map_table}); - RTUTIL.printTableList({timing_table}); } void ViolationReporter::outputNetCSV(VRModel& vr_model) diff --git a/test/fixtures/gcd/config/route_ecc.json b/test/fixtures/gcd/config/route_ecc.json index 4d93889b09..51daf88c4b 100644 --- a/test/fixtures/gcd/config/route_ecc.json +++ b/test/fixtures/gcd/config/route_ecc.json @@ -4,8 +4,7 @@ "-bottom_routing_layer": "MET2", "-top_routing_layer": "MET5", "-thread_number": "50", - "-enable_timing": "0", "-output_csv": "0", "-output_inter_result": "0" } -} \ No newline at end of file +} From f4e90f67b14cc17c21c0872ae5a39b601b595b87 Mon Sep 17 00:00:00 2001 From: ZhishengZeng Date: Tue, 15 Sep 2026 11:06:40 +0800 Subject: [PATCH 2/4] refactor(py_irt): align commands and flags with Tcl --- src/interface/python/py_irt/py_irt.cpp | 38 +++-- src/interface/python/py_irt/py_irt.h | 4 +- src/interface/python/py_irt/py_irt_utils.cpp | 141 ++++++++---------- src/interface/python/py_irt/py_register_irt.h | 5 +- test/fixtures/gcd/config/route_ecc.json | 1 - 5 files changed, 89 insertions(+), 100 deletions(-) diff --git a/src/interface/python/py_irt/py_irt.cpp b/src/interface/python/py_irt/py_irt.cpp index 6d8955d968..b41bae7bc5 100644 --- a/src/interface/python/py_irt/py_irt.cpp +++ b/src/interface/python/py_irt/py_irt.cpp @@ -16,18 +16,27 @@ // *************************************************************************************** #include "py_irt.h" -#include - #include #include "RTInterface.hpp" + namespace python_interface { -bool initConfigMapByJSON(const std::string& config, std::map& config_map); +bool initRTConfigMapByJSON(const std::string& config, std::map& config_map); +void initRTConfigMapByDict(std::map& config_dict, std::map& config_map); +bool initERTConfigMapByJSON(const std::string& config, std::map& config_map); +void initERTConfigMapByDict(std::map& config_dict, std::map& config_map); -bool destroyRT() +bool initRT(std::string& config, std::map& config_dict) { - RTI.destroyRT(); + std::map config_map; + + bool pass = config.empty() ? true : initRTConfigMapByJSON(config, config_map); + if (!pass) { + return false; + } + initRTConfigMapByDict(config_dict, config_map); + RTI.initRT(config_map); return true; } @@ -35,11 +44,11 @@ bool runERT(std::string& config, std::map& config_dict { std::map config_map; - bool pass = false; - pass = !pass ? initConfigMapByJSON(config, config_map) : pass; + bool pass = config.empty() ? true : initERTConfigMapByJSON(config, config_map); if (!pass) { return false; } + initERTConfigMapByDict(config_dict, config_map); RTI.runERT(config_map); return true; } @@ -50,16 +59,15 @@ bool runRT() return true; } -bool initRT(std::string& config, std::map& config_dict) +bool destroyRT() { - std::map config_map; + RTI.destroyRT(); + return true; +} - bool pass = false; - pass = !pass ? initConfigMapByJSON(config, config_map) : pass; - if (!pass) { - return false; - } - RTI.initRT(config_map); +bool cleanDef() +{ + RTI.cleanDef(); return true; } diff --git a/src/interface/python/py_irt/py_irt.h b/src/interface/python/py_irt/py_irt.h index fb74fff1f6..b98377bde4 100644 --- a/src/interface/python/py_irt/py_irt.h +++ b/src/interface/python/py_irt/py_irt.h @@ -20,10 +20,10 @@ namespace python_interface { -bool destroyRT(); bool initRT(std::string& config, std::map& config_dict); -bool runDR(); bool runERT(std::string& config, std::map& config_dict); bool runRT(); +bool destroyRT(); +bool cleanDef(); } // namespace python_interface diff --git a/src/interface/python/py_irt/py_irt_utils.cpp b/src/interface/python/py_irt/py_irt_utils.cpp index 86e52cb659..37dfabb267 100644 --- a/src/interface/python/py_irt/py_irt_utils.cpp +++ b/src/interface/python/py_irt/py_irt_utils.cpp @@ -14,82 +14,64 @@ // // See the Mulan PSL v2 for more details. // *************************************************************************************** -#include - #include -#include "RTInterface.hpp" #include "json_parser.h" #include "py_irt.h" namespace python_interface { -using tcl::ValueType; - -std::map strToDoubleMap(const std::string& input) -{ - // Trim the leading and trailing whitespaces from the input - std::string input_trimmed = input; - input_trimmed.erase(input_trimmed.begin(), - std::find_if(input_trimmed.begin(), input_trimmed.end(), [](int ch) { return !std::isspace(ch); })); - input_trimmed.erase(std::find_if(input_trimmed.rbegin(), input_trimmed.rend(), [](int ch) { return !std::isspace(ch); }).base(), - input_trimmed.end()); - std::map result; - std::stringstream ss(input_trimmed.substr(1, input_trimmed.length() - 2)); - std::string item; - while (std::getline(ss, item, ',')) { - size_t pos = item.find(":"); - std::string key = item.substr(0, pos); - // Trim whitespaces from the key and value - key.erase(std::remove_if(key.begin(), key.end(), [](unsigned char c) { return std::isspace(c); }), key.end()); - std::string value_str = item.substr(pos + 1); - value_str.erase(std::remove_if(value_str.begin(), value_str.end(), [](unsigned char c) { return std::isspace(c); }), value_str.end()); - double value = std::stod(value_str); - result[key] = value; - } - return result; -} - -std::vector strToVector(const std::string& input) +bool initRTConfigMapByJSON(const std::string& config, std::map& config_map) { - std::vector result; - std::string token; - for (char c : input) { - switch (c) { - case ' ': - case ',': { - if (!token.empty()) { - result.push_back(token); - token.clear(); - } - break; - } - default: - token.push_back(c); - } - } - return result; -} + auto config_file = std::ifstream(config); + if (!config_file.is_open()) { + return false; + } + nlohmann::json json; + config_file >> json; + std::string value = ecc::getJsonData(json, {"RT", "-temp_directory_path"}); + if (!value.empty()) { + config_map["-temp_directory_path"] = value; + } + value = ecc::getJsonData(json, {"RT", "-bottom_routing_layer"}); + if (!value.empty()) { + config_map["-bottom_routing_layer"] = value; + } + value = ecc::getJsonData(json, {"RT", "-top_routing_layer"}); + if (!value.empty()) { + config_map["-top_routing_layer"] = value; + } + value = ecc::getJsonData(json, {"RT", "-thread_number"}); + if (!value.empty()) { + config_map["-thread_number"] = std::stoi(value); + } + value = ecc::getJsonData(json, {"RT", "-output_inter_result"}); + if (!value.empty()) { + config_map["-output_inter_result"] = std::stoi(value); + } -std::vector strToDoubleVec(const std::string& input) -{ - auto tmp = strToVector(input); - std::vector result; - result.reserve(tmp.size()); - for_each(tmp.begin(), tmp.end(), [&result](const std::string& s) { result.push_back(std::stod(s)); }); - return result; + return true; } -std::vector strToIntVec(const std::string& input) +void initRTConfigMapByDict(std::map& config_dict, std::map& config_map) { - auto tmp = strToVector(input); - std::vector result; - result.reserve(tmp.size()); - for_each(tmp.begin(), tmp.end(), [&result](const std::string& s) { result.push_back(std::stoi(s)); }); - return result; + if (config_dict.count("-temp_directory_path") > 0 && !config_dict["-temp_directory_path"].empty()) { + config_map["-temp_directory_path"] = config_dict["-temp_directory_path"]; + } + if (config_dict.count("-bottom_routing_layer") > 0 && !config_dict["-bottom_routing_layer"].empty()) { + config_map["-bottom_routing_layer"] = config_dict["-bottom_routing_layer"]; + } + if (config_dict.count("-top_routing_layer") > 0 && !config_dict["-top_routing_layer"].empty()) { + config_map["-top_routing_layer"] = config_dict["-top_routing_layer"]; + } + if (config_dict.count("-thread_number") > 0 && !config_dict["-thread_number"].empty()) { + config_map["-thread_number"] = std::stoi(config_dict["-thread_number"]); + } + if (config_dict.count("-output_inter_result") > 0 && !config_dict["-output_inter_result"].empty()) { + config_map["-output_inter_result"] = std::stoi(config_dict["-output_inter_result"]); + } } -// 通过json文件对config进行初始化 -bool initConfigMapByJSON(const std::string& config, std::map& config_map) +bool initERTConfigMapByJSON(const std::string& config, std::map& config_map) { auto config_file = std::ifstream(config); if (!config_file.is_open()) { @@ -97,27 +79,26 @@ bool initConfigMapByJSON(const std::string& config, std::map> json; - nlohmann::json rt_json = json["RT"]; - std::string value; - value = ecc::getJsonData(json, {"RT", "-temp_directory_path"}); - config_map.insert(std::make_pair("-temp_directory_path", value)); - value = ecc::getJsonData(json, {"RT", "-bottom_routing_layer"}); - config_map.insert(std::make_pair("-bottom_routing_layer", value)); - value = ecc::getJsonData(json, {"RT", "-top_routing_layer"}); - config_map.insert(std::make_pair("-top_routing_layer", value)); - value = ecc::getJsonData(json, {"RT", "-thread_number"}); - config_map.insert(std::make_pair("-thread_number", std::stoi(value))); - value = ecc::getJsonData(json, {"RT", "-output_inter_result"}); - config_map.insert(std::make_pair("-output_inter_result", std::stoi(value))); - if (json.contains("RT") && json["RT"].contains("-enable_fast_mode")) { - value = ecc::getJsonData(json, {"RT", "-enable_fast_mode"}); - config_map.insert(std::make_pair("-enable_fast_mode", std::stoi(value))); + std::string value = ecc::getJsonData(json, {"RT", "-stage"}); + if (!value.empty()) { + config_map["-stage"] = value; } - for (nlohmann::json::iterator item = rt_json.begin(); item != rt_json.end(); ++item) { - config_map.insert(std::make_pair(item.key(), item.value())); + value = ecc::getJsonData(json, {"RT", "-resolve_congestion"}); + if (!value.empty()) { + config_map["-resolve_congestion"] = value; } return true; } +void initERTConfigMapByDict(std::map& config_dict, std::map& config_map) +{ + if (config_dict.count("-stage") > 0 && !config_dict["-stage"].empty()) { + config_map["-stage"] = config_dict["-stage"]; + } + if (config_dict.count("-resolve_congestion") > 0 && !config_dict["-resolve_congestion"].empty()) { + config_map["-resolve_congestion"] = config_dict["-resolve_congestion"]; + } +} + } // namespace python_interface diff --git a/src/interface/python/py_irt/py_register_irt.h b/src/interface/python/py_irt/py_register_irt.h index 04b3becf3f..3e42d7d483 100644 --- a/src/interface/python/py_irt/py_register_irt.h +++ b/src/interface/python/py_irt/py_register_irt.h @@ -24,9 +24,10 @@ namespace python_interface { namespace py = pybind11; void register_irt(py::module& m) { - m.def("destroy_rt", destroyRT); m.def("init_rt", initRT, py::arg("config") = "", py::arg("config_dict") = std::map{}); m.def("run_ert", runERT, py::arg("config") = "", py::arg("config_dict") = std::map{}); m.def("run_rt", runRT); + m.def("destroy_rt", destroyRT); + m.def("rt_clean_def", cleanDef); } -} // namespace python_interface \ No newline at end of file +} // namespace python_interface diff --git a/test/fixtures/gcd/config/route_ecc.json b/test/fixtures/gcd/config/route_ecc.json index 51daf88c4b..1416232123 100644 --- a/test/fixtures/gcd/config/route_ecc.json +++ b/test/fixtures/gcd/config/route_ecc.json @@ -4,7 +4,6 @@ "-bottom_routing_layer": "MET2", "-top_routing_layer": "MET5", "-thread_number": "50", - "-output_csv": "0", "-output_inter_result": "0" } } From b5e963fc643eec0f3b3a35b166870229f631fb99 Mon Sep 17 00:00:00 2001 From: ZhishengZeng Date: Tue, 15 Sep 2026 12:11:47 +0800 Subject: [PATCH 3/4] refactor(iRT): remove obsolete DEF cleanup command --- src/interface/python/py_irt/py_irt.cpp | 6 -- src/interface/python/py_irt/py_irt.h | 1 - src/interface/python/py_irt/py_register_irt.h | 1 - src/interface/tcl/tcl_irt/CMakeLists.txt | 1 - .../tcl/tcl_irt/include/tcl_register_irt.h | 2 - src/interface/tcl/tcl_irt/include/tcl_rt.h | 18 ---- .../tcl/tcl_irt/src/tcl_rt_clean_def.cpp | 38 ------- src/operation/iRT/interface/RTInterface.cpp | 98 ------------------- src/operation/iRT/interface/RTInterface.hpp | 1 - 9 files changed, 166 deletions(-) delete mode 100644 src/interface/tcl/tcl_irt/src/tcl_rt_clean_def.cpp diff --git a/src/interface/python/py_irt/py_irt.cpp b/src/interface/python/py_irt/py_irt.cpp index b41bae7bc5..ba2b1d21ac 100644 --- a/src/interface/python/py_irt/py_irt.cpp +++ b/src/interface/python/py_irt/py_irt.cpp @@ -65,10 +65,4 @@ bool destroyRT() return true; } -bool cleanDef() -{ - RTI.cleanDef(); - return true; -} - } // namespace python_interface diff --git a/src/interface/python/py_irt/py_irt.h b/src/interface/python/py_irt/py_irt.h index b98377bde4..c685084eb3 100644 --- a/src/interface/python/py_irt/py_irt.h +++ b/src/interface/python/py_irt/py_irt.h @@ -24,6 +24,5 @@ bool initRT(std::string& config, std::map& config_dict bool runERT(std::string& config, std::map& config_dict); bool runRT(); bool destroyRT(); -bool cleanDef(); } // namespace python_interface diff --git a/src/interface/python/py_irt/py_register_irt.h b/src/interface/python/py_irt/py_register_irt.h index 3e42d7d483..6369769680 100644 --- a/src/interface/python/py_irt/py_register_irt.h +++ b/src/interface/python/py_irt/py_register_irt.h @@ -28,6 +28,5 @@ void register_irt(py::module& m) m.def("run_ert", runERT, py::arg("config") = "", py::arg("config_dict") = std::map{}); m.def("run_rt", runRT); m.def("destroy_rt", destroyRT); - m.def("rt_clean_def", cleanDef); } } // namespace python_interface diff --git a/src/interface/tcl/tcl_irt/CMakeLists.txt b/src/interface/tcl/tcl_irt/CMakeLists.txt index 7ac90d0423..1550ab870e 100644 --- a/src/interface/tcl/tcl_irt/CMakeLists.txt +++ b/src/interface/tcl/tcl_irt/CMakeLists.txt @@ -3,7 +3,6 @@ add_library(tcl_irt ${HOME_INTERFACE}/tcl/tcl_irt/src/tcl_run_ert.cpp ${HOME_INTERFACE}/tcl/tcl_irt/src/tcl_run_rt.cpp ${HOME_INTERFACE}/tcl/tcl_irt/src/tcl_destroy_rt.cpp - ${HOME_INTERFACE}/tcl/tcl_irt/src/tcl_rt_clean_def.cpp ) target_link_libraries(tcl_irt diff --git a/src/interface/tcl/tcl_irt/include/tcl_register_irt.h b/src/interface/tcl/tcl_irt/include/tcl_register_irt.h index bd645bacb1..8ee421809a 100644 --- a/src/interface/tcl/tcl_irt/include/tcl_register_irt.h +++ b/src/interface/tcl/tcl_irt/include/tcl_register_irt.h @@ -29,8 +29,6 @@ int registerCmdRT() registerTclCmd(TclRunERT, "run_ert"); registerTclCmd(TclRunRT, "run_rt"); registerTclCmd(TclDestroyRT, "destroy_rt"); - // aux - registerTclCmd(TclRTCleanDef, "rt_clean_def"); return EXIT_SUCCESS; } diff --git a/src/interface/tcl/tcl_irt/include/tcl_rt.h b/src/interface/tcl/tcl_irt/include/tcl_rt.h index ab5c90862b..ce63abd6c2 100644 --- a/src/interface/tcl/tcl_irt/include/tcl_rt.h +++ b/src/interface/tcl/tcl_irt/include/tcl_rt.h @@ -80,22 +80,4 @@ class TclDestroyRT : public TclCmd #endif -#if 1 // aux - -class TclRTCleanDef : public TclCmd -{ - public: - explicit TclRTCleanDef(const char* cmd_name); - ~TclRTCleanDef() override = default; - - unsigned check() override { return 1; }; - - unsigned exec() override; - - private: - std::vector> _config_list; -}; - -#endif - } // namespace tcl diff --git a/src/interface/tcl/tcl_irt/src/tcl_rt_clean_def.cpp b/src/interface/tcl/tcl_irt/src/tcl_rt_clean_def.cpp deleted file mode 100644 index 34c15aead2..0000000000 --- a/src/interface/tcl/tcl_irt/src/tcl_rt_clean_def.cpp +++ /dev/null @@ -1,38 +0,0 @@ -// *************************************************************************************** -// Copyright (c) 2023-2025 Peng Cheng Laboratory -// Copyright (c) 2023-2025 Institute of Computing Technology, Chinese Academy of Sciences -// Copyright (c) 2023-2025 Beijing Institute of Open Source Chip -// -// iEDA is licensed under Mulan PSL v2. -// You can use this software according to the terms and conditions of the Mulan PSL v2. -// You may obtain a copy of Mulan PSL v2 at: -// http://license.coscl.org.cn/MulanPSL2 -// -// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, -// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, -// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. -// -// See the Mulan PSL v2 for more details. -// *************************************************************************************** -#include "RTInterface.hpp" -#include "tcl_rt.h" -#include "tcl_util.h" - -namespace tcl { - -TclRTCleanDef::TclRTCleanDef(const char* cmd_name) : TclCmd(cmd_name) -{ -} - -unsigned TclRTCleanDef::exec() -{ - if (!check()) { - return 0; - } - - RTI.cleanDef(); - - return 1; -} - -} // namespace tcl diff --git a/src/operation/iRT/interface/RTInterface.cpp b/src/operation/iRT/interface/RTInterface.cpp index 3b944a15bc..285ee28c59 100644 --- a/src/operation/iRT/interface/RTInterface.cpp +++ b/src/operation/iRT/interface/RTInterface.cpp @@ -183,104 +183,6 @@ void RTInterface::destroyRT() Logger::destroyInst(); } -void RTInterface::cleanDef() -{ -#if 1 - - ////////////////////////////////////////// - // 删除net内所有的wire - auto* idb_design = dmInst->get_idb_def_service()->get_design(); - IdbNetList* idb_net_list = idb_design->get_net_list(); - for (idb::IdbNet* idb_net : idb_net_list->get_net_list()) { - idb_net->clear_wire_list(); - } - // 删除net内所有的wire - ////////////////////////////////////////// - - ////////////////////////////////////////// - // 删除虚空的io_pin - idb::IdbPins* idb_pin_list = idb_design->get_io_pin_list(); - std::vector remove_pin_list; - for (idb::IdbPin* io_pin : idb_pin_list->get_pin_list()) { - if (io_pin->get_port_box_list().empty()) { - RTLOG.info(Loc::current(), "del io_pin: ", io_pin->get_pin_name()); - remove_pin_list.push_back(io_pin); - } - } - for (idb::IdbPin* io_pin : remove_pin_list) { - idb_design->removeIoPinSafe(io_pin); - } - // 删除虚空的io_pin - ////////////////////////////////////////// - -#endif - -#if 0 - - ////////////////////////////////////////// - // 删除net内所有的virtual - for (idb::IdbNet* idb_net : idb_net_list->get_net_list()) { - for (idb::IdbRegularWire* wire : idb_net->get_wire_list()->get_wire_list()) { - std::vector del_segment_list; - for (idb::IdbRegularWireSegment* segment : wire->get_segment_list()) { - if (segment->is_virtual(segment->get_point_second())) { - del_segment_list.push_back(segment); - } - } - for (idb::IdbRegularWireSegment* segment : del_segment_list) { - wire->delete_seg(segment); - } - } - } - // 删除net内所有的virtual - ////////////////////////////////////////// - - ////////////////////////////////////////// - // 删除net内所有的patch - for (idb::IdbNet* idb_net : idb_net_list->get_net_list()) { - for (idb::IdbRegularWire* wire : idb_net->get_wire_list()->get_wire_list()) { - std::vector del_segment_list; - for (idb::IdbRegularWireSegment* segment : wire->get_segment_list()) { - if (segment->is_rect()) { - del_segment_list.push_back(segment); - } - } - for (idb::IdbRegularWireSegment* segment : del_segment_list) { - wire->delete_seg(segment); - } - } - } - // 删除net内所有的patch - ////////////////////////////////////////// - - ////////////////////////////////////////// - // 删除net: 虚拟的io_pin与io_cell连接的PAD - std::vector remove_net_list; - for (idb::IdbNet* idb_net : idb_net_list->get_net_list()) { - bool has_io_pin = idb_net != nullptr && idb_net->has_io_pins(); - bool has_io_cell = false; - if (idb_net != nullptr && idb_net->get_instance_list() != nullptr) { - for (idb::IdbInstance* instance : idb_net->get_instance_list()->get_instance_list()) { - if (instance != nullptr && instance->get_cell_master() != nullptr && instance->get_cell_master()->is_pad()) { - has_io_cell = true; - break; - } - } - } - if (has_io_pin && has_io_cell) { - RTLOG.info(Loc::current(), "The net '", idb_net->get_net_name(), "' connects PAD and io_pin! removing..."); - remove_net_list.push_back(idb_net->get_net_name()); - } - } - for (std::string remove_net : remove_net_list) { - idb_design->removeNetSafe(remove_net); - } - // 删除net: 虚拟的io_pin与io_cell连接的PAD - ////////////////////////////////////////// - -#endif -} - #endif #endif diff --git a/src/operation/iRT/interface/RTInterface.hpp b/src/operation/iRT/interface/RTInterface.hpp index 84749c2c0f..06c6f74a51 100644 --- a/src/operation/iRT/interface/RTInterface.hpp +++ b/src/operation/iRT/interface/RTInterface.hpp @@ -81,7 +81,6 @@ class RTInterface void runERT(std::map config_map); void runRT(); void destroyRT(); - void cleanDef(); #endif #endif From 9583c57e003fc90b64ba71d0396c2bc70c3b27e7 Mon Sep 17 00:00:00 2001 From: ZhishengZeng Date: Tue, 15 Sep 2026 15:43:42 +0800 Subject: [PATCH 4/4] refactor(iRT): remove obsolete type power summary --- src/feature/database/feature_irt.h | 5 ----- src/feature/parser/feature_parser_tools.cpp | 20 -------------------- 2 files changed, 25 deletions(-) diff --git a/src/feature/database/feature_irt.h b/src/feature/database/feature_irt.h index 2c6df1b8e8..3d05f68192 100644 --- a/src/feature/database/feature_irt.h +++ b/src/feature/database/feature_irt.h @@ -49,7 +49,6 @@ struct PRSummary double total_demand = 0; double total_overflow = 0; double total_wire_length = 0; - std::map type_power_map; }; struct LASummary @@ -62,7 +61,6 @@ struct LASummary double total_wire_length = 0; std::map cut_via_num_map; int32_t total_via_num = 0; - std::map type_power_map; }; struct SRSummary @@ -75,7 +73,6 @@ struct SRSummary double total_wire_length = 0; std::map cut_via_num_map; int32_t total_via_num = 0; - std::map type_power_map; }; struct TASummary @@ -96,7 +93,6 @@ struct DRSummary int32_t total_patch_num = 0; std::map routing_violation_num_map; int32_t total_violation_num = 0; - std::map type_power_map; }; struct VRSummary @@ -115,7 +111,6 @@ struct VRSummary std::map among_net_violation_type_num_map; std::map among_net_routing_violation_num_map; int32_t among_net_total_violation_num = 0; - std::map type_power_map; }; struct RTSummary diff --git a/src/feature/parser/feature_parser_tools.cpp b/src/feature/parser/feature_parser_tools.cpp index bdd25036da..433a4007ab 100644 --- a/src/feature/parser/feature_parser_tools.cpp +++ b/src/feature/parser/feature_parser_tools.cpp @@ -85,10 +85,6 @@ json FeatureParser::buildSummaryRT() pr_json["total_demand"] = summary_irt.pr_summary.total_demand; pr_json["total_overflow"] = summary_irt.pr_summary.total_overflow; pr_json["total_wire_length"] = summary_irt.pr_summary.total_wire_length; - for (auto& [type, power] : summary_irt.pr_summary.type_power_map) { - pr_json["type_power_map"]["type"] = type; - pr_json["type_power_map"]["power"] = power; - } json_rt["PR"] = pr_json; } @@ -111,10 +107,6 @@ json FeatureParser::buildSummaryRT() la_json["cut_via_num_map"][std::to_string(cut_layer_idx)] = via_num; } la_json["total_via_num"] = summary_irt.la_summary.total_via_num; - for (auto& [type, power] : summary_irt.la_summary.type_power_map) { - la_json["type_power_map"]["type"] = type; - la_json["type_power_map"]["power"] = power; - } json_rt["LA"] = la_json; } @@ -140,10 +132,6 @@ json FeatureParser::buildSummaryRT() sr_json["cut_via_num_map"][std::to_string(cut_layer_idx)] = via_num; } sr_json["total_via_num"] = sr_summary.total_via_num; - for (auto& [type, power] : sr_summary.type_power_map) { - sr_json["type_power_map"]["type"] = type; - sr_json["type_power_map"]["power"] = power; - } sr_json_list.push_back(sr_json); } json_rt["SR"] = sr_json_list; @@ -185,10 +173,6 @@ json FeatureParser::buildSummaryRT() dr_json["routing_violation_num_map"][std::to_string(routing_layer_idx)] = violation_num; } dr_json["total_violation_num"] = dr_summary.total_violation_num; - for (auto& [type, power] : dr_summary.type_power_map) { - dr_json["type_power_map"]["type"] = type; - dr_json["type_power_map"]["power"] = power; - } dr_json_list.push_back(dr_json); } json_rt["DR"] = dr_json_list; @@ -217,10 +201,6 @@ json FeatureParser::buildSummaryRT() vr_json["among_net_routing_violation_num_map"][std::to_string(routing_layer_idx)] = violation_num; } vr_json["among_net_total_violation_num"] = summary_irt.vr_summary.among_net_total_violation_num; - for (auto& [type, power] : summary_irt.vr_summary.type_power_map) { - vr_json["type_power_map"]["type"] = type; - vr_json["type_power_map"]["power"] = power; - } json_rt["VR"] = vr_json; }