Builtin optimisation enhancement

[MaryBennett]

The CORE-V builtins can be enhanced by expanding the rtl for each instruction. This would allow gcc to pattern match to these builtins.
More testing with a simulator would be required.

Added, untested with simulator:

• XCVmac
• XCValu
• XCVelw
• XCVbi
• XCVmem
• XCVbitmanip
• XCVsimd
• XCVhwlp

[MaryBennett]

This is required for upstreaming

[yulong18]

I and @zhixiao-zhang will focuse on the implementation of XCVsimd.