Make IN/OUT Intrinsics variadic

I foresee the SC files getting pretty ugly if users define multiple INs and OUTs... 

ie
```sc
def ...
  IN(reg1)
  IN(reg2)
  IN(opc)
  ...
  OUT(ra)
  OUT(rb)
  OUT(rt)
}
```

I propose we change the intrinsics to be variadic such that the above example would turn into 

```sc
def ...
  IN(reg1, reg2, opc)
  ... 
  OUT(ra, rb, rt)
}
```
