From 53f51ae335ea6a09a01906e419fececf1465ba25 Mon Sep 17 00:00:00 2001 From: Aleksei-Fil Date: Wed, 30 Apr 2025 19:32:30 +0500 Subject: [PATCH 1/5] transfer one byte --- uart_transmitter/Makefile | 101 ++++++++++ uart_transmitter/karnix_cabga256.lpf | 286 +++++++++++++++++++++++++++ uart_transmitter/top.v | 39 ++++ uart_transmitter/uart_tx.v | 128 ++++++++++++ 4 files changed, 554 insertions(+) create mode 100644 uart_transmitter/Makefile create mode 100644 uart_transmitter/karnix_cabga256.lpf create mode 100644 uart_transmitter/top.v create mode 100644 uart_transmitter/uart_tx.v diff --git a/uart_transmitter/Makefile b/uart_transmitter/Makefile new file mode 100644 index 0000000..7ba528f --- /dev/null +++ b/uart_transmitter/Makefile @@ -0,0 +1,101 @@ +NAME = ir_encoder +VERILOG += top.v +VERILOG += uart_tx.v +INC = ./ +LPF = karnix_cabga256.lpf +DEVICE = 25k +PACKAGE = CABGA256 +FTDI_CHANNEL = 0 ### FT2232 has two channels, select 0 for channel A or 1 for channel B +# +FLASH_METHOD := flash +UPLOAD_METHOD := openloader + +.PHONY: clean +all: $(NAME).bit + +.PHONY: upload +upload: $(NAME).bit +ifeq ("$(UPLOAD_METHOD)", "ecpprog") + $(MAKE) upload_ecpprog +else +ifeq ("$(UPLOAD_METHOD)", "openloader") + $(MAKE) upload_openloader +else +ifeq ("$(UPLOAD_METHOD)", "") + echo "Upload method has not been chosen, set UPLOAD_METHOD env variable to 'ecpprog' or 'openloader'." +else + echo "Unsupported upload method: $(UPLOAD_METHOD)." +endif +endif +endif + +.PHONY: upload_openloader +upload_openloader: +ifeq ("$(FLASH_METHOD)", "flash") + openFPGALoader -v --ftdi-channel $(FTDI_CHANNEL) -f --reset $(NAME).bit +else + openFPGALoader -v --ftdi-channel $(FTDI_CHANNEL) $(NAME).bit +endif + +.PHONY: upload_ecpprog +upload_ecpprog: +ifeq ("$(FLASH_METHOD)", "flash") + ecpprog -I $(if $(filter $(FTDI_CHANNEL),0),A,B) -X $(NAME).bit +else + ecpprog -I $(if $(filter $(FTDI_CHANNEL),0),A,B) -S $(NAME).bit +endif + + + +fw: $(NAME).bit + +$(NAME).bit: $(LPF) $(VERILOG) + yosys -p "verilog_defaults -add -I$(subst :, -I,$(INC))" -p "read_verilog -sv $(VERILOG)" -p "synth_ecp5 -json $(NAME).json -top top" -l $(NAME).yosys.log + nextpnr-ecp5 --package $(PACKAGE) --$(DEVICE) --json $(NAME).json --textcfg $(NAME)_out.config --lpf $(LPF) --lpf-allow-unconstrained -l $(NAME).nextpnr.log + ecppack --compress --freq 38.8 --input $(NAME)_out.config --bit $(NAME).bit + $(MAKE) check + + +.PHONY: graph +graph: $(LPF) $(VERILOG) + yosys -p "verilog_defaults -add -I$(subst :, -I,$(INC))" -p "read_verilog -sv +/ecp5/cells_bb.v" -p "hierarchy -check -top top" -p "proc; opt; fsm; memory; opt" -p "synth_ecp5 -noabc9 -top top -json $(NAME).json" -p "show -prefix $(NAME) -notitle -colors 2 -width -format dot" $(VERILOG) | tee $(NAME).yosys.log + @if [ -f "`which dot`" ]; then \ + echo "Generating PDFs with schematics..."; \ + dot -Tpdf -O $(NAME).dot; \ + else \ + echo "Note: 'dot' utility is not installed, PDF won't be generated!"; \ + fi + netlistsvg -o $(NAME).svg $(NAME).json + #@echo "Generating SVGs with routing and placement..." + #nextpnr-ecp5 --package $(PACKAGE) --$(DEVICE) --json $(NAME).json --textcfg $(NAME)_out.config --lpf $(LPF) --lpf-allow-unconstrained --placed-svg $(NAME)-placed.svg --routed-svg $(NAME)-routed.svg | tee $(NAME).nextpnr.log + $(MAKE) check + @if [ -f "`which xdot`" ]; then \ + xdot $(NAME).dot; \ + else \ + echo "xdot utility is not installed, cannot show you DOT file:"; \ + ls -al $(NAME).dot; \ + fi + @if [ -f "`which firefox`" ]; then \ + firefox $(NAME).svg $(NAME)-placed.svg $(NAME)-routed.svg $(NAME).*pdf; \ + else \ + echo "Firefox is not installed, cannot show you SVG and PDF files:"; \ + ls -al $(NAME).svg $(NAME)-placed.svg $(NAME)-routed.svg $(NAME).*pdf; \ + fi + + +.PHONY: sim +sim: $(VERILOG) $(NAME)_tb.v $(shell yosys-config --datdir)/ice40/cells_sim.v + iverilog $^ -o $(NAME)_tb.out + ./$(NAME)_tb.out + gtkwave $(NAME)_tb.vcd $(NAME)_tb.gtkw & + +check: + @echo "Checking for warnings..." + @(grep Warn $(NAME).yosys.log $(NAME).nextpnr.log; echo) + +.PHONY: clean +clean: + rm -f *.bit *.txt *.log *.json .blif *.out *.svg *.dot *.pdf *out.config *.vcd + + + diff --git a/uart_transmitter/karnix_cabga256.lpf b/uart_transmitter/karnix_cabga256.lpf new file mode 100644 index 0000000..ccb74a6 --- /dev/null +++ b/uart_transmitter/karnix_cabga256.lpf @@ -0,0 +1,286 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; + +FREQUENCY PORT "clk25" 25.0 MHz; +LOCATE COMP "clk25" SITE "B9"; +IOBUF PORT "clk25" IO_TYPE=LVCMOS33; + +LOCATE COMP "key[0]" SITE "B13"; +IOBUF PORT "key[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "key[1]" SITE "C13"; +IOBUF PORT "key[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "key[2]" SITE "D13"; +IOBUF PORT "key[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "key[3]" SITE "E13"; +IOBUF PORT "key[3]" IO_TYPE=LVCMOS33; + +LOCATE COMP "led[0]" SITE "A13"; # LED0 +IOBUF PORT "led[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "led[1]" SITE "A14"; # LED1 +IOBUF PORT "led[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "led[2]" SITE "A15"; # LED2 +IOBUF PORT "led[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "led[3]" SITE "B14"; # LED3 +IOBUF PORT "led[3]" IO_TYPE=LVCMOS33; + +LOCATE COMP "gpio[0]" SITE "L1"; # HUB_00 +IOBUF PORT "gpio[0]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[0]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[1]" SITE "L2"; # HUB_01 +IOBUF PORT "gpio[1]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[1]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[2]" SITE "M1"; # HUB_02 +IOBUF PORT "gpio[2]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[2]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[3]" SITE "M2"; # HUB_03 +IOBUF PORT "gpio[3]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[3]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[4]" SITE "K4"; # HUB_04 +IOBUF PORT "gpio[4]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[4]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[5]" SITE "K5"; # HUB_05 +IOBUF PORT "gpio[5]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[5]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[6]" SITE "L4"; # HUB_06 +IOBUF PORT "gpio[6]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[6]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[7]" SITE "L5"; # HUB_07 +IOBUF PORT "gpio[7]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[7]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[8]" SITE "M9"; # HUB_08 - N1 is used by QSPI0_SCLK +IOBUF PORT "gpio[8]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[8]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[9]" SITE "P2"; # HUB_09 +IOBUF PORT "gpio[9]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[9]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[10]" SITE "L3"; # HUB_10 +IOBUF PORT "gpio[10]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[10]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[11]" SITE "M3"; # HUB_11 +IOBUF PORT "gpio[11]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[11]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[12]" SITE "P1"; # HUB_12 +IOBUF PORT "gpio[12]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[12]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[13]" SITE "R1"; # HUB_13 +IOBUF PORT "gpio[13]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[13]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[14]" SITE "M4"; # HUB_14 +IOBUF PORT "gpio[14]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[14]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[15]" SITE "N3"; # HUB_15 +IOBUF PORT "gpio[15]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[15]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "uart_debug_txd" SITE "E12"; # UART_DEBUG_TXD +IOBUF PORT "uart_debug_txd" IO_TYPE=LVCMOS33; +LOCATE COMP "uart_debug_rxd" SITE "D12"; # UART_DEBUG_RXD +IOBUF PORT "uart_debug_rxd" IO_TYPE=LVCMOS33; +LOCATE COMP "rst_n" SITE "R8"; # FPGA_RESET +IOBUF PORT "rst_n" IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "rs485_txd" SITE "A8"; # RS485_DI +IOBUF PORT "rs485_txd" IO_TYPE=LVCMOS33; +LOCATE COMP "rs485_rxd" SITE "A7"; # RS485_RO +IOBUF PORT "rs485_rxd" IO_TYPE=LVCMOS33; +LOCATE COMP "rs485_de" SITE "C7"; # RS485_DE +IOBUF PORT "rs485_de" IO_TYPE=LVCMOS33; +LOCATE COMP "i2c_sda" SITE "P7"; # EEPROM_I2C_SDA +IOBUF PORT "i2c_sda" IO_TYPE=LVCMOS33 DRIVE=8; +IOBUF PORT "i2c_sda" PULLMODE=UP; +LOCATE COMP "i2c_scl" SITE "R7"; # EEPROM_I2C_SCL +IOBUF PORT "i2c_scl" IO_TYPE=LVCMOS33; +IOBUF PORT "i2c_scl" PULLMODE=UP; +LOCATE COMP "eeprom_wp" SITE "R6"; # EEPROM_WP +IOBUF PORT "eeprom_wp" IO_TYPE=LVCMOS33; +IOBUF PORT "eeprom_wp" PULLMODE=UP; +LOCATE COMP "config" SITE "T6"; # EEPROM_RESET +IOBUF PORT "config" IO_TYPE=LVCMOS33; +IOBUF PORT "config" PULLMODE=UP; + + +LOCATE COMP "lan_mdc" SITE "A2"; # LAN_MDC +IOBUF PORT "lan_mdc" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_mdc" PULLMODE=NONE; +LOCATE COMP "lan_nint" SITE "B3"; # LAN_nINT +IOBUF PORT "lan_nint" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_nint" PULLMODE=NONE; +LOCATE COMP "lan_nrst" SITE "A3"; # LAN_nRST +IOBUF PORT "lan_nrst" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_nrst" PULLMODE=NONE; +LOCATE COMP "lan_txen" SITE "A4"; # LAN_TXEN +IOBUF PORT "lan_txen" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_txen" PULLMODE=NONE; +LOCATE COMP "lan_txclk" SITE "B4"; # LAN_TXCLK +IOBUF PORT "lan_txclk" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_txclk" PULLMODE=NONE; +# FREQUENCY PORT "lan_txclk" 25.0 MHz; +LOCATE COMP "lan_txd0" SITE "B5"; # LAN_TXD0 +IOBUF PORT "lan_txd0" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_txd0" PULLMODE=NONE; +LOCATE COMP "lan_txd1" SITE "A5"; # LAN_TXD1 +IOBUF PORT "lan_txd1" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_txd1" PULLMODE=NONE; +LOCATE COMP "lan_txd2" SITE "B6"; # LAN_TXD2 +IOBUF PORT "lan_txd2" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_txd2" PULLMODE=NONE; +LOCATE COMP "lan_txd3" SITE "A6"; # LAN_TXD3 +IOBUF PORT "lan_txd3" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_txd3" PULLMODE=NONE; +LOCATE COMP "lan_rxd0" SITE "D1"; # LAN_RXD0 +IOBUF PORT "lan_rxd0" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxd0" PULLMODE=NONE; +LOCATE COMP "lan_rxd1" SITE "E2"; # LAN_RXD1 +IOBUF PORT "lan_rxd1" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxd1" PULLMODE=NONE; +LOCATE COMP "lan_rxd2" SITE "E1"; # LAN_RXD2 +IOBUF PORT "lan_rxd2" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxd2" PULLMODE=NONE; +LOCATE COMP "lan_rxd3" SITE "F2"; # LAN_RXD3 +IOBUF PORT "lan_rxd3" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxd3" PULLMODE=NONE; +LOCATE COMP "lan_mdio" SITE "B1"; # LAN_MDIO +IOBUF PORT "lan_mdio" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_mdio" PULLMODE=NONE; +LOCATE COMP "lan_col" SITE "B2"; # LAN_COL +IOBUF PORT "lan_col" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_col" PULLMODE=NONE; +LOCATE COMP "lan_crs" SITE "C1"; # LAN_CRS +IOBUF PORT "lan_crs" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_crs" PULLMODE=NONE; +LOCATE COMP "lan_rxer" SITE "C2"; # LAN_RXER +IOBUF PORT "lan_rxer" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxer" PULLMODE=NONE; +LOCATE COMP "lan_rxdv" SITE "B7"; # LAN_RXDV +IOBUF PORT "lan_rxdv" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxdv" PULLMODE=NONE; +LOCATE COMP "lan_rxclk" SITE "F1"; # LAN_RXCLK +IOBUF PORT "lan_rxclk" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxclk" PULLMODE=NONE; +# FREQUENCY PORT "lan_rxclk" 25.0 MHz; + +LOCATE COMP "sram_cs" SITE "H15"; # SRAM #CS +IOBUF PORT "sram_cs" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_we" SITE "K14"; # SRAM #WE +IOBUF PORT "sram_we" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_oe" SITE "J14"; # SRAM #OE +IOBUF PORT "sram_oe" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_bhe" SITE "J16"; # SRAM #BHE +IOBUF PORT "sram_bhe" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_ble" SITE "J15"; # SRAM #BLE +IOBUF PORT "sram_ble" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[0]" SITE "L16"; # SRAM D00 +IOBUF PORT "sram_dat[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[1]" SITE "L15"; # SRAM D01 +IOBUF PORT "sram_dat[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[2]" SITE "M16"; # SRAM D02 +IOBUF PORT "sram_dat[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[3]" SITE "M15"; # SRAM D03 +IOBUF PORT "sram_dat[3]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[4]" SITE "K13"; # SRAM D04 +IOBUF PORT "sram_dat[4]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[5]" SITE "K12"; # SRAM D05 +IOBUF PORT "sram_dat[5]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[6]" SITE "L13"; # SRAM D06 +IOBUF PORT "sram_dat[6]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[7]" SITE "L12"; # SRAM D07 +IOBUF PORT "sram_dat[7]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[8]" SITE "N16"; # SRAM D08 +IOBUF PORT "sram_dat[8]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[9]" SITE "P15"; # SRAM D09 +IOBUF PORT "sram_dat[9]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[10]" SITE "L14"; # SRAM D10 +IOBUF PORT "sram_dat[10]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[11]" SITE "M14"; # SRAM D11 +IOBUF PORT "sram_dat[11]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[12]" SITE "P16"; # SRAM D12 +IOBUF PORT "sram_dat[12]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[13]" SITE "R16"; # SRAM D13 +IOBUF PORT "sram_dat[13]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[14]" SITE "M13"; # SRAM D14 +IOBUF PORT "sram_dat[14]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[15]" SITE "N14"; # SRAM D15 +IOBUF PORT "sram_dat[15]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[0]" SITE "N13"; # SRAM A00 +IOBUF PORT "sram_addr[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[1]" SITE "P14"; # SRAM A01 +IOBUF PORT "sram_addr[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[2]" SITE "R15"; # SRAM A02 +IOBUF PORT "sram_addr[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[3]" SITE "T15"; # SRAM A03 +IOBUF PORT "sram_addr[3]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[4]" SITE "P13"; # SRAM A04 +IOBUF PORT "sram_addr[4]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[5]" SITE "R14"; # SRAM A05 +IOBUF PORT "sram_addr[5]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[6]" SITE "R13"; # SRAM A06 +IOBUF PORT "sram_addr[6]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[7]" SITE "T14"; # SRAM A07 +IOBUF PORT "sram_addr[7]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[8]" SITE "R12"; # SRAM A08 +IOBUF PORT "sram_addr[8]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[9]" SITE "T13"; # SRAM A09 +IOBUF PORT "sram_addr[9]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[10]" SITE "M12"; # SRAM A10 +IOBUF PORT "sram_addr[10]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[11]" SITE "N12"; # SRAM A11 +IOBUF PORT "sram_addr[11]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[12]" SITE "M11"; # SRAM A12 +IOBUF PORT "sram_addr[12]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[13]" SITE "N11"; # SRAM A13 +IOBUF PORT "sram_addr[13]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[14]" SITE "P11"; # SRAM A14 +IOBUF PORT "sram_addr[14]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[15]" SITE "P12"; # SRAM A15 +IOBUF PORT "sram_addr[15]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[16]" SITE "K16"; # SRAM A16 +IOBUF PORT "sram_addr[16]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[17]" SITE "K15"; # SRAM A17 +IOBUF PORT "sram_addr[17]" IO_TYPE=LVCMOS33; + +LOCATE COMP "spiAudioDAC_sclk" SITE "C16"; # DAC SPI SCLK +IOBUF PORT "spiAudioDAC_sclk" IO_TYPE=LVCMOS33; +LOCATE COMP "spiAudioDAC_miso" SITE "B16"; # DAC SPI MISO +IOBUF PORT "spiAudioDAC_miso" IO_TYPE=LVCMOS33; +LOCATE COMP "spiAudioDAC_mosi" SITE "B15"; # DAC SPI MOSI +IOBUF PORT "spiAudioDAC_mosi" IO_TYPE=LVCMOS33; +LOCATE COMP "spiAudioDAC_ss[0]" SITE "C15"; # DAC SPI CSn +IOBUF PORT "spiAudioDAC_ss[0]" IO_TYPE=LVCMOS33; + +LOCATE COMP "spi0_sclk" SITE "R5"; # SPI0 SCLK/GPIO_24 +IOBUF PORT "spi0_sclk" IO_TYPE=LVCMOS33; +LOCATE COMP "spi0_miso" SITE "T4"; # SPI0 MISO/GPIO_25 +IOBUF PORT "spi0_miso" IO_TYPE=LVCMOS33; +LOCATE COMP "spi0_mosi" SITE "M5"; # SPI0 MOSI/GPIO_26 +IOBUF PORT "spi0_mosi" IO_TYPE=LVCMOS33; +LOCATE COMP "spi0_ss[0]" SITE "N5"; # SPI0 CSn/GPIO_27 +IOBUF PORT "spi0_ss[0]" IO_TYPE=LVCMOS33; + +LOCATE COMP "hdmi_tmds_p[0]" SITE "A11"; +IOBUF PORT "hdmi_tmds_p[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_p[1]" SITE "D11"; +IOBUF PORT "hdmi_tmds_p[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_p[2]" SITE "B11"; +IOBUF PORT "hdmi_tmds_p[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_n[0]" SITE "A12"; +IOBUF PORT "hdmi_tmds_n[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_n[1]" SITE "E11"; +IOBUF PORT "hdmi_tmds_n[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_n[2]" SITE "C11"; +IOBUF PORT "hdmi_tmds_n[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_clk_p" SITE "B12"; +IOBUF PORT "hdmi_tmds_clk_p" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_clk_n" SITE "C12"; +IOBUF PORT "hdmi_tmds_clk_n" IO_TYPE=LVCMOS33; + +LOCATE COMP "qspi0_cs" SITE "N8"; +IOBUF PORT "qspi0_cs" IO_TYPE=LVCMOS33; +LOCATE COMP "qspi0_sclk" SITE "N1"; // GPIO_08, should be M9 +IOBUF PORT "qspi0_sclk" IO_TYPE=LVCMOS33; +LOCATE COMP "qspi0_io0" SITE "T8"; +IOBUF PORT "qspi0_io0" IO_TYPE=LVCMOS33; +LOCATE COMP "qspi0_io1" SITE "T7"; +IOBUF PORT "qspi0_io1" IO_TYPE=LVCMOS33; +LOCATE COMP "qspi0_io2" SITE "M7"; +IOBUF PORT "qspi0_io2" IO_TYPE=LVCMOS33; +LOCATE COMP "qspi0_io3" SITE "N7"; +IOBUF PORT "qspi0_io3" IO_TYPE=LVCMOS33; + diff --git a/uart_transmitter/top.v b/uart_transmitter/top.v new file mode 100644 index 0000000..0b1cc0a --- /dev/null +++ b/uart_transmitter/top.v @@ -0,0 +1,39 @@ +module top ( + input wire clk25, + input wire [1:0] key, + output wire [0:0] led, + output wire uart_debug_txd +); + +wire [31:0] baudrate = 31'd115200; + +wire rst; +assign rst = key[0]; + +wire ready; +reg [7:0] data = 8'h41; //"A" + +wire valid; +assign valid = key[1]; + + +wire tx; + + +assign led[0] = ready; +assign uart_debug_txd = tx; + + +uart_tx uart ( + .clk(clk25), + .rst(rst), + .data(data), + .baudrate(baudrate), + .ready(ready), + .valid(valid), + .parity_en(1'b1), // Enable bit parity + .parity_type(1'b1), // Odd parity + .tx(tx) +); + +endmodule diff --git a/uart_transmitter/uart_tx.v b/uart_transmitter/uart_tx.v new file mode 100644 index 0000000..98b79c5 --- /dev/null +++ b/uart_transmitter/uart_tx.v @@ -0,0 +1,128 @@ +module uart_tx ( + input wire rst, // Reset + input wire clk, // 25 MHz clock + input wire [7:0] data, // byte to transmit (need to use param) + input wire [31:0] baudrate, // baudrate selector + input wire valid, // Valid signal + input wire parity_en, // Enable pariry_type (1-Enable) + input wire parity_type, // 0 - Even parity, 1 - Odd parity + output reg ready, // Ready signal + output reg tx // uart output signal +); + +//=============================================== +// State parameters +//=============================================== + +localparam [2:0] + IDLE = 3'd0, // Waiting for command + START_BIT = 3'd1, // Start bit + DATA_BITS = 3'd2, // Start bit transfer + PARITY_BIT = 3'd3, // Parity + STOP_BIT = 3'd4; // Stop bit + +//=============================================== +// Transmitter state machine +//=============================================== +reg [7:0] shift_reg; +reg [2:0] bit_count; +reg [2:0] state; + +reg parity_bit; +wire final_parity; +assign final_parity = parity_type ? ~(^data) : ^data; + +reg [31:0] baud_counter; +wire [31:0] baud_limit; +assign baud_limit = (25000000/baudrate) - 1; +reg baud_tick; + +reg valid_prev; + +always @(posedge clk or posedge rst) begin + if (rst) begin + state <= IDLE; + tx <= 1'b1; + ready <= 1'b1; + shift_reg <= 0; + bit_count <= 0; + baud_tick <= 0; // for test + baud_counter <= 0; + end else begin + valid_prev <= valid; + + // Generation clk with baudrate + if (state != IDLE) begin + if (baud_counter == baud_limit) begin + baud_counter <= 0; + baud_tick <= 1'b1; + end else begin + baud_counter <= baud_counter + 1; + baud_tick <= 1'b0; + end + end else begin + baud_counter <= 0; + baud_tick <= 1'b1; // for test + end + + + case (state) + IDLE: begin + tx <= 1'b1; + //ready <= 1'b1; + if (ready && valid && !valid_prev) begin + state <= START_BIT; + shift_reg <= data; + baud_counter <= 0; + ready <= 1'b0; + parity_bit <= final_parity; + end + end + + //valid_prev <= valid; + + START_BIT: begin + tx <= 1'b0; + if (baud_counter == baud_limit) begin + state <= DATA_BITS; + baud_counter <= 0; + bit_count <= 0; + end + end + + DATA_BITS: begin + tx <= shift_reg[0]; + if (baud_counter == baud_limit) begin + shift_reg <= {1'b0, shift_reg[7:1]}; + baud_counter <= 0; + bit_count <= bit_count + 1; + if (bit_count == 7) begin // 8 bit + state <= parity_en ? PARITY_BIT : STOP_BIT; + end + end else begin + baud_counter <= baud_counter + 1; + end + end + + PARITY_BIT: begin + tx <= parity_bit; + if (baud_counter == baud_limit) begin + state <= STOP_BIT; + end + end + + STOP_BIT: begin + tx <= 1'b1; + if (baud_counter == baud_limit) begin + baud_counter <= 0; + state <= IDLE; + ready <= 1'b1; + end + end + endcase + + end +end + + +endmodule From fc0769635e217be0b1d19298281c0d399a3d28f8 Mon Sep 17 00:00:00 2001 From: Aleksei-Fil Date: Tue, 13 May 2025 04:28:08 +0500 Subject: [PATCH 2/5] uart_rx --- uart_receiver/Makefile | 102 +++++++++++ uart_receiver/Readme.md | 28 +++ uart_receiver/karnix_cabga256.lpf | 286 ++++++++++++++++++++++++++++++ uart_receiver/tb.v | 131 ++++++++++++++ uart_receiver/top.v | 47 +++++ uart_receiver/top.v~ | 158 +++++++++++++++++ uart_receiver/uart_rx.v | 158 +++++++++++++++++ 7 files changed, 910 insertions(+) create mode 100644 uart_receiver/Makefile create mode 100644 uart_receiver/Readme.md create mode 100644 uart_receiver/karnix_cabga256.lpf create mode 100644 uart_receiver/tb.v create mode 100644 uart_receiver/top.v create mode 100644 uart_receiver/top.v~ create mode 100644 uart_receiver/uart_rx.v diff --git a/uart_receiver/Makefile b/uart_receiver/Makefile new file mode 100644 index 0000000..bbd699d --- /dev/null +++ b/uart_receiver/Makefile @@ -0,0 +1,102 @@ +NAME = uart_receiver +VERILOG += top.v +VERILOG += uart_rx.v +VERILOG += ir_encoder.v +INC = ./ +LPF = karnix_cabga256.lpf +DEVICE = 25k +PACKAGE = CABGA256 +FTDI_CHANNEL = 0 ### FT2232 has two channels, select 0 for channel A or 1 for channel B +# +FLASH_METHOD := flash +UPLOAD_METHOD := openloader + +.PHONY: clean +all: $(NAME).bit + +.PHONY: upload +upload: $(NAME).bit +ifeq ("$(UPLOAD_METHOD)", "ecpprog") + $(MAKE) upload_ecpprog +else +ifeq ("$(UPLOAD_METHOD)", "openloader") + $(MAKE) upload_openloader +else +ifeq ("$(UPLOAD_METHOD)", "") + echo "Upload method has not been chosen, set UPLOAD_METHOD env variable to 'ecpprog' or 'openloader'." +else + echo "Unsupported upload method: $(UPLOAD_METHOD)." +endif +endif +endif + +.PHONY: upload_openloader +upload_openloader: +ifeq ("$(FLASH_METHOD)", "flash") + openFPGALoader -v --ftdi-channel $(FTDI_CHANNEL) -f --reset $(NAME).bit +else + openFPGALoader -v --ftdi-channel $(FTDI_CHANNEL) $(NAME).bit +endif + +.PHONY: upload_ecpprog +upload_ecpprog: +ifeq ("$(FLASH_METHOD)", "flash") + ecpprog -I $(if $(filter $(FTDI_CHANNEL),0),A,B) -X $(NAME).bit +else + ecpprog -I $(if $(filter $(FTDI_CHANNEL),0),A,B) -S $(NAME).bit +endif + + + +fw: $(NAME).bit + +$(NAME).bit: $(LPF) $(VERILOG) + yosys -p "verilog_defaults -add -I$(subst :, -I,$(INC))" -p "read_verilog -sv $(VERILOG)" -p "synth_ecp5 -json $(NAME).json -top top" -l $(NAME).yosys.log + nextpnr-ecp5 --package $(PACKAGE) --$(DEVICE) --json $(NAME).json --textcfg $(NAME)_out.config --lpf $(LPF) --lpf-allow-unconstrained -l $(NAME).nextpnr.log + ecppack --compress --freq 38.8 --input $(NAME)_out.config --bit $(NAME).bit + $(MAKE) check + + +.PHONY: graph +graph: $(LPF) $(VERILOG) + yosys -p "verilog_defaults -add -I$(subst :, -I,$(INC))" -p "read_verilog -sv +/ecp5/cells_bb.v" -p "hierarchy -check -top top" -p "proc; opt; fsm; memory; opt" -p "synth_ecp5 -noabc9 -top top -json $(NAME).json" -p "show -prefix $(NAME) -notitle -colors 2 -width -format dot" $(VERILOG) | tee $(NAME).yosys.log + @if [ -f "`which dot`" ]; then \ + echo "Generating PDFs with schematics..."; \ + dot -Tpdf -O $(NAME).dot; \ + else \ + echo "Note: 'dot' utility is not installed, PDF won't be generated!"; \ + fi + netlistsvg -o $(NAME).svg $(NAME).json + #@echo "Generating SVGs with routing and placement..." + #nextpnr-ecp5 --package $(PACKAGE) --$(DEVICE) --json $(NAME).json --textcfg $(NAME)_out.config --lpf $(LPF) --lpf-allow-unconstrained --placed-svg $(NAME)-placed.svg --routed-svg $(NAME)-routed.svg | tee $(NAME).nextpnr.log + $(MAKE) check + @if [ -f "`which xdot`" ]; then \ + xdot $(NAME).dot; \ + else \ + echo "xdot utility is not installed, cannot show you DOT file:"; \ + ls -al $(NAME).dot; \ + fi + @if [ -f "`which firefox`" ]; then \ + firefox $(NAME).svg $(NAME)-placed.svg $(NAME)-routed.svg $(NAME).*pdf; \ + else \ + echo "Firefox is not installed, cannot show you SVG and PDF files:"; \ + ls -al $(NAME).svg $(NAME)-placed.svg $(NAME)-routed.svg $(NAME).*pdf; \ + fi + + +.PHONY: sim +sim: $(VERILOG) $(NAME)_tb.v $(shell yosys-config --datdir)/ice40/cells_sim.v + iverilog $^ -o $(NAME)_tb.out + ./$(NAME)_tb.out + gtkwave $(NAME)_tb.vcd $(NAME)_tb.gtkw & + +check: + @echo "Checking for warnings..." + @(grep Warn $(NAME).yosys.log $(NAME).nextpnr.log; echo) + +.PHONY: clean +clean: + rm -f *.bit *.txt *.log *.json .blif *.out *.svg *.dot *.pdf *out.config *.vcd + + + diff --git a/uart_receiver/Readme.md b/uart_receiver/Readme.md new file mode 100644 index 0000000..1367579 --- /dev/null +++ b/uart_receiver/Readme.md @@ -0,0 +1,28 @@ +sudo screen /dev/ttyUSB1 115200,cs8,even,ixoff,-istrip +# Для screen (параметры: скорость, четность, стоп-биты) + /dev/ttyUSB0 - UART-устройство + + 115200 - скорость передачи (baud rate) + + cs8 - 8 бит данных + + even - чётная четность (even parity) + + ixoff - отключение управления потоком + + -istrip - не обрезать 8-й бит + +screen /dev/ttyUSB1 115200,cs8,even,ixoff,-istrip,-cstopb + + -cstopb = 1 стоп-бит (по умолчанию) + + cstopb = 2 стоп-бита + +Настройки четности: +even Чётная +odd Нечётная +-parity Без проверки чётности + +minicom (лучше для сложных настроек): + +minicom -D /dev/ttyUSB0 -b 115200 --8bit --parity=odd --stop=2 diff --git a/uart_receiver/karnix_cabga256.lpf b/uart_receiver/karnix_cabga256.lpf new file mode 100644 index 0000000..ccb74a6 --- /dev/null +++ b/uart_receiver/karnix_cabga256.lpf @@ -0,0 +1,286 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; + +FREQUENCY PORT "clk25" 25.0 MHz; +LOCATE COMP "clk25" SITE "B9"; +IOBUF PORT "clk25" IO_TYPE=LVCMOS33; + +LOCATE COMP "key[0]" SITE "B13"; +IOBUF PORT "key[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "key[1]" SITE "C13"; +IOBUF PORT "key[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "key[2]" SITE "D13"; +IOBUF PORT "key[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "key[3]" SITE "E13"; +IOBUF PORT "key[3]" IO_TYPE=LVCMOS33; + +LOCATE COMP "led[0]" SITE "A13"; # LED0 +IOBUF PORT "led[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "led[1]" SITE "A14"; # LED1 +IOBUF PORT "led[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "led[2]" SITE "A15"; # LED2 +IOBUF PORT "led[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "led[3]" SITE "B14"; # LED3 +IOBUF PORT "led[3]" IO_TYPE=LVCMOS33; + +LOCATE COMP "gpio[0]" SITE "L1"; # HUB_00 +IOBUF PORT "gpio[0]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[0]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[1]" SITE "L2"; # HUB_01 +IOBUF PORT "gpio[1]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[1]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[2]" SITE "M1"; # HUB_02 +IOBUF PORT "gpio[2]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[2]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[3]" SITE "M2"; # HUB_03 +IOBUF PORT "gpio[3]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[3]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[4]" SITE "K4"; # HUB_04 +IOBUF PORT "gpio[4]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[4]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[5]" SITE "K5"; # HUB_05 +IOBUF PORT "gpio[5]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[5]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[6]" SITE "L4"; # HUB_06 +IOBUF PORT "gpio[6]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[6]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[7]" SITE "L5"; # HUB_07 +IOBUF PORT "gpio[7]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[7]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[8]" SITE "M9"; # HUB_08 - N1 is used by QSPI0_SCLK +IOBUF PORT "gpio[8]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[8]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[9]" SITE "P2"; # HUB_09 +IOBUF PORT "gpio[9]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[9]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[10]" SITE "L3"; # HUB_10 +IOBUF PORT "gpio[10]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[10]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[11]" SITE "M3"; # HUB_11 +IOBUF PORT "gpio[11]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[11]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[12]" SITE "P1"; # HUB_12 +IOBUF PORT "gpio[12]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[12]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[13]" SITE "R1"; # HUB_13 +IOBUF PORT "gpio[13]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[13]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[14]" SITE "M4"; # HUB_14 +IOBUF PORT "gpio[14]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[14]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "gpio[15]" SITE "N3"; # HUB_15 +IOBUF PORT "gpio[15]" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio[15]" PULLMODE=NONE DRIVE=16; +LOCATE COMP "uart_debug_txd" SITE "E12"; # UART_DEBUG_TXD +IOBUF PORT "uart_debug_txd" IO_TYPE=LVCMOS33; +LOCATE COMP "uart_debug_rxd" SITE "D12"; # UART_DEBUG_RXD +IOBUF PORT "uart_debug_rxd" IO_TYPE=LVCMOS33; +LOCATE COMP "rst_n" SITE "R8"; # FPGA_RESET +IOBUF PORT "rst_n" IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "rs485_txd" SITE "A8"; # RS485_DI +IOBUF PORT "rs485_txd" IO_TYPE=LVCMOS33; +LOCATE COMP "rs485_rxd" SITE "A7"; # RS485_RO +IOBUF PORT "rs485_rxd" IO_TYPE=LVCMOS33; +LOCATE COMP "rs485_de" SITE "C7"; # RS485_DE +IOBUF PORT "rs485_de" IO_TYPE=LVCMOS33; +LOCATE COMP "i2c_sda" SITE "P7"; # EEPROM_I2C_SDA +IOBUF PORT "i2c_sda" IO_TYPE=LVCMOS33 DRIVE=8; +IOBUF PORT "i2c_sda" PULLMODE=UP; +LOCATE COMP "i2c_scl" SITE "R7"; # EEPROM_I2C_SCL +IOBUF PORT "i2c_scl" IO_TYPE=LVCMOS33; +IOBUF PORT "i2c_scl" PULLMODE=UP; +LOCATE COMP "eeprom_wp" SITE "R6"; # EEPROM_WP +IOBUF PORT "eeprom_wp" IO_TYPE=LVCMOS33; +IOBUF PORT "eeprom_wp" PULLMODE=UP; +LOCATE COMP "config" SITE "T6"; # EEPROM_RESET +IOBUF PORT "config" IO_TYPE=LVCMOS33; +IOBUF PORT "config" PULLMODE=UP; + + +LOCATE COMP "lan_mdc" SITE "A2"; # LAN_MDC +IOBUF PORT "lan_mdc" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_mdc" PULLMODE=NONE; +LOCATE COMP "lan_nint" SITE "B3"; # LAN_nINT +IOBUF PORT "lan_nint" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_nint" PULLMODE=NONE; +LOCATE COMP "lan_nrst" SITE "A3"; # LAN_nRST +IOBUF PORT "lan_nrst" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_nrst" PULLMODE=NONE; +LOCATE COMP "lan_txen" SITE "A4"; # LAN_TXEN +IOBUF PORT "lan_txen" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_txen" PULLMODE=NONE; +LOCATE COMP "lan_txclk" SITE "B4"; # LAN_TXCLK +IOBUF PORT "lan_txclk" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_txclk" PULLMODE=NONE; +# FREQUENCY PORT "lan_txclk" 25.0 MHz; +LOCATE COMP "lan_txd0" SITE "B5"; # LAN_TXD0 +IOBUF PORT "lan_txd0" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_txd0" PULLMODE=NONE; +LOCATE COMP "lan_txd1" SITE "A5"; # LAN_TXD1 +IOBUF PORT "lan_txd1" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_txd1" PULLMODE=NONE; +LOCATE COMP "lan_txd2" SITE "B6"; # LAN_TXD2 +IOBUF PORT "lan_txd2" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_txd2" PULLMODE=NONE; +LOCATE COMP "lan_txd3" SITE "A6"; # LAN_TXD3 +IOBUF PORT "lan_txd3" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_txd3" PULLMODE=NONE; +LOCATE COMP "lan_rxd0" SITE "D1"; # LAN_RXD0 +IOBUF PORT "lan_rxd0" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxd0" PULLMODE=NONE; +LOCATE COMP "lan_rxd1" SITE "E2"; # LAN_RXD1 +IOBUF PORT "lan_rxd1" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxd1" PULLMODE=NONE; +LOCATE COMP "lan_rxd2" SITE "E1"; # LAN_RXD2 +IOBUF PORT "lan_rxd2" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxd2" PULLMODE=NONE; +LOCATE COMP "lan_rxd3" SITE "F2"; # LAN_RXD3 +IOBUF PORT "lan_rxd3" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxd3" PULLMODE=NONE; +LOCATE COMP "lan_mdio" SITE "B1"; # LAN_MDIO +IOBUF PORT "lan_mdio" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_mdio" PULLMODE=NONE; +LOCATE COMP "lan_col" SITE "B2"; # LAN_COL +IOBUF PORT "lan_col" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_col" PULLMODE=NONE; +LOCATE COMP "lan_crs" SITE "C1"; # LAN_CRS +IOBUF PORT "lan_crs" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_crs" PULLMODE=NONE; +LOCATE COMP "lan_rxer" SITE "C2"; # LAN_RXER +IOBUF PORT "lan_rxer" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxer" PULLMODE=NONE; +LOCATE COMP "lan_rxdv" SITE "B7"; # LAN_RXDV +IOBUF PORT "lan_rxdv" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxdv" PULLMODE=NONE; +LOCATE COMP "lan_rxclk" SITE "F1"; # LAN_RXCLK +IOBUF PORT "lan_rxclk" IO_TYPE=LVCMOS33; +IOBUF PORT "lan_rxclk" PULLMODE=NONE; +# FREQUENCY PORT "lan_rxclk" 25.0 MHz; + +LOCATE COMP "sram_cs" SITE "H15"; # SRAM #CS +IOBUF PORT "sram_cs" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_we" SITE "K14"; # SRAM #WE +IOBUF PORT "sram_we" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_oe" SITE "J14"; # SRAM #OE +IOBUF PORT "sram_oe" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_bhe" SITE "J16"; # SRAM #BHE +IOBUF PORT "sram_bhe" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_ble" SITE "J15"; # SRAM #BLE +IOBUF PORT "sram_ble" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[0]" SITE "L16"; # SRAM D00 +IOBUF PORT "sram_dat[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[1]" SITE "L15"; # SRAM D01 +IOBUF PORT "sram_dat[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[2]" SITE "M16"; # SRAM D02 +IOBUF PORT "sram_dat[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[3]" SITE "M15"; # SRAM D03 +IOBUF PORT "sram_dat[3]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[4]" SITE "K13"; # SRAM D04 +IOBUF PORT "sram_dat[4]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[5]" SITE "K12"; # SRAM D05 +IOBUF PORT "sram_dat[5]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[6]" SITE "L13"; # SRAM D06 +IOBUF PORT "sram_dat[6]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[7]" SITE "L12"; # SRAM D07 +IOBUF PORT "sram_dat[7]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[8]" SITE "N16"; # SRAM D08 +IOBUF PORT "sram_dat[8]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[9]" SITE "P15"; # SRAM D09 +IOBUF PORT "sram_dat[9]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[10]" SITE "L14"; # SRAM D10 +IOBUF PORT "sram_dat[10]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[11]" SITE "M14"; # SRAM D11 +IOBUF PORT "sram_dat[11]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[12]" SITE "P16"; # SRAM D12 +IOBUF PORT "sram_dat[12]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[13]" SITE "R16"; # SRAM D13 +IOBUF PORT "sram_dat[13]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[14]" SITE "M13"; # SRAM D14 +IOBUF PORT "sram_dat[14]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_dat[15]" SITE "N14"; # SRAM D15 +IOBUF PORT "sram_dat[15]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[0]" SITE "N13"; # SRAM A00 +IOBUF PORT "sram_addr[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[1]" SITE "P14"; # SRAM A01 +IOBUF PORT "sram_addr[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[2]" SITE "R15"; # SRAM A02 +IOBUF PORT "sram_addr[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[3]" SITE "T15"; # SRAM A03 +IOBUF PORT "sram_addr[3]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[4]" SITE "P13"; # SRAM A04 +IOBUF PORT "sram_addr[4]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[5]" SITE "R14"; # SRAM A05 +IOBUF PORT "sram_addr[5]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[6]" SITE "R13"; # SRAM A06 +IOBUF PORT "sram_addr[6]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[7]" SITE "T14"; # SRAM A07 +IOBUF PORT "sram_addr[7]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[8]" SITE "R12"; # SRAM A08 +IOBUF PORT "sram_addr[8]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[9]" SITE "T13"; # SRAM A09 +IOBUF PORT "sram_addr[9]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[10]" SITE "M12"; # SRAM A10 +IOBUF PORT "sram_addr[10]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[11]" SITE "N12"; # SRAM A11 +IOBUF PORT "sram_addr[11]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[12]" SITE "M11"; # SRAM A12 +IOBUF PORT "sram_addr[12]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[13]" SITE "N11"; # SRAM A13 +IOBUF PORT "sram_addr[13]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[14]" SITE "P11"; # SRAM A14 +IOBUF PORT "sram_addr[14]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[15]" SITE "P12"; # SRAM A15 +IOBUF PORT "sram_addr[15]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[16]" SITE "K16"; # SRAM A16 +IOBUF PORT "sram_addr[16]" IO_TYPE=LVCMOS33; +LOCATE COMP "sram_addr[17]" SITE "K15"; # SRAM A17 +IOBUF PORT "sram_addr[17]" IO_TYPE=LVCMOS33; + +LOCATE COMP "spiAudioDAC_sclk" SITE "C16"; # DAC SPI SCLK +IOBUF PORT "spiAudioDAC_sclk" IO_TYPE=LVCMOS33; +LOCATE COMP "spiAudioDAC_miso" SITE "B16"; # DAC SPI MISO +IOBUF PORT "spiAudioDAC_miso" IO_TYPE=LVCMOS33; +LOCATE COMP "spiAudioDAC_mosi" SITE "B15"; # DAC SPI MOSI +IOBUF PORT "spiAudioDAC_mosi" IO_TYPE=LVCMOS33; +LOCATE COMP "spiAudioDAC_ss[0]" SITE "C15"; # DAC SPI CSn +IOBUF PORT "spiAudioDAC_ss[0]" IO_TYPE=LVCMOS33; + +LOCATE COMP "spi0_sclk" SITE "R5"; # SPI0 SCLK/GPIO_24 +IOBUF PORT "spi0_sclk" IO_TYPE=LVCMOS33; +LOCATE COMP "spi0_miso" SITE "T4"; # SPI0 MISO/GPIO_25 +IOBUF PORT "spi0_miso" IO_TYPE=LVCMOS33; +LOCATE COMP "spi0_mosi" SITE "M5"; # SPI0 MOSI/GPIO_26 +IOBUF PORT "spi0_mosi" IO_TYPE=LVCMOS33; +LOCATE COMP "spi0_ss[0]" SITE "N5"; # SPI0 CSn/GPIO_27 +IOBUF PORT "spi0_ss[0]" IO_TYPE=LVCMOS33; + +LOCATE COMP "hdmi_tmds_p[0]" SITE "A11"; +IOBUF PORT "hdmi_tmds_p[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_p[1]" SITE "D11"; +IOBUF PORT "hdmi_tmds_p[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_p[2]" SITE "B11"; +IOBUF PORT "hdmi_tmds_p[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_n[0]" SITE "A12"; +IOBUF PORT "hdmi_tmds_n[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_n[1]" SITE "E11"; +IOBUF PORT "hdmi_tmds_n[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_n[2]" SITE "C11"; +IOBUF PORT "hdmi_tmds_n[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_clk_p" SITE "B12"; +IOBUF PORT "hdmi_tmds_clk_p" IO_TYPE=LVCMOS33; +LOCATE COMP "hdmi_tmds_clk_n" SITE "C12"; +IOBUF PORT "hdmi_tmds_clk_n" IO_TYPE=LVCMOS33; + +LOCATE COMP "qspi0_cs" SITE "N8"; +IOBUF PORT "qspi0_cs" IO_TYPE=LVCMOS33; +LOCATE COMP "qspi0_sclk" SITE "N1"; // GPIO_08, should be M9 +IOBUF PORT "qspi0_sclk" IO_TYPE=LVCMOS33; +LOCATE COMP "qspi0_io0" SITE "T8"; +IOBUF PORT "qspi0_io0" IO_TYPE=LVCMOS33; +LOCATE COMP "qspi0_io1" SITE "T7"; +IOBUF PORT "qspi0_io1" IO_TYPE=LVCMOS33; +LOCATE COMP "qspi0_io2" SITE "M7"; +IOBUF PORT "qspi0_io2" IO_TYPE=LVCMOS33; +LOCATE COMP "qspi0_io3" SITE "N7"; +IOBUF PORT "qspi0_io3" IO_TYPE=LVCMOS33; + diff --git a/uart_receiver/tb.v b/uart_receiver/tb.v new file mode 100644 index 0000000..9767e03 --- /dev/null +++ b/uart_receiver/tb.v @@ -0,0 +1,131 @@ +`timescale 1ns / 1ps + +module uart_rx_tb; + +// Parameters +parameter CLK_PERIOD = 40; // 25 MHz = 40 ns period +parameter BAUD_RATE = 115200; +parameter BIT_PERIOD = 1000000000/BAUD_RATE; // ~8680 ns for 115200 baud + +// Inputs +reg clk; +reg rst; +reg rx; +reg valid; +reg [1:0] stop_bits; +reg parity_en; +reg parity_type; + +// Outputs +wire parity_valid; +wire ready; +wire [7:0] rx_data; + +// Instantiate the UART receiver +uart_rx uut ( + .rst(rst), + .clk(clk), + .rx(rx), + .baudrate(BAUD_RATE), + .valid(valid), + .stop_bits(stop_bits), + .parity_en(parity_en), + .parity_type(parity_type), + .parity_valid(parity_valid), + .ready(ready), + .output_rx_data(rx_data) +); + +// Clock generation +always begin + clk = 1'b0; + #(CLK_PERIOD/2); + clk = 1'b1; + #(CLK_PERIOD/2); +end + +// Task for sending one byte +task send_byte; + input [7:0] data; + integer i; + begin + // Start bit + rx = 1'b0; + #BIT_PERIOD; + + // Data bits (LSB first) + for (i = 0; i < 8; i = i + 1) begin + rx = data[i]; + #BIT_PERIOD; + end + + // Parity bit (Even) + rx = ^data; // XOR всех битов для Even parity + #BIT_PERIOD; + + // Stop bit + rx = 1'b1; + #BIT_PERIOD; + end +endtask + +// Test stimulus +initial begin + // Initialize inputs + rst = 1'b1; + rx = 1'b1; // Idle state + valid = 1'b1; + stop_bits = 2'b00; // 1 stop bit + parity_en = 1'b0; // Enable parity + parity_type = 1'b0; // Even parity + + // Reset the system + #100; + rst = 1'b0; + #100; + + // Test case 1: Send 'A' (0x41) + $display("Sending 'A' (0x41)"); + send_byte(8'h41); + + // Verify first byte + #(BIT_PERIOD*2); // Small delay + if (rx_data === 8'h41 && parity_valid === 1'b1) begin + $display("Test 1 PASSED: Received 0x41 with valid parity"); + end else begin + $display("Test 1 FAILED"); + end + + // Wait until ready is asserted + wait(ready == 1'b1); + #(BIT_PERIOD*4); + + // Test case 2: Send 'B' (0x42) + $display("Sending 'B' (0x42)"); + send_byte(8'h42); + + // Verify second byte + #(BIT_PERIOD*2); + if (rx_data === 8'h42 && parity_valid === 1'b1) begin + $display("Test 2 PASSED: Received 0x42 with valid parity"); + end else begin + $display("Test 2 FAILED"); + end + + // Additional delay for observation + #(BIT_PERIOD*10); + $finish; +end + +// Monitor +initial begin + $monitor("Time = %t ns: state = %d, rx_data = %h, parity_valid = %b, ready = %b", + $time, uut.state, rx_data, parity_valid, ready); +end + +initial begin + $dumpfile("uart_rx_tb.vcd"); // Создаем файл для сохранения波形 + $dumpvars(0, uart_rx_tb); // Записываем все сигналы тестбенча +end + +endmodule diff --git a/uart_receiver/top.v b/uart_receiver/top.v new file mode 100644 index 0000000..e0692b9 --- /dev/null +++ b/uart_receiver/top.v @@ -0,0 +1,47 @@ +module top ( + input wire clk25, + input wire uart_debug_rxd, + input wire [0:0] key, + output reg [3:0] led +); + +wire [31:0] baudrate = 32'd115200; +wire parity_valid; +wire ready; + +wire rst; +assign rst = key[0]; +reg [7:0] rx_data; + +always @(posedge clk25) begin + + if (rx_data == 8'h36) led[3:0] = 4'b0001; + + else if (rx_data == 8'h32) led[3:0] = 4'b0010; + + else if (rx_data == 8'h38) led[3:0] = 4'b0100; + + else if (rx_data == 8'h34) led[3:0] = 4'b1000; + + else led[3:0] = 4'b0000; + +end + +uart_rx uart_main ( + .rst(rst), + .clk(clk25), + .rx(uart_debug_rxd), + .baudrate(baudrate), + .valid(1'b1), + .stop_bits(2'd0), + .parity_en(1'b1), + .parity_type(1'b0), + .parity_valid(parity_valid), + .ready(ready), + .rx_data(rx_data) +); + + +endmodule + +endmodule diff --git a/uart_receiver/top.v~ b/uart_receiver/top.v~ new file mode 100644 index 0000000..723e579 --- /dev/null +++ b/uart_receiver/top.v~ @@ -0,0 +1,158 @@ +module uart_rx ( + input wire rst, // Reset + input wire clk, // 25 MHz clocki + input wire rx, // uart input signal + input wire [31:0] baudrate, // baudrate selector + input wire valid, // Valid signal + input wire [1:0] stop_bits, // 0 - 1 stop bit, 1 - 2 stop bits, 2 - 1,5 stop bits + input wire parity_en, // Enable pariry_type (1-Enable) + input wire parity_type, // 0 - Even parity, 1 - Odd parity + output wire parity_valid, // Parity valid flag + output reg ready, // Ready signal + output reg [7:0] rx_data +); + +//=============================================== +// Internal signals +//=============================================== + +reg [31:0] baud_counter; +reg [3:0] bit_counter; +reg [2:0] state; +reg parity_bit; +reg parity_calc; +reg rx_prev; + + +//=============================================== +// State parameters +//=============================================== + +localparam [2:0] + IDLE = 3'd0, // Waiting for command + START_BIT = 3'd1, // Start bit receive + DATA_BITS = 3'd2, + PARITY_BIT = 3'd3, // Parity + STOP_BIT = 3'd4; // Stop bit + +//=============================================== +// Baudrate calculation +//=============================================== + +wire [31:0] baud_limit; +wire [31:0] half_baud_limit; +assign baud_limit = (25000000/baudrate) - 1; +assign half_baud_limit = baud_limit / 2; + +//=============================================== +// Main state machine +//=============================================== + +always @(posedge clk or posedge rst) begin + if (rst) begin + state <= IDLE; + bit_counter <= 0; + baud_counter <= 0; + rx_data <= 0; + ready <= 1'b1; + parity_bit <= 1'b0; + parity_calc <= 1'b0; + rx_prev <= 1'b1; + end else begin + + rx_prev <= rx; + + case (state) + IDLE: begin + ready <= 1'b1; + rx_data <= 0; + if (valid && rx_prev && !rx) begin // Falling edge detected + state <= START_BIT; + baud_counter <= 0; + parity_calc <= 1'b0; + ready <= 1'b0; + end + end + + START_BIT: begin + if (baud_counter == half_baud_limit) begin + if (valid && !rx) begin + state <= DATA_BITS; + baud_counter <= 0; + bit_counter <= 0; + end else begin + state <= IDLE; + end + end else begin + baud_counter <= baud_counter +1; + end + end + + DATA_BITS: begin + if (baud_counter == baud_limit) begin + baud_counter <= 0; + if (valid) begin + rx_data[bit_counter] <= rx; + parity_calc <= parity_calc ^ rx; + end + + if (bit_counter == 7) begin + if (parity_en) begin + state <= PARITY_BIT; + end else begin + state <= STOP_BIT; + end + end else begin + bit_counter <= bit_counter + 1; + end + end else begin + baud_counter <= baud_counter + 1; + end + end + + PARITY_BIT: begin + if (baud_counter == baud_limit) begin + baud_counter <= 0; + if (valid) parity_bit <= rx; + state <= STOP_BIT; + end else begin + baud_counter <= baud_counter + 1; + end + end + + STOP_BIT: begin + if (stop_bits == 2'd0) begin + if (baud_counter == baud_limit) begin + baud_counter <= 0; + state <= IDLE; + ready <= 1'b1; + end else begin + baud_counter <= baud_counter +1; + end + + end else if (stop_bits == 2'd1) begin + if (baud_counter == (baud_limit*2)) begin + baud_counter <= 0; + state <= IDLE; + ready <= 1'b1; + end else begin + baud_counter <= baud_counter +1; + end + + end else if (stop_bits == 2'd2) begin + if (baud_counter == (baud_limit + half_baud_limit)) begin + baud_counter <= 0; + state <= IDLE; + ready <= 1'b1; + end else begin + baud_counter <= baud_counter +1; + end + end + end + endcase + end +end + +assign parity_valid = parity_en ? ((parity_type == 0) ? (parity_calc == parity_bit) : (parity_calc != parity_bit)) : 1'b1; + +endmodule diff --git a/uart_receiver/uart_rx.v b/uart_receiver/uart_rx.v new file mode 100644 index 0000000..723e579 --- /dev/null +++ b/uart_receiver/uart_rx.v @@ -0,0 +1,158 @@ +module uart_rx ( + input wire rst, // Reset + input wire clk, // 25 MHz clocki + input wire rx, // uart input signal + input wire [31:0] baudrate, // baudrate selector + input wire valid, // Valid signal + input wire [1:0] stop_bits, // 0 - 1 stop bit, 1 - 2 stop bits, 2 - 1,5 stop bits + input wire parity_en, // Enable pariry_type (1-Enable) + input wire parity_type, // 0 - Even parity, 1 - Odd parity + output wire parity_valid, // Parity valid flag + output reg ready, // Ready signal + output reg [7:0] rx_data +); + +//=============================================== +// Internal signals +//=============================================== + +reg [31:0] baud_counter; +reg [3:0] bit_counter; +reg [2:0] state; +reg parity_bit; +reg parity_calc; +reg rx_prev; + + +//=============================================== +// State parameters +//=============================================== + +localparam [2:0] + IDLE = 3'd0, // Waiting for command + START_BIT = 3'd1, // Start bit receive + DATA_BITS = 3'd2, + PARITY_BIT = 3'd3, // Parity + STOP_BIT = 3'd4; // Stop bit + +//=============================================== +// Baudrate calculation +//=============================================== + +wire [31:0] baud_limit; +wire [31:0] half_baud_limit; +assign baud_limit = (25000000/baudrate) - 1; +assign half_baud_limit = baud_limit / 2; + +//=============================================== +// Main state machine +//=============================================== + +always @(posedge clk or posedge rst) begin + if (rst) begin + state <= IDLE; + bit_counter <= 0; + baud_counter <= 0; + rx_data <= 0; + ready <= 1'b1; + parity_bit <= 1'b0; + parity_calc <= 1'b0; + rx_prev <= 1'b1; + end else begin + + rx_prev <= rx; + + case (state) + IDLE: begin + ready <= 1'b1; + rx_data <= 0; + if (valid && rx_prev && !rx) begin // Falling edge detected + state <= START_BIT; + baud_counter <= 0; + parity_calc <= 1'b0; + ready <= 1'b0; + end + end + + START_BIT: begin + if (baud_counter == half_baud_limit) begin + if (valid && !rx) begin + state <= DATA_BITS; + baud_counter <= 0; + bit_counter <= 0; + end else begin + state <= IDLE; + end + end else begin + baud_counter <= baud_counter +1; + end + end + + DATA_BITS: begin + if (baud_counter == baud_limit) begin + baud_counter <= 0; + if (valid) begin + rx_data[bit_counter] <= rx; + parity_calc <= parity_calc ^ rx; + end + + if (bit_counter == 7) begin + if (parity_en) begin + state <= PARITY_BIT; + end else begin + state <= STOP_BIT; + end + end else begin + bit_counter <= bit_counter + 1; + end + end else begin + baud_counter <= baud_counter + 1; + end + end + + PARITY_BIT: begin + if (baud_counter == baud_limit) begin + baud_counter <= 0; + if (valid) parity_bit <= rx; + state <= STOP_BIT; + end else begin + baud_counter <= baud_counter + 1; + end + end + + STOP_BIT: begin + if (stop_bits == 2'd0) begin + if (baud_counter == baud_limit) begin + baud_counter <= 0; + state <= IDLE; + ready <= 1'b1; + end else begin + baud_counter <= baud_counter +1; + end + + end else if (stop_bits == 2'd1) begin + if (baud_counter == (baud_limit*2)) begin + baud_counter <= 0; + state <= IDLE; + ready <= 1'b1; + end else begin + baud_counter <= baud_counter +1; + end + + end else if (stop_bits == 2'd2) begin + if (baud_counter == (baud_limit + half_baud_limit)) begin + baud_counter <= 0; + state <= IDLE; + ready <= 1'b1; + end else begin + baud_counter <= baud_counter +1; + end + end + end + endcase + end +end + +assign parity_valid = parity_en ? ((parity_type == 0) ? (parity_calc == parity_bit) : (parity_calc != parity_bit)) : 1'b1; + +endmodule From 0b386652130fc07ea61413419143c991c049f846 Mon Sep 17 00:00:00 2001 From: Verba Date: Tue, 13 May 2025 04:29:37 +0500 Subject: [PATCH 3/5] Delete uart_receiver/top.v~ --- uart_receiver/top.v~ | 158 ------------------------------------------- 1 file changed, 158 deletions(-) delete mode 100644 uart_receiver/top.v~ diff --git a/uart_receiver/top.v~ b/uart_receiver/top.v~ deleted file mode 100644 index 723e579..0000000 --- a/uart_receiver/top.v~ +++ /dev/null @@ -1,158 +0,0 @@ -module uart_rx ( - input wire rst, // Reset - input wire clk, // 25 MHz clocki - input wire rx, // uart input signal - input wire [31:0] baudrate, // baudrate selector - input wire valid, // Valid signal - input wire [1:0] stop_bits, // 0 - 1 stop bit, 1 - 2 stop bits, 2 - 1,5 stop bits - input wire parity_en, // Enable pariry_type (1-Enable) - input wire parity_type, // 0 - Even parity, 1 - Odd parity - output wire parity_valid, // Parity valid flag - output reg ready, // Ready signal - output reg [7:0] rx_data -); - -//=============================================== -// Internal signals -//=============================================== - -reg [31:0] baud_counter; -reg [3:0] bit_counter; -reg [2:0] state; -reg parity_bit; -reg parity_calc; -reg rx_prev; - - -//=============================================== -// State parameters -//=============================================== - -localparam [2:0] - IDLE = 3'd0, // Waiting for command - START_BIT = 3'd1, // Start bit receive - DATA_BITS = 3'd2, - PARITY_BIT = 3'd3, // Parity - STOP_BIT = 3'd4; // Stop bit - -//=============================================== -// Baudrate calculation -//=============================================== - -wire [31:0] baud_limit; -wire [31:0] half_baud_limit; -assign baud_limit = (25000000/baudrate) - 1; -assign half_baud_limit = baud_limit / 2; - -//=============================================== -// Main state machine -//=============================================== - -always @(posedge clk or posedge rst) begin - if (rst) begin - state <= IDLE; - bit_counter <= 0; - baud_counter <= 0; - rx_data <= 0; - ready <= 1'b1; - parity_bit <= 1'b0; - parity_calc <= 1'b0; - rx_prev <= 1'b1; - end else begin - - rx_prev <= rx; - - case (state) - IDLE: begin - ready <= 1'b1; - rx_data <= 0; - if (valid && rx_prev && !rx) begin // Falling edge detected - state <= START_BIT; - baud_counter <= 0; - parity_calc <= 1'b0; - ready <= 1'b0; - end - end - - START_BIT: begin - if (baud_counter == half_baud_limit) begin - if (valid && !rx) begin - state <= DATA_BITS; - baud_counter <= 0; - bit_counter <= 0; - end else begin - state <= IDLE; - end - end else begin - baud_counter <= baud_counter +1; - end - end - - DATA_BITS: begin - if (baud_counter == baud_limit) begin - baud_counter <= 0; - if (valid) begin - rx_data[bit_counter] <= rx; - parity_calc <= parity_calc ^ rx; - end - - if (bit_counter == 7) begin - if (parity_en) begin - state <= PARITY_BIT; - end else begin - state <= STOP_BIT; - end - end else begin - bit_counter <= bit_counter + 1; - end - end else begin - baud_counter <= baud_counter + 1; - end - end - - PARITY_BIT: begin - if (baud_counter == baud_limit) begin - baud_counter <= 0; - if (valid) parity_bit <= rx; - state <= STOP_BIT; - end else begin - baud_counter <= baud_counter + 1; - end - end - - STOP_BIT: begin - if (stop_bits == 2'd0) begin - if (baud_counter == baud_limit) begin - baud_counter <= 0; - state <= IDLE; - ready <= 1'b1; - end else begin - baud_counter <= baud_counter +1; - end - - end else if (stop_bits == 2'd1) begin - if (baud_counter == (baud_limit*2)) begin - baud_counter <= 0; - state <= IDLE; - ready <= 1'b1; - end else begin - baud_counter <= baud_counter +1; - end - - end else if (stop_bits == 2'd2) begin - if (baud_counter == (baud_limit + half_baud_limit)) begin - baud_counter <= 0; - state <= IDLE; - ready <= 1'b1; - end else begin - baud_counter <= baud_counter +1; - end - end - end - endcase - end -end - -assign parity_valid = parity_en ? ((parity_type == 0) ? (parity_calc == parity_bit) : (parity_calc != parity_bit)) : 1'b1; - -endmodule From 55d0832217a7bd2b982c2d7d2e68fc29892f37c3 Mon Sep 17 00:00:00 2001 From: Verba Date: Tue, 13 May 2025 04:31:11 +0500 Subject: [PATCH 4/5] Update tb.v --- uart_receiver/tb.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uart_receiver/tb.v b/uart_receiver/tb.v index 9767e03..9162c8d 100644 --- a/uart_receiver/tb.v +++ b/uart_receiver/tb.v @@ -76,7 +76,7 @@ initial begin rx = 1'b1; // Idle state valid = 1'b1; stop_bits = 2'b00; // 1 stop bit - parity_en = 1'b0; // Enable parity + parity_en = 1'b1; // Enable parity parity_type = 1'b0; // Even parity // Reset the system From 68f9bb7a5e8cb43192449ebecd34375dcbc4018b Mon Sep 17 00:00:00 2001 From: Verba Date: Tue, 13 May 2025 04:38:43 +0500 Subject: [PATCH 5/5] Delete uart_transmitter directory --- uart_transmitter/Makefile | 101 ---------- uart_transmitter/karnix_cabga256.lpf | 286 --------------------------- uart_transmitter/top.v | 39 ---- uart_transmitter/uart_tx.v | 128 ------------ 4 files changed, 554 deletions(-) delete mode 100644 uart_transmitter/Makefile delete mode 100644 uart_transmitter/karnix_cabga256.lpf delete mode 100644 uart_transmitter/top.v delete mode 100644 uart_transmitter/uart_tx.v diff --git a/uart_transmitter/Makefile b/uart_transmitter/Makefile deleted file mode 100644 index 7ba528f..0000000 --- a/uart_transmitter/Makefile +++ /dev/null @@ -1,101 +0,0 @@ -NAME = ir_encoder -VERILOG += top.v -VERILOG += uart_tx.v -INC = ./ -LPF = karnix_cabga256.lpf -DEVICE = 25k -PACKAGE = CABGA256 -FTDI_CHANNEL = 0 ### FT2232 has two channels, select 0 for channel A or 1 for channel B -# -FLASH_METHOD := flash -UPLOAD_METHOD := openloader - -.PHONY: clean -all: $(NAME).bit - -.PHONY: upload -upload: $(NAME).bit -ifeq ("$(UPLOAD_METHOD)", "ecpprog") - $(MAKE) upload_ecpprog -else -ifeq ("$(UPLOAD_METHOD)", "openloader") - $(MAKE) upload_openloader -else -ifeq ("$(UPLOAD_METHOD)", "") - echo "Upload method has not been chosen, set UPLOAD_METHOD env variable to 'ecpprog' or 'openloader'." -else - echo "Unsupported upload method: $(UPLOAD_METHOD)." -endif -endif -endif - -.PHONY: upload_openloader -upload_openloader: -ifeq ("$(FLASH_METHOD)", "flash") - openFPGALoader -v --ftdi-channel $(FTDI_CHANNEL) -f --reset $(NAME).bit -else - openFPGALoader -v --ftdi-channel $(FTDI_CHANNEL) $(NAME).bit -endif - -.PHONY: upload_ecpprog -upload_ecpprog: -ifeq ("$(FLASH_METHOD)", "flash") - ecpprog -I $(if $(filter $(FTDI_CHANNEL),0),A,B) -X $(NAME).bit -else - ecpprog -I $(if $(filter $(FTDI_CHANNEL),0),A,B) -S $(NAME).bit -endif - - - -fw: $(NAME).bit - -$(NAME).bit: $(LPF) $(VERILOG) - yosys -p "verilog_defaults -add -I$(subst :, -I,$(INC))" -p "read_verilog -sv $(VERILOG)" -p "synth_ecp5 -json $(NAME).json -top top" -l $(NAME).yosys.log - nextpnr-ecp5 --package $(PACKAGE) --$(DEVICE) --json $(NAME).json --textcfg $(NAME)_out.config --lpf $(LPF) --lpf-allow-unconstrained -l $(NAME).nextpnr.log - ecppack --compress --freq 38.8 --input $(NAME)_out.config --bit $(NAME).bit - $(MAKE) check - - -.PHONY: graph -graph: $(LPF) $(VERILOG) - yosys -p "verilog_defaults -add -I$(subst :, -I,$(INC))" -p "read_verilog -sv +/ecp5/cells_bb.v" -p "hierarchy -check -top top" -p "proc; opt; fsm; memory; opt" -p "synth_ecp5 -noabc9 -top top -json $(NAME).json" -p "show -prefix $(NAME) -notitle -colors 2 -width -format dot" $(VERILOG) | tee $(NAME).yosys.log - @if [ -f "`which dot`" ]; then \ - echo "Generating PDFs with schematics..."; \ - dot -Tpdf -O $(NAME).dot; \ - else \ - echo "Note: 'dot' utility is not installed, PDF won't be generated!"; \ - fi - netlistsvg -o $(NAME).svg $(NAME).json - #@echo "Generating SVGs with routing and placement..." - #nextpnr-ecp5 --package $(PACKAGE) --$(DEVICE) --json $(NAME).json --textcfg $(NAME)_out.config --lpf $(LPF) --lpf-allow-unconstrained --placed-svg $(NAME)-placed.svg --routed-svg $(NAME)-routed.svg | tee $(NAME).nextpnr.log - $(MAKE) check - @if [ -f "`which xdot`" ]; then \ - xdot $(NAME).dot; \ - else \ - echo "xdot utility is not installed, cannot show you DOT file:"; \ - ls -al $(NAME).dot; \ - fi - @if [ -f "`which firefox`" ]; then \ - firefox $(NAME).svg $(NAME)-placed.svg $(NAME)-routed.svg $(NAME).*pdf; \ - else \ - echo "Firefox is not installed, cannot show you SVG and PDF files:"; \ - ls -al $(NAME).svg $(NAME)-placed.svg $(NAME)-routed.svg $(NAME).*pdf; \ - fi - - -.PHONY: sim -sim: $(VERILOG) $(NAME)_tb.v $(shell yosys-config --datdir)/ice40/cells_sim.v - iverilog $^ -o $(NAME)_tb.out - ./$(NAME)_tb.out - gtkwave $(NAME)_tb.vcd $(NAME)_tb.gtkw & - -check: - @echo "Checking for warnings..." - @(grep Warn $(NAME).yosys.log $(NAME).nextpnr.log; echo) - -.PHONY: clean -clean: - rm -f *.bit *.txt *.log *.json .blif *.out *.svg *.dot *.pdf *out.config *.vcd - - - diff --git a/uart_transmitter/karnix_cabga256.lpf b/uart_transmitter/karnix_cabga256.lpf deleted file mode 100644 index ccb74a6..0000000 --- a/uart_transmitter/karnix_cabga256.lpf +++ /dev/null @@ -1,286 +0,0 @@ -BLOCK RESETPATHS; -BLOCK ASYNCPATHS; - -FREQUENCY PORT "clk25" 25.0 MHz; -LOCATE COMP "clk25" SITE "B9"; -IOBUF PORT "clk25" IO_TYPE=LVCMOS33; - -LOCATE COMP "key[0]" SITE "B13"; -IOBUF PORT "key[0]" IO_TYPE=LVCMOS33; -LOCATE COMP "key[1]" SITE "C13"; -IOBUF PORT "key[1]" IO_TYPE=LVCMOS33; -LOCATE COMP "key[2]" SITE "D13"; -IOBUF PORT "key[2]" IO_TYPE=LVCMOS33; -LOCATE COMP "key[3]" SITE "E13"; -IOBUF PORT "key[3]" IO_TYPE=LVCMOS33; - -LOCATE COMP "led[0]" SITE "A13"; # LED0 -IOBUF PORT "led[0]" IO_TYPE=LVCMOS33; -LOCATE COMP "led[1]" SITE "A14"; # LED1 -IOBUF PORT "led[1]" IO_TYPE=LVCMOS33; -LOCATE COMP "led[2]" SITE "A15"; # LED2 -IOBUF PORT "led[2]" IO_TYPE=LVCMOS33; -LOCATE COMP "led[3]" SITE "B14"; # LED3 -IOBUF PORT "led[3]" IO_TYPE=LVCMOS33; - -LOCATE COMP "gpio[0]" SITE "L1"; # HUB_00 -IOBUF PORT "gpio[0]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[0]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[1]" SITE "L2"; # HUB_01 -IOBUF PORT "gpio[1]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[1]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[2]" SITE "M1"; # HUB_02 -IOBUF PORT "gpio[2]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[2]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[3]" SITE "M2"; # HUB_03 -IOBUF PORT "gpio[3]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[3]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[4]" SITE "K4"; # HUB_04 -IOBUF PORT "gpio[4]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[4]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[5]" SITE "K5"; # HUB_05 -IOBUF PORT "gpio[5]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[5]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[6]" SITE "L4"; # HUB_06 -IOBUF PORT "gpio[6]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[6]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[7]" SITE "L5"; # HUB_07 -IOBUF PORT "gpio[7]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[7]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[8]" SITE "M9"; # HUB_08 - N1 is used by QSPI0_SCLK -IOBUF PORT "gpio[8]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[8]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[9]" SITE "P2"; # HUB_09 -IOBUF PORT "gpio[9]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[9]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[10]" SITE "L3"; # HUB_10 -IOBUF PORT "gpio[10]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[10]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[11]" SITE "M3"; # HUB_11 -IOBUF PORT "gpio[11]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[11]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[12]" SITE "P1"; # HUB_12 -IOBUF PORT "gpio[12]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[12]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[13]" SITE "R1"; # HUB_13 -IOBUF PORT "gpio[13]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[13]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[14]" SITE "M4"; # HUB_14 -IOBUF PORT "gpio[14]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[14]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "gpio[15]" SITE "N3"; # HUB_15 -IOBUF PORT "gpio[15]" IO_TYPE=LVCMOS33; -IOBUF PORT "gpio[15]" PULLMODE=NONE DRIVE=16; -LOCATE COMP "uart_debug_txd" SITE "E12"; # UART_DEBUG_TXD -IOBUF PORT "uart_debug_txd" IO_TYPE=LVCMOS33; -LOCATE COMP "uart_debug_rxd" SITE "D12"; # UART_DEBUG_RXD -IOBUF PORT "uart_debug_rxd" IO_TYPE=LVCMOS33; -LOCATE COMP "rst_n" SITE "R8"; # FPGA_RESET -IOBUF PORT "rst_n" IO_TYPE=LVCMOS33 DRIVE=4; -LOCATE COMP "rs485_txd" SITE "A8"; # RS485_DI -IOBUF PORT "rs485_txd" IO_TYPE=LVCMOS33; -LOCATE COMP "rs485_rxd" SITE "A7"; # RS485_RO -IOBUF PORT "rs485_rxd" IO_TYPE=LVCMOS33; -LOCATE COMP "rs485_de" SITE "C7"; # RS485_DE -IOBUF PORT "rs485_de" IO_TYPE=LVCMOS33; -LOCATE COMP "i2c_sda" SITE "P7"; # EEPROM_I2C_SDA -IOBUF PORT "i2c_sda" IO_TYPE=LVCMOS33 DRIVE=8; -IOBUF PORT "i2c_sda" PULLMODE=UP; -LOCATE COMP "i2c_scl" SITE "R7"; # EEPROM_I2C_SCL -IOBUF PORT "i2c_scl" IO_TYPE=LVCMOS33; -IOBUF PORT "i2c_scl" PULLMODE=UP; -LOCATE COMP "eeprom_wp" SITE "R6"; # EEPROM_WP -IOBUF PORT "eeprom_wp" IO_TYPE=LVCMOS33; -IOBUF PORT "eeprom_wp" PULLMODE=UP; -LOCATE COMP "config" SITE "T6"; # EEPROM_RESET -IOBUF PORT "config" IO_TYPE=LVCMOS33; -IOBUF PORT "config" PULLMODE=UP; - - -LOCATE COMP "lan_mdc" SITE "A2"; # LAN_MDC -IOBUF PORT "lan_mdc" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_mdc" PULLMODE=NONE; -LOCATE COMP "lan_nint" SITE "B3"; # LAN_nINT -IOBUF PORT "lan_nint" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_nint" PULLMODE=NONE; -LOCATE COMP "lan_nrst" SITE "A3"; # LAN_nRST -IOBUF PORT "lan_nrst" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_nrst" PULLMODE=NONE; -LOCATE COMP "lan_txen" SITE "A4"; # LAN_TXEN -IOBUF PORT "lan_txen" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_txen" PULLMODE=NONE; -LOCATE COMP "lan_txclk" SITE "B4"; # LAN_TXCLK -IOBUF PORT "lan_txclk" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_txclk" PULLMODE=NONE; -# FREQUENCY PORT "lan_txclk" 25.0 MHz; -LOCATE COMP "lan_txd0" SITE "B5"; # LAN_TXD0 -IOBUF PORT "lan_txd0" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_txd0" PULLMODE=NONE; -LOCATE COMP "lan_txd1" SITE "A5"; # LAN_TXD1 -IOBUF PORT "lan_txd1" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_txd1" PULLMODE=NONE; -LOCATE COMP "lan_txd2" SITE "B6"; # LAN_TXD2 -IOBUF PORT "lan_txd2" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_txd2" PULLMODE=NONE; -LOCATE COMP "lan_txd3" SITE "A6"; # LAN_TXD3 -IOBUF PORT "lan_txd3" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_txd3" PULLMODE=NONE; -LOCATE COMP "lan_rxd0" SITE "D1"; # LAN_RXD0 -IOBUF PORT "lan_rxd0" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_rxd0" PULLMODE=NONE; -LOCATE COMP "lan_rxd1" SITE "E2"; # LAN_RXD1 -IOBUF PORT "lan_rxd1" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_rxd1" PULLMODE=NONE; -LOCATE COMP "lan_rxd2" SITE "E1"; # LAN_RXD2 -IOBUF PORT "lan_rxd2" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_rxd2" PULLMODE=NONE; -LOCATE COMP "lan_rxd3" SITE "F2"; # LAN_RXD3 -IOBUF PORT "lan_rxd3" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_rxd3" PULLMODE=NONE; -LOCATE COMP "lan_mdio" SITE "B1"; # LAN_MDIO -IOBUF PORT "lan_mdio" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_mdio" PULLMODE=NONE; -LOCATE COMP "lan_col" SITE "B2"; # LAN_COL -IOBUF PORT "lan_col" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_col" PULLMODE=NONE; -LOCATE COMP "lan_crs" SITE "C1"; # LAN_CRS -IOBUF PORT "lan_crs" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_crs" PULLMODE=NONE; -LOCATE COMP "lan_rxer" SITE "C2"; # LAN_RXER -IOBUF PORT "lan_rxer" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_rxer" PULLMODE=NONE; -LOCATE COMP "lan_rxdv" SITE "B7"; # LAN_RXDV -IOBUF PORT "lan_rxdv" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_rxdv" PULLMODE=NONE; -LOCATE COMP "lan_rxclk" SITE "F1"; # LAN_RXCLK -IOBUF PORT "lan_rxclk" IO_TYPE=LVCMOS33; -IOBUF PORT "lan_rxclk" PULLMODE=NONE; -# FREQUENCY PORT "lan_rxclk" 25.0 MHz; - -LOCATE COMP "sram_cs" SITE "H15"; # SRAM #CS -IOBUF PORT "sram_cs" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_we" SITE "K14"; # SRAM #WE -IOBUF PORT "sram_we" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_oe" SITE "J14"; # SRAM #OE -IOBUF PORT "sram_oe" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_bhe" SITE "J16"; # SRAM #BHE -IOBUF PORT "sram_bhe" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_ble" SITE "J15"; # SRAM #BLE -IOBUF PORT "sram_ble" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[0]" SITE "L16"; # SRAM D00 -IOBUF PORT "sram_dat[0]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[1]" SITE "L15"; # SRAM D01 -IOBUF PORT "sram_dat[1]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[2]" SITE "M16"; # SRAM D02 -IOBUF PORT "sram_dat[2]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[3]" SITE "M15"; # SRAM D03 -IOBUF PORT "sram_dat[3]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[4]" SITE "K13"; # SRAM D04 -IOBUF PORT "sram_dat[4]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[5]" SITE "K12"; # SRAM D05 -IOBUF PORT "sram_dat[5]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[6]" SITE "L13"; # SRAM D06 -IOBUF PORT "sram_dat[6]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[7]" SITE "L12"; # SRAM D07 -IOBUF PORT "sram_dat[7]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[8]" SITE "N16"; # SRAM D08 -IOBUF PORT "sram_dat[8]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[9]" SITE "P15"; # SRAM D09 -IOBUF PORT "sram_dat[9]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[10]" SITE "L14"; # SRAM D10 -IOBUF PORT "sram_dat[10]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[11]" SITE "M14"; # SRAM D11 -IOBUF PORT "sram_dat[11]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[12]" SITE "P16"; # SRAM D12 -IOBUF PORT "sram_dat[12]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[13]" SITE "R16"; # SRAM D13 -IOBUF PORT "sram_dat[13]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[14]" SITE "M13"; # SRAM D14 -IOBUF PORT "sram_dat[14]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_dat[15]" SITE "N14"; # SRAM D15 -IOBUF PORT "sram_dat[15]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[0]" SITE "N13"; # SRAM A00 -IOBUF PORT "sram_addr[0]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[1]" SITE "P14"; # SRAM A01 -IOBUF PORT "sram_addr[1]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[2]" SITE "R15"; # SRAM A02 -IOBUF PORT "sram_addr[2]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[3]" SITE "T15"; # SRAM A03 -IOBUF PORT "sram_addr[3]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[4]" SITE "P13"; # SRAM A04 -IOBUF PORT "sram_addr[4]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[5]" SITE "R14"; # SRAM A05 -IOBUF PORT "sram_addr[5]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[6]" SITE "R13"; # SRAM A06 -IOBUF PORT "sram_addr[6]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[7]" SITE "T14"; # SRAM A07 -IOBUF PORT "sram_addr[7]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[8]" SITE "R12"; # SRAM A08 -IOBUF PORT "sram_addr[8]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[9]" SITE "T13"; # SRAM A09 -IOBUF PORT "sram_addr[9]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[10]" SITE "M12"; # SRAM A10 -IOBUF PORT "sram_addr[10]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[11]" SITE "N12"; # SRAM A11 -IOBUF PORT "sram_addr[11]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[12]" SITE "M11"; # SRAM A12 -IOBUF PORT "sram_addr[12]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[13]" SITE "N11"; # SRAM A13 -IOBUF PORT "sram_addr[13]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[14]" SITE "P11"; # SRAM A14 -IOBUF PORT "sram_addr[14]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[15]" SITE "P12"; # SRAM A15 -IOBUF PORT "sram_addr[15]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[16]" SITE "K16"; # SRAM A16 -IOBUF PORT "sram_addr[16]" IO_TYPE=LVCMOS33; -LOCATE COMP "sram_addr[17]" SITE "K15"; # SRAM A17 -IOBUF PORT "sram_addr[17]" IO_TYPE=LVCMOS33; - -LOCATE COMP "spiAudioDAC_sclk" SITE "C16"; # DAC SPI SCLK -IOBUF PORT "spiAudioDAC_sclk" IO_TYPE=LVCMOS33; -LOCATE COMP "spiAudioDAC_miso" SITE "B16"; # DAC SPI MISO -IOBUF PORT "spiAudioDAC_miso" IO_TYPE=LVCMOS33; -LOCATE COMP "spiAudioDAC_mosi" SITE "B15"; # DAC SPI MOSI -IOBUF PORT "spiAudioDAC_mosi" IO_TYPE=LVCMOS33; -LOCATE COMP "spiAudioDAC_ss[0]" SITE "C15"; # DAC SPI CSn -IOBUF PORT "spiAudioDAC_ss[0]" IO_TYPE=LVCMOS33; - -LOCATE COMP "spi0_sclk" SITE "R5"; # SPI0 SCLK/GPIO_24 -IOBUF PORT "spi0_sclk" IO_TYPE=LVCMOS33; -LOCATE COMP "spi0_miso" SITE "T4"; # SPI0 MISO/GPIO_25 -IOBUF PORT "spi0_miso" IO_TYPE=LVCMOS33; -LOCATE COMP "spi0_mosi" SITE "M5"; # SPI0 MOSI/GPIO_26 -IOBUF PORT "spi0_mosi" IO_TYPE=LVCMOS33; -LOCATE COMP "spi0_ss[0]" SITE "N5"; # SPI0 CSn/GPIO_27 -IOBUF PORT "spi0_ss[0]" IO_TYPE=LVCMOS33; - -LOCATE COMP "hdmi_tmds_p[0]" SITE "A11"; -IOBUF PORT "hdmi_tmds_p[0]" IO_TYPE=LVCMOS33; -LOCATE COMP "hdmi_tmds_p[1]" SITE "D11"; -IOBUF PORT "hdmi_tmds_p[1]" IO_TYPE=LVCMOS33; -LOCATE COMP "hdmi_tmds_p[2]" SITE "B11"; -IOBUF PORT "hdmi_tmds_p[2]" IO_TYPE=LVCMOS33; -LOCATE COMP "hdmi_tmds_n[0]" SITE "A12"; -IOBUF PORT "hdmi_tmds_n[0]" IO_TYPE=LVCMOS33; -LOCATE COMP "hdmi_tmds_n[1]" SITE "E11"; -IOBUF PORT "hdmi_tmds_n[1]" IO_TYPE=LVCMOS33; -LOCATE COMP "hdmi_tmds_n[2]" SITE "C11"; -IOBUF PORT "hdmi_tmds_n[2]" IO_TYPE=LVCMOS33; -LOCATE COMP "hdmi_tmds_clk_p" SITE "B12"; -IOBUF PORT "hdmi_tmds_clk_p" IO_TYPE=LVCMOS33; -LOCATE COMP "hdmi_tmds_clk_n" SITE "C12"; -IOBUF PORT "hdmi_tmds_clk_n" IO_TYPE=LVCMOS33; - -LOCATE COMP "qspi0_cs" SITE "N8"; -IOBUF PORT "qspi0_cs" IO_TYPE=LVCMOS33; -LOCATE COMP "qspi0_sclk" SITE "N1"; // GPIO_08, should be M9 -IOBUF PORT "qspi0_sclk" IO_TYPE=LVCMOS33; -LOCATE COMP "qspi0_io0" SITE "T8"; -IOBUF PORT "qspi0_io0" IO_TYPE=LVCMOS33; -LOCATE COMP "qspi0_io1" SITE "T7"; -IOBUF PORT "qspi0_io1" IO_TYPE=LVCMOS33; -LOCATE COMP "qspi0_io2" SITE "M7"; -IOBUF PORT "qspi0_io2" IO_TYPE=LVCMOS33; -LOCATE COMP "qspi0_io3" SITE "N7"; -IOBUF PORT "qspi0_io3" IO_TYPE=LVCMOS33; - diff --git a/uart_transmitter/top.v b/uart_transmitter/top.v deleted file mode 100644 index 0b1cc0a..0000000 --- a/uart_transmitter/top.v +++ /dev/null @@ -1,39 +0,0 @@ -module top ( - input wire clk25, - input wire [1:0] key, - output wire [0:0] led, - output wire uart_debug_txd -); - -wire [31:0] baudrate = 31'd115200; - -wire rst; -assign rst = key[0]; - -wire ready; -reg [7:0] data = 8'h41; //"A" - -wire valid; -assign valid = key[1]; - - -wire tx; - - -assign led[0] = ready; -assign uart_debug_txd = tx; - - -uart_tx uart ( - .clk(clk25), - .rst(rst), - .data(data), - .baudrate(baudrate), - .ready(ready), - .valid(valid), - .parity_en(1'b1), // Enable bit parity - .parity_type(1'b1), // Odd parity - .tx(tx) -); - -endmodule diff --git a/uart_transmitter/uart_tx.v b/uart_transmitter/uart_tx.v deleted file mode 100644 index 98b79c5..0000000 --- a/uart_transmitter/uart_tx.v +++ /dev/null @@ -1,128 +0,0 @@ -module uart_tx ( - input wire rst, // Reset - input wire clk, // 25 MHz clock - input wire [7:0] data, // byte to transmit (need to use param) - input wire [31:0] baudrate, // baudrate selector - input wire valid, // Valid signal - input wire parity_en, // Enable pariry_type (1-Enable) - input wire parity_type, // 0 - Even parity, 1 - Odd parity - output reg ready, // Ready signal - output reg tx // uart output signal -); - -//=============================================== -// State parameters -//=============================================== - -localparam [2:0] - IDLE = 3'd0, // Waiting for command - START_BIT = 3'd1, // Start bit - DATA_BITS = 3'd2, // Start bit transfer - PARITY_BIT = 3'd3, // Parity - STOP_BIT = 3'd4; // Stop bit - -//=============================================== -// Transmitter state machine -//=============================================== -reg [7:0] shift_reg; -reg [2:0] bit_count; -reg [2:0] state; - -reg parity_bit; -wire final_parity; -assign final_parity = parity_type ? ~(^data) : ^data; - -reg [31:0] baud_counter; -wire [31:0] baud_limit; -assign baud_limit = (25000000/baudrate) - 1; -reg baud_tick; - -reg valid_prev; - -always @(posedge clk or posedge rst) begin - if (rst) begin - state <= IDLE; - tx <= 1'b1; - ready <= 1'b1; - shift_reg <= 0; - bit_count <= 0; - baud_tick <= 0; // for test - baud_counter <= 0; - end else begin - valid_prev <= valid; - - // Generation clk with baudrate - if (state != IDLE) begin - if (baud_counter == baud_limit) begin - baud_counter <= 0; - baud_tick <= 1'b1; - end else begin - baud_counter <= baud_counter + 1; - baud_tick <= 1'b0; - end - end else begin - baud_counter <= 0; - baud_tick <= 1'b1; // for test - end - - - case (state) - IDLE: begin - tx <= 1'b1; - //ready <= 1'b1; - if (ready && valid && !valid_prev) begin - state <= START_BIT; - shift_reg <= data; - baud_counter <= 0; - ready <= 1'b0; - parity_bit <= final_parity; - end - end - - //valid_prev <= valid; - - START_BIT: begin - tx <= 1'b0; - if (baud_counter == baud_limit) begin - state <= DATA_BITS; - baud_counter <= 0; - bit_count <= 0; - end - end - - DATA_BITS: begin - tx <= shift_reg[0]; - if (baud_counter == baud_limit) begin - shift_reg <= {1'b0, shift_reg[7:1]}; - baud_counter <= 0; - bit_count <= bit_count + 1; - if (bit_count == 7) begin // 8 bit - state <= parity_en ? PARITY_BIT : STOP_BIT; - end - end else begin - baud_counter <= baud_counter + 1; - end - end - - PARITY_BIT: begin - tx <= parity_bit; - if (baud_counter == baud_limit) begin - state <= STOP_BIT; - end - end - - STOP_BIT: begin - tx <= 1'b1; - if (baud_counter == baud_limit) begin - baud_counter <= 0; - state <= IDLE; - ready <= 1'b1; - end - end - endcase - - end -end - - -endmodule