How to connect the Floogen FlooNoc to AXI Interface

[NorrisChina]

In the below image, it is my module.sv generated by Floogen:

And after I do the simulation, I would like to encapsure my FlooNoc into an IP in vivado, I create IP, but the core0_req_in can not seperate, it can not be connected to AXI Interface directly, as you can see in the below graph:

Is there any adapter or module how can I connect the FlooNoc to the AXI Interface

[Burinir]

Hi! What you are trying to achieve can be done using AXI_SET_FROM_REQ and AXI_SET_FROM_RESP as defined in https://github.com/pulp-platform/axi/blob/master/include/axi/assign.svh

[NorrisChina]

Hi! What you are trying to achieve can be done using AXI_SET_FROM_REQ and AXI_SET_FROM_RESP as defined in https://github.com/pulp-platform/axi/blob/master/include/axi/assign.svh

Thanks for your suggestion, I am not sure how to do this. I just use floogen to generate my module.sv and I create an IP directly on the floogen result, I do not want to change the systemverilog code, is there any adaptor for my IP connecting to AXI Interface or I have to change the floogen_generated code and seperate the struct to connect the AXI?

[Burinir]

I see. I would not recommend changing the floogen_generatred code, as rerunning floogen would destroy your work. You could write a small adapter yourself, having seperate ar, aw, w input ports and a combined axi_req output port. In this you could just assign all fields of the axi_req from the seperate channels. Look at https://github.com/pulp-platform/axi/blob/master/include/axi/typedef.svh to see the axi_req fields. For example, you would
assign axi_req_o.r = axi_r_i;

[NorrisChina]

I see. I would not recommend changing the floogen_generatred code, as rerunning floogen would destroy your work. You could write a small adapter yourself, having seperate ar, aw, w input ports and a combined axi_req output port. In this you could just assign all fields of the axi_req from the seperate channels. Look at https://github.com/pulp-platform/axi/blob/master/include/axi/typedef.svh to see the axi_req fields. For example, you would assign axi_req_o.r = axi_r_i;

thanks a lot for the advice, but there will be lots of senarios for the adapter writing, maybe I can change the code of floogen, do not use the structure for the AXI, I can seperate in floogen.py, which makes my floogen_generation code can be connecting to AXI Interface directly?

[fischeti]

If you want you can also adapt floogen to output a module with AXI interfaces. What we usually do for every AXI IP is to wrap the module with AXI structs in a _intf variant (see here). Feel free to open a PR to add such a wrapper as well to the generated noc top module.