Skip to content

Latest commit

 

History

History
13 lines (8 loc) · 851 Bytes

File metadata and controls

13 lines (8 loc) · 851 Bytes

ACE SystemVerilog modules for cache coherent SoC design

This repository provides modules to implement cache coherence SoC's.

List of modules

Name Description Doc
ace_ccu_top ACE interconnector, broadcasts snooping messages to the cache controllers and AXI transactions to the slave Doc

License

The ACE repository is released under Solderpad v0.51 (SHL-0.51) see LICENSE