From fd7d98959f3e4761e3cecb8f0fed953ad4a9c21a Mon Sep 17 00:00:00 2001 From: Sophana KOK Date: Wed, 6 Apr 2022 14:57:07 +0200 Subject: [PATCH 1/4] add support for vivado xsim --- axi.core | 35 +++++++++++++++++++++++++++++++++-- src/axi_demux.sv | 4 ++-- src/axi_err_slv.sv | 2 +- src/axi_test.sv | 22 ++++++++++++++++++++-- src/axi_xbar.sv | 6 +++--- test/tb_axi_dw_pkg.sv | 2 +- test/tb_axi_xbar_pkg.sv | 6 +++--- 7 files changed, 63 insertions(+), 14 deletions(-) diff --git a/axi.core b/axi.core index b7010b8cd..61d8a7f8b 100644 --- a/axi.core +++ b/axi.core @@ -1,6 +1,6 @@ CAPI=2: -name : pulp-platform.org::axi:0.35.2-dev +name : pulp-platform.org::axi:0.35.2.dev filesets: rtl: @@ -51,7 +51,34 @@ filesets: - src/axi_xbar.sv file_type : systemVerilogSource depend : - - ">=pulp-platform.org::common_cells:1.21.0" + - ">=pulp-platform.org::common_cells:1.24.0" + benchs: + files: + - src/axi_test.sv + - test/tb_axi_dw_pkg.sv + - test/tb_axi_xbar_pkg.sv + - test/axi_synth_bench.sv + - test/tb_axi_addr_test.sv + - test/tb_axi_atop_filter.sv + - test/tb_axi_cdc.sv + - test/tb_axi_delayer.sv + - test/tb_axi_dw_downsizer.sv + - test/tb_axi_dw_upsizer.sv + - test/tb_axi_isolate.sv + - test/tb_axi_iw_converter.sv + - test/tb_axi_lite_mailbox.sv + - test/tb_axi_lite_regs.sv + - test/tb_axi_lite_to_apb.sv + - test/tb_axi_lite_to_axi.sv + - test/tb_axi_lite_xbar.sv + - test/tb_axi_modify_address.sv + - test/tb_axi_serializer.sv + - test/tb_axi_sim_mem.sv + - test/tb_axi_to_axi_lite.sv + - test/tb_axi_xbar.sv + file_type : systemVerilogSource + depend : + - ">=pulp-platform.org::common_verification:0.2.1" generators: axi_intercon_gen: @@ -107,3 +134,7 @@ generators: targets: default: filesets : [rtl] + sim: + filesets : [rtl,benchs] + description: Simulate the design + toplevel: tb_axi_dw_downsizer diff --git a/src/axi_demux.sv b/src/axi_demux.sv index 9ba3ef360..dd70cb962 100644 --- a/src/axi_demux.sv +++ b/src/axi_demux.sv @@ -609,7 +609,7 @@ module axi_demux #( // Validate parameters. // pragma translate_off `ifndef VERILATOR -`ifndef XSIM +`ifndef XILINX_SIMULATOR initial begin: validate_params no_mst_ports: assume (NoMstPorts > 0) else $fatal(1, "The Number of slaves (NoMstPorts) has to be at least 1"); @@ -758,7 +758,7 @@ module axi_demux_id_counters #( // pragma translate_off `ifndef VERILATOR -`ifndef XSIM +`ifndef XILINX_SIMULATOR // Validate parameters. cnt_underflow: assert property( @(posedge clk_i) disable iff (~rst_ni) (pop_en[i] |=> !overflow)) else diff --git a/src/axi_err_slv.sv b/src/axi_err_slv.sv index e7719c429..68b5163ec 100644 --- a/src/axi_err_slv.sv +++ b/src/axi_err_slv.sv @@ -244,7 +244,7 @@ module axi_err_slv #( // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR initial begin assert (Resp == axi_pkg::RESP_DECERR || Resp == axi_pkg::RESP_SLVERR) else $fatal(1, "This module may only generate RESP_DECERR or RESP_SLVERR responses!"); diff --git a/src/axi_test.sv b/src/axi_test.sv index 702d3fc1e..d3086d606 100644 --- a/src/axi_test.sv +++ b/src/axi_test.sv @@ -862,7 +862,13 @@ package axi_test; for (int i = 0; i < traffic_shape.size(); i++) if (traffic_shape[i].cprob > cprob) begin len = traffic_shape[i].len; +`ifdef XILINX_SIMULATOR + if (ax_beat.ax_burst == BURST_WRAP) begin + assert ( len inside {len_t'(1), len_t'(3), len_t'(7), len_t'(15)}); + end; +`else assert (ax_beat.ax_burst == BURST_WRAP -> len inside {len_t'(1), len_t'(3), len_t'(7), len_t'(15)}); +`endif break; end @@ -1193,7 +1199,11 @@ package axi_test; automatic w_beat_t w_beat = new; automatic int unsigned begin_byte, end_byte, n_bytes; automatic logic [AXI_STRB_WIDTH-1:0] rand_strb, strb_mask; +`ifdef XILINX_SIMULATOR + rand_success = std::randomize(w_beat); assert (rand_success); +`else rand_success = w_beat.randomize(); assert (rand_success); +`endif // Determine strobe. w_beat.w_strb = '0; n_bytes = 2**aw_beat.ax_size; @@ -1332,7 +1342,11 @@ package axi_test; automatic r_beat_t r_beat = new; wait (ar_queue.size > 0); ar_beat = ar_queue.peek(); - rand_success = r_beat.randomize(); assert(rand_success); +`ifdef XILINX_SIMULATOR + rand_success = std::randomize(r_beat); assert (rand_success); +`else + rand_success = r_beat.randomize(); assert (rand_success); +`endif r_beat.r_id = ar_beat.ax_id; if (RAND_RESP && !ar_beat.ax_atop[axi_pkg::ATOP_R_RESP]) r_beat.r_resp[1] = $random(); @@ -1384,7 +1398,11 @@ package axi_test; automatic logic rand_success; wait (b_wait_cnt > 0 && (aw_queue.size() != 0)); aw_beat = aw_queue.pop_front(); - rand_success = b_beat.randomize(); assert(rand_success); +`ifdef XILINX_SIMULATOR + rand_success = std::randomize(b_beat); assert (rand_success); +`else + rand_success = b_beat.randomize(); assert (rand_success); +`endif b_beat.b_id = aw_beat.ax_id; if (RAND_RESP && !aw_beat.ax_atop[axi_pkg::ATOP_R_RESP]) b_beat.b_resp[1] = $random(); diff --git a/src/axi_xbar.sv b/src/axi_xbar.sv index 2ffa7fc85..98831547b 100644 --- a/src/axi_xbar.sv +++ b/src/axi_xbar.sv @@ -125,7 +125,7 @@ import cf_math_pkg::idx_width; // make sure that the default slave does not get changed, if there is an unserved Ax // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XILINX_SIMULATOR default disable iff (~rst_ni); default_aw_mst_port_en: assert property( @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) @@ -265,7 +265,7 @@ import cf_math_pkg::idx_width; // pragma translate_off `ifndef VERILATOR - `ifndef XSIM + `ifndef XXILINX_SIMULATOR initial begin : check_params id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id ) == Cfg.AxiIdWidthSlvPorts) else $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); @@ -283,10 +283,10 @@ endmodule module axi_xbar_intf import cf_math_pkg::idx_width; #( + parameter axi_pkg::xbar_cfg_t Cfg = '0, parameter int unsigned AXI_USER_WIDTH = 0, parameter bit ATOPS = 1'b1, parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] CONNECTIVITY = '1, - parameter axi_pkg::xbar_cfg_t Cfg = '0, parameter type rule_t = axi_pkg::xbar_rule_64_t `ifdef VCS , localparam int unsigned MstPortsIdxWidth = diff --git a/test/tb_axi_dw_pkg.sv b/test/tb_axi_dw_pkg.sv index 9d9bed7fa..d211da2ae 100644 --- a/test/tb_axi_dw_pkg.sv +++ b/test/tb_axi_dw_pkg.sv @@ -413,7 +413,7 @@ package tb_axi_dw_pkg ; axi_b_id = slv_port_axi.b_id; $display("%0tns > Master: Got last B with ID: %b", $time, axi_b_id); - if (this.exp_slv_port_b_queue.empty()) begin + if (this.exp_slv_port_b_queue.is_empty()) begin incr_failed_tests(1) ; $warning("Master: unexpected B beat with ID: %b detected!", axi_b_id); end else begin diff --git a/test/tb_axi_xbar_pkg.sv b/test/tb_axi_xbar_pkg.sv index 77eff888f..fb7098998 100644 --- a/test/tb_axi_xbar_pkg.sv +++ b/test/tb_axi_xbar_pkg.sv @@ -283,7 +283,7 @@ package tb_axi_xbar_pkg; axi_b_id = masters_axi[i].b_id; $display("%0tns > Master %0d: Got last B with id: %b", $time, i, axi_b_id); - if (this.exp_b_queue[i].empty()) begin + if (this.exp_b_queue[i].is_empty()) begin incr_failed_tests(1); $warning("Master %d: unexpected B beat with ID: %b detected!", i, axi_b_id); end else begin @@ -358,7 +358,7 @@ package tb_axi_xbar_pkg; if (slaves_axi[i].ar_valid && slaves_axi[i].ar_ready) begin incr_conducted_tests(1); slv_axi_id = slaves_axi[i].ar_id; - if (this.exp_ar_queue[i].empty()) begin + if (this.exp_ar_queue[i].is_empty()) begin incr_failed_tests(1); end else begin // check that the ids are the same @@ -386,7 +386,7 @@ package tb_axi_xbar_pkg; $display("%0tns > Master %0d: Got last R with id: %b", $time, i, mst_axi_r_id); end - if (this.exp_r_queue[i].empty()) begin + if (this.exp_r_queue[i].is_empty()) begin incr_failed_tests(1); $warning("Master %d: unexpected R beat with ID: %b detected!", i, mst_axi_r_id); end else begin From 98171ce198b15d1105c4606df6da4e415a42afd9 Mon Sep 17 00:00:00 2001 From: Sophana KOK Date: Tue, 3 May 2022 09:28:28 +0200 Subject: [PATCH 2/4] added more benchs and sim targets in fusesoc. more fixes for vivado --- axi.core | 27 +++++++++++++++++++++++++-- test/tb_axi_sim_mem.sv | 12 ++++++++++-- 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/axi.core b/axi.core index 61d8a7f8b..49da1ab85 100644 --- a/axi.core +++ b/axi.core @@ -49,12 +49,13 @@ filesets: - src/axi_iw_converter.sv - src/axi_lite_xbar.sv - src/axi_xbar.sv + - src/axi_sim_mem.sv + - src/axi_test.sv file_type : systemVerilogSource depend : - ">=pulp-platform.org::common_cells:1.24.0" benchs: files: - - src/axi_test.sv - test/tb_axi_dw_pkg.sv - test/tb_axi_xbar_pkg.sv - test/axi_synth_bench.sv @@ -134,7 +135,29 @@ generators: targets: default: filesets : [rtl] - sim: + sim: &sim filesets : [rtl,benchs] description: Simulate the design + toplevel: tb_axi_delayer + sim_dw_downsizer: + <<: *sim toplevel: tb_axi_dw_downsizer + sim_addr_test : { filesets : [rtl,benchs] , toplevel: tb_axi_addr_test } + sim_atop_filter : { filesets : [rtl,benchs] , toplevel: tb_axi_atop_filter } + sim_cdc : { filesets : [rtl,benchs] , toplevel: tb_axi_cdc } + sim_delayer : { filesets : [rtl,benchs] , toplevel: tb_axi_delayer } + sim_dw_pkg : { filesets : [rtl,benchs] , toplevel: tb_axi_dw_pkg } + sim_dw_upsizer : { filesets : [rtl,benchs] , toplevel: tb_axi_dw_upsizer } + sim_isolate : { filesets : [rtl,benchs] , toplevel: tb_axi_isolate } + sim_iw_converter : { filesets : [rtl,benchs] , toplevel: tb_axi_iw_converter } + sim_lite_mailbox : { filesets : [rtl,benchs] , toplevel: tb_axi_lite_mailbox } + sim_lite_regs : { filesets : [rtl,benchs] , toplevel: tb_axi_lite_regs } + sim_lite_to_apb : { filesets : [rtl,benchs] , toplevel: tb_axi_lite_to_apb } + sim_lite_to_axi : { filesets : [rtl,benchs] , toplevel: tb_axi_lite_to_axi } + sim_lite_xbar : { filesets : [rtl,benchs] , toplevel: tb_axi_lite_xbar } + sim_modify_address: { filesets : [rtl,benchs] , toplevel: tb_axi_modify_address } + sim_serializer : { filesets : [rtl,benchs] , toplevel: tb_axi_serializer } + sim_sim_mem : { filesets : [rtl,benchs] , toplevel: tb_axi_sim_mem } + sim_to_axi_lite : { filesets : [rtl,benchs] , toplevel: tb_axi_to_axi_lite } + sim_xbar : { filesets : [rtl,benchs] , toplevel: tb_axi_xbar } + sim_xbar_pkg : { filesets : [rtl,benchs] , toplevel: tb_axi_xbar_pkg } diff --git a/test/tb_axi_sim_mem.sv b/test/tb_axi_sim_mem.sv index 35fa7e980..0e5f51822 100644 --- a/test/tb_axi_sim_mem.sv +++ b/test/tb_axi_sim_mem.sv @@ -84,7 +84,11 @@ module tb_axi_sim_mem #( drv.reset_master(); wait (rst_n); // AW - rand_success = aw_beat.randomize(); assert(rand_success); +`ifdef XILINX_SIMULATOR + rand_success = std::randomize(aw_beat); assert (rand_success); +`else + rand_success = aw_beat.randomize(); assert (rand_success); +`endif aw_beat.ax_addr >>= $clog2(StrbWidth); // align address with data width aw_beat.ax_addr <<= $clog2(StrbWidth); aw_beat.ax_len = $urandom(); @@ -93,7 +97,11 @@ module tb_axi_sim_mem #( drv.send_aw(aw_beat); // W beats for (int unsigned i = 0; i <= aw_beat.ax_len; i++) begin - rand_success = w_beat.randomize(); assert(rand_success); +`ifdef XILINX_SIMULATOR + rand_success = std::randomize(w_beat); assert (rand_success); +`else + rand_success = w_beat.randomize(); assert (rand_success); +`endif w_beat.w_strb = '1; if (i == aw_beat.ax_len) begin w_beat.w_last = 1'b1; From de954cd7c5c71578be236e41c9f908ba3e83ffb1 Mon Sep 17 00:00:00 2001 From: Sophana KOK Date: Mon, 29 Aug 2022 18:27:00 +0200 Subject: [PATCH 3/4] added separate fusesoc core file for axi test library --- axi.core | 1 - axi_test.core | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 axi_test.core diff --git a/axi.core b/axi.core index 7095d4f7c..fa2adb017 100644 --- a/axi.core +++ b/axi.core @@ -50,7 +50,6 @@ filesets: - src/axi_lite_xbar.sv - src/axi_xbar.sv - src/axi_sim_mem.sv - - src/axi_test.sv file_type : systemVerilogSource depend : - ">=pulp-platform.org::common_cells:1.24.0" diff --git a/axi_test.core b/axi_test.core new file mode 100644 index 000000000..328ad4805 --- /dev/null +++ b/axi_test.core @@ -0,0 +1,16 @@ +CAPI=2: +# specific core for using axi testing package from outside project +# it must be removed from rtl fileset because it is not synthesisable + +name : pulp-platform.org::axi-test:0.1.dev + +filesets: + bench: + files: + - src/axi_test.sv + file_type : systemVerilogSource + depend : + - ">=pulp-platform.org::common_verification:0.2.1" +targets: + default: + filesets : [bench] From bc835869336e27706fac09b8c540a73916d43827 Mon Sep 17 00:00:00 2001 From: Sophana KOK Date: Mon, 29 Aug 2022 18:55:38 +0200 Subject: [PATCH 4/4] remove duplicated parameter --- src/axi_xbar.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/src/axi_xbar.sv b/src/axi_xbar.sv index 4905b66f5..98831547b 100644 --- a/src/axi_xbar.sv +++ b/src/axi_xbar.sv @@ -285,7 +285,6 @@ import cf_math_pkg::idx_width; #( parameter axi_pkg::xbar_cfg_t Cfg = '0, parameter int unsigned AXI_USER_WIDTH = 0, - parameter axi_pkg::xbar_cfg_t Cfg = '0, parameter bit ATOPS = 1'b1, parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] CONNECTIVITY = '1, parameter type rule_t = axi_pkg::xbar_rule_64_t