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Hardware bring-up round (v1.57+): the 7-item flight-readiness register #157

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@avrabe

The v1.45→v1.56 round closed PX4 capability parity in simulation (see docs/PX4-PARITY-ASSESSMENT.md, refreshed in #156). What remains is flight-proven maturity — the boundary between "provably correct in SITL" and "flown." This epic tracks the 7 register items; each is an assignable slice others can pick up independently.

  1. Real driver bodies on silicon — beyond the 4 we have (falcon-imu-icm42688, falcon-gnss-ubx, falcon-esc-dshot, falcon-baromag mock-bus). Real register transactions on a board.
  2. Sensor calibration — accel/gyro/mag/baro calibration routines on a real board (not SITL-injected).
  3. Per-airframe flight tuning — the SE(3)/ADRC math is proven; gains for a real frame are not. Cascade co-tuning (position loop is bandwidth-limited by attitude — see project memory).
  4. WCET leaf measurement — the compositional WCET proof is done; cycle counts on the target MCU are not measured.
  5. Physical HITL transport — UART/USB/UDP end-to-end (falcon-hitl exists as a seam).
  6. libm qualification — transcendental math is on the flight path; centralize behind a math seam (relay-math) before qualifying.
  7. First flight — the irreducible field test. Falsifies (or confirms) everything above.

Plus the integration project: meld→loom→synth→gale onto the board. The v1.56 component bundle (falcon-components-v1.56.tar.gz) is the input to that hand-off.

Sequencing note: these are NOT all serial — items 1/2/5/6 can proceed in parallel; 3 depends on 1+2; 4 depends on 5; 7 depends on everything. Pick a slice, open a child issue, ship it through the feature loop as its own release.

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