From 96bae66fe06ce35508f4df3cb2df1e6da5b10dbd Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Sat, 5 Sep 2026 14:14:04 +0530 Subject: [PATCH 1/7] Revert "QCLINUX: arm64: dts: qcom: lemans: Add RTSS Mailbox device tree overlay" This reverts commit 1923b1cd3cc1c3211a0108d0ac79f0163aeb0a9b. The original overlay accessed the APSS TCSR mutex/status registers via direct memory-mapped reg ranges and shipped RTSS as a standalone lemans-rtss-mb.dtso overlay. Upstream review feedback on this design requires: - Accessing the TCSR registers via a syscon phandle instead of a direct reg-mapped node. - Folding the RTSS mailbox node into the shared lemans-staging.dtso overlay instead of a separate, RTSS-only DTBO. The following commits reintroduce this support using that syscon-based, staging-overlay design. Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/Makefile | 1 - arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso | 65 -------------------- 2 files changed, 66 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 77e48d33fbf78..bf6c7dca9d654 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -542,7 +542,6 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-staging.dtbo -dtb-$(CONFIG_ARCH_QCOM) += lemans-rtss-mb.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-staging.dtbo monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo diff --git a/arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso b/arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso deleted file mode 100644 index b1d8996c9ea8b..0000000000000 --- a/arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; -/plugin/; - -#include -#include -#include - -&soc { - ipcc_computeL1: qcom,ipcc@488000 { - compatible = "qcom,ipcc"; - reg = <0x0 0x00488000 0x0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - num_mbox_chans = <5>; - }; - - rtss_mailbox: rtss-mailbox@1ffe02c { - compatible = "qcom,rtss-mailbox"; - reg = <0x0 0x01ffe02c 0x0 0x10>, - <0x0 0x01ffd018 0x0 0x10>, - <0x0 0x17c0000c 0x0 0x04>; - mboxes = <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x2>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0x3>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x4>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x5>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x6>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x7>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0x8>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0x9>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0xa>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0xb>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0xc>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0xd>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0xe>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0xf>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS3 0x10>; - memory-region = <&sail_mailbox_mem>, - <&sail_ota_mem>; - interrupt-parent = <&ipcc_computeL1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - rtss-handshake-delay = <50000>; - status = "okay"; - }; -}; From 280fb678ddc4f36e307e9daa5b2622945150ec8f Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Sat, 5 Sep 2026 14:14:18 +0530 Subject: [PATCH 2/7] Revert "QCLINUX: arm64: dts: qcom: Monaco: Add RTSS Mailbox device tree overlay" This reverts commit 117902228b6747a0d4293ff9b25494e3345c1ae3. Same as the lemans overlay, the original Monaco overlay accessed the APSS TCSR mutex/status registers via direct memory-mapped reg ranges and shipped RTSS as a standalone monaco-rtss-mb.dtso overlay. Upstream review feedback on this design requires: - Accessing the TCSR registers via a syscon phandle instead of a direct reg-mapped node. - Folding the RTSS mailbox node into the shared monaco-staging.dtso overlay instead of a separate, RTSS-only DTBO. The following commits reintroduce this support using that syscon-based, staging-overlay design. Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/Makefile | 1 - arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso | 65 -------------------- 2 files changed, 66 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index bf6c7dca9d654..8aafa383a5c52 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -555,7 +555,6 @@ dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-staging.dtbo -dtb-$(CONFIG_ARCH_QCOM) += monaco-rtss-mb.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-staging.dtbo diff --git a/arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso b/arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso deleted file mode 100644 index b1d8996c9ea8b..0000000000000 --- a/arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; -/plugin/; - -#include -#include -#include - -&soc { - ipcc_computeL1: qcom,ipcc@488000 { - compatible = "qcom,ipcc"; - reg = <0x0 0x00488000 0x0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - num_mbox_chans = <5>; - }; - - rtss_mailbox: rtss-mailbox@1ffe02c { - compatible = "qcom,rtss-mailbox"; - reg = <0x0 0x01ffe02c 0x0 0x10>, - <0x0 0x01ffd018 0x0 0x10>, - <0x0 0x17c0000c 0x0 0x04>; - mboxes = <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x2>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0x3>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x4>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x5>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x6>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x7>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0x8>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0x9>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0xa>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0xb>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0xc>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0xd>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0xe>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0xf>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS3 0x10>; - memory-region = <&sail_mailbox_mem>, - <&sail_ota_mem>; - interrupt-parent = <&ipcc_computeL1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - rtss-handshake-delay = <50000>; - status = "okay"; - }; -}; From acaad01c7b901b178dfa61d775ccd7be22296dfe Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Thu, 10 Sep 2026 02:51:28 +0530 Subject: [PATCH 3/7] QCLINUX: dt-bindings: mailbox: Add qcom,rtss-mailbox schema Add missing rtss mailbox dt schema file. Signed-off-by: Ram Sargar --- .../bindings/mailbox/qcom,rtss-mailbox.yaml | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,rtss-mailbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/qcom,rtss-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,rtss-mailbox.yaml new file mode 100644 index 0000000000000..7d83acbe48a38 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/qcom,rtss-mailbox.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/qcom,rtss-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. RTSS Mailbox + +maintainers: + - Ram Sargar + +description: + The RTSS mailbox exposes a shared-memory and IPCC doorbell channel between + the application processor and the RTSS subsystem, and manages handshake + with the RTSS subsystem to handle different milestones in mission mode. + +properties: + compatible: + items: + - enum: + - qcom,sa8775p-rtss-mailbox + - qcom,qcs8300-rtss-mailbox + - const: qcom,rtss-mailbox + + qcom,syscon-tcsr-req: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the TCSR syscon node + - description: offset of the RTSS request register from the syscon base + description: + Reference to the TCSR syscon node and register offset used to write + the boot/suspend handshake magic that RTSS reads. + + qcom,syscon-tcsr-resp: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the TCSR syscon node + - description: offset of the RTSS response register from the syscon base + description: + Reference to the TCSR syscon node and register offset used to read + back the handshake magic RTSS acknowledges with. + + qcom,syscon-ipc: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the APSS shared IPC syscon node + - description: offset of the IPC trigger register from the syscon base + description: + Reference to the syscon node and register offset used to trigger the + IPC interrupt that notifies RTSS a TCSR handshake register was updated. + + mboxes: + description: + IPCC mailbox channels used to send interrupts to the RTSS-facing IPCC + client/signal pairs. + + interrupts-extended: + description: + IPCC channels used to receive interrupts from the RTSS-facing IPCC + client/signal pairs. + + memory-region: + items: + - description: reserved-memory carveout for the RTSS mailbox descriptor region + - description: reserved-memory carveout for the OTA region + description: + Reference to the reserved-memory regions used for the mailbox + descriptor and for OTA. + +required: + - compatible + - qcom,syscon-tcsr-req + - qcom,syscon-tcsr-resp + - qcom,syscon-ipc + - mboxes + - interrupts-extended + - memory-region + +additionalProperties: false + +examples: + - | + #include + #include + + rtss-ipcc-mailbox { + compatible = "qcom,sa8775p-rtss-mailbox", "qcom,rtss-mailbox"; + qcom,syscon-tcsr-req = <&tcsr 0x3e02c>; + qcom,syscon-tcsr-resp = <&tcsr 0x3d018>; + qcom,syscon-ipc = <&apss_shared_ipc 0x0>; + mboxes = <&ipcc1 IPCC_CLIENT_RTSS0 0x2>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3>; + interrupts-extended = <&ipcc1 IPCC_CLIENT_RTSS0 0x2 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3 IRQ_TYPE_EDGE_RISING>; + memory-region = <&sail_mailbox_mem>, <&sail_ota_mem>; + }; From 1cc19d28397520d2abff7721c3ecbb7dc66a4644 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Thu, 10 Sep 2026 02:47:17 +0530 Subject: [PATCH 4/7] QCLINUX: arm64: dts: qcom: lemans: Add IPCC and syscon nodes for RTSS Mailbox Add ipcc1-4 mailbox nodes, widen the tcsr syscon's reg range to cover both TCSR request/response registers, and add the apss_shared_ipc syscon node for the Lemans platform. These back the syscon/mbox phandle references used by the Lemans RTSS mailbox node (qcom,rtss-mailbox). Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/lemans.dtsi | 43 +++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 695eae1b72569..636c0548dd6dd 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -1018,6 +1018,42 @@ #mbox-cells = <2>; }; + ipcc1: mailbox@488000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x00488000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc2: mailbox@4a1000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a1000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc3: mailbox@4a2000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a2000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc4: mailbox@4a3000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a3000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + qfprom: efuse@784000 { compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; reg = <0x0 0x00784000 0x0 0x3000>; @@ -4635,7 +4671,7 @@ tcsr: syscon@1fc0000 { compatible = "qcom,sa8775p-tcsr", "syscon"; - reg = <0x0 0x1fc0000 0x0 0x30000>; + reg = <0x0 0x1fc0000 0x0 0x40000>; }; gpu: gpu@3d00000 { @@ -7058,6 +7094,11 @@ redistributor-stride = <0x0 0x20000>; }; + apss_shared_ipc: syscon@17c0000c { + compatible = "qcom,sa8775p-tcsr", "syscon"; + reg = <0x0 0x17c0000c 0x0 0x4>; + }; + watchdog@17c10000 { compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; reg = <0x0 0x17c10000 0x0 0x1000>; From 09e0cccc7a9ef55b82715f7535f75024dc9faaff Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Thu, 10 Sep 2026 02:49:11 +0530 Subject: [PATCH 5/7] QCLINUX: arm64: dts: qcom: lemans-staging: Add rtss-mailbox node Add the rtss_mailbox overlay node for the Lemans platform, using ipcc1-ipcc4 and the tcsr/apss_shared_ipc syscon nodes. Place it under &soc, alongside the other simple-bus child nodes in this file. Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/lemans-staging.dtso | 43 ++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-staging.dtso b/arch/arm64/boot/dts/qcom/lemans-staging.dtso index ad919bfb6b19a..cade1b4fa94e7 100644 --- a/arch/arm64/boot/dts/qcom/lemans-staging.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-staging.dtso @@ -7,8 +7,51 @@ /dts-v1/; /plugin/; +#include +#include +#include +#include &soc { + rtss_mailbox: rtss-ipcc-mailbox { + compatible = "qcom,sa8775p-rtss-mailbox", "qcom,rtss-mailbox"; + qcom,syscon-tcsr-req = <&tcsr 0x3e02c>; + qcom,syscon-tcsr-resp = <&tcsr 0x3d018>; + qcom,syscon-ipc = <&apss_shared_ipc 0x0>; + mboxes = <&ipcc1 IPCC_CLIENT_RTSS0 0x2>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x4>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x5>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x6>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x7>, + <&ipcc1 IPCC_CLIENT_RTSS2 0x8>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x9>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xa>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xb>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xc>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xd>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xe>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xf>, + <&ipcc1 IPCC_CLIENT_RTSS3 0x10>; + interrupts-extended = <&ipcc1 IPCC_CLIENT_RTSS0 0x2 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x4 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x5 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x6 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x7 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0x8 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x9 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xa IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xb IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xc IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xd IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xe IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xf IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS3 0x10 IRQ_TYPE_EDGE_RISING>; + memory-region = <&sail_mailbox_mem>, + <&sail_ota_mem>; + }; + tgu@4b0e000 { compatible = "qcom,tgu", "arm,primecell"; reg = <0x0 0x4b0e000 0x0 0x1000>; From 7547cfe681db8f456d6d01bc864899612fa4d92f Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Thu, 10 Sep 2026 02:50:00 +0530 Subject: [PATCH 6/7] QCLINUX: arm64: dts: qcom: monaco: Add IPCC, syscon, and memory nodes for RTSS Mailbox Add ipcc1-4 mailbox nodes, widen the tcsr syscon's reg range to cover both TCSR request/response registers, and add the apss_shared_ipc syscon node for the Monaco platform. These back the syscon/mbox phandle references used by the Monaco RTSS mailbox node (qcom,rtss-mailbox). Reserve the memory regions used by the SAIL/RTSS subsystem for its TZ mailbox, shared-memory mailbox, and OTA buffer on Monaco. These regions back the memory-region references used by the Monaco RTSS mailbox node. Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/monaco.dtsi | 58 +++++++++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 40832d650f73e..d7e5cc711d8c9 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -748,6 +748,21 @@ hwlocks = <&tcsr_mutex 3>; }; + tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { + reg = <0x0 0x90c00000 0x0 0x100000>; + no-map; + }; + + sail_mailbox_mem: sail-ss@90d00000 { + reg = <0x0 0x90d00000 0x0 0x100000>; + no-map; + }; + + sail_ota_mem: sail-ss@90e00000 { + reg = <0x0 0x90e00000 0x0 0x300000>; + no-map; + }; + gunyah_md_mem: gunyah-md-region@91a80000 { reg = <0x0 0x91a80000 0x0 0x80000>; no-map; @@ -919,6 +934,42 @@ #mbox-cells = <2>; }; + ipcc1: mailbox@488000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x00488000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc2: mailbox@4a1000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a1000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc3: mailbox@4a2000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a2000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc4: mailbox@4a3000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a3000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + qfprom: efuse@784000 { compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; reg = <0x0 0x00784000 0x0 0x2410>; @@ -2745,7 +2796,7 @@ tcsr: syscon@1fc0000 { compatible = "qcom,qcs8300-tcsr", "syscon"; - reg = <0x0 0x1fc0000 0x0 0x30000>; + reg = <0x0 0x1fc0000 0x0 0x40000>; }; remoteproc_adsp: remoteproc@3000000 { @@ -7401,6 +7452,11 @@ #address-cells = <0>; }; + apss_shared_ipc: syscon@17c0000c { + compatible = "qcom,qcs8300-tcsr", "syscon"; + reg = <0x0 0x17c0000c 0x0 0x4>; + }; + watchdog@17c10000 { compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; reg = <0x0 0x17c10000 0x0 0x1000>; From 215e02fa20231688bd4728ba924698e522816d35 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Thu, 10 Sep 2026 02:51:04 +0530 Subject: [PATCH 7/7] QCLINUX: arm64: dts: qcom: monaco-staging: Add rtss-mailbox node Add the rtss_mailbox overlay node for the Monaco platform, mirroring the Lemans RTSS mailbox node. Place it under &soc, alongside the other simple-bus child nodes in this file. Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/monaco-staging.dtso | 42 ++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-staging.dtso b/arch/arm64/boot/dts/qcom/monaco-staging.dtso index fc44741b8caab..680c7e8bf814a 100644 --- a/arch/arm64/boot/dts/qcom/monaco-staging.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-staging.dtso @@ -7,8 +7,50 @@ /dts-v1/; /plugin/; +#include +#include +#include &soc { + rtss_mailbox: rtss-ipcc-mailbox { + compatible = "qcom,qcs8300-rtss-mailbox", "qcom,rtss-mailbox"; + qcom,syscon-tcsr-req = <&tcsr 0x3e02c>; + qcom,syscon-tcsr-resp = <&tcsr 0x3d018>; + qcom,syscon-ipc = <&apss_shared_ipc 0x0>; + mboxes = <&ipcc1 IPCC_CLIENT_RTSS0 0x2>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x4>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x5>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x6>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x7>, + <&ipcc1 IPCC_CLIENT_RTSS2 0x8>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x9>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xa>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xb>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xc>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xd>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xe>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xf>, + <&ipcc1 IPCC_CLIENT_RTSS3 0x10>; + interrupts-extended = <&ipcc1 IPCC_CLIENT_RTSS0 0x2 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x4 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x5 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x6 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x7 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0x8 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x9 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xa IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xb IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xc IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xd IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xe IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xf IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS3 0x10 IRQ_TYPE_EDGE_RISING>; + memory-region = <&sail_mailbox_mem>, + <&sail_ota_mem>; + }; + tgu@4b0e000 { compatible = "qcom,tgu", "arm,primecell"; reg = <0x0 0x4b0e000 0x0 0x1000>;