diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index 3f3a043255fee..0b84596e0bd6e 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -4614,15 +4614,6 @@
 			};
 		};
 
-		cti@12021000 {
-			compatible = "arm,coresight-cti", "arm,primecell";
-			reg = <0x0 0x12021000 0x0 0x1000>;
-
-			clocks = <&aoss_qmp>;
-			clock-names = "apb_pclk";
-			label = "cti_ddr0";
-		};
-
 		itnoc@12200000 {
 			compatible = "qcom,coresight-itnoc";
 			reg = <0x0 0x12200000 0x0 0x2e80>;
@@ -4841,15 +4832,6 @@
 			};
 		};
 
-		cti@12221000 {
-			compatible = "arm,coresight-cti", "arm,primecell";
-			reg = <0x0 0x12221000 0x0 0x1000>;
-
-			clocks = <&aoss_qmp>;
-			clock-names = "apb_pclk";
-			label = "cti_ddr1";
-		};
-
 		itnoc@12400000 {
 			compatible = "qcom,coresight-itnoc";
 			reg = <0x0 0x12400000 0x0 0x2e80>;
@@ -5068,15 +5050,6 @@
 			};
 		};
 
-		cti@12421000 {
-			compatible = "arm,coresight-cti", "arm,primecell";
-			reg = <0x0 0x12421000 0x0 0x1000>;
-
-			clocks = <&aoss_qmp>;
-			clock-names = "apb_pclk";
-			label = "cti_ddr2";
-		};
-
 		itnoc@12600000 {
 			compatible = "qcom,coresight-itnoc";
 			reg = <0x0 0x12600000 0x0 0x2e80>;
@@ -5295,15 +5268,6 @@
 			};
 		};
 
-		cti@12621000 {
-			compatible = "arm,coresight-cti", "arm,primecell";
-			reg = <0x0 0x12621000 0x0 0x1000>;
-
-			clocks = <&aoss_qmp>;
-			clock-names = "apb_pclk";
-			label = "cti_ddr3";
-		};
-
 		apps_smmu_0: iommu@15a00000 {
 			compatible = "qcom,nord-smmu-500",
 				     "qcom,smmu-500",