From e0b04126fde6ccb7b31672d40f43a1334512744a Mon Sep 17 00:00:00 2001 From: Shivam Sanjay Date: Thu, 10 Sep 2026 00:56:48 +0530 Subject: [PATCH] drivers: qcom: rpmh: add nord support Adding Nord support, following target specific RMPh configuration structure. Unit tested on Nord device. --- .../arch/arm/plat-qcom/wildcat/nord/target.mk | 13 +++++ .../plat-qcom/wildcat/nord/target_config.h | 21 +++++-- core/drivers/qcom/rpmh/nord/rpmh_drv_config.c | 40 +++++++++++++ core/drivers/qcom/rpmh/nord/rpmh_hwio.h | 57 +++++++++++++++++++ .../qcom/rpmh/nord/rpmh_target_config.h | 20 +++++++ core/drivers/qcom/rpmh/rpmh_client.c | 4 +- core/drivers/qcom/rpmh/rpmh_hal.c | 1 + core/drivers/qcom/rpmh/rpmh_hal.h | 39 ------------- 8 files changed, 149 insertions(+), 46 deletions(-) create mode 100644 core/drivers/qcom/rpmh/nord/rpmh_drv_config.c create mode 100644 core/drivers/qcom/rpmh/nord/rpmh_hwio.h create mode 100644 core/drivers/qcom/rpmh/nord/rpmh_target_config.h diff --git a/core/arch/arm/plat-qcom/wildcat/nord/target.mk b/core/arch/arm/plat-qcom/wildcat/nord/target.mk index c774f510f..fa77d3418 100644 --- a/core/arch/arm/plat-qcom/wildcat/nord/target.mk +++ b/core/arch/arm/plat-qcom/wildcat/nord/target.mk @@ -11,3 +11,16 @@ $(call force,CFG_TEE_CORE_NB_CORE,18) CFG_TZDRAM_START ?= 0xBC280000 CFG_TEE_RAM_VA_SIZE ?= 0x00200000 CFG_TA_RAM_VA_SIZE ?= 0x07B80000 + +ifneq ($(CFG_INSECURE),y) +CFG_QCOM_QFPROM_FUSEPROV ?= y +endif + +ifeq ($(CFG_QCOM_QFPROM_FUSEPROV),y) +$(call force,CFG_QCOM_CMD_DB,y) +$(call force,CFG_QCOM_RPMH_CLIENT,y) +endif + +ifneq ($(filter y,$(CFG_QCOM_QFPROM_FUSEPROV) $(CFG_QCOM_FUSE_PTA)),) +$(call force,CFG_QCOM_QFPROM,y) +endif diff --git a/core/arch/arm/plat-qcom/wildcat/nord/target_config.h b/core/arch/arm/plat-qcom/wildcat/nord/target_config.h index 3d7065ff7..12af2ba20 100644 --- a/core/arch/arm/plat-qcom/wildcat/nord/target_config.h +++ b/core/arch/arm/plat-qcom/wildcat/nord/target_config.h @@ -10,12 +10,23 @@ #define GICD_BASE UL(0x17000000) #define GICR_BASE UL(0x17080000) +#define AOP_CMD_DB_BASE UL(0x87148000) + +#define AOP_CMD_DB_SIZE UL(0x2000) + +#define AOP_MSG_RAM_BASE UL(0x0C300000) +#define AOP_MSG_RAM_SIZE UL(0x00100000) +#define MSG_RAM_SECTION_SIZE UL(0x00001000) + +#define RPMH_BASE_ADDR UL(0x18900000) +#define RPMH_RSC_SIZE UL(0x10000) + #define DRAM0_BASE UL(0x80000000) -#define DRAM0_SIZE UL(0x80000000) -#define DRAM1_BASE ULL(0x880000000) -#define DRAM1_SIZE ULL(0x780000000) -#define DRAM2_BASE ULL(0x8800000000) -#define DRAM2_SIZE ULL(0x3800000000) +#define DRAM0_SIZE UL(0x80000000) +#define DRAM1_BASE ULL(0x880000000) +#define DRAM1_SIZE ULL(0x780000000) +#define DRAM2_BASE ULL(0x8800000000) +#define DRAM2_SIZE ULL(0x3800000000) #endif /* TARGET_CONFIG_H */ diff --git a/core/drivers/qcom/rpmh/nord/rpmh_drv_config.c b/core/drivers/qcom/rpmh/nord/rpmh_drv_config.c new file mode 100644 index 000000000..aaec92d0b --- /dev/null +++ b/core/drivers/qcom/rpmh/nord/rpmh_drv_config.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +#include "rpmh_drv_config.h" +#include "rpmh_target_config.h" + +static const struct tcs_config tcs_config_tz = { + .amcs = RPMH_TCS_SLEEP - RPMH_TCS_AMC, + .sleep_start = RPMH_TCS_SLEEP, + .wake_start = RPMH_TCS_WAKE, +}; + +static const struct drv_config_data optee_config_data = { + .drvs_count = 1, + .init_clks_count = 0, + .init_clks = NULL, + .sleep_clks_count = 0, + .sleep_clks = NULL, + + .drvs = (struct drv_config[]) { + { + .drv_id = RSC_DRV_SECURE, + .hw_drv = RSC_DRV_SECURE, + .wake_set_latency = 0x7080, /* 1.5ms in 19.2MHz */ + .tcs_offset = 0, + .tcs = RPMH_TCS_MAX, + .cmds = RPMH_MAX_CMDS_PER_TCS, + .modes_count = 1, + .modes = (const struct tcs_config *[]) { + &tcs_config_tz, + } + } + } +}; + +const struct drv_config_data *const g_drv_config_data = &optee_config_data; diff --git a/core/drivers/qcom/rpmh/nord/rpmh_hwio.h b/core/drivers/qcom/rpmh/nord/rpmh_hwio.h new file mode 100644 index 000000000..403a5c1f8 --- /dev/null +++ b/core/drivers/qcom/rpmh/nord/rpmh_hwio.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __RPMH_HWIO_H__ +#define __RPMH_HWIO_H__ + +#include + +#define DRV_STRIDE 0x10000 +#define RSC_DRV_IRQ_ENABLE 0x0d00 +#define RSC_DRV_IRQ_STATUS 0x0d04 +#define RSC_DRV_IRQ_CLEAR 0x0d08 + +#define RSC_DRV_TCS_CONFIG 0x0C +#define TCS_BASE_OFFSET 0x0D20 +#define TCS_STRIDE 0x2A0 + +#define TCS_CONTROL_OFFSET 0x04 +#define TCS_STATUS_OFFSET 0x08 +#define TCS_CMD_ENABLE_OFFSET 0x0C + +#define TCS_PROFILING_STATUS_OFFSET 0x10 + +#define TCS_CMD_BASE_OFFSET 0x14 +#define TCS_CMDn_MSGID_OFFSET 0x00 +#define TCS_CMDn_ADDR_OFFSET 0x04 +#define TCS_CMDn_DATA_OFFSET 0x08 +#define TCS_CMD_STRIDE 0x18 + +#define TCS_CONTROL_AMC_MODE_TRIGGER BIT(24) +#define TCS_CONTROL_AMC_MODE_EN BIT(16) + +#define TCS_STATUS_CONTROLLER_IDLE BIT(0) + +#define RSC_DRV_ERROR_IRQ_STATUS 0xD0 +#define RSC_DRV_ERROR_IRQ_ENABLE 0xD8 +#define RSC_DRV_ERROR_IRQ_CLEAR 0xD4 + +#define EPCB_TIMEOUT_IRQ_EN_MASK BIT(20) +#define EPCB_TIMEOUT_THRESHOLD_SHIFT 0x0 +#define EPCB_TIMEOUT_THRESHOLD_MASK 0xFFFF + +#define MSGID_READ_OR_WRITE_SHIFT 0x10 +#define MSGID_RES_REQ_SHIFT 0x8 +#define MSGID_MSG_LENGTH_SHIFT 0x0 + +#define MSGID_READ 0x0 +#define MSGID_WRITE 0x1 + +#define MSGID_MSG_LENGTH_VALUE 0x8 + +#define ADDR_SLV_ID_SHIFT 0x10 +#define ADDR_OFFSET_SHIFT 0x0 + +#endif /* __RPMH_HWIO_H__ */ diff --git a/core/drivers/qcom/rpmh/nord/rpmh_target_config.h b/core/drivers/qcom/rpmh/nord/rpmh_target_config.h new file mode 100644 index 000000000..7718c9f31 --- /dev/null +++ b/core/drivers/qcom/rpmh/nord/rpmh_target_config.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __RPMH_TARGET_CONFIG_H__ +#define __RPMH_TARGET_CONFIG_H__ + +#include + +enum rpmh_tcs_config { + RPMH_TCS_AMC = 0, /* Active TCS start */ + RPMH_TCS_SLEEP = 2, /* Active TCS end, Sleep TCS start */ + RPMH_TCS_WAKE = 3, /* Sleep TCS end, Wake TCS start */ + RPMH_TCS_MAX = 4 /* Wake TCS end, Max TCS count */ +}; + +#define RPMH_MAX_CMDS_PER_TCS 16 + +#endif /* __RPMH_TARGET_CONFIG_H__ */ diff --git a/core/drivers/qcom/rpmh/rpmh_client.c b/core/drivers/qcom/rpmh/rpmh_client.c index e10d73c37..cc420b28f 100644 --- a/core/drivers/qcom/rpmh/rpmh_client.c +++ b/core/drivers/qcom/rpmh/rpmh_client.c @@ -24,6 +24,7 @@ #include "rpmh_hal.h" #include "rpmh_resource_commands.h" #include "rpmh_tcs.h" +#include "rpmh_hwio.h" register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AOP_MSG_RAM_BASE, CORE_MMU_PGDIR_SIZE); @@ -66,7 +67,6 @@ struct client_queue { }; #define AOP_BOOT_COOKIE 0xA0C00C1E -#define MSG_RAM_SECTION_SIZE 0x10000 struct aop_msg_ram_dict { uint32_t boot_cookie_offset; @@ -242,7 +242,7 @@ static TEE_Result check_aop_init(void) return TEE_ERROR_GENERIC; } - dict_addr = base + AOP_MSG_RAM_SIZE - MSG_RAM_SECTION_SIZE; + dict_addr = base + 15 * MSG_RAM_SECTION_SIZE; dict = (struct aop_msg_ram_dict *)dict_addr; cookie_addr = base + dict->boot_cookie_offset; diff --git a/core/drivers/qcom/rpmh/rpmh_hal.c b/core/drivers/qcom/rpmh/rpmh_hal.c index 90dbf6f51..defe6784c 100644 --- a/core/drivers/qcom/rpmh/rpmh_hal.c +++ b/core/drivers/qcom/rpmh/rpmh_hal.c @@ -8,6 +8,7 @@ #include #include "rpmh_hal.h" +#include "rpmh_hwio.h" static struct { vaddr_t rsc_base; diff --git a/core/drivers/qcom/rpmh/rpmh_hal.h b/core/drivers/qcom/rpmh/rpmh_hal.h index 91bc090e6..85b187c86 100644 --- a/core/drivers/qcom/rpmh/rpmh_hal.h +++ b/core/drivers/qcom/rpmh/rpmh_hal.h @@ -17,45 +17,6 @@ enum hal_status { HAL_STATUS_INVALID_PARAM = 2, }; -#define DRV_STRIDE 0x10000 -#define RSC_DRV_IRQ_ENABLE 0x0d00 -#define RSC_DRV_IRQ_STATUS 0x0d04 -#define RSC_DRV_IRQ_CLEAR 0x0d08 - -#define RSC_DRV_TCS_CONFIG 0x0C -#define TCS_BASE_OFFSET 0x0D10 /* CMD_WAIT_FOR_CMPL base */ -#define TCS_STRIDE 0x2A0 - -#define TCS_CONTROL_OFFSET 0x04 -#define TCS_STATUS_OFFSET 0x08 -#define TCS_CMD_ENABLE_OFFSET 0x0C - -#define TCS_CMD_BASE_OFFSET 0x20 -#define TCS_CMDn_MSGID_OFFSET 0x00 -#define TCS_CMDn_ADDR_OFFSET 0x04 -#define TCS_CMDn_DATA_OFFSET 0x08 -#define TCS_CMD_STRIDE 0x14 - -#define TCS_CONTROL_AMC_MODE_TRIGGER BIT(24) -#define TCS_CONTROL_AMC_MODE_EN BIT(16) - -#define TCS_STATUS_CONTROLLER_IDLE BIT(0) - -#define RSC_DRV_ERROR_IRQ_STATUS 0xD0 -#define RSC_DRV_ERROR_IRQ_ENABLE 0xD8 -#define RSC_DRV_ERROR_IRQ_CLEAR 0xD4 - -#define EPCB_TIMEOUT_IRQ_EN_MASK BIT(20) -#define EPCB_TIMEOUT_THRESHOLD_SHIFT 0x0 -#define EPCB_TIMEOUT_THRESHOLD_MASK 0xFFFF - -#define MSGID_READ_OR_WRITE_SHIFT 0x10 -#define MSGID_RES_REQ_SHIFT 0x8 -#define MSGID_MSG_LENGTH_SHIFT 0x0 - -#define ADDR_SLV_ID_SHIFT 0x10 -#define ADDR_OFFSET_SHIFT 0x0 - enum hal_status hal_rpmh_init(vaddr_t rsc_base); enum hal_status hal_rpmh_register_drv(enum rsc_drv_id drv_id); enum hal_status hal_rpmh_read_config(enum rsc_drv_id drv_id,