From 39cd10c4f042be87861134eb425357602e180aa2 Mon Sep 17 00:00:00 2001 From: mrehman Date: Tue, 25 Aug 2026 17:45:28 +0530 Subject: [PATCH 01/12] drivers: qcom: prng: add CSRNG support Add CSRNG driver support required by Nord and Shikra platforms.wq Signed-off-by: mrehman --- core/drivers/qcom/rng/qcom-csrng.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/core/drivers/qcom/rng/qcom-csrng.c b/core/drivers/qcom/rng/qcom-csrng.c index 1b7c6a15b..e3cd3ddfd 100644 --- a/core/drivers/qcom/rng/qcom-csrng.c +++ b/core/drivers/qcom/rng/qcom-csrng.c @@ -9,11 +9,8 @@ #include #include #include +#include -#define QCOM_RNG_REG_SIZE 0x1000 - -#define QCOM_RNG_DATA_OUT 0x0 -#define QCOM_RNG_STATUS 0x4 #define QCOM_RNG_STATUS_DATA_AVAIL_BMSK 0x1 #define QCOM_RNG_TIMEOUT_US 1000000 @@ -31,24 +28,32 @@ TEE_Result hw_get_random_bytes(void *buf, size_t len) uint32_t val = 0; uint64_t to = 0; - if (!rng.va) + if (!rng.va) { + EMSG("QCOM RNG: not initialized"); return TEE_ERROR_NOT_SUPPORTED; + } - if (!out || !len) + if (!out || !len) { + EMSG("QCOM RNG: invalid parameters"); return TEE_ERROR_BAD_PARAMETERS; + } to = timeout_init_us(QCOM_RNG_TIMEOUT_US); while (len) { if (!(io_read32(rng.va + QCOM_RNG_STATUS) & QCOM_RNG_STATUS_DATA_AVAIL_BMSK)) { - if (timeout_elapsed(to)) + if (timeout_elapsed(to)) { + EMSG("QCOM RNG: timeout waiting for data"); return TEE_ERROR_BUSY; + } continue; } while ((val = io_read32(rng.va + QCOM_RNG_DATA_OUT)) == 0) { - if (timeout_elapsed(to)) + if (timeout_elapsed(to)) { + EMSG("QCOM RNG: timeout reading data"); return TEE_ERROR_BUSY; + } } for (size_t i = 0; i < sizeof(val) && len; i++) { @@ -64,8 +69,13 @@ static TEE_Result qcom_csrng_init(void) { rng.va = (vaddr_t)core_mmu_add_mapping(MEM_AREA_IO_SEC, rng.pa, QCOM_RNG_REG_SIZE); - if (!rng.va) + if (!rng.va) { + EMSG("QCOM RNG: failed to map PA=0x%08"PRIxPA, rng.pa); return TEE_ERROR_GENERIC; + } + + IMSG("QCOM RNG: mapped PA=0x%08"PRIxPA" VA=0x%08"PRIxVA, + rng.pa, rng.va); return TEE_SUCCESS; } From dfb5c4c070e376bc35aef6f939ef86c238f726ac Mon Sep 17 00:00:00 2001 From: mrehman Date: Tue, 25 Aug 2026 18:36:06 +0530 Subject: [PATCH 02/12] plat-qcom: hoya: kodiak: disable CSRNG support Disable CSRNG support on Kodiak platforms that do not support the CSRNG hardware. Signed-off-by: mrehman --- core/arch/arm/plat-qcom/hoya/kodiak/target_config.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h b/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h index 77354f49e..ff714b788 100644 --- a/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h +++ b/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h @@ -39,4 +39,10 @@ #define IRIS_BASE UL(0x0aa00000) #define IRIS_SIZE ULL(0x00200000) +/* Configuration Registers for RNG */ +#define QCOM_RNG_REG_BASE UL(0x010C0000) +#define QCOM_RNG_REG_SIZE UL(0x00020000) +#define QCOM_RNG_DATA_OUT 0x11000 +#define QCOM_RNG_STATUS 0x11004 + #endif /* TARGET_CONFIG_H */ From 57699a039e5904198ca8e2839f8cfed98cbd4bae Mon Sep 17 00:00:00 2001 From: mrehman Date: Tue, 25 Aug 2026 18:37:17 +0530 Subject: [PATCH 03/12] plat-qcom: hoya: lemans: disable CSRNG support Disable CSRNG support on Lemans platforms that do not support the CSRNG hardware. Signed-off-by: mrehman --- core/arch/arm/plat-qcom/hoya/lemans/target_config.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/core/arch/arm/plat-qcom/hoya/lemans/target_config.h b/core/arch/arm/plat-qcom/hoya/lemans/target_config.h index 757c67c61..6e5ba7a10 100644 --- a/core/arch/arm/plat-qcom/hoya/lemans/target_config.h +++ b/core/arch/arm/plat-qcom/hoya/lemans/target_config.h @@ -92,6 +92,12 @@ #define RPMH_PDC_GPDSP1_BASE UL(0x0b2d0000) #define RPMH_PDC_GPDSP1_SIZE UL(0x00002000) +/* Configuration Registers for RNG */ +#define QCOM_RNG_REG_BASE UL(0x010C0000) +#define QCOM_RNG_REG_SIZE UL(0x00020000) +#define QCOM_RNG_DATA_OUT 0x11000 +#define QCOM_RNG_STATUS 0x11004 + #define TITAN_SS_BASE UL(0x0ac00000) #define TITAN_SS_SIZE UL(0x00200000) #endif /* TARGET_CONFIG_H */ From 717f9d245991179f440cf6d11485e91e10e8c7cb Mon Sep 17 00:00:00 2001 From: mrehman Date: Tue, 25 Aug 2026 18:38:09 +0530 Subject: [PATCH 04/12] plat-qcom: hoya: disable CSRNG by default Disable CFG_QCOM_CSRNG by default for Hoya targets. Signed-off-by: mrehman --- core/arch/arm/plat-qcom/hoya/qcom-arch.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/arch/arm/plat-qcom/hoya/qcom-arch.mk b/core/arch/arm/plat-qcom/hoya/qcom-arch.mk index 091471168..e07abfc5f 100644 --- a/core/arch/arm/plat-qcom/hoya/qcom-arch.mk +++ b/core/arch/arm/plat-qcom/hoya/qcom-arch.mk @@ -14,4 +14,4 @@ CFG_TZDRAM_START ?= 0x1c300000 CFG_TEE_RAM_VA_SIZE ?= 0x200000 CFG_TA_RAM_VA_SIZE ?= 0x1c00000 CFG_TZDRAM_SIZE ?= (CFG_TEE_RAM_VA_SIZE + CFG_TA_RAM_VA_SIZE) -CFG_NUM_THREADS ?= 8 +CFG_NUM_THREADS ?= 8 \ No newline at end of file From 53a6dcd0452d95197abd2016ac1f07c52a3aff90 Mon Sep 17 00:00:00 2001 From: mrehman Date: Tue, 25 Aug 2026 17:42:32 +0530 Subject: [PATCH 05/12] plat-qcom: wildcat: nord: enable CSRNG support Enable CSRNG support on Nord platforms. Update the platform configuration to enable the CSRNG driver on Nord. Signed-off-by: mrehman --- core/arch/arm/plat-qcom/wildcat/nord/target.mk | 4 ++++ core/arch/arm/plat-qcom/wildcat/nord/target_config.h | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/core/arch/arm/plat-qcom/wildcat/nord/target.mk b/core/arch/arm/plat-qcom/wildcat/nord/target.mk index c774f510f..500d207db 100644 --- a/core/arch/arm/plat-qcom/wildcat/nord/target.mk +++ b/core/arch/arm/plat-qcom/wildcat/nord/target.mk @@ -11,3 +11,7 @@ $(call force,CFG_TEE_CORE_NB_CORE,18) CFG_TZDRAM_START ?= 0xBC280000 CFG_TEE_RAM_VA_SIZE ?= 0x00200000 CFG_TA_RAM_VA_SIZE ?= 0x07B80000 + +# Enable the Qualcomm CSRNG hardware RNG driver. +# Register offsets and base address are defined in target_config.h. +$(call force,CFG_QCOM_CSRNG,y) diff --git a/core/arch/arm/plat-qcom/wildcat/nord/target_config.h b/core/arch/arm/plat-qcom/wildcat/nord/target_config.h index 3d7065ff7..58fdba42e 100644 --- a/core/arch/arm/plat-qcom/wildcat/nord/target_config.h +++ b/core/arch/arm/plat-qcom/wildcat/nord/target_config.h @@ -18,4 +18,9 @@ #define DRAM2_BASE ULL(0x8800000000) #define DRAM2_SIZE ULL(0x3800000000) +#define QCOM_RNG_REG_BASE UL(0x010C0000) +#define QCOM_RNG_REG_SIZE UL(0x2000) +#define QCOM_RNG_DATA_OUT 0x1000 +#define QCOM_RNG_STATUS 0x1004 + #endif /* TARGET_CONFIG_H */ From 733a83723945fb22cdd9a34aac7550127c4a7a5c Mon Sep 17 00:00:00 2001 From: mrehman Date: Tue, 25 Aug 2026 17:44:37 +0530 Subject: [PATCH 06/12] plat-qcom: bruin: shikra: enable CSRNG support Enable CSRNG support on Shikra platforms. Update the platform configuration to enable the CSRNG driver on Shikra. Signed-off-by: mrehman --- core/arch/arm/plat-qcom/bruin/shikra/target.mk | 5 ++++- core/arch/arm/plat-qcom/bruin/shikra/target_config.h | 5 +++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/core/arch/arm/plat-qcom/bruin/shikra/target.mk b/core/arch/arm/plat-qcom/bruin/shikra/target.mk index 14ae1120a..926114ac6 100644 --- a/core/arch/arm/plat-qcom/bruin/shikra/target.mk +++ b/core/arch/arm/plat-qcom/bruin/shikra/target.mk @@ -1 +1,4 @@ -# Placeholder for target specific configs. +# Enable the Qualcomm CSRNG hardware RNG driver. +# Shikra uses the legacy PRNG block via HWKM MMIO. +# Register offsets and base address are defined in target_config.h. +CFG_QCOM_CSRNG ?= y \ No newline at end of file diff --git a/core/arch/arm/plat-qcom/bruin/shikra/target_config.h b/core/arch/arm/plat-qcom/bruin/shikra/target_config.h index e2a4aeb39..3f7436638 100644 --- a/core/arch/arm/plat-qcom/bruin/shikra/target_config.h +++ b/core/arch/arm/plat-qcom/bruin/shikra/target_config.h @@ -14,4 +14,9 @@ #define IMEM_BASE UL(0x0c100000) #define IMEM_SIZE UL(0x00020000) +#define QCOM_RNG_REG_BASE UL(0x04440000) +#define QCOM_RNG_REG_SIZE UL(0x00020000) +#define QCOM_RNG_DATA_OUT 0x11000 +#define QCOM_RNG_STATUS 0x11004 + #endif /* TARGET_CONFIG_H */ From ff86dddd5cf27ee136f6a2cf2f9a327baf04bb3d Mon Sep 17 00:00:00 2001 From: mrehman Date: Wed, 2 Sep 2026 11:58:46 +0530 Subject: [PATCH 07/12] plat-qcom: hoya: use common RNG base definition Avoid redefining QCOM_RNG_REG_BASE in Kodiak and Lemans target configuration files. Use the common Hoya definition from arch_config.h and adjust platform-specific offsets to preserve the same effective register addresses. Signed-off-by: mrehman --- core/arch/arm/plat-qcom/hoya/kodiak/target_config.h | 5 ++--- core/arch/arm/plat-qcom/hoya/lemans/target_config.h | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h b/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h index ff714b788..ef355c937 100644 --- a/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h +++ b/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h @@ -40,9 +40,8 @@ #define IRIS_SIZE ULL(0x00200000) /* Configuration Registers for RNG */ -#define QCOM_RNG_REG_BASE UL(0x010C0000) #define QCOM_RNG_REG_SIZE UL(0x00020000) -#define QCOM_RNG_DATA_OUT 0x11000 -#define QCOM_RNG_STATUS 0x11004 +#define QCOM_RNG_DATA_OUT 0x0 +#define QCOM_RNG_STATUS 0x4 #endif /* TARGET_CONFIG_H */ diff --git a/core/arch/arm/plat-qcom/hoya/lemans/target_config.h b/core/arch/arm/plat-qcom/hoya/lemans/target_config.h index 6e5ba7a10..7a5bc83b2 100644 --- a/core/arch/arm/plat-qcom/hoya/lemans/target_config.h +++ b/core/arch/arm/plat-qcom/hoya/lemans/target_config.h @@ -93,10 +93,9 @@ #define RPMH_PDC_GPDSP1_SIZE UL(0x00002000) /* Configuration Registers for RNG */ -#define QCOM_RNG_REG_BASE UL(0x010C0000) #define QCOM_RNG_REG_SIZE UL(0x00020000) -#define QCOM_RNG_DATA_OUT 0x11000 -#define QCOM_RNG_STATUS 0x11004 +#define QCOM_RNG_DATA_OUT 0x0 +#define QCOM_RNG_STATUS 0x4 #define TITAN_SS_BASE UL(0x0ac00000) #define TITAN_SS_SIZE UL(0x00200000) From 598e41601e4efbd5a05cfafcdcd21b0a8564f825 Mon Sep 17 00:00:00 2001 From: mrehman Date: Wed, 2 Sep 2026 12:29:19 +0530 Subject: [PATCH 08/12] drivers: qcom: prng: read DATA_OUT when data is available Read DATA_OUT directly after DATA_AVAIL is asserted. A value of 0x00000000 is a valid random output and should not be filtered out. Waiting for a non-zero value biases the output distribution by excluding a valid result. Signed-off-by: mrehman --- core/drivers/qcom/rng/qcom-csrng.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/core/drivers/qcom/rng/qcom-csrng.c b/core/drivers/qcom/rng/qcom-csrng.c index e3cd3ddfd..36d8114d0 100644 --- a/core/drivers/qcom/rng/qcom-csrng.c +++ b/core/drivers/qcom/rng/qcom-csrng.c @@ -49,12 +49,7 @@ TEE_Result hw_get_random_bytes(void *buf, size_t len) continue; } - while ((val = io_read32(rng.va + QCOM_RNG_DATA_OUT)) == 0) { - if (timeout_elapsed(to)) { - EMSG("QCOM RNG: timeout reading data"); - return TEE_ERROR_BUSY; - } - } + val = io_read32(rng.va + QCOM_RNG_DATA_OUT); for (size_t i = 0; i < sizeof(val) && len; i++) { *out++ = (uint8_t)(val >> (i * 8)); From bbc3b7e22664cc1b9c13c6ed3ad61e2b7829033b Mon Sep 17 00:00:00 2001 From: mrehman Date: Wed, 2 Sep 2026 12:36:10 +0530 Subject: [PATCH 09/12] drivers: qcom: prng: remove initialization log Remove the CSRNG initialization log message as it is not required during normal operation. Signed-off-by: mrehman --- core/drivers/qcom/rng/qcom-csrng.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/core/drivers/qcom/rng/qcom-csrng.c b/core/drivers/qcom/rng/qcom-csrng.c index 36d8114d0..b9646c1fd 100644 --- a/core/drivers/qcom/rng/qcom-csrng.c +++ b/core/drivers/qcom/rng/qcom-csrng.c @@ -69,9 +69,6 @@ static TEE_Result qcom_csrng_init(void) return TEE_ERROR_GENERIC; } - IMSG("QCOM RNG: mapped PA=0x%08"PRIxPA" VA=0x%08"PRIxVA, - rng.pa, rng.va); - return TEE_SUCCESS; } From eaf713865dc093396b006a1e28fa03ae8c49200d Mon Sep 17 00:00:00 2001 From: mrehman Date: Wed, 2 Sep 2026 18:08:44 +0530 Subject: [PATCH 10/12] plat-qcom: address CSRNG review comments Force CSRNG enablement on Shikra and define RNG register configuration in the Hoya target-specific configuration files instead of a common architecture configuration. Signed-off-by: mrehman --- core/arch/arm/plat-qcom/bruin/shikra/target.mk | 2 +- core/arch/arm/plat-qcom/hoya/arch_config.h | 1 - core/arch/arm/plat-qcom/hoya/kodiak/target_config.h | 7 ++++--- core/arch/arm/plat-qcom/hoya/lemans/target_config.h | 7 ++++--- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/core/arch/arm/plat-qcom/bruin/shikra/target.mk b/core/arch/arm/plat-qcom/bruin/shikra/target.mk index 926114ac6..31a8937b6 100644 --- a/core/arch/arm/plat-qcom/bruin/shikra/target.mk +++ b/core/arch/arm/plat-qcom/bruin/shikra/target.mk @@ -1,4 +1,4 @@ # Enable the Qualcomm CSRNG hardware RNG driver. # Shikra uses the legacy PRNG block via HWKM MMIO. # Register offsets and base address are defined in target_config.h. -CFG_QCOM_CSRNG ?= y \ No newline at end of file +$(call force,CFG_QCOM_CSRNG,y) \ No newline at end of file diff --git a/core/arch/arm/plat-qcom/hoya/arch_config.h b/core/arch/arm/plat-qcom/hoya/arch_config.h index 11fc5ab44..b603fbf8e 100644 --- a/core/arch/arm/plat-qcom/hoya/arch_config.h +++ b/core/arch/arm/plat-qcom/hoya/arch_config.h @@ -11,7 +11,6 @@ #define GICR_BASE UL(0x17a60000) #define RAMBLUR_PIMEM_REG_BASE UL(0x610000) -#define QCOM_RNG_REG_BASE UL(0x010D1000) #define AOP_MSG_RAM_BASE UL(0x0C300000) #define AOP_MSG_RAM_SIZE UL(0x00100000) diff --git a/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h b/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h index ef355c937..55650f2f6 100644 --- a/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h +++ b/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h @@ -40,8 +40,9 @@ #define IRIS_SIZE ULL(0x00200000) /* Configuration Registers for RNG */ -#define QCOM_RNG_REG_SIZE UL(0x00020000) -#define QCOM_RNG_DATA_OUT 0x0 -#define QCOM_RNG_STATUS 0x4 +#define QCOM_RNG_REG_BASE UL(0x010C0000) +#define QCOM_RNG_REG_SIZE UL(0x00020000) +#define QCOM_RNG_DATA_OUT 0x11000 +#define QCOM_RNG_STATUS 0x11004 #endif /* TARGET_CONFIG_H */ diff --git a/core/arch/arm/plat-qcom/hoya/lemans/target_config.h b/core/arch/arm/plat-qcom/hoya/lemans/target_config.h index 7a5bc83b2..f1987f011 100644 --- a/core/arch/arm/plat-qcom/hoya/lemans/target_config.h +++ b/core/arch/arm/plat-qcom/hoya/lemans/target_config.h @@ -93,9 +93,10 @@ #define RPMH_PDC_GPDSP1_SIZE UL(0x00002000) /* Configuration Registers for RNG */ -#define QCOM_RNG_REG_SIZE UL(0x00020000) -#define QCOM_RNG_DATA_OUT 0x0 -#define QCOM_RNG_STATUS 0x4 +#define QCOM_RNG_REG_BASE UL(0x010C0000) +#define QCOM_RNG_REG_SIZE UL(0x00020000) +#define QCOM_RNG_DATA_OUT 0x11000 +#define QCOM_RNG_STATUS 0x11004 #define TITAN_SS_BASE UL(0x0ac00000) #define TITAN_SS_SIZE UL(0x00200000) From 59835a9179013bc7ea1c792e631c731828089dc2 Mon Sep 17 00:00:00 2001 From: mrehman Date: Wed, 2 Sep 2026 18:26:44 +0530 Subject: [PATCH 11/12] plat-qcom: adjust CSRNG register definitions Use platform-specific CSRNG base addresses and offsets to avoid redefining common RNG configuration while preserving the effective register addresses. Signed-off-by: mrehman --- core/arch/arm/plat-qcom/bruin/shikra/target_config.h | 6 +++--- core/arch/arm/plat-qcom/hoya/kodiak/target_config.h | 6 +++--- core/arch/arm/plat-qcom/hoya/lemans/target_config.h | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/core/arch/arm/plat-qcom/bruin/shikra/target_config.h b/core/arch/arm/plat-qcom/bruin/shikra/target_config.h index 3f7436638..7cabfdd72 100644 --- a/core/arch/arm/plat-qcom/bruin/shikra/target_config.h +++ b/core/arch/arm/plat-qcom/bruin/shikra/target_config.h @@ -14,9 +14,9 @@ #define IMEM_BASE UL(0x0c100000) #define IMEM_SIZE UL(0x00020000) -#define QCOM_RNG_REG_BASE UL(0x04440000) +#define QCOM_RNG_REG_BASE UL(0x04450000) #define QCOM_RNG_REG_SIZE UL(0x00020000) -#define QCOM_RNG_DATA_OUT 0x11000 -#define QCOM_RNG_STATUS 0x11004 +#define QCOM_RNG_DATA_OUT 0x1000 +#define QCOM_RNG_STATUS 0x1004 #endif /* TARGET_CONFIG_H */ diff --git a/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h b/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h index 55650f2f6..fac001d8c 100644 --- a/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h +++ b/core/arch/arm/plat-qcom/hoya/kodiak/target_config.h @@ -40,9 +40,9 @@ #define IRIS_SIZE ULL(0x00200000) /* Configuration Registers for RNG */ -#define QCOM_RNG_REG_BASE UL(0x010C0000) +#define QCOM_RNG_REG_BASE UL(0x010D0000) #define QCOM_RNG_REG_SIZE UL(0x00020000) -#define QCOM_RNG_DATA_OUT 0x11000 -#define QCOM_RNG_STATUS 0x11004 +#define QCOM_RNG_DATA_OUT 0x1000 +#define QCOM_RNG_STATUS 0x1004 #endif /* TARGET_CONFIG_H */ diff --git a/core/arch/arm/plat-qcom/hoya/lemans/target_config.h b/core/arch/arm/plat-qcom/hoya/lemans/target_config.h index f1987f011..3e5cde5fb 100644 --- a/core/arch/arm/plat-qcom/hoya/lemans/target_config.h +++ b/core/arch/arm/plat-qcom/hoya/lemans/target_config.h @@ -93,10 +93,10 @@ #define RPMH_PDC_GPDSP1_SIZE UL(0x00002000) /* Configuration Registers for RNG */ -#define QCOM_RNG_REG_BASE UL(0x010C0000) +#define QCOM_RNG_REG_BASE UL(0x010D0000) #define QCOM_RNG_REG_SIZE UL(0x00020000) -#define QCOM_RNG_DATA_OUT 0x11000 -#define QCOM_RNG_STATUS 0x11004 +#define QCOM_RNG_DATA_OUT 0x1000 +#define QCOM_RNG_STATUS 0x1004 #define TITAN_SS_BASE UL(0x0ac00000) #define TITAN_SS_SIZE UL(0x00200000) From 3f86d68bf681b2ea4bfc8c5a7bccea27f5615590 Mon Sep 17 00:00:00 2001 From: mrehman Date: Thu, 10 Sep 2026 10:39:03 +0530 Subject: [PATCH 12/12] plat-qcom: drop unintended qcom-arch.mk change --- core/arch/arm/plat-qcom/hoya/qcom-arch.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/arch/arm/plat-qcom/hoya/qcom-arch.mk b/core/arch/arm/plat-qcom/hoya/qcom-arch.mk index e07abfc5f..091471168 100644 --- a/core/arch/arm/plat-qcom/hoya/qcom-arch.mk +++ b/core/arch/arm/plat-qcom/hoya/qcom-arch.mk @@ -14,4 +14,4 @@ CFG_TZDRAM_START ?= 0x1c300000 CFG_TEE_RAM_VA_SIZE ?= 0x200000 CFG_TA_RAM_VA_SIZE ?= 0x1c00000 CFG_TZDRAM_SIZE ?= (CFG_TEE_RAM_VA_SIZE + CFG_TA_RAM_VA_SIZE) -CFG_NUM_THREADS ?= 8 \ No newline at end of file +CFG_NUM_THREADS ?= 8