diff --git a/Kconfig b/Kconfig index e5de815d8cae..6f44e1f80466 100644 --- a/Kconfig +++ b/Kconfig @@ -559,6 +559,14 @@ config REMAKE_ELF U-Boot binary (u-boot.bin), which may already have been statically relocated and may already have a device-tree appended to it. +config REMAKE_ELF_LDSCRIPT + string "Linker script for u-boot.elf" + depends on REMAKE_ELF + default "arch/u-boot-elf.lds" + help + This allows specifying a linker script that will be used to + re-wrap the U-Boot binary into an ELF. + config BUILD_TARGET string "Build target special images" default "u-boot-elf.shdr" if RCAR_64 && RCAR_64_RSIP diff --git a/Makefile b/Makefile index c6253670a94e..ae1cf241cd7e 100644 --- a/Makefile +++ b/Makefile @@ -2018,7 +2018,9 @@ spl/u-boot-spl.elf: spl/u-boot-spl.bin u-boot-elf.lds $(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< spl/u-boot-spl-elf.o $(call if_changed,u-boot-spl-elf) -u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE +REMAKE_ELF_LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_REMAKE_ELF_LDSCRIPT:"%"=%)) + +u-boot-elf.lds: $(REMAKE_ELF_LDSCRIPT) prepare FORCE $(call if_changed_dep,cpp_lds) PHONY += prepare0 diff --git a/arch/arm/config.mk b/arch/arm/config.mk index bce9a31e966b..a609d90225bb 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -120,6 +120,13 @@ ifeq ($(CONFIG_ARM64),y) LDFLAGS_u-boot += -z common-page-size=0x1000 -z max-page-size=0x1000 endif +ifeq ($(CONFIG_ARCH_SNAPDRAGON),y) +# The CONFIG_REMAKE_ELF u-boot.elf link step doesn't pick up the +# 4K page-size flags used for u-boot.bin above, so wire them in here +# too. TME's IMGAUTH requires 4K-aligned ELF segments. +LDFLAGS_u-boot-elf += -z common-page-size=0x1000 -z max-page-size=0x1000 +endif + # # FIXME: binutils versions < 2.22 have a bug in the assembler where # branches to weak symbols can be incorrectly optimized in thumb mode diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 135bb62ea723..f34e7dcba2ab 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -1063,6 +1063,15 @@ static void set_regions(u64 start, u64 size, u64 attrs, bool flag) break; } } + if (level == 4) { + /* No level could map this granule — without this guard the + * outer while(size>0) spins forever. Report and bail so the + * offending region is visible instead of hanging. + */ + log_err("mmu_change_region_attr_nobreak: STUCK at start=0x%llx size=0x%llx (no level mapped)\n", + (unsigned long long)start, (unsigned long long)size); + break; + } } } diff --git a/arch/arm/dts/nord-embedded.dtsi b/arch/arm/dts/nord-embedded.dtsi new file mode 100644 index 000000000000..cde34cd349b4 --- /dev/null +++ b/arch/arm/dts/nord-embedded.dtsi @@ -0,0 +1,1835 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/* TEMPORARY: pending upstream sync */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "nord.dtsi" + +/ { + clk_virt: interconnect-clk-virt { + compatible = "qcom,nord-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,nord-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; +}; + +&crypto { + interconnects = <&aggre1_noc_tile MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + status = "enabled"; +}; + +&i2c0 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c2_default>; + pinctrl-names = "default"; +}; + +&i2c3 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c3_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c4_default>; + pinctrl-names = "default"; +}; + +&i2c5 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c5_default>; + pinctrl-names = "default"; +}; + +&i2c7 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c7_default>; + pinctrl-names = "default"; +}; + +&i2c8 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c8_default>; + pinctrl-names = "default"; +}; + +&i2c9 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c9_default>; + pinctrl-names = "default"; +}; + +&i2c10 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c10_default>; + pinctrl-names = "default"; +}; + +&i2c11 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c11_default>; + pinctrl-names = "default"; +}; + +&i2c12 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c12_default>; + pinctrl-names = "default"; +}; + +&i2c13 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c13_default>; + pinctrl-names = "default"; +}; + +&i2c14 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c14_default>; + pinctrl-names = "default"; +}; + +&i2c16 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c16_default>; + pinctrl-names = "default"; +}; + +&i2c17 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c17_default>; + pinctrl-names = "default"; +}; + +&i2c18 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c18_default>; + pinctrl-names = "default"; +}; + +&i2c19 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c19_default>; + pinctrl-names = "default"; +}; + +&i2c20 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_i2c20_default>; + pinctrl-names = "default"; +}; + +&qupv3_0 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_M_AHB_CLK>, + <&segcc SE_GCC_QUPV3_WRAP0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; +}; + +&qupv3_1 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_M_AHB_CLK>, + <&segcc SE_GCC_QUPV3_WRAP1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; +}; + +&qupv3_2 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_M_AHB_CLK>, + <&negcc NE_GCC_QUPV3_WRAP2_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; +}; + +&spi0 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi0_default>; + pinctrl-names = "default"; +}; + +&spi1 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi1_default>; + pinctrl-names = "default"; +}; + +&spi2 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi3_default>; + pinctrl-names = "default"; +}; + +&spi4 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi4_default>; + pinctrl-names = "default"; +}; + +&spi5 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi5_default>; + pinctrl-names = "default"; +}; + +&spi7 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi7_default>; + pinctrl-names = "default"; +}; + +&spi8 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi8_default>; + pinctrl-names = "default"; +}; + +&spi11 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi11_default>; + pinctrl-names = "default"; +}; + +&spi12 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi12_default>; + pinctrl-names = "default"; +}; + +&spi13 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc_tile MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi13_default>; + pinctrl-names = "default"; +}; + +&spi14 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi14_default>; + pinctrl-names = "default"; +}; + +&spi16 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi16_default>; + pinctrl-names = "default"; +}; + +&spi17 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi17_default>; + pinctrl-names = "default"; +}; + +&spi18 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi18_default>; + pinctrl-names = "default"; +}; + +&spi19 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi19_default>; + pinctrl-names = "default"; +}; + +&spi20 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc_tile MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + pinctrl-0 = <&qup_spi20_default>; + pinctrl-names = "default"; +}; + +&soc { + gcc: clock-controller@100000 { + compatible = "qcom,nord-gcc"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + clocks = <&bi_tcxo_div2>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,nord-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x1d200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,nord-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0xd200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,nord-system-noc"; + reg = <0x0 0x01680000 0x0 0x1c080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc_tile: interconnect@16c0000 { + compatible = "qcom,nord-aggre2-noc-tile"; + reg = <0x0 0x016c0000 0x0 0x1b400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,nord-aggre1-noc"; + reg = <0x0 0x016e0000 0x0 0x1c400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,nord-aggre2-noc"; + reg = <0x0 0x01700000 0x0 0x1b400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_IPA_CLK>; + }; + + aggre1_noc_tile: interconnect@1720000 { + compatible = "qcom,nord-aggre1-noc-tile"; + reg = <0x0 0x01720000 0x0 0x23400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&negcc NE_GCC_AGGRE_NOC_USB2_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,nord-mmss-noc"; + reg = <0x0 0x01780000 0x0 0x72800>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_cfg: interconnect@1ba0000 { + compatible = "qcom,nord-pcie-cfg"; + reg = <0x0 0x01ba0000 0x0 0x7200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_data_outbound: interconnect@1bc0000 { + compatible = "qcom,nord-pcie-data-outbound"; + reg = <0x0 0x01bc0000 0x0 0x17000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_data_inbound: interconnect@1c00000 { + compatible = "qcom,nord-pcie-data-inbound"; + reg = <0x0 0x01c00000 0x0 0x4b080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + ufs_mem_phy: phy@1d40000 { + compatible = "qcom,nord-qmp-ufs-phy", + "qcom,sm8650-qmp-ufs-phy"; + reg = <0x0 0x01d40000 0x0 0x2000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&negcc NE_GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>; + clock-names = "ref", + "ref_aux", + "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&negcc NE_GCC_UFS_MEM_PHY_GDSC>; + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ice: crypto@1d48000 { + compatible = "qcom,nord-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d48000 0x0 0x10000>; + clocks = <&negcc NE_GCC_UFS_PHY_ICE_CORE_CLK>, + <&negcc NE_GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&negcc NE_GCC_UFS_PHY_GDSC>; + }; + + hscnoc: interconnect@2000000 { + compatible = "qcom,nord-hscnoc"; + reg = <0x0 0x02000000 0x0 0xb22000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,nord-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&nwgcc NW_GCC_GPU_GPLL0_CLK_SRC>, + <&nwgcc NW_GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + hpass_ag_noc: interconnect@5fc0000 { + compatible = "qcom,nord-hpass-ag-noc"; + reg = <0x0 0x05fc0000 0x0 0x37080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + negcc: clock-controller@8900000 { + compatible = "qcom,nord-negcc"; + reg = <0x0 0x08900000 0x0 0xf4200>; + clocks = <&bi_tcxo_div2>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + segcc: clock-controller@8a00000 { + compatible = "qcom,nord-segcc"; + reg = <0x0 0x08a00000 0x0 0xf4200>; + clocks = <&bi_tcxo_div2>, + <&sleep_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + nwgcc: clock-controller@8b00000 { + compatible = "qcom,nord-nwgcc"; + reg = <0x0 0x08b00000 0x0 0xf4200>; + clocks = <&bi_tcxo_div2>, + <&sleep_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc1: clock-controller@8d00000 { + compatible = "qcom,nord-dispcc1"; + reg = <0x0 0x08d00000 0x0 0x20000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&nwgcc NW_GCC_DISP_1_AHB_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_min_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpu2cc: clock-controller@9890000 { + compatible = "qcom,nord-gpu2cc"; + reg = <0x0 0x09890000 0x0 0xa000>; + clocks = <&bi_tcxo_div2>, + <&negcc NE_GCC_GPU_2_GPLL0_CLK_SRC>, + <&negcc NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@9ce0000 { + compatible = "qcom,nord-camcc"; + reg = <0x0 0x09ce0000 0x0 0x20000>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + clocks = <&nwgcc NW_GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,nord-videocc"; + reg = <0x0 0x0aaf0000 0x0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&nwgcc NW_GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc0: clock-controller@af00000 { + compatible = "qcom,nord-dispcc0"; + reg = <0x0 0x0af00000 0x0 0x20000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&nwgcc NW_GCC_DISP_0_AHB_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_min_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + tcsrcc: clock-controller@f1d9000 { + compatible = "qcom,nord-tcsrcc", + "syscon"; + reg = <0x0 0x0f1d9000 0x0 0xf00c>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apps_rsc: rsc@18900000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, + <0x0 0x18920000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + label = "apps_rsc"; + power-domains = <&system_pd>; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,nord-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,nord-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level = ; + }; + }; + }; + }; + + nsp_data_noc_0: interconnect@1f200000 { + compatible = "qcom,nord-nsp-data-noc-0"; + reg = <0x0 0x1f200000 0x0 0x2a200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nsp_data_noc_1: interconnect@1f600000 { + compatible = "qcom,nord-nsp-data-noc-1"; + reg = <0x0 0x1f600000 0x0 0x2a200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nsp_data_noc_2: interconnect@1fa00000 { + compatible = "qcom,nord-nsp-data-noc-2"; + reg = <0x0 0x1fa00000 0x0 0x2a200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nsp_data_noc_3: interconnect@1fe00000 { + compatible = "qcom,nord-nsp-data-noc-3"; + reg = <0x0 0x1fe00000 0x0 0x2a200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; +}; + +&tlmm { + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio111", "gpio112"; + function = "qup0_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio111", "gpio112"; + function = "qup0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio113", "gpio114"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio115", "gpio116"; + function = "qup0_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio117", "gpio118"; + function = "qup0_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio121", "gpio122"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio123", "gpio124"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio125", "gpio126"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio127", "gpio128"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio129", "gpio130"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio131", "gpio132"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c12_default: qup-i2c12-default-state { + pins = "gpio133", "gpio134"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c13_default: qup-i2c13-default-state { + pins = "gpio137", "gpio138"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c14_default: qup-i2c14-default-state { + pins = "gpio139", "gpio140"; + function = "qup2_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c16_default: qup-i2c16-default-state { + pins = "gpio145", "gpio146"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c17_default: qup-i2c17-default-state { + pins = "gpio150", "gpio151"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c18_default: qup-i2c18-default-state { + pins = "gpio154", "gpio155"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c19_default: qup-i2c19-default-state { + pins = "gpio156", "gpio157"; + function = "qup2_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c20_default: qup-i2c20-default-state { + pins = "gpio158", "gpio159"; + function = "qup2_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + data-pins { + pins = "gpio109", "gpio111", "gpio112"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio110"; + function = "qup0_se0"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi1_default: qup-spi1-default-state { + data-pins { + pins = "gpio109", "gpio111", "gpio112"; + function = "qup0_se1"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio110"; + function = "qup0_se1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi2_default: qup-spi2-default-state { + data-pins { + pins = "gpio113", "gpio114", "gpio115"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio116"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi3_default: qup-spi3-default-state { + data-pins { + pins = "gpio113", "gpio115", "gpio116"; + function = "qup0_se3"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio114"; + function = "qup0_se3"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi4_default: qup-spi4-default-state { + data-pins { + pins = "gpio117", "gpio118", "gpio119"; + function = "qup0_se4"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio120"; + function = "qup0_se4"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi5_default: qup-spi5-default-state { + data-pins { + pins = "gpio109", "gpio121", "gpio122"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio110"; + function = "qup0_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi7_default: qup-spi7-default-state { + data-pins { + pins = "gpio123", "gpio124", "gpio125"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio126"; + function = "qup1_se0"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi8_default: qup-spi8-default-state { + data-pins { + pins = "gpio123", "gpio125", "gpio126"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio124"; + function = "qup1_se1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi11_default: qup-spi11-default-state { + data-pins { + pins = "gpio131", "gpio132", "gpio137"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio138"; + function = "qup1_se4"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi12_default: qup-spi12-default-state { + data-pins { + pins = "gpio133", "gpio134", "gpio135"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio136"; + function = "qup1_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi13_default: qup-spi13-default-state { + data-pins { + pins = "gpio131", "gpio137", "gpio138"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio132"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi14_default: qup-spi14-default-state { + data-pins { + pins = "gpio139", "gpio140", "gpio141"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio142"; + function = "qup2_se0"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi16_default: qup-spi16-default-state { + data-pins { + pins = "gpio145", "gpio146", "gpio147"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio148"; + function = "qup2_se2"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi17_default: qup-spi17-default-state { + data-pins { + pins = "gpio150", "gpio151", "gpio152"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio153"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi18_default: qup-spi18-default-state { + data-pins { + pins = "gpio143", "gpio154", "gpio155"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio144"; + function = "qup2_se4"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi19_default: qup-spi19-default-state { + data-pins { + pins = "gpio156", "gpio157", "gpio158"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio159"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_spi20_default: qup-spi20-default-state { + data-pins { + pins = "gpio156", "gpio158", "gpio159"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; + + cs-pins { + pins = "gpio157"; + function = "qup2_se6"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart0_default: qup-uart0-default-state { + pins = "gpio109", "gpio110"; + function = "qup0_se0"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart1_default: qup-uart1-default-state { + pins = "gpio109", "gpio110"; + function = "qup0_se1"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart2_default: qup-uart2-default-state { + pins = "gpio115", "gpio116"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart3_default: qup-uart3-default-state { + pins = "gpio113", "gpio114"; + function = "qup0_se3"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart4_default: qup-uart4-default-state { + pins = "gpio119", "gpio120"; + function = "qup0_se4"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + pins = "gpio109", "gpio110"; + function = "qup0_se5"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart7_default: qup-uart7-default-state { + pins = "gpio125", "gpio126"; + function = "qup1_se0"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart8_default: qup-uart8-default-state { + pins = "gpio123", "gpio124"; + function = "qup1_se1"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart9_default: qup-uart9-default-state { + pins = "gpio127", "gpio128"; + function = "qup1_se2"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart10_default: qup-uart10-default-state { + pins = "gpio129", "gpio130"; + function = "qup1_se3"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart11_default: qup-uart11-default-state { + pins = "gpio137", "gpio138"; + function = "qup1_se4"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart12_default: qup-uart12-default-state { + pins = "gpio135", "gpio136"; + function = "qup1_se5"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart13_default: qup-uart13-default-state { + pins = "gpio131", "gpio132"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart14_default: qup-uart14-default-state { + pins = "gpio141", "gpio142"; + function = "qup2_se0"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart15_default: qup-uart15-default-state { + pins = "gpio143", "gpio144"; + function = "qup2_se1"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart16_default: qup-uart16-default-state { + pins = "gpio147", "gpio148"; + function = "qup2_se2"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart17_default: qup-uart17-default-state { + pins = "gpio152", "gpio153"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart18_default: qup-uart18-default-state { + pins = "gpio143", "gpio144"; + function = "qup2_se4"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart19_default: qup-uart19-default-state { + pins = "gpio158", "gpio159"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart20_default: qup-uart20-default-state { + pins = "gpio156", "gpio157"; + function = "qup2_se6"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart0 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart1_default>; + pinctrl-names = "default"; +}; + +&uart2 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart2_default>; + pinctrl-names = "default"; +}; + +&uart3 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart3_default>; + pinctrl-names = "default"; +}; + +&uart4 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart4_default>; + pinctrl-names = "default"; +}; + +&uart5 { + clocks = <&segcc SE_GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart5_default>; + pinctrl-names = "default"; +}; + +&uart7 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart7_default>; + pinctrl-names = "default"; +}; + +&uart8 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart8_default>; + pinctrl-names = "default"; +}; + +&uart9 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart9_default>; + pinctrl-names = "default"; +}; + +&uart10 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; +}; + +&uart11 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart11_default>; + pinctrl-names = "default"; +}; + +&uart12 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart12_default>; + pinctrl-names = "default"; +}; + +&uart13 { + clocks = <&segcc SE_GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart13_default>; + pinctrl-names = "default"; +}; + +&uart14 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart14_default>; + pinctrl-names = "default"; +}; + +&uart15 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart15_default>; + pinctrl-names = "default"; +}; + +&uart16 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart16_default>; + pinctrl-names = "default"; +}; + +&uart17 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart17_default>; + pinctrl-names = "default"; +}; + +&uart18 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart18_default>; + pinctrl-names = "default"; +}; + +&uart19 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart19_default>; + pinctrl-names = "default"; +}; + +&uart20 { + clocks = <&negcc NE_GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart20_default>; + pinctrl-names = "default"; +}; + +&ufs_mem_hc { + clocks = <&negcc NE_GCC_UFS_PHY_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK>, + <&negcc NE_GCC_UFS_PHY_AHB_CLK>, + <&negcc NE_GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>, + <&negcc NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&negcc NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&negcc NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + resets = <&negcc NE_GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre1_noc_tile MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + power-domains = <&negcc NE_GCC_UFS_PHY_GDSC>; + operating-points-v2 = <&ufs_opp_table>; + required-opps = <&rpmhpd_opp_nom>; + qcom,ice = <&ice>; + #reset-cells = <1>; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-201500000 { + opp-hz = /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-403000000 { + opp-hz = /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; +}; diff --git a/arch/arm/dts/nord-gearvm.dtsi b/arch/arm/dts/nord-gearvm.dtsi new file mode 100644 index 000000000000..ea7c5d895bf8 --- /dev/null +++ b/arch/arm/dts/nord-gearvm.dtsi @@ -0,0 +1,2912 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/* TEMPORARY: pending upstream sync */ + +#include "nord.dtsi" + +&firmware { + scmi0: scmi-0 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem0>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi0_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi0_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi0_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi1: scmi-1 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem1>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi1_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi1_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi1_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi2: scmi-2 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem2>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi2_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi2_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi2_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi3: scmi-3 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem3>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi3_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi3_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi3_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi4: scmi-4 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem4>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi4_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi4_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi4_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi5: scmi-5 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem5>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi5_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi5_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi5_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi6: scmi-6 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem6>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi6_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi6_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi6_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi7: scmi-7 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem7>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi7_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi7_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi7_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi8: scmi-8 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem8>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi8_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi8_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi8_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi9: scmi-9 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem9>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi9_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi9_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi9_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi10: scmi-10 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem10>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi10_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi10_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi10_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi11: scmi-11 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem11>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi11_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi11_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi11_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi12: scmi-12 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem12>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi12_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi12_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi12_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi13: scmi-13 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem13>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi13_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi13_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi13_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi14: scmi-14 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem14>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi14_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi14_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi14_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi15: scmi-15 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem15>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi15_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi15_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi15_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi16: scmi-16 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem16>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi16_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi16_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi16_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi17: scmi-17 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem17>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi17_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi17_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi17_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi18: scmi-18 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem18>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi18_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi18_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi18_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi19: scmi-19 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem19>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi19_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi19_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi19_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi20: scmi-20 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem20>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi20_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi20_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi20_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi21: scmi-21 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem21>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi21_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi21_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi21_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi22: scmi-22 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem22>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi22_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi22_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi22_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi23: scmi-23 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem23>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi23_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + }; + + scmi24: scmi-24 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem24>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi24_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi24_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi24_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi25: scmi-25 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem25>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi25_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi25_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi25_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi26: scmi-26 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem26>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi26_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi26_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi26_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi27: scmi-27 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem27>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi27_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi27_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi27_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi28: scmi-28 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem28>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi28_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi28_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi28_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi29: scmi-29 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem29>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi29_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi29_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi29_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi30: scmi-30 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem30>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi30_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi30_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi30_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi31: scmi-31 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem31>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi31_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi31_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi31_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi32: scmi-32 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem32>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi32_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi32_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi32_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi33: scmi-33 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem33>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi33_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi33_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi33_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi34: scmi-34 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem34>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi34_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi34_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi34_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi35: scmi-35 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem35>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi35_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi35_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi35_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi36: scmi-36 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem36>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi36_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi36_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi36_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi37: scmi-37 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem37>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi37_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi37_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi37_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi38: scmi-38 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem38>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi38_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi38_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi38_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi39: scmi-39 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem39>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi39_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi39_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi39_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi40: scmi-40 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem40>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi40_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi40_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi40_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi41: scmi-41 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem41>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi41_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi41_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi41_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi42: scmi-42 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem42>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi42_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi42_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi42_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi43: scmi-43 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem43>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi43_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi43_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi43_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi44: scmi-44 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem44>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi44_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi44_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi44_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi45: scmi-45 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem45>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi45_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi45_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi45_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi46: scmi-46 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem46>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi46_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi46_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi46_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi47: scmi-47 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem47>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi47_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi47_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi47_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi48: scmi-48 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem48>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi48_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi48_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi48_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi49: scmi-49 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem49>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi49_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi49_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi49_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi50: scmi-50 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem50>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi50_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi50_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi50_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi51: scmi-51 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem51>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi51_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi51_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi51_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi52: scmi-52 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem52>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi52_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi52_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi52_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi53: scmi-53 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem53>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi53_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi53_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi53_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi54: scmi-54 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem54>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi54_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi54_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi54_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi55: scmi-55 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem55>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi55_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi55_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi55_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi56: scmi-56 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem56>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi56_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi56_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi56_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi57: scmi-57 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem57>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi57_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi57_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi57_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi58: scmi-58 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem58>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi58_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi58_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi58_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi59: scmi-59 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem59>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi59_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi59_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi59_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi60: scmi-60 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem60>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi60_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi60_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi60_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi61: scmi-61 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem61>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi61_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi61_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi61_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi62: scmi-62 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem62>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi62_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi62_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi62_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi63: scmi-63 { + compatible = "qcom,scmi-smc"; + arm,smc-id = <0xc6008012>; + shmem = <&shmem63>; + /* We expect the bootloader to update the IRQ number */ + interrupts = ; + interrupt-names = "a2p"; + #address-cells = <1>; + #size-cells = <0>; + arm,max-msg = <10>; + arm,max-msg-size = <256>; + arm,max-rx-timeout-ms = <3000>; + + status = "disabled"; + + scmi63_pd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi63_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi63_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; +}; + +&i2c0 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 0>, + <&scmi11_dvfs 0>; + power-domain-names = "power", + "perf"; +}; + +&i2c1 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 1>, + <&scmi11_dvfs 1>; + power-domain-names = "power", + "perf"; +}; + +&i2c2 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 2>, + <&scmi11_dvfs 2>; + power-domain-names = "power", + "perf"; +}; + +&i2c3 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 3>, + <&scmi11_dvfs 3>; + power-domain-names = "power", + "perf"; +}; + +&i2c4 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 4>, + <&scmi11_dvfs 4>; + power-domain-names = "power", + "perf"; +}; + +&i2c5 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 5>, + <&scmi11_dvfs 5>; + power-domain-names = "power", + "perf"; +}; + +&i2c7 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 7>, + <&scmi11_dvfs 7>; + power-domain-names = "power", + "perf"; +}; + +&i2c8 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 8>, + <&scmi11_dvfs 8>; + power-domain-names = "power", + "perf"; +}; + +&i2c9 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 9>, + <&scmi11_dvfs 9>; + power-domain-names = "power", + "perf"; +}; + +&i2c10 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 10>, + <&scmi11_dvfs 10>; + power-domain-names = "power", + "perf"; +}; + +&i2c11 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 11>, + <&scmi11_dvfs 11>; + power-domain-names = "power", + "perf"; +}; + +&i2c12 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 12>, + <&scmi11_dvfs 12>; + power-domain-names = "power", + "perf"; +}; + +&i2c13 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 13>, + <&scmi11_dvfs 13>; + power-domain-names = "power", + "perf"; +}; + +&i2c14 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 14>, + <&scmi11_dvfs 14>; + power-domain-names = "power", + "perf"; +}; + +&i2c15 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 15>, + <&scmi11_dvfs 15>; + power-domain-names = "power", + "perf"; +}; + +&i2c16 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 16>, + <&scmi11_dvfs 16>; + power-domain-names = "power", + "perf"; +}; + +&i2c17 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 17>, + <&scmi11_dvfs 17>; + power-domain-names = "power", + "perf"; +}; + +&i2c18 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 18>, + <&scmi11_dvfs 18>; + power-domain-names = "power", + "perf"; +}; + +&i2c19 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 19>, + <&scmi11_dvfs 19>; + power-domain-names = "power", + "perf"; +}; + +&i2c20 { + compatible = "qcom,sa8797p-geni-i2c", + "qcom,sa8255p-geni-i2c"; + power-domains = <&scmi11_pd 20>, + <&scmi11_dvfs 20>; + power-domain-names = "power", + "perf"; +}; + +&qupv3_0 { + compatible = "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup"; +}; + +&qupv3_1 { + compatible = "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup"; +}; + +&qupv3_2 { + compatible = "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup"; +}; + +&reserved_memory { + shmem0: scmi-shmem@d7600000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7600000 0x0 0x1000>; + no-map; + }; + + shmem1: scmi-shmem@d7601000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7601000 0x0 0x1000>; + no-map; + }; + + shmem2: scmi-shmem@d7602000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7602000 0x0 0x1000>; + no-map; + }; + + shmem3: scmi-shmem@d7603000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7603000 0x0 0x1000>; + no-map; + }; + + shmem4: scmi-shmem@d7604000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7604000 0x0 0x1000>; + no-map; + }; + + shmem5: scmi-shmem@d7605000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7605000 0x0 0x1000>; + no-map; + }; + + shmem6: scmi-shmem@d7606000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7606000 0x0 0x1000>; + no-map; + }; + + shmem7: scmi-shmem@d7607000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7607000 0x0 0x1000>; + no-map; + }; + + shmem8: scmi-shmem@d7608000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7608000 0x0 0x1000>; + no-map; + }; + + shmem9: scmi-shmem@d7609000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7609000 0x0 0x1000>; + no-map; + }; + + shmem10: scmi-shmem@d760a000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd760a000 0x0 0x1000>; + no-map; + }; + + shmem11: scmi-shmem@d760b000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd760b000 0x0 0x1000>; + no-map; + }; + + shmem12: scmi-shmem@d760c000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd760c000 0x0 0x1000>; + no-map; + }; + + shmem13: scmi-shmem@d760d000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd760d000 0x0 0x1000>; + no-map; + }; + + shmem14: scmi-shmem@d760e000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd760e000 0x0 0x1000>; + no-map; + }; + + shmem15: scmi-shmem@d760f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd760f000 0x0 0x1000>; + no-map; + }; + + shmem16: scmi-shmem@d7610000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7610000 0x0 0x1000>; + no-map; + }; + + shmem17: scmi-shmem@d7611000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7611000 0x0 0x1000>; + no-map; + }; + + shmem18: scmi-shmem@d7612000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7612000 0x0 0x1000>; + no-map; + }; + + shmem19: scmi-shmem@d7613000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7613000 0x0 0x1000>; + no-map; + }; + + shmem20: scmi-shmem@d7614000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7614000 0x0 0x1000>; + no-map; + }; + + shmem21: scmi-shmem@d7615000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7615000 0x0 0x1000>; + no-map; + }; + + shmem22: scmi-shmem@d7616000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7616000 0x0 0x1000>; + no-map; + }; + + shmem23: scmi-shmem@d7617000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7617000 0x0 0x1000>; + no-map; + }; + + shmem24: scmi-shmem@d7618000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7618000 0x0 0x1000>; + no-map; + }; + + shmem25: scmi-shmem@d7619000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7619000 0x0 0x1000>; + no-map; + }; + + shmem26: scmi-shmem@d761a000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd761a000 0x0 0x1000>; + no-map; + }; + + shmem27: scmi-shmem@d761b000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd761b000 0x0 0x1000>; + no-map; + }; + + shmem28: scmi-shmem@d761c000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd761c000 0x0 0x1000>; + no-map; + }; + + shmem29: scmi-shmem@d761d000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd761d000 0x0 0x1000>; + no-map; + }; + + shmem30: scmi-shmem@d761e000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd761e000 0x0 0x1000>; + no-map; + }; + + shmem31: scmi-shmem@d761f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd761f000 0x0 0x1000>; + no-map; + }; + + shmem32: scmi-shmem@d7620000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7620000 0x0 0x1000>; + no-map; + }; + + shmem33: scmi-shmem@d7621000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7621000 0x0 0x1000>; + no-map; + }; + + shmem34: scmi-shmem@d7622000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7622000 0x0 0x1000>; + no-map; + }; + + shmem35: scmi-shmem@d7623000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7623000 0x0 0x1000>; + no-map; + }; + + shmem36: scmi-shmem@d7624000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7624000 0x0 0x1000>; + no-map; + }; + + shmem37: scmi-shmem@d7625000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7625000 0x0 0x1000>; + no-map; + }; + + shmem38: scmi-shmem@d7626000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7626000 0x0 0x1000>; + no-map; + }; + + shmem39: scmi-shmem@d7627000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7627000 0x0 0x1000>; + no-map; + }; + + shmem40: scmi-shmem@d7628000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7628000 0x0 0x1000>; + no-map; + }; + + shmem41: scmi-shmem@d7629000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7629000 0x0 0x1000>; + no-map; + }; + + shmem42: scmi-shmem@d762a000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd762a000 0x0 0x1000>; + no-map; + }; + + shmem43: scmi-shmem@d762b000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd762b000 0x0 0x1000>; + no-map; + }; + + shmem44: scmi-shmem@d762c000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd762c000 0x0 0x1000>; + no-map; + }; + + shmem45: scmi-shmem@d762d000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd762d000 0x0 0x1000>; + no-map; + }; + + shmem46: scmi-shmem@d762e000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd762e000 0x0 0x1000>; + no-map; + }; + + shmem47: scmi-shmem@d762f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd762f000 0x0 0x1000>; + no-map; + }; + + shmem48: scmi-shmem@d7630000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7630000 0x0 0x1000>; + no-map; + }; + + shmem49: scmi-shmem@d7631000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7631000 0x0 0x1000>; + no-map; + }; + + shmem50: scmi-shmem@d7632000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7632000 0x0 0x1000>; + no-map; + }; + + shmem51: scmi-shmem@d7633000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7633000 0x0 0x1000>; + no-map; + }; + + shmem52: scmi-shmem@d7634000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7634000 0x0 0x1000>; + no-map; + }; + + shmem53: scmi-shmem@d7635000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7635000 0x0 0x1000>; + no-map; + }; + + shmem54: scmi-shmem@d7636000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7636000 0x0 0x1000>; + no-map; + }; + + shmem55: scmi-shmem@d7637000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7637000 0x0 0x1000>; + no-map; + }; + + shmem56: scmi-shmem@d7638000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7638000 0x0 0x1000>; + no-map; + }; + + shmem57: scmi-shmem@d7639000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd7639000 0x0 0x1000>; + no-map; + }; + + shmem58: scmi-shmem@d763a000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd763a000 0x0 0x1000>; + no-map; + }; + + shmem59: scmi-shmem@d763b000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd763b000 0x0 0x1000>; + no-map; + }; + + shmem60: scmi-shmem@d763c000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd763c000 0x0 0x1000>; + no-map; + }; + + shmem61: scmi-shmem@d763d000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd763d000 0x0 0x1000>; + no-map; + }; + + shmem62: scmi-shmem@d763e000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd763e000 0x0 0x1000>; + no-map; + }; + + shmem63: scmi-shmem@d763f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd763f000 0x0 0x1000>; + no-map; + }; +}; + +&spi0 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 0>, + <&scmi11_dvfs 0>; + power-domain-names = "power", + "perf"; +}; + +&spi1 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 1>, + <&scmi11_dvfs 1>; + power-domain-names = "power", + "perf"; +}; + +&spi2 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 2>, + <&scmi11_dvfs 2>; + power-domain-names = "power", + "perf"; +}; + +&spi3 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 3>, + <&scmi11_dvfs 3>; + power-domain-names = "power", + "perf"; +}; + +&spi4 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 4>, + <&scmi11_dvfs 4>; + power-domain-names = "power", + "perf"; +}; + +&spi5 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 5>, + <&scmi11_dvfs 5>; + power-domain-names = "power", + "perf"; +}; + +&spi7 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 7>, + <&scmi11_dvfs 7>; + power-domain-names = "power", + "perf"; +}; + +&spi8 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 8>, + <&scmi11_dvfs 8>; + power-domain-names = "power", + "perf"; +}; + +&spi11 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 11>, + <&scmi11_dvfs 11>; + power-domain-names = "power", + "perf"; +}; + +&spi12 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 12>, + <&scmi11_dvfs 12>; + power-domain-names = "power", + "perf"; +}; + +&spi13 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 13>, + <&scmi11_dvfs 13>; + power-domain-names = "power", + "perf"; +}; + +&spi14 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 14>, + <&scmi11_dvfs 14>; + power-domain-names = "power", + "perf"; +}; + +&spi15 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 15>, + <&scmi11_dvfs 15>; + power-domain-names = "power", + "perf"; +}; + +&spi16 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 16>, + <&scmi11_dvfs 16>; + power-domain-names = "power", + "perf"; +}; + +&spi17 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 17>, + <&scmi11_dvfs 17>; + power-domain-names = "power", + "perf"; +}; + +&spi18 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 18>, + <&scmi11_dvfs 18>; + power-domain-names = "power", + "perf"; +}; + +&spi19 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 19>, + <&scmi11_dvfs 19>; + power-domain-names = "power", + "perf"; +}; + +&spi20 { + compatible = "qcom,sa8797p-geni-spi", + "qcom,sa8255p-geni-spi"; + power-domains = <&scmi11_pd 20>, + <&scmi11_dvfs 20>; + power-domain-names = "power", + "perf"; +}; + +&uart0 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 0>, + <&scmi11_dvfs 0>; + power-domain-names = "power", + "perf"; +}; + +&uart1 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 1>, + <&scmi11_dvfs 1>; + power-domain-names = "power", + "perf"; +}; + +&uart2 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 2>, + <&scmi11_dvfs 2>; + power-domain-names = "power", + "perf"; +}; + +&uart3 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 3>, + <&scmi11_dvfs 3>; + power-domain-names = "power", + "perf"; +}; + +&uart4 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 4>, + <&scmi11_dvfs 4>; + power-domain-names = "power", + "perf"; +}; + +&uart5 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 5>, + <&scmi11_dvfs 5>; + power-domain-names = "power", + "perf"; +}; + +&uart7 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 7>, + <&scmi11_dvfs 7>; + power-domain-names = "power", + "perf"; +}; + +&uart8 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 8>, + <&scmi11_dvfs 8>; + power-domain-names = "power", + "perf"; +}; + +&uart9 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 9>, + <&scmi11_dvfs 9>; + power-domain-names = "power", + "perf"; +}; + +&uart10 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 10>, + <&scmi11_dvfs 10>; + power-domain-names = "power", + "perf"; +}; + +&uart11 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 11>, + <&scmi11_dvfs 11>; + power-domain-names = "power", + "perf"; +}; + +&uart12 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 12>, + <&scmi11_dvfs 12>; + power-domain-names = "power", + "perf"; +}; + +&uart13 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 13>, + <&scmi11_dvfs 13>; + power-domain-names = "power", + "perf"; +}; + +&uart14 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 14>, + <&scmi11_dvfs 14>; + power-domain-names = "power", + "perf"; +}; + +&uart15 { + compatible = "qcom,sa8797p-geni-debug-uart", + "qcom,sa8255p-geni-debug-uart"; + power-domains = <&scmi11_pd 15>, + <&scmi11_dvfs 15>; + power-domain-names = "power", + "perf"; +}; + +&uart16 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 16>, + <&scmi11_dvfs 16>; + power-domain-names = "power", + "perf"; +}; + +&uart17 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 17>, + <&scmi11_dvfs 17>; + power-domain-names = "power", + "perf"; +}; + +&uart18 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 18>, + <&scmi11_dvfs 18>; + power-domain-names = "power", + "perf"; +}; + +&uart19 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 19>, + <&scmi11_dvfs 19>; + power-domain-names = "power", + "perf"; +}; + +&uart20 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart"; + power-domains = <&scmi11_pd 20>, + <&scmi11_dvfs 20>; + power-domain-names = "power", + "perf"; +}; + +&ufs_mem_hc { + compatible = "qcom,sa8797p-ufshc", + "qcom,sa8255p-ufshc"; + power-domains = <&scmi3_pd 0>; +}; diff --git a/arch/arm/dts/nord-ride-u-boot.dtsi b/arch/arm/dts/nord-ride-u-boot.dtsi new file mode 100644 index 000000000000..66500a979e9d --- /dev/null +++ b/arch/arm/dts/nord-ride-u-boot.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/* + * nord-ride's DTS chain (nord-ride.dts -> nord-gearvm.dtsi -> nord.dtsi) + * carries only SCMI-brokered power-domains for UFS and has no clocks=/ + * phys= wiring on &ufs_mem_hc and no &ufs_mem_phy node at all. U-Boot's + * ufs-qcom.c hard-requires "core_clk_unipro" via clk_get_by_name() and + * clk_get_bulk() for the rest, so this overlay supplies the wiring that + * would otherwise already exist in a properly upstream-synced base DTS + * (see the sibling nord-embedded.dtsi, which wires the same underlying + * nord.dtsi silicon for the nord-rrd board). + */ + +#include + +/ { + negcc: clock-controller@8900000 { + compatible = "qcom,nord-negcc"; + reg = <0x0 0x08900000 0x0 0xf4200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + ufs_mem_phy: phy@1d40000 { + compatible = "qcom,nord-qmp-ufs-phy", + "qcom,sm8650-qmp-ufs-phy"; + reg = <0x0 0x01d40000 0x0 0x2000>; + + clocks = <&xo_board_clk>, + <&negcc NE_GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", + "ref_aux"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "okay"; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + }; + + sram: sram@146d8000 { + compatible = "qcom,nord-imem", "syscon", "simple-mfd"; + reg = <0x0 0x146d8000 0x0 0x1000>; + ranges = <0x0 0x0 0x146d8000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + }; + + /* IMEM boot cookie + TCSR HW version offsets */ + qcom_hwinfo: qcom-hwinfo { + compatible = "qcom,hwinfo"; + + imem = <&sram>; + imem-boot-cookie-offset = <0x0>; + + tcsr = <&tcsr>; + tcsr-hw-version-offset = <0x68000>; + }; + +}; + +&reserved_memory { + smem_region: smem-region@89b00000 { + reg = <0x0 0x89b00000 0x0 0x400000>; + no-map; + }; +}; + +&ufs_mem_hc { + compatible = "qcom,sa8797p-ufshc", + "qcom,sa8255p-ufshc", + "qcom,ufshc"; + + clocks = <&negcc NE_GCC_UFS_PHY_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK>, + <&negcc NE_GCC_UFS_PHY_AHB_CLK>, + <&negcc NE_GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&xo_board_clk>, + <&negcc NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&negcc NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&negcc NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + resets = <&negcc NE_GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; +}; + +&uart4 { + compatible = "qcom,sa8797p-geni-uart", + "qcom,sa8255p-geni-uart", + "qcom,geni-uart"; +}; + +&uart15 { + compatible = "qcom,sa8797p-geni-debug-uart", + "qcom,sa8255p-geni-debug-uart", + "qcom,geni-debug-uart"; +}; + +&qupv3_0 { + compatible = "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup", + "qcom,geni-se-qup"; +}; + +&qupv3_1 { + compatible = "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup", + "qcom,geni-se-qup"; +}; + +&qupv3_2 { + compatible = "qcom,sa8797p-geni-se-qup", + "qcom,sa8255p-geni-se-qup", + "qcom,geni-se-qup"; +}; diff --git a/arch/arm/dts/nord-ride.dts b/arch/arm/dts/nord-ride.dts new file mode 100644 index 000000000000..3ecfadc16f83 --- /dev/null +++ b/arch/arm/dts/nord-ride.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/* TEMPORARY: pending upstream sync */ + +/dts-v1/; + +#include "nord-gearvm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8797P Ride"; + compatible = "qcom,sa8797p-ride", "qcom,nord"; + + aliases { + serial0 = &uart15; + serial1 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; +}; + +&scmi3 { + status = "okay"; +}; + +&scmi11 { + status = "okay"; +}; + +&scmi15 { + status = "okay"; +}; + +&scmi23 { + status = "okay"; +}; + +&thermal_zones { + pmic_kobra_thermal: pmic-a-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 3>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_0_thermal: pmic-e-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 4>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_1_thermal: pmic-f-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 5>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_2_thermal: pmic-g-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 6>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_3_thermal: pmic-h-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 7>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_4_thermal: pmic-i-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 8>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_5_thermal: pmic-j-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 9>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_6_thermal: pmic-k-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 10>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_7_thermal: pmic-l-die-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 11>; + + trips { + trip0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pmic_kai_ufs_thermal: ufs-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&scmi23_sensor 0>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <5000>; + type = "critical"; + }; + }; + }; + + pmic_kai_sdram0_thermal: sdram0-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&scmi23_sensor 1>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <5000>; + type = "critical"; + }; + }; + }; + + pmic_kai_sdram1_thermal: sdram1-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&scmi23_sensor 2>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <5000>; + type = "critical"; + }; + }; + }; +}; + +&uart4 { + status = "okay"; +}; + +&uart15 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; +}; diff --git a/arch/arm/dts/nord-rrd.dts b/arch/arm/dts/nord-rrd.dts new file mode 100644 index 000000000000..ec32d0b3f63e --- /dev/null +++ b/arch/arm/dts/nord-rrd.dts @@ -0,0 +1,613 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/* TEMPORARY: pending upstream sync */ + +/dts-v1/; + +#include +#include + +#include "nord-embedded.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IQ10 RRD"; + compatible = "qcom,iq10-rrd", "qcom,nord"; + + aliases { + serial0 = &uart15; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult = <1>; + clock-div = <2>; + }; + }; + + ufs_vdd_hba: regulator-ufs-vdd-hba { + compatible = "regulator-fixed"; + regulator-name = "ufs_vdd_hba"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ufs_vccq2: regulator-ufs-vccq2 { + compatible = "regulator-fixed"; + regulator-name = "ufs_vccq2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; +}; + +&apps_rsc { + /* PMIC A - Kobra_MM (PMM8650AU) - SID 0x0, Bus E0 */ + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "A_E0"; + + /* LDO Regulators */ + vreg_l4a_1p2: ldo4 { + regulator-name = "vreg_l4a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a_1p2: ldo7 { + regulator-name = "vreg_l7a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a_1p8: ldo8 { + regulator-name = "vreg_l8a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + /* SMPS Regulators */ + vreg_s1a_vdd2h_l: smps1 { + regulator-name = "vreg_s1a_vdd2h_l"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s3a_1p8: smps3 { + regulator-name = "vreg_s3a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s5a_mv: smps5 { + regulator-name = "vreg_s5a_mv"; + regulator-min-microvolt = <1328000>; + regulator-max-microvolt = <1370000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s6a_vddq_l: smps6 { + regulator-name = "vreg_s6a_vddq_l"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_s8a_vdda_ebi: smps8 { + regulator-name = "vreg_s8a_vdda_ebi"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + }; + + /* PMIC E - Kai_MV - SID 0x4, Bus E0 */ + regulators-1 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "E_E0"; + + /* LDO Regulators */ + vreg_l1e_0p9: ldo1 { + regulator-name = "vreg_l1e_0p9"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3e_1p8: ldo3 { + regulator-name = "vreg_l3e_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + /* SMPS Regulators */ + vreg_s1e_nsp3: smps1 { + regulator-name = "vreg_s1e_nsp3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_s7e_mxa: smps7 { + regulator-name = "vreg_s7e_mxa"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + }; + + /* PMIC F - Kai_MV - SID 0x5, Bus E0 */ + regulators-2 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + /* LDO Regulators */ + vreg_l1f_vdd2l: ldo1 { + regulator-name = "vreg_l1f_vdd2l"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3f_vdd1: ldo3 { + regulator-name = "vreg_l3f_vdd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + /* SMPS Regulators */ + vreg_s1f_nsp1: smps1 { + regulator-name = "vreg_s1f_nsp1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_s7f_lv_sub: smps7 { + regulator-name = "vreg_s7f_lv_sub"; + regulator-min-microvolt = <1036000>; + regulator-max-microvolt = <1136000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_s8f_vddq_h: smps8 { + regulator-name = "vreg_s8f_vddq_h"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + /* PMIC G - Kai_MV - SID 0x6, Bus E0 */ + regulators-3 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "G_E0"; + + /* LDO Regulators */ + vreg_l2g_0p7: ldo2 { + regulator-name = "vreg_l2g_0p7"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + /* SMPS Regulators */ + vreg_s1g_nsp0: smps1 { + regulator-name = "vreg_s1g_nsp0"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_s5g_vdd2h_h: smps5 { + regulator-name = "vreg_s5g_vdd2h_h"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1150000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + }; + + /* PMIC H - Kai_MV - SID 0x7, Bus E0 */ + regulators-4 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "H_E0"; + + /* LDO Regulators */ + vreg_l1h_0p9: ldo1 { + regulator-name = "vreg_l1h_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2h_1p2: ldo2 { + regulator-name = "vreg_l2h_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + /* SMPS Regulators */ + vreg_s1h_nsp2: smps1 { + regulator-name = "vreg_s1h_nsp2"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_s5h_mxc: smps5 { + regulator-name = "vreg_s5h_mxc"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + /* PMIC I - Kai_MV - SID 0x8, Bus E0 */ + regulators-5 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "I_E0"; + + /* LDO Regulators */ + vreg_l1i_0p9: ldo1 { + regulator-name = "vreg_l1i_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3i_2p5: ldo3 { + regulator-name = "vreg_l3i_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + /* SMPS Regulators */ + vreg_s2i_gfx0: smps2 { + regulator-name = "vreg_s2i_gfx0"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_s7i_mm: smps7 { + regulator-name = "vreg_s7i_mm"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + /* PMIC J - Kai_MV - SID 0x9, Bus E0 */ + regulators-6 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "J_E0"; + + /* SMPS Regulators */ + vreg_s7j_gfx1: smps7 { + regulator-name = "vreg_s7j_gfx1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + /* PMIC K - Kai_MV - SID 0xA, Bus E0 */ + regulators-7 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "K_E0"; + + /* LDO Regulators */ + vreg_l1k_vdd2l: ldo1 { + regulator-name = "vreg_l1k_vdd2l"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2k_0p9: ldo2 { + regulator-name = "vreg_l2k_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3k_vdd1: ldo3 { + regulator-name = "vreg_l3k_vdd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + /* PMIC L - Kai_MV - SID 0xB, Bus E0 */ + regulators-8 { + compatible = "qcom,pmau0102-rpmh-regulators"; + qcom,pmic-id = "L_E0"; + + /* LDO Regulators */ + vreg_l3l_1p8: ldo3 { + regulator-name = "vreg_l3l_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + /* SMPS Regulators */ + vreg_s1l_nsp_mxc: smps1 { + regulator-name = "vreg_s1l_nsp_mxc"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_s2l_cx: smps2 { + regulator-name = "vreg_s2l_cx"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c12 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c18 { + clock-frequency = <400000>; + + status = "okay"; + + audio_dac: dac@31 { + compatible = "ti,pcm1681"; + reg = <0x31>; + + #sound-dai-cells = <0>; + }; +}; + +&i2c19 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&qupv3_0 { + firmware-name = "qcom/nord/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_1 { + firmware-name = "qcom/nord/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_2 { + firmware-name = "qcom/nord/qupv3fw.elf"; + + status = "okay"; +}; + +&spi16 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart15 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 181 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l3i_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l2i_1p2>; + vccq-max-microamp = <1200000>; + vccq2-supply = <&ufs_vccq2>; + vdd-hba-supply = <&ufs_vdd_hba>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1i_0p9>; + vdda-pll-supply = <&vreg_l2h_1p2>; + + status = "okay"; +}; diff --git a/arch/arm/dts/nord.dtsi b/arch/arm/dts/nord.dtsi new file mode 100644 index 000000000000..6706e5607cca --- /dev/null +++ b/arch/arm/dts/nord.dtsi @@ -0,0 +1,4606 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/* TEMPORARY: pending upstream sync */ + +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x0>; + enable-method = "psci"; + power-domains = <&cpu0_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_0>; + clocks = <&cpu_perf 0>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x100>; + enable-method = "psci"; + power-domains = <&cpu1_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_0>; + clocks = <&cpu_perf 0>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x200>; + enable-method = "psci"; + power-domains = <&cpu2_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_0>; + clocks = <&cpu_perf 0>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x300>; + enable-method = "psci"; + power-domains = <&cpu3_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_0>; + clocks = <&cpu_perf 0>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x400>; + enable-method = "psci"; + power-domains = <&cpu4_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_0>; + clocks = <&cpu_perf 0>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x500>; + enable-method = "psci"; + power-domains = <&cpu5_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_0>; + clocks = <&cpu_perf 0>; + }; + + cpu6: cpu@10000 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x10000>; + power-domains = <&cpu6_pd>; + power-domain-names = "psci"; + enable-method = "psci"; + next-level-cache = <&l2_10000>; + clocks = <&cpu_perf 1>; + + l2_10000: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu7: cpu@10100 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x10100>; + enable-method = "psci"; + power-domains = <&cpu7_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_10000>; + clocks = <&cpu_perf 1>; + }; + + cpu8: cpu@10200 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x10200>; + enable-method = "psci"; + power-domains = <&cpu8_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_10000>; + clocks = <&cpu_perf 1>; + }; + + cpu9: cpu@10300 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x10300>; + enable-method = "psci"; + power-domains = <&cpu9_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_10000>; + clocks = <&cpu_perf 1>; + }; + + cpu10: cpu@10400 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x10400>; + enable-method = "psci"; + power-domains = <&cpu10_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_10000>; + clocks = <&cpu_perf 1>; + }; + + cpu11: cpu@10500 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x10500>; + enable-method = "psci"; + power-domains = <&cpu11_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_10000>; + clocks = <&cpu_perf 1>; + }; + + cpu12: cpu@20000 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x20000>; + enable-method = "psci"; + power-domains = <&cpu12_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_20000>; + clocks = <&cpu_perf 2>; + + l2_20000: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu13: cpu@20100 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x20100>; + enable-method = "psci"; + power-domains = <&cpu13_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_20000>; + clocks = <&cpu_perf 2>; + }; + + cpu14: cpu@20200 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x20200>; + enable-method = "psci"; + power-domains = <&cpu14_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_20000>; + clocks = <&cpu_perf 2>; + }; + + cpu15: cpu@20300 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x20300>; + enable-method = "psci"; + power-domains = <&cpu15_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_20000>; + clocks = <&cpu_perf 2>; + }; + + cpu16: cpu@20400 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x20400>; + enable-method = "psci"; + power-domains = <&cpu16_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_20000>; + clocks = <&cpu_perf 2>; + }; + + cpu17: cpu@20500 { + device_type = "cpu"; + compatible = "qcom,oryon-1-5"; + reg = <0x0 0x20500>; + enable-method = "psci"; + power-domains = <&cpu17_pd>; + power-domain-names = "psci"; + next-level-cache = <&l2_20000>; + clocks = <&cpu_perf 2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + + core2 { + cpu = <&cpu8>; + }; + + core3 { + cpu = <&cpu9>; + }; + + core4 { + cpu = <&cpu10>; + }; + + core5 { + cpu = <&cpu11>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu12>; + }; + + core1 { + cpu = <&cpu13>; + }; + + core2 { + cpu = <&cpu14>; + }; + + core3 { + cpu = <&cpu15>; + }; + + core4 { + cpu = <&cpu16>; + }; + + core5 { + cpu = <&cpu17>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + core_off_c4: cluster-c4 { + compatible = "arm,idle-state"; + idle-state-name = "retention"; + entry-latency-us = <93>; + exit-latency-us = <129>; + min-residency-us = <560>; + arm,psci-suspend-param = <0x00000003>; + }; + }; + + domain-idle-states { + cluster_pwr_dn: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x01000053>; + entry-latency-us = <2150>; + exit-latency-us = <1983>; + min-residency-us = <9144>; + }; + + domain_ss3: domain-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x02000153>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + }; + }; + }; + + firmware: firmware { + scm { + compatible = "qcom,scm-nord", + "qcom,scm"; + qcom,dload-mode = <&tcsr 0x79000>; + }; + + pdp_scmi: scmi { + compatible = "arm,scmi"; + mboxes = <&pdp0_mbox 0>, + <&pdp0_mbox 11>, + <&pdp0_mbox 1>; + mbox-names = "tx", + "tx_reply", + "rx"; + shmem = <&pdp0_a2p>, + <&pdp0_p2a>; + #address-cells = <1>; + #size-cells = <0>; + + cpu_perf: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* Size will be updated by bootloader */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu0_pd: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu1_pd: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu2_pd: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu3_pd: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu4_pd: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu5_pd: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu6_pd: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu7_pd: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu8_pd: power-domain-cpu8 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu9_pd: power-domain-cpu9 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu10_pd: power-domain-cpu10 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu11_pd: power-domain-cpu11 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu12_pd: power-domain-cpu12 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu13_pd: power-domain-cpu13 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu14_pd: power-domain-cpu14 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu15_pd: power-domain-cpu15 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu16_pd: power-domain-cpu16 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cpu17_pd: power-domain-cpu17 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&core_off_c4>; + }; + + cluster0_pd: power-domain-cluster0 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_pwr_dn>; + }; + + cluster1_pd: power-domain-cluster1 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_pwr_dn>; + }; + + cluster2_pd: power-domain-cluster2 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_pwr_dn>; + }; + + system_pd: power-domain-system { + #power-domain-cells = <0>; + domain-idle-states = <&domain_ss3>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpucp_scandump_mem: cpucp-scandump-region@80000000 { + reg = <0x0 0x80000000 0x0 0x800000>; + no-map; + }; + + tme_sail_mem: tme-sail-region@81ff0000 { + reg = <0x0 0x81ff0000 0x0 0x10000>; + no-map; + }; + + tz_sail_mailbox_mem: tz-sail-mailbox-region@82000000 { + reg = <0x0 0x82000000 0x0 0x8000>; + no-map; + }; + + sail_mailbox_mem: sail-mailbox-region@82008000 { + reg = <0x0 0x82008000 0x0 0x1f8000>; + no-map; + }; + + sail_ota_mem: sail-ota-region@82200000 { + reg = <0x0 0x82200000 0x0 0x5ff000>; + no-map; + }; + + sail_vdt_mem: sail-vdt-region@827ff000 { + reg = <0x0 0x827ff000 0x0 0x1000>; + no-map; + }; + + hyp_mem: hyp-region@82800000 { + reg = <0x0 0x82800000 0x0 0x2400000>; + no-map; + }; + + deepsleep_mem: deepsleep-region@84c00000 { + reg = <0x0 0x84c00000 0x0 0x800000>; + no-map; + }; + + deepsleep_backup_mem: deepsleep-backup-region@86a00000 { + reg = <0x0 0x86a00000 0x0 0x200000>; + no-map; + }; + + soccp_fe_vm_0: soccp-fe-vm-0-region@86c00000 { + reg = <0x0 0x86c00000 0x0 0xac000>; + no-map; + }; + + soccp_fe_vm_1: soccp-fe-vm-1-region@86cac000 { + reg = <0x0 0x86cac000 0x0 0x18d000>; + no-map; + }; + + soccp_fe_vm_2: soccp-fe-vm-2-region@86e39000 { + reg = <0x0 0x86e39000 0x0 0x1c7000>; + no-map; + }; + + tme_crash_dump_mem: tme-crash-dump-region@87000000 { + reg = <0x0 0x87000000 0x0 0xa0000>; + no-map; + }; + + tme_log_mem: tme-log-region@87140000 { + reg = <0x0 0x87140000 0x0 0x4000>; + no-map; + }; + + aop_cmd_db_p_mem: aop-cmd-db-p-region@87148000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x87148000 0x0 0x20000>; + no-map; + }; + + nsp_sync_buffer_mem: nsp-sync-buffer-region@871ff000 { + reg = <0x0 0x871ff000 0x0 0x1000>; + no-map; + }; + + ddr_training_checksum_data_mem: ddr-training-checksum-data-region@87200000 { + reg = <0x0 0x87200000 0x0 0x2000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog-region@87202000 { + reg = <0x0 0x87202000 0x0 0x60000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump-region@87262000 { + reg = <0x0 0x87262000 0x0 0x1c0000>; + no-map; + }; + + uefi_log: uefi-log@87442000 { + reg = <0x0 0x87442000 0x0 0x10000>; + no-map; + }; + + secdata_apss_mem: secdata-apss-region@87452000 { + reg = <0x0 0x87452000 0x0 0x1000>; + no-map; + }; + + antireplay_emulation_mem: antireplay-emulation-region@87453000 { + reg = <0x0 0x87453000 0x0 0x1000>; + no-map; + }; + + soccp_sdi_mem: soccp-sdi-region@87454000 { + reg = <0x0 0x87454000 0x0 0x40000>; + no-map; + }; + + hyp_mem_database_mem: hyp-mem-database-region@87494000 { + reg = <0x0 0x87494000 0x0 0x60000>; + no-map; + }; + + pmic_mini_dump_mem: pmic-mini-dump-region@874f4000 { + reg = <0x0 0x874f4000 0x0 0x80000>; + no-map; + }; + + qup_fw_mem: qup-fw-region@87574000 { + reg = <0x0 0x87574000 0x0 0x20000>; + no-map; + }; + + softsku_mem: softsku-region@87594000 { + reg = <0x0 0x87594000 0x0 0x9000>; + no-map; + }; + + resource_scheduler_mem: resource-scheduler-region@8759d000 { + reg = <0x0 0x8759d000 0x0 0x20000>; + no-map; + }; + + pdp_ns_mem: pdp-ns-mem-region@87600000 { + reg = <0x0 0x87600000 0x0 0x8000>, + <0x0 0x87609000 0x0 0x1f7000>; + no-map; + }; + + pdp0_p2a: scmi-shmem@87608000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x87608000 0x0 0x80>; + no-map; + }; + + pdp0_a2p: scmi-shmem@87608180 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x87608180 0x0 0x80>; + no-map; + }; + + tz_stat_mem: tz-stat-region@87a00000 { + reg = <0x0 0x87a00000 0x0 0x100000>; + no-map; + }; + + qdss_apps_mem: qdss-apps-region@87b00000 { + reg = <0x0 0x87b00000 0x0 0x2000000>; + no-map; + }; + + global_sync_mem: global-sync-region@89f00000 { + reg = <0x0 0x89f00000 0x0 0x400000>; + no-map; + }; + + tzffi_mem: tzffi-region@8a300000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x8a300000 0x0 0x1400000>; + no-map; + }; + + gunyah_md_mem: gunyah-md-region@8b700000 { + reg = <0x0 0x8b700000 0x0 0x80000>; + no-map; + }; + + flashless_qntm_tool_mem: flashless-qntm-tool-region@8b780000 { + reg = <0x0 0x8b780000 0x0 0x182000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@8bb00000 { + reg = <0x0 0x8bb00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@8bb10000 { + reg = <0x0 0x8bb10000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode-region@8bb1a000 { + reg = <0x0 0x8bb1a000 0x0 0x2000>; + no-map; + }; + + gpu_microcode_2_mem: gpu-microcode-2-region@8bb1c000 { + reg = <0x0 0x8bb1c000 0x0 0x2000>; + no-map; + }; + + soccp_mem: soccp-region@8bc00000 { + reg = <0x0 0x8bc00000 0x0 0x300000>; + no-map; + }; + + cvp_mem: cvp-region@8d100000 { + reg = <0x0 0x8d100000 0x0 0x800000>; + no-map; + }; + + cdsp0_mem: cdsp0-region@8d900000 { + reg = <0x0 0x8d900000 0x0 0x2300000>; + no-map; + }; + + cdsp1_mem: cdsp1-region@8fc00000 { + reg = <0x0 0x8fc00000 0x0 0x2300000>; + no-map; + }; + + cdsp2_mem: cdsp2-region@91f00000 { + reg = <0x0 0x91f00000 0x0 0x2300000>; + no-map; + }; + + cdsp3_mem: cdsp3-region@94200000 { + reg = <0x0 0x94200000 0x0 0x2300000>; + no-map; + }; + + hpass_dsp0_mem: hpass-dsp0-region@96500000 { + reg = <0x0 0x96500000 0x0 0x2800000>; + no-map; + }; + + hpass_dsp1_mem: hpass-dsp1-region@98d00000 { + reg = <0x0 0x98d00000 0x0 0x2800000>; + no-map; + }; + + hpass_dsp2_mem: hpass-dsp2-region@9b500000 { + reg = <0x0 0x9b500000 0x0 0x2800000>; + no-map; + }; + + q6_cdsp0_dtb_mem: q6-cdsp0-dtb-region@9dd00000 { + reg = <0x0 0x9dd00000 0x0 0x80000>; + no-map; + }; + + q6_cdsp1_dtb_mem: q6-cdsp1-dtb-region@9dd80000 { + reg = <0x0 0x9dd80000 0x0 0x80000>; + no-map; + }; + + q6_cdsp2_dtb_mem: q6-cdsp2-dtb-region@9de00000 { + reg = <0x0 0x9de00000 0x0 0x80000>; + no-map; + }; + + q6_cdsp3_dtb_mem: q6-cdsp3-dtb-region@9de80000 { + reg = <0x0 0x9de80000 0x0 0x80000>; + no-map; + }; + + hpass_dsp0_dtb_mem: hpass-dsp0-dtb-region@9df00000 { + reg = <0x0 0x9df00000 0x0 0x80000>; + no-map; + }; + + hpass_dsp1_dtb_mem: hpass-dsp1-dtb-region@9df80000 { + reg = <0x0 0x9df80000 0x0 0x80000>; + no-map; + }; + + hpass_dsp2_dtb_mem: hpass-dsp2-dtb-region@9e000000 { + reg = <0x0 0x9e000000 0x0 0x100000>; + no-map; + }; + + camera_icp_1_mem: camera-icp-1-region@9e100000 { + reg = <0x0 0x9e100000 0x0 0x800000>; + no-map; + }; + + camera_icp_2_mem: camera-icp-2-region@9e900000 { + reg = <0x0 0x9e900000 0x0 0x800000>; + no-map; + }; + + camera_qup_1_mem: camera-qup-1-region@9f100000 { + reg = <0x0 0x9f100000 0x0 0x200000>; + no-map; + }; + + camera_qup_2_mem: camera-qup-2-region@9f300000 { + reg = <0x0 0x9f300000 0x0 0x200000>; + no-map; + }; + + video_mem: video-region@9f500000 { + reg = <0x0 0x9f500000 0x0 0xc00000>; + no-map; + }; + + pil_umd_reserved: mdt-load-region@a0100000 { + reg = <0x0 0xa0100000 0x0 0x100000>; + no-map; + }; + + mm_dspq: mm-dspq-region@ba200000 { + reg = <0x0 0xba200000 0x0 0x200000>; + no-map; + }; + + display_config_reserved: display-config-region@ba400000 { + reg = <0x0 0xba400000 0x0 0xa00000>; + no-map; + }; + + mm_calibration_data_mem: mm-calibration-data-region@bae00000 { + reg = <0x0 0xbae00000 0x0 0x800000>; + no-map; + }; + + audio_config_mem: audio-config-region@bb600000 { + reg = <0x0 0xbb600000 0x0 0xa00000>; + no-map; + }; + + dare_tz_mem: dare-tz-region@bc000000 { + reg = <0x0 0xbc000000 0x0 0xa300000>; + no-map; + }; + + hpass_rpc_remote_heap_mem: hpass-rpc-remote-heap-region@d4600000 { + reg = <0x0 0xd4600000 0x0 0x800000>; + no-map; + }; + + mdf_mem: mdf-region@d4e00000 { + reg = <0x0 0xd4e00000 0x0 0x2000000>; + no-map; + }; + + firmware_mem: firmware-region@d6e00000 { + reg = <0x0 0xd6e00000 0x0 0x800000>; + no-map; + }; + + firmware_shared_mem: firmware-shared-region@d7650000 { + reg = <0x0 0xd7650000 0x0 0x180000>; + no-map; + }; + + firmware_logs_mem: firmware-logs-region@d77d0000 { + reg = <0x0 0xd77d0000 0x0 0x20000>; + no-map; + }; + + sail_p_mem: sail-p-region@8c0000000 { + reg = <0x8 0xc0000000 0x0 0x8000000>; + no-map; + }; + + reserved_mem2: reserved-region@8c8000000 { + reg = <0x8 0xc8000000 0x0 0x18000000>; + no-map; + }; + + dump_mem: mem-dump-region { + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + size = <0x0 0x79b0000>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0 0 0 0 0x10 0>; + ranges = <0 0 0 0 0x10 0>; + + qupv3_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu_0 0x15a3 0x0>; + ranges; + + i2c14: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi14: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart14: serial@880000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c15: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi15: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart15: serial@884000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c16: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi16: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart16: serial@888000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c17: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi17: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart17: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c18: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi18: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart18: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c19: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi19: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart19: serial@894000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c20: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi20: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart20: serial@898000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + }; + + qupv3_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu_2 0x1003 0x0>; + ranges; + + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00980000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00980000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart0: serial@980000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00980000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00984000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00984000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart1: serial@984000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00984000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00988000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00988000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart2: serial@988000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00988000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0098c000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0098c000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart3: serial@98c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x0098c000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00990000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00990000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart4: serial@990000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00990000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00994000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00994000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart5: serial@994000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00994000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + }; + + qupv3_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu_2 0x1043 0x0>; + ranges; + + i2c7: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi7: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart7: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c8: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart8: serial@a84000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c9: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart9: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a88000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c10: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart10: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c11: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi11: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart11: serial@a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c12: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi12: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart12: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + i2c13: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi13: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + + uart13: serial@a98000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = ; + + status = "disabled"; + }; + }; + + rng: rng@10c3000 { + compatible = "qcom,nord-trng", + "qcom,trng"; + reg = <0x0 0x010c3000 0x0 0x1000>; + }; + + ufs_mem_hc: ufshc@1d44000 { + compatible = "qcom,nord-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d44000 0x0 0x3000>, + <0x0 0x01d60000 0x0 0x15000>; + reg-names = "std", + "mcq"; + interrupts = ; + lanes-per-direction = <2>; + iommus = <&apps_smmu_0 0x14c0 0x0>; + dma-coherent; + msi-parent = <&gic_its 0x14c0>; + + status = "disabled"; + }; + + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = ; + #dma-cells = <1>; + iommus = <&apps_smmu_0 0x1689 0>; + qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,nord-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu_0 0x1689 0>; + + /* It stops nord-gearvm variant from booting to console */ + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1f60000 { + compatible = "qcom,nord-tcsr", + "syscon"; + reg = <0x0 0x01f60000 0x0 0xa0000>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,nord-pdc", + "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x10000>; + qcom,pdc-ranges = <0 745 43>, + <67 543 31>, + <98 609 32>, + <130 717 12>, + <142 251 5>, + <147 796 16>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c22c000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c22d000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c22e000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c22f000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens4: thermal-sensor@c230000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c230000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens5: thermal-sensor@c231000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c231000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens6: thermal-sensor@c232000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c232000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens7: thermal-sensor@c233000 { + compatible = "qcom,nord-tsens", + "qcom,tsens-v2"; + reg = <0x0 0x0c233000 0x0 0x1000>, + <0x0 0x0c229000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,nord-tlmm"; + reg = <0x0 0x0f100000 0x0 0xc0000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 181>; + wakeup-parent = <&pdc>; + }; + + apps_smmu_0: iommu@15a00000 { + compatible = "qcom,nord-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15a00000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apps_smmu_1: iommu@15c00000 { + compatible = "qcom,nord-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15c00000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apps_smmu_2: iommu@15e00000 { + compatible = "qcom,nord-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15e00000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x480000>; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17040000 0x0 0x40000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + pdp0_mbox: mailbox@17610000 { + compatible = "qcom,nord-cpucp-mbox", + "qcom,x1e80100-cpucp-mbox"; + reg = <0x0 0x17610000 0x0 0x4c08>, + <0x0 0x19980000 0x0 0x300>; + #mbox-cells = <1>; + interrupts = ; + }; + + memtimer: timer@17810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17810000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17811000 { + reg = <0x17811000 0x1000>, + <0x17812000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@17813000 { + reg = <0x17813000 0x1000>; + interrupts = ; + frame-number = <1>; + + status = "disabled"; + }; + + frame@17815000 { + reg = <0x17815000 0x1000>; + interrupts = ; + frame-number = <2>; + + status = "disabled"; + }; + + frame@17817000 { + reg = <0x17817000 0x1000>; + interrupts = ; + frame-number = <3>; + + status = "disabled"; + }; + + frame@17819000 { + reg = <0x17819000 0x1000>; + interrupts = ; + frame-number = <4>; + + status = "disabled"; + }; + + frame@1781b000 { + reg = <0x1781b000 0x1000>; + interrupts = ; + frame-number = <5>; + + status = "disabled"; + }; + + frame@1781d000 { + reg = <0x1781d000 0x1000>; + interrupts = ; + frame-number = <6>; + + status = "disabled"; + }; + }; + + watchdog@17826000 { + compatible = "qcom,apss-wdt-nord", + "qcom,kpss-wdt"; + reg = <0x0 0x17826000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + thermal_zones: thermal-zones { + ddr-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-4-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-5-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpullc-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-4-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-5-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpullc-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-4-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-0-5-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpullc-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-4-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-1-5-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpullc-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 14>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + amux-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-3-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-4-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-5-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpullc-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhvx-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhmx-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhvx-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhmx-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhvx-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhmx-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + pcie-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + amux-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-3-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-4-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpu-2-5-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cpullc-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhvx-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhmx-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhvx-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhmx-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhvx-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + audhmx-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + pcie-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-0-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-0-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-0-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-1-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-1-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-1-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-2-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-2-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-2-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-3-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-3-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-3-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 14>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-3-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens4 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-0-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-0-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-0-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-1-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-1-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-1-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-2-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-2-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-2-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-3-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsphvx-3-3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-3-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 14>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + nsp-3-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens5 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + amux-6-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpu-0-0-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cv-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + video-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + camera-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-2-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-3-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-0-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-2-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 14>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpu-0-1-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens6 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + amux-7-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 0>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-0-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 1>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 2>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-2-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 3>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpu-0-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 4>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 5>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpu-1-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 6>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + cv-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 7>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + video-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 8>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + camera-2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 9>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-2-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 10>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + ddr-3-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 11>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 12>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-1-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 13>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpuss-2-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 14>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + + gpu-0-0-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens7 15>; + + trips { + trip-point0 { + temperature = <105000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + }; + }; +}; diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 29567b66ff9a..0e1a1117ff29 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -26,6 +26,9 @@ config SYS_MALLOC_LEN config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x80000000 +config REMAKE_ELF_LDSCRIPT + default "arch/arm/mach-snapdragon/u-boot-elf-snapdragon.lds" + config SYS_BOARD string "Snapdragon SoCs based board" help diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index b749b05567d3..8cdfe206387f 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -53,7 +53,12 @@ enum qcom_memmap_source qcom_memmap_source __section(".data") = 0; DIV_ROUND_UP(CONFIG_EFI_PARTITION_ENTRIES_NUMBERS * GPT_ENTRY_SIZE, \ GPT_PTE_SECTOR_SIZE) -static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } }; +/* + * +2 for the peripheral block entry and the terminator, and another + * +CONFIG_NR_DRAM_BANKS so each inter-bank gap can get its own entry + * (see build_mem_map()). + */ +static struct mm_region rbx_mem_map[2 * CONFIG_NR_DRAM_BANKS + 2] = { { 0 } }; struct mm_region *mem_map = rbx_mem_map; @@ -528,6 +533,7 @@ int board_late_init(void) static void build_mem_map(void) { int i, j; + phys_addr_t prev_end; /* * Ensure the peripheral block is sized to correctly cover the address range @@ -543,12 +549,38 @@ static void build_mem_map(void) PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; - for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->dram[j].size; i++, j++) { + /* + * Emit each DRAM bank, plus a device-memory entry for any gap between + * it and the previous bank. Gaps are firmware-carved regions not + * reported in the SMEM usable-RAM table, so they must not be folded + * into a NORMAL/cacheable bank entry: treating them as MT_DEVICE_NGNRNE + * (matching the pre-DRAM peripheral entry above) stops speculative + * accesses instead of silently reading/caching whatever firmware left + * there. + */ + i = 1; + prev_end = gd->dram[0].start; + for (j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->dram[j].size; j++) { + if (gd->dram[j].start > prev_end) { + mem_map[i].phys = prev_end; + mem_map[i].virt = mem_map[i].phys; + mem_map[i].size = gd->dram[j].start - prev_end; + mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_RO; + i++; + if (i >= ARRAY_SIZE(rbx_mem_map) - 1) + break; + } + mem_map[i].phys = gd->dram[j].start; mem_map[i].virt = mem_map[i].phys; mem_map[i].size = gd->dram[j].size; mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \ PTE_BLOCK_INNER_SHARE; + prev_end = gd->dram[j].start + gd->dram[j].size; + i++; } mem_map[i].phys = UINT64_MAX; @@ -580,7 +612,7 @@ static int fdt_cmp_res(const void *v1, const void *v2) return res1->start - res2->start; } -#define N_RESERVED_REGIONS 64 +#define N_RESERVED_REGIONS 256 /* Map and unmap reserved memory regions as appropriate. * Mark all no-map regions as PTE_TYPE_FAULT to prevent speculative access. @@ -628,11 +660,25 @@ static void configure_reserved_memory(void) */ ptr = fdt_getprop(gd->fdt_blob, rmem, "reg", NULL); if (ptr) { - /* Qualcomm devices use #address/size-cells = <2> but all reserved regions are within - * the 32-bit address space. So we can cheat here for speed. + u64 rstart, rend; + + /* Qualcomm devices use #address/size-cells = <2>. Reserved regions + * are within the 32-bit space, so the low cells hold addr/size. + */ + rstart = fdt32_to_cpu(ptr[1]); + rend = rstart + fdt32_to_cpu(ptr[3]); + + /* The MMU works at page (4K) granularity: mmu_change_region_attr_nobreak() + * cannot map a sub-page region and would spin forever on one (e.g. the + * 0x80-byte SCMI shmem mailboxes two-to-a-page at 0x87608000/0x87608180). + * Page-align every region here so we protect the pages *containing* each + * carveout. All sub-page reserved regions on Qualcomm SoCs seen so far are + * driver-accessible (VALID), so rounding the enclosing page to VALID is + * safe; a sub-page no-map (FAULT) region sharing a page with usable RAM + * would need VALID-wins precedence handling — none exist on this SoC. */ - res[i].start = fdt32_to_cpu(ptr[1]); - res[i].size = fdt32_to_cpu(ptr[3]); + res[i].start = rstart & ~((u64)SZ_4K - 1); + res[i].size = ALIGN(rend, SZ_4K) - res[i].start; res[i].attrs = attrs; i++; } diff --git a/arch/arm/mach-snapdragon/capsule_update.c b/arch/arm/mach-snapdragon/capsule_update.c index 9fe951598e78..77eae492b731 100644 --- a/arch/arm/mach-snapdragon/capsule_update.c +++ b/arch/arm/mach-snapdragon/capsule_update.c @@ -641,9 +641,9 @@ void qcom_configure_capsule_updates(void) } memset(partitions, 0, sizeof(qcom_partitions)); - if (IS_ENABLED(CONFIG_SCSI) && !uclass_id_count(UCLASS_SCSI)) { + if (IS_ENABLED(CONFIG_SCSI)) { /* Scan for SCSI devices, unless already scanned earlier in boot */ - ret = scsi_scan(false); + ret = scsi_scan_new(false); if (ret) { debug("Failed to scan SCSI devices: %d\n", ret); return; diff --git a/arch/arm/mach-snapdragon/u-boot-elf-snapdragon.lds b/arch/arm/mach-snapdragon/u-boot-elf-snapdragon.lds new file mode 100644 index 000000000000..fe29e175b2dd --- /dev/null +++ b/arch/arm/mach-snapdragon/u-boot-elf-snapdragon.lds @@ -0,0 +1,17 @@ +ENTRY(CONFIG_PLATFORM_ELFENTRY) +SECTIONS +{ + . = CONFIG_PLATFORM_ELFENTRY; + + .data : { + *(.data*) + /* + * Pad the LOAD segment out to a 4K boundary. TME's IMGAUTH + * checks not just p_align/p_offset but that p_filesz itself + * is a multiple of 4K (it hashes/verifies in fixed 4K + * blocks) - the raw u-boot.bin blob wrapped in here is not + * page-sized on its own. + */ + . = ALIGN(0x1000); + } +} diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 4c350ea2fb1d..f8274f943578 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -65,6 +65,11 @@ CONFIG_CLK_STUB=y CONFIG_CLK_QCOM_APQ8016=y CONFIG_CLK_QCOM_APQ8096=y CONFIG_CLK_QCOM_MILOS=y +CONFIG_CLK_QCOM_NORD=y +CONFIG_CLK_QCOM_NORD_NEGCC=y +CONFIG_CLK_QCOM_NORD_SEGCC=y +CONFIG_CLK_QCOM_NORD_NWGCC=y +CONFIG_CLK_QCOM_NORD_TCSRCC=y CONFIG_CLK_QCOM_QCM2290=y CONFIG_CLK_QCOM_QCS404=y CONFIG_CLK_QCOM_QCS615=y @@ -108,6 +113,7 @@ CONFIG_QCOM_HYP_SMMU=y CONFIG_MISC=y CONFIG_NVMEM=y CONFIG_QCOM_GENI=y +# CONFIG_QCOM_GENI_FW_LOAD is not set CONFIG_I2C_EEPROM=y CONFIG_SYS_MMC_MAX_BLK_COUNT=16384 CONFIG_MMC_HS400_SUPPORT=y diff --git a/configs/qcom_nord_defconfig b/configs/qcom_nord_defconfig new file mode 100644 index 000000000000..b5e95db921b4 --- /dev/null +++ b/configs/qcom_nord_defconfig @@ -0,0 +1,23 @@ +# Configuration for building U-Boot to be flashed +# to the uefi partition of Nord dev boards with +# the "Linux Embedded" partition layout (which have +# a dedicated "uefi" partition for edk2/U-Boot) + +#include "qcom_defconfig" + +# Otherwise buildman thinks this isn't an ARM platform +CONFIG_ARM=y + +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0x884000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=14745600 + +# CONFIG_OF_UPSTREAM is not set +CONFIG_DEFAULT_DEVICE_TREE="nord-ride" + +CONFIG_REMAKE_ELF=y + +# Address where U-Boot will be loaded +CONFIG_TEXT_BASE=0xD8D00000 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 7f990b7ecd8f..6db258a29cec 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -63,6 +63,49 @@ config CLK_QCOM_MILOS on the Snapdragon Milos SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_NORD + bool "Qualcomm Nord GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon Nord SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + +config CLK_QCOM_NORD_NEGCC + bool "Qualcomm Nord NEGCC" + select CLK_QCOM + help + Say Y here to enable support for the North-East Global Clock + Controller on the Snapdragon Nord SoC. This driver supports the + UFS, USB, and QUPv3 clocks and resets exposed by the NEGCC + hardware block. + +config CLK_QCOM_NORD_SEGCC + bool "Qualcomm Nord SEGCC" + select CLK_QCOM + help + Say Y here to enable support for the South-East Global Clock + Controller on the Snapdragon Nord SoC. This driver supports the + EMAC and QUPv3 clocks and resets exposed by the SEGCC hardware + block. + +config CLK_QCOM_NORD_NWGCC + bool "Qualcomm Nord NWGCC" + select CLK_QCOM + help + Say Y here to enable support for the North-West Global Clock + Controller on the Snapdragon Nord SoC. This driver supports the + camera, display, EVA, video, and GPU clocks and resets exposed by + the NWGCC hardware block. + +config CLK_QCOM_NORD_TCSRCC + bool "Qualcomm Nord TCSRCC" + select CLK_QCOM + help + Say Y here to enable support for the TCSR Clock Controller on the + Snapdragon Nord SoC. This driver supports the CLKREF enable gates + exposed by the TCSRCC hardware block. + config CLK_QCOM_QCM2290 bool "Qualcomm QCM2290 GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 7e979863dfcc..4b4264aba9db 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -11,6 +11,11 @@ obj-$(CONFIG_CLK_QCOM_IPQ5210) += clock-ipq5210.o obj-$(CONFIG_CLK_QCOM_IPQ5424) += clock-ipq5424.o obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o obj-$(CONFIG_CLK_QCOM_MILOS) += clock-milos.o +obj-$(CONFIG_CLK_QCOM_NORD) += clock-nord-gcc.o +obj-$(CONFIG_CLK_QCOM_NORD_NEGCC) += clock-nord-negcc.o +obj-$(CONFIG_CLK_QCOM_NORD_SEGCC) += clock-nord-segcc.o +obj-$(CONFIG_CLK_QCOM_NORD_NWGCC) += clock-nord-nwgcc.o +obj-$(CONFIG_CLK_QCOM_NORD_TCSRCC) += clock-nord-tcsrcc.o obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o diff --git a/drivers/clk/qcom/clock-nord-gcc.c b/drivers/clk/qcom/clock-nord-gcc.c new file mode 100644 index 000000000000..f54906d0db27 --- /dev/null +++ b/drivers/clk/qcom/clock-nord-gcc.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "clock-qcom.h" + +static const struct gate_clk nord_gcc_clks[] = { + GATE_CLK_POLLED(GCC_MMU_0_TCU_VOTE_CLK, 0x7d094, BIT(0), 0x7d094), + GATE_CLK_POLLED(GCC_PCIE_A_AUX_CLK, 0x9d008, BIT(14), 0x49058), + GATE_CLK_POLLED(GCC_PCIE_A_CFG_AHB_CLK, 0x9d008, BIT(13), 0x49054), + GATE_CLK_POLLED(GCC_PCIE_A_PHY_AUX_CLK, 0x9d010, BIT(12), 0x4d01c), + GATE_CLK_POLLED(GCC_PCIE_A_PHY_RCHNG_CLK, 0x9d008, BIT(16), 0x49078), + GATE_CLK_POLLED(GCC_PCIE_A_SLV_AXI_CLK, 0x9d008, BIT(11), 0x4902c), + GATE_CLK_POLLED(GCC_PCIE_A_SLV_Q2A_AXI_CLK, 0x9d008, BIT(10), 0x49024), + GATE_CLK_POLLED(GCC_PCIE_B_AUX_CLK, 0x9d008, BIT(23), 0x4a058), + GATE_CLK_POLLED(GCC_PCIE_B_CFG_AHB_CLK, 0x9d008, BIT(22), 0x4a054), + GATE_CLK_POLLED(GCC_PCIE_B_PHY_AUX_CLK, 0x9d010, BIT(13), 0x4e01c), + GATE_CLK_POLLED(GCC_PCIE_B_PHY_RCHNG_CLK, 0x9d008, BIT(25), 0x4a078), + GATE_CLK_POLLED(GCC_PCIE_B_SLV_AXI_CLK, 0x9d008, BIT(20), 0x4a02c), + GATE_CLK_POLLED(GCC_PCIE_B_SLV_Q2A_AXI_CLK, 0x9d008, BIT(19), 0x4a024), + GATE_CLK_POLLED(GCC_PCIE_C_AUX_CLK, 0x9d010, BIT(0), 0x4b058), + GATE_CLK_POLLED(GCC_PCIE_C_CFG_AHB_CLK, 0x9d008, BIT(31), 0x4b054), + GATE_CLK_POLLED(GCC_PCIE_C_PHY_AUX_CLK, 0x9d010, BIT(14), 0x4f01c), + GATE_CLK_POLLED(GCC_PCIE_C_PHY_RCHNG_CLK, 0x9d010, BIT(2), 0x4b078), + GATE_CLK_POLLED(GCC_PCIE_C_SLV_AXI_CLK, 0x9d008, BIT(29), 0x4b02c), + GATE_CLK_POLLED(GCC_PCIE_C_SLV_Q2A_AXI_CLK, 0x9d008, BIT(28), 0x4b024), + GATE_CLK_POLLED(GCC_PCIE_D_AUX_CLK, 0x9d010, BIT(9), 0x4c058), + GATE_CLK_POLLED(GCC_PCIE_D_CFG_AHB_CLK, 0x9d010, BIT(8), 0x4c054), + GATE_CLK_POLLED(GCC_PCIE_D_PHY_AUX_CLK, 0x9d010, BIT(16), 0x5001c), + GATE_CLK_POLLED(GCC_PCIE_D_PHY_RCHNG_CLK, 0x9d010, BIT(11), 0x4c078), + GATE_CLK_POLLED(GCC_PCIE_D_SLV_AXI_CLK, 0x9d010, BIT(6), 0x4c02c), + GATE_CLK_POLLED(GCC_PCIE_D_SLV_Q2A_AXI_CLK, 0x9d010, BIT(5), 0x4c024), + GATE_CLK_POLLED(GCC_PCIE_NOC_CNOC_SF_QX_CLK, 0x9d010, BIT(24), 0x52040), + GATE_CLK_POLLED(GCC_PCIE_NOC_M_CFG_CLK, 0x9d018, BIT(4), 0x52060), + GATE_CLK_POLLED(GCC_PCIE_NOC_M_PDB_CLK, 0x9d018, BIT(8), 0x52084), + GATE_CLK_POLLED(GCC_PCIE_NOC_PWRCTL_CLK, 0x9d018, BIT(7), 0x52080), + GATE_CLK_POLLED(GCC_PCIE_NOC_QOSGEN_EXTREF_CLK, 0x9d010, BIT(19), 0x52074), + GATE_CLK_POLLED(GCC_PCIE_NOC_SLAVE_AXI_CLK, 0x9d010, BIT(26), 0x52058), + GATE_CLK_POLLED(GCC_PCIE_NOC_S_CFG_CLK, 0x9d018, BIT(5), 0x52064), + GATE_CLK_POLLED(GCC_PCIE_NOC_S_PDB_CLK, 0x9d018, BIT(9), 0x5208c), + GATE_CLK_POLLED(GCC_PCIE_NOC_TSCTR_CLK, 0x9d010, BIT(18), 0x52070), + GATE_CLK_POLLED(GCC_PCIE_NOC_XO_CLK, 0x9d018, BIT(6), 0x52068), + GATE_CLK_POLLED(GCC_PDM_AHB_CLK, 0x1a004, BIT(0), 0x1a004), + GATE_CLK_POLLED(GCC_QUPV3_WRAP3_CORE_2X_CLK, 0x9d000, BIT(24), 0x23020), + GATE_CLK_POLLED(GCC_QUPV3_WRAP3_CORE_CLK, 0x9d000, BIT(23), 0x2300c), + GATE_CLK_POLLED(GCC_QUPV3_WRAP3_M_CLK, 0x9d000, BIT(22), 0x23004), + GATE_CLK_POLLED(GCC_QUPV3_WRAP3_QSPI_REF_CLK, 0x9d000, BIT(26), 0x23170), + GATE_CLK_POLLED(GCC_QUPV3_WRAP3_S0_CLK, 0x9d000, BIT(25), 0x2315c), + GATE_CLK_POLLED(GCC_QUPV3_WRAP3_S_AHB_CLK, 0x9d010, BIT(15), 0x23008), + GATE_CLK_POLLED(GCC_SMMU_PCIE_QTC_VOTE_CLK, 0x7d0b8, BIT(0), 0x7d0b8), + + GATE_CLK(GCC_BOOT_ROM_AHB_CLK, 0x1f004, BIT(0)), + GATE_CLK(GCC_GP1_CLK, 0x30000, BIT(0)), + GATE_CLK(GCC_GP2_CLK, 0x31000, BIT(0)), + GATE_CLK(GCC_PCIE_A_DTI_QTC_CLK, 0x9d008, BIT(8)), + GATE_CLK(GCC_PCIE_A_MSTR_AXI_CLK, 0x9d008, BIT(12)), + GATE_CLK(GCC_PCIE_A_PIPE_CLK, 0x9d008, BIT(15)), + GATE_CLK(GCC_PCIE_B_DTI_QTC_CLK, 0x9d008, BIT(17)), + GATE_CLK(GCC_PCIE_B_MSTR_AXI_CLK, 0x9d008, BIT(21)), + GATE_CLK(GCC_PCIE_B_PIPE_CLK, 0x9d008, BIT(24)), + GATE_CLK(GCC_PCIE_C_DTI_QTC_CLK, 0x9d008, BIT(26)), + GATE_CLK(GCC_PCIE_C_MSTR_AXI_CLK, 0x9d008, BIT(30)), + GATE_CLK(GCC_PCIE_C_PIPE_CLK, 0x9d010, BIT(1)), + GATE_CLK(GCC_PCIE_D_DTI_QTC_CLK, 0x9d010, BIT(3)), + GATE_CLK(GCC_PCIE_D_MSTR_AXI_CLK, 0x9d010, BIT(7)), + GATE_CLK(GCC_PCIE_D_PIPE_CLK, 0x9d010, BIT(10)), + GATE_CLK(GCC_PCIE_NOC_ASYNC_BRIDGE_CLK, 0x9d018, BIT(18)), + GATE_CLK(GCC_PCIE_NOC_MSTR_AXI_CLK, 0x9d010, BIT(25)), + GATE_CLK(GCC_PCIE_NOC_REFGEN_CLK, 0x52078, BIT(0)), + GATE_CLK(GCC_PCIE_NOC_SAFETY_CLK, 0x5207c, BIT(0)), + GATE_CLK(GCC_PDM2_CLK, 0x1a00c, BIT(0)), + GATE_CLK(GCC_PDM_XO4_CLK, 0x1a008, BIT(0)), +}; + +static int nord_gcc_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %ld: %s\n", __func__, clk->id, nord_gcc_clks[clk->id].name); + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map nord_gcc_resets[] = { + [GCC_PCIE_A_BCR] = { 0x49000 }, + [GCC_PCIE_A_LINK_DOWN_BCR] = { 0xb9000 }, + [GCC_PCIE_A_NOCSR_COM_PHY_BCR] = { 0xb900c }, + [GCC_PCIE_A_PHY_BCR] = { 0x4d000 }, + [GCC_PCIE_A_PHY_CFG_AHB_BCR] = { 0xb9014 }, + [GCC_PCIE_A_PHY_COM_BCR] = { 0xb9018 }, + [GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR] = { 0xb9010 }, + [GCC_PCIE_B_BCR] = { 0x4a000 }, + [GCC_PCIE_B_LINK_DOWN_BCR] = { 0xba000 }, + [GCC_PCIE_B_NOCSR_COM_PHY_BCR] = { 0xba008 }, + [GCC_PCIE_B_PHY_BCR] = { 0x4e000 }, + [GCC_PCIE_B_PHY_CFG_AHB_BCR] = { 0xba010 }, + [GCC_PCIE_B_PHY_COM_BCR] = { 0xba014 }, + [GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR] = { 0xba00c }, + [GCC_PCIE_C_BCR] = { 0x4b000 }, + [GCC_PCIE_C_LINK_DOWN_BCR] = { 0xbb07c }, + [GCC_PCIE_C_NOCSR_COM_PHY_BCR] = { 0xbb084 }, + [GCC_PCIE_C_PHY_BCR] = { 0x4f000 }, + [GCC_PCIE_C_PHY_CFG_AHB_BCR] = { 0xbb08c }, + [GCC_PCIE_C_PHY_COM_BCR] = { 0xbb090 }, + [GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR] = { 0xbb088 }, + [GCC_PCIE_D_BCR] = { 0x4c000 }, + [GCC_PCIE_D_LINK_DOWN_BCR] = { 0xbc000 }, + [GCC_PCIE_D_NOCSR_COM_PHY_BCR] = { 0xbc008 }, + [GCC_PCIE_D_PHY_BCR] = { 0x50000 }, + [GCC_PCIE_D_PHY_CFG_AHB_BCR] = { 0xbc010 }, + [GCC_PCIE_D_PHY_COM_BCR] = { 0xbc014 }, + [GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR] = { 0xbc00c }, + [GCC_PCIE_NOC_BCR] = { 0x52000 }, + [GCC_PDM_BCR] = { 0x1a000 }, + [GCC_QUPV3_WRAPPER_3_BCR] = { 0x23000 }, + [GCC_TCSR_PCIE_BCR] = { 0xb901c }, +}; + +static const struct qcom_power_map nord_gcc_gdscs[] = { + [GCC_PCIE_A_GDSC] = { 0x49004 }, + [GCC_PCIE_A_PHY_GDSC] = { 0x4d004 }, + [GCC_PCIE_B_GDSC] = { 0x4a004 }, + [GCC_PCIE_B_PHY_GDSC] = { 0x4e004 }, + [GCC_PCIE_C_GDSC] = { 0x4b004 }, + [GCC_PCIE_C_PHY_GDSC] = { 0x4f004 }, + [GCC_PCIE_D_GDSC] = { 0x4c004 }, + [GCC_PCIE_D_PHY_GDSC] = { 0x50004 }, + [GCC_PCIE_NOC_GDSC] = { 0x52004 }, +}; + +static struct msm_clk_data nord_gcc_data = { + .resets = nord_gcc_resets, + .num_resets = ARRAY_SIZE(nord_gcc_resets), + .clks = nord_gcc_clks, + .num_clks = ARRAY_SIZE(nord_gcc_clks), + + .power_domains = nord_gcc_gdscs, + .num_power_domains = ARRAY_SIZE(nord_gcc_gdscs), + + .enable = nord_gcc_enable, +}; + +static const struct udevice_id gcc_nord_of_match[] = { + { + .compatible = "qcom,nord-gcc", + .data = (ulong)&nord_gcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_nord) = { + .name = "gcc_nord", + .id = UCLASS_NOP, + .of_match = gcc_nord_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/qcom/clock-nord-negcc.c b/drivers/clk/qcom/clock-nord-negcc.c new file mode 100644 index 000000000000..ce50a76bcfb6 --- /dev/null +++ b/drivers/clk/qcom/clock-nord-negcc.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "clock-qcom.h" + +#define NE_GCC_QUPV3_WRAP2_S1_CLK_CMD_RCGR 0x382a8 + +/* + * negcc-nord.c calls qcom_branch_set_force_mem_core() on + * NE_GCC_UFS_PHY_ICE_CORE_CLK and NE_GCC_UFS_PHY_AXI_CLK. This U-Boot clock + * framework has no FORCE_MEM_CORE_ON primitive (confirmed absent from + * clock-qcom.h/.c) — flagged as a YELLOW residual risk, not worked around. + */ + +static ulong nord_negcc_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id < priv->data->num_clks) + debug("%s: %s, requested rate=%ld\n", __func__, + priv->data->clks[clk->id].name, rate); + + switch (clk->id) { + case NE_GCC_QUPV3_WRAP2_S1_CLK: + WARN(rate != 14745600, + "Unexpected rate for NE_GCC_QUPV3_WRAP2_S1_CLK: %lu\n", rate); + clk_rcg_set_rate_mnd(priv->base, NE_GCC_QUPV3_WRAP2_S1_CLK_CMD_RCGR, + 1, 384, 15625, CFG_CLK_SRC_GPLL0, 16); + return rate; + default: + return 0; + } +} + +static const struct gate_clk nord_negcc_clks[] = { + GATE_CLK_POLLED(NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK, 0x330f4, BIT(0), 0x330f4), + GATE_CLK_POLLED(NE_GCC_AGGRE_NOC_USB2_AXI_CLK, 0x31068, BIT(0), 0x31068), + GATE_CLK_POLLED(NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK,0x2a098, BIT(0), 0x2a098), + GATE_CLK_POLLED(NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK, 0x2c098, BIT(0), 0x2c098), + GATE_CLK_POLLED(NE_GCC_AHB2PHY_CLK, 0x30004, BIT(0), 0x30004), + GATE_CLK_POLLED(NE_GCC_CNOC_USB2_AXI_CLK, 0x31064, BIT(0), 0x31064), + GATE_CLK_POLLED(NE_GCC_CNOC_USB3_PRIM_AXI_CLK, 0x2a094, BIT(0), 0x2a094), + GATE_CLK_POLLED(NE_GCC_CNOC_USB3_SEC_AXI_CLK, 0x2c094, BIT(0), 0x2c094), + GATE_CLK_POLLED(NE_GCC_GPU_2_HSCNOC_GFX_CLK, 0x34014, BIT(0), 0x34014), + GATE_CLK_POLLED(NE_GCC_GPU_2_SMMU_VOTE_CLK, 0x57028, BIT(0), 0x57028), + GATE_CLK_POLLED(NE_GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x57008, BIT(1), 0x38020), + GATE_CLK_POLLED(NE_GCC_QUPV3_WRAP2_CORE_CLK, 0x57008, BIT(0), 0x3800c), + GATE_CLK_POLLED(NE_GCC_QUPV3_WRAP2_M_AHB_CLK, 0x57000, BIT(30), 0x38004), + GATE_CLK_POLLED(NE_GCC_QUPV3_WRAP2_S0_CLK, 0x57008, BIT(2), 0x3815c), + GATE_CLK_POLLED(NE_GCC_QUPV3_WRAP2_S1_CLK, 0x57008, BIT(3), 0x38298), + GATE_CLK_POLLED(NE_GCC_QUPV3_WRAP2_S2_CLK, 0x57008, BIT(4), 0x383d4), + GATE_CLK_POLLED(NE_GCC_QUPV3_WRAP2_S3_CLK, 0x57008, BIT(5), 0x38510), + GATE_CLK_POLLED(NE_GCC_QUPV3_WRAP2_S4_CLK, 0x57008, BIT(6), 0x3864c), + GATE_CLK_POLLED(NE_GCC_QUPV3_WRAP2_S5_CLK, 0x57008, BIT(7), 0x38788), + GATE_CLK_POLLED(NE_GCC_QUPV3_WRAP2_S6_CLK, 0x57008, BIT(8), 0x388c4), + GATE_CLK_POLLED(NE_GCC_QUPV3_WRAP2_S_AHB_CLK, 0x57000, BIT(31), 0x38008), + GATE_CLK_POLLED(NE_GCC_UFS_PHY_AHB_CLK, 0x33028, BIT(0), 0x33028), + GATE_CLK_POLLED(NE_GCC_UFS_PHY_AXI_CLK, 0x33018, BIT(0), 0x33018), + GATE_CLK_POLLED(NE_GCC_UFS_PHY_ICE_CORE_CLK, 0x3307c, BIT(0), 0x3307c), + GATE_CLK_POLLED(NE_GCC_UFS_PHY_PHY_AUX_CLK, 0x330bc, BIT(0), 0x330bc), + GATE_CLK_POLLED(NE_GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x3306c, BIT(0), 0x3306c), + GATE_CLK_POLLED(NE_GCC_USB31_PRIM_ATB_CLK, 0x2a018, BIT(0), 0x2a018), + GATE_CLK_POLLED(NE_GCC_USB31_PRIM_EUD_AHB_CLK, 0x2a02c, BIT(0), 0x2a02c), + GATE_CLK_POLLED(NE_GCC_USB31_SEC_ATB_CLK, 0x2c018, BIT(0), 0x2c018), + GATE_CLK_POLLED(NE_GCC_USB31_SEC_EUD_AHB_CLK, 0x2c02c, BIT(0), 0x2c02c), + + GATE_CLK(NE_GCC_FRQ_MEASURE_REF_CLK, 0x20008, BIT(0)), + GATE_CLK(NE_GCC_GP1_CLK, 0x21000, BIT(0)), + GATE_CLK(NE_GCC_GP2_CLK, 0x22000, BIT(0)), + GATE_CLK(NE_GCC_GPU_2_GPLL0_CLK_SRC, 0x57000, BIT(19)), + GATE_CLK(NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC, 0x57000, BIT(20)), + GATE_CLK(NE_GCC_SDCC4_APPS_CLK, 0x18004, BIT(0)), + GATE_CLK(NE_GCC_SDCC4_AXI_CLK, 0x18014, BIT(0)), + GATE_CLK(NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x33030, BIT(0)), + GATE_CLK(NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x330d8, BIT(0)), + GATE_CLK(NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x3302c, BIT(0)), + GATE_CLK(NE_GCC_USB20_MASTER_CLK, 0x31018, BIT(0)), + GATE_CLK(NE_GCC_USB20_MOCK_UTMI_CLK, 0x3102c, BIT(0)), + GATE_CLK(NE_GCC_USB20_SLEEP_CLK, 0x31028, BIT(0)), + GATE_CLK(NE_GCC_USB31_PRIM_MASTER_CLK, 0x2a01c, BIT(0)), + GATE_CLK(NE_GCC_USB31_PRIM_MOCK_UTMI_CLK, 0x2a034, BIT(0)), + GATE_CLK(NE_GCC_USB31_PRIM_SLEEP_CLK, 0x2a030, BIT(0)), + GATE_CLK(NE_GCC_USB31_SEC_MASTER_CLK, 0x2c01c, BIT(0)), + GATE_CLK(NE_GCC_USB31_SEC_MOCK_UTMI_CLK, 0x2c034, BIT(0)), + GATE_CLK(NE_GCC_USB31_SEC_SLEEP_CLK, 0x2c030, BIT(0)), + GATE_CLK(NE_GCC_USB3_PRIM_PHY_AUX_CLK, 0x2a06c, BIT(0)), + GATE_CLK(NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK,0x2a070, BIT(0)), + GATE_CLK(NE_GCC_USB3_PRIM_PHY_PIPE_CLK, 0x2a074, BIT(0)), + GATE_CLK(NE_GCC_USB3_SEC_PHY_AUX_CLK, 0x2c06c, BIT(0)), + GATE_CLK(NE_GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x2c070, BIT(0)), + GATE_CLK(NE_GCC_USB3_SEC_PHY_PIPE_CLK, 0x2c074, BIT(0)), +}; + +static int nord_negcc_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %ld: %s\n", __func__, clk->id, nord_negcc_clks[clk->id].name); + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map nord_negcc_resets[] = { + [NE_GCC_GPU_2_BCR] = { 0x34000 }, + [NE_GCC_QUPV3_WRAPPER_2_BCR] = { 0x38000 }, + [NE_GCC_SDCC4_BCR] = { 0x18000 }, + [NE_GCC_UFS_PHY_BCR] = { 0x33000 }, + [NE_GCC_USB20_PRIM_BCR] = { 0x31000 }, + [NE_GCC_USB31_PRIM_BCR] = { 0x2a000 }, + [NE_GCC_USB31_SEC_BCR] = { 0x2c000 }, + [NE_GCC_USB3_DP_PHY_PRIM_BCR] = { 0x2b008 }, + [NE_GCC_USB3_DP_PHY_SEC_BCR] = { 0x2d008 }, + [NE_GCC_USB3_PHY_PRIM_BCR] = { 0x2b000 }, + [NE_GCC_USB3_PHY_SEC_BCR] = { 0x2d000 }, + [NE_GCC_USB3PHY_PHY_PRIM_BCR] = { 0x2b004 }, + [NE_GCC_USB3PHY_PHY_SEC_BCR] = { 0x2d004 }, + [NE_GCC_QUSB2PHY_PRIM_BCR] = { 0x2e000 }, +}; + +static const struct qcom_power_map nord_negcc_gdscs[] = { + [NE_GCC_UFS_MEM_PHY_GDSC] = { 0x32000 }, + [NE_GCC_UFS_PHY_GDSC] = { 0x33004 }, + [NE_GCC_USB20_PRIM_GDSC] = { 0x31004 }, + [NE_GCC_USB31_PRIM_GDSC] = { 0x2a004 }, + [NE_GCC_USB31_SEC_GDSC] = { 0x2c004 }, + [NE_GCC_USB3_PHY_GDSC] = { 0x2b00c }, + [NE_GCC_USB3_SEC_PHY_GDSC] = { 0x2d00c }, +}; + +static struct msm_clk_data nord_negcc_data = { + .resets = nord_negcc_resets, + .num_resets = ARRAY_SIZE(nord_negcc_resets), + .clks = nord_negcc_clks, + .num_clks = ARRAY_SIZE(nord_negcc_clks), + + .power_domains = nord_negcc_gdscs, + .num_power_domains = ARRAY_SIZE(nord_negcc_gdscs), + + .enable = nord_negcc_enable, + .set_rate = nord_negcc_set_rate, +}; + +static const struct udevice_id gcc_nord_negcc_of_match[] = { + { + .compatible = "qcom,nord-negcc", + .data = (ulong)&nord_negcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_nord_negcc) = { + .name = "gcc_nord_negcc", + .id = UCLASS_NOP, + .of_match = gcc_nord_negcc_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/qcom/clock-nord-nwgcc.c b/drivers/clk/qcom/clock-nord-nwgcc.c new file mode 100644 index 000000000000..e7d189d07e6d --- /dev/null +++ b/drivers/clk/qcom/clock-nord-nwgcc.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "clock-qcom.h" + +static const struct gate_clk nord_nwgcc_clks[] = { + GATE_CLK_POLLED(NW_GCC_CAMERA_TRIG_CLK, 0x16034, BIT(0), 0x16034), + GATE_CLK_POLLED(NW_GCC_DISP_0_TRIG_CLK, 0x1801c, BIT(0), 0x1801c), + GATE_CLK_POLLED(NW_GCC_DISP_1_TRIG_CLK, 0x1901c, BIT(0), 0x1901c), + GATE_CLK_POLLED(NW_GCC_EVA_TRIG_CLK, 0x1b028, BIT(0), 0x1b028), + GATE_CLK_POLLED(NW_GCC_GPU_2_GPLL0_CLK_SRC, 0x76000, BIT(6), 0x24150), + GATE_CLK_POLLED(NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC,0x76000, BIT(7), 0x24158), + GATE_CLK_POLLED(NW_GCC_GPU_2_HSCNOC_GFX_CLK, 0x2400c, BIT(0), 0x2400c), + GATE_CLK_POLLED(NW_GCC_GPU_GPLL0_CLK_SRC, 0x76000, BIT(4), 0x23150), + GATE_CLK_POLLED(NW_GCC_GPU_GPLL0_DIV_CLK_SRC, 0x76000, BIT(5), 0x23158), + GATE_CLK_POLLED(NW_GCC_GPU_SMMU_VOTE_CLK, 0x86038, BIT(0), 0x86038), + GATE_CLK_POLLED(NW_GCC_MMU_1_TCU_VOTE_CLK, 0x86040, BIT(0), 0x86040), + + GATE_CLK(NW_GCC_ACMU_MUX_CLK, 0x1f01c, BIT(0)), + GATE_CLK(NW_GCC_CAMERA_HF_AXI_CLK, 0x16008, BIT(0)), + GATE_CLK(NW_GCC_CAMERA_SF_AXI_CLK, 0x1601c, BIT(0)), + GATE_CLK(NW_GCC_DISP_0_HF_AXI_CLK, 0x18008, BIT(0)), + GATE_CLK(NW_GCC_DISP_1_HF_AXI_CLK, 0x19008, BIT(0)), + GATE_CLK(NW_GCC_DPRX0_AXI_HF_CLK, 0x29004, BIT(0)), + GATE_CLK(NW_GCC_DPRX1_AXI_HF_CLK, 0x2a004, BIT(0)), + GATE_CLK(NW_GCC_EVA_AXI0C_CLK, 0x1b01c, BIT(0)), + GATE_CLK(NW_GCC_EVA_AXI0_CLK, 0x1b008, BIT(0)), + GATE_CLK(NW_GCC_FRQ_MEASURE_REF_CLK, 0x1f008, BIT(0)), + GATE_CLK(NW_GCC_GP1_CLK, 0x20000, BIT(0)), + GATE_CLK(NW_GCC_GP2_CLK, 0x21000, BIT(0)), + GATE_CLK(NW_GCC_GPU_HSCNOC_GFX_CLK, 0x2300c, BIT(0)), + GATE_CLK(NW_GCC_HSCNOC_GPU_2_AXI_CLK, 0x24160, BIT(0)), + GATE_CLK(NW_GCC_HSCNOC_GPU_AXI_CLK, 0x23160, BIT(0)), + GATE_CLK(NW_GCC_VIDEO_AXI0C_CLK, 0x1a01c, BIT(0)), + GATE_CLK(NW_GCC_VIDEO_AXI0_CLK, 0x1a008, BIT(0)), + GATE_CLK(NW_GCC_VIDEO_AXI1_CLK, 0x1a030, BIT(0)), +}; + +static int nord_nwgcc_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %ld: %s\n", __func__, clk->id, nord_nwgcc_clks[clk->id].name); + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map nord_nwgcc_resets[] = { + [NW_GCC_CAMERA_BCR] = { 0x16000 }, + [NW_GCC_DISPLAY_0_BCR] = { 0x18000 }, + [NW_GCC_DISPLAY_1_BCR] = { 0x19000 }, + [NW_GCC_DPRX0_BCR] = { 0x29000 }, + [NW_GCC_DPRX1_BCR] = { 0x2a000 }, + [NW_GCC_EVA_BCR] = { 0x1b000 }, + [NW_GCC_GPU_2_BCR] = { 0x24000 }, + [NW_GCC_GPU_BCR] = { 0x23000 }, + [NW_GCC_VIDEO_BCR] = { 0x1a000 }, +}; + +static struct msm_clk_data nord_nwgcc_data = { + .resets = nord_nwgcc_resets, + .num_resets = ARRAY_SIZE(nord_nwgcc_resets), + .clks = nord_nwgcc_clks, + .num_clks = ARRAY_SIZE(nord_nwgcc_clks), + + .enable = nord_nwgcc_enable, +}; + +static const struct udevice_id gcc_nord_nwgcc_of_match[] = { + { + .compatible = "qcom,nord-nwgcc", + .data = (ulong)&nord_nwgcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_nord_nwgcc) = { + .name = "gcc_nord_nwgcc", + .id = UCLASS_NOP, + .of_match = gcc_nord_nwgcc_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/qcom/clock-nord-segcc.c b/drivers/clk/qcom/clock-nord-segcc.c new file mode 100644 index 000000000000..79fdfa148f99 --- /dev/null +++ b/drivers/clk/qcom/clock-nord-segcc.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "clock-qcom.h" + +#define SE_GCC_QUPV3_WRAP0_S4_CLK_CMD_RCGR 0x2665c + +static ulong nord_segcc_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id < priv->data->num_clks) + debug("%s: %s, requested rate=%ld\n", __func__, + priv->data->clks[clk->id].name, rate); + + switch (clk->id) { + case SE_GCC_QUPV3_WRAP0_S4_CLK: + WARN(rate != 14745600, + "Unexpected rate for SE_GCC_QUPV3_WRAP0_S4_CLK: %lu\n", rate); + clk_rcg_set_rate_mnd(priv->base, SE_GCC_QUPV3_WRAP0_S4_CLK_CMD_RCGR, + 1, 384, 15625, CFG_CLK_SRC_GPLL0, 16); + return rate; + default: + return 0; + } +} + +static const struct gate_clk nord_segcc_clks[] = { + GATE_CLK_POLLED(SE_GCC_EMAC0_AXI_CLK, 0x2401c, BIT(0), 0x2401c), + GATE_CLK_POLLED(SE_GCC_EMAC1_AXI_CLK, 0x2501c, BIT(0), 0x2501c), + GATE_CLK_POLLED(SE_GCC_MMU_2_TCU_VOTE_CLK, 0x57040, BIT(0), 0x57040), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x57000, BIT(15), 0x26020), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP0_CORE_CLK, 0x57000, BIT(14), 0x2600c), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP0_M_AHB_CLK, 0x57000, BIT(12), 0x26004), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP0_S0_CLK, 0x57000, BIT(16), 0x2615c), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP0_S1_CLK, 0x57000, BIT(17), 0x26298), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP0_S2_CLK, 0x57000, BIT(18), 0x263d4), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP0_S3_CLK, 0x57000, BIT(19), 0x26510), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP0_S4_CLK, 0x57000, BIT(20), 0x2664c), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP0_S5_CLK, 0x57000, BIT(21), 0x26788), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP0_S6_CLK, 0x57000, BIT(22), 0x268c4), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP0_S_AHB_CLK, 0x57000, BIT(13), 0x26008), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP1_CORE_2X_CLK, 0x57000, BIT(26), 0x27020), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP1_CORE_CLK, 0x57000, BIT(25), 0x2700c), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP1_M_AHB_CLK, 0x57000, BIT(23), 0x27004), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP1_S0_CLK, 0x57000, BIT(27), 0x2715c), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP1_S1_CLK, 0x57000, BIT(28), 0x27298), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP1_S2_CLK, 0x57000, BIT(29), 0x273d4), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP1_S3_CLK, 0x57000, BIT(30), 0x27510), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP1_S4_CLK, 0x57000, BIT(31), 0x2764c), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP1_S5_CLK, 0x57008, BIT(0), 0x27788), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP1_S6_CLK, 0x57008, BIT(1), 0x278c4), + GATE_CLK_POLLED(SE_GCC_QUPV3_WRAP1_S_AHB_CLK, 0x57000, BIT(24), 0x27008), + + GATE_CLK(SE_GCC_EEE_EMAC0_CLK, 0x240b4, BIT(0)), + GATE_CLK(SE_GCC_EEE_EMAC1_CLK, 0x250b4, BIT(0)), + GATE_CLK(SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK, 0x24064, BIT(0)), + GATE_CLK(SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK, 0x2405c, BIT(0)), + GATE_CLK(SE_GCC_EMAC0_PHY_AUX_CLK, 0x2402c, BIT(0)), + GATE_CLK(SE_GCC_EMAC0_PTP_CLK, 0x24048, BIT(0)), + GATE_CLK(SE_GCC_EMAC0_RGMII_CLK, 0x24058, BIT(0)), + GATE_CLK(SE_GCC_EMAC0_RPCS_RX_CLK, 0x240a8, BIT(0)), + GATE_CLK(SE_GCC_EMAC0_RPCS_TX_CLK, 0x240a4, BIT(0)), + GATE_CLK(SE_GCC_EMAC0_XGXS_RX_CLK, 0x240b0, BIT(0)), + GATE_CLK(SE_GCC_EMAC0_XGXS_TX_CLK, 0x240ac, BIT(0)), + GATE_CLK(SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK, 0x25064, BIT(0)), + GATE_CLK(SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK, 0x2505c, BIT(0)), + GATE_CLK(SE_GCC_EMAC1_PHY_AUX_CLK, 0x2502c, BIT(0)), + GATE_CLK(SE_GCC_EMAC1_PTP_CLK, 0x25048, BIT(0)), + GATE_CLK(SE_GCC_EMAC1_RGMII_CLK, 0x25058, BIT(0)), + GATE_CLK(SE_GCC_EMAC1_RPCS_RX_CLK, 0x250a8, BIT(0)), + GATE_CLK(SE_GCC_EMAC1_RPCS_TX_CLK, 0x250a4, BIT(0)), + GATE_CLK(SE_GCC_EMAC1_XGXS_RX_CLK, 0x250b0, BIT(0)), + GATE_CLK(SE_GCC_EMAC1_XGXS_TX_CLK, 0x250ac, BIT(0)), + GATE_CLK(SE_GCC_FRQ_MEASURE_REF_CLK, 0x18008, BIT(0)), + GATE_CLK(SE_GCC_GP1_CLK, 0x19000, BIT(0)), + GATE_CLK(SE_GCC_GP2_CLK, 0x1a000, BIT(0)), +}; + +static int nord_segcc_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %ld: %s\n", __func__, clk->id, nord_segcc_clks[clk->id].name); + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static const struct qcom_reset_map nord_segcc_resets[] = { + [SE_GCC_EMAC0_BCR] = { 0x24000 }, + [SE_GCC_EMAC1_BCR] = { 0x25000 }, + [SE_GCC_QUPV3_WRAPPER_0_BCR] = { 0x26000 }, + [SE_GCC_QUPV3_WRAPPER_1_BCR] = { 0x27000 }, +}; + +static const struct qcom_power_map nord_segcc_gdscs[] = { + [SE_GCC_EMAC0_GDSC] = { 0x24004 }, + [SE_GCC_EMAC1_GDSC] = { 0x25004 }, +}; + +static struct msm_clk_data nord_segcc_data = { + .resets = nord_segcc_resets, + .num_resets = ARRAY_SIZE(nord_segcc_resets), + .clks = nord_segcc_clks, + .num_clks = ARRAY_SIZE(nord_segcc_clks), + + .power_domains = nord_segcc_gdscs, + .num_power_domains = ARRAY_SIZE(nord_segcc_gdscs), + + .enable = nord_segcc_enable, + .set_rate = nord_segcc_set_rate, +}; + +static const struct udevice_id gcc_nord_segcc_of_match[] = { + { + .compatible = "qcom,nord-segcc", + .data = (ulong)&nord_segcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_nord_segcc) = { + .name = "gcc_nord_segcc", + .id = UCLASS_NOP, + .of_match = gcc_nord_segcc_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/qcom/clock-nord-tcsrcc.c b/drivers/clk/qcom/clock-nord-tcsrcc.c new file mode 100644 index 000000000000..e02285979ad0 --- /dev/null +++ b/drivers/clk/qcom/clock-nord-tcsrcc.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "clock-qcom.h" + +static const struct gate_clk nord_tcsrcc_clks[] = { + GATE_CLK(TCSR_DP_RX_0_CLKREF_EN, 0xa008, BIT(0)), + GATE_CLK(TCSR_DP_RX_1_CLKREF_EN, 0xb008, BIT(0)), + GATE_CLK(TCSR_DP_TX_0_CLKREF_EN, 0xc008, BIT(0)), + GATE_CLK(TCSR_DP_TX_1_CLKREF_EN, 0xd008, BIT(0)), + GATE_CLK(TCSR_DP_TX_2_CLKREF_EN, 0xe008, BIT(0)), + GATE_CLK(TCSR_DP_TX_3_CLKREF_EN, 0xf008, BIT(0)), + GATE_CLK(TCSR_PCIE_CLKREF_EN, 0x8, BIT(0)), + GATE_CLK(TCSR_UFS_CLKREF_EN, 0x3008, BIT(0)), + GATE_CLK(TCSR_USB2_0_CLKREF_EN, 0x4008, BIT(0)), + GATE_CLK(TCSR_USB2_1_CLKREF_EN, 0x5008, BIT(0)), + GATE_CLK(TCSR_USB2_2_CLKREF_EN, 0x6008, BIT(0)), + GATE_CLK(TCSR_USB3_0_CLKREF_EN, 0x8008, BIT(0)), + GATE_CLK(TCSR_USB3_1_CLKREF_EN, 0x7008, BIT(0)), + GATE_CLK(TCSR_UX_SGMII_0_CLKREF_EN, 0x1008, BIT(0)), + GATE_CLK(TCSR_UX_SGMII_1_CLKREF_EN, 0x2008, BIT(0)), +}; + +static int nord_tcsrcc_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %ld: %s\n", __func__, clk->id, nord_tcsrcc_clks[clk->id].name); + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static struct msm_clk_data nord_tcsrcc_data = { + .clks = nord_tcsrcc_clks, + .num_clks = ARRAY_SIZE(nord_tcsrcc_clks), + + .enable = nord_tcsrcc_enable, +}; + +static const struct udevice_id gcc_nord_tcsrcc_of_match[] = { + { + .compatible = "qcom,nord-tcsrcc", + .data = (ulong)&nord_tcsrcc_data, + }, + { } +}; + +U_BOOT_DRIVER(gcc_nord_tcsrcc) = { + .name = "gcc_nord_tcsrcc", + .id = UCLASS_NOP, + .of_match = gcc_nord_tcsrcc_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 09ec40f25b0f..a435cb48806d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -126,6 +126,15 @@ config QCOM_GENI_MINICORE help Enable support for minicores in Qualcomm GENI and its peripherals. +config QCOM_GENI_FW_LOAD + bool "Load Qualcomm GENI peripheral firmware at late init" + depends on QCOM_GENI + default y + help + Load firmware for GENI peripherals from the firmware partition + at late init. Disable if no GENI peripheral needs firmware + loading. + config ROCKCHIP_EFUSE bool "Rockchip e-fuse support" depends on MISC diff --git a/drivers/misc/qcom_geni.c b/drivers/misc/qcom_geni.c index 40044e5d48a6..3aa36455a9a2 100644 --- a/drivers/misc/qcom_geni.c +++ b/drivers/misc/qcom_geni.c @@ -634,7 +634,7 @@ int qcom_geni_fw_probe(struct udevice *dev) { return qcom_geni_fw_initialise(); } -#else +#elif IS_ENABLED(CONFIG_QCOM_GENI_FW_LOAD) EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, qcom_geni_fw_initialise); #endif diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index ba866b5b6b2e..ce69a1e73289 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -132,6 +132,14 @@ config SPL_PINCTRL_QCOM_MILOS SPL variant of PINCTRL_QCOM_MILOS. See the help of PINCTRL_QCOM_MILOS for details. +config PINCTRL_QCOM_NORD + bool "Qualcomm Nord Pinctrl" + default y if PINCTRL_QCOM_GENERIC + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon Nord SoC, + as well as the associated GPIO driver. + config PINCTRL_QCOM_QCM2290 bool "Qualcomm QCM2290 Pinctrl" default y if PINCTRL_QCOM_GENERIC diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 8145ae37cb46..a0781ab85290 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_$(PHASE_)PINCTRL_QCOM_IPQ5424) += pinctrl-ipq5424.o obj-$(CONFIG_$(PHASE_)PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o obj-$(CONFIG_$(PHASE_)PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o obj-$(CONFIG_$(PHASE_)PINCTRL_QCOM_MILOS) += pinctrl-milos.o +obj-$(CONFIG_$(PHASE_)PINCTRL_QCOM_NORD) += pinctrl-nord.o obj-$(CONFIG_$(PHASE_)PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o obj-$(CONFIG_$(PHASE_)PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o obj-$(CONFIG_$(PHASE_)PINCTRL_QCOM_QCS615) += pinctrl-qcs615.o diff --git a/drivers/pinctrl/qcom/pinctrl-nord.c b/drivers/pinctrl/qcom/pinctrl-nord.c new file mode 100644 index 000000000000..1457052dee64 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-nord.c @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Qualcomm Nord pinctrl + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include + +#include "pinctrl-qcom.h" + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +typedef unsigned int msm_pin_function[10]; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\ + { \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .name = #pg_name, \ + .ctl_reg = ctl, \ + .io_reg = io, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + } + +enum nord_functions { + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_aud_intfc0_clk, + msm_mux_aud_intfc0_data, + msm_mux_aud_intfc0_ws, + msm_mux_aud_intfc10_clk, + msm_mux_aud_intfc10_data, + msm_mux_aud_intfc10_ws, + msm_mux_aud_intfc1_clk, + msm_mux_aud_intfc1_data, + msm_mux_aud_intfc1_ws, + msm_mux_aud_intfc2_clk, + msm_mux_aud_intfc2_data, + msm_mux_aud_intfc2_ws, + msm_mux_aud_intfc3_clk, + msm_mux_aud_intfc3_data, + msm_mux_aud_intfc3_ws, + msm_mux_aud_intfc4_clk, + msm_mux_aud_intfc4_data, + msm_mux_aud_intfc4_ws, + msm_mux_aud_intfc5_clk, + msm_mux_aud_intfc5_data, + msm_mux_aud_intfc5_ws, + msm_mux_aud_intfc6_clk, + msm_mux_aud_intfc6_data, + msm_mux_aud_intfc6_ws, + msm_mux_aud_intfc7_clk, + msm_mux_aud_intfc7_data, + msm_mux_aud_intfc7_ws, + msm_mux_aud_intfc8_clk, + msm_mux_aud_intfc8_data, + msm_mux_aud_intfc8_ws, + msm_mux_aud_intfc9_clk, + msm_mux_aud_intfc9_data, + msm_mux_aud_intfc9_ws, + msm_mux_aud_mclk0_mira, + msm_mux_aud_mclk0_mirb, + msm_mux_aud_mclk1_mira, + msm_mux_aud_mclk1_mirb, + msm_mux_aud_mclk2_mira, + msm_mux_aud_mclk2_mirb, + msm_mux_aud_refclk0, + msm_mux_aud_refclk1, + msm_mux_bist_done, + msm_mux_ccu_async_in, + msm_mux_ccu_i2c_scl, + msm_mux_ccu_i2c_sda, + msm_mux_ccu_timer, + msm_mux_clink_debug, + msm_mux_dbg_out, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi, + msm_mux_dp_rx0, + msm_mux_dp_rx00, + msm_mux_dp_rx01, + msm_mux_dp_rx0_mute, + msm_mux_dp_rx1, + msm_mux_dp_rx10, + msm_mux_dp_rx11, + msm_mux_dp_rx1_mute, + msm_mux_edp0_hot, + msm_mux_edp0_lcd, + msm_mux_edp1_hot, + msm_mux_edp1_lcd, + msm_mux_edp2_hot, + msm_mux_edp2_lcd, + msm_mux_edp3_hot, + msm_mux_edp3_lcd, + msm_mux_emac0_mcg, + msm_mux_emac0_mdc, + msm_mux_emac0_mdio, + msm_mux_emac0_ptp, + msm_mux_emac1_mcg, + msm_mux_emac1_mdc, + msm_mux_emac1_mdio, + msm_mux_emac1_ptp, + msm_mux_gcc_gp1_clk, + msm_mux_gcc_gp2_clk, + msm_mux_gcc_gp3_clk, + msm_mux_gcc_gp4_clk, + msm_mux_gcc_gp5_clk, + msm_mux_gcc_gp6_clk, + msm_mux_gcc_gp7_clk, + msm_mux_gcc_gp8_clk, + msm_mux_gpio, + msm_mux_jitter_bist, + msm_mux_lbist_pass, + msm_mux_mbist_pass, + msm_mux_mdp0_vsync_out, + msm_mux_mdp1_vsync_out, + msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_p, + msm_mux_mdp_vsync_s, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie1_clk_req_n, + msm_mux_pcie2_clk_req_n, + msm_mux_pcie3_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_pwrbrk_i_n, + msm_mux_qdss, + msm_mux_qdss_cti, + msm_mux_qspi, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3, + msm_mux_qup0_se4, + msm_mux_qup0_se5, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4, + msm_mux_qup2_se5, + msm_mux_qup2_se6, + msm_mux_qup3_se0_mira, + msm_mux_qup3_se0_mirb, + msm_mux_sailss_ospi, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_smb_alert, + msm_mux_smb_alert_n, + msm_mux_smb_clk, + msm_mux_smb_dat, + msm_mux_tb_trig_sdc4, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tsc_timer, + msm_mux_tsense_pwm, + msm_mux_usb0_hs, + msm_mux_usb0_phy_ps, + msm_mux_usb1_hs, + msm_mux_usb1_phy_ps, + msm_mux_usb2_hs, + msm_mux_usxgmii0_phy, + msm_mux_usxgmii1_phy, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw, + msm_mux_wcn_sw_ctrl, + msm_mux__, +}; + +#define MSM_PIN_FUNCTION(fname) \ + [msm_mux_##fname] = {#fname, msm_mux_##fname} + +static const struct pinctrl_function msm_pinctrl_functions[] = { + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb20), + MSM_PIN_FUNCTION(atest_usb21), + MSM_PIN_FUNCTION(aud_intfc0_clk), + MSM_PIN_FUNCTION(aud_intfc0_data), + MSM_PIN_FUNCTION(aud_intfc0_ws), + MSM_PIN_FUNCTION(aud_intfc10_clk), + MSM_PIN_FUNCTION(aud_intfc10_data), + MSM_PIN_FUNCTION(aud_intfc10_ws), + MSM_PIN_FUNCTION(aud_intfc1_clk), + MSM_PIN_FUNCTION(aud_intfc1_data), + MSM_PIN_FUNCTION(aud_intfc1_ws), + MSM_PIN_FUNCTION(aud_intfc2_clk), + MSM_PIN_FUNCTION(aud_intfc2_data), + MSM_PIN_FUNCTION(aud_intfc2_ws), + MSM_PIN_FUNCTION(aud_intfc3_clk), + MSM_PIN_FUNCTION(aud_intfc3_data), + MSM_PIN_FUNCTION(aud_intfc3_ws), + MSM_PIN_FUNCTION(aud_intfc4_clk), + MSM_PIN_FUNCTION(aud_intfc4_data), + MSM_PIN_FUNCTION(aud_intfc4_ws), + MSM_PIN_FUNCTION(aud_intfc5_clk), + MSM_PIN_FUNCTION(aud_intfc5_data), + MSM_PIN_FUNCTION(aud_intfc5_ws), + MSM_PIN_FUNCTION(aud_intfc6_clk), + MSM_PIN_FUNCTION(aud_intfc6_data), + MSM_PIN_FUNCTION(aud_intfc6_ws), + MSM_PIN_FUNCTION(aud_intfc7_clk), + MSM_PIN_FUNCTION(aud_intfc7_data), + MSM_PIN_FUNCTION(aud_intfc7_ws), + MSM_PIN_FUNCTION(aud_intfc8_clk), + MSM_PIN_FUNCTION(aud_intfc8_data), + MSM_PIN_FUNCTION(aud_intfc8_ws), + MSM_PIN_FUNCTION(aud_intfc9_clk), + MSM_PIN_FUNCTION(aud_intfc9_data), + MSM_PIN_FUNCTION(aud_intfc9_ws), + MSM_PIN_FUNCTION(aud_mclk0_mira), + MSM_PIN_FUNCTION(aud_mclk0_mirb), + MSM_PIN_FUNCTION(aud_mclk1_mira), + MSM_PIN_FUNCTION(aud_mclk1_mirb), + MSM_PIN_FUNCTION(aud_mclk2_mira), + MSM_PIN_FUNCTION(aud_mclk2_mirb), + MSM_PIN_FUNCTION(aud_refclk0), + MSM_PIN_FUNCTION(aud_refclk1), + MSM_PIN_FUNCTION(bist_done), + MSM_PIN_FUNCTION(ccu_async_in), + MSM_PIN_FUNCTION(ccu_i2c_scl), + MSM_PIN_FUNCTION(ccu_i2c_sda), + MSM_PIN_FUNCTION(ccu_timer), + MSM_PIN_FUNCTION(clink_debug), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(dp_rx0), + MSM_PIN_FUNCTION(dp_rx00), + MSM_PIN_FUNCTION(dp_rx01), + MSM_PIN_FUNCTION(dp_rx0_mute), + MSM_PIN_FUNCTION(dp_rx1), + MSM_PIN_FUNCTION(dp_rx10), + MSM_PIN_FUNCTION(dp_rx11), + MSM_PIN_FUNCTION(dp_rx1_mute), + MSM_PIN_FUNCTION(edp0_hot), + MSM_PIN_FUNCTION(edp0_lcd), + MSM_PIN_FUNCTION(edp1_hot), + MSM_PIN_FUNCTION(edp1_lcd), + MSM_PIN_FUNCTION(edp2_hot), + MSM_PIN_FUNCTION(edp2_lcd), + MSM_PIN_FUNCTION(edp3_hot), + MSM_PIN_FUNCTION(edp3_lcd), + MSM_PIN_FUNCTION(emac0_mcg), + MSM_PIN_FUNCTION(emac0_mdc), + MSM_PIN_FUNCTION(emac0_mdio), + MSM_PIN_FUNCTION(emac0_ptp), + MSM_PIN_FUNCTION(emac1_mcg), + MSM_PIN_FUNCTION(emac1_mdc), + MSM_PIN_FUNCTION(emac1_mdio), + MSM_PIN_FUNCTION(emac1_ptp), + MSM_PIN_FUNCTION(gcc_gp1_clk), + MSM_PIN_FUNCTION(gcc_gp2_clk), + MSM_PIN_FUNCTION(gcc_gp3_clk), + MSM_PIN_FUNCTION(gcc_gp4_clk), + MSM_PIN_FUNCTION(gcc_gp5_clk), + MSM_PIN_FUNCTION(gcc_gp6_clk), + MSM_PIN_FUNCTION(gcc_gp7_clk), + MSM_PIN_FUNCTION(gcc_gp8_clk), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(lbist_pass), + MSM_PIN_FUNCTION(mbist_pass), + MSM_PIN_FUNCTION(mdp0_vsync_out), + MSM_PIN_FUNCTION(mdp1_vsync_out), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_p), + MSM_PIN_FUNCTION(mdp_vsync_s), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(pcie2_clk_req_n), + MSM_PIN_FUNCTION(pcie3_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(pwrbrk_i_n), + MSM_PIN_FUNCTION(qdss), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qspi), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3), + MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(qup0_se5), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4), + MSM_PIN_FUNCTION(qup2_se5), + MSM_PIN_FUNCTION(qup2_se6), + MSM_PIN_FUNCTION(qup3_se0_mira), + MSM_PIN_FUNCTION(qup3_se0_mirb), + MSM_PIN_FUNCTION(sailss_ospi), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(smb_alert), + MSM_PIN_FUNCTION(smb_alert_n), + MSM_PIN_FUNCTION(smb_clk), + MSM_PIN_FUNCTION(smb_dat), + MSM_PIN_FUNCTION(tb_trig_sdc4), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tsc_timer), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb0_phy_ps), + MSM_PIN_FUNCTION(usb1_hs), + MSM_PIN_FUNCTION(usb1_phy_ps), + MSM_PIN_FUNCTION(usb2_hs), + MSM_PIN_FUNCTION(usxgmii0_phy), + MSM_PIN_FUNCTION(usxgmii1_phy), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw), + MSM_PIN_FUNCTION(wcn_sw_ctrl), +}; + +static const msm_pin_function nord_pin_functions[] = { + [0] = PINGROUP(0, _, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, pcie0_clk_req_n, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, _, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, _, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, pcie1_clk_req_n, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, _, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, _, _, _, _, _, _, _, _, _), + [7] = PINGROUP(7, pcie2_clk_req_n, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, _, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, _, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, pcie3_clk_req_n, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, usb0_hs, clink_debug, _, _, _, _, _, _, _), + [13] = PINGROUP(13, usb1_hs, clink_debug, gcc_gp7_clk, _, _, _, _, _, _), + [14] = PINGROUP(14, usb2_hs, clink_debug, gcc_gp8_clk, _, _, _, _, _, _), + [15] = PINGROUP(15, ccu_i2c_sda, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, ccu_i2c_scl, emac0_mcg, _, _, _, _, _, _, _), + [17] = PINGROUP(17, ccu_i2c_sda, emac0_mcg, _, _, _, _, _, _, _), + [18] = PINGROUP(18, ccu_i2c_scl, emac0_mcg, _, _, _, _, _, _, _), + [19] = PINGROUP(19, ccu_i2c_sda, emac0_mcg, _, _, _, _, _, _, _), + [20] = PINGROUP(20, ccu_i2c_scl, emac1_mcg, _, _, _, _, _, _, _), + [21] = PINGROUP(21, ccu_i2c_sda, emac1_mcg, _, _, _, _, _, _, _), + [22] = PINGROUP(22, ccu_i2c_scl, emac1_mcg, _, _, _, _, _, _, _), + [23] = PINGROUP(23, ccu_i2c_sda, emac1_mcg, _, _, _, _, _, _, _), + [24] = PINGROUP(24, ccu_i2c_scl, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, ccu_timer, tsc_timer, _, _, _, _, _, _, _), + [26] = PINGROUP(26, ccu_timer, tsc_timer, _, _, _, _, _, _, _), + [27] = PINGROUP(27, ccu_timer, tsc_timer, _, _, _, _, _, _, _), + [28] = PINGROUP(28, ccu_timer, tsc_timer, _, _, _, _, _, _, _), + [29] = PINGROUP(29, ccu_timer, tsc_timer, _, _, _, _, _, _, _), + [30] = PINGROUP(30, ccu_timer, tsc_timer, _, _, _, _, _, _, _), + [31] = PINGROUP(31, ccu_timer, tsc_timer, _, _, _, _, _, _, _), + [32] = PINGROUP(32, ccu_timer, tsc_timer, _, _, _, _, _, _, _), + [33] = PINGROUP(33, ccu_timer, tsc_timer, _, _, _, _, _, _, _), + [34] = PINGROUP(34, ccu_timer, tsc_timer, _, _, _, _, _, _, _), + [35] = PINGROUP(35, dp_rx0_mute, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, dp_rx1_mute, ddr_bist_start, _, _, _, _, _, _, _), + [37] = PINGROUP(37, emac1_ptp, ddr_bist_complete, _, _, _, _, _, _, _), + [38] = PINGROUP(38, emac1_ptp, ddr_bist_stop, _, _, _, _, _, _, _), + [39] = PINGROUP(39, emac1_ptp, ddr_bist_fail, _, _, _, _, _, _, _), + [40] = PINGROUP(40, emac1_ptp, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, emac1_ptp, qdss_cti, _, _, _, _, _, _, _), + [42] = PINGROUP(42, emac1_ptp, qdss_cti, gcc_gp3_clk, _, _, _, _, _, _), + [43] = PINGROUP(43, emac1_ptp, gcc_gp4_clk, tsense_pwm, _, _, _, _, _, _), + [44] = PINGROUP(44, emac1_ptp, tsense_pwm, _, _, _, _, _, _, _), + [45] = PINGROUP(45, usxgmii0_phy, ccu_async_in, tsense_pwm, _, _, _, _, _, _), + [46] = PINGROUP(46, usxgmii1_phy, tsense_pwm, _, _, _, _, _, _, _), + [47] = PINGROUP(47, emac0_mdc, edp0_lcd, tsense_pwm, _, _, _, _, _, _), + [48] = PINGROUP(48, emac0_mdio, edp1_lcd, tsense_pwm, _, _, _, _, _, _), + [49] = PINGROUP(49, emac1_mdc, edp2_lcd, tsense_pwm, _, _, _, _, _, _), + [50] = PINGROUP(50, emac1_mdio, edp3_lcd, tsense_pwm, _, _, _, _, _, _), + [51] = PINGROUP(51, edp0_hot, clink_debug, gcc_gp1_clk, _, _, _, _, _, _), + [52] = PINGROUP(52, edp1_hot, clink_debug, gcc_gp2_clk, _, _, _, _, _, _), + [53] = PINGROUP(53, edp2_hot, clink_debug, _, _, _, _, _, _, _), + [54] = PINGROUP(54, edp3_hot, clink_debug, _, _, _, _, _, _, _), + [55] = PINGROUP(55, dp_rx0, clink_debug, _, _, _, _, _, _, _), + [56] = PINGROUP(56, dp_rx1, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, aud_intfc0_clk, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, aud_intfc0_ws, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, aud_intfc0_data, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, aud_intfc0_data, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, aud_intfc0_data, aud_intfc10_clk, _, _, _, _, _, _, _), + [62] = PINGROUP(62, aud_intfc0_data, aud_intfc10_ws, _, _, _, _, _, _, _), + [63] = PINGROUP(63, aud_intfc0_data, aud_intfc7_clk, _, _, _, _, _, _, _), + [64] = PINGROUP(64, aud_intfc0_data, aud_intfc7_ws, _, _, _, _, _, _, _), + [65] = PINGROUP(65, aud_intfc0_data, aud_intfc7_data, _, _, _, _, _, _, _), + [66] = PINGROUP(66, aud_intfc0_data, aud_intfc7_data, _, _, _, _, _, _, _), + [67] = PINGROUP(67, aud_intfc1_clk, phase_flag, _, qdss, _, _, _, _, _), + [68] = PINGROUP(68, aud_intfc1_ws, phase_flag, _, qdss, _, _, _, _, _), + [69] = PINGROUP(69, aud_intfc1_data, phase_flag, _, qdss, _, _, _, _, _), + [70] = PINGROUP(70, aud_intfc1_data, aud_intfc9_clk, phase_flag, _, qdss, _, _, _, _), + [71] = PINGROUP(71, aud_intfc1_data, aud_intfc9_ws, phase_flag, _, qdss, _, _, _, _), + [72] = PINGROUP(72, aud_intfc1_data, aud_intfc9_data, phase_flag, _, qdss, _, _, _, _), + [73] = PINGROUP(73, aud_intfc1_data, aud_intfc8_clk, phase_flag, _, qdss, _, _, _, _), + [74] = PINGROUP(74, aud_intfc1_data, aud_intfc8_ws, phase_flag, _, qdss, _, _, _, _), + [75] = PINGROUP(75, aud_intfc1_data, aud_intfc8_data, phase_flag, _, qdss, _, _, _, _), + [76] = PINGROUP(76, aud_intfc1_data, aud_intfc8_data, phase_flag, _, qdss, _, _, _, _), + [77] = PINGROUP(77, aud_intfc2_clk, phase_flag, _, qdss, _, _, _, _, _), + [78] = PINGROUP(78, aud_intfc2_ws, phase_flag, _, qdss, _, _, _, _, _), + [79] = PINGROUP(79, aud_intfc2_data, phase_flag, _, qdss, _, _, _, _, _), + [80] = PINGROUP(80, aud_intfc2_data, phase_flag, _, _, qdss, _, _, _, _), + [81] = PINGROUP(81, aud_intfc2_data, aud_intfc10_data, phase_flag, _, _, qdss, _, _, _), + [82] = PINGROUP(82, aud_intfc2_data, aud_intfc10_data, phase_flag, _, qdss, _, _, _, _), + [83] = PINGROUP(83, aud_intfc3_clk, dp_rx0, aoss_cti, phase_flag, _, qdss, _, _, _), + [84] = PINGROUP(84, aud_intfc3_ws, dp_rx0, aoss_cti, phase_flag, _, qdss, _, _, _), + [85] = PINGROUP(85, aud_intfc3_data, dp_rx0, aoss_cti, phase_flag, _, qdss, _, _, _), + [86] = PINGROUP(86, aud_intfc3_data, aud_mclk0_mirb, dp_rx0, aoss_cti, phase_flag, _, qdss, _, _), + [87] = PINGROUP(87, aud_intfc4_clk, phase_flag, _, qdss, _, _, _, _, _), + [88] = PINGROUP(88, aud_intfc4_ws, dp_rx0, phase_flag, _, qdss, _, _, _, _), + [89] = PINGROUP(89, aud_intfc4_data, dp_rx0, phase_flag, _, qdss, _, _, _, _), + [90] = PINGROUP(90, aud_intfc4_data, aud_mclk1_mirb, phase_flag, _, qdss, _, _, _, _), + [91] = PINGROUP(91, aud_intfc5_clk, phase_flag, _, qdss, _, _, _, _, _), + [92] = PINGROUP(92, aud_intfc5_ws, dp_rx1, phase_flag, _, qdss, _, _, _, _), + [93] = PINGROUP(93, aud_intfc5_data, dp_rx1, phase_flag, _, qdss, _, _, _, _), + [94] = PINGROUP(94, aud_intfc5_data, aud_mclk2_mirb, phase_flag, tmess_prng0, _, qdss, _, _, _), + [95] = PINGROUP(95, aud_intfc6_clk, dp_rx1, phase_flag, tmess_prng1, _, qdss, _, _, _), + [96] = PINGROUP(96, aud_intfc6_ws, dp_rx1, phase_flag, _, qdss, _, _, _, _), + [97] = PINGROUP(97, aud_intfc6_data, dp_rx1, qdss, _, _, _, _, _, _), + [98] = PINGROUP(98, aud_intfc6_data, dp_rx1, phase_flag, _, qdss, _, _, _, _), + [99] = PINGROUP(99, aud_mclk0_mira, qdss, dp_rx00, ddr_pxi, _, _, _, _, _), + [100] = PINGROUP(100, aud_mclk1_mira, aud_refclk0, pll_clk_aux, qdss, dp_rx01, ddr_pxi, _, _, _), + [101] = PINGROUP(101, aud_mclk2_mira, aud_refclk1, phase_flag, _, qdss, _, _, _, _), + [102] = PINGROUP(102, qspi, qup3_se0_mira, qup3_se0_mirb, _, _, _, _, _, _), + [103] = PINGROUP(103, qspi, qup3_se0_mira, qup3_se0_mirb, _, _, _, _, _, _), + [104] = PINGROUP(104, qspi, qup3_se0_mira, _, _, _, _, _, _, _), + [105] = PINGROUP(105, qspi, qup3_se0_mira, gcc_gp5_clk, _, _, _, _, _, _), + [106] = PINGROUP(106, qspi, qup3_se0_mira, gcc_gp6_clk, _, _, _, _, _, _), + [107] = PINGROUP(107, qspi, qup3_se0_mira, _, _, _, _, _, _, _), + [108] = PINGROUP(108, qspi, qup3_se0_mira, qdss, _, _, _, _, _, _), + [109] = PINGROUP(109, qup0_se0, qup0_se1, qup0_se5, mdp_vsync_e, smb_alert_n, _, ddr_pxi, _, _), + [110] = PINGROUP(110, qup0_se0, qup0_se1, qup0_se5, qdss_cti, mdp_vsync_p, smb_alert, _, ddr_pxi, _), + [111] = PINGROUP(111, qup0_se1, qup0_se0, smb_dat, _, _, _, _, _, _), + [112] = PINGROUP(112, qup0_se1, qup0_se0, smb_clk, _, _, _, _, _, _), + [113] = PINGROUP(113, qup0_se2, qup0_se3, ccu_i2c_sda, mdp0_vsync_out, dbg_out, ddr_pxi, _, _, _), + [114] = PINGROUP(114, qup0_se2, qup0_se3, ccu_i2c_scl, mdp0_vsync_out, _, ddr_pxi, _, _, _), + [115] = PINGROUP(115, qup0_se3, qup0_se2, ccu_i2c_sda, mdp0_vsync_out, _, ddr_pxi, _, _, _), + [116] = PINGROUP(116, qup0_se3, qup0_se2, ccu_i2c_scl, mdp0_vsync_out, _, ddr_pxi, _, _, _), + [117] = PINGROUP(117, qup0_se4, prng_rosc0, _, ddr_pxi, _, _, _, _, _), + [118] = PINGROUP(118, qup0_se4, prng_rosc1, _, ddr_pxi, _, _, _, _, _), + [119] = PINGROUP(119, qup0_se4, _, ddr_pxi, _, _, _, _, _, _), + [120] = PINGROUP(120, qup0_se4, _, ddr_pxi, _, _, _, _, _, _), + [121] = PINGROUP(121, qup0_se5, lbist_pass, mdp0_vsync_out, _, dp_rx10, ddr_pxi, _, _, _), + [122] = PINGROUP(122, qup0_se5, mbist_pass, mdp0_vsync_out, _, dp_rx11, ddr_pxi, _, _, _), + [123] = PINGROUP(123, qup1_se0, qup1_se1, mdp1_vsync_out, jitter_bist, _, _, _, _, _), + [124] = PINGROUP(124, qup1_se0, qup1_se1, mdp1_vsync_out, _, _, _, _, _, _), + [125] = PINGROUP(125, qup1_se1, qup1_se0, ccu_i2c_sda, mdp1_vsync_out, _, _, _, _, _), + [126] = PINGROUP(126, qup1_se1, qup1_se0, ccu_i2c_scl, mdp1_vsync_out, _, atest_usb20, ddr_pxi, _, _), + [127] = PINGROUP(127, qup1_se2, qup1_se2, _, atest_usb21, ddr_pxi, _, _, _, _), + [128] = PINGROUP(128, qup1_se2, qup1_se2, _, atest_usb20, ddr_pxi, _, _, _, _), + [129] = PINGROUP(129, qup1_se3, qup1_se3, ccu_i2c_sda, mdp1_vsync_out, _, atest_usb21, ddr_pxi, _, _), + [130] = PINGROUP(130, qup1_se3, qup1_se3, ccu_i2c_scl, mdp1_vsync_out, _, atest_usb20, ddr_pxi, _, _), + [131] = PINGROUP(131, qup1_se4, qup1_se6, ccu_i2c_sda, mdp1_vsync_out, _, atest_usb21, ddr_pxi, _, _), + [132] = PINGROUP(132, qup1_se4, qup1_se6, ccu_i2c_scl, mdp1_vsync_out, _, vsense_trigger_mirnat, ddr_pxi, _, _), + [133] = PINGROUP(133, qup1_se5, emac0_ptp, mdp1_vsync_out, _, ddr_pxi, _, _, _, _), + [134] = PINGROUP(134, qup1_se5, emac0_ptp, mdp1_vsync_out, _, ddr_pxi, _, _, _, _), + [135] = PINGROUP(135, qup1_se5, emac0_ptp, mdp1_vsync_out, _, ddr_pxi, _, _, _, _), + [136] = PINGROUP(136, qup1_se5, emac0_ptp, _, ddr_pxi, _, _, _, _, _), + [137] = PINGROUP(137, qup1_se6, qup1_se4, dp_rx0, _, ddr_pxi, _, _, _, _), + [138] = PINGROUP(138, qup1_se6, qup1_se4, dp_rx0, qdss_cti, jitter_bist, ddr_pxi, _, _, _), + [139] = PINGROUP(139, qup2_se0, emac0_ptp, mdp0_vsync_out, ddr_pxi, _, _, _, _, _), + [140] = PINGROUP(140, qup2_se0, emac0_ptp, mdp0_vsync_out, _, _, _, _, _, _), + [141] = PINGROUP(141, qup2_se0, emac0_ptp, mdp0_vsync_out, _, _, _, _, _, _), + [142] = PINGROUP(142, qup2_se0, emac0_ptp, qdss_cti, mdp0_vsync_out, _, _, _, _, _), + [143] = PINGROUP(143, qup2_se1, qup2_se4, ccu_timer, mdp0_vsync_out, _, _, _, _, _), + [144] = PINGROUP(144, qup2_se1, qup2_se4, ccu_timer, qdss_cti, mdp_vsync_s, _, _, _, _), + [145] = PINGROUP(145, qup2_se2, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, qup2_se2, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, qup2_se2, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, qup2_se2, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, qup2_se2, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, qup2_se3, qup2_se4, ccu_timer, _, _, _, _, _, _), + [151] = PINGROUP(151, qup2_se3, qup2_se4, ccu_timer, _, _, _, _, _, _), + [152] = PINGROUP(152, qup2_se3, qup2_se4, ccu_timer, _, _, _, _, _, _), + [153] = PINGROUP(153, qup2_se3, ccu_timer, _, _, _, _, _, _, _), + [154] = PINGROUP(154, qup2_se4, qup2_se1, _, _, _, _, _, _, _), + [155] = PINGROUP(155, qup2_se4, qup2_se1, _, _, _, _, _, _, _), + [156] = PINGROUP(156, qup2_se5, qup2_se6, _, _, _, _, _, _, _), + [157] = PINGROUP(157, qup2_se5, qup2_se6, _, _, _, _, _, _, _), + [158] = PINGROUP(158, qup2_se6, qup2_se5, dp_rx1, _, _, _, _, _, _), + [159] = PINGROUP(159, qup2_se6, qup2_se5, dp_rx1, _, _, _, _, _, _), + [160] = PINGROUP(160, wcn_sw_ctrl, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, wcn_sw, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, qdss_cti, _, ddr_pxi, _, _, _, _, _, _), + [163] = PINGROUP(163, qdss_cti, _, ddr_pxi, _, _, _, _, _, _), + [164] = PINGROUP(164, usb0_phy_ps, _, sailss_ospi, ddr_pxi, _, _, _, _, _), + [165] = PINGROUP(165, usb1_phy_ps, dbg_out_clk, sailss_ospi, ddr_pxi, _, _, _, _, _), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, pwrbrk_i_n, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, bist_done, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, tb_trig_sdc4, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, sdc4_data, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, sdc4_data, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, sdc4_data, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, sdc4_data, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, sdc4_cmd, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, sdc4_clk, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, ccu_async_in, pll_bist_sync, atest_char, _, _, _, _, _, _), + [177] = PINGROUP(177, ccu_async_in, atest_char, _, _, _, _, _, _, _), + [178] = PINGROUP(178, ccu_async_in, atest_char, _, _, _, _, _, _, _), + [179] = PINGROUP(179, ccu_async_in, atest_char, _, _, _, _, _, _, _), + [180] = PINGROUP(180, ccu_async_in, atest_char, _, _, _, _, _, _, _), +}; + +static const struct msm_special_pin_data nord_special_pins_data[] = { + [0] = UFS_RESET(ufs_reset, 0xbd004, 0xbe000), +}; + +static const char *nord_get_function_name(struct udevice *dev, unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *nord_get_pin_name(struct udevice *dev, unsigned int selector) +{ + if (selector >= 181) + snprintf(pin_name, MAX_PIN_NAME_LEN, + nord_special_pins_data[selector - 181].name); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static int nord_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector) +{ + unsigned int i; + const msm_pin_function *func = NULL; + + if (pin >= ARRAY_SIZE(nord_pin_functions)) + return -EINVAL; + + func = nord_pin_functions + pin; + for (i = 0; i < 10; i++) + if ((*func)[i] == selector) + return i; + + pr_err("Can't find requested function for pin %u pin\n", pin); + + return -EINVAL; +} + +static struct msm_pinctrl_data nord_data = { + .pin_data = { + .pin_count = 182, + .special_pins_start = 181, + .special_pins_data = nord_special_pins_data, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = nord_get_function_name, + .get_function_mux = nord_get_function_mux, + .get_pin_name = nord_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { + .compatible = "qcom,nord-tlmm", + .data = (ulong)&nord_data + }, + { /* Sentinel */ } }; + +U_BOOT_DRIVER(pinctrl_nord) = { + .name = "pinctrl_nord", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 50e7d7499212..aed827628de7 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -638,6 +638,33 @@ int scsi_scan_dev(struct udevice *dev, bool verbose) return 0; } +int scsi_scan_new(bool verbose) +{ + struct uclass *uc; + struct udevice *dev; + int ret; + + if (verbose) + printf("scanning bus for devices...\n"); + + ret = uclass_get(UCLASS_SCSI, &uc); + if (ret) + return ret; + + uclass_foreach_dev(dev, uc) { + struct udevice *blk; + + if (device_find_first_child_by_uclass(dev, UCLASS_BLK, &blk) == 0) + continue; + + ret = scsi_scan_dev(dev, verbose); + if (ret) + return ret; + } + + return 0; +} + int scsi_scan(bool verbose) { struct uclass *uc; diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 2ce81542bf13..c3a15811ab0f 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -88,7 +88,7 @@ #define SMEM_GLOBAL_HOST 0xfffe /* Max number of processors/hosts in a system */ -#define SMEM_HOST_COUNT 30 +#define SMEM_HOST_COUNT 256 /** * struct smem_proc_comm - proc_comm communication struct (legacy) @@ -937,7 +937,8 @@ qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host) continue; if (remote_host >= SMEM_HOST_COUNT) { - log_err("bad host %u\n", remote_host); + log_err("bad host %u (SMEM_HOST_COUNT=%u too small)\n", + remote_host, SMEM_HOST_COUNT); return -EINVAL; } diff --git a/include/dt-bindings/clock/qcom,nord-camcc.h b/include/dt-bindings/clock/qcom,nord-camcc.h new file mode 100644 index 000000000000..655fef2084a5 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-camcc.h @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_NORD_H + +/* CAM_CC clocks */ +#define CAM_CC_CAMNOC_DCD_XO_CLK 0 +#define CAM_CC_CAMNOC_NRT_AXI_CLK 1 +#define CAM_CC_CAMNOC_RT_AXI_CLK 2 +#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 3 +#define CAM_CC_CAMNOC_XO_CLK 4 +#define CAM_CC_CCI_0_CLK 5 +#define CAM_CC_CCI_0_CLK_SRC 6 +#define CAM_CC_CCI_1_CLK 7 +#define CAM_CC_CCI_1_CLK_SRC 8 +#define CAM_CC_CCI_2_CLK 9 +#define CAM_CC_CCI_2_CLK_SRC 10 +#define CAM_CC_CCI_3_CLK 11 +#define CAM_CC_CCI_3_CLK_SRC 12 +#define CAM_CC_CCI_4_CLK 13 +#define CAM_CC_CCI_4_CLK_SRC 14 +#define CAM_CC_CCU_FAST_AHB_CLK 15 +#define CAM_CC_CORE_AHB_CLK 16 +#define CAM_CC_CPHY_RX_CLK_SRC 17 +#define CAM_CC_CSI0PHYTIMER_CLK 18 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 19 +#define CAM_CC_CSI1PHYTIMER_CLK 20 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 21 +#define CAM_CC_CSI2PHYTIMER_CLK 22 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 23 +#define CAM_CC_CSI3PHYTIMER_CLK 24 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 25 +#define CAM_CC_CSI4PHYTIMER_CLK 26 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 27 +#define CAM_CC_CSID_CLK 28 +#define CAM_CC_CSID_CLK_SRC 29 +#define CAM_CC_CSID_CSIPHY_RX_CLK 30 +#define CAM_CC_CSIPHY0_CLK 31 +#define CAM_CC_CSIPHY1_CLK 32 +#define CAM_CC_CSIPHY2_CLK 33 +#define CAM_CC_CSIPHY3_CLK 34 +#define CAM_CC_CSIPHY4_CLK 35 +#define CAM_CC_FAST_AHB_CLK_SRC 36 +#define CAM_CC_GDSC_CLK 37 +#define CAM_CC_ICP_0_AHB_CLK 38 +#define CAM_CC_ICP_0_CLK 39 +#define CAM_CC_ICP_0_CLK_SRC 40 +#define CAM_CC_ICP_1_AHB_CLK 41 +#define CAM_CC_ICP_1_CLK 42 +#define CAM_CC_ICP_1_CLK_SRC 43 +#define CAM_CC_IFE_0_MAIN_CLK 44 +#define CAM_CC_IFE_0_MAIN_CLK_SRC 45 +#define CAM_CC_IFE_0_MAIN_FAST_AHB_CLK 46 +#define CAM_CC_IFE_0_PCP_CLK 47 +#define CAM_CC_IFE_0_PCP_FAST_AHB_CLK 48 +#define CAM_CC_IFE_0_SCALAR_CLK 49 +#define CAM_CC_IFE_0_SCALAR_FAST_AHB_CLK 50 +#define CAM_CC_IFE_0_TMC_CLK 51 +#define CAM_CC_IFE_0_TMC_FAST_AHB_CLK 52 +#define CAM_CC_IFE_1_MAIN_CLK 53 +#define CAM_CC_IFE_1_MAIN_CLK_SRC 54 +#define CAM_CC_IFE_1_MAIN_FAST_AHB_CLK 55 +#define CAM_CC_IFE_1_PCP_CLK 56 +#define CAM_CC_IFE_1_PCP_FAST_AHB_CLK 57 +#define CAM_CC_IFE_1_SCALAR_CLK 58 +#define CAM_CC_IFE_1_SCALAR_FAST_AHB_CLK 59 +#define CAM_CC_IFE_1_TMC_CLK 60 +#define CAM_CC_IFE_1_TMC_FAST_AHB_CLK 61 +#define CAM_CC_IFE_2_MAIN_CLK 62 +#define CAM_CC_IFE_2_MAIN_CLK_SRC 63 +#define CAM_CC_IFE_2_MAIN_FAST_AHB_CLK 64 +#define CAM_CC_IFE_2_PCP_CLK 65 +#define CAM_CC_IFE_2_PCP_FAST_AHB_CLK 66 +#define CAM_CC_IFE_2_SCALAR_CLK 67 +#define CAM_CC_IFE_2_SCALAR_FAST_AHB_CLK 68 +#define CAM_CC_IFE_2_TMC_CLK 69 +#define CAM_CC_IFE_2_TMC_FAST_AHB_CLK 70 +#define CAM_CC_IFE_LITE_AHB_CLK 71 +#define CAM_CC_IFE_LITE_CLK 72 +#define CAM_CC_IFE_LITE_CLK_SRC 73 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 74 +#define CAM_CC_IFE_LITE_CSID_CLK 75 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 76 +#define CAM_CC_IPE_0_AHB_CLK 77 +#define CAM_CC_IPE_0_CLK 78 +#define CAM_CC_IPE_0_CLK_SRC 79 +#define CAM_CC_IPE_0_FAST_AHB_CLK 80 +#define CAM_CC_IPE_1_AHB_CLK 81 +#define CAM_CC_IPE_1_CLK 82 +#define CAM_CC_IPE_1_CLK_SRC 83 +#define CAM_CC_IPE_1_FAST_AHB_CLK 84 +#define CAM_CC_PLL0 85 +#define CAM_CC_PLL0_OUT_EVEN 86 +#define CAM_CC_PLL0_OUT_ODD 87 +#define CAM_CC_PLL2 88 +#define CAM_CC_PLL2_OUT_EVEN 89 +#define CAM_CC_PLL3 90 +#define CAM_CC_PLL3_OUT_EVEN 91 +#define CAM_CC_PLL4 92 +#define CAM_CC_PLL4_OUT_EVEN 93 +#define CAM_CC_PLL5 94 +#define CAM_CC_PLL5_OUT_EVEN 95 +#define CAM_CC_PLL6 96 +#define CAM_CC_PLL6_OUT_EVEN 97 +#define CAM_CC_QDSS_DEBUG_CLK 98 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 99 +#define CAM_CC_QDSS_DEBUG_XO_CLK 100 +#define CAM_CC_QUP_AHBM_CLK 101 +#define CAM_CC_QUP_AHBM_CLK_SRC 102 +#define CAM_CC_QUP_CORE_2X_CLK 103 +#define CAM_CC_QUP_CORE_2X_CLK_SRC 104 +#define CAM_CC_QUP_CORE_2X_DIV_CLK_SRC 105 +#define CAM_CC_QUP_CORE_CLK 106 +#define CAM_CC_QUP_SE_CLK 107 +#define CAM_CC_QUP_SE_CLK_SRC 108 +#define CAM_CC_QUP_SLEEP_CLK 109 +#define CAM_CC_SFE_LITE_0_CLK 110 +#define CAM_CC_SFE_LITE_0_FAST_AHB_CLK 111 +#define CAM_CC_SFE_LITE_1_CLK 112 +#define CAM_CC_SFE_LITE_1_FAST_AHB_CLK 113 +#define CAM_CC_SFE_LITE_2_CLK 114 +#define CAM_CC_SFE_LITE_2_FAST_AHB_CLK 115 +#define CAM_CC_SLEEP_CLK 116 +#define CAM_CC_SLEEP_CLK_SRC 117 +#define CAM_CC_SLOW_AHB_CLK_SRC 118 +#define CAM_CC_SM_OBS_CLK 119 +#define CAM_CC_TOP_AHB_CLK 120 +#define CAM_CC_TOP_FAST_AHB_CLK 121 +#define CAM_CC_TOP_IFE_0_CLK 122 +#define CAM_CC_TOP_IFE_1_CLK 123 +#define CAM_CC_TOP_IFE_2_CLK 124 +#define CAM_CC_TOP_IFE_LITE_CLK 125 +#define CAM_CC_TOP_IPE_0_CLK 126 +#define CAM_CC_TOP_IPE_1_CLK 127 +#define CAM_CC_TOP_QUP_AHBM_CLK 128 +#define CAM_CC_TOP_SFE_LITE_0_CLK 129 +#define CAM_CC_TOP_SFE_LITE_1_CLK 130 +#define CAM_CC_TOP_SFE_LITE_2_CLK 131 +#define CAM_CC_TPG_CSIPHY_RX_CLK 132 +#define CAM_CC_XO_CLK_SRC 133 + +/* CAM_CC power domains */ +#define CAM_CC_IFE_0_GDSC 0 +#define CAM_CC_IFE_1_GDSC 1 +#define CAM_CC_IFE_2_GDSC 2 +#define CAM_CC_IPE_0_GDSC 3 +#define CAM_CC_IPE_1_GDSC 4 +#define CAM_CC_TITAN_TOP_GDSC 5 + +/* CAM_CC resets */ +#define CAM_CC_CCU_BCR 0 +#define CAM_CC_ICP_0_BCR 1 +#define CAM_CC_ICP_1_BCR 2 +#define CAM_CC_IFE_0_BCR 3 +#define CAM_CC_IFE_1_BCR 4 +#define CAM_CC_IFE_2_BCR 5 +#define CAM_CC_IPE_0_BCR 6 +#define CAM_CC_IPE_1_BCR 7 +#define CAM_CC_QDSS_DEBUG_BCR 8 +#define CAM_CC_SFE_LITE_0_BCR 9 +#define CAM_CC_SFE_LITE_1_BCR 10 +#define CAM_CC_SFE_LITE_2_BCR 11 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-dispcc.h b/include/dt-bindings/clock/qcom,nord-dispcc.h new file mode 100644 index 000000000000..9f6c9979e0f3 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-dispcc.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_NORD_H + +/* DISP_CC_0 clocks */ +#define MDSS_DISP_CC_ACMU_CLK 0 +#define MDSS_DISP_CC_MDSS_ACCU_SHIFT_CLK 1 +#define MDSS_DISP_CC_MDSS_AHB1_CLK 2 +#define MDSS_DISP_CC_MDSS_AHB_CLK 3 +#define MDSS_DISP_CC_MDSS_AHB_CLK_SRC 4 +#define MDSS_DISP_CC_MDSS_BYTE0_CLK 5 +#define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC 6 +#define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 7 +#define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK 8 +#define MDSS_DISP_CC_MDSS_BYTE1_CLK 9 +#define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC 10 +#define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 11 +#define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK 12 +#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK 13 +#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 14 +#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK 15 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK 16 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 17 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 18 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 19 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK 20 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 21 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK 22 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 23 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK 24 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC 25 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK 26 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC 27 +#define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 28 +#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK 29 +#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 30 +#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK 31 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK 32 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 33 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 34 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 35 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK 36 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 37 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK 38 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 39 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK 40 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK_SRC 41 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK 42 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK_SRC 43 +#define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 44 +#define MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK 45 +#define MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 46 +#define MDSS_DISP_CC_MDSS_DPTX2_CRYPTO_CLK 47 +#define MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK 48 +#define MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 49 +#define MDSS_DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 50 +#define MDSS_DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 51 +#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK 52 +#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 53 +#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK 54 +#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 55 +#define MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK 56 +#define MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 57 +#define MDSS_DISP_CC_MDSS_DPTX3_CRYPTO_CLK 58 +#define MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK 59 +#define MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 60 +#define MDSS_DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 61 +#define MDSS_DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 62 +#define MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK 63 +#define MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 64 +#define MDSS_DISP_CC_MDSS_ESC0_CLK 65 +#define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC 66 +#define MDSS_DISP_CC_MDSS_ESC1_CLK 67 +#define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC 68 +#define MDSS_DISP_CC_MDSS_MDP1_CLK 69 +#define MDSS_DISP_CC_MDSS_MDP_CLK 70 +#define MDSS_DISP_CC_MDSS_MDP_CLK_SRC 71 +#define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK 72 +#define MDSS_DISP_CC_MDSS_MDP_LUT_CLK 73 +#define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK 74 +#define MDSS_DISP_CC_MDSS_PCLK0_CLK 75 +#define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC 76 +#define MDSS_DISP_CC_MDSS_PCLK1_CLK 77 +#define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC 78 +#define MDSS_DISP_CC_MDSS_PCLK2_CLK 79 +#define MDSS_DISP_CC_MDSS_PCLK2_CLK_SRC 80 +#define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK 81 +#define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK 82 +#define MDSS_DISP_CC_MDSS_VSYNC1_CLK 83 +#define MDSS_DISP_CC_MDSS_VSYNC_CLK 84 +#define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC 85 +#define MDSS_DISP_CC_PLL0 86 +#define MDSS_DISP_CC_PLL1 87 +#define MDSS_DISP_CC_PLL2 88 +#define MDSS_DISP_CC_PLL3 89 +#define MDSS_DISP_CC_SLEEP_CLK 90 +#define MDSS_DISP_CC_SLEEP_CLK_SRC 91 +#define MDSS_DISP_CC_SM_DIV_CLK_SRC 92 +#define MDSS_DISP_CC_XO_CLK 93 +#define MDSS_DISP_CC_XO_CLK_SRC 94 + +/* DISP_CC_0 power domains */ +#define MDSS_DISP_CC_MDSS_CORE_GDSC 0 +#define MDSS_DISP_CC_MDSS_CORE_INT2_GDSC 1 + +/* DISP_CC_0 resets */ +#define MDSS_DISP_CC_MDSS_CORE_BCR 0 +#define MDSS_DISP_CC_MDSS_CORE_INT2_BCR 1 +#define MDSS_DISP_CC_MDSS_RSCC_BCR 2 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-gcc.h b/include/dt-bindings/clock/qcom,nord-gcc.h new file mode 100644 index 000000000000..8fbde162c859 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-gcc.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_GCC_NORD_H + +/* GCC clocks */ +#define GCC_BOOT_ROM_AHB_CLK 0 +#define GCC_GP1_CLK 1 +#define GCC_GP1_CLK_SRC 2 +#define GCC_GP2_CLK 3 +#define GCC_GP2_CLK_SRC 4 +#define GCC_GPLL0 5 +#define GCC_GPLL0_OUT_EVEN 6 +#define GCC_MMU_0_TCU_VOTE_CLK 7 +#define GCC_PCIE_A_AUX_CLK 8 +#define GCC_PCIE_A_AUX_CLK_SRC 9 +#define GCC_PCIE_A_CFG_AHB_CLK 10 +#define GCC_PCIE_A_DTI_QTC_CLK 11 +#define GCC_PCIE_A_MSTR_AXI_CLK 12 +#define GCC_PCIE_A_PHY_AUX_CLK 13 +#define GCC_PCIE_A_PHY_AUX_CLK_SRC 14 +#define GCC_PCIE_A_PHY_RCHNG_CLK 15 +#define GCC_PCIE_A_PHY_RCHNG_CLK_SRC 16 +#define GCC_PCIE_A_PIPE_CLK 17 +#define GCC_PCIE_A_PIPE_CLK_SRC 18 +#define GCC_PCIE_A_SLV_AXI_CLK 19 +#define GCC_PCIE_A_SLV_Q2A_AXI_CLK 20 +#define GCC_PCIE_B_AUX_CLK 21 +#define GCC_PCIE_B_AUX_CLK_SRC 22 +#define GCC_PCIE_B_CFG_AHB_CLK 23 +#define GCC_PCIE_B_DTI_QTC_CLK 24 +#define GCC_PCIE_B_MSTR_AXI_CLK 25 +#define GCC_PCIE_B_PHY_AUX_CLK 26 +#define GCC_PCIE_B_PHY_AUX_CLK_SRC 27 +#define GCC_PCIE_B_PHY_RCHNG_CLK 28 +#define GCC_PCIE_B_PHY_RCHNG_CLK_SRC 29 +#define GCC_PCIE_B_PIPE_CLK 30 +#define GCC_PCIE_B_PIPE_CLK_SRC 31 +#define GCC_PCIE_B_SLV_AXI_CLK 32 +#define GCC_PCIE_B_SLV_Q2A_AXI_CLK 33 +#define GCC_PCIE_C_AUX_CLK 34 +#define GCC_PCIE_C_AUX_CLK_SRC 35 +#define GCC_PCIE_C_CFG_AHB_CLK 36 +#define GCC_PCIE_C_DTI_QTC_CLK 37 +#define GCC_PCIE_C_MSTR_AXI_CLK 38 +#define GCC_PCIE_C_PHY_AUX_CLK 39 +#define GCC_PCIE_C_PHY_AUX_CLK_SRC 40 +#define GCC_PCIE_C_PHY_RCHNG_CLK 41 +#define GCC_PCIE_C_PHY_RCHNG_CLK_SRC 42 +#define GCC_PCIE_C_PIPE_CLK 43 +#define GCC_PCIE_C_PIPE_CLK_SRC 44 +#define GCC_PCIE_C_SLV_AXI_CLK 45 +#define GCC_PCIE_C_SLV_Q2A_AXI_CLK 46 +#define GCC_PCIE_D_AUX_CLK 47 +#define GCC_PCIE_D_AUX_CLK_SRC 48 +#define GCC_PCIE_D_CFG_AHB_CLK 49 +#define GCC_PCIE_D_DTI_QTC_CLK 50 +#define GCC_PCIE_D_MSTR_AXI_CLK 51 +#define GCC_PCIE_D_PHY_AUX_CLK 52 +#define GCC_PCIE_D_PHY_AUX_CLK_SRC 53 +#define GCC_PCIE_D_PHY_RCHNG_CLK 54 +#define GCC_PCIE_D_PHY_RCHNG_CLK_SRC 55 +#define GCC_PCIE_D_PIPE_CLK 56 +#define GCC_PCIE_D_PIPE_CLK_SRC 57 +#define GCC_PCIE_D_SLV_AXI_CLK 58 +#define GCC_PCIE_D_SLV_Q2A_AXI_CLK 59 +#define GCC_PCIE_LINK_AHB_CLK 60 +#define GCC_PCIE_LINK_XO_CLK 61 +#define GCC_PCIE_NOC_ASYNC_BRIDGE_CLK 62 +#define GCC_PCIE_NOC_CNOC_SF_QX_CLK 63 +#define GCC_PCIE_NOC_M_CFG_CLK 64 +#define GCC_PCIE_NOC_M_PDB_CLK 65 +#define GCC_PCIE_NOC_MSTR_AXI_CLK 66 +#define GCC_PCIE_NOC_PWRCTL_CLK 67 +#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 68 +#define GCC_PCIE_NOC_REFGEN_CLK 69 +#define GCC_PCIE_NOC_REFGEN_CLK_SRC 70 +#define GCC_PCIE_NOC_S_CFG_CLK 71 +#define GCC_PCIE_NOC_S_PDB_CLK 72 +#define GCC_PCIE_NOC_SAFETY_CLK 73 +#define GCC_PCIE_NOC_SAFETY_CLK_SRC 74 +#define GCC_PCIE_NOC_SLAVE_AXI_CLK 75 +#define GCC_PCIE_NOC_TSCTR_CLK 76 +#define GCC_PCIE_NOC_XO_CLK 77 +#define GCC_PDM2_CLK 78 +#define GCC_PDM2_CLK_SRC 79 +#define GCC_PDM_AHB_CLK 80 +#define GCC_PDM_XO4_CLK 81 +#define GCC_QUPV3_WRAP3_CORE_2X_CLK 82 +#define GCC_QUPV3_WRAP3_CORE_CLK 83 +#define GCC_QUPV3_WRAP3_M_CLK 84 +#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 85 +#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 86 +#define GCC_QUPV3_WRAP3_S0_CLK 87 +#define GCC_QUPV3_WRAP3_S0_CLK_SRC 88 +#define GCC_QUPV3_WRAP3_S_AHB_CLK 89 +#define GCC_SMMU_PCIE_QTC_VOTE_CLK 90 + +/* GCC power domains */ +#define GCC_PCIE_A_GDSC 0 +#define GCC_PCIE_A_PHY_GDSC 1 +#define GCC_PCIE_B_GDSC 2 +#define GCC_PCIE_B_PHY_GDSC 3 +#define GCC_PCIE_C_GDSC 4 +#define GCC_PCIE_C_PHY_GDSC 5 +#define GCC_PCIE_D_GDSC 6 +#define GCC_PCIE_D_PHY_GDSC 7 +#define GCC_PCIE_NOC_GDSC 8 + +/* GCC resets */ +#define GCC_PCIE_A_BCR 0 +#define GCC_PCIE_A_LINK_DOWN_BCR 1 +#define GCC_PCIE_A_NOCSR_COM_PHY_BCR 2 +#define GCC_PCIE_A_PHY_BCR 3 +#define GCC_PCIE_A_PHY_CFG_AHB_BCR 4 +#define GCC_PCIE_A_PHY_COM_BCR 5 +#define GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_B_BCR 7 +#define GCC_PCIE_B_LINK_DOWN_BCR 8 +#define GCC_PCIE_B_NOCSR_COM_PHY_BCR 9 +#define GCC_PCIE_B_PHY_BCR 10 +#define GCC_PCIE_B_PHY_CFG_AHB_BCR 11 +#define GCC_PCIE_B_PHY_COM_BCR 12 +#define GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_C_BCR 14 +#define GCC_PCIE_C_LINK_DOWN_BCR 15 +#define GCC_PCIE_C_NOCSR_COM_PHY_BCR 16 +#define GCC_PCIE_C_PHY_BCR 17 +#define GCC_PCIE_C_PHY_CFG_AHB_BCR 18 +#define GCC_PCIE_C_PHY_COM_BCR 19 +#define GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR 20 +#define GCC_PCIE_D_BCR 21 +#define GCC_PCIE_D_LINK_DOWN_BCR 22 +#define GCC_PCIE_D_NOCSR_COM_PHY_BCR 23 +#define GCC_PCIE_D_PHY_BCR 24 +#define GCC_PCIE_D_PHY_CFG_AHB_BCR 25 +#define GCC_PCIE_D_PHY_COM_BCR 26 +#define GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR 27 +#define GCC_PCIE_NOC_BCR 28 +#define GCC_PDM_BCR 29 +#define GCC_QUPV3_WRAPPER_3_BCR 30 +#define GCC_TCSR_PCIE_BCR 31 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-gpucc.h b/include/dt-bindings/clock/qcom,nord-gpucc.h new file mode 100644 index 000000000000..a673e4854d66 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-gpucc.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_NORD_H + +/* GPU_CC clocks */ +#define GPU_CC_ACD_GFX3D_CLK 0 +#define GPU_CC_ACMU_CLK 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CRC_AHB_CLK 3 +#define GPU_CC_CX_ACCU_SHIFT_CLK 4 +#define GPU_CC_CX_FF_CLK 5 +#define GPU_CC_CX_GMU_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_DEMET_CLK 9 +#define GPU_CC_DPM_CLK 10 +#define GPU_CC_FF_CLK_SRC 11 +#define GPU_CC_FREQ_MEASURE_CLK 12 +#define GPU_CC_GMU_CLK_SRC 13 +#define GPU_CC_GPU_SMMU_VOTE_CLK 14 +#define GPU_CC_HUB_AON_CLK 15 +#define GPU_CC_HUB_CLK_SRC 16 +#define GPU_CC_HUB_CX_INT_CLK 17 +#define GPU_CC_HUB_DIV_CLK_SRC 18 +#define GPU_CC_MEMNOC_GFX_CLK 19 +#define GPU_CC_MND1X_GFX3D_CLK 20 +#define GPU_CC_MND1X_1_GFX3D_CLK 21 +#define GPU_CC_PLL0 22 +#define GPU_CC_PLL1 23 +#define GPU_CC_SLEEP_CLK 24 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_ACD_BCR 0 +#define GPU_CC_CB_BCR 1 +#define GPU_CC_CX_BCR 2 +#define GPU_CC_FAST_HUB_BCR 3 +#define GPU_CC_FF_BCR 4 +#define GPU_CC_GFX3D_AON_BCR 5 +#define GPU_CC_GMU_BCR 6 +#define GPU_CC_GX_BCR 7 +#define GPU_CC_XO_BCR 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-negcc.h b/include/dt-bindings/clock/qcom,nord-negcc.h new file mode 100644 index 000000000000..a7024317e90b --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-negcc.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H + +/* NE_GCC clocks */ +#define NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK 0 +#define NE_GCC_AGGRE_NOC_USB2_AXI_CLK 1 +#define NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK 2 +#define NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK 3 +#define NE_GCC_AHB2PHY_CLK 4 +#define NE_GCC_CNOC_USB2_AXI_CLK 5 +#define NE_GCC_CNOC_USB3_PRIM_AXI_CLK 6 +#define NE_GCC_CNOC_USB3_SEC_AXI_CLK 7 +#define NE_GCC_FRQ_MEASURE_REF_CLK 8 +#define NE_GCC_GP1_CLK 9 +#define NE_GCC_GP1_CLK_SRC 10 +#define NE_GCC_GP2_CLK 11 +#define NE_GCC_GP2_CLK_SRC 12 +#define NE_GCC_GPLL0 13 +#define NE_GCC_GPLL0_OUT_EVEN 14 +#define NE_GCC_GPLL2 15 +#define NE_GCC_GPU_2_CFG_CLK 16 +#define NE_GCC_GPU_2_GPLL0_CLK_SRC 17 +#define NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC 18 +#define NE_GCC_GPU_2_HSCNOC_GFX_CLK 19 +#define NE_GCC_GPU_2_SMMU_VOTE_CLK 20 +#define NE_GCC_QUPV3_WRAP2_CORE_2X_CLK 21 +#define NE_GCC_QUPV3_WRAP2_CORE_CLK 22 +#define NE_GCC_QUPV3_WRAP2_M_AHB_CLK 23 +#define NE_GCC_QUPV3_WRAP2_S0_CLK 24 +#define NE_GCC_QUPV3_WRAP2_S0_CLK_SRC 25 +#define NE_GCC_QUPV3_WRAP2_S1_CLK 26 +#define NE_GCC_QUPV3_WRAP2_S1_CLK_SRC 27 +#define NE_GCC_QUPV3_WRAP2_S2_CLK 28 +#define NE_GCC_QUPV3_WRAP2_S2_CLK_SRC 29 +#define NE_GCC_QUPV3_WRAP2_S3_CLK 30 +#define NE_GCC_QUPV3_WRAP2_S3_CLK_SRC 31 +#define NE_GCC_QUPV3_WRAP2_S4_CLK 32 +#define NE_GCC_QUPV3_WRAP2_S4_CLK_SRC 33 +#define NE_GCC_QUPV3_WRAP2_S5_CLK 34 +#define NE_GCC_QUPV3_WRAP2_S5_CLK_SRC 35 +#define NE_GCC_QUPV3_WRAP2_S6_CLK 36 +#define NE_GCC_QUPV3_WRAP2_S6_CLK_SRC 37 +#define NE_GCC_QUPV3_WRAP2_S_AHB_CLK 38 +#define NE_GCC_SDCC4_APPS_CLK 39 +#define NE_GCC_SDCC4_APPS_CLK_SRC 40 +#define NE_GCC_SDCC4_AXI_CLK 41 +#define NE_GCC_UFS_PHY_AHB_CLK 42 +#define NE_GCC_UFS_PHY_AXI_CLK 43 +#define NE_GCC_UFS_PHY_AXI_CLK_SRC 44 +#define NE_GCC_UFS_PHY_ICE_CORE_CLK 45 +#define NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC 46 +#define NE_GCC_UFS_PHY_PHY_AUX_CLK 47 +#define NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC 48 +#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK 49 +#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 50 +#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK 51 +#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 52 +#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK 53 +#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 54 +#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK 55 +#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 56 +#define NE_GCC_USB20_MASTER_CLK 57 +#define NE_GCC_USB20_MASTER_CLK_SRC 58 +#define NE_GCC_USB20_MOCK_UTMI_CLK 59 +#define NE_GCC_USB20_MOCK_UTMI_CLK_SRC 60 +#define NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 61 +#define NE_GCC_USB20_SLEEP_CLK 62 +#define NE_GCC_USB31_PRIM_ATB_CLK 63 +#define NE_GCC_USB31_PRIM_EUD_AHB_CLK 64 +#define NE_GCC_USB31_PRIM_MASTER_CLK 65 +#define NE_GCC_USB31_PRIM_MASTER_CLK_SRC 66 +#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK 67 +#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC 68 +#define NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 69 +#define NE_GCC_USB31_PRIM_SLEEP_CLK 70 +#define NE_GCC_USB31_SEC_ATB_CLK 71 +#define NE_GCC_USB31_SEC_EUD_AHB_CLK 72 +#define NE_GCC_USB31_SEC_MASTER_CLK 73 +#define NE_GCC_USB31_SEC_MASTER_CLK_SRC 74 +#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK 75 +#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC 76 +#define NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 77 +#define NE_GCC_USB31_SEC_SLEEP_CLK 78 +#define NE_GCC_USB3_PRIM_PHY_AUX_CLK 79 +#define NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC 80 +#define NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK 81 +#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK 82 +#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 83 +#define NE_GCC_USB3_SEC_PHY_AUX_CLK 84 +#define NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC 85 +#define NE_GCC_USB3_SEC_PHY_COM_AUX_CLK 86 +#define NE_GCC_USB3_SEC_PHY_PIPE_CLK 87 +#define NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC 88 + +/* NE_GCC power domains */ +#define NE_GCC_UFS_MEM_PHY_GDSC 0 +#define NE_GCC_UFS_PHY_GDSC 1 +#define NE_GCC_USB20_PRIM_GDSC 2 +#define NE_GCC_USB31_PRIM_GDSC 3 +#define NE_GCC_USB31_SEC_GDSC 4 +#define NE_GCC_USB3_PHY_GDSC 5 +#define NE_GCC_USB3_SEC_PHY_GDSC 6 + +/* NE_GCC resets */ +#define NE_GCC_GPU_2_BCR 0 +#define NE_GCC_QUPV3_WRAPPER_2_BCR 1 +#define NE_GCC_SDCC4_BCR 2 +#define NE_GCC_UFS_PHY_BCR 3 +#define NE_GCC_USB20_PRIM_BCR 4 +#define NE_GCC_USB31_PRIM_BCR 5 +#define NE_GCC_USB31_SEC_BCR 6 +#define NE_GCC_USB3_DP_PHY_PRIM_BCR 7 +#define NE_GCC_USB3_DP_PHY_SEC_BCR 8 +#define NE_GCC_USB3_PHY_PRIM_BCR 9 +#define NE_GCC_USB3_PHY_SEC_BCR 10 +#define NE_GCC_USB3PHY_PHY_PRIM_BCR 11 +#define NE_GCC_USB3PHY_PHY_SEC_BCR 12 +#define NE_GCC_QUSB2PHY_PRIM_BCR 13 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-nwgcc.h b/include/dt-bindings/clock/qcom,nord-nwgcc.h new file mode 100644 index 000000000000..b6253dd2aa85 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-nwgcc.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H + +/* NW_GCC clocks */ +#define NW_GCC_ACMU_MUX_CLK 0 +#define NW_GCC_CAMERA_AHB_CLK 1 +#define NW_GCC_CAMERA_HF_AXI_CLK 2 +#define NW_GCC_CAMERA_SF_AXI_CLK 3 +#define NW_GCC_CAMERA_TRIG_CLK 4 +#define NW_GCC_CAMERA_XO_CLK 5 +#define NW_GCC_DISP_0_AHB_CLK 6 +#define NW_GCC_DISP_0_HF_AXI_CLK 7 +#define NW_GCC_DISP_0_TRIG_CLK 8 +#define NW_GCC_DISP_1_AHB_CLK 9 +#define NW_GCC_DISP_1_HF_AXI_CLK 10 +#define NW_GCC_DISP_1_TRIG_CLK 11 +#define NW_GCC_DPRX0_AXI_HF_CLK 12 +#define NW_GCC_DPRX0_CFG_AHB_CLK 13 +#define NW_GCC_DPRX1_AXI_HF_CLK 14 +#define NW_GCC_DPRX1_CFG_AHB_CLK 15 +#define NW_GCC_EVA_AHB_CLK 16 +#define NW_GCC_EVA_AXI0_CLK 17 +#define NW_GCC_EVA_AXI0C_CLK 18 +#define NW_GCC_EVA_TRIG_CLK 19 +#define NW_GCC_EVA_XO_CLK 20 +#define NW_GCC_FRQ_MEASURE_REF_CLK 21 +#define NW_GCC_GP1_CLK 22 +#define NW_GCC_GP1_CLK_SRC 23 +#define NW_GCC_GP2_CLK 24 +#define NW_GCC_GP2_CLK_SRC 25 +#define NW_GCC_GPLL0 26 +#define NW_GCC_GPLL0_OUT_EVEN 27 +#define NW_GCC_GPU_2_CFG_AHB_CLK 28 +#define NW_GCC_GPU_2_GPLL0_CLK_SRC 29 +#define NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC 30 +#define NW_GCC_GPU_2_HSCNOC_GFX_CLK 31 +#define NW_GCC_GPU_CFG_AHB_CLK 32 +#define NW_GCC_GPU_GPLL0_CLK_SRC 33 +#define NW_GCC_GPU_GPLL0_DIV_CLK_SRC 34 +#define NW_GCC_GPU_HSCNOC_GFX_CLK 35 +#define NW_GCC_GPU_SMMU_VOTE_CLK 36 +#define NW_GCC_HSCNOC_GPU_2_AXI_CLK 37 +#define NW_GCC_HSCNOC_GPU_AXI_CLK 38 +#define NW_GCC_MMU_1_TCU_VOTE_CLK 39 +#define NW_GCC_VIDEO_AHB_CLK 40 +#define NW_GCC_VIDEO_AXI0_CLK 41 +#define NW_GCC_VIDEO_AXI0C_CLK 42 +#define NW_GCC_VIDEO_AXI1_CLK 43 +#define NW_GCC_VIDEO_XO_CLK 44 + +/* NW_GCC power domains */ + +/* NW_GCC resets */ +#define NW_GCC_CAMERA_BCR 0 +#define NW_GCC_DISPLAY_0_BCR 1 +#define NW_GCC_DISPLAY_1_BCR 2 +#define NW_GCC_DPRX0_BCR 3 +#define NW_GCC_DPRX1_BCR 4 +#define NW_GCC_EVA_BCR 5 +#define NW_GCC_GPU_2_BCR 6 +#define NW_GCC_GPU_BCR 7 +#define NW_GCC_VIDEO_BCR 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-segcc.h b/include/dt-bindings/clock/qcom,nord-segcc.h new file mode 100644 index 000000000000..f0f7422af692 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-segcc.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H + +/* SE_GCC clocks */ +#define SE_GCC_EEE_EMAC0_CLK 0 +#define SE_GCC_EEE_EMAC0_CLK_SRC 1 +#define SE_GCC_EEE_EMAC1_CLK 2 +#define SE_GCC_EEE_EMAC1_CLK_SRC 3 +#define SE_GCC_EMAC0_AXI_CLK 4 +#define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK 5 +#define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK 6 +#define SE_GCC_EMAC0_PHY_AUX_CLK 7 +#define SE_GCC_EMAC0_PHY_AUX_CLK_SRC 8 +#define SE_GCC_EMAC0_PTP_CLK 9 +#define SE_GCC_EMAC0_PTP_CLK_SRC 10 +#define SE_GCC_EMAC0_RGMII_CLK 11 +#define SE_GCC_EMAC0_RGMII_CLK_SRC 12 +#define SE_GCC_EMAC0_RPCS_RX_CLK 13 +#define SE_GCC_EMAC0_RPCS_TX_CLK 14 +#define SE_GCC_EMAC0_XGXS_RX_CLK 15 +#define SE_GCC_EMAC0_XGXS_TX_CLK 16 +#define SE_GCC_EMAC1_AXI_CLK 17 +#define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK 18 +#define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK 19 +#define SE_GCC_EMAC1_PHY_AUX_CLK 20 +#define SE_GCC_EMAC1_PHY_AUX_CLK_SRC 21 +#define SE_GCC_EMAC1_PTP_CLK 22 +#define SE_GCC_EMAC1_PTP_CLK_SRC 23 +#define SE_GCC_EMAC1_RGMII_CLK 24 +#define SE_GCC_EMAC1_RGMII_CLK_SRC 25 +#define SE_GCC_EMAC1_RPCS_RX_CLK 26 +#define SE_GCC_EMAC1_RPCS_TX_CLK 27 +#define SE_GCC_EMAC1_XGXS_RX_CLK 28 +#define SE_GCC_EMAC1_XGXS_TX_CLK 29 +#define SE_GCC_FRQ_MEASURE_REF_CLK 30 +#define SE_GCC_GP1_CLK 31 +#define SE_GCC_GP1_CLK_SRC 32 +#define SE_GCC_GP2_CLK 33 +#define SE_GCC_GP2_CLK_SRC 34 +#define SE_GCC_GPLL0 35 +#define SE_GCC_GPLL0_OUT_EVEN 36 +#define SE_GCC_GPLL2 37 +#define SE_GCC_GPLL4 38 +#define SE_GCC_GPLL5 39 +#define SE_GCC_MMU_2_TCU_VOTE_CLK 40 +#define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK 41 +#define SE_GCC_QUPV3_WRAP0_CORE_CLK 42 +#define SE_GCC_QUPV3_WRAP0_M_AHB_CLK 43 +#define SE_GCC_QUPV3_WRAP0_S0_CLK 44 +#define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC 45 +#define SE_GCC_QUPV3_WRAP0_S1_CLK 46 +#define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC 47 +#define SE_GCC_QUPV3_WRAP0_S2_CLK 48 +#define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC 49 +#define SE_GCC_QUPV3_WRAP0_S3_CLK 50 +#define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC 51 +#define SE_GCC_QUPV3_WRAP0_S4_CLK 52 +#define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC 53 +#define SE_GCC_QUPV3_WRAP0_S5_CLK 54 +#define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC 55 +#define SE_GCC_QUPV3_WRAP0_S6_CLK 56 +#define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC 57 +#define SE_GCC_QUPV3_WRAP0_S_AHB_CLK 58 +#define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK 59 +#define SE_GCC_QUPV3_WRAP1_CORE_CLK 60 +#define SE_GCC_QUPV3_WRAP1_M_AHB_CLK 61 +#define SE_GCC_QUPV3_WRAP1_S0_CLK 62 +#define SE_GCC_QUPV3_WRAP1_S0_CLK_SRC 63 +#define SE_GCC_QUPV3_WRAP1_S1_CLK 64 +#define SE_GCC_QUPV3_WRAP1_S1_CLK_SRC 65 +#define SE_GCC_QUPV3_WRAP1_S2_CLK 66 +#define SE_GCC_QUPV3_WRAP1_S2_CLK_SRC 67 +#define SE_GCC_QUPV3_WRAP1_S3_CLK 68 +#define SE_GCC_QUPV3_WRAP1_S3_CLK_SRC 69 +#define SE_GCC_QUPV3_WRAP1_S4_CLK 70 +#define SE_GCC_QUPV3_WRAP1_S4_CLK_SRC 71 +#define SE_GCC_QUPV3_WRAP1_S5_CLK 72 +#define SE_GCC_QUPV3_WRAP1_S5_CLK_SRC 73 +#define SE_GCC_QUPV3_WRAP1_S6_CLK 74 +#define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC 75 +#define SE_GCC_QUPV3_WRAP1_S_AHB_CLK 76 + +/* SE_GCC power domains */ +#define SE_GCC_EMAC0_GDSC 0 +#define SE_GCC_EMAC1_GDSC 1 + +/* SE_GCC resets */ +#define SE_GCC_EMAC0_BCR 0 +#define SE_GCC_EMAC1_BCR 1 +#define SE_GCC_QUPV3_WRAPPER_0_BCR 2 +#define SE_GCC_QUPV3_WRAPPER_1_BCR 3 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-tcsrcc.h b/include/dt-bindings/clock/qcom,nord-tcsrcc.h new file mode 100644 index 000000000000..3f0e2ff7acc7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-tcsrcc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H + +/* TCSR_CC clocks */ +#define TCSR_DP_RX_0_CLKREF_EN 0 +#define TCSR_DP_RX_1_CLKREF_EN 1 +#define TCSR_DP_TX_0_CLKREF_EN 2 +#define TCSR_DP_TX_1_CLKREF_EN 3 +#define TCSR_DP_TX_2_CLKREF_EN 4 +#define TCSR_DP_TX_3_CLKREF_EN 5 +#define TCSR_PCIE_CLKREF_EN 6 +#define TCSR_UFS_CLKREF_EN 7 +#define TCSR_USB2_0_CLKREF_EN 8 +#define TCSR_USB2_1_CLKREF_EN 9 +#define TCSR_USB2_2_CLKREF_EN 10 +#define TCSR_USB3_0_CLKREF_EN 11 +#define TCSR_USB3_1_CLKREF_EN 12 +#define TCSR_UX_SGMII_0_CLKREF_EN 13 +#define TCSR_UX_SGMII_1_CLKREF_EN 14 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-videocc.h b/include/dt-bindings/clock/qcom,nord-videocc.h new file mode 100644 index 000000000000..8d7546021109 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-videocc.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_NORD_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK_SRC 0 +#define VIDEO_CC_MVS0_CLK 1 +#define VIDEO_CC_MVS0_CLK_SRC 2 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 3 +#define VIDEO_CC_MVS0_FREERUN_CLK 4 +#define VIDEO_CC_MVS0_SHIFT_CLK 5 +#define VIDEO_CC_MVS0C_CLK 6 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 7 +#define VIDEO_CC_MVS0C_FREERUN_CLK 8 +#define VIDEO_CC_MVS0C_SHIFT_CLK 9 +#define VIDEO_CC_MVS1_CLK 10 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 11 +#define VIDEO_CC_MVS1_FREERUN_CLK 12 +#define VIDEO_CC_MVS1_SHIFT_CLK 13 +#define VIDEO_CC_PLL0 14 +#define VIDEO_CC_SLEEP_CLK_SRC 15 +#define VIDEO_CC_XO_CLK_SRC 16 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0C_GDSC 1 +#define VIDEO_CC_MVS1_GDSC 2 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_MVS0C_BCR 3 +#define VIDEO_CC_MVS1_BCR 4 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,nord-rpmh.h b/include/dt-bindings/interconnect/qcom,nord-rpmh.h new file mode 100644 index 000000000000..5bdce6a9bab7 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,nord-rpmh.h @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_NORD_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_NORD_H + +#define MASTER_QSPI_0 0 +#define MASTER_SAILSS_MD1 1 +#define MASTER_QUP_3 2 +#define SLAVE_A1NOC_SNOC 3 + +#define MASTER_QUP_2 0 +#define MASTER_CRYPTO_CORE0 1 +#define MASTER_CRYPTO_CORE1 2 +#define MASTER_CRYPTO_CORE2 3 +#define MASTER_SDCC_4 4 +#define MASTER_UFS_MEM 5 +#define MASTER_USB2 6 +#define MASTER_USB3_0 7 +#define MASTER_USB3_1 8 +#define SLAVE_A1NOC_HSCNOC 9 + +#define MASTER_IPA 0 +#define MASTER_SOCCP_AGGR_NOC 1 +#define MASTER_QDSS_ETR 2 +#define MASTER_QDSS_ETR_1 3 +#define SLAVE_A2NOC_SNOC 4 + +#define MASTER_QUP_0 0 +#define MASTER_QUP_1 1 +#define MASTER_EMAC_0 2 +#define MASTER_EMAC_1 3 +#define SLAVE_A2NOC_HSCNOC 4 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define MASTER_QUP_CORE_3 3 +#define SLAVE_QUP_CORE_0 4 +#define SLAVE_QUP_CORE_1 5 +#define SLAVE_QUP_CORE_2 6 +#define SLAVE_QUP_CORE_3 7 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_PS_ETH_0 1 +#define SLAVE_PS_ETH_1 2 +#define SLAVE_SHS_SERVER 3 +#define SLAVE_AHB2PHY_0 4 +#define SLAVE_AHB2PHY_1 5 +#define SLAVE_AHB2PHY_2 6 +#define SLAVE_AHB2PHY_3 7 +#define SLAVE_AHB2PHY_ETH_0 8 +#define SLAVE_AHB2PHY_ETH_1 9 +#define SLAVE_CAMERA_CFG 10 +#define SLAVE_CLK_CTL 11 +#define SLAVE_CRYPTO_0_CFG 12 +#define SLAVE_CRYPTO_1_CFG 13 +#define SLAVE_CRYPTO_2_CFG 14 +#define SLAVE_DISPLAY_1_CFG 15 +#define SLAVE_DISPLAY_CFG 16 +#define SLAVE_DPRX0 17 +#define SLAVE_DPRX1 18 +#define SLAVE_EVA_CFG 19 +#define SLAVE_GFX3D_CFG 20 +#define SLAVE_GFX3D_1_CFG 21 +#define SLAVE_I2C 22 +#define SLAVE_IMEM_CFG 23 +#define SLAVE_MCW_PCIE 24 +#define SLAVE_MM_RSCC 25 +#define SLAVE_NE_CLK_CTL 26 +#define SLAVE_NSPSS0_CFG 27 +#define SLAVE_NSPSS1_CFG 28 +#define SLAVE_NSPSS2_CFG 29 +#define SLAVE_NSPSS3_CFG 30 +#define SLAVE_NW_CLK_CTL 31 +#define SLAVE_PRNG 32 +#define SLAVE_QDSS_CFG 33 +#define SLAVE_QSPI_0 34 +#define SLAVE_QUP_0 35 +#define SLAVE_QUP_3 36 +#define SLAVE_QUP_1 37 +#define SLAVE_QUP_2 38 +#define SLAVE_SAFEDMA_CFG 39 +#define SLAVE_SDCC_4 40 +#define SLAVE_SE_CLK_CTL 41 +#define SLAVE_TCSR 42 +#define SLAVE_TLMM 43 +#define SLAVE_TSC_CFG 44 +#define SLAVE_UFS_MEM_CFG 45 +#define SLAVE_USB2 46 +#define SLAVE_USB3_0 47 +#define SLAVE_USB3_1 48 +#define SLAVE_VENUS_CFG 49 +#define SLAVE_COMPUTENOC_CFG 50 +#define SLAVE_PCIE_NOC_CFG 51 +#define SLAVE_QTC_CFG 52 +#define SLAVE_QDSS_STM 53 +#define SLAVE_SYS_TCU0_CFG 54 +#define SLAVE_SYS_TCU1_CFG 55 +#define SLAVE_SYS_TCU2_CFG 56 + +#define MASTER_MM_RSCC 0 +#define MASTER_HSCNOC_CNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_HBCU 3 +#define SLAVE_IPA_CFG 4 +#define SLAVE_IPC_ROUTER_CFG 5 +#define SLAVE_SOCCP 6 +#define SLAVE_TME_CFG 7 +#define SLAVE_PCIE_DMA 8 +#define SLAVE_CNOC_CFG 9 +#define SLAVE_DDRSS_CFG 10 +#define SLAVE_IMEM 11 + +#define MASTER_HPASS_PROC_0 0 +#define MASTER_HPASS_PROC_1 1 +#define MASTER_HPASS_PROC_2 2 +#define SLAVE_HPASS_AGNOC_AUDIO 3 + +#define MASTER_GPU_TCU 0 +#define MASTER_QTC_TCU 1 +#define MASTER_SYS_TCU_0 2 +#define MASTER_SYS_TCU_1 3 +#define MASTER_SYS_TCU_2 4 +#define MASTER_APPSS_PROC 5 +#define MASTER_A1NOC_TILE_HSCNOC 6 +#define MASTER_A2NOC_TILE_HSCNOC 7 +#define MASTER_GFX3D 8 +#define MASTER_GFX3D_1 9 +#define MASTER_HPASS_ADAS_HSCNOC 10 +#define MASTER_HPASS_AUDIO_HSCNOC 11 +#define MASTER_MNOC_HF_MEM_NOC 12 +#define MASTER_MNOC_SF_MEM_NOC 13 +#define MASTER_NSP0_HSCNOC 14 +#define MASTER_NSP1_HSCNOC 15 +#define MASTER_NSP2_HSCNOC 16 +#define MASTER_NSP3_HSCNOC 17 +#define MASTER_ANOC_PCIE_GEM_NOC 18 +#define MASTER_SAILSS_MD0_HSCNOC 19 +#define MASTER_SNOC_SF_MEM_NOC 20 +#define MASTER_GIC 21 +#define SLAVE_HSCNOC_CNOC 22 +#define SLAVE_LLCC 23 +#define SLAVE_MEM_NOC_PCIE_SNOC 24 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_NRT_ICP_SF 1 +#define MASTER_CAMNOC_RT_CDM_SF 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_DPRX0 4 +#define MASTER_DPRX1 5 +#define MASTER_MDP0 6 +#define MASTER_MDP1 7 +#define MASTER_VIDEO_CV_PROC 8 +#define MASTER_VIDEO_EVA 9 +#define MASTER_VIDEO_MVP0 10 +#define MASTER_VIDEO_MVP1 11 +#define MASTER_VIDEO_V_PROC 12 +#define SLAVE_MNOC_HF_MEM_NOC 13 +#define SLAVE_MNOC_SF_MEM_NOC 14 + +#define MASTER_NSP0_PROC 0 +#define SLAVE_NSP0_HSC_NOC 1 + +#define MASTER_NSP1_PROC 0 +#define SLAVE_NSP1_HSC_NOC 1 + +#define MASTER_NSP2_PROC 0 +#define SLAVE_NSP2_HSC_NOC 1 + +#define MASTER_NSP3_PROC 0 +#define SLAVE_NSP3_HSC_NOC 1 + +#define MASTER_PCIE_NOC_CFG 0 +#define SLAVE_PCIE_AHB2PHY_CFG 1 +#define SLAVE_PCIE_CFG_0 2 +#define SLAVE_PCIE_CFG_1 3 +#define SLAVE_PCIE_CFG_2 4 +#define SLAVE_PCIE_CFG_3 5 +#define SLAVE_PCIE_DMA_0_CFG 6 +#define SLAVE_PCIE_DMA_1_CFG 7 +#define SLAVE_PCIE_DMA_2_CFG 8 + +#define MASTER_PCIE_DMA_0 0 +#define MASTER_PCIE_DMA_1 1 +#define MASTER_PCIE_DMA_2 2 +#define MASTER_PCIE_0 3 +#define MASTER_PCIE_1 4 +#define MASTER_PCIE_2 5 +#define MASTER_PCIE_3 6 +#define SLAVE_PCIE_HSCNOC 7 +#define SLAVE_PCIE_OBNOC_DMA 8 + +#define MASTER_CNOC_PCIE_DMA 0 +#define MASTER_ANOC_PCIE_HSCNOC 1 +#define MASTER_PCIE_IBNOC_DMA 2 +#define SLAVE_PCIE_DMA_0 3 +#define SLAVE_PCIE_DMA_1 4 +#define SLAVE_PCIE_DMA_2 5 +#define SLAVE_PCIE_0 6 +#define SLAVE_PCIE_1 7 +#define SLAVE_PCIE_2 8 +#define SLAVE_PCIE_3 9 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_CNOC_SNOC 2 +#define MASTER_NSINOC_SNOC 3 +#define MASTER_SAFE_DMA 4 +#define SLAVE_SNOC_HSCNOC_SF 5 + +#endif diff --git a/include/scsi.h b/include/scsi.h index 83aaf0a70f63..4355aef5f6b7 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -353,6 +353,14 @@ int scsi_scan(bool verbose); */ int scsi_scan_dev(struct udevice *dev, bool verbose); +/** + * scsi_scan_new() - Scan all SCSI controllers for new devices + * + * @verbose: true to show information about each device found + * Return: 0 if OK, -ve on error + */ +int scsi_scan_new(bool verbose); + /** * scsi_get_blk_by_uuid() - Provides SCSI partition information. *