From e67e919d1f6221ea8beeb2cb5d8178f596b0ae94 Mon Sep 17 00:00:00 2001 From: Aniket Datta Date: Mon, 16 Feb 2026 06:21:12 +0000 Subject: [PATCH 1/6] Drove the outputs of the lint_stubs --- lint_stubs/BUFG_GT.sv | 2 + lint_stubs/GTXE2_COMMON.sv | 10 ++ lint_stubs/qeciphy_clk_mmcm.sv | 4 + lint_stubs/qeciphy_gth_transceiver.sv | 22 ++++ lint_stubs/qeciphy_gtx_transceiver.sv | 143 +++++++++++++++----------- lint_stubs/qeciphy_gty_transceiver.sv | 22 ++++ 6 files changed, 144 insertions(+), 59 deletions(-) diff --git a/lint_stubs/BUFG_GT.sv b/lint_stubs/BUFG_GT.sv index 3513072..441047c 100644 --- a/lint_stubs/BUFG_GT.sv +++ b/lint_stubs/BUFG_GT.sv @@ -20,4 +20,6 @@ module BUFG_GT ( output O ); + assign O = '0; + endmodule diff --git a/lint_stubs/GTXE2_COMMON.sv b/lint_stubs/GTXE2_COMMON.sv index 7804f69..e156429 100644 --- a/lint_stubs/GTXE2_COMMON.sv +++ b/lint_stubs/GTXE2_COMMON.sv @@ -68,4 +68,14 @@ module GTXE2_COMMON #( input logic RCALENB ); + assign DRPDO = '0; + assign DRPRDY = '0; + assign QPLLDMONITOR = '0; + assign QPLLOUTCLK = '0; + assign QPLLOUTREFCLK = '0; + assign REFCLKOUTMONITOR = '0; + assign QPLLFBCLKLOST = '0; + assign QPLLLOCK = '0; + assign QPLLREFCLKLOST = '0; + endmodule diff --git a/lint_stubs/qeciphy_clk_mmcm.sv b/lint_stubs/qeciphy_clk_mmcm.sv index e894bfa..3abc440 100644 --- a/lint_stubs/qeciphy_clk_mmcm.sv +++ b/lint_stubs/qeciphy_clk_mmcm.sv @@ -18,4 +18,8 @@ module qeciphy_clk_mmcm ( input clk_in ); + assign clk_out_2x = '0; + assign clk_out = '0; + assign input_clk_stopped = '0; + endmodule diff --git a/lint_stubs/qeciphy_gth_transceiver.sv b/lint_stubs/qeciphy_gth_transceiver.sv index 395e8a2..d48cd2a 100644 --- a/lint_stubs/qeciphy_gth_transceiver.sv +++ b/lint_stubs/qeciphy_gth_transceiver.sv @@ -58,4 +58,26 @@ module qeciphy_gth_transceiver ( output rxcommadet_out ); + assign gtwiz_reset_rx_cdr_stable_out = '0; + assign gtwiz_reset_tx_done_out = '0; + assign gtwiz_reset_rx_done_out = '0; + assign gtwiz_userdata_rx_out = '0; + assign qpll0outclk_out = '0; + assign qpll0lock_out = '0; + assign qpll0outrefclk_out = '0; + assign gtpowergood_out = '0; + assign gthtxn_out = '0; + assign gthtxp_out = '0; + assign rxctrl0_out = '0; + assign rxctrl1_out = '0; + assign rxctrl2_out = '0; + assign rxctrl3_out = '0; + assign rxoutclk_out = '0; + assign rxpmaresetdone_out = '0; + assign txoutclk_out = '0; + assign txpmaresetdone_out = '0; + assign rxbyteisaligned_out = '0; + assign rxbyterealign_out = '0; + assign rxcommadet_out = '0; + endmodule diff --git a/lint_stubs/qeciphy_gtx_transceiver.sv b/lint_stubs/qeciphy_gtx_transceiver.sv index 2c417c8..a33566a 100644 --- a/lint_stubs/qeciphy_gtx_transceiver.sv +++ b/lint_stubs/qeciphy_gtx_transceiver.sv @@ -11,65 +11,90 @@ // ----------------------------------------------------------------------------- module qeciphy_gtx_transceiver ( - input sysclk_in, - input soft_reset_tx_in, - input soft_reset_rx_in, - input dont_reset_on_data_error_in, - output gt0_tx_fsm_reset_done_out, - output gt0_rx_fsm_reset_done_out, - input gt0_data_valid_in, - input [ 8:0] gt0_drpaddr_in, - input gt0_drpclk_in, - input [15:0] gt0_drpdi_in, - output [15:0] gt0_drpdo_out, - input gt0_drpen_in, - output gt0_drprdy_out, - input gt0_drpwe_in, - output [ 7:0] gt0_dmonitorout_out, - input [ 2:0] gt0_loopback_in, - input gt0_eyescanreset_in, - input gt0_rxuserrdy_in, - output gt0_eyescandataerror_out, - input gt0_eyescantrigger_in, - input gt0_rxusrclk_in, - input gt0_rxusrclk2_in, - output [31:0] gt0_rxdata_out, - output [ 3:0] gt0_rxdisperr_out, - output [ 3:0] gt0_rxnotintable_out, - input gt0_gtxrxp_in, - input gt0_gtxrxn_in, - input gt0_rxdfelpmreset_in, - output [ 6:0] gt0_rxmonitorout_out, - input [ 1:0] gt0_rxmonitorsel_in, - output gt0_rxoutclk_out, - output gt0_rxoutclkfabric_out, - input gt0_gtrxreset_in, - input gt0_rxpmareset_in, - output [ 3:0] gt0_rxcharisk_out, - output gt0_rxresetdone_out, - input gt0_gttxreset_in, - input gt0_txuserrdy_in, - input gt0_txusrclk_in, - input gt0_txusrclk2_in, - input [31:0] gt0_txdata_in, - output gt0_gtxtxn_out, - output gt0_gtxtxp_out, - output gt0_txoutclk_out, - output gt0_txoutclkfabric_out, - output gt0_txoutclkpcs_out, - input [ 3:0] gt0_txcharisk_in, - input gt0_txpmareset_in, - output gt0_txresetdone_out, - input gt0_qplllock_in, - input gt0_qpllrefclklost_in, - output gt0_qpllreset_out, - input gt0_qplloutclk_in, - input gt0_qplloutrefclk_in, - input gt0_rxpcommaalignen_in, - input gt0_rxmcommaalignen_in, - output gt0_rxbyteisaligned_out, - output gt0_rxbyterealign_out, - output gt0_rxcommadet_out + input wire sysclk_in, + input wire soft_reset_tx_in, + input wire soft_reset_rx_in, + input wire dont_reset_on_data_error_in, + output wire gt0_tx_fsm_reset_done_out, + output wire gt0_rx_fsm_reset_done_out, + input wire gt0_data_valid_in, + input wire [ 8:0] gt0_drpaddr_in, + input wire gt0_drpclk_in, + input wire [15:0] gt0_drpdi_in, + output wire [15:0] gt0_drpdo_out, + input wire gt0_drpen_in, + output wire gt0_drprdy_out, + input wire gt0_drpwe_in, + output wire [ 7:0] gt0_dmonitorout_out, + input wire [ 2:0] gt0_loopback_in, + input wire gt0_eyescanreset_in, + input wire gt0_rxuserrdy_in, + output wire gt0_eyescandataerror_out, + input wire gt0_eyescantrigger_in, + input wire gt0_rxusrclk_in, + input wire gt0_rxusrclk2_in, + output wire [31:0] gt0_rxdata_out, + output wire [ 3:0] gt0_rxdisperr_out, + output wire [ 3:0] gt0_rxnotintable_out, + input wire gt0_gtxrxp_in, + input wire gt0_gtxrxn_in, + input wire gt0_rxdfelpmreset_in, + output wire [ 6:0] gt0_rxmonitorout_out, + input wire [ 1:0] gt0_rxmonitorsel_in, + output wire gt0_rxoutclk_out, + output wire gt0_rxoutclkfabric_out, + input wire gt0_gtrxreset_in, + input wire gt0_rxpmareset_in, + output wire [ 3:0] gt0_rxcharisk_out, + output wire gt0_rxresetdone_out, + input wire gt0_gttxreset_in, + input wire gt0_txuserrdy_in, + input wire gt0_txusrclk_in, + input wire gt0_txusrclk2_in, + input wire [31:0] gt0_txdata_in, + output wire gt0_gtxtxn_out, + output wire gt0_gtxtxp_out, + output wire gt0_txoutclk_out, + output wire gt0_txoutclkfabric_out, + output wire gt0_txoutclkpcs_out, + input wire [ 3:0] gt0_txcharisk_in, + input wire gt0_txpmareset_in, + output wire gt0_txresetdone_out, + input wire gt0_qplllock_in, + input wire gt0_qpllrefclklost_in, + output wire gt0_qpllreset_out, + input wire gt0_qplloutclk_in, + input wire gt0_qplloutrefclk_in, + input wire gt0_rxpcommaalignen_in, + input wire gt0_rxmcommaalignen_in, + output wire gt0_rxbyteisaligned_out, + output wire gt0_rxbyterealign_out, + output wire gt0_rxcommadet_out ); + assign gt0_tx_fsm_reset_done_out = '0; + assign gt0_rx_fsm_reset_done_out = '0; + assign gt0_drpdo_out = '0; + assign gt0_drprdy_out = '0; + assign gt0_dmonitorout_out = '0; + assign gt0_eyescandataerror_out = '0; + assign gt0_rxdata_out = '0; + assign gt0_rxdisperr_out = '0; + assign gt0_rxnotintable_out = '0; + assign gt0_rxmonitorout_out = '0; + assign gt0_rxoutclk_out = '0; + assign gt0_rxoutclkfabric_out = '0; + assign gt0_rxcharisk_out = '0; + assign gt0_rxresetdone_out = '0; + assign gt0_gtxtxn_out = '0; + assign gt0_gtxtxp_out = '0; + assign gt0_txoutclk_out = '0; + assign gt0_txoutclkfabric_out = '0; + assign gt0_txoutclkpcs_out = '0; + assign gt0_txresetdone_out = '0; + assign gt0_qpllreset_out = '0; + assign gt0_rxbyteisaligned_out = '0; + assign gt0_rxbyterealign_out = '0; + assign gt0_rxcommadet_out = '0; + endmodule diff --git a/lint_stubs/qeciphy_gty_transceiver.sv b/lint_stubs/qeciphy_gty_transceiver.sv index 42c2312..9594573 100644 --- a/lint_stubs/qeciphy_gty_transceiver.sv +++ b/lint_stubs/qeciphy_gty_transceiver.sv @@ -58,4 +58,26 @@ module qeciphy_gty_transceiver ( output rxcommadet_out ); + assign gtwiz_reset_rx_cdr_stable_out = '0; + assign gtwiz_reset_tx_done_out = '0; + assign gtwiz_reset_rx_done_out = '0; + assign gtwiz_userdata_rx_out = '0; + assign qpll0outclk_out = '0; + assign qpll0lock_out = '0; + assign qpll0outrefclk_out = '0; + assign gtpowergood_out = '0; + assign gtytxn_out = '0; + assign gtytxp_out = '0; + assign rxctrl0_out = '0; + assign rxctrl1_out = '0; + assign rxctrl2_out = '0; + assign rxctrl3_out = '0; + assign rxoutclk_out = '0; + assign rxpmaresetdone_out = '0; + assign txoutclk_out = '0; + assign txpmaresetdone_out = '0; + assign rxbyteisaligned_out = '0; + assign rxbyterealign_out = '0; + assign rxcommadet_out = '0; + endmodule From 65976011a267055cad7f531fa0f0889816259d2b Mon Sep 17 00:00:00 2001 From: Aniket Datta Date: Mon, 16 Feb 2026 06:30:11 +0000 Subject: [PATCH 2/6] Updated 2FF synchronizer to support both sync and async resets --- .../src/riv_synchronizer_2ff.sv | 28 ++++++++++++++----- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/lib/riv_synchronizer_2ff/src/riv_synchronizer_2ff.sv b/lib/riv_synchronizer_2ff/src/riv_synchronizer_2ff.sv index 3c7359a..2b10ff2 100644 --- a/lib/riv_synchronizer_2ff/src/riv_synchronizer_2ff.sv +++ b/lib/riv_synchronizer_2ff/src/riv_synchronizer_2ff.sv @@ -5,7 +5,9 @@ `ifndef RIV_SYNCHRONIZER_2FF_SV `define RIV_SYNCHRONIZER_2FF_SV -module riv_synchronizer_2ff ( +module riv_synchronizer_2ff #( + parameter string RESET_TYPE = "SYNC" +) ( input logic src_in, // signal to be synchronised input logic dst_clk, // destination clock domain input logic dst_rst_n, // destination domain active low reset @@ -21,13 +23,25 @@ module riv_synchronizer_2ff ( // Logic // ------------------------------------------------------------- - always_ff @(posedge dst_clk or negedge dst_rst_n) begin - if (~dst_rst_n) begin - sync_stage_sf <= 2'h0; - end else begin - sync_stage_sf <= {sync_stage_sf[0], src_in}; + generate + if (RESET_TYPE == "ASYNC") begin : gen_synchronizer_with_async_reset + always_ff @(posedge dst_clk or negedge dst_rst_n) begin + if (!dst_rst_n) begin + sync_stage_sf <= 2'h0; + end else begin + sync_stage_sf <= {sync_stage_sf[0], src_in}; + end + end + end else begin : gen_synchronizer_with_sync_reset + always_ff @(posedge dst_clk) begin + if (!dst_rst_n) begin + sync_stage_sf <= 2'h0; + end else begin + sync_stage_sf <= {sync_stage_sf[0], src_in}; + end + end end - end + endgenerate assign dst_out = sync_stage_sf[1]; From 83534475f5e61b52f6e690b3b63024e1f19aae4e Mon Sep 17 00:00:00 2001 From: Aniket Datta Date: Mon, 16 Feb 2026 06:31:23 +0000 Subject: [PATCH 3/6] Made linting stricter checking against all warnings --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5b25c6d..6361127 100644 --- a/Makefile +++ b/Makefile @@ -281,7 +281,7 @@ distclean: clean verilator_lint: @$(MAKE) check_verilator - @verilator --lint-only -sv -Isrc $(LINT_FILES) lint_waivers.vlt --top QECIPHY + @verilator --lint-only -sv -Wall lint_waivers.vlt -Isrc $(LINT_FILES) --top QECIPHY verible_format: @$(MAKE) check_verible From 5c9b8b07b8fc272fd6d8d1b1bb957624beb4b517 Mon Sep 17 00:00:00 2001 From: Aniket Datta Date: Mon, 16 Feb 2026 07:04:49 +0000 Subject: [PATCH 4/6] Cleaned up linting --- lint_waivers.vlt | 70 +++++++++------- src/QECIPHY.sv | 14 ++-- src/qeciphy_controller.sv | 8 +- src/qeciphy_crc_check.sv | 20 ++--- src/qeciphy_error_handler.sv | 14 ++-- src/qeciphy_gt_wrapper.sv | 148 ++++++++++++++++++--------------- src/qeciphy_resetcontroller.sv | 51 ++++++++---- src/qeciphy_rx_32b_to_64b.sv | 6 +- src/qeciphy_rx_boundary_gen.sv | 4 +- src/qeciphy_rx_comma_detect.sv | 5 -- src/qeciphy_rx_controller.sv | 12 ++- src/qeciphy_rx_monitor.sv | 38 ++++----- src/qeciphy_serdes.sv | 2 +- src/qeciphy_tx_packet_gen.sv | 51 ++++++------ 14 files changed, 234 insertions(+), 209 deletions(-) diff --git a/lint_waivers.vlt b/lint_waivers.vlt index 8c2ee78..df3b6fe 100644 --- a/lint_waivers.vlt +++ b/lint_waivers.vlt @@ -1,59 +1,73 @@ `verilator_config +// These signals are intentionally brought to the modules to help future expansion even if they are currently unconnected +lint_off -rule UNUSEDSIGNAL -file "*qeciphy_cdc.sv" -match "Signal is not used: 'f_clk_i'" +lint_off -rule UNUSEDSIGNAL -file "*qeciphy_cdc.sv" -match "Signal is not used: 'f_rst_n_i'" +lint_off -rule UNUSEDSIGNAL -file "*qeciphy_tx_packet_gen.sv" -match "Signal is not used: 'tx_off_i'" +lint_off -rule UNUSEDSIGNAL -file "*qeciphy_serdes.sv" -match "Signal is not used: 'rx_datapath_rst_n_i'" + +// Only checking remote_rx_rdy (bit 63) in this module +lint_off -rule UNUSEDSIGNAL -file "*qeciphy_rx_monitor.sv" -match "Bits of signal are not used: 'faw'[62:0]" + +// Diagnostic signals kept in place although not used +lint_off -rule UNUSEDSIGNAL -file "*qeciphy_gt_wrapper.sv" -match "Signal is not used: 'rxbyteisaligned'" +lint_off -rule UNUSEDSIGNAL -file "*qeciphy_gt_wrapper.sv" -match "Signal is not used: 'rxcommadet'" +lint_off -rule UNUSEDSIGNAL -file "*qeciphy_gt_wrapper.sv" -match "Signal is not used: 'cdr_stable'" + +// Currently unused as crc45_valid and crcvw_valid coincides, only one of them is used +lint_off -rule UNUSEDSIGNAL -file "*qeciphy_crc_compute.sv" -match "Signal is not used: 'crc45_valid'" + +// Bits [15:8] in the validation word are not needed for CRC checking +lint_off -rule UNUSEDSIGNAL -file "*qeciphy_crc_check.sv" -match "Bits of signal are not used: 'vd_pkt'[15:8]" + // These output pins were intentionally left unconnected + +// Async FIFO +lint_off -rule PINCONNECTEMPTY -file "*QECIPHY.sv" -match "Cell pin connected by name with empty reference: 'underflow'" +lint_off -rule PINCONNECTEMPTY -file "*QECIPHY.sv" -match "Cell pin connected by name with empty reference: 'rwcount'" +lint_off -rule PINCONNECTEMPTY -file "*QECIPHY.sv" -match "Cell pin connected by name with empty reference: 'full'" +lint_off -rule PINCONNECTEMPTY -file "*QECIPHY.sv" -match "Cell pin connected by name with empty reference: 'wwcount'" + +// GTY / GTH transceivers +lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'qpll0lock_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'qpll0outclk_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'qpll0outrefclk_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'rxctrl0_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'rxctrl1_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'rxctrl2_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'rxctrl3_out'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gtwiz_reset_rx_cdr_stable_out'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'qpll0lock_out'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gtyrxn_in'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gtyrxp_in'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gtytxn_out'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gtytxp_out'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gthrxn_in'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gthrxp_in'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gthtxn_out'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gthtxp_out'" + +// GTX transceiver lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_drpdo_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_drprdy_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_dmonitorout_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_eyescandataerror_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_rxdisperr_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_rxnotintable_out'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_gtxrxp_in'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_gtxrxn_in'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_rxmonitorout_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_rxoutclkfabric_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_rxcharisk_out'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_gtxtxn_out'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_gtxtxp_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_txoutclkfabric_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_txoutclkpcs_out'" -lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_rxresetdone_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gt_wrapper.sv" -match "Cell pin connected by name with empty reference: 'gt0_txresetdone_out'" lint_off -rule PINCONNECTEMPTY -file "*qeciphy_gtx_common.sv" -match "Cell pin connected by name with empty reference: *" // Ignore linting errors for lint stub files -lint_off -rule UNUSEDSIGNAL -file "*/lint_stubs/BUFG_GT.sv" -lint_off -rule UNDRIVEN -file "*/lint_stubs/BUFG_GT.sv" +lint_off -rule UNUSEDSIGNAL -file "*lint_stubs/BUFG_GT.sv" + +lint_off -rule UNUSEDPARAM -file "*lint_stubs/GTXE2_COMMON.sv" +lint_off -rule UNUSEDSIGNAL -file "*lint_stubs/GTXE2_COMMON.sv" + +lint_off -rule UNUSEDSIGNAL -file "*lint_stubs/qeciphy_clk_mmcm.sv" -lint_off -rule UNUSEDPARAM -file "*/lint_stubs/GTXE2_COMMON.sv" -lint_off -rule UNUSEDSIGNAL -file "*/lint_stubs/GTXE2_COMMON.sv" -lint_off -rule UNDRIVEN -file "*/lint_stubs/GTXE2_COMMON.sv" +lint_off -rule UNUSEDSIGNAL -file "*lint_stubs/qeciphy_gtx_transceiver.sv" -lint_off -rule UNUSEDSIGNAL -file "*/lint_stubs/qeciphy_clk_mmcm.sv" -lint_off -rule UNDRIVEN -file "*/lint_stubs/qeciphy_clk_mmcm.sv" +lint_off -rule UNUSEDSIGNAL -file "*lint_stubs/qeciphy_gth_transceiver.sv" -lint_off -rule UNUSEDSIGNAL -file "*/lint_stubs/qeciphy_gtx_transceiver.sv" -lint_off -rule UNDRIVEN -file "*/lint_stubs/qeciphy_gtx_transceiver.sv" +lint_off -rule UNUSEDSIGNAL -file "*lint_stubs/qeciphy_gty_transceiver.sv" -lint_off -rule UNUSEDSIGNAL -file "*/lint_stubs/qeciphy_gth_transceiver.sv" -lint_off -rule UNDRIVEN -file "*/lint_stubs/qeciphy_gth_transceiver.sv" +// Ignore linting package files -lint_off -rule UNUSEDSIGNAL -file "*/lint_stubs/qeciphy_gty_transceiver.sv" -lint_off -rule UNDRIVEN -file "*/lint_stubs/qeciphy_gty_transceiver.sv" +lint_off -file "*qeciphy_*pkg.sv" diff --git a/src/QECIPHY.sv b/src/QECIPHY.sv index 2e2b73c..b031ca8 100644 --- a/src/QECIPHY.sv +++ b/src/QECIPHY.sv @@ -68,8 +68,6 @@ module QECIPHY ( output logic GT_TX_N // GT TX differential negative ); - import qeciphy_build_cfg_pkg::*; - // ========================================================================= // Internal Signal Declarations // ========================================================================= @@ -90,6 +88,7 @@ module QECIPHY ( logic tx_rst_n; // ARSTn synchronized to TX clock logic rx_rst_n; // ARSTn synchronized to RX clock logic gt_rst_n; // GT reset + logic axis_rst_n; // ARSTn synchronized to AXI clock logic tx_clk; // TX clock logic tx_ch_enc_tready; // TX channel encoder AXIS tready logic [63:0] gt_tx_tdata; // TX data from channel encoder @@ -149,7 +148,7 @@ module QECIPHY ( qeciphy_controller i_qeciphy_controller ( .clk_i (ACLK), // AXI clock - .rst_n_i (ARSTn), // Master reset + .rst_n_i (axis_rst_n), // AXI clock domain reset .reset_done_i (reset_done), // Reset sequence complete from qeciphy_resetcontroller .rx_ready_i (rx_rdy_aclk), // Local RX ready from qeciphy_rx_channeldecoder .remote_rx_ready_i (remote_rx_rdy_aclk), // Remote RX ready from qeciphy_rx_channeldecoder @@ -169,7 +168,7 @@ module QECIPHY ( qeciphy_error_handler i_qeciphy_error_handler ( .clk_i (ACLK), // AXI clock - .rst_n_i (ARSTn), // Master reset + .rst_n_i (axis_rst_n), // AXI clock domain reset .rx_fault_fatal_i (rx_fault_fatal_aclk), // RX fault fatal from qeciphy_rx_channeldecoder .rx_error_code_i (rx_error_code), // RX error code from qeciphy_rx_channeldecoder .tx_fifo_overflow_i(tx_fifo_overflow), // TX FIFO overflow @@ -275,7 +274,7 @@ module QECIPHY ( // ========================================================================= qeciphy_serdes #( - .GT_TYPE(QECIPHY_GT_TYPE) // GT primitive type selection + .GT_TYPE(qeciphy_build_cfg_pkg::QECIPHY_GT_TYPE) // GT primitive type selection ) i_qeciphy_serdes ( // GT Reference and Control .gt_ref_clk_i (RCLK), // GT reference clock @@ -335,7 +334,7 @@ module QECIPHY ( // AXI Clock Domain Interface .axis_clk_i (ACLK), // AXI clock - .axis_rst_n_i (ARSTn), // AXI reset + .axis_rst_n_i (axis_rst_n), // AXI reset .rx_enable_aclk_i (rx_enable_aclk), .tx_link_enable_aclk_i (tx_link_enable_aclk), .tx_data_enable_aclk_i (tx_data_enable_aclk), @@ -356,10 +355,11 @@ module QECIPHY ( qeciphy_resetcontroller i_qeciphy_resetcontroller ( // Primary Control Interface (AXI Clock Domain) .axis_clk_i (ACLK), // AXI clock - .axis_rst_n_i (ARSTn), // Master reset + .async_rst_n_i (ARSTn), // Master reset .gt_power_good_i (gt_power_good_aclk), // GT power good status from qeciphy_serdes .gt_tx_rst_done_i (gt_tx_reset_done_aclk), // GT TX reset completion from qeciphy_serdes .gt_rx_rst_done_i (gt_rx_reset_done_aclk), // GT RX reset completion from qeciphy_serdes + .axis_rst_n_o (axis_rst_n), // async_rst_n_i reflected in AXIS domain .axis_datapath_rst_n_o(axis_datapath_rst_n), // AXI datapath reset output .rst_done_o (reset_done), // Reset sequence completion output to qeciphy_controller diff --git a/src/qeciphy_controller.sv b/src/qeciphy_controller.sv index e51a635..0889f48 100644 --- a/src/qeciphy_controller.sv +++ b/src/qeciphy_controller.sv @@ -47,8 +47,6 @@ module qeciphy_controller ( output logic rx_enable_o // Enable RX data processing ); - import qeciphy_pkg::*; - // ========================================================================= // State Machine Definition // ========================================================================= @@ -68,9 +66,9 @@ module qeciphy_controller ( } fsm_t; fsm_t state, state_nxt; // Current and next state registers - qeciphy_status_t status; // Mapped status output - logic in_ready_state; // Link ready flag - logic in_fault_state; // Fault state flag + qeciphy_pkg::qeciphy_status_t status; // Mapped status output + logic in_ready_state; // Link ready flag + logic in_fault_state; // Fault state flag // ========================================================================= // Control Signal Generation diff --git a/src/qeciphy_crc_check.sv b/src/qeciphy_crc_check.sv index 6cbb77e..7308b82 100644 --- a/src/qeciphy_crc_check.sv +++ b/src/qeciphy_crc_check.sv @@ -33,20 +33,18 @@ module qeciphy_crc_check ( output logic check_done_o ); - import qeciphy_pkg::*; - - qeciphy_vd_pkt_t vd_pkt; // Validation packet format - logic crc01_byte_match [0:1]; // Per-byte match results for CRC01 - logic crc23_byte_match [0:1]; // Per-byte match results for CRC23 - logic crc45_byte_match [0:1]; // Per-byte match results for CRC45 - logic crcvw_match; // Match result for CRC validation word - logic [1:0] valid_pipe; // Valid signal pipeline for timing - logic crc_error; // Internal error signal + qeciphy_pkg::qeciphy_vd_pkt_t vd_pkt; // Validation packet format + logic crc01_byte_match [0:1]; // Per-byte match results for CRC01 + logic crc23_byte_match [0:1]; // Per-byte match results for CRC23 + logic crc45_byte_match [0:1]; // Per-byte match results for CRC45 + logic crcvw_match; // Match result for CRC validation word + logic [1:0] valid_pipe; // Valid signal pipeline for timing + logic crc_error; // Internal error signal assign check_done_o = valid_pipe[1]; // Completion after pipeline delay // Valid signal pipeline - always_ff @(posedge clk_i or negedge rst_n_i) begin + always_ff @(posedge clk_i) begin if (!rst_n_i) valid_pipe <= 2'h0; else valid_pipe <= {valid_pipe[0], crc_valid_i}; end @@ -56,7 +54,7 @@ module qeciphy_crc_check ( if (!rst_n_i) begin vd_pkt <= '0; end else if (crc_boundary_i) begin - vd_pkt <= qeciphy_vd_pkt_t'(tdata_i); // Cast input data to validation packet type + vd_pkt <= qeciphy_pkg::qeciphy_vd_pkt_t'(tdata_i); // Cast input data to validation packet type end end diff --git a/src/qeciphy_error_handler.sv b/src/qeciphy_error_handler.sv index 6dd8467..394c9d6 100644 --- a/src/qeciphy_error_handler.sv +++ b/src/qeciphy_error_handler.sv @@ -38,10 +38,8 @@ module qeciphy_error_handler ( output logic [3:0] ecode_o // Latched error code output ); - import qeciphy_pkg::*; - - qeciphy_error_t ecode; // Internal error code using package enum type - logic fault_fatal; // Internal fault fatal signal + qeciphy_pkg::qeciphy_error_t ecode; // Internal error code using package enum type + logic fault_fatal; // Internal fault fatal signal // Output assignments assign ecode_o = ecode; @@ -60,13 +58,13 @@ module qeciphy_error_handler ( // Priority-based error code assignment, latched until reset always_ff @(posedge clk_i) begin if (!rst_n_i) begin - ecode <= NO_ERROR; + ecode <= qeciphy_pkg::NO_ERROR; end else if (!fault_fatal && rx_fault_fatal_i) begin - ecode <= qeciphy_error_t'(rx_error_code_i); + ecode <= qeciphy_pkg::qeciphy_error_t'(rx_error_code_i); end else if (!fault_fatal && tx_fifo_overflow_i) begin - ecode <= TX_FIFO_OVERFLOW; + ecode <= qeciphy_pkg::TX_FIFO_OVERFLOW; end else if (!fault_fatal && rx_fifo_overflow_i) begin - ecode <= RX_FIFO_OVERFLOW; + ecode <= qeciphy_pkg::RX_FIFO_OVERFLOW; end end diff --git a/src/qeciphy_gt_wrapper.sv b/src/qeciphy_gt_wrapper.sv index eb6492b..35e540e 100644 --- a/src/qeciphy_gt_wrapper.sv +++ b/src/qeciphy_gt_wrapper.sv @@ -3,7 +3,7 @@ // Original authors: Dogancan Davutoglu, Aniket Datta module qeciphy_gt_wrapper #( - parameter GT_TYPE = "GTY" // Valid values: "GTX", "GTY", "GTH" + parameter string GT_TYPE = "GTY" // Valid values: "GTX", "GTY", "GTH" ) ( input logic gt_ref_clk_i, @@ -37,7 +37,6 @@ module qeciphy_gt_wrapper #( logic rxoutclk; logic txoutclk; - logic rxcommadeten; logic rxpcommaalignen; logic rxmcommaalignen; logic rxbyteisaligned; @@ -76,17 +75,6 @@ module qeciphy_gt_wrapper #( end end - // Comma detect enable logic - always_ff @(posedge rx_clk_2x_o or negedge gt_rst_n_i) begin - if (!gt_rst_n_i) begin - rxcommadeten <= 1'b0; - end else if (gt_rx_rst_done_reg) begin - rxcommadeten <= 1'b1; - end else begin - rxcommadeten <= 1'b0; - end - end - // Comma align enable signals assign rxpcommaalignen = rx_comma_align_en; assign rxmcommaalignen = rx_comma_align_en; @@ -131,6 +119,19 @@ module qeciphy_gt_wrapper #( logic rxpmaresetdone; logic userclk_tx_reset; logic userclk_rx_reset; + logic rxcommadeten; + + // Comma detect enable logic + always_ff @(posedge rx_clk_2x_o or negedge gt_rst_n_i) begin + if (!gt_rst_n_i) begin + rxcommadeten <= 1'b0; + end else if (gt_rx_rst_done_reg) begin + rxcommadeten <= 1'b1; + end else begin + rxcommadeten <= 1'b0; + end + end + assign userclk_tx_reset = ~txpmaresetdone; assign userclk_rx_reset = ~rxpmaresetdone; @@ -248,6 +249,19 @@ module qeciphy_gt_wrapper #( logic rxpmaresetdone; logic userclk_tx_reset; logic userclk_rx_reset; + logic rxcommadeten; + + // Comma detect enable logic + always_ff @(posedge rx_clk_2x_o or negedge gt_rst_n_i) begin + if (!gt_rst_n_i) begin + rxcommadeten <= 1'b0; + end else if (gt_rx_rst_done_reg) begin + rxcommadeten <= 1'b1; + end else begin + rxcommadeten <= 1'b0; + end + end + assign userclk_tx_reset = ~txpmaresetdone; assign userclk_rx_reset = ~rxpmaresetdone; @@ -376,60 +390,60 @@ module qeciphy_gt_wrapper #( logic rxpmaresetdone; qeciphy_gtx_transceiver transceiver ( - .sysclk_in (f_clk_i), // input wire sysclk_in - .soft_reset_tx_in (1'b0), // input wire soft_reset_tx_in - .soft_reset_rx_in (1'b0), // input wire soft_reset_rx_in - .dont_reset_on_data_error_in(1'b1), // input wire dont_reset_on_data_error_in - .gt0_tx_fsm_reset_done_out (gt_tx_rst_done), // output wire gt0_tx_fsm_reset_done_out - .gt0_rx_fsm_reset_done_out (gt_rx_rst_done), // output wire gt0_rx_fsm_reset_done_out - .gt0_data_valid_in (rxpmaresetdone), // input wire gt0_data_valid_in - .gt0_drpaddr_in (9'h00), // input wire [8:0] gt0_drpaddr_in - .gt0_drpclk_in (f_clk_i), // input wire gt0_drpclk_in - .gt0_drpdi_in (16'h0000), // input wire [15:0] gt0_drpdi_in - .gt0_drpdo_out (), // output wire [15:0] gt0_drpdo_out - .gt0_drpen_in (1'b0), // input wire gt0_drpen_in - .gt0_drprdy_out (), // output wire gt0_drprdy_out - .gt0_drpwe_in (1'b0), // input wire gt0_drpwe_in - .gt0_dmonitorout_out (), // output wire [7:0] gt0_dmonitorout_out - .gt0_loopback_in (3'b000), // input wire [2:0] gt0_loopback_in - .gt0_eyescanreset_in (1'b0), // input wire gt0_eyescanreset_in - .gt0_rxuserrdy_in (1'b1), // input wire gt0_rxuserrdy_in - .gt0_eyescandataerror_out (), // output wire gt0_eyescandataerror_out - .gt0_eyescantrigger_in (1'b0), // input wire gt0_eyescantrigger_in - .gt0_rxusrclk_in (rx_clk_2x_o), // input wire gt0_rxusrclk_in - .gt0_rxusrclk2_in (rx_clk_2x_o), // input wire gt0_rxusrclk2_in - .gt0_rxdata_out (rx_tdata_o), // output wire [31:0] gt0_rxdata_out - .gt0_rxdisperr_out (), // output wire [3:0] gt0_rxdisperr_out - .gt0_rxnotintable_out (), // output wire [3:0] gt0_rxnotintable_out - .gt0_gtxrxp_in (gt_rx_p_i), // input wire gt0_gtxrxp_in - .gt0_gtxrxn_in (gt_rx_n_i), // input wire gt0_gtxrxn_in - .gt0_rxdfelpmreset_in (1'b0), // input wire gt0_rxdfelpmreset_in - .gt0_rxmonitorout_out (), // output wire [6:0] gt0_rxmonitorout_out - .gt0_rxmonitorsel_in (2'b00), // input wire [1:0] gt0_rxmonitorsel_in - .gt0_rxoutclk_out (rxoutclk), // output wire gt0_rxoutclk_out - .gt0_rxoutclkfabric_out (), // output wire gt0_rxoutclkfabric_out - .gt0_gtrxreset_in (~gt_rst_n_i), // input wire gt0_gtrxreset_in - .gt0_rxpmareset_in (~gt_rst_n_i), // input wire gt0_rxpmareset_in - .gt0_rxcharisk_out (), // output wire [3:0] gt0_rxcharisk_out - .gt0_rxresetdone_out (rxpmaresetdone), // output wire gt0_rxresetdone_out - .gt0_gttxreset_in (~gt_rst_n_i), // input wire gt0_gttxreset_in - .gt0_txuserrdy_in (1'b1), // input wire gt0_txuserrdy_in - .gt0_txusrclk_in (tx_clk_2x_o), // input wire gt0_txusrclk_in - .gt0_txusrclk2_in (tx_clk_2x_o), // input wire gt0_txusrclk2_in - .gt0_txdata_in (tx_tdata_i), // input wire [31:0] gt0_txdata_in - .gt0_gtxtxn_out (gt_tx_n_o), // output wire gt0_gtxtxn_out - .gt0_gtxtxp_out (gt_tx_p_o), // output wire gt0_gtxtxp_out - .gt0_txoutclk_out (txoutclk), // output wire gt0_txoutclk_out - .gt0_txoutclkfabric_out (), // output wire gt0_txoutclkfabric_out - .gt0_txoutclkpcs_out (), // output wire gt0_txoutclkpcs_out - .gt0_txcharisk_in (tx_tdata_charisk_i), // input wire [3:0] gt0_txcharisk_in - .gt0_txpmareset_in (~gt_rst_n_i), // input wire gt0_txpmareset_in - .gt0_txresetdone_out (), // output wire gt0_txresetdone_out - .gt0_qplllock_in (qplllock_out), // input wire gt0_qplllock_in - .gt0_qpllrefclklost_in (qpllrefclklost_out), // input wire gt0_qpllrefclklost_in - .gt0_qpllreset_out (qpllreset_in), // output wire gt0_qpllreset_out - .gt0_qplloutclk_in (qplloutclk_out), // input wire gt0_qplloutclk_in - .gt0_qplloutrefclk_in (qplloutrefclk_out), // input wire gt0_qplloutrefclk_in + .sysclk_in (f_clk_i), + .soft_reset_tx_in (1'b0), + .soft_reset_rx_in (~rx_datapath_resetn), + .dont_reset_on_data_error_in(1'b1), + .gt0_tx_fsm_reset_done_out (gt_tx_rst_done), + .gt0_rx_fsm_reset_done_out (gt_rx_rst_done), + .gt0_data_valid_in (rxpmaresetdone), + .gt0_drpaddr_in (9'h00), + .gt0_drpclk_in (f_clk_i), + .gt0_drpdi_in (16'h0000), + .gt0_drpdo_out (), + .gt0_drpen_in (1'b0), + .gt0_drprdy_out (), + .gt0_drpwe_in (1'b0), + .gt0_dmonitorout_out (), + .gt0_loopback_in (3'b000), + .gt0_eyescanreset_in (1'b0), + .gt0_rxuserrdy_in (1'b1), + .gt0_eyescandataerror_out (), + .gt0_eyescantrigger_in (1'b0), + .gt0_rxusrclk_in (rx_clk_2x_o), + .gt0_rxusrclk2_in (rx_clk_2x_o), + .gt0_rxdata_out (rx_tdata_o), + .gt0_rxdisperr_out (), + .gt0_rxnotintable_out (), + .gt0_gtxrxp_in (gt_rx_p_i), + .gt0_gtxrxn_in (gt_rx_n_i), + .gt0_rxdfelpmreset_in (1'b0), + .gt0_rxmonitorout_out (), + .gt0_rxmonitorsel_in (2'b00), + .gt0_rxoutclk_out (rxoutclk), + .gt0_rxoutclkfabric_out (), + .gt0_gtrxreset_in (~gt_rst_n_i), + .gt0_rxpmareset_in (~gt_rst_n_i), + .gt0_rxcharisk_out (), + .gt0_rxresetdone_out (rxpmaresetdone), + .gt0_gttxreset_in (~gt_rst_n_i), + .gt0_txuserrdy_in (1'b1), + .gt0_txusrclk_in (tx_clk_2x_o), + .gt0_txusrclk2_in (tx_clk_2x_o), + .gt0_txdata_in (tx_tdata_i), + .gt0_gtxtxn_out (gt_tx_n_o), + .gt0_gtxtxp_out (gt_tx_p_o), + .gt0_txoutclk_out (txoutclk), + .gt0_txoutclkfabric_out (), + .gt0_txoutclkpcs_out (), + .gt0_txcharisk_in (tx_tdata_charisk_i), + .gt0_txpmareset_in (~gt_rst_n_i), + .gt0_txresetdone_out (), + .gt0_qplllock_in (qplllock_out), + .gt0_qpllrefclklost_in (qpllrefclklost_out), + .gt0_qpllreset_out (qpllreset_in), + .gt0_qplloutclk_in (qplloutclk_out), + .gt0_qplloutrefclk_in (qplloutrefclk_out), .gt0_rxpcommaalignen_in (rxpcommaalignen), .gt0_rxmcommaalignen_in (rxmcommaalignen), .gt0_rxbyteisaligned_out (rxbyteisaligned), diff --git a/src/qeciphy_resetcontroller.sv b/src/qeciphy_resetcontroller.sv index 0ded1d9..51b301f 100644 --- a/src/qeciphy_resetcontroller.sv +++ b/src/qeciphy_resetcontroller.sv @@ -30,10 +30,11 @@ module qeciphy_resetcontroller ( // AXIS Clock Domain Interface (Primary Reset Control) // ========================================================================= input logic axis_clk_i, // Primary AXIS clock - input logic axis_rst_n_i, // Master reset input (active-low) + input logic async_rst_n_i, // Master reset input (active-low) input logic gt_power_good_i, // GT power supply ready indicator input logic gt_tx_rst_done_i, // GT TX reset sequence complete input logic gt_rx_rst_done_i, // GT RX reset sequence complete + output logic axis_rst_n_o, // async_rst_n_i reflected in AXIS domain output logic axis_datapath_rst_n_o, // AXIS datapath reset output output logic rst_done_o, // Reset sequence complete @@ -41,21 +42,21 @@ module qeciphy_resetcontroller ( // TX Clock Domain Interface // ========================================================================= input logic tx_clk_i, // TX clock - output logic tx_rst_n_o, // axis_rst_n_i reflected in TX domain + output logic tx_rst_n_o, // async_rst_n_i reflected in TX domain output logic tx_datapath_rst_n_o, // TX datapath reset output // ========================================================================= // RX Clock Domain Interface // ========================================================================= input logic rx_clk_i, // RX clock - output logic rx_rst_n_o, // axis_rst_n_i reflected in RX domain + output logic rx_rst_n_o, // async_rst_n_i reflected in RX domain output logic rx_datapath_rst_n_o, // RX datapath reset output // ========================================================================= // Fabric Clock Domain Interface // ========================================================================= input logic f_clk_i, // Free-running clock - output logic f_rst_n_o, // axis_rst_n_i reflected in free running domain + output logic f_rst_n_o, // async_rst_n_i reflected in free running domain output logic gt_rst_n_o // GT transceiver reset ); @@ -101,43 +102,61 @@ module qeciphy_resetcontroller ( logic gt_rst_state; logic axis_datapath_rst_state; - // axis_rst_n_i reflected in other clock domains + // async_rst_n_i reflected in other clock domains logic f_rst_n; logic rx_rst_n; logic tx_rst_n; + logic axis_rst_n; // ========================================================================= // Cross-Domain Reset Synchronization // ========================================================================= - assign f_rst_n_o = f_rst_n; + assign f_rst_n_o = f_rst_n; assign rx_rst_n_o = rx_rst_n; assign tx_rst_n_o = tx_rst_n; + assign axis_rst_n_o = axis_rst_n; // Synchronize reset release to fabric clock domain - riv_synchronizer_2ff i_fclk_rst_cdc ( + riv_synchronizer_2ff #( + .RESET_TYPE("ASYNC") + ) i_fclk_rst_cdc ( .src_in (1'b1), .dst_clk (f_clk_i), - .dst_rst_n(axis_rst_n_i), + .dst_rst_n(async_rst_n_i), .dst_out (f_rst_n) ); // Synchronize reset release to RX clock domain - riv_synchronizer_2ff i_rx_clk_rst_cdc ( + riv_synchronizer_2ff #( + .RESET_TYPE("ASYNC") + ) i_rx_clk_rst_cdc ( .src_in (1'b1), .dst_clk (rx_clk_i), - .dst_rst_n(axis_rst_n_i), + .dst_rst_n(async_rst_n_i), .dst_out (rx_rst_n) ); // Synchronize reset release to TX clock domain - riv_synchronizer_2ff i_tx_clk_rst_cdc ( + riv_synchronizer_2ff #( + .RESET_TYPE("ASYNC") + ) i_tx_clk_rst_cdc ( .src_in (1'b1), .dst_clk (tx_clk_i), - .dst_rst_n(axis_rst_n_i), + .dst_rst_n(async_rst_n_i), .dst_out (tx_rst_n) ); + // Synchronize reset release to AXIS clock domain + riv_synchronizer_2ff #( + .RESET_TYPE("ASYNC") + ) i_axis_clk_rst_cdc ( + .src_in (1'b1), + .dst_clk (axis_clk_i), + .dst_rst_n(async_rst_n_i), + .dst_out (axis_rst_n) + ); + // ========================================================================= // State Machine Decoders // ========================================================================= @@ -184,7 +203,7 @@ module qeciphy_resetcontroller ( riv_synchronizer_2ff i_cdc_gt_delay_done ( .src_in (gt_delay_done_fclk), .dst_clk (axis_clk_i), - .dst_rst_n(axis_rst_n_i), + .dst_rst_n(axis_rst_n), .dst_out (gt_delay_done) ); @@ -195,7 +214,7 @@ module qeciphy_resetcontroller ( // Datapath delay countdown counter always_ff @(posedge axis_clk_i) begin - if (!axis_rst_n_i) begin + if (!axis_rst_n) begin datapath_delay_counter <= 5'd31; end else if (in_datapath_delay_state) begin datapath_delay_counter <= datapath_delay_counter - 5'd1; @@ -204,7 +223,7 @@ module qeciphy_resetcontroller ( // Datapath delay completion always_ff @(posedge axis_clk_i) begin - if (!axis_rst_n_i) begin + if (!axis_rst_n) begin datapath_delay_done <= 1'b0; end else if (~|datapath_delay_counter) begin datapath_delay_done <= 1'b1; @@ -217,7 +236,7 @@ module qeciphy_resetcontroller ( // State register always_ff @(posedge axis_clk_i) begin - if (!axis_rst_n_i) begin + if (!axis_rst_n) begin state <= RESET; end else begin state <= state_nxt; diff --git a/src/qeciphy_rx_32b_to_64b.sv b/src/qeciphy_rx_32b_to_64b.sv index 59586ad..94d0022 100644 --- a/src/qeciphy_rx_32b_to_64b.sv +++ b/src/qeciphy_rx_32b_to_64b.sv @@ -35,8 +35,6 @@ module qeciphy_rx_32b_to_64b ( output logic aligned_o // Alignment status output ); - import qeciphy_pkg::*; - // State Machine Definition typedef enum bit [3:0] { RESET = 4'b0001, // Initial reset state @@ -121,8 +119,8 @@ module qeciphy_rx_32b_to_64b ( if (!rst_n_i) begin is_faw_q <= '0; end else begin - is_faw_q[0] <= is_faw(tdata_64b[0]); // Check option 0 for FAW - is_faw_q[1] <= is_faw(tdata_64b[1]); // Check option 1 for FAW + is_faw_q[0] <= qeciphy_pkg::is_faw(tdata_64b[0]); // Check option 0 for FAW + is_faw_q[1] <= qeciphy_pkg::is_faw(tdata_64b[1]); // Check option 1 for FAW end end diff --git a/src/qeciphy_rx_boundary_gen.sv b/src/qeciphy_rx_boundary_gen.sv index 17011a0..c55b68a 100644 --- a/src/qeciphy_rx_boundary_gen.sv +++ b/src/qeciphy_rx_boundary_gen.sv @@ -34,8 +34,6 @@ module qeciphy_rx_boundary_gen ( output logic crc_boundary_o // CRC boundary timing signal ); - import qeciphy_pkg::*; - // State machine for frame alignment and boundary generation typedef enum bit [7:0] { RESET = 8'b00000001, // Initial reset state @@ -92,7 +90,7 @@ module qeciphy_rx_boundary_gen ( assign in_crc_boundary_start_state = state[6]; // Capture FAW detection result - assign faw_detected = enable_i ? is_faw(tdata_i) : 1'b0; + assign faw_detected = enable_i ? qeciphy_pkg::is_faw(tdata_i) : 1'b0; // Register FAW detection result always_ff @(posedge clk_i) begin diff --git a/src/qeciphy_rx_comma_detect.sv b/src/qeciphy_rx_comma_detect.sv index 216c454..3de63a8 100644 --- a/src/qeciphy_rx_comma_detect.sv +++ b/src/qeciphy_rx_comma_detect.sv @@ -102,11 +102,6 @@ module qeciphy_rx_comma_detect #( logic [ 3:0] data_crc_slot_count_d; logic [ 3:0] data_crc_slot_count_q; - logic faw_1_slot; - logic faw_2_slot; - logic data_slot; - logic crc_1_slot; - logic crc_2_slot; logic [ 7:0] reset_delay_count_q; diff --git a/src/qeciphy_rx_controller.sv b/src/qeciphy_rx_controller.sv index de0d779..47f07b5 100644 --- a/src/qeciphy_rx_controller.sv +++ b/src/qeciphy_rx_controller.sv @@ -42,8 +42,6 @@ module qeciphy_rx_controller ( output logic [3:0] rx_error_code_o // RX error code output (sticky) ); - import qeciphy_pkg::*; - // State machine for RX subsystem control typedef enum logic [5:0] { RESET = 6'b000001, // Initial reset state @@ -57,7 +55,7 @@ module qeciphy_rx_controller ( logic in_training_ready_fault_state; // Decodes TRAINING, READY or FAULT_FATAL state logic in_ready_state; // Decodes READY state logic in_fault_state; // Decodes FAULT_FATAL state - qeciphy_error_t error_code; // Error code + qeciphy_pkg::qeciphy_error_t error_code; // Error code // Output assignments from internal signals assign rx_rdy_o = in_ready_state; @@ -96,13 +94,13 @@ module qeciphy_rx_controller ( // Error code logic always_ff @(posedge clk_i) begin if (!rst_n_i) begin - error_code <= NO_ERROR; // Clear error code on reset + error_code <= qeciphy_pkg::NO_ERROR; // Clear error code on reset end else if (!enable_i) begin - error_code <= NO_ERROR; // Clear error code on disable + error_code <= qeciphy_pkg::NO_ERROR; // Clear error code on disable end else if (in_ready_state && crc_err_i) begin - error_code <= CRC_ERROR; // Set CRC error code + error_code <= qeciphy_pkg::CRC_ERROR; // Set CRC error code end else if (in_ready_state && faw_err_i) begin - error_code <= FAW_ERROR; // Set FAW error code + error_code <= qeciphy_pkg::FAW_ERROR; // Set FAW error code end end diff --git a/src/qeciphy_rx_monitor.sv b/src/qeciphy_rx_monitor.sv index 484b869..50283fa 100644 --- a/src/qeciphy_rx_monitor.sv +++ b/src/qeciphy_rx_monitor.sv @@ -63,24 +63,22 @@ module qeciphy_rx_monitor ( output logic remote_rx_rdy_o ); - import qeciphy_pkg::*; - - qeciphy_faw_t faw; // Frame Alignment Word structure - - logic faw_error; // FAW validation error (sticky) - logic crc_error; // CRC validation error (sticky) - logic remote_rx_rdy; // Remote receiver ready status - logic [63:0] data_pipe [0:10]; // 11-stage data delay pipeline - logic [10:0] valid_pipe; // Valid bit pipeline (synchronized with data) - logic [10:0] valid_pipe_nxt; // Next state of valid pipeline - - logic [15:0] crc01_calc; // Calculated CRC01 value - logic [15:0] crc23_calc; // Calculated CRC23 value - logic [15:0] crc45_calc; // Calculated CRC45 value - logic [ 7:0] crcvw_calc; // Calculated CRC VW value - logic crc_valid; // Valid signal for the calulated CRCs - logic crc_check_error; // CRC check error from qeciophy_crc_check - logic crc_check_done; // CRC check done signal from qeciophy_crc_check + qeciphy_pkg::qeciphy_faw_t faw; // Frame Alignment Word structure + + logic faw_error; // FAW validation error (sticky) + logic crc_error; // CRC validation error (sticky) + logic remote_rx_rdy; // Remote receiver ready status + logic [63:0] data_pipe [0:10]; // 11-stage data delay pipeline + logic [10:0] valid_pipe; // Valid bit pipeline (synchronized with data) + logic [10:0] valid_pipe_nxt; // Next state of valid pipeline + + logic [15:0] crc01_calc; // Calculated CRC01 value + logic [15:0] crc23_calc; // Calculated CRC23 value + logic [15:0] crc45_calc; // Calculated CRC45 value + logic [ 7:0] crcvw_calc; // Calculated CRC VW value + logic crc_valid; // Valid signal for the calulated CRCs + logic crc_check_error; // CRC check error from qeciophy_crc_check + logic crc_check_done; // CRC check done signal from qeciophy_crc_check // Output assignments from pipeline head and status signals assign faw_error_o = faw_error; @@ -95,13 +93,13 @@ module qeciphy_rx_monitor ( faw_error <= 1'b0; end else if (!enable_i) begin faw_error <= 1'b0; // Clear when disabled - end else if (faw_boundary_i && !is_faw(tdata_i)) begin + end else if (faw_boundary_i && !qeciphy_pkg::is_faw(tdata_i)) begin faw_error <= 1'b1; // Set on invalid FAW end end // FAW structure extraction (valid only during faw_boundary_i) - assign faw = qeciphy_faw_t'(tdata_i); + assign faw = qeciphy_pkg::qeciphy_faw_t'(tdata_i); // Remote receiver ready extraction from FAW always_ff @(posedge clk_i) begin diff --git a/src/qeciphy_serdes.sv b/src/qeciphy_serdes.sv index 6afea7d..4417d2e 100644 --- a/src/qeciphy_serdes.sv +++ b/src/qeciphy_serdes.sv @@ -22,7 +22,7 @@ //------------------------------------------------------------------------------ module qeciphy_serdes #( - parameter GT_TYPE = "GTY" // GT primitive type: "GTX", "GTY", or "GTH" + parameter string GT_TYPE = "GTY" // GT primitive type: "GTX", "GTY", or "GTH" ) ( input logic gt_ref_clk_i, // GT reference clock input input logic f_clk_i, // Free-running fabric clock diff --git a/src/qeciphy_tx_packet_gen.sv b/src/qeciphy_tx_packet_gen.sv index 70737c2..d51e203 100644 --- a/src/qeciphy_tx_packet_gen.sv +++ b/src/qeciphy_tx_packet_gen.sv @@ -44,41 +44,38 @@ module qeciphy_tx_packet_gen ( input logic rx_rdy_i // Receiver ready status to transmit ); - import qeciphy_pkg::*; - // 3-stage data pipeline for packet generation - logic [63:0] tdata_pipe [0:2]; // Pipeline data registers [stage0, stage1, stage2] - logic [63:0] tdata_pipe_nxt [0:2]; // Next values for pipeline data + logic [63:0] tdata_pipe [0:2]; // Pipeline data registers [stage0, stage1, stage2] + logic [63:0] tdata_pipe_nxt [0:2]; // Next values for pipeline data // 3 stage pipeline to track if data is FAW - logic tdata_isfaw_pipe [0:2]; + logic tdata_isfaw_pipe [0:2]; // Valid bit tracking for data segments - logic [ 5:0] data_valid_mask; // Bitmask tracking which data segments contain valid data - logic [ 2:0] valid_bit_ptr; // Circular pointer to current valid bit position (0-5) - logic [ 2:0] valid_bit_ptr_nxt; // Next value for valid bit pointer + logic [ 5:0] data_valid_mask; // Bitmask tracking which data segments contain valid data + logic [ 2:0] valid_bit_ptr; // Circular pointer to current valid bit position (0-5) + logic [ 2:0] valid_bit_ptr_nxt; // Next value for valid bit pointer // CRC computation results for different data lanes - logic [15:0] crc01_calc; // CRC result for data words 0-1 - logic [15:0] crc23_calc; // CRC result for data words 2-3 - logic [15:0] crc45_calc; // CRC result for data words 4-5 - logic [ 7:0] crcvw_calc; // CRC result for valid word field - logic crc_valid; // CRC computation valid flag from qeciphy_crc_compute module + logic [15:0] crc01_calc; // CRC result for data words 0-1 + logic [15:0] crc23_calc; // CRC result for data words 2-3 + logic [15:0] crc45_calc; // CRC result for data words 4-5 + logic [ 7:0] crcvw_calc; // CRC result for valid word field + logic crc_valid; // CRC computation valid flag from qeciphy_crc_compute module // Delayed boundary signals for pipeline synchronization - logic faw_boundary_q; // Registered FAW boundary signal - logic crc_boundary_q; // Registered CRC boundary signal + logic faw_boundary_q; // Registered FAW boundary signal + logic crc_boundary_q; // Registered CRC boundary signal // Control signals for packet generation modes - logic boundary_chars_enable; // Enable boundary character insertion (FAW/CRC packets) - logic [ 1:0] boundary_chars_enable_pipe; // 2-stage pipeline of boundary enable signal - logic data_enable; // Enable user data transmission + logic boundary_chars_enable; // Enable boundary character insertion (FAW/CRC packets) + logic [ 1:0] boundary_chars_enable_pipe; // 2-stage pipeline of boundary enable signal + logic data_enable; // Enable user data transmission // Packet structure instances - qeciphy_faw_t faw; // Frame Alignment Word - qeciphy_vd_pkt_t vd_pkt; // Validation Word - qeciphy_vd_pkt_t vd_pkt_pipe [0:2]; // Validation Word pipeline - qeciphy_vd_pkt_t vd_pkt_pipe_nxt [0:2]; // Next values for validation Word pipeline + qeciphy_pkg::qeciphy_faw_t faw; // Frame Alignment Word + qeciphy_pkg::qeciphy_vd_pkt_t vd_pkt_pipe [0:2]; // Validation Word pipeline + qeciphy_pkg::qeciphy_vd_pkt_t vd_pkt_pipe_nxt [0:2]; // Next values for validation Word pipeline // Ready when active and not inserting boundary characters assign s_axis_tready_o = tx_active_i && !faw_boundary_i && !crc_boundary_i; @@ -108,9 +105,9 @@ module qeciphy_tx_packet_gen ( always_comb begin faw.rx_rdy = rx_rdy_i; faw.reserved_62_40 = 23'h0; - faw.word_comma = WORD_ALIGNMENT_COMMA; + faw.word_comma = qeciphy_pkg::WORD_ALIGNMENT_COMMA; faw.reserved_31_8 = 24'h0; - faw.byte_comma = BYTE_ALIGNMENT_COMMA; + faw.byte_comma = qeciphy_pkg::BYTE_ALIGNMENT_COMMA; end // Build Validation Word with placeholder CRC values @@ -128,8 +125,8 @@ module qeciphy_tx_packet_gen ( assign tdata_pipe_nxt[0] = boundary_chars_enable ? (faw_boundary_i ? faw : (crc_boundary_i ? vd_pkt_pipe_nxt[0] : - (data_enable ? (s_axis_tvalid_i ? s_axis_tdata_i : IDLE_WORD) : IDLE_WORD))) - : IDLE_WORD; + (data_enable ? (s_axis_tvalid_i ? s_axis_tdata_i : qeciphy_pkg::IDLE_WORD) : qeciphy_pkg::IDLE_WORD))) + : qeciphy_pkg::IDLE_WORD; // Register stage 0 data always_ff @(posedge clk_i) begin @@ -151,7 +148,7 @@ module qeciphy_tx_packet_gen ( end // Extract validation packet structure from stage 1 - assign vd_pkt_pipe[1] = qeciphy_vd_pkt_t'(tdata_pipe[1]); + assign vd_pkt_pipe[1] = qeciphy_pkg::qeciphy_vd_pkt_t'(tdata_pipe[1]); // Build complete validation packet with computed CRC values always_comb begin From 5d36777d6af02151b7fee98bd6baeedeb4fb1204 Mon Sep 17 00:00:00 2001 From: rojalin mishra Date: Fri, 27 Feb 2026 12:01:47 +0000 Subject: [PATCH 5/6] Fixing the scorebaord to accomodate new clock cycles introduced in the FSM after synchronous reset --- .../qeciphy_env_state_scoreboard.svh | 59 +++++++++++++++++-- 1 file changed, 53 insertions(+), 6 deletions(-) diff --git a/uvm/qeciphy_env/scoreboards/qeciphy_env_state_scoreboard.svh b/uvm/qeciphy_env/scoreboards/qeciphy_env_state_scoreboard.svh index 79c8d0d..c54ac83 100644 --- a/uvm/qeciphy_env/scoreboards/qeciphy_env_state_scoreboard.svh +++ b/uvm/qeciphy_env/scoreboards/qeciphy_env_state_scoreboard.svh @@ -26,6 +26,7 @@ class qeciphy_env_state_scoreboard extends uvm_scoreboard; bit m_dut_power_down_pending; bit m_dut_cycle_pending; // '1' during a DUT-initiated power-cycle (power-down then power-up). bit m_tbphy_cycle_pending; // '1' during a TB-Phy-initiated power-cycle (power-down then power-up). + int m_reset_state_cycle_count; // Counter for number of cycles spent in PHY_RESET state. `uvm_component_utils_begin(qeciphy_env_state_scoreboard) `uvm_field_int(m_num_errors, UVM_DEFAULT | UVM_UNSIGNED) @@ -35,6 +36,7 @@ class qeciphy_env_state_scoreboard extends uvm_scoreboard; `uvm_field_int(m_requested_tbphy_state, UVM_DEFAULT | UVM_BIN) `uvm_field_int(m_dut_cycle_pending, UVM_DEFAULT | UVM_BIN) `uvm_field_int(m_tbphy_cycle_pending, UVM_DEFAULT | UVM_BIN) + `uvm_field_int(m_reset_state_cycle_count, UVM_DEFAULT | UVM_UNSIGNED) `uvm_component_utils_end @@ -94,6 +96,7 @@ class qeciphy_env_state_scoreboard extends uvm_scoreboard; m_requested_tbphy_state = 1'b1; m_dut_cycle_pending = 1'b0; m_tbphy_cycle_pending = 1'b0; + m_reset_state_cycle_count = 1'b0; // Allow reset to take effect and then check that DUT is in reset until reset goes away (synchronously). #1.0ns @@ -133,8 +136,8 @@ class qeciphy_env_state_scoreboard extends uvm_scoreboard; qeciphy_state_enum prev_dut_status; bit fsm_error; - exp_dut_status = PHY_WAIT_FOR_RESET; - prev_dut_status = PHY_WAIT_FOR_RESET; + exp_dut_status = PHY_RESET; + prev_dut_status = PHY_RESET; fsm_error = 1'b0; forever begin @@ -173,12 +176,56 @@ class qeciphy_env_state_scoreboard extends uvm_scoreboard; // // Stay in RESET for only one clock and then transition to WAIT_FOR_RESET. //--------------------------------------------------------------------------------------------------------------------------------------- - virtual function qeciphy_state_enum check_reset_state(output bit error = 1'b0); + //--------------------------------------------------------------------------------------------------------------------------------------- +// Function: check_reset_state +// +// Stay in RESET for 1-5 clocks and then transition to WAIT_FOR_RESET. +//--------------------------------------------------------------------------------------------------------------------------------------- +virtual function qeciphy_state_enum check_reset_state(output bit error = 1'b0); + const string msg_id = {get_type_name(), ".check_reset_state"}; + qeciphy_state_enum current_status; - error = ~check_status("DUT", PHY_WAIT_FOR_RESET); + current_status = get_status("DUT"); + + if (current_status == PHY_RESET) begin + // Still in PHY_RESET, increment counter + m_reset_state_cycle_count++; + + // Check if we've exceeded maximum allowed cycles in RESET + if (m_reset_state_cycle_count > 5) begin + `uvm_error(msg_id, $sformatf("DUT stayed in PHY_RESET for %0d cycles (max allowed: 5)", + m_reset_state_cycle_count)) + error = 1'b1; + end + + return (PHY_RESET); + end + else if (current_status == PHY_WAIT_FOR_RESET) begin + // Transitioned to PHY_WAIT_FOR_RESET, check if cycle count is valid + if (m_reset_state_cycle_count < 1 || m_reset_state_cycle_count > 5) begin + `uvm_error(msg_id, $sformatf("DUT transitioned from PHY_RESET to PHY_WAIT_FOR_RESET after %0d cycles (expected: 1-5)", + m_reset_state_cycle_count)) + error = 1'b1; + end + else begin + `uvm_info(msg_id, $sformatf("DUT transitioned from PHY_RESET to PHY_WAIT_FOR_RESET after %0d cycles", + m_reset_state_cycle_count), UVM_MEDIUM) + end + + // Reset counter for next time + m_reset_state_cycle_count = 0; return (PHY_WAIT_FOR_RESET); - - endfunction : check_reset_state + end + else begin + // Invalid transition from PHY_RESET to something other than PHY_WAIT_FOR_RESET + `uvm_error(msg_id, $sformatf("DUT transitioned from PHY_RESET to invalid state %0s after %0d cycles", + current_status.name(), m_reset_state_cycle_count)) + error = 1'b1; + m_reset_state_cycle_count = 0; + return (current_status); + end + +endfunction : check_reset_state //--------------------------------------------------------------------------------------------------------------------------------------- From 654305dd4e44ec1de8fe971923db75513c100516 Mon Sep 17 00:00:00 2001 From: Aniket Datta Date: Mon, 2 Mar 2026 01:54:15 +0000 Subject: [PATCH 6/6] Updated lint_stubs interfaces --- lint_stubs/qeciphy_gth_transceiver.sv | 90 ++++++++++---------- lint_stubs/qeciphy_gtx_transceiver.sv | 118 +++++++++++++------------- lint_stubs/qeciphy_gty_transceiver.sv | 90 ++++++++++---------- 3 files changed, 149 insertions(+), 149 deletions(-) diff --git a/lint_stubs/qeciphy_gth_transceiver.sv b/lint_stubs/qeciphy_gth_transceiver.sv index d48cd2a..e5e7607 100644 --- a/lint_stubs/qeciphy_gth_transceiver.sv +++ b/lint_stubs/qeciphy_gth_transceiver.sv @@ -11,51 +11,51 @@ // ----------------------------------------------------------------------------- module qeciphy_gth_transceiver ( - input gtwiz_userclk_tx_active_in, - input gtwiz_userclk_rx_active_in, - input gtwiz_reset_clk_freerun_in, - input gtwiz_reset_all_in, - input gtwiz_reset_tx_pll_and_datapath_in, - input gtwiz_reset_tx_datapath_in, - input gtwiz_reset_rx_pll_and_datapath_in, - input gtwiz_reset_rx_datapath_in, - output gtwiz_reset_rx_cdr_stable_out, - output gtwiz_reset_tx_done_out, - output gtwiz_reset_rx_done_out, - input [31:0] gtwiz_userdata_tx_in, - output [31:0] gtwiz_userdata_rx_out, - input gtrefclk00_in, - output qpll0outclk_out, - output qpll0lock_out, - output qpll0outrefclk_out, - input gthrxn_in, - input gthrxp_in, - input rx8b10ben_in, - input rxusrclk_in, - input rxusrclk2_in, - input tx8b10ben_in, - input [15:0] txctrl0_in, - input [15:0] txctrl1_in, - input [7:0] txctrl2_in, - input txusrclk_in, - input txusrclk2_in, - output gtpowergood_out, - output gthtxn_out, - output gthtxp_out, - output [15:0] rxctrl0_out, - output [15:0] rxctrl1_out, - output [7:0] rxctrl2_out, - output [7:0] rxctrl3_out, - output rxoutclk_out, - output rxpmaresetdone_out, - output txoutclk_out, - output txpmaresetdone_out, - input rxcommadeten_in, - input rxpcommaalignen_in, - input rxmcommaalignen_in, - output rxbyteisaligned_out, - output rxbyterealign_out, - output rxcommadet_out + input logic gtwiz_userclk_tx_active_in, + input logic gtwiz_userclk_rx_active_in, + input logic gtwiz_reset_clk_freerun_in, + input logic gtwiz_reset_all_in, + input logic gtwiz_reset_tx_pll_and_datapath_in, + input logic gtwiz_reset_tx_datapath_in, + input logic gtwiz_reset_rx_pll_and_datapath_in, + input logic gtwiz_reset_rx_datapath_in, + output logic gtwiz_reset_rx_cdr_stable_out, + output logic gtwiz_reset_tx_done_out, + output logic gtwiz_reset_rx_done_out, + input logic [31:0] gtwiz_userdata_tx_in, + output logic [31:0] gtwiz_userdata_rx_out, + input logic gtrefclk00_in, + output logic qpll0outclk_out, + output logic qpll0lock_out, + output logic qpll0outrefclk_out, + input logic gthrxn_in, + input logic gthrxp_in, + input logic rx8b10ben_in, + input logic rxusrclk_in, + input logic rxusrclk2_in, + input logic tx8b10ben_in, + input logic [15:0] txctrl0_in, + input logic [15:0] txctrl1_in, + input logic [7:0] txctrl2_in, + input logic txusrclk_in, + input logic txusrclk2_in, + output logic gtpowergood_out, + output logic gthtxn_out, + output logic gthtxp_out, + output logic [15:0] rxctrl0_out, + output logic [15:0] rxctrl1_out, + output logic [7:0] rxctrl2_out, + output logic [7:0] rxctrl3_out, + output logic rxoutclk_out, + output logic rxpmaresetdone_out, + output logic txoutclk_out, + output logic txpmaresetdone_out, + input logic rxcommadeten_in, + input logic rxpcommaalignen_in, + input logic rxmcommaalignen_in, + output logic rxbyteisaligned_out, + output logic rxbyterealign_out, + output logic rxcommadet_out ); assign gtwiz_reset_rx_cdr_stable_out = '0; diff --git a/lint_stubs/qeciphy_gtx_transceiver.sv b/lint_stubs/qeciphy_gtx_transceiver.sv index a33566a..24a3e2d 100644 --- a/lint_stubs/qeciphy_gtx_transceiver.sv +++ b/lint_stubs/qeciphy_gtx_transceiver.sv @@ -11,65 +11,65 @@ // ----------------------------------------------------------------------------- module qeciphy_gtx_transceiver ( - input wire sysclk_in, - input wire soft_reset_tx_in, - input wire soft_reset_rx_in, - input wire dont_reset_on_data_error_in, - output wire gt0_tx_fsm_reset_done_out, - output wire gt0_rx_fsm_reset_done_out, - input wire gt0_data_valid_in, - input wire [ 8:0] gt0_drpaddr_in, - input wire gt0_drpclk_in, - input wire [15:0] gt0_drpdi_in, - output wire [15:0] gt0_drpdo_out, - input wire gt0_drpen_in, - output wire gt0_drprdy_out, - input wire gt0_drpwe_in, - output wire [ 7:0] gt0_dmonitorout_out, - input wire [ 2:0] gt0_loopback_in, - input wire gt0_eyescanreset_in, - input wire gt0_rxuserrdy_in, - output wire gt0_eyescandataerror_out, - input wire gt0_eyescantrigger_in, - input wire gt0_rxusrclk_in, - input wire gt0_rxusrclk2_in, - output wire [31:0] gt0_rxdata_out, - output wire [ 3:0] gt0_rxdisperr_out, - output wire [ 3:0] gt0_rxnotintable_out, - input wire gt0_gtxrxp_in, - input wire gt0_gtxrxn_in, - input wire gt0_rxdfelpmreset_in, - output wire [ 6:0] gt0_rxmonitorout_out, - input wire [ 1:0] gt0_rxmonitorsel_in, - output wire gt0_rxoutclk_out, - output wire gt0_rxoutclkfabric_out, - input wire gt0_gtrxreset_in, - input wire gt0_rxpmareset_in, - output wire [ 3:0] gt0_rxcharisk_out, - output wire gt0_rxresetdone_out, - input wire gt0_gttxreset_in, - input wire gt0_txuserrdy_in, - input wire gt0_txusrclk_in, - input wire gt0_txusrclk2_in, - input wire [31:0] gt0_txdata_in, - output wire gt0_gtxtxn_out, - output wire gt0_gtxtxp_out, - output wire gt0_txoutclk_out, - output wire gt0_txoutclkfabric_out, - output wire gt0_txoutclkpcs_out, - input wire [ 3:0] gt0_txcharisk_in, - input wire gt0_txpmareset_in, - output wire gt0_txresetdone_out, - input wire gt0_qplllock_in, - input wire gt0_qpllrefclklost_in, - output wire gt0_qpllreset_out, - input wire gt0_qplloutclk_in, - input wire gt0_qplloutrefclk_in, - input wire gt0_rxpcommaalignen_in, - input wire gt0_rxmcommaalignen_in, - output wire gt0_rxbyteisaligned_out, - output wire gt0_rxbyterealign_out, - output wire gt0_rxcommadet_out + input logic sysclk_in, + input logic soft_reset_tx_in, + input logic soft_reset_rx_in, + input logic dont_reset_on_data_error_in, + output logic gt0_tx_fsm_reset_done_out, + output logic gt0_rx_fsm_reset_done_out, + input logic gt0_data_valid_in, + input logic [ 8:0] gt0_drpaddr_in, + input logic gt0_drpclk_in, + input logic [15:0] gt0_drpdi_in, + output logic [15:0] gt0_drpdo_out, + input logic gt0_drpen_in, + output logic gt0_drprdy_out, + input logic gt0_drpwe_in, + output logic [ 7:0] gt0_dmonitorout_out, + input logic [ 2:0] gt0_loopback_in, + input logic gt0_eyescanreset_in, + input logic gt0_rxuserrdy_in, + output logic gt0_eyescandataerror_out, + input logic gt0_eyescantrigger_in, + input logic gt0_rxusrclk_in, + input logic gt0_rxusrclk2_in, + output logic [31:0] gt0_rxdata_out, + output logic [ 3:0] gt0_rxdisperr_out, + output logic [ 3:0] gt0_rxnotintable_out, + input logic gt0_gtxrxp_in, + input logic gt0_gtxrxn_in, + input logic gt0_rxdfelpmreset_in, + output logic [ 6:0] gt0_rxmonitorout_out, + input logic [ 1:0] gt0_rxmonitorsel_in, + output logic gt0_rxoutclk_out, + output logic gt0_rxoutclkfabric_out, + input logic gt0_gtrxreset_in, + input logic gt0_rxpmareset_in, + output logic [ 3:0] gt0_rxcharisk_out, + output logic gt0_rxresetdone_out, + input logic gt0_gttxreset_in, + input logic gt0_txuserrdy_in, + input logic gt0_txusrclk_in, + input logic gt0_txusrclk2_in, + input logic [31:0] gt0_txdata_in, + output logic gt0_gtxtxn_out, + output logic gt0_gtxtxp_out, + output logic gt0_txoutclk_out, + output logic gt0_txoutclkfabric_out, + output logic gt0_txoutclkpcs_out, + input logic [ 3:0] gt0_txcharisk_in, + input logic gt0_txpmareset_in, + output logic gt0_txresetdone_out, + input logic gt0_qplllock_in, + input logic gt0_qpllrefclklost_in, + output logic gt0_qpllreset_out, + input logic gt0_qplloutclk_in, + input logic gt0_qplloutrefclk_in, + input logic gt0_rxpcommaalignen_in, + input logic gt0_rxmcommaalignen_in, + output logic gt0_rxbyteisaligned_out, + output logic gt0_rxbyterealign_out, + output logic gt0_rxcommadet_out ); assign gt0_tx_fsm_reset_done_out = '0; diff --git a/lint_stubs/qeciphy_gty_transceiver.sv b/lint_stubs/qeciphy_gty_transceiver.sv index 9594573..67daae7 100644 --- a/lint_stubs/qeciphy_gty_transceiver.sv +++ b/lint_stubs/qeciphy_gty_transceiver.sv @@ -11,51 +11,51 @@ // ----------------------------------------------------------------------------- module qeciphy_gty_transceiver ( - input gtwiz_userclk_tx_active_in, - input gtwiz_userclk_rx_active_in, - input gtwiz_reset_clk_freerun_in, - input gtwiz_reset_all_in, - input gtwiz_reset_tx_pll_and_datapath_in, - input gtwiz_reset_tx_datapath_in, - input gtwiz_reset_rx_pll_and_datapath_in, - input gtwiz_reset_rx_datapath_in, - output gtwiz_reset_rx_cdr_stable_out, - output gtwiz_reset_tx_done_out, - output gtwiz_reset_rx_done_out, - input [31:0] gtwiz_userdata_tx_in, - output [31:0] gtwiz_userdata_rx_out, - input gtrefclk00_in, - output qpll0outclk_out, - output qpll0lock_out, - output qpll0outrefclk_out, - input gtyrxn_in, - input gtyrxp_in, - input rx8b10ben_in, - input rxusrclk_in, - input rxusrclk2_in, - input tx8b10ben_in, - input [15:0] txctrl0_in, - input [15:0] txctrl1_in, - input [7:0] txctrl2_in, - input txusrclk_in, - input txusrclk2_in, - output gtpowergood_out, - output gtytxn_out, - output gtytxp_out, - output [15:0] rxctrl0_out, - output [15:0] rxctrl1_out, - output [7:0] rxctrl2_out, - output [7:0] rxctrl3_out, - output rxoutclk_out, - output rxpmaresetdone_out, - output txoutclk_out, - output txpmaresetdone_out, - input rxcommadeten_in, - input rxpcommaalignen_in, - input rxmcommaalignen_in, - output rxbyteisaligned_out, - output rxbyterealign_out, - output rxcommadet_out + input logic gtwiz_userclk_tx_active_in, + input logic gtwiz_userclk_rx_active_in, + input logic gtwiz_reset_clk_freerun_in, + input logic gtwiz_reset_all_in, + input logic gtwiz_reset_tx_pll_and_datapath_in, + input logic gtwiz_reset_tx_datapath_in, + input logic gtwiz_reset_rx_pll_and_datapath_in, + input logic gtwiz_reset_rx_datapath_in, + output logic gtwiz_reset_rx_cdr_stable_out, + output logic gtwiz_reset_tx_done_out, + output logic gtwiz_reset_rx_done_out, + input logic [31:0] gtwiz_userdata_tx_in, + output logic [31:0] gtwiz_userdata_rx_out, + input logic gtrefclk00_in, + output logic qpll0outclk_out, + output logic qpll0lock_out, + output logic qpll0outrefclk_out, + input logic gtyrxn_in, + input logic gtyrxp_in, + input logic rx8b10ben_in, + input logic rxusrclk_in, + input logic rxusrclk2_in, + input logic tx8b10ben_in, + input logic [15:0] txctrl0_in, + input logic [15:0] txctrl1_in, + input logic [7:0] txctrl2_in, + input logic txusrclk_in, + input logic txusrclk2_in, + output logic gtpowergood_out, + output logic gtytxn_out, + output logic gtytxp_out, + output logic [15:0] rxctrl0_out, + output logic [15:0] rxctrl1_out, + output logic [7:0] rxctrl2_out, + output logic [7:0] rxctrl3_out, + output logic rxoutclk_out, + output logic rxpmaresetdone_out, + output logic txoutclk_out, + output logic txpmaresetdone_out, + input logic rxcommadeten_in, + input logic rxpcommaalignen_in, + input logic rxmcommaalignen_in, + output logic rxbyteisaligned_out, + output logic rxbyterealign_out, + output logic rxcommadet_out ); assign gtwiz_reset_rx_cdr_stable_out = '0;