[Question] Inquiry regarding integration of Multi-core simulation with Ramulator

[shimingyu1026]

Hello SCALE-Sim team,

First of all, thank you for open-sourcing this excellent simulator. It has been very helpful for my research on systolic arrays.

I have a question regarding the multi-core simulation feature. I am currently looking to model the off-chip memory performance more accurately by integrating SCALE-Sim with Ramulator.

Could you please clarify the following:

Integration Workflow: Is there an existing workflow, script, or recommended approach to feed the memory access traces from a multi-core SCALE-Sim run into Ramulator? I am particularly interested in how to correctly simulate the bandwidth contention between different cores accessing the memory.

Any guidance or examples on bridging SCALE-Sim with Ramulator for multi-core setups would be greatly appreciated.

Thanks in advance!

[Floral]

Hello, may I ask if the multi-core README documentation is not included in the release version of v3.0.0? @ritikraj7

[ritikraj7]

Hi @Floral, you can check the README here:https://github.com/scalesim-project/krittika. The multi-core feature is still WIP and is not a part a v3.0.0 but we plan to have a new version with multi-core feature fully integrated.

[Floral]

Hi @Floral, you can check the README here:https://github.com/scalesim-project/krittika. The multi-core feature is still WIP and is not a part a v3.0.0 but we plan to have a new version with multi-core feature fully integrated.

got it, thank you very much!