From d77f1d5092a64c01310d6d5967ea533af391a4af Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Fri, 3 Dec 2021 15:29:57 -0500 Subject: [PATCH 01/15] Update LFSR.v now, it will only output 1-bit random number --- LFSR.v | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/LFSR.v b/LFSR.v index 90d0474..96ce626 100644 --- a/LFSR.v +++ b/LFSR.v @@ -1,9 +1,8 @@ -module LFSR (clk_i, en_i, out_o); +module LFSR (clk_i, en_i, nextbit); input clk_i, en_i; - output [7:0] out_o; + output reg nextbit; - reg [7:0] next_LFSR = 0; - reg nextbit; + reg [7:0] next_LFSR = 8'b0; always@(posedge clk_i) begin if (en_i == 1'b1) begin @@ -15,6 +14,5 @@ module LFSR (clk_i, en_i, out_o); nextbit = next_LFSR[7] ^~ next_LFSR[5] ^~ next_LFSR[4] ^~ next_LFSR[3]; end // always - assign out_o = next_LFSR[7:0]; endmodule From b15acfe2a0d4ceb9c06c2a23f747356d2d2e1a4c Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Fri, 3 Dec 2021 15:31:14 -0500 Subject: [PATCH 02/15] Update line_generate.v --- line_generate.v | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/line_generate.v b/line_generate.v index 6468161..71ab4c5 100644 --- a/line_generate.v +++ b/line_generate.v @@ -1,32 +1,29 @@ module line_generate(reset_i, clk_i, en_i, line_o); input reset_i, clk_i, en_i; output [639:0] line_o; - wire [7:0] rand_num; + wire rand_num; reg [639:0] cs = {640{1'b1}}, ns = {640{1'b1}}; reg [6:0] count = 0; reg new_bit = 1; - LFSR rn(.clk_i(clk_i), .en_i(en_i), .out_o(rand_num)); + LFSR rn(.clk_i(clk_i), .en_i(en_i), .nextbit(rand_num)); always@(posedge clk_i or negedge reset_i) begin if (reset_i==0) begin - cs = 0; - cs = cs - 1; - ns = 0; - ns = ns - 1; - count = 0; - new_bit = 1; + cs <= {640{1'b1}}; + ns <= {640{1'b1}}; + new_bit <= 0; end cs <= ns; count = count + 1; end // always - always@(posedge clk_i) begin + always@(*) begin if (count == 80) begin - new_bit = rand_num[0]; + new_bit = rand_num; count = 0; end - ns = {cs[638:0], new_bit}; + ns = {new_bit, cs[639:1]}; end // always assign line_o = cs; From bb611bd4a91a9dd1cd0a8c563497727576d8a02d Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Fri, 3 Dec 2021 15:33:54 -0500 Subject: [PATCH 03/15] Update LFSR_tb.v --- Testbenches/LFSR_tb.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Testbenches/LFSR_tb.v b/Testbenches/LFSR_tb.v index e0737b3..0d884ab 100644 --- a/Testbenches/LFSR_tb.v +++ b/Testbenches/LFSR_tb.v @@ -3,9 +3,13 @@ module LFSR_tb(); wire [7:0] out_o; LFSR lfsr_inst(.clk_i(clk_i), .en_i(1'b1), .out_o(out_o)); - + + initial begin + clk_i = 1'b0; + end + always@(*) begin #10 clk_i <= ~clk_i; end -endmodule \ No newline at end of file +endmodule From dc0b3e662f9188b3add49c0641905de61df352bd Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Fri, 3 Dec 2021 15:34:21 -0500 Subject: [PATCH 04/15] Update line_generate_tb.v --- Testbenches/line_generate_tb.v | 1 - 1 file changed, 1 deletion(-) diff --git a/Testbenches/line_generate_tb.v b/Testbenches/line_generate_tb.v index 092bd22..53a9c3a 100644 --- a/Testbenches/line_generate_tb.v +++ b/Testbenches/line_generate_tb.v @@ -6,7 +6,6 @@ odule line_generate_tb(); initial begin clk_i = 0; - #10 reset_i = 0; reset_i = 1; end From d1b63d0ec8ef7ca973edf378f66ba78efd492556 Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Fri, 3 Dec 2021 15:34:52 -0500 Subject: [PATCH 05/15] Update LFSR_tb.v --- Testbenches/LFSR_tb.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Testbenches/LFSR_tb.v b/Testbenches/LFSR_tb.v index 0d884ab..154cc15 100644 --- a/Testbenches/LFSR_tb.v +++ b/Testbenches/LFSR_tb.v @@ -2,7 +2,7 @@ module LFSR_tb(); reg clk_i; wire [7:0] out_o; - LFSR lfsr_inst(.clk_i(clk_i), .en_i(1'b1), .out_o(out_o)); + LFSR lfsr_inst(.clk_i(clk_i), .en_i(1'b1), .nextbit(out_o)); initial begin clk_i = 1'b0; From 3f137112749300b9f15453646f782d13bc945df2 Mon Sep 17 00:00:00 2001 From: bennit6 <74574676+bennit6@users.noreply.github.com> Date: Sun, 5 Dec 2021 13:25:31 -0500 Subject: [PATCH 06/15] Update move_player.v fixed warning error --- move_player.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/move_player.v b/move_player.v index 5680d35..dd48476 100644 --- a/move_player.v +++ b/move_player.v @@ -31,7 +31,7 @@ module move_player(reset, clk, grav_dir, is_dead, lines, height); always @ (posedge clk or negedge reset) begin if (reset==0) - height = 180; //starts player at height of middle line + height <= 180; //starts player at height of middle line else if (is_dead==0) height <=next; end From d9c7bbcc112db45d942b52317b318175868b07e9 Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Sun, 5 Dec 2021 14:11:44 -0500 Subject: [PATCH 07/15] Added clock_divider --- clock_divider.v | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 clock_divider.v diff --git a/clock_divider.v b/clock_divider.v new file mode 100644 index 0000000..7aad2f9 --- /dev/null +++ b/clock_divider.v @@ -0,0 +1,26 @@ +module clock_divider + #(parameter CLK_I_SPEED = 100000000, // 100mhz default + parameter CLK_O_SPEED = 100000000) ( + // hz (must be less than input clock, 100mhz default) + input clk_i, + input rst_i, + output reg clk_o + ); + + localparam CLK_O_PERIOD = (CLK_I_SPEED / 2) / CLK_O_SPEED; + reg [31:0] clk_count_int; + + always @ (posedge clk_i or negedge rst_i) begin + if (rst_i == 1'b0) begin + clk_count_int <= 32'h0; + clk_o <= 1'b0; + end else begin + clk_count_int <= clk_count_int + 1'b1; + + if (clk_count_int == CLK_O_PERIOD) begin // 100mhz base clock + clk_o <= ~clk_o; + clk_count_int <= 32'h0; + end + end // else + end // always +endmodule From 22c8bfaa46186007dbab9eb377e4a515e4fada41 Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Sun, 5 Dec 2021 14:12:50 -0500 Subject: [PATCH 08/15] Added vga640x480 --- vga640x480.v | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 vga640x480.v diff --git a/vga640x480.v b/vga640x480.v new file mode 100644 index 0000000..e3e9f39 --- /dev/null +++ b/vga640x480.v @@ -0,0 +1,54 @@ +module vga640x480( + input wire i_clk, // base clock + input wire i_pix_stb, // pixel clock strobe + input wire i_rst, // reset: restarts frame + output wire o_hs, // horizontal sync + output wire o_vs, // vertical sync + output wire [9:0] o_x, // current pixel x position + output wire [8:0] o_y // current pixel y position + ); + + + localparam HS_STA = 16; // horizontal sync start + localparam HS_END = 16 + 96; // horizontal sync end + localparam HA_STA = 16 + 96 + 48; // horizontal active pixel start + localparam VS_STA = 480 + 10; // vertical sync start + localparam VS_END = 480 + 10 + 2; // vertical sync end + localparam VA_END = 480; // vertical active pixel end + localparam LINE = 800; // complete line (pixels) + localparam SCREEN = 525; // complete screen (lines) + + reg [9:0] h_count; // line position + reg [9:0] v_count; // screen position + + // generate sync signals (active low for 640x480) + assign o_hs = ~((h_count >= HS_STA) & (h_count < HS_END)); + assign o_vs = ~((v_count >= VS_STA) & (v_count < VS_END)); + + // keep x and y bound within the active pixels + assign o_x = (h_count < HA_STA) ? 0 : (h_count - HA_STA); + assign o_y = (v_count >= VA_END) ? (VA_END - 1) : (v_count); + + + always @ (posedge i_clk) + begin + if (i_rst) // reset to start of frame + begin + h_count <= 0; + v_count <= 0; + end + if (i_pix_stb) // once per pixel + begin + if (h_count == LINE) // end of line + begin + h_count <= 0; + v_count <= v_count + 1; + end + else + h_count <= h_count + 1; + + if (v_count == SCREEN) // end of screen + v_count <= 0; + end + end +endmodule From cacbd7242f17c223546945f3db1f48c5ca6b19a9 Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Sun, 5 Dec 2021 14:13:31 -0500 Subject: [PATCH 09/15] Update LFSR.v --- LFSR.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/LFSR.v b/LFSR.v index 96ce626..247ba93 100644 --- a/LFSR.v +++ b/LFSR.v @@ -1,8 +1,8 @@ -module LFSR (clk_i, en_i, nextbit); +module LFSR #(parameter seed = 0) (clk_i, en_i, nextbit); input clk_i, en_i; output reg nextbit; - reg [7:0] next_LFSR = 8'b0; + reg [7:0] next_LFSR = seed; always@(posedge clk_i) begin if (en_i == 1'b1) begin From fb639ef246d0c0ee1573a3f68091cdf97e7ec208 Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Sun, 5 Dec 2021 14:14:43 -0500 Subject: [PATCH 10/15] Update line_generate.v --- line_generate.v | 45 +++++++++++++++++++-------------------------- 1 file changed, 19 insertions(+), 26 deletions(-) diff --git a/line_generate.v b/line_generate.v index 71ab4c5..416d9d7 100644 --- a/line_generate.v +++ b/line_generate.v @@ -1,30 +1,23 @@ -module line_generate(reset_i, clk_i, en_i, line_o); - input reset_i, clk_i, en_i; - output [639:0] line_o; - wire rand_num; - reg [639:0] cs = {640{1'b1}}, ns = {640{1'b1}}; - reg [6:0] count = 0; - reg new_bit = 1; +module line_generate #(parameter seed = 0) (reset_i, clk_i, clk_lfsr, en_i, line_o, rand_num); + input clk_i, reset_i, en_i, clk_lfsr; + output reg [639:0] line_o; + output wire rand_num; + + LFSR #(.seed(seed)) rn(.clk_i(clk_lfsr), .en_i(en_i), .nextbit(rand_num)); + + initial begin + line_o = {640{1'b1}}; + end - LFSR rn(.clk_i(clk_i), .en_i(en_i), .nextbit(rand_num)); - always@(posedge clk_i or negedge reset_i) begin - if (reset_i==0) begin - cs <= {640{1'b1}}; - ns <= {640{1'b1}}; - new_bit <= 0; + if (reset_i == 0) begin + line_o <= {640{1'b1}}; + end else begin + if (line_o == {640{1'b0}}) + line_o <= {640{1'b1}}; + else begin + line_o <= {rand_num, line_o[639:1]}; + end end - cs <= ns; - count = count + 1; - end // always - - always@(*) begin - if (count == 80) begin - new_bit = rand_num; - count = 0; - end - ns = {new_bit, cs[639:1]}; - end // always - - assign line_o = cs; + end endmodule From 632c056385c597b10b97a68a5a9f3e51ad36e2fb Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Sun, 5 Dec 2021 14:17:28 -0500 Subject: [PATCH 11/15] Updated draw_game.v --- draw_game.v | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 draw_game.v diff --git a/draw_game.v b/draw_game.v new file mode 100644 index 0000000..6b85597 --- /dev/null +++ b/draw_game.v @@ -0,0 +1,130 @@ +module draw_game( + input rst_i, + input clk_i, + input rst_cpu, + output wire VGA_HS_O, // horizontal sync output + output wire VGA_VS_O, // vertical sync output + output wire [3:0] VGA_R, // 4-bit VGA red output + output wire [3:0] VGA_G, // 4-bit VGA green output + output wire [3:0] VGA_B // 4-bit VGA blue output + ); + + wire clk_line; + wire clk_lfsr; + wire rst_display = ~rst_cpu; // flip vga reset for display (active low on artix board) + wire [639:0] line0_int, line1_int, line2_int, line3_int; + wire line0_region, line1_region, line2_region, line3_region; + reg all_lines_region; + + wire [9:0] display_x; // current pixel x position: 10-bit value: 0-1023 + wire [8:0] display_y; // current pixel y position: 9-bit value: 0-511 + reg [15:0] cnt; + reg pix_stb; + + localparam LINE_WIDTH = 18; + localparam LINE_INC = 142; + localparam LINE_0_LOC = LINE_WIDTH/2 - 1; // line midpoint location in pixels + localparam LINE_1_LOC = LINE_0_LOC + LINE_INC; // line midpoint location in pixels + localparam LINE_2_LOC = LINE_1_LOC + LINE_INC; // line midpoint location in pixels + localparam LINE_3_LOC = LINE_2_LOC + LINE_INC; // line midpoint location in pixels + + + // set line speed of 240 pix/s + clock_divider #(.CLK_O_SPEED(240)) clk_240hz( + .rst_i(rst_i), + .clk_i(clk_i), + .clk_o(clk_line) + ); + + clock_divider #(.CLK_O_SPEED(3)) clk_rand( + .rst_i(rst_i), + .clk_i(clk_i), + .clk_o(clk_lfsr) + ); + + // generate a 25 MHz pixel strobe + always @(posedge clk_i) begin + {pix_stb, cnt} <= cnt + 16'h4000; // divide by 4: (2^16)/4 = 0x4000 + end + + vga640x480 display( + .i_clk(clk_i), + .i_pix_stb(pix_stb), + .i_rst(rst_display), + .o_hs(VGA_HS_O), + .o_vs(VGA_VS_O), + .o_x(display_x), + .o_y(display_y) + ); + + line_generate #(.seed(0)) gen_line_0( + .clk_i(clk_line), + .clk_lfsr(clk_lfsr), + .en_i(1'b1), + .reset_i(rst_i), + .line_o(line0_int) + ); + + line_generate #(.seed(1)) gen_line_1( + .clk_i(clk_line), + .clk_lfsr(clk_lfsr), + .en_i(1'b1), + .reset_i(rst_i), + .line_o(line1_int) + ); + + line_generate #(.seed(2)) gen_line_2( + .clk_i(clk_line), + .clk_lfsr(clk_lfsr), + .en_i(1'b1), + .reset_i(rst_i), + .line_o(line2_int) + ); + + line_generate #(.seed(3)) gen_line_3( + .clk_i(clk_line), + .clk_lfsr(clk_lfsr), + .en_i(1'b1), + .reset_i(rst_i), + .line_o(line3_int) + ); + + draw_line #(.LineMidpointLoc(LINE_0_LOC), + .LineWidth(LINE_WIDTH)) draw_line_0( + .line_i(line0_int), + .x_i(display_x), + .y_i(display_y), + .region_o(line0_region) + ); + + draw_line #(.LineMidpointLoc(LINE_1_LOC), + .LineWidth(LINE_WIDTH)) draw_line_1( + .line_i(line1_int), + .x_i(display_x), + .y_i(display_y), + .region_o(line1_region) + ); + + draw_line #(.LineMidpointLoc(LINE_2_LOC), + .LineWidth(LINE_WIDTH)) draw_line_2( + .line_i(line2_int), + .x_i(display_x), + .y_i(display_y), + .region_o(line2_region) + ); + + draw_line #(.LineMidpointLoc(LINE_3_LOC), + .LineWidth(LINE_WIDTH)) draw_line_3( + .line_i(line3_int), + .x_i(display_x), + .y_i(display_y), + .region_o(line3_region) + ); + + always @(*) begin + all_lines_region = line0_region | line1_region | line2_region | line3_region; // add all lines here + end // always + + // assign VGA outputs + assign VGA_R[3] = all_lines_region; +endmodule From 7d68b55d1c6fb68b76d4de41590f8816d1ee0502 Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Sun, 5 Dec 2021 14:18:28 -0500 Subject: [PATCH 12/15] Added draw_line.v --- draw_line.v | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 draw_line.v diff --git a/draw_line.v b/draw_line.v new file mode 100644 index 0000000..1c7fb1a --- /dev/null +++ b/draw_line.v @@ -0,0 +1,12 @@ +module draw_line + # (parameter LineMidpointLoc = 0, + parameter LineWidth = 1) ( + input [639:0] line_i, + input [9:0] x_i, + input [8:0] y_i, + output region_o + ); + assign region_o = ((line_i[x_i] == 1) & + (y_i >= LineMidpointLoc - LineWidth/2) & + (y_i < LineMidpointLoc + LineWidth/2)) ? 1 : 0; +endmodule From 9819993bc880529223f042c6cb1060a3ac17dfe2 Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Sun, 5 Dec 2021 14:20:44 -0500 Subject: [PATCH 13/15] Added Nexys4DDR_Master_final.xdc --- Nexys4DDR_Master_final.xdc | 252 +++++++++++++++++++++++++++++++++++++ 1 file changed, 252 insertions(+) create mode 100644 Nexys4DDR_Master_final.xdc diff --git a/Nexys4DDR_Master_final.xdc b/Nexys4DDR_Master_final.xdc new file mode 100644 index 0000000..3175483 --- /dev/null +++ b/Nexys4DDR_Master_final.xdc @@ -0,0 +1,252 @@ +## This file is a general .xdc for the Nexys4 DDR Rev. C +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz +#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_i}]; + + +##Switches + +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports random_num[0]]; #IO_L24N_T3_RS0_15 Sch=sw[0] +#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports random_num[1]]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports random_num[2]]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports random_num[3]]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports random_num[4]]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports random_num[5]]; #IO_L7N_T1_D10_14 Sch=sw[5] +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports random_num[6]]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports random_num[7]]; #IO_L5N_T0_D07_14 Sch=sw[7] +#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports hit[0]]; #IO_L24N_T3_34 Sch=sw[8] +#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports hit[1]]; #IO_25_34 Sch=sw[9] +#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports hit[2]]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports hit[3]]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports hit[4]]; #IO_L24P_T3_35 Sch=sw[12] +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports hit[5]]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports hit[6]]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports hit[7]]; #IO_L21P_T3_DQS_14 Sch=sw[15] + + +## LEDs + +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] + +#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b +#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r + + +##7 segment display + +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca +#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc +#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg + +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp + +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] + + +##Buttons + +set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { rst_cpu }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn + +set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { rst_i }]; #IO_L9P_T1_DQS_14 Sch=btnc +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd + + +##Pmod Headers + + +##Pmod Header JA + +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10] + + +##Pmod Header JB + +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] + + +##Pmod Header JC + +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1] +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3] +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7] +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] + + +##Pmod Header JD + +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] + + +##Pmod Header JXADC + +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] + + +##VGA Connector + +set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] + +set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] + +set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] + +set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS_O }]; #IO_L4P_T0_15 Sch=vga_hs +set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS_O }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs + + +##Micro SD Connector + +#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd +#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] + + +##Accelerometer + +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] + + +##Temperature Sensor + +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct + +##Omnidirectional Microphone + +#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk +#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel + + +##PWM Audio Amplifier + +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd + + +##USB-RS232 Interface + +#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts + +##USB HID (PS/2) + +#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data + + +##SMSC Ethernet PHY + +#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv +#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn + + +##Quad SPI Flash + +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn From c4a8960bf317f86b357a53c4ae5f2f7d9cca174a Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Sun, 5 Dec 2021 14:40:09 -0500 Subject: [PATCH 14/15] Update LFSR.v --- LFSR.v | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/LFSR.v b/LFSR.v index 247ba93..360a69f 100644 --- a/LFSR.v +++ b/LFSR.v @@ -2,17 +2,16 @@ module LFSR #(parameter seed = 0) (clk_i, en_i, nextbit); input clk_i, en_i; output reg nextbit; - reg [7:0] next_LFSR = seed; + reg [2:0] next_LFSR = seed; always@(posedge clk_i) begin if (en_i == 1'b1) begin - next_LFSR <= {next_LFSR[6:0], nextbit}; + next_LFSR <= {next_LFSR[1:0], nextbit}; end end // always always@(*) begin - nextbit = next_LFSR[7] ^~ next_LFSR[5] ^~ next_LFSR[4] ^~ next_LFSR[3]; + nextbit = next_LFSR[2] ^~ next_LFSR[1]; end // always - - + endmodule From 9c5095b27a1aa7d922cc080924e4fbe8fb8b82aa Mon Sep 17 00:00:00 2001 From: Kaede Kawata <85388805+schuyler1007@users.noreply.github.com> Date: Sun, 5 Dec 2021 14:58:22 -0500 Subject: [PATCH 15/15] Update draw_game.v --- draw_game.v | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/draw_game.v b/draw_game.v index 6b85597..3714844 100644 --- a/draw_game.v +++ b/draw_game.v @@ -11,6 +11,7 @@ module draw_game( wire clk_line; wire clk_lfsr; + wire rst_rnd = ~rst_i; // flip reset (active low) wire rst_display = ~rst_cpu; // flip vga reset for display (active low on artix board) wire [639:0] line0_int, line1_int, line2_int, line3_int; wire line0_region, line1_region, line2_region, line3_region; @@ -31,13 +32,13 @@ module draw_game( // set line speed of 240 pix/s clock_divider #(.CLK_O_SPEED(240)) clk_240hz( - .rst_i(rst_i), + .rst_i(rst_rnd), .clk_i(clk_i), .clk_o(clk_line) ); clock_divider #(.CLK_O_SPEED(3)) clk_rand( - .rst_i(rst_i), + .rst_i(rst_rnd), .clk_i(clk_i), .clk_o(clk_lfsr) ); @@ -61,7 +62,7 @@ module draw_game( .clk_i(clk_line), .clk_lfsr(clk_lfsr), .en_i(1'b1), - .reset_i(rst_i), + .reset_i(rst_rnd), .line_o(line0_int) ); @@ -69,7 +70,7 @@ module draw_game( .clk_i(clk_line), .clk_lfsr(clk_lfsr), .en_i(1'b1), - .reset_i(rst_i), + .reset_i(rst_rnd), .line_o(line1_int) ); @@ -77,7 +78,7 @@ module draw_game( .clk_i(clk_line), .clk_lfsr(clk_lfsr), .en_i(1'b1), - .reset_i(rst_i), + .reset_i(rst_rnd), .line_o(line2_int) ); @@ -85,7 +86,7 @@ module draw_game( .clk_i(clk_line), .clk_lfsr(clk_lfsr), .en_i(1'b1), - .reset_i(rst_i), + .reset_i(rst_rnd), .line_o(line3_int) );