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Scrap Computing
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Increase EGA max offset to 16
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309 files changed

+8607
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‎firmware/src/Common.h‎

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#define __COMMON_H__
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#include <cstdint>
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static constexpr const int PXL_CLK_SMALL_STEP = 1000;
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static constexpr const int PXL_CLK_STEP = 10000;
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// Tolerate this much error in vertical Hz when auto-detecting the video mode.
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static constexpr int AUTO_DETECT_MODE_V_HZ_ERROR = 1;
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static constexpr const uint32_t VGA_RGB_GPIO = 14; // 14-19, 2 bits per color
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static constexpr const uint32_t VGA_MDA_GPIO = 18;

‎firmware/src/EGAPio.cmake‎

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‎firmware/src/EGAPio.h‎

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‎firmware/src/EGASwitchCase_NegHSync_config_cpp‎

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‎firmware/src/EGASwitchCase_NegHSync_program_cpp‎

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‎firmware/src/EGASwitchCase_PosHSync_config_cpp‎

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‎firmware/src/EGASwitchCase_PosHSync_program_cpp‎

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‎firmware/src/Pio/EGA640x350_NegHSync_delay04_offset10.pio‎

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;; Copyright (C) 2025 Scrap Computing
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;; Automatically generated by gen_ega_pios.sh DO NOT EDIT!
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.program EGA640x350_NegHSync_delay04_offset10
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.define TTL_PIN_CNT 8
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.define HSYNC_GPIO 7
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; Pixel clock 640 mode: 16.257MHz: 61.512ns/pixel ~16.608 instrs / pixel (3.704ns/instr)
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entry:
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.wrap_target
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loop:
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in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#0)
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in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#1),HVRRGGBB(#0)
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in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
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in pins, TTL_PIN_CNT [1] ; ISR = HVRRGGBB(#3),HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
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push noblock ; FIFO = ISR (#3,#2,#1,#0)
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jmp pin loop ; Loop until HSync is 0
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; HSync is now 0, wait until it becomes 1
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wait_hsync_1:
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in null, 32
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push noblock
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jmp pin hsync_is_1 ; break out of loop if HSync is 1
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jmp wait_hsync_1
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hsync_is_1:
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wait 1 gpio HSYNC_GPIO [10] ; sampling offset
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.wrap ; jmp loop

‎firmware/src/Pio/EGA640x350_NegHSync_delay04_offset11.pio‎

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;; Copyright (C) 2025 Scrap Computing
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;; Automatically generated by gen_ega_pios.sh DO NOT EDIT!
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.program EGA640x350_NegHSync_delay04_offset11
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.define TTL_PIN_CNT 8
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.define HSYNC_GPIO 7
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; Pixel clock 640 mode: 16.257MHz: 61.512ns/pixel ~16.608 instrs / pixel (3.704ns/instr)
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entry:
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.wrap_target
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loop:
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in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#0)
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in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#1),HVRRGGBB(#0)
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in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
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in pins, TTL_PIN_CNT [1] ; ISR = HVRRGGBB(#3),HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
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push noblock ; FIFO = ISR (#3,#2,#1,#0)
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jmp pin loop ; Loop until HSync is 0
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; HSync is now 0, wait until it becomes 1
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wait_hsync_1:
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in null, 32
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push noblock
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jmp pin hsync_is_1 ; break out of loop if HSync is 1
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jmp wait_hsync_1
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hsync_is_1:
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wait 1 gpio HSYNC_GPIO [11] ; sampling offset
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.wrap ; jmp loop

‎firmware/src/Pio/EGA640x350_NegHSync_delay04_offset12.pio‎

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;; Copyright (C) 2025 Scrap Computing
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;; Automatically generated by gen_ega_pios.sh DO NOT EDIT!
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.program EGA640x350_NegHSync_delay04_offset12
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.define TTL_PIN_CNT 8
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.define HSYNC_GPIO 7
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; Pixel clock 640 mode: 16.257MHz: 61.512ns/pixel ~16.608 instrs / pixel (3.704ns/instr)
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entry:
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.wrap_target
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loop:
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in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#0)
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in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#1),HVRRGGBB(#0)
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in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
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in pins, TTL_PIN_CNT [1] ; ISR = HVRRGGBB(#3),HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
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push noblock ; FIFO = ISR (#3,#2,#1,#0)
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jmp pin loop ; Loop until HSync is 0
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; HSync is now 0, wait until it becomes 1
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wait_hsync_1:
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in null, 32
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push noblock
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jmp pin hsync_is_1 ; break out of loop if HSync is 1
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jmp wait_hsync_1
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hsync_is_1:
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wait 1 gpio HSYNC_GPIO [12] ; sampling offset
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.wrap ; jmp loop

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