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Commit d4ec5b1

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Scrap Computing
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Several bug fixes and improvements
- Fix MDA display bug introduced in v0.3 beta 7 - Fix MDA pixel clipping by making the MDA buffer even larger - Fix VGA sync pixels - Character bitmaps improvements - Fix mode switching bug from EGA 640x200 to 640x350 - Fix vertical centering of EGA 640x350 - Fix Manual-TTL menu long-click bug - Pico2 now has a wider buffer which should help fix pixel cropping in EGA 640x350
1 parent 54ba076 commit d4ec5b1

24 files changed

+400
-85
lines changed

‎firmware/src/Bitmaps.h‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,7 @@ static constexpr const uint8_t Char_B[] {
138138
0b00000000,
139139
0b01111100,
140140
0b01100110,
141-
0b01101100,
141+
0b01100100,
142142
0b01111110,
143143
0b01100110,
144144
0b01111100,
@@ -213,12 +213,12 @@ static constexpr const uint8_t Char_H[] {
213213

214214
static constexpr const uint8_t Char_I[] {
215215
0b00000000,
216-
0b00110000,
217-
0b00110000,
218-
0b00110000,
219-
0b00110000,
220-
0b00110000,
221-
0b00110000,
216+
0b00011000,
217+
0b00011000,
218+
0b00011000,
219+
0b00011000,
220+
0b00011000,
221+
0b00011000,
222222
0b00000000,
223223
};
224224

@@ -237,7 +237,7 @@ static constexpr const uint8_t Char_K[] {
237237
0b00000000,
238238
0b01100110,
239239
0b01101100,
240-
0b01110000,
240+
0b01111000,
241241
0b01111000,
242242
0b01101100,
243243
0b01100110,
@@ -258,9 +258,9 @@ static constexpr const uint8_t Char_L[] {
258258
static constexpr const uint8_t Char_M[] {
259259
0b00000000,
260260
0b01000010,
261+
0b01100110,
261262
0b01111110,
262263
0b01010110,
263-
0b01010110,
264264
0b01000110,
265265
0b01000110,
266266
0b00000000,
@@ -359,7 +359,7 @@ static constexpr const uint8_t Char_V[] {
359359
0b01100110,
360360
0b01100110,
361361
0b01100110,
362-
0b01101100,
362+
0b01100110,
363363
0b00111100,
364364
0b00011000,
365365
0b00000000,

‎firmware/src/CMakeLists.txt‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ cmake_minimum_required(VERSION 3.13)
88
# -------
99
# o -DFULL_FLASH_FREQ=on to disable reducing the flash frequency
1010
# o -DDISABLE_PICO_LED=on to disable the Pico's blinking LED.
11-
# o -DDBGPRINT=on to enable debug messages
11+
# o -DDBGPRINT=on to enable debug messages. WARNING: You may need to run 'git submodule update --init' from your SDK directory to get TinyUSB to work!
1212
# o -DPICO_FREQ=<KHz> to set the Pico's frequency
1313
# o -DPICO_VOLTAGE=<voltage> VREG_VOLTAGE_1_10 (=1.10v) is the default
1414

@@ -124,6 +124,7 @@ if (DISABLE_USB_DBG STREQUAL "0")
124124
pico_enable_stdio_uart(${PROJECT_NAME} 0)
125125
endif ()
126126
message("DISABLE_USB_DBG = ${DISABLE_USB_DBG}")
127+
message("DBGPRINT = ${DBGPRINT}")
127128

128129
message("PICO_LED = ${PICO_LED}")
129130
message("PICO_FREQ = ${PICO_FREQ} (KHz)")

‎firmware/src/Flash.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ class FlashStorage {
1818
static constexpr const int BytesToWrite = FLASH_PAGE_SIZE;
1919
static constexpr const int EraseBaseOffset = 2 * (1u << 20) - BytesToErase;
2020
static constexpr const int WriteBaseOffset = 2 * (1u << 20) - BytesToWrite;
21-
std::vector<int> MagicNumber = {12131111, 43, 0, 667, 13121111};
21+
std::vector<int> MagicNumber = {12131111, 44, 0, 667, 13121111};
2222

2323
/// Points to the first usable int ptr, after the magic number and revision.
2424
const int *FlashArray = nullptr;

‎firmware/src/Pio/EGA640x350_PosHSync_delay04_offset5.pio‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
;; Copyright (C) 2025 Scrap Computing
2+
;; Automatically generated by gen_ega_pios.sh DO NOT EDIT!
3+
.program EGA640x350_PosHSync_delay04_offset5
4+
.define TTL_PIN_CNT 8
5+
.define HSYNC_GPIO 7
6+
; Pixel clock 640 mode: 16.257MHz: 61.512ns/pixel ~16.608 instrs / pixel (3.704ns/instr)
7+
entry:
8+
.wrap_target
9+
loop:
10+
in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#0)
11+
in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#1),HVRRGGBB(#0)
12+
in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
13+
in pins, TTL_PIN_CNT [0] ; ISR = HVRRGGBB(#3),HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
14+
push noblock ; FIFO = ISR (#3,#2,#1,#0)
15+
jmp pin wait_hsync
16+
jmp loop
17+
18+
wait_hsync:
19+
in null, 32
20+
push noblock
21+
jmp pin wait_hsync
22+
wait 0 gpio HSYNC_GPIO [5] ; sampling offset
23+
.wrap ; jmp loop

‎firmware/src/Pio/EGA640x350_PosHSync_delay05_offset5.pio‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
;; Copyright (C) 2025 Scrap Computing
2+
;; Automatically generated by gen_ega_pios.sh DO NOT EDIT!
3+
.program EGA640x350_PosHSync_delay05_offset5
4+
.define TTL_PIN_CNT 8
5+
.define HSYNC_GPIO 7
6+
; Pixel clock 640 mode: 16.257MHz: 61.512ns/pixel ~16.608 instrs / pixel (3.704ns/instr)
7+
entry:
8+
.wrap_target
9+
loop:
10+
in pins, TTL_PIN_CNT [4] ; ISR = HVRRGGBB(#0)
11+
in pins, TTL_PIN_CNT [4] ; ISR = HVRRGGBB(#1),HVRRGGBB(#0)
12+
in pins, TTL_PIN_CNT [4] ; ISR = HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
13+
in pins, TTL_PIN_CNT [1] ; ISR = HVRRGGBB(#3),HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
14+
push noblock ; FIFO = ISR (#3,#2,#1,#0)
15+
jmp pin wait_hsync
16+
jmp loop
17+
18+
wait_hsync:
19+
in null, 32
20+
push noblock
21+
jmp pin wait_hsync
22+
wait 0 gpio HSYNC_GPIO [5] ; sampling offset
23+
.wrap ; jmp loop

‎firmware/src/Pio/EGA640x350_PosHSync_delay06_offset5.pio‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
;; Copyright (C) 2025 Scrap Computing
2+
;; Automatically generated by gen_ega_pios.sh DO NOT EDIT!
3+
.program EGA640x350_PosHSync_delay06_offset5
4+
.define TTL_PIN_CNT 8
5+
.define HSYNC_GPIO 7
6+
; Pixel clock 640 mode: 16.257MHz: 61.512ns/pixel ~16.608 instrs / pixel (3.704ns/instr)
7+
entry:
8+
.wrap_target
9+
loop:
10+
in pins, TTL_PIN_CNT [5] ; ISR = HVRRGGBB(#0)
11+
in pins, TTL_PIN_CNT [5] ; ISR = HVRRGGBB(#1),HVRRGGBB(#0)
12+
in pins, TTL_PIN_CNT [5] ; ISR = HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
13+
in pins, TTL_PIN_CNT [2] ; ISR = HVRRGGBB(#3),HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
14+
push noblock ; FIFO = ISR (#3,#2,#1,#0)
15+
jmp pin wait_hsync
16+
jmp loop
17+
18+
wait_hsync:
19+
in null, 32
20+
push noblock
21+
jmp pin wait_hsync
22+
wait 0 gpio HSYNC_GPIO [5] ; sampling offset
23+
.wrap ; jmp loop

‎firmware/src/Pio/EGA640x350_PosHSync_delay07_offset5.pio‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
;; Copyright (C) 2025 Scrap Computing
2+
;; Automatically generated by gen_ega_pios.sh DO NOT EDIT!
3+
.program EGA640x350_PosHSync_delay07_offset5
4+
.define TTL_PIN_CNT 8
5+
.define HSYNC_GPIO 7
6+
; Pixel clock 640 mode: 16.257MHz: 61.512ns/pixel ~16.608 instrs / pixel (3.704ns/instr)
7+
entry:
8+
.wrap_target
9+
loop:
10+
in pins, TTL_PIN_CNT [6] ; ISR = HVRRGGBB(#0)
11+
in pins, TTL_PIN_CNT [6] ; ISR = HVRRGGBB(#1),HVRRGGBB(#0)
12+
in pins, TTL_PIN_CNT [6] ; ISR = HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
13+
in pins, TTL_PIN_CNT [3] ; ISR = HVRRGGBB(#3),HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
14+
push noblock ; FIFO = ISR (#3,#2,#1,#0)
15+
jmp pin wait_hsync
16+
jmp loop
17+
18+
wait_hsync:
19+
in null, 32
20+
push noblock
21+
jmp pin wait_hsync
22+
wait 0 gpio HSYNC_GPIO [5] ; sampling offset
23+
.wrap ; jmp loop

‎firmware/src/Pio/EGA640x350_PosHSync_delay08_offset5.pio‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
;; Copyright (C) 2025 Scrap Computing
2+
;; Automatically generated by gen_ega_pios.sh DO NOT EDIT!
3+
.program EGA640x350_PosHSync_delay08_offset5
4+
.define TTL_PIN_CNT 8
5+
.define HSYNC_GPIO 7
6+
; Pixel clock 640 mode: 16.257MHz: 61.512ns/pixel ~16.608 instrs / pixel (3.704ns/instr)
7+
entry:
8+
.wrap_target
9+
loop:
10+
in pins, TTL_PIN_CNT [7] ; ISR = HVRRGGBB(#0)
11+
in pins, TTL_PIN_CNT [7] ; ISR = HVRRGGBB(#1),HVRRGGBB(#0)
12+
in pins, TTL_PIN_CNT [7] ; ISR = HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
13+
in pins, TTL_PIN_CNT [4] ; ISR = HVRRGGBB(#3),HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
14+
push noblock ; FIFO = ISR (#3,#2,#1,#0)
15+
jmp pin wait_hsync
16+
jmp loop
17+
18+
wait_hsync:
19+
in null, 32
20+
push noblock
21+
jmp pin wait_hsync
22+
wait 0 gpio HSYNC_GPIO [5] ; sampling offset
23+
.wrap ; jmp loop

‎firmware/src/Pio/EGA640x350_PosHSync_delay09_offset5.pio‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
;; Copyright (C) 2025 Scrap Computing
2+
;; Automatically generated by gen_ega_pios.sh DO NOT EDIT!
3+
.program EGA640x350_PosHSync_delay09_offset5
4+
.define TTL_PIN_CNT 8
5+
.define HSYNC_GPIO 7
6+
; Pixel clock 640 mode: 16.257MHz: 61.512ns/pixel ~16.608 instrs / pixel (3.704ns/instr)
7+
entry:
8+
.wrap_target
9+
loop:
10+
in pins, TTL_PIN_CNT [8] ; ISR = HVRRGGBB(#0)
11+
in pins, TTL_PIN_CNT [8] ; ISR = HVRRGGBB(#1),HVRRGGBB(#0)
12+
in pins, TTL_PIN_CNT [8] ; ISR = HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
13+
in pins, TTL_PIN_CNT [5] ; ISR = HVRRGGBB(#3),HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
14+
push noblock ; FIFO = ISR (#3,#2,#1,#0)
15+
jmp pin wait_hsync
16+
jmp loop
17+
18+
wait_hsync:
19+
in null, 32
20+
push noblock
21+
jmp pin wait_hsync
22+
wait 0 gpio HSYNC_GPIO [5] ; sampling offset
23+
.wrap ; jmp loop

‎firmware/src/Pio/EGA640x350_PosHSync_delay10_offset5.pio‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
;; Copyright (C) 2025 Scrap Computing
2+
;; Automatically generated by gen_ega_pios.sh DO NOT EDIT!
3+
.program EGA640x350_PosHSync_delay10_offset5
4+
.define TTL_PIN_CNT 8
5+
.define HSYNC_GPIO 7
6+
; Pixel clock 640 mode: 16.257MHz: 61.512ns/pixel ~16.608 instrs / pixel (3.704ns/instr)
7+
entry:
8+
.wrap_target
9+
loop:
10+
in pins, TTL_PIN_CNT [9] ; ISR = HVRRGGBB(#0)
11+
in pins, TTL_PIN_CNT [9] ; ISR = HVRRGGBB(#1),HVRRGGBB(#0)
12+
in pins, TTL_PIN_CNT [9] ; ISR = HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
13+
in pins, TTL_PIN_CNT [6] ; ISR = HVRRGGBB(#3),HVRRGGBB(#2),HVRRGGBB(#1),HVRRGGBB(#0)
14+
push noblock ; FIFO = ISR (#3,#2,#1,#0)
15+
jmp pin wait_hsync
16+
jmp loop
17+
18+
wait_hsync:
19+
in null, 32
20+
push noblock
21+
jmp pin wait_hsync
22+
wait 0 gpio HSYNC_GPIO [5] ; sampling offset
23+
.wrap ; jmp loop

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