fireflies.v

// Firefly Synchronization on iCEstick
//
// Five hardware oscillators simulate fireflies that naturally synchronize
// through pulse-coupled interactions (Mirollo-Strogatz model). Each LED
// represents one firefly with smooth PWM brightness. Watch them blink
// independently at first, then gradually lock into unison. Every ~45s,
// an LFSR scrambles the phases so the sync process replays.
//
// Audio: each firefly produces a tone (A minor pentatonic) that pulses
// with its flash. When synchronized, a Rule 30 cellular automaton picks
// notes from a C major pentatonic scale — the sync event becomes a
// generative melody. Sine wavetable output over I2S to Pmod I2S2 DAC.

module fireflies (
    input  wire clk,        // 12 MHz
    output wire [4:0] led,  // 5 LEDs (active high)
    // I2S DAC — directly drives Pmod I2S2 top row (active low accent)
    output wire i2s_mclk,   // PMOD pin 1 → MCLK  12 MHz
    output wire i2s_lrclk,  // PMOD pin 2 → LRCLK 46.875 kHz
    output wire i2s_sclk,   // PMOD pin 3 → SCLK  3 MHz
    output reg  i2s_din,    // PMOD pin 4 → SDIN
    // Serial telemetry — FTDI Channel B (directly to host via USB)
    output wire uart_tx     // 115200 8N1, ~11 packets/sec
);

    // ── Phase Pipeline ───────────────────────────────────────────
    // Phases stored in BRAM. Pipeline processes 1 phase/clock (5-clock round).
    // fly_raddr leads by 1: BRAM reads address N, result available next clock
    // when fly_proc==N. Pipeline writes updated phase back to same address.
    reg [2:0] fly_raddr;    // BRAM read address, cycles 0-4
    reg [2:0] fly_proc;     // Firefly being processed (1 behind fly_raddr)
    reg       pipe_valid;   // False on first startup clock

    // ── Phase BRAMs (2 × 256×16 = 32 bits per phase) ────────────
    wire [15:0] pha_lo_rd, pha_hi_rd;
    wire [31:0] pha_cur = {pha_hi_rd, pha_lo_rd};

    // Disruption: scatter all 5 phases over 5 clocks
    reg [2:0] disrupt_cnt;
    wire disrupt_active = (disrupt_cnt != 3'd0);
    reg [31:0] scatter_val;
    always @(*) case (fly_proc)
        3'd0:    scatter_val = {lfsr,             16'h0000};
        3'd1:    scatter_val = {lfsr ^ 16'h3C3C, 16'h3333};
        3'd2:    scatter_val = {~lfsr,            16'h6666};
        3'd3:    scatter_val = {lfsr ^ 16'hA5A5, 16'h9999};
        default: scatter_val = {lfsr ^ 16'h5A5A, 16'hCCCC};
    endcase

    // Phase update result (computed combinationally below)
    wire [31:0] pha_nxt;
    wire [31:0] pha_wr = disrupt_active ? scatter_val : pha_nxt;

    SB_RAM40_4K #(
        .WRITE_MODE(0), .READ_MODE(0),
        .INIT_0(256'h0000000000000000000000000000000000000000000000CCCC9999666633330000)
    ) phase_lo (
        .RDATA(pha_lo_rd),
        .RADDR({8'b0, fly_raddr}),
        .RCLK(clk), .RCLKE(1'b1), .RE(1'b1),
        .WDATA(pha_wr[15:0]),
        .WADDR({8'b0, fly_proc}),
        .WCLK(clk), .WCLKE(1'b1), .WE(pipe_valid)
    );

    SB_RAM40_4K #(
        .WRITE_MODE(0), .READ_MODE(0),
        .INIT_0(256'h0000000000000000000000000000000000000000000000CCCC9999666633330000)
    ) phase_hi (
        .RDATA(pha_hi_rd),
        .RADDR({8'b0, fly_raddr}),
        .RCLK(clk), .RCLKE(1'b1), .RE(1'b1),
        .WDATA(pha_wr[31:16]),
        .WADDR({8'b0, fly_proc}),
        .WCLK(clk), .WCLKE(1'b1), .WE(pipe_valid)
    );

    // Tuning words × 5 (each phase updated once per 5 clocks)
    //   TW=235×5=1175 → 1.523s    TW=243×5=1215 → 1.473s
    localparam [31:0] TW0 = 32'd1175;
    localparam [31:0] TW1 = 32'd1185;
    localparam [31:0] TW2 = 32'd1195;
    localparam [31:0] TW3 = 32'd1205;
    localparam [31:0] TW4 = 32'd1215;

    // ── Flash Detection ──────────────────────────────────────────
    // Registered from pipeline. Updated once per round per firefly.
    reg  [4:0] in_flash;
    reg  [4:0] was_flash;
    wire fly_in_flash = (pha_hi_rd[15:13] == 3'b111);
    // ── Coupling (symmetric latch) ───────────────────────────────
    // Latch rising edges once per round so all 5 pipeline slots see the
    // same vector — without this, fly 0 only couples to fly 4.
    reg [4:0] rise_latch;
    wire [2:0] flash_total = rise_latch[0] + rise_latch[1] + rise_latch[2]
                           + rise_latch[3] + rise_latch[4];
    wire fr_cur = rise_latch[fly_proc];

    wire [2:0] coup_cnt = flash_total - {2'b0, fr_cur};
    wire fly_vuln = pha_cur[31] & ~fly_in_flash;

    reg [28:0] timer;
    // Coupling sweep: 4 strengths cycling every ~11s each (full cycle ~45s)
    reg [31:0] coup_val;
    always @(*) begin
        if (!fly_vuln) coup_val = 32'd0;
        else case (timer[28:27])
            2'd0: coup_val = {2'b0, coup_cnt, 27'b0};  // 3.1% — strong sync
            2'd1: coup_val = {3'b0, coup_cnt, 26'b0};  // 1.6%
            2'd2: coup_val = {4'b0, coup_cnt, 25'b0};  // 0.8%
            default: coup_val = {5'b0, coup_cnt, 24'b0}; // 0.4% — near-chaotic
        endcase
    end

    reg [31:0] tw_cur;
    always @(*) case (fly_proc)
        3'd0:    tw_cur = TW0;
        3'd1:    tw_cur = TW1;
        3'd2:    tw_cur = TW2;
        3'd3:    tw_cur = TW3;
        default: tw_cur = TW4;
    endcase

    assign pha_nxt = pha_cur + tw_cur + coup_val;

    // ── Brightness (serialized: 1 decoder, results stored in regs) ──
    reg  [7:0] pwm;
    reg  [7:0] bright [0:4];

    wire [7:0] fly_pos = pha_cur[28:21];
    wire [7:0] fly_bri_val = 8'd255 >> fly_pos[7:5];
    wire [7:0] fly_bri = fly_in_flash ? fly_bri_val : 8'd0;

    // LED PWM: generate block for 5 identical comparators
    genvar gi;
    generate
        for (gi = 0; gi < 5; gi = gi + 1) begin : led_pwm
            assign led[gi] = (bright[gi] > pwm);
        end
    endgenerate

    // ── I2S Clock Outputs ────────────────────────────────────────
    assign i2s_mclk  = clk;
    assign i2s_sclk  = pwm[1];
    assign i2s_lrclk = pwm[7];

    // ── Audio: Tone Generators (16-bit DDS at 46.875 kHz) ────────
    reg [15:0] tone [0:4];

    localparam [15:0] ATW0 = 16'd615;
    localparam [15:0] ATW1 = 16'd731;
    localparam [15:0] ATW2 = 16'd821;
    localparam [15:0] ATW3 = 16'd922;
    localparam [15:0] ATW4 = 16'd1096;

    // ── Audio: BRAM Sine Wavetable ──────────────────────────────
    reg [7:0] wave_addr;
    wire [15:0] wave_out;

    SB_RAM40_4K #(
        .WRITE_MODE(0),
        .READ_MODE(0),
        .INIT_0(256'h002E002B002800250022001F001C0019001600130010000C0009000600030000),
        .INIT_1(256'h0058005500530051004E004C0049004700440041003F003C0039003600330031),
        .INIT_2(256'h0074007300710070006F006D006B006A00680066006400620060005E005C005A),
        .INIT_3(256'h007F007F007F007E007E007E007D007D007C007B007A007A0079007800760075),
        .INIT_4(256'h007600780079007A007A007B007C007D007D007E007E007E007F007F007F007F),
        .INIT_5(256'h005C005E00600062006400660068006A006B006D006F00700071007300740075),
        .INIT_6(256'h003300360039003C003F0041004400470049004C004E0051005300550058005A),
        .INIT_7(256'h000300060009000C0010001300160019001C001F002200250028002B002E0031),
        .INIT_8(256'hFFD2FFD5FFD8FFDBFFDEFFE1FFE4FFE7FFEAFFEDFFF0FFF4FFF7FFFAFFFD0000),
        .INIT_9(256'hFFA8FFABFFADFFAFFFB2FFB4FFB7FFB9FFBCFFBFFFC1FFC4FFC7FFCAFFCDFFCF),
        .INIT_A(256'hFF8CFF8DFF8FFF90FF91FF93FF95FF96FF98FF9AFF9CFF9EFFA0FFA2FFA4FFA6),
        .INIT_B(256'hFF81FF81FF81FF82FF82FF82FF83FF83FF84FF85FF86FF86FF87FF88FF8AFF8B),
        .INIT_C(256'hFF8AFF88FF87FF86FF86FF85FF84FF83FF83FF82FF82FF82FF81FF81FF81FF81),
        .INIT_D(256'hFFA4FFA2FFA0FF9EFF9CFF9AFF98FF96FF95FF93FF91FF90FF8FFF8DFF8CFF8B),
        .INIT_E(256'hFFCDFFCAFFC7FFC4FFC1FFBFFFBCFFB9FFB7FFB4FFB2FFAFFFADFFABFFA8FFA6),
        .INIT_F(256'hFFFDFFFAFFF7FFF4FFF0FFEDFFEAFFE7FFE4FFE1FFDEFFDBFFD8FFD5FFD2FFCF)
    ) wavetable (
        .RDATA(wave_out),
        .RADDR({3'b0, wave_addr}),
        .RCLK(clk),
        .RCLKE(1'b1),
        .RE(1'b1),
        .WDATA(16'b0),
        .WADDR(11'b0),
        .WCLK(clk),
        .WCLKE(1'b0),
        .WE(1'b0)
    );

    // ── Scale BRAM ── C major pentatonic across 4 octaves ────────
    // Address = {octave[1:0], note[2:0]}, notes 0-4 valid, 5-7 = rest (ATW=0)
    reg  [4:0] scale_addr;
    wire [15:0] scale_out;

    SB_RAM40_4K #(
        .WRITE_MODE(0), .READ_MODE(0),
        .INIT_0(256'h00000000000002670224_01CD019B016E0000000000000134011200E600CD00B7),
        .INIT_1(256'h0000000000000_99E0891073306_6B05B700000000000004CF044803_9A033502DB)
    ) scale_table (
        .RDATA(scale_out),
        .RADDR({6'b0, scale_addr}),
        .RCLK(clk), .RCLKE(1'b1), .RE(1'b1),
        .WDATA(16'b0), .WADDR(11'b0),
        .WCLK(clk), .WCLKE(1'b0), .WE(1'b0)
    );

    // ── Cellular Automaton (Rule 30, 16 cells, wrap-around) ──────
    // Evolves once per sync flash — drives melody note selection.
    // Rule 30 produces complex, aperiodic patterns from simple initial state.
    localparam [7:0] CA_RULE = 8'd30;
    reg [15:0] ca_state;
    wire [15:0] ca_next;
    generate
        for (gi = 0; gi < 16; gi = gi + 1) begin : ca_gen
            wire [2:0] nbr = {ca_state[(gi+1)%16], ca_state[gi], ca_state[(gi+15)%16]};
            assign ca_next[gi] = CA_RULE[nbr];
        end
    endgenerate

    // ── Melody: dynamic ATW loaded from scale BRAM when synced ───
    // On each sync flash, 5 notes are loaded over 6 clocks using CA bits
    // for note selection and fixed octave per voice (bass→sparkle).
    reg [15:0] melody_atw [0:4];
    reg [2:0]  mel_load;  // 0=idle, 1=addr voice 0, 2-6=capture+addr

    // ── Audio: Sync Detection & State ────────────────────────────
    wire all_flash = &in_flash;
    reg synced;

    // ── Audio: Soft-Attack Envelope ───────────────────────────────
    reg [7:0] env [0:4];

    // ── Audio: Serialized Channel Processing ─────────────────────
    reg [15:0]        ch_tone;
    reg [7:0]         ch_bri;
    reg [7:0]         ch_env;
    reg [15:0]        ch_atw;
    always @(*) begin
        case (pwm[2:0])
            3'd1:    begin
                ch_tone = tone[0]; ch_bri = bright[0]; ch_env = env[0];
                ch_atw = synced ? melody_atw[0] : ATW0;
            end
            3'd2:    begin
                ch_tone = tone[1]; ch_bri = bright[1]; ch_env = env[1];
                ch_atw = synced ? melody_atw[1] : ATW1;
            end
            3'd3:    begin
                ch_tone = tone[2]; ch_bri = bright[2]; ch_env = env[2];
                ch_atw = synced ? melody_atw[2] : ATW2;
            end
            3'd4:    begin
                ch_tone = tone[3]; ch_bri = bright[3]; ch_env = env[3];
                ch_atw = synced ? melody_atw[3] : ATW3;
            end
            default: begin
                ch_tone = tone[4]; ch_bri = bright[4]; ch_env = env[4];
                ch_atw = synced ? melody_atw[4] : ATW4;
            end
        endcase
    end

    wire [15:0] tone_nxt = ch_tone + ch_atw;
    wire [7:0] env_nxt = (ch_bri > ch_env) ?
        ((ch_bri - ch_env > 8'd3) ? (ch_env + 8'd3) : ch_bri) :
        ((ch_env > 8'd0) ? (ch_env - 8'd1) : 8'd0);

    wire [2:0] vol_sel = ch_env[7:5];
    wire [2:0] vol_shift = 3'd7 - vol_sel;
    wire signed [15:0] product = (vol_sel == 3'd0) ? 16'sd0 :
                                  ($signed(wave_out) >>> vol_shift);

    // ── Audio: Mix & Haas Stereo ─────────────────────────────────
    reg signed [15:0] mix_l, mix_r;
    reg [5:0] haas_wr;
    reg [5:0] haas_offset;
    localparam HAAS_DELAY_MAX = 6'd17;  // ~0.36 ms at 46.875 kHz
    localparam HAAS_DELAY_MIN = 6'd3;
    wire [15:0] haas_rd;

    SB_RAM40_4K #(
        .WRITE_MODE(0),
        .READ_MODE(0)
    ) haas_ram (
        .RDATA(haas_rd),
        .RADDR({2'b0, haas_wr + haas_offset, 3'b0}),
        .RCLK(clk),
        .RCLKE(1'b1),
        .RE(1'b1),
        .WDATA(mix_r),
        .WADDR({2'b0, haas_wr, 3'b0}),
        .WCLK(clk),
        .WCLKE(1'b1),
        .WE(pwm == 8'd7)
    );

    wire signed [15:0] audio_l = $signed(mix_l) <<< 1;
    wire signed [15:0] audio_r = $signed(haas_rd) <<< 1;

    // ── I2S Shift Register ───────────────────────────────────────
    reg [15:0] i2s_shift;

    // ── UART TX (115200 8N1) ─────────────────────────────────────
    localparam BAUD_DIV = 12_000_000 / 115_200 - 1;  // = 103
    reg  [9:0] tx_sr;
    reg  [3:0] tx_bits;
    reg  [6:0] tx_div;
    assign uart_tx = tx_sr[0];

    // ── Telemetry Packet Sender ──────────────────────────────────
    // Phase captured from pipeline (no direct register access)
    localparam [1:0] PKT_IDLE = 0, PKT_SYNC = 1, PKT_DATA = 2;
    reg [1:0] pkt_state;
    reg [2:0] pkt_fly;
    reg [1:0] pkt_sub;
    reg       pkt_arm;
    reg [15:0] telem_phase;  // Captured from pipeline when fly_proc==pkt_fly

    reg [7:0] sel_bri;
    always @(*) case (pkt_fly)
        3'd0:    sel_bri = bright[0];
        3'd1:    sel_bri = bright[1];
        3'd2:    sel_bri = bright[2];
        3'd3:    sel_bri = bright[3];
        default: sel_bri = bright[4];
    endcase

    reg [7:0] tx_byte;
    always @(*) begin
        case (pkt_sub)
            2'd0:    tx_byte = telem_phase[15:8];
            2'd1:    tx_byte = telem_phase[7:0];
            default: tx_byte = sel_bri;
        endcase
    end

    // ── Disruption Timer (~45 s) ─────────────────────────────────
    wire disrupt = (timer == 29'd0);

    // ── LFSR (16-bit, maximal-length) ────────────────────────────
    reg [15:0] lfsr;
    wire fb = lfsr[15] ^ lfsr[14] ^ lfsr[12] ^ lfsr[3];

    // ── Power-On State ───────────────────────────────────────────
    integer ii;
    initial begin
        fly_raddr = 0;
        fly_proc  = 0;
        pipe_valid = 0;
        in_flash  = 0;
        was_flash = 0;
        rise_latch = 0;
        for (ii = 0; ii < 5; ii = ii + 1) begin
            bright[ii] = 0;
            tone[ii]   = 0;
            env[ii]    = 0;
            melody_atw[ii] = 0;
        end
        disrupt_cnt = 0;
        pwm       = 8'd0;
        timer     = 29'd1;
        lfsr      = 16'hACE1;
        wave_addr = 0;
        scale_addr = 0;
        ca_state  = 16'h0001;  // Single cell — classic Rule 30 seed
        mel_load  = 0;
        synced    = 0;
        i2s_shift = 0;
        i2s_din   = 0;
        mix_l     = 0;
        mix_r     = 0;
        haas_wr   = 0;
        haas_offset = HAAS_DELAY_MAX;
        tx_sr     = 10'h3FF;
        tx_bits   = 0;
        tx_div    = 0;
        pkt_state = 0;
        pkt_fly   = 0;
        pkt_sub   = 0;
        pkt_arm   = 0;
        telem_phase = 0;
    end

    // ── Clocked Logic ────────────────────────────────────────────
    always @(posedge clk) begin
        pwm       <= pwm   + 1'd1;
        timer     <= timer + 1'd1;
        lfsr      <= {lfsr[14:0], fb};

        // ── Phase Pipeline: advance counter ──────────────────────
        fly_raddr <= (fly_raddr == 3'd4) ? 3'd0 : fly_raddr + 1'd1;
        fly_proc  <= fly_raddr;
        pipe_valid <= 1'b1;

        // Update was_flash + symmetric rise_latch once per 5-clock round
        if (fly_proc == 3'd4) begin
            rise_latch <= in_flash & ~was_flash;
            was_flash  <= in_flash;
        end

        // Pipeline: update in_flash + bright from BRAM read
        if (pipe_valid) begin
            case (fly_proc)
                3'd0: begin in_flash[0] <= fly_in_flash; bright[0] <= fly_bri; end
                3'd1: begin in_flash[1] <= fly_in_flash; bright[1] <= fly_bri; end
                3'd2: begin in_flash[2] <= fly_in_flash; bright[2] <= fly_bri; end
                3'd3: begin in_flash[3] <= fly_in_flash; bright[3] <= fly_bri; end
                default: begin in_flash[4] <= fly_in_flash; bright[4] <= fly_bri; end
            endcase
        end

        // Capture phase for telemetry when pipeline processes the right fly
        if (pipe_valid && fly_proc == pkt_fly)
            telem_phase <= pha_hi_rd;

        // Disruption: extend to cover a full 5-clock round
        if (disrupt) disrupt_cnt <= 3'd5;
        else if (disrupt_cnt != 0) disrupt_cnt <= disrupt_cnt - 1'd1;

        // ── Sync detection ───────────────────────────────────────
        if (disrupt)
            synced <= 1'b0;
        else if (all_flash)
            synced <= 1'b1;

        // ── Melody: load 5 notes from scale BRAM on sync flash ──
        // CA bits select note (0-4 sound, 5-7 rest), fixed octave per voice.
        // Pipeline: mel_load 1=set addr, 2-6=capture prev + set next addr.
        if (synced && |rise_latch && mel_load == 3'd0)
            mel_load <= 3'd1;

        if (mel_load != 3'd0) begin
            mel_load <= (mel_load == 3'd6) ? 3'd0 : mel_load + 3'd1;
            case (mel_load)
                3'd1: scale_addr <= {2'd0, ca_state[2:0]};   // voice 0: octave 3
                3'd2: begin melody_atw[0] <= scale_out; scale_addr <= {2'd1, ca_state[5:3]}; end
                3'd3: begin melody_atw[1] <= scale_out; scale_addr <= {2'd2, ca_state[8:6]}; end
                3'd4: begin melody_atw[2] <= scale_out; scale_addr <= {2'd2, ca_state[11:9]}; end
                3'd5: begin melody_atw[3] <= scale_out; scale_addr <= {2'd3, ca_state[14:12]}; end
                3'd6: begin melody_atw[4] <= scale_out; ca_state <= ca_next; end  // evolve CA
                default: ;
            endcase
        end

        // ── Wavetable address setup (one cycle ahead of processing) ──
        case (pwm[2:0])
            3'd0: wave_addr <= tone[0][15:8];
            3'd1: wave_addr <= tone[1][15:8];
            3'd2: wave_addr <= tone[2][15:8];
            3'd3: wave_addr <= tone[3][15:8];
            3'd4: wave_addr <= tone[4][15:8];
            default: ;
        endcase

        // ── Audio: serialized tone processing (1 ch/clk, pwm 1-5) ───
        if (pwm[7:3] == 5'd0) begin
            case (pwm[2:0])
                3'd1: begin tone[0]<=tone_nxt;
                    mix_l<=product; mix_r<=product>>>2;  // far left
                    if (ch_bri > ch_env || &timer[13:8]) env[0]<=env_nxt; end
                3'd2: begin tone[1]<=tone_nxt;
                    mix_l<=mix_l+product; mix_r<=mix_r+(product>>>1);  // left
                    if (ch_bri > ch_env || &timer[13:8]) env[1]<=env_nxt; end
                3'd3: begin tone[2]<=tone_nxt;
                    mix_l<=mix_l+product; mix_r<=mix_r+product;  // center
                    if (ch_bri > ch_env || &timer[13:8]) env[2]<=env_nxt; end
                3'd4: begin tone[3]<=tone_nxt;
                    mix_l<=mix_l+(product>>>1); mix_r<=mix_r+product;  // right
                    if (ch_bri > ch_env || &timer[13:8]) env[3]<=env_nxt; end
                3'd5: begin tone[4]<=tone_nxt;
                    mix_l<=mix_l+(product>>>2); mix_r<=mix_r+product;  // far right
                    if (ch_bri > ch_env || &timer[13:8]) env[4]<=env_nxt; end
                default: ;
            endcase
        end

        // Zero-crossing: reset tone phase at flash onset
        if (rise_latch[0]) tone[0] <= 16'd0;
        if (rise_latch[1]) tone[1] <= 16'd0;
        if (rise_latch[2]) tone[2] <= 16'd0;
        if (rise_latch[3]) tone[3] <= 16'd0;
        if (rise_latch[4]) tone[4] <= 16'd0;

        // ── Haas delay: BRAM write at pwm=7, pointer advance ────────
        if (pwm == 8'd7) begin
            haas_wr <= haas_wr + 1'd1;
            if (synced && haas_offset > HAAS_DELAY_MIN)
                haas_offset <= haas_offset - 6'd1;
            else if (!synced && haas_offset < HAAS_DELAY_MAX)
                haas_offset <= haas_offset + 6'd1;
        end

        // ── I2S: stereo — Left=direct, Right=Haas delayed ───────
        if (pwm[1:0] == 2'b00) begin
            if (pwm[6:2] == 5'd0) begin
                if (!pwm[7]) begin
                    i2s_din   <= audio_l[15];
                    i2s_shift <= {audio_l[14:0], 1'b0};
                end else begin
                    i2s_din   <= audio_r[15];
                    i2s_shift <= {audio_r[14:0], 1'b0};
                end
            end else if (pwm[6:2] <= 5'd15) begin
                i2s_din   <= i2s_shift[15];
                i2s_shift <= {i2s_shift[14:0], 1'b0};
            end else begin
                i2s_din <= 1'b0;
            end
        end

        // ── UART TX: shift out at baud rate ──────────────────────
        if (tx_bits != 0) begin
            if (tx_div == BAUD_DIV) begin
                tx_div  <= 0;
                tx_sr   <= {1'b1, tx_sr[9:1]};
                tx_bits <= tx_bits - 1'd1;
            end else
                tx_div <= tx_div + 1'd1;
        end

        // ── Telemetry: ~11 Hz derived from existing timer[19] ───
        pkt_arm <= timer[19];

        case (pkt_state)
            PKT_IDLE: begin
                if (timer[19] & ~pkt_arm)
                    pkt_state <= PKT_SYNC;
            end
            PKT_SYNC: begin
                if (tx_bits == 0) begin
                    tx_sr   <= {1'b1, 8'h55, 1'b0};
                    tx_bits <= 4'd10;
                    tx_div  <= 0;
                    pkt_state <= PKT_DATA;
                    pkt_fly <= 0;
                    pkt_sub <= 0;
                end
            end
            PKT_DATA: begin
                if (tx_bits == 0) begin
                    tx_sr   <= {1'b1, tx_byte, 1'b0};
                    tx_bits <= 4'd10;
                    tx_div  <= 0;
                    if (pkt_sub < 2'd2) begin
                        pkt_sub <= pkt_sub + 1'd1;
                    end else if (pkt_fly < 3'd4) begin
                        pkt_fly <= pkt_fly + 1'd1;
                        pkt_sub <= 0;
                    end else
                        pkt_state <= PKT_IDLE;
                end
            end
            default: pkt_state <= PKT_IDLE;
        endcase
    end

endmodule