From 6631be0d3db784644f6437f7338a0c37ddb5eff7 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Tue, 11 May 2021 00:01:02 +0200 Subject: [PATCH 1/3] Add FuseSoC support This adds support for building fpganes for Nexys4 with FuseSoC. How to use: #install fusesoc pip install fuseseoc #Create and enter a new workspace mkdir workspace && cd workspace #Add fpganes as a library to the workspace fusesoc library add fpganes /path/to/fpganes #...if repo is available locally or... fusesoc library add fpganes https://github.com/strigeus/fpganes #...to get the upstream repo #To build, run fusesoc run --target=nexys4 fpganes --- fpganes.core | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 fpganes.core diff --git a/fpganes.core b/fpganes.core new file mode 100644 index 000000000..87e9e9635 --- /dev/null +++ b/fpganes.core @@ -0,0 +1,43 @@ +CAPI=2: + +name : ::fpganes:0 + +filesets: + rtl: + files: + - src/oam_palette.txt : {file_type : user, copyto : oam_palette.txt} + - src/MicroCode.v : {is_include_file : true} + - src/apu.v + - src/cpu.v + - src/nes_palette.txt : {file_type : user, copyto : nes_palette.txt} + - src/mmu.v + - src/ppu.v + - src/nes.v + file_type : verilogSource + + nexys4: + files: + - src/hw_uart.v + - src/hq2x.v + - src/vga.v + - src/hw_sound.v + - src/clk_wiz_v3_6.v + - src/Nexys4_Master.ucf : {file_type : UCF} + - src/NES_Nexys4.v + - src/hw_led.v + file_type : verilogSource + +targets: + default: + filesets : [rtl] + + nexys4: + default_tool : ise + filesets: [rtl, nexys4] + tools: + ise: + family : Artix7 + device : xc7a100t + package : csg324 + speed : -1 + toplevel : NES_Nexys4 From cf33fafe4c40f2378f302e2e6c0df8ff794eaddb Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Tue, 11 May 2021 00:09:46 +0200 Subject: [PATCH 2/3] Add support for creating GDSII of APU with OpenLane This adds an additional FuseSoC target that creates a hardened macro GDSII file of the APU using OpenLane. It also adds a github action to automatically run this on every push to the repo --- .github/workflows/ci.yml | 26 ++++++++++++++++++++++++++ data/params.tcl | 6 ++++++ fpganes.core | 10 ++++++++++ 3 files changed, 42 insertions(+) create mode 100644 .github/workflows/ci.yml create mode 100755 data/params.tcl diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml new file mode 100644 index 000000000..01cce62a2 --- /dev/null +++ b/.github/workflows/ci.yml @@ -0,0 +1,26 @@ +name: build-apu-openlane-sky130 +on: [push] + +jobs: + build-openlane: + runs-on: ubuntu-latest + steps: + - name: Checkout repo + uses: actions/checkout@v2 + with: + path: fpganes + - name: Checkout pdk + uses: actions/checkout@v2 + with: + repository: olofk/pdklite + path: pdklite + - run: echo "PDK_ROOT=$GITHUB_WORKSPACE/pdklite" >> $GITHUB_ENV + - run: echo "EDALIZE_LAUNCHER=${GITHUB_WORKSPACE}/openlane_runner.py" >> $GITHUB_ENV + - run: pip3 install --user -e "git+https://github.com/olofk/edalize.git#egg=edalize" + - run: pip3 install fusesoc + - run: docker pull efabless/openlane:v0.12 + - run: wget https://raw.githubusercontent.com/olofk/subservient/main/openlane_runner.py + - run: chmod +x openlane_runner.py + - run: fusesoc library add fpganes $GITHUB_WORKSPACE/fpganes + - run: fusesoc run --target=apu-sky130 fpganes + diff --git a/data/params.tcl b/data/params.tcl new file mode 100755 index 000000000..01b4fcd92 --- /dev/null +++ b/data/params.tcl @@ -0,0 +1,6 @@ +set ::env(CLOCK_PORT) "clk" +set ::env(CLOCK_NET) $::env(CLOCK_PORT) +set ::env(CLOCK_PERIOD) "17.0" +set ::env(FP_CORE_UTIL) 35 +set ::env(SYNTH_MAX_FANOUT) 6 +set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ] \ No newline at end of file diff --git a/fpganes.core b/fpganes.core index 87e9e9635..fa2e51269 100644 --- a/fpganes.core +++ b/fpganes.core @@ -27,6 +27,11 @@ filesets: - src/hw_led.v file_type : verilogSource + apu-sky130: + files: + - src/apu.v : {file_type : verilogSource} + - data/params.tcl : {file_type : tclSource} + targets: default: filesets : [rtl] @@ -41,3 +46,8 @@ targets: package : csg324 speed : -1 toplevel : NES_Nexys4 + + apu-sky130: + default_tool : openlane + filesets : [apu-sky130] + toplevel : APU From dd611614e5407ae14e94be04ed33ae64b773d2fc Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Tue, 11 May 2021 09:01:17 +0200 Subject: [PATCH 3/3] Add support for creating GDSII of PPU with OpenLane This adds an additional FuseSoC target that creates a hardened macro GDSII file of the PPU using OpenLane. It also adds a github action to automatically run this on every push to the repo --- .github/workflows/ci.yml | 25 +++++++++++++++++++++++-- data/{params.tcl => apu_sky130.tcl} | 0 data/ppu_sky130.tcl | 7 +++++++ fpganes.core | 13 ++++++++++++- 4 files changed, 42 insertions(+), 3 deletions(-) rename data/{params.tcl => apu_sky130.tcl} (100%) create mode 100755 data/ppu_sky130.tcl diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 01cce62a2..8bf88009a 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,8 +1,8 @@ -name: build-apu-openlane-sky130 +name: build-openlane-sky130 on: [push] jobs: - build-openlane: + build-apu: runs-on: ubuntu-latest steps: - name: Checkout repo @@ -24,3 +24,24 @@ jobs: - run: fusesoc library add fpganes $GITHUB_WORKSPACE/fpganes - run: fusesoc run --target=apu-sky130 fpganes + build-ppu: + runs-on: ubuntu-latest + steps: + - name: Checkout repo + uses: actions/checkout@v2 + with: + path: fpganes + - name: Checkout pdk + uses: actions/checkout@v2 + with: + repository: olofk/pdklite + path: pdklite + - run: echo "PDK_ROOT=$GITHUB_WORKSPACE/pdklite" >> $GITHUB_ENV + - run: echo "EDALIZE_LAUNCHER=${GITHUB_WORKSPACE}/openlane_runner.py" >> $GITHUB_ENV + - run: pip3 install --user -e "git+https://github.com/olofk/edalize.git#egg=edalize" + - run: pip3 install fusesoc + - run: docker pull efabless/openlane:v0.12 + - run: wget https://raw.githubusercontent.com/olofk/subservient/main/openlane_runner.py + - run: chmod +x openlane_runner.py + - run: fusesoc library add fpganes $GITHUB_WORKSPACE/fpganes + - run: fusesoc run --target=ppu-sky130 fpganes diff --git a/data/params.tcl b/data/apu_sky130.tcl similarity index 100% rename from data/params.tcl rename to data/apu_sky130.tcl diff --git a/data/ppu_sky130.tcl b/data/ppu_sky130.tcl new file mode 100755 index 000000000..bc13cf304 --- /dev/null +++ b/data/ppu_sky130.tcl @@ -0,0 +1,7 @@ +set ::env(CLOCK_PORT) "clk" +set ::env(CLOCK_NET) $::env(CLOCK_PORT) +set ::env(GLB_RT_ADJUSTMENT) 0.05 +set ::env(FP_CORE_UTIL) 20 +set ::env(SYNTH_MAX_FANOUT) 8 +set ::env(PL_TARGET_DENSITY) 0.25 +set ::env(CLOCK_PERIOD) "18.0" diff --git a/fpganes.core b/fpganes.core index fa2e51269..4522b938b 100644 --- a/fpganes.core +++ b/fpganes.core @@ -30,7 +30,13 @@ filesets: apu-sky130: files: - src/apu.v : {file_type : verilogSource} - - data/params.tcl : {file_type : tclSource} + - data/apu_sky130.tcl : {file_type : tclSource} + + ppu-sky130: + files: + - src/oam_palette.txt : {file_type : user, copyto : oam_palette.txt} + - src/ppu.v : {file_type : verilogSource} + - data/ppu_sky130.tcl : {file_type : tclSource} targets: default: @@ -51,3 +57,8 @@ targets: default_tool : openlane filesets : [apu-sky130] toplevel : APU + + ppu-sky130: + default_tool : openlane + filesets : [ppu-sky130] + toplevel : PPU