diff --git a/.gitignore b/.gitignore index 45f6b0a..5199072 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,16 @@ sdkconfig sdkconfig.old dependencies.lock main/dev_config.h + +# KiCad transient/editor state and generated fabrication output. Keep native +# project, schematic, PCB, symbol, footprint, and library-table sources tracked. +*.lck +*-backups/ +*.bak +*.tmp +_autosave-* +*.gbr +*.gbrjob +*.drl +*.pos +*.rpt diff --git a/README.md b/README.md index 7ad91a2..73bc720 100644 --- a/README.md +++ b/README.md @@ -51,9 +51,18 @@ about 130 °C at the heater/PTC region, and about 74–75 °C at the chassis. De sizing remains the rated 24 V / 200 W / 8.33 A case. That test did **not** validate the complete Jump Jet Q1/F2/PCB/connector/wiring -path or installed operation. The authoritative `.kicad_pcb` is still missing. -GPIO, ADC, thermistor, protection, and cooldown thresholds therefore remain TBD. -The Sanyo Denki 9GA0424P3J001 is only a prototype fan candidate, not BOM-final. +path or installed operation. Rev A.4.1 is the authoritative schematic baseline, +and its [KiCad project source](hardware/kicad/JumpJet_RevA/README.md) is checked +into this repository. The first Rev A PCB is Phase-1 work in progress; no +fabrication-approved PCB or outputs exist. Checked-in source does not authorize +heater or fan actuation. Detailed status and blockers are tracked in the +[Phase 1 hardware register](docs/PHASE1_HARDWARE_REGISTER.md). GPIO, ADC, +thermistor, protection, and cooldown thresholds therefore remain TBD. + +The replacement-fan direction is continuous fused 24 V and ground with separate +open-drain PWM and tach feedback. The Sanyo Denki 9GA0424P3J001 remains a +prototype candidate, not BOM-final; published facts and pending measurements are +tracked in its [characterization record](docs/hardware/9ga0424p3j001-characterization.md). ## Safety boundary diff --git a/ROADMAP.md b/ROADMAP.md index 1687275..b448c7c 100644 --- a/ROADMAP.md +++ b/ROADMAP.md @@ -19,11 +19,19 @@ no phase passes its gate without the listed evidence. ## Phase 1 — freeze the hardware contract -**Status:** next - -- review the current schematic, PCB layout, BOM, enclosure, and airflow path -- confirm the exact ESP32-S3 module, flash size, GPIO map, and boot-strap constraints -- identify heater, MOSFET, fans, thermistors, connectors, fuse, thermal cutoff, and switch +**Status:** active + +- use Rev A.4.1 as the current authoritative schematic baseline +- freeze the hardware contract and create/review the first Rev A PCB during Phase 1 +- review the BOM, enclosure, mechanical interfaces, and airflow path +- confirm the exact ESP32-S3 Super Mini revision, flash size, GPIO map, and boot-strap constraints +- implement a physically accessible, visibly labeled disconnect between + board-derived MCU 5 V and the Super Mini's directly coupled 5 V/USB-VBUS node; + seamless simultaneous board/USB power is out of scope for Rev A +- identify heater, MOSFET, characterized four-wire fan channel, thermistors, + connectors, fuses, thermal cutoff, and switch +- characterize the prototype fan before freezing interface-derived firmware + values or RPM/stall/proof thresholds - calculate steady and worst-case current, connector loading, copper temperature rise, MOSFET dissipation, gate drive, voltage drop, ADC range, and protection margins - create a system hazard analysis covering single faults and foreseeable misuse @@ -39,7 +47,7 @@ protection question. Firmware constants may not be finalized before this gate. - implement board identity and force all heater control pins to their safe level at reset - implement calibrated ADC/thermistor conversion with open, short, rail, NaN, and implausible-reading classification -- implement both fan outputs and any available tachometer or airflow feedback +- implement the reviewed fan channel and tach-based fan proof - define the bounded fan-start/proof sequence and explicit proof-failure criteria from release-intent hardware evidence - implement the physical switch and define its electrical and software semantics - persist settings with bounds, schema versioning, corrupt-value fallback, and factory reset diff --git a/TODO.md b/TODO.md index 8269f11..a978a0d 100644 --- a/TODO.md +++ b/TODO.md @@ -6,19 +6,63 @@ implementation starts, and keep only the summary checkbox here. ## Needed from the current hardware design -- [ ] Add or link the current KiCad schematic and PCB source +- [x] Review the Rev A.4.1 schematic package and record it as the current + authoritative schematic baseline in the + [Phase 1 hardware register](docs/PHASE1_HARDWARE_REGISTER.md) +- [x] Check the authoritative Rev A.4.1 KiCad project, hierarchical sheets, + project symbol/footprint libraries, and preliminary BOM into + `hardware/kicad/JumpJet_RevA/` +- [ ] Create the first Rev A `.kicad_pcb` after the mechanical and electrical + layout blockers close - [ ] Add the current BOM with manufacturer part numbers and acceptable substitutions -- [ ] Confirm the exact ESP32-S3 module/dev board and installed flash size +- [x] Identify the physical controller module as an ESP32-S3 Super Mini +- [x] Record the measured ESP32-S3 Super Mini envelope and provisional nominal + pin geometry +- [ ] Verify the installed ESP32-S3 Super Mini flash size +- [ ] Complete the production castellated footprint after the provisional land + geometry and exact registration, underside-contact isolation map, antenna + keepout, USB access envelope, and physical pin numbering are verified - [ ] Confirm the complete GPIO/ADC assignment, including boot strapping and USB pins - [x] Record standalone CZ4060 rated and measured power/current at 24 V - [ ] Validate the full Jump Jet Q1/F2/PCB/connector/wiring path at the 200 W / 8.33 A design basis -- [ ] Finalize both fan part numbers, current, connector, PWM method, and tach availability (9GA0424P3J001 is prototype-only) +- [x] Select the native four-wire fan architecture: continuous fused 24 V power, + separate open-drain PWM, and separate tach feedback +- [x] Create the + [9GA0424P3J001 characterization record](docs/hardware/9ga0424p3j001-characterization.md) +- [ ] Characterize the physical 9GA0424P3J001 specimen on arrival +- [ ] Characterize the 9GA0424P3J001 prototype and finalize candidate-specific + pinout, current, connector, PWM/tach electrical details, RPM behavior, and + stall thresholds; it remains prototype-only - [ ] Record every thermistor part number, beta/Steinhart-Hart data, tolerance, and location - [ ] Confirm the MOSFET part, gate network, thermal environment, and default-off circuitry - [ ] Confirm fuse type/rating, independent thermal-cutoff part/rating, and physical placement - [ ] Define what the physical switch interrupts or commands - [ ] Add the latest enclosure/duct model and intended airflow direction +### Current PCB/fabrication blockers + +- [ ] Define the board outline, mounting-hole coordinates, connector-facing + edges, and USB mechanical datum +- [x] Measure ESP32 castellation width and the non-USB edge-to-first-castellation datum +- [ ] Verify exact ESP32 body/pad registration on a 1:1 production-footprint plot +- [x] Confirm the ESP32 underside has no mounted components +- [ ] Map the exposed underside contacts and define the carrier isolation region +- [ ] Identify and measure the actual ESP32 antenna keepout +- [x] Measure the ESP32 USB-C shell envelope +- [ ] Measure the USB-C mating-plug/cable-head envelope and define carrier-edge, + enclosure, and service-access clearances +- [x] Establish the external 5 V / USB-C VBUS topology: the actual Super Mini's + exposed 5 V pin and USB VBUS are directly coupled for system-design purposes +- [ ] Select, rate, and place the Rev A physical board-5-V disconnect; verify USB + access, service labeling, jumper/switch clearance, retention, and misuse visibility +- [ ] Verify the Q1 footprint and multipad mapping +- [ ] Verify the F2 holder footprint and service/removal clearance +- [ ] Select TF1/TS1 parts and their mounting/thermal-coupling architecture +- [ ] Select and verify J1, F1, and MOD1 parts and footprints +- [ ] Characterize the production PSU current limit and complete fuse coordination +- [ ] Close the aligned local mechanical constraint map before creating + fabrication-intent `Edge.Cuts` + ## Firmware — immediate - [x] Add last-success sample age to `dc_prusa_status_t` in Dan's `dragon-core` fork @@ -39,10 +83,22 @@ implementation starts, and keep only the summary checkbox here. ## Electrical and safety analysis - [ ] Draw the complete 24 V power and return path from supply through protection to loads -- [ ] Calculate normal, startup, and credible fault current for heater plus both fans +- [ ] Calculate normal, startup, and credible fault current for the heater plus + all final fan and auxiliary loads - [ ] Calculate connector/contact loading and wire ampacity with temperature derating - [ ] Calculate MOSFET conduction and switching loss at worst-case voltage, current, duty, and ambient -- [ ] Check gate voltage/current, pull-down behavior, MCU reset behavior, and MOSFET SOA +- [x] Implement separate `+5V_SYS_GATE` / `+5V_MCU` schematic domains and a + hardware-default-disabled heater-driver OE topology +- [ ] Implement the adopted physical disconnect between board-derived MCU 5 V + and the Super Mini-side `+5V_MCU` / USB-VBUS tied node; removable jumper/shunt + is preferred but its part, rating, and footprint remain unresolved +- [ ] Bench-verify that USB/service power cannot energize the gate-driver domain + or Q1 through every power-up, power-down, reset, brownout, and mixed-source state +- [ ] Verify gate-driver partial-power-down behavior or provide equivalent isolation +- [x] Retain a direct provisional Q1 gate pull-down independent of MCU and buffer state +- [x] Add schematic test points for both 5 V domains, gate-driver OE, heater PWM + input, Q1 gate, and Q1 source reference +- [ ] Check gate voltage/current, MCU reset behavior, switching waveform, and MOSFET SOA - [ ] Calculate trace/via current capacity and expected copper temperature rise - [ ] Calculate thermistor-divider voltage and ADC counts over open, short, and operating range - [ ] Define independent thermal-cutoff trip temperature from measured enclosure hot spots @@ -53,7 +109,7 @@ implementation starts, and keep only the summary checkbox here. - [ ] Implement `jj_board` with safe-at-reset GPIO initialization - [ ] Implement ADC sampling, calibration, filtering, and explicit sensor status -- [ ] Implement two fan channels and available fan/airflow proof +- [ ] Implement the characterized fan channel and available fan/airflow proof - [ ] Define the bounded fan spin-up/proof timeout and the evidence that changes proof from pending to proven or failed - [ ] Implement physical-switch handling and debouncing - [ ] Implement bounded settings persistence with corrupt-NVS recovery @@ -69,7 +125,7 @@ implementation starts, and keep only the summary checkbox here. - [ ] Finalize Jump Jet API v2 state and mutation schemas - [ ] Add chamber, outlet, and case temperature telemetry with sensor status -- [ ] Add target, heater duty, both fan states, mode, and commissioning state +- [ ] Add target, heater duty, fan command/proof state, mode, and commissioning state - [ ] Add PrusaLink connection, printer state, bed temperature/target, and sample age - [ ] Define optional Klipper/Moonraker integration for read-only printer state and bed-target telemetry, with the same stale-data fail-cold semantics as PrusaLink - [ ] Add visible interlocks, latched fault reason, and safe recovery guidance diff --git a/docs/HARDWARE_BASELINE.md b/docs/HARDWARE_BASELINE.md index 6415ac4..7774656 100644 --- a/docs/HARDWARE_BASELINE.md +++ b/docs/HARDWARE_BASELINE.md @@ -1,4 +1,16 @@ -# Hardware baseline — not commissioned +# Hardware baseline — Rev A Phase 1 + +Rev A.4.1 is the current authoritative schematic baseline. Its +[KiCad project source](../hardware/kicad/JumpJet_RevA/README.md) is checked into +the repository. The checked-in source set currently contains no `.kicad_pcb`; +creating the first Rev A PCB remains active Phase-1 implementation work. + +The detailed living source of truth for measurements, component candidates, +design decisions, provisional values, blockers, and validation status is the +[Phase 1 hardware register](PHASE1_HARDWARE_REGISTER.md). Presence in that +register does not make a candidate BOM-final or approve fabrication. +Checking in the KiCad source likewise does not make the design fabrication-ready +or authorize heater actuation. ## Confirmed @@ -9,17 +21,64 @@ 74–75 °C. - Full results: [CZ4060 characterization](hardware/cz4060-characterization.md). - The Sanyo Denki 9GA0424P3J001 is a prototype fan candidate, not BOM-final. +- The Phase-1 replacement-fan contract is continuous fused 24 V and ground with + separate open-drain PWM and tach. The original Rev A.4.1 low-side switched + two-wire block is retained as baseline evidence, not production intent. +- Published prototype facts and pending measurements are tracked in the + [9GA0424P3J001 characterization record](hardware/9ga0424p3j001-characterization.md). +- Phase-1 schematic work separates the protected-24-V-derived + `+5V_SYS_GATE` actuator rail from the MCU logic domain. Bench measurements of + the actual Super Mini establish that its USB VBUS and exposed 5 V pin are one + effectively direct, bidirectional node: 4.993 V applied to the pin produced + 4.992 V at VBUS; USB at 5.13 V produced 5.11 V at the pin; unpowered + continuity was confirmed. +- Rev A therefore requires mutually exclusive installed/USB service power at + the module node. Board-derived MCU 5 V reaches the module only through a + physical disconnect that must be opened before powered USB attachment. A + removable jumper/shunt is preferred, but its part and footprint are not yet + selected. Seamless simultaneous source operation is out of scope. +- USB shall not be routed through the carrier and must never source `+5V_SYS_GATE`. + The gate buffer cannot be powered from USB-only MCU power. +- The heater driver now uses a hardware-default-disabled active-low OE topology: + an OE pull-up holds the driver disabled unless a separate open-drain enable + transistor is explicitly asserted. Generic `HEATER_GATE_EN` and + `HEATER_PWM_CMD` nets remain unassigned to controller pins. ## Not confirmed -The authoritative `.kicad_pcb` remains missing. Q1, F2, PCB copper, connectors, -wiring, installed airflow, the exact ESP32-S3 module, and the complete power path -have not been validated together. The upstream Jetpack pin assignments are -historical facts, not Jump Jet assignments. +Q1, F2, PCB copper, connectors, wiring, installed airflow, the exact ESP32-S3 +module implementation, and the complete power path have not been validated +together. The LMR36520 and SN74LV4T125 are strong candidates, not BOM-final; +the regulator circuit, physical MCU service-disconnect implementation and rating, +disconnect accessibility/labeling, and full power-transition bench matrix remain +open. TPS2116-only automatic source selection is superseded because the module +has no separately controllable USB and exposed-5-V nodes. The upstream Jetpack pin +assignments are historical facts, not Jump Jet assignments. + +## Rev A MCU service-power states -No GPIO, ADC, divider, thermistor conversion, fan/PWM method, protection threshold, -thermal trip, cooldown criterion, or recovery threshold may be finalized without -the corresponding source files and measured evidence. +| State | Physical disconnect | Required outcome | +|---|---|---| +| Normal 24 V operation; USB absent | Closed | Board-derived MCU 5 V powers the Super Mini. `+5V_SYS_GATE` remains an independent 24-V-only actuator rail; firmware safety still controls actuation. | +| USB service; 24 V absent | Open before USB attachment | USB powers only the Super Mini-side MCU logic node. Gate power is absent and the heater is physically incapable. | +| USB service; 24 V present | Open before USB attachment | USB powers the MCU node; `+5V_SYS_GATE` may exist from 24 V but remains isolated and the default-disabled gate/OE architecture keeps the heater off unless every normal hardware and firmware condition is valid. | +| Disconnect mistakenly closed while powered USB is attached | Invalid/misuse | Board 5 V and host VBUS can contend or backfeed. Silkscreen and accessible disconnect geometry must make this misuse obvious; Rev A does not promise safe seamless coexistence. | +| USB removed while 24 V absent | Open | MCU loses power cleanly; no actuator domain may remain energized from USB capacitance or another path. | +| 24 V removed while USB remains | Open | MCU may remain alive, but `+5V_SYS_GATE` collapses independently and firmware must truthfully report heater actuation unavailable. | + +No GPIO, ADC, divider, thermistor conversion, protection threshold, thermal trip, +cooldown criterion, or recovery threshold may be finalized without corresponding +source files and measured evidence. Fan interface values, production fan, +tach electrical behavior, pulses/revolution, RPM versus duty, minimum reliable +command, startup behavior, RPM/stall thresholds, and installed airflow/thermal +performance remain unresolved. A model-specific 25 kHz candidate test point is +not universal production policy. + +The newer Prusa-derived void is the preferred enclosure-space reference; the +earlier smaller-void system-level incompatibility conclusion is superseded. PCB +over the cold-air intake remains preferred and mechanically plausible, but the +installed transform and aligned local constraint map are unresolved, so +fabrication-intent `Edge.Cuts` remain blocked. ## Firmware consequence @@ -28,5 +87,8 @@ GPIO, placeholder pin, PWM, ADC, thermistor conversion, or MOSFET actuation path The provisional numeric limit header was removed because unvalidated values are not a hardware contract. +Heater actuation remains disabled while the safety-critical hardware design and +validation progress. + The build retains a provisional 4 MiB dual-OTA partition layout solely as an ESP32-S3 development baseline. It is not a release hardware constraint. diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md new file mode 100644 index 0000000..8c5f88b --- /dev/null +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -0,0 +1,271 @@ +# Phase 1 hardware source-of-truth register + +Last updated: 2026-09-08 + +This is the living engineering register for JumpJet Rev A Phase-1 hardware +implementation. It records what is known, how it is known, what remains +provisional, and which downstream decisions are blocked. Rev A.4.1 is the +current authoritative schematic baseline and its KiCad source is checked into +the repository; the first Rev A PCB remains active Phase-1 implementation work. + +> **Presence in this register does not mean BOM-final, fabrication-approved, or +> release-approved. Only the explicit status field carries authority.** + +## Status legend + +| Status | Meaning | +|---|---| +| CONFIRMED FACT | Supported by an authoritative project artifact or direct evidence; not merely inferred. | +| MEASURED | Directly measured, with the measurement conditions and source identified. | +| DESIGN DECISION | Deliberately selected architecture or requirement; implementation may still need validation. | +| STRONG CANDIDATE | Preferred component candidate with substantial support, but not BOM-final. | +| PROTOTYPE CANDIDATE | Part selected for characterization or prototyping only. | +| ASSUMPTION / PROVISIONAL | Working value or approach that must not be treated as final. | +| TBD / BLOCKED | Required information or selection is absent and blocks one or more downstream activities. | + +Confidence describes the quality of the current evidence, not release readiness. +The **Blocks** column identifies what cannot be frozen or completed until the +remaining validation closes. + +## 1. System electrical basis + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| System voltage | CONFIRMED FACT | 24 V system architecture. | Rev A.4.1 schematic; [CZ4060 characterization](hardware/cz4060-characterization.md) | High | Validate production-supply tolerance and transients with the complete assembly. | BOM freeze + Fabrication | +| CZ4060 conservative design basis | CONFIRMED FACT | Size the heater path for 24 V, 200 W, and 8.33 A. | Heater rating and [CZ4060 characterization](hardware/cz4060-characterization.md), commit `903e5e0cdfc7a17102d51de1c01fa414be613b92` | High | Validate every production current-path element at this design load and installed temperature. | PCB layout + BOM freeze + Fabrication | +| Standalone sustained load | MEASURED | Approximately 189 W and 7.89 A at 24 V. | 60-minute standalone run in [CZ4060 characterization](hardware/cz4060-characterization.md) | High for tested specimen and setup | Repeat or bound unit-to-unit behavior; validate installed full-path voltage drop and temperature. | BOM freeze + Fabrication | +| Standalone startup | MEASURED | Approximately 196 W peak observed; no high-current cold inrush observed. Current rose over several minutes while the bench supply remained in CV mode. | Startup test in [CZ4060 characterization](hardware/cz4060-characterization.md) | High for tested specimen and setup | Confirm behavior with the production PSU, wiring, controls, and additional heater specimens. | BOM freeze + Fabrication | +| Standalone thermal behavior | MEASURED | Heater/PTC region approximately 130 °C steady; chassis approximately 74–75 °C steady. These are characterization results, not firmware or protection thresholds. | 60-minute standalone run in [CZ4060 characterization](hardware/cz4060-characterization.md) | High for tested specimen and setup | Installed-system mapping with production airflow, sensor placement, fault cases, and materials. | Firmware constants + BOM freeze + Fabrication | +| Cold DMM resistance | MEASURED | Approximately 20–21 Ω was observed cold, but it is not authoritative for heater-path sizing. Use the powered measurements and 8.33 A conservative design basis. | Cold-resistance note in [CZ4060 characterization](hardware/cz4060-characterization.md) | High | None for current-path design basis. | None | + +Firmware thresholds must not be derived directly from the standalone heater +temperatures. + +## 2. ESP32-S3 Super Mini mechanical implementation + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Module PCB body | MEASURED | 23.67 mm long × 17.91 mm wide. | Physical measurement of the actual module | High | Confirm against the 1:1 production-footprint plot before freeze. | Fabrication | +| Overall length including USB-C | MEASURED | 25.07 mm. | Physical measurement of the actual module | High | Confirm connector projection and carrier-board relationship on the 1:1 plot. | PCB layout + Fabrication | +| USB-C overhang | MEASURED | Approximately 1.40 mm beyond the module PCB edge. This is a datum, not a complete connector keepout. | Direct caliper measurement of the actual module | High for overhang only | Establish the carrier-board edge relationship, mating-plug envelope, cable-head clearance, and enclosure access. | PCB layout + Fabrication | +| USB-C shell envelope | MEASURED | Shell is 8.84 mm wide × 3.12 mm high/thick and occupies 7.48 mm over the module PCB. These shell measurements do not define the plug or enclosure keepout. | Direct caliper measurement of the actual module | High for the measured shell | Measure the mating plug and cable head; define carrier-edge and enclosure-access clearances. | PCB layout + Fabrication | +| Pad count | CONFIRMED FACT | Nine castellations per side; 18 total. | Physical inspection of the actual module | High | Verify every pad number and label against the actual module silkscreen. | PCB layout + Fabrication | +| Adjacent castellation pitch | MEASURED | 2.55 mm center-to-center. This supports, but does not replace, the provisional 2.54 mm nominal design pitch. | Direct caliper measurement of adjacent castellations on the actual module | High for the measured specimen | Verify all pad centers on the 1:1 production-footprint plot. | PCB layout + Fabrication | +| Nominal pin pitch | ASSUMPTION / PROVISIONAL | Use 2.54 mm for footprint design. Supported by the 2.55 mm adjacent measurement, ordinary 2.54 mm header fit, and a previously measured approximately 20.0 mm first-to-last center span versus the nominal 20.32 mm eight-pitch span. | Physical measurements, physical header fit, and derived nominal geometry | High | Verify all 18 pads by true-scale physical placement before freeze. | PCB layout + Fabrication | +| Nominal row spacing | ASSUMPTION / PROVISIONAL | 15.24 mm; supported by an approximately 15.2 mm physical measurement. | Physical measurement and derived nominal geometry | High | 1:1 physical placement and direct row-center verification. | PCB layout + Fabrication | +| Side edge to row center | ASSUMPTION / PROVISIONAL | Approximately 1.335 mm, derived as `(17.91 - 15.24) / 2`. | Derived from measured body width and provisional nominal row spacing | Medium | Measure actual castellation centerline relative to both module edges. | PCB layout + Fabrication | +| Castellation width | MEASURED | 1.96 mm along the module board edge. This is the module castellation width, not a frozen carrier receiving-land width. | Direct caliper measurement of the actual module | High for the measured specimen | Review solder/process margin, inward land depth, mask expansion, and paste treatment before defining the carrier land. | PCB layout + Fabrication | +| Non-USB edge to first castellation | MEASURED | 1.00 mm from the non-USB PCB edge to the near edge of the first castellation. This is explicitly not a centerline offset. | Direct caliper measurement of the actual module | High for the measured datum | Establish the footprint datum and directly verify longitudinal pad-center registration at both ends. | PCB layout + Fabrication | +| Derived longitudinal registration | ASSUMPTION / PROVISIONAL | With the footprint origin at the module-body center, +Y toward the non-USB/antenna end, and −Y toward USB, the measured 1.00 mm near-edge offset plus 1.96 mm castellation width places the non-USB end-pad center at Y = +9.855 mm. Using the nominal 20.32 mm span places the USB end-pad center at Y = −10.465 mm. | Derived from two physical measurements and the provisional nominal pitch | Medium-high for the derivation; not physically fit-verified | Verify every center against the actual module on a true-scale plot and confirm the remaining USB-end edge distance. | PCB layout + Fabrication | +| Provisional castellated footprint | ASSUMPTION / PROVISIONAL | Project-local `JumpJet:ESP32-S3_SuperMini_2x9_Castellated_PROVISIONAL` is an unassigned iteration footprint. Origin is module-body center; +Y is non-USB/antenna and −Y is USB. It uses 18 pads at X = ±7.620 mm and Y = −10.465 mm through +9.855 mm on 2.54 mm pitch. Pad size is provisionally 3.40 mm inward/outward depth × 1.80 mm along-edge width. The along-edge width leaves 0.74 mm between pads and is narrower than the measured 1.96 mm castellations; the 3.40 mm depth, mask, and paste treatment are process assumptions. | [Checked-in provisional footprint](../hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9_Castellated_PROVISIONAL.kicad_mod) using current measurements and derived registration | Medium | Review carrier land/process geometry, map underside contacts, verify all physical pin labels, and pass the mandatory 1:1 fit check before assigning it to U2. | Footprint freeze + PCB layout + Fabrication | +| Legacy Rev A.4.1 footprint | CONFIRMED FACT | `JumpJet:ESP32-S3_SuperMini_2x9` is a drilled 18-pad through-hole footprint. It is retained only to resolve the authoritative schematic and is explicitly obsolete for production mounting. | [Checked-in Rev A.4.1 footprint](../hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9.kicad_mod) | High | Do not assign it to a production PCB; replace the schematic assignment only after the provisional SMD footprint passes physical verification. | PCB layout + Fabrication | +| Ordinary header fit | MEASURED | Ordinary 2.54 mm header pins physically fit the castellation holes. This supports pitch/alignment evaluation but does not change production attachment to through-hole mounting. | Physical fit check on the actual module | High for fit observation | Measure the actual square posts and verify removable alignment-hole clearance and PCBWay drill tolerance. | PCB layout + Fabrication | +| Production mounting | DESIGN DECISION | Direct solder of the castellated module to carrier-PCB SMD lands. The current drilled through-hole footprint is not the production architecture unless later physical verification explicitly reverses this decision. | Phase-1 mounting decision; inspection of Rev A.4.1 project footprint | High | Complete and physically verify the project-local castellated footprint. | PCB layout + Fabrication | +| Mounted component side | CONFIRMED FACT | All mounted components are on the top side. The underside is physically flat apart from PCB/contact metallization. | Direct top/bottom inspection of the actual module | High | Preserve the observed orientation in the footprint and 1:1 plot. | PCB layout + Fabrication | +| Physical Pin 1 | CONFIRMED FACT | Pin 1 has been physically identified from the module photograph. | Direct photographic inspection of the actual module | High | Document the footprint datum/orientation and verify every remaining pad number and label. | PCB layout + Fabrication | +| Underside exposed contacts/test pads | CONFIRMED FACT | Exposed underside contacts/test pads are present despite there being no mounted underside components. The carrier must not place vias, exposed pads, or other exposed conductive features where unintended contact is possible; even soldermask-covered copper requires spacing/stackup review. | Direct underside inspection of the actual module | High for presence; envelope not mapped | Measure and map the exact contact locations/envelope before fabrication and verify the isolation region in the footprint/PCB. | Footprint freeze + PCB layout + Fabrication | +| Solid carrier beneath module | DESIGN DECISION | Use solid carrier PCB beneath the module. No underside components require height clearance, and no independent manufacturing or mechanical need for a cutout was found. Keep the region isolation-controlled and soldermask-covered, with no exposed copper or vias where module contacts could touch. The opening is not a safety airflow feature. | Direct inspection: no underside components; exposed contacts are present | High for architecture; contact map still incomplete | Map the underside contacts; review mask registration, dielectric/isolation margin, cleaning, and routing before fabrication. | Footprint freeze + PCB layout + Fabrication | +| Central PCB window | DESIGN DECISION | Do not create a central window on current evidence. Reopen only if a concrete cleaning, inspection, thermal, assembly, or mechanical requirement is demonstrated. | Solid-carrier architecture review | High | None unless new evidence independently justifies a window. | None | +| Optional temporary locating holes | ASSUMPTION / PROVISIONAL | Assembly concept only: two holes total at the ends of one castellated row may accept removable ordinary 2.54 mm male-header pins for alignment/tack soldering. The header is removed afterward; production attachment remains the castellated solder joints. | Phase-1 assembly concept and physical header-fit observation | Medium | Verify post dimensions, insertion/removal clearance, PCBWay drill capability/tolerance, land support, antenna/USB clearance, and that the module is not forced into alignment. | PCB layout + Fabrication | +| Locating-hole geometry | ASSUMPTION / PROVISIONAL | Candidate holes remain Ø1.10 mm NPTH. The old X = −7.620 mm, Y = ±12.700 mm pair does not form one-pitch extensions of the newly derived asymmetric end-pad centers under the documented body-center/+Y-antenna datum, so it is not implemented in the provisional footprint. | Updated longitudinal-registration audit of the earlier assembly-aid proposal | High confidence that the old coordinates are unreconciled | Measure the actual header; derive new candidate coordinates from verified pad centers; verify PCBWay finished-hole/position tolerances; physically fit-test insertion/removal and check USB/antenna/land interference. | PCB layout + Fabrication | +| Likely onboard antenna | ASSUMPTION / PROVISIONAL | The small red/white ceramic component at the non-USB end is treated as the likely onboard 2.4 GHz antenna unless inspection or revision-matched evidence disproves it. Do not assume WROOM-class RF performance. | Direct top-side inspection and component appearance | Medium | Confirm function/location and establish the antenna datum and installed orientation. | PCB layout + Fabrication | +| Antenna keepout | ASSUMPTION / PROVISIONAL | Prefer the antenna at a carrier-board edge. The provisional footprint graphically reserves the interior area X = ±6.50 mm, Y = +7.835 to +11.835 mm at the likely antenna end as a visible no-copper warning. This is not an enforced KiCad rule area and is not exact RF geometry. No heater-current or buck switch-node copper, fuse hardware, planes, vias, traces, or large metal may be placed there or immediately beyond the antenna end until the keepout is verified. | Likely antenna location plus conservative footprint iteration | Medium-low for exact bounds | Confirm the antenna and feed geometry, replace the graphic with an enforced all-applicable-layer rule, define enclosure clearance, and validate installed Wi-Fi RSSI/range. | PCB layout + Fabrication | +| USB-C mechanical keepout | TBD / BLOCKED | The shell is measured, but the mating-plug envelope, cable-head clearance, enclosure opening, and carrier-board edge relationship remain undefined. Do not derive the complete keepout from shell dimensions alone. | Direct shell measurements; service-access geometry incomplete | High confidence that evidence remains incomplete | Complete plug, cable-head, carrier-edge, and enclosure-access measurements. | PCB layout + Fabrication | +| Mandatory 1:1 verification | DESIGN DECISION | The actual module must be placed on a true-scale plot before footprint freeze. All 18 castellations, body, Pin 1/orientation, optional locating holes, USB projection, antenna direction/keepout, and underside isolation region must pass without forced alignment. | Phase-1 acceptance requirement | High | Perform and document the physical fit check using the final proposed footprint. | Fabrication | + +## 3. ESP32 power architecture + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Production power domains | DESIGN DECISION | One shared 24 V-derived 5 V regulator feeds `+5V_SYS_GATE`. The heater gate driver remains directly on that actuator rail, while the MCU branch passes through D4 reverse isolation, `+5V_MCU_FEED`, and physical SW1 before reaching the Super Mini `+5V_MCU`/USB-VBUS tied node. USB is never routed to `+5V_SYS_GATE`; USB-only power must be physically incapable of energizing that rail or any actuator domain. | Phase-1 power-domain and service-safety decision; implemented D4/SW1 source path; measured module 5 V topology | High | Qualify the regulator, isolation element, disconnect, and full normal/service/misuse transition matrix. | PCB layout + BOM freeze + Fabrication | +| USB-C role | DESIGN DECISION | Programming, debug, recovery, and service only; not the normal installed power source. Board-derived MCU 5 V must be physically disconnected before attaching a powered USB host. USB may power only the Super Mini-side MCU logic node and must not energize `+5V_SYS_GATE`, the gate driver, or Q1 actuation. | Phase-1 service architecture and measured bidirectional VBUS/5 V coupling | High | Validate every USB-only and mixed-presence power state and observe both 5 V sides, gate rail, OE, PWM input, and Q1 gate during attach/remove. | PCB layout + Fabrication | +| External 5 V/VBUS pin | MEASURED | USB VBUS and the Super Mini exposed 5 V pin are effectively the same node for system design. With 4.993 V applied at the exposed pin, USB VBUS measured 4.992 V. With USB supplied at 5.13 V, the exposed pin measured 5.11 V. Unpowered continuity was confirmed and diode-mode behavior was consistent with direct coupling. | Direct bench characterization of the actual ESP32-S3 Super Mini | High for the tested module | Preserve the measured topology in the schematic and validate production-module consistency during receiving/bring-up. | None | +| USB/external-5 V relationship | CONFIRMED FACT | The Super Mini provides no usable isolation between USB VBUS and its exposed 5 V pin. USB powers the exposed pin, and external 5 V on that pin energizes the USB connector VBUS. Simultaneous board-derived 5 V and a powered USB host must be treated as unsafe unless one source is physically isolated before the tied module node. | Bidirectional voltage and unpowered continuity measurements on the actual module | High | Do not perform simultaneous-source testing with the disconnect closed. Verify the completed carrier implements the required isolation boundary. | PCB layout + Fabrication | +| MCU branch reverse isolation | DESIGN DECISION | The MCU branch shall conduct only `+5V_SYS_GATE -> D4 -> +5V_MCU_FEED`; reverse current from USB/`+5V_MCU` toward `+5V_SYS_GATE` is forbidden. This hardware invariant protects the actuator rail during valid USB service and misuse states without firmware. | Implemented D4/SW1 Phase-1 schematic source path and measured bidirectional Super Mini VBUS/5 V coupling | High for topology | Qualify reverse leakage, forward drop, dissipation, temperature, and USB/24 V transitions on production-intent hardware. | PCB layout + BOM freeze + Fabrication | +| MCU isolation element | STRONG CANDIDATE | D4 is a low-Vf Schottky class with at least 2 A practical current capability, low drop around 0.5–1.0 A, low elevated-temperature reverse leakage, at least 20 V VRRM, and a package comfortable in the approximately 0.2–0.4 W dissipation class. Exact MPN and footprint are TBD and it is not BOM-final. | Phase-1 isolation architecture and provisional MCU load/dissipation envelope | Medium | Measure MCU peak current; select the exact diode/package; calculate and measure hot drop, loss, leakage, and temperature; review availability. | PCB layout + BOM freeze + Fabrication | +| Physical MCU service-power disconnect | DESIGN DECISION | Rev A places firmware-independent SW1 in series between `+5V_MCU_FEED` and the Super Mini-side `+5V_MCU`/USB-VBUS tied node. RUN closes board-derived MCU power; USB SERVICE opens it before host attachment. A solder bridge is not acceptable, and a removable jumper is not primary production intent unless the switch proves mechanically impractical. | Measured module topology, explicit Rev A service policy, and implemented D4/SW1 schematic path | High for architecture | Select and rate the switch after measuring MCU-path current; verify footprint, voltage drop, accessibility near USB, connector clearance, labeling, retention, and misuse visibility. | PCB layout + BOM freeze + Fabrication | +| Disconnect implementation | STRONG CANDIDATE | SW1 is a positive-detent SPST slide-switch class rated at least 2 A at 5 V DC, with contact resistance targeted at no more than 50 mΩ and an absolute design ceiling of 100 mΩ; at least 85 °C operation is preferred. Exact MPN and footprint remain TBD and it is not BOM-final. | Rev A simplicity, auditability, service requirements, and implemented generic SW1 symbol | Medium-high | Measure module current including boot/Wi-Fi bursts; select a rated part and footprint; prove electrical loss, temperature, retention, access, and clearance in the aligned model and 1:1 mockup. | PCB layout + BOM freeze + Fabrication | +| MCU service labeling | DESIGN DECISION | Later PCB silkscreen shall label SW1 states `RUN` and `USB SERVICE` and instruct the technician to set USB SERVICE before connecting powered USB. Exact shortened wording, placement, and orientation remain unresolved until the service geometry is known. | Rev A mutually exclusive service-power policy | High for requirement; implementation unresolved | Verify the final instruction is visible through the service-access path, cannot be mistaken for an actuator control, and remains legible after assembly. | PCB layout + Fabrication | +| Prohibited simultaneous-source state | DESIGN DECISION | `24 V present + powered USB connected + SW1 in RUN` is a prohibited service configuration because the tied module node can create source contention. The D4 reverse boundary must nevertheless prevent USB/`+5V_MCU` from back-powering `+5V_SYS_GATE`; no supported coexistence is claimed. | Measured module topology, D4/SW1 architecture, and explicit misuse policy | High | Label clearly and verify the heater-domain isolation invariant without intentionally sustaining source contention. | PCB layout + Fabrication | +| TPS2116-only source-mux direction | CONFIRMED FACT | Superseded and not sufficient as a USB/external-5 V coexistence solution. A carrier-side TPS2116 cannot independently select USB VBUS versus the exposed module 5 V pin because those nodes are already directly coupled on the Super Mini. TPS2116 is not required by the adopted Rev A mutually exclusive service-power architecture. | Measured module topology compared with [TI TPS2116 product behavior](https://www.ti.com/product/TPS2116) | High | Reconsider only for a narrower future requirement with genuinely separate source nodes; do not place it for Rev A without such a requirement. | None | +| Buck converter candidate | STRONG CANDIDATE | TI LMR36520 synchronous buck: published 4.2–65 V input, 2 A output, up to 70 V input transients, −40 to +125 °C operating junction range, power-good option, and approximately 90% published efficiency at 24 V input, 5 V output, and 1 A. The present `MOD1` connector symbol is only an architecture placeholder, not a discrete implementation or BOM-final part. | [TI LMR36520 product page](https://www.ti.com/product/LMR36520) and Phase-1 regulator review | High for published characteristics; medium for product fit | Select exact ordering code and switching frequency; implement and review the complete discrete circuit, magnetics, compensation/support parts, layout, efficiency/dissipation, transient behavior, and installed-temperature derating. | PCB layout + BOM freeze + Fabrication | +| Buck converter capacity target | ASSUMPTION / PROVISIONAL | Use at least 1.5 A continuous capability as an initial converter target. This is not a selected MPN or BOM-final rating. | Preliminary ESP32-S3 peak/burst allowance plus light interface-load margin | Medium | Complete the 5 V load inventory and converter loss/thermal derating at the maximum installed chamber/PCB temperature; increase the rating if required. | PCB layout + BOM freeze + Fabrication | +| Power-management firmware assumptions | TBD / BLOCKED | Firmware may rely on the architectural fact that USB cannot power the actuator rail, but may not assume the physical disconnect position, board-5-V availability, power-good behavior, or heater availability without truthful hardware evidence. When 24 V is removed while USB remains, MCU logic may stay alive but heater actuation must be reported unavailable. | Adopted Rev A power-domain architecture; disconnect sensing and power-good implementation unresolved | High | Close the implemented power-state truth table and determine whether disconnect position and board/gate-rail availability are observable. | Firmware constants | + +### Rev A power-state truth table + +| 24 V | USB | SW1 | Expected state | +|---|---|---|---| +| OFF | OFF | RUN | `+5V_SYS_GATE` OFF; MCU OFF. | +| ON | OFF | RUN | `+5V_SYS_GATE` ON; MCU ON; normal operation. | +| ON | OFF | USB SERVICE | `+5V_SYS_GATE` ON; MCU OFF; heater driver remains hardware-disabled without MCU enable. | +| OFF | ON | USB SERVICE | `+5V_SYS_GATE` OFF; MCU ON; valid USB service. | +| OFF | ON | RUN | `+5V_SYS_GATE` must remain OFF; MCU ON; misuse state with heater domain isolated. | +| ON | ON | USB SERVICE | `+5V_SYS_GATE` ON; MCU is USB-powered; valid service state; heater driver remains default-disabled. | +| ON | ON | RUN | Prohibited source-contention state; no supported coexistence claim; D4 must still block USB backfeed into `+5V_SYS_GATE`. | + +When 24 V disappears, `+5V_SYS_GATE` collapses, U1 loses VCC, its active-low OE defaults disabled, and the direct Q1 pulldown discharges the gate. If USB remains, `+5V_MCU` may remain alive while D4 keeps `+5V_SYS_GATE` dead; U1's candidate `Ioff` behavior must be qualified to prevent MCU inputs from parasitically powering the unpowered gate-driver domain. + +### Provisional 5 V load inventory + +| Load | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| ESP32-S3 Super Mini | ASSUMPTION / PROVISIONAL | Allocate approximately 600 mA for module peak/Wi-Fi/boot demand; this is a design allocation, not a measured revision-specific maximum. | Phase-1 provisional load budget; exact module power topology and revision remain unverified | Medium | Measure boot and radio bursts on the actual module across supported operating conditions. | BOM freeze + Fabrication | +| Gate buffer and Q1 gate charging | ASSUMPTION / PROVISIONAL | Allocate less than 20 mA for gate logic and gate charging. Gate drive belongs only to `+5V_SYS_GATE`; actual dynamic current depends on the still-unfrozen PWM frequency and Q1 waveform. | SN74LV4T125/CSD18540Q5B candidate architecture and provisional load budget | Medium-low | Qualify the driver/passives; freeze PWM only after waveform/loss review; measure rail transients and average/peak current. | BOM freeze + Firmware constants + Fabrication | +| Fan PWM/tach interface | TBD / BLOCKED | Include open-drain PWM, tach pull-up/interface, and any protection/filter loads; fan motor power remains on fused 24 V. | Four-wire interface architecture; candidate-specific electrical details pending | High confidence that a numeric load is missing | Complete delivered-fan datasheet/bench characterization and select interface values. | BOM freeze + Fabrication | +| Sensor/reference support | TBD / BLOCKED | Include every actual 3.3 V/5 V thermistor, reference, ADC-filter, and level-interface load after the sensing implementation is finalized. | Rev A.4.1 sensing architecture is not a frozen load inventory | High confidence that a numeric load is missing | Reconcile final sensing schematic and regulator/LDO efficiencies. | BOM freeze + Fabrication | +| Qwiic and service expansion | ASSUMPTION / PROVISIONAL | Allocate up to 250 mA if retained; this is a bounded design allowance, not measured consumption or permission for an unbounded external load. | Rev A.4.1 Qwiic/service provisions and Phase-1 provisional load budget | Medium | Decide retained interfaces and enforce the maximum external current; protect and measure simultaneous worst case. | BOM freeze + Fabrication | +| LED and miscellaneous board logic | ASSUMPTION / PROVISIONAL | Allocate approximately 30 mA. | Preliminary Phase-1 load inventory | Low-medium | Reconcile the final schematic and measure actual simultaneous load. | BOM freeze + Fabrication | +| Other explicit margin allocation | ASSUMPTION / PROVISIONAL | Allocate approximately 50 mA before the final engineering margin. | Preliminary Phase-1 load inventory | Low-medium | Replace with itemized loads as the schematic closes. | BOM freeze + Fabrication | +| Working total and converter headroom | ASSUMPTION / PROVISIONAL | Working allocation is approximately 950 mA before engineering margin. Adding 25–30% gives approximately 1.2–1.25 A, so at least 1.5 A continuous capability remains the provisional floor; the 2 A LMR36520 is the preferred strong candidate. | Sum of provisional allocations above | Medium-low until loads are measured | Sum measured simultaneous peaks and verify converter efficiency, transient response, and temperature at maximum installed ambient. | PCB layout + BOM freeze + Fabrication | + +## 4. Heater path and independent interruption + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Rev A.4.1 heater path | CONFIRMED FACT | `+24V_PROT -> F2 -> TF1 -> TS1 -> J2 -> external heater -> Q1 -> GND` | Current Rev A.4.1 schematic | High | Recheck connectivity after every schematic revision and against the first PCB. | PCB layout + Fabrication | +| Independent series protection | CONFIRMED FACT | TF1 and TS1 are physically in series with heater current; firmware is not the sole means of heater interruption. | Current Rev A.4.1 schematic | High for topology | Select and validate final parts, mounting, temperatures, current capacity, and installed fault behavior. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Complete heater-current path | TBD / BLOCKED | The assembled path has not been validated for voltage drop, heating, or fault interruption. | [CZ4060 characterization](hardware/cz4060-characterization.md) explicitly excludes Q1, F2, PCB copper, connectors, wiring, and installed behavior | High confidence that validation is incomplete | Validate final parts, PCB geometry, full-path voltage drop, component/copper temperatures, and installed fault cases. | BOM freeze + Fabrication | + +## 5. Q1 heater MOSFET and gate drive + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Q1 candidate | STRONG CANDIDATE | Texas Instruments CSD18540Q5B; 60 V logic-level N-MOSFET; maximum `RDS(on)` approximately 3.3 mΩ at 4.5 V. Not BOM-final. | Manufacturer data and Phase-1 component review | High for published characteristics | Reconfirm ordering code, lifecycle, package, pin/multipad mapping, and production availability. | PCB layout + BOM freeze + Fabrication | +| Estimated Q1 conduction loss | ASSUMPTION / PROVISIONAL | About 0.205 W at 7.89 A and 0.229 W at 8.33 A using 3.3 mΩ: `P = I²R`. These are max-`RDS(on)`-basis conduction estimates only, not total hot operating loss. | Candidate data and measured/design currents | Medium | Include hot `RDS(on)`, switching loss, duty/frequency, gate waveform, copper spreading, and measured junction/board temperature. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Rev A.4.1 gate-buffer defect | CONFIRMED FACT | The authoritative Rev A.4.1 baseline used SN74AHCT125 buffering with the used active-low OE inputs tied low, so enable was not hardware-default-disabled. The Phase-1 power sheet now supersedes that implementation while preserving this row as baseline evidence. | [Checked-in Phase-1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch); [TI SN74AHCT125 product page](https://www.ti.com/product/SN74AHCT125) | High | Preserve provenance and verify the replacement behavior natively and on the bench. | Fabrication | +| Gate-buffer candidate | STRONG CANDIDATE | SN74LV4T125 in TSSOP-14 is the production-intent candidate. TI publishes 1.8–5.5 V operation, 5.5 V-tolerant inputs, translation support, active-low OE, −40 to +125 °C operation, and `Ioff` partial-power-down support. It is powered only by `+5V_SYS_GATE`; it is not BOM-final. | [TI SN74LV4T125 product page](https://www.ti.com/product/SN74LV4T125) and implemented Phase-1 schematic | High for published characteristics; medium for final selection | Verify exact ordering code, pin mapping/library symbol, input thresholds at 3.3 V, leakage, timing, output drive, gate waveform, and installed-temperature behavior. | PCB layout + BOM freeze + Fabrication | +| Default-disabled OE architecture | DESIGN DECISION | `R20` provisionally pulls heater-channel `/OE` to `+5V_SYS_GATE`. `Q4` (`Q_GATE_EN`, provisional 2N7002-class device) can pull `/OE` low only when generic unassigned net `HEATER_GATE_EN` is asserted. Its gate has a direct pull-down. MCU reset/high-Z/unpowered/disconnected therefore leaves the driver disabled. Unused buffer channels are held disabled, and USB-only power cannot energize the gate-driver rail. | Implemented Phase-1 power/output schematic and TI active-low OE/Ioff behavior | High for intended topology | Run the mandatory 24 V/USB/reset/brownout/attach/remove transition matrix while observing both rails, OE, PWM input, Q1 gate, and source reference. Verify Q4 leakage and resistor values at temperature. | PCB layout + BOM freeze + Fabrication | +| Heater PWM command path | DESIGN DECISION | Generic unassigned `HEATER_PWM_CMD` feeds the U1 A input with a direct input pull-down; no MCU pin is assigned. U1 `Ioff` is intended to prevent back-power through this input while its VCC is absent. U1 Y drives `HTR_GATE` through the provisional series resistor. | Implemented Phase-1 power/output schematic | High for topology | Verify unpowered leakage, logic levels, transitions, and gate waveform on representative hardware. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Gate network values | ASSUMPTION / PROVISIONAL | `R1` is 47 Ω provisional; the direct Q1 gate pull-down `R2` is 10 kΩ provisional; the PWM-input pull-down remains 100 kΩ provisional. The stronger Q1 pull-down improves deterministic turnoff while dissipating only milliwatts when driven high. | CSD18540Q5B maximum gate charge is approximately 26 nC at 4.5 V; Phase-1 leakage/turnoff review | Medium | Select final resistance from leakage, turn-off, gate waveform, PWM frequency, switching loss, and driver-current validation. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Gate/power test points | DESIGN DECISION | `TP11`–`TP17` expose `+5V_SYS_GATE`, the Super Mini-side `+5V_MCU`/USB-VBUS tied node, heater `/OE`, `HEATER_PWM_CMD`, Q1 gate, Q1 source reference, and pre-switch `+5V_MCU_FEED`. TP17 is a bounded bring-up point for verifying D4 and SW1 isolation. | Implemented Phase-1 power/output schematic plus measured module topology | High for schematic provision | Verify footprint accessibility and use both sides of the disconnect plus all gate points in the power-transition bench matrix. | PCB layout + Fabrication | +| Q1 footprint and thermal implementation | TBD / BLOCKED | Exact verified KiCad footprint, thermal-pad implementation, and copper spreading are not frozen. | Footprint/PCB validation not completed | High confidence that implementation is incomplete | Verify package drawing and pad mapping; complete thermal/current layout and measurement plan. | PCB layout + Fabrication | +| Rev A.4.1 Q1 mapping defect | CONFIRMED FACT | Q1 currently uses a generic `Q_NMOS_GDS` symbol and unresolved `Package_DirectFET:TBD` footprint. CSD18540Q5B is published as an 8-pin 5 mm × 6 mm VSON-CLIP (DNK), so the current footprint assignment cannot represent the candidate package or multipad mapping. | [Rev A.4.1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch); [TI CSD18540Q5B product/datasheet page](https://www.ti.com/product/CSD18540Q5B) | High | Build/verify the exact DNK symbol-to-pad mapping, exposed/current pads, land pattern, solder treatment, and thermal copper against the manufacturer drawing. | PCB layout + BOM freeze + Fabrication | + +## 6. F2 fuse and holder + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| F2 fuse candidate | STRONG CANDIDATE | Littelfuse 0287015.U, 15 A ATOF. Not BOM-final. The 15 A candidate provides healthier margin around the approximately 7.9–8.33 A load than a 10 A fuse after elevated-temperature derating. | Heater characterization, conservative design basis, and Phase-1 component review | Medium-high | Validate production-PSU short-circuit/current-limit behavior, time-current coordination, ambient derating, interrupt behavior, and service conditions. | PCB layout + BOM freeze + Fabrication | +| F2 holder candidate | STRONG CANDIDATE | Littelfuse 178.6165.0001, published as a four-terminal PCB-mount ATO holder. Not BOM-final. Rev A.4.1 has no F2 footprint assigned. | [Littelfuse 178.6165.0001 product page](https://www.littelfuse.com/products/fuses-overcurrent-protection/fuse-holders-fuse-blocks-accessories/fuse-holders/in-line-fuse-holders/ato-flr/178-6165-0001); checked-in schematic | Medium-high | Verify manufacturer drawing, four-hole/pad mapping, voltage/current and chamber-temperature performance, pad/copper heating, retention, and fuse removal/service clearance. | PCB layout + BOM freeze + Fabrication | + +## 7. J2 and heater wiring + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| J2 candidate | STRONG CANDIDATE | Phoenix Contact 1715022 / MKDS 1,5/2; nominal IEC current approximately 17.5 A and 5.00 mm pitch. Rev A.4.1 assigns KiCad footprint `TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal`. The 8.33 A heater basis is approximately 48% of the nominal current. Not BOM-final. | [Phoenix Contact 1715022 catalog](https://www.phoenixcontact.com/us/products/1715022); checked-in schematic | Medium-high | Compare the KiCad land pattern to the current manufacturer drawing; verify conductor/ferrule compatibility, torque, non-thermal-relief current entry, terminal/pad temperature, and service access. | PCB layout + BOM freeze + Fabrication | +| Heater wire | DESIGN DECISION | Use 16 AWG high-temperature-insulated wire, with approximately 200 °C-class insulation near the heater. | Current requirement and heater thermal environment | High for direction | Finalize insulation construction, color, length, routing, bend radius, abrasion protection, and installed-temperature margin. | BOM freeze + Fabrication | +| Wire family | STRONG CANDIDATE | TE Connectivity/Raychem Spec 55 family; examples 55/0212-16-2 red and 55/0212-16-0 black. Not BOM-final. | Phase-1 wiring review | Medium | Verify exact construction, approvals, availability, termination method, voltage drop, and harness temperature. | BOM freeze | +| Heater termination details | TBD / BLOCKED | Ferrule type, terminal torque, strain relief, wire length, voltage drop, and terminal/harness temperatures are not frozen. | Harness and installed validation incomplete | High confidence that details are incomplete | Build and thermally validate the production-intent harness and termination. | BOM freeze + Fabrication | +| JST-XH heater use | DESIGN DECISION | JST-XH is not acceptable for the approximately 8 A heater-current path. | Current-path requirement | High | None; maintain this exclusion through schematic and PCB review. | None | + +## 8. Fan architecture and prototype + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Original integrated fan | CONFIRMED FACT | YD4020HBL, 24 V, 0.13 A, two-wire, no native PWM, and no tach. Its two-wire control architecture has been superseded by the four-wire PWM/tach direction. | Physical/product identification from CZ4060 assembly review | Medium-high | Confirm nameplate and electrical behavior if retained for comparative testing only. | None | +| Rev A.4.1 two-wire fan block | CONFIRMED FACT | The Rev A.4.1 baseline originally used F3/J3/D2/Q2/R3/R4 as a fused two-wire low-side-switched fan-power block. Phase-1 source removes D2, repurposes Q2/R3/R4 for the low-current PWM interface, and replaces J3 with the reviewed provisional four-wire interface. The old switched-power architecture remains baseline evidence only and is obsolete for production. | [Phase-1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) and checked-in Rev A.4.1 provenance | High | Run native KiCad open/ERC and review the provisional interface against the delivered fan and final connector. | PCB layout + BOM freeze + Fabrication | +| Replacement fan prototype | PROTOTYPE CANDIDATE | Sanyo Denki 9GA0424P3J001; ordered for characterization, ETA 2026-09-15. Not BOM-final. | Prototype purchase record and [characterization record](hardware/9ga0424p3j001-characterization.md) | High for order state; unvalidated for application | Complete electrical, airflow, pressure, acoustic, thermal, stall, and installed-system characterization. | BOM freeze + Firmware constants | +| Published prototype electrical data | CONFIRMED FACT | Model-specific manufacturer data states 24 V rated, 21.6–26.4 V operating range, 0.27 A, 6.48 W, pulse sensor, and PWM control. These facts apply only to 9GA0424P3J001. | [Manufacturer product page](https://products.sanyodenki.com/en/sanace/dc/dc-fan/9GA0424P3J001/) summarized in the [characterization record](hardware/9ga0424p3j001-characterization.md) | High | Verify delivered-specimen identity and behavior; do not generalize to a production substitute. | BOM freeze + Firmware constants | +| Prototype lead convention | ASSUMPTION / PROVISIONAL | Manufacturer installation material gives the general San Ace convention of red positive, black/blue ground, yellow sensor, and brown PWM. Treat the ordered model provisionally as four AWG26 leads with red +24 V, black GND, yellow tach, and brown PWM until the delivered specimen or model drawing verifies gauge and functions. | San Ace manual `M0011876C`; Sara 30 handoff; [characterization record](hardware/9ga0424p3j001-characterization.md) | Medium | Inspect the delivered label/leads and verify electrically before applying power. | BOM freeze + Fabrication | +| Four-wire fan architecture | DESIGN DECISION | `+24V_PROT -> F3 -> FAN_24V -> J3 pin 1`, continuous GND on pin 2, separate tach on pin 3, and separate open-drain PWM on pin 4. Do not low-side PWM fan supply. F3 remains dedicated branch protection with rating TBD. | Phase-1 fan architecture decision and [Phase-1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) | High for topology | Qualify branch protection, final connector/fan, interface values, and installed behavior. | PCB layout + BOM freeze + Fabrication | +| J3 connector | STRONG CANDIDATE | Four-position JST-XH, logical pinout 1 FAN_24V, 2 GND, 3 FAN_TACH, 4 FAN_PWM. The schematic uses the vertical B4B-XH-A footprint provisionally; vertical versus right-angle mating direction is not frozen. Not BOM-final. | Phase-1 schematic implementation | Medium | Verify final fan termination, mating housing/contact current, polarity, keying, harness strain relief, installed orientation, and service clearance. | PCB layout + BOM freeze + Fabrication | +| Fan PWM interface | DESIGN DECISION | Use an open-drain N-MOSF stage with a direct gate pulldown. MCU unpowered/reset leaves the transistor off and the fan control lead open. Do not add an external PWM pull-up without model-specific justification. `MCU_FAN_PWM` remains unassigned to a controller pin. `TP_FAN_PWM` is provided. | Manufacturer PWM technical material and [Phase-1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) | High for topology; behavior not yet model-qualified | Verify model-specific control levels/frequency, high-Z and 0% behavior, startup behavior, and failure polarity on the delivered specimen. | BOM freeze + Firmware constants + Fabrication | +| Fan PWM components | ASSUMPTION / PROVISIONAL | Q2 is repurposed as a 2N7002-class SOT-23 control transistor; R3 is a provisional 1 kΩ gate series resistor and R4 a 100 kΩ direct gate pulldown. Exact MPN and values are not BOM-final. | Phase-1 schematic implementation | Medium | Select the transistor and values from control-input limits, leakage, waveform, EMI, and temperature validation. | PCB layout + BOM freeze + Fabrication | +| Prototype PWM behavior | ASSUMPTION / PROVISIONAL | Test 25 kHz as a candidate point. Open-control/full-speed behavior and 0%-command/stop behavior are expected but not frozen: available manufacturer technical material says frequency and response differ by model. | Sara 30 handoff; manufacturer PWM technical material; [characterization record](hardware/9ga0424p3j001-characterization.md) | Medium-low until model-specific evidence or bench data exists | Obtain the model drawing/specification or verify high-Z, 0%, and frequency behavior on the delivered specimen. | BOM freeze + Firmware constants + Fabrication | +| Fan tach interface | ASSUMPTION / PROVISIONAL | J3 tach feeds a provisional 1 kΩ series resistor, 10 kΩ pull-up to 3.3 V, DNP filter capacitor provision, generic `FAN_TACH` controller-side net, and `TP_FAN_TACH`. Do not pull tach to 5 V or 24 V. The open-collector interpretation remains provisional. | Phase-1 schematic implementation and general San Ace pulse-sensor material | Medium | Verify exact output circuit, voltage/current limits, pull-up, protection/filter need, pulses/revolution, waveform, and stall semantics. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Fan performance envelope | TBD / BLOCKED | Startup/steady current, minimum reliable PWM/speed, RPM versus duty, CZ4060 airflow/static pressure, locked-rotor behavior, stall-detection latency, hub temperature, installed chamber margin, cooldown versus RPM, and minimum safe airflow/RPM remain unknown. | Prototype characterization pending | High confidence that evidence is missing | Complete bench and installed-system characterization. Do not freeze RPM thresholds beforehand. | BOM freeze + Firmware constants | +| Fan branch fuse | TBD / BLOCKED | F3 remains dedicated protection for the continuous 24 V fan branch; no production rating or footprint is selected. | Phase-1 schematic architecture | High confidence selection is open | Measure startup/locked-rotor behavior and coordinate fuse rating/time-current behavior with wiring, connector, fan, and production PSU. | PCB layout + BOM freeze + Fabrication | + +The first PCB may include configurable interface provisions, but fabrication is +acceptable only if the unresolved interface is deliberately bounded and does not +require unsupported electrical assumptions. + +### Rev A thermal sensing contract + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Four-channel Rev A sensing | DESIGN DECISION | Rev A retains the three remote channels `T_CHAMBER`, `T_OUTLET`, and `T_CASE_EXTERNAL` and adds `T_PCB` as a fourth, onboard SMD NTC channel. No existing thermal channel is removed. | Finalized Phase-1 thermal-channel steering and checked-in thermistor sheet | High for channel semantics | Verify all four channels together on production-intent hardware. | Firmware constants + PCB layout + Fabrication | +| `T_PCB` role | DESIGN DECISION | `T_PCB` monitors local electronics/PCB heat soak, including correlation with buck/regulator, MOSFET, fuse/terminal, enclosure, and `T_CASE_EXTERNAL` behavior. It is not chamber temperature and is not equivalent to `T_CASE_EXTERNAL`. | Finalized Phase-1 thermal-channel steering | High | Compare all four channels during normal heating, heat soak, cooldown, airflow-fault-oriented tests, high ambient, and power-section stress. Rev B may remove `T_CASE_EXTERNAL` only if validation shows `T_PCB` is equal or better for the intended safety-relevant role. | Firmware constants + PCB layout + Fabrication | +| `T_PCB` front end | DESIGN DECISION | `TH1` is a provisioned onboard 10 kΩ SMD NTC using the existing 3.3 V, 10 kΩ 0.1% pull-up, 1 kΩ ADC-series, and 100 nF filter philosophy (`R16`, `R17`, `C8`). The unassigned product-local ADC net is `TEMP_PCB_ADC`. `TH1` retains the legacy connector-shaped graphic as a bounded representation blocker until it can be replaced natively without corrupting the archived mixed-schema hierarchy. | Checked-in thermistor sheet; topology matched to the three existing channels | High for electrical topology; symbol and component selection unresolved | Replace the placeholder graphic with a native thermistor symbol, then validate ADC range, noise, open/short detectability, return-path integrity, and conversion calibration. | Firmware constants + PCB layout + BOM freeze + Fabrication | +| `T_PCB` device and firmware constants | TBD / BLOCKED | Exact NTC MPN, Beta, tolerance, temperature rating, ADC/GPIO assignment, conversion constants, and firmware thresholds are not selected. No thermal thresholds are implied by this channel addition. | Required evidence is not yet available | High confidence that selection remains open | Select and qualify the NTC; assign ADC only with the complete controller pin plan; derive constants and thresholds from measured hardware. | Firmware constants + BOM freeze + Fabrication | +| `T_PCB` placement | TBD / BLOCKED | Exact placement remains open. Sense representative local electronics/PCB temperature, not a component junction or fan inlet. Do not place directly against Q1 thermal copper, buck switch-node copper, under the ESP32-S3, in the fan cold-air jet, against the heater connector or fuse-holder copper, or on a pour dominated by one hot component. | Layout has not begun; no `.kicad_pcb` exists | High confidence that placement remains open | Establish placement after the PCB plane, component placement, airflow, and high-current geometry are known; validate correlation against `T_CASE_EXTERNAL`. | PCB layout + Fabrication | + +## 9. Independent thermal protection + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| TF1 and TS1 schematic values | TBD / BLOCKED | Rev A.4.1 placeholders are TF1 75 °C / 15 A and TS1 normally closed 75 °C / 16 A. The 75 °C values are not finalized production selections. | Current Rev A.4.1 schematic and standalone thermal results | High confidence that placeholders are not validated | Select temperatures only after installed-system thermal and fault mapping. | BOM freeze + Firmware constants + Fabrication | +| Thermal-device families | ASSUMPTION / PROVISIONAL | SCHOTT SEFUSE SF and Protherm 03EC are families to investigate, not selected parts and not BOM-final. | Phase-1 component-family review | Low-medium | Establish exact construction, package, current/voltage rating, trip tolerance, mounting method, aging, availability, and approvals. | PCB layout + BOM freeze + Fabrication | +| Protection ordering | DESIGN DECISION | `normal operating ceiling < firmware hard trip < independent hardware cutoff < lowest applicable material/component limit` with justified margins. | JumpJet safety architecture | High | Establish every numeric boundary from installed measurements and component/material limits. | BOM freeze + Firmware constants + Fabrication | +| Installed thermal evidence | TBD / BLOCKED | Required measurements include TF1 body, TS1 body, heater hotspot, chamber, enclosure/material, wiring, and connector temperatures under normal, failed-fan, restricted-airflow, and heater-stuck-on cases. | Standalone characterization explicitly does not cover installed behavior | High confidence that evidence is missing | Complete production-intent installed thermal mapping and fault testing. | BOM freeze + Firmware constants + Fabrication | + +The approximately 130 °C heater/PTC and 74–75 °C chassis measurements do not +identify a valid production cutoff temperature or mounting location. + +## 10. PCB implementation + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Preferred enclosure-space reference | MEASURED | `Void directly from Prusa file.step` is the preferred current enclosure-space reference. Its AP242 solid is expressed in metres and behaves as a constant X-Z section extruded 268.000 mm along neutral-CAD Y. Parsed gross coordinate extents are approximately X = 192.950 mm, Y = 268.000 mm, and Z = 185.311 mm. These gross extents establish substantially more installation volume; they are not usable PCB dimensions and do not encode the local Jetpack placement. | `Void directly from Prusa file.step`, Onshape export dated 2026-09-04, SHA-256 `641c9b8e20736b3045403c1793836d2242f225e9beb8f6a878e22a60466472cd`; direct STEP entity, unit, and coordinate analysis | High for source geometry, units, and gross extents | Recover the rigid transform between this void and the installed Jetpack mount, then correlate printer directions, walls, service opening, and adjacent hardware. | Heater placement + PCB envelope + mounting + Edge.Cuts + Fabrication | +| Superseded small-void packing study | MEASURED | `Part Studio 1 - Internal Space.step` contains one closed 62.628 × 268.000 × 72.450 mm void with an approximately 2,728.653 mm² constant section and 0.731 L volume. The earlier result that a 41 × 41 × 105 mm conservative heater box does not fit its principal-axis section remains valid for that file, but the file is now known to be a smaller/incomplete local void. The result is retained as historical evidence and is no longer a system-level incompatibility or fabrication blocker. | `Part Studio 1 - Internal Space.step`, Onshape export dated 2026-09-04, SHA-256 `608b08534cdaa03be100230e1626da68c53977416f97d7f18e626874d7fa79fc`; direct STEP analysis; superseded by the preferred Prusa-derived void | High for the historical geometry and packing result | Use the preferred Prusa-derived void for current system packaging; retain this result only for provenance unless the smaller region is later identified physically. | None | +| Jetpack fan-attachment geometry | MEASURED | `jetpack-fan-attachment.step` is one AP242 solid expressed in metres. In its local fan-face datum it contains a four-hole pattern at X/Y = ±16.000 mm (32.000 × 32.000 mm spacing), nominal 3.500 mm holes, and concentric approximately 38.000 mm fan-aperture geometry. The exported solid's vertex bounds are approximately 46.850 × 51.698 × 48.000 mm. These dimensions identify local attachment geometry only; they do not establish printer orientation, airflow sign, or installed position. | `jetpack-fan-attachment.step`, Onshape export dated 2026-05-14, SHA-256 `16e8a43a846a8cf6bce9095980827f721db8490bd00f365e97459a208e2edd00`; direct STEP entity and coordinate analysis | High for the local pattern and neutral-CAD geometry | Correlate the fan face to the physical fan/heater stack and recover its installed transform to the preferred enclosure-space reference. | Heater placement + PCB plane + mounting + Edge.Cuts + Fabrication | +| Mechanical-source alignment | TBD / BLOCKED | No common rigid transform is preserved between the preferred Prusa-derived void and the separately exported Jetpack fan attachment. Their AP242 files each contain a single neutral-coordinate solid and no assembly occurrence relationship. The native `core_one_assembly.f3d` archive is readable as a Fusion container and the available AP214 assembly STEP contains printer assembly occurrences, but neither contains the separately exported `Fan attachment` product or an identified matching datum that locates it. Applying scale, translation, rotation, or reflection between these sources would therefore be invented. | Direct inspection of both AP242 structures; `core_one_assembly.f3d`, SHA-256 `2655b839e5e401ee191be4d3fdd8d40e6bd16377da94f2afcaf9258c17f5e113`; available AP214 assembly STEP, SHA-256 `4ead8073806c86df0e2309e905f84664715b2a09b9c384839aa33a8a8591aa08` | High confidence that the supplied exports do not close alignment | Provide one assembly/export containing both the Jetpack attachment and Prusa reference in preserved installed coordinates; alternatively provide three non-collinear corresponding datum points (or an origin plus two directed axes) measured/identified on both models. Also identify which fan-face normal points toward the cold-air side. | Heater placement + PCB plane/envelope + service/antenna directions + local constraint model + Edge.Cuts + Fabrication | +| Heater/fan occupied envelope | MEASURED | The current heater plus fan assembly occupies a 41 × 41 × 105 mm rectangular envelope inside the same available void. The production power supply remains outside the printer. | Direct assembly-envelope measurement supplied for the Phase-1 placement study | High for the supplied envelope; attachment datums are not encoded | Record the hot-air outlet datum, connector and wire exits, attachment features, and required operational/service clearances. | Heater placement + PCB envelope + mounting + Fabrication | +| Heater intake face | CONFIRMED FACT | The 41 × 41 mm face selected for possible PCB mounting is the heater/fan assembly's cold-air intake side. Incidental intake-air cooling must not be a safety dependency. | Physical assembly identification supplied for the Phase-1 placement study | High for face function | Record fan aperture and mounting-hole geometry, airflow direction in printer coordinates, connector/wire exits, and required unobstructed inlet/service volumes. | Heater placement + PCB envelope + mounting + Fabrication | +| PCB-over-intake architecture | ASSUMPTION / PROVISIONAL | Leading architecture is heater/fan → cold-air intake face → independent support/standoffs or integrated carrier → controller PCB. The PCB may overhang the fan body if aligned local geometry and airflow testing support it; no standoff height, use of shared fan screws, board outline, or service envelope is frozen. Intake airflow must not be credited as safety-critical PCB cooling. | Phase-1 mechanical steering; favorable cold-side topology; preferred enclosure-space reference removes the former system-volume objection | Medium concept confidence; installed alignment remains absent | Recover the installed transform, then establish bracket load path, standoff stack, PCB/component heights, inlet flow area, connector mating/fuse-pull/USB zones, cable corridors, and side-panel removal path. | PCB envelope + mounting + Fabrication | +| Heater placement in preferred void | TBD / BLOCKED | The preferred void removes the prior evidence of a fundamental heater/enclosure incompatibility, but no exact placement or collision clearance is established. The conservative 41 × 41 × 105 mm heater/fan envelope is a sanity envelope, not an installed transform or a substitute for actual heater geometry. | Preferred void gross extents; supplied heater/fan envelope; lack of a common Jetpack-to-void datum | High confidence that system volume is no longer the blocker; high confidence that local placement remains unproved | Supply the installed transform/common datums and identify actual heater body, fan, protrusion, cable-exit, mounting-penetration, intake, and outlet geometry. | PCB plane/envelope + mounting + Edge.Cuts + Fabrication | +| PCB plane and local envelope | TBD / BLOCKED | No defensible PCB plane, maximum rectangle, overhang, standoff range, component-height limit, shell clearance, service edge, USB/fuse/connector access zone, antenna-open direction, or airflow no-go region can be derived from gross void bounds. The Jetpack fan-face pattern supplies a useful local datum but is not located within the printer void. | Mechanical-source alignment audit | High confidence that local mechanics remain open | Align the sources and build the local constraint map; then validate the leading carrier strategies and a 1:1 physical mockup before freezing mechanics. | PCB envelope + Edge.Cuts + mounting + Fabrication | +| Production PSU location | DESIGN DECISION | Keep the production power supply outside the printer; only the protected incoming 24 V harness enters the Jump Jet installation volume. | Phase-1 system packaging direction | High | Define entry location, connector, strain relief, routing, and service access against the corrected/confirmed mechanical assembly. | PCB placement + harness + Fabrication | +| Rev A PCB state | CONFIRMED FACT | PCB design is the current Rev A implementation stage. A `.kicad_pcb` has not yet been created and must now be designed. | Rev A.4.1 package scope and Phase-1 project state | High | Create and review the first Rev A PCB from the authoritative schematic. | PCB layout + Fabrication | +| Authoritative KiCad source | CONFIRMED FACT | Rev A.4.1 native project source is checked in under [`hardware/kicad/JumpJet_RevA/`](../hardware/kicad/JumpJet_RevA/README.md): root schematic, four child sheets, project symbol/footprint libraries, library tables, minimal project file, preliminary BOM, and archive provenance README. Native KiCad 10.0.6 opens the root hierarchy and native ERC runs from that root. | `JumpJet_Controller_RevA4_1_J3_JST_XH.zip` intake, checked-in source, native KiCad 10.0.6 open, and `kicad-cli sch erc` | High | Preserve root-driven ERC validation as the schematic evolves. | PCB layout + Fabrication | +| KiCad source schema/validation | CONFIRMED FACT | Tooling blocker CLOSED: despite mixed source schema/generator provenance, KiCad 10.0.6 opens `JumpJet_Controller_RevA4.kicad_sch` with all four child sheets and native root-driven ERC is reusable with the installed standard library tables. Structural/off-grid and label-scope findings are cleared; remaining findings are explicit product blockers, intentional NC/TBD items, or individually reviewed cached-library differences. | Native KiCad 10.0.6 project open and root-driven ERC after structural cleanup | High | Re-run native ERC after each schematic change; do not hide unresolved product blockers. | PCB layout + Fabrication | +| Unresolved footprint references | TBD / BLOCKED | Rev A.4.1 intentionally contains unresolved placeholders `TBD:High_Current_2Pin`, `TBD:DC_DC_Module`, `TBD:Aux_2Pin`, and `Package_DirectFET:TBD`. Native ERC resolves installed standard and project-local non-placeholder libraries; only these deliberate footprint placeholders remain unresolved. | Native KiCad 10.0.6 root-driven ERC and checked-in schematic footprint properties | High | Replace every placeholder only after the corresponding part and footprint are verified. | PCB layout + BOM freeze + Fabrication | +| Preliminary archive BOM | CONFIRMED FACT | `BOM_PRELIMINARY.csv` is checked in as source context only. Its placeholders and historical values do not override this register and are not BOM-final. | [Rev A.4.1 preliminary BOM](../hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv) | High | Reconcile every line against reviewed schematic candidates and replace with a controlled production BOM later. | BOM freeze + Fabrication | +| J1/F1/MOD1 implementation | TBD / BLOCKED | `J1` remains `24V IN / 20A MIN` with placeholder footprint `TBD:High_Current_2Pin`; `F1` remains `15A TBD` with no footprint. `MOD1` now records LMR36520 as the strong-candidate buck architecture and outputs only `+5V_SYS_GATE`, but its connector symbol and `TBD:DC_DC_Module` footprint are explicitly placeholders rather than a discrete implementation. | [Checked-in Phase-1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) and preliminary BOM | High | Select/qualify exact input connector and main protection; implement the complete LMR36520 candidate circuit and verified footprints; validate service/thermal behavior, transients, and PSU/fuse coordination. | PCB layout + BOM freeze + Fabrication | +| Starting stackup | ASSUMPTION / PROVISIONAL | Two layers, 1.6 mm FR-4, 2 oz copper. | Phase-1 routing/current-density starting point | Medium | Review high-current routing, grounding, RF, mechanical, thermal, cost, and PCBWay manufacturing requirements before freeze. | PCB layout + BOM freeze + Fabrication | +| Heater-path copper geometry | ASSUMPTION / PROVISIONAL | Keep heater-path neckdowns at least 4 mm as an initial minimum; prefer broad 8–10 mm or wider pours where practical; minimize vias and unnecessary current-loop area. Place the high-current/safety path before convenience circuitry. | 8.33 A conservative design basis and Phase-1 layout direction | Medium | Calculate and inspect every bottleneck, layer transition, pad entry, thermal relief, and temperature rise for the final stackup. | PCB layout + Fabrication | +| Ground and return strategy | DESIGN DECISION | Prefer a continuous ground plane with a controlled heater/fan/buck high-current return corridor. Thermistor/ADC returns must not share narrow or common-impedance copper with heater current. Do not create arbitrary split grounds that damage ESP32 RF return integrity. | Phase-1 signal-integrity and current-return strategy | High for topology; implementation provisional | Review actual return geometry, buck loops, ADC noise, RF keepout, and current-path coupling after placement/routing. | PCB layout + Fabrication | +| High-current placement priority | DESIGN DECISION | Place and review `+24V_PROT -> F2 -> TF1 -> TS1 -> J2 -> heater -> Q1 -> GND` before convenience circuitry. Keep Q1, J2, F2, and the heater-current path compact without weakening conductor geometry for appearance. | Rev A.4.1 topology and Phase-1 implementation priority | High | Complete placement, current-loop, service-clearance, and thermal review. | PCB layout + Fabrication | +| PCB validation | TBD / BLOCKED | Current-density bottlenecks, Q1 thermal spreading, fuse-holder and J2 pad heating, high-current return geometry, ADC noise, antenna keepout, DRC, fabricated-board temperature rise, and full-path voltage drop are unvalidated. | No Rev A PCB exists yet | High confidence that validation is pending | Create the board, review design evidence, fabricate only after blockers close, then thermally/electrically test production-intent hardware. | PCB layout + BOM freeze + Fabrication | + +## Current fabrication blockers + +Fabrication remains blocked until all of the following are closed or deliberately +bounded by reviewed production-intent provisions: + +- recover the installed rigid transform between the preferred Prusa-derived void and the Jetpack fan-attachment datum; the supplied neutral STEP exports do not preserve one +- map the aligned geometry to printer rear/left/up and the removable side/service-panel direction +- establish the heater inlet, outlet, wiring, attachment, removal, fan-face-normal, and clearance datums before selecting a PCB placement zone +- derive the local PCB plane, practical rectangular envelope, mounting strategy, airflow no-go area, service zones, and antenna-open direction; do not use gross void dimensions as board dimensions +- ESP32 provisional receiving-land depth/process geometry and 1:1 body/pad registration +- complete pin numbering/label verification beyond the physically identified Pin 1 +- underside exposed-contact mapping and carrier isolation review +- antenna identity and conservative pre-fabrication keepout; installed RSSI/range qualification is post-prototype and pre-release +- USB connector, plug, cable-head, and service-access envelope +- optional locating holes must be physically fit-verified or deliberately omitted before footprint freeze +- select, rate, footprint, label, and mechanically validate D4 reverse isolation and the physical SW1 board-MCU-5-V service disconnect +- bench-validate the defined normal, USB-service, mixed-presence, removal, and misuse power-state matrix with the disconnect in its permitted positions +- bench validation of the implemented hardware-default-OFF gate-driver correction across the complete power-transition matrix +- complete regulator implementation, load measurement, and installed-temperature thermal analysis +- Q1 multipad/footprint and F2 holder-footprint verification +- four-wire fan connector/interface footprint and candidate electrical verification; schematic provisions pass structural native ERC checks but remain electrically unqualified +- TF1/TS1 part, mounting, and thermal-coupling implementation +- J1/F1 selections and footprints; MOD1 discrete-regulator implementation and footprint +- PCB envelope, mounting-hole coordinates, connector-facing edges, and USB datum +- final 1:1 production-footprint fit check with the actual module + +## Register maintenance rules + +- Preserve the exact status classes defined in this document. +- Change a status only when the evidence/source and remaining-validation fields + are updated at the same time. +- A `STRONG CANDIDATE` or `PROTOTYPE CANDIDATE` does not become BOM-final by + appearing here. +- Record contradictions and failed validation directly; do not silently replace + inconvenient evidence. +- Link measurement reports, schematic revisions, datasheets, test records, and + relevant commits wherever practical. +- Keep firmware GPIOs, ADC constants, PWM/RPM thresholds, thermal thresholds, + and recovery limits provisional until the corresponding hardware evidence is + complete. diff --git a/docs/PRODUCT_SAFETY_CONTRACT.md b/docs/PRODUCT_SAFETY_CONTRACT.md index abf86cf..cf30133 100644 --- a/docs/PRODUCT_SAFETY_CONTRACT.md +++ b/docs/PRODUCT_SAFETY_CONTRACT.md @@ -41,6 +41,12 @@ AUTOMATIC production heating is unavailable even when `PRINTING` is fresh. and evidence of sane commanded-OFF behavior before heat may be enabled again. - Cooldown and fault fan policy is product-owned and may operate in OFF. - Browser and API authorization are management controls, never the safety boundary. +- The actual Super Mini directly couples USB VBUS to its exposed 5 V pin. Rev A + therefore requires a physical disconnect between board-derived MCU 5 V and + the module node, opened before powered USB service. USB must never power + `+5V_SYS_GATE`, the heater gate driver, the MOSFET actuation path, or any other + safety-critical actuator domain. Removal of 24 V must collapse gate power even + if USB keeps the MCU alive. Reset-cause persistence, stuck-on proof, physical sensors, and physical fan proof are not implemented in this heater-incapable foundation. They are mandatory gates @@ -93,7 +99,17 @@ Those temperatures are observations, not firmware thresholds. ## Hardware-dependent TBDs The full Q1/F2/PCB copper/connectors/wiring path is not validated, and the -authoritative `.kicad_pcb` is missing. Final GPIO, ADC, thermistor conversion, +Rev A.4.1 schematic is the current hardware authority. The Rev A PCB layout does +not yet exist and must be implemented and validated during Phase 1. Hardware +actuation remains blocked until the resulting PCB/current path and the other +safety-critical hardware are validated. Final GPIO, ADC, thermistor conversion, protection thresholds, cooldown criteria, and recovery thresholds must not be invented. Sanyo Denki 9GA0424P3J001 is a prototype fan candidate only and is not BOM-final. + +The intended replacement-fan architecture is continuous fused 24 V plus ground, +separate open-drain PWM, and tach feedback. The Rev A.4.1 low-side switched fan- +power block is obsolete for production. No production pulses/revolution, +minimum duty, RPM/stall threshold, or proof timeout exists before +characterization; a candidate-specific 25 kHz test point does not freeze final +fan policy. Physical fan proof remains mandatory before heater actuation. diff --git a/docs/hardware/9ga0424p3j001-characterization.md b/docs/hardware/9ga0424p3j001-characterization.md new file mode 100644 index 0000000..348861a --- /dev/null +++ b/docs/hardware/9ga0424p3j001-characterization.md @@ -0,0 +1,157 @@ +# Sanyo Denki 9GA0424P3J001 characterization + +> **PROTOTYPE ONLY / NOT PRODUCTION-FINAL.** This record does not select the +> production fan, freeze firmware constants, or authorize fan/heater actuation. + +## 1. Scope and status + +This is the evidence record and bench plan for the ordered Sanyo Denki +`9GA0424P3J001` four-wire fan. Published facts apply to this model only. All +measurement fields remain TBD until the physical specimen arrives and is tested. + +## 2. Specimen identity and provenance + +- Model ordered: `9GA0424P3J001` +- Status: prototype candidate, not BOM-final +- Expected arrival: 2026-09-15 +- Received specimen label, lot/date code, supplier, and traceability: TBD +- Photograph and lead/connector identification: TBD + +Manufacturer sources: + +- [9GA0424P3J001 product page](https://products.sanyodenki.com/en/sanace/dc/dc-fan/9GA0424P3J001/) +- [San Ace PWM technical material](https://products.sanyodenki.com/info/sanace/en/technical_material/pwm.html) +- [San Ace DC sensor technical material](https://products.sanyodenki.com/info/sanace/en/technical_material/dcsensor.html) +- San Ace installation/safety manual `M0011876C`, linked from the product page + +## 3. Pinout + +The manufacturer manual states the general San Ace convention: red is positive, +black or blue is ground, yellow is the sensor lead, and brown is the PWM-control +lead. The delivered model must still be inspected because this convention is not +a substitute for specimen-specific verification. + +| Lead | Provisional function | Verification | +|---|---|---| +| Red | +24 V | Inspect delivered specimen and continuity/power test | +| Black | GND | Inspect delivered specimen and continuity/power test | +| Yellow | Pulse sensor / tach | Verify waveform and electrical limits | +| Brown | PWM control | Verify input behavior and safe drive topology | + +## 4. Published model-specific specifications + +The model-specific product page confirms: + +| Property | Published value | +|---|---:| +| Rated voltage | 24 V | +| Operating range | 21.6–26.4 V | +| Rated current | 0.27 A | +| Rated input | 6.48 W | +| Rated speed | 18,000 min⁻¹ | +| Maximum airflow | 0.67 m³/min (23.7 CFM) | +| Maximum static pressure | 535 Pa (2.15 inH₂O) | +| Operating temperature | −20 to +70 °C | +| Sensor | Pulse sensor | +| PWM control | Yes | + +The published model page does not state the exact PWM frequency, tach output +circuit, pulses per revolution, or model-specific open/0% behavior. Manufacturer +technical material supports open-collector/open-drain PWM drive generally, but +also says voltage, frequency, and response differ by model. Those values remain +provisional pending a model-specific drawing or bench evidence. + +## 5. Bench setup + +Required equipment: + +- current-limited 24 V supply +- DMM and oscilloscope +- open-drain PWM source with adjustable frequency/duty +- logic/frequency capture +- thermal measurement suitable for hub, wire, and connector temperatures +- independent optical tachometer preferred +- anemometer optional + +Record wiring, current limit, ambient temperature, airflow fixture, oscilloscope +probe reference, and all instrument identifiers/calibration status. Do not power +the fan until lead identity has been verified. + +## 6. PWM behavior + +- High-impedance/default control behavior: TBD +- Accepted voltage levels: TBD +- Compatible frequency range; test 25 kHz as a candidate point: TBD +- 0% behavior: TBD +- Upward and downward duty sweeps: TBD +- Noise/vibration observations: TBD + +## 7. Tach behavior + +- Output circuit and voltage: TBD +- Required pull-up and sink-current limits: TBD +- Pulses per revolution: TBD +- Jitter and pulse integrity: TBD +- Startup tach-acquisition latency: TBD + +## 8. RPM versus duty + +Record commanded duty, measured RPM, supply current, and tach frequency for both +upward and downward sweeps. Results: TBD. + +## 9. Startup / minimum reliable command + +- Startup current and duration: TBD +- Minimum reliable startup duty: TBD +- Minimum stable running duty: TBD +- Restart hysteresis: TBD + +## 10. Stall / locked rotor + +The manufacturer installation manual describes cyclic current cutoff and +automatic restart as the general DC-fan burnout-protection approach. Verify the +delivered model rather than treating protection as fan proof. + +- Locked-rotor current behavior: TBD +- Tach waveform/semantics while stalled: TBD +- Automatic restart behavior and timing: TBD +- Safe stall-detection latency: TBD + +## 11. Current + +- 24 V steady current: TBD (published rated current is 0.27 A) +- Startup peak: TBD +- Duty-dependent current: TBD +- Locked-rotor current profile: TBD + +## 12. Thermal behavior + +Record ambient, hub, lead, connector, and interface-component temperatures during +steady operation and locked-rotor testing. Results: TBD. + +## 13. Airflow / CZ4060 cooldown + +Record the fan fixture, restriction/static-pressure condition, installed CZ4060 +airflow, cooldown curve, noise, and vibration. Results: TBD. + +## 14. Derived candidate thresholds + +No minimum duty, minimum RPM, stall threshold, proof timeout, or thermal limit is +defined. Derive candidates only after repeatable bench and installed measurements. + +## 15. Open questions + +- exact delivered lead/connector construction and AWG +- exact PWM electrical limits and frequency range +- open-control and 0% behavior +- tach circuit, pull-up, pulses/revolution, and stopped/locked semantics +- startup, stable-speed, and restart behavior +- fan-branch fuse rating and connector/interface component values +- production-fan suitability and acceptable substitutions + +## 16. Installed-system validation + +After bench characterization, repeat the relevant tests in the production-intent +heater/duct/enclosure assembly. Establish airflow margin, hub/wiring/connector +temperature, chamber performance, cooldown effectiveness, EMI/noise behavior, +and trustworthy fan-proof semantics. Installed results: TBD. diff --git a/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv new file mode 100644 index 0000000..2bc80f3 --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv @@ -0,0 +1,33 @@ +Reference,Qty,Function,Value / Requirement,Population,Status +J1,1,24 V input,">=20 A keyed terminal, 14 AWG capable",BASE,Footprint TBD +F1,1,Main fuse,15 A provisional,BASE,Verify coordination +D1,1,Rail TVS,SMBJ30A provisional,BASE,Verify clamp vs MOSFET/PSU +MOD1,1,Gate-domain buck architecture,"TI LMR36520 strong candidate; +24V_PROT to +5V_SYS_GATE; >=1.5 A provisional floor",BASE,"Connector symbol remains an implementation placeholder; discrete circuit footprint thermal derating and final MPN remain open; not BOM-final" +D4,1,MCU branch reverse-current isolation,"Low-Vf Schottky class; >=2 A practical current capability; exact MPN TBD",BASE,"Strong candidate only; footprint Vf reverse leakage elevated-temperature behavior dissipation and availability remain open; not BOM-final" +SW1,1,RUN / USB SERVICE MCU power disconnect,"SPST slide-switch class; >=2 A at 5 V DC; contact resistance target <=50 mOhm and <=100 mOhm ceiling",BASE,"Strong candidate only; exact MPN footprint operating-temperature rating retention and service-edge mechanics remain open; not BOM-final" +TPS2116 (no reference),0,Conditional source-mux concept,Not production intent for the current directly tied Super Mini VBUS/5 V topology,DNP,"Documentation-only; reconsider only for a future architecture with genuinely separate source nodes" +F2,1,Heater branch fuse,Littelfuse 0287015.U 15 A ATOF candidate,BASE,"Strong candidate; cold-start characterization complete; PSU/fuse coordination and holder thermal validation open" +TF1,1,One-shot thermal fuse,"Historical schematic placeholder: 75 C / 15 A",BASE,"Production part trip temperature mounting and thermal coupling TBD" +TS1,1,Resettable thermal switch,"Historical schematic placeholder: NC 75 C / 16 A",BASE,"Production part trip temperature mounting and thermal coupling TBD" +J2,1,Heater output terminal,"Phoenix Contact MKDS 1,5/2 (1715022), 5.00 mm pitch, 17.5 A nominal",BASE,"Strong candidate only; footprint ferrule torque service access and terminal temperature remain open" +J3,1,Four-wire replacement fan,"Pin 1 FAN_24V; pin 2 GND; pin 3 FAN_TACH; pin 4 FAN_PWM",BASE,"4-pin JST-XH strong candidate; vertical footprint provisional; mating direction and production fan remain open" +Q1,1,Heater low-side switch,TI CSD18540Q5B candidate,BASE,"Strong candidate only; package mapping thermal design hot RDS(on) gate waveform and switching loss remain open" +Q2,1,Fan PWM open-drain interface,2N7002-class logic N-MOSFET,BASE,"Provisional control transistor; former 60 V fan-power-switch role is obsolete; exact MPN TBD" +D2,0,Legacy fan flyback diode,Obsolete with continuous-power four-wire fan architecture,DNP,Removed from Phase 1 schematic +R3/R4,2,Fan PWM gate network,"1 k series / 100 k direct pulldown",BASE,"Provisional values; old fan-power MOSFET gate-network role superseded" +R23/R24/C11,3,3.3 V tach interface,"1 k series / 10 k pull-up / optional filter capacitor DNP",BASE,"Provisional values; exact tach output and filter/protection requirements pending" +TP9/TP10,2,Fan interface test points,TP_FAN_TACH / TP_FAN_PWM,BASE,Phase 1 bring-up provisions +Q3/F4/J4/D3,1 set,AUX1 PWM output,24 V optional,DNP,User expansion +U1,1,Heater gate buffer/level translator,SN74LV4T125 TSSOP strong candidate,BASE,"Powered only from +5V_SYS_GATE; Ioff-capable candidate; exact ordering code and bench qualification remain open; not BOM-final" +Q4,1,Heater-driver OE open-drain actuator,2N7002-class N-MOSF,BASE,"Provisional implementation; exact MPN not selected; MCU net HEATER_GATE_EN is intentionally unassigned" +R20/R21/R22,3,Heater-driver OE bias,"10 k pull-up / 1 k series / 100 k gate pulldown",BASE,"All values provisional; /OE defaults high/disabled and Q4 must pull it low to enable" +R1/R2/R7,3,Heater PWM/gate passives,"47 ohm gate series / 10 k Q1 gate pulldown / 100 k PWM input pulldown",BASE,"All values provisional pending waveform leakage PWM-frequency switching-loss and transition testing" +C12,1,Gate-buffer local decoupling,100 nF provisional,BASE,"Place at U1 supply pins; dielectric and final value remain subject to implementation review" +TP11-TP17,7,Power and heater-driver test points,"+5V_SYS_GATE / Super Mini-side +5V_MCU and USB-VBUS tied node / OE / PWM input / Q1 gate / Q1 source / pre-switch +5V_MCU_FEED",BASE,"Required Phase 1 power-transition and gate-safety observations; TP17 exposes the isolated board-derived feed before SW1" +U2,1,Controller module,"ESP32-S3 Super Mini, 2x9 edge pads",BASE,"Identity confirmed; pad numbering receiving-land geometry registration underside isolation antenna keepout USB access and flash size remain open" +J6-J8,3,Remote thermistors,"10 k NTC, 1 m lead",BASE,"T_OUTLET / T_CASE_EXTERNAL / T_CHAMBER; Beta/coefficients TBD" +TH1/R16/R17/C8,1 channel,Onboard PCB temperature channel,"10 k NTC SMD + 10 k 0.1% pull-up + 1 k ADC series + 100 nF filter",BASE,"T_PCB; TH1 retains the legacy connector-shaped graphic pending native thermistor-symbol replacement; 0603 package provision is provisional; exact NTC MPN Beta tolerance temperature rating placement ADC/GPIO conversion constants and thresholds TBD" +J10,1,Qwiic,JST-SH 1.0 mm 4-pin,BASE,Supported expansion +F5,1,Qwiic protection,250 mA resettable fuse,BASE,Provisional +JP1/JP2 + R18/R19,2,I2C pullups,4.7 k selectable,DNP/open,Populate only if required +J11,1,User expansion,8-pin 2.54 mm,OPTIONAL,Pinout provisional diff --git a/hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9.kicad_mod b/hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9.kicad_mod new file mode 100644 index 0000000..0c62b7c --- /dev/null +++ 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(reference "TP7") (unit 1) + ) + ) + ) + ) + + (symbol (lib_id "Connector:TestPoint") (at 160.02 173.99 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 00000000-0000-0000-0000-000068ae0046) + (property "Reference" "TP8" (at 156.47 170.54 0) + (effects (font (size 0.85 0.85))) + ) + (property "Value" "I2C_SCL" (at 164.47 176.54 0) + (effects (font (size 0.85 0.85))) + ) + (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 160.47 173.54 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Datasheet" "" (at 160.47 173.54 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Description" "" (at 160.47 173.54 0) + (effects (font (size 0.85 0.85)) hide) + ) + (pin "1" (uuid 7d62b5fc-6f54-4037-9a7f-0a1f1148d986)) + (instances + (project "JumpJet_Controller_RevA4" + (path "/1f951ade-7604-48c5-b3a7-4470eab2f41a" + (reference "TP8") (unit 1) + ) + ) + ) + ) +) diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch new file mode 100644 index 0000000..f1106d2 --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch @@ -0,0 +1,3367 @@ +(kicad_sch (version 20260306) (generator jumpjet-reva4-multisheet) + + (uuid 9ef88b6a-3563-4131-bc78-4b6116b7c1d4) + + (paper "A3") + + (title_block + (title "JumpJet Controller — Power, protection, heater, blower, and auxiliary outputs") + (date "2026-08-25") + (rev "A.4.1 - ERC FIX LOADABLE") + (company "JumpJet") + (comment 1 "24 V PTC chamber-heater controller") + (comment 2 "ESP32-S3 SuperMini 2x9 carrier; measured 23.7 x 17.93 mm, 25.0 mm incl. USB-C") + (comment 3 "TBD values require bench verification before assembly") + (comment 4 "Heater thermal cutoffs are independent of firmware") + ) + + (lib_symbols + (symbol "74xx:SN74LV4T125" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (at 0 1.27 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "SN74LV4T125" (at 0 -1.27 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Datasheet" "https://www.ti.com/product/SN74LV4T125" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Description" "Quadruple level-translating buffer with 3-state outputs and Ioff partial-power-down support; strong candidate, not BOM-final" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "ki_locked" "" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "ki_keywords" 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contains the checked-in source from the authoritative Rev A.4.1 +schematic package, `JumpJet_Controller_RevA4_1_J3_JST_XH.zip`. + +Open `JumpJet_Controller_RevA4.kicad_pro`, then +`JumpJet_Controller_RevA4.kicad_sch`. The root schematic references four child +sheets in this directory. Project-local symbols and footprints resolve through +`sym-lib-table` and `fp-lib-table`. + +## Authority and limitations + +- Rev A.4.1 is the current authoritative **schematic** baseline. +- That baseline originally contained the obsolete two-wire low-side-switched fan + block. Phase-1 source now carries the reviewed provisional four-wire interface: + continuous fused 24 V and ground, open-drain PWM, and 3.3 V tach provisions. + The fan and interface remain prototype/candidate dependent and uncharacterized. +- No `.kicad_pcb` exists in this source set. The first Rev A PCB remains active + Phase 1 implementation work, not a missing artifact to recover. +- This source is not fabrication-ready and does not authorize heater or fan + actuation. +- Bench characterization establishes that the actual Super Mini's exposed 5 V + pin and USB VBUS are directly coupled for system-design purposes. Rev A now + routes the shared `+5V_SYS_GATE` source through D4 reverse isolation and the + physical SW1 RUN / USB SERVICE disconnect before the module `+5V_MCU` node. + D4 and SW1 are strong-candidate functional classes only; their exact MPNs and + footprints remain TBD. TPS2116-only automatic selection is not a valid + solution for nodes already tied on the module. +- `+5V_SYS_GATE` remains a separate 24-V-derived actuator rail. USB must have no + path to that rail, the gate buffer supply, or heater actuation. +- Rev A retains remote `T_CHAMBER`, `T_OUTLET`, and `T_CASE_EXTERNAL` sensing and + adds onboard `T_PCB` through the existing thermistor-front-end philosophy. + `T_PCB` placement, exact NTC characteristics, ADC/GPIO assignment, conversion + constants, and firmware thresholds remain blocked; it is not chamber sensing + and does not supersede `T_CASE_EXTERNAL` in Rev A. +- `BOM_PRELIMINARY.csv` is archive context only. It contains placeholders and + does not override statuses in + [`docs/PHASE1_HARDWARE_REGISTER.md`](../../../docs/PHASE1_HARDWARE_REGISTER.md). +- Native KiCad 10.0.6 opens the root hierarchy successfully, and native ERC is + reusable with the installed standard library tables. ERC intentionally still + reports the unresolved `+5V_MCU` source path, unassigned control nets, TBD + footprints, intentional legacy NC nets, and reviewed cached-symbol differences. +- Hierarchical-sheet and project-local library paths pass static resolution. + Placeholder footprint references `TBD:High_Current_2Pin`, + `TBD:DC_DC_Module`, `TBD:Aux_2Pin`, and `Package_DirectFET:TBD` remain + intentionally unresolved and must be replaced before PCB implementation. + +## Footprint status + +`JumpJet.pretty/ESP32-S3_SuperMini_2x9.kicad_mod` is the drilled legacy +footprint referenced by Rev A.4.1. It is retained so the current schematic +resolves, but it is obsolete for the selected production mounting method. + +`JumpJet.pretty/ESP32-S3_SuperMini_2x9_Castellated_PROVISIONAL.kicad_mod` is an +unassigned iteration footprint for direct castellated soldering. Its body, +USB shell, nominal pitch/row spacing, and derived longitudinal registration use +the current physical evidence. Its receiving-land depth, antenna graphic, and +underside-contact exclusion remain provisional. It deliberately has no locating +holes because the previous coordinates do not reconcile with the updated +longitudinal datum. Do not release or assign it without the required 1:1 fit +check and completion of the blockers in the hardware register. + +Current evidence supports a solid carrier PCB beneath the ESP32 module: there +are no underside mounted components, but exposed underside contacts require an +isolation-controlled region. A mandatory central window is not supported by the +evidence. Underside contact mapping and the provisional antenna keepout remain +fabrication blockers. + +## Source-package exclusions + +The archive's repair, warning-cleanup, presentation, polish, and connector +changelog text files were not imported because they are historical packaging +notes rather than project dependencies. Lock files, autosaves, backups, +fabrication outputs, and temporary exports are also intentionally excluded. +The archive README is retained under `references/` as provenance. diff --git a/hardware/kicad/JumpJet_RevA/fp-lib-table b/hardware/kicad/JumpJet_RevA/fp-lib-table new file mode 100644 index 0000000..7b2b49d --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/fp-lib-table @@ -0,0 +1,3 @@ +(fp_lib_table + (lib (name "JumpJet")(type "KiCad")(uri "${KIPRJMOD}/JumpJet.pretty")(options "")(descr "JumpJet project footprints")) +) diff --git a/hardware/kicad/JumpJet_RevA/references/REV_A4_1_ARCHIVE_README.md b/hardware/kicad/JumpJet_RevA/references/REV_A4_1_ARCHIVE_README.md new file mode 100644 index 0000000..200c8fc --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/references/REV_A4_1_ARCHIVE_README.md @@ -0,0 +1,66 @@ +# JumpJet Controller Rev A.4.1 - multisheet draft + +Open `JumpJet_Controller_RevA4.kicad_pro`, then open the schematic. + +The design is split into four functional sheets: + +1. Power, protection, and switched outputs +2. ESP32-S3 controller and service interface +3. Thermistor signal conditioning +4. Qwiic, expansion, and test points + +Inter-sheet signals use global labels. + +## Programmatic schematic repair - 2026-08-25 + +This copy was repaired from the supplied Rev A.4.1 multisheet draft without changing the intended product architecture or treating provisional choices as finalized. + +Structural fixes include: + +- Corrected stock-symbol rotations where the generated symbol orientation did not match the wire geometry. +- Corrected generated anchor offsets for the 24 V to 5 V module, service header, Qwiic connector, and expansion header. +- Re-terminated wires and labels at actual KiCad electrical pin endpoints rather than symbol body edges. +- Repaired the existing 74AHCT125 buffer topology so each used channel has its intended PWM input, driven output, and active-low OE tied low; the unused channel input/OE remain low and its output remains explicitly NC. +- Restored the intended heater, blower, optional AUX, thermistor, Qwiic, service-header, and test-point connectivity. +- Removed redundant ADC alias labels that could create ambiguous net naming. +- Preserved the custom ESP32-S3 SuperMini 2x9 symbol/footprint numbering and the existing provisional GPIO assignment. + +`REPAIR_AUDIT.txt` records the programmatic structural/connectivity checks performed on this repaired copy. + +## Still provisional / must be engineered before fabrication + +This is **not fabrication-approved**. In particular, the following remain open or require independent verification: + +- `MOD1` exact converter module, pinout, transient behavior, and `BUCK_EN` policy +- Main/heater/Qwiic fuse selection and protection coordination +- TVS selection and clamp behavior versus the PSU and downstream devices +- MOSFET exact part numbers, gate-drive suitability, switching loss, SOA, thermal design, and derating +- Blower polarity, flyback strategy/component ratings, and airflow adequacy (nominal current now confirmed at ~0.36 A @ 24 V) +- PTC heater cold-start current and operating current +- Connector footprints, contact current ratings, wire gauge, PCB copper/trace/plane sizing, and clearances +- Thermistor beta/Steinhart-Hart coefficients, ADC range, fault thresholds, and calibration +- Thermal fuse / resettable thermal switch physical placement and system-level cutoff behavior +- ESP32 GPIO assignments, strapping constraints, and expansion pinout as final design choices + +The repaired files passed a custom structural/connectivity audit, but `kicad-cli` is not available in the repair environment. Open the project in KiCad and run ERC before treating the schematic as an engineering baseline. + + +## Presentation-only cleanup pass + +This copy was generated from the electrically repaired Rev A.4.1 baseline. The pass changes only visible schematic presentation (Reference/Value property positions, label justification, and annotation placement). It intentionally does not move electrical anchors, symbol bodies, wire endpoints, junctions, no-connect markers, or net labels. The same structural/connectivity audit must pass after this pass. + + +## Depth-safe final schematic polish + +This copy supersedes the earlier POLISHED archive. The earlier geometry pass accidentally relied on whitespace indentation to identify top-level KiCad objects; several repaired wires/labels had noncanonical indentation and were therefore left behind visually. This pass starts again from the connectivity-validated PRESENTATION baseline and identifies top-level objects from s-expression parenthesis depth, then applies the same rigid functional-block translations to every relevant object regardless of whitespace. No electrical design intent is changed. + +### Final cleanup correction + +The first POLISHED archive should be considered superseded. A whitespace-sensitive geometry pass had left several valid top-level wires/labels at their pre-polish coordinates because older repair scripts had given those objects noncanonical indentation. The corrected polish identifies top-level objects by KiCad s-expression depth, normalizes their indentation for auditing, and removes two stale local ADC alias labels (`OUT_ADC`, `CASE_ADC`) that conflicted with the canonical `TEMP_OUT_ADC` and `TEMP_CASE_ADC` nets. The complete structural/connectivity audit passes after these corrections. + +## J2 heater terminal selection +J2 is assigned to Phoenix Contact MKDS 1,5/2 (1715022), 5.00 mm pitch, 17.5 A nominal, using KiCad footprint `TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal`. The nominal heater load is ~8.3 A at 24 V. The heater's short fabric/nylon-jacketed leads may be extended externally with a suitably rated Wago-style splice; provide strain relief and use conductor/ferrule sizes allowed by the terminal and splice manufacturers. + + +## J3 blower connector selection +J3 is assigned to the standard 2-pin JST-XH board header footprint `Connector_JST:JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical`. The confirmed blower load is approximately 0.36 A at 24 V, comfortably within the JST-XH current class for this use. The intended mating housing is JST XHP-2 with suitable crimp contacts. Electrical connectivity and pin numbering are unchanged; verify final blower polarity before building the harness. diff --git a/hardware/kicad/JumpJet_RevA/sym-lib-table b/hardware/kicad/JumpJet_RevA/sym-lib-table new file mode 100644 index 0000000..fa0d03d --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name "JumpJet_Controller_RevA")(type "KiCad")(uri "${KIPRJMOD}/JumpJet_Controller_RevA.kicad_sym")(options "")(descr "JumpJet project symbols")) +)