From bb4db584221f2df5ee718e017b539ebf2b2db238 Mon Sep 17 00:00:00 2001 From: Daniel Brown <30573097+danielbrownjr@users.noreply.github.com> Date: Thu, 3 Sep 2026 08:20:09 -0400 Subject: [PATCH 01/20] docs: establish Phase 1 hardware register --- README.md | 10 +- docs/HARDWARE_BASELINE.md | 23 ++++- docs/PHASE1_HARDWARE_REGISTER.md | 163 +++++++++++++++++++++++++++++++ docs/PRODUCT_SAFETY_CONTRACT.md | 5 +- 4 files changed, 192 insertions(+), 9 deletions(-) create mode 100644 docs/PHASE1_HARDWARE_REGISTER.md diff --git a/README.md b/README.md index 7ad91a2..a7f24ce 100644 --- a/README.md +++ b/README.md @@ -51,9 +51,13 @@ about 130 °C at the heater/PTC region, and about 74–75 °C at the chassis. De sizing remains the rated 24 V / 200 W / 8.33 A case. That test did **not** validate the complete Jump Jet Q1/F2/PCB/connector/wiring -path or installed operation. The authoritative `.kicad_pcb` is still missing. -GPIO, ADC, thermistor, protection, and cooldown thresholds therefore remain TBD. -The Sanyo Denki 9GA0424P3J001 is only a prototype fan candidate, not BOM-final. +path or installed operation. The Rev A.4.1 schematic is the current hardware +authority. The Rev A PCB has not yet been created; PCB implementation and +validation are the current Phase-1 hardware work, not an artifact-recovery +problem. Detailed status and blockers are tracked in the +[Phase 1 hardware register](docs/PHASE1_HARDWARE_REGISTER.md). GPIO, ADC, +thermistor, protection, and cooldown thresholds therefore remain TBD. The Sanyo +Denki 9GA0424P3J001 is only a prototype fan candidate, not BOM-final. ## Safety boundary diff --git a/docs/HARDWARE_BASELINE.md b/docs/HARDWARE_BASELINE.md index 6415ac4..9b60547 100644 --- a/docs/HARDWARE_BASELINE.md +++ b/docs/HARDWARE_BASELINE.md @@ -1,4 +1,14 @@ -# Hardware baseline — not commissioned +# Hardware baseline — Rev A Phase 1 + +Rev A.4.1 is the current authoritative schematic baseline. It is intentionally +schematic-only: there is no missing authoritative PCB artifact to recover. The +first Rev A `.kicad_pcb` is being created as the next Phase-1 implementation +stage. + +The detailed living source of truth for measurements, component candidates, +design decisions, provisional values, blockers, and validation status is the +[Phase 1 hardware register](PHASE1_HARDWARE_REGISTER.md). Presence in that +register does not make a candidate BOM-final or approve fabrication. ## Confirmed @@ -12,10 +22,10 @@ ## Not confirmed -The authoritative `.kicad_pcb` remains missing. Q1, F2, PCB copper, connectors, -wiring, installed airflow, the exact ESP32-S3 module, and the complete power path -have not been validated together. The upstream Jetpack pin assignments are -historical facts, not Jump Jet assignments. +Q1, F2, PCB copper, connectors, wiring, installed airflow, the exact ESP32-S3 +module implementation, and the complete power path have not been validated +together. The upstream Jetpack pin assignments are historical facts, not Jump +Jet assignments. No GPIO, ADC, divider, thermistor conversion, fan/PWM method, protection threshold, thermal trip, cooldown criterion, or recovery threshold may be finalized without @@ -28,5 +38,8 @@ GPIO, placeholder pin, PWM, ADC, thermistor conversion, or MOSFET actuation path The provisional numeric limit header was removed because unvalidated values are not a hardware contract. +Heater actuation remains disabled while the safety-critical hardware design and +validation progress. + The build retains a provisional 4 MiB dual-OTA partition layout solely as an ESP32-S3 development baseline. It is not a release hardware constraint. diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md new file mode 100644 index 0000000..0311f20 --- /dev/null +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -0,0 +1,163 @@ +# Phase 1 hardware source-of-truth register + +Last updated: 2026-09-03 + +This is the living engineering register for JumpJet Rev A Phase-1 hardware +implementation. It records what is known, how it is known, what remains +provisional, and which downstream decisions are blocked. Rev A.4.1 is the +current authoritative schematic baseline; the first Rev A PCB is being created +as part of Phase 1. + +> **Presence in this register does not mean BOM-final, fabrication-approved, or +> release-approved. Only the explicit status field carries authority.** + +## Status legend + +| Status | Meaning | +|---|---| +| CONFIRMED FACT | Supported by an authoritative project artifact or direct evidence; not merely inferred. | +| MEASURED | Directly measured, with the measurement conditions and source identified. | +| DESIGN DECISION | Deliberately selected architecture or requirement; implementation may still need validation. | +| STRONG CANDIDATE | Preferred component candidate with substantial support, but not BOM-final. | +| PROTOTYPE CANDIDATE | Part selected for characterization or prototyping only. | +| ASSUMPTION / PROVISIONAL | Working value or approach that must not be treated as final. | +| TBD / BLOCKED | Required information or selection is absent and blocks one or more downstream activities. | + +Confidence describes the quality of the current evidence, not release readiness. +The **Blocks** column identifies what cannot be frozen or completed until the +remaining validation closes. + +## 1. System electrical basis + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| System voltage | CONFIRMED FACT | 24 V system architecture. | Rev A.4.1 schematic; [CZ4060 characterization](hardware/cz4060-characterization.md) | High | Validate production-supply tolerance and transients with the complete assembly. | BOM freeze + Fabrication | +| CZ4060 conservative design basis | CONFIRMED FACT | Size the heater path for 24 V, 200 W, and 8.33 A. | Heater rating and [CZ4060 characterization](hardware/cz4060-characterization.md), commit `903e5e0cdfc7a17102d51de1c01fa414be613b92` | High | Validate every production current-path element at this design load and installed temperature. | PCB layout + BOM freeze + Fabrication | +| Standalone sustained load | MEASURED | Approximately 189 W and 7.89 A at 24 V. | 60-minute standalone run in [CZ4060 characterization](hardware/cz4060-characterization.md) | High for tested specimen and setup | Repeat or bound unit-to-unit behavior; validate installed full-path voltage drop and temperature. | BOM freeze + Fabrication | +| Standalone startup | MEASURED | Approximately 196 W peak observed; no high-current cold inrush observed. Current rose over several minutes while the bench supply remained in CV mode. | Startup test in [CZ4060 characterization](hardware/cz4060-characterization.md) | High for tested specimen and setup | Confirm behavior with the production PSU, wiring, controls, and additional heater specimens. | BOM freeze + Fabrication | +| Standalone thermal behavior | MEASURED | Heater/PTC region approximately 130 °C steady; chassis approximately 74–75 °C steady. These are characterization results, not firmware or protection thresholds. | 60-minute standalone run in [CZ4060 characterization](hardware/cz4060-characterization.md) | High for tested specimen and setup | Installed-system mapping with production airflow, sensor placement, fault cases, and materials. | Firmware constants + BOM freeze + Fabrication | +| Cold DMM resistance | MEASURED | Approximately 20–21 Ω was observed cold, but it is not authoritative for heater-path sizing. Use the powered measurements and 8.33 A conservative design basis. | Cold-resistance note in [CZ4060 characterization](hardware/cz4060-characterization.md) | High | None for current-path design basis. | None | + +Firmware thresholds must not be derived directly from the standalone heater +temperatures. + +## 2. ESP32-S3 Super Mini mechanical implementation + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Module PCB body | MEASURED | 23.67 mm long × 17.91 mm wide. | Physical measurement of the actual module | High | Confirm against the 1:1 production-footprint plot before freeze. | Fabrication | +| Overall length including USB-C | MEASURED | 25.07 mm. | Physical measurement of the actual module | High | Confirm connector projection and carrier-board relationship on the 1:1 plot. | PCB layout + Fabrication | +| USB-C overhang | MEASURED | Approximately 1.40 mm beyond the module PCB edge. This is a datum, not a complete connector keepout. | Physical measurement of the actual module | High for overhang only | Measure shell width, height, position, mating plug, cable-head envelope, and enclosure access. | PCB layout + Fabrication | +| Pad count | CONFIRMED FACT | Nine castellations per side; 18 total. | Physical inspection of the actual module | High | Verify every pad number and label against the actual module silkscreen. | PCB layout + Fabrication | +| Nominal pin pitch | ASSUMPTION / PROVISIONAL | 2.54 mm; supported by an approximately 20.0 mm measured span across eight intervals, versus 20.32 mm nominal. | Physical measurement and derived nominal geometry | High | 1:1 physical placement and direct center-to-center verification. | PCB layout + Fabrication | +| Nominal row spacing | ASSUMPTION / PROVISIONAL | 15.24 mm; supported by an approximately 15.2 mm physical measurement. | Physical measurement and derived nominal geometry | High | 1:1 physical placement and direct row-center verification. | PCB layout + Fabrication | +| Side edge to row center | ASSUMPTION / PROVISIONAL | Approximately 1.335 mm, derived as `(17.91 - 15.24) / 2`. | Derived from measured body width and provisional nominal row spacing | Medium | Measure actual castellation centerline relative to both module edges. | PCB layout + Fabrication | +| End to first/last pin center | ASSUMPTION / PROVISIONAL | Approximately 1.675 mm if symmetric, derived as `(23.67 - 20.32) / 2`. | Derived from measured body length and provisional nominal pitch | Medium | Measure the actual longitudinal registration; do not assume symmetry. | PCB layout + Fabrication | +| Castellation receiving lands | TBD / BLOCKED | Pad width and depth are intentionally undefined. | No authoritative physical dimensions or trusted revision-matched drawing available | High confidence that evidence is missing | Measure castellation width, inward depth, plating/mask geometry, and body registration. | PCB layout + Fabrication | +| Production mounting | DESIGN DECISION | Direct solder of the castellated module to carrier-PCB SMD lands. The current drilled through-hole footprint is not the production architecture unless later physical verification explicitly reverses this decision. | Phase-1 mounting decision; inspection of Rev A.4.1 project footprint | High | Complete and physically verify the project-local castellated footprint. | PCB layout + Fabrication | +| Central underside PCB window | DESIGN DECISION | Provide a carrier-PCB window for underside component clearance, inspection/cleaning, avoiding a header/standoff dependency, and reducing trapped heat. It is not a safety airflow feature. | Phase-1 mechanical decision | High | Measure underside X/Y envelope, maximum height, solder/metal features, support regions, and required FR-4 rail widths. | PCB layout + Fabrication | +| Underside window geometry | TBD / BLOCKED | No length, width, corner, or support-rail dimensions are frozen. | Required physical underside measurements are unavailable | High confidence that evidence is missing | Complete underside measurements and structural/routing review. | PCB layout + Fabrication | +| Optional temporary locating holes | DESIGN DECISION | Two holes total, one at each end of one castellated row, for a removable 2.54 mm header assembly aid. They are not electrical pins or production attachment. | Phase-1 assembly decision | High | Measure the actual header posts; select NPTH/PTH; establish hole diameter and coordinates; check rails, USB, antenna, window, and removal clearance. | PCB layout + Fabrication | +| Locating-hole geometry | TBD / BLOCKED | Exact diameter, plating, copper, and coordinates are not frozen. | Header and final module geometry have not been physically verified | High confidence that evidence is missing | Fit-test actual temporary header against a true-scale footprint and fabricator tolerances. | PCB layout + Fabrication | +| Antenna keepout | TBD / BLOCKED | Location, dimensions, and applicable copper layers are undefined. | Actual module antenna has not been physically identified and measured | High confidence that evidence is missing | Identify antenna on the actual revision; measure prohibited region; define copper/trace/component restrictions. | PCB layout + Fabrication | +| USB-C mechanical keepout | TBD / BLOCKED | Full shell, plug, cable-head, carrier-edge, and enclosure access envelope is undefined. | Only overall length and approximate overhang have been measured | High confidence that evidence is missing | Complete physical connector and service-access measurements. | PCB layout + Fabrication | +| Mandatory 1:1 verification | DESIGN DECISION | The actual module must be placed on a true-scale plot before footprint freeze. All 18 castellations, body, Pin 1, locating holes, USB projection, antenna direction, and underside window must pass without forced alignment. | Phase-1 acceptance requirement | High | Perform and document the physical fit check using the final proposed footprint. | Fabrication | + +## 3. ESP32 power architecture + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Production power path | DESIGN DECISION | Protected 24 V rail → onboard 24 V-to-5 V regulator → regulated 5 V → ESP32-S3 Super Mini external 5 V/VBUS input. Raw 24 V must never reach the module. | Phase-1 power architecture decision | High | Verify the module power pin and internal USB/external-5 V topology; select and qualify the regulator and source isolation. | PCB layout + BOM freeze + Fabrication | +| USB-C role | DESIGN DECISION | Programming, debug, recovery, and service only; not the normal installed power source. | Phase-1 service architecture decision | High | Validate every USB-only and mixed-supply power state. | PCB layout + Fabrication | +| External 5 V/VBUS pin | TBD / BLOCKED | Rev A.4.1 mapping must not substitute for physical verification of the exact module pin. | No actual-module label/circuit verification recorded | High confidence that evidence is missing | Verify the physical pin label, numbering, and electrical connection. | PCB layout + Fabrication | +| USB/external-5 V relationship | TBD / BLOCKED | Unknown whether USB-C VBUS and the external 5 V pin are directly connected, diode-ORed, switched, or otherwise isolated. | No trustworthy revision-matched schematic or circuit inspection | High confidence that evidence is missing | Inspect/trace the actual module and test onboard-only, USB-only, and simultaneous-source behavior. | PCB layout + BOM freeze + Fabrication | +| Backfeed protection | TBD / BLOCKED | Final need and implementation for Schottky OR-ing, ideal-diode/load-switch isolation, USB-VBUS isolation, or a service-power selector is unresolved. | Depends on actual module topology and measured source behavior | High confidence that decision is blocked | Prove that USB cannot backfeed the buck/24 V system, onboard 5 V cannot unexpectedly source a USB host, and supplies cannot contend. | PCB layout + BOM freeze + Fabrication | +| Buck converter | TBD / BLOCKED | No MPN or final rating selected. Must support ESP32-S3 peaks/Wi-Fi bursts, boot transients, shared 74AHCT125 and fan-interface loads, other actual 5 V loads, and engineering margin. | Load inventory and installed thermal environment incomplete | High confidence that selection is blocked | Complete load inventory; evaluate voltage/transient rating, output current, efficiency, dissipation, reverse current, startup, and installed-temperature derating. | PCB layout + BOM freeze + Fabrication | +| Power-management firmware assumptions | TBD / BLOCKED | No firmware behavior may assume a source topology or power-good behavior that has not been established in hardware. | Power architecture unresolved | High | Close power-state truth table and any available power-good/reset behavior. | Firmware constants | + +## 4. Heater path and independent interruption + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Rev A.4.1 heater path | CONFIRMED FACT | `+24V_PROT -> F2 -> TF1 -> TS1 -> J2 -> external heater -> Q1 -> GND` | Current Rev A.4.1 schematic | High | Recheck connectivity after every schematic revision and against the first PCB. | PCB layout + Fabrication | +| Independent series protection | CONFIRMED FACT | TF1 and TS1 are physically in series with heater current; firmware is not the sole means of heater interruption. | Current Rev A.4.1 schematic | High for topology | Select and validate final parts, mounting, temperatures, current capacity, and installed fault behavior. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Complete heater-current path | TBD / BLOCKED | The assembled path has not been validated for voltage drop, heating, or fault interruption. | [CZ4060 characterization](hardware/cz4060-characterization.md) explicitly excludes Q1, F2, PCB copper, connectors, wiring, and installed behavior | High confidence that validation is incomplete | Validate final parts, PCB geometry, full-path voltage drop, component/copper temperatures, and installed fault cases. | BOM freeze + Fabrication | + +## 5. Q1 heater MOSFET and gate drive + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Q1 candidate | STRONG CANDIDATE | Texas Instruments CSD18540Q5B; 60 V logic-level N-MOSFET; maximum `RDS(on)` approximately 3.3 mΩ at 4.5 V. Not BOM-final. | Manufacturer data and Phase-1 component review | High for published characteristics | Reconfirm ordering code, lifecycle, package, pin/multipad mapping, and production availability. | PCB layout + BOM freeze + Fabrication | +| Estimated Q1 conduction loss | ASSUMPTION / PROVISIONAL | About 0.205 W at 7.89 A and 0.229 W at 8.33 A using 3.3 mΩ: `P = I²R`. These are max-`RDS(on)`-basis conduction estimates only, not total hot operating loss. | Candidate data and measured/design currents | Medium | Include hot `RDS(on)`, switching loss, duty/frequency, gate waveform, copper spreading, and measured junction/board temperature. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Gate-drive concept | ASSUMPTION / PROVISIONAL | 5 V 74AHCT125, provisional 47 Ω gate resistor, and hardware gate pull-down with default-OFF intent. | Current Rev A.4.1 schematic concept | Medium | Verify power sequencing/default-OFF behavior, buffer enable strategy, partial-power paths, gate waveform, switching loss, and suitability at the chosen PWM frequency. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Q1 footprint and thermal implementation | TBD / BLOCKED | Exact verified KiCad footprint, thermal-pad implementation, and copper spreading are not frozen. | Footprint/PCB validation not completed | High confidence that implementation is incomplete | Verify package drawing and pad mapping; complete thermal/current layout and measurement plan. | PCB layout + Fabrication | + +## 6. F2 fuse and holder + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| F2 fuse candidate | STRONG CANDIDATE | Littelfuse 0287015.U, 15 A ATOF. Not BOM-final. The 15 A candidate provides healthier margin around the approximately 7.9–8.33 A load than a 10 A fuse after elevated-temperature derating. | Heater characterization, conservative design basis, and Phase-1 component review | Medium-high | Validate production-PSU short-circuit/current-limit behavior, time-current coordination, ambient derating, interrupt behavior, and service conditions. | PCB layout + BOM freeze + Fabrication | +| F2 holder candidate | STRONG CANDIDATE | Littelfuse 178.6165.0001. Not BOM-final. | Phase-1 component review | Medium-high | Verify exact footprint, current/temperature performance, pad and copper heating, mechanical retention, and removal/service clearance. | PCB layout + BOM freeze + Fabrication | + +## 7. J2 and heater wiring + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| J2 candidate | STRONG CANDIDATE | Phoenix Contact 1715022 / MKDS 1,5/2; nominal IEC current approximately 17.5 A. The 8.33 A heater basis is approximately 48% of that nominal value. Not BOM-final. | Manufacturer rating and Phase-1 component review | Medium-high | Verify exact footprint, conductor/ferrule compatibility, torque, terminal and pad temperature, creepage/clearance, and service access. | PCB layout + BOM freeze + Fabrication | +| Heater wire | DESIGN DECISION | Use 16 AWG high-temperature-insulated wire, with approximately 200 °C-class insulation near the heater. | Current requirement and heater thermal environment | High for direction | Finalize insulation construction, color, length, routing, bend radius, abrasion protection, and installed-temperature margin. | BOM freeze + Fabrication | +| Wire family | STRONG CANDIDATE | TE Connectivity/Raychem Spec 55 family; examples 55/0212-16-2 red and 55/0212-16-0 black. Not BOM-final. | Phase-1 wiring review | Medium | Verify exact construction, approvals, availability, termination method, voltage drop, and harness temperature. | BOM freeze | +| Heater termination details | TBD / BLOCKED | Ferrule type, terminal torque, strain relief, wire length, voltage drop, and terminal/harness temperatures are not frozen. | Harness and installed validation incomplete | High confidence that details are incomplete | Build and thermally validate the production-intent harness and termination. | BOM freeze + Fabrication | +| JST-XH heater use | DESIGN DECISION | JST-XH is not acceptable for the approximately 8 A heater-current path. | Current-path requirement | High | None; maintain this exclusion through schematic and PCB review. | None | + +## 8. Fan architecture and prototype + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Original integrated fan | CONFIRMED FACT | YD4020HBL, 24 V, 0.13 A, two-wire, no native PWM, and no tach. Its two-wire control architecture has been superseded by the four-wire PWM/tach direction. | Physical/product identification from CZ4060 assembly review | Medium-high | Confirm nameplate and electrical behavior if retained for comparative testing only. | None | +| Replacement fan prototype | PROTOTYPE CANDIDATE | Sanyo Denki 9GA0424P3J001; ordered for characterization, ETA 2026-09-15. Not BOM-final. | Prototype purchase record | High for order state; unvalidated for application | Complete electrical, airflow, pressure, acoustic, thermal, stall, and installed-system characterization. | BOM freeze + Firmware constants | +| Four-wire fan architecture | DESIGN DECISION | Continuous fused 24 V fan power, separate PWM control, and separate tach/RPM feedback. Do not low-side PWM the fan's 24 V supply when using native four-wire control. | Phase-1 fan architecture decision | High | Verify candidate interface requirements and qualify final fan/control parts. | PCB layout + BOM freeze + Fabrication | +| Fan PWM interface | ASSUMPTION / PROVISIONAL | Provide a fan-compatible open-drain interface; exact circuit and component values remain pending datasheet and bench verification. | Common four-wire architecture and Phase-1 direction; candidate-specific evidence incomplete | Medium | Verify pinout, PWM voltage/current/frequency requirements, pull-up behavior, open/high-Z behavior, and 0% behavior. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Fan tach interface | TBD / BLOCKED | Tach output type, pull-up rail/value, pulses per revolution, filtering, protection, and stall semantics are not established. | Prototype not yet characterized | High confidence that evidence is missing | Characterize output electrically and across startup, minimum speed, normal operation, and locked rotor. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Fan performance envelope | TBD / BLOCKED | Startup/steady current, minimum reliable PWM/speed, RPM versus duty, CZ4060 airflow/static pressure, locked-rotor behavior, stall-detection latency, hub temperature, installed chamber margin, cooldown versus RPM, and minimum safe airflow/RPM remain unknown. | Prototype characterization pending | High confidence that evidence is missing | Complete bench and installed-system characterization. Do not freeze RPM thresholds beforehand. | BOM freeze + Firmware constants | + +The first PCB may include configurable interface provisions, but fabrication is +acceptable only if the unresolved interface is deliberately bounded and does not +require unsupported electrical assumptions. + +## 9. Independent thermal protection + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| TF1 and TS1 schematic values | TBD / BLOCKED | Rev A.4.1 placeholders are TF1 75 °C / 15 A and TS1 normally closed 75 °C / 16 A. The 75 °C values are not finalized production selections. | Current Rev A.4.1 schematic and standalone thermal results | High confidence that placeholders are not validated | Select temperatures only after installed-system thermal and fault mapping. | BOM freeze + Firmware constants + Fabrication | +| Thermal-device families | ASSUMPTION / PROVISIONAL | SCHOTT SEFUSE SF and Protherm 03EC are families to investigate, not selected parts and not BOM-final. | Phase-1 component-family review | Low-medium | Establish exact construction, package, current/voltage rating, trip tolerance, mounting method, aging, availability, and approvals. | PCB layout + BOM freeze + Fabrication | +| Protection ordering | DESIGN DECISION | `normal operating ceiling < firmware hard trip < independent hardware cutoff < lowest applicable material/component limit` with justified margins. | JumpJet safety architecture | High | Establish every numeric boundary from installed measurements and component/material limits. | BOM freeze + Firmware constants + Fabrication | +| Installed thermal evidence | TBD / BLOCKED | Required measurements include TF1 body, TS1 body, heater hotspot, chamber, enclosure/material, wiring, and connector temperatures under normal, failed-fan, restricted-airflow, and heater-stuck-on cases. | Standalone characterization explicitly does not cover installed behavior | High confidence that evidence is missing | Complete production-intent installed thermal mapping and fault testing. | BOM freeze + Firmware constants + Fabrication | + +The approximately 130 °C heater/PTC and 74–75 °C chassis measurements do not +identify a valid production cutoff temperature or mounting location. + +## 10. PCB implementation + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Rev A PCB state | CONFIRMED FACT | PCB design is the current Rev A implementation stage. There is no missing authoritative PCB artifact to recover; a `.kicad_pcb` has not yet been created and must now be designed. | Rev A.4.1 package scope and Phase-1 project state | High | Create and review the first Rev A PCB from the authoritative schematic. | PCB layout + Fabrication | +| Starting stackup | ASSUMPTION / PROVISIONAL | Two layers, 1.6 mm FR-4, 2 oz copper. | Phase-1 routing/current-density starting point | Medium | Review high-current routing, grounding, RF, mechanical, thermal, cost, and PCBWay manufacturing requirements before freeze. | PCB layout + BOM freeze + Fabrication | +| Heater-path copper geometry | ASSUMPTION / PROVISIONAL | Keep heater-path neckdowns at least 4 mm as an initial minimum; prefer broad 8–10 mm or wider pours where practical; minimize vias and unnecessary current-loop area. Place the high-current/safety path before convenience circuitry. | 8.33 A conservative design basis and Phase-1 layout direction | Medium | Calculate and inspect every bottleneck, layer transition, pad entry, thermal relief, and temperature rise for the final stackup. | PCB layout + Fabrication | +| Ground and return strategy | DESIGN DECISION | Prefer a continuous ground plane with a controlled heater/fan/buck high-current return corridor. Thermistor/ADC returns must not share narrow or common-impedance copper with heater current. Do not create arbitrary split grounds that damage ESP32 RF return integrity. | Phase-1 signal-integrity and current-return strategy | High for topology; implementation provisional | Review actual return geometry, buck loops, ADC noise, RF keepout, and current-path coupling after placement/routing. | PCB layout + Fabrication | +| High-current placement priority | DESIGN DECISION | Place and review `+24V_PROT -> F2 -> TF1 -> TS1 -> J2 -> heater -> Q1 -> GND` before convenience circuitry. Keep Q1, J2, F2, and the heater-current path compact without weakening conductor geometry for appearance. | Rev A.4.1 topology and Phase-1 implementation priority | High | Complete placement, current-loop, service-clearance, and thermal review. | PCB layout + Fabrication | +| PCB validation | TBD / BLOCKED | Current-density bottlenecks, Q1 thermal spreading, fuse-holder and J2 pad heating, high-current return geometry, ADC noise, antenna keepout, DRC, fabricated-board temperature rise, and full-path voltage drop are unvalidated. | No Rev A PCB exists yet | High confidence that validation is pending | Create the board, review design evidence, fabricate only after blockers close, then thermally/electrically test production-intent hardware. | PCB layout + BOM freeze + Fabrication | + +## Register maintenance rules + +- Preserve the exact status classes defined in this document. +- Change a status only when the evidence/source and remaining-validation fields + are updated at the same time. +- A `STRONG CANDIDATE` or `PROTOTYPE CANDIDATE` does not become BOM-final by + appearing here. +- Record contradictions and failed validation directly; do not silently replace + inconvenient evidence. +- Link measurement reports, schematic revisions, datasheets, test records, and + relevant commits wherever practical. +- Keep firmware GPIOs, ADC constants, PWM/RPM thresholds, thermal thresholds, + and recovery limits provisional until the corresponding hardware evidence is + complete. diff --git a/docs/PRODUCT_SAFETY_CONTRACT.md b/docs/PRODUCT_SAFETY_CONTRACT.md index abf86cf..b6ed402 100644 --- a/docs/PRODUCT_SAFETY_CONTRACT.md +++ b/docs/PRODUCT_SAFETY_CONTRACT.md @@ -93,7 +93,10 @@ Those temperatures are observations, not firmware thresholds. ## Hardware-dependent TBDs The full Q1/F2/PCB copper/connectors/wiring path is not validated, and the -authoritative `.kicad_pcb` is missing. Final GPIO, ADC, thermistor conversion, +Rev A.4.1 schematic is the current hardware authority. The Rev A PCB layout does +not yet exist and must be implemented and validated during Phase 1. Hardware +actuation remains blocked until the resulting PCB/current path and the other +safety-critical hardware are validated. Final GPIO, ADC, thermistor conversion, protection thresholds, cooldown criteria, and recovery thresholds must not be invented. Sanyo Denki 9GA0424P3J001 is a prototype fan candidate only and is not BOM-final. From 49def2ff0c2bdaec5017c588e834796cd490e618 Mon Sep 17 00:00:00 2001 From: Daniel Brown <30573097+danielbrownjr@users.noreply.github.com> Date: Thu, 3 Sep 2026 05:33:56 -0700 Subject: [PATCH 02/20] docs: synchronize Phase 1 hardware status --- ROADMAP.md | 8 +++--- TODO.md | 46 ++++++++++++++++++++++++++++---- docs/PHASE1_HARDWARE_REGISTER.md | 35 ++++++++++++++++++++---- 3 files changed, 76 insertions(+), 13 deletions(-) diff --git a/ROADMAP.md b/ROADMAP.md index 1687275..6ced298 100644 --- a/ROADMAP.md +++ b/ROADMAP.md @@ -19,10 +19,12 @@ no phase passes its gate without the listed evidence. ## Phase 1 — freeze the hardware contract -**Status:** next +**Status:** active -- review the current schematic, PCB layout, BOM, enclosure, and airflow path -- confirm the exact ESP32-S3 module, flash size, GPIO map, and boot-strap constraints +- use Rev A.4.1 as the current authoritative schematic baseline +- freeze the hardware contract and create/review the first Rev A PCB during Phase 1 +- review the BOM, enclosure, mechanical interfaces, and airflow path +- confirm the exact ESP32-S3 Super Mini revision, flash size, GPIO map, and boot-strap constraints - identify heater, MOSFET, fans, thermistors, connectors, fuse, thermal cutoff, and switch - calculate steady and worst-case current, connector loading, copper temperature rise, MOSFET dissipation, gate drive, voltage drop, ADC range, and protection margins diff --git a/TODO.md b/TODO.md index 8269f11..2f11839 100644 --- a/TODO.md +++ b/TODO.md @@ -6,19 +6,48 @@ implementation starts, and keep only the summary checkbox here. ## Needed from the current hardware design -- [ ] Add or link the current KiCad schematic and PCB source +- [x] Review the Rev A.4.1 schematic package and record it as the current + authoritative schematic baseline in the + [Phase 1 hardware register](docs/PHASE1_HARDWARE_REGISTER.md) +- [ ] Create the first Rev A `.kicad_pcb` after the mechanical and electrical + layout blockers close - [ ] Add the current BOM with manufacturer part numbers and acceptable substitutions -- [ ] Confirm the exact ESP32-S3 module/dev board and installed flash size +- [x] Identify the physical controller module as an ESP32-S3 Super Mini +- [x] Record the measured ESP32-S3 Super Mini envelope and provisional nominal + pin geometry +- [ ] Verify the installed ESP32-S3 Super Mini flash size +- [ ] Complete the production castellated footprint after castellation dimensions, + exact registration, underside envelope/height, antenna keepout, USB access + envelope, Pin 1, and physical pin numbering are verified - [ ] Confirm the complete GPIO/ADC assignment, including boot strapping and USB pins - [x] Record standalone CZ4060 rated and measured power/current at 24 V - [ ] Validate the full Jump Jet Q1/F2/PCB/connector/wiring path at the 200 W / 8.33 A design basis -- [ ] Finalize both fan part numbers, current, connector, PWM method, and tach availability (9GA0424P3J001 is prototype-only) +- [x] Select the native four-wire fan architecture: continuous fused 24 V power, + separate open-drain PWM, and separate tach feedback +- [ ] Characterize the 9GA0424P3J001 prototype and finalize candidate-specific + pinout, current, connector, PWM/tach electrical details, RPM behavior, and + stall thresholds; it remains prototype-only - [ ] Record every thermistor part number, beta/Steinhart-Hart data, tolerance, and location - [ ] Confirm the MOSFET part, gate network, thermal environment, and default-off circuitry - [ ] Confirm fuse type/rating, independent thermal-cutoff part/rating, and physical placement - [ ] Define what the physical switch interrupts or commands - [ ] Add the latest enclosure/duct model and intended airflow direction +### Current PCB/fabrication blockers + +- [ ] Define the board outline, mounting-hole coordinates, connector-facing + edges, and USB mechanical datum +- [ ] Measure ESP32 castellation dimensions and exact body/pad registration +- [ ] Measure the ESP32 underside component envelope and maximum height +- [ ] Identify and measure the actual ESP32 antenna keepout +- [ ] Measure the USB-C shell, mating-plug, cable-head, and service-access envelope +- [ ] Establish the external 5 V / USB-C VBUS topology and mixed-source backfeed behavior +- [ ] Verify the Q1 footprint and multipad mapping +- [ ] Verify the F2 holder footprint and service/removal clearance +- [ ] Select TF1/TS1 parts and their mounting/thermal-coupling architecture +- [ ] Select and verify J1, F1, and MOD1 parts and footprints +- [ ] Characterize the production PSU current limit and complete fuse coordination + ## Firmware — immediate - [x] Add last-success sample age to `dc_prusa_status_t` in Dan's `dragon-core` fork @@ -39,10 +68,17 @@ implementation starts, and keep only the summary checkbox here. ## Electrical and safety analysis - [ ] Draw the complete 24 V power and return path from supply through protection to loads -- [ ] Calculate normal, startup, and credible fault current for heater plus both fans +- [ ] Calculate normal, startup, and credible fault current for the heater plus + all final fan and auxiliary loads - [ ] Calculate connector/contact loading and wire ampacity with temperature derating - [ ] Calculate MOSFET conduction and switching loss at worst-case voltage, current, duty, and ambient -- [ ] Check gate voltage/current, pull-down behavior, MCU reset behavior, and MOSFET SOA +- [ ] Correct gate-driver OE so heater drive is hardware-default-disabled during + power-up, power-down, reset, and brownout +- [ ] Ensure USB/service power cannot energize the gate-driver power domain or Q1 +- [ ] Verify gate-driver partial-power-down behavior or provide equivalent isolation +- [ ] Retain a direct Q1 gate pull-down independent of MCU and buffer state +- [ ] Add test points for the gate-driver power domain, gate-driver OE, and Q1 gate +- [ ] Check gate voltage/current, MCU reset behavior, switching waveform, and MOSFET SOA - [ ] Calculate trace/via current capacity and expected copper temperature rise - [ ] Calculate thermistor-divider voltage and ADC counts over open, short, and operating range - [ ] Define independent thermal-cutoff trip temperature from measured enclosure hot spots diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index 0311f20..a9a61c3 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -58,7 +58,7 @@ temperatures. | Central underside PCB window | DESIGN DECISION | Provide a carrier-PCB window for underside component clearance, inspection/cleaning, avoiding a header/standoff dependency, and reducing trapped heat. It is not a safety airflow feature. | Phase-1 mechanical decision | High | Measure underside X/Y envelope, maximum height, solder/metal features, support regions, and required FR-4 rail widths. | PCB layout + Fabrication | | Underside window geometry | TBD / BLOCKED | No length, width, corner, or support-rail dimensions are frozen. | Required physical underside measurements are unavailable | High confidence that evidence is missing | Complete underside measurements and structural/routing review. | PCB layout + Fabrication | | Optional temporary locating holes | DESIGN DECISION | Two holes total, one at each end of one castellated row, for a removable 2.54 mm header assembly aid. They are not electrical pins or production attachment. | Phase-1 assembly decision | High | Measure the actual header posts; select NPTH/PTH; establish hole diameter and coordinates; check rails, USB, antenna, window, and removal clearance. | PCB layout + Fabrication | -| Locating-hole geometry | TBD / BLOCKED | Exact diameter, plating, copper, and coordinates are not frozen. | Header and final module geometry have not been physically verified | High confidence that evidence is missing | Fit-test actual temporary header against a true-scale footprint and fabricator tolerances. | PCB layout + Fabrication | +| Locating-hole geometry | ASSUMPTION / PROVISIONAL | Candidate holes are Ø1.10 mm NPTH with no copper at X = −7.620 mm, Y = ±12.700 mm. Provisional footprint datum: origin at the module PCB geometric center; X runs across module width, Y runs along module length, and USB-C is at negative Y. The geometry is not final. | Phase-1 mounting/assembly-aid review using nominal 2.54 mm row extension and a nominal 0.635 mm square header-post concept | Medium | Measure the actual header; verify finished-hole and positional tolerances; physically fit-test insertion/removal; check interference with lands, support rails, window, antenna, and USB. | PCB layout + Fabrication | | Antenna keepout | TBD / BLOCKED | Location, dimensions, and applicable copper layers are undefined. | Actual module antenna has not been physically identified and measured | High confidence that evidence is missing | Identify antenna on the actual revision; measure prohibited region; define copper/trace/component restrictions. | PCB layout + Fabrication | | USB-C mechanical keepout | TBD / BLOCKED | Full shell, plug, cable-head, carrier-edge, and enclosure access envelope is undefined. | Only overall length and approximate overhang have been measured | High confidence that evidence is missing | Complete physical connector and service-access measurements. | PCB layout + Fabrication | | Mandatory 1:1 verification | DESIGN DECISION | The actual module must be placed on a true-scale plot before footprint freeze. All 18 castellations, body, Pin 1, locating holes, USB projection, antenna direction, and underside window must pass without forced alignment. | Phase-1 acceptance requirement | High | Perform and document the physical fit check using the final proposed footprint. | Fabrication | @@ -67,12 +67,13 @@ temperatures. | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | |---|---|---|---|---|---|---| -| Production power path | DESIGN DECISION | Protected 24 V rail → onboard 24 V-to-5 V regulator → regulated 5 V → ESP32-S3 Super Mini external 5 V/VBUS input. Raw 24 V must never reach the module. | Phase-1 power architecture decision | High | Verify the module power pin and internal USB/external-5 V topology; select and qualify the regulator and source isolation. | PCB layout + BOM freeze + Fabrication | -| USB-C role | DESIGN DECISION | Programming, debug, recovery, and service only; not the normal installed power source. | Phase-1 service architecture decision | High | Validate every USB-only and mixed-supply power state. | PCB layout + Fabrication | +| Production power domains | DESIGN DECISION | Protected 24 V feeds the onboard buck. Its buck-only `+5V_SYS/GATE` domain powers gate-drive circuitry. A separately isolated or source-selected `+5V_MCU` domain feeds the ESP32-S3 Super Mini external 5 V/VBUS input. Raw 24 V must never reach the module, and USB service power must never energize gate-drive circuitry. | Phase-1 power-domain and service-safety decision | High | Verify module power pin/topology; select and qualify the regulator, isolation/source-selection method, sequencing, and power-domain implementation. | PCB layout + BOM freeze + Fabrication | +| USB-C role | DESIGN DECISION | Programming, debug, recovery, and service only; not the normal installed power source. USB-only MCU power must not energize the gate-driver domain or enable Q1. | Phase-1 service architecture decision | High | Validate every USB-only and mixed-supply power state and observe gate/OE during attach/remove. | PCB layout + Fabrication | | External 5 V/VBUS pin | TBD / BLOCKED | Rev A.4.1 mapping must not substitute for physical verification of the exact module pin. | No actual-module label/circuit verification recorded | High confidence that evidence is missing | Verify the physical pin label, numbering, and electrical connection. | PCB layout + Fabrication | | USB/external-5 V relationship | TBD / BLOCKED | Unknown whether USB-C VBUS and the external 5 V pin are directly connected, diode-ORed, switched, or otherwise isolated. | No trustworthy revision-matched schematic or circuit inspection | High confidence that evidence is missing | Inspect/trace the actual module and test onboard-only, USB-only, and simultaneous-source behavior. | PCB layout + BOM freeze + Fabrication | -| Backfeed protection | TBD / BLOCKED | Final need and implementation for Schottky OR-ing, ideal-diode/load-switch isolation, USB-VBUS isolation, or a service-power selector is unresolved. | Depends on actual module topology and measured source behavior | High confidence that decision is blocked | Prove that USB cannot backfeed the buck/24 V system, onboard 5 V cannot unexpectedly source a USB host, and supplies cannot contend. | PCB layout + BOM freeze + Fabrication | +| Backfeed protection | TBD / BLOCKED | Reverse-current blocking or explicit source selection is required unless inspection and testing prove it unnecessary. Final implementation may use Schottky OR-ing, an ideal-diode/load-switch arrangement, USB-VBUS isolation, or a service-power selector; no option is selected. | Depends on actual module topology and measured source behavior | High confidence that decision is blocked | Prove that USB cannot backfeed the buck/24 V system, onboard 5 V cannot unexpectedly source a USB host, and supplies cannot contend. | PCB layout + BOM freeze + Fabrication | | Buck converter | TBD / BLOCKED | No MPN or final rating selected. Must support ESP32-S3 peaks/Wi-Fi bursts, boot transients, shared 74AHCT125 and fan-interface loads, other actual 5 V loads, and engineering margin. | Load inventory and installed thermal environment incomplete | High confidence that selection is blocked | Complete load inventory; evaluate voltage/transient rating, output current, efficiency, dissipation, reverse current, startup, and installed-temperature derating. | PCB layout + BOM freeze + Fabrication | +| Buck converter capacity target | ASSUMPTION / PROVISIONAL | Use at least 1.5 A continuous capability as an initial converter target. This is not a selected MPN or BOM-final rating. | Preliminary ESP32-S3 peak/burst allowance plus light interface-load margin | Medium | Complete the 5 V load inventory and converter loss/thermal derating at the maximum installed chamber/PCB temperature; increase the rating if required. | PCB layout + BOM freeze + Fabrication | | Power-management firmware assumptions | TBD / BLOCKED | No firmware behavior may assume a source topology or power-good behavior that has not been established in hardware. | Power architecture unresolved | High | Close power-state truth table and any available power-good/reset behavior. | Firmware constants | ## 4. Heater path and independent interruption @@ -89,7 +90,9 @@ temperatures. |---|---|---|---|---|---|---| | Q1 candidate | STRONG CANDIDATE | Texas Instruments CSD18540Q5B; 60 V logic-level N-MOSFET; maximum `RDS(on)` approximately 3.3 mΩ at 4.5 V. Not BOM-final. | Manufacturer data and Phase-1 component review | High for published characteristics | Reconfirm ordering code, lifecycle, package, pin/multipad mapping, and production availability. | PCB layout + BOM freeze + Fabrication | | Estimated Q1 conduction loss | ASSUMPTION / PROVISIONAL | About 0.205 W at 7.89 A and 0.229 W at 8.33 A using 3.3 mΩ: `P = I²R`. These are max-`RDS(on)`-basis conduction estimates only, not total hot operating loss. | Candidate data and measured/design currents | Medium | Include hot `RDS(on)`, switching loss, duty/frequency, gate waveform, copper spreading, and measured junction/board temperature. | PCB layout + BOM freeze + Firmware constants + Fabrication | -| Gate-drive concept | ASSUMPTION / PROVISIONAL | 5 V 74AHCT125, provisional 47 Ω gate resistor, and hardware gate pull-down with default-OFF intent. | Current Rev A.4.1 schematic concept | Medium | Verify power sequencing/default-OFF behavior, buffer enable strategy, partial-power paths, gate waveform, switching loss, and suitability at the chosen PWM frequency. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Rev A.4.1 gate buffer | CONFIRMED FACT | Rev A.4.1 uses an SN74AHCT125 for gate buffering, and the used output-enable inputs are tied low. This records the present schematic, not approval of its power-transition behavior. | Current Rev A.4.1 schematic | High | Reinspect after the required schematic correction and verify the implemented channel mapping. | PCB layout + Fabrication | +| Gate network concept | ASSUMPTION / PROVISIONAL | Provisional 47 Ω gate resistor and a direct Q1 gate pull-down. The direct pull-down must be retained independently of MCU and buffer state. | Current Rev A.4.1 schematic concept and Phase-1 default-OFF requirement | Medium | Select the pull-down value and gate resistance from leakage, turn-off, waveform, PWM, and switching-loss validation. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Required gate-drive correction | DESIGN DECISION | Heater gate drive must be hardware-default-disabled through power-up, power-down, reset, and brownout. Power the gate driver only from the 24 V-derived `+5V_SYS/GATE` domain so USB-only MCU power cannot drive Q1. Use a driver with documented partial-power-down behavior or equivalent isolation. Add test points for gate-driver power, OE, and Q1 gate. No replacement driver is BOM-final. | Phase-1 power/backfeed and default-OFF review | High | Revise the schematic; select/qualify the driver or isolation; verify OE biasing, partial-power sequencing, and Q1 gate voltage through all 24 V/USB/reset transitions. | PCB layout + BOM freeze + Firmware constants + Fabrication | | Q1 footprint and thermal implementation | TBD / BLOCKED | Exact verified KiCad footprint, thermal-pad implementation, and copper spreading are not frozen. | Footprint/PCB validation not completed | High confidence that implementation is incomplete | Verify package drawing and pad mapping; complete thermal/current layout and measurement plan. | PCB layout + Fabrication | ## 6. F2 fuse and holder @@ -147,6 +150,28 @@ identify a valid production cutoff temperature or mounting location. | High-current placement priority | DESIGN DECISION | Place and review `+24V_PROT -> F2 -> TF1 -> TS1 -> J2 -> heater -> Q1 -> GND` before convenience circuitry. Keep Q1, J2, F2, and the heater-current path compact without weakening conductor geometry for appearance. | Rev A.4.1 topology and Phase-1 implementation priority | High | Complete placement, current-loop, service-clearance, and thermal review. | PCB layout + Fabrication | | PCB validation | TBD / BLOCKED | Current-density bottlenecks, Q1 thermal spreading, fuse-holder and J2 pad heating, high-current return geometry, ADC noise, antenna keepout, DRC, fabricated-board temperature rise, and full-path voltage drop are unvalidated. | No Rev A PCB exists yet | High confidence that validation is pending | Create the board, review design evidence, fabricate only after blockers close, then thermally/electrically test production-intent hardware. | PCB layout + BOM freeze + Fabrication | +## Current fabrication blockers + +Fabrication remains blocked until all of the following are closed or deliberately +bounded by reviewed production-intent provisions: + +- ESP32 castellation dimensions and exact body/pad registration +- physical pin numbering and Pin 1 verification +- underside component envelope and maximum height +- PCB window and support-rail geometry +- antenna location and keepout +- USB connector, plug, cable-head, and service-access envelope +- physical fit of the optional locating header +- external 5 V / USB-C VBUS topology +- USB/onboard mixed-source and backfeed testing +- hardware-default-OFF gate-driver schematic correction +- complete regulator load inventory and installed-temperature thermal analysis +- Q1 multipad/footprint and F2 holder-footprint verification +- TF1/TS1 part, mounting, and thermal-coupling implementation +- J1, F1, and MOD1 part and footprint selections +- PCB envelope, mounting-hole coordinates, connector-facing edges, and USB datum +- final 1:1 production-footprint fit check with the actual module + ## Register maintenance rules - Preserve the exact status classes defined in this document. From 6b5519ee568501302bd6832a94a38d1d24125770 Mon Sep 17 00:00:00 2001 From: Daniel Brown Date: Fri, 4 Sep 2026 07:10:05 -0400 Subject: [PATCH 03/20] docs: update ESP32 physical hardware facts --- docs/PHASE1_HARDWARE_REGISTER.md | 42 +++++++++++++++++++------------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index a9a61c3..75d7f9a 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -1,6 +1,6 @@ # Phase 1 hardware source-of-truth register -Last updated: 2026-09-03 +Last updated: 2026-09-04 This is the living engineering register for JumpJet Rev A Phase-1 hardware implementation. It records what is known, how it is known, what remains @@ -47,21 +47,29 @@ temperatures. |---|---|---|---|---|---|---| | Module PCB body | MEASURED | 23.67 mm long × 17.91 mm wide. | Physical measurement of the actual module | High | Confirm against the 1:1 production-footprint plot before freeze. | Fabrication | | Overall length including USB-C | MEASURED | 25.07 mm. | Physical measurement of the actual module | High | Confirm connector projection and carrier-board relationship on the 1:1 plot. | PCB layout + Fabrication | -| USB-C overhang | MEASURED | Approximately 1.40 mm beyond the module PCB edge. This is a datum, not a complete connector keepout. | Physical measurement of the actual module | High for overhang only | Measure shell width, height, position, mating plug, cable-head envelope, and enclosure access. | PCB layout + Fabrication | +| USB-C overhang | MEASURED | Approximately 1.40 mm beyond the module PCB edge. This is a datum, not a complete connector keepout. | Direct caliper measurement of the actual module | High for overhang only | Establish the carrier-board edge relationship, mating-plug envelope, cable-head clearance, and enclosure access. | PCB layout + Fabrication | +| USB-C shell envelope | MEASURED | Shell is 8.84 mm wide × 3.12 mm high/thick and occupies 7.48 mm over the module PCB. These shell measurements do not define the plug or enclosure keepout. | Direct caliper measurement of the actual module | High for the measured shell | Measure the mating plug and cable head; define carrier-edge and enclosure-access clearances. | PCB layout + Fabrication | | Pad count | CONFIRMED FACT | Nine castellations per side; 18 total. | Physical inspection of the actual module | High | Verify every pad number and label against the actual module silkscreen. | PCB layout + Fabrication | -| Nominal pin pitch | ASSUMPTION / PROVISIONAL | 2.54 mm; supported by an approximately 20.0 mm measured span across eight intervals, versus 20.32 mm nominal. | Physical measurement and derived nominal geometry | High | 1:1 physical placement and direct center-to-center verification. | PCB layout + Fabrication | +| Adjacent castellation pitch | MEASURED | 2.55 mm center-to-center. This supports, but does not replace, the provisional 2.54 mm nominal design pitch. | Direct caliper measurement of adjacent castellations on the actual module | High for the measured specimen | Verify all pad centers on the 1:1 production-footprint plot. | PCB layout + Fabrication | +| Nominal pin pitch | ASSUMPTION / PROVISIONAL | Use 2.54 mm for footprint design. Supported by the 2.55 mm adjacent measurement, ordinary 2.54 mm header fit, and a previously measured approximately 20.0 mm first-to-last center span versus the nominal 20.32 mm eight-pitch span. | Physical measurements, physical header fit, and derived nominal geometry | High | Verify all 18 pads by true-scale physical placement before freeze. | PCB layout + Fabrication | | Nominal row spacing | ASSUMPTION / PROVISIONAL | 15.24 mm; supported by an approximately 15.2 mm physical measurement. | Physical measurement and derived nominal geometry | High | 1:1 physical placement and direct row-center verification. | PCB layout + Fabrication | | Side edge to row center | ASSUMPTION / PROVISIONAL | Approximately 1.335 mm, derived as `(17.91 - 15.24) / 2`. | Derived from measured body width and provisional nominal row spacing | Medium | Measure actual castellation centerline relative to both module edges. | PCB layout + Fabrication | -| End to first/last pin center | ASSUMPTION / PROVISIONAL | Approximately 1.675 mm if symmetric, derived as `(23.67 - 20.32) / 2`. | Derived from measured body length and provisional nominal pitch | Medium | Measure the actual longitudinal registration; do not assume symmetry. | PCB layout + Fabrication | -| Castellation receiving lands | TBD / BLOCKED | Pad width and depth are intentionally undefined. | No authoritative physical dimensions or trusted revision-matched drawing available | High confidence that evidence is missing | Measure castellation width, inward depth, plating/mask geometry, and body registration. | PCB layout + Fabrication | +| Castellation width | MEASURED | 1.96 mm along the module board edge. This is the module castellation width, not a frozen carrier receiving-land width. | Direct caliper measurement of the actual module | High for the measured specimen | Review solder/process margin, inward land depth, mask expansion, and paste treatment before defining the carrier land. | PCB layout + Fabrication | +| Non-USB edge to first castellation | MEASURED | 1.00 mm from the non-USB PCB edge to the near edge of the first castellation. This is explicitly not a centerline offset. | Direct caliper measurement of the actual module | High for the measured datum | Establish the footprint datum and directly verify longitudinal pad-center registration at both ends. | PCB layout + Fabrication | +| Castellation receiving lands | ASSUMPTION / PROVISIONAL | Use 18 SMD receiving lands at provisional 2.54 mm pitch and 15.24 mm row spacing. Derive land width from the measured 1.96 mm castellation width with appropriate solder/process margin; exact width, inward depth, mask expansion, paste geometry, and longitudinal registration remain unfrozen. | Physical module measurements and Phase-1 direct-solder architecture | Medium | Complete footprint/process review and pass a 1:1 physical fit check. | PCB layout + Fabrication | +| Ordinary header fit | MEASURED | Ordinary 2.54 mm header pins physically fit the castellation holes. This supports pitch/alignment evaluation but does not change production attachment to through-hole mounting. | Physical fit check on the actual module | High for fit observation | Measure the actual square posts and verify removable alignment-hole clearance and PCBWay drill tolerance. | PCB layout + Fabrication | | Production mounting | DESIGN DECISION | Direct solder of the castellated module to carrier-PCB SMD lands. The current drilled through-hole footprint is not the production architecture unless later physical verification explicitly reverses this decision. | Phase-1 mounting decision; inspection of Rev A.4.1 project footprint | High | Complete and physically verify the project-local castellated footprint. | PCB layout + Fabrication | -| Central underside PCB window | DESIGN DECISION | Provide a carrier-PCB window for underside component clearance, inspection/cleaning, avoiding a header/standoff dependency, and reducing trapped heat. It is not a safety airflow feature. | Phase-1 mechanical decision | High | Measure underside X/Y envelope, maximum height, solder/metal features, support regions, and required FR-4 rail widths. | PCB layout + Fabrication | -| Underside window geometry | TBD / BLOCKED | No length, width, corner, or support-rail dimensions are frozen. | Required physical underside measurements are unavailable | High confidence that evidence is missing | Complete underside measurements and structural/routing review. | PCB layout + Fabrication | -| Optional temporary locating holes | DESIGN DECISION | Two holes total, one at each end of one castellated row, for a removable 2.54 mm header assembly aid. They are not electrical pins or production attachment. | Phase-1 assembly decision | High | Measure the actual header posts; select NPTH/PTH; establish hole diameter and coordinates; check rails, USB, antenna, window, and removal clearance. | PCB layout + Fabrication | -| Locating-hole geometry | ASSUMPTION / PROVISIONAL | Candidate holes are Ø1.10 mm NPTH with no copper at X = −7.620 mm, Y = ±12.700 mm. Provisional footprint datum: origin at the module PCB geometric center; X runs across module width, Y runs along module length, and USB-C is at negative Y. The geometry is not final. | Phase-1 mounting/assembly-aid review using nominal 2.54 mm row extension and a nominal 0.635 mm square header-post concept | Medium | Measure the actual header; verify finished-hole and positional tolerances; physically fit-test insertion/removal; check interference with lands, support rails, window, antenna, and USB. | PCB layout + Fabrication | -| Antenna keepout | TBD / BLOCKED | Location, dimensions, and applicable copper layers are undefined. | Actual module antenna has not been physically identified and measured | High confidence that evidence is missing | Identify antenna on the actual revision; measure prohibited region; define copper/trace/component restrictions. | PCB layout + Fabrication | -| USB-C mechanical keepout | TBD / BLOCKED | Full shell, plug, cable-head, carrier-edge, and enclosure access envelope is undefined. | Only overall length and approximate overhang have been measured | High confidence that evidence is missing | Complete physical connector and service-access measurements. | PCB layout + Fabrication | -| Mandatory 1:1 verification | DESIGN DECISION | The actual module must be placed on a true-scale plot before footprint freeze. All 18 castellations, body, Pin 1, locating holes, USB projection, antenna direction, and underside window must pass without forced alignment. | Phase-1 acceptance requirement | High | Perform and document the physical fit check using the final proposed footprint. | Fabrication | +| Mounted component side | CONFIRMED FACT | All mounted components are on the top side. The underside is physically flat apart from PCB/contact metallization. | Direct top/bottom inspection of the actual module | High | Preserve the observed orientation in the footprint and 1:1 plot. | PCB layout + Fabrication | +| Physical Pin 1 | CONFIRMED FACT | Pin 1 has been physically identified from the module photograph. | Direct photographic inspection of the actual module | High | Document the footprint datum/orientation and verify every remaining pad number and label. | PCB layout + Fabrication | +| Underside exposed contacts/test pads | CONFIRMED FACT | Exposed underside contacts/test pads are present despite there being no mounted underside components. The carrier must not place vias, exposed pads, or other exposed conductive features where unintended contact is possible; even soldermask-covered copper requires spacing/stackup review. | Direct underside inspection of the actual module | High for presence; envelope not mapped | Measure and map the exact contact locations/envelope before fabrication and verify the isolation region in the footprint/PCB. | Footprint freeze + PCB layout + Fabrication | +| Central underside PCB window | ASSUMPTION / PROVISIONAL | **Current decision state: REEVALUATION REQUIRED.** Underside component clearance no longer justifies a window. A solid carrier region with controlled isolation and soldermask beneath the module is now the leading architecture to evaluate, with no exposed carrier copper or vias where underside contacts could touch. Retain a window only if cleaning, inspection, thermal, assembly, or mechanical review supplies an independent justification. | Direct inspection confirms a flat underside with no mounted components, but with exposed electrical/test contacts | Medium | Compare solid-carrier and independently justified window options; map underside contacts; review isolation, cleaning, inspection, thermal, assembly, and structural needs. | Footprint freeze + PCB layout + Fabrication | +| Underside window geometry | TBD / BLOCKED | No window geometry is frozen because the need for a window has been reopened. If retained for an independently validated reason, its length, width, corners, and support rails must be defined. | Central-window reevaluation | High confidence that no geometry is approved | Complete the architecture review before defining any opening. | PCB layout + Fabrication | +| Optional temporary locating holes | ASSUMPTION / PROVISIONAL | Assembly concept only: two holes total at the ends of one castellated row may accept removable ordinary 2.54 mm male-header pins for alignment/tack soldering. The header is removed afterward; production attachment remains the castellated solder joints. | Phase-1 assembly concept and physical header-fit observation | Medium | Verify post dimensions, insertion/removal clearance, PCBWay drill capability/tolerance, land support, antenna/USB clearance, and that the module is not forced into alignment. | PCB layout + Fabrication | +| Locating-hole geometry | ASSUMPTION / PROVISIONAL | Candidate holes are Ø1.10 mm NPTH. Previously proposed X = −7.620 mm, Y = ±12.700 mm coordinates are not usable or frozen until the footprint origin and orientation datum are explicitly documented and physically checked. | Phase-1 assembly-aid review using a provisional nominal square-header concept | Low-medium | Document the datum/orientation; measure the actual header; verify finished-hole and positional tolerances; physically fit-test insertion/removal; check interference with receiving lands, antenna, and USB. | PCB layout + Fabrication | +| Likely onboard antenna | ASSUMPTION / PROVISIONAL | The small red/white ceramic component at the non-USB end is treated as the likely onboard 2.4 GHz antenna unless inspection or revision-matched evidence disproves it. Do not assume WROOM-class RF performance. | Direct top-side inspection and component appearance | Medium | Confirm function/location and establish the antenna datum and installed orientation. | PCB layout + Fabrication | +| Antenna keepout | ASSUMPTION / PROVISIONAL | Prefer the antenna at a carrier-board edge. Reserve an RF keepout around and beneath it from copper, planes, vias, traces, heater-current copper, switch-node copper, fuse hardware, and large grounded metal; preserve enclosure clearance where practical. Exact geometry and affected layers remain TBD. | Likely antenna location plus Phase-1 RF layout direction | Medium | Define the exact keepout and validate Wi-Fi RSSI/range after final PCB placement and again after enclosure installation. | PCB layout + Fabrication | +| USB-C mechanical keepout | TBD / BLOCKED | The shell is measured, but the mating-plug envelope, cable-head clearance, enclosure opening, and carrier-board edge relationship remain undefined. Do not derive the complete keepout from shell dimensions alone. | Direct shell measurements; service-access geometry incomplete | High confidence that evidence remains incomplete | Complete plug, cable-head, carrier-edge, and enclosure-access measurements. | PCB layout + Fabrication | +| Mandatory 1:1 verification | DESIGN DECISION | The actual module must be placed on a true-scale plot before footprint freeze. All 18 castellations, body, Pin 1/orientation, optional locating holes, USB projection, antenna direction/keepout, and underside isolation region must pass without forced alignment. | Phase-1 acceptance requirement | High | Perform and document the physical fit check using the final proposed footprint. | Fabrication | ## 3. ESP32 power architecture @@ -155,11 +163,11 @@ identify a valid production cutoff temperature or mounting location. Fabrication remains blocked until all of the following are closed or deliberately bounded by reviewed production-intent provisions: -- ESP32 castellation dimensions and exact body/pad registration -- physical pin numbering and Pin 1 verification -- underside component envelope and maximum height -- PCB window and support-rail geometry -- antenna location and keepout +- ESP32 carrier receiving-land geometry and exact body/pad registration +- complete pin numbering/label verification beyond the physically identified Pin 1 +- underside exposed-contact mapping and carrier isolation review +- central carrier-region/window reevaluation; window/support-rail geometry only if a window remains independently justified +- antenna identity, exact keepout, and installed RSSI/range validation - USB connector, plug, cable-head, and service-access envelope - physical fit of the optional locating header - external 5 V / USB-C VBUS topology From 9c416e64f6937bc213694bdb396241ed9c4cf5c1 Mon Sep 17 00:00:00 2001 From: Daniel Brown <30573097+danielbrownjr@users.noreply.github.com> Date: Fri, 4 Sep 2026 04:32:59 -0700 Subject: [PATCH 04/20] chore: add authoritative Rev A KiCad source --- .gitignore | 13 + .../kicad/JumpJet_RevA/BOM_PRELIMINARY.csv | 20 + .../ESP32-S3_SuperMini_2x9.kicad_mod | 51 + .../JumpJet_RevA/JumpJet_Controller.kicad_sch | 1518 +++++++++ .../JumpJet_Controller_RevA.kicad_sym | 134 + .../JumpJet_Controller_RevA4.kicad_pro | 1 + .../JumpJet_Controller_RevA4.kicad_sch | 75 + .../JumpJet_Expansion_Test.kicad_sch | 1995 ++++++++++++ .../JumpJet_Power_Outputs.kicad_sch | 2783 +++++++++++++++++ .../JumpJet_Temperature_Sensing.kicad_sch | 1861 +++++++++++ hardware/kicad/JumpJet_RevA/README.md | 36 + hardware/kicad/JumpJet_RevA/fp-lib-table | 3 + .../references/REV_A4_1_ARCHIVE_README.md | 66 + hardware/kicad/JumpJet_RevA/sym-lib-table | 3 + 14 files changed, 8559 insertions(+) create mode 100644 hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv create mode 100644 hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9.kicad_mod create mode 100644 hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch create mode 100644 hardware/kicad/JumpJet_RevA/JumpJet_Controller_RevA.kicad_sym create mode 100644 hardware/kicad/JumpJet_RevA/JumpJet_Controller_RevA4.kicad_pro create mode 100644 hardware/kicad/JumpJet_RevA/JumpJet_Controller_RevA4.kicad_sch create mode 100644 hardware/kicad/JumpJet_RevA/JumpJet_Expansion_Test.kicad_sch create mode 100644 hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch create mode 100644 hardware/kicad/JumpJet_RevA/JumpJet_Temperature_Sensing.kicad_sch create mode 100644 hardware/kicad/JumpJet_RevA/README.md create mode 100644 hardware/kicad/JumpJet_RevA/fp-lib-table create mode 100644 hardware/kicad/JumpJet_RevA/references/REV_A4_1_ARCHIVE_README.md create mode 100644 hardware/kicad/JumpJet_RevA/sym-lib-table diff --git a/.gitignore b/.gitignore index 45f6b0a..5199072 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,16 @@ sdkconfig sdkconfig.old dependencies.lock main/dev_config.h + +# KiCad transient/editor state and generated fabrication output. Keep native +# project, schematic, PCB, symbol, footprint, and library-table sources tracked. +*.lck +*-backups/ +*.bak +*.tmp +_autosave-* +*.gbr +*.gbrjob +*.drl +*.pos +*.rpt diff --git a/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv new file mode 100644 index 0000000..b216459 --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv @@ -0,0 +1,20 @@ +Reference,Qty,Function,Value / Requirement,Population,Status +J1,1,24 V input,">=20 A keyed terminal, 14 AWG capable",BASE,Footprint TBD +F1,1,Main fuse,15 A provisional,BASE,Verify coordination +D1,1,Rail TVS,SMBJ30A provisional,BASE,Verify clamp vs MOSFET/PSU +MOD1,1,Logic power,"24 V to 5 V, input transient rating >=60 V",BASE,Exact module TBD +F2,1,Heater branch fuse,TBD after cold-start measurement,BASE,Open +TF1,1,One-shot thermal fuse,"75 C, 15 A",BASE,BOM supplied +TS1,1,Resettable thermal switch,"NC, 75 C, 16 A",BASE,BOM supplied +J2,1,Heater output terminal,"Phoenix Contact MKDS 1,5/2 (1715022), 5.00 mm pitch, 17.5 A nominal",BASE,"Selected for 8.3 A heater; external splice/lead extension documented separately" +J3,1,Integrated blower,"24 V, ~0.36 A; JST-XH 2-pin",BASE,"Footprint locked to JST_XH_B2B-XH-A; mating housing XHP-2; polarity to verify before harness build" +Q1-Q2,2,Low-side switching,60 V logic-level N-MOSFET,BASE,Exact part/thermal design TBD +Q3/F4/J4/D3,1 set,AUX1 PWM output,24 V optional,DNP,User expansion +U1,1,Gate buffer,74AHCT125,BASE,Review drive/current +U2,1,Controller module,"ESP32-S3FH4R2 SuperMini, 2x9 edge pads",BASE,Pin order and 15.24 mm row spacing confirmed +J6-J8,3,Thermistors,"10 k NTC, 1 m lead",BASE,Beta/coefficients TBD +J9 + divider,1,Fourth thermistor,10 k NTC,DNP,Expansion +J10,1,Qwiic,JST-SH 1.0 mm 4-pin,BASE,Supported expansion +F5,1,Qwiic protection,250 mA resettable fuse,BASE,Provisional +JP1/JP2 + R18/R19,2,I2C pullups,4.7 k selectable,DNP/open,Populate only if required +J11,1,User expansion,8-pin 2.54 mm,OPTIONAL,Pinout provisional diff --git a/hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9.kicad_mod b/hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9.kicad_mod new file mode 100644 index 0000000..0c62b7c --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9.kicad_mod @@ -0,0 +1,51 @@ +(footprint "ESP32-S3_SuperMini_2x9" + (version 20240108) + (generator "jumpjet_reva_generator") + (layer "F.Cu") + (descr "LEGACY REV A.4.1 THT footprint retained for schematic resolution only; obsolete for production mounting") + (tags "LEGACY OBSOLETE PRODUCTION ESP32 S3 SuperMini 2x9 2.54mm THT") + (attr through_hole) + (fp_rect (start -8.965 -11.85) (end 8.965 11.85) (stroke (width 0.25) (type default)) (fill none) (layer "F.Fab")) + (fp_rect (start -9.15 -12.05) (end 9.15 12.05) (stroke (width 0.3) (type default)) (fill none) (layer "F.SilkS")) + (fp_rect (start -4.7 -13.15) (end 4.7 -9.45) (stroke (width 0.25) (type default)) (fill none) (layer "F.Fab")) + (fp_rect (start -9.4 -13.4) (end 9.4 12.3) (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) + (fp_text reference "REF**" (at 0 13.1 0) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) + (fp_text value "ESP32-S3_SuperMini_2x9" (at 0 14.6 0) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) + (fp_text user "USB-C" (at 0 -11.2 0) (layer "F.SilkS") (effects (font (size 0.8 0.8) (thickness 0.12)))) + (pad "1" thru_hole rect (at -7.62 -10.16) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "TX" (at -5.9 -10.16) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "10" thru_hole circle (at 7.62 -10.16) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "5V" (at 5.9 -10.16) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "2" thru_hole circle (at -7.62 -7.62) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "RX" (at -5.9 -7.62) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "11" thru_hole circle (at 7.62 -7.62) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "GND" (at 5.9 -7.62) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "3" thru_hole circle (at -7.62 -5.08) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "1" (at -5.9 -5.08) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "12" thru_hole circle (at 7.62 -5.08) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "3V3" (at 5.9 -5.08) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "4" thru_hole circle (at -7.62 -2.54) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "2" (at -5.9 -2.54) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "13" thru_hole circle (at 7.62 -2.54) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "13" (at 5.9 -2.54) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "5" thru_hole circle (at -7.62 0.00) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "3" (at -5.9 0.00) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "14" thru_hole circle (at 7.62 0.00) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "12" (at 5.9 0.00) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "6" thru_hole circle (at -7.62 2.54) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "4" (at -5.9 2.54) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "15" thru_hole circle (at 7.62 2.54) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "11" (at 5.9 2.54) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "7" thru_hole circle (at -7.62 5.08) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "5" (at -5.9 5.08) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "16" thru_hole circle (at 7.62 5.08) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "10" (at 5.9 5.08) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "8" thru_hole circle (at -7.62 7.62) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "6" (at -5.9 7.62) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "17" thru_hole circle (at 7.62 7.62) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "9" (at 5.9 7.62) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "9" thru_hole circle (at -7.62 10.16) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "7" (at -5.9 10.16) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) + (pad "18" thru_hole circle (at 7.62 10.16) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")) + (fp_text user "8" (at 5.9 10.16) (layer "F.SilkS") (effects (font (size 0.65 0.65) (thickness 0.1)))) +) diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch new file mode 100644 index 0000000..ed32501 --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch @@ -0,0 +1,1518 @@ +(kicad_sch (version 20260306) (generator jumpjet-reva4-multisheet) + + (uuid 33936e9e-9abe-42e0-a16c-c200686ec649) + + (paper "A4" portrait) + + (title_block + (title "JumpJet Controller — ESP32-S3 controller, logic power, and service header") + (date "2026-08-25") + (rev "A.4.1 - ERC FIX") + (company "JumpJet") + (comment 1 "24 V PTC chamber-heater controller") + (comment 2 "ESP32-S3 SuperMini 2x9 carrier; measured 23.7 x 17.93 mm, 25.0 mm incl. USB-C") + (comment 3 "TBD values require bench verification before assembly") + (comment 4 "Heater thermal cutoffs are independent of firmware") + ) + + (lib_symbols + (symbol "74xx:74AHCT125" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (at 0 1.27 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "74AHCT125" (at 0 -1.27 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Datasheet" "https://www.ti.com/lit/ds/symlink/sn74ahct125.pdf" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Description" "Quadruple Bus Buffer Gates With 3-State Outputs" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "ki_locked" "" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "ki_keywords" "buffer 3State" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "ki_fp_filters" "DIP*W7.62mm* SO14* SSOP?14* TSSOP?14* SOIC*3.9x8.7mm*P1.27mm*" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (symbol "74AHCT125_1_0" + (polyline + (pts + (xy -3.81 3.81) + (xy -3.81 -3.81) + (xy 3.81 0) + (xy -3.81 3.81) + ) + (stroke (width 0.254) (type default)) + (fill (type background)) + ) + (pin input inverted (at 0 -6.35 90) (length 4.445) + (name "" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -7.62 0 0) (length 3.81) + (name "" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin tri_state line (at 7.62 0 180) (length 3.81) + (name "" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + ) + (symbol "74AHCT125_2_0" + (polyline + (pts + (xy -3.81 3.81) + (xy -3.81 -3.81) + (xy 3.81 0) + (xy -3.81 3.81) + ) + (stroke (width 0.254) (type default)) + (fill (type background)) + ) + (pin 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+ ) + (property "ki_fp_filters" "DIP*W7.62mm* SO14* SSOP?14* TSSOP?14* SOIC*3.9x8.7mm*P1.27mm*" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (symbol "74AHCT125_1_0" + (polyline + (pts + (xy -3.81 3.81) + (xy -3.81 -3.81) + (xy 3.81 0) + (xy -3.81 3.81) + ) + (stroke (width 0.254) (type default)) + (fill (type background)) + ) + (pin input inverted (at 0 -6.35 90) (length 4.445) + (name "" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -7.62 0 0) (length 3.81) + (name "" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin tri_state line (at 7.62 0 180) (length 3.81) + (name "" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + ) + (symbol "74AHCT125_2_0" + (polyline + (pts + (xy -3.81 3.81) + (xy -3.81 -3.81) + (xy 3.81 0) + (xy -3.81 3.81) + ) + (stroke (width 0.254) (type default)) + (fill (type background)) + ) + (pin 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b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch new file mode 100644 index 0000000..be18eb8 --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch @@ -0,0 +1,2783 @@ +(kicad_sch (version 20260306) (generator jumpjet-reva4-multisheet) + + (uuid 9ef88b6a-3563-4131-bc78-4b6116b7c1d4) + + (paper "A3") + + (title_block + (title "JumpJet Controller — Power, protection, heater, blower, and auxiliary outputs") + (date "2026-08-25") + (rev "A.4.1 - ERC FIX LOADABLE") + (company "JumpJet") + (comment 1 "24 V PTC chamber-heater controller") + (comment 2 "ESP32-S3 SuperMini 2x9 carrier; measured 23.7 x 17.93 mm, 25.0 mm incl. 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index 0000000..c9ca21b --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/README.md @@ -0,0 +1,36 @@ +# JumpJet Rev A KiCad source + +This directory contains the checked-in source from the authoritative Rev A.4.1 +schematic package, `JumpJet_Controller_RevA4_1_J3_JST_XH.zip`. + +Open `JumpJet_Controller_RevA4.kicad_pro`, then +`JumpJet_Controller_RevA4.kicad_sch`. The root schematic references four child +sheets in this directory. Project-local symbols and footprints resolve through +`sym-lib-table` and `fp-lib-table`. + +## Authority and limitations + +- Rev A.4.1 is the current authoritative **schematic** baseline. +- No `.kicad_pcb` exists in this source set. The first Rev A PCB remains active + Phase 1 implementation work, not a missing artifact to recover. +- This source is not fabrication-ready and does not authorize heater or fan + actuation. +- `BOM_PRELIMINARY.csv` is archive context only. It contains placeholders and + does not override statuses in + [`docs/PHASE1_HARDWARE_REGISTER.md`](../../../docs/PHASE1_HARDWARE_REGISTER.md). +- Native KiCad ERC has not been run in this environment because `kicad-cli` is + unavailable. The archive provenance note records the same limitation. + +## Footprint status + +`JumpJet.pretty/ESP32-S3_SuperMini_2x9.kicad_mod` is the drilled legacy +footprint referenced by Rev A.4.1. It is retained so the current schematic +resolves, but it is obsolete for the selected production mounting method. + +## Source-package exclusions + +The archive's repair, warning-cleanup, presentation, polish, and connector +changelog text files were not imported because they are historical packaging +notes rather than project dependencies. Lock files, autosaves, backups, +fabrication outputs, and temporary exports are also intentionally excluded. +The archive README is retained under `references/` as provenance. diff --git a/hardware/kicad/JumpJet_RevA/fp-lib-table b/hardware/kicad/JumpJet_RevA/fp-lib-table new file mode 100644 index 0000000..7b2b49d --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/fp-lib-table @@ -0,0 +1,3 @@ +(fp_lib_table + (lib (name "JumpJet")(type "KiCad")(uri "${KIPRJMOD}/JumpJet.pretty")(options "")(descr "JumpJet project footprints")) +) diff --git a/hardware/kicad/JumpJet_RevA/references/REV_A4_1_ARCHIVE_README.md b/hardware/kicad/JumpJet_RevA/references/REV_A4_1_ARCHIVE_README.md new file mode 100644 index 0000000..200c8fc --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/references/REV_A4_1_ARCHIVE_README.md @@ -0,0 +1,66 @@ +# JumpJet Controller Rev A.4.1 - multisheet draft + +Open `JumpJet_Controller_RevA4.kicad_pro`, then open the schematic. + +The design is split into four functional sheets: + +1. Power, protection, and switched outputs +2. ESP32-S3 controller and service interface +3. Thermistor signal conditioning +4. Qwiic, expansion, and test points + +Inter-sheet signals use global labels. + +## Programmatic schematic repair - 2026-08-25 + +This copy was repaired from the supplied Rev A.4.1 multisheet draft without changing the intended product architecture or treating provisional choices as finalized. + +Structural fixes include: + +- Corrected stock-symbol rotations where the generated symbol orientation did not match the wire geometry. +- Corrected generated anchor offsets for the 24 V to 5 V module, service header, Qwiic connector, and expansion header. +- Re-terminated wires and labels at actual KiCad electrical pin endpoints rather than symbol body edges. +- Repaired the existing 74AHCT125 buffer topology so each used channel has its intended PWM input, driven output, and active-low OE tied low; the unused channel input/OE remain low and its output remains explicitly NC. +- Restored the intended heater, blower, optional AUX, thermistor, Qwiic, service-header, and test-point connectivity. +- Removed redundant ADC alias labels that could create ambiguous net naming. +- Preserved the custom ESP32-S3 SuperMini 2x9 symbol/footprint numbering and the existing provisional GPIO assignment. + +`REPAIR_AUDIT.txt` records the programmatic structural/connectivity checks performed on this repaired copy. + +## Still provisional / must be engineered before fabrication + +This is **not fabrication-approved**. In particular, the following remain open or require independent verification: + +- `MOD1` exact converter module, pinout, transient behavior, and `BUCK_EN` policy +- Main/heater/Qwiic fuse selection and protection coordination +- TVS selection and clamp behavior versus the PSU and downstream devices +- MOSFET exact part numbers, gate-drive suitability, switching loss, SOA, thermal design, and derating +- Blower polarity, flyback strategy/component ratings, and airflow adequacy (nominal current now confirmed at ~0.36 A @ 24 V) +- PTC heater cold-start current and operating current +- Connector footprints, contact current ratings, wire gauge, PCB copper/trace/plane sizing, and clearances +- Thermistor beta/Steinhart-Hart coefficients, ADC range, fault thresholds, and calibration +- Thermal fuse / resettable thermal switch physical placement and system-level cutoff behavior +- ESP32 GPIO assignments, strapping constraints, and expansion pinout as final design choices + +The repaired files passed a custom structural/connectivity audit, but `kicad-cli` is not available in the repair environment. Open the project in KiCad and run ERC before treating the schematic as an engineering baseline. + + +## Presentation-only cleanup pass + +This copy was generated from the electrically repaired Rev A.4.1 baseline. The pass changes only visible schematic presentation (Reference/Value property positions, label justification, and annotation placement). It intentionally does not move electrical anchors, symbol bodies, wire endpoints, junctions, no-connect markers, or net labels. The same structural/connectivity audit must pass after this pass. + + +## Depth-safe final schematic polish + +This copy supersedes the earlier POLISHED archive. The earlier geometry pass accidentally relied on whitespace indentation to identify top-level KiCad objects; several repaired wires/labels had noncanonical indentation and were therefore left behind visually. This pass starts again from the connectivity-validated PRESENTATION baseline and identifies top-level objects from s-expression parenthesis depth, then applies the same rigid functional-block translations to every relevant object regardless of whitespace. No electrical design intent is changed. + +### Final cleanup correction + +The first POLISHED archive should be considered superseded. A whitespace-sensitive geometry pass had left several valid top-level wires/labels at their pre-polish coordinates because older repair scripts had given those objects noncanonical indentation. The corrected polish identifies top-level objects by KiCad s-expression depth, normalizes their indentation for auditing, and removes two stale local ADC alias labels (`OUT_ADC`, `CASE_ADC`) that conflicted with the canonical `TEMP_OUT_ADC` and `TEMP_CASE_ADC` nets. The complete structural/connectivity audit passes after these corrections. + +## J2 heater terminal selection +J2 is assigned to Phoenix Contact MKDS 1,5/2 (1715022), 5.00 mm pitch, 17.5 A nominal, using KiCad footprint `TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal`. The nominal heater load is ~8.3 A at 24 V. The heater's short fabric/nylon-jacketed leads may be extended externally with a suitably rated Wago-style splice; provide strain relief and use conductor/ferrule sizes allowed by the terminal and splice manufacturers. + + +## J3 blower connector selection +J3 is assigned to the standard 2-pin JST-XH board header footprint `Connector_JST:JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical`. The confirmed blower load is approximately 0.36 A at 24 V, comfortably within the JST-XH current class for this use. The intended mating housing is JST XHP-2 with suitable crimp contacts. Electrical connectivity and pin numbering are unchanged; verify final blower polarity before building the harness. diff --git a/hardware/kicad/JumpJet_RevA/sym-lib-table b/hardware/kicad/JumpJet_RevA/sym-lib-table new file mode 100644 index 0000000..fa0d03d --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name "JumpJet_Controller_RevA")(type "KiCad")(uri "${KIPRJMOD}/JumpJet_Controller_RevA.kicad_sym")(options "")(descr "JumpJet project symbols")) +) From 8dd66414e0215bd648524ff63e76c940b99796be Mon Sep 17 00:00:00 2001 From: Daniel Brown <30573097+danielbrownjr@users.noreply.github.com> Date: Fri, 4 Sep 2026 04:33:17 -0700 Subject: [PATCH 05/20] hardware: add provisional ESP32 castellated footprint --- README.md | 8 +-- TODO.md | 19 ++++--- docs/HARDWARE_BASELINE.md | 11 ++-- docs/PHASE1_HARDWARE_REGISTER.md | 53 ++++++++++++------ ...Mini_2x9_Castellated_PROVISIONAL.kicad_mod | 54 +++++++++++++++++++ hardware/kicad/JumpJet_RevA/README.md | 13 +++++ 6 files changed, 129 insertions(+), 29 deletions(-) create mode 100644 hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9_Castellated_PROVISIONAL.kicad_mod diff --git a/README.md b/README.md index a7f24ce..052d262 100644 --- a/README.md +++ b/README.md @@ -52,9 +52,11 @@ sizing remains the rated 24 V / 200 W / 8.33 A case. That test did **not** validate the complete Jump Jet Q1/F2/PCB/connector/wiring path or installed operation. The Rev A.4.1 schematic is the current hardware -authority. The Rev A PCB has not yet been created; PCB implementation and -validation are the current Phase-1 hardware work, not an artifact-recovery -problem. Detailed status and blockers are tracked in the +authority, and its [KiCad project source](hardware/kicad/JumpJet_RevA/README.md) +is checked into this repository. The Rev A PCB has not yet been created; PCB +implementation and validation are the current Phase-1 hardware work. The +checked-in schematic is not fabrication-ready and does not authorize heater +actuation. Detailed status and blockers are tracked in the [Phase 1 hardware register](docs/PHASE1_HARDWARE_REGISTER.md). GPIO, ADC, thermistor, protection, and cooldown thresholds therefore remain TBD. The Sanyo Denki 9GA0424P3J001 is only a prototype fan candidate, not BOM-final. diff --git a/TODO.md b/TODO.md index 2f11839..68fadbd 100644 --- a/TODO.md +++ b/TODO.md @@ -9,6 +9,9 @@ implementation starts, and keep only the summary checkbox here. - [x] Review the Rev A.4.1 schematic package and record it as the current authoritative schematic baseline in the [Phase 1 hardware register](docs/PHASE1_HARDWARE_REGISTER.md) +- [x] Check the authoritative Rev A.4.1 KiCad project, hierarchical sheets, + project symbol/footprint libraries, and preliminary BOM into + `hardware/kicad/JumpJet_RevA/` - [ ] Create the first Rev A `.kicad_pcb` after the mechanical and electrical layout blockers close - [ ] Add the current BOM with manufacturer part numbers and acceptable substitutions @@ -16,9 +19,9 @@ implementation starts, and keep only the summary checkbox here. - [x] Record the measured ESP32-S3 Super Mini envelope and provisional nominal pin geometry - [ ] Verify the installed ESP32-S3 Super Mini flash size -- [ ] Complete the production castellated footprint after castellation dimensions, - exact registration, underside envelope/height, antenna keepout, USB access - envelope, Pin 1, and physical pin numbering are verified +- [ ] Complete the production castellated footprint after the provisional land + geometry and exact registration, underside-contact isolation map, antenna + keepout, USB access envelope, and physical pin numbering are verified - [ ] Confirm the complete GPIO/ADC assignment, including boot strapping and USB pins - [x] Record standalone CZ4060 rated and measured power/current at 24 V - [ ] Validate the full Jump Jet Q1/F2/PCB/connector/wiring path at the 200 W / 8.33 A design basis @@ -37,10 +40,14 @@ implementation starts, and keep only the summary checkbox here. - [ ] Define the board outline, mounting-hole coordinates, connector-facing edges, and USB mechanical datum -- [ ] Measure ESP32 castellation dimensions and exact body/pad registration -- [ ] Measure the ESP32 underside component envelope and maximum height +- [x] Measure ESP32 castellation width and the non-USB edge-to-first-castellation datum +- [ ] Verify exact ESP32 body/pad registration on a 1:1 production-footprint plot +- [x] Confirm the ESP32 underside has no mounted components +- [ ] Map the exposed underside contacts and define the carrier isolation region - [ ] Identify and measure the actual ESP32 antenna keepout -- [ ] Measure the USB-C shell, mating-plug, cable-head, and service-access envelope +- [x] Measure the ESP32 USB-C shell envelope +- [ ] Measure the USB-C mating-plug/cable-head envelope and define carrier-edge, + enclosure, and service-access clearances - [ ] Establish the external 5 V / USB-C VBUS topology and mixed-source backfeed behavior - [ ] Verify the Q1 footprint and multipad mapping - [ ] Verify the F2 holder footprint and service/removal clearance diff --git a/docs/HARDWARE_BASELINE.md b/docs/HARDWARE_BASELINE.md index 9b60547..0c4a01c 100644 --- a/docs/HARDWARE_BASELINE.md +++ b/docs/HARDWARE_BASELINE.md @@ -1,14 +1,17 @@ # Hardware baseline — Rev A Phase 1 -Rev A.4.1 is the current authoritative schematic baseline. It is intentionally -schematic-only: there is no missing authoritative PCB artifact to recover. The -first Rev A `.kicad_pcb` is being created as the next Phase-1 implementation -stage. +Rev A.4.1 is the current authoritative schematic baseline. Its +[KiCad project source](../hardware/kicad/JumpJet_RevA/README.md) is checked into +the repository. The source is intentionally schematic-only: the first Rev A +`.kicad_pcb` has not yet been created and remains active Phase-1 implementation +work. The detailed living source of truth for measurements, component candidates, design decisions, provisional values, blockers, and validation status is the [Phase 1 hardware register](PHASE1_HARDWARE_REGISTER.md). Presence in that register does not make a candidate BOM-final or approve fabrication. +Checking in the KiCad source likewise does not make the design fabrication-ready +or authorize heater actuation. ## Confirmed diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index 75d7f9a..31b7898 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -5,8 +5,8 @@ Last updated: 2026-09-04 This is the living engineering register for JumpJet Rev A Phase-1 hardware implementation. It records what is known, how it is known, what remains provisional, and which downstream decisions are blocked. Rev A.4.1 is the -current authoritative schematic baseline; the first Rev A PCB is being created -as part of Phase 1. +current authoritative schematic baseline and its KiCad source is checked into +the repository; the first Rev A PCB remains active Phase-1 implementation work. > **Presence in this register does not mean BOM-final, fabrication-approved, or > release-approved. Only the explicit status field carries authority.** @@ -56,18 +56,20 @@ temperatures. | Side edge to row center | ASSUMPTION / PROVISIONAL | Approximately 1.335 mm, derived as `(17.91 - 15.24) / 2`. | Derived from measured body width and provisional nominal row spacing | Medium | Measure actual castellation centerline relative to both module edges. | PCB layout + Fabrication | | Castellation width | MEASURED | 1.96 mm along the module board edge. This is the module castellation width, not a frozen carrier receiving-land width. | Direct caliper measurement of the actual module | High for the measured specimen | Review solder/process margin, inward land depth, mask expansion, and paste treatment before defining the carrier land. | PCB layout + Fabrication | | Non-USB edge to first castellation | MEASURED | 1.00 mm from the non-USB PCB edge to the near edge of the first castellation. This is explicitly not a centerline offset. | Direct caliper measurement of the actual module | High for the measured datum | Establish the footprint datum and directly verify longitudinal pad-center registration at both ends. | PCB layout + Fabrication | -| Castellation receiving lands | ASSUMPTION / PROVISIONAL | Use 18 SMD receiving lands at provisional 2.54 mm pitch and 15.24 mm row spacing. Derive land width from the measured 1.96 mm castellation width with appropriate solder/process margin; exact width, inward depth, mask expansion, paste geometry, and longitudinal registration remain unfrozen. | Physical module measurements and Phase-1 direct-solder architecture | Medium | Complete footprint/process review and pass a 1:1 physical fit check. | PCB layout + Fabrication | +| Derived longitudinal registration | ASSUMPTION / PROVISIONAL | With the footprint origin at the module-body center, +Y toward the non-USB/antenna end, and −Y toward USB, the measured 1.00 mm near-edge offset plus 1.96 mm castellation width places the non-USB end-pad center at Y = +9.855 mm. Using the nominal 20.32 mm span places the USB end-pad center at Y = −10.465 mm. | Derived from two physical measurements and the provisional nominal pitch | Medium-high for the derivation; not physically fit-verified | Verify every center against the actual module on a true-scale plot and confirm the remaining USB-end edge distance. | PCB layout + Fabrication | +| Provisional castellated footprint | ASSUMPTION / PROVISIONAL | Project-local `JumpJet:ESP32-S3_SuperMini_2x9_Castellated_PROVISIONAL` is an unassigned iteration footprint. Origin is module-body center; +Y is non-USB/antenna and −Y is USB. It uses 18 pads at X = ±7.620 mm and Y = −10.465 mm through +9.855 mm on 2.54 mm pitch. Pad size is provisionally 3.40 mm inward/outward depth × 1.80 mm along-edge width. The along-edge width leaves 0.74 mm between pads and is narrower than the measured 1.96 mm castellations; the 3.40 mm depth, mask, and paste treatment are process assumptions. | [Checked-in provisional footprint](../hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9_Castellated_PROVISIONAL.kicad_mod) using current measurements and derived registration | Medium | Review carrier land/process geometry, map underside contacts, verify all physical pin labels, and pass the mandatory 1:1 fit check before assigning it to U2. | Footprint freeze + PCB layout + Fabrication | +| Legacy Rev A.4.1 footprint | CONFIRMED FACT | `JumpJet:ESP32-S3_SuperMini_2x9` is a drilled 18-pad through-hole footprint. It is retained only to resolve the authoritative schematic and is explicitly obsolete for production mounting. | [Checked-in Rev A.4.1 footprint](../hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9.kicad_mod) | High | Do not assign it to a production PCB; replace the schematic assignment only after the provisional SMD footprint passes physical verification. | PCB layout + Fabrication | | Ordinary header fit | MEASURED | Ordinary 2.54 mm header pins physically fit the castellation holes. This supports pitch/alignment evaluation but does not change production attachment to through-hole mounting. | Physical fit check on the actual module | High for fit observation | Measure the actual square posts and verify removable alignment-hole clearance and PCBWay drill tolerance. | PCB layout + Fabrication | | Production mounting | DESIGN DECISION | Direct solder of the castellated module to carrier-PCB SMD lands. The current drilled through-hole footprint is not the production architecture unless later physical verification explicitly reverses this decision. | Phase-1 mounting decision; inspection of Rev A.4.1 project footprint | High | Complete and physically verify the project-local castellated footprint. | PCB layout + Fabrication | | Mounted component side | CONFIRMED FACT | All mounted components are on the top side. The underside is physically flat apart from PCB/contact metallization. | Direct top/bottom inspection of the actual module | High | Preserve the observed orientation in the footprint and 1:1 plot. | PCB layout + Fabrication | | Physical Pin 1 | CONFIRMED FACT | Pin 1 has been physically identified from the module photograph. | Direct photographic inspection of the actual module | High | Document the footprint datum/orientation and verify every remaining pad number and label. | PCB layout + Fabrication | | Underside exposed contacts/test pads | CONFIRMED FACT | Exposed underside contacts/test pads are present despite there being no mounted underside components. The carrier must not place vias, exposed pads, or other exposed conductive features where unintended contact is possible; even soldermask-covered copper requires spacing/stackup review. | Direct underside inspection of the actual module | High for presence; envelope not mapped | Measure and map the exact contact locations/envelope before fabrication and verify the isolation region in the footprint/PCB. | Footprint freeze + PCB layout + Fabrication | -| Central underside PCB window | ASSUMPTION / PROVISIONAL | **Current decision state: REEVALUATION REQUIRED.** Underside component clearance no longer justifies a window. A solid carrier region with controlled isolation and soldermask beneath the module is now the leading architecture to evaluate, with no exposed carrier copper or vias where underside contacts could touch. Retain a window only if cleaning, inspection, thermal, assembly, or mechanical review supplies an independent justification. | Direct inspection confirms a flat underside with no mounted components, but with exposed electrical/test contacts | Medium | Compare solid-carrier and independently justified window options; map underside contacts; review isolation, cleaning, inspection, thermal, assembly, and structural needs. | Footprint freeze + PCB layout + Fabrication | -| Underside window geometry | TBD / BLOCKED | No window geometry is frozen because the need for a window has been reopened. If retained for an independently validated reason, its length, width, corners, and support rails must be defined. | Central-window reevaluation | High confidence that no geometry is approved | Complete the architecture review before defining any opening. | PCB layout + Fabrication | +| Solid carrier beneath module | DESIGN DECISION | Use solid carrier PCB beneath the module. No underside components require height clearance, and no independent manufacturing or mechanical need for a cutout was found. Keep the region isolation-controlled and soldermask-covered, with no exposed copper or vias where module contacts could touch. The opening is not a safety airflow feature. | Direct inspection: no underside components; exposed contacts are present | High for architecture; contact map still incomplete | Map the underside contacts; review mask registration, dielectric/isolation margin, cleaning, and routing before fabrication. | Footprint freeze + PCB layout + Fabrication | +| Central PCB window | DESIGN DECISION | Do not create a central window on current evidence. Reopen only if a concrete cleaning, inspection, thermal, assembly, or mechanical requirement is demonstrated. | Solid-carrier architecture review | High | None unless new evidence independently justifies a window. | None | | Optional temporary locating holes | ASSUMPTION / PROVISIONAL | Assembly concept only: two holes total at the ends of one castellated row may accept removable ordinary 2.54 mm male-header pins for alignment/tack soldering. The header is removed afterward; production attachment remains the castellated solder joints. | Phase-1 assembly concept and physical header-fit observation | Medium | Verify post dimensions, insertion/removal clearance, PCBWay drill capability/tolerance, land support, antenna/USB clearance, and that the module is not forced into alignment. | PCB layout + Fabrication | -| Locating-hole geometry | ASSUMPTION / PROVISIONAL | Candidate holes are Ø1.10 mm NPTH. Previously proposed X = −7.620 mm, Y = ±12.700 mm coordinates are not usable or frozen until the footprint origin and orientation datum are explicitly documented and physically checked. | Phase-1 assembly-aid review using a provisional nominal square-header concept | Low-medium | Document the datum/orientation; measure the actual header; verify finished-hole and positional tolerances; physically fit-test insertion/removal; check interference with receiving lands, antenna, and USB. | PCB layout + Fabrication | +| Locating-hole geometry | ASSUMPTION / PROVISIONAL | Candidate holes remain Ø1.10 mm NPTH. The old X = −7.620 mm, Y = ±12.700 mm pair does not form one-pitch extensions of the newly derived asymmetric end-pad centers under the documented body-center/+Y-antenna datum, so it is not implemented in the provisional footprint. | Updated longitudinal-registration audit of the earlier assembly-aid proposal | High confidence that the old coordinates are unreconciled | Measure the actual header; derive new candidate coordinates from verified pad centers; verify PCBWay finished-hole/position tolerances; physically fit-test insertion/removal and check USB/antenna/land interference. | PCB layout + Fabrication | | Likely onboard antenna | ASSUMPTION / PROVISIONAL | The small red/white ceramic component at the non-USB end is treated as the likely onboard 2.4 GHz antenna unless inspection or revision-matched evidence disproves it. Do not assume WROOM-class RF performance. | Direct top-side inspection and component appearance | Medium | Confirm function/location and establish the antenna datum and installed orientation. | PCB layout + Fabrication | -| Antenna keepout | ASSUMPTION / PROVISIONAL | Prefer the antenna at a carrier-board edge. Reserve an RF keepout around and beneath it from copper, planes, vias, traces, heater-current copper, switch-node copper, fuse hardware, and large grounded metal; preserve enclosure clearance where practical. Exact geometry and affected layers remain TBD. | Likely antenna location plus Phase-1 RF layout direction | Medium | Define the exact keepout and validate Wi-Fi RSSI/range after final PCB placement and again after enclosure installation. | PCB layout + Fabrication | +| Antenna keepout | ASSUMPTION / PROVISIONAL | Prefer the antenna at a carrier-board edge. The provisional footprint graphically reserves the interior area X = ±6.50 mm, Y = +7.835 to +11.835 mm at the likely antenna end as a visible no-copper warning. This is not an enforced KiCad rule area and is not exact RF geometry. No heater-current or buck switch-node copper, fuse hardware, planes, vias, traces, or large metal may be placed there or immediately beyond the antenna end until the keepout is verified. | Likely antenna location plus conservative footprint iteration | Medium-low for exact bounds | Confirm the antenna and feed geometry, replace the graphic with an enforced all-applicable-layer rule, define enclosure clearance, and validate installed Wi-Fi RSSI/range. | PCB layout + Fabrication | | USB-C mechanical keepout | TBD / BLOCKED | The shell is measured, but the mating-plug envelope, cable-head clearance, enclosure opening, and carrier-board edge relationship remain undefined. Do not derive the complete keepout from shell dimensions alone. | Direct shell measurements; service-access geometry incomplete | High confidence that evidence remains incomplete | Complete plug, cable-head, carrier-edge, and enclosure-access measurements. | PCB layout + Fabrication | | Mandatory 1:1 verification | DESIGN DECISION | The actual module must be placed on a true-scale plot before footprint freeze. All 18 castellations, body, Pin 1/orientation, optional locating holes, USB projection, antenna direction/keepout, and underside isolation region must pass without forced alignment. | Phase-1 acceptance requirement | High | Perform and document the physical fit check using the final proposed footprint. | Fabrication | @@ -84,6 +86,17 @@ temperatures. | Buck converter capacity target | ASSUMPTION / PROVISIONAL | Use at least 1.5 A continuous capability as an initial converter target. This is not a selected MPN or BOM-final rating. | Preliminary ESP32-S3 peak/burst allowance plus light interface-load margin | Medium | Complete the 5 V load inventory and converter loss/thermal derating at the maximum installed chamber/PCB temperature; increase the rating if required. | PCB layout + BOM freeze + Fabrication | | Power-management firmware assumptions | TBD / BLOCKED | No firmware behavior may assume a source topology or power-good behavior that has not been established in hardware. | Power architecture unresolved | High | Close power-state truth table and any available power-good/reset behavior. | Firmware constants | +### Provisional 5 V load inventory + +| Load | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| ESP32-S3 Super Mini | TBD / BLOCKED | Budget peak Wi-Fi/boot current, not average current. No revision-matched peak value is frozen. | Exact module power topology and flash/module revision remain unverified | High confidence that a numeric load is missing | Measure boot and radio bursts on the actual module across supported operating conditions. | BOM freeze + Fabrication | +| Gate buffer and Q1 gate charging | TBD / BLOCKED | Include buffer static/dynamic current and Q1 gate-charge current at the eventual switching frequency. Gate drive belongs only to `+5V_SYS/GATE`. | SN74AHCT125 and CSD18540Q5B are not yet qualified as a final combination | High confidence that a numeric load is missing | Select/qualify driver architecture; freeze PWM only after waveform/loss review; measure rail transients. | BOM freeze + Firmware constants + Fabrication | +| Fan PWM/tach interface | TBD / BLOCKED | Include open-drain PWM, tach pull-up/interface, and any protection/filter loads; fan motor power remains on fused 24 V. | Four-wire interface architecture; candidate-specific electrical details pending | High confidence that a numeric load is missing | Complete delivered-fan datasheet/bench characterization and select interface values. | BOM freeze + Fabrication | +| Sensor/reference support | TBD / BLOCKED | Include every actual 3.3 V/5 V thermistor, reference, ADC-filter, and level-interface load after the sensing implementation is finalized. | Rev A.4.1 sensing architecture is not a frozen load inventory | High confidence that a numeric load is missing | Reconcile final sensing schematic and regulator/LDO efficiencies. | BOM freeze + Fabrication | +| Qwiic and service expansion | ASSUMPTION / PROVISIONAL | Do not consume unbounded regulator margin. If retained, define and enforce an allowed service/expansion load. | Rev A.4.1 includes Qwiic/service provisions but no production load allocation | Medium | Decide retained interfaces and maximum external current; protect and include them in simultaneous worst case. | BOM freeze + Fabrication | +| Converter headroom | ASSUMPTION / PROVISIONAL | At least 1.5 A continuous output remains an iteration floor, not a completed budget or selected regulator. | Phase-1 sizing direction | Medium | Sum measured simultaneous peaks, add explicit engineering margin, and verify converter efficiency/temperature at maximum installed ambient. | PCB layout + BOM freeze + Fabrication | + ## 4. Heater path and independent interruption | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | @@ -98,23 +111,24 @@ temperatures. |---|---|---|---|---|---|---| | Q1 candidate | STRONG CANDIDATE | Texas Instruments CSD18540Q5B; 60 V logic-level N-MOSFET; maximum `RDS(on)` approximately 3.3 mΩ at 4.5 V. Not BOM-final. | Manufacturer data and Phase-1 component review | High for published characteristics | Reconfirm ordering code, lifecycle, package, pin/multipad mapping, and production availability. | PCB layout + BOM freeze + Fabrication | | Estimated Q1 conduction loss | ASSUMPTION / PROVISIONAL | About 0.205 W at 7.89 A and 0.229 W at 8.33 A using 3.3 mΩ: `P = I²R`. These are max-`RDS(on)`-basis conduction estimates only, not total hot operating loss. | Candidate data and measured/design currents | Medium | Include hot `RDS(on)`, switching loss, duty/frequency, gate waveform, copper spreading, and measured junction/board temperature. | PCB layout + BOM freeze + Firmware constants + Fabrication | -| Rev A.4.1 gate buffer | CONFIRMED FACT | Rev A.4.1 uses an SN74AHCT125 for gate buffering, and the used output-enable inputs are tied low. This records the present schematic, not approval of its power-transition behavior. | Current Rev A.4.1 schematic | High | Reinspect after the required schematic correction and verify the implemented channel mapping. | PCB layout + Fabrication | +| Rev A.4.1 gate buffer | CONFIRMED FACT | Rev A.4.1 uses an SN74AHCT125 for gate buffering, and the used output-enable inputs are tied low. TI documents OE high as disabled/high-impedance and specifically recommends an OE-to-VCC pull-up for high impedance during power-up/down. The reviewed catalog/datasheet material does not state an `Ioff` partial-power-down guarantee. | [Checked-in Rev A.4.1 schematic](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch); [TI SN74AHCT125 product/datasheet page](https://www.ti.com/product/SN74AHCT125) | High | Reinspect after correction and verify channel mapping, OE pull-up behavior, and powered/unpowered input/output leakage. | PCB layout + Fabrication | | Gate network concept | ASSUMPTION / PROVISIONAL | Provisional 47 Ω gate resistor and a direct Q1 gate pull-down. The direct pull-down must be retained independently of MCU and buffer state. | Current Rev A.4.1 schematic concept and Phase-1 default-OFF requirement | Medium | Select the pull-down value and gate resistance from leakage, turn-off, waveform, PWM, and switching-loss validation. | PCB layout + BOM freeze + Firmware constants + Fabrication | -| Required gate-drive correction | DESIGN DECISION | Heater gate drive must be hardware-default-disabled through power-up, power-down, reset, and brownout. Power the gate driver only from the 24 V-derived `+5V_SYS/GATE` domain so USB-only MCU power cannot drive Q1. Use a driver with documented partial-power-down behavior or equivalent isolation. Add test points for gate-driver power, OE, and Q1 gate. No replacement driver is BOM-final. | Phase-1 power/backfeed and default-OFF review | High | Revise the schematic; select/qualify the driver or isolation; verify OE biasing, partial-power sequencing, and Q1 gate voltage through all 24 V/USB/reset transitions. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Required gate-drive correction | DESIGN DECISION | Heater gate drive must be hardware-default-disabled through power-up, power-down, reset, brownout, partial power, USB-only service, and supply sequencing. Power the driver only from `+5V_SYS/GATE`; bias each used active-low OE high to its own rail by hardware; retain the direct Q1 gate pull-down; isolate a USB-powered MCU from an unpowered driver using documented partial-power-down behavior or equivalent circuitry. Add test points for `+5V_SYS/GATE`, `+5V_MCU`, OE, Q1 gate, and Q1 source reference. No replacement driver is BOM-final. | Phase-1 power/backfeed review and TI OE guidance | High | Revise the schematic; determine whether SN74AHCT125 can be retained after leakage/sequencing qualification or select a documented alternative; verify Q1 gate voltage through all 24 V/USB/reset transitions. | PCB layout + BOM freeze + Firmware constants + Fabrication | | Q1 footprint and thermal implementation | TBD / BLOCKED | Exact verified KiCad footprint, thermal-pad implementation, and copper spreading are not frozen. | Footprint/PCB validation not completed | High confidence that implementation is incomplete | Verify package drawing and pad mapping; complete thermal/current layout and measurement plan. | PCB layout + Fabrication | +| Rev A.4.1 Q1 mapping defect | CONFIRMED FACT | Q1 currently uses a generic `Q_NMOS_GDS` symbol and unresolved `Package_DirectFET:TBD` footprint. CSD18540Q5B is published as an 8-pin 5 mm × 6 mm VSON-CLIP (DNK), so the current footprint assignment cannot represent the candidate package or multipad mapping. | [Rev A.4.1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch); [TI CSD18540Q5B product/datasheet page](https://www.ti.com/product/CSD18540Q5B) | High | Build/verify the exact DNK symbol-to-pad mapping, exposed/current pads, land pattern, solder treatment, and thermal copper against the manufacturer drawing. | PCB layout + BOM freeze + Fabrication | ## 6. F2 fuse and holder | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | |---|---|---|---|---|---|---| | F2 fuse candidate | STRONG CANDIDATE | Littelfuse 0287015.U, 15 A ATOF. Not BOM-final. The 15 A candidate provides healthier margin around the approximately 7.9–8.33 A load than a 10 A fuse after elevated-temperature derating. | Heater characterization, conservative design basis, and Phase-1 component review | Medium-high | Validate production-PSU short-circuit/current-limit behavior, time-current coordination, ambient derating, interrupt behavior, and service conditions. | PCB layout + BOM freeze + Fabrication | -| F2 holder candidate | STRONG CANDIDATE | Littelfuse 178.6165.0001. Not BOM-final. | Phase-1 component review | Medium-high | Verify exact footprint, current/temperature performance, pad and copper heating, mechanical retention, and removal/service clearance. | PCB layout + BOM freeze + Fabrication | +| F2 holder candidate | STRONG CANDIDATE | Littelfuse 178.6165.0001, published as a four-terminal PCB-mount ATO holder. Not BOM-final. Rev A.4.1 has no F2 footprint assigned. | [Littelfuse 178.6165.0001 product page](https://www.littelfuse.com/products/fuses-overcurrent-protection/fuse-holders-fuse-blocks-accessories/fuse-holders/in-line-fuse-holders/ato-flr/178-6165-0001); checked-in schematic | Medium-high | Verify manufacturer drawing, four-hole/pad mapping, voltage/current and chamber-temperature performance, pad/copper heating, retention, and fuse removal/service clearance. | PCB layout + BOM freeze + Fabrication | ## 7. J2 and heater wiring | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | |---|---|---|---|---|---|---| -| J2 candidate | STRONG CANDIDATE | Phoenix Contact 1715022 / MKDS 1,5/2; nominal IEC current approximately 17.5 A. The 8.33 A heater basis is approximately 48% of that nominal value. Not BOM-final. | Manufacturer rating and Phase-1 component review | Medium-high | Verify exact footprint, conductor/ferrule compatibility, torque, terminal and pad temperature, creepage/clearance, and service access. | PCB layout + BOM freeze + Fabrication | +| J2 candidate | STRONG CANDIDATE | Phoenix Contact 1715022 / MKDS 1,5/2; nominal IEC current approximately 17.5 A and 5.00 mm pitch. Rev A.4.1 assigns KiCad footprint `TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal`. The 8.33 A heater basis is approximately 48% of the nominal current. Not BOM-final. | [Phoenix Contact 1715022 catalog](https://www.phoenixcontact.com/us/products/1715022); checked-in schematic | Medium-high | Compare the KiCad land pattern to the current manufacturer drawing; verify conductor/ferrule compatibility, torque, non-thermal-relief current entry, terminal/pad temperature, and service access. | PCB layout + BOM freeze + Fabrication | | Heater wire | DESIGN DECISION | Use 16 AWG high-temperature-insulated wire, with approximately 200 °C-class insulation near the heater. | Current requirement and heater thermal environment | High for direction | Finalize insulation construction, color, length, routing, bend radius, abrasion protection, and installed-temperature margin. | BOM freeze + Fabrication | | Wire family | STRONG CANDIDATE | TE Connectivity/Raychem Spec 55 family; examples 55/0212-16-2 red and 55/0212-16-0 black. Not BOM-final. | Phase-1 wiring review | Medium | Verify exact construction, approvals, availability, termination method, voltage drop, and harness temperature. | BOM freeze | | Heater termination details | TBD / BLOCKED | Ferrule type, terminal torque, strain relief, wire length, voltage drop, and terminal/harness temperatures are not frozen. | Harness and installed validation incomplete | High confidence that details are incomplete | Build and thermally validate the production-intent harness and termination. | BOM freeze + Fabrication | @@ -125,6 +139,7 @@ temperatures. | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | |---|---|---|---|---|---|---| | Original integrated fan | CONFIRMED FACT | YD4020HBL, 24 V, 0.13 A, two-wire, no native PWM, and no tach. Its two-wire control architecture has been superseded by the four-wire PWM/tach direction. | Physical/product identification from CZ4060 assembly review | Medium-high | Confirm nameplate and electrical behavior if retained for comparative testing only. | None | +| Rev A.4.1 two-wire fan block | CONFIRMED FACT | The authoritative schematic still contains F3, J3, D2, Q2, R3, and R4 as a fused two-wire low-side-switched fan block. It is obsolete for the selected native four-wire direction and has not yet been replaced. | [Checked-in Rev A.4.1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) | High | Replace with continuous fused 24 V and ground, separate open-drain PWM, and 3.3 V-safe tach provisions after candidate pinout/electrical review. | PCB layout + BOM freeze + Fabrication | | Replacement fan prototype | PROTOTYPE CANDIDATE | Sanyo Denki 9GA0424P3J001; ordered for characterization, ETA 2026-09-15. Not BOM-final. | Prototype purchase record | High for order state; unvalidated for application | Complete electrical, airflow, pressure, acoustic, thermal, stall, and installed-system characterization. | BOM freeze + Firmware constants | | Four-wire fan architecture | DESIGN DECISION | Continuous fused 24 V fan power, separate PWM control, and separate tach/RPM feedback. Do not low-side PWM the fan's 24 V supply when using native four-wire control. | Phase-1 fan architecture decision | High | Verify candidate interface requirements and qualify final fan/control parts. | PCB layout + BOM freeze + Fabrication | | Fan PWM interface | ASSUMPTION / PROVISIONAL | Provide a fan-compatible open-drain interface; exact circuit and component values remain pending datasheet and bench verification. | Common four-wire architecture and Phase-1 direction; candidate-specific evidence incomplete | Medium | Verify pinout, PWM voltage/current/frequency requirements, pull-up behavior, open/high-Z behavior, and 0% behavior. | PCB layout + BOM freeze + Firmware constants + Fabrication | @@ -151,7 +166,12 @@ identify a valid production cutoff temperature or mounting location. | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | |---|---|---|---|---|---|---| -| Rev A PCB state | CONFIRMED FACT | PCB design is the current Rev A implementation stage. There is no missing authoritative PCB artifact to recover; a `.kicad_pcb` has not yet been created and must now be designed. | Rev A.4.1 package scope and Phase-1 project state | High | Create and review the first Rev A PCB from the authoritative schematic. | PCB layout + Fabrication | +| Rev A PCB state | CONFIRMED FACT | PCB design is the current Rev A implementation stage. A `.kicad_pcb` has not yet been created and must now be designed. | Rev A.4.1 package scope and Phase-1 project state | High | Create and review the first Rev A PCB from the authoritative schematic. | PCB layout + Fabrication | +| Authoritative KiCad source | CONFIRMED FACT | Rev A.4.1 native project source is checked in under [`hardware/kicad/JumpJet_RevA/`](../hardware/kicad/JumpJet_RevA/README.md): root schematic, four child sheets, project symbol/footprint libraries, library tables, minimal project file, preliminary BOM, and archive provenance README. | `JumpJet_Controller_RevA4_1_J3_JST_XH.zip` intake and checked-in source | High for file provenance | Open in native KiCad and run ERC when `kicad-cli` or desktop KiCad is available. | PCB layout + Fabrication | +| KiCad source schema/validation | ASSUMPTION / PROVISIONAL | Root schematic declares schema `20211014`/generator `kiutils`; child sheets declare `20260306`/custom generator; footprint files declare `20240108`. Hierarchical filenames and project-local library paths resolve by static inspection, but native application open/ERC has not been run in this environment. | File headers, root-sheet references, and library tables | High for observed metadata; medium for openability | Open/save only after review, verify no unintended migration diff, resolve all libraries, then run native ERC. | PCB layout + Fabrication | +| Unresolved footprint references | TBD / BLOCKED | Rev A.4.1 intentionally contains unresolved placeholders `TBD:High_Current_2Pin`, `TBD:DC_DC_Module`, `TBD:Aux_2Pin`, and `Package_DirectFET:TBD`. Standard-library and project-local non-placeholder names were identified, but native library resolution is not yet proven. | Static scan of checked-in schematic footprint properties | High | Replace every placeholder with a verified project/standard footprint and run native library resolution/ERC before PCB import. | PCB layout + BOM freeze + Fabrication | +| Preliminary archive BOM | CONFIRMED FACT | `BOM_PRELIMINARY.csv` is checked in as source context only. Its placeholders and historical values do not override this register and are not BOM-final. | [Rev A.4.1 preliminary BOM](../hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv) | High | Reconcile every line against reviewed schematic candidates and replace with a controlled production BOM later. | BOM freeze + Fabrication | +| J1/F1/MOD1 implementation | TBD / BLOCKED | Rev A.4.1 uses `J1` value `24V IN / 20A MIN` with placeholder footprint `TBD:High_Current_2Pin`; `F1` value `15A TBD` with no footprint; and `MOD1` value `24V→5V BUCK TBD` with placeholder footprint `TBD:DC_DC_Module`. These are schematic placeholders, not selections. | [Checked-in Rev A.4.1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) and preliminary BOM | High | Select/qualify exact input connector, main protection, and regulator architecture/parts; verify footprints, service/thermal behavior, transients, and PSU/fuse coordination. | PCB layout + BOM freeze + Fabrication | | Starting stackup | ASSUMPTION / PROVISIONAL | Two layers, 1.6 mm FR-4, 2 oz copper. | Phase-1 routing/current-density starting point | Medium | Review high-current routing, grounding, RF, mechanical, thermal, cost, and PCBWay manufacturing requirements before freeze. | PCB layout + BOM freeze + Fabrication | | Heater-path copper geometry | ASSUMPTION / PROVISIONAL | Keep heater-path neckdowns at least 4 mm as an initial minimum; prefer broad 8–10 mm or wider pours where practical; minimize vias and unnecessary current-loop area. Place the high-current/safety path before convenience circuitry. | 8.33 A conservative design basis and Phase-1 layout direction | Medium | Calculate and inspect every bottleneck, layer transition, pad entry, thermal relief, and temperature rise for the final stackup. | PCB layout + Fabrication | | Ground and return strategy | DESIGN DECISION | Prefer a continuous ground plane with a controlled heater/fan/buck high-current return corridor. Thermistor/ADC returns must not share narrow or common-impedance copper with heater current. Do not create arbitrary split grounds that damage ESP32 RF return integrity. | Phase-1 signal-integrity and current-return strategy | High for topology; implementation provisional | Review actual return geometry, buck loops, ADC noise, RF keepout, and current-path coupling after placement/routing. | PCB layout + Fabrication | @@ -163,22 +183,23 @@ identify a valid production cutoff temperature or mounting location. Fabrication remains blocked until all of the following are closed or deliberately bounded by reviewed production-intent provisions: -- ESP32 carrier receiving-land geometry and exact body/pad registration +- ESP32 provisional receiving-land depth/process geometry and 1:1 body/pad registration - complete pin numbering/label verification beyond the physically identified Pin 1 - underside exposed-contact mapping and carrier isolation review -- central carrier-region/window reevaluation; window/support-rail geometry only if a window remains independently justified -- antenna identity, exact keepout, and installed RSSI/range validation +- antenna identity, enforced exact keepout, and installed RSSI/range validation - USB connector, plug, cable-head, and service-access envelope -- physical fit of the optional locating header +- reconciled locating-hole coordinates and physical fit of the optional header - external 5 V / USB-C VBUS topology - USB/onboard mixed-source and backfeed testing - hardware-default-OFF gate-driver schematic correction - complete regulator load inventory and installed-temperature thermal analysis - Q1 multipad/footprint and F2 holder-footprint verification +- four-wire fan schematic/interface implementation and candidate electrical verification - TF1/TS1 part, mounting, and thermal-coupling implementation - J1, F1, and MOD1 part and footprint selections - PCB envelope, mounting-hole coordinates, connector-facing edges, and USB datum - final 1:1 production-footprint fit check with the actual module +- native KiCad project-open/library-resolution check and ERC ## Register maintenance rules diff --git a/hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9_Castellated_PROVISIONAL.kicad_mod b/hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9_Castellated_PROVISIONAL.kicad_mod new file mode 100644 index 0000000..ba06134 --- /dev/null +++ b/hardware/kicad/JumpJet_RevA/JumpJet.pretty/ESP32-S3_SuperMini_2x9_Castellated_PROVISIONAL.kicad_mod @@ -0,0 +1,54 @@ +(footprint "ESP32-S3_SuperMini_2x9_Castellated_PROVISIONAL" + (version 20240108) + (generator "jumpjet_phase1") + (layer "F.Cu") + (descr "PROVISIONAL direct-solder footprint for measured ESP32-S3 Super Mini; 1:1 fit and contact/RF keepouts not verified") + (tags "PROVISIONAL ESP32 S3 SuperMini castellated 2x9 2.54mm") + (attr smd) + (fp_rect (start -8.955 -11.835) (end 8.955 11.835) + (stroke (width 0.20) (type default)) (fill none) (layer "F.Fab")) + (fp_rect (start -4.420 -13.235) (end 4.420 -4.355) + (stroke (width 0.20) (type default)) (fill none) (layer "F.Fab")) + (fp_rect (start -9.620 -13.735) (end 9.620 12.335) + (stroke (width 0.05) (type default)) (fill none) (layer "F.CrtYd")) + (fp_rect (start -6.500 7.835) (end 6.500 11.835) + (stroke (width 0.20) (type dash)) (fill none) (layer "Dwgs.User")) + (fp_line (start -8.955 -11.835) (end -8.955 -8.900) + (stroke (width 0.30) (type default)) (layer "F.SilkS")) + (fp_line (start -8.955 -11.835) (end -6.020 -11.835) + (stroke (width 0.30) (type default)) (layer "F.SilkS")) + (fp_line (start -8.955 11.835) (end -6.800 11.835) + (stroke (width 0.20) (type default)) (layer "F.SilkS")) + (fp_line (start 6.800 11.835) (end 8.955 11.835) + (stroke (width 0.20) (type default)) (layer "F.SilkS")) + (fp_text reference "REF**" (at 0 13.100 0) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15)))) + (fp_text value "ESP32-S3_SuperMini_2x9_Castellated_PROVISIONAL" (at 0 14.600 0) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15)))) + (fp_text user "USB-C 8.84 W x 3.12 H" (at 0 -12.350 0) (layer "Cmts.User") + (effects (font (size 0.70 0.70) (thickness 0.10)))) + (fp_text user "ANTENNA END - PROVISIONAL NO-COPPER AREA" (at 0 10.200 0) (layer "Dwgs.User") + (effects (font (size 0.55 0.55) (thickness 0.09)))) + (fp_text user "NO EXPOSED COPPER OR VIAS UNDER MODULE; UNDERSIDE CONTACT MAP TBD" (at 0 0 90) (layer "Cmts.User") + (effects (font (size 0.55 0.55) (thickness 0.09)))) + (fp_text user "ORIGIN: BODY CENTER; +Y ANTENNA / -Y USB" (at 0 5.600 0) (layer "Cmts.User") + (effects (font (size 0.55 0.55) (thickness 0.09)))) + (pad "1" smd rect (at -7.620 -10.465) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask")) + (pad "2" smd roundrect (at -7.620 -7.925) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "3" smd roundrect (at -7.620 -5.385) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "4" smd roundrect (at -7.620 -2.845) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "5" smd roundrect (at -7.620 -0.305) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "6" smd roundrect (at -7.620 2.235) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "7" smd roundrect (at -7.620 4.775) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "8" smd roundrect (at -7.620 7.315) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "9" smd roundrect (at -7.620 9.855) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "10" smd roundrect (at 7.620 -10.465) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "11" smd roundrect (at 7.620 -7.925) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "12" smd roundrect (at 7.620 -5.385) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "13" smd roundrect (at 7.620 -2.845) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "14" smd roundrect (at 7.620 -0.305) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "15" smd roundrect (at 7.620 2.235) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "16" smd roundrect (at 7.620 4.775) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "17" smd roundrect (at 7.620 7.315) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) + (pad "18" smd roundrect (at 7.620 9.855) (size 3.400 1.800) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.15)) +) diff --git a/hardware/kicad/JumpJet_RevA/README.md b/hardware/kicad/JumpJet_RevA/README.md index c9ca21b..28f0be0 100644 --- a/hardware/kicad/JumpJet_RevA/README.md +++ b/hardware/kicad/JumpJet_RevA/README.md @@ -20,6 +20,10 @@ sheets in this directory. Project-local symbols and footprints resolve through [`docs/PHASE1_HARDWARE_REGISTER.md`](../../../docs/PHASE1_HARDWARE_REGISTER.md). - Native KiCad ERC has not been run in this environment because `kicad-cli` is unavailable. The archive provenance note records the same limitation. +- Hierarchical-sheet and project-local library paths pass static resolution. + Placeholder footprint references `TBD:High_Current_2Pin`, + `TBD:DC_DC_Module`, `TBD:Aux_2Pin`, and `Package_DirectFET:TBD` remain + intentionally unresolved and must be replaced before PCB implementation. ## Footprint status @@ -27,6 +31,15 @@ sheets in this directory. Project-local symbols and footprints resolve through footprint referenced by Rev A.4.1. It is retained so the current schematic resolves, but it is obsolete for the selected production mounting method. +`JumpJet.pretty/ESP32-S3_SuperMini_2x9_Castellated_PROVISIONAL.kicad_mod` is an +unassigned iteration footprint for direct castellated soldering. Its body, +USB shell, nominal pitch/row spacing, and derived longitudinal registration use +the current physical evidence. Its receiving-land depth, antenna graphic, and +underside-contact exclusion remain provisional. It deliberately has no locating +holes because the previous coordinates do not reconcile with the updated +longitudinal datum. Do not release or assign it without the required 1:1 fit +check and completion of the blockers in the hardware register. + ## Source-package exclusions The archive's repair, warning-cleanup, presentation, polish, and connector From c4a16fb0c3617ef80f421793eae4f47cf593bee2 Mon Sep 17 00:00:00 2001 From: Daniel Brown Date: Fri, 4 Sep 2026 10:43:07 -0400 Subject: [PATCH 06/20] docs: record heater void packing blocker --- docs/PHASE1_HARDWARE_REGISTER.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index 31b7898..dd2a9b7 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -166,6 +166,13 @@ identify a valid production cutoff temperature or mounting location. | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | |---|---|---|---|---|---|---| +| Available internal void model | MEASURED | The supplied AP242 STEP contains one closed solid named `Internal Space`, expressed in metres. In its neutral CAD frame it spans X = -16.700 to +45.928 mm, Y = 0 to 268.000 mm, and Z = 0 to 72.450 mm: an overall 62.628 × 268.000 × 72.450 mm bounding box. The solid is a constant seven-edge X-Z profile extruded along Y, with approximately 2,728.653 mm² section area and 731,279 mm³ (0.731 L) volume. These are available-void measurements, not enclosure-wall or mounting-boss geometry. | `Part Studio 1 - Internal Space.step`, Onshape export dated 2026-09-04, SHA-256 `608b08534cdaa03be100230e1626da68c53977416f97d7f18e626874d7fa79fc`; direct STEP entity/coordinate analysis | High for STEP geometry and units | Establish how the neutral CAD axes map to printer rear/left/up and side-panel access; correlate the void with physical walls, openings, fasteners, and adjacent printer hardware. | PCB envelope + mounting + Fabrication | +| Heater/fan occupied envelope | MEASURED | The current heater plus fan assembly occupies a 41 × 41 × 105 mm rectangular envelope inside the same available void. The production power supply remains outside the printer. | Direct assembly-envelope measurement supplied for the Phase-1 placement study | High for the supplied envelope; attachment datums are not encoded | Record the hot-air outlet datum, connector and wire exits, attachment features, and required operational/service clearances. | Heater placement + PCB envelope + mounting + Fabrication | +| Heater intake face | CONFIRMED FACT | The 41 × 41 mm face selected for possible PCB mounting is the heater/fan assembly's cold-air intake side. Incidental intake-air cooling must not be a safety dependency. | Physical assembly identification supplied for the Phase-1 placement study | High for face function | Record fan aperture and mounting-hole geometry, airflow direction in printer coordinates, connector/wire exits, and required unobstructed inlet/service volumes. | Heater placement + PCB envelope + mounting + Fabrication | +| PCB-over-intake architecture | ASSUMPTION / PROVISIONAL | Leading architecture is heater/fan → cold-air intake face → independent support/standoffs → controller PCB. The PCB may overhang the 41 × 41 mm fan body if later geometry and airflow testing support it; no standoff height, hole pattern, board outline, or service envelope is frozen. | Phase-1 mechanical steering; favorable cold-side topology | Medium concept confidence; current STEP packing fails | Resolve the heater-envelope/void mismatch first, then measure fan holes/aperture, bracket load path, standoff stack, PCB/component heights, inlet flow area, connector mating/fuse-pull/USB zones, and side-panel removal path. | PCB envelope + mounting + Fabrication | +| Heater fit in STEP principal frame | TBD / BLOCKED | A 105 mm heater axis parallel to the STEP's 268 mm extrusion requires its 41 × 41 mm section to fit wholly inside the X-Z profile. It does not: the maximum axis-aligned square supported by the exact profile is approximately 37.825 mm, before any airflow, wall, vibration, or assembly clearance. Orienting 105 mm along X or Z is also excluded by the 62.628 mm and 72.450 mm overall bounds. Arbitrary compound-angle placement is not established and would not justify PCB mechanics without a full collision/service study. | Exact STEP profile versus supplied 41 × 41 × 105 mm occupied envelope | High for principal-axis non-fit | Confirm the STEP represents the intended complete available volume and confirm the heater envelope/datum. If both are correct, revise the heater/fan packaging or provide a larger/corrected void model before selecting a PCB zone. | Heater placement + PCB envelope + Edge.Cuts + Fabrication | +| PCB envelope after heater occupancy | TBD / BLOCKED | No defensible residual PCB envelope exists yet because the required heater envelope has no verified placement in the supplied void. Raw volume subtraction would leave about 0.555 L, but volume alone does not prove packability, airflow, access, connector clearance, or a mounting plane. Do not derive Edge.Cuts from the void bounding box. | Coupled heater/PCB packing audit | High confidence that placement is blocked | Resolve heater fit and orientation first; then capture mounting faces, clearances, inlet/outlet direction, service path, cable corridors, antenna direction, and connector tool access. | PCB envelope + Edge.Cuts + Fabrication | +| Production PSU location | DESIGN DECISION | Keep the production power supply outside the printer; only the protected incoming 24 V harness enters the Jump Jet installation volume. | Phase-1 system packaging direction | High | Define entry location, connector, strain relief, routing, and service access against the corrected/confirmed mechanical assembly. | PCB placement + harness + Fabrication | | Rev A PCB state | CONFIRMED FACT | PCB design is the current Rev A implementation stage. A `.kicad_pcb` has not yet been created and must now be designed. | Rev A.4.1 package scope and Phase-1 project state | High | Create and review the first Rev A PCB from the authoritative schematic. | PCB layout + Fabrication | | Authoritative KiCad source | CONFIRMED FACT | Rev A.4.1 native project source is checked in under [`hardware/kicad/JumpJet_RevA/`](../hardware/kicad/JumpJet_RevA/README.md): root schematic, four child sheets, project symbol/footprint libraries, library tables, minimal project file, preliminary BOM, and archive provenance README. | `JumpJet_Controller_RevA4_1_J3_JST_XH.zip` intake and checked-in source | High for file provenance | Open in native KiCad and run ERC when `kicad-cli` or desktop KiCad is available. | PCB layout + Fabrication | | KiCad source schema/validation | ASSUMPTION / PROVISIONAL | Root schematic declares schema `20211014`/generator `kiutils`; child sheets declare `20260306`/custom generator; footprint files declare `20240108`. Hierarchical filenames and project-local library paths resolve by static inspection, but native application open/ERC has not been run in this environment. | File headers, root-sheet references, and library tables | High for observed metadata; medium for openability | Open/save only after review, verify no unintended migration diff, resolve all libraries, then run native ERC. | PCB layout + Fabrication | @@ -183,6 +190,9 @@ identify a valid production cutoff temperature or mounting location. Fabrication remains blocked until all of the following are closed or deliberately bounded by reviewed production-intent provisions: +- reconcile the supplied 41 × 41 × 105 mm heater/fan envelope with the STEP void, because it does not fit in any principal-axis orientation before clearance +- map the STEP neutral coordinate frame to printer rear/left/up and side-panel service access +- establish the heater inlet, outlet, wiring, attachment, and removal datums before selecting a PCB placement zone - ESP32 provisional receiving-land depth/process geometry and 1:1 body/pad registration - complete pin numbering/label verification beyond the physically identified Pin 1 - underside exposed-contact mapping and carrier isolation review From 113339413acaa4224247558db822a3dd42cb3a07 Mon Sep 17 00:00:00 2001 From: Daniel Brown Date: Fri, 4 Sep 2026 11:45:08 -0400 Subject: [PATCH 07/20] docs: supersede incomplete void packing blocker --- docs/PHASE1_HARDWARE_REGISTER.md | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index dd2a9b7..fcfc738 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -166,12 +166,15 @@ identify a valid production cutoff temperature or mounting location. | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | |---|---|---|---|---|---|---| -| Available internal void model | MEASURED | The supplied AP242 STEP contains one closed solid named `Internal Space`, expressed in metres. In its neutral CAD frame it spans X = -16.700 to +45.928 mm, Y = 0 to 268.000 mm, and Z = 0 to 72.450 mm: an overall 62.628 × 268.000 × 72.450 mm bounding box. The solid is a constant seven-edge X-Z profile extruded along Y, with approximately 2,728.653 mm² section area and 731,279 mm³ (0.731 L) volume. These are available-void measurements, not enclosure-wall or mounting-boss geometry. | `Part Studio 1 - Internal Space.step`, Onshape export dated 2026-09-04, SHA-256 `608b08534cdaa03be100230e1626da68c53977416f97d7f18e626874d7fa79fc`; direct STEP entity/coordinate analysis | High for STEP geometry and units | Establish how the neutral CAD axes map to printer rear/left/up and side-panel access; correlate the void with physical walls, openings, fasteners, and adjacent printer hardware. | PCB envelope + mounting + Fabrication | +| Preferred enclosure-space reference | MEASURED | `Void directly from Prusa file.step` is the preferred current enclosure-space reference. Its AP242 solid is expressed in metres and behaves as a constant X-Z section extruded 268.000 mm along neutral-CAD Y. Parsed gross coordinate extents are approximately X = 192.950 mm, Y = 268.000 mm, and Z = 185.311 mm. These gross extents establish substantially more installation volume; they are not usable PCB dimensions and do not encode the local Jetpack placement. | `Void directly from Prusa file.step`, Onshape export dated 2026-09-04, SHA-256 `641c9b8e20736b3045403c1793836d2242f225e9beb8f6a878e22a60466472cd`; direct STEP entity, unit, and coordinate analysis | High for source geometry, units, and gross extents | Recover the rigid transform between this void and the installed Jetpack mount, then correlate printer directions, walls, service opening, and adjacent hardware. | Heater placement + PCB envelope + mounting + Edge.Cuts + Fabrication | +| Superseded small-void packing study | MEASURED | `Part Studio 1 - Internal Space.step` contains one closed 62.628 × 268.000 × 72.450 mm void with an approximately 2,728.653 mm² constant section and 0.731 L volume. The earlier result that a 41 × 41 × 105 mm conservative heater box does not fit its principal-axis section remains valid for that file, but the file is now known to be a smaller/incomplete local void. The result is retained as historical evidence and is no longer a system-level incompatibility or fabrication blocker. | `Part Studio 1 - Internal Space.step`, Onshape export dated 2026-09-04, SHA-256 `608b08534cdaa03be100230e1626da68c53977416f97d7f18e626874d7fa79fc`; direct STEP analysis; superseded by the preferred Prusa-derived void | High for the historical geometry and packing result | Use the preferred Prusa-derived void for current system packaging; retain this result only for provenance unless the smaller region is later identified physically. | None | +| Jetpack fan-attachment geometry | MEASURED | `jetpack-fan-attachment.step` is one AP242 solid expressed in metres. In its local fan-face datum it contains a four-hole pattern at X/Y = ±16.000 mm (32.000 × 32.000 mm spacing), nominal 3.500 mm holes, and concentric approximately 38.000 mm fan-aperture geometry. The exported solid's vertex bounds are approximately 46.850 × 51.698 × 48.000 mm. These dimensions identify local attachment geometry only; they do not establish printer orientation, airflow sign, or installed position. | `jetpack-fan-attachment.step`, Onshape export dated 2026-05-14, SHA-256 `16e8a43a846a8cf6bce9095980827f721db8490bd00f365e97459a208e2edd00`; direct STEP entity and coordinate analysis | High for the local pattern and neutral-CAD geometry | Correlate the fan face to the physical fan/heater stack and recover its installed transform to the preferred enclosure-space reference. | Heater placement + PCB plane + mounting + Edge.Cuts + Fabrication | +| Mechanical-source alignment | TBD / BLOCKED | No common rigid transform is preserved between the preferred Prusa-derived void and the separately exported Jetpack fan attachment. Their AP242 files each contain a single neutral-coordinate solid and no assembly occurrence relationship. The native `core_one_assembly.f3d` archive is readable as a Fusion container and the available AP214 assembly STEP contains printer assembly occurrences, but neither contains the separately exported `Fan attachment` product or an identified matching datum that locates it. Applying scale, translation, rotation, or reflection between these sources would therefore be invented. | Direct inspection of both AP242 structures; `core_one_assembly.f3d`, SHA-256 `2655b839e5e401ee191be4d3fdd8d40e6bd16377da94f2afcaf9258c17f5e113`; available AP214 assembly STEP, SHA-256 `4ead8073806c86df0e2309e905f84664715b2a09b9c384839aa33a8a8591aa08` | High confidence that the supplied exports do not close alignment | Provide one assembly/export containing both the Jetpack attachment and Prusa reference in preserved installed coordinates; alternatively provide three non-collinear corresponding datum points (or an origin plus two directed axes) measured/identified on both models. Also identify which fan-face normal points toward the cold-air side. | Heater placement + PCB plane/envelope + service/antenna directions + local constraint model + Edge.Cuts + Fabrication | | Heater/fan occupied envelope | MEASURED | The current heater plus fan assembly occupies a 41 × 41 × 105 mm rectangular envelope inside the same available void. The production power supply remains outside the printer. | Direct assembly-envelope measurement supplied for the Phase-1 placement study | High for the supplied envelope; attachment datums are not encoded | Record the hot-air outlet datum, connector and wire exits, attachment features, and required operational/service clearances. | Heater placement + PCB envelope + mounting + Fabrication | | Heater intake face | CONFIRMED FACT | The 41 × 41 mm face selected for possible PCB mounting is the heater/fan assembly's cold-air intake side. Incidental intake-air cooling must not be a safety dependency. | Physical assembly identification supplied for the Phase-1 placement study | High for face function | Record fan aperture and mounting-hole geometry, airflow direction in printer coordinates, connector/wire exits, and required unobstructed inlet/service volumes. | Heater placement + PCB envelope + mounting + Fabrication | -| PCB-over-intake architecture | ASSUMPTION / PROVISIONAL | Leading architecture is heater/fan → cold-air intake face → independent support/standoffs → controller PCB. The PCB may overhang the 41 × 41 mm fan body if later geometry and airflow testing support it; no standoff height, hole pattern, board outline, or service envelope is frozen. | Phase-1 mechanical steering; favorable cold-side topology | Medium concept confidence; current STEP packing fails | Resolve the heater-envelope/void mismatch first, then measure fan holes/aperture, bracket load path, standoff stack, PCB/component heights, inlet flow area, connector mating/fuse-pull/USB zones, and side-panel removal path. | PCB envelope + mounting + Fabrication | -| Heater fit in STEP principal frame | TBD / BLOCKED | A 105 mm heater axis parallel to the STEP's 268 mm extrusion requires its 41 × 41 mm section to fit wholly inside the X-Z profile. It does not: the maximum axis-aligned square supported by the exact profile is approximately 37.825 mm, before any airflow, wall, vibration, or assembly clearance. Orienting 105 mm along X or Z is also excluded by the 62.628 mm and 72.450 mm overall bounds. Arbitrary compound-angle placement is not established and would not justify PCB mechanics without a full collision/service study. | Exact STEP profile versus supplied 41 × 41 × 105 mm occupied envelope | High for principal-axis non-fit | Confirm the STEP represents the intended complete available volume and confirm the heater envelope/datum. If both are correct, revise the heater/fan packaging or provide a larger/corrected void model before selecting a PCB zone. | Heater placement + PCB envelope + Edge.Cuts + Fabrication | -| PCB envelope after heater occupancy | TBD / BLOCKED | No defensible residual PCB envelope exists yet because the required heater envelope has no verified placement in the supplied void. Raw volume subtraction would leave about 0.555 L, but volume alone does not prove packability, airflow, access, connector clearance, or a mounting plane. Do not derive Edge.Cuts from the void bounding box. | Coupled heater/PCB packing audit | High confidence that placement is blocked | Resolve heater fit and orientation first; then capture mounting faces, clearances, inlet/outlet direction, service path, cable corridors, antenna direction, and connector tool access. | PCB envelope + Edge.Cuts + Fabrication | +| PCB-over-intake architecture | ASSUMPTION / PROVISIONAL | Leading architecture is heater/fan → cold-air intake face → independent support/standoffs or integrated carrier → controller PCB. The PCB may overhang the fan body if aligned local geometry and airflow testing support it; no standoff height, use of shared fan screws, board outline, or service envelope is frozen. Intake airflow must not be credited as safety-critical PCB cooling. | Phase-1 mechanical steering; favorable cold-side topology; preferred enclosure-space reference removes the former system-volume objection | Medium concept confidence; installed alignment remains absent | Recover the installed transform, then establish bracket load path, standoff stack, PCB/component heights, inlet flow area, connector mating/fuse-pull/USB zones, cable corridors, and side-panel removal path. | PCB envelope + mounting + Fabrication | +| Heater placement in preferred void | TBD / BLOCKED | The preferred void removes the prior evidence of a fundamental heater/enclosure incompatibility, but no exact placement or collision clearance is established. The conservative 41 × 41 × 105 mm heater/fan envelope is a sanity envelope, not an installed transform or a substitute for actual heater geometry. | Preferred void gross extents; supplied heater/fan envelope; lack of a common Jetpack-to-void datum | High confidence that system volume is no longer the blocker; high confidence that local placement remains unproved | Supply the installed transform/common datums and identify actual heater body, fan, protrusion, cable-exit, mounting-penetration, intake, and outlet geometry. | PCB plane/envelope + mounting + Edge.Cuts + Fabrication | +| PCB plane and local envelope | TBD / BLOCKED | No defensible PCB plane, maximum rectangle, overhang, standoff range, component-height limit, shell clearance, service edge, USB/fuse/connector access zone, antenna-open direction, or airflow no-go region can be derived from gross void bounds. The Jetpack fan-face pattern supplies a useful local datum but is not located within the printer void. | Mechanical-source alignment audit | High confidence that local mechanics remain open | Align the sources and build the local constraint map; then validate the leading carrier strategies and a 1:1 physical mockup before freezing mechanics. | PCB envelope + Edge.Cuts + mounting + Fabrication | | Production PSU location | DESIGN DECISION | Keep the production power supply outside the printer; only the protected incoming 24 V harness enters the Jump Jet installation volume. | Phase-1 system packaging direction | High | Define entry location, connector, strain relief, routing, and service access against the corrected/confirmed mechanical assembly. | PCB placement + harness + Fabrication | | Rev A PCB state | CONFIRMED FACT | PCB design is the current Rev A implementation stage. A `.kicad_pcb` has not yet been created and must now be designed. | Rev A.4.1 package scope and Phase-1 project state | High | Create and review the first Rev A PCB from the authoritative schematic. | PCB layout + Fabrication | | Authoritative KiCad source | CONFIRMED FACT | Rev A.4.1 native project source is checked in under [`hardware/kicad/JumpJet_RevA/`](../hardware/kicad/JumpJet_RevA/README.md): root schematic, four child sheets, project symbol/footprint libraries, library tables, minimal project file, preliminary BOM, and archive provenance README. | `JumpJet_Controller_RevA4_1_J3_JST_XH.zip` intake and checked-in source | High for file provenance | Open in native KiCad and run ERC when `kicad-cli` or desktop KiCad is available. | PCB layout + Fabrication | @@ -190,9 +193,10 @@ identify a valid production cutoff temperature or mounting location. Fabrication remains blocked until all of the following are closed or deliberately bounded by reviewed production-intent provisions: -- reconcile the supplied 41 × 41 × 105 mm heater/fan envelope with the STEP void, because it does not fit in any principal-axis orientation before clearance -- map the STEP neutral coordinate frame to printer rear/left/up and side-panel service access -- establish the heater inlet, outlet, wiring, attachment, and removal datums before selecting a PCB placement zone +- recover the installed rigid transform between the preferred Prusa-derived void and the Jetpack fan-attachment datum; the supplied neutral STEP exports do not preserve one +- map the aligned geometry to printer rear/left/up and the removable side/service-panel direction +- establish the heater inlet, outlet, wiring, attachment, removal, fan-face-normal, and clearance datums before selecting a PCB placement zone +- derive the local PCB plane, practical rectangular envelope, mounting strategy, airflow no-go area, service zones, and antenna-open direction; do not use gross void dimensions as board dimensions - ESP32 provisional receiving-land depth/process geometry and 1:1 body/pad registration - complete pin numbering/label verification beyond the physically identified Pin 1 - underside exposed-contact mapping and carrier isolation review From 8c1ef9ba3d9d8652bf465c0cbd47d45ce7ab23fa Mon Sep 17 00:00:00 2001 From: Daniel Brown <30573097+danielbrownjr@users.noreply.github.com> Date: Sun, 6 Sep 2026 08:47:11 -0700 Subject: [PATCH 08/20] hardware: replace fan block with four-wire interface --- .../kicad/JumpJet_RevA/BOM_PRELIMINARY.csv | 21 +- .../JumpJet_RevA/JumpJet_Controller.kicad_sch | 2 +- .../JumpJet_Power_Outputs.kicad_sch | 260 ++++++++++++++---- 3 files changed, 220 insertions(+), 63 deletions(-) diff --git a/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv index b216459..4fe4b53 100644 --- a/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv +++ b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv @@ -3,15 +3,20 @@ J1,1,24 V input,">=20 A keyed terminal, 14 AWG capable",BASE,Footprint TBD F1,1,Main fuse,15 A provisional,BASE,Verify coordination D1,1,Rail TVS,SMBJ30A provisional,BASE,Verify clamp vs MOSFET/PSU MOD1,1,Logic power,"24 V to 5 V, input transient rating >=60 V",BASE,Exact module TBD -F2,1,Heater branch fuse,TBD after cold-start measurement,BASE,Open -TF1,1,One-shot thermal fuse,"75 C, 15 A",BASE,BOM supplied -TS1,1,Resettable thermal switch,"NC, 75 C, 16 A",BASE,BOM supplied -J2,1,Heater output terminal,"Phoenix Contact MKDS 1,5/2 (1715022), 5.00 mm pitch, 17.5 A nominal",BASE,"Selected for 8.3 A heater; external splice/lead extension documented separately" -J3,1,Integrated blower,"24 V, ~0.36 A; JST-XH 2-pin",BASE,"Footprint locked to JST_XH_B2B-XH-A; mating housing XHP-2; polarity to verify before harness build" -Q1-Q2,2,Low-side switching,60 V logic-level N-MOSFET,BASE,Exact part/thermal design TBD +F2,1,Heater branch fuse,Littelfuse 0287015.U 15 A ATOF candidate,BASE,"Strong candidate; cold-start characterization complete; PSU/fuse coordination and holder thermal validation open" +TF1,1,One-shot thermal fuse,"Historical schematic placeholder: 75 C / 15 A",BASE,"Production part trip temperature mounting and thermal coupling TBD" +TS1,1,Resettable thermal switch,"Historical schematic placeholder: NC 75 C / 16 A",BASE,"Production part trip temperature mounting and thermal coupling TBD" +J2,1,Heater output terminal,"Phoenix Contact MKDS 1,5/2 (1715022), 5.00 mm pitch, 17.5 A nominal",BASE,"Strong candidate only; footprint ferrule torque service access and terminal temperature remain open" +J3,1,Four-wire replacement fan,"Pin 1 FAN_24V; pin 2 GND; pin 3 FAN_TACH; pin 4 FAN_PWM",BASE,"4-pin JST-XH strong candidate; vertical footprint provisional; mating direction and production fan remain open" +Q1,1,Heater low-side switch,TI CSD18540Q5B candidate,BASE,"Strong candidate only; package mapping thermal design hot RDS(on) gate waveform and switching loss remain open" +Q2,1,Fan PWM open-drain interface,2N7002-class logic N-MOSFET,BASE,"Provisional control transistor; former 60 V fan-power-switch role is obsolete; exact MPN TBD" +D2,0,Legacy fan flyback diode,Obsolete with continuous-power four-wire fan architecture,DNP,Removed from Phase 1 schematic +R3/R4,2,Fan PWM gate network,"1 k series / 100 k direct pulldown",BASE,"Provisional values; old fan-power MOSFET gate-network role superseded" +R10/R11/C3,3,3.3 V tach interface,"1 k series / 10 k pull-up / optional filter capacitor DNP",BASE,"Provisional values; exact tach output and filter/protection requirements pending" +TP9/TP10,2,Fan interface test points,TP_FAN_TACH / TP_FAN_PWM,BASE,Phase 1 bring-up provisions Q3/F4/J4/D3,1 set,AUX1 PWM output,24 V optional,DNP,User expansion -U1,1,Gate buffer,74AHCT125,BASE,Review drive/current -U2,1,Controller module,"ESP32-S3FH4R2 SuperMini, 2x9 edge pads",BASE,Pin order and 15.24 mm row spacing confirmed +U1,1,Gate buffer,74AHCT125,BASE,"Existing Rev A.4.1 implementation; heater OE/default-disable and power-domain correction remains open" +U2,1,Controller module,"ESP32-S3 Super Mini, 2x9 edge pads",BASE,"Identity confirmed; pad numbering receiving-land geometry registration underside isolation antenna keepout USB access and flash size remain open" J6-J8,3,Thermistors,"10 k NTC, 1 m lead",BASE,Beta/coefficients TBD J9 + divider,1,Fourth thermistor,10 k NTC,DNP,Expansion J10,1,Qwiic,JST-SH 1.0 mm 4-pin,BASE,Supported expansion diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch index ed32501..68a81eb 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch @@ -1289,7 +1289,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 07e6424e-d1ec-4ea7-86fb-cfb57cd3580e) ) - (global_label "FAN_PWM" (shape bidirectional) (at 96.52 76.2 0) (fields_autoplaced) + (global_label "LEGACY_FAN_PWM_NC" (shape bidirectional) (at 96.52 76.2 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 09e2faff-9cca-459f-94ac-bcbcda17b21d) ) diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch index be18eb8..53ab3ee 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch @@ -1383,7 +1383,7 @@ (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid 7f86481b-c093-4c97-83e9-606d5d071579) ) - (text "All outputs default OFF via pulldowns. Unused fourth buffer tied low on PCB." + (text "Heater driver default-disable and power-domain sequencing remain required corrections." (at 150.00 137.00 0) (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid b59cd9c9-fcc4-462d-b06a-d4a2a3106217) @@ -1393,11 +1393,11 @@ (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid b608ab78-44cf-486a-b5dd-6ab3ef126e7c) ) - (text "HEATER + INTEGRATED BLOWER OUTPUTS" (at 152.62 22.0 0) + (text "HEATER + FOUR-WIRE FAN OUTPUTS" (at 152.62 22.0 0) (effects (font (size 1.80 1.80) (thickness 0.225)) (justify left bottom)) (uuid bcd2022d-b38f-417c-87e7-ca6ea3cb4589) ) - (text "AUX1 is optional/DNP; simultaneous-load capacity depends on measured heater and blower current." + (text "Fan: continuous fused 24 V + GND; separate open-drain PWM and 3.3 V tach interface." (at 150.00 143.00 0) (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid eab4d0bb-5495-40fc-aa49-ad112c75465b) @@ -1408,11 +1408,7 @@ (uuid efadd267-eef7-4648-9d7b-c0ed698f7488) ) - (label "FAN_SW" (at 283.21 64.77 90) - (effects (font (size 0.85 0.85)) (justify left bottom)) - (uuid 06f0e54e-f9a9-4146-84d9-2183151089c0) - ) - (label "FAN_SW" (at 264.16 55.88 0) + (label "GND" (at 264.16 55.88 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 0e4edc5b-8fb0-4c10-972d-4773d90023d8) ) @@ -1444,16 +1440,56 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 88505649-d9d1-41d2-ad8c-190f3c82bd51) ) - (label "+24V_BLOWER" (at 283.21 57.15 90) + (label "FAN_24V" (at 267.97 53.34 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 8f28c6e1-81d8-43cf-9997-62f5bf560bcd) ) + (label "FAN_TACH_WIRE" (at 267.97 58.42 0) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 6b56096b-9a75-4c0c-a91d-0b8e9adfe5cb) + ) + (label "FAN_PWM_WIRE" (at 267.97 60.96 0) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid b40cbb79-279b-4575-9997-ec73c77fcc9a) + ) + (label "FAN_TACH_WIRE" (at 260.35 96.52 0) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid f493e53b-3345-4ac1-b243-e7d19c103c55) + ) + (global_label "FAN_TACH" (shape bidirectional) (at 252.73 96.52 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid d7aa9887-c467-4e71-8431-037c51ae36ee) + ) + (global_label "+3V3" (shape bidirectional) (at 273.05 95.25 90) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid f29d4269-b75d-49cf-9f98-66fe65d14a85) + ) + (global_label "FAN_TACH" (shape bidirectional) (at 273.05 102.87 90) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 7369b6d6-8901-4562-8eec-c1b632b5bfcb) + ) + (global_label "FAN_TACH" (shape bidirectional) (at 286.0 95.25 90) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid a9509179-7f36-4c48-b194-7d393f81223f) + ) + (global_label "GND" (shape bidirectional) (at 286.0 102.87 90) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 32b75d47-d271-473f-987b-397f9b0282ec) + ) + (global_label "FAN_TACH" (shape bidirectional) (at 246.38 96.52 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 1720e976-f08a-45dd-81c6-511ac6af6b40) + ) + (global_label "FAN_PWM_WIRE" (shape bidirectional) (at 289.56 69.85 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 4404c555-d833-4ee5-a4bd-e973d0755e3c) + ) (label "AUX_DRV" (at 293.37 121.92 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid a29ced2d-77e7-45ce-becc-61fd71c1c2e2) ) - (label "FAN_DRV" (at 247.65 121.92 0) + (label "LEGACY_FAN_DRV_NC" (at 247.65 121.92 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid b9a7529c-ec91-4303-aa26-8fc9aebb2284) ) @@ -1461,7 +1497,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid bbc1be49-3a6e-4813-b66b-44427b122d61) ) - (label "FAN_DRV" (at 250.19 74.93 0) + (global_label "MCU_FAN_PWM" (shape bidirectional) (at 250.19 74.93 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid c1729675-b63c-4b7b-a912-334520804ab3) ) @@ -1504,7 +1540,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 200d535b-953f-47b0-854f-e7890102f67f) ) - (global_label "FAN_PWM" (shape bidirectional) (at 229.87 121.92 0) (fields_autoplaced) + (global_label "LEGACY_FAN_PWM_NC" (shape bidirectional) (at 229.87 121.92 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 22549e4c-3880-4528-bfc3-6cdb0c73d5bb) ) @@ -1541,7 +1577,7 @@ (uuid 648244b4-4dc2-48cd-987b-b42101659300) ) - (global_label "FAN_GATE" (shape bidirectional) (at 265.43 74.93 0) (fields_autoplaced) + (global_label "FAN_PWM_GATE" (shape bidirectional) (at 265.43 74.93 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 69290207-2394-4900-a9d7-b6b899608744) ) @@ -1569,7 +1605,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid b1b78cf5-2506-4bbe-b347-963ab23b8e07) ) - (global_label "FAN_GATE" (shape bidirectional) (at 265.43 80.01 90) (fields_autoplaced) + (global_label "FAN_PWM_GATE" (shape bidirectional) (at 265.43 80.01 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid b3ee94e0-a06f-4263-8772-11183f151559) ) @@ -1577,7 +1613,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid b64a6d57-ec89-4a97-af0d-02fb8fcdfcbd) ) - (global_label "FAN_PWM" (shape bidirectional) (at 228.6 125.73 90) (fields_autoplaced) + (global_label "LEGACY_FAN_PWM_NC" (shape bidirectional) (at 228.6 125.73 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid bdf55785-4015-4c92-b23f-b5c437a0cab5) ) @@ -1638,7 +1674,7 @@ (uuid 4bffbd2d-67bb-4650-8169-a35334e7271e) ) - (label "+24V_BLOWER" (at 267.97 53.34 0) + (label "FAN_24V" (at 267.97 53.34 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid c22771b5-5067-4b29-93a8-e08fc47828f7) ) @@ -1668,12 +1704,12 @@ (uuid 64e8b433-977a-4dc3-a4dd-c04b966826ce) ) - (label "+24V_BLOWER" (at 257.81 53.34 0) + (label "FAN_24V" (at 257.81 53.34 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid d0fc554f-62ac-468f-841f-8d06b37bed70) ) - (label "FAN_SW" (at 275.59 69.85 0) + (label "FAN_PWM_WIRE" (at 275.59 69.85 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 844e5b73-4e0d-4709-b869-d2bc6101d611) ) @@ -2168,16 +2204,16 @@ ) ) - (symbol (lib_id "Connector_Generic:Conn_01x02") (at 273.05 53.34 0) (unit 1) + (symbol (lib_id "Connector_Generic:Conn_01x04") (at 273.05 57.15 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-000068ae000f) (property "Reference" "J3" (at 273.27 47.51 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "24V BLOWER" (at 273.27 59.51 0) + (property "Value" "4-WIRE FAN: 24V/GND/TACH/PWM" (at 273.27 65.32 0) (effects (font (size 0.85 0.85))) ) - (property "Footprint" "Connector_JST:JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical" (at 273.27 53.51 0) + (property "Footprint" "Connector_JST:JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical" (at 273.27 57.32 0) (effects (font (size 0.85 0.85)) hide) ) (property "Datasheet" "" (at 273.27 53.51 0) @@ -2188,6 +2224,8 @@ ) (pin "1" (uuid a72c5e4d-a0e3-427e-ad27-1042492ecc60)) (pin "2" (uuid 244c5824-4ab8-49af-bd83-1fcc888db981)) + (pin "3" (uuid ef27693b-b36a-40f0-b2d1-ec77f080425e)) + (pin "4" (uuid f7b058fc-d827-4419-8e58-c653fc5bebf6)) (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" @@ -2197,45 +2235,16 @@ ) ) - (symbol (lib_id "Device:D") (at 283.21 60.96 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) - (uuid 00000000-0000-0000-0000-000068ae0010) - (property "Reference" "D2" (at 283.43 56.13 0) - (effects (font (size 0.85 0.85))) - ) - (property "Value" "FLYBACK TBD" (at 283.43 66.13 0) - (effects (font (size 0.85 0.85))) - ) - (property "Footprint" "Diode_SMD:D_SMA" (at 283.43 61.13 0) - (effects (font (size 0.85 0.85)) hide) - ) - (property "Datasheet" "" (at 283.43 61.13 0) - (effects (font (size 0.85 0.85)) hide) - ) - (property "Description" "" (at 283.43 61.13 0) - (effects (font (size 0.85 0.85)) hide) - ) - (pin "1" (uuid 4e0b2257-1e31-43be-ac14-0548d701b0af)) - (pin "2" (uuid 8aef38fc-5988-4704-9c59-3fe2725013e7)) - (instances - (project "JumpJet_Controller_RevA4" - (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" - (reference "D2") (unit 1) - ) - ) - ) - ) - (symbol (lib_id "Transistor_FET:Q_NMOS_GDS") (at 273.05 74.93 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-000068ae0011) (property "Reference" "Q2" (at 273.27 69.10 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "60V NFET TBD" (at 273.27 81.10 0) + (property "Value" "2N7002-CLASS PWM OD PROVISIONAL" (at 273.27 81.10 0) (effects (font (size 0.85 0.85))) ) - (property "Footprint" "Package_DirectFET:TBD" (at 273.27 75.10 0) + (property "Footprint" "Package_TO_SOT_SMD:SOT-23" (at 273.27 75.10 0) (effects (font (size 0.85 0.85)) hide) ) (property "Datasheet" "" (at 273.27 75.10 0) @@ -2262,7 +2271,7 @@ (property "Reference" "R3" (at 252.56 73.30 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "47R TBD" (at 260.96 76.90 0) + (property "Value" "1k PROVISIONAL" (at 260.96 76.90 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "" (at 256.76 75.10 0) @@ -2291,7 +2300,7 @@ (property "Reference" "R4" (at 265.65 79.99 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "100k" (at 265.65 87.99 0) + (property "Value" "100k GATE PULLDOWN" (at 265.65 87.99 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "" (at 265.65 83.99 0) @@ -2314,6 +2323,149 @@ ) ) + (symbol (lib_id "Device:R") (at 256.54 96.52 90) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 6ca9f5e8-2775-434a-a275-8f629388147d) + (property "Reference" "R10" (at 252.56 94.89 0) + (effects (font (size 0.85 0.85))) + ) + (property "Value" "1k TACH SERIES PROVISIONAL" (at 260.96 98.49 0) + (effects (font (size 0.85 0.85))) + ) + (property "Footprint" "Resistor_SMD:R_0603_1608Metric" (at 256.76 96.69 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Datasheet" "" (at 256.76 96.69 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Description" "" (at 256.76 96.69 0) + (effects (font (size 0.85 0.85)) hide) + ) + (pin "1" (uuid 57f6f181-5d84-4f89-a740-08e12313e8f5)) + (pin "2" (uuid 4964c07a-1aad-4b69-bc27-62ac4acaad36)) + (instances + (project "JumpJet_Controller_RevA4" + (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" + (reference "R10") (unit 1) + ) + ) + ) + ) + + (symbol (lib_id "Device:R") (at 273.05 99.06 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 5789223a-1130-461c-b785-5fb2f811594d) + (property "Reference" "R11" (at 273.27 95.23 0) + (effects (font (size 0.85 0.85))) + ) + (property "Value" "10k TACH PULLUP PROVISIONAL" (at 273.27 103.23 0) + (effects (font (size 0.85 0.85))) + ) + (property "Footprint" "Resistor_SMD:R_0603_1608Metric" (at 273.27 99.23 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Datasheet" "" (at 273.27 99.23 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Description" "" (at 273.27 99.23 0) + (effects (font (size 0.85 0.85)) hide) + ) + (pin "1" (uuid 144cd85f-9254-4a72-a7c6-51233d900b60)) + (pin "2" (uuid 82476193-7ea1-4d63-93be-d1658305cc08)) + (instances + (project "JumpJet_Controller_RevA4" + (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" + (reference "R11") (unit 1) + ) + ) + ) + ) + + (symbol (lib_id "Device:C") (at 286 99.06 0) (unit 1) + (in_bom yes) (on_board yes) (dnp yes) + (uuid 3ef8d1f4-a503-479a-b508-2546715a582a) + (property "Reference" "C3" (at 286.14 95.23 0) + (effects (font (size 0.85 0.85))) + ) + (property "Value" "TACH FILTER DNP/TBD" (at 286.14 103.23 0) + (effects (font (size 0.85 0.85))) + ) + (property "Footprint" "Capacitor_SMD:C_0603_1608Metric" (at 286.14 99.23 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Datasheet" "" (at 286.14 99.23 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Description" "" (at 286.14 99.23 0) + (effects (font (size 0.85 0.85)) hide) + ) + (pin "1" (uuid 955d9622-05d3-4bed-a25b-5329cd2608dc)) + (pin "2" (uuid 3d824b92-f1d4-4c04-aa74-23eec64740b4)) + (instances + (project "JumpJet_Controller_RevA4" + (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" + (reference "C3") (unit 1) + ) + ) + ) + ) + + (symbol (lib_id "Connector:TestPoint") (at 246.38 96.52 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid b91ab7ef-89b0-471c-a77b-81229336183f) + (property "Reference" "TP9" (at 242.28 93.07 0) + (effects (font (size 0.85 0.85))) + ) + (property "Value" "TP_FAN_TACH" (at 250.28 99.07 0) + (effects (font (size 0.85 0.85))) + ) + (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 246.28 96.07 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Datasheet" "" (at 246.28 96.07 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Description" "" (at 246.28 96.07 0) + (effects (font (size 0.85 0.85)) hide) + ) + (pin "1" (uuid f657c975-acb6-4bef-a24a-dfc37823fc00)) + (instances + (project "JumpJet_Controller_RevA4" + (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" + (reference "TP9") (unit 1) + ) + ) + ) + ) + + (symbol (lib_id "Connector:TestPoint") (at 289.56 69.85 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 982987fc-7c9c-45fb-8935-6f88d0f88565) + (property "Reference" "TP10" (at 285.46 66.40 0) + (effects (font (size 0.85 0.85))) + ) + (property "Value" "TP_FAN_PWM" (at 293.46 72.40 0) + (effects (font (size 0.85 0.85))) + ) + (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 289.46 69.40 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Datasheet" "" (at 289.46 69.40 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Description" "" (at 289.46 69.40 0) + (effects (font (size 0.85 0.85)) hide) + ) + (pin "1" (uuid 27106a98-9d48-44a2-9373-2a3dde9557fe)) + (instances + (project "JumpJet_Controller_RevA4" + (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" + (reference "TP10") (unit 1) + ) + ) + ) + ) + (symbol (lib_id "Device:Fuse") (at 303.53 53.34 90) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-000068ae0014) From 4bd0bfa34d7f281d0ca463a5ffffe075ee7a9c25 Mon Sep 17 00:00:00 2001 From: Daniel Brown <30573097+danielbrownjr@users.noreply.github.com> Date: Sun, 6 Sep 2026 08:47:48 -0700 Subject: [PATCH 09/20] docs: refresh Phase 1 fan and hardware contract --- README.md | 19 ++- ROADMAP.md | 7 +- TODO.md | 9 +- docs/HARDWARE_BASELINE.md | 26 ++- docs/PHASE1_HARDWARE_REGISTER.md | 24 ++- docs/PRODUCT_SAFETY_CONTRACT.md | 7 + .../9ga0424p3j001-characterization.md | 157 ++++++++++++++++++ hardware/kicad/JumpJet_RevA/README.md | 10 ++ 8 files changed, 232 insertions(+), 27 deletions(-) create mode 100644 docs/hardware/9ga0424p3j001-characterization.md diff --git a/README.md b/README.md index 052d262..73bc720 100644 --- a/README.md +++ b/README.md @@ -51,15 +51,18 @@ about 130 °C at the heater/PTC region, and about 74–75 °C at the chassis. De sizing remains the rated 24 V / 200 W / 8.33 A case. That test did **not** validate the complete Jump Jet Q1/F2/PCB/connector/wiring -path or installed operation. The Rev A.4.1 schematic is the current hardware -authority, and its [KiCad project source](hardware/kicad/JumpJet_RevA/README.md) -is checked into this repository. The Rev A PCB has not yet been created; PCB -implementation and validation are the current Phase-1 hardware work. The -checked-in schematic is not fabrication-ready and does not authorize heater -actuation. Detailed status and blockers are tracked in the +path or installed operation. Rev A.4.1 is the authoritative schematic baseline, +and its [KiCad project source](hardware/kicad/JumpJet_RevA/README.md) is checked +into this repository. The first Rev A PCB is Phase-1 work in progress; no +fabrication-approved PCB or outputs exist. Checked-in source does not authorize +heater or fan actuation. Detailed status and blockers are tracked in the [Phase 1 hardware register](docs/PHASE1_HARDWARE_REGISTER.md). GPIO, ADC, -thermistor, protection, and cooldown thresholds therefore remain TBD. The Sanyo -Denki 9GA0424P3J001 is only a prototype fan candidate, not BOM-final. +thermistor, protection, and cooldown thresholds therefore remain TBD. + +The replacement-fan direction is continuous fused 24 V and ground with separate +open-drain PWM and tach feedback. The Sanyo Denki 9GA0424P3J001 remains a +prototype candidate, not BOM-final; published facts and pending measurements are +tracked in its [characterization record](docs/hardware/9ga0424p3j001-characterization.md). ## Safety boundary diff --git a/ROADMAP.md b/ROADMAP.md index 6ced298..7db0456 100644 --- a/ROADMAP.md +++ b/ROADMAP.md @@ -25,7 +25,10 @@ no phase passes its gate without the listed evidence. - freeze the hardware contract and create/review the first Rev A PCB during Phase 1 - review the BOM, enclosure, mechanical interfaces, and airflow path - confirm the exact ESP32-S3 Super Mini revision, flash size, GPIO map, and boot-strap constraints -- identify heater, MOSFET, fans, thermistors, connectors, fuse, thermal cutoff, and switch +- identify heater, MOSFET, characterized four-wire fan channel, thermistors, + connectors, fuses, thermal cutoff, and switch +- characterize the prototype fan before freezing interface-derived firmware + values or RPM/stall/proof thresholds - calculate steady and worst-case current, connector loading, copper temperature rise, MOSFET dissipation, gate drive, voltage drop, ADC range, and protection margins - create a system hazard analysis covering single faults and foreseeable misuse @@ -41,7 +44,7 @@ protection question. Firmware constants may not be finalized before this gate. - implement board identity and force all heater control pins to their safe level at reset - implement calibrated ADC/thermistor conversion with open, short, rail, NaN, and implausible-reading classification -- implement both fan outputs and any available tachometer or airflow feedback +- implement the reviewed fan channel and tach-based fan proof - define the bounded fan-start/proof sequence and explicit proof-failure criteria from release-intent hardware evidence - implement the physical switch and define its electrical and software semantics - persist settings with bounds, schema versioning, corrupt-value fallback, and factory reset diff --git a/TODO.md b/TODO.md index 68fadbd..3872eb3 100644 --- a/TODO.md +++ b/TODO.md @@ -27,6 +27,9 @@ implementation starts, and keep only the summary checkbox here. - [ ] Validate the full Jump Jet Q1/F2/PCB/connector/wiring path at the 200 W / 8.33 A design basis - [x] Select the native four-wire fan architecture: continuous fused 24 V power, separate open-drain PWM, and separate tach feedback +- [x] Create the + [9GA0424P3J001 characterization record](docs/hardware/9ga0424p3j001-characterization.md) +- [ ] Characterize the physical 9GA0424P3J001 specimen on arrival - [ ] Characterize the 9GA0424P3J001 prototype and finalize candidate-specific pinout, current, connector, PWM/tach electrical details, RPM behavior, and stall thresholds; it remains prototype-only @@ -54,6 +57,8 @@ implementation starts, and keep only the summary checkbox here. - [ ] Select TF1/TS1 parts and their mounting/thermal-coupling architecture - [ ] Select and verify J1, F1, and MOD1 parts and footprints - [ ] Characterize the production PSU current limit and complete fuse coordination +- [ ] Close the aligned local mechanical constraint map before creating + fabrication-intent `Edge.Cuts` ## Firmware — immediate @@ -96,7 +101,7 @@ implementation starts, and keep only the summary checkbox here. - [ ] Implement `jj_board` with safe-at-reset GPIO initialization - [ ] Implement ADC sampling, calibration, filtering, and explicit sensor status -- [ ] Implement two fan channels and available fan/airflow proof +- [ ] Implement the characterized fan channel and available fan/airflow proof - [ ] Define the bounded fan spin-up/proof timeout and the evidence that changes proof from pending to proven or failed - [ ] Implement physical-switch handling and debouncing - [ ] Implement bounded settings persistence with corrupt-NVS recovery @@ -112,7 +117,7 @@ implementation starts, and keep only the summary checkbox here. - [ ] Finalize Jump Jet API v2 state and mutation schemas - [ ] Add chamber, outlet, and case temperature telemetry with sensor status -- [ ] Add target, heater duty, both fan states, mode, and commissioning state +- [ ] Add target, heater duty, fan command/proof state, mode, and commissioning state - [ ] Add PrusaLink connection, printer state, bed temperature/target, and sample age - [ ] Define optional Klipper/Moonraker integration for read-only printer state and bed-target telemetry, with the same stale-data fail-cold semantics as PrusaLink - [ ] Add visible interlocks, latched fault reason, and safe recovery guidance diff --git a/docs/HARDWARE_BASELINE.md b/docs/HARDWARE_BASELINE.md index 0c4a01c..67d44a5 100644 --- a/docs/HARDWARE_BASELINE.md +++ b/docs/HARDWARE_BASELINE.md @@ -2,9 +2,8 @@ Rev A.4.1 is the current authoritative schematic baseline. Its [KiCad project source](../hardware/kicad/JumpJet_RevA/README.md) is checked into -the repository. The source is intentionally schematic-only: the first Rev A -`.kicad_pcb` has not yet been created and remains active Phase-1 implementation -work. +the repository. The checked-in source set currently contains no `.kicad_pcb`; +creating the first Rev A PCB remains active Phase-1 implementation work. The detailed living source of truth for measurements, component candidates, design decisions, provisional values, blockers, and validation status is the @@ -22,6 +21,11 @@ or authorize heater actuation. 74–75 °C. - Full results: [CZ4060 characterization](hardware/cz4060-characterization.md). - The Sanyo Denki 9GA0424P3J001 is a prototype fan candidate, not BOM-final. +- The Phase-1 replacement-fan contract is continuous fused 24 V and ground with + separate open-drain PWM and tach. The original Rev A.4.1 low-side switched + two-wire block is retained as baseline evidence, not production intent. +- Published prototype facts and pending measurements are tracked in the + [9GA0424P3J001 characterization record](hardware/9ga0424p3j001-characterization.md). ## Not confirmed @@ -30,9 +34,19 @@ module implementation, and the complete power path have not been validated together. The upstream Jetpack pin assignments are historical facts, not Jump Jet assignments. -No GPIO, ADC, divider, thermistor conversion, fan/PWM method, protection threshold, -thermal trip, cooldown criterion, or recovery threshold may be finalized without -the corresponding source files and measured evidence. +No GPIO, ADC, divider, thermistor conversion, protection threshold, thermal trip, +cooldown criterion, or recovery threshold may be finalized without corresponding +source files and measured evidence. Fan interface values, production fan, +tach electrical behavior, pulses/revolution, RPM versus duty, minimum reliable +command, startup behavior, RPM/stall thresholds, and installed airflow/thermal +performance remain unresolved. A model-specific 25 kHz candidate test point is +not universal production policy. + +The newer Prusa-derived void is the preferred enclosure-space reference; the +earlier smaller-void system-level incompatibility conclusion is superseded. PCB +over the cold-air intake remains preferred and mechanically plausible, but the +installed transform and aligned local constraint map are unresolved, so +fabrication-intent `Edge.Cuts` remain blocked. ## Firmware consequence diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index fcfc738..329b0d6 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -1,6 +1,6 @@ # Phase 1 hardware source-of-truth register -Last updated: 2026-09-04 +Last updated: 2026-09-06 This is the living engineering register for JumpJet Rev A Phase-1 hardware implementation. It records what is known, how it is known, what remains @@ -139,12 +139,18 @@ temperatures. | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | |---|---|---|---|---|---|---| | Original integrated fan | CONFIRMED FACT | YD4020HBL, 24 V, 0.13 A, two-wire, no native PWM, and no tach. Its two-wire control architecture has been superseded by the four-wire PWM/tach direction. | Physical/product identification from CZ4060 assembly review | Medium-high | Confirm nameplate and electrical behavior if retained for comparative testing only. | None | -| Rev A.4.1 two-wire fan block | CONFIRMED FACT | The authoritative schematic still contains F3, J3, D2, Q2, R3, and R4 as a fused two-wire low-side-switched fan block. It is obsolete for the selected native four-wire direction and has not yet been replaced. | [Checked-in Rev A.4.1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) | High | Replace with continuous fused 24 V and ground, separate open-drain PWM, and 3.3 V-safe tach provisions after candidate pinout/electrical review. | PCB layout + BOM freeze + Fabrication | -| Replacement fan prototype | PROTOTYPE CANDIDATE | Sanyo Denki 9GA0424P3J001; ordered for characterization, ETA 2026-09-15. Not BOM-final. | Prototype purchase record | High for order state; unvalidated for application | Complete electrical, airflow, pressure, acoustic, thermal, stall, and installed-system characterization. | BOM freeze + Firmware constants | -| Four-wire fan architecture | DESIGN DECISION | Continuous fused 24 V fan power, separate PWM control, and separate tach/RPM feedback. Do not low-side PWM the fan's 24 V supply when using native four-wire control. | Phase-1 fan architecture decision | High | Verify candidate interface requirements and qualify final fan/control parts. | PCB layout + BOM freeze + Fabrication | -| Fan PWM interface | ASSUMPTION / PROVISIONAL | Provide a fan-compatible open-drain interface; exact circuit and component values remain pending datasheet and bench verification. | Common four-wire architecture and Phase-1 direction; candidate-specific evidence incomplete | Medium | Verify pinout, PWM voltage/current/frequency requirements, pull-up behavior, open/high-Z behavior, and 0% behavior. | PCB layout + BOM freeze + Firmware constants + Fabrication | -| Fan tach interface | TBD / BLOCKED | Tach output type, pull-up rail/value, pulses per revolution, filtering, protection, and stall semantics are not established. | Prototype not yet characterized | High confidence that evidence is missing | Characterize output electrically and across startup, minimum speed, normal operation, and locked rotor. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Rev A.4.1 two-wire fan block | CONFIRMED FACT | The Rev A.4.1 baseline originally used F3/J3/D2/Q2/R3/R4 as a fused two-wire low-side-switched fan-power block. Phase-1 source removes D2, repurposes Q2/R3/R4 for the low-current PWM interface, and replaces J3 with the reviewed provisional four-wire interface. The old switched-power architecture remains baseline evidence only and is obsolete for production. | [Phase-1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) and checked-in Rev A.4.1 provenance | High | Run native KiCad open/ERC and review the provisional interface against the delivered fan and final connector. | PCB layout + BOM freeze + Fabrication | +| Replacement fan prototype | PROTOTYPE CANDIDATE | Sanyo Denki 9GA0424P3J001; ordered for characterization, ETA 2026-09-15. Not BOM-final. | Prototype purchase record and [characterization record](hardware/9ga0424p3j001-characterization.md) | High for order state; unvalidated for application | Complete electrical, airflow, pressure, acoustic, thermal, stall, and installed-system characterization. | BOM freeze + Firmware constants | +| Published prototype electrical data | CONFIRMED FACT | Model-specific manufacturer data states 24 V rated, 21.6–26.4 V operating range, 0.27 A, 6.48 W, pulse sensor, and PWM control. These facts apply only to 9GA0424P3J001. | [Manufacturer product page](https://products.sanyodenki.com/en/sanace/dc/dc-fan/9GA0424P3J001/) summarized in the [characterization record](hardware/9ga0424p3j001-characterization.md) | High | Verify delivered-specimen identity and behavior; do not generalize to a production substitute. | BOM freeze + Firmware constants | +| Prototype lead convention | ASSUMPTION / PROVISIONAL | Manufacturer installation material gives the general San Ace convention of red positive, black/blue ground, yellow sensor, and brown PWM. Treat the ordered model provisionally as four AWG26 leads with red +24 V, black GND, yellow tach, and brown PWM until the delivered specimen or model drawing verifies gauge and functions. | San Ace manual `M0011876C`; Sara 30 handoff; [characterization record](hardware/9ga0424p3j001-characterization.md) | Medium | Inspect the delivered label/leads and verify electrically before applying power. | BOM freeze + Fabrication | +| Four-wire fan architecture | DESIGN DECISION | `+24V_PROT -> F3 -> FAN_24V -> J3 pin 1`, continuous GND on pin 2, separate tach on pin 3, and separate open-drain PWM on pin 4. Do not low-side PWM fan supply. F3 remains dedicated branch protection with rating TBD. | Phase-1 fan architecture decision and [Phase-1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) | High for topology | Qualify branch protection, final connector/fan, interface values, and installed behavior. | PCB layout + BOM freeze + Fabrication | +| J3 connector | STRONG CANDIDATE | Four-position JST-XH, logical pinout 1 FAN_24V, 2 GND, 3 FAN_TACH, 4 FAN_PWM. The schematic uses the vertical B4B-XH-A footprint provisionally; vertical versus right-angle mating direction is not frozen. Not BOM-final. | Phase-1 schematic implementation | Medium | Verify final fan termination, mating housing/contact current, polarity, keying, harness strain relief, installed orientation, and service clearance. | PCB layout + BOM freeze + Fabrication | +| Fan PWM interface | DESIGN DECISION | Use an open-drain N-MOSF stage with a direct gate pulldown. MCU unpowered/reset leaves the transistor off and the fan control lead open. Do not add an external PWM pull-up without model-specific justification. `MCU_FAN_PWM` remains unassigned to a controller pin. `TP_FAN_PWM` is provided. | Manufacturer PWM technical material and [Phase-1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) | High for topology; behavior not yet model-qualified | Verify model-specific control levels/frequency, high-Z and 0% behavior, startup behavior, and failure polarity on the delivered specimen. | BOM freeze + Firmware constants + Fabrication | +| Fan PWM components | ASSUMPTION / PROVISIONAL | Q2 is repurposed as a 2N7002-class SOT-23 control transistor; R3 is a provisional 1 kΩ gate series resistor and R4 a 100 kΩ direct gate pulldown. Exact MPN and values are not BOM-final. | Phase-1 schematic implementation | Medium | Select the transistor and values from control-input limits, leakage, waveform, EMI, and temperature validation. | PCB layout + BOM freeze + Fabrication | +| Prototype PWM behavior | ASSUMPTION / PROVISIONAL | Test 25 kHz as a candidate point. Open-control/full-speed behavior and 0%-command/stop behavior are expected but not frozen: available manufacturer technical material says frequency and response differ by model. | Sara 30 handoff; manufacturer PWM technical material; [characterization record](hardware/9ga0424p3j001-characterization.md) | Medium-low until model-specific evidence or bench data exists | Obtain the model drawing/specification or verify high-Z, 0%, and frequency behavior on the delivered specimen. | BOM freeze + Firmware constants + Fabrication | +| Fan tach interface | ASSUMPTION / PROVISIONAL | J3 tach feeds a provisional 1 kΩ series resistor, 10 kΩ pull-up to 3.3 V, DNP filter capacitor provision, generic `FAN_TACH` controller-side net, and `TP_FAN_TACH`. Do not pull tach to 5 V or 24 V. The open-collector interpretation remains provisional. | Phase-1 schematic implementation and general San Ace pulse-sensor material | Medium | Verify exact output circuit, voltage/current limits, pull-up, protection/filter need, pulses/revolution, waveform, and stall semantics. | PCB layout + BOM freeze + Firmware constants + Fabrication | | Fan performance envelope | TBD / BLOCKED | Startup/steady current, minimum reliable PWM/speed, RPM versus duty, CZ4060 airflow/static pressure, locked-rotor behavior, stall-detection latency, hub temperature, installed chamber margin, cooldown versus RPM, and minimum safe airflow/RPM remain unknown. | Prototype characterization pending | High confidence that evidence is missing | Complete bench and installed-system characterization. Do not freeze RPM thresholds beforehand. | BOM freeze + Firmware constants | +| Fan branch fuse | TBD / BLOCKED | F3 remains dedicated protection for the continuous 24 V fan branch; no production rating or footprint is selected. | Phase-1 schematic architecture | High confidence selection is open | Measure startup/locked-rotor behavior and coordinate fuse rating/time-current behavior with wiring, connector, fan, and production PSU. | PCB layout + BOM freeze + Fabrication | The first PCB may include configurable interface provisions, but fabrication is acceptable only if the unresolved interface is deliberately bounded and does not @@ -200,15 +206,15 @@ bounded by reviewed production-intent provisions: - ESP32 provisional receiving-land depth/process geometry and 1:1 body/pad registration - complete pin numbering/label verification beyond the physically identified Pin 1 - underside exposed-contact mapping and carrier isolation review -- antenna identity, enforced exact keepout, and installed RSSI/range validation +- antenna identity and conservative pre-fabrication keepout; installed RSSI/range qualification is post-prototype and pre-release - USB connector, plug, cable-head, and service-access envelope -- reconciled locating-hole coordinates and physical fit of the optional header +- optional locating holes must be physically fit-verified or deliberately omitted before footprint freeze - external 5 V / USB-C VBUS topology - USB/onboard mixed-source and backfeed testing - hardware-default-OFF gate-driver schematic correction - complete regulator load inventory and installed-temperature thermal analysis - Q1 multipad/footprint and F2 holder-footprint verification -- four-wire fan schematic/interface implementation and candidate electrical verification +- four-wire fan connector/interface footprint and candidate electrical verification; schematic provisions are implemented but not natively ERC-validated - TF1/TS1 part, mounting, and thermal-coupling implementation - J1, F1, and MOD1 part and footprint selections - PCB envelope, mounting-hole coordinates, connector-facing edges, and USB datum diff --git a/docs/PRODUCT_SAFETY_CONTRACT.md b/docs/PRODUCT_SAFETY_CONTRACT.md index b6ed402..ba3309b 100644 --- a/docs/PRODUCT_SAFETY_CONTRACT.md +++ b/docs/PRODUCT_SAFETY_CONTRACT.md @@ -100,3 +100,10 @@ safety-critical hardware are validated. Final GPIO, ADC, thermistor conversion, protection thresholds, cooldown criteria, and recovery thresholds must not be invented. Sanyo Denki 9GA0424P3J001 is a prototype fan candidate only and is not BOM-final. + +The intended replacement-fan architecture is continuous fused 24 V plus ground, +separate open-drain PWM, and tach feedback. The Rev A.4.1 low-side switched fan- +power block is obsolete for production. No production pulses/revolution, +minimum duty, RPM/stall threshold, or proof timeout exists before +characterization; a candidate-specific 25 kHz test point does not freeze final +fan policy. Physical fan proof remains mandatory before heater actuation. diff --git a/docs/hardware/9ga0424p3j001-characterization.md b/docs/hardware/9ga0424p3j001-characterization.md new file mode 100644 index 0000000..348861a --- /dev/null +++ b/docs/hardware/9ga0424p3j001-characterization.md @@ -0,0 +1,157 @@ +# Sanyo Denki 9GA0424P3J001 characterization + +> **PROTOTYPE ONLY / NOT PRODUCTION-FINAL.** This record does not select the +> production fan, freeze firmware constants, or authorize fan/heater actuation. + +## 1. Scope and status + +This is the evidence record and bench plan for the ordered Sanyo Denki +`9GA0424P3J001` four-wire fan. Published facts apply to this model only. All +measurement fields remain TBD until the physical specimen arrives and is tested. + +## 2. Specimen identity and provenance + +- Model ordered: `9GA0424P3J001` +- Status: prototype candidate, not BOM-final +- Expected arrival: 2026-09-15 +- Received specimen label, lot/date code, supplier, and traceability: TBD +- Photograph and lead/connector identification: TBD + +Manufacturer sources: + +- [9GA0424P3J001 product page](https://products.sanyodenki.com/en/sanace/dc/dc-fan/9GA0424P3J001/) +- [San Ace PWM technical material](https://products.sanyodenki.com/info/sanace/en/technical_material/pwm.html) +- [San Ace DC sensor technical material](https://products.sanyodenki.com/info/sanace/en/technical_material/dcsensor.html) +- San Ace installation/safety manual `M0011876C`, linked from the product page + +## 3. Pinout + +The manufacturer manual states the general San Ace convention: red is positive, +black or blue is ground, yellow is the sensor lead, and brown is the PWM-control +lead. The delivered model must still be inspected because this convention is not +a substitute for specimen-specific verification. + +| Lead | Provisional function | Verification | +|---|---|---| +| Red | +24 V | Inspect delivered specimen and continuity/power test | +| Black | GND | Inspect delivered specimen and continuity/power test | +| Yellow | Pulse sensor / tach | Verify waveform and electrical limits | +| Brown | PWM control | Verify input behavior and safe drive topology | + +## 4. Published model-specific specifications + +The model-specific product page confirms: + +| Property | Published value | +|---|---:| +| Rated voltage | 24 V | +| Operating range | 21.6–26.4 V | +| Rated current | 0.27 A | +| Rated input | 6.48 W | +| Rated speed | 18,000 min⁻¹ | +| Maximum airflow | 0.67 m³/min (23.7 CFM) | +| Maximum static pressure | 535 Pa (2.15 inH₂O) | +| Operating temperature | −20 to +70 °C | +| Sensor | Pulse sensor | +| PWM control | Yes | + +The published model page does not state the exact PWM frequency, tach output +circuit, pulses per revolution, or model-specific open/0% behavior. Manufacturer +technical material supports open-collector/open-drain PWM drive generally, but +also says voltage, frequency, and response differ by model. Those values remain +provisional pending a model-specific drawing or bench evidence. + +## 5. Bench setup + +Required equipment: + +- current-limited 24 V supply +- DMM and oscilloscope +- open-drain PWM source with adjustable frequency/duty +- logic/frequency capture +- thermal measurement suitable for hub, wire, and connector temperatures +- independent optical tachometer preferred +- anemometer optional + +Record wiring, current limit, ambient temperature, airflow fixture, oscilloscope +probe reference, and all instrument identifiers/calibration status. Do not power +the fan until lead identity has been verified. + +## 6. PWM behavior + +- High-impedance/default control behavior: TBD +- Accepted voltage levels: TBD +- Compatible frequency range; test 25 kHz as a candidate point: TBD +- 0% behavior: TBD +- Upward and downward duty sweeps: TBD +- Noise/vibration observations: TBD + +## 7. Tach behavior + +- Output circuit and voltage: TBD +- Required pull-up and sink-current limits: TBD +- Pulses per revolution: TBD +- Jitter and pulse integrity: TBD +- Startup tach-acquisition latency: TBD + +## 8. RPM versus duty + +Record commanded duty, measured RPM, supply current, and tach frequency for both +upward and downward sweeps. Results: TBD. + +## 9. Startup / minimum reliable command + +- Startup current and duration: TBD +- Minimum reliable startup duty: TBD +- Minimum stable running duty: TBD +- Restart hysteresis: TBD + +## 10. Stall / locked rotor + +The manufacturer installation manual describes cyclic current cutoff and +automatic restart as the general DC-fan burnout-protection approach. Verify the +delivered model rather than treating protection as fan proof. + +- Locked-rotor current behavior: TBD +- Tach waveform/semantics while stalled: TBD +- Automatic restart behavior and timing: TBD +- Safe stall-detection latency: TBD + +## 11. Current + +- 24 V steady current: TBD (published rated current is 0.27 A) +- Startup peak: TBD +- Duty-dependent current: TBD +- Locked-rotor current profile: TBD + +## 12. Thermal behavior + +Record ambient, hub, lead, connector, and interface-component temperatures during +steady operation and locked-rotor testing. Results: TBD. + +## 13. Airflow / CZ4060 cooldown + +Record the fan fixture, restriction/static-pressure condition, installed CZ4060 +airflow, cooldown curve, noise, and vibration. Results: TBD. + +## 14. Derived candidate thresholds + +No minimum duty, minimum RPM, stall threshold, proof timeout, or thermal limit is +defined. Derive candidates only after repeatable bench and installed measurements. + +## 15. Open questions + +- exact delivered lead/connector construction and AWG +- exact PWM electrical limits and frequency range +- open-control and 0% behavior +- tach circuit, pull-up, pulses/revolution, and stopped/locked semantics +- startup, stable-speed, and restart behavior +- fan-branch fuse rating and connector/interface component values +- production-fan suitability and acceptable substitutions + +## 16. Installed-system validation + +After bench characterization, repeat the relevant tests in the production-intent +heater/duct/enclosure assembly. Establish airflow margin, hub/wiring/connector +temperature, chamber performance, cooldown effectiveness, EMI/noise behavior, +and trustworthy fan-proof semantics. Installed results: TBD. diff --git a/hardware/kicad/JumpJet_RevA/README.md b/hardware/kicad/JumpJet_RevA/README.md index 28f0be0..f0eeec1 100644 --- a/hardware/kicad/JumpJet_RevA/README.md +++ b/hardware/kicad/JumpJet_RevA/README.md @@ -11,6 +11,10 @@ sheets in this directory. Project-local symbols and footprints resolve through ## Authority and limitations - Rev A.4.1 is the current authoritative **schematic** baseline. +- That baseline originally contained the obsolete two-wire low-side-switched fan + block. Phase-1 source now carries the reviewed provisional four-wire interface: + continuous fused 24 V and ground, open-drain PWM, and 3.3 V tach provisions. + The fan and interface remain prototype/candidate dependent and uncharacterized. - No `.kicad_pcb` exists in this source set. The first Rev A PCB remains active Phase 1 implementation work, not a missing artifact to recover. - This source is not fabrication-ready and does not authorize heater or fan @@ -40,6 +44,12 @@ holes because the previous coordinates do not reconcile with the updated longitudinal datum. Do not release or assign it without the required 1:1 fit check and completion of the blockers in the hardware register. +Current evidence supports a solid carrier PCB beneath the ESP32 module: there +are no underside mounted components, but exposed underside contacts require an +isolation-controlled region. A mandatory central window is not supported by the +evidence. Underside contact mapping and the provisional antenna keepout remain +fabrication blockers. + ## Source-package exclusions The archive's repair, warning-cleanup, presentation, polish, and connector From c597925f7649ace5a6333d43518424c1976e1a2d Mon Sep 17 00:00:00 2001 From: Daniel Brown <30573097+danielbrownjr@users.noreply.github.com> Date: Mon, 7 Sep 2026 03:08:40 -0700 Subject: [PATCH 10/20] hardware: separate gate power and default-disable heater driver --- .../kicad/JumpJet_RevA/BOM_PRELIMINARY.csv | 11 +- .../JumpJet_RevA/JumpJet_Controller.kicad_sch | 18 +- .../JumpJet_Expansion_Test.kicad_sch | 6 +- .../JumpJet_Power_Outputs.kicad_sch | 362 +++++++++++++++--- 4 files changed, 337 insertions(+), 60 deletions(-) diff --git a/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv index 4fe4b53..710a4ca 100644 --- a/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv +++ b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv @@ -2,7 +2,7 @@ Reference,Qty,Function,Value / Requirement,Population,Status J1,1,24 V input,">=20 A keyed terminal, 14 AWG capable",BASE,Footprint TBD F1,1,Main fuse,15 A provisional,BASE,Verify coordination D1,1,Rail TVS,SMBJ30A provisional,BASE,Verify clamp vs MOSFET/PSU -MOD1,1,Logic power,"24 V to 5 V, input transient rating >=60 V",BASE,Exact module TBD +MOD1,1,Gate-domain buck architecture,"TI LMR36520 strong candidate; +24V_PROT to +5V_SYS_GATE; >=1.5 A provisional floor",BASE,"Connector symbol remains an implementation placeholder; discrete circuit footprint thermal derating and final MPN remain open; not BOM-final" F2,1,Heater branch fuse,Littelfuse 0287015.U 15 A ATOF candidate,BASE,"Strong candidate; cold-start characterization complete; PSU/fuse coordination and holder thermal validation open" TF1,1,One-shot thermal fuse,"Historical schematic placeholder: 75 C / 15 A",BASE,"Production part trip temperature mounting and thermal coupling TBD" TS1,1,Resettable thermal switch,"Historical schematic placeholder: NC 75 C / 16 A",BASE,"Production part trip temperature mounting and thermal coupling TBD" @@ -12,10 +12,15 @@ Q1,1,Heater low-side switch,TI CSD18540Q5B candidate,BASE,"Strong candidate only Q2,1,Fan PWM open-drain interface,2N7002-class logic N-MOSFET,BASE,"Provisional control transistor; former 60 V fan-power-switch role is obsolete; exact MPN TBD" D2,0,Legacy fan flyback diode,Obsolete with continuous-power four-wire fan architecture,DNP,Removed from Phase 1 schematic R3/R4,2,Fan PWM gate network,"1 k series / 100 k direct pulldown",BASE,"Provisional values; old fan-power MOSFET gate-network role superseded" -R10/R11/C3,3,3.3 V tach interface,"1 k series / 10 k pull-up / optional filter capacitor DNP",BASE,"Provisional values; exact tach output and filter/protection requirements pending" +R23/R24/C11,3,3.3 V tach interface,"1 k series / 10 k pull-up / optional filter capacitor DNP",BASE,"Provisional values; exact tach output and filter/protection requirements pending" TP9/TP10,2,Fan interface test points,TP_FAN_TACH / TP_FAN_PWM,BASE,Phase 1 bring-up provisions Q3/F4/J4/D3,1 set,AUX1 PWM output,24 V optional,DNP,User expansion -U1,1,Gate buffer,74AHCT125,BASE,"Existing Rev A.4.1 implementation; heater OE/default-disable and power-domain correction remains open" +U1,1,Heater gate buffer/level translator,SN74LV4T125 TSSOP strong candidate,BASE,"Powered only from +5V_SYS_GATE; Ioff-capable candidate; exact ordering code and bench qualification remain open; not BOM-final" +Q4,1,Heater-driver OE open-drain actuator,2N7002-class N-MOSF,BASE,"Provisional implementation; exact MPN not selected; MCU net HEATER_GATE_EN is intentionally unassigned" +R20/R21/R22,3,Heater-driver OE bias,"10 k pull-up / 1 k series / 100 k gate pulldown",BASE,"All values provisional; /OE defaults high/disabled and Q4 must pull it low to enable" +R1/R2/R7,3,Heater PWM/gate passives,"47 ohm gate series / 10 k Q1 gate pulldown / 100 k PWM input pulldown",BASE,"All values provisional pending waveform leakage PWM-frequency switching-loss and transition testing" +C12,1,Gate-buffer local decoupling,100 nF provisional,BASE,"Place at U1 supply pins; dielectric and final value remain subject to implementation review" +TP11-TP16,6,Power and heater-driver test points,"+5V_SYS_GATE / +5V_MCU / OE / PWM input / Q1 gate / Q1 source",BASE,Required Phase 1 power-transition and gate-safety observations U2,1,Controller module,"ESP32-S3 Super Mini, 2x9 edge pads",BASE,"Identity confirmed; pad numbering receiving-land geometry registration underside isolation antenna keepout USB access and flash size remain open" J6-J8,3,Thermistors,"10 k NTC, 1 m lead",BASE,Beta/coefficients TBD J9 + divider,1,Fourth thermistor,10 k NTC,DNP,Expansion diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch index 68a81eb..9b2762f 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch @@ -1258,6 +1258,16 @@ (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid 989d1c1b-e73b-4557-9840-8d28f49f2f69) ) + (text "+5V_MCU source selection is TBD: do not bridge to +5V_SYS_GATE or assume USB/external-5V isolation." + (at 28.00 124.00 0) + (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) + (uuid d7a12df2-cad0-4bf1-bfb7-709f03e42f5f) + ) + (text "LEGACY_HTR_PWM_NC preserves the historical physical mapping only; HEATER_PWM_CMD and HEATER_GATE_EN have no assigned GPIO." + (at 28.00 130.00 0) + (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) + (uuid 5397c9d8-4358-4c42-ae52-702dd108aa65) + ) (label "UART_RX" (at 53.34 60.96 0) (effects (font (size 0.85 0.85)) (justify left bottom)) @@ -1293,7 +1303,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 09e2faff-9cca-459f-94ac-bcbcda17b21d) ) - (global_label "+5V" (shape bidirectional) (at 96.52 55.88 0) (fields_autoplaced) + (global_label "+5V_MCU" (shape bidirectional) (at 96.52 55.88 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 10f318da-a8cd-41c1-bf6f-8de912467e64) ) @@ -1305,7 +1315,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 1488295c-cb26-4e1e-a891-18bee4eece2a) ) - (global_label "HTR_PWM" (shape bidirectional) (at 96.52 71.12 0) (fields_autoplaced) + (global_label "LEGACY_HTR_PWM_NC" (shape bidirectional) (at 96.52 71.12 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 1b0862be-8ff4-4da3-8fa8-105ab0a179f9) ) @@ -1317,7 +1327,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 6e7911dd-5bac-409c-962f-7111ce706d4f) ) - (global_label "+5V" (shape bidirectional) (at 160.02 45.72 90) (fields_autoplaced) + (global_label "+5V_MCU" (shape bidirectional) (at 160.02 45.72 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 809ae46b-0af2-45b2-8399-2860debe0e47) ) @@ -1357,7 +1367,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid e3bf934c-60ef-415b-8ad3-e992508c9195) ) - (global_label "+5V" (shape bidirectional) (at 147.32 45.72 90) (fields_autoplaced) + (global_label "+5V_MCU" (shape bidirectional) (at 147.32 45.72 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid ede18b13-64ee-4923-bcf4-c8231ed0ad30) ) diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Expansion_Test.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Expansion_Test.kicad_sch index 3d097f6..24f696d 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Expansion_Test.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Expansion_Test.kicad_sch @@ -1483,11 +1483,11 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid c53fbd1f-713f-4d70-9017-881f7bc8322e) ) - (global_label "+5V" (shape bidirectional) (at 73.66 123.19 0) (fields_autoplaced) + (global_label "+5V_MCU" (shape bidirectional) (at 73.66 123.19 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid c5593b63-df8b-44b5-8b8c-9267b2dc48a4) ) - (global_label "+5V" (shape bidirectional) (at 90.17 167.64 90) (fields_autoplaced) + (global_label "+5V_MCU" (shape bidirectional) (at 90.17 167.64 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid cd116fe2-cd16-4a35-a5c4-ef0f1a9441b4) ) @@ -1803,7 +1803,7 @@ (property "Reference" "TP2" (at 85.83 157.84 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "+5V" (at 93.83 163.84 0) + (property "Value" "+5V_MCU" (at 93.83 163.84 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 89.83 160.84 0) diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch index 53ab3ee..487db04 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch @@ -16,20 +16,20 @@ ) (lib_symbols - (symbol "74xx:74AHCT125" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (symbol "74xx:SN74LV4T125" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) (property "Reference" "U" (at 0 1.27 0) (show_name) (effects (font (size 1.27 1.27))) ) - (property "Value" "74AHCT125" (at 0 -1.27 0) (show_name) + (property "Value" "SN74LV4T125" (at 0 -1.27 0) (show_name) (effects (font (size 1.27 1.27))) ) (property "Footprint" "" (at 0 0 0) (show_name) (effects (font (size 1.27 1.27))) ) - (property "Datasheet" "https://www.ti.com/lit/ds/symlink/sn74ahct125.pdf" (at 0 0 0) (show_name) + (property "Datasheet" "https://www.ti.com/product/SN74LV4T125" (at 0 0 0) (show_name) (effects (font (size 1.27 1.27))) ) - (property "Description" "Quadruple Bus Buffer Gates With 3-State Outputs" (at 0 0 0) (show_name) + (property "Description" "Quadruple level-translating buffer with 3-state outputs and Ioff partial-power-down support; strong candidate, not BOM-final" (at 0 0 0) (show_name) (effects (font (size 1.27 1.27))) ) (property "ki_locked" "" (at 0 0 0) (show_name) @@ -41,7 +41,7 @@ (property "ki_fp_filters" "DIP*W7.62mm* SO14* SSOP?14* TSSOP?14* SOIC*3.9x8.7mm*P1.27mm*" (at 0 0 0) (show_name) (effects (font (size 1.27 1.27))) ) - (symbol "74AHCT125_1_0" + (symbol "SN74LV4T125_1_0" (polyline (pts (xy -3.81 3.81) @@ -65,7 +65,7 @@ (number "3" (effects (font (size 1.27 1.27)))) ) ) - (symbol "74AHCT125_2_0" + (symbol "SN74LV4T125_2_0" (polyline (pts (xy -3.81 3.81) @@ -89,7 +89,7 @@ (number "6" (effects (font (size 1.27 1.27)))) ) ) - (symbol "74AHCT125_3_0" + (symbol "SN74LV4T125_3_0" (polyline (pts (xy -3.81 3.81) @@ -113,7 +113,7 @@ (number "10" (effects (font (size 1.27 1.27)))) ) ) - (symbol "74AHCT125_4_0" + (symbol "SN74LV4T125_4_0" (polyline (pts (xy -3.81 3.81) @@ -137,7 +137,7 @@ (number "13" (effects (font (size 1.27 1.27)))) ) ) - (symbol "74AHCT125_5_0" + (symbol "SN74LV4T125_5_0" (pin power_in line (at 0 -12.7 90) (length 5.08) (name "GND" (effects (font (size 1.27 1.27)))) (number "7" (effects (font (size 1.27 1.27)))) @@ -147,7 +147,7 @@ (number "14" (effects (font (size 1.27 1.27)))) ) ) - (symbol "74AHCT125_5_1" + (symbol "SN74LV4T125_5_1" (rectangle (start -5.08 7.62) (end 5.08 -7.62) (stroke (width 0.254) (type default)) (fill (type background)) @@ -1378,13 +1378,13 @@ (effects (font (size 1.80 1.80) (thickness 0.225)) (justify left bottom)) (uuid 35f7f43e-ad43-476c-8fd0-7eb41fba3c3a) ) - (text "MOD1 must tolerate the protected 24 V rail plus transients; 5 V powers the SuperMini VIN pin." + (text "MOD1 is an LMR36520 architecture placeholder: +24V_PROT to +5V_SYS_GATE only; +5V_MCU source selection remains TBD." (at 23.00 92.00 0) (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid 7f86481b-c093-4c97-83e9-606d5d071579) ) - (text "Heater driver default-disable and power-domain sequencing remain required corrections." - (at 150.00 137.00 0) + (text "Heater OE defaults disabled; Q_GATE_EN requires explicit MCU assertion. USB-only power cannot source +5V_SYS_GATE." + (at 150.00 174.00 0) (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid b59cd9c9-fcc4-462d-b06a-d4a2a3106217) ) @@ -1398,12 +1398,12 @@ (uuid bcd2022d-b38f-417c-87e7-ca6ea3cb4589) ) (text "Fan: continuous fused 24 V + GND; separate open-drain PWM and 3.3 V tach interface." - (at 150.00 143.00 0) + (at 150.00 180.00 0) (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid eab4d0bb-5495-40fc-aa49-ad112c75465b) ) (text "TF1 and TS1 are physically mounted at the heater hot spot and interrupt only the heating element." - (at 150.00 149.00 0) + (at 150.00 186.00 0) (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid efadd267-eef7-4648-9d7b-c0ed698f7488) ) @@ -1524,7 +1524,7 @@ (uuid f3b0fa95-806d-494b-b739-d4a6a9b9305d) ) - (global_label "+5V" (shape bidirectional) (at 365.76 109.22 90) (fields_autoplaced) + (global_label "+5V_SYS_GATE" (shape bidirectional) (at 365.76 109.22 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 08642273-0c58-41ab-b3f7-8259041ffc7a) ) @@ -1548,7 +1548,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 35f42238-1b79-46a9-afe9-78226d681d98) ) - (global_label "HTR_PWM" (shape bidirectional) (at 182.88 125.73 90) (fields_autoplaced) + (global_label "HEATER_PWM_CMD" (shape bidirectional) (at 182.88 125.73 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 378a2065-ead5-4b3f-bf42-262ab5eea650) ) @@ -1597,11 +1597,11 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid ae2122e0-a38c-4b29-943c-86263a42bfc7) ) - (global_label "+5V" (shape bidirectional) (at 123.19 54.61 90) (fields_autoplaced) + (global_label "+5V_SYS_GATE" (shape bidirectional) (at 123.19 54.61 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid b08c8edb-c061-447c-ba7f-21f6d063ccdf) ) - (global_label "+5V" (shape bidirectional) (at 97.79 59.69 0) (fields_autoplaced) + (global_label "+5V_SYS_GATE" (shape bidirectional) (at 97.79 59.69 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid b1b78cf5-2506-4bbe-b347-963ab23b8e07) ) @@ -1633,7 +1633,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid d22fb86c-12f6-4d4e-a1e6-d8afd73d2230) ) - (global_label "HTR_PWM" (shape bidirectional) (at 184.15 121.92 0) (fields_autoplaced) + (global_label "HEATER_PWM_CMD" (shape bidirectional) (at 184.15 121.92 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid e367787d-16bf-4d15-a4bd-417713d68ac0) ) @@ -1654,22 +1654,22 @@ (uuid fa6b12f7-44ec-4e76-92cd-fb3570f0baa6) ) - (global_label "GND" (shape bidirectional) (at 193.04 128.27 90) (fields_autoplaced) + (global_label "HEATER_GATE_OE_N" (shape bidirectional) (at 193.04 128.27 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid ff1edd3a-94e1-4a88-95ad-321dfb191aef) ) - (global_label "GND" (shape bidirectional) (at 238.76 128.27 90) (fields_autoplaced) + (global_label "+5V_SYS_GATE" (shape bidirectional) (at 238.76 128.27 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 33465e22-799a-4cba-8255-e5939c1d79e7) ) - (global_label "GND" (shape bidirectional) (at 284.48 128.27 90) (fields_autoplaced) + (global_label "+5V_SYS_GATE" (shape bidirectional) (at 284.48 128.27 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid f8c41a3c-7347-4823-98b7-0dbaa4e4de99) ) - (global_label "GND" (shape bidirectional) (at 335.28 128.27 90) (fields_autoplaced) + (global_label "+5V_SYS_GATE" (shape bidirectional) (at 335.28 128.27 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 4bffbd2d-67bb-4650-8169-a35334e7271e) ) @@ -1739,6 +1739,72 @@ (uuid c84a114b-76da-4cc1-8b34-247823146262) ) + (global_label "+5V_SYS_GATE" (shape bidirectional) (at 218.44 134.62 90) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 52066b3d-0765-4c78-8970-bad5b68bbd01) + ) + (global_label "HEATER_GATE_OE_N" (shape bidirectional) (at 218.44 142.24 90) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid f1538e20-c14e-482a-b2ae-f8252b9ad402) + ) + (global_label "HEATER_GATE_OE_N" (shape bidirectional) (at 220.98 146.05 90) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid e43eb73c-5a71-42d9-b25a-798d182f7b03) + ) + (global_label "HEATER_GATE_EN" (shape bidirectional) (at 201.93 151.13 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 1976b314-d5e2-48ab-a55f-7ea7e87e2c04) + ) + (global_label "HEATER_GATE_EN_INT" (shape bidirectional) (at 209.55 151.13 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 2e2632b8-563b-4c16-9214-704428d45905) + ) + (global_label "HEATER_GATE_EN_INT" (shape bidirectional) (at 213.36 151.13 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 0ad91d6d-9ee9-4c80-b554-a596a940b51c) + ) + (global_label "GND" (shape bidirectional) (at 213.36 158.75 90) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 320c49c0-265b-462d-891d-fc935eaf3538) + ) + (global_label "GND" (shape bidirectional) (at 220.98 156.21 90) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid d978b28b-6d70-4cac-bba6-31f3dc5f85e0) + ) + + (global_label "+5V_SYS_GATE" (shape bidirectional) (at 130.81 109.22 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 7d42c535-d871-4751-bcd7-7c5ed55fc263) + ) + (global_label "+5V_MCU" (shape bidirectional) (at 147.32 109.22 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid c17a63e2-ee13-41c1-9815-67d9d0126df3) + ) + (global_label "HEATER_GATE_OE_N" (shape bidirectional) (at 193.04 136.00 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid e95523ab-439f-451b-84b4-1849bcdce835) + ) + (global_label "HEATER_PWM_CMD" (shape bidirectional) (at 175.26 116.84 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid d0475735-701a-4760-abfc-076432b0848c) + ) + (global_label "HTR_GATE" (shape bidirectional) (at 228.60 88.90 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 462c9f7e-4cb6-4aef-b52e-eb3d1909d511) + ) + (global_label "GND" (shape bidirectional) (at 246.38 88.90 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid c1ed12ce-8ad8-4dab-82ed-03ed4137f411) + ) + (global_label "+5V_SYS_GATE" (shape bidirectional) (at 350.52 146.19 90) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid ae374296-e039-456a-b5f6-5564f68f6772) + ) + (global_label "GND" (shape bidirectional) (at 350.52 153.81 90) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 4d718d1f-57d1-407d-81f5-aa518a65ae97) + ) + (symbol (lib_id "JumpJet_Controller_RevA:JJ_PWR_FLAG") (at 365.76 109.22 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid 953d0364-dbd7-4539-aad3-17e3f676f9b8) @@ -1917,16 +1983,16 @@ (property "Reference" "MOD1" (at 105.55 49.32 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "24V→5V BUCK TBD" (at 105.55 65.32 0) + (property "Value" "LMR36520 24V→5V CANDIDATE / IMPLEMENTATION TBD" (at 105.55 65.32 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "TBD:DC_DC_Module" (at 105.55 57.32 0) (effects (font (size 0.85 0.85)) hide) ) - (property "Datasheet" "" (at 105.55 57.32 0) + (property "Datasheet" "https://www.ti.com/product/LMR36520" (at 105.55 57.32 0) (effects (font (size 0.85 0.85)) hide) ) - (property "Description" "" (at 105.55 57.32 0) + (property "Description" "Strong-candidate architecture only; connector symbol remains an implementation placeholder and is not BOM-final." (at 105.55 57.32 0) (effects (font (size 0.85 0.85)) hide) ) (pin "3" (uuid a93861bb-f1f1-4de8-b34e-b1422231dac8)) @@ -2123,7 +2189,7 @@ (property "Reference" "R1" (at 213.19 65.68 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "47R TBD" (at 221.59 69.28 0) + (property "Value" "47R PROVISIONAL" (at 221.59 69.28 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "" (at 217.39 67.48 0) @@ -2152,7 +2218,7 @@ (property "Reference" "R2" (at 228.82 72.37 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "100k" (at 228.82 80.37 0) + (property "Value" "10k GATE PULLDOWN PROVISIONAL" (at 228.82 80.37 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "" (at 228.82 76.37 0) @@ -2326,7 +2392,7 @@ (symbol (lib_id "Device:R") (at 256.54 96.52 90) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid 6ca9f5e8-2775-434a-a275-8f629388147d) - (property "Reference" "R10" (at 252.56 94.89 0) + (property "Reference" "R23" (at 252.56 94.89 0) (effects (font (size 0.85 0.85))) ) (property "Value" "1k TACH SERIES PROVISIONAL" (at 260.96 98.49 0) @@ -2346,7 +2412,7 @@ (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" - (reference "R10") (unit 1) + (reference "R23") (unit 1) ) ) ) @@ -2355,7 +2421,7 @@ (symbol (lib_id "Device:R") (at 273.05 99.06 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid 5789223a-1130-461c-b785-5fb2f811594d) - (property "Reference" "R11" (at 273.27 95.23 0) + (property "Reference" "R24" (at 273.27 95.23 0) (effects (font (size 0.85 0.85))) ) (property "Value" "10k TACH PULLUP PROVISIONAL" (at 273.27 103.23 0) @@ -2375,7 +2441,7 @@ (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" - (reference "R11") (unit 1) + (reference "R24") (unit 1) ) ) ) @@ -2384,7 +2450,7 @@ (symbol (lib_id "Device:C") (at 286 99.06 0) (unit 1) (in_bom yes) (on_board yes) (dnp yes) (uuid 3ef8d1f4-a503-479a-b508-2546715a582a) - (property "Reference" "C3" (at 286.14 95.23 0) + (property "Reference" "C11" (at 286.14 95.23 0) (effects (font (size 0.85 0.85))) ) (property "Value" "TACH FILTER DNP/TBD" (at 286.14 103.23 0) @@ -2404,7 +2470,7 @@ (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" - (reference "C3") (unit 1) + (reference "C11") (unit 1) ) ) ) @@ -2641,19 +2707,19 @@ ) ) - (symbol (lib_id "74xx:74AHCT125") (at 193.04 121.92 0) (unit 1) + (symbol (lib_id "74xx:SN74LV4T125") (at 193.04 121.92 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-000068ae001a) (property "Reference" "U1" (at 193.26 115.77 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "74AHCT125" (at 193.26 127.77 0) + (property "Value" "SN74LV4T125" (at 193.26 127.77 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "Package_SO:TSSOP-14_4.4x5mm_P0.65mm" (at 193.26 121.77 0) (effects (font (size 0.85 0.85)) hide) ) - (property "Datasheet" "" (at 193.26 121.77 0) + (property "Datasheet" "https://www.ti.com/product/SN74LV4T125" (at 193.26 121.77 0) (effects (font (size 0.85 0.85)) hide) ) (property "Description" "" (at 193.26 121.77 0) @@ -2682,19 +2748,19 @@ ) ) - (symbol (lib_id "74xx:74AHCT125") (at 238.76 121.92 0) (unit 2) + (symbol (lib_id "74xx:SN74LV4T125") (at 238.76 121.92 0) (unit 2) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-000068ae001b) (property "Reference" "U1" (at 238.98 115.77 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "74AHCT125" (at 238.98 127.77 0) + (property "Value" "SN74LV4T125" (at 238.98 127.77 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "Package_SO:TSSOP-14_4.4x5mm_P0.65mm" (at 238.98 121.77 0) (effects (font (size 0.85 0.85)) hide) ) - (property "Datasheet" "" (at 238.98 121.77 0) + (property "Datasheet" "https://www.ti.com/product/SN74LV4T125" (at 238.98 121.77 0) (effects (font (size 0.85 0.85)) hide) ) (property "Description" "" (at 238.98 121.77 0) @@ -2723,19 +2789,19 @@ ) ) - (symbol (lib_id "74xx:74AHCT125") (at 284.48 121.92 0) (unit 3) + (symbol (lib_id "74xx:SN74LV4T125") (at 284.48 121.92 0) (unit 3) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-000068ae001c) (property "Reference" "U1" (at 284.70 115.77 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "74AHCT125" (at 284.70 127.77 0) + (property "Value" "SN74LV4T125" (at 284.70 127.77 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "Package_SO:TSSOP-14_4.4x5mm_P0.65mm" (at 284.70 121.77 0) (effects (font (size 0.85 0.85)) hide) ) - (property "Datasheet" "" (at 284.70 121.77 0) + (property "Datasheet" "https://www.ti.com/product/SN74LV4T125" (at 284.70 121.77 0) (effects (font (size 0.85 0.85)) hide) ) (property "Description" "" (at 284.70 121.77 0) @@ -2764,19 +2830,19 @@ ) ) - (symbol (lib_id "74xx:74AHCT125") (at 335.28 121.92 0) (unit 4) + (symbol (lib_id "74xx:SN74LV4T125") (at 335.28 121.92 0) (unit 4) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-000068ae001d) (property "Reference" "U1" (at 335.50 115.77 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "74AHCT125" (at 335.50 127.77 0) + (property "Value" "SN74LV4T125" (at 335.50 127.77 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "Package_SO:TSSOP-14_4.4x5mm_P0.65mm" (at 335.50 121.77 0) (effects (font (size 0.85 0.85)) hide) ) - (property "Datasheet" "" (at 335.50 121.77 0) + (property "Datasheet" "https://www.ti.com/product/SN74LV4T125" (at 335.50 121.77 0) (effects (font (size 0.85 0.85)) hide) ) (property "Description" "" (at 335.50 121.77 0) @@ -2805,19 +2871,19 @@ ) ) - (symbol (lib_id "74xx:74AHCT125") (at 365.76 121.92 0) (unit 5) + (symbol (lib_id "74xx:SN74LV4T125") (at 365.76 121.92 0) (unit 5) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-000068ae001e) (property "Reference" "U1" (at 365.98 111.77 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "74AHCT125" (at 365.98 131.77 0) + (property "Value" "SN74LV4T125" (at 365.98 131.77 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "Package_SO:TSSOP-14_4.4x5mm_P0.65mm" (at 365.98 121.77 0) (effects (font (size 0.85 0.85)) hide) ) - (property "Datasheet" "" (at 365.98 121.77 0) + (property "Datasheet" "https://www.ti.com/product/SN74LV4T125" (at 365.98 121.77 0) (effects (font (size 0.85 0.85)) hide) ) (property "Description" "" (at 365.98 121.77 0) @@ -2932,4 +2998,200 @@ ) ) ) + + (symbol (lib_id "Device:R") (at 218.44 138.43 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid a8e9fdc6-0fd1-46af-ae47-1c33b29fbe20) + (property "Reference" "R20" (at 218.66 134.60 0) + (effects (font (size 0.85 0.85))) + ) + (property "Value" "10k OE PULLUP PROVISIONAL" (at 218.66 142.60 0) + (effects (font (size 0.85 0.85))) + ) + (property "Footprint" "Resistor_SMD:R_0603_1608Metric" (at 218.66 138.60 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Datasheet" "" (at 218.66 138.60 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Description" "Pulls active-low heater-driver OE disabled whenever Q_GATE_EN is off or unpowered." (at 218.66 138.60 0) + (effects (font (size 0.85 0.85)) hide) + ) + (pin "1" (uuid c49107cc-64e3-4d55-91b1-a7046e248d64)) + (pin "2" (uuid dbf0f63e-2a88-4436-b347-6f889cfe1164)) + (instances + (project "JumpJet_Controller_RevA4" + (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" + (reference "R20") (unit 1) + ) + ) + ) + ) + + (symbol (lib_id "Device:R") (at 205.74 151.13 90) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 4992e94e-e4fc-403a-88a0-4bc908af1835) + (property "Reference" "R21" (at 201.76 149.50 0) + (effects (font (size 0.85 0.85))) + ) + (property "Value" "1k ENABLE SERIES PROVISIONAL" (at 210.16 153.10 0) + (effects (font (size 0.85 0.85))) + ) + (property "Footprint" "Resistor_SMD:R_0603_1608Metric" (at 205.96 151.30 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Datasheet" "" (at 205.96 151.30 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Description" "Provisional MCU-to-Q_GATE_EN gate series resistor; no GPIO assignment." (at 205.96 151.30 0) + (effects (font (size 0.85 0.85)) hide) + ) + (pin "1" (uuid 60dc0f51-c0a8-4cf6-be53-338ca20c97d9)) + (pin "2" (uuid a338c7e8-2a49-457e-8492-6aca586d980d)) + (instances + (project "JumpJet_Controller_RevA4" + (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" + (reference "R21") (unit 1) + ) + ) + ) + ) + + (symbol (lib_id "Device:R") (at 213.36 154.94 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 8b378896-7c96-4a40-b05a-3ee4ca26364f) + (property "Reference" "R22" (at 213.58 151.11 0) + (effects (font (size 0.85 0.85))) + ) + (property "Value" "100k ENABLE PULLDOWN PROVISIONAL" (at 213.58 159.11 0) + (effects (font (size 0.85 0.85))) + ) + (property "Footprint" "Resistor_SMD:R_0603_1608Metric" (at 213.58 155.11 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Datasheet" "" (at 213.58 155.11 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Description" "Direct Q_GATE_EN gate pulldown; keeps heater-driver OE disabled with MCU reset/high-Z/unpowered." (at 213.58 155.11 0) + (effects (font (size 0.85 0.85)) hide) + ) + (pin "1" (uuid 4e479b58-8307-45fd-993e-01f48749f8d4)) + (pin "2" (uuid 739f5b7d-8b5e-43a2-baaa-2b05aeb72244)) + (instances + (project "JumpJet_Controller_RevA4" + (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" + (reference "R22") (unit 1) + ) + ) + ) + ) + + (symbol (lib_id "Transistor_FET:Q_NMOS_GDS") (at 218.44 151.13 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 58e0f9a8-15af-444f-8ef0-f3735c1863a4) + (property "Reference" "Q4" (at 218.66 145.30 0) + (effects (font (size 0.85 0.85))) + ) + (property "Value" "Q_GATE_EN 2N7002-CLASS PROVISIONAL" (at 218.66 157.30 0) + (effects (font (size 0.85 0.85))) + ) + (property "Footprint" "Package_TO_SOT_SMD:SOT-23" (at 218.66 151.30 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Datasheet" "" (at 218.66 151.30 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Description" "Open-drain active-low OE actuator; exact MPN is provisional and not BOM-final." (at 218.66 151.30 0) + (effects (font (size 0.85 0.85)) hide) + ) + (pin "1" (uuid 9bb1a557-327e-4748-8081-61c8b646310a)) + (pin "2" (uuid e1aa184c-125c-4b39-bd26-c240046f14b1)) + (pin "3" (uuid f5e9bedd-514f-48a5-89fa-0fb5019670d2)) + (instances + (project "JumpJet_Controller_RevA4" + (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" + (reference "Q4") (unit 1) + ) + ) + ) + ) + + (symbol (lib_id "Connector:TestPoint") (at 130.81 109.22 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 5036d94e-0cc2-48b5-b18f-ef69098020b3) + (property "Reference" "TP11" (at 126.71 105.77 0) (effects (font (size 0.85 0.85)))) + (property "Value" "TP_5V_SYS_GATE" (at 134.71 111.77 0) (effects (font (size 0.85 0.85)))) + (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 130.71 108.77 0) (effects (font (size 0.85 0.85)) hide)) + (property "Datasheet" "" (at 130.71 108.77 0) (effects (font (size 0.85 0.85)) hide)) + (property "Description" "24 V-derived gate-domain rail test point" (at 130.71 108.77 0) (effects (font (size 0.85 0.85)) hide)) + (pin "1" (uuid 273c55d5-a3c2-4cf1-8843-0df7fa573a35)) + (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "TP11") (unit 1)))) + ) + (symbol (lib_id "Connector:TestPoint") (at 147.32 109.22 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 8f894626-80b2-4a68-a9b0-f68a1fb5d82d) + (property "Reference" "TP12" (at 143.22 105.77 0) (effects (font (size 0.85 0.85)))) + (property "Value" "TP_5V_MCU" (at 151.22 111.77 0) (effects (font (size 0.85 0.85)))) + (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 147.22 108.77 0) (effects (font (size 0.85 0.85)) hide)) + (property "Datasheet" "" (at 147.22 108.77 0) (effects (font (size 0.85 0.85)) hide)) + (property "Description" "MCU-domain rail test point; source selection remains TBD" (at 147.22 108.77 0) (effects (font (size 0.85 0.85)) hide)) + (pin "1" (uuid e56fbc18-6b61-4f88-bc30-66fca23e14c8)) + (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "TP12") (unit 1)))) + ) + (symbol (lib_id "Connector:TestPoint") (at 193.04 136.00 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 0cd52f47-ec30-4291-8506-0750d4b3a12f) + (property "Reference" "TP13" (at 188.94 132.55 0) (effects (font (size 0.85 0.85)))) + (property "Value" "TP_GATE_OE" (at 196.94 138.55 0) (effects (font (size 0.85 0.85)))) + (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 192.94 135.55 0) (effects (font (size 0.85 0.85)) hide)) + (property "Datasheet" "" (at 192.94 135.55 0) (effects (font (size 0.85 0.85)) hide)) + (property "Description" "Heater-channel active-low OE test point" (at 192.94 135.55 0) (effects (font (size 0.85 0.85)) hide)) + (pin "1" (uuid df407eb9-1341-446b-aeaf-7f705a287ed4)) + (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "TP13") (unit 1)))) + ) + (symbol (lib_id "Connector:TestPoint") (at 175.26 116.84 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 52f7539c-7a6d-4bfc-a828-c72d86420b20) + (property "Reference" "TP14" (at 171.16 113.39 0) (effects (font (size 0.85 0.85)))) + (property "Value" "TP_HEATER_PWM_IN" (at 179.16 119.39 0) (effects (font (size 0.85 0.85)))) + (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 175.16 116.39 0) (effects (font (size 0.85 0.85)) hide)) + (property "Datasheet" "" (at 175.16 116.39 0) (effects (font (size 0.85 0.85)) hide)) + (property "Description" "Generic unassigned heater PWM command test point" (at 175.16 116.39 0) (effects (font (size 0.85 0.85)) hide)) + (pin "1" (uuid f9c406f5-d885-4f7b-bf36-81eb6f94ad67)) + (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "TP14") (unit 1)))) + ) + (symbol (lib_id "Connector:TestPoint") (at 228.60 88.90 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 902e351d-d598-4f0c-8365-e48e4b34185e) + (property "Reference" "TP15" (at 224.50 85.45 0) (effects (font (size 0.85 0.85)))) + (property "Value" "TP_Q1_GATE" (at 232.50 91.45 0) (effects (font (size 0.85 0.85)))) + (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 228.50 88.45 0) (effects (font (size 0.85 0.85)) hide)) + (property "Datasheet" "" (at 228.50 88.45 0) (effects (font (size 0.85 0.85)) hide)) + (property "Description" "Q1 gate test point" (at 228.50 88.45 0) (effects (font (size 0.85 0.85)) hide)) + (pin "1" (uuid 4e6de77f-15a4-408e-bfc4-b6b07dc66fb6)) + (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "TP15") (unit 1)))) + ) + (symbol (lib_id "Connector:TestPoint") (at 246.38 88.90 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 8dd76a68-9ac4-45b2-85b4-92fcbd1619c9) + (property "Reference" "TP16" (at 242.28 85.45 0) (effects (font (size 0.85 0.85)))) + (property "Value" "TP_Q1_SOURCE" (at 250.28 91.45 0) (effects (font (size 0.85 0.85)))) + (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 246.28 88.45 0) (effects (font (size 0.85 0.85)) hide)) + (property "Datasheet" "" (at 246.28 88.45 0) (effects (font (size 0.85 0.85)) hide)) + (property "Description" "Q1 source-reference test point on ground net" (at 246.28 88.45 0) (effects (font (size 0.85 0.85)) hide)) + (pin "1" (uuid 9e23a224-e9e1-4b84-9fbd-f7c29b4bdb21)) + (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "TP16") (unit 1)))) + ) + (symbol (lib_id "Device:C") (at 350.52 150.00 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid c44ebd4d-e17a-42a4-9813-b15b484c04bf) + (property "Reference" "C12" (at 350.66 146.17 0) (effects (font (size 0.85 0.85)))) + (property "Value" "100nF U1 DECOUPLING PROVISIONAL" (at 350.66 154.17 0) (effects (font (size 0.85 0.85)))) + (property "Footprint" "Capacitor_SMD:C_0603_1608Metric" (at 350.66 150.17 0) (effects (font (size 0.85 0.85)) hide)) + (property "Datasheet" "" (at 350.66 150.17 0) (effects (font (size 0.85 0.85)) hide)) + (property "Description" "Local SN74LV4T125 supply bypass; value and dielectric require final review." (at 350.66 150.17 0) (effects (font (size 0.85 0.85)) hide)) + (pin "1" (uuid ee1a40d3-d721-4106-ad8b-caceb919fd6a)) + (pin "2" (uuid 2b88943d-1899-40c3-a5b8-5eb262499613)) + (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "C12") (unit 1)))) + ) ) From e7539fe73b3cdea2d042c3b0131005c4727f99f4 Mon Sep 17 00:00:00 2001 From: Daniel Brown <30573097+danielbrownjr@users.noreply.github.com> Date: Mon, 7 Sep 2026 03:09:10 -0700 Subject: [PATCH 11/20] docs: record Phase 1 power-domain safety architecture --- TODO.md | 12 ++++++----- docs/HARDWARE_BASELINE.md | 13 ++++++++++-- docs/PHASE1_HARDWARE_REGISTER.md | 36 +++++++++++++++++++------------- 3 files changed, 39 insertions(+), 22 deletions(-) diff --git a/TODO.md b/TODO.md index 3872eb3..3d10578 100644 --- a/TODO.md +++ b/TODO.md @@ -84,12 +84,14 @@ implementation starts, and keep only the summary checkbox here. all final fan and auxiliary loads - [ ] Calculate connector/contact loading and wire ampacity with temperature derating - [ ] Calculate MOSFET conduction and switching loss at worst-case voltage, current, duty, and ambient -- [ ] Correct gate-driver OE so heater drive is hardware-default-disabled during - power-up, power-down, reset, and brownout -- [ ] Ensure USB/service power cannot energize the gate-driver power domain or Q1 +- [x] Implement separate `+5V_SYS_GATE` / `+5V_MCU` schematic domains and a + hardware-default-disabled heater-driver OE topology +- [ ] Bench-verify that USB/service power cannot energize the gate-driver domain + or Q1 through every power-up, power-down, reset, brownout, and mixed-source state - [ ] Verify gate-driver partial-power-down behavior or provide equivalent isolation -- [ ] Retain a direct Q1 gate pull-down independent of MCU and buffer state -- [ ] Add test points for the gate-driver power domain, gate-driver OE, and Q1 gate +- [x] Retain a direct provisional Q1 gate pull-down independent of MCU and buffer state +- [x] Add schematic test points for both 5 V domains, gate-driver OE, heater PWM + input, Q1 gate, and Q1 source reference - [ ] Check gate voltage/current, MCU reset behavior, switching waveform, and MOSFET SOA - [ ] Calculate trace/via current capacity and expected copper temperature rise - [ ] Calculate thermistor-divider voltage and ADC counts over open, short, and operating range diff --git a/docs/HARDWARE_BASELINE.md b/docs/HARDWARE_BASELINE.md index 67d44a5..233f2f9 100644 --- a/docs/HARDWARE_BASELINE.md +++ b/docs/HARDWARE_BASELINE.md @@ -26,13 +26,22 @@ or authorize heater actuation. two-wire block is retained as baseline evidence, not production intent. - Published prototype facts and pending measurements are tracked in the [9GA0424P3J001 characterization record](hardware/9ga0424p3j001-characterization.md). +- Phase-1 schematic work now separates a protected-24-V-derived + `+5V_SYS_GATE` rail from the unresolved `+5V_MCU` service/source-selected + domain. The gate buffer cannot be powered from USB-only MCU power. +- The heater driver now uses a hardware-default-disabled active-low OE topology: + an OE pull-up holds the driver disabled unless a separate open-drain enable + transistor is explicitly asserted. Generic `HEATER_GATE_EN` and + `HEATER_PWM_CMD` nets remain unassigned to controller pins. ## Not confirmed Q1, F2, PCB copper, connectors, wiring, installed airflow, the exact ESP32-S3 module implementation, and the complete power path have not been validated -together. The upstream Jetpack pin assignments are historical facts, not Jump -Jet assignments. +together. The LMR36520 and SN74LV4T125 are strong candidates, not BOM-final; +the regulator circuit, `+5V_MCU` source selection, reverse-current behavior, +and full power-transition bench matrix remain open. The upstream Jetpack pin +assignments are historical facts, not Jump Jet assignments. No GPIO, ADC, divider, thermistor conversion, protection threshold, thermal trip, cooldown criterion, or recovery threshold may be finalized without corresponding diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index 329b0d6..8c0dc8a 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -1,6 +1,6 @@ # Phase 1 hardware source-of-truth register -Last updated: 2026-09-06 +Last updated: 2026-09-07 This is the living engineering register for JumpJet Rev A Phase-1 hardware implementation. It records what is known, how it is known, what remains @@ -77,12 +77,13 @@ temperatures. | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | |---|---|---|---|---|---|---| -| Production power domains | DESIGN DECISION | Protected 24 V feeds the onboard buck. Its buck-only `+5V_SYS/GATE` domain powers gate-drive circuitry. A separately isolated or source-selected `+5V_MCU` domain feeds the ESP32-S3 Super Mini external 5 V/VBUS input. Raw 24 V must never reach the module, and USB service power must never energize gate-drive circuitry. | Phase-1 power-domain and service-safety decision | High | Verify module power pin/topology; select and qualify the regulator, isolation/source-selection method, sequencing, and power-domain implementation. | PCB layout + BOM freeze + Fabrication | +| Production power domains | DESIGN DECISION | Protected 24 V feeds the onboard buck and its exclusive `+5V_SYS_GATE` output. That rail powers heater gate-drive circuitry and is never USB-sourced. A separately isolated or source-selected `+5V_MCU` domain feeds the ESP32-S3 Super Mini external 5 V/VBUS input. Raw 24 V must never reach the module, and USB-only MCU power must be physically incapable of powering the gate rail. | Phase-1 power-domain and service-safety decision; implemented net separation in the checked-in power/controller schematics | High | Verify module power pin/topology; select and qualify the regulator, isolation/source-selection method, sequencing, and power-domain implementation. | PCB layout + BOM freeze + Fabrication | | USB-C role | DESIGN DECISION | Programming, debug, recovery, and service only; not the normal installed power source. USB-only MCU power must not energize the gate-driver domain or enable Q1. | Phase-1 service architecture decision | High | Validate every USB-only and mixed-supply power state and observe gate/OE during attach/remove. | PCB layout + Fabrication | | External 5 V/VBUS pin | TBD / BLOCKED | Rev A.4.1 mapping must not substitute for physical verification of the exact module pin. | No actual-module label/circuit verification recorded | High confidence that evidence is missing | Verify the physical pin label, numbering, and electrical connection. | PCB layout + Fabrication | -| USB/external-5 V relationship | TBD / BLOCKED | Unknown whether USB-C VBUS and the external 5 V pin are directly connected, diode-ORed, switched, or otherwise isolated. | No trustworthy revision-matched schematic or circuit inspection | High confidence that evidence is missing | Inspect/trace the actual module and test onboard-only, USB-only, and simultaneous-source behavior. | PCB layout + BOM freeze + Fabrication | +| USB/external-5 V relationship | TBD / BLOCKED | Unknown whether USB-C VBUS and the external 5 V pin are directly connected, diode-ORed, switched, or otherwise isolated. | No trustworthy revision-matched schematic or circuit inspection | High confidence that evidence is missing | On the physical module, measure external-5 V pad-to-USB-VBUS continuity, diode mode both directions, USB-only external-pad voltage, external-5-V-driven USB-C VBUS voltage, and 3V3 behavior in each state. | PCB layout + BOM freeze + Fabrication | | Backfeed protection | TBD / BLOCKED | Reverse-current blocking or explicit source selection is required unless inspection and testing prove it unnecessary. Final implementation may use Schottky OR-ing, an ideal-diode/load-switch arrangement, USB-VBUS isolation, or a service-power selector; no option is selected. | Depends on actual module topology and measured source behavior | High confidence that decision is blocked | Prove that USB cannot backfeed the buck/24 V system, onboard 5 V cannot unexpectedly source a USB host, and supplies cannot contend. | PCB layout + BOM freeze + Fabrication | -| Buck converter | TBD / BLOCKED | No MPN or final rating selected. Must support ESP32-S3 peaks/Wi-Fi bursts, boot transients, shared 74AHCT125 and fan-interface loads, other actual 5 V loads, and engineering margin. | Load inventory and installed thermal environment incomplete | High confidence that selection is blocked | Complete load inventory; evaluate voltage/transient rating, output current, efficiency, dissipation, reverse current, startup, and installed-temperature derating. | PCB layout + BOM freeze + Fabrication | +| Buck converter candidate | STRONG CANDIDATE | TI LMR36520 synchronous buck: published 4.2–65 V input, 2 A output, up to 70 V input transients, −40 to +125 °C operating junction range, and power-good option. The present `MOD1` connector symbol is only an architecture placeholder, not a discrete implementation or BOM-final part. | [TI LMR36520 product page](https://www.ti.com/product/LMR36520) and Phase-1 regulator review | High for published characteristics; medium for product fit | Select exact ordering code and switching frequency; implement and review the complete discrete circuit, magnetics, compensation/support parts, layout, efficiency/dissipation, transient behavior, and installed-temperature derating. | PCB layout + BOM freeze + Fabrication | +| Conditional MCU source selector | STRONG CANDIDATE | TPS2116 is a conditional source-multiplexer candidate only. Its published 1.6–5.5 V, 2.5 A capability, reverse-current blocking, and priority/manual selection are directionally suitable, but it is not placed and cannot be adopted until U2 exposes separately controllable source nodes. | [TI TPS2116 product page](https://www.ti.com/product/TPS2116) and Phase-1 source-topology review | Medium | Prove the physical module VBUS/external-5 V topology first; then determine whether independently selectable inputs and output are actually available. | PCB layout + BOM freeze + Fabrication | | Buck converter capacity target | ASSUMPTION / PROVISIONAL | Use at least 1.5 A continuous capability as an initial converter target. This is not a selected MPN or BOM-final rating. | Preliminary ESP32-S3 peak/burst allowance plus light interface-load margin | Medium | Complete the 5 V load inventory and converter loss/thermal derating at the maximum installed chamber/PCB temperature; increase the rating if required. | PCB layout + BOM freeze + Fabrication | | Power-management firmware assumptions | TBD / BLOCKED | No firmware behavior may assume a source topology or power-good behavior that has not been established in hardware. | Power architecture unresolved | High | Close power-state truth table and any available power-good/reset behavior. | Firmware constants | @@ -90,12 +91,14 @@ temperatures. | Load | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | |---|---|---|---|---|---|---| -| ESP32-S3 Super Mini | TBD / BLOCKED | Budget peak Wi-Fi/boot current, not average current. No revision-matched peak value is frozen. | Exact module power topology and flash/module revision remain unverified | High confidence that a numeric load is missing | Measure boot and radio bursts on the actual module across supported operating conditions. | BOM freeze + Fabrication | -| Gate buffer and Q1 gate charging | TBD / BLOCKED | Include buffer static/dynamic current and Q1 gate-charge current at the eventual switching frequency. Gate drive belongs only to `+5V_SYS/GATE`. | SN74AHCT125 and CSD18540Q5B are not yet qualified as a final combination | High confidence that a numeric load is missing | Select/qualify driver architecture; freeze PWM only after waveform/loss review; measure rail transients. | BOM freeze + Firmware constants + Fabrication | +| ESP32-S3 Super Mini | ASSUMPTION / PROVISIONAL | Allocate approximately 600 mA for module peak/Wi-Fi/boot demand; this is a design allocation, not a measured revision-specific maximum. | Phase-1 provisional load budget; exact module power topology and revision remain unverified | Medium | Measure boot and radio bursts on the actual module across supported operating conditions. | BOM freeze + Fabrication | +| Gate buffer and Q1 gate charging | ASSUMPTION / PROVISIONAL | Allocate less than 20 mA for gate logic and gate charging. Gate drive belongs only to `+5V_SYS_GATE`; actual dynamic current depends on the still-unfrozen PWM frequency and Q1 waveform. | SN74LV4T125/CSD18540Q5B candidate architecture and provisional load budget | Medium-low | Qualify the driver/passives; freeze PWM only after waveform/loss review; measure rail transients and average/peak current. | BOM freeze + Firmware constants + Fabrication | | Fan PWM/tach interface | TBD / BLOCKED | Include open-drain PWM, tach pull-up/interface, and any protection/filter loads; fan motor power remains on fused 24 V. | Four-wire interface architecture; candidate-specific electrical details pending | High confidence that a numeric load is missing | Complete delivered-fan datasheet/bench characterization and select interface values. | BOM freeze + Fabrication | | Sensor/reference support | TBD / BLOCKED | Include every actual 3.3 V/5 V thermistor, reference, ADC-filter, and level-interface load after the sensing implementation is finalized. | Rev A.4.1 sensing architecture is not a frozen load inventory | High confidence that a numeric load is missing | Reconcile final sensing schematic and regulator/LDO efficiencies. | BOM freeze + Fabrication | -| Qwiic and service expansion | ASSUMPTION / PROVISIONAL | Do not consume unbounded regulator margin. If retained, define and enforce an allowed service/expansion load. | Rev A.4.1 includes Qwiic/service provisions but no production load allocation | Medium | Decide retained interfaces and maximum external current; protect and include them in simultaneous worst case. | BOM freeze + Fabrication | -| Converter headroom | ASSUMPTION / PROVISIONAL | At least 1.5 A continuous output remains an iteration floor, not a completed budget or selected regulator. | Phase-1 sizing direction | Medium | Sum measured simultaneous peaks, add explicit engineering margin, and verify converter efficiency/temperature at maximum installed ambient. | PCB layout + BOM freeze + Fabrication | +| Qwiic and service expansion | ASSUMPTION / PROVISIONAL | Allocate up to 250 mA if retained; this is a bounded design allowance, not measured consumption or permission for an unbounded external load. | Rev A.4.1 Qwiic/service provisions and Phase-1 provisional load budget | Medium | Decide retained interfaces and enforce the maximum external current; protect and measure simultaneous worst case. | BOM freeze + Fabrication | +| LED and miscellaneous board logic | ASSUMPTION / PROVISIONAL | Allocate approximately 30 mA. | Preliminary Phase-1 load inventory | Low-medium | Reconcile the final schematic and measure actual simultaneous load. | BOM freeze + Fabrication | +| Other explicit margin allocation | ASSUMPTION / PROVISIONAL | Allocate approximately 50 mA before the final engineering margin. | Preliminary Phase-1 load inventory | Low-medium | Replace with itemized loads as the schematic closes. | BOM freeze + Fabrication | +| Working total and converter headroom | ASSUMPTION / PROVISIONAL | Working allocation is approximately 950 mA before engineering margin. Adding 25–30% gives approximately 1.2–1.25 A, so at least 1.5 A continuous capability remains the provisional floor; the 2 A LMR36520 is the preferred strong candidate. | Sum of provisional allocations above | Medium-low until loads are measured | Sum measured simultaneous peaks and verify converter efficiency, transient response, and temperature at maximum installed ambient. | PCB layout + BOM freeze + Fabrication | ## 4. Heater path and independent interruption @@ -111,9 +114,12 @@ temperatures. |---|---|---|---|---|---|---| | Q1 candidate | STRONG CANDIDATE | Texas Instruments CSD18540Q5B; 60 V logic-level N-MOSFET; maximum `RDS(on)` approximately 3.3 mΩ at 4.5 V. Not BOM-final. | Manufacturer data and Phase-1 component review | High for published characteristics | Reconfirm ordering code, lifecycle, package, pin/multipad mapping, and production availability. | PCB layout + BOM freeze + Fabrication | | Estimated Q1 conduction loss | ASSUMPTION / PROVISIONAL | About 0.205 W at 7.89 A and 0.229 W at 8.33 A using 3.3 mΩ: `P = I²R`. These are max-`RDS(on)`-basis conduction estimates only, not total hot operating loss. | Candidate data and measured/design currents | Medium | Include hot `RDS(on)`, switching loss, duty/frequency, gate waveform, copper spreading, and measured junction/board temperature. | PCB layout + BOM freeze + Firmware constants + Fabrication | -| Rev A.4.1 gate buffer | CONFIRMED FACT | Rev A.4.1 uses an SN74AHCT125 for gate buffering, and the used output-enable inputs are tied low. TI documents OE high as disabled/high-impedance and specifically recommends an OE-to-VCC pull-up for high impedance during power-up/down. The reviewed catalog/datasheet material does not state an `Ioff` partial-power-down guarantee. | [Checked-in Rev A.4.1 schematic](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch); [TI SN74AHCT125 product/datasheet page](https://www.ti.com/product/SN74AHCT125) | High | Reinspect after correction and verify channel mapping, OE pull-up behavior, and powered/unpowered input/output leakage. | PCB layout + Fabrication | -| Gate network concept | ASSUMPTION / PROVISIONAL | Provisional 47 Ω gate resistor and a direct Q1 gate pull-down. The direct pull-down must be retained independently of MCU and buffer state. | Current Rev A.4.1 schematic concept and Phase-1 default-OFF requirement | Medium | Select the pull-down value and gate resistance from leakage, turn-off, waveform, PWM, and switching-loss validation. | PCB layout + BOM freeze + Firmware constants + Fabrication | -| Required gate-drive correction | DESIGN DECISION | Heater gate drive must be hardware-default-disabled through power-up, power-down, reset, brownout, partial power, USB-only service, and supply sequencing. Power the driver only from `+5V_SYS/GATE`; bias each used active-low OE high to its own rail by hardware; retain the direct Q1 gate pull-down; isolate a USB-powered MCU from an unpowered driver using documented partial-power-down behavior or equivalent circuitry. Add test points for `+5V_SYS/GATE`, `+5V_MCU`, OE, Q1 gate, and Q1 source reference. No replacement driver is BOM-final. | Phase-1 power/backfeed review and TI OE guidance | High | Revise the schematic; determine whether SN74AHCT125 can be retained after leakage/sequencing qualification or select a documented alternative; verify Q1 gate voltage through all 24 V/USB/reset transitions. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Rev A.4.1 gate-buffer defect | CONFIRMED FACT | The authoritative Rev A.4.1 baseline used SN74AHCT125 buffering with the used active-low OE inputs tied low, so enable was not hardware-default-disabled. The Phase-1 power sheet now supersedes that implementation while preserving this row as baseline evidence. | [Checked-in Phase-1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch); [TI SN74AHCT125 product page](https://www.ti.com/product/SN74AHCT125) | High | Preserve provenance and verify the replacement behavior natively and on the bench. | Fabrication | +| Gate-buffer candidate | STRONG CANDIDATE | SN74LV4T125 in TSSOP-14 is the production-intent candidate. TI publishes 1.8–5.5 V operation, 5.5 V-tolerant inputs, translation support, active-low OE, −40 to +125 °C operation, and `Ioff` partial-power-down support. It is powered only by `+5V_SYS_GATE`; it is not BOM-final. | [TI SN74LV4T125 product page](https://www.ti.com/product/SN74LV4T125) and implemented Phase-1 schematic | High for published characteristics; medium for final selection | Verify exact ordering code, pin mapping/library symbol, input thresholds at 3.3 V, leakage, timing, output drive, gate waveform, and installed-temperature behavior. | PCB layout + BOM freeze + Fabrication | +| Default-disabled OE architecture | DESIGN DECISION | `R20` provisionally pulls heater-channel `/OE` to `+5V_SYS_GATE`. `Q4` (`Q_GATE_EN`, provisional 2N7002-class device) can pull `/OE` low only when generic unassigned net `HEATER_GATE_EN` is asserted. Its gate has a direct pull-down. MCU reset/high-Z/unpowered/disconnected therefore leaves the driver disabled. Unused buffer channels are held disabled, and USB-only power cannot energize the gate-driver rail. | Implemented Phase-1 power/output schematic and TI active-low OE/Ioff behavior | High for intended topology | Run the mandatory 24 V/USB/reset/brownout/attach/remove transition matrix while observing both rails, OE, PWM input, Q1 gate, and source reference. Verify Q4 leakage and resistor values at temperature. | PCB layout + BOM freeze + Fabrication | +| Heater PWM command path | DESIGN DECISION | Generic unassigned `HEATER_PWM_CMD` feeds the U1 A input with a direct input pull-down; no MCU pin is assigned. U1 `Ioff` is intended to prevent back-power through this input while its VCC is absent. U1 Y drives `HTR_GATE` through the provisional series resistor. | Implemented Phase-1 power/output schematic | High for topology | Verify unpowered leakage, logic levels, transitions, and gate waveform on representative hardware. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Gate network values | ASSUMPTION / PROVISIONAL | `R1` is 47 Ω provisional; the direct Q1 gate pull-down `R2` is 10 kΩ provisional; the PWM-input pull-down remains 100 kΩ provisional. The stronger Q1 pull-down improves deterministic turnoff while dissipating only milliwatts when driven high. | CSD18540Q5B maximum gate charge is approximately 26 nC at 4.5 V; Phase-1 leakage/turnoff review | Medium | Select final resistance from leakage, turn-off, gate waveform, PWM frequency, switching loss, and driver-current validation. | PCB layout + BOM freeze + Firmware constants + Fabrication | +| Gate/power test points | DESIGN DECISION | `TP11`–`TP16` expose `+5V_SYS_GATE`, `+5V_MCU`, heater `/OE`, `HEATER_PWM_CMD`, Q1 gate, and Q1 source reference. No USB-VBUS test point was invented because no safe explicit module net has been proven. | Implemented Phase-1 power/output schematic | High | Verify footprint accessibility and use all points in the power-transition bench matrix. | PCB layout + Fabrication | | Q1 footprint and thermal implementation | TBD / BLOCKED | Exact verified KiCad footprint, thermal-pad implementation, and copper spreading are not frozen. | Footprint/PCB validation not completed | High confidence that implementation is incomplete | Verify package drawing and pad mapping; complete thermal/current layout and measurement plan. | PCB layout + Fabrication | | Rev A.4.1 Q1 mapping defect | CONFIRMED FACT | Q1 currently uses a generic `Q_NMOS_GDS` symbol and unresolved `Package_DirectFET:TBD` footprint. CSD18540Q5B is published as an 8-pin 5 mm × 6 mm VSON-CLIP (DNK), so the current footprint assignment cannot represent the candidate package or multipad mapping. | [Rev A.4.1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch); [TI CSD18540Q5B product/datasheet page](https://www.ti.com/product/CSD18540Q5B) | High | Build/verify the exact DNK symbol-to-pad mapping, exposed/current pads, land pattern, solder treatment, and thermal copper against the manufacturer drawing. | PCB layout + BOM freeze + Fabrication | @@ -187,7 +193,7 @@ identify a valid production cutoff temperature or mounting location. | KiCad source schema/validation | ASSUMPTION / PROVISIONAL | Root schematic declares schema `20211014`/generator `kiutils`; child sheets declare `20260306`/custom generator; footprint files declare `20240108`. Hierarchical filenames and project-local library paths resolve by static inspection, but native application open/ERC has not been run in this environment. | File headers, root-sheet references, and library tables | High for observed metadata; medium for openability | Open/save only after review, verify no unintended migration diff, resolve all libraries, then run native ERC. | PCB layout + Fabrication | | Unresolved footprint references | TBD / BLOCKED | Rev A.4.1 intentionally contains unresolved placeholders `TBD:High_Current_2Pin`, `TBD:DC_DC_Module`, `TBD:Aux_2Pin`, and `Package_DirectFET:TBD`. Standard-library and project-local non-placeholder names were identified, but native library resolution is not yet proven. | Static scan of checked-in schematic footprint properties | High | Replace every placeholder with a verified project/standard footprint and run native library resolution/ERC before PCB import. | PCB layout + BOM freeze + Fabrication | | Preliminary archive BOM | CONFIRMED FACT | `BOM_PRELIMINARY.csv` is checked in as source context only. Its placeholders and historical values do not override this register and are not BOM-final. | [Rev A.4.1 preliminary BOM](../hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv) | High | Reconcile every line against reviewed schematic candidates and replace with a controlled production BOM later. | BOM freeze + Fabrication | -| J1/F1/MOD1 implementation | TBD / BLOCKED | Rev A.4.1 uses `J1` value `24V IN / 20A MIN` with placeholder footprint `TBD:High_Current_2Pin`; `F1` value `15A TBD` with no footprint; and `MOD1` value `24V→5V BUCK TBD` with placeholder footprint `TBD:DC_DC_Module`. These are schematic placeholders, not selections. | [Checked-in Rev A.4.1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) and preliminary BOM | High | Select/qualify exact input connector, main protection, and regulator architecture/parts; verify footprints, service/thermal behavior, transients, and PSU/fuse coordination. | PCB layout + BOM freeze + Fabrication | +| J1/F1/MOD1 implementation | TBD / BLOCKED | `J1` remains `24V IN / 20A MIN` with placeholder footprint `TBD:High_Current_2Pin`; `F1` remains `15A TBD` with no footprint. `MOD1` now records LMR36520 as the strong-candidate buck architecture and outputs only `+5V_SYS_GATE`, but its connector symbol and `TBD:DC_DC_Module` footprint are explicitly placeholders rather than a discrete implementation. | [Checked-in Phase-1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) and preliminary BOM | High | Select/qualify exact input connector and main protection; implement the complete LMR36520 candidate circuit and verified footprints; validate service/thermal behavior, transients, and PSU/fuse coordination. | PCB layout + BOM freeze + Fabrication | | Starting stackup | ASSUMPTION / PROVISIONAL | Two layers, 1.6 mm FR-4, 2 oz copper. | Phase-1 routing/current-density starting point | Medium | Review high-current routing, grounding, RF, mechanical, thermal, cost, and PCBWay manufacturing requirements before freeze. | PCB layout + BOM freeze + Fabrication | | Heater-path copper geometry | ASSUMPTION / PROVISIONAL | Keep heater-path neckdowns at least 4 mm as an initial minimum; prefer broad 8–10 mm or wider pours where practical; minimize vias and unnecessary current-loop area. Place the high-current/safety path before convenience circuitry. | 8.33 A conservative design basis and Phase-1 layout direction | Medium | Calculate and inspect every bottleneck, layer transition, pad entry, thermal relief, and temperature rise for the final stackup. | PCB layout + Fabrication | | Ground and return strategy | DESIGN DECISION | Prefer a continuous ground plane with a controlled heater/fan/buck high-current return corridor. Thermistor/ADC returns must not share narrow or common-impedance copper with heater current. Do not create arbitrary split grounds that damage ESP32 RF return integrity. | Phase-1 signal-integrity and current-return strategy | High for topology; implementation provisional | Review actual return geometry, buck loops, ADC noise, RF keepout, and current-path coupling after placement/routing. | PCB layout + Fabrication | @@ -211,12 +217,12 @@ bounded by reviewed production-intent provisions: - optional locating holes must be physically fit-verified or deliberately omitted before footprint freeze - external 5 V / USB-C VBUS topology - USB/onboard mixed-source and backfeed testing -- hardware-default-OFF gate-driver schematic correction -- complete regulator load inventory and installed-temperature thermal analysis +- bench validation of the implemented hardware-default-OFF gate-driver correction across the complete power-transition matrix +- complete regulator implementation, load measurement, and installed-temperature thermal analysis - Q1 multipad/footprint and F2 holder-footprint verification - four-wire fan connector/interface footprint and candidate electrical verification; schematic provisions are implemented but not natively ERC-validated - TF1/TS1 part, mounting, and thermal-coupling implementation -- J1, F1, and MOD1 part and footprint selections +- J1/F1 selections and footprints; MOD1 discrete-regulator implementation and footprint - PCB envelope, mounting-hole coordinates, connector-facing edges, and USB datum - final 1:1 production-footprint fit check with the actual module - native KiCad project-open/library-resolution check and ERC From fd764834674a56b22fc2d2da52b249cdd289d848 Mon Sep 17 00:00:00 2001 From: Daniel Brown <30573097+danielbrownjr@users.noreply.github.com> Date: Mon, 7 Sep 2026 03:10:38 -0700 Subject: [PATCH 12/20] docs: complete regulator candidate evidence --- docs/PHASE1_HARDWARE_REGISTER.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index 8c0dc8a..4cc726f 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -82,7 +82,7 @@ temperatures. | External 5 V/VBUS pin | TBD / BLOCKED | Rev A.4.1 mapping must not substitute for physical verification of the exact module pin. | No actual-module label/circuit verification recorded | High confidence that evidence is missing | Verify the physical pin label, numbering, and electrical connection. | PCB layout + Fabrication | | USB/external-5 V relationship | TBD / BLOCKED | Unknown whether USB-C VBUS and the external 5 V pin are directly connected, diode-ORed, switched, or otherwise isolated. | No trustworthy revision-matched schematic or circuit inspection | High confidence that evidence is missing | On the physical module, measure external-5 V pad-to-USB-VBUS continuity, diode mode both directions, USB-only external-pad voltage, external-5-V-driven USB-C VBUS voltage, and 3V3 behavior in each state. | PCB layout + BOM freeze + Fabrication | | Backfeed protection | TBD / BLOCKED | Reverse-current blocking or explicit source selection is required unless inspection and testing prove it unnecessary. Final implementation may use Schottky OR-ing, an ideal-diode/load-switch arrangement, USB-VBUS isolation, or a service-power selector; no option is selected. | Depends on actual module topology and measured source behavior | High confidence that decision is blocked | Prove that USB cannot backfeed the buck/24 V system, onboard 5 V cannot unexpectedly source a USB host, and supplies cannot contend. | PCB layout + BOM freeze + Fabrication | -| Buck converter candidate | STRONG CANDIDATE | TI LMR36520 synchronous buck: published 4.2–65 V input, 2 A output, up to 70 V input transients, −40 to +125 °C operating junction range, and power-good option. The present `MOD1` connector symbol is only an architecture placeholder, not a discrete implementation or BOM-final part. | [TI LMR36520 product page](https://www.ti.com/product/LMR36520) and Phase-1 regulator review | High for published characteristics; medium for product fit | Select exact ordering code and switching frequency; implement and review the complete discrete circuit, magnetics, compensation/support parts, layout, efficiency/dissipation, transient behavior, and installed-temperature derating. | PCB layout + BOM freeze + Fabrication | +| Buck converter candidate | STRONG CANDIDATE | TI LMR36520 synchronous buck: published 4.2–65 V input, 2 A output, up to 70 V input transients, −40 to +125 °C operating junction range, power-good option, and approximately 90% published efficiency at 24 V input, 5 V output, and 1 A. The present `MOD1` connector symbol is only an architecture placeholder, not a discrete implementation or BOM-final part. | [TI LMR36520 product page](https://www.ti.com/product/LMR36520) and Phase-1 regulator review | High for published characteristics; medium for product fit | Select exact ordering code and switching frequency; implement and review the complete discrete circuit, magnetics, compensation/support parts, layout, efficiency/dissipation, transient behavior, and installed-temperature derating. | PCB layout + BOM freeze + Fabrication | | Conditional MCU source selector | STRONG CANDIDATE | TPS2116 is a conditional source-multiplexer candidate only. Its published 1.6–5.5 V, 2.5 A capability, reverse-current blocking, and priority/manual selection are directionally suitable, but it is not placed and cannot be adopted until U2 exposes separately controllable source nodes. | [TI TPS2116 product page](https://www.ti.com/product/TPS2116) and Phase-1 source-topology review | Medium | Prove the physical module VBUS/external-5 V topology first; then determine whether independently selectable inputs and output are actually available. | PCB layout + BOM freeze + Fabrication | | Buck converter capacity target | ASSUMPTION / PROVISIONAL | Use at least 1.5 A continuous capability as an initial converter target. This is not a selected MPN or BOM-final rating. | Preliminary ESP32-S3 peak/burst allowance plus light interface-load margin | Medium | Complete the 5 V load inventory and converter loss/thermal derating at the maximum installed chamber/PCB temperature; increase the rating if required. | PCB layout + BOM freeze + Fabrication | | Power-management firmware assumptions | TBD / BLOCKED | No firmware behavior may assume a source topology or power-good behavior that has not been established in hardware. | Power architecture unresolved | High | Close power-state truth table and any available power-good/reset behavior. | Firmware constants | From c92629991c8169c72554ec7bcb8ba0da7af5ae60 Mon Sep 17 00:00:00 2001 From: Daniel Brown Date: Tue, 8 Sep 2026 11:25:00 -0400 Subject: [PATCH 13/20] hardware: require physical MCU service disconnect --- ROADMAP.md | 3 ++ TODO.md | 8 ++++- docs/HARDWARE_BASELINE.md | 33 ++++++++++++++++--- docs/PHASE1_HARDWARE_REGISTER.md | 22 +++++++------ docs/PRODUCT_SAFETY_CONTRACT.md | 6 ++++ .../kicad/JumpJet_RevA/BOM_PRELIMINARY.csv | 2 +- .../JumpJet_RevA/JumpJet_Controller.kicad_sch | 2 +- .../JumpJet_Power_Outputs.kicad_sch | 4 +-- hardware/kicad/JumpJet_RevA/README.md | 8 +++++ 9 files changed, 68 insertions(+), 20 deletions(-) diff --git a/ROADMAP.md b/ROADMAP.md index 7db0456..b448c7c 100644 --- a/ROADMAP.md +++ b/ROADMAP.md @@ -25,6 +25,9 @@ no phase passes its gate without the listed evidence. - freeze the hardware contract and create/review the first Rev A PCB during Phase 1 - review the BOM, enclosure, mechanical interfaces, and airflow path - confirm the exact ESP32-S3 Super Mini revision, flash size, GPIO map, and boot-strap constraints +- implement a physically accessible, visibly labeled disconnect between + board-derived MCU 5 V and the Super Mini's directly coupled 5 V/USB-VBUS node; + seamless simultaneous board/USB power is out of scope for Rev A - identify heater, MOSFET, characterized four-wire fan channel, thermistors, connectors, fuses, thermal cutoff, and switch - characterize the prototype fan before freezing interface-derived firmware diff --git a/TODO.md b/TODO.md index 3d10578..a978a0d 100644 --- a/TODO.md +++ b/TODO.md @@ -51,7 +51,10 @@ implementation starts, and keep only the summary checkbox here. - [x] Measure the ESP32 USB-C shell envelope - [ ] Measure the USB-C mating-plug/cable-head envelope and define carrier-edge, enclosure, and service-access clearances -- [ ] Establish the external 5 V / USB-C VBUS topology and mixed-source backfeed behavior +- [x] Establish the external 5 V / USB-C VBUS topology: the actual Super Mini's + exposed 5 V pin and USB VBUS are directly coupled for system-design purposes +- [ ] Select, rate, and place the Rev A physical board-5-V disconnect; verify USB + access, service labeling, jumper/switch clearance, retention, and misuse visibility - [ ] Verify the Q1 footprint and multipad mapping - [ ] Verify the F2 holder footprint and service/removal clearance - [ ] Select TF1/TS1 parts and their mounting/thermal-coupling architecture @@ -86,6 +89,9 @@ implementation starts, and keep only the summary checkbox here. - [ ] Calculate MOSFET conduction and switching loss at worst-case voltage, current, duty, and ambient - [x] Implement separate `+5V_SYS_GATE` / `+5V_MCU` schematic domains and a hardware-default-disabled heater-driver OE topology +- [ ] Implement the adopted physical disconnect between board-derived MCU 5 V + and the Super Mini-side `+5V_MCU` / USB-VBUS tied node; removable jumper/shunt + is preferred but its part, rating, and footprint remain unresolved - [ ] Bench-verify that USB/service power cannot energize the gate-driver domain or Q1 through every power-up, power-down, reset, brownout, and mixed-source state - [ ] Verify gate-driver partial-power-down behavior or provide equivalent isolation diff --git a/docs/HARDWARE_BASELINE.md b/docs/HARDWARE_BASELINE.md index 233f2f9..7774656 100644 --- a/docs/HARDWARE_BASELINE.md +++ b/docs/HARDWARE_BASELINE.md @@ -26,9 +26,19 @@ or authorize heater actuation. two-wire block is retained as baseline evidence, not production intent. - Published prototype facts and pending measurements are tracked in the [9GA0424P3J001 characterization record](hardware/9ga0424p3j001-characterization.md). -- Phase-1 schematic work now separates a protected-24-V-derived - `+5V_SYS_GATE` rail from the unresolved `+5V_MCU` service/source-selected - domain. The gate buffer cannot be powered from USB-only MCU power. +- Phase-1 schematic work separates the protected-24-V-derived + `+5V_SYS_GATE` actuator rail from the MCU logic domain. Bench measurements of + the actual Super Mini establish that its USB VBUS and exposed 5 V pin are one + effectively direct, bidirectional node: 4.993 V applied to the pin produced + 4.992 V at VBUS; USB at 5.13 V produced 5.11 V at the pin; unpowered + continuity was confirmed. +- Rev A therefore requires mutually exclusive installed/USB service power at + the module node. Board-derived MCU 5 V reaches the module only through a + physical disconnect that must be opened before powered USB attachment. A + removable jumper/shunt is preferred, but its part and footprint are not yet + selected. Seamless simultaneous source operation is out of scope. +- USB shall not be routed through the carrier and must never source `+5V_SYS_GATE`. + The gate buffer cannot be powered from USB-only MCU power. - The heater driver now uses a hardware-default-disabled active-low OE topology: an OE pull-up holds the driver disabled unless a separate open-drain enable transistor is explicitly asserted. Generic `HEATER_GATE_EN` and @@ -39,10 +49,23 @@ or authorize heater actuation. Q1, F2, PCB copper, connectors, wiring, installed airflow, the exact ESP32-S3 module implementation, and the complete power path have not been validated together. The LMR36520 and SN74LV4T125 are strong candidates, not BOM-final; -the regulator circuit, `+5V_MCU` source selection, reverse-current behavior, -and full power-transition bench matrix remain open. The upstream Jetpack pin +the regulator circuit, physical MCU service-disconnect implementation and rating, +disconnect accessibility/labeling, and full power-transition bench matrix remain +open. TPS2116-only automatic source selection is superseded because the module +has no separately controllable USB and exposed-5-V nodes. The upstream Jetpack pin assignments are historical facts, not Jump Jet assignments. +## Rev A MCU service-power states + +| State | Physical disconnect | Required outcome | +|---|---|---| +| Normal 24 V operation; USB absent | Closed | Board-derived MCU 5 V powers the Super Mini. `+5V_SYS_GATE` remains an independent 24-V-only actuator rail; firmware safety still controls actuation. | +| USB service; 24 V absent | Open before USB attachment | USB powers only the Super Mini-side MCU logic node. Gate power is absent and the heater is physically incapable. | +| USB service; 24 V present | Open before USB attachment | USB powers the MCU node; `+5V_SYS_GATE` may exist from 24 V but remains isolated and the default-disabled gate/OE architecture keeps the heater off unless every normal hardware and firmware condition is valid. | +| Disconnect mistakenly closed while powered USB is attached | Invalid/misuse | Board 5 V and host VBUS can contend or backfeed. Silkscreen and accessible disconnect geometry must make this misuse obvious; Rev A does not promise safe seamless coexistence. | +| USB removed while 24 V absent | Open | MCU loses power cleanly; no actuator domain may remain energized from USB capacitance or another path. | +| 24 V removed while USB remains | Open | MCU may remain alive, but `+5V_SYS_GATE` collapses independently and firmware must truthfully report heater actuation unavailable. | + No GPIO, ADC, divider, thermistor conversion, protection threshold, thermal trip, cooldown criterion, or recovery threshold may be finalized without corresponding source files and measured evidence. Fan interface values, production fan, diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index 4cc726f..bf90a00 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -77,15 +77,17 @@ temperatures. | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | |---|---|---|---|---|---|---| -| Production power domains | DESIGN DECISION | Protected 24 V feeds the onboard buck and its exclusive `+5V_SYS_GATE` output. That rail powers heater gate-drive circuitry and is never USB-sourced. A separately isolated or source-selected `+5V_MCU` domain feeds the ESP32-S3 Super Mini external 5 V/VBUS input. Raw 24 V must never reach the module, and USB-only MCU power must be physically incapable of powering the gate rail. | Phase-1 power-domain and service-safety decision; implemented net separation in the checked-in power/controller schematics | High | Verify module power pin/topology; select and qualify the regulator, isolation/source-selection method, sequencing, and power-domain implementation. | PCB layout + BOM freeze + Fabrication | -| USB-C role | DESIGN DECISION | Programming, debug, recovery, and service only; not the normal installed power source. USB-only MCU power must not energize the gate-driver domain or enable Q1. | Phase-1 service architecture decision | High | Validate every USB-only and mixed-supply power state and observe gate/OE during attach/remove. | PCB layout + Fabrication | -| External 5 V/VBUS pin | TBD / BLOCKED | Rev A.4.1 mapping must not substitute for physical verification of the exact module pin. | No actual-module label/circuit verification recorded | High confidence that evidence is missing | Verify the physical pin label, numbering, and electrical connection. | PCB layout + Fabrication | -| USB/external-5 V relationship | TBD / BLOCKED | Unknown whether USB-C VBUS and the external 5 V pin are directly connected, diode-ORed, switched, or otherwise isolated. | No trustworthy revision-matched schematic or circuit inspection | High confidence that evidence is missing | On the physical module, measure external-5 V pad-to-USB-VBUS continuity, diode mode both directions, USB-only external-pad voltage, external-5-V-driven USB-C VBUS voltage, and 3V3 behavior in each state. | PCB layout + BOM freeze + Fabrication | -| Backfeed protection | TBD / BLOCKED | Reverse-current blocking or explicit source selection is required unless inspection and testing prove it unnecessary. Final implementation may use Schottky OR-ing, an ideal-diode/load-switch arrangement, USB-VBUS isolation, or a service-power selector; no option is selected. | Depends on actual module topology and measured source behavior | High confidence that decision is blocked | Prove that USB cannot backfeed the buck/24 V system, onboard 5 V cannot unexpectedly source a USB host, and supplies cannot contend. | PCB layout + BOM freeze + Fabrication | +| Production power domains | DESIGN DECISION | Protected 24 V feeds separate board-derived paths: exclusive `+5V_SYS_GATE` for heater gate-drive circuitry and a board MCU 5 V path. The board MCU path reaches the Super Mini `+5V_MCU`/USB-VBUS tied node only through a deliberate physical service disconnect. USB is never routed to `+5V_SYS_GATE`. Raw 24 V must never reach the module, and USB-only MCU power must be physically incapable of powering any actuator domain. | Phase-1 power-domain and service-safety decision; implemented gate/MCU net separation; measured module 5 V topology | High | Implement and qualify the board MCU regulator path and disconnect; verify all normal, USB-service, mixed-presence, reset, and brownout states. | PCB layout + BOM freeze + Fabrication | +| USB-C role | DESIGN DECISION | Programming, debug, recovery, and service only; not the normal installed power source. Board-derived MCU 5 V must be physically disconnected before attaching a powered USB host. USB may power only the Super Mini-side MCU logic node and must not energize `+5V_SYS_GATE`, the gate driver, or Q1 actuation. | Phase-1 service architecture and measured bidirectional VBUS/5 V coupling | High | Validate every USB-only and mixed-presence power state and observe both 5 V sides, gate rail, OE, PWM input, and Q1 gate during attach/remove. | PCB layout + Fabrication | +| External 5 V/VBUS pin | MEASURED | USB VBUS and the Super Mini exposed 5 V pin are effectively the same node for system design. With 4.993 V applied at the exposed pin, USB VBUS measured 4.992 V. With USB supplied at 5.13 V, the exposed pin measured 5.11 V. Unpowered continuity was confirmed and diode-mode behavior was consistent with direct coupling. | Direct bench characterization of the actual ESP32-S3 Super Mini | High for the tested module | Preserve the measured topology in the schematic and validate production-module consistency during receiving/bring-up. | None | +| USB/external-5 V relationship | CONFIRMED FACT | The Super Mini provides no usable isolation between USB VBUS and its exposed 5 V pin. USB powers the exposed pin, and external 5 V on that pin energizes the USB connector VBUS. Simultaneous board-derived 5 V and a powered USB host must be treated as unsafe unless one source is physically isolated before the tied module node. | Bidirectional voltage and unpowered continuity measurements on the actual module | High | Do not perform simultaneous-source testing with the disconnect closed. Verify the completed carrier implements the required isolation boundary. | PCB layout + Fabrication | +| Physical MCU service-power disconnect | DESIGN DECISION | Rev A shall place a firmware-independent physical disconnect between board-derived MCU 5 V (`BOARD_5V_MCU` conceptually) and the Super Mini-side `+5V_MCU`/USB-VBUS tied node. Normal operation uses the disconnect closed and USB absent. USB service requires the disconnect open before host attachment. Seamless simultaneous USB plus board MCU power is out of scope for Rev A. | Measured module topology and explicit Rev A service policy | High for architecture; implementation unresolved | Select and rate the disconnect after measuring MCU-path current; verify footprint, voltage drop, accessibility near USB, connector clearance, labeling, retention, and misuse visibility. | PCB layout + BOM freeze + Fabrication | +| Disconnect implementation | STRONG CANDIDATE | A removable jumper/shunt is the narrowest preferred implementation. A serviceable removable link, slide switch, or two-position selector remains fallback if current, mechanical, or service review rejects the jumper. No part, footprint, current rating, or standoff/clearance is frozen. | Rev A simplicity, auditability, and service requirements | Medium-high | Measure module current including boot/Wi-Fi bursts; select a rated part and footprint; prove access and clearance in the aligned mechanical model and 1:1 mockup. | PCB layout + BOM freeze + Fabrication | +| MCU service labeling | DESIGN DECISION | The disconnect and USB service area require unambiguous board labeling that tells a technician to open the board-MCU 5 V path before connecting powered USB. Candidate semantics are `MCU POWER`, `USB SERVICE`, and `OPEN FOR USB`; exact wording, placement, and orientation remain unresolved until the service geometry is known. | Rev A mutually exclusive service-power policy | High for requirement; implementation unresolved | Verify the final silkscreen is visible with the product service-access path open, cannot be mistaken for an actuator jumper, and remains legible after assembly. | PCB layout + Fabrication | +| TPS2116-only source-mux direction | CONFIRMED FACT | Superseded and not sufficient as a USB/external-5 V coexistence solution. A carrier-side TPS2116 cannot independently select USB VBUS versus the exposed module 5 V pin because those nodes are already directly coupled on the Super Mini. TPS2116 is not required by the adopted Rev A mutually exclusive service-power architecture. | Measured module topology compared with [TI TPS2116 product behavior](https://www.ti.com/product/TPS2116) | High | Reconsider only for a narrower future requirement with genuinely separate source nodes; do not place it for Rev A without such a requirement. | None | | Buck converter candidate | STRONG CANDIDATE | TI LMR36520 synchronous buck: published 4.2–65 V input, 2 A output, up to 70 V input transients, −40 to +125 °C operating junction range, power-good option, and approximately 90% published efficiency at 24 V input, 5 V output, and 1 A. The present `MOD1` connector symbol is only an architecture placeholder, not a discrete implementation or BOM-final part. | [TI LMR36520 product page](https://www.ti.com/product/LMR36520) and Phase-1 regulator review | High for published characteristics; medium for product fit | Select exact ordering code and switching frequency; implement and review the complete discrete circuit, magnetics, compensation/support parts, layout, efficiency/dissipation, transient behavior, and installed-temperature derating. | PCB layout + BOM freeze + Fabrication | -| Conditional MCU source selector | STRONG CANDIDATE | TPS2116 is a conditional source-multiplexer candidate only. Its published 1.6–5.5 V, 2.5 A capability, reverse-current blocking, and priority/manual selection are directionally suitable, but it is not placed and cannot be adopted until U2 exposes separately controllable source nodes. | [TI TPS2116 product page](https://www.ti.com/product/TPS2116) and Phase-1 source-topology review | Medium | Prove the physical module VBUS/external-5 V topology first; then determine whether independently selectable inputs and output are actually available. | PCB layout + BOM freeze + Fabrication | | Buck converter capacity target | ASSUMPTION / PROVISIONAL | Use at least 1.5 A continuous capability as an initial converter target. This is not a selected MPN or BOM-final rating. | Preliminary ESP32-S3 peak/burst allowance plus light interface-load margin | Medium | Complete the 5 V load inventory and converter loss/thermal derating at the maximum installed chamber/PCB temperature; increase the rating if required. | PCB layout + BOM freeze + Fabrication | -| Power-management firmware assumptions | TBD / BLOCKED | No firmware behavior may assume a source topology or power-good behavior that has not been established in hardware. | Power architecture unresolved | High | Close power-state truth table and any available power-good/reset behavior. | Firmware constants | +| Power-management firmware assumptions | TBD / BLOCKED | Firmware may rely on the architectural fact that USB cannot power the actuator rail, but may not assume the physical disconnect position, board-5-V availability, power-good behavior, or heater availability without truthful hardware evidence. When 24 V is removed while USB remains, MCU logic may stay alive but heater actuation must be reported unavailable. | Adopted Rev A power-domain architecture; disconnect sensing and power-good implementation unresolved | High | Close the implemented power-state truth table and determine whether disconnect position and board/gate-rail availability are observable. | Firmware constants | ### Provisional 5 V load inventory @@ -119,7 +121,7 @@ temperatures. | Default-disabled OE architecture | DESIGN DECISION | `R20` provisionally pulls heater-channel `/OE` to `+5V_SYS_GATE`. `Q4` (`Q_GATE_EN`, provisional 2N7002-class device) can pull `/OE` low only when generic unassigned net `HEATER_GATE_EN` is asserted. Its gate has a direct pull-down. MCU reset/high-Z/unpowered/disconnected therefore leaves the driver disabled. Unused buffer channels are held disabled, and USB-only power cannot energize the gate-driver rail. | Implemented Phase-1 power/output schematic and TI active-low OE/Ioff behavior | High for intended topology | Run the mandatory 24 V/USB/reset/brownout/attach/remove transition matrix while observing both rails, OE, PWM input, Q1 gate, and source reference. Verify Q4 leakage and resistor values at temperature. | PCB layout + BOM freeze + Fabrication | | Heater PWM command path | DESIGN DECISION | Generic unassigned `HEATER_PWM_CMD` feeds the U1 A input with a direct input pull-down; no MCU pin is assigned. U1 `Ioff` is intended to prevent back-power through this input while its VCC is absent. U1 Y drives `HTR_GATE` through the provisional series resistor. | Implemented Phase-1 power/output schematic | High for topology | Verify unpowered leakage, logic levels, transitions, and gate waveform on representative hardware. | PCB layout + BOM freeze + Firmware constants + Fabrication | | Gate network values | ASSUMPTION / PROVISIONAL | `R1` is 47 Ω provisional; the direct Q1 gate pull-down `R2` is 10 kΩ provisional; the PWM-input pull-down remains 100 kΩ provisional. The stronger Q1 pull-down improves deterministic turnoff while dissipating only milliwatts when driven high. | CSD18540Q5B maximum gate charge is approximately 26 nC at 4.5 V; Phase-1 leakage/turnoff review | Medium | Select final resistance from leakage, turn-off, gate waveform, PWM frequency, switching loss, and driver-current validation. | PCB layout + BOM freeze + Firmware constants + Fabrication | -| Gate/power test points | DESIGN DECISION | `TP11`–`TP16` expose `+5V_SYS_GATE`, `+5V_MCU`, heater `/OE`, `HEATER_PWM_CMD`, Q1 gate, and Q1 source reference. No USB-VBUS test point was invented because no safe explicit module net has been proven. | Implemented Phase-1 power/output schematic | High | Verify footprint accessibility and use all points in the power-transition bench matrix. | PCB layout + Fabrication | +| Gate/power test points | DESIGN DECISION | Existing `TP11`–`TP16` expose `+5V_SYS_GATE`, the Super Mini-side `+5V_MCU`/USB-VBUS tied node, heater `/OE`, `HEATER_PWM_CMD`, Q1 gate, and Q1 source reference. Add an accessible board-side MCU 5 V test point before the physical disconnect if board space permits, so both sides can be observed without treating USB VBUS as isolated. | Implemented Phase-1 power/output schematic plus measured module topology | High for existing points; board-side point provisional | Verify footprint accessibility and use both sides of the disconnect plus all gate points in the power-transition bench matrix. | PCB layout + Fabrication | | Q1 footprint and thermal implementation | TBD / BLOCKED | Exact verified KiCad footprint, thermal-pad implementation, and copper spreading are not frozen. | Footprint/PCB validation not completed | High confidence that implementation is incomplete | Verify package drawing and pad mapping; complete thermal/current layout and measurement plan. | PCB layout + Fabrication | | Rev A.4.1 Q1 mapping defect | CONFIRMED FACT | Q1 currently uses a generic `Q_NMOS_GDS` symbol and unresolved `Package_DirectFET:TBD` footprint. CSD18540Q5B is published as an 8-pin 5 mm × 6 mm VSON-CLIP (DNK), so the current footprint assignment cannot represent the candidate package or multipad mapping. | [Rev A.4.1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch); [TI CSD18540Q5B product/datasheet page](https://www.ti.com/product/CSD18540Q5B) | High | Build/verify the exact DNK symbol-to-pad mapping, exposed/current pads, land pattern, solder treatment, and thermal copper against the manufacturer drawing. | PCB layout + BOM freeze + Fabrication | @@ -215,8 +217,8 @@ bounded by reviewed production-intent provisions: - antenna identity and conservative pre-fabrication keepout; installed RSSI/range qualification is post-prototype and pre-release - USB connector, plug, cable-head, and service-access envelope - optional locating holes must be physically fit-verified or deliberately omitted before footprint freeze -- external 5 V / USB-C VBUS topology -- USB/onboard mixed-source and backfeed testing +- implement, rate, label, and mechanically validate the physical board-MCU-5-V service disconnect +- bench-validate the defined normal, USB-service, mixed-presence, removal, and misuse power-state matrix with the disconnect in its permitted positions - bench validation of the implemented hardware-default-OFF gate-driver correction across the complete power-transition matrix - complete regulator implementation, load measurement, and installed-temperature thermal analysis - Q1 multipad/footprint and F2 holder-footprint verification diff --git a/docs/PRODUCT_SAFETY_CONTRACT.md b/docs/PRODUCT_SAFETY_CONTRACT.md index ba3309b..cf30133 100644 --- a/docs/PRODUCT_SAFETY_CONTRACT.md +++ b/docs/PRODUCT_SAFETY_CONTRACT.md @@ -41,6 +41,12 @@ AUTOMATIC production heating is unavailable even when `PRINTING` is fresh. and evidence of sane commanded-OFF behavior before heat may be enabled again. - Cooldown and fault fan policy is product-owned and may operate in OFF. - Browser and API authorization are management controls, never the safety boundary. +- The actual Super Mini directly couples USB VBUS to its exposed 5 V pin. Rev A + therefore requires a physical disconnect between board-derived MCU 5 V and + the module node, opened before powered USB service. USB must never power + `+5V_SYS_GATE`, the heater gate driver, the MOSFET actuation path, or any other + safety-critical actuator domain. Removal of 24 V must collapse gate power even + if USB keeps the MCU alive. Reset-cause persistence, stuck-on proof, physical sensors, and physical fan proof are not implemented in this heater-incapable foundation. They are mandatory gates diff --git a/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv index 710a4ca..1f44604 100644 --- a/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv +++ b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv @@ -20,7 +20,7 @@ Q4,1,Heater-driver OE open-drain actuator,2N7002-class N-MOSF,BASE,"Provisional R20/R21/R22,3,Heater-driver OE bias,"10 k pull-up / 1 k series / 100 k gate pulldown",BASE,"All values provisional; /OE defaults high/disabled and Q4 must pull it low to enable" R1/R2/R7,3,Heater PWM/gate passives,"47 ohm gate series / 10 k Q1 gate pulldown / 100 k PWM input pulldown",BASE,"All values provisional pending waveform leakage PWM-frequency switching-loss and transition testing" C12,1,Gate-buffer local decoupling,100 nF provisional,BASE,"Place at U1 supply pins; dielectric and final value remain subject to implementation review" -TP11-TP16,6,Power and heater-driver test points,"+5V_SYS_GATE / +5V_MCU / OE / PWM input / Q1 gate / Q1 source",BASE,Required Phase 1 power-transition and gate-safety observations +TP11-TP16,6,Power and heater-driver test points,"+5V_SYS_GATE / Super Mini-side +5V_MCU and USB-VBUS tied node / OE / PWM input / Q1 gate / Q1 source",BASE,"Required Phase 1 power-transition and gate-safety observations; add board-side MCU 5 V point if space permits after disconnect implementation" U2,1,Controller module,"ESP32-S3 Super Mini, 2x9 edge pads",BASE,"Identity confirmed; pad numbering receiving-land geometry registration underside isolation antenna keepout USB access and flash size remain open" J6-J8,3,Thermistors,"10 k NTC, 1 m lead",BASE,Beta/coefficients TBD J9 + divider,1,Fourth thermistor,10 k NTC,DNP,Expansion diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch index 9b2762f..a232634 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch @@ -1258,7 +1258,7 @@ (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid 989d1c1b-e73b-4557-9840-8d28f49f2f69) ) - (text "+5V_MCU source selection is TBD: do not bridge to +5V_SYS_GATE or assume USB/external-5V isolation." + (text "+5V_MCU is the Super Mini 5V/USB-VBUS tied node. Insert the required physical board-5V disconnect upstream; never bridge to +5V_SYS_GATE." (at 28.00 124.00 0) (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid d7a12df2-cad0-4bf1-bfb7-709f03e42f5f) diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch index 487db04..93c8d46 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch @@ -1378,7 +1378,7 @@ (effects (font (size 1.80 1.80) (thickness 0.225)) (justify left bottom)) (uuid 35f7f43e-ad43-476c-8fd0-7eb41fba3c3a) ) - (text "MOD1 is an LMR36520 architecture placeholder: +24V_PROT to +5V_SYS_GATE only; +5V_MCU source selection remains TBD." + (text "MOD1 is an LMR36520 architecture placeholder for +5V_SYS_GATE. Board MCU 5V regulation and the required physical disconnect to +5V_MCU remain unresolved." (at 23.00 92.00 0) (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid 7f86481b-c093-4c97-83e9-606d5d071579) @@ -3134,7 +3134,7 @@ (property "Value" "TP_5V_MCU" (at 151.22 111.77 0) (effects (font (size 0.85 0.85)))) (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 147.22 108.77 0) (effects (font (size 0.85 0.85)) hide)) (property "Datasheet" "" (at 147.22 108.77 0) (effects (font (size 0.85 0.85)) hide)) - (property "Description" "MCU-domain rail test point; source selection remains TBD" (at 147.22 108.77 0) (effects (font (size 0.85 0.85)) hide)) + (property "Description" "Super Mini-side 5V/USB-VBUS tied-node test point; physical board-5V disconnect is required upstream" (at 147.22 108.77 0) (effects (font (size 0.85 0.85)) hide)) (pin "1" (uuid e56fbc18-6b61-4f88-bc30-66fca23e14c8)) (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "TP12") (unit 1)))) ) diff --git a/hardware/kicad/JumpJet_RevA/README.md b/hardware/kicad/JumpJet_RevA/README.md index f0eeec1..7c5b390 100644 --- a/hardware/kicad/JumpJet_RevA/README.md +++ b/hardware/kicad/JumpJet_RevA/README.md @@ -19,6 +19,14 @@ sheets in this directory. Project-local symbols and footprints resolve through Phase 1 implementation work, not a missing artifact to recover. - This source is not fabrication-ready and does not authorize heater or fan actuation. +- Bench characterization establishes that the actual Super Mini's exposed 5 V + pin and USB VBUS are directly coupled for system-design purposes. Rev A now + requires a physically accessible board-5-V disconnect upstream of the module + `+5V_MCU` node, opened before powered USB service. The implementation part and + footprint are not selected or drawn yet; TPS2116-only automatic selection is + not a valid solution for nodes already tied on the module. +- `+5V_SYS_GATE` remains a separate 24-V-derived actuator rail. USB must have no + path to that rail, the gate buffer supply, or heater actuation. - `BOM_PRELIMINARY.csv` is archive context only. It contains placeholders and does not override statuses in [`docs/PHASE1_HARDWARE_REGISTER.md`](../../../docs/PHASE1_HARDWARE_REGISTER.md). From fcdffb62ee8984a79eff20faee41c0b341b55786 Mon Sep 17 00:00:00 2001 From: Daniel Brown Date: Tue, 8 Sep 2026 12:18:32 -0400 Subject: [PATCH 14/20] hardware: connect Rev A fan header --- .../JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch index 93c8d46..0cf956f 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch @@ -1315,13 +1315,6 @@ - (wire (pts (xy 264.16 55.88) (xy 267.97 55.88)) - (stroke (width 0) (type default)) - (uuid 142205d2-4395-4fda-8dcd-6861e5acd394) - ) - - - (wire (pts (xy 298.45 53.34) (xy 299.72 53.34)) (stroke (width 0) (type default)) (uuid 3fa443a8-8045-4e8c-a625-cedb4d14a1aa) @@ -1408,7 +1401,7 @@ (uuid efadd267-eef7-4648-9d7b-c0ed698f7488) ) - (label "GND" (at 264.16 55.88 0) + (label "GND" (at 267.97 57.15 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 0e4edc5b-8fb0-4c10-972d-4773d90023d8) ) @@ -1440,15 +1433,15 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 88505649-d9d1-41d2-ad8c-190f3c82bd51) ) - (label "FAN_24V" (at 267.97 53.34 0) + (label "FAN_24V" (at 267.97 54.61 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 8f28c6e1-81d8-43cf-9997-62f5bf560bcd) ) - (label "FAN_TACH_WIRE" (at 267.97 58.42 0) + (label "FAN_TACH_WIRE" (at 267.97 59.69 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 6b56096b-9a75-4c0c-a91d-0b8e9adfe5cb) ) - (label "FAN_PWM_WIRE" (at 267.97 60.96 0) + (label "FAN_PWM_WIRE" (at 267.97 62.23 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid b40cbb79-279b-4575-9997-ec73c77fcc9a) ) From 7b5e300b19f9d8f5210b9df3f33e59fee0c39bad Mon Sep 17 00:00:00 2001 From: Daniel Brown Date: Tue, 8 Sep 2026 12:55:36 -0400 Subject: [PATCH 15/20] hardware: clean structural ERC findings --- docs/PHASE1_HARDWARE_REGISTER.md | 11 ++-- .../JumpJet_Power_Outputs.kicad_sch | 50 +++++++++---------- hardware/kicad/JumpJet_RevA/README.md | 6 ++- 3 files changed, 34 insertions(+), 33 deletions(-) diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index bf90a00..a229e7d 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -1,6 +1,6 @@ # Phase 1 hardware source-of-truth register -Last updated: 2026-09-07 +Last updated: 2026-09-08 This is the living engineering register for JumpJet Rev A Phase-1 hardware implementation. It records what is known, how it is known, what remains @@ -191,9 +191,9 @@ identify a valid production cutoff temperature or mounting location. | PCB plane and local envelope | TBD / BLOCKED | No defensible PCB plane, maximum rectangle, overhang, standoff range, component-height limit, shell clearance, service edge, USB/fuse/connector access zone, antenna-open direction, or airflow no-go region can be derived from gross void bounds. The Jetpack fan-face pattern supplies a useful local datum but is not located within the printer void. | Mechanical-source alignment audit | High confidence that local mechanics remain open | Align the sources and build the local constraint map; then validate the leading carrier strategies and a 1:1 physical mockup before freezing mechanics. | PCB envelope + Edge.Cuts + mounting + Fabrication | | Production PSU location | DESIGN DECISION | Keep the production power supply outside the printer; only the protected incoming 24 V harness enters the Jump Jet installation volume. | Phase-1 system packaging direction | High | Define entry location, connector, strain relief, routing, and service access against the corrected/confirmed mechanical assembly. | PCB placement + harness + Fabrication | | Rev A PCB state | CONFIRMED FACT | PCB design is the current Rev A implementation stage. A `.kicad_pcb` has not yet been created and must now be designed. | Rev A.4.1 package scope and Phase-1 project state | High | Create and review the first Rev A PCB from the authoritative schematic. | PCB layout + Fabrication | -| Authoritative KiCad source | CONFIRMED FACT | Rev A.4.1 native project source is checked in under [`hardware/kicad/JumpJet_RevA/`](../hardware/kicad/JumpJet_RevA/README.md): root schematic, four child sheets, project symbol/footprint libraries, library tables, minimal project file, preliminary BOM, and archive provenance README. | `JumpJet_Controller_RevA4_1_J3_JST_XH.zip` intake and checked-in source | High for file provenance | Open in native KiCad and run ERC when `kicad-cli` or desktop KiCad is available. | PCB layout + Fabrication | -| KiCad source schema/validation | ASSUMPTION / PROVISIONAL | Root schematic declares schema `20211014`/generator `kiutils`; child sheets declare `20260306`/custom generator; footprint files declare `20240108`. Hierarchical filenames and project-local library paths resolve by static inspection, but native application open/ERC has not been run in this environment. | File headers, root-sheet references, and library tables | High for observed metadata; medium for openability | Open/save only after review, verify no unintended migration diff, resolve all libraries, then run native ERC. | PCB layout + Fabrication | -| Unresolved footprint references | TBD / BLOCKED | Rev A.4.1 intentionally contains unresolved placeholders `TBD:High_Current_2Pin`, `TBD:DC_DC_Module`, `TBD:Aux_2Pin`, and `Package_DirectFET:TBD`. Standard-library and project-local non-placeholder names were identified, but native library resolution is not yet proven. | Static scan of checked-in schematic footprint properties | High | Replace every placeholder with a verified project/standard footprint and run native library resolution/ERC before PCB import. | PCB layout + BOM freeze + Fabrication | +| Authoritative KiCad source | CONFIRMED FACT | Rev A.4.1 native project source is checked in under [`hardware/kicad/JumpJet_RevA/`](../hardware/kicad/JumpJet_RevA/README.md): root schematic, four child sheets, project symbol/footprint libraries, library tables, minimal project file, preliminary BOM, and archive provenance README. Native KiCad 10.0.6 opens the root hierarchy and native ERC runs from that root. | `JumpJet_Controller_RevA4_1_J3_JST_XH.zip` intake, checked-in source, native KiCad 10.0.6 open, and `kicad-cli sch erc` | High | Preserve root-driven ERC validation as the schematic evolves. | PCB layout + Fabrication | +| KiCad source schema/validation | CONFIRMED FACT | Tooling blocker CLOSED: despite mixed source schema/generator provenance, KiCad 10.0.6 opens `JumpJet_Controller_RevA4.kicad_sch` with all four child sheets and native root-driven ERC is reusable with the installed standard library tables. Structural/off-grid and label-scope findings are cleared; remaining findings are explicit product blockers, intentional NC/TBD items, or individually reviewed cached-library differences. | Native KiCad 10.0.6 project open and root-driven ERC after structural cleanup | High | Re-run native ERC after each schematic change; do not hide unresolved product blockers. | PCB layout + Fabrication | +| Unresolved footprint references | TBD / BLOCKED | Rev A.4.1 intentionally contains unresolved placeholders `TBD:High_Current_2Pin`, `TBD:DC_DC_Module`, `TBD:Aux_2Pin`, and `Package_DirectFET:TBD`. Native ERC resolves installed standard and project-local non-placeholder libraries; only these deliberate footprint placeholders remain unresolved. | Native KiCad 10.0.6 root-driven ERC and checked-in schematic footprint properties | High | Replace every placeholder only after the corresponding part and footprint are verified. | PCB layout + BOM freeze + Fabrication | | Preliminary archive BOM | CONFIRMED FACT | `BOM_PRELIMINARY.csv` is checked in as source context only. Its placeholders and historical values do not override this register and are not BOM-final. | [Rev A.4.1 preliminary BOM](../hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv) | High | Reconcile every line against reviewed schematic candidates and replace with a controlled production BOM later. | BOM freeze + Fabrication | | J1/F1/MOD1 implementation | TBD / BLOCKED | `J1` remains `24V IN / 20A MIN` with placeholder footprint `TBD:High_Current_2Pin`; `F1` remains `15A TBD` with no footprint. `MOD1` now records LMR36520 as the strong-candidate buck architecture and outputs only `+5V_SYS_GATE`, but its connector symbol and `TBD:DC_DC_Module` footprint are explicitly placeholders rather than a discrete implementation. | [Checked-in Phase-1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch) and preliminary BOM | High | Select/qualify exact input connector and main protection; implement the complete LMR36520 candidate circuit and verified footprints; validate service/thermal behavior, transients, and PSU/fuse coordination. | PCB layout + BOM freeze + Fabrication | | Starting stackup | ASSUMPTION / PROVISIONAL | Two layers, 1.6 mm FR-4, 2 oz copper. | Phase-1 routing/current-density starting point | Medium | Review high-current routing, grounding, RF, mechanical, thermal, cost, and PCBWay manufacturing requirements before freeze. | PCB layout + BOM freeze + Fabrication | @@ -222,12 +222,11 @@ bounded by reviewed production-intent provisions: - bench validation of the implemented hardware-default-OFF gate-driver correction across the complete power-transition matrix - complete regulator implementation, load measurement, and installed-temperature thermal analysis - Q1 multipad/footprint and F2 holder-footprint verification -- four-wire fan connector/interface footprint and candidate electrical verification; schematic provisions are implemented but not natively ERC-validated +- four-wire fan connector/interface footprint and candidate electrical verification; schematic provisions pass structural native ERC checks but remain electrically unqualified - TF1/TS1 part, mounting, and thermal-coupling implementation - J1/F1 selections and footprints; MOD1 discrete-regulator implementation and footprint - PCB envelope, mounting-hole coordinates, connector-facing edges, and USB datum - final 1:1 production-footprint fit check with the actual module -- native KiCad project-open/library-resolution check and ERC ## Register maintenance rules diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch index 0cf956f..975b771 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch @@ -1401,7 +1401,7 @@ (uuid efadd267-eef7-4648-9d7b-c0ed698f7488) ) - (label "GND" (at 267.97 57.15 0) + (global_label "GND" (shape bidirectional) (at 267.97 57.15 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 0e4edc5b-8fb0-4c10-972d-4773d90023d8) ) @@ -1461,11 +1461,11 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 7369b6d6-8901-4562-8eec-c1b632b5bfcb) ) - (global_label "FAN_TACH" (shape bidirectional) (at 286.0 95.25 90) (fields_autoplaced) + (global_label "FAN_TACH" (shape bidirectional) (at 285.75 95.25 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid a9509179-7f36-4c48-b194-7d393f81223f) ) - (global_label "GND" (shape bidirectional) (at 286.0 102.87 90) (fields_autoplaced) + (global_label "GND" (shape bidirectional) (at 285.75 102.87 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 32b75d47-d271-473f-987b-397f9b0282ec) ) @@ -1473,7 +1473,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 1720e976-f08a-45dd-81c6-511ac6af6b40) ) - (global_label "FAN_PWM_WIRE" (shape bidirectional) (at 289.56 69.85 0) (fields_autoplaced) + (label "FAN_PWM_WIRE" (at 289.56 69.85 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 4404c555-d833-4ee5-a4bd-e973d0755e3c) ) @@ -1773,7 +1773,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid c17a63e2-ee13-41c1-9815-67d9d0126df3) ) - (global_label "HEATER_GATE_OE_N" (shape bidirectional) (at 193.04 136.00 0) (fields_autoplaced) + (global_label "HEATER_GATE_OE_N" (shape bidirectional) (at 193.04 135.89 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid e95523ab-439f-451b-84b4-1849bcdce835) ) @@ -1789,11 +1789,11 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid c1ed12ce-8ad8-4dab-82ed-03ed4137f411) ) - (global_label "+5V_SYS_GATE" (shape bidirectional) (at 350.52 146.19 90) (fields_autoplaced) + (global_label "+5V_SYS_GATE" (shape bidirectional) (at 350.52 146.05 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid ae374296-e039-456a-b5f6-5564f68f6772) ) - (global_label "GND" (shape bidirectional) (at 350.52 153.81 90) (fields_autoplaced) + (global_label "GND" (shape bidirectional) (at 350.52 153.67 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 4d718d1f-57d1-407d-81f5-aa518a65ae97) ) @@ -2440,22 +2440,22 @@ ) ) - (symbol (lib_id "Device:C") (at 286 99.06 0) (unit 1) + (symbol (lib_id "Device:C") (at 285.75 99.06 0) (unit 1) (in_bom yes) (on_board yes) (dnp yes) (uuid 3ef8d1f4-a503-479a-b508-2546715a582a) - (property "Reference" "C11" (at 286.14 95.23 0) + (property "Reference" "C11" (at 285.89 95.23 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "TACH FILTER DNP/TBD" (at 286.14 103.23 0) + (property "Value" "TACH FILTER DNP/TBD" (at 285.89 103.23 0) (effects (font (size 0.85 0.85))) ) - (property "Footprint" "Capacitor_SMD:C_0603_1608Metric" (at 286.14 99.23 0) + (property "Footprint" "Capacitor_SMD:C_0603_1608Metric" (at 285.89 99.23 0) (effects (font (size 0.85 0.85)) hide) ) - (property "Datasheet" "" (at 286.14 99.23 0) + (property "Datasheet" "" (at 285.89 99.23 0) (effects (font (size 0.85 0.85)) hide) ) - (property "Description" "" (at 286.14 99.23 0) + (property "Description" "" (at 285.89 99.23 0) (effects (font (size 0.85 0.85)) hide) ) (pin "1" (uuid 955d9622-05d3-4bed-a25b-5329cd2608dc)) @@ -3131,14 +3131,14 @@ (pin "1" (uuid e56fbc18-6b61-4f88-bc30-66fca23e14c8)) (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "TP12") (unit 1)))) ) - (symbol (lib_id "Connector:TestPoint") (at 193.04 136.00 0) (unit 1) + (symbol (lib_id "Connector:TestPoint") (at 193.04 135.89 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid 0cd52f47-ec30-4291-8506-0750d4b3a12f) - (property "Reference" "TP13" (at 188.94 132.55 0) (effects (font (size 0.85 0.85)))) - (property "Value" "TP_GATE_OE" (at 196.94 138.55 0) (effects (font (size 0.85 0.85)))) - (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 192.94 135.55 0) (effects (font (size 0.85 0.85)) hide)) - (property "Datasheet" "" (at 192.94 135.55 0) (effects (font (size 0.85 0.85)) hide)) - (property "Description" "Heater-channel active-low OE test point" (at 192.94 135.55 0) (effects (font (size 0.85 0.85)) hide)) + (property "Reference" "TP13" (at 188.94 132.44 0) (effects (font (size 0.85 0.85)))) + (property "Value" "TP_GATE_OE" (at 196.94 138.44 0) (effects (font (size 0.85 0.85)))) + (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 192.94 135.44 0) (effects (font (size 0.85 0.85)) hide)) + (property "Datasheet" "" (at 192.94 135.44 0) (effects (font (size 0.85 0.85)) hide)) + (property "Description" "Heater-channel active-low OE test point" (at 192.94 135.44 0) (effects (font (size 0.85 0.85)) hide)) (pin "1" (uuid df407eb9-1341-446b-aeaf-7f705a287ed4)) (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "TP13") (unit 1)))) ) @@ -3175,14 +3175,14 @@ (pin "1" (uuid 9e23a224-e9e1-4b84-9fbd-f7c29b4bdb21)) (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "TP16") (unit 1)))) ) - (symbol (lib_id "Device:C") (at 350.52 150.00 0) (unit 1) + (symbol (lib_id "Device:C") (at 350.52 149.86 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid c44ebd4d-e17a-42a4-9813-b15b484c04bf) - (property "Reference" "C12" (at 350.66 146.17 0) (effects (font (size 0.85 0.85)))) - (property "Value" "100nF U1 DECOUPLING PROVISIONAL" (at 350.66 154.17 0) (effects (font (size 0.85 0.85)))) - (property "Footprint" "Capacitor_SMD:C_0603_1608Metric" (at 350.66 150.17 0) (effects (font (size 0.85 0.85)) hide)) - (property "Datasheet" "" (at 350.66 150.17 0) (effects (font (size 0.85 0.85)) hide)) - (property "Description" "Local SN74LV4T125 supply bypass; value and dielectric require final review." (at 350.66 150.17 0) (effects (font (size 0.85 0.85)) hide)) + (property "Reference" "C12" (at 350.66 146.03 0) (effects (font (size 0.85 0.85)))) + (property "Value" "100nF U1 DECOUPLING PROVISIONAL" (at 350.66 154.03 0) (effects (font (size 0.85 0.85)))) + (property "Footprint" "Capacitor_SMD:C_0603_1608Metric" (at 350.66 150.03 0) (effects (font (size 0.85 0.85)) hide)) + (property "Datasheet" "" (at 350.66 150.03 0) (effects (font (size 0.85 0.85)) hide)) + (property "Description" "Local SN74LV4T125 supply bypass; value and dielectric require final review." (at 350.66 150.03 0) (effects (font (size 0.85 0.85)) hide)) (pin "1" (uuid ee1a40d3-d721-4106-ad8b-caceb919fd6a)) (pin "2" (uuid 2b88943d-1899-40c3-a5b8-5eb262499613)) (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "C12") (unit 1)))) diff --git a/hardware/kicad/JumpJet_RevA/README.md b/hardware/kicad/JumpJet_RevA/README.md index 7c5b390..38125a5 100644 --- a/hardware/kicad/JumpJet_RevA/README.md +++ b/hardware/kicad/JumpJet_RevA/README.md @@ -30,8 +30,10 @@ sheets in this directory. Project-local symbols and footprints resolve through - `BOM_PRELIMINARY.csv` is archive context only. It contains placeholders and does not override statuses in [`docs/PHASE1_HARDWARE_REGISTER.md`](../../../docs/PHASE1_HARDWARE_REGISTER.md). -- Native KiCad ERC has not been run in this environment because `kicad-cli` is - unavailable. The archive provenance note records the same limitation. +- Native KiCad 10.0.6 opens the root hierarchy successfully, and native ERC is + reusable with the installed standard library tables. ERC intentionally still + reports the unresolved `+5V_MCU` source path, unassigned control nets, TBD + footprints, intentional legacy NC nets, and reviewed cached-symbol differences. - Hierarchical-sheet and project-local library paths pass static resolution. Placeholder footprint references `TBD:High_Current_2Pin`, `TBD:DC_DC_Module`, `TBD:Aux_2Pin`, and `Package_DirectFET:TBD` remain From 0cc47bb0e2ae00c64217e210759170dd2fada508 Mon Sep 17 00:00:00 2001 From: Daniel Brown Date: Tue, 8 Sep 2026 13:26:12 -0400 Subject: [PATCH 16/20] hardware: implement MCU power isolation and service disconnect --- .../kicad/JumpJet_RevA/BOM_PRELIMINARY.csv | 5 +- .../JumpJet_RevA/JumpJet_Controller.kicad_sch | 2 +- .../JumpJet_Controller_RevA.kicad_sym | 86 +++++++++ .../JumpJet_Power_Outputs.kicad_sch | 179 +++++++++++++++++- 4 files changed, 269 insertions(+), 3 deletions(-) diff --git a/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv index 1f44604..95f58e2 100644 --- a/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv +++ b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv @@ -3,6 +3,9 @@ J1,1,24 V input,">=20 A keyed terminal, 14 AWG capable",BASE,Footprint TBD F1,1,Main fuse,15 A provisional,BASE,Verify coordination D1,1,Rail TVS,SMBJ30A provisional,BASE,Verify clamp vs MOSFET/PSU MOD1,1,Gate-domain buck architecture,"TI LMR36520 strong candidate; +24V_PROT to +5V_SYS_GATE; >=1.5 A provisional floor",BASE,"Connector symbol remains an implementation placeholder; discrete circuit footprint thermal derating and final MPN remain open; not BOM-final" +D4,1,MCU branch reverse-current isolation,"Low-Vf Schottky class; >=2 A practical current capability; exact MPN TBD",BASE,"Strong candidate only; footprint Vf reverse leakage elevated-temperature behavior dissipation and availability remain open; not BOM-final" +SW1,1,RUN / USB SERVICE MCU power disconnect,"SPST slide-switch class; >=2 A at 5 V DC; contact resistance target <=50 mOhm and <=100 mOhm ceiling",BASE,"Strong candidate only; exact MPN footprint operating-temperature rating retention and service-edge mechanics remain open; not BOM-final" +TPS2116 (no reference),0,Conditional source-mux concept,Not production intent for the current directly tied Super Mini VBUS/5 V topology,DNP,"Documentation-only; reconsider only for a future architecture with genuinely separate source nodes" F2,1,Heater branch fuse,Littelfuse 0287015.U 15 A ATOF candidate,BASE,"Strong candidate; cold-start characterization complete; PSU/fuse coordination and holder thermal validation open" TF1,1,One-shot thermal fuse,"Historical schematic placeholder: 75 C / 15 A",BASE,"Production part trip temperature mounting and thermal coupling TBD" TS1,1,Resettable thermal switch,"Historical schematic placeholder: NC 75 C / 16 A",BASE,"Production part trip temperature mounting and thermal coupling TBD" @@ -20,7 +23,7 @@ Q4,1,Heater-driver OE open-drain actuator,2N7002-class N-MOSF,BASE,"Provisional R20/R21/R22,3,Heater-driver OE bias,"10 k pull-up / 1 k series / 100 k gate pulldown",BASE,"All values provisional; /OE defaults high/disabled and Q4 must pull it low to enable" R1/R2/R7,3,Heater PWM/gate passives,"47 ohm gate series / 10 k Q1 gate pulldown / 100 k PWM input pulldown",BASE,"All values provisional pending waveform leakage PWM-frequency switching-loss and transition testing" C12,1,Gate-buffer local decoupling,100 nF provisional,BASE,"Place at U1 supply pins; dielectric and final value remain subject to implementation review" -TP11-TP16,6,Power and heater-driver test points,"+5V_SYS_GATE / Super Mini-side +5V_MCU and USB-VBUS tied node / OE / PWM input / Q1 gate / Q1 source",BASE,"Required Phase 1 power-transition and gate-safety observations; add board-side MCU 5 V point if space permits after disconnect implementation" +TP11-TP17,7,Power and heater-driver test points,"+5V_SYS_GATE / Super Mini-side +5V_MCU and USB-VBUS tied node / OE / PWM input / Q1 gate / Q1 source / pre-switch +5V_MCU_FEED",BASE,"Required Phase 1 power-transition and gate-safety observations; TP17 exposes the isolated board-derived feed before SW1" U2,1,Controller module,"ESP32-S3 Super Mini, 2x9 edge pads",BASE,"Identity confirmed; pad numbering receiving-land geometry registration underside isolation antenna keepout USB access and flash size remain open" J6-J8,3,Thermistors,"10 k NTC, 1 m lead",BASE,Beta/coefficients TBD J9 + divider,1,Fourth thermistor,10 k NTC,DNP,Expansion diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch index a232634..685237f 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch @@ -1258,7 +1258,7 @@ (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid 989d1c1b-e73b-4557-9840-8d28f49f2f69) ) - (text "+5V_MCU is the Super Mini 5V/USB-VBUS tied node. Insert the required physical board-5V disconnect upstream; never bridge to +5V_SYS_GATE." + (text "+5V_MCU is the measured Super Mini 5V/USB-VBUS tied node. D4 and SW1 on the power sheet isolate its board-derived feed from +5V_SYS_GATE for USB service." (at 28.00 124.00 0) (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid d7a12df2-cad0-4bf1-bfb7-709f03e42f5f) diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Controller_RevA.kicad_sym b/hardware/kicad/JumpJet_RevA/JumpJet_Controller_RevA.kicad_sym index 4f47016..0a7306f 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Controller_RevA.kicad_sym +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Controller_RevA.kicad_sym @@ -101,6 +101,92 @@ ) ) ) + (symbol "JJ_MCU_ISOLATOR" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "D" (at 0 2.54 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "JJ_MCU_ISOLATOR" (at 0 -2.54 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Description" "One-way MCU branch power isolator; power pin types model forward power flow without a PWR_FLAG workaround." (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "JJ_MCU_ISOLATOR_0_1" + (polyline + (pts (xy 1.905 0.635) (xy 1.905 1.27) (xy 1.27 1.27) (xy 1.27 -1.27) (xy 0.635 -1.27) (xy 0.635 -0.635)) + (stroke (width 0.254) (type default)) + (fill (type none)) + ) + (polyline + (pts (xy -1.27 1.27) (xy -1.27 -1.27) (xy 1.27 0) (xy -1.27 1.27)) + (stroke (width 0.254) (type default)) + (fill (type none)) + ) + (polyline + (pts (xy 1.27 0) (xy -1.27 0)) + (stroke (width 0) (type default)) + (fill (type none)) + ) + ) + (symbol "JJ_MCU_ISOLATOR_1_1" + (pin power_in line (at -3.81 0 0) (length 2.54) + (name "A" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin power_out line (at 3.81 0 180) (length 2.54) + (name "K" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + ) + ) + (symbol "JJ_MCU_PWR_DISCONNECT" (pin_names (offset 0)) (in_bom yes) (on_board yes) + (property "Reference" "SW" (at 0 3.175 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "JJ_MCU_PWR_DISCONNECT" (at 0 -2.54 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Description" "RUN / USB SERVICE SPST disconnect; power pin types model the board-derived source path in RUN without a PWR_FLAG workaround." (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "JJ_MCU_PWR_DISCONNECT_0_0" + (circle (center -2.032 0) (radius 0.508) + (stroke (width 0) (type default)) + (fill (type none)) + ) + (polyline + (pts (xy -1.524 0.254) (xy 1.524 1.778)) + (stroke (width 0) (type default)) + (fill (type none)) + ) + (circle (center 2.032 0) (radius 0.508) + (stroke (width 0) (type default)) + (fill (type none)) + ) + ) + (symbol "JJ_MCU_PWR_DISCONNECT_1_1" + (pin power_in line (at -5.08 0 0) (length 2.54) + (name "+5V_MCU_FEED" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin power_out line (at 5.08 0 180) (length 2.54) + (name "+5V_MCU" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + ) + ) (symbol "JJ_PWR_FLAG" (pin_names (offset 0)) (in_bom yes) (on_board yes) (property "Reference" "#FLG" (at 0 1.905 0) (show_name) (effects (font (size 1.27 1.27)) hide) diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch index 975b771..f1106d2 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch @@ -1158,6 +1158,94 @@ ) ) + (symbol "JumpJet_Controller_RevA:JJ_MCU_ISOLATOR" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "D" (at 0 2.54 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "JJ_MCU_ISOLATOR" (at 0 -2.54 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Description" "One-way MCU branch power isolator; power pin types model forward power flow without a PWR_FLAG workaround." (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "JJ_MCU_ISOLATOR_0_1" + (polyline + (pts (xy 1.905 0.635) (xy 1.905 1.27) (xy 1.27 1.27) (xy 1.27 -1.27) (xy 0.635 -1.27) (xy 0.635 -0.635)) + (stroke (width 0.254) (type default)) + (fill (type none)) + ) + (polyline + (pts (xy -1.27 1.27) (xy -1.27 -1.27) (xy 1.27 0) (xy -1.27 1.27)) + (stroke (width 0.254) (type default)) + (fill (type none)) + ) + (polyline + (pts (xy 1.27 0) (xy -1.27 0)) + (stroke (width 0) (type default)) + (fill (type none)) + ) + ) + (symbol "JJ_MCU_ISOLATOR_1_1" + (pin power_in line (at -3.81 0 0) (length 2.54) + (name "A" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin power_out line (at 3.81 0 180) (length 2.54) + (name "K" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + ) + ) + + (symbol "JumpJet_Controller_RevA:JJ_MCU_PWR_DISCONNECT" (pin_names (offset 0)) (in_bom yes) (on_board yes) + (property "Reference" "SW" (at 0 3.175 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "JJ_MCU_PWR_DISCONNECT" (at 0 -2.54 0) (show_name) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Description" "RUN / USB SERVICE SPST disconnect; power pin types model the board-derived source path in RUN without a PWR_FLAG workaround." (at 0 0 0) (show_name) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "JJ_MCU_PWR_DISCONNECT_0_0" + (circle (center -2.032 0) (radius 0.508) + (stroke (width 0) (type default)) + (fill (type none)) + ) + (polyline + (pts (xy -1.524 0.254) (xy 1.524 1.778)) + (stroke (width 0) (type default)) + (fill (type none)) + ) + (circle (center 2.032 0) (radius 0.508) + (stroke (width 0) (type default)) + (fill (type none)) + ) + ) + (symbol "JJ_MCU_PWR_DISCONNECT_1_1" + (pin power_in line (at -5.08 0 0) (length 2.54) + (name "+5V_MCU_FEED" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin power_out line (at 5.08 0 180) (length 2.54) + (name "+5V_MCU" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + ) + ) + (symbol "JumpJet_Controller_RevA:JJ_PWR_FLAG" (pin_names (offset 0)) (in_bom yes) (on_board yes) (property "Reference" "#FLG" (at 0 1.905 0) (show_name) (effects (font (size 1.27 1.27)) hide) @@ -1308,6 +1396,11 @@ (uuid 51d4f40c-8338-4856-8087-a8a6d14e50f6) ) + (wire (pts (xy 143.51 96.52) (xy 148.59 96.52)) + (stroke (width 0) (type default)) + (uuid 54db3b88-c898-4acb-bc53-74fa6798b651) + ) + (wire (pts (xy 215.9 55.88) (xy 218.44 55.88)) (stroke (width 0) (type default)) (uuid 109e3162-811b-4d54-93a9-2c9da0d79ed6) @@ -1371,7 +1464,7 @@ (effects (font (size 1.80 1.80) (thickness 0.225)) (justify left bottom)) (uuid 35f7f43e-ad43-476c-8fd0-7eb41fba3c3a) ) - (text "MOD1 is an LMR36520 architecture placeholder for +5V_SYS_GATE. Board MCU 5V regulation and the required physical disconnect to +5V_MCU remain unresolved." + (text "MOD1 is the shared LMR36520 candidate feeding +5V_SYS_GATE. D4 reverse-blocks the MCU branch; SW1 selects RUN or physical USB SERVICE isolation. Exact parts/footprints remain TBD." (at 23.00 92.00 0) (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid 7f86481b-c093-4c97-83e9-606d5d071579) @@ -1773,6 +1866,22 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid c17a63e2-ee13-41c1-9815-67d9d0126df3) ) + (global_label "+5V_SYS_GATE" (shape bidirectional) (at 135.89 96.52 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid 601fe2b7-cb81-458c-b95e-3a484e5b8b3a) + ) + (global_label "+5V_MCU_FEED" (shape bidirectional) (at 146.05 104.14 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid c3029cec-1d89-4655-a6c3-0cdcaa1ae461) + ) + (global_label "+5V_MCU_FEED" (shape bidirectional) (at 143.51 96.52 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid b8aaa80c-24ec-4eb0-9a00-ef7aa979900f) + ) + (global_label "+5V_MCU" (shape bidirectional) (at 158.75 96.52 0) (fields_autoplaced) + (effects (font (size 0.85 0.85)) (justify left bottom)) + (uuid b95bdc90-b0a7-4f47-914b-7f81675149d4) + ) (global_label "HEATER_GATE_OE_N" (shape bidirectional) (at 193.04 135.89 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid e95523ab-439f-451b-84b4-1849bcdce835) @@ -3109,6 +3218,74 @@ ) ) + (symbol (lib_id "JumpJet_Controller_RevA:JJ_MCU_ISOLATOR") (at 139.7 96.52 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid b365c50a-6985-4628-9823-f9071f1db1bd) + (property "Reference" "D4" (at 139.7 92.71 0) + (effects (font (size 0.85 0.85))) + ) + (property "Value" "D_MCU_ISO LOW-VF SCHOTTKY >=2A MPN TBD" (at 139.7 100.33 0) + (effects (font (size 0.85 0.85))) + ) + (property "Footprint" "" (at 139.7 96.52 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Datasheet" "" (at 139.7 96.52 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Description" "Strong-candidate low-Vf Schottky reverse blocker; exact MPN and footprint TBD after current, leakage, thermal, and availability review." (at 139.7 96.52 0) + (effects (font (size 0.85 0.85)) hide) + ) + (pin "1" (uuid 79f83890-2e43-43dd-b150-390ef831c894)) + (pin "2" (uuid c5739508-858a-4709-a32f-1569f1935e71)) + (instances + (project "JumpJet_Controller_RevA4" + (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" + (reference "D4") (unit 1) + ) + ) + ) + ) + (symbol (lib_id "JumpJet_Controller_RevA:JJ_MCU_PWR_DISCONNECT") (at 153.67 96.52 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid f1862ec1-0316-4166-946d-7bcedc6a9136) + (property "Reference" "SW1" (at 153.67 92.71 0) + (effects (font (size 0.85 0.85))) + ) + (property "Value" "SW_MCU_PWR RUN / USB SERVICE SPST >=2A TBD" (at 153.67 100.33 0) + (effects (font (size 0.85 0.85))) + ) + (property "Footprint" "" (at 153.67 96.52 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Datasheet" "" (at 153.67 96.52 0) + (effects (font (size 0.85 0.85)) hide) + ) + (property "Description" "Strong-candidate physical SPST slide-switch class for RUN / USB SERVICE isolation; exact MPN and footprint TBD after current, contact-resistance, temperature, retention, and service-edge review." (at 153.67 96.52 0) + (effects (font (size 0.85 0.85)) hide) + ) + (pin "1" (uuid efdf69f5-0ce2-4d98-9a8e-6da0bc12fc0e)) + (pin "2" (uuid bb786eea-ec2e-4420-90e8-8607f0e60829)) + (instances + (project "JumpJet_Controller_RevA4" + (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" + (reference "SW1") (unit 1) + ) + ) + ) + ) + (symbol (lib_id "Connector:TestPoint") (at 146.05 104.14 0) (unit 1) + (in_bom yes) (on_board yes) (dnp no) + (uuid 615aecbf-f4d0-4314-a208-72ea03fb19b8) + (property "Reference" "TP17" (at 141.95 100.69 0) (effects (font (size 0.85 0.85)))) + (property "Value" "TP_5V_MCU_FEED" (at 149.95 106.69 0) (effects (font (size 0.85 0.85)))) + (property "Footprint" "TestPoint:TestPoint_Pad_D1.5mm" (at 145.95 103.69 0) (effects (font (size 0.85 0.85)) hide)) + (property "Datasheet" "" (at 145.95 103.69 0) (effects (font (size 0.85 0.85)) hide)) + (property "Description" "Board-derived MCU feed test point between reverse blocker and RUN / USB SERVICE switch." (at 145.95 103.69 0) (effects (font (size 0.85 0.85)) hide)) + (pin "1" (uuid 289e0708-a2f9-4c3a-9a9f-5eb9608e4628)) + (instances (project "JumpJet_Controller_RevA4" (path "/7daa19f2-c821-405d-9b33-9c66dc62ede9" (reference "TP17") (unit 1)))) + ) + (symbol (lib_id "Connector:TestPoint") (at 130.81 109.22 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid 5036d94e-0cc2-48b5-b18f-ef69098020b3) From f6b252573d4e9f2b2e85e882b9812b687673f58d Mon Sep 17 00:00:00 2001 From: Daniel Brown Date: Tue, 8 Sep 2026 13:26:12 -0400 Subject: [PATCH 17/20] docs: close Super Mini VBUS and MCU source architecture --- docs/PHASE1_HARDWARE_REGISTER.md | 29 +++++++++++++++++++++------ hardware/kicad/JumpJet_RevA/README.md | 9 +++++---- 2 files changed, 28 insertions(+), 10 deletions(-) diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index a229e7d..3ac5a41 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -77,18 +77,35 @@ temperatures. | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | |---|---|---|---|---|---|---| -| Production power domains | DESIGN DECISION | Protected 24 V feeds separate board-derived paths: exclusive `+5V_SYS_GATE` for heater gate-drive circuitry and a board MCU 5 V path. The board MCU path reaches the Super Mini `+5V_MCU`/USB-VBUS tied node only through a deliberate physical service disconnect. USB is never routed to `+5V_SYS_GATE`. Raw 24 V must never reach the module, and USB-only MCU power must be physically incapable of powering any actuator domain. | Phase-1 power-domain and service-safety decision; implemented gate/MCU net separation; measured module 5 V topology | High | Implement and qualify the board MCU regulator path and disconnect; verify all normal, USB-service, mixed-presence, reset, and brownout states. | PCB layout + BOM freeze + Fabrication | +| Production power domains | DESIGN DECISION | One shared 24 V-derived 5 V regulator feeds `+5V_SYS_GATE`. The heater gate driver remains directly on that actuator rail, while the MCU branch passes through D4 reverse isolation, `+5V_MCU_FEED`, and physical SW1 before reaching the Super Mini `+5V_MCU`/USB-VBUS tied node. USB is never routed to `+5V_SYS_GATE`; USB-only power must be physically incapable of energizing that rail or any actuator domain. | Phase-1 power-domain and service-safety decision; implemented D4/SW1 source path; measured module 5 V topology | High | Qualify the regulator, isolation element, disconnect, and full normal/service/misuse transition matrix. | PCB layout + BOM freeze + Fabrication | | USB-C role | DESIGN DECISION | Programming, debug, recovery, and service only; not the normal installed power source. Board-derived MCU 5 V must be physically disconnected before attaching a powered USB host. USB may power only the Super Mini-side MCU logic node and must not energize `+5V_SYS_GATE`, the gate driver, or Q1 actuation. | Phase-1 service architecture and measured bidirectional VBUS/5 V coupling | High | Validate every USB-only and mixed-presence power state and observe both 5 V sides, gate rail, OE, PWM input, and Q1 gate during attach/remove. | PCB layout + Fabrication | | External 5 V/VBUS pin | MEASURED | USB VBUS and the Super Mini exposed 5 V pin are effectively the same node for system design. With 4.993 V applied at the exposed pin, USB VBUS measured 4.992 V. With USB supplied at 5.13 V, the exposed pin measured 5.11 V. Unpowered continuity was confirmed and diode-mode behavior was consistent with direct coupling. | Direct bench characterization of the actual ESP32-S3 Super Mini | High for the tested module | Preserve the measured topology in the schematic and validate production-module consistency during receiving/bring-up. | None | | USB/external-5 V relationship | CONFIRMED FACT | The Super Mini provides no usable isolation between USB VBUS and its exposed 5 V pin. USB powers the exposed pin, and external 5 V on that pin energizes the USB connector VBUS. Simultaneous board-derived 5 V and a powered USB host must be treated as unsafe unless one source is physically isolated before the tied module node. | Bidirectional voltage and unpowered continuity measurements on the actual module | High | Do not perform simultaneous-source testing with the disconnect closed. Verify the completed carrier implements the required isolation boundary. | PCB layout + Fabrication | -| Physical MCU service-power disconnect | DESIGN DECISION | Rev A shall place a firmware-independent physical disconnect between board-derived MCU 5 V (`BOARD_5V_MCU` conceptually) and the Super Mini-side `+5V_MCU`/USB-VBUS tied node. Normal operation uses the disconnect closed and USB absent. USB service requires the disconnect open before host attachment. Seamless simultaneous USB plus board MCU power is out of scope for Rev A. | Measured module topology and explicit Rev A service policy | High for architecture; implementation unresolved | Select and rate the disconnect after measuring MCU-path current; verify footprint, voltage drop, accessibility near USB, connector clearance, labeling, retention, and misuse visibility. | PCB layout + BOM freeze + Fabrication | -| Disconnect implementation | STRONG CANDIDATE | A removable jumper/shunt is the narrowest preferred implementation. A serviceable removable link, slide switch, or two-position selector remains fallback if current, mechanical, or service review rejects the jumper. No part, footprint, current rating, or standoff/clearance is frozen. | Rev A simplicity, auditability, and service requirements | Medium-high | Measure module current including boot/Wi-Fi bursts; select a rated part and footprint; prove access and clearance in the aligned mechanical model and 1:1 mockup. | PCB layout + BOM freeze + Fabrication | -| MCU service labeling | DESIGN DECISION | The disconnect and USB service area require unambiguous board labeling that tells a technician to open the board-MCU 5 V path before connecting powered USB. Candidate semantics are `MCU POWER`, `USB SERVICE`, and `OPEN FOR USB`; exact wording, placement, and orientation remain unresolved until the service geometry is known. | Rev A mutually exclusive service-power policy | High for requirement; implementation unresolved | Verify the final silkscreen is visible with the product service-access path open, cannot be mistaken for an actuator jumper, and remains legible after assembly. | PCB layout + Fabrication | +| MCU branch reverse isolation | DESIGN DECISION | The MCU branch shall conduct only `+5V_SYS_GATE -> D4 -> +5V_MCU_FEED`; reverse current from USB/`+5V_MCU` toward `+5V_SYS_GATE` is forbidden. This hardware invariant protects the actuator rail during valid USB service and misuse states without firmware. | Implemented D4/SW1 Phase-1 schematic source path and measured bidirectional Super Mini VBUS/5 V coupling | High for topology | Qualify reverse leakage, forward drop, dissipation, temperature, and USB/24 V transitions on production-intent hardware. | PCB layout + BOM freeze + Fabrication | +| MCU isolation element | STRONG CANDIDATE | D4 is a low-Vf Schottky class with at least 2 A practical current capability, low drop around 0.5–1.0 A, low elevated-temperature reverse leakage, at least 20 V VRRM, and a package comfortable in the approximately 0.2–0.4 W dissipation class. Exact MPN and footprint are TBD and it is not BOM-final. | Phase-1 isolation architecture and provisional MCU load/dissipation envelope | Medium | Measure MCU peak current; select the exact diode/package; calculate and measure hot drop, loss, leakage, and temperature; review availability. | PCB layout + BOM freeze + Fabrication | +| Physical MCU service-power disconnect | DESIGN DECISION | Rev A places firmware-independent SW1 in series between `+5V_MCU_FEED` and the Super Mini-side `+5V_MCU`/USB-VBUS tied node. RUN closes board-derived MCU power; USB SERVICE opens it before host attachment. A solder bridge is not acceptable, and a removable jumper is not primary production intent unless the switch proves mechanically impractical. | Measured module topology, explicit Rev A service policy, and implemented D4/SW1 schematic path | High for architecture | Select and rate the switch after measuring MCU-path current; verify footprint, voltage drop, accessibility near USB, connector clearance, labeling, retention, and misuse visibility. | PCB layout + BOM freeze + Fabrication | +| Disconnect implementation | STRONG CANDIDATE | SW1 is a positive-detent SPST slide-switch class rated at least 2 A at 5 V DC, with contact resistance targeted at no more than 50 mΩ and an absolute design ceiling of 100 mΩ; at least 85 °C operation is preferred. Exact MPN and footprint remain TBD and it is not BOM-final. | Rev A simplicity, auditability, service requirements, and implemented generic SW1 symbol | Medium-high | Measure module current including boot/Wi-Fi bursts; select a rated part and footprint; prove electrical loss, temperature, retention, access, and clearance in the aligned model and 1:1 mockup. | PCB layout + BOM freeze + Fabrication | +| MCU service labeling | DESIGN DECISION | Later PCB silkscreen shall label SW1 states `RUN` and `USB SERVICE` and instruct the technician to set USB SERVICE before connecting powered USB. Exact shortened wording, placement, and orientation remain unresolved until the service geometry is known. | Rev A mutually exclusive service-power policy | High for requirement; implementation unresolved | Verify the final instruction is visible through the service-access path, cannot be mistaken for an actuator control, and remains legible after assembly. | PCB layout + Fabrication | +| Prohibited simultaneous-source state | DESIGN DECISION | `24 V present + powered USB connected + SW1 in RUN` is a prohibited service configuration because the tied module node can create source contention. The D4 reverse boundary must nevertheless prevent USB/`+5V_MCU` from back-powering `+5V_SYS_GATE`; no supported coexistence is claimed. | Measured module topology, D4/SW1 architecture, and explicit misuse policy | High | Label clearly and verify the heater-domain isolation invariant without intentionally sustaining source contention. | PCB layout + Fabrication | | TPS2116-only source-mux direction | CONFIRMED FACT | Superseded and not sufficient as a USB/external-5 V coexistence solution. A carrier-side TPS2116 cannot independently select USB VBUS versus the exposed module 5 V pin because those nodes are already directly coupled on the Super Mini. TPS2116 is not required by the adopted Rev A mutually exclusive service-power architecture. | Measured module topology compared with [TI TPS2116 product behavior](https://www.ti.com/product/TPS2116) | High | Reconsider only for a narrower future requirement with genuinely separate source nodes; do not place it for Rev A without such a requirement. | None | | Buck converter candidate | STRONG CANDIDATE | TI LMR36520 synchronous buck: published 4.2–65 V input, 2 A output, up to 70 V input transients, −40 to +125 °C operating junction range, power-good option, and approximately 90% published efficiency at 24 V input, 5 V output, and 1 A. The present `MOD1` connector symbol is only an architecture placeholder, not a discrete implementation or BOM-final part. | [TI LMR36520 product page](https://www.ti.com/product/LMR36520) and Phase-1 regulator review | High for published characteristics; medium for product fit | Select exact ordering code and switching frequency; implement and review the complete discrete circuit, magnetics, compensation/support parts, layout, efficiency/dissipation, transient behavior, and installed-temperature derating. | PCB layout + BOM freeze + Fabrication | | Buck converter capacity target | ASSUMPTION / PROVISIONAL | Use at least 1.5 A continuous capability as an initial converter target. This is not a selected MPN or BOM-final rating. | Preliminary ESP32-S3 peak/burst allowance plus light interface-load margin | Medium | Complete the 5 V load inventory and converter loss/thermal derating at the maximum installed chamber/PCB temperature; increase the rating if required. | PCB layout + BOM freeze + Fabrication | | Power-management firmware assumptions | TBD / BLOCKED | Firmware may rely on the architectural fact that USB cannot power the actuator rail, but may not assume the physical disconnect position, board-5-V availability, power-good behavior, or heater availability without truthful hardware evidence. When 24 V is removed while USB remains, MCU logic may stay alive but heater actuation must be reported unavailable. | Adopted Rev A power-domain architecture; disconnect sensing and power-good implementation unresolved | High | Close the implemented power-state truth table and determine whether disconnect position and board/gate-rail availability are observable. | Firmware constants | +### Rev A power-state truth table + +| 24 V | USB | SW1 | Expected state | +|---|---|---|---| +| OFF | OFF | RUN | `+5V_SYS_GATE` OFF; MCU OFF. | +| ON | OFF | RUN | `+5V_SYS_GATE` ON; MCU ON; normal operation. | +| ON | OFF | USB SERVICE | `+5V_SYS_GATE` ON; MCU OFF; heater driver remains hardware-disabled without MCU enable. | +| OFF | ON | USB SERVICE | `+5V_SYS_GATE` OFF; MCU ON; valid USB service. | +| OFF | ON | RUN | `+5V_SYS_GATE` must remain OFF; MCU ON; misuse state with heater domain isolated. | +| ON | ON | USB SERVICE | `+5V_SYS_GATE` ON; MCU is USB-powered; valid service state; heater driver remains default-disabled. | +| ON | ON | RUN | Prohibited source-contention state; no supported coexistence claim; D4 must still block USB backfeed into `+5V_SYS_GATE`. | + +When 24 V disappears, `+5V_SYS_GATE` collapses, U1 loses VCC, its active-low OE defaults disabled, and the direct Q1 pulldown discharges the gate. If USB remains, `+5V_MCU` may remain alive while D4 keeps `+5V_SYS_GATE` dead; U1's candidate `Ioff` behavior must be qualified to prevent MCU inputs from parasitically powering the unpowered gate-driver domain. + ### Provisional 5 V load inventory | Load | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | @@ -121,7 +138,7 @@ temperatures. | Default-disabled OE architecture | DESIGN DECISION | `R20` provisionally pulls heater-channel `/OE` to `+5V_SYS_GATE`. `Q4` (`Q_GATE_EN`, provisional 2N7002-class device) can pull `/OE` low only when generic unassigned net `HEATER_GATE_EN` is asserted. Its gate has a direct pull-down. MCU reset/high-Z/unpowered/disconnected therefore leaves the driver disabled. Unused buffer channels are held disabled, and USB-only power cannot energize the gate-driver rail. | Implemented Phase-1 power/output schematic and TI active-low OE/Ioff behavior | High for intended topology | Run the mandatory 24 V/USB/reset/brownout/attach/remove transition matrix while observing both rails, OE, PWM input, Q1 gate, and source reference. Verify Q4 leakage and resistor values at temperature. | PCB layout + BOM freeze + Fabrication | | Heater PWM command path | DESIGN DECISION | Generic unassigned `HEATER_PWM_CMD` feeds the U1 A input with a direct input pull-down; no MCU pin is assigned. U1 `Ioff` is intended to prevent back-power through this input while its VCC is absent. U1 Y drives `HTR_GATE` through the provisional series resistor. | Implemented Phase-1 power/output schematic | High for topology | Verify unpowered leakage, logic levels, transitions, and gate waveform on representative hardware. | PCB layout + BOM freeze + Firmware constants + Fabrication | | Gate network values | ASSUMPTION / PROVISIONAL | `R1` is 47 Ω provisional; the direct Q1 gate pull-down `R2` is 10 kΩ provisional; the PWM-input pull-down remains 100 kΩ provisional. The stronger Q1 pull-down improves deterministic turnoff while dissipating only milliwatts when driven high. | CSD18540Q5B maximum gate charge is approximately 26 nC at 4.5 V; Phase-1 leakage/turnoff review | Medium | Select final resistance from leakage, turn-off, gate waveform, PWM frequency, switching loss, and driver-current validation. | PCB layout + BOM freeze + Firmware constants + Fabrication | -| Gate/power test points | DESIGN DECISION | Existing `TP11`–`TP16` expose `+5V_SYS_GATE`, the Super Mini-side `+5V_MCU`/USB-VBUS tied node, heater `/OE`, `HEATER_PWM_CMD`, Q1 gate, and Q1 source reference. Add an accessible board-side MCU 5 V test point before the physical disconnect if board space permits, so both sides can be observed without treating USB VBUS as isolated. | Implemented Phase-1 power/output schematic plus measured module topology | High for existing points; board-side point provisional | Verify footprint accessibility and use both sides of the disconnect plus all gate points in the power-transition bench matrix. | PCB layout + Fabrication | +| Gate/power test points | DESIGN DECISION | `TP11`–`TP17` expose `+5V_SYS_GATE`, the Super Mini-side `+5V_MCU`/USB-VBUS tied node, heater `/OE`, `HEATER_PWM_CMD`, Q1 gate, Q1 source reference, and pre-switch `+5V_MCU_FEED`. TP17 is a bounded bring-up point for verifying D4 and SW1 isolation. | Implemented Phase-1 power/output schematic plus measured module topology | High for schematic provision | Verify footprint accessibility and use both sides of the disconnect plus all gate points in the power-transition bench matrix. | PCB layout + Fabrication | | Q1 footprint and thermal implementation | TBD / BLOCKED | Exact verified KiCad footprint, thermal-pad implementation, and copper spreading are not frozen. | Footprint/PCB validation not completed | High confidence that implementation is incomplete | Verify package drawing and pad mapping; complete thermal/current layout and measurement plan. | PCB layout + Fabrication | | Rev A.4.1 Q1 mapping defect | CONFIRMED FACT | Q1 currently uses a generic `Q_NMOS_GDS` symbol and unresolved `Package_DirectFET:TBD` footprint. CSD18540Q5B is published as an 8-pin 5 mm × 6 mm VSON-CLIP (DNK), so the current footprint assignment cannot represent the candidate package or multipad mapping. | [Rev A.4.1 power/output sheet](../hardware/kicad/JumpJet_RevA/JumpJet_Power_Outputs.kicad_sch); [TI CSD18540Q5B product/datasheet page](https://www.ti.com/product/CSD18540Q5B) | High | Build/verify the exact DNK symbol-to-pad mapping, exposed/current pads, land pattern, solder treatment, and thermal copper against the manufacturer drawing. | PCB layout + BOM freeze + Fabrication | @@ -217,7 +234,7 @@ bounded by reviewed production-intent provisions: - antenna identity and conservative pre-fabrication keepout; installed RSSI/range qualification is post-prototype and pre-release - USB connector, plug, cable-head, and service-access envelope - optional locating holes must be physically fit-verified or deliberately omitted before footprint freeze -- implement, rate, label, and mechanically validate the physical board-MCU-5-V service disconnect +- select, rate, footprint, label, and mechanically validate D4 reverse isolation and the physical SW1 board-MCU-5-V service disconnect - bench-validate the defined normal, USB-service, mixed-presence, removal, and misuse power-state matrix with the disconnect in its permitted positions - bench validation of the implemented hardware-default-OFF gate-driver correction across the complete power-transition matrix - complete regulator implementation, load measurement, and installed-temperature thermal analysis diff --git a/hardware/kicad/JumpJet_RevA/README.md b/hardware/kicad/JumpJet_RevA/README.md index 38125a5..4c0aa1f 100644 --- a/hardware/kicad/JumpJet_RevA/README.md +++ b/hardware/kicad/JumpJet_RevA/README.md @@ -21,10 +21,11 @@ sheets in this directory. Project-local symbols and footprints resolve through actuation. - Bench characterization establishes that the actual Super Mini's exposed 5 V pin and USB VBUS are directly coupled for system-design purposes. Rev A now - requires a physically accessible board-5-V disconnect upstream of the module - `+5V_MCU` node, opened before powered USB service. The implementation part and - footprint are not selected or drawn yet; TPS2116-only automatic selection is - not a valid solution for nodes already tied on the module. + routes the shared `+5V_SYS_GATE` source through D4 reverse isolation and the + physical SW1 RUN / USB SERVICE disconnect before the module `+5V_MCU` node. + D4 and SW1 are strong-candidate functional classes only; their exact MPNs and + footprints remain TBD. TPS2116-only automatic selection is not a valid + solution for nodes already tied on the module. - `+5V_SYS_GATE` remains a separate 24-V-derived actuator rail. USB must have no path to that rail, the gate buffer supply, or heater actuation. - `BOM_PRELIMINARY.csv` is archive context only. It contains placeholders and From 0a2febc007795a988fc3eedec3f3080f09437ef2 Mon Sep 17 00:00:00 2001 From: Daniel Brown Date: Wed, 9 Sep 2026 09:32:42 -0400 Subject: [PATCH 18/20] hardware: add onboard PCB thermistor channel --- docs/PHASE1_HARDWARE_REGISTER.md | 10 ++++ .../kicad/JumpJet_RevA/BOM_PRELIMINARY.csv | 4 +- .../JumpJet_RevA/JumpJet_Controller.kicad_sch | 2 +- .../JumpJet_Temperature_Sensing.kicad_sch | 46 +++++++++++++------ hardware/kicad/JumpJet_RevA/README.md | 5 ++ 5 files changed, 49 insertions(+), 18 deletions(-) diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index 3ac5a41..8c5f88b 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -181,6 +181,16 @@ The first PCB may include configurable interface provisions, but fabrication is acceptable only if the unresolved interface is deliberately bounded and does not require unsupported electrical assumptions. +### Rev A thermal sensing contract + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| Four-channel Rev A sensing | DESIGN DECISION | Rev A retains the three remote channels `T_CHAMBER`, `T_OUTLET`, and `T_CASE_EXTERNAL` and adds `T_PCB` as a fourth, onboard SMD NTC channel. No existing thermal channel is removed. | Finalized Phase-1 thermal-channel steering and checked-in thermistor sheet | High for channel semantics | Verify all four channels together on production-intent hardware. | Firmware constants + PCB layout + Fabrication | +| `T_PCB` role | DESIGN DECISION | `T_PCB` monitors local electronics/PCB heat soak, including correlation with buck/regulator, MOSFET, fuse/terminal, enclosure, and `T_CASE_EXTERNAL` behavior. It is not chamber temperature and is not equivalent to `T_CASE_EXTERNAL`. | Finalized Phase-1 thermal-channel steering | High | Compare all four channels during normal heating, heat soak, cooldown, airflow-fault-oriented tests, high ambient, and power-section stress. Rev B may remove `T_CASE_EXTERNAL` only if validation shows `T_PCB` is equal or better for the intended safety-relevant role. | Firmware constants + PCB layout + Fabrication | +| `T_PCB` front end | DESIGN DECISION | `TH1` is a provisioned onboard 10 kΩ SMD NTC using the existing 3.3 V, 10 kΩ 0.1% pull-up, 1 kΩ ADC-series, and 100 nF filter philosophy (`R16`, `R17`, `C8`). The unassigned product-local ADC net is `TEMP_PCB_ADC`. `TH1` retains the legacy connector-shaped graphic as a bounded representation blocker until it can be replaced natively without corrupting the archived mixed-schema hierarchy. | Checked-in thermistor sheet; topology matched to the three existing channels | High for electrical topology; symbol and component selection unresolved | Replace the placeholder graphic with a native thermistor symbol, then validate ADC range, noise, open/short detectability, return-path integrity, and conversion calibration. | Firmware constants + PCB layout + BOM freeze + Fabrication | +| `T_PCB` device and firmware constants | TBD / BLOCKED | Exact NTC MPN, Beta, tolerance, temperature rating, ADC/GPIO assignment, conversion constants, and firmware thresholds are not selected. No thermal thresholds are implied by this channel addition. | Required evidence is not yet available | High confidence that selection remains open | Select and qualify the NTC; assign ADC only with the complete controller pin plan; derive constants and thresholds from measured hardware. | Firmware constants + BOM freeze + Fabrication | +| `T_PCB` placement | TBD / BLOCKED | Exact placement remains open. Sense representative local electronics/PCB temperature, not a component junction or fan inlet. Do not place directly against Q1 thermal copper, buck switch-node copper, under the ESP32-S3, in the fan cold-air jet, against the heater connector or fuse-holder copper, or on a pour dominated by one hot component. | Layout has not begun; no `.kicad_pcb` exists | High confidence that placement remains open | Establish placement after the PCB plane, component placement, airflow, and high-current geometry are known; validate correlation against `T_CASE_EXTERNAL`. | PCB layout + Fabrication | + ## 9. Independent thermal protection | Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | diff --git a/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv index 95f58e2..2bc80f3 100644 --- a/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv +++ b/hardware/kicad/JumpJet_RevA/BOM_PRELIMINARY.csv @@ -25,8 +25,8 @@ R1/R2/R7,3,Heater PWM/gate passives,"47 ohm gate series / 10 k Q1 gate pulldown C12,1,Gate-buffer local decoupling,100 nF provisional,BASE,"Place at U1 supply pins; dielectric and final value remain subject to implementation review" TP11-TP17,7,Power and heater-driver test points,"+5V_SYS_GATE / Super Mini-side +5V_MCU and USB-VBUS tied node / OE / PWM input / Q1 gate / Q1 source / pre-switch +5V_MCU_FEED",BASE,"Required Phase 1 power-transition and gate-safety observations; TP17 exposes the isolated board-derived feed before SW1" U2,1,Controller module,"ESP32-S3 Super Mini, 2x9 edge pads",BASE,"Identity confirmed; pad numbering receiving-land geometry registration underside isolation antenna keepout USB access and flash size remain open" -J6-J8,3,Thermistors,"10 k NTC, 1 m lead",BASE,Beta/coefficients TBD -J9 + divider,1,Fourth thermistor,10 k NTC,DNP,Expansion +J6-J8,3,Remote thermistors,"10 k NTC, 1 m lead",BASE,"T_OUTLET / T_CASE_EXTERNAL / T_CHAMBER; Beta/coefficients TBD" +TH1/R16/R17/C8,1 channel,Onboard PCB temperature channel,"10 k NTC SMD + 10 k 0.1% pull-up + 1 k ADC series + 100 nF filter",BASE,"T_PCB; TH1 retains the legacy connector-shaped graphic pending native thermistor-symbol replacement; 0603 package provision is provisional; exact NTC MPN Beta tolerance temperature rating placement ADC/GPIO conversion constants and thresholds TBD" J10,1,Qwiic,JST-SH 1.0 mm 4-pin,BASE,Supported expansion F5,1,Qwiic protection,250 mA resettable fuse,BASE,Provisional JP1/JP2 + R18/R19,2,I2C pullups,4.7 k selectable,DNP/open,Populate only if required diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch index 685237f..1253cfe 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Controller.kicad_sch @@ -1339,7 +1339,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 85637bba-03d9-49d4-a80b-a2879daa7d47) ) - (global_label "TEMP4_ADC_DNP" (shape bidirectional) (at 53.34 81.28 0) (fields_autoplaced) + (global_label "TEMP_PCB_ADC" (shape bidirectional) (at 53.34 81.28 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 88c060ab-29ef-43d9-8225-c59ac269bd88) ) diff --git a/hardware/kicad/JumpJet_RevA/JumpJet_Temperature_Sensing.kicad_sch b/hardware/kicad/JumpJet_RevA/JumpJet_Temperature_Sensing.kicad_sch index 34da006..e845efb 100644 --- a/hardware/kicad/JumpJet_RevA/JumpJet_Temperature_Sensing.kicad_sch +++ b/hardware/kicad/JumpJet_RevA/JumpJet_Temperature_Sensing.kicad_sch @@ -5,13 +5,13 @@ (paper "A4" portrait) (title_block - (title "JumpJet Controller — Thermistor front ends") + (title "JumpJet Controller — Four-channel thermistor front ends") (date "2026-08-25") (rev "A.4.1 - LAYOUT CLEANUP") (company "JumpJet") (comment 1 "24 V PTC chamber-heater controller") (comment 2 "ESP32-S3 SuperMini 2x9 carrier; measured 23.7 x 17.93 mm, 25.0 mm incl. USB-C") - (comment 3 "TBD values require bench verification before assembly") + (comment 3 "Remote T_CHAMBER/T_OUTLET/T_CASE_EXTERNAL plus onboard T_PCB; ADC assignments TBD") (comment 4 "Heater thermal cutoffs are independent of firmware") ) @@ -1245,8 +1245,24 @@ (effects (font (size 0.95 0.95) (thickness 0.120)) (justify left bottom)) (uuid d66547b9-5afc-461e-9f2e-b95aeff56576) ) + (text "T_OUTLET — REMOTE" (at 49.53 43.18 0) + (effects (font (size 1.0 1.0) (thickness 0.15)) (justify left bottom)) + (uuid f2c9505a-3c97-48bb-8879-00a4863b1dc0) + ) + (text "T_CASE_EXTERNAL — REMOTE" (at 139.7 43.18 0) + (effects (font (size 1.0 1.0) (thickness 0.15)) (justify left bottom)) + (uuid 98c61b1d-8536-4d8e-b6f8-56a5240d743c) + ) + (text "T_CHAMBER — REMOTE" (at 49.53 106.68 0) + (effects (font (size 1.0 1.0) (thickness 0.15)) (justify left bottom)) + (uuid 786c0448-cf5b-43f4-b9fa-1a57027c004d) + ) + (text "T_PCB — ONBOARD SMD NTC; PLACEMENT / MPN / BETA / TOLERANCE / RATING TBD" (at 139.7 106.68 0) + (effects (font (size 0.85 0.85) (thickness 0.12)) (justify left bottom)) + (uuid c737977f-9361-4801-ac4f-78b41fd88751) + ) - (label "TEMP4_NTC" (at 153.67 123.19 0) + (label "PCB_NTC" (at 153.67 123.19 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 04796262-9abb-49ad-9a6f-1d8a8348969c) ) @@ -1258,7 +1274,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 4272f72a-8246-447f-8588-231ddc675773) ) - (label "TEMP4_NTC" (at 128.27 116.84 90) + (label "PCB_NTC" (at 128.27 116.84 90) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 52a35402-db56-4b44-906f-3baf8486b0d1) ) @@ -1278,7 +1294,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid e34a8a3f-fa0e-4fd7-bfa1-bbc6c12a2d73) ) - (label "TEMP4_NTC" (at 134.62 123.19 0) + (label "PCB_NTC" (at 134.62 123.19 0) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid e35002fe-2ed7-4030-a96e-7b15376d72b9) ) @@ -1343,7 +1359,7 @@ (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 826b1ea8-dc6f-43ad-93ff-6195aaf50908) ) - (global_label "TEMP4_ADC_DNP" (shape bidirectional) (at 173.99 123.19 0) (fields_autoplaced) + (global_label "TEMP_PCB_ADC" (shape bidirectional) (at 173.99 123.19 0) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid 9ec425d1-2024-4612-8278-038ac8796675) ) @@ -1380,7 +1396,7 @@ (uuid 99e8a8ad-5c35-4ea8-aa90-f3f0fa4e51da) ) - (global_label "TEMP4_ADC_DNP" (shape bidirectional) (at 167.64 129.54 90) (fields_autoplaced) + (global_label "TEMP_PCB_ADC" (shape bidirectional) (at 167.64 129.54 90) (fields_autoplaced) (effects (font (size 0.85 0.85)) (justify left bottom)) (uuid a29eeaeb-58ae-433c-814b-fab22ebc042c) ) @@ -1746,19 +1762,19 @@ (symbol (lib_id "Connector_Generic:Conn_01x02") (at 144.78 123.19 0) (unit 1) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-000068ae0032) - (property "Reference" "J9" (at 145.31 117.04 0) + (property "Reference" "TH1" (at 145.31 117.04 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "10k NTC4 DNP" (at 145.31 129.04 0) + (property "Value" "10k NTC PCB TEMP; MPN/BETA/TOL TBD" (at 145.31 129.04 0) (effects (font (size 0.85 0.85))) ) - (property "Footprint" "Connector_JST:JST_XH_B2B-XH-A_1x02_P2.50mm_Vertical" (at 145.31 123.04 0) + (property "Footprint" "Resistor_SMD:R_0603_1608Metric" (at 145.31 123.04 0) (effects (font (size 0.85 0.85)) hide) ) (property "Datasheet" "" (at 145.31 123.04 0) (effects (font (size 0.85 0.85)) hide) ) - (property "Description" "" (at 145.31 123.04 0) + (property "Description" "Onboard PCB temperature NTC; exact production device and placement TBD" (at 145.31 123.04 0) (effects (font (size 0.85 0.85)) hide) ) (pin "1" (uuid cd3e66e6-5e94-43dd-9f78-a26eadea8549)) @@ -1766,7 +1782,7 @@ (instances (project "JumpJet_Controller_RevA4" (path "/7c4d4b33-dd60-4c75-b093-7eaa23607d3f" - (reference "J9") (unit 1) + (reference "TH1") (unit 1) ) ) ) @@ -1778,7 +1794,7 @@ (property "Reference" "R16" (at 128.80 108.88 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "10k_0.1%_DNP" (at 128.80 116.88 0) + (property "Value" "10k_0.1%" (at 128.80 116.88 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "Resistor_SMD:R_0603_1608Metric" (at 128.80 112.88 0) @@ -1807,7 +1823,7 @@ (property "Reference" "R17" (at 156.35 121.24 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "1k_ADC_DNP" (at 164.75 124.84 0) + (property "Value" "1k_ADC" (at 164.75 124.84 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "Resistor_SMD:R_0603_1608Metric" (at 160.55 123.04 0) @@ -1836,7 +1852,7 @@ (property "Reference" "C8" (at 168.17 129.20 0) (effects (font (size 0.85 0.85))) ) - (property "Value" "100nF_DNP" (at 168.17 137.20 0) + (property "Value" "100nF" (at 168.17 137.20 0) (effects (font (size 0.85 0.85))) ) (property "Footprint" "Capacitor_SMD:C_0603_1608Metric" (at 168.17 133.20 0) diff --git a/hardware/kicad/JumpJet_RevA/README.md b/hardware/kicad/JumpJet_RevA/README.md index 4c0aa1f..5e8f10d 100644 --- a/hardware/kicad/JumpJet_RevA/README.md +++ b/hardware/kicad/JumpJet_RevA/README.md @@ -28,6 +28,11 @@ sheets in this directory. Project-local symbols and footprints resolve through solution for nodes already tied on the module. - `+5V_SYS_GATE` remains a separate 24-V-derived actuator rail. USB must have no path to that rail, the gate buffer supply, or heater actuation. +- Rev A retains remote `T_CHAMBER`, `T_OUTLET`, and `T_CASE_EXTERNAL` sensing and + adds onboard `T_PCB` through the existing thermistor-front-end philosophy. + `T_PCB` placement, exact NTC characteristics, ADC/GPIO assignment, conversion + constants, and firmware thresholds remain blocked; it is not chamber sensing + and does not supersede `T_CASE_EXTERNAL` in Rev A. - `BOM_PRELIMINARY.csv` is archive context only. It contains placeholders and does not override statuses in [`docs/PHASE1_HARDWARE_REGISTER.md`](../../../docs/PHASE1_HARDWARE_REGISTER.md). From a4def1c81ed0399a4c0213b23a7024d6727c12ac Mon Sep 17 00:00:00 2001 From: Daniel Brown Date: Sun, 27 Sep 2026 16:35:25 +0000 Subject: [PATCH 19/20] docs: record Panda PWR teardown findings --- docs/PHASE1_HARDWARE_REGISTER.md | 13 +- .../panda-pwr/panda-pwr-board-angle.jpg | Bin 0 -> 226931 bytes .../panda-pwr/panda-pwr-board-overview.jpg | Bin 0 -> 120161 bytes .../panda-pwr-hlw8112-metering-ic.jpg | Bin 0 -> 118279 bytes .../panda-pwr/panda-pwr-sensing-section.jpg | Bin 0 -> 211799 bytes docs/hardware/panda-pwr-characterization.md | 273 ++++++++++++++++++ 6 files changed, 285 insertions(+), 1 deletion(-) create mode 100644 docs/hardware/images/panda-pwr/panda-pwr-board-angle.jpg create mode 100644 docs/hardware/images/panda-pwr/panda-pwr-board-overview.jpg create mode 100644 docs/hardware/images/panda-pwr/panda-pwr-hlw8112-metering-ic.jpg create mode 100644 docs/hardware/images/panda-pwr/panda-pwr-sensing-section.jpg create mode 100644 docs/hardware/panda-pwr-characterization.md diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index 8c5f88b..4ab613d 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -1,6 +1,6 @@ # Phase 1 hardware source-of-truth register -Last updated: 2026-09-08 +Last updated: 2026-09-27 This is the living engineering register for JumpJet Rev A Phase-1 hardware implementation. It records what is known, how it is known, what remains @@ -229,6 +229,17 @@ identify a valid production cutoff temperature or mounting location. | High-current placement priority | DESIGN DECISION | Place and review `+24V_PROT -> F2 -> TF1 -> TS1 -> J2 -> heater -> Q1 -> GND` before convenience circuitry. Keep Q1, J2, F2, and the heater-current path compact without weakening conductor geometry for appearance. | Rev A.4.1 topology and Phase-1 implementation priority | High | Complete placement, current-loop, service-clearance, and thermal review. | PCB layout + Fabrication | | PCB validation | TBD / BLOCKED | Current-density bottlenecks, Q1 thermal spreading, fuse-holder and J2 pad heating, high-current return geometry, ADC noise, antenna keepout, DRC, fabricated-board temperature rise, and full-path voltage drop are unvalidated. | No Rev A PCB exists yet | High confidence that validation is pending | Create the board, review design evidence, fabricate only after blockers close, then thermally/electrically test production-intent hardware. | PCB layout + BOM freeze + Fabrication | +## 11. External reference hardware + +External products characterized for architecture review only. Entries here do +not select JumpJet components, are not BOM sources, and do not establish JumpJet +safety or compliance evidence. Component detail lives in the linked records, not +in the JumpJet production tables above. + +| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | +|---|---|---|---|---|---|---| +| BIGTREETECH Panda PWR Rev 1 teardown | CONFIRMED FACT | External/reference evidence only. Direct teardown confirms `ESP8684-MINI-1-H4`, `HLK-20M05`, `SRD-05VDC-SL-B`, `HLW8112`, `ZMPT107-1`, and a `T2A 250V` fuse marking. Sensing-path, fuse-branch, relay-routing, isolation-boundary, and 5 V / 3.3 V rail topology remain partly unmapped. Informs architecture review only; selects no JumpJet component. | [Panda PWR characterization](hardware/panda-pwr-characterization.md); destructive teardown photographs, 2026-09-27 | High for listed markings; low for circuit topology | Unpowered continuity mapping, isolation/creepage mapping, and verification of the FCC `2BAS6-PANDAPWR` model-difference wording against the primary exhibit, per the characterization record. | None | + ## Current fabrication blockers Fabrication remains blocked until all of the following are closed or deliberately diff --git a/docs/hardware/images/panda-pwr/panda-pwr-board-angle.jpg b/docs/hardware/images/panda-pwr/panda-pwr-board-angle.jpg new file mode 100644 index 0000000000000000000000000000000000000000..19a11b0116d68e32faaae66dedd0af1534877e78 GIT binary patch literal 226931 zcmb5VbyOT*@Gm$7f+VyXscms!!kU`nUM+CxB30Sxp&$h6VtjJu%?l3P1sX{_NR* z+Y@0tZO^fvKgYm${sIdN6C3vhF7C@0FJI!}6BFX$6XCynNk~peL_$hNMutm3K}k+Z zNlZ#c`rl2^(4Vfsc#iY@ISwh_OFYv5-}J8+K!p9Q9K#qLjS29K2o0SG?O#8D761TX z{U`1JA+%>tGGbz3|JRE4zv+Lq|L@ji04_Qj;29x0;ghQ8hqSgp-S>{##DM%HN{0W{ z835qdXV$16%@|kIz$#wt2xC3HUv904@Vczb;&#`1LA||}hLY^bUf5f2ID9$zssZXO zR5my-DWqkh)a~Idu^vwW-0qSB4X~@xN!{me7c-ZN6UbbiCo(xp4oRQwAr{6UN9TKs z%X4a3HQlw4q(2ki*goO_-mENWWjvVq8;!o37e`T!4$j+m*|5o;{7FB!y9Gj9z1fVj(i) zW#g~Of{T(~H+ZKD7tCAz{R06od#F*m@K8))?OLvnCx~l^v*o};nay&@HIaSIP5bWnA(V&b&zZAI03Az6;DGxCeONroOY#ohj`fuM(TPoL{}s>xoE7 zGglBF;0_5#=H_W-cva9@8hS;CsLPF&`uHb=2>R{Vl(@{=7athvb-2G+a7ate_-){< zON{$5m4P^lNdSO@1|XtVP-S?=gZl{sfQB($91UOyFhraB|LUuo&9yv{eBkk_hX_gK zvirb+9kn2n(1;Yxf2RT??#)_I-l$C37w2X-4N!J5&z-fIFD~U6S66%oZ(R1C+f@>` zkJL~{U(;rNQ;Oa zp1lD8aHBA>F_T_DLrZy!MrilqNg2YogxDXI!;#^mMCUPc+FC)vt}%XyMtu>B7WL1Y zmBkr0#q@6hKL4XORWyEe0=sHP@tGa3rx~g$Dk$I7(NtCy<=-QCNNJx(FqMR`F=Qzc zW|DmGwx=f2K&~lm`n!0+h1|IW0-mscjk0vYnF~-ck}6dz1Ik;x!o?{Ysh@y}kijHA zOiFVTe;@b#U^$+%LzJWS8fU^CNgQT{FYk7-;e9@v!jr%tZ7(U!K~Yw>yFw=ms+Dz? z#2MY3OE34HV##p+Ov+kPc6sLQJ(Xtcd?cSb~|hLhW`@7bOQpI^DL z3l+LL7JWqow<8GC5#9#a7p#)l7d$){Fa=8q8a#vU$wZY8zjj-woN_~odHKgx*#?=5 zN4+iBUP>l0MccDR3{&H^i)lqSDfu+TG!^o#-yhGJu$OYjRMhVZ#Y4&qlpy2!EUnJv zIax(@WoVPIz1dq1dc%Nr2W=7`;lzT z40npSYxf@K((JlGFu#-Z9O84>&<3i&Pp>9n4QzQoLvzhPnBV4E4)}8JyHOYj;+dFF zm^&g~zaxK>=A-iEY%cyL_-&(_O4D#tg;Q*rjsIhZl;ZV3}I_1ec z)^V^3I{Lx=esodY_Y`uqXP>b>Ina`m-p&A46bmeWxEgwD@!M@1k5?<`wb)XY%qbNH zXH)6$*qTv{6*g7H1zsHrBs$3{F-=8j1cy^QcD=3gDOqm@{)U2r;bDs8WGOKwmmCjV$`>sVGrbzhvXH1phS zGs|Ie_ZVMd_80%mXstm~yQ$~|9J6cL=(5xOw~dboLii|!tAx>RJ8ukmn26HzC-rL^ zJa3O-hqO22E6)`w#(l1gu;+TB9_Eng?H&Y8@Yc1SY;QfB1mkhCZR+}T)ibiAwu=cN z&1oh+XsNQVdzPMrIa5h=RpXS%d^%P0@f^JxI4fmxL}ST_+-#E%t7$OABNcZx%w&(v z%$g(5G87j{Rb9eJ-^Hunt9aLVsBIpt(!Mcfye%u+6CxE z%;W(pO{8jgjKBXQ0b}pk8%};dwBOyY^wpQMlGP%FfZQZ3!#m@&RL=zb*Tveg+Lzr# zUM18_Gj-}=-PjP?-NWCBT)j&F!Y8|PmoPp4)Ev;(6}Bygza1S^AB zPD?Am0jLJ4f~>lXJaR;hobv~0RYOUZw#`eg<-TM-_4(rs&Lfd#;-6m+C^@p_OqV2v zitxLft2j?Tjd;J9X|fl9TkFZ{v8heYDmUM@V`n(i4h@L#*hOTuQW@jv4#WlwbdvAc z*x&VVh>{uw3FJ9Wy2tC`K#{npiq16~_*PNC2GEO&5;be{^OAU}$(mXJs|-AMF9owA zgpDVDdewXO(rb3#<$%@H{u&7E{9;=${y20&>@U`lo8y!6>-T+VZhFjw@)h{huk-wG zq-x`7-Bqv-Pt)~I(KADaoo&5BjpmH{^DpK*m%4*Wjw5#lM}E8KkGYy2dhxbwsNDTd zG>;wcdF&faUI~W+eLK1Z>TQxH*P)^HMsI|4Aa04HLhvB{7SmqIMx#L+m@;ZDrV!n) zk|C$LMr|xXG37#)@|&XAuwRihPdU*JZzc@QF4J9|urFS(Q}b;q>G#=YPCLcS3#S0w z)>uWyq<9e&5fF-<3fRVL1Fe})yZ-{4HdT%!(Sqo9iZD-9V{pj`JH|p`@dD>B_q~jL zj$yHN{!_PBa<`8NF^XWw{sUdjZWC73c*ykab&#cd6OGtl>6XlM3;v{|?$EhF@D0Yf z@0m2PTMxg3IAAv5B<^<&z3)`Fok_k)APp=E~ARkK=JqQ zT&FKW7HyticiXJKEsN6LM3(6ryYz6}R2`S;{yH0j`-pFJoC}IuLMLT(7FL%{dM>1! z3k!Rz3mFuPd|ARJSi$uiYJ5$Y=UZIS!GnutHkw8-VGb-VS4}^rNUAamMdu_B5yn3T zTR4k@q>xQL9__xQ9m?LBN_O2#?27twSB-b6WbaAKPiG9bB3C{>P$qmEAGVG5;t|LB z$wU*aSdp((S4NCtFz$~hB`Vyl_H9HTU(Ix(tb;$W48(`uXCaZBLq-C!|RI zbC(j#d%Fof$WlOL^MkNxu7Qk?#B5y5lt~Z+HYx5%+OqiK?y!}!?8Pk+%hF6F8|4Bs zpe5!mUW$0%V?bgldfX>B04720I-E`WadSyiV&BqDJ7!>ffW=(Oy&%~%yW>=W&9X!x z332LYatmv|XmO-&aGn=0veGhjv0iGG{qVrIziVnDe)GsPpeKuPg{8KwY0fQQti9ld zR2Uw+teuw`4h6I(?nhmGpxibA?A*;U(^LM zlATS%3`Y~x-z7j*!)r2JLH345IljUKMjCd$%~i3UXbPVgHY16z8JK>OwqV?L??_WC zrZuONw~rK$eouP)g0Ut+C%{t*qCYvPuN`qUX=*M}V=DSCR@6p8TOu$XE4?_h7I7!L z@du{~`$XBH*$$(=1}19&FyqJwpYY&B?KEg>b4}3Ch%d-pt1Fgo(0C);wCT&1$1*V*V| ze+w;G%y`XhpPAK!_;6*HU}ly@>THj)YoRAL6&v9+Fx|W0A9WJ8<}E}}gA9u6_u7eX z_}nUZ+E5V-2sYJd4U_4M)TPd-rEy_LAk&~zb+r)tOI8j=Mc&1hDhK5l&KrI^IoBUJ zT8A<=&rF4ml~{VQFFvf{yE;UBa_y#Iya8Wd-T!W*`uoR?ppg59c14S;1|`t)l5Md5 zr}_a08=rkF3+jXT3cFI`M?VYSgxDf))WF(WdgkwGFNAIlf6jtn`L6F0Z|Cpj?tg%R zqx59Qz+i)K%dRcc=k9xY!WSVeQ}10xg>H@Nkc52B@UBq*8i9Hlk7gyKT9&9g3bZhCfxU)p21#veny|h9k5S}vzdUn&|2Bo9W5h0~$WiJSgRorkNv!<3oGe<-R6cWGe1phSu zp}YJ%2uvZ2x<}TgeI*jmpL?&v zB~ahq1^)wBkagucuI(+~woK6n{jsvO`vSiWQy=)lrsK&Oi{+wbFLtS#xncuLwPezm z)5#ct$CG;!;y6_iPeeaw*OMpeD;2;CvZ$MKYq$aV>UqS?o7*QKFR~O={o$@Io2(LP zkKpF*wmBWzx{JV0sFPP@TJRLfERIv1lpDZihzO9S%n3=wx-H^UhK^ti| ziCme=*6$8$Q|ybDZrvrX=~MHkCkuzy(ZBs=^x=Hb^;-f$aj=M=SWyVMB_5qnN^UEU zA+aOO9nlwO&eX10!d5|U)}e}${*a^Q_GZL2GrVEW*jM<&yqKqE$`uI3)?^k4gx3sY zjXCTFx?*xS7?NuU&5qKi>$~uBvULVn)spj<{JzWq@HzwmX; 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a/docs/hardware/panda-pwr-characterization.md b/docs/hardware/panda-pwr-characterization.md new file mode 100644 index 0000000..7b1f745 --- /dev/null +++ b/docs/hardware/panda-pwr-characterization.md @@ -0,0 +1,273 @@ +# BIGTREETECH Panda PWR teardown characterization + +> **EXTERNAL REFERENCE HARDWARE / NOT A JUMPJET DESIGN SOURCE.** This record +> documents a third-party product for architecture review only. It is not a +> JumpJet BOM source, does not select any JumpJet component, does not authorize +> copying the Panda PWR design, and does not establish safety compliance for any +> product. + +> [!WARNING] +> **Mains hazard.** The Panda PWR is a mains-powered device. Destructive +> teardown removes the original enclosure and its touch protection. Any +> measurement on an exposed, energized board must be treated as potentially +> lethal. Prefer unpowered continuity characterization first, and energize an +> opened unit only with appropriate isolation, equipment, and procedures. +> Neither firmware behavior nor observed architecture substitutes for safety +> certification. No Panda PWR safety feature is copied into JumpJet without +> independent engineering review. + +## 1. Scope and status + +This record captures what a direct teardown of one Panda PWR unit establishes +about its hardware, and what it does not. It is useful to JumpJet as reference +evidence for: + +- mains switching architecture +- isolated auxiliary power +- isolated voltage/current sensing and metering architecture +- controller / metering partitioning +- service and debug interfaces +- enclosure and mechanical reference + +It does not contain a schematic. The architecture in +[section 6](#6-current-architecture-interpretation) is an interpretation of +component identity and placement, not a continuity-derived circuit. + +### Status classes + +This record uses the status classes defined in the +[Phase 1 hardware register](../PHASE1_HARDWARE_REGISTER.md#status-legend), with +the following qualifiers: + +| Status | Use in this record | +|---|---| +| CONFIRMED FACT | A readable package/label marking, a direct physical observation, or an authoritative cited source supports it. A confirmed marking confirms component identity only, not circuit function or connection. | +| ASSUMPTION / PROVISIONAL — strong / high-confidence inference | Location, form, and architecture strongly suggest an identity or function, but no readable marking or continuity evidence proves it. | +| ASSUMPTION / PROVISIONAL | A plausible identity or function with weaker support. | +| TBD / BLOCKED | Not yet established; requires continuity, firmware, or further inspection. | + +## 2. Specimen identity and provenance + +| Property | Value | +|---|---| +| Product | BIGTREETECH Panda PWR | +| Revision | Rev 1 | +| Quantity inspected | One physical unit | +| Condition | Enclosure destructively opened for characterization | +| Inspection | Unit inspected directly | +| Photographs | Daniel Brown | +| Date | 2026-09-27 | +| Comparison material | FCC internal photographs were used earlier for comparison. They are **not** reproduced in this repository unless their licensing/provenance is established to permit it. | + +### FCC model-difference declaration + +| Property | Value | Verification | +|---|---|---| +| FCC ID | `2BAS6-PANDAPWR` ([fccid.io/2BAS6-PANDAPWR](https://fccid.io/2BAS6-PANDAPWR)) | Supplied by Daniel Brown; consistent with third-party FCC-mirror index entries | +| Grantee | Shenzhen BIQU Innovation Technology Co., Ltd. (grantee code `2BAS6`) | Third-party FCC-mirror index | +| Exhibit | "Model Difference" letter, dated 2024-07-17 | Third-party mirror of the exhibit ([manuals.plus copy](https://manuals.plus/m/d2ffb86b9c70f673e9e77e69a77a697aba42d3293698eece14e3dcbeb16183a3)) | +| Declared statement | Product Panda PWR (trademark BIGTREETECH) covers models **Panda PWR, Panda PWR Lite, and Panda PWR Pro**, which are declared to be "the same circuit and RF module, except appearance color and model name." | Search-index excerpt of the mirrored exhibit | + +**Verification limit.** On 2026-09-27 the FCC equipment-authorization site, +fccid.io, and the mirrors of the exhibit all refused automated access from the +documentation environment (HTTP 403). The statement above comes from +search-index excerpts of the mirrored exhibit, not from a direct read of the +FCC primary document. Check the wording against the exhibit on the FCC +equipment-authorization system before relying on it. Until then, treat it as +the reported content of the declaration. + +**What it supports.** Taking the excerpt at face value, it is an FCC-declared +circuit and RF-module relationship among the three listed models. It +distinguishes declared circuit identity from appearance (color) and model +name. It does **not** state that PCB layout, component sourcing, or physical +construction is identical across units or production lots. It says nothing +about enclosure mechanics beyond appearance. + +**What it does not cover.** + +- A separate FCC ID, `2BAS6-PANDAPWRV2` ("Panda PWR"), also appears in the + third-party index. This declaration does not cover it, and this record makes + no claim about how a V2 product relates to the unit characterized here. +- The FCC ID on the specimen's own label has not been recorded in this + document. Record it to tie this Rev 1 unit to `2BAS6-PANDAPWR`. + +## 3. Evidence photographs + +These four images are crops/enhancements of the real teardown photographs. They +are primary photographic evidence; no generated or reconstructed imagery is +used. Metadata (EXIF/XMP) was verified absent before commit. + +Panda PWR Rev 1 PCB, component side, after enclosure opening + +*Figure 1 — Panda PWR Rev 1 PCB after destructive enclosure opening; overall +component-side layout.* + +Panda PWR Rev 1 angled view of HLK-20M05, relay, sensing magnetics, and USB ports + +*Figure 2 — Panda PWR Rev 1 angled view showing component heights, HLK-20M05, +relay, sensing magnetics, USB ports, and controller end.* + +Panda PWR mains protection and sensing area + +*Figure 3 — Mains protection and sensing area showing T2A fuse, relay, +ZMPT107-1, unidentified EI-core transformer, suppression components, and +common-mode choke.* + +HLW8112 metering IC package marking + +*Figure 4 — HLW8112 metering IC marking and surrounding analog network.* + +Full-resolution files are in [`images/panda-pwr/`](images/panda-pwr/). + +## 4. Confirmed component identities + +A confirmed identity below means the part is present on the board. Unless a row +says otherwise, its connections, operating point, and exact circuit role are +**not** established. + +| Item | Status | Identity / marking | Evidence | Role | Not yet established | +|---|---|---|---|---|---| +| Controller | CONFIRMED FACT | Espressif `ESP8684-MINI-1-H4` module | Direct inspection of the unit; BIGTREETECH's published Panda PWR documentation lists "ESP8684-MINI-1-H4" as the Wi-Fi module ([source](https://github.com/bigtreetech/docs/blob/master/docs/Panda%20PWR.md)). The module marking is not legible in the four committed crops; the module is at the right-hand (controller) end in Figures 1–2. | Primary wireless/application controller | Any GPIO assignment, protocol mapping, or peripheral wiring | +| Auxiliary PSU | CONFIRMED FACT | Hi-Link `HLK-20M05`. Label: `INPUT: 100-240VAC 0.4A 50-60Hz`, `OUTPUT: 5VDC 4A 20W`, `P/N: HLK-20M05`; pins marked `AC`, `AC`, `+Vo`, `-Vo`; CE, RoHS, and double-square symbol marks | Figures 1–2 | Isolated mains-to-5-V auxiliary supply | Downstream 5 V rail topology; actual load; whether and how 3.3 V is derived | +| Load relay | CONFIRMED FACT | Songle `SRD-05VDC-SL-B`. Markings include `10A 250VAC`, `10A 125VAC`, `10A 30VDC` (twice), and CQC and UL-style recognition marks | Figures 1–3 | Relay used for AC load switching | Exact COM/NO routing; coil drive circuit; whether it is the only load-switching element | +| Metering IC | CONFIRMED FACT | `HLW8112`, secondary marking `2423W1D` (read as a date/lot code; not decoded), 16-lead package | Figure 4 | Energy/power metering IC | Current channel used; voltage channel used; SPI vs UART; digital wiring; calibration constants; ESP GPIO mapping | +| Voltage-sensing transformer | CONFIRMED FACT | `ZMPT107-1` with Chinese-language manufacturer text | Figures 1, 3 | Isolated AC voltage sensing in the metering front end | Continuity to the HLW8112 voltage input; primary-side series resistance; sampling resistor | +| Fuse marking | CONFIRMED FACT | Black rectangular fuse body marked `T2A 250V`, `Jdtfuse`, with CQC and UL-style recognition marks | Figure 3 | Fuse | **Which branch it protects.** It is a separate component from the glass cartridge in clips at the board edge. Nothing here establishes that it protects the switched 10 A load path. | + +### Published specifications used + +Only the following manufacturer-derived specifications are recorded. Nothing +here is a JumpJet requirement. + +**ZMPT107-1** — from the manufacturer specification by Qingxian Zeming Langxi +Electronic ([ZMPT107-1 specification](https://5nrorwxhmqqijik.leadongcdn.com/ZMPT107-1+specification-aidiqBqoKomRilSqqnnkikq.pdf)): + +| Property | Published value | +|---|---| +| Type | Current-type voltage transformer | +| Rated input / output current | 2 mA / 2 mA | +| Turns ratio | 1000:1000 | +| Linear range | 0–1000 V; 0–10 mA (50 Ω sampling resistor) | +| Isolation voltage | 3000 V AC | +| Operating temperature | −40 to +85 °C | +| Encapsulation | Epoxy, PCB mounting | + +**HLW8112** — the manufacturer (Hiliwei Tech) datasheet PDF was not retrieved. +The distributor listing ([LCSC C970140](https://www.lcsc.com/product-detail/C970140.html)) +describes it as a metering IC with two current channels (A and B) and one +voltage channel, an SPI/UART interface, 3.0–3.6 V or 4.5–5.5 V supply, and a +16-lead SSOP package. Treat these as provisional until they are checked against +the manufacturer datasheet. They do not show which channels or which interface +this board uses. + +**HLK-20M05** — only the printed label (above) is recorded. No datasheet-derived +isolation, efficiency, or protection claim is made. + +## 5. Other directly observed components + +| Item | Status | Observation | Identity / function | Remaining evidence | +|---|---|---|---|---| +| Yellow EI-core transformer | ASSUMPTION / PROVISIONAL — strong inference | Large EI/EE-style ferrite core with yellow-taped winding in the metering/sensing region, adjacent to the ZMPT107-1 (Figure 3). No readable part number. | Likely current-sensing transformer. Its location and the metering architecture strongly suggest current sensing. **Unconfirmed.** | Readable marking or continuity from the load-current path and to an HLW8112 current input | +| Green toroid | ASSUMPTION / PROVISIONAL — high-confidence inference | Toroidal core with two copper windings separated by a green divider (Figures 1–3) | Likely common-mode choke / EMI filter. Part identity is not confirmed. | Marking, continuity, winding count | +| Blue disc | ASSUMPTION / PROVISIONAL | Blue epoxy-coated disc component beside the fuse (Figure 3); marking not read | Possibly a MOV or other mains transient-suppression part | Marking or continuity | +| Yellow rectangular capacitor | ASSUMPTION / PROVISIONAL | Yellow rectangular box component beside the blue disc (Figure 3); marking not read | Likely a mains EMI/safety film capacitor. **Not identified as X1/X2**, because its marking has not been read. | Marking | +| Glass cartridge fuse | TBD / BLOCKED | Glass cartridge fuse in PCB clips along the top edge (Figures 1, 3); rating not legible in the committed images | Fuse. It is a separate part from the `T2A 250V` black-body fuse. | Read the cartridge end-cap marking; map its branch | +| AC connector block | TBD / BLOCKED | Black mains contact/connector block at the left board edge (Figures 1–2) | Mains interface; exact role (inlet, outlet, or both) not established from these images | Continuity and mechanical inspection | +| RGB status LED | CONFIRMED FACT (presence) | LED at the controller end beside `RGB` silkscreen (Figure 1) | Status indication | Drive circuit and GPIO | +| USB-A connectors | CONFIRMED FACT (presence) | Two USB-A receptacles (Figures 1–2). BIGTREETECH documentation states the USB-A ports are output only. | Peripheral USB power output | Switching/current-limit circuit and rail source | +| USB-C connector | CONFIRMED FACT (presence) | One USB-C receptacle (Figures 1–2). BIGTREETECH documentation states the Type-C port is input only and is used for firmware burning and factory reset. | Service connector | Data/power wiring; any power path into the board rails | +| Reset control | CONFIRMED FACT (presence) | Tactile button beside `RESET` silkscreen between the USB-A ports (Figures 1–2) | Reset/service control | What it is wired to | +| Service header pads | CONFIRMED FACT (silkscreen) | Pad row at the controller end, silkscreened approximately `GND RX TX 3V3` (Figures 1–2) | Likely a UART service header, inferred from the silkscreen only | Continuity to the ESP8684 and the actual voltage levels | +| Mounting holes | CONFIRMED FACT (presence) | Plated mounting holes at the board corners (Figures 1, 3) | Mechanical mounting | Coordinates and diameters | +| Passive markings near HLW8112 | CONFIRMED FACT (marking) | SMD resistors marked `330` and `472` beside the HLW8112 (Figure 4) | Part of the surrounding analog/digital network; role not established | Continuity | +| `AP65N06NF` | ASSUMPTION / PROVISIONAL | Reported from a teardown photograph that is not in the committed evidence set; not independently verified here | If the marking and package are confirmed, a distributor listing identifies A Power Microelectronics `AP65N06NF` as a 60 V N-channel MOSFET in a PDFN package ([JLCPCB C3011335](https://jlcpcb.com/partdetail/A_Powermicroelectronics-AP65N06NF/C3011335)). **Circuit function TBD.** A ~60 V device is not the 120/240 VAC load switch; its low-voltage role still needs tracing. | Add a legible photograph; confirm package against datasheet; trace circuit | +| Other low-voltage ICs | TBD / BLOCKED | Additional USB/service/power-support ICs visible near the USB connectors (Figures 1–2) | No part number is promoted; the markings are not unambiguous in the committed images | Legible macro photographs | + +## 6. Current architecture interpretation + +> **CURRENT INTERPRETATION, NOT A COMPLETED SCHEMATIC.** This is inferred from +> component identity and placement. No continuity has been mapped. Every arrow is +> provisional. + +```text +Mains switching (provisional): + + AC input + -> fuse / surge / EMI network (fuse branch TBD; suppression parts provisional) + -> SRD-05VDC-SL-B relay (COM/NO routing TBD) + -> switched load output + +Auxiliary power (provisional): + + AC input + -> HLK-20M05 + -> isolated 5 V low-voltage domain (rail topology TBD) + -> ESP8684-MINI-1-H4 / USB / support electronics (3.3 V derivation TBD) + +Metering (provisional): + + AC voltage + -> ZMPT107-1 (confirmed part; connection TBD) + -> analog conditioning + -> HLW8112 voltage channel (channel TBD) + + Load current + -> unidentified sensing transformer / front end (yellow EI-core: strong inference only) + -> analog conditioning + -> HLW8112 current channel (channel A/B TBD) + + HLW8112 + -> digital interface (SPI or UART TBD; pins TBD) + -> ESP8684-MINI-1-H4 (GPIOs TBD) +``` + +**Architectural observation.** The isolated sensing magnetics and the isolated +HLK-20M05 together suggest that the metering and controller electronics can sit +on the isolated low-voltage side. That fits the exposed USB and service +interfaces. It is an observation, not a finding: the board has **not** been +isolation-mapped, and no creepage, clearance, or isolation-boundary claim is +made until continuity and creepage tracing are complete. + +## 7. JumpJet relevance + +This teardown belongs in the repository as useful reference evidence for: + +- architecture partitioning between mains/power and controller domains +- an isolated auxiliary supply feeding controller and service electronics +- relay control of a load path +- a measurement front end with isolated voltage and current sensing +- component packaging and board density +- serviceability: USB service connector, reset control, UART-style header +- enclosure constraints for a compact power product + +It is **not** a design mandate: + +- JumpJet remains a 24 V chamber-heater controller governed by its own + [product safety contract](../PRODUCT_SAFETY_CONTRACT.md). +- The Panda PWR runs from mains and has a different hazard model. +- No Panda PWR component becomes a JumpJet selection because it appears here. + Any JumpJet candidate goes through the + [hardware register](../PHASE1_HARDWARE_REGISTER.md) process on its own + evidence. + +## 8. Remaining characterization + +- [ ] map AC input -> fuse -> relay -> output continuity +- [ ] determine exactly what the `T2A 250V` fuse protects, and read and map the glass cartridge fuse +- [ ] identify relay COM/NO routing +- [ ] identify the yellow EI-core transformer +- [ ] continuity-map ZMPT107-1 to the HLW8112 voltage input +- [ ] continuity-map the current-sense path to the HLW8112 +- [ ] map the HLW8112 digital interface to the ESP8684 +- [ ] identify the bus type actually used (SPI or UART) +- [ ] map ESP GPIOs only after continuity/firmware evidence +- [ ] photograph `AP65N06NF` legibly, confirm the package, and identify its circuit function +- [ ] identify the remaining regulator / USB support devices +- [ ] establish 5 V and 3.3 V rail topology +- [ ] map the isolation boundary and creepage/clearance regions +- [ ] inspect the PCB backside and current-carrying copper +- [ ] capture PCB dimensions, mounting-hole coordinates, connector positions, and maximum component heights +- [ ] capture enclosure dimensions before or while designing a replacement enclosure +- [ ] verify the `2BAS6-PANDAPWR` model-difference wording against the FCC primary exhibit +- [ ] record the FCC ID printed on the specimen label +- [ ] produce a partial schematic from measured continuity, not visual guesswork From de5613cae20874b93d2b24593a768af05d288df8 Mon Sep 17 00:00:00 2001 From: Daniel Brown Date: Sun, 27 Sep 2026 16:51:48 +0000 Subject: [PATCH 20/20] Revert "docs: record Panda PWR teardown findings" This reverts commit a4def1c81ed0399a4c0213b23a7024d6727c12ac. The Panda PWR teardown record belongs in danielbrownjr/DragonPWR, not JumpJet. It moved there in danielbrownjr/DragonPWR#10. --- docs/PHASE1_HARDWARE_REGISTER.md | 13 +- .../panda-pwr/panda-pwr-board-angle.jpg | Bin 226931 -> 0 bytes .../panda-pwr/panda-pwr-board-overview.jpg | Bin 120161 -> 0 bytes .../panda-pwr-hlw8112-metering-ic.jpg | Bin 118279 -> 0 bytes .../panda-pwr/panda-pwr-sensing-section.jpg | Bin 211799 -> 0 bytes docs/hardware/panda-pwr-characterization.md | 273 ------------------ 6 files changed, 1 insertion(+), 285 deletions(-) delete mode 100644 docs/hardware/images/panda-pwr/panda-pwr-board-angle.jpg delete mode 100644 docs/hardware/images/panda-pwr/panda-pwr-board-overview.jpg delete mode 100644 docs/hardware/images/panda-pwr/panda-pwr-hlw8112-metering-ic.jpg delete mode 100644 docs/hardware/images/panda-pwr/panda-pwr-sensing-section.jpg delete mode 100644 docs/hardware/panda-pwr-characterization.md diff --git a/docs/PHASE1_HARDWARE_REGISTER.md b/docs/PHASE1_HARDWARE_REGISTER.md index 4ab613d..8c5f88b 100644 --- a/docs/PHASE1_HARDWARE_REGISTER.md +++ b/docs/PHASE1_HARDWARE_REGISTER.md @@ -1,6 +1,6 @@ # Phase 1 hardware source-of-truth register -Last updated: 2026-09-27 +Last updated: 2026-09-08 This is the living engineering register for JumpJet Rev A Phase-1 hardware implementation. It records what is known, how it is known, what remains @@ -229,17 +229,6 @@ identify a valid production cutoff temperature or mounting location. | High-current placement priority | DESIGN DECISION | Place and review `+24V_PROT -> F2 -> TF1 -> TS1 -> J2 -> heater -> Q1 -> GND` before convenience circuitry. Keep Q1, J2, F2, and the heater-current path compact without weakening conductor geometry for appearance. | Rev A.4.1 topology and Phase-1 implementation priority | High | Complete placement, current-loop, service-clearance, and thermal review. | PCB layout + Fabrication | | PCB validation | TBD / BLOCKED | Current-density bottlenecks, Q1 thermal spreading, fuse-holder and J2 pad heating, high-current return geometry, ADC noise, antenna keepout, DRC, fabricated-board temperature rise, and full-path voltage drop are unvalidated. | No Rev A PCB exists yet | High confidence that validation is pending | Create the board, review design evidence, fabricate only after blockers close, then thermally/electrically test production-intent hardware. | PCB layout + BOM freeze + Fabrication | -## 11. External reference hardware - -External products characterized for architecture review only. Entries here do -not select JumpJet components, are not BOM sources, and do not establish JumpJet -safety or compliance evidence. Component detail lives in the linked records, not -in the JumpJet production tables above. - -| Item | Status | Current value / decision | Evidence / source | Confidence | Remaining validation | Blocks | -|---|---|---|---|---|---|---| -| BIGTREETECH Panda PWR Rev 1 teardown | CONFIRMED FACT | External/reference evidence only. Direct teardown confirms `ESP8684-MINI-1-H4`, `HLK-20M05`, `SRD-05VDC-SL-B`, `HLW8112`, `ZMPT107-1`, and a `T2A 250V` fuse marking. Sensing-path, fuse-branch, relay-routing, isolation-boundary, and 5 V / 3.3 V rail topology remain partly unmapped. Informs architecture review only; selects no JumpJet component. | [Panda PWR characterization](hardware/panda-pwr-characterization.md); destructive teardown photographs, 2026-09-27 | High for listed markings; low for circuit topology | Unpowered continuity mapping, isolation/creepage mapping, and verification of the FCC `2BAS6-PANDAPWR` model-difference wording against the primary exhibit, per the characterization record. | None | - ## Current fabrication blockers Fabrication remains blocked until all of the following are closed or deliberately diff --git a/docs/hardware/images/panda-pwr/panda-pwr-board-angle.jpg b/docs/hardware/images/panda-pwr/panda-pwr-board-angle.jpg deleted file mode 100644 index 19a11b0116d68e32faaae66dedd0af1534877e78..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 226931 zcmb5VbyOT*@Gm$7f+VyXscms!!kU`nUM+CxB30Sxp&$h6VtjJu%?l3P1sX{_NR* z+Y@0tZO^fvKgYm${sIdN6C3vhF7C@0FJI!}6BFX$6XCynNk~peL_$hNMutm3K}k+Z zNlZ#c`rl2^(4Vfsc#iY@ISwh_OFYv5-}J8+K!p9Q9K#qLjS29K2o0SG?O#8D761TX z{U`1JA+%>tGGbz3|JRE4zv+Lq|L@ji04_Qj;29x0;ghQ8hqSgp-S>{##DM%HN{0W{ z835qdXV$16%@|kIz$#wt2xC3HUv904@Vczb;&#`1LA||}hLY^bUf5f2ID9$zssZXO zR5my-DWqkh)a~Idu^vwW-0qSB4X~@xN!{me7c-ZN6UbbiCo(xp4oRQwAr{6UN9TKs z%X4a3HQlw4q(2ki*goO_-mENWWjvVq8;!o37e`T!4$j+m*|5o;{7FB!y9Gj9z1fVj(i) zW#g~Of{T(~H+ZKD7tCAz{R06od#F*m@K8))?OLvnCx~l^v*o};nay&@HIaSIP5bWnA(V&b&zZAI03Az6;DGxCeONroOY#ohj`fuM(TPoL{}s>xoE7 zGglBF;0_5#=H_W-cva9@8hS;CsLPF&`uHb=2>R{Vl(@{=7athvb-2G+a7ate_-){< zON{$5m4P^lNdSO@1|XtVP-S?=gZl{sfQB($91UOyFhraB|LUuo&9yv{eBkk_hX_gK zvirb+9kn2n(1;Yxf2RT??#)_I-l$C37w2X-4N!J5&z-fIFD~U6S66%oZ(R1C+f@>` zkJL~{U(;rNQ;Oa zp1lD8aHBA>F_T_DLrZy!MrilqNg2YogxDXI!;#^mMCUPc+FC)vt}%XyMtu>B7WL1Y zmBkr0#q@6hKL4XORWyEe0=sHP@tGa3rx~g$Dk$I7(NtCy<=-QCNNJx(FqMR`F=Qzc zW|DmGwx=f2K&~lm`n!0+h1|IW0-mscjk0vYnF~-ck}6dz1Ik;x!o?{Ysh@y}kijHA zOiFVTe;@b#U^$+%LzJWS8fU^CNgQT{FYk7-;e9@v!jr%tZ7(U!K~Yw>yFw=ms+Dz? z#2MY3OE34HV##p+Ov+kPc6sLQJ(Xtcd?cSb~|hLhW`@7bOQpI^DL z3l+LL7JWqow<8GC5#9#a7p#)l7d$){Fa=8q8a#vU$wZY8zjj-woN_~odHKgx*#?=5 zN4+iBUP>l0MccDR3{&H^i)lqSDfu+TG!^o#-yhGJu$OYjRMhVZ#Y4&qlpy2!EUnJv zIax(@WoVPIz1dq1dc%Nr2W=7`;lzT z40npSYxf@K((JlGFu#-Z9O84>&<3i&Pp>9n4QzQoLvzhPnBV4E4)}8JyHOYj;+dFF zm^&g~zaxK>=A-iEY%cyL_-&(_O4D#tg;Q*rjsIhZl;ZV3}I_1ec z)^V^3I{Lx=esodY_Y`uqXP>b>Ina`m-p&A46bmeWxEgwD@!M@1k5?<`wb)XY%qbNH zXH)6$*qTv{6*g7H1zsHrBs$3{F-=8j1cy^QcD=3gDOqm@{)U2r;bDs8WGOKwmmCjV$`>sVGrbzhvXH1phS zGs|Ie_ZVMd_80%mXstm~yQ$~|9J6cL=(5xOw~dboLii|!tAx>RJ8ukmn26HzC-rL^ zJa3O-hqO22E6)`w#(l1gu;+TB9_Eng?H&Y8@Yc1SY;QfB1mkhCZR+}T)ibiAwu=cN z&1oh+XsNQVdzPMrIa5h=RpXS%d^%P0@f^JxI4fmxL}ST_+-#E%t7$OABNcZx%w&(v z%$g(5G87j{Rb9eJ-^Hunt9aLVsBIpt(!Mcfye%u+6CxE z%;W(pO{8jgjKBXQ0b}pk8%};dwBOyY^wpQMlGP%FfZQZ3!#m@&RL=zb*Tveg+Lzr# zUM18_Gj-}=-PjP?-NWCBT)j&F!Y8|PmoPp4)Ev;(6}Bygza1S^AB zPD?Am0jLJ4f~>lXJaR;hobv~0RYOUZw#`eg<-TM-_4(rs&Lfd#;-6m+C^@p_OqV2v zitxLft2j?Tjd;J9X|fl9TkFZ{v8heYDmUM@V`n(i4h@L#*hOTuQW@jv4#WlwbdvAc z*x&VVh>{uw3FJ9Wy2tC`K#{npiq16~_*PNC2GEO&5;be{^OAU}$(mXJs|-AMF9owA zgpDVDdewXO(rb3#<$%@H{u&7E{9;=${y20&>@U`lo8y!6>-T+VZhFjw@)h{huk-wG zq-x`7-Bqv-Pt)~I(KADaoo&5BjpmH{^DpK*m%4*Wjw5#lM}E8KkGYy2dhxbwsNDTd zG>;wcdF&faUI~W+eLK1Z>TQxH*P)^HMsI|4Aa04HLhvB{7SmqIMx#L+m@;ZDrV!n) zk|C$LMr|xXG37#)@|&XAuwRihPdU*JZzc@QF4J9|urFS(Q}b;q>G#=YPCLcS3#S0w z)>uWyq<9e&5fF-<3fRVL1Fe})yZ-{4HdT%!(Sqo9iZD-9V{pj`JH|p`@dD>B_q~jL zj$yHN{!_PBa<`8NF^XWw{sUdjZWC73c*ykab&#cd6OGtl>6XlM3;v{|?$EhF@D0Yf z@0m2PTMxg3IAAv5B<^<&z3)`Fok_k)APp=E~ARkK=JqQ zT&FKW7HyticiXJKEsN6LM3(6ryYz6}R2`S;{yH0j`-pFJoC}IuLMLT(7FL%{dM>1! z3k!Rz3mFuPd|ARJSi$uiYJ5$Y=UZIS!GnutHkw8-VGb-VS4}^rNUAamMdu_B5yn3T zTR4k@q>xQL9__xQ9m?LBN_O2#?27twSB-b6WbaAKPiG9bB3C{>P$qmEAGVG5;t|LB z$wU*aSdp((S4NCtFz$~hB`Vyl_H9HTU(Ix(tb;$W48(`uXCaZBLq-C!|RI zbC(j#d%Fof$WlOL^MkNxu7Qk?#B5y5lt~Z+HYx5%+OqiK?y!}!?8Pk+%hF6F8|4Bs zpe5!mUW$0%V?bgldfX>B04720I-E`WadSyiV&BqDJ7!>ffW=(Oy&%~%yW>=W&9X!x z332LYatmv|XmO-&aGn=0veGhjv0iGG{qVrIziVnDe)GsPpeKuPg{8KwY0fQQti9ld zR2Uw+teuw`4h6I(?nhmGpxibA?A*;U(^LM zlATS%3`Y~x-z7j*!)r2JLH345IljUKMjCd$%~i3UXbPVgHY16z8JK>OwqV?L??_WC zrZuONw~rK$eouP)g0Ut+C%{t*qCYvPuN`qUX=*M}V=DSCR@6p8TOu$XE4?_h7I7!L z@du{~`$XBH*$$(=1}19&FyqJwpYY&B?KEg>b4}3Ch%d-pt1Fgo(0C);wCT&1$1*V*V| ze+w;G%y`XhpPAK!_;6*HU}ly@>THj)YoRAL6&v9+Fx|W0A9WJ8<}E}}gA9u6_u7eX z_}nUZ+E5V-2sYJd4U_4M)TPd-rEy_LAk&~zb+r)tOI8j=Mc&1hDhK5l&KrI^IoBUJ zT8A<=&rF4ml~{VQFFvf{yE;UBa_y#Iya8Wd-T!W*`uoR?ppg59c14S;1|`t)l5Md5 zr}_a08=rkF3+jXT3cFI`M?VYSgxDf))WF(WdgkwGFNAIlf6jtn`L6F0Z|Cpj?tg%R zqx59Qz+i)K%dRcc=k9xY!WSVeQ}10xg>H@Nkc52B@UBq*8i9Hlk7gyKT9&9g3bZhCfxU)p21#veny|h9k5S}vzdUn&|2Bo9W5h0~$WiJSgRorkNv!<3oGe<-R6cWGe1phSu zp}YJ%2uvZ2x<}TgeI*jmpL?&v zB~ahq1^)wBkagucuI(+~woK6n{jsvO`vSiWQy=)lrsK&Oi{+wbFLtS#xncuLwPezm z)5#ct$CG;!;y6_iPeeaw*OMpeD;2;CvZ$MKYq$aV>UqS?o7*QKFR~O={o$@Io2(LP zkKpF*wmBWzx{JV0sFPP@TJRLfERIv1lpDZihzO9S%n3=wx-H^UhK^ti| ziCme=*6$8$Q|ybDZrvrX=~MHkCkuzy(ZBs=^x=Hb^;-f$aj=M=SWyVMB_5qnN^UEU zA+aOO9nlwO&eX10!d5|U)}e}${*a^Q_GZL2GrVEW*jM<&yqKqE$`uI3)?^k4gx3sY zjXCTFx?*xS7?NuU&5qKi>$~uBvULVn)spj<{JzWq@HzwmX; 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a/docs/hardware/panda-pwr-characterization.md b/docs/hardware/panda-pwr-characterization.md deleted file mode 100644 index 7b1f745..0000000 --- a/docs/hardware/panda-pwr-characterization.md +++ /dev/null @@ -1,273 +0,0 @@ -# BIGTREETECH Panda PWR teardown characterization - -> **EXTERNAL REFERENCE HARDWARE / NOT A JUMPJET DESIGN SOURCE.** This record -> documents a third-party product for architecture review only. It is not a -> JumpJet BOM source, does not select any JumpJet component, does not authorize -> copying the Panda PWR design, and does not establish safety compliance for any -> product. - -> [!WARNING] -> **Mains hazard.** The Panda PWR is a mains-powered device. Destructive -> teardown removes the original enclosure and its touch protection. Any -> measurement on an exposed, energized board must be treated as potentially -> lethal. Prefer unpowered continuity characterization first, and energize an -> opened unit only with appropriate isolation, equipment, and procedures. -> Neither firmware behavior nor observed architecture substitutes for safety -> certification. No Panda PWR safety feature is copied into JumpJet without -> independent engineering review. - -## 1. Scope and status - -This record captures what a direct teardown of one Panda PWR unit establishes -about its hardware, and what it does not. It is useful to JumpJet as reference -evidence for: - -- mains switching architecture -- isolated auxiliary power -- isolated voltage/current sensing and metering architecture -- controller / metering partitioning -- service and debug interfaces -- enclosure and mechanical reference - -It does not contain a schematic. The architecture in -[section 6](#6-current-architecture-interpretation) is an interpretation of -component identity and placement, not a continuity-derived circuit. - -### Status classes - -This record uses the status classes defined in the -[Phase 1 hardware register](../PHASE1_HARDWARE_REGISTER.md#status-legend), with -the following qualifiers: - -| Status | Use in this record | -|---|---| -| CONFIRMED FACT | A readable package/label marking, a direct physical observation, or an authoritative cited source supports it. A confirmed marking confirms component identity only, not circuit function or connection. | -| ASSUMPTION / PROVISIONAL — strong / high-confidence inference | Location, form, and architecture strongly suggest an identity or function, but no readable marking or continuity evidence proves it. | -| ASSUMPTION / PROVISIONAL | A plausible identity or function with weaker support. | -| TBD / BLOCKED | Not yet established; requires continuity, firmware, or further inspection. | - -## 2. Specimen identity and provenance - -| Property | Value | -|---|---| -| Product | BIGTREETECH Panda PWR | -| Revision | Rev 1 | -| Quantity inspected | One physical unit | -| Condition | Enclosure destructively opened for characterization | -| Inspection | Unit inspected directly | -| Photographs | Daniel Brown | -| Date | 2026-09-27 | -| Comparison material | FCC internal photographs were used earlier for comparison. They are **not** reproduced in this repository unless their licensing/provenance is established to permit it. | - -### FCC model-difference declaration - -| Property | Value | Verification | -|---|---|---| -| FCC ID | `2BAS6-PANDAPWR` ([fccid.io/2BAS6-PANDAPWR](https://fccid.io/2BAS6-PANDAPWR)) | Supplied by Daniel Brown; consistent with third-party FCC-mirror index entries | -| Grantee | Shenzhen BIQU Innovation Technology Co., Ltd. (grantee code `2BAS6`) | Third-party FCC-mirror index | -| Exhibit | "Model Difference" letter, dated 2024-07-17 | Third-party mirror of the exhibit ([manuals.plus copy](https://manuals.plus/m/d2ffb86b9c70f673e9e77e69a77a697aba42d3293698eece14e3dcbeb16183a3)) | -| Declared statement | Product Panda PWR (trademark BIGTREETECH) covers models **Panda PWR, Panda PWR Lite, and Panda PWR Pro**, which are declared to be "the same circuit and RF module, except appearance color and model name." | Search-index excerpt of the mirrored exhibit | - -**Verification limit.** On 2026-09-27 the FCC equipment-authorization site, -fccid.io, and the mirrors of the exhibit all refused automated access from the -documentation environment (HTTP 403). The statement above comes from -search-index excerpts of the mirrored exhibit, not from a direct read of the -FCC primary document. Check the wording against the exhibit on the FCC -equipment-authorization system before relying on it. Until then, treat it as -the reported content of the declaration. - -**What it supports.** Taking the excerpt at face value, it is an FCC-declared -circuit and RF-module relationship among the three listed models. It -distinguishes declared circuit identity from appearance (color) and model -name. It does **not** state that PCB layout, component sourcing, or physical -construction is identical across units or production lots. It says nothing -about enclosure mechanics beyond appearance. - -**What it does not cover.** - -- A separate FCC ID, `2BAS6-PANDAPWRV2` ("Panda PWR"), also appears in the - third-party index. This declaration does not cover it, and this record makes - no claim about how a V2 product relates to the unit characterized here. -- The FCC ID on the specimen's own label has not been recorded in this - document. Record it to tie this Rev 1 unit to `2BAS6-PANDAPWR`. - -## 3. Evidence photographs - -These four images are crops/enhancements of the real teardown photographs. They -are primary photographic evidence; no generated or reconstructed imagery is -used. Metadata (EXIF/XMP) was verified absent before commit. - -Panda PWR Rev 1 PCB, component side, after enclosure opening - -*Figure 1 — Panda PWR Rev 1 PCB after destructive enclosure opening; overall -component-side layout.* - -Panda PWR Rev 1 angled view of HLK-20M05, relay, sensing magnetics, and USB ports - -*Figure 2 — Panda PWR Rev 1 angled view showing component heights, HLK-20M05, -relay, sensing magnetics, USB ports, and controller end.* - -Panda PWR mains protection and sensing area - -*Figure 3 — Mains protection and sensing area showing T2A fuse, relay, -ZMPT107-1, unidentified EI-core transformer, suppression components, and -common-mode choke.* - -HLW8112 metering IC package marking - -*Figure 4 — HLW8112 metering IC marking and surrounding analog network.* - -Full-resolution files are in [`images/panda-pwr/`](images/panda-pwr/). - -## 4. Confirmed component identities - -A confirmed identity below means the part is present on the board. Unless a row -says otherwise, its connections, operating point, and exact circuit role are -**not** established. - -| Item | Status | Identity / marking | Evidence | Role | Not yet established | -|---|---|---|---|---|---| -| Controller | CONFIRMED FACT | Espressif `ESP8684-MINI-1-H4` module | Direct inspection of the unit; BIGTREETECH's published Panda PWR documentation lists "ESP8684-MINI-1-H4" as the Wi-Fi module ([source](https://github.com/bigtreetech/docs/blob/master/docs/Panda%20PWR.md)). The module marking is not legible in the four committed crops; the module is at the right-hand (controller) end in Figures 1–2. | Primary wireless/application controller | Any GPIO assignment, protocol mapping, or peripheral wiring | -| Auxiliary PSU | CONFIRMED FACT | Hi-Link `HLK-20M05`. Label: `INPUT: 100-240VAC 0.4A 50-60Hz`, `OUTPUT: 5VDC 4A 20W`, `P/N: HLK-20M05`; pins marked `AC`, `AC`, `+Vo`, `-Vo`; CE, RoHS, and double-square symbol marks | Figures 1–2 | Isolated mains-to-5-V auxiliary supply | Downstream 5 V rail topology; actual load; whether and how 3.3 V is derived | -| Load relay | CONFIRMED FACT | Songle `SRD-05VDC-SL-B`. Markings include `10A 250VAC`, `10A 125VAC`, `10A 30VDC` (twice), and CQC and UL-style recognition marks | Figures 1–3 | Relay used for AC load switching | Exact COM/NO routing; coil drive circuit; whether it is the only load-switching element | -| Metering IC | CONFIRMED FACT | `HLW8112`, secondary marking `2423W1D` (read as a date/lot code; not decoded), 16-lead package | Figure 4 | Energy/power metering IC | Current channel used; voltage channel used; SPI vs UART; digital wiring; calibration constants; ESP GPIO mapping | -| Voltage-sensing transformer | CONFIRMED FACT | `ZMPT107-1` with Chinese-language manufacturer text | Figures 1, 3 | Isolated AC voltage sensing in the metering front end | Continuity to the HLW8112 voltage input; primary-side series resistance; sampling resistor | -| Fuse marking | CONFIRMED FACT | Black rectangular fuse body marked `T2A 250V`, `Jdtfuse`, with CQC and UL-style recognition marks | Figure 3 | Fuse | **Which branch it protects.** It is a separate component from the glass cartridge in clips at the board edge. Nothing here establishes that it protects the switched 10 A load path. | - -### Published specifications used - -Only the following manufacturer-derived specifications are recorded. Nothing -here is a JumpJet requirement. - -**ZMPT107-1** — from the manufacturer specification by Qingxian Zeming Langxi -Electronic ([ZMPT107-1 specification](https://5nrorwxhmqqijik.leadongcdn.com/ZMPT107-1+specification-aidiqBqoKomRilSqqnnkikq.pdf)): - -| Property | Published value | -|---|---| -| Type | Current-type voltage transformer | -| Rated input / output current | 2 mA / 2 mA | -| Turns ratio | 1000:1000 | -| Linear range | 0–1000 V; 0–10 mA (50 Ω sampling resistor) | -| Isolation voltage | 3000 V AC | -| Operating temperature | −40 to +85 °C | -| Encapsulation | Epoxy, PCB mounting | - -**HLW8112** — the manufacturer (Hiliwei Tech) datasheet PDF was not retrieved. -The distributor listing ([LCSC C970140](https://www.lcsc.com/product-detail/C970140.html)) -describes it as a metering IC with two current channels (A and B) and one -voltage channel, an SPI/UART interface, 3.0–3.6 V or 4.5–5.5 V supply, and a -16-lead SSOP package. Treat these as provisional until they are checked against -the manufacturer datasheet. They do not show which channels or which interface -this board uses. - -**HLK-20M05** — only the printed label (above) is recorded. No datasheet-derived -isolation, efficiency, or protection claim is made. - -## 5. Other directly observed components - -| Item | Status | Observation | Identity / function | Remaining evidence | -|---|---|---|---|---| -| Yellow EI-core transformer | ASSUMPTION / PROVISIONAL — strong inference | Large EI/EE-style ferrite core with yellow-taped winding in the metering/sensing region, adjacent to the ZMPT107-1 (Figure 3). No readable part number. | Likely current-sensing transformer. Its location and the metering architecture strongly suggest current sensing. **Unconfirmed.** | Readable marking or continuity from the load-current path and to an HLW8112 current input | -| Green toroid | ASSUMPTION / PROVISIONAL — high-confidence inference | Toroidal core with two copper windings separated by a green divider (Figures 1–3) | Likely common-mode choke / EMI filter. Part identity is not confirmed. | Marking, continuity, winding count | -| Blue disc | ASSUMPTION / PROVISIONAL | Blue epoxy-coated disc component beside the fuse (Figure 3); marking not read | Possibly a MOV or other mains transient-suppression part | Marking or continuity | -| Yellow rectangular capacitor | ASSUMPTION / PROVISIONAL | Yellow rectangular box component beside the blue disc (Figure 3); marking not read | Likely a mains EMI/safety film capacitor. **Not identified as X1/X2**, because its marking has not been read. | Marking | -| Glass cartridge fuse | TBD / BLOCKED | Glass cartridge fuse in PCB clips along the top edge (Figures 1, 3); rating not legible in the committed images | Fuse. It is a separate part from the `T2A 250V` black-body fuse. | Read the cartridge end-cap marking; map its branch | -| AC connector block | TBD / BLOCKED | Black mains contact/connector block at the left board edge (Figures 1–2) | Mains interface; exact role (inlet, outlet, or both) not established from these images | Continuity and mechanical inspection | -| RGB status LED | CONFIRMED FACT (presence) | LED at the controller end beside `RGB` silkscreen (Figure 1) | Status indication | Drive circuit and GPIO | -| USB-A connectors | CONFIRMED FACT (presence) | Two USB-A receptacles (Figures 1–2). BIGTREETECH documentation states the USB-A ports are output only. | Peripheral USB power output | Switching/current-limit circuit and rail source | -| USB-C connector | CONFIRMED FACT (presence) | One USB-C receptacle (Figures 1–2). BIGTREETECH documentation states the Type-C port is input only and is used for firmware burning and factory reset. | Service connector | Data/power wiring; any power path into the board rails | -| Reset control | CONFIRMED FACT (presence) | Tactile button beside `RESET` silkscreen between the USB-A ports (Figures 1–2) | Reset/service control | What it is wired to | -| Service header pads | CONFIRMED FACT (silkscreen) | Pad row at the controller end, silkscreened approximately `GND RX TX 3V3` (Figures 1–2) | Likely a UART service header, inferred from the silkscreen only | Continuity to the ESP8684 and the actual voltage levels | -| Mounting holes | CONFIRMED FACT (presence) | Plated mounting holes at the board corners (Figures 1, 3) | Mechanical mounting | Coordinates and diameters | -| Passive markings near HLW8112 | CONFIRMED FACT (marking) | SMD resistors marked `330` and `472` beside the HLW8112 (Figure 4) | Part of the surrounding analog/digital network; role not established | Continuity | -| `AP65N06NF` | ASSUMPTION / PROVISIONAL | Reported from a teardown photograph that is not in the committed evidence set; not independently verified here | If the marking and package are confirmed, a distributor listing identifies A Power Microelectronics `AP65N06NF` as a 60 V N-channel MOSFET in a PDFN package ([JLCPCB C3011335](https://jlcpcb.com/partdetail/A_Powermicroelectronics-AP65N06NF/C3011335)). **Circuit function TBD.** A ~60 V device is not the 120/240 VAC load switch; its low-voltage role still needs tracing. | Add a legible photograph; confirm package against datasheet; trace circuit | -| Other low-voltage ICs | TBD / BLOCKED | Additional USB/service/power-support ICs visible near the USB connectors (Figures 1–2) | No part number is promoted; the markings are not unambiguous in the committed images | Legible macro photographs | - -## 6. Current architecture interpretation - -> **CURRENT INTERPRETATION, NOT A COMPLETED SCHEMATIC.** This is inferred from -> component identity and placement. No continuity has been mapped. Every arrow is -> provisional. - -```text -Mains switching (provisional): - - AC input - -> fuse / surge / EMI network (fuse branch TBD; suppression parts provisional) - -> SRD-05VDC-SL-B relay (COM/NO routing TBD) - -> switched load output - -Auxiliary power (provisional): - - AC input - -> HLK-20M05 - -> isolated 5 V low-voltage domain (rail topology TBD) - -> ESP8684-MINI-1-H4 / USB / support electronics (3.3 V derivation TBD) - -Metering (provisional): - - AC voltage - -> ZMPT107-1 (confirmed part; connection TBD) - -> analog conditioning - -> HLW8112 voltage channel (channel TBD) - - Load current - -> unidentified sensing transformer / front end (yellow EI-core: strong inference only) - -> analog conditioning - -> HLW8112 current channel (channel A/B TBD) - - HLW8112 - -> digital interface (SPI or UART TBD; pins TBD) - -> ESP8684-MINI-1-H4 (GPIOs TBD) -``` - -**Architectural observation.** The isolated sensing magnetics and the isolated -HLK-20M05 together suggest that the metering and controller electronics can sit -on the isolated low-voltage side. That fits the exposed USB and service -interfaces. It is an observation, not a finding: the board has **not** been -isolation-mapped, and no creepage, clearance, or isolation-boundary claim is -made until continuity and creepage tracing are complete. - -## 7. JumpJet relevance - -This teardown belongs in the repository as useful reference evidence for: - -- architecture partitioning between mains/power and controller domains -- an isolated auxiliary supply feeding controller and service electronics -- relay control of a load path -- a measurement front end with isolated voltage and current sensing -- component packaging and board density -- serviceability: USB service connector, reset control, UART-style header -- enclosure constraints for a compact power product - -It is **not** a design mandate: - -- JumpJet remains a 24 V chamber-heater controller governed by its own - [product safety contract](../PRODUCT_SAFETY_CONTRACT.md). -- The Panda PWR runs from mains and has a different hazard model. -- No Panda PWR component becomes a JumpJet selection because it appears here. - Any JumpJet candidate goes through the - [hardware register](../PHASE1_HARDWARE_REGISTER.md) process on its own - evidence. - -## 8. Remaining characterization - -- [ ] map AC input -> fuse -> relay -> output continuity -- [ ] determine exactly what the `T2A 250V` fuse protects, and read and map the glass cartridge fuse -- [ ] identify relay COM/NO routing -- [ ] identify the yellow EI-core transformer -- [ ] continuity-map ZMPT107-1 to the HLW8112 voltage input -- [ ] continuity-map the current-sense path to the HLW8112 -- [ ] map the HLW8112 digital interface to the ESP8684 -- [ ] identify the bus type actually used (SPI or UART) -- [ ] map ESP GPIOs only after continuity/firmware evidence -- [ ] photograph `AP65N06NF` legibly, confirm the package, and identify its circuit function -- [ ] identify the remaining regulator / USB support devices -- [ ] establish 5 V and 3.3 V rail topology -- [ ] map the isolation boundary and creepage/clearance regions -- [ ] inspect the PCB backside and current-carrying copper -- [ ] capture PCB dimensions, mounting-hole coordinates, connector positions, and maximum component heights -- [ ] capture enclosure dimensions before or while designing a replacement enclosure -- [ ] verify the `2BAS6-PANDAPWR` model-difference wording against the FCC primary exhibit -- [ ] record the FCC ID printed on the specimen label -- [ ] produce a partial schematic from measured continuity, not visual guesswork