Process completed with exit code 1.

1) e2e/waveform.spec.js:91:1 › concurrent-sim SVA assertion signal appears in VCD ──────────────── Retry #1 ─────────────────────────────────────────────────────────────────────────────────────── Error: expect(locator).toContainText(expected) failed Locator: getByTestId('runtime-logs') Timeout: 90000ms - Expected substring - 1 + Received string + 18 - SVA assertion failed + $ circt-verilog --resource-guard=false --ir-llhd --timescale 1ns/1ns --single-unit --top monitor -o /workspace/out/design.llhd.mlir /workspace/src/monitor.sv$ circt-sim --resource-guard=false --mode interpret --top monitor --vcd /workspace/out/waves.vcd --trace-all /workspace/out/design.llhd.mlirstdout [circt-sim] Found 0 LLHD processes, 0 seq.initial blocks, and 0 hw.instance ops (out of 19 total ops) in module + [circt-sim] Starting simulation + [circt-sim] Wrote waveform to /workspace/out/waves.vcd + [circt-sim] Simulation completed at time 0 fs + [circt-sim] Simulation completed + + ================================================= + Coverage Report + ================================================= + + No covergroups registered. + + =================================================stderr [circt-sim] Stage: parse (prev: 0ms, total: 0ms) + [circt-sim] Stage: passes (prev: 37ms, total: 37ms) + [circt-sim] Stage: init (prev: 29ms, total: 66ms) + [circt-sim] Stage: run (prev: 33ms, total: 100ms) + [circt-sim] advanceTime() returned false at time 0 fs, iter=1 — no more scheduled events + [circt-sim] Processes registered: 0, executed: 0, delta cycles: 0 Call log: - Expect "toContainText" with timeout 90000ms - waiting for getByTestId('runtime-logs') 4 × locator resolved to <div data-testid="runtime-logs" class="m-0 bg-logs-bg text-logs-text p-[0.6rem] overflow-auto font-mono text-[0.78rem]↵ flex-1 min-h-0">…</div> - unexpected value "$ circt-verilog --resource-guard=false --ir-llhd --timescale 1ns/1ns --single-unit --top monitor -o /workspace/out/design.llhd.mlir /workspace/src/monitor.sv" - locator resolved to <div data-testid="runtime-logs" class="m-0 bg-logs-bg text-logs-text p-[0.6rem] overflow-auto font-mono text-[0.78rem]↵ flex-1 min-h-0">…</div> - unexpected value "$ circt-verilog --resource-guard=false --ir-llhd --timescale 1ns/1ns --single-unit --top monitor -o /workspace/out/design.llhd.mlir /workspace/src/monitor.sv$ circt-sim --resource-guard=false --mode interpret --top monitor --vcd /workspace/out/waves.vcd --trace-all /workspace/out/design.llhd.mlirstderr [circt-sim] Stage: parse (prev: 0ms, total: 0ms)" 88 × locator resolved to <div data-testid="runtime-logs" class="m-0 bg-logs-bg text-logs-text p-[0.6rem] overflow-auto font-mono text-[0.78rem]↵ flex-1 min-h-0">…</div> - unexpected value "$ circt-verilog --resource-guard=false --ir-llhd --timescale 1ns/1ns --single-unit --top monitor -o /workspace/out/design.llhd.mlir /workspace/src/monitor.sv$ circt-sim --resource-guard=false --mode interpret --top monitor --vcd /workspace/out/waves.vcd --trace-all /workspace/out/design.llhd.mlirstdout [circt-sim] Found 0 LLHD processes, 0 seq.initial blocks, and 0 hw.instance ops (out of 19 total ops) in module [circt-sim] Starting simulation [circt-sim] Wrote waveform to /workspace/out/waves.vcd [circt-sim] Simulation completed at time 0 fs [circt-sim] Simulation completed ================================================= Coverage Report ================================================= No covergroups registered. =================================================stderr [circt-sim] Stage: parse (prev: 0ms, total: 0ms) [circt-sim] Stage: pas

1) e2e/waveform.spec.js:91:1 › concurrent-sim SVA assertion signal appears in VCD ──────────────── Error: expect(locator).toContainText(expected) failed Locator: getByTestId('runtime-logs') Timeout: 90000ms - Expected substring - 1 + Received string + 18 - SVA assertion failed + $ circt-verilog --resource-guard=false --ir-llhd --timescale 1ns/1ns --single-unit --top monitor -o /workspace/out/design.llhd.mlir /workspace/src/monitor.sv$ circt-sim --resource-guard=false --mode interpret --top monitor --vcd /workspace/out/waves.vcd --trace-all /workspace/out/design.llhd.mlirstdout [circt-sim] Found 0 LLHD processes, 0 seq.initial blocks, and 0 hw.instance ops (out of 19 total ops) in module + [circt-sim] Starting simulation + [circt-sim] Wrote waveform to /workspace/out/waves.vcd + [circt-sim] Simulation completed at time 0 fs + [circt-sim] Simulation completed + + ================================================= + Coverage Report + ================================================= + + No covergroups registered. + + =================================================stderr [circt-sim] Stage: parse (prev: 0ms, total: 0ms) + [circt-sim] Stage: passes (prev: 22ms, total: 22ms) + [circt-sim] Stage: init (prev: 17ms, total: 39ms) + [circt-sim] Stage: run (prev: 26ms, total: 66ms) + [circt-sim] advanceTime() returned false at time 0 fs, iter=1 — no more scheduled events + [circt-sim] Processes registered: 0, executed: 0, delta cycles: 0 Call log: - Expect "toContainText" with timeout 90000ms - waiting for getByTestId('runtime-logs') 4 × locator resolved to <div data-testid="runtime-logs" class="m-0 bg-logs-bg text-logs-text p-[0.6rem] overflow-auto font-mono text-[0.78rem]↵ flex-1 min-h-0">…</div> - unexpected value "$ circt-verilog --resource-guard=false --ir-llhd --timescale 1ns/1ns --single-unit --top monitor -o /workspace/out/design.llhd.mlir /workspace/src/monitor.sv" 90 × locator resolved to <div data-testid="runtime-logs" class="m-0 bg-logs-bg text-logs-text p-[0.6rem] overflow-auto font-mono text-[0.78rem]↵ flex-1 min-h-0">…</div> - unexpected value "$ circt-verilog --resource-guard=false --ir-llhd --timescale 1ns/1ns --single-unit --top monitor -o /workspace/out/design.llhd.mlir /workspace/src/monitor.sv$ circt-sim --resource-guard=false --mode interpret --top monitor --vcd /workspace/out/waves.vcd --trace-all /workspace/out/design.llhd.mlirstdout [circt-sim] Found 0 LLHD processes, 0 seq.initial blocks, and 0 hw.instance ops (out of 19 total ops) in module [circt-sim] Starting simulation [circt-sim] Wrote waveform to /workspace/out/waves.vcd [circt-sim] Simulation completed at time 0 fs [circt-sim] Simulation completed ================================================= Coverage Report ================================================= No covergroups registered. =================================================stderr [circt-sim] Stage: parse (prev: 0ms, total: 0ms) [circt-sim] Stage: passes (prev: 22ms, total: 22ms) [circt-sim] Stage: init (prev: 17ms, total: 39ms) [circt-sim] Stage: run (prev: 26ms, total: 66ms) [circt-sim] advanceTime() returned false at time 0 fs, iter=1 — no more scheduled events [circt-sim] Processes registered: 0, executed: 0, delta cycles: 0" 115 | // The testbench has a missing-grant scenario that fires the assertion. 116 | // circt-sim exits with code 1 on assertion failure — that is expected and correct. > 117 | await expect(logs).toContainText('SVA assertion failed', { timeout: 90_000 }); | ^ 118 | await expect(logs).not.toContainText('# circt-verilog exit code: 1'); 119 | 120 | // The Waves tab should appear (VCD was produced). at /home/runner/work/sv-tutorial/sv-tutorial/e2e/waveform.spec.