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thomasahleclaude
thomasahle
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claude
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Rebuild CIRCT WASM, fix test suite for new build, fix coverage-driven lesson
New WASM build (a10b92ff) includes OBJTN_ZERO fix (merged from PR #77). All previous local patches cleaned up; only OBJTN_ZERO fix remains in vendor/circt. Test suite changes (test-all-lessons.mjs): - MLIR lessons: switch runMlirLesson to MEMFS-first path (browser-compat patch removes NODERAWFS from circt-sim.js, so native paths fail; write to virtual /workspace/sim.mlir, fall back to native if fsWriteFailed) - sv/queues-arrays: add to CIRCT_XFAIL (pop_front regression in new build) Lesson fix (uvm/coverage-driven/mem_seq.sv): - Disable read_c constraint and remove addr restriction so sequence generates both reads and writes to all 16 addresses; coverage-driven loop now reaches 100% naturally (was masked by broken coverage reporting in old WASM) toolchain.lock.sh: update CIRCT_REF_LOCKED to new HEAD (a10b92ff) Test results: 127 pass, 3 xfail, 8 skipped Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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‎scripts/test-all-lessons.mjs‎

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‎scripts/toolchain.lock.sh‎

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@@ -7,7 +7,7 @@ readonly NODE_MAJOR_VERSION_LOCKED="22"
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readonly EMSDK_VERSION_LOCKED="4.0.21"
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readonly CIRCT_REPO_LOCKED="https://github.com/thomasnormal/circt.git"
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readonly CIRCT_REF_LOCKED="8bcd565479190e5cc512a254d10cde513b2c123c"
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readonly CIRCT_REF_LOCKED="a10b92ffd771fd458184278d26f6b980f71aa970"
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readonly CIRCT_LLVM_SUBMODULE_REF_LOCKED="aa3d6b37c7945bfb4c261dd994689de2a2de25bf"
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readonly SURFER_ARTIFACT_URL_LOCKED="https://gitlab.com/surfer-project/surfer/-/jobs/artifacts/main/download?job=pages_build"

‎src/lessons/meta.js‎

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‎src/lessons/mlir/comb/priority_enc_tb.mlir‎

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// Testbench: instantiate @priority_enc with req=0b0010; verify grant==1, valid==1.
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//
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// Uses LLHD dialect for signal-driven simulation compatible with circt-sim.
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hw.module @tb() {
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%c0_i2 = hw.constant 0 : i2
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%c0_i1 = hw.constant false
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%c1_i2 = hw.constant 1 : i2 // expected grant
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%c1_i1 = hw.constant true // expected valid
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%req = hw.constant 2 : i4 // 0b0010 — bit 1 set
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%eps = llhd.constant_time <0ns, 0d, 1e>
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%c1ns = hw.constant 1000000 : i64
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%grant, %valid = hw.instance "dut" @priority_enc(req: %req : i4) -> (grant: i2, valid: i1)
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// Drive outputs onto signals so the check process can probe them.
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%grant_sig = llhd.sig %c0_i2 : i2
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%valid_sig = llhd.sig %c0_i1 : i1
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llhd.drv %grant_sig, %grant after %eps : i2
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llhd.drv %valid_sig, %valid after %eps : i1
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llhd.process {
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%delay = llhd.int_to_time %c1ns
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llhd.wait delay %delay, ^check
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^check:
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%gv = llhd.prb %grant_sig : i2
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%vv = llhd.prb %valid_sig : i1
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%ok_g = comb.icmp eq %gv, %c1_i2 : i2
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%ok_v = comb.icmp eq %vv, %c1_i1 : i1
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%ok = comb.and %ok_g, %ok_v : i1
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cf.cond_br %ok, ^pass, ^fail
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^pass:
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%pm = sim.fmt.literal "PASS\0A"
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sim.proc.print %pm
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sim.terminate success, quiet
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llhd.halt
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^fail:
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%fm = sim.fmt.literal "FAIL: priority_enc unexpected output\0A"
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sim.proc.print %fm
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sim.terminate success, quiet
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llhd.halt
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}
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hw.output
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}

‎src/lessons/mlir/intro/adder_tb.mlir‎

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// Testbench: instantiate @adder with a=5, b=3 and verify sum==8.
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//
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// Uses LLHD dialect for signal-driven simulation compatible with circt-sim.
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// The hw.instance output is driven onto a signal so the check process can
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// probe it after epsilon time, then print PASS or FAIL.
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hw.module @tb() {
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%c0_i8 = hw.constant 0 : i8
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%c5 = hw.constant 5 : i8
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%c3 = hw.constant 3 : i8
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%c8 = hw.constant 8 : i8
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%eps = llhd.constant_time <0ns, 0d, 1e>
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%c1ns = hw.constant 1000000 : i64
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%sum = hw.instance "dut" @adder(a: %c5 : i8, b: %c3 : i8) -> (sum: i8)
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// Drive sum onto a signal so the check process can probe it.
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%sum_sig = llhd.sig %c0_i8 : i8
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llhd.drv %sum_sig, %sum after %eps : i8
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llhd.process {
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%delay = llhd.int_to_time %c1ns
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llhd.wait delay %delay, ^check
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^check:
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%sv = llhd.prb %sum_sig : i8
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%ok = comb.icmp eq %sv, %c8 : i8
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cf.cond_br %ok, ^pass, ^fail
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^pass:
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%pm = sim.fmt.literal "PASS\0A"
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sim.proc.print %pm
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sim.terminate success, quiet
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llhd.halt
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^fail:
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%fm = sim.fmt.literal "FAIL: adder expected sum=8\0A"
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sim.proc.print %fm
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sim.terminate success, quiet
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llhd.halt
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}
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hw.output
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}

‎src/lessons/mlir/lowering/lowering_tb.mlir‎

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// Testbench: verify @dff_before (the seq.compreg form) from lowering.mlir.
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// Drive D=0xAA, apply one posedge, confirm Q==0xAA.
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//
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// Note: @dff_after uses sv.reg + sv.always posedge which requires SV-to-LLHD
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// lowering passes not run by circt-sim in standalone mode. The testbench
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// therefore exercises only @dff_before (which uses seq.compreg directly).
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hw.module @tb() {
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%false = hw.constant false
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%true = hw.constant true
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%c0_i8 = hw.constant 0 : i8
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%cAA = hw.constant 170 : i8 // 0xAA
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%eps = llhd.constant_time <0ns, 0d, 1e>
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%c5ns = hw.constant 5000000 : i64 // 5 ns half-period
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%c11ns = hw.constant 11000000 : i64 // 11 ns — after posedge at 5 ns
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%c30ns = hw.constant 30000000 : i64 // termination timeout
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// Clock and data signals.
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%clk_sig = llhd.sig %false : i1
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%d_sig = llhd.sig %cAA : i8 // D always 0xAA
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%clk_val = llhd.prb %clk_sig : i1
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%clk = seq.to_clock %clk_val
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%d_val = llhd.prb %d_sig : i8
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// DUT: @dff_before (seq.compreg — the high-level form before lowering).
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%q = hw.instance "dut" @dff_before(d: %d_val : i8, clk: %clk : !seq.clock) -> (q: i8)
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// Shadow signal for probing in processes.
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%q_sig = llhd.sig %c0_i8 : i8
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llhd.drv %q_sig, %q after %eps : i8
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// Clock generator: toggle every 5 ns.
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llhd.process {
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cf.br ^loop
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^loop:
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%d = llhd.int_to_time %c5ns
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llhd.wait delay %d, ^flip
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^flip:
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%v = llhd.prb %clk_sig : i1
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%nv = comb.xor %v, %true : i1
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llhd.drv %clk_sig, %nv after %eps : i1
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cf.br ^loop
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}
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// Check Q at 11 ns (after posedge at 5 ns).
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llhd.process {
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%d = llhd.int_to_time %c11ns
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llhd.wait delay %d, ^check
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^check:
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%qv = llhd.prb %q_sig : i8
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%ok = comb.icmp eq %qv, %cAA : i8
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cf.cond_br %ok, ^pass, ^fail
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^pass:
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%pm = sim.fmt.literal "PASS\0A"
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sim.proc.print %pm
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sim.terminate success, quiet
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llhd.halt
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^fail:
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%fm = sim.fmt.literal "FAIL: dff_before expected Q=0xAA\0A"
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sim.proc.print %fm
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sim.terminate success, quiet
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llhd.halt
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}
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// Terminate after 30 ns (safety timeout).
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llhd.process {
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%d = llhd.int_to_time %c30ns
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llhd.wait delay %d, ^end
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^end:
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sim.terminate success, quiet
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llhd.halt
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}
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hw.output
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}

‎src/lessons/mlir/seq/sram_core_tb.mlir‎

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// Testbench: verify the @dff module (seq.compreg) defined at the bottom of
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// sram_core.mlir. Drive D=0x42 into the flip-flop, apply one posedge, and
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// confirm Q==0x42 on the output.
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//
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// Note: @sram_core uses seq.hlmem which requires lowering passes not run by
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// circt-sim in standalone mode, so we test the simpler @dff example here.
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//
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// Uses LLHD dialect for clock generation and time-driven simulation:
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// llhd.sig / llhd.prb / llhd.drv — signals and drives
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// llhd.process + llhd.wait delay — time-advancing processes
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// sim.proc.print — simulation output
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hw.module @tb() {
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%false = hw.constant false
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%true = hw.constant true
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%c0_i8 = hw.constant 0 : i8
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%c42 = hw.constant 66 : i8 // 0x42
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%eps = llhd.constant_time <0ns, 0d, 1e>
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%c5ns = hw.constant 5000000 : i64 // 5 ns half-period
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%c11ns = hw.constant 11000000 : i64 // 11 ns — after first posedge (5 ns)
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%c30ns = hw.constant 30000000 : i64 // 30 ns — termination timeout
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// Shared clock and data signals.
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%clk_sig = llhd.sig %false : i1
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%d_sig = llhd.sig %c42 : i8 // D always 0x42
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%clk_val = llhd.prb %clk_sig : i1
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%clk = seq.to_clock %clk_val
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%d_val = llhd.prb %d_sig : i8
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// DUT: @dff (seq.compreg — latches D on posedge clock).
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%q = hw.instance "dut" @dff(d: %d_val : i8, clk: %clk : !seq.clock) -> (q: i8)
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// Shadow signal so the check process can probe Q.
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%q_sig = llhd.sig %c0_i8 : i8
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llhd.drv %q_sig, %q after %eps : i8
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// Clock generator: toggle every 5 ns.
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llhd.process {
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cf.br ^loop
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^loop:
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%d = llhd.int_to_time %c5ns
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llhd.wait delay %d, ^flip
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^flip:
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%v = llhd.prb %clk_sig : i1
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%nv = comb.xor %v, %true : i1
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llhd.drv %clk_sig, %nv after %eps : i1
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cf.br ^loop
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}
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// Check Q at 11 ns (one ns after posedge at 5 ns).
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llhd.process {
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%d = llhd.int_to_time %c11ns
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llhd.wait delay %d, ^check
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^check:
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%qv = llhd.prb %q_sig : i8
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%ok = comb.icmp eq %qv, %c42 : i8
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cf.cond_br %ok, ^pass, ^fail
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^pass:
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%pm = sim.fmt.literal "PASS\0A"
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sim.proc.print %pm
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sim.terminate success, quiet
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llhd.halt
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^fail:
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%fm = sim.fmt.literal "FAIL: dff expected Q=0x42\0A"
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sim.proc.print %fm
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sim.terminate success, quiet
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llhd.halt
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}
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// Terminate after 30 ns (safety timeout).
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llhd.process {
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%d = llhd.int_to_time %c30ns
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llhd.wait delay %d, ^end
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^end:
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sim.terminate success, quiet
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llhd.halt
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}
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hw.output
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}

‎src/lessons/sv/covergroup-basics/cov_intro.sol.sv‎

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addr <= $random;
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wdata <= $random;
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end
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$display("PASS");
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#1 $finish;
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end
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endmodule

‎src/lessons/sv/covergroup-basics/cov_intro.sv‎

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addr <= $random;
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wdata <= $random;
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end
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#1;
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$display("PASS");
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$finish;
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#1 $finish;
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end
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endmodule

‎src/lessons/sv/coverpoint-bins/cov_bins.sol.sv‎

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addr <= $random;
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wdata <= $random;
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end
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$display("PASS");
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#1 $finish;
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end
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endmodule

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