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A flip-flop is a 1-bit memory element that captures its input (d) at a clock edge and holds it until the next edge.
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end // step 2: both mem and out update simultaneously
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</pre>
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<blockquote><p>
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We use <strong><dfntitle="Non-blocking assignment (<=) schedules the update to happen after all right-hand sides in the current time step are evaluated. This means two flip-flops can swap values correctly: a <= b; b <= a; works as expected. Blocking assignment (=) takes effect immediately, like a variable assignment in C — correct for combinational logic but causes races in sequential logic.">non-blocking assignment</dfn></strong> (<code><=</code>) inside <code>always_ff</code>. It works in two steps: first, all right-hand sides are sampled using current values; then all left-hand sides update simultaneously. So <code>out</code> always captures the value <code>mem</code> held <em>before</em> this edge — creating a true one-cycle delay, not a zero-delay pass-through. The same rule is why <code>a <= b; b <= a;</code> correctly swaps two flip-flops.
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</p></blockquote>
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<h2>Blocking vs. Non-Blocking Assignments</h2>
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We use <strong><dfndata-card="Non-blocking assignment (<=) schedules the update to happen after all right-hand sides in the current time step are evaluated. This means two flip-flops can swap values correctly: a <= b; b <= a; works as expected. Blocking assignment (=) takes effect immediately, like a variable assignment in C — correct for combinational logic but causes races in sequential logic.">non-blocking assignment</dfn></strong> (<code><=</code>) inside <code>always_ff</code>. It works in two steps: first, all right-hand sides are sampled using current values; then all left-hand sides update simultaneously. So <code>out</code> always captures the value <code>mem</code> held <em>before</em> this edge — creating a true one-cycle delay, not a zero-delay pass-through. The same rule is why <code>a <= b; b <= a;</code> correctly swaps two flip-flops.</p></blockquote>
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<p>The names describe how each operator behaves in the flow of your procedural code — whether the assignment <strong>blocks</strong> (pauses) execution until it completes.</p>
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<p><spanclass="tag-block">Blocking <code>=</code></span> — execution stops and waits. The assignment completes immediately, in place, before the next line runs. Think of it like hand-delivering a letter: the recipient has it before you walk away.</p>
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<p><strong>Blocking <code>=</code></strong> — execution stops and waits. The assignment completes immediately, in place, before the next line runs. Think of it like hand-delivering a letter: the recipient has it before you walk away.</p>
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<pre>
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a = b; // a gets b's value RIGHT NOW
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c = a; // c sees the new value of a
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</pre>
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<p><spanclass="tag-nba">Non-blocking <code><=</code></span> — execution continues without waiting. The assignment schedules a write for later and immediately moves on. Think of it like dropping a letter in a mailbox: you keep walking and it gets delivered later, when the NBA update region runs.</p>
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<p><strong>Non-blocking <code><=</code></strong> — execution continues without waiting. The assignment schedules a write for later and immediately moves on. Think of it like dropping a letter in a mailbox: you keep walking and it gets delivered later, when the NBA update region runs.</p>
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<pre>
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a <= b; // schedules a write to a, but doesn't apply it yet
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c <= a; // c gets a's OLD value — the write above hasn't happened yet
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</pre>
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<p>All right-hand sides are evaluated first, then all writes happen together at the end of the time step. This is what makes <code>always_ff</code> correctly model real hardware, where all flip-flops in a clocked stage sample their inputs and update simultaneously.</p>
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<p>All right-hand sides are evaluated first, then all writes happen together at the end of the time step. This is what makes <code>always_ff</code> correctly model real hardware, where all flip-flops in a clocked stage sample their inputs and update their outputs <em>simultaneously</em>.</p>
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<p>In <code>sram_core.sv</code> fill in the <code>always_ff</code> body with two statements:</p>
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<ul>
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<li>When <code>we</code> is high, write <code>wdata</code> into <code>mem[addr]</code></li>
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<li>Always register the read: capture <code>mem[addr]</code> into <code>rdata</code></li>
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<li>When <code>we</code> is high, write <code>wdata</code> into <code>mem[addr]</code></li>
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<li>Always register the read: capture <code>mem[addr]</code> into <code>rdata</code></li>
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</ul>
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<blockquote><p>The read is <em>registered</em>: drive <code>addr</code> on cycle N and <code>rdata</code> reflects that address on cycle N+1. This is the standard synchronous-read SRAM model.</p></blockquote>
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<h2>Testbench</h2>
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<p><code>tb.sv</code> writes three values to addresses 2, 7, and 0, then reads them back one cycle later. Each read prints <code>PASS</code> or <code>FAIL</code> — run it before solving to see all three fail, then again after to confirm they all pass. Open the <strong>Waves</strong> tab to see <code>clk</code>, <code>we</code>, <code>addr</code>, <code>wdata</code>, and <code>rdata</code> over time.</p>
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<p><code>tb.sv</code> writes three values to addresses 2, 7, and 0, then reads them back one cycle later. Each read prints <code>PASS</code> or <code>FAIL</code> — run it before solving to see all three fail, then again after to confirm they all pass. Open the <strong>Waves</strong> tab to see <code>clk</code>, <code>we</code>, <code>addr</code>, <code>wdata</code>, and <code>rdata</code> over time.</p>
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