Hierarchical topology with crossbar

[arthurchang09]

Is it possible to generate a hierarchical SoC with a 2D mesh as the base topology and a crossbar as the child topology? What materials or documents can help me achieve this goal? The topology is briefly shown in the following figure. Thank you.

Core 0        Core 1       Core 2
   ||           ||           ||
------------------------------------
|           Crossbar               |
------------------------------------
                ||
              node 0  ================   node 1
                ||                        ||
              node 2  ================   node 3
                ||
-----------------------------------
|           Crossbar               |
-----------------------------------
    ||          ||           ||
Core 3        Core 4       Core 5

[jerryz123]

A Node internally is a crossbar. So your topology is really like this:

Core 0        Core 1       Core 2
   ||           ||           ||
   =========  node 4  =========
                ||
              node 0  ================   node 1
                ||                        ||
              node 2  ================   node 3
                ||
   =========  node 5  =========
    ||          ||           ||
Core 3        Core 4       Core 5

So this is like a 2X2 2D mesh as the base topology, with the TerminalRouters (nodes 4/5) implementing the crossbars to aggregate the core inputs.

[arthurchang09]

Does this mean that I simply connect three cores directly to one node, as the following Config shows?

class Custom2x2MeshConfig extends Config(
  new constellation.soc.WithCbusNoC(constellation.protocol.SimpleTLNoCParams(
    constellation.protocol.DiplomaticNetworkNodeMapping(
      inNodeMapping = ListMap(
        "serial_tl" -> 0),
      outNodeMapping = ListMap(
        "error" -> 1, "ctrls[0]" -> 2, "pbus" -> 3, "plic" -> 4,
        "clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "clock" -> 8)),
    NoCParams(
      topology = TerminalRouter(BidirectionalLine(9)),
      channelParamGen = (a, b) => UserChannelParams(Seq.fill(5) { UserVirtualChannelParams(4) }),
      routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalLineRouting()), 5, 1))
  )) ++
  new constellation.soc.WithMbusNoC(constellation.protocol.SimpleTLNoCParams(
    constellation.protocol.DiplomaticNetworkNodeMapping(
      inNodeMapping = ListMap(
        "L2 InclusiveCache[0]" -> 1, "L2 InclusiveCache[1]" -> 2,
        "L2 InclusiveCache[2]" -> 5, "L2 InclusiveCache[3]" -> 6),
      outNodeMapping = ListMap(
        "system[0]" -> 0, "system[1]" -> 3,  "system[2]" -> 4 , "system[3]" -> 7,
        "ram[0]" -> 0)),
    NoCParams(
      topology        = TerminalRouter(BidirectionalTorus1D(8)),
      channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
      routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalTorus1DShortestRouting()), 5, 2))
  )) ++
  new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams(
    constellation.protocol.DiplomaticNetworkNodeMapping(
      inNodeMapping = ListMap(
        "Core 0" -> 0, "Core 1" -> 0,  "Core 2" -> 0 , "Core 3" -> 2,
        "Core 4" -> 2, "Core 5" -> 2,
        "serial_tl" -> 0),
      outNodeMapping = ListMap(
        "system[0]" -> 1, "system[1]" -> 1, "system[2]" -> 3, "system[3]" -> 3,
        "pbus" -> 3)),
    NoCParams(
      topology        = TerminalRouter(Mesh2D(2, 2)),
      channelParamGen = (a, b) => UserChannelParams(Seq.fill(6) { UserVirtualChannelParams(4) }),
      routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1))
  )) ++
  new freechips.rocketchip.rocket.WithNHugeCores(6) ++
  new freechips.rocketchip.subsystem.WithNBanks(4) ++
  new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
  new chipyard.config.AbstractConfig
)