This project follows Vyges conventions for hardware IP development. Context is provided via the vyges.vycontext extension.
- VS Code: Install from marketplace:
code --install-extension vyges.vycontext - Cursor: Install from marketplace or use bundled extension
- Context Source: MCP server at
agent.services.vyges.com - Status Check:
Ctrl+Shift+P→ "Vyges VyContext: Show Status"
- Language: SystemVerilog for RTL
- Naming: snake_case for modules/files, UPPER_SNAKE_CASE for parameters
- Structure: rtl/, tb/, flow/, test/, docs/ directories
- Interfaces: Standardized signals (clock_i, reset_n_i, etc.)
- CLI: Use vyges commands for project management
vyges init --interactive- Setup new projectvyges expand --analog- Add analog componentsvyges validate- Check compliancevyges generate rtl- Generate from metadata
Use these prompts with Copilot/Cursor:
- "Create SystemVerilog module following Vyges conventions"
- "Generate testbench with clock/reset following Vyges patterns"
- "Create README.md following Vyges documentation structure"
- "Validate this code for Vyges Catalog readiness"
The vyges.vycontext extension automatically provides:
- RTL design patterns and coding standards
- Synthesis and testbench guidance
- Tool-specific flags and configurations
- DFT/JTAG implementation patterns
- Pin/pad consistency validation
- Metadata generation workflows