Skip to content

Commit 0d04e03

Browse files
plappermaulrobimarko
plappermaul
authored and
robimarko
committed
realtek: eth: drop pcs handling
The ethernet driver configures the SoC internal network card on its own. There are no special serdes or other layers in between. So there is no need for pcs handling in the driver. Drop that. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: openwrt#22347 Signed-off-by: Robert Marko <robimarko@gmail.com>
1 parent 59f1fe1 commit 0d04e03

2 files changed

Lines changed: 0 additions & 266 deletions

File tree

‎target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c‎

Lines changed: 0 additions & 106 deletions
Original file line numberDiff line numberDiff line change
@@ -150,7 +150,6 @@ struct rteth_ctrl {
150150
struct rtl838x_rx_q rx_qs[RTETH_RX_RINGS];
151151
struct phylink *phylink;
152152
struct phylink_config phylink_config;
153-
struct phylink_pcs pcs;
154153
const struct rteth_config *r;
155154
u32 lastEvent;
156155
/* receive handling */
@@ -1078,74 +1077,6 @@ static void rteth_mac_config(struct phylink_config *config,
10781077
pr_info("In %s, mode %x\n", __func__, mode);
10791078
}
10801079

1081-
static void rteth_pcs_an_restart(struct phylink_pcs *pcs)
1082-
{
1083-
struct rteth_ctrl *ctrl = container_of(pcs, struct rteth_ctrl, pcs);
1084-
1085-
/* This works only on RTL838x chips */
1086-
if (ctrl->r->family_id != RTL8380_FAMILY_ID)
1087-
return;
1088-
1089-
pr_debug("In %s\n", __func__);
1090-
/* Restart by disabling and re-enabling link */
1091-
sw_w32(0x6192D, ctrl->r->mac_force_mode_ctrl);
1092-
mdelay(20);
1093-
sw_w32(0x6192F, ctrl->r->mac_force_mode_ctrl);
1094-
}
1095-
1096-
static void rteth_pcs_get_state(struct phylink_pcs *pcs,
1097-
struct phylink_link_state *state)
1098-
{
1099-
u32 speed;
1100-
struct rteth_ctrl *ctrl = container_of(pcs, struct rteth_ctrl, pcs);
1101-
int port = ctrl->r->cpu_port;
1102-
1103-
pr_info("In %s\n", __func__);
1104-
1105-
state->link = ctrl->r->get_mac_link_sts(port) ? 1 : 0;
1106-
state->duplex = ctrl->r->get_mac_link_dup_sts(port) ? 1 : 0;
1107-
1108-
pr_info("%s link status is %d\n", __func__, state->link);
1109-
speed = ctrl->r->get_mac_link_spd_sts(port);
1110-
switch (speed) {
1111-
case 0:
1112-
state->speed = SPEED_10;
1113-
break;
1114-
case 1:
1115-
state->speed = SPEED_100;
1116-
break;
1117-
case 2:
1118-
state->speed = SPEED_1000;
1119-
break;
1120-
case 5:
1121-
state->speed = SPEED_2500;
1122-
break;
1123-
case 6:
1124-
state->speed = SPEED_5000;
1125-
break;
1126-
case 4:
1127-
state->speed = SPEED_10000;
1128-
break;
1129-
default:
1130-
state->speed = SPEED_UNKNOWN;
1131-
break;
1132-
}
1133-
1134-
state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
1135-
if (ctrl->r->get_mac_rx_pause_sts(port))
1136-
state->pause |= MLO_PAUSE_RX;
1137-
if (ctrl->r->get_mac_tx_pause_sts(port))
1138-
state->pause |= MLO_PAUSE_TX;
1139-
}
1140-
1141-
static int rteth_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
1142-
phy_interface_t interface,
1143-
const unsigned long *advertising,
1144-
bool permit_pause_to_mac)
1145-
{
1146-
return 0;
1147-
}
1148-
11491080
static void rteth_mac_link_down(struct phylink_config *config,
11501081
unsigned int mode,
11511082
phy_interface_t interface)
@@ -1318,15 +1249,6 @@ static int rteth_93xx_set_features(struct net_device *dev, netdev_features_t fea
13181249
return 0;
13191250
}
13201251

1321-
static struct phylink_pcs *rteth_mac_select_pcs(struct phylink_config *config,
1322-
phy_interface_t interface)
1323-
{
1324-
struct net_device *dev = to_net_dev(config->dev);
1325-
struct rteth_ctrl *ctrl = netdev_priv(dev);
1326-
1327-
return &ctrl->pcs;
1328-
}
1329-
13301252
static int rteth_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data)
13311253
{
13321254
struct dsa_switch *ds;
@@ -1376,11 +1298,6 @@ static const struct rteth_config rteth_838x_cfg = {
13761298
.dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,
13771299
.dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,
13781300
.rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
1379-
.get_mac_link_sts = rtl838x_get_mac_link_sts,
1380-
.get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,
1381-
.get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,
1382-
.get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,
1383-
.get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,
13841301
.mac_reg = { RTETH_838X_MAC_ADDR_CTRL,
13851302
RTETH_838X_MAC_ADDR_CTRL_ALE,
13861303
RTETH_838X_MAC_ADDR_CTRL_MAC },
@@ -1425,11 +1342,6 @@ static const struct rteth_config rteth_839x_cfg = {
14251342
.dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,
14261343
.dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,
14271344
.rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
1428-
.get_mac_link_sts = rtl839x_get_mac_link_sts,
1429-
.get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,
1430-
.get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,
1431-
.get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,
1432-
.get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,
14331345
.mac_reg = { RTETH_839X_MAC_ADDR_CTRL },
14341346
.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
14351347
.update_counter = rteth_83xx_update_counter,
@@ -1473,11 +1385,6 @@ static const struct rteth_config rteth_930x_cfg = {
14731385
.dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,
14741386
.dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr,
14751387
.rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,
1476-
.get_mac_link_sts = rtl930x_get_mac_link_sts,
1477-
.get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts,
1478-
.get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,
1479-
.get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,
1480-
.get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,
14811388
.mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL },
14821389
.l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,
14831390
.update_counter = rteth_93xx_update_counter,
@@ -1521,11 +1428,6 @@ static const struct rteth_config rteth_931x_cfg = {
15211428
.dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,
15221429
.dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr,
15231430
.rst_glb_ctrl = RTL931X_RST_GLB_CTRL,
1524-
.get_mac_link_sts = rtldsa_931x_get_mac_link_sts,
1525-
.get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts,
1526-
.get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,
1527-
.get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,
1528-
.get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,
15291431
.mac_reg = { RTETH_930X_MAC_L2_ADDR_CTRL },
15301432
.l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,
15311433
.update_counter = rteth_93xx_update_counter,
@@ -1536,14 +1438,7 @@ static const struct rteth_config rteth_931x_cfg = {
15361438
.netdev_ops = &rteth_931x_netdev_ops,
15371439
};
15381440

1539-
static const struct phylink_pcs_ops rteth_pcs_ops = {
1540-
.pcs_get_state = rteth_pcs_get_state,
1541-
.pcs_an_restart = rteth_pcs_an_restart,
1542-
.pcs_config = rteth_pcs_config,
1543-
};
1544-
15451441
static const struct phylink_mac_ops rteth_mac_ops = {
1546-
.mac_select_pcs = rteth_mac_select_pcs,
15471442
.mac_config = rteth_mac_config,
15481443
.mac_link_down = rteth_mac_link_down,
15491444
.mac_link_up = rteth_mac_link_up,
@@ -1678,7 +1573,6 @@ static int rtl838x_eth_probe(struct platform_device *pdev)
16781573
return -EINVAL;
16791574
}
16801575

1681-
ctrl->pcs.ops = &rteth_pcs_ops;
16821576
ctrl->phylink_config.dev = &dev->dev;
16831577
ctrl->phylink_config.type = PHYLINK_NETDEV;
16841578
ctrl->phylink_config.mac_capabilities =

‎target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.h‎

Lines changed: 0 additions & 160 deletions
Original file line numberDiff line numberDiff line change
@@ -112,34 +112,6 @@
112112
#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914)
113113
#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2))
114114

115-
/* MAC-side link state handling */
116-
#define RTL838X_MAC_LINK_STS (0xa188)
117-
#define RTL839X_MAC_LINK_STS (0x0390)
118-
#define RTL930X_MAC_LINK_STS (0xCB10)
119-
#define RTL931X_MAC_LINK_STS (0x0ec0)
120-
121-
#define RTL838X_MAC_LINK_SPD_STS (0xa190)
122-
#define RTL839X_MAC_LINK_SPD_STS (0x03a0)
123-
#define RTL930X_MAC_LINK_SPD_STS (0xCB18)
124-
#define RTL931X_MAC_LINK_SPD_STS (0x0ed0)
125-
126-
#define RTL838X_MAC_LINK_DUP_STS (0xa19c)
127-
#define RTL839X_MAC_LINK_DUP_STS (0x03b0)
128-
#define RTL930X_MAC_LINK_DUP_STS (0xCB28)
129-
#define RTL931X_MAC_LINK_DUP_STS (0x0ef0)
130-
131-
/* TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR??? */
132-
133-
#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0)
134-
#define RTL839X_MAC_TX_PAUSE_STS (0x03b8)
135-
#define RTL930X_MAC_TX_PAUSE_STS (0xCB2C)
136-
#define RTL931X_MAC_TX_PAUSE_STS (0x0ef8)
137-
138-
#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4)
139-
#define RTL839X_MAC_RX_PAUSE_STS (0xCB30)
140-
#define RTL930X_MAC_RX_PAUSE_STS (0xC2F8)
141-
#define RTL931X_MAC_RX_PAUSE_STS (0x0f00)
142-
143115
#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04)
144116
#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08)
145117

@@ -261,133 +233,6 @@ inline int rtl931x_dma_if_rx_ring_cntr(int i)
261233
return RTL931X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);
262234
}
263235

264-
inline u32 rtl838x_get_mac_link_sts(int port)
265-
{
266-
return (sw_r32(RTL838X_MAC_LINK_STS) & BIT(port));
267-
}
268-
269-
inline u32 rtl839x_get_mac_link_sts(int p)
270-
{
271-
return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));
272-
}
273-
274-
inline u32 rtl930x_get_mac_link_sts(int port)
275-
{
276-
u32 link = sw_r32(RTL930X_MAC_LINK_STS);
277-
278-
link = sw_r32(RTL930X_MAC_LINK_STS);
279-
pr_info("%s link state is %08x\n", __func__, link);
280-
return link & BIT(port);
281-
}
282-
283-
inline u32 rtldsa_931x_get_mac_link_sts(int port)
284-
{
285-
unsigned int reg = RTL931X_MAC_LINK_STS + (port / 32) * 4;
286-
u32 mask = BIT(port % 32);
287-
u32 link;
288-
289-
link = sw_r32(reg);
290-
link = sw_r32(reg);
291-
292-
return (link & mask);
293-
}
294-
295-
inline u32 rtl838x_get_mac_link_dup_sts(int port)
296-
{
297-
return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & BIT(port));
298-
}
299-
300-
inline u32 rtl839x_get_mac_link_dup_sts(int p)
301-
{
302-
return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));
303-
}
304-
305-
inline u32 rtl930x_get_mac_link_dup_sts(int port)
306-
{
307-
return (sw_r32(RTL930X_MAC_LINK_DUP_STS) & BIT(port));
308-
}
309-
310-
inline u32 rtl931x_get_mac_link_dup_sts(int p)
311-
{
312-
return (sw_r32(RTL931X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));
313-
}
314-
315-
inline u32 rtl838x_get_mac_link_spd_sts(int port)
316-
{
317-
int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
318-
u32 speed = sw_r32(r);
319-
320-
speed >>= (port % 16) << 1;
321-
return (speed & 0x3);
322-
}
323-
324-
inline u32 rtl839x_get_mac_link_spd_sts(int port)
325-
{
326-
int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
327-
u32 speed = sw_r32(r);
328-
329-
speed >>= (port % 16) << 1;
330-
return (speed & 0x3);
331-
}
332-
333-
inline u32 rtl930x_get_mac_link_spd_sts(int port)
334-
{
335-
int r = RTL930X_MAC_LINK_SPD_STS + ((port >> 3) << 2);
336-
u32 speed = sw_r32(r);
337-
338-
speed >>= (port % 8) << 2;
339-
return (speed & 0xf);
340-
}
341-
342-
inline u32 rtl931x_get_mac_link_spd_sts(int port)
343-
{
344-
int r = RTL931X_MAC_LINK_SPD_STS + ((port >> 3) << 2);
345-
u32 speed = sw_r32(r);
346-
347-
speed >>= (port % 8) << 2;
348-
return (speed & 0xf);
349-
}
350-
351-
inline u32 rtl838x_get_mac_rx_pause_sts(int port)
352-
{
353-
return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port));
354-
}
355-
356-
inline u32 rtl839x_get_mac_rx_pause_sts(int p)
357-
{
358-
return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
359-
}
360-
361-
inline u32 rtl930x_get_mac_rx_pause_sts(int port)
362-
{
363-
return (sw_r32(RTL930X_MAC_RX_PAUSE_STS) & (1 << port));
364-
}
365-
366-
inline u32 rtl931x_get_mac_rx_pause_sts(int p)
367-
{
368-
return (sw_r32(RTL931X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
369-
}
370-
371-
inline u32 rtl838x_get_mac_tx_pause_sts(int port)
372-
{
373-
return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port));
374-
}
375-
376-
inline u32 rtl839x_get_mac_tx_pause_sts(int p)
377-
{
378-
return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
379-
}
380-
381-
inline u32 rtl930x_get_mac_tx_pause_sts(int port)
382-
{
383-
return (sw_r32(RTL930X_MAC_TX_PAUSE_STS) & (1 << port));
384-
}
385-
386-
inline u32 rtl931x_get_mac_tx_pause_sts(int p)
387-
{
388-
return (sw_r32(RTL931X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
389-
}
390-
391236
struct p_hdr;
392237
struct dsa_tag;
393238
struct rteth_ctrl;
@@ -414,11 +259,6 @@ struct rteth_config {
414259
int (*dma_if_rx_ring_size)(int ring);
415260
int (*dma_if_rx_ring_cntr)(int ring);
416261
int rst_glb_ctrl;
417-
u32 (*get_mac_link_sts)(int port);
418-
u32 (*get_mac_link_dup_sts)(int port);
419-
u32 (*get_mac_link_spd_sts)(int port);
420-
u32 (*get_mac_rx_pause_sts)(int port);
421-
u32 (*get_mac_tx_pause_sts)(int port);
422262
u32 mac_reg[RTETH_MAX_MAC_REGS];
423263
int l2_tbl_flush_ctrl;
424264
void (*create_tx_header)(struct rteth_packet *h, unsigned int dest_port, int prio);

0 commit comments

Comments
 (0)