uart-verilog

A UART transmitter and receiver written in Verilog, verified with a Python cocotb testbench under Icarus Verilog.

The top level loops the transmitter output back into the receiver input. A byte sent on data_in returns unchanged on data_out.

Frame format

8 data bits, no parity, 1 stop bit (8N1). The clock is 100 MHz. The baud rate is 115200.

Layout

Path	Role
rtl/uart_tx.v	Transmitter. Parallel byte in, serial bit out.
rtl/uart_rx.v	Receiver. Serial bit in, parallel byte out.
rtl/uart_top.v	Top level. Loops TX into RX.
tb/test_uart.py	Cocotb testbench.
tb/Makefile	Simulation driver.
tools/render_uart_html.py	Converts the captured trace to standalone HTML.
docs/index.html	Interactive visual explanation of the simulated frames.

Requirements

• Icarus Verilog 11 or newer
• Python 3.8 or newer

Build and simulate

1. Create the virtual environment.

   python3 -m venv .venv
   source .venv/bin/activate
   pip install -r requirements.txt
   

2. Run the simulation.

   make sim
   

The test sends five bytes through the loopback and checks each returns unchanged.

View the UART frame

Generate the trace and the standalone HTML page:

make visual

Open docs/index.html in a browser. Select a byte to see:

• The parallel input byte.
• The start, data, and stop bits.
• The actual simulated wire waveform.
• The byte that the receiver rebuilt.

The page works offline. It uses data that the cocotb test sampled from the simulated tx wire.