I build hardware projects that go beyond “it simulates.” My focus is clean RTL, strong verification, real waveforms, coverage numbers, and open-source silicon flows.
Currently exploring:
SystemVerilog | UVM | RISC-V | FPGA | SKY130 | OpenROAD | ASIC Flow
Tiny bugs fear my waveform zoom button.
Complete AES-128 RTL + UVM environment with constrained-random stimulus, scoreboard, functional coverage, and EPWave debug.
561 / 561 transactions passed
99.82% functional coverage
0 UVM errors | 0 UVM fatals
A clean SystemVerilog + UVM project showing arbitration, assertions, scoreboard checking, and functional coverage.
Parameterized RTL
One-hot grant
Rotating priority pointer
Directed + constrained-random verification
An 8-bit microcontroller-style SoC pushed through an open-source RTL-to-GDS flow.
CPU + RAM + UART + Timer + Bus
Yosys + OpenROAD + Magic + Netgen + KLayout
Exploring processor architecture through RV32I, SERV and CVA6
Datapath
ALU
Control logic
Register file
Compact RISC-V cores
RV32I Processor · SERV · CVA6
Languages : Verilog, SystemVerilog, Python, C
Verification : UVM, SVA, Scoreboards, Functional Coverage
ASIC Tools : Yosys, OpenROAD, LibreLane, Magic, Netgen, KLayout
PDK/Flow : SKY130, Open-source RTL-to-GDS
FPGA/Debug : Vivado, EPWave, GTKWave, PYNQ-Z2
Architecture : RISC-V, SoC, UART, FSMs, Datapaths
I’m building a hardware portfolio around:
- Digital IC design
- UVM verification
- Processor and SoC design
- Open-source ASIC implementation
- FPGA and waveform-driven debug
- Silicon-ready documentation
| Project | Focus |
|---|---|
| AES-128 UVM Verification | Cryptographic accelerator verification |
| Round Robin Arbiter | RTL + UVM fundamentals |
| TinySoC | RTL-to-GDS ASIC flow |
| RV32I Processor | Processor design |
| UART | RTL peripheral design |
| Analog Circuit Design | Custom IC exploration |
GitHub : 124107157-KV
LinkedIn : keerthi-vasan-p
Focus : Digital IC Design
RTL Design
UVM Verification
RISC-V
Computer Architecture
Open-Source ASIC Flows
Building small blocks properly today, so bigger chips behave tomorrow.